CCSModuleSW30Web.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001e8 08008000 08008000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000e468 080081e8 080081e8 000011e8 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000c04 08016650 08016650 0000f650 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08017254 08017254 00011240 2**0 CONTENTS 4 .ARM 00000008 08017254 08017254 00010254 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 0801725c 0801725c 00011240 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0801725c 0801725c 0001025c 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08017260 08017260 00010260 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000240 20000000 08017264 00011000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00001158 20000240 080174a4 00011240 2**3 ALLOC 10 ._user_heap_stack 00000600 20001398 080174a4 00011398 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 00011240 2**0 CONTENTS, READONLY 12 .debug_info 0001cd62 00000000 00000000 00011269 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 000056d7 00000000 00000000 0002dfcb 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_loclists 00000f22 00000000 00000000 000336a2 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_aranges 000016f0 00000000 00000000 000345c8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_rnglists 000011ff 00000000 00000000 00035cb8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_macro 000264f0 00000000 00000000 00036eb7 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_line 0002128e 00000000 00000000 0005d3a7 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_str 000c9825 00000000 00000000 0007e635 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .comment 00000043 00000000 00000000 00147e5a 2**0 CONTENTS, READONLY 21 .debug_frame 00006d18 00000000 00000000 00147ea0 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 22 .debug_line_str 00000073 00000000 00000000 0014ebb8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080081e8 <__do_global_dtors_aux>: 80081e8: b510 push {r4, lr} 80081ea: 4c05 ldr r4, [pc, #20] @ (8008200 <__do_global_dtors_aux+0x18>) 80081ec: 7823 ldrb r3, [r4, #0] 80081ee: b933 cbnz r3, 80081fe <__do_global_dtors_aux+0x16> 80081f0: 4b04 ldr r3, [pc, #16] @ (8008204 <__do_global_dtors_aux+0x1c>) 80081f2: b113 cbz r3, 80081fa <__do_global_dtors_aux+0x12> 80081f4: 4804 ldr r0, [pc, #16] @ (8008208 <__do_global_dtors_aux+0x20>) 80081f6: f3af 8000 nop.w 80081fa: 2301 movs r3, #1 80081fc: 7023 strb r3, [r4, #0] 80081fe: bd10 pop {r4, pc} 8008200: 20000240 .word 0x20000240 8008204: 00000000 .word 0x00000000 8008208: 08016638 .word 0x08016638 0800820c : 800820c: b508 push {r3, lr} 800820e: 4b03 ldr r3, [pc, #12] @ (800821c ) 8008210: b11b cbz r3, 800821a 8008212: 4903 ldr r1, [pc, #12] @ (8008220 ) 8008214: 4803 ldr r0, [pc, #12] @ (8008224 ) 8008216: f3af 8000 nop.w 800821a: bd08 pop {r3, pc} 800821c: 00000000 .word 0x00000000 8008220: 20000244 .word 0x20000244 8008224: 08016638 .word 0x08016638 08008228 : 8008228: 4603 mov r3, r0 800822a: f813 2b01 ldrb.w r2, [r3], #1 800822e: 2a00 cmp r2, #0 8008230: d1fb bne.n 800822a 8008232: 1a18 subs r0, r3, r0 8008234: 3801 subs r0, #1 8008236: 4770 bx lr 08008238 <__aeabi_drsub>: 8008238: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 800823c: e002 b.n 8008244 <__adddf3> 800823e: bf00 nop 08008240 <__aeabi_dsub>: 8008240: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 08008244 <__adddf3>: 8008244: b530 push {r4, r5, lr} 8008246: ea4f 0441 mov.w r4, r1, lsl #1 800824a: ea4f 0543 mov.w r5, r3, lsl #1 800824e: ea94 0f05 teq r4, r5 8008252: bf08 it eq 8008254: ea90 0f02 teqeq r0, r2 8008258: bf1f itttt ne 800825a: ea54 0c00 orrsne.w ip, r4, r0 800825e: ea55 0c02 orrsne.w ip, r5, r2 8008262: ea7f 5c64 mvnsne.w ip, r4, asr #21 8008266: ea7f 5c65 mvnsne.w ip, r5, asr #21 800826a: f000 80e2 beq.w 8008432 <__adddf3+0x1ee> 800826e: ea4f 5454 mov.w r4, r4, lsr #21 8008272: ebd4 5555 rsbs r5, r4, r5, lsr #21 8008276: bfb8 it lt 8008278: 426d neglt r5, r5 800827a: dd0c ble.n 8008296 <__adddf3+0x52> 800827c: 442c add r4, r5 800827e: ea80 0202 eor.w r2, r0, r2 8008282: ea81 0303 eor.w r3, r1, r3 8008286: ea82 0000 eor.w r0, r2, r0 800828a: ea83 0101 eor.w r1, r3, r1 800828e: ea80 0202 eor.w r2, r0, r2 8008292: ea81 0303 eor.w r3, r1, r3 8008296: 2d36 cmp r5, #54 @ 0x36 8008298: bf88 it hi 800829a: bd30 pophi {r4, r5, pc} 800829c: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 80082a0: ea4f 3101 mov.w r1, r1, lsl #12 80082a4: f44f 1c80 mov.w ip, #1048576 @ 0x100000 80082a8: ea4c 3111 orr.w r1, ip, r1, lsr #12 80082ac: d002 beq.n 80082b4 <__adddf3+0x70> 80082ae: 4240 negs r0, r0 80082b0: eb61 0141 sbc.w r1, r1, r1, lsl #1 80082b4: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 80082b8: ea4f 3303 mov.w r3, r3, lsl #12 80082bc: ea4c 3313 orr.w r3, ip, r3, lsr #12 80082c0: d002 beq.n 80082c8 <__adddf3+0x84> 80082c2: 4252 negs r2, r2 80082c4: eb63 0343 sbc.w r3, r3, r3, lsl #1 80082c8: ea94 0f05 teq r4, r5 80082cc: f000 80a7 beq.w 800841e <__adddf3+0x1da> 80082d0: f1a4 0401 sub.w r4, r4, #1 80082d4: f1d5 0e20 rsbs lr, r5, #32 80082d8: db0d blt.n 80082f6 <__adddf3+0xb2> 80082da: fa02 fc0e lsl.w ip, r2, lr 80082de: fa22 f205 lsr.w r2, r2, r5 80082e2: 1880 adds r0, r0, r2 80082e4: f141 0100 adc.w r1, r1, #0 80082e8: fa03 f20e lsl.w r2, r3, lr 80082ec: 1880 adds r0, r0, r2 80082ee: fa43 f305 asr.w r3, r3, r5 80082f2: 4159 adcs r1, r3 80082f4: e00e b.n 8008314 <__adddf3+0xd0> 80082f6: f1a5 0520 sub.w r5, r5, #32 80082fa: f10e 0e20 add.w lr, lr, #32 80082fe: 2a01 cmp r2, #1 8008300: fa03 fc0e lsl.w ip, r3, lr 8008304: bf28 it cs 8008306: f04c 0c02 orrcs.w ip, ip, #2 800830a: fa43 f305 asr.w r3, r3, r5 800830e: 18c0 adds r0, r0, r3 8008310: eb51 71e3 adcs.w r1, r1, r3, asr #31 8008314: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008318: d507 bpl.n 800832a <__adddf3+0xe6> 800831a: f04f 0e00 mov.w lr, #0 800831e: f1dc 0c00 rsbs ip, ip, #0 8008322: eb7e 0000 sbcs.w r0, lr, r0 8008326: eb6e 0101 sbc.w r1, lr, r1 800832a: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 800832e: d31b bcc.n 8008368 <__adddf3+0x124> 8008330: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 8008334: d30c bcc.n 8008350 <__adddf3+0x10c> 8008336: 0849 lsrs r1, r1, #1 8008338: ea5f 0030 movs.w r0, r0, rrx 800833c: ea4f 0c3c mov.w ip, ip, rrx 8008340: f104 0401 add.w r4, r4, #1 8008344: ea4f 5244 mov.w r2, r4, lsl #21 8008348: f512 0f80 cmn.w r2, #4194304 @ 0x400000 800834c: f080 809a bcs.w 8008484 <__adddf3+0x240> 8008350: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008354: bf08 it eq 8008356: ea5f 0c50 movseq.w ip, r0, lsr #1 800835a: f150 0000 adcs.w r0, r0, #0 800835e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008362: ea41 0105 orr.w r1, r1, r5 8008366: bd30 pop {r4, r5, pc} 8008368: ea5f 0c4c movs.w ip, ip, lsl #1 800836c: 4140 adcs r0, r0 800836e: eb41 0101 adc.w r1, r1, r1 8008372: 3c01 subs r4, #1 8008374: bf28 it cs 8008376: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 800837a: d2e9 bcs.n 8008350 <__adddf3+0x10c> 800837c: f091 0f00 teq r1, #0 8008380: bf04 itt eq 8008382: 4601 moveq r1, r0 8008384: 2000 moveq r0, #0 8008386: fab1 f381 clz r3, r1 800838a: bf08 it eq 800838c: 3320 addeq r3, #32 800838e: f1a3 030b sub.w r3, r3, #11 8008392: f1b3 0220 subs.w r2, r3, #32 8008396: da0c bge.n 80083b2 <__adddf3+0x16e> 8008398: 320c adds r2, #12 800839a: dd08 ble.n 80083ae <__adddf3+0x16a> 800839c: f102 0c14 add.w ip, r2, #20 80083a0: f1c2 020c rsb r2, r2, #12 80083a4: fa01 f00c lsl.w r0, r1, ip 80083a8: fa21 f102 lsr.w r1, r1, r2 80083ac: e00c b.n 80083c8 <__adddf3+0x184> 80083ae: f102 0214 add.w r2, r2, #20 80083b2: bfd8 it le 80083b4: f1c2 0c20 rsble ip, r2, #32 80083b8: fa01 f102 lsl.w r1, r1, r2 80083bc: fa20 fc0c lsr.w ip, r0, ip 80083c0: bfdc itt le 80083c2: ea41 010c orrle.w r1, r1, ip 80083c6: 4090 lslle r0, r2 80083c8: 1ae4 subs r4, r4, r3 80083ca: bfa2 ittt ge 80083cc: eb01 5104 addge.w r1, r1, r4, lsl #20 80083d0: 4329 orrge r1, r5 80083d2: bd30 popge {r4, r5, pc} 80083d4: ea6f 0404 mvn.w r4, r4 80083d8: 3c1f subs r4, #31 80083da: da1c bge.n 8008416 <__adddf3+0x1d2> 80083dc: 340c adds r4, #12 80083de: dc0e bgt.n 80083fe <__adddf3+0x1ba> 80083e0: f104 0414 add.w r4, r4, #20 80083e4: f1c4 0220 rsb r2, r4, #32 80083e8: fa20 f004 lsr.w r0, r0, r4 80083ec: fa01 f302 lsl.w r3, r1, r2 80083f0: ea40 0003 orr.w r0, r0, r3 80083f4: fa21 f304 lsr.w r3, r1, r4 80083f8: ea45 0103 orr.w r1, r5, r3 80083fc: bd30 pop {r4, r5, pc} 80083fe: f1c4 040c rsb r4, r4, #12 8008402: f1c4 0220 rsb r2, r4, #32 8008406: fa20 f002 lsr.w r0, r0, r2 800840a: fa01 f304 lsl.w r3, r1, r4 800840e: ea40 0003 orr.w r0, r0, r3 8008412: 4629 mov r1, r5 8008414: bd30 pop {r4, r5, pc} 8008416: fa21 f004 lsr.w r0, r1, r4 800841a: 4629 mov r1, r5 800841c: bd30 pop {r4, r5, pc} 800841e: f094 0f00 teq r4, #0 8008422: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 8008426: bf06 itte eq 8008428: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 800842c: 3401 addeq r4, #1 800842e: 3d01 subne r5, #1 8008430: e74e b.n 80082d0 <__adddf3+0x8c> 8008432: ea7f 5c64 mvns.w ip, r4, asr #21 8008436: bf18 it ne 8008438: ea7f 5c65 mvnsne.w ip, r5, asr #21 800843c: d029 beq.n 8008492 <__adddf3+0x24e> 800843e: ea94 0f05 teq r4, r5 8008442: bf08 it eq 8008444: ea90 0f02 teqeq r0, r2 8008448: d005 beq.n 8008456 <__adddf3+0x212> 800844a: ea54 0c00 orrs.w ip, r4, r0 800844e: bf04 itt eq 8008450: 4619 moveq r1, r3 8008452: 4610 moveq r0, r2 8008454: bd30 pop {r4, r5, pc} 8008456: ea91 0f03 teq r1, r3 800845a: bf1e ittt ne 800845c: 2100 movne r1, #0 800845e: 2000 movne r0, #0 8008460: bd30 popne {r4, r5, pc} 8008462: ea5f 5c54 movs.w ip, r4, lsr #21 8008466: d105 bne.n 8008474 <__adddf3+0x230> 8008468: 0040 lsls r0, r0, #1 800846a: 4149 adcs r1, r1 800846c: bf28 it cs 800846e: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 8008472: bd30 pop {r4, r5, pc} 8008474: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 8008478: bf3c itt cc 800847a: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 800847e: bd30 popcc {r4, r5, pc} 8008480: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008484: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 8008488: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 800848c: f04f 0000 mov.w r0, #0 8008490: bd30 pop {r4, r5, pc} 8008492: ea7f 5c64 mvns.w ip, r4, asr #21 8008496: bf1a itte ne 8008498: 4619 movne r1, r3 800849a: 4610 movne r0, r2 800849c: ea7f 5c65 mvnseq.w ip, r5, asr #21 80084a0: bf1c itt ne 80084a2: 460b movne r3, r1 80084a4: 4602 movne r2, r0 80084a6: ea50 3401 orrs.w r4, r0, r1, lsl #12 80084aa: bf06 itte eq 80084ac: ea52 3503 orrseq.w r5, r2, r3, lsl #12 80084b0: ea91 0f03 teqeq r1, r3 80084b4: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 80084b8: bd30 pop {r4, r5, pc} 80084ba: bf00 nop 080084bc <__aeabi_ui2d>: 80084bc: f090 0f00 teq r0, #0 80084c0: bf04 itt eq 80084c2: 2100 moveq r1, #0 80084c4: 4770 bxeq lr 80084c6: b530 push {r4, r5, lr} 80084c8: f44f 6480 mov.w r4, #1024 @ 0x400 80084cc: f104 0432 add.w r4, r4, #50 @ 0x32 80084d0: f04f 0500 mov.w r5, #0 80084d4: f04f 0100 mov.w r1, #0 80084d8: e750 b.n 800837c <__adddf3+0x138> 80084da: bf00 nop 080084dc <__aeabi_i2d>: 80084dc: f090 0f00 teq r0, #0 80084e0: bf04 itt eq 80084e2: 2100 moveq r1, #0 80084e4: 4770 bxeq lr 80084e6: b530 push {r4, r5, lr} 80084e8: f44f 6480 mov.w r4, #1024 @ 0x400 80084ec: f104 0432 add.w r4, r4, #50 @ 0x32 80084f0: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 80084f4: bf48 it mi 80084f6: 4240 negmi r0, r0 80084f8: f04f 0100 mov.w r1, #0 80084fc: e73e b.n 800837c <__adddf3+0x138> 80084fe: bf00 nop 08008500 <__aeabi_f2d>: 8008500: 0042 lsls r2, r0, #1 8008502: ea4f 01e2 mov.w r1, r2, asr #3 8008506: ea4f 0131 mov.w r1, r1, rrx 800850a: ea4f 7002 mov.w r0, r2, lsl #28 800850e: bf1f itttt ne 8008510: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 8008514: f093 4f7f teqne r3, #4278190080 @ 0xff000000 8008518: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 800851c: 4770 bxne lr 800851e: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 8008522: bf08 it eq 8008524: 4770 bxeq lr 8008526: f093 4f7f teq r3, #4278190080 @ 0xff000000 800852a: bf04 itt eq 800852c: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 8008530: 4770 bxeq lr 8008532: b530 push {r4, r5, lr} 8008534: f44f 7460 mov.w r4, #896 @ 0x380 8008538: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 800853c: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 8008540: e71c b.n 800837c <__adddf3+0x138> 8008542: bf00 nop 08008544 <__aeabi_ul2d>: 8008544: ea50 0201 orrs.w r2, r0, r1 8008548: bf08 it eq 800854a: 4770 bxeq lr 800854c: b530 push {r4, r5, lr} 800854e: f04f 0500 mov.w r5, #0 8008552: e00a b.n 800856a <__aeabi_l2d+0x16> 08008554 <__aeabi_l2d>: 8008554: ea50 0201 orrs.w r2, r0, r1 8008558: bf08 it eq 800855a: 4770 bxeq lr 800855c: b530 push {r4, r5, lr} 800855e: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 8008562: d502 bpl.n 800856a <__aeabi_l2d+0x16> 8008564: 4240 negs r0, r0 8008566: eb61 0141 sbc.w r1, r1, r1, lsl #1 800856a: f44f 6480 mov.w r4, #1024 @ 0x400 800856e: f104 0432 add.w r4, r4, #50 @ 0x32 8008572: ea5f 5c91 movs.w ip, r1, lsr #22 8008576: f43f aed8 beq.w 800832a <__adddf3+0xe6> 800857a: f04f 0203 mov.w r2, #3 800857e: ea5f 0cdc movs.w ip, ip, lsr #3 8008582: bf18 it ne 8008584: 3203 addne r2, #3 8008586: ea5f 0cdc movs.w ip, ip, lsr #3 800858a: bf18 it ne 800858c: 3203 addne r2, #3 800858e: eb02 02dc add.w r2, r2, ip, lsr #3 8008592: f1c2 0320 rsb r3, r2, #32 8008596: fa00 fc03 lsl.w ip, r0, r3 800859a: fa20 f002 lsr.w r0, r0, r2 800859e: fa01 fe03 lsl.w lr, r1, r3 80085a2: ea40 000e orr.w r0, r0, lr 80085a6: fa21 f102 lsr.w r1, r1, r2 80085aa: 4414 add r4, r2 80085ac: e6bd b.n 800832a <__adddf3+0xe6> 80085ae: bf00 nop 080085b0 <__aeabi_dmul>: 80085b0: b570 push {r4, r5, r6, lr} 80085b2: f04f 0cff mov.w ip, #255 @ 0xff 80085b6: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 80085ba: ea1c 5411 ands.w r4, ip, r1, lsr #20 80085be: bf1d ittte ne 80085c0: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80085c4: ea94 0f0c teqne r4, ip 80085c8: ea95 0f0c teqne r5, ip 80085cc: f000 f8de bleq 800878c <__aeabi_dmul+0x1dc> 80085d0: 442c add r4, r5 80085d2: ea81 0603 eor.w r6, r1, r3 80085d6: ea21 514c bic.w r1, r1, ip, lsl #21 80085da: ea23 534c bic.w r3, r3, ip, lsl #21 80085de: ea50 3501 orrs.w r5, r0, r1, lsl #12 80085e2: bf18 it ne 80085e4: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80085e8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 80085ec: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80085f0: d038 beq.n 8008664 <__aeabi_dmul+0xb4> 80085f2: fba0 ce02 umull ip, lr, r0, r2 80085f6: f04f 0500 mov.w r5, #0 80085fa: fbe1 e502 umlal lr, r5, r1, r2 80085fe: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 8008602: fbe0 e503 umlal lr, r5, r0, r3 8008606: f04f 0600 mov.w r6, #0 800860a: fbe1 5603 umlal r5, r6, r1, r3 800860e: f09c 0f00 teq ip, #0 8008612: bf18 it ne 8008614: f04e 0e01 orrne.w lr, lr, #1 8008618: f1a4 04ff sub.w r4, r4, #255 @ 0xff 800861c: f5b6 7f00 cmp.w r6, #512 @ 0x200 8008620: f564 7440 sbc.w r4, r4, #768 @ 0x300 8008624: d204 bcs.n 8008630 <__aeabi_dmul+0x80> 8008626: ea5f 0e4e movs.w lr, lr, lsl #1 800862a: 416d adcs r5, r5 800862c: eb46 0606 adc.w r6, r6, r6 8008630: ea42 21c6 orr.w r1, r2, r6, lsl #11 8008634: ea41 5155 orr.w r1, r1, r5, lsr #21 8008638: ea4f 20c5 mov.w r0, r5, lsl #11 800863c: ea40 505e orr.w r0, r0, lr, lsr #21 8008640: ea4f 2ece mov.w lr, lr, lsl #11 8008644: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008648: bf88 it hi 800864a: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800864e: d81e bhi.n 800868e <__aeabi_dmul+0xde> 8008650: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 8008654: bf08 it eq 8008656: ea5f 0e50 movseq.w lr, r0, lsr #1 800865a: f150 0000 adcs.w r0, r0, #0 800865e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008662: bd70 pop {r4, r5, r6, pc} 8008664: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 8008668: ea46 0101 orr.w r1, r6, r1 800866c: ea40 0002 orr.w r0, r0, r2 8008670: ea81 0103 eor.w r1, r1, r3 8008674: ebb4 045c subs.w r4, r4, ip, lsr #1 8008678: bfc2 ittt gt 800867a: ebd4 050c rsbsgt r5, r4, ip 800867e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8008682: bd70 popgt {r4, r5, r6, pc} 8008684: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008688: f04f 0e00 mov.w lr, #0 800868c: 3c01 subs r4, #1 800868e: f300 80ab bgt.w 80087e8 <__aeabi_dmul+0x238> 8008692: f114 0f36 cmn.w r4, #54 @ 0x36 8008696: bfde ittt le 8008698: 2000 movle r0, #0 800869a: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 800869e: bd70 pople {r4, r5, r6, pc} 80086a0: f1c4 0400 rsb r4, r4, #0 80086a4: 3c20 subs r4, #32 80086a6: da35 bge.n 8008714 <__aeabi_dmul+0x164> 80086a8: 340c adds r4, #12 80086aa: dc1b bgt.n 80086e4 <__aeabi_dmul+0x134> 80086ac: f104 0414 add.w r4, r4, #20 80086b0: f1c4 0520 rsb r5, r4, #32 80086b4: fa00 f305 lsl.w r3, r0, r5 80086b8: fa20 f004 lsr.w r0, r0, r4 80086bc: fa01 f205 lsl.w r2, r1, r5 80086c0: ea40 0002 orr.w r0, r0, r2 80086c4: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 80086c8: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 80086cc: eb10 70d3 adds.w r0, r0, r3, lsr #31 80086d0: fa21 f604 lsr.w r6, r1, r4 80086d4: eb42 0106 adc.w r1, r2, r6 80086d8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80086dc: bf08 it eq 80086de: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80086e2: bd70 pop {r4, r5, r6, pc} 80086e4: f1c4 040c rsb r4, r4, #12 80086e8: f1c4 0520 rsb r5, r4, #32 80086ec: fa00 f304 lsl.w r3, r0, r4 80086f0: fa20 f005 lsr.w r0, r0, r5 80086f4: fa01 f204 lsl.w r2, r1, r4 80086f8: ea40 0002 orr.w r0, r0, r2 80086fc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008700: eb10 70d3 adds.w r0, r0, r3, lsr #31 8008704: f141 0100 adc.w r1, r1, #0 8008708: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800870c: bf08 it eq 800870e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8008712: bd70 pop {r4, r5, r6, pc} 8008714: f1c4 0520 rsb r5, r4, #32 8008718: fa00 f205 lsl.w r2, r0, r5 800871c: ea4e 0e02 orr.w lr, lr, r2 8008720: fa20 f304 lsr.w r3, r0, r4 8008724: fa01 f205 lsl.w r2, r1, r5 8008728: ea43 0302 orr.w r3, r3, r2 800872c: fa21 f004 lsr.w r0, r1, r4 8008730: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008734: fa21 f204 lsr.w r2, r1, r4 8008738: ea20 0002 bic.w r0, r0, r2 800873c: eb00 70d3 add.w r0, r0, r3, lsr #31 8008740: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8008744: bf08 it eq 8008746: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800874a: bd70 pop {r4, r5, r6, pc} 800874c: f094 0f00 teq r4, #0 8008750: d10f bne.n 8008772 <__aeabi_dmul+0x1c2> 8008752: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 8008756: 0040 lsls r0, r0, #1 8008758: eb41 0101 adc.w r1, r1, r1 800875c: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008760: bf08 it eq 8008762: 3c01 subeq r4, #1 8008764: d0f7 beq.n 8008756 <__aeabi_dmul+0x1a6> 8008766: ea41 0106 orr.w r1, r1, r6 800876a: f095 0f00 teq r5, #0 800876e: bf18 it ne 8008770: 4770 bxne lr 8008772: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 8008776: 0052 lsls r2, r2, #1 8008778: eb43 0303 adc.w r3, r3, r3 800877c: f413 1f80 tst.w r3, #1048576 @ 0x100000 8008780: bf08 it eq 8008782: 3d01 subeq r5, #1 8008784: d0f7 beq.n 8008776 <__aeabi_dmul+0x1c6> 8008786: ea43 0306 orr.w r3, r3, r6 800878a: 4770 bx lr 800878c: ea94 0f0c teq r4, ip 8008790: ea0c 5513 and.w r5, ip, r3, lsr #20 8008794: bf18 it ne 8008796: ea95 0f0c teqne r5, ip 800879a: d00c beq.n 80087b6 <__aeabi_dmul+0x206> 800879c: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087a0: bf18 it ne 80087a2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087a6: d1d1 bne.n 800874c <__aeabi_dmul+0x19c> 80087a8: ea81 0103 eor.w r1, r1, r3 80087ac: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087b0: f04f 0000 mov.w r0, #0 80087b4: bd70 pop {r4, r5, r6, pc} 80087b6: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087ba: bf06 itte eq 80087bc: 4610 moveq r0, r2 80087be: 4619 moveq r1, r3 80087c0: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087c4: d019 beq.n 80087fa <__aeabi_dmul+0x24a> 80087c6: ea94 0f0c teq r4, ip 80087ca: d102 bne.n 80087d2 <__aeabi_dmul+0x222> 80087cc: ea50 3601 orrs.w r6, r0, r1, lsl #12 80087d0: d113 bne.n 80087fa <__aeabi_dmul+0x24a> 80087d2: ea95 0f0c teq r5, ip 80087d6: d105 bne.n 80087e4 <__aeabi_dmul+0x234> 80087d8: ea52 3603 orrs.w r6, r2, r3, lsl #12 80087dc: bf1c itt ne 80087de: 4610 movne r0, r2 80087e0: 4619 movne r1, r3 80087e2: d10a bne.n 80087fa <__aeabi_dmul+0x24a> 80087e4: ea81 0103 eor.w r1, r1, r3 80087e8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087ec: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087f0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 80087f4: f04f 0000 mov.w r0, #0 80087f8: bd70 pop {r4, r5, r6, pc} 80087fa: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087fe: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 8008802: bd70 pop {r4, r5, r6, pc} 08008804 <__aeabi_ddiv>: 8008804: b570 push {r4, r5, r6, lr} 8008806: f04f 0cff mov.w ip, #255 @ 0xff 800880a: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 800880e: ea1c 5411 ands.w r4, ip, r1, lsr #20 8008812: bf1d ittte ne 8008814: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8008818: ea94 0f0c teqne r4, ip 800881c: ea95 0f0c teqne r5, ip 8008820: f000 f8a7 bleq 8008972 <__aeabi_ddiv+0x16e> 8008824: eba4 0405 sub.w r4, r4, r5 8008828: ea81 0e03 eor.w lr, r1, r3 800882c: ea52 3503 orrs.w r5, r2, r3, lsl #12 8008830: ea4f 3101 mov.w r1, r1, lsl #12 8008834: f000 8088 beq.w 8008948 <__aeabi_ddiv+0x144> 8008838: ea4f 3303 mov.w r3, r3, lsl #12 800883c: f04f 5580 mov.w r5, #268435456 @ 0x10000000 8008840: ea45 1313 orr.w r3, r5, r3, lsr #4 8008844: ea43 6312 orr.w r3, r3, r2, lsr #24 8008848: ea4f 2202 mov.w r2, r2, lsl #8 800884c: ea45 1511 orr.w r5, r5, r1, lsr #4 8008850: ea45 6510 orr.w r5, r5, r0, lsr #24 8008854: ea4f 2600 mov.w r6, r0, lsl #8 8008858: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000 800885c: 429d cmp r5, r3 800885e: bf08 it eq 8008860: 4296 cmpeq r6, r2 8008862: f144 04fd adc.w r4, r4, #253 @ 0xfd 8008866: f504 7440 add.w r4, r4, #768 @ 0x300 800886a: d202 bcs.n 8008872 <__aeabi_ddiv+0x6e> 800886c: 085b lsrs r3, r3, #1 800886e: ea4f 0232 mov.w r2, r2, rrx 8008872: 1ab6 subs r6, r6, r2 8008874: eb65 0503 sbc.w r5, r5, r3 8008878: 085b lsrs r3, r3, #1 800887a: ea4f 0232 mov.w r2, r2, rrx 800887e: f44f 1080 mov.w r0, #1048576 @ 0x100000 8008882: f44f 2c00 mov.w ip, #524288 @ 0x80000 8008886: ebb6 0e02 subs.w lr, r6, r2 800888a: eb75 0e03 sbcs.w lr, r5, r3 800888e: bf22 ittt cs 8008890: 1ab6 subcs r6, r6, r2 8008892: 4675 movcs r5, lr 8008894: ea40 000c orrcs.w r0, r0, ip 8008898: 085b lsrs r3, r3, #1 800889a: ea4f 0232 mov.w r2, r2, rrx 800889e: ebb6 0e02 subs.w lr, r6, r2 80088a2: eb75 0e03 sbcs.w lr, r5, r3 80088a6: bf22 ittt cs 80088a8: 1ab6 subcs r6, r6, r2 80088aa: 4675 movcs r5, lr 80088ac: ea40 005c orrcs.w r0, r0, ip, lsr #1 80088b0: 085b lsrs r3, r3, #1 80088b2: ea4f 0232 mov.w r2, r2, rrx 80088b6: ebb6 0e02 subs.w lr, r6, r2 80088ba: eb75 0e03 sbcs.w lr, r5, r3 80088be: bf22 ittt cs 80088c0: 1ab6 subcs r6, r6, r2 80088c2: 4675 movcs r5, lr 80088c4: ea40 009c orrcs.w r0, r0, ip, lsr #2 80088c8: 085b lsrs r3, r3, #1 80088ca: ea4f 0232 mov.w r2, r2, rrx 80088ce: ebb6 0e02 subs.w lr, r6, r2 80088d2: eb75 0e03 sbcs.w lr, r5, r3 80088d6: bf22 ittt cs 80088d8: 1ab6 subcs r6, r6, r2 80088da: 4675 movcs r5, lr 80088dc: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80088e0: ea55 0e06 orrs.w lr, r5, r6 80088e4: d018 beq.n 8008918 <__aeabi_ddiv+0x114> 80088e6: ea4f 1505 mov.w r5, r5, lsl #4 80088ea: ea45 7516 orr.w r5, r5, r6, lsr #28 80088ee: ea4f 1606 mov.w r6, r6, lsl #4 80088f2: ea4f 03c3 mov.w r3, r3, lsl #3 80088f6: ea43 7352 orr.w r3, r3, r2, lsr #29 80088fa: ea4f 02c2 mov.w r2, r2, lsl #3 80088fe: ea5f 1c1c movs.w ip, ip, lsr #4 8008902: d1c0 bne.n 8008886 <__aeabi_ddiv+0x82> 8008904: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008908: d10b bne.n 8008922 <__aeabi_ddiv+0x11e> 800890a: ea41 0100 orr.w r1, r1, r0 800890e: f04f 0000 mov.w r0, #0 8008912: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000 8008916: e7b6 b.n 8008886 <__aeabi_ddiv+0x82> 8008918: f411 1f80 tst.w r1, #1048576 @ 0x100000 800891c: bf04 itt eq 800891e: 4301 orreq r1, r0 8008920: 2000 moveq r0, #0 8008922: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008926: bf88 it hi 8008928: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800892c: f63f aeaf bhi.w 800868e <__aeabi_dmul+0xde> 8008930: ebb5 0c03 subs.w ip, r5, r3 8008934: bf04 itt eq 8008936: ebb6 0c02 subseq.w ip, r6, r2 800893a: ea5f 0c50 movseq.w ip, r0, lsr #1 800893e: f150 0000 adcs.w r0, r0, #0 8008942: eb41 5104 adc.w r1, r1, r4, lsl #20 8008946: bd70 pop {r4, r5, r6, pc} 8008948: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000 800894c: ea4e 3111 orr.w r1, lr, r1, lsr #12 8008950: eb14 045c adds.w r4, r4, ip, lsr #1 8008954: bfc2 ittt gt 8008956: ebd4 050c rsbsgt r5, r4, ip 800895a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800895e: bd70 popgt {r4, r5, r6, pc} 8008960: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008964: f04f 0e00 mov.w lr, #0 8008968: 3c01 subs r4, #1 800896a: e690 b.n 800868e <__aeabi_dmul+0xde> 800896c: ea45 0e06 orr.w lr, r5, r6 8008970: e68d b.n 800868e <__aeabi_dmul+0xde> 8008972: ea0c 5513 and.w r5, ip, r3, lsr #20 8008976: ea94 0f0c teq r4, ip 800897a: bf08 it eq 800897c: ea95 0f0c teqeq r5, ip 8008980: f43f af3b beq.w 80087fa <__aeabi_dmul+0x24a> 8008984: ea94 0f0c teq r4, ip 8008988: d10a bne.n 80089a0 <__aeabi_ddiv+0x19c> 800898a: ea50 3401 orrs.w r4, r0, r1, lsl #12 800898e: f47f af34 bne.w 80087fa <__aeabi_dmul+0x24a> 8008992: ea95 0f0c teq r5, ip 8008996: f47f af25 bne.w 80087e4 <__aeabi_dmul+0x234> 800899a: 4610 mov r0, r2 800899c: 4619 mov r1, r3 800899e: e72c b.n 80087fa <__aeabi_dmul+0x24a> 80089a0: ea95 0f0c teq r5, ip 80089a4: d106 bne.n 80089b4 <__aeabi_ddiv+0x1b0> 80089a6: ea52 3503 orrs.w r5, r2, r3, lsl #12 80089aa: f43f aefd beq.w 80087a8 <__aeabi_dmul+0x1f8> 80089ae: 4610 mov r0, r2 80089b0: 4619 mov r1, r3 80089b2: e722 b.n 80087fa <__aeabi_dmul+0x24a> 80089b4: ea50 0641 orrs.w r6, r0, r1, lsl #1 80089b8: bf18 it ne 80089ba: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80089be: f47f aec5 bne.w 800874c <__aeabi_dmul+0x19c> 80089c2: ea50 0441 orrs.w r4, r0, r1, lsl #1 80089c6: f47f af0d bne.w 80087e4 <__aeabi_dmul+0x234> 80089ca: ea52 0543 orrs.w r5, r2, r3, lsl #1 80089ce: f47f aeeb bne.w 80087a8 <__aeabi_dmul+0x1f8> 80089d2: e712 b.n 80087fa <__aeabi_dmul+0x24a> 080089d4 <__gedf2>: 80089d4: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80089d8: e006 b.n 80089e8 <__cmpdf2+0x4> 80089da: bf00 nop 080089dc <__ledf2>: 80089dc: f04f 0c01 mov.w ip, #1 80089e0: e002 b.n 80089e8 <__cmpdf2+0x4> 80089e2: bf00 nop 080089e4 <__cmpdf2>: 80089e4: f04f 0c01 mov.w ip, #1 80089e8: f84d cd04 str.w ip, [sp, #-4]! 80089ec: ea4f 0c41 mov.w ip, r1, lsl #1 80089f0: ea7f 5c6c mvns.w ip, ip, asr #21 80089f4: ea4f 0c43 mov.w ip, r3, lsl #1 80089f8: bf18 it ne 80089fa: ea7f 5c6c mvnsne.w ip, ip, asr #21 80089fe: d01b beq.n 8008a38 <__cmpdf2+0x54> 8008a00: b001 add sp, #4 8008a02: ea50 0c41 orrs.w ip, r0, r1, lsl #1 8008a06: bf0c ite eq 8008a08: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 8008a0c: ea91 0f03 teqne r1, r3 8008a10: bf02 ittt eq 8008a12: ea90 0f02 teqeq r0, r2 8008a16: 2000 moveq r0, #0 8008a18: 4770 bxeq lr 8008a1a: f110 0f00 cmn.w r0, #0 8008a1e: ea91 0f03 teq r1, r3 8008a22: bf58 it pl 8008a24: 4299 cmppl r1, r3 8008a26: bf08 it eq 8008a28: 4290 cmpeq r0, r2 8008a2a: bf2c ite cs 8008a2c: 17d8 asrcs r0, r3, #31 8008a2e: ea6f 70e3 mvncc.w r0, r3, asr #31 8008a32: f040 0001 orr.w r0, r0, #1 8008a36: 4770 bx lr 8008a38: ea4f 0c41 mov.w ip, r1, lsl #1 8008a3c: ea7f 5c6c mvns.w ip, ip, asr #21 8008a40: d102 bne.n 8008a48 <__cmpdf2+0x64> 8008a42: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8008a46: d107 bne.n 8008a58 <__cmpdf2+0x74> 8008a48: ea4f 0c43 mov.w ip, r3, lsl #1 8008a4c: ea7f 5c6c mvns.w ip, ip, asr #21 8008a50: d1d6 bne.n 8008a00 <__cmpdf2+0x1c> 8008a52: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8008a56: d0d3 beq.n 8008a00 <__cmpdf2+0x1c> 8008a58: f85d 0b04 ldr.w r0, [sp], #4 8008a5c: 4770 bx lr 8008a5e: bf00 nop 08008a60 <__aeabi_cdrcmple>: 8008a60: 4684 mov ip, r0 8008a62: 4610 mov r0, r2 8008a64: 4662 mov r2, ip 8008a66: 468c mov ip, r1 8008a68: 4619 mov r1, r3 8008a6a: 4663 mov r3, ip 8008a6c: e000 b.n 8008a70 <__aeabi_cdcmpeq> 8008a6e: bf00 nop 08008a70 <__aeabi_cdcmpeq>: 8008a70: b501 push {r0, lr} 8008a72: f7ff ffb7 bl 80089e4 <__cmpdf2> 8008a76: 2800 cmp r0, #0 8008a78: bf48 it mi 8008a7a: f110 0f00 cmnmi.w r0, #0 8008a7e: bd01 pop {r0, pc} 08008a80 <__aeabi_dcmpeq>: 8008a80: f84d ed08 str.w lr, [sp, #-8]! 8008a84: f7ff fff4 bl 8008a70 <__aeabi_cdcmpeq> 8008a88: bf0c ite eq 8008a8a: 2001 moveq r0, #1 8008a8c: 2000 movne r0, #0 8008a8e: f85d fb08 ldr.w pc, [sp], #8 8008a92: bf00 nop 08008a94 <__aeabi_dcmplt>: 8008a94: f84d ed08 str.w lr, [sp, #-8]! 8008a98: f7ff ffea bl 8008a70 <__aeabi_cdcmpeq> 8008a9c: bf34 ite cc 8008a9e: 2001 movcc r0, #1 8008aa0: 2000 movcs r0, #0 8008aa2: f85d fb08 ldr.w pc, [sp], #8 8008aa6: bf00 nop 08008aa8 <__aeabi_dcmple>: 8008aa8: f84d ed08 str.w lr, [sp, #-8]! 8008aac: f7ff ffe0 bl 8008a70 <__aeabi_cdcmpeq> 8008ab0: bf94 ite ls 8008ab2: 2001 movls r0, #1 8008ab4: 2000 movhi r0, #0 8008ab6: f85d fb08 ldr.w pc, [sp], #8 8008aba: bf00 nop 08008abc <__aeabi_dcmpge>: 8008abc: f84d ed08 str.w lr, [sp, #-8]! 8008ac0: f7ff ffce bl 8008a60 <__aeabi_cdrcmple> 8008ac4: bf94 ite ls 8008ac6: 2001 movls r0, #1 8008ac8: 2000 movhi r0, #0 8008aca: f85d fb08 ldr.w pc, [sp], #8 8008ace: bf00 nop 08008ad0 <__aeabi_dcmpgt>: 8008ad0: f84d ed08 str.w lr, [sp, #-8]! 8008ad4: f7ff ffc4 bl 8008a60 <__aeabi_cdrcmple> 8008ad8: bf34 ite cc 8008ada: 2001 movcc r0, #1 8008adc: 2000 movcs r0, #0 8008ade: f85d fb08 ldr.w pc, [sp], #8 8008ae2: bf00 nop 08008ae4 <__aeabi_dcmpun>: 8008ae4: ea4f 0c41 mov.w ip, r1, lsl #1 8008ae8: ea7f 5c6c mvns.w ip, ip, asr #21 8008aec: d102 bne.n 8008af4 <__aeabi_dcmpun+0x10> 8008aee: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8008af2: d10a bne.n 8008b0a <__aeabi_dcmpun+0x26> 8008af4: ea4f 0c43 mov.w ip, r3, lsl #1 8008af8: ea7f 5c6c mvns.w ip, ip, asr #21 8008afc: d102 bne.n 8008b04 <__aeabi_dcmpun+0x20> 8008afe: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8008b02: d102 bne.n 8008b0a <__aeabi_dcmpun+0x26> 8008b04: f04f 0000 mov.w r0, #0 8008b08: 4770 bx lr 8008b0a: f04f 0001 mov.w r0, #1 8008b0e: 4770 bx lr 08008b10 <__aeabi_d2iz>: 8008b10: ea4f 0241 mov.w r2, r1, lsl #1 8008b14: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 8008b18: d215 bcs.n 8008b46 <__aeabi_d2iz+0x36> 8008b1a: d511 bpl.n 8008b40 <__aeabi_d2iz+0x30> 8008b1c: f46f 7378 mvn.w r3, #992 @ 0x3e0 8008b20: ebb3 5262 subs.w r2, r3, r2, asr #21 8008b24: d912 bls.n 8008b4c <__aeabi_d2iz+0x3c> 8008b26: ea4f 23c1 mov.w r3, r1, lsl #11 8008b2a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8008b2e: ea43 5350 orr.w r3, r3, r0, lsr #21 8008b32: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008b36: fa23 f002 lsr.w r0, r3, r2 8008b3a: bf18 it ne 8008b3c: 4240 negne r0, r0 8008b3e: 4770 bx lr 8008b40: f04f 0000 mov.w r0, #0 8008b44: 4770 bx lr 8008b46: ea50 3001 orrs.w r0, r0, r1, lsl #12 8008b4a: d105 bne.n 8008b58 <__aeabi_d2iz+0x48> 8008b4c: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000 8008b50: bf08 it eq 8008b52: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 8008b56: 4770 bx lr 8008b58: f04f 0000 mov.w r0, #0 8008b5c: 4770 bx lr 8008b5e: bf00 nop 08008b60 <__aeabi_d2f>: 8008b60: ea4f 0241 mov.w r2, r1, lsl #1 8008b64: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000 8008b68: bf24 itt cs 8008b6a: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000 8008b6e: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000 8008b72: d90d bls.n 8008b90 <__aeabi_d2f+0x30> 8008b74: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008b78: ea4f 02c0 mov.w r2, r0, lsl #3 8008b7c: ea4c 7050 orr.w r0, ip, r0, lsr #29 8008b80: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000 8008b84: eb40 0083 adc.w r0, r0, r3, lsl #2 8008b88: bf08 it eq 8008b8a: f020 0001 biceq.w r0, r0, #1 8008b8e: 4770 bx lr 8008b90: f011 4f80 tst.w r1, #1073741824 @ 0x40000000 8008b94: d121 bne.n 8008bda <__aeabi_d2f+0x7a> 8008b96: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000 8008b9a: bfbc itt lt 8008b9c: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000 8008ba0: 4770 bxlt lr 8008ba2: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008ba6: ea4f 5252 mov.w r2, r2, lsr #21 8008baa: f1c2 0218 rsb r2, r2, #24 8008bae: f1c2 0c20 rsb ip, r2, #32 8008bb2: fa10 f30c lsls.w r3, r0, ip 8008bb6: fa20 f002 lsr.w r0, r0, r2 8008bba: bf18 it ne 8008bbc: f040 0001 orrne.w r0, r0, #1 8008bc0: ea4f 23c1 mov.w r3, r1, lsl #11 8008bc4: ea4f 23d3 mov.w r3, r3, lsr #11 8008bc8: fa03 fc0c lsl.w ip, r3, ip 8008bcc: ea40 000c orr.w r0, r0, ip 8008bd0: fa23 f302 lsr.w r3, r3, r2 8008bd4: ea4f 0343 mov.w r3, r3, lsl #1 8008bd8: e7cc b.n 8008b74 <__aeabi_d2f+0x14> 8008bda: ea7f 5362 mvns.w r3, r2, asr #21 8008bde: d107 bne.n 8008bf0 <__aeabi_d2f+0x90> 8008be0: ea50 3301 orrs.w r3, r0, r1, lsl #12 8008be4: bf1e ittt ne 8008be6: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000 8008bea: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000 8008bee: 4770 bxne lr 8008bf0: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000 8008bf4: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008bf8: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008bfc: 4770 bx lr 8008bfe: bf00 nop 08008c00 <__aeabi_frsub>: 8008c00: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000 8008c04: e002 b.n 8008c0c <__addsf3> 8008c06: bf00 nop 08008c08 <__aeabi_fsub>: 8008c08: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 08008c0c <__addsf3>: 8008c0c: 0042 lsls r2, r0, #1 8008c0e: bf1f itttt ne 8008c10: ea5f 0341 movsne.w r3, r1, lsl #1 8008c14: ea92 0f03 teqne r2, r3 8008c18: ea7f 6c22 mvnsne.w ip, r2, asr #24 8008c1c: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008c20: d06a beq.n 8008cf8 <__addsf3+0xec> 8008c22: ea4f 6212 mov.w r2, r2, lsr #24 8008c26: ebd2 6313 rsbs r3, r2, r3, lsr #24 8008c2a: bfc1 itttt gt 8008c2c: 18d2 addgt r2, r2, r3 8008c2e: 4041 eorgt r1, r0 8008c30: 4048 eorgt r0, r1 8008c32: 4041 eorgt r1, r0 8008c34: bfb8 it lt 8008c36: 425b neglt r3, r3 8008c38: 2b19 cmp r3, #25 8008c3a: bf88 it hi 8008c3c: 4770 bxhi lr 8008c3e: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 8008c42: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008c46: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000 8008c4a: bf18 it ne 8008c4c: 4240 negne r0, r0 8008c4e: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008c52: f441 0100 orr.w r1, r1, #8388608 @ 0x800000 8008c56: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000 8008c5a: bf18 it ne 8008c5c: 4249 negne r1, r1 8008c5e: ea92 0f03 teq r2, r3 8008c62: d03f beq.n 8008ce4 <__addsf3+0xd8> 8008c64: f1a2 0201 sub.w r2, r2, #1 8008c68: fa41 fc03 asr.w ip, r1, r3 8008c6c: eb10 000c adds.w r0, r0, ip 8008c70: f1c3 0320 rsb r3, r3, #32 8008c74: fa01 f103 lsl.w r1, r1, r3 8008c78: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008c7c: d502 bpl.n 8008c84 <__addsf3+0x78> 8008c7e: 4249 negs r1, r1 8008c80: eb60 0040 sbc.w r0, r0, r0, lsl #1 8008c84: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000 8008c88: d313 bcc.n 8008cb2 <__addsf3+0xa6> 8008c8a: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000 8008c8e: d306 bcc.n 8008c9e <__addsf3+0x92> 8008c90: 0840 lsrs r0, r0, #1 8008c92: ea4f 0131 mov.w r1, r1, rrx 8008c96: f102 0201 add.w r2, r2, #1 8008c9a: 2afe cmp r2, #254 @ 0xfe 8008c9c: d251 bcs.n 8008d42 <__addsf3+0x136> 8008c9e: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000 8008ca2: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008ca6: bf08 it eq 8008ca8: f020 0001 biceq.w r0, r0, #1 8008cac: ea40 0003 orr.w r0, r0, r3 8008cb0: 4770 bx lr 8008cb2: 0049 lsls r1, r1, #1 8008cb4: eb40 0000 adc.w r0, r0, r0 8008cb8: 3a01 subs r2, #1 8008cba: bf28 it cs 8008cbc: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000 8008cc0: d2ed bcs.n 8008c9e <__addsf3+0x92> 8008cc2: fab0 fc80 clz ip, r0 8008cc6: f1ac 0c08 sub.w ip, ip, #8 8008cca: ebb2 020c subs.w r2, r2, ip 8008cce: fa00 f00c lsl.w r0, r0, ip 8008cd2: bfaa itet ge 8008cd4: eb00 50c2 addge.w r0, r0, r2, lsl #23 8008cd8: 4252 neglt r2, r2 8008cda: 4318 orrge r0, r3 8008cdc: bfbc itt lt 8008cde: 40d0 lsrlt r0, r2 8008ce0: 4318 orrlt r0, r3 8008ce2: 4770 bx lr 8008ce4: f092 0f00 teq r2, #0 8008ce8: f481 0100 eor.w r1, r1, #8388608 @ 0x800000 8008cec: bf06 itte eq 8008cee: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000 8008cf2: 3201 addeq r2, #1 8008cf4: 3b01 subne r3, #1 8008cf6: e7b5 b.n 8008c64 <__addsf3+0x58> 8008cf8: ea4f 0341 mov.w r3, r1, lsl #1 8008cfc: ea7f 6c22 mvns.w ip, r2, asr #24 8008d00: bf18 it ne 8008d02: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008d06: d021 beq.n 8008d4c <__addsf3+0x140> 8008d08: ea92 0f03 teq r2, r3 8008d0c: d004 beq.n 8008d18 <__addsf3+0x10c> 8008d0e: f092 0f00 teq r2, #0 8008d12: bf08 it eq 8008d14: 4608 moveq r0, r1 8008d16: 4770 bx lr 8008d18: ea90 0f01 teq r0, r1 8008d1c: bf1c itt ne 8008d1e: 2000 movne r0, #0 8008d20: 4770 bxne lr 8008d22: f012 4f7f tst.w r2, #4278190080 @ 0xff000000 8008d26: d104 bne.n 8008d32 <__addsf3+0x126> 8008d28: 0040 lsls r0, r0, #1 8008d2a: bf28 it cs 8008d2c: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000 8008d30: 4770 bx lr 8008d32: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000 8008d36: bf3c itt cc 8008d38: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000 8008d3c: 4770 bxcc lr 8008d3e: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008d42: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000 8008d46: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008d4a: 4770 bx lr 8008d4c: ea7f 6222 mvns.w r2, r2, asr #24 8008d50: bf16 itet ne 8008d52: 4608 movne r0, r1 8008d54: ea7f 6323 mvnseq.w r3, r3, asr #24 8008d58: 4601 movne r1, r0 8008d5a: 0242 lsls r2, r0, #9 8008d5c: bf06 itte eq 8008d5e: ea5f 2341 movseq.w r3, r1, lsl #9 8008d62: ea90 0f01 teqeq r0, r1 8008d66: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000 8008d6a: 4770 bx lr 08008d6c <__aeabi_ui2f>: 8008d6c: f04f 0300 mov.w r3, #0 8008d70: e004 b.n 8008d7c <__aeabi_i2f+0x8> 8008d72: bf00 nop 08008d74 <__aeabi_i2f>: 8008d74: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000 8008d78: bf48 it mi 8008d7a: 4240 negmi r0, r0 8008d7c: ea5f 0c00 movs.w ip, r0 8008d80: bf08 it eq 8008d82: 4770 bxeq lr 8008d84: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000 8008d88: 4601 mov r1, r0 8008d8a: f04f 0000 mov.w r0, #0 8008d8e: e01c b.n 8008dca <__aeabi_l2f+0x2a> 08008d90 <__aeabi_ul2f>: 8008d90: ea50 0201 orrs.w r2, r0, r1 8008d94: bf08 it eq 8008d96: 4770 bxeq lr 8008d98: f04f 0300 mov.w r3, #0 8008d9c: e00a b.n 8008db4 <__aeabi_l2f+0x14> 8008d9e: bf00 nop 08008da0 <__aeabi_l2f>: 8008da0: ea50 0201 orrs.w r2, r0, r1 8008da4: bf08 it eq 8008da6: 4770 bxeq lr 8008da8: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000 8008dac: d502 bpl.n 8008db4 <__aeabi_l2f+0x14> 8008dae: 4240 negs r0, r0 8008db0: eb61 0141 sbc.w r1, r1, r1, lsl #1 8008db4: ea5f 0c01 movs.w ip, r1 8008db8: bf02 ittt eq 8008dba: 4684 moveq ip, r0 8008dbc: 4601 moveq r1, r0 8008dbe: 2000 moveq r0, #0 8008dc0: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000 8008dc4: bf08 it eq 8008dc6: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000 8008dca: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 8008dce: fabc f28c clz r2, ip 8008dd2: 3a08 subs r2, #8 8008dd4: eba3 53c2 sub.w r3, r3, r2, lsl #23 8008dd8: db10 blt.n 8008dfc <__aeabi_l2f+0x5c> 8008dda: fa01 fc02 lsl.w ip, r1, r2 8008dde: 4463 add r3, ip 8008de0: fa00 fc02 lsl.w ip, r0, r2 8008de4: f1c2 0220 rsb r2, r2, #32 8008de8: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008dec: fa20 f202 lsr.w r2, r0, r2 8008df0: eb43 0002 adc.w r0, r3, r2 8008df4: bf08 it eq 8008df6: f020 0001 biceq.w r0, r0, #1 8008dfa: 4770 bx lr 8008dfc: f102 0220 add.w r2, r2, #32 8008e00: fa01 fc02 lsl.w ip, r1, r2 8008e04: f1c2 0220 rsb r2, r2, #32 8008e08: ea50 004c orrs.w r0, r0, ip, lsl #1 8008e0c: fa21 f202 lsr.w r2, r1, r2 8008e10: eb43 0002 adc.w r0, r3, r2 8008e14: bf08 it eq 8008e16: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008e1a: 4770 bx lr 08008e1c <__aeabi_fmul>: 8008e1c: f04f 0cff mov.w ip, #255 @ 0xff 8008e20: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008e24: bf1e ittt ne 8008e26: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008e2a: ea92 0f0c teqne r2, ip 8008e2e: ea93 0f0c teqne r3, ip 8008e32: d06f beq.n 8008f14 <__aeabi_fmul+0xf8> 8008e34: 441a add r2, r3 8008e36: ea80 0c01 eor.w ip, r0, r1 8008e3a: 0240 lsls r0, r0, #9 8008e3c: bf18 it ne 8008e3e: ea5f 2141 movsne.w r1, r1, lsl #9 8008e42: d01e beq.n 8008e82 <__aeabi_fmul+0x66> 8008e44: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8008e48: ea43 1050 orr.w r0, r3, r0, lsr #5 8008e4c: ea43 1151 orr.w r1, r3, r1, lsr #5 8008e50: fba0 3101 umull r3, r1, r0, r1 8008e54: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008e58: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000 8008e5c: bf3e ittt cc 8008e5e: 0049 lslcc r1, r1, #1 8008e60: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 8008e64: 005b lslcc r3, r3, #1 8008e66: ea40 0001 orr.w r0, r0, r1 8008e6a: f162 027f sbc.w r2, r2, #127 @ 0x7f 8008e6e: 2afd cmp r2, #253 @ 0xfd 8008e70: d81d bhi.n 8008eae <__aeabi_fmul+0x92> 8008e72: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008e76: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008e7a: bf08 it eq 8008e7c: f020 0001 biceq.w r0, r0, #1 8008e80: 4770 bx lr 8008e82: f090 0f00 teq r0, #0 8008e86: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8008e8a: bf08 it eq 8008e8c: 0249 lsleq r1, r1, #9 8008e8e: ea4c 2050 orr.w r0, ip, r0, lsr #9 8008e92: ea40 2051 orr.w r0, r0, r1, lsr #9 8008e96: 3a7f subs r2, #127 @ 0x7f 8008e98: bfc2 ittt gt 8008e9a: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 8008e9e: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8008ea2: 4770 bxgt lr 8008ea4: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008ea8: f04f 0300 mov.w r3, #0 8008eac: 3a01 subs r2, #1 8008eae: dc5d bgt.n 8008f6c <__aeabi_fmul+0x150> 8008eb0: f112 0f19 cmn.w r2, #25 8008eb4: bfdc itt le 8008eb6: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000 8008eba: 4770 bxle lr 8008ebc: f1c2 0200 rsb r2, r2, #0 8008ec0: 0041 lsls r1, r0, #1 8008ec2: fa21 f102 lsr.w r1, r1, r2 8008ec6: f1c2 0220 rsb r2, r2, #32 8008eca: fa00 fc02 lsl.w ip, r0, r2 8008ece: ea5f 0031 movs.w r0, r1, rrx 8008ed2: f140 0000 adc.w r0, r0, #0 8008ed6: ea53 034c orrs.w r3, r3, ip, lsl #1 8008eda: bf08 it eq 8008edc: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008ee0: 4770 bx lr 8008ee2: f092 0f00 teq r2, #0 8008ee6: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8008eea: bf02 ittt eq 8008eec: 0040 lsleq r0, r0, #1 8008eee: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 8008ef2: 3a01 subeq r2, #1 8008ef4: d0f9 beq.n 8008eea <__aeabi_fmul+0xce> 8008ef6: ea40 000c orr.w r0, r0, ip 8008efa: f093 0f00 teq r3, #0 8008efe: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008f02: bf02 ittt eq 8008f04: 0049 lsleq r1, r1, #1 8008f06: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8008f0a: 3b01 subeq r3, #1 8008f0c: d0f9 beq.n 8008f02 <__aeabi_fmul+0xe6> 8008f0e: ea41 010c orr.w r1, r1, ip 8008f12: e78f b.n 8008e34 <__aeabi_fmul+0x18> 8008f14: ea0c 53d1 and.w r3, ip, r1, lsr #23 8008f18: ea92 0f0c teq r2, ip 8008f1c: bf18 it ne 8008f1e: ea93 0f0c teqne r3, ip 8008f22: d00a beq.n 8008f3a <__aeabi_fmul+0x11e> 8008f24: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 8008f28: bf18 it ne 8008f2a: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 8008f2e: d1d8 bne.n 8008ee2 <__aeabi_fmul+0xc6> 8008f30: ea80 0001 eor.w r0, r0, r1 8008f34: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008f38: 4770 bx lr 8008f3a: f090 0f00 teq r0, #0 8008f3e: bf17 itett ne 8008f40: f090 4f00 teqne r0, #2147483648 @ 0x80000000 8008f44: 4608 moveq r0, r1 8008f46: f091 0f00 teqne r1, #0 8008f4a: f091 4f00 teqne r1, #2147483648 @ 0x80000000 8008f4e: d014 beq.n 8008f7a <__aeabi_fmul+0x15e> 8008f50: ea92 0f0c teq r2, ip 8008f54: d101 bne.n 8008f5a <__aeabi_fmul+0x13e> 8008f56: 0242 lsls r2, r0, #9 8008f58: d10f bne.n 8008f7a <__aeabi_fmul+0x15e> 8008f5a: ea93 0f0c teq r3, ip 8008f5e: d103 bne.n 8008f68 <__aeabi_fmul+0x14c> 8008f60: 024b lsls r3, r1, #9 8008f62: bf18 it ne 8008f64: 4608 movne r0, r1 8008f66: d108 bne.n 8008f7a <__aeabi_fmul+0x15e> 8008f68: ea80 0001 eor.w r0, r0, r1 8008f6c: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008f70: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008f74: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008f78: 4770 bx lr 8008f7a: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008f7e: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000 8008f82: 4770 bx lr 08008f84 <__aeabi_fdiv>: 8008f84: f04f 0cff mov.w ip, #255 @ 0xff 8008f88: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008f8c: bf1e ittt ne 8008f8e: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008f92: ea92 0f0c teqne r2, ip 8008f96: ea93 0f0c teqne r3, ip 8008f9a: d069 beq.n 8009070 <__aeabi_fdiv+0xec> 8008f9c: eba2 0203 sub.w r2, r2, r3 8008fa0: ea80 0c01 eor.w ip, r0, r1 8008fa4: 0249 lsls r1, r1, #9 8008fa6: ea4f 2040 mov.w r0, r0, lsl #9 8008faa: d037 beq.n 800901c <__aeabi_fdiv+0x98> 8008fac: f04f 5380 mov.w r3, #268435456 @ 0x10000000 8008fb0: ea43 1111 orr.w r1, r3, r1, lsr #4 8008fb4: ea43 1310 orr.w r3, r3, r0, lsr #4 8008fb8: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008fbc: 428b cmp r3, r1 8008fbe: bf38 it cc 8008fc0: 005b lslcc r3, r3, #1 8008fc2: f142 027d adc.w r2, r2, #125 @ 0x7d 8008fc6: f44f 0c00 mov.w ip, #8388608 @ 0x800000 8008fca: 428b cmp r3, r1 8008fcc: bf24 itt cs 8008fce: 1a5b subcs r3, r3, r1 8008fd0: ea40 000c orrcs.w r0, r0, ip 8008fd4: ebb3 0f51 cmp.w r3, r1, lsr #1 8008fd8: bf24 itt cs 8008fda: eba3 0351 subcs.w r3, r3, r1, lsr #1 8008fde: ea40 005c orrcs.w r0, r0, ip, lsr #1 8008fe2: ebb3 0f91 cmp.w r3, r1, lsr #2 8008fe6: bf24 itt cs 8008fe8: eba3 0391 subcs.w r3, r3, r1, lsr #2 8008fec: ea40 009c orrcs.w r0, r0, ip, lsr #2 8008ff0: ebb3 0fd1 cmp.w r3, r1, lsr #3 8008ff4: bf24 itt cs 8008ff6: eba3 03d1 subcs.w r3, r3, r1, lsr #3 8008ffa: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8008ffe: 011b lsls r3, r3, #4 8009000: bf18 it ne 8009002: ea5f 1c1c movsne.w ip, ip, lsr #4 8009006: d1e0 bne.n 8008fca <__aeabi_fdiv+0x46> 8009008: 2afd cmp r2, #253 @ 0xfd 800900a: f63f af50 bhi.w 8008eae <__aeabi_fmul+0x92> 800900e: 428b cmp r3, r1 8009010: eb40 50c2 adc.w r0, r0, r2, lsl #23 8009014: bf08 it eq 8009016: f020 0001 biceq.w r0, r0, #1 800901a: 4770 bx lr 800901c: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8009020: ea4c 2050 orr.w r0, ip, r0, lsr #9 8009024: 327f adds r2, #127 @ 0x7f 8009026: bfc2 ittt gt 8009028: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 800902c: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8009030: 4770 bxgt lr 8009032: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8009036: f04f 0300 mov.w r3, #0 800903a: 3a01 subs r2, #1 800903c: e737 b.n 8008eae <__aeabi_fmul+0x92> 800903e: f092 0f00 teq r2, #0 8009042: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8009046: bf02 ittt eq 8009048: 0040 lsleq r0, r0, #1 800904a: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 800904e: 3a01 subeq r2, #1 8009050: d0f9 beq.n 8009046 <__aeabi_fdiv+0xc2> 8009052: ea40 000c orr.w r0, r0, ip 8009056: f093 0f00 teq r3, #0 800905a: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 800905e: bf02 ittt eq 8009060: 0049 lsleq r1, r1, #1 8009062: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8009066: 3b01 subeq r3, #1 8009068: d0f9 beq.n 800905e <__aeabi_fdiv+0xda> 800906a: ea41 010c orr.w r1, r1, ip 800906e: e795 b.n 8008f9c <__aeabi_fdiv+0x18> 8009070: ea0c 53d1 and.w r3, ip, r1, lsr #23 8009074: ea92 0f0c teq r2, ip 8009078: d108 bne.n 800908c <__aeabi_fdiv+0x108> 800907a: 0242 lsls r2, r0, #9 800907c: f47f af7d bne.w 8008f7a <__aeabi_fmul+0x15e> 8009080: ea93 0f0c teq r3, ip 8009084: f47f af70 bne.w 8008f68 <__aeabi_fmul+0x14c> 8009088: 4608 mov r0, r1 800908a: e776 b.n 8008f7a <__aeabi_fmul+0x15e> 800908c: ea93 0f0c teq r3, ip 8009090: d104 bne.n 800909c <__aeabi_fdiv+0x118> 8009092: 024b lsls r3, r1, #9 8009094: f43f af4c beq.w 8008f30 <__aeabi_fmul+0x114> 8009098: 4608 mov r0, r1 800909a: e76e b.n 8008f7a <__aeabi_fmul+0x15e> 800909c: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 80090a0: bf18 it ne 80090a2: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 80090a6: d1ca bne.n 800903e <__aeabi_fdiv+0xba> 80090a8: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000 80090ac: f47f af5c bne.w 8008f68 <__aeabi_fmul+0x14c> 80090b0: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000 80090b4: f47f af3c bne.w 8008f30 <__aeabi_fmul+0x114> 80090b8: e75f b.n 8008f7a <__aeabi_fmul+0x15e> 80090ba: bf00 nop 080090bc <__gesf2>: 80090bc: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80090c0: e006 b.n 80090d0 <__cmpsf2+0x4> 80090c2: bf00 nop 080090c4 <__lesf2>: 80090c4: f04f 0c01 mov.w ip, #1 80090c8: e002 b.n 80090d0 <__cmpsf2+0x4> 80090ca: bf00 nop 080090cc <__cmpsf2>: 80090cc: f04f 0c01 mov.w ip, #1 80090d0: f84d cd04 str.w ip, [sp, #-4]! 80090d4: ea4f 0240 mov.w r2, r0, lsl #1 80090d8: ea4f 0341 mov.w r3, r1, lsl #1 80090dc: ea7f 6c22 mvns.w ip, r2, asr #24 80090e0: bf18 it ne 80090e2: ea7f 6c23 mvnsne.w ip, r3, asr #24 80090e6: d011 beq.n 800910c <__cmpsf2+0x40> 80090e8: b001 add sp, #4 80090ea: ea52 0c53 orrs.w ip, r2, r3, lsr #1 80090ee: bf18 it ne 80090f0: ea90 0f01 teqne r0, r1 80090f4: bf58 it pl 80090f6: ebb2 0003 subspl.w r0, r2, r3 80090fa: bf88 it hi 80090fc: 17c8 asrhi r0, r1, #31 80090fe: bf38 it cc 8009100: ea6f 70e1 mvncc.w r0, r1, asr #31 8009104: bf18 it ne 8009106: f040 0001 orrne.w r0, r0, #1 800910a: 4770 bx lr 800910c: ea7f 6c22 mvns.w ip, r2, asr #24 8009110: d102 bne.n 8009118 <__cmpsf2+0x4c> 8009112: ea5f 2c40 movs.w ip, r0, lsl #9 8009116: d105 bne.n 8009124 <__cmpsf2+0x58> 8009118: ea7f 6c23 mvns.w ip, r3, asr #24 800911c: d1e4 bne.n 80090e8 <__cmpsf2+0x1c> 800911e: ea5f 2c41 movs.w ip, r1, lsl #9 8009122: d0e1 beq.n 80090e8 <__cmpsf2+0x1c> 8009124: f85d 0b04 ldr.w r0, [sp], #4 8009128: 4770 bx lr 800912a: bf00 nop 0800912c <__aeabi_cfrcmple>: 800912c: 4684 mov ip, r0 800912e: 4608 mov r0, r1 8009130: 4661 mov r1, ip 8009132: e7ff b.n 8009134 <__aeabi_cfcmpeq> 08009134 <__aeabi_cfcmpeq>: 8009134: b50f push {r0, r1, r2, r3, lr} 8009136: f7ff ffc9 bl 80090cc <__cmpsf2> 800913a: 2800 cmp r0, #0 800913c: bf48 it mi 800913e: f110 0f00 cmnmi.w r0, #0 8009142: bd0f pop {r0, r1, r2, r3, pc} 08009144 <__aeabi_fcmpeq>: 8009144: f84d ed08 str.w lr, [sp, #-8]! 8009148: f7ff fff4 bl 8009134 <__aeabi_cfcmpeq> 800914c: bf0c ite eq 800914e: 2001 moveq r0, #1 8009150: 2000 movne r0, #0 8009152: f85d fb08 ldr.w pc, [sp], #8 8009156: bf00 nop 08009158 <__aeabi_fcmplt>: 8009158: f84d ed08 str.w lr, [sp, #-8]! 800915c: f7ff ffea bl 8009134 <__aeabi_cfcmpeq> 8009160: bf34 ite cc 8009162: 2001 movcc r0, #1 8009164: 2000 movcs r0, #0 8009166: f85d fb08 ldr.w pc, [sp], #8 800916a: bf00 nop 0800916c <__aeabi_fcmple>: 800916c: f84d ed08 str.w lr, [sp, #-8]! 8009170: f7ff ffe0 bl 8009134 <__aeabi_cfcmpeq> 8009174: bf94 ite ls 8009176: 2001 movls r0, #1 8009178: 2000 movhi r0, #0 800917a: f85d fb08 ldr.w pc, [sp], #8 800917e: bf00 nop 08009180 <__aeabi_fcmpge>: 8009180: f84d ed08 str.w lr, [sp, #-8]! 8009184: f7ff ffd2 bl 800912c <__aeabi_cfrcmple> 8009188: bf94 ite ls 800918a: 2001 movls r0, #1 800918c: 2000 movhi r0, #0 800918e: f85d fb08 ldr.w pc, [sp], #8 8009192: bf00 nop 08009194 <__aeabi_fcmpgt>: 8009194: f84d ed08 str.w lr, [sp, #-8]! 8009198: f7ff ffc8 bl 800912c <__aeabi_cfrcmple> 800919c: bf34 ite cc 800919e: 2001 movcc r0, #1 80091a0: 2000 movcs r0, #0 80091a2: f85d fb08 ldr.w pc, [sp], #8 80091a6: bf00 nop 080091a8 <__aeabi_f2iz>: 80091a8: ea4f 0240 mov.w r2, r0, lsl #1 80091ac: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000 80091b0: d30f bcc.n 80091d2 <__aeabi_f2iz+0x2a> 80091b2: f04f 039e mov.w r3, #158 @ 0x9e 80091b6: ebb3 6212 subs.w r2, r3, r2, lsr #24 80091ba: d90d bls.n 80091d8 <__aeabi_f2iz+0x30> 80091bc: ea4f 2300 mov.w r3, r0, lsl #8 80091c0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80091c4: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 80091c8: fa23 f002 lsr.w r0, r3, r2 80091cc: bf18 it ne 80091ce: 4240 negne r0, r0 80091d0: 4770 bx lr 80091d2: f04f 0000 mov.w r0, #0 80091d6: 4770 bx lr 80091d8: f112 0f61 cmn.w r2, #97 @ 0x61 80091dc: d101 bne.n 80091e2 <__aeabi_f2iz+0x3a> 80091de: 0242 lsls r2, r0, #9 80091e0: d105 bne.n 80091ee <__aeabi_f2iz+0x46> 80091e2: f010 4000 ands.w r0, r0, #2147483648 @ 0x80000000 80091e6: bf08 it eq 80091e8: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 80091ec: 4770 bx lr 80091ee: f04f 0000 mov.w r0, #0 80091f2: 4770 bx lr 080091f4 <__aeabi_uldivmod>: 80091f4: b953 cbnz r3, 800920c <__aeabi_uldivmod+0x18> 80091f6: b94a cbnz r2, 800920c <__aeabi_uldivmod+0x18> 80091f8: 2900 cmp r1, #0 80091fa: bf08 it eq 80091fc: 2800 cmpeq r0, #0 80091fe: bf1c itt ne 8009200: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8009204: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8009208: f000 b98c b.w 8009524 <__aeabi_idiv0> 800920c: f1ad 0c08 sub.w ip, sp, #8 8009210: e96d ce04 strd ip, lr, [sp, #-16]! 8009214: f000 f806 bl 8009224 <__udivmoddi4> 8009218: f8dd e004 ldr.w lr, [sp, #4] 800921c: e9dd 2302 ldrd r2, r3, [sp, #8] 8009220: b004 add sp, #16 8009222: 4770 bx lr 08009224 <__udivmoddi4>: 8009224: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8009228: 9d08 ldr r5, [sp, #32] 800922a: 468e mov lr, r1 800922c: 4604 mov r4, r0 800922e: 4688 mov r8, r1 8009230: 2b00 cmp r3, #0 8009232: d14a bne.n 80092ca <__udivmoddi4+0xa6> 8009234: 428a cmp r2, r1 8009236: 4617 mov r7, r2 8009238: d962 bls.n 8009300 <__udivmoddi4+0xdc> 800923a: fab2 f682 clz r6, r2 800923e: b14e cbz r6, 8009254 <__udivmoddi4+0x30> 8009240: f1c6 0320 rsb r3, r6, #32 8009244: fa01 f806 lsl.w r8, r1, r6 8009248: fa20 f303 lsr.w r3, r0, r3 800924c: 40b7 lsls r7, r6 800924e: ea43 0808 orr.w r8, r3, r8 8009252: 40b4 lsls r4, r6 8009254: ea4f 4e17 mov.w lr, r7, lsr #16 8009258: fbb8 f1fe udiv r1, r8, lr 800925c: fa1f fc87 uxth.w ip, r7 8009260: fb0e 8811 mls r8, lr, r1, r8 8009264: fb01 f20c mul.w r2, r1, ip 8009268: 0c23 lsrs r3, r4, #16 800926a: ea43 4308 orr.w r3, r3, r8, lsl #16 800926e: 429a cmp r2, r3 8009270: d909 bls.n 8009286 <__udivmoddi4+0x62> 8009272: 18fb adds r3, r7, r3 8009274: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8009278: f080 80eb bcs.w 8009452 <__udivmoddi4+0x22e> 800927c: 429a cmp r2, r3 800927e: f240 80e8 bls.w 8009452 <__udivmoddi4+0x22e> 8009282: 3902 subs r1, #2 8009284: 443b add r3, r7 8009286: 1a9a subs r2, r3, r2 8009288: fbb2 f0fe udiv r0, r2, lr 800928c: fb0e 2210 mls r2, lr, r0, r2 8009290: fb00 fc0c mul.w ip, r0, ip 8009294: b2a3 uxth r3, r4 8009296: ea43 4302 orr.w r3, r3, r2, lsl #16 800929a: 459c cmp ip, r3 800929c: d909 bls.n 80092b2 <__udivmoddi4+0x8e> 800929e: 18fb adds r3, r7, r3 80092a0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80092a4: f080 80d7 bcs.w 8009456 <__udivmoddi4+0x232> 80092a8: 459c cmp ip, r3 80092aa: f240 80d4 bls.w 8009456 <__udivmoddi4+0x232> 80092ae: 443b add r3, r7 80092b0: 3802 subs r0, #2 80092b2: ea40 4001 orr.w r0, r0, r1, lsl #16 80092b6: 2100 movs r1, #0 80092b8: eba3 030c sub.w r3, r3, ip 80092bc: b11d cbz r5, 80092c6 <__udivmoddi4+0xa2> 80092be: 2200 movs r2, #0 80092c0: 40f3 lsrs r3, r6 80092c2: e9c5 3200 strd r3, r2, [r5] 80092c6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80092ca: 428b cmp r3, r1 80092cc: d905 bls.n 80092da <__udivmoddi4+0xb6> 80092ce: b10d cbz r5, 80092d4 <__udivmoddi4+0xb0> 80092d0: e9c5 0100 strd r0, r1, [r5] 80092d4: 2100 movs r1, #0 80092d6: 4608 mov r0, r1 80092d8: e7f5 b.n 80092c6 <__udivmoddi4+0xa2> 80092da: fab3 f183 clz r1, r3 80092de: 2900 cmp r1, #0 80092e0: d146 bne.n 8009370 <__udivmoddi4+0x14c> 80092e2: 4573 cmp r3, lr 80092e4: d302 bcc.n 80092ec <__udivmoddi4+0xc8> 80092e6: 4282 cmp r2, r0 80092e8: f200 8108 bhi.w 80094fc <__udivmoddi4+0x2d8> 80092ec: 1a84 subs r4, r0, r2 80092ee: eb6e 0203 sbc.w r2, lr, r3 80092f2: 2001 movs r0, #1 80092f4: 4690 mov r8, r2 80092f6: 2d00 cmp r5, #0 80092f8: d0e5 beq.n 80092c6 <__udivmoddi4+0xa2> 80092fa: e9c5 4800 strd r4, r8, [r5] 80092fe: e7e2 b.n 80092c6 <__udivmoddi4+0xa2> 8009300: 2a00 cmp r2, #0 8009302: f000 8091 beq.w 8009428 <__udivmoddi4+0x204> 8009306: fab2 f682 clz r6, r2 800930a: 2e00 cmp r6, #0 800930c: f040 80a5 bne.w 800945a <__udivmoddi4+0x236> 8009310: 1a8a subs r2, r1, r2 8009312: 2101 movs r1, #1 8009314: 0c03 lsrs r3, r0, #16 8009316: ea4f 4e17 mov.w lr, r7, lsr #16 800931a: b280 uxth r0, r0 800931c: b2bc uxth r4, r7 800931e: fbb2 fcfe udiv ip, r2, lr 8009322: fb0e 221c mls r2, lr, ip, r2 8009326: ea43 4302 orr.w r3, r3, r2, lsl #16 800932a: fb04 f20c mul.w r2, r4, ip 800932e: 429a cmp r2, r3 8009330: d907 bls.n 8009342 <__udivmoddi4+0x11e> 8009332: 18fb adds r3, r7, r3 8009334: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8009338: d202 bcs.n 8009340 <__udivmoddi4+0x11c> 800933a: 429a cmp r2, r3 800933c: f200 80e3 bhi.w 8009506 <__udivmoddi4+0x2e2> 8009340: 46c4 mov ip, r8 8009342: 1a9b subs r3, r3, r2 8009344: fbb3 f2fe udiv r2, r3, lr 8009348: fb0e 3312 mls r3, lr, r2, r3 800934c: fb02 f404 mul.w r4, r2, r4 8009350: ea40 4303 orr.w r3, r0, r3, lsl #16 8009354: 429c cmp r4, r3 8009356: d907 bls.n 8009368 <__udivmoddi4+0x144> 8009358: 18fb adds r3, r7, r3 800935a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800935e: d202 bcs.n 8009366 <__udivmoddi4+0x142> 8009360: 429c cmp r4, r3 8009362: f200 80cd bhi.w 8009500 <__udivmoddi4+0x2dc> 8009366: 4602 mov r2, r0 8009368: 1b1b subs r3, r3, r4 800936a: ea42 400c orr.w r0, r2, ip, lsl #16 800936e: e7a5 b.n 80092bc <__udivmoddi4+0x98> 8009370: f1c1 0620 rsb r6, r1, #32 8009374: 408b lsls r3, r1 8009376: fa22 f706 lsr.w r7, r2, r6 800937a: 431f orrs r7, r3 800937c: fa2e fa06 lsr.w sl, lr, r6 8009380: ea4f 4917 mov.w r9, r7, lsr #16 8009384: fbba f8f9 udiv r8, sl, r9 8009388: fa0e fe01 lsl.w lr, lr, r1 800938c: fa20 f306 lsr.w r3, r0, r6 8009390: fb09 aa18 mls sl, r9, r8, sl 8009394: fa1f fc87 uxth.w ip, r7 8009398: ea43 030e orr.w r3, r3, lr 800939c: fa00 fe01 lsl.w lr, r0, r1 80093a0: fb08 f00c mul.w r0, r8, ip 80093a4: 0c1c lsrs r4, r3, #16 80093a6: ea44 440a orr.w r4, r4, sl, lsl #16 80093aa: 42a0 cmp r0, r4 80093ac: fa02 f201 lsl.w r2, r2, r1 80093b0: d90a bls.n 80093c8 <__udivmoddi4+0x1a4> 80093b2: 193c adds r4, r7, r4 80093b4: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff 80093b8: f080 809e bcs.w 80094f8 <__udivmoddi4+0x2d4> 80093bc: 42a0 cmp r0, r4 80093be: f240 809b bls.w 80094f8 <__udivmoddi4+0x2d4> 80093c2: f1a8 0802 sub.w r8, r8, #2 80093c6: 443c add r4, r7 80093c8: 1a24 subs r4, r4, r0 80093ca: b298 uxth r0, r3 80093cc: fbb4 f3f9 udiv r3, r4, r9 80093d0: fb09 4413 mls r4, r9, r3, r4 80093d4: fb03 fc0c mul.w ip, r3, ip 80093d8: ea40 4404 orr.w r4, r0, r4, lsl #16 80093dc: 45a4 cmp ip, r4 80093de: d909 bls.n 80093f4 <__udivmoddi4+0x1d0> 80093e0: 193c adds r4, r7, r4 80093e2: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 80093e6: f080 8085 bcs.w 80094f4 <__udivmoddi4+0x2d0> 80093ea: 45a4 cmp ip, r4 80093ec: f240 8082 bls.w 80094f4 <__udivmoddi4+0x2d0> 80093f0: 3b02 subs r3, #2 80093f2: 443c add r4, r7 80093f4: ea43 4008 orr.w r0, r3, r8, lsl #16 80093f8: eba4 040c sub.w r4, r4, ip 80093fc: fba0 8c02 umull r8, ip, r0, r2 8009400: 4564 cmp r4, ip 8009402: 4643 mov r3, r8 8009404: 46e1 mov r9, ip 8009406: d364 bcc.n 80094d2 <__udivmoddi4+0x2ae> 8009408: d061 beq.n 80094ce <__udivmoddi4+0x2aa> 800940a: b15d cbz r5, 8009424 <__udivmoddi4+0x200> 800940c: ebbe 0203 subs.w r2, lr, r3 8009410: eb64 0409 sbc.w r4, r4, r9 8009414: fa04 f606 lsl.w r6, r4, r6 8009418: fa22 f301 lsr.w r3, r2, r1 800941c: 431e orrs r6, r3 800941e: 40cc lsrs r4, r1 8009420: e9c5 6400 strd r6, r4, [r5] 8009424: 2100 movs r1, #0 8009426: e74e b.n 80092c6 <__udivmoddi4+0xa2> 8009428: fbb1 fcf2 udiv ip, r1, r2 800942c: 0c01 lsrs r1, r0, #16 800942e: ea41 410e orr.w r1, r1, lr, lsl #16 8009432: b280 uxth r0, r0 8009434: ea40 4201 orr.w r2, r0, r1, lsl #16 8009438: 463b mov r3, r7 800943a: fbb1 f1f7 udiv r1, r1, r7 800943e: 4638 mov r0, r7 8009440: 463c mov r4, r7 8009442: 46b8 mov r8, r7 8009444: 46be mov lr, r7 8009446: 2620 movs r6, #32 8009448: eba2 0208 sub.w r2, r2, r8 800944c: ea41 410c orr.w r1, r1, ip, lsl #16 8009450: e765 b.n 800931e <__udivmoddi4+0xfa> 8009452: 4601 mov r1, r0 8009454: e717 b.n 8009286 <__udivmoddi4+0x62> 8009456: 4610 mov r0, r2 8009458: e72b b.n 80092b2 <__udivmoddi4+0x8e> 800945a: f1c6 0120 rsb r1, r6, #32 800945e: fa2e fc01 lsr.w ip, lr, r1 8009462: 40b7 lsls r7, r6 8009464: fa0e fe06 lsl.w lr, lr, r6 8009468: fa20 f101 lsr.w r1, r0, r1 800946c: ea41 010e orr.w r1, r1, lr 8009470: ea4f 4e17 mov.w lr, r7, lsr #16 8009474: fbbc f8fe udiv r8, ip, lr 8009478: b2bc uxth r4, r7 800947a: fb0e cc18 mls ip, lr, r8, ip 800947e: fb08 f904 mul.w r9, r8, r4 8009482: 0c0a lsrs r2, r1, #16 8009484: ea42 420c orr.w r2, r2, ip, lsl #16 8009488: 40b0 lsls r0, r6 800948a: 4591 cmp r9, r2 800948c: ea4f 4310 mov.w r3, r0, lsr #16 8009490: b280 uxth r0, r0 8009492: d93e bls.n 8009512 <__udivmoddi4+0x2ee> 8009494: 18ba adds r2, r7, r2 8009496: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 800949a: d201 bcs.n 80094a0 <__udivmoddi4+0x27c> 800949c: 4591 cmp r9, r2 800949e: d81f bhi.n 80094e0 <__udivmoddi4+0x2bc> 80094a0: eba2 0209 sub.w r2, r2, r9 80094a4: fbb2 f9fe udiv r9, r2, lr 80094a8: fb09 f804 mul.w r8, r9, r4 80094ac: fb0e 2a19 mls sl, lr, r9, r2 80094b0: b28a uxth r2, r1 80094b2: ea42 420a orr.w r2, r2, sl, lsl #16 80094b6: 4542 cmp r2, r8 80094b8: d229 bcs.n 800950e <__udivmoddi4+0x2ea> 80094ba: 18ba adds r2, r7, r2 80094bc: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80094c0: d2c2 bcs.n 8009448 <__udivmoddi4+0x224> 80094c2: 4542 cmp r2, r8 80094c4: d2c0 bcs.n 8009448 <__udivmoddi4+0x224> 80094c6: f1a9 0102 sub.w r1, r9, #2 80094ca: 443a add r2, r7 80094cc: e7bc b.n 8009448 <__udivmoddi4+0x224> 80094ce: 45c6 cmp lr, r8 80094d0: d29b bcs.n 800940a <__udivmoddi4+0x1e6> 80094d2: ebb8 0302 subs.w r3, r8, r2 80094d6: eb6c 0c07 sbc.w ip, ip, r7 80094da: 3801 subs r0, #1 80094dc: 46e1 mov r9, ip 80094de: e794 b.n 800940a <__udivmoddi4+0x1e6> 80094e0: eba7 0909 sub.w r9, r7, r9 80094e4: 444a add r2, r9 80094e6: fbb2 f9fe udiv r9, r2, lr 80094ea: f1a8 0c02 sub.w ip, r8, #2 80094ee: fb09 f804 mul.w r8, r9, r4 80094f2: e7db b.n 80094ac <__udivmoddi4+0x288> 80094f4: 4603 mov r3, r0 80094f6: e77d b.n 80093f4 <__udivmoddi4+0x1d0> 80094f8: 46d0 mov r8, sl 80094fa: e765 b.n 80093c8 <__udivmoddi4+0x1a4> 80094fc: 4608 mov r0, r1 80094fe: e6fa b.n 80092f6 <__udivmoddi4+0xd2> 8009500: 443b add r3, r7 8009502: 3a02 subs r2, #2 8009504: e730 b.n 8009368 <__udivmoddi4+0x144> 8009506: f1ac 0c02 sub.w ip, ip, #2 800950a: 443b add r3, r7 800950c: e719 b.n 8009342 <__udivmoddi4+0x11e> 800950e: 4649 mov r1, r9 8009510: e79a b.n 8009448 <__udivmoddi4+0x224> 8009512: eba2 0209 sub.w r2, r2, r9 8009516: fbb2 f9fe udiv r9, r2, lr 800951a: 46c4 mov ip, r8 800951c: fb09 f804 mul.w r8, r9, r4 8009520: e7c4 b.n 80094ac <__udivmoddi4+0x288> 8009522: bf00 nop 08009524 <__aeabi_idiv0>: 8009524: 4770 bx lr 8009526: bf00 nop 08009528 : static volatile uint16_t adc_dma_raw[6]; volatile ADC_ScanData_t adc_data = {0}; static volatile uint8_t adc_scan_data_ready = 0u; void ADC_ScanStart(void) { 8009528: b580 push {r7, lr} 800952a: af00 add r7, sp, #0 if (HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc_dma_raw, 6u) != HAL_OK) 800952c: 2206 movs r2, #6 800952e: 4905 ldr r1, [pc, #20] @ (8009544 ) 8009530: 4805 ldr r0, [pc, #20] @ (8009548 ) 8009532: f004 fcd7 bl 800dee4 8009536: 4603 mov r3, r0 8009538: 2b00 cmp r3, #0 800953a: d001 beq.n 8009540 { Error_Handler(); 800953c: f001 fa72 bl 800aa24 } } 8009540: bf00 nop 8009542: bd80 pop {r7, pc} 8009544: 2000025c .word 0x2000025c 8009548: 20000278 .word 0x20000278 0800954c : ISR_FAST void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { if (hadc->Instance != ADC1) 800954c: 4b0e ldr r3, [pc, #56] @ (8009588 ) 800954e: 6802 ldr r2, [r0, #0] 8009550: 429a cmp r2, r3 8009552: d118 bne.n 8009586 adc_data.cp_raw = adc_dma_raw[1]; adc_data.ntc1_raw = adc_dma_raw[2]; adc_data.ntc2_raw = adc_dma_raw[3]; adc_data.temp_sensor_raw = adc_dma_raw[4]; adc_data.vrefint_raw = adc_dma_raw[5]; adc_scan_data_ready = 1u; 8009554: f04f 0c01 mov.w ip, #1 adc_data.in3_raw = adc_dma_raw[0]; 8009558: 4a0c ldr r2, [pc, #48] @ (800958c ) 800955a: 4b0d ldr r3, [pc, #52] @ (8009590 ) 800955c: 8811 ldrh r1, [r2, #0] adc_scan_data_ready = 1u; 800955e: 480d ldr r0, [pc, #52] @ (8009594 ) adc_data.in3_raw = adc_dma_raw[0]; 8009560: b289 uxth r1, r1 8009562: 8019 strh r1, [r3, #0] adc_data.cp_raw = adc_dma_raw[1]; 8009564: 8851 ldrh r1, [r2, #2] 8009566: b289 uxth r1, r1 8009568: 8059 strh r1, [r3, #2] adc_data.ntc1_raw = adc_dma_raw[2]; 800956a: 8891 ldrh r1, [r2, #4] 800956c: b289 uxth r1, r1 800956e: 8099 strh r1, [r3, #4] adc_data.ntc2_raw = adc_dma_raw[3]; 8009570: 88d1 ldrh r1, [r2, #6] 8009572: b289 uxth r1, r1 8009574: 80d9 strh r1, [r3, #6] adc_data.temp_sensor_raw = adc_dma_raw[4]; 8009576: 8911 ldrh r1, [r2, #8] 8009578: b289 uxth r1, r1 800957a: 8119 strh r1, [r3, #8] adc_data.vrefint_raw = adc_dma_raw[5]; 800957c: 8952 ldrh r2, [r2, #10] 800957e: b292 uxth r2, r2 8009580: 815a strh r2, [r3, #10] adc_scan_data_ready = 1u; 8009582: f880 c000 strb.w ip, [r0] } 8009586: 4770 bx lr 8009588: 40012400 .word 0x40012400 800958c: 2000025c .word 0x2000025c 8009590: 20000268 .word 0x20000268 8009594: 20000274 .word 0x20000274 08009598 : ADC_HandleTypeDef hadc1; DMA_HandleTypeDef hdma_adc1; /* ADC1 init function */ void MX_ADC1_Init(void) { 8009598: b580 push {r7, lr} 800959a: b084 sub sp, #16 800959c: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 800959e: 1d3b adds r3, r7, #4 80095a0: 2200 movs r2, #0 80095a2: 601a str r2, [r3, #0] 80095a4: 605a str r2, [r3, #4] 80095a6: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 80095a8: 4b3c ldr r3, [pc, #240] @ (800969c ) 80095aa: 4a3d ldr r2, [pc, #244] @ (80096a0 ) 80095ac: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 80095ae: 4b3b ldr r3, [pc, #236] @ (800969c ) 80095b0: f44f 7280 mov.w r2, #256 @ 0x100 80095b4: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = DISABLE; 80095b6: 4b39 ldr r3, [pc, #228] @ (800969c ) 80095b8: 2200 movs r2, #0 80095ba: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 80095bc: 4b37 ldr r3, [pc, #220] @ (800969c ) 80095be: 2200 movs r2, #0 80095c0: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T3_TRGO; 80095c2: 4b36 ldr r3, [pc, #216] @ (800969c ) 80095c4: f44f 2200 mov.w r2, #524288 @ 0x80000 80095c8: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80095ca: 4b34 ldr r3, [pc, #208] @ (800969c ) 80095cc: 2200 movs r2, #0 80095ce: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 6; 80095d0: 4b32 ldr r3, [pc, #200] @ (800969c ) 80095d2: 2206 movs r2, #6 80095d4: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 80095d6: 4831 ldr r0, [pc, #196] @ (800969c ) 80095d8: f004 fbac bl 800dd34 80095dc: 4603 mov r3, r0 80095de: 2b00 cmp r3, #0 80095e0: d001 beq.n 80095e6 { Error_Handler(); 80095e2: f001 fa1f bl 800aa24 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 80095e6: 2303 movs r3, #3 80095e8: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 80095ea: 2301 movs r3, #1 80095ec: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_41CYCLES_5; 80095ee: 2304 movs r3, #4 80095f0: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80095f2: 1d3b adds r3, r7, #4 80095f4: 4619 mov r1, r3 80095f6: 4829 ldr r0, [pc, #164] @ (800969c ) 80095f8: f004 fe2c bl 800e254 80095fc: 4603 mov r3, r0 80095fe: 2b00 cmp r3, #0 8009600: d001 beq.n 8009606 { Error_Handler(); 8009602: f001 fa0f bl 800aa24 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8009606: 2304 movs r3, #4 8009608: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 800960a: 2302 movs r3, #2 800960c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800960e: 1d3b adds r3, r7, #4 8009610: 4619 mov r1, r3 8009612: 4822 ldr r0, [pc, #136] @ (800969c ) 8009614: f004 fe1e bl 800e254 8009618: 4603 mov r3, r0 800961a: 2b00 cmp r3, #0 800961c: d001 beq.n 8009622 { Error_Handler(); 800961e: f001 fa01 bl 800aa24 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8009622: 2308 movs r3, #8 8009624: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8009626: 2303 movs r3, #3 8009628: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800962a: 1d3b adds r3, r7, #4 800962c: 4619 mov r1, r3 800962e: 481b ldr r0, [pc, #108] @ (800969c ) 8009630: f004 fe10 bl 800e254 8009634: 4603 mov r3, r0 8009636: 2b00 cmp r3, #0 8009638: d001 beq.n 800963e { Error_Handler(); 800963a: f001 f9f3 bl 800aa24 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_9; 800963e: 2309 movs r3, #9 8009640: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_4; 8009642: 2304 movs r3, #4 8009644: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8009646: 1d3b adds r3, r7, #4 8009648: 4619 mov r1, r3 800964a: 4814 ldr r0, [pc, #80] @ (800969c ) 800964c: f004 fe02 bl 800e254 8009650: 4603 mov r3, r0 8009652: 2b00 cmp r3, #0 8009654: d001 beq.n 800965a { Error_Handler(); 8009656: f001 f9e5 bl 800aa24 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; 800965a: 2310 movs r3, #16 800965c: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_5; 800965e: 2305 movs r3, #5 8009660: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8009662: 1d3b adds r3, r7, #4 8009664: 4619 mov r1, r3 8009666: 480d ldr r0, [pc, #52] @ (800969c ) 8009668: f004 fdf4 bl 800e254 800966c: 4603 mov r3, r0 800966e: 2b00 cmp r3, #0 8009670: d001 beq.n 8009676 { Error_Handler(); 8009672: f001 f9d7 bl 800aa24 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; 8009676: 2311 movs r3, #17 8009678: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_6; 800967a: 2306 movs r3, #6 800967c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800967e: 1d3b adds r3, r7, #4 8009680: 4619 mov r1, r3 8009682: 4806 ldr r0, [pc, #24] @ (800969c ) 8009684: f004 fde6 bl 800e254 8009688: 4603 mov r3, r0 800968a: 2b00 cmp r3, #0 800968c: d001 beq.n 8009692 { Error_Handler(); 800968e: f001 f9c9 bl 800aa24 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 8009692: bf00 nop 8009694: 3710 adds r7, #16 8009696: 46bd mov sp, r7 8009698: bd80 pop {r7, pc} 800969a: bf00 nop 800969c: 20000278 .word 0x20000278 80096a0: 40012400 .word 0x40012400 080096a4 : void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 80096a4: b580 push {r7, lr} 80096a6: b08a sub sp, #40 @ 0x28 80096a8: af00 add r7, sp, #0 80096aa: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80096ac: f107 0318 add.w r3, r7, #24 80096b0: 2200 movs r2, #0 80096b2: 601a str r2, [r3, #0] 80096b4: 605a str r2, [r3, #4] 80096b6: 609a str r2, [r3, #8] 80096b8: 60da str r2, [r3, #12] if(adcHandle->Instance==ADC1) 80096ba: 687b ldr r3, [r7, #4] 80096bc: 681b ldr r3, [r3, #0] 80096be: 4a38 ldr r2, [pc, #224] @ (80097a0 ) 80096c0: 4293 cmp r3, r2 80096c2: d168 bne.n 8009796 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 80096c4: 4b37 ldr r3, [pc, #220] @ (80097a4 ) 80096c6: 699b ldr r3, [r3, #24] 80096c8: 4a36 ldr r2, [pc, #216] @ (80097a4 ) 80096ca: f443 7300 orr.w r3, r3, #512 @ 0x200 80096ce: 6193 str r3, [r2, #24] 80096d0: 4b34 ldr r3, [pc, #208] @ (80097a4 ) 80096d2: 699b ldr r3, [r3, #24] 80096d4: f403 7300 and.w r3, r3, #512 @ 0x200 80096d8: 617b str r3, [r7, #20] 80096da: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 80096dc: 4b31 ldr r3, [pc, #196] @ (80097a4 ) 80096de: 699b ldr r3, [r3, #24] 80096e0: 4a30 ldr r2, [pc, #192] @ (80097a4 ) 80096e2: f043 0304 orr.w r3, r3, #4 80096e6: 6193 str r3, [r2, #24] 80096e8: 4b2e ldr r3, [pc, #184] @ (80097a4 ) 80096ea: 699b ldr r3, [r3, #24] 80096ec: f003 0304 and.w r3, r3, #4 80096f0: 613b str r3, [r7, #16] 80096f2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80096f4: 4b2b ldr r3, [pc, #172] @ (80097a4 ) 80096f6: 699b ldr r3, [r3, #24] 80096f8: 4a2a ldr r2, [pc, #168] @ (80097a4 ) 80096fa: f043 0308 orr.w r3, r3, #8 80096fe: 6193 str r3, [r2, #24] 8009700: 4b28 ldr r3, [pc, #160] @ (80097a4 ) 8009702: 699b ldr r3, [r3, #24] 8009704: f003 0308 and.w r3, r3, #8 8009708: 60fb str r3, [r7, #12] 800970a: 68fb ldr r3, [r7, #12] PA3 ------> ADC1_IN3 PA4 ------> ADC1_IN4 PB0 ------> ADC1_IN8 PB1 ------> ADC1_IN9 */ GPIO_InitStruct.Pin = GPIO_PIN_3|CP_ADC_Pin; 800970c: 2318 movs r3, #24 800970e: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009710: 2303 movs r3, #3 8009712: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8009714: f107 0318 add.w r3, r7, #24 8009718: 4619 mov r1, r3 800971a: 4823 ldr r0, [pc, #140] @ (80097a8 ) 800971c: f006 fd00 bl 8010120 GPIO_InitStruct.Pin = ADC_NTC1_Pin|ADC_NTC2_Pin; 8009720: 2303 movs r3, #3 8009722: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009724: 2303 movs r3, #3 8009726: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009728: f107 0318 add.w r3, r7, #24 800972c: 4619 mov r1, r3 800972e: 481f ldr r0, [pc, #124] @ (80097ac ) 8009730: f006 fcf6 bl 8010120 /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; 8009734: 4b1e ldr r3, [pc, #120] @ (80097b0 ) 8009736: 4a1f ldr r2, [pc, #124] @ (80097b4 ) 8009738: 601a str r2, [r3, #0] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 800973a: 4b1d ldr r3, [pc, #116] @ (80097b0 ) 800973c: 2200 movs r2, #0 800973e: 605a str r2, [r3, #4] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8009740: 4b1b ldr r3, [pc, #108] @ (80097b0 ) 8009742: 2200 movs r2, #0 8009744: 609a str r2, [r3, #8] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8009746: 4b1a ldr r3, [pc, #104] @ (80097b0 ) 8009748: 2280 movs r2, #128 @ 0x80 800974a: 60da str r2, [r3, #12] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 800974c: 4b18 ldr r3, [pc, #96] @ (80097b0 ) 800974e: f44f 7280 mov.w r2, #256 @ 0x100 8009752: 611a str r2, [r3, #16] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8009754: 4b16 ldr r3, [pc, #88] @ (80097b0 ) 8009756: f44f 6280 mov.w r2, #1024 @ 0x400 800975a: 615a str r2, [r3, #20] hdma_adc1.Init.Mode = DMA_CIRCULAR; 800975c: 4b14 ldr r3, [pc, #80] @ (80097b0 ) 800975e: 2220 movs r2, #32 8009760: 619a str r2, [r3, #24] hdma_adc1.Init.Priority = DMA_PRIORITY_HIGH; 8009762: 4b13 ldr r3, [pc, #76] @ (80097b0 ) 8009764: f44f 5200 mov.w r2, #8192 @ 0x2000 8009768: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 800976a: 4811 ldr r0, [pc, #68] @ (80097b0 ) 800976c: f006 f854 bl 800f818 8009770: 4603 mov r3, r0 8009772: 2b00 cmp r3, #0 8009774: d001 beq.n 800977a { Error_Handler(); 8009776: f001 f955 bl 800aa24 } __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1); 800977a: 687b ldr r3, [r7, #4] 800977c: 4a0c ldr r2, [pc, #48] @ (80097b0 ) 800977e: 621a str r2, [r3, #32] 8009780: 4a0b ldr r2, [pc, #44] @ (80097b0 ) 8009782: 687b ldr r3, [r7, #4] 8009784: 6253 str r3, [r2, #36] @ 0x24 /* ADC1 interrupt Init */ HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0); 8009786: 2200 movs r2, #0 8009788: 2100 movs r1, #0 800978a: 2012 movs r0, #18 800978c: f005 ffe3 bl 800f756 HAL_NVIC_EnableIRQ(ADC1_2_IRQn); 8009790: 2012 movs r0, #18 8009792: f005 fffc bl 800f78e /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8009796: bf00 nop 8009798: 3728 adds r7, #40 @ 0x28 800979a: 46bd mov sp, r7 800979c: bd80 pop {r7, pc} 800979e: bf00 nop 80097a0: 40012400 .word 0x40012400 80097a4: 40021000 .word 0x40021000 80097a8: 40010800 .word 0x40010800 80097ac: 40010c00 .word 0x40010c00 80097b0: 200002a8 .word 0x200002a8 80097b4: 40020008 .word 0x40020008 080097b8 : uint8_t RELAY_State[RELAY_COUNT]; static volatile uint8_t adc_lock = 0; static SMAFilter_t conn_temp_adc_filter[2]; void RELAY_Write(relay_t num, uint8_t state){ 80097b8: b580 push {r7, lr} 80097ba: b082 sub sp, #8 80097bc: af00 add r7, sp, #0 80097be: 4603 mov r3, r0 80097c0: 460a mov r2, r1 80097c2: 71fb strb r3, [r7, #7] 80097c4: 4613 mov r3, r2 80097c6: 71bb strb r3, [r7, #6] switch (num) { 80097c8: 79fb ldrb r3, [r7, #7] 80097ca: 2b07 cmp r3, #7 80097cc: d850 bhi.n 8009870 80097ce: a201 add r2, pc, #4 @ (adr r2, 80097d4 ) 80097d0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80097d4: 080097f5 .word 0x080097f5 80097d8: 08009805 .word 0x08009805 80097dc: 08009815 .word 0x08009815 80097e0: 08009825 .word 0x08009825 80097e4: 08009835 .word 0x08009835 80097e8: 08009845 .word 0x08009845 80097ec: 08009853 .word 0x08009853 80097f0: 08009863 .word 0x08009863 case RELAY_AUX0: HAL_GPIO_WritePin(RELAY1_GPIO_Port, RELAY1_Pin, state); 80097f4: 79bb ldrb r3, [r7, #6] 80097f6: 461a mov r2, r3 80097f8: f44f 7180 mov.w r1, #256 @ 0x100 80097fc: 4821 ldr r0, [pc, #132] @ (8009884 ) 80097fe: f006 fee6 bl 80105ce break; 8009802: e036 b.n 8009872 case RELAY_AUX1: HAL_GPIO_WritePin(RELAY2_GPIO_Port, RELAY2_Pin, state); 8009804: 79bb ldrb r3, [r7, #6] 8009806: 461a mov r2, r3 8009808: f44f 7100 mov.w r1, #512 @ 0x200 800980c: 481d ldr r0, [pc, #116] @ (8009884 ) 800980e: f006 fede bl 80105ce break; 8009812: e02e b.n 8009872 case RELAY3: HAL_GPIO_WritePin(RELAY3_GPIO_Port, RELAY3_Pin, state); 8009814: 79bb ldrb r3, [r7, #6] 8009816: 461a mov r2, r3 8009818: f44f 6180 mov.w r1, #1024 @ 0x400 800981c: 4819 ldr r0, [pc, #100] @ (8009884 ) 800981e: f006 fed6 bl 80105ce break; 8009822: e026 b.n 8009872 case RELAY_DC: HAL_GPIO_WritePin(RELAY4_GPIO_Port, RELAY4_Pin, state); 8009824: 79bb ldrb r3, [r7, #6] 8009826: 461a mov r2, r3 8009828: f44f 6100 mov.w r1, #2048 @ 0x800 800982c: 4815 ldr r0, [pc, #84] @ (8009884 ) 800982e: f006 fece bl 80105ce break; 8009832: e01e b.n 8009872 case RELAY_AC: HAL_GPIO_WritePin(RELAY5_GPIO_Port, RELAY5_Pin, state); 8009834: 79bb ldrb r3, [r7, #6] 8009836: 461a mov r2, r3 8009838: f44f 5180 mov.w r1, #4096 @ 0x1000 800983c: 4811 ldr r0, [pc, #68] @ (8009884 ) 800983e: f006 fec6 bl 80105ce break; 8009842: e016 b.n 8009872 case RELAY_CP: HAL_GPIO_WritePin(RELAY_CP_GPIO_Port, RELAY_CP_Pin, state); 8009844: 79bb ldrb r3, [r7, #6] 8009846: 461a mov r2, r3 8009848: 2108 movs r1, #8 800984a: 480f ldr r0, [pc, #60] @ (8009888 ) 800984c: f006 febf bl 80105ce break; 8009850: e00f b.n 8009872 case RELAY_CC: HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, state); 8009852: 79bb ldrb r3, [r7, #6] 8009854: 461a mov r2, r3 8009856: f44f 4100 mov.w r1, #32768 @ 0x8000 800985a: 480c ldr r0, [pc, #48] @ (800988c ) 800985c: f006 feb7 bl 80105ce break; 8009860: e007 b.n 8009872 case RELAY_DC1: HAL_GPIO_WritePin(RELAY_DC_GPIO_Port, RELAY_DC_Pin, state); 8009862: 79bb ldrb r3, [r7, #6] 8009864: 461a mov r2, r3 8009866: 2108 movs r1, #8 8009868: 4809 ldr r0, [pc, #36] @ (8009890 ) 800986a: f006 feb0 bl 80105ce break; 800986e: e000 b.n 8009872 default: break; 8009870: bf00 nop } RELAY_State[num] = state; 8009872: 79fb ldrb r3, [r7, #7] 8009874: 4907 ldr r1, [pc, #28] @ (8009894 ) 8009876: 79ba ldrb r2, [r7, #6] 8009878: 54ca strb r2, [r1, r3] } 800987a: bf00 nop 800987c: 3708 adds r7, #8 800987e: 46bd mov sp, r7 8009880: bd80 pop {r7, pc} 8009882: bf00 nop 8009884: 40011800 .word 0x40011800 8009888: 40011000 .word 0x40011000 800988c: 40010800 .word 0x40010800 8009890: 40011400 .word 0x40011400 8009894: 200002ec .word 0x200002ec 08009898 : uint8_t RELAY_Read(relay_t num){ 8009898: b480 push {r7} 800989a: b083 sub sp, #12 800989c: af00 add r7, sp, #0 800989e: 4603 mov r3, r0 80098a0: 71fb strb r3, [r7, #7] return RELAY_State[num]; 80098a2: 79fb ldrb r3, [r7, #7] 80098a4: 4a03 ldr r2, [pc, #12] @ (80098b4 ) 80098a6: 5cd3 ldrb r3, [r2, r3] } 80098a8: 4618 mov r0, r3 80098aa: 370c adds r7, #12 80098ac: 46bd mov sp, r7 80098ae: bc80 pop {r7} 80098b0: 4770 bx lr 80098b2: bf00 nop 80098b4: 200002ec .word 0x200002ec 080098b8 : uint8_t IN_ReadInput(inputNum_t input_n){ 80098b8: b580 push {r7, lr} 80098ba: b082 sub sp, #8 80098bc: af00 add r7, sp, #0 80098be: 4603 mov r3, r0 80098c0: 71fb strb r3, [r7, #7] switch(input_n){ 80098c2: 79fb ldrb r3, [r7, #7] 80098c4: 2b06 cmp r3, #6 80098c6: d83b bhi.n 8009940 80098c8: a201 add r2, pc, #4 @ (adr r2, 80098d0 ) 80098ca: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80098ce: bf00 nop 80098d0: 080098ed .word 0x080098ed 80098d4: 080098f9 .word 0x080098f9 80098d8: 08009905 .word 0x08009905 80098dc: 08009911 .word 0x08009911 80098e0: 0800991d .word 0x0800991d 80098e4: 08009929 .word 0x08009929 80098e8: 08009935 .word 0x08009935 case IN_SW0: return HAL_GPIO_ReadPin(IN_SW0_GPIO_Port, IN_SW0_Pin); 80098ec: 2102 movs r1, #2 80098ee: 4817 ldr r0, [pc, #92] @ (800994c ) 80098f0: f006 fe56 bl 80105a0 80098f4: 4603 mov r3, r0 80098f6: e024 b.n 8009942 case IN_SW1: return HAL_GPIO_ReadPin(IN_SW1_GPIO_Port, IN_SW1_Pin); 80098f8: 2104 movs r1, #4 80098fa: 4814 ldr r0, [pc, #80] @ (800994c ) 80098fc: f006 fe50 bl 80105a0 8009900: 4603 mov r3, r0 8009902: e01e b.n 8009942 case IN0: return HAL_GPIO_ReadPin(IN0_GPIO_Port, IN0_Pin); 8009904: 2180 movs r1, #128 @ 0x80 8009906: 4812 ldr r0, [pc, #72] @ (8009950 ) 8009908: f006 fe4a bl 80105a0 800990c: 4603 mov r3, r0 800990e: e018 b.n 8009942 case IN_ESTOP: return HAL_GPIO_ReadPin(IN_ESTOP_GPIO_Port, IN_ESTOP_Pin); 8009910: 2180 movs r1, #128 @ 0x80 8009912: 4810 ldr r0, [pc, #64] @ (8009954 ) 8009914: f006 fe44 bl 80105a0 8009918: 4603 mov r3, r0 800991a: e012 b.n 8009942 case IN_FB1: return HAL_GPIO_ReadPin(IN_FB1_GPIO_Port, IN_FB1_Pin); 800991c: 2110 movs r1, #16 800991e: 480e ldr r0, [pc, #56] @ (8009958 ) 8009920: f006 fe3e bl 80105a0 8009924: 4603 mov r3, r0 8009926: e00c b.n 8009942 case IN_CONT_FB_DC: return HAL_GPIO_ReadPin(IN_FB2_GPIO_Port, IN_FB2_Pin); 8009928: 2108 movs r1, #8 800992a: 480b ldr r0, [pc, #44] @ (8009958 ) 800992c: f006 fe38 bl 80105a0 8009930: 4603 mov r3, r0 8009932: e006 b.n 8009942 case ISO_IN: return HAL_GPIO_ReadPin(ISO_IN_GPIO_Port, ISO_IN_Pin); 8009934: 2102 movs r1, #2 8009936: 4806 ldr r0, [pc, #24] @ (8009950 ) 8009938: f006 fe32 bl 80105a0 800993c: 4603 mov r3, r0 800993e: e000 b.n 8009942 default: return 0; 8009940: 2300 movs r3, #0 } } 8009942: 4618 mov r0, r3 8009944: 3708 adds r7, #8 8009946: 46bd mov sp, r7 8009948: bd80 pop {r7, pc} 800994a: bf00 nop 800994c: 40010800 .word 0x40010800 8009950: 40011800 .word 0x40011800 8009954: 40011400 .word 0x40011400 8009958: 40010c00 .word 0x40010c00 0800995c : // // HAL_ADC_Stop(&hadc1); // stop adc return 0; } void Init_Peripheral(){ 800995c: b580 push {r7, lr} 800995e: af00 add r7, sp, #0 HAL_ADCEx_Calibration_Start(&hadc1); 8009960: 4816 ldr r0, [pc, #88] @ (80099bc ) 8009962: f004 fe71 bl 800e648 ADC_ScanStart(); 8009966: f7ff fddf bl 8009528 RELAY_Write(RELAY_AUX0, 0); 800996a: 2100 movs r1, #0 800996c: 2000 movs r0, #0 800996e: f7ff ff23 bl 80097b8 RELAY_Write(RELAY_AUX1, 0); 8009972: 2100 movs r1, #0 8009974: 2001 movs r0, #1 8009976: f7ff ff1f bl 80097b8 RELAY_Write(RELAY3, 0); 800997a: 2100 movs r1, #0 800997c: 2002 movs r0, #2 800997e: f7ff ff1b bl 80097b8 RELAY_Write(RELAY_DC, 0); 8009982: 2100 movs r1, #0 8009984: 2003 movs r0, #3 8009986: f7ff ff17 bl 80097b8 RELAY_Write(RELAY_AC, 0); 800998a: 2100 movs r1, #0 800998c: 2004 movs r0, #4 800998e: f7ff ff13 bl 80097b8 RELAY_Write(RELAY_CP, 1); 8009992: 2101 movs r1, #1 8009994: 2005 movs r0, #5 8009996: f7ff ff0f bl 80097b8 RELAY_Write(RELAY_CC, 1); 800999a: 2101 movs r1, #1 800999c: 2006 movs r0, #6 800999e: f7ff ff0b bl 80097b8 RELAY_Write(RELAY_DC1, 0); 80099a2: 2100 movs r1, #0 80099a4: 2007 movs r0, #7 80099a6: f7ff ff07 bl 80097b8 SMAFilter_Init(&conn_temp_adc_filter[0]); 80099aa: 4805 ldr r0, [pc, #20] @ (80099c0 ) 80099ac: f003 faac bl 800cf08 SMAFilter_Init(&conn_temp_adc_filter[1]); 80099b0: 4804 ldr r0, [pc, #16] @ (80099c4 ) 80099b2: f003 faa9 bl 800cf08 } 80099b6: bf00 nop 80099b8: bd80 pop {r7, pc} 80099ba: bf00 nop 80099bc: 20000278 .word 0x20000278 80099c0: 200002f4 .word 0x200002f4 80099c4: 2000031c .word 0x2000031c 080099c8 : float pt1000_to_temperature(float resistance) { 80099c8: b590 push {r4, r7, lr} 80099ca: b087 sub sp, #28 80099cc: af00 add r7, sp, #0 80099ce: 6078 str r0, [r7, #4] // Константы для PT1000 const float R0 = 1000.0; // Сопротивление при 0 °C 80099d0: 4b0c ldr r3, [pc, #48] @ (8009a04 ) 80099d2: 617b str r3, [r7, #20] const float C_A = 3.9083E-3f; 80099d4: 4b0c ldr r3, [pc, #48] @ (8009a08 ) 80099d6: 613b str r3, [r7, #16] float temperature = (resistance-R0) / ( R0 * C_A); 80099d8: 6979 ldr r1, [r7, #20] 80099da: 6878 ldr r0, [r7, #4] 80099dc: f7ff f914 bl 8008c08 <__aeabi_fsub> 80099e0: 4603 mov r3, r0 80099e2: 461c mov r4, r3 80099e4: 6939 ldr r1, [r7, #16] 80099e6: 6978 ldr r0, [r7, #20] 80099e8: f7ff fa18 bl 8008e1c <__aeabi_fmul> 80099ec: 4603 mov r3, r0 80099ee: 4619 mov r1, r3 80099f0: 4620 mov r0, r4 80099f2: f7ff fac7 bl 8008f84 <__aeabi_fdiv> 80099f6: 4603 mov r3, r0 80099f8: 60fb str r3, [r7, #12] return temperature; 80099fa: 68fb ldr r3, [r7, #12] } 80099fc: 4618 mov r0, r3 80099fe: 371c adds r7, #28 8009a00: 46bd mov sp, r7 8009a02: bd90 pop {r4, r7, pc} 8009a04: 447a0000 .word 0x447a0000 8009a08: 3b801132 .word 0x3b801132 8009a0c: 00000000 .word 0x00000000 08009a10 : float calculate_NTC_resistance(int adc_value, float Vref, float Vin, float R) { 8009a10: b5b0 push {r4, r5, r7, lr} 8009a12: b086 sub sp, #24 8009a14: af00 add r7, sp, #0 8009a16: 60f8 str r0, [r7, #12] 8009a18: 60b9 str r1, [r7, #8] 8009a1a: 607a str r2, [r7, #4] 8009a1c: 603b str r3, [r7, #0] // Преобразуем значение АЦП в выходное напряжение float Vout = (adc_value / 4095.0) * Vref; 8009a1e: 68f8 ldr r0, [r7, #12] 8009a20: f7fe fd5c bl 80084dc <__aeabi_i2d> 8009a24: a31c add r3, pc, #112 @ (adr r3, 8009a98 ) 8009a26: e9d3 2300 ldrd r2, r3, [r3] 8009a2a: f7fe feeb bl 8008804 <__aeabi_ddiv> 8009a2e: 4602 mov r2, r0 8009a30: 460b mov r3, r1 8009a32: 4614 mov r4, r2 8009a34: 461d mov r5, r3 8009a36: 68b8 ldr r0, [r7, #8] 8009a38: f7fe fd62 bl 8008500 <__aeabi_f2d> 8009a3c: 4602 mov r2, r0 8009a3e: 460b mov r3, r1 8009a40: 4620 mov r0, r4 8009a42: 4629 mov r1, r5 8009a44: f7fe fdb4 bl 80085b0 <__aeabi_dmul> 8009a48: 4602 mov r2, r0 8009a4a: 460b mov r3, r1 8009a4c: 4610 mov r0, r2 8009a4e: 4619 mov r1, r3 8009a50: f7ff f886 bl 8008b60 <__aeabi_d2f> 8009a54: 4603 mov r3, r0 8009a56: 617b str r3, [r7, #20] // Проверяем, чтобы Vout не было равно Vin if (Vout >= Vin) { 8009a58: 6879 ldr r1, [r7, #4] 8009a5a: 6978 ldr r0, [r7, #20] 8009a5c: f7ff fb90 bl 8009180 <__aeabi_fcmpge> 8009a60: 4603 mov r3, r0 8009a62: 2b00 cmp r3, #0 8009a64: d001 beq.n 8009a6a return -1; // Ошибка: Vout не может быть больше или равно Vin 8009a66: 4b0e ldr r3, [pc, #56] @ (8009aa0 ) 8009a68: e010 b.n 8009a8c } // Вычисляем сопротивление термистора float R_NTC = R * (Vout / (Vin - Vout)); 8009a6a: 6979 ldr r1, [r7, #20] 8009a6c: 6878 ldr r0, [r7, #4] 8009a6e: f7ff f8cb bl 8008c08 <__aeabi_fsub> 8009a72: 4603 mov r3, r0 8009a74: 4619 mov r1, r3 8009a76: 6978 ldr r0, [r7, #20] 8009a78: f7ff fa84 bl 8008f84 <__aeabi_fdiv> 8009a7c: 4603 mov r3, r0 8009a7e: 4619 mov r1, r3 8009a80: 6838 ldr r0, [r7, #0] 8009a82: f7ff f9cb bl 8008e1c <__aeabi_fmul> 8009a86: 4603 mov r3, r0 8009a88: 613b str r3, [r7, #16] return R_NTC; 8009a8a: 693b ldr r3, [r7, #16] } 8009a8c: 4618 mov r0, r3 8009a8e: 3718 adds r7, #24 8009a90: 46bd mov sp, r7 8009a92: bdb0 pop {r4, r5, r7, pc} 8009a94: f3af 8000 nop.w 8009a98: 00000000 .word 0x00000000 8009a9c: 40affe00 .word 0x40affe00 8009aa0: bf800000 .word 0xbf800000 08009aa4 : int16_t CONN_ReadTemp(uint8_t ch){ 8009aa4: b580 push {r7, lr} 8009aa6: b088 sub sp, #32 8009aa8: af00 add r7, sp, #0 8009aaa: 4603 mov r3, r0 8009aac: 71fb strb r3, [r7, #7] uint32_t adcValue = 0u; 8009aae: 2300 movs r3, #0 8009ab0: 61fb str r3, [r7, #28] adcValue = ch ? adc_data.ntc2_raw : adc_data.ntc1_raw; 8009ab2: 79fb ldrb r3, [r7, #7] 8009ab4: 2b00 cmp r3, #0 8009ab6: d003 beq.n 8009ac0 8009ab8: 4b1c ldr r3, [pc, #112] @ (8009b2c ) 8009aba: 88db ldrh r3, [r3, #6] 8009abc: b29b uxth r3, r3 8009abe: e002 b.n 8009ac6 8009ac0: 4b1a ldr r3, [pc, #104] @ (8009b2c ) 8009ac2: 889b ldrh r3, [r3, #4] 8009ac4: b29b uxth r3, r3 8009ac6: 61fb str r3, [r7, #28] int32_t adc_filtered = SMAFilter_Update(&conn_temp_adc_filter[ch ? 1u : 0u], (int32_t)adcValue); 8009ac8: 79fb ldrb r3, [r7, #7] 8009aca: 2b00 cmp r3, #0 8009acc: d001 beq.n 8009ad2 8009ace: 2201 movs r2, #1 8009ad0: e000 b.n 8009ad4 8009ad2: 2200 movs r2, #0 8009ad4: 4613 mov r3, r2 8009ad6: 009b lsls r3, r3, #2 8009ad8: 4413 add r3, r2 8009ada: 00db lsls r3, r3, #3 8009adc: 4a14 ldr r2, [pc, #80] @ (8009b30 ) 8009ade: 4413 add r3, r2 8009ae0: 69fa ldr r2, [r7, #28] 8009ae2: 4611 mov r1, r2 8009ae4: 4618 mov r0, r3 8009ae6: f003 fa34 bl 800cf52 8009aea: 61b8 str r0, [r7, #24] if((uint32_t)adc_filtered > 4000u) { 8009aec: 69bb ldr r3, [r7, #24] 8009aee: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 8009af2: d901 bls.n 8009af8 return 20; //Термодатчик не подключен 8009af4: 2314 movs r3, #20 8009af6: e015 b.n 8009b24 } // int adc_value = 2048; // Пример значения АЦП float Vref = 3.3; // Напряжение опорное 8009af8: 4b0e ldr r3, [pc, #56] @ (8009b34 ) 8009afa: 617b str r3, [r7, #20] float Vin = 5.0; // Входное напряжение 8009afc: 4b0e ldr r3, [pc, #56] @ (8009b38 ) 8009afe: 613b str r3, [r7, #16] float R = 1000; // Сопротивление резистора в Омах 8009b00: 4b0e ldr r3, [pc, #56] @ (8009b3c ) 8009b02: 60fb str r3, [r7, #12] float temp = pt1000_to_temperature(calculate_NTC_resistance((int)adc_filtered, Vref, Vin, R)); 8009b04: 68fb ldr r3, [r7, #12] 8009b06: 693a ldr r2, [r7, #16] 8009b08: 6979 ldr r1, [r7, #20] 8009b0a: 69b8 ldr r0, [r7, #24] 8009b0c: f7ff ff80 bl 8009a10 8009b10: 4603 mov r3, r0 8009b12: 4618 mov r0, r3 8009b14: f7ff ff58 bl 80099c8 8009b18: 60b8 str r0, [r7, #8] return (int16_t)temp; 8009b1a: 68b8 ldr r0, [r7, #8] 8009b1c: f7ff fb44 bl 80091a8 <__aeabi_f2iz> 8009b20: 4603 mov r3, r0 8009b22: b21b sxth r3, r3 } 8009b24: 4618 mov r0, r3 8009b26: 3720 adds r7, #32 8009b28: 46bd mov sp, r7 8009b2a: bd80 pop {r7, pc} 8009b2c: 20000268 .word 0x20000268 8009b30: 200002f4 .word 0x200002f4 8009b34: 40533333 .word 0x40533333 8009b38: 40a00000 .word 0x40a00000 8009b3c: 447a0000 .word 0x447a0000 08009b40 : CAN_HandleTypeDef hcan1; CAN_HandleTypeDef hcan2; /* CAN1 init function */ void MX_CAN1_Init(void) { 8009b40: b580 push {r7, lr} 8009b42: af00 add r7, sp, #0 /* USER CODE END CAN1_Init 0 */ /* USER CODE BEGIN CAN1_Init 1 */ /* USER CODE END CAN1_Init 1 */ hcan1.Instance = CAN1; 8009b44: 4b17 ldr r3, [pc, #92] @ (8009ba4 ) 8009b46: 4a18 ldr r2, [pc, #96] @ (8009ba8 ) 8009b48: 601a str r2, [r3, #0] hcan1.Init.Prescaler = 8; 8009b4a: 4b16 ldr r3, [pc, #88] @ (8009ba4 ) 8009b4c: 2208 movs r2, #8 8009b4e: 605a str r2, [r3, #4] hcan1.Init.Mode = CAN_MODE_NORMAL; 8009b50: 4b14 ldr r3, [pc, #80] @ (8009ba4 ) 8009b52: 2200 movs r2, #0 8009b54: 609a str r2, [r3, #8] hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; 8009b56: 4b13 ldr r3, [pc, #76] @ (8009ba4 ) 8009b58: 2200 movs r2, #0 8009b5a: 60da str r2, [r3, #12] hcan1.Init.TimeSeg1 = CAN_BS1_15TQ; 8009b5c: 4b11 ldr r3, [pc, #68] @ (8009ba4 ) 8009b5e: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009b62: 611a str r2, [r3, #16] hcan1.Init.TimeSeg2 = CAN_BS2_2TQ; 8009b64: 4b0f ldr r3, [pc, #60] @ (8009ba4 ) 8009b66: f44f 1280 mov.w r2, #1048576 @ 0x100000 8009b6a: 615a str r2, [r3, #20] hcan1.Init.TimeTriggeredMode = DISABLE; 8009b6c: 4b0d ldr r3, [pc, #52] @ (8009ba4 ) 8009b6e: 2200 movs r2, #0 8009b70: 761a strb r2, [r3, #24] hcan1.Init.AutoBusOff = ENABLE; 8009b72: 4b0c ldr r3, [pc, #48] @ (8009ba4 ) 8009b74: 2201 movs r2, #1 8009b76: 765a strb r2, [r3, #25] hcan1.Init.AutoWakeUp = ENABLE; 8009b78: 4b0a ldr r3, [pc, #40] @ (8009ba4 ) 8009b7a: 2201 movs r2, #1 8009b7c: 769a strb r2, [r3, #26] hcan1.Init.AutoRetransmission = ENABLE; 8009b7e: 4b09 ldr r3, [pc, #36] @ (8009ba4 ) 8009b80: 2201 movs r2, #1 8009b82: 76da strb r2, [r3, #27] hcan1.Init.ReceiveFifoLocked = DISABLE; 8009b84: 4b07 ldr r3, [pc, #28] @ (8009ba4 ) 8009b86: 2200 movs r2, #0 8009b88: 771a strb r2, [r3, #28] hcan1.Init.TransmitFifoPriority = ENABLE; 8009b8a: 4b06 ldr r3, [pc, #24] @ (8009ba4 ) 8009b8c: 2201 movs r2, #1 8009b8e: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan1) != HAL_OK) 8009b90: 4804 ldr r0, [pc, #16] @ (8009ba4 ) 8009b92: f004 fe10 bl 800e7b6 8009b96: 4603 mov r3, r0 8009b98: 2b00 cmp r3, #0 8009b9a: d001 beq.n 8009ba0 { Error_Handler(); 8009b9c: f000 ff42 bl 800aa24 } /* USER CODE BEGIN CAN1_Init 2 */ /* USER CODE END CAN1_Init 2 */ } 8009ba0: bf00 nop 8009ba2: bd80 pop {r7, pc} 8009ba4: 20000344 .word 0x20000344 8009ba8: 40006400 .word 0x40006400 08009bac : /* CAN2 init function */ void MX_CAN2_Init(void) { 8009bac: b580 push {r7, lr} 8009bae: af00 add r7, sp, #0 /* USER CODE END CAN2_Init 0 */ /* USER CODE BEGIN CAN2_Init 1 */ /* USER CODE END CAN2_Init 1 */ hcan2.Instance = CAN2; 8009bb0: 4b17 ldr r3, [pc, #92] @ (8009c10 ) 8009bb2: 4a18 ldr r2, [pc, #96] @ (8009c14 ) 8009bb4: 601a str r2, [r3, #0] hcan2.Init.Prescaler = 16; 8009bb6: 4b16 ldr r3, [pc, #88] @ (8009c10 ) 8009bb8: 2210 movs r2, #16 8009bba: 605a str r2, [r3, #4] hcan2.Init.Mode = CAN_MODE_NORMAL; 8009bbc: 4b14 ldr r3, [pc, #80] @ (8009c10 ) 8009bbe: 2200 movs r2, #0 8009bc0: 609a str r2, [r3, #8] hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; 8009bc2: 4b13 ldr r3, [pc, #76] @ (8009c10 ) 8009bc4: 2200 movs r2, #0 8009bc6: 60da str r2, [r3, #12] hcan2.Init.TimeSeg1 = CAN_BS1_15TQ; 8009bc8: 4b11 ldr r3, [pc, #68] @ (8009c10 ) 8009bca: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009bce: 611a str r2, [r3, #16] hcan2.Init.TimeSeg2 = CAN_BS2_2TQ; 8009bd0: 4b0f ldr r3, [pc, #60] @ (8009c10 ) 8009bd2: f44f 1280 mov.w r2, #1048576 @ 0x100000 8009bd6: 615a str r2, [r3, #20] hcan2.Init.TimeTriggeredMode = DISABLE; 8009bd8: 4b0d ldr r3, [pc, #52] @ (8009c10 ) 8009bda: 2200 movs r2, #0 8009bdc: 761a strb r2, [r3, #24] hcan2.Init.AutoBusOff = ENABLE; 8009bde: 4b0c ldr r3, [pc, #48] @ (8009c10 ) 8009be0: 2201 movs r2, #1 8009be2: 765a strb r2, [r3, #25] hcan2.Init.AutoWakeUp = ENABLE; 8009be4: 4b0a ldr r3, [pc, #40] @ (8009c10 ) 8009be6: 2201 movs r2, #1 8009be8: 769a strb r2, [r3, #26] hcan2.Init.AutoRetransmission = ENABLE; 8009bea: 4b09 ldr r3, [pc, #36] @ (8009c10 ) 8009bec: 2201 movs r2, #1 8009bee: 76da strb r2, [r3, #27] hcan2.Init.ReceiveFifoLocked = DISABLE; 8009bf0: 4b07 ldr r3, [pc, #28] @ (8009c10 ) 8009bf2: 2200 movs r2, #0 8009bf4: 771a strb r2, [r3, #28] hcan2.Init.TransmitFifoPriority = ENABLE; 8009bf6: 4b06 ldr r3, [pc, #24] @ (8009c10 ) 8009bf8: 2201 movs r2, #1 8009bfa: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan2) != HAL_OK) 8009bfc: 4804 ldr r0, [pc, #16] @ (8009c10 ) 8009bfe: f004 fdda bl 800e7b6 8009c02: 4603 mov r3, r0 8009c04: 2b00 cmp r3, #0 8009c06: d001 beq.n 8009c0c { Error_Handler(); 8009c08: f000 ff0c bl 800aa24 } /* USER CODE BEGIN CAN2_Init 2 */ /* USER CODE END CAN2_Init 2 */ } 8009c0c: bf00 nop 8009c0e: bd80 pop {r7, pc} 8009c10: 2000036c .word 0x2000036c 8009c14: 40006800 .word 0x40006800 08009c18 : static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0; void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) { 8009c18: b580 push {r7, lr} 8009c1a: b08e sub sp, #56 @ 0x38 8009c1c: af00 add r7, sp, #0 8009c1e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8009c20: f107 0320 add.w r3, r7, #32 8009c24: 2200 movs r2, #0 8009c26: 601a str r2, [r3, #0] 8009c28: 605a str r2, [r3, #4] 8009c2a: 609a str r2, [r3, #8] 8009c2c: 60da str r2, [r3, #12] if(canHandle->Instance==CAN1) 8009c2e: 687b ldr r3, [r7, #4] 8009c30: 681b ldr r3, [r3, #0] 8009c32: 4a61 ldr r2, [pc, #388] @ (8009db8 ) 8009c34: 4293 cmp r3, r2 8009c36: d153 bne.n 8009ce0 { /* USER CODE BEGIN CAN1_MspInit 0 */ /* USER CODE END CAN1_MspInit 0 */ /* CAN1 clock enable */ HAL_RCC_CAN1_CLK_ENABLED++; 8009c38: 4b60 ldr r3, [pc, #384] @ (8009dbc ) 8009c3a: 681b ldr r3, [r3, #0] 8009c3c: 3301 adds r3, #1 8009c3e: 4a5f ldr r2, [pc, #380] @ (8009dbc ) 8009c40: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009c42: 4b5e ldr r3, [pc, #376] @ (8009dbc ) 8009c44: 681b ldr r3, [r3, #0] 8009c46: 2b01 cmp r3, #1 8009c48: d10b bne.n 8009c62 __HAL_RCC_CAN1_CLK_ENABLE(); 8009c4a: 4b5d ldr r3, [pc, #372] @ (8009dc0 ) 8009c4c: 69db ldr r3, [r3, #28] 8009c4e: 4a5c ldr r2, [pc, #368] @ (8009dc0 ) 8009c50: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009c54: 61d3 str r3, [r2, #28] 8009c56: 4b5a ldr r3, [pc, #360] @ (8009dc0 ) 8009c58: 69db ldr r3, [r3, #28] 8009c5a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009c5e: 61fb str r3, [r7, #28] 8009c60: 69fb ldr r3, [r7, #28] } __HAL_RCC_GPIOD_CLK_ENABLE(); 8009c62: 4b57 ldr r3, [pc, #348] @ (8009dc0 ) 8009c64: 699b ldr r3, [r3, #24] 8009c66: 4a56 ldr r2, [pc, #344] @ (8009dc0 ) 8009c68: f043 0320 orr.w r3, r3, #32 8009c6c: 6193 str r3, [r2, #24] 8009c6e: 4b54 ldr r3, [pc, #336] @ (8009dc0 ) 8009c70: 699b ldr r3, [r3, #24] 8009c72: f003 0320 and.w r3, r3, #32 8009c76: 61bb str r3, [r7, #24] 8009c78: 69bb ldr r3, [r7, #24] /**CAN1 GPIO Configuration PD0 ------> CAN1_RX PD1 ------> CAN1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0; 8009c7a: 2301 movs r3, #1 8009c7c: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009c7e: 2300 movs r3, #0 8009c80: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009c82: 2300 movs r3, #0 8009c84: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009c86: f107 0320 add.w r3, r7, #32 8009c8a: 4619 mov r1, r3 8009c8c: 484d ldr r0, [pc, #308] @ (8009dc4 ) 8009c8e: f006 fa47 bl 8010120 GPIO_InitStruct.Pin = GPIO_PIN_1; 8009c92: 2302 movs r3, #2 8009c94: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009c96: 2302 movs r3, #2 8009c98: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009c9a: 2303 movs r3, #3 8009c9c: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009c9e: f107 0320 add.w r3, r7, #32 8009ca2: 4619 mov r1, r3 8009ca4: 4847 ldr r0, [pc, #284] @ (8009dc4 ) 8009ca6: f006 fa3b bl 8010120 __HAL_AFIO_REMAP_CAN1_3(); 8009caa: 4b47 ldr r3, [pc, #284] @ (8009dc8 ) 8009cac: 685b ldr r3, [r3, #4] 8009cae: 633b str r3, [r7, #48] @ 0x30 8009cb0: 6b3b ldr r3, [r7, #48] @ 0x30 8009cb2: f423 43c0 bic.w r3, r3, #24576 @ 0x6000 8009cb6: 633b str r3, [r7, #48] @ 0x30 8009cb8: 6b3b ldr r3, [r7, #48] @ 0x30 8009cba: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009cbe: 633b str r3, [r7, #48] @ 0x30 8009cc0: 6b3b ldr r3, [r7, #48] @ 0x30 8009cc2: f443 43c0 orr.w r3, r3, #24576 @ 0x6000 8009cc6: 633b str r3, [r7, #48] @ 0x30 8009cc8: 4a3f ldr r2, [pc, #252] @ (8009dc8 ) 8009cca: 6b3b ldr r3, [r7, #48] @ 0x30 8009ccc: 6053 str r3, [r2, #4] /* CAN1 interrupt Init */ HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0); 8009cce: 2200 movs r2, #0 8009cd0: 2100 movs r1, #0 8009cd2: 2014 movs r0, #20 8009cd4: f005 fd3f bl 800f756 HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn); 8009cd8: 2014 movs r0, #20 8009cda: f005 fd58 bl 800f78e HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); /* USER CODE BEGIN CAN2_MspInit 1 */ /* USER CODE END CAN2_MspInit 1 */ } } 8009cde: e067 b.n 8009db0 else if(canHandle->Instance==CAN2) 8009ce0: 687b ldr r3, [r7, #4] 8009ce2: 681b ldr r3, [r3, #0] 8009ce4: 4a39 ldr r2, [pc, #228] @ (8009dcc ) 8009ce6: 4293 cmp r3, r2 8009ce8: d162 bne.n 8009db0 __HAL_RCC_CAN2_CLK_ENABLE(); 8009cea: 4b35 ldr r3, [pc, #212] @ (8009dc0 ) 8009cec: 69db ldr r3, [r3, #28] 8009cee: 4a34 ldr r2, [pc, #208] @ (8009dc0 ) 8009cf0: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 8009cf4: 61d3 str r3, [r2, #28] 8009cf6: 4b32 ldr r3, [pc, #200] @ (8009dc0 ) 8009cf8: 69db ldr r3, [r3, #28] 8009cfa: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8009cfe: 617b str r3, [r7, #20] 8009d00: 697b ldr r3, [r7, #20] HAL_RCC_CAN1_CLK_ENABLED++; 8009d02: 4b2e ldr r3, [pc, #184] @ (8009dbc ) 8009d04: 681b ldr r3, [r3, #0] 8009d06: 3301 adds r3, #1 8009d08: 4a2c ldr r2, [pc, #176] @ (8009dbc ) 8009d0a: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009d0c: 4b2b ldr r3, [pc, #172] @ (8009dbc ) 8009d0e: 681b ldr r3, [r3, #0] 8009d10: 2b01 cmp r3, #1 8009d12: d10b bne.n 8009d2c __HAL_RCC_CAN1_CLK_ENABLE(); 8009d14: 4b2a ldr r3, [pc, #168] @ (8009dc0 ) 8009d16: 69db ldr r3, [r3, #28] 8009d18: 4a29 ldr r2, [pc, #164] @ (8009dc0 ) 8009d1a: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009d1e: 61d3 str r3, [r2, #28] 8009d20: 4b27 ldr r3, [pc, #156] @ (8009dc0 ) 8009d22: 69db ldr r3, [r3, #28] 8009d24: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009d28: 613b str r3, [r7, #16] 8009d2a: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8009d2c: 4b24 ldr r3, [pc, #144] @ (8009dc0 ) 8009d2e: 699b ldr r3, [r3, #24] 8009d30: 4a23 ldr r2, [pc, #140] @ (8009dc0 ) 8009d32: f043 0308 orr.w r3, r3, #8 8009d36: 6193 str r3, [r2, #24] 8009d38: 4b21 ldr r3, [pc, #132] @ (8009dc0 ) 8009d3a: 699b ldr r3, [r3, #24] 8009d3c: f003 0308 and.w r3, r3, #8 8009d40: 60fb str r3, [r7, #12] 8009d42: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_5; 8009d44: 2320 movs r3, #32 8009d46: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009d48: 2300 movs r3, #0 8009d4a: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009d4c: 2300 movs r3, #0 8009d4e: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009d50: f107 0320 add.w r3, r7, #32 8009d54: 4619 mov r1, r3 8009d56: 481e ldr r0, [pc, #120] @ (8009dd0 ) 8009d58: f006 f9e2 bl 8010120 GPIO_InitStruct.Pin = GPIO_PIN_6; 8009d5c: 2340 movs r3, #64 @ 0x40 8009d5e: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009d60: 2302 movs r3, #2 8009d62: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009d64: 2303 movs r3, #3 8009d66: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009d68: f107 0320 add.w r3, r7, #32 8009d6c: 4619 mov r1, r3 8009d6e: 4818 ldr r0, [pc, #96] @ (8009dd0 ) 8009d70: f006 f9d6 bl 8010120 __HAL_AFIO_REMAP_CAN2_ENABLE(); 8009d74: 4b14 ldr r3, [pc, #80] @ (8009dc8 ) 8009d76: 685b ldr r3, [r3, #4] 8009d78: 637b str r3, [r7, #52] @ 0x34 8009d7a: 6b7b ldr r3, [r7, #52] @ 0x34 8009d7c: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009d80: 637b str r3, [r7, #52] @ 0x34 8009d82: 6b7b ldr r3, [r7, #52] @ 0x34 8009d84: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8009d88: 637b str r3, [r7, #52] @ 0x34 8009d8a: 4a0f ldr r2, [pc, #60] @ (8009dc8 ) 8009d8c: 6b7b ldr r3, [r7, #52] @ 0x34 8009d8e: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(CAN2_TX_IRQn, 0, 0); 8009d90: 2200 movs r2, #0 8009d92: 2100 movs r1, #0 8009d94: 203f movs r0, #63 @ 0x3f 8009d96: f005 fcde bl 800f756 HAL_NVIC_EnableIRQ(CAN2_TX_IRQn); 8009d9a: 203f movs r0, #63 @ 0x3f 8009d9c: f005 fcf7 bl 800f78e HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 0, 0); 8009da0: 2200 movs r2, #0 8009da2: 2100 movs r1, #0 8009da4: 2041 movs r0, #65 @ 0x41 8009da6: f005 fcd6 bl 800f756 HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); 8009daa: 2041 movs r0, #65 @ 0x41 8009dac: f005 fcef bl 800f78e } 8009db0: bf00 nop 8009db2: 3738 adds r7, #56 @ 0x38 8009db4: 46bd mov sp, r7 8009db6: bd80 pop {r7, pc} 8009db8: 40006400 .word 0x40006400 8009dbc: 20000394 .word 0x20000394 8009dc0: 40021000 .word 0x40021000 8009dc4: 40011400 .word 0x40011400 8009dc8: 40010000 .word 0x40010000 8009dcc: 40006800 .word 0x40006800 8009dd0: 40010c00 .word 0x40010c00 08009dd4 : ChargingConnector_t CONN; CONN_State_t connectorState; extern uint8_t config_initialized; void CONN_Init(){ 8009dd4: b480 push {r7} 8009dd6: af00 add r7, sp, #0 CONN.connControl = CMD_NONE; 8009dd8: 4b08 ldr r3, [pc, #32] @ (8009dfc ) 8009dda: 2200 movs r2, #0 8009ddc: 701a strb r2, [r3, #0] CONN.connState = Unknown; 8009dde: 4b07 ldr r3, [pc, #28] @ (8009dfc ) 8009de0: 2200 movs r2, #0 8009de2: 705a strb r2, [r3, #1] CONN.RequestedVoltage = PSU_MIN_VOLTAGE; 8009de4: 4b05 ldr r3, [pc, #20] @ (8009dfc ) 8009de6: 2200 movs r2, #0 8009de8: f062 0269 orn r2, r2, #105 @ 0x69 8009dec: 73da strb r2, [r3, #15] 8009dee: 2200 movs r2, #0 8009df0: 741a strb r2, [r3, #16] } 8009df2: bf00 nop 8009df4: 46bd mov sp, r7 8009df6: bc80 pop {r7} 8009df8: 4770 bx lr 8009dfa: bf00 nop 8009dfc: 20000398 .word 0x20000398 08009e00 : void CONN_Loop(){ 8009e00: b580 push {r7, lr} 8009e02: af00 add r7, sp, #0 static CONN_State_t last_connState = Unknown; if(last_connState != CONN.connState){ 8009e04: 4b1a ldr r3, [pc, #104] @ (8009e70 ) 8009e06: 785a ldrb r2, [r3, #1] 8009e08: 4b1a ldr r3, [pc, #104] @ (8009e74 ) 8009e0a: 781b ldrb r3, [r3, #0] 8009e0c: 429a cmp r2, r3 8009e0e: d006 beq.n 8009e1e last_connState = CONN.connState; 8009e10: 4b17 ldr r3, [pc, #92] @ (8009e70 ) 8009e12: 785a ldrb r2, [r3, #1] 8009e14: 4b17 ldr r3, [pc, #92] @ (8009e74 ) 8009e16: 701a strb r2, [r3, #0] CONN.connControl = CMD_NONE; 8009e18: 4b15 ldr r3, [pc, #84] @ (8009e70 ) 8009e1a: 2200 movs r2, #0 8009e1c: 701a strb r2, [r3, #0] } if(PSU0.cont_fault){ 8009e1e: 4b16 ldr r3, [pc, #88] @ (8009e78 ) 8009e20: 7b1b ldrb r3, [r3, #12] 8009e22: 2b00 cmp r3, #0 8009e24: d003 beq.n 8009e2e CONN.chargingError = CONN_ERR_CONTACTOR; 8009e26: 4b12 ldr r3, [pc, #72] @ (8009e70 ) 8009e28: 2207 movs r2, #7 8009e2a: 775a strb r2, [r3, #29] 8009e2c: e00e b.n 8009e4c } else if(PSU0.psu_fault){ 8009e2e: 4b12 ldr r3, [pc, #72] @ (8009e78 ) 8009e30: 7b5b ldrb r3, [r3, #13] 8009e32: 2b00 cmp r3, #0 8009e34: d003 beq.n 8009e3e CONN.chargingError = CONN_ERR_PSU_FAULT; 8009e36: 4b0e ldr r3, [pc, #56] @ (8009e70 ) 8009e38: 220a movs r2, #10 8009e3a: 775a strb r2, [r3, #29] 8009e3c: e006 b.n 8009e4c // } else if(!CTRL.ac_ok) { // CONN.chargingError = CONN_ERR_AC_FAULT; // } else }else if (CONN.EvConnected == 0){ 8009e3e: 4b0c ldr r3, [pc, #48] @ (8009e70 ) 8009e40: 7f9b ldrb r3, [r3, #30] 8009e42: 2b00 cmp r3, #0 8009e44: d102 bne.n 8009e4c CONN.chargingError = CONN_NO_ERROR; 8009e46: 4b0a ldr r3, [pc, #40] @ (8009e70 ) 8009e48: 2200 movs r2, #0 8009e4a: 775a strb r2, [r3, #29] } if(ED_TraceWarning(CONN.chargingError, 0)) printf("CONN%d Error: %d\n", 0, CONN.chargingError); 8009e4c: 4b08 ldr r3, [pc, #32] @ (8009e70 ) 8009e4e: 7f5b ldrb r3, [r3, #29] 8009e50: 2100 movs r1, #0 8009e52: 4618 mov r0, r3 8009e54: f000 fc7c bl 800a750 8009e58: 4603 mov r3, r0 8009e5a: 2b00 cmp r3, #0 8009e5c: d006 beq.n 8009e6c 8009e5e: 4b04 ldr r3, [pc, #16] @ (8009e70 ) 8009e60: 7f5b ldrb r3, [r3, #29] 8009e62: 461a mov r2, r3 8009e64: 2100 movs r1, #0 8009e66: 4805 ldr r0, [pc, #20] @ (8009e7c ) 8009e68: f00a fab8 bl 80143dc } 8009e6c: bf00 nop 8009e6e: bd80 pop {r7, pc} 8009e70: 20000398 .word 0x20000398 8009e74: 200003b8 .word 0x200003b8 8009e78: 200008e4 .word 0x200008e4 8009e7c: 08016650 .word 0x08016650 08009e80 : void CONN_Task(){ 8009e80: b580 push {r7, lr} 8009e82: af00 add r7, sp, #0 /* CCS state machine is handled in serial.c. * Keep this task lightweight for scheduler compatibility. */ if (CONN.chargingError != CONN_NO_ERROR) { 8009e84: 4b0f ldr r3, [pc, #60] @ (8009ec4 ) 8009e86: 7f5b ldrb r3, [r3, #29] 8009e88: 2b00 cmp r3, #0 8009e8a: d003 beq.n 8009e94 CONN_SetState(Disabled); 8009e8c: 2002 movs r0, #2 8009e8e: f000 f81f bl 8009ed0 return; 8009e92: e016 b.n 8009ec2 } if (connectorState == Unknown && config_initialized) { 8009e94: 4b0c ldr r3, [pc, #48] @ (8009ec8 ) 8009e96: 781b ldrb r3, [r3, #0] 8009e98: 2b00 cmp r3, #0 8009e9a: d107 bne.n 8009eac 8009e9c: 4b0b ldr r3, [pc, #44] @ (8009ecc ) 8009e9e: 781b ldrb r3, [r3, #0] 8009ea0: 2b00 cmp r3, #0 8009ea2: d003 beq.n 8009eac CONN_SetState(Unplugged); 8009ea4: 2001 movs r0, #1 8009ea6: f000 f813 bl 8009ed0 8009eaa: e00a b.n 8009ec2 } else if (connectorState == Disabled && CONN.chargingError == CONN_NO_ERROR) { 8009eac: 4b06 ldr r3, [pc, #24] @ (8009ec8 ) 8009eae: 781b ldrb r3, [r3, #0] 8009eb0: 2b02 cmp r3, #2 8009eb2: d106 bne.n 8009ec2 8009eb4: 4b03 ldr r3, [pc, #12] @ (8009ec4 ) 8009eb6: 7f5b ldrb r3, [r3, #29] 8009eb8: 2b00 cmp r3, #0 8009eba: d102 bne.n 8009ec2 CONN_SetState(Unplugged); 8009ebc: 2001 movs r0, #1 8009ebe: f000 f807 bl 8009ed0 } } 8009ec2: bd80 pop {r7, pc} 8009ec4: 20000398 .word 0x20000398 8009ec8: 200003b7 .word 0x200003b7 8009ecc: 20001092 .word 0x20001092 08009ed0 : void CONN_SetState(CONN_State_t state){ 8009ed0: b580 push {r7, lr} 8009ed2: b082 sub sp, #8 8009ed4: af00 add r7, sp, #0 8009ed6: 4603 mov r3, r0 8009ed8: 71fb strb r3, [r7, #7] if (connectorState == state) { 8009eda: 4b41 ldr r3, [pc, #260] @ (8009fe0 ) 8009edc: 781b ldrb r3, [r3, #0] 8009ede: 79fa ldrb r2, [r7, #7] 8009ee0: 429a cmp r2, r3 8009ee2: d103 bne.n 8009eec CONN.connState = state; 8009ee4: 4a3f ldr r2, [pc, #252] @ (8009fe4 ) 8009ee6: 79fb ldrb r3, [r7, #7] 8009ee8: 7053 strb r3, [r2, #1] return; 8009eea: e075 b.n 8009fd8 } connectorState = state; 8009eec: 4a3c ldr r2, [pc, #240] @ (8009fe0 ) 8009eee: 79fb ldrb r3, [r7, #7] 8009ef0: 7013 strb r3, [r2, #0] if(connectorState == Unknown) log_printf(LOG_INFO, "Connector: Unknown\n"); 8009ef2: 4b3b ldr r3, [pc, #236] @ (8009fe0 ) 8009ef4: 781b ldrb r3, [r3, #0] 8009ef6: 2b00 cmp r3, #0 8009ef8: d103 bne.n 8009f02 8009efa: 493b ldr r1, [pc, #236] @ (8009fe8 ) 8009efc: 2007 movs r0, #7 8009efe: f000 fa85 bl 800a40c if(connectorState == Unplugged) log_printf(LOG_INFO, "Connector: Unplugged\n"); 8009f02: 4b37 ldr r3, [pc, #220] @ (8009fe0 ) 8009f04: 781b ldrb r3, [r3, #0] 8009f06: 2b01 cmp r3, #1 8009f08: d103 bne.n 8009f12 8009f0a: 4938 ldr r1, [pc, #224] @ (8009fec ) 8009f0c: 2007 movs r0, #7 8009f0e: f000 fa7d bl 800a40c if(connectorState == Disabled) log_printf(LOG_INFO, "Connector: Disabled\n"); 8009f12: 4b33 ldr r3, [pc, #204] @ (8009fe0 ) 8009f14: 781b ldrb r3, [r3, #0] 8009f16: 2b02 cmp r3, #2 8009f18: d103 bne.n 8009f22 8009f1a: 4935 ldr r1, [pc, #212] @ (8009ff0 ) 8009f1c: 2007 movs r0, #7 8009f1e: f000 fa75 bl 800a40c if(connectorState == Preparing) log_printf(LOG_INFO, "Connector: Preparing\n"); 8009f22: 4b2f ldr r3, [pc, #188] @ (8009fe0 ) 8009f24: 781b ldrb r3, [r3, #0] 8009f26: 2b03 cmp r3, #3 8009f28: d103 bne.n 8009f32 8009f2a: 4932 ldr r1, [pc, #200] @ (8009ff4 ) 8009f2c: 2007 movs r0, #7 8009f2e: f000 fa6d bl 800a40c if(connectorState == AuthRequired) log_printf(LOG_INFO, "Connector: AuthRequired\n"); 8009f32: 4b2b ldr r3, [pc, #172] @ (8009fe0 ) 8009f34: 781b ldrb r3, [r3, #0] 8009f36: 2b04 cmp r3, #4 8009f38: d103 bne.n 8009f42 8009f3a: 492f ldr r1, [pc, #188] @ (8009ff8 ) 8009f3c: 2007 movs r0, #7 8009f3e: f000 fa65 bl 800a40c if(connectorState == WaitingForEnergy) log_printf(LOG_INFO, "Connector: WaitingForEnergy\n"); 8009f42: 4b27 ldr r3, [pc, #156] @ (8009fe0 ) 8009f44: 781b ldrb r3, [r3, #0] 8009f46: 2b05 cmp r3, #5 8009f48: d103 bne.n 8009f52 8009f4a: 492c ldr r1, [pc, #176] @ (8009ffc ) 8009f4c: 2007 movs r0, #7 8009f4e: f000 fa5d bl 800a40c if(connectorState == ChargingPausedEV) log_printf(LOG_INFO, "Connector: ChargingPausedEV\n"); 8009f52: 4b23 ldr r3, [pc, #140] @ (8009fe0 ) 8009f54: 781b ldrb r3, [r3, #0] 8009f56: 2b06 cmp r3, #6 8009f58: d103 bne.n 8009f62 8009f5a: 4929 ldr r1, [pc, #164] @ (800a000 ) 8009f5c: 2007 movs r0, #7 8009f5e: f000 fa55 bl 800a40c if(connectorState == ChargingPausedEVSE) log_printf(LOG_INFO, "Connector: ChargingPausedEVSE\n"); 8009f62: 4b1f ldr r3, [pc, #124] @ (8009fe0 ) 8009f64: 781b ldrb r3, [r3, #0] 8009f66: 2b07 cmp r3, #7 8009f68: d103 bne.n 8009f72 8009f6a: 4926 ldr r1, [pc, #152] @ (800a004 ) 8009f6c: 2007 movs r0, #7 8009f6e: f000 fa4d bl 800a40c if(connectorState == Charging) log_printf(LOG_INFO, "Connector: Charging\n"); 8009f72: 4b1b ldr r3, [pc, #108] @ (8009fe0 ) 8009f74: 781b ldrb r3, [r3, #0] 8009f76: 2b08 cmp r3, #8 8009f78: d103 bne.n 8009f82 8009f7a: 4923 ldr r1, [pc, #140] @ (800a008 ) 8009f7c: 2007 movs r0, #7 8009f7e: f000 fa45 bl 800a40c if(connectorState == AuthTimeout) log_printf(LOG_INFO, "Connector: AuthTimeout\n"); 8009f82: 4b17 ldr r3, [pc, #92] @ (8009fe0 ) 8009f84: 781b ldrb r3, [r3, #0] 8009f86: 2b09 cmp r3, #9 8009f88: d103 bne.n 8009f92 8009f8a: 4920 ldr r1, [pc, #128] @ (800a00c ) 8009f8c: 2007 movs r0, #7 8009f8e: f000 fa3d bl 800a40c if(connectorState == Finished) log_printf(LOG_INFO, "Connector: Finished\n"); 8009f92: 4b13 ldr r3, [pc, #76] @ (8009fe0 ) 8009f94: 781b ldrb r3, [r3, #0] 8009f96: 2b0a cmp r3, #10 8009f98: d103 bne.n 8009fa2 8009f9a: 491d ldr r1, [pc, #116] @ (800a010 ) 8009f9c: 2007 movs r0, #7 8009f9e: f000 fa35 bl 800a40c if(connectorState == FinishedEVSE) log_printf(LOG_INFO, "Connector: FinishedEVSE\n"); 8009fa2: 4b0f ldr r3, [pc, #60] @ (8009fe0 ) 8009fa4: 781b ldrb r3, [r3, #0] 8009fa6: 2b0b cmp r3, #11 8009fa8: d103 bne.n 8009fb2 8009faa: 491a ldr r1, [pc, #104] @ (800a014 ) 8009fac: 2007 movs r0, #7 8009fae: f000 fa2d bl 800a40c if(connectorState == FinishedEV) log_printf(LOG_INFO, "Connector: FinishedEV\n"); 8009fb2: 4b0b ldr r3, [pc, #44] @ (8009fe0 ) 8009fb4: 781b ldrb r3, [r3, #0] 8009fb6: 2b0c cmp r3, #12 8009fb8: d103 bne.n 8009fc2 8009fba: 4917 ldr r1, [pc, #92] @ (800a018 ) 8009fbc: 2007 movs r0, #7 8009fbe: f000 fa25 bl 800a40c if(connectorState == Replugging) log_printf(LOG_INFO, "Connector: Replugging\n"); 8009fc2: 4b07 ldr r3, [pc, #28] @ (8009fe0 ) 8009fc4: 781b ldrb r3, [r3, #0] 8009fc6: 2b0d cmp r3, #13 8009fc8: d103 bne.n 8009fd2 8009fca: 4914 ldr r1, [pc, #80] @ (800a01c ) 8009fcc: 2007 movs r0, #7 8009fce: f000 fa1d bl 800a40c CONN.connState = state; 8009fd2: 4a04 ldr r2, [pc, #16] @ (8009fe4 ) 8009fd4: 79fb ldrb r3, [r7, #7] 8009fd6: 7053 strb r3, [r2, #1] } 8009fd8: 3708 adds r7, #8 8009fda: 46bd mov sp, r7 8009fdc: bd80 pop {r7, pc} 8009fde: bf00 nop 8009fe0: 200003b7 .word 0x200003b7 8009fe4: 20000398 .word 0x20000398 8009fe8: 08016664 .word 0x08016664 8009fec: 08016678 .word 0x08016678 8009ff0: 08016690 .word 0x08016690 8009ff4: 080166a8 .word 0x080166a8 8009ff8: 080166c0 .word 0x080166c0 8009ffc: 080166dc .word 0x080166dc 800a000: 080166fc .word 0x080166fc 800a004: 0801671c .word 0x0801671c 800a008: 0801673c .word 0x0801673c 800a00c: 08016754 .word 0x08016754 800a010: 0801676c .word 0x0801676c 800a014: 08016784 .word 0x08016784 800a018: 080167a0 .word 0x080167a0 800a01c: 080167b8 .word 0x080167b8 0800a020 : CP_State_t fake_cp_state = EV_STATE_ACQUIRING; #define VREFINT_CAL_ADDR ((uint16_t*)0x1FFFF7BA) // для STM32F1! static int32_t CP_ReadVoltageMv(void) { 800a020: b480 push {r7} 800a022: b087 sub sp, #28 800a024: af00 add r7, sp, #0 uint32_t adc_cp = adc_data.cp_raw; 800a026: 4b13 ldr r3, [pc, #76] @ (800a074 ) 800a028: 885b ldrh r3, [r3, #2] 800a02a: b29b uxth r3, r3 800a02c: 617b str r3, [r7, #20] uint32_t adc_vref = adc_data.vrefint_raw; // нужно измерять! 800a02e: 4b11 ldr r3, [pc, #68] @ (800a074 ) 800a030: 895b ldrh r3, [r3, #10] 800a032: b29b uxth r3, r3 800a034: 613b str r3, [r7, #16] // VREFINT в мВ (берётся из даташита или калибровки MCU) const int32_t VREFINT_MV = 1210; 800a036: f240 43ba movw r3, #1210 @ 0x4ba 800a03a: 60fb str r3, [r7, #12] // напряжение на входе АЦП int32_t v_adc_mv = (adc_cp * VREFINT_MV) / adc_vref; 800a03c: 68fb ldr r3, [r7, #12] 800a03e: 697a ldr r2, [r7, #20] 800a040: fb03 f202 mul.w r2, r3, r2 800a044: 693b ldr r3, [r7, #16] 800a046: fbb2 f3f3 udiv r3, r2, r3 800a04a: 60bb str r3, [r7, #8] // дальше твоя формула int32_t v_out_mv = ((v_adc_mv - 1723) * 7704) / 1000; 800a04c: 68bb ldr r3, [r7, #8] 800a04e: f2a3 63bb subw r3, r3, #1723 @ 0x6bb 800a052: f641 6218 movw r2, #7704 @ 0x1e18 800a056: fb02 f303 mul.w r3, r2, r3 800a05a: 4a07 ldr r2, [pc, #28] @ (800a078 ) 800a05c: fb82 1203 smull r1, r2, r2, r3 800a060: 1192 asrs r2, r2, #6 800a062: 17db asrs r3, r3, #31 800a064: 1ad3 subs r3, r2, r3 800a066: 607b str r3, [r7, #4] return v_out_mv; 800a068: 687b ldr r3, [r7, #4] } 800a06a: 4618 mov r0, r3 800a06c: 371c adds r7, #28 800a06e: 46bd mov sp, r7 800a070: bc80 pop {r7} 800a072: 4770 bx lr 800a074: 20000268 .word 0x20000268 800a078: 10624dd3 .word 0x10624dd3 0800a07c : void CP_Init(void) { 800a07c: b580 push {r7, lr} 800a07e: af00 add r7, sp, #0 /* TIM3_CH2 (PA7): set 1kHz PWM like original CCS logic. */ htim3.Instance->PSC = 160 - 1; 800a080: 4b0e ldr r3, [pc, #56] @ (800a0bc ) 800a082: 681b ldr r3, [r3, #0] 800a084: 229f movs r2, #159 @ 0x9f 800a086: 629a str r2, [r3, #40] @ 0x28 htim3.Instance->ARR = MAX_DUTY - 1; 800a088: 4b0c ldr r3, [pc, #48] @ (800a0bc ) 800a08a: 681b ldr r3, [r3, #0] 800a08c: f240 12c1 movw r2, #449 @ 0x1c1 800a090: 62da str r2, [r3, #44] @ 0x2c #if DUTY_INVERT == 0 htim3.Instance->CCR2 = MAX_DUTY; 800a092: 4b0a ldr r3, [pc, #40] @ (800a0bc ) 800a094: 681b ldr r3, [r3, #0] 800a096: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a09a: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = MAX_DUTY + 5; 800a09c: 4b07 ldr r3, [pc, #28] @ (800a0bc ) 800a09e: 681b ldr r3, [r3, #0] 800a0a0: f240 12c7 movw r2, #455 @ 0x1c7 800a0a4: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = 0; htim3.Instance->CCR1 = 0; #endif HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_2); 800a0a6: 2104 movs r1, #4 800a0a8: 4804 ldr r0, [pc, #16] @ (800a0bc ) 800a0aa: f007 fdc7 bl 8011c3c HAL_TIM_OC_Start(&htim3, TIM_CHANNEL_1); 800a0ae: 2100 movs r1, #0 800a0b0: 4802 ldr r0, [pc, #8] @ (800a0bc ) 800a0b2: f007 fcc1 bl 8011a38 } 800a0b6: bf00 nop 800a0b8: bd80 pop {r7, pc} 800a0ba: bf00 nop 800a0bc: 20001098 .word 0x20001098 0800a0c0 : void CP_SetDuty(uint8_t percentage) { 800a0c0: b480 push {r7} 800a0c2: b085 sub sp, #20 800a0c4: af00 add r7, sp, #0 800a0c6: 4603 mov r3, r0 800a0c8: 71fb strb r3, [r7, #7] uint32_t pwmduty = MAX_DUTY * percentage / 100; 800a0ca: 79fb ldrb r3, [r7, #7] 800a0cc: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a0d0: fb02 f303 mul.w r3, r2, r3 800a0d4: 4a0b ldr r2, [pc, #44] @ (800a104 ) 800a0d6: fb82 1203 smull r1, r2, r2, r3 800a0da: 1152 asrs r2, r2, #5 800a0dc: 17db asrs r3, r3, #31 800a0de: 1ad3 subs r3, r2, r3 800a0e0: 60fb str r3, [r7, #12] cp_duty = percentage; 800a0e2: 4a09 ldr r2, [pc, #36] @ (800a108 ) 800a0e4: 79fb ldrb r3, [r7, #7] 800a0e6: 7013 strb r3, [r2, #0] #if DUTY_INVERT == 0 htim3.Instance->CCR2 = pwmduty; 800a0e8: 4b08 ldr r3, [pc, #32] @ (800a10c ) 800a0ea: 681b ldr r3, [r3, #0] 800a0ec: 68fa ldr r2, [r7, #12] 800a0ee: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = 0 + 1; 800a0f0: 4b06 ldr r3, [pc, #24] @ (800a10c ) 800a0f2: 681b ldr r3, [r3, #0] 800a0f4: 2201 movs r2, #1 800a0f6: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = MAX_DUTY - pwmduty; htim3.Instance->CCR1 = MAX_DUTY - pwmduty + 5; #endif } 800a0f8: bf00 nop 800a0fa: 3714 adds r7, #20 800a0fc: 46bd mov sp, r7 800a0fe: bc80 pop {r7} 800a100: 4770 bx lr 800a102: bf00 nop 800a104: 51eb851f .word 0x51eb851f 800a108: 200003c0 .word 0x200003c0 800a10c: 20001098 .word 0x20001098 0800a110 : uint8_t CP_GetDuty(void) { 800a110: b480 push {r7} 800a112: af00 add r7, sp, #0 return cp_duty; 800a114: 4b02 ldr r3, [pc, #8] @ (800a120 ) 800a116: 781b ldrb r3, [r3, #0] } 800a118: 4618 mov r0, r3 800a11a: 46bd mov sp, r7 800a11c: bc80 pop {r7} 800a11e: 4770 bx lr 800a120: 200003c0 .word 0x200003c0 0800a124 : int32_t CP_GetVoltage(void) { 800a124: b580 push {r7, lr} 800a126: af00 add r7, sp, #0 cp_voltage_mv = CP_ReadVoltageMv(); 800a128: f7ff ff7a bl 800a020 800a12c: 4603 mov r3, r0 800a12e: 4a03 ldr r2, [pc, #12] @ (800a13c ) 800a130: 6013 str r3, [r2, #0] return cp_voltage_mv; 800a132: 4b02 ldr r3, [pc, #8] @ (800a13c ) 800a134: 681b ldr r3, [r3, #0] } 800a136: 4618 mov r0, r3 800a138: bd80 pop {r7, pc} 800a13a: bf00 nop 800a13c: 200003bc .word 0x200003bc 0800a140 : CP_State_t CP_GetState(void) { 800a140: b580 push {r7, lr} 800a142: b082 sub sp, #8 800a144: af00 add r7, sp, #0 int32_t voltage_real = CP_GetVoltage(); 800a146: f7ff ffed bl 800a124 800a14a: 6078 str r0, [r7, #4] if(fake_cp_state != EV_STATE_ACQUIRING) { 800a14c: 4b21 ldr r3, [pc, #132] @ (800a1d4 ) 800a14e: 781b ldrb r3, [r3, #0] 800a150: 2b06 cmp r3, #6 800a152: d002 beq.n 800a15a return fake_cp_state; 800a154: 4b1f ldr r3, [pc, #124] @ (800a1d4 ) 800a156: 781b ldrb r3, [r3, #0] 800a158: e038 b.n 800a1cc } if (voltage_real >= (12000-1000)) { 800a15a: 687b ldr r3, [r7, #4] 800a15c: f642 22f7 movw r2, #10999 @ 0x2af7 800a160: 4293 cmp r3, r2 800a162: dd01 ble.n 800a168 return EV_STATE_A_IDLE; 800a164: 2300 movs r3, #0 800a166: e031 b.n 800a1cc } else if (voltage_real >= (9000-1000) && voltage_real <= (9000+1000)) { 800a168: 687b ldr r3, [r7, #4] 800a16a: f5b3 5ffa cmp.w r3, #8000 @ 0x1f40 800a16e: db06 blt.n 800a17e 800a170: 687b ldr r3, [r7, #4] 800a172: f242 7210 movw r2, #10000 @ 0x2710 800a176: 4293 cmp r3, r2 800a178: dc01 bgt.n 800a17e return EV_STATE_B_CONN_PREP; 800a17a: 2301 movs r3, #1 800a17c: e026 b.n 800a1cc } else if (voltage_real >= (6000-1000) && voltage_real <= (6000+1000)) { 800a17e: 687b ldr r3, [r7, #4] 800a180: f241 3287 movw r2, #4999 @ 0x1387 800a184: 4293 cmp r3, r2 800a186: dd06 ble.n 800a196 800a188: 687b ldr r3, [r7, #4] 800a18a: f641 3258 movw r2, #7000 @ 0x1b58 800a18e: 4293 cmp r3, r2 800a190: dc01 bgt.n 800a196 return EV_STATE_C_CONN_ACTIVE; 800a192: 2302 movs r3, #2 800a194: e01a b.n 800a1cc } else if (voltage_real >= (3000-1000) && voltage_real <= (3000 + 1000)) { 800a196: 687b ldr r3, [r7, #4] 800a198: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800a19c: db05 blt.n 800a1aa 800a19e: 687b ldr r3, [r7, #4] 800a1a0: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800a1a4: dc01 bgt.n 800a1aa return EV_STATE_D_CONN_ACT_VENT; 800a1a6: 2303 movs r3, #3 800a1a8: e010 b.n 800a1cc } else if (voltage_real >= (0-1000) && voltage_real <= (0+2000)){ 800a1aa: 687b ldr r3, [r7, #4] 800a1ac: f513 7f7a cmn.w r3, #1000 @ 0x3e8 800a1b0: db05 blt.n 800a1be 800a1b2: 687b ldr r3, [r7, #4] 800a1b4: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800a1b8: dc01 bgt.n 800a1be return EV_STATE_E_NO_POWER; 800a1ba: 2304 movs r3, #4 800a1bc: e006 b.n 800a1cc } else if (voltage_real <= (-12000+1000)) { 800a1be: 687b ldr r3, [r7, #4] 800a1c0: 4a05 ldr r2, [pc, #20] @ (800a1d8 ) 800a1c2: 4293 cmp r3, r2 800a1c4: da01 bge.n 800a1ca return EV_STATE_F_ERROR; 800a1c6: 2305 movs r3, #5 800a1c8: e000 b.n 800a1cc } else { return EV_STATE_ACQUIRING; 800a1ca: 2306 movs r3, #6 } } 800a1cc: 4618 mov r0, r3 800a1ce: 3708 adds r7, #8 800a1d0: 46bd mov sp, r7 800a1d2: bd80 pop {r7, pc} 800a1d4: 20000004 .word 0x20000004 800a1d8: ffffd509 .word 0xffffd509 0800a1dc : CRC_HandleTypeDef hcrc; /* CRC init function */ void MX_CRC_Init(void) { 800a1dc: b580 push {r7, lr} 800a1de: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 800a1e0: 4b06 ldr r3, [pc, #24] @ (800a1fc ) 800a1e2: 4a07 ldr r2, [pc, #28] @ (800a200 ) 800a1e4: 601a str r2, [r3, #0] if (HAL_CRC_Init(&hcrc) != HAL_OK) 800a1e6: 4805 ldr r0, [pc, #20] @ (800a1fc ) 800a1e8: f005 faf9 bl 800f7de 800a1ec: 4603 mov r3, r0 800a1ee: 2b00 cmp r3, #0 800a1f0: d001 beq.n 800a1f6 { Error_Handler(); 800a1f2: f000 fc17 bl 800aa24 } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 800a1f6: bf00 nop 800a1f8: bd80 pop {r7, pc} 800a1fa: bf00 nop 800a1fc: 200003c4 .word 0x200003c4 800a200: 40023000 .word 0x40023000 0800a204 : void HAL_CRC_MspInit(CRC_HandleTypeDef* crcHandle) { 800a204: b480 push {r7} 800a206: b085 sub sp, #20 800a208: af00 add r7, sp, #0 800a20a: 6078 str r0, [r7, #4] if(crcHandle->Instance==CRC) 800a20c: 687b ldr r3, [r7, #4] 800a20e: 681b ldr r3, [r3, #0] 800a210: 4a09 ldr r2, [pc, #36] @ (800a238 ) 800a212: 4293 cmp r3, r2 800a214: d10b bne.n 800a22e { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* CRC clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 800a216: 4b09 ldr r3, [pc, #36] @ (800a23c ) 800a218: 695b ldr r3, [r3, #20] 800a21a: 4a08 ldr r2, [pc, #32] @ (800a23c ) 800a21c: f043 0340 orr.w r3, r3, #64 @ 0x40 800a220: 6153 str r3, [r2, #20] 800a222: 4b06 ldr r3, [pc, #24] @ (800a23c ) 800a224: 695b ldr r3, [r3, #20] 800a226: f003 0340 and.w r3, r3, #64 @ 0x40 800a22a: 60fb str r3, [r7, #12] 800a22c: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 800a22e: bf00 nop 800a230: 3714 adds r7, #20 800a232: 46bd mov sp, r7 800a234: bc80 pop {r7} 800a236: 4770 bx lr 800a238: 40023000 .word 0x40023000 800a23c: 40021000 .word 0x40021000 0800a240 <_write>: #if defined(__GNUC__) int _write(int fd, char * ptr, int len) { 800a240: b580 push {r7, lr} 800a242: b084 sub sp, #16 800a244: af00 add r7, sp, #0 800a246: 60f8 str r0, [r7, #12] 800a248: 60b9 str r1, [r7, #8] 800a24a: 607a str r2, [r7, #4] debug_buffer_add((const uint8_t*)ptr, len); 800a24c: 687b ldr r3, [r7, #4] 800a24e: b29b uxth r3, r3 800a250: 4619 mov r1, r3 800a252: 68b8 ldr r0, [r7, #8] 800a254: f000 f806 bl 800a264 return len; 800a258: 687b ldr r3, [r7, #4] } 800a25a: 4618 mov r0, r3 800a25c: 3710 adds r7, #16 800a25e: 46bd mov sp, r7 800a260: bd80 pop {r7, pc} ... 0800a264 : #endif // Добавляет данные в кольцевой буфер void debug_buffer_add(const uint8_t* data, uint16_t len) { 800a264: b480 push {r7} 800a266: b085 sub sp, #20 800a268: af00 add r7, sp, #0 800a26a: 6078 str r0, [r7, #4] 800a26c: 460b mov r3, r1 800a26e: 807b strh r3, [r7, #2] \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 800a270: b672 cpsid i } 800a272: bf00 nop __disable_irq(); for (uint16_t i = 0; i < len; i++) { 800a274: 2300 movs r3, #0 800a276: 81fb strh r3, [r7, #14] 800a278: e045 b.n 800a306 // Если буфер полон, перезаписываем старые данные if (debug_buffer.count >= DEBUG_BUFFER_SIZE) { 800a27a: 4b28 ldr r3, [pc, #160] @ (800a31c ) 800a27c: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a280: b29b uxth r3, r3 800a282: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800a286: d318 bcc.n 800a2ba debug_buffer.read_index = (debug_buffer.read_index + 1) % DEBUG_BUFFER_SIZE; 800a288: 4b24 ldr r3, [pc, #144] @ (800a31c ) 800a28a: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a28e: b29b uxth r3, r3 800a290: 3301 adds r3, #1 800a292: 425a negs r2, r3 800a294: f3c3 0309 ubfx r3, r3, #0, #10 800a298: f3c2 0209 ubfx r2, r2, #0, #10 800a29c: bf58 it pl 800a29e: 4253 negpl r3, r2 800a2a0: b29a uxth r2, r3 800a2a2: 4b1e ldr r3, [pc, #120] @ (800a31c ) 800a2a4: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count--; 800a2a8: 4b1c ldr r3, [pc, #112] @ (800a31c ) 800a2aa: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a2ae: b29b uxth r3, r3 800a2b0: 3b01 subs r3, #1 800a2b2: b29a uxth r2, r3 800a2b4: 4b19 ldr r3, [pc, #100] @ (800a31c ) 800a2b6: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 } debug_buffer.buffer[debug_buffer.write_index] = data[i]; 800a2ba: 89fb ldrh r3, [r7, #14] 800a2bc: 687a ldr r2, [r7, #4] 800a2be: 4413 add r3, r2 800a2c0: 4a16 ldr r2, [pc, #88] @ (800a31c ) 800a2c2: f8b2 2400 ldrh.w r2, [r2, #1024] @ 0x400 800a2c6: b292 uxth r2, r2 800a2c8: 7819 ldrb r1, [r3, #0] 800a2ca: 4b14 ldr r3, [pc, #80] @ (800a31c ) 800a2cc: 5499 strb r1, [r3, r2] debug_buffer.write_index = (debug_buffer.write_index + 1) % DEBUG_BUFFER_SIZE; 800a2ce: 4b13 ldr r3, [pc, #76] @ (800a31c ) 800a2d0: f8b3 3400 ldrh.w r3, [r3, #1024] @ 0x400 800a2d4: b29b uxth r3, r3 800a2d6: 3301 adds r3, #1 800a2d8: 425a negs r2, r3 800a2da: f3c3 0309 ubfx r3, r3, #0, #10 800a2de: f3c2 0209 ubfx r2, r2, #0, #10 800a2e2: bf58 it pl 800a2e4: 4253 negpl r3, r2 800a2e6: b29a uxth r2, r3 800a2e8: 4b0c ldr r3, [pc, #48] @ (800a31c ) 800a2ea: f8a3 2400 strh.w r2, [r3, #1024] @ 0x400 debug_buffer.count++; 800a2ee: 4b0b ldr r3, [pc, #44] @ (800a31c ) 800a2f0: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a2f4: b29b uxth r3, r3 800a2f6: 3301 adds r3, #1 800a2f8: b29a uxth r2, r3 800a2fa: 4b08 ldr r3, [pc, #32] @ (800a31c ) 800a2fc: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 for (uint16_t i = 0; i < len; i++) { 800a300: 89fb ldrh r3, [r7, #14] 800a302: 3301 adds r3, #1 800a304: 81fb strh r3, [r7, #14] 800a306: 89fa ldrh r2, [r7, #14] 800a308: 887b ldrh r3, [r7, #2] 800a30a: 429a cmp r2, r3 800a30c: d3b5 bcc.n 800a27a __ASM volatile ("cpsie i" : : : "memory"); 800a30e: b662 cpsie i } 800a310: bf00 nop } __enable_irq(); } 800a312: bf00 nop 800a314: 3714 adds r7, #20 800a316: 46bd mov sp, r7 800a318: bc80 pop {r7} 800a31a: 4770 bx lr 800a31c: 200003cc .word 0x200003cc 0800a320 : // Возвращает количество доступных данных в буфере uint16_t debug_buffer_available(void) { 800a320: b480 push {r7} 800a322: b083 sub sp, #12 800a324: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a326: b672 cpsid i } 800a328: bf00 nop __disable_irq(); uint16_t count = debug_buffer.count; 800a32a: 4b06 ldr r3, [pc, #24] @ (800a344 ) 800a32c: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a330: 80fb strh r3, [r7, #6] __ASM volatile ("cpsie i" : : : "memory"); 800a332: b662 cpsie i } 800a334: bf00 nop __enable_irq(); return count; 800a336: 88fb ldrh r3, [r7, #6] } 800a338: 4618 mov r0, r3 800a33a: 370c adds r7, #12 800a33c: 46bd mov sp, r7 800a33e: bc80 pop {r7} 800a340: 4770 bx lr 800a342: bf00 nop 800a344: 200003cc .word 0x200003cc 0800a348 : // Отправляет один пакет данных из буфера через SC_SendPacket (не более 250 байт) void debug_buffer_send(void) { 800a348: b580 push {r7, lr} 800a34a: b082 sub sp, #8 800a34c: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a34e: b672 cpsid i } 800a350: bf00 nop __disable_irq(); // Если буфер пуст, ничего не делаем if (debug_buffer.count == 0) { 800a352: 4b2d ldr r3, [pc, #180] @ (800a408 ) 800a354: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a358: b29b uxth r3, r3 800a35a: 2b00 cmp r3, #0 800a35c: d102 bne.n 800a364 __ASM volatile ("cpsie i" : : : "memory"); 800a35e: b662 cpsie i } 800a360: bf00 nop __enable_irq(); return; 800a362: e04e b.n 800a402 } // Определяем сколько байт можно отправить (не более 250) uint16_t bytes_to_send = debug_buffer.count; 800a364: 4b28 ldr r3, [pc, #160] @ (800a408 ) 800a366: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a36a: 80fb strh r3, [r7, #6] if (bytes_to_send > DEBUG_BUFFER_MAX_COUNT) { 800a36c: 88fb ldrh r3, [r7, #6] 800a36e: 2b80 cmp r3, #128 @ 0x80 800a370: d901 bls.n 800a376 bytes_to_send = DEBUG_BUFFER_MAX_COUNT; 800a372: 2380 movs r3, #128 @ 0x80 800a374: 80fb strh r3, [r7, #6] } // Вычисляем сколько байт до конца буфера uint16_t bytes_to_end = DEBUG_BUFFER_SIZE - debug_buffer.read_index; 800a376: 4b24 ldr r3, [pc, #144] @ (800a408 ) 800a378: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a37c: b29b uxth r3, r3 800a37e: f5c3 6380 rsb r3, r3, #1024 @ 0x400 800a382: 80bb strh r3, [r7, #4] // Отправляем только непрерывный блок (до конца буфера или до bytes_to_send) if (bytes_to_send > bytes_to_end) { 800a384: 88fa ldrh r2, [r7, #6] 800a386: 88bb ldrh r3, [r7, #4] 800a388: 429a cmp r2, r3 800a38a: d901 bls.n 800a390 bytes_to_send = bytes_to_end; 800a38c: 88bb ldrh r3, [r7, #4] 800a38e: 80fb strh r3, [r7, #6] } // Отправляем данные напрямую из буфера if(bytes_to_send == debug_buffer.count){ 800a390: 4b1d ldr r3, [pc, #116] @ (800a408 ) 800a392: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a396: b29b uxth r3, r3 800a398: 88fa ldrh r2, [r7, #6] 800a39a: 429a cmp r2, r3 800a39c: d10c bne.n 800a3b8 SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG); 800a39e: 4b1a ldr r3, [pc, #104] @ (800a408 ) 800a3a0: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a3a4: b29b uxth r3, r3 800a3a6: 461a mov r2, r3 800a3a8: 4b17 ldr r3, [pc, #92] @ (800a408 ) 800a3aa: 4413 add r3, r2 800a3ac: 88f9 ldrh r1, [r7, #6] 800a3ae: 2250 movs r2, #80 @ 0x50 800a3b0: 4618 mov r0, r3 800a3b2: f002 fa73 bl 800c89c 800a3b6: e00b b.n 800a3d0 }else{ SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG_CONTINUE); 800a3b8: 4b13 ldr r3, [pc, #76] @ (800a408 ) 800a3ba: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a3be: b29b uxth r3, r3 800a3c0: 461a mov r2, r3 800a3c2: 4b11 ldr r3, [pc, #68] @ (800a408 ) 800a3c4: 4413 add r3, r2 800a3c6: 88f9 ldrh r1, [r7, #6] 800a3c8: 2251 movs r2, #81 @ 0x51 800a3ca: 4618 mov r0, r3 800a3cc: f002 fa66 bl 800c89c } debug_buffer.read_index = (debug_buffer.read_index + bytes_to_send) % DEBUG_BUFFER_SIZE; 800a3d0: 4b0d ldr r3, [pc, #52] @ (800a408 ) 800a3d2: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a3d6: b29a uxth r2, r3 800a3d8: 88fb ldrh r3, [r7, #6] 800a3da: 4413 add r3, r2 800a3dc: b29b uxth r3, r3 800a3de: f3c3 0309 ubfx r3, r3, #0, #10 800a3e2: b29a uxth r2, r3 800a3e4: 4b08 ldr r3, [pc, #32] @ (800a408 ) 800a3e6: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count -= bytes_to_send; 800a3ea: 4b07 ldr r3, [pc, #28] @ (800a408 ) 800a3ec: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a3f0: b29a uxth r2, r3 800a3f2: 88fb ldrh r3, [r7, #6] 800a3f4: 1ad3 subs r3, r2, r3 800a3f6: b29a uxth r2, r3 800a3f8: 4b03 ldr r3, [pc, #12] @ (800a408 ) 800a3fa: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 __ASM volatile ("cpsie i" : : : "memory"); 800a3fe: b662 cpsie i } 800a400: bf00 nop __enable_irq(); } 800a402: 3708 adds r7, #8 800a404: 46bd mov sp, r7 800a406: bd80 pop {r7, pc} 800a408: 200003cc .word 0x200003cc 0800a40c : #define LOG_BUFFER_SIZE 128 uint8_t log_buffer[LOG_BUFFER_SIZE]; // Кастомный printf с приоритетом лога int log_printf(LogLevel_t level, const char *format, ...) { 800a40c: b40e push {r1, r2, r3} 800a40e: b580 push {r7, lr} 800a410: b085 sub sp, #20 800a412: af00 add r7, sp, #0 800a414: 4603 mov r3, r0 800a416: 71fb strb r3, [r7, #7] va_list args; int result; // Добавляем приоритет первым байтом log_buffer[0] = (uint8_t)level; 800a418: 4a15 ldr r2, [pc, #84] @ (800a470 ) 800a41a: 79fb ldrb r3, [r7, #7] 800a41c: 7013 strb r3, [r2, #0] // Форматируем строку начиная со второго байта va_start(args, format); 800a41e: f107 0320 add.w r3, r7, #32 800a422: 60bb str r3, [r7, #8] result = vsnprintf((char*)&log_buffer[1], LOG_BUFFER_SIZE - 2, format, args); 800a424: 68bb ldr r3, [r7, #8] 800a426: 69fa ldr r2, [r7, #28] 800a428: 217e movs r1, #126 @ 0x7e 800a42a: 4812 ldr r0, [pc, #72] @ (800a474 ) 800a42c: f009 ffaa bl 8014384 800a430: 60f8 str r0, [r7, #12] va_end(args); // Проверяем, не переполнился ли буфер if (result < 0) { 800a432: 68fb ldr r3, [r7, #12] 800a434: 2b00 cmp r3, #0 800a436: da01 bge.n 800a43c return result; 800a438: 68fb ldr r3, [r7, #12] 800a43a: e012 b.n 800a462 } // Ограничиваем размер, чтобы оставить место для нуль-терминатора if (result >= (LOG_BUFFER_SIZE - 2)) { 800a43c: 68fb ldr r3, [r7, #12] 800a43e: 2b7d cmp r3, #125 @ 0x7d 800a440: dd01 ble.n 800a446 result = LOG_BUFFER_SIZE - 2; 800a442: 237e movs r3, #126 @ 0x7e 800a444: 60fb str r3, [r7, #12] } // Добавляем нуль-терминатор в конец log_buffer[result + 1] = '\0'; 800a446: 68fb ldr r3, [r7, #12] 800a448: 3301 adds r3, #1 800a44a: 4a09 ldr r2, [pc, #36] @ (800a470 ) 800a44c: 2100 movs r1, #0 800a44e: 54d1 strb r1, [r2, r3] // Отправляем в буфер (приоритет + строка + нуль-терминатор) debug_buffer_add(log_buffer, result + 2); 800a450: 68fb ldr r3, [r7, #12] 800a452: b29b uxth r3, r3 800a454: 3302 adds r3, #2 800a456: b29b uxth r3, r3 800a458: 4619 mov r1, r3 800a45a: 4805 ldr r0, [pc, #20] @ (800a470 ) 800a45c: f7ff ff02 bl 800a264 return result; 800a460: 68fb ldr r3, [r7, #12] } 800a462: 4618 mov r0, r3 800a464: 3714 adds r7, #20 800a466: 46bd mov sp, r7 800a468: e8bd 4080 ldmia.w sp!, {r7, lr} 800a46c: b003 add sp, #12 800a46e: 4770 bx lr 800a470: 200007d4 .word 0x200007d4 800a474: 200007d5 .word 0x200007d5 0800a478 : /** * Enable DMA controller clock */ void MX_DMA_Init(void) { 800a478: b580 push {r7, lr} 800a47a: b082 sub sp, #8 800a47c: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 800a47e: 4b0c ldr r3, [pc, #48] @ (800a4b0 ) 800a480: 695b ldr r3, [r3, #20] 800a482: 4a0b ldr r2, [pc, #44] @ (800a4b0 ) 800a484: f043 0301 orr.w r3, r3, #1 800a488: 6153 str r3, [r2, #20] 800a48a: 4b09 ldr r3, [pc, #36] @ (800a4b0 ) 800a48c: 695b ldr r3, [r3, #20] 800a48e: f003 0301 and.w r3, r3, #1 800a492: 607b str r3, [r7, #4] 800a494: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); 800a496: 2200 movs r2, #0 800a498: 2100 movs r1, #0 800a49a: 200b movs r0, #11 800a49c: f005 f95b bl 800f756 HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 800a4a0: 200b movs r0, #11 800a4a2: f005 f974 bl 800f78e } 800a4a6: bf00 nop 800a4a8: 3708 adds r7, #8 800a4aa: 46bd mov sp, r7 800a4ac: bd80 pop {r7, pc} 800a4ae: bf00 nop 800a4b0: 40021000 .word 0x40021000 0800a4b4 : * EXTI PB8 ------> I2C1_SCL PB9 ------> I2C1_SDA */ void MX_GPIO_Init(void) { 800a4b4: b580 push {r7, lr} 800a4b6: b08a sub sp, #40 @ 0x28 800a4b8: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800a4ba: f107 0314 add.w r3, r7, #20 800a4be: 2200 movs r2, #0 800a4c0: 601a str r2, [r3, #0] 800a4c2: 605a str r2, [r3, #4] 800a4c4: 609a str r2, [r3, #8] 800a4c6: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 800a4c8: 4b93 ldr r3, [pc, #588] @ (800a718 ) 800a4ca: 699b ldr r3, [r3, #24] 800a4cc: 4a92 ldr r2, [pc, #584] @ (800a718 ) 800a4ce: f043 0310 orr.w r3, r3, #16 800a4d2: 6193 str r3, [r2, #24] 800a4d4: 4b90 ldr r3, [pc, #576] @ (800a718 ) 800a4d6: 699b ldr r3, [r3, #24] 800a4d8: f003 0310 and.w r3, r3, #16 800a4dc: 613b str r3, [r7, #16] 800a4de: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800a4e0: 4b8d ldr r3, [pc, #564] @ (800a718 ) 800a4e2: 699b ldr r3, [r3, #24] 800a4e4: 4a8c ldr r2, [pc, #560] @ (800a718 ) 800a4e6: f043 0304 orr.w r3, r3, #4 800a4ea: 6193 str r3, [r2, #24] 800a4ec: 4b8a ldr r3, [pc, #552] @ (800a718 ) 800a4ee: 699b ldr r3, [r3, #24] 800a4f0: f003 0304 and.w r3, r3, #4 800a4f4: 60fb str r3, [r7, #12] 800a4f6: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 800a4f8: 4b87 ldr r3, [pc, #540] @ (800a718 ) 800a4fa: 699b ldr r3, [r3, #24] 800a4fc: 4a86 ldr r2, [pc, #536] @ (800a718 ) 800a4fe: f043 0308 orr.w r3, r3, #8 800a502: 6193 str r3, [r2, #24] 800a504: 4b84 ldr r3, [pc, #528] @ (800a718 ) 800a506: 699b ldr r3, [r3, #24] 800a508: f003 0308 and.w r3, r3, #8 800a50c: 60bb str r3, [r7, #8] 800a50e: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOE_CLK_ENABLE(); 800a510: 4b81 ldr r3, [pc, #516] @ (800a718 ) 800a512: 699b ldr r3, [r3, #24] 800a514: 4a80 ldr r2, [pc, #512] @ (800a718 ) 800a516: f043 0340 orr.w r3, r3, #64 @ 0x40 800a51a: 6193 str r3, [r2, #24] 800a51c: 4b7e ldr r3, [pc, #504] @ (800a718 ) 800a51e: 699b ldr r3, [r3, #24] 800a520: f003 0340 and.w r3, r3, #64 @ 0x40 800a524: 607b str r3, [r7, #4] 800a526: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 800a528: 4b7b ldr r3, [pc, #492] @ (800a718 ) 800a52a: 699b ldr r3, [r3, #24] 800a52c: 4a7a ldr r2, [pc, #488] @ (800a718 ) 800a52e: f043 0320 orr.w r3, r3, #32 800a532: 6193 str r3, [r2, #24] 800a534: 4b78 ldr r3, [pc, #480] @ (800a718 ) 800a536: 699b ldr r3, [r3, #24] 800a538: f003 0320 and.w r3, r3, #32 800a53c: 603b str r3, [r7, #0] 800a53e: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, DBG1_Pin|RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin, GPIO_PIN_RESET); 800a540: 2200 movs r2, #0 800a542: 213c movs r1, #60 @ 0x3c 800a544: 4875 ldr r0, [pc, #468] @ (800a71c ) 800a546: f006 f842 bl 80105ce /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, DBG2_Pin|DBG3_Pin|RELAY_CC_Pin, GPIO_PIN_RESET); 800a54a: 2200 movs r2, #0 800a54c: f248 0160 movw r1, #32864 @ 0x8060 800a550: 4873 ldr r0, [pc, #460] @ (800a720 ) 800a552: f006 f83c bl 80105ce /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a556: 2200 movs r2, #0 800a558: f44f 51f8 mov.w r1, #7936 @ 0x1f00 800a55c: 4871 ldr r0, [pc, #452] @ (800a724 ) 800a55e: f006 f836 bl 80105ce |RELAY5_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, DBG5_Pin|DBG4_Pin|EE_WP_Pin, GPIO_PIN_RESET); 800a562: 2200 movs r2, #0 800a564: f44f 6148 mov.w r1, #3200 @ 0xc80 800a568: 486f ldr r0, [pc, #444] @ (800a728 ) 800a56a: f006 f830 bl 80105ce /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, RELAY_DC_Pin|USART2_DIR_Pin, GPIO_PIN_RESET); 800a56e: 2200 movs r2, #0 800a570: 2118 movs r1, #24 800a572: 486e ldr r0, [pc, #440] @ (800a72c ) 800a574: f006 f82b bl 80105ce /*Configure GPIO pin : DBG1_Pin */ GPIO_InitStruct.Pin = DBG1_Pin; 800a578: 2304 movs r3, #4 800a57a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a57c: 2301 movs r3, #1 800a57e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a580: 2300 movs r3, #0 800a582: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a584: 2303 movs r3, #3 800a586: 623b str r3, [r7, #32] HAL_GPIO_Init(DBG1_GPIO_Port, &GPIO_InitStruct); 800a588: f107 0314 add.w r3, r7, #20 800a58c: 4619 mov r1, r3 800a58e: 4863 ldr r0, [pc, #396] @ (800a71c ) 800a590: f005 fdc6 bl 8010120 /*Configure GPIO pins : RELAY_CP_Pin LOCK_A_Pin LOCK_B_Pin */ GPIO_InitStruct.Pin = RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin; 800a594: 2338 movs r3, #56 @ 0x38 800a596: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a598: 2301 movs r3, #1 800a59a: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a59c: 2300 movs r3, #0 800a59e: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a5a0: 2302 movs r3, #2 800a5a2: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800a5a4: f107 0314 add.w r3, r7, #20 800a5a8: 4619 mov r1, r3 800a5aa: 485c ldr r0, [pc, #368] @ (800a71c ) 800a5ac: f005 fdb8 bl 8010120 /*Configure GPIO pin : IN_SW0_Pin */ GPIO_InitStruct.Pin = IN_SW0_Pin; 800a5b0: 2302 movs r3, #2 800a5b2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a5b4: 2300 movs r3, #0 800a5b6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a5b8: 2300 movs r3, #0 800a5ba: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW0_GPIO_Port, &GPIO_InitStruct); 800a5bc: f107 0314 add.w r3, r7, #20 800a5c0: 4619 mov r1, r3 800a5c2: 4857 ldr r0, [pc, #348] @ (800a720 ) 800a5c4: f005 fdac bl 8010120 /*Configure GPIO pin : IN_SW1_Pin */ GPIO_InitStruct.Pin = IN_SW1_Pin; 800a5c8: 2304 movs r3, #4 800a5ca: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a5cc: 2300 movs r3, #0 800a5ce: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 800a5d0: 2302 movs r3, #2 800a5d2: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW1_GPIO_Port, &GPIO_InitStruct); 800a5d4: f107 0314 add.w r3, r7, #20 800a5d8: 4619 mov r1, r3 800a5da: 4851 ldr r0, [pc, #324] @ (800a720 ) 800a5dc: f005 fda0 bl 8010120 /*Configure GPIO pins : DBG2_Pin DBG3_Pin */ GPIO_InitStruct.Pin = DBG2_Pin|DBG3_Pin; 800a5e0: 2360 movs r3, #96 @ 0x60 800a5e2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a5e4: 2301 movs r3, #1 800a5e6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a5e8: 2300 movs r3, #0 800a5ea: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a5ec: 2303 movs r3, #3 800a5ee: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800a5f0: f107 0314 add.w r3, r7, #20 800a5f4: 4619 mov r1, r3 800a5f6: 484a ldr r0, [pc, #296] @ (800a720 ) 800a5f8: f005 fd92 bl 8010120 /*Configure GPIO pins : IN0_Pin AC_OK_Pin ISO_IN_Pin */ GPIO_InitStruct.Pin = IN0_Pin|AC_OK_Pin|ISO_IN_Pin; 800a5fc: f244 0382 movw r3, #16514 @ 0x4082 800a600: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a602: 2300 movs r3, #0 800a604: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a606: 2300 movs r3, #0 800a608: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a60a: f107 0314 add.w r3, r7, #20 800a60e: 4619 mov r1, r3 800a610: 4844 ldr r0, [pc, #272] @ (800a724 ) 800a612: f005 fd85 bl 8010120 /*Configure GPIO pins : RELAY1_Pin RELAY2_Pin RELAY3_Pin RELAY4_Pin RELAY5_Pin */ GPIO_InitStruct.Pin = RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a616: f44f 53f8 mov.w r3, #7936 @ 0x1f00 800a61a: 617b str r3, [r7, #20] |RELAY5_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a61c: 2301 movs r3, #1 800a61e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a620: 2300 movs r3, #0 800a622: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a624: 2302 movs r3, #2 800a626: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a628: f107 0314 add.w r3, r7, #20 800a62c: 4619 mov r1, r3 800a62e: 483d ldr r0, [pc, #244] @ (800a724 ) 800a630: f005 fd76 bl 8010120 /*Configure GPIO pins : DBG5_Pin DBG4_Pin */ GPIO_InitStruct.Pin = DBG5_Pin|DBG4_Pin; 800a634: f44f 6340 mov.w r3, #3072 @ 0xc00 800a638: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a63a: 2301 movs r3, #1 800a63c: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a63e: 2300 movs r3, #0 800a640: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a642: 2303 movs r3, #3 800a644: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a646: f107 0314 add.w r3, r7, #20 800a64a: 4619 mov r1, r3 800a64c: 4836 ldr r0, [pc, #216] @ (800a728 ) 800a64e: f005 fd67 bl 8010120 /*Configure GPIO pin : RELAY_CC_Pin */ GPIO_InitStruct.Pin = RELAY_CC_Pin; 800a652: f44f 4300 mov.w r3, #32768 @ 0x8000 800a656: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a658: 2301 movs r3, #1 800a65a: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a65c: 2300 movs r3, #0 800a65e: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a660: 2302 movs r3, #2 800a662: 623b str r3, [r7, #32] HAL_GPIO_Init(RELAY_CC_GPIO_Port, &GPIO_InitStruct); 800a664: f107 0314 add.w r3, r7, #20 800a668: 4619 mov r1, r3 800a66a: 482d ldr r0, [pc, #180] @ (800a720 ) 800a66c: f005 fd58 bl 8010120 /*Configure GPIO pins : RELAY_DC_Pin USART2_DIR_Pin */ GPIO_InitStruct.Pin = RELAY_DC_Pin|USART2_DIR_Pin; 800a670: 2318 movs r3, #24 800a672: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a674: 2301 movs r3, #1 800a676: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a678: 2300 movs r3, #0 800a67a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a67c: 2302 movs r3, #2 800a67e: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800a680: f107 0314 add.w r3, r7, #20 800a684: 4619 mov r1, r3 800a686: 4829 ldr r0, [pc, #164] @ (800a72c ) 800a688: f005 fd4a bl 8010120 /*Configure GPIO pin : IN_ESTOP_Pin */ GPIO_InitStruct.Pin = IN_ESTOP_Pin; 800a68c: 2380 movs r3, #128 @ 0x80 800a68e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a690: 2300 movs r3, #0 800a692: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a694: 2300 movs r3, #0 800a696: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_ESTOP_GPIO_Port, &GPIO_InitStruct); 800a698: f107 0314 add.w r3, r7, #20 800a69c: 4619 mov r1, r3 800a69e: 4823 ldr r0, [pc, #140] @ (800a72c ) 800a6a0: f005 fd3e bl 8010120 /*Configure GPIO pins : IN_FB2_Pin IN_FB1_Pin */ GPIO_InitStruct.Pin = IN_FB2_Pin|IN_FB1_Pin; 800a6a4: 2318 movs r3, #24 800a6a6: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a6a8: 2300 movs r3, #0 800a6aa: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a6ac: 2300 movs r3, #0 800a6ae: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a6b0: f107 0314 add.w r3, r7, #20 800a6b4: 4619 mov r1, r3 800a6b6: 481c ldr r0, [pc, #112] @ (800a728 ) 800a6b8: f005 fd32 bl 8010120 /*Configure GPIO pin : EE_WP_Pin */ GPIO_InitStruct.Pin = EE_WP_Pin; 800a6bc: 2380 movs r3, #128 @ 0x80 800a6be: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a6c0: 2301 movs r3, #1 800a6c2: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a6c4: 2300 movs r3, #0 800a6c6: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a6c8: 2302 movs r3, #2 800a6ca: 623b str r3, [r7, #32] HAL_GPIO_Init(EE_WP_GPIO_Port, &GPIO_InitStruct); 800a6cc: f107 0314 add.w r3, r7, #20 800a6d0: 4619 mov r1, r3 800a6d2: 4815 ldr r0, [pc, #84] @ (800a728 ) 800a6d4: f005 fd24 bl 8010120 /*Configure GPIO pins : PB8 PB9 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 800a6d8: f44f 7340 mov.w r3, #768 @ 0x300 800a6dc: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 800a6de: 2312 movs r3, #18 800a6e0: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a6e2: 2303 movs r3, #3 800a6e4: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a6e6: f107 0314 add.w r3, r7, #20 800a6ea: 4619 mov r1, r3 800a6ec: 480e ldr r0, [pc, #56] @ (800a728 ) 800a6ee: f005 fd17 bl 8010120 /*Configure peripheral I/O remapping */ __HAL_AFIO_REMAP_I2C1_ENABLE(); 800a6f2: 4b0f ldr r3, [pc, #60] @ (800a730 ) 800a6f4: 685b ldr r3, [r3, #4] 800a6f6: 627b str r3, [r7, #36] @ 0x24 800a6f8: 6a7b ldr r3, [r7, #36] @ 0x24 800a6fa: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800a6fe: 627b str r3, [r7, #36] @ 0x24 800a700: 6a7b ldr r3, [r7, #36] @ 0x24 800a702: f043 0302 orr.w r3, r3, #2 800a706: 627b str r3, [r7, #36] @ 0x24 800a708: 4a09 ldr r2, [pc, #36] @ (800a730 ) 800a70a: 6a7b ldr r3, [r7, #36] @ 0x24 800a70c: 6053 str r3, [r2, #4] } 800a70e: bf00 nop 800a710: 3728 adds r7, #40 @ 0x28 800a712: 46bd mov sp, r7 800a714: bd80 pop {r7, pc} 800a716: bf00 nop 800a718: 40021000 .word 0x40021000 800a71c: 40011000 .word 0x40011000 800a720: 40010800 .word 0x40010800 800a724: 40011800 .word 0x40011800 800a728: 40010c00 .word 0x40010c00 800a72c: 40011400 .word 0x40011400 800a730: 40010000 .word 0x40010000 0800a734 : * bootloader before starting this program. Unfortunately, function * SystemInit() overwrites this change again. * @return none. */ static void VectorBase_Config(void) { 800a734: b480 push {r7} 800a736: af00 add r7, sp, #0 * c-startup code. */ extern const unsigned long g_pfnVectors[]; /* Remap the vector table to where the vector table is located for this program. */ SCB->VTOR = (unsigned long)&g_pfnVectors[0]; 800a738: 4b03 ldr r3, [pc, #12] @ (800a748 ) 800a73a: 4a04 ldr r2, [pc, #16] @ (800a74c ) 800a73c: 609a str r2, [r3, #8] } 800a73e: bf00 nop 800a740: 46bd mov sp, r7 800a742: bc80 pop {r7} 800a744: 4770 bx lr 800a746: bf00 nop 800a748: e000ed00 .word 0xe000ed00 800a74c: 08008000 .word 0x08008000 0800a750 : uint8_t ED_TraceWarning(uint8_t flag, uint8_t id){ 800a750: b480 push {r7} 800a752: b085 sub sp, #20 800a754: af00 add r7, sp, #0 800a756: 4603 mov r3, r0 800a758: 460a mov r2, r1 800a75a: 71fb strb r3, [r7, #7] 800a75c: 4613 mov r3, r2 800a75e: 71bb strb r3, [r7, #6] static uint8_t memory[32]; if(id > 31) return 0; 800a760: 79bb ldrb r3, [r7, #6] 800a762: 2b1f cmp r3, #31 800a764: d901 bls.n 800a76a 800a766: 2300 movs r3, #0 800a768: e00e b.n 800a788 uint8_t result = 0; 800a76a: 2300 movs r3, #0 800a76c: 73fb strb r3, [r7, #15] if(memory[id] != flag){ 800a76e: 79bb ldrb r3, [r7, #6] 800a770: 4a08 ldr r2, [pc, #32] @ (800a794 ) 800a772: 5cd3 ldrb r3, [r2, r3] 800a774: 79fa ldrb r2, [r7, #7] 800a776: 429a cmp r2, r3 800a778: d001 beq.n 800a77e result = 1; 800a77a: 2301 movs r3, #1 800a77c: 73fb strb r3, [r7, #15] } memory[id] = flag; 800a77e: 79bb ldrb r3, [r7, #6] 800a780: 4904 ldr r1, [pc, #16] @ (800a794 ) 800a782: 79fa ldrb r2, [r7, #7] 800a784: 54ca strb r2, [r1, r3] return result; 800a786: 7bfb ldrb r3, [r7, #15] } 800a788: 4618 mov r0, r3 800a78a: 3714 adds r7, #20 800a78c: 46bd mov sp, r7 800a78e: bc80 pop {r7} 800a790: 4770 bx lr 800a792: bf00 nop 800a794: 20000854 .word 0x20000854 0800a798 : void ED_Delay(uint32_t Delay) { 800a798: b580 push {r7, lr} 800a79a: b084 sub sp, #16 800a79c: af00 add r7, sp, #0 800a79e: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800a7a0: f003 fa9a bl 800dcd8 800a7a4: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800a7a6: 687b ldr r3, [r7, #4] 800a7a8: 60fb str r3, [r7, #12] if (wait < HAL_MAX_DELAY) 800a7aa: 68fb ldr r3, [r7, #12] 800a7ac: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800a7b0: d00e beq.n 800a7d0 { wait += (uint32_t)(uwTickFreq); 800a7b2: 4b0e ldr r3, [pc, #56] @ (800a7ec ) 800a7b4: 781b ldrb r3, [r3, #0] 800a7b6: 461a mov r2, r3 800a7b8: 68fb ldr r3, [r7, #12] 800a7ba: 4413 add r3, r2 800a7bc: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait){ 800a7be: e007 b.n 800a7d0 CCS_SerialLoop(); 800a7c0: f001 f974 bl 800baac // CP_Loop(); CONN_Task(); 800a7c4: f7ff fb5c bl 8009e80 LED_Task(); 800a7c8: f000 ff90 bl 800b6ec SC_Task(); 800a7cc: f001 fee2 bl 800c594 while ((HAL_GetTick() - tickstart) < wait){ 800a7d0: f003 fa82 bl 800dcd8 800a7d4: 4602 mov r2, r0 800a7d6: 68bb ldr r3, [r7, #8] 800a7d8: 1ad3 subs r3, r2, r3 800a7da: 68fa ldr r2, [r7, #12] 800a7dc: 429a cmp r2, r3 800a7de: d8ef bhi.n 800a7c0 } } 800a7e0: bf00 nop 800a7e2: bf00 nop 800a7e4: 3710 adds r7, #16 800a7e6: 46bd mov sp, r7 800a7e8: bd80 pop {r7, pc} 800a7ea: bf00 nop 800a7ec: 20000074 .word 0x20000074 0800a7f0 : void StopButtonControl(){ 800a7f0: b580 push {r7, lr} 800a7f2: af00 add r7, sp, #0 //Charging do nothing if(!IN_ReadInput(IN_ESTOP)){ 800a7f4: 2003 movs r0, #3 800a7f6: f7ff f85f bl 80098b8 800a7fa: 4603 mov r3, r0 800a7fc: 2b00 cmp r3, #0 800a7fe: d102 bne.n 800a806 CONN.connControl = CMD_STOP; 800a800: 4b02 ldr r3, [pc, #8] @ (800a80c ) 800a802: 2201 movs r2, #1 800a804: 701a strb r2, [r3, #0] } } 800a806: bf00 nop 800a808: bd80 pop {r7, pc} 800a80a: bf00 nop 800a80c: 20000398 .word 0x20000398 0800a810 : uint8_t temp0, temp1; static void CAN1_MinimalReInit(void) { 800a810: b580 push {r7, lr} 800a812: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan1); 800a814: 480b ldr r0, [pc, #44] @ (800a844 ) 800a816: f004 f9ed bl 800ebf4 MX_CAN1_Init(); 800a81a: f7ff f991 bl 8009b40 if (HAL_CAN_Start(&hcan1) != HAL_OK) { 800a81e: 4809 ldr r0, [pc, #36] @ (800a844 ) 800a820: f004 f9a4 bl 800eb6c 800a824: 4603 mov r3, r0 800a826: 2b00 cmp r3, #0 800a828: d001 beq.n 800a82e Error_Handler(); 800a82a: f000 f8fb bl 800aa24 } if (HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) { 800a82e: 2102 movs r1, #2 800a830: 4804 ldr r0, [pc, #16] @ (800a844 ) 800a832: f004 fc4c bl 800f0ce 800a836: 4603 mov r3, r0 800a838: 2b00 cmp r3, #0 800a83a: d001 beq.n 800a840 Error_Handler(); 800a83c: f000 f8f2 bl 800aa24 } } 800a840: bf00 nop 800a842: bd80 pop {r7, pc} 800a844: 20000344 .word 0x20000344 0800a848
: /** * @brief The application entry point. * @retval int */ int main(void) { 800a848: b580 push {r7, lr} 800a84a: b082 sub sp, #8 800a84c: af02 add r7, sp, #8 /* USER CODE BEGIN 1 */ VectorBase_Config(); 800a84e: f7ff ff71 bl 800a734 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800a852: f003 f9e9 bl 800dc28 /* USER CODE BEGIN Init */ HAL_RCC_DeInit(); 800a856: f005 fedf bl 8010618 /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800a85a: f000 f873 bl 800a944 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800a85e: f7ff fe29 bl 800a4b4 MX_DMA_Init(); 800a862: f7ff fe09 bl 800a478 MX_ADC1_Init(); 800a866: f7fe fe97 bl 8009598 MX_CAN1_Init(); 800a86a: f7ff f969 bl 8009b40 MX_CAN2_Init(); 800a86e: f7ff f99d bl 8009bac MX_RTC_Init(); 800a872: f000 ffd9 bl 800b828 MX_TIM4_Init(); 800a876: f002 fe29 bl 800d4cc MX_USART2_UART_Init(); 800a87a: f002 ffa7 bl 800d7cc MX_CRC_Init(); 800a87e: f7ff fcad bl 800a1dc MX_UART5_Init(); 800a882: f002 ff4f bl 800d724 MX_USART1_UART_Init(); 800a886: f002 ff77 bl 800d778 MX_USART3_UART_Init(); 800a88a: f002 ffc9 bl 800d820 MX_TIM3_Init(); 800a88e: f002 fd8f bl 800d3b0 /* USER CODE BEGIN 2 */ Init_Peripheral(); 800a892: f7ff f863 bl 800995c LED_Init(); 800a896: f000 ff09 bl 800b6ac HAL_Delay(300); 800a89a: f44f 7096 mov.w r0, #300 @ 0x12c 800a89e: f003 fa25 bl 800dcec CCS_Init(); 800a8a2: f001 fb17 bl 800bed4 SC_Init(); 800a8a6: f001 fe49 bl 800c53c log_printf(LOG_INFO, "CCS module start\n"); 800a8aa: 4921 ldr r1, [pc, #132] @ (800a930 ) 800a8ac: 2007 movs r0, #7 800a8ae: f7ff fdad bl 800a40c ReadVersion(); 800a8b2: f001 fe1f bl 800c4f4 log_printf(LOG_INFO, "Serial number: %d\n", infoPacket.serialNumber); 800a8b6: 4b1f ldr r3, [pc, #124] @ (800a934 ) 800a8b8: 881b ldrh r3, [r3, #0] 800a8ba: b29b uxth r3, r3 800a8bc: 461a mov r2, r3 800a8be: 491e ldr r1, [pc, #120] @ (800a938 ) 800a8c0: 2007 movs r0, #7 800a8c2: f7ff fda3 bl 800a40c log_printf(LOG_INFO, "Board revision: %d\n", infoPacket.boardVersion); 800a8c6: 4b1b ldr r3, [pc, #108] @ (800a934 ) 800a8c8: 789b ldrb r3, [r3, #2] 800a8ca: 461a mov r2, r3 800a8cc: 491b ldr r1, [pc, #108] @ (800a93c ) 800a8ce: 2007 movs r0, #7 800a8d0: f7ff fd9c bl 800a40c log_printf(LOG_INFO, "FW version: %d.%d.%d\n", infoPacket.fw_version_major, infoPacket.fw_version_minor, infoPacket.fw_version_patch); 800a8d4: 4b17 ldr r3, [pc, #92] @ (800a934 ) 800a8d6: 889b ldrh r3, [r3, #4] 800a8d8: b29b uxth r3, r3 800a8da: 461a mov r2, r3 800a8dc: 4b15 ldr r3, [pc, #84] @ (800a934 ) 800a8de: 88db ldrh r3, [r3, #6] 800a8e0: b29b uxth r3, r3 800a8e2: 4619 mov r1, r3 800a8e4: 4b13 ldr r3, [pc, #76] @ (800a934 ) 800a8e6: 891b ldrh r3, [r3, #8] 800a8e8: b29b uxth r3, r3 800a8ea: 9300 str r3, [sp, #0] 800a8ec: 460b mov r3, r1 800a8ee: 4914 ldr r1, [pc, #80] @ (800a940 ) 800a8f0: 2007 movs r0, #7 800a8f2: f7ff fd8b bl 800a40c CAN1_MinimalReInit(); 800a8f6: f7ff ff8b bl 800a810 PSU_Init(); 800a8fa: f000 f9ed bl 800acd8 CONN_Init(); 800a8fe: f7ff fa69 bl 8009dd4 /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ PSU_ReadWrite(); 800a902: f000 faf7 bl 800aef4 PSU_Task(); 800a906: f000 fba3 bl 800b050 ED_Delay(10); 800a90a: 200a movs r0, #10 800a90c: f7ff ff44 bl 800a798 METER_CalculateEnergy(); 800a910: f000 f88e bl 800aa30 CONN_Loop(); 800a914: f7ff fa74 bl 8009e00 LED_Write(); 800a918: f000 fd8e bl 800b438 ED_Delay(10); 800a91c: 200a movs r0, #10 800a91e: f7ff ff3b bl 800a798 StopButtonControl(); 800a922: f7ff ff65 bl 800a7f0 ED_Delay(50); 800a926: 2032 movs r0, #50 @ 0x32 800a928: f7ff ff36 bl 800a798 { 800a92c: bf00 nop 800a92e: e7e8 b.n 800a902 800a930: 08016804 .word 0x08016804 800a934: 20001088 .word 0x20001088 800a938: 08016818 .word 0x08016818 800a93c: 0801682c .word 0x0801682c 800a940: 08016840 .word 0x08016840 0800a944 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800a944: b580 push {r7, lr} 800a946: b09c sub sp, #112 @ 0x70 800a948: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800a94a: f107 0338 add.w r3, r7, #56 @ 0x38 800a94e: 2238 movs r2, #56 @ 0x38 800a950: 2100 movs r1, #0 800a952: 4618 mov r0, r3 800a954: f009 fd54 bl 8014400 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800a958: f107 0324 add.w r3, r7, #36 @ 0x24 800a95c: 2200 movs r2, #0 800a95e: 601a str r2, [r3, #0] 800a960: 605a str r2, [r3, #4] 800a962: 609a str r2, [r3, #8] 800a964: 60da str r2, [r3, #12] 800a966: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 800a968: 1d3b adds r3, r7, #4 800a96a: 2220 movs r2, #32 800a96c: 2100 movs r1, #0 800a96e: 4618 mov r0, r3 800a970: f009 fd46 bl 8014400 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; 800a974: 2305 movs r3, #5 800a976: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800a978: f44f 3380 mov.w r3, #65536 @ 0x10000 800a97c: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV5; 800a97e: 2304 movs r3, #4 800a980: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 800a982: 2301 movs r3, #1 800a984: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800a986: 2301 movs r3, #1 800a988: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.Prediv1Source = RCC_PREDIV1_SOURCE_PLL2; 800a98a: f44f 3380 mov.w r3, #65536 @ 0x10000 800a98e: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800a990: 2302 movs r3, #2 800a992: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800a994: f44f 3380 mov.w r3, #65536 @ 0x10000 800a998: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 800a99a: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000 800a99e: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL2.PLL2State = RCC_PLL2_ON; 800a9a0: 2302 movs r3, #2 800a9a2: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL2.PLL2MUL = RCC_PLL2_MUL8; 800a9a4: f44f 63c0 mov.w r3, #1536 @ 0x600 800a9a8: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL2.HSEPrediv2Value = RCC_HSE_PREDIV2_DIV5; 800a9aa: 2340 movs r3, #64 @ 0x40 800a9ac: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800a9ae: f107 0338 add.w r3, r7, #56 @ 0x38 800a9b2: 4618 mov r0, r3 800a9b4: f005 ff00 bl 80107b8 800a9b8: 4603 mov r3, r0 800a9ba: 2b00 cmp r3, #0 800a9bc: d001 beq.n 800a9c2 { Error_Handler(); 800a9be: f000 f831 bl 800aa24 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800a9c2: 230f movs r3, #15 800a9c4: 627b str r3, [r7, #36] @ 0x24 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800a9c6: 2302 movs r3, #2 800a9c8: 62bb str r3, [r7, #40] @ 0x28 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800a9ca: 2300 movs r3, #0 800a9cc: 62fb str r3, [r7, #44] @ 0x2c RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 800a9ce: f44f 6380 mov.w r3, #1024 @ 0x400 800a9d2: 633b str r3, [r7, #48] @ 0x30 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 800a9d4: 2300 movs r3, #0 800a9d6: 637b str r3, [r7, #52] @ 0x34 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800a9d8: f107 0324 add.w r3, r7, #36 @ 0x24 800a9dc: 2102 movs r1, #2 800a9de: 4618 mov r0, r3 800a9e0: f006 fa00 bl 8010de4 800a9e4: 4603 mov r3, r0 800a9e6: 2b00 cmp r3, #0 800a9e8: d001 beq.n 800a9ee { Error_Handler(); 800a9ea: f000 f81b bl 800aa24 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; 800a9ee: 2303 movs r3, #3 800a9f0: 607b str r3, [r7, #4] PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 800a9f2: f44f 7380 mov.w r3, #256 @ 0x100 800a9f6: 60bb str r3, [r7, #8] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 800a9f8: f44f 4300 mov.w r3, #32768 @ 0x8000 800a9fc: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 800a9fe: 1d3b adds r3, r7, #4 800aa00: 4618 mov r0, r3 800aa02: f006 fbe5 bl 80111d0 800aa06: 4603 mov r3, r0 800aa08: 2b00 cmp r3, #0 800aa0a: d001 beq.n 800aa10 { Error_Handler(); 800aa0c: f000 f80a bl 800aa24 } /** Configure the Systick interrupt time */ __HAL_RCC_PLLI2S_ENABLE(); 800aa10: 4b03 ldr r3, [pc, #12] @ (800aa20 ) 800aa12: 2201 movs r2, #1 800aa14: 601a str r2, [r3, #0] } 800aa16: bf00 nop 800aa18: 3770 adds r7, #112 @ 0x70 800aa1a: 46bd mov sp, r7 800aa1c: bd80 pop {r7, pc} 800aa1e: bf00 nop 800aa20: 42420070 .word 0x42420070 0800aa24 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800aa24: b480 push {r7} 800aa26: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800aa28: b672 cpsid i } 800aa2a: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 800aa2c: bf00 nop 800aa2e: e7fd b.n 800aa2c 0800aa30 : METER_t METER; // Функция для расчета и накопления энергии c дробной частью без счетчиков void METER_CalculateEnergy() { 800aa30: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} 800aa34: b084 sub sp, #16 800aa36: af00 add r7, sp, #0 // Проверяем, что индекс находится в пределах массива METER.online = 0; 800aa38: 4b2e ldr r3, [pc, #184] @ (800aaf4 ) 800aa3a: 2200 movs r2, #0 800aa3c: 711a strb r2, [r3, #4] if(CONN.connState == Charging){ 800aa3e: 4b2e ldr r3, [pc, #184] @ (800aaf8 ) 800aa40: 785b ldrb r3, [r3, #1] 800aa42: 2b08 cmp r3, #8 800aa44: d104 bne.n 800aa50 METER.enable = 1; 800aa46: 4b2b ldr r3, [pc, #172] @ (800aaf4 ) 800aa48: 2201 movs r2, #1 800aa4a: f883 2024 strb.w r2, [r3, #36] @ 0x24 800aa4e: e003 b.n 800aa58 }else{ METER.enable = 0; 800aa50: 4b28 ldr r3, [pc, #160] @ (800aaf4 ) 800aa52: 2200 movs r2, #0 800aa54: f883 2024 strb.w r2, [r3, #36] @ 0x24 } uint32_t currentTick = HAL_GetTick(); // Получаем текущее время в миллисекундах 800aa58: f003 f93e bl 800dcd8 800aa5c: 60f8 str r0, [r7, #12] uint32_t elapsedTimeMs = currentTick - METER.lastTick; // Вычисляем время, прошедшее с последнего вызова в секундах 800aa5e: 4b25 ldr r3, [pc, #148] @ (800aaf4 ) 800aa60: 689b ldr r3, [r3, #8] 800aa62: 68fa ldr r2, [r7, #12] 800aa64: 1ad3 subs r3, r2, r3 800aa66: 60bb str r3, [r7, #8] METER.lastTick = currentTick; // Обновляем время последнего вызова для текущего коннектора 800aa68: 4a22 ldr r2, [pc, #136] @ (800aaf4 ) 800aa6a: 68fb ldr r3, [r7, #12] 800aa6c: 6093 str r3, [r2, #8] uint32_t energyWs = CONN.Power * elapsedTimeMs / 1000; // Рассчитываем энергию в ватт-секундах за прошедший промежуток времени 800aa6e: 4b22 ldr r3, [pc, #136] @ (800aaf8 ) 800aa70: f8d3 3003 ldr.w r3, [r3, #3] 800aa74: 68ba ldr r2, [r7, #8] 800aa76: fb02 f303 mul.w r3, r2, r3 800aa7a: 4a20 ldr r2, [pc, #128] @ (800aafc ) 800aa7c: fba2 2303 umull r2, r3, r2, r3 800aa80: 099b lsrs r3, r3, #6 800aa82: 607b str r3, [r7, #4] //Расчет энергии теперь идет всегда, смещение берем суммарное METER.EnergyPSU_Ws += energyWs; 800aa84: 4b1b ldr r3, [pc, #108] @ (800aaf4 ) 800aa86: e9d3 2304 ldrd r2, r3, [r3, #16] 800aa8a: 6879 ldr r1, [r7, #4] 800aa8c: 2000 movs r0, #0 800aa8e: 460c mov r4, r1 800aa90: 4605 mov r5, r0 800aa92: eb12 0804 adds.w r8, r2, r4 800aa96: eb43 0905 adc.w r9, r3, r5 800aa9a: 4b16 ldr r3, [pc, #88] @ (800aaf4 ) 800aa9c: e9c3 8904 strd r8, r9, [r3, #16] // Абсолютное значение энергии разъема складывается из накопленной дробной части и значения со счетчиков METER.AbsoluteEnergy = (uint32_t)METER.EnergyPSU_Ws/3600; //переводим в Вт*час 800aaa0: 4b14 ldr r3, [pc, #80] @ (800aaf4 ) 800aaa2: e9d3 2304 ldrd r2, r3, [r3, #16] 800aaa6: 4b16 ldr r3, [pc, #88] @ (800ab00 ) 800aaa8: fba3 2302 umull r2, r3, r3, r2 800aaac: 0adb lsrs r3, r3, #11 800aaae: 4a11 ldr r2, [pc, #68] @ (800aaf4 ) 800aab0: 6193 str r3, [r2, #24] if(METER.enable) { 800aab2: 4b10 ldr r3, [pc, #64] @ (800aaf4 ) 800aab4: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800aab8: 2b00 cmp r3, #0 800aaba: d008 beq.n 800aace //enabled state CONN.Energy = METER.AbsoluteEnergy - METER.EnergyOffset;//переводим в Вт*час 800aabc: 4b0d ldr r3, [pc, #52] @ (800aaf4 ) 800aabe: 699a ldr r2, [r3, #24] 800aac0: 4b0c ldr r3, [pc, #48] @ (800aaf4 ) 800aac2: 69db ldr r3, [r3, #28] 800aac4: 1ad3 subs r3, r2, r3 800aac6: 4a0c ldr r2, [pc, #48] @ (800aaf8 ) 800aac8: f8c2 3007 str.w r3, [r2, #7] METER.EnergyOffset = METER.AbsoluteEnergy; } } 800aacc: e00c b.n 800aae8 CONN.Energy = 0; 800aace: 4b0a ldr r3, [pc, #40] @ (800aaf8 ) 800aad0: 2200 movs r2, #0 800aad2: 71da strb r2, [r3, #7] 800aad4: 2200 movs r2, #0 800aad6: 721a strb r2, [r3, #8] 800aad8: 2200 movs r2, #0 800aada: 725a strb r2, [r3, #9] 800aadc: 2200 movs r2, #0 800aade: 729a strb r2, [r3, #10] METER.EnergyOffset = METER.AbsoluteEnergy; 800aae0: 4b04 ldr r3, [pc, #16] @ (800aaf4 ) 800aae2: 699b ldr r3, [r3, #24] 800aae4: 4a03 ldr r2, [pc, #12] @ (800aaf4 ) 800aae6: 61d3 str r3, [r2, #28] } 800aae8: bf00 nop 800aaea: 3710 adds r7, #16 800aaec: 46bd mov sp, r7 800aaee: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} 800aaf2: bf00 nop 800aaf4: 20000878 .word 0x20000878 800aaf8: 20000398 .word 0x20000398 800aafc: 10624dd3 .word 0x10624dd3 800ab00: 91a2b3c5 .word 0x91a2b3c5 0800ab04 : uint32_t can_lastpacket; extern CAN_HandleTypeDef hcan2; static void PSU_SwitchState(PSU_State_t state){ 800ab04: b580 push {r7, lr} 800ab06: b082 sub sp, #8 800ab08: af00 add r7, sp, #0 800ab0a: 4603 mov r3, r0 800ab0c: 71fb strb r3, [r7, #7] PSU0.state = state; 800ab0e: 4a06 ldr r2, [pc, #24] @ (800ab28 ) 800ab10: 79fb ldrb r3, [r7, #7] 800ab12: 71d3 strb r3, [r2, #7] PSU0.statetick = HAL_GetTick(); 800ab14: f003 f8e0 bl 800dcd8 800ab18: 4603 mov r3, r0 800ab1a: 4a03 ldr r2, [pc, #12] @ (800ab28 ) 800ab1c: 6113 str r3, [r2, #16] } 800ab1e: bf00 nop 800ab20: 3708 adds r7, #8 800ab22: 46bd mov sp, r7 800ab24: bd80 pop {r7, pc} 800ab26: bf00 nop 800ab28: 200008e4 .word 0x200008e4 0800ab2c : static uint32_t PSU_StateTime(void){ 800ab2c: b580 push {r7, lr} 800ab2e: af00 add r7, sp, #0 return HAL_GetTick() - PSU0.statetick; 800ab30: f003 f8d2 bl 800dcd8 800ab34: 4602 mov r2, r0 800ab36: 4b02 ldr r3, [pc, #8] @ (800ab40 ) 800ab38: 691b ldr r3, [r3, #16] 800ab3a: 1ad3 subs r3, r2, r3 } 800ab3c: 4618 mov r0, r3 800ab3e: bd80 pop {r7, pc} 800ab40: 200008e4 .word 0x200008e4 0800ab44 : ISR_FAST void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan){ 800ab44: b538 push {r3, r4, r5, lr} static CAN_RxHeaderTypeDef RxHeader; static uint8_t RxData[8] = {0,}; CanId_t CanId; if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO1, &RxHeader, RxData) == HAL_OK) 800ab46: 4c42 ldr r4, [pc, #264] @ (800ac50 ) 800ab48: 4d42 ldr r5, [pc, #264] @ (800ac54 ) 800ab4a: 4623 mov r3, r4 800ab4c: 462a mov r2, r5 800ab4e: 2101 movs r1, #1 800ab50: f004 f99c bl 800ee8c 800ab54: b910 cbnz r0, 800ab5c { memcpy(&CanId, &RxHeader.ExtId, sizeof(CanId_t)); 800ab56: 686d ldr r5, [r5, #4] /* Для DC30 поддерживается только один силовой модуль (source == 0) */ if(CanId.source != 0) return; 800ab58: b2eb uxtb r3, r5 800ab5a: b103 cbz r3, 800ab5e CONN.outputEnabled = PSU0.PSU_enabled; } } } } } 800ab5c: bd38 pop {r3, r4, r5, pc} can_lastpacket = HAL_GetTick(); 800ab5e: f003 f8bb bl 800dcd8 if(CanId.command==0x02){ 800ab62: f3c5 4505 ubfx r5, r5, #16, #6 can_lastpacket = HAL_GetTick(); 800ab66: 4b3c ldr r3, [pc, #240] @ (800ac58 ) if(CanId.command==0x02){ 800ab68: 2d02 cmp r5, #2 can_lastpacket = HAL_GetTick(); 800ab6a: 6018 str r0, [r3, #0] if(CanId.command==0x02){ 800ab6c: d013 beq.n 800ab96 if(CanId.command==0x04){ 800ab6e: 2d04 cmp r5, #4 800ab70: d117 bne.n 800aba2 memcpy(&PSU_04, RxData, 8); 800ab72: e894 0003 ldmia.w r4, {r0, r1} 800ab76: 4b39 ldr r3, [pc, #228] @ (800ac5c ) PSU0.tempAmbient = PSU_04.moduleTemperature; 800ab78: 4a39 ldr r2, [pc, #228] @ (800ac60 ) memcpy(&PSU_04, RxData, 8); 800ab7a: e883 0003 stmia.w r3, {r0, r1} PSU0.status0.raw = PSU_04.modularForm0; 800ab7e: 7a18 ldrb r0, [r3, #8] PSU0.tempAmbient = PSU_04.moduleTemperature; 800ab80: 791c ldrb r4, [r3, #4] PSU0.status1.raw = PSU_04.modularForm1; 800ab82: 79d9 ldrb r1, [r3, #7] PSU0.status2.raw = PSU_04.modularForm2; 800ab84: 799b ldrb r3, [r3, #6] PSU0.tempAmbient = PSU_04.moduleTemperature; 800ab86: 61d4 str r4, [r2, #28] PSU0.status0.raw = PSU_04.modularForm0; 800ab88: f882 0020 strb.w r0, [r2, #32] PSU0.status1.raw = PSU_04.modularForm1; 800ab8c: f882 1021 strb.w r1, [r2, #33] @ 0x21 PSU0.status2.raw = PSU_04.modularForm2; 800ab90: f882 3022 strb.w r3, [r2, #34] @ 0x22 } 800ab94: bd38 pop {r3, r4, r5, pc} memcpy(&PSU_02, RxData, 8); 800ab96: 4b33 ldr r3, [pc, #204] @ (800ac64 ) 800ab98: e894 0003 ldmia.w r4, {r0, r1} 800ab9c: e883 0003 stmia.w r3, {r0, r1} } 800aba0: bd38 pop {r3, r4, r5, pc} if(CanId.command==0x06){ 800aba2: 2d06 cmp r5, #6 800aba4: d111 bne.n 800abca memcpy(&PSU_06, RxData, 8); 800aba6: e894 0003 ldmia.w r4, {r0, r1} 800abaa: 4b2f ldr r3, [pc, #188] @ (800ac68 ) 800abac: e883 0003 stmia.w r3, {r0, r1} PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800abb0: 8818 ldrh r0, [r3, #0] PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800abb2: 8859 ldrh r1, [r3, #2] PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800abb4: 889a ldrh r2, [r3, #4] PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800abb6: ba40 rev16 r0, r0 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800abb8: ba49 rev16 r1, r1 PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800abba: ba52 rev16 r2, r2 PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800abbc: b280 uxth r0, r0 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800abbe: b289 uxth r1, r1 PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800abc0: b292 uxth r2, r2 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800abc2: e9c3 0102 strd r0, r1, [r3, #8] PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800abc6: 611a str r2, [r3, #16] } 800abc8: bd38 pop {r3, r4, r5, pc} if(CanId.command==0x08){ 800abca: 2d08 cmp r5, #8 800abcc: d03a beq.n 800ac44 if(CanId.command==0x09){ 800abce: 2d09 cmp r5, #9 800abd0: d1c4 bne.n 800ab5c memcpy(&PSU_09, RxData, 8); 800abd2: e894 0003 ldmia.w r4, {r0, r1} PSU0.temperature = PSU_04.moduleTemperature; 800abd6: 4b21 ldr r3, [pc, #132] @ (800ac5c ) memcpy(&PSU_09, RxData, 8); 800abd8: 4d24 ldr r5, [pc, #144] @ (800ac6c ) PSU0.outputVoltage = v; 800abda: 4c21 ldr r4, [pc, #132] @ (800ac60 ) PSU0.temperature = PSU_04.moduleTemperature; 800abdc: f893 c004 ldrb.w ip, [r3, #4] uint16_t v = PSU_09.moduleNVoltage / 1000; 800abe0: 4a23 ldr r2, [pc, #140] @ (800ac70 ) memcpy(&PSU_09, RxData, 8); 800abe2: e885 0003 stmia.w r5, {r0, r1} PSU_09.moduleNCurrent = PSU_09.moduleNCurrent_[3]; 800abe6: ba00 rev r0, r0 PSU0.temperature = PSU_04.moduleTemperature; 800abe8: f884 c006 strb.w ip, [r4, #6] uint16_t v = PSU_09.moduleNVoltage / 1000; 800abec: fba2 c200 umull ip, r2, r2, r0 800abf0: ba09 rev r1, r1 PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[0]<<24; 800abf2: e9c5 0102 strd r0, r1, [r5, #8] uint16_t v = PSU_09.moduleNVoltage / 1000; 800abf6: f3c2 108f ubfx r0, r2, #6, #16 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800abfa: 2813 cmp r0, #19 PSU0.online = 1; 800abfc: f04f 0e01 mov.w lr, #1 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800ac00: bf94 ite ls 800ac02: 2500 movls r5, #0 800ac04: 2501 movhi r5, #1 int16_t i = PSU_09.moduleNCurrent / 100; 800ac06: 4b1b ldr r3, [pc, #108] @ (800ac74 ) PSU0.online = 1; 800ac08: f884 e008 strb.w lr, [r4, #8] int16_t i = PSU_09.moduleNCurrent / 100; 800ac0c: fba3 c301 umull ip, r3, r3, r1 if(PSU0.state >= PSU_READY){ 800ac10: 79e1 ldrb r1, [r4, #7] int16_t i = PSU_09.moduleNCurrent / 100; 800ac12: 095b lsrs r3, r3, #5 if(PSU0.state >= PSU_READY){ 800ac14: 4571 cmp r1, lr PSU0.outputVoltage = v; 800ac16: 8060 strh r0, [r4, #2] int16_t i = PSU_09.moduleNCurrent / 100; 800ac18: 80a3 strh r3, [r4, #4] uint16_t v = PSU_09.moduleNVoltage / 1000; 800ac1a: ea4f 1292 mov.w r2, r2, lsr #6 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800ac1e: 72a5 strb r5, [r4, #10] if(PSU0.state >= PSU_READY){ 800ac20: d99c bls.n 800ab5c CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800ac22: b299 uxth r1, r3 800ac24: b292 uxth r2, r2 800ac26: fb01 f202 mul.w r2, r1, r2 800ac2a: 4c13 ldr r4, [pc, #76] @ (800ac78 ) CONN.MeasuredVoltage = PSU0.outputVoltage; 800ac2c: 4913 ldr r1, [pc, #76] @ (800ac7c ) CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800ac2e: fba4 4202 umull r4, r2, r4, r2 CONN.MeasuredCurrent = PSU0.outputCurrent; 800ac32: f8a1 3015 strh.w r3, [r1, #21] CONN.outputEnabled = PSU0.PSU_enabled; 800ac36: 760d strb r5, [r1, #24] CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800ac38: 08d3 lsrs r3, r2, #3 CONN.MeasuredVoltage = PSU0.outputVoltage; 800ac3a: f8a1 0013 strh.w r0, [r1, #19] CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800ac3e: f8c1 3003 str.w r3, [r1, #3] } 800ac42: bd38 pop {r3, r4, r5, pc} memcpy(&PSU_08, RxData, 8); 800ac44: 4b0e ldr r3, [pc, #56] @ (800ac80 ) 800ac46: e894 0003 ldmia.w r4, {r0, r1} 800ac4a: e883 0003 stmia.w r3, {r0, r1} } 800ac4e: bd38 pop {r3, r4, r5, pc} 800ac50: 20000928 .word 0x20000928 800ac54: 2000090c .word 0x2000090c 800ac58: 20000908 .word 0x20000908 800ac5c: 200008ac .word 0x200008ac 800ac60: 200008e4 .word 0x200008e4 800ac64: 200008a0 .word 0x200008a0 800ac68: 200008b8 .word 0x200008b8 800ac6c: 200008d4 .word 0x200008d4 800ac70: 10624dd3 .word 0x10624dd3 800ac74: 51eb851f .word 0x51eb851f 800ac78: cccccccd .word 0xcccccccd 800ac7c: 20000398 .word 0x20000398 800ac80: 200008cc .word 0x200008cc 0800ac84 : void PSU_CAN_FilterInit(){ 800ac84: b580 push {r7, lr} 800ac86: b08a sub sp, #40 @ 0x28 800ac88: af00 add r7, sp, #0 CAN_FilterTypeDef sFilterConfig; sFilterConfig.FilterBank = 14; 800ac8a: 230e movs r3, #14 800ac8c: 617b str r3, [r7, #20] sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; 800ac8e: 2300 movs r3, #0 800ac90: 61bb str r3, [r7, #24] sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; 800ac92: 2301 movs r3, #1 800ac94: 61fb str r3, [r7, #28] sFilterConfig.FilterIdHigh = 0x0000; 800ac96: 2300 movs r3, #0 800ac98: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = 0x0000; 800ac9a: 2300 movs r3, #0 800ac9c: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 800ac9e: 2300 movs r3, #0 800aca0: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = 0x0000; 800aca2: 2300 movs r3, #0 800aca4: 60fb str r3, [r7, #12] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; 800aca6: 2300 movs r3, #0 800aca8: 613b str r3, [r7, #16] sFilterConfig.FilterActivation = ENABLE; 800acaa: 2301 movs r3, #1 800acac: 623b str r3, [r7, #32] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 800acae: 2301 movs r3, #1 800acb0: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 800acb2: 230e movs r3, #14 800acb4: 627b str r3, [r7, #36] @ 0x24 if(HAL_CAN_ConfigFilter(&hcan2, &sFilterConfig) != HAL_OK) 800acb6: 463b mov r3, r7 800acb8: 4619 mov r1, r3 800acba: 4806 ldr r0, [pc, #24] @ (800acd4 ) 800acbc: f003 fe76 bl 800e9ac 800acc0: 4603 mov r3, r0 800acc2: 2b00 cmp r3, #0 800acc4: d001 beq.n 800acca { Error_Handler(); 800acc6: f7ff fead bl 800aa24 } } 800acca: bf00 nop 800accc: 3728 adds r7, #40 @ 0x28 800acce: 46bd mov sp, r7 800acd0: bd80 pop {r7, pc} 800acd2: bf00 nop 800acd4: 2000036c .word 0x2000036c 0800acd8 : void PSU_Init(){ 800acd8: b580 push {r7, lr} 800acda: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan2); 800acdc: 4813 ldr r0, [pc, #76] @ (800ad2c ) 800acde: f003 ff89 bl 800ebf4 MX_CAN2_Init(); 800ace2: f7fe ff63 bl 8009bac PSU_CAN_FilterInit(); 800ace6: f7ff ffcd bl 800ac84 HAL_CAN_Start(&hcan2); 800acea: 4810 ldr r0, [pc, #64] @ (800ad2c ) 800acec: f003 ff3e bl 800eb6c HAL_CAN_ActivateNotification(&hcan2, CAN_IT_RX_FIFO1_MSG_PENDING /* | CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | CAN_IT_TX_MAILBOX_EMPTY*/); 800acf0: 2110 movs r1, #16 800acf2: 480e ldr r0, [pc, #56] @ (800ad2c ) 800acf4: f004 f9eb bl 800f0ce memset(&PSU0, 0, sizeof(PSU0)); 800acf8: 2224 movs r2, #36 @ 0x24 800acfa: 2100 movs r1, #0 800acfc: 480c ldr r0, [pc, #48] @ (800ad30 ) 800acfe: f009 fb7f bl 8014400 PSU0.state = PSU_UNREADY; 800ad02: 4b0b ldr r3, [pc, #44] @ (800ad30 ) 800ad04: 2200 movs r2, #0 800ad06: 71da strb r2, [r3, #7] PSU0.statetick = HAL_GetTick(); 800ad08: f002 ffe6 bl 800dcd8 800ad0c: 4603 mov r3, r0 800ad0e: 4a08 ldr r2, [pc, #32] @ (800ad30 ) 800ad10: 6113 str r3, [r2, #16] PSU0.power_limit = PSU_MAX_POWER; // kW 800ad12: 4b07 ldr r3, [pc, #28] @ (800ad30 ) 800ad14: f247 5230 movw r2, #30000 @ 0x7530 800ad18: 615a str r2, [r3, #20] PSU0.hv_mode = 0; 800ad1a: 4b05 ldr r3, [pc, #20] @ (800ad30 ) 800ad1c: 2200 movs r2, #0 800ad1e: 761a strb r2, [r3, #24] PSU_Enable(0, 0); 800ad20: 2100 movs r1, #0 800ad22: 2000 movs r0, #0 800ad24: f000 f806 bl 800ad34 } 800ad28: bf00 nop 800ad2a: bd80 pop {r7, pc} 800ad2c: 2000036c .word 0x2000036c 800ad30: 200008e4 .word 0x200008e4 0800ad34 : void PSU_Enable(uint8_t addr, uint8_t enable){ 800ad34: b580 push {r7, lr} 800ad36: b084 sub sp, #16 800ad38: af00 add r7, sp, #0 800ad3a: 4603 mov r3, r0 800ad3c: 460a mov r2, r1 800ad3e: 71fb strb r3, [r7, #7] 800ad40: 4613 mov r3, r2 800ad42: 71bb strb r3, [r7, #6] PSU_1A_t data; memset(&data, 0, sizeof(data)); 800ad44: f107 0308 add.w r3, r7, #8 800ad48: 2208 movs r2, #8 800ad4a: 2100 movs r1, #0 800ad4c: 4618 mov r0, r3 800ad4e: f009 fb57 bl 8014400 /* Для DC30 поддерживается только один модуль с адресом 0 */ if(addr != 0) return; 800ad52: 79fb ldrb r3, [r7, #7] 800ad54: 2b00 cmp r3, #0 800ad56: d115 bne.n 800ad84 if(PSU0.online == 0) return; 800ad58: 4b0d ldr r3, [pc, #52] @ (800ad90 ) 800ad5a: 7a1b ldrb r3, [r3, #8] 800ad5c: 2b00 cmp r3, #0 800ad5e: d013 beq.n 800ad88 data.enable = !enable; 800ad60: 79bb ldrb r3, [r7, #6] 800ad62: 2b00 cmp r3, #0 800ad64: bf0c ite eq 800ad66: 2301 moveq r3, #1 800ad68: 2300 movne r3, #0 800ad6a: b2db uxtb r3, r3 800ad6c: 723b strb r3, [r7, #8] PSU_SendCmd(0xF0, addr, 0x1A, &data); 800ad6e: 79f9 ldrb r1, [r7, #7] 800ad70: f107 0308 add.w r3, r7, #8 800ad74: 221a movs r2, #26 800ad76: 20f0 movs r0, #240 @ 0xf0 800ad78: f000 f866 bl 800ae48 ED_Delay(CAN_DELAY); 800ad7c: 2014 movs r0, #20 800ad7e: f7ff fd0b bl 800a798 800ad82: e002 b.n 800ad8a if(addr != 0) return; 800ad84: bf00 nop 800ad86: e000 b.n 800ad8a if(PSU0.online == 0) return; 800ad88: bf00 nop } 800ad8a: 3710 adds r7, #16 800ad8c: 46bd mov sp, r7 800ad8e: bd80 pop {r7, pc} 800ad90: 200008e4 .word 0x200008e4 0800ad94 : memset(&data, 0, sizeof(data)); data.enable = !enable; if(addr != 0) return; PSU_SendCmd(0xF0, addr, 0x1D, &data); } void PSU_SetVoltageCurrent(uint8_t addr, uint16_t voltage, uint16_t current){ 800ad94: b580 push {r7, lr} 800ad96: b086 sub sp, #24 800ad98: af00 add r7, sp, #0 800ad9a: 4603 mov r3, r0 800ad9c: 71fb strb r3, [r7, #7] 800ad9e: 460b mov r3, r1 800ada0: 80bb strh r3, [r7, #4] 800ada2: 4613 mov r3, r2 800ada4: 807b strh r3, [r7, #2] PSU_1C_t data; memset(&data, 0, sizeof(data)); 800ada6: f107 0308 add.w r3, r7, #8 800adaa: 2208 movs r2, #8 800adac: 2100 movs r1, #0 800adae: 4618 mov r0, r3 800adb0: f009 fb26 bl 8014400 if(addr != 0) return; 800adb4: 79fb ldrb r3, [r7, #7] 800adb6: 2b00 cmp r3, #0 800adb8: d140 bne.n 800ae3c if(voltage 800adc0: 2396 movs r3, #150 @ 0x96 800adc2: 80bb strh r3, [r7, #4] if((PSU0.hv_mode==0) && voltage>499) voltage = 499; 800adc4: 4b1f ldr r3, [pc, #124] @ (800ae44 ) 800adc6: 7e1b ldrb r3, [r3, #24] 800adc8: 2b00 cmp r3, #0 800adca: d106 bne.n 800adda 800adcc: 88bb ldrh r3, [r7, #4] 800adce: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800add2: d302 bcc.n 800adda 800add4: f240 13f3 movw r3, #499 @ 0x1f3 800add8: 80bb strh r3, [r7, #4] uint32_t current_ma = current * 100; 800adda: 887b ldrh r3, [r7, #2] 800addc: 2264 movs r2, #100 @ 0x64 800adde: fb02 f303 mul.w r3, r2, r3 800ade2: 617b str r3, [r7, #20] uint32_t voltage_mv = voltage * 1000; 800ade4: 88bb ldrh r3, [r7, #4] 800ade6: f44f 727a mov.w r2, #1000 @ 0x3e8 800adea: fb02 f303 mul.w r3, r2, r3 800adee: 613b str r3, [r7, #16] data.moduleCurrentTotal[0] = (current_ma >> 24) & 0xFF; 800adf0: 697b ldr r3, [r7, #20] 800adf2: 0e1b lsrs r3, r3, #24 800adf4: b2db uxtb r3, r3 800adf6: 733b strb r3, [r7, #12] data.moduleCurrentTotal[1] = (current_ma >> 16) & 0xFF; 800adf8: 697b ldr r3, [r7, #20] 800adfa: 0c1b lsrs r3, r3, #16 800adfc: b2db uxtb r3, r3 800adfe: 737b strb r3, [r7, #13] data.moduleCurrentTotal[2] = (current_ma >> 8) & 0xFF; 800ae00: 697b ldr r3, [r7, #20] 800ae02: 0a1b lsrs r3, r3, #8 800ae04: b2db uxtb r3, r3 800ae06: 73bb strb r3, [r7, #14] data.moduleCurrentTotal[3] = (current_ma >> 0) & 0xFF; 800ae08: 697b ldr r3, [r7, #20] 800ae0a: b2db uxtb r3, r3 800ae0c: 73fb strb r3, [r7, #15] data.moduleVoltage[0] = (voltage_mv >> 24) & 0xFF; 800ae0e: 693b ldr r3, [r7, #16] 800ae10: 0e1b lsrs r3, r3, #24 800ae12: b2db uxtb r3, r3 800ae14: 723b strb r3, [r7, #8] data.moduleVoltage[1] = (voltage_mv >> 16) & 0xFF; 800ae16: 693b ldr r3, [r7, #16] 800ae18: 0c1b lsrs r3, r3, #16 800ae1a: b2db uxtb r3, r3 800ae1c: 727b strb r3, [r7, #9] data.moduleVoltage[2] = (voltage_mv >> 8) & 0xFF; 800ae1e: 693b ldr r3, [r7, #16] 800ae20: 0a1b lsrs r3, r3, #8 800ae22: b2db uxtb r3, r3 800ae24: 72bb strb r3, [r7, #10] data.moduleVoltage[3] = (voltage_mv >> 0) & 0xFF; 800ae26: 693b ldr r3, [r7, #16] 800ae28: b2db uxtb r3, r3 800ae2a: 72fb strb r3, [r7, #11] PSU_SendCmd(0xF0, addr, 0x1C, &data); 800ae2c: 79f9 ldrb r1, [r7, #7] 800ae2e: f107 0308 add.w r3, r7, #8 800ae32: 221c movs r2, #28 800ae34: 20f0 movs r0, #240 @ 0xf0 800ae36: f000 f807 bl 800ae48 800ae3a: e000 b.n 800ae3e if(addr != 0) return; 800ae3c: bf00 nop } 800ae3e: 3718 adds r7, #24 800ae40: 46bd mov sp, r7 800ae42: bd80 pop {r7, pc} 800ae44: 200008e4 .word 0x200008e4 0800ae48 : void PSU_SendCmd(uint8_t source, uint8_t destination, uint8_t cmd, void *data){ 800ae48: b580 push {r7, lr} 800ae4a: b08c sub sp, #48 @ 0x30 800ae4c: af00 add r7, sp, #0 800ae4e: 603b str r3, [r7, #0] 800ae50: 4603 mov r3, r0 800ae52: 71fb strb r3, [r7, #7] 800ae54: 460b mov r3, r1 800ae56: 71bb strb r3, [r7, #6] 800ae58: 4613 mov r3, r2 800ae5a: 717b strb r3, [r7, #5] CanId_t CanId; CanId.source = source; 800ae5c: 79fb ldrb r3, [r7, #7] 800ae5e: f887 3028 strb.w r3, [r7, #40] @ 0x28 CanId.destination = destination; 800ae62: 79bb ldrb r3, [r7, #6] 800ae64: f887 3029 strb.w r3, [r7, #41] @ 0x29 CanId.command = cmd; 800ae68: 797b ldrb r3, [r7, #5] 800ae6a: f003 033f and.w r3, r3, #63 @ 0x3f 800ae6e: b2da uxtb r2, r3 800ae70: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 800ae74: f362 0305 bfi r3, r2, #0, #6 800ae78: f887 302a strb.w r3, [r7, #42] @ 0x2a CanId.device = 0x0A; 800ae7c: 8d7b ldrh r3, [r7, #42] @ 0x2a 800ae7e: 220a movs r2, #10 800ae80: f362 1389 bfi r3, r2, #6, #4 800ae84: 857b strh r3, [r7, #42] @ 0x2a int8_t retry_counter = 10; 800ae86: 230a movs r3, #10 800ae88: f887 302f strb.w r3, [r7, #47] @ 0x2f CAN_TxHeaderTypeDef tx_header; uint32_t tx_mailbox; HAL_StatusTypeDef CAN_result; memcpy(&tx_header.ExtId, &CanId, sizeof(CanId_t)); 800ae8c: 6abb ldr r3, [r7, #40] @ 0x28 800ae8e: 617b str r3, [r7, #20] tx_header.RTR = CAN_RTR_DATA; 800ae90: 2300 movs r3, #0 800ae92: 61fb str r3, [r7, #28] tx_header.IDE = CAN_ID_EXT; 800ae94: 2304 movs r3, #4 800ae96: 61bb str r3, [r7, #24] tx_header.DLC = 8; 800ae98: 2308 movs r3, #8 800ae9a: 623b str r3, [r7, #32] while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800ae9c: e01e b.n 800aedc if (HAL_CAN_GetTxMailboxesFreeLevel(&hcan2) > 0){ 800ae9e: 4814 ldr r0, [pc, #80] @ (800aef0 ) 800aea0: f003 ffc0 bl 800ee24 800aea4: 4603 mov r3, r0 800aea6: 2b00 cmp r3, #0 800aea8: d00e beq.n 800aec8 /* отправка сообщения */ CAN_result = HAL_CAN_AddTxMessage(&hcan2, &tx_header, (uint8_t*)data, &tx_mailbox); 800aeaa: f107 030c add.w r3, r7, #12 800aeae: f107 0110 add.w r1, r7, #16 800aeb2: 683a ldr r2, [r7, #0] 800aeb4: 480e ldr r0, [pc, #56] @ (800aef0 ) 800aeb6: f003 fee6 bl 800ec86 800aeba: 4603 mov r3, r0 800aebc: f887 302e strb.w r3, [r7, #46] @ 0x2e /* если отправка удалась, выход */ if(CAN_result == HAL_OK) { 800aec0: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 800aec4: 2b00 cmp r3, #0 800aec6: d00e beq.n 800aee6 return; retry_counter = 0; } } ED_Delay(1); 800aec8: 2001 movs r0, #1 800aeca: f7ff fc65 bl 800a798 retry_counter--; 800aece: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800aed2: b2db uxtb r3, r3 800aed4: 3b01 subs r3, #1 800aed6: b2db uxtb r3, r3 800aed8: f887 302f strb.w r3, [r7, #47] @ 0x2f while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800aedc: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800aee0: 2b00 cmp r3, #0 800aee2: dcdc bgt.n 800ae9e 800aee4: e000 b.n 800aee8 return; 800aee6: bf00 nop } } 800aee8: 3730 adds r7, #48 @ 0x30 800aeea: 46bd mov sp, r7 800aeec: bd80 pop {r7, pc} 800aeee: bf00 nop 800aef0: 2000036c .word 0x2000036c 0800aef4 : uint32_t max(uint32_t a, uint32_t b){ if(a>b) return a; else return b; } void PSU_ReadWrite(){ 800aef4: b580 push {r7, lr} 800aef6: b082 sub sp, #8 800aef8: af00 add r7, sp, #0 uint8_t zero_data[8] = {0,0,0,0,0,0,0,0}; 800aefa: 463b mov r3, r7 800aefc: 2200 movs r2, #0 800aefe: 601a str r2, [r3, #0] 800af00: 605a str r2, [r3, #4] PSU_SendCmd(0xF0, 0, 0x04, zero_data);ED_Delay(CAN_DELAY); 800af02: 463b mov r3, r7 800af04: 2204 movs r2, #4 800af06: 2100 movs r1, #0 800af08: 20f0 movs r0, #240 @ 0xf0 800af0a: f7ff ff9d bl 800ae48 800af0e: 2014 movs r0, #20 800af10: f7ff fc42 bl 800a798 PSU_SendCmd(0xF0, 0, 0x06, zero_data);ED_Delay(CAN_DELAY); 800af14: 463b mov r3, r7 800af16: 2206 movs r2, #6 800af18: 2100 movs r1, #0 800af1a: 20f0 movs r0, #240 @ 0xf0 800af1c: f7ff ff94 bl 800ae48 800af20: 2014 movs r0, #20 800af22: f7ff fc39 bl 800a798 // PSU_SendCmd(0xF0, 0, 0x08, zero_data);ED_Delay(CAN_DELAY); PSU_SendCmd(0xF0, 0, 0x09, zero_data);ED_Delay(CAN_DELAY); 800af26: 463b mov r3, r7 800af28: 2209 movs r2, #9 800af2a: 2100 movs r1, #0 800af2c: 20f0 movs r0, #240 @ 0xf0 800af2e: f7ff ff8b bl 800ae48 800af32: 2014 movs r0, #20 800af34: f7ff fc30 bl 800a798 // Power Limit if ((CONN.WantedCurrent/10) * CONN.MeasuredVoltage > PSU0.power_limit){ 800af38: 4b41 ldr r3, [pc, #260] @ (800b040 ) 800af3a: f8b3 301b ldrh.w r3, [r3, #27] 800af3e: b29b uxth r3, r3 800af40: 4a40 ldr r2, [pc, #256] @ (800b044 ) 800af42: fba2 2303 umull r2, r3, r2, r3 800af46: 08db lsrs r3, r3, #3 800af48: b29b uxth r3, r3 800af4a: 461a mov r2, r3 800af4c: 4b3c ldr r3, [pc, #240] @ (800b040 ) 800af4e: f8b3 3013 ldrh.w r3, [r3, #19] 800af52: b29b uxth r3, r3 800af54: fb02 f303 mul.w r3, r2, r3 800af58: 461a mov r2, r3 800af5a: 4b3b ldr r3, [pc, #236] @ (800b048 ) 800af5c: 695b ldr r3, [r3, #20] 800af5e: 429a cmp r2, r3 800af60: d911 bls.n 800af86 CONN.RequestedCurrent = PSU0.power_limit * 10 / CONN.MeasuredVoltage; 800af62: 4b39 ldr r3, [pc, #228] @ (800b048 ) 800af64: 695a ldr r2, [r3, #20] 800af66: 4613 mov r3, r2 800af68: 009b lsls r3, r3, #2 800af6a: 4413 add r3, r2 800af6c: 005b lsls r3, r3, #1 800af6e: 461a mov r2, r3 800af70: 4b33 ldr r3, [pc, #204] @ (800b040 ) 800af72: f8b3 3013 ldrh.w r3, [r3, #19] 800af76: b29b uxth r3, r3 800af78: fbb2 f3f3 udiv r3, r2, r3 800af7c: b29a uxth r2, r3 800af7e: 4b30 ldr r3, [pc, #192] @ (800b040 ) 800af80: f8a3 2011 strh.w r2, [r3, #17] 800af84: e006 b.n 800af94 }else{ CONN.RequestedCurrent = CONN.WantedCurrent; 800af86: 4b2e ldr r3, [pc, #184] @ (800b040 ) 800af88: f8b3 301b ldrh.w r3, [r3, #27] 800af8c: b29a uxth r2, r3 800af8e: 4b2c ldr r3, [pc, #176] @ (800b040 ) 800af90: f8a3 2011 strh.w r2, [r3, #17] } if(CONN.RequestedCurrent > (PSU_MAX_CURRENT*10)){ 800af94: 4b2a ldr r3, [pc, #168] @ (800b040 ) 800af96: f8b3 3011 ldrh.w r3, [r3, #17] 800af9a: b29b uxth r3, r3 800af9c: f240 5232 movw r2, #1330 @ 0x532 800afa0: 4293 cmp r3, r2 800afa2: d908 bls.n 800afb6 CONN.RequestedCurrent = PSU_MAX_CURRENT*10; 800afa4: 4b26 ldr r3, [pc, #152] @ (800b040 ) 800afa6: 2200 movs r2, #0 800afa8: f042 0232 orr.w r2, r2, #50 @ 0x32 800afac: 745a strb r2, [r3, #17] 800afae: 2200 movs r2, #0 800afb0: f042 0205 orr.w r2, r2, #5 800afb4: 749a strb r2, [r3, #18] } CONN.RequestedPower = CONN.RequestedCurrent * CONN.RequestedVoltage / 10; 800afb6: 4b22 ldr r3, [pc, #136] @ (800b040 ) 800afb8: f8b3 3011 ldrh.w r3, [r3, #17] 800afbc: b29b uxth r3, r3 800afbe: 461a mov r2, r3 800afc0: 4b1f ldr r3, [pc, #124] @ (800b040 ) 800afc2: f8b3 300f ldrh.w r3, [r3, #15] 800afc6: b29b uxth r3, r3 800afc8: fb02 f303 mul.w r3, r2, r3 800afcc: 4a1f ldr r2, [pc, #124] @ (800b04c ) 800afce: fb82 1203 smull r1, r2, r2, r3 800afd2: 1092 asrs r2, r2, #2 800afd4: 17db asrs r3, r3, #31 800afd6: 1ad3 subs r3, r2, r3 800afd8: 461a mov r2, r3 800afda: 4b19 ldr r3, [pc, #100] @ (800b040 ) 800afdc: f8c3 200b str.w r2, [r3, #11] if(PSU0.ready){ 800afe0: 4b19 ldr r3, [pc, #100] @ (800b048 ) 800afe2: 7a5b ldrb r3, [r3, #9] 800afe4: 2b00 cmp r3, #0 800afe6: d026 beq.n 800b036 if (CONN.RequestedVoltage == 500) { // fake 800afe8: 4b15 ldr r3, [pc, #84] @ (800b040 ) 800afea: f8b3 300f ldrh.w r3, [r3, #15] 800afee: b29b uxth r3, r3 800aff0: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800aff4: d106 bne.n 800b004 PSU_SetVoltageCurrent(0, 300, 10); // Normal mode 800aff6: 220a movs r2, #10 800aff8: f44f 7196 mov.w r1, #300 @ 0x12c 800affc: 2000 movs r0, #0 800affe: f7ff fec9 bl 800ad94 800b002: e00b b.n 800b01c }else{ PSU_SetVoltageCurrent(0, CONN.RequestedVoltage, CONN.RequestedCurrent); // Normal mode 800b004: 4b0e ldr r3, [pc, #56] @ (800b040 ) 800b006: f8b3 300f ldrh.w r3, [r3, #15] 800b00a: b29b uxth r3, r3 800b00c: 4a0c ldr r2, [pc, #48] @ (800b040 ) 800b00e: f8b2 2011 ldrh.w r2, [r2, #17] 800b012: b292 uxth r2, r2 800b014: 4619 mov r1, r3 800b016: 2000 movs r0, #0 800b018: f7ff febc bl 800ad94 } ED_Delay(CAN_DELAY); 800b01c: 2014 movs r0, #20 800b01e: f7ff fbbb bl 800a798 if(CONN.MeasuredVoltage>490) PSU0.hv_mode = 1; 800b022: 4b07 ldr r3, [pc, #28] @ (800b040 ) 800b024: f8b3 3013 ldrh.w r3, [r3, #19] 800b028: b29b uxth r3, r3 800b02a: f5b3 7ff5 cmp.w r3, #490 @ 0x1ea 800b02e: d902 bls.n 800b036 800b030: 4b05 ldr r3, [pc, #20] @ (800b048 ) 800b032: 2201 movs r2, #1 800b034: 761a strb r2, [r3, #24] } // PSU_SetHVMode(0, PSU0.hv_mode); // auto set, no need // ED_Delay(CAN_DELAY); } 800b036: bf00 nop 800b038: 3708 adds r7, #8 800b03a: 46bd mov sp, r7 800b03c: bd80 pop {r7, pc} 800b03e: bf00 nop 800b040: 20000398 .word 0x20000398 800b044: cccccccd .word 0xcccccccd 800b048: 200008e4 .word 0x200008e4 800b04c: 66666667 .word 0x66666667 0800b050 : void PSU_Task(void){ 800b050: b598 push {r3, r4, r7, lr} 800b052: af00 add r7, sp, #0 static uint32_t psu_on_tick = 0; static uint32_t dc_on_tick = 0; static uint32_t cont_ok_tick = 0; // Обновляем ONLINE/READY по таймауту if((HAL_GetTick() - can_lastpacket) > PSU_ONLINE_TIMEOUT){ 800b054: f002 fe40 bl 800dcd8 800b058: 4602 mov r2, r0 800b05a: 4bb4 ldr r3, [pc, #720] @ (800b32c ) 800b05c: 681b ldr r3, [r3, #0] 800b05e: 1ad3 subs r3, r2, r3 800b060: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b064: d920 bls.n 800b0a8 PSU0.online = 0; 800b066: 4bb2 ldr r3, [pc, #712] @ (800b330 ) 800b068: 2200 movs r2, #0 800b06a: 721a strb r2, [r3, #8] PSU0.PSU_enabled = 0; 800b06c: 4bb0 ldr r3, [pc, #704] @ (800b330 ) 800b06e: 2200 movs r2, #0 800b070: 729a strb r2, [r3, #10] PSU_04.moduleTemperature = 0; 800b072: 4bb0 ldr r3, [pc, #704] @ (800b334 ) 800b074: 2200 movs r2, #0 800b076: 711a strb r2, [r3, #4] PSU_04.modularForm0 = 0; 800b078: 4bae ldr r3, [pc, #696] @ (800b334 ) 800b07a: 2200 movs r2, #0 800b07c: 721a strb r2, [r3, #8] PSU_04.modularForm1 = 0; 800b07e: 4bad ldr r3, [pc, #692] @ (800b334 ) 800b080: 2200 movs r2, #0 800b082: 71da strb r2, [r3, #7] PSU_04.modularForm2 = 0; 800b084: 4bab ldr r3, [pc, #684] @ (800b334 ) 800b086: 2200 movs r2, #0 800b088: 719a strb r2, [r3, #6] PSU_06.VAB = 0; 800b08a: 4bab ldr r3, [pc, #684] @ (800b338 ) 800b08c: 2200 movs r2, #0 800b08e: 609a str r2, [r3, #8] PSU_06.VBC = 0; 800b090: 4ba9 ldr r3, [pc, #676] @ (800b338 ) 800b092: 2200 movs r2, #0 800b094: 60da str r2, [r3, #12] PSU_06.VCA = 0; 800b096: 4ba8 ldr r3, [pc, #672] @ (800b338 ) 800b098: 2200 movs r2, #0 800b09a: 611a str r2, [r3, #16] PSU_09.moduleNCurrent = 0; 800b09c: 4ba7 ldr r3, [pc, #668] @ (800b33c ) 800b09e: 2200 movs r2, #0 800b0a0: 60da str r2, [r3, #12] PSU_09.moduleNVoltage = 0; 800b0a2: 4ba6 ldr r3, [pc, #664] @ (800b33c ) 800b0a4: 2200 movs r2, #0 800b0a6: 609a str r2, [r3, #8] } if(!PSU0.online || !PSU0.enableAC){ 800b0a8: 4ba1 ldr r3, [pc, #644] @ (800b330 ) 800b0aa: 7a1b ldrb r3, [r3, #8] 800b0ac: 2b00 cmp r3, #0 800b0ae: d003 beq.n 800b0b8 800b0b0: 4b9f ldr r3, [pc, #636] @ (800b330 ) 800b0b2: 781b ldrb r3, [r3, #0] 800b0b4: 2b00 cmp r3, #0 800b0b6: d10c bne.n 800b0d2 CONN.MeasuredVoltage = 0; 800b0b8: 4ba1 ldr r3, [pc, #644] @ (800b340 ) 800b0ba: 2200 movs r2, #0 800b0bc: 74da strb r2, [r3, #19] 800b0be: 2200 movs r2, #0 800b0c0: 751a strb r2, [r3, #20] CONN.MeasuredCurrent = 0; 800b0c2: 4b9f ldr r3, [pc, #636] @ (800b340 ) 800b0c4: 2200 movs r2, #0 800b0c6: 755a strb r2, [r3, #21] 800b0c8: 2200 movs r2, #0 800b0ca: 759a strb r2, [r3, #22] CONN.outputEnabled = 0; 800b0cc: 4b9c ldr r3, [pc, #624] @ (800b340 ) 800b0ce: 2200 movs r2, #0 800b0d0: 761a strb r2, [r3, #24] } // Управление AC-контактором с задержкой отключения 1 минута if(CONN.EvConnected){ 800b0d2: 4b9b ldr r3, [pc, #620] @ (800b340 ) 800b0d4: 7f9b ldrb r3, [r3, #30] 800b0d6: 2b00 cmp r3, #0 800b0d8: d00c beq.n 800b0f4 RELAY_Write(RELAY_AC, 1); 800b0da: 2101 movs r1, #1 800b0dc: 2004 movs r0, #4 800b0de: f7fe fb6b bl 80097b8 psu_on_tick = HAL_GetTick(); 800b0e2: f002 fdf9 bl 800dcd8 800b0e6: 4603 mov r3, r0 800b0e8: 4a96 ldr r2, [pc, #600] @ (800b344 ) 800b0ea: 6013 str r3, [r2, #0] PSU0.enableAC = 1; 800b0ec: 4b90 ldr r3, [pc, #576] @ (800b330 ) 800b0ee: 2201 movs r2, #1 800b0f0: 701a strb r2, [r3, #0] 800b0f2: e010 b.n 800b116 }else{ if((HAL_GetTick() - psu_on_tick) > 1 * 60000){ 800b0f4: f002 fdf0 bl 800dcd8 800b0f8: 4602 mov r2, r0 800b0fa: 4b92 ldr r3, [pc, #584] @ (800b344 ) 800b0fc: 681b ldr r3, [r3, #0] 800b0fe: 1ad3 subs r3, r2, r3 800b100: f64e 2260 movw r2, #60000 @ 0xea60 800b104: 4293 cmp r3, r2 800b106: d906 bls.n 800b116 RELAY_Write(RELAY_AC, 0); 800b108: 2100 movs r1, #0 800b10a: 2004 movs r0, #4 800b10c: f7fe fb54 bl 80097b8 PSU0.enableAC = 0; 800b110: 4b87 ldr r3, [pc, #540] @ (800b330 ) 800b112: 2200 movs r2, #0 800b114: 701a strb r2, [r3, #0] } } // Текущее состояние DC-контактора по обратной связи PSU0.CONT_enabled = IN_ReadInput(IN_CONT_FB_DC); 800b116: 2005 movs r0, #5 800b118: f7fe fbce bl 80098b8 800b11c: 4603 mov r3, r0 800b11e: 461a mov r2, r3 800b120: 4b83 ldr r3, [pc, #524] @ (800b330 ) 800b122: 72da strb r2, [r3, #11] // Обновляем ready с учётом ошибок if(PSU0.online && !PSU0.cont_fault && PSU0.enableAC){ 800b124: 4b82 ldr r3, [pc, #520] @ (800b330 ) 800b126: 7a1b ldrb r3, [r3, #8] 800b128: 2b00 cmp r3, #0 800b12a: d007 beq.n 800b13c 800b12c: 4b80 ldr r3, [pc, #512] @ (800b330 ) 800b12e: 7b1b ldrb r3, [r3, #12] 800b130: 2b00 cmp r3, #0 800b132: d103 bne.n 800b13c 800b134: 4b7e ldr r3, [pc, #504] @ (800b330 ) 800b136: 781b ldrb r3, [r3, #0] 800b138: 2b00 cmp r3, #0 800b13a: d102 bne.n 800b142 // PSU0.ready = 1; }else{ PSU0.ready = 0; 800b13c: 4b7c ldr r3, [pc, #496] @ (800b330 ) 800b13e: 2200 movs r2, #0 800b140: 725a strb r2, [r3, #9] } switch(PSU0.state){ 800b142: 4b7b ldr r3, [pc, #492] @ (800b330 ) 800b144: 79db ldrb r3, [r3, #7] 800b146: 2b09 cmp r3, #9 800b148: f200 8155 bhi.w 800b3f6 800b14c: a201 add r2, pc, #4 @ (adr r2, 800b154 ) 800b14e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b152: bf00 nop 800b154: 0800b17d .word 0x0800b17d 800b158: 0800b1b1 .word 0x0800b1b1 800b15c: 0800b1cd .word 0x0800b1cd 800b160: 0800b205 .word 0x0800b205 800b164: 0800b253 .word 0x0800b253 800b168: 0800b295 .word 0x0800b295 800b16c: 0800b2ff .word 0x0800b2ff 800b170: 0800b3a9 .word 0x0800b3a9 800b174: 0800b359 .word 0x0800b359 800b178: 0800b3e3 .word 0x0800b3e3 case PSU_UNREADY: PSU0.enableOutput = 0; 800b17c: 4b6c ldr r3, [pc, #432] @ (800b330 ) 800b17e: 2200 movs r2, #0 800b180: 705a strb r2, [r3, #1] RELAY_Write(RELAY_DC, 0); 800b182: 2100 movs r1, #0 800b184: 2003 movs r0, #3 800b186: f7fe fb17 bl 80097b8 if(PSU0.online && PSU0.enableAC && !PSU0.cont_fault){ 800b18a: 4b69 ldr r3, [pc, #420] @ (800b330 ) 800b18c: 7a1b ldrb r3, [r3, #8] 800b18e: 2b00 cmp r3, #0 800b190: f000 8135 beq.w 800b3fe 800b194: 4b66 ldr r3, [pc, #408] @ (800b330 ) 800b196: 781b ldrb r3, [r3, #0] 800b198: 2b00 cmp r3, #0 800b19a: f000 8130 beq.w 800b3fe 800b19e: 4b64 ldr r3, [pc, #400] @ (800b330 ) 800b1a0: 7b1b ldrb r3, [r3, #12] 800b1a2: 2b00 cmp r3, #0 800b1a4: f040 812b bne.w 800b3fe PSU_SwitchState(PSU_INITIALIZING); 800b1a8: 2001 movs r0, #1 800b1aa: f7ff fcab bl 800ab04 } break; 800b1ae: e126 b.n 800b3fe case PSU_INITIALIZING: if(PSU_StateTime() > 4000){ // Wait 4s for PSU to initialize 800b1b0: f7ff fcbc bl 800ab2c 800b1b4: 4603 mov r3, r0 800b1b6: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b1ba: f240 8122 bls.w 800b402 PSU0.ready = 1; 800b1be: 4b5c ldr r3, [pc, #368] @ (800b330 ) 800b1c0: 2201 movs r2, #1 800b1c2: 725a strb r2, [r3, #9] PSU_SwitchState(PSU_READY); 800b1c4: 2002 movs r0, #2 800b1c6: f7ff fc9d bl 800ab04 } break; 800b1ca: e11a b.n 800b402 case PSU_READY: // модуль готов, но выключен PSU0.hv_mode = 0; 800b1cc: 4b58 ldr r3, [pc, #352] @ (800b330 ) 800b1ce: 2200 movs r2, #0 800b1d0: 761a strb r2, [r3, #24] RELAY_Write(RELAY_DC, 0); 800b1d2: 2100 movs r1, #0 800b1d4: 2003 movs r0, #3 800b1d6: f7fe faef bl 80097b8 if(!PSU0.ready){ 800b1da: 4b55 ldr r3, [pc, #340] @ (800b330 ) 800b1dc: 7a5b ldrb r3, [r3, #9] 800b1de: 2b00 cmp r3, #0 800b1e0: d103 bne.n 800b1ea PSU_SwitchState(PSU_UNREADY); 800b1e2: 2000 movs r0, #0 800b1e4: f7ff fc8e bl 800ab04 break; 800b1e8: e11c b.n 800b424 } if(CONN.EnableOutput){ 800b1ea: 4b55 ldr r3, [pc, #340] @ (800b340 ) 800b1ec: 7ddb ldrb r3, [r3, #23] 800b1ee: 2b00 cmp r3, #0 800b1f0: f000 8109 beq.w 800b406 PSU_Enable(0, 1); 800b1f4: 2101 movs r1, #1 800b1f6: 2000 movs r0, #0 800b1f8: f7ff fd9c bl 800ad34 PSU_SwitchState(PSU_WAIT_ACK_ON); 800b1fc: 2003 movs r0, #3 800b1fe: f7ff fc81 bl 800ab04 } break; 800b202: e100 b.n 800b406 case PSU_WAIT_ACK_ON: if(PSU0.PSU_enabled && PSU0.ready){ 800b204: 4b4a ldr r3, [pc, #296] @ (800b330 ) 800b206: 7a9b ldrb r3, [r3, #10] 800b208: 2b00 cmp r3, #0 800b20a: d00c beq.n 800b226 800b20c: 4b48 ldr r3, [pc, #288] @ (800b330 ) 800b20e: 7a5b ldrb r3, [r3, #9] 800b210: 2b00 cmp r3, #0 800b212: d008 beq.n 800b226 dc_on_tick = HAL_GetTick(); 800b214: f002 fd60 bl 800dcd8 800b218: 4603 mov r3, r0 800b21a: 4a4b ldr r2, [pc, #300] @ (800b348 ) 800b21c: 6013 str r3, [r2, #0] PSU_SwitchState(PSU_CONT_WAIT_ACK_ON); 800b21e: 2004 movs r0, #4 800b220: f7ff fc70 bl 800ab04 PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU on timeout\n"); } break; 800b224: e0f1 b.n 800b40a }else if(PSU_StateTime() > 10000){ 800b226: f7ff fc81 bl 800ab2c 800b22a: 4603 mov r3, r0 800b22c: f242 7210 movw r2, #10000 @ 0x2710 800b230: 4293 cmp r3, r2 800b232: f240 80ea bls.w 800b40a PSU0.psu_fault = 1; 800b236: 4b3e ldr r3, [pc, #248] @ (800b330 ) 800b238: 2201 movs r2, #1 800b23a: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b23c: 4b40 ldr r3, [pc, #256] @ (800b340 ) 800b23e: 220a movs r2, #10 800b240: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b242: 2000 movs r0, #0 800b244: f7ff fc5e bl 800ab04 log_printf(LOG_ERR, "PSU on timeout\n"); 800b248: 4940 ldr r1, [pc, #256] @ (800b34c ) 800b24a: 2004 movs r0, #4 800b24c: f7ff f8de bl 800a40c break; 800b250: e0db b.n 800b40a case PSU_CONT_WAIT_ACK_ON: // замыкаем DC-контактор и ждём подтверждение RELAY_Write(RELAY_DC, 1); 800b252: 2101 movs r1, #1 800b254: 2003 movs r0, #3 800b256: f7fe faaf bl 80097b8 if(PSU0.CONT_enabled){ 800b25a: 4b35 ldr r3, [pc, #212] @ (800b330 ) 800b25c: 7adb ldrb r3, [r3, #11] 800b25e: 2b00 cmp r3, #0 800b260: d003 beq.n 800b26a PSU_SwitchState(PSU_CONNECTED); 800b262: 2005 movs r0, #5 800b264: f7ff fc4e bl 800ab04 PSU0.cont_fault = 1; CONN.chargingError = CONN_ERR_CONTACTOR; PSU_SwitchState(PSU_CURRENT_DROP); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b268: e0d1 b.n 800b40e }else if(PSU_StateTime() > 1000){ 800b26a: f7ff fc5f bl 800ab2c 800b26e: 4603 mov r3, r0 800b270: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b274: f240 80cb bls.w 800b40e PSU0.cont_fault = 1; 800b278: 4b2d ldr r3, [pc, #180] @ (800b330 ) 800b27a: 2201 movs r2, #1 800b27c: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b27e: 4b30 ldr r3, [pc, #192] @ (800b340 ) 800b280: 2207 movs r2, #7 800b282: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_CURRENT_DROP); 800b284: 2006 movs r0, #6 800b286: f7ff fc3d bl 800ab04 log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b28a: 4931 ldr r1, [pc, #196] @ (800b350 ) 800b28c: 2004 movs r0, #4 800b28e: f7ff f8bd bl 800a40c break; 800b292: e0bc b.n 800b40e case PSU_CONNECTED: // Основное рабочее состояние if(!CONN.EnableOutput || !PSU0.ready){ 800b294: 4b2a ldr r3, [pc, #168] @ (800b340 ) 800b296: 7ddb ldrb r3, [r3, #23] 800b298: 2b00 cmp r3, #0 800b29a: d003 beq.n 800b2a4 800b29c: 4b24 ldr r3, [pc, #144] @ (800b330 ) 800b29e: 7a5b ldrb r3, [r3, #9] 800b2a0: 2b00 cmp r3, #0 800b2a2: d103 bne.n 800b2ac PSU_SwitchState(PSU_CURRENT_DROP); 800b2a4: 2006 movs r0, #6 800b2a6: f7ff fc2d bl 800ab04 break; 800b2aa: e0bb b.n 800b424 } // контроль контактора: 1 c таймаут if (IN_ReadInput(IN_CONT_FB_DC) != RELAY_Read(RELAY_DC)){ 800b2ac: 2005 movs r0, #5 800b2ae: f7fe fb03 bl 80098b8 800b2b2: 4603 mov r3, r0 800b2b4: 461c mov r4, r3 800b2b6: 2003 movs r0, #3 800b2b8: f7fe faee bl 8009898 800b2bc: 4603 mov r3, r0 800b2be: 429c cmp r4, r3 800b2c0: d017 beq.n 800b2f2 if((HAL_GetTick() - cont_ok_tick) > 1000){ 800b2c2: f002 fd09 bl 800dcd8 800b2c6: 4602 mov r2, r0 800b2c8: 4b22 ldr r3, [pc, #136] @ (800b354 ) 800b2ca: 681b ldr r3, [r3, #0] 800b2cc: 1ad3 subs r3, r2, r3 800b2ce: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b2d2: f240 809e bls.w 800b412 CONN.chargingError = CONN_ERR_CONTACTOR; 800b2d6: 4b1a ldr r3, [pc, #104] @ (800b340 ) 800b2d8: 2207 movs r2, #7 800b2da: 775a strb r2, [r3, #29] PSU0.cont_fault = 1; 800b2dc: 4b14 ldr r3, [pc, #80] @ (800b330 ) 800b2de: 2201 movs r2, #1 800b2e0: 731a strb r2, [r3, #12] PSU_SwitchState(PSU_CURRENT_DROP); 800b2e2: 2006 movs r0, #6 800b2e4: f7ff fc0e bl 800ab04 log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b2e8: 4919 ldr r1, [pc, #100] @ (800b350 ) 800b2ea: 2004 movs r0, #4 800b2ec: f7ff f88e bl 800a40c } }else{ cont_ok_tick = HAL_GetTick(); } break; 800b2f0: e08f b.n 800b412 cont_ok_tick = HAL_GetTick(); 800b2f2: f002 fcf1 bl 800dcd8 800b2f6: 4603 mov r3, r0 800b2f8: 4a16 ldr r2, [pc, #88] @ (800b354 ) 800b2fa: 6013 str r3, [r2, #0] break; 800b2fc: e089 b.n 800b412 case PSU_CURRENT_DROP: // снижаем ток до нуля перед отключением DC CONN.RequestedCurrent = 0; 800b2fe: 4b10 ldr r3, [pc, #64] @ (800b340 ) 800b300: 2200 movs r2, #0 800b302: 745a strb r2, [r3, #17] 800b304: 2200 movs r2, #0 800b306: 749a strb r2, [r3, #18] // если ток действительно упал или вышло время, отключаем DC if((CONN.MeasuredCurrent < 30) || (PSU_StateTime() > 5000)){ 800b308: 4b0d ldr r3, [pc, #52] @ (800b340 ) 800b30a: f8b3 3015 ldrh.w r3, [r3, #21] 800b30e: b29b uxth r3, r3 800b310: 2b1d cmp r3, #29 800b312: d906 bls.n 800b322 800b314: f7ff fc0a bl 800ab2c 800b318: 4603 mov r3, r0 800b31a: f241 3288 movw r2, #5000 @ 0x1388 800b31e: 4293 cmp r3, r2 800b320: d979 bls.n 800b416 PSU_SwitchState(PSU_CONT_WAIT_ACK_OFF); 800b322: 2008 movs r0, #8 800b324: f7ff fbee bl 800ab04 } break; 800b328: e075 b.n 800b416 800b32a: bf00 nop 800b32c: 20000908 .word 0x20000908 800b330: 200008e4 .word 0x200008e4 800b334: 200008ac .word 0x200008ac 800b338: 200008b8 .word 0x200008b8 800b33c: 200008d4 .word 0x200008d4 800b340: 20000398 .word 0x20000398 800b344: 20000930 .word 0x20000930 800b348: 20000934 .word 0x20000934 800b34c: 08016858 .word 0x08016858 800b350: 08016868 .word 0x08016868 800b354: 20000938 .word 0x20000938 case PSU_CONT_WAIT_ACK_OFF: RELAY_Write(RELAY_DC, 0); 800b358: 2100 movs r1, #0 800b35a: 2003 movs r0, #3 800b35c: f7fe fa2c bl 80097b8 if(!PSU0.CONT_enabled){ 800b360: 4b31 ldr r3, [pc, #196] @ (800b428 ) 800b362: 7adb ldrb r3, [r3, #11] 800b364: 2b00 cmp r3, #0 800b366: d107 bne.n 800b378 PSU_Enable(0, 0); 800b368: 2100 movs r1, #0 800b36a: 2000 movs r0, #0 800b36c: f7ff fce2 bl 800ad34 PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b370: 2007 movs r0, #7 800b372: f7ff fbc7 bl 800ab04 CONN.chargingError = CONN_ERR_CONTACTOR; PSU_Enable(0, 0); PSU_SwitchState(PSU_WAIT_ACK_OFF); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b376: e050 b.n 800b41a }else if(PSU_StateTime() > 1000){ 800b378: f7ff fbd8 bl 800ab2c 800b37c: 4603 mov r3, r0 800b37e: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b382: d94a bls.n 800b41a PSU0.cont_fault = 1; 800b384: 4b28 ldr r3, [pc, #160] @ (800b428 ) 800b386: 2201 movs r2, #1 800b388: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b38a: 4b28 ldr r3, [pc, #160] @ (800b42c ) 800b38c: 2207 movs r2, #7 800b38e: 775a strb r2, [r3, #29] PSU_Enable(0, 0); 800b390: 2100 movs r1, #0 800b392: 2000 movs r0, #0 800b394: f7ff fcce bl 800ad34 PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b398: 2007 movs r0, #7 800b39a: f7ff fbb3 bl 800ab04 log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b39e: 4924 ldr r1, [pc, #144] @ (800b430 ) 800b3a0: 2004 movs r0, #4 800b3a2: f7ff f833 bl 800a40c break; 800b3a6: e038 b.n 800b41a case PSU_WAIT_ACK_OFF: if(!PSU0.PSU_enabled){ 800b3a8: 4b1f ldr r3, [pc, #124] @ (800b428 ) 800b3aa: 7a9b ldrb r3, [r3, #10] 800b3ac: 2b00 cmp r3, #0 800b3ae: d103 bne.n 800b3b8 PSU_SwitchState(PSU_OFF_PAUSE); 800b3b0: 2009 movs r0, #9 800b3b2: f7ff fba7 bl 800ab04 PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU off timeout\n"); } break; 800b3b6: e032 b.n 800b41e }else if(PSU_StateTime() > 10000){ 800b3b8: f7ff fbb8 bl 800ab2c 800b3bc: 4603 mov r3, r0 800b3be: f242 7210 movw r2, #10000 @ 0x2710 800b3c2: 4293 cmp r3, r2 800b3c4: d92b bls.n 800b41e PSU0.psu_fault = 1; 800b3c6: 4b18 ldr r3, [pc, #96] @ (800b428 ) 800b3c8: 2201 movs r2, #1 800b3ca: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b3cc: 4b17 ldr r3, [pc, #92] @ (800b42c ) 800b3ce: 220a movs r2, #10 800b3d0: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b3d2: 2000 movs r0, #0 800b3d4: f7ff fb96 bl 800ab04 log_printf(LOG_ERR, "PSU off timeout\n"); 800b3d8: 4916 ldr r1, [pc, #88] @ (800b434 ) 800b3da: 2004 movs r0, #4 800b3dc: f7ff f816 bl 800a40c break; 800b3e0: e01d b.n 800b41e case PSU_OFF_PAUSE: if(PSU_StateTime() > 4000){ 800b3e2: f7ff fba3 bl 800ab2c 800b3e6: 4603 mov r3, r0 800b3e8: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b3ec: d919 bls.n 800b422 PSU_SwitchState(PSU_READY); 800b3ee: 2002 movs r0, #2 800b3f0: f7ff fb88 bl 800ab04 } break; 800b3f4: e015 b.n 800b422 default: PSU_SwitchState(PSU_UNREADY); 800b3f6: 2000 movs r0, #0 800b3f8: f7ff fb84 bl 800ab04 break; 800b3fc: e012 b.n 800b424 break; 800b3fe: bf00 nop 800b400: e010 b.n 800b424 break; 800b402: bf00 nop 800b404: e00e b.n 800b424 break; 800b406: bf00 nop 800b408: e00c b.n 800b424 break; 800b40a: bf00 nop 800b40c: e00a b.n 800b424 break; 800b40e: bf00 nop 800b410: e008 b.n 800b424 break; 800b412: bf00 nop 800b414: e006 b.n 800b424 break; 800b416: bf00 nop 800b418: e004 b.n 800b424 break; 800b41a: bf00 nop 800b41c: e002 b.n 800b424 break; 800b41e: bf00 nop 800b420: e000 b.n 800b424 break; 800b422: bf00 nop } } 800b424: bf00 nop 800b426: bd98 pop {r3, r4, r7, pc} 800b428: 200008e4 .word 0x200008e4 800b42c: 20000398 .word 0x20000398 800b430: 08016868 .word 0x08016868 800b434: 08016888 .word 0x08016888 0800b438 : .Th = 10, .Tf = 50, .Tl = 0, }; void LED_Write(){ 800b438: b580 push {r7, lr} 800b43a: af00 add r7, sp, #0 if(CONN.chargingError != CONN_NO_ERROR){ 800b43c: 4b34 ldr r3, [pc, #208] @ (800b510 ) 800b43e: 7f5b ldrb r3, [r3, #29] 800b440: 2b00 cmp r3, #0 800b442: d003 beq.n 800b44c LED_SetColor(&color_error); 800b444: 4833 ldr r0, [pc, #204] @ (800b514 ) 800b446: f000 f91f bl 800b688 return; 800b44a: e05f b.n 800b50c } switch(CONN.connState){ 800b44c: 4b30 ldr r3, [pc, #192] @ (800b510 ) 800b44e: 785b ldrb r3, [r3, #1] 800b450: 2b0d cmp r3, #13 800b452: d857 bhi.n 800b504 800b454: a201 add r2, pc, #4 @ (adr r2, 800b45c ) 800b456: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b45a: bf00 nop 800b45c: 0800b495 .word 0x0800b495 800b460: 0800b49d .word 0x0800b49d 800b464: 0800b4a5 .word 0x0800b4a5 800b468: 0800b4ad .word 0x0800b4ad 800b46c: 0800b4b5 .word 0x0800b4b5 800b470: 0800b4bd .word 0x0800b4bd 800b474: 0800b4c5 .word 0x0800b4c5 800b478: 0800b4cd .word 0x0800b4cd 800b47c: 0800b4d5 .word 0x0800b4d5 800b480: 0800b4dd .word 0x0800b4dd 800b484: 0800b4e5 .word 0x0800b4e5 800b488: 0800b4ed .word 0x0800b4ed 800b48c: 0800b4f5 .word 0x0800b4f5 800b490: 0800b4fd .word 0x0800b4fd case Unknown: LED_SetColor(&color_unknown); 800b494: 4820 ldr r0, [pc, #128] @ (800b518 ) 800b496: f000 f8f7 bl 800b688 break; 800b49a: e037 b.n 800b50c case Unplugged: LED_SetColor(&color_unplugged); 800b49c: 481f ldr r0, [pc, #124] @ (800b51c ) 800b49e: f000 f8f3 bl 800b688 break; 800b4a2: e033 b.n 800b50c case Disabled: LED_SetColor(&color_error); 800b4a4: 481b ldr r0, [pc, #108] @ (800b514 ) 800b4a6: f000 f8ef bl 800b688 break; 800b4aa: e02f b.n 800b50c case Preparing: LED_SetColor(&color_preparing); 800b4ac: 481c ldr r0, [pc, #112] @ (800b520 ) 800b4ae: f000 f8eb bl 800b688 break; 800b4b2: e02b b.n 800b50c case AuthRequired: LED_SetColor(&color_preparing); 800b4b4: 481a ldr r0, [pc, #104] @ (800b520 ) 800b4b6: f000 f8e7 bl 800b688 break; 800b4ba: e027 b.n 800b50c case WaitingForEnergy: LED_SetColor(&color_charging); 800b4bc: 4819 ldr r0, [pc, #100] @ (800b524 ) 800b4be: f000 f8e3 bl 800b688 break; 800b4c2: e023 b.n 800b50c case ChargingPausedEV: LED_SetColor(&color_charging); 800b4c4: 4817 ldr r0, [pc, #92] @ (800b524 ) 800b4c6: f000 f8df bl 800b688 break; 800b4ca: e01f b.n 800b50c case ChargingPausedEVSE: LED_SetColor(&color_charging); 800b4cc: 4815 ldr r0, [pc, #84] @ (800b524 ) 800b4ce: f000 f8db bl 800b688 break; 800b4d2: e01b b.n 800b50c case Charging: LED_SetColor(&color_charging); 800b4d4: 4813 ldr r0, [pc, #76] @ (800b524 ) 800b4d6: f000 f8d7 bl 800b688 break; 800b4da: e017 b.n 800b50c case AuthTimeout: LED_SetColor(&color_finished); 800b4dc: 4812 ldr r0, [pc, #72] @ (800b528 ) 800b4de: f000 f8d3 bl 800b688 break; 800b4e2: e013 b.n 800b50c case Finished: LED_SetColor(&color_finished); 800b4e4: 4810 ldr r0, [pc, #64] @ (800b528 ) 800b4e6: f000 f8cf bl 800b688 break; 800b4ea: e00f b.n 800b50c case FinishedEVSE: LED_SetColor(&color_finished); 800b4ec: 480e ldr r0, [pc, #56] @ (800b528 ) 800b4ee: f000 f8cb bl 800b688 break; 800b4f2: e00b b.n 800b50c case FinishedEV: LED_SetColor(&color_finished); 800b4f4: 480c ldr r0, [pc, #48] @ (800b528 ) 800b4f6: f000 f8c7 bl 800b688 break; 800b4fa: e007 b.n 800b50c case Replugging: LED_SetColor(&color_preparing); 800b4fc: 4808 ldr r0, [pc, #32] @ (800b520 ) 800b4fe: f000 f8c3 bl 800b688 break; 800b502: e003 b.n 800b50c default: LED_SetColor(&color_unknown); 800b504: 4804 ldr r0, [pc, #16] @ (800b518 ) 800b506: f000 f8bf bl 800b688 break; 800b50a: bf00 nop } } 800b50c: bd80 pop {r7, pc} 800b50e: bf00 nop 800b510: 20000398 .word 0x20000398 800b514: 20000044 .word 0x20000044 800b518: 20000008 .word 0x20000008 800b51c: 20000014 .word 0x20000014 800b520: 20000020 .word 0x20000020 800b524: 2000002c .word 0x2000002c 800b528: 20000038 .word 0x20000038 0800b52c : void interpolateColors(RGB_t* color1, RGB_t* color2, uint16_t a, uint16_t b, RGB_t *result) { 800b52c: b480 push {r7} 800b52e: b087 sub sp, #28 800b530: af00 add r7, sp, #0 800b532: 60f8 str r0, [r7, #12] 800b534: 60b9 str r1, [r7, #8] 800b536: 4611 mov r1, r2 800b538: 461a mov r2, r3 800b53a: 460b mov r3, r1 800b53c: 80fb strh r3, [r7, #6] 800b53e: 4613 mov r3, r2 800b540: 80bb strh r3, [r7, #4] // Проверяем, чтобы a не выходила за пределы диапазона if (a > b) a = b; 800b542: 88fa ldrh r2, [r7, #6] 800b544: 88bb ldrh r3, [r7, #4] 800b546: 429a cmp r2, r3 800b548: d901 bls.n 800b54e 800b54a: 88bb ldrh r3, [r7, #4] 800b54c: 80fb strh r3, [r7, #6] if(b==0) b = 1; 800b54e: 88bb ldrh r3, [r7, #4] 800b550: 2b00 cmp r3, #0 800b552: d101 bne.n 800b558 800b554: 2301 movs r3, #1 800b556: 80bb strh r3, [r7, #4] // Вычисляем коэффициент смешивания в виде целого числа uint16_t t = (a * 255) / b; // t будет от 0 до 255 800b558: 88fa ldrh r2, [r7, #6] 800b55a: 4613 mov r3, r2 800b55c: 021b lsls r3, r3, #8 800b55e: 1a9a subs r2, r3, r2 800b560: 88bb ldrh r3, [r7, #4] 800b562: fb92 f3f3 sdiv r3, r2, r3 800b566: 82fb strh r3, [r7, #22] // Линейная интерполяция с использованием целых чисел result->R = (color1->R * (255 - t) + color2->R * t) / 255; 800b568: 68fb ldr r3, [r7, #12] 800b56a: 781b ldrb r3, [r3, #0] 800b56c: 461a mov r2, r3 800b56e: 8afb ldrh r3, [r7, #22] 800b570: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b574: fb03 f202 mul.w r2, r3, r2 800b578: 68bb ldr r3, [r7, #8] 800b57a: 781b ldrb r3, [r3, #0] 800b57c: 4619 mov r1, r3 800b57e: 8afb ldrh r3, [r7, #22] 800b580: fb01 f303 mul.w r3, r1, r3 800b584: 4413 add r3, r2 800b586: 4a20 ldr r2, [pc, #128] @ (800b608 ) 800b588: fb82 1203 smull r1, r2, r2, r3 800b58c: 441a add r2, r3 800b58e: 11d2 asrs r2, r2, #7 800b590: 17db asrs r3, r3, #31 800b592: 1ad3 subs r3, r2, r3 800b594: b2da uxtb r2, r3 800b596: 6a3b ldr r3, [r7, #32] 800b598: 701a strb r2, [r3, #0] result->G = (color1->G * (255 - t) + color2->G * t) / 255; 800b59a: 68fb ldr r3, [r7, #12] 800b59c: 785b ldrb r3, [r3, #1] 800b59e: 461a mov r2, r3 800b5a0: 8afb ldrh r3, [r7, #22] 800b5a2: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b5a6: fb03 f202 mul.w r2, r3, r2 800b5aa: 68bb ldr r3, [r7, #8] 800b5ac: 785b ldrb r3, [r3, #1] 800b5ae: 4619 mov r1, r3 800b5b0: 8afb ldrh r3, [r7, #22] 800b5b2: fb01 f303 mul.w r3, r1, r3 800b5b6: 4413 add r3, r2 800b5b8: 4a13 ldr r2, [pc, #76] @ (800b608 ) 800b5ba: fb82 1203 smull r1, r2, r2, r3 800b5be: 441a add r2, r3 800b5c0: 11d2 asrs r2, r2, #7 800b5c2: 17db asrs r3, r3, #31 800b5c4: 1ad3 subs r3, r2, r3 800b5c6: b2da uxtb r2, r3 800b5c8: 6a3b ldr r3, [r7, #32] 800b5ca: 705a strb r2, [r3, #1] result->B = (color1->B * (255 - t) + color2->B * t) / 255; 800b5cc: 68fb ldr r3, [r7, #12] 800b5ce: 789b ldrb r3, [r3, #2] 800b5d0: 461a mov r2, r3 800b5d2: 8afb ldrh r3, [r7, #22] 800b5d4: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b5d8: fb03 f202 mul.w r2, r3, r2 800b5dc: 68bb ldr r3, [r7, #8] 800b5de: 789b ldrb r3, [r3, #2] 800b5e0: 4619 mov r1, r3 800b5e2: 8afb ldrh r3, [r7, #22] 800b5e4: fb01 f303 mul.w r3, r1, r3 800b5e8: 4413 add r3, r2 800b5ea: 4a07 ldr r2, [pc, #28] @ (800b608 ) 800b5ec: fb82 1203 smull r1, r2, r2, r3 800b5f0: 441a add r2, r3 800b5f2: 11d2 asrs r2, r2, #7 800b5f4: 17db asrs r3, r3, #31 800b5f6: 1ad3 subs r3, r2, r3 800b5f8: b2da uxtb r2, r3 800b5fa: 6a3b ldr r3, [r7, #32] 800b5fc: 709a strb r2, [r3, #2] } 800b5fe: bf00 nop 800b600: 371c adds r7, #28 800b602: 46bd mov sp, r7 800b604: bc80 pop {r7} 800b606: 4770 bx lr 800b608: 80808081 .word 0x80808081 0800b60c : void RGB_SetColor(RGB_t *color){ 800b60c: b480 push {r7} 800b60e: b083 sub sp, #12 800b610: af00 add r7, sp, #0 800b612: 6078 str r0, [r7, #4] htim4.Instance->CCR2 = color->R * 100 / 255; 800b614: 687b ldr r3, [r7, #4] 800b616: 781b ldrb r3, [r3, #0] 800b618: 461a mov r2, r3 800b61a: 2364 movs r3, #100 @ 0x64 800b61c: fb02 f303 mul.w r3, r2, r3 800b620: 4a17 ldr r2, [pc, #92] @ (800b680 ) 800b622: fb82 1203 smull r1, r2, r2, r3 800b626: 441a add r2, r3 800b628: 11d2 asrs r2, r2, #7 800b62a: 17db asrs r3, r3, #31 800b62c: 1ad2 subs r2, r2, r3 800b62e: 4b15 ldr r3, [pc, #84] @ (800b684 ) 800b630: 681b ldr r3, [r3, #0] 800b632: 639a str r2, [r3, #56] @ 0x38 htim4.Instance->CCR3 = color->G * 100 / 255; 800b634: 687b ldr r3, [r7, #4] 800b636: 785b ldrb r3, [r3, #1] 800b638: 461a mov r2, r3 800b63a: 2364 movs r3, #100 @ 0x64 800b63c: fb02 f303 mul.w r3, r2, r3 800b640: 4a0f ldr r2, [pc, #60] @ (800b680 ) 800b642: fb82 1203 smull r1, r2, r2, r3 800b646: 441a add r2, r3 800b648: 11d2 asrs r2, r2, #7 800b64a: 17db asrs r3, r3, #31 800b64c: 1ad2 subs r2, r2, r3 800b64e: 4b0d ldr r3, [pc, #52] @ (800b684 ) 800b650: 681b ldr r3, [r3, #0] 800b652: 63da str r2, [r3, #60] @ 0x3c htim4.Instance->CCR4 = color->B * 100 / 255; 800b654: 687b ldr r3, [r7, #4] 800b656: 789b ldrb r3, [r3, #2] 800b658: 461a mov r2, r3 800b65a: 2364 movs r3, #100 @ 0x64 800b65c: fb02 f303 mul.w r3, r2, r3 800b660: 4a07 ldr r2, [pc, #28] @ (800b680 ) 800b662: fb82 1203 smull r1, r2, r2, r3 800b666: 441a add r2, r3 800b668: 11d2 asrs r2, r2, #7 800b66a: 17db asrs r3, r3, #31 800b66c: 1ad2 subs r2, r2, r3 800b66e: 4b05 ldr r3, [pc, #20] @ (800b684 ) 800b670: 681b ldr r3, [r3, #0] 800b672: 641a str r2, [r3, #64] @ 0x40 } 800b674: bf00 nop 800b676: 370c adds r7, #12 800b678: 46bd mov sp, r7 800b67a: bc80 pop {r7} 800b67c: 4770 bx lr 800b67e: bf00 nop 800b680: 80808081 .word 0x80808081 800b684: 200010e0 .word 0x200010e0 0800b688 : void LED_SetColor(RGB_Cycle_t *color){ 800b688: b480 push {r7} 800b68a: b083 sub sp, #12 800b68c: af00 add r7, sp, #0 800b68e: 6078 str r0, [r7, #4] memcpy(&LED_Cycle, color, sizeof(RGB_Cycle_t)); 800b690: 4b05 ldr r3, [pc, #20] @ (800b6a8 ) 800b692: 687a ldr r2, [r7, #4] 800b694: 6810 ldr r0, [r2, #0] 800b696: 6851 ldr r1, [r2, #4] 800b698: c303 stmia r3!, {r0, r1} 800b69a: 8912 ldrh r2, [r2, #8] 800b69c: 801a strh r2, [r3, #0] } 800b69e: bf00 nop 800b6a0: 370c adds r7, #12 800b6a2: 46bd mov sp, r7 800b6a4: bc80 pop {r7} 800b6a6: 4770 bx lr 800b6a8: 20000944 .word 0x20000944 0800b6ac : void LED_Init(){ 800b6ac: b580 push {r7, lr} 800b6ae: b082 sub sp, #8 800b6b0: af00 add r7, sp, #0 RGB_t color = {.R=0, .G=0, .B=0}; 800b6b2: 2300 movs r3, #0 800b6b4: 713b strb r3, [r7, #4] 800b6b6: 2300 movs r3, #0 800b6b8: 717b strb r3, [r7, #5] 800b6ba: 2300 movs r3, #0 800b6bc: 71bb strb r3, [r7, #6] HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_2); 800b6be: 2104 movs r1, #4 800b6c0: 4809 ldr r0, [pc, #36] @ (800b6e8 ) 800b6c2: f006 fabb bl 8011c3c HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); 800b6c6: 2108 movs r1, #8 800b6c8: 4807 ldr r0, [pc, #28] @ (800b6e8 ) 800b6ca: f006 fab7 bl 8011c3c HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4); 800b6ce: 210c movs r1, #12 800b6d0: 4805 ldr r0, [pc, #20] @ (800b6e8 ) 800b6d2: f006 fab3 bl 8011c3c RGB_SetColor(&color); 800b6d6: 1d3b adds r3, r7, #4 800b6d8: 4618 mov r0, r3 800b6da: f7ff ff97 bl 800b60c } 800b6de: bf00 nop 800b6e0: 3708 adds r7, #8 800b6e2: 46bd mov sp, r7 800b6e4: bd80 pop {r7, pc} 800b6e6: bf00 nop 800b6e8: 200010e0 .word 0x200010e0 0800b6ec : // } // } // } // } void LED_Task(){ 800b6ec: b580 push {r7, lr} 800b6ee: b082 sub sp, #8 800b6f0: af02 add r7, sp, #8 static uint32_t led_tick; if((HAL_GetTick() - led_tick) > 20){ 800b6f2: f002 faf1 bl 800dcd8 800b6f6: 4602 mov r2, r0 800b6f8: 4b46 ldr r3, [pc, #280] @ (800b814 ) 800b6fa: 681b ldr r3, [r3, #0] 800b6fc: 1ad3 subs r3, r2, r3 800b6fe: 2b14 cmp r3, #20 800b700: f240 8085 bls.w 800b80e led_tick = HAL_GetTick(); 800b704: f002 fae8 bl 800dcd8 800b708: 4603 mov r3, r0 800b70a: 4a42 ldr r2, [pc, #264] @ (800b814 ) 800b70c: 6013 str r3, [r2, #0] LED_State.tick++; 800b70e: 4b42 ldr r3, [pc, #264] @ (800b818 ) 800b710: 885b ldrh r3, [r3, #2] 800b712: 3301 adds r3, #1 800b714: b29a uxth r2, r3 800b716: 4b40 ldr r3, [pc, #256] @ (800b818 ) 800b718: 805a strh r2, [r3, #2] // LED_PhaseSync(led_n); switch(LED_State.state){ 800b71a: 4b3f ldr r3, [pc, #252] @ (800b818 ) 800b71c: 781b ldrb r3, [r3, #0] 800b71e: 2b03 cmp r3, #3 800b720: d867 bhi.n 800b7f2 800b722: a201 add r2, pc, #4 @ (adr r2, 800b728 ) 800b724: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b728: 0800b739 .word 0x0800b739 800b72c: 0800b76b .word 0x0800b76b 800b730: 0800b797 .word 0x0800b797 800b734: 0800b7c9 .word 0x0800b7c9 case LED_RISING: interpolateColors(&LED_Cycle.Color2, &LED_Cycle.Color1, LED_State.tick, LED_Cycle.Tr, &LED_State.color); 800b738: 4b37 ldr r3, [pc, #220] @ (800b818 ) 800b73a: 885a ldrh r2, [r3, #2] 800b73c: 4b37 ldr r3, [pc, #220] @ (800b81c ) 800b73e: 78db ldrb r3, [r3, #3] 800b740: 4619 mov r1, r3 800b742: 4b37 ldr r3, [pc, #220] @ (800b820 ) 800b744: 9300 str r3, [sp, #0] 800b746: 460b mov r3, r1 800b748: 4934 ldr r1, [pc, #208] @ (800b81c ) 800b74a: 4836 ldr r0, [pc, #216] @ (800b824 ) 800b74c: f7ff feee bl 800b52c if(LED_State.tick>LED_Cycle.Tr){ 800b750: 4b31 ldr r3, [pc, #196] @ (800b818 ) 800b752: 885b ldrh r3, [r3, #2] 800b754: 4a31 ldr r2, [pc, #196] @ (800b81c ) 800b756: 78d2 ldrb r2, [r2, #3] 800b758: 4293 cmp r3, r2 800b75a: d94e bls.n 800b7fa LED_State.state = LED_HIGH; 800b75c: 4b2e ldr r3, [pc, #184] @ (800b818 ) 800b75e: 2201 movs r2, #1 800b760: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b762: 4b2d ldr r3, [pc, #180] @ (800b818 ) 800b764: 2200 movs r2, #0 800b766: 805a strh r2, [r3, #2] } break; 800b768: e047 b.n 800b7fa case LED_HIGH: memcpy(&LED_State.color, &LED_Cycle.Color1, sizeof(RGB_t)); 800b76a: 4b2b ldr r3, [pc, #172] @ (800b818 ) 800b76c: 4a2b ldr r2, [pc, #172] @ (800b81c ) 800b76e: 3304 adds r3, #4 800b770: 6812 ldr r2, [r2, #0] 800b772: 4611 mov r1, r2 800b774: 8019 strh r1, [r3, #0] 800b776: 3302 adds r3, #2 800b778: 0c12 lsrs r2, r2, #16 800b77a: 701a strb r2, [r3, #0] if(LED_State.tick>LED_Cycle.Th){ 800b77c: 4b26 ldr r3, [pc, #152] @ (800b818 ) 800b77e: 885b ldrh r3, [r3, #2] 800b780: 4a26 ldr r2, [pc, #152] @ (800b81c ) 800b782: 7912 ldrb r2, [r2, #4] 800b784: 4293 cmp r3, r2 800b786: d93a bls.n 800b7fe LED_State.state = LED_FALLING; 800b788: 4b23 ldr r3, [pc, #140] @ (800b818 ) 800b78a: 2202 movs r2, #2 800b78c: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b78e: 4b22 ldr r3, [pc, #136] @ (800b818 ) 800b790: 2200 movs r2, #0 800b792: 805a strh r2, [r3, #2] } break; 800b794: e033 b.n 800b7fe case LED_FALLING: interpolateColors(&LED_Cycle.Color1, &LED_Cycle.Color2, LED_State.tick, LED_Cycle.Tf, &LED_State.color); 800b796: 4b20 ldr r3, [pc, #128] @ (800b818 ) 800b798: 885a ldrh r2, [r3, #2] 800b79a: 4b20 ldr r3, [pc, #128] @ (800b81c ) 800b79c: 795b ldrb r3, [r3, #5] 800b79e: 4619 mov r1, r3 800b7a0: 4b1f ldr r3, [pc, #124] @ (800b820 ) 800b7a2: 9300 str r3, [sp, #0] 800b7a4: 460b mov r3, r1 800b7a6: 491f ldr r1, [pc, #124] @ (800b824 ) 800b7a8: 481c ldr r0, [pc, #112] @ (800b81c ) 800b7aa: f7ff febf bl 800b52c if(LED_State.tick>LED_Cycle.Tf){ 800b7ae: 4b1a ldr r3, [pc, #104] @ (800b818 ) 800b7b0: 885b ldrh r3, [r3, #2] 800b7b2: 4a1a ldr r2, [pc, #104] @ (800b81c ) 800b7b4: 7952 ldrb r2, [r2, #5] 800b7b6: 4293 cmp r3, r2 800b7b8: d923 bls.n 800b802 LED_State.state = LED_LOW; 800b7ba: 4b17 ldr r3, [pc, #92] @ (800b818 ) 800b7bc: 2203 movs r2, #3 800b7be: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b7c0: 4b15 ldr r3, [pc, #84] @ (800b818 ) 800b7c2: 2200 movs r2, #0 800b7c4: 805a strh r2, [r3, #2] } break; 800b7c6: e01c b.n 800b802 case LED_LOW: memcpy(&LED_State.color, &LED_Cycle.Color2, sizeof(RGB_t)); 800b7c8: 4b13 ldr r3, [pc, #76] @ (800b818 ) 800b7ca: 4a14 ldr r2, [pc, #80] @ (800b81c ) 800b7cc: 3304 adds r3, #4 800b7ce: 3207 adds r2, #7 800b7d0: 8811 ldrh r1, [r2, #0] 800b7d2: 7892 ldrb r2, [r2, #2] 800b7d4: 8019 strh r1, [r3, #0] 800b7d6: 709a strb r2, [r3, #2] if(LED_State.tick>LED_Cycle.Tl){ 800b7d8: 4b0f ldr r3, [pc, #60] @ (800b818 ) 800b7da: 885b ldrh r3, [r3, #2] 800b7dc: 4a0f ldr r2, [pc, #60] @ (800b81c ) 800b7de: 7992 ldrb r2, [r2, #6] 800b7e0: 4293 cmp r3, r2 800b7e2: d910 bls.n 800b806 LED_State.state = LED_RISING; 800b7e4: 4b0c ldr r3, [pc, #48] @ (800b818 ) 800b7e6: 2200 movs r2, #0 800b7e8: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b7ea: 4b0b ldr r3, [pc, #44] @ (800b818 ) 800b7ec: 2200 movs r2, #0 800b7ee: 805a strh r2, [r3, #2] } break; 800b7f0: e009 b.n 800b806 default: LED_State.state = LED_RISING; 800b7f2: 4b09 ldr r3, [pc, #36] @ (800b818 ) 800b7f4: 2200 movs r2, #0 800b7f6: 701a strb r2, [r3, #0] 800b7f8: e006 b.n 800b808 break; 800b7fa: bf00 nop 800b7fc: e004 b.n 800b808 break; 800b7fe: bf00 nop 800b800: e002 b.n 800b808 break; 800b802: bf00 nop 800b804: e000 b.n 800b808 break; 800b806: bf00 nop } RGB_SetColor(&LED_State.color); 800b808: 4805 ldr r0, [pc, #20] @ (800b820 ) 800b80a: f7ff feff bl 800b60c } } 800b80e: bf00 nop 800b810: 46bd mov sp, r7 800b812: bd80 pop {r7, pc} 800b814: 20000950 .word 0x20000950 800b818: 2000093c .word 0x2000093c 800b81c: 20000944 .word 0x20000944 800b820: 20000940 .word 0x20000940 800b824: 2000094b .word 0x2000094b 0800b828 : RTC_HandleTypeDef hrtc; /* RTC init function */ void MX_RTC_Init(void) { 800b828: b580 push {r7, lr} 800b82a: af00 add r7, sp, #0 /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 800b82c: 4b0a ldr r3, [pc, #40] @ (800b858 ) 800b82e: 4a0b ldr r2, [pc, #44] @ (800b85c ) 800b830: 601a str r2, [r3, #0] hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; 800b832: 4b09 ldr r3, [pc, #36] @ (800b858 ) 800b834: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800b838: 605a str r2, [r3, #4] hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; 800b83a: 4b07 ldr r3, [pc, #28] @ (800b858 ) 800b83c: f44f 7280 mov.w r2, #256 @ 0x100 800b840: 609a str r2, [r3, #8] if (HAL_RTC_Init(&hrtc) != HAL_OK) 800b842: 4805 ldr r0, [pc, #20] @ (800b858 ) 800b844: f005 ff48 bl 80116d8 800b848: 4603 mov r3, r0 800b84a: 2b00 cmp r3, #0 800b84c: d001 beq.n 800b852 { Error_Handler(); 800b84e: f7ff f8e9 bl 800aa24 } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 800b852: bf00 nop 800b854: bd80 pop {r7, pc} 800b856: bf00 nop 800b858: 20000954 .word 0x20000954 800b85c: 40002800 .word 0x40002800 0800b860 : void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) { 800b860: b580 push {r7, lr} 800b862: b084 sub sp, #16 800b864: af00 add r7, sp, #0 800b866: 6078 str r0, [r7, #4] if(rtcHandle->Instance==RTC) 800b868: 687b ldr r3, [r7, #4] 800b86a: 681b ldr r3, [r3, #0] 800b86c: 4a0b ldr r2, [pc, #44] @ (800b89c ) 800b86e: 4293 cmp r3, r2 800b870: d110 bne.n 800b894 { /* USER CODE BEGIN RTC_MspInit 0 */ /* USER CODE END RTC_MspInit 0 */ HAL_PWR_EnableBkUpAccess(); 800b872: f004 fec5 bl 8010600 /* Enable BKP CLK enable for backup registers */ __HAL_RCC_BKP_CLK_ENABLE(); 800b876: 4b0a ldr r3, [pc, #40] @ (800b8a0 ) 800b878: 69db ldr r3, [r3, #28] 800b87a: 4a09 ldr r2, [pc, #36] @ (800b8a0 ) 800b87c: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800b880: 61d3 str r3, [r2, #28] 800b882: 4b07 ldr r3, [pc, #28] @ (800b8a0 ) 800b884: 69db ldr r3, [r3, #28] 800b886: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800b88a: 60fb str r3, [r7, #12] 800b88c: 68fb ldr r3, [r7, #12] /* RTC clock enable */ __HAL_RCC_RTC_ENABLE(); 800b88e: 4b05 ldr r3, [pc, #20] @ (800b8a4 ) 800b890: 2201 movs r2, #1 800b892: 601a str r2, [r3, #0] /* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE END RTC_MspInit 1 */ } } 800b894: bf00 nop 800b896: 3710 adds r7, #16 800b898: 46bd mov sp, r7 800b89a: bd80 pop {r7, pc} 800b89c: 40002800 .word 0x40002800 800b8a0: 40021000 .word 0x40021000 800b8a4: 4242043c .word 0x4242043c 0800b8a8 : CCS_ConnectorState_t CCS_ConnectorState = CCS_UNPLUGGED; ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len); static void CCS_UART3_Watchdog(void); ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800b8a8: 4602 mov r2, r0 if (err == HAL_UART_ERROR_NONE) { 800b8aa: b359 cbz r1, 800b904 ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800b8ac: b570 push {r4, r5, r6, lr} 800b8ae: 460c mov r4, r1 log_printf(LOG_ERR, "UART%u HAL error decode: NONE\n", uart_num); return; } log_printf(LOG_ERR, "UART%u HAL error decode: %s%s%s%s%s%s raw=0x%08lx\n", 800b8b0: 07cb lsls r3, r1, #31 800b8b2: bf58 it pl 800b8b4: 4915 ldrpl r1, [pc, #84] @ (800b90c ) 800b8b6: 4d15 ldr r5, [pc, #84] @ (800b90c ) 800b8b8: bf48 it mi 800b8ba: 4914 ldrmi r1, [pc, #80] @ (800b90c ) ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800b8bc: b086 sub sp, #24 log_printf(LOG_ERR, "UART%u HAL error decode: %s%s%s%s%s%s raw=0x%08lx\n", 800b8be: bf54 ite pl 800b8c0: 460b movpl r3, r1 800b8c2: 4b13 ldrmi r3, [pc, #76] @ (800b910 ) 800b8c4: f014 0f02 tst.w r4, #2 800b8c8: 9104 str r1, [sp, #16] 800b8ca: 4912 ldr r1, [pc, #72] @ (800b914 ) 800b8cc: bf08 it eq 800b8ce: 4629 moveq r1, r5 800b8d0: f014 0f04 tst.w r4, #4 800b8d4: 4810 ldr r0, [pc, #64] @ (800b918 ) 800b8d6: bf08 it eq 800b8d8: 4628 moveq r0, r5 800b8da: f014 0f08 tst.w r4, #8 800b8de: 9001 str r0, [sp, #4] 800b8e0: 480e ldr r0, [pc, #56] @ (800b91c ) 800b8e2: 4e0f ldr r6, [pc, #60] @ (800b920 ) 800b8e4: bf08 it eq 800b8e6: 462e moveq r6, r5 800b8e8: f014 0f10 tst.w r4, #16 800b8ec: bf18 it ne 800b8ee: 4605 movne r5, r0 800b8f0: 9100 str r1, [sp, #0] 800b8f2: e9cd 6502 strd r6, r5, [sp, #8] 800b8f6: 490b ldr r1, [pc, #44] @ (800b924 ) 800b8f8: 9405 str r4, [sp, #20] 800b8fa: 2004 movs r0, #4 800b8fc: f7fe fd86 bl 800a40c (err & HAL_UART_ERROR_INVALID_CALLBACK) ? "INV_CB " : "", #else "", #endif (unsigned long)err); } 800b900: b006 add sp, #24 800b902: bd70 pop {r4, r5, r6, pc} log_printf(LOG_ERR, "UART%u HAL error decode: NONE\n", uart_num); 800b904: 2004 movs r0, #4 800b906: 4908 ldr r1, [pc, #32] @ (800b928 ) 800b908: f7fe bd80 b.w 800a40c 800b90c: 08016c1c .word 0x08016c1c 800b910: 0801689c .word 0x0801689c 800b914: 080168a0 .word 0x080168a0 800b918: 080168a4 .word 0x080168a4 800b91c: 080168b0 .word 0x080168b0 800b920: 080168a8 .word 0x080168a8 800b924: 080168d8 .word 0x080168d8 800b928: 080168b8 .word 0x080168b8 0800b92c : ISR_FAST static void uart3_arm_rx_or_log(const char *where) { 800b92c: b530 push {r4, r5, lr} HAL_StatusTypeDef st = HAL_UARTEx_ReceiveToIdle_IT(&huart3, rx_buffer, sizeof(rx_buffer)); 800b92e: f44f 7280 mov.w r2, #256 @ 0x100 ISR_FAST static void uart3_arm_rx_or_log(const char *where) { 800b932: 4605 mov r5, r0 800b934: b083 sub sp, #12 HAL_StatusTypeDef st = HAL_UARTEx_ReceiveToIdle_IT(&huart3, rx_buffer, sizeof(rx_buffer)); 800b936: 4910 ldr r1, [pc, #64] @ (800b978 ) 800b938: 4810 ldr r0, [pc, #64] @ (800b97c ) 800b93a: f007 f914 bl 8012b66 if (st == HAL_OK) { 800b93e: b908 cbnz r0, 800b944 where, (int)st, (unsigned long)err_after); uart3_log_hal_error(3u, err_after); if (err_after != HAL_UART_ERROR_NONE) { (void)HAL_UART_Abort_IT(&huart3); } } 800b940: b003 add sp, #12 800b942: bd30 pop {r4, r5, pc} uint32_t err_after = HAL_UART_GetError(&huart3); 800b944: 4604 mov r4, r0 800b946: 480d ldr r0, [pc, #52] @ (800b97c ) 800b948: f007 fd22 bl 8013390 800b94c: 4602 mov r2, r0 log_printf(LOG_ERR, 800b94e: 4623 mov r3, r4 uint32_t err_after = HAL_UART_GetError(&huart3); 800b950: 4614 mov r4, r2 log_printf(LOG_ERR, 800b952: 490b ldr r1, [pc, #44] @ (800b980 ) 800b954: 2004 movs r0, #4 800b956: 462a mov r2, r5 800b958: 9400 str r4, [sp, #0] 800b95a: f7fe fd57 bl 800a40c uart3_log_hal_error(3u, err_after); 800b95e: 4621 mov r1, r4 800b960: 2003 movs r0, #3 800b962: f7ff ffa1 bl 800b8a8 if (err_after != HAL_UART_ERROR_NONE) { 800b966: 2c00 cmp r4, #0 800b968: d0ea beq.n 800b940 (void)HAL_UART_Abort_IT(&huart3); 800b96a: 4804 ldr r0, [pc, #16] @ (800b97c ) } 800b96c: b003 add sp, #12 800b96e: e8bd 4030 ldmia.w sp!, {r4, r5, lr} (void)HAL_UART_Abort_IT(&huart3); 800b972: f007 b955 b.w 8012c20 800b976: bf00 nop 800b978: 2000098c .word 0x2000098c 800b97c: 20001200 .word 0x20001200 800b980: 0801690c .word 0x0801690c 0800b984 : ISR_FAST void CCS_RxEventCallback(UART_HandleTypeDef *huart, uint16_t size) { 800b984: b538 push {r3, r4, r5, lr} if (huart != &huart3) { 800b986: 4b1a ldr r3, [pc, #104] @ (800b9f0 ) ISR_FAST void CCS_RxEventCallback(UART_HandleTypeDef *huart, uint16_t size) { 800b988: 460c mov r4, r1 if (huart != &huart3) { 800b98a: 4283 cmp r3, r0 800b98c: d113 bne.n 800b9b6 log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", (unsigned)size); return; } if (size == 0u) { 800b98e: b329 cbz r1, 800b9dc log_printf(LOG_WARN, "UART3 RX drop: RxEvent size=0 (idle, no payload)\n"); uart3_arm_rx_or_log("RxEventCallback"); return; } if (size > sizeof(rx_buffer)) { 800b990: f5b1 7f80 cmp.w r1, #256 @ 0x100 800b994: d816 bhi.n 800b9c4 log_printf(LOG_ERR, "UART3 RX drop: size=%u > rx_buffer %u (overflow, not parsed)\n", (unsigned)size, (unsigned)sizeof(rx_buffer)); uart3_arm_rx_or_log("RxEventCallback"); return; } uart3_last_packet_tick = HAL_GetTick(); 800b996: f002 f99f bl 800dcd8 800b99a: 4603 mov r3, r0 800b99c: 4d15 ldr r5, [pc, #84] @ (800b9f4 ) uart3_last_reinit_tick = uart3_last_packet_tick; 800b99e: 4a16 ldr r2, [pc, #88] @ (800b9f8 ) process_received_packet(rx_buffer, size); 800b9a0: 4621 mov r1, r4 800b9a2: 4816 ldr r0, [pc, #88] @ (800b9fc ) uart3_last_packet_tick = HAL_GetTick(); 800b9a4: 602b str r3, [r5, #0] uart3_last_reinit_tick = uart3_last_packet_tick; 800b9a6: 6013 str r3, [r2, #0] process_received_packet(rx_buffer, size); 800b9a8: f000 fcf8 bl 800c39c uart3_arm_rx_or_log("RxEventCallback"); } 800b9ac: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800b9b0: 4813 ldr r0, [pc, #76] @ (800ba00 ) 800b9b2: f7ff bfbb b.w 800b92c log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", 800b9b6: 460a mov r2, r1 } 800b9b8: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", 800b9bc: 2005 movs r0, #5 800b9be: 4911 ldr r1, [pc, #68] @ (800ba04 ) 800b9c0: f7fe bd24 b.w 800a40c log_printf(LOG_ERR, "UART3 RX drop: size=%u > rx_buffer %u (overflow, not parsed)\n", 800b9c4: f44f 7380 mov.w r3, #256 @ 0x100 800b9c8: 460a mov r2, r1 800b9ca: 2004 movs r0, #4 800b9cc: 490e ldr r1, [pc, #56] @ (800ba08 ) 800b9ce: f7fe fd1d bl 800a40c } 800b9d2: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800b9d6: 480a ldr r0, [pc, #40] @ (800ba00 ) 800b9d8: f7ff bfa8 b.w 800b92c log_printf(LOG_WARN, "UART3 RX drop: RxEvent size=0 (idle, no payload)\n"); 800b9dc: 2005 movs r0, #5 800b9de: 490b ldr r1, [pc, #44] @ (800ba0c ) 800b9e0: f7fe fd14 bl 800a40c } 800b9e4: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800b9e8: 4805 ldr r0, [pc, #20] @ (800ba00 ) 800b9ea: f7ff bf9f b.w 800b92c 800b9ee: bf00 nop 800b9f0: 20001200 .word 0x20001200 800b9f4: 20000b9c .word 0x20000b9c 800b9f8: 20000ba0 .word 0x20000ba0 800b9fc: 2000098c .word 0x2000098c 800ba00: 080169b8 .word 0x080169b8 800ba04: 08016948 .word 0x08016948 800ba08: 080169c8 .word 0x080169c8 800ba0c: 08016984 .word 0x08016984 0800ba10 : ISR_FAST void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 800ba10: b5f8 push {r3, r4, r5, r6, r7, lr} 800ba12: 4604 mov r4, r0 uint32_t error = HAL_UART_GetError(huart); 800ba14: f007 fcbc bl 8013390 uint8_t uart_num = 800ba18: 4b1f ldr r3, [pc, #124] @ (800ba98 ) uint32_t error = HAL_UART_GetError(huart); 800ba1a: 4605 mov r5, r0 uint8_t uart_num = 800ba1c: 429c cmp r4, r3 800ba1e: d014 beq.n 800ba4a 800ba20: 4e1e ldr r6, [pc, #120] @ (800ba9c ) 800ba22: 42b4 cmp r4, r6 800ba24: d023 beq.n 800ba6e 800ba26: 4b1e ldr r3, [pc, #120] @ (800baa0 ) 800ba28: 429c cmp r4, r3 800ba2a: d032 beq.n 800ba92 (huart == &huart2) ? 2 : (huart == &huart3) ? 3 : (huart == &huart5) ? 5 : 0; log_printf(LOG_ERR, 800ba2c: 4603 mov r3, r0 800ba2e: 2200 movs r2, #0 800ba30: 491c ldr r1, [pc, #112] @ (800baa4 ) 800ba32: 2004 movs r0, #4 800ba34: f7fe fcea bl 800a40c "UART%u HAL error (ISR): raw=0x%08lx — RX may be corrupted until re-arm\n", uart_num, (unsigned long)error); uart3_log_hal_error(uart_num, error); 800ba38: 4629 mov r1, r5 800ba3a: 2000 movs r0, #0 800ba3c: f7ff ff34 bl 800b8a8 (void)HAL_UART_Abort_IT(huart); 800ba40: 4620 mov r0, r4 if (huart == &huart3) { uart3_arm_rx_or_log("ErrorCallback"); } } 800ba42: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} (void)HAL_UART_Abort_IT(huart); 800ba46: f007 b8eb b.w 8012c20 800ba4a: 2202 movs r2, #2 uint8_t uart_num = 800ba4c: 4617 mov r7, r2 800ba4e: 4e13 ldr r6, [pc, #76] @ (800ba9c ) log_printf(LOG_ERR, 800ba50: 462b mov r3, r5 800ba52: 4914 ldr r1, [pc, #80] @ (800baa4 ) 800ba54: 2004 movs r0, #4 800ba56: f7fe fcd9 bl 800a40c uart3_log_hal_error(uart_num, error); 800ba5a: 4629 mov r1, r5 800ba5c: 4638 mov r0, r7 800ba5e: f7ff ff23 bl 800b8a8 (void)HAL_UART_Abort_IT(huart); 800ba62: 4620 mov r0, r4 800ba64: f007 f8dc bl 8012c20 if (huart == &huart3) { 800ba68: 42b4 cmp r4, r6 800ba6a: d00d beq.n 800ba88 } 800ba6c: bdf8 pop {r3, r4, r5, r6, r7, pc} log_printf(LOG_ERR, 800ba6e: 4603 mov r3, r0 800ba70: 2203 movs r2, #3 800ba72: 490c ldr r1, [pc, #48] @ (800baa4 ) 800ba74: 2004 movs r0, #4 800ba76: f7fe fcc9 bl 800a40c uart3_log_hal_error(uart_num, error); 800ba7a: 2003 movs r0, #3 800ba7c: 4629 mov r1, r5 800ba7e: f7ff ff13 bl 800b8a8 (void)HAL_UART_Abort_IT(huart); 800ba82: 4620 mov r0, r4 800ba84: f007 f8cc bl 8012c20 } 800ba88: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} uart3_arm_rx_or_log("ErrorCallback"); 800ba8c: 4806 ldr r0, [pc, #24] @ (800baa8 ) 800ba8e: f7ff bf4d b.w 800b92c 800ba92: 2205 movs r2, #5 uint8_t uart_num = 800ba94: 4617 mov r7, r2 800ba96: e7db b.n 800ba50 800ba98: 200011b8 .word 0x200011b8 800ba9c: 20001200 .word 0x20001200 800baa0: 20001128 .word 0x20001128 800baa4: 08016a08 .word 0x08016a08 800baa8: 08016a54 .word 0x08016a54 0800baac : void CCS_SerialLoop(void) { 800baac: b580 push {r7, lr} 800baae: af00 add r7, sp, #0 static uint32_t replug_tick = 0; static uint32_t replug_watchdog_tick = 0; static uint32_t replug_watchdog1_tick = 0; static uint32_t last_state_sent = 0; if ((&huart3)->RxState == HAL_UART_STATE_READY) { 800bab0: 4ba7 ldr r3, [pc, #668] @ (800bd50 ) 800bab2: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800bab6: b2db uxtb r3, r3 800bab8: 2b20 cmp r3, #32 800baba: d102 bne.n 800bac2 uart3_arm_rx_or_log("SerialLoop"); 800babc: 48a5 ldr r0, [pc, #660] @ (800bd54 ) 800babe: f7ff ff35 bl 800b92c } CCS_UART3_Watchdog(); 800bac2: f000 fcd9 bl 800c478 /* Read CP once per loop and use buffered value below. */ cp_state_buffer = CP_GetState(); 800bac6: f7fe fb3b bl 800a140 800baca: 4603 mov r3, r0 800bacc: 461a mov r2, r3 800bace: 4ba2 ldr r3, [pc, #648] @ (800bd58 ) 800bad0: 701a strb r2, [r3, #0] if (CONN.connControl != CMD_NONE) { 800bad2: 4ba2 ldr r3, [pc, #648] @ (800bd5c ) 800bad4: 781b ldrb r3, [r3, #0] 800bad6: 2b00 cmp r3, #0 800bad8: d003 beq.n 800bae2 last_cmd = CONN.connControl; 800bada: 4ba0 ldr r3, [pc, #640] @ (800bd5c ) 800badc: 781a ldrb r2, [r3, #0] 800bade: 4ba0 ldr r3, [pc, #640] @ (800bd60 ) 800bae0: 701a strb r2, [r3, #0] } if((HAL_GetTick() - last_cmd_sent) > CMD_INTERVAL){ 800bae2: f002 f8f9 bl 800dcd8 800bae6: 4602 mov r2, r0 800bae8: 4b9e ldr r3, [pc, #632] @ (800bd64 ) 800baea: 681b ldr r3, [r3, #0] 800baec: 1ad3 subs r3, r2, r3 800baee: 2b0a cmp r3, #10 800baf0: d953 bls.n 800bb9a if ((HAL_GetTick() - last_state_sent) >= 200) { 800baf2: f002 f8f1 bl 800dcd8 800baf6: 4602 mov r2, r0 800baf8: 4b9b ldr r3, [pc, #620] @ (800bd68 ) 800bafa: 681b ldr r3, [r3, #0] 800bafc: 1ad3 subs r3, r2, r3 800bafe: 2bc7 cmp r3, #199 @ 0xc7 800bb00: d906 bls.n 800bb10 send_state(); 800bb02: f000 fb33 bl 800c16c last_state_sent = HAL_GetTick(); 800bb06: f002 f8e7 bl 800dcd8 800bb0a: 4603 mov r3, r0 800bb0c: 4a96 ldr r2, [pc, #600] @ (800bd68 ) 800bb0e: 6013 str r3, [r2, #0] } if (ESTOP) { 800bb10: 4b96 ldr r3, [pc, #600] @ (800bd6c ) 800bb12: 781b ldrb r3, [r3, #0] 800bb14: 2b00 cmp r3, #0 800bb16: d008 beq.n 800bb2a log_printf(LOG_ERR, "ESTOP triggered\n"); 800bb18: 4995 ldr r1, [pc, #596] @ (800bd70 ) 800bb1a: 2004 movs r0, #4 800bb1c: f7fe fc76 bl 800a40c CCS_SendEmergencyStop(); 800bb20: f000 fac4 bl 800c0ac ESTOP = 0; 800bb24: 4b91 ldr r3, [pc, #580] @ (800bd6c ) 800bb26: 2200 movs r2, #0 800bb28: 701a strb r2, [r3, #0] } if (((CONN.connControl == CMD_STOP) || 800bb2a: 4b8c ldr r3, [pc, #560] @ (800bd5c ) 800bb2c: 781b ldrb r3, [r3, #0] 800bb2e: 2b01 cmp r3, #1 800bb30: d003 beq.n 800bb3a (CONN.chargingError != CONN_NO_ERROR)) && 800bb32: 4b8a ldr r3, [pc, #552] @ (800bd5c ) 800bb34: 7f5b ldrb r3, [r3, #29] if (((CONN.connControl == CMD_STOP) || 800bb36: 2b00 cmp r3, #0 800bb38: d013 beq.n 800bb62 ((HAL_GetTick() - last_stop_sent) > 1000)) { 800bb3a: f002 f8cd bl 800dcd8 800bb3e: 4602 mov r2, r0 800bb40: 4b8c ldr r3, [pc, #560] @ (800bd74 ) 800bb42: 681b ldr r3, [r3, #0] 800bb44: 1ad3 subs r3, r2, r3 (CONN.chargingError != CONN_NO_ERROR)) && 800bb46: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bb4a: d90a bls.n 800bb62 last_stop_sent = HAL_GetTick(); 800bb4c: f002 f8c4 bl 800dcd8 800bb50: 4603 mov r3, r0 800bb52: 4a88 ldr r2, [pc, #544] @ (800bd74 ) 800bb54: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "Stopping charging...\n"); 800bb56: 4988 ldr r1, [pc, #544] @ (800bd78 ) 800bb58: 2005 movs r0, #5 800bb5a: f7fe fc57 bl 800a40c CCS_SendEmergencyStop(); 800bb5e: f000 faa5 bl 800c0ac } if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800bb62: 4b86 ldr r3, [pc, #536] @ (800bd7c ) 800bb64: 781b ldrb r3, [r3, #0] 800bb66: 2b0c cmp r3, #12 800bb68: d003 beq.n 800bb72 800bb6a: 4b84 ldr r3, [pc, #528] @ (800bd7c ) 800bb6c: 781b ldrb r3, [r3, #0] 800bb6e: 2b0b cmp r3, #11 800bb70: d113 bne.n 800bb9a ((HAL_GetTick() - last_stop_sent) > 1000)) { 800bb72: f002 f8b1 bl 800dcd8 800bb76: 4602 mov r2, r0 800bb78: 4b7e ldr r3, [pc, #504] @ (800bd74 ) 800bb7a: 681b ldr r3, [r3, #0] 800bb7c: 1ad3 subs r3, r2, r3 if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800bb7e: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bb82: d90a bls.n 800bb9a last_stop_sent = HAL_GetTick(); 800bb84: f002 f8a8 bl 800dcd8 800bb88: 4603 mov r3, r0 800bb8a: 4a7a ldr r2, [pc, #488] @ (800bd74 ) 800bb8c: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "FinishedEV, stopping...\n"); 800bb8e: 497c ldr r1, [pc, #496] @ (800bd80 ) 800bb90: 2005 movs r0, #5 800bb92: f7fe fc3b bl 800a40c CCS_SendEmergencyStop(); 800bb96: f000 fa89 bl 800c0ac } (void)replug_watchdog_tick; (void)replug_watchdog1_tick; if (!config_initialized) { 800bb9a: 4b7a ldr r3, [pc, #488] @ (800bd84 ) 800bb9c: 781b ldrb r3, [r3, #0] 800bb9e: 2b00 cmp r3, #0 800bba0: d107 bne.n 800bbb2 // Keep connector in Unknown until host sends valid SET_CONFIG. RELAY_Write(RELAY_CP, 1); 800bba2: 2101 movs r1, #1 800bba4: 2005 movs r0, #5 800bba6: f7fd fe07 bl 80097b8 CONN_SetState(Unknown); 800bbaa: 2000 movs r0, #0 800bbac: f7fe f990 bl 8009ed0 800bbb0: e0fd b.n 800bdae } else { switch(CCS_ConnectorState){ 800bbb2: 4b75 ldr r3, [pc, #468] @ (800bd88 ) 800bbb4: 781b ldrb r3, [r3, #0] 800bbb6: 2b04 cmp r3, #4 800bbb8: f200 80f9 bhi.w 800bdae 800bbbc: a201 add r2, pc, #4 @ (adr r2, 800bbc4 ) 800bbbe: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800bbc2: bf00 nop 800bbc4: 0800bbd9 .word 0x0800bbd9 800bbc8: 0800bbf9 .word 0x0800bbf9 800bbcc: 0800bc3d .word 0x0800bc3d 800bbd0: 0800bc79 .word 0x0800bc79 800bbd4: 0800bcc9 .word 0x0800bcc9 case CCS_DISABLED: RELAY_Write(RELAY_CP, 0); 800bbd8: 2100 movs r1, #0 800bbda: 2005 movs r0, #5 800bbdc: f7fd fdec bl 80097b8 CONN_SetState(Disabled); 800bbe0: 2002 movs r0, #2 800bbe2: f7fe f975 bl 8009ed0 if (CONN.chargingError == CONN_NO_ERROR){ 800bbe6: 4b5d ldr r3, [pc, #372] @ (800bd5c ) 800bbe8: 7f5b ldrb r3, [r3, #29] 800bbea: 2b00 cmp r3, #0 800bbec: f040 80a7 bne.w 800bd3e CCS_ConnectorState = CCS_UNPLUGGED; 800bbf0: 4b65 ldr r3, [pc, #404] @ (800bd88 ) 800bbf2: 2201 movs r2, #1 800bbf4: 701a strb r2, [r3, #0] } break; 800bbf6: e0a2 b.n 800bd3e case CCS_UNPLUGGED: RELAY_Write(RELAY_CP, 1); 800bbf8: 2101 movs r1, #1 800bbfa: 2005 movs r0, #5 800bbfc: f7fd fddc bl 80097b8 CONN_SetState(Unplugged); 800bc00: 2001 movs r0, #1 800bc02: f7fe f965 bl 8009ed0 if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || (cp_state_buffer == EV_STATE_C_CONN_ACTIVE)){ 800bc06: 4b54 ldr r3, [pc, #336] @ (800bd58 ) 800bc08: 781b ldrb r3, [r3, #0] 800bc0a: 2b01 cmp r3, #1 800bc0c: d003 beq.n 800bc16 800bc0e: 4b52 ldr r3, [pc, #328] @ (800bd58 ) 800bc10: 781b ldrb r3, [r3, #0] 800bc12: 2b02 cmp r3, #2 800bc14: d102 bne.n 800bc1c CCS_ConnectorState = CCS_AUTH_REQUIRED; 800bc16: 4b5c ldr r3, [pc, #368] @ (800bd88 ) 800bc18: 2202 movs r2, #2 800bc1a: 701a strb r2, [r3, #0] } if (CONN.chargingError != CONN_NO_ERROR){ 800bc1c: 4b4f ldr r3, [pc, #316] @ (800bd5c ) 800bc1e: 7f5b ldrb r3, [r3, #29] 800bc20: 2b00 cmp r3, #0 800bc22: f000 808e beq.w 800bd42 log_printf(LOG_ERR, "Charging error %d, state -> disabled\n", CONN.chargingError); 800bc26: 4b4d ldr r3, [pc, #308] @ (800bd5c ) 800bc28: 7f5b ldrb r3, [r3, #29] 800bc2a: 461a mov r2, r3 800bc2c: 4957 ldr r1, [pc, #348] @ (800bd8c ) 800bc2e: 2004 movs r0, #4 800bc30: f7fe fbec bl 800a40c CCS_ConnectorState = CCS_DISABLED; 800bc34: 4b54 ldr r3, [pc, #336] @ (800bd88 ) 800bc36: 2200 movs r2, #0 800bc38: 701a strb r2, [r3, #0] } break; 800bc3a: e082 b.n 800bd42 case CCS_AUTH_REQUIRED: RELAY_Write(RELAY_CP, 1); 800bc3c: 2101 movs r1, #1 800bc3e: 2005 movs r0, #5 800bc40: f7fd fdba bl 80097b8 CONN_SetState(AuthRequired); 800bc44: 2004 movs r0, #4 800bc46: f7fe f943 bl 8009ed0 if(CONN.connControl == CMD_START){ 800bc4a: 4b44 ldr r3, [pc, #272] @ (800bd5c ) 800bc4c: 781b ldrb r3, [r3, #0] 800bc4e: 2b02 cmp r3, #2 800bc50: d106 bne.n 800bc60 log_printf(LOG_INFO, "Charging permitted, start charging\n"); 800bc52: 494f ldr r1, [pc, #316] @ (800bd90 ) 800bc54: 2007 movs r0, #7 800bc56: f7fe fbd9 bl 800a40c CCS_ConnectorState = CCS_CONNECTED; 800bc5a: 4b4b ldr r3, [pc, #300] @ (800bd88 ) 800bc5c: 2203 movs r2, #3 800bc5e: 701a strb r2, [r3, #0] } if (cp_state_buffer == EV_STATE_A_IDLE){ 800bc60: 4b3d ldr r3, [pc, #244] @ (800bd58 ) 800bc62: 781b ldrb r3, [r3, #0] 800bc64: 2b00 cmp r3, #0 800bc66: d16e bne.n 800bd46 log_printf(LOG_INFO, "Car unplugged\n"); 800bc68: 494a ldr r1, [pc, #296] @ (800bd94 ) 800bc6a: 2007 movs r0, #7 800bc6c: f7fe fbce bl 800a40c CCS_ConnectorState = CCS_UNPLUGGED; 800bc70: 4b45 ldr r3, [pc, #276] @ (800bd88 ) 800bc72: 2201 movs r2, #1 800bc74: 701a strb r2, [r3, #0] } break; 800bc76: e066 b.n 800bd46 case CCS_CONNECTED: RELAY_Write(RELAY_CP, 1); 800bc78: 2101 movs r1, #1 800bc7a: 2005 movs r0, #5 800bc7c: f7fd fd9c bl 80097b8 if(CCS_EvseState < Preparing) { 800bc80: 4b3e ldr r3, [pc, #248] @ (800bd7c ) 800bc82: 781b ldrb r3, [r3, #0] 800bc84: 2b02 cmp r3, #2 800bc86: d803 bhi.n 800bc90 CONN_SetState(Preparing); 800bc88: 2003 movs r0, #3 800bc8a: f7fe f921 bl 8009ed0 800bc8e: e004 b.n 800bc9a } else { CONN_SetState(CCS_EvseState); 800bc90: 4b3a ldr r3, [pc, #232] @ (800bd7c ) 800bc92: 781b ldrb r3, [r3, #0] 800bc94: 4618 mov r0, r3 800bc96: f7fe f91b bl 8009ed0 } if (cp_state_buffer == EV_STATE_A_IDLE){ 800bc9a: 4b2f ldr r3, [pc, #188] @ (800bd58 ) 800bc9c: 781b ldrb r3, [r3, #0] 800bc9e: 2b00 cmp r3, #0 800bca0: d106 bne.n 800bcb0 log_printf(LOG_INFO, "Car unplugged\n"); 800bca2: 493c ldr r1, [pc, #240] @ (800bd94 ) 800bca4: 2007 movs r0, #7 800bca6: f7fe fbb1 bl 800a40c CCS_ConnectorState = CCS_UNPLUGGED; 800bcaa: 4b37 ldr r3, [pc, #220] @ (800bd88 ) 800bcac: 2201 movs r2, #1 800bcae: 701a strb r2, [r3, #0] } if(REPLUG > 0){ 800bcb0: 4b39 ldr r3, [pc, #228] @ (800bd98 ) 800bcb2: 781b ldrb r3, [r3, #0] 800bcb4: 2b00 cmp r3, #0 800bcb6: d048 beq.n 800bd4a log_printf(LOG_INFO, "Replugging...\n"); 800bcb8: 4938 ldr r1, [pc, #224] @ (800bd9c ) 800bcba: 2007 movs r0, #7 800bcbc: f7fe fba6 bl 800a40c CCS_ConnectorState = CCS_REPLUGGING; 800bcc0: 4b31 ldr r3, [pc, #196] @ (800bd88 ) 800bcc2: 2204 movs r2, #4 800bcc4: 701a strb r2, [r3, #0] } break; 800bcc6: e040 b.n 800bd4a case CCS_REPLUGGING: RELAY_Write(RELAY_CP, 0); 800bcc8: 2100 movs r1, #0 800bcca: 2005 movs r0, #5 800bccc: f7fd fd74 bl 80097b8 CONN_SetState(Replugging); 800bcd0: 200d movs r0, #13 800bcd2: f7fe f8fd bl 8009ed0 if((HAL_GetTick() - replug_tick) > 1000){ 800bcd6: f001 ffff bl 800dcd8 800bcda: 4602 mov r2, r0 800bcdc: 4b30 ldr r3, [pc, #192] @ (800bda0 ) 800bcde: 681b ldr r3, [r3, #0] 800bce0: 1ad3 subs r3, r2, r3 800bce2: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bce6: d91a bls.n 800bd1e replug_tick = HAL_GetTick(); 800bce8: f001 fff6 bl 800dcd8 800bcec: 4603 mov r3, r0 800bcee: 4a2c ldr r2, [pc, #176] @ (800bda0 ) 800bcf0: 6013 str r3, [r2, #0] if(REPLUG > 0){ 800bcf2: 4b29 ldr r3, [pc, #164] @ (800bd98 ) 800bcf4: 781b ldrb r3, [r3, #0] 800bcf6: 2b00 cmp r3, #0 800bcf8: d00a beq.n 800bd10 if (REPLUG != 0xFF) REPLUG--; 800bcfa: 4b27 ldr r3, [pc, #156] @ (800bd98 ) 800bcfc: 781b ldrb r3, [r3, #0] 800bcfe: 2bff cmp r3, #255 @ 0xff 800bd00: d00d beq.n 800bd1e 800bd02: 4b25 ldr r3, [pc, #148] @ (800bd98 ) 800bd04: 781b ldrb r3, [r3, #0] 800bd06: 3b01 subs r3, #1 800bd08: b2da uxtb r2, r3 800bd0a: 4b23 ldr r3, [pc, #140] @ (800bd98 ) 800bd0c: 701a strb r2, [r3, #0] 800bd0e: e006 b.n 800bd1e } else { log_printf(LOG_INFO, "Replugging finished, but car unplugged\n"); 800bd10: 4924 ldr r1, [pc, #144] @ (800bda4 ) 800bd12: 2007 movs r0, #7 800bd14: f7fe fb7a bl 800a40c CCS_ConnectorState = CCS_UNPLUGGED; 800bd18: 4b1b ldr r3, [pc, #108] @ (800bd88 ) 800bd1a: 2201 movs r2, #1 800bd1c: 701a strb r2, [r3, #0] } } if(REPLUG == 0){ 800bd1e: 4b1e ldr r3, [pc, #120] @ (800bd98 ) 800bd20: 781b ldrb r3, [r3, #0] 800bd22: 2b00 cmp r3, #0 800bd24: d142 bne.n 800bdac if(cp_state_buffer == EV_STATE_B_CONN_PREP){ 800bd26: 4b0c ldr r3, [pc, #48] @ (800bd58 ) 800bd28: 781b ldrb r3, [r3, #0] 800bd2a: 2b01 cmp r3, #1 800bd2c: d13e bne.n 800bdac log_printf(LOG_INFO, "Replugging finished, car plugged, state -> auth required\n"); 800bd2e: 491e ldr r1, [pc, #120] @ (800bda8 ) 800bd30: 2007 movs r0, #7 800bd32: f7fe fb6b bl 800a40c CCS_ConnectorState = CCS_AUTH_REQUIRED; 800bd36: 4b14 ldr r3, [pc, #80] @ (800bd88 ) 800bd38: 2202 movs r2, #2 800bd3a: 701a strb r2, [r3, #0] } } break; 800bd3c: e036 b.n 800bdac break; 800bd3e: bf00 nop 800bd40: e035 b.n 800bdae break; 800bd42: bf00 nop 800bd44: e033 b.n 800bdae break; 800bd46: bf00 nop 800bd48: e031 b.n 800bdae break; 800bd4a: bf00 nop 800bd4c: e02f b.n 800bdae 800bd4e: bf00 nop 800bd50: 20001200 .word 0x20001200 800bd54: 08016a64 .word 0x08016a64 800bd58: 2000004f .word 0x2000004f 800bd5c: 20000398 .word 0x20000398 800bd60: 20000988 .word 0x20000988 800bd64: 20000980 .word 0x20000980 800bd68: 20000bf4 .word 0x20000bf4 800bd6c: 20000b8c .word 0x20000b8c 800bd70: 08016a70 .word 0x08016a70 800bd74: 20000984 .word 0x20000984 800bd78: 08016a84 .word 0x08016a84 800bd7c: 20000bf0 .word 0x20000bf0 800bd80: 08016a9c .word 0x08016a9c 800bd84: 20001092 .word 0x20001092 800bd88: 20000050 .word 0x20000050 800bd8c: 08016ab8 .word 0x08016ab8 800bd90: 08016ae0 .word 0x08016ae0 800bd94: 08016b04 .word 0x08016b04 800bd98: 20000b8d .word 0x20000b8d 800bd9c: 08016b14 .word 0x08016b14 800bda0: 20000bf8 .word 0x20000bf8 800bda4: 08016b24 .word 0x08016b24 800bda8: 08016b4c .word 0x08016b4c break; 800bdac: bf00 nop } } // If Everest timeout happened, keep safe-state and limit log frequency. // The safe-state must remain until we receive a valid packet from the host. if (everest_timed_out) { 800bdae: 4b40 ldr r3, [pc, #256] @ (800beb0 ) 800bdb0: 781b ldrb r3, [r3, #0] 800bdb2: 2b00 cmp r3, #0 800bdb4: d020 beq.n 800bdf8 if (last_everest_timeout_log_tick == 0 || 800bdb6: 4b3f ldr r3, [pc, #252] @ (800beb4 ) 800bdb8: 681b ldr r3, [r3, #0] 800bdba: 2b00 cmp r3, #0 800bdbc: d009 beq.n 800bdd2 (HAL_GetTick() - last_everest_timeout_log_tick) >= EVEREST_TIMEOUT_MS) { 800bdbe: f001 ff8b bl 800dcd8 800bdc2: 4602 mov r2, r0 800bdc4: 4b3b ldr r3, [pc, #236] @ (800beb4 ) 800bdc6: 681b ldr r3, [r3, #0] 800bdc8: 1ad3 subs r3, r2, r3 if (last_everest_timeout_log_tick == 0 || 800bdca: f241 3287 movw r2, #4999 @ 0x1387 800bdce: 4293 cmp r3, r2 800bdd0: d908 bls.n 800bde4 log_printf(LOG_ERR, "Everest timeout\n"); 800bdd2: 4939 ldr r1, [pc, #228] @ (800beb8 ) 800bdd4: 2004 movs r0, #4 800bdd6: f7fe fb19 bl 800a40c last_everest_timeout_log_tick = HAL_GetTick(); 800bdda: f001 ff7d bl 800dcd8 800bdde: 4603 mov r3, r0 800bde0: 4a34 ldr r2, [pc, #208] @ (800beb4 ) 800bde2: 6013 str r3, [r2, #0] } CONN.EnableOutput = 0; 800bde4: 4b35 ldr r3, [pc, #212] @ (800bebc ) 800bde6: 2200 movs r2, #0 800bde8: 75da strb r2, [r3, #23] CCS_EvseState = Unknown; 800bdea: 4b35 ldr r3, [pc, #212] @ (800bec0 ) 800bdec: 2200 movs r2, #0 800bdee: 701a strb r2, [r3, #0] CP_SetDuty(100); 800bdf0: 2064 movs r0, #100 @ 0x64 800bdf2: f7fe f965 bl 800a0c0 800bdf6: e045 b.n 800be84 } else if (last_host_seen > 0 && (HAL_GetTick() - last_host_seen) > EVEREST_TIMEOUT_MS) { 800bdf8: 4b32 ldr r3, [pc, #200] @ (800bec4 ) 800bdfa: 681b ldr r3, [r3, #0] 800bdfc: 2b00 cmp r3, #0 800bdfe: d024 beq.n 800be4a 800be00: f001 ff6a bl 800dcd8 800be04: 4602 mov r2, r0 800be06: 4b2f ldr r3, [pc, #188] @ (800bec4 ) 800be08: 681b ldr r3, [r3, #0] 800be0a: 1ad3 subs r3, r2, r3 800be0c: f241 3288 movw r2, #5000 @ 0x1388 800be10: 4293 cmp r3, r2 800be12: d91a bls.n 800be4a log_printf(LOG_ERR, "Everest timeout\n"); 800be14: 4928 ldr r1, [pc, #160] @ (800beb8 ) 800be16: 2004 movs r0, #4 800be18: f7fe faf8 bl 800a40c everest_timed_out = 1; 800be1c: 4b24 ldr r3, [pc, #144] @ (800beb0 ) 800be1e: 2201 movs r2, #1 800be20: 701a strb r2, [r3, #0] last_host_seen = HAL_GetTick(); // reset after the first timeout 800be22: f001 ff59 bl 800dcd8 800be26: 4603 mov r3, r0 800be28: 4a26 ldr r2, [pc, #152] @ (800bec4 ) 800be2a: 6013 str r3, [r2, #0] last_everest_timeout_log_tick = HAL_GetTick(); 800be2c: f001 ff54 bl 800dcd8 800be30: 4603 mov r3, r0 800be32: 4a20 ldr r2, [pc, #128] @ (800beb4 ) 800be34: 6013 str r3, [r2, #0] CONN.EnableOutput = 0; 800be36: 4b21 ldr r3, [pc, #132] @ (800bebc ) 800be38: 2200 movs r2, #0 800be3a: 75da strb r2, [r3, #23] CCS_EvseState = Unknown; 800be3c: 4b20 ldr r3, [pc, #128] @ (800bec0 ) 800be3e: 2200 movs r2, #0 800be40: 701a strb r2, [r3, #0] CP_SetDuty(100); 800be42: 2064 movs r0, #100 @ 0x64 800be44: f7fe f93c bl 800a0c0 800be48: e01c b.n 800be84 } else { if (last_cmd == CMD_STOP) { 800be4a: 4b1f ldr r3, [pc, #124] @ (800bec8 ) 800be4c: 781b ldrb r3, [r3, #0] 800be4e: 2b01 cmp r3, #1 800be50: d103 bne.n 800be5a CONN.EnableOutput = 0; 800be52: 4b1a ldr r3, [pc, #104] @ (800bebc ) 800be54: 2200 movs r2, #0 800be56: 75da strb r2, [r3, #23] 800be58: e014 b.n 800be84 } else { CONN.EnableOutput = ev_enable_output ? 1 : 0; 800be5a: 4b1c ldr r3, [pc, #112] @ (800becc ) 800be5c: 781b ldrb r3, [r3, #0] 800be5e: 2b00 cmp r3, #0 800be60: bf14 ite ne 800be62: 2301 movne r3, #1 800be64: 2300 moveq r3, #0 800be66: b2db uxtb r3, r3 800be68: 461a mov r2, r3 800be6a: 4b14 ldr r3, [pc, #80] @ (800bebc ) 800be6c: 75da strb r2, [r3, #23] if((CONN.EnableOutput == 0) && (CONN.connState == Preparing)){ 800be6e: 4b13 ldr r3, [pc, #76] @ (800bebc ) 800be70: 7ddb ldrb r3, [r3, #23] 800be72: 2b00 cmp r3, #0 800be74: d106 bne.n 800be84 800be76: 4b11 ldr r3, [pc, #68] @ (800bebc ) 800be78: 785b ldrb r3, [r3, #1] 800be7a: 2b03 cmp r3, #3 800be7c: d102 bne.n 800be84 CONN.EnableOutput = 0; 800be7e: 4b0f ldr r3, [pc, #60] @ (800bebc ) 800be80: 2200 movs r2, #0 800be82: 75da strb r2, [r3, #23] } } } if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800be84: 4b12 ldr r3, [pc, #72] @ (800bed0 ) 800be86: 781b ldrb r3, [r3, #0] 800be88: 2b01 cmp r3, #1 800be8a: d007 beq.n 800be9c (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800be8c: 4b10 ldr r3, [pc, #64] @ (800bed0 ) 800be8e: 781b ldrb r3, [r3, #0] if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800be90: 2b02 cmp r3, #2 800be92: d003 beq.n 800be9c (cp_state_buffer == EV_STATE_D_CONN_ACT_VENT)) { 800be94: 4b0e ldr r3, [pc, #56] @ (800bed0 ) 800be96: 781b ldrb r3, [r3, #0] (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800be98: 2b03 cmp r3, #3 800be9a: d103 bne.n 800bea4 CONN.EvConnected = 1; 800be9c: 4b07 ldr r3, [pc, #28] @ (800bebc ) 800be9e: 2201 movs r2, #1 800bea0: 779a strb r2, [r3, #30] 800bea2: e003 b.n 800beac } else { CONN.EvConnected = 0; 800bea4: 4b05 ldr r3, [pc, #20] @ (800bebc ) 800bea6: 2200 movs r2, #0 800bea8: 779a strb r2, [r3, #30] } } 800beaa: bf00 nop 800beac: bf00 nop 800beae: bd80 pop {r7, pc} 800beb0: 20000b94 .word 0x20000b94 800beb4: 20000b98 .word 0x20000b98 800beb8: 08016b88 .word 0x08016b88 800bebc: 20000398 .word 0x20000398 800bec0: 20000bf0 .word 0x20000bf0 800bec4: 20000b90 .word 0x20000b90 800bec8: 20000988 .word 0x20000988 800becc: 20000989 .word 0x20000989 800bed0: 2000004f .word 0x2000004f 0800bed4 : void CCS_Init(void){ 800bed4: b580 push {r7, lr} 800bed6: af00 add r7, sp, #0 CP_Init(); 800bed8: f7fe f8d0 bl 800a07c CP_SetDuty(100); 800bedc: 2064 movs r0, #100 @ 0x64 800bede: f7fe f8ef bl 800a0c0 CCS_MaxLoad.maxVoltage = PSU_MAX_VOLTAGE; // 1000V 800bee2: 4b11 ldr r3, [pc, #68] @ (800bf28 ) 800bee4: f44f 727a mov.w r2, #1000 @ 0x3e8 800bee8: 801a strh r2, [r3, #0] CCS_MaxLoad.minVoltage = PSU_MIN_VOLTAGE; //150V 800beea: 4b0f ldr r3, [pc, #60] @ (800bf28 ) 800beec: 2296 movs r2, #150 @ 0x96 800beee: 805a strh r2, [r3, #2] CCS_MaxLoad.maxCurrent = PSU_MAX_CURRENT*10; //100A 800bef0: 4b0d ldr r3, [pc, #52] @ (800bf28 ) 800bef2: f240 5232 movw r2, #1330 @ 0x532 800bef6: 809a strh r2, [r3, #4] CCS_MaxLoad.minCurrent = PSU_MIN_CURRENT*10; //1A 800bef8: 4b0b ldr r3, [pc, #44] @ (800bf28 ) 800befa: 220a movs r2, #10 800befc: 80da strh r2, [r3, #6] CCS_MaxLoad.maxPower = PSU_MAX_POWER; //30000W 800befe: 4b0a ldr r3, [pc, #40] @ (800bf28 ) 800bf00: f247 5230 movw r2, #30000 @ 0x7530 800bf04: 609a str r2, [r3, #8] uart3_last_packet_tick = HAL_GetTick(); 800bf06: f001 fee7 bl 800dcd8 800bf0a: 4603 mov r3, r0 800bf0c: 4a07 ldr r2, [pc, #28] @ (800bf2c ) 800bf0e: 6013 str r3, [r2, #0] uart3_last_reinit_tick = uart3_last_packet_tick; 800bf10: 4b06 ldr r3, [pc, #24] @ (800bf2c ) 800bf12: 681b ldr r3, [r3, #0] 800bf14: 4a06 ldr r2, [pc, #24] @ (800bf30 ) 800bf16: 6013 str r3, [r2, #0] CCS_SendResetReason(); 800bf18: f000 f8be bl 800c098 log_printf(LOG_INFO, "CCS init\n"); 800bf1c: 4905 ldr r1, [pc, #20] @ (800bf34 ) 800bf1e: 2007 movs r0, #7 800bf20: f7fe fa74 bl 800a40c } 800bf24: bf00 nop 800bf26: bd80 pop {r7, pc} 800bf28: 20000968 .word 0x20000968 800bf2c: 20000b9c .word 0x20000b9c 800bf30: 20000ba0 .word 0x20000ba0 800bf34: 08016b9c .word 0x08016b9c 0800bf38 : ISR_FAST static uint16_t crc16_ibm(const uint8_t* data, uint16_t length) { uint16_t crc = 0xFFFFu; for (uint16_t i = 0; i < length; i++) { 800bf38: b3e9 cbz r1, 800bfb6 800bf3a: 4684 mov ip, r0 ISR_FAST static uint16_t crc16_ibm(const uint8_t* data, uint16_t length) { 800bf3c: b500 push {lr} 800bf3e: 468e mov lr, r1 uint16_t crc = 0xFFFFu; 800bf40: f64f 70ff movw r0, #65535 @ 0xffff crc ^= data[i]; for (uint8_t j = 0; j < 8; j++) { if (crc & 1u) { 800bf44: 491d ldr r1, [pc, #116] @ (800bfbc ) 800bf46: 44e6 add lr, ip crc ^= data[i]; 800bf48: f81c 2b01 ldrb.w r2, [ip], #1 800bf4c: 4042 eors r2, r0 if (crc & 1u) { 800bf4e: f342 0300 sbfx r3, r2, #0, #1 800bf52: 400b ands r3, r1 800bf54: ea83 0352 eor.w r3, r3, r2, lsr #1 800bf58: f343 0200 sbfx r2, r3, #0, #1 800bf5c: 400a ands r2, r1 crc = (crc >> 1) ^ 0xA001u; } else { crc >>= 1; 800bf5e: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800bf62: 405a eors r2, r3 800bf64: f342 0300 sbfx r3, r2, #0, #1 800bf68: 400b ands r3, r1 crc >>= 1; 800bf6a: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800bf6e: 4053 eors r3, r2 800bf70: f343 0200 sbfx r2, r3, #0, #1 800bf74: 400a ands r2, r1 crc >>= 1; 800bf76: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800bf7a: 405a eors r2, r3 800bf7c: f342 0300 sbfx r3, r2, #0, #1 800bf80: 400b ands r3, r1 crc >>= 1; 800bf82: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800bf86: 4053 eors r3, r2 800bf88: f343 0200 sbfx r2, r3, #0, #1 800bf8c: 400a ands r2, r1 crc >>= 1; 800bf8e: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800bf92: 405a eors r2, r3 800bf94: f342 0300 sbfx r3, r2, #0, #1 800bf98: 400b ands r3, r1 crc >>= 1; 800bf9a: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800bf9e: 4053 eors r3, r2 800bfa0: f343 0000 sbfx r0, r3, #0, #1 800bfa4: 4008 ands r0, r1 crc >>= 1; 800bfa6: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800bfaa: 4058 eors r0, r3 for (uint16_t i = 0; i < length; i++) { 800bfac: 45e6 cmp lr, ip if (crc & 1u) { 800bfae: b280 uxth r0, r0 for (uint16_t i = 0; i < length; i++) { 800bfb0: d1ca bne.n 800bf48 } } } return crc; } 800bfb2: f85d fb04 ldr.w pc, [sp], #4 uint16_t crc = 0xFFFFu; 800bfb6: f64f 70ff movw r0, #65535 @ 0xffff } 800bfba: 4770 bx lr 800bfbc: ffffa001 .word 0xffffa001 0800bfc0 : static uint16_t CCS_BuildPacket(uint8_t cmd, const void* payload, uint16_t payload_len, uint8_t* out, uint16_t out_max) { 800bfc0: b580 push {r7, lr} 800bfc2: b086 sub sp, #24 800bfc4: af00 add r7, sp, #0 800bfc6: 60b9 str r1, [r7, #8] 800bfc8: 607b str r3, [r7, #4] 800bfca: 4603 mov r3, r0 800bfcc: 73fb strb r3, [r7, #15] 800bfce: 4613 mov r3, r2 800bfd0: 81bb strh r3, [r7, #12] uint16_t total_len = (uint16_t)(1u + payload_len + 2u); 800bfd2: 89bb ldrh r3, [r7, #12] 800bfd4: 3303 adds r3, #3 800bfd6: 82fb strh r3, [r7, #22] if (total_len > out_max) return 0; 800bfd8: 8afa ldrh r2, [r7, #22] 800bfda: 8c3b ldrh r3, [r7, #32] 800bfdc: 429a cmp r2, r3 800bfde: d901 bls.n 800bfe4 800bfe0: 2300 movs r3, #0 800bfe2: e029 b.n 800c038 out[0] = cmd; 800bfe4: 687b ldr r3, [r7, #4] 800bfe6: 7bfa ldrb r2, [r7, #15] 800bfe8: 701a strb r2, [r3, #0] if (payload_len && payload != NULL) { 800bfea: 89bb ldrh r3, [r7, #12] 800bfec: 2b00 cmp r3, #0 800bfee: d009 beq.n 800c004 800bff0: 68bb ldr r3, [r7, #8] 800bff2: 2b00 cmp r3, #0 800bff4: d006 beq.n 800c004 memcpy(&out[1], payload, payload_len); 800bff6: 687b ldr r3, [r7, #4] 800bff8: 3301 adds r3, #1 800bffa: 89ba ldrh r2, [r7, #12] 800bffc: 68b9 ldr r1, [r7, #8] 800bffe: 4618 mov r0, r3 800c000: f008 fa46 bl 8014490 } uint16_t crc = crc16_ibm(out, (uint16_t)(1u + payload_len)); 800c004: 89bb ldrh r3, [r7, #12] 800c006: 3301 adds r3, #1 800c008: b29b uxth r3, r3 800c00a: 4619 mov r1, r3 800c00c: 6878 ldr r0, [r7, #4] 800c00e: f7ff ff93 bl 800bf38 800c012: 4603 mov r3, r0 800c014: 82bb strh r3, [r7, #20] out[1u + payload_len] = (uint8_t)(crc & 0xFFu); 800c016: 89bb ldrh r3, [r7, #12] 800c018: 3301 adds r3, #1 800c01a: 687a ldr r2, [r7, #4] 800c01c: 4413 add r3, r2 800c01e: 8aba ldrh r2, [r7, #20] 800c020: b2d2 uxtb r2, r2 800c022: 701a strb r2, [r3, #0] out[1u + payload_len + 1u] = (uint8_t)((crc >> 8) & 0xFFu); 800c024: 8abb ldrh r3, [r7, #20] 800c026: 0a1b lsrs r3, r3, #8 800c028: b299 uxth r1, r3 800c02a: 89bb ldrh r3, [r7, #12] 800c02c: 3302 adds r3, #2 800c02e: 687a ldr r2, [r7, #4] 800c030: 4413 add r3, r2 800c032: b2ca uxtb r2, r1 800c034: 701a strb r2, [r3, #0] return total_len; 800c036: 8afb ldrh r3, [r7, #22] } 800c038: 4618 mov r0, r3 800c03a: 3718 adds r7, #24 800c03c: 46bd mov sp, r7 800c03e: bd80 pop {r7, pc} 0800c040 : static void CCS_SendPacket(uint8_t cmd, const void* payload, uint16_t payload_len) { 800c040: b580 push {r7, lr} 800c042: b086 sub sp, #24 800c044: af02 add r7, sp, #8 800c046: 4603 mov r3, r0 800c048: 6039 str r1, [r7, #0] 800c04a: 71fb strb r3, [r7, #7] 800c04c: 4613 mov r3, r2 800c04e: 80bb strh r3, [r7, #4] uint16_t len = CCS_BuildPacket(cmd, payload, payload_len, tx_buffer, sizeof(tx_buffer)); 800c050: 88ba ldrh r2, [r7, #4] 800c052: 79f8 ldrb r0, [r7, #7] 800c054: f44f 7380 mov.w r3, #256 @ 0x100 800c058: 9300 str r3, [sp, #0] 800c05a: 4b0c ldr r3, [pc, #48] @ (800c08c ) 800c05c: 6839 ldr r1, [r7, #0] 800c05e: f7ff ffaf bl 800bfc0 800c062: 4603 mov r3, r0 800c064: 81fb strh r3, [r7, #14] if (len > 0) { 800c066: 89fb ldrh r3, [r7, #14] 800c068: 2b00 cmp r3, #0 800c06a: d005 beq.n 800c078 HAL_UART_Transmit_IT(&huart3, tx_buffer, len); 800c06c: 89fb ldrh r3, [r7, #14] 800c06e: 461a mov r2, r3 800c070: 4906 ldr r1, [pc, #24] @ (800c08c ) 800c072: 4807 ldr r0, [pc, #28] @ (800c090 ) 800c074: f006 fd42 bl 8012afc } last_cmd_sent = HAL_GetTick(); 800c078: f001 fe2e bl 800dcd8 800c07c: 4603 mov r3, r0 800c07e: 4a05 ldr r2, [pc, #20] @ (800c094 ) 800c080: 6013 str r3, [r2, #0] } 800c082: bf00 nop 800c084: 3710 adds r7, #16 800c086: 46bd mov sp, r7 800c088: bd80 pop {r7, pc} 800c08a: bf00 nop 800c08c: 20000a8c .word 0x20000a8c 800c090: 20001200 .word 0x20001200 800c094: 20000980 .word 0x20000980 0800c098 : static void CCS_SendResetReason(void) { 800c098: b580 push {r7, lr} 800c09a: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_RESET, NULL, 0); 800c09c: 2200 movs r2, #0 800c09e: 2100 movs r1, #0 800c0a0: 2052 movs r0, #82 @ 0x52 800c0a2: f7ff ffcd bl 800c040 } 800c0a6: bf00 nop 800c0a8: bd80 pop {r7, pc} 800c0aa: bf00 nop 0800c0ac : void CCS_SendEmergencyStop(void) { 800c0ac: b580 push {r7, lr} 800c0ae: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_ESTOP, NULL, 0); 800c0b0: 2200 movs r2, #0 800c0b2: 2100 movs r1, #0 800c0b4: 2053 movs r0, #83 @ 0x53 800c0b6: f7ff ffc3 bl 800c040 } 800c0ba: bf00 nop 800c0bc: bd80 pop {r7, pc} 800c0be: bf00 nop 0800c0c0 : void CCS_SendStart(void) { CCS_SendPacket(CMD_M2E_START, NULL, 0); } static void CCS_CalculateEnergy(void) { 800c0c0: b580 push {r7, lr} 800c0c2: b082 sub sp, #8 800c0c4: af00 add r7, sp, #0 static uint32_t lastTick = 0; uint32_t currentTick = HAL_GetTick(); 800c0c6: f001 fe07 bl 800dcd8 800c0ca: 6078 str r0, [r7, #4] uint32_t elapsedTimeMs = currentTick - lastTick; 800c0cc: 4b1e ldr r3, [pc, #120] @ (800c148 ) 800c0ce: 681b ldr r3, [r3, #0] 800c0d0: 687a ldr r2, [r7, #4] 800c0d2: 1ad3 subs r3, r2, r3 800c0d4: 603b str r3, [r7, #0] lastTick = currentTick; 800c0d6: 4a1c ldr r2, [pc, #112] @ (800c148 ) 800c0d8: 687b ldr r3, [r7, #4] 800c0da: 6013 str r3, [r2, #0] CCS_Power = CONN.MeasuredVoltage * CONN.MeasuredCurrent / 10; 800c0dc: 4b1b ldr r3, [pc, #108] @ (800c14c ) 800c0de: f8b3 3013 ldrh.w r3, [r3, #19] 800c0e2: b29b uxth r3, r3 800c0e4: 461a mov r2, r3 800c0e6: 4b19 ldr r3, [pc, #100] @ (800c14c ) 800c0e8: f8b3 3015 ldrh.w r3, [r3, #21] 800c0ec: b29b uxth r3, r3 800c0ee: fb02 f303 mul.w r3, r2, r3 800c0f2: 4a17 ldr r2, [pc, #92] @ (800c150 ) 800c0f4: fb82 1203 smull r1, r2, r2, r3 800c0f8: 1092 asrs r2, r2, #2 800c0fa: 17db asrs r3, r3, #31 800c0fc: 1ad3 subs r3, r2, r3 800c0fe: 461a mov r2, r3 800c100: 4b14 ldr r3, [pc, #80] @ (800c154 ) 800c102: 601a str r2, [r3, #0] CCS_EnergyWs += (CCS_Power * elapsedTimeMs) / 1000; 800c104: 4b13 ldr r3, [pc, #76] @ (800c154 ) 800c106: 681b ldr r3, [r3, #0] 800c108: 683a ldr r2, [r7, #0] 800c10a: fb02 f303 mul.w r3, r2, r3 800c10e: 4a12 ldr r2, [pc, #72] @ (800c158 ) 800c110: fba2 2303 umull r2, r3, r2, r3 800c114: 099a lsrs r2, r3, #6 800c116: 4b11 ldr r3, [pc, #68] @ (800c15c ) 800c118: 681b ldr r3, [r3, #0] 800c11a: 4413 add r3, r2 800c11c: 4a0f ldr r2, [pc, #60] @ (800c15c ) 800c11e: 6013 str r3, [r2, #0] if(CCS_EvseState == Unplugged) { 800c120: 4b0f ldr r3, [pc, #60] @ (800c160 ) 800c122: 781b ldrb r3, [r3, #0] 800c124: 2b01 cmp r3, #1 800c126: d102 bne.n 800c12e CCS_EnergyWs = 0; 800c128: 4b0c ldr r3, [pc, #48] @ (800c15c ) 800c12a: 2200 movs r2, #0 800c12c: 601a str r2, [r3, #0] } CCS_Energy = CCS_EnergyWs / 3600; 800c12e: 4b0b ldr r3, [pc, #44] @ (800c15c ) 800c130: 681b ldr r3, [r3, #0] 800c132: 4a0c ldr r2, [pc, #48] @ (800c164 ) 800c134: fba2 2303 umull r2, r3, r2, r3 800c138: 0adb lsrs r3, r3, #11 800c13a: 4a0b ldr r2, [pc, #44] @ (800c168 ) 800c13c: 6013 str r3, [r2, #0] } 800c13e: bf00 nop 800c140: 3708 adds r7, #8 800c142: 46bd mov sp, r7 800c144: bd80 pop {r7, pc} 800c146: bf00 nop 800c148: 20000bfc .word 0x20000bfc 800c14c: 20000398 .word 0x20000398 800c150: 66666667 .word 0x66666667 800c154: 20000974 .word 0x20000974 800c158: 10624dd3 .word 0x10624dd3 800c15c: 20000978 .word 0x20000978 800c160: 20000bf0 .word 0x20000bf0 800c164: 91a2b3c5 .word 0x91a2b3c5 800c168: 2000097c .word 0x2000097c 0800c16c : static void send_state(void) { 800c16c: b580 push {r7, lr} 800c16e: af00 add r7, sp, #0 CCS_CalculateEnergy(); 800c170: f7ff ffa6 bl 800c0c0 CCS_State.DutyCycle = CP_GetDuty(); 800c174: f7fd ffcc bl 800a110 800c178: 4603 mov r3, r0 800c17a: 461a mov r2, r3 800c17c: 4b30 ldr r3, [pc, #192] @ (800c240 ) 800c17e: 701a strb r2, [r3, #0] CCS_State.OutputEnabled = PSU0.CONT_enabled; 800c180: 4b30 ldr r3, [pc, #192] @ (800c244 ) 800c182: 7ada ldrb r2, [r3, #11] 800c184: 4b2e ldr r3, [pc, #184] @ (800c240 ) 800c186: 705a strb r2, [r3, #1] CCS_State.MeasuredVoltage = (uint16_t)CONN.MeasuredVoltage; 800c188: 4b2f ldr r3, [pc, #188] @ (800c248 ) 800c18a: f8b3 3013 ldrh.w r3, [r3, #19] 800c18e: b29a uxth r2, r3 800c190: 4b2b ldr r3, [pc, #172] @ (800c240 ) 800c192: 805a strh r2, [r3, #2] if (CONN.RequestedVoltage == 500) CCS_State.MeasuredVoltage = 500; // fake 800c194: 4b2c ldr r3, [pc, #176] @ (800c248 ) 800c196: f8b3 300f ldrh.w r3, [r3, #15] 800c19a: b29b uxth r3, r3 800c19c: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800c1a0: d103 bne.n 800c1aa 800c1a2: 4b27 ldr r3, [pc, #156] @ (800c240 ) 800c1a4: f44f 72fa mov.w r2, #500 @ 0x1f4 800c1a8: 805a strh r2, [r3, #2] CCS_State.MeasuredCurrent = (uint16_t)CONN.MeasuredCurrent; 800c1aa: 4b27 ldr r3, [pc, #156] @ (800c248 ) 800c1ac: f8b3 3015 ldrh.w r3, [r3, #21] 800c1b0: b29a uxth r2, r3 800c1b2: 4b23 ldr r3, [pc, #140] @ (800c240 ) 800c1b4: 809a strh r2, [r3, #4] CCS_State.Power = CCS_Power; 800c1b6: 4b25 ldr r3, [pc, #148] @ (800c24c ) 800c1b8: 681b ldr r3, [r3, #0] 800c1ba: 4a21 ldr r2, [pc, #132] @ (800c240 ) 800c1bc: f8c2 3006 str.w r3, [r2, #6] CCS_State.Energy = CCS_Energy; 800c1c0: 4b23 ldr r3, [pc, #140] @ (800c250 ) 800c1c2: 681b ldr r3, [r3, #0] 800c1c4: 4a1e ldr r2, [pc, #120] @ (800c240 ) 800c1c6: f8c2 300a str.w r3, [r2, #10] if(CCS_ConnectorState == CCS_CONNECTED){ 800c1ca: 4b22 ldr r3, [pc, #136] @ (800c254 ) 800c1cc: 781b ldrb r3, [r3, #0] 800c1ce: 2b03 cmp r3, #3 800c1d0: d104 bne.n 800c1dc CCS_State.CpState = cp_state_buffer; 800c1d2: 4b21 ldr r3, [pc, #132] @ (800c258 ) 800c1d4: 781a ldrb r2, [r3, #0] 800c1d6: 4b1a ldr r3, [pc, #104] @ (800c240 ) 800c1d8: 74da strb r2, [r3, #19] 800c1da: e002 b.n 800c1e2 } else { CCS_State.CpState = EV_STATE_A_IDLE; 800c1dc: 4b18 ldr r3, [pc, #96] @ (800c240 ) 800c1de: 2200 movs r2, #0 800c1e0: 74da strb r2, [r3, #19] } CCS_State.MaxVoltage = CCS_MaxLoad.maxVoltage; 800c1e2: 4b1e ldr r3, [pc, #120] @ (800c25c ) 800c1e4: 881a ldrh r2, [r3, #0] 800c1e6: 4b16 ldr r3, [pc, #88] @ (800c240 ) 800c1e8: 829a strh r2, [r3, #20] CCS_State.MinVoltage = CCS_MaxLoad.minVoltage; 800c1ea: 4b1c ldr r3, [pc, #112] @ (800c25c ) 800c1ec: 885a ldrh r2, [r3, #2] 800c1ee: 4b14 ldr r3, [pc, #80] @ (800c240 ) 800c1f0: 82da strh r2, [r3, #22] CCS_State.MaxCurrent = CCS_MaxLoad.maxCurrent; 800c1f2: 4b1a ldr r3, [pc, #104] @ (800c25c ) 800c1f4: 889a ldrh r2, [r3, #4] 800c1f6: 4b12 ldr r3, [pc, #72] @ (800c240 ) 800c1f8: 831a strh r2, [r3, #24] CCS_State.MinCurrent = CCS_MaxLoad.minCurrent; 800c1fa: 4b18 ldr r3, [pc, #96] @ (800c25c ) 800c1fc: 88da ldrh r2, [r3, #6] 800c1fe: 4b10 ldr r3, [pc, #64] @ (800c240 ) 800c200: 835a strh r2, [r3, #26] CCS_State.MaxPower = CCS_MaxLoad.maxPower; 800c202: 4b16 ldr r3, [pc, #88] @ (800c25c ) 800c204: 689b ldr r3, [r3, #8] 800c206: 4a0e ldr r2, [pc, #56] @ (800c240 ) 800c208: 61d3 str r3, [r2, #28] CCS_State.IsolationValid = isolation_enable; 800c20a: 4b15 ldr r3, [pc, #84] @ (800c260 ) 800c20c: 781a ldrb r2, [r3, #0] 800c20e: 4b0c ldr r3, [pc, #48] @ (800c240 ) 800c210: 749a strb r2, [r3, #18] CCS_State.IsolationResistance = 900000; 800c212: 4a0b ldr r2, [pc, #44] @ (800c240 ) 800c214: 2300 movs r3, #0 800c216: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800c21a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800c21e: f443 433b orr.w r3, r3, #47872 @ 0xbb00 800c222: f043 03a0 orr.w r3, r3, #160 @ 0xa0 800c226: 81d3 strh r3, [r2, #14] 800c228: 2300 movs r3, #0 800c22a: f043 030d orr.w r3, r3, #13 800c22e: 8213 strh r3, [r2, #16] CCS_SendPacket(CMD_M2E_STATE, &CCS_State, sizeof(CCS_State)); 800c230: 2220 movs r2, #32 800c232: 4903 ldr r1, [pc, #12] @ (800c240 ) 800c234: 2050 movs r0, #80 @ 0x50 800c236: f7ff ff03 bl 800c040 } 800c23a: bf00 nop 800c23c: bd80 pop {r7, pc} 800c23e: bf00 nop 800c240: 20000ba4 .word 0x20000ba4 800c244: 200008e4 .word 0x200008e4 800c248: 20000398 .word 0x20000398 800c24c: 20000974 .word 0x20000974 800c250: 2000097c .word 0x2000097c 800c254: 20000050 .word 0x20000050 800c258: 2000004f .word 0x2000004f 800c25c: 20000968 .word 0x20000968 800c260: 20000b8f .word 0x20000b8f 0800c264 : ISR_FAST static uint16_t expected_payload_len(uint8_t cmd) { switch (cmd) { 800c264: 3840 subs r0, #64 @ 0x40 800c266: b2c0 uxtb r0, r0 800c268: 2809 cmp r0, #9 800c26a: bf9a itte ls 800c26c: 4b02 ldrls r3, [pc, #8] @ (800c278 ) 800c26e: f833 0010 ldrhls.w r0, [r3, r0, lsl #1] ISR_FAST static uint16_t expected_payload_len(uint8_t cmd) { 800c272: f64f 70ff movwhi r0, #65535 @ 0xffff case CMD_E2M_EV_INFO: return sizeof(CCS_EvInfo_t); case CMD_E2M_EVSE_STATE: return sizeof(CONN_State_t); case CMD_E2M_KEEP_ALIVE: return 0; default: return 0xFFFFu; } } 800c276: 4770 bx lr 800c278: 08016e70 .word 0x08016e70 0800c27c : ISR_FAST static void apply_command(uint8_t cmd, const uint8_t* payload, uint16_t payload_len) { 800c27c: b5f8 push {r3, r4, r5, r6, r7, lr} 800c27e: 4604 mov r4, r0 800c280: 460e mov r6, r1 (void)payload_len; last_host_seen = HAL_GetTick(); 800c282: f001 fd29 bl 800dcd8 everest_timed_out = 0; 800c286: 2300 movs r3, #0 800c288: 4a37 ldr r2, [pc, #220] @ (800c368 ) last_host_seen = HAL_GetTick(); 800c28a: 4d38 ldr r5, [pc, #224] @ (800c36c ) everest_timed_out = 0; 800c28c: 7013 strb r3, [r2, #0] last_everest_timeout_log_tick = 0; 800c28e: 4a38 ldr r2, [pc, #224] @ (800c370 ) last_host_seen = HAL_GetTick(); 800c290: 6028 str r0, [r5, #0] last_everest_timeout_log_tick = 0; 800c292: 6013 str r3, [r2, #0] switch (cmd) { 800c294: f1a4 0340 sub.w r3, r4, #64 @ 0x40 800c298: 2b09 cmp r3, #9 800c29a: d85d bhi.n 800c358 800c29c: e8df f003 tbb [pc, r3] 800c2a0: 231a1309 .word 0x231a1309 800c2a4: 3c38302a .word 0x3c38302a 800c2a8: 0558 .short 0x0558 (void)payload; CP_SetDuty(pwm_duty_percent); break; } case CMD_E2M_KEEP_ALIVE: { last_host_seen = HAL_GetTick(); 800c2aa: f001 fd15 bl 800dcd8 800c2ae: 6028 str r0, [r5, #0] log_printf(LOG_WARN, "UART3 RX warn: cmd 0x%02x CRC/len OK but no switch case (expected_payload vs apply_command)\n", cmd); break; } } 800c2b0: bdf8 pop {r3, r4, r5, r6, r7, pc} if (duty > 100) duty = 100; 800c2b2: 7830 ldrb r0, [r6, #0] pwm_duty_percent = duty; 800c2b4: 4b2f ldr r3, [pc, #188] @ (800c374 ) if (duty > 100) duty = 100; 800c2b6: 2864 cmp r0, #100 @ 0x64 800c2b8: bf28 it cs 800c2ba: 2064 movcs r0, #100 @ 0x64 pwm_duty_percent = duty; 800c2bc: 7018 strb r0, [r3, #0] } 800c2be: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} CP_SetDuty(duty); 800c2c2: f7fd befd b.w 800a0c0 ev_enable_output = (p->enable_output != 0); 800c2c6: 7833 ldrb r3, [r6, #0] 800c2c8: 4a2b ldr r2, [pc, #172] @ (800c378 ) 800c2ca: 3b00 subs r3, #0 800c2cc: bf18 it ne 800c2ce: 2301 movne r3, #1 800c2d0: 7013 strb r3, [r2, #0] } 800c2d2: bdf8 pop {r3, r4, r5, r6, r7, pc} if (p->reset) { 800c2d4: 7833 ldrb r3, [r6, #0] 800c2d6: 2b00 cmp r3, #0 800c2d8: d0ea beq.n 800c2b0 } 800c2da: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} log_printf(LOG_WARN, "Everest reset command\n"); 800c2de: 2005 movs r0, #5 800c2e0: 4926 ldr r1, [pc, #152] @ (800c37c ) 800c2e2: f7fe b893 b.w 800a40c enabled = (p->enable != 0); 800c2e6: 7833 ldrb r3, [r6, #0] 800c2e8: 4a25 ldr r2, [pc, #148] @ (800c380 ) 800c2ea: 3b00 subs r3, #0 800c2ec: bf18 it ne 800c2ee: 2301 movne r3, #1 800c2f0: 7013 strb r3, [r2, #0] } 800c2f2: bdf8 pop {r3, r4, r5, r6, r7, pc} CP_SetDuty(pwm_duty_percent); 800c2f4: 4b1f ldr r3, [pc, #124] @ (800c374 ) 800c2f6: 7818 ldrb r0, [r3, #0] } 800c2f8: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} CP_SetDuty(pwm_duty_percent); 800c2fc: f7fd bee0 b.w 800a0c0 CONN.RequestedVoltage = p->voltage_V; 800c300: 8832 ldrh r2, [r6, #0] 800c302: 4b20 ldr r3, [pc, #128] @ (800c384 ) 800c304: f8a3 200f strh.w r2, [r3, #15] CONN.WantedCurrent = p->current_0p1A; 800c308: 8872 ldrh r2, [r6, #2] 800c30a: f8a3 201b strh.w r2, [r3, #27] } 800c30e: bdf8 pop {r3, r4, r5, r6, r7, pc} isolation_enable = p->command; 800c310: 7832 ldrb r2, [r6, #0] 800c312: 4b1d ldr r3, [pc, #116] @ (800c388 ) 800c314: 701a strb r2, [r3, #0] } 800c316: bdf8 pop {r3, r4, r5, r6, r7, pc} memcpy(&CCS_EvInfo, payload, sizeof(CCS_EvInfo_t)); 800c318: 4f1c ldr r7, [pc, #112] @ (800c38c ) 800c31a: 4634 mov r4, r6 800c31c: 463e mov r6, r7 800c31e: f104 0c20 add.w ip, r4, #32 800c322: 4635 mov r5, r6 800c324: 6820 ldr r0, [r4, #0] 800c326: 6861 ldr r1, [r4, #4] 800c328: 68a2 ldr r2, [r4, #8] 800c32a: 68e3 ldr r3, [r4, #12] 800c32c: 3410 adds r4, #16 800c32e: 4564 cmp r4, ip 800c330: c50f stmia r5!, {r0, r1, r2, r3} 800c332: f106 0610 add.w r6, r6, #16 800c336: d1f4 bne.n 800c322 800c338: 6861 ldr r1, [r4, #4] 800c33a: 68a2 ldr r2, [r4, #8] 800c33c: 6820 ldr r0, [r4, #0] 800c33e: c607 stmia r6!, {r0, r1, r2} CONN.SOC = (uint8_t)(CCS_EvInfo.soc / 10); 800c340: 4a13 ldr r2, [pc, #76] @ (800c390 ) 800c342: 887b ldrh r3, [r7, #2] 800c344: 490f ldr r1, [pc, #60] @ (800c384 ) 800c346: fba2 2303 umull r2, r3, r2, r3 800c34a: 08db lsrs r3, r3, #3 800c34c: 708b strb r3, [r1, #2] } 800c34e: bdf8 pop {r3, r4, r5, r6, r7, pc} CCS_EvseState = (CONN_State_t)payload[0]; 800c350: 7832 ldrb r2, [r6, #0] 800c352: 4b10 ldr r3, [pc, #64] @ (800c394 ) 800c354: 701a strb r2, [r3, #0] } 800c356: bdf8 pop {r3, r4, r5, r6, r7, pc} log_printf(LOG_WARN, 800c358: 4622 mov r2, r4 } 800c35a: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} log_printf(LOG_WARN, 800c35e: 2005 movs r0, #5 800c360: 490d ldr r1, [pc, #52] @ (800c398 ) 800c362: f7fe b853 b.w 800a40c 800c366: bf00 nop 800c368: 20000b94 .word 0x20000b94 800c36c: 20000b90 .word 0x20000b90 800c370: 20000b98 .word 0x20000b98 800c374: 2000004e .word 0x2000004e 800c378: 20000989 .word 0x20000989 800c37c: 08016ba8 .word 0x08016ba8 800c380: 20000b8e .word 0x20000b8e 800c384: 20000398 .word 0x20000398 800c388: 20000b8f .word 0x20000b8f 800c38c: 20000bc4 .word 0x20000bc4 800c390: cccccccd .word 0xcccccccd 800c394: 20000bf0 .word 0x20000bf0 800c398: 08016bc0 .word 0x08016bc0 0800c39c : ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len) { 800c39c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} if (packet_len < 3u) { 800c3a0: 2902 cmp r1, #2 ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len) { 800c3a2: 460c mov r4, r1 800c3a4: 4605 mov r5, r0 800c3a6: b084 sub sp, #16 if (packet_len < 3u) { 800c3a8: d930 bls.n 800c40c uint8_t cmd = packet[0]; uint16_t payload_len = (uint16_t)(packet_len - 3u); uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | (uint16_t)packet[packet_len - 1u] << 8; 800c3aa: 1843 adds r3, r0, r1 uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c3ac: f813 2c01 ldrb.w r2, [r3, #-1] 800c3b0: f813 7c02 ldrb.w r7, [r3, #-2] uint16_t payload_len = (uint16_t)(packet_len - 3u); 800c3b4: 1ece subs r6, r1, #3 uint16_t calculated_crc = crc16_ibm(packet, (uint16_t)(1u + payload_len)); 800c3b6: 3902 subs r1, #2 800c3b8: b289 uxth r1, r1 uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c3ba: ea47 2702 orr.w r7, r7, r2, lsl #8 uint8_t cmd = packet[0]; 800c3be: f890 8000 ldrb.w r8, [r0] uint16_t calculated_crc = crc16_ibm(packet, (uint16_t)(1u + payload_len)); 800c3c2: f7ff fdb9 bl 800bf38 if (received_crc != calculated_crc) { 800c3c6: 4287 cmp r7, r0 uint16_t payload_len = (uint16_t)(packet_len - 3u); 800c3c8: b2b6 uxth r6, r6 if (received_crc != calculated_crc) { 800c3ca: d112 bne.n 800c3f2 cmd, (unsigned)packet_len, (unsigned)payload_len, (unsigned)received_crc, (unsigned)calculated_crc); return 0; } uint16_t expected_len = expected_payload_len(cmd); 800c3cc: 4640 mov r0, r8 800c3ce: f7ff ff49 bl 800c264 if (expected_len == 0xFFFFu) { 800c3d2: f64f 72ff movw r2, #65535 @ 0xffff 800c3d6: 4290 cmp r0, r2 800c3d8: d03a beq.n 800c450 log_printf(LOG_WARN, "UART3 RX drop: unknown_cmd cmd=0x%02x total_len=%u payload_len=%u\n", cmd, (unsigned)packet_len, (unsigned)payload_len); return 0; } if (expected_len != payload_len) { 800c3da: 4286 cmp r6, r0 800c3dc: d12a bne.n 800c434 cmd, (unsigned)expected_len, (unsigned)payload_len, (unsigned)packet_len); return 0; } if (payload_len > 0) { apply_command(cmd, &packet[1], payload_len); 800c3de: 4632 mov r2, r6 if (payload_len > 0) { 800c3e0: b9fe cbnz r6, 800c422 } else { apply_command(cmd, NULL, 0); 800c3e2: 4631 mov r1, r6 800c3e4: 4640 mov r0, r8 800c3e6: f7ff ff49 bl 800c27c } return 1; 800c3ea: 2001 movs r0, #1 } 800c3ec: b004 add sp, #16 800c3ee: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} log_printf(LOG_ERR, 800c3f2: 9002 str r0, [sp, #8] 800c3f4: 4623 mov r3, r4 800c3f6: 4642 mov r2, r8 800c3f8: 2004 movs r0, #4 800c3fa: e9cd 6700 strd r6, r7, [sp] 800c3fe: 4918 ldr r1, [pc, #96] @ (800c460 ) 800c400: f7fe f804 bl 800a40c return 0; 800c404: 2000 movs r0, #0 } 800c406: b004 add sp, #16 800c408: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} if (packet_len == 0u) { 800c40c: b1d9 cbz r1, 800c446 } else if (packet_len == 1u) { 800c40e: 2901 cmp r1, #1 log_printf(LOG_WARN, "UART3 RX drop: too_short len=1 b0=0x%02x\n", packet[0]); 800c410: 7802 ldrb r2, [r0, #0] 800c412: f04f 0005 mov.w r0, #5 } else if (packet_len == 1u) { 800c416: d009 beq.n 800c42c log_printf(LOG_WARN, "UART3 RX drop: too_short len=2 b0=0x%02x b1=0x%02x\n", 800c418: 786b ldrb r3, [r5, #1] 800c41a: 4912 ldr r1, [pc, #72] @ (800c464 ) 800c41c: f7fd fff6 bl 800a40c 800c420: e7f0 b.n 800c404 apply_command(cmd, &packet[1], payload_len); 800c422: 4640 mov r0, r8 800c424: 1c69 adds r1, r5, #1 800c426: f7ff ff29 bl 800c27c 800c42a: e7de b.n 800c3ea log_printf(LOG_WARN, "UART3 RX drop: too_short len=1 b0=0x%02x\n", packet[0]); 800c42c: 490e ldr r1, [pc, #56] @ (800c468 ) 800c42e: f7fd ffed bl 800a40c 800c432: e7e7 b.n 800c404 log_printf(LOG_ERR, 800c434: 4603 mov r3, r0 800c436: 4642 mov r2, r8 800c438: e9cd 6400 strd r6, r4, [sp] 800c43c: 490b ldr r1, [pc, #44] @ (800c46c ) 800c43e: 2004 movs r0, #4 800c440: f7fd ffe4 bl 800a40c return 0; 800c444: e7de b.n 800c404 log_printf(LOG_WARN, "UART3 RX drop: too_short len=0 (empty chunk)\n"); 800c446: 490a ldr r1, [pc, #40] @ (800c470 ) 800c448: 2005 movs r0, #5 800c44a: f7fd ffdf bl 800a40c 800c44e: e7d9 b.n 800c404 log_printf(LOG_WARN, 800c450: 4623 mov r3, r4 800c452: 4642 mov r2, r8 800c454: 4907 ldr r1, [pc, #28] @ (800c474 ) 800c456: 9600 str r6, [sp, #0] 800c458: 2005 movs r0, #5 800c45a: f7fd ffd7 bl 800a40c return 0; 800c45e: e7d1 b.n 800c404 800c460: 08016cb0 .word 0x08016cb0 800c464: 08016c7c .word 0x08016c7c 800c468: 08016c50 .word 0x08016c50 800c46c: 08016d58 .word 0x08016d58 800c470: 08016c20 .word 0x08016c20 800c474: 08016d14 .word 0x08016d14 0800c478 : static void CCS_UART3_Watchdog(void) { 800c478: b580 push {r7, lr} 800c47a: b082 sub sp, #8 800c47c: af00 add r7, sp, #0 const uint32_t now = HAL_GetTick(); 800c47e: f001 fc2b bl 800dcd8 800c482: 6078 str r0, [r7, #4] const uint32_t since_last_packet = now - uart3_last_packet_tick; 800c484: 4b16 ldr r3, [pc, #88] @ (800c4e0 ) 800c486: 681b ldr r3, [r3, #0] 800c488: 687a ldr r2, [r7, #4] 800c48a: 1ad3 subs r3, r2, r3 800c48c: 603b str r3, [r7, #0] if ((since_last_packet >= UART3_REINIT_TIMEOUT_MS) && 800c48e: 683b ldr r3, [r7, #0] 800c490: f240 52db movw r2, #1499 @ 0x5db 800c494: 4293 cmp r3, r2 800c496: d91f bls.n 800c4d8 ((now - uart3_last_reinit_tick) >= UART3_REINIT_TIMEOUT_MS)) { 800c498: 4b12 ldr r3, [pc, #72] @ (800c4e4 ) 800c49a: 681b ldr r3, [r3, #0] 800c49c: 687a ldr r2, [r7, #4] 800c49e: 1ad3 subs r3, r2, r3 if ((since_last_packet >= UART3_REINIT_TIMEOUT_MS) && 800c4a0: f240 52db movw r2, #1499 @ 0x5db 800c4a4: 4293 cmp r3, r2 800c4a6: d917 bls.n 800c4d8 (void)HAL_UART_Abort_IT(&huart3); 800c4a8: 480f ldr r0, [pc, #60] @ (800c4e8 ) 800c4aa: f006 fbb9 bl 8012c20 (void)HAL_UART_DeInit(&huart3); 800c4ae: 480e ldr r0, [pc, #56] @ (800c4e8 ) 800c4b0: f006 faf2 bl 8012a98 (void)HAL_UART_Init(&huart3); 800c4b4: 480c ldr r0, [pc, #48] @ (800c4e8 ) 800c4b6: f006 fa9f bl 80129f8 (void)HAL_UARTEx_ReceiveToIdle_IT(&huart3, rx_buffer, sizeof(rx_buffer)); 800c4ba: f44f 7280 mov.w r2, #256 @ 0x100 800c4be: 490b ldr r1, [pc, #44] @ (800c4ec ) 800c4c0: 4809 ldr r0, [pc, #36] @ (800c4e8 ) 800c4c2: f006 fb50 bl 8012b66 log_printf(LOG_ERR, 800c4c6: f240 52dc movw r2, #1500 @ 0x5dc 800c4ca: 4909 ldr r1, [pc, #36] @ (800c4f0 ) 800c4cc: 2004 movs r0, #4 800c4ce: f7fd ff9d bl 800a40c "UART3 RX recover: stalled (no RxEvent data for %ums), hard reinit\n", (unsigned)UART3_REINIT_TIMEOUT_MS); uart3_last_reinit_tick = now; 800c4d2: 4a04 ldr r2, [pc, #16] @ (800c4e4 ) 800c4d4: 687b ldr r3, [r7, #4] 800c4d6: 6013 str r3, [r2, #0] } } 800c4d8: bf00 nop 800c4da: 3708 adds r7, #8 800c4dc: 46bd mov sp, r7 800c4de: bd80 pop {r7, pc} 800c4e0: 20000b9c .word 0x20000b9c 800c4e4: 20000ba0 .word 0x20000ba0 800c4e8: 20001200 .word 0x20001200 800c4ec: 2000098c .word 0x2000098c 800c4f0: 08016db0 .word 0x08016db0 0800c4f4 : .fw_version_major = 0, .fw_version_minor = 0, .fw_version_patch = 0, }; void ReadVersion(){ 800c4f4: b480 push {r7} 800c4f6: af00 add r7, sp, #0 infoPacket.serialNumber = InfoBlock->serialNumber; 800c4f8: 4b0e ldr r3, [pc, #56] @ (800c534 ) 800c4fa: 681b ldr r3, [r3, #0] 800c4fc: 681b ldr r3, [r3, #0] 800c4fe: b29a uxth r2, r3 800c500: 4b0d ldr r3, [pc, #52] @ (800c538 ) 800c502: 801a strh r2, [r3, #0] infoPacket.boardVersion = InfoBlock->boardVersion; 800c504: 4b0b ldr r3, [pc, #44] @ (800c534 ) 800c506: 681b ldr r3, [r3, #0] 800c508: 795a ldrb r2, [r3, #5] 800c50a: 4b0b ldr r3, [pc, #44] @ (800c538 ) 800c50c: 709a strb r2, [r3, #2] infoPacket.stationType = InfoBlock->stationType; 800c50e: 4b09 ldr r3, [pc, #36] @ (800c534 ) 800c510: 681b ldr r3, [r3, #0] 800c512: 791a ldrb r2, [r3, #4] 800c514: 4b08 ldr r3, [pc, #32] @ (800c538 ) 800c516: 70da strb r2, [r3, #3] infoPacket.fw_version_major = FW_VERSION_MAJOR; 800c518: 4b07 ldr r3, [pc, #28] @ (800c538 ) 800c51a: 2201 movs r2, #1 800c51c: 809a strh r2, [r3, #4] infoPacket.fw_version_minor = FW_VERSION_MINOR; 800c51e: 4b06 ldr r3, [pc, #24] @ (800c538 ) 800c520: 2200 movs r2, #0 800c522: 80da strh r2, [r3, #6] infoPacket.fw_version_patch = FW_VERSION_PATCH; 800c524: 4b04 ldr r3, [pc, #16] @ (800c538 ) 800c526: 220f movs r2, #15 800c528: 811a strh r2, [r3, #8] } 800c52a: bf00 nop 800c52c: 46bd mov sp, r7 800c52e: bc80 pop {r7} 800c530: 4770 bx lr 800c532: bf00 nop 800c534: 20000000 .word 0x20000000 800c538: 20001088 .word 0x20001088 0800c53c : // Внешняя функция обработки команд (определена в serial_handler.c) extern void SC_CommandHandler(ReceivedCommand_t* cmd); void SC_Init() { 800c53c: b580 push {r7, lr} 800c53e: af00 add r7, sp, #0 // Обнуляем структуру memset(&serial_control, 0, sizeof(SerialControl_t)); 800c540: f44f 7204 mov.w r2, #528 @ 0x210 800c544: 2100 movs r1, #0 800c546: 480d ldr r0, [pc, #52] @ (800c57c ) 800c548: f007 ff5a bl 8014400 memset(&serial_iso, 0, sizeof(serial_iso)); 800c54c: f44f 7204 mov.w r2, #528 @ 0x210 800c550: 2100 movs r1, #0 800c552: 480b ldr r0, [pc, #44] @ (800c580 ) 800c554: f007 ff54 bl 8014400 sc_uart2_timed_out = 0; 800c558: 4b0a ldr r3, [pc, #40] @ (800c584 ) 800c55a: 2200 movs r2, #0 800c55c: 701a strb r2, [r3, #0] sc_uart2_last_packet_tick = HAL_GetTick(); 800c55e: f001 fbbb bl 800dcd8 800c562: 4603 mov r3, r0 800c564: 4a08 ldr r2, [pc, #32] @ (800c588 ) 800c566: 6013 str r3, [r2, #0] sc_uart2_last_reinit_tick = sc_uart2_last_packet_tick; 800c568: 4b07 ldr r3, [pc, #28] @ (800c588 ) 800c56a: 681b ldr r3, [r3, #0] 800c56c: 4a07 ldr r2, [pc, #28] @ (800c58c ) 800c56e: 6013 str r3, [r2, #0] sc_uart2_rx_during_tx = 0; 800c570: 4b07 ldr r3, [pc, #28] @ (800c590 ) 800c572: 2200 movs r2, #0 800c574: 701a strb r2, [r3, #0] } 800c576: bf00 nop 800c578: bd80 pop {r7, pc} 800c57a: bf00 nop 800c57c: 20000c00 .word 0x20000c00 800c580: 20000e10 .word 0x20000e10 800c584: 20001021 .word 0x20001021 800c588: 20001024 .word 0x20001024 800c58c: 20001028 .word 0x20001028 800c590: 2000102c .word 0x2000102c 0800c594 : void SC_Task() { 800c594: b580 push {r7, lr} 800c596: af00 add r7, sp, #0 SC_UART2_Watchdog(); 800c598: f000 f9e8 bl 800c96c // Запуск приема в режиме прерывания с ожиданием idle if ((huart2.RxState == HAL_UART_STATE_READY) && (serial_control.command_ready == 0)) { 800c59c: 4b3c ldr r3, [pc, #240] @ (800c690 ) 800c59e: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800c5a2: b2db uxtb r3, r3 800c5a4: 2b20 cmp r3, #32 800c5a6: d116 bne.n 800c5d6 800c5a8: 4b3a ldr r3, [pc, #232] @ (800c694 ) 800c5aa: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800c5ae: b2db uxtb r3, r3 800c5b0: 2b00 cmp r3, #0 800c5b2: d110 bne.n 800c5d6 if ((HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1) != HAL_OK) && 800c5b4: 22ff movs r2, #255 @ 0xff 800c5b6: 4938 ldr r1, [pc, #224] @ (800c698 ) 800c5b8: 4835 ldr r0, [pc, #212] @ (800c690 ) 800c5ba: f006 fad4 bl 8012b66 800c5be: 4603 mov r3, r0 800c5c0: 2b00 cmp r3, #0 800c5c2: d008 beq.n 800c5d6 (HAL_UART_GetError(&huart2) != HAL_UART_ERROR_NONE)) { 800c5c4: 4832 ldr r0, [pc, #200] @ (800c690 ) 800c5c6: f006 fee3 bl 8013390 800c5ca: 4603 mov r3, r0 if ((HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1) != HAL_OK) && 800c5cc: 2b00 cmp r3, #0 800c5ce: d002 beq.n 800c5d6 (void)HAL_UART_Abort_IT(&huart2); 800c5d0: 482f ldr r0, [pc, #188] @ (800c690 ) 800c5d2: f006 fb25 bl 8012c20 } } if (huart5.RxState == HAL_UART_STATE_READY) { 800c5d6: 4b31 ldr r3, [pc, #196] @ (800c69c ) 800c5d8: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800c5dc: b2db uxtb r3, r3 800c5de: 2b20 cmp r3, #32 800c5e0: d110 bne.n 800c604 if ((HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1) != HAL_OK) && 800c5e2: 22ff movs r2, #255 @ 0xff 800c5e4: 492e ldr r1, [pc, #184] @ (800c6a0 ) 800c5e6: 482d ldr r0, [pc, #180] @ (800c69c ) 800c5e8: f006 fabd bl 8012b66 800c5ec: 4603 mov r3, r0 800c5ee: 2b00 cmp r3, #0 800c5f0: d008 beq.n 800c604 (HAL_UART_GetError(&huart5) != HAL_UART_ERROR_NONE)) { 800c5f2: 482a ldr r0, [pc, #168] @ (800c69c ) 800c5f4: f006 fecc bl 8013390 800c5f8: 4603 mov r3, r0 if ((HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1) != HAL_OK) && 800c5fa: 2b00 cmp r3, #0 800c5fc: d002 beq.n 800c604 (void)HAL_UART_Abort_IT(&huart5); 800c5fe: 4827 ldr r0, [pc, #156] @ (800c69c ) 800c600: f006 fb0e bl 8012c20 } } // Проверка таймаута отправки пакета (больше 100 мс) if (huart2.gState == HAL_UART_STATE_BUSY_TX && serial_control.tx_tick != 0) { 800c604: 4b22 ldr r3, [pc, #136] @ (800c690 ) 800c606: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800c60a: b2db uxtb r3, r3 800c60c: 2b21 cmp r3, #33 @ 0x21 800c60e: d119 bne.n 800c644 800c610: 4b20 ldr r3, [pc, #128] @ (800c694 ) 800c612: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800c616: 2b00 cmp r3, #0 800c618: d014 beq.n 800c644 if ((HAL_GetTick() - serial_control.tx_tick) > 100) { 800c61a: f001 fb5d bl 800dcd8 800c61e: 4602 mov r2, r0 800c620: 4b1c ldr r3, [pc, #112] @ (800c694 ) 800c622: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800c626: 1ad3 subs r3, r2, r3 800c628: 2b64 cmp r3, #100 @ 0x64 800c62a: d90b bls.n 800c644 // Таймаут: принудительно сбрасываем передачу HAL_UART_Abort_IT(&huart2); 800c62c: 4818 ldr r0, [pc, #96] @ (800c690 ) 800c62e: f006 faf7 bl 8012c20 // Выключаем DIR при сбросе передачи HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800c632: 2200 movs r2, #0 800c634: 2110 movs r1, #16 800c636: 481b ldr r0, [pc, #108] @ (800c6a4 ) 800c638: f003 ffc9 bl 80105ce serial_control.tx_tick = 0; // Сбрасываем tick 800c63c: 4b15 ldr r3, [pc, #84] @ (800c694 ) 800c63e: 2200 movs r2, #0 800c640: f8c3 220c str.w r2, [r3, #524] @ 0x20c } } // Проверка наличия принятой команды для обработки if (serial_control.command_ready && (huart2.gState != HAL_UART_STATE_BUSY_TX)) { 800c644: 4b13 ldr r3, [pc, #76] @ (800c694 ) 800c646: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800c64a: b2db uxtb r3, r3 800c64c: 2b00 cmp r3, #0 800c64e: d01d beq.n 800c68c 800c650: 4b0f ldr r3, [pc, #60] @ (800c690 ) 800c652: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800c656: b2db uxtb r3, r3 800c658: 2b21 cmp r3, #33 @ 0x21 800c65a: d017 beq.n 800c68c // HAL_Delay(2); SC_CommandHandler(&serial_control.received_command); 800c65c: 4812 ldr r0, [pc, #72] @ (800c6a8 ) 800c65e: f000 fa25 bl 800caac if ((HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1) != HAL_OK) && 800c662: 22ff movs r2, #255 @ 0xff 800c664: 490c ldr r1, [pc, #48] @ (800c698 ) 800c666: 480a ldr r0, [pc, #40] @ (800c690 ) 800c668: f006 fa7d bl 8012b66 800c66c: 4603 mov r3, r0 800c66e: 2b00 cmp r3, #0 800c670: d008 beq.n 800c684 (HAL_UART_GetError(&huart2) != HAL_UART_ERROR_NONE)) { 800c672: 4807 ldr r0, [pc, #28] @ (800c690 ) 800c674: f006 fe8c bl 8013390 800c678: 4603 mov r3, r0 if ((HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1) != HAL_OK) && 800c67a: 2b00 cmp r3, #0 800c67c: d002 beq.n 800c684 (void)HAL_UART_Abort_IT(&huart2); 800c67e: 4804 ldr r0, [pc, #16] @ (800c690 ) 800c680: f006 face bl 8012c20 } serial_control.command_ready = 0; // Сбрасываем флаг 800c684: 4b03 ldr r3, [pc, #12] @ (800c694 ) 800c686: 2200 movs r2, #0 800c688: f883 2208 strb.w r2, [r3, #520] @ 0x208 } } 800c68c: bf00 nop 800c68e: bd80 pop {r7, pc} 800c690: 200011b8 .word 0x200011b8 800c694: 20000c00 .word 0x20000c00 800c698: 20000d00 .word 0x20000d00 800c69c: 20001128 .word 0x20001128 800c6a0: 20000f10 .word 0x20000f10 800c6a4: 40011400 .word 0x40011400 800c6a8: 20000e00 .word 0x20000e00 0800c6ac : ISR_FAST void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800c6ac: b570 push {r4, r5, r6, lr} if (huart->Instance == huart2.Instance) { 800c6ae: 4c28 ldr r4, [pc, #160] @ (800c750 ) 800c6b0: 6803 ldr r3, [r0, #0] 800c6b2: 6822 ldr r2, [r4, #0] ISR_FAST void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800c6b4: 460d mov r5, r1 if (huart->Instance == huart2.Instance) { 800c6b6: 4293 cmp r3, r2 800c6b8: d008 beq.n 800c6cc if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ SC_SendPacket(NULL, 0, RESP_INVALID); } g_sc_command_source = SC_SOURCE_UART2; HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); } else if (huart->Instance == huart5.Instance) { 800c6ba: 4a26 ldr r2, [pc, #152] @ (800c754 ) 800c6bc: 6812 ldr r2, [r2, #0] 800c6be: 4293 cmp r3, r2 800c6c0: d02c beq.n 800c71c if (process_received_packet(&serial_iso, serial_iso.rx_buffer, Size)) { g_sc_command_source = SC_SOURCE_UART5; SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); } HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1); } else if (huart->Instance == huart3.Instance) { 800c6c2: 4a25 ldr r2, [pc, #148] @ (800c758 ) 800c6c4: 6812 ldr r2, [r2, #0] 800c6c6: 4293 cmp r3, r2 800c6c8: d024 beq.n 800c714 CCS_RxEventCallback(huart, Size); } } 800c6ca: bd70 pop {r4, r5, r6, pc} if (huart2.gState == HAL_UART_STATE_BUSY_TX) { 800c6cc: f894 3041 ldrb.w r3, [r4, #65] @ 0x41 800c6d0: 2b21 cmp r3, #33 @ 0x21 800c6d2: d01b beq.n 800c70c sc_uart2_last_packet_tick = HAL_GetTick(); 800c6d4: f001 fb00 bl 800dcd8 sc_uart2_timed_out = 0; 800c6d8: 2200 movs r2, #0 800c6da: 4b20 ldr r3, [pc, #128] @ (800c75c ) if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800c6dc: 4920 ldr r1, [pc, #128] @ (800c760 ) sc_uart2_timed_out = 0; 800c6de: 701a strb r2, [r3, #0] sc_uart2_last_packet_tick = HAL_GetTick(); 800c6e0: 4603 mov r3, r0 800c6e2: 4e20 ldr r6, [pc, #128] @ (800c764 ) sc_uart2_last_reinit_tick = sc_uart2_last_packet_tick; 800c6e4: 4c20 ldr r4, [pc, #128] @ (800c768 ) if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800c6e6: f5a1 7080 sub.w r0, r1, #256 @ 0x100 800c6ea: 462a mov r2, r5 sc_uart2_last_packet_tick = HAL_GetTick(); 800c6ec: 6033 str r3, [r6, #0] sc_uart2_last_reinit_tick = sc_uart2_last_packet_tick; 800c6ee: 6023 str r3, [r4, #0] if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800c6f0: f000 f92e bl 800c950 800c6f4: 4601 mov r1, r0 800c6f6: b1f8 cbz r0, 800c738 g_sc_command_source = SC_SOURCE_UART2; 800c6f8: 2400 movs r4, #0 800c6fa: 4b1c ldr r3, [pc, #112] @ (800c76c ) HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c6fc: 22ff movs r2, #255 @ 0xff g_sc_command_source = SC_SOURCE_UART2; 800c6fe: 701c strb r4, [r3, #0] HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c700: 4917 ldr r1, [pc, #92] @ (800c760 ) 800c702: 4813 ldr r0, [pc, #76] @ (800c750 ) } 800c704: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c708: f006 ba2d b.w 8012b66 sc_uart2_rx_during_tx = 1u; 800c70c: 2201 movs r2, #1 800c70e: 4b18 ldr r3, [pc, #96] @ (800c770 ) 800c710: 701a strb r2, [r3, #0] 800c712: e7df b.n 800c6d4 } 800c714: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} CCS_RxEventCallback(huart, Size); 800c718: f7ff b934 b.w 800b984 if (process_received_packet(&serial_iso, serial_iso.rx_buffer, Size)) { 800c71c: 4915 ldr r1, [pc, #84] @ (800c774 ) 800c71e: 462a mov r2, r5 800c720: f5a1 7080 sub.w r0, r1, #256 @ 0x100 800c724: f000 f914 bl 800c950 800c728: b950 cbnz r0, 800c740 } 800c72a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c72e: 22ff movs r2, #255 @ 0xff 800c730: 4910 ldr r1, [pc, #64] @ (800c774 ) 800c732: 4808 ldr r0, [pc, #32] @ (800c754 ) 800c734: f006 ba17 b.w 8012b66 SC_SendPacket(NULL, 0, RESP_INVALID); 800c738: 2214 movs r2, #20 800c73a: f000 f8af bl 800c89c 800c73e: e7db b.n 800c6f8 g_sc_command_source = SC_SOURCE_UART5; 800c740: 2201 movs r2, #1 800c742: 4b0a ldr r3, [pc, #40] @ (800c76c ) SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); 800c744: 480c ldr r0, [pc, #48] @ (800c778 ) g_sc_command_source = SC_SOURCE_UART5; 800c746: 701a strb r2, [r3, #0] SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); 800c748: f000 f9b0 bl 800caac 800c74c: e7ed b.n 800c72a 800c74e: bf00 nop 800c750: 200011b8 .word 0x200011b8 800c754: 20001128 .word 0x20001128 800c758: 20001200 .word 0x20001200 800c75c: 20001021 .word 0x20001021 800c760: 20000d00 .word 0x20000d00 800c764: 20001024 .word 0x20001024 800c768: 20001028 .word 0x20001028 800c76c: 20001020 .word 0x20001020 800c770: 2000102c .word 0x2000102c 800c774: 20000f10 .word 0x20000f10 800c778: 20001010 .word 0x20001010 0800c77c : ISR_FAST void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 800c77c: b508 push {r3, lr} if (huart->Instance == huart2.Instance) { 800c77e: 4b08 ldr r3, [pc, #32] @ (800c7a0 ) 800c780: 6802 ldr r2, [r0, #0] 800c782: 681b ldr r3, [r3, #0] 800c784: 429a cmp r2, r3 800c786: d000 beq.n 800c78a HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); serial_control.tx_tick = 0; } } 800c788: bd08 pop {r3, pc} HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800c78a: 2200 movs r2, #0 800c78c: 2110 movs r1, #16 800c78e: 4805 ldr r0, [pc, #20] @ (800c7a4 ) 800c790: f003 ff1d bl 80105ce serial_control.tx_tick = 0; 800c794: 2200 movs r2, #0 800c796: 4b04 ldr r3, [pc, #16] @ (800c7a8 ) 800c798: f8c3 220c str.w r2, [r3, #524] @ 0x20c } 800c79c: bd08 pop {r3, pc} 800c79e: bf00 nop 800c7a0: 200011b8 .word 0x200011b8 800c7a4: 40011400 .word 0x40011400 800c7a8: 20000c00 .word 0x20000c00 0800c7ac : // Полностью программная реализация CRC-32 (полином CRC32_POLYNOMIAL, порядок little-endian) ISR_FAST static uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { uint32_t crc = 0xFFFFFFFFu; for (uint16_t i = 0; i < length; i++) { 800c7ac: b3c9 cbz r1, 800c822 uint32_t crc = 0xFFFFFFFFu; 800c7ae: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff ISR_FAST static uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { 800c7b2: b500 push {lr} crc ^= data[i]; for (uint8_t bit = 0; bit < 8; bit++) { if (crc & 0x1u) { 800c7b4: 4a1c ldr r2, [pc, #112] @ (800c828 ) 800c7b6: 4401 add r1, r0 crc ^= data[i]; 800c7b8: f810 eb01 ldrb.w lr, [r0], #1 800c7bc: ea8e 0e03 eor.w lr, lr, r3 if (crc & 0x1u) { 800c7c0: f34e 0300 sbfx r3, lr, #0, #1 800c7c4: f34e 0c40 sbfx ip, lr, #1, #1 800c7c8: 4013 ands r3, r2 800c7ca: ea83 035e eor.w r3, r3, lr, lsr #1 800c7ce: ea0c 0c02 and.w ip, ip, r2 800c7d2: ea8c 0c53 eor.w ip, ip, r3, lsr #1 800c7d6: f343 0340 sbfx r3, r3, #1, #1 800c7da: f34c 0e40 sbfx lr, ip, #1, #1 800c7de: 4013 ands r3, r2 800c7e0: ea83 035c eor.w r3, r3, ip, lsr #1 800c7e4: ea0e 0e02 and.w lr, lr, r2 800c7e8: ea8e 0e53 eor.w lr, lr, r3, lsr #1 800c7ec: f343 0340 sbfx r3, r3, #1, #1 800c7f0: f34e 0c40 sbfx ip, lr, #1, #1 800c7f4: 4013 ands r3, r2 800c7f6: ea83 035e eor.w r3, r3, lr, lsr #1 800c7fa: ea0c 0c02 and.w ip, ip, r2 800c7fe: ea8c 0c53 eor.w ip, ip, r3, lsr #1 800c802: f343 0340 sbfx r3, r3, #1, #1 800c806: 4013 ands r3, r2 800c808: f34c 0e40 sbfx lr, ip, #1, #1 800c80c: ea83 035c eor.w r3, r3, ip, lsr #1 for (uint16_t i = 0; i < length; i++) { 800c810: 4281 cmp r1, r0 if (crc & 0x1u) { 800c812: ea0e 0c02 and.w ip, lr, r2 800c816: ea8c 0353 eor.w r3, ip, r3, lsr #1 for (uint16_t i = 0; i < length; i++) { 800c81a: d1cd bne.n 800c7b8 crc >>= 1; } } } return crc ^ 0xFFFFFFFFu; 800c81c: 43d8 mvns r0, r3 } 800c81e: f85d fb04 ldr.w pc, [sp], #4 for (uint16_t i = 0; i < length; i++) { 800c822: 4608 mov r0, r1 } 800c824: 4770 bx lr 800c826: bf00 nop 800c828: edb88320 .word 0xedb88320 0800c82c : ISR_FAST static uint16_t encode_packet(const uint8_t* payload, uint16_t payload_len, uint8_t* output, uint8_t response_code) { 800c82c: b570 push {r4, r5, r6, lr} 800c82e: 4615 mov r5, r2 uint16_t out_index = 0; output[out_index++] = response_code; 800c830: 7013 strb r3, [r2, #0] if (payload != NULL) { 800c832: b360 cbz r0, 800c88e // Просто копируем полезную нагрузку без какого‑либо экранирования for (uint16_t i = 0; i < payload_len; i++) { 800c834: b359 cbz r1, 800c88e output[out_index++] = payload[i]; 800c836: 4694 mov ip, r2 800c838: 2302 movs r3, #2 800c83a: 7802 ldrb r2, [r0, #0] 800c83c: 1e4c subs r4, r1, #1 800c83e: b2a4 uxth r4, r4 800c840: 441c add r4, r3 800c842: f80c 2f01 strb.w r2, [ip, #1]! // Проверка переполнения if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800c846: e005 b.n 800c854 output[out_index++] = payload[i]; 800c848: f810 1f01 ldrb.w r1, [r0, #1]! if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800c84c: 2bfb cmp r3, #251 @ 0xfb output[out_index++] = payload[i]; 800c84e: f80c 1f01 strb.w r1, [ip, #1]! if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800c852: d020 beq.n 800c896 for (uint16_t i = 0; i < payload_len; i++) { 800c854: 42a3 cmp r3, r4 if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800c856: f103 0301 add.w r3, r3, #1 for (uint16_t i = 0; i < payload_len; i++) { 800c85a: d1f5 bne.n 800c848 800c85c: b2a1 uxth r1, r4 output[out_index++] = payload[i]; 800c85e: 1c4e adds r6, r1, #1 800c860: b2b6 uxth r6, r6 } } } // Вычисляем CRC для всего содержимого (код ответа + полезная нагрузка) uint32_t crc = calculate_crc32(output, out_index); 800c862: 4628 mov r0, r5 800c864: f7ff ffa2 bl 800c7ac 800c868: 4603 mov r3, r0 uint8_t* crc_bytes = (uint8_t*)&crc; // Добавляем CRC без экранирования for (int i = 0; i < 4; i++) { output[out_index++] = crc_bytes[i]; 800c86a: 1c71 adds r1, r6, #1 800c86c: 1cb2 adds r2, r6, #2 800c86e: 552b strb r3, [r5, r4] 800c870: f3c3 2c07 ubfx ip, r3, #8, #8 800c874: f3c3 4407 ubfx r4, r3, #16, #8 800c878: b289 uxth r1, r1 800c87a: b292 uxth r2, r2 800c87c: f3c3 6307 ubfx r3, r3, #24, #8 800c880: f805 c006 strb.w ip, [r5, r6] 800c884: 1cf0 adds r0, r6, #3 800c886: 546c strb r4, [r5, r1] 800c888: 54ab strb r3, [r5, r2] 800c88a: b280 uxth r0, r0 return 0; } } return out_index; } 800c88c: bd70 pop {r4, r5, r6, pc} for (uint16_t i = 0; i < payload_len; i++) { 800c88e: 2401 movs r4, #1 800c890: 2602 movs r6, #2 output[out_index++] = response_code; 800c892: 4621 mov r1, r4 800c894: e7e5 b.n 800c862 return 0; 800c896: 2000 movs r0, #0 } 800c898: bd70 pop {r4, r5, r6, pc} 800c89a: bf00 nop 0800c89c : ISR_FAST void SC_SendPacket(const uint8_t* payload, uint16_t payload_len, uint8_t response_code) { 800c89c: b538 push {r3, r4, r5, lr} 800c89e: 4613 mov r3, r2 uint16_t packet_len = encode_packet(payload, payload_len, serial_control.tx_buffer, response_code); 800c8a0: 4a13 ldr r2, [pc, #76] @ (800c8f0 ) 800c8a2: f7ff ffc3 bl 800c82c if (packet_len > 0) { 800c8a6: b1c8 cbz r0, 800c8dc if (huart2.gState == HAL_UART_STATE_BUSY_TX) { 800c8a8: 4604 mov r4, r0 800c8aa: 4812 ldr r0, [pc, #72] @ (800c8f4 ) 800c8ac: f890 3041 ldrb.w r3, [r0, #65] @ 0x41 800c8b0: 2b21 cmp r3, #33 @ 0x21 800c8b2: d014 beq.n 800c8de HAL_UART_Abort_IT(&huart2); HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); } HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_SET); 800c8b4: 2201 movs r2, #1 800c8b6: 2110 movs r1, #16 800c8b8: 480f ldr r0, [pc, #60] @ (800c8f8 ) 800c8ba: f003 fe88 bl 80105ce sc_uart2_rx_during_tx = 0u; 800c8be: f04f 0c00 mov.w ip, #0 HAL_UART_Transmit_IT(&huart2, serial_control.tx_buffer, packet_len); 800c8c2: 4d0b ldr r5, [pc, #44] @ (800c8f0 ) sc_uart2_rx_during_tx = 0u; 800c8c4: 4b0d ldr r3, [pc, #52] @ (800c8fc ) HAL_UART_Transmit_IT(&huart2, serial_control.tx_buffer, packet_len); 800c8c6: 4629 mov r1, r5 800c8c8: 4622 mov r2, r4 800c8ca: 480a ldr r0, [pc, #40] @ (800c8f4 ) sc_uart2_rx_during_tx = 0u; 800c8cc: f883 c000 strb.w ip, [r3] HAL_UART_Transmit_IT(&huart2, serial_control.tx_buffer, packet_len); 800c8d0: f006 f914 bl 8012afc serial_control.tx_tick = HAL_GetTick(); 800c8d4: f001 fa00 bl 800dcd8 800c8d8: f8c5 020c str.w r0, [r5, #524] @ 0x20c } } 800c8dc: bd38 pop {r3, r4, r5, pc} HAL_UART_Abort_IT(&huart2); 800c8de: f006 f99f bl 8012c20 HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800c8e2: 2200 movs r2, #0 800c8e4: 2110 movs r1, #16 800c8e6: 4804 ldr r0, [pc, #16] @ (800c8f8 ) 800c8e8: f003 fe71 bl 80105ce 800c8ec: e7e2 b.n 800c8b4 800c8ee: bf00 nop 800c8f0: 20000c00 .word 0x20000c00 800c8f4: 200011b8 .word 0x200011b8 800c8f8: 40011400 .word 0x40011400 800c8fc: 2000102c .word 0x2000102c 0800c900 : ISR_FAST static uint8_t parse_packet(const uint8_t* packet_data, uint16_t packet_len, ReceivedCommand_t* out_cmd) { 800c900: e92d 4178 stmdb sp!, {r3, r4, r5, r6, r8, lr} // }else{ // test_crc_invalid = 5; // } // Минимальный размер: 1 байт команды + 4 байта CRC if (packet_len < 5) return 0; 800c904: 1f4b subs r3, r1, #5 800c906: 2bfb cmp r3, #251 @ 0xfb 800c908: d813 bhi.n 800c932 if (packet_len > MAX_RX_BUFFER_SIZE) return 0; uint16_t payload_length = packet_len - 4; 800c90a: 3904 subs r1, #4 800c90c: b28c uxth r4, r1 // Извлекаем принятую CRC (последние 4 байта, little-endian) uint32_t received_checksum = ((uint32_t)packet_data[payload_length] << 0) | ((uint32_t)packet_data[payload_length + 1] << 8) | 800c90e: 1903 adds r3, r0, r4 ((uint32_t)packet_data[payload_length + 2] << 16) | 800c910: 789d ldrb r5, [r3, #2] 800c912: 4690 mov r8, r2 ((uint32_t)packet_data[payload_length + 1] << 8) | 800c914: 785a ldrb r2, [r3, #1] ((uint32_t)packet_data[payload_length + 2] << 16) | 800c916: 042d lsls r5, r5, #16 ((uint32_t)packet_data[payload_length + 1] << 8) | 800c918: ea45 2502 orr.w r5, r5, r2, lsl #8 ((uint32_t)packet_data[payload_length] << 0) | 800c91c: 5d02 ldrb r2, [r0, r4] ((uint32_t)packet_data[payload_length + 3] << 24); 800c91e: 78db ldrb r3, [r3, #3] ((uint32_t)packet_data[payload_length + 1] << 8) | 800c920: 4315 orrs r5, r2 // Вычисляем CRC для полезной нагрузки uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); 800c922: 4621 mov r1, r4 uint32_t received_checksum = 800c924: ea45 6503 orr.w r5, r5, r3, lsl #24 uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); 800c928: 4606 mov r6, r0 800c92a: f7ff ff3f bl 800c7ac if (received_checksum != calculated_checksum) return 0; // CRC не совпадает 800c92e: 4285 cmp r5, r0 800c930: d002 beq.n 800c938 if (packet_len < 5) return 0; 800c932: 2000 movs r0, #0 out_cmd->argument = (void *)&packet_data[1]; out_cmd->command = packet_data[0]; out_cmd->argument_length = (uint8_t)(payload_length - 1); return 1; } 800c934: e8bd 8178 ldmia.w sp!, {r3, r4, r5, r6, r8, pc} out_cmd->argument = (void *)&packet_data[1]; 800c938: 1c73 adds r3, r6, #1 800c93a: f8c8 3004 str.w r3, [r8, #4] out_cmd->command = packet_data[0]; 800c93e: 7833 ldrb r3, [r6, #0] out_cmd->argument_length = (uint8_t)(payload_length - 1); 800c940: 3c01 subs r4, #1 out_cmd->command = packet_data[0]; 800c942: f888 3000 strb.w r3, [r8] out_cmd->argument_length = (uint8_t)(payload_length - 1); 800c946: f888 4001 strb.w r4, [r8, #1] return 1; 800c94a: 2001 movs r0, #1 } 800c94c: e8bd 8178 ldmia.w sp!, {r3, r4, r5, r6, r8, pc} 0800c950 : ISR_FAST static uint8_t process_received_packet(SerialControl_t *ctx, const uint8_t* packet_data, uint16_t packet_len) { 800c950: b510 push {r4, lr} 800c952: 4604 mov r4, r0 if (!parse_packet(packet_data, packet_len, (ReceivedCommand_t *)&ctx->received_command)) { 800c954: 4608 mov r0, r1 800c956: 4611 mov r1, r2 800c958: f504 7200 add.w r2, r4, #512 @ 0x200 800c95c: f7ff ffd0 bl 800c900 800c960: b118 cbz r0, 800c96a return 0; } ctx->command_ready = 1; 800c962: 2301 movs r3, #1 return 1; 800c964: 4618 mov r0, r3 ctx->command_ready = 1; 800c966: f884 3208 strb.w r3, [r4, #520] @ 0x208 } 800c96a: bd10 pop {r4, pc} 0800c96c : static void SC_UART2_Watchdog(void) { 800c96c: b580 push {r7, lr} 800c96e: b082 sub sp, #8 800c970: af00 add r7, sp, #0 const uint32_t now = HAL_GetTick(); 800c972: f001 f9b1 bl 800dcd8 800c976: 6078 str r0, [r7, #4] const uint32_t since_last_packet = now - sc_uart2_last_packet_tick; 800c978: 4b37 ldr r3, [pc, #220] @ (800ca58 ) 800c97a: 681b ldr r3, [r3, #0] 800c97c: 687a ldr r2, [r7, #4] 800c97e: 1ad3 subs r3, r2, r3 800c980: 603b str r3, [r7, #0] if ((huart2.gState == HAL_UART_STATE_BUSY_TX) && (sc_uart2_rx_during_tx != 0u)) { 800c982: 4b36 ldr r3, [pc, #216] @ (800ca5c ) 800c984: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800c988: b2db uxtb r3, r3 800c98a: 2b21 cmp r3, #33 @ 0x21 800c98c: d126 bne.n 800c9dc 800c98e: 4b34 ldr r3, [pc, #208] @ (800ca60 ) 800c990: 781b ldrb r3, [r3, #0] 800c992: b2db uxtb r3, r3 800c994: 2b00 cmp r3, #0 800c996: d021 beq.n 800c9dc HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800c998: 2200 movs r2, #0 800c99a: 2110 movs r1, #16 800c99c: 4831 ldr r0, [pc, #196] @ (800ca64 ) 800c99e: f003 fe16 bl 80105ce (void)HAL_UART_Abort_IT(&huart2); 800c9a2: 482e ldr r0, [pc, #184] @ (800ca5c ) 800c9a4: f006 f93c bl 8012c20 (void)HAL_UART_DeInit(&huart2); 800c9a8: 482c ldr r0, [pc, #176] @ (800ca5c ) 800c9aa: f006 f875 bl 8012a98 (void)HAL_UART_Init(&huart2); 800c9ae: 482b ldr r0, [pc, #172] @ (800ca5c ) 800c9b0: f006 f822 bl 80129f8 (void)HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c9b4: 22ff movs r2, #255 @ 0xff 800c9b6: 492c ldr r1, [pc, #176] @ (800ca68 ) 800c9b8: 4828 ldr r0, [pc, #160] @ (800ca5c ) 800c9ba: f006 f8d4 bl 8012b66 serial_control.tx_tick = 0; 800c9be: 4b2b ldr r3, [pc, #172] @ (800ca6c ) 800c9c0: 2200 movs r2, #0 800c9c2: f8c3 220c str.w r2, [r3, #524] @ 0x20c sc_uart2_rx_during_tx = 0u; 800c9c6: 4b26 ldr r3, [pc, #152] @ (800ca60 ) 800c9c8: 2200 movs r2, #0 800c9ca: 701a strb r2, [r3, #0] sc_uart2_last_reinit_tick = now; 800c9cc: 4a28 ldr r2, [pc, #160] @ (800ca70 ) 800c9ce: 687b ldr r3, [r7, #4] 800c9d0: 6013 str r3, [r2, #0] log_printf(LOG_ERR, "USART2 BUSY_TX: hard reinit\n"); 800c9d2: 4928 ldr r1, [pc, #160] @ (800ca74 ) 800c9d4: 2004 movs r0, #4 800c9d6: f7fd fd19 bl 800a40c return; 800c9da: e039 b.n 800ca50 } if (since_last_packet >= SC_UART2_PACKET_TIMEOUT_MS) { 800c9dc: 683b ldr r3, [r7, #0] 800c9de: f241 3287 movw r2, #4999 @ 0x1387 800c9e2: 4293 cmp r3, r2 800c9e4: d90c bls.n 800ca00 if (sc_uart2_timed_out == 0u) { 800c9e6: 4b24 ldr r3, [pc, #144] @ (800ca78 ) 800c9e8: 781b ldrb r3, [r3, #0] 800c9ea: b2db uxtb r3, r3 800c9ec: 2b00 cmp r3, #0 800c9ee: d103 bne.n 800c9f8 serial_control.command_ready = 0; 800c9f0: 4b1e ldr r3, [pc, #120] @ (800ca6c ) 800c9f2: 2200 movs r2, #0 800c9f4: f883 2208 strb.w r2, [r3, #520] @ 0x208 } sc_uart2_timed_out = 1; 800c9f8: 4b1f ldr r3, [pc, #124] @ (800ca78 ) 800c9fa: 2201 movs r2, #1 800c9fc: 701a strb r2, [r3, #0] 800c9fe: e002 b.n 800ca06 } else { sc_uart2_timed_out = 0; 800ca00: 4b1d ldr r3, [pc, #116] @ (800ca78 ) 800ca02: 2200 movs r2, #0 800ca04: 701a strb r2, [r3, #0] } if ((since_last_packet >= SC_UART2_REINIT_TIMEOUT_MS) && 800ca06: 683b ldr r3, [r7, #0] 800ca08: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800ca0c: d320 bcc.n 800ca50 ((now - sc_uart2_last_reinit_tick) >= SC_UART2_REINIT_TIMEOUT_MS)) { 800ca0e: 4b18 ldr r3, [pc, #96] @ (800ca70 ) 800ca10: 681b ldr r3, [r3, #0] 800ca12: 687a ldr r2, [r7, #4] 800ca14: 1ad3 subs r3, r2, r3 if ((since_last_packet >= SC_UART2_REINIT_TIMEOUT_MS) && 800ca16: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800ca1a: d319 bcc.n 800ca50 HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800ca1c: 2200 movs r2, #0 800ca1e: 2110 movs r1, #16 800ca20: 4810 ldr r0, [pc, #64] @ (800ca64 ) 800ca22: f003 fdd4 bl 80105ce (void)HAL_UART_Abort_IT(&huart2); 800ca26: 480d ldr r0, [pc, #52] @ (800ca5c ) 800ca28: f006 f8fa bl 8012c20 (void)HAL_UART_DeInit(&huart2); 800ca2c: 480b ldr r0, [pc, #44] @ (800ca5c ) 800ca2e: f006 f833 bl 8012a98 (void)HAL_UART_Init(&huart2); 800ca32: 480a ldr r0, [pc, #40] @ (800ca5c ) 800ca34: f005 ffe0 bl 80129f8 (void)HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800ca38: 22ff movs r2, #255 @ 0xff 800ca3a: 490b ldr r1, [pc, #44] @ (800ca68 ) 800ca3c: 4807 ldr r0, [pc, #28] @ (800ca5c ) 800ca3e: f006 f892 bl 8012b66 sc_uart2_last_reinit_tick = now; 800ca42: 4a0b ldr r2, [pc, #44] @ (800ca70 ) 800ca44: 687b ldr r3, [r7, #4] 800ca46: 6013 str r3, [r2, #0] log_printf(LOG_ERR, "USART2 stalled: hard reinit\n"); 800ca48: 490c ldr r1, [pc, #48] @ (800ca7c ) 800ca4a: 2004 movs r0, #4 800ca4c: f7fd fcde bl 800a40c } } 800ca50: 3708 adds r7, #8 800ca52: 46bd mov sp, r7 800ca54: bd80 pop {r7, pc} 800ca56: bf00 nop 800ca58: 20001024 .word 0x20001024 800ca5c: 200011b8 .word 0x200011b8 800ca60: 2000102c .word 0x2000102c 800ca64: 40011400 .word 0x40011400 800ca68: 20000d00 .word 0x20000d00 800ca6c: 20000c00 .word 0x20000c00 800ca70: 20001028 .word 0x20001028 800ca74: 08016df4 .word 0x08016df4 800ca78: 20001021 .word 0x20001021 800ca7c: 08016e14 .word 0x08016e14 0800ca80 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 800ca80: b480 push {r7} 800ca82: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 800ca84: f3bf 8f4f dsb sy } 800ca88: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800ca8a: 4b06 ldr r3, [pc, #24] @ (800caa4 <__NVIC_SystemReset+0x24>) 800ca8c: 68db ldr r3, [r3, #12] 800ca8e: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800ca92: 4904 ldr r1, [pc, #16] @ (800caa4 <__NVIC_SystemReset+0x24>) 800ca94: 4b04 ldr r3, [pc, #16] @ (800caa8 <__NVIC_SystemReset+0x28>) 800ca96: 4313 orrs r3, r2 800ca98: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800ca9a: f3bf 8f4f dsb sy } 800ca9e: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 800caa0: bf00 nop 800caa2: e7fd b.n 800caa0 <__NVIC_SystemReset+0x20> 800caa4: e000ed00 .word 0xe000ed00 800caa8: 05fa0004 .word 0x05fa0004 0800caac : .chargerNumber = 00001, .unixTime = 1721651966, }; // Единая функция-обработчик всех команд со switch-case void SC_CommandHandler(ReceivedCommand_t* cmd) { 800caac: b580 push {r7, lr} 800caae: b084 sub sp, #16 800cab0: af00 add r7, sp, #0 800cab2: 6078 str r0, [r7, #4] uint8_t response_code = RESP_FAILED; 800cab4: 2313 movs r3, #19 800cab6: 73fb strb r3, [r7, #15] switch (cmd->command) { 800cab8: 687b ldr r3, [r7, #4] 800caba: 781b ldrb r3, [r3, #0] 800cabc: 2bc2 cmp r3, #194 @ 0xc2 800cabe: f300 80cc bgt.w 800cc5a 800cac2: 2bb0 cmp r3, #176 @ 0xb0 800cac4: da0f bge.n 800cae6 800cac6: 2b60 cmp r3, #96 @ 0x60 800cac8: d042 beq.n 800cb50 800caca: 2b60 cmp r3, #96 @ 0x60 800cacc: f300 80c5 bgt.w 800cc5a 800cad0: 2b50 cmp r3, #80 @ 0x50 800cad2: d043 beq.n 800cb5c 800cad4: 2b50 cmp r3, #80 @ 0x50 800cad6: f300 80c0 bgt.w 800cc5a 800cada: 2b01 cmp r3, #1 800cadc: f000 80a6 beq.w 800cc2c 800cae0: 2b40 cmp r3, #64 @ 0x40 800cae2: d02d beq.n 800cb40 800cae4: e0b9 b.n 800cc5a 800cae6: 3bb0 subs r3, #176 @ 0xb0 800cae8: 2b12 cmp r3, #18 800caea: f200 80b6 bhi.w 800cc5a 800caee: a201 add r2, pc, #4 @ (adr r2, 800caf4 ) 800caf0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800caf4: 0800cb63 .word 0x0800cb63 800caf8: 0800cc5b .word 0x0800cc5b 800cafc: 0800cc5b .word 0x0800cc5b 800cb00: 0800cc5b .word 0x0800cc5b 800cb04: 0800cc5b .word 0x0800cc5b 800cb08: 0800cc0b .word 0x0800cc0b 800cb0c: 0800cc5b .word 0x0800cc5b 800cb10: 0800cc5b .word 0x0800cc5b 800cb14: 0800cc5b .word 0x0800cc5b 800cb18: 0800cc5b .word 0x0800cc5b 800cb1c: 0800cc5b .word 0x0800cc5b 800cb20: 0800cc5b .word 0x0800cc5b 800cb24: 0800cc5b .word 0x0800cc5b 800cb28: 0800cc5b .word 0x0800cc5b 800cb2c: 0800cc5b .word 0x0800cc5b 800cb30: 0800cc5b .word 0x0800cc5b 800cb34: 0800cba1 .word 0x0800cba1 800cb38: 0800cc05 .word 0x0800cc05 800cb3c: 0800cbd9 .word 0x0800cbd9 // Команды БЕЗ аргументов case CMD_GET_STATUS: // Логика получения информации monitoring_data_callback(); 800cb40: f000 f8b2 bl 800cca8 // Отправляем с нормальным приоритетом SC_SendPacket((uint8_t*)&statusPacket, sizeof(statusPacket), CMD_GET_STATUS); 800cb44: 2240 movs r2, #64 @ 0x40 800cb46: 2158 movs r1, #88 @ 0x58 800cb48: 484b ldr r0, [pc, #300] @ (800cc78 ) 800cb4a: f7ff fea7 bl 800c89c return; // Специальный ответ уже отправлен 800cb4e: e08f b.n 800cc70 case CMD_GET_INFO: SC_SendPacket((uint8_t*)&infoPacket, sizeof(infoPacket), CMD_GET_INFO); 800cb50: 2260 movs r2, #96 @ 0x60 800cb52: 210a movs r1, #10 800cb54: 4849 ldr r0, [pc, #292] @ (800cc7c ) 800cb56: f7ff fea1 bl 800c89c return; 800cb5a: e089 b.n 800cc70 case CMD_GET_LOG: debug_buffer_send(); 800cb5c: f7fd fbf4 bl 800a348 return; // Ответ формируется внутри debug_buffer_send 800cb60: e086 b.n 800cc70 // Команды С аргументами case CMD_SET_CONFIG: if (cmd->argument_length == sizeof(ConfigBlock_t)) { 800cb62: 687b ldr r3, [r7, #4] 800cb64: 785b ldrb r3, [r3, #1] 800cb66: 2b0b cmp r3, #11 800cb68: d117 bne.n 800cb9a memcpy(&config, cmd->argument, sizeof(ConfigBlock_t)); 800cb6a: 687b ldr r3, [r7, #4] 800cb6c: 685a ldr r2, [r3, #4] 800cb6e: 4b44 ldr r3, [pc, #272] @ (800cc80 ) 800cb70: 6810 ldr r0, [r2, #0] 800cb72: 6851 ldr r1, [r2, #4] 800cb74: c303 stmia r3!, {r0, r1} 800cb76: 8911 ldrh r1, [r2, #8] 800cb78: 7a92 ldrb r2, [r2, #10] 800cb7a: 8019 strh r1, [r3, #0] 800cb7c: 709a strb r2, [r3, #2] config_initialized = 1; 800cb7e: 4b41 ldr r3, [pc, #260] @ (800cc84 ) 800cb80: 2201 movs r2, #1 800cb82: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Set Config: %s %d\n", config.location, config.chargerNumber); 800cb84: 4b3e ldr r3, [pc, #248] @ (800cc80 ) 800cb86: f8d3 3003 ldr.w r3, [r3, #3] 800cb8a: 4a3d ldr r2, [pc, #244] @ (800cc80 ) 800cb8c: 493e ldr r1, [pc, #248] @ (800cc88 ) 800cb8e: 2007 movs r0, #7 800cb90: f7fd fc3c bl 800a40c response_code = RESP_SUCCESS; 800cb94: 2312 movs r3, #18 800cb96: 73fb strb r3, [r7, #15] break; 800cb98: e062 b.n 800cc60 } response_code = RESP_FAILED; 800cb9a: 2313 movs r3, #19 800cb9c: 73fb strb r3, [r7, #15] break; 800cb9e: e05f b.n 800cc60 case CMD_SET_POWER_LIMIT: if (cmd->argument_length == 1) { 800cba0: 687b ldr r3, [r7, #4] 800cba2: 785b ldrb r3, [r3, #1] 800cba4: 2b01 cmp r3, #1 800cba6: d114 bne.n 800cbd2 PSU0.power_limit = ((uint8_t*)cmd->argument)[0] * 1000; 800cba8: 687b ldr r3, [r7, #4] 800cbaa: 685b ldr r3, [r3, #4] 800cbac: 781b ldrb r3, [r3, #0] 800cbae: 461a mov r2, r3 800cbb0: f44f 737a mov.w r3, #1000 @ 0x3e8 800cbb4: fb02 f303 mul.w r3, r2, r3 800cbb8: 461a mov r2, r3 800cbba: 4b34 ldr r3, [pc, #208] @ (800cc8c ) 800cbbc: 615a str r2, [r3, #20] log_printf(LOG_INFO, "Power limit: %d\n", PSU0.power_limit); 800cbbe: 4b33 ldr r3, [pc, #204] @ (800cc8c ) 800cbc0: 695b ldr r3, [r3, #20] 800cbc2: 461a mov r2, r3 800cbc4: 4932 ldr r1, [pc, #200] @ (800cc90 ) 800cbc6: 2007 movs r0, #7 800cbc8: f7fd fc20 bl 800a40c //CONN.connState = (((uint8_t*)cmd->argument)[0])/4; response_code = RESP_SUCCESS; 800cbcc: 2312 movs r3, #18 800cbce: 73fb strb r3, [r7, #15] break; 800cbd0: e046 b.n 800cc60 } response_code = RESP_FAILED; 800cbd2: 2313 movs r3, #19 800cbd4: 73fb strb r3, [r7, #15] break; 800cbd6: e043 b.n 800cc60 case CMD_CHARGE_PERMIT: if (cmd->argument_length == 1) { 800cbd8: 687b ldr r3, [r7, #4] 800cbda: 785b ldrb r3, [r3, #1] 800cbdc: 2b01 cmp r3, #1 800cbde: d10e bne.n 800cbfe CONN.connControl = ((uint8_t*)cmd->argument)[0]; 800cbe0: 687b ldr r3, [r7, #4] 800cbe2: 685b ldr r3, [r3, #4] 800cbe4: 781a ldrb r2, [r3, #0] 800cbe6: 4b2b ldr r3, [pc, #172] @ (800cc94 ) 800cbe8: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Charge permit: %d\n", CONN.connControl); 800cbea: 4b2a ldr r3, [pc, #168] @ (800cc94 ) 800cbec: 781b ldrb r3, [r3, #0] 800cbee: 461a mov r2, r3 800cbf0: 4929 ldr r1, [pc, #164] @ (800cc98 ) 800cbf2: 2007 movs r0, #7 800cbf4: f7fd fc0a bl 800a40c response_code = RESP_SUCCESS; 800cbf8: 2312 movs r3, #18 800cbfa: 73fb strb r3, [r7, #15] break; 800cbfc: e030 b.n 800cc60 } response_code = RESP_FAILED; 800cbfe: 2313 movs r3, #19 800cc00: 73fb strb r3, [r7, #15] break; 800cc02: e02d b.n 800cc60 // memcpy(&PSU_TestMode, cmd->argument, sizeof(PSU_TestMode_t)); // log_printf(LOG_INFO, "Test PSU: %d %d %d\n", PSU_TestMode.enable, PSU_TestMode.voltage, PSU_TestMode.current); // response_code = RESP_SUCCESS; // break; // } response_code = RESP_FAILED; 800cc04: 2313 movs r3, #19 800cc06: 73fb strb r3, [r7, #15] break; 800cc08: e02a b.n 800cc60 case CMD_DEVICE_RESET: // 2. Отправляем SUCCESS (хост может успеть получить его перед ребутом) SC_SendPacket(NULL, 0, RESP_SUCCESS); 800cc0a: 2212 movs r2, #18 800cc0c: 2100 movs r1, #0 800cc0e: 2000 movs r0, #0 800cc10: f7ff fe44 bl 800c89c while(huart2.gState == HAL_UART_STATE_BUSY_TX); // Ожидание завершения передачи 800cc14: bf00 nop 800cc16: 4b21 ldr r3, [pc, #132] @ (800cc9c ) 800cc18: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800cc1c: b2db uxtb r3, r3 800cc1e: 2b21 cmp r3, #33 @ 0x21 800cc20: d0f9 beq.n 800cc16 HAL_Delay(10); 800cc22: 200a movs r0, #10 800cc24: f001 f862 bl 800dcec // 3. Выполняем программный сброс NVIC_SystemReset(); 800cc28: f7ff ff2a bl 800ca80 <__NVIC_SystemReset> return; // Сюда код уже не дойдет, но для компилятора нxужно case CMD_ISOLATION_STATUS: if (cmd->argument_length == sizeof(IsolationStatusPacket_t)) { 800cc2c: 687b ldr r3, [r7, #4] 800cc2e: 785b ldrb r3, [r3, #1] 800cc30: 2b09 cmp r3, #9 800cc32: d10f bne.n 800cc54 memcpy(&ISO, cmd->argument, sizeof(IsolationStatusPacket_t)); 800cc34: 687b ldr r3, [r7, #4] 800cc36: 685a ldr r2, [r3, #4] 800cc38: 4b19 ldr r3, [pc, #100] @ (800cca0 ) 800cc3a: 6810 ldr r0, [r2, #0] 800cc3c: 6851 ldr r1, [r2, #4] 800cc3e: c303 stmia r3!, {r0, r1} 800cc40: 7a12 ldrb r2, [r2, #8] 800cc42: 701a strb r2, [r3, #0] // Для однонаправленного UART5 ответ не нужен if (g_sc_command_source == SC_SOURCE_UART5) { 800cc44: 4b17 ldr r3, [pc, #92] @ (800cca4 ) 800cc46: 781b ldrb r3, [r3, #0] 800cc48: b2db uxtb r3, r3 800cc4a: 2b01 cmp r3, #1 800cc4c: d00f beq.n 800cc6e return; } response_code = RESP_SUCCESS; 800cc4e: 2312 movs r3, #18 800cc50: 73fb strb r3, [r7, #15] break; 800cc52: e005 b.n 800cc60 } response_code = RESP_FAILED; 800cc54: 2313 movs r3, #19 800cc56: 73fb strb r3, [r7, #15] break; 800cc58: e002 b.n 800cc60 default: // Неизвестная команда response_code = RESP_FAILED; 800cc5a: 2313 movs r3, #19 800cc5c: 73fb strb r3, [r7, #15] break; 800cc5e: bf00 nop } // Отправляем финальный ответ (для команд без собственного ответа) SC_SendPacket(NULL, 0, response_code); 800cc60: 7bfb ldrb r3, [r7, #15] 800cc62: 461a mov r2, r3 800cc64: 2100 movs r1, #0 800cc66: 2000 movs r0, #0 800cc68: f7ff fe18 bl 800c89c 800cc6c: e000 b.n 800cc70 return; 800cc6e: bf00 nop } 800cc70: 3710 adds r7, #16 800cc72: 46bd mov sp, r7 800cc74: bd80 pop {r7, pc} 800cc76: bf00 nop 800cc78: 20001030 .word 0x20001030 800cc7c: 20001088 .word 0x20001088 800cc80: 20000060 .word 0x20000060 800cc84: 20001092 .word 0x20001092 800cc88: 08016e34 .word 0x08016e34 800cc8c: 200008e4 .word 0x200008e4 800cc90: 08016e48 .word 0x08016e48 800cc94: 20000398 .word 0x20000398 800cc98: 08016e5c .word 0x08016e5c 800cc9c: 200011b8 .word 0x200011b8 800cca0: 20000054 .word 0x20000054 800cca4: 20001020 .word 0x20001020 0800cca8 : // Колбэк для заполнения данных мониторинга void monitoring_data_callback() { 800cca8: b580 push {r7, lr} 800ccaa: af00 add r7, sp, #0 // Информация о зарядной сессии statusPacket.SOC = CONN.SOC; 800ccac: 4b8f ldr r3, [pc, #572] @ (800ceec ) 800ccae: 789a ldrb r2, [r3, #2] 800ccb0: 4b8f ldr r3, [pc, #572] @ (800cef0 ) 800ccb2: 709a strb r2, [r3, #2] statusPacket.Energy = CONN.Energy; 800ccb4: 4b8d ldr r3, [pc, #564] @ (800ceec ) 800ccb6: f8d3 3007 ldr.w r3, [r3, #7] 800ccba: 4a8d ldr r2, [pc, #564] @ (800cef0 ) 800ccbc: f8c2 3003 str.w r3, [r2, #3] statusPacket.RequestedVoltage = CONN.RequestedVoltage; 800ccc0: 4b8a ldr r3, [pc, #552] @ (800ceec ) 800ccc2: f8b3 300f ldrh.w r3, [r3, #15] 800ccc6: b29a uxth r2, r3 800ccc8: 4b89 ldr r3, [pc, #548] @ (800cef0 ) 800ccca: f8a3 2007 strh.w r2, [r3, #7] statusPacket.RequestedCurrent = CONN.WantedCurrent; 800ccce: 4b87 ldr r3, [pc, #540] @ (800ceec ) 800ccd0: f8b3 301b ldrh.w r3, [r3, #27] 800ccd4: b29a uxth r2, r3 800ccd6: 4b86 ldr r3, [pc, #536] @ (800cef0 ) 800ccd8: f8a3 2009 strh.w r2, [r3, #9] statusPacket.MeasuredVoltage = CONN.MeasuredVoltage; 800ccdc: 4b83 ldr r3, [pc, #524] @ (800ceec ) 800ccde: f8b3 3013 ldrh.w r3, [r3, #19] 800cce2: b29a uxth r2, r3 800cce4: 4b82 ldr r3, [pc, #520] @ (800cef0 ) 800cce6: f8a3 200b strh.w r2, [r3, #11] statusPacket.MeasuredCurrent = CONN.MeasuredCurrent; 800ccea: 4b80 ldr r3, [pc, #512] @ (800ceec ) 800ccec: f8b3 3015 ldrh.w r3, [r3, #21] 800ccf0: b29a uxth r2, r3 800ccf2: 4b7f ldr r3, [pc, #508] @ (800cef0 ) 800ccf4: f8a3 200d strh.w r2, [r3, #13] statusPacket.outputEnabled = CONN.outputEnabled; 800ccf8: 4b7c ldr r3, [pc, #496] @ (800ceec ) 800ccfa: 7e1a ldrb r2, [r3, #24] 800ccfc: 4b7c ldr r3, [pc, #496] @ (800cef0 ) 800ccfe: 73da strb r2, [r3, #15] statusPacket.chargingError = CONN.chargingError; 800cd00: 4b7a ldr r3, [pc, #488] @ (800ceec ) 800cd02: 7f5a ldrb r2, [r3, #29] 800cd04: 4b7a ldr r3, [pc, #488] @ (800cef0 ) 800cd06: 705a strb r2, [r3, #1] statusPacket.connState = CONN.connState; 800cd08: 4b78 ldr r3, [pc, #480] @ (800ceec ) 800cd0a: 785a ldrb r2, [r3, #1] 800cd0c: 4b78 ldr r3, [pc, #480] @ (800cef0 ) 800cd0e: 701a strb r2, [r3, #0] statusPacket.chargingElapsedTimeMin = 0; 800cd10: 4b77 ldr r3, [pc, #476] @ (800cef0 ) 800cd12: 2200 movs r2, #0 800cd14: 741a strb r2, [r3, #16] 800cd16: 2200 movs r2, #0 800cd18: 745a strb r2, [r3, #17] statusPacket.chargingElapsedTimeSec = 0; 800cd1a: 4b75 ldr r3, [pc, #468] @ (800cef0 ) 800cd1c: 2200 movs r2, #0 800cd1e: 749a strb r2, [r3, #18] statusPacket.estimatedRemainingChargingTime = 0; 800cd20: 4b73 ldr r3, [pc, #460] @ (800cef0 ) 800cd22: 2200 movs r2, #0 800cd24: 74da strb r2, [r3, #19] 800cd26: 2200 movs r2, #0 800cd28: 751a strb r2, [r3, #20] // состояние зарядной станции statusPacket.relayAC = RELAY_Read(RELAY_AC); 800cd2a: 2004 movs r0, #4 800cd2c: f7fc fdb4 bl 8009898 800cd30: 4603 mov r3, r0 800cd32: f003 0301 and.w r3, r3, #1 800cd36: b2d9 uxtb r1, r3 800cd38: 4a6d ldr r2, [pc, #436] @ (800cef0 ) 800cd3a: 7d53 ldrb r3, [r2, #21] 800cd3c: f361 0300 bfi r3, r1, #0, #1 800cd40: 7553 strb r3, [r2, #21] statusPacket.relayDC = RELAY_Read(RELAY_DC); 800cd42: 2003 movs r0, #3 800cd44: f7fc fda8 bl 8009898 800cd48: 4603 mov r3, r0 800cd4a: f003 0301 and.w r3, r3, #1 800cd4e: b2d9 uxtb r1, r3 800cd50: 4a67 ldr r2, [pc, #412] @ (800cef0 ) 800cd52: 7d53 ldrb r3, [r2, #21] 800cd54: f361 0341 bfi r3, r1, #1, #1 800cd58: 7553 strb r3, [r2, #21] statusPacket.relayAUX = RELAY_Read(RELAY_AUX0); 800cd5a: 2000 movs r0, #0 800cd5c: f7fc fd9c bl 8009898 800cd60: 4603 mov r3, r0 800cd62: f003 0301 and.w r3, r3, #1 800cd66: b2d9 uxtb r1, r3 800cd68: 4a61 ldr r2, [pc, #388] @ (800cef0 ) 800cd6a: 7d53 ldrb r3, [r2, #21] 800cd6c: f361 0382 bfi r3, r1, #2, #1 800cd70: 7553 strb r3, [r2, #21] statusPacket.lockState = 0; 800cd72: 4a5f ldr r2, [pc, #380] @ (800cef0 ) 800cd74: 7d53 ldrb r3, [r2, #21] 800cd76: f023 0308 bic.w r3, r3, #8 800cd7a: 7553 strb r3, [r2, #21] statusPacket.stopButton = !IN_ReadInput(IN_ESTOP); 800cd7c: 2003 movs r0, #3 800cd7e: f7fc fd9b bl 80098b8 800cd82: 4603 mov r3, r0 800cd84: 2b00 cmp r3, #0 800cd86: bf0c ite eq 800cd88: 2301 moveq r3, #1 800cd8a: 2300 movne r3, #0 800cd8c: b2d9 uxtb r1, r3 800cd8e: 4a58 ldr r2, [pc, #352] @ (800cef0 ) 800cd90: 7d53 ldrb r3, [r2, #21] 800cd92: f361 1304 bfi r3, r1, #4, #1 800cd96: 7553 strb r3, [r2, #21] statusPacket.logAvailable = (debug_buffer_available()>0)?1:0; 800cd98: f7fd fac2 bl 800a320 800cd9c: 4603 mov r3, r0 800cd9e: 2b00 cmp r3, #0 800cda0: bf14 ite ne 800cda2: 2301 movne r3, #1 800cda4: 2300 moveq r3, #0 800cda6: b2d9 uxtb r1, r3 800cda8: 4a51 ldr r2, [pc, #324] @ (800cef0 ) 800cdaa: 7d53 ldrb r3, [r2, #21] 800cdac: f361 1345 bfi r3, r1, #5, #1 800cdb0: 7553 strb r3, [r2, #21] statusPacket.evInfoAvailable = 0; 800cdb2: 4a4f ldr r2, [pc, #316] @ (800cef0 ) 800cdb4: 7d53 ldrb r3, [r2, #21] 800cdb6: f023 0340 bic.w r3, r3, #64 @ 0x40 800cdba: 7553 strb r3, [r2, #21] statusPacket.psuOnline = PSU0.online; 800cdbc: 4b4d ldr r3, [pc, #308] @ (800cef4 ) 800cdbe: 7a1b ldrb r3, [r3, #8] 800cdc0: f003 0301 and.w r3, r3, #1 800cdc4: b2d9 uxtb r1, r3 800cdc6: 4a4a ldr r2, [pc, #296] @ (800cef0 ) 800cdc8: 7d53 ldrb r3, [r2, #21] 800cdca: f361 13c7 bfi r3, r1, #7, #1 800cdce: 7553 strb r3, [r2, #21] statusPacket.tempConnector0 = CONN_ReadTemp(0); // температура коннектора 800cdd0: 2000 movs r0, #0 800cdd2: f7fc fe67 bl 8009aa4 800cdd6: 4603 mov r3, r0 800cdd8: b25a sxtb r2, r3 800cdda: 4b45 ldr r3, [pc, #276] @ (800cef0 ) 800cddc: 765a strb r2, [r3, #25] statusPacket.tempConnector1 = CONN_ReadTemp(1); 800cdde: 2001 movs r0, #1 800cde0: f7fc fe60 bl 8009aa4 800cde4: 4603 mov r3, r0 800cde6: b25a sxtb r2, r3 800cde8: 4b41 ldr r3, [pc, #260] @ (800cef0 ) 800cdea: 769a strb r2, [r3, #26] statusPacket.tempAmbient = PSU0.tempAmbient; // температура окружающего воздуха 800cdec: 4b41 ldr r3, [pc, #260] @ (800cef4 ) 800cdee: 69db ldr r3, [r3, #28] 800cdf0: b25a sxtb r2, r3 800cdf2: 4b3f ldr r3, [pc, #252] @ (800cef0 ) 800cdf4: 76da strb r2, [r3, #27] statusPacket.tempBatteryMax = 0; 800cdf6: 4b3e ldr r3, [pc, #248] @ (800cef0 ) 800cdf8: 2200 movs r2, #0 800cdfa: 771a strb r2, [r3, #28] statusPacket.tempBatteryMin = 0; 800cdfc: 4b3c ldr r3, [pc, #240] @ (800cef0 ) 800cdfe: 2200 movs r2, #0 800ce00: 775a strb r2, [r3, #29] statusPacket.highestVoltageOfBatteryCell = 0; 800ce02: 4b3b ldr r3, [pc, #236] @ (800cef0 ) 800ce04: 2200 movs r2, #0 800ce06: 779a strb r2, [r3, #30] 800ce08: 2200 movs r2, #0 800ce0a: 77da strb r2, [r3, #31] statusPacket.batteryStatus = 0; 800ce0c: 4b38 ldr r3, [pc, #224] @ (800cef0 ) 800ce0e: 2200 movs r2, #0 800ce10: f883 2020 strb.w r2, [r3, #32] statusPacket.phaseVoltageAB = PSU_06.VAB; 800ce14: 4b38 ldr r3, [pc, #224] @ (800cef8 ) 800ce16: 689b ldr r3, [r3, #8] 800ce18: b29a uxth r2, r3 800ce1a: 4b35 ldr r3, [pc, #212] @ (800cef0 ) 800ce1c: f8a3 2021 strh.w r2, [r3, #33] @ 0x21 statusPacket.phaseVoltageBC = PSU_06.VBC; 800ce20: 4b35 ldr r3, [pc, #212] @ (800cef8 ) 800ce22: 68db ldr r3, [r3, #12] 800ce24: b29a uxth r2, r3 800ce26: 4b32 ldr r3, [pc, #200] @ (800cef0 ) 800ce28: f8a3 2023 strh.w r2, [r3, #35] @ 0x23 statusPacket.phaseVoltageCA = PSU_06.VCA; 800ce2c: 4b32 ldr r3, [pc, #200] @ (800cef8 ) 800ce2e: 691b ldr r3, [r3, #16] 800ce30: b29a uxth r2, r3 800ce32: 4b2f ldr r3, [pc, #188] @ (800cef0 ) 800ce34: f8a3 2025 strh.w r2, [r3, #37] @ 0x25 // GBT TODO memset(statusPacket.VIN, 0, sizeof(statusPacket.VIN)); 800ce38: 2211 movs r2, #17 800ce3a: 2100 movs r1, #0 800ce3c: 482f ldr r0, [pc, #188] @ (800cefc ) 800ce3e: f007 fadf bl 8014400 // GBT TODO statusPacket.batteryType = 0; 800ce42: 4b2b ldr r3, [pc, #172] @ (800cef0 ) 800ce44: 2200 movs r2, #0 800ce46: f883 2038 strb.w r2, [r3, #56] @ 0x38 statusPacket.batteryCapacity = 0; 800ce4a: 4b29 ldr r3, [pc, #164] @ (800cef0 ) 800ce4c: 2200 movs r2, #0 800ce4e: f883 2039 strb.w r2, [r3, #57] @ 0x39 800ce52: 2200 movs r2, #0 800ce54: f883 203a strb.w r2, [r3, #58] @ 0x3a statusPacket.batteryVoltage = 0; 800ce58: 4b25 ldr r3, [pc, #148] @ (800cef0 ) 800ce5a: 2200 movs r2, #0 800ce5c: f883 203b strb.w r2, [r3, #59] @ 0x3b 800ce60: 2200 movs r2, #0 800ce62: f883 203c strb.w r2, [r3, #60] @ 0x3c memset(statusPacket.batteryVendor, 0, sizeof(statusPacket.batteryVendor)); 800ce66: 2204 movs r2, #4 800ce68: 2100 movs r1, #0 800ce6a: 4825 ldr r0, [pc, #148] @ (800cf00 ) 800ce6c: f007 fac8 bl 8014400 statusPacket.batterySN = 0; 800ce70: 4b1f ldr r3, [pc, #124] @ (800cef0 ) 800ce72: 2200 movs r2, #0 800ce74: f883 2041 strb.w r2, [r3, #65] @ 0x41 800ce78: 2200 movs r2, #0 800ce7a: f883 2042 strb.w r2, [r3, #66] @ 0x42 800ce7e: 2200 movs r2, #0 800ce80: f883 2043 strb.w r2, [r3, #67] @ 0x43 800ce84: 2200 movs r2, #0 800ce86: f883 2044 strb.w r2, [r3, #68] @ 0x44 statusPacket.batteryManuD = 0; 800ce8a: 4b19 ldr r3, [pc, #100] @ (800cef0 ) 800ce8c: 2200 movs r2, #0 800ce8e: f883 2047 strb.w r2, [r3, #71] @ 0x47 statusPacket.batteryManuM = 0; 800ce92: 4b17 ldr r3, [pc, #92] @ (800cef0 ) 800ce94: 2200 movs r2, #0 800ce96: f883 2046 strb.w r2, [r3, #70] @ 0x46 statusPacket.batteryManuY = 0; 800ce9a: 4b15 ldr r3, [pc, #84] @ (800cef0 ) 800ce9c: 2200 movs r2, #0 800ce9e: f883 2045 strb.w r2, [r3, #69] @ 0x45 statusPacket.batteryCycleCount = 0; 800cea2: 4b13 ldr r3, [pc, #76] @ (800cef0 ) 800cea4: 2200 movs r2, #0 800cea6: f883 2048 strb.w r2, [r3, #72] @ 0x48 800ceaa: 2200 movs r2, #0 800ceac: f883 2049 strb.w r2, [r3, #73] @ 0x49 statusPacket.ownAuto = 0; 800ceb0: 4b0f ldr r3, [pc, #60] @ (800cef0 ) 800ceb2: 2200 movs r2, #0 800ceb4: f883 204a strb.w r2, [r3, #74] @ 0x4a memset(statusPacket.EV_SW_VER, 0, sizeof(statusPacket.EV_SW_VER)); 800ceb8: 2208 movs r2, #8 800ceba: 2100 movs r1, #0 800cebc: 4811 ldr r0, [pc, #68] @ (800cf04 ) 800cebe: f007 fa9f bl 8014400 statusPacket.testMode = 0; 800cec2: 4b0b ldr r3, [pc, #44] @ (800cef0 ) 800cec4: 2200 movs r2, #0 800cec6: f883 2053 strb.w r2, [r3, #83] @ 0x53 statusPacket.testVoltage = 0; 800ceca: 4b09 ldr r3, [pc, #36] @ (800cef0 ) 800cecc: 2200 movs r2, #0 800cece: f883 2054 strb.w r2, [r3, #84] @ 0x54 800ced2: 2200 movs r2, #0 800ced4: f883 2055 strb.w r2, [r3, #85] @ 0x55 statusPacket.testCurrent = 0; 800ced8: 4b05 ldr r3, [pc, #20] @ (800cef0 ) 800ceda: 2200 movs r2, #0 800cedc: f883 2056 strb.w r2, [r3, #86] @ 0x56 800cee0: 2200 movs r2, #0 800cee2: f883 2057 strb.w r2, [r3, #87] @ 0x57 // В debug.c есть CONN_SetState, предполагаем наличие CONN_GetState() // Если такой функции нет, закомментируйте следующую строку: // statusPacket.connState = CONN_GetState(); } 800cee6: bf00 nop 800cee8: bd80 pop {r7, pc} 800ceea: bf00 nop 800ceec: 20000398 .word 0x20000398 800cef0: 20001030 .word 0x20001030 800cef4: 200008e4 .word 0x200008e4 800cef8: 200008b8 .word 0x200008b8 800cefc: 20001057 .word 0x20001057 800cf00: 2000106d .word 0x2000106d 800cf04: 2000107b .word 0x2000107b 0800cf08 : #include "sma_filter.h" void SMAFilter_Init(SMAFilter_t* f) { 800cf08: b480 push {r7} 800cf0a: b085 sub sp, #20 800cf0c: af00 add r7, sp, #0 800cf0e: 6078 str r0, [r7, #4] if (f == 0) return; 800cf10: 687b ldr r3, [r7, #4] 800cf12: 2b00 cmp r3, #0 800cf14: d018 beq.n 800cf48 f->sum = 0; 800cf16: 687b ldr r3, [r7, #4] 800cf18: 2200 movs r2, #0 800cf1a: 601a str r2, [r3, #0] f->idx = 0; 800cf1c: 687b ldr r3, [r7, #4] 800cf1e: 2200 movs r2, #0 800cf20: 809a strh r2, [r3, #4] f->count = 0; 800cf22: 687b ldr r3, [r7, #4] 800cf24: 2200 movs r2, #0 800cf26: 80da strh r2, [r3, #6] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800cf28: 2300 movs r3, #0 800cf2a: 81fb strh r3, [r7, #14] 800cf2c: e008 b.n 800cf40 f->buffer[i] = 0; 800cf2e: 89fa ldrh r2, [r7, #14] 800cf30: 687b ldr r3, [r7, #4] 800cf32: 3202 adds r2, #2 800cf34: 2100 movs r1, #0 800cf36: f843 1022 str.w r1, [r3, r2, lsl #2] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800cf3a: 89fb ldrh r3, [r7, #14] 800cf3c: 3301 adds r3, #1 800cf3e: 81fb strh r3, [r7, #14] 800cf40: 89fb ldrh r3, [r7, #14] 800cf42: 2b07 cmp r3, #7 800cf44: d9f3 bls.n 800cf2e 800cf46: e000 b.n 800cf4a if (f == 0) return; 800cf48: bf00 nop } } 800cf4a: 3714 adds r7, #20 800cf4c: 46bd mov sp, r7 800cf4e: bc80 pop {r7} 800cf50: 4770 bx lr 0800cf52 : int32_t SMAFilter_Update(SMAFilter_t* f, int32_t x) { 800cf52: b480 push {r7} 800cf54: b085 sub sp, #20 800cf56: af00 add r7, sp, #0 800cf58: 6078 str r0, [r7, #4] 800cf5a: 6039 str r1, [r7, #0] if (f == 0) return x; 800cf5c: 687b ldr r3, [r7, #4] 800cf5e: 2b00 cmp r3, #0 800cf60: d101 bne.n 800cf66 800cf62: 683b ldr r3, [r7, #0] 800cf64: e056 b.n 800d014 // Пока окно не заполнено полностью, делим по фактическому count. if (f->count < SMA_FILTER_WINDOW) { 800cf66: 687b ldr r3, [r7, #4] 800cf68: 88db ldrh r3, [r3, #6] 800cf6a: 2b07 cmp r3, #7 800cf6c: d827 bhi.n 800cfbe f->buffer[f->idx] = x; 800cf6e: 687b ldr r3, [r7, #4] 800cf70: 889b ldrh r3, [r3, #4] 800cf72: 461a mov r2, r3 800cf74: 687b ldr r3, [r7, #4] 800cf76: 3202 adds r2, #2 800cf78: 6839 ldr r1, [r7, #0] 800cf7a: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += x; 800cf7e: 687b ldr r3, [r7, #4] 800cf80: 681a ldr r2, [r3, #0] 800cf82: 683b ldr r3, [r7, #0] 800cf84: 441a add r2, r3 800cf86: 687b ldr r3, [r7, #4] 800cf88: 601a str r2, [r3, #0] f->idx++; 800cf8a: 687b ldr r3, [r7, #4] 800cf8c: 889b ldrh r3, [r3, #4] 800cf8e: 3301 adds r3, #1 800cf90: b29a uxth r2, r3 800cf92: 687b ldr r3, [r7, #4] 800cf94: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800cf96: 687b ldr r3, [r7, #4] 800cf98: 889b ldrh r3, [r3, #4] 800cf9a: 2b07 cmp r3, #7 800cf9c: d902 bls.n 800cfa4 800cf9e: 687b ldr r3, [r7, #4] 800cfa0: 2200 movs r2, #0 800cfa2: 809a strh r2, [r3, #4] f->count++; 800cfa4: 687b ldr r3, [r7, #4] 800cfa6: 88db ldrh r3, [r3, #6] 800cfa8: 3301 adds r3, #1 800cfaa: b29a uxth r2, r3 800cfac: 687b ldr r3, [r7, #4] 800cfae: 80da strh r2, [r3, #6] return (int32_t)(f->sum / (int32_t)f->count); 800cfb0: 687b ldr r3, [r7, #4] 800cfb2: 681b ldr r3, [r3, #0] 800cfb4: 687a ldr r2, [r7, #4] 800cfb6: 88d2 ldrh r2, [r2, #6] 800cfb8: fb93 f3f2 sdiv r3, r3, r2 800cfbc: e02a b.n 800d014 } // Окно заполнено: "вычитаем старое + добавляем новое". int32_t old = f->buffer[f->idx]; 800cfbe: 687b ldr r3, [r7, #4] 800cfc0: 889b ldrh r3, [r3, #4] 800cfc2: 461a mov r2, r3 800cfc4: 687b ldr r3, [r7, #4] 800cfc6: 3202 adds r2, #2 800cfc8: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800cfcc: 60fb str r3, [r7, #12] f->buffer[f->idx] = x; 800cfce: 687b ldr r3, [r7, #4] 800cfd0: 889b ldrh r3, [r3, #4] 800cfd2: 461a mov r2, r3 800cfd4: 687b ldr r3, [r7, #4] 800cfd6: 3202 adds r2, #2 800cfd8: 6839 ldr r1, [r7, #0] 800cfda: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += (x - old); 800cfde: 687b ldr r3, [r7, #4] 800cfe0: 681a ldr r2, [r3, #0] 800cfe2: 6839 ldr r1, [r7, #0] 800cfe4: 68fb ldr r3, [r7, #12] 800cfe6: 1acb subs r3, r1, r3 800cfe8: 441a add r2, r3 800cfea: 687b ldr r3, [r7, #4] 800cfec: 601a str r2, [r3, #0] f->idx++; 800cfee: 687b ldr r3, [r7, #4] 800cff0: 889b ldrh r3, [r3, #4] 800cff2: 3301 adds r3, #1 800cff4: b29a uxth r2, r3 800cff6: 687b ldr r3, [r7, #4] 800cff8: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800cffa: 687b ldr r3, [r7, #4] 800cffc: 889b ldrh r3, [r3, #4] 800cffe: 2b07 cmp r3, #7 800d000: d902 bls.n 800d008 800d002: 687b ldr r3, [r7, #4] 800d004: 2200 movs r2, #0 800d006: 809a strh r2, [r3, #4] return (int32_t)(f->sum / (int32_t)SMA_FILTER_WINDOW); 800d008: 687b ldr r3, [r7, #4] 800d00a: 681b ldr r3, [r3, #0] 800d00c: 2b00 cmp r3, #0 800d00e: da00 bge.n 800d012 800d010: 3307 adds r3, #7 800d012: 10db asrs r3, r3, #3 } 800d014: 4618 mov r0, r3 800d016: 3714 adds r7, #20 800d018: 46bd mov sp, r7 800d01a: bc80 pop {r7} 800d01c: 4770 bx lr ... 0800d020 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800d020: b480 push {r7} 800d022: b085 sub sp, #20 800d024: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 800d026: 4b15 ldr r3, [pc, #84] @ (800d07c ) 800d028: 699b ldr r3, [r3, #24] 800d02a: 4a14 ldr r2, [pc, #80] @ (800d07c ) 800d02c: f043 0301 orr.w r3, r3, #1 800d030: 6193 str r3, [r2, #24] 800d032: 4b12 ldr r3, [pc, #72] @ (800d07c ) 800d034: 699b ldr r3, [r3, #24] 800d036: f003 0301 and.w r3, r3, #1 800d03a: 60bb str r3, [r7, #8] 800d03c: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800d03e: 4b0f ldr r3, [pc, #60] @ (800d07c ) 800d040: 69db ldr r3, [r3, #28] 800d042: 4a0e ldr r2, [pc, #56] @ (800d07c ) 800d044: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800d048: 61d3 str r3, [r2, #28] 800d04a: 4b0c ldr r3, [pc, #48] @ (800d07c ) 800d04c: 69db ldr r3, [r3, #28] 800d04e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800d052: 607b str r3, [r7, #4] 800d054: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 800d056: 4b0a ldr r3, [pc, #40] @ (800d080 ) 800d058: 685b ldr r3, [r3, #4] 800d05a: 60fb str r3, [r7, #12] 800d05c: 68fb ldr r3, [r7, #12] 800d05e: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 800d062: 60fb str r3, [r7, #12] 800d064: 68fb ldr r3, [r7, #12] 800d066: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 800d06a: 60fb str r3, [r7, #12] 800d06c: 4a04 ldr r2, [pc, #16] @ (800d080 ) 800d06e: 68fb ldr r3, [r7, #12] 800d070: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800d072: bf00 nop 800d074: 3714 adds r7, #20 800d076: 46bd mov sp, r7 800d078: bc80 pop {r7} 800d07a: 4770 bx lr 800d07c: 40021000 .word 0x40021000 800d080: 40010000 .word 0x40010000 0800d084 : { /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800d084: e7fe b.n 800d084 800d086: bf00 nop 0800d088 : void HardFault_Handler(void) { /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800d088: e7fe b.n 800d088 800d08a: bf00 nop 0800d08c : void MemManage_Handler(void) { /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800d08c: e7fe b.n 800d08c 800d08e: bf00 nop 0800d090 : void BusFault_Handler(void) { /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800d090: e7fe b.n 800d090 800d092: bf00 nop 0800d094 : void UsageFault_Handler(void) { /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 800d094: e7fe b.n 800d094 800d096: bf00 nop 0800d098 : /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800d098: 4770 bx lr 800d09a: bf00 nop 0800d09c : /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800d09c: 4770 bx lr 800d09e: bf00 nop 0800d0a0 : /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800d0a0: 4770 bx lr 800d0a2: bf00 nop 0800d0a4 : void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800d0a4: f000 be06 b.w 800dcb4 0800d0a8 : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { 800d0a8: b510 push {r4, lr} /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800d0aa: 4c09 ldr r4, [pc, #36] @ (800d0d0 ) 800d0ac: 2201 movs r2, #1 800d0ae: f44f 6100 mov.w r1, #2048 @ 0x800 800d0b2: 4620 mov r0, r4 800d0b4: f003 fa8b bl 80105ce /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 800d0b8: 4806 ldr r0, [pc, #24] @ (800d0d4 ) 800d0ba: f002 fdc7 bl 800fc4c /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d0be: 4620 mov r0, r4 /* USER CODE END DMA1_Channel1_IRQn 1 */ } 800d0c0: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d0c4: 2200 movs r2, #0 800d0c6: f44f 6100 mov.w r1, #2048 @ 0x800 800d0ca: f003 ba80 b.w 80105ce 800d0ce: bf00 nop 800d0d0: 40010c00 .word 0x40010c00 800d0d4: 200002a8 .word 0x200002a8 0800d0d8 : /** * @brief This function handles ADC1 and ADC2 global interrupts. */ void ADC1_2_IRQHandler(void) { 800d0d8: b510 push {r4, lr} /* USER CODE BEGIN ADC1_2_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800d0da: 4c09 ldr r4, [pc, #36] @ (800d100 ) 800d0dc: 2201 movs r2, #1 800d0de: f44f 6100 mov.w r1, #2048 @ 0x800 800d0e2: 4620 mov r0, r4 800d0e4: f003 fa73 bl 80105ce /* USER CODE END ADC1_2_IRQn 0 */ HAL_ADC_IRQHandler(&hadc1); 800d0e8: 4806 ldr r0, [pc, #24] @ (800d104 ) 800d0ea: f000 ffd9 bl 800e0a0 /* USER CODE BEGIN ADC1_2_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d0ee: 4620 mov r0, r4 /* USER CODE END ADC1_2_IRQn 1 */ } 800d0f0: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d0f4: 2200 movs r2, #0 800d0f6: f44f 6100 mov.w r1, #2048 @ 0x800 800d0fa: f003 ba68 b.w 80105ce 800d0fe: bf00 nop 800d100: 40010c00 .word 0x40010c00 800d104: 20000278 .word 0x20000278 0800d108 : /** * @brief This function handles CAN1 RX0 interrupt. */ void CAN1_RX0_IRQHandler(void) { 800d108: b510 push {r4, lr} /* USER CODE BEGIN CAN1_RX0_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800d10a: 4c09 ldr r4, [pc, #36] @ (800d130 ) 800d10c: 2201 movs r2, #1 800d10e: f44f 6180 mov.w r1, #1024 @ 0x400 800d112: 4620 mov r0, r4 800d114: f003 fa5b bl 80105ce /* USER CODE END CAN1_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan1); 800d118: 4806 ldr r0, [pc, #24] @ (800d134 ) 800d11a: f001 fffd bl 800f118 /* USER CODE BEGIN CAN1_RX0_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d11e: 4620 mov r0, r4 /* USER CODE END CAN1_RX0_IRQn 1 */ } 800d120: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d124: 2200 movs r2, #0 800d126: f44f 6180 mov.w r1, #1024 @ 0x400 800d12a: f003 ba50 b.w 80105ce 800d12e: bf00 nop 800d130: 40010c00 .word 0x40010c00 800d134: 20000344 .word 0x20000344 0800d138 : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 800d138: b510 push {r4, lr} /* USER CODE BEGIN TIM3_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800d13a: 4c09 ldr r4, [pc, #36] @ (800d160 ) 800d13c: 2201 movs r2, #1 800d13e: f44f 6100 mov.w r1, #2048 @ 0x800 800d142: 4620 mov r0, r4 800d144: f003 fa43 bl 80105ce /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 800d148: 4806 ldr r0, [pc, #24] @ (800d164 ) 800d14a: f004 fe21 bl 8011d90 /* USER CODE BEGIN TIM3_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d14e: 4620 mov r0, r4 /* USER CODE END TIM3_IRQn 1 */ } 800d150: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d154: 2200 movs r2, #0 800d156: f44f 6100 mov.w r1, #2048 @ 0x800 800d15a: f003 ba38 b.w 80105ce 800d15e: bf00 nop 800d160: 40010c00 .word 0x40010c00 800d164: 20001098 .word 0x20001098 0800d168 : void USART1_IRQHandler(void) { /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 800d168: 4801 ldr r0, [pc, #4] @ (800d170 ) 800d16a: f005 be6d b.w 8012e48 800d16e: bf00 nop 800d170: 20001170 .word 0x20001170 0800d174 : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 800d174: b510 push {r4, lr} /* USER CODE BEGIN USART2_IRQn 0 */ HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_SET); 800d176: 4c08 ldr r4, [pc, #32] @ (800d198 ) 800d178: 2201 movs r2, #1 800d17a: 2120 movs r1, #32 800d17c: 4620 mov r0, r4 800d17e: f003 fa26 bl 80105ce /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 800d182: 4806 ldr r0, [pc, #24] @ (800d19c ) 800d184: f005 fe60 bl 8012e48 /* USER CODE BEGIN USART2_IRQn 1 */ HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_RESET); 800d188: 4620 mov r0, r4 /* USER CODE END USART2_IRQn 1 */ } 800d18a: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_RESET); 800d18e: 2200 movs r2, #0 800d190: 2120 movs r1, #32 800d192: f003 ba1c b.w 80105ce 800d196: bf00 nop 800d198: 40010800 .word 0x40010800 800d19c: 200011b8 .word 0x200011b8 0800d1a0 : /** * @brief This function handles USART3 global interrupt. */ void USART3_IRQHandler(void) { 800d1a0: b510 push {r4, lr} /* USER CODE BEGIN USART3_IRQn 0 */ HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_SET); 800d1a2: 4c08 ldr r4, [pc, #32] @ (800d1c4 ) 800d1a4: 2201 movs r2, #1 800d1a6: 2140 movs r1, #64 @ 0x40 800d1a8: 4620 mov r0, r4 800d1aa: f003 fa10 bl 80105ce /* USER CODE END USART3_IRQn 0 */ HAL_UART_IRQHandler(&huart3); 800d1ae: 4806 ldr r0, [pc, #24] @ (800d1c8 ) 800d1b0: f005 fe4a bl 8012e48 /* USER CODE BEGIN USART3_IRQn 1 */ HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_RESET); 800d1b4: 4620 mov r0, r4 /* USER CODE END USART3_IRQn 1 */ } 800d1b6: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_RESET); 800d1ba: 2200 movs r2, #0 800d1bc: 2140 movs r1, #64 @ 0x40 800d1be: f003 ba06 b.w 80105ce 800d1c2: bf00 nop 800d1c4: 40010800 .word 0x40010800 800d1c8: 20001200 .word 0x20001200 0800d1cc : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 800d1cc: b510 push {r4, lr} /* USER CODE BEGIN UART5_IRQn 0 */ HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_SET); 800d1ce: 4c08 ldr r4, [pc, #32] @ (800d1f0 ) 800d1d0: 2201 movs r2, #1 800d1d2: 2104 movs r1, #4 800d1d4: 4620 mov r0, r4 800d1d6: f003 f9fa bl 80105ce /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 800d1da: 4806 ldr r0, [pc, #24] @ (800d1f4 ) 800d1dc: f005 fe34 bl 8012e48 /* USER CODE BEGIN UART5_IRQn 1 */ HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_RESET); 800d1e0: 4620 mov r0, r4 /* USER CODE END UART5_IRQn 1 */ } 800d1e2: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_RESET); 800d1e6: 2200 movs r2, #0 800d1e8: 2104 movs r1, #4 800d1ea: f003 b9f0 b.w 80105ce 800d1ee: bf00 nop 800d1f0: 40011000 .word 0x40011000 800d1f4: 20001128 .word 0x20001128 0800d1f8 : /** * @brief This function handles CAN2 TX interrupt. */ void CAN2_TX_IRQHandler(void) { 800d1f8: b510 push {r4, lr} /* USER CODE BEGIN CAN2_TX_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800d1fa: 4c09 ldr r4, [pc, #36] @ (800d220 ) 800d1fc: 2201 movs r2, #1 800d1fe: f44f 6180 mov.w r1, #1024 @ 0x400 800d202: 4620 mov r0, r4 800d204: f003 f9e3 bl 80105ce /* USER CODE END CAN2_TX_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800d208: 4806 ldr r0, [pc, #24] @ (800d224 ) 800d20a: f001 ff85 bl 800f118 /* USER CODE BEGIN CAN2_TX_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d20e: 4620 mov r0, r4 /* USER CODE END CAN2_TX_IRQn 1 */ } 800d210: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d214: 2200 movs r2, #0 800d216: f44f 6180 mov.w r1, #1024 @ 0x400 800d21a: f003 b9d8 b.w 80105ce 800d21e: bf00 nop 800d220: 40010c00 .word 0x40010c00 800d224: 2000036c .word 0x2000036c 0800d228 : /** * @brief This function handles CAN2 RX1 interrupt. */ void CAN2_RX1_IRQHandler(void) { 800d228: b510 push {r4, lr} /* USER CODE BEGIN CAN2_RX1_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800d22a: 4c09 ldr r4, [pc, #36] @ (800d250 ) 800d22c: 2201 movs r2, #1 800d22e: f44f 6180 mov.w r1, #1024 @ 0x400 800d232: 4620 mov r0, r4 800d234: f003 f9cb bl 80105ce /* USER CODE END CAN2_RX1_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800d238: 4806 ldr r0, [pc, #24] @ (800d254 ) 800d23a: f001 ff6d bl 800f118 /* USER CODE BEGIN CAN2_RX1_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d23e: 4620 mov r0, r4 /* USER CODE END CAN2_RX1_IRQn 1 */ } 800d240: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d244: 2200 movs r2, #0 800d246: f44f 6180 mov.w r1, #1024 @ 0x400 800d24a: f003 b9c0 b.w 80105ce 800d24e: bf00 nop 800d250: 40010c00 .word 0x40010c00 800d254: 2000036c .word 0x2000036c 0800d258 <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 800d258: b480 push {r7} 800d25a: af00 add r7, sp, #0 return 1; 800d25c: 2301 movs r3, #1 } 800d25e: 4618 mov r0, r3 800d260: 46bd mov sp, r7 800d262: bc80 pop {r7} 800d264: 4770 bx lr 0800d266 <_kill>: int _kill(int pid, int sig) { 800d266: b580 push {r7, lr} 800d268: b082 sub sp, #8 800d26a: af00 add r7, sp, #0 800d26c: 6078 str r0, [r7, #4] 800d26e: 6039 str r1, [r7, #0] (void)pid; (void)sig; errno = EINVAL; 800d270: f007 f8ce bl 8014410 <__errno> 800d274: 4603 mov r3, r0 800d276: 2216 movs r2, #22 800d278: 601a str r2, [r3, #0] return -1; 800d27a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800d27e: 4618 mov r0, r3 800d280: 3708 adds r7, #8 800d282: 46bd mov sp, r7 800d284: bd80 pop {r7, pc} 0800d286 <_exit>: void _exit (int status) { 800d286: b580 push {r7, lr} 800d288: b082 sub sp, #8 800d28a: af00 add r7, sp, #0 800d28c: 6078 str r0, [r7, #4] _kill(status, -1); 800d28e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800d292: 6878 ldr r0, [r7, #4] 800d294: f7ff ffe7 bl 800d266 <_kill> while (1) {} /* Make sure we hang here */ 800d298: bf00 nop 800d29a: e7fd b.n 800d298 <_exit+0x12> 0800d29c <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 800d29c: b580 push {r7, lr} 800d29e: b086 sub sp, #24 800d2a0: af00 add r7, sp, #0 800d2a2: 60f8 str r0, [r7, #12] 800d2a4: 60b9 str r1, [r7, #8] 800d2a6: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800d2a8: 2300 movs r3, #0 800d2aa: 617b str r3, [r7, #20] 800d2ac: e00a b.n 800d2c4 <_read+0x28> { *ptr++ = __io_getchar(); 800d2ae: f3af 8000 nop.w 800d2b2: 4601 mov r1, r0 800d2b4: 68bb ldr r3, [r7, #8] 800d2b6: 1c5a adds r2, r3, #1 800d2b8: 60ba str r2, [r7, #8] 800d2ba: b2ca uxtb r2, r1 800d2bc: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 800d2be: 697b ldr r3, [r7, #20] 800d2c0: 3301 adds r3, #1 800d2c2: 617b str r3, [r7, #20] 800d2c4: 697a ldr r2, [r7, #20] 800d2c6: 687b ldr r3, [r7, #4] 800d2c8: 429a cmp r2, r3 800d2ca: dbf0 blt.n 800d2ae <_read+0x12> } return len; 800d2cc: 687b ldr r3, [r7, #4] } 800d2ce: 4618 mov r0, r3 800d2d0: 3718 adds r7, #24 800d2d2: 46bd mov sp, r7 800d2d4: bd80 pop {r7, pc} 0800d2d6 <_close>: } return len; } int _close(int file) { 800d2d6: b480 push {r7} 800d2d8: b083 sub sp, #12 800d2da: af00 add r7, sp, #0 800d2dc: 6078 str r0, [r7, #4] (void)file; return -1; 800d2de: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800d2e2: 4618 mov r0, r3 800d2e4: 370c adds r7, #12 800d2e6: 46bd mov sp, r7 800d2e8: bc80 pop {r7} 800d2ea: 4770 bx lr 0800d2ec <_fstat>: int _fstat(int file, struct stat *st) { 800d2ec: b480 push {r7} 800d2ee: b083 sub sp, #12 800d2f0: af00 add r7, sp, #0 800d2f2: 6078 str r0, [r7, #4] 800d2f4: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 800d2f6: 683b ldr r3, [r7, #0] 800d2f8: f44f 5200 mov.w r2, #8192 @ 0x2000 800d2fc: 605a str r2, [r3, #4] return 0; 800d2fe: 2300 movs r3, #0 } 800d300: 4618 mov r0, r3 800d302: 370c adds r7, #12 800d304: 46bd mov sp, r7 800d306: bc80 pop {r7} 800d308: 4770 bx lr 0800d30a <_isatty>: int _isatty(int file) { 800d30a: b480 push {r7} 800d30c: b083 sub sp, #12 800d30e: af00 add r7, sp, #0 800d310: 6078 str r0, [r7, #4] (void)file; return 1; 800d312: 2301 movs r3, #1 } 800d314: 4618 mov r0, r3 800d316: 370c adds r7, #12 800d318: 46bd mov sp, r7 800d31a: bc80 pop {r7} 800d31c: 4770 bx lr 0800d31e <_lseek>: int _lseek(int file, int ptr, int dir) { 800d31e: b480 push {r7} 800d320: b085 sub sp, #20 800d322: af00 add r7, sp, #0 800d324: 60f8 str r0, [r7, #12] 800d326: 60b9 str r1, [r7, #8] 800d328: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 800d32a: 2300 movs r3, #0 } 800d32c: 4618 mov r0, r3 800d32e: 3714 adds r7, #20 800d330: 46bd mov sp, r7 800d332: bc80 pop {r7} 800d334: 4770 bx lr ... 0800d338 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 800d338: b580 push {r7, lr} 800d33a: b086 sub sp, #24 800d33c: af00 add r7, sp, #0 800d33e: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 800d340: 4a14 ldr r2, [pc, #80] @ (800d394 <_sbrk+0x5c>) 800d342: 4b15 ldr r3, [pc, #84] @ (800d398 <_sbrk+0x60>) 800d344: 1ad3 subs r3, r2, r3 800d346: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 800d348: 697b ldr r3, [r7, #20] 800d34a: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 800d34c: 4b13 ldr r3, [pc, #76] @ (800d39c <_sbrk+0x64>) 800d34e: 681b ldr r3, [r3, #0] 800d350: 2b00 cmp r3, #0 800d352: d102 bne.n 800d35a <_sbrk+0x22> { __sbrk_heap_end = &_end; 800d354: 4b11 ldr r3, [pc, #68] @ (800d39c <_sbrk+0x64>) 800d356: 4a12 ldr r2, [pc, #72] @ (800d3a0 <_sbrk+0x68>) 800d358: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 800d35a: 4b10 ldr r3, [pc, #64] @ (800d39c <_sbrk+0x64>) 800d35c: 681a ldr r2, [r3, #0] 800d35e: 687b ldr r3, [r7, #4] 800d360: 4413 add r3, r2 800d362: 693a ldr r2, [r7, #16] 800d364: 429a cmp r2, r3 800d366: d207 bcs.n 800d378 <_sbrk+0x40> { errno = ENOMEM; 800d368: f007 f852 bl 8014410 <__errno> 800d36c: 4603 mov r3, r0 800d36e: 220c movs r2, #12 800d370: 601a str r2, [r3, #0] return (void *)-1; 800d372: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800d376: e009 b.n 800d38c <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 800d378: 4b08 ldr r3, [pc, #32] @ (800d39c <_sbrk+0x64>) 800d37a: 681b ldr r3, [r3, #0] 800d37c: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 800d37e: 4b07 ldr r3, [pc, #28] @ (800d39c <_sbrk+0x64>) 800d380: 681a ldr r2, [r3, #0] 800d382: 687b ldr r3, [r7, #4] 800d384: 4413 add r3, r2 800d386: 4a05 ldr r2, [pc, #20] @ (800d39c <_sbrk+0x64>) 800d388: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 800d38a: 68fb ldr r3, [r7, #12] } 800d38c: 4618 mov r0, r3 800d38e: 3718 adds r7, #24 800d390: 46bd mov sp, r7 800d392: bd80 pop {r7, pc} 800d394: 20010000 .word 0x20010000 800d398: 00000400 .word 0x00000400 800d39c: 20001094 .word 0x20001094 800d3a0: 20001398 .word 0x20001398 0800d3a4 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 800d3a4: b480 push {r7} 800d3a6: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 800d3a8: bf00 nop 800d3aa: 46bd mov sp, r7 800d3ac: bc80 pop {r7} 800d3ae: 4770 bx lr 0800d3b0 : TIM_HandleTypeDef htim3; TIM_HandleTypeDef htim4; /* TIM3 init function */ void MX_TIM3_Init(void) { 800d3b0: b580 push {r7, lr} 800d3b2: b08e sub sp, #56 @ 0x38 800d3b4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800d3b6: f107 0328 add.w r3, r7, #40 @ 0x28 800d3ba: 2200 movs r2, #0 800d3bc: 601a str r2, [r3, #0] 800d3be: 605a str r2, [r3, #4] 800d3c0: 609a str r2, [r3, #8] 800d3c2: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800d3c4: f107 0320 add.w r3, r7, #32 800d3c8: 2200 movs r2, #0 800d3ca: 601a str r2, [r3, #0] 800d3cc: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800d3ce: 1d3b adds r3, r7, #4 800d3d0: 2200 movs r2, #0 800d3d2: 601a str r2, [r3, #0] 800d3d4: 605a str r2, [r3, #4] 800d3d6: 609a str r2, [r3, #8] 800d3d8: 60da str r2, [r3, #12] 800d3da: 611a str r2, [r3, #16] 800d3dc: 615a str r2, [r3, #20] 800d3de: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 800d3e0: 4b38 ldr r3, [pc, #224] @ (800d4c4 ) 800d3e2: 4a39 ldr r2, [pc, #228] @ (800d4c8 ) 800d3e4: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 800d3e6: 4b37 ldr r3, [pc, #220] @ (800d4c4 ) 800d3e8: 2200 movs r2, #0 800d3ea: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 800d3ec: 4b35 ldr r3, [pc, #212] @ (800d4c4 ) 800d3ee: 2200 movs r2, #0 800d3f0: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 800d3f2: 4b34 ldr r3, [pc, #208] @ (800d4c4 ) 800d3f4: f64f 72ff movw r2, #65535 @ 0xffff 800d3f8: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800d3fa: 4b32 ldr r3, [pc, #200] @ (800d4c4 ) 800d3fc: 2200 movs r2, #0 800d3fe: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800d400: 4b30 ldr r3, [pc, #192] @ (800d4c4 ) 800d402: 2200 movs r2, #0 800d404: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 800d406: 482f ldr r0, [pc, #188] @ (800d4c4 ) 800d408: f004 fa6f bl 80118ea 800d40c: 4603 mov r3, r0 800d40e: 2b00 cmp r3, #0 800d410: d001 beq.n 800d416 { Error_Handler(); 800d412: f7fd fb07 bl 800aa24 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800d416: f44f 5380 mov.w r3, #4096 @ 0x1000 800d41a: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 800d41c: f107 0328 add.w r3, r7, #40 @ 0x28 800d420: 4619 mov r1, r3 800d422: 4828 ldr r0, [pc, #160] @ (800d4c4 ) 800d424: f004 fec2 bl 80121ac 800d428: 4603 mov r3, r0 800d42a: 2b00 cmp r3, #0 800d42c: d001 beq.n 800d432 { Error_Handler(); 800d42e: f7fd faf9 bl 800aa24 } if (HAL_TIM_OC_Init(&htim3) != HAL_OK) 800d432: 4824 ldr r0, [pc, #144] @ (800d4c4 ) 800d434: f004 faa8 bl 8011988 800d438: 4603 mov r3, r0 800d43a: 2b00 cmp r3, #0 800d43c: d001 beq.n 800d442 { Error_Handler(); 800d43e: f7fd faf1 bl 800aa24 } if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 800d442: 4820 ldr r0, [pc, #128] @ (800d4c4 ) 800d444: f004 fba2 bl 8011b8c 800d448: 4603 mov r3, r0 800d44a: 2b00 cmp r3, #0 800d44c: d001 beq.n 800d452 { Error_Handler(); 800d44e: f7fd fae9 bl 800aa24 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_OC1; 800d452: 2330 movs r3, #48 @ 0x30 800d454: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800d456: 2300 movs r3, #0 800d458: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800d45a: f107 0320 add.w r3, r7, #32 800d45e: 4619 mov r1, r3 800d460: 4818 ldr r0, [pc, #96] @ (800d4c4 ) 800d462: f005 fa51 bl 8012908 800d466: 4603 mov r3, r0 800d468: 2b00 cmp r3, #0 800d46a: d001 beq.n 800d470 { Error_Handler(); 800d46c: f7fd fada bl 800aa24 } sConfigOC.OCMode = TIM_OCMODE_TIMING; 800d470: 2300 movs r3, #0 800d472: 607b str r3, [r7, #4] sConfigOC.Pulse = 1; 800d474: 2301 movs r3, #1 800d476: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800d478: 2300 movs r3, #0 800d47a: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800d47c: 2300 movs r3, #0 800d47e: 617b str r3, [r7, #20] if (HAL_TIM_OC_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 800d480: 1d3b adds r3, r7, #4 800d482: 2200 movs r2, #0 800d484: 4619 mov r1, r3 800d486: 480f ldr r0, [pc, #60] @ (800d4c4 ) 800d488: f004 fd72 bl 8011f70 800d48c: 4603 mov r3, r0 800d48e: 2b00 cmp r3, #0 800d490: d001 beq.n 800d496 { Error_Handler(); 800d492: f7fd fac7 bl 800aa24 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800d496: 2360 movs r3, #96 @ 0x60 800d498: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800d49a: 2300 movs r3, #0 800d49c: 60bb str r3, [r7, #8] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800d49e: 1d3b adds r3, r7, #4 800d4a0: 2204 movs r2, #4 800d4a2: 4619 mov r1, r3 800d4a4: 4807 ldr r0, [pc, #28] @ (800d4c4 ) 800d4a6: f004 fdbf bl 8012028 800d4aa: 4603 mov r3, r0 800d4ac: 2b00 cmp r3, #0 800d4ae: d001 beq.n 800d4b4 { Error_Handler(); 800d4b0: f7fd fab8 bl 800aa24 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 800d4b4: 4803 ldr r0, [pc, #12] @ (800d4c4 ) 800d4b6: f000 f8cf bl 800d658 } 800d4ba: bf00 nop 800d4bc: 3738 adds r7, #56 @ 0x38 800d4be: 46bd mov sp, r7 800d4c0: bd80 pop {r7, pc} 800d4c2: bf00 nop 800d4c4: 20001098 .word 0x20001098 800d4c8: 40000400 .word 0x40000400 0800d4cc : /* TIM4 init function */ void MX_TIM4_Init(void) { 800d4cc: b580 push {r7, lr} 800d4ce: b08e sub sp, #56 @ 0x38 800d4d0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800d4d2: f107 0328 add.w r3, r7, #40 @ 0x28 800d4d6: 2200 movs r2, #0 800d4d8: 601a str r2, [r3, #0] 800d4da: 605a str r2, [r3, #4] 800d4dc: 609a str r2, [r3, #8] 800d4de: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800d4e0: f107 0320 add.w r3, r7, #32 800d4e4: 2200 movs r2, #0 800d4e6: 601a str r2, [r3, #0] 800d4e8: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800d4ea: 1d3b adds r3, r7, #4 800d4ec: 2200 movs r2, #0 800d4ee: 601a str r2, [r3, #0] 800d4f0: 605a str r2, [r3, #4] 800d4f2: 609a str r2, [r3, #8] 800d4f4: 60da str r2, [r3, #12] 800d4f6: 611a str r2, [r3, #16] 800d4f8: 615a str r2, [r3, #20] 800d4fa: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM4_Init 1 */ /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; 800d4fc: 4b37 ldr r3, [pc, #220] @ (800d5dc ) 800d4fe: 4a38 ldr r2, [pc, #224] @ (800d5e0 ) 800d500: 601a str r2, [r3, #0] htim4.Init.Prescaler = 720; 800d502: 4b36 ldr r3, [pc, #216] @ (800d5dc ) 800d504: f44f 7234 mov.w r2, #720 @ 0x2d0 800d508: 605a str r2, [r3, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 800d50a: 4b34 ldr r3, [pc, #208] @ (800d5dc ) 800d50c: 2200 movs r2, #0 800d50e: 609a str r2, [r3, #8] htim4.Init.Period = 100; 800d510: 4b32 ldr r3, [pc, #200] @ (800d5dc ) 800d512: 2264 movs r2, #100 @ 0x64 800d514: 60da str r2, [r3, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800d516: 4b31 ldr r3, [pc, #196] @ (800d5dc ) 800d518: 2200 movs r2, #0 800d51a: 611a str r2, [r3, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800d51c: 4b2f ldr r3, [pc, #188] @ (800d5dc ) 800d51e: 2200 movs r2, #0 800d520: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 800d522: 482e ldr r0, [pc, #184] @ (800d5dc ) 800d524: f004 f9e1 bl 80118ea 800d528: 4603 mov r3, r0 800d52a: 2b00 cmp r3, #0 800d52c: d001 beq.n 800d532 { Error_Handler(); 800d52e: f7fd fa79 bl 800aa24 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800d532: f44f 5380 mov.w r3, #4096 @ 0x1000 800d536: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 800d538: f107 0328 add.w r3, r7, #40 @ 0x28 800d53c: 4619 mov r1, r3 800d53e: 4827 ldr r0, [pc, #156] @ (800d5dc ) 800d540: f004 fe34 bl 80121ac 800d544: 4603 mov r3, r0 800d546: 2b00 cmp r3, #0 800d548: d001 beq.n 800d54e { Error_Handler(); 800d54a: f7fd fa6b bl 800aa24 } if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) 800d54e: 4823 ldr r0, [pc, #140] @ (800d5dc ) 800d550: f004 fb1c bl 8011b8c 800d554: 4603 mov r3, r0 800d556: 2b00 cmp r3, #0 800d558: d001 beq.n 800d55e { Error_Handler(); 800d55a: f7fd fa63 bl 800aa24 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800d55e: 2300 movs r3, #0 800d560: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800d562: 2300 movs r3, #0 800d564: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 800d566: f107 0320 add.w r3, r7, #32 800d56a: 4619 mov r1, r3 800d56c: 481b ldr r0, [pc, #108] @ (800d5dc ) 800d56e: f005 f9cb bl 8012908 800d572: 4603 mov r3, r0 800d574: 2b00 cmp r3, #0 800d576: d001 beq.n 800d57c { Error_Handler(); 800d578: f7fd fa54 bl 800aa24 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800d57c: 2360 movs r3, #96 @ 0x60 800d57e: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800d580: 2300 movs r3, #0 800d582: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800d584: 2300 movs r3, #0 800d586: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800d588: 2300 movs r3, #0 800d58a: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800d58c: 1d3b adds r3, r7, #4 800d58e: 2204 movs r2, #4 800d590: 4619 mov r1, r3 800d592: 4812 ldr r0, [pc, #72] @ (800d5dc ) 800d594: f004 fd48 bl 8012028 800d598: 4603 mov r3, r0 800d59a: 2b00 cmp r3, #0 800d59c: d001 beq.n 800d5a2 { Error_Handler(); 800d59e: f7fd fa41 bl 800aa24 } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 800d5a2: 1d3b adds r3, r7, #4 800d5a4: 2208 movs r2, #8 800d5a6: 4619 mov r1, r3 800d5a8: 480c ldr r0, [pc, #48] @ (800d5dc ) 800d5aa: f004 fd3d bl 8012028 800d5ae: 4603 mov r3, r0 800d5b0: 2b00 cmp r3, #0 800d5b2: d001 beq.n 800d5b8 { Error_Handler(); 800d5b4: f7fd fa36 bl 800aa24 } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 800d5b8: 1d3b adds r3, r7, #4 800d5ba: 220c movs r2, #12 800d5bc: 4619 mov r1, r3 800d5be: 4807 ldr r0, [pc, #28] @ (800d5dc ) 800d5c0: f004 fd32 bl 8012028 800d5c4: 4603 mov r3, r0 800d5c6: 2b00 cmp r3, #0 800d5c8: d001 beq.n 800d5ce { Error_Handler(); 800d5ca: f7fd fa2b bl 800aa24 } /* USER CODE BEGIN TIM4_Init 2 */ /* USER CODE END TIM4_Init 2 */ HAL_TIM_MspPostInit(&htim4); 800d5ce: 4803 ldr r0, [pc, #12] @ (800d5dc ) 800d5d0: f000 f842 bl 800d658 } 800d5d4: bf00 nop 800d5d6: 3738 adds r7, #56 @ 0x38 800d5d8: 46bd mov sp, r7 800d5da: bd80 pop {r7, pc} 800d5dc: 200010e0 .word 0x200010e0 800d5e0: 40000800 .word 0x40000800 0800d5e4 : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 800d5e4: b580 push {r7, lr} 800d5e6: b084 sub sp, #16 800d5e8: af00 add r7, sp, #0 800d5ea: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM3) 800d5ec: 687b ldr r3, [r7, #4] 800d5ee: 681b ldr r3, [r3, #0] 800d5f0: 4a16 ldr r2, [pc, #88] @ (800d64c ) 800d5f2: 4293 cmp r3, r2 800d5f4: d114 bne.n 800d620 { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 800d5f6: 4b16 ldr r3, [pc, #88] @ (800d650 ) 800d5f8: 69db ldr r3, [r3, #28] 800d5fa: 4a15 ldr r2, [pc, #84] @ (800d650 ) 800d5fc: f043 0302 orr.w r3, r3, #2 800d600: 61d3 str r3, [r2, #28] 800d602: 4b13 ldr r3, [pc, #76] @ (800d650 ) 800d604: 69db ldr r3, [r3, #28] 800d606: f003 0302 and.w r3, r3, #2 800d60a: 60fb str r3, [r7, #12] 800d60c: 68fb ldr r3, [r7, #12] /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); 800d60e: 2200 movs r2, #0 800d610: 2100 movs r1, #0 800d612: 201d movs r0, #29 800d614: f002 f89f bl 800f756 HAL_NVIC_EnableIRQ(TIM3_IRQn); 800d618: 201d movs r0, #29 800d61a: f002 f8b8 bl 800f78e __HAL_RCC_TIM4_CLK_ENABLE(); /* USER CODE BEGIN TIM4_MspInit 1 */ /* USER CODE END TIM4_MspInit 1 */ } } 800d61e: e010 b.n 800d642 else if(tim_baseHandle->Instance==TIM4) 800d620: 687b ldr r3, [r7, #4] 800d622: 681b ldr r3, [r3, #0] 800d624: 4a0b ldr r2, [pc, #44] @ (800d654 ) 800d626: 4293 cmp r3, r2 800d628: d10b bne.n 800d642 __HAL_RCC_TIM4_CLK_ENABLE(); 800d62a: 4b09 ldr r3, [pc, #36] @ (800d650 ) 800d62c: 69db ldr r3, [r3, #28] 800d62e: 4a08 ldr r2, [pc, #32] @ (800d650 ) 800d630: f043 0304 orr.w r3, r3, #4 800d634: 61d3 str r3, [r2, #28] 800d636: 4b06 ldr r3, [pc, #24] @ (800d650 ) 800d638: 69db ldr r3, [r3, #28] 800d63a: f003 0304 and.w r3, r3, #4 800d63e: 60bb str r3, [r7, #8] 800d640: 68bb ldr r3, [r7, #8] } 800d642: bf00 nop 800d644: 3710 adds r7, #16 800d646: 46bd mov sp, r7 800d648: bd80 pop {r7, pc} 800d64a: bf00 nop 800d64c: 40000400 .word 0x40000400 800d650: 40021000 .word 0x40021000 800d654: 40000800 .word 0x40000800 0800d658 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 800d658: b580 push {r7, lr} 800d65a: b08a sub sp, #40 @ 0x28 800d65c: af00 add r7, sp, #0 800d65e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800d660: f107 0314 add.w r3, r7, #20 800d664: 2200 movs r2, #0 800d666: 601a str r2, [r3, #0] 800d668: 605a str r2, [r3, #4] 800d66a: 609a str r2, [r3, #8] 800d66c: 60da str r2, [r3, #12] if(timHandle->Instance==TIM3) 800d66e: 687b ldr r3, [r7, #4] 800d670: 681b ldr r3, [r3, #0] 800d672: 4a26 ldr r2, [pc, #152] @ (800d70c ) 800d674: 4293 cmp r3, r2 800d676: d118 bne.n 800d6aa { /* USER CODE BEGIN TIM3_MspPostInit 0 */ /* USER CODE END TIM3_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800d678: 4b25 ldr r3, [pc, #148] @ (800d710 ) 800d67a: 699b ldr r3, [r3, #24] 800d67c: 4a24 ldr r2, [pc, #144] @ (800d710 ) 800d67e: f043 0304 orr.w r3, r3, #4 800d682: 6193 str r3, [r2, #24] 800d684: 4b22 ldr r3, [pc, #136] @ (800d710 ) 800d686: 699b ldr r3, [r3, #24] 800d688: f003 0304 and.w r3, r3, #4 800d68c: 613b str r3, [r7, #16] 800d68e: 693b ldr r3, [r7, #16] /**TIM3 GPIO Configuration PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = CP_PWM_Pin; 800d690: 2380 movs r3, #128 @ 0x80 800d692: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d694: 2302 movs r3, #2 800d696: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800d698: 2302 movs r3, #2 800d69a: 623b str r3, [r7, #32] HAL_GPIO_Init(CP_PWM_GPIO_Port, &GPIO_InitStruct); 800d69c: f107 0314 add.w r3, r7, #20 800d6a0: 4619 mov r1, r3 800d6a2: 481c ldr r0, [pc, #112] @ (800d714 ) 800d6a4: f002 fd3c bl 8010120 /* USER CODE BEGIN TIM4_MspPostInit 1 */ /* USER CODE END TIM4_MspPostInit 1 */ } } 800d6a8: e02b b.n 800d702 else if(timHandle->Instance==TIM4) 800d6aa: 687b ldr r3, [r7, #4] 800d6ac: 681b ldr r3, [r3, #0] 800d6ae: 4a1a ldr r2, [pc, #104] @ (800d718 ) 800d6b0: 4293 cmp r3, r2 800d6b2: d126 bne.n 800d702 __HAL_RCC_GPIOD_CLK_ENABLE(); 800d6b4: 4b16 ldr r3, [pc, #88] @ (800d710 ) 800d6b6: 699b ldr r3, [r3, #24] 800d6b8: 4a15 ldr r2, [pc, #84] @ (800d710 ) 800d6ba: f043 0320 orr.w r3, r3, #32 800d6be: 6193 str r3, [r2, #24] 800d6c0: 4b13 ldr r3, [pc, #76] @ (800d710 ) 800d6c2: 699b ldr r3, [r3, #24] 800d6c4: f003 0320 and.w r3, r3, #32 800d6c8: 60fb str r3, [r7, #12] 800d6ca: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; 800d6cc: f44f 4360 mov.w r3, #57344 @ 0xe000 800d6d0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d6d2: 2302 movs r3, #2 800d6d4: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800d6d6: 2302 movs r3, #2 800d6d8: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d6da: f107 0314 add.w r3, r7, #20 800d6de: 4619 mov r1, r3 800d6e0: 480e ldr r0, [pc, #56] @ (800d71c ) 800d6e2: f002 fd1d bl 8010120 __HAL_AFIO_REMAP_TIM4_ENABLE(); 800d6e6: 4b0e ldr r3, [pc, #56] @ (800d720 ) 800d6e8: 685b ldr r3, [r3, #4] 800d6ea: 627b str r3, [r7, #36] @ 0x24 800d6ec: 6a7b ldr r3, [r7, #36] @ 0x24 800d6ee: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800d6f2: 627b str r3, [r7, #36] @ 0x24 800d6f4: 6a7b ldr r3, [r7, #36] @ 0x24 800d6f6: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800d6fa: 627b str r3, [r7, #36] @ 0x24 800d6fc: 4a08 ldr r2, [pc, #32] @ (800d720 ) 800d6fe: 6a7b ldr r3, [r7, #36] @ 0x24 800d700: 6053 str r3, [r2, #4] } 800d702: bf00 nop 800d704: 3728 adds r7, #40 @ 0x28 800d706: 46bd mov sp, r7 800d708: bd80 pop {r7, pc} 800d70a: bf00 nop 800d70c: 40000400 .word 0x40000400 800d710: 40021000 .word 0x40021000 800d714: 40010800 .word 0x40010800 800d718: 40000800 .word 0x40000800 800d71c: 40011400 .word 0x40011400 800d720: 40010000 .word 0x40010000 0800d724 : UART_HandleTypeDef huart2; UART_HandleTypeDef huart3; /* UART5 init function */ void MX_UART5_Init(void) { 800d724: b580 push {r7, lr} 800d726: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 800d728: 4b11 ldr r3, [pc, #68] @ (800d770 ) 800d72a: 4a12 ldr r2, [pc, #72] @ (800d774 ) 800d72c: 601a str r2, [r3, #0] huart5.Init.BaudRate = 9600; 800d72e: 4b10 ldr r3, [pc, #64] @ (800d770 ) 800d730: f44f 5216 mov.w r2, #9600 @ 0x2580 800d734: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 800d736: 4b0e ldr r3, [pc, #56] @ (800d770 ) 800d738: 2200 movs r2, #0 800d73a: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 800d73c: 4b0c ldr r3, [pc, #48] @ (800d770 ) 800d73e: 2200 movs r2, #0 800d740: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 800d742: 4b0b ldr r3, [pc, #44] @ (800d770 ) 800d744: 2200 movs r2, #0 800d746: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 800d748: 4b09 ldr r3, [pc, #36] @ (800d770 ) 800d74a: 220c movs r2, #12 800d74c: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d74e: 4b08 ldr r3, [pc, #32] @ (800d770 ) 800d750: 2200 movs r2, #0 800d752: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 800d754: 4b06 ldr r3, [pc, #24] @ (800d770 ) 800d756: 2200 movs r2, #0 800d758: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 800d75a: 4805 ldr r0, [pc, #20] @ (800d770 ) 800d75c: f005 f94c bl 80129f8 800d760: 4603 mov r3, r0 800d762: 2b00 cmp r3, #0 800d764: d001 beq.n 800d76a { Error_Handler(); 800d766: f7fd f95d bl 800aa24 } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 800d76a: bf00 nop 800d76c: bd80 pop {r7, pc} 800d76e: bf00 nop 800d770: 20001128 .word 0x20001128 800d774: 40005000 .word 0x40005000 0800d778 : /* USART1 init function */ void MX_USART1_UART_Init(void) { 800d778: b580 push {r7, lr} 800d77a: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 800d77c: 4b11 ldr r3, [pc, #68] @ (800d7c4 ) 800d77e: 4a12 ldr r2, [pc, #72] @ (800d7c8 ) 800d780: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800d782: 4b10 ldr r3, [pc, #64] @ (800d7c4 ) 800d784: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800d788: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800d78a: 4b0e ldr r3, [pc, #56] @ (800d7c4 ) 800d78c: 2200 movs r2, #0 800d78e: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 800d790: 4b0c ldr r3, [pc, #48] @ (800d7c4 ) 800d792: 2200 movs r2, #0 800d794: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800d796: 4b0b ldr r3, [pc, #44] @ (800d7c4 ) 800d798: 2200 movs r2, #0 800d79a: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 800d79c: 4b09 ldr r3, [pc, #36] @ (800d7c4 ) 800d79e: 220c movs r2, #12 800d7a0: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d7a2: 4b08 ldr r3, [pc, #32] @ (800d7c4 ) 800d7a4: 2200 movs r2, #0 800d7a6: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800d7a8: 4b06 ldr r3, [pc, #24] @ (800d7c4 ) 800d7aa: 2200 movs r2, #0 800d7ac: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 800d7ae: 4805 ldr r0, [pc, #20] @ (800d7c4 ) 800d7b0: f005 f922 bl 80129f8 800d7b4: 4603 mov r3, r0 800d7b6: 2b00 cmp r3, #0 800d7b8: d001 beq.n 800d7be { Error_Handler(); 800d7ba: f7fd f933 bl 800aa24 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 800d7be: bf00 nop 800d7c0: bd80 pop {r7, pc} 800d7c2: bf00 nop 800d7c4: 20001170 .word 0x20001170 800d7c8: 40013800 .word 0x40013800 0800d7cc : /* USART2 init function */ void MX_USART2_UART_Init(void) { 800d7cc: b580 push {r7, lr} 800d7ce: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 800d7d0: 4b11 ldr r3, [pc, #68] @ (800d818 ) 800d7d2: 4a12 ldr r2, [pc, #72] @ (800d81c ) 800d7d4: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 800d7d6: 4b10 ldr r3, [pc, #64] @ (800d818 ) 800d7d8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800d7dc: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 800d7de: 4b0e ldr r3, [pc, #56] @ (800d818 ) 800d7e0: 2200 movs r2, #0 800d7e2: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 800d7e4: 4b0c ldr r3, [pc, #48] @ (800d818 ) 800d7e6: 2200 movs r2, #0 800d7e8: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800d7ea: 4b0b ldr r3, [pc, #44] @ (800d818 ) 800d7ec: 2200 movs r2, #0 800d7ee: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 800d7f0: 4b09 ldr r3, [pc, #36] @ (800d818 ) 800d7f2: 220c movs r2, #12 800d7f4: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d7f6: 4b08 ldr r3, [pc, #32] @ (800d818 ) 800d7f8: 2200 movs r2, #0 800d7fa: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 800d7fc: 4b06 ldr r3, [pc, #24] @ (800d818 ) 800d7fe: 2200 movs r2, #0 800d800: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 800d802: 4805 ldr r0, [pc, #20] @ (800d818 ) 800d804: f005 f8f8 bl 80129f8 800d808: 4603 mov r3, r0 800d80a: 2b00 cmp r3, #0 800d80c: d001 beq.n 800d812 { Error_Handler(); 800d80e: f7fd f909 bl 800aa24 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 800d812: bf00 nop 800d814: bd80 pop {r7, pc} 800d816: bf00 nop 800d818: 200011b8 .word 0x200011b8 800d81c: 40004400 .word 0x40004400 0800d820 : /* USART3 init function */ void MX_USART3_UART_Init(void) { 800d820: b580 push {r7, lr} 800d822: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 800d824: 4b11 ldr r3, [pc, #68] @ (800d86c ) 800d826: 4a12 ldr r2, [pc, #72] @ (800d870 ) 800d828: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 800d82a: 4b10 ldr r3, [pc, #64] @ (800d86c ) 800d82c: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800d830: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 800d832: 4b0e ldr r3, [pc, #56] @ (800d86c ) 800d834: 2200 movs r2, #0 800d836: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 800d838: 4b0c ldr r3, [pc, #48] @ (800d86c ) 800d83a: 2200 movs r2, #0 800d83c: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 800d83e: 4b0b ldr r3, [pc, #44] @ (800d86c ) 800d840: 2200 movs r2, #0 800d842: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 800d844: 4b09 ldr r3, [pc, #36] @ (800d86c ) 800d846: 220c movs r2, #12 800d848: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d84a: 4b08 ldr r3, [pc, #32] @ (800d86c ) 800d84c: 2200 movs r2, #0 800d84e: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 800d850: 4b06 ldr r3, [pc, #24] @ (800d86c ) 800d852: 2200 movs r2, #0 800d854: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart3) != HAL_OK) 800d856: 4805 ldr r0, [pc, #20] @ (800d86c ) 800d858: f005 f8ce bl 80129f8 800d85c: 4603 mov r3, r0 800d85e: 2b00 cmp r3, #0 800d860: d001 beq.n 800d866 { Error_Handler(); 800d862: f7fd f8df bl 800aa24 } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 800d866: bf00 nop 800d868: bd80 pop {r7, pc} 800d86a: bf00 nop 800d86c: 20001200 .word 0x20001200 800d870: 40004800 .word 0x40004800 0800d874 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 800d874: b580 push {r7, lr} 800d876: b092 sub sp, #72 @ 0x48 800d878: af00 add r7, sp, #0 800d87a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800d87c: f107 0330 add.w r3, r7, #48 @ 0x30 800d880: 2200 movs r2, #0 800d882: 601a str r2, [r3, #0] 800d884: 605a str r2, [r3, #4] 800d886: 609a str r2, [r3, #8] 800d888: 60da str r2, [r3, #12] if(uartHandle->Instance==UART5) 800d88a: 687b ldr r3, [r7, #4] 800d88c: 681b ldr r3, [r3, #0] 800d88e: 4a95 ldr r2, [pc, #596] @ (800dae4 ) 800d890: 4293 cmp r3, r2 800d892: d145 bne.n 800d920 { /* USER CODE BEGIN UART5_MspInit 0 */ /* USER CODE END UART5_MspInit 0 */ /* UART5 clock enable */ __HAL_RCC_UART5_CLK_ENABLE(); 800d894: 4b94 ldr r3, [pc, #592] @ (800dae8 ) 800d896: 69db ldr r3, [r3, #28] 800d898: 4a93 ldr r2, [pc, #588] @ (800dae8 ) 800d89a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800d89e: 61d3 str r3, [r2, #28] 800d8a0: 4b91 ldr r3, [pc, #580] @ (800dae8 ) 800d8a2: 69db ldr r3, [r3, #28] 800d8a4: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800d8a8: 62fb str r3, [r7, #44] @ 0x2c 800d8aa: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 800d8ac: 4b8e ldr r3, [pc, #568] @ (800dae8 ) 800d8ae: 699b ldr r3, [r3, #24] 800d8b0: 4a8d ldr r2, [pc, #564] @ (800dae8 ) 800d8b2: f043 0310 orr.w r3, r3, #16 800d8b6: 6193 str r3, [r2, #24] 800d8b8: 4b8b ldr r3, [pc, #556] @ (800dae8 ) 800d8ba: 699b ldr r3, [r3, #24] 800d8bc: f003 0310 and.w r3, r3, #16 800d8c0: 62bb str r3, [r7, #40] @ 0x28 800d8c2: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOD_CLK_ENABLE(); 800d8c4: 4b88 ldr r3, [pc, #544] @ (800dae8 ) 800d8c6: 699b ldr r3, [r3, #24] 800d8c8: 4a87 ldr r2, [pc, #540] @ (800dae8 ) 800d8ca: f043 0320 orr.w r3, r3, #32 800d8ce: 6193 str r3, [r2, #24] 800d8d0: 4b85 ldr r3, [pc, #532] @ (800dae8 ) 800d8d2: 699b ldr r3, [r3, #24] 800d8d4: f003 0320 and.w r3, r3, #32 800d8d8: 627b str r3, [r7, #36] @ 0x24 800d8da: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART5 GPIO Configuration PC12 ------> UART5_TX PD2 ------> UART5_RX */ GPIO_InitStruct.Pin = GPIO_PIN_12; 800d8dc: f44f 5380 mov.w r3, #4096 @ 0x1000 800d8e0: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d8e2: 2302 movs r3, #2 800d8e4: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800d8e6: 2303 movs r3, #3 800d8e8: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800d8ea: f107 0330 add.w r3, r7, #48 @ 0x30 800d8ee: 4619 mov r1, r3 800d8f0: 487e ldr r0, [pc, #504] @ (800daec ) 800d8f2: f002 fc15 bl 8010120 GPIO_InitStruct.Pin = GPIO_PIN_2; 800d8f6: 2304 movs r3, #4 800d8f8: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800d8fa: 2300 movs r3, #0 800d8fc: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800d8fe: 2300 movs r3, #0 800d900: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d902: f107 0330 add.w r3, r7, #48 @ 0x30 800d906: 4619 mov r1, r3 800d908: 4879 ldr r0, [pc, #484] @ (800daf0 ) 800d90a: f002 fc09 bl 8010120 /* UART5 interrupt Init */ HAL_NVIC_SetPriority(UART5_IRQn, 0, 0); 800d90e: 2200 movs r2, #0 800d910: 2100 movs r1, #0 800d912: 2035 movs r0, #53 @ 0x35 800d914: f001 ff1f bl 800f756 HAL_NVIC_EnableIRQ(UART5_IRQn); 800d918: 2035 movs r0, #53 @ 0x35 800d91a: f001 ff38 bl 800f78e HAL_NVIC_EnableIRQ(USART3_IRQn); /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 800d91e: e0dc b.n 800dada else if(uartHandle->Instance==USART1) 800d920: 687b ldr r3, [r7, #4] 800d922: 681b ldr r3, [r3, #0] 800d924: 4a73 ldr r2, [pc, #460] @ (800daf4 ) 800d926: 4293 cmp r3, r2 800d928: d13a bne.n 800d9a0 __HAL_RCC_USART1_CLK_ENABLE(); 800d92a: 4b6f ldr r3, [pc, #444] @ (800dae8 ) 800d92c: 699b ldr r3, [r3, #24] 800d92e: 4a6e ldr r2, [pc, #440] @ (800dae8 ) 800d930: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800d934: 6193 str r3, [r2, #24] 800d936: 4b6c ldr r3, [pc, #432] @ (800dae8 ) 800d938: 699b ldr r3, [r3, #24] 800d93a: f403 4380 and.w r3, r3, #16384 @ 0x4000 800d93e: 623b str r3, [r7, #32] 800d940: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 800d942: 4b69 ldr r3, [pc, #420] @ (800dae8 ) 800d944: 699b ldr r3, [r3, #24] 800d946: 4a68 ldr r2, [pc, #416] @ (800dae8 ) 800d948: f043 0304 orr.w r3, r3, #4 800d94c: 6193 str r3, [r2, #24] 800d94e: 4b66 ldr r3, [pc, #408] @ (800dae8 ) 800d950: 699b ldr r3, [r3, #24] 800d952: f003 0304 and.w r3, r3, #4 800d956: 61fb str r3, [r7, #28] 800d958: 69fb ldr r3, [r7, #28] GPIO_InitStruct.Pin = GPIO_PIN_9; 800d95a: f44f 7300 mov.w r3, #512 @ 0x200 800d95e: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d960: 2302 movs r3, #2 800d962: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800d964: 2303 movs r3, #3 800d966: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800d968: f107 0330 add.w r3, r7, #48 @ 0x30 800d96c: 4619 mov r1, r3 800d96e: 4862 ldr r0, [pc, #392] @ (800daf8 ) 800d970: f002 fbd6 bl 8010120 GPIO_InitStruct.Pin = GPIO_PIN_10; 800d974: f44f 6380 mov.w r3, #1024 @ 0x400 800d978: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800d97a: 2300 movs r3, #0 800d97c: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800d97e: 2300 movs r3, #0 800d980: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800d982: f107 0330 add.w r3, r7, #48 @ 0x30 800d986: 4619 mov r1, r3 800d988: 485b ldr r0, [pc, #364] @ (800daf8 ) 800d98a: f002 fbc9 bl 8010120 HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 800d98e: 2200 movs r2, #0 800d990: 2100 movs r1, #0 800d992: 2025 movs r0, #37 @ 0x25 800d994: f001 fedf bl 800f756 HAL_NVIC_EnableIRQ(USART1_IRQn); 800d998: 2025 movs r0, #37 @ 0x25 800d99a: f001 fef8 bl 800f78e } 800d99e: e09c b.n 800dada else if(uartHandle->Instance==USART2) 800d9a0: 687b ldr r3, [r7, #4] 800d9a2: 681b ldr r3, [r3, #0] 800d9a4: 4a55 ldr r2, [pc, #340] @ (800dafc ) 800d9a6: 4293 cmp r3, r2 800d9a8: d146 bne.n 800da38 __HAL_RCC_USART2_CLK_ENABLE(); 800d9aa: 4b4f ldr r3, [pc, #316] @ (800dae8 ) 800d9ac: 69db ldr r3, [r3, #28] 800d9ae: 4a4e ldr r2, [pc, #312] @ (800dae8 ) 800d9b0: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d9b4: 61d3 str r3, [r2, #28] 800d9b6: 4b4c ldr r3, [pc, #304] @ (800dae8 ) 800d9b8: 69db ldr r3, [r3, #28] 800d9ba: f403 3300 and.w r3, r3, #131072 @ 0x20000 800d9be: 61bb str r3, [r7, #24] 800d9c0: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOD_CLK_ENABLE(); 800d9c2: 4b49 ldr r3, [pc, #292] @ (800dae8 ) 800d9c4: 699b ldr r3, [r3, #24] 800d9c6: 4a48 ldr r2, [pc, #288] @ (800dae8 ) 800d9c8: f043 0320 orr.w r3, r3, #32 800d9cc: 6193 str r3, [r2, #24] 800d9ce: 4b46 ldr r3, [pc, #280] @ (800dae8 ) 800d9d0: 699b ldr r3, [r3, #24] 800d9d2: f003 0320 and.w r3, r3, #32 800d9d6: 617b str r3, [r7, #20] 800d9d8: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_5; 800d9da: 2320 movs r3, #32 800d9dc: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d9de: 2302 movs r3, #2 800d9e0: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800d9e2: 2303 movs r3, #3 800d9e4: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d9e6: f107 0330 add.w r3, r7, #48 @ 0x30 800d9ea: 4619 mov r1, r3 800d9ec: 4840 ldr r0, [pc, #256] @ (800daf0 ) 800d9ee: f002 fb97 bl 8010120 GPIO_InitStruct.Pin = GPIO_PIN_6; 800d9f2: 2340 movs r3, #64 @ 0x40 800d9f4: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800d9f6: 2300 movs r3, #0 800d9f8: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800d9fa: 2300 movs r3, #0 800d9fc: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d9fe: f107 0330 add.w r3, r7, #48 @ 0x30 800da02: 4619 mov r1, r3 800da04: 483a ldr r0, [pc, #232] @ (800daf0 ) 800da06: f002 fb8b bl 8010120 __HAL_AFIO_REMAP_USART2_ENABLE(); 800da0a: 4b3d ldr r3, [pc, #244] @ (800db00 ) 800da0c: 685b ldr r3, [r3, #4] 800da0e: 643b str r3, [r7, #64] @ 0x40 800da10: 6c3b ldr r3, [r7, #64] @ 0x40 800da12: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800da16: 643b str r3, [r7, #64] @ 0x40 800da18: 6c3b ldr r3, [r7, #64] @ 0x40 800da1a: f043 0308 orr.w r3, r3, #8 800da1e: 643b str r3, [r7, #64] @ 0x40 800da20: 4a37 ldr r2, [pc, #220] @ (800db00 ) 800da22: 6c3b ldr r3, [r7, #64] @ 0x40 800da24: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); 800da26: 2200 movs r2, #0 800da28: 2100 movs r1, #0 800da2a: 2026 movs r0, #38 @ 0x26 800da2c: f001 fe93 bl 800f756 HAL_NVIC_EnableIRQ(USART2_IRQn); 800da30: 2026 movs r0, #38 @ 0x26 800da32: f001 feac bl 800f78e } 800da36: e050 b.n 800dada else if(uartHandle->Instance==USART3) 800da38: 687b ldr r3, [r7, #4] 800da3a: 681b ldr r3, [r3, #0] 800da3c: 4a31 ldr r2, [pc, #196] @ (800db04 ) 800da3e: 4293 cmp r3, r2 800da40: d14b bne.n 800dada __HAL_RCC_USART3_CLK_ENABLE(); 800da42: 4b29 ldr r3, [pc, #164] @ (800dae8 ) 800da44: 69db ldr r3, [r3, #28] 800da46: 4a28 ldr r2, [pc, #160] @ (800dae8 ) 800da48: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800da4c: 61d3 str r3, [r2, #28] 800da4e: 4b26 ldr r3, [pc, #152] @ (800dae8 ) 800da50: 69db ldr r3, [r3, #28] 800da52: f403 2380 and.w r3, r3, #262144 @ 0x40000 800da56: 613b str r3, [r7, #16] 800da58: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 800da5a: 4b23 ldr r3, [pc, #140] @ (800dae8 ) 800da5c: 699b ldr r3, [r3, #24] 800da5e: 4a22 ldr r2, [pc, #136] @ (800dae8 ) 800da60: f043 0310 orr.w r3, r3, #16 800da64: 6193 str r3, [r2, #24] 800da66: 4b20 ldr r3, [pc, #128] @ (800dae8 ) 800da68: 699b ldr r3, [r3, #24] 800da6a: f003 0310 and.w r3, r3, #16 800da6e: 60fb str r3, [r7, #12] 800da70: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_10; 800da72: f44f 6380 mov.w r3, #1024 @ 0x400 800da76: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800da78: 2302 movs r3, #2 800da7a: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800da7c: 2303 movs r3, #3 800da7e: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800da80: f107 0330 add.w r3, r7, #48 @ 0x30 800da84: 4619 mov r1, r3 800da86: 4819 ldr r0, [pc, #100] @ (800daec ) 800da88: f002 fb4a bl 8010120 GPIO_InitStruct.Pin = GPIO_PIN_11; 800da8c: f44f 6300 mov.w r3, #2048 @ 0x800 800da90: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800da92: 2300 movs r3, #0 800da94: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800da96: 2300 movs r3, #0 800da98: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800da9a: f107 0330 add.w r3, r7, #48 @ 0x30 800da9e: 4619 mov r1, r3 800daa0: 4812 ldr r0, [pc, #72] @ (800daec ) 800daa2: f002 fb3d bl 8010120 __HAL_AFIO_REMAP_USART3_PARTIAL(); 800daa6: 4b16 ldr r3, [pc, #88] @ (800db00 ) 800daa8: 685b ldr r3, [r3, #4] 800daaa: 647b str r3, [r7, #68] @ 0x44 800daac: 6c7b ldr r3, [r7, #68] @ 0x44 800daae: f023 0330 bic.w r3, r3, #48 @ 0x30 800dab2: 647b str r3, [r7, #68] @ 0x44 800dab4: 6c7b ldr r3, [r7, #68] @ 0x44 800dab6: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800daba: 647b str r3, [r7, #68] @ 0x44 800dabc: 6c7b ldr r3, [r7, #68] @ 0x44 800dabe: f043 0310 orr.w r3, r3, #16 800dac2: 647b str r3, [r7, #68] @ 0x44 800dac4: 4a0e ldr r2, [pc, #56] @ (800db00 ) 800dac6: 6c7b ldr r3, [r7, #68] @ 0x44 800dac8: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); 800daca: 2200 movs r2, #0 800dacc: 2100 movs r1, #0 800dace: 2027 movs r0, #39 @ 0x27 800dad0: f001 fe41 bl 800f756 HAL_NVIC_EnableIRQ(USART3_IRQn); 800dad4: 2027 movs r0, #39 @ 0x27 800dad6: f001 fe5a bl 800f78e } 800dada: bf00 nop 800dadc: 3748 adds r7, #72 @ 0x48 800dade: 46bd mov sp, r7 800dae0: bd80 pop {r7, pc} 800dae2: bf00 nop 800dae4: 40005000 .word 0x40005000 800dae8: 40021000 .word 0x40021000 800daec: 40011000 .word 0x40011000 800daf0: 40011400 .word 0x40011400 800daf4: 40013800 .word 0x40013800 800daf8: 40010800 .word 0x40010800 800dafc: 40004400 .word 0x40004400 800db00: 40010000 .word 0x40010000 800db04: 40004800 .word 0x40004800 0800db08 : void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) { 800db08: b580 push {r7, lr} 800db0a: b082 sub sp, #8 800db0c: af00 add r7, sp, #0 800db0e: 6078 str r0, [r7, #4] if(uartHandle->Instance==UART5) 800db10: 687b ldr r3, [r7, #4] 800db12: 681b ldr r3, [r3, #0] 800db14: 4a29 ldr r2, [pc, #164] @ (800dbbc ) 800db16: 4293 cmp r3, r2 800db18: d112 bne.n 800db40 { /* USER CODE BEGIN UART5_MspDeInit 0 */ /* USER CODE END UART5_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_UART5_CLK_DISABLE(); 800db1a: 4b29 ldr r3, [pc, #164] @ (800dbc0 ) 800db1c: 69db ldr r3, [r3, #28] 800db1e: 4a28 ldr r2, [pc, #160] @ (800dbc0 ) 800db20: f423 1380 bic.w r3, r3, #1048576 @ 0x100000 800db24: 61d3 str r3, [r2, #28] /**UART5 GPIO Configuration PC12 ------> UART5_TX PD2 ------> UART5_RX */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12); 800db26: f44f 5180 mov.w r1, #4096 @ 0x1000 800db2a: 4826 ldr r0, [pc, #152] @ (800dbc4 ) 800db2c: f002 fc7c bl 8010428 HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); 800db30: 2104 movs r1, #4 800db32: 4825 ldr r0, [pc, #148] @ (800dbc8 ) 800db34: f002 fc78 bl 8010428 /* UART5 interrupt Deinit */ HAL_NVIC_DisableIRQ(UART5_IRQn); 800db38: 2035 movs r0, #53 @ 0x35 800db3a: f001 fe36 bl 800f7aa HAL_NVIC_DisableIRQ(USART3_IRQn); /* USER CODE BEGIN USART3_MspDeInit 1 */ /* USER CODE END USART3_MspDeInit 1 */ } } 800db3e: e039 b.n 800dbb4 else if(uartHandle->Instance==USART1) 800db40: 687b ldr r3, [r7, #4] 800db42: 681b ldr r3, [r3, #0] 800db44: 4a21 ldr r2, [pc, #132] @ (800dbcc ) 800db46: 4293 cmp r3, r2 800db48: d10e bne.n 800db68 __HAL_RCC_USART1_CLK_DISABLE(); 800db4a: 4b1d ldr r3, [pc, #116] @ (800dbc0 ) 800db4c: 699b ldr r3, [r3, #24] 800db4e: 4a1c ldr r2, [pc, #112] @ (800dbc0 ) 800db50: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800db54: 6193 str r3, [r2, #24] HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); 800db56: f44f 61c0 mov.w r1, #1536 @ 0x600 800db5a: 481d ldr r0, [pc, #116] @ (800dbd0 ) 800db5c: f002 fc64 bl 8010428 HAL_NVIC_DisableIRQ(USART1_IRQn); 800db60: 2025 movs r0, #37 @ 0x25 800db62: f001 fe22 bl 800f7aa } 800db66: e025 b.n 800dbb4 else if(uartHandle->Instance==USART2) 800db68: 687b ldr r3, [r7, #4] 800db6a: 681b ldr r3, [r3, #0] 800db6c: 4a19 ldr r2, [pc, #100] @ (800dbd4 ) 800db6e: 4293 cmp r3, r2 800db70: d10d bne.n 800db8e __HAL_RCC_USART2_CLK_DISABLE(); 800db72: 4b13 ldr r3, [pc, #76] @ (800dbc0 ) 800db74: 69db ldr r3, [r3, #28] 800db76: 4a12 ldr r2, [pc, #72] @ (800dbc0 ) 800db78: f423 3300 bic.w r3, r3, #131072 @ 0x20000 800db7c: 61d3 str r3, [r2, #28] HAL_GPIO_DeInit(GPIOD, GPIO_PIN_5|GPIO_PIN_6); 800db7e: 2160 movs r1, #96 @ 0x60 800db80: 4811 ldr r0, [pc, #68] @ (800dbc8 ) 800db82: f002 fc51 bl 8010428 HAL_NVIC_DisableIRQ(USART2_IRQn); 800db86: 2026 movs r0, #38 @ 0x26 800db88: f001 fe0f bl 800f7aa } 800db8c: e012 b.n 800dbb4 else if(uartHandle->Instance==USART3) 800db8e: 687b ldr r3, [r7, #4] 800db90: 681b ldr r3, [r3, #0] 800db92: 4a11 ldr r2, [pc, #68] @ (800dbd8 ) 800db94: 4293 cmp r3, r2 800db96: d10d bne.n 800dbb4 __HAL_RCC_USART3_CLK_DISABLE(); 800db98: 4b09 ldr r3, [pc, #36] @ (800dbc0 ) 800db9a: 69db ldr r3, [r3, #28] 800db9c: 4a08 ldr r2, [pc, #32] @ (800dbc0 ) 800db9e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800dba2: 61d3 str r3, [r2, #28] HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11); 800dba4: f44f 6140 mov.w r1, #3072 @ 0xc00 800dba8: 4806 ldr r0, [pc, #24] @ (800dbc4 ) 800dbaa: f002 fc3d bl 8010428 HAL_NVIC_DisableIRQ(USART3_IRQn); 800dbae: 2027 movs r0, #39 @ 0x27 800dbb0: f001 fdfb bl 800f7aa } 800dbb4: bf00 nop 800dbb6: 3708 adds r7, #8 800dbb8: 46bd mov sp, r7 800dbba: bd80 pop {r7, pc} 800dbbc: 40005000 .word 0x40005000 800dbc0: 40021000 .word 0x40021000 800dbc4: 40011000 .word 0x40011000 800dbc8: 40011400 .word 0x40011400 800dbcc: 40013800 .word 0x40013800 800dbd0: 40010800 .word 0x40010800 800dbd4: 40004400 .word 0x40004400 800dbd8: 40004800 .word 0x40004800 0800dbdc : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 800dbdc: f7ff fbe2 bl 800d3a4 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 800dbe0: 480b ldr r0, [pc, #44] @ (800dc10 ) ldr r1, =_edata 800dbe2: 490c ldr r1, [pc, #48] @ (800dc14 ) ldr r2, =_sidata 800dbe4: 4a0c ldr r2, [pc, #48] @ (800dc18 ) movs r3, #0 800dbe6: 2300 movs r3, #0 b LoopCopyDataInit 800dbe8: e002 b.n 800dbf0 0800dbea : CopyDataInit: ldr r4, [r2, r3] 800dbea: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800dbec: 50c4 str r4, [r0, r3] adds r3, r3, #4 800dbee: 3304 adds r3, #4 0800dbf0 : LoopCopyDataInit: adds r4, r0, r3 800dbf0: 18c4 adds r4, r0, r3 cmp r4, r1 800dbf2: 428c cmp r4, r1 bcc CopyDataInit 800dbf4: d3f9 bcc.n 800dbea /* Zero fill the bss segment. */ ldr r2, =_sbss 800dbf6: 4a09 ldr r2, [pc, #36] @ (800dc1c ) ldr r4, =_ebss 800dbf8: 4c09 ldr r4, [pc, #36] @ (800dc20 ) movs r3, #0 800dbfa: 2300 movs r3, #0 b LoopFillZerobss 800dbfc: e001 b.n 800dc02 0800dbfe : FillZerobss: str r3, [r2] 800dbfe: 6013 str r3, [r2, #0] adds r2, r2, #4 800dc00: 3204 adds r2, #4 0800dc02 : LoopFillZerobss: cmp r2, r4 800dc02: 42a2 cmp r2, r4 bcc FillZerobss 800dc04: d3fb bcc.n 800dbfe /* Call static constructors */ bl __libc_init_array 800dc06: f006 fc09 bl 801441c <__libc_init_array> /* Call the application's entry point.*/ bl main 800dc0a: f7fc fe1d bl 800a848
bx lr 800dc0e: 4770 bx lr ldr r0, =_sdata 800dc10: 20000000 .word 0x20000000 ldr r1, =_edata 800dc14: 20000240 .word 0x20000240 ldr r2, =_sidata 800dc18: 08017264 .word 0x08017264 ldr r2, =_sbss 800dc1c: 20000240 .word 0x20000240 ldr r4, =_ebss 800dc20: 20001398 .word 0x20001398 0800dc24 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 800dc24: e7fe b.n 800dc24 ... 0800dc28 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800dc28: b580 push {r7, lr} 800dc2a: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 800dc2c: 4b08 ldr r3, [pc, #32] @ (800dc50 ) 800dc2e: 681b ldr r3, [r3, #0] 800dc30: 4a07 ldr r2, [pc, #28] @ (800dc50 ) 800dc32: f043 0310 orr.w r3, r3, #16 800dc36: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800dc38: 2003 movs r0, #3 800dc3a: f001 fd81 bl 800f740 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800dc3e: 200f movs r0, #15 800dc40: f000 f808 bl 800dc54 /* Init the low level hardware */ HAL_MspInit(); 800dc44: f7ff f9ec bl 800d020 /* Return function status */ return HAL_OK; 800dc48: 2300 movs r3, #0 } 800dc4a: 4618 mov r0, r3 800dc4c: bd80 pop {r7, pc} 800dc4e: bf00 nop 800dc50: 40022000 .word 0x40022000 0800dc54 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800dc54: b580 push {r7, lr} 800dc56: b082 sub sp, #8 800dc58: af00 add r7, sp, #0 800dc5a: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 800dc5c: 4b12 ldr r3, [pc, #72] @ (800dca8 ) 800dc5e: 681a ldr r2, [r3, #0] 800dc60: 4b12 ldr r3, [pc, #72] @ (800dcac ) 800dc62: 781b ldrb r3, [r3, #0] 800dc64: 4619 mov r1, r3 800dc66: f44f 737a mov.w r3, #1000 @ 0x3e8 800dc6a: fbb3 f3f1 udiv r3, r3, r1 800dc6e: fbb2 f3f3 udiv r3, r2, r3 800dc72: 4618 mov r0, r3 800dc74: f001 fda7 bl 800f7c6 800dc78: 4603 mov r3, r0 800dc7a: 2b00 cmp r3, #0 800dc7c: d001 beq.n 800dc82 { return HAL_ERROR; 800dc7e: 2301 movs r3, #1 800dc80: e00e b.n 800dca0 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800dc82: 687b ldr r3, [r7, #4] 800dc84: 2b0f cmp r3, #15 800dc86: d80a bhi.n 800dc9e { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800dc88: 2200 movs r2, #0 800dc8a: 6879 ldr r1, [r7, #4] 800dc8c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800dc90: f001 fd61 bl 800f756 uwTickPrio = TickPriority; 800dc94: 4a06 ldr r2, [pc, #24] @ (800dcb0 ) 800dc96: 687b ldr r3, [r7, #4] 800dc98: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800dc9a: 2300 movs r3, #0 800dc9c: e000 b.n 800dca0 return HAL_ERROR; 800dc9e: 2301 movs r3, #1 } 800dca0: 4618 mov r0, r3 800dca2: 3708 adds r7, #8 800dca4: 46bd mov sp, r7 800dca6: bd80 pop {r7, pc} 800dca8: 2000006c .word 0x2000006c 800dcac: 20000074 .word 0x20000074 800dcb0: 20000070 .word 0x20000070 0800dcb4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800dcb4: b480 push {r7} 800dcb6: af00 add r7, sp, #0 uwTick += uwTickFreq; 800dcb8: 4b05 ldr r3, [pc, #20] @ (800dcd0 ) 800dcba: 781b ldrb r3, [r3, #0] 800dcbc: 461a mov r2, r3 800dcbe: 4b05 ldr r3, [pc, #20] @ (800dcd4 ) 800dcc0: 681b ldr r3, [r3, #0] 800dcc2: 4413 add r3, r2 800dcc4: 4a03 ldr r2, [pc, #12] @ (800dcd4 ) 800dcc6: 6013 str r3, [r2, #0] } 800dcc8: bf00 nop 800dcca: 46bd mov sp, r7 800dccc: bc80 pop {r7} 800dcce: 4770 bx lr 800dcd0: 20000074 .word 0x20000074 800dcd4: 20001248 .word 0x20001248 0800dcd8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 800dcd8: b480 push {r7} 800dcda: af00 add r7, sp, #0 return uwTick; 800dcdc: 4b02 ldr r3, [pc, #8] @ (800dce8 ) 800dcde: 681b ldr r3, [r3, #0] } 800dce0: 4618 mov r0, r3 800dce2: 46bd mov sp, r7 800dce4: bc80 pop {r7} 800dce6: 4770 bx lr 800dce8: 20001248 .word 0x20001248 0800dcec : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 800dcec: b580 push {r7, lr} 800dcee: b084 sub sp, #16 800dcf0: af00 add r7, sp, #0 800dcf2: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800dcf4: f7ff fff0 bl 800dcd8 800dcf8: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800dcfa: 687b ldr r3, [r7, #4] 800dcfc: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800dcfe: 68fb ldr r3, [r7, #12] 800dd00: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800dd04: d005 beq.n 800dd12 { wait += (uint32_t)(uwTickFreq); 800dd06: 4b0a ldr r3, [pc, #40] @ (800dd30 ) 800dd08: 781b ldrb r3, [r3, #0] 800dd0a: 461a mov r2, r3 800dd0c: 68fb ldr r3, [r7, #12] 800dd0e: 4413 add r3, r2 800dd10: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 800dd12: bf00 nop 800dd14: f7ff ffe0 bl 800dcd8 800dd18: 4602 mov r2, r0 800dd1a: 68bb ldr r3, [r7, #8] 800dd1c: 1ad3 subs r3, r2, r3 800dd1e: 68fa ldr r2, [r7, #12] 800dd20: 429a cmp r2, r3 800dd22: d8f7 bhi.n 800dd14 { } } 800dd24: bf00 nop 800dd26: bf00 nop 800dd28: 3710 adds r7, #16 800dd2a: 46bd mov sp, r7 800dd2c: bd80 pop {r7, pc} 800dd2e: bf00 nop 800dd30: 20000074 .word 0x20000074 0800dd34 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 800dd34: b580 push {r7, lr} 800dd36: b086 sub sp, #24 800dd38: af00 add r7, sp, #0 800dd3a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800dd3c: 2300 movs r3, #0 800dd3e: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 800dd40: 2300 movs r3, #0 800dd42: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 800dd44: 2300 movs r3, #0 800dd46: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 800dd48: 2300 movs r3, #0 800dd4a: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 800dd4c: 687b ldr r3, [r7, #4] 800dd4e: 2b00 cmp r3, #0 800dd50: d101 bne.n 800dd56 { return HAL_ERROR; 800dd52: 2301 movs r3, #1 800dd54: e0be b.n 800ded4 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 800dd56: 687b ldr r3, [r7, #4] 800dd58: 689b ldr r3, [r3, #8] 800dd5a: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 800dd5c: 687b ldr r3, [r7, #4] 800dd5e: 6a9b ldr r3, [r3, #40] @ 0x28 800dd60: 2b00 cmp r3, #0 800dd62: d109 bne.n 800dd78 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 800dd64: 687b ldr r3, [r7, #4] 800dd66: 2200 movs r2, #0 800dd68: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 800dd6a: 687b ldr r3, [r7, #4] 800dd6c: 2200 movs r2, #0 800dd6e: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800dd72: 6878 ldr r0, [r7, #4] 800dd74: f7fb fc96 bl 80096a4 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800dd78: 6878 ldr r0, [r7, #4] 800dd7a: f000 fbbd bl 800e4f8 800dd7e: 4603 mov r3, r0 800dd80: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 800dd82: 687b ldr r3, [r7, #4] 800dd84: 6a9b ldr r3, [r3, #40] @ 0x28 800dd86: f003 0310 and.w r3, r3, #16 800dd8a: 2b00 cmp r3, #0 800dd8c: f040 8099 bne.w 800dec2 800dd90: 7dfb ldrb r3, [r7, #23] 800dd92: 2b00 cmp r3, #0 800dd94: f040 8095 bne.w 800dec2 (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800dd98: 687b ldr r3, [r7, #4] 800dd9a: 6a9b ldr r3, [r3, #40] @ 0x28 800dd9c: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800dda0: f023 0302 bic.w r3, r3, #2 800dda4: f043 0202 orr.w r2, r3, #2 800dda8: 687b ldr r3, [r7, #4] 800ddaa: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 800ddac: 687b ldr r3, [r7, #4] 800ddae: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800ddb0: 687b ldr r3, [r7, #4] 800ddb2: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 800ddb4: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 800ddb6: 687b ldr r3, [r7, #4] 800ddb8: 7b1b ldrb r3, [r3, #12] 800ddba: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800ddbc: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 800ddbe: 68ba ldr r2, [r7, #8] 800ddc0: 4313 orrs r3, r2 800ddc2: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 800ddc4: 687b ldr r3, [r7, #4] 800ddc6: 689b ldr r3, [r3, #8] 800ddc8: f5b3 7f80 cmp.w r3, #256 @ 0x100 800ddcc: d003 beq.n 800ddd6 800ddce: 687b ldr r3, [r7, #4] 800ddd0: 689b ldr r3, [r3, #8] 800ddd2: 2b01 cmp r3, #1 800ddd4: d102 bne.n 800dddc 800ddd6: f44f 7380 mov.w r3, #256 @ 0x100 800ddda: e000 b.n 800ddde 800dddc: 2300 movs r3, #0 800ddde: 693a ldr r2, [r7, #16] 800dde0: 4313 orrs r3, r2 800dde2: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 800dde4: 687b ldr r3, [r7, #4] 800dde6: 7d1b ldrb r3, [r3, #20] 800dde8: 2b01 cmp r3, #1 800ddea: d119 bne.n 800de20 { if (hadc->Init.ContinuousConvMode == DISABLE) 800ddec: 687b ldr r3, [r7, #4] 800ddee: 7b1b ldrb r3, [r3, #12] 800ddf0: 2b00 cmp r3, #0 800ddf2: d109 bne.n 800de08 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 800ddf4: 687b ldr r3, [r7, #4] 800ddf6: 699b ldr r3, [r3, #24] 800ddf8: 3b01 subs r3, #1 800ddfa: 035a lsls r2, r3, #13 800ddfc: 693b ldr r3, [r7, #16] 800ddfe: 4313 orrs r3, r2 800de00: f443 6300 orr.w r3, r3, #2048 @ 0x800 800de04: 613b str r3, [r7, #16] 800de06: e00b b.n 800de20 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800de08: 687b ldr r3, [r7, #4] 800de0a: 6a9b ldr r3, [r3, #40] @ 0x28 800de0c: f043 0220 orr.w r2, r3, #32 800de10: 687b ldr r3, [r7, #4] 800de12: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800de14: 687b ldr r3, [r7, #4] 800de16: 6adb ldr r3, [r3, #44] @ 0x2c 800de18: f043 0201 orr.w r2, r3, #1 800de1c: 687b ldr r3, [r7, #4] 800de1e: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 800de20: 687b ldr r3, [r7, #4] 800de22: 681b ldr r3, [r3, #0] 800de24: 685b ldr r3, [r3, #4] 800de26: f423 4169 bic.w r1, r3, #59648 @ 0xe900 800de2a: 687b ldr r3, [r7, #4] 800de2c: 681b ldr r3, [r3, #0] 800de2e: 693a ldr r2, [r7, #16] 800de30: 430a orrs r2, r1 800de32: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 800de34: 687b ldr r3, [r7, #4] 800de36: 681b ldr r3, [r3, #0] 800de38: 689a ldr r2, [r3, #8] 800de3a: 4b28 ldr r3, [pc, #160] @ (800dedc ) 800de3c: 4013 ands r3, r2 800de3e: 687a ldr r2, [r7, #4] 800de40: 6812 ldr r2, [r2, #0] 800de42: 68b9 ldr r1, [r7, #8] 800de44: 430b orrs r3, r1 800de46: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 800de48: 687b ldr r3, [r7, #4] 800de4a: 689b ldr r3, [r3, #8] 800de4c: f5b3 7f80 cmp.w r3, #256 @ 0x100 800de50: d003 beq.n 800de5a 800de52: 687b ldr r3, [r7, #4] 800de54: 689b ldr r3, [r3, #8] 800de56: 2b01 cmp r3, #1 800de58: d104 bne.n 800de64 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 800de5a: 687b ldr r3, [r7, #4] 800de5c: 691b ldr r3, [r3, #16] 800de5e: 3b01 subs r3, #1 800de60: 051b lsls r3, r3, #20 800de62: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 800de64: 687b ldr r3, [r7, #4] 800de66: 681b ldr r3, [r3, #0] 800de68: 6adb ldr r3, [r3, #44] @ 0x2c 800de6a: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 800de6e: 687b ldr r3, [r7, #4] 800de70: 681b ldr r3, [r3, #0] 800de72: 68fa ldr r2, [r7, #12] 800de74: 430a orrs r2, r1 800de76: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800de78: 687b ldr r3, [r7, #4] 800de7a: 681b ldr r3, [r3, #0] 800de7c: 689a ldr r2, [r3, #8] 800de7e: 4b18 ldr r3, [pc, #96] @ (800dee0 ) 800de80: 4013 ands r3, r2 800de82: 68ba ldr r2, [r7, #8] 800de84: 429a cmp r2, r3 800de86: d10b bne.n 800dea0 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 800de88: 687b ldr r3, [r7, #4] 800de8a: 2200 movs r2, #0 800de8c: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 800de8e: 687b ldr r3, [r7, #4] 800de90: 6a9b ldr r3, [r3, #40] @ 0x28 800de92: f023 0303 bic.w r3, r3, #3 800de96: f043 0201 orr.w r2, r3, #1 800de9a: 687b ldr r3, [r7, #4] 800de9c: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800de9e: e018 b.n 800ded2 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800dea0: 687b ldr r3, [r7, #4] 800dea2: 6a9b ldr r3, [r3, #40] @ 0x28 800dea4: f023 0312 bic.w r3, r3, #18 800dea8: f043 0210 orr.w r2, r3, #16 800deac: 687b ldr r3, [r7, #4] 800deae: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800deb0: 687b ldr r3, [r7, #4] 800deb2: 6adb ldr r3, [r3, #44] @ 0x2c 800deb4: f043 0201 orr.w r2, r3, #1 800deb8: 687b ldr r3, [r7, #4] 800deba: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 800debc: 2301 movs r3, #1 800debe: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800dec0: e007 b.n 800ded2 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800dec2: 687b ldr r3, [r7, #4] 800dec4: 6a9b ldr r3, [r3, #40] @ 0x28 800dec6: f043 0210 orr.w r2, r3, #16 800deca: 687b ldr r3, [r7, #4] 800decc: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800dece: 2301 movs r3, #1 800ded0: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800ded2: 7dfb ldrb r3, [r7, #23] } 800ded4: 4618 mov r0, r3 800ded6: 3718 adds r7, #24 800ded8: 46bd mov sp, r7 800deda: bd80 pop {r7, pc} 800dedc: ffe1f7fd .word 0xffe1f7fd 800dee0: ff1f0efe .word 0xff1f0efe 0800dee4 : * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { 800dee4: b580 push {r7, lr} 800dee6: b086 sub sp, #24 800dee8: af00 add r7, sp, #0 800deea: 60f8 str r0, [r7, #12] 800deec: 60b9 str r1, [r7, #8] 800deee: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800def0: 2300 movs r3, #0 800def2: 75fb strb r3, [r7, #23] assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); /* Verification if multimode is disabled (for devices with several ADC) */ /* If multimode is enabled, dedicated function multimode conversion */ /* start DMA must be used. */ if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) 800def4: 68fb ldr r3, [r7, #12] 800def6: 681b ldr r3, [r3, #0] 800def8: 4a64 ldr r2, [pc, #400] @ (800e08c ) 800defa: 4293 cmp r3, r2 800defc: d004 beq.n 800df08 800defe: 68fb ldr r3, [r7, #12] 800df00: 681b ldr r3, [r3, #0] 800df02: 4a63 ldr r2, [pc, #396] @ (800e090 ) 800df04: 4293 cmp r3, r2 800df06: d106 bne.n 800df16 800df08: 4b60 ldr r3, [pc, #384] @ (800e08c ) 800df0a: 685b ldr r3, [r3, #4] 800df0c: f403 2370 and.w r3, r3, #983040 @ 0xf0000 800df10: 2b00 cmp r3, #0 800df12: f040 80b3 bne.w 800e07c { /* Process locked */ __HAL_LOCK(hadc); 800df16: 68fb ldr r3, [r7, #12] 800df18: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800df1c: 2b01 cmp r3, #1 800df1e: d101 bne.n 800df24 800df20: 2302 movs r3, #2 800df22: e0ae b.n 800e082 800df24: 68fb ldr r3, [r7, #12] 800df26: 2201 movs r2, #1 800df28: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 800df2c: 68f8 ldr r0, [r7, #12] 800df2e: f000 fa89 bl 800e444 800df32: 4603 mov r3, r0 800df34: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800df36: 7dfb ldrb r3, [r7, #23] 800df38: 2b00 cmp r3, #0 800df3a: f040 809a bne.w 800e072 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 800df3e: 68fb ldr r3, [r7, #12] 800df40: 6a9b ldr r3, [r3, #40] @ 0x28 800df42: f423 6370 bic.w r3, r3, #3840 @ 0xf00 800df46: f023 0301 bic.w r3, r3, #1 800df4a: f443 7280 orr.w r2, r3, #256 @ 0x100 800df4e: 68fb ldr r3, [r7, #12] 800df50: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 800df52: 68fb ldr r3, [r7, #12] 800df54: 681b ldr r3, [r3, #0] 800df56: 4a4e ldr r2, [pc, #312] @ (800e090 ) 800df58: 4293 cmp r3, r2 800df5a: d105 bne.n 800df68 800df5c: 4b4b ldr r3, [pc, #300] @ (800e08c ) 800df5e: 685b ldr r3, [r3, #4] 800df60: f403 2370 and.w r3, r3, #983040 @ 0xf0000 800df64: 2b00 cmp r3, #0 800df66: d115 bne.n 800df94 { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800df68: 68fb ldr r3, [r7, #12] 800df6a: 6a9b ldr r3, [r3, #40] @ 0x28 800df6c: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 800df70: 68fb ldr r3, [r7, #12] 800df72: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800df74: 68fb ldr r3, [r7, #12] 800df76: 681b ldr r3, [r3, #0] 800df78: 685b ldr r3, [r3, #4] 800df7a: f403 6380 and.w r3, r3, #1024 @ 0x400 800df7e: 2b00 cmp r3, #0 800df80: d026 beq.n 800dfd0 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800df82: 68fb ldr r3, [r7, #12] 800df84: 6a9b ldr r3, [r3, #40] @ 0x28 800df86: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800df8a: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800df8e: 68fb ldr r3, [r7, #12] 800df90: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800df92: e01d b.n 800dfd0 } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800df94: 68fb ldr r3, [r7, #12] 800df96: 6a9b ldr r3, [r3, #40] @ 0x28 800df98: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800df9c: 68fb ldr r3, [r7, #12] 800df9e: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 800dfa0: 68fb ldr r3, [r7, #12] 800dfa2: 681b ldr r3, [r3, #0] 800dfa4: 4a39 ldr r2, [pc, #228] @ (800e08c ) 800dfa6: 4293 cmp r3, r2 800dfa8: d004 beq.n 800dfb4 800dfaa: 68fb ldr r3, [r7, #12] 800dfac: 681b ldr r3, [r3, #0] 800dfae: 4a38 ldr r2, [pc, #224] @ (800e090 ) 800dfb0: 4293 cmp r3, r2 800dfb2: d10d bne.n 800dfd0 800dfb4: 4b35 ldr r3, [pc, #212] @ (800e08c ) 800dfb6: 685b ldr r3, [r3, #4] 800dfb8: f403 6380 and.w r3, r3, #1024 @ 0x400 800dfbc: 2b00 cmp r3, #0 800dfbe: d007 beq.n 800dfd0 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800dfc0: 68fb ldr r3, [r7, #12] 800dfc2: 6a9b ldr r3, [r3, #40] @ 0x28 800dfc4: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800dfc8: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800dfcc: 68fb ldr r3, [r7, #12] 800dfce: 629a str r2, [r3, #40] @ 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800dfd0: 68fb ldr r3, [r7, #12] 800dfd2: 6a9b ldr r3, [r3, #40] @ 0x28 800dfd4: f403 5380 and.w r3, r3, #4096 @ 0x1000 800dfd8: 2b00 cmp r3, #0 800dfda: d006 beq.n 800dfea { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 800dfdc: 68fb ldr r3, [r7, #12] 800dfde: 6adb ldr r3, [r3, #44] @ 0x2c 800dfe0: f023 0206 bic.w r2, r3, #6 800dfe4: 68fb ldr r3, [r7, #12] 800dfe6: 62da str r2, [r3, #44] @ 0x2c 800dfe8: e002 b.n 800dff0 } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 800dfea: 68fb ldr r3, [r7, #12] 800dfec: 2200 movs r2, #0 800dfee: 62da str r2, [r3, #44] @ 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 800dff0: 68fb ldr r3, [r7, #12] 800dff2: 2200 movs r2, #0 800dff4: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 800dff8: 68fb ldr r3, [r7, #12] 800dffa: 6a1b ldr r3, [r3, #32] 800dffc: 4a25 ldr r2, [pc, #148] @ (800e094 ) 800dffe: 629a str r2, [r3, #40] @ 0x28 /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 800e000: 68fb ldr r3, [r7, #12] 800e002: 6a1b ldr r3, [r3, #32] 800e004: 4a24 ldr r2, [pc, #144] @ (800e098 ) 800e006: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 800e008: 68fb ldr r3, [r7, #12] 800e00a: 6a1b ldr r3, [r3, #32] 800e00c: 4a23 ldr r2, [pc, #140] @ (800e09c ) 800e00e: 631a str r2, [r3, #48] @ 0x30 /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 800e010: 68fb ldr r3, [r7, #12] 800e012: 681b ldr r3, [r3, #0] 800e014: f06f 0202 mvn.w r2, #2 800e018: 601a str r2, [r3, #0] /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); 800e01a: 68fb ldr r3, [r7, #12] 800e01c: 681b ldr r3, [r3, #0] 800e01e: 689a ldr r2, [r3, #8] 800e020: 68fb ldr r3, [r7, #12] 800e022: 681b ldr r3, [r3, #0] 800e024: f442 7280 orr.w r2, r2, #256 @ 0x100 800e028: 609a str r2, [r3, #8] /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 800e02a: 68fb ldr r3, [r7, #12] 800e02c: 6a18 ldr r0, [r3, #32] 800e02e: 68fb ldr r3, [r7, #12] 800e030: 681b ldr r3, [r3, #0] 800e032: 334c adds r3, #76 @ 0x4c 800e034: 4619 mov r1, r3 800e036: 68ba ldr r2, [r7, #8] 800e038: 687b ldr r3, [r7, #4] 800e03a: f001 fc63 bl 800f904 /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) 800e03e: 68fb ldr r3, [r7, #12] 800e040: 681b ldr r3, [r3, #0] 800e042: 689b ldr r3, [r3, #8] 800e044: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800e048: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e04c: d108 bne.n 800e060 { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 800e04e: 68fb ldr r3, [r7, #12] 800e050: 681b ldr r3, [r3, #0] 800e052: 689a ldr r2, [r3, #8] 800e054: 68fb ldr r3, [r7, #12] 800e056: 681b ldr r3, [r3, #0] 800e058: f442 02a0 orr.w r2, r2, #5242880 @ 0x500000 800e05c: 609a str r2, [r3, #8] if (tmp_hal_status == HAL_OK) 800e05e: e00f b.n 800e080 } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 800e060: 68fb ldr r3, [r7, #12] 800e062: 681b ldr r3, [r3, #0] 800e064: 689a ldr r2, [r3, #8] 800e066: 68fb ldr r3, [r7, #12] 800e068: 681b ldr r3, [r3, #0] 800e06a: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 800e06e: 609a str r2, [r3, #8] if (tmp_hal_status == HAL_OK) 800e070: e006 b.n 800e080 } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 800e072: 68fb ldr r3, [r7, #12] 800e074: 2200 movs r2, #0 800e076: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (tmp_hal_status == HAL_OK) 800e07a: e001 b.n 800e080 } } else { tmp_hal_status = HAL_ERROR; 800e07c: 2301 movs r3, #1 800e07e: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800e080: 7dfb ldrb r3, [r7, #23] } 800e082: 4618 mov r0, r3 800e084: 3718 adds r7, #24 800e086: 46bd mov sp, r7 800e088: bd80 pop {r7, pc} 800e08a: bf00 nop 800e08c: 40012400 .word 0x40012400 800e090: 40012800 .word 0x40012800 800e094: 0800e57b .word 0x0800e57b 800e098: 0800e5f7 .word 0x0800e5f7 800e09c: 0800e613 .word 0x0800e613 0800e0a0 : * @brief Handles ADC interrupt request * @param hadc: ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { 800e0a0: b580 push {r7, lr} 800e0a2: b084 sub sp, #16 800e0a4: af00 add r7, sp, #0 800e0a6: 6078 str r0, [r7, #4] uint32_t tmp_sr = hadc->Instance->SR; 800e0a8: 687b ldr r3, [r7, #4] 800e0aa: 681b ldr r3, [r3, #0] 800e0ac: 681b ldr r3, [r3, #0] 800e0ae: 60fb str r3, [r7, #12] uint32_t tmp_cr1 = hadc->Instance->CR1; 800e0b0: 687b ldr r3, [r7, #4] 800e0b2: 681b ldr r3, [r3, #0] 800e0b4: 685b ldr r3, [r3, #4] 800e0b6: 60bb str r3, [r7, #8] assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); /* ========== Check End of Conversion flag for regular group ========== */ if((tmp_cr1 & ADC_IT_EOC) == ADC_IT_EOC) 800e0b8: 68bb ldr r3, [r7, #8] 800e0ba: f003 0320 and.w r3, r3, #32 800e0be: 2b00 cmp r3, #0 800e0c0: d03e beq.n 800e140 { if((tmp_sr & ADC_FLAG_EOC) == ADC_FLAG_EOC) 800e0c2: 68fb ldr r3, [r7, #12] 800e0c4: f003 0302 and.w r3, r3, #2 800e0c8: 2b00 cmp r3, #0 800e0ca: d039 beq.n 800e140 { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 800e0cc: 687b ldr r3, [r7, #4] 800e0ce: 6a9b ldr r3, [r3, #40] @ 0x28 800e0d0: f003 0310 and.w r3, r3, #16 800e0d4: 2b00 cmp r3, #0 800e0d6: d105 bne.n 800e0e4 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800e0d8: 687b ldr r3, [r7, #4] 800e0da: 6a9b ldr r3, [r3, #40] @ 0x28 800e0dc: f443 7200 orr.w r2, r3, #512 @ 0x200 800e0e0: 687b ldr r3, [r7, #4] 800e0e2: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e0e4: 687b ldr r3, [r7, #4] 800e0e6: 681b ldr r3, [r3, #0] 800e0e8: 689b ldr r3, [r3, #8] 800e0ea: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800e0ee: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e0f2: d11d bne.n 800e130 (hadc->Init.ContinuousConvMode == DISABLE) ) 800e0f4: 687b ldr r3, [r7, #4] 800e0f6: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e0f8: 2b00 cmp r3, #0 800e0fa: d119 bne.n 800e130 { /* Disable ADC end of conversion interrupt on group regular */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); 800e0fc: 687b ldr r3, [r7, #4] 800e0fe: 681b ldr r3, [r3, #0] 800e100: 685a ldr r2, [r3, #4] 800e102: 687b ldr r3, [r7, #4] 800e104: 681b ldr r3, [r3, #0] 800e106: f022 0220 bic.w r2, r2, #32 800e10a: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800e10c: 687b ldr r3, [r7, #4] 800e10e: 6a9b ldr r3, [r3, #40] @ 0x28 800e110: f423 7280 bic.w r2, r3, #256 @ 0x100 800e114: 687b ldr r3, [r7, #4] 800e116: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800e118: 687b ldr r3, [r7, #4] 800e11a: 6a9b ldr r3, [r3, #40] @ 0x28 800e11c: f403 5380 and.w r3, r3, #4096 @ 0x1000 800e120: 2b00 cmp r3, #0 800e122: d105 bne.n 800e130 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800e124: 687b ldr r3, [r7, #4] 800e126: 6a9b ldr r3, [r3, #40] @ 0x28 800e128: f043 0201 orr.w r2, r3, #1 800e12c: 687b ldr r3, [r7, #4] 800e12e: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800e130: 6878 ldr r0, [r7, #4] 800e132: f7fb fa0b bl 800954c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 800e136: 687b ldr r3, [r7, #4] 800e138: 681b ldr r3, [r3, #0] 800e13a: f06f 0212 mvn.w r2, #18 800e13e: 601a str r2, [r3, #0] } } /* ========== Check End of Conversion flag for injected group ========== */ if((tmp_cr1 & ADC_IT_JEOC) == ADC_IT_JEOC) 800e140: 68bb ldr r3, [r7, #8] 800e142: f003 0380 and.w r3, r3, #128 @ 0x80 800e146: 2b00 cmp r3, #0 800e148: d04d beq.n 800e1e6 { if((tmp_sr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) 800e14a: 68fb ldr r3, [r7, #12] 800e14c: f003 0304 and.w r3, r3, #4 800e150: 2b00 cmp r3, #0 800e152: d048 beq.n 800e1e6 { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 800e154: 687b ldr r3, [r7, #4] 800e156: 6a9b ldr r3, [r3, #40] @ 0x28 800e158: f003 0310 and.w r3, r3, #16 800e15c: 2b00 cmp r3, #0 800e15e: d105 bne.n 800e16c { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 800e160: 687b ldr r3, [r7, #4] 800e162: 6a9b ldr r3, [r3, #40] @ 0x28 800e164: f443 5200 orr.w r2, r3, #8192 @ 0x2000 800e168: 687b ldr r3, [r7, #4] 800e16a: 629a str r2, [r3, #40] @ 0x28 /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 800e16c: 687b ldr r3, [r7, #4] 800e16e: 681b ldr r3, [r3, #0] 800e170: 689b ldr r3, [r3, #8] 800e172: f403 43e0 and.w r3, r3, #28672 @ 0x7000 800e176: f5b3 4fe0 cmp.w r3, #28672 @ 0x7000 800e17a: d012 beq.n 800e1a2 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 800e17c: 687b ldr r3, [r7, #4] 800e17e: 681b ldr r3, [r3, #0] 800e180: 685b ldr r3, [r3, #4] 800e182: f403 6380 and.w r3, r3, #1024 @ 0x400 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 800e186: 2b00 cmp r3, #0 800e188: d125 bne.n 800e1d6 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e18a: 687b ldr r3, [r7, #4] 800e18c: 681b ldr r3, [r3, #0] 800e18e: 689b ldr r3, [r3, #8] 800e190: f403 2360 and.w r3, r3, #917504 @ 0xe0000 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 800e194: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e198: d11d bne.n 800e1d6 (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) 800e19a: 687b ldr r3, [r7, #4] 800e19c: 7b1b ldrb r3, [r3, #12] (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e19e: 2b00 cmp r3, #0 800e1a0: d119 bne.n 800e1d6 { /* Disable ADC end of conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 800e1a2: 687b ldr r3, [r7, #4] 800e1a4: 681b ldr r3, [r3, #0] 800e1a6: 685a ldr r2, [r3, #4] 800e1a8: 687b ldr r3, [r7, #4] 800e1aa: 681b ldr r3, [r3, #0] 800e1ac: f022 0280 bic.w r2, r2, #128 @ 0x80 800e1b0: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 800e1b2: 687b ldr r3, [r7, #4] 800e1b4: 6a9b ldr r3, [r3, #40] @ 0x28 800e1b6: f423 5280 bic.w r2, r3, #4096 @ 0x1000 800e1ba: 687b ldr r3, [r7, #4] 800e1bc: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 800e1be: 687b ldr r3, [r7, #4] 800e1c0: 6a9b ldr r3, [r3, #40] @ 0x28 800e1c2: f403 7380 and.w r3, r3, #256 @ 0x100 800e1c6: 2b00 cmp r3, #0 800e1c8: d105 bne.n 800e1d6 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800e1ca: 687b ldr r3, [r7, #4] 800e1cc: 6a9b ldr r3, [r3, #40] @ 0x28 800e1ce: f043 0201 orr.w r2, r3, #1 800e1d2: 687b ldr r3, [r7, #4] 800e1d4: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); 800e1d6: 6878 ldr r0, [r7, #4] 800e1d8: f000 fae4 bl 800e7a4 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); 800e1dc: 687b ldr r3, [r7, #4] 800e1de: 681b ldr r3, [r3, #0] 800e1e0: f06f 020c mvn.w r2, #12 800e1e4: 601a str r2, [r3, #0] } } /* ========== Check Analog watchdog flags ========== */ if((tmp_cr1 & ADC_IT_AWD) == ADC_IT_AWD) 800e1e6: 68bb ldr r3, [r7, #8] 800e1e8: f003 0340 and.w r3, r3, #64 @ 0x40 800e1ec: 2b00 cmp r3, #0 800e1ee: d012 beq.n 800e216 { if((tmp_sr & ADC_FLAG_AWD) == ADC_FLAG_AWD) 800e1f0: 68fb ldr r3, [r7, #12] 800e1f2: f003 0301 and.w r3, r3, #1 800e1f6: 2b00 cmp r3, #0 800e1f8: d00d beq.n 800e216 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 800e1fa: 687b ldr r3, [r7, #4] 800e1fc: 6a9b ldr r3, [r3, #40] @ 0x28 800e1fe: f443 3280 orr.w r2, r3, #65536 @ 0x10000 800e202: 687b ldr r3, [r7, #4] 800e204: 629a str r2, [r3, #40] @ 0x28 /* Level out of window callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); 800e206: 6878 ldr r0, [r7, #4] 800e208: f000 f812 bl 800e230 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear the ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); 800e20c: 687b ldr r3, [r7, #4] 800e20e: 681b ldr r3, [r3, #0] 800e210: f06f 0201 mvn.w r2, #1 800e214: 601a str r2, [r3, #0] } } } 800e216: bf00 nop 800e218: 3710 adds r7, #16 800e21a: 46bd mov sp, r7 800e21c: bd80 pop {r7, pc} 0800e21e : * @brief Conversion DMA half-transfer callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) { 800e21e: b480 push {r7} 800e220: b083 sub sp, #12 800e222: af00 add r7, sp, #0 800e224: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 800e226: bf00 nop 800e228: 370c adds r7, #12 800e22a: 46bd mov sp, r7 800e22c: bc80 pop {r7} 800e22e: 4770 bx lr 0800e230 : * @brief Analog watchdog callback in non blocking mode. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { 800e230: b480 push {r7} 800e232: b083 sub sp, #12 800e234: af00 add r7, sp, #0 800e236: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } 800e238: bf00 nop 800e23a: 370c adds r7, #12 800e23c: 46bd mov sp, r7 800e23e: bc80 pop {r7} 800e240: 4770 bx lr 0800e242 : * (ADC conversion with interruption or transfer by DMA) * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 800e242: b480 push {r7} 800e244: b083 sub sp, #12 800e246: af00 add r7, sp, #0 800e248: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 800e24a: bf00 nop 800e24c: 370c adds r7, #12 800e24e: 46bd mov sp, r7 800e250: bc80 pop {r7} 800e252: 4770 bx lr 0800e254 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 800e254: b480 push {r7} 800e256: b085 sub sp, #20 800e258: af00 add r7, sp, #0 800e25a: 6078 str r0, [r7, #4] 800e25c: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e25e: 2300 movs r3, #0 800e260: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 800e262: 2300 movs r3, #0 800e264: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 800e266: 687b ldr r3, [r7, #4] 800e268: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e26c: 2b01 cmp r3, #1 800e26e: d101 bne.n 800e274 800e270: 2302 movs r3, #2 800e272: e0dc b.n 800e42e 800e274: 687b ldr r3, [r7, #4] 800e276: 2201 movs r2, #1 800e278: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 800e27c: 683b ldr r3, [r7, #0] 800e27e: 685b ldr r3, [r3, #4] 800e280: 2b06 cmp r3, #6 800e282: d81c bhi.n 800e2be { MODIFY_REG(hadc->Instance->SQR3 , 800e284: 687b ldr r3, [r7, #4] 800e286: 681b ldr r3, [r3, #0] 800e288: 6b59 ldr r1, [r3, #52] @ 0x34 800e28a: 683b ldr r3, [r7, #0] 800e28c: 685a ldr r2, [r3, #4] 800e28e: 4613 mov r3, r2 800e290: 009b lsls r3, r3, #2 800e292: 4413 add r3, r2 800e294: 3b05 subs r3, #5 800e296: 221f movs r2, #31 800e298: fa02 f303 lsl.w r3, r2, r3 800e29c: 43db mvns r3, r3 800e29e: 4019 ands r1, r3 800e2a0: 683b ldr r3, [r7, #0] 800e2a2: 6818 ldr r0, [r3, #0] 800e2a4: 683b ldr r3, [r7, #0] 800e2a6: 685a ldr r2, [r3, #4] 800e2a8: 4613 mov r3, r2 800e2aa: 009b lsls r3, r3, #2 800e2ac: 4413 add r3, r2 800e2ae: 3b05 subs r3, #5 800e2b0: fa00 f203 lsl.w r2, r0, r3 800e2b4: 687b ldr r3, [r7, #4] 800e2b6: 681b ldr r3, [r3, #0] 800e2b8: 430a orrs r2, r1 800e2ba: 635a str r2, [r3, #52] @ 0x34 800e2bc: e03c b.n 800e338 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 800e2be: 683b ldr r3, [r7, #0] 800e2c0: 685b ldr r3, [r3, #4] 800e2c2: 2b0c cmp r3, #12 800e2c4: d81c bhi.n 800e300 { MODIFY_REG(hadc->Instance->SQR2 , 800e2c6: 687b ldr r3, [r7, #4] 800e2c8: 681b ldr r3, [r3, #0] 800e2ca: 6b19 ldr r1, [r3, #48] @ 0x30 800e2cc: 683b ldr r3, [r7, #0] 800e2ce: 685a ldr r2, [r3, #4] 800e2d0: 4613 mov r3, r2 800e2d2: 009b lsls r3, r3, #2 800e2d4: 4413 add r3, r2 800e2d6: 3b23 subs r3, #35 @ 0x23 800e2d8: 221f movs r2, #31 800e2da: fa02 f303 lsl.w r3, r2, r3 800e2de: 43db mvns r3, r3 800e2e0: 4019 ands r1, r3 800e2e2: 683b ldr r3, [r7, #0] 800e2e4: 6818 ldr r0, [r3, #0] 800e2e6: 683b ldr r3, [r7, #0] 800e2e8: 685a ldr r2, [r3, #4] 800e2ea: 4613 mov r3, r2 800e2ec: 009b lsls r3, r3, #2 800e2ee: 4413 add r3, r2 800e2f0: 3b23 subs r3, #35 @ 0x23 800e2f2: fa00 f203 lsl.w r2, r0, r3 800e2f6: 687b ldr r3, [r7, #4] 800e2f8: 681b ldr r3, [r3, #0] 800e2fa: 430a orrs r2, r1 800e2fc: 631a str r2, [r3, #48] @ 0x30 800e2fe: e01b b.n 800e338 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 800e300: 687b ldr r3, [r7, #4] 800e302: 681b ldr r3, [r3, #0] 800e304: 6ad9 ldr r1, [r3, #44] @ 0x2c 800e306: 683b ldr r3, [r7, #0] 800e308: 685a ldr r2, [r3, #4] 800e30a: 4613 mov r3, r2 800e30c: 009b lsls r3, r3, #2 800e30e: 4413 add r3, r2 800e310: 3b41 subs r3, #65 @ 0x41 800e312: 221f movs r2, #31 800e314: fa02 f303 lsl.w r3, r2, r3 800e318: 43db mvns r3, r3 800e31a: 4019 ands r1, r3 800e31c: 683b ldr r3, [r7, #0] 800e31e: 6818 ldr r0, [r3, #0] 800e320: 683b ldr r3, [r7, #0] 800e322: 685a ldr r2, [r3, #4] 800e324: 4613 mov r3, r2 800e326: 009b lsls r3, r3, #2 800e328: 4413 add r3, r2 800e32a: 3b41 subs r3, #65 @ 0x41 800e32c: fa00 f203 lsl.w r2, r0, r3 800e330: 687b ldr r3, [r7, #4] 800e332: 681b ldr r3, [r3, #0] 800e334: 430a orrs r2, r1 800e336: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 800e338: 683b ldr r3, [r7, #0] 800e33a: 681b ldr r3, [r3, #0] 800e33c: 2b09 cmp r3, #9 800e33e: d91c bls.n 800e37a { MODIFY_REG(hadc->Instance->SMPR1 , 800e340: 687b ldr r3, [r7, #4] 800e342: 681b ldr r3, [r3, #0] 800e344: 68d9 ldr r1, [r3, #12] 800e346: 683b ldr r3, [r7, #0] 800e348: 681a ldr r2, [r3, #0] 800e34a: 4613 mov r3, r2 800e34c: 005b lsls r3, r3, #1 800e34e: 4413 add r3, r2 800e350: 3b1e subs r3, #30 800e352: 2207 movs r2, #7 800e354: fa02 f303 lsl.w r3, r2, r3 800e358: 43db mvns r3, r3 800e35a: 4019 ands r1, r3 800e35c: 683b ldr r3, [r7, #0] 800e35e: 6898 ldr r0, [r3, #8] 800e360: 683b ldr r3, [r7, #0] 800e362: 681a ldr r2, [r3, #0] 800e364: 4613 mov r3, r2 800e366: 005b lsls r3, r3, #1 800e368: 4413 add r3, r2 800e36a: 3b1e subs r3, #30 800e36c: fa00 f203 lsl.w r2, r0, r3 800e370: 687b ldr r3, [r7, #4] 800e372: 681b ldr r3, [r3, #0] 800e374: 430a orrs r2, r1 800e376: 60da str r2, [r3, #12] 800e378: e019 b.n 800e3ae ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 800e37a: 687b ldr r3, [r7, #4] 800e37c: 681b ldr r3, [r3, #0] 800e37e: 6919 ldr r1, [r3, #16] 800e380: 683b ldr r3, [r7, #0] 800e382: 681a ldr r2, [r3, #0] 800e384: 4613 mov r3, r2 800e386: 005b lsls r3, r3, #1 800e388: 4413 add r3, r2 800e38a: 2207 movs r2, #7 800e38c: fa02 f303 lsl.w r3, r2, r3 800e390: 43db mvns r3, r3 800e392: 4019 ands r1, r3 800e394: 683b ldr r3, [r7, #0] 800e396: 6898 ldr r0, [r3, #8] 800e398: 683b ldr r3, [r7, #0] 800e39a: 681a ldr r2, [r3, #0] 800e39c: 4613 mov r3, r2 800e39e: 005b lsls r3, r3, #1 800e3a0: 4413 add r3, r2 800e3a2: fa00 f203 lsl.w r2, r0, r3 800e3a6: 687b ldr r3, [r7, #4] 800e3a8: 681b ldr r3, [r3, #0] 800e3aa: 430a orrs r2, r1 800e3ac: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800e3ae: 683b ldr r3, [r7, #0] 800e3b0: 681b ldr r3, [r3, #0] 800e3b2: 2b10 cmp r3, #16 800e3b4: d003 beq.n 800e3be (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 800e3b6: 683b ldr r3, [r7, #0] 800e3b8: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800e3ba: 2b11 cmp r3, #17 800e3bc: d132 bne.n 800e424 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 800e3be: 687b ldr r3, [r7, #4] 800e3c0: 681b ldr r3, [r3, #0] 800e3c2: 4a1d ldr r2, [pc, #116] @ (800e438 ) 800e3c4: 4293 cmp r3, r2 800e3c6: d125 bne.n 800e414 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 800e3c8: 687b ldr r3, [r7, #4] 800e3ca: 681b ldr r3, [r3, #0] 800e3cc: 689b ldr r3, [r3, #8] 800e3ce: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800e3d2: 2b00 cmp r3, #0 800e3d4: d126 bne.n 800e424 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 800e3d6: 687b ldr r3, [r7, #4] 800e3d8: 681b ldr r3, [r3, #0] 800e3da: 689a ldr r2, [r3, #8] 800e3dc: 687b ldr r3, [r7, #4] 800e3de: 681b ldr r3, [r3, #0] 800e3e0: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 800e3e4: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 800e3e6: 683b ldr r3, [r7, #0] 800e3e8: 681b ldr r3, [r3, #0] 800e3ea: 2b10 cmp r3, #16 800e3ec: d11a bne.n 800e424 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 800e3ee: 4b13 ldr r3, [pc, #76] @ (800e43c ) 800e3f0: 681b ldr r3, [r3, #0] 800e3f2: 4a13 ldr r2, [pc, #76] @ (800e440 ) 800e3f4: fba2 2303 umull r2, r3, r2, r3 800e3f8: 0c9a lsrs r2, r3, #18 800e3fa: 4613 mov r3, r2 800e3fc: 009b lsls r3, r3, #2 800e3fe: 4413 add r3, r2 800e400: 005b lsls r3, r3, #1 800e402: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e404: e002 b.n 800e40c { wait_loop_index--; 800e406: 68bb ldr r3, [r7, #8] 800e408: 3b01 subs r3, #1 800e40a: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e40c: 68bb ldr r3, [r7, #8] 800e40e: 2b00 cmp r3, #0 800e410: d1f9 bne.n 800e406 800e412: e007 b.n 800e424 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800e414: 687b ldr r3, [r7, #4] 800e416: 6a9b ldr r3, [r3, #40] @ 0x28 800e418: f043 0220 orr.w r2, r3, #32 800e41c: 687b ldr r3, [r7, #4] 800e41e: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800e420: 2301 movs r3, #1 800e422: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 800e424: 687b ldr r3, [r7, #4] 800e426: 2200 movs r2, #0 800e428: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800e42c: 7bfb ldrb r3, [r7, #15] } 800e42e: 4618 mov r0, r3 800e430: 3714 adds r7, #20 800e432: 46bd mov sp, r7 800e434: bc80 pop {r7} 800e436: 4770 bx lr 800e438: 40012400 .word 0x40012400 800e43c: 2000006c .word 0x2000006c 800e440: 431bde83 .word 0x431bde83 0800e444 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 800e444: b580 push {r7, lr} 800e446: b084 sub sp, #16 800e448: af00 add r7, sp, #0 800e44a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800e44c: 2300 movs r3, #0 800e44e: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 800e450: 2300 movs r3, #0 800e452: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 800e454: 687b ldr r3, [r7, #4] 800e456: 681b ldr r3, [r3, #0] 800e458: 689b ldr r3, [r3, #8] 800e45a: f003 0301 and.w r3, r3, #1 800e45e: 2b01 cmp r3, #1 800e460: d040 beq.n 800e4e4 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 800e462: 687b ldr r3, [r7, #4] 800e464: 681b ldr r3, [r3, #0] 800e466: 689a ldr r2, [r3, #8] 800e468: 687b ldr r3, [r7, #4] 800e46a: 681b ldr r3, [r3, #0] 800e46c: f042 0201 orr.w r2, r2, #1 800e470: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 800e472: 4b1f ldr r3, [pc, #124] @ (800e4f0 ) 800e474: 681b ldr r3, [r3, #0] 800e476: 4a1f ldr r2, [pc, #124] @ (800e4f4 ) 800e478: fba2 2303 umull r2, r3, r2, r3 800e47c: 0c9b lsrs r3, r3, #18 800e47e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e480: e002 b.n 800e488 { wait_loop_index--; 800e482: 68bb ldr r3, [r7, #8] 800e484: 3b01 subs r3, #1 800e486: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e488: 68bb ldr r3, [r7, #8] 800e48a: 2b00 cmp r3, #0 800e48c: d1f9 bne.n 800e482 } /* Get tick count */ tickstart = HAL_GetTick(); 800e48e: f7ff fc23 bl 800dcd8 800e492: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 800e494: e01f b.n 800e4d6 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 800e496: f7ff fc1f bl 800dcd8 800e49a: 4602 mov r2, r0 800e49c: 68fb ldr r3, [r7, #12] 800e49e: 1ad3 subs r3, r2, r3 800e4a0: 2b02 cmp r3, #2 800e4a2: d918 bls.n 800e4d6 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 800e4a4: 687b ldr r3, [r7, #4] 800e4a6: 681b ldr r3, [r3, #0] 800e4a8: 689b ldr r3, [r3, #8] 800e4aa: f003 0301 and.w r3, r3, #1 800e4ae: 2b01 cmp r3, #1 800e4b0: d011 beq.n 800e4d6 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800e4b2: 687b ldr r3, [r7, #4] 800e4b4: 6a9b ldr r3, [r3, #40] @ 0x28 800e4b6: f043 0210 orr.w r2, r3, #16 800e4ba: 687b ldr r3, [r7, #4] 800e4bc: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e4be: 687b ldr r3, [r7, #4] 800e4c0: 6adb ldr r3, [r3, #44] @ 0x2c 800e4c2: f043 0201 orr.w r2, r3, #1 800e4c6: 687b ldr r3, [r7, #4] 800e4c8: 62da str r2, [r3, #44] @ 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 800e4ca: 687b ldr r3, [r7, #4] 800e4cc: 2200 movs r2, #0 800e4ce: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e4d2: 2301 movs r3, #1 800e4d4: e007 b.n 800e4e6 while(ADC_IS_ENABLE(hadc) == RESET) 800e4d6: 687b ldr r3, [r7, #4] 800e4d8: 681b ldr r3, [r3, #0] 800e4da: 689b ldr r3, [r3, #8] 800e4dc: f003 0301 and.w r3, r3, #1 800e4e0: 2b01 cmp r3, #1 800e4e2: d1d8 bne.n 800e496 } } } /* Return HAL status */ return HAL_OK; 800e4e4: 2300 movs r3, #0 } 800e4e6: 4618 mov r0, r3 800e4e8: 3710 adds r7, #16 800e4ea: 46bd mov sp, r7 800e4ec: bd80 pop {r7, pc} 800e4ee: bf00 nop 800e4f0: 2000006c .word 0x2000006c 800e4f4: 431bde83 .word 0x431bde83 0800e4f8 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 800e4f8: b580 push {r7, lr} 800e4fa: b084 sub sp, #16 800e4fc: af00 add r7, sp, #0 800e4fe: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800e500: 2300 movs r3, #0 800e502: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 800e504: 687b ldr r3, [r7, #4] 800e506: 681b ldr r3, [r3, #0] 800e508: 689b ldr r3, [r3, #8] 800e50a: f003 0301 and.w r3, r3, #1 800e50e: 2b01 cmp r3, #1 800e510: d12e bne.n 800e570 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 800e512: 687b ldr r3, [r7, #4] 800e514: 681b ldr r3, [r3, #0] 800e516: 689a ldr r2, [r3, #8] 800e518: 687b ldr r3, [r7, #4] 800e51a: 681b ldr r3, [r3, #0] 800e51c: f022 0201 bic.w r2, r2, #1 800e520: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 800e522: f7ff fbd9 bl 800dcd8 800e526: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 800e528: e01b b.n 800e562 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800e52a: f7ff fbd5 bl 800dcd8 800e52e: 4602 mov r2, r0 800e530: 68fb ldr r3, [r7, #12] 800e532: 1ad3 subs r3, r2, r3 800e534: 2b02 cmp r3, #2 800e536: d914 bls.n 800e562 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 800e538: 687b ldr r3, [r7, #4] 800e53a: 681b ldr r3, [r3, #0] 800e53c: 689b ldr r3, [r3, #8] 800e53e: f003 0301 and.w r3, r3, #1 800e542: 2b01 cmp r3, #1 800e544: d10d bne.n 800e562 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800e546: 687b ldr r3, [r7, #4] 800e548: 6a9b ldr r3, [r3, #40] @ 0x28 800e54a: f043 0210 orr.w r2, r3, #16 800e54e: 687b ldr r3, [r7, #4] 800e550: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e552: 687b ldr r3, [r7, #4] 800e554: 6adb ldr r3, [r3, #44] @ 0x2c 800e556: f043 0201 orr.w r2, r3, #1 800e55a: 687b ldr r3, [r7, #4] 800e55c: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 800e55e: 2301 movs r3, #1 800e560: e007 b.n 800e572 while(ADC_IS_ENABLE(hadc) != RESET) 800e562: 687b ldr r3, [r7, #4] 800e564: 681b ldr r3, [r3, #0] 800e566: 689b ldr r3, [r3, #8] 800e568: f003 0301 and.w r3, r3, #1 800e56c: 2b01 cmp r3, #1 800e56e: d0dc beq.n 800e52a } } } /* Return HAL status */ return HAL_OK; 800e570: 2300 movs r3, #0 } 800e572: 4618 mov r0, r3 800e574: 3710 adds r7, #16 800e576: 46bd mov sp, r7 800e578: bd80 pop {r7, pc} 0800e57a : * @brief DMA transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 800e57a: b580 push {r7, lr} 800e57c: b084 sub sp, #16 800e57e: af00 add r7, sp, #0 800e580: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800e582: 687b ldr r3, [r7, #4] 800e584: 6a5b ldr r3, [r3, #36] @ 0x24 800e586: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) 800e588: 68fb ldr r3, [r7, #12] 800e58a: 6a9b ldr r3, [r3, #40] @ 0x28 800e58c: f003 0350 and.w r3, r3, #80 @ 0x50 800e590: 2b00 cmp r3, #0 800e592: d127 bne.n 800e5e4 { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800e594: 68fb ldr r3, [r7, #12] 800e596: 6a9b ldr r3, [r3, #40] @ 0x28 800e598: f443 7200 orr.w r2, r3, #512 @ 0x200 800e59c: 68fb ldr r3, [r7, #12] 800e59e: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e5a0: 68fb ldr r3, [r7, #12] 800e5a2: 681b ldr r3, [r3, #0] 800e5a4: 689b ldr r3, [r3, #8] 800e5a6: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800e5aa: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e5ae: d115 bne.n 800e5dc (hadc->Init.ContinuousConvMode == DISABLE) ) 800e5b0: 68fb ldr r3, [r7, #12] 800e5b2: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e5b4: 2b00 cmp r3, #0 800e5b6: d111 bne.n 800e5dc { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800e5b8: 68fb ldr r3, [r7, #12] 800e5ba: 6a9b ldr r3, [r3, #40] @ 0x28 800e5bc: f423 7280 bic.w r2, r3, #256 @ 0x100 800e5c0: 68fb ldr r3, [r7, #12] 800e5c2: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800e5c4: 68fb ldr r3, [r7, #12] 800e5c6: 6a9b ldr r3, [r3, #40] @ 0x28 800e5c8: f403 5380 and.w r3, r3, #4096 @ 0x1000 800e5cc: 2b00 cmp r3, #0 800e5ce: d105 bne.n 800e5dc { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800e5d0: 68fb ldr r3, [r7, #12] 800e5d2: 6a9b ldr r3, [r3, #40] @ 0x28 800e5d4: f043 0201 orr.w r2, r3, #1 800e5d8: 68fb ldr r3, [r7, #12] 800e5da: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800e5dc: 68f8 ldr r0, [r7, #12] 800e5de: f7fa ffb5 bl 800954c else { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } 800e5e2: e004 b.n 800e5ee hadc->DMA_Handle->XferErrorCallback(hdma); 800e5e4: 68fb ldr r3, [r7, #12] 800e5e6: 6a1b ldr r3, [r3, #32] 800e5e8: 6b1b ldr r3, [r3, #48] @ 0x30 800e5ea: 6878 ldr r0, [r7, #4] 800e5ec: 4798 blx r3 } 800e5ee: bf00 nop 800e5f0: 3710 adds r7, #16 800e5f2: 46bd mov sp, r7 800e5f4: bd80 pop {r7, pc} 0800e5f6 : * @brief DMA half transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 800e5f6: b580 push {r7, lr} 800e5f8: b084 sub sp, #16 800e5fa: af00 add r7, sp, #0 800e5fc: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800e5fe: 687b ldr r3, [r7, #4] 800e600: 6a5b ldr r3, [r3, #36] @ 0x24 800e602: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 800e604: 68f8 ldr r0, [r7, #12] 800e606: f7ff fe0a bl 800e21e #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800e60a: bf00 nop 800e60c: 3710 adds r7, #16 800e60e: 46bd mov sp, r7 800e610: bd80 pop {r7, pc} 0800e612 : * @brief DMA error callback * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 800e612: b580 push {r7, lr} 800e614: b084 sub sp, #16 800e616: af00 add r7, sp, #0 800e618: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800e61a: 687b ldr r3, [r7, #4] 800e61c: 6a5b ldr r3, [r3, #36] @ 0x24 800e61e: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 800e620: 68fb ldr r3, [r7, #12] 800e622: 6a9b ldr r3, [r3, #40] @ 0x28 800e624: f043 0240 orr.w r2, r3, #64 @ 0x40 800e628: 68fb ldr r3, [r7, #12] 800e62a: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 800e62c: 68fb ldr r3, [r7, #12] 800e62e: 6adb ldr r3, [r3, #44] @ 0x2c 800e630: f043 0204 orr.w r2, r3, #4 800e634: 68fb ldr r3, [r7, #12] 800e636: 62da str r2, [r3, #44] @ 0x2c /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 800e638: 68f8 ldr r0, [r7, #12] 800e63a: f7ff fe02 bl 800e242 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800e63e: bf00 nop 800e640: 3710 adds r7, #16 800e642: 46bd mov sp, r7 800e644: bd80 pop {r7, pc} ... 0800e648 : * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { 800e648: b590 push {r4, r7, lr} 800e64a: b087 sub sp, #28 800e64c: af00 add r7, sp, #0 800e64e: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e650: 2300 movs r3, #0 800e652: 75fb strb r3, [r7, #23] uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; 800e654: 2300 movs r3, #0 800e656: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800e658: 687b ldr r3, [r7, #4] 800e65a: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e65e: 2b01 cmp r3, #1 800e660: d101 bne.n 800e666 800e662: 2302 movs r3, #2 800e664: e097 b.n 800e796 800e666: 687b ldr r3, [r7, #4] 800e668: 2201 movs r2, #1 800e66a: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* 1. Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800e66e: 6878 ldr r0, [r7, #4] 800e670: f7ff ff42 bl 800e4f8 800e674: 4603 mov r3, r0 800e676: 75fb strb r3, [r7, #23] /* 2. Calibration prerequisite delay before starting the calibration. */ /* - ADC must be enabled for at least two ADC clock cycles */ tmp_hal_status = ADC_Enable(hadc); 800e678: 6878 ldr r0, [r7, #4] 800e67a: f7ff fee3 bl 800e444 800e67e: 4603 mov r3, r0 800e680: 75fb strb r3, [r7, #23] /* Check if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800e682: 7dfb ldrb r3, [r7, #23] 800e684: 2b00 cmp r3, #0 800e686: f040 8081 bne.w 800e78c { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e68a: 687b ldr r3, [r7, #4] 800e68c: 6a9b ldr r3, [r3, #40] @ 0x28 800e68e: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800e692: f023 0302 bic.w r3, r3, #2 800e696: f043 0202 orr.w r2, r3, #2 800e69a: 687b ldr r3, [r7, #4] 800e69c: 629a str r2, [r3, #40] @ 0x28 /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 800e69e: 4b40 ldr r3, [pc, #256] @ (800e7a0 ) 800e6a0: 681c ldr r4, [r3, #0] 800e6a2: 2002 movs r0, #2 800e6a4: f002 fec6 bl 8011434 800e6a8: 4603 mov r3, r0 800e6aa: fbb4 f3f3 udiv r3, r4, r3 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 800e6ae: 005b lsls r3, r3, #1 wait_loop_index = ((SystemCoreClock 800e6b0: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800e6b2: e002 b.n 800e6ba { wait_loop_index--; 800e6b4: 68fb ldr r3, [r7, #12] 800e6b6: 3b01 subs r3, #1 800e6b8: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800e6ba: 68fb ldr r3, [r7, #12] 800e6bc: 2b00 cmp r3, #0 800e6be: d1f9 bne.n 800e6b4 } /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 800e6c0: 687b ldr r3, [r7, #4] 800e6c2: 681b ldr r3, [r3, #0] 800e6c4: 689a ldr r2, [r3, #8] 800e6c6: 687b ldr r3, [r7, #4] 800e6c8: 681b ldr r3, [r3, #0] 800e6ca: f042 0208 orr.w r2, r2, #8 800e6ce: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800e6d0: f7ff fb02 bl 800dcd8 800e6d4: 6138 str r0, [r7, #16] /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800e6d6: e01b b.n 800e710 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800e6d8: f7ff fafe bl 800dcd8 800e6dc: 4602 mov r2, r0 800e6de: 693b ldr r3, [r7, #16] 800e6e0: 1ad3 subs r3, r2, r3 800e6e2: 2b0a cmp r3, #10 800e6e4: d914 bls.n 800e710 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800e6e6: 687b ldr r3, [r7, #4] 800e6e8: 681b ldr r3, [r3, #0] 800e6ea: 689b ldr r3, [r3, #8] 800e6ec: f003 0308 and.w r3, r3, #8 800e6f0: 2b00 cmp r3, #0 800e6f2: d00d beq.n 800e710 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800e6f4: 687b ldr r3, [r7, #4] 800e6f6: 6a9b ldr r3, [r3, #40] @ 0x28 800e6f8: f023 0312 bic.w r3, r3, #18 800e6fc: f043 0210 orr.w r2, r3, #16 800e700: 687b ldr r3, [r7, #4] 800e702: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800e704: 687b ldr r3, [r7, #4] 800e706: 2200 movs r2, #0 800e708: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e70c: 2301 movs r3, #1 800e70e: e042 b.n 800e796 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800e710: 687b ldr r3, [r7, #4] 800e712: 681b ldr r3, [r3, #0] 800e714: 689b ldr r3, [r3, #8] 800e716: f003 0308 and.w r3, r3, #8 800e71a: 2b00 cmp r3, #0 800e71c: d1dc bne.n 800e6d8 } } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 800e71e: 687b ldr r3, [r7, #4] 800e720: 681b ldr r3, [r3, #0] 800e722: 689a ldr r2, [r3, #8] 800e724: 687b ldr r3, [r7, #4] 800e726: 681b ldr r3, [r3, #0] 800e728: f042 0204 orr.w r2, r2, #4 800e72c: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800e72e: f7ff fad3 bl 800dcd8 800e732: 6138 str r0, [r7, #16] /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800e734: e01b b.n 800e76e { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800e736: f7ff facf bl 800dcd8 800e73a: 4602 mov r2, r0 800e73c: 693b ldr r3, [r7, #16] 800e73e: 1ad3 subs r3, r2, r3 800e740: 2b0a cmp r3, #10 800e742: d914 bls.n 800e76e { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800e744: 687b ldr r3, [r7, #4] 800e746: 681b ldr r3, [r3, #0] 800e748: 689b ldr r3, [r3, #8] 800e74a: f003 0304 and.w r3, r3, #4 800e74e: 2b00 cmp r3, #0 800e750: d00d beq.n 800e76e { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800e752: 687b ldr r3, [r7, #4] 800e754: 6a9b ldr r3, [r3, #40] @ 0x28 800e756: f023 0312 bic.w r3, r3, #18 800e75a: f043 0210 orr.w r2, r3, #16 800e75e: 687b ldr r3, [r7, #4] 800e760: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800e762: 687b ldr r3, [r7, #4] 800e764: 2200 movs r2, #0 800e766: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e76a: 2301 movs r3, #1 800e76c: e013 b.n 800e796 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800e76e: 687b ldr r3, [r7, #4] 800e770: 681b ldr r3, [r3, #0] 800e772: 689b ldr r3, [r3, #8] 800e774: f003 0304 and.w r3, r3, #4 800e778: 2b00 cmp r3, #0 800e77a: d1dc bne.n 800e736 } } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e77c: 687b ldr r3, [r7, #4] 800e77e: 6a9b ldr r3, [r3, #40] @ 0x28 800e780: f023 0303 bic.w r3, r3, #3 800e784: f043 0201 orr.w r2, r3, #1 800e788: 687b ldr r3, [r7, #4] 800e78a: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 800e78c: 687b ldr r3, [r7, #4] 800e78e: 2200 movs r2, #0 800e790: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800e794: 7dfb ldrb r3, [r7, #23] } 800e796: 4618 mov r0, r3 800e798: 371c adds r7, #28 800e79a: 46bd mov sp, r7 800e79c: bd90 pop {r4, r7, pc} 800e79e: bf00 nop 800e7a0: 2000006c .word 0x2000006c 0800e7a4 : * @brief Injected conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { 800e7a4: b480 push {r7} 800e7a6: b083 sub sp, #12 800e7a8: af00 add r7, sp, #0 800e7aa: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } 800e7ac: bf00 nop 800e7ae: 370c adds r7, #12 800e7b0: 46bd mov sp, r7 800e7b2: bc80 pop {r7} 800e7b4: 4770 bx lr 0800e7b6 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { 800e7b6: b580 push {r7, lr} 800e7b8: b084 sub sp, #16 800e7ba: af00 add r7, sp, #0 800e7bc: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) 800e7be: 687b ldr r3, [r7, #4] 800e7c0: 2b00 cmp r3, #0 800e7c2: d101 bne.n 800e7c8 { return HAL_ERROR; 800e7c4: 2301 movs r3, #1 800e7c6: e0ed b.n 800e9a4 /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) 800e7c8: 687b ldr r3, [r7, #4] 800e7ca: f893 3020 ldrb.w r3, [r3, #32] 800e7ce: b2db uxtb r3, r3 800e7d0: 2b00 cmp r3, #0 800e7d2: d102 bne.n 800e7da { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); 800e7d4: 6878 ldr r0, [r7, #4] 800e7d6: f7fb fa1f bl 8009c18 } #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800e7da: 687b ldr r3, [r7, #4] 800e7dc: 681b ldr r3, [r3, #0] 800e7de: 681a ldr r2, [r3, #0] 800e7e0: 687b ldr r3, [r7, #4] 800e7e2: 681b ldr r3, [r3, #0] 800e7e4: f042 0201 orr.w r2, r2, #1 800e7e8: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800e7ea: f7ff fa75 bl 800dcd8 800e7ee: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800e7f0: e012 b.n 800e818 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800e7f2: f7ff fa71 bl 800dcd8 800e7f6: 4602 mov r2, r0 800e7f8: 68fb ldr r3, [r7, #12] 800e7fa: 1ad3 subs r3, r2, r3 800e7fc: 2b0a cmp r3, #10 800e7fe: d90b bls.n 800e818 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800e800: 687b ldr r3, [r7, #4] 800e802: 6a5b ldr r3, [r3, #36] @ 0x24 800e804: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800e808: 687b ldr r3, [r7, #4] 800e80a: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800e80c: 687b ldr r3, [r7, #4] 800e80e: 2205 movs r2, #5 800e810: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800e814: 2301 movs r3, #1 800e816: e0c5 b.n 800e9a4 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800e818: 687b ldr r3, [r7, #4] 800e81a: 681b ldr r3, [r3, #0] 800e81c: 685b ldr r3, [r3, #4] 800e81e: f003 0301 and.w r3, r3, #1 800e822: 2b00 cmp r3, #0 800e824: d0e5 beq.n 800e7f2 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800e826: 687b ldr r3, [r7, #4] 800e828: 681b ldr r3, [r3, #0] 800e82a: 681a ldr r2, [r3, #0] 800e82c: 687b ldr r3, [r7, #4] 800e82e: 681b ldr r3, [r3, #0] 800e830: f022 0202 bic.w r2, r2, #2 800e834: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800e836: f7ff fa4f bl 800dcd8 800e83a: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800e83c: e012 b.n 800e864 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800e83e: f7ff fa4b bl 800dcd8 800e842: 4602 mov r2, r0 800e844: 68fb ldr r3, [r7, #12] 800e846: 1ad3 subs r3, r2, r3 800e848: 2b0a cmp r3, #10 800e84a: d90b bls.n 800e864 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800e84c: 687b ldr r3, [r7, #4] 800e84e: 6a5b ldr r3, [r3, #36] @ 0x24 800e850: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800e854: 687b ldr r3, [r7, #4] 800e856: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800e858: 687b ldr r3, [r7, #4] 800e85a: 2205 movs r2, #5 800e85c: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800e860: 2301 movs r3, #1 800e862: e09f b.n 800e9a4 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800e864: 687b ldr r3, [r7, #4] 800e866: 681b ldr r3, [r3, #0] 800e868: 685b ldr r3, [r3, #4] 800e86a: f003 0302 and.w r3, r3, #2 800e86e: 2b00 cmp r3, #0 800e870: d1e5 bne.n 800e83e } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) 800e872: 687b ldr r3, [r7, #4] 800e874: 7e1b ldrb r3, [r3, #24] 800e876: 2b01 cmp r3, #1 800e878: d108 bne.n 800e88c { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800e87a: 687b ldr r3, [r7, #4] 800e87c: 681b ldr r3, [r3, #0] 800e87e: 681a ldr r2, [r3, #0] 800e880: 687b ldr r3, [r7, #4] 800e882: 681b ldr r3, [r3, #0] 800e884: f042 0280 orr.w r2, r2, #128 @ 0x80 800e888: 601a str r2, [r3, #0] 800e88a: e007 b.n 800e89c } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800e88c: 687b ldr r3, [r7, #4] 800e88e: 681b ldr r3, [r3, #0] 800e890: 681a ldr r2, [r3, #0] 800e892: 687b ldr r3, [r7, #4] 800e894: 681b ldr r3, [r3, #0] 800e896: f022 0280 bic.w r2, r2, #128 @ 0x80 800e89a: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) 800e89c: 687b ldr r3, [r7, #4] 800e89e: 7e5b ldrb r3, [r3, #25] 800e8a0: 2b01 cmp r3, #1 800e8a2: d108 bne.n 800e8b6 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800e8a4: 687b ldr r3, [r7, #4] 800e8a6: 681b ldr r3, [r3, #0] 800e8a8: 681a ldr r2, [r3, #0] 800e8aa: 687b ldr r3, [r7, #4] 800e8ac: 681b ldr r3, [r3, #0] 800e8ae: f042 0240 orr.w r2, r2, #64 @ 0x40 800e8b2: 601a str r2, [r3, #0] 800e8b4: e007 b.n 800e8c6 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800e8b6: 687b ldr r3, [r7, #4] 800e8b8: 681b ldr r3, [r3, #0] 800e8ba: 681a ldr r2, [r3, #0] 800e8bc: 687b ldr r3, [r7, #4] 800e8be: 681b ldr r3, [r3, #0] 800e8c0: f022 0240 bic.w r2, r2, #64 @ 0x40 800e8c4: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) 800e8c6: 687b ldr r3, [r7, #4] 800e8c8: 7e9b ldrb r3, [r3, #26] 800e8ca: 2b01 cmp r3, #1 800e8cc: d108 bne.n 800e8e0 { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800e8ce: 687b ldr r3, [r7, #4] 800e8d0: 681b ldr r3, [r3, #0] 800e8d2: 681a ldr r2, [r3, #0] 800e8d4: 687b ldr r3, [r7, #4] 800e8d6: 681b ldr r3, [r3, #0] 800e8d8: f042 0220 orr.w r2, r2, #32 800e8dc: 601a str r2, [r3, #0] 800e8de: e007 b.n 800e8f0 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800e8e0: 687b ldr r3, [r7, #4] 800e8e2: 681b ldr r3, [r3, #0] 800e8e4: 681a ldr r2, [r3, #0] 800e8e6: 687b ldr r3, [r7, #4] 800e8e8: 681b ldr r3, [r3, #0] 800e8ea: f022 0220 bic.w r2, r2, #32 800e8ee: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) 800e8f0: 687b ldr r3, [r7, #4] 800e8f2: 7edb ldrb r3, [r3, #27] 800e8f4: 2b01 cmp r3, #1 800e8f6: d108 bne.n 800e90a { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800e8f8: 687b ldr r3, [r7, #4] 800e8fa: 681b ldr r3, [r3, #0] 800e8fc: 681a ldr r2, [r3, #0] 800e8fe: 687b ldr r3, [r7, #4] 800e900: 681b ldr r3, [r3, #0] 800e902: f022 0210 bic.w r2, r2, #16 800e906: 601a str r2, [r3, #0] 800e908: e007 b.n 800e91a } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800e90a: 687b ldr r3, [r7, #4] 800e90c: 681b ldr r3, [r3, #0] 800e90e: 681a ldr r2, [r3, #0] 800e910: 687b ldr r3, [r7, #4] 800e912: 681b ldr r3, [r3, #0] 800e914: f042 0210 orr.w r2, r2, #16 800e918: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) 800e91a: 687b ldr r3, [r7, #4] 800e91c: 7f1b ldrb r3, [r3, #28] 800e91e: 2b01 cmp r3, #1 800e920: d108 bne.n 800e934 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800e922: 687b ldr r3, [r7, #4] 800e924: 681b ldr r3, [r3, #0] 800e926: 681a ldr r2, [r3, #0] 800e928: 687b ldr r3, [r7, #4] 800e92a: 681b ldr r3, [r3, #0] 800e92c: f042 0208 orr.w r2, r2, #8 800e930: 601a str r2, [r3, #0] 800e932: e007 b.n 800e944 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800e934: 687b ldr r3, [r7, #4] 800e936: 681b ldr r3, [r3, #0] 800e938: 681a ldr r2, [r3, #0] 800e93a: 687b ldr r3, [r7, #4] 800e93c: 681b ldr r3, [r3, #0] 800e93e: f022 0208 bic.w r2, r2, #8 800e942: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) 800e944: 687b ldr r3, [r7, #4] 800e946: 7f5b ldrb r3, [r3, #29] 800e948: 2b01 cmp r3, #1 800e94a: d108 bne.n 800e95e { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800e94c: 687b ldr r3, [r7, #4] 800e94e: 681b ldr r3, [r3, #0] 800e950: 681a ldr r2, [r3, #0] 800e952: 687b ldr r3, [r7, #4] 800e954: 681b ldr r3, [r3, #0] 800e956: f042 0204 orr.w r2, r2, #4 800e95a: 601a str r2, [r3, #0] 800e95c: e007 b.n 800e96e } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800e95e: 687b ldr r3, [r7, #4] 800e960: 681b ldr r3, [r3, #0] 800e962: 681a ldr r2, [r3, #0] 800e964: 687b ldr r3, [r7, #4] 800e966: 681b ldr r3, [r3, #0] 800e968: f022 0204 bic.w r2, r2, #4 800e96c: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | 800e96e: 687b ldr r3, [r7, #4] 800e970: 689a ldr r2, [r3, #8] 800e972: 687b ldr r3, [r7, #4] 800e974: 68db ldr r3, [r3, #12] 800e976: 431a orrs r2, r3 800e978: 687b ldr r3, [r7, #4] 800e97a: 691b ldr r3, [r3, #16] 800e97c: 431a orrs r2, r3 800e97e: 687b ldr r3, [r7, #4] 800e980: 695b ldr r3, [r3, #20] 800e982: ea42 0103 orr.w r1, r2, r3 800e986: 687b ldr r3, [r7, #4] 800e988: 685b ldr r3, [r3, #4] 800e98a: 1e5a subs r2, r3, #1 800e98c: 687b ldr r3, [r7, #4] 800e98e: 681b ldr r3, [r3, #0] 800e990: 430a orrs r2, r1 800e992: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800e994: 687b ldr r3, [r7, #4] 800e996: 2200 movs r2, #0 800e998: 625a str r2, [r3, #36] @ 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; 800e99a: 687b ldr r3, [r7, #4] 800e99c: 2201 movs r2, #1 800e99e: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800e9a2: 2300 movs r3, #0 } 800e9a4: 4618 mov r0, r3 800e9a6: 3710 adds r7, #16 800e9a8: 46bd mov sp, r7 800e9aa: bd80 pop {r7, pc} 0800e9ac : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { 800e9ac: b480 push {r7} 800e9ae: b087 sub sp, #28 800e9b0: af00 add r7, sp, #0 800e9b2: 6078 str r0, [r7, #4] 800e9b4: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; 800e9b6: 687b ldr r3, [r7, #4] 800e9b8: 681b ldr r3, [r3, #0] 800e9ba: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; 800e9bc: 687b ldr r3, [r7, #4] 800e9be: f893 3020 ldrb.w r3, [r3, #32] 800e9c2: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || 800e9c4: 7cfb ldrb r3, [r7, #19] 800e9c6: 2b01 cmp r3, #1 800e9c8: d003 beq.n 800e9d2 800e9ca: 7cfb ldrb r3, [r7, #19] 800e9cc: 2b02 cmp r3, #2 800e9ce: f040 80be bne.w 800eb4e assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); #if defined(CAN2) /* CAN1 and CAN2 are dual instances with 28 common filters banks */ /* Select master instance to access the filter banks */ can_ip = CAN1; 800e9d2: 4b65 ldr r3, [pc, #404] @ (800eb68 ) 800e9d4: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); #endif /* CAN3 */ /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); 800e9d6: 697b ldr r3, [r7, #20] 800e9d8: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800e9dc: f043 0201 orr.w r2, r3, #1 800e9e0: 697b ldr r3, [r7, #20] 800e9e2: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #if defined(CAN2) /* Select the start filter number of CAN2 slave instance */ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); 800e9e6: 697b ldr r3, [r7, #20] 800e9e8: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800e9ec: f423 527c bic.w r2, r3, #16128 @ 0x3f00 800e9f0: 697b ldr r3, [r7, #20] 800e9f2: f8c3 2200 str.w r2, [r3, #512] @ 0x200 SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); 800e9f6: 697b ldr r3, [r7, #20] 800e9f8: f8d3 2200 ldr.w r2, [r3, #512] @ 0x200 800e9fc: 683b ldr r3, [r7, #0] 800e9fe: 6a5b ldr r3, [r3, #36] @ 0x24 800ea00: 021b lsls r3, r3, #8 800ea02: 431a orrs r2, r3 800ea04: 697b ldr r3, [r7, #20] 800ea06: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #endif /* CAN3 */ /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); 800ea0a: 683b ldr r3, [r7, #0] 800ea0c: 695b ldr r3, [r3, #20] 800ea0e: f003 031f and.w r3, r3, #31 800ea12: 2201 movs r2, #1 800ea14: fa02 f303 lsl.w r3, r2, r3 800ea18: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); 800ea1a: 697b ldr r3, [r7, #20] 800ea1c: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800ea20: 68fb ldr r3, [r7, #12] 800ea22: 43db mvns r3, r3 800ea24: 401a ands r2, r3 800ea26: 697b ldr r3, [r7, #20] 800ea28: f8c3 221c str.w r2, [r3, #540] @ 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) 800ea2c: 683b ldr r3, [r7, #0] 800ea2e: 69db ldr r3, [r3, #28] 800ea30: 2b00 cmp r3, #0 800ea32: d123 bne.n 800ea7c { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); 800ea34: 697b ldr r3, [r7, #20] 800ea36: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800ea3a: 68fb ldr r3, [r7, #12] 800ea3c: 43db mvns r3, r3 800ea3e: 401a ands r2, r3 800ea40: 697b ldr r3, [r7, #20] 800ea42: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800ea46: 683b ldr r3, [r7, #0] 800ea48: 68db ldr r3, [r3, #12] 800ea4a: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800ea4c: 683b ldr r3, [r7, #0] 800ea4e: 685b ldr r3, [r3, #4] 800ea50: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800ea52: 683a ldr r2, [r7, #0] 800ea54: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800ea56: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800ea58: 697b ldr r3, [r7, #20] 800ea5a: 3248 adds r2, #72 @ 0x48 800ea5c: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800ea60: 683b ldr r3, [r7, #0] 800ea62: 689b ldr r3, [r3, #8] 800ea64: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); 800ea66: 683b ldr r3, [r7, #0] 800ea68: 681b ldr r3, [r3, #0] 800ea6a: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800ea6c: 683b ldr r3, [r7, #0] 800ea6e: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800ea70: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800ea72: 6979 ldr r1, [r7, #20] 800ea74: 3348 adds r3, #72 @ 0x48 800ea76: 00db lsls r3, r3, #3 800ea78: 440b add r3, r1 800ea7a: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) 800ea7c: 683b ldr r3, [r7, #0] 800ea7e: 69db ldr r3, [r3, #28] 800ea80: 2b01 cmp r3, #1 800ea82: d122 bne.n 800eaca { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); 800ea84: 697b ldr r3, [r7, #20] 800ea86: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800ea8a: 68fb ldr r3, [r7, #12] 800ea8c: 431a orrs r2, r3 800ea8e: 697b ldr r3, [r7, #20] 800ea90: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800ea94: 683b ldr r3, [r7, #0] 800ea96: 681b ldr r3, [r3, #0] 800ea98: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800ea9a: 683b ldr r3, [r7, #0] 800ea9c: 685b ldr r3, [r3, #4] 800ea9e: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800eaa0: 683a ldr r2, [r7, #0] 800eaa2: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800eaa4: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800eaa6: 697b ldr r3, [r7, #20] 800eaa8: 3248 adds r2, #72 @ 0x48 800eaaa: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800eaae: 683b ldr r3, [r7, #0] 800eab0: 689b ldr r3, [r3, #8] 800eab2: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); 800eab4: 683b ldr r3, [r7, #0] 800eab6: 68db ldr r3, [r3, #12] 800eab8: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800eaba: 683b ldr r3, [r7, #0] 800eabc: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800eabe: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800eac0: 6979 ldr r1, [r7, #20] 800eac2: 3348 adds r3, #72 @ 0x48 800eac4: 00db lsls r3, r3, #3 800eac6: 440b add r3, r1 800eac8: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) 800eaca: 683b ldr r3, [r7, #0] 800eacc: 699b ldr r3, [r3, #24] 800eace: 2b00 cmp r3, #0 800ead0: d109 bne.n 800eae6 { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); 800ead2: 697b ldr r3, [r7, #20] 800ead4: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800ead8: 68fb ldr r3, [r7, #12] 800eada: 43db mvns r3, r3 800eadc: 401a ands r2, r3 800eade: 697b ldr r3, [r7, #20] 800eae0: f8c3 2204 str.w r2, [r3, #516] @ 0x204 800eae4: e007 b.n 800eaf6 } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); 800eae6: 697b ldr r3, [r7, #20] 800eae8: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800eaec: 68fb ldr r3, [r7, #12] 800eaee: 431a orrs r2, r3 800eaf0: 697b ldr r3, [r7, #20] 800eaf2: f8c3 2204 str.w r2, [r3, #516] @ 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) 800eaf6: 683b ldr r3, [r7, #0] 800eaf8: 691b ldr r3, [r3, #16] 800eafa: 2b00 cmp r3, #0 800eafc: d109 bne.n 800eb12 { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); 800eafe: 697b ldr r3, [r7, #20] 800eb00: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800eb04: 68fb ldr r3, [r7, #12] 800eb06: 43db mvns r3, r3 800eb08: 401a ands r2, r3 800eb0a: 697b ldr r3, [r7, #20] 800eb0c: f8c3 2214 str.w r2, [r3, #532] @ 0x214 800eb10: e007 b.n 800eb22 } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); 800eb12: 697b ldr r3, [r7, #20] 800eb14: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800eb18: 68fb ldr r3, [r7, #12] 800eb1a: 431a orrs r2, r3 800eb1c: 697b ldr r3, [r7, #20] 800eb1e: f8c3 2214 str.w r2, [r3, #532] @ 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) 800eb22: 683b ldr r3, [r7, #0] 800eb24: 6a1b ldr r3, [r3, #32] 800eb26: 2b01 cmp r3, #1 800eb28: d107 bne.n 800eb3a { SET_BIT(can_ip->FA1R, filternbrbitpos); 800eb2a: 697b ldr r3, [r7, #20] 800eb2c: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800eb30: 68fb ldr r3, [r7, #12] 800eb32: 431a orrs r2, r3 800eb34: 697b ldr r3, [r7, #20] 800eb36: f8c3 221c str.w r2, [r3, #540] @ 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); 800eb3a: 697b ldr r3, [r7, #20] 800eb3c: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800eb40: f023 0201 bic.w r2, r3, #1 800eb44: 697b ldr r3, [r7, #20] 800eb46: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Return function status */ return HAL_OK; 800eb4a: 2300 movs r3, #0 800eb4c: e006 b.n 800eb5c } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800eb4e: 687b ldr r3, [r7, #4] 800eb50: 6a5b ldr r3, [r3, #36] @ 0x24 800eb52: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800eb56: 687b ldr r3, [r7, #4] 800eb58: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800eb5a: 2301 movs r3, #1 } } 800eb5c: 4618 mov r0, r3 800eb5e: 371c adds r7, #28 800eb60: 46bd mov sp, r7 800eb62: bc80 pop {r7} 800eb64: 4770 bx lr 800eb66: bf00 nop 800eb68: 40006400 .word 0x40006400 0800eb6c : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { 800eb6c: b580 push {r7, lr} 800eb6e: b084 sub sp, #16 800eb70: af00 add r7, sp, #0 800eb72: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) 800eb74: 687b ldr r3, [r7, #4] 800eb76: f893 3020 ldrb.w r3, [r3, #32] 800eb7a: b2db uxtb r3, r3 800eb7c: 2b01 cmp r3, #1 800eb7e: d12e bne.n 800ebde { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; 800eb80: 687b ldr r3, [r7, #4] 800eb82: 2202 movs r2, #2 800eb84: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800eb88: 687b ldr r3, [r7, #4] 800eb8a: 681b ldr r3, [r3, #0] 800eb8c: 681a ldr r2, [r3, #0] 800eb8e: 687b ldr r3, [r7, #4] 800eb90: 681b ldr r3, [r3, #0] 800eb92: f022 0201 bic.w r2, r2, #1 800eb96: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800eb98: f7ff f89e bl 800dcd8 800eb9c: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800eb9e: e012 b.n 800ebc6 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800eba0: f7ff f89a bl 800dcd8 800eba4: 4602 mov r2, r0 800eba6: 68fb ldr r3, [r7, #12] 800eba8: 1ad3 subs r3, r2, r3 800ebaa: 2b0a cmp r3, #10 800ebac: d90b bls.n 800ebc6 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800ebae: 687b ldr r3, [r7, #4] 800ebb0: 6a5b ldr r3, [r3, #36] @ 0x24 800ebb2: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800ebb6: 687b ldr r3, [r7, #4] 800ebb8: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800ebba: 687b ldr r3, [r7, #4] 800ebbc: 2205 movs r2, #5 800ebbe: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800ebc2: 2301 movs r3, #1 800ebc4: e012 b.n 800ebec while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800ebc6: 687b ldr r3, [r7, #4] 800ebc8: 681b ldr r3, [r3, #0] 800ebca: 685b ldr r3, [r3, #4] 800ebcc: f003 0301 and.w r3, r3, #1 800ebd0: 2b00 cmp r3, #0 800ebd2: d1e5 bne.n 800eba0 } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800ebd4: 687b ldr r3, [r7, #4] 800ebd6: 2200 movs r2, #0 800ebd8: 625a str r2, [r3, #36] @ 0x24 /* Return function status */ return HAL_OK; 800ebda: 2300 movs r3, #0 800ebdc: e006 b.n 800ebec } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; 800ebde: 687b ldr r3, [r7, #4] 800ebe0: 6a5b ldr r3, [r3, #36] @ 0x24 800ebe2: f443 2200 orr.w r2, r3, #524288 @ 0x80000 800ebe6: 687b ldr r3, [r7, #4] 800ebe8: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ebea: 2301 movs r3, #1 } } 800ebec: 4618 mov r0, r3 800ebee: 3710 adds r7, #16 800ebf0: 46bd mov sp, r7 800ebf2: bd80 pop {r7, pc} 0800ebf4 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { 800ebf4: b580 push {r7, lr} 800ebf6: b084 sub sp, #16 800ebf8: af00 add r7, sp, #0 800ebfa: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_LISTENING) 800ebfc: 687b ldr r3, [r7, #4] 800ebfe: f893 3020 ldrb.w r3, [r3, #32] 800ec02: b2db uxtb r3, r3 800ec04: 2b02 cmp r3, #2 800ec06: d133 bne.n 800ec70 { /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800ec08: 687b ldr r3, [r7, #4] 800ec0a: 681b ldr r3, [r3, #0] 800ec0c: 681a ldr r2, [r3, #0] 800ec0e: 687b ldr r3, [r7, #4] 800ec10: 681b ldr r3, [r3, #0] 800ec12: f042 0201 orr.w r2, r2, #1 800ec16: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800ec18: f7ff f85e bl 800dcd8 800ec1c: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800ec1e: e012 b.n 800ec46 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800ec20: f7ff f85a bl 800dcd8 800ec24: 4602 mov r2, r0 800ec26: 68fb ldr r3, [r7, #12] 800ec28: 1ad3 subs r3, r2, r3 800ec2a: 2b0a cmp r3, #10 800ec2c: d90b bls.n 800ec46 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800ec2e: 687b ldr r3, [r7, #4] 800ec30: 6a5b ldr r3, [r3, #36] @ 0x24 800ec32: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800ec36: 687b ldr r3, [r7, #4] 800ec38: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800ec3a: 687b ldr r3, [r7, #4] 800ec3c: 2205 movs r2, #5 800ec3e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800ec42: 2301 movs r3, #1 800ec44: e01b b.n 800ec7e while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800ec46: 687b ldr r3, [r7, #4] 800ec48: 681b ldr r3, [r3, #0] 800ec4a: 685b ldr r3, [r3, #4] 800ec4c: f003 0301 and.w r3, r3, #1 800ec50: 2b00 cmp r3, #0 800ec52: d0e5 beq.n 800ec20 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800ec54: 687b ldr r3, [r7, #4] 800ec56: 681b ldr r3, [r3, #0] 800ec58: 681a ldr r2, [r3, #0] 800ec5a: 687b ldr r3, [r7, #4] 800ec5c: 681b ldr r3, [r3, #0] 800ec5e: f022 0202 bic.w r2, r2, #2 800ec62: 601a str r2, [r3, #0] /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_READY; 800ec64: 687b ldr r3, [r7, #4] 800ec66: 2201 movs r2, #1 800ec68: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800ec6c: 2300 movs r3, #0 800ec6e: e006 b.n 800ec7e } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; 800ec70: 687b ldr r3, [r7, #4] 800ec72: 6a5b ldr r3, [r3, #36] @ 0x24 800ec74: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800ec78: 687b ldr r3, [r7, #4] 800ec7a: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ec7c: 2301 movs r3, #1 } } 800ec7e: 4618 mov r0, r3 800ec80: 3710 adds r7, #16 800ec82: 46bd mov sp, r7 800ec84: bd80 pop {r7, pc} 0800ec86 : * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, const uint8_t aData[], uint32_t *pTxMailbox) { 800ec86: b480 push {r7} 800ec88: b089 sub sp, #36 @ 0x24 800ec8a: af00 add r7, sp, #0 800ec8c: 60f8 str r0, [r7, #12] 800ec8e: 60b9 str r1, [r7, #8] 800ec90: 607a str r2, [r7, #4] 800ec92: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; 800ec94: 68fb ldr r3, [r7, #12] 800ec96: f893 3020 ldrb.w r3, [r3, #32] 800ec9a: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); 800ec9c: 68fb ldr r3, [r7, #12] 800ec9e: 681b ldr r3, [r3, #0] 800eca0: 689b ldr r3, [r3, #8] 800eca2: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || 800eca4: 7ffb ldrb r3, [r7, #31] 800eca6: 2b01 cmp r3, #1 800eca8: d003 beq.n 800ecb2 800ecaa: 7ffb ldrb r3, [r7, #31] 800ecac: 2b02 cmp r3, #2 800ecae: f040 80ad bne.w 800ee0c (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || 800ecb2: 69bb ldr r3, [r7, #24] 800ecb4: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800ecb8: 2b00 cmp r3, #0 800ecba: d10a bne.n 800ecd2 ((tsr & CAN_TSR_TME1) != 0U) || 800ecbc: 69bb ldr r3, [r7, #24] 800ecbe: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || 800ecc2: 2b00 cmp r3, #0 800ecc4: d105 bne.n 800ecd2 ((tsr & CAN_TSR_TME2) != 0U)) 800ecc6: 69bb ldr r3, [r7, #24] 800ecc8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || 800eccc: 2b00 cmp r3, #0 800ecce: f000 8095 beq.w 800edfc { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; 800ecd2: 69bb ldr r3, [r7, #24] 800ecd4: 0e1b lsrs r3, r3, #24 800ecd6: f003 0303 and.w r3, r3, #3 800ecda: 617b str r3, [r7, #20] /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; 800ecdc: 2201 movs r2, #1 800ecde: 697b ldr r3, [r7, #20] 800ece0: 409a lsls r2, r3 800ece2: 683b ldr r3, [r7, #0] 800ece4: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) 800ece6: 68bb ldr r3, [r7, #8] 800ece8: 689b ldr r3, [r3, #8] 800ecea: 2b00 cmp r3, #0 800ecec: d10d bne.n 800ed0a { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800ecee: 68bb ldr r3, [r7, #8] 800ecf0: 681b ldr r3, [r3, #0] 800ecf2: 055a lsls r2, r3, #21 pHeader->RTR); 800ecf4: 68bb ldr r3, [r7, #8] 800ecf6: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800ecf8: 68f9 ldr r1, [r7, #12] 800ecfa: 6809 ldr r1, [r1, #0] 800ecfc: 431a orrs r2, r3 800ecfe: 697b ldr r3, [r7, #20] 800ed00: 3318 adds r3, #24 800ed02: 011b lsls r3, r3, #4 800ed04: 440b add r3, r1 800ed06: 601a str r2, [r3, #0] 800ed08: e00f b.n 800ed2a } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800ed0a: 68bb ldr r3, [r7, #8] 800ed0c: 685b ldr r3, [r3, #4] 800ed0e: 00da lsls r2, r3, #3 pHeader->IDE | 800ed10: 68bb ldr r3, [r7, #8] 800ed12: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800ed14: 431a orrs r2, r3 pHeader->RTR); 800ed16: 68bb ldr r3, [r7, #8] 800ed18: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800ed1a: 68f9 ldr r1, [r7, #12] 800ed1c: 6809 ldr r1, [r1, #0] pHeader->IDE | 800ed1e: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800ed20: 697b ldr r3, [r7, #20] 800ed22: 3318 adds r3, #24 800ed24: 011b lsls r3, r3, #4 800ed26: 440b add r3, r1 800ed28: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); 800ed2a: 68fb ldr r3, [r7, #12] 800ed2c: 6819 ldr r1, [r3, #0] 800ed2e: 68bb ldr r3, [r7, #8] 800ed30: 691a ldr r2, [r3, #16] 800ed32: 697b ldr r3, [r7, #20] 800ed34: 3318 adds r3, #24 800ed36: 011b lsls r3, r3, #4 800ed38: 440b add r3, r1 800ed3a: 3304 adds r3, #4 800ed3c: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) 800ed3e: 68bb ldr r3, [r7, #8] 800ed40: 7d1b ldrb r3, [r3, #20] 800ed42: 2b01 cmp r3, #1 800ed44: d111 bne.n 800ed6a { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); 800ed46: 68fb ldr r3, [r7, #12] 800ed48: 681a ldr r2, [r3, #0] 800ed4a: 697b ldr r3, [r7, #20] 800ed4c: 3318 adds r3, #24 800ed4e: 011b lsls r3, r3, #4 800ed50: 4413 add r3, r2 800ed52: 3304 adds r3, #4 800ed54: 681b ldr r3, [r3, #0] 800ed56: 68fa ldr r2, [r7, #12] 800ed58: 6811 ldr r1, [r2, #0] 800ed5a: f443 7280 orr.w r2, r3, #256 @ 0x100 800ed5e: 697b ldr r3, [r7, #20] 800ed60: 3318 adds r3, #24 800ed62: 011b lsls r3, r3, #4 800ed64: 440b add r3, r1 800ed66: 3304 adds r3, #4 800ed68: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, 800ed6a: 687b ldr r3, [r7, #4] 800ed6c: 3307 adds r3, #7 800ed6e: 781b ldrb r3, [r3, #0] 800ed70: 061a lsls r2, r3, #24 800ed72: 687b ldr r3, [r7, #4] 800ed74: 3306 adds r3, #6 800ed76: 781b ldrb r3, [r3, #0] 800ed78: 041b lsls r3, r3, #16 800ed7a: 431a orrs r2, r3 800ed7c: 687b ldr r3, [r7, #4] 800ed7e: 3305 adds r3, #5 800ed80: 781b ldrb r3, [r3, #0] 800ed82: 021b lsls r3, r3, #8 800ed84: 4313 orrs r3, r2 800ed86: 687a ldr r2, [r7, #4] 800ed88: 3204 adds r2, #4 800ed8a: 7812 ldrb r2, [r2, #0] 800ed8c: 4610 mov r0, r2 800ed8e: 68fa ldr r2, [r7, #12] 800ed90: 6811 ldr r1, [r2, #0] 800ed92: ea43 0200 orr.w r2, r3, r0 800ed96: 697b ldr r3, [r7, #20] 800ed98: 011b lsls r3, r3, #4 800ed9a: 440b add r3, r1 800ed9c: f503 73c6 add.w r3, r3, #396 @ 0x18c 800eda0: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, 800eda2: 687b ldr r3, [r7, #4] 800eda4: 3303 adds r3, #3 800eda6: 781b ldrb r3, [r3, #0] 800eda8: 061a lsls r2, r3, #24 800edaa: 687b ldr r3, [r7, #4] 800edac: 3302 adds r3, #2 800edae: 781b ldrb r3, [r3, #0] 800edb0: 041b lsls r3, r3, #16 800edb2: 431a orrs r2, r3 800edb4: 687b ldr r3, [r7, #4] 800edb6: 3301 adds r3, #1 800edb8: 781b ldrb r3, [r3, #0] 800edba: 021b lsls r3, r3, #8 800edbc: 4313 orrs r3, r2 800edbe: 687a ldr r2, [r7, #4] 800edc0: 7812 ldrb r2, [r2, #0] 800edc2: 4610 mov r0, r2 800edc4: 68fa ldr r2, [r7, #12] 800edc6: 6811 ldr r1, [r2, #0] 800edc8: ea43 0200 orr.w r2, r3, r0 800edcc: 697b ldr r3, [r7, #20] 800edce: 011b lsls r3, r3, #4 800edd0: 440b add r3, r1 800edd2: f503 73c4 add.w r3, r3, #392 @ 0x188 800edd6: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); 800edd8: 68fb ldr r3, [r7, #12] 800edda: 681a ldr r2, [r3, #0] 800eddc: 697b ldr r3, [r7, #20] 800edde: 3318 adds r3, #24 800ede0: 011b lsls r3, r3, #4 800ede2: 4413 add r3, r2 800ede4: 681b ldr r3, [r3, #0] 800ede6: 68fa ldr r2, [r7, #12] 800ede8: 6811 ldr r1, [r2, #0] 800edea: f043 0201 orr.w r2, r3, #1 800edee: 697b ldr r3, [r7, #20] 800edf0: 3318 adds r3, #24 800edf2: 011b lsls r3, r3, #4 800edf4: 440b add r3, r1 800edf6: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800edf8: 2300 movs r3, #0 800edfa: e00e b.n 800ee1a } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800edfc: 68fb ldr r3, [r7, #12] 800edfe: 6a5b ldr r3, [r3, #36] @ 0x24 800ee00: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800ee04: 68fb ldr r3, [r7, #12] 800ee06: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ee08: 2301 movs r3, #1 800ee0a: e006 b.n 800ee1a } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800ee0c: 68fb ldr r3, [r7, #12] 800ee0e: 6a5b ldr r3, [r3, #36] @ 0x24 800ee10: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800ee14: 68fb ldr r3, [r7, #12] 800ee16: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ee18: 2301 movs r3, #1 } } 800ee1a: 4618 mov r0, r3 800ee1c: 3724 adds r7, #36 @ 0x24 800ee1e: 46bd mov sp, r7 800ee20: bc80 pop {r7} 800ee22: 4770 bx lr 0800ee24 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval Number of free Tx Mailboxes. */ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) { 800ee24: b480 push {r7} 800ee26: b085 sub sp, #20 800ee28: af00 add r7, sp, #0 800ee2a: 6078 str r0, [r7, #4] uint32_t freelevel = 0U; 800ee2c: 2300 movs r3, #0 800ee2e: 60fb str r3, [r7, #12] HAL_CAN_StateTypeDef state = hcan->State; 800ee30: 687b ldr r3, [r7, #4] 800ee32: f893 3020 ldrb.w r3, [r3, #32] 800ee36: 72fb strb r3, [r7, #11] if ((state == HAL_CAN_STATE_READY) || 800ee38: 7afb ldrb r3, [r7, #11] 800ee3a: 2b01 cmp r3, #1 800ee3c: d002 beq.n 800ee44 800ee3e: 7afb ldrb r3, [r7, #11] 800ee40: 2b02 cmp r3, #2 800ee42: d11d bne.n 800ee80 (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 status */ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) 800ee44: 687b ldr r3, [r7, #4] 800ee46: 681b ldr r3, [r3, #0] 800ee48: 689b ldr r3, [r3, #8] 800ee4a: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800ee4e: 2b00 cmp r3, #0 800ee50: d002 beq.n 800ee58 { freelevel++; 800ee52: 68fb ldr r3, [r7, #12] 800ee54: 3301 adds r3, #1 800ee56: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 1 status */ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) 800ee58: 687b ldr r3, [r7, #4] 800ee5a: 681b ldr r3, [r3, #0] 800ee5c: 689b ldr r3, [r3, #8] 800ee5e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800ee62: 2b00 cmp r3, #0 800ee64: d002 beq.n 800ee6c { freelevel++; 800ee66: 68fb ldr r3, [r7, #12] 800ee68: 3301 adds r3, #1 800ee6a: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 2 status */ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) 800ee6c: 687b ldr r3, [r7, #4] 800ee6e: 681b ldr r3, [r3, #0] 800ee70: 689b ldr r3, [r3, #8] 800ee72: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800ee76: 2b00 cmp r3, #0 800ee78: d002 beq.n 800ee80 { freelevel++; 800ee7a: 68fb ldr r3, [r7, #12] 800ee7c: 3301 adds r3, #1 800ee7e: 60fb str r3, [r7, #12] } } /* Return Tx Mailboxes free level */ return freelevel; 800ee80: 68fb ldr r3, [r7, #12] } 800ee82: 4618 mov r0, r3 800ee84: 3714 adds r7, #20 800ee86: 46bd mov sp, r7 800ee88: bc80 pop {r7} 800ee8a: 4770 bx lr 0800ee8c : * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { 800ee8c: b480 push {r7} 800ee8e: b087 sub sp, #28 800ee90: af00 add r7, sp, #0 800ee92: 60f8 str r0, [r7, #12] 800ee94: 60b9 str r1, [r7, #8] 800ee96: 607a str r2, [r7, #4] 800ee98: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800ee9a: 68fb ldr r3, [r7, #12] 800ee9c: f893 3020 ldrb.w r3, [r3, #32] 800eea0: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || 800eea2: 7dfb ldrb r3, [r7, #23] 800eea4: 2b01 cmp r3, #1 800eea6: d003 beq.n 800eeb0 800eea8: 7dfb ldrb r3, [r7, #23] 800eeaa: 2b02 cmp r3, #2 800eeac: f040 8103 bne.w 800f0b6 (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800eeb0: 68bb ldr r3, [r7, #8] 800eeb2: 2b00 cmp r3, #0 800eeb4: d10e bne.n 800eed4 { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) 800eeb6: 68fb ldr r3, [r7, #12] 800eeb8: 681b ldr r3, [r3, #0] 800eeba: 68db ldr r3, [r3, #12] 800eebc: f003 0303 and.w r3, r3, #3 800eec0: 2b00 cmp r3, #0 800eec2: d116 bne.n 800eef2 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800eec4: 68fb ldr r3, [r7, #12] 800eec6: 6a5b ldr r3, [r3, #36] @ 0x24 800eec8: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800eecc: 68fb ldr r3, [r7, #12] 800eece: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800eed0: 2301 movs r3, #1 800eed2: e0f7 b.n 800f0c4 } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) 800eed4: 68fb ldr r3, [r7, #12] 800eed6: 681b ldr r3, [r3, #0] 800eed8: 691b ldr r3, [r3, #16] 800eeda: f003 0303 and.w r3, r3, #3 800eede: 2b00 cmp r3, #0 800eee0: d107 bne.n 800eef2 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800eee2: 68fb ldr r3, [r7, #12] 800eee4: 6a5b ldr r3, [r3, #36] @ 0x24 800eee6: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800eeea: 68fb ldr r3, [r7, #12] 800eeec: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800eeee: 2301 movs r3, #1 800eef0: e0e8 b.n 800f0c4 } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; 800eef2: 68fb ldr r3, [r7, #12] 800eef4: 681a ldr r2, [r3, #0] 800eef6: 68bb ldr r3, [r7, #8] 800eef8: 331b adds r3, #27 800eefa: 011b lsls r3, r3, #4 800eefc: 4413 add r3, r2 800eefe: 681b ldr r3, [r3, #0] 800ef00: f003 0204 and.w r2, r3, #4 800ef04: 687b ldr r3, [r7, #4] 800ef06: 609a str r2, [r3, #8] if (pHeader->IDE == CAN_ID_STD) 800ef08: 687b ldr r3, [r7, #4] 800ef0a: 689b ldr r3, [r3, #8] 800ef0c: 2b00 cmp r3, #0 800ef0e: d10c bne.n 800ef2a { pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; 800ef10: 68fb ldr r3, [r7, #12] 800ef12: 681a ldr r2, [r3, #0] 800ef14: 68bb ldr r3, [r7, #8] 800ef16: 331b adds r3, #27 800ef18: 011b lsls r3, r3, #4 800ef1a: 4413 add r3, r2 800ef1c: 681b ldr r3, [r3, #0] 800ef1e: 0d5b lsrs r3, r3, #21 800ef20: f3c3 020a ubfx r2, r3, #0, #11 800ef24: 687b ldr r3, [r7, #4] 800ef26: 601a str r2, [r3, #0] 800ef28: e00b b.n 800ef42 } else { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; 800ef2a: 68fb ldr r3, [r7, #12] 800ef2c: 681a ldr r2, [r3, #0] 800ef2e: 68bb ldr r3, [r7, #8] 800ef30: 331b adds r3, #27 800ef32: 011b lsls r3, r3, #4 800ef34: 4413 add r3, r2 800ef36: 681b ldr r3, [r3, #0] 800ef38: 08db lsrs r3, r3, #3 800ef3a: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & 800ef3e: 687b ldr r3, [r7, #4] 800ef40: 605a str r2, [r3, #4] } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); 800ef42: 68fb ldr r3, [r7, #12] 800ef44: 681a ldr r2, [r3, #0] 800ef46: 68bb ldr r3, [r7, #8] 800ef48: 331b adds r3, #27 800ef4a: 011b lsls r3, r3, #4 800ef4c: 4413 add r3, r2 800ef4e: 681b ldr r3, [r3, #0] 800ef50: f003 0202 and.w r2, r3, #2 800ef54: 687b ldr r3, [r7, #4] 800ef56: 60da str r2, [r3, #12] if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) 800ef58: 68fb ldr r3, [r7, #12] 800ef5a: 681a ldr r2, [r3, #0] 800ef5c: 68bb ldr r3, [r7, #8] 800ef5e: 331b adds r3, #27 800ef60: 011b lsls r3, r3, #4 800ef62: 4413 add r3, r2 800ef64: 3304 adds r3, #4 800ef66: 681b ldr r3, [r3, #0] 800ef68: f003 0308 and.w r3, r3, #8 800ef6c: 2b00 cmp r3, #0 800ef6e: d003 beq.n 800ef78 { /* Truncate DLC to 8 if received field is over range */ pHeader->DLC = 8U; 800ef70: 687b ldr r3, [r7, #4] 800ef72: 2208 movs r2, #8 800ef74: 611a str r2, [r3, #16] 800ef76: e00b b.n 800ef90 } else { pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; 800ef78: 68fb ldr r3, [r7, #12] 800ef7a: 681a ldr r2, [r3, #0] 800ef7c: 68bb ldr r3, [r7, #8] 800ef7e: 331b adds r3, #27 800ef80: 011b lsls r3, r3, #4 800ef82: 4413 add r3, r2 800ef84: 3304 adds r3, #4 800ef86: 681b ldr r3, [r3, #0] 800ef88: f003 020f and.w r2, r3, #15 800ef8c: 687b ldr r3, [r7, #4] 800ef8e: 611a str r2, [r3, #16] } pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; 800ef90: 68fb ldr r3, [r7, #12] 800ef92: 681a ldr r2, [r3, #0] 800ef94: 68bb ldr r3, [r7, #8] 800ef96: 331b adds r3, #27 800ef98: 011b lsls r3, r3, #4 800ef9a: 4413 add r3, r2 800ef9c: 3304 adds r3, #4 800ef9e: 681b ldr r3, [r3, #0] 800efa0: 0a1b lsrs r3, r3, #8 800efa2: b2da uxtb r2, r3 800efa4: 687b ldr r3, [r7, #4] 800efa6: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; 800efa8: 68fb ldr r3, [r7, #12] 800efaa: 681a ldr r2, [r3, #0] 800efac: 68bb ldr r3, [r7, #8] 800efae: 331b adds r3, #27 800efb0: 011b lsls r3, r3, #4 800efb2: 4413 add r3, r2 800efb4: 3304 adds r3, #4 800efb6: 681b ldr r3, [r3, #0] 800efb8: 0c1b lsrs r3, r3, #16 800efba: b29a uxth r2, r3 800efbc: 687b ldr r3, [r7, #4] 800efbe: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); 800efc0: 68fb ldr r3, [r7, #12] 800efc2: 681a ldr r2, [r3, #0] 800efc4: 68bb ldr r3, [r7, #8] 800efc6: 011b lsls r3, r3, #4 800efc8: 4413 add r3, r2 800efca: f503 73dc add.w r3, r3, #440 @ 0x1b8 800efce: 681b ldr r3, [r3, #0] 800efd0: b2da uxtb r2, r3 800efd2: 683b ldr r3, [r7, #0] 800efd4: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); 800efd6: 68fb ldr r3, [r7, #12] 800efd8: 681a ldr r2, [r3, #0] 800efda: 68bb ldr r3, [r7, #8] 800efdc: 011b lsls r3, r3, #4 800efde: 4413 add r3, r2 800efe0: f503 73dc add.w r3, r3, #440 @ 0x1b8 800efe4: 681b ldr r3, [r3, #0] 800efe6: 0a1a lsrs r2, r3, #8 800efe8: 683b ldr r3, [r7, #0] 800efea: 3301 adds r3, #1 800efec: b2d2 uxtb r2, r2 800efee: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); 800eff0: 68fb ldr r3, [r7, #12] 800eff2: 681a ldr r2, [r3, #0] 800eff4: 68bb ldr r3, [r7, #8] 800eff6: 011b lsls r3, r3, #4 800eff8: 4413 add r3, r2 800effa: f503 73dc add.w r3, r3, #440 @ 0x1b8 800effe: 681b ldr r3, [r3, #0] 800f000: 0c1a lsrs r2, r3, #16 800f002: 683b ldr r3, [r7, #0] 800f004: 3302 adds r3, #2 800f006: b2d2 uxtb r2, r2 800f008: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); 800f00a: 68fb ldr r3, [r7, #12] 800f00c: 681a ldr r2, [r3, #0] 800f00e: 68bb ldr r3, [r7, #8] 800f010: 011b lsls r3, r3, #4 800f012: 4413 add r3, r2 800f014: f503 73dc add.w r3, r3, #440 @ 0x1b8 800f018: 681b ldr r3, [r3, #0] 800f01a: 0e1a lsrs r2, r3, #24 800f01c: 683b ldr r3, [r7, #0] 800f01e: 3303 adds r3, #3 800f020: b2d2 uxtb r2, r2 800f022: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); 800f024: 68fb ldr r3, [r7, #12] 800f026: 681a ldr r2, [r3, #0] 800f028: 68bb ldr r3, [r7, #8] 800f02a: 011b lsls r3, r3, #4 800f02c: 4413 add r3, r2 800f02e: f503 73de add.w r3, r3, #444 @ 0x1bc 800f032: 681a ldr r2, [r3, #0] 800f034: 683b ldr r3, [r7, #0] 800f036: 3304 adds r3, #4 800f038: b2d2 uxtb r2, r2 800f03a: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); 800f03c: 68fb ldr r3, [r7, #12] 800f03e: 681a ldr r2, [r3, #0] 800f040: 68bb ldr r3, [r7, #8] 800f042: 011b lsls r3, r3, #4 800f044: 4413 add r3, r2 800f046: f503 73de add.w r3, r3, #444 @ 0x1bc 800f04a: 681b ldr r3, [r3, #0] 800f04c: 0a1a lsrs r2, r3, #8 800f04e: 683b ldr r3, [r7, #0] 800f050: 3305 adds r3, #5 800f052: b2d2 uxtb r2, r2 800f054: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); 800f056: 68fb ldr r3, [r7, #12] 800f058: 681a ldr r2, [r3, #0] 800f05a: 68bb ldr r3, [r7, #8] 800f05c: 011b lsls r3, r3, #4 800f05e: 4413 add r3, r2 800f060: f503 73de add.w r3, r3, #444 @ 0x1bc 800f064: 681b ldr r3, [r3, #0] 800f066: 0c1a lsrs r2, r3, #16 800f068: 683b ldr r3, [r7, #0] 800f06a: 3306 adds r3, #6 800f06c: b2d2 uxtb r2, r2 800f06e: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); 800f070: 68fb ldr r3, [r7, #12] 800f072: 681a ldr r2, [r3, #0] 800f074: 68bb ldr r3, [r7, #8] 800f076: 011b lsls r3, r3, #4 800f078: 4413 add r3, r2 800f07a: f503 73de add.w r3, r3, #444 @ 0x1bc 800f07e: 681b ldr r3, [r3, #0] 800f080: 0e1a lsrs r2, r3, #24 800f082: 683b ldr r3, [r7, #0] 800f084: 3307 adds r3, #7 800f086: b2d2 uxtb r2, r2 800f088: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800f08a: 68bb ldr r3, [r7, #8] 800f08c: 2b00 cmp r3, #0 800f08e: d108 bne.n 800f0a2 { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); 800f090: 68fb ldr r3, [r7, #12] 800f092: 681b ldr r3, [r3, #0] 800f094: 68da ldr r2, [r3, #12] 800f096: 68fb ldr r3, [r7, #12] 800f098: 681b ldr r3, [r3, #0] 800f09a: f042 0220 orr.w r2, r2, #32 800f09e: 60da str r2, [r3, #12] 800f0a0: e007 b.n 800f0b2 } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); 800f0a2: 68fb ldr r3, [r7, #12] 800f0a4: 681b ldr r3, [r3, #0] 800f0a6: 691a ldr r2, [r3, #16] 800f0a8: 68fb ldr r3, [r7, #12] 800f0aa: 681b ldr r3, [r3, #0] 800f0ac: f042 0220 orr.w r2, r2, #32 800f0b0: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; 800f0b2: 2300 movs r3, #0 800f0b4: e006 b.n 800f0c4 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f0b6: 68fb ldr r3, [r7, #12] 800f0b8: 6a5b ldr r3, [r3, #36] @ 0x24 800f0ba: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f0be: 68fb ldr r3, [r7, #12] 800f0c0: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f0c2: 2301 movs r3, #1 } } 800f0c4: 4618 mov r0, r3 800f0c6: 371c adds r7, #28 800f0c8: 46bd mov sp, r7 800f0ca: bc80 pop {r7} 800f0cc: 4770 bx lr 0800f0ce : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { 800f0ce: b480 push {r7} 800f0d0: b085 sub sp, #20 800f0d2: af00 add r7, sp, #0 800f0d4: 6078 str r0, [r7, #4] 800f0d6: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800f0d8: 687b ldr r3, [r7, #4] 800f0da: f893 3020 ldrb.w r3, [r3, #32] 800f0de: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || 800f0e0: 7bfb ldrb r3, [r7, #15] 800f0e2: 2b01 cmp r3, #1 800f0e4: d002 beq.n 800f0ec 800f0e6: 7bfb ldrb r3, [r7, #15] 800f0e8: 2b02 cmp r3, #2 800f0ea: d109 bne.n 800f100 (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); 800f0ec: 687b ldr r3, [r7, #4] 800f0ee: 681b ldr r3, [r3, #0] 800f0f0: 6959 ldr r1, [r3, #20] 800f0f2: 687b ldr r3, [r7, #4] 800f0f4: 681b ldr r3, [r3, #0] 800f0f6: 683a ldr r2, [r7, #0] 800f0f8: 430a orrs r2, r1 800f0fa: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; 800f0fc: 2300 movs r3, #0 800f0fe: e006 b.n 800f10e } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f100: 687b ldr r3, [r7, #4] 800f102: 6a5b ldr r3, [r3, #36] @ 0x24 800f104: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f108: 687b ldr r3, [r7, #4] 800f10a: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f10c: 2301 movs r3, #1 } } 800f10e: 4618 mov r0, r3 800f110: 3714 adds r7, #20 800f112: 46bd mov sp, r7 800f114: bc80 pop {r7} 800f116: 4770 bx lr 0800f118 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { 800f118: b580 push {r7, lr} 800f11a: b08a sub sp, #40 @ 0x28 800f11c: af00 add r7, sp, #0 800f11e: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; 800f120: 2300 movs r3, #0 800f122: 627b str r3, [r7, #36] @ 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); 800f124: 687b ldr r3, [r7, #4] 800f126: 681b ldr r3, [r3, #0] 800f128: 695b ldr r3, [r3, #20] 800f12a: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); 800f12c: 687b ldr r3, [r7, #4] 800f12e: 681b ldr r3, [r3, #0] 800f130: 685b ldr r3, [r3, #4] 800f132: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); 800f134: 687b ldr r3, [r7, #4] 800f136: 681b ldr r3, [r3, #0] 800f138: 689b ldr r3, [r3, #8] 800f13a: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); 800f13c: 687b ldr r3, [r7, #4] 800f13e: 681b ldr r3, [r3, #0] 800f140: 68db ldr r3, [r3, #12] 800f142: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); 800f144: 687b ldr r3, [r7, #4] 800f146: 681b ldr r3, [r3, #0] 800f148: 691b ldr r3, [r3, #16] 800f14a: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); 800f14c: 687b ldr r3, [r7, #4] 800f14e: 681b ldr r3, [r3, #0] 800f150: 699b ldr r3, [r3, #24] 800f152: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) 800f154: 6a3b ldr r3, [r7, #32] 800f156: f003 0301 and.w r3, r3, #1 800f15a: 2b00 cmp r3, #0 800f15c: d07c beq.n 800f258 { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) 800f15e: 69bb ldr r3, [r7, #24] 800f160: f003 0301 and.w r3, r3, #1 800f164: 2b00 cmp r3, #0 800f166: d023 beq.n 800f1b0 { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); 800f168: 687b ldr r3, [r7, #4] 800f16a: 681b ldr r3, [r3, #0] 800f16c: 2201 movs r2, #1 800f16e: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) 800f170: 69bb ldr r3, [r7, #24] 800f172: f003 0302 and.w r3, r3, #2 800f176: 2b00 cmp r3, #0 800f178: d003 beq.n 800f182 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); 800f17a: 6878 ldr r0, [r7, #4] 800f17c: f000 f983 bl 800f486 800f180: e016 b.n 800f1b0 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) 800f182: 69bb ldr r3, [r7, #24] 800f184: f003 0304 and.w r3, r3, #4 800f188: 2b00 cmp r3, #0 800f18a: d004 beq.n 800f196 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; 800f18c: 6a7b ldr r3, [r7, #36] @ 0x24 800f18e: f443 6300 orr.w r3, r3, #2048 @ 0x800 800f192: 627b str r3, [r7, #36] @ 0x24 800f194: e00c b.n 800f1b0 } else if ((tsrflags & CAN_TSR_TERR0) != 0U) 800f196: 69bb ldr r3, [r7, #24] 800f198: f003 0308 and.w r3, r3, #8 800f19c: 2b00 cmp r3, #0 800f19e: d004 beq.n 800f1aa { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; 800f1a0: 6a7b ldr r3, [r7, #36] @ 0x24 800f1a2: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800f1a6: 627b str r3, [r7, #36] @ 0x24 800f1a8: e002 b.n 800f1b0 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); 800f1aa: 6878 ldr r0, [r7, #4] 800f1ac: f000 f986 bl 800f4bc } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) 800f1b0: 69bb ldr r3, [r7, #24] 800f1b2: f403 7380 and.w r3, r3, #256 @ 0x100 800f1b6: 2b00 cmp r3, #0 800f1b8: d024 beq.n 800f204 { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); 800f1ba: 687b ldr r3, [r7, #4] 800f1bc: 681b ldr r3, [r3, #0] 800f1be: f44f 7280 mov.w r2, #256 @ 0x100 800f1c2: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) 800f1c4: 69bb ldr r3, [r7, #24] 800f1c6: f403 7300 and.w r3, r3, #512 @ 0x200 800f1ca: 2b00 cmp r3, #0 800f1cc: d003 beq.n 800f1d6 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); 800f1ce: 6878 ldr r0, [r7, #4] 800f1d0: f000 f962 bl 800f498 800f1d4: e016 b.n 800f204 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) 800f1d6: 69bb ldr r3, [r7, #24] 800f1d8: f403 6380 and.w r3, r3, #1024 @ 0x400 800f1dc: 2b00 cmp r3, #0 800f1de: d004 beq.n 800f1ea { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; 800f1e0: 6a7b ldr r3, [r7, #36] @ 0x24 800f1e2: f443 5300 orr.w r3, r3, #8192 @ 0x2000 800f1e6: 627b str r3, [r7, #36] @ 0x24 800f1e8: e00c b.n 800f204 } else if ((tsrflags & CAN_TSR_TERR1) != 0U) 800f1ea: 69bb ldr r3, [r7, #24] 800f1ec: f403 6300 and.w r3, r3, #2048 @ 0x800 800f1f0: 2b00 cmp r3, #0 800f1f2: d004 beq.n 800f1fe { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; 800f1f4: 6a7b ldr r3, [r7, #36] @ 0x24 800f1f6: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800f1fa: 627b str r3, [r7, #36] @ 0x24 800f1fc: e002 b.n 800f204 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); 800f1fe: 6878 ldr r0, [r7, #4] 800f200: f000 f965 bl 800f4ce } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) 800f204: 69bb ldr r3, [r7, #24] 800f206: f403 3380 and.w r3, r3, #65536 @ 0x10000 800f20a: 2b00 cmp r3, #0 800f20c: d024 beq.n 800f258 { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); 800f20e: 687b ldr r3, [r7, #4] 800f210: 681b ldr r3, [r3, #0] 800f212: f44f 3280 mov.w r2, #65536 @ 0x10000 800f216: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) 800f218: 69bb ldr r3, [r7, #24] 800f21a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800f21e: 2b00 cmp r3, #0 800f220: d003 beq.n 800f22a #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); 800f222: 6878 ldr r0, [r7, #4] 800f224: f000 f941 bl 800f4aa 800f228: e016 b.n 800f258 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) 800f22a: 69bb ldr r3, [r7, #24] 800f22c: f403 2380 and.w r3, r3, #262144 @ 0x40000 800f230: 2b00 cmp r3, #0 800f232: d004 beq.n 800f23e { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; 800f234: 6a7b ldr r3, [r7, #36] @ 0x24 800f236: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f23a: 627b str r3, [r7, #36] @ 0x24 800f23c: e00c b.n 800f258 } else if ((tsrflags & CAN_TSR_TERR2) != 0U) 800f23e: 69bb ldr r3, [r7, #24] 800f240: f403 2300 and.w r3, r3, #524288 @ 0x80000 800f244: 2b00 cmp r3, #0 800f246: d004 beq.n 800f252 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; 800f248: 6a7b ldr r3, [r7, #36] @ 0x24 800f24a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800f24e: 627b str r3, [r7, #36] @ 0x24 800f250: e002 b.n 800f258 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); 800f252: 6878 ldr r0, [r7, #4] 800f254: f000 f944 bl 800f4e0 } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) 800f258: 6a3b ldr r3, [r7, #32] 800f25a: f003 0308 and.w r3, r3, #8 800f25e: 2b00 cmp r3, #0 800f260: d00c beq.n 800f27c { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) 800f262: 697b ldr r3, [r7, #20] 800f264: f003 0310 and.w r3, r3, #16 800f268: 2b00 cmp r3, #0 800f26a: d007 beq.n 800f27c { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; 800f26c: 6a7b ldr r3, [r7, #36] @ 0x24 800f26e: f443 7300 orr.w r3, r3, #512 @ 0x200 800f272: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); 800f274: 687b ldr r3, [r7, #4] 800f276: 681b ldr r3, [r3, #0] 800f278: 2210 movs r2, #16 800f27a: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) 800f27c: 6a3b ldr r3, [r7, #32] 800f27e: f003 0304 and.w r3, r3, #4 800f282: 2b00 cmp r3, #0 800f284: d00b beq.n 800f29e { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) 800f286: 697b ldr r3, [r7, #20] 800f288: f003 0308 and.w r3, r3, #8 800f28c: 2b00 cmp r3, #0 800f28e: d006 beq.n 800f29e { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); 800f290: 687b ldr r3, [r7, #4] 800f292: 681b ldr r3, [r3, #0] 800f294: 2208 movs r2, #8 800f296: 60da str r2, [r3, #12] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); 800f298: 6878 ldr r0, [r7, #4] 800f29a: f000 f933 bl 800f504 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) 800f29e: 6a3b ldr r3, [r7, #32] 800f2a0: f003 0302 and.w r3, r3, #2 800f2a4: 2b00 cmp r3, #0 800f2a6: d009 beq.n 800f2bc { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) 800f2a8: 687b ldr r3, [r7, #4] 800f2aa: 681b ldr r3, [r3, #0] 800f2ac: 68db ldr r3, [r3, #12] 800f2ae: f003 0303 and.w r3, r3, #3 800f2b2: 2b00 cmp r3, #0 800f2b4: d002 beq.n 800f2bc #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); 800f2b6: 6878 ldr r0, [r7, #4] 800f2b8: f000 f91b bl 800f4f2 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) 800f2bc: 6a3b ldr r3, [r7, #32] 800f2be: f003 0340 and.w r3, r3, #64 @ 0x40 800f2c2: 2b00 cmp r3, #0 800f2c4: d00c beq.n 800f2e0 { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) 800f2c6: 693b ldr r3, [r7, #16] 800f2c8: f003 0310 and.w r3, r3, #16 800f2cc: 2b00 cmp r3, #0 800f2ce: d007 beq.n 800f2e0 { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; 800f2d0: 6a7b ldr r3, [r7, #36] @ 0x24 800f2d2: f443 6380 orr.w r3, r3, #1024 @ 0x400 800f2d6: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); 800f2d8: 687b ldr r3, [r7, #4] 800f2da: 681b ldr r3, [r3, #0] 800f2dc: 2210 movs r2, #16 800f2de: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) 800f2e0: 6a3b ldr r3, [r7, #32] 800f2e2: f003 0320 and.w r3, r3, #32 800f2e6: 2b00 cmp r3, #0 800f2e8: d00b beq.n 800f302 { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) 800f2ea: 693b ldr r3, [r7, #16] 800f2ec: f003 0308 and.w r3, r3, #8 800f2f0: 2b00 cmp r3, #0 800f2f2: d006 beq.n 800f302 { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); 800f2f4: 687b ldr r3, [r7, #4] 800f2f6: 681b ldr r3, [r3, #0] 800f2f8: 2208 movs r2, #8 800f2fa: 611a str r2, [r3, #16] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); 800f2fc: 6878 ldr r0, [r7, #4] 800f2fe: f000 f90a bl 800f516 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) 800f302: 6a3b ldr r3, [r7, #32] 800f304: f003 0310 and.w r3, r3, #16 800f308: 2b00 cmp r3, #0 800f30a: d009 beq.n 800f320 { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) 800f30c: 687b ldr r3, [r7, #4] 800f30e: 681b ldr r3, [r3, #0] 800f310: 691b ldr r3, [r3, #16] 800f312: f003 0303 and.w r3, r3, #3 800f316: 2b00 cmp r3, #0 800f318: d002 beq.n 800f320 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); 800f31a: 6878 ldr r0, [r7, #4] 800f31c: f7fb fc12 bl 800ab44 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) 800f320: 6a3b ldr r3, [r7, #32] 800f322: f403 3300 and.w r3, r3, #131072 @ 0x20000 800f326: 2b00 cmp r3, #0 800f328: d00b beq.n 800f342 { if ((msrflags & CAN_MSR_SLAKI) != 0U) 800f32a: 69fb ldr r3, [r7, #28] 800f32c: f003 0310 and.w r3, r3, #16 800f330: 2b00 cmp r3, #0 800f332: d006 beq.n 800f342 { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); 800f334: 687b ldr r3, [r7, #4] 800f336: 681b ldr r3, [r3, #0] 800f338: 2210 movs r2, #16 800f33a: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->SleepCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); 800f33c: 6878 ldr r0, [r7, #4] 800f33e: f000 f8f3 bl 800f528 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ if ((interrupts & CAN_IT_WAKEUP) != 0U) 800f342: 6a3b ldr r3, [r7, #32] 800f344: f403 3380 and.w r3, r3, #65536 @ 0x10000 800f348: 2b00 cmp r3, #0 800f34a: d00b beq.n 800f364 { if ((msrflags & CAN_MSR_WKUI) != 0U) 800f34c: 69fb ldr r3, [r7, #28] 800f34e: f003 0308 and.w r3, r3, #8 800f352: 2b00 cmp r3, #0 800f354: d006 beq.n 800f364 { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); 800f356: 687b ldr r3, [r7, #4] 800f358: 681b ldr r3, [r3, #0] 800f35a: 2208 movs r2, #8 800f35c: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->WakeUpFromRxMsgCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); 800f35e: 6878 ldr r0, [r7, #4] 800f360: f000 f8eb bl 800f53a #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ if ((interrupts & CAN_IT_ERROR) != 0U) 800f364: 6a3b ldr r3, [r7, #32] 800f366: f403 4300 and.w r3, r3, #32768 @ 0x8000 800f36a: 2b00 cmp r3, #0 800f36c: d07b beq.n 800f466 { if ((msrflags & CAN_MSR_ERRI) != 0U) 800f36e: 69fb ldr r3, [r7, #28] 800f370: f003 0304 and.w r3, r3, #4 800f374: 2b00 cmp r3, #0 800f376: d072 beq.n 800f45e { /* Check Error Warning Flag */ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800f378: 6a3b ldr r3, [r7, #32] 800f37a: f403 7380 and.w r3, r3, #256 @ 0x100 800f37e: 2b00 cmp r3, #0 800f380: d008 beq.n 800f394 ((esrflags & CAN_ESR_EWGF) != 0U)) 800f382: 68fb ldr r3, [r7, #12] 800f384: f003 0301 and.w r3, r3, #1 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800f388: 2b00 cmp r3, #0 800f38a: d003 beq.n 800f394 { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; 800f38c: 6a7b ldr r3, [r7, #36] @ 0x24 800f38e: f043 0301 orr.w r3, r3, #1 800f392: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Warning Flag as read-only */ } /* Check Error Passive Flag */ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800f394: 6a3b ldr r3, [r7, #32] 800f396: f403 7300 and.w r3, r3, #512 @ 0x200 800f39a: 2b00 cmp r3, #0 800f39c: d008 beq.n 800f3b0 ((esrflags & CAN_ESR_EPVF) != 0U)) 800f39e: 68fb ldr r3, [r7, #12] 800f3a0: f003 0302 and.w r3, r3, #2 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800f3a4: 2b00 cmp r3, #0 800f3a6: d003 beq.n 800f3b0 { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; 800f3a8: 6a7b ldr r3, [r7, #36] @ 0x24 800f3aa: f043 0302 orr.w r3, r3, #2 800f3ae: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-off Flag */ if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800f3b0: 6a3b ldr r3, [r7, #32] 800f3b2: f403 6380 and.w r3, r3, #1024 @ 0x400 800f3b6: 2b00 cmp r3, #0 800f3b8: d008 beq.n 800f3cc ((esrflags & CAN_ESR_BOFF) != 0U)) 800f3ba: 68fb ldr r3, [r7, #12] 800f3bc: f003 0304 and.w r3, r3, #4 if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800f3c0: 2b00 cmp r3, #0 800f3c2: d003 beq.n 800f3cc { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; 800f3c4: 6a7b ldr r3, [r7, #36] @ 0x24 800f3c6: f043 0304 orr.w r3, r3, #4 800f3ca: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Bus-Off as read-only */ } /* Check Last Error Code Flag */ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800f3cc: 6a3b ldr r3, [r7, #32] 800f3ce: f403 6300 and.w r3, r3, #2048 @ 0x800 800f3d2: 2b00 cmp r3, #0 800f3d4: d043 beq.n 800f45e ((esrflags & CAN_ESR_LEC) != 0U)) 800f3d6: 68fb ldr r3, [r7, #12] 800f3d8: f003 0370 and.w r3, r3, #112 @ 0x70 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800f3dc: 2b00 cmp r3, #0 800f3de: d03e beq.n 800f45e { switch (esrflags & CAN_ESR_LEC) 800f3e0: 68fb ldr r3, [r7, #12] 800f3e2: f003 0370 and.w r3, r3, #112 @ 0x70 800f3e6: 2b60 cmp r3, #96 @ 0x60 800f3e8: d02b beq.n 800f442 800f3ea: 2b60 cmp r3, #96 @ 0x60 800f3ec: d82e bhi.n 800f44c 800f3ee: 2b50 cmp r3, #80 @ 0x50 800f3f0: d022 beq.n 800f438 800f3f2: 2b50 cmp r3, #80 @ 0x50 800f3f4: d82a bhi.n 800f44c 800f3f6: 2b40 cmp r3, #64 @ 0x40 800f3f8: d019 beq.n 800f42e 800f3fa: 2b40 cmp r3, #64 @ 0x40 800f3fc: d826 bhi.n 800f44c 800f3fe: 2b30 cmp r3, #48 @ 0x30 800f400: d010 beq.n 800f424 800f402: 2b30 cmp r3, #48 @ 0x30 800f404: d822 bhi.n 800f44c 800f406: 2b10 cmp r3, #16 800f408: d002 beq.n 800f410 800f40a: 2b20 cmp r3, #32 800f40c: d005 beq.n 800f41a case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): /* Set CAN error code to CRC error */ errorcode |= HAL_CAN_ERROR_CRC; break; default: break; 800f40e: e01d b.n 800f44c errorcode |= HAL_CAN_ERROR_STF; 800f410: 6a7b ldr r3, [r7, #36] @ 0x24 800f412: f043 0308 orr.w r3, r3, #8 800f416: 627b str r3, [r7, #36] @ 0x24 break; 800f418: e019 b.n 800f44e errorcode |= HAL_CAN_ERROR_FOR; 800f41a: 6a7b ldr r3, [r7, #36] @ 0x24 800f41c: f043 0310 orr.w r3, r3, #16 800f420: 627b str r3, [r7, #36] @ 0x24 break; 800f422: e014 b.n 800f44e errorcode |= HAL_CAN_ERROR_ACK; 800f424: 6a7b ldr r3, [r7, #36] @ 0x24 800f426: f043 0320 orr.w r3, r3, #32 800f42a: 627b str r3, [r7, #36] @ 0x24 break; 800f42c: e00f b.n 800f44e errorcode |= HAL_CAN_ERROR_BR; 800f42e: 6a7b ldr r3, [r7, #36] @ 0x24 800f430: f043 0340 orr.w r3, r3, #64 @ 0x40 800f434: 627b str r3, [r7, #36] @ 0x24 break; 800f436: e00a b.n 800f44e errorcode |= HAL_CAN_ERROR_BD; 800f438: 6a7b ldr r3, [r7, #36] @ 0x24 800f43a: f043 0380 orr.w r3, r3, #128 @ 0x80 800f43e: 627b str r3, [r7, #36] @ 0x24 break; 800f440: e005 b.n 800f44e errorcode |= HAL_CAN_ERROR_CRC; 800f442: 6a7b ldr r3, [r7, #36] @ 0x24 800f444: f443 7380 orr.w r3, r3, #256 @ 0x100 800f448: 627b str r3, [r7, #36] @ 0x24 break; 800f44a: e000 b.n 800f44e break; 800f44c: bf00 nop } /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); 800f44e: 687b ldr r3, [r7, #4] 800f450: 681b ldr r3, [r3, #0] 800f452: 699a ldr r2, [r3, #24] 800f454: 687b ldr r3, [r7, #4] 800f456: 681b ldr r3, [r3, #0] 800f458: f022 0270 bic.w r2, r2, #112 @ 0x70 800f45c: 619a str r2, [r3, #24] } } /* Clear ERRI Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); 800f45e: 687b ldr r3, [r7, #4] 800f460: 681b ldr r3, [r3, #0] 800f462: 2204 movs r2, #4 800f464: 605a str r2, [r3, #4] } /* Call the Error call Back in case of Errors */ if (errorcode != HAL_CAN_ERROR_NONE) 800f466: 6a7b ldr r3, [r7, #36] @ 0x24 800f468: 2b00 cmp r3, #0 800f46a: d008 beq.n 800f47e { /* Update error code in handle */ hcan->ErrorCode |= errorcode; 800f46c: 687b ldr r3, [r7, #4] 800f46e: 6a5a ldr r2, [r3, #36] @ 0x24 800f470: 6a7b ldr r3, [r7, #36] @ 0x24 800f472: 431a orrs r2, r3 800f474: 687b ldr r3, [r7, #4] 800f476: 625a str r2, [r3, #36] @ 0x24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->ErrorCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); 800f478: 6878 ldr r0, [r7, #4] 800f47a: f000 f867 bl 800f54c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } 800f47e: bf00 nop 800f480: 3728 adds r7, #40 @ 0x28 800f482: 46bd mov sp, r7 800f484: bd80 pop {r7, pc} 0800f486 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { 800f486: b480 push {r7} 800f488: b083 sub sp, #12 800f48a: af00 add r7, sp, #0 800f48c: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the user file */ } 800f48e: bf00 nop 800f490: 370c adds r7, #12 800f492: 46bd mov sp, r7 800f494: bc80 pop {r7} 800f496: 4770 bx lr 0800f498 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { 800f498: b480 push {r7} 800f49a: b083 sub sp, #12 800f49c: af00 add r7, sp, #0 800f49e: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the user file */ } 800f4a0: bf00 nop 800f4a2: 370c adds r7, #12 800f4a4: 46bd mov sp, r7 800f4a6: bc80 pop {r7} 800f4a8: 4770 bx lr 0800f4aa : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) { 800f4aa: b480 push {r7} 800f4ac: b083 sub sp, #12 800f4ae: af00 add r7, sp, #0 800f4b0: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the user file */ } 800f4b2: bf00 nop 800f4b4: 370c adds r7, #12 800f4b6: 46bd mov sp, r7 800f4b8: bc80 pop {r7} 800f4ba: 4770 bx lr 0800f4bc : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { 800f4bc: b480 push {r7} 800f4be: b083 sub sp, #12 800f4c0: af00 add r7, sp, #0 800f4c2: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } 800f4c4: bf00 nop 800f4c6: 370c adds r7, #12 800f4c8: 46bd mov sp, r7 800f4ca: bc80 pop {r7} 800f4cc: 4770 bx lr 0800f4ce : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { 800f4ce: b480 push {r7} 800f4d0: b083 sub sp, #12 800f4d2: af00 add r7, sp, #0 800f4d4: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } 800f4d6: bf00 nop 800f4d8: 370c adds r7, #12 800f4da: 46bd mov sp, r7 800f4dc: bc80 pop {r7} 800f4de: 4770 bx lr 0800f4e0 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { 800f4e0: b480 push {r7} 800f4e2: b083 sub sp, #12 800f4e4: af00 add r7, sp, #0 800f4e6: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } 800f4e8: bf00 nop 800f4ea: 370c adds r7, #12 800f4ec: 46bd mov sp, r7 800f4ee: bc80 pop {r7} 800f4f0: 4770 bx lr 0800f4f2 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { 800f4f2: b480 push {r7} 800f4f4: b083 sub sp, #12 800f4f6: af00 add r7, sp, #0 800f4f8: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the user file */ } 800f4fa: bf00 nop 800f4fc: 370c adds r7, #12 800f4fe: 46bd mov sp, r7 800f500: bc80 pop {r7} 800f502: 4770 bx lr 0800f504 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { 800f504: b480 push {r7} 800f506: b083 sub sp, #12 800f508: af00 add r7, sp, #0 800f50a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } 800f50c: bf00 nop 800f50e: 370c adds r7, #12 800f510: 46bd mov sp, r7 800f512: bc80 pop {r7} 800f514: 4770 bx lr 0800f516 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { 800f516: b480 push {r7} 800f518: b083 sub sp, #12 800f51a: af00 add r7, sp, #0 800f51c: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } 800f51e: bf00 nop 800f520: 370c adds r7, #12 800f522: 46bd mov sp, r7 800f524: bc80 pop {r7} 800f526: 4770 bx lr 0800f528 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { 800f528: b480 push {r7} 800f52a: b083 sub sp, #12 800f52c: af00 add r7, sp, #0 800f52e: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } 800f530: bf00 nop 800f532: 370c adds r7, #12 800f534: 46bd mov sp, r7 800f536: bc80 pop {r7} 800f538: 4770 bx lr 0800f53a : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { 800f53a: b480 push {r7} 800f53c: b083 sub sp, #12 800f53e: af00 add r7, sp, #0 800f540: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } 800f542: bf00 nop 800f544: 370c adds r7, #12 800f546: 46bd mov sp, r7 800f548: bc80 pop {r7} 800f54a: 4770 bx lr 0800f54c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { 800f54c: b480 push {r7} 800f54e: b083 sub sp, #12 800f550: af00 add r7, sp, #0 800f552: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } 800f554: bf00 nop 800f556: 370c adds r7, #12 800f558: 46bd mov sp, r7 800f55a: bc80 pop {r7} 800f55c: 4770 bx lr ... 0800f560 <__NVIC_SetPriorityGrouping>: { 800f560: b480 push {r7} 800f562: b085 sub sp, #20 800f564: af00 add r7, sp, #0 800f566: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800f568: 687b ldr r3, [r7, #4] 800f56a: f003 0307 and.w r3, r3, #7 800f56e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 800f570: 4b0c ldr r3, [pc, #48] @ (800f5a4 <__NVIC_SetPriorityGrouping+0x44>) 800f572: 68db ldr r3, [r3, #12] 800f574: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800f576: 68ba ldr r2, [r7, #8] 800f578: f64f 03ff movw r3, #63743 @ 0xf8ff 800f57c: 4013 ands r3, r2 800f57e: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800f580: 68fb ldr r3, [r7, #12] 800f582: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800f584: 68bb ldr r3, [r7, #8] 800f586: 4313 orrs r3, r2 reg_value = (reg_value | 800f588: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 800f58c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800f590: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800f592: 4a04 ldr r2, [pc, #16] @ (800f5a4 <__NVIC_SetPriorityGrouping+0x44>) 800f594: 68bb ldr r3, [r7, #8] 800f596: 60d3 str r3, [r2, #12] } 800f598: bf00 nop 800f59a: 3714 adds r7, #20 800f59c: 46bd mov sp, r7 800f59e: bc80 pop {r7} 800f5a0: 4770 bx lr 800f5a2: bf00 nop 800f5a4: e000ed00 .word 0xe000ed00 0800f5a8 <__NVIC_GetPriorityGrouping>: { 800f5a8: b480 push {r7} 800f5aa: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800f5ac: 4b04 ldr r3, [pc, #16] @ (800f5c0 <__NVIC_GetPriorityGrouping+0x18>) 800f5ae: 68db ldr r3, [r3, #12] 800f5b0: 0a1b lsrs r3, r3, #8 800f5b2: f003 0307 and.w r3, r3, #7 } 800f5b6: 4618 mov r0, r3 800f5b8: 46bd mov sp, r7 800f5ba: bc80 pop {r7} 800f5bc: 4770 bx lr 800f5be: bf00 nop 800f5c0: e000ed00 .word 0xe000ed00 0800f5c4 <__NVIC_EnableIRQ>: { 800f5c4: b480 push {r7} 800f5c6: b083 sub sp, #12 800f5c8: af00 add r7, sp, #0 800f5ca: 4603 mov r3, r0 800f5cc: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800f5ce: f997 3007 ldrsb.w r3, [r7, #7] 800f5d2: 2b00 cmp r3, #0 800f5d4: db0b blt.n 800f5ee <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800f5d6: 79fb ldrb r3, [r7, #7] 800f5d8: f003 021f and.w r2, r3, #31 800f5dc: 4906 ldr r1, [pc, #24] @ (800f5f8 <__NVIC_EnableIRQ+0x34>) 800f5de: f997 3007 ldrsb.w r3, [r7, #7] 800f5e2: 095b lsrs r3, r3, #5 800f5e4: 2001 movs r0, #1 800f5e6: fa00 f202 lsl.w r2, r0, r2 800f5ea: f841 2023 str.w r2, [r1, r3, lsl #2] } 800f5ee: bf00 nop 800f5f0: 370c adds r7, #12 800f5f2: 46bd mov sp, r7 800f5f4: bc80 pop {r7} 800f5f6: 4770 bx lr 800f5f8: e000e100 .word 0xe000e100 0800f5fc <__NVIC_DisableIRQ>: { 800f5fc: b480 push {r7} 800f5fe: b083 sub sp, #12 800f600: af00 add r7, sp, #0 800f602: 4603 mov r3, r0 800f604: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800f606: f997 3007 ldrsb.w r3, [r7, #7] 800f60a: 2b00 cmp r3, #0 800f60c: db12 blt.n 800f634 <__NVIC_DisableIRQ+0x38> NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800f60e: 79fb ldrb r3, [r7, #7] 800f610: f003 021f and.w r2, r3, #31 800f614: 490a ldr r1, [pc, #40] @ (800f640 <__NVIC_DisableIRQ+0x44>) 800f616: f997 3007 ldrsb.w r3, [r7, #7] 800f61a: 095b lsrs r3, r3, #5 800f61c: 2001 movs r0, #1 800f61e: fa00 f202 lsl.w r2, r0, r2 800f622: 3320 adds r3, #32 800f624: f841 2023 str.w r2, [r1, r3, lsl #2] __ASM volatile ("dsb 0xF":::"memory"); 800f628: f3bf 8f4f dsb sy } 800f62c: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 800f62e: f3bf 8f6f isb sy } 800f632: bf00 nop } 800f634: bf00 nop 800f636: 370c adds r7, #12 800f638: 46bd mov sp, r7 800f63a: bc80 pop {r7} 800f63c: 4770 bx lr 800f63e: bf00 nop 800f640: e000e100 .word 0xe000e100 0800f644 <__NVIC_SetPriority>: { 800f644: b480 push {r7} 800f646: b083 sub sp, #12 800f648: af00 add r7, sp, #0 800f64a: 4603 mov r3, r0 800f64c: 6039 str r1, [r7, #0] 800f64e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800f650: f997 3007 ldrsb.w r3, [r7, #7] 800f654: 2b00 cmp r3, #0 800f656: db0a blt.n 800f66e <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800f658: 683b ldr r3, [r7, #0] 800f65a: b2da uxtb r2, r3 800f65c: 490c ldr r1, [pc, #48] @ (800f690 <__NVIC_SetPriority+0x4c>) 800f65e: f997 3007 ldrsb.w r3, [r7, #7] 800f662: 0112 lsls r2, r2, #4 800f664: b2d2 uxtb r2, r2 800f666: 440b add r3, r1 800f668: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 800f66c: e00a b.n 800f684 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800f66e: 683b ldr r3, [r7, #0] 800f670: b2da uxtb r2, r3 800f672: 4908 ldr r1, [pc, #32] @ (800f694 <__NVIC_SetPriority+0x50>) 800f674: 79fb ldrb r3, [r7, #7] 800f676: f003 030f and.w r3, r3, #15 800f67a: 3b04 subs r3, #4 800f67c: 0112 lsls r2, r2, #4 800f67e: b2d2 uxtb r2, r2 800f680: 440b add r3, r1 800f682: 761a strb r2, [r3, #24] } 800f684: bf00 nop 800f686: 370c adds r7, #12 800f688: 46bd mov sp, r7 800f68a: bc80 pop {r7} 800f68c: 4770 bx lr 800f68e: bf00 nop 800f690: e000e100 .word 0xe000e100 800f694: e000ed00 .word 0xe000ed00 0800f698 : { 800f698: b480 push {r7} 800f69a: b089 sub sp, #36 @ 0x24 800f69c: af00 add r7, sp, #0 800f69e: 60f8 str r0, [r7, #12] 800f6a0: 60b9 str r1, [r7, #8] 800f6a2: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800f6a4: 68fb ldr r3, [r7, #12] 800f6a6: f003 0307 and.w r3, r3, #7 800f6aa: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 800f6ac: 69fb ldr r3, [r7, #28] 800f6ae: f1c3 0307 rsb r3, r3, #7 800f6b2: 2b04 cmp r3, #4 800f6b4: bf28 it cs 800f6b6: 2304 movcs r3, #4 800f6b8: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800f6ba: 69fb ldr r3, [r7, #28] 800f6bc: 3304 adds r3, #4 800f6be: 2b06 cmp r3, #6 800f6c0: d902 bls.n 800f6c8 800f6c2: 69fb ldr r3, [r7, #28] 800f6c4: 3b03 subs r3, #3 800f6c6: e000 b.n 800f6ca 800f6c8: 2300 movs r3, #0 800f6ca: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800f6cc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800f6d0: 69bb ldr r3, [r7, #24] 800f6d2: fa02 f303 lsl.w r3, r2, r3 800f6d6: 43da mvns r2, r3 800f6d8: 68bb ldr r3, [r7, #8] 800f6da: 401a ands r2, r3 800f6dc: 697b ldr r3, [r7, #20] 800f6de: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800f6e0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800f6e4: 697b ldr r3, [r7, #20] 800f6e6: fa01 f303 lsl.w r3, r1, r3 800f6ea: 43d9 mvns r1, r3 800f6ec: 687b ldr r3, [r7, #4] 800f6ee: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800f6f0: 4313 orrs r3, r2 } 800f6f2: 4618 mov r0, r3 800f6f4: 3724 adds r7, #36 @ 0x24 800f6f6: 46bd mov sp, r7 800f6f8: bc80 pop {r7} 800f6fa: 4770 bx lr 0800f6fc : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800f6fc: b580 push {r7, lr} 800f6fe: b082 sub sp, #8 800f700: af00 add r7, sp, #0 800f702: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 800f704: 687b ldr r3, [r7, #4] 800f706: 3b01 subs r3, #1 800f708: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800f70c: d301 bcc.n 800f712 { return (1UL); /* Reload value impossible */ 800f70e: 2301 movs r3, #1 800f710: e00f b.n 800f732 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800f712: 4a0a ldr r2, [pc, #40] @ (800f73c ) 800f714: 687b ldr r3, [r7, #4] 800f716: 3b01 subs r3, #1 800f718: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800f71a: 210f movs r1, #15 800f71c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800f720: f7ff ff90 bl 800f644 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800f724: 4b05 ldr r3, [pc, #20] @ (800f73c ) 800f726: 2200 movs r2, #0 800f728: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800f72a: 4b04 ldr r3, [pc, #16] @ (800f73c ) 800f72c: 2207 movs r2, #7 800f72e: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 800f730: 2300 movs r3, #0 } 800f732: 4618 mov r0, r3 800f734: 3708 adds r7, #8 800f736: 46bd mov sp, r7 800f738: bd80 pop {r7, pc} 800f73a: bf00 nop 800f73c: e000e010 .word 0xe000e010 0800f740 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 800f740: b580 push {r7, lr} 800f742: b082 sub sp, #8 800f744: af00 add r7, sp, #0 800f746: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800f748: 6878 ldr r0, [r7, #4] 800f74a: f7ff ff09 bl 800f560 <__NVIC_SetPriorityGrouping> } 800f74e: bf00 nop 800f750: 3708 adds r7, #8 800f752: 46bd mov sp, r7 800f754: bd80 pop {r7, pc} 0800f756 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800f756: b580 push {r7, lr} 800f758: b086 sub sp, #24 800f75a: af00 add r7, sp, #0 800f75c: 4603 mov r3, r0 800f75e: 60b9 str r1, [r7, #8] 800f760: 607a str r2, [r7, #4] 800f762: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 800f764: 2300 movs r3, #0 800f766: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800f768: f7ff ff1e bl 800f5a8 <__NVIC_GetPriorityGrouping> 800f76c: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800f76e: 687a ldr r2, [r7, #4] 800f770: 68b9 ldr r1, [r7, #8] 800f772: 6978 ldr r0, [r7, #20] 800f774: f7ff ff90 bl 800f698 800f778: 4602 mov r2, r0 800f77a: f997 300f ldrsb.w r3, [r7, #15] 800f77e: 4611 mov r1, r2 800f780: 4618 mov r0, r3 800f782: f7ff ff5f bl 800f644 <__NVIC_SetPriority> } 800f786: bf00 nop 800f788: 3718 adds r7, #24 800f78a: 46bd mov sp, r7 800f78c: bd80 pop {r7, pc} 0800f78e : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 800f78e: b580 push {r7, lr} 800f790: b082 sub sp, #8 800f792: af00 add r7, sp, #0 800f794: 4603 mov r3, r0 800f796: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800f798: f997 3007 ldrsb.w r3, [r7, #7] 800f79c: 4618 mov r0, r3 800f79e: f7ff ff11 bl 800f5c4 <__NVIC_EnableIRQ> } 800f7a2: bf00 nop 800f7a4: 3708 adds r7, #8 800f7a6: 46bd mov sp, r7 800f7a8: bd80 pop {r7, pc} 0800f7aa : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) { 800f7aa: b580 push {r7, lr} 800f7ac: b082 sub sp, #8 800f7ae: af00 add r7, sp, #0 800f7b0: 4603 mov r3, r0 800f7b2: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Disable interrupt */ NVIC_DisableIRQ(IRQn); 800f7b4: f997 3007 ldrsb.w r3, [r7, #7] 800f7b8: 4618 mov r0, r3 800f7ba: f7ff ff1f bl 800f5fc <__NVIC_DisableIRQ> } 800f7be: bf00 nop 800f7c0: 3708 adds r7, #8 800f7c2: 46bd mov sp, r7 800f7c4: bd80 pop {r7, pc} 0800f7c6 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800f7c6: b580 push {r7, lr} 800f7c8: b082 sub sp, #8 800f7ca: af00 add r7, sp, #0 800f7cc: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800f7ce: 6878 ldr r0, [r7, #4] 800f7d0: f7ff ff94 bl 800f6fc 800f7d4: 4603 mov r3, r0 } 800f7d6: 4618 mov r0, r3 800f7d8: 3708 adds r7, #8 800f7da: 46bd mov sp, r7 800f7dc: bd80 pop {r7, pc} 0800f7de : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 800f7de: b580 push {r7, lr} 800f7e0: b082 sub sp, #8 800f7e2: af00 add r7, sp, #0 800f7e4: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 800f7e6: 687b ldr r3, [r7, #4] 800f7e8: 2b00 cmp r3, #0 800f7ea: d101 bne.n 800f7f0 { return HAL_ERROR; 800f7ec: 2301 movs r3, #1 800f7ee: e00e b.n 800f80e } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 800f7f0: 687b ldr r3, [r7, #4] 800f7f2: 795b ldrb r3, [r3, #5] 800f7f4: b2db uxtb r3, r3 800f7f6: 2b00 cmp r3, #0 800f7f8: d105 bne.n 800f806 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 800f7fa: 687b ldr r3, [r7, #4] 800f7fc: 2200 movs r2, #0 800f7fe: 711a strb r2, [r3, #4] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 800f800: 6878 ldr r0, [r7, #4] 800f802: f7fa fcff bl 800a204 } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 800f806: 687b ldr r3, [r7, #4] 800f808: 2201 movs r2, #1 800f80a: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 800f80c: 2300 movs r3, #0 } 800f80e: 4618 mov r0, r3 800f810: 3708 adds r7, #8 800f812: 46bd mov sp, r7 800f814: bd80 pop {r7, pc} ... 0800f818 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 800f818: b480 push {r7} 800f81a: b085 sub sp, #20 800f81c: af00 add r7, sp, #0 800f81e: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 800f820: 2300 movs r3, #0 800f822: 60fb str r3, [r7, #12] /* Check the DMA handle allocation */ if(hdma == NULL) 800f824: 687b ldr r3, [r7, #4] 800f826: 2b00 cmp r3, #0 800f828: d101 bne.n 800f82e { return HAL_ERROR; 800f82a: 2301 movs r3, #1 800f82c: e059 b.n 800f8e2 assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); #if defined (DMA2) /* calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 800f82e: 687b ldr r3, [r7, #4] 800f830: 681b ldr r3, [r3, #0] 800f832: 461a mov r2, r3 800f834: 4b2d ldr r3, [pc, #180] @ (800f8ec ) 800f836: 429a cmp r2, r3 800f838: d80f bhi.n 800f85a { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 800f83a: 687b ldr r3, [r7, #4] 800f83c: 681b ldr r3, [r3, #0] 800f83e: 461a mov r2, r3 800f840: 4b2b ldr r3, [pc, #172] @ (800f8f0 ) 800f842: 4413 add r3, r2 800f844: 4a2b ldr r2, [pc, #172] @ (800f8f4 ) 800f846: fba2 2303 umull r2, r3, r2, r3 800f84a: 091b lsrs r3, r3, #4 800f84c: 009a lsls r2, r3, #2 800f84e: 687b ldr r3, [r7, #4] 800f850: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA1; 800f852: 687b ldr r3, [r7, #4] 800f854: 4a28 ldr r2, [pc, #160] @ (800f8f8 ) 800f856: 63da str r2, [r3, #60] @ 0x3c 800f858: e00e b.n 800f878 } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; 800f85a: 687b ldr r3, [r7, #4] 800f85c: 681b ldr r3, [r3, #0] 800f85e: 461a mov r2, r3 800f860: 4b26 ldr r3, [pc, #152] @ (800f8fc ) 800f862: 4413 add r3, r2 800f864: 4a23 ldr r2, [pc, #140] @ (800f8f4 ) 800f866: fba2 2303 umull r2, r3, r2, r3 800f86a: 091b lsrs r3, r3, #4 800f86c: 009a lsls r2, r3, #2 800f86e: 687b ldr r3, [r7, #4] 800f870: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA2; 800f872: 687b ldr r3, [r7, #4] 800f874: 4a22 ldr r2, [pc, #136] @ (800f900 ) 800f876: 63da str r2, [r3, #60] @ 0x3c hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; #endif /* DMA2 */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 800f878: 687b ldr r3, [r7, #4] 800f87a: 2202 movs r2, #2 800f87c: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Get the CR register value */ tmp = hdma->Instance->CCR; 800f880: 687b ldr r3, [r7, #4] 800f882: 681b ldr r3, [r3, #0] 800f884: 681b ldr r3, [r3, #0] 800f886: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 800f888: 68fb ldr r3, [r7, #12] 800f88a: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 800f88e: f023 0330 bic.w r3, r3, #48 @ 0x30 800f892: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 800f894: 687b ldr r3, [r7, #4] 800f896: 685a ldr r2, [r3, #4] hdma->Init.PeriphInc | hdma->Init.MemInc | 800f898: 687b ldr r3, [r7, #4] 800f89a: 689b ldr r3, [r3, #8] tmp |= hdma->Init.Direction | 800f89c: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 800f89e: 687b ldr r3, [r7, #4] 800f8a0: 68db ldr r3, [r3, #12] 800f8a2: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800f8a4: 687b ldr r3, [r7, #4] 800f8a6: 691b ldr r3, [r3, #16] hdma->Init.PeriphInc | hdma->Init.MemInc | 800f8a8: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800f8aa: 687b ldr r3, [r7, #4] 800f8ac: 695b ldr r3, [r3, #20] 800f8ae: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800f8b0: 687b ldr r3, [r7, #4] 800f8b2: 699b ldr r3, [r3, #24] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800f8b4: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800f8b6: 687b ldr r3, [r7, #4] 800f8b8: 69db ldr r3, [r3, #28] 800f8ba: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | 800f8bc: 68fa ldr r2, [r7, #12] 800f8be: 4313 orrs r3, r2 800f8c0: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; 800f8c2: 687b ldr r3, [r7, #4] 800f8c4: 681b ldr r3, [r3, #0] 800f8c6: 68fa ldr r2, [r7, #12] 800f8c8: 601a str r2, [r3, #0] /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800f8ca: 687b ldr r3, [r7, #4] 800f8cc: 2200 movs r2, #0 800f8ce: 639a str r2, [r3, #56] @ 0x38 /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 800f8d0: 687b ldr r3, [r7, #4] 800f8d2: 2201 movs r2, #1 800f8d4: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; 800f8d8: 687b ldr r3, [r7, #4] 800f8da: 2200 movs r2, #0 800f8dc: f883 2020 strb.w r2, [r3, #32] return HAL_OK; 800f8e0: 2300 movs r3, #0 } 800f8e2: 4618 mov r0, r3 800f8e4: 3714 adds r7, #20 800f8e6: 46bd mov sp, r7 800f8e8: bc80 pop {r7} 800f8ea: 4770 bx lr 800f8ec: 40020407 .word 0x40020407 800f8f0: bffdfff8 .word 0xbffdfff8 800f8f4: cccccccd .word 0xcccccccd 800f8f8: 40020000 .word 0x40020000 800f8fc: bffdfbf8 .word 0xbffdfbf8 800f900: 40020400 .word 0x40020400 0800f904 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 800f904: b580 push {r7, lr} 800f906: b086 sub sp, #24 800f908: af00 add r7, sp, #0 800f90a: 60f8 str r0, [r7, #12] 800f90c: 60b9 str r1, [r7, #8] 800f90e: 607a str r2, [r7, #4] 800f910: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800f912: 2300 movs r3, #0 800f914: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 800f916: 68fb ldr r3, [r7, #12] 800f918: f893 3020 ldrb.w r3, [r3, #32] 800f91c: 2b01 cmp r3, #1 800f91e: d101 bne.n 800f924 800f920: 2302 movs r3, #2 800f922: e04b b.n 800f9bc 800f924: 68fb ldr r3, [r7, #12] 800f926: 2201 movs r2, #1 800f928: f883 2020 strb.w r2, [r3, #32] if(HAL_DMA_STATE_READY == hdma->State) 800f92c: 68fb ldr r3, [r7, #12] 800f92e: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800f932: b2db uxtb r3, r3 800f934: 2b01 cmp r3, #1 800f936: d13a bne.n 800f9ae { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 800f938: 68fb ldr r3, [r7, #12] 800f93a: 2202 movs r2, #2 800f93c: f883 2021 strb.w r2, [r3, #33] @ 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800f940: 68fb ldr r3, [r7, #12] 800f942: 2200 movs r2, #0 800f944: 639a str r2, [r3, #56] @ 0x38 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 800f946: 68fb ldr r3, [r7, #12] 800f948: 681b ldr r3, [r3, #0] 800f94a: 681a ldr r2, [r3, #0] 800f94c: 68fb ldr r3, [r7, #12] 800f94e: 681b ldr r3, [r3, #0] 800f950: f022 0201 bic.w r2, r2, #1 800f954: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 800f956: 683b ldr r3, [r7, #0] 800f958: 687a ldr r2, [r7, #4] 800f95a: 68b9 ldr r1, [r7, #8] 800f95c: 68f8 ldr r0, [r7, #12] 800f95e: f000 fbb1 bl 80100c4 /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if(NULL != hdma->XferHalfCpltCallback) 800f962: 68fb ldr r3, [r7, #12] 800f964: 6adb ldr r3, [r3, #44] @ 0x2c 800f966: 2b00 cmp r3, #0 800f968: d008 beq.n 800f97c { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800f96a: 68fb ldr r3, [r7, #12] 800f96c: 681b ldr r3, [r3, #0] 800f96e: 681a ldr r2, [r3, #0] 800f970: 68fb ldr r3, [r7, #12] 800f972: 681b ldr r3, [r3, #0] 800f974: f042 020e orr.w r2, r2, #14 800f978: 601a str r2, [r3, #0] 800f97a: e00f b.n 800f99c } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800f97c: 68fb ldr r3, [r7, #12] 800f97e: 681b ldr r3, [r3, #0] 800f980: 681a ldr r2, [r3, #0] 800f982: 68fb ldr r3, [r7, #12] 800f984: 681b ldr r3, [r3, #0] 800f986: f022 0204 bic.w r2, r2, #4 800f98a: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 800f98c: 68fb ldr r3, [r7, #12] 800f98e: 681b ldr r3, [r3, #0] 800f990: 681a ldr r2, [r3, #0] 800f992: 68fb ldr r3, [r7, #12] 800f994: 681b ldr r3, [r3, #0] 800f996: f042 020a orr.w r2, r2, #10 800f99a: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 800f99c: 68fb ldr r3, [r7, #12] 800f99e: 681b ldr r3, [r3, #0] 800f9a0: 681a ldr r2, [r3, #0] 800f9a2: 68fb ldr r3, [r7, #12] 800f9a4: 681b ldr r3, [r3, #0] 800f9a6: f042 0201 orr.w r2, r2, #1 800f9aa: 601a str r2, [r3, #0] 800f9ac: e005 b.n 800f9ba } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); 800f9ae: 68fb ldr r3, [r7, #12] 800f9b0: 2200 movs r2, #0 800f9b2: f883 2020 strb.w r2, [r3, #32] /* Remain BUSY */ status = HAL_BUSY; 800f9b6: 2302 movs r3, #2 800f9b8: 75fb strb r3, [r7, #23] } return status; 800f9ba: 7dfb ldrb r3, [r7, #23] } 800f9bc: 4618 mov r0, r3 800f9be: 3718 adds r7, #24 800f9c0: 46bd mov sp, r7 800f9c2: bd80 pop {r7, pc} 0800f9c4 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 800f9c4: b480 push {r7} 800f9c6: b085 sub sp, #20 800f9c8: af00 add r7, sp, #0 800f9ca: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800f9cc: 2300 movs r3, #0 800f9ce: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 800f9d0: 687b ldr r3, [r7, #4] 800f9d2: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800f9d6: b2db uxtb r3, r3 800f9d8: 2b02 cmp r3, #2 800f9da: d008 beq.n 800f9ee { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800f9dc: 687b ldr r3, [r7, #4] 800f9de: 2204 movs r2, #4 800f9e0: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800f9e2: 687b ldr r3, [r7, #4] 800f9e4: 2200 movs r2, #0 800f9e6: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800f9ea: 2301 movs r3, #1 800f9ec: e020 b.n 800fa30 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800f9ee: 687b ldr r3, [r7, #4] 800f9f0: 681b ldr r3, [r3, #0] 800f9f2: 681a ldr r2, [r3, #0] 800f9f4: 687b ldr r3, [r7, #4] 800f9f6: 681b ldr r3, [r3, #0] 800f9f8: f022 020e bic.w r2, r2, #14 800f9fc: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800f9fe: 687b ldr r3, [r7, #4] 800fa00: 681b ldr r3, [r3, #0] 800fa02: 681a ldr r2, [r3, #0] 800fa04: 687b ldr r3, [r7, #4] 800fa06: 681b ldr r3, [r3, #0] 800fa08: f022 0201 bic.w r2, r2, #1 800fa0c: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 800fa0e: 687b ldr r3, [r7, #4] 800fa10: 6c1a ldr r2, [r3, #64] @ 0x40 800fa12: 687b ldr r3, [r7, #4] 800fa14: 6bdb ldr r3, [r3, #60] @ 0x3c 800fa16: 2101 movs r1, #1 800fa18: fa01 f202 lsl.w r2, r1, r2 800fa1c: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800fa1e: 687b ldr r3, [r7, #4] 800fa20: 2201 movs r2, #1 800fa22: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800fa26: 687b ldr r3, [r7, #4] 800fa28: 2200 movs r2, #0 800fa2a: f883 2020 strb.w r2, [r3, #32] return status; 800fa2e: 7bfb ldrb r3, [r7, #15] } 800fa30: 4618 mov r0, r3 800fa32: 3714 adds r7, #20 800fa34: 46bd mov sp, r7 800fa36: bc80 pop {r7} 800fa38: 4770 bx lr ... 0800fa3c : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 800fa3c: b580 push {r7, lr} 800fa3e: b084 sub sp, #16 800fa40: af00 add r7, sp, #0 800fa42: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800fa44: 2300 movs r3, #0 800fa46: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 800fa48: 687b ldr r3, [r7, #4] 800fa4a: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800fa4e: b2db uxtb r3, r3 800fa50: 2b02 cmp r3, #2 800fa52: d005 beq.n 800fa60 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800fa54: 687b ldr r3, [r7, #4] 800fa56: 2204 movs r2, #4 800fa58: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 800fa5a: 2301 movs r3, #1 800fa5c: 73fb strb r3, [r7, #15] 800fa5e: e0d6 b.n 800fc0e } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800fa60: 687b ldr r3, [r7, #4] 800fa62: 681b ldr r3, [r3, #0] 800fa64: 681a ldr r2, [r3, #0] 800fa66: 687b ldr r3, [r7, #4] 800fa68: 681b ldr r3, [r3, #0] 800fa6a: f022 020e bic.w r2, r2, #14 800fa6e: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800fa70: 687b ldr r3, [r7, #4] 800fa72: 681b ldr r3, [r3, #0] 800fa74: 681a ldr r2, [r3, #0] 800fa76: 687b ldr r3, [r7, #4] 800fa78: 681b ldr r3, [r3, #0] 800fa7a: f022 0201 bic.w r2, r2, #1 800fa7e: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 800fa80: 687b ldr r3, [r7, #4] 800fa82: 681b ldr r3, [r3, #0] 800fa84: 461a mov r2, r3 800fa86: 4b64 ldr r3, [pc, #400] @ (800fc18 ) 800fa88: 429a cmp r2, r3 800fa8a: d958 bls.n 800fb3e 800fa8c: 687b ldr r3, [r7, #4] 800fa8e: 681b ldr r3, [r3, #0] 800fa90: 4a62 ldr r2, [pc, #392] @ (800fc1c ) 800fa92: 4293 cmp r3, r2 800fa94: d04f beq.n 800fb36 800fa96: 687b ldr r3, [r7, #4] 800fa98: 681b ldr r3, [r3, #0] 800fa9a: 4a61 ldr r2, [pc, #388] @ (800fc20 ) 800fa9c: 4293 cmp r3, r2 800fa9e: d048 beq.n 800fb32 800faa0: 687b ldr r3, [r7, #4] 800faa2: 681b ldr r3, [r3, #0] 800faa4: 4a5f ldr r2, [pc, #380] @ (800fc24 ) 800faa6: 4293 cmp r3, r2 800faa8: d040 beq.n 800fb2c 800faaa: 687b ldr r3, [r7, #4] 800faac: 681b ldr r3, [r3, #0] 800faae: 4a5e ldr r2, [pc, #376] @ (800fc28 ) 800fab0: 4293 cmp r3, r2 800fab2: d038 beq.n 800fb26 800fab4: 687b ldr r3, [r7, #4] 800fab6: 681b ldr r3, [r3, #0] 800fab8: 4a5c ldr r2, [pc, #368] @ (800fc2c ) 800faba: 4293 cmp r3, r2 800fabc: d030 beq.n 800fb20 800fabe: 687b ldr r3, [r7, #4] 800fac0: 681b ldr r3, [r3, #0] 800fac2: 4a5b ldr r2, [pc, #364] @ (800fc30 ) 800fac4: 4293 cmp r3, r2 800fac6: d028 beq.n 800fb1a 800fac8: 687b ldr r3, [r7, #4] 800faca: 681b ldr r3, [r3, #0] 800facc: 4a52 ldr r2, [pc, #328] @ (800fc18 ) 800face: 4293 cmp r3, r2 800fad0: d020 beq.n 800fb14 800fad2: 687b ldr r3, [r7, #4] 800fad4: 681b ldr r3, [r3, #0] 800fad6: 4a57 ldr r2, [pc, #348] @ (800fc34 ) 800fad8: 4293 cmp r3, r2 800fada: d019 beq.n 800fb10 800fadc: 687b ldr r3, [r7, #4] 800fade: 681b ldr r3, [r3, #0] 800fae0: 4a55 ldr r2, [pc, #340] @ (800fc38 ) 800fae2: 4293 cmp r3, r2 800fae4: d012 beq.n 800fb0c 800fae6: 687b ldr r3, [r7, #4] 800fae8: 681b ldr r3, [r3, #0] 800faea: 4a54 ldr r2, [pc, #336] @ (800fc3c ) 800faec: 4293 cmp r3, r2 800faee: d00a beq.n 800fb06 800faf0: 687b ldr r3, [r7, #4] 800faf2: 681b ldr r3, [r3, #0] 800faf4: 4a52 ldr r2, [pc, #328] @ (800fc40 ) 800faf6: 4293 cmp r3, r2 800faf8: d102 bne.n 800fb00 800fafa: f44f 5380 mov.w r3, #4096 @ 0x1000 800fafe: e01b b.n 800fb38 800fb00: f44f 3380 mov.w r3, #65536 @ 0x10000 800fb04: e018 b.n 800fb38 800fb06: f44f 7380 mov.w r3, #256 @ 0x100 800fb0a: e015 b.n 800fb38 800fb0c: 2310 movs r3, #16 800fb0e: e013 b.n 800fb38 800fb10: 2301 movs r3, #1 800fb12: e011 b.n 800fb38 800fb14: f04f 7380 mov.w r3, #16777216 @ 0x1000000 800fb18: e00e b.n 800fb38 800fb1a: f44f 1380 mov.w r3, #1048576 @ 0x100000 800fb1e: e00b b.n 800fb38 800fb20: f44f 3380 mov.w r3, #65536 @ 0x10000 800fb24: e008 b.n 800fb38 800fb26: f44f 5380 mov.w r3, #4096 @ 0x1000 800fb2a: e005 b.n 800fb38 800fb2c: f44f 7380 mov.w r3, #256 @ 0x100 800fb30: e002 b.n 800fb38 800fb32: 2310 movs r3, #16 800fb34: e000 b.n 800fb38 800fb36: 2301 movs r3, #1 800fb38: 4a42 ldr r2, [pc, #264] @ (800fc44 ) 800fb3a: 6053 str r3, [r2, #4] 800fb3c: e057 b.n 800fbee 800fb3e: 687b ldr r3, [r7, #4] 800fb40: 681b ldr r3, [r3, #0] 800fb42: 4a36 ldr r2, [pc, #216] @ (800fc1c ) 800fb44: 4293 cmp r3, r2 800fb46: d04f beq.n 800fbe8 800fb48: 687b ldr r3, [r7, #4] 800fb4a: 681b ldr r3, [r3, #0] 800fb4c: 4a34 ldr r2, [pc, #208] @ (800fc20 ) 800fb4e: 4293 cmp r3, r2 800fb50: d048 beq.n 800fbe4 800fb52: 687b ldr r3, [r7, #4] 800fb54: 681b ldr r3, [r3, #0] 800fb56: 4a33 ldr r2, [pc, #204] @ (800fc24 ) 800fb58: 4293 cmp r3, r2 800fb5a: d040 beq.n 800fbde 800fb5c: 687b ldr r3, [r7, #4] 800fb5e: 681b ldr r3, [r3, #0] 800fb60: 4a31 ldr r2, [pc, #196] @ (800fc28 ) 800fb62: 4293 cmp r3, r2 800fb64: d038 beq.n 800fbd8 800fb66: 687b ldr r3, [r7, #4] 800fb68: 681b ldr r3, [r3, #0] 800fb6a: 4a30 ldr r2, [pc, #192] @ (800fc2c ) 800fb6c: 4293 cmp r3, r2 800fb6e: d030 beq.n 800fbd2 800fb70: 687b ldr r3, [r7, #4] 800fb72: 681b ldr r3, [r3, #0] 800fb74: 4a2e ldr r2, [pc, #184] @ (800fc30 ) 800fb76: 4293 cmp r3, r2 800fb78: d028 beq.n 800fbcc 800fb7a: 687b ldr r3, [r7, #4] 800fb7c: 681b ldr r3, [r3, #0] 800fb7e: 4a26 ldr r2, [pc, #152] @ (800fc18 ) 800fb80: 4293 cmp r3, r2 800fb82: d020 beq.n 800fbc6 800fb84: 687b ldr r3, [r7, #4] 800fb86: 681b ldr r3, [r3, #0] 800fb88: 4a2a ldr r2, [pc, #168] @ (800fc34 ) 800fb8a: 4293 cmp r3, r2 800fb8c: d019 beq.n 800fbc2 800fb8e: 687b ldr r3, [r7, #4] 800fb90: 681b ldr r3, [r3, #0] 800fb92: 4a29 ldr r2, [pc, #164] @ (800fc38 ) 800fb94: 4293 cmp r3, r2 800fb96: d012 beq.n 800fbbe 800fb98: 687b ldr r3, [r7, #4] 800fb9a: 681b ldr r3, [r3, #0] 800fb9c: 4a27 ldr r2, [pc, #156] @ (800fc3c ) 800fb9e: 4293 cmp r3, r2 800fba0: d00a beq.n 800fbb8 800fba2: 687b ldr r3, [r7, #4] 800fba4: 681b ldr r3, [r3, #0] 800fba6: 4a26 ldr r2, [pc, #152] @ (800fc40 ) 800fba8: 4293 cmp r3, r2 800fbaa: d102 bne.n 800fbb2 800fbac: f44f 5380 mov.w r3, #4096 @ 0x1000 800fbb0: e01b b.n 800fbea 800fbb2: f44f 3380 mov.w r3, #65536 @ 0x10000 800fbb6: e018 b.n 800fbea 800fbb8: f44f 7380 mov.w r3, #256 @ 0x100 800fbbc: e015 b.n 800fbea 800fbbe: 2310 movs r3, #16 800fbc0: e013 b.n 800fbea 800fbc2: 2301 movs r3, #1 800fbc4: e011 b.n 800fbea 800fbc6: f04f 7380 mov.w r3, #16777216 @ 0x1000000 800fbca: e00e b.n 800fbea 800fbcc: f44f 1380 mov.w r3, #1048576 @ 0x100000 800fbd0: e00b b.n 800fbea 800fbd2: f44f 3380 mov.w r3, #65536 @ 0x10000 800fbd6: e008 b.n 800fbea 800fbd8: f44f 5380 mov.w r3, #4096 @ 0x1000 800fbdc: e005 b.n 800fbea 800fbde: f44f 7380 mov.w r3, #256 @ 0x100 800fbe2: e002 b.n 800fbea 800fbe4: 2310 movs r3, #16 800fbe6: e000 b.n 800fbea 800fbe8: 2301 movs r3, #1 800fbea: 4a17 ldr r2, [pc, #92] @ (800fc48 ) 800fbec: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800fbee: 687b ldr r3, [r7, #4] 800fbf0: 2201 movs r2, #1 800fbf2: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800fbf6: 687b ldr r3, [r7, #4] 800fbf8: 2200 movs r2, #0 800fbfa: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 800fbfe: 687b ldr r3, [r7, #4] 800fc00: 6b5b ldr r3, [r3, #52] @ 0x34 800fc02: 2b00 cmp r3, #0 800fc04: d003 beq.n 800fc0e { hdma->XferAbortCallback(hdma); 800fc06: 687b ldr r3, [r7, #4] 800fc08: 6b5b ldr r3, [r3, #52] @ 0x34 800fc0a: 6878 ldr r0, [r7, #4] 800fc0c: 4798 blx r3 } } return status; 800fc0e: 7bfb ldrb r3, [r7, #15] } 800fc10: 4618 mov r0, r3 800fc12: 3710 adds r7, #16 800fc14: 46bd mov sp, r7 800fc16: bd80 pop {r7, pc} 800fc18: 40020080 .word 0x40020080 800fc1c: 40020008 .word 0x40020008 800fc20: 4002001c .word 0x4002001c 800fc24: 40020030 .word 0x40020030 800fc28: 40020044 .word 0x40020044 800fc2c: 40020058 .word 0x40020058 800fc30: 4002006c .word 0x4002006c 800fc34: 40020408 .word 0x40020408 800fc38: 4002041c .word 0x4002041c 800fc3c: 40020430 .word 0x40020430 800fc40: 40020444 .word 0x40020444 800fc44: 40020400 .word 0x40020400 800fc48: 40020000 .word 0x40020000 0800fc4c : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 800fc4c: b580 push {r7, lr} 800fc4e: b084 sub sp, #16 800fc50: af00 add r7, sp, #0 800fc52: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; 800fc54: 687b ldr r3, [r7, #4] 800fc56: 6bdb ldr r3, [r3, #60] @ 0x3c 800fc58: 681b ldr r3, [r3, #0] 800fc5a: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; 800fc5c: 687b ldr r3, [r7, #4] 800fc5e: 681b ldr r3, [r3, #0] 800fc60: 681b ldr r3, [r3, #0] 800fc62: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 800fc64: 687b ldr r3, [r7, #4] 800fc66: 6c1b ldr r3, [r3, #64] @ 0x40 800fc68: 2204 movs r2, #4 800fc6a: 409a lsls r2, r3 800fc6c: 68fb ldr r3, [r7, #12] 800fc6e: 4013 ands r3, r2 800fc70: 2b00 cmp r3, #0 800fc72: f000 80f1 beq.w 800fe58 800fc76: 68bb ldr r3, [r7, #8] 800fc78: f003 0304 and.w r3, r3, #4 800fc7c: 2b00 cmp r3, #0 800fc7e: f000 80eb beq.w 800fe58 { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 800fc82: 687b ldr r3, [r7, #4] 800fc84: 681b ldr r3, [r3, #0] 800fc86: 681b ldr r3, [r3, #0] 800fc88: f003 0320 and.w r3, r3, #32 800fc8c: 2b00 cmp r3, #0 800fc8e: d107 bne.n 800fca0 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800fc90: 687b ldr r3, [r7, #4] 800fc92: 681b ldr r3, [r3, #0] 800fc94: 681a ldr r2, [r3, #0] 800fc96: 687b ldr r3, [r7, #4] 800fc98: 681b ldr r3, [r3, #0] 800fc9a: f022 0204 bic.w r2, r2, #4 800fc9e: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); 800fca0: 687b ldr r3, [r7, #4] 800fca2: 681b ldr r3, [r3, #0] 800fca4: 461a mov r2, r3 800fca6: 4b5f ldr r3, [pc, #380] @ (800fe24 ) 800fca8: 429a cmp r2, r3 800fcaa: d958 bls.n 800fd5e 800fcac: 687b ldr r3, [r7, #4] 800fcae: 681b ldr r3, [r3, #0] 800fcb0: 4a5d ldr r2, [pc, #372] @ (800fe28 ) 800fcb2: 4293 cmp r3, r2 800fcb4: d04f beq.n 800fd56 800fcb6: 687b ldr r3, [r7, #4] 800fcb8: 681b ldr r3, [r3, #0] 800fcba: 4a5c ldr r2, [pc, #368] @ (800fe2c ) 800fcbc: 4293 cmp r3, r2 800fcbe: d048 beq.n 800fd52 800fcc0: 687b ldr r3, [r7, #4] 800fcc2: 681b ldr r3, [r3, #0] 800fcc4: 4a5a ldr r2, [pc, #360] @ (800fe30 ) 800fcc6: 4293 cmp r3, r2 800fcc8: d040 beq.n 800fd4c 800fcca: 687b ldr r3, [r7, #4] 800fccc: 681b ldr r3, [r3, #0] 800fcce: 4a59 ldr r2, [pc, #356] @ (800fe34 ) 800fcd0: 4293 cmp r3, r2 800fcd2: d038 beq.n 800fd46 800fcd4: 687b ldr r3, [r7, #4] 800fcd6: 681b ldr r3, [r3, #0] 800fcd8: 4a57 ldr r2, [pc, #348] @ (800fe38 ) 800fcda: 4293 cmp r3, r2 800fcdc: d030 beq.n 800fd40 800fcde: 687b ldr r3, [r7, #4] 800fce0: 681b ldr r3, [r3, #0] 800fce2: 4a56 ldr r2, [pc, #344] @ (800fe3c ) 800fce4: 4293 cmp r3, r2 800fce6: d028 beq.n 800fd3a 800fce8: 687b ldr r3, [r7, #4] 800fcea: 681b ldr r3, [r3, #0] 800fcec: 4a4d ldr r2, [pc, #308] @ (800fe24 ) 800fcee: 4293 cmp r3, r2 800fcf0: d020 beq.n 800fd34 800fcf2: 687b ldr r3, [r7, #4] 800fcf4: 681b ldr r3, [r3, #0] 800fcf6: 4a52 ldr r2, [pc, #328] @ (800fe40 ) 800fcf8: 4293 cmp r3, r2 800fcfa: d019 beq.n 800fd30 800fcfc: 687b ldr r3, [r7, #4] 800fcfe: 681b ldr r3, [r3, #0] 800fd00: 4a50 ldr r2, [pc, #320] @ (800fe44 ) 800fd02: 4293 cmp r3, r2 800fd04: d012 beq.n 800fd2c 800fd06: 687b ldr r3, [r7, #4] 800fd08: 681b ldr r3, [r3, #0] 800fd0a: 4a4f ldr r2, [pc, #316] @ (800fe48 ) 800fd0c: 4293 cmp r3, r2 800fd0e: d00a beq.n 800fd26 800fd10: 687b ldr r3, [r7, #4] 800fd12: 681b ldr r3, [r3, #0] 800fd14: 4a4d ldr r2, [pc, #308] @ (800fe4c ) 800fd16: 4293 cmp r3, r2 800fd18: d102 bne.n 800fd20 800fd1a: f44f 4380 mov.w r3, #16384 @ 0x4000 800fd1e: e01b b.n 800fd58 800fd20: f44f 2380 mov.w r3, #262144 @ 0x40000 800fd24: e018 b.n 800fd58 800fd26: f44f 6380 mov.w r3, #1024 @ 0x400 800fd2a: e015 b.n 800fd58 800fd2c: 2340 movs r3, #64 @ 0x40 800fd2e: e013 b.n 800fd58 800fd30: 2304 movs r3, #4 800fd32: e011 b.n 800fd58 800fd34: f04f 6380 mov.w r3, #67108864 @ 0x4000000 800fd38: e00e b.n 800fd58 800fd3a: f44f 0380 mov.w r3, #4194304 @ 0x400000 800fd3e: e00b b.n 800fd58 800fd40: f44f 2380 mov.w r3, #262144 @ 0x40000 800fd44: e008 b.n 800fd58 800fd46: f44f 4380 mov.w r3, #16384 @ 0x4000 800fd4a: e005 b.n 800fd58 800fd4c: f44f 6380 mov.w r3, #1024 @ 0x400 800fd50: e002 b.n 800fd58 800fd52: 2340 movs r3, #64 @ 0x40 800fd54: e000 b.n 800fd58 800fd56: 2304 movs r3, #4 800fd58: 4a3d ldr r2, [pc, #244] @ (800fe50 ) 800fd5a: 6053 str r3, [r2, #4] 800fd5c: e057 b.n 800fe0e 800fd5e: 687b ldr r3, [r7, #4] 800fd60: 681b ldr r3, [r3, #0] 800fd62: 4a31 ldr r2, [pc, #196] @ (800fe28 ) 800fd64: 4293 cmp r3, r2 800fd66: d04f beq.n 800fe08 800fd68: 687b ldr r3, [r7, #4] 800fd6a: 681b ldr r3, [r3, #0] 800fd6c: 4a2f ldr r2, [pc, #188] @ (800fe2c ) 800fd6e: 4293 cmp r3, r2 800fd70: d048 beq.n 800fe04 800fd72: 687b ldr r3, [r7, #4] 800fd74: 681b ldr r3, [r3, #0] 800fd76: 4a2e ldr r2, [pc, #184] @ (800fe30 ) 800fd78: 4293 cmp r3, r2 800fd7a: d040 beq.n 800fdfe 800fd7c: 687b ldr r3, [r7, #4] 800fd7e: 681b ldr r3, [r3, #0] 800fd80: 4a2c ldr r2, [pc, #176] @ (800fe34 ) 800fd82: 4293 cmp r3, r2 800fd84: d038 beq.n 800fdf8 800fd86: 687b ldr r3, [r7, #4] 800fd88: 681b ldr r3, [r3, #0] 800fd8a: 4a2b ldr r2, [pc, #172] @ (800fe38 ) 800fd8c: 4293 cmp r3, r2 800fd8e: d030 beq.n 800fdf2 800fd90: 687b ldr r3, [r7, #4] 800fd92: 681b ldr r3, [r3, #0] 800fd94: 4a29 ldr r2, [pc, #164] @ (800fe3c ) 800fd96: 4293 cmp r3, r2 800fd98: d028 beq.n 800fdec 800fd9a: 687b ldr r3, [r7, #4] 800fd9c: 681b ldr r3, [r3, #0] 800fd9e: 4a21 ldr r2, [pc, #132] @ (800fe24 ) 800fda0: 4293 cmp r3, r2 800fda2: d020 beq.n 800fde6 800fda4: 687b ldr r3, [r7, #4] 800fda6: 681b ldr r3, [r3, #0] 800fda8: 4a25 ldr r2, [pc, #148] @ (800fe40 ) 800fdaa: 4293 cmp r3, r2 800fdac: d019 beq.n 800fde2 800fdae: 687b ldr r3, [r7, #4] 800fdb0: 681b ldr r3, [r3, #0] 800fdb2: 4a24 ldr r2, [pc, #144] @ (800fe44 ) 800fdb4: 4293 cmp r3, r2 800fdb6: d012 beq.n 800fdde 800fdb8: 687b ldr r3, [r7, #4] 800fdba: 681b ldr r3, [r3, #0] 800fdbc: 4a22 ldr r2, [pc, #136] @ (800fe48 ) 800fdbe: 4293 cmp r3, r2 800fdc0: d00a beq.n 800fdd8 800fdc2: 687b ldr r3, [r7, #4] 800fdc4: 681b ldr r3, [r3, #0] 800fdc6: 4a21 ldr r2, [pc, #132] @ (800fe4c ) 800fdc8: 4293 cmp r3, r2 800fdca: d102 bne.n 800fdd2 800fdcc: f44f 4380 mov.w r3, #16384 @ 0x4000 800fdd0: e01b b.n 800fe0a 800fdd2: f44f 2380 mov.w r3, #262144 @ 0x40000 800fdd6: e018 b.n 800fe0a 800fdd8: f44f 6380 mov.w r3, #1024 @ 0x400 800fddc: e015 b.n 800fe0a 800fdde: 2340 movs r3, #64 @ 0x40 800fde0: e013 b.n 800fe0a 800fde2: 2304 movs r3, #4 800fde4: e011 b.n 800fe0a 800fde6: f04f 6380 mov.w r3, #67108864 @ 0x4000000 800fdea: e00e b.n 800fe0a 800fdec: f44f 0380 mov.w r3, #4194304 @ 0x400000 800fdf0: e00b b.n 800fe0a 800fdf2: f44f 2380 mov.w r3, #262144 @ 0x40000 800fdf6: e008 b.n 800fe0a 800fdf8: f44f 4380 mov.w r3, #16384 @ 0x4000 800fdfc: e005 b.n 800fe0a 800fdfe: f44f 6380 mov.w r3, #1024 @ 0x400 800fe02: e002 b.n 800fe0a 800fe04: 2340 movs r3, #64 @ 0x40 800fe06: e000 b.n 800fe0a 800fe08: 2304 movs r3, #4 800fe0a: 4a12 ldr r2, [pc, #72] @ (800fe54 ) 800fe0c: 6053 str r3, [r2, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 800fe0e: 687b ldr r3, [r7, #4] 800fe10: 6adb ldr r3, [r3, #44] @ 0x2c 800fe12: 2b00 cmp r3, #0 800fe14: f000 8136 beq.w 8010084 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800fe18: 687b ldr r3, [r7, #4] 800fe1a: 6adb ldr r3, [r3, #44] @ 0x2c 800fe1c: 6878 ldr r0, [r7, #4] 800fe1e: 4798 blx r3 if(hdma->XferHalfCpltCallback != NULL) 800fe20: e130 b.n 8010084 800fe22: bf00 nop 800fe24: 40020080 .word 0x40020080 800fe28: 40020008 .word 0x40020008 800fe2c: 4002001c .word 0x4002001c 800fe30: 40020030 .word 0x40020030 800fe34: 40020044 .word 0x40020044 800fe38: 40020058 .word 0x40020058 800fe3c: 4002006c .word 0x4002006c 800fe40: 40020408 .word 0x40020408 800fe44: 4002041c .word 0x4002041c 800fe48: 40020430 .word 0x40020430 800fe4c: 40020444 .word 0x40020444 800fe50: 40020400 .word 0x40020400 800fe54: 40020000 .word 0x40020000 } } /* Transfer Complete Interrupt management ***********************************/ else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) 800fe58: 687b ldr r3, [r7, #4] 800fe5a: 6c1b ldr r3, [r3, #64] @ 0x40 800fe5c: 2202 movs r2, #2 800fe5e: 409a lsls r2, r3 800fe60: 68fb ldr r3, [r7, #12] 800fe62: 4013 ands r3, r2 800fe64: 2b00 cmp r3, #0 800fe66: f000 80dd beq.w 8010024 800fe6a: 68bb ldr r3, [r7, #8] 800fe6c: f003 0302 and.w r3, r3, #2 800fe70: 2b00 cmp r3, #0 800fe72: f000 80d7 beq.w 8010024 { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 800fe76: 687b ldr r3, [r7, #4] 800fe78: 681b ldr r3, [r3, #0] 800fe7a: 681b ldr r3, [r3, #0] 800fe7c: f003 0320 and.w r3, r3, #32 800fe80: 2b00 cmp r3, #0 800fe82: d10b bne.n 800fe9c { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 800fe84: 687b ldr r3, [r7, #4] 800fe86: 681b ldr r3, [r3, #0] 800fe88: 681a ldr r2, [r3, #0] 800fe8a: 687b ldr r3, [r7, #4] 800fe8c: 681b ldr r3, [r3, #0] 800fe8e: f022 020a bic.w r2, r2, #10 800fe92: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800fe94: 687b ldr r3, [r7, #4] 800fe96: 2201 movs r2, #1 800fe98: f883 2021 strb.w r2, [r3, #33] @ 0x21 } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 800fe9c: 687b ldr r3, [r7, #4] 800fe9e: 681b ldr r3, [r3, #0] 800fea0: 461a mov r2, r3 800fea2: 4b7b ldr r3, [pc, #492] @ (8010090 ) 800fea4: 429a cmp r2, r3 800fea6: d958 bls.n 800ff5a 800fea8: 687b ldr r3, [r7, #4] 800feaa: 681b ldr r3, [r3, #0] 800feac: 4a79 ldr r2, [pc, #484] @ (8010094 ) 800feae: 4293 cmp r3, r2 800feb0: d04f beq.n 800ff52 800feb2: 687b ldr r3, [r7, #4] 800feb4: 681b ldr r3, [r3, #0] 800feb6: 4a78 ldr r2, [pc, #480] @ (8010098 ) 800feb8: 4293 cmp r3, r2 800feba: d048 beq.n 800ff4e 800febc: 687b ldr r3, [r7, #4] 800febe: 681b ldr r3, [r3, #0] 800fec0: 4a76 ldr r2, [pc, #472] @ (801009c ) 800fec2: 4293 cmp r3, r2 800fec4: d040 beq.n 800ff48 800fec6: 687b ldr r3, [r7, #4] 800fec8: 681b ldr r3, [r3, #0] 800feca: 4a75 ldr r2, [pc, #468] @ (80100a0 ) 800fecc: 4293 cmp r3, r2 800fece: d038 beq.n 800ff42 800fed0: 687b ldr r3, [r7, #4] 800fed2: 681b ldr r3, [r3, #0] 800fed4: 4a73 ldr r2, [pc, #460] @ (80100a4 ) 800fed6: 4293 cmp r3, r2 800fed8: d030 beq.n 800ff3c 800feda: 687b ldr r3, [r7, #4] 800fedc: 681b ldr r3, [r3, #0] 800fede: 4a72 ldr r2, [pc, #456] @ (80100a8 ) 800fee0: 4293 cmp r3, r2 800fee2: d028 beq.n 800ff36 800fee4: 687b ldr r3, [r7, #4] 800fee6: 681b ldr r3, [r3, #0] 800fee8: 4a69 ldr r2, [pc, #420] @ (8010090 ) 800feea: 4293 cmp r3, r2 800feec: d020 beq.n 800ff30 800feee: 687b ldr r3, [r7, #4] 800fef0: 681b ldr r3, [r3, #0] 800fef2: 4a6e ldr r2, [pc, #440] @ (80100ac ) 800fef4: 4293 cmp r3, r2 800fef6: d019 beq.n 800ff2c 800fef8: 687b ldr r3, [r7, #4] 800fefa: 681b ldr r3, [r3, #0] 800fefc: 4a6c ldr r2, [pc, #432] @ (80100b0 ) 800fefe: 4293 cmp r3, r2 800ff00: d012 beq.n 800ff28 800ff02: 687b ldr r3, [r7, #4] 800ff04: 681b ldr r3, [r3, #0] 800ff06: 4a6b ldr r2, [pc, #428] @ (80100b4 ) 800ff08: 4293 cmp r3, r2 800ff0a: d00a beq.n 800ff22 800ff0c: 687b ldr r3, [r7, #4] 800ff0e: 681b ldr r3, [r3, #0] 800ff10: 4a69 ldr r2, [pc, #420] @ (80100b8 ) 800ff12: 4293 cmp r3, r2 800ff14: d102 bne.n 800ff1c 800ff16: f44f 5300 mov.w r3, #8192 @ 0x2000 800ff1a: e01b b.n 800ff54 800ff1c: f44f 3300 mov.w r3, #131072 @ 0x20000 800ff20: e018 b.n 800ff54 800ff22: f44f 7300 mov.w r3, #512 @ 0x200 800ff26: e015 b.n 800ff54 800ff28: 2320 movs r3, #32 800ff2a: e013 b.n 800ff54 800ff2c: 2302 movs r3, #2 800ff2e: e011 b.n 800ff54 800ff30: f04f 7300 mov.w r3, #33554432 @ 0x2000000 800ff34: e00e b.n 800ff54 800ff36: f44f 1300 mov.w r3, #2097152 @ 0x200000 800ff3a: e00b b.n 800ff54 800ff3c: f44f 3300 mov.w r3, #131072 @ 0x20000 800ff40: e008 b.n 800ff54 800ff42: f44f 5300 mov.w r3, #8192 @ 0x2000 800ff46: e005 b.n 800ff54 800ff48: f44f 7300 mov.w r3, #512 @ 0x200 800ff4c: e002 b.n 800ff54 800ff4e: 2320 movs r3, #32 800ff50: e000 b.n 800ff54 800ff52: 2302 movs r3, #2 800ff54: 4a59 ldr r2, [pc, #356] @ (80100bc ) 800ff56: 6053 str r3, [r2, #4] 800ff58: e057 b.n 801000a 800ff5a: 687b ldr r3, [r7, #4] 800ff5c: 681b ldr r3, [r3, #0] 800ff5e: 4a4d ldr r2, [pc, #308] @ (8010094 ) 800ff60: 4293 cmp r3, r2 800ff62: d04f beq.n 8010004 800ff64: 687b ldr r3, [r7, #4] 800ff66: 681b ldr r3, [r3, #0] 800ff68: 4a4b ldr r2, [pc, #300] @ (8010098 ) 800ff6a: 4293 cmp r3, r2 800ff6c: d048 beq.n 8010000 800ff6e: 687b ldr r3, [r7, #4] 800ff70: 681b ldr r3, [r3, #0] 800ff72: 4a4a ldr r2, [pc, #296] @ (801009c ) 800ff74: 4293 cmp r3, r2 800ff76: d040 beq.n 800fffa 800ff78: 687b ldr r3, [r7, #4] 800ff7a: 681b ldr r3, [r3, #0] 800ff7c: 4a48 ldr r2, [pc, #288] @ (80100a0 ) 800ff7e: 4293 cmp r3, r2 800ff80: d038 beq.n 800fff4 800ff82: 687b ldr r3, [r7, #4] 800ff84: 681b ldr r3, [r3, #0] 800ff86: 4a47 ldr r2, [pc, #284] @ (80100a4 ) 800ff88: 4293 cmp r3, r2 800ff8a: d030 beq.n 800ffee 800ff8c: 687b ldr r3, [r7, #4] 800ff8e: 681b ldr r3, [r3, #0] 800ff90: 4a45 ldr r2, [pc, #276] @ (80100a8 ) 800ff92: 4293 cmp r3, r2 800ff94: d028 beq.n 800ffe8 800ff96: 687b ldr r3, [r7, #4] 800ff98: 681b ldr r3, [r3, #0] 800ff9a: 4a3d ldr r2, [pc, #244] @ (8010090 ) 800ff9c: 4293 cmp r3, r2 800ff9e: d020 beq.n 800ffe2 800ffa0: 687b ldr r3, [r7, #4] 800ffa2: 681b ldr r3, [r3, #0] 800ffa4: 4a41 ldr r2, [pc, #260] @ (80100ac ) 800ffa6: 4293 cmp r3, r2 800ffa8: d019 beq.n 800ffde 800ffaa: 687b ldr r3, [r7, #4] 800ffac: 681b ldr r3, [r3, #0] 800ffae: 4a40 ldr r2, [pc, #256] @ (80100b0 ) 800ffb0: 4293 cmp r3, r2 800ffb2: d012 beq.n 800ffda 800ffb4: 687b ldr r3, [r7, #4] 800ffb6: 681b ldr r3, [r3, #0] 800ffb8: 4a3e ldr r2, [pc, #248] @ (80100b4 ) 800ffba: 4293 cmp r3, r2 800ffbc: d00a beq.n 800ffd4 800ffbe: 687b ldr r3, [r7, #4] 800ffc0: 681b ldr r3, [r3, #0] 800ffc2: 4a3d ldr r2, [pc, #244] @ (80100b8 ) 800ffc4: 4293 cmp r3, r2 800ffc6: d102 bne.n 800ffce 800ffc8: f44f 5300 mov.w r3, #8192 @ 0x2000 800ffcc: e01b b.n 8010006 800ffce: f44f 3300 mov.w r3, #131072 @ 0x20000 800ffd2: e018 b.n 8010006 800ffd4: f44f 7300 mov.w r3, #512 @ 0x200 800ffd8: e015 b.n 8010006 800ffda: 2320 movs r3, #32 800ffdc: e013 b.n 8010006 800ffde: 2302 movs r3, #2 800ffe0: e011 b.n 8010006 800ffe2: f04f 7300 mov.w r3, #33554432 @ 0x2000000 800ffe6: e00e b.n 8010006 800ffe8: f44f 1300 mov.w r3, #2097152 @ 0x200000 800ffec: e00b b.n 8010006 800ffee: f44f 3300 mov.w r3, #131072 @ 0x20000 800fff2: e008 b.n 8010006 800fff4: f44f 5300 mov.w r3, #8192 @ 0x2000 800fff8: e005 b.n 8010006 800fffa: f44f 7300 mov.w r3, #512 @ 0x200 800fffe: e002 b.n 8010006 8010000: 2320 movs r3, #32 8010002: e000 b.n 8010006 8010004: 2302 movs r3, #2 8010006: 4a2e ldr r2, [pc, #184] @ (80100c0 ) 8010008: 6053 str r3, [r2, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 801000a: 687b ldr r3, [r7, #4] 801000c: 2200 movs r2, #0 801000e: f883 2020 strb.w r2, [r3, #32] if(hdma->XferCpltCallback != NULL) 8010012: 687b ldr r3, [r7, #4] 8010014: 6a9b ldr r3, [r3, #40] @ 0x28 8010016: 2b00 cmp r3, #0 8010018: d034 beq.n 8010084 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 801001a: 687b ldr r3, [r7, #4] 801001c: 6a9b ldr r3, [r3, #40] @ 0x28 801001e: 6878 ldr r0, [r7, #4] 8010020: 4798 blx r3 if(hdma->XferCpltCallback != NULL) 8010022: e02f b.n 8010084 } } /* Transfer Error Interrupt management **************************************/ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) 8010024: 687b ldr r3, [r7, #4] 8010026: 6c1b ldr r3, [r3, #64] @ 0x40 8010028: 2208 movs r2, #8 801002a: 409a lsls r2, r3 801002c: 68fb ldr r3, [r7, #12] 801002e: 4013 ands r3, r2 8010030: 2b00 cmp r3, #0 8010032: d028 beq.n 8010086 8010034: 68bb ldr r3, [r7, #8] 8010036: f003 0308 and.w r3, r3, #8 801003a: 2b00 cmp r3, #0 801003c: d023 beq.n 8010086 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 801003e: 687b ldr r3, [r7, #4] 8010040: 681b ldr r3, [r3, #0] 8010042: 681a ldr r2, [r3, #0] 8010044: 687b ldr r3, [r7, #4] 8010046: 681b ldr r3, [r3, #0] 8010048: f022 020e bic.w r2, r2, #14 801004c: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 801004e: 687b ldr r3, [r7, #4] 8010050: 6c1a ldr r2, [r3, #64] @ 0x40 8010052: 687b ldr r3, [r7, #4] 8010054: 6bdb ldr r3, [r3, #60] @ 0x3c 8010056: 2101 movs r1, #1 8010058: fa01 f202 lsl.w r2, r1, r2 801005c: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 801005e: 687b ldr r3, [r7, #4] 8010060: 2201 movs r2, #1 8010062: 639a str r2, [r3, #56] @ 0x38 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8010064: 687b ldr r3, [r7, #4] 8010066: 2201 movs r2, #1 8010068: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 801006c: 687b ldr r3, [r7, #4] 801006e: 2200 movs r2, #0 8010070: f883 2020 strb.w r2, [r3, #32] if (hdma->XferErrorCallback != NULL) 8010074: 687b ldr r3, [r7, #4] 8010076: 6b1b ldr r3, [r3, #48] @ 0x30 8010078: 2b00 cmp r3, #0 801007a: d004 beq.n 8010086 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 801007c: 687b ldr r3, [r7, #4] 801007e: 6b1b ldr r3, [r3, #48] @ 0x30 8010080: 6878 ldr r0, [r7, #4] 8010082: 4798 blx r3 } } return; 8010084: bf00 nop 8010086: bf00 nop } 8010088: 3710 adds r7, #16 801008a: 46bd mov sp, r7 801008c: bd80 pop {r7, pc} 801008e: bf00 nop 8010090: 40020080 .word 0x40020080 8010094: 40020008 .word 0x40020008 8010098: 4002001c .word 0x4002001c 801009c: 40020030 .word 0x40020030 80100a0: 40020044 .word 0x40020044 80100a4: 40020058 .word 0x40020058 80100a8: 4002006c .word 0x4002006c 80100ac: 40020408 .word 0x40020408 80100b0: 4002041c .word 0x4002041c 80100b4: 40020430 .word 0x40020430 80100b8: 40020444 .word 0x40020444 80100bc: 40020400 .word 0x40020400 80100c0: 40020000 .word 0x40020000 080100c4 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 80100c4: b480 push {r7} 80100c6: b085 sub sp, #20 80100c8: af00 add r7, sp, #0 80100ca: 60f8 str r0, [r7, #12] 80100cc: 60b9 str r1, [r7, #8] 80100ce: 607a str r2, [r7, #4] 80100d0: 603b str r3, [r7, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 80100d2: 68fb ldr r3, [r7, #12] 80100d4: 6c1a ldr r2, [r3, #64] @ 0x40 80100d6: 68fb ldr r3, [r7, #12] 80100d8: 6bdb ldr r3, [r3, #60] @ 0x3c 80100da: 2101 movs r1, #1 80100dc: fa01 f202 lsl.w r2, r1, r2 80100e0: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 80100e2: 68fb ldr r3, [r7, #12] 80100e4: 681b ldr r3, [r3, #0] 80100e6: 683a ldr r2, [r7, #0] 80100e8: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 80100ea: 68fb ldr r3, [r7, #12] 80100ec: 685b ldr r3, [r3, #4] 80100ee: 2b10 cmp r3, #16 80100f0: d108 bne.n 8010104 { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 80100f2: 68fb ldr r3, [r7, #12] 80100f4: 681b ldr r3, [r3, #0] 80100f6: 687a ldr r2, [r7, #4] 80100f8: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; 80100fa: 68fb ldr r3, [r7, #12] 80100fc: 681b ldr r3, [r3, #0] 80100fe: 68ba ldr r2, [r7, #8] 8010100: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } 8010102: e007 b.n 8010114 hdma->Instance->CPAR = SrcAddress; 8010104: 68fb ldr r3, [r7, #12] 8010106: 681b ldr r3, [r3, #0] 8010108: 68ba ldr r2, [r7, #8] 801010a: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; 801010c: 68fb ldr r3, [r7, #12] 801010e: 681b ldr r3, [r3, #0] 8010110: 687a ldr r2, [r7, #4] 8010112: 60da str r2, [r3, #12] } 8010114: bf00 nop 8010116: 3714 adds r7, #20 8010118: 46bd mov sp, r7 801011a: bc80 pop {r7} 801011c: 4770 bx lr ... 08010120 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8010120: b480 push {r7} 8010122: b08b sub sp, #44 @ 0x2c 8010124: af00 add r7, sp, #0 8010126: 6078 str r0, [r7, #4] 8010128: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 801012a: 2300 movs r3, #0 801012c: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 801012e: 2300 movs r3, #0 8010130: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8010132: e169 b.n 8010408 { /* Get the IO position */ ioposition = (0x01uL << position); 8010134: 2201 movs r2, #1 8010136: 6a7b ldr r3, [r7, #36] @ 0x24 8010138: fa02 f303 lsl.w r3, r2, r3 801013c: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 801013e: 683b ldr r3, [r7, #0] 8010140: 681b ldr r3, [r3, #0] 8010142: 69fa ldr r2, [r7, #28] 8010144: 4013 ands r3, r2 8010146: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8010148: 69ba ldr r2, [r7, #24] 801014a: 69fb ldr r3, [r7, #28] 801014c: 429a cmp r2, r3 801014e: f040 8158 bne.w 8010402 { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 8010152: 683b ldr r3, [r7, #0] 8010154: 685b ldr r3, [r3, #4] 8010156: 4a9a ldr r2, [pc, #616] @ (80103c0 ) 8010158: 4293 cmp r3, r2 801015a: d05e beq.n 801021a 801015c: 4a98 ldr r2, [pc, #608] @ (80103c0 ) 801015e: 4293 cmp r3, r2 8010160: d875 bhi.n 801024e 8010162: 4a98 ldr r2, [pc, #608] @ (80103c4 ) 8010164: 4293 cmp r3, r2 8010166: d058 beq.n 801021a 8010168: 4a96 ldr r2, [pc, #600] @ (80103c4 ) 801016a: 4293 cmp r3, r2 801016c: d86f bhi.n 801024e 801016e: 4a96 ldr r2, [pc, #600] @ (80103c8 ) 8010170: 4293 cmp r3, r2 8010172: d052 beq.n 801021a 8010174: 4a94 ldr r2, [pc, #592] @ (80103c8 ) 8010176: 4293 cmp r3, r2 8010178: d869 bhi.n 801024e 801017a: 4a94 ldr r2, [pc, #592] @ (80103cc ) 801017c: 4293 cmp r3, r2 801017e: d04c beq.n 801021a 8010180: 4a92 ldr r2, [pc, #584] @ (80103cc ) 8010182: 4293 cmp r3, r2 8010184: d863 bhi.n 801024e 8010186: 4a92 ldr r2, [pc, #584] @ (80103d0 ) 8010188: 4293 cmp r3, r2 801018a: d046 beq.n 801021a 801018c: 4a90 ldr r2, [pc, #576] @ (80103d0 ) 801018e: 4293 cmp r3, r2 8010190: d85d bhi.n 801024e 8010192: 2b12 cmp r3, #18 8010194: d82a bhi.n 80101ec 8010196: 2b12 cmp r3, #18 8010198: d859 bhi.n 801024e 801019a: a201 add r2, pc, #4 @ (adr r2, 80101a0 ) 801019c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80101a0: 0801021b .word 0x0801021b 80101a4: 080101f5 .word 0x080101f5 80101a8: 08010207 .word 0x08010207 80101ac: 08010249 .word 0x08010249 80101b0: 0801024f .word 0x0801024f 80101b4: 0801024f .word 0x0801024f 80101b8: 0801024f .word 0x0801024f 80101bc: 0801024f .word 0x0801024f 80101c0: 0801024f .word 0x0801024f 80101c4: 0801024f .word 0x0801024f 80101c8: 0801024f .word 0x0801024f 80101cc: 0801024f .word 0x0801024f 80101d0: 0801024f .word 0x0801024f 80101d4: 0801024f .word 0x0801024f 80101d8: 0801024f .word 0x0801024f 80101dc: 0801024f .word 0x0801024f 80101e0: 0801024f .word 0x0801024f 80101e4: 080101fd .word 0x080101fd 80101e8: 08010211 .word 0x08010211 80101ec: 4a79 ldr r2, [pc, #484] @ (80103d4 ) 80101ee: 4293 cmp r3, r2 80101f0: d013 beq.n 801021a config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 80101f2: e02c b.n 801024e config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 80101f4: 683b ldr r3, [r7, #0] 80101f6: 68db ldr r3, [r3, #12] 80101f8: 623b str r3, [r7, #32] break; 80101fa: e029 b.n 8010250 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 80101fc: 683b ldr r3, [r7, #0] 80101fe: 68db ldr r3, [r3, #12] 8010200: 3304 adds r3, #4 8010202: 623b str r3, [r7, #32] break; 8010204: e024 b.n 8010250 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8010206: 683b ldr r3, [r7, #0] 8010208: 68db ldr r3, [r3, #12] 801020a: 3308 adds r3, #8 801020c: 623b str r3, [r7, #32] break; 801020e: e01f b.n 8010250 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8010210: 683b ldr r3, [r7, #0] 8010212: 68db ldr r3, [r3, #12] 8010214: 330c adds r3, #12 8010216: 623b str r3, [r7, #32] break; 8010218: e01a b.n 8010250 if (GPIO_Init->Pull == GPIO_NOPULL) 801021a: 683b ldr r3, [r7, #0] 801021c: 689b ldr r3, [r3, #8] 801021e: 2b00 cmp r3, #0 8010220: d102 bne.n 8010228 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8010222: 2304 movs r3, #4 8010224: 623b str r3, [r7, #32] break; 8010226: e013 b.n 8010250 else if (GPIO_Init->Pull == GPIO_PULLUP) 8010228: 683b ldr r3, [r7, #0] 801022a: 689b ldr r3, [r3, #8] 801022c: 2b01 cmp r3, #1 801022e: d105 bne.n 801023c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8010230: 2308 movs r3, #8 8010232: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8010234: 687b ldr r3, [r7, #4] 8010236: 69fa ldr r2, [r7, #28] 8010238: 611a str r2, [r3, #16] break; 801023a: e009 b.n 8010250 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 801023c: 2308 movs r3, #8 801023e: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 8010240: 687b ldr r3, [r7, #4] 8010242: 69fa ldr r2, [r7, #28] 8010244: 615a str r2, [r3, #20] break; 8010246: e003 b.n 8010250 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8010248: 2300 movs r3, #0 801024a: 623b str r3, [r7, #32] break; 801024c: e000 b.n 8010250 break; 801024e: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8010250: 69bb ldr r3, [r7, #24] 8010252: 2bff cmp r3, #255 @ 0xff 8010254: d801 bhi.n 801025a 8010256: 687b ldr r3, [r7, #4] 8010258: e001 b.n 801025e 801025a: 687b ldr r3, [r7, #4] 801025c: 3304 adds r3, #4 801025e: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8010260: 69bb ldr r3, [r7, #24] 8010262: 2bff cmp r3, #255 @ 0xff 8010264: d802 bhi.n 801026c 8010266: 6a7b ldr r3, [r7, #36] @ 0x24 8010268: 009b lsls r3, r3, #2 801026a: e002 b.n 8010272 801026c: 6a7b ldr r3, [r7, #36] @ 0x24 801026e: 3b08 subs r3, #8 8010270: 009b lsls r3, r3, #2 8010272: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8010274: 697b ldr r3, [r7, #20] 8010276: 681a ldr r2, [r3, #0] 8010278: 210f movs r1, #15 801027a: 693b ldr r3, [r7, #16] 801027c: fa01 f303 lsl.w r3, r1, r3 8010280: 43db mvns r3, r3 8010282: 401a ands r2, r3 8010284: 6a39 ldr r1, [r7, #32] 8010286: 693b ldr r3, [r7, #16] 8010288: fa01 f303 lsl.w r3, r1, r3 801028c: 431a orrs r2, r3 801028e: 697b ldr r3, [r7, #20] 8010290: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8010292: 683b ldr r3, [r7, #0] 8010294: 685b ldr r3, [r3, #4] 8010296: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 801029a: 2b00 cmp r3, #0 801029c: f000 80b1 beq.w 8010402 { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 80102a0: 4b4d ldr r3, [pc, #308] @ (80103d8 ) 80102a2: 699b ldr r3, [r3, #24] 80102a4: 4a4c ldr r2, [pc, #304] @ (80103d8 ) 80102a6: f043 0301 orr.w r3, r3, #1 80102aa: 6193 str r3, [r2, #24] 80102ac: 4b4a ldr r3, [pc, #296] @ (80103d8 ) 80102ae: 699b ldr r3, [r3, #24] 80102b0: f003 0301 and.w r3, r3, #1 80102b4: 60bb str r3, [r7, #8] 80102b6: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 80102b8: 4a48 ldr r2, [pc, #288] @ (80103dc ) 80102ba: 6a7b ldr r3, [r7, #36] @ 0x24 80102bc: 089b lsrs r3, r3, #2 80102be: 3302 adds r3, #2 80102c0: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80102c4: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 80102c6: 6a7b ldr r3, [r7, #36] @ 0x24 80102c8: f003 0303 and.w r3, r3, #3 80102cc: 009b lsls r3, r3, #2 80102ce: 220f movs r2, #15 80102d0: fa02 f303 lsl.w r3, r2, r3 80102d4: 43db mvns r3, r3 80102d6: 68fa ldr r2, [r7, #12] 80102d8: 4013 ands r3, r2 80102da: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 80102dc: 687b ldr r3, [r7, #4] 80102de: 4a40 ldr r2, [pc, #256] @ (80103e0 ) 80102e0: 4293 cmp r3, r2 80102e2: d013 beq.n 801030c 80102e4: 687b ldr r3, [r7, #4] 80102e6: 4a3f ldr r2, [pc, #252] @ (80103e4 ) 80102e8: 4293 cmp r3, r2 80102ea: d00d beq.n 8010308 80102ec: 687b ldr r3, [r7, #4] 80102ee: 4a3e ldr r2, [pc, #248] @ (80103e8 ) 80102f0: 4293 cmp r3, r2 80102f2: d007 beq.n 8010304 80102f4: 687b ldr r3, [r7, #4] 80102f6: 4a3d ldr r2, [pc, #244] @ (80103ec ) 80102f8: 4293 cmp r3, r2 80102fa: d101 bne.n 8010300 80102fc: 2303 movs r3, #3 80102fe: e006 b.n 801030e 8010300: 2304 movs r3, #4 8010302: e004 b.n 801030e 8010304: 2302 movs r3, #2 8010306: e002 b.n 801030e 8010308: 2301 movs r3, #1 801030a: e000 b.n 801030e 801030c: 2300 movs r3, #0 801030e: 6a7a ldr r2, [r7, #36] @ 0x24 8010310: f002 0203 and.w r2, r2, #3 8010314: 0092 lsls r2, r2, #2 8010316: 4093 lsls r3, r2 8010318: 68fa ldr r2, [r7, #12] 801031a: 4313 orrs r3, r2 801031c: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 801031e: 492f ldr r1, [pc, #188] @ (80103dc ) 8010320: 6a7b ldr r3, [r7, #36] @ 0x24 8010322: 089b lsrs r3, r3, #2 8010324: 3302 adds r3, #2 8010326: 68fa ldr r2, [r7, #12] 8010328: f841 2023 str.w r2, [r1, r3, lsl #2] /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 801032c: 683b ldr r3, [r7, #0] 801032e: 685b ldr r3, [r3, #4] 8010330: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8010334: 2b00 cmp r3, #0 8010336: d006 beq.n 8010346 { SET_BIT(EXTI->RTSR, iocurrent); 8010338: 4b2d ldr r3, [pc, #180] @ (80103f0 ) 801033a: 689a ldr r2, [r3, #8] 801033c: 492c ldr r1, [pc, #176] @ (80103f0 ) 801033e: 69bb ldr r3, [r7, #24] 8010340: 4313 orrs r3, r2 8010342: 608b str r3, [r1, #8] 8010344: e006 b.n 8010354 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8010346: 4b2a ldr r3, [pc, #168] @ (80103f0 ) 8010348: 689a ldr r2, [r3, #8] 801034a: 69bb ldr r3, [r7, #24] 801034c: 43db mvns r3, r3 801034e: 4928 ldr r1, [pc, #160] @ (80103f0 ) 8010350: 4013 ands r3, r2 8010352: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8010354: 683b ldr r3, [r7, #0] 8010356: 685b ldr r3, [r3, #4] 8010358: f403 1300 and.w r3, r3, #2097152 @ 0x200000 801035c: 2b00 cmp r3, #0 801035e: d006 beq.n 801036e { SET_BIT(EXTI->FTSR, iocurrent); 8010360: 4b23 ldr r3, [pc, #140] @ (80103f0 ) 8010362: 68da ldr r2, [r3, #12] 8010364: 4922 ldr r1, [pc, #136] @ (80103f0 ) 8010366: 69bb ldr r3, [r7, #24] 8010368: 4313 orrs r3, r2 801036a: 60cb str r3, [r1, #12] 801036c: e006 b.n 801037c } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 801036e: 4b20 ldr r3, [pc, #128] @ (80103f0 ) 8010370: 68da ldr r2, [r3, #12] 8010372: 69bb ldr r3, [r7, #24] 8010374: 43db mvns r3, r3 8010376: 491e ldr r1, [pc, #120] @ (80103f0 ) 8010378: 4013 ands r3, r2 801037a: 60cb str r3, [r1, #12] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 801037c: 683b ldr r3, [r7, #0] 801037e: 685b ldr r3, [r3, #4] 8010380: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010384: 2b00 cmp r3, #0 8010386: d006 beq.n 8010396 { SET_BIT(EXTI->EMR, iocurrent); 8010388: 4b19 ldr r3, [pc, #100] @ (80103f0 ) 801038a: 685a ldr r2, [r3, #4] 801038c: 4918 ldr r1, [pc, #96] @ (80103f0 ) 801038e: 69bb ldr r3, [r7, #24] 8010390: 4313 orrs r3, r2 8010392: 604b str r3, [r1, #4] 8010394: e006 b.n 80103a4 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8010396: 4b16 ldr r3, [pc, #88] @ (80103f0 ) 8010398: 685a ldr r2, [r3, #4] 801039a: 69bb ldr r3, [r7, #24] 801039c: 43db mvns r3, r3 801039e: 4914 ldr r1, [pc, #80] @ (80103f0 ) 80103a0: 4013 ands r3, r2 80103a2: 604b str r3, [r1, #4] } /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 80103a4: 683b ldr r3, [r7, #0] 80103a6: 685b ldr r3, [r3, #4] 80103a8: f403 3380 and.w r3, r3, #65536 @ 0x10000 80103ac: 2b00 cmp r3, #0 80103ae: d021 beq.n 80103f4 { SET_BIT(EXTI->IMR, iocurrent); 80103b0: 4b0f ldr r3, [pc, #60] @ (80103f0 ) 80103b2: 681a ldr r2, [r3, #0] 80103b4: 490e ldr r1, [pc, #56] @ (80103f0 ) 80103b6: 69bb ldr r3, [r7, #24] 80103b8: 4313 orrs r3, r2 80103ba: 600b str r3, [r1, #0] 80103bc: e021 b.n 8010402 80103be: bf00 nop 80103c0: 10320000 .word 0x10320000 80103c4: 10310000 .word 0x10310000 80103c8: 10220000 .word 0x10220000 80103cc: 10210000 .word 0x10210000 80103d0: 10120000 .word 0x10120000 80103d4: 10110000 .word 0x10110000 80103d8: 40021000 .word 0x40021000 80103dc: 40010000 .word 0x40010000 80103e0: 40010800 .word 0x40010800 80103e4: 40010c00 .word 0x40010c00 80103e8: 40011000 .word 0x40011000 80103ec: 40011400 .word 0x40011400 80103f0: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 80103f4: 4b0b ldr r3, [pc, #44] @ (8010424 ) 80103f6: 681a ldr r2, [r3, #0] 80103f8: 69bb ldr r3, [r7, #24] 80103fa: 43db mvns r3, r3 80103fc: 4909 ldr r1, [pc, #36] @ (8010424 ) 80103fe: 4013 ands r3, r2 8010400: 600b str r3, [r1, #0] } } } position++; 8010402: 6a7b ldr r3, [r7, #36] @ 0x24 8010404: 3301 adds r3, #1 8010406: 627b str r3, [r7, #36] @ 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8010408: 683b ldr r3, [r7, #0] 801040a: 681a ldr r2, [r3, #0] 801040c: 6a7b ldr r3, [r7, #36] @ 0x24 801040e: fa22 f303 lsr.w r3, r2, r3 8010412: 2b00 cmp r3, #0 8010414: f47f ae8e bne.w 8010134 } } 8010418: bf00 nop 801041a: bf00 nop 801041c: 372c adds r7, #44 @ 0x2c 801041e: 46bd mov sp, r7 8010420: bc80 pop {r7} 8010422: 4770 bx lr 8010424: 40010400 .word 0x40010400 08010428 : * @param GPIO_Pin: specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { 8010428: b480 push {r7} 801042a: b089 sub sp, #36 @ 0x24 801042c: af00 add r7, sp, #0 801042e: 6078 str r0, [r7, #4] 8010430: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8010432: 2300 movs r3, #0 8010434: 61fb str r3, [r7, #28] /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Configure the port pins */ while ((GPIO_Pin >> position) != 0u) 8010436: e09a b.n 801056e { /* Get current io position */ iocurrent = (GPIO_Pin) & (1uL << position); 8010438: 2201 movs r2, #1 801043a: 69fb ldr r3, [r7, #28] 801043c: fa02 f303 lsl.w r3, r2, r3 8010440: 683a ldr r2, [r7, #0] 8010442: 4013 ands r3, r2 8010444: 61bb str r3, [r7, #24] if (iocurrent) 8010446: 69bb ldr r3, [r7, #24] 8010448: 2b00 cmp r3, #0 801044a: f000 808d beq.w 8010568 { /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ tmp = AFIO->EXTICR[position >> 2u]; 801044e: 4a4e ldr r2, [pc, #312] @ (8010588 ) 8010450: 69fb ldr r3, [r7, #28] 8010452: 089b lsrs r3, r3, #2 8010454: 3302 adds r3, #2 8010456: f852 3023 ldr.w r3, [r2, r3, lsl #2] 801045a: 617b str r3, [r7, #20] tmp &= 0x0FuL << (4u * (position & 0x03u)); 801045c: 69fb ldr r3, [r7, #28] 801045e: f003 0303 and.w r3, r3, #3 8010462: 009b lsls r3, r3, #2 8010464: 220f movs r2, #15 8010466: fa02 f303 lsl.w r3, r2, r3 801046a: 697a ldr r2, [r7, #20] 801046c: 4013 ands r3, r2 801046e: 617b str r3, [r7, #20] if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) 8010470: 687b ldr r3, [r7, #4] 8010472: 4a46 ldr r2, [pc, #280] @ (801058c ) 8010474: 4293 cmp r3, r2 8010476: d013 beq.n 80104a0 8010478: 687b ldr r3, [r7, #4] 801047a: 4a45 ldr r2, [pc, #276] @ (8010590 ) 801047c: 4293 cmp r3, r2 801047e: d00d beq.n 801049c 8010480: 687b ldr r3, [r7, #4] 8010482: 4a44 ldr r2, [pc, #272] @ (8010594 ) 8010484: 4293 cmp r3, r2 8010486: d007 beq.n 8010498 8010488: 687b ldr r3, [r7, #4] 801048a: 4a43 ldr r2, [pc, #268] @ (8010598 ) 801048c: 4293 cmp r3, r2 801048e: d101 bne.n 8010494 8010490: 2303 movs r3, #3 8010492: e006 b.n 80104a2 8010494: 2304 movs r3, #4 8010496: e004 b.n 80104a2 8010498: 2302 movs r3, #2 801049a: e002 b.n 80104a2 801049c: 2301 movs r3, #1 801049e: e000 b.n 80104a2 80104a0: 2300 movs r3, #0 80104a2: 69fa ldr r2, [r7, #28] 80104a4: f002 0203 and.w r2, r2, #3 80104a8: 0092 lsls r2, r2, #2 80104aa: 4093 lsls r3, r2 80104ac: 697a ldr r2, [r7, #20] 80104ae: 429a cmp r2, r3 80104b0: d132 bne.n 8010518 { /* Clear EXTI line configuration */ CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); 80104b2: 4b3a ldr r3, [pc, #232] @ (801059c ) 80104b4: 681a ldr r2, [r3, #0] 80104b6: 69bb ldr r3, [r7, #24] 80104b8: 43db mvns r3, r3 80104ba: 4938 ldr r1, [pc, #224] @ (801059c ) 80104bc: 4013 ands r3, r2 80104be: 600b str r3, [r1, #0] CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); 80104c0: 4b36 ldr r3, [pc, #216] @ (801059c ) 80104c2: 685a ldr r2, [r3, #4] 80104c4: 69bb ldr r3, [r7, #24] 80104c6: 43db mvns r3, r3 80104c8: 4934 ldr r1, [pc, #208] @ (801059c ) 80104ca: 4013 ands r3, r2 80104cc: 604b str r3, [r1, #4] /* Clear Rising Falling edge configuration */ CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); 80104ce: 4b33 ldr r3, [pc, #204] @ (801059c ) 80104d0: 68da ldr r2, [r3, #12] 80104d2: 69bb ldr r3, [r7, #24] 80104d4: 43db mvns r3, r3 80104d6: 4931 ldr r1, [pc, #196] @ (801059c ) 80104d8: 4013 ands r3, r2 80104da: 60cb str r3, [r1, #12] CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); 80104dc: 4b2f ldr r3, [pc, #188] @ (801059c ) 80104de: 689a ldr r2, [r3, #8] 80104e0: 69bb ldr r3, [r7, #24] 80104e2: 43db mvns r3, r3 80104e4: 492d ldr r1, [pc, #180] @ (801059c ) 80104e6: 4013 ands r3, r2 80104e8: 608b str r3, [r1, #8] tmp = 0x0FuL << (4u * (position & 0x03u)); 80104ea: 69fb ldr r3, [r7, #28] 80104ec: f003 0303 and.w r3, r3, #3 80104f0: 009b lsls r3, r3, #2 80104f2: 220f movs r2, #15 80104f4: fa02 f303 lsl.w r3, r2, r3 80104f8: 617b str r3, [r7, #20] CLEAR_BIT(AFIO->EXTICR[position >> 2u], tmp); 80104fa: 4a23 ldr r2, [pc, #140] @ (8010588 ) 80104fc: 69fb ldr r3, [r7, #28] 80104fe: 089b lsrs r3, r3, #2 8010500: 3302 adds r3, #2 8010502: f852 1023 ldr.w r1, [r2, r3, lsl #2] 8010506: 697b ldr r3, [r7, #20] 8010508: 43da mvns r2, r3 801050a: 481f ldr r0, [pc, #124] @ (8010588 ) 801050c: 69fb ldr r3, [r7, #28] 801050e: 089b lsrs r3, r3, #2 8010510: 400a ands r2, r1 8010512: 3302 adds r3, #2 8010514: f840 2023 str.w r2, [r0, r3, lsl #2] } /*------------------------- GPIO Mode Configuration --------------------*/ /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register */ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8010518: 69bb ldr r3, [r7, #24] 801051a: 2bff cmp r3, #255 @ 0xff 801051c: d801 bhi.n 8010522 801051e: 687b ldr r3, [r7, #4] 8010520: e001 b.n 8010526 8010522: 687b ldr r3, [r7, #4] 8010524: 3304 adds r3, #4 8010526: 613b str r3, [r7, #16] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8010528: 69bb ldr r3, [r7, #24] 801052a: 2bff cmp r3, #255 @ 0xff 801052c: d802 bhi.n 8010534 801052e: 69fb ldr r3, [r7, #28] 8010530: 009b lsls r3, r3, #2 8010532: e002 b.n 801053a 8010534: 69fb ldr r3, [r7, #28] 8010536: 3b08 subs r3, #8 8010538: 009b lsls r3, r3, #2 801053a: 60fb str r3, [r7, #12] /* CRL/CRH default value is floating input(0x04) shifted to correct position */ MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), GPIO_CRL_CNF0_0 << registeroffset); 801053c: 693b ldr r3, [r7, #16] 801053e: 681a ldr r2, [r3, #0] 8010540: 210f movs r1, #15 8010542: 68fb ldr r3, [r7, #12] 8010544: fa01 f303 lsl.w r3, r1, r3 8010548: 43db mvns r3, r3 801054a: 401a ands r2, r3 801054c: 2104 movs r1, #4 801054e: 68fb ldr r3, [r7, #12] 8010550: fa01 f303 lsl.w r3, r1, r3 8010554: 431a orrs r2, r3 8010556: 693b ldr r3, [r7, #16] 8010558: 601a str r2, [r3, #0] /* ODR default value is 0 */ CLEAR_BIT(GPIOx->ODR, iocurrent); 801055a: 687b ldr r3, [r7, #4] 801055c: 68da ldr r2, [r3, #12] 801055e: 69bb ldr r3, [r7, #24] 8010560: 43db mvns r3, r3 8010562: 401a ands r2, r3 8010564: 687b ldr r3, [r7, #4] 8010566: 60da str r2, [r3, #12] } position++; 8010568: 69fb ldr r3, [r7, #28] 801056a: 3301 adds r3, #1 801056c: 61fb str r3, [r7, #28] while ((GPIO_Pin >> position) != 0u) 801056e: 683a ldr r2, [r7, #0] 8010570: 69fb ldr r3, [r7, #28] 8010572: fa22 f303 lsr.w r3, r2, r3 8010576: 2b00 cmp r3, #0 8010578: f47f af5e bne.w 8010438 } } 801057c: bf00 nop 801057e: bf00 nop 8010580: 3724 adds r7, #36 @ 0x24 8010582: 46bd mov sp, r7 8010584: bc80 pop {r7} 8010586: 4770 bx lr 8010588: 40010000 .word 0x40010000 801058c: 40010800 .word 0x40010800 8010590: 40010c00 .word 0x40010c00 8010594: 40011000 .word 0x40011000 8010598: 40011400 .word 0x40011400 801059c: 40010400 .word 0x40010400 080105a0 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 80105a0: b480 push {r7} 80105a2: b085 sub sp, #20 80105a4: af00 add r7, sp, #0 80105a6: 6078 str r0, [r7, #4] 80105a8: 460b mov r3, r1 80105aa: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 80105ac: 687b ldr r3, [r7, #4] 80105ae: 689a ldr r2, [r3, #8] 80105b0: 887b ldrh r3, [r7, #2] 80105b2: 4013 ands r3, r2 80105b4: 2b00 cmp r3, #0 80105b6: d002 beq.n 80105be { bitstatus = GPIO_PIN_SET; 80105b8: 2301 movs r3, #1 80105ba: 73fb strb r3, [r7, #15] 80105bc: e001 b.n 80105c2 } else { bitstatus = GPIO_PIN_RESET; 80105be: 2300 movs r3, #0 80105c0: 73fb strb r3, [r7, #15] } return bitstatus; 80105c2: 7bfb ldrb r3, [r7, #15] } 80105c4: 4618 mov r0, r3 80105c6: 3714 adds r7, #20 80105c8: 46bd mov sp, r7 80105ca: bc80 pop {r7} 80105cc: 4770 bx lr 080105ce : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 80105ce: b480 push {r7} 80105d0: b083 sub sp, #12 80105d2: af00 add r7, sp, #0 80105d4: 6078 str r0, [r7, #4] 80105d6: 460b mov r3, r1 80105d8: 807b strh r3, [r7, #2] 80105da: 4613 mov r3, r2 80105dc: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 80105de: 787b ldrb r3, [r7, #1] 80105e0: 2b00 cmp r3, #0 80105e2: d003 beq.n 80105ec { GPIOx->BSRR = GPIO_Pin; 80105e4: 887a ldrh r2, [r7, #2] 80105e6: 687b ldr r3, [r7, #4] 80105e8: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 80105ea: e003 b.n 80105f4 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 80105ec: 887b ldrh r3, [r7, #2] 80105ee: 041a lsls r2, r3, #16 80105f0: 687b ldr r3, [r7, #4] 80105f2: 611a str r2, [r3, #16] } 80105f4: bf00 nop 80105f6: 370c adds r7, #12 80105f8: 46bd mov sp, r7 80105fa: bc80 pop {r7} 80105fc: 4770 bx lr ... 08010600 : * @note If the HSE divided by 128 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 8010600: b480 push {r7} 8010602: af00 add r7, sp, #0 /* Enable access to RTC and backup registers */ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 8010604: 4b03 ldr r3, [pc, #12] @ (8010614 ) 8010606: 2201 movs r2, #1 8010608: 601a str r2, [r3, #0] } 801060a: bf00 nop 801060c: 46bd mov sp, r7 801060e: bc80 pop {r7} 8010610: 4770 bx lr 8010612: bf00 nop 8010614: 420e0020 .word 0x420e0020 08010618 : * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval HAL_StatusTypeDef */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { 8010618: b580 push {r7, lr} 801061a: b082 sub sp, #8 801061c: af00 add r7, sp, #0 uint32_t tickstart; /* Get Start Tick */ tickstart = HAL_GetTick(); 801061e: f7fd fb5b bl 800dcd8 8010622: 6078 str r0, [r7, #4] /* Set HSION bit */ SET_BIT(RCC->CR, RCC_CR_HSION); 8010624: 4b60 ldr r3, [pc, #384] @ (80107a8 ) 8010626: 681b ldr r3, [r3, #0] 8010628: 4a5f ldr r2, [pc, #380] @ (80107a8 ) 801062a: f043 0301 orr.w r3, r3, #1 801062e: 6013 str r3, [r2, #0] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 8010630: e008 b.n 8010644 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8010632: f7fd fb51 bl 800dcd8 8010636: 4602 mov r2, r0 8010638: 687b ldr r3, [r7, #4] 801063a: 1ad3 subs r3, r2, r3 801063c: 2b02 cmp r3, #2 801063e: d901 bls.n 8010644 { return HAL_TIMEOUT; 8010640: 2303 movs r3, #3 8010642: e0ac b.n 801079e while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 8010644: 4b58 ldr r3, [pc, #352] @ (80107a8 ) 8010646: 681b ldr r3, [r3, #0] 8010648: f003 0302 and.w r3, r3, #2 801064c: 2b00 cmp r3, #0 801064e: d0f0 beq.n 8010632 } } /* Set HSITRIM bits to the reset value */ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); 8010650: 4b55 ldr r3, [pc, #340] @ (80107a8 ) 8010652: 681b ldr r3, [r3, #0] 8010654: f023 03f8 bic.w r3, r3, #248 @ 0xf8 8010658: 4a53 ldr r2, [pc, #332] @ (80107a8 ) 801065a: f043 0380 orr.w r3, r3, #128 @ 0x80 801065e: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010660: f7fd fb3a bl 800dcd8 8010664: 6078 str r0, [r7, #4] /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); 8010666: 4b50 ldr r3, [pc, #320] @ (80107a8 ) 8010668: 2200 movs r2, #0 801066a: 605a str r2, [r3, #4] /* Wait till clock switch is ready */ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 801066c: e00a b.n 8010684 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 801066e: f7fd fb33 bl 800dcd8 8010672: 4602 mov r2, r0 8010674: 687b ldr r3, [r7, #4] 8010676: 1ad3 subs r3, r2, r3 8010678: f241 3288 movw r2, #5000 @ 0x1388 801067c: 4293 cmp r3, r2 801067e: d901 bls.n 8010684 { return HAL_TIMEOUT; 8010680: 2303 movs r3, #3 8010682: e08c b.n 801079e while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 8010684: 4b48 ldr r3, [pc, #288] @ (80107a8 ) 8010686: 685b ldr r3, [r3, #4] 8010688: f003 030c and.w r3, r3, #12 801068c: 2b00 cmp r3, #0 801068e: d1ee bne.n 801066e } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; 8010690: 4b46 ldr r3, [pc, #280] @ (80107ac ) 8010692: 4a47 ldr r2, [pc, #284] @ (80107b0 ) 8010694: 601a str r2, [r3, #0] /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 8010696: 4b47 ldr r3, [pc, #284] @ (80107b4 ) 8010698: 681b ldr r3, [r3, #0] 801069a: 4618 mov r0, r3 801069c: f7fd fada bl 800dc54 80106a0: 4603 mov r3, r0 80106a2: 2b00 cmp r3, #0 80106a4: d001 beq.n 80106aa { return HAL_ERROR; 80106a6: 2301 movs r3, #1 80106a8: e079 b.n 801079e } /* Get Start Tick */ tickstart = HAL_GetTick(); 80106aa: f7fd fb15 bl 800dcd8 80106ae: 6078 str r0, [r7, #4] /* Second step is to clear PLLON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 80106b0: 4b3d ldr r3, [pc, #244] @ (80107a8 ) 80106b2: 681b ldr r3, [r3, #0] 80106b4: 4a3c ldr r2, [pc, #240] @ (80107a8 ) 80106b6: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 80106ba: 6013 str r3, [r2, #0] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 80106bc: e008 b.n 80106d0 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80106be: f7fd fb0b bl 800dcd8 80106c2: 4602 mov r2, r0 80106c4: 687b ldr r3, [r7, #4] 80106c6: 1ad3 subs r3, r2, r3 80106c8: 2b02 cmp r3, #2 80106ca: d901 bls.n 80106d0 { return HAL_TIMEOUT; 80106cc: 2303 movs r3, #3 80106ce: e066 b.n 801079e while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 80106d0: 4b35 ldr r3, [pc, #212] @ (80107a8 ) 80106d2: 681b ldr r3, [r3, #0] 80106d4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80106d8: 2b00 cmp r3, #0 80106da: d1f0 bne.n 80106be } } /* Ensure to reset PLLSRC and PLLMUL bits */ CLEAR_REG(RCC->CFGR); 80106dc: 4b32 ldr r3, [pc, #200] @ (80107a8 ) 80106de: 2200 movs r2, #0 80106e0: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 80106e2: f7fd faf9 bl 800dcd8 80106e6: 6078 str r0, [r7, #4] /* Reset HSEON & CSSON bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON); 80106e8: 4b2f ldr r3, [pc, #188] @ (80107a8 ) 80106ea: 681b ldr r3, [r3, #0] 80106ec: 4a2e ldr r2, [pc, #184] @ (80107a8 ) 80106ee: f423 2310 bic.w r3, r3, #589824 @ 0x90000 80106f2: 6013 str r3, [r2, #0] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 80106f4: e008 b.n 8010708 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80106f6: f7fd faef bl 800dcd8 80106fa: 4602 mov r2, r0 80106fc: 687b ldr r3, [r7, #4] 80106fe: 1ad3 subs r3, r2, r3 8010700: 2b64 cmp r3, #100 @ 0x64 8010702: d901 bls.n 8010708 { return HAL_TIMEOUT; 8010704: 2303 movs r3, #3 8010706: e04a b.n 801079e while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 8010708: 4b27 ldr r3, [pc, #156] @ (80107a8 ) 801070a: 681b ldr r3, [r3, #0] 801070c: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010710: 2b00 cmp r3, #0 8010712: d1f0 bne.n 80106f6 } } /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 8010714: 4b24 ldr r3, [pc, #144] @ (80107a8 ) 8010716: 681b ldr r3, [r3, #0] 8010718: 4a23 ldr r2, [pc, #140] @ (80107a8 ) 801071a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 801071e: 6013 str r3, [r2, #0] #if defined(RCC_PLL2_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 8010720: f7fd fada bl 800dcd8 8010724: 6078 str r0, [r7, #4] /* Clear PLL2ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); 8010726: 4b20 ldr r3, [pc, #128] @ (80107a8 ) 8010728: 681b ldr r3, [r3, #0] 801072a: 4a1f ldr r2, [pc, #124] @ (80107a8 ) 801072c: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8010730: 6013 str r3, [r2, #0] /* Wait till PLL2 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 8010732: e008 b.n 8010746 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8010734: f7fd fad0 bl 800dcd8 8010738: 4602 mov r2, r0 801073a: 687b ldr r3, [r7, #4] 801073c: 1ad3 subs r3, r2, r3 801073e: 2b64 cmp r3, #100 @ 0x64 8010740: d901 bls.n 8010746 { return HAL_TIMEOUT; 8010742: 2303 movs r3, #3 8010744: e02b b.n 801079e while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 8010746: 4b18 ldr r3, [pc, #96] @ (80107a8 ) 8010748: 681b ldr r3, [r3, #0] 801074a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 801074e: 2b00 cmp r3, #0 8010750: d1f0 bne.n 8010734 } #endif /* RCC_PLL2_SUPPORT */ #if defined(RCC_PLLI2S_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 8010752: f7fd fac1 bl 800dcd8 8010756: 6078 str r0, [r7, #4] /* Clear PLL3ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); 8010758: 4b13 ldr r3, [pc, #76] @ (80107a8 ) 801075a: 681b ldr r3, [r3, #0] 801075c: 4a12 ldr r2, [pc, #72] @ (80107a8 ) 801075e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8010762: 6013 str r3, [r2, #0] /* Wait till PLL3 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 8010764: e008 b.n 8010778 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8010766: f7fd fab7 bl 800dcd8 801076a: 4602 mov r2, r0 801076c: 687b ldr r3, [r7, #4] 801076e: 1ad3 subs r3, r2, r3 8010770: 2b64 cmp r3, #100 @ 0x64 8010772: d901 bls.n 8010778 { return HAL_TIMEOUT; 8010774: 2303 movs r3, #3 8010776: e012 b.n 801079e while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 8010778: 4b0b ldr r3, [pc, #44] @ (80107a8 ) 801077a: 681b ldr r3, [r3, #0] 801077c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8010780: 2b00 cmp r3, #0 8010782: d1f0 bne.n 8010766 } #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_CFGR2_PREDIV1) /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); 8010784: 4b08 ldr r3, [pc, #32] @ (80107a8 ) 8010786: 2200 movs r2, #0 8010788: 62da str r2, [r3, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1 */ /* Reset all CSR flags */ SET_BIT(RCC->CSR, RCC_CSR_RMVF); 801078a: 4b07 ldr r3, [pc, #28] @ (80107a8 ) 801078c: 6a5b ldr r3, [r3, #36] @ 0x24 801078e: 4a06 ldr r2, [pc, #24] @ (80107a8 ) 8010790: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8010794: 6253 str r3, [r2, #36] @ 0x24 /* Disable all interrupts */ CLEAR_REG(RCC->CIR); 8010796: 4b04 ldr r3, [pc, #16] @ (80107a8 ) 8010798: 2200 movs r2, #0 801079a: 609a str r2, [r3, #8] return HAL_OK; 801079c: 2300 movs r3, #0 } 801079e: 4618 mov r0, r3 80107a0: 3708 adds r7, #8 80107a2: 46bd mov sp, r7 80107a4: bd80 pop {r7, pc} 80107a6: bf00 nop 80107a8: 40021000 .word 0x40021000 80107ac: 2000006c .word 0x2000006c 80107b0: 007a1200 .word 0x007a1200 80107b4: 20000070 .word 0x20000070 080107b8 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 80107b8: b580 push {r7, lr} 80107ba: b086 sub sp, #24 80107bc: af00 add r7, sp, #0 80107be: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 80107c0: 687b ldr r3, [r7, #4] 80107c2: 2b00 cmp r3, #0 80107c4: d101 bne.n 80107ca { return HAL_ERROR; 80107c6: 2301 movs r3, #1 80107c8: e304 b.n 8010dd4 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 80107ca: 687b ldr r3, [r7, #4] 80107cc: 681b ldr r3, [r3, #0] 80107ce: f003 0301 and.w r3, r3, #1 80107d2: 2b00 cmp r3, #0 80107d4: f000 8087 beq.w 80108e6 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 80107d8: 4b92 ldr r3, [pc, #584] @ (8010a24 ) 80107da: 685b ldr r3, [r3, #4] 80107dc: f003 030c and.w r3, r3, #12 80107e0: 2b04 cmp r3, #4 80107e2: d00c beq.n 80107fe || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 80107e4: 4b8f ldr r3, [pc, #572] @ (8010a24 ) 80107e6: 685b ldr r3, [r3, #4] 80107e8: f003 030c and.w r3, r3, #12 80107ec: 2b08 cmp r3, #8 80107ee: d112 bne.n 8010816 80107f0: 4b8c ldr r3, [pc, #560] @ (8010a24 ) 80107f2: 685b ldr r3, [r3, #4] 80107f4: f403 3380 and.w r3, r3, #65536 @ 0x10000 80107f8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80107fc: d10b bne.n 8010816 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80107fe: 4b89 ldr r3, [pc, #548] @ (8010a24 ) 8010800: 681b ldr r3, [r3, #0] 8010802: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010806: 2b00 cmp r3, #0 8010808: d06c beq.n 80108e4 801080a: 687b ldr r3, [r7, #4] 801080c: 689b ldr r3, [r3, #8] 801080e: 2b00 cmp r3, #0 8010810: d168 bne.n 80108e4 { return HAL_ERROR; 8010812: 2301 movs r3, #1 8010814: e2de b.n 8010dd4 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8010816: 687b ldr r3, [r7, #4] 8010818: 689b ldr r3, [r3, #8] 801081a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 801081e: d106 bne.n 801082e 8010820: 4b80 ldr r3, [pc, #512] @ (8010a24 ) 8010822: 681b ldr r3, [r3, #0] 8010824: 4a7f ldr r2, [pc, #508] @ (8010a24 ) 8010826: f443 3380 orr.w r3, r3, #65536 @ 0x10000 801082a: 6013 str r3, [r2, #0] 801082c: e02e b.n 801088c 801082e: 687b ldr r3, [r7, #4] 8010830: 689b ldr r3, [r3, #8] 8010832: 2b00 cmp r3, #0 8010834: d10c bne.n 8010850 8010836: 4b7b ldr r3, [pc, #492] @ (8010a24 ) 8010838: 681b ldr r3, [r3, #0] 801083a: 4a7a ldr r2, [pc, #488] @ (8010a24 ) 801083c: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8010840: 6013 str r3, [r2, #0] 8010842: 4b78 ldr r3, [pc, #480] @ (8010a24 ) 8010844: 681b ldr r3, [r3, #0] 8010846: 4a77 ldr r2, [pc, #476] @ (8010a24 ) 8010848: f423 2380 bic.w r3, r3, #262144 @ 0x40000 801084c: 6013 str r3, [r2, #0] 801084e: e01d b.n 801088c 8010850: 687b ldr r3, [r7, #4] 8010852: 689b ldr r3, [r3, #8] 8010854: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8010858: d10c bne.n 8010874 801085a: 4b72 ldr r3, [pc, #456] @ (8010a24 ) 801085c: 681b ldr r3, [r3, #0] 801085e: 4a71 ldr r2, [pc, #452] @ (8010a24 ) 8010860: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8010864: 6013 str r3, [r2, #0] 8010866: 4b6f ldr r3, [pc, #444] @ (8010a24 ) 8010868: 681b ldr r3, [r3, #0] 801086a: 4a6e ldr r2, [pc, #440] @ (8010a24 ) 801086c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8010870: 6013 str r3, [r2, #0] 8010872: e00b b.n 801088c 8010874: 4b6b ldr r3, [pc, #428] @ (8010a24 ) 8010876: 681b ldr r3, [r3, #0] 8010878: 4a6a ldr r2, [pc, #424] @ (8010a24 ) 801087a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 801087e: 6013 str r3, [r2, #0] 8010880: 4b68 ldr r3, [pc, #416] @ (8010a24 ) 8010882: 681b ldr r3, [r3, #0] 8010884: 4a67 ldr r2, [pc, #412] @ (8010a24 ) 8010886: f423 2380 bic.w r3, r3, #262144 @ 0x40000 801088a: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 801088c: 687b ldr r3, [r7, #4] 801088e: 689b ldr r3, [r3, #8] 8010890: 2b00 cmp r3, #0 8010892: d013 beq.n 80108bc { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010894: f7fd fa20 bl 800dcd8 8010898: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 801089a: e008 b.n 80108ae { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 801089c: f7fd fa1c bl 800dcd8 80108a0: 4602 mov r2, r0 80108a2: 693b ldr r3, [r7, #16] 80108a4: 1ad3 subs r3, r2, r3 80108a6: 2b64 cmp r3, #100 @ 0x64 80108a8: d901 bls.n 80108ae { return HAL_TIMEOUT; 80108aa: 2303 movs r3, #3 80108ac: e292 b.n 8010dd4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80108ae: 4b5d ldr r3, [pc, #372] @ (8010a24 ) 80108b0: 681b ldr r3, [r3, #0] 80108b2: f403 3300 and.w r3, r3, #131072 @ 0x20000 80108b6: 2b00 cmp r3, #0 80108b8: d0f0 beq.n 801089c 80108ba: e014 b.n 80108e6 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80108bc: f7fd fa0c bl 800dcd8 80108c0: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80108c2: e008 b.n 80108d6 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80108c4: f7fd fa08 bl 800dcd8 80108c8: 4602 mov r2, r0 80108ca: 693b ldr r3, [r7, #16] 80108cc: 1ad3 subs r3, r2, r3 80108ce: 2b64 cmp r3, #100 @ 0x64 80108d0: d901 bls.n 80108d6 { return HAL_TIMEOUT; 80108d2: 2303 movs r3, #3 80108d4: e27e b.n 8010dd4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80108d6: 4b53 ldr r3, [pc, #332] @ (8010a24 ) 80108d8: 681b ldr r3, [r3, #0] 80108da: f403 3300 and.w r3, r3, #131072 @ 0x20000 80108de: 2b00 cmp r3, #0 80108e0: d1f0 bne.n 80108c4 80108e2: e000 b.n 80108e6 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80108e4: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 80108e6: 687b ldr r3, [r7, #4] 80108e8: 681b ldr r3, [r3, #0] 80108ea: f003 0302 and.w r3, r3, #2 80108ee: 2b00 cmp r3, #0 80108f0: d063 beq.n 80109ba /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 80108f2: 4b4c ldr r3, [pc, #304] @ (8010a24 ) 80108f4: 685b ldr r3, [r3, #4] 80108f6: f003 030c and.w r3, r3, #12 80108fa: 2b00 cmp r3, #0 80108fc: d00b beq.n 8010916 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 80108fe: 4b49 ldr r3, [pc, #292] @ (8010a24 ) 8010900: 685b ldr r3, [r3, #4] 8010902: f003 030c and.w r3, r3, #12 8010906: 2b08 cmp r3, #8 8010908: d11c bne.n 8010944 801090a: 4b46 ldr r3, [pc, #280] @ (8010a24 ) 801090c: 685b ldr r3, [r3, #4] 801090e: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010912: 2b00 cmp r3, #0 8010914: d116 bne.n 8010944 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8010916: 4b43 ldr r3, [pc, #268] @ (8010a24 ) 8010918: 681b ldr r3, [r3, #0] 801091a: f003 0302 and.w r3, r3, #2 801091e: 2b00 cmp r3, #0 8010920: d005 beq.n 801092e 8010922: 687b ldr r3, [r7, #4] 8010924: 695b ldr r3, [r3, #20] 8010926: 2b01 cmp r3, #1 8010928: d001 beq.n 801092e { return HAL_ERROR; 801092a: 2301 movs r3, #1 801092c: e252 b.n 8010dd4 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 801092e: 4b3d ldr r3, [pc, #244] @ (8010a24 ) 8010930: 681b ldr r3, [r3, #0] 8010932: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8010936: 687b ldr r3, [r7, #4] 8010938: 699b ldr r3, [r3, #24] 801093a: 00db lsls r3, r3, #3 801093c: 4939 ldr r1, [pc, #228] @ (8010a24 ) 801093e: 4313 orrs r3, r2 8010940: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8010942: e03a b.n 80109ba } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8010944: 687b ldr r3, [r7, #4] 8010946: 695b ldr r3, [r3, #20] 8010948: 2b00 cmp r3, #0 801094a: d020 beq.n 801098e { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 801094c: 4b36 ldr r3, [pc, #216] @ (8010a28 ) 801094e: 2201 movs r2, #1 8010950: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010952: f7fd f9c1 bl 800dcd8 8010956: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8010958: e008 b.n 801096c { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 801095a: f7fd f9bd bl 800dcd8 801095e: 4602 mov r2, r0 8010960: 693b ldr r3, [r7, #16] 8010962: 1ad3 subs r3, r2, r3 8010964: 2b02 cmp r3, #2 8010966: d901 bls.n 801096c { return HAL_TIMEOUT; 8010968: 2303 movs r3, #3 801096a: e233 b.n 8010dd4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 801096c: 4b2d ldr r3, [pc, #180] @ (8010a24 ) 801096e: 681b ldr r3, [r3, #0] 8010970: f003 0302 and.w r3, r3, #2 8010974: 2b00 cmp r3, #0 8010976: d0f0 beq.n 801095a } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8010978: 4b2a ldr r3, [pc, #168] @ (8010a24 ) 801097a: 681b ldr r3, [r3, #0] 801097c: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8010980: 687b ldr r3, [r7, #4] 8010982: 699b ldr r3, [r3, #24] 8010984: 00db lsls r3, r3, #3 8010986: 4927 ldr r1, [pc, #156] @ (8010a24 ) 8010988: 4313 orrs r3, r2 801098a: 600b str r3, [r1, #0] 801098c: e015 b.n 80109ba } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 801098e: 4b26 ldr r3, [pc, #152] @ (8010a28 ) 8010990: 2200 movs r2, #0 8010992: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010994: f7fd f9a0 bl 800dcd8 8010998: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 801099a: e008 b.n 80109ae { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 801099c: f7fd f99c bl 800dcd8 80109a0: 4602 mov r2, r0 80109a2: 693b ldr r3, [r7, #16] 80109a4: 1ad3 subs r3, r2, r3 80109a6: 2b02 cmp r3, #2 80109a8: d901 bls.n 80109ae { return HAL_TIMEOUT; 80109aa: 2303 movs r3, #3 80109ac: e212 b.n 8010dd4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80109ae: 4b1d ldr r3, [pc, #116] @ (8010a24 ) 80109b0: 681b ldr r3, [r3, #0] 80109b2: f003 0302 and.w r3, r3, #2 80109b6: 2b00 cmp r3, #0 80109b8: d1f0 bne.n 801099c } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80109ba: 687b ldr r3, [r7, #4] 80109bc: 681b ldr r3, [r3, #0] 80109be: f003 0308 and.w r3, r3, #8 80109c2: 2b00 cmp r3, #0 80109c4: d03a beq.n 8010a3c { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 80109c6: 687b ldr r3, [r7, #4] 80109c8: 69db ldr r3, [r3, #28] 80109ca: 2b00 cmp r3, #0 80109cc: d019 beq.n 8010a02 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 80109ce: 4b17 ldr r3, [pc, #92] @ (8010a2c ) 80109d0: 2201 movs r2, #1 80109d2: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80109d4: f7fd f980 bl 800dcd8 80109d8: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 80109da: e008 b.n 80109ee { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80109dc: f7fd f97c bl 800dcd8 80109e0: 4602 mov r2, r0 80109e2: 693b ldr r3, [r7, #16] 80109e4: 1ad3 subs r3, r2, r3 80109e6: 2b02 cmp r3, #2 80109e8: d901 bls.n 80109ee { return HAL_TIMEOUT; 80109ea: 2303 movs r3, #3 80109ec: e1f2 b.n 8010dd4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 80109ee: 4b0d ldr r3, [pc, #52] @ (8010a24 ) 80109f0: 6a5b ldr r3, [r3, #36] @ 0x24 80109f2: f003 0302 and.w r3, r3, #2 80109f6: 2b00 cmp r3, #0 80109f8: d0f0 beq.n 80109dc } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 80109fa: 2001 movs r0, #1 80109fc: f000 fbca bl 8011194 8010a00: e01c b.n 8010a3c } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8010a02: 4b0a ldr r3, [pc, #40] @ (8010a2c ) 8010a04: 2200 movs r2, #0 8010a06: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010a08: f7fd f966 bl 800dcd8 8010a0c: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8010a0e: e00f b.n 8010a30 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8010a10: f7fd f962 bl 800dcd8 8010a14: 4602 mov r2, r0 8010a16: 693b ldr r3, [r7, #16] 8010a18: 1ad3 subs r3, r2, r3 8010a1a: 2b02 cmp r3, #2 8010a1c: d908 bls.n 8010a30 { return HAL_TIMEOUT; 8010a1e: 2303 movs r3, #3 8010a20: e1d8 b.n 8010dd4 8010a22: bf00 nop 8010a24: 40021000 .word 0x40021000 8010a28: 42420000 .word 0x42420000 8010a2c: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8010a30: 4b9b ldr r3, [pc, #620] @ (8010ca0 ) 8010a32: 6a5b ldr r3, [r3, #36] @ 0x24 8010a34: f003 0302 and.w r3, r3, #2 8010a38: 2b00 cmp r3, #0 8010a3a: d1e9 bne.n 8010a10 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8010a3c: 687b ldr r3, [r7, #4] 8010a3e: 681b ldr r3, [r3, #0] 8010a40: f003 0304 and.w r3, r3, #4 8010a44: 2b00 cmp r3, #0 8010a46: f000 80a6 beq.w 8010b96 { FlagStatus pwrclkchanged = RESET; 8010a4a: 2300 movs r3, #0 8010a4c: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8010a4e: 4b94 ldr r3, [pc, #592] @ (8010ca0 ) 8010a50: 69db ldr r3, [r3, #28] 8010a52: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010a56: 2b00 cmp r3, #0 8010a58: d10d bne.n 8010a76 { __HAL_RCC_PWR_CLK_ENABLE(); 8010a5a: 4b91 ldr r3, [pc, #580] @ (8010ca0 ) 8010a5c: 69db ldr r3, [r3, #28] 8010a5e: 4a90 ldr r2, [pc, #576] @ (8010ca0 ) 8010a60: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8010a64: 61d3 str r3, [r2, #28] 8010a66: 4b8e ldr r3, [pc, #568] @ (8010ca0 ) 8010a68: 69db ldr r3, [r3, #28] 8010a6a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010a6e: 60bb str r3, [r7, #8] 8010a70: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8010a72: 2301 movs r3, #1 8010a74: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010a76: 4b8b ldr r3, [pc, #556] @ (8010ca4 ) 8010a78: 681b ldr r3, [r3, #0] 8010a7a: f403 7380 and.w r3, r3, #256 @ 0x100 8010a7e: 2b00 cmp r3, #0 8010a80: d118 bne.n 8010ab4 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8010a82: 4b88 ldr r3, [pc, #544] @ (8010ca4 ) 8010a84: 681b ldr r3, [r3, #0] 8010a86: 4a87 ldr r2, [pc, #540] @ (8010ca4 ) 8010a88: f443 7380 orr.w r3, r3, #256 @ 0x100 8010a8c: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8010a8e: f7fd f923 bl 800dcd8 8010a92: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010a94: e008 b.n 8010aa8 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8010a96: f7fd f91f bl 800dcd8 8010a9a: 4602 mov r2, r0 8010a9c: 693b ldr r3, [r7, #16] 8010a9e: 1ad3 subs r3, r2, r3 8010aa0: 2b64 cmp r3, #100 @ 0x64 8010aa2: d901 bls.n 8010aa8 { return HAL_TIMEOUT; 8010aa4: 2303 movs r3, #3 8010aa6: e195 b.n 8010dd4 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010aa8: 4b7e ldr r3, [pc, #504] @ (8010ca4 ) 8010aaa: 681b ldr r3, [r3, #0] 8010aac: f403 7380 and.w r3, r3, #256 @ 0x100 8010ab0: 2b00 cmp r3, #0 8010ab2: d0f0 beq.n 8010a96 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8010ab4: 687b ldr r3, [r7, #4] 8010ab6: 691b ldr r3, [r3, #16] 8010ab8: 2b01 cmp r3, #1 8010aba: d106 bne.n 8010aca 8010abc: 4b78 ldr r3, [pc, #480] @ (8010ca0 ) 8010abe: 6a1b ldr r3, [r3, #32] 8010ac0: 4a77 ldr r2, [pc, #476] @ (8010ca0 ) 8010ac2: f043 0301 orr.w r3, r3, #1 8010ac6: 6213 str r3, [r2, #32] 8010ac8: e02d b.n 8010b26 8010aca: 687b ldr r3, [r7, #4] 8010acc: 691b ldr r3, [r3, #16] 8010ace: 2b00 cmp r3, #0 8010ad0: d10c bne.n 8010aec 8010ad2: 4b73 ldr r3, [pc, #460] @ (8010ca0 ) 8010ad4: 6a1b ldr r3, [r3, #32] 8010ad6: 4a72 ldr r2, [pc, #456] @ (8010ca0 ) 8010ad8: f023 0301 bic.w r3, r3, #1 8010adc: 6213 str r3, [r2, #32] 8010ade: 4b70 ldr r3, [pc, #448] @ (8010ca0 ) 8010ae0: 6a1b ldr r3, [r3, #32] 8010ae2: 4a6f ldr r2, [pc, #444] @ (8010ca0 ) 8010ae4: f023 0304 bic.w r3, r3, #4 8010ae8: 6213 str r3, [r2, #32] 8010aea: e01c b.n 8010b26 8010aec: 687b ldr r3, [r7, #4] 8010aee: 691b ldr r3, [r3, #16] 8010af0: 2b05 cmp r3, #5 8010af2: d10c bne.n 8010b0e 8010af4: 4b6a ldr r3, [pc, #424] @ (8010ca0 ) 8010af6: 6a1b ldr r3, [r3, #32] 8010af8: 4a69 ldr r2, [pc, #420] @ (8010ca0 ) 8010afa: f043 0304 orr.w r3, r3, #4 8010afe: 6213 str r3, [r2, #32] 8010b00: 4b67 ldr r3, [pc, #412] @ (8010ca0 ) 8010b02: 6a1b ldr r3, [r3, #32] 8010b04: 4a66 ldr r2, [pc, #408] @ (8010ca0 ) 8010b06: f043 0301 orr.w r3, r3, #1 8010b0a: 6213 str r3, [r2, #32] 8010b0c: e00b b.n 8010b26 8010b0e: 4b64 ldr r3, [pc, #400] @ (8010ca0 ) 8010b10: 6a1b ldr r3, [r3, #32] 8010b12: 4a63 ldr r2, [pc, #396] @ (8010ca0 ) 8010b14: f023 0301 bic.w r3, r3, #1 8010b18: 6213 str r3, [r2, #32] 8010b1a: 4b61 ldr r3, [pc, #388] @ (8010ca0 ) 8010b1c: 6a1b ldr r3, [r3, #32] 8010b1e: 4a60 ldr r2, [pc, #384] @ (8010ca0 ) 8010b20: f023 0304 bic.w r3, r3, #4 8010b24: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8010b26: 687b ldr r3, [r7, #4] 8010b28: 691b ldr r3, [r3, #16] 8010b2a: 2b00 cmp r3, #0 8010b2c: d015 beq.n 8010b5a { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010b2e: f7fd f8d3 bl 800dcd8 8010b32: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8010b34: e00a b.n 8010b4c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8010b36: f7fd f8cf bl 800dcd8 8010b3a: 4602 mov r2, r0 8010b3c: 693b ldr r3, [r7, #16] 8010b3e: 1ad3 subs r3, r2, r3 8010b40: f241 3288 movw r2, #5000 @ 0x1388 8010b44: 4293 cmp r3, r2 8010b46: d901 bls.n 8010b4c { return HAL_TIMEOUT; 8010b48: 2303 movs r3, #3 8010b4a: e143 b.n 8010dd4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8010b4c: 4b54 ldr r3, [pc, #336] @ (8010ca0 ) 8010b4e: 6a1b ldr r3, [r3, #32] 8010b50: f003 0302 and.w r3, r3, #2 8010b54: 2b00 cmp r3, #0 8010b56: d0ee beq.n 8010b36 8010b58: e014 b.n 8010b84 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010b5a: f7fd f8bd bl 800dcd8 8010b5e: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8010b60: e00a b.n 8010b78 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8010b62: f7fd f8b9 bl 800dcd8 8010b66: 4602 mov r2, r0 8010b68: 693b ldr r3, [r7, #16] 8010b6a: 1ad3 subs r3, r2, r3 8010b6c: f241 3288 movw r2, #5000 @ 0x1388 8010b70: 4293 cmp r3, r2 8010b72: d901 bls.n 8010b78 { return HAL_TIMEOUT; 8010b74: 2303 movs r3, #3 8010b76: e12d b.n 8010dd4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8010b78: 4b49 ldr r3, [pc, #292] @ (8010ca0 ) 8010b7a: 6a1b ldr r3, [r3, #32] 8010b7c: f003 0302 and.w r3, r3, #2 8010b80: 2b00 cmp r3, #0 8010b82: d1ee bne.n 8010b62 } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8010b84: 7dfb ldrb r3, [r7, #23] 8010b86: 2b01 cmp r3, #1 8010b88: d105 bne.n 8010b96 { __HAL_RCC_PWR_CLK_DISABLE(); 8010b8a: 4b45 ldr r3, [pc, #276] @ (8010ca0 ) 8010b8c: 69db ldr r3, [r3, #28] 8010b8e: 4a44 ldr r2, [pc, #272] @ (8010ca0 ) 8010b90: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8010b94: 61d3 str r3, [r2, #28] #if defined(RCC_CR_PLL2ON) /*-------------------------------- PLL2 Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) 8010b96: 687b ldr r3, [r7, #4] 8010b98: 6adb ldr r3, [r3, #44] @ 0x2c 8010b9a: 2b00 cmp r3, #0 8010b9c: f000 808c beq.w 8010cb8 { /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 8010ba0: 4b3f ldr r3, [pc, #252] @ (8010ca0 ) 8010ba2: 685b ldr r3, [r3, #4] 8010ba4: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010ba8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010bac: d10e bne.n 8010bcc (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 8010bae: 4b3c ldr r3, [pc, #240] @ (8010ca0 ) 8010bb0: 685b ldr r3, [r3, #4] 8010bb2: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 8010bb6: 2b08 cmp r3, #8 8010bb8: d108 bne.n 8010bcc ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) 8010bba: 4b39 ldr r3, [pc, #228] @ (8010ca0 ) 8010bbc: 6adb ldr r3, [r3, #44] @ 0x2c 8010bbe: f403 3380 and.w r3, r3, #65536 @ 0x10000 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 8010bc2: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010bc6: d101 bne.n 8010bcc { return HAL_ERROR; 8010bc8: 2301 movs r3, #1 8010bca: e103 b.n 8010dd4 } else { if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) 8010bcc: 687b ldr r3, [r7, #4] 8010bce: 6adb ldr r3, [r3, #44] @ 0x2c 8010bd0: 2b02 cmp r3, #2 8010bd2: d14e bne.n 8010c72 assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); /* Prediv2 can be written only when the PLLI2S is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 8010bd4: 4b32 ldr r3, [pc, #200] @ (8010ca0 ) 8010bd6: 681b ldr r3, [r3, #0] 8010bd8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010bdc: 2b00 cmp r3, #0 8010bde: d009 beq.n 8010bf4 (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) 8010be0: 4b2f ldr r3, [pc, #188] @ (8010ca0 ) 8010be2: 6adb ldr r3, [r3, #44] @ 0x2c 8010be4: f003 02f0 and.w r2, r3, #240 @ 0xf0 8010be8: 687b ldr r3, [r7, #4] 8010bea: 6b5b ldr r3, [r3, #52] @ 0x34 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 8010bec: 429a cmp r2, r3 8010bee: d001 beq.n 8010bf4 { return HAL_ERROR; 8010bf0: 2301 movs r3, #1 8010bf2: e0ef b.n 8010dd4 } /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 8010bf4: 4b2c ldr r3, [pc, #176] @ (8010ca8 ) 8010bf6: 2200 movs r2, #0 8010bf8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010bfa: f7fd f86d bl 800dcd8 8010bfe: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8010c00: e008 b.n 8010c14 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8010c02: f7fd f869 bl 800dcd8 8010c06: 4602 mov r2, r0 8010c08: 693b ldr r3, [r7, #16] 8010c0a: 1ad3 subs r3, r2, r3 8010c0c: 2b64 cmp r3, #100 @ 0x64 8010c0e: d901 bls.n 8010c14 { return HAL_TIMEOUT; 8010c10: 2303 movs r3, #3 8010c12: e0df b.n 8010dd4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8010c14: 4b22 ldr r3, [pc, #136] @ (8010ca0 ) 8010c16: 681b ldr r3, [r3, #0] 8010c18: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8010c1c: 2b00 cmp r3, #0 8010c1e: d1f0 bne.n 8010c02 } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); 8010c20: 4b1f ldr r3, [pc, #124] @ (8010ca0 ) 8010c22: 6adb ldr r3, [r3, #44] @ 0x2c 8010c24: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8010c28: 687b ldr r3, [r7, #4] 8010c2a: 6b5b ldr r3, [r3, #52] @ 0x34 8010c2c: 491c ldr r1, [pc, #112] @ (8010ca0 ) 8010c2e: 4313 orrs r3, r2 8010c30: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); 8010c32: 4b1b ldr r3, [pc, #108] @ (8010ca0 ) 8010c34: 6adb ldr r3, [r3, #44] @ 0x2c 8010c36: f423 6270 bic.w r2, r3, #3840 @ 0xf00 8010c3a: 687b ldr r3, [r7, #4] 8010c3c: 6b1b ldr r3, [r3, #48] @ 0x30 8010c3e: 4918 ldr r1, [pc, #96] @ (8010ca0 ) 8010c40: 4313 orrs r3, r2 8010c42: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); 8010c44: 4b18 ldr r3, [pc, #96] @ (8010ca8 ) 8010c46: 2201 movs r2, #1 8010c48: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010c4a: f7fd f845 bl 800dcd8 8010c4e: 6138 str r0, [r7, #16] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8010c50: e008 b.n 8010c64 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8010c52: f7fd f841 bl 800dcd8 8010c56: 4602 mov r2, r0 8010c58: 693b ldr r3, [r7, #16] 8010c5a: 1ad3 subs r3, r2, r3 8010c5c: 2b64 cmp r3, #100 @ 0x64 8010c5e: d901 bls.n 8010c64 { return HAL_TIMEOUT; 8010c60: 2303 movs r3, #3 8010c62: e0b7 b.n 8010dd4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8010c64: 4b0e ldr r3, [pc, #56] @ (8010ca0 ) 8010c66: 681b ldr r3, [r3, #0] 8010c68: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8010c6c: 2b00 cmp r3, #0 8010c6e: d0f0 beq.n 8010c52 8010c70: e022 b.n 8010cb8 } } else { /* Set PREDIV1 source to HSE */ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); 8010c72: 4b0b ldr r3, [pc, #44] @ (8010ca0 ) 8010c74: 6adb ldr r3, [r3, #44] @ 0x2c 8010c76: 4a0a ldr r2, [pc, #40] @ (8010ca0 ) 8010c78: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8010c7c: 62d3 str r3, [r2, #44] @ 0x2c /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 8010c7e: 4b0a ldr r3, [pc, #40] @ (8010ca8 ) 8010c80: 2200 movs r2, #0 8010c82: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010c84: f7fd f828 bl 800dcd8 8010c88: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8010c8a: e00f b.n 8010cac { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8010c8c: f7fd f824 bl 800dcd8 8010c90: 4602 mov r2, r0 8010c92: 693b ldr r3, [r7, #16] 8010c94: 1ad3 subs r3, r2, r3 8010c96: 2b64 cmp r3, #100 @ 0x64 8010c98: d908 bls.n 8010cac { return HAL_TIMEOUT; 8010c9a: 2303 movs r3, #3 8010c9c: e09a b.n 8010dd4 8010c9e: bf00 nop 8010ca0: 40021000 .word 0x40021000 8010ca4: 40007000 .word 0x40007000 8010ca8: 42420068 .word 0x42420068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8010cac: 4b4b ldr r3, [pc, #300] @ (8010ddc ) 8010cae: 681b ldr r3, [r3, #0] 8010cb0: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8010cb4: 2b00 cmp r3, #0 8010cb6: d1e9 bne.n 8010c8c #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8010cb8: 687b ldr r3, [r7, #4] 8010cba: 6a1b ldr r3, [r3, #32] 8010cbc: 2b00 cmp r3, #0 8010cbe: f000 8088 beq.w 8010dd2 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8010cc2: 4b46 ldr r3, [pc, #280] @ (8010ddc ) 8010cc4: 685b ldr r3, [r3, #4] 8010cc6: f003 030c and.w r3, r3, #12 8010cca: 2b08 cmp r3, #8 8010ccc: d068 beq.n 8010da0 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8010cce: 687b ldr r3, [r7, #4] 8010cd0: 6a1b ldr r3, [r3, #32] 8010cd2: 2b02 cmp r3, #2 8010cd4: d14d bne.n 8010d72 /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8010cd6: 4b42 ldr r3, [pc, #264] @ (8010de0 ) 8010cd8: 2200 movs r2, #0 8010cda: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010cdc: f7fc fffc bl 800dcd8 8010ce0: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8010ce2: e008 b.n 8010cf6 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8010ce4: f7fc fff8 bl 800dcd8 8010ce8: 4602 mov r2, r0 8010cea: 693b ldr r3, [r7, #16] 8010cec: 1ad3 subs r3, r2, r3 8010cee: 2b02 cmp r3, #2 8010cf0: d901 bls.n 8010cf6 { return HAL_TIMEOUT; 8010cf2: 2303 movs r3, #3 8010cf4: e06e b.n 8010dd4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8010cf6: 4b39 ldr r3, [pc, #228] @ (8010ddc ) 8010cf8: 681b ldr r3, [r3, #0] 8010cfa: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8010cfe: 2b00 cmp r3, #0 8010d00: d1f0 bne.n 8010ce4 } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 8010d02: 687b ldr r3, [r7, #4] 8010d04: 6a5b ldr r3, [r3, #36] @ 0x24 8010d06: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010d0a: d10f bne.n 8010d2c assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); #if defined(RCC_CFGR2_PREDIV1SRC) assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); 8010d0c: 4b33 ldr r3, [pc, #204] @ (8010ddc ) 8010d0e: 6ada ldr r2, [r3, #44] @ 0x2c 8010d10: 687b ldr r3, [r7, #4] 8010d12: 685b ldr r3, [r3, #4] 8010d14: 4931 ldr r1, [pc, #196] @ (8010ddc ) 8010d16: 4313 orrs r3, r2 8010d18: 62cb str r3, [r1, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8010d1a: 4b30 ldr r3, [pc, #192] @ (8010ddc ) 8010d1c: 6adb ldr r3, [r3, #44] @ 0x2c 8010d1e: f023 020f bic.w r2, r3, #15 8010d22: 687b ldr r3, [r7, #4] 8010d24: 68db ldr r3, [r3, #12] 8010d26: 492d ldr r1, [pc, #180] @ (8010ddc ) 8010d28: 4313 orrs r3, r2 8010d2a: 62cb str r3, [r1, #44] @ 0x2c } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8010d2c: 4b2b ldr r3, [pc, #172] @ (8010ddc ) 8010d2e: 685b ldr r3, [r3, #4] 8010d30: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 8010d34: 687b ldr r3, [r7, #4] 8010d36: 6a59 ldr r1, [r3, #36] @ 0x24 8010d38: 687b ldr r3, [r7, #4] 8010d3a: 6a9b ldr r3, [r3, #40] @ 0x28 8010d3c: 430b orrs r3, r1 8010d3e: 4927 ldr r1, [pc, #156] @ (8010ddc ) 8010d40: 4313 orrs r3, r2 8010d42: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8010d44: 4b26 ldr r3, [pc, #152] @ (8010de0 ) 8010d46: 2201 movs r2, #1 8010d48: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010d4a: f7fc ffc5 bl 800dcd8 8010d4e: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8010d50: e008 b.n 8010d64 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8010d52: f7fc ffc1 bl 800dcd8 8010d56: 4602 mov r2, r0 8010d58: 693b ldr r3, [r7, #16] 8010d5a: 1ad3 subs r3, r2, r3 8010d5c: 2b02 cmp r3, #2 8010d5e: d901 bls.n 8010d64 { return HAL_TIMEOUT; 8010d60: 2303 movs r3, #3 8010d62: e037 b.n 8010dd4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8010d64: 4b1d ldr r3, [pc, #116] @ (8010ddc ) 8010d66: 681b ldr r3, [r3, #0] 8010d68: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8010d6c: 2b00 cmp r3, #0 8010d6e: d0f0 beq.n 8010d52 8010d70: e02f b.n 8010dd2 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8010d72: 4b1b ldr r3, [pc, #108] @ (8010de0 ) 8010d74: 2200 movs r2, #0 8010d76: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010d78: f7fc ffae bl 800dcd8 8010d7c: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8010d7e: e008 b.n 8010d92 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8010d80: f7fc ffaa bl 800dcd8 8010d84: 4602 mov r2, r0 8010d86: 693b ldr r3, [r7, #16] 8010d88: 1ad3 subs r3, r2, r3 8010d8a: 2b02 cmp r3, #2 8010d8c: d901 bls.n 8010d92 { return HAL_TIMEOUT; 8010d8e: 2303 movs r3, #3 8010d90: e020 b.n 8010dd4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8010d92: 4b12 ldr r3, [pc, #72] @ (8010ddc ) 8010d94: 681b ldr r3, [r3, #0] 8010d96: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8010d9a: 2b00 cmp r3, #0 8010d9c: d1f0 bne.n 8010d80 8010d9e: e018 b.n 8010dd2 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8010da0: 687b ldr r3, [r7, #4] 8010da2: 6a1b ldr r3, [r3, #32] 8010da4: 2b01 cmp r3, #1 8010da6: d101 bne.n 8010dac { return HAL_ERROR; 8010da8: 2301 movs r3, #1 8010daa: e013 b.n 8010dd4 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8010dac: 4b0b ldr r3, [pc, #44] @ (8010ddc ) 8010dae: 685b ldr r3, [r3, #4] 8010db0: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8010db2: 68fb ldr r3, [r7, #12] 8010db4: f403 3280 and.w r2, r3, #65536 @ 0x10000 8010db8: 687b ldr r3, [r7, #4] 8010dba: 6a5b ldr r3, [r3, #36] @ 0x24 8010dbc: 429a cmp r2, r3 8010dbe: d106 bne.n 8010dce (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8010dc0: 68fb ldr r3, [r7, #12] 8010dc2: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 8010dc6: 687b ldr r3, [r7, #4] 8010dc8: 6a9b ldr r3, [r3, #40] @ 0x28 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8010dca: 429a cmp r2, r3 8010dcc: d001 beq.n 8010dd2 { return HAL_ERROR; 8010dce: 2301 movs r3, #1 8010dd0: e000 b.n 8010dd4 } } } } return HAL_OK; 8010dd2: 2300 movs r3, #0 } 8010dd4: 4618 mov r0, r3 8010dd6: 3718 adds r7, #24 8010dd8: 46bd mov sp, r7 8010dda: bd80 pop {r7, pc} 8010ddc: 40021000 .word 0x40021000 8010de0: 42420060 .word 0x42420060 08010de4 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8010de4: b580 push {r7, lr} 8010de6: b084 sub sp, #16 8010de8: af00 add r7, sp, #0 8010dea: 6078 str r0, [r7, #4] 8010dec: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8010dee: 687b ldr r3, [r7, #4] 8010df0: 2b00 cmp r3, #0 8010df2: d101 bne.n 8010df8 { return HAL_ERROR; 8010df4: 2301 movs r3, #1 8010df6: e0d0 b.n 8010f9a must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8010df8: 4b6a ldr r3, [pc, #424] @ (8010fa4 ) 8010dfa: 681b ldr r3, [r3, #0] 8010dfc: f003 0307 and.w r3, r3, #7 8010e00: 683a ldr r2, [r7, #0] 8010e02: 429a cmp r2, r3 8010e04: d910 bls.n 8010e28 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8010e06: 4b67 ldr r3, [pc, #412] @ (8010fa4 ) 8010e08: 681b ldr r3, [r3, #0] 8010e0a: f023 0207 bic.w r2, r3, #7 8010e0e: 4965 ldr r1, [pc, #404] @ (8010fa4 ) 8010e10: 683b ldr r3, [r7, #0] 8010e12: 4313 orrs r3, r2 8010e14: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8010e16: 4b63 ldr r3, [pc, #396] @ (8010fa4 ) 8010e18: 681b ldr r3, [r3, #0] 8010e1a: f003 0307 and.w r3, r3, #7 8010e1e: 683a ldr r2, [r7, #0] 8010e20: 429a cmp r2, r3 8010e22: d001 beq.n 8010e28 { return HAL_ERROR; 8010e24: 2301 movs r3, #1 8010e26: e0b8 b.n 8010f9a } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8010e28: 687b ldr r3, [r7, #4] 8010e2a: 681b ldr r3, [r3, #0] 8010e2c: f003 0302 and.w r3, r3, #2 8010e30: 2b00 cmp r3, #0 8010e32: d020 beq.n 8010e76 { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8010e34: 687b ldr r3, [r7, #4] 8010e36: 681b ldr r3, [r3, #0] 8010e38: f003 0304 and.w r3, r3, #4 8010e3c: 2b00 cmp r3, #0 8010e3e: d005 beq.n 8010e4c { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8010e40: 4b59 ldr r3, [pc, #356] @ (8010fa8 ) 8010e42: 685b ldr r3, [r3, #4] 8010e44: 4a58 ldr r2, [pc, #352] @ (8010fa8 ) 8010e46: f443 63e0 orr.w r3, r3, #1792 @ 0x700 8010e4a: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8010e4c: 687b ldr r3, [r7, #4] 8010e4e: 681b ldr r3, [r3, #0] 8010e50: f003 0308 and.w r3, r3, #8 8010e54: 2b00 cmp r3, #0 8010e56: d005 beq.n 8010e64 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8010e58: 4b53 ldr r3, [pc, #332] @ (8010fa8 ) 8010e5a: 685b ldr r3, [r3, #4] 8010e5c: 4a52 ldr r2, [pc, #328] @ (8010fa8 ) 8010e5e: f443 5360 orr.w r3, r3, #14336 @ 0x3800 8010e62: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8010e64: 4b50 ldr r3, [pc, #320] @ (8010fa8 ) 8010e66: 685b ldr r3, [r3, #4] 8010e68: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8010e6c: 687b ldr r3, [r7, #4] 8010e6e: 689b ldr r3, [r3, #8] 8010e70: 494d ldr r1, [pc, #308] @ (8010fa8 ) 8010e72: 4313 orrs r3, r2 8010e74: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8010e76: 687b ldr r3, [r7, #4] 8010e78: 681b ldr r3, [r3, #0] 8010e7a: f003 0301 and.w r3, r3, #1 8010e7e: 2b00 cmp r3, #0 8010e80: d040 beq.n 8010f04 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8010e82: 687b ldr r3, [r7, #4] 8010e84: 685b ldr r3, [r3, #4] 8010e86: 2b01 cmp r3, #1 8010e88: d107 bne.n 8010e9a { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8010e8a: 4b47 ldr r3, [pc, #284] @ (8010fa8 ) 8010e8c: 681b ldr r3, [r3, #0] 8010e8e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010e92: 2b00 cmp r3, #0 8010e94: d115 bne.n 8010ec2 { return HAL_ERROR; 8010e96: 2301 movs r3, #1 8010e98: e07f b.n 8010f9a } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8010e9a: 687b ldr r3, [r7, #4] 8010e9c: 685b ldr r3, [r3, #4] 8010e9e: 2b02 cmp r3, #2 8010ea0: d107 bne.n 8010eb2 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8010ea2: 4b41 ldr r3, [pc, #260] @ (8010fa8 ) 8010ea4: 681b ldr r3, [r3, #0] 8010ea6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8010eaa: 2b00 cmp r3, #0 8010eac: d109 bne.n 8010ec2 { return HAL_ERROR; 8010eae: 2301 movs r3, #1 8010eb0: e073 b.n 8010f9a } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8010eb2: 4b3d ldr r3, [pc, #244] @ (8010fa8 ) 8010eb4: 681b ldr r3, [r3, #0] 8010eb6: f003 0302 and.w r3, r3, #2 8010eba: 2b00 cmp r3, #0 8010ebc: d101 bne.n 8010ec2 { return HAL_ERROR; 8010ebe: 2301 movs r3, #1 8010ec0: e06b b.n 8010f9a } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8010ec2: 4b39 ldr r3, [pc, #228] @ (8010fa8 ) 8010ec4: 685b ldr r3, [r3, #4] 8010ec6: f023 0203 bic.w r2, r3, #3 8010eca: 687b ldr r3, [r7, #4] 8010ecc: 685b ldr r3, [r3, #4] 8010ece: 4936 ldr r1, [pc, #216] @ (8010fa8 ) 8010ed0: 4313 orrs r3, r2 8010ed2: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010ed4: f7fc ff00 bl 800dcd8 8010ed8: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8010eda: e00a b.n 8010ef2 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8010edc: f7fc fefc bl 800dcd8 8010ee0: 4602 mov r2, r0 8010ee2: 68fb ldr r3, [r7, #12] 8010ee4: 1ad3 subs r3, r2, r3 8010ee6: f241 3288 movw r2, #5000 @ 0x1388 8010eea: 4293 cmp r3, r2 8010eec: d901 bls.n 8010ef2 { return HAL_TIMEOUT; 8010eee: 2303 movs r3, #3 8010ef0: e053 b.n 8010f9a while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8010ef2: 4b2d ldr r3, [pc, #180] @ (8010fa8 ) 8010ef4: 685b ldr r3, [r3, #4] 8010ef6: f003 020c and.w r2, r3, #12 8010efa: 687b ldr r3, [r7, #4] 8010efc: 685b ldr r3, [r3, #4] 8010efe: 009b lsls r3, r3, #2 8010f00: 429a cmp r2, r3 8010f02: d1eb bne.n 8010edc } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8010f04: 4b27 ldr r3, [pc, #156] @ (8010fa4 ) 8010f06: 681b ldr r3, [r3, #0] 8010f08: f003 0307 and.w r3, r3, #7 8010f0c: 683a ldr r2, [r7, #0] 8010f0e: 429a cmp r2, r3 8010f10: d210 bcs.n 8010f34 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8010f12: 4b24 ldr r3, [pc, #144] @ (8010fa4 ) 8010f14: 681b ldr r3, [r3, #0] 8010f16: f023 0207 bic.w r2, r3, #7 8010f1a: 4922 ldr r1, [pc, #136] @ (8010fa4 ) 8010f1c: 683b ldr r3, [r7, #0] 8010f1e: 4313 orrs r3, r2 8010f20: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8010f22: 4b20 ldr r3, [pc, #128] @ (8010fa4 ) 8010f24: 681b ldr r3, [r3, #0] 8010f26: f003 0307 and.w r3, r3, #7 8010f2a: 683a ldr r2, [r7, #0] 8010f2c: 429a cmp r2, r3 8010f2e: d001 beq.n 8010f34 { return HAL_ERROR; 8010f30: 2301 movs r3, #1 8010f32: e032 b.n 8010f9a } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8010f34: 687b ldr r3, [r7, #4] 8010f36: 681b ldr r3, [r3, #0] 8010f38: f003 0304 and.w r3, r3, #4 8010f3c: 2b00 cmp r3, #0 8010f3e: d008 beq.n 8010f52 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8010f40: 4b19 ldr r3, [pc, #100] @ (8010fa8 ) 8010f42: 685b ldr r3, [r3, #4] 8010f44: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8010f48: 687b ldr r3, [r7, #4] 8010f4a: 68db ldr r3, [r3, #12] 8010f4c: 4916 ldr r1, [pc, #88] @ (8010fa8 ) 8010f4e: 4313 orrs r3, r2 8010f50: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8010f52: 687b ldr r3, [r7, #4] 8010f54: 681b ldr r3, [r3, #0] 8010f56: f003 0308 and.w r3, r3, #8 8010f5a: 2b00 cmp r3, #0 8010f5c: d009 beq.n 8010f72 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 8010f5e: 4b12 ldr r3, [pc, #72] @ (8010fa8 ) 8010f60: 685b ldr r3, [r3, #4] 8010f62: f423 5260 bic.w r2, r3, #14336 @ 0x3800 8010f66: 687b ldr r3, [r7, #4] 8010f68: 691b ldr r3, [r3, #16] 8010f6a: 00db lsls r3, r3, #3 8010f6c: 490e ldr r1, [pc, #56] @ (8010fa8 ) 8010f6e: 4313 orrs r3, r2 8010f70: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8010f72: f000 f821 bl 8010fb8 8010f76: 4602 mov r2, r0 8010f78: 4b0b ldr r3, [pc, #44] @ (8010fa8 ) 8010f7a: 685b ldr r3, [r3, #4] 8010f7c: 091b lsrs r3, r3, #4 8010f7e: f003 030f and.w r3, r3, #15 8010f82: 490a ldr r1, [pc, #40] @ (8010fac ) 8010f84: 5ccb ldrb r3, [r1, r3] 8010f86: fa22 f303 lsr.w r3, r2, r3 8010f8a: 4a09 ldr r2, [pc, #36] @ (8010fb0 ) 8010f8c: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 8010f8e: 4b09 ldr r3, [pc, #36] @ (8010fb4 ) 8010f90: 681b ldr r3, [r3, #0] 8010f92: 4618 mov r0, r3 8010f94: f7fc fe5e bl 800dc54 return HAL_OK; 8010f98: 2300 movs r3, #0 } 8010f9a: 4618 mov r0, r3 8010f9c: 3710 adds r7, #16 8010f9e: 46bd mov sp, r7 8010fa0: bd80 pop {r7, pc} 8010fa2: bf00 nop 8010fa4: 40022000 .word 0x40022000 8010fa8: 40021000 .word 0x40021000 8010fac: 08016e84 .word 0x08016e84 8010fb0: 2000006c .word 0x2000006c 8010fb4: 20000070 .word 0x20000070 08010fb8 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8010fb8: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8010fbc: b08e sub sp, #56 @ 0x38 8010fbe: af00 add r7, sp, #0 #else static const uint8_t aPredivFactorTable[2U] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8010fc0: 2300 movs r3, #0 8010fc2: 62fb str r3, [r7, #44] @ 0x2c 8010fc4: 2300 movs r3, #0 8010fc6: 62bb str r3, [r7, #40] @ 0x28 8010fc8: 2300 movs r3, #0 8010fca: 637b str r3, [r7, #52] @ 0x34 8010fcc: 2300 movs r3, #0 8010fce: 627b str r3, [r7, #36] @ 0x24 uint32_t sysclockfreq = 0U; 8010fd0: 2300 movs r3, #0 8010fd2: 633b str r3, [r7, #48] @ 0x30 #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; 8010fd4: 2300 movs r3, #0 8010fd6: 623b str r3, [r7, #32] 8010fd8: 2300 movs r3, #0 8010fda: 61fb str r3, [r7, #28] #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 8010fdc: 4b4e ldr r3, [pc, #312] @ (8011118 ) 8010fde: 685b ldr r3, [r3, #4] 8010fe0: 62fb str r3, [r7, #44] @ 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8010fe2: 6afb ldr r3, [r7, #44] @ 0x2c 8010fe4: f003 030c and.w r3, r3, #12 8010fe8: 2b04 cmp r3, #4 8010fea: d002 beq.n 8010ff2 8010fec: 2b08 cmp r3, #8 8010fee: d003 beq.n 8010ff8 8010ff0: e089 b.n 8011106 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8010ff2: 4b4a ldr r3, [pc, #296] @ (801111c ) 8010ff4: 633b str r3, [r7, #48] @ 0x30 break; 8010ff6: e089 b.n 801110c } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8010ff8: 6afb ldr r3, [r7, #44] @ 0x2c 8010ffa: 0c9b lsrs r3, r3, #18 8010ffc: f003 020f and.w r2, r3, #15 8011000: 4b47 ldr r3, [pc, #284] @ (8011120 ) 8011002: 5c9b ldrb r3, [r3, r2] 8011004: 627b str r3, [r7, #36] @ 0x24 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8011006: 6afb ldr r3, [r7, #44] @ 0x2c 8011008: f403 3380 and.w r3, r3, #65536 @ 0x10000 801100c: 2b00 cmp r3, #0 801100e: d072 beq.n 80110f6 { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 8011010: 4b41 ldr r3, [pc, #260] @ (8011118 ) 8011012: 6adb ldr r3, [r3, #44] @ 0x2c 8011014: f003 020f and.w r2, r3, #15 8011018: 4b42 ldr r3, [pc, #264] @ (8011124 ) 801101a: 5c9b ldrb r3, [r3, r2] 801101c: 62bb str r3, [r7, #40] @ 0x28 #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /*RCC_CFGR2_PREDIV1*/ #if defined(RCC_CFGR2_PREDIV1SRC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 801101e: 4b3e ldr r3, [pc, #248] @ (8011118 ) 8011020: 6adb ldr r3, [r3, #44] @ 0x2c 8011022: f403 3380 and.w r3, r3, #65536 @ 0x10000 8011026: 2b00 cmp r3, #0 8011028: d053 beq.n 80110d2 { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 801102a: 4b3b ldr r3, [pc, #236] @ (8011118 ) 801102c: 6adb ldr r3, [r3, #44] @ 0x2c 801102e: 091b lsrs r3, r3, #4 8011030: f003 030f and.w r3, r3, #15 8011034: 3301 adds r3, #1 8011036: 623b str r3, [r7, #32] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 8011038: 4b37 ldr r3, [pc, #220] @ (8011118 ) 801103a: 6adb ldr r3, [r3, #44] @ 0x2c 801103c: 0a1b lsrs r3, r3, #8 801103e: f003 030f and.w r3, r3, #15 8011042: 3302 adds r3, #2 8011044: 61fb str r3, [r7, #28] pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); 8011046: 69fb ldr r3, [r7, #28] 8011048: 2200 movs r2, #0 801104a: 469a mov sl, r3 801104c: 4693 mov fp, r2 801104e: 6a7b ldr r3, [r7, #36] @ 0x24 8011050: 2200 movs r2, #0 8011052: 613b str r3, [r7, #16] 8011054: 617a str r2, [r7, #20] 8011056: 693b ldr r3, [r7, #16] 8011058: fb03 f20b mul.w r2, r3, fp 801105c: 697b ldr r3, [r7, #20] 801105e: fb0a f303 mul.w r3, sl, r3 8011062: 4413 add r3, r2 8011064: 693a ldr r2, [r7, #16] 8011066: fbaa 0102 umull r0, r1, sl, r2 801106a: 440b add r3, r1 801106c: 4619 mov r1, r3 801106e: 4b2b ldr r3, [pc, #172] @ (801111c ) 8011070: fb03 f201 mul.w r2, r3, r1 8011074: 2300 movs r3, #0 8011076: fb00 f303 mul.w r3, r0, r3 801107a: 4413 add r3, r2 801107c: 4a27 ldr r2, [pc, #156] @ (801111c ) 801107e: fba0 4502 umull r4, r5, r0, r2 8011082: 442b add r3, r5 8011084: 461d mov r5, r3 8011086: 6a3b ldr r3, [r7, #32] 8011088: 2200 movs r2, #0 801108a: 60bb str r3, [r7, #8] 801108c: 60fa str r2, [r7, #12] 801108e: 6abb ldr r3, [r7, #40] @ 0x28 8011090: 2200 movs r2, #0 8011092: 603b str r3, [r7, #0] 8011094: 607a str r2, [r7, #4] 8011096: e9d7 0102 ldrd r0, r1, [r7, #8] 801109a: 460b mov r3, r1 801109c: e9d7 ab00 ldrd sl, fp, [r7] 80110a0: 4652 mov r2, sl 80110a2: fb02 f203 mul.w r2, r2, r3 80110a6: 465b mov r3, fp 80110a8: 4684 mov ip, r0 80110aa: fb0c f303 mul.w r3, ip, r3 80110ae: 4413 add r3, r2 80110b0: 4602 mov r2, r0 80110b2: 4651 mov r1, sl 80110b4: fba2 8901 umull r8, r9, r2, r1 80110b8: 444b add r3, r9 80110ba: 4699 mov r9, r3 80110bc: 4642 mov r2, r8 80110be: 464b mov r3, r9 80110c0: 4620 mov r0, r4 80110c2: 4629 mov r1, r5 80110c4: f7f8 f896 bl 80091f4 <__aeabi_uldivmod> 80110c8: 4602 mov r2, r0 80110ca: 460b mov r3, r1 80110cc: 4613 mov r3, r2 80110ce: 637b str r3, [r7, #52] @ 0x34 80110d0: e007 b.n 80110e2 } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 80110d2: 6a7b ldr r3, [r7, #36] @ 0x24 80110d4: 4a11 ldr r2, [pc, #68] @ (801111c ) 80110d6: fb03 f202 mul.w r2, r3, r2 80110da: 6abb ldr r3, [r7, #40] @ 0x28 80110dc: fbb2 f3f3 udiv r3, r2, r3 80110e0: 637b str r3, [r7, #52] @ 0x34 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 80110e2: 4b0f ldr r3, [pc, #60] @ (8011120 ) 80110e4: 7b5b ldrb r3, [r3, #13] 80110e6: 461a mov r2, r3 80110e8: 6a7b ldr r3, [r7, #36] @ 0x24 80110ea: 4293 cmp r3, r2 80110ec: d108 bne.n 8011100 { pllclk = pllclk / 2; 80110ee: 6b7b ldr r3, [r7, #52] @ 0x34 80110f0: 085b lsrs r3, r3, #1 80110f2: 637b str r3, [r7, #52] @ 0x34 80110f4: e004 b.n 8011100 #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 80110f6: 6a7b ldr r3, [r7, #36] @ 0x24 80110f8: 4a0b ldr r2, [pc, #44] @ (8011128 ) 80110fa: fb02 f303 mul.w r3, r2, r3 80110fe: 637b str r3, [r7, #52] @ 0x34 } sysclockfreq = pllclk; 8011100: 6b7b ldr r3, [r7, #52] @ 0x34 8011102: 633b str r3, [r7, #48] @ 0x30 break; 8011104: e002 b.n 801110c } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8011106: 4b09 ldr r3, [pc, #36] @ (801112c ) 8011108: 633b str r3, [r7, #48] @ 0x30 break; 801110a: bf00 nop } } return sysclockfreq; 801110c: 6b3b ldr r3, [r7, #48] @ 0x30 } 801110e: 4618 mov r0, r3 8011110: 3738 adds r7, #56 @ 0x38 8011112: 46bd mov sp, r7 8011114: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8011118: 40021000 .word 0x40021000 801111c: 017d7840 .word 0x017d7840 8011120: 08016e9c .word 0x08016e9c 8011124: 08016eac .word 0x08016eac 8011128: 003d0900 .word 0x003d0900 801112c: 007a1200 .word 0x007a1200 08011130 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8011130: b480 push {r7} 8011132: af00 add r7, sp, #0 return SystemCoreClock; 8011134: 4b02 ldr r3, [pc, #8] @ (8011140 ) 8011136: 681b ldr r3, [r3, #0] } 8011138: 4618 mov r0, r3 801113a: 46bd mov sp, r7 801113c: bc80 pop {r7} 801113e: 4770 bx lr 8011140: 2000006c .word 0x2000006c 08011144 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8011144: b580 push {r7, lr} 8011146: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8011148: f7ff fff2 bl 8011130 801114c: 4602 mov r2, r0 801114e: 4b05 ldr r3, [pc, #20] @ (8011164 ) 8011150: 685b ldr r3, [r3, #4] 8011152: 0a1b lsrs r3, r3, #8 8011154: f003 0307 and.w r3, r3, #7 8011158: 4903 ldr r1, [pc, #12] @ (8011168 ) 801115a: 5ccb ldrb r3, [r1, r3] 801115c: fa22 f303 lsr.w r3, r2, r3 } 8011160: 4618 mov r0, r3 8011162: bd80 pop {r7, pc} 8011164: 40021000 .word 0x40021000 8011168: 08016e94 .word 0x08016e94 0801116c : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 801116c: b580 push {r7, lr} 801116e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8011170: f7ff ffde bl 8011130 8011174: 4602 mov r2, r0 8011176: 4b05 ldr r3, [pc, #20] @ (801118c ) 8011178: 685b ldr r3, [r3, #4] 801117a: 0adb lsrs r3, r3, #11 801117c: f003 0307 and.w r3, r3, #7 8011180: 4903 ldr r1, [pc, #12] @ (8011190 ) 8011182: 5ccb ldrb r3, [r1, r3] 8011184: fa22 f303 lsr.w r3, r2, r3 } 8011188: 4618 mov r0, r3 801118a: bd80 pop {r7, pc} 801118c: 40021000 .word 0x40021000 8011190: 08016e94 .word 0x08016e94 08011194 : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8011194: b480 push {r7} 8011196: b085 sub sp, #20 8011198: af00 add r7, sp, #0 801119a: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 801119c: 4b0a ldr r3, [pc, #40] @ (80111c8 ) 801119e: 681b ldr r3, [r3, #0] 80111a0: 4a0a ldr r2, [pc, #40] @ (80111cc ) 80111a2: fba2 2303 umull r2, r3, r2, r3 80111a6: 0a5b lsrs r3, r3, #9 80111a8: 687a ldr r2, [r7, #4] 80111aa: fb02 f303 mul.w r3, r2, r3 80111ae: 60fb str r3, [r7, #12] do { __NOP(); 80111b0: bf00 nop } while (Delay --); 80111b2: 68fb ldr r3, [r7, #12] 80111b4: 1e5a subs r2, r3, #1 80111b6: 60fa str r2, [r7, #12] 80111b8: 2b00 cmp r3, #0 80111ba: d1f9 bne.n 80111b0 } 80111bc: bf00 nop 80111be: bf00 nop 80111c0: 3714 adds r7, #20 80111c2: 46bd mov sp, r7 80111c4: bc80 pop {r7} 80111c6: 4770 bx lr 80111c8: 2000006c .word 0x2000006c 80111cc: 10624dd3 .word 0x10624dd3 080111d0 : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 80111d0: b580 push {r7, lr} 80111d2: b088 sub sp, #32 80111d4: af00 add r7, sp, #0 80111d6: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 80111d8: 2300 movs r3, #0 80111da: 617b str r3, [r7, #20] 80111dc: 2300 movs r3, #0 80111de: 613b str r3, [r7, #16] #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t pllactive = 0U; 80111e0: 2300 movs r3, #0 80111e2: 61fb str r3, [r7, #28] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 80111e4: 687b ldr r3, [r7, #4] 80111e6: 681b ldr r3, [r3, #0] 80111e8: f003 0301 and.w r3, r3, #1 80111ec: 2b00 cmp r3, #0 80111ee: d07d beq.n 80112ec { FlagStatus pwrclkchanged = RESET; 80111f0: 2300 movs r3, #0 80111f2: 76fb strb r3, [r7, #27] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80111f4: 4b8b ldr r3, [pc, #556] @ (8011424 ) 80111f6: 69db ldr r3, [r3, #28] 80111f8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80111fc: 2b00 cmp r3, #0 80111fe: d10d bne.n 801121c { __HAL_RCC_PWR_CLK_ENABLE(); 8011200: 4b88 ldr r3, [pc, #544] @ (8011424 ) 8011202: 69db ldr r3, [r3, #28] 8011204: 4a87 ldr r2, [pc, #540] @ (8011424 ) 8011206: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 801120a: 61d3 str r3, [r2, #28] 801120c: 4b85 ldr r3, [pc, #532] @ (8011424 ) 801120e: 69db ldr r3, [r3, #28] 8011210: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011214: 60fb str r3, [r7, #12] 8011216: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8011218: 2301 movs r3, #1 801121a: 76fb strb r3, [r7, #27] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 801121c: 4b82 ldr r3, [pc, #520] @ (8011428 ) 801121e: 681b ldr r3, [r3, #0] 8011220: f403 7380 and.w r3, r3, #256 @ 0x100 8011224: 2b00 cmp r3, #0 8011226: d118 bne.n 801125a { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8011228: 4b7f ldr r3, [pc, #508] @ (8011428 ) 801122a: 681b ldr r3, [r3, #0] 801122c: 4a7e ldr r2, [pc, #504] @ (8011428 ) 801122e: f443 7380 orr.w r3, r3, #256 @ 0x100 8011232: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8011234: f7fc fd50 bl 800dcd8 8011238: 6178 str r0, [r7, #20] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 801123a: e008 b.n 801124e { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 801123c: f7fc fd4c bl 800dcd8 8011240: 4602 mov r2, r0 8011242: 697b ldr r3, [r7, #20] 8011244: 1ad3 subs r3, r2, r3 8011246: 2b64 cmp r3, #100 @ 0x64 8011248: d901 bls.n 801124e { return HAL_TIMEOUT; 801124a: 2303 movs r3, #3 801124c: e0e5 b.n 801141a while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 801124e: 4b76 ldr r3, [pc, #472] @ (8011428 ) 8011250: 681b ldr r3, [r3, #0] 8011252: f403 7380 and.w r3, r3, #256 @ 0x100 8011256: 2b00 cmp r3, #0 8011258: d0f0 beq.n 801123c } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 801125a: 4b72 ldr r3, [pc, #456] @ (8011424 ) 801125c: 6a1b ldr r3, [r3, #32] 801125e: f403 7340 and.w r3, r3, #768 @ 0x300 8011262: 613b str r3, [r7, #16] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8011264: 693b ldr r3, [r7, #16] 8011266: 2b00 cmp r3, #0 8011268: d02e beq.n 80112c8 801126a: 687b ldr r3, [r7, #4] 801126c: 685b ldr r3, [r3, #4] 801126e: f403 7340 and.w r3, r3, #768 @ 0x300 8011272: 693a ldr r2, [r7, #16] 8011274: 429a cmp r2, r3 8011276: d027 beq.n 80112c8 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8011278: 4b6a ldr r3, [pc, #424] @ (8011424 ) 801127a: 6a1b ldr r3, [r3, #32] 801127c: f423 7340 bic.w r3, r3, #768 @ 0x300 8011280: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8011282: 4b6a ldr r3, [pc, #424] @ (801142c ) 8011284: 2201 movs r2, #1 8011286: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8011288: 4b68 ldr r3, [pc, #416] @ (801142c ) 801128a: 2200 movs r2, #0 801128c: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 801128e: 4a65 ldr r2, [pc, #404] @ (8011424 ) 8011290: 693b ldr r3, [r7, #16] 8011292: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8011294: 693b ldr r3, [r7, #16] 8011296: f003 0301 and.w r3, r3, #1 801129a: 2b00 cmp r3, #0 801129c: d014 beq.n 80112c8 { /* Get Start Tick */ tickstart = HAL_GetTick(); 801129e: f7fc fd1b bl 800dcd8 80112a2: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80112a4: e00a b.n 80112bc { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80112a6: f7fc fd17 bl 800dcd8 80112aa: 4602 mov r2, r0 80112ac: 697b ldr r3, [r7, #20] 80112ae: 1ad3 subs r3, r2, r3 80112b0: f241 3288 movw r2, #5000 @ 0x1388 80112b4: 4293 cmp r3, r2 80112b6: d901 bls.n 80112bc { return HAL_TIMEOUT; 80112b8: 2303 movs r3, #3 80112ba: e0ae b.n 801141a while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80112bc: 4b59 ldr r3, [pc, #356] @ (8011424 ) 80112be: 6a1b ldr r3, [r3, #32] 80112c0: f003 0302 and.w r3, r3, #2 80112c4: 2b00 cmp r3, #0 80112c6: d0ee beq.n 80112a6 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80112c8: 4b56 ldr r3, [pc, #344] @ (8011424 ) 80112ca: 6a1b ldr r3, [r3, #32] 80112cc: f423 7240 bic.w r2, r3, #768 @ 0x300 80112d0: 687b ldr r3, [r7, #4] 80112d2: 685b ldr r3, [r3, #4] 80112d4: 4953 ldr r1, [pc, #332] @ (8011424 ) 80112d6: 4313 orrs r3, r2 80112d8: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 80112da: 7efb ldrb r3, [r7, #27] 80112dc: 2b01 cmp r3, #1 80112de: d105 bne.n 80112ec { __HAL_RCC_PWR_CLK_DISABLE(); 80112e0: 4b50 ldr r3, [pc, #320] @ (8011424 ) 80112e2: 69db ldr r3, [r3, #28] 80112e4: 4a4f ldr r2, [pc, #316] @ (8011424 ) 80112e6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80112ea: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 80112ec: 687b ldr r3, [r7, #4] 80112ee: 681b ldr r3, [r3, #0] 80112f0: f003 0302 and.w r3, r3, #2 80112f4: 2b00 cmp r3, #0 80112f6: d008 beq.n 801130a { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 80112f8: 4b4a ldr r3, [pc, #296] @ (8011424 ) 80112fa: 685b ldr r3, [r3, #4] 80112fc: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8011300: 687b ldr r3, [r7, #4] 8011302: 689b ldr r3, [r3, #8] 8011304: 4947 ldr r1, [pc, #284] @ (8011424 ) 8011306: 4313 orrs r3, r2 8011308: 604b str r3, [r1, #4] } #if defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ I2S2 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) 801130a: 687b ldr r3, [r7, #4] 801130c: 681b ldr r3, [r3, #0] 801130e: f003 0304 and.w r3, r3, #4 8011312: 2b00 cmp r3, #0 8011314: d008 beq.n 8011328 { /* Check the parameters */ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); /* Configure the I2S2 clock source */ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); 8011316: 4b43 ldr r3, [pc, #268] @ (8011424 ) 8011318: 6adb ldr r3, [r3, #44] @ 0x2c 801131a: f423 3200 bic.w r2, r3, #131072 @ 0x20000 801131e: 687b ldr r3, [r7, #4] 8011320: 68db ldr r3, [r3, #12] 8011322: 4940 ldr r1, [pc, #256] @ (8011424 ) 8011324: 4313 orrs r3, r2 8011326: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ I2S3 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) 8011328: 687b ldr r3, [r7, #4] 801132a: 681b ldr r3, [r3, #0] 801132c: f003 0308 and.w r3, r3, #8 8011330: 2b00 cmp r3, #0 8011332: d008 beq.n 8011346 { /* Check the parameters */ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); /* Configure the I2S3 clock source */ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); 8011334: 4b3b ldr r3, [pc, #236] @ (8011424 ) 8011336: 6adb ldr r3, [r3, #44] @ 0x2c 8011338: f423 2280 bic.w r2, r3, #262144 @ 0x40000 801133c: 687b ldr r3, [r7, #4] 801133e: 691b ldr r3, [r3, #16] 8011340: 4938 ldr r1, [pc, #224] @ (8011424 ) 8011342: 4313 orrs r3, r2 8011344: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ PLL I2S Configuration ----------------------*/ /* Check that PLLI2S need to be enabled */ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) 8011346: 4b37 ldr r3, [pc, #220] @ (8011424 ) 8011348: 6adb ldr r3, [r3, #44] @ 0x2c 801134a: f403 3300 and.w r3, r3, #131072 @ 0x20000 801134e: 2b00 cmp r3, #0 8011350: d105 bne.n 801135e 8011352: 4b34 ldr r3, [pc, #208] @ (8011424 ) 8011354: 6adb ldr r3, [r3, #44] @ 0x2c 8011356: f403 2380 and.w r3, r3, #262144 @ 0x40000 801135a: 2b00 cmp r3, #0 801135c: d001 beq.n 8011362 { /* Update flag to indicate that PLL I2S should be active */ pllactive = 1; 801135e: 2301 movs r3, #1 8011360: 61fb str r3, [r7, #28] } /* Check if PLL I2S need to be enabled */ if (pllactive == 1) 8011362: 69fb ldr r3, [r7, #28] 8011364: 2b01 cmp r3, #1 8011366: d148 bne.n 80113fa { /* Enable PLL I2S only if not active */ if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) 8011368: 4b2e ldr r3, [pc, #184] @ (8011424 ) 801136a: 681b ldr r3, [r3, #0] 801136c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011370: 2b00 cmp r3, #0 8011372: d138 bne.n 80113e6 assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); /* Prediv2 can be written only when the PLL2 is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 8011374: 4b2b ldr r3, [pc, #172] @ (8011424 ) 8011376: 681b ldr r3, [r3, #0] 8011378: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 801137c: 2b00 cmp r3, #0 801137e: d009 beq.n 8011394 (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) 8011380: 4b28 ldr r3, [pc, #160] @ (8011424 ) 8011382: 6adb ldr r3, [r3, #44] @ 0x2c 8011384: f003 02f0 and.w r2, r3, #240 @ 0xf0 8011388: 687b ldr r3, [r7, #4] 801138a: 699b ldr r3, [r3, #24] if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 801138c: 429a cmp r2, r3 801138e: d001 beq.n 8011394 { return HAL_ERROR; 8011390: 2301 movs r3, #1 8011392: e042 b.n 801141a } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); 8011394: 4b23 ldr r3, [pc, #140] @ (8011424 ) 8011396: 6adb ldr r3, [r3, #44] @ 0x2c 8011398: f023 02f0 bic.w r2, r3, #240 @ 0xf0 801139c: 687b ldr r3, [r7, #4] 801139e: 699b ldr r3, [r3, #24] 80113a0: 4920 ldr r1, [pc, #128] @ (8011424 ) 80113a2: 4313 orrs r3, r2 80113a4: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); 80113a6: 4b1f ldr r3, [pc, #124] @ (8011424 ) 80113a8: 6adb ldr r3, [r3, #44] @ 0x2c 80113aa: f423 4270 bic.w r2, r3, #61440 @ 0xf000 80113ae: 687b ldr r3, [r7, #4] 80113b0: 695b ldr r3, [r3, #20] 80113b2: 491c ldr r1, [pc, #112] @ (8011424 ) 80113b4: 4313 orrs r3, r2 80113b6: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); 80113b8: 4b1d ldr r3, [pc, #116] @ (8011430 ) 80113ba: 2201 movs r2, #1 80113bc: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80113be: f7fc fc8b bl 800dcd8 80113c2: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 80113c4: e008 b.n 80113d8 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 80113c6: f7fc fc87 bl 800dcd8 80113ca: 4602 mov r2, r0 80113cc: 697b ldr r3, [r7, #20] 80113ce: 1ad3 subs r3, r2, r3 80113d0: 2b64 cmp r3, #100 @ 0x64 80113d2: d901 bls.n 80113d8 { return HAL_TIMEOUT; 80113d4: 2303 movs r3, #3 80113d6: e020 b.n 801141a while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 80113d8: 4b12 ldr r3, [pc, #72] @ (8011424 ) 80113da: 681b ldr r3, [r3, #0] 80113dc: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80113e0: 2b00 cmp r3, #0 80113e2: d0f0 beq.n 80113c6 80113e4: e009 b.n 80113fa } } else { /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) 80113e6: 4b0f ldr r3, [pc, #60] @ (8011424 ) 80113e8: 6adb ldr r3, [r3, #44] @ 0x2c 80113ea: f403 4270 and.w r2, r3, #61440 @ 0xf000 80113ee: 687b ldr r3, [r7, #4] 80113f0: 695b ldr r3, [r3, #20] 80113f2: 429a cmp r2, r3 80113f4: d001 beq.n 80113fa { return HAL_ERROR; 80113f6: 2301 movs r3, #1 80113f8: e00f b.n 801141a #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 80113fa: 687b ldr r3, [r7, #4] 80113fc: 681b ldr r3, [r3, #0] 80113fe: f003 0310 and.w r3, r3, #16 8011402: 2b00 cmp r3, #0 8011404: d008 beq.n 8011418 { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8011406: 4b07 ldr r3, [pc, #28] @ (8011424 ) 8011408: 685b ldr r3, [r3, #4] 801140a: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 801140e: 687b ldr r3, [r7, #4] 8011410: 69db ldr r3, [r3, #28] 8011412: 4904 ldr r1, [pc, #16] @ (8011424 ) 8011414: 4313 orrs r3, r2 8011416: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 8011418: 2300 movs r3, #0 } 801141a: 4618 mov r0, r3 801141c: 3720 adds r7, #32 801141e: 46bd mov sp, r7 8011420: bd80 pop {r7, pc} 8011422: bf00 nop 8011424: 40021000 .word 0x40021000 8011428: 40007000 .word 0x40007000 801142c: 42420440 .word 0x42420440 8011430: 42420070 .word 0x42420070 08011434 : * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 8011434: b580 push {r7, lr} 8011436: b08a sub sp, #40 @ 0x28 8011438: af00 add r7, sp, #0 801143a: 6078 str r0, [r7, #4] #if defined(STM32F105xC) || defined(STM32F107xC) static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; 801143c: 2300 movs r3, #0 801143e: 61fb str r3, [r7, #28] 8011440: 2300 movs r3, #0 8011442: 627b str r3, [r7, #36] @ 0x24 8011444: 2300 movs r3, #0 8011446: 61bb str r3, [r7, #24] uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; 8011448: 2300 movs r3, #0 801144a: 617b str r3, [r7, #20] 801144c: 2300 movs r3, #0 801144e: 613b str r3, [r7, #16] 8011450: 2300 movs r3, #0 8011452: 60fb str r3, [r7, #12] static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; static const uint8_t aPredivFactorTable[2U] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 8011454: 2300 movs r3, #0 8011456: 60bb str r3, [r7, #8] 8011458: 2300 movs r3, #0 801145a: 623b str r3, [r7, #32] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 801145c: 687b ldr r3, [r7, #4] 801145e: 3b01 subs r3, #1 8011460: 2b0f cmp r3, #15 8011462: f200 811d bhi.w 80116a0 8011466: a201 add r2, pc, #4 @ (adr r2, 801146c ) 8011468: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801146c: 08011621 .word 0x08011621 8011470: 08011685 .word 0x08011685 8011474: 080116a1 .word 0x080116a1 8011478: 0801157f .word 0x0801157f 801147c: 080116a1 .word 0x080116a1 8011480: 080116a1 .word 0x080116a1 8011484: 080116a1 .word 0x080116a1 8011488: 080115d1 .word 0x080115d1 801148c: 080116a1 .word 0x080116a1 8011490: 080116a1 .word 0x080116a1 8011494: 080116a1 .word 0x080116a1 8011498: 080116a1 .word 0x080116a1 801149c: 080116a1 .word 0x080116a1 80114a0: 080116a1 .word 0x080116a1 80114a4: 080116a1 .word 0x080116a1 80114a8: 080114ad .word 0x080114ad || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_USB: { /* Get RCC configuration ------------------------------------------------------*/ temp_reg = RCC->CFGR; 80114ac: 4b83 ldr r3, [pc, #524] @ (80116bc ) 80114ae: 685b ldr r3, [r3, #4] 80114b0: 60bb str r3, [r7, #8] /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) 80114b2: 4b82 ldr r3, [pc, #520] @ (80116bc ) 80114b4: 681b ldr r3, [r3, #0] 80114b6: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80114ba: 2b00 cmp r3, #0 80114bc: f000 80f2 beq.w 80116a4 { pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 80114c0: 68bb ldr r3, [r7, #8] 80114c2: 0c9b lsrs r3, r3, #18 80114c4: f003 030f and.w r3, r3, #15 80114c8: 4a7d ldr r2, [pc, #500] @ (80116c0 ) 80114ca: 5cd3 ldrb r3, [r2, r3] 80114cc: 61bb str r3, [r7, #24] if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 80114ce: 68bb ldr r3, [r7, #8] 80114d0: f403 3380 and.w r3, r3, #65536 @ 0x10000 80114d4: 2b00 cmp r3, #0 80114d6: d03b beq.n 8011550 { #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ || defined(STM32F100xE) prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 80114d8: 4b78 ldr r3, [pc, #480] @ (80116bc ) 80114da: 6adb ldr r3, [r3, #44] @ 0x2c 80114dc: f003 030f and.w r3, r3, #15 80114e0: 4a78 ldr r2, [pc, #480] @ (80116c4 ) 80114e2: 5cd3 ldrb r3, [r2, r3] 80114e4: 61fb str r3, [r7, #28] #else prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 80114e6: 4b75 ldr r3, [pc, #468] @ (80116bc ) 80114e8: 6adb ldr r3, [r3, #44] @ 0x2c 80114ea: f403 3380 and.w r3, r3, #65536 @ 0x10000 80114ee: 2b00 cmp r3, #0 80114f0: d01c beq.n 801152c { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 80114f2: 4b72 ldr r3, [pc, #456] @ (80116bc ) 80114f4: 6adb ldr r3, [r3, #44] @ 0x2c 80114f6: 091b lsrs r3, r3, #4 80114f8: f003 030f and.w r3, r3, #15 80114fc: 3301 adds r3, #1 80114fe: 60fb str r3, [r7, #12] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 8011500: 4b6e ldr r3, [pc, #440] @ (80116bc ) 8011502: 6adb ldr r3, [r3, #44] @ 0x2c 8011504: 0a1b lsrs r3, r3, #8 8011506: f003 030f and.w r3, r3, #15 801150a: 3302 adds r3, #2 801150c: 617b str r3, [r7, #20] pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); 801150e: 4a6e ldr r2, [pc, #440] @ (80116c8 ) 8011510: 68fb ldr r3, [r7, #12] 8011512: fbb2 f3f3 udiv r3, r2, r3 8011516: 697a ldr r2, [r7, #20] 8011518: fb03 f202 mul.w r2, r3, r2 801151c: 69fb ldr r3, [r7, #28] 801151e: fbb2 f2f3 udiv r2, r2, r3 8011522: 69bb ldr r3, [r7, #24] 8011524: fb02 f303 mul.w r3, r2, r3 8011528: 627b str r3, [r7, #36] @ 0x24 801152a: e007 b.n 801153c } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); 801152c: 4a66 ldr r2, [pc, #408] @ (80116c8 ) 801152e: 69fb ldr r3, [r7, #28] 8011530: fbb2 f2f3 udiv r2, r2, r3 8011534: 69bb ldr r3, [r7, #24] 8011536: fb02 f303 mul.w r3, r2, r3 801153a: 627b str r3, [r7, #36] @ 0x24 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 801153c: 4b60 ldr r3, [pc, #384] @ (80116c0 ) 801153e: 7b5b ldrb r3, [r3, #13] 8011540: 461a mov r2, r3 8011542: 69bb ldr r3, [r7, #24] 8011544: 4293 cmp r3, r2 8011546: d108 bne.n 801155a { pllclk = pllclk / 2; 8011548: 6a7b ldr r3, [r7, #36] @ 0x24 801154a: 085b lsrs r3, r3, #1 801154c: 627b str r3, [r7, #36] @ 0x24 801154e: e004 b.n 801155a #endif /* STM32F105xC || STM32F107xC */ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8011550: 69bb ldr r3, [r7, #24] 8011552: 4a5e ldr r2, [pc, #376] @ (80116cc ) 8011554: fb02 f303 mul.w r3, r2, r3 8011558: 627b str r3, [r7, #36] @ 0x24 } /* Calcul of the USB frequency*/ #if defined(STM32F105xC) || defined(STM32F107xC) /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) 801155a: 4b58 ldr r3, [pc, #352] @ (80116bc ) 801155c: 685b ldr r3, [r3, #4] 801155e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8011562: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8011566: d102 bne.n 801156e { /* Prescaler of 2 selected for USB */ frequency = pllclk; 8011568: 6a7b ldr r3, [r7, #36] @ 0x24 801156a: 623b str r3, [r7, #32] /* Prescaler of 1.5 selected for USB */ frequency = (pllclk * 2) / 3; } #endif } break; 801156c: e09a b.n 80116a4 frequency = (2 * pllclk) / 3; 801156e: 6a7b ldr r3, [r7, #36] @ 0x24 8011570: 005b lsls r3, r3, #1 8011572: 4a57 ldr r2, [pc, #348] @ (80116d0 ) 8011574: fba2 2303 umull r2, r3, r2, r3 8011578: 085b lsrs r3, r3, #1 801157a: 623b str r3, [r7, #32] break; 801157c: e092 b.n 80116a4 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) 801157e: 4b4f ldr r3, [pc, #316] @ (80116bc ) 8011580: 6adb ldr r3, [r3, #44] @ 0x2c 8011582: f403 3300 and.w r3, r3, #131072 @ 0x20000 8011586: 2b00 cmp r3, #0 8011588: d103 bne.n 8011592 { /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); 801158a: f7ff fd15 bl 8010fb8 801158e: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8011590: e08a b.n 80116a8 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8011592: 4b4a ldr r3, [pc, #296] @ (80116bc ) 8011594: 681b ldr r3, [r3, #0] 8011596: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 801159a: 2b00 cmp r3, #0 801159c: f000 8084 beq.w 80116a8 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 80115a0: 4b46 ldr r3, [pc, #280] @ (80116bc ) 80115a2: 6adb ldr r3, [r3, #44] @ 0x2c 80115a4: 091b lsrs r3, r3, #4 80115a6: f003 030f and.w r3, r3, #15 80115aa: 3301 adds r3, #1 80115ac: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 80115ae: 4b43 ldr r3, [pc, #268] @ (80116bc ) 80115b0: 6adb ldr r3, [r3, #44] @ 0x2c 80115b2: 0b1b lsrs r3, r3, #12 80115b4: f003 030f and.w r3, r3, #15 80115b8: 3302 adds r3, #2 80115ba: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 80115bc: 4a42 ldr r2, [pc, #264] @ (80116c8 ) 80115be: 68fb ldr r3, [r7, #12] 80115c0: fbb2 f3f3 udiv r3, r2, r3 80115c4: 693a ldr r2, [r7, #16] 80115c6: fb02 f303 mul.w r3, r2, r3 80115ca: 005b lsls r3, r3, #1 80115cc: 623b str r3, [r7, #32] break; 80115ce: e06b b.n 80116a8 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) 80115d0: 4b3a ldr r3, [pc, #232] @ (80116bc ) 80115d2: 6adb ldr r3, [r3, #44] @ 0x2c 80115d4: f403 2380 and.w r3, r3, #262144 @ 0x40000 80115d8: 2b00 cmp r3, #0 80115da: d103 bne.n 80115e4 { /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); 80115dc: f7ff fcec bl 8010fb8 80115e0: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 80115e2: e063 b.n 80116ac if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 80115e4: 4b35 ldr r3, [pc, #212] @ (80116bc ) 80115e6: 681b ldr r3, [r3, #0] 80115e8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80115ec: 2b00 cmp r3, #0 80115ee: d05d beq.n 80116ac prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 80115f0: 4b32 ldr r3, [pc, #200] @ (80116bc ) 80115f2: 6adb ldr r3, [r3, #44] @ 0x2c 80115f4: 091b lsrs r3, r3, #4 80115f6: f003 030f and.w r3, r3, #15 80115fa: 3301 adds r3, #1 80115fc: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 80115fe: 4b2f ldr r3, [pc, #188] @ (80116bc ) 8011600: 6adb ldr r3, [r3, #44] @ 0x2c 8011602: 0b1b lsrs r3, r3, #12 8011604: f003 030f and.w r3, r3, #15 8011608: 3302 adds r3, #2 801160a: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 801160c: 4a2e ldr r2, [pc, #184] @ (80116c8 ) 801160e: 68fb ldr r3, [r7, #12] 8011610: fbb2 f3f3 udiv r3, r2, r3 8011614: 693a ldr r2, [r7, #16] 8011616: fb02 f303 mul.w r3, r2, r3 801161a: 005b lsls r3, r3, #1 801161c: 623b str r3, [r7, #32] break; 801161e: e045 b.n 80116ac } #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ case RCC_PERIPHCLK_RTC: { /* Get RCC BDCR configuration ------------------------------------------------------*/ temp_reg = RCC->BDCR; 8011620: 4b26 ldr r3, [pc, #152] @ (80116bc ) 8011622: 6a1b ldr r3, [r3, #32] 8011624: 60bb str r3, [r7, #8] /* Check if LSE is ready if RTC clock selection is LSE */ if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 8011626: 68bb ldr r3, [r7, #8] 8011628: f403 7340 and.w r3, r3, #768 @ 0x300 801162c: f5b3 7f80 cmp.w r3, #256 @ 0x100 8011630: d108 bne.n 8011644 8011632: 68bb ldr r3, [r7, #8] 8011634: f003 0302 and.w r3, r3, #2 8011638: 2b00 cmp r3, #0 801163a: d003 beq.n 8011644 { frequency = LSE_VALUE; 801163c: f44f 4300 mov.w r3, #32768 @ 0x8000 8011640: 623b str r3, [r7, #32] 8011642: e01e b.n 8011682 } /* Check if LSI is ready if RTC clock selection is LSI */ else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 8011644: 68bb ldr r3, [r7, #8] 8011646: f403 7340 and.w r3, r3, #768 @ 0x300 801164a: f5b3 7f00 cmp.w r3, #512 @ 0x200 801164e: d109 bne.n 8011664 8011650: 4b1a ldr r3, [pc, #104] @ (80116bc ) 8011652: 6a5b ldr r3, [r3, #36] @ 0x24 8011654: f003 0302 and.w r3, r3, #2 8011658: 2b00 cmp r3, #0 801165a: d003 beq.n 8011664 { frequency = LSI_VALUE; 801165c: f649 4340 movw r3, #40000 @ 0x9c40 8011660: 623b str r3, [r7, #32] 8011662: e00e b.n 8011682 } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 8011664: 68bb ldr r3, [r7, #8] 8011666: f403 7340 and.w r3, r3, #768 @ 0x300 801166a: f5b3 7f40 cmp.w r3, #768 @ 0x300 801166e: d11f bne.n 80116b0 8011670: 4b12 ldr r3, [pc, #72] @ (80116bc ) 8011672: 681b ldr r3, [r3, #0] 8011674: f403 3300 and.w r3, r3, #131072 @ 0x20000 8011678: 2b00 cmp r3, #0 801167a: d019 beq.n 80116b0 { frequency = HSE_VALUE / 128U; 801167c: 4b15 ldr r3, [pc, #84] @ (80116d4 ) 801167e: 623b str r3, [r7, #32] /* Clock not enabled for RTC*/ else { /* nothing to do: frequency already initialized to 0U */ } break; 8011680: e016 b.n 80116b0 8011682: e015 b.n 80116b0 } case RCC_PERIPHCLK_ADC: { frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 8011684: f7ff fd72 bl 801116c 8011688: 4602 mov r2, r0 801168a: 4b0c ldr r3, [pc, #48] @ (80116bc ) 801168c: 685b ldr r3, [r3, #4] 801168e: 0b9b lsrs r3, r3, #14 8011690: f003 0303 and.w r3, r3, #3 8011694: 3301 adds r3, #1 8011696: 005b lsls r3, r3, #1 8011698: fbb2 f3f3 udiv r3, r2, r3 801169c: 623b str r3, [r7, #32] break; 801169e: e008 b.n 80116b2 } default: { break; 80116a0: bf00 nop 80116a2: e006 b.n 80116b2 break; 80116a4: bf00 nop 80116a6: e004 b.n 80116b2 break; 80116a8: bf00 nop 80116aa: e002 b.n 80116b2 break; 80116ac: bf00 nop 80116ae: e000 b.n 80116b2 break; 80116b0: bf00 nop } } return (frequency); 80116b2: 6a3b ldr r3, [r7, #32] } 80116b4: 4618 mov r0, r3 80116b6: 3728 adds r7, #40 @ 0x28 80116b8: 46bd mov sp, r7 80116ba: bd80 pop {r7, pc} 80116bc: 40021000 .word 0x40021000 80116c0: 08016ebc .word 0x08016ebc 80116c4: 08016ecc .word 0x08016ecc 80116c8: 017d7840 .word 0x017d7840 80116cc: 003d0900 .word 0x003d0900 80116d0: aaaaaaab .word 0xaaaaaaab 80116d4: 0002faf0 .word 0x0002faf0 080116d8 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { 80116d8: b580 push {r7, lr} 80116da: b084 sub sp, #16 80116dc: af00 add r7, sp, #0 80116de: 6078 str r0, [r7, #4] uint32_t prescaler = 0U; 80116e0: 2300 movs r3, #0 80116e2: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 80116e4: 687b ldr r3, [r7, #4] 80116e6: 2b00 cmp r3, #0 80116e8: d101 bne.n 80116ee { return HAL_ERROR; 80116ea: 2301 movs r3, #1 80116ec: e07a b.n 80117e4 { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else if (hrtc->State == HAL_RTC_STATE_RESET) 80116ee: 687b ldr r3, [r7, #4] 80116f0: 7c5b ldrb r3, [r3, #17] 80116f2: b2db uxtb r3, r3 80116f4: 2b00 cmp r3, #0 80116f6: d105 bne.n 8011704 { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; 80116f8: 687b ldr r3, [r7, #4] 80116fa: 2200 movs r2, #0 80116fc: 741a strb r2, [r3, #16] /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); 80116fe: 6878 ldr r0, [r7, #4] 8011700: f7fa f8ae bl 800b860 } #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; 8011704: 687b ldr r3, [r7, #4] 8011706: 2202 movs r2, #2 8011708: 745a strb r2, [r3, #17] /* Waiting for synchro */ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 801170a: 6878 ldr r0, [r7, #4] 801170c: f000 f870 bl 80117f0 8011710: 4603 mov r3, r0 8011712: 2b00 cmp r3, #0 8011714: d004 beq.n 8011720 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8011716: 687b ldr r3, [r7, #4] 8011718: 2204 movs r2, #4 801171a: 745a strb r2, [r3, #17] return HAL_ERROR; 801171c: 2301 movs r3, #1 801171e: e061 b.n 80117e4 } /* Set Initialization mode */ if (RTC_EnterInitMode(hrtc) != HAL_OK) 8011720: 6878 ldr r0, [r7, #4] 8011722: f000 f892 bl 801184a 8011726: 4603 mov r3, r0 8011728: 2b00 cmp r3, #0 801172a: d004 beq.n 8011736 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 801172c: 687b ldr r3, [r7, #4] 801172e: 2204 movs r2, #4 8011730: 745a strb r2, [r3, #17] return HAL_ERROR; 8011732: 2301 movs r3, #1 8011734: e056 b.n 80117e4 } else { /* Clear Flags Bits */ CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); 8011736: 687b ldr r3, [r7, #4] 8011738: 681b ldr r3, [r3, #0] 801173a: 685a ldr r2, [r3, #4] 801173c: 687b ldr r3, [r7, #4] 801173e: 681b ldr r3, [r3, #0] 8011740: f022 0207 bic.w r2, r2, #7 8011744: 605a str r2, [r3, #4] if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) 8011746: 687b ldr r3, [r7, #4] 8011748: 689b ldr r3, [r3, #8] 801174a: 2b00 cmp r3, #0 801174c: d005 beq.n 801175a { /* Disable the selected Tamper pin */ CLEAR_BIT(BKP->CR, BKP_CR_TPE); 801174e: 4b27 ldr r3, [pc, #156] @ (80117ec ) 8011750: 6b1b ldr r3, [r3, #48] @ 0x30 8011752: 4a26 ldr r2, [pc, #152] @ (80117ec ) 8011754: f023 0301 bic.w r3, r3, #1 8011758: 6313 str r3, [r2, #48] @ 0x30 } /* Set the signal which will be routed to RTC Tamper pin*/ MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); 801175a: 4b24 ldr r3, [pc, #144] @ (80117ec ) 801175c: 6adb ldr r3, [r3, #44] @ 0x2c 801175e: f423 7260 bic.w r2, r3, #896 @ 0x380 8011762: 687b ldr r3, [r7, #4] 8011764: 689b ldr r3, [r3, #8] 8011766: 4921 ldr r1, [pc, #132] @ (80117ec ) 8011768: 4313 orrs r3, r2 801176a: 62cb str r3, [r1, #44] @ 0x2c if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) 801176c: 687b ldr r3, [r7, #4] 801176e: 685b ldr r3, [r3, #4] 8011770: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8011774: d003 beq.n 801177e { /* RTC Prescaler provided directly by end-user*/ prescaler = hrtc->Init.AsynchPrediv; 8011776: 687b ldr r3, [r7, #4] 8011778: 685b ldr r3, [r3, #4] 801177a: 60fb str r3, [r7, #12] 801177c: e00e b.n 801179c } else { /* RTC Prescaler will be automatically calculated to get 1 second timebase */ /* Get the RTCCLK frequency */ prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); 801177e: 2001 movs r0, #1 8011780: f7ff fe58 bl 8011434 8011784: 60f8 str r0, [r7, #12] /* Check that RTC clock is enabled*/ if (prescaler == 0U) 8011786: 68fb ldr r3, [r7, #12] 8011788: 2b00 cmp r3, #0 801178a: d104 bne.n 8011796 { /* Should not happen. Frequency is not available*/ hrtc->State = HAL_RTC_STATE_ERROR; 801178c: 687b ldr r3, [r7, #4] 801178e: 2204 movs r2, #4 8011790: 745a strb r2, [r3, #17] return HAL_ERROR; 8011792: 2301 movs r3, #1 8011794: e026 b.n 80117e4 } else { /* RTC period = RTCCLK/(RTC_PR + 1) */ prescaler = prescaler - 1U; 8011796: 68fb ldr r3, [r7, #12] 8011798: 3b01 subs r3, #1 801179a: 60fb str r3, [r7, #12] } } /* Configure the RTC_PRLH / RTC_PRLL */ WRITE_REG(hrtc->Instance->PRLH, ((prescaler >> 16U) & RTC_PRLH_PRL)); 801179c: 68fb ldr r3, [r7, #12] 801179e: 0c1a lsrs r2, r3, #16 80117a0: 687b ldr r3, [r7, #4] 80117a2: 681b ldr r3, [r3, #0] 80117a4: f002 020f and.w r2, r2, #15 80117a8: 609a str r2, [r3, #8] WRITE_REG(hrtc->Instance->PRLL, (prescaler & RTC_PRLL_PRL)); 80117aa: 687b ldr r3, [r7, #4] 80117ac: 681b ldr r3, [r3, #0] 80117ae: 68fa ldr r2, [r7, #12] 80117b0: b292 uxth r2, r2 80117b2: 60da str r2, [r3, #12] /* Wait for synchro */ if (RTC_ExitInitMode(hrtc) != HAL_OK) 80117b4: 6878 ldr r0, [r7, #4] 80117b6: f000 f870 bl 801189a 80117ba: 4603 mov r3, r0 80117bc: 2b00 cmp r3, #0 80117be: d004 beq.n 80117ca { hrtc->State = HAL_RTC_STATE_ERROR; 80117c0: 687b ldr r3, [r7, #4] 80117c2: 2204 movs r2, #4 80117c4: 745a strb r2, [r3, #17] return HAL_ERROR; 80117c6: 2301 movs r3, #1 80117c8: e00c b.n 80117e4 } /* Initialize date to 1st of January 2000 */ hrtc->DateToUpdate.Year = 0x00U; 80117ca: 687b ldr r3, [r7, #4] 80117cc: 2200 movs r2, #0 80117ce: 73da strb r2, [r3, #15] hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; 80117d0: 687b ldr r3, [r7, #4] 80117d2: 2201 movs r2, #1 80117d4: 735a strb r2, [r3, #13] hrtc->DateToUpdate.Date = 0x01U; 80117d6: 687b ldr r3, [r7, #4] 80117d8: 2201 movs r2, #1 80117da: 739a strb r2, [r3, #14] /* Set RTC state */ hrtc->State = HAL_RTC_STATE_READY; 80117dc: 687b ldr r3, [r7, #4] 80117de: 2201 movs r2, #1 80117e0: 745a strb r2, [r3, #17] return HAL_OK; 80117e2: 2300 movs r3, #0 } } 80117e4: 4618 mov r0, r3 80117e6: 3710 adds r7, #16 80117e8: 46bd mov sp, r7 80117ea: bd80 pop {r7, pc} 80117ec: 40006c00 .word 0x40006c00 080117f0 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { 80117f0: b580 push {r7, lr} 80117f2: b084 sub sp, #16 80117f4: af00 add r7, sp, #0 80117f6: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80117f8: 2300 movs r3, #0 80117fa: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 80117fc: 687b ldr r3, [r7, #4] 80117fe: 2b00 cmp r3, #0 8011800: d101 bne.n 8011806 { return HAL_ERROR; 8011802: 2301 movs r3, #1 8011804: e01d b.n 8011842 } /* Clear RSF flag */ CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); 8011806: 687b ldr r3, [r7, #4] 8011808: 681b ldr r3, [r3, #0] 801180a: 685a ldr r2, [r3, #4] 801180c: 687b ldr r3, [r7, #4] 801180e: 681b ldr r3, [r3, #0] 8011810: f022 0208 bic.w r2, r2, #8 8011814: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8011816: f7fc fa5f bl 800dcd8 801181a: 60f8 str r0, [r7, #12] /* Wait the registers to be synchronised */ while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 801181c: e009 b.n 8011832 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 801181e: f7fc fa5b bl 800dcd8 8011822: 4602 mov r2, r0 8011824: 68fb ldr r3, [r7, #12] 8011826: 1ad3 subs r3, r2, r3 8011828: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 801182c: d901 bls.n 8011832 { return HAL_TIMEOUT; 801182e: 2303 movs r3, #3 8011830: e007 b.n 8011842 while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8011832: 687b ldr r3, [r7, #4] 8011834: 681b ldr r3, [r3, #0] 8011836: 685b ldr r3, [r3, #4] 8011838: f003 0308 and.w r3, r3, #8 801183c: 2b00 cmp r3, #0 801183e: d0ee beq.n 801181e } } return HAL_OK; 8011840: 2300 movs r3, #0 } 8011842: 4618 mov r0, r3 8011844: 3710 adds r7, #16 8011846: 46bd mov sp, r7 8011848: bd80 pop {r7, pc} 0801184a : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { 801184a: b580 push {r7, lr} 801184c: b084 sub sp, #16 801184e: af00 add r7, sp, #0 8011850: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8011852: 2300 movs r3, #0 8011854: 60fb str r3, [r7, #12] tickstart = HAL_GetTick(); 8011856: f7fc fa3f bl 800dcd8 801185a: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 801185c: e009 b.n 8011872 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 801185e: f7fc fa3b bl 800dcd8 8011862: 4602 mov r2, r0 8011864: 68fb ldr r3, [r7, #12] 8011866: 1ad3 subs r3, r2, r3 8011868: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 801186c: d901 bls.n 8011872 { return HAL_TIMEOUT; 801186e: 2303 movs r3, #3 8011870: e00f b.n 8011892 while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8011872: 687b ldr r3, [r7, #4] 8011874: 681b ldr r3, [r3, #0] 8011876: 685b ldr r3, [r3, #4] 8011878: f003 0320 and.w r3, r3, #32 801187c: 2b00 cmp r3, #0 801187e: d0ee beq.n 801185e } } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 8011880: 687b ldr r3, [r7, #4] 8011882: 681b ldr r3, [r3, #0] 8011884: 685a ldr r2, [r3, #4] 8011886: 687b ldr r3, [r7, #4] 8011888: 681b ldr r3, [r3, #0] 801188a: f042 0210 orr.w r2, r2, #16 801188e: 605a str r2, [r3, #4] return HAL_OK; 8011890: 2300 movs r3, #0 } 8011892: 4618 mov r0, r3 8011894: 3710 adds r7, #16 8011896: 46bd mov sp, r7 8011898: bd80 pop {r7, pc} 0801189a : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) { 801189a: b580 push {r7, lr} 801189c: b084 sub sp, #16 801189e: af00 add r7, sp, #0 80118a0: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80118a2: 2300 movs r3, #0 80118a4: 60fb str r3, [r7, #12] /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 80118a6: 687b ldr r3, [r7, #4] 80118a8: 681b ldr r3, [r3, #0] 80118aa: 685a ldr r2, [r3, #4] 80118ac: 687b ldr r3, [r7, #4] 80118ae: 681b ldr r3, [r3, #0] 80118b0: f022 0210 bic.w r2, r2, #16 80118b4: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 80118b6: f7fc fa0f bl 800dcd8 80118ba: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 80118bc: e009 b.n 80118d2 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 80118be: f7fc fa0b bl 800dcd8 80118c2: 4602 mov r2, r0 80118c4: 68fb ldr r3, [r7, #12] 80118c6: 1ad3 subs r3, r2, r3 80118c8: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 80118cc: d901 bls.n 80118d2 { return HAL_TIMEOUT; 80118ce: 2303 movs r3, #3 80118d0: e007 b.n 80118e2 while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 80118d2: 687b ldr r3, [r7, #4] 80118d4: 681b ldr r3, [r3, #0] 80118d6: 685b ldr r3, [r3, #4] 80118d8: f003 0320 and.w r3, r3, #32 80118dc: 2b00 cmp r3, #0 80118de: d0ee beq.n 80118be } } return HAL_OK; 80118e0: 2300 movs r3, #0 } 80118e2: 4618 mov r0, r3 80118e4: 3710 adds r7, #16 80118e6: 46bd mov sp, r7 80118e8: bd80 pop {r7, pc} 080118ea : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 80118ea: b580 push {r7, lr} 80118ec: b082 sub sp, #8 80118ee: af00 add r7, sp, #0 80118f0: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 80118f2: 687b ldr r3, [r7, #4] 80118f4: 2b00 cmp r3, #0 80118f6: d101 bne.n 80118fc { return HAL_ERROR; 80118f8: 2301 movs r3, #1 80118fa: e041 b.n 8011980 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 80118fc: 687b ldr r3, [r7, #4] 80118fe: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8011902: b2db uxtb r3, r3 8011904: 2b00 cmp r3, #0 8011906: d106 bne.n 8011916 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8011908: 687b ldr r3, [r7, #4] 801190a: 2200 movs r2, #0 801190c: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8011910: 6878 ldr r0, [r7, #4] 8011912: f7fb fe67 bl 800d5e4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8011916: 687b ldr r3, [r7, #4] 8011918: 2202 movs r2, #2 801191a: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 801191e: 687b ldr r3, [r7, #4] 8011920: 681a ldr r2, [r3, #0] 8011922: 687b ldr r3, [r7, #4] 8011924: 3304 adds r3, #4 8011926: 4619 mov r1, r3 8011928: 4610 mov r0, r2 801192a: f000 fd33 bl 8012394 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 801192e: 687b ldr r3, [r7, #4] 8011930: 2201 movs r2, #1 8011932: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011936: 687b ldr r3, [r7, #4] 8011938: 2201 movs r2, #1 801193a: f883 203e strb.w r2, [r3, #62] @ 0x3e 801193e: 687b ldr r3, [r7, #4] 8011940: 2201 movs r2, #1 8011942: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011946: 687b ldr r3, [r7, #4] 8011948: 2201 movs r2, #1 801194a: f883 2040 strb.w r2, [r3, #64] @ 0x40 801194e: 687b ldr r3, [r7, #4] 8011950: 2201 movs r2, #1 8011952: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011956: 687b ldr r3, [r7, #4] 8011958: 2201 movs r2, #1 801195a: f883 2042 strb.w r2, [r3, #66] @ 0x42 801195e: 687b ldr r3, [r7, #4] 8011960: 2201 movs r2, #1 8011962: f883 2043 strb.w r2, [r3, #67] @ 0x43 8011966: 687b ldr r3, [r7, #4] 8011968: 2201 movs r2, #1 801196a: f883 2044 strb.w r2, [r3, #68] @ 0x44 801196e: 687b ldr r3, [r7, #4] 8011970: 2201 movs r2, #1 8011972: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8011976: 687b ldr r3, [r7, #4] 8011978: 2201 movs r2, #1 801197a: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 801197e: 2300 movs r3, #0 } 8011980: 4618 mov r0, r3 8011982: 3708 adds r7, #8 8011984: 46bd mov sp, r7 8011986: bd80 pop {r7, pc} 08011988 : * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { 8011988: b580 push {r7, lr} 801198a: b082 sub sp, #8 801198c: af00 add r7, sp, #0 801198e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8011990: 687b ldr r3, [r7, #4] 8011992: 2b00 cmp r3, #0 8011994: d101 bne.n 801199a { return HAL_ERROR; 8011996: 2301 movs r3, #1 8011998: e041 b.n 8011a1e assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 801199a: 687b ldr r3, [r7, #4] 801199c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 80119a0: b2db uxtb r3, r3 80119a2: 2b00 cmp r3, #0 80119a4: d106 bne.n 80119b4 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 80119a6: 687b ldr r3, [r7, #4] 80119a8: 2200 movs r2, #0 80119aa: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); 80119ae: 6878 ldr r0, [r7, #4] 80119b0: f000 f839 bl 8011a26 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80119b4: 687b ldr r3, [r7, #4] 80119b6: 2202 movs r2, #2 80119b8: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 80119bc: 687b ldr r3, [r7, #4] 80119be: 681a ldr r2, [r3, #0] 80119c0: 687b ldr r3, [r7, #4] 80119c2: 3304 adds r3, #4 80119c4: 4619 mov r1, r3 80119c6: 4610 mov r0, r2 80119c8: f000 fce4 bl 8012394 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 80119cc: 687b ldr r3, [r7, #4] 80119ce: 2201 movs r2, #1 80119d0: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80119d4: 687b ldr r3, [r7, #4] 80119d6: 2201 movs r2, #1 80119d8: f883 203e strb.w r2, [r3, #62] @ 0x3e 80119dc: 687b ldr r3, [r7, #4] 80119de: 2201 movs r2, #1 80119e0: f883 203f strb.w r2, [r3, #63] @ 0x3f 80119e4: 687b ldr r3, [r7, #4] 80119e6: 2201 movs r2, #1 80119e8: f883 2040 strb.w r2, [r3, #64] @ 0x40 80119ec: 687b ldr r3, [r7, #4] 80119ee: 2201 movs r2, #1 80119f0: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80119f4: 687b ldr r3, [r7, #4] 80119f6: 2201 movs r2, #1 80119f8: f883 2042 strb.w r2, [r3, #66] @ 0x42 80119fc: 687b ldr r3, [r7, #4] 80119fe: 2201 movs r2, #1 8011a00: f883 2043 strb.w r2, [r3, #67] @ 0x43 8011a04: 687b ldr r3, [r7, #4] 8011a06: 2201 movs r2, #1 8011a08: f883 2044 strb.w r2, [r3, #68] @ 0x44 8011a0c: 687b ldr r3, [r7, #4] 8011a0e: 2201 movs r2, #1 8011a10: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8011a14: 687b ldr r3, [r7, #4] 8011a16: 2201 movs r2, #1 8011a18: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8011a1c: 2300 movs r3, #0 } 8011a1e: 4618 mov r0, r3 8011a20: 3708 adds r7, #8 8011a22: 46bd mov sp, r7 8011a24: bd80 pop {r7, pc} 08011a26 : * @brief Initializes the TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) { 8011a26: b480 push {r7} 8011a28: b083 sub sp, #12 8011a2a: af00 add r7, sp, #0 8011a2c: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspInit could be implemented in the user file */ } 8011a2e: bf00 nop 8011a30: 370c adds r7, #12 8011a32: 46bd mov sp, r7 8011a34: bc80 pop {r7} 8011a36: 4770 bx lr 08011a38 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8011a38: b580 push {r7, lr} 8011a3a: b084 sub sp, #16 8011a3c: af00 add r7, sp, #0 8011a3e: 6078 str r0, [r7, #4] 8011a40: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 8011a42: 683b ldr r3, [r7, #0] 8011a44: 2b00 cmp r3, #0 8011a46: d109 bne.n 8011a5c 8011a48: 687b ldr r3, [r7, #4] 8011a4a: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8011a4e: b2db uxtb r3, r3 8011a50: 2b01 cmp r3, #1 8011a52: bf14 ite ne 8011a54: 2301 movne r3, #1 8011a56: 2300 moveq r3, #0 8011a58: b2db uxtb r3, r3 8011a5a: e022 b.n 8011aa2 8011a5c: 683b ldr r3, [r7, #0] 8011a5e: 2b04 cmp r3, #4 8011a60: d109 bne.n 8011a76 8011a62: 687b ldr r3, [r7, #4] 8011a64: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8011a68: b2db uxtb r3, r3 8011a6a: 2b01 cmp r3, #1 8011a6c: bf14 ite ne 8011a6e: 2301 movne r3, #1 8011a70: 2300 moveq r3, #0 8011a72: b2db uxtb r3, r3 8011a74: e015 b.n 8011aa2 8011a76: 683b ldr r3, [r7, #0] 8011a78: 2b08 cmp r3, #8 8011a7a: d109 bne.n 8011a90 8011a7c: 687b ldr r3, [r7, #4] 8011a7e: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8011a82: b2db uxtb r3, r3 8011a84: 2b01 cmp r3, #1 8011a86: bf14 ite ne 8011a88: 2301 movne r3, #1 8011a8a: 2300 moveq r3, #0 8011a8c: b2db uxtb r3, r3 8011a8e: e008 b.n 8011aa2 8011a90: 687b ldr r3, [r7, #4] 8011a92: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011a96: b2db uxtb r3, r3 8011a98: 2b01 cmp r3, #1 8011a9a: bf14 ite ne 8011a9c: 2301 movne r3, #1 8011a9e: 2300 moveq r3, #0 8011aa0: b2db uxtb r3, r3 8011aa2: 2b00 cmp r3, #0 8011aa4: d001 beq.n 8011aaa { return HAL_ERROR; 8011aa6: 2301 movs r3, #1 8011aa8: e063 b.n 8011b72 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8011aaa: 683b ldr r3, [r7, #0] 8011aac: 2b00 cmp r3, #0 8011aae: d104 bne.n 8011aba 8011ab0: 687b ldr r3, [r7, #4] 8011ab2: 2202 movs r2, #2 8011ab4: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011ab8: e013 b.n 8011ae2 8011aba: 683b ldr r3, [r7, #0] 8011abc: 2b04 cmp r3, #4 8011abe: d104 bne.n 8011aca 8011ac0: 687b ldr r3, [r7, #4] 8011ac2: 2202 movs r2, #2 8011ac4: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011ac8: e00b b.n 8011ae2 8011aca: 683b ldr r3, [r7, #0] 8011acc: 2b08 cmp r3, #8 8011ace: d104 bne.n 8011ada 8011ad0: 687b ldr r3, [r7, #4] 8011ad2: 2202 movs r2, #2 8011ad4: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011ad8: e003 b.n 8011ae2 8011ada: 687b ldr r3, [r7, #4] 8011adc: 2202 movs r2, #2 8011ade: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 8011ae2: 687b ldr r3, [r7, #4] 8011ae4: 681b ldr r3, [r3, #0] 8011ae6: 2201 movs r2, #1 8011ae8: 6839 ldr r1, [r7, #0] 8011aea: 4618 mov r0, r3 8011aec: f000 fee8 bl 80128c0 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8011af0: 687b ldr r3, [r7, #4] 8011af2: 681b ldr r3, [r3, #0] 8011af4: 4a21 ldr r2, [pc, #132] @ (8011b7c ) 8011af6: 4293 cmp r3, r2 8011af8: d107 bne.n 8011b0a { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8011afa: 687b ldr r3, [r7, #4] 8011afc: 681b ldr r3, [r3, #0] 8011afe: 6c5a ldr r2, [r3, #68] @ 0x44 8011b00: 687b ldr r3, [r7, #4] 8011b02: 681b ldr r3, [r3, #0] 8011b04: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8011b08: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8011b0a: 687b ldr r3, [r7, #4] 8011b0c: 681b ldr r3, [r3, #0] 8011b0e: 4a1b ldr r2, [pc, #108] @ (8011b7c ) 8011b10: 4293 cmp r3, r2 8011b12: d013 beq.n 8011b3c 8011b14: 687b ldr r3, [r7, #4] 8011b16: 681b ldr r3, [r3, #0] 8011b18: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8011b1c: d00e beq.n 8011b3c 8011b1e: 687b ldr r3, [r7, #4] 8011b20: 681b ldr r3, [r3, #0] 8011b22: 4a17 ldr r2, [pc, #92] @ (8011b80 ) 8011b24: 4293 cmp r3, r2 8011b26: d009 beq.n 8011b3c 8011b28: 687b ldr r3, [r7, #4] 8011b2a: 681b ldr r3, [r3, #0] 8011b2c: 4a15 ldr r2, [pc, #84] @ (8011b84 ) 8011b2e: 4293 cmp r3, r2 8011b30: d004 beq.n 8011b3c 8011b32: 687b ldr r3, [r7, #4] 8011b34: 681b ldr r3, [r3, #0] 8011b36: 4a14 ldr r2, [pc, #80] @ (8011b88 ) 8011b38: 4293 cmp r3, r2 8011b3a: d111 bne.n 8011b60 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8011b3c: 687b ldr r3, [r7, #4] 8011b3e: 681b ldr r3, [r3, #0] 8011b40: 689b ldr r3, [r3, #8] 8011b42: f003 0307 and.w r3, r3, #7 8011b46: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8011b48: 68fb ldr r3, [r7, #12] 8011b4a: 2b06 cmp r3, #6 8011b4c: d010 beq.n 8011b70 { __HAL_TIM_ENABLE(htim); 8011b4e: 687b ldr r3, [r7, #4] 8011b50: 681b ldr r3, [r3, #0] 8011b52: 681a ldr r2, [r3, #0] 8011b54: 687b ldr r3, [r7, #4] 8011b56: 681b ldr r3, [r3, #0] 8011b58: f042 0201 orr.w r2, r2, #1 8011b5c: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8011b5e: e007 b.n 8011b70 } } else { __HAL_TIM_ENABLE(htim); 8011b60: 687b ldr r3, [r7, #4] 8011b62: 681b ldr r3, [r3, #0] 8011b64: 681a ldr r2, [r3, #0] 8011b66: 687b ldr r3, [r7, #4] 8011b68: 681b ldr r3, [r3, #0] 8011b6a: f042 0201 orr.w r2, r2, #1 8011b6e: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8011b70: 2300 movs r3, #0 } 8011b72: 4618 mov r0, r3 8011b74: 3710 adds r7, #16 8011b76: 46bd mov sp, r7 8011b78: bd80 pop {r7, pc} 8011b7a: bf00 nop 8011b7c: 40012c00 .word 0x40012c00 8011b80: 40000400 .word 0x40000400 8011b84: 40000800 .word 0x40000800 8011b88: 40000c00 .word 0x40000c00 08011b8c : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 8011b8c: b580 push {r7, lr} 8011b8e: b082 sub sp, #8 8011b90: af00 add r7, sp, #0 8011b92: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8011b94: 687b ldr r3, [r7, #4] 8011b96: 2b00 cmp r3, #0 8011b98: d101 bne.n 8011b9e { return HAL_ERROR; 8011b9a: 2301 movs r3, #1 8011b9c: e041 b.n 8011c22 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8011b9e: 687b ldr r3, [r7, #4] 8011ba0: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8011ba4: b2db uxtb r3, r3 8011ba6: 2b00 cmp r3, #0 8011ba8: d106 bne.n 8011bb8 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8011baa: 687b ldr r3, [r7, #4] 8011bac: 2200 movs r2, #0 8011bae: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 8011bb2: 6878 ldr r0, [r7, #4] 8011bb4: f000 f839 bl 8011c2a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8011bb8: 687b ldr r3, [r7, #4] 8011bba: 2202 movs r2, #2 8011bbc: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8011bc0: 687b ldr r3, [r7, #4] 8011bc2: 681a ldr r2, [r3, #0] 8011bc4: 687b ldr r3, [r7, #4] 8011bc6: 3304 adds r3, #4 8011bc8: 4619 mov r1, r3 8011bca: 4610 mov r0, r2 8011bcc: f000 fbe2 bl 8012394 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8011bd0: 687b ldr r3, [r7, #4] 8011bd2: 2201 movs r2, #1 8011bd4: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011bd8: 687b ldr r3, [r7, #4] 8011bda: 2201 movs r2, #1 8011bdc: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011be0: 687b ldr r3, [r7, #4] 8011be2: 2201 movs r2, #1 8011be4: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011be8: 687b ldr r3, [r7, #4] 8011bea: 2201 movs r2, #1 8011bec: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011bf0: 687b ldr r3, [r7, #4] 8011bf2: 2201 movs r2, #1 8011bf4: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011bf8: 687b ldr r3, [r7, #4] 8011bfa: 2201 movs r2, #1 8011bfc: f883 2042 strb.w r2, [r3, #66] @ 0x42 8011c00: 687b ldr r3, [r7, #4] 8011c02: 2201 movs r2, #1 8011c04: f883 2043 strb.w r2, [r3, #67] @ 0x43 8011c08: 687b ldr r3, [r7, #4] 8011c0a: 2201 movs r2, #1 8011c0c: f883 2044 strb.w r2, [r3, #68] @ 0x44 8011c10: 687b ldr r3, [r7, #4] 8011c12: 2201 movs r2, #1 8011c14: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8011c18: 687b ldr r3, [r7, #4] 8011c1a: 2201 movs r2, #1 8011c1c: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8011c20: 2300 movs r3, #0 } 8011c22: 4618 mov r0, r3 8011c24: 3708 adds r7, #8 8011c26: 46bd mov sp, r7 8011c28: bd80 pop {r7, pc} 08011c2a : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 8011c2a: b480 push {r7} 8011c2c: b083 sub sp, #12 8011c2e: af00 add r7, sp, #0 8011c30: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 8011c32: bf00 nop 8011c34: 370c adds r7, #12 8011c36: 46bd mov sp, r7 8011c38: bc80 pop {r7} 8011c3a: 4770 bx lr 08011c3c : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8011c3c: b580 push {r7, lr} 8011c3e: b084 sub sp, #16 8011c40: af00 add r7, sp, #0 8011c42: 6078 str r0, [r7, #4] 8011c44: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 8011c46: 683b ldr r3, [r7, #0] 8011c48: 2b00 cmp r3, #0 8011c4a: d109 bne.n 8011c60 8011c4c: 687b ldr r3, [r7, #4] 8011c4e: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8011c52: b2db uxtb r3, r3 8011c54: 2b01 cmp r3, #1 8011c56: bf14 ite ne 8011c58: 2301 movne r3, #1 8011c5a: 2300 moveq r3, #0 8011c5c: b2db uxtb r3, r3 8011c5e: e022 b.n 8011ca6 8011c60: 683b ldr r3, [r7, #0] 8011c62: 2b04 cmp r3, #4 8011c64: d109 bne.n 8011c7a 8011c66: 687b ldr r3, [r7, #4] 8011c68: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8011c6c: b2db uxtb r3, r3 8011c6e: 2b01 cmp r3, #1 8011c70: bf14 ite ne 8011c72: 2301 movne r3, #1 8011c74: 2300 moveq r3, #0 8011c76: b2db uxtb r3, r3 8011c78: e015 b.n 8011ca6 8011c7a: 683b ldr r3, [r7, #0] 8011c7c: 2b08 cmp r3, #8 8011c7e: d109 bne.n 8011c94 8011c80: 687b ldr r3, [r7, #4] 8011c82: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8011c86: b2db uxtb r3, r3 8011c88: 2b01 cmp r3, #1 8011c8a: bf14 ite ne 8011c8c: 2301 movne r3, #1 8011c8e: 2300 moveq r3, #0 8011c90: b2db uxtb r3, r3 8011c92: e008 b.n 8011ca6 8011c94: 687b ldr r3, [r7, #4] 8011c96: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011c9a: b2db uxtb r3, r3 8011c9c: 2b01 cmp r3, #1 8011c9e: bf14 ite ne 8011ca0: 2301 movne r3, #1 8011ca2: 2300 moveq r3, #0 8011ca4: b2db uxtb r3, r3 8011ca6: 2b00 cmp r3, #0 8011ca8: d001 beq.n 8011cae { return HAL_ERROR; 8011caa: 2301 movs r3, #1 8011cac: e063 b.n 8011d76 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8011cae: 683b ldr r3, [r7, #0] 8011cb0: 2b00 cmp r3, #0 8011cb2: d104 bne.n 8011cbe 8011cb4: 687b ldr r3, [r7, #4] 8011cb6: 2202 movs r2, #2 8011cb8: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011cbc: e013 b.n 8011ce6 8011cbe: 683b ldr r3, [r7, #0] 8011cc0: 2b04 cmp r3, #4 8011cc2: d104 bne.n 8011cce 8011cc4: 687b ldr r3, [r7, #4] 8011cc6: 2202 movs r2, #2 8011cc8: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011ccc: e00b b.n 8011ce6 8011cce: 683b ldr r3, [r7, #0] 8011cd0: 2b08 cmp r3, #8 8011cd2: d104 bne.n 8011cde 8011cd4: 687b ldr r3, [r7, #4] 8011cd6: 2202 movs r2, #2 8011cd8: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011cdc: e003 b.n 8011ce6 8011cde: 687b ldr r3, [r7, #4] 8011ce0: 2202 movs r2, #2 8011ce2: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 8011ce6: 687b ldr r3, [r7, #4] 8011ce8: 681b ldr r3, [r3, #0] 8011cea: 2201 movs r2, #1 8011cec: 6839 ldr r1, [r7, #0] 8011cee: 4618 mov r0, r3 8011cf0: f000 fde6 bl 80128c0 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8011cf4: 687b ldr r3, [r7, #4] 8011cf6: 681b ldr r3, [r3, #0] 8011cf8: 4a21 ldr r2, [pc, #132] @ (8011d80 ) 8011cfa: 4293 cmp r3, r2 8011cfc: d107 bne.n 8011d0e { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8011cfe: 687b ldr r3, [r7, #4] 8011d00: 681b ldr r3, [r3, #0] 8011d02: 6c5a ldr r2, [r3, #68] @ 0x44 8011d04: 687b ldr r3, [r7, #4] 8011d06: 681b ldr r3, [r3, #0] 8011d08: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8011d0c: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8011d0e: 687b ldr r3, [r7, #4] 8011d10: 681b ldr r3, [r3, #0] 8011d12: 4a1b ldr r2, [pc, #108] @ (8011d80 ) 8011d14: 4293 cmp r3, r2 8011d16: d013 beq.n 8011d40 8011d18: 687b ldr r3, [r7, #4] 8011d1a: 681b ldr r3, [r3, #0] 8011d1c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8011d20: d00e beq.n 8011d40 8011d22: 687b ldr r3, [r7, #4] 8011d24: 681b ldr r3, [r3, #0] 8011d26: 4a17 ldr r2, [pc, #92] @ (8011d84 ) 8011d28: 4293 cmp r3, r2 8011d2a: d009 beq.n 8011d40 8011d2c: 687b ldr r3, [r7, #4] 8011d2e: 681b ldr r3, [r3, #0] 8011d30: 4a15 ldr r2, [pc, #84] @ (8011d88 ) 8011d32: 4293 cmp r3, r2 8011d34: d004 beq.n 8011d40 8011d36: 687b ldr r3, [r7, #4] 8011d38: 681b ldr r3, [r3, #0] 8011d3a: 4a14 ldr r2, [pc, #80] @ (8011d8c ) 8011d3c: 4293 cmp r3, r2 8011d3e: d111 bne.n 8011d64 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8011d40: 687b ldr r3, [r7, #4] 8011d42: 681b ldr r3, [r3, #0] 8011d44: 689b ldr r3, [r3, #8] 8011d46: f003 0307 and.w r3, r3, #7 8011d4a: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8011d4c: 68fb ldr r3, [r7, #12] 8011d4e: 2b06 cmp r3, #6 8011d50: d010 beq.n 8011d74 { __HAL_TIM_ENABLE(htim); 8011d52: 687b ldr r3, [r7, #4] 8011d54: 681b ldr r3, [r3, #0] 8011d56: 681a ldr r2, [r3, #0] 8011d58: 687b ldr r3, [r7, #4] 8011d5a: 681b ldr r3, [r3, #0] 8011d5c: f042 0201 orr.w r2, r2, #1 8011d60: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8011d62: e007 b.n 8011d74 } } else { __HAL_TIM_ENABLE(htim); 8011d64: 687b ldr r3, [r7, #4] 8011d66: 681b ldr r3, [r3, #0] 8011d68: 681a ldr r2, [r3, #0] 8011d6a: 687b ldr r3, [r7, #4] 8011d6c: 681b ldr r3, [r3, #0] 8011d6e: f042 0201 orr.w r2, r2, #1 8011d72: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8011d74: 2300 movs r3, #0 } 8011d76: 4618 mov r0, r3 8011d78: 3710 adds r7, #16 8011d7a: 46bd mov sp, r7 8011d7c: bd80 pop {r7, pc} 8011d7e: bf00 nop 8011d80: 40012c00 .word 0x40012c00 8011d84: 40000400 .word 0x40000400 8011d88: 40000800 .word 0x40000800 8011d8c: 40000c00 .word 0x40000c00 08011d90 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8011d90: b580 push {r7, lr} 8011d92: b084 sub sp, #16 8011d94: af00 add r7, sp, #0 8011d96: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 8011d98: 687b ldr r3, [r7, #4] 8011d9a: 681b ldr r3, [r3, #0] 8011d9c: 68db ldr r3, [r3, #12] 8011d9e: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 8011da0: 687b ldr r3, [r7, #4] 8011da2: 681b ldr r3, [r3, #0] 8011da4: 691b ldr r3, [r3, #16] 8011da6: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 8011da8: 68bb ldr r3, [r7, #8] 8011daa: f003 0302 and.w r3, r3, #2 8011dae: 2b00 cmp r3, #0 8011db0: d020 beq.n 8011df4 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 8011db2: 68fb ldr r3, [r7, #12] 8011db4: f003 0302 and.w r3, r3, #2 8011db8: 2b00 cmp r3, #0 8011dba: d01b beq.n 8011df4 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 8011dbc: 687b ldr r3, [r7, #4] 8011dbe: 681b ldr r3, [r3, #0] 8011dc0: f06f 0202 mvn.w r2, #2 8011dc4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 8011dc6: 687b ldr r3, [r7, #4] 8011dc8: 2201 movs r2, #1 8011dca: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8011dcc: 687b ldr r3, [r7, #4] 8011dce: 681b ldr r3, [r3, #0] 8011dd0: 699b ldr r3, [r3, #24] 8011dd2: f003 0303 and.w r3, r3, #3 8011dd6: 2b00 cmp r3, #0 8011dd8: d003 beq.n 8011de2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8011dda: 6878 ldr r0, [r7, #4] 8011ddc: f000 fabf bl 801235e 8011de0: e005 b.n 8011dee { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8011de2: 6878 ldr r0, [r7, #4] 8011de4: f000 fab2 bl 801234c HAL_TIM_PWM_PulseFinishedCallback(htim); 8011de8: 6878 ldr r0, [r7, #4] 8011dea: f000 fac1 bl 8012370 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8011dee: 687b ldr r3, [r7, #4] 8011df0: 2200 movs r2, #0 8011df2: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 8011df4: 68bb ldr r3, [r7, #8] 8011df6: f003 0304 and.w r3, r3, #4 8011dfa: 2b00 cmp r3, #0 8011dfc: d020 beq.n 8011e40 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 8011dfe: 68fb ldr r3, [r7, #12] 8011e00: f003 0304 and.w r3, r3, #4 8011e04: 2b00 cmp r3, #0 8011e06: d01b beq.n 8011e40 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 8011e08: 687b ldr r3, [r7, #4] 8011e0a: 681b ldr r3, [r3, #0] 8011e0c: f06f 0204 mvn.w r2, #4 8011e10: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8011e12: 687b ldr r3, [r7, #4] 8011e14: 2202 movs r2, #2 8011e16: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8011e18: 687b ldr r3, [r7, #4] 8011e1a: 681b ldr r3, [r3, #0] 8011e1c: 699b ldr r3, [r3, #24] 8011e1e: f403 7340 and.w r3, r3, #768 @ 0x300 8011e22: 2b00 cmp r3, #0 8011e24: d003 beq.n 8011e2e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8011e26: 6878 ldr r0, [r7, #4] 8011e28: f000 fa99 bl 801235e 8011e2c: e005 b.n 8011e3a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8011e2e: 6878 ldr r0, [r7, #4] 8011e30: f000 fa8c bl 801234c HAL_TIM_PWM_PulseFinishedCallback(htim); 8011e34: 6878 ldr r0, [r7, #4] 8011e36: f000 fa9b bl 8012370 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8011e3a: 687b ldr r3, [r7, #4] 8011e3c: 2200 movs r2, #0 8011e3e: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 8011e40: 68bb ldr r3, [r7, #8] 8011e42: f003 0308 and.w r3, r3, #8 8011e46: 2b00 cmp r3, #0 8011e48: d020 beq.n 8011e8c { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 8011e4a: 68fb ldr r3, [r7, #12] 8011e4c: f003 0308 and.w r3, r3, #8 8011e50: 2b00 cmp r3, #0 8011e52: d01b beq.n 8011e8c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 8011e54: 687b ldr r3, [r7, #4] 8011e56: 681b ldr r3, [r3, #0] 8011e58: f06f 0208 mvn.w r2, #8 8011e5c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8011e5e: 687b ldr r3, [r7, #4] 8011e60: 2204 movs r2, #4 8011e62: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8011e64: 687b ldr r3, [r7, #4] 8011e66: 681b ldr r3, [r3, #0] 8011e68: 69db ldr r3, [r3, #28] 8011e6a: f003 0303 and.w r3, r3, #3 8011e6e: 2b00 cmp r3, #0 8011e70: d003 beq.n 8011e7a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8011e72: 6878 ldr r0, [r7, #4] 8011e74: f000 fa73 bl 801235e 8011e78: e005 b.n 8011e86 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8011e7a: 6878 ldr r0, [r7, #4] 8011e7c: f000 fa66 bl 801234c HAL_TIM_PWM_PulseFinishedCallback(htim); 8011e80: 6878 ldr r0, [r7, #4] 8011e82: f000 fa75 bl 8012370 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8011e86: 687b ldr r3, [r7, #4] 8011e88: 2200 movs r2, #0 8011e8a: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 8011e8c: 68bb ldr r3, [r7, #8] 8011e8e: f003 0310 and.w r3, r3, #16 8011e92: 2b00 cmp r3, #0 8011e94: d020 beq.n 8011ed8 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 8011e96: 68fb ldr r3, [r7, #12] 8011e98: f003 0310 and.w r3, r3, #16 8011e9c: 2b00 cmp r3, #0 8011e9e: d01b beq.n 8011ed8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 8011ea0: 687b ldr r3, [r7, #4] 8011ea2: 681b ldr r3, [r3, #0] 8011ea4: f06f 0210 mvn.w r2, #16 8011ea8: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8011eaa: 687b ldr r3, [r7, #4] 8011eac: 2208 movs r2, #8 8011eae: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8011eb0: 687b ldr r3, [r7, #4] 8011eb2: 681b ldr r3, [r3, #0] 8011eb4: 69db ldr r3, [r3, #28] 8011eb6: f403 7340 and.w r3, r3, #768 @ 0x300 8011eba: 2b00 cmp r3, #0 8011ebc: d003 beq.n 8011ec6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8011ebe: 6878 ldr r0, [r7, #4] 8011ec0: f000 fa4d bl 801235e 8011ec4: e005 b.n 8011ed2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8011ec6: 6878 ldr r0, [r7, #4] 8011ec8: f000 fa40 bl 801234c HAL_TIM_PWM_PulseFinishedCallback(htim); 8011ecc: 6878 ldr r0, [r7, #4] 8011ece: f000 fa4f bl 8012370 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8011ed2: 687b ldr r3, [r7, #4] 8011ed4: 2200 movs r2, #0 8011ed6: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 8011ed8: 68bb ldr r3, [r7, #8] 8011eda: f003 0301 and.w r3, r3, #1 8011ede: 2b00 cmp r3, #0 8011ee0: d00c beq.n 8011efc { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 8011ee2: 68fb ldr r3, [r7, #12] 8011ee4: f003 0301 and.w r3, r3, #1 8011ee8: 2b00 cmp r3, #0 8011eea: d007 beq.n 8011efc { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 8011eec: 687b ldr r3, [r7, #4] 8011eee: 681b ldr r3, [r3, #0] 8011ef0: f06f 0201 mvn.w r2, #1 8011ef4: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 8011ef6: 6878 ldr r0, [r7, #4] 8011ef8: f000 fa1f bl 801233a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) 8011efc: 68bb ldr r3, [r7, #8] 8011efe: f003 0380 and.w r3, r3, #128 @ 0x80 8011f02: 2b00 cmp r3, #0 8011f04: d00c beq.n 8011f20 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8011f06: 68fb ldr r3, [r7, #12] 8011f08: f003 0380 and.w r3, r3, #128 @ 0x80 8011f0c: 2b00 cmp r3, #0 8011f0e: d007 beq.n 8011f20 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); 8011f10: 687b ldr r3, [r7, #4] 8011f12: 681b ldr r3, [r3, #0] 8011f14: f06f 0280 mvn.w r2, #128 @ 0x80 8011f18: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8011f1a: 6878 ldr r0, [r7, #4] 8011f1c: f000 fd63 bl 80129e6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 8011f20: 68bb ldr r3, [r7, #8] 8011f22: f003 0340 and.w r3, r3, #64 @ 0x40 8011f26: 2b00 cmp r3, #0 8011f28: d00c beq.n 8011f44 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 8011f2a: 68fb ldr r3, [r7, #12] 8011f2c: f003 0340 and.w r3, r3, #64 @ 0x40 8011f30: 2b00 cmp r3, #0 8011f32: d007 beq.n 8011f44 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 8011f34: 687b ldr r3, [r7, #4] 8011f36: 681b ldr r3, [r3, #0] 8011f38: f06f 0240 mvn.w r2, #64 @ 0x40 8011f3c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 8011f3e: 6878 ldr r0, [r7, #4] 8011f40: f000 fa1f bl 8012382 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 8011f44: 68bb ldr r3, [r7, #8] 8011f46: f003 0320 and.w r3, r3, #32 8011f4a: 2b00 cmp r3, #0 8011f4c: d00c beq.n 8011f68 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 8011f4e: 68fb ldr r3, [r7, #12] 8011f50: f003 0320 and.w r3, r3, #32 8011f54: 2b00 cmp r3, #0 8011f56: d007 beq.n 8011f68 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 8011f58: 687b ldr r3, [r7, #4] 8011f5a: 681b ldr r3, [r3, #0] 8011f5c: f06f 0220 mvn.w r2, #32 8011f60: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8011f62: 6878 ldr r0, [r7, #4] 8011f64: f000 fd36 bl 80129d4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8011f68: bf00 nop 8011f6a: 3710 adds r7, #16 8011f6c: 46bd mov sp, r7 8011f6e: bd80 pop {r7, pc} 08011f70 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8011f70: b580 push {r7, lr} 8011f72: b086 sub sp, #24 8011f74: af00 add r7, sp, #0 8011f76: 60f8 str r0, [r7, #12] 8011f78: 60b9 str r1, [r7, #8] 8011f7a: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8011f7c: 2300 movs r3, #0 8011f7e: 75fb strb r3, [r7, #23] assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); 8011f80: 68fb ldr r3, [r7, #12] 8011f82: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8011f86: 2b01 cmp r3, #1 8011f88: d101 bne.n 8011f8e 8011f8a: 2302 movs r3, #2 8011f8c: e048 b.n 8012020 8011f8e: 68fb ldr r3, [r7, #12] 8011f90: 2201 movs r2, #1 8011f92: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 8011f96: 687b ldr r3, [r7, #4] 8011f98: 2b0c cmp r3, #12 8011f9a: d839 bhi.n 8012010 8011f9c: a201 add r2, pc, #4 @ (adr r2, 8011fa4 ) 8011f9e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011fa2: bf00 nop 8011fa4: 08011fd9 .word 0x08011fd9 8011fa8: 08012011 .word 0x08012011 8011fac: 08012011 .word 0x08012011 8011fb0: 08012011 .word 0x08012011 8011fb4: 08011fe7 .word 0x08011fe7 8011fb8: 08012011 .word 0x08012011 8011fbc: 08012011 .word 0x08012011 8011fc0: 08012011 .word 0x08012011 8011fc4: 08011ff5 .word 0x08011ff5 8011fc8: 08012011 .word 0x08012011 8011fcc: 08012011 .word 0x08012011 8011fd0: 08012011 .word 0x08012011 8011fd4: 08012003 .word 0x08012003 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8011fd8: 68fb ldr r3, [r7, #12] 8011fda: 681b ldr r3, [r3, #0] 8011fdc: 68b9 ldr r1, [r7, #8] 8011fde: 4618 mov r0, r3 8011fe0: f000 fa50 bl 8012484 break; 8011fe4: e017 b.n 8012016 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8011fe6: 68fb ldr r3, [r7, #12] 8011fe8: 681b ldr r3, [r3, #0] 8011fea: 68b9 ldr r1, [r7, #8] 8011fec: 4618 mov r0, r3 8011fee: f000 faaf bl 8012550 break; 8011ff2: e010 b.n 8012016 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8011ff4: 68fb ldr r3, [r7, #12] 8011ff6: 681b ldr r3, [r3, #0] 8011ff8: 68b9 ldr r1, [r7, #8] 8011ffa: 4618 mov r0, r3 8011ffc: f000 fb12 bl 8012624 break; 8012000: e009 b.n 8012016 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8012002: 68fb ldr r3, [r7, #12] 8012004: 681b ldr r3, [r3, #0] 8012006: 68b9 ldr r1, [r7, #8] 8012008: 4618 mov r0, r3 801200a: f000 fb75 bl 80126f8 break; 801200e: e002 b.n 8012016 } default: status = HAL_ERROR; 8012010: 2301 movs r3, #1 8012012: 75fb strb r3, [r7, #23] break; 8012014: bf00 nop } __HAL_UNLOCK(htim); 8012016: 68fb ldr r3, [r7, #12] 8012018: 2200 movs r2, #0 801201a: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 801201e: 7dfb ldrb r3, [r7, #23] } 8012020: 4618 mov r0, r3 8012022: 3718 adds r7, #24 8012024: 46bd mov sp, r7 8012026: bd80 pop {r7, pc} 08012028 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8012028: b580 push {r7, lr} 801202a: b086 sub sp, #24 801202c: af00 add r7, sp, #0 801202e: 60f8 str r0, [r7, #12] 8012030: 60b9 str r1, [r7, #8] 8012032: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8012034: 2300 movs r3, #0 8012036: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 8012038: 68fb ldr r3, [r7, #12] 801203a: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 801203e: 2b01 cmp r3, #1 8012040: d101 bne.n 8012046 8012042: 2302 movs r3, #2 8012044: e0ae b.n 80121a4 8012046: 68fb ldr r3, [r7, #12] 8012048: 2201 movs r2, #1 801204a: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 801204e: 687b ldr r3, [r7, #4] 8012050: 2b0c cmp r3, #12 8012052: f200 809f bhi.w 8012194 8012056: a201 add r2, pc, #4 @ (adr r2, 801205c ) 8012058: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801205c: 08012091 .word 0x08012091 8012060: 08012195 .word 0x08012195 8012064: 08012195 .word 0x08012195 8012068: 08012195 .word 0x08012195 801206c: 080120d1 .word 0x080120d1 8012070: 08012195 .word 0x08012195 8012074: 08012195 .word 0x08012195 8012078: 08012195 .word 0x08012195 801207c: 08012113 .word 0x08012113 8012080: 08012195 .word 0x08012195 8012084: 08012195 .word 0x08012195 8012088: 08012195 .word 0x08012195 801208c: 08012153 .word 0x08012153 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8012090: 68fb ldr r3, [r7, #12] 8012092: 681b ldr r3, [r3, #0] 8012094: 68b9 ldr r1, [r7, #8] 8012096: 4618 mov r0, r3 8012098: f000 f9f4 bl 8012484 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 801209c: 68fb ldr r3, [r7, #12] 801209e: 681b ldr r3, [r3, #0] 80120a0: 699a ldr r2, [r3, #24] 80120a2: 68fb ldr r3, [r7, #12] 80120a4: 681b ldr r3, [r3, #0] 80120a6: f042 0208 orr.w r2, r2, #8 80120aa: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 80120ac: 68fb ldr r3, [r7, #12] 80120ae: 681b ldr r3, [r3, #0] 80120b0: 699a ldr r2, [r3, #24] 80120b2: 68fb ldr r3, [r7, #12] 80120b4: 681b ldr r3, [r3, #0] 80120b6: f022 0204 bic.w r2, r2, #4 80120ba: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 80120bc: 68fb ldr r3, [r7, #12] 80120be: 681b ldr r3, [r3, #0] 80120c0: 6999 ldr r1, [r3, #24] 80120c2: 68bb ldr r3, [r7, #8] 80120c4: 691a ldr r2, [r3, #16] 80120c6: 68fb ldr r3, [r7, #12] 80120c8: 681b ldr r3, [r3, #0] 80120ca: 430a orrs r2, r1 80120cc: 619a str r2, [r3, #24] break; 80120ce: e064 b.n 801219a { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 80120d0: 68fb ldr r3, [r7, #12] 80120d2: 681b ldr r3, [r3, #0] 80120d4: 68b9 ldr r1, [r7, #8] 80120d6: 4618 mov r0, r3 80120d8: f000 fa3a bl 8012550 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 80120dc: 68fb ldr r3, [r7, #12] 80120de: 681b ldr r3, [r3, #0] 80120e0: 699a ldr r2, [r3, #24] 80120e2: 68fb ldr r3, [r7, #12] 80120e4: 681b ldr r3, [r3, #0] 80120e6: f442 6200 orr.w r2, r2, #2048 @ 0x800 80120ea: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 80120ec: 68fb ldr r3, [r7, #12] 80120ee: 681b ldr r3, [r3, #0] 80120f0: 699a ldr r2, [r3, #24] 80120f2: 68fb ldr r3, [r7, #12] 80120f4: 681b ldr r3, [r3, #0] 80120f6: f422 6280 bic.w r2, r2, #1024 @ 0x400 80120fa: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 80120fc: 68fb ldr r3, [r7, #12] 80120fe: 681b ldr r3, [r3, #0] 8012100: 6999 ldr r1, [r3, #24] 8012102: 68bb ldr r3, [r7, #8] 8012104: 691b ldr r3, [r3, #16] 8012106: 021a lsls r2, r3, #8 8012108: 68fb ldr r3, [r7, #12] 801210a: 681b ldr r3, [r3, #0] 801210c: 430a orrs r2, r1 801210e: 619a str r2, [r3, #24] break; 8012110: e043 b.n 801219a { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8012112: 68fb ldr r3, [r7, #12] 8012114: 681b ldr r3, [r3, #0] 8012116: 68b9 ldr r1, [r7, #8] 8012118: 4618 mov r0, r3 801211a: f000 fa83 bl 8012624 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 801211e: 68fb ldr r3, [r7, #12] 8012120: 681b ldr r3, [r3, #0] 8012122: 69da ldr r2, [r3, #28] 8012124: 68fb ldr r3, [r7, #12] 8012126: 681b ldr r3, [r3, #0] 8012128: f042 0208 orr.w r2, r2, #8 801212c: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 801212e: 68fb ldr r3, [r7, #12] 8012130: 681b ldr r3, [r3, #0] 8012132: 69da ldr r2, [r3, #28] 8012134: 68fb ldr r3, [r7, #12] 8012136: 681b ldr r3, [r3, #0] 8012138: f022 0204 bic.w r2, r2, #4 801213c: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 801213e: 68fb ldr r3, [r7, #12] 8012140: 681b ldr r3, [r3, #0] 8012142: 69d9 ldr r1, [r3, #28] 8012144: 68bb ldr r3, [r7, #8] 8012146: 691a ldr r2, [r3, #16] 8012148: 68fb ldr r3, [r7, #12] 801214a: 681b ldr r3, [r3, #0] 801214c: 430a orrs r2, r1 801214e: 61da str r2, [r3, #28] break; 8012150: e023 b.n 801219a { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8012152: 68fb ldr r3, [r7, #12] 8012154: 681b ldr r3, [r3, #0] 8012156: 68b9 ldr r1, [r7, #8] 8012158: 4618 mov r0, r3 801215a: f000 facd bl 80126f8 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 801215e: 68fb ldr r3, [r7, #12] 8012160: 681b ldr r3, [r3, #0] 8012162: 69da ldr r2, [r3, #28] 8012164: 68fb ldr r3, [r7, #12] 8012166: 681b ldr r3, [r3, #0] 8012168: f442 6200 orr.w r2, r2, #2048 @ 0x800 801216c: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 801216e: 68fb ldr r3, [r7, #12] 8012170: 681b ldr r3, [r3, #0] 8012172: 69da ldr r2, [r3, #28] 8012174: 68fb ldr r3, [r7, #12] 8012176: 681b ldr r3, [r3, #0] 8012178: f422 6280 bic.w r2, r2, #1024 @ 0x400 801217c: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 801217e: 68fb ldr r3, [r7, #12] 8012180: 681b ldr r3, [r3, #0] 8012182: 69d9 ldr r1, [r3, #28] 8012184: 68bb ldr r3, [r7, #8] 8012186: 691b ldr r3, [r3, #16] 8012188: 021a lsls r2, r3, #8 801218a: 68fb ldr r3, [r7, #12] 801218c: 681b ldr r3, [r3, #0] 801218e: 430a orrs r2, r1 8012190: 61da str r2, [r3, #28] break; 8012192: e002 b.n 801219a } default: status = HAL_ERROR; 8012194: 2301 movs r3, #1 8012196: 75fb strb r3, [r7, #23] break; 8012198: bf00 nop } __HAL_UNLOCK(htim); 801219a: 68fb ldr r3, [r7, #12] 801219c: 2200 movs r2, #0 801219e: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 80121a2: 7dfb ldrb r3, [r7, #23] } 80121a4: 4618 mov r0, r3 80121a6: 3718 adds r7, #24 80121a8: 46bd mov sp, r7 80121aa: bd80 pop {r7, pc} 080121ac : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 80121ac: b580 push {r7, lr} 80121ae: b084 sub sp, #16 80121b0: af00 add r7, sp, #0 80121b2: 6078 str r0, [r7, #4] 80121b4: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 80121b6: 2300 movs r3, #0 80121b8: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 80121ba: 687b ldr r3, [r7, #4] 80121bc: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80121c0: 2b01 cmp r3, #1 80121c2: d101 bne.n 80121c8 80121c4: 2302 movs r3, #2 80121c6: e0b4 b.n 8012332 80121c8: 687b ldr r3, [r7, #4] 80121ca: 2201 movs r2, #1 80121cc: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 80121d0: 687b ldr r3, [r7, #4] 80121d2: 2202 movs r2, #2 80121d4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 80121d8: 687b ldr r3, [r7, #4] 80121da: 681b ldr r3, [r3, #0] 80121dc: 689b ldr r3, [r3, #8] 80121de: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 80121e0: 68bb ldr r3, [r7, #8] 80121e2: f023 0377 bic.w r3, r3, #119 @ 0x77 80121e6: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80121e8: 68bb ldr r3, [r7, #8] 80121ea: f423 437f bic.w r3, r3, #65280 @ 0xff00 80121ee: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 80121f0: 687b ldr r3, [r7, #4] 80121f2: 681b ldr r3, [r3, #0] 80121f4: 68ba ldr r2, [r7, #8] 80121f6: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 80121f8: 683b ldr r3, [r7, #0] 80121fa: 681b ldr r3, [r3, #0] 80121fc: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8012200: d03e beq.n 8012280 8012202: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8012206: f200 8087 bhi.w 8012318 801220a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 801220e: f000 8086 beq.w 801231e 8012212: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012216: d87f bhi.n 8012318 8012218: 2b70 cmp r3, #112 @ 0x70 801221a: d01a beq.n 8012252 801221c: 2b70 cmp r3, #112 @ 0x70 801221e: d87b bhi.n 8012318 8012220: 2b60 cmp r3, #96 @ 0x60 8012222: d050 beq.n 80122c6 8012224: 2b60 cmp r3, #96 @ 0x60 8012226: d877 bhi.n 8012318 8012228: 2b50 cmp r3, #80 @ 0x50 801222a: d03c beq.n 80122a6 801222c: 2b50 cmp r3, #80 @ 0x50 801222e: d873 bhi.n 8012318 8012230: 2b40 cmp r3, #64 @ 0x40 8012232: d058 beq.n 80122e6 8012234: 2b40 cmp r3, #64 @ 0x40 8012236: d86f bhi.n 8012318 8012238: 2b30 cmp r3, #48 @ 0x30 801223a: d064 beq.n 8012306 801223c: 2b30 cmp r3, #48 @ 0x30 801223e: d86b bhi.n 8012318 8012240: 2b20 cmp r3, #32 8012242: d060 beq.n 8012306 8012244: 2b20 cmp r3, #32 8012246: d867 bhi.n 8012318 8012248: 2b00 cmp r3, #0 801224a: d05c beq.n 8012306 801224c: 2b10 cmp r3, #16 801224e: d05a beq.n 8012306 8012250: e062 b.n 8012318 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8012252: 687b ldr r3, [r7, #4] 8012254: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8012256: 683b ldr r3, [r7, #0] 8012258: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 801225a: 683b ldr r3, [r7, #0] 801225c: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 801225e: 683b ldr r3, [r7, #0] 8012260: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8012262: f000 fb0e bl 8012882 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 8012266: 687b ldr r3, [r7, #4] 8012268: 681b ldr r3, [r3, #0] 801226a: 689b ldr r3, [r3, #8] 801226c: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 801226e: 68bb ldr r3, [r7, #8] 8012270: f043 0377 orr.w r3, r3, #119 @ 0x77 8012274: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8012276: 687b ldr r3, [r7, #4] 8012278: 681b ldr r3, [r3, #0] 801227a: 68ba ldr r2, [r7, #8] 801227c: 609a str r2, [r3, #8] break; 801227e: e04f b.n 8012320 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8012280: 687b ldr r3, [r7, #4] 8012282: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8012284: 683b ldr r3, [r7, #0] 8012286: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 8012288: 683b ldr r3, [r7, #0] 801228a: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 801228c: 683b ldr r3, [r7, #0] 801228e: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8012290: f000 faf7 bl 8012882 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 8012294: 687b ldr r3, [r7, #4] 8012296: 681b ldr r3, [r3, #0] 8012298: 689a ldr r2, [r3, #8] 801229a: 687b ldr r3, [r7, #4] 801229c: 681b ldr r3, [r3, #0] 801229e: f442 4280 orr.w r2, r2, #16384 @ 0x4000 80122a2: 609a str r2, [r3, #8] break; 80122a4: e03c b.n 8012320 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 80122a6: 687b ldr r3, [r7, #4] 80122a8: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80122aa: 683b ldr r3, [r7, #0] 80122ac: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80122ae: 683b ldr r3, [r7, #0] 80122b0: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 80122b2: 461a mov r2, r3 80122b4: f000 fa6e bl 8012794 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 80122b8: 687b ldr r3, [r7, #4] 80122ba: 681b ldr r3, [r3, #0] 80122bc: 2150 movs r1, #80 @ 0x50 80122be: 4618 mov r0, r3 80122c0: f000 fac5 bl 801284e break; 80122c4: e02c b.n 8012320 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 80122c6: 687b ldr r3, [r7, #4] 80122c8: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80122ca: 683b ldr r3, [r7, #0] 80122cc: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80122ce: 683b ldr r3, [r7, #0] 80122d0: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 80122d2: 461a mov r2, r3 80122d4: f000 fa8c bl 80127f0 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 80122d8: 687b ldr r3, [r7, #4] 80122da: 681b ldr r3, [r3, #0] 80122dc: 2160 movs r1, #96 @ 0x60 80122de: 4618 mov r0, r3 80122e0: f000 fab5 bl 801284e break; 80122e4: e01c b.n 8012320 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 80122e6: 687b ldr r3, [r7, #4] 80122e8: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80122ea: 683b ldr r3, [r7, #0] 80122ec: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80122ee: 683b ldr r3, [r7, #0] 80122f0: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 80122f2: 461a mov r2, r3 80122f4: f000 fa4e bl 8012794 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 80122f8: 687b ldr r3, [r7, #4] 80122fa: 681b ldr r3, [r3, #0] 80122fc: 2140 movs r1, #64 @ 0x40 80122fe: 4618 mov r0, r3 8012300: f000 faa5 bl 801284e break; 8012304: e00c b.n 8012320 case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 8012306: 687b ldr r3, [r7, #4] 8012308: 681a ldr r2, [r3, #0] 801230a: 683b ldr r3, [r7, #0] 801230c: 681b ldr r3, [r3, #0] 801230e: 4619 mov r1, r3 8012310: 4610 mov r0, r2 8012312: f000 fa9c bl 801284e break; 8012316: e003 b.n 8012320 } default: status = HAL_ERROR; 8012318: 2301 movs r3, #1 801231a: 73fb strb r3, [r7, #15] break; 801231c: e000 b.n 8012320 break; 801231e: bf00 nop } htim->State = HAL_TIM_STATE_READY; 8012320: 687b ldr r3, [r7, #4] 8012322: 2201 movs r2, #1 8012324: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8012328: 687b ldr r3, [r7, #4] 801232a: 2200 movs r2, #0 801232c: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8012330: 7bfb ldrb r3, [r7, #15] } 8012332: 4618 mov r0, r3 8012334: 3710 adds r7, #16 8012336: 46bd mov sp, r7 8012338: bd80 pop {r7, pc} 0801233a : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 801233a: b480 push {r7} 801233c: b083 sub sp, #12 801233e: af00 add r7, sp, #0 8012340: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } 8012342: bf00 nop 8012344: 370c adds r7, #12 8012346: 46bd mov sp, r7 8012348: bc80 pop {r7} 801234a: 4770 bx lr 0801234c : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 801234c: b480 push {r7} 801234e: b083 sub sp, #12 8012350: af00 add r7, sp, #0 8012352: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 8012354: bf00 nop 8012356: 370c adds r7, #12 8012358: 46bd mov sp, r7 801235a: bc80 pop {r7} 801235c: 4770 bx lr 0801235e : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 801235e: b480 push {r7} 8012360: b083 sub sp, #12 8012362: af00 add r7, sp, #0 8012364: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 8012366: bf00 nop 8012368: 370c adds r7, #12 801236a: 46bd mov sp, r7 801236c: bc80 pop {r7} 801236e: 4770 bx lr 08012370 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8012370: b480 push {r7} 8012372: b083 sub sp, #12 8012374: af00 add r7, sp, #0 8012376: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8012378: bf00 nop 801237a: 370c adds r7, #12 801237c: 46bd mov sp, r7 801237e: bc80 pop {r7} 8012380: 4770 bx lr 08012382 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8012382: b480 push {r7} 8012384: b083 sub sp, #12 8012386: af00 add r7, sp, #0 8012388: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 801238a: bf00 nop 801238c: 370c adds r7, #12 801238e: 46bd mov sp, r7 8012390: bc80 pop {r7} 8012392: 4770 bx lr 08012394 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8012394: b480 push {r7} 8012396: b085 sub sp, #20 8012398: af00 add r7, sp, #0 801239a: 6078 str r0, [r7, #4] 801239c: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 801239e: 687b ldr r3, [r7, #4] 80123a0: 681b ldr r3, [r3, #0] 80123a2: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80123a4: 687b ldr r3, [r7, #4] 80123a6: 4a33 ldr r2, [pc, #204] @ (8012474 ) 80123a8: 4293 cmp r3, r2 80123aa: d00f beq.n 80123cc 80123ac: 687b ldr r3, [r7, #4] 80123ae: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80123b2: d00b beq.n 80123cc 80123b4: 687b ldr r3, [r7, #4] 80123b6: 4a30 ldr r2, [pc, #192] @ (8012478 ) 80123b8: 4293 cmp r3, r2 80123ba: d007 beq.n 80123cc 80123bc: 687b ldr r3, [r7, #4] 80123be: 4a2f ldr r2, [pc, #188] @ (801247c ) 80123c0: 4293 cmp r3, r2 80123c2: d003 beq.n 80123cc 80123c4: 687b ldr r3, [r7, #4] 80123c6: 4a2e ldr r2, [pc, #184] @ (8012480 ) 80123c8: 4293 cmp r3, r2 80123ca: d108 bne.n 80123de { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80123cc: 68fb ldr r3, [r7, #12] 80123ce: f023 0370 bic.w r3, r3, #112 @ 0x70 80123d2: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80123d4: 683b ldr r3, [r7, #0] 80123d6: 685b ldr r3, [r3, #4] 80123d8: 68fa ldr r2, [r7, #12] 80123da: 4313 orrs r3, r2 80123dc: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80123de: 687b ldr r3, [r7, #4] 80123e0: 4a24 ldr r2, [pc, #144] @ (8012474 ) 80123e2: 4293 cmp r3, r2 80123e4: d00f beq.n 8012406 80123e6: 687b ldr r3, [r7, #4] 80123e8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80123ec: d00b beq.n 8012406 80123ee: 687b ldr r3, [r7, #4] 80123f0: 4a21 ldr r2, [pc, #132] @ (8012478 ) 80123f2: 4293 cmp r3, r2 80123f4: d007 beq.n 8012406 80123f6: 687b ldr r3, [r7, #4] 80123f8: 4a20 ldr r2, [pc, #128] @ (801247c ) 80123fa: 4293 cmp r3, r2 80123fc: d003 beq.n 8012406 80123fe: 687b ldr r3, [r7, #4] 8012400: 4a1f ldr r2, [pc, #124] @ (8012480 ) 8012402: 4293 cmp r3, r2 8012404: d108 bne.n 8012418 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8012406: 68fb ldr r3, [r7, #12] 8012408: f423 7340 bic.w r3, r3, #768 @ 0x300 801240c: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 801240e: 683b ldr r3, [r7, #0] 8012410: 68db ldr r3, [r3, #12] 8012412: 68fa ldr r2, [r7, #12] 8012414: 4313 orrs r3, r2 8012416: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8012418: 68fb ldr r3, [r7, #12] 801241a: f023 0280 bic.w r2, r3, #128 @ 0x80 801241e: 683b ldr r3, [r7, #0] 8012420: 695b ldr r3, [r3, #20] 8012422: 4313 orrs r3, r2 8012424: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 8012426: 687b ldr r3, [r7, #4] 8012428: 68fa ldr r2, [r7, #12] 801242a: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 801242c: 683b ldr r3, [r7, #0] 801242e: 689a ldr r2, [r3, #8] 8012430: 687b ldr r3, [r7, #4] 8012432: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8012434: 683b ldr r3, [r7, #0] 8012436: 681a ldr r2, [r3, #0] 8012438: 687b ldr r3, [r7, #4] 801243a: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 801243c: 687b ldr r3, [r7, #4] 801243e: 4a0d ldr r2, [pc, #52] @ (8012474 ) 8012440: 4293 cmp r3, r2 8012442: d103 bne.n 801244c { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8012444: 683b ldr r3, [r7, #0] 8012446: 691a ldr r2, [r3, #16] 8012448: 687b ldr r3, [r7, #4] 801244a: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 801244c: 687b ldr r3, [r7, #4] 801244e: 2201 movs r2, #1 8012450: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 8012452: 687b ldr r3, [r7, #4] 8012454: 691b ldr r3, [r3, #16] 8012456: f003 0301 and.w r3, r3, #1 801245a: 2b00 cmp r3, #0 801245c: d005 beq.n 801246a { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 801245e: 687b ldr r3, [r7, #4] 8012460: 691b ldr r3, [r3, #16] 8012462: f023 0201 bic.w r2, r3, #1 8012466: 687b ldr r3, [r7, #4] 8012468: 611a str r2, [r3, #16] } } 801246a: bf00 nop 801246c: 3714 adds r7, #20 801246e: 46bd mov sp, r7 8012470: bc80 pop {r7} 8012472: 4770 bx lr 8012474: 40012c00 .word 0x40012c00 8012478: 40000400 .word 0x40000400 801247c: 40000800 .word 0x40000800 8012480: 40000c00 .word 0x40000c00 08012484 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012484: b480 push {r7} 8012486: b087 sub sp, #28 8012488: af00 add r7, sp, #0 801248a: 6078 str r0, [r7, #4] 801248c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 801248e: 687b ldr r3, [r7, #4] 8012490: 6a1b ldr r3, [r3, #32] 8012492: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 8012494: 687b ldr r3, [r7, #4] 8012496: 6a1b ldr r3, [r3, #32] 8012498: f023 0201 bic.w r2, r3, #1 801249c: 687b ldr r3, [r7, #4] 801249e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80124a0: 687b ldr r3, [r7, #4] 80124a2: 685b ldr r3, [r3, #4] 80124a4: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80124a6: 687b ldr r3, [r7, #4] 80124a8: 699b ldr r3, [r3, #24] 80124aa: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 80124ac: 68fb ldr r3, [r7, #12] 80124ae: f023 0370 bic.w r3, r3, #112 @ 0x70 80124b2: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 80124b4: 68fb ldr r3, [r7, #12] 80124b6: f023 0303 bic.w r3, r3, #3 80124ba: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80124bc: 683b ldr r3, [r7, #0] 80124be: 681b ldr r3, [r3, #0] 80124c0: 68fa ldr r2, [r7, #12] 80124c2: 4313 orrs r3, r2 80124c4: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 80124c6: 697b ldr r3, [r7, #20] 80124c8: f023 0302 bic.w r3, r3, #2 80124cc: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 80124ce: 683b ldr r3, [r7, #0] 80124d0: 689b ldr r3, [r3, #8] 80124d2: 697a ldr r2, [r7, #20] 80124d4: 4313 orrs r3, r2 80124d6: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 80124d8: 687b ldr r3, [r7, #4] 80124da: 4a1c ldr r2, [pc, #112] @ (801254c ) 80124dc: 4293 cmp r3, r2 80124de: d10c bne.n 80124fa { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 80124e0: 697b ldr r3, [r7, #20] 80124e2: f023 0308 bic.w r3, r3, #8 80124e6: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 80124e8: 683b ldr r3, [r7, #0] 80124ea: 68db ldr r3, [r3, #12] 80124ec: 697a ldr r2, [r7, #20] 80124ee: 4313 orrs r3, r2 80124f0: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 80124f2: 697b ldr r3, [r7, #20] 80124f4: f023 0304 bic.w r3, r3, #4 80124f8: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80124fa: 687b ldr r3, [r7, #4] 80124fc: 4a13 ldr r2, [pc, #76] @ (801254c ) 80124fe: 4293 cmp r3, r2 8012500: d111 bne.n 8012526 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 8012502: 693b ldr r3, [r7, #16] 8012504: f423 7380 bic.w r3, r3, #256 @ 0x100 8012508: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 801250a: 693b ldr r3, [r7, #16] 801250c: f423 7300 bic.w r3, r3, #512 @ 0x200 8012510: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8012512: 683b ldr r3, [r7, #0] 8012514: 695b ldr r3, [r3, #20] 8012516: 693a ldr r2, [r7, #16] 8012518: 4313 orrs r3, r2 801251a: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 801251c: 683b ldr r3, [r7, #0] 801251e: 699b ldr r3, [r3, #24] 8012520: 693a ldr r2, [r7, #16] 8012522: 4313 orrs r3, r2 8012524: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012526: 687b ldr r3, [r7, #4] 8012528: 693a ldr r2, [r7, #16] 801252a: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 801252c: 687b ldr r3, [r7, #4] 801252e: 68fa ldr r2, [r7, #12] 8012530: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 8012532: 683b ldr r3, [r7, #0] 8012534: 685a ldr r2, [r3, #4] 8012536: 687b ldr r3, [r7, #4] 8012538: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 801253a: 687b ldr r3, [r7, #4] 801253c: 697a ldr r2, [r7, #20] 801253e: 621a str r2, [r3, #32] } 8012540: bf00 nop 8012542: 371c adds r7, #28 8012544: 46bd mov sp, r7 8012546: bc80 pop {r7} 8012548: 4770 bx lr 801254a: bf00 nop 801254c: 40012c00 .word 0x40012c00 08012550 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012550: b480 push {r7} 8012552: b087 sub sp, #28 8012554: af00 add r7, sp, #0 8012556: 6078 str r0, [r7, #4] 8012558: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 801255a: 687b ldr r3, [r7, #4] 801255c: 6a1b ldr r3, [r3, #32] 801255e: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8012560: 687b ldr r3, [r7, #4] 8012562: 6a1b ldr r3, [r3, #32] 8012564: f023 0210 bic.w r2, r3, #16 8012568: 687b ldr r3, [r7, #4] 801256a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 801256c: 687b ldr r3, [r7, #4] 801256e: 685b ldr r3, [r3, #4] 8012570: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8012572: 687b ldr r3, [r7, #4] 8012574: 699b ldr r3, [r3, #24] 8012576: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 8012578: 68fb ldr r3, [r7, #12] 801257a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 801257e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8012580: 68fb ldr r3, [r7, #12] 8012582: f423 7340 bic.w r3, r3, #768 @ 0x300 8012586: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8012588: 683b ldr r3, [r7, #0] 801258a: 681b ldr r3, [r3, #0] 801258c: 021b lsls r3, r3, #8 801258e: 68fa ldr r2, [r7, #12] 8012590: 4313 orrs r3, r2 8012592: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 8012594: 697b ldr r3, [r7, #20] 8012596: f023 0320 bic.w r3, r3, #32 801259a: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 801259c: 683b ldr r3, [r7, #0] 801259e: 689b ldr r3, [r3, #8] 80125a0: 011b lsls r3, r3, #4 80125a2: 697a ldr r2, [r7, #20] 80125a4: 4313 orrs r3, r2 80125a6: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 80125a8: 687b ldr r3, [r7, #4] 80125aa: 4a1d ldr r2, [pc, #116] @ (8012620 ) 80125ac: 4293 cmp r3, r2 80125ae: d10d bne.n 80125cc { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 80125b0: 697b ldr r3, [r7, #20] 80125b2: f023 0380 bic.w r3, r3, #128 @ 0x80 80125b6: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 80125b8: 683b ldr r3, [r7, #0] 80125ba: 68db ldr r3, [r3, #12] 80125bc: 011b lsls r3, r3, #4 80125be: 697a ldr r2, [r7, #20] 80125c0: 4313 orrs r3, r2 80125c2: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 80125c4: 697b ldr r3, [r7, #20] 80125c6: f023 0340 bic.w r3, r3, #64 @ 0x40 80125ca: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80125cc: 687b ldr r3, [r7, #4] 80125ce: 4a14 ldr r2, [pc, #80] @ (8012620 ) 80125d0: 4293 cmp r3, r2 80125d2: d113 bne.n 80125fc /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 80125d4: 693b ldr r3, [r7, #16] 80125d6: f423 6380 bic.w r3, r3, #1024 @ 0x400 80125da: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 80125dc: 693b ldr r3, [r7, #16] 80125de: f423 6300 bic.w r3, r3, #2048 @ 0x800 80125e2: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 80125e4: 683b ldr r3, [r7, #0] 80125e6: 695b ldr r3, [r3, #20] 80125e8: 009b lsls r3, r3, #2 80125ea: 693a ldr r2, [r7, #16] 80125ec: 4313 orrs r3, r2 80125ee: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 80125f0: 683b ldr r3, [r7, #0] 80125f2: 699b ldr r3, [r3, #24] 80125f4: 009b lsls r3, r3, #2 80125f6: 693a ldr r2, [r7, #16] 80125f8: 4313 orrs r3, r2 80125fa: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80125fc: 687b ldr r3, [r7, #4] 80125fe: 693a ldr r2, [r7, #16] 8012600: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8012602: 687b ldr r3, [r7, #4] 8012604: 68fa ldr r2, [r7, #12] 8012606: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8012608: 683b ldr r3, [r7, #0] 801260a: 685a ldr r2, [r3, #4] 801260c: 687b ldr r3, [r7, #4] 801260e: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012610: 687b ldr r3, [r7, #4] 8012612: 697a ldr r2, [r7, #20] 8012614: 621a str r2, [r3, #32] } 8012616: bf00 nop 8012618: 371c adds r7, #28 801261a: 46bd mov sp, r7 801261c: bc80 pop {r7} 801261e: 4770 bx lr 8012620: 40012c00 .word 0x40012c00 08012624 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012624: b480 push {r7} 8012626: b087 sub sp, #28 8012628: af00 add r7, sp, #0 801262a: 6078 str r0, [r7, #4] 801262c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 801262e: 687b ldr r3, [r7, #4] 8012630: 6a1b ldr r3, [r3, #32] 8012632: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8012634: 687b ldr r3, [r7, #4] 8012636: 6a1b ldr r3, [r3, #32] 8012638: f423 7280 bic.w r2, r3, #256 @ 0x100 801263c: 687b ldr r3, [r7, #4] 801263e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8012640: 687b ldr r3, [r7, #4] 8012642: 685b ldr r3, [r3, #4] 8012644: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8012646: 687b ldr r3, [r7, #4] 8012648: 69db ldr r3, [r3, #28] 801264a: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 801264c: 68fb ldr r3, [r7, #12] 801264e: f023 0370 bic.w r3, r3, #112 @ 0x70 8012652: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8012654: 68fb ldr r3, [r7, #12] 8012656: f023 0303 bic.w r3, r3, #3 801265a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 801265c: 683b ldr r3, [r7, #0] 801265e: 681b ldr r3, [r3, #0] 8012660: 68fa ldr r2, [r7, #12] 8012662: 4313 orrs r3, r2 8012664: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8012666: 697b ldr r3, [r7, #20] 8012668: f423 7300 bic.w r3, r3, #512 @ 0x200 801266c: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 801266e: 683b ldr r3, [r7, #0] 8012670: 689b ldr r3, [r3, #8] 8012672: 021b lsls r3, r3, #8 8012674: 697a ldr r2, [r7, #20] 8012676: 4313 orrs r3, r2 8012678: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 801267a: 687b ldr r3, [r7, #4] 801267c: 4a1d ldr r2, [pc, #116] @ (80126f4 ) 801267e: 4293 cmp r3, r2 8012680: d10d bne.n 801269e { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8012682: 697b ldr r3, [r7, #20] 8012684: f423 6300 bic.w r3, r3, #2048 @ 0x800 8012688: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 801268a: 683b ldr r3, [r7, #0] 801268c: 68db ldr r3, [r3, #12] 801268e: 021b lsls r3, r3, #8 8012690: 697a ldr r2, [r7, #20] 8012692: 4313 orrs r3, r2 8012694: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8012696: 697b ldr r3, [r7, #20] 8012698: f423 6380 bic.w r3, r3, #1024 @ 0x400 801269c: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 801269e: 687b ldr r3, [r7, #4] 80126a0: 4a14 ldr r2, [pc, #80] @ (80126f4 ) 80126a2: 4293 cmp r3, r2 80126a4: d113 bne.n 80126ce /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 80126a6: 693b ldr r3, [r7, #16] 80126a8: f423 5380 bic.w r3, r3, #4096 @ 0x1000 80126ac: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 80126ae: 693b ldr r3, [r7, #16] 80126b0: f423 5300 bic.w r3, r3, #8192 @ 0x2000 80126b4: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 80126b6: 683b ldr r3, [r7, #0] 80126b8: 695b ldr r3, [r3, #20] 80126ba: 011b lsls r3, r3, #4 80126bc: 693a ldr r2, [r7, #16] 80126be: 4313 orrs r3, r2 80126c0: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 80126c2: 683b ldr r3, [r7, #0] 80126c4: 699b ldr r3, [r3, #24] 80126c6: 011b lsls r3, r3, #4 80126c8: 693a ldr r2, [r7, #16] 80126ca: 4313 orrs r3, r2 80126cc: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80126ce: 687b ldr r3, [r7, #4] 80126d0: 693a ldr r2, [r7, #16] 80126d2: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 80126d4: 687b ldr r3, [r7, #4] 80126d6: 68fa ldr r2, [r7, #12] 80126d8: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 80126da: 683b ldr r3, [r7, #0] 80126dc: 685a ldr r2, [r3, #4] 80126de: 687b ldr r3, [r7, #4] 80126e0: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80126e2: 687b ldr r3, [r7, #4] 80126e4: 697a ldr r2, [r7, #20] 80126e6: 621a str r2, [r3, #32] } 80126e8: bf00 nop 80126ea: 371c adds r7, #28 80126ec: 46bd mov sp, r7 80126ee: bc80 pop {r7} 80126f0: 4770 bx lr 80126f2: bf00 nop 80126f4: 40012c00 .word 0x40012c00 080126f8 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80126f8: b480 push {r7} 80126fa: b087 sub sp, #28 80126fc: af00 add r7, sp, #0 80126fe: 6078 str r0, [r7, #4] 8012700: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8012702: 687b ldr r3, [r7, #4] 8012704: 6a1b ldr r3, [r3, #32] 8012706: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8012708: 687b ldr r3, [r7, #4] 801270a: 6a1b ldr r3, [r3, #32] 801270c: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8012710: 687b ldr r3, [r7, #4] 8012712: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8012714: 687b ldr r3, [r7, #4] 8012716: 685b ldr r3, [r3, #4] 8012718: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 801271a: 687b ldr r3, [r7, #4] 801271c: 69db ldr r3, [r3, #28] 801271e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8012720: 68fb ldr r3, [r7, #12] 8012722: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8012726: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8012728: 68fb ldr r3, [r7, #12] 801272a: f423 7340 bic.w r3, r3, #768 @ 0x300 801272e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8012730: 683b ldr r3, [r7, #0] 8012732: 681b ldr r3, [r3, #0] 8012734: 021b lsls r3, r3, #8 8012736: 68fa ldr r2, [r7, #12] 8012738: 4313 orrs r3, r2 801273a: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 801273c: 693b ldr r3, [r7, #16] 801273e: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8012742: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8012744: 683b ldr r3, [r7, #0] 8012746: 689b ldr r3, [r3, #8] 8012748: 031b lsls r3, r3, #12 801274a: 693a ldr r2, [r7, #16] 801274c: 4313 orrs r3, r2 801274e: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8012750: 687b ldr r3, [r7, #4] 8012752: 4a0f ldr r2, [pc, #60] @ (8012790 ) 8012754: 4293 cmp r3, r2 8012756: d109 bne.n 801276c { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8012758: 697b ldr r3, [r7, #20] 801275a: f423 4380 bic.w r3, r3, #16384 @ 0x4000 801275e: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8012760: 683b ldr r3, [r7, #0] 8012762: 695b ldr r3, [r3, #20] 8012764: 019b lsls r3, r3, #6 8012766: 697a ldr r2, [r7, #20] 8012768: 4313 orrs r3, r2 801276a: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 801276c: 687b ldr r3, [r7, #4] 801276e: 697a ldr r2, [r7, #20] 8012770: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8012772: 687b ldr r3, [r7, #4] 8012774: 68fa ldr r2, [r7, #12] 8012776: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8012778: 683b ldr r3, [r7, #0] 801277a: 685a ldr r2, [r3, #4] 801277c: 687b ldr r3, [r7, #4] 801277e: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012780: 687b ldr r3, [r7, #4] 8012782: 693a ldr r2, [r7, #16] 8012784: 621a str r2, [r3, #32] } 8012786: bf00 nop 8012788: 371c adds r7, #28 801278a: 46bd mov sp, r7 801278c: bc80 pop {r7} 801278e: 4770 bx lr 8012790: 40012c00 .word 0x40012c00 08012794 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8012794: b480 push {r7} 8012796: b087 sub sp, #28 8012798: af00 add r7, sp, #0 801279a: 60f8 str r0, [r7, #12] 801279c: 60b9 str r1, [r7, #8] 801279e: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 80127a0: 68fb ldr r3, [r7, #12] 80127a2: 6a1b ldr r3, [r3, #32] 80127a4: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 80127a6: 68fb ldr r3, [r7, #12] 80127a8: 6a1b ldr r3, [r3, #32] 80127aa: f023 0201 bic.w r2, r3, #1 80127ae: 68fb ldr r3, [r7, #12] 80127b0: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 80127b2: 68fb ldr r3, [r7, #12] 80127b4: 699b ldr r3, [r3, #24] 80127b6: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 80127b8: 693b ldr r3, [r7, #16] 80127ba: f023 03f0 bic.w r3, r3, #240 @ 0xf0 80127be: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 80127c0: 687b ldr r3, [r7, #4] 80127c2: 011b lsls r3, r3, #4 80127c4: 693a ldr r2, [r7, #16] 80127c6: 4313 orrs r3, r2 80127c8: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 80127ca: 697b ldr r3, [r7, #20] 80127cc: f023 030a bic.w r3, r3, #10 80127d0: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 80127d2: 697a ldr r2, [r7, #20] 80127d4: 68bb ldr r3, [r7, #8] 80127d6: 4313 orrs r3, r2 80127d8: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 80127da: 68fb ldr r3, [r7, #12] 80127dc: 693a ldr r2, [r7, #16] 80127de: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 80127e0: 68fb ldr r3, [r7, #12] 80127e2: 697a ldr r2, [r7, #20] 80127e4: 621a str r2, [r3, #32] } 80127e6: bf00 nop 80127e8: 371c adds r7, #28 80127ea: 46bd mov sp, r7 80127ec: bc80 pop {r7} 80127ee: 4770 bx lr 080127f0 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 80127f0: b480 push {r7} 80127f2: b087 sub sp, #28 80127f4: af00 add r7, sp, #0 80127f6: 60f8 str r0, [r7, #12] 80127f8: 60b9 str r1, [r7, #8] 80127fa: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 80127fc: 68fb ldr r3, [r7, #12] 80127fe: 6a1b ldr r3, [r3, #32] 8012800: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8012802: 68fb ldr r3, [r7, #12] 8012804: 6a1b ldr r3, [r3, #32] 8012806: f023 0210 bic.w r2, r3, #16 801280a: 68fb ldr r3, [r7, #12] 801280c: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 801280e: 68fb ldr r3, [r7, #12] 8012810: 699b ldr r3, [r3, #24] 8012812: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8012814: 693b ldr r3, [r7, #16] 8012816: f423 4370 bic.w r3, r3, #61440 @ 0xf000 801281a: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 801281c: 687b ldr r3, [r7, #4] 801281e: 031b lsls r3, r3, #12 8012820: 693a ldr r2, [r7, #16] 8012822: 4313 orrs r3, r2 8012824: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8012826: 697b ldr r3, [r7, #20] 8012828: f023 03a0 bic.w r3, r3, #160 @ 0xa0 801282c: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 801282e: 68bb ldr r3, [r7, #8] 8012830: 011b lsls r3, r3, #4 8012832: 697a ldr r2, [r7, #20] 8012834: 4313 orrs r3, r2 8012836: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8012838: 68fb ldr r3, [r7, #12] 801283a: 693a ldr r2, [r7, #16] 801283c: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 801283e: 68fb ldr r3, [r7, #12] 8012840: 697a ldr r2, [r7, #20] 8012842: 621a str r2, [r3, #32] } 8012844: bf00 nop 8012846: 371c adds r7, #28 8012848: 46bd mov sp, r7 801284a: bc80 pop {r7} 801284c: 4770 bx lr 0801284e : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 801284e: b480 push {r7} 8012850: b085 sub sp, #20 8012852: af00 add r7, sp, #0 8012854: 6078 str r0, [r7, #4] 8012856: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8012858: 687b ldr r3, [r7, #4] 801285a: 689b ldr r3, [r3, #8] 801285c: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 801285e: 68fb ldr r3, [r7, #12] 8012860: f023 0370 bic.w r3, r3, #112 @ 0x70 8012864: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8012866: 683a ldr r2, [r7, #0] 8012868: 68fb ldr r3, [r7, #12] 801286a: 4313 orrs r3, r2 801286c: f043 0307 orr.w r3, r3, #7 8012870: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8012872: 687b ldr r3, [r7, #4] 8012874: 68fa ldr r2, [r7, #12] 8012876: 609a str r2, [r3, #8] } 8012878: bf00 nop 801287a: 3714 adds r7, #20 801287c: 46bd mov sp, r7 801287e: bc80 pop {r7} 8012880: 4770 bx lr 08012882 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8012882: b480 push {r7} 8012884: b087 sub sp, #28 8012886: af00 add r7, sp, #0 8012888: 60f8 str r0, [r7, #12] 801288a: 60b9 str r1, [r7, #8] 801288c: 607a str r2, [r7, #4] 801288e: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8012890: 68fb ldr r3, [r7, #12] 8012892: 689b ldr r3, [r3, #8] 8012894: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8012896: 697b ldr r3, [r7, #20] 8012898: f423 437f bic.w r3, r3, #65280 @ 0xff00 801289c: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 801289e: 683b ldr r3, [r7, #0] 80128a0: 021a lsls r2, r3, #8 80128a2: 687b ldr r3, [r7, #4] 80128a4: 431a orrs r2, r3 80128a6: 68bb ldr r3, [r7, #8] 80128a8: 4313 orrs r3, r2 80128aa: 697a ldr r2, [r7, #20] 80128ac: 4313 orrs r3, r2 80128ae: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 80128b0: 68fb ldr r3, [r7, #12] 80128b2: 697a ldr r2, [r7, #20] 80128b4: 609a str r2, [r3, #8] } 80128b6: bf00 nop 80128b8: 371c adds r7, #28 80128ba: 46bd mov sp, r7 80128bc: bc80 pop {r7} 80128be: 4770 bx lr 080128c0 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 80128c0: b480 push {r7} 80128c2: b087 sub sp, #28 80128c4: af00 add r7, sp, #0 80128c6: 60f8 str r0, [r7, #12] 80128c8: 60b9 str r1, [r7, #8] 80128ca: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 80128cc: 68bb ldr r3, [r7, #8] 80128ce: f003 031f and.w r3, r3, #31 80128d2: 2201 movs r2, #1 80128d4: fa02 f303 lsl.w r3, r2, r3 80128d8: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 80128da: 68fb ldr r3, [r7, #12] 80128dc: 6a1a ldr r2, [r3, #32] 80128de: 697b ldr r3, [r7, #20] 80128e0: 43db mvns r3, r3 80128e2: 401a ands r2, r3 80128e4: 68fb ldr r3, [r7, #12] 80128e6: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 80128e8: 68fb ldr r3, [r7, #12] 80128ea: 6a1a ldr r2, [r3, #32] 80128ec: 68bb ldr r3, [r7, #8] 80128ee: f003 031f and.w r3, r3, #31 80128f2: 6879 ldr r1, [r7, #4] 80128f4: fa01 f303 lsl.w r3, r1, r3 80128f8: 431a orrs r2, r3 80128fa: 68fb ldr r3, [r7, #12] 80128fc: 621a str r2, [r3, #32] } 80128fe: bf00 nop 8012900: 371c adds r7, #28 8012902: 46bd mov sp, r7 8012904: bc80 pop {r7} 8012906: 4770 bx lr 08012908 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8012908: b480 push {r7} 801290a: b085 sub sp, #20 801290c: af00 add r7, sp, #0 801290e: 6078 str r0, [r7, #4] 8012910: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8012912: 687b ldr r3, [r7, #4] 8012914: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8012918: 2b01 cmp r3, #1 801291a: d101 bne.n 8012920 801291c: 2302 movs r3, #2 801291e: e04b b.n 80129b8 8012920: 687b ldr r3, [r7, #4] 8012922: 2201 movs r2, #1 8012924: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8012928: 687b ldr r3, [r7, #4] 801292a: 2202 movs r2, #2 801292c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8012930: 687b ldr r3, [r7, #4] 8012932: 681b ldr r3, [r3, #0] 8012934: 685b ldr r3, [r3, #4] 8012936: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8012938: 687b ldr r3, [r7, #4] 801293a: 681b ldr r3, [r3, #0] 801293c: 689b ldr r3, [r3, #8] 801293e: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8012940: 68fb ldr r3, [r7, #12] 8012942: f023 0370 bic.w r3, r3, #112 @ 0x70 8012946: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8012948: 683b ldr r3, [r7, #0] 801294a: 681b ldr r3, [r3, #0] 801294c: 68fa ldr r2, [r7, #12] 801294e: 4313 orrs r3, r2 8012950: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8012952: 687b ldr r3, [r7, #4] 8012954: 681b ldr r3, [r3, #0] 8012956: 68fa ldr r2, [r7, #12] 8012958: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 801295a: 687b ldr r3, [r7, #4] 801295c: 681b ldr r3, [r3, #0] 801295e: 4a19 ldr r2, [pc, #100] @ (80129c4 ) 8012960: 4293 cmp r3, r2 8012962: d013 beq.n 801298c 8012964: 687b ldr r3, [r7, #4] 8012966: 681b ldr r3, [r3, #0] 8012968: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 801296c: d00e beq.n 801298c 801296e: 687b ldr r3, [r7, #4] 8012970: 681b ldr r3, [r3, #0] 8012972: 4a15 ldr r2, [pc, #84] @ (80129c8 ) 8012974: 4293 cmp r3, r2 8012976: d009 beq.n 801298c 8012978: 687b ldr r3, [r7, #4] 801297a: 681b ldr r3, [r3, #0] 801297c: 4a13 ldr r2, [pc, #76] @ (80129cc ) 801297e: 4293 cmp r3, r2 8012980: d004 beq.n 801298c 8012982: 687b ldr r3, [r7, #4] 8012984: 681b ldr r3, [r3, #0] 8012986: 4a12 ldr r2, [pc, #72] @ (80129d0 ) 8012988: 4293 cmp r3, r2 801298a: d10c bne.n 80129a6 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 801298c: 68bb ldr r3, [r7, #8] 801298e: f023 0380 bic.w r3, r3, #128 @ 0x80 8012992: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8012994: 683b ldr r3, [r7, #0] 8012996: 685b ldr r3, [r3, #4] 8012998: 68ba ldr r2, [r7, #8] 801299a: 4313 orrs r3, r2 801299c: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 801299e: 687b ldr r3, [r7, #4] 80129a0: 681b ldr r3, [r3, #0] 80129a2: 68ba ldr r2, [r7, #8] 80129a4: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 80129a6: 687b ldr r3, [r7, #4] 80129a8: 2201 movs r2, #1 80129aa: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 80129ae: 687b ldr r3, [r7, #4] 80129b0: 2200 movs r2, #0 80129b2: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 80129b6: 2300 movs r3, #0 } 80129b8: 4618 mov r0, r3 80129ba: 3714 adds r7, #20 80129bc: 46bd mov sp, r7 80129be: bc80 pop {r7} 80129c0: 4770 bx lr 80129c2: bf00 nop 80129c4: 40012c00 .word 0x40012c00 80129c8: 40000400 .word 0x40000400 80129cc: 40000800 .word 0x40000800 80129d0: 40000c00 .word 0x40000c00 080129d4 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 80129d4: b480 push {r7} 80129d6: b083 sub sp, #12 80129d8: af00 add r7, sp, #0 80129da: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 80129dc: bf00 nop 80129de: 370c adds r7, #12 80129e0: 46bd mov sp, r7 80129e2: bc80 pop {r7} 80129e4: 4770 bx lr 080129e6 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 80129e6: b480 push {r7} 80129e8: b083 sub sp, #12 80129ea: af00 add r7, sp, #0 80129ec: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 80129ee: bf00 nop 80129f0: 370c adds r7, #12 80129f2: 46bd mov sp, r7 80129f4: bc80 pop {r7} 80129f6: 4770 bx lr 080129f8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 80129f8: b580 push {r7, lr} 80129fa: b082 sub sp, #8 80129fc: af00 add r7, sp, #0 80129fe: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8012a00: 687b ldr r3, [r7, #4] 8012a02: 2b00 cmp r3, #0 8012a04: d101 bne.n 8012a0a { return HAL_ERROR; 8012a06: 2301 movs r3, #1 8012a08: e042 b.n 8012a90 assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 8012a0a: 687b ldr r3, [r7, #4] 8012a0c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8012a10: b2db uxtb r3, r3 8012a12: 2b00 cmp r3, #0 8012a14: d106 bne.n 8012a24 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8012a16: 687b ldr r3, [r7, #4] 8012a18: 2200 movs r2, #0 8012a1a: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8012a1e: 6878 ldr r0, [r7, #4] 8012a20: f7fa ff28 bl 800d874 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8012a24: 687b ldr r3, [r7, #4] 8012a26: 2224 movs r2, #36 @ 0x24 8012a28: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8012a2c: 687b ldr r3, [r7, #4] 8012a2e: 681b ldr r3, [r3, #0] 8012a30: 68da ldr r2, [r3, #12] 8012a32: 687b ldr r3, [r7, #4] 8012a34: 681b ldr r3, [r3, #0] 8012a36: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8012a3a: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8012a3c: 6878 ldr r0, [r7, #4] 8012a3e: f000 fee7 bl 8013810 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8012a42: 687b ldr r3, [r7, #4] 8012a44: 681b ldr r3, [r3, #0] 8012a46: 691a ldr r2, [r3, #16] 8012a48: 687b ldr r3, [r7, #4] 8012a4a: 681b ldr r3, [r3, #0] 8012a4c: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8012a50: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8012a52: 687b ldr r3, [r7, #4] 8012a54: 681b ldr r3, [r3, #0] 8012a56: 695a ldr r2, [r3, #20] 8012a58: 687b ldr r3, [r7, #4] 8012a5a: 681b ldr r3, [r3, #0] 8012a5c: f022 022a bic.w r2, r2, #42 @ 0x2a 8012a60: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8012a62: 687b ldr r3, [r7, #4] 8012a64: 681b ldr r3, [r3, #0] 8012a66: 68da ldr r2, [r3, #12] 8012a68: 687b ldr r3, [r7, #4] 8012a6a: 681b ldr r3, [r3, #0] 8012a6c: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8012a70: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012a72: 687b ldr r3, [r7, #4] 8012a74: 2200 movs r2, #0 8012a76: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8012a78: 687b ldr r3, [r7, #4] 8012a7a: 2220 movs r2, #32 8012a7c: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8012a80: 687b ldr r3, [r7, #4] 8012a82: 2220 movs r2, #32 8012a84: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8012a88: 687b ldr r3, [r7, #4] 8012a8a: 2200 movs r2, #0 8012a8c: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8012a8e: 2300 movs r3, #0 } 8012a90: 4618 mov r0, r3 8012a92: 3708 adds r7, #8 8012a94: 46bd mov sp, r7 8012a96: bd80 pop {r7, pc} 08012a98 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) { 8012a98: b580 push {r7, lr} 8012a9a: b082 sub sp, #8 8012a9c: af00 add r7, sp, #0 8012a9e: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8012aa0: 687b ldr r3, [r7, #4] 8012aa2: 2b00 cmp r3, #0 8012aa4: d101 bne.n 8012aaa { return HAL_ERROR; 8012aa6: 2301 movs r3, #1 8012aa8: e024 b.n 8012af4 } /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); huart->gState = HAL_UART_STATE_BUSY; 8012aaa: 687b ldr r3, [r7, #4] 8012aac: 2224 movs r2, #36 @ 0x24 8012aae: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); 8012ab2: 687b ldr r3, [r7, #4] 8012ab4: 681b ldr r3, [r3, #0] 8012ab6: 68da ldr r2, [r3, #12] 8012ab8: 687b ldr r3, [r7, #4] 8012aba: 681b ldr r3, [r3, #0] 8012abc: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8012ac0: 60da str r2, [r3, #12] } /* DeInit the low level hardware */ huart->MspDeInitCallback(huart); #else /* DeInit the low level hardware */ HAL_UART_MspDeInit(huart); 8012ac2: 6878 ldr r0, [r7, #4] 8012ac4: f7fb f820 bl 800db08 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012ac8: 687b ldr r3, [r7, #4] 8012aca: 2200 movs r2, #0 8012acc: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_RESET; 8012ace: 687b ldr r3, [r7, #4] 8012ad0: 2200 movs r2, #0 8012ad2: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_RESET; 8012ad6: 687b ldr r3, [r7, #4] 8012ad8: 2200 movs r2, #0 8012ada: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012ade: 687b ldr r3, [r7, #4] 8012ae0: 2200 movs r2, #0 8012ae2: 631a str r2, [r3, #48] @ 0x30 huart->RxEventType = HAL_UART_RXEVENT_TC; 8012ae4: 687b ldr r3, [r7, #4] 8012ae6: 2200 movs r2, #0 8012ae8: 635a str r2, [r3, #52] @ 0x34 /* Process Unlock */ __HAL_UNLOCK(huart); 8012aea: 687b ldr r3, [r7, #4] 8012aec: 2200 movs r2, #0 8012aee: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_OK; 8012af2: 2300 movs r3, #0 } 8012af4: 4618 mov r0, r3 8012af6: 3708 adds r7, #8 8012af8: 46bd mov sp, r7 8012afa: bd80 pop {r7, pc} 08012afc : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8012afc: b480 push {r7} 8012afe: b085 sub sp, #20 8012b00: af00 add r7, sp, #0 8012b02: 60f8 str r0, [r7, #12] 8012b04: 60b9 str r1, [r7, #8] 8012b06: 4613 mov r3, r2 8012b08: 80fb strh r3, [r7, #6] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8012b0a: 68fb ldr r3, [r7, #12] 8012b0c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8012b10: b2db uxtb r3, r3 8012b12: 2b20 cmp r3, #32 8012b14: d121 bne.n 8012b5a { if ((pData == NULL) || (Size == 0U)) 8012b16: 68bb ldr r3, [r7, #8] 8012b18: 2b00 cmp r3, #0 8012b1a: d002 beq.n 8012b22 8012b1c: 88fb ldrh r3, [r7, #6] 8012b1e: 2b00 cmp r3, #0 8012b20: d101 bne.n 8012b26 { return HAL_ERROR; 8012b22: 2301 movs r3, #1 8012b24: e01a b.n 8012b5c } huart->pTxBuffPtr = pData; 8012b26: 68fb ldr r3, [r7, #12] 8012b28: 68ba ldr r2, [r7, #8] 8012b2a: 621a str r2, [r3, #32] huart->TxXferSize = Size; 8012b2c: 68fb ldr r3, [r7, #12] 8012b2e: 88fa ldrh r2, [r7, #6] 8012b30: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8012b32: 68fb ldr r3, [r7, #12] 8012b34: 88fa ldrh r2, [r7, #6] 8012b36: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 8012b38: 68fb ldr r3, [r7, #12] 8012b3a: 2200 movs r2, #0 8012b3c: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8012b3e: 68fb ldr r3, [r7, #12] 8012b40: 2221 movs r2, #33 @ 0x21 8012b42: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the UART Transmit data register empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); 8012b46: 68fb ldr r3, [r7, #12] 8012b48: 681b ldr r3, [r3, #0] 8012b4a: 68da ldr r2, [r3, #12] 8012b4c: 68fb ldr r3, [r7, #12] 8012b4e: 681b ldr r3, [r3, #0] 8012b50: f042 0280 orr.w r2, r2, #128 @ 0x80 8012b54: 60da str r2, [r3, #12] return HAL_OK; 8012b56: 2300 movs r3, #0 8012b58: e000 b.n 8012b5c } else { return HAL_BUSY; 8012b5a: 2302 movs r3, #2 } } 8012b5c: 4618 mov r0, r3 8012b5e: 3714 adds r7, #20 8012b60: 46bd mov sp, r7 8012b62: bc80 pop {r7} 8012b64: 4770 bx lr 08012b66 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8012b66: b580 push {r7, lr} 8012b68: b08c sub sp, #48 @ 0x30 8012b6a: af00 add r7, sp, #0 8012b6c: 60f8 str r0, [r7, #12] 8012b6e: 60b9 str r1, [r7, #8] 8012b70: 4613 mov r3, r2 8012b72: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8012b74: 68fb ldr r3, [r7, #12] 8012b76: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8012b7a: b2db uxtb r3, r3 8012b7c: 2b20 cmp r3, #32 8012b7e: d14a bne.n 8012c16 { if ((pData == NULL) || (Size == 0U)) 8012b80: 68bb ldr r3, [r7, #8] 8012b82: 2b00 cmp r3, #0 8012b84: d002 beq.n 8012b8c 8012b86: 88fb ldrh r3, [r7, #6] 8012b88: 2b00 cmp r3, #0 8012b8a: d101 bne.n 8012b90 { return HAL_ERROR; 8012b8c: 2301 movs r3, #1 8012b8e: e043 b.n 8012c18 } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8012b90: 68fb ldr r3, [r7, #12] 8012b92: 2201 movs r2, #1 8012b94: 631a str r2, [r3, #48] @ 0x30 huart->RxEventType = HAL_UART_RXEVENT_TC; 8012b96: 68fb ldr r3, [r7, #12] 8012b98: 2200 movs r2, #0 8012b9a: 635a str r2, [r3, #52] @ 0x34 status = UART_Start_Receive_IT(huart, pData, Size); 8012b9c: 88fb ldrh r3, [r7, #6] 8012b9e: 461a mov r2, r3 8012ba0: 68b9 ldr r1, [r7, #8] 8012ba2: 68f8 ldr r0, [r7, #12] 8012ba4: f000 fbff bl 80133a6 8012ba8: 4603 mov r3, r0 8012baa: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check Rx process has been successfully started */ if (status == HAL_OK) 8012bae: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8012bb2: 2b00 cmp r3, #0 8012bb4: d12c bne.n 8012c10 { if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012bb6: 68fb ldr r3, [r7, #12] 8012bb8: 6b1b ldr r3, [r3, #48] @ 0x30 8012bba: 2b01 cmp r3, #1 8012bbc: d125 bne.n 8012c0a { __HAL_UART_CLEAR_IDLEFLAG(huart); 8012bbe: 2300 movs r3, #0 8012bc0: 613b str r3, [r7, #16] 8012bc2: 68fb ldr r3, [r7, #12] 8012bc4: 681b ldr r3, [r3, #0] 8012bc6: 681b ldr r3, [r3, #0] 8012bc8: 613b str r3, [r7, #16] 8012bca: 68fb ldr r3, [r7, #12] 8012bcc: 681b ldr r3, [r3, #0] 8012bce: 685b ldr r3, [r3, #4] 8012bd0: 613b str r3, [r7, #16] 8012bd2: 693b ldr r3, [r7, #16] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012bd4: 68fb ldr r3, [r7, #12] 8012bd6: 681b ldr r3, [r3, #0] 8012bd8: 330c adds r3, #12 8012bda: 61bb str r3, [r7, #24] */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012bdc: 69bb ldr r3, [r7, #24] 8012bde: e853 3f00 ldrex r3, [r3] 8012be2: 617b str r3, [r7, #20] return(result); 8012be4: 697b ldr r3, [r7, #20] 8012be6: f043 0310 orr.w r3, r3, #16 8012bea: 62bb str r3, [r7, #40] @ 0x28 8012bec: 68fb ldr r3, [r7, #12] 8012bee: 681b ldr r3, [r3, #0] 8012bf0: 330c adds r3, #12 8012bf2: 6aba ldr r2, [r7, #40] @ 0x28 8012bf4: 627a str r2, [r7, #36] @ 0x24 8012bf6: 623b str r3, [r7, #32] */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012bf8: 6a39 ldr r1, [r7, #32] 8012bfa: 6a7a ldr r2, [r7, #36] @ 0x24 8012bfc: e841 2300 strex r3, r2, [r1] 8012c00: 61fb str r3, [r7, #28] return(result); 8012c02: 69fb ldr r3, [r7, #28] 8012c04: 2b00 cmp r3, #0 8012c06: d1e5 bne.n 8012bd4 8012c08: e002 b.n 8012c10 { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8012c0a: 2301 movs r3, #1 8012c0c: f887 302f strb.w r3, [r7, #47] @ 0x2f } } return status; 8012c10: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8012c14: e000 b.n 8012c18 } else { return HAL_BUSY; 8012c16: 2302 movs r3, #2 } } 8012c18: 4618 mov r0, r3 8012c1a: 3730 adds r7, #48 @ 0x30 8012c1c: 46bd mov sp, r7 8012c1e: bd80 pop {r7, pc} 08012c20 : * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { 8012c20: b580 push {r7, lr} 8012c22: b0a2 sub sp, #136 @ 0x88 8012c24: af00 add r7, sp, #0 8012c26: 6078 str r0, [r7, #4] uint32_t AbortCplt = 0x01U; 8012c28: 2301 movs r3, #1 8012c2a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); 8012c2e: 687b ldr r3, [r7, #4] 8012c30: 681b ldr r3, [r3, #0] 8012c32: 330c adds r3, #12 8012c34: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012c36: 6e3b ldr r3, [r7, #96] @ 0x60 8012c38: e853 3f00 ldrex r3, [r3] 8012c3c: 65fb str r3, [r7, #92] @ 0x5c return(result); 8012c3e: 6dfb ldr r3, [r7, #92] @ 0x5c 8012c40: f423 73f0 bic.w r3, r3, #480 @ 0x1e0 8012c44: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8012c48: 687b ldr r3, [r7, #4] 8012c4a: 681b ldr r3, [r3, #0] 8012c4c: 330c adds r3, #12 8012c4e: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8012c52: 66fa str r2, [r7, #108] @ 0x6c 8012c54: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012c56: 6eb9 ldr r1, [r7, #104] @ 0x68 8012c58: 6efa ldr r2, [r7, #108] @ 0x6c 8012c5a: e841 2300 strex r3, r2, [r1] 8012c5e: 667b str r3, [r7, #100] @ 0x64 return(result); 8012c60: 6e7b ldr r3, [r7, #100] @ 0x64 8012c62: 2b00 cmp r3, #0 8012c64: d1e3 bne.n 8012c2e ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012c66: 687b ldr r3, [r7, #4] 8012c68: 681b ldr r3, [r3, #0] 8012c6a: 3314 adds r3, #20 8012c6c: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012c6e: 6cfb ldr r3, [r7, #76] @ 0x4c 8012c70: e853 3f00 ldrex r3, [r3] 8012c74: 64bb str r3, [r7, #72] @ 0x48 return(result); 8012c76: 6cbb ldr r3, [r7, #72] @ 0x48 8012c78: f023 0301 bic.w r3, r3, #1 8012c7c: 67fb str r3, [r7, #124] @ 0x7c 8012c7e: 687b ldr r3, [r7, #4] 8012c80: 681b ldr r3, [r3, #0] 8012c82: 3314 adds r3, #20 8012c84: 6ffa ldr r2, [r7, #124] @ 0x7c 8012c86: 65ba str r2, [r7, #88] @ 0x58 8012c88: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012c8a: 6d79 ldr r1, [r7, #84] @ 0x54 8012c8c: 6dba ldr r2, [r7, #88] @ 0x58 8012c8e: e841 2300 strex r3, r2, [r1] 8012c92: 653b str r3, [r7, #80] @ 0x50 return(result); 8012c94: 6d3b ldr r3, [r7, #80] @ 0x50 8012c96: 2b00 cmp r3, #0 8012c98: d1e5 bne.n 8012c66 /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012c9a: 687b ldr r3, [r7, #4] 8012c9c: 6b1b ldr r3, [r3, #48] @ 0x30 8012c9e: 2b01 cmp r3, #1 8012ca0: d119 bne.n 8012cd6 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); 8012ca2: 687b ldr r3, [r7, #4] 8012ca4: 681b ldr r3, [r3, #0] 8012ca6: 330c adds r3, #12 8012ca8: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012caa: 6bbb ldr r3, [r7, #56] @ 0x38 8012cac: e853 3f00 ldrex r3, [r3] 8012cb0: 637b str r3, [r7, #52] @ 0x34 return(result); 8012cb2: 6b7b ldr r3, [r7, #52] @ 0x34 8012cb4: f023 0310 bic.w r3, r3, #16 8012cb8: 67bb str r3, [r7, #120] @ 0x78 8012cba: 687b ldr r3, [r7, #4] 8012cbc: 681b ldr r3, [r3, #0] 8012cbe: 330c adds r3, #12 8012cc0: 6fba ldr r2, [r7, #120] @ 0x78 8012cc2: 647a str r2, [r7, #68] @ 0x44 8012cc4: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012cc6: 6c39 ldr r1, [r7, #64] @ 0x40 8012cc8: 6c7a ldr r2, [r7, #68] @ 0x44 8012cca: e841 2300 strex r3, r2, [r1] 8012cce: 63fb str r3, [r7, #60] @ 0x3c return(result); 8012cd0: 6bfb ldr r3, [r7, #60] @ 0x3c 8012cd2: 2b00 cmp r3, #0 8012cd4: d1e5 bne.n 8012ca2 } /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ if (huart->hdmatx != NULL) 8012cd6: 687b ldr r3, [r7, #4] 8012cd8: 6b9b ldr r3, [r3, #56] @ 0x38 8012cda: 2b00 cmp r3, #0 8012cdc: d00f beq.n 8012cfe { /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. Otherwise, set it to NULL */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) 8012cde: 687b ldr r3, [r7, #4] 8012ce0: 681b ldr r3, [r3, #0] 8012ce2: 695b ldr r3, [r3, #20] 8012ce4: f003 0380 and.w r3, r3, #128 @ 0x80 8012ce8: 2b00 cmp r3, #0 8012cea: d004 beq.n 8012cf6 { huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; 8012cec: 687b ldr r3, [r7, #4] 8012cee: 6b9b ldr r3, [r3, #56] @ 0x38 8012cf0: 4a53 ldr r2, [pc, #332] @ (8012e40 ) 8012cf2: 635a str r2, [r3, #52] @ 0x34 8012cf4: e003 b.n 8012cfe } else { huart->hdmatx->XferAbortCallback = NULL; 8012cf6: 687b ldr r3, [r7, #4] 8012cf8: 6b9b ldr r3, [r3, #56] @ 0x38 8012cfa: 2200 movs r2, #0 8012cfc: 635a str r2, [r3, #52] @ 0x34 } } /* DMA Rx Handle is valid */ if (huart->hdmarx != NULL) 8012cfe: 687b ldr r3, [r7, #4] 8012d00: 6bdb ldr r3, [r3, #60] @ 0x3c 8012d02: 2b00 cmp r3, #0 8012d04: d00f beq.n 8012d26 { /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. Otherwise, set it to NULL */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8012d06: 687b ldr r3, [r7, #4] 8012d08: 681b ldr r3, [r3, #0] 8012d0a: 695b ldr r3, [r3, #20] 8012d0c: f003 0340 and.w r3, r3, #64 @ 0x40 8012d10: 2b00 cmp r3, #0 8012d12: d004 beq.n 8012d1e { huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; 8012d14: 687b ldr r3, [r7, #4] 8012d16: 6bdb ldr r3, [r3, #60] @ 0x3c 8012d18: 4a4a ldr r2, [pc, #296] @ (8012e44 ) 8012d1a: 635a str r2, [r3, #52] @ 0x34 8012d1c: e003 b.n 8012d26 } else { huart->hdmarx->XferAbortCallback = NULL; 8012d1e: 687b ldr r3, [r7, #4] 8012d20: 6bdb ldr r3, [r3, #60] @ 0x3c 8012d22: 2200 movs r2, #0 8012d24: 635a str r2, [r3, #52] @ 0x34 } } /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) 8012d26: 687b ldr r3, [r7, #4] 8012d28: 681b ldr r3, [r3, #0] 8012d2a: 695b ldr r3, [r3, #20] 8012d2c: f003 0380 and.w r3, r3, #128 @ 0x80 8012d30: 2b00 cmp r3, #0 8012d32: d02d beq.n 8012d90 { /* Disable DMA Tx at UART level */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8012d34: 687b ldr r3, [r7, #4] 8012d36: 681b ldr r3, [r3, #0] 8012d38: 3314 adds r3, #20 8012d3a: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012d3c: 6a7b ldr r3, [r7, #36] @ 0x24 8012d3e: e853 3f00 ldrex r3, [r3] 8012d42: 623b str r3, [r7, #32] return(result); 8012d44: 6a3b ldr r3, [r7, #32] 8012d46: f023 0380 bic.w r3, r3, #128 @ 0x80 8012d4a: 677b str r3, [r7, #116] @ 0x74 8012d4c: 687b ldr r3, [r7, #4] 8012d4e: 681b ldr r3, [r3, #0] 8012d50: 3314 adds r3, #20 8012d52: 6f7a ldr r2, [r7, #116] @ 0x74 8012d54: 633a str r2, [r7, #48] @ 0x30 8012d56: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d58: 6af9 ldr r1, [r7, #44] @ 0x2c 8012d5a: 6b3a ldr r2, [r7, #48] @ 0x30 8012d5c: e841 2300 strex r3, r2, [r1] 8012d60: 62bb str r3, [r7, #40] @ 0x28 return(result); 8012d62: 6abb ldr r3, [r7, #40] @ 0x28 8012d64: 2b00 cmp r3, #0 8012d66: d1e5 bne.n 8012d34 /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) 8012d68: 687b ldr r3, [r7, #4] 8012d6a: 6b9b ldr r3, [r3, #56] @ 0x38 8012d6c: 2b00 cmp r3, #0 8012d6e: d00f beq.n 8012d90 { /* UART Tx DMA Abort callback has already been initialised : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA TX */ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) 8012d70: 687b ldr r3, [r7, #4] 8012d72: 6b9b ldr r3, [r3, #56] @ 0x38 8012d74: 4618 mov r0, r3 8012d76: f7fc fe61 bl 800fa3c 8012d7a: 4603 mov r3, r0 8012d7c: 2b00 cmp r3, #0 8012d7e: d004 beq.n 8012d8a { huart->hdmatx->XferAbortCallback = NULL; 8012d80: 687b ldr r3, [r7, #4] 8012d82: 6b9b ldr r3, [r3, #56] @ 0x38 8012d84: 2200 movs r2, #0 8012d86: 635a str r2, [r3, #52] @ 0x34 8012d88: e002 b.n 8012d90 } else { AbortCplt = 0x00U; 8012d8a: 2300 movs r3, #0 8012d8c: f8c7 3084 str.w r3, [r7, #132] @ 0x84 } } } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8012d90: 687b ldr r3, [r7, #4] 8012d92: 681b ldr r3, [r3, #0] 8012d94: 695b ldr r3, [r3, #20] 8012d96: f003 0340 and.w r3, r3, #64 @ 0x40 8012d9a: 2b00 cmp r3, #0 8012d9c: d030 beq.n 8012e00 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8012d9e: 687b ldr r3, [r7, #4] 8012da0: 681b ldr r3, [r3, #0] 8012da2: 3314 adds r3, #20 8012da4: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012da6: 693b ldr r3, [r7, #16] 8012da8: e853 3f00 ldrex r3, [r3] 8012dac: 60fb str r3, [r7, #12] return(result); 8012dae: 68fb ldr r3, [r7, #12] 8012db0: f023 0340 bic.w r3, r3, #64 @ 0x40 8012db4: 673b str r3, [r7, #112] @ 0x70 8012db6: 687b ldr r3, [r7, #4] 8012db8: 681b ldr r3, [r3, #0] 8012dba: 3314 adds r3, #20 8012dbc: 6f3a ldr r2, [r7, #112] @ 0x70 8012dbe: 61fa str r2, [r7, #28] 8012dc0: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012dc2: 69b9 ldr r1, [r7, #24] 8012dc4: 69fa ldr r2, [r7, #28] 8012dc6: e841 2300 strex r3, r2, [r1] 8012dca: 617b str r3, [r7, #20] return(result); 8012dcc: 697b ldr r3, [r7, #20] 8012dce: 2b00 cmp r3, #0 8012dd0: d1e5 bne.n 8012d9e /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) 8012dd2: 687b ldr r3, [r7, #4] 8012dd4: 6bdb ldr r3, [r3, #60] @ 0x3c 8012dd6: 2b00 cmp r3, #0 8012dd8: d012 beq.n 8012e00 { /* UART Rx DMA Abort callback has already been initialised : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8012dda: 687b ldr r3, [r7, #4] 8012ddc: 6bdb ldr r3, [r3, #60] @ 0x3c 8012dde: 4618 mov r0, r3 8012de0: f7fc fe2c bl 800fa3c 8012de4: 4603 mov r3, r0 8012de6: 2b00 cmp r3, #0 8012de8: d007 beq.n 8012dfa { huart->hdmarx->XferAbortCallback = NULL; 8012dea: 687b ldr r3, [r7, #4] 8012dec: 6bdb ldr r3, [r3, #60] @ 0x3c 8012dee: 2200 movs r2, #0 8012df0: 635a str r2, [r3, #52] @ 0x34 AbortCplt = 0x01U; 8012df2: 2301 movs r3, #1 8012df4: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8012df8: e002 b.n 8012e00 } else { AbortCplt = 0x00U; 8012dfa: 2300 movs r3, #0 8012dfc: f8c7 3084 str.w r3, [r7, #132] @ 0x84 } } } /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (AbortCplt == 0x01U) 8012e00: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8012e04: 2b01 cmp r3, #1 8012e06: d116 bne.n 8012e36 { /* Reset Tx and Rx transfer counters */ huart->TxXferCount = 0x00U; 8012e08: 687b ldr r3, [r7, #4] 8012e0a: 2200 movs r2, #0 8012e0c: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 8012e0e: 687b ldr r3, [r7, #4] 8012e10: 2200 movs r2, #0 8012e12: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012e14: 687b ldr r3, [r7, #4] 8012e16: 2200 movs r2, #0 8012e18: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 8012e1a: 687b ldr r3, [r7, #4] 8012e1c: 2220 movs r2, #32 8012e1e: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8012e22: 687b ldr r3, [r7, #4] 8012e24: 2220 movs r2, #32 8012e26: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012e2a: 687b ldr r3, [r7, #4] 8012e2c: 2200 movs r2, #0 8012e2e: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 8012e30: 6878 ldr r0, [r7, #4] 8012e32: f000 faa4 bl 801337e #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8012e36: 2300 movs r3, #0 } 8012e38: 4618 mov r0, r3 8012e3a: 3788 adds r7, #136 @ 0x88 8012e3c: 46bd mov sp, r7 8012e3e: bd80 pop {r7, pc} 8012e40: 08013505 .word 0x08013505 8012e44: 08013565 .word 0x08013565 08012e48 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8012e48: b580 push {r7, lr} 8012e4a: b0ba sub sp, #232 @ 0xe8 8012e4c: af00 add r7, sp, #0 8012e4e: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 8012e50: 687b ldr r3, [r7, #4] 8012e52: 681b ldr r3, [r3, #0] 8012e54: 681b ldr r3, [r3, #0] 8012e56: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8012e5a: 687b ldr r3, [r7, #4] 8012e5c: 681b ldr r3, [r3, #0] 8012e5e: 68db ldr r3, [r3, #12] 8012e60: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8012e64: 687b ldr r3, [r7, #4] 8012e66: 681b ldr r3, [r3, #0] 8012e68: 695b ldr r3, [r3, #20] 8012e6a: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 8012e6e: 2300 movs r3, #0 8012e70: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 8012e74: 2300 movs r3, #0 8012e76: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8012e7a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012e7e: f003 030f and.w r3, r3, #15 8012e82: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 8012e86: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8012e8a: 2b00 cmp r3, #0 8012e8c: d10f bne.n 8012eae { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8012e8e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012e92: f003 0320 and.w r3, r3, #32 8012e96: 2b00 cmp r3, #0 8012e98: d009 beq.n 8012eae 8012e9a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012e9e: f003 0320 and.w r3, r3, #32 8012ea2: 2b00 cmp r3, #0 8012ea4: d003 beq.n 8012eae { UART_Receive_IT(huart); 8012ea6: 6878 ldr r0, [r7, #4] 8012ea8: f000 fbf3 bl 8013692 return; 8012eac: e25b b.n 8013366 } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 8012eae: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8012eb2: 2b00 cmp r3, #0 8012eb4: f000 80de beq.w 8013074 8012eb8: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8012ebc: f003 0301 and.w r3, r3, #1 8012ec0: 2b00 cmp r3, #0 8012ec2: d106 bne.n 8012ed2 || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8012ec4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012ec8: f403 7390 and.w r3, r3, #288 @ 0x120 8012ecc: 2b00 cmp r3, #0 8012ece: f000 80d1 beq.w 8013074 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 8012ed2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012ed6: f003 0301 and.w r3, r3, #1 8012eda: 2b00 cmp r3, #0 8012edc: d00b beq.n 8012ef6 8012ede: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012ee2: f403 7380 and.w r3, r3, #256 @ 0x100 8012ee6: 2b00 cmp r3, #0 8012ee8: d005 beq.n 8012ef6 { huart->ErrorCode |= HAL_UART_ERROR_PE; 8012eea: 687b ldr r3, [r7, #4] 8012eec: 6c5b ldr r3, [r3, #68] @ 0x44 8012eee: f043 0201 orr.w r2, r3, #1 8012ef2: 687b ldr r3, [r7, #4] 8012ef4: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8012ef6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012efa: f003 0304 and.w r3, r3, #4 8012efe: 2b00 cmp r3, #0 8012f00: d00b beq.n 8012f1a 8012f02: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8012f06: f003 0301 and.w r3, r3, #1 8012f0a: 2b00 cmp r3, #0 8012f0c: d005 beq.n 8012f1a { huart->ErrorCode |= HAL_UART_ERROR_NE; 8012f0e: 687b ldr r3, [r7, #4] 8012f10: 6c5b ldr r3, [r3, #68] @ 0x44 8012f12: f043 0202 orr.w r2, r3, #2 8012f16: 687b ldr r3, [r7, #4] 8012f18: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8012f1a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012f1e: f003 0302 and.w r3, r3, #2 8012f22: 2b00 cmp r3, #0 8012f24: d00b beq.n 8012f3e 8012f26: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8012f2a: f003 0301 and.w r3, r3, #1 8012f2e: 2b00 cmp r3, #0 8012f30: d005 beq.n 8012f3e { huart->ErrorCode |= HAL_UART_ERROR_FE; 8012f32: 687b ldr r3, [r7, #4] 8012f34: 6c5b ldr r3, [r3, #68] @ 0x44 8012f36: f043 0204 orr.w r2, r3, #4 8012f3a: 687b ldr r3, [r7, #4] 8012f3c: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 8012f3e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012f42: f003 0308 and.w r3, r3, #8 8012f46: 2b00 cmp r3, #0 8012f48: d011 beq.n 8012f6e 8012f4a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012f4e: f003 0320 and.w r3, r3, #32 8012f52: 2b00 cmp r3, #0 8012f54: d105 bne.n 8012f62 || ((cr3its & USART_CR3_EIE) != RESET))) 8012f56: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8012f5a: f003 0301 and.w r3, r3, #1 8012f5e: 2b00 cmp r3, #0 8012f60: d005 beq.n 8012f6e { huart->ErrorCode |= HAL_UART_ERROR_ORE; 8012f62: 687b ldr r3, [r7, #4] 8012f64: 6c5b ldr r3, [r3, #68] @ 0x44 8012f66: f043 0208 orr.w r2, r3, #8 8012f6a: 687b ldr r3, [r7, #4] 8012f6c: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8012f6e: 687b ldr r3, [r7, #4] 8012f70: 6c5b ldr r3, [r3, #68] @ 0x44 8012f72: 2b00 cmp r3, #0 8012f74: f000 81f2 beq.w 801335c { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8012f78: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012f7c: f003 0320 and.w r3, r3, #32 8012f80: 2b00 cmp r3, #0 8012f82: d008 beq.n 8012f96 8012f84: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012f88: f003 0320 and.w r3, r3, #32 8012f8c: 2b00 cmp r3, #0 8012f8e: d002 beq.n 8012f96 { UART_Receive_IT(huart); 8012f90: 6878 ldr r0, [r7, #4] 8012f92: f000 fb7e bl 8013692 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8012f96: 687b ldr r3, [r7, #4] 8012f98: 681b ldr r3, [r3, #0] 8012f9a: 695b ldr r3, [r3, #20] 8012f9c: f003 0340 and.w r3, r3, #64 @ 0x40 8012fa0: 2b00 cmp r3, #0 8012fa2: bf14 ite ne 8012fa4: 2301 movne r3, #1 8012fa6: 2300 moveq r3, #0 8012fa8: b2db uxtb r3, r3 8012faa: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8012fae: 687b ldr r3, [r7, #4] 8012fb0: 6c5b ldr r3, [r3, #68] @ 0x44 8012fb2: f003 0308 and.w r3, r3, #8 8012fb6: 2b00 cmp r3, #0 8012fb8: d103 bne.n 8012fc2 8012fba: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8012fbe: 2b00 cmp r3, #0 8012fc0: d04f beq.n 8013062 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8012fc2: 6878 ldr r0, [r7, #4] 8012fc4: f000 fa28 bl 8013418 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8012fc8: 687b ldr r3, [r7, #4] 8012fca: 681b ldr r3, [r3, #0] 8012fcc: 695b ldr r3, [r3, #20] 8012fce: f003 0340 and.w r3, r3, #64 @ 0x40 8012fd2: 2b00 cmp r3, #0 8012fd4: d041 beq.n 801305a { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8012fd6: 687b ldr r3, [r7, #4] 8012fd8: 681b ldr r3, [r3, #0] 8012fda: 3314 adds r3, #20 8012fdc: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012fe0: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8012fe4: e853 3f00 ldrex r3, [r3] 8012fe8: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8012fec: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8012ff0: f023 0340 bic.w r3, r3, #64 @ 0x40 8012ff4: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8012ff8: 687b ldr r3, [r7, #4] 8012ffa: 681b ldr r3, [r3, #0] 8012ffc: 3314 adds r3, #20 8012ffe: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8013002: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8013006: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801300a: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 801300e: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8013012: e841 2300 strex r3, r2, [r1] 8013016: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 801301a: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 801301e: 2b00 cmp r3, #0 8013020: d1d9 bne.n 8012fd6 /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 8013022: 687b ldr r3, [r7, #4] 8013024: 6bdb ldr r3, [r3, #60] @ 0x3c 8013026: 2b00 cmp r3, #0 8013028: d013 beq.n 8013052 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 801302a: 687b ldr r3, [r7, #4] 801302c: 6bdb ldr r3, [r3, #60] @ 0x3c 801302e: 4a7e ldr r2, [pc, #504] @ (8013228 ) 8013030: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8013032: 687b ldr r3, [r7, #4] 8013034: 6bdb ldr r3, [r3, #60] @ 0x3c 8013036: 4618 mov r0, r3 8013038: f7fc fd00 bl 800fa3c 801303c: 4603 mov r3, r0 801303e: 2b00 cmp r3, #0 8013040: d016 beq.n 8013070 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8013042: 687b ldr r3, [r7, #4] 8013044: 6bdb ldr r3, [r3, #60] @ 0x3c 8013046: 6b5b ldr r3, [r3, #52] @ 0x34 8013048: 687a ldr r2, [r7, #4] 801304a: 6bd2 ldr r2, [r2, #60] @ 0x3c 801304c: 4610 mov r0, r2 801304e: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013050: e00e b.n 8013070 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013052: 6878 ldr r0, [r7, #4] 8013054: f7f8 fcdc bl 800ba10 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013058: e00a b.n 8013070 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 801305a: 6878 ldr r0, [r7, #4] 801305c: f7f8 fcd8 bl 800ba10 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013060: e006 b.n 8013070 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013062: 6878 ldr r0, [r7, #4] 8013064: f7f8 fcd4 bl 800ba10 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8013068: 687b ldr r3, [r7, #4] 801306a: 2200 movs r2, #0 801306c: 645a str r2, [r3, #68] @ 0x44 } } return; 801306e: e175 b.n 801335c if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013070: bf00 nop return; 8013072: e173 b.n 801335c } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013074: 687b ldr r3, [r7, #4] 8013076: 6b1b ldr r3, [r3, #48] @ 0x30 8013078: 2b01 cmp r3, #1 801307a: f040 814f bne.w 801331c && ((isrflags & USART_SR_IDLE) != 0U) 801307e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013082: f003 0310 and.w r3, r3, #16 8013086: 2b00 cmp r3, #0 8013088: f000 8148 beq.w 801331c && ((cr1its & USART_SR_IDLE) != 0U)) 801308c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013090: f003 0310 and.w r3, r3, #16 8013094: 2b00 cmp r3, #0 8013096: f000 8141 beq.w 801331c { __HAL_UART_CLEAR_IDLEFLAG(huart); 801309a: 2300 movs r3, #0 801309c: 60bb str r3, [r7, #8] 801309e: 687b ldr r3, [r7, #4] 80130a0: 681b ldr r3, [r3, #0] 80130a2: 681b ldr r3, [r3, #0] 80130a4: 60bb str r3, [r7, #8] 80130a6: 687b ldr r3, [r7, #4] 80130a8: 681b ldr r3, [r3, #0] 80130aa: 685b ldr r3, [r3, #4] 80130ac: 60bb str r3, [r7, #8] 80130ae: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80130b0: 687b ldr r3, [r7, #4] 80130b2: 681b ldr r3, [r3, #0] 80130b4: 695b ldr r3, [r3, #20] 80130b6: f003 0340 and.w r3, r3, #64 @ 0x40 80130ba: 2b00 cmp r3, #0 80130bc: f000 80b6 beq.w 801322c { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 80130c0: 687b ldr r3, [r7, #4] 80130c2: 6bdb ldr r3, [r3, #60] @ 0x3c 80130c4: 681b ldr r3, [r3, #0] 80130c6: 685b ldr r3, [r3, #4] 80130c8: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 80130cc: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 80130d0: 2b00 cmp r3, #0 80130d2: f000 8145 beq.w 8013360 && (nb_remaining_rx_data < huart->RxXferSize)) 80130d6: 687b ldr r3, [r7, #4] 80130d8: 8d9b ldrh r3, [r3, #44] @ 0x2c 80130da: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80130de: 429a cmp r2, r3 80130e0: f080 813e bcs.w 8013360 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 80130e4: 687b ldr r3, [r7, #4] 80130e6: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80130ea: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 80130ec: 687b ldr r3, [r7, #4] 80130ee: 6bdb ldr r3, [r3, #60] @ 0x3c 80130f0: 699b ldr r3, [r3, #24] 80130f2: 2b20 cmp r3, #32 80130f4: f000 8088 beq.w 8013208 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80130f8: 687b ldr r3, [r7, #4] 80130fa: 681b ldr r3, [r3, #0] 80130fc: 330c adds r3, #12 80130fe: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013102: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8013106: e853 3f00 ldrex r3, [r3] 801310a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 801310e: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8013112: f423 7380 bic.w r3, r3, #256 @ 0x100 8013116: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 801311a: 687b ldr r3, [r7, #4] 801311c: 681b ldr r3, [r3, #0] 801311e: 330c adds r3, #12 8013120: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 8013124: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8013128: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801312c: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8013130: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8013134: e841 2300 strex r3, r2, [r1] 8013138: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 801313c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8013140: 2b00 cmp r3, #0 8013142: d1d9 bne.n 80130f8 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013144: 687b ldr r3, [r7, #4] 8013146: 681b ldr r3, [r3, #0] 8013148: 3314 adds r3, #20 801314a: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801314c: 6f7b ldr r3, [r7, #116] @ 0x74 801314e: e853 3f00 ldrex r3, [r3] 8013152: 673b str r3, [r7, #112] @ 0x70 return(result); 8013154: 6f3b ldr r3, [r7, #112] @ 0x70 8013156: f023 0301 bic.w r3, r3, #1 801315a: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 801315e: 687b ldr r3, [r7, #4] 8013160: 681b ldr r3, [r3, #0] 8013162: 3314 adds r3, #20 8013164: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8013168: f8c7 2080 str.w r2, [r7, #128] @ 0x80 801316c: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801316e: 6ff9 ldr r1, [r7, #124] @ 0x7c 8013170: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8013174: e841 2300 strex r3, r2, [r1] 8013178: 67bb str r3, [r7, #120] @ 0x78 return(result); 801317a: 6fbb ldr r3, [r7, #120] @ 0x78 801317c: 2b00 cmp r3, #0 801317e: d1e1 bne.n 8013144 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8013180: 687b ldr r3, [r7, #4] 8013182: 681b ldr r3, [r3, #0] 8013184: 3314 adds r3, #20 8013186: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013188: 6e3b ldr r3, [r7, #96] @ 0x60 801318a: e853 3f00 ldrex r3, [r3] 801318e: 65fb str r3, [r7, #92] @ 0x5c return(result); 8013190: 6dfb ldr r3, [r7, #92] @ 0x5c 8013192: f023 0340 bic.w r3, r3, #64 @ 0x40 8013196: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 801319a: 687b ldr r3, [r7, #4] 801319c: 681b ldr r3, [r3, #0] 801319e: 3314 adds r3, #20 80131a0: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 80131a4: 66fa str r2, [r7, #108] @ 0x6c 80131a6: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80131a8: 6eb9 ldr r1, [r7, #104] @ 0x68 80131aa: 6efa ldr r2, [r7, #108] @ 0x6c 80131ac: e841 2300 strex r3, r2, [r1] 80131b0: 667b str r3, [r7, #100] @ 0x64 return(result); 80131b2: 6e7b ldr r3, [r7, #100] @ 0x64 80131b4: 2b00 cmp r3, #0 80131b6: d1e3 bne.n 8013180 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80131b8: 687b ldr r3, [r7, #4] 80131ba: 2220 movs r2, #32 80131bc: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80131c0: 687b ldr r3, [r7, #4] 80131c2: 2200 movs r2, #0 80131c4: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80131c6: 687b ldr r3, [r7, #4] 80131c8: 681b ldr r3, [r3, #0] 80131ca: 330c adds r3, #12 80131cc: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80131ce: 6cfb ldr r3, [r7, #76] @ 0x4c 80131d0: e853 3f00 ldrex r3, [r3] 80131d4: 64bb str r3, [r7, #72] @ 0x48 return(result); 80131d6: 6cbb ldr r3, [r7, #72] @ 0x48 80131d8: f023 0310 bic.w r3, r3, #16 80131dc: f8c7 30ac str.w r3, [r7, #172] @ 0xac 80131e0: 687b ldr r3, [r7, #4] 80131e2: 681b ldr r3, [r3, #0] 80131e4: 330c adds r3, #12 80131e6: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 80131ea: 65ba str r2, [r7, #88] @ 0x58 80131ec: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80131ee: 6d79 ldr r1, [r7, #84] @ 0x54 80131f0: 6dba ldr r2, [r7, #88] @ 0x58 80131f2: e841 2300 strex r3, r2, [r1] 80131f6: 653b str r3, [r7, #80] @ 0x50 return(result); 80131f8: 6d3b ldr r3, [r7, #80] @ 0x50 80131fa: 2b00 cmp r3, #0 80131fc: d1e3 bne.n 80131c6 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 80131fe: 687b ldr r3, [r7, #4] 8013200: 6bdb ldr r3, [r3, #60] @ 0x3c 8013202: 4618 mov r0, r3 8013204: f7fc fbde bl 800f9c4 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8013208: 687b ldr r3, [r7, #4] 801320a: 2202 movs r2, #2 801320c: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 801320e: 687b ldr r3, [r7, #4] 8013210: 8d9a ldrh r2, [r3, #44] @ 0x2c 8013212: 687b ldr r3, [r7, #4] 8013214: 8ddb ldrh r3, [r3, #46] @ 0x2e 8013216: b29b uxth r3, r3 8013218: 1ad3 subs r3, r2, r3 801321a: b29b uxth r3, r3 801321c: 4619 mov r1, r3 801321e: 6878 ldr r0, [r7, #4] 8013220: f7f9 fa44 bl 800c6ac #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8013224: e09c b.n 8013360 8013226: bf00 nop 8013228: 080134dd .word 0x080134dd else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 801322c: 687b ldr r3, [r7, #4] 801322e: 8d9a ldrh r2, [r3, #44] @ 0x2c 8013230: 687b ldr r3, [r7, #4] 8013232: 8ddb ldrh r3, [r3, #46] @ 0x2e 8013234: b29b uxth r3, r3 8013236: 1ad3 subs r3, r2, r3 8013238: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 801323c: 687b ldr r3, [r7, #4] 801323e: 8ddb ldrh r3, [r3, #46] @ 0x2e 8013240: b29b uxth r3, r3 8013242: 2b00 cmp r3, #0 8013244: f000 808e beq.w 8013364 && (nb_rx_data > 0U)) 8013248: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 801324c: 2b00 cmp r3, #0 801324e: f000 8089 beq.w 8013364 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8013252: 687b ldr r3, [r7, #4] 8013254: 681b ldr r3, [r3, #0] 8013256: 330c adds r3, #12 8013258: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801325a: 6bbb ldr r3, [r7, #56] @ 0x38 801325c: e853 3f00 ldrex r3, [r3] 8013260: 637b str r3, [r7, #52] @ 0x34 return(result); 8013262: 6b7b ldr r3, [r7, #52] @ 0x34 8013264: f423 7390 bic.w r3, r3, #288 @ 0x120 8013268: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 801326c: 687b ldr r3, [r7, #4] 801326e: 681b ldr r3, [r3, #0] 8013270: 330c adds r3, #12 8013272: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 8013276: 647a str r2, [r7, #68] @ 0x44 8013278: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801327a: 6c39 ldr r1, [r7, #64] @ 0x40 801327c: 6c7a ldr r2, [r7, #68] @ 0x44 801327e: e841 2300 strex r3, r2, [r1] 8013282: 63fb str r3, [r7, #60] @ 0x3c return(result); 8013284: 6bfb ldr r3, [r7, #60] @ 0x3c 8013286: 2b00 cmp r3, #0 8013288: d1e3 bne.n 8013252 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 801328a: 687b ldr r3, [r7, #4] 801328c: 681b ldr r3, [r3, #0] 801328e: 3314 adds r3, #20 8013290: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013292: 6a7b ldr r3, [r7, #36] @ 0x24 8013294: e853 3f00 ldrex r3, [r3] 8013298: 623b str r3, [r7, #32] return(result); 801329a: 6a3b ldr r3, [r7, #32] 801329c: f023 0301 bic.w r3, r3, #1 80132a0: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 80132a4: 687b ldr r3, [r7, #4] 80132a6: 681b ldr r3, [r3, #0] 80132a8: 3314 adds r3, #20 80132aa: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 80132ae: 633a str r2, [r7, #48] @ 0x30 80132b0: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80132b2: 6af9 ldr r1, [r7, #44] @ 0x2c 80132b4: 6b3a ldr r2, [r7, #48] @ 0x30 80132b6: e841 2300 strex r3, r2, [r1] 80132ba: 62bb str r3, [r7, #40] @ 0x28 return(result); 80132bc: 6abb ldr r3, [r7, #40] @ 0x28 80132be: 2b00 cmp r3, #0 80132c0: d1e3 bne.n 801328a /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80132c2: 687b ldr r3, [r7, #4] 80132c4: 2220 movs r2, #32 80132c6: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80132ca: 687b ldr r3, [r7, #4] 80132cc: 2200 movs r2, #0 80132ce: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80132d0: 687b ldr r3, [r7, #4] 80132d2: 681b ldr r3, [r3, #0] 80132d4: 330c adds r3, #12 80132d6: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80132d8: 693b ldr r3, [r7, #16] 80132da: e853 3f00 ldrex r3, [r3] 80132de: 60fb str r3, [r7, #12] return(result); 80132e0: 68fb ldr r3, [r7, #12] 80132e2: f023 0310 bic.w r3, r3, #16 80132e6: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 80132ea: 687b ldr r3, [r7, #4] 80132ec: 681b ldr r3, [r3, #0] 80132ee: 330c adds r3, #12 80132f0: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 80132f4: 61fa str r2, [r7, #28] 80132f6: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80132f8: 69b9 ldr r1, [r7, #24] 80132fa: 69fa ldr r2, [r7, #28] 80132fc: e841 2300 strex r3, r2, [r1] 8013300: 617b str r3, [r7, #20] return(result); 8013302: 697b ldr r3, [r7, #20] 8013304: 2b00 cmp r3, #0 8013306: d1e3 bne.n 80132d0 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8013308: 687b ldr r3, [r7, #4] 801330a: 2202 movs r2, #2 801330c: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 801330e: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8013312: 4619 mov r1, r3 8013314: 6878 ldr r0, [r7, #4] 8013316: f7f9 f9c9 bl 800c6ac #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 801331a: e023 b.n 8013364 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 801331c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013320: f003 0380 and.w r3, r3, #128 @ 0x80 8013324: 2b00 cmp r3, #0 8013326: d009 beq.n 801333c 8013328: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801332c: f003 0380 and.w r3, r3, #128 @ 0x80 8013330: 2b00 cmp r3, #0 8013332: d003 beq.n 801333c { UART_Transmit_IT(huart); 8013334: 6878 ldr r0, [r7, #4] 8013336: f000 f945 bl 80135c4 return; 801333a: e014 b.n 8013366 } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 801333c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013340: f003 0340 and.w r3, r3, #64 @ 0x40 8013344: 2b00 cmp r3, #0 8013346: d00e beq.n 8013366 8013348: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801334c: f003 0340 and.w r3, r3, #64 @ 0x40 8013350: 2b00 cmp r3, #0 8013352: d008 beq.n 8013366 { UART_EndTransmit_IT(huart); 8013354: 6878 ldr r0, [r7, #4] 8013356: f000 f984 bl 8013662 return; 801335a: e004 b.n 8013366 return; 801335c: bf00 nop 801335e: e002 b.n 8013366 return; 8013360: bf00 nop 8013362: e000 b.n 8013366 return; 8013364: bf00 nop } } 8013366: 37e8 adds r7, #232 @ 0xe8 8013368: 46bd mov sp, r7 801336a: bd80 pop {r7, pc} 0801336c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 801336c: b480 push {r7} 801336e: b083 sub sp, #12 8013370: af00 add r7, sp, #0 8013372: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback could be implemented in the user file */ } 8013374: bf00 nop 8013376: 370c adds r7, #12 8013378: 46bd mov sp, r7 801337a: bc80 pop {r7} 801337c: 4770 bx lr 0801337e : * @brief UART Abort Complete callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) { 801337e: b480 push {r7} 8013380: b083 sub sp, #12 8013382: af00 add r7, sp, #0 8013384: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_AbortCpltCallback can be implemented in the user file. */ } 8013386: bf00 nop 8013388: 370c adds r7, #12 801338a: 46bd mov sp, r7 801338c: bc80 pop {r7} 801338e: 4770 bx lr 08013390 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. * @retval UART Error Code */ uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) { 8013390: b480 push {r7} 8013392: b083 sub sp, #12 8013394: af00 add r7, sp, #0 8013396: 6078 str r0, [r7, #4] return huart->ErrorCode; 8013398: 687b ldr r3, [r7, #4] 801339a: 6c5b ldr r3, [r3, #68] @ 0x44 } 801339c: 4618 mov r0, r3 801339e: 370c adds r7, #12 80133a0: 46bd mov sp, r7 80133a2: bc80 pop {r7} 80133a4: 4770 bx lr 080133a6 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80133a6: b480 push {r7} 80133a8: b085 sub sp, #20 80133aa: af00 add r7, sp, #0 80133ac: 60f8 str r0, [r7, #12] 80133ae: 60b9 str r1, [r7, #8] 80133b0: 4613 mov r3, r2 80133b2: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 80133b4: 68fb ldr r3, [r7, #12] 80133b6: 68ba ldr r2, [r7, #8] 80133b8: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 80133ba: 68fb ldr r3, [r7, #12] 80133bc: 88fa ldrh r2, [r7, #6] 80133be: 859a strh r2, [r3, #44] @ 0x2c huart->RxXferCount = Size; 80133c0: 68fb ldr r3, [r7, #12] 80133c2: 88fa ldrh r2, [r7, #6] 80133c4: 85da strh r2, [r3, #46] @ 0x2e huart->ErrorCode = HAL_UART_ERROR_NONE; 80133c6: 68fb ldr r3, [r7, #12] 80133c8: 2200 movs r2, #0 80133ca: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 80133cc: 68fb ldr r3, [r7, #12] 80133ce: 2222 movs r2, #34 @ 0x22 80133d0: f883 2042 strb.w r2, [r3, #66] @ 0x42 if (huart->Init.Parity != UART_PARITY_NONE) 80133d4: 68fb ldr r3, [r7, #12] 80133d6: 691b ldr r3, [r3, #16] 80133d8: 2b00 cmp r3, #0 80133da: d007 beq.n 80133ec { /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); 80133dc: 68fb ldr r3, [r7, #12] 80133de: 681b ldr r3, [r3, #0] 80133e0: 68da ldr r2, [r3, #12] 80133e2: 68fb ldr r3, [r7, #12] 80133e4: 681b ldr r3, [r3, #0] 80133e6: f442 7280 orr.w r2, r2, #256 @ 0x100 80133ea: 60da str r2, [r3, #12] } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); 80133ec: 68fb ldr r3, [r7, #12] 80133ee: 681b ldr r3, [r3, #0] 80133f0: 695a ldr r2, [r3, #20] 80133f2: 68fb ldr r3, [r7, #12] 80133f4: 681b ldr r3, [r3, #0] 80133f6: f042 0201 orr.w r2, r2, #1 80133fa: 615a str r2, [r3, #20] /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); 80133fc: 68fb ldr r3, [r7, #12] 80133fe: 681b ldr r3, [r3, #0] 8013400: 68da ldr r2, [r3, #12] 8013402: 68fb ldr r3, [r7, #12] 8013404: 681b ldr r3, [r3, #0] 8013406: f042 0220 orr.w r2, r2, #32 801340a: 60da str r2, [r3, #12] return HAL_OK; 801340c: 2300 movs r3, #0 } 801340e: 4618 mov r0, r3 8013410: 3714 adds r7, #20 8013412: 46bd mov sp, r7 8013414: bc80 pop {r7} 8013416: 4770 bx lr 08013418 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8013418: b480 push {r7} 801341a: b095 sub sp, #84 @ 0x54 801341c: af00 add r7, sp, #0 801341e: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8013420: 687b ldr r3, [r7, #4] 8013422: 681b ldr r3, [r3, #0] 8013424: 330c adds r3, #12 8013426: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013428: 6b7b ldr r3, [r7, #52] @ 0x34 801342a: e853 3f00 ldrex r3, [r3] 801342e: 633b str r3, [r7, #48] @ 0x30 return(result); 8013430: 6b3b ldr r3, [r7, #48] @ 0x30 8013432: f423 7390 bic.w r3, r3, #288 @ 0x120 8013436: 64fb str r3, [r7, #76] @ 0x4c 8013438: 687b ldr r3, [r7, #4] 801343a: 681b ldr r3, [r3, #0] 801343c: 330c adds r3, #12 801343e: 6cfa ldr r2, [r7, #76] @ 0x4c 8013440: 643a str r2, [r7, #64] @ 0x40 8013442: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013444: 6bf9 ldr r1, [r7, #60] @ 0x3c 8013446: 6c3a ldr r2, [r7, #64] @ 0x40 8013448: e841 2300 strex r3, r2, [r1] 801344c: 63bb str r3, [r7, #56] @ 0x38 return(result); 801344e: 6bbb ldr r3, [r7, #56] @ 0x38 8013450: 2b00 cmp r3, #0 8013452: d1e5 bne.n 8013420 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013454: 687b ldr r3, [r7, #4] 8013456: 681b ldr r3, [r3, #0] 8013458: 3314 adds r3, #20 801345a: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801345c: 6a3b ldr r3, [r7, #32] 801345e: e853 3f00 ldrex r3, [r3] 8013462: 61fb str r3, [r7, #28] return(result); 8013464: 69fb ldr r3, [r7, #28] 8013466: f023 0301 bic.w r3, r3, #1 801346a: 64bb str r3, [r7, #72] @ 0x48 801346c: 687b ldr r3, [r7, #4] 801346e: 681b ldr r3, [r3, #0] 8013470: 3314 adds r3, #20 8013472: 6cba ldr r2, [r7, #72] @ 0x48 8013474: 62fa str r2, [r7, #44] @ 0x2c 8013476: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013478: 6ab9 ldr r1, [r7, #40] @ 0x28 801347a: 6afa ldr r2, [r7, #44] @ 0x2c 801347c: e841 2300 strex r3, r2, [r1] 8013480: 627b str r3, [r7, #36] @ 0x24 return(result); 8013482: 6a7b ldr r3, [r7, #36] @ 0x24 8013484: 2b00 cmp r3, #0 8013486: d1e5 bne.n 8013454 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013488: 687b ldr r3, [r7, #4] 801348a: 6b1b ldr r3, [r3, #48] @ 0x30 801348c: 2b01 cmp r3, #1 801348e: d119 bne.n 80134c4 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013490: 687b ldr r3, [r7, #4] 8013492: 681b ldr r3, [r3, #0] 8013494: 330c adds r3, #12 8013496: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013498: 68fb ldr r3, [r7, #12] 801349a: e853 3f00 ldrex r3, [r3] 801349e: 60bb str r3, [r7, #8] return(result); 80134a0: 68bb ldr r3, [r7, #8] 80134a2: f023 0310 bic.w r3, r3, #16 80134a6: 647b str r3, [r7, #68] @ 0x44 80134a8: 687b ldr r3, [r7, #4] 80134aa: 681b ldr r3, [r3, #0] 80134ac: 330c adds r3, #12 80134ae: 6c7a ldr r2, [r7, #68] @ 0x44 80134b0: 61ba str r2, [r7, #24] 80134b2: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80134b4: 6979 ldr r1, [r7, #20] 80134b6: 69ba ldr r2, [r7, #24] 80134b8: e841 2300 strex r3, r2, [r1] 80134bc: 613b str r3, [r7, #16] return(result); 80134be: 693b ldr r3, [r7, #16] 80134c0: 2b00 cmp r3, #0 80134c2: d1e5 bne.n 8013490 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80134c4: 687b ldr r3, [r7, #4] 80134c6: 2220 movs r2, #32 80134c8: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80134cc: 687b ldr r3, [r7, #4] 80134ce: 2200 movs r2, #0 80134d0: 631a str r2, [r3, #48] @ 0x30 } 80134d2: bf00 nop 80134d4: 3754 adds r7, #84 @ 0x54 80134d6: 46bd mov sp, r7 80134d8: bc80 pop {r7} 80134da: 4770 bx lr 080134dc : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 80134dc: b580 push {r7, lr} 80134de: b084 sub sp, #16 80134e0: af00 add r7, sp, #0 80134e2: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80134e4: 687b ldr r3, [r7, #4] 80134e6: 6a5b ldr r3, [r3, #36] @ 0x24 80134e8: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 80134ea: 68fb ldr r3, [r7, #12] 80134ec: 2200 movs r2, #0 80134ee: 85da strh r2, [r3, #46] @ 0x2e huart->TxXferCount = 0x00U; 80134f0: 68fb ldr r3, [r7, #12] 80134f2: 2200 movs r2, #0 80134f4: 84da strh r2, [r3, #38] @ 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80134f6: 68f8 ldr r0, [r7, #12] 80134f8: f7f8 fa8a bl 800ba10 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80134fc: bf00 nop 80134fe: 3710 adds r7, #16 8013500: 46bd mov sp, r7 8013502: bd80 pop {r7, pc} 08013504 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { 8013504: b580 push {r7, lr} 8013506: b084 sub sp, #16 8013508: af00 add r7, sp, #0 801350a: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 801350c: 687b ldr r3, [r7, #4] 801350e: 6a5b ldr r3, [r3, #36] @ 0x24 8013510: 60fb str r3, [r7, #12] huart->hdmatx->XferAbortCallback = NULL; 8013512: 68fb ldr r3, [r7, #12] 8013514: 6b9b ldr r3, [r3, #56] @ 0x38 8013516: 2200 movs r2, #0 8013518: 635a str r2, [r3, #52] @ 0x34 /* Check if an Abort process is still ongoing */ if (huart->hdmarx != NULL) 801351a: 68fb ldr r3, [r7, #12] 801351c: 6bdb ldr r3, [r3, #60] @ 0x3c 801351e: 2b00 cmp r3, #0 8013520: d004 beq.n 801352c { if (huart->hdmarx->XferAbortCallback != NULL) 8013522: 68fb ldr r3, [r7, #12] 8013524: 6bdb ldr r3, [r3, #60] @ 0x3c 8013526: 6b5b ldr r3, [r3, #52] @ 0x34 8013528: 2b00 cmp r3, #0 801352a: d117 bne.n 801355c return; } } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ huart->TxXferCount = 0x00U; 801352c: 68fb ldr r3, [r7, #12] 801352e: 2200 movs r2, #0 8013530: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 8013532: 68fb ldr r3, [r7, #12] 8013534: 2200 movs r2, #0 8013536: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8013538: 68fb ldr r3, [r7, #12] 801353a: 2200 movs r2, #0 801353c: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 801353e: 68fb ldr r3, [r7, #12] 8013540: 2220 movs r2, #32 8013542: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8013546: 68fb ldr r3, [r7, #12] 8013548: 2220 movs r2, #32 801354a: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801354e: 68fb ldr r3, [r7, #12] 8013550: 2200 movs r2, #0 8013552: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 8013554: 68f8 ldr r0, [r7, #12] 8013556: f7ff ff12 bl 801337e 801355a: e000 b.n 801355e return; 801355c: bf00 nop #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 801355e: 3710 adds r7, #16 8013560: 46bd mov sp, r7 8013562: bd80 pop {r7, pc} 08013564 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { 8013564: b580 push {r7, lr} 8013566: b084 sub sp, #16 8013568: af00 add r7, sp, #0 801356a: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 801356c: 687b ldr r3, [r7, #4] 801356e: 6a5b ldr r3, [r3, #36] @ 0x24 8013570: 60fb str r3, [r7, #12] huart->hdmarx->XferAbortCallback = NULL; 8013572: 68fb ldr r3, [r7, #12] 8013574: 6bdb ldr r3, [r3, #60] @ 0x3c 8013576: 2200 movs r2, #0 8013578: 635a str r2, [r3, #52] @ 0x34 /* Check if an Abort process is still ongoing */ if (huart->hdmatx != NULL) 801357a: 68fb ldr r3, [r7, #12] 801357c: 6b9b ldr r3, [r3, #56] @ 0x38 801357e: 2b00 cmp r3, #0 8013580: d004 beq.n 801358c { if (huart->hdmatx->XferAbortCallback != NULL) 8013582: 68fb ldr r3, [r7, #12] 8013584: 6b9b ldr r3, [r3, #56] @ 0x38 8013586: 6b5b ldr r3, [r3, #52] @ 0x34 8013588: 2b00 cmp r3, #0 801358a: d117 bne.n 80135bc return; } } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ huart->TxXferCount = 0x00U; 801358c: 68fb ldr r3, [r7, #12] 801358e: 2200 movs r2, #0 8013590: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 8013592: 68fb ldr r3, [r7, #12] 8013594: 2200 movs r2, #0 8013596: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8013598: 68fb ldr r3, [r7, #12] 801359a: 2200 movs r2, #0 801359c: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 801359e: 68fb ldr r3, [r7, #12] 80135a0: 2220 movs r2, #32 80135a2: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 80135a6: 68fb ldr r3, [r7, #12] 80135a8: 2220 movs r2, #32 80135aa: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80135ae: 68fb ldr r3, [r7, #12] 80135b0: 2200 movs r2, #0 80135b2: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 80135b4: 68f8 ldr r0, [r7, #12] 80135b6: f7ff fee2 bl 801337e 80135ba: e000 b.n 80135be return; 80135bc: bf00 nop #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80135be: 3710 adds r7, #16 80135c0: 46bd mov sp, r7 80135c2: bd80 pop {r7, pc} 080135c4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 80135c4: b480 push {r7} 80135c6: b085 sub sp, #20 80135c8: af00 add r7, sp, #0 80135ca: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 80135cc: 687b ldr r3, [r7, #4] 80135ce: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80135d2: b2db uxtb r3, r3 80135d4: 2b21 cmp r3, #33 @ 0x21 80135d6: d13e bne.n 8013656 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80135d8: 687b ldr r3, [r7, #4] 80135da: 689b ldr r3, [r3, #8] 80135dc: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80135e0: d114 bne.n 801360c 80135e2: 687b ldr r3, [r7, #4] 80135e4: 691b ldr r3, [r3, #16] 80135e6: 2b00 cmp r3, #0 80135e8: d110 bne.n 801360c { tmp = (const uint16_t *) huart->pTxBuffPtr; 80135ea: 687b ldr r3, [r7, #4] 80135ec: 6a1b ldr r3, [r3, #32] 80135ee: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 80135f0: 68fb ldr r3, [r7, #12] 80135f2: 881b ldrh r3, [r3, #0] 80135f4: 461a mov r2, r3 80135f6: 687b ldr r3, [r7, #4] 80135f8: 681b ldr r3, [r3, #0] 80135fa: f3c2 0208 ubfx r2, r2, #0, #9 80135fe: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 8013600: 687b ldr r3, [r7, #4] 8013602: 6a1b ldr r3, [r3, #32] 8013604: 1c9a adds r2, r3, #2 8013606: 687b ldr r3, [r7, #4] 8013608: 621a str r2, [r3, #32] 801360a: e008 b.n 801361e } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 801360c: 687b ldr r3, [r7, #4] 801360e: 6a1b ldr r3, [r3, #32] 8013610: 1c59 adds r1, r3, #1 8013612: 687a ldr r2, [r7, #4] 8013614: 6211 str r1, [r2, #32] 8013616: 781a ldrb r2, [r3, #0] 8013618: 687b ldr r3, [r7, #4] 801361a: 681b ldr r3, [r3, #0] 801361c: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 801361e: 687b ldr r3, [r7, #4] 8013620: 8cdb ldrh r3, [r3, #38] @ 0x26 8013622: b29b uxth r3, r3 8013624: 3b01 subs r3, #1 8013626: b29b uxth r3, r3 8013628: 687a ldr r2, [r7, #4] 801362a: 4619 mov r1, r3 801362c: 84d1 strh r1, [r2, #38] @ 0x26 801362e: 2b00 cmp r3, #0 8013630: d10f bne.n 8013652 { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8013632: 687b ldr r3, [r7, #4] 8013634: 681b ldr r3, [r3, #0] 8013636: 68da ldr r2, [r3, #12] 8013638: 687b ldr r3, [r7, #4] 801363a: 681b ldr r3, [r3, #0] 801363c: f022 0280 bic.w r2, r2, #128 @ 0x80 8013640: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8013642: 687b ldr r3, [r7, #4] 8013644: 681b ldr r3, [r3, #0] 8013646: 68da ldr r2, [r3, #12] 8013648: 687b ldr r3, [r7, #4] 801364a: 681b ldr r3, [r3, #0] 801364c: f042 0240 orr.w r2, r2, #64 @ 0x40 8013650: 60da str r2, [r3, #12] } return HAL_OK; 8013652: 2300 movs r3, #0 8013654: e000 b.n 8013658 } else { return HAL_BUSY; 8013656: 2302 movs r3, #2 } } 8013658: 4618 mov r0, r3 801365a: 3714 adds r7, #20 801365c: 46bd mov sp, r7 801365e: bc80 pop {r7} 8013660: 4770 bx lr 08013662 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8013662: b580 push {r7, lr} 8013664: b082 sub sp, #8 8013666: af00 add r7, sp, #0 8013668: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 801366a: 687b ldr r3, [r7, #4] 801366c: 681b ldr r3, [r3, #0] 801366e: 68da ldr r2, [r3, #12] 8013670: 687b ldr r3, [r7, #4] 8013672: 681b ldr r3, [r3, #0] 8013674: f022 0240 bic.w r2, r2, #64 @ 0x40 8013678: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 801367a: 687b ldr r3, [r7, #4] 801367c: 2220 movs r2, #32 801367e: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8013682: 6878 ldr r0, [r7, #4] 8013684: f7f9 f87a bl 800c77c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8013688: 2300 movs r3, #0 } 801368a: 4618 mov r0, r3 801368c: 3708 adds r7, #8 801368e: 46bd mov sp, r7 8013690: bd80 pop {r7, pc} 08013692 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 8013692: b580 push {r7, lr} 8013694: b08c sub sp, #48 @ 0x30 8013696: af00 add r7, sp, #0 8013698: 6078 str r0, [r7, #4] uint8_t *pdata8bits; uint16_t *pdata16bits; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 801369a: 687b ldr r3, [r7, #4] 801369c: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 80136a0: b2db uxtb r3, r3 80136a2: 2b22 cmp r3, #34 @ 0x22 80136a4: f040 80ae bne.w 8013804 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80136a8: 687b ldr r3, [r7, #4] 80136aa: 689b ldr r3, [r3, #8] 80136ac: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80136b0: d117 bne.n 80136e2 80136b2: 687b ldr r3, [r7, #4] 80136b4: 691b ldr r3, [r3, #16] 80136b6: 2b00 cmp r3, #0 80136b8: d113 bne.n 80136e2 { pdata8bits = NULL; 80136ba: 2300 movs r3, #0 80136bc: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = (uint16_t *) huart->pRxBuffPtr; 80136be: 687b ldr r3, [r7, #4] 80136c0: 6a9b ldr r3, [r3, #40] @ 0x28 80136c2: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 80136c4: 687b ldr r3, [r7, #4] 80136c6: 681b ldr r3, [r3, #0] 80136c8: 685b ldr r3, [r3, #4] 80136ca: b29b uxth r3, r3 80136cc: f3c3 0308 ubfx r3, r3, #0, #9 80136d0: b29a uxth r2, r3 80136d2: 6abb ldr r3, [r7, #40] @ 0x28 80136d4: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 80136d6: 687b ldr r3, [r7, #4] 80136d8: 6a9b ldr r3, [r3, #40] @ 0x28 80136da: 1c9a adds r2, r3, #2 80136dc: 687b ldr r3, [r7, #4] 80136de: 629a str r2, [r3, #40] @ 0x28 80136e0: e026 b.n 8013730 } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 80136e2: 687b ldr r3, [r7, #4] 80136e4: 6a9b ldr r3, [r3, #40] @ 0x28 80136e6: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = NULL; 80136e8: 2300 movs r3, #0 80136ea: 62bb str r3, [r7, #40] @ 0x28 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 80136ec: 687b ldr r3, [r7, #4] 80136ee: 689b ldr r3, [r3, #8] 80136f0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80136f4: d007 beq.n 8013706 80136f6: 687b ldr r3, [r7, #4] 80136f8: 689b ldr r3, [r3, #8] 80136fa: 2b00 cmp r3, #0 80136fc: d10a bne.n 8013714 80136fe: 687b ldr r3, [r7, #4] 8013700: 691b ldr r3, [r3, #16] 8013702: 2b00 cmp r3, #0 8013704: d106 bne.n 8013714 { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8013706: 687b ldr r3, [r7, #4] 8013708: 681b ldr r3, [r3, #0] 801370a: 685b ldr r3, [r3, #4] 801370c: b2da uxtb r2, r3 801370e: 6afb ldr r3, [r7, #44] @ 0x2c 8013710: 701a strb r2, [r3, #0] 8013712: e008 b.n 8013726 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8013714: 687b ldr r3, [r7, #4] 8013716: 681b ldr r3, [r3, #0] 8013718: 685b ldr r3, [r3, #4] 801371a: b2db uxtb r3, r3 801371c: f003 037f and.w r3, r3, #127 @ 0x7f 8013720: b2da uxtb r2, r3 8013722: 6afb ldr r3, [r7, #44] @ 0x2c 8013724: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8013726: 687b ldr r3, [r7, #4] 8013728: 6a9b ldr r3, [r3, #40] @ 0x28 801372a: 1c5a adds r2, r3, #1 801372c: 687b ldr r3, [r7, #4] 801372e: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 8013730: 687b ldr r3, [r7, #4] 8013732: 8ddb ldrh r3, [r3, #46] @ 0x2e 8013734: b29b uxth r3, r3 8013736: 3b01 subs r3, #1 8013738: b29b uxth r3, r3 801373a: 687a ldr r2, [r7, #4] 801373c: 4619 mov r1, r3 801373e: 85d1 strh r1, [r2, #46] @ 0x2e 8013740: 2b00 cmp r3, #0 8013742: d15d bne.n 8013800 { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8013744: 687b ldr r3, [r7, #4] 8013746: 681b ldr r3, [r3, #0] 8013748: 68da ldr r2, [r3, #12] 801374a: 687b ldr r3, [r7, #4] 801374c: 681b ldr r3, [r3, #0] 801374e: f022 0220 bic.w r2, r2, #32 8013752: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8013754: 687b ldr r3, [r7, #4] 8013756: 681b ldr r3, [r3, #0] 8013758: 68da ldr r2, [r3, #12] 801375a: 687b ldr r3, [r7, #4] 801375c: 681b ldr r3, [r3, #0] 801375e: f422 7280 bic.w r2, r2, #256 @ 0x100 8013762: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8013764: 687b ldr r3, [r7, #4] 8013766: 681b ldr r3, [r3, #0] 8013768: 695a ldr r2, [r3, #20] 801376a: 687b ldr r3, [r7, #4] 801376c: 681b ldr r3, [r3, #0] 801376e: f022 0201 bic.w r2, r2, #1 8013772: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013774: 687b ldr r3, [r7, #4] 8013776: 2220 movs r2, #32 8013778: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 801377c: 687b ldr r3, [r7, #4] 801377e: 2200 movs r2, #0 8013780: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013782: 687b ldr r3, [r7, #4] 8013784: 6b1b ldr r3, [r3, #48] @ 0x30 8013786: 2b01 cmp r3, #1 8013788: d135 bne.n 80137f6 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801378a: 687b ldr r3, [r7, #4] 801378c: 2200 movs r2, #0 801378e: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013790: 687b ldr r3, [r7, #4] 8013792: 681b ldr r3, [r3, #0] 8013794: 330c adds r3, #12 8013796: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013798: 697b ldr r3, [r7, #20] 801379a: e853 3f00 ldrex r3, [r3] 801379e: 613b str r3, [r7, #16] return(result); 80137a0: 693b ldr r3, [r7, #16] 80137a2: f023 0310 bic.w r3, r3, #16 80137a6: 627b str r3, [r7, #36] @ 0x24 80137a8: 687b ldr r3, [r7, #4] 80137aa: 681b ldr r3, [r3, #0] 80137ac: 330c adds r3, #12 80137ae: 6a7a ldr r2, [r7, #36] @ 0x24 80137b0: 623a str r2, [r7, #32] 80137b2: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80137b4: 69f9 ldr r1, [r7, #28] 80137b6: 6a3a ldr r2, [r7, #32] 80137b8: e841 2300 strex r3, r2, [r1] 80137bc: 61bb str r3, [r7, #24] return(result); 80137be: 69bb ldr r3, [r7, #24] 80137c0: 2b00 cmp r3, #0 80137c2: d1e5 bne.n 8013790 /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 80137c4: 687b ldr r3, [r7, #4] 80137c6: 681b ldr r3, [r3, #0] 80137c8: 681b ldr r3, [r3, #0] 80137ca: f003 0310 and.w r3, r3, #16 80137ce: 2b10 cmp r3, #16 80137d0: d10a bne.n 80137e8 { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 80137d2: 2300 movs r3, #0 80137d4: 60fb str r3, [r7, #12] 80137d6: 687b ldr r3, [r7, #4] 80137d8: 681b ldr r3, [r3, #0] 80137da: 681b ldr r3, [r3, #0] 80137dc: 60fb str r3, [r7, #12] 80137de: 687b ldr r3, [r7, #4] 80137e0: 681b ldr r3, [r3, #0] 80137e2: 685b ldr r3, [r3, #4] 80137e4: 60fb str r3, [r7, #12] 80137e6: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 80137e8: 687b ldr r3, [r7, #4] 80137ea: 8d9b ldrh r3, [r3, #44] @ 0x2c 80137ec: 4619 mov r1, r3 80137ee: 6878 ldr r0, [r7, #4] 80137f0: f7f8 ff5c bl 800c6ac 80137f4: e002 b.n 80137fc #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 80137f6: 6878 ldr r0, [r7, #4] 80137f8: f7ff fdb8 bl 801336c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 80137fc: 2300 movs r3, #0 80137fe: e002 b.n 8013806 } return HAL_OK; 8013800: 2300 movs r3, #0 8013802: e000 b.n 8013806 } else { return HAL_BUSY; 8013804: 2302 movs r3, #2 } } 8013806: 4618 mov r0, r3 8013808: 3730 adds r7, #48 @ 0x30 801380a: 46bd mov sp, r7 801380c: bd80 pop {r7, pc} ... 08013810 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8013810: b580 push {r7, lr} 8013812: b084 sub sp, #16 8013814: af00 add r7, sp, #0 8013816: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8013818: 687b ldr r3, [r7, #4] 801381a: 681b ldr r3, [r3, #0] 801381c: 691b ldr r3, [r3, #16] 801381e: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8013822: 687b ldr r3, [r7, #4] 8013824: 68da ldr r2, [r3, #12] 8013826: 687b ldr r3, [r7, #4] 8013828: 681b ldr r3, [r3, #0] 801382a: 430a orrs r2, r1 801382c: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 801382e: 687b ldr r3, [r7, #4] 8013830: 689a ldr r2, [r3, #8] 8013832: 687b ldr r3, [r7, #4] 8013834: 691b ldr r3, [r3, #16] 8013836: 431a orrs r2, r3 8013838: 687b ldr r3, [r7, #4] 801383a: 695b ldr r3, [r3, #20] 801383c: 4313 orrs r3, r2 801383e: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 8013840: 687b ldr r3, [r7, #4] 8013842: 681b ldr r3, [r3, #0] 8013844: 68db ldr r3, [r3, #12] 8013846: f423 53b0 bic.w r3, r3, #5632 @ 0x1600 801384a: f023 030c bic.w r3, r3, #12 801384e: 687a ldr r2, [r7, #4] 8013850: 6812 ldr r2, [r2, #0] 8013852: 68b9 ldr r1, [r7, #8] 8013854: 430b orrs r3, r1 8013856: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8013858: 687b ldr r3, [r7, #4] 801385a: 681b ldr r3, [r3, #0] 801385c: 695b ldr r3, [r3, #20] 801385e: f423 7140 bic.w r1, r3, #768 @ 0x300 8013862: 687b ldr r3, [r7, #4] 8013864: 699a ldr r2, [r3, #24] 8013866: 687b ldr r3, [r7, #4] 8013868: 681b ldr r3, [r3, #0] 801386a: 430a orrs r2, r1 801386c: 615a str r2, [r3, #20] if(huart->Instance == USART1) 801386e: 687b ldr r3, [r7, #4] 8013870: 681b ldr r3, [r3, #0] 8013872: 4a2c ldr r2, [pc, #176] @ (8013924 ) 8013874: 4293 cmp r3, r2 8013876: d103 bne.n 8013880 { pclk = HAL_RCC_GetPCLK2Freq(); 8013878: f7fd fc78 bl 801116c 801387c: 60f8 str r0, [r7, #12] 801387e: e002 b.n 8013886 } else { pclk = HAL_RCC_GetPCLK1Freq(); 8013880: f7fd fc60 bl 8011144 8013884: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8013886: 68fa ldr r2, [r7, #12] 8013888: 4613 mov r3, r2 801388a: 009b lsls r3, r3, #2 801388c: 4413 add r3, r2 801388e: 009a lsls r2, r3, #2 8013890: 441a add r2, r3 8013892: 687b ldr r3, [r7, #4] 8013894: 685b ldr r3, [r3, #4] 8013896: 009b lsls r3, r3, #2 8013898: fbb2 f3f3 udiv r3, r2, r3 801389c: 4a22 ldr r2, [pc, #136] @ (8013928 ) 801389e: fba2 2303 umull r2, r3, r2, r3 80138a2: 095b lsrs r3, r3, #5 80138a4: 0119 lsls r1, r3, #4 80138a6: 68fa ldr r2, [r7, #12] 80138a8: 4613 mov r3, r2 80138aa: 009b lsls r3, r3, #2 80138ac: 4413 add r3, r2 80138ae: 009a lsls r2, r3, #2 80138b0: 441a add r2, r3 80138b2: 687b ldr r3, [r7, #4] 80138b4: 685b ldr r3, [r3, #4] 80138b6: 009b lsls r3, r3, #2 80138b8: fbb2 f2f3 udiv r2, r2, r3 80138bc: 4b1a ldr r3, [pc, #104] @ (8013928 ) 80138be: fba3 0302 umull r0, r3, r3, r2 80138c2: 095b lsrs r3, r3, #5 80138c4: 2064 movs r0, #100 @ 0x64 80138c6: fb00 f303 mul.w r3, r0, r3 80138ca: 1ad3 subs r3, r2, r3 80138cc: 011b lsls r3, r3, #4 80138ce: 3332 adds r3, #50 @ 0x32 80138d0: 4a15 ldr r2, [pc, #84] @ (8013928 ) 80138d2: fba2 2303 umull r2, r3, r2, r3 80138d6: 095b lsrs r3, r3, #5 80138d8: f003 03f0 and.w r3, r3, #240 @ 0xf0 80138dc: 4419 add r1, r3 80138de: 68fa ldr r2, [r7, #12] 80138e0: 4613 mov r3, r2 80138e2: 009b lsls r3, r3, #2 80138e4: 4413 add r3, r2 80138e6: 009a lsls r2, r3, #2 80138e8: 441a add r2, r3 80138ea: 687b ldr r3, [r7, #4] 80138ec: 685b ldr r3, [r3, #4] 80138ee: 009b lsls r3, r3, #2 80138f0: fbb2 f2f3 udiv r2, r2, r3 80138f4: 4b0c ldr r3, [pc, #48] @ (8013928 ) 80138f6: fba3 0302 umull r0, r3, r3, r2 80138fa: 095b lsrs r3, r3, #5 80138fc: 2064 movs r0, #100 @ 0x64 80138fe: fb00 f303 mul.w r3, r0, r3 8013902: 1ad3 subs r3, r2, r3 8013904: 011b lsls r3, r3, #4 8013906: 3332 adds r3, #50 @ 0x32 8013908: 4a07 ldr r2, [pc, #28] @ (8013928 ) 801390a: fba2 2303 umull r2, r3, r2, r3 801390e: 095b lsrs r3, r3, #5 8013910: f003 020f and.w r2, r3, #15 8013914: 687b ldr r3, [r7, #4] 8013916: 681b ldr r3, [r3, #0] 8013918: 440a add r2, r1 801391a: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 801391c: bf00 nop 801391e: 3710 adds r7, #16 8013920: 46bd mov sp, r7 8013922: bd80 pop {r7, pc} 8013924: 40013800 .word 0x40013800 8013928: 51eb851f .word 0x51eb851f 0801392c <__cvt>: 801392c: 2b00 cmp r3, #0 801392e: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8013932: 461d mov r5, r3 8013934: bfbb ittet lt 8013936: f103 4300 addlt.w r3, r3, #2147483648 @ 0x80000000 801393a: 461d movlt r5, r3 801393c: 2300 movge r3, #0 801393e: 232d movlt r3, #45 @ 0x2d 8013940: b088 sub sp, #32 8013942: 4614 mov r4, r2 8013944: bfb8 it lt 8013946: 4614 movlt r4, r2 8013948: 9a12 ldr r2, [sp, #72] @ 0x48 801394a: 9e10 ldr r6, [sp, #64] @ 0x40 801394c: 7013 strb r3, [r2, #0] 801394e: 9b14 ldr r3, [sp, #80] @ 0x50 8013950: f8dd a04c ldr.w sl, [sp, #76] @ 0x4c 8013954: f023 0820 bic.w r8, r3, #32 8013958: f1b8 0f46 cmp.w r8, #70 @ 0x46 801395c: d005 beq.n 801396a <__cvt+0x3e> 801395e: f1b8 0f45 cmp.w r8, #69 @ 0x45 8013962: d100 bne.n 8013966 <__cvt+0x3a> 8013964: 3601 adds r6, #1 8013966: 2302 movs r3, #2 8013968: e000 b.n 801396c <__cvt+0x40> 801396a: 2303 movs r3, #3 801396c: aa07 add r2, sp, #28 801396e: 9204 str r2, [sp, #16] 8013970: aa06 add r2, sp, #24 8013972: e9cd a202 strd sl, r2, [sp, #8] 8013976: e9cd 3600 strd r3, r6, [sp] 801397a: 4622 mov r2, r4 801397c: 462b mov r3, r5 801397e: f000 fe3b bl 80145f8 <_dtoa_r> 8013982: f1b8 0f47 cmp.w r8, #71 @ 0x47 8013986: 4607 mov r7, r0 8013988: d119 bne.n 80139be <__cvt+0x92> 801398a: 9b11 ldr r3, [sp, #68] @ 0x44 801398c: 07db lsls r3, r3, #31 801398e: d50e bpl.n 80139ae <__cvt+0x82> 8013990: eb00 0906 add.w r9, r0, r6 8013994: 2200 movs r2, #0 8013996: 2300 movs r3, #0 8013998: 4620 mov r0, r4 801399a: 4629 mov r1, r5 801399c: f7f5 f870 bl 8008a80 <__aeabi_dcmpeq> 80139a0: b108 cbz r0, 80139a6 <__cvt+0x7a> 80139a2: f8cd 901c str.w r9, [sp, #28] 80139a6: 2230 movs r2, #48 @ 0x30 80139a8: 9b07 ldr r3, [sp, #28] 80139aa: 454b cmp r3, r9 80139ac: d31e bcc.n 80139ec <__cvt+0xc0> 80139ae: 4638 mov r0, r7 80139b0: 9b07 ldr r3, [sp, #28] 80139b2: 9a15 ldr r2, [sp, #84] @ 0x54 80139b4: 1bdb subs r3, r3, r7 80139b6: 6013 str r3, [r2, #0] 80139b8: b008 add sp, #32 80139ba: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80139be: f1b8 0f46 cmp.w r8, #70 @ 0x46 80139c2: eb00 0906 add.w r9, r0, r6 80139c6: d1e5 bne.n 8013994 <__cvt+0x68> 80139c8: 7803 ldrb r3, [r0, #0] 80139ca: 2b30 cmp r3, #48 @ 0x30 80139cc: d10a bne.n 80139e4 <__cvt+0xb8> 80139ce: 2200 movs r2, #0 80139d0: 2300 movs r3, #0 80139d2: 4620 mov r0, r4 80139d4: 4629 mov r1, r5 80139d6: f7f5 f853 bl 8008a80 <__aeabi_dcmpeq> 80139da: b918 cbnz r0, 80139e4 <__cvt+0xb8> 80139dc: f1c6 0601 rsb r6, r6, #1 80139e0: f8ca 6000 str.w r6, [sl] 80139e4: f8da 3000 ldr.w r3, [sl] 80139e8: 4499 add r9, r3 80139ea: e7d3 b.n 8013994 <__cvt+0x68> 80139ec: 1c59 adds r1, r3, #1 80139ee: 9107 str r1, [sp, #28] 80139f0: 701a strb r2, [r3, #0] 80139f2: e7d9 b.n 80139a8 <__cvt+0x7c> 080139f4 <__exponent>: 80139f4: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 80139f6: 2900 cmp r1, #0 80139f8: bfb6 itet lt 80139fa: 232d movlt r3, #45 @ 0x2d 80139fc: 232b movge r3, #43 @ 0x2b 80139fe: 4249 neglt r1, r1 8013a00: 2909 cmp r1, #9 8013a02: 7002 strb r2, [r0, #0] 8013a04: 7043 strb r3, [r0, #1] 8013a06: dd29 ble.n 8013a5c <__exponent+0x68> 8013a08: f10d 0307 add.w r3, sp, #7 8013a0c: 461d mov r5, r3 8013a0e: 270a movs r7, #10 8013a10: fbb1 f6f7 udiv r6, r1, r7 8013a14: 461a mov r2, r3 8013a16: fb07 1416 mls r4, r7, r6, r1 8013a1a: 3430 adds r4, #48 @ 0x30 8013a1c: f802 4c01 strb.w r4, [r2, #-1] 8013a20: 460c mov r4, r1 8013a22: 2c63 cmp r4, #99 @ 0x63 8013a24: 4631 mov r1, r6 8013a26: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff 8013a2a: dcf1 bgt.n 8013a10 <__exponent+0x1c> 8013a2c: 3130 adds r1, #48 @ 0x30 8013a2e: 1e94 subs r4, r2, #2 8013a30: f803 1c01 strb.w r1, [r3, #-1] 8013a34: 4623 mov r3, r4 8013a36: 1c41 adds r1, r0, #1 8013a38: 42ab cmp r3, r5 8013a3a: d30a bcc.n 8013a52 <__exponent+0x5e> 8013a3c: f10d 0309 add.w r3, sp, #9 8013a40: 1a9b subs r3, r3, r2 8013a42: 42ac cmp r4, r5 8013a44: bf88 it hi 8013a46: 2300 movhi r3, #0 8013a48: 3302 adds r3, #2 8013a4a: 4403 add r3, r0 8013a4c: 1a18 subs r0, r3, r0 8013a4e: b003 add sp, #12 8013a50: bdf0 pop {r4, r5, r6, r7, pc} 8013a52: f813 6b01 ldrb.w r6, [r3], #1 8013a56: f801 6f01 strb.w r6, [r1, #1]! 8013a5a: e7ed b.n 8013a38 <__exponent+0x44> 8013a5c: 2330 movs r3, #48 @ 0x30 8013a5e: 3130 adds r1, #48 @ 0x30 8013a60: 7083 strb r3, [r0, #2] 8013a62: 70c1 strb r1, [r0, #3] 8013a64: 1d03 adds r3, r0, #4 8013a66: e7f1 b.n 8013a4c <__exponent+0x58> 08013a68 <_printf_float>: 8013a68: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8013a6c: b091 sub sp, #68 @ 0x44 8013a6e: 460c mov r4, r1 8013a70: f8dd 8068 ldr.w r8, [sp, #104] @ 0x68 8013a74: 4616 mov r6, r2 8013a76: 461f mov r7, r3 8013a78: 4605 mov r5, r0 8013a7a: f000 fcf7 bl 801446c <_localeconv_r> 8013a7e: 6803 ldr r3, [r0, #0] 8013a80: 4618 mov r0, r3 8013a82: 9308 str r3, [sp, #32] 8013a84: f7f4 fbd0 bl 8008228 8013a88: 2300 movs r3, #0 8013a8a: 930e str r3, [sp, #56] @ 0x38 8013a8c: f8d8 3000 ldr.w r3, [r8] 8013a90: 9009 str r0, [sp, #36] @ 0x24 8013a92: 3307 adds r3, #7 8013a94: f023 0307 bic.w r3, r3, #7 8013a98: f103 0208 add.w r2, r3, #8 8013a9c: f894 a018 ldrb.w sl, [r4, #24] 8013aa0: f8d4 b000 ldr.w fp, [r4] 8013aa4: f8c8 2000 str.w r2, [r8] 8013aa8: e9d3 8900 ldrd r8, r9, [r3] 8013aac: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000 8013ab0: 930b str r3, [sp, #44] @ 0x2c 8013ab2: f8cd 8028 str.w r8, [sp, #40] @ 0x28 8013ab6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8013aba: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 8013abe: e9c4 8912 strd r8, r9, [r4, #72] @ 0x48 8013ac2: 4b9c ldr r3, [pc, #624] @ (8013d34 <_printf_float+0x2cc>) 8013ac4: f7f5 f80e bl 8008ae4 <__aeabi_dcmpun> 8013ac8: bb70 cbnz r0, 8013b28 <_printf_float+0xc0> 8013aca: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 8013ace: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8013ad2: 4b98 ldr r3, [pc, #608] @ (8013d34 <_printf_float+0x2cc>) 8013ad4: f7f4 ffe8 bl 8008aa8 <__aeabi_dcmple> 8013ad8: bb30 cbnz r0, 8013b28 <_printf_float+0xc0> 8013ada: 2200 movs r2, #0 8013adc: 2300 movs r3, #0 8013ade: 4640 mov r0, r8 8013ae0: 4649 mov r1, r9 8013ae2: f7f4 ffd7 bl 8008a94 <__aeabi_dcmplt> 8013ae6: b110 cbz r0, 8013aee <_printf_float+0x86> 8013ae8: 232d movs r3, #45 @ 0x2d 8013aea: f884 3043 strb.w r3, [r4, #67] @ 0x43 8013aee: 4a92 ldr r2, [pc, #584] @ (8013d38 <_printf_float+0x2d0>) 8013af0: 4b92 ldr r3, [pc, #584] @ (8013d3c <_printf_float+0x2d4>) 8013af2: f1ba 0f47 cmp.w sl, #71 @ 0x47 8013af6: bf8c ite hi 8013af8: 4690 movhi r8, r2 8013afa: 4698 movls r8, r3 8013afc: 2303 movs r3, #3 8013afe: f04f 0900 mov.w r9, #0 8013b02: 6123 str r3, [r4, #16] 8013b04: f02b 0304 bic.w r3, fp, #4 8013b08: 6023 str r3, [r4, #0] 8013b0a: 4633 mov r3, r6 8013b0c: 4621 mov r1, r4 8013b0e: 4628 mov r0, r5 8013b10: 9700 str r7, [sp, #0] 8013b12: aa0f add r2, sp, #60 @ 0x3c 8013b14: f000 f9d4 bl 8013ec0 <_printf_common> 8013b18: 3001 adds r0, #1 8013b1a: f040 8090 bne.w 8013c3e <_printf_float+0x1d6> 8013b1e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8013b22: b011 add sp, #68 @ 0x44 8013b24: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8013b28: 4642 mov r2, r8 8013b2a: 464b mov r3, r9 8013b2c: 4640 mov r0, r8 8013b2e: 4649 mov r1, r9 8013b30: f7f4 ffd8 bl 8008ae4 <__aeabi_dcmpun> 8013b34: b148 cbz r0, 8013b4a <_printf_float+0xe2> 8013b36: 464b mov r3, r9 8013b38: 2b00 cmp r3, #0 8013b3a: bfb8 it lt 8013b3c: 232d movlt r3, #45 @ 0x2d 8013b3e: 4a80 ldr r2, [pc, #512] @ (8013d40 <_printf_float+0x2d8>) 8013b40: bfb8 it lt 8013b42: f884 3043 strblt.w r3, [r4, #67] @ 0x43 8013b46: 4b7f ldr r3, [pc, #508] @ (8013d44 <_printf_float+0x2dc>) 8013b48: e7d3 b.n 8013af2 <_printf_float+0x8a> 8013b4a: 6863 ldr r3, [r4, #4] 8013b4c: f00a 01df and.w r1, sl, #223 @ 0xdf 8013b50: 1c5a adds r2, r3, #1 8013b52: d13f bne.n 8013bd4 <_printf_float+0x16c> 8013b54: 2306 movs r3, #6 8013b56: 6063 str r3, [r4, #4] 8013b58: 2200 movs r2, #0 8013b5a: f44b 6380 orr.w r3, fp, #1024 @ 0x400 8013b5e: 6023 str r3, [r4, #0] 8013b60: 9206 str r2, [sp, #24] 8013b62: aa0e add r2, sp, #56 @ 0x38 8013b64: e9cd a204 strd sl, r2, [sp, #16] 8013b68: aa0d add r2, sp, #52 @ 0x34 8013b6a: 9203 str r2, [sp, #12] 8013b6c: f10d 0233 add.w r2, sp, #51 @ 0x33 8013b70: e9cd 3201 strd r3, r2, [sp, #4] 8013b74: 6863 ldr r3, [r4, #4] 8013b76: 4642 mov r2, r8 8013b78: 9300 str r3, [sp, #0] 8013b7a: 4628 mov r0, r5 8013b7c: 464b mov r3, r9 8013b7e: 910a str r1, [sp, #40] @ 0x28 8013b80: f7ff fed4 bl 801392c <__cvt> 8013b84: 990a ldr r1, [sp, #40] @ 0x28 8013b86: 4680 mov r8, r0 8013b88: 2947 cmp r1, #71 @ 0x47 8013b8a: 990d ldr r1, [sp, #52] @ 0x34 8013b8c: d128 bne.n 8013be0 <_printf_float+0x178> 8013b8e: 1cc8 adds r0, r1, #3 8013b90: db02 blt.n 8013b98 <_printf_float+0x130> 8013b92: 6863 ldr r3, [r4, #4] 8013b94: 4299 cmp r1, r3 8013b96: dd40 ble.n 8013c1a <_printf_float+0x1b2> 8013b98: f1aa 0a02 sub.w sl, sl, #2 8013b9c: fa5f fa8a uxtb.w sl, sl 8013ba0: 4652 mov r2, sl 8013ba2: 3901 subs r1, #1 8013ba4: f104 0050 add.w r0, r4, #80 @ 0x50 8013ba8: 910d str r1, [sp, #52] @ 0x34 8013baa: f7ff ff23 bl 80139f4 <__exponent> 8013bae: 9a0e ldr r2, [sp, #56] @ 0x38 8013bb0: 4681 mov r9, r0 8013bb2: 1813 adds r3, r2, r0 8013bb4: 2a01 cmp r2, #1 8013bb6: 6123 str r3, [r4, #16] 8013bb8: dc02 bgt.n 8013bc0 <_printf_float+0x158> 8013bba: 6822 ldr r2, [r4, #0] 8013bbc: 07d2 lsls r2, r2, #31 8013bbe: d501 bpl.n 8013bc4 <_printf_float+0x15c> 8013bc0: 3301 adds r3, #1 8013bc2: 6123 str r3, [r4, #16] 8013bc4: f89d 3033 ldrb.w r3, [sp, #51] @ 0x33 8013bc8: 2b00 cmp r3, #0 8013bca: d09e beq.n 8013b0a <_printf_float+0xa2> 8013bcc: 232d movs r3, #45 @ 0x2d 8013bce: f884 3043 strb.w r3, [r4, #67] @ 0x43 8013bd2: e79a b.n 8013b0a <_printf_float+0xa2> 8013bd4: 2947 cmp r1, #71 @ 0x47 8013bd6: d1bf bne.n 8013b58 <_printf_float+0xf0> 8013bd8: 2b00 cmp r3, #0 8013bda: d1bd bne.n 8013b58 <_printf_float+0xf0> 8013bdc: 2301 movs r3, #1 8013bde: e7ba b.n 8013b56 <_printf_float+0xee> 8013be0: f1ba 0f65 cmp.w sl, #101 @ 0x65 8013be4: d9dc bls.n 8013ba0 <_printf_float+0x138> 8013be6: f1ba 0f66 cmp.w sl, #102 @ 0x66 8013bea: d118 bne.n 8013c1e <_printf_float+0x1b6> 8013bec: 2900 cmp r1, #0 8013bee: 6863 ldr r3, [r4, #4] 8013bf0: dd0b ble.n 8013c0a <_printf_float+0x1a2> 8013bf2: 6121 str r1, [r4, #16] 8013bf4: b913 cbnz r3, 8013bfc <_printf_float+0x194> 8013bf6: 6822 ldr r2, [r4, #0] 8013bf8: 07d0 lsls r0, r2, #31 8013bfa: d502 bpl.n 8013c02 <_printf_float+0x19a> 8013bfc: 3301 adds r3, #1 8013bfe: 440b add r3, r1 8013c00: 6123 str r3, [r4, #16] 8013c02: f04f 0900 mov.w r9, #0 8013c06: 65a1 str r1, [r4, #88] @ 0x58 8013c08: e7dc b.n 8013bc4 <_printf_float+0x15c> 8013c0a: b913 cbnz r3, 8013c12 <_printf_float+0x1aa> 8013c0c: 6822 ldr r2, [r4, #0] 8013c0e: 07d2 lsls r2, r2, #31 8013c10: d501 bpl.n 8013c16 <_printf_float+0x1ae> 8013c12: 3302 adds r3, #2 8013c14: e7f4 b.n 8013c00 <_printf_float+0x198> 8013c16: 2301 movs r3, #1 8013c18: e7f2 b.n 8013c00 <_printf_float+0x198> 8013c1a: f04f 0a67 mov.w sl, #103 @ 0x67 8013c1e: 9b0e ldr r3, [sp, #56] @ 0x38 8013c20: 4299 cmp r1, r3 8013c22: db05 blt.n 8013c30 <_printf_float+0x1c8> 8013c24: 6823 ldr r3, [r4, #0] 8013c26: 6121 str r1, [r4, #16] 8013c28: 07d8 lsls r0, r3, #31 8013c2a: d5ea bpl.n 8013c02 <_printf_float+0x19a> 8013c2c: 1c4b adds r3, r1, #1 8013c2e: e7e7 b.n 8013c00 <_printf_float+0x198> 8013c30: 2900 cmp r1, #0 8013c32: bfcc ite gt 8013c34: 2201 movgt r2, #1 8013c36: f1c1 0202 rsble r2, r1, #2 8013c3a: 4413 add r3, r2 8013c3c: e7e0 b.n 8013c00 <_printf_float+0x198> 8013c3e: 6823 ldr r3, [r4, #0] 8013c40: 055a lsls r2, r3, #21 8013c42: d407 bmi.n 8013c54 <_printf_float+0x1ec> 8013c44: 6923 ldr r3, [r4, #16] 8013c46: 4642 mov r2, r8 8013c48: 4631 mov r1, r6 8013c4a: 4628 mov r0, r5 8013c4c: 47b8 blx r7 8013c4e: 3001 adds r0, #1 8013c50: d12b bne.n 8013caa <_printf_float+0x242> 8013c52: e764 b.n 8013b1e <_printf_float+0xb6> 8013c54: f1ba 0f65 cmp.w sl, #101 @ 0x65 8013c58: f240 80dc bls.w 8013e14 <_printf_float+0x3ac> 8013c5c: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 8013c60: 2200 movs r2, #0 8013c62: 2300 movs r3, #0 8013c64: f7f4 ff0c bl 8008a80 <__aeabi_dcmpeq> 8013c68: 2800 cmp r0, #0 8013c6a: d033 beq.n 8013cd4 <_printf_float+0x26c> 8013c6c: 2301 movs r3, #1 8013c6e: 4631 mov r1, r6 8013c70: 4628 mov r0, r5 8013c72: 4a35 ldr r2, [pc, #212] @ (8013d48 <_printf_float+0x2e0>) 8013c74: 47b8 blx r7 8013c76: 3001 adds r0, #1 8013c78: f43f af51 beq.w 8013b1e <_printf_float+0xb6> 8013c7c: e9dd 380d ldrd r3, r8, [sp, #52] @ 0x34 8013c80: 4543 cmp r3, r8 8013c82: db02 blt.n 8013c8a <_printf_float+0x222> 8013c84: 6823 ldr r3, [r4, #0] 8013c86: 07d8 lsls r0, r3, #31 8013c88: d50f bpl.n 8013caa <_printf_float+0x242> 8013c8a: e9dd 2308 ldrd r2, r3, [sp, #32] 8013c8e: 4631 mov r1, r6 8013c90: 4628 mov r0, r5 8013c92: 47b8 blx r7 8013c94: 3001 adds r0, #1 8013c96: f43f af42 beq.w 8013b1e <_printf_float+0xb6> 8013c9a: f04f 0900 mov.w r9, #0 8013c9e: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 8013ca2: f104 0a1a add.w sl, r4, #26 8013ca6: 45c8 cmp r8, r9 8013ca8: dc09 bgt.n 8013cbe <_printf_float+0x256> 8013caa: 6823 ldr r3, [r4, #0] 8013cac: 079b lsls r3, r3, #30 8013cae: f100 8102 bmi.w 8013eb6 <_printf_float+0x44e> 8013cb2: 68e0 ldr r0, [r4, #12] 8013cb4: 9b0f ldr r3, [sp, #60] @ 0x3c 8013cb6: 4298 cmp r0, r3 8013cb8: bfb8 it lt 8013cba: 4618 movlt r0, r3 8013cbc: e731 b.n 8013b22 <_printf_float+0xba> 8013cbe: 2301 movs r3, #1 8013cc0: 4652 mov r2, sl 8013cc2: 4631 mov r1, r6 8013cc4: 4628 mov r0, r5 8013cc6: 47b8 blx r7 8013cc8: 3001 adds r0, #1 8013cca: f43f af28 beq.w 8013b1e <_printf_float+0xb6> 8013cce: f109 0901 add.w r9, r9, #1 8013cd2: e7e8 b.n 8013ca6 <_printf_float+0x23e> 8013cd4: 9b0d ldr r3, [sp, #52] @ 0x34 8013cd6: 2b00 cmp r3, #0 8013cd8: dc38 bgt.n 8013d4c <_printf_float+0x2e4> 8013cda: 2301 movs r3, #1 8013cdc: 4631 mov r1, r6 8013cde: 4628 mov r0, r5 8013ce0: 4a19 ldr r2, [pc, #100] @ (8013d48 <_printf_float+0x2e0>) 8013ce2: 47b8 blx r7 8013ce4: 3001 adds r0, #1 8013ce6: f43f af1a beq.w 8013b1e <_printf_float+0xb6> 8013cea: e9dd 390d ldrd r3, r9, [sp, #52] @ 0x34 8013cee: ea59 0303 orrs.w r3, r9, r3 8013cf2: d102 bne.n 8013cfa <_printf_float+0x292> 8013cf4: 6823 ldr r3, [r4, #0] 8013cf6: 07d9 lsls r1, r3, #31 8013cf8: d5d7 bpl.n 8013caa <_printf_float+0x242> 8013cfa: e9dd 2308 ldrd r2, r3, [sp, #32] 8013cfe: 4631 mov r1, r6 8013d00: 4628 mov r0, r5 8013d02: 47b8 blx r7 8013d04: 3001 adds r0, #1 8013d06: f43f af0a beq.w 8013b1e <_printf_float+0xb6> 8013d0a: f04f 0a00 mov.w sl, #0 8013d0e: f104 0b1a add.w fp, r4, #26 8013d12: 9b0d ldr r3, [sp, #52] @ 0x34 8013d14: 425b negs r3, r3 8013d16: 4553 cmp r3, sl 8013d18: dc01 bgt.n 8013d1e <_printf_float+0x2b6> 8013d1a: 464b mov r3, r9 8013d1c: e793 b.n 8013c46 <_printf_float+0x1de> 8013d1e: 2301 movs r3, #1 8013d20: 465a mov r2, fp 8013d22: 4631 mov r1, r6 8013d24: 4628 mov r0, r5 8013d26: 47b8 blx r7 8013d28: 3001 adds r0, #1 8013d2a: f43f aef8 beq.w 8013b1e <_printf_float+0xb6> 8013d2e: f10a 0a01 add.w sl, sl, #1 8013d32: e7ee b.n 8013d12 <_printf_float+0x2aa> 8013d34: 7fefffff .word 0x7fefffff 8013d38: 08016ee0 .word 0x08016ee0 8013d3c: 08016edc .word 0x08016edc 8013d40: 08016ee8 .word 0x08016ee8 8013d44: 08016ee4 .word 0x08016ee4 8013d48: 08016eec .word 0x08016eec 8013d4c: 6da3 ldr r3, [r4, #88] @ 0x58 8013d4e: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 8013d52: 4553 cmp r3, sl 8013d54: bfa8 it ge 8013d56: 4653 movge r3, sl 8013d58: 2b00 cmp r3, #0 8013d5a: 4699 mov r9, r3 8013d5c: dc36 bgt.n 8013dcc <_printf_float+0x364> 8013d5e: f04f 0b00 mov.w fp, #0 8013d62: ea29 79e9 bic.w r9, r9, r9, asr #31 8013d66: f104 021a add.w r2, r4, #26 8013d6a: 6da3 ldr r3, [r4, #88] @ 0x58 8013d6c: 930a str r3, [sp, #40] @ 0x28 8013d6e: eba3 0309 sub.w r3, r3, r9 8013d72: 455b cmp r3, fp 8013d74: dc31 bgt.n 8013dda <_printf_float+0x372> 8013d76: 9b0d ldr r3, [sp, #52] @ 0x34 8013d78: 459a cmp sl, r3 8013d7a: dc3a bgt.n 8013df2 <_printf_float+0x38a> 8013d7c: 6823 ldr r3, [r4, #0] 8013d7e: 07da lsls r2, r3, #31 8013d80: d437 bmi.n 8013df2 <_printf_float+0x38a> 8013d82: 9b0d ldr r3, [sp, #52] @ 0x34 8013d84: ebaa 0903 sub.w r9, sl, r3 8013d88: 9b0a ldr r3, [sp, #40] @ 0x28 8013d8a: ebaa 0303 sub.w r3, sl, r3 8013d8e: 4599 cmp r9, r3 8013d90: bfa8 it ge 8013d92: 4699 movge r9, r3 8013d94: f1b9 0f00 cmp.w r9, #0 8013d98: dc33 bgt.n 8013e02 <_printf_float+0x39a> 8013d9a: f04f 0800 mov.w r8, #0 8013d9e: ea29 79e9 bic.w r9, r9, r9, asr #31 8013da2: f104 0b1a add.w fp, r4, #26 8013da6: 9b0d ldr r3, [sp, #52] @ 0x34 8013da8: ebaa 0303 sub.w r3, sl, r3 8013dac: eba3 0309 sub.w r3, r3, r9 8013db0: 4543 cmp r3, r8 8013db2: f77f af7a ble.w 8013caa <_printf_float+0x242> 8013db6: 2301 movs r3, #1 8013db8: 465a mov r2, fp 8013dba: 4631 mov r1, r6 8013dbc: 4628 mov r0, r5 8013dbe: 47b8 blx r7 8013dc0: 3001 adds r0, #1 8013dc2: f43f aeac beq.w 8013b1e <_printf_float+0xb6> 8013dc6: f108 0801 add.w r8, r8, #1 8013dca: e7ec b.n 8013da6 <_printf_float+0x33e> 8013dcc: 4642 mov r2, r8 8013dce: 4631 mov r1, r6 8013dd0: 4628 mov r0, r5 8013dd2: 47b8 blx r7 8013dd4: 3001 adds r0, #1 8013dd6: d1c2 bne.n 8013d5e <_printf_float+0x2f6> 8013dd8: e6a1 b.n 8013b1e <_printf_float+0xb6> 8013dda: 2301 movs r3, #1 8013ddc: 4631 mov r1, r6 8013dde: 4628 mov r0, r5 8013de0: 920a str r2, [sp, #40] @ 0x28 8013de2: 47b8 blx r7 8013de4: 3001 adds r0, #1 8013de6: f43f ae9a beq.w 8013b1e <_printf_float+0xb6> 8013dea: 9a0a ldr r2, [sp, #40] @ 0x28 8013dec: f10b 0b01 add.w fp, fp, #1 8013df0: e7bb b.n 8013d6a <_printf_float+0x302> 8013df2: 4631 mov r1, r6 8013df4: e9dd 2308 ldrd r2, r3, [sp, #32] 8013df8: 4628 mov r0, r5 8013dfa: 47b8 blx r7 8013dfc: 3001 adds r0, #1 8013dfe: d1c0 bne.n 8013d82 <_printf_float+0x31a> 8013e00: e68d b.n 8013b1e <_printf_float+0xb6> 8013e02: 9a0a ldr r2, [sp, #40] @ 0x28 8013e04: 464b mov r3, r9 8013e06: 4631 mov r1, r6 8013e08: 4628 mov r0, r5 8013e0a: 4442 add r2, r8 8013e0c: 47b8 blx r7 8013e0e: 3001 adds r0, #1 8013e10: d1c3 bne.n 8013d9a <_printf_float+0x332> 8013e12: e684 b.n 8013b1e <_printf_float+0xb6> 8013e14: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 8013e18: f1ba 0f01 cmp.w sl, #1 8013e1c: dc01 bgt.n 8013e22 <_printf_float+0x3ba> 8013e1e: 07db lsls r3, r3, #31 8013e20: d536 bpl.n 8013e90 <_printf_float+0x428> 8013e22: 2301 movs r3, #1 8013e24: 4642 mov r2, r8 8013e26: 4631 mov r1, r6 8013e28: 4628 mov r0, r5 8013e2a: 47b8 blx r7 8013e2c: 3001 adds r0, #1 8013e2e: f43f ae76 beq.w 8013b1e <_printf_float+0xb6> 8013e32: e9dd 2308 ldrd r2, r3, [sp, #32] 8013e36: 4631 mov r1, r6 8013e38: 4628 mov r0, r5 8013e3a: 47b8 blx r7 8013e3c: 3001 adds r0, #1 8013e3e: f43f ae6e beq.w 8013b1e <_printf_float+0xb6> 8013e42: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 8013e46: 2200 movs r2, #0 8013e48: 2300 movs r3, #0 8013e4a: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff 8013e4e: f7f4 fe17 bl 8008a80 <__aeabi_dcmpeq> 8013e52: b9c0 cbnz r0, 8013e86 <_printf_float+0x41e> 8013e54: 4653 mov r3, sl 8013e56: f108 0201 add.w r2, r8, #1 8013e5a: 4631 mov r1, r6 8013e5c: 4628 mov r0, r5 8013e5e: 47b8 blx r7 8013e60: 3001 adds r0, #1 8013e62: d10c bne.n 8013e7e <_printf_float+0x416> 8013e64: e65b b.n 8013b1e <_printf_float+0xb6> 8013e66: 2301 movs r3, #1 8013e68: 465a mov r2, fp 8013e6a: 4631 mov r1, r6 8013e6c: 4628 mov r0, r5 8013e6e: 47b8 blx r7 8013e70: 3001 adds r0, #1 8013e72: f43f ae54 beq.w 8013b1e <_printf_float+0xb6> 8013e76: f108 0801 add.w r8, r8, #1 8013e7a: 45d0 cmp r8, sl 8013e7c: dbf3 blt.n 8013e66 <_printf_float+0x3fe> 8013e7e: 464b mov r3, r9 8013e80: f104 0250 add.w r2, r4, #80 @ 0x50 8013e84: e6e0 b.n 8013c48 <_printf_float+0x1e0> 8013e86: f04f 0800 mov.w r8, #0 8013e8a: f104 0b1a add.w fp, r4, #26 8013e8e: e7f4 b.n 8013e7a <_printf_float+0x412> 8013e90: 2301 movs r3, #1 8013e92: 4642 mov r2, r8 8013e94: e7e1 b.n 8013e5a <_printf_float+0x3f2> 8013e96: 2301 movs r3, #1 8013e98: 464a mov r2, r9 8013e9a: 4631 mov r1, r6 8013e9c: 4628 mov r0, r5 8013e9e: 47b8 blx r7 8013ea0: 3001 adds r0, #1 8013ea2: f43f ae3c beq.w 8013b1e <_printf_float+0xb6> 8013ea6: f108 0801 add.w r8, r8, #1 8013eaa: 68e3 ldr r3, [r4, #12] 8013eac: 990f ldr r1, [sp, #60] @ 0x3c 8013eae: 1a5b subs r3, r3, r1 8013eb0: 4543 cmp r3, r8 8013eb2: dcf0 bgt.n 8013e96 <_printf_float+0x42e> 8013eb4: e6fd b.n 8013cb2 <_printf_float+0x24a> 8013eb6: f04f 0800 mov.w r8, #0 8013eba: f104 0919 add.w r9, r4, #25 8013ebe: e7f4 b.n 8013eaa <_printf_float+0x442> 08013ec0 <_printf_common>: 8013ec0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8013ec4: 4616 mov r6, r2 8013ec6: 4698 mov r8, r3 8013ec8: 688a ldr r2, [r1, #8] 8013eca: 690b ldr r3, [r1, #16] 8013ecc: 4607 mov r7, r0 8013ece: 4293 cmp r3, r2 8013ed0: bfb8 it lt 8013ed2: 4613 movlt r3, r2 8013ed4: 6033 str r3, [r6, #0] 8013ed6: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 8013eda: 460c mov r4, r1 8013edc: f8dd 9020 ldr.w r9, [sp, #32] 8013ee0: b10a cbz r2, 8013ee6 <_printf_common+0x26> 8013ee2: 3301 adds r3, #1 8013ee4: 6033 str r3, [r6, #0] 8013ee6: 6823 ldr r3, [r4, #0] 8013ee8: 0699 lsls r1, r3, #26 8013eea: bf42 ittt mi 8013eec: 6833 ldrmi r3, [r6, #0] 8013eee: 3302 addmi r3, #2 8013ef0: 6033 strmi r3, [r6, #0] 8013ef2: 6825 ldr r5, [r4, #0] 8013ef4: f015 0506 ands.w r5, r5, #6 8013ef8: d106 bne.n 8013f08 <_printf_common+0x48> 8013efa: f104 0a19 add.w sl, r4, #25 8013efe: 68e3 ldr r3, [r4, #12] 8013f00: 6832 ldr r2, [r6, #0] 8013f02: 1a9b subs r3, r3, r2 8013f04: 42ab cmp r3, r5 8013f06: dc2b bgt.n 8013f60 <_printf_common+0xa0> 8013f08: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 8013f0c: 6822 ldr r2, [r4, #0] 8013f0e: 3b00 subs r3, #0 8013f10: bf18 it ne 8013f12: 2301 movne r3, #1 8013f14: 0692 lsls r2, r2, #26 8013f16: d430 bmi.n 8013f7a <_printf_common+0xba> 8013f18: 4641 mov r1, r8 8013f1a: 4638 mov r0, r7 8013f1c: f104 0243 add.w r2, r4, #67 @ 0x43 8013f20: 47c8 blx r9 8013f22: 3001 adds r0, #1 8013f24: d023 beq.n 8013f6e <_printf_common+0xae> 8013f26: 6823 ldr r3, [r4, #0] 8013f28: 6922 ldr r2, [r4, #16] 8013f2a: f003 0306 and.w r3, r3, #6 8013f2e: 2b04 cmp r3, #4 8013f30: bf14 ite ne 8013f32: 2500 movne r5, #0 8013f34: 6833 ldreq r3, [r6, #0] 8013f36: f04f 0600 mov.w r6, #0 8013f3a: bf08 it eq 8013f3c: 68e5 ldreq r5, [r4, #12] 8013f3e: f104 041a add.w r4, r4, #26 8013f42: bf08 it eq 8013f44: 1aed subeq r5, r5, r3 8013f46: f854 3c12 ldr.w r3, [r4, #-18] 8013f4a: bf08 it eq 8013f4c: ea25 75e5 biceq.w r5, r5, r5, asr #31 8013f50: 4293 cmp r3, r2 8013f52: bfc4 itt gt 8013f54: 1a9b subgt r3, r3, r2 8013f56: 18ed addgt r5, r5, r3 8013f58: 42b5 cmp r5, r6 8013f5a: d11a bne.n 8013f92 <_printf_common+0xd2> 8013f5c: 2000 movs r0, #0 8013f5e: e008 b.n 8013f72 <_printf_common+0xb2> 8013f60: 2301 movs r3, #1 8013f62: 4652 mov r2, sl 8013f64: 4641 mov r1, r8 8013f66: 4638 mov r0, r7 8013f68: 47c8 blx r9 8013f6a: 3001 adds r0, #1 8013f6c: d103 bne.n 8013f76 <_printf_common+0xb6> 8013f6e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8013f72: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8013f76: 3501 adds r5, #1 8013f78: e7c1 b.n 8013efe <_printf_common+0x3e> 8013f7a: 2030 movs r0, #48 @ 0x30 8013f7c: 18e1 adds r1, r4, r3 8013f7e: f881 0043 strb.w r0, [r1, #67] @ 0x43 8013f82: 1c5a adds r2, r3, #1 8013f84: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 8013f88: 4422 add r2, r4 8013f8a: 3302 adds r3, #2 8013f8c: f882 1043 strb.w r1, [r2, #67] @ 0x43 8013f90: e7c2 b.n 8013f18 <_printf_common+0x58> 8013f92: 2301 movs r3, #1 8013f94: 4622 mov r2, r4 8013f96: 4641 mov r1, r8 8013f98: 4638 mov r0, r7 8013f9a: 47c8 blx r9 8013f9c: 3001 adds r0, #1 8013f9e: d0e6 beq.n 8013f6e <_printf_common+0xae> 8013fa0: 3601 adds r6, #1 8013fa2: e7d9 b.n 8013f58 <_printf_common+0x98> 08013fa4 <_printf_i>: 8013fa4: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8013fa8: 7e0f ldrb r7, [r1, #24] 8013faa: 4691 mov r9, r2 8013fac: 2f78 cmp r7, #120 @ 0x78 8013fae: 4680 mov r8, r0 8013fb0: 460c mov r4, r1 8013fb2: 469a mov sl, r3 8013fb4: 9e0c ldr r6, [sp, #48] @ 0x30 8013fb6: f101 0243 add.w r2, r1, #67 @ 0x43 8013fba: d807 bhi.n 8013fcc <_printf_i+0x28> 8013fbc: 2f62 cmp r7, #98 @ 0x62 8013fbe: d80a bhi.n 8013fd6 <_printf_i+0x32> 8013fc0: 2f00 cmp r7, #0 8013fc2: f000 80d1 beq.w 8014168 <_printf_i+0x1c4> 8013fc6: 2f58 cmp r7, #88 @ 0x58 8013fc8: f000 80b8 beq.w 801413c <_printf_i+0x198> 8013fcc: f104 0642 add.w r6, r4, #66 @ 0x42 8013fd0: f884 7042 strb.w r7, [r4, #66] @ 0x42 8013fd4: e03a b.n 801404c <_printf_i+0xa8> 8013fd6: f1a7 0363 sub.w r3, r7, #99 @ 0x63 8013fda: 2b15 cmp r3, #21 8013fdc: d8f6 bhi.n 8013fcc <_printf_i+0x28> 8013fde: a101 add r1, pc, #4 @ (adr r1, 8013fe4 <_printf_i+0x40>) 8013fe0: f851 f023 ldr.w pc, [r1, r3, lsl #2] 8013fe4: 0801403d .word 0x0801403d 8013fe8: 08014051 .word 0x08014051 8013fec: 08013fcd .word 0x08013fcd 8013ff0: 08013fcd .word 0x08013fcd 8013ff4: 08013fcd .word 0x08013fcd 8013ff8: 08013fcd .word 0x08013fcd 8013ffc: 08014051 .word 0x08014051 8014000: 08013fcd .word 0x08013fcd 8014004: 08013fcd .word 0x08013fcd 8014008: 08013fcd .word 0x08013fcd 801400c: 08013fcd .word 0x08013fcd 8014010: 0801414f .word 0x0801414f 8014014: 0801407b .word 0x0801407b 8014018: 08014109 .word 0x08014109 801401c: 08013fcd .word 0x08013fcd 8014020: 08013fcd .word 0x08013fcd 8014024: 08014171 .word 0x08014171 8014028: 08013fcd .word 0x08013fcd 801402c: 0801407b .word 0x0801407b 8014030: 08013fcd .word 0x08013fcd 8014034: 08013fcd .word 0x08013fcd 8014038: 08014111 .word 0x08014111 801403c: 6833 ldr r3, [r6, #0] 801403e: 1d1a adds r2, r3, #4 8014040: 681b ldr r3, [r3, #0] 8014042: 6032 str r2, [r6, #0] 8014044: f104 0642 add.w r6, r4, #66 @ 0x42 8014048: f884 3042 strb.w r3, [r4, #66] @ 0x42 801404c: 2301 movs r3, #1 801404e: e09c b.n 801418a <_printf_i+0x1e6> 8014050: 6833 ldr r3, [r6, #0] 8014052: 6820 ldr r0, [r4, #0] 8014054: 1d19 adds r1, r3, #4 8014056: 6031 str r1, [r6, #0] 8014058: 0606 lsls r6, r0, #24 801405a: d501 bpl.n 8014060 <_printf_i+0xbc> 801405c: 681d ldr r5, [r3, #0] 801405e: e003 b.n 8014068 <_printf_i+0xc4> 8014060: 0645 lsls r5, r0, #25 8014062: d5fb bpl.n 801405c <_printf_i+0xb8> 8014064: f9b3 5000 ldrsh.w r5, [r3] 8014068: 2d00 cmp r5, #0 801406a: da03 bge.n 8014074 <_printf_i+0xd0> 801406c: 232d movs r3, #45 @ 0x2d 801406e: 426d negs r5, r5 8014070: f884 3043 strb.w r3, [r4, #67] @ 0x43 8014074: 230a movs r3, #10 8014076: 4858 ldr r0, [pc, #352] @ (80141d8 <_printf_i+0x234>) 8014078: e011 b.n 801409e <_printf_i+0xfa> 801407a: 6821 ldr r1, [r4, #0] 801407c: 6833 ldr r3, [r6, #0] 801407e: 0608 lsls r0, r1, #24 8014080: f853 5b04 ldr.w r5, [r3], #4 8014084: d402 bmi.n 801408c <_printf_i+0xe8> 8014086: 0649 lsls r1, r1, #25 8014088: bf48 it mi 801408a: b2ad uxthmi r5, r5 801408c: 2f6f cmp r7, #111 @ 0x6f 801408e: 6033 str r3, [r6, #0] 8014090: bf14 ite ne 8014092: 230a movne r3, #10 8014094: 2308 moveq r3, #8 8014096: 4850 ldr r0, [pc, #320] @ (80141d8 <_printf_i+0x234>) 8014098: 2100 movs r1, #0 801409a: f884 1043 strb.w r1, [r4, #67] @ 0x43 801409e: 6866 ldr r6, [r4, #4] 80140a0: 2e00 cmp r6, #0 80140a2: 60a6 str r6, [r4, #8] 80140a4: db05 blt.n 80140b2 <_printf_i+0x10e> 80140a6: 6821 ldr r1, [r4, #0] 80140a8: 432e orrs r6, r5 80140aa: f021 0104 bic.w r1, r1, #4 80140ae: 6021 str r1, [r4, #0] 80140b0: d04b beq.n 801414a <_printf_i+0x1a6> 80140b2: 4616 mov r6, r2 80140b4: fbb5 f1f3 udiv r1, r5, r3 80140b8: fb03 5711 mls r7, r3, r1, r5 80140bc: 5dc7 ldrb r7, [r0, r7] 80140be: f806 7d01 strb.w r7, [r6, #-1]! 80140c2: 462f mov r7, r5 80140c4: 42bb cmp r3, r7 80140c6: 460d mov r5, r1 80140c8: d9f4 bls.n 80140b4 <_printf_i+0x110> 80140ca: 2b08 cmp r3, #8 80140cc: d10b bne.n 80140e6 <_printf_i+0x142> 80140ce: 6823 ldr r3, [r4, #0] 80140d0: 07df lsls r7, r3, #31 80140d2: d508 bpl.n 80140e6 <_printf_i+0x142> 80140d4: 6923 ldr r3, [r4, #16] 80140d6: 6861 ldr r1, [r4, #4] 80140d8: 4299 cmp r1, r3 80140da: bfde ittt le 80140dc: 2330 movle r3, #48 @ 0x30 80140de: f806 3c01 strble.w r3, [r6, #-1] 80140e2: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 80140e6: 1b92 subs r2, r2, r6 80140e8: 6122 str r2, [r4, #16] 80140ea: 464b mov r3, r9 80140ec: 4621 mov r1, r4 80140ee: 4640 mov r0, r8 80140f0: f8cd a000 str.w sl, [sp] 80140f4: aa03 add r2, sp, #12 80140f6: f7ff fee3 bl 8013ec0 <_printf_common> 80140fa: 3001 adds r0, #1 80140fc: d14a bne.n 8014194 <_printf_i+0x1f0> 80140fe: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8014102: b004 add sp, #16 8014104: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8014108: 6823 ldr r3, [r4, #0] 801410a: f043 0320 orr.w r3, r3, #32 801410e: 6023 str r3, [r4, #0] 8014110: 2778 movs r7, #120 @ 0x78 8014112: 4832 ldr r0, [pc, #200] @ (80141dc <_printf_i+0x238>) 8014114: f884 7045 strb.w r7, [r4, #69] @ 0x45 8014118: 6823 ldr r3, [r4, #0] 801411a: 6831 ldr r1, [r6, #0] 801411c: 061f lsls r7, r3, #24 801411e: f851 5b04 ldr.w r5, [r1], #4 8014122: d402 bmi.n 801412a <_printf_i+0x186> 8014124: 065f lsls r7, r3, #25 8014126: bf48 it mi 8014128: b2ad uxthmi r5, r5 801412a: 6031 str r1, [r6, #0] 801412c: 07d9 lsls r1, r3, #31 801412e: bf44 itt mi 8014130: f043 0320 orrmi.w r3, r3, #32 8014134: 6023 strmi r3, [r4, #0] 8014136: b11d cbz r5, 8014140 <_printf_i+0x19c> 8014138: 2310 movs r3, #16 801413a: e7ad b.n 8014098 <_printf_i+0xf4> 801413c: 4826 ldr r0, [pc, #152] @ (80141d8 <_printf_i+0x234>) 801413e: e7e9 b.n 8014114 <_printf_i+0x170> 8014140: 6823 ldr r3, [r4, #0] 8014142: f023 0320 bic.w r3, r3, #32 8014146: 6023 str r3, [r4, #0] 8014148: e7f6 b.n 8014138 <_printf_i+0x194> 801414a: 4616 mov r6, r2 801414c: e7bd b.n 80140ca <_printf_i+0x126> 801414e: 6833 ldr r3, [r6, #0] 8014150: 6825 ldr r5, [r4, #0] 8014152: 1d18 adds r0, r3, #4 8014154: 6961 ldr r1, [r4, #20] 8014156: 6030 str r0, [r6, #0] 8014158: 062e lsls r6, r5, #24 801415a: 681b ldr r3, [r3, #0] 801415c: d501 bpl.n 8014162 <_printf_i+0x1be> 801415e: 6019 str r1, [r3, #0] 8014160: e002 b.n 8014168 <_printf_i+0x1c4> 8014162: 0668 lsls r0, r5, #25 8014164: d5fb bpl.n 801415e <_printf_i+0x1ba> 8014166: 8019 strh r1, [r3, #0] 8014168: 2300 movs r3, #0 801416a: 4616 mov r6, r2 801416c: 6123 str r3, [r4, #16] 801416e: e7bc b.n 80140ea <_printf_i+0x146> 8014170: 6833 ldr r3, [r6, #0] 8014172: 2100 movs r1, #0 8014174: 1d1a adds r2, r3, #4 8014176: 6032 str r2, [r6, #0] 8014178: 681e ldr r6, [r3, #0] 801417a: 6862 ldr r2, [r4, #4] 801417c: 4630 mov r0, r6 801417e: f000 f979 bl 8014474 8014182: b108 cbz r0, 8014188 <_printf_i+0x1e4> 8014184: 1b80 subs r0, r0, r6 8014186: 6060 str r0, [r4, #4] 8014188: 6863 ldr r3, [r4, #4] 801418a: 6123 str r3, [r4, #16] 801418c: 2300 movs r3, #0 801418e: f884 3043 strb.w r3, [r4, #67] @ 0x43 8014192: e7aa b.n 80140ea <_printf_i+0x146> 8014194: 4632 mov r2, r6 8014196: 4649 mov r1, r9 8014198: 4640 mov r0, r8 801419a: 6923 ldr r3, [r4, #16] 801419c: 47d0 blx sl 801419e: 3001 adds r0, #1 80141a0: d0ad beq.n 80140fe <_printf_i+0x15a> 80141a2: 6823 ldr r3, [r4, #0] 80141a4: 079b lsls r3, r3, #30 80141a6: d413 bmi.n 80141d0 <_printf_i+0x22c> 80141a8: 68e0 ldr r0, [r4, #12] 80141aa: 9b03 ldr r3, [sp, #12] 80141ac: 4298 cmp r0, r3 80141ae: bfb8 it lt 80141b0: 4618 movlt r0, r3 80141b2: e7a6 b.n 8014102 <_printf_i+0x15e> 80141b4: 2301 movs r3, #1 80141b6: 4632 mov r2, r6 80141b8: 4649 mov r1, r9 80141ba: 4640 mov r0, r8 80141bc: 47d0 blx sl 80141be: 3001 adds r0, #1 80141c0: d09d beq.n 80140fe <_printf_i+0x15a> 80141c2: 3501 adds r5, #1 80141c4: 68e3 ldr r3, [r4, #12] 80141c6: 9903 ldr r1, [sp, #12] 80141c8: 1a5b subs r3, r3, r1 80141ca: 42ab cmp r3, r5 80141cc: dcf2 bgt.n 80141b4 <_printf_i+0x210> 80141ce: e7eb b.n 80141a8 <_printf_i+0x204> 80141d0: 2500 movs r5, #0 80141d2: f104 0619 add.w r6, r4, #25 80141d6: e7f5 b.n 80141c4 <_printf_i+0x220> 80141d8: 08016eee .word 0x08016eee 80141dc: 08016eff .word 0x08016eff 080141e0 : 80141e0: 2300 movs r3, #0 80141e2: b510 push {r4, lr} 80141e4: 4604 mov r4, r0 80141e6: e9c0 3300 strd r3, r3, [r0] 80141ea: e9c0 3304 strd r3, r3, [r0, #16] 80141ee: 6083 str r3, [r0, #8] 80141f0: 8181 strh r1, [r0, #12] 80141f2: 6643 str r3, [r0, #100] @ 0x64 80141f4: 81c2 strh r2, [r0, #14] 80141f6: 6183 str r3, [r0, #24] 80141f8: 4619 mov r1, r3 80141fa: 2208 movs r2, #8 80141fc: 305c adds r0, #92 @ 0x5c 80141fe: f000 f8ff bl 8014400 8014202: 4b0d ldr r3, [pc, #52] @ (8014238 ) 8014204: 6224 str r4, [r4, #32] 8014206: 6263 str r3, [r4, #36] @ 0x24 8014208: 4b0c ldr r3, [pc, #48] @ (801423c ) 801420a: 62a3 str r3, [r4, #40] @ 0x28 801420c: 4b0c ldr r3, [pc, #48] @ (8014240 ) 801420e: 62e3 str r3, [r4, #44] @ 0x2c 8014210: 4b0c ldr r3, [pc, #48] @ (8014244 ) 8014212: 6323 str r3, [r4, #48] @ 0x30 8014214: 4b0c ldr r3, [pc, #48] @ (8014248 ) 8014216: 429c cmp r4, r3 8014218: d006 beq.n 8014228 801421a: f103 0268 add.w r2, r3, #104 @ 0x68 801421e: 4294 cmp r4, r2 8014220: d002 beq.n 8014228 8014222: 33d0 adds r3, #208 @ 0xd0 8014224: 429c cmp r4, r3 8014226: d105 bne.n 8014234 8014228: f104 0058 add.w r0, r4, #88 @ 0x58 801422c: e8bd 4010 ldmia.w sp!, {r4, lr} 8014230: f000 b918 b.w 8014464 <__retarget_lock_init_recursive> 8014234: bd10 pop {r4, pc} 8014236: bf00 nop 8014238: 08016081 .word 0x08016081 801423c: 080160a3 .word 0x080160a3 8014240: 080160db .word 0x080160db 8014244: 080160ff .word 0x080160ff 8014248: 2000124c .word 0x2000124c 0801424c : 801424c: 4a02 ldr r2, [pc, #8] @ (8014258 ) 801424e: 4903 ldr r1, [pc, #12] @ (801425c ) 8014250: 4803 ldr r0, [pc, #12] @ (8014260 ) 8014252: f000 b8a5 b.w 80143a0 <_fwalk_sglue> 8014256: bf00 nop 8014258: 20000078 .word 0x20000078 801425c: 08015925 .word 0x08015925 8014260: 20000088 .word 0x20000088 08014264 : 8014264: 6841 ldr r1, [r0, #4] 8014266: 4b0c ldr r3, [pc, #48] @ (8014298 ) 8014268: b510 push {r4, lr} 801426a: 4299 cmp r1, r3 801426c: 4604 mov r4, r0 801426e: d001 beq.n 8014274 8014270: f001 fb58 bl 8015924 <_fflush_r> 8014274: 68a1 ldr r1, [r4, #8] 8014276: 4b09 ldr r3, [pc, #36] @ (801429c ) 8014278: 4299 cmp r1, r3 801427a: d002 beq.n 8014282 801427c: 4620 mov r0, r4 801427e: f001 fb51 bl 8015924 <_fflush_r> 8014282: 68e1 ldr r1, [r4, #12] 8014284: 4b06 ldr r3, [pc, #24] @ (80142a0 ) 8014286: 4299 cmp r1, r3 8014288: d004 beq.n 8014294 801428a: 4620 mov r0, r4 801428c: e8bd 4010 ldmia.w sp!, {r4, lr} 8014290: f001 bb48 b.w 8015924 <_fflush_r> 8014294: bd10 pop {r4, pc} 8014296: bf00 nop 8014298: 2000124c .word 0x2000124c 801429c: 200012b4 .word 0x200012b4 80142a0: 2000131c .word 0x2000131c 080142a4 : 80142a4: b510 push {r4, lr} 80142a6: 4b0b ldr r3, [pc, #44] @ (80142d4 ) 80142a8: 4c0b ldr r4, [pc, #44] @ (80142d8 ) 80142aa: 4a0c ldr r2, [pc, #48] @ (80142dc ) 80142ac: 4620 mov r0, r4 80142ae: 601a str r2, [r3, #0] 80142b0: 2104 movs r1, #4 80142b2: 2200 movs r2, #0 80142b4: f7ff ff94 bl 80141e0 80142b8: f104 0068 add.w r0, r4, #104 @ 0x68 80142bc: 2201 movs r2, #1 80142be: 2109 movs r1, #9 80142c0: f7ff ff8e bl 80141e0 80142c4: f104 00d0 add.w r0, r4, #208 @ 0xd0 80142c8: 2202 movs r2, #2 80142ca: e8bd 4010 ldmia.w sp!, {r4, lr} 80142ce: 2112 movs r1, #18 80142d0: f7ff bf86 b.w 80141e0 80142d4: 20001384 .word 0x20001384 80142d8: 2000124c .word 0x2000124c 80142dc: 0801424d .word 0x0801424d 080142e0 <__sfp_lock_acquire>: 80142e0: 4801 ldr r0, [pc, #4] @ (80142e8 <__sfp_lock_acquire+0x8>) 80142e2: f000 b8c0 b.w 8014466 <__retarget_lock_acquire_recursive> 80142e6: bf00 nop 80142e8: 20001389 .word 0x20001389 080142ec <__sfp_lock_release>: 80142ec: 4801 ldr r0, [pc, #4] @ (80142f4 <__sfp_lock_release+0x8>) 80142ee: f000 b8bb b.w 8014468 <__retarget_lock_release_recursive> 80142f2: bf00 nop 80142f4: 20001389 .word 0x20001389 080142f8 <__sinit>: 80142f8: b510 push {r4, lr} 80142fa: 4604 mov r4, r0 80142fc: f7ff fff0 bl 80142e0 <__sfp_lock_acquire> 8014300: 6a23 ldr r3, [r4, #32] 8014302: b11b cbz r3, 801430c <__sinit+0x14> 8014304: e8bd 4010 ldmia.w sp!, {r4, lr} 8014308: f7ff bff0 b.w 80142ec <__sfp_lock_release> 801430c: 4b04 ldr r3, [pc, #16] @ (8014320 <__sinit+0x28>) 801430e: 6223 str r3, [r4, #32] 8014310: 4b04 ldr r3, [pc, #16] @ (8014324 <__sinit+0x2c>) 8014312: 681b ldr r3, [r3, #0] 8014314: 2b00 cmp r3, #0 8014316: d1f5 bne.n 8014304 <__sinit+0xc> 8014318: f7ff ffc4 bl 80142a4 801431c: e7f2 b.n 8014304 <__sinit+0xc> 801431e: bf00 nop 8014320: 08014265 .word 0x08014265 8014324: 20001384 .word 0x20001384 08014328 <_vsniprintf_r>: 8014328: b530 push {r4, r5, lr} 801432a: 4614 mov r4, r2 801432c: 2c00 cmp r4, #0 801432e: 4605 mov r5, r0 8014330: 461a mov r2, r3 8014332: b09b sub sp, #108 @ 0x6c 8014334: da05 bge.n 8014342 <_vsniprintf_r+0x1a> 8014336: 238b movs r3, #139 @ 0x8b 8014338: 6003 str r3, [r0, #0] 801433a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801433e: b01b add sp, #108 @ 0x6c 8014340: bd30 pop {r4, r5, pc} 8014342: f44f 7302 mov.w r3, #520 @ 0x208 8014346: f8ad 300c strh.w r3, [sp, #12] 801434a: f04f 0300 mov.w r3, #0 801434e: 9319 str r3, [sp, #100] @ 0x64 8014350: bf0c ite eq 8014352: 4623 moveq r3, r4 8014354: f104 33ff addne.w r3, r4, #4294967295 @ 0xffffffff 8014358: 9302 str r3, [sp, #8] 801435a: 9305 str r3, [sp, #20] 801435c: f64f 73ff movw r3, #65535 @ 0xffff 8014360: 9100 str r1, [sp, #0] 8014362: 9104 str r1, [sp, #16] 8014364: f8ad 300e strh.w r3, [sp, #14] 8014368: 4669 mov r1, sp 801436a: 9b1e ldr r3, [sp, #120] @ 0x78 801436c: f000 ff74 bl 8015258 <_svfiprintf_r> 8014370: 1c43 adds r3, r0, #1 8014372: bfbc itt lt 8014374: 238b movlt r3, #139 @ 0x8b 8014376: 602b strlt r3, [r5, #0] 8014378: 2c00 cmp r4, #0 801437a: d0e0 beq.n 801433e <_vsniprintf_r+0x16> 801437c: 2200 movs r2, #0 801437e: 9b00 ldr r3, [sp, #0] 8014380: 701a strb r2, [r3, #0] 8014382: e7dc b.n 801433e <_vsniprintf_r+0x16> 08014384 : 8014384: b507 push {r0, r1, r2, lr} 8014386: 9300 str r3, [sp, #0] 8014388: 4613 mov r3, r2 801438a: 460a mov r2, r1 801438c: 4601 mov r1, r0 801438e: 4803 ldr r0, [pc, #12] @ (801439c ) 8014390: 6800 ldr r0, [r0, #0] 8014392: f7ff ffc9 bl 8014328 <_vsniprintf_r> 8014396: b003 add sp, #12 8014398: f85d fb04 ldr.w pc, [sp], #4 801439c: 20000084 .word 0x20000084 080143a0 <_fwalk_sglue>: 80143a0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 80143a4: 4607 mov r7, r0 80143a6: 4688 mov r8, r1 80143a8: 4614 mov r4, r2 80143aa: 2600 movs r6, #0 80143ac: e9d4 9501 ldrd r9, r5, [r4, #4] 80143b0: f1b9 0901 subs.w r9, r9, #1 80143b4: d505 bpl.n 80143c2 <_fwalk_sglue+0x22> 80143b6: 6824 ldr r4, [r4, #0] 80143b8: 2c00 cmp r4, #0 80143ba: d1f7 bne.n 80143ac <_fwalk_sglue+0xc> 80143bc: 4630 mov r0, r6 80143be: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 80143c2: 89ab ldrh r3, [r5, #12] 80143c4: 2b01 cmp r3, #1 80143c6: d907 bls.n 80143d8 <_fwalk_sglue+0x38> 80143c8: f9b5 300e ldrsh.w r3, [r5, #14] 80143cc: 3301 adds r3, #1 80143ce: d003 beq.n 80143d8 <_fwalk_sglue+0x38> 80143d0: 4629 mov r1, r5 80143d2: 4638 mov r0, r7 80143d4: 47c0 blx r8 80143d6: 4306 orrs r6, r0 80143d8: 3568 adds r5, #104 @ 0x68 80143da: e7e9 b.n 80143b0 <_fwalk_sglue+0x10> 080143dc : 80143dc: b40f push {r0, r1, r2, r3} 80143de: b507 push {r0, r1, r2, lr} 80143e0: 4906 ldr r1, [pc, #24] @ (80143fc ) 80143e2: ab04 add r3, sp, #16 80143e4: 6808 ldr r0, [r1, #0] 80143e6: f853 2b04 ldr.w r2, [r3], #4 80143ea: 6881 ldr r1, [r0, #8] 80143ec: 9301 str r3, [sp, #4] 80143ee: f001 f857 bl 80154a0 <_vfiprintf_r> 80143f2: b003 add sp, #12 80143f4: f85d eb04 ldr.w lr, [sp], #4 80143f8: b004 add sp, #16 80143fa: 4770 bx lr 80143fc: 20000084 .word 0x20000084 08014400 : 8014400: 4603 mov r3, r0 8014402: 4402 add r2, r0 8014404: 4293 cmp r3, r2 8014406: d100 bne.n 801440a 8014408: 4770 bx lr 801440a: f803 1b01 strb.w r1, [r3], #1 801440e: e7f9 b.n 8014404 08014410 <__errno>: 8014410: 4b01 ldr r3, [pc, #4] @ (8014418 <__errno+0x8>) 8014412: 6818 ldr r0, [r3, #0] 8014414: 4770 bx lr 8014416: bf00 nop 8014418: 20000084 .word 0x20000084 0801441c <__libc_init_array>: 801441c: b570 push {r4, r5, r6, lr} 801441e: 2600 movs r6, #0 8014420: 4d0c ldr r5, [pc, #48] @ (8014454 <__libc_init_array+0x38>) 8014422: 4c0d ldr r4, [pc, #52] @ (8014458 <__libc_init_array+0x3c>) 8014424: 1b64 subs r4, r4, r5 8014426: 10a4 asrs r4, r4, #2 8014428: 42a6 cmp r6, r4 801442a: d109 bne.n 8014440 <__libc_init_array+0x24> 801442c: f002 f904 bl 8016638 <_init> 8014430: 2600 movs r6, #0 8014432: 4d0a ldr r5, [pc, #40] @ (801445c <__libc_init_array+0x40>) 8014434: 4c0a ldr r4, [pc, #40] @ (8014460 <__libc_init_array+0x44>) 8014436: 1b64 subs r4, r4, r5 8014438: 10a4 asrs r4, r4, #2 801443a: 42a6 cmp r6, r4 801443c: d105 bne.n 801444a <__libc_init_array+0x2e> 801443e: bd70 pop {r4, r5, r6, pc} 8014440: f855 3b04 ldr.w r3, [r5], #4 8014444: 4798 blx r3 8014446: 3601 adds r6, #1 8014448: e7ee b.n 8014428 <__libc_init_array+0xc> 801444a: f855 3b04 ldr.w r3, [r5], #4 801444e: 4798 blx r3 8014450: 3601 adds r6, #1 8014452: e7f2 b.n 801443a <__libc_init_array+0x1e> 8014454: 0801725c .word 0x0801725c 8014458: 0801725c .word 0x0801725c 801445c: 0801725c .word 0x0801725c 8014460: 08017260 .word 0x08017260 08014464 <__retarget_lock_init_recursive>: 8014464: 4770 bx lr 08014466 <__retarget_lock_acquire_recursive>: 8014466: 4770 bx lr 08014468 <__retarget_lock_release_recursive>: 8014468: 4770 bx lr ... 0801446c <_localeconv_r>: 801446c: 4800 ldr r0, [pc, #0] @ (8014470 <_localeconv_r+0x4>) 801446e: 4770 bx lr 8014470: 200001c4 .word 0x200001c4 08014474 : 8014474: 4603 mov r3, r0 8014476: b510 push {r4, lr} 8014478: b2c9 uxtb r1, r1 801447a: 4402 add r2, r0 801447c: 4293 cmp r3, r2 801447e: 4618 mov r0, r3 8014480: d101 bne.n 8014486 8014482: 2000 movs r0, #0 8014484: e003 b.n 801448e 8014486: 7804 ldrb r4, [r0, #0] 8014488: 3301 adds r3, #1 801448a: 428c cmp r4, r1 801448c: d1f6 bne.n 801447c 801448e: bd10 pop {r4, pc} 08014490 : 8014490: 440a add r2, r1 8014492: 4291 cmp r1, r2 8014494: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8014498: d100 bne.n 801449c 801449a: 4770 bx lr 801449c: b510 push {r4, lr} 801449e: f811 4b01 ldrb.w r4, [r1], #1 80144a2: 4291 cmp r1, r2 80144a4: f803 4f01 strb.w r4, [r3, #1]! 80144a8: d1f9 bne.n 801449e 80144aa: bd10 pop {r4, pc} 080144ac <__assert_func>: 80144ac: b51f push {r0, r1, r2, r3, r4, lr} 80144ae: 4614 mov r4, r2 80144b0: 461a mov r2, r3 80144b2: 4b09 ldr r3, [pc, #36] @ (80144d8 <__assert_func+0x2c>) 80144b4: 4605 mov r5, r0 80144b6: 681b ldr r3, [r3, #0] 80144b8: 68d8 ldr r0, [r3, #12] 80144ba: b14c cbz r4, 80144d0 <__assert_func+0x24> 80144bc: 4b07 ldr r3, [pc, #28] @ (80144dc <__assert_func+0x30>) 80144be: e9cd 3401 strd r3, r4, [sp, #4] 80144c2: 9100 str r1, [sp, #0] 80144c4: 462b mov r3, r5 80144c6: 4906 ldr r1, [pc, #24] @ (80144e0 <__assert_func+0x34>) 80144c8: f001 fe1e bl 8016108 80144cc: f001 ffe4 bl 8016498 80144d0: 4b04 ldr r3, [pc, #16] @ (80144e4 <__assert_func+0x38>) 80144d2: 461c mov r4, r3 80144d4: e7f3 b.n 80144be <__assert_func+0x12> 80144d6: bf00 nop 80144d8: 20000084 .word 0x20000084 80144dc: 08016f10 .word 0x08016f10 80144e0: 08016f1d .word 0x08016f1d 80144e4: 08016f4b .word 0x08016f4b 080144e8 : 80144e8: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 80144ec: 6903 ldr r3, [r0, #16] 80144ee: 690c ldr r4, [r1, #16] 80144f0: 4607 mov r7, r0 80144f2: 42a3 cmp r3, r4 80144f4: db7e blt.n 80145f4 80144f6: 3c01 subs r4, #1 80144f8: 00a3 lsls r3, r4, #2 80144fa: f100 0514 add.w r5, r0, #20 80144fe: f101 0814 add.w r8, r1, #20 8014502: 9300 str r3, [sp, #0] 8014504: eb05 0384 add.w r3, r5, r4, lsl #2 8014508: 9301 str r3, [sp, #4] 801450a: f858 3024 ldr.w r3, [r8, r4, lsl #2] 801450e: f855 2024 ldr.w r2, [r5, r4, lsl #2] 8014512: 3301 adds r3, #1 8014514: 429a cmp r2, r3 8014516: fbb2 f6f3 udiv r6, r2, r3 801451a: eb08 0984 add.w r9, r8, r4, lsl #2 801451e: d32e bcc.n 801457e 8014520: f04f 0a00 mov.w sl, #0 8014524: 46c4 mov ip, r8 8014526: 46ae mov lr, r5 8014528: 46d3 mov fp, sl 801452a: f85c 3b04 ldr.w r3, [ip], #4 801452e: b298 uxth r0, r3 8014530: fb06 a000 mla r0, r6, r0, sl 8014534: 0c1b lsrs r3, r3, #16 8014536: 0c02 lsrs r2, r0, #16 8014538: fb06 2303 mla r3, r6, r3, r2 801453c: f8de 2000 ldr.w r2, [lr] 8014540: b280 uxth r0, r0 8014542: b292 uxth r2, r2 8014544: 1a12 subs r2, r2, r0 8014546: 445a add r2, fp 8014548: f8de 0000 ldr.w r0, [lr] 801454c: ea4f 4a13 mov.w sl, r3, lsr #16 8014550: b29b uxth r3, r3 8014552: ebc3 4322 rsb r3, r3, r2, asr #16 8014556: eb03 4310 add.w r3, r3, r0, lsr #16 801455a: b292 uxth r2, r2 801455c: ea42 4203 orr.w r2, r2, r3, lsl #16 8014560: 45e1 cmp r9, ip 8014562: ea4f 4b23 mov.w fp, r3, asr #16 8014566: f84e 2b04 str.w r2, [lr], #4 801456a: d2de bcs.n 801452a 801456c: 9b00 ldr r3, [sp, #0] 801456e: 58eb ldr r3, [r5, r3] 8014570: b92b cbnz r3, 801457e 8014572: 9b01 ldr r3, [sp, #4] 8014574: 3b04 subs r3, #4 8014576: 429d cmp r5, r3 8014578: 461a mov r2, r3 801457a: d32f bcc.n 80145dc 801457c: 613c str r4, [r7, #16] 801457e: 4638 mov r0, r7 8014580: f001 fc76 bl 8015e70 <__mcmp> 8014584: 2800 cmp r0, #0 8014586: db25 blt.n 80145d4 8014588: 4629 mov r1, r5 801458a: 2000 movs r0, #0 801458c: f858 2b04 ldr.w r2, [r8], #4 8014590: f8d1 c000 ldr.w ip, [r1] 8014594: fa1f fe82 uxth.w lr, r2 8014598: fa1f f38c uxth.w r3, ip 801459c: eba3 030e sub.w r3, r3, lr 80145a0: 4403 add r3, r0 80145a2: 0c12 lsrs r2, r2, #16 80145a4: ebc2 4223 rsb r2, r2, r3, asr #16 80145a8: eb02 421c add.w r2, r2, ip, lsr #16 80145ac: b29b uxth r3, r3 80145ae: ea43 4302 orr.w r3, r3, r2, lsl #16 80145b2: 45c1 cmp r9, r8 80145b4: ea4f 4022 mov.w r0, r2, asr #16 80145b8: f841 3b04 str.w r3, [r1], #4 80145bc: d2e6 bcs.n 801458c 80145be: f855 2024 ldr.w r2, [r5, r4, lsl #2] 80145c2: eb05 0384 add.w r3, r5, r4, lsl #2 80145c6: b922 cbnz r2, 80145d2 80145c8: 3b04 subs r3, #4 80145ca: 429d cmp r5, r3 80145cc: 461a mov r2, r3 80145ce: d30b bcc.n 80145e8 80145d0: 613c str r4, [r7, #16] 80145d2: 3601 adds r6, #1 80145d4: 4630 mov r0, r6 80145d6: b003 add sp, #12 80145d8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80145dc: 6812 ldr r2, [r2, #0] 80145de: 3b04 subs r3, #4 80145e0: 2a00 cmp r2, #0 80145e2: d1cb bne.n 801457c 80145e4: 3c01 subs r4, #1 80145e6: e7c6 b.n 8014576 80145e8: 6812 ldr r2, [r2, #0] 80145ea: 3b04 subs r3, #4 80145ec: 2a00 cmp r2, #0 80145ee: d1ef bne.n 80145d0 80145f0: 3c01 subs r4, #1 80145f2: e7ea b.n 80145ca 80145f4: 2000 movs r0, #0 80145f6: e7ee b.n 80145d6 080145f8 <_dtoa_r>: 80145f8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80145fc: 4614 mov r4, r2 80145fe: 461d mov r5, r3 8014600: 69c7 ldr r7, [r0, #28] 8014602: b097 sub sp, #92 @ 0x5c 8014604: 4681 mov r9, r0 8014606: e9cd 4506 strd r4, r5, [sp, #24] 801460a: 9e23 ldr r6, [sp, #140] @ 0x8c 801460c: b97f cbnz r7, 801462e <_dtoa_r+0x36> 801460e: 2010 movs r0, #16 8014610: f001 f85e bl 80156d0 8014614: 4602 mov r2, r0 8014616: f8c9 001c str.w r0, [r9, #28] 801461a: b920 cbnz r0, 8014626 <_dtoa_r+0x2e> 801461c: 21ef movs r1, #239 @ 0xef 801461e: 4bac ldr r3, [pc, #688] @ (80148d0 <_dtoa_r+0x2d8>) 8014620: 48ac ldr r0, [pc, #688] @ (80148d4 <_dtoa_r+0x2dc>) 8014622: f7ff ff43 bl 80144ac <__assert_func> 8014626: e9c0 7701 strd r7, r7, [r0, #4] 801462a: 6007 str r7, [r0, #0] 801462c: 60c7 str r7, [r0, #12] 801462e: f8d9 301c ldr.w r3, [r9, #28] 8014632: 6819 ldr r1, [r3, #0] 8014634: b159 cbz r1, 801464e <_dtoa_r+0x56> 8014636: 685a ldr r2, [r3, #4] 8014638: 2301 movs r3, #1 801463a: 4093 lsls r3, r2 801463c: 604a str r2, [r1, #4] 801463e: 608b str r3, [r1, #8] 8014640: 4648 mov r0, r9 8014642: f001 f9e3 bl 8015a0c <_Bfree> 8014646: 2200 movs r2, #0 8014648: f8d9 301c ldr.w r3, [r9, #28] 801464c: 601a str r2, [r3, #0] 801464e: 1e2b subs r3, r5, #0 8014650: bfaf iteee ge 8014652: 2300 movge r3, #0 8014654: 2201 movlt r2, #1 8014656: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000 801465a: 9307 strlt r3, [sp, #28] 801465c: bfa8 it ge 801465e: 6033 strge r3, [r6, #0] 8014660: f8dd 801c ldr.w r8, [sp, #28] 8014664: 4b9c ldr r3, [pc, #624] @ (80148d8 <_dtoa_r+0x2e0>) 8014666: bfb8 it lt 8014668: 6032 strlt r2, [r6, #0] 801466a: ea33 0308 bics.w r3, r3, r8 801466e: d112 bne.n 8014696 <_dtoa_r+0x9e> 8014670: f242 730f movw r3, #9999 @ 0x270f 8014674: 9a22 ldr r2, [sp, #136] @ 0x88 8014676: 6013 str r3, [r2, #0] 8014678: f3c8 0313 ubfx r3, r8, #0, #20 801467c: 4323 orrs r3, r4 801467e: f000 855e beq.w 801513e <_dtoa_r+0xb46> 8014682: 9b24 ldr r3, [sp, #144] @ 0x90 8014684: f8df a254 ldr.w sl, [pc, #596] @ 80148dc <_dtoa_r+0x2e4> 8014688: 2b00 cmp r3, #0 801468a: f000 8560 beq.w 801514e <_dtoa_r+0xb56> 801468e: f10a 0303 add.w r3, sl, #3 8014692: f000 bd5a b.w 801514a <_dtoa_r+0xb52> 8014696: e9dd 2306 ldrd r2, r3, [sp, #24] 801469a: e9cd 230c strd r2, r3, [sp, #48] @ 0x30 801469e: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 80146a2: 2200 movs r2, #0 80146a4: 2300 movs r3, #0 80146a6: f7f4 f9eb bl 8008a80 <__aeabi_dcmpeq> 80146aa: 4607 mov r7, r0 80146ac: b158 cbz r0, 80146c6 <_dtoa_r+0xce> 80146ae: 2301 movs r3, #1 80146b0: 9a22 ldr r2, [sp, #136] @ 0x88 80146b2: 6013 str r3, [r2, #0] 80146b4: 9b24 ldr r3, [sp, #144] @ 0x90 80146b6: b113 cbz r3, 80146be <_dtoa_r+0xc6> 80146b8: 4b89 ldr r3, [pc, #548] @ (80148e0 <_dtoa_r+0x2e8>) 80146ba: 9a24 ldr r2, [sp, #144] @ 0x90 80146bc: 6013 str r3, [r2, #0] 80146be: f8df a224 ldr.w sl, [pc, #548] @ 80148e4 <_dtoa_r+0x2ec> 80146c2: f000 bd44 b.w 801514e <_dtoa_r+0xb56> 80146c6: ab14 add r3, sp, #80 @ 0x50 80146c8: 9301 str r3, [sp, #4] 80146ca: ab15 add r3, sp, #84 @ 0x54 80146cc: 9300 str r3, [sp, #0] 80146ce: 4648 mov r0, r9 80146d0: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30 80146d4: f001 fc7c bl 8015fd0 <__d2b> 80146d8: f3c8 560a ubfx r6, r8, #20, #11 80146dc: 9003 str r0, [sp, #12] 80146de: 2e00 cmp r6, #0 80146e0: d078 beq.n 80147d4 <_dtoa_r+0x1dc> 80146e2: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 80146e6: 9b0d ldr r3, [sp, #52] @ 0x34 80146e8: f2a6 36ff subw r6, r6, #1023 @ 0x3ff 80146ec: f3c3 0313 ubfx r3, r3, #0, #20 80146f0: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000 80146f4: f443 1340 orr.w r3, r3, #3145728 @ 0x300000 80146f8: 9712 str r7, [sp, #72] @ 0x48 80146fa: 4619 mov r1, r3 80146fc: 2200 movs r2, #0 80146fe: 4b7a ldr r3, [pc, #488] @ (80148e8 <_dtoa_r+0x2f0>) 8014700: f7f3 fd9e bl 8008240 <__aeabi_dsub> 8014704: a36c add r3, pc, #432 @ (adr r3, 80148b8 <_dtoa_r+0x2c0>) 8014706: e9d3 2300 ldrd r2, r3, [r3] 801470a: f7f3 ff51 bl 80085b0 <__aeabi_dmul> 801470e: a36c add r3, pc, #432 @ (adr r3, 80148c0 <_dtoa_r+0x2c8>) 8014710: e9d3 2300 ldrd r2, r3, [r3] 8014714: f7f3 fd96 bl 8008244 <__adddf3> 8014718: 4604 mov r4, r0 801471a: 4630 mov r0, r6 801471c: 460d mov r5, r1 801471e: f7f3 fedd bl 80084dc <__aeabi_i2d> 8014722: a369 add r3, pc, #420 @ (adr r3, 80148c8 <_dtoa_r+0x2d0>) 8014724: e9d3 2300 ldrd r2, r3, [r3] 8014728: f7f3 ff42 bl 80085b0 <__aeabi_dmul> 801472c: 4602 mov r2, r0 801472e: 460b mov r3, r1 8014730: 4620 mov r0, r4 8014732: 4629 mov r1, r5 8014734: f7f3 fd86 bl 8008244 <__adddf3> 8014738: 4604 mov r4, r0 801473a: 460d mov r5, r1 801473c: f7f4 f9e8 bl 8008b10 <__aeabi_d2iz> 8014740: 2200 movs r2, #0 8014742: 4607 mov r7, r0 8014744: 2300 movs r3, #0 8014746: 4620 mov r0, r4 8014748: 4629 mov r1, r5 801474a: f7f4 f9a3 bl 8008a94 <__aeabi_dcmplt> 801474e: b140 cbz r0, 8014762 <_dtoa_r+0x16a> 8014750: 4638 mov r0, r7 8014752: f7f3 fec3 bl 80084dc <__aeabi_i2d> 8014756: 4622 mov r2, r4 8014758: 462b mov r3, r5 801475a: f7f4 f991 bl 8008a80 <__aeabi_dcmpeq> 801475e: b900 cbnz r0, 8014762 <_dtoa_r+0x16a> 8014760: 3f01 subs r7, #1 8014762: 2f16 cmp r7, #22 8014764: d854 bhi.n 8014810 <_dtoa_r+0x218> 8014766: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 801476a: 4b60 ldr r3, [pc, #384] @ (80148ec <_dtoa_r+0x2f4>) 801476c: eb03 03c7 add.w r3, r3, r7, lsl #3 8014770: e9d3 2300 ldrd r2, r3, [r3] 8014774: f7f4 f98e bl 8008a94 <__aeabi_dcmplt> 8014778: 2800 cmp r0, #0 801477a: d04b beq.n 8014814 <_dtoa_r+0x21c> 801477c: 2300 movs r3, #0 801477e: 3f01 subs r7, #1 8014780: 930f str r3, [sp, #60] @ 0x3c 8014782: 9b14 ldr r3, [sp, #80] @ 0x50 8014784: 1b9b subs r3, r3, r6 8014786: 1e5a subs r2, r3, #1 8014788: bf49 itett mi 801478a: f1c3 0301 rsbmi r3, r3, #1 801478e: 2300 movpl r3, #0 8014790: 9304 strmi r3, [sp, #16] 8014792: 2300 movmi r3, #0 8014794: 9209 str r2, [sp, #36] @ 0x24 8014796: bf54 ite pl 8014798: 9304 strpl r3, [sp, #16] 801479a: 9309 strmi r3, [sp, #36] @ 0x24 801479c: 2f00 cmp r7, #0 801479e: db3b blt.n 8014818 <_dtoa_r+0x220> 80147a0: 9b09 ldr r3, [sp, #36] @ 0x24 80147a2: 970e str r7, [sp, #56] @ 0x38 80147a4: 443b add r3, r7 80147a6: 9309 str r3, [sp, #36] @ 0x24 80147a8: 2300 movs r3, #0 80147aa: 930a str r3, [sp, #40] @ 0x28 80147ac: 9b20 ldr r3, [sp, #128] @ 0x80 80147ae: 2b09 cmp r3, #9 80147b0: d865 bhi.n 801487e <_dtoa_r+0x286> 80147b2: 2b05 cmp r3, #5 80147b4: bfc4 itt gt 80147b6: 3b04 subgt r3, #4 80147b8: 9320 strgt r3, [sp, #128] @ 0x80 80147ba: 9b20 ldr r3, [sp, #128] @ 0x80 80147bc: bfc8 it gt 80147be: 2400 movgt r4, #0 80147c0: f1a3 0302 sub.w r3, r3, #2 80147c4: bfd8 it le 80147c6: 2401 movle r4, #1 80147c8: 2b03 cmp r3, #3 80147ca: d864 bhi.n 8014896 <_dtoa_r+0x29e> 80147cc: e8df f003 tbb [pc, r3] 80147d0: 2c385553 .word 0x2c385553 80147d4: e9dd 6314 ldrd r6, r3, [sp, #80] @ 0x50 80147d8: 441e add r6, r3 80147da: f206 4332 addw r3, r6, #1074 @ 0x432 80147de: 2b20 cmp r3, #32 80147e0: bfc1 itttt gt 80147e2: f1c3 0340 rsbgt r3, r3, #64 @ 0x40 80147e6: fa08 f803 lslgt.w r8, r8, r3 80147ea: f206 4312 addwgt r3, r6, #1042 @ 0x412 80147ee: fa24 f303 lsrgt.w r3, r4, r3 80147f2: bfd6 itet le 80147f4: f1c3 0320 rsble r3, r3, #32 80147f8: ea48 0003 orrgt.w r0, r8, r3 80147fc: fa04 f003 lslle.w r0, r4, r3 8014800: f7f3 fe5c bl 80084bc <__aeabi_ui2d> 8014804: 2201 movs r2, #1 8014806: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000 801480a: 3e01 subs r6, #1 801480c: 9212 str r2, [sp, #72] @ 0x48 801480e: e774 b.n 80146fa <_dtoa_r+0x102> 8014810: 2301 movs r3, #1 8014812: e7b5 b.n 8014780 <_dtoa_r+0x188> 8014814: 900f str r0, [sp, #60] @ 0x3c 8014816: e7b4 b.n 8014782 <_dtoa_r+0x18a> 8014818: 9b04 ldr r3, [sp, #16] 801481a: 1bdb subs r3, r3, r7 801481c: 9304 str r3, [sp, #16] 801481e: 427b negs r3, r7 8014820: 930a str r3, [sp, #40] @ 0x28 8014822: 2300 movs r3, #0 8014824: 930e str r3, [sp, #56] @ 0x38 8014826: e7c1 b.n 80147ac <_dtoa_r+0x1b4> 8014828: 2301 movs r3, #1 801482a: 930b str r3, [sp, #44] @ 0x2c 801482c: 9b21 ldr r3, [sp, #132] @ 0x84 801482e: eb07 0b03 add.w fp, r7, r3 8014832: f10b 0301 add.w r3, fp, #1 8014836: 2b01 cmp r3, #1 8014838: 9308 str r3, [sp, #32] 801483a: bfb8 it lt 801483c: 2301 movlt r3, #1 801483e: e006 b.n 801484e <_dtoa_r+0x256> 8014840: 2301 movs r3, #1 8014842: 930b str r3, [sp, #44] @ 0x2c 8014844: 9b21 ldr r3, [sp, #132] @ 0x84 8014846: 2b00 cmp r3, #0 8014848: dd28 ble.n 801489c <_dtoa_r+0x2a4> 801484a: 469b mov fp, r3 801484c: 9308 str r3, [sp, #32] 801484e: 2100 movs r1, #0 8014850: 2204 movs r2, #4 8014852: f8d9 001c ldr.w r0, [r9, #28] 8014856: f102 0514 add.w r5, r2, #20 801485a: 429d cmp r5, r3 801485c: d926 bls.n 80148ac <_dtoa_r+0x2b4> 801485e: 6041 str r1, [r0, #4] 8014860: 4648 mov r0, r9 8014862: f001 f893 bl 801598c <_Balloc> 8014866: 4682 mov sl, r0 8014868: 2800 cmp r0, #0 801486a: d143 bne.n 80148f4 <_dtoa_r+0x2fc> 801486c: 4602 mov r2, r0 801486e: f240 11af movw r1, #431 @ 0x1af 8014872: 4b1f ldr r3, [pc, #124] @ (80148f0 <_dtoa_r+0x2f8>) 8014874: e6d4 b.n 8014620 <_dtoa_r+0x28> 8014876: 2300 movs r3, #0 8014878: e7e3 b.n 8014842 <_dtoa_r+0x24a> 801487a: 2300 movs r3, #0 801487c: e7d5 b.n 801482a <_dtoa_r+0x232> 801487e: 2401 movs r4, #1 8014880: 2300 movs r3, #0 8014882: 940b str r4, [sp, #44] @ 0x2c 8014884: 9320 str r3, [sp, #128] @ 0x80 8014886: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff 801488a: 2200 movs r2, #0 801488c: 2312 movs r3, #18 801488e: f8cd b020 str.w fp, [sp, #32] 8014892: 9221 str r2, [sp, #132] @ 0x84 8014894: e7db b.n 801484e <_dtoa_r+0x256> 8014896: 2301 movs r3, #1 8014898: 930b str r3, [sp, #44] @ 0x2c 801489a: e7f4 b.n 8014886 <_dtoa_r+0x28e> 801489c: f04f 0b01 mov.w fp, #1 80148a0: 465b mov r3, fp 80148a2: f8cd b020 str.w fp, [sp, #32] 80148a6: f8cd b084 str.w fp, [sp, #132] @ 0x84 80148aa: e7d0 b.n 801484e <_dtoa_r+0x256> 80148ac: 3101 adds r1, #1 80148ae: 0052 lsls r2, r2, #1 80148b0: e7d1 b.n 8014856 <_dtoa_r+0x25e> 80148b2: bf00 nop 80148b4: f3af 8000 nop.w 80148b8: 636f4361 .word 0x636f4361 80148bc: 3fd287a7 .word 0x3fd287a7 80148c0: 8b60c8b3 .word 0x8b60c8b3 80148c4: 3fc68a28 .word 0x3fc68a28 80148c8: 509f79fb .word 0x509f79fb 80148cc: 3fd34413 .word 0x3fd34413 80148d0: 08016f59 .word 0x08016f59 80148d4: 08016f70 .word 0x08016f70 80148d8: 7ff00000 .word 0x7ff00000 80148dc: 08016f55 .word 0x08016f55 80148e0: 08016eed .word 0x08016eed 80148e4: 08016eec .word 0x08016eec 80148e8: 3ff80000 .word 0x3ff80000 80148ec: 08017088 .word 0x08017088 80148f0: 08016fc8 .word 0x08016fc8 80148f4: f8d9 301c ldr.w r3, [r9, #28] 80148f8: 6018 str r0, [r3, #0] 80148fa: 9b08 ldr r3, [sp, #32] 80148fc: 2b0e cmp r3, #14 80148fe: f200 80a1 bhi.w 8014a44 <_dtoa_r+0x44c> 8014902: 2c00 cmp r4, #0 8014904: f000 809e beq.w 8014a44 <_dtoa_r+0x44c> 8014908: 2f00 cmp r7, #0 801490a: dd33 ble.n 8014974 <_dtoa_r+0x37c> 801490c: 4b9c ldr r3, [pc, #624] @ (8014b80 <_dtoa_r+0x588>) 801490e: f007 020f and.w r2, r7, #15 8014912: eb03 03c2 add.w r3, r3, r2, lsl #3 8014916: 05f8 lsls r0, r7, #23 8014918: e9d3 3400 ldrd r3, r4, [r3] 801491c: e9cd 3410 strd r3, r4, [sp, #64] @ 0x40 8014920: ea4f 1427 mov.w r4, r7, asr #4 8014924: d516 bpl.n 8014954 <_dtoa_r+0x35c> 8014926: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 801492a: 4b96 ldr r3, [pc, #600] @ (8014b84 <_dtoa_r+0x58c>) 801492c: 2603 movs r6, #3 801492e: e9d3 2308 ldrd r2, r3, [r3, #32] 8014932: f7f3 ff67 bl 8008804 <__aeabi_ddiv> 8014936: e9cd 0106 strd r0, r1, [sp, #24] 801493a: f004 040f and.w r4, r4, #15 801493e: 4d91 ldr r5, [pc, #580] @ (8014b84 <_dtoa_r+0x58c>) 8014940: b954 cbnz r4, 8014958 <_dtoa_r+0x360> 8014942: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8014946: e9dd 0106 ldrd r0, r1, [sp, #24] 801494a: f7f3 ff5b bl 8008804 <__aeabi_ddiv> 801494e: e9cd 0106 strd r0, r1, [sp, #24] 8014952: e028 b.n 80149a6 <_dtoa_r+0x3ae> 8014954: 2602 movs r6, #2 8014956: e7f2 b.n 801493e <_dtoa_r+0x346> 8014958: 07e1 lsls r1, r4, #31 801495a: d508 bpl.n 801496e <_dtoa_r+0x376> 801495c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8014960: e9d5 2300 ldrd r2, r3, [r5] 8014964: f7f3 fe24 bl 80085b0 <__aeabi_dmul> 8014968: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 801496c: 3601 adds r6, #1 801496e: 1064 asrs r4, r4, #1 8014970: 3508 adds r5, #8 8014972: e7e5 b.n 8014940 <_dtoa_r+0x348> 8014974: f000 80af beq.w 8014ad6 <_dtoa_r+0x4de> 8014978: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 801497c: 427c negs r4, r7 801497e: 4b80 ldr r3, [pc, #512] @ (8014b80 <_dtoa_r+0x588>) 8014980: f004 020f and.w r2, r4, #15 8014984: eb03 03c2 add.w r3, r3, r2, lsl #3 8014988: e9d3 2300 ldrd r2, r3, [r3] 801498c: f7f3 fe10 bl 80085b0 <__aeabi_dmul> 8014990: 2602 movs r6, #2 8014992: 2300 movs r3, #0 8014994: e9cd 0106 strd r0, r1, [sp, #24] 8014998: 4d7a ldr r5, [pc, #488] @ (8014b84 <_dtoa_r+0x58c>) 801499a: 1124 asrs r4, r4, #4 801499c: 2c00 cmp r4, #0 801499e: f040 808f bne.w 8014ac0 <_dtoa_r+0x4c8> 80149a2: 2b00 cmp r3, #0 80149a4: d1d3 bne.n 801494e <_dtoa_r+0x356> 80149a6: e9dd 4506 ldrd r4, r5, [sp, #24] 80149aa: 9b0f ldr r3, [sp, #60] @ 0x3c 80149ac: 2b00 cmp r3, #0 80149ae: f000 8094 beq.w 8014ada <_dtoa_r+0x4e2> 80149b2: 2200 movs r2, #0 80149b4: 4620 mov r0, r4 80149b6: 4629 mov r1, r5 80149b8: 4b73 ldr r3, [pc, #460] @ (8014b88 <_dtoa_r+0x590>) 80149ba: f7f4 f86b bl 8008a94 <__aeabi_dcmplt> 80149be: 2800 cmp r0, #0 80149c0: f000 808b beq.w 8014ada <_dtoa_r+0x4e2> 80149c4: 9b08 ldr r3, [sp, #32] 80149c6: 2b00 cmp r3, #0 80149c8: f000 8087 beq.w 8014ada <_dtoa_r+0x4e2> 80149cc: f1bb 0f00 cmp.w fp, #0 80149d0: dd34 ble.n 8014a3c <_dtoa_r+0x444> 80149d2: 4620 mov r0, r4 80149d4: 2200 movs r2, #0 80149d6: 4629 mov r1, r5 80149d8: 4b6c ldr r3, [pc, #432] @ (8014b8c <_dtoa_r+0x594>) 80149da: f7f3 fde9 bl 80085b0 <__aeabi_dmul> 80149de: 465c mov r4, fp 80149e0: e9cd 0106 strd r0, r1, [sp, #24] 80149e4: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 80149e8: 3601 adds r6, #1 80149ea: 4630 mov r0, r6 80149ec: f7f3 fd76 bl 80084dc <__aeabi_i2d> 80149f0: e9dd 2306 ldrd r2, r3, [sp, #24] 80149f4: f7f3 fddc bl 80085b0 <__aeabi_dmul> 80149f8: 2200 movs r2, #0 80149fa: 4b65 ldr r3, [pc, #404] @ (8014b90 <_dtoa_r+0x598>) 80149fc: f7f3 fc22 bl 8008244 <__adddf3> 8014a00: 4605 mov r5, r0 8014a02: f1a1 7650 sub.w r6, r1, #54525952 @ 0x3400000 8014a06: 2c00 cmp r4, #0 8014a08: d16a bne.n 8014ae0 <_dtoa_r+0x4e8> 8014a0a: e9dd 0106 ldrd r0, r1, [sp, #24] 8014a0e: 2200 movs r2, #0 8014a10: 4b60 ldr r3, [pc, #384] @ (8014b94 <_dtoa_r+0x59c>) 8014a12: f7f3 fc15 bl 8008240 <__aeabi_dsub> 8014a16: 4602 mov r2, r0 8014a18: 460b mov r3, r1 8014a1a: e9cd 2306 strd r2, r3, [sp, #24] 8014a1e: 462a mov r2, r5 8014a20: 4633 mov r3, r6 8014a22: f7f4 f855 bl 8008ad0 <__aeabi_dcmpgt> 8014a26: 2800 cmp r0, #0 8014a28: f040 8298 bne.w 8014f5c <_dtoa_r+0x964> 8014a2c: e9dd 0106 ldrd r0, r1, [sp, #24] 8014a30: 462a mov r2, r5 8014a32: f106 4300 add.w r3, r6, #2147483648 @ 0x80000000 8014a36: f7f4 f82d bl 8008a94 <__aeabi_dcmplt> 8014a3a: bb38 cbnz r0, 8014a8c <_dtoa_r+0x494> 8014a3c: e9dd 340c ldrd r3, r4, [sp, #48] @ 0x30 8014a40: e9cd 3406 strd r3, r4, [sp, #24] 8014a44: 9b15 ldr r3, [sp, #84] @ 0x54 8014a46: 2b00 cmp r3, #0 8014a48: f2c0 8157 blt.w 8014cfa <_dtoa_r+0x702> 8014a4c: 2f0e cmp r7, #14 8014a4e: f300 8154 bgt.w 8014cfa <_dtoa_r+0x702> 8014a52: 4b4b ldr r3, [pc, #300] @ (8014b80 <_dtoa_r+0x588>) 8014a54: eb03 03c7 add.w r3, r3, r7, lsl #3 8014a58: e9d3 3400 ldrd r3, r4, [r3] 8014a5c: e9cd 3404 strd r3, r4, [sp, #16] 8014a60: 9b21 ldr r3, [sp, #132] @ 0x84 8014a62: 2b00 cmp r3, #0 8014a64: f280 80e5 bge.w 8014c32 <_dtoa_r+0x63a> 8014a68: 9b08 ldr r3, [sp, #32] 8014a6a: 2b00 cmp r3, #0 8014a6c: f300 80e1 bgt.w 8014c32 <_dtoa_r+0x63a> 8014a70: d10c bne.n 8014a8c <_dtoa_r+0x494> 8014a72: e9dd 0104 ldrd r0, r1, [sp, #16] 8014a76: 2200 movs r2, #0 8014a78: 4b46 ldr r3, [pc, #280] @ (8014b94 <_dtoa_r+0x59c>) 8014a7a: f7f3 fd99 bl 80085b0 <__aeabi_dmul> 8014a7e: e9dd 2306 ldrd r2, r3, [sp, #24] 8014a82: f7f4 f81b bl 8008abc <__aeabi_dcmpge> 8014a86: 2800 cmp r0, #0 8014a88: f000 8266 beq.w 8014f58 <_dtoa_r+0x960> 8014a8c: 2400 movs r4, #0 8014a8e: 4625 mov r5, r4 8014a90: 9b21 ldr r3, [sp, #132] @ 0x84 8014a92: 4656 mov r6, sl 8014a94: ea6f 0803 mvn.w r8, r3 8014a98: 2700 movs r7, #0 8014a9a: 4621 mov r1, r4 8014a9c: 4648 mov r0, r9 8014a9e: f000 ffb5 bl 8015a0c <_Bfree> 8014aa2: 2d00 cmp r5, #0 8014aa4: f000 80bd beq.w 8014c22 <_dtoa_r+0x62a> 8014aa8: b12f cbz r7, 8014ab6 <_dtoa_r+0x4be> 8014aaa: 42af cmp r7, r5 8014aac: d003 beq.n 8014ab6 <_dtoa_r+0x4be> 8014aae: 4639 mov r1, r7 8014ab0: 4648 mov r0, r9 8014ab2: f000 ffab bl 8015a0c <_Bfree> 8014ab6: 4629 mov r1, r5 8014ab8: 4648 mov r0, r9 8014aba: f000 ffa7 bl 8015a0c <_Bfree> 8014abe: e0b0 b.n 8014c22 <_dtoa_r+0x62a> 8014ac0: 07e2 lsls r2, r4, #31 8014ac2: d505 bpl.n 8014ad0 <_dtoa_r+0x4d8> 8014ac4: e9d5 2300 ldrd r2, r3, [r5] 8014ac8: f7f3 fd72 bl 80085b0 <__aeabi_dmul> 8014acc: 2301 movs r3, #1 8014ace: 3601 adds r6, #1 8014ad0: 1064 asrs r4, r4, #1 8014ad2: 3508 adds r5, #8 8014ad4: e762 b.n 801499c <_dtoa_r+0x3a4> 8014ad6: 2602 movs r6, #2 8014ad8: e765 b.n 80149a6 <_dtoa_r+0x3ae> 8014ada: 46b8 mov r8, r7 8014adc: 9c08 ldr r4, [sp, #32] 8014ade: e784 b.n 80149ea <_dtoa_r+0x3f2> 8014ae0: 4b27 ldr r3, [pc, #156] @ (8014b80 <_dtoa_r+0x588>) 8014ae2: 990b ldr r1, [sp, #44] @ 0x2c 8014ae4: eb03 03c4 add.w r3, r3, r4, lsl #3 8014ae8: e953 2302 ldrd r2, r3, [r3, #-8] 8014aec: 4454 add r4, sl 8014aee: 2900 cmp r1, #0 8014af0: d054 beq.n 8014b9c <_dtoa_r+0x5a4> 8014af2: 2000 movs r0, #0 8014af4: 4928 ldr r1, [pc, #160] @ (8014b98 <_dtoa_r+0x5a0>) 8014af6: f7f3 fe85 bl 8008804 <__aeabi_ddiv> 8014afa: 4633 mov r3, r6 8014afc: 462a mov r2, r5 8014afe: f7f3 fb9f bl 8008240 <__aeabi_dsub> 8014b02: 4656 mov r6, sl 8014b04: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 8014b08: e9dd 0106 ldrd r0, r1, [sp, #24] 8014b0c: f7f4 f800 bl 8008b10 <__aeabi_d2iz> 8014b10: 4605 mov r5, r0 8014b12: f7f3 fce3 bl 80084dc <__aeabi_i2d> 8014b16: 4602 mov r2, r0 8014b18: 460b mov r3, r1 8014b1a: e9dd 0106 ldrd r0, r1, [sp, #24] 8014b1e: f7f3 fb8f bl 8008240 <__aeabi_dsub> 8014b22: 4602 mov r2, r0 8014b24: 460b mov r3, r1 8014b26: 3530 adds r5, #48 @ 0x30 8014b28: e9cd 2306 strd r2, r3, [sp, #24] 8014b2c: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8014b30: f806 5b01 strb.w r5, [r6], #1 8014b34: f7f3 ffae bl 8008a94 <__aeabi_dcmplt> 8014b38: 2800 cmp r0, #0 8014b3a: d172 bne.n 8014c22 <_dtoa_r+0x62a> 8014b3c: e9dd 2306 ldrd r2, r3, [sp, #24] 8014b40: 2000 movs r0, #0 8014b42: 4911 ldr r1, [pc, #68] @ (8014b88 <_dtoa_r+0x590>) 8014b44: f7f3 fb7c bl 8008240 <__aeabi_dsub> 8014b48: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8014b4c: f7f3 ffa2 bl 8008a94 <__aeabi_dcmplt> 8014b50: 2800 cmp r0, #0 8014b52: f040 80b4 bne.w 8014cbe <_dtoa_r+0x6c6> 8014b56: 42a6 cmp r6, r4 8014b58: f43f af70 beq.w 8014a3c <_dtoa_r+0x444> 8014b5c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8014b60: 2200 movs r2, #0 8014b62: 4b0a ldr r3, [pc, #40] @ (8014b8c <_dtoa_r+0x594>) 8014b64: f7f3 fd24 bl 80085b0 <__aeabi_dmul> 8014b68: 2200 movs r2, #0 8014b6a: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 8014b6e: e9dd 0106 ldrd r0, r1, [sp, #24] 8014b72: 4b06 ldr r3, [pc, #24] @ (8014b8c <_dtoa_r+0x594>) 8014b74: f7f3 fd1c bl 80085b0 <__aeabi_dmul> 8014b78: e9cd 0106 strd r0, r1, [sp, #24] 8014b7c: e7c4 b.n 8014b08 <_dtoa_r+0x510> 8014b7e: bf00 nop 8014b80: 08017088 .word 0x08017088 8014b84: 08017060 .word 0x08017060 8014b88: 3ff00000 .word 0x3ff00000 8014b8c: 40240000 .word 0x40240000 8014b90: 401c0000 .word 0x401c0000 8014b94: 40140000 .word 0x40140000 8014b98: 3fe00000 .word 0x3fe00000 8014b9c: 4631 mov r1, r6 8014b9e: 4628 mov r0, r5 8014ba0: f7f3 fd06 bl 80085b0 <__aeabi_dmul> 8014ba4: 4656 mov r6, sl 8014ba6: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 8014baa: 9413 str r4, [sp, #76] @ 0x4c 8014bac: e9dd 0106 ldrd r0, r1, [sp, #24] 8014bb0: f7f3 ffae bl 8008b10 <__aeabi_d2iz> 8014bb4: 4605 mov r5, r0 8014bb6: f7f3 fc91 bl 80084dc <__aeabi_i2d> 8014bba: 4602 mov r2, r0 8014bbc: 460b mov r3, r1 8014bbe: e9dd 0106 ldrd r0, r1, [sp, #24] 8014bc2: f7f3 fb3d bl 8008240 <__aeabi_dsub> 8014bc6: 4602 mov r2, r0 8014bc8: 460b mov r3, r1 8014bca: 3530 adds r5, #48 @ 0x30 8014bcc: f806 5b01 strb.w r5, [r6], #1 8014bd0: 42a6 cmp r6, r4 8014bd2: e9cd 2306 strd r2, r3, [sp, #24] 8014bd6: f04f 0200 mov.w r2, #0 8014bda: d124 bne.n 8014c26 <_dtoa_r+0x62e> 8014bdc: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8014be0: 4bae ldr r3, [pc, #696] @ (8014e9c <_dtoa_r+0x8a4>) 8014be2: f7f3 fb2f bl 8008244 <__adddf3> 8014be6: 4602 mov r2, r0 8014be8: 460b mov r3, r1 8014bea: e9dd 0106 ldrd r0, r1, [sp, #24] 8014bee: f7f3 ff6f bl 8008ad0 <__aeabi_dcmpgt> 8014bf2: 2800 cmp r0, #0 8014bf4: d163 bne.n 8014cbe <_dtoa_r+0x6c6> 8014bf6: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8014bfa: 2000 movs r0, #0 8014bfc: 49a7 ldr r1, [pc, #668] @ (8014e9c <_dtoa_r+0x8a4>) 8014bfe: f7f3 fb1f bl 8008240 <__aeabi_dsub> 8014c02: 4602 mov r2, r0 8014c04: 460b mov r3, r1 8014c06: e9dd 0106 ldrd r0, r1, [sp, #24] 8014c0a: f7f3 ff43 bl 8008a94 <__aeabi_dcmplt> 8014c0e: 2800 cmp r0, #0 8014c10: f43f af14 beq.w 8014a3c <_dtoa_r+0x444> 8014c14: 9e13 ldr r6, [sp, #76] @ 0x4c 8014c16: 1e73 subs r3, r6, #1 8014c18: 9313 str r3, [sp, #76] @ 0x4c 8014c1a: f816 3c01 ldrb.w r3, [r6, #-1] 8014c1e: 2b30 cmp r3, #48 @ 0x30 8014c20: d0f8 beq.n 8014c14 <_dtoa_r+0x61c> 8014c22: 4647 mov r7, r8 8014c24: e03b b.n 8014c9e <_dtoa_r+0x6a6> 8014c26: 4b9e ldr r3, [pc, #632] @ (8014ea0 <_dtoa_r+0x8a8>) 8014c28: f7f3 fcc2 bl 80085b0 <__aeabi_dmul> 8014c2c: e9cd 0106 strd r0, r1, [sp, #24] 8014c30: e7bc b.n 8014bac <_dtoa_r+0x5b4> 8014c32: 4656 mov r6, sl 8014c34: e9dd 4506 ldrd r4, r5, [sp, #24] 8014c38: e9dd 2304 ldrd r2, r3, [sp, #16] 8014c3c: 4620 mov r0, r4 8014c3e: 4629 mov r1, r5 8014c40: f7f3 fde0 bl 8008804 <__aeabi_ddiv> 8014c44: f7f3 ff64 bl 8008b10 <__aeabi_d2iz> 8014c48: 4680 mov r8, r0 8014c4a: f7f3 fc47 bl 80084dc <__aeabi_i2d> 8014c4e: e9dd 2304 ldrd r2, r3, [sp, #16] 8014c52: f7f3 fcad bl 80085b0 <__aeabi_dmul> 8014c56: 4602 mov r2, r0 8014c58: 460b mov r3, r1 8014c5a: 4620 mov r0, r4 8014c5c: 4629 mov r1, r5 8014c5e: f7f3 faef bl 8008240 <__aeabi_dsub> 8014c62: f108 0430 add.w r4, r8, #48 @ 0x30 8014c66: 9d08 ldr r5, [sp, #32] 8014c68: f806 4b01 strb.w r4, [r6], #1 8014c6c: eba6 040a sub.w r4, r6, sl 8014c70: 42a5 cmp r5, r4 8014c72: 4602 mov r2, r0 8014c74: 460b mov r3, r1 8014c76: d133 bne.n 8014ce0 <_dtoa_r+0x6e8> 8014c78: f7f3 fae4 bl 8008244 <__adddf3> 8014c7c: e9dd 2304 ldrd r2, r3, [sp, #16] 8014c80: 4604 mov r4, r0 8014c82: 460d mov r5, r1 8014c84: f7f3 ff24 bl 8008ad0 <__aeabi_dcmpgt> 8014c88: b9c0 cbnz r0, 8014cbc <_dtoa_r+0x6c4> 8014c8a: e9dd 2304 ldrd r2, r3, [sp, #16] 8014c8e: 4620 mov r0, r4 8014c90: 4629 mov r1, r5 8014c92: f7f3 fef5 bl 8008a80 <__aeabi_dcmpeq> 8014c96: b110 cbz r0, 8014c9e <_dtoa_r+0x6a6> 8014c98: f018 0f01 tst.w r8, #1 8014c9c: d10e bne.n 8014cbc <_dtoa_r+0x6c4> 8014c9e: 4648 mov r0, r9 8014ca0: 9903 ldr r1, [sp, #12] 8014ca2: f000 feb3 bl 8015a0c <_Bfree> 8014ca6: 2300 movs r3, #0 8014ca8: 7033 strb r3, [r6, #0] 8014caa: 9b22 ldr r3, [sp, #136] @ 0x88 8014cac: 3701 adds r7, #1 8014cae: 601f str r7, [r3, #0] 8014cb0: 9b24 ldr r3, [sp, #144] @ 0x90 8014cb2: 2b00 cmp r3, #0 8014cb4: f000 824b beq.w 801514e <_dtoa_r+0xb56> 8014cb8: 601e str r6, [r3, #0] 8014cba: e248 b.n 801514e <_dtoa_r+0xb56> 8014cbc: 46b8 mov r8, r7 8014cbe: 4633 mov r3, r6 8014cc0: 461e mov r6, r3 8014cc2: f813 2d01 ldrb.w r2, [r3, #-1]! 8014cc6: 2a39 cmp r2, #57 @ 0x39 8014cc8: d106 bne.n 8014cd8 <_dtoa_r+0x6e0> 8014cca: 459a cmp sl, r3 8014ccc: d1f8 bne.n 8014cc0 <_dtoa_r+0x6c8> 8014cce: 2230 movs r2, #48 @ 0x30 8014cd0: f108 0801 add.w r8, r8, #1 8014cd4: f88a 2000 strb.w r2, [sl] 8014cd8: 781a ldrb r2, [r3, #0] 8014cda: 3201 adds r2, #1 8014cdc: 701a strb r2, [r3, #0] 8014cde: e7a0 b.n 8014c22 <_dtoa_r+0x62a> 8014ce0: 2200 movs r2, #0 8014ce2: 4b6f ldr r3, [pc, #444] @ (8014ea0 <_dtoa_r+0x8a8>) 8014ce4: f7f3 fc64 bl 80085b0 <__aeabi_dmul> 8014ce8: 2200 movs r2, #0 8014cea: 2300 movs r3, #0 8014cec: 4604 mov r4, r0 8014cee: 460d mov r5, r1 8014cf0: f7f3 fec6 bl 8008a80 <__aeabi_dcmpeq> 8014cf4: 2800 cmp r0, #0 8014cf6: d09f beq.n 8014c38 <_dtoa_r+0x640> 8014cf8: e7d1 b.n 8014c9e <_dtoa_r+0x6a6> 8014cfa: 9a0b ldr r2, [sp, #44] @ 0x2c 8014cfc: 2a00 cmp r2, #0 8014cfe: f000 80ea beq.w 8014ed6 <_dtoa_r+0x8de> 8014d02: 9a20 ldr r2, [sp, #128] @ 0x80 8014d04: 2a01 cmp r2, #1 8014d06: f300 80cd bgt.w 8014ea4 <_dtoa_r+0x8ac> 8014d0a: 9a12 ldr r2, [sp, #72] @ 0x48 8014d0c: 2a00 cmp r2, #0 8014d0e: f000 80c1 beq.w 8014e94 <_dtoa_r+0x89c> 8014d12: f203 4333 addw r3, r3, #1075 @ 0x433 8014d16: 9c0a ldr r4, [sp, #40] @ 0x28 8014d18: 9e04 ldr r6, [sp, #16] 8014d1a: 9a04 ldr r2, [sp, #16] 8014d1c: 2101 movs r1, #1 8014d1e: 441a add r2, r3 8014d20: 9204 str r2, [sp, #16] 8014d22: 9a09 ldr r2, [sp, #36] @ 0x24 8014d24: 4648 mov r0, r9 8014d26: 441a add r2, r3 8014d28: 9209 str r2, [sp, #36] @ 0x24 8014d2a: f000 ff23 bl 8015b74 <__i2b> 8014d2e: 4605 mov r5, r0 8014d30: b166 cbz r6, 8014d4c <_dtoa_r+0x754> 8014d32: 9b09 ldr r3, [sp, #36] @ 0x24 8014d34: 2b00 cmp r3, #0 8014d36: dd09 ble.n 8014d4c <_dtoa_r+0x754> 8014d38: 42b3 cmp r3, r6 8014d3a: bfa8 it ge 8014d3c: 4633 movge r3, r6 8014d3e: 9a04 ldr r2, [sp, #16] 8014d40: 1af6 subs r6, r6, r3 8014d42: 1ad2 subs r2, r2, r3 8014d44: 9204 str r2, [sp, #16] 8014d46: 9a09 ldr r2, [sp, #36] @ 0x24 8014d48: 1ad3 subs r3, r2, r3 8014d4a: 9309 str r3, [sp, #36] @ 0x24 8014d4c: 9b0a ldr r3, [sp, #40] @ 0x28 8014d4e: b30b cbz r3, 8014d94 <_dtoa_r+0x79c> 8014d50: 9b0b ldr r3, [sp, #44] @ 0x2c 8014d52: 2b00 cmp r3, #0 8014d54: f000 80c6 beq.w 8014ee4 <_dtoa_r+0x8ec> 8014d58: 2c00 cmp r4, #0 8014d5a: f000 80c0 beq.w 8014ede <_dtoa_r+0x8e6> 8014d5e: 4629 mov r1, r5 8014d60: 4622 mov r2, r4 8014d62: 4648 mov r0, r9 8014d64: f000 ffbe bl 8015ce4 <__pow5mult> 8014d68: 9a03 ldr r2, [sp, #12] 8014d6a: 4601 mov r1, r0 8014d6c: 4605 mov r5, r0 8014d6e: 4648 mov r0, r9 8014d70: f000 ff16 bl 8015ba0 <__multiply> 8014d74: 9903 ldr r1, [sp, #12] 8014d76: 4680 mov r8, r0 8014d78: 4648 mov r0, r9 8014d7a: f000 fe47 bl 8015a0c <_Bfree> 8014d7e: 9b0a ldr r3, [sp, #40] @ 0x28 8014d80: 1b1b subs r3, r3, r4 8014d82: 930a str r3, [sp, #40] @ 0x28 8014d84: f000 80b1 beq.w 8014eea <_dtoa_r+0x8f2> 8014d88: 4641 mov r1, r8 8014d8a: 9a0a ldr r2, [sp, #40] @ 0x28 8014d8c: 4648 mov r0, r9 8014d8e: f000 ffa9 bl 8015ce4 <__pow5mult> 8014d92: 9003 str r0, [sp, #12] 8014d94: 2101 movs r1, #1 8014d96: 4648 mov r0, r9 8014d98: f000 feec bl 8015b74 <__i2b> 8014d9c: 9b0e ldr r3, [sp, #56] @ 0x38 8014d9e: 4604 mov r4, r0 8014da0: 2b00 cmp r3, #0 8014da2: f000 81d8 beq.w 8015156 <_dtoa_r+0xb5e> 8014da6: 461a mov r2, r3 8014da8: 4601 mov r1, r0 8014daa: 4648 mov r0, r9 8014dac: f000 ff9a bl 8015ce4 <__pow5mult> 8014db0: 9b20 ldr r3, [sp, #128] @ 0x80 8014db2: 4604 mov r4, r0 8014db4: 2b01 cmp r3, #1 8014db6: f300 809f bgt.w 8014ef8 <_dtoa_r+0x900> 8014dba: 9b06 ldr r3, [sp, #24] 8014dbc: 2b00 cmp r3, #0 8014dbe: f040 8097 bne.w 8014ef0 <_dtoa_r+0x8f8> 8014dc2: 9b07 ldr r3, [sp, #28] 8014dc4: f3c3 0313 ubfx r3, r3, #0, #20 8014dc8: 2b00 cmp r3, #0 8014dca: f040 8093 bne.w 8014ef4 <_dtoa_r+0x8fc> 8014dce: 9b07 ldr r3, [sp, #28] 8014dd0: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8014dd4: 0d1b lsrs r3, r3, #20 8014dd6: 051b lsls r3, r3, #20 8014dd8: b133 cbz r3, 8014de8 <_dtoa_r+0x7f0> 8014dda: 9b04 ldr r3, [sp, #16] 8014ddc: 3301 adds r3, #1 8014dde: 9304 str r3, [sp, #16] 8014de0: 9b09 ldr r3, [sp, #36] @ 0x24 8014de2: 3301 adds r3, #1 8014de4: 9309 str r3, [sp, #36] @ 0x24 8014de6: 2301 movs r3, #1 8014de8: 930a str r3, [sp, #40] @ 0x28 8014dea: 9b0e ldr r3, [sp, #56] @ 0x38 8014dec: 2b00 cmp r3, #0 8014dee: f000 81b8 beq.w 8015162 <_dtoa_r+0xb6a> 8014df2: 6923 ldr r3, [r4, #16] 8014df4: eb04 0383 add.w r3, r4, r3, lsl #2 8014df8: 6918 ldr r0, [r3, #16] 8014dfa: f000 fe6f bl 8015adc <__hi0bits> 8014dfe: f1c0 0020 rsb r0, r0, #32 8014e02: 9b09 ldr r3, [sp, #36] @ 0x24 8014e04: 4418 add r0, r3 8014e06: f010 001f ands.w r0, r0, #31 8014e0a: f000 8082 beq.w 8014f12 <_dtoa_r+0x91a> 8014e0e: f1c0 0320 rsb r3, r0, #32 8014e12: 2b04 cmp r3, #4 8014e14: dd73 ble.n 8014efe <_dtoa_r+0x906> 8014e16: 9b04 ldr r3, [sp, #16] 8014e18: f1c0 001c rsb r0, r0, #28 8014e1c: 4403 add r3, r0 8014e1e: 9304 str r3, [sp, #16] 8014e20: 9b09 ldr r3, [sp, #36] @ 0x24 8014e22: 4406 add r6, r0 8014e24: 4403 add r3, r0 8014e26: 9309 str r3, [sp, #36] @ 0x24 8014e28: 9b04 ldr r3, [sp, #16] 8014e2a: 2b00 cmp r3, #0 8014e2c: dd05 ble.n 8014e3a <_dtoa_r+0x842> 8014e2e: 461a mov r2, r3 8014e30: 4648 mov r0, r9 8014e32: 9903 ldr r1, [sp, #12] 8014e34: f000 ffb0 bl 8015d98 <__lshift> 8014e38: 9003 str r0, [sp, #12] 8014e3a: 9b09 ldr r3, [sp, #36] @ 0x24 8014e3c: 2b00 cmp r3, #0 8014e3e: dd05 ble.n 8014e4c <_dtoa_r+0x854> 8014e40: 4621 mov r1, r4 8014e42: 461a mov r2, r3 8014e44: 4648 mov r0, r9 8014e46: f000 ffa7 bl 8015d98 <__lshift> 8014e4a: 4604 mov r4, r0 8014e4c: 9b0f ldr r3, [sp, #60] @ 0x3c 8014e4e: 2b00 cmp r3, #0 8014e50: d061 beq.n 8014f16 <_dtoa_r+0x91e> 8014e52: 4621 mov r1, r4 8014e54: 9803 ldr r0, [sp, #12] 8014e56: f001 f80b bl 8015e70 <__mcmp> 8014e5a: 2800 cmp r0, #0 8014e5c: da5b bge.n 8014f16 <_dtoa_r+0x91e> 8014e5e: 2300 movs r3, #0 8014e60: 220a movs r2, #10 8014e62: 4648 mov r0, r9 8014e64: 9903 ldr r1, [sp, #12] 8014e66: f000 fdf3 bl 8015a50 <__multadd> 8014e6a: 9b0b ldr r3, [sp, #44] @ 0x2c 8014e6c: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 8014e70: 9003 str r0, [sp, #12] 8014e72: 2b00 cmp r3, #0 8014e74: f000 8177 beq.w 8015166 <_dtoa_r+0xb6e> 8014e78: 4629 mov r1, r5 8014e7a: 2300 movs r3, #0 8014e7c: 220a movs r2, #10 8014e7e: 4648 mov r0, r9 8014e80: f000 fde6 bl 8015a50 <__multadd> 8014e84: f1bb 0f00 cmp.w fp, #0 8014e88: 4605 mov r5, r0 8014e8a: dc6f bgt.n 8014f6c <_dtoa_r+0x974> 8014e8c: 9b20 ldr r3, [sp, #128] @ 0x80 8014e8e: 2b02 cmp r3, #2 8014e90: dc49 bgt.n 8014f26 <_dtoa_r+0x92e> 8014e92: e06b b.n 8014f6c <_dtoa_r+0x974> 8014e94: 9b14 ldr r3, [sp, #80] @ 0x50 8014e96: f1c3 0336 rsb r3, r3, #54 @ 0x36 8014e9a: e73c b.n 8014d16 <_dtoa_r+0x71e> 8014e9c: 3fe00000 .word 0x3fe00000 8014ea0: 40240000 .word 0x40240000 8014ea4: 9b08 ldr r3, [sp, #32] 8014ea6: 1e5c subs r4, r3, #1 8014ea8: 9b0a ldr r3, [sp, #40] @ 0x28 8014eaa: 42a3 cmp r3, r4 8014eac: db09 blt.n 8014ec2 <_dtoa_r+0x8ca> 8014eae: 1b1c subs r4, r3, r4 8014eb0: 9b08 ldr r3, [sp, #32] 8014eb2: 2b00 cmp r3, #0 8014eb4: f6bf af30 bge.w 8014d18 <_dtoa_r+0x720> 8014eb8: 9b04 ldr r3, [sp, #16] 8014eba: 9a08 ldr r2, [sp, #32] 8014ebc: 1a9e subs r6, r3, r2 8014ebe: 2300 movs r3, #0 8014ec0: e72b b.n 8014d1a <_dtoa_r+0x722> 8014ec2: 9b0a ldr r3, [sp, #40] @ 0x28 8014ec4: 9a0e ldr r2, [sp, #56] @ 0x38 8014ec6: 1ae3 subs r3, r4, r3 8014ec8: 441a add r2, r3 8014eca: 940a str r4, [sp, #40] @ 0x28 8014ecc: 9e04 ldr r6, [sp, #16] 8014ece: 2400 movs r4, #0 8014ed0: 9b08 ldr r3, [sp, #32] 8014ed2: 920e str r2, [sp, #56] @ 0x38 8014ed4: e721 b.n 8014d1a <_dtoa_r+0x722> 8014ed6: 9c0a ldr r4, [sp, #40] @ 0x28 8014ed8: 9e04 ldr r6, [sp, #16] 8014eda: 9d0b ldr r5, [sp, #44] @ 0x2c 8014edc: e728 b.n 8014d30 <_dtoa_r+0x738> 8014ede: f8dd 800c ldr.w r8, [sp, #12] 8014ee2: e751 b.n 8014d88 <_dtoa_r+0x790> 8014ee4: 9a0a ldr r2, [sp, #40] @ 0x28 8014ee6: 9903 ldr r1, [sp, #12] 8014ee8: e750 b.n 8014d8c <_dtoa_r+0x794> 8014eea: f8cd 800c str.w r8, [sp, #12] 8014eee: e751 b.n 8014d94 <_dtoa_r+0x79c> 8014ef0: 2300 movs r3, #0 8014ef2: e779 b.n 8014de8 <_dtoa_r+0x7f0> 8014ef4: 9b06 ldr r3, [sp, #24] 8014ef6: e777 b.n 8014de8 <_dtoa_r+0x7f0> 8014ef8: 2300 movs r3, #0 8014efa: 930a str r3, [sp, #40] @ 0x28 8014efc: e779 b.n 8014df2 <_dtoa_r+0x7fa> 8014efe: d093 beq.n 8014e28 <_dtoa_r+0x830> 8014f00: 9a04 ldr r2, [sp, #16] 8014f02: 331c adds r3, #28 8014f04: 441a add r2, r3 8014f06: 9204 str r2, [sp, #16] 8014f08: 9a09 ldr r2, [sp, #36] @ 0x24 8014f0a: 441e add r6, r3 8014f0c: 441a add r2, r3 8014f0e: 9209 str r2, [sp, #36] @ 0x24 8014f10: e78a b.n 8014e28 <_dtoa_r+0x830> 8014f12: 4603 mov r3, r0 8014f14: e7f4 b.n 8014f00 <_dtoa_r+0x908> 8014f16: 9b08 ldr r3, [sp, #32] 8014f18: 46b8 mov r8, r7 8014f1a: 2b00 cmp r3, #0 8014f1c: dc20 bgt.n 8014f60 <_dtoa_r+0x968> 8014f1e: 469b mov fp, r3 8014f20: 9b20 ldr r3, [sp, #128] @ 0x80 8014f22: 2b02 cmp r3, #2 8014f24: dd1e ble.n 8014f64 <_dtoa_r+0x96c> 8014f26: f1bb 0f00 cmp.w fp, #0 8014f2a: f47f adb1 bne.w 8014a90 <_dtoa_r+0x498> 8014f2e: 4621 mov r1, r4 8014f30: 465b mov r3, fp 8014f32: 2205 movs r2, #5 8014f34: 4648 mov r0, r9 8014f36: f000 fd8b bl 8015a50 <__multadd> 8014f3a: 4601 mov r1, r0 8014f3c: 4604 mov r4, r0 8014f3e: 9803 ldr r0, [sp, #12] 8014f40: f000 ff96 bl 8015e70 <__mcmp> 8014f44: 2800 cmp r0, #0 8014f46: f77f ada3 ble.w 8014a90 <_dtoa_r+0x498> 8014f4a: 4656 mov r6, sl 8014f4c: 2331 movs r3, #49 @ 0x31 8014f4e: f108 0801 add.w r8, r8, #1 8014f52: f806 3b01 strb.w r3, [r6], #1 8014f56: e59f b.n 8014a98 <_dtoa_r+0x4a0> 8014f58: 46b8 mov r8, r7 8014f5a: 9c08 ldr r4, [sp, #32] 8014f5c: 4625 mov r5, r4 8014f5e: e7f4 b.n 8014f4a <_dtoa_r+0x952> 8014f60: f8dd b020 ldr.w fp, [sp, #32] 8014f64: 9b0b ldr r3, [sp, #44] @ 0x2c 8014f66: 2b00 cmp r3, #0 8014f68: f000 8101 beq.w 801516e <_dtoa_r+0xb76> 8014f6c: 2e00 cmp r6, #0 8014f6e: dd05 ble.n 8014f7c <_dtoa_r+0x984> 8014f70: 4629 mov r1, r5 8014f72: 4632 mov r2, r6 8014f74: 4648 mov r0, r9 8014f76: f000 ff0f bl 8015d98 <__lshift> 8014f7a: 4605 mov r5, r0 8014f7c: 9b0a ldr r3, [sp, #40] @ 0x28 8014f7e: 2b00 cmp r3, #0 8014f80: d05c beq.n 801503c <_dtoa_r+0xa44> 8014f82: 4648 mov r0, r9 8014f84: 6869 ldr r1, [r5, #4] 8014f86: f000 fd01 bl 801598c <_Balloc> 8014f8a: 4606 mov r6, r0 8014f8c: b928 cbnz r0, 8014f9a <_dtoa_r+0x9a2> 8014f8e: 4602 mov r2, r0 8014f90: f240 21ef movw r1, #751 @ 0x2ef 8014f94: 4b80 ldr r3, [pc, #512] @ (8015198 <_dtoa_r+0xba0>) 8014f96: f7ff bb43 b.w 8014620 <_dtoa_r+0x28> 8014f9a: 692a ldr r2, [r5, #16] 8014f9c: f105 010c add.w r1, r5, #12 8014fa0: 3202 adds r2, #2 8014fa2: 0092 lsls r2, r2, #2 8014fa4: 300c adds r0, #12 8014fa6: f7ff fa73 bl 8014490 8014faa: 2201 movs r2, #1 8014fac: 4631 mov r1, r6 8014fae: 4648 mov r0, r9 8014fb0: f000 fef2 bl 8015d98 <__lshift> 8014fb4: 462f mov r7, r5 8014fb6: 4605 mov r5, r0 8014fb8: f10a 0301 add.w r3, sl, #1 8014fbc: 9304 str r3, [sp, #16] 8014fbe: eb0a 030b add.w r3, sl, fp 8014fc2: 930a str r3, [sp, #40] @ 0x28 8014fc4: 9b06 ldr r3, [sp, #24] 8014fc6: f003 0301 and.w r3, r3, #1 8014fca: 9309 str r3, [sp, #36] @ 0x24 8014fcc: 9b04 ldr r3, [sp, #16] 8014fce: 4621 mov r1, r4 8014fd0: 9803 ldr r0, [sp, #12] 8014fd2: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff 8014fd6: f7ff fa87 bl 80144e8 8014fda: 4603 mov r3, r0 8014fdc: 4639 mov r1, r7 8014fde: 3330 adds r3, #48 @ 0x30 8014fe0: 9006 str r0, [sp, #24] 8014fe2: 9803 ldr r0, [sp, #12] 8014fe4: 930b str r3, [sp, #44] @ 0x2c 8014fe6: f000 ff43 bl 8015e70 <__mcmp> 8014fea: 462a mov r2, r5 8014fec: 9008 str r0, [sp, #32] 8014fee: 4621 mov r1, r4 8014ff0: 4648 mov r0, r9 8014ff2: f000 ff59 bl 8015ea8 <__mdiff> 8014ff6: 68c2 ldr r2, [r0, #12] 8014ff8: 4606 mov r6, r0 8014ffa: 9b0b ldr r3, [sp, #44] @ 0x2c 8014ffc: bb02 cbnz r2, 8015040 <_dtoa_r+0xa48> 8014ffe: 4601 mov r1, r0 8015000: 9803 ldr r0, [sp, #12] 8015002: f000 ff35 bl 8015e70 <__mcmp> 8015006: 4602 mov r2, r0 8015008: 9b0b ldr r3, [sp, #44] @ 0x2c 801500a: 4631 mov r1, r6 801500c: 4648 mov r0, r9 801500e: e9cd 320b strd r3, r2, [sp, #44] @ 0x2c 8015012: f000 fcfb bl 8015a0c <_Bfree> 8015016: 9b20 ldr r3, [sp, #128] @ 0x80 8015018: 9a0c ldr r2, [sp, #48] @ 0x30 801501a: 9e04 ldr r6, [sp, #16] 801501c: ea42 0103 orr.w r1, r2, r3 8015020: 9b09 ldr r3, [sp, #36] @ 0x24 8015022: 4319 orrs r1, r3 8015024: 9b0b ldr r3, [sp, #44] @ 0x2c 8015026: d10d bne.n 8015044 <_dtoa_r+0xa4c> 8015028: 2b39 cmp r3, #57 @ 0x39 801502a: d027 beq.n 801507c <_dtoa_r+0xa84> 801502c: 9a08 ldr r2, [sp, #32] 801502e: 2a00 cmp r2, #0 8015030: dd01 ble.n 8015036 <_dtoa_r+0xa3e> 8015032: 9b06 ldr r3, [sp, #24] 8015034: 3331 adds r3, #49 @ 0x31 8015036: f88b 3000 strb.w r3, [fp] 801503a: e52e b.n 8014a9a <_dtoa_r+0x4a2> 801503c: 4628 mov r0, r5 801503e: e7b9 b.n 8014fb4 <_dtoa_r+0x9bc> 8015040: 2201 movs r2, #1 8015042: e7e2 b.n 801500a <_dtoa_r+0xa12> 8015044: 9908 ldr r1, [sp, #32] 8015046: 2900 cmp r1, #0 8015048: db04 blt.n 8015054 <_dtoa_r+0xa5c> 801504a: 9820 ldr r0, [sp, #128] @ 0x80 801504c: 4301 orrs r1, r0 801504e: 9809 ldr r0, [sp, #36] @ 0x24 8015050: 4301 orrs r1, r0 8015052: d120 bne.n 8015096 <_dtoa_r+0xa9e> 8015054: 2a00 cmp r2, #0 8015056: ddee ble.n 8015036 <_dtoa_r+0xa3e> 8015058: 2201 movs r2, #1 801505a: 9903 ldr r1, [sp, #12] 801505c: 4648 mov r0, r9 801505e: 9304 str r3, [sp, #16] 8015060: f000 fe9a bl 8015d98 <__lshift> 8015064: 4621 mov r1, r4 8015066: 9003 str r0, [sp, #12] 8015068: f000 ff02 bl 8015e70 <__mcmp> 801506c: 2800 cmp r0, #0 801506e: 9b04 ldr r3, [sp, #16] 8015070: dc02 bgt.n 8015078 <_dtoa_r+0xa80> 8015072: d1e0 bne.n 8015036 <_dtoa_r+0xa3e> 8015074: 07da lsls r2, r3, #31 8015076: d5de bpl.n 8015036 <_dtoa_r+0xa3e> 8015078: 2b39 cmp r3, #57 @ 0x39 801507a: d1da bne.n 8015032 <_dtoa_r+0xa3a> 801507c: 2339 movs r3, #57 @ 0x39 801507e: f88b 3000 strb.w r3, [fp] 8015082: 4633 mov r3, r6 8015084: 461e mov r6, r3 8015086: f816 2c01 ldrb.w r2, [r6, #-1] 801508a: 3b01 subs r3, #1 801508c: 2a39 cmp r2, #57 @ 0x39 801508e: d04e beq.n 801512e <_dtoa_r+0xb36> 8015090: 3201 adds r2, #1 8015092: 701a strb r2, [r3, #0] 8015094: e501 b.n 8014a9a <_dtoa_r+0x4a2> 8015096: 2a00 cmp r2, #0 8015098: dd03 ble.n 80150a2 <_dtoa_r+0xaaa> 801509a: 2b39 cmp r3, #57 @ 0x39 801509c: d0ee beq.n 801507c <_dtoa_r+0xa84> 801509e: 3301 adds r3, #1 80150a0: e7c9 b.n 8015036 <_dtoa_r+0xa3e> 80150a2: 9a04 ldr r2, [sp, #16] 80150a4: 990a ldr r1, [sp, #40] @ 0x28 80150a6: f802 3c01 strb.w r3, [r2, #-1] 80150aa: 428a cmp r2, r1 80150ac: d028 beq.n 8015100 <_dtoa_r+0xb08> 80150ae: 2300 movs r3, #0 80150b0: 220a movs r2, #10 80150b2: 9903 ldr r1, [sp, #12] 80150b4: 4648 mov r0, r9 80150b6: f000 fccb bl 8015a50 <__multadd> 80150ba: 42af cmp r7, r5 80150bc: 9003 str r0, [sp, #12] 80150be: f04f 0300 mov.w r3, #0 80150c2: f04f 020a mov.w r2, #10 80150c6: 4639 mov r1, r7 80150c8: 4648 mov r0, r9 80150ca: d107 bne.n 80150dc <_dtoa_r+0xae4> 80150cc: f000 fcc0 bl 8015a50 <__multadd> 80150d0: 4607 mov r7, r0 80150d2: 4605 mov r5, r0 80150d4: 9b04 ldr r3, [sp, #16] 80150d6: 3301 adds r3, #1 80150d8: 9304 str r3, [sp, #16] 80150da: e777 b.n 8014fcc <_dtoa_r+0x9d4> 80150dc: f000 fcb8 bl 8015a50 <__multadd> 80150e0: 4629 mov r1, r5 80150e2: 4607 mov r7, r0 80150e4: 2300 movs r3, #0 80150e6: 220a movs r2, #10 80150e8: 4648 mov r0, r9 80150ea: f000 fcb1 bl 8015a50 <__multadd> 80150ee: 4605 mov r5, r0 80150f0: e7f0 b.n 80150d4 <_dtoa_r+0xadc> 80150f2: f1bb 0f00 cmp.w fp, #0 80150f6: bfcc ite gt 80150f8: 465e movgt r6, fp 80150fa: 2601 movle r6, #1 80150fc: 2700 movs r7, #0 80150fe: 4456 add r6, sl 8015100: 2201 movs r2, #1 8015102: 9903 ldr r1, [sp, #12] 8015104: 4648 mov r0, r9 8015106: 9304 str r3, [sp, #16] 8015108: f000 fe46 bl 8015d98 <__lshift> 801510c: 4621 mov r1, r4 801510e: 9003 str r0, [sp, #12] 8015110: f000 feae bl 8015e70 <__mcmp> 8015114: 2800 cmp r0, #0 8015116: dcb4 bgt.n 8015082 <_dtoa_r+0xa8a> 8015118: d102 bne.n 8015120 <_dtoa_r+0xb28> 801511a: 9b04 ldr r3, [sp, #16] 801511c: 07db lsls r3, r3, #31 801511e: d4b0 bmi.n 8015082 <_dtoa_r+0xa8a> 8015120: 4633 mov r3, r6 8015122: 461e mov r6, r3 8015124: f813 2d01 ldrb.w r2, [r3, #-1]! 8015128: 2a30 cmp r2, #48 @ 0x30 801512a: d0fa beq.n 8015122 <_dtoa_r+0xb2a> 801512c: e4b5 b.n 8014a9a <_dtoa_r+0x4a2> 801512e: 459a cmp sl, r3 8015130: d1a8 bne.n 8015084 <_dtoa_r+0xa8c> 8015132: 2331 movs r3, #49 @ 0x31 8015134: f108 0801 add.w r8, r8, #1 8015138: f88a 3000 strb.w r3, [sl] 801513c: e4ad b.n 8014a9a <_dtoa_r+0x4a2> 801513e: 9b24 ldr r3, [sp, #144] @ 0x90 8015140: f8df a058 ldr.w sl, [pc, #88] @ 801519c <_dtoa_r+0xba4> 8015144: b11b cbz r3, 801514e <_dtoa_r+0xb56> 8015146: f10a 0308 add.w r3, sl, #8 801514a: 9a24 ldr r2, [sp, #144] @ 0x90 801514c: 6013 str r3, [r2, #0] 801514e: 4650 mov r0, sl 8015150: b017 add sp, #92 @ 0x5c 8015152: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8015156: 9b20 ldr r3, [sp, #128] @ 0x80 8015158: 2b01 cmp r3, #1 801515a: f77f ae2e ble.w 8014dba <_dtoa_r+0x7c2> 801515e: 9b0e ldr r3, [sp, #56] @ 0x38 8015160: 930a str r3, [sp, #40] @ 0x28 8015162: 2001 movs r0, #1 8015164: e64d b.n 8014e02 <_dtoa_r+0x80a> 8015166: f1bb 0f00 cmp.w fp, #0 801516a: f77f aed9 ble.w 8014f20 <_dtoa_r+0x928> 801516e: 4656 mov r6, sl 8015170: 4621 mov r1, r4 8015172: 9803 ldr r0, [sp, #12] 8015174: f7ff f9b8 bl 80144e8 8015178: f100 0330 add.w r3, r0, #48 @ 0x30 801517c: f806 3b01 strb.w r3, [r6], #1 8015180: eba6 020a sub.w r2, r6, sl 8015184: 4593 cmp fp, r2 8015186: ddb4 ble.n 80150f2 <_dtoa_r+0xafa> 8015188: 2300 movs r3, #0 801518a: 220a movs r2, #10 801518c: 4648 mov r0, r9 801518e: 9903 ldr r1, [sp, #12] 8015190: f000 fc5e bl 8015a50 <__multadd> 8015194: 9003 str r0, [sp, #12] 8015196: e7eb b.n 8015170 <_dtoa_r+0xb78> 8015198: 08016fc8 .word 0x08016fc8 801519c: 08016f4c .word 0x08016f4c 080151a0 <__ssputs_r>: 80151a0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80151a4: 461f mov r7, r3 80151a6: 688e ldr r6, [r1, #8] 80151a8: 4682 mov sl, r0 80151aa: 42be cmp r6, r7 80151ac: 460c mov r4, r1 80151ae: 4690 mov r8, r2 80151b0: 680b ldr r3, [r1, #0] 80151b2: d82d bhi.n 8015210 <__ssputs_r+0x70> 80151b4: f9b1 200c ldrsh.w r2, [r1, #12] 80151b8: f412 6f90 tst.w r2, #1152 @ 0x480 80151bc: d026 beq.n 801520c <__ssputs_r+0x6c> 80151be: 6965 ldr r5, [r4, #20] 80151c0: 6909 ldr r1, [r1, #16] 80151c2: eb05 0545 add.w r5, r5, r5, lsl #1 80151c6: eba3 0901 sub.w r9, r3, r1 80151ca: eb05 75d5 add.w r5, r5, r5, lsr #31 80151ce: 1c7b adds r3, r7, #1 80151d0: 444b add r3, r9 80151d2: 106d asrs r5, r5, #1 80151d4: 429d cmp r5, r3 80151d6: bf38 it cc 80151d8: 461d movcc r5, r3 80151da: 0553 lsls r3, r2, #21 80151dc: d527 bpl.n 801522e <__ssputs_r+0x8e> 80151de: 4629 mov r1, r5 80151e0: f000 faa0 bl 8015724 <_malloc_r> 80151e4: 4606 mov r6, r0 80151e6: b360 cbz r0, 8015242 <__ssputs_r+0xa2> 80151e8: 464a mov r2, r9 80151ea: 6921 ldr r1, [r4, #16] 80151ec: f7ff f950 bl 8014490 80151f0: 89a3 ldrh r3, [r4, #12] 80151f2: f423 6390 bic.w r3, r3, #1152 @ 0x480 80151f6: f043 0380 orr.w r3, r3, #128 @ 0x80 80151fa: 81a3 strh r3, [r4, #12] 80151fc: 6126 str r6, [r4, #16] 80151fe: 444e add r6, r9 8015200: 6026 str r6, [r4, #0] 8015202: 463e mov r6, r7 8015204: 6165 str r5, [r4, #20] 8015206: eba5 0509 sub.w r5, r5, r9 801520a: 60a5 str r5, [r4, #8] 801520c: 42be cmp r6, r7 801520e: d900 bls.n 8015212 <__ssputs_r+0x72> 8015210: 463e mov r6, r7 8015212: 4632 mov r2, r6 8015214: 4641 mov r1, r8 8015216: 6820 ldr r0, [r4, #0] 8015218: f001 f8ab bl 8016372 801521c: 2000 movs r0, #0 801521e: 68a3 ldr r3, [r4, #8] 8015220: 1b9b subs r3, r3, r6 8015222: 60a3 str r3, [r4, #8] 8015224: 6823 ldr r3, [r4, #0] 8015226: 4433 add r3, r6 8015228: 6023 str r3, [r4, #0] 801522a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801522e: 462a mov r2, r5 8015230: f000 ff7c bl 801612c <_realloc_r> 8015234: 4606 mov r6, r0 8015236: 2800 cmp r0, #0 8015238: d1e0 bne.n 80151fc <__ssputs_r+0x5c> 801523a: 4650 mov r0, sl 801523c: 6921 ldr r1, [r4, #16] 801523e: f001 f947 bl 80164d0 <_free_r> 8015242: 230c movs r3, #12 8015244: f8ca 3000 str.w r3, [sl] 8015248: 89a3 ldrh r3, [r4, #12] 801524a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801524e: f043 0340 orr.w r3, r3, #64 @ 0x40 8015252: 81a3 strh r3, [r4, #12] 8015254: e7e9 b.n 801522a <__ssputs_r+0x8a> ... 08015258 <_svfiprintf_r>: 8015258: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801525c: 4698 mov r8, r3 801525e: 898b ldrh r3, [r1, #12] 8015260: 4607 mov r7, r0 8015262: 061b lsls r3, r3, #24 8015264: 460d mov r5, r1 8015266: 4614 mov r4, r2 8015268: b09d sub sp, #116 @ 0x74 801526a: d510 bpl.n 801528e <_svfiprintf_r+0x36> 801526c: 690b ldr r3, [r1, #16] 801526e: b973 cbnz r3, 801528e <_svfiprintf_r+0x36> 8015270: 2140 movs r1, #64 @ 0x40 8015272: f000 fa57 bl 8015724 <_malloc_r> 8015276: 6028 str r0, [r5, #0] 8015278: 6128 str r0, [r5, #16] 801527a: b930 cbnz r0, 801528a <_svfiprintf_r+0x32> 801527c: 230c movs r3, #12 801527e: 603b str r3, [r7, #0] 8015280: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015284: b01d add sp, #116 @ 0x74 8015286: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801528a: 2340 movs r3, #64 @ 0x40 801528c: 616b str r3, [r5, #20] 801528e: 2300 movs r3, #0 8015290: 9309 str r3, [sp, #36] @ 0x24 8015292: 2320 movs r3, #32 8015294: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8015298: 2330 movs r3, #48 @ 0x30 801529a: f04f 0901 mov.w r9, #1 801529e: f8cd 800c str.w r8, [sp, #12] 80152a2: f8df 8198 ldr.w r8, [pc, #408] @ 801543c <_svfiprintf_r+0x1e4> 80152a6: f88d 302a strb.w r3, [sp, #42] @ 0x2a 80152aa: 4623 mov r3, r4 80152ac: 469a mov sl, r3 80152ae: f813 2b01 ldrb.w r2, [r3], #1 80152b2: b10a cbz r2, 80152b8 <_svfiprintf_r+0x60> 80152b4: 2a25 cmp r2, #37 @ 0x25 80152b6: d1f9 bne.n 80152ac <_svfiprintf_r+0x54> 80152b8: ebba 0b04 subs.w fp, sl, r4 80152bc: d00b beq.n 80152d6 <_svfiprintf_r+0x7e> 80152be: 465b mov r3, fp 80152c0: 4622 mov r2, r4 80152c2: 4629 mov r1, r5 80152c4: 4638 mov r0, r7 80152c6: f7ff ff6b bl 80151a0 <__ssputs_r> 80152ca: 3001 adds r0, #1 80152cc: f000 80a7 beq.w 801541e <_svfiprintf_r+0x1c6> 80152d0: 9a09 ldr r2, [sp, #36] @ 0x24 80152d2: 445a add r2, fp 80152d4: 9209 str r2, [sp, #36] @ 0x24 80152d6: f89a 3000 ldrb.w r3, [sl] 80152da: 2b00 cmp r3, #0 80152dc: f000 809f beq.w 801541e <_svfiprintf_r+0x1c6> 80152e0: 2300 movs r3, #0 80152e2: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80152e6: e9cd 2305 strd r2, r3, [sp, #20] 80152ea: f10a 0a01 add.w sl, sl, #1 80152ee: 9304 str r3, [sp, #16] 80152f0: 9307 str r3, [sp, #28] 80152f2: f88d 3053 strb.w r3, [sp, #83] @ 0x53 80152f6: 931a str r3, [sp, #104] @ 0x68 80152f8: 4654 mov r4, sl 80152fa: 2205 movs r2, #5 80152fc: f814 1b01 ldrb.w r1, [r4], #1 8015300: 484e ldr r0, [pc, #312] @ (801543c <_svfiprintf_r+0x1e4>) 8015302: f7ff f8b7 bl 8014474 8015306: 9a04 ldr r2, [sp, #16] 8015308: b9d8 cbnz r0, 8015342 <_svfiprintf_r+0xea> 801530a: 06d0 lsls r0, r2, #27 801530c: bf44 itt mi 801530e: 2320 movmi r3, #32 8015310: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8015314: 0711 lsls r1, r2, #28 8015316: bf44 itt mi 8015318: 232b movmi r3, #43 @ 0x2b 801531a: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 801531e: f89a 3000 ldrb.w r3, [sl] 8015322: 2b2a cmp r3, #42 @ 0x2a 8015324: d015 beq.n 8015352 <_svfiprintf_r+0xfa> 8015326: 4654 mov r4, sl 8015328: 2000 movs r0, #0 801532a: f04f 0c0a mov.w ip, #10 801532e: 9a07 ldr r2, [sp, #28] 8015330: 4621 mov r1, r4 8015332: f811 3b01 ldrb.w r3, [r1], #1 8015336: 3b30 subs r3, #48 @ 0x30 8015338: 2b09 cmp r3, #9 801533a: d94b bls.n 80153d4 <_svfiprintf_r+0x17c> 801533c: b1b0 cbz r0, 801536c <_svfiprintf_r+0x114> 801533e: 9207 str r2, [sp, #28] 8015340: e014 b.n 801536c <_svfiprintf_r+0x114> 8015342: eba0 0308 sub.w r3, r0, r8 8015346: fa09 f303 lsl.w r3, r9, r3 801534a: 4313 orrs r3, r2 801534c: 46a2 mov sl, r4 801534e: 9304 str r3, [sp, #16] 8015350: e7d2 b.n 80152f8 <_svfiprintf_r+0xa0> 8015352: 9b03 ldr r3, [sp, #12] 8015354: 1d19 adds r1, r3, #4 8015356: 681b ldr r3, [r3, #0] 8015358: 9103 str r1, [sp, #12] 801535a: 2b00 cmp r3, #0 801535c: bfbb ittet lt 801535e: 425b neglt r3, r3 8015360: f042 0202 orrlt.w r2, r2, #2 8015364: 9307 strge r3, [sp, #28] 8015366: 9307 strlt r3, [sp, #28] 8015368: bfb8 it lt 801536a: 9204 strlt r2, [sp, #16] 801536c: 7823 ldrb r3, [r4, #0] 801536e: 2b2e cmp r3, #46 @ 0x2e 8015370: d10a bne.n 8015388 <_svfiprintf_r+0x130> 8015372: 7863 ldrb r3, [r4, #1] 8015374: 2b2a cmp r3, #42 @ 0x2a 8015376: d132 bne.n 80153de <_svfiprintf_r+0x186> 8015378: 9b03 ldr r3, [sp, #12] 801537a: 3402 adds r4, #2 801537c: 1d1a adds r2, r3, #4 801537e: 681b ldr r3, [r3, #0] 8015380: 9203 str r2, [sp, #12] 8015382: ea43 73e3 orr.w r3, r3, r3, asr #31 8015386: 9305 str r3, [sp, #20] 8015388: f8df a0b4 ldr.w sl, [pc, #180] @ 8015440 <_svfiprintf_r+0x1e8> 801538c: 2203 movs r2, #3 801538e: 4650 mov r0, sl 8015390: 7821 ldrb r1, [r4, #0] 8015392: f7ff f86f bl 8014474 8015396: b138 cbz r0, 80153a8 <_svfiprintf_r+0x150> 8015398: 2240 movs r2, #64 @ 0x40 801539a: 9b04 ldr r3, [sp, #16] 801539c: eba0 000a sub.w r0, r0, sl 80153a0: 4082 lsls r2, r0 80153a2: 4313 orrs r3, r2 80153a4: 3401 adds r4, #1 80153a6: 9304 str r3, [sp, #16] 80153a8: f814 1b01 ldrb.w r1, [r4], #1 80153ac: 2206 movs r2, #6 80153ae: 4825 ldr r0, [pc, #148] @ (8015444 <_svfiprintf_r+0x1ec>) 80153b0: f88d 1028 strb.w r1, [sp, #40] @ 0x28 80153b4: f7ff f85e bl 8014474 80153b8: 2800 cmp r0, #0 80153ba: d036 beq.n 801542a <_svfiprintf_r+0x1d2> 80153bc: 4b22 ldr r3, [pc, #136] @ (8015448 <_svfiprintf_r+0x1f0>) 80153be: bb1b cbnz r3, 8015408 <_svfiprintf_r+0x1b0> 80153c0: 9b03 ldr r3, [sp, #12] 80153c2: 3307 adds r3, #7 80153c4: f023 0307 bic.w r3, r3, #7 80153c8: 3308 adds r3, #8 80153ca: 9303 str r3, [sp, #12] 80153cc: 9b09 ldr r3, [sp, #36] @ 0x24 80153ce: 4433 add r3, r6 80153d0: 9309 str r3, [sp, #36] @ 0x24 80153d2: e76a b.n 80152aa <_svfiprintf_r+0x52> 80153d4: 460c mov r4, r1 80153d6: 2001 movs r0, #1 80153d8: fb0c 3202 mla r2, ip, r2, r3 80153dc: e7a8 b.n 8015330 <_svfiprintf_r+0xd8> 80153de: 2300 movs r3, #0 80153e0: f04f 0c0a mov.w ip, #10 80153e4: 4619 mov r1, r3 80153e6: 3401 adds r4, #1 80153e8: 9305 str r3, [sp, #20] 80153ea: 4620 mov r0, r4 80153ec: f810 2b01 ldrb.w r2, [r0], #1 80153f0: 3a30 subs r2, #48 @ 0x30 80153f2: 2a09 cmp r2, #9 80153f4: d903 bls.n 80153fe <_svfiprintf_r+0x1a6> 80153f6: 2b00 cmp r3, #0 80153f8: d0c6 beq.n 8015388 <_svfiprintf_r+0x130> 80153fa: 9105 str r1, [sp, #20] 80153fc: e7c4 b.n 8015388 <_svfiprintf_r+0x130> 80153fe: 4604 mov r4, r0 8015400: 2301 movs r3, #1 8015402: fb0c 2101 mla r1, ip, r1, r2 8015406: e7f0 b.n 80153ea <_svfiprintf_r+0x192> 8015408: ab03 add r3, sp, #12 801540a: 9300 str r3, [sp, #0] 801540c: 462a mov r2, r5 801540e: 4638 mov r0, r7 8015410: 4b0e ldr r3, [pc, #56] @ (801544c <_svfiprintf_r+0x1f4>) 8015412: a904 add r1, sp, #16 8015414: f7fe fb28 bl 8013a68 <_printf_float> 8015418: 1c42 adds r2, r0, #1 801541a: 4606 mov r6, r0 801541c: d1d6 bne.n 80153cc <_svfiprintf_r+0x174> 801541e: 89ab ldrh r3, [r5, #12] 8015420: 065b lsls r3, r3, #25 8015422: f53f af2d bmi.w 8015280 <_svfiprintf_r+0x28> 8015426: 9809 ldr r0, [sp, #36] @ 0x24 8015428: e72c b.n 8015284 <_svfiprintf_r+0x2c> 801542a: ab03 add r3, sp, #12 801542c: 9300 str r3, [sp, #0] 801542e: 462a mov r2, r5 8015430: 4638 mov r0, r7 8015432: 4b06 ldr r3, [pc, #24] @ (801544c <_svfiprintf_r+0x1f4>) 8015434: a904 add r1, sp, #16 8015436: f7fe fdb5 bl 8013fa4 <_printf_i> 801543a: e7ed b.n 8015418 <_svfiprintf_r+0x1c0> 801543c: 08016fd9 .word 0x08016fd9 8015440: 08016fdf .word 0x08016fdf 8015444: 08016fe3 .word 0x08016fe3 8015448: 08013a69 .word 0x08013a69 801544c: 080151a1 .word 0x080151a1 08015450 <__sfputc_r>: 8015450: 6893 ldr r3, [r2, #8] 8015452: b410 push {r4} 8015454: 3b01 subs r3, #1 8015456: 2b00 cmp r3, #0 8015458: 6093 str r3, [r2, #8] 801545a: da07 bge.n 801546c <__sfputc_r+0x1c> 801545c: 6994 ldr r4, [r2, #24] 801545e: 42a3 cmp r3, r4 8015460: db01 blt.n 8015466 <__sfputc_r+0x16> 8015462: 290a cmp r1, #10 8015464: d102 bne.n 801546c <__sfputc_r+0x1c> 8015466: bc10 pop {r4} 8015468: f000 be8e b.w 8016188 <__swbuf_r> 801546c: 6813 ldr r3, [r2, #0] 801546e: 1c58 adds r0, r3, #1 8015470: 6010 str r0, [r2, #0] 8015472: 7019 strb r1, [r3, #0] 8015474: 4608 mov r0, r1 8015476: bc10 pop {r4} 8015478: 4770 bx lr 0801547a <__sfputs_r>: 801547a: b5f8 push {r3, r4, r5, r6, r7, lr} 801547c: 4606 mov r6, r0 801547e: 460f mov r7, r1 8015480: 4614 mov r4, r2 8015482: 18d5 adds r5, r2, r3 8015484: 42ac cmp r4, r5 8015486: d101 bne.n 801548c <__sfputs_r+0x12> 8015488: 2000 movs r0, #0 801548a: e007 b.n 801549c <__sfputs_r+0x22> 801548c: 463a mov r2, r7 801548e: 4630 mov r0, r6 8015490: f814 1b01 ldrb.w r1, [r4], #1 8015494: f7ff ffdc bl 8015450 <__sfputc_r> 8015498: 1c43 adds r3, r0, #1 801549a: d1f3 bne.n 8015484 <__sfputs_r+0xa> 801549c: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 080154a0 <_vfiprintf_r>: 80154a0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80154a4: 460d mov r5, r1 80154a6: 4614 mov r4, r2 80154a8: 4698 mov r8, r3 80154aa: 4606 mov r6, r0 80154ac: b09d sub sp, #116 @ 0x74 80154ae: b118 cbz r0, 80154b8 <_vfiprintf_r+0x18> 80154b0: 6a03 ldr r3, [r0, #32] 80154b2: b90b cbnz r3, 80154b8 <_vfiprintf_r+0x18> 80154b4: f7fe ff20 bl 80142f8 <__sinit> 80154b8: 6e6b ldr r3, [r5, #100] @ 0x64 80154ba: 07d9 lsls r1, r3, #31 80154bc: d405 bmi.n 80154ca <_vfiprintf_r+0x2a> 80154be: 89ab ldrh r3, [r5, #12] 80154c0: 059a lsls r2, r3, #22 80154c2: d402 bmi.n 80154ca <_vfiprintf_r+0x2a> 80154c4: 6da8 ldr r0, [r5, #88] @ 0x58 80154c6: f7fe ffce bl 8014466 <__retarget_lock_acquire_recursive> 80154ca: 89ab ldrh r3, [r5, #12] 80154cc: 071b lsls r3, r3, #28 80154ce: d501 bpl.n 80154d4 <_vfiprintf_r+0x34> 80154d0: 692b ldr r3, [r5, #16] 80154d2: b99b cbnz r3, 80154fc <_vfiprintf_r+0x5c> 80154d4: 4629 mov r1, r5 80154d6: 4630 mov r0, r6 80154d8: f000 fe94 bl 8016204 <__swsetup_r> 80154dc: b170 cbz r0, 80154fc <_vfiprintf_r+0x5c> 80154de: 6e6b ldr r3, [r5, #100] @ 0x64 80154e0: 07dc lsls r4, r3, #31 80154e2: d504 bpl.n 80154ee <_vfiprintf_r+0x4e> 80154e4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80154e8: b01d add sp, #116 @ 0x74 80154ea: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80154ee: 89ab ldrh r3, [r5, #12] 80154f0: 0598 lsls r0, r3, #22 80154f2: d4f7 bmi.n 80154e4 <_vfiprintf_r+0x44> 80154f4: 6da8 ldr r0, [r5, #88] @ 0x58 80154f6: f7fe ffb7 bl 8014468 <__retarget_lock_release_recursive> 80154fa: e7f3 b.n 80154e4 <_vfiprintf_r+0x44> 80154fc: 2300 movs r3, #0 80154fe: 9309 str r3, [sp, #36] @ 0x24 8015500: 2320 movs r3, #32 8015502: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8015506: 2330 movs r3, #48 @ 0x30 8015508: f04f 0901 mov.w r9, #1 801550c: f8cd 800c str.w r8, [sp, #12] 8015510: f8df 81a8 ldr.w r8, [pc, #424] @ 80156bc <_vfiprintf_r+0x21c> 8015514: f88d 302a strb.w r3, [sp, #42] @ 0x2a 8015518: 4623 mov r3, r4 801551a: 469a mov sl, r3 801551c: f813 2b01 ldrb.w r2, [r3], #1 8015520: b10a cbz r2, 8015526 <_vfiprintf_r+0x86> 8015522: 2a25 cmp r2, #37 @ 0x25 8015524: d1f9 bne.n 801551a <_vfiprintf_r+0x7a> 8015526: ebba 0b04 subs.w fp, sl, r4 801552a: d00b beq.n 8015544 <_vfiprintf_r+0xa4> 801552c: 465b mov r3, fp 801552e: 4622 mov r2, r4 8015530: 4629 mov r1, r5 8015532: 4630 mov r0, r6 8015534: f7ff ffa1 bl 801547a <__sfputs_r> 8015538: 3001 adds r0, #1 801553a: f000 80a7 beq.w 801568c <_vfiprintf_r+0x1ec> 801553e: 9a09 ldr r2, [sp, #36] @ 0x24 8015540: 445a add r2, fp 8015542: 9209 str r2, [sp, #36] @ 0x24 8015544: f89a 3000 ldrb.w r3, [sl] 8015548: 2b00 cmp r3, #0 801554a: f000 809f beq.w 801568c <_vfiprintf_r+0x1ec> 801554e: 2300 movs r3, #0 8015550: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8015554: e9cd 2305 strd r2, r3, [sp, #20] 8015558: f10a 0a01 add.w sl, sl, #1 801555c: 9304 str r3, [sp, #16] 801555e: 9307 str r3, [sp, #28] 8015560: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8015564: 931a str r3, [sp, #104] @ 0x68 8015566: 4654 mov r4, sl 8015568: 2205 movs r2, #5 801556a: f814 1b01 ldrb.w r1, [r4], #1 801556e: 4853 ldr r0, [pc, #332] @ (80156bc <_vfiprintf_r+0x21c>) 8015570: f7fe ff80 bl 8014474 8015574: 9a04 ldr r2, [sp, #16] 8015576: b9d8 cbnz r0, 80155b0 <_vfiprintf_r+0x110> 8015578: 06d1 lsls r1, r2, #27 801557a: bf44 itt mi 801557c: 2320 movmi r3, #32 801557e: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8015582: 0713 lsls r3, r2, #28 8015584: bf44 itt mi 8015586: 232b movmi r3, #43 @ 0x2b 8015588: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 801558c: f89a 3000 ldrb.w r3, [sl] 8015590: 2b2a cmp r3, #42 @ 0x2a 8015592: d015 beq.n 80155c0 <_vfiprintf_r+0x120> 8015594: 4654 mov r4, sl 8015596: 2000 movs r0, #0 8015598: f04f 0c0a mov.w ip, #10 801559c: 9a07 ldr r2, [sp, #28] 801559e: 4621 mov r1, r4 80155a0: f811 3b01 ldrb.w r3, [r1], #1 80155a4: 3b30 subs r3, #48 @ 0x30 80155a6: 2b09 cmp r3, #9 80155a8: d94b bls.n 8015642 <_vfiprintf_r+0x1a2> 80155aa: b1b0 cbz r0, 80155da <_vfiprintf_r+0x13a> 80155ac: 9207 str r2, [sp, #28] 80155ae: e014 b.n 80155da <_vfiprintf_r+0x13a> 80155b0: eba0 0308 sub.w r3, r0, r8 80155b4: fa09 f303 lsl.w r3, r9, r3 80155b8: 4313 orrs r3, r2 80155ba: 46a2 mov sl, r4 80155bc: 9304 str r3, [sp, #16] 80155be: e7d2 b.n 8015566 <_vfiprintf_r+0xc6> 80155c0: 9b03 ldr r3, [sp, #12] 80155c2: 1d19 adds r1, r3, #4 80155c4: 681b ldr r3, [r3, #0] 80155c6: 9103 str r1, [sp, #12] 80155c8: 2b00 cmp r3, #0 80155ca: bfbb ittet lt 80155cc: 425b neglt r3, r3 80155ce: f042 0202 orrlt.w r2, r2, #2 80155d2: 9307 strge r3, [sp, #28] 80155d4: 9307 strlt r3, [sp, #28] 80155d6: bfb8 it lt 80155d8: 9204 strlt r2, [sp, #16] 80155da: 7823 ldrb r3, [r4, #0] 80155dc: 2b2e cmp r3, #46 @ 0x2e 80155de: d10a bne.n 80155f6 <_vfiprintf_r+0x156> 80155e0: 7863 ldrb r3, [r4, #1] 80155e2: 2b2a cmp r3, #42 @ 0x2a 80155e4: d132 bne.n 801564c <_vfiprintf_r+0x1ac> 80155e6: 9b03 ldr r3, [sp, #12] 80155e8: 3402 adds r4, #2 80155ea: 1d1a adds r2, r3, #4 80155ec: 681b ldr r3, [r3, #0] 80155ee: 9203 str r2, [sp, #12] 80155f0: ea43 73e3 orr.w r3, r3, r3, asr #31 80155f4: 9305 str r3, [sp, #20] 80155f6: f8df a0c8 ldr.w sl, [pc, #200] @ 80156c0 <_vfiprintf_r+0x220> 80155fa: 2203 movs r2, #3 80155fc: 4650 mov r0, sl 80155fe: 7821 ldrb r1, [r4, #0] 8015600: f7fe ff38 bl 8014474 8015604: b138 cbz r0, 8015616 <_vfiprintf_r+0x176> 8015606: 2240 movs r2, #64 @ 0x40 8015608: 9b04 ldr r3, [sp, #16] 801560a: eba0 000a sub.w r0, r0, sl 801560e: 4082 lsls r2, r0 8015610: 4313 orrs r3, r2 8015612: 3401 adds r4, #1 8015614: 9304 str r3, [sp, #16] 8015616: f814 1b01 ldrb.w r1, [r4], #1 801561a: 2206 movs r2, #6 801561c: 4829 ldr r0, [pc, #164] @ (80156c4 <_vfiprintf_r+0x224>) 801561e: f88d 1028 strb.w r1, [sp, #40] @ 0x28 8015622: f7fe ff27 bl 8014474 8015626: 2800 cmp r0, #0 8015628: d03f beq.n 80156aa <_vfiprintf_r+0x20a> 801562a: 4b27 ldr r3, [pc, #156] @ (80156c8 <_vfiprintf_r+0x228>) 801562c: bb1b cbnz r3, 8015676 <_vfiprintf_r+0x1d6> 801562e: 9b03 ldr r3, [sp, #12] 8015630: 3307 adds r3, #7 8015632: f023 0307 bic.w r3, r3, #7 8015636: 3308 adds r3, #8 8015638: 9303 str r3, [sp, #12] 801563a: 9b09 ldr r3, [sp, #36] @ 0x24 801563c: 443b add r3, r7 801563e: 9309 str r3, [sp, #36] @ 0x24 8015640: e76a b.n 8015518 <_vfiprintf_r+0x78> 8015642: 460c mov r4, r1 8015644: 2001 movs r0, #1 8015646: fb0c 3202 mla r2, ip, r2, r3 801564a: e7a8 b.n 801559e <_vfiprintf_r+0xfe> 801564c: 2300 movs r3, #0 801564e: f04f 0c0a mov.w ip, #10 8015652: 4619 mov r1, r3 8015654: 3401 adds r4, #1 8015656: 9305 str r3, [sp, #20] 8015658: 4620 mov r0, r4 801565a: f810 2b01 ldrb.w r2, [r0], #1 801565e: 3a30 subs r2, #48 @ 0x30 8015660: 2a09 cmp r2, #9 8015662: d903 bls.n 801566c <_vfiprintf_r+0x1cc> 8015664: 2b00 cmp r3, #0 8015666: d0c6 beq.n 80155f6 <_vfiprintf_r+0x156> 8015668: 9105 str r1, [sp, #20] 801566a: e7c4 b.n 80155f6 <_vfiprintf_r+0x156> 801566c: 4604 mov r4, r0 801566e: 2301 movs r3, #1 8015670: fb0c 2101 mla r1, ip, r1, r2 8015674: e7f0 b.n 8015658 <_vfiprintf_r+0x1b8> 8015676: ab03 add r3, sp, #12 8015678: 9300 str r3, [sp, #0] 801567a: 462a mov r2, r5 801567c: 4630 mov r0, r6 801567e: 4b13 ldr r3, [pc, #76] @ (80156cc <_vfiprintf_r+0x22c>) 8015680: a904 add r1, sp, #16 8015682: f7fe f9f1 bl 8013a68 <_printf_float> 8015686: 4607 mov r7, r0 8015688: 1c78 adds r0, r7, #1 801568a: d1d6 bne.n 801563a <_vfiprintf_r+0x19a> 801568c: 6e6b ldr r3, [r5, #100] @ 0x64 801568e: 07d9 lsls r1, r3, #31 8015690: d405 bmi.n 801569e <_vfiprintf_r+0x1fe> 8015692: 89ab ldrh r3, [r5, #12] 8015694: 059a lsls r2, r3, #22 8015696: d402 bmi.n 801569e <_vfiprintf_r+0x1fe> 8015698: 6da8 ldr r0, [r5, #88] @ 0x58 801569a: f7fe fee5 bl 8014468 <__retarget_lock_release_recursive> 801569e: 89ab ldrh r3, [r5, #12] 80156a0: 065b lsls r3, r3, #25 80156a2: f53f af1f bmi.w 80154e4 <_vfiprintf_r+0x44> 80156a6: 9809 ldr r0, [sp, #36] @ 0x24 80156a8: e71e b.n 80154e8 <_vfiprintf_r+0x48> 80156aa: ab03 add r3, sp, #12 80156ac: 9300 str r3, [sp, #0] 80156ae: 462a mov r2, r5 80156b0: 4630 mov r0, r6 80156b2: 4b06 ldr r3, [pc, #24] @ (80156cc <_vfiprintf_r+0x22c>) 80156b4: a904 add r1, sp, #16 80156b6: f7fe fc75 bl 8013fa4 <_printf_i> 80156ba: e7e4 b.n 8015686 <_vfiprintf_r+0x1e6> 80156bc: 08016fd9 .word 0x08016fd9 80156c0: 08016fdf .word 0x08016fdf 80156c4: 08016fe3 .word 0x08016fe3 80156c8: 08013a69 .word 0x08013a69 80156cc: 0801547b .word 0x0801547b 080156d0 : 80156d0: 4b02 ldr r3, [pc, #8] @ (80156dc ) 80156d2: 4601 mov r1, r0 80156d4: 6818 ldr r0, [r3, #0] 80156d6: f000 b825 b.w 8015724 <_malloc_r> 80156da: bf00 nop 80156dc: 20000084 .word 0x20000084 080156e0 : 80156e0: b570 push {r4, r5, r6, lr} 80156e2: 4e0f ldr r6, [pc, #60] @ (8015720 ) 80156e4: 460c mov r4, r1 80156e6: 6831 ldr r1, [r6, #0] 80156e8: 4605 mov r5, r0 80156ea: b911 cbnz r1, 80156f2 80156ec: f000 fe90 bl 8016410 <_sbrk_r> 80156f0: 6030 str r0, [r6, #0] 80156f2: 4621 mov r1, r4 80156f4: 4628 mov r0, r5 80156f6: f000 fe8b bl 8016410 <_sbrk_r> 80156fa: 1c43 adds r3, r0, #1 80156fc: d103 bne.n 8015706 80156fe: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 8015702: 4620 mov r0, r4 8015704: bd70 pop {r4, r5, r6, pc} 8015706: 1cc4 adds r4, r0, #3 8015708: f024 0403 bic.w r4, r4, #3 801570c: 42a0 cmp r0, r4 801570e: d0f8 beq.n 8015702 8015710: 1a21 subs r1, r4, r0 8015712: 4628 mov r0, r5 8015714: f000 fe7c bl 8016410 <_sbrk_r> 8015718: 3001 adds r0, #1 801571a: d1f2 bne.n 8015702 801571c: e7ef b.n 80156fe 801571e: bf00 nop 8015720: 2000138c .word 0x2000138c 08015724 <_malloc_r>: 8015724: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8015728: 1ccd adds r5, r1, #3 801572a: f025 0503 bic.w r5, r5, #3 801572e: 3508 adds r5, #8 8015730: 2d0c cmp r5, #12 8015732: bf38 it cc 8015734: 250c movcc r5, #12 8015736: 2d00 cmp r5, #0 8015738: 4606 mov r6, r0 801573a: db01 blt.n 8015740 <_malloc_r+0x1c> 801573c: 42a9 cmp r1, r5 801573e: d904 bls.n 801574a <_malloc_r+0x26> 8015740: 230c movs r3, #12 8015742: 6033 str r3, [r6, #0] 8015744: 2000 movs r0, #0 8015746: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 801574a: f8df 80d4 ldr.w r8, [pc, #212] @ 8015820 <_malloc_r+0xfc> 801574e: f000 f911 bl 8015974 <__malloc_lock> 8015752: f8d8 3000 ldr.w r3, [r8] 8015756: 461c mov r4, r3 8015758: bb44 cbnz r4, 80157ac <_malloc_r+0x88> 801575a: 4629 mov r1, r5 801575c: 4630 mov r0, r6 801575e: f7ff ffbf bl 80156e0 8015762: 1c43 adds r3, r0, #1 8015764: 4604 mov r4, r0 8015766: d158 bne.n 801581a <_malloc_r+0xf6> 8015768: f8d8 4000 ldr.w r4, [r8] 801576c: 4627 mov r7, r4 801576e: 2f00 cmp r7, #0 8015770: d143 bne.n 80157fa <_malloc_r+0xd6> 8015772: 2c00 cmp r4, #0 8015774: d04b beq.n 801580e <_malloc_r+0xea> 8015776: 6823 ldr r3, [r4, #0] 8015778: 4639 mov r1, r7 801577a: 4630 mov r0, r6 801577c: eb04 0903 add.w r9, r4, r3 8015780: f000 fe46 bl 8016410 <_sbrk_r> 8015784: 4581 cmp r9, r0 8015786: d142 bne.n 801580e <_malloc_r+0xea> 8015788: 6821 ldr r1, [r4, #0] 801578a: 4630 mov r0, r6 801578c: 1a6d subs r5, r5, r1 801578e: 4629 mov r1, r5 8015790: f7ff ffa6 bl 80156e0 8015794: 3001 adds r0, #1 8015796: d03a beq.n 801580e <_malloc_r+0xea> 8015798: 6823 ldr r3, [r4, #0] 801579a: 442b add r3, r5 801579c: 6023 str r3, [r4, #0] 801579e: f8d8 3000 ldr.w r3, [r8] 80157a2: 685a ldr r2, [r3, #4] 80157a4: bb62 cbnz r2, 8015800 <_malloc_r+0xdc> 80157a6: f8c8 7000 str.w r7, [r8] 80157aa: e00f b.n 80157cc <_malloc_r+0xa8> 80157ac: 6822 ldr r2, [r4, #0] 80157ae: 1b52 subs r2, r2, r5 80157b0: d420 bmi.n 80157f4 <_malloc_r+0xd0> 80157b2: 2a0b cmp r2, #11 80157b4: d917 bls.n 80157e6 <_malloc_r+0xc2> 80157b6: 1961 adds r1, r4, r5 80157b8: 42a3 cmp r3, r4 80157ba: 6025 str r5, [r4, #0] 80157bc: bf18 it ne 80157be: 6059 strne r1, [r3, #4] 80157c0: 6863 ldr r3, [r4, #4] 80157c2: bf08 it eq 80157c4: f8c8 1000 streq.w r1, [r8] 80157c8: 5162 str r2, [r4, r5] 80157ca: 604b str r3, [r1, #4] 80157cc: 4630 mov r0, r6 80157ce: f000 f8d7 bl 8015980 <__malloc_unlock> 80157d2: f104 000b add.w r0, r4, #11 80157d6: 1d23 adds r3, r4, #4 80157d8: f020 0007 bic.w r0, r0, #7 80157dc: 1ac2 subs r2, r0, r3 80157de: bf1c itt ne 80157e0: 1a1b subne r3, r3, r0 80157e2: 50a3 strne r3, [r4, r2] 80157e4: e7af b.n 8015746 <_malloc_r+0x22> 80157e6: 6862 ldr r2, [r4, #4] 80157e8: 42a3 cmp r3, r4 80157ea: bf0c ite eq 80157ec: f8c8 2000 streq.w r2, [r8] 80157f0: 605a strne r2, [r3, #4] 80157f2: e7eb b.n 80157cc <_malloc_r+0xa8> 80157f4: 4623 mov r3, r4 80157f6: 6864 ldr r4, [r4, #4] 80157f8: e7ae b.n 8015758 <_malloc_r+0x34> 80157fa: 463c mov r4, r7 80157fc: 687f ldr r7, [r7, #4] 80157fe: e7b6 b.n 801576e <_malloc_r+0x4a> 8015800: 461a mov r2, r3 8015802: 685b ldr r3, [r3, #4] 8015804: 42a3 cmp r3, r4 8015806: d1fb bne.n 8015800 <_malloc_r+0xdc> 8015808: 2300 movs r3, #0 801580a: 6053 str r3, [r2, #4] 801580c: e7de b.n 80157cc <_malloc_r+0xa8> 801580e: 230c movs r3, #12 8015810: 4630 mov r0, r6 8015812: 6033 str r3, [r6, #0] 8015814: f000 f8b4 bl 8015980 <__malloc_unlock> 8015818: e794 b.n 8015744 <_malloc_r+0x20> 801581a: 6005 str r5, [r0, #0] 801581c: e7d6 b.n 80157cc <_malloc_r+0xa8> 801581e: bf00 nop 8015820: 20001390 .word 0x20001390 08015824 <__sflush_r>: 8015824: f9b1 200c ldrsh.w r2, [r1, #12] 8015828: b5f8 push {r3, r4, r5, r6, r7, lr} 801582a: 0716 lsls r6, r2, #28 801582c: 4605 mov r5, r0 801582e: 460c mov r4, r1 8015830: d454 bmi.n 80158dc <__sflush_r+0xb8> 8015832: 684b ldr r3, [r1, #4] 8015834: 2b00 cmp r3, #0 8015836: dc02 bgt.n 801583e <__sflush_r+0x1a> 8015838: 6c0b ldr r3, [r1, #64] @ 0x40 801583a: 2b00 cmp r3, #0 801583c: dd48 ble.n 80158d0 <__sflush_r+0xac> 801583e: 6ae6 ldr r6, [r4, #44] @ 0x2c 8015840: 2e00 cmp r6, #0 8015842: d045 beq.n 80158d0 <__sflush_r+0xac> 8015844: 2300 movs r3, #0 8015846: f412 5280 ands.w r2, r2, #4096 @ 0x1000 801584a: 682f ldr r7, [r5, #0] 801584c: 6a21 ldr r1, [r4, #32] 801584e: 602b str r3, [r5, #0] 8015850: d030 beq.n 80158b4 <__sflush_r+0x90> 8015852: 6d62 ldr r2, [r4, #84] @ 0x54 8015854: 89a3 ldrh r3, [r4, #12] 8015856: 0759 lsls r1, r3, #29 8015858: d505 bpl.n 8015866 <__sflush_r+0x42> 801585a: 6863 ldr r3, [r4, #4] 801585c: 1ad2 subs r2, r2, r3 801585e: 6b63 ldr r3, [r4, #52] @ 0x34 8015860: b10b cbz r3, 8015866 <__sflush_r+0x42> 8015862: 6c23 ldr r3, [r4, #64] @ 0x40 8015864: 1ad2 subs r2, r2, r3 8015866: 2300 movs r3, #0 8015868: 4628 mov r0, r5 801586a: 6ae6 ldr r6, [r4, #44] @ 0x2c 801586c: 6a21 ldr r1, [r4, #32] 801586e: 47b0 blx r6 8015870: 1c43 adds r3, r0, #1 8015872: 89a3 ldrh r3, [r4, #12] 8015874: d106 bne.n 8015884 <__sflush_r+0x60> 8015876: 6829 ldr r1, [r5, #0] 8015878: 291d cmp r1, #29 801587a: d82b bhi.n 80158d4 <__sflush_r+0xb0> 801587c: 4a28 ldr r2, [pc, #160] @ (8015920 <__sflush_r+0xfc>) 801587e: 40ca lsrs r2, r1 8015880: 07d6 lsls r6, r2, #31 8015882: d527 bpl.n 80158d4 <__sflush_r+0xb0> 8015884: 2200 movs r2, #0 8015886: 6062 str r2, [r4, #4] 8015888: 6922 ldr r2, [r4, #16] 801588a: 04d9 lsls r1, r3, #19 801588c: 6022 str r2, [r4, #0] 801588e: d504 bpl.n 801589a <__sflush_r+0x76> 8015890: 1c42 adds r2, r0, #1 8015892: d101 bne.n 8015898 <__sflush_r+0x74> 8015894: 682b ldr r3, [r5, #0] 8015896: b903 cbnz r3, 801589a <__sflush_r+0x76> 8015898: 6560 str r0, [r4, #84] @ 0x54 801589a: 6b61 ldr r1, [r4, #52] @ 0x34 801589c: 602f str r7, [r5, #0] 801589e: b1b9 cbz r1, 80158d0 <__sflush_r+0xac> 80158a0: f104 0344 add.w r3, r4, #68 @ 0x44 80158a4: 4299 cmp r1, r3 80158a6: d002 beq.n 80158ae <__sflush_r+0x8a> 80158a8: 4628 mov r0, r5 80158aa: f000 fe11 bl 80164d0 <_free_r> 80158ae: 2300 movs r3, #0 80158b0: 6363 str r3, [r4, #52] @ 0x34 80158b2: e00d b.n 80158d0 <__sflush_r+0xac> 80158b4: 2301 movs r3, #1 80158b6: 4628 mov r0, r5 80158b8: 47b0 blx r6 80158ba: 4602 mov r2, r0 80158bc: 1c50 adds r0, r2, #1 80158be: d1c9 bne.n 8015854 <__sflush_r+0x30> 80158c0: 682b ldr r3, [r5, #0] 80158c2: 2b00 cmp r3, #0 80158c4: d0c6 beq.n 8015854 <__sflush_r+0x30> 80158c6: 2b1d cmp r3, #29 80158c8: d001 beq.n 80158ce <__sflush_r+0xaa> 80158ca: 2b16 cmp r3, #22 80158cc: d11d bne.n 801590a <__sflush_r+0xe6> 80158ce: 602f str r7, [r5, #0] 80158d0: 2000 movs r0, #0 80158d2: e021 b.n 8015918 <__sflush_r+0xf4> 80158d4: f043 0340 orr.w r3, r3, #64 @ 0x40 80158d8: b21b sxth r3, r3 80158da: e01a b.n 8015912 <__sflush_r+0xee> 80158dc: 690f ldr r7, [r1, #16] 80158de: 2f00 cmp r7, #0 80158e0: d0f6 beq.n 80158d0 <__sflush_r+0xac> 80158e2: 0793 lsls r3, r2, #30 80158e4: bf18 it ne 80158e6: 2300 movne r3, #0 80158e8: 680e ldr r6, [r1, #0] 80158ea: bf08 it eq 80158ec: 694b ldreq r3, [r1, #20] 80158ee: 1bf6 subs r6, r6, r7 80158f0: 600f str r7, [r1, #0] 80158f2: 608b str r3, [r1, #8] 80158f4: 2e00 cmp r6, #0 80158f6: ddeb ble.n 80158d0 <__sflush_r+0xac> 80158f8: 4633 mov r3, r6 80158fa: 463a mov r2, r7 80158fc: 4628 mov r0, r5 80158fe: 6a21 ldr r1, [r4, #32] 8015900: f8d4 c028 ldr.w ip, [r4, #40] @ 0x28 8015904: 47e0 blx ip 8015906: 2800 cmp r0, #0 8015908: dc07 bgt.n 801591a <__sflush_r+0xf6> 801590a: f9b4 300c ldrsh.w r3, [r4, #12] 801590e: f043 0340 orr.w r3, r3, #64 @ 0x40 8015912: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015916: 81a3 strh r3, [r4, #12] 8015918: bdf8 pop {r3, r4, r5, r6, r7, pc} 801591a: 4407 add r7, r0 801591c: 1a36 subs r6, r6, r0 801591e: e7e9 b.n 80158f4 <__sflush_r+0xd0> 8015920: 20400001 .word 0x20400001 08015924 <_fflush_r>: 8015924: b538 push {r3, r4, r5, lr} 8015926: 690b ldr r3, [r1, #16] 8015928: 4605 mov r5, r0 801592a: 460c mov r4, r1 801592c: b913 cbnz r3, 8015934 <_fflush_r+0x10> 801592e: 2500 movs r5, #0 8015930: 4628 mov r0, r5 8015932: bd38 pop {r3, r4, r5, pc} 8015934: b118 cbz r0, 801593e <_fflush_r+0x1a> 8015936: 6a03 ldr r3, [r0, #32] 8015938: b90b cbnz r3, 801593e <_fflush_r+0x1a> 801593a: f7fe fcdd bl 80142f8 <__sinit> 801593e: f9b4 300c ldrsh.w r3, [r4, #12] 8015942: 2b00 cmp r3, #0 8015944: d0f3 beq.n 801592e <_fflush_r+0xa> 8015946: 6e62 ldr r2, [r4, #100] @ 0x64 8015948: 07d0 lsls r0, r2, #31 801594a: d404 bmi.n 8015956 <_fflush_r+0x32> 801594c: 0599 lsls r1, r3, #22 801594e: d402 bmi.n 8015956 <_fflush_r+0x32> 8015950: 6da0 ldr r0, [r4, #88] @ 0x58 8015952: f7fe fd88 bl 8014466 <__retarget_lock_acquire_recursive> 8015956: 4628 mov r0, r5 8015958: 4621 mov r1, r4 801595a: f7ff ff63 bl 8015824 <__sflush_r> 801595e: 6e63 ldr r3, [r4, #100] @ 0x64 8015960: 4605 mov r5, r0 8015962: 07da lsls r2, r3, #31 8015964: d4e4 bmi.n 8015930 <_fflush_r+0xc> 8015966: 89a3 ldrh r3, [r4, #12] 8015968: 059b lsls r3, r3, #22 801596a: d4e1 bmi.n 8015930 <_fflush_r+0xc> 801596c: 6da0 ldr r0, [r4, #88] @ 0x58 801596e: f7fe fd7b bl 8014468 <__retarget_lock_release_recursive> 8015972: e7dd b.n 8015930 <_fflush_r+0xc> 08015974 <__malloc_lock>: 8015974: 4801 ldr r0, [pc, #4] @ (801597c <__malloc_lock+0x8>) 8015976: f7fe bd76 b.w 8014466 <__retarget_lock_acquire_recursive> 801597a: bf00 nop 801597c: 20001388 .word 0x20001388 08015980 <__malloc_unlock>: 8015980: 4801 ldr r0, [pc, #4] @ (8015988 <__malloc_unlock+0x8>) 8015982: f7fe bd71 b.w 8014468 <__retarget_lock_release_recursive> 8015986: bf00 nop 8015988: 20001388 .word 0x20001388 0801598c <_Balloc>: 801598c: b570 push {r4, r5, r6, lr} 801598e: 69c6 ldr r6, [r0, #28] 8015990: 4604 mov r4, r0 8015992: 460d mov r5, r1 8015994: b976 cbnz r6, 80159b4 <_Balloc+0x28> 8015996: 2010 movs r0, #16 8015998: f7ff fe9a bl 80156d0 801599c: 4602 mov r2, r0 801599e: 61e0 str r0, [r4, #28] 80159a0: b920 cbnz r0, 80159ac <_Balloc+0x20> 80159a2: 216b movs r1, #107 @ 0x6b 80159a4: 4b17 ldr r3, [pc, #92] @ (8015a04 <_Balloc+0x78>) 80159a6: 4818 ldr r0, [pc, #96] @ (8015a08 <_Balloc+0x7c>) 80159a8: f7fe fd80 bl 80144ac <__assert_func> 80159ac: e9c0 6601 strd r6, r6, [r0, #4] 80159b0: 6006 str r6, [r0, #0] 80159b2: 60c6 str r6, [r0, #12] 80159b4: 69e6 ldr r6, [r4, #28] 80159b6: 68f3 ldr r3, [r6, #12] 80159b8: b183 cbz r3, 80159dc <_Balloc+0x50> 80159ba: 69e3 ldr r3, [r4, #28] 80159bc: 68db ldr r3, [r3, #12] 80159be: f853 0025 ldr.w r0, [r3, r5, lsl #2] 80159c2: b9b8 cbnz r0, 80159f4 <_Balloc+0x68> 80159c4: 2101 movs r1, #1 80159c6: fa01 f605 lsl.w r6, r1, r5 80159ca: 1d72 adds r2, r6, #5 80159cc: 4620 mov r0, r4 80159ce: 0092 lsls r2, r2, #2 80159d0: f000 fd69 bl 80164a6 <_calloc_r> 80159d4: b160 cbz r0, 80159f0 <_Balloc+0x64> 80159d6: e9c0 5601 strd r5, r6, [r0, #4] 80159da: e00e b.n 80159fa <_Balloc+0x6e> 80159dc: 2221 movs r2, #33 @ 0x21 80159de: 2104 movs r1, #4 80159e0: 4620 mov r0, r4 80159e2: f000 fd60 bl 80164a6 <_calloc_r> 80159e6: 69e3 ldr r3, [r4, #28] 80159e8: 60f0 str r0, [r6, #12] 80159ea: 68db ldr r3, [r3, #12] 80159ec: 2b00 cmp r3, #0 80159ee: d1e4 bne.n 80159ba <_Balloc+0x2e> 80159f0: 2000 movs r0, #0 80159f2: bd70 pop {r4, r5, r6, pc} 80159f4: 6802 ldr r2, [r0, #0] 80159f6: f843 2025 str.w r2, [r3, r5, lsl #2] 80159fa: 2300 movs r3, #0 80159fc: e9c0 3303 strd r3, r3, [r0, #12] 8015a00: e7f7 b.n 80159f2 <_Balloc+0x66> 8015a02: bf00 nop 8015a04: 08016f59 .word 0x08016f59 8015a08: 08016fea .word 0x08016fea 08015a0c <_Bfree>: 8015a0c: b570 push {r4, r5, r6, lr} 8015a0e: 69c6 ldr r6, [r0, #28] 8015a10: 4605 mov r5, r0 8015a12: 460c mov r4, r1 8015a14: b976 cbnz r6, 8015a34 <_Bfree+0x28> 8015a16: 2010 movs r0, #16 8015a18: f7ff fe5a bl 80156d0 8015a1c: 4602 mov r2, r0 8015a1e: 61e8 str r0, [r5, #28] 8015a20: b920 cbnz r0, 8015a2c <_Bfree+0x20> 8015a22: 218f movs r1, #143 @ 0x8f 8015a24: 4b08 ldr r3, [pc, #32] @ (8015a48 <_Bfree+0x3c>) 8015a26: 4809 ldr r0, [pc, #36] @ (8015a4c <_Bfree+0x40>) 8015a28: f7fe fd40 bl 80144ac <__assert_func> 8015a2c: e9c0 6601 strd r6, r6, [r0, #4] 8015a30: 6006 str r6, [r0, #0] 8015a32: 60c6 str r6, [r0, #12] 8015a34: b13c cbz r4, 8015a46 <_Bfree+0x3a> 8015a36: 69eb ldr r3, [r5, #28] 8015a38: 6862 ldr r2, [r4, #4] 8015a3a: 68db ldr r3, [r3, #12] 8015a3c: f853 1022 ldr.w r1, [r3, r2, lsl #2] 8015a40: 6021 str r1, [r4, #0] 8015a42: f843 4022 str.w r4, [r3, r2, lsl #2] 8015a46: bd70 pop {r4, r5, r6, pc} 8015a48: 08016f59 .word 0x08016f59 8015a4c: 08016fea .word 0x08016fea 08015a50 <__multadd>: 8015a50: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8015a54: 4607 mov r7, r0 8015a56: 460c mov r4, r1 8015a58: 461e mov r6, r3 8015a5a: 2000 movs r0, #0 8015a5c: 690d ldr r5, [r1, #16] 8015a5e: f101 0c14 add.w ip, r1, #20 8015a62: f8dc 3000 ldr.w r3, [ip] 8015a66: 3001 adds r0, #1 8015a68: b299 uxth r1, r3 8015a6a: fb02 6101 mla r1, r2, r1, r6 8015a6e: 0c1e lsrs r6, r3, #16 8015a70: 0c0b lsrs r3, r1, #16 8015a72: fb02 3306 mla r3, r2, r6, r3 8015a76: b289 uxth r1, r1 8015a78: eb01 4103 add.w r1, r1, r3, lsl #16 8015a7c: 4285 cmp r5, r0 8015a7e: ea4f 4613 mov.w r6, r3, lsr #16 8015a82: f84c 1b04 str.w r1, [ip], #4 8015a86: dcec bgt.n 8015a62 <__multadd+0x12> 8015a88: b30e cbz r6, 8015ace <__multadd+0x7e> 8015a8a: 68a3 ldr r3, [r4, #8] 8015a8c: 42ab cmp r3, r5 8015a8e: dc19 bgt.n 8015ac4 <__multadd+0x74> 8015a90: 6861 ldr r1, [r4, #4] 8015a92: 4638 mov r0, r7 8015a94: 3101 adds r1, #1 8015a96: f7ff ff79 bl 801598c <_Balloc> 8015a9a: 4680 mov r8, r0 8015a9c: b928 cbnz r0, 8015aaa <__multadd+0x5a> 8015a9e: 4602 mov r2, r0 8015aa0: 21ba movs r1, #186 @ 0xba 8015aa2: 4b0c ldr r3, [pc, #48] @ (8015ad4 <__multadd+0x84>) 8015aa4: 480c ldr r0, [pc, #48] @ (8015ad8 <__multadd+0x88>) 8015aa6: f7fe fd01 bl 80144ac <__assert_func> 8015aaa: 6922 ldr r2, [r4, #16] 8015aac: f104 010c add.w r1, r4, #12 8015ab0: 3202 adds r2, #2 8015ab2: 0092 lsls r2, r2, #2 8015ab4: 300c adds r0, #12 8015ab6: f7fe fceb bl 8014490 8015aba: 4621 mov r1, r4 8015abc: 4638 mov r0, r7 8015abe: f7ff ffa5 bl 8015a0c <_Bfree> 8015ac2: 4644 mov r4, r8 8015ac4: eb04 0385 add.w r3, r4, r5, lsl #2 8015ac8: 3501 adds r5, #1 8015aca: 615e str r6, [r3, #20] 8015acc: 6125 str r5, [r4, #16] 8015ace: 4620 mov r0, r4 8015ad0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8015ad4: 08016fc8 .word 0x08016fc8 8015ad8: 08016fea .word 0x08016fea 08015adc <__hi0bits>: 8015adc: 4603 mov r3, r0 8015ade: f5b0 3f80 cmp.w r0, #65536 @ 0x10000 8015ae2: bf3a itte cc 8015ae4: 0403 lslcc r3, r0, #16 8015ae6: 2010 movcc r0, #16 8015ae8: 2000 movcs r0, #0 8015aea: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8015aee: bf3c itt cc 8015af0: 021b lslcc r3, r3, #8 8015af2: 3008 addcc r0, #8 8015af4: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8015af8: bf3c itt cc 8015afa: 011b lslcc r3, r3, #4 8015afc: 3004 addcc r0, #4 8015afe: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8015b02: bf3c itt cc 8015b04: 009b lslcc r3, r3, #2 8015b06: 3002 addcc r0, #2 8015b08: 2b00 cmp r3, #0 8015b0a: db05 blt.n 8015b18 <__hi0bits+0x3c> 8015b0c: f013 4f80 tst.w r3, #1073741824 @ 0x40000000 8015b10: f100 0001 add.w r0, r0, #1 8015b14: bf08 it eq 8015b16: 2020 moveq r0, #32 8015b18: 4770 bx lr 08015b1a <__lo0bits>: 8015b1a: 6803 ldr r3, [r0, #0] 8015b1c: 4602 mov r2, r0 8015b1e: f013 0007 ands.w r0, r3, #7 8015b22: d00b beq.n 8015b3c <__lo0bits+0x22> 8015b24: 07d9 lsls r1, r3, #31 8015b26: d421 bmi.n 8015b6c <__lo0bits+0x52> 8015b28: 0798 lsls r0, r3, #30 8015b2a: bf49 itett mi 8015b2c: 085b lsrmi r3, r3, #1 8015b2e: 089b lsrpl r3, r3, #2 8015b30: 2001 movmi r0, #1 8015b32: 6013 strmi r3, [r2, #0] 8015b34: bf5c itt pl 8015b36: 2002 movpl r0, #2 8015b38: 6013 strpl r3, [r2, #0] 8015b3a: 4770 bx lr 8015b3c: b299 uxth r1, r3 8015b3e: b909 cbnz r1, 8015b44 <__lo0bits+0x2a> 8015b40: 2010 movs r0, #16 8015b42: 0c1b lsrs r3, r3, #16 8015b44: b2d9 uxtb r1, r3 8015b46: b909 cbnz r1, 8015b4c <__lo0bits+0x32> 8015b48: 3008 adds r0, #8 8015b4a: 0a1b lsrs r3, r3, #8 8015b4c: 0719 lsls r1, r3, #28 8015b4e: bf04 itt eq 8015b50: 091b lsreq r3, r3, #4 8015b52: 3004 addeq r0, #4 8015b54: 0799 lsls r1, r3, #30 8015b56: bf04 itt eq 8015b58: 089b lsreq r3, r3, #2 8015b5a: 3002 addeq r0, #2 8015b5c: 07d9 lsls r1, r3, #31 8015b5e: d403 bmi.n 8015b68 <__lo0bits+0x4e> 8015b60: 085b lsrs r3, r3, #1 8015b62: f100 0001 add.w r0, r0, #1 8015b66: d003 beq.n 8015b70 <__lo0bits+0x56> 8015b68: 6013 str r3, [r2, #0] 8015b6a: 4770 bx lr 8015b6c: 2000 movs r0, #0 8015b6e: 4770 bx lr 8015b70: 2020 movs r0, #32 8015b72: 4770 bx lr 08015b74 <__i2b>: 8015b74: b510 push {r4, lr} 8015b76: 460c mov r4, r1 8015b78: 2101 movs r1, #1 8015b7a: f7ff ff07 bl 801598c <_Balloc> 8015b7e: 4602 mov r2, r0 8015b80: b928 cbnz r0, 8015b8e <__i2b+0x1a> 8015b82: f240 1145 movw r1, #325 @ 0x145 8015b86: 4b04 ldr r3, [pc, #16] @ (8015b98 <__i2b+0x24>) 8015b88: 4804 ldr r0, [pc, #16] @ (8015b9c <__i2b+0x28>) 8015b8a: f7fe fc8f bl 80144ac <__assert_func> 8015b8e: 2301 movs r3, #1 8015b90: 6144 str r4, [r0, #20] 8015b92: 6103 str r3, [r0, #16] 8015b94: bd10 pop {r4, pc} 8015b96: bf00 nop 8015b98: 08016fc8 .word 0x08016fc8 8015b9c: 08016fea .word 0x08016fea 08015ba0 <__multiply>: 8015ba0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8015ba4: 4617 mov r7, r2 8015ba6: 690a ldr r2, [r1, #16] 8015ba8: 693b ldr r3, [r7, #16] 8015baa: 4689 mov r9, r1 8015bac: 429a cmp r2, r3 8015bae: bfa2 ittt ge 8015bb0: 463b movge r3, r7 8015bb2: 460f movge r7, r1 8015bb4: 4699 movge r9, r3 8015bb6: 693d ldr r5, [r7, #16] 8015bb8: f8d9 a010 ldr.w sl, [r9, #16] 8015bbc: 68bb ldr r3, [r7, #8] 8015bbe: 6879 ldr r1, [r7, #4] 8015bc0: eb05 060a add.w r6, r5, sl 8015bc4: 42b3 cmp r3, r6 8015bc6: b085 sub sp, #20 8015bc8: bfb8 it lt 8015bca: 3101 addlt r1, #1 8015bcc: f7ff fede bl 801598c <_Balloc> 8015bd0: b930 cbnz r0, 8015be0 <__multiply+0x40> 8015bd2: 4602 mov r2, r0 8015bd4: f44f 71b1 mov.w r1, #354 @ 0x162 8015bd8: 4b40 ldr r3, [pc, #256] @ (8015cdc <__multiply+0x13c>) 8015bda: 4841 ldr r0, [pc, #260] @ (8015ce0 <__multiply+0x140>) 8015bdc: f7fe fc66 bl 80144ac <__assert_func> 8015be0: f100 0414 add.w r4, r0, #20 8015be4: 4623 mov r3, r4 8015be6: 2200 movs r2, #0 8015be8: eb04 0e86 add.w lr, r4, r6, lsl #2 8015bec: 4573 cmp r3, lr 8015bee: d320 bcc.n 8015c32 <__multiply+0x92> 8015bf0: f107 0814 add.w r8, r7, #20 8015bf4: f109 0114 add.w r1, r9, #20 8015bf8: eb08 0585 add.w r5, r8, r5, lsl #2 8015bfc: eb01 038a add.w r3, r1, sl, lsl #2 8015c00: 9302 str r3, [sp, #8] 8015c02: 1beb subs r3, r5, r7 8015c04: 3b15 subs r3, #21 8015c06: f023 0303 bic.w r3, r3, #3 8015c0a: 3304 adds r3, #4 8015c0c: 3715 adds r7, #21 8015c0e: 42bd cmp r5, r7 8015c10: bf38 it cc 8015c12: 2304 movcc r3, #4 8015c14: 9301 str r3, [sp, #4] 8015c16: 9b02 ldr r3, [sp, #8] 8015c18: 9103 str r1, [sp, #12] 8015c1a: 428b cmp r3, r1 8015c1c: d80c bhi.n 8015c38 <__multiply+0x98> 8015c1e: 2e00 cmp r6, #0 8015c20: dd03 ble.n 8015c2a <__multiply+0x8a> 8015c22: f85e 3d04 ldr.w r3, [lr, #-4]! 8015c26: 2b00 cmp r3, #0 8015c28: d055 beq.n 8015cd6 <__multiply+0x136> 8015c2a: 6106 str r6, [r0, #16] 8015c2c: b005 add sp, #20 8015c2e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8015c32: f843 2b04 str.w r2, [r3], #4 8015c36: e7d9 b.n 8015bec <__multiply+0x4c> 8015c38: f8b1 a000 ldrh.w sl, [r1] 8015c3c: f1ba 0f00 cmp.w sl, #0 8015c40: d01f beq.n 8015c82 <__multiply+0xe2> 8015c42: 46c4 mov ip, r8 8015c44: 46a1 mov r9, r4 8015c46: 2700 movs r7, #0 8015c48: f85c 2b04 ldr.w r2, [ip], #4 8015c4c: f8d9 3000 ldr.w r3, [r9] 8015c50: fa1f fb82 uxth.w fp, r2 8015c54: b29b uxth r3, r3 8015c56: fb0a 330b mla r3, sl, fp, r3 8015c5a: 443b add r3, r7 8015c5c: f8d9 7000 ldr.w r7, [r9] 8015c60: 0c12 lsrs r2, r2, #16 8015c62: 0c3f lsrs r7, r7, #16 8015c64: fb0a 7202 mla r2, sl, r2, r7 8015c68: eb02 4213 add.w r2, r2, r3, lsr #16 8015c6c: b29b uxth r3, r3 8015c6e: ea43 4302 orr.w r3, r3, r2, lsl #16 8015c72: 4565 cmp r5, ip 8015c74: ea4f 4712 mov.w r7, r2, lsr #16 8015c78: f849 3b04 str.w r3, [r9], #4 8015c7c: d8e4 bhi.n 8015c48 <__multiply+0xa8> 8015c7e: 9b01 ldr r3, [sp, #4] 8015c80: 50e7 str r7, [r4, r3] 8015c82: 9b03 ldr r3, [sp, #12] 8015c84: 3104 adds r1, #4 8015c86: f8b3 9002 ldrh.w r9, [r3, #2] 8015c8a: f1b9 0f00 cmp.w r9, #0 8015c8e: d020 beq.n 8015cd2 <__multiply+0x132> 8015c90: 4647 mov r7, r8 8015c92: 46a4 mov ip, r4 8015c94: f04f 0a00 mov.w sl, #0 8015c98: 6823 ldr r3, [r4, #0] 8015c9a: f8b7 b000 ldrh.w fp, [r7] 8015c9e: f8bc 2002 ldrh.w r2, [ip, #2] 8015ca2: b29b uxth r3, r3 8015ca4: fb09 220b mla r2, r9, fp, r2 8015ca8: 4452 add r2, sl 8015caa: ea43 4302 orr.w r3, r3, r2, lsl #16 8015cae: f84c 3b04 str.w r3, [ip], #4 8015cb2: f857 3b04 ldr.w r3, [r7], #4 8015cb6: ea4f 4a13 mov.w sl, r3, lsr #16 8015cba: f8bc 3000 ldrh.w r3, [ip] 8015cbe: 42bd cmp r5, r7 8015cc0: fb09 330a mla r3, r9, sl, r3 8015cc4: eb03 4312 add.w r3, r3, r2, lsr #16 8015cc8: ea4f 4a13 mov.w sl, r3, lsr #16 8015ccc: d8e5 bhi.n 8015c9a <__multiply+0xfa> 8015cce: 9a01 ldr r2, [sp, #4] 8015cd0: 50a3 str r3, [r4, r2] 8015cd2: 3404 adds r4, #4 8015cd4: e79f b.n 8015c16 <__multiply+0x76> 8015cd6: 3e01 subs r6, #1 8015cd8: e7a1 b.n 8015c1e <__multiply+0x7e> 8015cda: bf00 nop 8015cdc: 08016fc8 .word 0x08016fc8 8015ce0: 08016fea .word 0x08016fea 08015ce4 <__pow5mult>: 8015ce4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8015ce8: 4615 mov r5, r2 8015cea: f012 0203 ands.w r2, r2, #3 8015cee: 4607 mov r7, r0 8015cf0: 460e mov r6, r1 8015cf2: d007 beq.n 8015d04 <__pow5mult+0x20> 8015cf4: 4c25 ldr r4, [pc, #148] @ (8015d8c <__pow5mult+0xa8>) 8015cf6: 3a01 subs r2, #1 8015cf8: 2300 movs r3, #0 8015cfa: f854 2022 ldr.w r2, [r4, r2, lsl #2] 8015cfe: f7ff fea7 bl 8015a50 <__multadd> 8015d02: 4606 mov r6, r0 8015d04: 10ad asrs r5, r5, #2 8015d06: d03d beq.n 8015d84 <__pow5mult+0xa0> 8015d08: 69fc ldr r4, [r7, #28] 8015d0a: b97c cbnz r4, 8015d2c <__pow5mult+0x48> 8015d0c: 2010 movs r0, #16 8015d0e: f7ff fcdf bl 80156d0 8015d12: 4602 mov r2, r0 8015d14: 61f8 str r0, [r7, #28] 8015d16: b928 cbnz r0, 8015d24 <__pow5mult+0x40> 8015d18: f240 11b3 movw r1, #435 @ 0x1b3 8015d1c: 4b1c ldr r3, [pc, #112] @ (8015d90 <__pow5mult+0xac>) 8015d1e: 481d ldr r0, [pc, #116] @ (8015d94 <__pow5mult+0xb0>) 8015d20: f7fe fbc4 bl 80144ac <__assert_func> 8015d24: e9c0 4401 strd r4, r4, [r0, #4] 8015d28: 6004 str r4, [r0, #0] 8015d2a: 60c4 str r4, [r0, #12] 8015d2c: f8d7 801c ldr.w r8, [r7, #28] 8015d30: f8d8 4008 ldr.w r4, [r8, #8] 8015d34: b94c cbnz r4, 8015d4a <__pow5mult+0x66> 8015d36: f240 2171 movw r1, #625 @ 0x271 8015d3a: 4638 mov r0, r7 8015d3c: f7ff ff1a bl 8015b74 <__i2b> 8015d40: 2300 movs r3, #0 8015d42: 4604 mov r4, r0 8015d44: f8c8 0008 str.w r0, [r8, #8] 8015d48: 6003 str r3, [r0, #0] 8015d4a: f04f 0900 mov.w r9, #0 8015d4e: 07eb lsls r3, r5, #31 8015d50: d50a bpl.n 8015d68 <__pow5mult+0x84> 8015d52: 4631 mov r1, r6 8015d54: 4622 mov r2, r4 8015d56: 4638 mov r0, r7 8015d58: f7ff ff22 bl 8015ba0 <__multiply> 8015d5c: 4680 mov r8, r0 8015d5e: 4631 mov r1, r6 8015d60: 4638 mov r0, r7 8015d62: f7ff fe53 bl 8015a0c <_Bfree> 8015d66: 4646 mov r6, r8 8015d68: 106d asrs r5, r5, #1 8015d6a: d00b beq.n 8015d84 <__pow5mult+0xa0> 8015d6c: 6820 ldr r0, [r4, #0] 8015d6e: b938 cbnz r0, 8015d80 <__pow5mult+0x9c> 8015d70: 4622 mov r2, r4 8015d72: 4621 mov r1, r4 8015d74: 4638 mov r0, r7 8015d76: f7ff ff13 bl 8015ba0 <__multiply> 8015d7a: 6020 str r0, [r4, #0] 8015d7c: f8c0 9000 str.w r9, [r0] 8015d80: 4604 mov r4, r0 8015d82: e7e4 b.n 8015d4e <__pow5mult+0x6a> 8015d84: 4630 mov r0, r6 8015d86: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8015d8a: bf00 nop 8015d8c: 08017050 .word 0x08017050 8015d90: 08016f59 .word 0x08016f59 8015d94: 08016fea .word 0x08016fea 08015d98 <__lshift>: 8015d98: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8015d9c: 460c mov r4, r1 8015d9e: 4607 mov r7, r0 8015da0: 4691 mov r9, r2 8015da2: 6923 ldr r3, [r4, #16] 8015da4: 6849 ldr r1, [r1, #4] 8015da6: eb03 1862 add.w r8, r3, r2, asr #5 8015daa: 68a3 ldr r3, [r4, #8] 8015dac: ea4f 1a62 mov.w sl, r2, asr #5 8015db0: f108 0601 add.w r6, r8, #1 8015db4: 42b3 cmp r3, r6 8015db6: db0b blt.n 8015dd0 <__lshift+0x38> 8015db8: 4638 mov r0, r7 8015dba: f7ff fde7 bl 801598c <_Balloc> 8015dbe: 4605 mov r5, r0 8015dc0: b948 cbnz r0, 8015dd6 <__lshift+0x3e> 8015dc2: 4602 mov r2, r0 8015dc4: f44f 71ef mov.w r1, #478 @ 0x1de 8015dc8: 4b27 ldr r3, [pc, #156] @ (8015e68 <__lshift+0xd0>) 8015dca: 4828 ldr r0, [pc, #160] @ (8015e6c <__lshift+0xd4>) 8015dcc: f7fe fb6e bl 80144ac <__assert_func> 8015dd0: 3101 adds r1, #1 8015dd2: 005b lsls r3, r3, #1 8015dd4: e7ee b.n 8015db4 <__lshift+0x1c> 8015dd6: 2300 movs r3, #0 8015dd8: f100 0114 add.w r1, r0, #20 8015ddc: f100 0210 add.w r2, r0, #16 8015de0: 4618 mov r0, r3 8015de2: 4553 cmp r3, sl 8015de4: db33 blt.n 8015e4e <__lshift+0xb6> 8015de6: 6920 ldr r0, [r4, #16] 8015de8: ea2a 7aea bic.w sl, sl, sl, asr #31 8015dec: f104 0314 add.w r3, r4, #20 8015df0: f019 091f ands.w r9, r9, #31 8015df4: eb01 018a add.w r1, r1, sl, lsl #2 8015df8: eb03 0c80 add.w ip, r3, r0, lsl #2 8015dfc: d02b beq.n 8015e56 <__lshift+0xbe> 8015dfe: 468a mov sl, r1 8015e00: 2200 movs r2, #0 8015e02: f1c9 0e20 rsb lr, r9, #32 8015e06: 6818 ldr r0, [r3, #0] 8015e08: fa00 f009 lsl.w r0, r0, r9 8015e0c: 4310 orrs r0, r2 8015e0e: f84a 0b04 str.w r0, [sl], #4 8015e12: f853 2b04 ldr.w r2, [r3], #4 8015e16: 459c cmp ip, r3 8015e18: fa22 f20e lsr.w r2, r2, lr 8015e1c: d8f3 bhi.n 8015e06 <__lshift+0x6e> 8015e1e: ebac 0304 sub.w r3, ip, r4 8015e22: 3b15 subs r3, #21 8015e24: f023 0303 bic.w r3, r3, #3 8015e28: 3304 adds r3, #4 8015e2a: f104 0015 add.w r0, r4, #21 8015e2e: 4560 cmp r0, ip 8015e30: bf88 it hi 8015e32: 2304 movhi r3, #4 8015e34: 50ca str r2, [r1, r3] 8015e36: b10a cbz r2, 8015e3c <__lshift+0xa4> 8015e38: f108 0602 add.w r6, r8, #2 8015e3c: 3e01 subs r6, #1 8015e3e: 4638 mov r0, r7 8015e40: 4621 mov r1, r4 8015e42: 612e str r6, [r5, #16] 8015e44: f7ff fde2 bl 8015a0c <_Bfree> 8015e48: 4628 mov r0, r5 8015e4a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8015e4e: f842 0f04 str.w r0, [r2, #4]! 8015e52: 3301 adds r3, #1 8015e54: e7c5 b.n 8015de2 <__lshift+0x4a> 8015e56: 3904 subs r1, #4 8015e58: f853 2b04 ldr.w r2, [r3], #4 8015e5c: 459c cmp ip, r3 8015e5e: f841 2f04 str.w r2, [r1, #4]! 8015e62: d8f9 bhi.n 8015e58 <__lshift+0xc0> 8015e64: e7ea b.n 8015e3c <__lshift+0xa4> 8015e66: bf00 nop 8015e68: 08016fc8 .word 0x08016fc8 8015e6c: 08016fea .word 0x08016fea 08015e70 <__mcmp>: 8015e70: 4603 mov r3, r0 8015e72: 690a ldr r2, [r1, #16] 8015e74: 6900 ldr r0, [r0, #16] 8015e76: b530 push {r4, r5, lr} 8015e78: 1a80 subs r0, r0, r2 8015e7a: d10e bne.n 8015e9a <__mcmp+0x2a> 8015e7c: 3314 adds r3, #20 8015e7e: 3114 adds r1, #20 8015e80: eb03 0482 add.w r4, r3, r2, lsl #2 8015e84: eb01 0182 add.w r1, r1, r2, lsl #2 8015e88: f854 5d04 ldr.w r5, [r4, #-4]! 8015e8c: f851 2d04 ldr.w r2, [r1, #-4]! 8015e90: 4295 cmp r5, r2 8015e92: d003 beq.n 8015e9c <__mcmp+0x2c> 8015e94: d205 bcs.n 8015ea2 <__mcmp+0x32> 8015e96: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015e9a: bd30 pop {r4, r5, pc} 8015e9c: 42a3 cmp r3, r4 8015e9e: d3f3 bcc.n 8015e88 <__mcmp+0x18> 8015ea0: e7fb b.n 8015e9a <__mcmp+0x2a> 8015ea2: 2001 movs r0, #1 8015ea4: e7f9 b.n 8015e9a <__mcmp+0x2a> ... 08015ea8 <__mdiff>: 8015ea8: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8015eac: 4689 mov r9, r1 8015eae: 4606 mov r6, r0 8015eb0: 4611 mov r1, r2 8015eb2: 4648 mov r0, r9 8015eb4: 4614 mov r4, r2 8015eb6: f7ff ffdb bl 8015e70 <__mcmp> 8015eba: 1e05 subs r5, r0, #0 8015ebc: d112 bne.n 8015ee4 <__mdiff+0x3c> 8015ebe: 4629 mov r1, r5 8015ec0: 4630 mov r0, r6 8015ec2: f7ff fd63 bl 801598c <_Balloc> 8015ec6: 4602 mov r2, r0 8015ec8: b928 cbnz r0, 8015ed6 <__mdiff+0x2e> 8015eca: f240 2137 movw r1, #567 @ 0x237 8015ece: 4b3e ldr r3, [pc, #248] @ (8015fc8 <__mdiff+0x120>) 8015ed0: 483e ldr r0, [pc, #248] @ (8015fcc <__mdiff+0x124>) 8015ed2: f7fe faeb bl 80144ac <__assert_func> 8015ed6: 2301 movs r3, #1 8015ed8: e9c0 3504 strd r3, r5, [r0, #16] 8015edc: 4610 mov r0, r2 8015ede: b003 add sp, #12 8015ee0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8015ee4: bfbc itt lt 8015ee6: 464b movlt r3, r9 8015ee8: 46a1 movlt r9, r4 8015eea: 4630 mov r0, r6 8015eec: f8d9 1004 ldr.w r1, [r9, #4] 8015ef0: bfba itte lt 8015ef2: 461c movlt r4, r3 8015ef4: 2501 movlt r5, #1 8015ef6: 2500 movge r5, #0 8015ef8: f7ff fd48 bl 801598c <_Balloc> 8015efc: 4602 mov r2, r0 8015efe: b918 cbnz r0, 8015f08 <__mdiff+0x60> 8015f00: f240 2145 movw r1, #581 @ 0x245 8015f04: 4b30 ldr r3, [pc, #192] @ (8015fc8 <__mdiff+0x120>) 8015f06: e7e3 b.n 8015ed0 <__mdiff+0x28> 8015f08: f100 0b14 add.w fp, r0, #20 8015f0c: f8d9 7010 ldr.w r7, [r9, #16] 8015f10: f109 0310 add.w r3, r9, #16 8015f14: 60c5 str r5, [r0, #12] 8015f16: f04f 0c00 mov.w ip, #0 8015f1a: f109 0514 add.w r5, r9, #20 8015f1e: 46d9 mov r9, fp 8015f20: 6926 ldr r6, [r4, #16] 8015f22: f104 0e14 add.w lr, r4, #20 8015f26: eb05 0887 add.w r8, r5, r7, lsl #2 8015f2a: eb0e 0686 add.w r6, lr, r6, lsl #2 8015f2e: 9301 str r3, [sp, #4] 8015f30: 9b01 ldr r3, [sp, #4] 8015f32: f85e 0b04 ldr.w r0, [lr], #4 8015f36: f853 af04 ldr.w sl, [r3, #4]! 8015f3a: b281 uxth r1, r0 8015f3c: 9301 str r3, [sp, #4] 8015f3e: fa1f f38a uxth.w r3, sl 8015f42: 1a5b subs r3, r3, r1 8015f44: 0c00 lsrs r0, r0, #16 8015f46: 4463 add r3, ip 8015f48: ebc0 401a rsb r0, r0, sl, lsr #16 8015f4c: eb00 4023 add.w r0, r0, r3, asr #16 8015f50: b29b uxth r3, r3 8015f52: ea43 4300 orr.w r3, r3, r0, lsl #16 8015f56: 4576 cmp r6, lr 8015f58: ea4f 4c20 mov.w ip, r0, asr #16 8015f5c: f849 3b04 str.w r3, [r9], #4 8015f60: d8e6 bhi.n 8015f30 <__mdiff+0x88> 8015f62: 1b33 subs r3, r6, r4 8015f64: 3b15 subs r3, #21 8015f66: f023 0303 bic.w r3, r3, #3 8015f6a: 3415 adds r4, #21 8015f6c: 3304 adds r3, #4 8015f6e: 42a6 cmp r6, r4 8015f70: bf38 it cc 8015f72: 2304 movcc r3, #4 8015f74: 441d add r5, r3 8015f76: 445b add r3, fp 8015f78: 461e mov r6, r3 8015f7a: 462c mov r4, r5 8015f7c: 4544 cmp r4, r8 8015f7e: d30e bcc.n 8015f9e <__mdiff+0xf6> 8015f80: f108 0103 add.w r1, r8, #3 8015f84: 1b49 subs r1, r1, r5 8015f86: f021 0103 bic.w r1, r1, #3 8015f8a: 3d03 subs r5, #3 8015f8c: 45a8 cmp r8, r5 8015f8e: bf38 it cc 8015f90: 2100 movcc r1, #0 8015f92: 440b add r3, r1 8015f94: f853 1d04 ldr.w r1, [r3, #-4]! 8015f98: b199 cbz r1, 8015fc2 <__mdiff+0x11a> 8015f9a: 6117 str r7, [r2, #16] 8015f9c: e79e b.n 8015edc <__mdiff+0x34> 8015f9e: 46e6 mov lr, ip 8015fa0: f854 1b04 ldr.w r1, [r4], #4 8015fa4: fa1f fc81 uxth.w ip, r1 8015fa8: 44f4 add ip, lr 8015faa: 0c08 lsrs r0, r1, #16 8015fac: 4471 add r1, lr 8015fae: eb00 402c add.w r0, r0, ip, asr #16 8015fb2: b289 uxth r1, r1 8015fb4: ea41 4100 orr.w r1, r1, r0, lsl #16 8015fb8: ea4f 4c20 mov.w ip, r0, asr #16 8015fbc: f846 1b04 str.w r1, [r6], #4 8015fc0: e7dc b.n 8015f7c <__mdiff+0xd4> 8015fc2: 3f01 subs r7, #1 8015fc4: e7e6 b.n 8015f94 <__mdiff+0xec> 8015fc6: bf00 nop 8015fc8: 08016fc8 .word 0x08016fc8 8015fcc: 08016fea .word 0x08016fea 08015fd0 <__d2b>: 8015fd0: e92d 4373 stmdb sp!, {r0, r1, r4, r5, r6, r8, r9, lr} 8015fd4: 2101 movs r1, #1 8015fd6: 4690 mov r8, r2 8015fd8: 4699 mov r9, r3 8015fda: 9e08 ldr r6, [sp, #32] 8015fdc: f7ff fcd6 bl 801598c <_Balloc> 8015fe0: 4604 mov r4, r0 8015fe2: b930 cbnz r0, 8015ff2 <__d2b+0x22> 8015fe4: 4602 mov r2, r0 8015fe6: f240 310f movw r1, #783 @ 0x30f 8015fea: 4b23 ldr r3, [pc, #140] @ (8016078 <__d2b+0xa8>) 8015fec: 4823 ldr r0, [pc, #140] @ (801607c <__d2b+0xac>) 8015fee: f7fe fa5d bl 80144ac <__assert_func> 8015ff2: f3c9 550a ubfx r5, r9, #20, #11 8015ff6: f3c9 0313 ubfx r3, r9, #0, #20 8015ffa: b10d cbz r5, 8016000 <__d2b+0x30> 8015ffc: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8016000: 9301 str r3, [sp, #4] 8016002: f1b8 0300 subs.w r3, r8, #0 8016006: d024 beq.n 8016052 <__d2b+0x82> 8016008: 4668 mov r0, sp 801600a: 9300 str r3, [sp, #0] 801600c: f7ff fd85 bl 8015b1a <__lo0bits> 8016010: e9dd 1200 ldrd r1, r2, [sp] 8016014: b1d8 cbz r0, 801604e <__d2b+0x7e> 8016016: f1c0 0320 rsb r3, r0, #32 801601a: fa02 f303 lsl.w r3, r2, r3 801601e: 430b orrs r3, r1 8016020: 40c2 lsrs r2, r0 8016022: 6163 str r3, [r4, #20] 8016024: 9201 str r2, [sp, #4] 8016026: 9b01 ldr r3, [sp, #4] 8016028: 2b00 cmp r3, #0 801602a: bf0c ite eq 801602c: 2201 moveq r2, #1 801602e: 2202 movne r2, #2 8016030: 61a3 str r3, [r4, #24] 8016032: 6122 str r2, [r4, #16] 8016034: b1ad cbz r5, 8016062 <__d2b+0x92> 8016036: f2a5 4533 subw r5, r5, #1075 @ 0x433 801603a: 4405 add r5, r0 801603c: 6035 str r5, [r6, #0] 801603e: f1c0 0035 rsb r0, r0, #53 @ 0x35 8016042: 9b09 ldr r3, [sp, #36] @ 0x24 8016044: 6018 str r0, [r3, #0] 8016046: 4620 mov r0, r4 8016048: b002 add sp, #8 801604a: e8bd 8370 ldmia.w sp!, {r4, r5, r6, r8, r9, pc} 801604e: 6161 str r1, [r4, #20] 8016050: e7e9 b.n 8016026 <__d2b+0x56> 8016052: a801 add r0, sp, #4 8016054: f7ff fd61 bl 8015b1a <__lo0bits> 8016058: 9b01 ldr r3, [sp, #4] 801605a: 2201 movs r2, #1 801605c: 6163 str r3, [r4, #20] 801605e: 3020 adds r0, #32 8016060: e7e7 b.n 8016032 <__d2b+0x62> 8016062: f2a0 4032 subw r0, r0, #1074 @ 0x432 8016066: eb04 0382 add.w r3, r4, r2, lsl #2 801606a: 6030 str r0, [r6, #0] 801606c: 6918 ldr r0, [r3, #16] 801606e: f7ff fd35 bl 8015adc <__hi0bits> 8016072: ebc0 1042 rsb r0, r0, r2, lsl #5 8016076: e7e4 b.n 8016042 <__d2b+0x72> 8016078: 08016fc8 .word 0x08016fc8 801607c: 08016fea .word 0x08016fea 08016080 <__sread>: 8016080: b510 push {r4, lr} 8016082: 460c mov r4, r1 8016084: f9b1 100e ldrsh.w r1, [r1, #14] 8016088: f000 f9b0 bl 80163ec <_read_r> 801608c: 2800 cmp r0, #0 801608e: bfab itete ge 8016090: 6d63 ldrge r3, [r4, #84] @ 0x54 8016092: 89a3 ldrhlt r3, [r4, #12] 8016094: 181b addge r3, r3, r0 8016096: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 801609a: bfac ite ge 801609c: 6563 strge r3, [r4, #84] @ 0x54 801609e: 81a3 strhlt r3, [r4, #12] 80160a0: bd10 pop {r4, pc} 080160a2 <__swrite>: 80160a2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80160a6: 461f mov r7, r3 80160a8: 898b ldrh r3, [r1, #12] 80160aa: 4605 mov r5, r0 80160ac: 05db lsls r3, r3, #23 80160ae: 460c mov r4, r1 80160b0: 4616 mov r6, r2 80160b2: d505 bpl.n 80160c0 <__swrite+0x1e> 80160b4: 2302 movs r3, #2 80160b6: 2200 movs r2, #0 80160b8: f9b1 100e ldrsh.w r1, [r1, #14] 80160bc: f000 f984 bl 80163c8 <_lseek_r> 80160c0: 89a3 ldrh r3, [r4, #12] 80160c2: 4632 mov r2, r6 80160c4: f423 5380 bic.w r3, r3, #4096 @ 0x1000 80160c8: 81a3 strh r3, [r4, #12] 80160ca: 4628 mov r0, r5 80160cc: 463b mov r3, r7 80160ce: f9b4 100e ldrsh.w r1, [r4, #14] 80160d2: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 80160d6: f000 b9ab b.w 8016430 <_write_r> 080160da <__sseek>: 80160da: b510 push {r4, lr} 80160dc: 460c mov r4, r1 80160de: f9b1 100e ldrsh.w r1, [r1, #14] 80160e2: f000 f971 bl 80163c8 <_lseek_r> 80160e6: 1c43 adds r3, r0, #1 80160e8: 89a3 ldrh r3, [r4, #12] 80160ea: bf15 itete ne 80160ec: 6560 strne r0, [r4, #84] @ 0x54 80160ee: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 80160f2: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 80160f6: 81a3 strheq r3, [r4, #12] 80160f8: bf18 it ne 80160fa: 81a3 strhne r3, [r4, #12] 80160fc: bd10 pop {r4, pc} 080160fe <__sclose>: 80160fe: f9b1 100e ldrsh.w r1, [r1, #14] 8016102: f000 b9a7 b.w 8016454 <_close_r> ... 08016108 : 8016108: b40e push {r1, r2, r3} 801610a: b503 push {r0, r1, lr} 801610c: 4601 mov r1, r0 801610e: ab03 add r3, sp, #12 8016110: 4805 ldr r0, [pc, #20] @ (8016128 ) 8016112: f853 2b04 ldr.w r2, [r3], #4 8016116: 6800 ldr r0, [r0, #0] 8016118: 9301 str r3, [sp, #4] 801611a: f7ff f9c1 bl 80154a0 <_vfiprintf_r> 801611e: b002 add sp, #8 8016120: f85d eb04 ldr.w lr, [sp], #4 8016124: b003 add sp, #12 8016126: 4770 bx lr 8016128: 20000084 .word 0x20000084 0801612c <_realloc_r>: 801612c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8016130: 4607 mov r7, r0 8016132: 4614 mov r4, r2 8016134: 460d mov r5, r1 8016136: b921 cbnz r1, 8016142 <_realloc_r+0x16> 8016138: 4611 mov r1, r2 801613a: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 801613e: f7ff baf1 b.w 8015724 <_malloc_r> 8016142: b92a cbnz r2, 8016150 <_realloc_r+0x24> 8016144: f000 f9c4 bl 80164d0 <_free_r> 8016148: 4625 mov r5, r4 801614a: 4628 mov r0, r5 801614c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8016150: f000 fa18 bl 8016584 <_malloc_usable_size_r> 8016154: 4284 cmp r4, r0 8016156: 4606 mov r6, r0 8016158: d802 bhi.n 8016160 <_realloc_r+0x34> 801615a: ebb4 0f50 cmp.w r4, r0, lsr #1 801615e: d8f4 bhi.n 801614a <_realloc_r+0x1e> 8016160: 4621 mov r1, r4 8016162: 4638 mov r0, r7 8016164: f7ff fade bl 8015724 <_malloc_r> 8016168: 4680 mov r8, r0 801616a: b908 cbnz r0, 8016170 <_realloc_r+0x44> 801616c: 4645 mov r5, r8 801616e: e7ec b.n 801614a <_realloc_r+0x1e> 8016170: 42b4 cmp r4, r6 8016172: 4622 mov r2, r4 8016174: 4629 mov r1, r5 8016176: bf28 it cs 8016178: 4632 movcs r2, r6 801617a: f7fe f989 bl 8014490 801617e: 4629 mov r1, r5 8016180: 4638 mov r0, r7 8016182: f000 f9a5 bl 80164d0 <_free_r> 8016186: e7f1 b.n 801616c <_realloc_r+0x40> 08016188 <__swbuf_r>: 8016188: b5f8 push {r3, r4, r5, r6, r7, lr} 801618a: 460e mov r6, r1 801618c: 4614 mov r4, r2 801618e: 4605 mov r5, r0 8016190: b118 cbz r0, 801619a <__swbuf_r+0x12> 8016192: 6a03 ldr r3, [r0, #32] 8016194: b90b cbnz r3, 801619a <__swbuf_r+0x12> 8016196: f7fe f8af bl 80142f8 <__sinit> 801619a: 69a3 ldr r3, [r4, #24] 801619c: 60a3 str r3, [r4, #8] 801619e: 89a3 ldrh r3, [r4, #12] 80161a0: 071a lsls r2, r3, #28 80161a2: d501 bpl.n 80161a8 <__swbuf_r+0x20> 80161a4: 6923 ldr r3, [r4, #16] 80161a6: b943 cbnz r3, 80161ba <__swbuf_r+0x32> 80161a8: 4621 mov r1, r4 80161aa: 4628 mov r0, r5 80161ac: f000 f82a bl 8016204 <__swsetup_r> 80161b0: b118 cbz r0, 80161ba <__swbuf_r+0x32> 80161b2: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff 80161b6: 4638 mov r0, r7 80161b8: bdf8 pop {r3, r4, r5, r6, r7, pc} 80161ba: 6823 ldr r3, [r4, #0] 80161bc: 6922 ldr r2, [r4, #16] 80161be: b2f6 uxtb r6, r6 80161c0: 1a98 subs r0, r3, r2 80161c2: 6963 ldr r3, [r4, #20] 80161c4: 4637 mov r7, r6 80161c6: 4283 cmp r3, r0 80161c8: dc05 bgt.n 80161d6 <__swbuf_r+0x4e> 80161ca: 4621 mov r1, r4 80161cc: 4628 mov r0, r5 80161ce: f7ff fba9 bl 8015924 <_fflush_r> 80161d2: 2800 cmp r0, #0 80161d4: d1ed bne.n 80161b2 <__swbuf_r+0x2a> 80161d6: 68a3 ldr r3, [r4, #8] 80161d8: 3b01 subs r3, #1 80161da: 60a3 str r3, [r4, #8] 80161dc: 6823 ldr r3, [r4, #0] 80161de: 1c5a adds r2, r3, #1 80161e0: 6022 str r2, [r4, #0] 80161e2: 701e strb r6, [r3, #0] 80161e4: 6962 ldr r2, [r4, #20] 80161e6: 1c43 adds r3, r0, #1 80161e8: 429a cmp r2, r3 80161ea: d004 beq.n 80161f6 <__swbuf_r+0x6e> 80161ec: 89a3 ldrh r3, [r4, #12] 80161ee: 07db lsls r3, r3, #31 80161f0: d5e1 bpl.n 80161b6 <__swbuf_r+0x2e> 80161f2: 2e0a cmp r6, #10 80161f4: d1df bne.n 80161b6 <__swbuf_r+0x2e> 80161f6: 4621 mov r1, r4 80161f8: 4628 mov r0, r5 80161fa: f7ff fb93 bl 8015924 <_fflush_r> 80161fe: 2800 cmp r0, #0 8016200: d0d9 beq.n 80161b6 <__swbuf_r+0x2e> 8016202: e7d6 b.n 80161b2 <__swbuf_r+0x2a> 08016204 <__swsetup_r>: 8016204: b538 push {r3, r4, r5, lr} 8016206: 4b29 ldr r3, [pc, #164] @ (80162ac <__swsetup_r+0xa8>) 8016208: 4605 mov r5, r0 801620a: 6818 ldr r0, [r3, #0] 801620c: 460c mov r4, r1 801620e: b118 cbz r0, 8016218 <__swsetup_r+0x14> 8016210: 6a03 ldr r3, [r0, #32] 8016212: b90b cbnz r3, 8016218 <__swsetup_r+0x14> 8016214: f7fe f870 bl 80142f8 <__sinit> 8016218: f9b4 300c ldrsh.w r3, [r4, #12] 801621c: 0719 lsls r1, r3, #28 801621e: d422 bmi.n 8016266 <__swsetup_r+0x62> 8016220: 06da lsls r2, r3, #27 8016222: d407 bmi.n 8016234 <__swsetup_r+0x30> 8016224: 2209 movs r2, #9 8016226: 602a str r2, [r5, #0] 8016228: f043 0340 orr.w r3, r3, #64 @ 0x40 801622c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016230: 81a3 strh r3, [r4, #12] 8016232: e033 b.n 801629c <__swsetup_r+0x98> 8016234: 0758 lsls r0, r3, #29 8016236: d512 bpl.n 801625e <__swsetup_r+0x5a> 8016238: 6b61 ldr r1, [r4, #52] @ 0x34 801623a: b141 cbz r1, 801624e <__swsetup_r+0x4a> 801623c: f104 0344 add.w r3, r4, #68 @ 0x44 8016240: 4299 cmp r1, r3 8016242: d002 beq.n 801624a <__swsetup_r+0x46> 8016244: 4628 mov r0, r5 8016246: f000 f943 bl 80164d0 <_free_r> 801624a: 2300 movs r3, #0 801624c: 6363 str r3, [r4, #52] @ 0x34 801624e: 89a3 ldrh r3, [r4, #12] 8016250: f023 0324 bic.w r3, r3, #36 @ 0x24 8016254: 81a3 strh r3, [r4, #12] 8016256: 2300 movs r3, #0 8016258: 6063 str r3, [r4, #4] 801625a: 6923 ldr r3, [r4, #16] 801625c: 6023 str r3, [r4, #0] 801625e: 89a3 ldrh r3, [r4, #12] 8016260: f043 0308 orr.w r3, r3, #8 8016264: 81a3 strh r3, [r4, #12] 8016266: 6923 ldr r3, [r4, #16] 8016268: b94b cbnz r3, 801627e <__swsetup_r+0x7a> 801626a: 89a3 ldrh r3, [r4, #12] 801626c: f403 7320 and.w r3, r3, #640 @ 0x280 8016270: f5b3 7f00 cmp.w r3, #512 @ 0x200 8016274: d003 beq.n 801627e <__swsetup_r+0x7a> 8016276: 4621 mov r1, r4 8016278: 4628 mov r0, r5 801627a: f000 f83e bl 80162fa <__smakebuf_r> 801627e: f9b4 300c ldrsh.w r3, [r4, #12] 8016282: f013 0201 ands.w r2, r3, #1 8016286: d00a beq.n 801629e <__swsetup_r+0x9a> 8016288: 2200 movs r2, #0 801628a: 60a2 str r2, [r4, #8] 801628c: 6962 ldr r2, [r4, #20] 801628e: 4252 negs r2, r2 8016290: 61a2 str r2, [r4, #24] 8016292: 6922 ldr r2, [r4, #16] 8016294: b942 cbnz r2, 80162a8 <__swsetup_r+0xa4> 8016296: f013 0080 ands.w r0, r3, #128 @ 0x80 801629a: d1c5 bne.n 8016228 <__swsetup_r+0x24> 801629c: bd38 pop {r3, r4, r5, pc} 801629e: 0799 lsls r1, r3, #30 80162a0: bf58 it pl 80162a2: 6962 ldrpl r2, [r4, #20] 80162a4: 60a2 str r2, [r4, #8] 80162a6: e7f4 b.n 8016292 <__swsetup_r+0x8e> 80162a8: 2000 movs r0, #0 80162aa: e7f7 b.n 801629c <__swsetup_r+0x98> 80162ac: 20000084 .word 0x20000084 080162b0 <__swhatbuf_r>: 80162b0: b570 push {r4, r5, r6, lr} 80162b2: 460c mov r4, r1 80162b4: f9b1 100e ldrsh.w r1, [r1, #14] 80162b8: 4615 mov r5, r2 80162ba: 2900 cmp r1, #0 80162bc: 461e mov r6, r3 80162be: b096 sub sp, #88 @ 0x58 80162c0: da0c bge.n 80162dc <__swhatbuf_r+0x2c> 80162c2: 89a3 ldrh r3, [r4, #12] 80162c4: 2100 movs r1, #0 80162c6: f013 0f80 tst.w r3, #128 @ 0x80 80162ca: bf14 ite ne 80162cc: 2340 movne r3, #64 @ 0x40 80162ce: f44f 6380 moveq.w r3, #1024 @ 0x400 80162d2: 2000 movs r0, #0 80162d4: 6031 str r1, [r6, #0] 80162d6: 602b str r3, [r5, #0] 80162d8: b016 add sp, #88 @ 0x58 80162da: bd70 pop {r4, r5, r6, pc} 80162dc: 466a mov r2, sp 80162de: f000 f8c9 bl 8016474 <_fstat_r> 80162e2: 2800 cmp r0, #0 80162e4: dbed blt.n 80162c2 <__swhatbuf_r+0x12> 80162e6: 9901 ldr r1, [sp, #4] 80162e8: f401 4170 and.w r1, r1, #61440 @ 0xf000 80162ec: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 80162f0: 4259 negs r1, r3 80162f2: 4159 adcs r1, r3 80162f4: f44f 6380 mov.w r3, #1024 @ 0x400 80162f8: e7eb b.n 80162d2 <__swhatbuf_r+0x22> 080162fa <__smakebuf_r>: 80162fa: 898b ldrh r3, [r1, #12] 80162fc: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 80162fe: 079d lsls r5, r3, #30 8016300: 4606 mov r6, r0 8016302: 460c mov r4, r1 8016304: d507 bpl.n 8016316 <__smakebuf_r+0x1c> 8016306: f104 0347 add.w r3, r4, #71 @ 0x47 801630a: 6023 str r3, [r4, #0] 801630c: 6123 str r3, [r4, #16] 801630e: 2301 movs r3, #1 8016310: 6163 str r3, [r4, #20] 8016312: b003 add sp, #12 8016314: bdf0 pop {r4, r5, r6, r7, pc} 8016316: 466a mov r2, sp 8016318: ab01 add r3, sp, #4 801631a: f7ff ffc9 bl 80162b0 <__swhatbuf_r> 801631e: 9f00 ldr r7, [sp, #0] 8016320: 4605 mov r5, r0 8016322: 4639 mov r1, r7 8016324: 4630 mov r0, r6 8016326: f7ff f9fd bl 8015724 <_malloc_r> 801632a: b948 cbnz r0, 8016340 <__smakebuf_r+0x46> 801632c: f9b4 300c ldrsh.w r3, [r4, #12] 8016330: 059a lsls r2, r3, #22 8016332: d4ee bmi.n 8016312 <__smakebuf_r+0x18> 8016334: f023 0303 bic.w r3, r3, #3 8016338: f043 0302 orr.w r3, r3, #2 801633c: 81a3 strh r3, [r4, #12] 801633e: e7e2 b.n 8016306 <__smakebuf_r+0xc> 8016340: 89a3 ldrh r3, [r4, #12] 8016342: e9c4 0704 strd r0, r7, [r4, #16] 8016346: f043 0380 orr.w r3, r3, #128 @ 0x80 801634a: 81a3 strh r3, [r4, #12] 801634c: 9b01 ldr r3, [sp, #4] 801634e: 6020 str r0, [r4, #0] 8016350: b15b cbz r3, 801636a <__smakebuf_r+0x70> 8016352: 4630 mov r0, r6 8016354: f9b4 100e ldrsh.w r1, [r4, #14] 8016358: f000 f826 bl 80163a8 <_isatty_r> 801635c: b128 cbz r0, 801636a <__smakebuf_r+0x70> 801635e: 89a3 ldrh r3, [r4, #12] 8016360: f023 0303 bic.w r3, r3, #3 8016364: f043 0301 orr.w r3, r3, #1 8016368: 81a3 strh r3, [r4, #12] 801636a: 89a3 ldrh r3, [r4, #12] 801636c: 431d orrs r5, r3 801636e: 81a5 strh r5, [r4, #12] 8016370: e7cf b.n 8016312 <__smakebuf_r+0x18> 08016372 : 8016372: 4288 cmp r0, r1 8016374: b510 push {r4, lr} 8016376: eb01 0402 add.w r4, r1, r2 801637a: d902 bls.n 8016382 801637c: 4284 cmp r4, r0 801637e: 4623 mov r3, r4 8016380: d807 bhi.n 8016392 8016382: 1e43 subs r3, r0, #1 8016384: 42a1 cmp r1, r4 8016386: d008 beq.n 801639a 8016388: f811 2b01 ldrb.w r2, [r1], #1 801638c: f803 2f01 strb.w r2, [r3, #1]! 8016390: e7f8 b.n 8016384 8016392: 4601 mov r1, r0 8016394: 4402 add r2, r0 8016396: 428a cmp r2, r1 8016398: d100 bne.n 801639c 801639a: bd10 pop {r4, pc} 801639c: f813 4d01 ldrb.w r4, [r3, #-1]! 80163a0: f802 4d01 strb.w r4, [r2, #-1]! 80163a4: e7f7 b.n 8016396 ... 080163a8 <_isatty_r>: 80163a8: b538 push {r3, r4, r5, lr} 80163aa: 2300 movs r3, #0 80163ac: 4d05 ldr r5, [pc, #20] @ (80163c4 <_isatty_r+0x1c>) 80163ae: 4604 mov r4, r0 80163b0: 4608 mov r0, r1 80163b2: 602b str r3, [r5, #0] 80163b4: f7f6 ffa9 bl 800d30a <_isatty> 80163b8: 1c43 adds r3, r0, #1 80163ba: d102 bne.n 80163c2 <_isatty_r+0x1a> 80163bc: 682b ldr r3, [r5, #0] 80163be: b103 cbz r3, 80163c2 <_isatty_r+0x1a> 80163c0: 6023 str r3, [r4, #0] 80163c2: bd38 pop {r3, r4, r5, pc} 80163c4: 20001394 .word 0x20001394 080163c8 <_lseek_r>: 80163c8: b538 push {r3, r4, r5, lr} 80163ca: 4604 mov r4, r0 80163cc: 4608 mov r0, r1 80163ce: 4611 mov r1, r2 80163d0: 2200 movs r2, #0 80163d2: 4d05 ldr r5, [pc, #20] @ (80163e8 <_lseek_r+0x20>) 80163d4: 602a str r2, [r5, #0] 80163d6: 461a mov r2, r3 80163d8: f7f6 ffa1 bl 800d31e <_lseek> 80163dc: 1c43 adds r3, r0, #1 80163de: d102 bne.n 80163e6 <_lseek_r+0x1e> 80163e0: 682b ldr r3, [r5, #0] 80163e2: b103 cbz r3, 80163e6 <_lseek_r+0x1e> 80163e4: 6023 str r3, [r4, #0] 80163e6: bd38 pop {r3, r4, r5, pc} 80163e8: 20001394 .word 0x20001394 080163ec <_read_r>: 80163ec: b538 push {r3, r4, r5, lr} 80163ee: 4604 mov r4, r0 80163f0: 4608 mov r0, r1 80163f2: 4611 mov r1, r2 80163f4: 2200 movs r2, #0 80163f6: 4d05 ldr r5, [pc, #20] @ (801640c <_read_r+0x20>) 80163f8: 602a str r2, [r5, #0] 80163fa: 461a mov r2, r3 80163fc: f7f6 ff4e bl 800d29c <_read> 8016400: 1c43 adds r3, r0, #1 8016402: d102 bne.n 801640a <_read_r+0x1e> 8016404: 682b ldr r3, [r5, #0] 8016406: b103 cbz r3, 801640a <_read_r+0x1e> 8016408: 6023 str r3, [r4, #0] 801640a: bd38 pop {r3, r4, r5, pc} 801640c: 20001394 .word 0x20001394 08016410 <_sbrk_r>: 8016410: b538 push {r3, r4, r5, lr} 8016412: 2300 movs r3, #0 8016414: 4d05 ldr r5, [pc, #20] @ (801642c <_sbrk_r+0x1c>) 8016416: 4604 mov r4, r0 8016418: 4608 mov r0, r1 801641a: 602b str r3, [r5, #0] 801641c: f7f6 ff8c bl 800d338 <_sbrk> 8016420: 1c43 adds r3, r0, #1 8016422: d102 bne.n 801642a <_sbrk_r+0x1a> 8016424: 682b ldr r3, [r5, #0] 8016426: b103 cbz r3, 801642a <_sbrk_r+0x1a> 8016428: 6023 str r3, [r4, #0] 801642a: bd38 pop {r3, r4, r5, pc} 801642c: 20001394 .word 0x20001394 08016430 <_write_r>: 8016430: b538 push {r3, r4, r5, lr} 8016432: 4604 mov r4, r0 8016434: 4608 mov r0, r1 8016436: 4611 mov r1, r2 8016438: 2200 movs r2, #0 801643a: 4d05 ldr r5, [pc, #20] @ (8016450 <_write_r+0x20>) 801643c: 602a str r2, [r5, #0] 801643e: 461a mov r2, r3 8016440: f7f3 fefe bl 800a240 <_write> 8016444: 1c43 adds r3, r0, #1 8016446: d102 bne.n 801644e <_write_r+0x1e> 8016448: 682b ldr r3, [r5, #0] 801644a: b103 cbz r3, 801644e <_write_r+0x1e> 801644c: 6023 str r3, [r4, #0] 801644e: bd38 pop {r3, r4, r5, pc} 8016450: 20001394 .word 0x20001394 08016454 <_close_r>: 8016454: b538 push {r3, r4, r5, lr} 8016456: 2300 movs r3, #0 8016458: 4d05 ldr r5, [pc, #20] @ (8016470 <_close_r+0x1c>) 801645a: 4604 mov r4, r0 801645c: 4608 mov r0, r1 801645e: 602b str r3, [r5, #0] 8016460: f7f6 ff39 bl 800d2d6 <_close> 8016464: 1c43 adds r3, r0, #1 8016466: d102 bne.n 801646e <_close_r+0x1a> 8016468: 682b ldr r3, [r5, #0] 801646a: b103 cbz r3, 801646e <_close_r+0x1a> 801646c: 6023 str r3, [r4, #0] 801646e: bd38 pop {r3, r4, r5, pc} 8016470: 20001394 .word 0x20001394 08016474 <_fstat_r>: 8016474: b538 push {r3, r4, r5, lr} 8016476: 2300 movs r3, #0 8016478: 4d06 ldr r5, [pc, #24] @ (8016494 <_fstat_r+0x20>) 801647a: 4604 mov r4, r0 801647c: 4608 mov r0, r1 801647e: 4611 mov r1, r2 8016480: 602b str r3, [r5, #0] 8016482: f7f6 ff33 bl 800d2ec <_fstat> 8016486: 1c43 adds r3, r0, #1 8016488: d102 bne.n 8016490 <_fstat_r+0x1c> 801648a: 682b ldr r3, [r5, #0] 801648c: b103 cbz r3, 8016490 <_fstat_r+0x1c> 801648e: 6023 str r3, [r4, #0] 8016490: bd38 pop {r3, r4, r5, pc} 8016492: bf00 nop 8016494: 20001394 .word 0x20001394 08016498 : 8016498: 2006 movs r0, #6 801649a: b508 push {r3, lr} 801649c: f000 f8b0 bl 8016600 80164a0: 2001 movs r0, #1 80164a2: f7f6 fef0 bl 800d286 <_exit> 080164a6 <_calloc_r>: 80164a6: b570 push {r4, r5, r6, lr} 80164a8: fba1 5402 umull r5, r4, r1, r2 80164ac: b934 cbnz r4, 80164bc <_calloc_r+0x16> 80164ae: 4629 mov r1, r5 80164b0: f7ff f938 bl 8015724 <_malloc_r> 80164b4: 4606 mov r6, r0 80164b6: b928 cbnz r0, 80164c4 <_calloc_r+0x1e> 80164b8: 4630 mov r0, r6 80164ba: bd70 pop {r4, r5, r6, pc} 80164bc: 220c movs r2, #12 80164be: 2600 movs r6, #0 80164c0: 6002 str r2, [r0, #0] 80164c2: e7f9 b.n 80164b8 <_calloc_r+0x12> 80164c4: 462a mov r2, r5 80164c6: 4621 mov r1, r4 80164c8: f7fd ff9a bl 8014400 80164cc: e7f4 b.n 80164b8 <_calloc_r+0x12> ... 080164d0 <_free_r>: 80164d0: b538 push {r3, r4, r5, lr} 80164d2: 4605 mov r5, r0 80164d4: 2900 cmp r1, #0 80164d6: d040 beq.n 801655a <_free_r+0x8a> 80164d8: f851 3c04 ldr.w r3, [r1, #-4] 80164dc: 1f0c subs r4, r1, #4 80164de: 2b00 cmp r3, #0 80164e0: bfb8 it lt 80164e2: 18e4 addlt r4, r4, r3 80164e4: f7ff fa46 bl 8015974 <__malloc_lock> 80164e8: 4a1c ldr r2, [pc, #112] @ (801655c <_free_r+0x8c>) 80164ea: 6813 ldr r3, [r2, #0] 80164ec: b933 cbnz r3, 80164fc <_free_r+0x2c> 80164ee: 6063 str r3, [r4, #4] 80164f0: 6014 str r4, [r2, #0] 80164f2: 4628 mov r0, r5 80164f4: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 80164f8: f7ff ba42 b.w 8015980 <__malloc_unlock> 80164fc: 42a3 cmp r3, r4 80164fe: d908 bls.n 8016512 <_free_r+0x42> 8016500: 6820 ldr r0, [r4, #0] 8016502: 1821 adds r1, r4, r0 8016504: 428b cmp r3, r1 8016506: bf01 itttt eq 8016508: 6819 ldreq r1, [r3, #0] 801650a: 685b ldreq r3, [r3, #4] 801650c: 1809 addeq r1, r1, r0 801650e: 6021 streq r1, [r4, #0] 8016510: e7ed b.n 80164ee <_free_r+0x1e> 8016512: 461a mov r2, r3 8016514: 685b ldr r3, [r3, #4] 8016516: b10b cbz r3, 801651c <_free_r+0x4c> 8016518: 42a3 cmp r3, r4 801651a: d9fa bls.n 8016512 <_free_r+0x42> 801651c: 6811 ldr r1, [r2, #0] 801651e: 1850 adds r0, r2, r1 8016520: 42a0 cmp r0, r4 8016522: d10b bne.n 801653c <_free_r+0x6c> 8016524: 6820 ldr r0, [r4, #0] 8016526: 4401 add r1, r0 8016528: 1850 adds r0, r2, r1 801652a: 4283 cmp r3, r0 801652c: 6011 str r1, [r2, #0] 801652e: d1e0 bne.n 80164f2 <_free_r+0x22> 8016530: 6818 ldr r0, [r3, #0] 8016532: 685b ldr r3, [r3, #4] 8016534: 4408 add r0, r1 8016536: 6010 str r0, [r2, #0] 8016538: 6053 str r3, [r2, #4] 801653a: e7da b.n 80164f2 <_free_r+0x22> 801653c: d902 bls.n 8016544 <_free_r+0x74> 801653e: 230c movs r3, #12 8016540: 602b str r3, [r5, #0] 8016542: e7d6 b.n 80164f2 <_free_r+0x22> 8016544: 6820 ldr r0, [r4, #0] 8016546: 1821 adds r1, r4, r0 8016548: 428b cmp r3, r1 801654a: bf01 itttt eq 801654c: 6819 ldreq r1, [r3, #0] 801654e: 685b ldreq r3, [r3, #4] 8016550: 1809 addeq r1, r1, r0 8016552: 6021 streq r1, [r4, #0] 8016554: 6063 str r3, [r4, #4] 8016556: 6054 str r4, [r2, #4] 8016558: e7cb b.n 80164f2 <_free_r+0x22> 801655a: bd38 pop {r3, r4, r5, pc} 801655c: 20001390 .word 0x20001390 08016560 <__ascii_mbtowc>: 8016560: b082 sub sp, #8 8016562: b901 cbnz r1, 8016566 <__ascii_mbtowc+0x6> 8016564: a901 add r1, sp, #4 8016566: b142 cbz r2, 801657a <__ascii_mbtowc+0x1a> 8016568: b14b cbz r3, 801657e <__ascii_mbtowc+0x1e> 801656a: 7813 ldrb r3, [r2, #0] 801656c: 600b str r3, [r1, #0] 801656e: 7812 ldrb r2, [r2, #0] 8016570: 1e10 subs r0, r2, #0 8016572: bf18 it ne 8016574: 2001 movne r0, #1 8016576: b002 add sp, #8 8016578: 4770 bx lr 801657a: 4610 mov r0, r2 801657c: e7fb b.n 8016576 <__ascii_mbtowc+0x16> 801657e: f06f 0001 mvn.w r0, #1 8016582: e7f8 b.n 8016576 <__ascii_mbtowc+0x16> 08016584 <_malloc_usable_size_r>: 8016584: f851 3c04 ldr.w r3, [r1, #-4] 8016588: 1f18 subs r0, r3, #4 801658a: 2b00 cmp r3, #0 801658c: bfbc itt lt 801658e: 580b ldrlt r3, [r1, r0] 8016590: 18c0 addlt r0, r0, r3 8016592: 4770 bx lr 08016594 <__ascii_wctomb>: 8016594: 4603 mov r3, r0 8016596: 4608 mov r0, r1 8016598: b141 cbz r1, 80165ac <__ascii_wctomb+0x18> 801659a: 2aff cmp r2, #255 @ 0xff 801659c: d904 bls.n 80165a8 <__ascii_wctomb+0x14> 801659e: 228a movs r2, #138 @ 0x8a 80165a0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80165a4: 601a str r2, [r3, #0] 80165a6: 4770 bx lr 80165a8: 2001 movs r0, #1 80165aa: 700a strb r2, [r1, #0] 80165ac: 4770 bx lr 080165ae <_raise_r>: 80165ae: 291f cmp r1, #31 80165b0: b538 push {r3, r4, r5, lr} 80165b2: 4605 mov r5, r0 80165b4: 460c mov r4, r1 80165b6: d904 bls.n 80165c2 <_raise_r+0x14> 80165b8: 2316 movs r3, #22 80165ba: 6003 str r3, [r0, #0] 80165bc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80165c0: bd38 pop {r3, r4, r5, pc} 80165c2: 6bc2 ldr r2, [r0, #60] @ 0x3c 80165c4: b112 cbz r2, 80165cc <_raise_r+0x1e> 80165c6: f852 3021 ldr.w r3, [r2, r1, lsl #2] 80165ca: b94b cbnz r3, 80165e0 <_raise_r+0x32> 80165cc: 4628 mov r0, r5 80165ce: f000 f831 bl 8016634 <_getpid_r> 80165d2: 4622 mov r2, r4 80165d4: 4601 mov r1, r0 80165d6: 4628 mov r0, r5 80165d8: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 80165dc: f000 b818 b.w 8016610 <_kill_r> 80165e0: 2b01 cmp r3, #1 80165e2: d00a beq.n 80165fa <_raise_r+0x4c> 80165e4: 1c59 adds r1, r3, #1 80165e6: d103 bne.n 80165f0 <_raise_r+0x42> 80165e8: 2316 movs r3, #22 80165ea: 6003 str r3, [r0, #0] 80165ec: 2001 movs r0, #1 80165ee: e7e7 b.n 80165c0 <_raise_r+0x12> 80165f0: 2100 movs r1, #0 80165f2: 4620 mov r0, r4 80165f4: f842 1024 str.w r1, [r2, r4, lsl #2] 80165f8: 4798 blx r3 80165fa: 2000 movs r0, #0 80165fc: e7e0 b.n 80165c0 <_raise_r+0x12> ... 08016600 : 8016600: 4b02 ldr r3, [pc, #8] @ (801660c ) 8016602: 4601 mov r1, r0 8016604: 6818 ldr r0, [r3, #0] 8016606: f7ff bfd2 b.w 80165ae <_raise_r> 801660a: bf00 nop 801660c: 20000084 .word 0x20000084 08016610 <_kill_r>: 8016610: b538 push {r3, r4, r5, lr} 8016612: 2300 movs r3, #0 8016614: 4d06 ldr r5, [pc, #24] @ (8016630 <_kill_r+0x20>) 8016616: 4604 mov r4, r0 8016618: 4608 mov r0, r1 801661a: 4611 mov r1, r2 801661c: 602b str r3, [r5, #0] 801661e: f7f6 fe22 bl 800d266 <_kill> 8016622: 1c43 adds r3, r0, #1 8016624: d102 bne.n 801662c <_kill_r+0x1c> 8016626: 682b ldr r3, [r5, #0] 8016628: b103 cbz r3, 801662c <_kill_r+0x1c> 801662a: 6023 str r3, [r4, #0] 801662c: bd38 pop {r3, r4, r5, pc} 801662e: bf00 nop 8016630: 20001394 .word 0x20001394 08016634 <_getpid_r>: 8016634: f7f6 be10 b.w 800d258 <_getpid> 08016638 <_init>: 8016638: b5f8 push {r3, r4, r5, r6, r7, lr} 801663a: bf00 nop 801663c: bcf8 pop {r3, r4, r5, r6, r7} 801663e: bc08 pop {r3} 8016640: 469e mov lr, r3 8016642: 4770 bx lr 08016644 <_fini>: 8016644: b5f8 push {r3, r4, r5, r6, r7, lr} 8016646: bf00 nop 8016648: bcf8 pop {r3, r4, r5, r6, r7} 801664a: bc08 pop {r3} 801664c: 469e mov lr, r3 801664e: 4770 bx lr