CCSModuleSW30Web.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001e4 08008000 08008000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000be1c 080081e8 080081e8 000011e8 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 000004ac 08014004 08014004 0000d004 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 080144b0 080144b0 0000e0d4 2**0 CONTENTS 4 .ARM 00000008 080144b0 080144b0 0000d4b0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 080144b8 080144b8 0000e0d4 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 080144b8 080144b8 0000d4b8 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 080144bc 080144bc 0000d4bc 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 000000d4 20000000 080144c0 0000e000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000010f0 200000d8 08014594 0000e0d8 2**3 ALLOC 10 ._user_heap_stack 00000600 200011c8 08014594 0000e1c8 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 0000e0d4 2**0 CONTENTS, READONLY 12 .debug_info 0001bc8b 00000000 00000000 0000e0fd 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00005452 00000000 00000000 00029d88 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 000016c0 00000000 00000000 0002f1e0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00001178 00000000 00000000 000308a0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00026207 00000000 00000000 00031a18 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 000211d3 00000000 00000000 00057c1f 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000c973b 00000000 00000000 00078df2 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 0014252d 2**0 CONTENTS, READONLY 20 .debug_frame 00006588 00000000 00000000 00142570 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000063 00000000 00000000 00148af8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080081e8 <__do_global_dtors_aux>: 80081e8: b510 push {r4, lr} 80081ea: 4c05 ldr r4, [pc, #20] @ (8008200 <__do_global_dtors_aux+0x18>) 80081ec: 7823 ldrb r3, [r4, #0] 80081ee: b933 cbnz r3, 80081fe <__do_global_dtors_aux+0x16> 80081f0: 4b04 ldr r3, [pc, #16] @ (8008204 <__do_global_dtors_aux+0x1c>) 80081f2: b113 cbz r3, 80081fa <__do_global_dtors_aux+0x12> 80081f4: 4804 ldr r0, [pc, #16] @ (8008208 <__do_global_dtors_aux+0x20>) 80081f6: f3af 8000 nop.w 80081fa: 2301 movs r3, #1 80081fc: 7023 strb r3, [r4, #0] 80081fe: bd10 pop {r4, pc} 8008200: 200000d8 .word 0x200000d8 8008204: 00000000 .word 0x00000000 8008208: 08013fec .word 0x08013fec 0800820c : 800820c: b508 push {r3, lr} 800820e: 4b03 ldr r3, [pc, #12] @ (800821c ) 8008210: b11b cbz r3, 800821a 8008212: 4903 ldr r1, [pc, #12] @ (8008220 ) 8008214: 4803 ldr r0, [pc, #12] @ (8008224 ) 8008216: f3af 8000 nop.w 800821a: bd08 pop {r3, pc} 800821c: 00000000 .word 0x00000000 8008220: 200000dc .word 0x200000dc 8008224: 08013fec .word 0x08013fec 08008228 <__aeabi_drsub>: 8008228: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 800822c: e002 b.n 8008234 <__adddf3> 800822e: bf00 nop 08008230 <__aeabi_dsub>: 8008230: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 08008234 <__adddf3>: 8008234: b530 push {r4, r5, lr} 8008236: ea4f 0441 mov.w r4, r1, lsl #1 800823a: ea4f 0543 mov.w r5, r3, lsl #1 800823e: ea94 0f05 teq r4, r5 8008242: bf08 it eq 8008244: ea90 0f02 teqeq r0, r2 8008248: bf1f itttt ne 800824a: ea54 0c00 orrsne.w ip, r4, r0 800824e: ea55 0c02 orrsne.w ip, r5, r2 8008252: ea7f 5c64 mvnsne.w ip, r4, asr #21 8008256: ea7f 5c65 mvnsne.w ip, r5, asr #21 800825a: f000 80e2 beq.w 8008422 <__adddf3+0x1ee> 800825e: ea4f 5454 mov.w r4, r4, lsr #21 8008262: ebd4 5555 rsbs r5, r4, r5, lsr #21 8008266: bfb8 it lt 8008268: 426d neglt r5, r5 800826a: dd0c ble.n 8008286 <__adddf3+0x52> 800826c: 442c add r4, r5 800826e: ea80 0202 eor.w r2, r0, r2 8008272: ea81 0303 eor.w r3, r1, r3 8008276: ea82 0000 eor.w r0, r2, r0 800827a: ea83 0101 eor.w r1, r3, r1 800827e: ea80 0202 eor.w r2, r0, r2 8008282: ea81 0303 eor.w r3, r1, r3 8008286: 2d36 cmp r5, #54 @ 0x36 8008288: bf88 it hi 800828a: bd30 pophi {r4, r5, pc} 800828c: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008290: ea4f 3101 mov.w r1, r1, lsl #12 8008294: f44f 1c80 mov.w ip, #1048576 @ 0x100000 8008298: ea4c 3111 orr.w r1, ip, r1, lsr #12 800829c: d002 beq.n 80082a4 <__adddf3+0x70> 800829e: 4240 negs r0, r0 80082a0: eb61 0141 sbc.w r1, r1, r1, lsl #1 80082a4: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 80082a8: ea4f 3303 mov.w r3, r3, lsl #12 80082ac: ea4c 3313 orr.w r3, ip, r3, lsr #12 80082b0: d002 beq.n 80082b8 <__adddf3+0x84> 80082b2: 4252 negs r2, r2 80082b4: eb63 0343 sbc.w r3, r3, r3, lsl #1 80082b8: ea94 0f05 teq r4, r5 80082bc: f000 80a7 beq.w 800840e <__adddf3+0x1da> 80082c0: f1a4 0401 sub.w r4, r4, #1 80082c4: f1d5 0e20 rsbs lr, r5, #32 80082c8: db0d blt.n 80082e6 <__adddf3+0xb2> 80082ca: fa02 fc0e lsl.w ip, r2, lr 80082ce: fa22 f205 lsr.w r2, r2, r5 80082d2: 1880 adds r0, r0, r2 80082d4: f141 0100 adc.w r1, r1, #0 80082d8: fa03 f20e lsl.w r2, r3, lr 80082dc: 1880 adds r0, r0, r2 80082de: fa43 f305 asr.w r3, r3, r5 80082e2: 4159 adcs r1, r3 80082e4: e00e b.n 8008304 <__adddf3+0xd0> 80082e6: f1a5 0520 sub.w r5, r5, #32 80082ea: f10e 0e20 add.w lr, lr, #32 80082ee: 2a01 cmp r2, #1 80082f0: fa03 fc0e lsl.w ip, r3, lr 80082f4: bf28 it cs 80082f6: f04c 0c02 orrcs.w ip, ip, #2 80082fa: fa43 f305 asr.w r3, r3, r5 80082fe: 18c0 adds r0, r0, r3 8008300: eb51 71e3 adcs.w r1, r1, r3, asr #31 8008304: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008308: d507 bpl.n 800831a <__adddf3+0xe6> 800830a: f04f 0e00 mov.w lr, #0 800830e: f1dc 0c00 rsbs ip, ip, #0 8008312: eb7e 0000 sbcs.w r0, lr, r0 8008316: eb6e 0101 sbc.w r1, lr, r1 800831a: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 800831e: d31b bcc.n 8008358 <__adddf3+0x124> 8008320: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 8008324: d30c bcc.n 8008340 <__adddf3+0x10c> 8008326: 0849 lsrs r1, r1, #1 8008328: ea5f 0030 movs.w r0, r0, rrx 800832c: ea4f 0c3c mov.w ip, ip, rrx 8008330: f104 0401 add.w r4, r4, #1 8008334: ea4f 5244 mov.w r2, r4, lsl #21 8008338: f512 0f80 cmn.w r2, #4194304 @ 0x400000 800833c: f080 809a bcs.w 8008474 <__adddf3+0x240> 8008340: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008344: bf08 it eq 8008346: ea5f 0c50 movseq.w ip, r0, lsr #1 800834a: f150 0000 adcs.w r0, r0, #0 800834e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008352: ea41 0105 orr.w r1, r1, r5 8008356: bd30 pop {r4, r5, pc} 8008358: ea5f 0c4c movs.w ip, ip, lsl #1 800835c: 4140 adcs r0, r0 800835e: eb41 0101 adc.w r1, r1, r1 8008362: 3c01 subs r4, #1 8008364: bf28 it cs 8008366: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 800836a: d2e9 bcs.n 8008340 <__adddf3+0x10c> 800836c: f091 0f00 teq r1, #0 8008370: bf04 itt eq 8008372: 4601 moveq r1, r0 8008374: 2000 moveq r0, #0 8008376: fab1 f381 clz r3, r1 800837a: bf08 it eq 800837c: 3320 addeq r3, #32 800837e: f1a3 030b sub.w r3, r3, #11 8008382: f1b3 0220 subs.w r2, r3, #32 8008386: da0c bge.n 80083a2 <__adddf3+0x16e> 8008388: 320c adds r2, #12 800838a: dd08 ble.n 800839e <__adddf3+0x16a> 800838c: f102 0c14 add.w ip, r2, #20 8008390: f1c2 020c rsb r2, r2, #12 8008394: fa01 f00c lsl.w r0, r1, ip 8008398: fa21 f102 lsr.w r1, r1, r2 800839c: e00c b.n 80083b8 <__adddf3+0x184> 800839e: f102 0214 add.w r2, r2, #20 80083a2: bfd8 it le 80083a4: f1c2 0c20 rsble ip, r2, #32 80083a8: fa01 f102 lsl.w r1, r1, r2 80083ac: fa20 fc0c lsr.w ip, r0, ip 80083b0: bfdc itt le 80083b2: ea41 010c orrle.w r1, r1, ip 80083b6: 4090 lslle r0, r2 80083b8: 1ae4 subs r4, r4, r3 80083ba: bfa2 ittt ge 80083bc: eb01 5104 addge.w r1, r1, r4, lsl #20 80083c0: 4329 orrge r1, r5 80083c2: bd30 popge {r4, r5, pc} 80083c4: ea6f 0404 mvn.w r4, r4 80083c8: 3c1f subs r4, #31 80083ca: da1c bge.n 8008406 <__adddf3+0x1d2> 80083cc: 340c adds r4, #12 80083ce: dc0e bgt.n 80083ee <__adddf3+0x1ba> 80083d0: f104 0414 add.w r4, r4, #20 80083d4: f1c4 0220 rsb r2, r4, #32 80083d8: fa20 f004 lsr.w r0, r0, r4 80083dc: fa01 f302 lsl.w r3, r1, r2 80083e0: ea40 0003 orr.w r0, r0, r3 80083e4: fa21 f304 lsr.w r3, r1, r4 80083e8: ea45 0103 orr.w r1, r5, r3 80083ec: bd30 pop {r4, r5, pc} 80083ee: f1c4 040c rsb r4, r4, #12 80083f2: f1c4 0220 rsb r2, r4, #32 80083f6: fa20 f002 lsr.w r0, r0, r2 80083fa: fa01 f304 lsl.w r3, r1, r4 80083fe: ea40 0003 orr.w r0, r0, r3 8008402: 4629 mov r1, r5 8008404: bd30 pop {r4, r5, pc} 8008406: fa21 f004 lsr.w r0, r1, r4 800840a: 4629 mov r1, r5 800840c: bd30 pop {r4, r5, pc} 800840e: f094 0f00 teq r4, #0 8008412: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 8008416: bf06 itte eq 8008418: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 800841c: 3401 addeq r4, #1 800841e: 3d01 subne r5, #1 8008420: e74e b.n 80082c0 <__adddf3+0x8c> 8008422: ea7f 5c64 mvns.w ip, r4, asr #21 8008426: bf18 it ne 8008428: ea7f 5c65 mvnsne.w ip, r5, asr #21 800842c: d029 beq.n 8008482 <__adddf3+0x24e> 800842e: ea94 0f05 teq r4, r5 8008432: bf08 it eq 8008434: ea90 0f02 teqeq r0, r2 8008438: d005 beq.n 8008446 <__adddf3+0x212> 800843a: ea54 0c00 orrs.w ip, r4, r0 800843e: bf04 itt eq 8008440: 4619 moveq r1, r3 8008442: 4610 moveq r0, r2 8008444: bd30 pop {r4, r5, pc} 8008446: ea91 0f03 teq r1, r3 800844a: bf1e ittt ne 800844c: 2100 movne r1, #0 800844e: 2000 movne r0, #0 8008450: bd30 popne {r4, r5, pc} 8008452: ea5f 5c54 movs.w ip, r4, lsr #21 8008456: d105 bne.n 8008464 <__adddf3+0x230> 8008458: 0040 lsls r0, r0, #1 800845a: 4149 adcs r1, r1 800845c: bf28 it cs 800845e: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 8008462: bd30 pop {r4, r5, pc} 8008464: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 8008468: bf3c itt cc 800846a: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 800846e: bd30 popcc {r4, r5, pc} 8008470: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008474: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 8008478: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 800847c: f04f 0000 mov.w r0, #0 8008480: bd30 pop {r4, r5, pc} 8008482: ea7f 5c64 mvns.w ip, r4, asr #21 8008486: bf1a itte ne 8008488: 4619 movne r1, r3 800848a: 4610 movne r0, r2 800848c: ea7f 5c65 mvnseq.w ip, r5, asr #21 8008490: bf1c itt ne 8008492: 460b movne r3, r1 8008494: 4602 movne r2, r0 8008496: ea50 3401 orrs.w r4, r0, r1, lsl #12 800849a: bf06 itte eq 800849c: ea52 3503 orrseq.w r5, r2, r3, lsl #12 80084a0: ea91 0f03 teqeq r1, r3 80084a4: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 80084a8: bd30 pop {r4, r5, pc} 80084aa: bf00 nop 080084ac <__aeabi_ui2d>: 80084ac: f090 0f00 teq r0, #0 80084b0: bf04 itt eq 80084b2: 2100 moveq r1, #0 80084b4: 4770 bxeq lr 80084b6: b530 push {r4, r5, lr} 80084b8: f44f 6480 mov.w r4, #1024 @ 0x400 80084bc: f104 0432 add.w r4, r4, #50 @ 0x32 80084c0: f04f 0500 mov.w r5, #0 80084c4: f04f 0100 mov.w r1, #0 80084c8: e750 b.n 800836c <__adddf3+0x138> 80084ca: bf00 nop 080084cc <__aeabi_i2d>: 80084cc: f090 0f00 teq r0, #0 80084d0: bf04 itt eq 80084d2: 2100 moveq r1, #0 80084d4: 4770 bxeq lr 80084d6: b530 push {r4, r5, lr} 80084d8: f44f 6480 mov.w r4, #1024 @ 0x400 80084dc: f104 0432 add.w r4, r4, #50 @ 0x32 80084e0: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 80084e4: bf48 it mi 80084e6: 4240 negmi r0, r0 80084e8: f04f 0100 mov.w r1, #0 80084ec: e73e b.n 800836c <__adddf3+0x138> 80084ee: bf00 nop 080084f0 <__aeabi_f2d>: 80084f0: 0042 lsls r2, r0, #1 80084f2: ea4f 01e2 mov.w r1, r2, asr #3 80084f6: ea4f 0131 mov.w r1, r1, rrx 80084fa: ea4f 7002 mov.w r0, r2, lsl #28 80084fe: bf1f itttt ne 8008500: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 8008504: f093 4f7f teqne r3, #4278190080 @ 0xff000000 8008508: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 800850c: 4770 bxne lr 800850e: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 8008512: bf08 it eq 8008514: 4770 bxeq lr 8008516: f093 4f7f teq r3, #4278190080 @ 0xff000000 800851a: bf04 itt eq 800851c: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 8008520: 4770 bxeq lr 8008522: b530 push {r4, r5, lr} 8008524: f44f 7460 mov.w r4, #896 @ 0x380 8008528: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 800852c: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 8008530: e71c b.n 800836c <__adddf3+0x138> 8008532: bf00 nop 08008534 <__aeabi_ul2d>: 8008534: ea50 0201 orrs.w r2, r0, r1 8008538: bf08 it eq 800853a: 4770 bxeq lr 800853c: b530 push {r4, r5, lr} 800853e: f04f 0500 mov.w r5, #0 8008542: e00a b.n 800855a <__aeabi_l2d+0x16> 08008544 <__aeabi_l2d>: 8008544: ea50 0201 orrs.w r2, r0, r1 8008548: bf08 it eq 800854a: 4770 bxeq lr 800854c: b530 push {r4, r5, lr} 800854e: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 8008552: d502 bpl.n 800855a <__aeabi_l2d+0x16> 8008554: 4240 negs r0, r0 8008556: eb61 0141 sbc.w r1, r1, r1, lsl #1 800855a: f44f 6480 mov.w r4, #1024 @ 0x400 800855e: f104 0432 add.w r4, r4, #50 @ 0x32 8008562: ea5f 5c91 movs.w ip, r1, lsr #22 8008566: f43f aed8 beq.w 800831a <__adddf3+0xe6> 800856a: f04f 0203 mov.w r2, #3 800856e: ea5f 0cdc movs.w ip, ip, lsr #3 8008572: bf18 it ne 8008574: 3203 addne r2, #3 8008576: ea5f 0cdc movs.w ip, ip, lsr #3 800857a: bf18 it ne 800857c: 3203 addne r2, #3 800857e: eb02 02dc add.w r2, r2, ip, lsr #3 8008582: f1c2 0320 rsb r3, r2, #32 8008586: fa00 fc03 lsl.w ip, r0, r3 800858a: fa20 f002 lsr.w r0, r0, r2 800858e: fa01 fe03 lsl.w lr, r1, r3 8008592: ea40 000e orr.w r0, r0, lr 8008596: fa21 f102 lsr.w r1, r1, r2 800859a: 4414 add r4, r2 800859c: e6bd b.n 800831a <__adddf3+0xe6> 800859e: bf00 nop 080085a0 <__aeabi_dmul>: 80085a0: b570 push {r4, r5, r6, lr} 80085a2: f04f 0cff mov.w ip, #255 @ 0xff 80085a6: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 80085aa: ea1c 5411 ands.w r4, ip, r1, lsr #20 80085ae: bf1d ittte ne 80085b0: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80085b4: ea94 0f0c teqne r4, ip 80085b8: ea95 0f0c teqne r5, ip 80085bc: f000 f8de bleq 800877c <__aeabi_dmul+0x1dc> 80085c0: 442c add r4, r5 80085c2: ea81 0603 eor.w r6, r1, r3 80085c6: ea21 514c bic.w r1, r1, ip, lsl #21 80085ca: ea23 534c bic.w r3, r3, ip, lsl #21 80085ce: ea50 3501 orrs.w r5, r0, r1, lsl #12 80085d2: bf18 it ne 80085d4: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80085d8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 80085dc: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80085e0: d038 beq.n 8008654 <__aeabi_dmul+0xb4> 80085e2: fba0 ce02 umull ip, lr, r0, r2 80085e6: f04f 0500 mov.w r5, #0 80085ea: fbe1 e502 umlal lr, r5, r1, r2 80085ee: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 80085f2: fbe0 e503 umlal lr, r5, r0, r3 80085f6: f04f 0600 mov.w r6, #0 80085fa: fbe1 5603 umlal r5, r6, r1, r3 80085fe: f09c 0f00 teq ip, #0 8008602: bf18 it ne 8008604: f04e 0e01 orrne.w lr, lr, #1 8008608: f1a4 04ff sub.w r4, r4, #255 @ 0xff 800860c: f5b6 7f00 cmp.w r6, #512 @ 0x200 8008610: f564 7440 sbc.w r4, r4, #768 @ 0x300 8008614: d204 bcs.n 8008620 <__aeabi_dmul+0x80> 8008616: ea5f 0e4e movs.w lr, lr, lsl #1 800861a: 416d adcs r5, r5 800861c: eb46 0606 adc.w r6, r6, r6 8008620: ea42 21c6 orr.w r1, r2, r6, lsl #11 8008624: ea41 5155 orr.w r1, r1, r5, lsr #21 8008628: ea4f 20c5 mov.w r0, r5, lsl #11 800862c: ea40 505e orr.w r0, r0, lr, lsr #21 8008630: ea4f 2ece mov.w lr, lr, lsl #11 8008634: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008638: bf88 it hi 800863a: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800863e: d81e bhi.n 800867e <__aeabi_dmul+0xde> 8008640: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 8008644: bf08 it eq 8008646: ea5f 0e50 movseq.w lr, r0, lsr #1 800864a: f150 0000 adcs.w r0, r0, #0 800864e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008652: bd70 pop {r4, r5, r6, pc} 8008654: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 8008658: ea46 0101 orr.w r1, r6, r1 800865c: ea40 0002 orr.w r0, r0, r2 8008660: ea81 0103 eor.w r1, r1, r3 8008664: ebb4 045c subs.w r4, r4, ip, lsr #1 8008668: bfc2 ittt gt 800866a: ebd4 050c rsbsgt r5, r4, ip 800866e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8008672: bd70 popgt {r4, r5, r6, pc} 8008674: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008678: f04f 0e00 mov.w lr, #0 800867c: 3c01 subs r4, #1 800867e: f300 80ab bgt.w 80087d8 <__aeabi_dmul+0x238> 8008682: f114 0f36 cmn.w r4, #54 @ 0x36 8008686: bfde ittt le 8008688: 2000 movle r0, #0 800868a: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 800868e: bd70 pople {r4, r5, r6, pc} 8008690: f1c4 0400 rsb r4, r4, #0 8008694: 3c20 subs r4, #32 8008696: da35 bge.n 8008704 <__aeabi_dmul+0x164> 8008698: 340c adds r4, #12 800869a: dc1b bgt.n 80086d4 <__aeabi_dmul+0x134> 800869c: f104 0414 add.w r4, r4, #20 80086a0: f1c4 0520 rsb r5, r4, #32 80086a4: fa00 f305 lsl.w r3, r0, r5 80086a8: fa20 f004 lsr.w r0, r0, r4 80086ac: fa01 f205 lsl.w r2, r1, r5 80086b0: ea40 0002 orr.w r0, r0, r2 80086b4: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 80086b8: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 80086bc: eb10 70d3 adds.w r0, r0, r3, lsr #31 80086c0: fa21 f604 lsr.w r6, r1, r4 80086c4: eb42 0106 adc.w r1, r2, r6 80086c8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80086cc: bf08 it eq 80086ce: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80086d2: bd70 pop {r4, r5, r6, pc} 80086d4: f1c4 040c rsb r4, r4, #12 80086d8: f1c4 0520 rsb r5, r4, #32 80086dc: fa00 f304 lsl.w r3, r0, r4 80086e0: fa20 f005 lsr.w r0, r0, r5 80086e4: fa01 f204 lsl.w r2, r1, r4 80086e8: ea40 0002 orr.w r0, r0, r2 80086ec: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80086f0: eb10 70d3 adds.w r0, r0, r3, lsr #31 80086f4: f141 0100 adc.w r1, r1, #0 80086f8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80086fc: bf08 it eq 80086fe: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8008702: bd70 pop {r4, r5, r6, pc} 8008704: f1c4 0520 rsb r5, r4, #32 8008708: fa00 f205 lsl.w r2, r0, r5 800870c: ea4e 0e02 orr.w lr, lr, r2 8008710: fa20 f304 lsr.w r3, r0, r4 8008714: fa01 f205 lsl.w r2, r1, r5 8008718: ea43 0302 orr.w r3, r3, r2 800871c: fa21 f004 lsr.w r0, r1, r4 8008720: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008724: fa21 f204 lsr.w r2, r1, r4 8008728: ea20 0002 bic.w r0, r0, r2 800872c: eb00 70d3 add.w r0, r0, r3, lsr #31 8008730: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8008734: bf08 it eq 8008736: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800873a: bd70 pop {r4, r5, r6, pc} 800873c: f094 0f00 teq r4, #0 8008740: d10f bne.n 8008762 <__aeabi_dmul+0x1c2> 8008742: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 8008746: 0040 lsls r0, r0, #1 8008748: eb41 0101 adc.w r1, r1, r1 800874c: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008750: bf08 it eq 8008752: 3c01 subeq r4, #1 8008754: d0f7 beq.n 8008746 <__aeabi_dmul+0x1a6> 8008756: ea41 0106 orr.w r1, r1, r6 800875a: f095 0f00 teq r5, #0 800875e: bf18 it ne 8008760: 4770 bxne lr 8008762: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 8008766: 0052 lsls r2, r2, #1 8008768: eb43 0303 adc.w r3, r3, r3 800876c: f413 1f80 tst.w r3, #1048576 @ 0x100000 8008770: bf08 it eq 8008772: 3d01 subeq r5, #1 8008774: d0f7 beq.n 8008766 <__aeabi_dmul+0x1c6> 8008776: ea43 0306 orr.w r3, r3, r6 800877a: 4770 bx lr 800877c: ea94 0f0c teq r4, ip 8008780: ea0c 5513 and.w r5, ip, r3, lsr #20 8008784: bf18 it ne 8008786: ea95 0f0c teqne r5, ip 800878a: d00c beq.n 80087a6 <__aeabi_dmul+0x206> 800878c: ea50 0641 orrs.w r6, r0, r1, lsl #1 8008790: bf18 it ne 8008792: ea52 0643 orrsne.w r6, r2, r3, lsl #1 8008796: d1d1 bne.n 800873c <__aeabi_dmul+0x19c> 8008798: ea81 0103 eor.w r1, r1, r3 800879c: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087a0: f04f 0000 mov.w r0, #0 80087a4: bd70 pop {r4, r5, r6, pc} 80087a6: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087aa: bf06 itte eq 80087ac: 4610 moveq r0, r2 80087ae: 4619 moveq r1, r3 80087b0: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087b4: d019 beq.n 80087ea <__aeabi_dmul+0x24a> 80087b6: ea94 0f0c teq r4, ip 80087ba: d102 bne.n 80087c2 <__aeabi_dmul+0x222> 80087bc: ea50 3601 orrs.w r6, r0, r1, lsl #12 80087c0: d113 bne.n 80087ea <__aeabi_dmul+0x24a> 80087c2: ea95 0f0c teq r5, ip 80087c6: d105 bne.n 80087d4 <__aeabi_dmul+0x234> 80087c8: ea52 3603 orrs.w r6, r2, r3, lsl #12 80087cc: bf1c itt ne 80087ce: 4610 movne r0, r2 80087d0: 4619 movne r1, r3 80087d2: d10a bne.n 80087ea <__aeabi_dmul+0x24a> 80087d4: ea81 0103 eor.w r1, r1, r3 80087d8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087dc: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087e0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 80087e4: f04f 0000 mov.w r0, #0 80087e8: bd70 pop {r4, r5, r6, pc} 80087ea: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087ee: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 80087f2: bd70 pop {r4, r5, r6, pc} 080087f4 <__aeabi_ddiv>: 80087f4: b570 push {r4, r5, r6, lr} 80087f6: f04f 0cff mov.w ip, #255 @ 0xff 80087fa: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 80087fe: ea1c 5411 ands.w r4, ip, r1, lsr #20 8008802: bf1d ittte ne 8008804: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8008808: ea94 0f0c teqne r4, ip 800880c: ea95 0f0c teqne r5, ip 8008810: f000 f8a7 bleq 8008962 <__aeabi_ddiv+0x16e> 8008814: eba4 0405 sub.w r4, r4, r5 8008818: ea81 0e03 eor.w lr, r1, r3 800881c: ea52 3503 orrs.w r5, r2, r3, lsl #12 8008820: ea4f 3101 mov.w r1, r1, lsl #12 8008824: f000 8088 beq.w 8008938 <__aeabi_ddiv+0x144> 8008828: ea4f 3303 mov.w r3, r3, lsl #12 800882c: f04f 5580 mov.w r5, #268435456 @ 0x10000000 8008830: ea45 1313 orr.w r3, r5, r3, lsr #4 8008834: ea43 6312 orr.w r3, r3, r2, lsr #24 8008838: ea4f 2202 mov.w r2, r2, lsl #8 800883c: ea45 1511 orr.w r5, r5, r1, lsr #4 8008840: ea45 6510 orr.w r5, r5, r0, lsr #24 8008844: ea4f 2600 mov.w r6, r0, lsl #8 8008848: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000 800884c: 429d cmp r5, r3 800884e: bf08 it eq 8008850: 4296 cmpeq r6, r2 8008852: f144 04fd adc.w r4, r4, #253 @ 0xfd 8008856: f504 7440 add.w r4, r4, #768 @ 0x300 800885a: d202 bcs.n 8008862 <__aeabi_ddiv+0x6e> 800885c: 085b lsrs r3, r3, #1 800885e: ea4f 0232 mov.w r2, r2, rrx 8008862: 1ab6 subs r6, r6, r2 8008864: eb65 0503 sbc.w r5, r5, r3 8008868: 085b lsrs r3, r3, #1 800886a: ea4f 0232 mov.w r2, r2, rrx 800886e: f44f 1080 mov.w r0, #1048576 @ 0x100000 8008872: f44f 2c00 mov.w ip, #524288 @ 0x80000 8008876: ebb6 0e02 subs.w lr, r6, r2 800887a: eb75 0e03 sbcs.w lr, r5, r3 800887e: bf22 ittt cs 8008880: 1ab6 subcs r6, r6, r2 8008882: 4675 movcs r5, lr 8008884: ea40 000c orrcs.w r0, r0, ip 8008888: 085b lsrs r3, r3, #1 800888a: ea4f 0232 mov.w r2, r2, rrx 800888e: ebb6 0e02 subs.w lr, r6, r2 8008892: eb75 0e03 sbcs.w lr, r5, r3 8008896: bf22 ittt cs 8008898: 1ab6 subcs r6, r6, r2 800889a: 4675 movcs r5, lr 800889c: ea40 005c orrcs.w r0, r0, ip, lsr #1 80088a0: 085b lsrs r3, r3, #1 80088a2: ea4f 0232 mov.w r2, r2, rrx 80088a6: ebb6 0e02 subs.w lr, r6, r2 80088aa: eb75 0e03 sbcs.w lr, r5, r3 80088ae: bf22 ittt cs 80088b0: 1ab6 subcs r6, r6, r2 80088b2: 4675 movcs r5, lr 80088b4: ea40 009c orrcs.w r0, r0, ip, lsr #2 80088b8: 085b lsrs r3, r3, #1 80088ba: ea4f 0232 mov.w r2, r2, rrx 80088be: ebb6 0e02 subs.w lr, r6, r2 80088c2: eb75 0e03 sbcs.w lr, r5, r3 80088c6: bf22 ittt cs 80088c8: 1ab6 subcs r6, r6, r2 80088ca: 4675 movcs r5, lr 80088cc: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80088d0: ea55 0e06 orrs.w lr, r5, r6 80088d4: d018 beq.n 8008908 <__aeabi_ddiv+0x114> 80088d6: ea4f 1505 mov.w r5, r5, lsl #4 80088da: ea45 7516 orr.w r5, r5, r6, lsr #28 80088de: ea4f 1606 mov.w r6, r6, lsl #4 80088e2: ea4f 03c3 mov.w r3, r3, lsl #3 80088e6: ea43 7352 orr.w r3, r3, r2, lsr #29 80088ea: ea4f 02c2 mov.w r2, r2, lsl #3 80088ee: ea5f 1c1c movs.w ip, ip, lsr #4 80088f2: d1c0 bne.n 8008876 <__aeabi_ddiv+0x82> 80088f4: f411 1f80 tst.w r1, #1048576 @ 0x100000 80088f8: d10b bne.n 8008912 <__aeabi_ddiv+0x11e> 80088fa: ea41 0100 orr.w r1, r1, r0 80088fe: f04f 0000 mov.w r0, #0 8008902: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000 8008906: e7b6 b.n 8008876 <__aeabi_ddiv+0x82> 8008908: f411 1f80 tst.w r1, #1048576 @ 0x100000 800890c: bf04 itt eq 800890e: 4301 orreq r1, r0 8008910: 2000 moveq r0, #0 8008912: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008916: bf88 it hi 8008918: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800891c: f63f aeaf bhi.w 800867e <__aeabi_dmul+0xde> 8008920: ebb5 0c03 subs.w ip, r5, r3 8008924: bf04 itt eq 8008926: ebb6 0c02 subseq.w ip, r6, r2 800892a: ea5f 0c50 movseq.w ip, r0, lsr #1 800892e: f150 0000 adcs.w r0, r0, #0 8008932: eb41 5104 adc.w r1, r1, r4, lsl #20 8008936: bd70 pop {r4, r5, r6, pc} 8008938: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000 800893c: ea4e 3111 orr.w r1, lr, r1, lsr #12 8008940: eb14 045c adds.w r4, r4, ip, lsr #1 8008944: bfc2 ittt gt 8008946: ebd4 050c rsbsgt r5, r4, ip 800894a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800894e: bd70 popgt {r4, r5, r6, pc} 8008950: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008954: f04f 0e00 mov.w lr, #0 8008958: 3c01 subs r4, #1 800895a: e690 b.n 800867e <__aeabi_dmul+0xde> 800895c: ea45 0e06 orr.w lr, r5, r6 8008960: e68d b.n 800867e <__aeabi_dmul+0xde> 8008962: ea0c 5513 and.w r5, ip, r3, lsr #20 8008966: ea94 0f0c teq r4, ip 800896a: bf08 it eq 800896c: ea95 0f0c teqeq r5, ip 8008970: f43f af3b beq.w 80087ea <__aeabi_dmul+0x24a> 8008974: ea94 0f0c teq r4, ip 8008978: d10a bne.n 8008990 <__aeabi_ddiv+0x19c> 800897a: ea50 3401 orrs.w r4, r0, r1, lsl #12 800897e: f47f af34 bne.w 80087ea <__aeabi_dmul+0x24a> 8008982: ea95 0f0c teq r5, ip 8008986: f47f af25 bne.w 80087d4 <__aeabi_dmul+0x234> 800898a: 4610 mov r0, r2 800898c: 4619 mov r1, r3 800898e: e72c b.n 80087ea <__aeabi_dmul+0x24a> 8008990: ea95 0f0c teq r5, ip 8008994: d106 bne.n 80089a4 <__aeabi_ddiv+0x1b0> 8008996: ea52 3503 orrs.w r5, r2, r3, lsl #12 800899a: f43f aefd beq.w 8008798 <__aeabi_dmul+0x1f8> 800899e: 4610 mov r0, r2 80089a0: 4619 mov r1, r3 80089a2: e722 b.n 80087ea <__aeabi_dmul+0x24a> 80089a4: ea50 0641 orrs.w r6, r0, r1, lsl #1 80089a8: bf18 it ne 80089aa: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80089ae: f47f aec5 bne.w 800873c <__aeabi_dmul+0x19c> 80089b2: ea50 0441 orrs.w r4, r0, r1, lsl #1 80089b6: f47f af0d bne.w 80087d4 <__aeabi_dmul+0x234> 80089ba: ea52 0543 orrs.w r5, r2, r3, lsl #1 80089be: f47f aeeb bne.w 8008798 <__aeabi_dmul+0x1f8> 80089c2: e712 b.n 80087ea <__aeabi_dmul+0x24a> 080089c4 <__aeabi_d2f>: 80089c4: ea4f 0241 mov.w r2, r1, lsl #1 80089c8: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000 80089cc: bf24 itt cs 80089ce: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000 80089d2: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000 80089d6: d90d bls.n 80089f4 <__aeabi_d2f+0x30> 80089d8: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 80089dc: ea4f 02c0 mov.w r2, r0, lsl #3 80089e0: ea4c 7050 orr.w r0, ip, r0, lsr #29 80089e4: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000 80089e8: eb40 0083 adc.w r0, r0, r3, lsl #2 80089ec: bf08 it eq 80089ee: f020 0001 biceq.w r0, r0, #1 80089f2: 4770 bx lr 80089f4: f011 4f80 tst.w r1, #1073741824 @ 0x40000000 80089f8: d121 bne.n 8008a3e <__aeabi_d2f+0x7a> 80089fa: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000 80089fe: bfbc itt lt 8008a00: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000 8008a04: 4770 bxlt lr 8008a06: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008a0a: ea4f 5252 mov.w r2, r2, lsr #21 8008a0e: f1c2 0218 rsb r2, r2, #24 8008a12: f1c2 0c20 rsb ip, r2, #32 8008a16: fa10 f30c lsls.w r3, r0, ip 8008a1a: fa20 f002 lsr.w r0, r0, r2 8008a1e: bf18 it ne 8008a20: f040 0001 orrne.w r0, r0, #1 8008a24: ea4f 23c1 mov.w r3, r1, lsl #11 8008a28: ea4f 23d3 mov.w r3, r3, lsr #11 8008a2c: fa03 fc0c lsl.w ip, r3, ip 8008a30: ea40 000c orr.w r0, r0, ip 8008a34: fa23 f302 lsr.w r3, r3, r2 8008a38: ea4f 0343 mov.w r3, r3, lsl #1 8008a3c: e7cc b.n 80089d8 <__aeabi_d2f+0x14> 8008a3e: ea7f 5362 mvns.w r3, r2, asr #21 8008a42: d107 bne.n 8008a54 <__aeabi_d2f+0x90> 8008a44: ea50 3301 orrs.w r3, r0, r1, lsl #12 8008a48: bf1e ittt ne 8008a4a: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000 8008a4e: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000 8008a52: 4770 bxne lr 8008a54: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000 8008a58: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008a5c: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008a60: 4770 bx lr 8008a62: bf00 nop 08008a64 <__aeabi_frsub>: 8008a64: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000 8008a68: e002 b.n 8008a70 <__addsf3> 8008a6a: bf00 nop 08008a6c <__aeabi_fsub>: 8008a6c: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 08008a70 <__addsf3>: 8008a70: 0042 lsls r2, r0, #1 8008a72: bf1f itttt ne 8008a74: ea5f 0341 movsne.w r3, r1, lsl #1 8008a78: ea92 0f03 teqne r2, r3 8008a7c: ea7f 6c22 mvnsne.w ip, r2, asr #24 8008a80: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008a84: d06a beq.n 8008b5c <__addsf3+0xec> 8008a86: ea4f 6212 mov.w r2, r2, lsr #24 8008a8a: ebd2 6313 rsbs r3, r2, r3, lsr #24 8008a8e: bfc1 itttt gt 8008a90: 18d2 addgt r2, r2, r3 8008a92: 4041 eorgt r1, r0 8008a94: 4048 eorgt r0, r1 8008a96: 4041 eorgt r1, r0 8008a98: bfb8 it lt 8008a9a: 425b neglt r3, r3 8008a9c: 2b19 cmp r3, #25 8008a9e: bf88 it hi 8008aa0: 4770 bxhi lr 8008aa2: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 8008aa6: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008aaa: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000 8008aae: bf18 it ne 8008ab0: 4240 negne r0, r0 8008ab2: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008ab6: f441 0100 orr.w r1, r1, #8388608 @ 0x800000 8008aba: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000 8008abe: bf18 it ne 8008ac0: 4249 negne r1, r1 8008ac2: ea92 0f03 teq r2, r3 8008ac6: d03f beq.n 8008b48 <__addsf3+0xd8> 8008ac8: f1a2 0201 sub.w r2, r2, #1 8008acc: fa41 fc03 asr.w ip, r1, r3 8008ad0: eb10 000c adds.w r0, r0, ip 8008ad4: f1c3 0320 rsb r3, r3, #32 8008ad8: fa01 f103 lsl.w r1, r1, r3 8008adc: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008ae0: d502 bpl.n 8008ae8 <__addsf3+0x78> 8008ae2: 4249 negs r1, r1 8008ae4: eb60 0040 sbc.w r0, r0, r0, lsl #1 8008ae8: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000 8008aec: d313 bcc.n 8008b16 <__addsf3+0xa6> 8008aee: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000 8008af2: d306 bcc.n 8008b02 <__addsf3+0x92> 8008af4: 0840 lsrs r0, r0, #1 8008af6: ea4f 0131 mov.w r1, r1, rrx 8008afa: f102 0201 add.w r2, r2, #1 8008afe: 2afe cmp r2, #254 @ 0xfe 8008b00: d251 bcs.n 8008ba6 <__addsf3+0x136> 8008b02: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000 8008b06: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008b0a: bf08 it eq 8008b0c: f020 0001 biceq.w r0, r0, #1 8008b10: ea40 0003 orr.w r0, r0, r3 8008b14: 4770 bx lr 8008b16: 0049 lsls r1, r1, #1 8008b18: eb40 0000 adc.w r0, r0, r0 8008b1c: 3a01 subs r2, #1 8008b1e: bf28 it cs 8008b20: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000 8008b24: d2ed bcs.n 8008b02 <__addsf3+0x92> 8008b26: fab0 fc80 clz ip, r0 8008b2a: f1ac 0c08 sub.w ip, ip, #8 8008b2e: ebb2 020c subs.w r2, r2, ip 8008b32: fa00 f00c lsl.w r0, r0, ip 8008b36: bfaa itet ge 8008b38: eb00 50c2 addge.w r0, r0, r2, lsl #23 8008b3c: 4252 neglt r2, r2 8008b3e: 4318 orrge r0, r3 8008b40: bfbc itt lt 8008b42: 40d0 lsrlt r0, r2 8008b44: 4318 orrlt r0, r3 8008b46: 4770 bx lr 8008b48: f092 0f00 teq r2, #0 8008b4c: f481 0100 eor.w r1, r1, #8388608 @ 0x800000 8008b50: bf06 itte eq 8008b52: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000 8008b56: 3201 addeq r2, #1 8008b58: 3b01 subne r3, #1 8008b5a: e7b5 b.n 8008ac8 <__addsf3+0x58> 8008b5c: ea4f 0341 mov.w r3, r1, lsl #1 8008b60: ea7f 6c22 mvns.w ip, r2, asr #24 8008b64: bf18 it ne 8008b66: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008b6a: d021 beq.n 8008bb0 <__addsf3+0x140> 8008b6c: ea92 0f03 teq r2, r3 8008b70: d004 beq.n 8008b7c <__addsf3+0x10c> 8008b72: f092 0f00 teq r2, #0 8008b76: bf08 it eq 8008b78: 4608 moveq r0, r1 8008b7a: 4770 bx lr 8008b7c: ea90 0f01 teq r0, r1 8008b80: bf1c itt ne 8008b82: 2000 movne r0, #0 8008b84: 4770 bxne lr 8008b86: f012 4f7f tst.w r2, #4278190080 @ 0xff000000 8008b8a: d104 bne.n 8008b96 <__addsf3+0x126> 8008b8c: 0040 lsls r0, r0, #1 8008b8e: bf28 it cs 8008b90: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000 8008b94: 4770 bx lr 8008b96: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000 8008b9a: bf3c itt cc 8008b9c: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000 8008ba0: 4770 bxcc lr 8008ba2: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008ba6: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000 8008baa: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008bae: 4770 bx lr 8008bb0: ea7f 6222 mvns.w r2, r2, asr #24 8008bb4: bf16 itet ne 8008bb6: 4608 movne r0, r1 8008bb8: ea7f 6323 mvnseq.w r3, r3, asr #24 8008bbc: 4601 movne r1, r0 8008bbe: 0242 lsls r2, r0, #9 8008bc0: bf06 itte eq 8008bc2: ea5f 2341 movseq.w r3, r1, lsl #9 8008bc6: ea90 0f01 teqeq r0, r1 8008bca: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000 8008bce: 4770 bx lr 08008bd0 <__aeabi_ui2f>: 8008bd0: f04f 0300 mov.w r3, #0 8008bd4: e004 b.n 8008be0 <__aeabi_i2f+0x8> 8008bd6: bf00 nop 08008bd8 <__aeabi_i2f>: 8008bd8: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000 8008bdc: bf48 it mi 8008bde: 4240 negmi r0, r0 8008be0: ea5f 0c00 movs.w ip, r0 8008be4: bf08 it eq 8008be6: 4770 bxeq lr 8008be8: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000 8008bec: 4601 mov r1, r0 8008bee: f04f 0000 mov.w r0, #0 8008bf2: e01c b.n 8008c2e <__aeabi_l2f+0x2a> 08008bf4 <__aeabi_ul2f>: 8008bf4: ea50 0201 orrs.w r2, r0, r1 8008bf8: bf08 it eq 8008bfa: 4770 bxeq lr 8008bfc: f04f 0300 mov.w r3, #0 8008c00: e00a b.n 8008c18 <__aeabi_l2f+0x14> 8008c02: bf00 nop 08008c04 <__aeabi_l2f>: 8008c04: ea50 0201 orrs.w r2, r0, r1 8008c08: bf08 it eq 8008c0a: 4770 bxeq lr 8008c0c: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000 8008c10: d502 bpl.n 8008c18 <__aeabi_l2f+0x14> 8008c12: 4240 negs r0, r0 8008c14: eb61 0141 sbc.w r1, r1, r1, lsl #1 8008c18: ea5f 0c01 movs.w ip, r1 8008c1c: bf02 ittt eq 8008c1e: 4684 moveq ip, r0 8008c20: 4601 moveq r1, r0 8008c22: 2000 moveq r0, #0 8008c24: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000 8008c28: bf08 it eq 8008c2a: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000 8008c2e: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 8008c32: fabc f28c clz r2, ip 8008c36: 3a08 subs r2, #8 8008c38: eba3 53c2 sub.w r3, r3, r2, lsl #23 8008c3c: db10 blt.n 8008c60 <__aeabi_l2f+0x5c> 8008c3e: fa01 fc02 lsl.w ip, r1, r2 8008c42: 4463 add r3, ip 8008c44: fa00 fc02 lsl.w ip, r0, r2 8008c48: f1c2 0220 rsb r2, r2, #32 8008c4c: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008c50: fa20 f202 lsr.w r2, r0, r2 8008c54: eb43 0002 adc.w r0, r3, r2 8008c58: bf08 it eq 8008c5a: f020 0001 biceq.w r0, r0, #1 8008c5e: 4770 bx lr 8008c60: f102 0220 add.w r2, r2, #32 8008c64: fa01 fc02 lsl.w ip, r1, r2 8008c68: f1c2 0220 rsb r2, r2, #32 8008c6c: ea50 004c orrs.w r0, r0, ip, lsl #1 8008c70: fa21 f202 lsr.w r2, r1, r2 8008c74: eb43 0002 adc.w r0, r3, r2 8008c78: bf08 it eq 8008c7a: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008c7e: 4770 bx lr 08008c80 <__aeabi_fmul>: 8008c80: f04f 0cff mov.w ip, #255 @ 0xff 8008c84: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008c88: bf1e ittt ne 8008c8a: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008c8e: ea92 0f0c teqne r2, ip 8008c92: ea93 0f0c teqne r3, ip 8008c96: d06f beq.n 8008d78 <__aeabi_fmul+0xf8> 8008c98: 441a add r2, r3 8008c9a: ea80 0c01 eor.w ip, r0, r1 8008c9e: 0240 lsls r0, r0, #9 8008ca0: bf18 it ne 8008ca2: ea5f 2141 movsne.w r1, r1, lsl #9 8008ca6: d01e beq.n 8008ce6 <__aeabi_fmul+0x66> 8008ca8: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8008cac: ea43 1050 orr.w r0, r3, r0, lsr #5 8008cb0: ea43 1151 orr.w r1, r3, r1, lsr #5 8008cb4: fba0 3101 umull r3, r1, r0, r1 8008cb8: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008cbc: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000 8008cc0: bf3e ittt cc 8008cc2: 0049 lslcc r1, r1, #1 8008cc4: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 8008cc8: 005b lslcc r3, r3, #1 8008cca: ea40 0001 orr.w r0, r0, r1 8008cce: f162 027f sbc.w r2, r2, #127 @ 0x7f 8008cd2: 2afd cmp r2, #253 @ 0xfd 8008cd4: d81d bhi.n 8008d12 <__aeabi_fmul+0x92> 8008cd6: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008cda: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008cde: bf08 it eq 8008ce0: f020 0001 biceq.w r0, r0, #1 8008ce4: 4770 bx lr 8008ce6: f090 0f00 teq r0, #0 8008cea: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8008cee: bf08 it eq 8008cf0: 0249 lsleq r1, r1, #9 8008cf2: ea4c 2050 orr.w r0, ip, r0, lsr #9 8008cf6: ea40 2051 orr.w r0, r0, r1, lsr #9 8008cfa: 3a7f subs r2, #127 @ 0x7f 8008cfc: bfc2 ittt gt 8008cfe: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 8008d02: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8008d06: 4770 bxgt lr 8008d08: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008d0c: f04f 0300 mov.w r3, #0 8008d10: 3a01 subs r2, #1 8008d12: dc5d bgt.n 8008dd0 <__aeabi_fmul+0x150> 8008d14: f112 0f19 cmn.w r2, #25 8008d18: bfdc itt le 8008d1a: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000 8008d1e: 4770 bxle lr 8008d20: f1c2 0200 rsb r2, r2, #0 8008d24: 0041 lsls r1, r0, #1 8008d26: fa21 f102 lsr.w r1, r1, r2 8008d2a: f1c2 0220 rsb r2, r2, #32 8008d2e: fa00 fc02 lsl.w ip, r0, r2 8008d32: ea5f 0031 movs.w r0, r1, rrx 8008d36: f140 0000 adc.w r0, r0, #0 8008d3a: ea53 034c orrs.w r3, r3, ip, lsl #1 8008d3e: bf08 it eq 8008d40: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008d44: 4770 bx lr 8008d46: f092 0f00 teq r2, #0 8008d4a: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8008d4e: bf02 ittt eq 8008d50: 0040 lsleq r0, r0, #1 8008d52: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 8008d56: 3a01 subeq r2, #1 8008d58: d0f9 beq.n 8008d4e <__aeabi_fmul+0xce> 8008d5a: ea40 000c orr.w r0, r0, ip 8008d5e: f093 0f00 teq r3, #0 8008d62: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008d66: bf02 ittt eq 8008d68: 0049 lsleq r1, r1, #1 8008d6a: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8008d6e: 3b01 subeq r3, #1 8008d70: d0f9 beq.n 8008d66 <__aeabi_fmul+0xe6> 8008d72: ea41 010c orr.w r1, r1, ip 8008d76: e78f b.n 8008c98 <__aeabi_fmul+0x18> 8008d78: ea0c 53d1 and.w r3, ip, r1, lsr #23 8008d7c: ea92 0f0c teq r2, ip 8008d80: bf18 it ne 8008d82: ea93 0f0c teqne r3, ip 8008d86: d00a beq.n 8008d9e <__aeabi_fmul+0x11e> 8008d88: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 8008d8c: bf18 it ne 8008d8e: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 8008d92: d1d8 bne.n 8008d46 <__aeabi_fmul+0xc6> 8008d94: ea80 0001 eor.w r0, r0, r1 8008d98: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008d9c: 4770 bx lr 8008d9e: f090 0f00 teq r0, #0 8008da2: bf17 itett ne 8008da4: f090 4f00 teqne r0, #2147483648 @ 0x80000000 8008da8: 4608 moveq r0, r1 8008daa: f091 0f00 teqne r1, #0 8008dae: f091 4f00 teqne r1, #2147483648 @ 0x80000000 8008db2: d014 beq.n 8008dde <__aeabi_fmul+0x15e> 8008db4: ea92 0f0c teq r2, ip 8008db8: d101 bne.n 8008dbe <__aeabi_fmul+0x13e> 8008dba: 0242 lsls r2, r0, #9 8008dbc: d10f bne.n 8008dde <__aeabi_fmul+0x15e> 8008dbe: ea93 0f0c teq r3, ip 8008dc2: d103 bne.n 8008dcc <__aeabi_fmul+0x14c> 8008dc4: 024b lsls r3, r1, #9 8008dc6: bf18 it ne 8008dc8: 4608 movne r0, r1 8008dca: d108 bne.n 8008dde <__aeabi_fmul+0x15e> 8008dcc: ea80 0001 eor.w r0, r0, r1 8008dd0: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008dd4: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008dd8: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008ddc: 4770 bx lr 8008dde: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008de2: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000 8008de6: 4770 bx lr 08008de8 <__aeabi_fdiv>: 8008de8: f04f 0cff mov.w ip, #255 @ 0xff 8008dec: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008df0: bf1e ittt ne 8008df2: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008df6: ea92 0f0c teqne r2, ip 8008dfa: ea93 0f0c teqne r3, ip 8008dfe: d069 beq.n 8008ed4 <__aeabi_fdiv+0xec> 8008e00: eba2 0203 sub.w r2, r2, r3 8008e04: ea80 0c01 eor.w ip, r0, r1 8008e08: 0249 lsls r1, r1, #9 8008e0a: ea4f 2040 mov.w r0, r0, lsl #9 8008e0e: d037 beq.n 8008e80 <__aeabi_fdiv+0x98> 8008e10: f04f 5380 mov.w r3, #268435456 @ 0x10000000 8008e14: ea43 1111 orr.w r1, r3, r1, lsr #4 8008e18: ea43 1310 orr.w r3, r3, r0, lsr #4 8008e1c: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008e20: 428b cmp r3, r1 8008e22: bf38 it cc 8008e24: 005b lslcc r3, r3, #1 8008e26: f142 027d adc.w r2, r2, #125 @ 0x7d 8008e2a: f44f 0c00 mov.w ip, #8388608 @ 0x800000 8008e2e: 428b cmp r3, r1 8008e30: bf24 itt cs 8008e32: 1a5b subcs r3, r3, r1 8008e34: ea40 000c orrcs.w r0, r0, ip 8008e38: ebb3 0f51 cmp.w r3, r1, lsr #1 8008e3c: bf24 itt cs 8008e3e: eba3 0351 subcs.w r3, r3, r1, lsr #1 8008e42: ea40 005c orrcs.w r0, r0, ip, lsr #1 8008e46: ebb3 0f91 cmp.w r3, r1, lsr #2 8008e4a: bf24 itt cs 8008e4c: eba3 0391 subcs.w r3, r3, r1, lsr #2 8008e50: ea40 009c orrcs.w r0, r0, ip, lsr #2 8008e54: ebb3 0fd1 cmp.w r3, r1, lsr #3 8008e58: bf24 itt cs 8008e5a: eba3 03d1 subcs.w r3, r3, r1, lsr #3 8008e5e: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8008e62: 011b lsls r3, r3, #4 8008e64: bf18 it ne 8008e66: ea5f 1c1c movsne.w ip, ip, lsr #4 8008e6a: d1e0 bne.n 8008e2e <__aeabi_fdiv+0x46> 8008e6c: 2afd cmp r2, #253 @ 0xfd 8008e6e: f63f af50 bhi.w 8008d12 <__aeabi_fmul+0x92> 8008e72: 428b cmp r3, r1 8008e74: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008e78: bf08 it eq 8008e7a: f020 0001 biceq.w r0, r0, #1 8008e7e: 4770 bx lr 8008e80: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8008e84: ea4c 2050 orr.w r0, ip, r0, lsr #9 8008e88: 327f adds r2, #127 @ 0x7f 8008e8a: bfc2 ittt gt 8008e8c: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 8008e90: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8008e94: 4770 bxgt lr 8008e96: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008e9a: f04f 0300 mov.w r3, #0 8008e9e: 3a01 subs r2, #1 8008ea0: e737 b.n 8008d12 <__aeabi_fmul+0x92> 8008ea2: f092 0f00 teq r2, #0 8008ea6: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8008eaa: bf02 ittt eq 8008eac: 0040 lsleq r0, r0, #1 8008eae: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 8008eb2: 3a01 subeq r2, #1 8008eb4: d0f9 beq.n 8008eaa <__aeabi_fdiv+0xc2> 8008eb6: ea40 000c orr.w r0, r0, ip 8008eba: f093 0f00 teq r3, #0 8008ebe: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008ec2: bf02 ittt eq 8008ec4: 0049 lsleq r1, r1, #1 8008ec6: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8008eca: 3b01 subeq r3, #1 8008ecc: d0f9 beq.n 8008ec2 <__aeabi_fdiv+0xda> 8008ece: ea41 010c orr.w r1, r1, ip 8008ed2: e795 b.n 8008e00 <__aeabi_fdiv+0x18> 8008ed4: ea0c 53d1 and.w r3, ip, r1, lsr #23 8008ed8: ea92 0f0c teq r2, ip 8008edc: d108 bne.n 8008ef0 <__aeabi_fdiv+0x108> 8008ede: 0242 lsls r2, r0, #9 8008ee0: f47f af7d bne.w 8008dde <__aeabi_fmul+0x15e> 8008ee4: ea93 0f0c teq r3, ip 8008ee8: f47f af70 bne.w 8008dcc <__aeabi_fmul+0x14c> 8008eec: 4608 mov r0, r1 8008eee: e776 b.n 8008dde <__aeabi_fmul+0x15e> 8008ef0: ea93 0f0c teq r3, ip 8008ef4: d104 bne.n 8008f00 <__aeabi_fdiv+0x118> 8008ef6: 024b lsls r3, r1, #9 8008ef8: f43f af4c beq.w 8008d94 <__aeabi_fmul+0x114> 8008efc: 4608 mov r0, r1 8008efe: e76e b.n 8008dde <__aeabi_fmul+0x15e> 8008f00: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 8008f04: bf18 it ne 8008f06: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 8008f0a: d1ca bne.n 8008ea2 <__aeabi_fdiv+0xba> 8008f0c: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000 8008f10: f47f af5c bne.w 8008dcc <__aeabi_fmul+0x14c> 8008f14: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000 8008f18: f47f af3c bne.w 8008d94 <__aeabi_fmul+0x114> 8008f1c: e75f b.n 8008dde <__aeabi_fmul+0x15e> 8008f1e: bf00 nop 08008f20 <__gesf2>: 8008f20: f04f 3cff mov.w ip, #4294967295 8008f24: e006 b.n 8008f34 <__cmpsf2+0x4> 8008f26: bf00 nop 08008f28 <__lesf2>: 8008f28: f04f 0c01 mov.w ip, #1 8008f2c: e002 b.n 8008f34 <__cmpsf2+0x4> 8008f2e: bf00 nop 08008f30 <__cmpsf2>: 8008f30: f04f 0c01 mov.w ip, #1 8008f34: f84d cd04 str.w ip, [sp, #-4]! 8008f38: ea4f 0240 mov.w r2, r0, lsl #1 8008f3c: ea4f 0341 mov.w r3, r1, lsl #1 8008f40: ea7f 6c22 mvns.w ip, r2, asr #24 8008f44: bf18 it ne 8008f46: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008f4a: d011 beq.n 8008f70 <__cmpsf2+0x40> 8008f4c: b001 add sp, #4 8008f4e: ea52 0c53 orrs.w ip, r2, r3, lsr #1 8008f52: bf18 it ne 8008f54: ea90 0f01 teqne r0, r1 8008f58: bf58 it pl 8008f5a: ebb2 0003 subspl.w r0, r2, r3 8008f5e: bf88 it hi 8008f60: 17c8 asrhi r0, r1, #31 8008f62: bf38 it cc 8008f64: ea6f 70e1 mvncc.w r0, r1, asr #31 8008f68: bf18 it ne 8008f6a: f040 0001 orrne.w r0, r0, #1 8008f6e: 4770 bx lr 8008f70: ea7f 6c22 mvns.w ip, r2, asr #24 8008f74: d102 bne.n 8008f7c <__cmpsf2+0x4c> 8008f76: ea5f 2c40 movs.w ip, r0, lsl #9 8008f7a: d105 bne.n 8008f88 <__cmpsf2+0x58> 8008f7c: ea7f 6c23 mvns.w ip, r3, asr #24 8008f80: d1e4 bne.n 8008f4c <__cmpsf2+0x1c> 8008f82: ea5f 2c41 movs.w ip, r1, lsl #9 8008f86: d0e1 beq.n 8008f4c <__cmpsf2+0x1c> 8008f88: f85d 0b04 ldr.w r0, [sp], #4 8008f8c: 4770 bx lr 8008f8e: bf00 nop 08008f90 <__aeabi_cfrcmple>: 8008f90: 4684 mov ip, r0 8008f92: 4608 mov r0, r1 8008f94: 4661 mov r1, ip 8008f96: e7ff b.n 8008f98 <__aeabi_cfcmpeq> 08008f98 <__aeabi_cfcmpeq>: 8008f98: b50f push {r0, r1, r2, r3, lr} 8008f9a: f7ff ffc9 bl 8008f30 <__cmpsf2> 8008f9e: 2800 cmp r0, #0 8008fa0: bf48 it mi 8008fa2: f110 0f00 cmnmi.w r0, #0 8008fa6: bd0f pop {r0, r1, r2, r3, pc} 08008fa8 <__aeabi_fcmpeq>: 8008fa8: f84d ed08 str.w lr, [sp, #-8]! 8008fac: f7ff fff4 bl 8008f98 <__aeabi_cfcmpeq> 8008fb0: bf0c ite eq 8008fb2: 2001 moveq r0, #1 8008fb4: 2000 movne r0, #0 8008fb6: f85d fb08 ldr.w pc, [sp], #8 8008fba: bf00 nop 08008fbc <__aeabi_fcmplt>: 8008fbc: f84d ed08 str.w lr, [sp, #-8]! 8008fc0: f7ff ffea bl 8008f98 <__aeabi_cfcmpeq> 8008fc4: bf34 ite cc 8008fc6: 2001 movcc r0, #1 8008fc8: 2000 movcs r0, #0 8008fca: f85d fb08 ldr.w pc, [sp], #8 8008fce: bf00 nop 08008fd0 <__aeabi_fcmple>: 8008fd0: f84d ed08 str.w lr, [sp, #-8]! 8008fd4: f7ff ffe0 bl 8008f98 <__aeabi_cfcmpeq> 8008fd8: bf94 ite ls 8008fda: 2001 movls r0, #1 8008fdc: 2000 movhi r0, #0 8008fde: f85d fb08 ldr.w pc, [sp], #8 8008fe2: bf00 nop 08008fe4 <__aeabi_fcmpge>: 8008fe4: f84d ed08 str.w lr, [sp, #-8]! 8008fe8: f7ff ffd2 bl 8008f90 <__aeabi_cfrcmple> 8008fec: bf94 ite ls 8008fee: 2001 movls r0, #1 8008ff0: 2000 movhi r0, #0 8008ff2: f85d fb08 ldr.w pc, [sp], #8 8008ff6: bf00 nop 08008ff8 <__aeabi_fcmpgt>: 8008ff8: f84d ed08 str.w lr, [sp, #-8]! 8008ffc: f7ff ffc8 bl 8008f90 <__aeabi_cfrcmple> 8009000: bf34 ite cc 8009002: 2001 movcc r0, #1 8009004: 2000 movcs r0, #0 8009006: f85d fb08 ldr.w pc, [sp], #8 800900a: bf00 nop 0800900c <__aeabi_f2iz>: 800900c: ea4f 0240 mov.w r2, r0, lsl #1 8009010: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000 8009014: d30f bcc.n 8009036 <__aeabi_f2iz+0x2a> 8009016: f04f 039e mov.w r3, #158 @ 0x9e 800901a: ebb3 6212 subs.w r2, r3, r2, lsr #24 800901e: d90d bls.n 800903c <__aeabi_f2iz+0x30> 8009020: ea4f 2300 mov.w r3, r0, lsl #8 8009024: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8009028: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 800902c: fa23 f002 lsr.w r0, r3, r2 8009030: bf18 it ne 8009032: 4240 negne r0, r0 8009034: 4770 bx lr 8009036: f04f 0000 mov.w r0, #0 800903a: 4770 bx lr 800903c: f112 0f61 cmn.w r2, #97 @ 0x61 8009040: d101 bne.n 8009046 <__aeabi_f2iz+0x3a> 8009042: 0242 lsls r2, r0, #9 8009044: d105 bne.n 8009052 <__aeabi_f2iz+0x46> 8009046: f010 4000 ands.w r0, r0, #2147483648 @ 0x80000000 800904a: bf08 it eq 800904c: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 8009050: 4770 bx lr 8009052: f04f 0000 mov.w r0, #0 8009056: 4770 bx lr 08009058 <__aeabi_uldivmod>: 8009058: b953 cbnz r3, 8009070 <__aeabi_uldivmod+0x18> 800905a: b94a cbnz r2, 8009070 <__aeabi_uldivmod+0x18> 800905c: 2900 cmp r1, #0 800905e: bf08 it eq 8009060: 2800 cmpeq r0, #0 8009062: bf1c itt ne 8009064: f04f 31ff movne.w r1, #4294967295 8009068: f04f 30ff movne.w r0, #4294967295 800906c: f000 b98c b.w 8009388 <__aeabi_idiv0> 8009070: f1ad 0c08 sub.w ip, sp, #8 8009074: e96d ce04 strd ip, lr, [sp, #-16]! 8009078: f000 f806 bl 8009088 <__udivmoddi4> 800907c: f8dd e004 ldr.w lr, [sp, #4] 8009080: e9dd 2302 ldrd r2, r3, [sp, #8] 8009084: b004 add sp, #16 8009086: 4770 bx lr 08009088 <__udivmoddi4>: 8009088: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800908c: 9d08 ldr r5, [sp, #32] 800908e: 468e mov lr, r1 8009090: 4604 mov r4, r0 8009092: 4688 mov r8, r1 8009094: 2b00 cmp r3, #0 8009096: d14a bne.n 800912e <__udivmoddi4+0xa6> 8009098: 428a cmp r2, r1 800909a: 4617 mov r7, r2 800909c: d962 bls.n 8009164 <__udivmoddi4+0xdc> 800909e: fab2 f682 clz r6, r2 80090a2: b14e cbz r6, 80090b8 <__udivmoddi4+0x30> 80090a4: f1c6 0320 rsb r3, r6, #32 80090a8: fa01 f806 lsl.w r8, r1, r6 80090ac: fa20 f303 lsr.w r3, r0, r3 80090b0: 40b7 lsls r7, r6 80090b2: ea43 0808 orr.w r8, r3, r8 80090b6: 40b4 lsls r4, r6 80090b8: ea4f 4e17 mov.w lr, r7, lsr #16 80090bc: fbb8 f1fe udiv r1, r8, lr 80090c0: fa1f fc87 uxth.w ip, r7 80090c4: fb0e 8811 mls r8, lr, r1, r8 80090c8: fb01 f20c mul.w r2, r1, ip 80090cc: 0c23 lsrs r3, r4, #16 80090ce: ea43 4308 orr.w r3, r3, r8, lsl #16 80090d2: 429a cmp r2, r3 80090d4: d909 bls.n 80090ea <__udivmoddi4+0x62> 80090d6: 18fb adds r3, r7, r3 80090d8: f101 30ff add.w r0, r1, #4294967295 80090dc: f080 80eb bcs.w 80092b6 <__udivmoddi4+0x22e> 80090e0: 429a cmp r2, r3 80090e2: f240 80e8 bls.w 80092b6 <__udivmoddi4+0x22e> 80090e6: 3902 subs r1, #2 80090e8: 443b add r3, r7 80090ea: 1a9a subs r2, r3, r2 80090ec: fbb2 f0fe udiv r0, r2, lr 80090f0: fb0e 2210 mls r2, lr, r0, r2 80090f4: fb00 fc0c mul.w ip, r0, ip 80090f8: b2a3 uxth r3, r4 80090fa: ea43 4302 orr.w r3, r3, r2, lsl #16 80090fe: 459c cmp ip, r3 8009100: d909 bls.n 8009116 <__udivmoddi4+0x8e> 8009102: 18fb adds r3, r7, r3 8009104: f100 32ff add.w r2, r0, #4294967295 8009108: f080 80d7 bcs.w 80092ba <__udivmoddi4+0x232> 800910c: 459c cmp ip, r3 800910e: f240 80d4 bls.w 80092ba <__udivmoddi4+0x232> 8009112: 443b add r3, r7 8009114: 3802 subs r0, #2 8009116: ea40 4001 orr.w r0, r0, r1, lsl #16 800911a: 2100 movs r1, #0 800911c: eba3 030c sub.w r3, r3, ip 8009120: b11d cbz r5, 800912a <__udivmoddi4+0xa2> 8009122: 2200 movs r2, #0 8009124: 40f3 lsrs r3, r6 8009126: e9c5 3200 strd r3, r2, [r5] 800912a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800912e: 428b cmp r3, r1 8009130: d905 bls.n 800913e <__udivmoddi4+0xb6> 8009132: b10d cbz r5, 8009138 <__udivmoddi4+0xb0> 8009134: e9c5 0100 strd r0, r1, [r5] 8009138: 2100 movs r1, #0 800913a: 4608 mov r0, r1 800913c: e7f5 b.n 800912a <__udivmoddi4+0xa2> 800913e: fab3 f183 clz r1, r3 8009142: 2900 cmp r1, #0 8009144: d146 bne.n 80091d4 <__udivmoddi4+0x14c> 8009146: 4573 cmp r3, lr 8009148: d302 bcc.n 8009150 <__udivmoddi4+0xc8> 800914a: 4282 cmp r2, r0 800914c: f200 8108 bhi.w 8009360 <__udivmoddi4+0x2d8> 8009150: 1a84 subs r4, r0, r2 8009152: eb6e 0203 sbc.w r2, lr, r3 8009156: 2001 movs r0, #1 8009158: 4690 mov r8, r2 800915a: 2d00 cmp r5, #0 800915c: d0e5 beq.n 800912a <__udivmoddi4+0xa2> 800915e: e9c5 4800 strd r4, r8, [r5] 8009162: e7e2 b.n 800912a <__udivmoddi4+0xa2> 8009164: 2a00 cmp r2, #0 8009166: f000 8091 beq.w 800928c <__udivmoddi4+0x204> 800916a: fab2 f682 clz r6, r2 800916e: 2e00 cmp r6, #0 8009170: f040 80a5 bne.w 80092be <__udivmoddi4+0x236> 8009174: 1a8a subs r2, r1, r2 8009176: 2101 movs r1, #1 8009178: 0c03 lsrs r3, r0, #16 800917a: ea4f 4e17 mov.w lr, r7, lsr #16 800917e: b280 uxth r0, r0 8009180: b2bc uxth r4, r7 8009182: fbb2 fcfe udiv ip, r2, lr 8009186: fb0e 221c mls r2, lr, ip, r2 800918a: ea43 4302 orr.w r3, r3, r2, lsl #16 800918e: fb04 f20c mul.w r2, r4, ip 8009192: 429a cmp r2, r3 8009194: d907 bls.n 80091a6 <__udivmoddi4+0x11e> 8009196: 18fb adds r3, r7, r3 8009198: f10c 38ff add.w r8, ip, #4294967295 800919c: d202 bcs.n 80091a4 <__udivmoddi4+0x11c> 800919e: 429a cmp r2, r3 80091a0: f200 80e3 bhi.w 800936a <__udivmoddi4+0x2e2> 80091a4: 46c4 mov ip, r8 80091a6: 1a9b subs r3, r3, r2 80091a8: fbb3 f2fe udiv r2, r3, lr 80091ac: fb0e 3312 mls r3, lr, r2, r3 80091b0: fb02 f404 mul.w r4, r2, r4 80091b4: ea40 4303 orr.w r3, r0, r3, lsl #16 80091b8: 429c cmp r4, r3 80091ba: d907 bls.n 80091cc <__udivmoddi4+0x144> 80091bc: 18fb adds r3, r7, r3 80091be: f102 30ff add.w r0, r2, #4294967295 80091c2: d202 bcs.n 80091ca <__udivmoddi4+0x142> 80091c4: 429c cmp r4, r3 80091c6: f200 80cd bhi.w 8009364 <__udivmoddi4+0x2dc> 80091ca: 4602 mov r2, r0 80091cc: 1b1b subs r3, r3, r4 80091ce: ea42 400c orr.w r0, r2, ip, lsl #16 80091d2: e7a5 b.n 8009120 <__udivmoddi4+0x98> 80091d4: f1c1 0620 rsb r6, r1, #32 80091d8: 408b lsls r3, r1 80091da: fa22 f706 lsr.w r7, r2, r6 80091de: 431f orrs r7, r3 80091e0: fa2e fa06 lsr.w sl, lr, r6 80091e4: ea4f 4917 mov.w r9, r7, lsr #16 80091e8: fbba f8f9 udiv r8, sl, r9 80091ec: fa0e fe01 lsl.w lr, lr, r1 80091f0: fa20 f306 lsr.w r3, r0, r6 80091f4: fb09 aa18 mls sl, r9, r8, sl 80091f8: fa1f fc87 uxth.w ip, r7 80091fc: ea43 030e orr.w r3, r3, lr 8009200: fa00 fe01 lsl.w lr, r0, r1 8009204: fb08 f00c mul.w r0, r8, ip 8009208: 0c1c lsrs r4, r3, #16 800920a: ea44 440a orr.w r4, r4, sl, lsl #16 800920e: 42a0 cmp r0, r4 8009210: fa02 f201 lsl.w r2, r2, r1 8009214: d90a bls.n 800922c <__udivmoddi4+0x1a4> 8009216: 193c adds r4, r7, r4 8009218: f108 3aff add.w sl, r8, #4294967295 800921c: f080 809e bcs.w 800935c <__udivmoddi4+0x2d4> 8009220: 42a0 cmp r0, r4 8009222: f240 809b bls.w 800935c <__udivmoddi4+0x2d4> 8009226: f1a8 0802 sub.w r8, r8, #2 800922a: 443c add r4, r7 800922c: 1a24 subs r4, r4, r0 800922e: b298 uxth r0, r3 8009230: fbb4 f3f9 udiv r3, r4, r9 8009234: fb09 4413 mls r4, r9, r3, r4 8009238: fb03 fc0c mul.w ip, r3, ip 800923c: ea40 4404 orr.w r4, r0, r4, lsl #16 8009240: 45a4 cmp ip, r4 8009242: d909 bls.n 8009258 <__udivmoddi4+0x1d0> 8009244: 193c adds r4, r7, r4 8009246: f103 30ff add.w r0, r3, #4294967295 800924a: f080 8085 bcs.w 8009358 <__udivmoddi4+0x2d0> 800924e: 45a4 cmp ip, r4 8009250: f240 8082 bls.w 8009358 <__udivmoddi4+0x2d0> 8009254: 3b02 subs r3, #2 8009256: 443c add r4, r7 8009258: ea43 4008 orr.w r0, r3, r8, lsl #16 800925c: eba4 040c sub.w r4, r4, ip 8009260: fba0 8c02 umull r8, ip, r0, r2 8009264: 4564 cmp r4, ip 8009266: 4643 mov r3, r8 8009268: 46e1 mov r9, ip 800926a: d364 bcc.n 8009336 <__udivmoddi4+0x2ae> 800926c: d061 beq.n 8009332 <__udivmoddi4+0x2aa> 800926e: b15d cbz r5, 8009288 <__udivmoddi4+0x200> 8009270: ebbe 0203 subs.w r2, lr, r3 8009274: eb64 0409 sbc.w r4, r4, r9 8009278: fa04 f606 lsl.w r6, r4, r6 800927c: fa22 f301 lsr.w r3, r2, r1 8009280: 431e orrs r6, r3 8009282: 40cc lsrs r4, r1 8009284: e9c5 6400 strd r6, r4, [r5] 8009288: 2100 movs r1, #0 800928a: e74e b.n 800912a <__udivmoddi4+0xa2> 800928c: fbb1 fcf2 udiv ip, r1, r2 8009290: 0c01 lsrs r1, r0, #16 8009292: ea41 410e orr.w r1, r1, lr, lsl #16 8009296: b280 uxth r0, r0 8009298: ea40 4201 orr.w r2, r0, r1, lsl #16 800929c: 463b mov r3, r7 800929e: fbb1 f1f7 udiv r1, r1, r7 80092a2: 4638 mov r0, r7 80092a4: 463c mov r4, r7 80092a6: 46b8 mov r8, r7 80092a8: 46be mov lr, r7 80092aa: 2620 movs r6, #32 80092ac: eba2 0208 sub.w r2, r2, r8 80092b0: ea41 410c orr.w r1, r1, ip, lsl #16 80092b4: e765 b.n 8009182 <__udivmoddi4+0xfa> 80092b6: 4601 mov r1, r0 80092b8: e717 b.n 80090ea <__udivmoddi4+0x62> 80092ba: 4610 mov r0, r2 80092bc: e72b b.n 8009116 <__udivmoddi4+0x8e> 80092be: f1c6 0120 rsb r1, r6, #32 80092c2: fa2e fc01 lsr.w ip, lr, r1 80092c6: 40b7 lsls r7, r6 80092c8: fa0e fe06 lsl.w lr, lr, r6 80092cc: fa20 f101 lsr.w r1, r0, r1 80092d0: ea41 010e orr.w r1, r1, lr 80092d4: ea4f 4e17 mov.w lr, r7, lsr #16 80092d8: fbbc f8fe udiv r8, ip, lr 80092dc: b2bc uxth r4, r7 80092de: fb0e cc18 mls ip, lr, r8, ip 80092e2: fb08 f904 mul.w r9, r8, r4 80092e6: 0c0a lsrs r2, r1, #16 80092e8: ea42 420c orr.w r2, r2, ip, lsl #16 80092ec: 40b0 lsls r0, r6 80092ee: 4591 cmp r9, r2 80092f0: ea4f 4310 mov.w r3, r0, lsr #16 80092f4: b280 uxth r0, r0 80092f6: d93e bls.n 8009376 <__udivmoddi4+0x2ee> 80092f8: 18ba adds r2, r7, r2 80092fa: f108 3cff add.w ip, r8, #4294967295 80092fe: d201 bcs.n 8009304 <__udivmoddi4+0x27c> 8009300: 4591 cmp r9, r2 8009302: d81f bhi.n 8009344 <__udivmoddi4+0x2bc> 8009304: eba2 0209 sub.w r2, r2, r9 8009308: fbb2 f9fe udiv r9, r2, lr 800930c: fb09 f804 mul.w r8, r9, r4 8009310: fb0e 2a19 mls sl, lr, r9, r2 8009314: b28a uxth r2, r1 8009316: ea42 420a orr.w r2, r2, sl, lsl #16 800931a: 4542 cmp r2, r8 800931c: d229 bcs.n 8009372 <__udivmoddi4+0x2ea> 800931e: 18ba adds r2, r7, r2 8009320: f109 31ff add.w r1, r9, #4294967295 8009324: d2c2 bcs.n 80092ac <__udivmoddi4+0x224> 8009326: 4542 cmp r2, r8 8009328: d2c0 bcs.n 80092ac <__udivmoddi4+0x224> 800932a: f1a9 0102 sub.w r1, r9, #2 800932e: 443a add r2, r7 8009330: e7bc b.n 80092ac <__udivmoddi4+0x224> 8009332: 45c6 cmp lr, r8 8009334: d29b bcs.n 800926e <__udivmoddi4+0x1e6> 8009336: ebb8 0302 subs.w r3, r8, r2 800933a: eb6c 0c07 sbc.w ip, ip, r7 800933e: 3801 subs r0, #1 8009340: 46e1 mov r9, ip 8009342: e794 b.n 800926e <__udivmoddi4+0x1e6> 8009344: eba7 0909 sub.w r9, r7, r9 8009348: 444a add r2, r9 800934a: fbb2 f9fe udiv r9, r2, lr 800934e: f1a8 0c02 sub.w ip, r8, #2 8009352: fb09 f804 mul.w r8, r9, r4 8009356: e7db b.n 8009310 <__udivmoddi4+0x288> 8009358: 4603 mov r3, r0 800935a: e77d b.n 8009258 <__udivmoddi4+0x1d0> 800935c: 46d0 mov r8, sl 800935e: e765 b.n 800922c <__udivmoddi4+0x1a4> 8009360: 4608 mov r0, r1 8009362: e6fa b.n 800915a <__udivmoddi4+0xd2> 8009364: 443b add r3, r7 8009366: 3a02 subs r2, #2 8009368: e730 b.n 80091cc <__udivmoddi4+0x144> 800936a: f1ac 0c02 sub.w ip, ip, #2 800936e: 443b add r3, r7 8009370: e719 b.n 80091a6 <__udivmoddi4+0x11e> 8009372: 4649 mov r1, r9 8009374: e79a b.n 80092ac <__udivmoddi4+0x224> 8009376: eba2 0209 sub.w r2, r2, r9 800937a: fbb2 f9fe udiv r9, r2, lr 800937e: 46c4 mov ip, r8 8009380: fb09 f804 mul.w r8, r9, r4 8009384: e7c4 b.n 8009310 <__udivmoddi4+0x288> 8009386: bf00 nop 08009388 <__aeabi_idiv0>: 8009388: 4770 bx lr 800938a: bf00 nop 0800938c : ADC_HandleTypeDef hadc1; /* ADC1 init function */ void MX_ADC1_Init(void) { 800938c: b580 push {r7, lr} 800938e: b084 sub sp, #16 8009390: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8009392: 1d3b adds r3, r7, #4 8009394: 2200 movs r2, #0 8009396: 601a str r2, [r3, #0] 8009398: 605a str r2, [r3, #4] 800939a: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 800939c: 4b18 ldr r3, [pc, #96] @ (8009400 ) 800939e: 4a19 ldr r2, [pc, #100] @ (8009404 ) 80093a0: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 80093a2: 4b17 ldr r3, [pc, #92] @ (8009400 ) 80093a4: 2200 movs r2, #0 80093a6: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = DISABLE; 80093a8: 4b15 ldr r3, [pc, #84] @ (8009400 ) 80093aa: 2200 movs r2, #0 80093ac: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 80093ae: 4b14 ldr r3, [pc, #80] @ (8009400 ) 80093b0: 2200 movs r2, #0 80093b2: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 80093b4: 4b12 ldr r3, [pc, #72] @ (8009400 ) 80093b6: f44f 2260 mov.w r2, #917504 @ 0xe0000 80093ba: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80093bc: 4b10 ldr r3, [pc, #64] @ (8009400 ) 80093be: 2200 movs r2, #0 80093c0: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 1; 80093c2: 4b0f ldr r3, [pc, #60] @ (8009400 ) 80093c4: 2201 movs r2, #1 80093c6: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 80093c8: 480d ldr r0, [pc, #52] @ (8009400 ) 80093ca: f004 faf5 bl 800d9b8 80093ce: 4603 mov r3, r0 80093d0: 2b00 cmp r3, #0 80093d2: d001 beq.n 80093d8 { Error_Handler(); 80093d4: f001 fb12 bl 800a9fc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 80093d8: 2308 movs r3, #8 80093da: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 80093dc: 2301 movs r3, #1 80093de: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 80093e0: 2300 movs r3, #0 80093e2: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80093e4: 1d3b adds r3, r7, #4 80093e6: 4619 mov r1, r3 80093e8: 4805 ldr r0, [pc, #20] @ (8009400 ) 80093ea: f004 fda9 bl 800df40 80093ee: 4603 mov r3, r0 80093f0: 2b00 cmp r3, #0 80093f2: d001 beq.n 80093f8 { Error_Handler(); 80093f4: f001 fb02 bl 800a9fc } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 80093f8: bf00 nop 80093fa: 3710 adds r7, #16 80093fc: 46bd mov sp, r7 80093fe: bd80 pop {r7, pc} 8009400: 200000f4 .word 0x200000f4 8009404: 40012400 .word 0x40012400 08009408 : void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 8009408: b580 push {r7, lr} 800940a: b08a sub sp, #40 @ 0x28 800940c: af00 add r7, sp, #0 800940e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8009410: f107 0318 add.w r3, r7, #24 8009414: 2200 movs r2, #0 8009416: 601a str r2, [r3, #0] 8009418: 605a str r2, [r3, #4] 800941a: 609a str r2, [r3, #8] 800941c: 60da str r2, [r3, #12] if(adcHandle->Instance==ADC1) 800941e: 687b ldr r3, [r7, #4] 8009420: 681b ldr r3, [r3, #0] 8009422: 4a1f ldr r2, [pc, #124] @ (80094a0 ) 8009424: 4293 cmp r3, r2 8009426: d137 bne.n 8009498 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 8009428: 4b1e ldr r3, [pc, #120] @ (80094a4 ) 800942a: 699b ldr r3, [r3, #24] 800942c: 4a1d ldr r2, [pc, #116] @ (80094a4 ) 800942e: f443 7300 orr.w r3, r3, #512 @ 0x200 8009432: 6193 str r3, [r2, #24] 8009434: 4b1b ldr r3, [pc, #108] @ (80094a4 ) 8009436: 699b ldr r3, [r3, #24] 8009438: f403 7300 and.w r3, r3, #512 @ 0x200 800943c: 617b str r3, [r7, #20] 800943e: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8009440: 4b18 ldr r3, [pc, #96] @ (80094a4 ) 8009442: 699b ldr r3, [r3, #24] 8009444: 4a17 ldr r2, [pc, #92] @ (80094a4 ) 8009446: f043 0304 orr.w r3, r3, #4 800944a: 6193 str r3, [r2, #24] 800944c: 4b15 ldr r3, [pc, #84] @ (80094a4 ) 800944e: 699b ldr r3, [r3, #24] 8009450: f003 0304 and.w r3, r3, #4 8009454: 613b str r3, [r7, #16] 8009456: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8009458: 4b12 ldr r3, [pc, #72] @ (80094a4 ) 800945a: 699b ldr r3, [r3, #24] 800945c: 4a11 ldr r2, [pc, #68] @ (80094a4 ) 800945e: f043 0308 orr.w r3, r3, #8 8009462: 6193 str r3, [r2, #24] 8009464: 4b0f ldr r3, [pc, #60] @ (80094a4 ) 8009466: 699b ldr r3, [r3, #24] 8009468: f003 0308 and.w r3, r3, #8 800946c: 60fb str r3, [r7, #12] 800946e: 68fb ldr r3, [r7, #12] PA3 ------> ADC1_IN3 PA4 ------> ADC1_IN4 PB0 ------> ADC1_IN8 PB1 ------> ADC1_IN9 */ GPIO_InitStruct.Pin = GPIO_PIN_3|CP_ADC_Pin; 8009470: 2318 movs r3, #24 8009472: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009474: 2303 movs r3, #3 8009476: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8009478: f107 0318 add.w r3, r7, #24 800947c: 4619 mov r1, r3 800947e: 480a ldr r0, [pc, #40] @ (80094a8 ) 8009480: f006 f8e2 bl 800f648 GPIO_InitStruct.Pin = ADC_NTC1_Pin|ADC_NTC2_Pin; 8009484: 2303 movs r3, #3 8009486: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009488: 2303 movs r3, #3 800948a: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800948c: f107 0318 add.w r3, r7, #24 8009490: 4619 mov r1, r3 8009492: 4806 ldr r0, [pc, #24] @ (80094ac ) 8009494: f006 f8d8 bl 800f648 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8009498: bf00 nop 800949a: 3728 adds r7, #40 @ 0x28 800949c: 46bd mov sp, r7 800949e: bd80 pop {r7, pc} 80094a0: 40012400 .word 0x40012400 80094a4: 40021000 .word 0x40021000 80094a8: 40010800 .word 0x40010800 80094ac: 40010c00 .word 0x40010c00 080094b0 : uint8_t RELAY_State[RELAY_COUNT]; static volatile uint8_t adc_lock = 0; static SMAFilter_t conn_temp_adc_filter[2]; void RELAY_Write(relay_t num, uint8_t state){ 80094b0: b580 push {r7, lr} 80094b2: b082 sub sp, #8 80094b4: af00 add r7, sp, #0 80094b6: 4603 mov r3, r0 80094b8: 460a mov r2, r1 80094ba: 71fb strb r3, [r7, #7] 80094bc: 4613 mov r3, r2 80094be: 71bb strb r3, [r7, #6] switch (num) { 80094c0: 79fb ldrb r3, [r7, #7] 80094c2: 2b07 cmp r3, #7 80094c4: d850 bhi.n 8009568 80094c6: a201 add r2, pc, #4 @ (adr r2, 80094cc ) 80094c8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80094cc: 080094ed .word 0x080094ed 80094d0: 080094fd .word 0x080094fd 80094d4: 0800950d .word 0x0800950d 80094d8: 0800951d .word 0x0800951d 80094dc: 0800952d .word 0x0800952d 80094e0: 0800953d .word 0x0800953d 80094e4: 0800954b .word 0x0800954b 80094e8: 0800955b .word 0x0800955b case RELAY_AUX0: HAL_GPIO_WritePin(RELAY1_GPIO_Port, RELAY1_Pin, state); 80094ec: 79bb ldrb r3, [r7, #6] 80094ee: 461a mov r2, r3 80094f0: f44f 7180 mov.w r1, #256 @ 0x100 80094f4: 4821 ldr r0, [pc, #132] @ (800957c ) 80094f6: f006 fa42 bl 800f97e break; 80094fa: e036 b.n 800956a case RELAY_AUX1: HAL_GPIO_WritePin(RELAY2_GPIO_Port, RELAY2_Pin, state); 80094fc: 79bb ldrb r3, [r7, #6] 80094fe: 461a mov r2, r3 8009500: f44f 7100 mov.w r1, #512 @ 0x200 8009504: 481d ldr r0, [pc, #116] @ (800957c ) 8009506: f006 fa3a bl 800f97e break; 800950a: e02e b.n 800956a case RELAY3: HAL_GPIO_WritePin(RELAY3_GPIO_Port, RELAY3_Pin, state); 800950c: 79bb ldrb r3, [r7, #6] 800950e: 461a mov r2, r3 8009510: f44f 6180 mov.w r1, #1024 @ 0x400 8009514: 4819 ldr r0, [pc, #100] @ (800957c ) 8009516: f006 fa32 bl 800f97e break; 800951a: e026 b.n 800956a case RELAY_DC: HAL_GPIO_WritePin(RELAY4_GPIO_Port, RELAY4_Pin, state); 800951c: 79bb ldrb r3, [r7, #6] 800951e: 461a mov r2, r3 8009520: f44f 6100 mov.w r1, #2048 @ 0x800 8009524: 4815 ldr r0, [pc, #84] @ (800957c ) 8009526: f006 fa2a bl 800f97e break; 800952a: e01e b.n 800956a case RELAY_AC: HAL_GPIO_WritePin(RELAY5_GPIO_Port, RELAY5_Pin, state); 800952c: 79bb ldrb r3, [r7, #6] 800952e: 461a mov r2, r3 8009530: f44f 5180 mov.w r1, #4096 @ 0x1000 8009534: 4811 ldr r0, [pc, #68] @ (800957c ) 8009536: f006 fa22 bl 800f97e break; 800953a: e016 b.n 800956a case RELAY_CP: HAL_GPIO_WritePin(RELAY_CP_GPIO_Port, RELAY_CP_Pin, state); 800953c: 79bb ldrb r3, [r7, #6] 800953e: 461a mov r2, r3 8009540: 2108 movs r1, #8 8009542: 480f ldr r0, [pc, #60] @ (8009580 ) 8009544: f006 fa1b bl 800f97e break; 8009548: e00f b.n 800956a case RELAY_CC: HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, state); 800954a: 79bb ldrb r3, [r7, #6] 800954c: 461a mov r2, r3 800954e: f44f 4100 mov.w r1, #32768 @ 0x8000 8009552: 480c ldr r0, [pc, #48] @ (8009584 ) 8009554: f006 fa13 bl 800f97e break; 8009558: e007 b.n 800956a case RELAY_DC1: HAL_GPIO_WritePin(RELAY_DC_GPIO_Port, RELAY_DC_Pin, state); 800955a: 79bb ldrb r3, [r7, #6] 800955c: 461a mov r2, r3 800955e: 2108 movs r1, #8 8009560: 4809 ldr r0, [pc, #36] @ (8009588 ) 8009562: f006 fa0c bl 800f97e break; 8009566: e000 b.n 800956a default: break; 8009568: bf00 nop } RELAY_State[num] = state; 800956a: 79fb ldrb r3, [r7, #7] 800956c: 4907 ldr r1, [pc, #28] @ (800958c ) 800956e: 79ba ldrb r2, [r7, #6] 8009570: 54ca strb r2, [r1, r3] } 8009572: bf00 nop 8009574: 3708 adds r7, #8 8009576: 46bd mov sp, r7 8009578: bd80 pop {r7, pc} 800957a: bf00 nop 800957c: 40011800 .word 0x40011800 8009580: 40011000 .word 0x40011000 8009584: 40010800 .word 0x40010800 8009588: 40011400 .word 0x40011400 800958c: 20000124 .word 0x20000124 08009590 : uint8_t RELAY_Read(relay_t num){ 8009590: b480 push {r7} 8009592: b083 sub sp, #12 8009594: af00 add r7, sp, #0 8009596: 4603 mov r3, r0 8009598: 71fb strb r3, [r7, #7] return RELAY_State[num]; 800959a: 79fb ldrb r3, [r7, #7] 800959c: 4a03 ldr r2, [pc, #12] @ (80095ac ) 800959e: 5cd3 ldrb r3, [r2, r3] } 80095a0: 4618 mov r0, r3 80095a2: 370c adds r7, #12 80095a4: 46bd mov sp, r7 80095a6: bc80 pop {r7} 80095a8: 4770 bx lr 80095aa: bf00 nop 80095ac: 20000124 .word 0x20000124 080095b0 : uint8_t IN_ReadInput(inputNum_t input_n){ 80095b0: b580 push {r7, lr} 80095b2: b082 sub sp, #8 80095b4: af00 add r7, sp, #0 80095b6: 4603 mov r3, r0 80095b8: 71fb strb r3, [r7, #7] switch(input_n){ 80095ba: 79fb ldrb r3, [r7, #7] 80095bc: 2b06 cmp r3, #6 80095be: d83b bhi.n 8009638 80095c0: a201 add r2, pc, #4 @ (adr r2, 80095c8 ) 80095c2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80095c6: bf00 nop 80095c8: 080095e5 .word 0x080095e5 80095cc: 080095f1 .word 0x080095f1 80095d0: 080095fd .word 0x080095fd 80095d4: 08009609 .word 0x08009609 80095d8: 08009615 .word 0x08009615 80095dc: 08009621 .word 0x08009621 80095e0: 0800962d .word 0x0800962d case IN_SW0: return HAL_GPIO_ReadPin(IN_SW0_GPIO_Port, IN_SW0_Pin); 80095e4: 2102 movs r1, #2 80095e6: 4817 ldr r0, [pc, #92] @ (8009644 ) 80095e8: f006 f9b2 bl 800f950 80095ec: 4603 mov r3, r0 80095ee: e024 b.n 800963a case IN_SW1: return HAL_GPIO_ReadPin(IN_SW1_GPIO_Port, IN_SW1_Pin); 80095f0: 2104 movs r1, #4 80095f2: 4814 ldr r0, [pc, #80] @ (8009644 ) 80095f4: f006 f9ac bl 800f950 80095f8: 4603 mov r3, r0 80095fa: e01e b.n 800963a case IN0: return HAL_GPIO_ReadPin(IN0_GPIO_Port, IN0_Pin); 80095fc: 2180 movs r1, #128 @ 0x80 80095fe: 4812 ldr r0, [pc, #72] @ (8009648 ) 8009600: f006 f9a6 bl 800f950 8009604: 4603 mov r3, r0 8009606: e018 b.n 800963a case IN_ESTOP: return HAL_GPIO_ReadPin(IN_ESTOP_GPIO_Port, IN_ESTOP_Pin); 8009608: 2180 movs r1, #128 @ 0x80 800960a: 4810 ldr r0, [pc, #64] @ (800964c ) 800960c: f006 f9a0 bl 800f950 8009610: 4603 mov r3, r0 8009612: e012 b.n 800963a case IN_FB1: return HAL_GPIO_ReadPin(IN_FB1_GPIO_Port, IN_FB1_Pin); 8009614: 2110 movs r1, #16 8009616: 480e ldr r0, [pc, #56] @ (8009650 ) 8009618: f006 f99a bl 800f950 800961c: 4603 mov r3, r0 800961e: e00c b.n 800963a case IN_CONT_FB_DC: return HAL_GPIO_ReadPin(IN_FB2_GPIO_Port, IN_FB2_Pin); 8009620: 2108 movs r1, #8 8009622: 480b ldr r0, [pc, #44] @ (8009650 ) 8009624: f006 f994 bl 800f950 8009628: 4603 mov r3, r0 800962a: e006 b.n 800963a case ISO_IN: return HAL_GPIO_ReadPin(ISO_IN_GPIO_Port, ISO_IN_Pin); 800962c: 2102 movs r1, #2 800962e: 4806 ldr r0, [pc, #24] @ (8009648 ) 8009630: f006 f98e bl 800f950 8009634: 4603 mov r3, r0 8009636: e000 b.n 800963a default: return 0; 8009638: 2300 movs r3, #0 } } 800963a: 4618 mov r0, r3 800963c: 3708 adds r7, #8 800963e: 46bd mov sp, r7 8009640: bd80 pop {r7, pc} 8009642: bf00 nop 8009644: 40010800 .word 0x40010800 8009648: 40011800 .word 0x40011800 800964c: 40011400 .word 0x40011400 8009650: 40010c00 .word 0x40010c00 08009654 : // // HAL_ADC_Stop(&hadc1); // stop adc return 0; } void Init_Peripheral(){ 8009654: b580 push {r7, lr} 8009656: af00 add r7, sp, #0 HAL_ADCEx_Calibration_Start(&hadc1); 8009658: 4815 ldr r0, [pc, #84] @ (80096b0 ) 800965a: f004 fe05 bl 800e268 RELAY_Write(RELAY_AUX0, 0); 800965e: 2100 movs r1, #0 8009660: 2000 movs r0, #0 8009662: f7ff ff25 bl 80094b0 RELAY_Write(RELAY_AUX1, 0); 8009666: 2100 movs r1, #0 8009668: 2001 movs r0, #1 800966a: f7ff ff21 bl 80094b0 RELAY_Write(RELAY3, 0); 800966e: 2100 movs r1, #0 8009670: 2002 movs r0, #2 8009672: f7ff ff1d bl 80094b0 RELAY_Write(RELAY_DC, 0); 8009676: 2100 movs r1, #0 8009678: 2003 movs r0, #3 800967a: f7ff ff19 bl 80094b0 RELAY_Write(RELAY_AC, 0); 800967e: 2100 movs r1, #0 8009680: 2004 movs r0, #4 8009682: f7ff ff15 bl 80094b0 RELAY_Write(RELAY_CP, 1); 8009686: 2101 movs r1, #1 8009688: 2005 movs r0, #5 800968a: f7ff ff11 bl 80094b0 RELAY_Write(RELAY_CC, 1); 800968e: 2101 movs r1, #1 8009690: 2006 movs r0, #6 8009692: f7ff ff0d bl 80094b0 RELAY_Write(RELAY_DC1, 0); 8009696: 2100 movs r1, #0 8009698: 2007 movs r0, #7 800969a: f7ff ff09 bl 80094b0 SMAFilter_Init(&conn_temp_adc_filter[0]); 800969e: 4805 ldr r0, [pc, #20] @ (80096b4 ) 80096a0: f003 fb86 bl 800cdb0 SMAFilter_Init(&conn_temp_adc_filter[1]); 80096a4: 4804 ldr r0, [pc, #16] @ (80096b8 ) 80096a6: f003 fb83 bl 800cdb0 } 80096aa: bf00 nop 80096ac: bd80 pop {r7, pc} 80096ae: bf00 nop 80096b0: 200000f4 .word 0x200000f4 80096b4: 20000130 .word 0x20000130 80096b8: 20000158 .word 0x20000158 080096bc : float pt1000_to_temperature(float resistance) { 80096bc: b590 push {r4, r7, lr} 80096be: b087 sub sp, #28 80096c0: af00 add r7, sp, #0 80096c2: 6078 str r0, [r7, #4] // Константы для PT1000 const float R0 = 1000.0; // Сопротивление при 0 °C 80096c4: 4b0c ldr r3, [pc, #48] @ (80096f8 ) 80096c6: 617b str r3, [r7, #20] const float C_A = 3.9083E-3f; 80096c8: 4b0c ldr r3, [pc, #48] @ (80096fc ) 80096ca: 613b str r3, [r7, #16] float temperature = (resistance-R0) / ( R0 * C_A); 80096cc: 6979 ldr r1, [r7, #20] 80096ce: 6878 ldr r0, [r7, #4] 80096d0: f7ff f9cc bl 8008a6c <__aeabi_fsub> 80096d4: 4603 mov r3, r0 80096d6: 461c mov r4, r3 80096d8: 6939 ldr r1, [r7, #16] 80096da: 6978 ldr r0, [r7, #20] 80096dc: f7ff fad0 bl 8008c80 <__aeabi_fmul> 80096e0: 4603 mov r3, r0 80096e2: 4619 mov r1, r3 80096e4: 4620 mov r0, r4 80096e6: f7ff fb7f bl 8008de8 <__aeabi_fdiv> 80096ea: 4603 mov r3, r0 80096ec: 60fb str r3, [r7, #12] return temperature; 80096ee: 68fb ldr r3, [r7, #12] } 80096f0: 4618 mov r0, r3 80096f2: 371c adds r7, #28 80096f4: 46bd mov sp, r7 80096f6: bd90 pop {r4, r7, pc} 80096f8: 447a0000 .word 0x447a0000 80096fc: 3b801132 .word 0x3b801132 08009700 : float calculate_NTC_resistance(int adc_value, float Vref, float Vin, float R) { 8009700: b5b0 push {r4, r5, r7, lr} 8009702: b086 sub sp, #24 8009704: af00 add r7, sp, #0 8009706: 60f8 str r0, [r7, #12] 8009708: 60b9 str r1, [r7, #8] 800970a: 607a str r2, [r7, #4] 800970c: 603b str r3, [r7, #0] // Преобразуем значение АЦП в выходное напряжение float Vout = (adc_value / 4095.0) * Vref; 800970e: 68f8 ldr r0, [r7, #12] 8009710: f7fe fedc bl 80084cc <__aeabi_i2d> 8009714: a31c add r3, pc, #112 @ (adr r3, 8009788 ) 8009716: e9d3 2300 ldrd r2, r3, [r3] 800971a: f7ff f86b bl 80087f4 <__aeabi_ddiv> 800971e: 4602 mov r2, r0 8009720: 460b mov r3, r1 8009722: 4614 mov r4, r2 8009724: 461d mov r5, r3 8009726: 68b8 ldr r0, [r7, #8] 8009728: f7fe fee2 bl 80084f0 <__aeabi_f2d> 800972c: 4602 mov r2, r0 800972e: 460b mov r3, r1 8009730: 4620 mov r0, r4 8009732: 4629 mov r1, r5 8009734: f7fe ff34 bl 80085a0 <__aeabi_dmul> 8009738: 4602 mov r2, r0 800973a: 460b mov r3, r1 800973c: 4610 mov r0, r2 800973e: 4619 mov r1, r3 8009740: f7ff f940 bl 80089c4 <__aeabi_d2f> 8009744: 4603 mov r3, r0 8009746: 617b str r3, [r7, #20] // Проверяем, чтобы Vout не было равно Vin if (Vout >= Vin) { 8009748: 6879 ldr r1, [r7, #4] 800974a: 6978 ldr r0, [r7, #20] 800974c: f7ff fc4a bl 8008fe4 <__aeabi_fcmpge> 8009750: 4603 mov r3, r0 8009752: 2b00 cmp r3, #0 8009754: d001 beq.n 800975a return -1; // Ошибка: Vout не может быть больше или равно Vin 8009756: 4b0e ldr r3, [pc, #56] @ (8009790 ) 8009758: e010 b.n 800977c } // Вычисляем сопротивление термистора float R_NTC = R * (Vout / (Vin - Vout)); 800975a: 6979 ldr r1, [r7, #20] 800975c: 6878 ldr r0, [r7, #4] 800975e: f7ff f985 bl 8008a6c <__aeabi_fsub> 8009762: 4603 mov r3, r0 8009764: 4619 mov r1, r3 8009766: 6978 ldr r0, [r7, #20] 8009768: f7ff fb3e bl 8008de8 <__aeabi_fdiv> 800976c: 4603 mov r3, r0 800976e: 4619 mov r1, r3 8009770: 6838 ldr r0, [r7, #0] 8009772: f7ff fa85 bl 8008c80 <__aeabi_fmul> 8009776: 4603 mov r3, r0 8009778: 613b str r3, [r7, #16] return R_NTC; 800977a: 693b ldr r3, [r7, #16] } 800977c: 4618 mov r0, r3 800977e: 3718 adds r7, #24 8009780: 46bd mov sp, r7 8009782: bdb0 pop {r4, r5, r7, pc} 8009784: f3af 8000 nop.w 8009788: 00000000 .word 0x00000000 800978c: 40affe00 .word 0x40affe00 8009790: bf800000 .word 0xbf800000 08009794 : int16_t CONN_ReadTemp(uint8_t ch){ 8009794: b580 push {r7, lr} 8009796: b088 sub sp, #32 8009798: af00 add r7, sp, #0 800979a: 4603 mov r3, r0 800979c: 71fb strb r3, [r7, #7] ADC_LockBlocking(); 800979e: f000 f89b bl 80098d8 //TODO if(ch)ADC_Select_Channel(ADC_CHANNEL_8); 80097a2: 79fb ldrb r3, [r7, #7] 80097a4: 2b00 cmp r3, #0 80097a6: d003 beq.n 80097b0 80097a8: 2008 movs r0, #8 80097aa: f000 f853 bl 8009854 80097ae: e002 b.n 80097b6 else ADC_Select_Channel(ADC_CHANNEL_9); 80097b0: 2009 movs r0, #9 80097b2: f000 f84f bl 8009854 // Начало конверсии HAL_ADC_Start(&hadc1); 80097b6: 4822 ldr r0, [pc, #136] @ (8009840 ) 80097b8: f004 f9d6 bl 800db68 // Ожидание окончания конверсии HAL_ADC_PollForConversion(&hadc1, HAL_MAX_DELAY); 80097bc: f04f 31ff mov.w r1, #4294967295 80097c0: 481f ldr r0, [pc, #124] @ (8009840 ) 80097c2: f004 faab bl 800dd1c // Получение значения uint32_t adcValue = HAL_ADC_GetValue(&hadc1); 80097c6: 481e ldr r0, [pc, #120] @ (8009840 ) 80097c8: f004 fbae bl 800df28 80097cc: 61f8 str r0, [r7, #28] // Остановка АЦП (по желанию) HAL_ADC_Stop(&hadc1); 80097ce: 481c ldr r0, [pc, #112] @ (8009840 ) 80097d0: f004 fa78 bl 800dcc4 int32_t adc_filtered = SMAFilter_Update(&conn_temp_adc_filter[ch ? 1u : 0u], (int32_t)adcValue); 80097d4: 79fb ldrb r3, [r7, #7] 80097d6: 2b00 cmp r3, #0 80097d8: d001 beq.n 80097de 80097da: 2201 movs r2, #1 80097dc: e000 b.n 80097e0 80097de: 2200 movs r2, #0 80097e0: 4613 mov r3, r2 80097e2: 009b lsls r3, r3, #2 80097e4: 4413 add r3, r2 80097e6: 00db lsls r3, r3, #3 80097e8: 4a16 ldr r2, [pc, #88] @ (8009844 ) 80097ea: 4413 add r3, r2 80097ec: 69fa ldr r2, [r7, #28] 80097ee: 4611 mov r1, r2 80097f0: 4618 mov r0, r3 80097f2: f003 fb02 bl 800cdfa 80097f6: 61b8 str r0, [r7, #24] if((uint32_t)adc_filtered > 4000u) { 80097f8: 69bb ldr r3, [r7, #24] 80097fa: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 80097fe: d903 bls.n 8009808 ADC_Unlock(); 8009800: f000 f876 bl 80098f0 return 20; //Термодатчик не подключен 8009804: 2314 movs r3, #20 8009806: e017 b.n 8009838 } // int adc_value = 2048; // Пример значения АЦП float Vref = 3.3; // Напряжение опорное 8009808: 4b0f ldr r3, [pc, #60] @ (8009848 ) 800980a: 617b str r3, [r7, #20] float Vin = 5.0; // Входное напряжение 800980c: 4b0f ldr r3, [pc, #60] @ (800984c ) 800980e: 613b str r3, [r7, #16] float R = 1000; // Сопротивление резистора в Омах 8009810: 4b0f ldr r3, [pc, #60] @ (8009850 ) 8009812: 60fb str r3, [r7, #12] float temp = pt1000_to_temperature(calculate_NTC_resistance((int)adc_filtered, Vref, Vin, R)); 8009814: 68fb ldr r3, [r7, #12] 8009816: 693a ldr r2, [r7, #16] 8009818: 6979 ldr r1, [r7, #20] 800981a: 69b8 ldr r0, [r7, #24] 800981c: f7ff ff70 bl 8009700 8009820: 4603 mov r3, r0 8009822: 4618 mov r0, r3 8009824: f7ff ff4a bl 80096bc 8009828: 60b8 str r0, [r7, #8] ADC_Unlock(); 800982a: f000 f861 bl 80098f0 return (int16_t)temp; 800982e: 68b8 ldr r0, [r7, #8] 8009830: f7ff fbec bl 800900c <__aeabi_f2iz> 8009834: 4603 mov r3, r0 8009836: b21b sxth r3, r3 } 8009838: 4618 mov r0, r3 800983a: 3720 adds r7, #32 800983c: 46bd mov sp, r7 800983e: bd80 pop {r7, pc} 8009840: 200000f4 .word 0x200000f4 8009844: 20000130 .word 0x20000130 8009848: 40533333 .word 0x40533333 800984c: 40a00000 .word 0x40a00000 8009850: 447a0000 .word 0x447a0000 08009854 : int16_t GBT_ReadTemp(uint8_t ch){ return CONN_ReadTemp(ch); } void ADC_Select_Channel(uint32_t ch) { 8009854: b580 push {r7, lr} 8009856: b086 sub sp, #24 8009858: af00 add r7, sp, #0 800985a: 6078 str r0, [r7, #4] ADC_ChannelConfTypeDef conf = { 800985c: 687b ldr r3, [r7, #4] 800985e: 60fb str r3, [r7, #12] 8009860: 2301 movs r3, #1 8009862: 613b str r3, [r7, #16] 8009864: 2303 movs r3, #3 8009866: 617b str r3, [r7, #20] .Channel = ch, .Rank = 1, .SamplingTime = ADC_SAMPLETIME_28CYCLES_5, }; if (HAL_ADC_ConfigChannel(&hadc1, &conf) != HAL_OK) { 8009868: f107 030c add.w r3, r7, #12 800986c: 4619 mov r1, r3 800986e: 4806 ldr r0, [pc, #24] @ (8009888 ) 8009870: f004 fb66 bl 800df40 8009874: 4603 mov r3, r0 8009876: 2b00 cmp r3, #0 8009878: d001 beq.n 800987e Error_Handler(); 800987a: f001 f8bf bl 800a9fc } } 800987e: bf00 nop 8009880: 3718 adds r7, #24 8009882: 46bd mov sp, r7 8009884: bd80 pop {r7, pc} 8009886: bf00 nop 8009888: 200000f4 .word 0x200000f4 0800988c : uint8_t ADC_TryLock(void) { 800988c: b480 push {r7} 800988e: b083 sub sp, #12 8009890: af00 add r7, sp, #0 */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8009892: f3ef 8310 mrs r3, PRIMASK 8009896: 603b str r3, [r7, #0] return(result); 8009898: 683b ldr r3, [r7, #0] uint32_t primask = __get_PRIMASK(); 800989a: 607b str r3, [r7, #4] __ASM volatile ("cpsid i" : : : "memory"); 800989c: b672 cpsid i } 800989e: bf00 nop __disable_irq(); if (adc_lock != 0u) { 80098a0: 4b0c ldr r3, [pc, #48] @ (80098d4 ) 80098a2: 781b ldrb r3, [r3, #0] 80098a4: b2db uxtb r3, r3 80098a6: 2b00 cmp r3, #0 80098a8: d006 beq.n 80098b8 if (primask == 0u) { 80098aa: 687b ldr r3, [r7, #4] 80098ac: 2b00 cmp r3, #0 80098ae: d101 bne.n 80098b4 __ASM volatile ("cpsie i" : : : "memory"); 80098b0: b662 cpsie i } 80098b2: bf00 nop __enable_irq(); } return 0u; 80098b4: 2300 movs r3, #0 80098b6: e008 b.n 80098ca } adc_lock = 1u; 80098b8: 4b06 ldr r3, [pc, #24] @ (80098d4 ) 80098ba: 2201 movs r2, #1 80098bc: 701a strb r2, [r3, #0] if (primask == 0u) { 80098be: 687b ldr r3, [r7, #4] 80098c0: 2b00 cmp r3, #0 80098c2: d101 bne.n 80098c8 __ASM volatile ("cpsie i" : : : "memory"); 80098c4: b662 cpsie i } 80098c6: bf00 nop __enable_irq(); } return 1u; 80098c8: 2301 movs r3, #1 } 80098ca: 4618 mov r0, r3 80098cc: 370c adds r7, #12 80098ce: 46bd mov sp, r7 80098d0: bc80 pop {r7} 80098d2: 4770 bx lr 80098d4: 2000012c .word 0x2000012c 080098d8 : void ADC_LockBlocking(void) { 80098d8: b580 push {r7, lr} 80098da: af00 add r7, sp, #0 while (ADC_TryLock() == 0u) { 80098dc: bf00 nop 80098de: f7ff ffd5 bl 800988c 80098e2: 4603 mov r3, r0 80098e4: 2b00 cmp r3, #0 80098e6: d0fa beq.n 80098de /* wait in main context until ADC is free */ } } 80098e8: bf00 nop 80098ea: bf00 nop 80098ec: bd80 pop {r7, pc} ... 080098f0 : void ADC_Unlock(void) { 80098f0: b480 push {r7} 80098f2: b083 sub sp, #12 80098f4: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 80098f6: f3ef 8310 mrs r3, PRIMASK 80098fa: 603b str r3, [r7, #0] return(result); 80098fc: 683b ldr r3, [r7, #0] uint32_t primask = __get_PRIMASK(); 80098fe: 607b str r3, [r7, #4] __ASM volatile ("cpsid i" : : : "memory"); 8009900: b672 cpsid i } 8009902: bf00 nop __disable_irq(); adc_lock = 0u; 8009904: 4b06 ldr r3, [pc, #24] @ (8009920 ) 8009906: 2200 movs r2, #0 8009908: 701a strb r2, [r3, #0] if (primask == 0u) { 800990a: 687b ldr r3, [r7, #4] 800990c: 2b00 cmp r3, #0 800990e: d101 bne.n 8009914 __ASM volatile ("cpsie i" : : : "memory"); 8009910: b662 cpsie i } 8009912: bf00 nop __enable_irq(); } } 8009914: bf00 nop 8009916: 370c adds r7, #12 8009918: 46bd mov sp, r7 800991a: bc80 pop {r7} 800991c: 4770 bx lr 800991e: bf00 nop 8009920: 2000012c .word 0x2000012c 08009924 : CAN_HandleTypeDef hcan1; CAN_HandleTypeDef hcan2; /* CAN1 init function */ void MX_CAN1_Init(void) { 8009924: b580 push {r7, lr} 8009926: af00 add r7, sp, #0 /* USER CODE END CAN1_Init 0 */ /* USER CODE BEGIN CAN1_Init 1 */ /* USER CODE END CAN1_Init 1 */ hcan1.Instance = CAN1; 8009928: 4b17 ldr r3, [pc, #92] @ (8009988 ) 800992a: 4a18 ldr r2, [pc, #96] @ (800998c ) 800992c: 601a str r2, [r3, #0] hcan1.Init.Prescaler = 8; 800992e: 4b16 ldr r3, [pc, #88] @ (8009988 ) 8009930: 2208 movs r2, #8 8009932: 605a str r2, [r3, #4] hcan1.Init.Mode = CAN_MODE_NORMAL; 8009934: 4b14 ldr r3, [pc, #80] @ (8009988 ) 8009936: 2200 movs r2, #0 8009938: 609a str r2, [r3, #8] hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; 800993a: 4b13 ldr r3, [pc, #76] @ (8009988 ) 800993c: 2200 movs r2, #0 800993e: 60da str r2, [r3, #12] hcan1.Init.TimeSeg1 = CAN_BS1_15TQ; 8009940: 4b11 ldr r3, [pc, #68] @ (8009988 ) 8009942: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009946: 611a str r2, [r3, #16] hcan1.Init.TimeSeg2 = CAN_BS2_2TQ; 8009948: 4b0f ldr r3, [pc, #60] @ (8009988 ) 800994a: f44f 1280 mov.w r2, #1048576 @ 0x100000 800994e: 615a str r2, [r3, #20] hcan1.Init.TimeTriggeredMode = DISABLE; 8009950: 4b0d ldr r3, [pc, #52] @ (8009988 ) 8009952: 2200 movs r2, #0 8009954: 761a strb r2, [r3, #24] hcan1.Init.AutoBusOff = ENABLE; 8009956: 4b0c ldr r3, [pc, #48] @ (8009988 ) 8009958: 2201 movs r2, #1 800995a: 765a strb r2, [r3, #25] hcan1.Init.AutoWakeUp = ENABLE; 800995c: 4b0a ldr r3, [pc, #40] @ (8009988 ) 800995e: 2201 movs r2, #1 8009960: 769a strb r2, [r3, #26] hcan1.Init.AutoRetransmission = ENABLE; 8009962: 4b09 ldr r3, [pc, #36] @ (8009988 ) 8009964: 2201 movs r2, #1 8009966: 76da strb r2, [r3, #27] hcan1.Init.ReceiveFifoLocked = DISABLE; 8009968: 4b07 ldr r3, [pc, #28] @ (8009988 ) 800996a: 2200 movs r2, #0 800996c: 771a strb r2, [r3, #28] hcan1.Init.TransmitFifoPriority = ENABLE; 800996e: 4b06 ldr r3, [pc, #24] @ (8009988 ) 8009970: 2201 movs r2, #1 8009972: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan1) != HAL_OK) 8009974: 4804 ldr r0, [pc, #16] @ (8009988 ) 8009976: f004 fd25 bl 800e3c4 800997a: 4603 mov r3, r0 800997c: 2b00 cmp r3, #0 800997e: d001 beq.n 8009984 { Error_Handler(); 8009980: f001 f83c bl 800a9fc } /* USER CODE BEGIN CAN1_Init 2 */ /* USER CODE END CAN1_Init 2 */ } 8009984: bf00 nop 8009986: bd80 pop {r7, pc} 8009988: 20000180 .word 0x20000180 800998c: 40006400 .word 0x40006400 08009990 : /* CAN2 init function */ void MX_CAN2_Init(void) { 8009990: b580 push {r7, lr} 8009992: af00 add r7, sp, #0 /* USER CODE END CAN2_Init 0 */ /* USER CODE BEGIN CAN2_Init 1 */ /* USER CODE END CAN2_Init 1 */ hcan2.Instance = CAN2; 8009994: 4b17 ldr r3, [pc, #92] @ (80099f4 ) 8009996: 4a18 ldr r2, [pc, #96] @ (80099f8 ) 8009998: 601a str r2, [r3, #0] hcan2.Init.Prescaler = 16; 800999a: 4b16 ldr r3, [pc, #88] @ (80099f4 ) 800999c: 2210 movs r2, #16 800999e: 605a str r2, [r3, #4] hcan2.Init.Mode = CAN_MODE_NORMAL; 80099a0: 4b14 ldr r3, [pc, #80] @ (80099f4 ) 80099a2: 2200 movs r2, #0 80099a4: 609a str r2, [r3, #8] hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; 80099a6: 4b13 ldr r3, [pc, #76] @ (80099f4 ) 80099a8: 2200 movs r2, #0 80099aa: 60da str r2, [r3, #12] hcan2.Init.TimeSeg1 = CAN_BS1_15TQ; 80099ac: 4b11 ldr r3, [pc, #68] @ (80099f4 ) 80099ae: f44f 2260 mov.w r2, #917504 @ 0xe0000 80099b2: 611a str r2, [r3, #16] hcan2.Init.TimeSeg2 = CAN_BS2_2TQ; 80099b4: 4b0f ldr r3, [pc, #60] @ (80099f4 ) 80099b6: f44f 1280 mov.w r2, #1048576 @ 0x100000 80099ba: 615a str r2, [r3, #20] hcan2.Init.TimeTriggeredMode = DISABLE; 80099bc: 4b0d ldr r3, [pc, #52] @ (80099f4 ) 80099be: 2200 movs r2, #0 80099c0: 761a strb r2, [r3, #24] hcan2.Init.AutoBusOff = ENABLE; 80099c2: 4b0c ldr r3, [pc, #48] @ (80099f4 ) 80099c4: 2201 movs r2, #1 80099c6: 765a strb r2, [r3, #25] hcan2.Init.AutoWakeUp = ENABLE; 80099c8: 4b0a ldr r3, [pc, #40] @ (80099f4 ) 80099ca: 2201 movs r2, #1 80099cc: 769a strb r2, [r3, #26] hcan2.Init.AutoRetransmission = ENABLE; 80099ce: 4b09 ldr r3, [pc, #36] @ (80099f4 ) 80099d0: 2201 movs r2, #1 80099d2: 76da strb r2, [r3, #27] hcan2.Init.ReceiveFifoLocked = DISABLE; 80099d4: 4b07 ldr r3, [pc, #28] @ (80099f4 ) 80099d6: 2200 movs r2, #0 80099d8: 771a strb r2, [r3, #28] hcan2.Init.TransmitFifoPriority = ENABLE; 80099da: 4b06 ldr r3, [pc, #24] @ (80099f4 ) 80099dc: 2201 movs r2, #1 80099de: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan2) != HAL_OK) 80099e0: 4804 ldr r0, [pc, #16] @ (80099f4 ) 80099e2: f004 fcef bl 800e3c4 80099e6: 4603 mov r3, r0 80099e8: 2b00 cmp r3, #0 80099ea: d001 beq.n 80099f0 { Error_Handler(); 80099ec: f001 f806 bl 800a9fc } /* USER CODE BEGIN CAN2_Init 2 */ /* USER CODE END CAN2_Init 2 */ } 80099f0: bf00 nop 80099f2: bd80 pop {r7, pc} 80099f4: 200001a8 .word 0x200001a8 80099f8: 40006800 .word 0x40006800 080099fc : static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0; void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) { 80099fc: b580 push {r7, lr} 80099fe: b08e sub sp, #56 @ 0x38 8009a00: af00 add r7, sp, #0 8009a02: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8009a04: f107 0320 add.w r3, r7, #32 8009a08: 2200 movs r2, #0 8009a0a: 601a str r2, [r3, #0] 8009a0c: 605a str r2, [r3, #4] 8009a0e: 609a str r2, [r3, #8] 8009a10: 60da str r2, [r3, #12] if(canHandle->Instance==CAN1) 8009a12: 687b ldr r3, [r7, #4] 8009a14: 681b ldr r3, [r3, #0] 8009a16: 4a61 ldr r2, [pc, #388] @ (8009b9c ) 8009a18: 4293 cmp r3, r2 8009a1a: d153 bne.n 8009ac4 { /* USER CODE BEGIN CAN1_MspInit 0 */ /* USER CODE END CAN1_MspInit 0 */ /* CAN1 clock enable */ HAL_RCC_CAN1_CLK_ENABLED++; 8009a1c: 4b60 ldr r3, [pc, #384] @ (8009ba0 ) 8009a1e: 681b ldr r3, [r3, #0] 8009a20: 3301 adds r3, #1 8009a22: 4a5f ldr r2, [pc, #380] @ (8009ba0 ) 8009a24: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009a26: 4b5e ldr r3, [pc, #376] @ (8009ba0 ) 8009a28: 681b ldr r3, [r3, #0] 8009a2a: 2b01 cmp r3, #1 8009a2c: d10b bne.n 8009a46 __HAL_RCC_CAN1_CLK_ENABLE(); 8009a2e: 4b5d ldr r3, [pc, #372] @ (8009ba4 ) 8009a30: 69db ldr r3, [r3, #28] 8009a32: 4a5c ldr r2, [pc, #368] @ (8009ba4 ) 8009a34: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009a38: 61d3 str r3, [r2, #28] 8009a3a: 4b5a ldr r3, [pc, #360] @ (8009ba4 ) 8009a3c: 69db ldr r3, [r3, #28] 8009a3e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009a42: 61fb str r3, [r7, #28] 8009a44: 69fb ldr r3, [r7, #28] } __HAL_RCC_GPIOD_CLK_ENABLE(); 8009a46: 4b57 ldr r3, [pc, #348] @ (8009ba4 ) 8009a48: 699b ldr r3, [r3, #24] 8009a4a: 4a56 ldr r2, [pc, #344] @ (8009ba4 ) 8009a4c: f043 0320 orr.w r3, r3, #32 8009a50: 6193 str r3, [r2, #24] 8009a52: 4b54 ldr r3, [pc, #336] @ (8009ba4 ) 8009a54: 699b ldr r3, [r3, #24] 8009a56: f003 0320 and.w r3, r3, #32 8009a5a: 61bb str r3, [r7, #24] 8009a5c: 69bb ldr r3, [r7, #24] /**CAN1 GPIO Configuration PD0 ------> CAN1_RX PD1 ------> CAN1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0; 8009a5e: 2301 movs r3, #1 8009a60: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009a62: 2300 movs r3, #0 8009a64: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009a66: 2300 movs r3, #0 8009a68: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009a6a: f107 0320 add.w r3, r7, #32 8009a6e: 4619 mov r1, r3 8009a70: 484d ldr r0, [pc, #308] @ (8009ba8 ) 8009a72: f005 fde9 bl 800f648 GPIO_InitStruct.Pin = GPIO_PIN_1; 8009a76: 2302 movs r3, #2 8009a78: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009a7a: 2302 movs r3, #2 8009a7c: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009a7e: 2303 movs r3, #3 8009a80: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009a82: f107 0320 add.w r3, r7, #32 8009a86: 4619 mov r1, r3 8009a88: 4847 ldr r0, [pc, #284] @ (8009ba8 ) 8009a8a: f005 fddd bl 800f648 __HAL_AFIO_REMAP_CAN1_3(); 8009a8e: 4b47 ldr r3, [pc, #284] @ (8009bac ) 8009a90: 685b ldr r3, [r3, #4] 8009a92: 633b str r3, [r7, #48] @ 0x30 8009a94: 6b3b ldr r3, [r7, #48] @ 0x30 8009a96: f423 43c0 bic.w r3, r3, #24576 @ 0x6000 8009a9a: 633b str r3, [r7, #48] @ 0x30 8009a9c: 6b3b ldr r3, [r7, #48] @ 0x30 8009a9e: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009aa2: 633b str r3, [r7, #48] @ 0x30 8009aa4: 6b3b ldr r3, [r7, #48] @ 0x30 8009aa6: f443 43c0 orr.w r3, r3, #24576 @ 0x6000 8009aaa: 633b str r3, [r7, #48] @ 0x30 8009aac: 4a3f ldr r2, [pc, #252] @ (8009bac ) 8009aae: 6b3b ldr r3, [r7, #48] @ 0x30 8009ab0: 6053 str r3, [r2, #4] /* CAN1 interrupt Init */ HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0); 8009ab2: 2200 movs r2, #0 8009ab4: 2100 movs r1, #0 8009ab6: 2014 movs r0, #20 8009ab8: f005 fc31 bl 800f31e HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn); 8009abc: 2014 movs r0, #20 8009abe: f005 fc4a bl 800f356 HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); /* USER CODE BEGIN CAN2_MspInit 1 */ /* USER CODE END CAN2_MspInit 1 */ } } 8009ac2: e067 b.n 8009b94 else if(canHandle->Instance==CAN2) 8009ac4: 687b ldr r3, [r7, #4] 8009ac6: 681b ldr r3, [r3, #0] 8009ac8: 4a39 ldr r2, [pc, #228] @ (8009bb0 ) 8009aca: 4293 cmp r3, r2 8009acc: d162 bne.n 8009b94 __HAL_RCC_CAN2_CLK_ENABLE(); 8009ace: 4b35 ldr r3, [pc, #212] @ (8009ba4 ) 8009ad0: 69db ldr r3, [r3, #28] 8009ad2: 4a34 ldr r2, [pc, #208] @ (8009ba4 ) 8009ad4: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 8009ad8: 61d3 str r3, [r2, #28] 8009ada: 4b32 ldr r3, [pc, #200] @ (8009ba4 ) 8009adc: 69db ldr r3, [r3, #28] 8009ade: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8009ae2: 617b str r3, [r7, #20] 8009ae4: 697b ldr r3, [r7, #20] HAL_RCC_CAN1_CLK_ENABLED++; 8009ae6: 4b2e ldr r3, [pc, #184] @ (8009ba0 ) 8009ae8: 681b ldr r3, [r3, #0] 8009aea: 3301 adds r3, #1 8009aec: 4a2c ldr r2, [pc, #176] @ (8009ba0 ) 8009aee: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009af0: 4b2b ldr r3, [pc, #172] @ (8009ba0 ) 8009af2: 681b ldr r3, [r3, #0] 8009af4: 2b01 cmp r3, #1 8009af6: d10b bne.n 8009b10 __HAL_RCC_CAN1_CLK_ENABLE(); 8009af8: 4b2a ldr r3, [pc, #168] @ (8009ba4 ) 8009afa: 69db ldr r3, [r3, #28] 8009afc: 4a29 ldr r2, [pc, #164] @ (8009ba4 ) 8009afe: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009b02: 61d3 str r3, [r2, #28] 8009b04: 4b27 ldr r3, [pc, #156] @ (8009ba4 ) 8009b06: 69db ldr r3, [r3, #28] 8009b08: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009b0c: 613b str r3, [r7, #16] 8009b0e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8009b10: 4b24 ldr r3, [pc, #144] @ (8009ba4 ) 8009b12: 699b ldr r3, [r3, #24] 8009b14: 4a23 ldr r2, [pc, #140] @ (8009ba4 ) 8009b16: f043 0308 orr.w r3, r3, #8 8009b1a: 6193 str r3, [r2, #24] 8009b1c: 4b21 ldr r3, [pc, #132] @ (8009ba4 ) 8009b1e: 699b ldr r3, [r3, #24] 8009b20: f003 0308 and.w r3, r3, #8 8009b24: 60fb str r3, [r7, #12] 8009b26: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_5; 8009b28: 2320 movs r3, #32 8009b2a: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009b2c: 2300 movs r3, #0 8009b2e: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009b30: 2300 movs r3, #0 8009b32: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009b34: f107 0320 add.w r3, r7, #32 8009b38: 4619 mov r1, r3 8009b3a: 481e ldr r0, [pc, #120] @ (8009bb4 ) 8009b3c: f005 fd84 bl 800f648 GPIO_InitStruct.Pin = GPIO_PIN_6; 8009b40: 2340 movs r3, #64 @ 0x40 8009b42: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009b44: 2302 movs r3, #2 8009b46: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009b48: 2303 movs r3, #3 8009b4a: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009b4c: f107 0320 add.w r3, r7, #32 8009b50: 4619 mov r1, r3 8009b52: 4818 ldr r0, [pc, #96] @ (8009bb4 ) 8009b54: f005 fd78 bl 800f648 __HAL_AFIO_REMAP_CAN2_ENABLE(); 8009b58: 4b14 ldr r3, [pc, #80] @ (8009bac ) 8009b5a: 685b ldr r3, [r3, #4] 8009b5c: 637b str r3, [r7, #52] @ 0x34 8009b5e: 6b7b ldr r3, [r7, #52] @ 0x34 8009b60: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009b64: 637b str r3, [r7, #52] @ 0x34 8009b66: 6b7b ldr r3, [r7, #52] @ 0x34 8009b68: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8009b6c: 637b str r3, [r7, #52] @ 0x34 8009b6e: 4a0f ldr r2, [pc, #60] @ (8009bac ) 8009b70: 6b7b ldr r3, [r7, #52] @ 0x34 8009b72: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(CAN2_TX_IRQn, 0, 0); 8009b74: 2200 movs r2, #0 8009b76: 2100 movs r1, #0 8009b78: 203f movs r0, #63 @ 0x3f 8009b7a: f005 fbd0 bl 800f31e HAL_NVIC_EnableIRQ(CAN2_TX_IRQn); 8009b7e: 203f movs r0, #63 @ 0x3f 8009b80: f005 fbe9 bl 800f356 HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 0, 0); 8009b84: 2200 movs r2, #0 8009b86: 2100 movs r1, #0 8009b88: 2041 movs r0, #65 @ 0x41 8009b8a: f005 fbc8 bl 800f31e HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); 8009b8e: 2041 movs r0, #65 @ 0x41 8009b90: f005 fbe1 bl 800f356 } 8009b94: bf00 nop 8009b96: 3738 adds r7, #56 @ 0x38 8009b98: 46bd mov sp, r7 8009b9a: bd80 pop {r7, pc} 8009b9c: 40006400 .word 0x40006400 8009ba0: 200001d0 .word 0x200001d0 8009ba4: 40021000 .word 0x40021000 8009ba8: 40011400 .word 0x40011400 8009bac: 40010000 .word 0x40010000 8009bb0: 40006800 .word 0x40006800 8009bb4: 40010c00 .word 0x40010c00 08009bb8 : ChargingConnector_t CONN; CONN_State_t connectorState; extern uint8_t config_initialized; void CONN_Init(){ 8009bb8: b480 push {r7} 8009bba: af00 add r7, sp, #0 CONN.connControl = CMD_NONE; 8009bbc: 4b08 ldr r3, [pc, #32] @ (8009be0 ) 8009bbe: 2200 movs r2, #0 8009bc0: 701a strb r2, [r3, #0] CONN.connState = Unknown; 8009bc2: 4b07 ldr r3, [pc, #28] @ (8009be0 ) 8009bc4: 2200 movs r2, #0 8009bc6: 705a strb r2, [r3, #1] CONN.RequestedVoltage = PSU_MIN_VOLTAGE; 8009bc8: 4b05 ldr r3, [pc, #20] @ (8009be0 ) 8009bca: 2200 movs r2, #0 8009bcc: f062 0269 orn r2, r2, #105 @ 0x69 8009bd0: 73da strb r2, [r3, #15] 8009bd2: 2200 movs r2, #0 8009bd4: 741a strb r2, [r3, #16] } 8009bd6: bf00 nop 8009bd8: 46bd mov sp, r7 8009bda: bc80 pop {r7} 8009bdc: 4770 bx lr 8009bde: bf00 nop 8009be0: 200001d4 .word 0x200001d4 08009be4 : void CONN_Loop(){ 8009be4: b580 push {r7, lr} 8009be6: af00 add r7, sp, #0 static CONN_State_t last_connState = Unknown; if(last_connState != CONN.connState){ 8009be8: 4b1a ldr r3, [pc, #104] @ (8009c54 ) 8009bea: 785a ldrb r2, [r3, #1] 8009bec: 4b1a ldr r3, [pc, #104] @ (8009c58 ) 8009bee: 781b ldrb r3, [r3, #0] 8009bf0: 429a cmp r2, r3 8009bf2: d006 beq.n 8009c02 last_connState = CONN.connState; 8009bf4: 4b17 ldr r3, [pc, #92] @ (8009c54 ) 8009bf6: 785a ldrb r2, [r3, #1] 8009bf8: 4b17 ldr r3, [pc, #92] @ (8009c58 ) 8009bfa: 701a strb r2, [r3, #0] CONN.connControl = CMD_NONE; 8009bfc: 4b15 ldr r3, [pc, #84] @ (8009c54 ) 8009bfe: 2200 movs r2, #0 8009c00: 701a strb r2, [r3, #0] } if(PSU0.cont_fault){ 8009c02: 4b16 ldr r3, [pc, #88] @ (8009c5c ) 8009c04: 7b1b ldrb r3, [r3, #12] 8009c06: 2b00 cmp r3, #0 8009c08: d003 beq.n 8009c12 CONN.chargingError = CONN_ERR_CONTACTOR; 8009c0a: 4b12 ldr r3, [pc, #72] @ (8009c54 ) 8009c0c: 2207 movs r2, #7 8009c0e: 775a strb r2, [r3, #29] 8009c10: e00e b.n 8009c30 } else if(PSU0.psu_fault){ 8009c12: 4b12 ldr r3, [pc, #72] @ (8009c5c ) 8009c14: 7b5b ldrb r3, [r3, #13] 8009c16: 2b00 cmp r3, #0 8009c18: d003 beq.n 8009c22 CONN.chargingError = CONN_ERR_PSU_FAULT; 8009c1a: 4b0e ldr r3, [pc, #56] @ (8009c54 ) 8009c1c: 220a movs r2, #10 8009c1e: 775a strb r2, [r3, #29] 8009c20: e006 b.n 8009c30 // } else if(!CTRL.ac_ok) { // CONN.chargingError = CONN_ERR_AC_FAULT; // } else }else if (CONN.EvConnected == 0){ 8009c22: 4b0c ldr r3, [pc, #48] @ (8009c54 ) 8009c24: 7f9b ldrb r3, [r3, #30] 8009c26: 2b00 cmp r3, #0 8009c28: d102 bne.n 8009c30 CONN.chargingError = CONN_NO_ERROR; 8009c2a: 4b0a ldr r3, [pc, #40] @ (8009c54 ) 8009c2c: 2200 movs r2, #0 8009c2e: 775a strb r2, [r3, #29] } if(ED_TraceWarning(CONN.chargingError, 0)) printf("CONN%d Error: %d\n", 0, CONN.chargingError); 8009c30: 4b08 ldr r3, [pc, #32] @ (8009c54 ) 8009c32: 7f5b ldrb r3, [r3, #29] 8009c34: 2100 movs r1, #0 8009c36: 4618 mov r0, r3 8009c38: f000 fd78 bl 800a72c 8009c3c: 4603 mov r3, r0 8009c3e: 2b00 cmp r3, #0 8009c40: d006 beq.n 8009c50 8009c42: 4b04 ldr r3, [pc, #16] @ (8009c54 ) 8009c44: 7f5b ldrb r3, [r3, #29] 8009c46: 461a mov r2, r3 8009c48: 2100 movs r1, #0 8009c4a: 4805 ldr r0, [pc, #20] @ (8009c60 ) 8009c4c: f009 f966 bl 8012f1c } 8009c50: bf00 nop 8009c52: bd80 pop {r7, pc} 8009c54: 200001d4 .word 0x200001d4 8009c58: 200001f4 .word 0x200001f4 8009c5c: 20000724 .word 0x20000724 8009c60: 08014004 .word 0x08014004 08009c64 : void CONN_Task(){ 8009c64: b580 push {r7, lr} 8009c66: af00 add r7, sp, #0 /* CCS state machine is handled in serial.c. * Keep this task lightweight for scheduler compatibility. */ if (CONN.chargingError != CONN_NO_ERROR) { 8009c68: 4b0f ldr r3, [pc, #60] @ (8009ca8 ) 8009c6a: 7f5b ldrb r3, [r3, #29] 8009c6c: 2b00 cmp r3, #0 8009c6e: d003 beq.n 8009c78 CONN_SetState(Disabled); 8009c70: 2002 movs r0, #2 8009c72: f000 f81f bl 8009cb4 return; 8009c76: e016 b.n 8009ca6 } if (connectorState == Unknown && config_initialized) { 8009c78: 4b0c ldr r3, [pc, #48] @ (8009cac ) 8009c7a: 781b ldrb r3, [r3, #0] 8009c7c: 2b00 cmp r3, #0 8009c7e: d107 bne.n 8009c90 8009c80: 4b0b ldr r3, [pc, #44] @ (8009cb0 ) 8009c82: 781b ldrb r3, [r3, #0] 8009c84: 2b00 cmp r3, #0 8009c86: d003 beq.n 8009c90 CONN_SetState(Unplugged); 8009c88: 2001 movs r0, #1 8009c8a: f000 f813 bl 8009cb4 8009c8e: e00a b.n 8009ca6 } else if (connectorState == Disabled && CONN.chargingError == CONN_NO_ERROR) { 8009c90: 4b06 ldr r3, [pc, #24] @ (8009cac ) 8009c92: 781b ldrb r3, [r3, #0] 8009c94: 2b02 cmp r3, #2 8009c96: d106 bne.n 8009ca6 8009c98: 4b03 ldr r3, [pc, #12] @ (8009ca8 ) 8009c9a: 7f5b ldrb r3, [r3, #29] 8009c9c: 2b00 cmp r3, #0 8009c9e: d102 bne.n 8009ca6 CONN_SetState(Unplugged); 8009ca0: 2001 movs r0, #1 8009ca2: f000 f807 bl 8009cb4 } } 8009ca6: bd80 pop {r7, pc} 8009ca8: 200001d4 .word 0x200001d4 8009cac: 200001f3 .word 0x200001f3 8009cb0: 20000ec2 .word 0x20000ec2 08009cb4 : void CONN_SetState(CONN_State_t state){ 8009cb4: b580 push {r7, lr} 8009cb6: b082 sub sp, #8 8009cb8: af00 add r7, sp, #0 8009cba: 4603 mov r3, r0 8009cbc: 71fb strb r3, [r7, #7] if (connectorState == state) { 8009cbe: 4b41 ldr r3, [pc, #260] @ (8009dc4 ) 8009cc0: 781b ldrb r3, [r3, #0] 8009cc2: 79fa ldrb r2, [r7, #7] 8009cc4: 429a cmp r2, r3 8009cc6: d103 bne.n 8009cd0 CONN.connState = state; 8009cc8: 4a3f ldr r2, [pc, #252] @ (8009dc8 ) 8009cca: 79fb ldrb r3, [r7, #7] 8009ccc: 7053 strb r3, [r2, #1] return; 8009cce: e075 b.n 8009dbc } connectorState = state; 8009cd0: 4a3c ldr r2, [pc, #240] @ (8009dc4 ) 8009cd2: 79fb ldrb r3, [r7, #7] 8009cd4: 7013 strb r3, [r2, #0] if(connectorState == Unknown) log_printf(LOG_INFO, "Connector: Unknown\n"); 8009cd6: 4b3b ldr r3, [pc, #236] @ (8009dc4 ) 8009cd8: 781b ldrb r3, [r3, #0] 8009cda: 2b00 cmp r3, #0 8009cdc: d103 bne.n 8009ce6 8009cde: 493b ldr r1, [pc, #236] @ (8009dcc ) 8009ce0: 2007 movs r0, #7 8009ce2: f000 fbcb bl 800a47c if(connectorState == Unplugged) log_printf(LOG_INFO, "Connector: Unplugged\n"); 8009ce6: 4b37 ldr r3, [pc, #220] @ (8009dc4 ) 8009ce8: 781b ldrb r3, [r3, #0] 8009cea: 2b01 cmp r3, #1 8009cec: d103 bne.n 8009cf6 8009cee: 4938 ldr r1, [pc, #224] @ (8009dd0 ) 8009cf0: 2007 movs r0, #7 8009cf2: f000 fbc3 bl 800a47c if(connectorState == Disabled) log_printf(LOG_INFO, "Connector: Disabled\n"); 8009cf6: 4b33 ldr r3, [pc, #204] @ (8009dc4 ) 8009cf8: 781b ldrb r3, [r3, #0] 8009cfa: 2b02 cmp r3, #2 8009cfc: d103 bne.n 8009d06 8009cfe: 4935 ldr r1, [pc, #212] @ (8009dd4 ) 8009d00: 2007 movs r0, #7 8009d02: f000 fbbb bl 800a47c if(connectorState == Preparing) log_printf(LOG_INFO, "Connector: Preparing\n"); 8009d06: 4b2f ldr r3, [pc, #188] @ (8009dc4 ) 8009d08: 781b ldrb r3, [r3, #0] 8009d0a: 2b03 cmp r3, #3 8009d0c: d103 bne.n 8009d16 8009d0e: 4932 ldr r1, [pc, #200] @ (8009dd8 ) 8009d10: 2007 movs r0, #7 8009d12: f000 fbb3 bl 800a47c if(connectorState == AuthRequired) log_printf(LOG_INFO, "Connector: AuthRequired\n"); 8009d16: 4b2b ldr r3, [pc, #172] @ (8009dc4 ) 8009d18: 781b ldrb r3, [r3, #0] 8009d1a: 2b04 cmp r3, #4 8009d1c: d103 bne.n 8009d26 8009d1e: 492f ldr r1, [pc, #188] @ (8009ddc ) 8009d20: 2007 movs r0, #7 8009d22: f000 fbab bl 800a47c if(connectorState == WaitingForEnergy) log_printf(LOG_INFO, "Connector: WaitingForEnergy\n"); 8009d26: 4b27 ldr r3, [pc, #156] @ (8009dc4 ) 8009d28: 781b ldrb r3, [r3, #0] 8009d2a: 2b05 cmp r3, #5 8009d2c: d103 bne.n 8009d36 8009d2e: 492c ldr r1, [pc, #176] @ (8009de0 ) 8009d30: 2007 movs r0, #7 8009d32: f000 fba3 bl 800a47c if(connectorState == ChargingPausedEV) log_printf(LOG_INFO, "Connector: ChargingPausedEV\n"); 8009d36: 4b23 ldr r3, [pc, #140] @ (8009dc4 ) 8009d38: 781b ldrb r3, [r3, #0] 8009d3a: 2b06 cmp r3, #6 8009d3c: d103 bne.n 8009d46 8009d3e: 4929 ldr r1, [pc, #164] @ (8009de4 ) 8009d40: 2007 movs r0, #7 8009d42: f000 fb9b bl 800a47c if(connectorState == ChargingPausedEVSE) log_printf(LOG_INFO, "Connector: ChargingPausedEVSE\n"); 8009d46: 4b1f ldr r3, [pc, #124] @ (8009dc4 ) 8009d48: 781b ldrb r3, [r3, #0] 8009d4a: 2b07 cmp r3, #7 8009d4c: d103 bne.n 8009d56 8009d4e: 4926 ldr r1, [pc, #152] @ (8009de8 ) 8009d50: 2007 movs r0, #7 8009d52: f000 fb93 bl 800a47c if(connectorState == Charging) log_printf(LOG_INFO, "Connector: Charging\n"); 8009d56: 4b1b ldr r3, [pc, #108] @ (8009dc4 ) 8009d58: 781b ldrb r3, [r3, #0] 8009d5a: 2b08 cmp r3, #8 8009d5c: d103 bne.n 8009d66 8009d5e: 4923 ldr r1, [pc, #140] @ (8009dec ) 8009d60: 2007 movs r0, #7 8009d62: f000 fb8b bl 800a47c if(connectorState == AuthTimeout) log_printf(LOG_INFO, "Connector: AuthTimeout\n"); 8009d66: 4b17 ldr r3, [pc, #92] @ (8009dc4 ) 8009d68: 781b ldrb r3, [r3, #0] 8009d6a: 2b09 cmp r3, #9 8009d6c: d103 bne.n 8009d76 8009d6e: 4920 ldr r1, [pc, #128] @ (8009df0 ) 8009d70: 2007 movs r0, #7 8009d72: f000 fb83 bl 800a47c if(connectorState == Finished) log_printf(LOG_INFO, "Connector: Finished\n"); 8009d76: 4b13 ldr r3, [pc, #76] @ (8009dc4 ) 8009d78: 781b ldrb r3, [r3, #0] 8009d7a: 2b0a cmp r3, #10 8009d7c: d103 bne.n 8009d86 8009d7e: 491d ldr r1, [pc, #116] @ (8009df4 ) 8009d80: 2007 movs r0, #7 8009d82: f000 fb7b bl 800a47c if(connectorState == FinishedEVSE) log_printf(LOG_INFO, "Connector: FinishedEVSE\n"); 8009d86: 4b0f ldr r3, [pc, #60] @ (8009dc4 ) 8009d88: 781b ldrb r3, [r3, #0] 8009d8a: 2b0b cmp r3, #11 8009d8c: d103 bne.n 8009d96 8009d8e: 491a ldr r1, [pc, #104] @ (8009df8 ) 8009d90: 2007 movs r0, #7 8009d92: f000 fb73 bl 800a47c if(connectorState == FinishedEV) log_printf(LOG_INFO, "Connector: FinishedEV\n"); 8009d96: 4b0b ldr r3, [pc, #44] @ (8009dc4 ) 8009d98: 781b ldrb r3, [r3, #0] 8009d9a: 2b0c cmp r3, #12 8009d9c: d103 bne.n 8009da6 8009d9e: 4917 ldr r1, [pc, #92] @ (8009dfc ) 8009da0: 2007 movs r0, #7 8009da2: f000 fb6b bl 800a47c if(connectorState == Replugging) log_printf(LOG_INFO, "Connector: Replugging\n"); 8009da6: 4b07 ldr r3, [pc, #28] @ (8009dc4 ) 8009da8: 781b ldrb r3, [r3, #0] 8009daa: 2b0d cmp r3, #13 8009dac: d103 bne.n 8009db6 8009dae: 4914 ldr r1, [pc, #80] @ (8009e00 ) 8009db0: 2007 movs r0, #7 8009db2: f000 fb63 bl 800a47c CONN.connState = state; 8009db6: 4a04 ldr r2, [pc, #16] @ (8009dc8 ) 8009db8: 79fb ldrb r3, [r7, #7] 8009dba: 7053 strb r3, [r2, #1] } 8009dbc: 3708 adds r7, #8 8009dbe: 46bd mov sp, r7 8009dc0: bd80 pop {r7, pc} 8009dc2: bf00 nop 8009dc4: 200001f3 .word 0x200001f3 8009dc8: 200001d4 .word 0x200001d4 8009dcc: 08014018 .word 0x08014018 8009dd0: 0801402c .word 0x0801402c 8009dd4: 08014044 .word 0x08014044 8009dd8: 0801405c .word 0x0801405c 8009ddc: 08014074 .word 0x08014074 8009de0: 08014090 .word 0x08014090 8009de4: 080140b0 .word 0x080140b0 8009de8: 080140d0 .word 0x080140d0 8009dec: 080140f0 .word 0x080140f0 8009df0: 08014108 .word 0x08014108 8009df4: 08014120 .word 0x08014120 8009df8: 08014138 .word 0x08014138 8009dfc: 08014154 .word 0x08014154 8009e00: 0801416c .word 0x0801416c 08009e04 : CP_State_t fake_cp_state = EV_STATE_ACQUIRING; static CP_State_t cp_stable_state = EV_STATE_ACQUIRING; static CP_State_t cp_candidate_state = EV_STATE_ACQUIRING; static uint32_t cp_candidate_since_ms = 0; static uint32_t CP_ReadAdcChannel(uint32_t ch) { 8009e04: b580 push {r7, lr} 8009e06: b084 sub sp, #16 8009e08: af00 add r7, sp, #0 8009e0a: 6078 str r0, [r7, #4] uint32_t adc = 0; 8009e0c: 2300 movs r3, #0 8009e0e: 60fb str r3, [r7, #12] ADC_Select_Channel(ch); 8009e10: 6878 ldr r0, [r7, #4] 8009e12: f7ff fd1f bl 8009854 HAL_ADC_Start(&hadc1); 8009e16: 4809 ldr r0, [pc, #36] @ (8009e3c ) 8009e18: f003 fea6 bl 800db68 HAL_ADC_PollForConversion(&hadc1, 10); 8009e1c: 210a movs r1, #10 8009e1e: 4807 ldr r0, [pc, #28] @ (8009e3c ) 8009e20: f003 ff7c bl 800dd1c adc = HAL_ADC_GetValue(&hadc1); 8009e24: 4805 ldr r0, [pc, #20] @ (8009e3c ) 8009e26: f004 f87f bl 800df28 8009e2a: 60f8 str r0, [r7, #12] HAL_ADC_Stop(&hadc1); 8009e2c: 4803 ldr r0, [pc, #12] @ (8009e3c ) 8009e2e: f003 ff49 bl 800dcc4 return adc; 8009e32: 68fb ldr r3, [r7, #12] } 8009e34: 4618 mov r0, r3 8009e36: 3710 adds r7, #16 8009e38: 46bd mov sp, r7 8009e3a: bd80 pop {r7, pc} 8009e3c: 200000f4 .word 0x200000f4 08009e40 : #define VREFINT_CAL_ADDR ((uint16_t*)0x1FFFF7BA) // для STM32F1! static uint8_t CP_IsInRange(int32_t v, int32_t lo, int32_t hi) { 8009e40: b480 push {r7} 8009e42: b085 sub sp, #20 8009e44: af00 add r7, sp, #0 8009e46: 60f8 str r0, [r7, #12] 8009e48: 60b9 str r1, [r7, #8] 8009e4a: 607a str r2, [r7, #4] return (v >= lo && v <= hi) ? 1u : 0u; 8009e4c: 68fa ldr r2, [r7, #12] 8009e4e: 68bb ldr r3, [r7, #8] 8009e50: 429a cmp r2, r3 8009e52: db05 blt.n 8009e60 8009e54: 68fa ldr r2, [r7, #12] 8009e56: 687b ldr r3, [r7, #4] 8009e58: 429a cmp r2, r3 8009e5a: dc01 bgt.n 8009e60 8009e5c: 2301 movs r3, #1 8009e5e: e000 b.n 8009e62 8009e60: 2300 movs r3, #0 } 8009e62: 4618 mov r0, r3 8009e64: 3714 adds r7, #20 8009e66: 46bd mov sp, r7 8009e68: bc80 pop {r7} 8009e6a: 4770 bx lr 08009e6c : static int32_t CP_ApplyEma(int32_t raw_mv) { 8009e6c: b480 push {r7} 8009e6e: b083 sub sp, #12 8009e70: af00 add r7, sp, #0 8009e72: 6078 str r0, [r7, #4] if (!cp_filter_initialized) { 8009e74: 4b12 ldr r3, [pc, #72] @ (8009ec0 ) 8009e76: 781b ldrb r3, [r3, #0] 8009e78: 2b00 cmp r3, #0 8009e7a: d108 bne.n 8009e8e cp_voltage_filt_mv = raw_mv; 8009e7c: 4a11 ldr r2, [pc, #68] @ (8009ec4 ) 8009e7e: 687b ldr r3, [r7, #4] 8009e80: 6013 str r3, [r2, #0] cp_filter_initialized = 1; 8009e82: 4b0f ldr r3, [pc, #60] @ (8009ec0 ) 8009e84: 2201 movs r2, #1 8009e86: 701a strb r2, [r3, #0] return cp_voltage_filt_mv; 8009e88: 4b0e ldr r3, [pc, #56] @ (8009ec4 ) 8009e8a: 681b ldr r3, [r3, #0] 8009e8c: e012 b.n 8009eb4 } cp_voltage_filt_mv += ((raw_mv - cp_voltage_filt_mv) * CP_EMA_ALPHA_Q8) / 256; 8009e8e: 4b0d ldr r3, [pc, #52] @ (8009ec4 ) 8009e90: 681b ldr r3, [r3, #0] 8009e92: 687a ldr r2, [r7, #4] 8009e94: 1ad3 subs r3, r2, r3 8009e96: 2226 movs r2, #38 @ 0x26 8009e98: fb02 f303 mul.w r3, r2, r3 8009e9c: 2b00 cmp r3, #0 8009e9e: da00 bge.n 8009ea2 8009ea0: 33ff adds r3, #255 @ 0xff 8009ea2: 121b asrs r3, r3, #8 8009ea4: 461a mov r2, r3 8009ea6: 4b07 ldr r3, [pc, #28] @ (8009ec4 ) 8009ea8: 681b ldr r3, [r3, #0] 8009eaa: 4413 add r3, r2 8009eac: 4a05 ldr r2, [pc, #20] @ (8009ec4 ) 8009eae: 6013 str r3, [r2, #0] return cp_voltage_filt_mv; 8009eb0: 4b04 ldr r3, [pc, #16] @ (8009ec4 ) 8009eb2: 681b ldr r3, [r3, #0] } 8009eb4: 4618 mov r0, r3 8009eb6: 370c adds r7, #12 8009eb8: 46bd mov sp, r7 8009eba: bc80 pop {r7} 8009ebc: 4770 bx lr 8009ebe: bf00 nop 8009ec0: 20000200 .word 0x20000200 8009ec4: 200001fc .word 0x200001fc 08009ec8 : static CP_State_t CP_ClassifyWithHysteresis(int32_t v, CP_State_t prev) { 8009ec8: b580 push {r7, lr} 8009eca: b082 sub sp, #8 8009ecc: af00 add r7, sp, #0 8009ece: 6078 str r0, [r7, #4] 8009ed0: 460b mov r3, r1 8009ed2: 70fb strb r3, [r7, #3] switch (prev) { 8009ed4: 78fb ldrb r3, [r7, #3] 8009ed6: 2b05 cmp r3, #5 8009ed8: d84a bhi.n 8009f70 8009eda: a201 add r2, pc, #4 @ (adr r2, 8009ee0 ) 8009edc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009ee0: 08009ef9 .word 0x08009ef9 8009ee4: 08009f07 .word 0x08009f07 8009ee8: 08009f1f .word 0x08009f1f 8009eec: 08009f37 .word 0x08009f37 8009ef0: 08009f4f .word 0x08009f4f 8009ef4: 08009f65 .word 0x08009f65 case EV_STATE_A_IDLE: if (v >= CP_A_EXIT_MV) return EV_STATE_A_IDLE; 8009ef8: 687b ldr r3, [r7, #4] 8009efa: f242 720f movw r2, #9999 @ 0x270f 8009efe: 4293 cmp r3, r2 8009f00: dd38 ble.n 8009f74 8009f02: 2300 movs r3, #0 8009f04: e07e b.n 800a004 break; case EV_STATE_B_CONN_PREP: if (CP_IsInRange(v, CP_B_EXIT_LOW_MV, CP_B_EXIT_HIGH_MV)) return EV_STATE_B_CONN_PREP; 8009f06: f642 1204 movw r2, #10500 @ 0x2904 8009f0a: f641 514c movw r1, #7500 @ 0x1d4c 8009f0e: 6878 ldr r0, [r7, #4] 8009f10: f7ff ff96 bl 8009e40 8009f14: 4603 mov r3, r0 8009f16: 2b00 cmp r3, #0 8009f18: d02e beq.n 8009f78 8009f1a: 2301 movs r3, #1 8009f1c: e072 b.n 800a004 break; case EV_STATE_C_CONN_ACTIVE: if (CP_IsInRange(v, CP_C_EXIT_LOW_MV, CP_C_EXIT_HIGH_MV)) return EV_STATE_C_CONN_ACTIVE; 8009f1e: f641 524c movw r2, #7500 @ 0x1d4c 8009f22: f241 1194 movw r1, #4500 @ 0x1194 8009f26: 6878 ldr r0, [r7, #4] 8009f28: f7ff ff8a bl 8009e40 8009f2c: 4603 mov r3, r0 8009f2e: 2b00 cmp r3, #0 8009f30: d024 beq.n 8009f7c 8009f32: 2302 movs r3, #2 8009f34: e066 b.n 800a004 break; case EV_STATE_D_CONN_ACT_VENT: if (CP_IsInRange(v, CP_D_EXIT_LOW_MV, CP_D_EXIT_HIGH_MV)) return EV_STATE_D_CONN_ACT_VENT; 8009f36: f241 1294 movw r2, #4500 @ 0x1194 8009f3a: f240 51dc movw r1, #1500 @ 0x5dc 8009f3e: 6878 ldr r0, [r7, #4] 8009f40: f7ff ff7e bl 8009e40 8009f44: 4603 mov r3, r0 8009f46: 2b00 cmp r3, #0 8009f48: d01a beq.n 8009f80 8009f4a: 2303 movs r3, #3 8009f4c: e05a b.n 800a004 break; case EV_STATE_E_NO_POWER: if (CP_IsInRange(v, CP_E_EXIT_LOW_MV, CP_E_EXIT_HIGH_MV)) return EV_STATE_E_NO_POWER; 8009f4e: f640 12c4 movw r2, #2500 @ 0x9c4 8009f52: 492e ldr r1, [pc, #184] @ (800a00c ) 8009f54: 6878 ldr r0, [r7, #4] 8009f56: f7ff ff73 bl 8009e40 8009f5a: 4603 mov r3, r0 8009f5c: 2b00 cmp r3, #0 8009f5e: d011 beq.n 8009f84 8009f60: 2304 movs r3, #4 8009f62: e04f b.n 800a004 break; case EV_STATE_F_ERROR: if (v <= CP_F_EXIT_MV) return EV_STATE_F_ERROR; 8009f64: 687b ldr r3, [r7, #4] 8009f66: 4a2a ldr r2, [pc, #168] @ (800a010 ) 8009f68: 4293 cmp r3, r2 8009f6a: da0d bge.n 8009f88 8009f6c: 2305 movs r3, #5 8009f6e: e049 b.n 800a004 break; default: break; 8009f70: bf00 nop 8009f72: e00a b.n 8009f8a break; 8009f74: bf00 nop 8009f76: e008 b.n 8009f8a break; 8009f78: bf00 nop 8009f7a: e006 b.n 8009f8a break; 8009f7c: bf00 nop 8009f7e: e004 b.n 8009f8a break; 8009f80: bf00 nop 8009f82: e002 b.n 8009f8a break; 8009f84: bf00 nop 8009f86: e000 b.n 8009f8a break; 8009f88: bf00 nop } if (v >= CP_A_ENTER_MV) return EV_STATE_A_IDLE; 8009f8a: 687b ldr r3, [r7, #4] 8009f8c: f642 22f7 movw r2, #10999 @ 0x2af7 8009f90: 4293 cmp r3, r2 8009f92: dd01 ble.n 8009f98 8009f94: 2300 movs r3, #0 8009f96: e035 b.n 800a004 if (CP_IsInRange(v, CP_B_ENTER_LOW_MV, CP_B_ENTER_HIGH_MV)) return EV_STATE_B_CONN_PREP; 8009f98: f242 7210 movw r2, #10000 @ 0x2710 8009f9c: f44f 51fa mov.w r1, #8000 @ 0x1f40 8009fa0: 6878 ldr r0, [r7, #4] 8009fa2: f7ff ff4d bl 8009e40 8009fa6: 4603 mov r3, r0 8009fa8: 2b00 cmp r3, #0 8009faa: d001 beq.n 8009fb0 8009fac: 2301 movs r3, #1 8009fae: e029 b.n 800a004 if (CP_IsInRange(v, CP_C_ENTER_LOW_MV, CP_C_ENTER_HIGH_MV)) return EV_STATE_C_CONN_ACTIVE; 8009fb0: f641 3258 movw r2, #7000 @ 0x1b58 8009fb4: f241 3188 movw r1, #5000 @ 0x1388 8009fb8: 6878 ldr r0, [r7, #4] 8009fba: f7ff ff41 bl 8009e40 8009fbe: 4603 mov r3, r0 8009fc0: 2b00 cmp r3, #0 8009fc2: d001 beq.n 8009fc8 8009fc4: 2302 movs r3, #2 8009fc6: e01d b.n 800a004 if (CP_IsInRange(v, CP_D_ENTER_LOW_MV, CP_D_ENTER_HIGH_MV)) return EV_STATE_D_CONN_ACT_VENT; 8009fc8: f44f 627a mov.w r2, #4000 @ 0xfa0 8009fcc: f44f 61fa mov.w r1, #2000 @ 0x7d0 8009fd0: 6878 ldr r0, [r7, #4] 8009fd2: f7ff ff35 bl 8009e40 8009fd6: 4603 mov r3, r0 8009fd8: 2b00 cmp r3, #0 8009fda: d001 beq.n 8009fe0 8009fdc: 2303 movs r3, #3 8009fde: e011 b.n 800a004 if (CP_IsInRange(v, CP_E_ENTER_LOW_MV, CP_E_ENTER_HIGH_MV)) return EV_STATE_E_NO_POWER; 8009fe0: f44f 62fa mov.w r2, #2000 @ 0x7d0 8009fe4: 490b ldr r1, [pc, #44] @ (800a014 ) 8009fe6: 6878 ldr r0, [r7, #4] 8009fe8: f7ff ff2a bl 8009e40 8009fec: 4603 mov r3, r0 8009fee: 2b00 cmp r3, #0 8009ff0: d001 beq.n 8009ff6 8009ff2: 2304 movs r3, #4 8009ff4: e006 b.n 800a004 if (v <= CP_F_ENTER_MV) return EV_STATE_F_ERROR; 8009ff6: 687b ldr r3, [r7, #4] 8009ff8: 4a07 ldr r2, [pc, #28] @ (800a018 ) 8009ffa: 4293 cmp r3, r2 8009ffc: da01 bge.n 800a002 8009ffe: 2305 movs r3, #5 800a000: e000 b.n 800a004 return EV_STATE_ACQUIRING; 800a002: 2306 movs r3, #6 } 800a004: 4618 mov r0, r3 800a006: 3708 adds r7, #8 800a008: 46bd mov sp, r7 800a00a: bd80 pop {r7, pc} 800a00c: fffffa24 .word 0xfffffa24 800a010: ffffd6fd .word 0xffffd6fd 800a014: fffffc18 .word 0xfffffc18 800a018: ffffd315 .word 0xffffd315 0800a01c : static uint32_t CP_GetDebounceMs(CP_State_t next_state) { 800a01c: b480 push {r7} 800a01e: b083 sub sp, #12 800a020: af00 add r7, sp, #0 800a022: 4603 mov r3, r0 800a024: 71fb strb r3, [r7, #7] if (next_state == EV_STATE_F_ERROR) { 800a026: 79fb ldrb r3, [r7, #7] 800a028: 2b05 cmp r3, #5 800a02a: d107 bne.n 800a03c if (cp_duty <= CP_LOW_DUTY_THRESHOLD_PERCENT) { 800a02c: 4b06 ldr r3, [pc, #24] @ (800a048 ) 800a02e: 781b ldrb r3, [r3, #0] 800a030: 2b0a cmp r3, #10 800a032: d801 bhi.n 800a038 return CP_DEBOUNCE_MS_F_LOW_DUTY; 800a034: 2364 movs r3, #100 @ 0x64 800a036: e002 b.n 800a03e } return CP_DEBOUNCE_MS_F; 800a038: 233c movs r3, #60 @ 0x3c 800a03a: e000 b.n 800a03e } return CP_DEBOUNCE_MS_DEFAULT; 800a03c: 230a movs r3, #10 } 800a03e: 4618 mov r0, r3 800a040: 370c adds r7, #12 800a042: 46bd mov sp, r7 800a044: bc80 pop {r7} 800a046: 4770 bx lr 800a048: 20000201 .word 0x20000201 0800a04c : static int32_t CP_ReadVoltageMv(void) { 800a04c: b580 push {r7, lr} 800a04e: b084 sub sp, #16 800a050: af00 add r7, sp, #0 uint32_t adc = 0; 800a052: 2300 movs r3, #0 800a054: 60fb str r3, [r7, #12] int32_t v_adc_mv = 0; 800a056: 2300 movs r3, #0 800a058: 60bb str r3, [r7, #8] int32_t v_out_mv = 0; 800a05a: 2300 movs r3, #0 800a05c: 607b str r3, [r7, #4] adc = CP_ReadAdcChannel((uint32_t)4u); 800a05e: 2004 movs r0, #4 800a060: f7ff fed0 bl 8009e04 800a064: 60f8 str r0, [r7, #12] v_adc_mv = (int32_t)((adc * 3300u) / 4095u); 800a066: 68fb ldr r3, [r7, #12] 800a068: f640 42e4 movw r2, #3300 @ 0xce4 800a06c: fb03 f202 mul.w r2, r3, r2 800a070: 4b0d ldr r3, [pc, #52] @ (800a0a8 ) 800a072: fba3 1302 umull r1, r3, r3, r2 800a076: 1ad2 subs r2, r2, r3 800a078: 0852 lsrs r2, r2, #1 800a07a: 4413 add r3, r2 800a07c: 0adb lsrs r3, r3, #11 800a07e: 60bb str r3, [r7, #8] v_out_mv = ((v_adc_mv - 1723) * 1000) / 130; 800a080: 68bb ldr r3, [r7, #8] 800a082: f2a3 63bb subw r3, r3, #1723 @ 0x6bb 800a086: f44f 727a mov.w r2, #1000 @ 0x3e8 800a08a: fb02 f303 mul.w r3, r2, r3 800a08e: 4a07 ldr r2, [pc, #28] @ (800a0ac ) 800a090: fb82 1203 smull r1, r2, r2, r3 800a094: 1192 asrs r2, r2, #6 800a096: 17db asrs r3, r3, #31 800a098: 1ad3 subs r3, r2, r3 800a09a: 607b str r3, [r7, #4] return v_out_mv; 800a09c: 687b ldr r3, [r7, #4] } 800a09e: 4618 mov r0, r3 800a0a0: 3710 adds r7, #16 800a0a2: 46bd mov sp, r7 800a0a4: bd80 pop {r7, pc} 800a0a6: bf00 nop 800a0a8: 00100101 .word 0x00100101 800a0ac: 7e07e07f .word 0x7e07e07f 0800a0b0 : void CP_Init(void) { 800a0b0: b580 push {r7, lr} 800a0b2: af00 add r7, sp, #0 /* TIM3_CH2 (PA7): set 1kHz PWM like original CCS logic. */ htim3.Instance->PSC = 160 - 1; 800a0b4: 4b0e ldr r3, [pc, #56] @ (800a0f0 ) 800a0b6: 681b ldr r3, [r3, #0] 800a0b8: 229f movs r2, #159 @ 0x9f 800a0ba: 629a str r2, [r3, #40] @ 0x28 htim3.Instance->ARR = MAX_DUTY - 1; 800a0bc: 4b0c ldr r3, [pc, #48] @ (800a0f0 ) 800a0be: 681b ldr r3, [r3, #0] 800a0c0: f240 12c1 movw r2, #449 @ 0x1c1 800a0c4: 62da str r2, [r3, #44] @ 0x2c #if DUTY_INVERT == 0 htim3.Instance->CCR2 = MAX_DUTY; 800a0c6: 4b0a ldr r3, [pc, #40] @ (800a0f0 ) 800a0c8: 681b ldr r3, [r3, #0] 800a0ca: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a0ce: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = MAX_DUTY + 5; 800a0d0: 4b07 ldr r3, [pc, #28] @ (800a0f0 ) 800a0d2: 681b ldr r3, [r3, #0] 800a0d4: f240 12c7 movw r2, #455 @ 0x1c7 800a0d8: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = 0; htim3.Instance->CCR1 = 0; #endif HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_2); 800a0da: 2104 movs r1, #4 800a0dc: 4804 ldr r0, [pc, #16] @ (800a0f0 ) 800a0de: f006 ff79 bl 8010fd4 HAL_TIM_OC_Start_IT(&htim3, TIM_CHANNEL_1); 800a0e2: 2100 movs r1, #0 800a0e4: 4802 ldr r0, [pc, #8] @ (800a0f0 ) 800a0e6: f006 fe27 bl 8010d38 } 800a0ea: bf00 nop 800a0ec: bd80 pop {r7, pc} 800a0ee: bf00 nop 800a0f0: 20000ec8 .word 0x20000ec8 0800a0f4 : void CP_SetDuty(uint8_t percentage) { 800a0f4: b480 push {r7} 800a0f6: b085 sub sp, #20 800a0f8: af00 add r7, sp, #0 800a0fa: 4603 mov r3, r0 800a0fc: 71fb strb r3, [r7, #7] uint32_t pwmduty = MAX_DUTY * percentage / 100; 800a0fe: 79fb ldrb r3, [r7, #7] 800a100: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a104: fb02 f303 mul.w r3, r2, r3 800a108: 4a0b ldr r2, [pc, #44] @ (800a138 ) 800a10a: fb82 1203 smull r1, r2, r2, r3 800a10e: 1152 asrs r2, r2, #5 800a110: 17db asrs r3, r3, #31 800a112: 1ad3 subs r3, r2, r3 800a114: 60fb str r3, [r7, #12] cp_duty = percentage; 800a116: 4a09 ldr r2, [pc, #36] @ (800a13c ) 800a118: 79fb ldrb r3, [r7, #7] 800a11a: 7013 strb r3, [r2, #0] #if DUTY_INVERT == 0 htim3.Instance->CCR2 = pwmduty; 800a11c: 4b08 ldr r3, [pc, #32] @ (800a140 ) 800a11e: 681b ldr r3, [r3, #0] 800a120: 68fa ldr r2, [r7, #12] 800a122: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = 0 + 1; 800a124: 4b06 ldr r3, [pc, #24] @ (800a140 ) 800a126: 681b ldr r3, [r3, #0] 800a128: 2201 movs r2, #1 800a12a: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = MAX_DUTY - pwmduty; htim3.Instance->CCR1 = MAX_DUTY - pwmduty + 5; #endif } 800a12c: bf00 nop 800a12e: 3714 adds r7, #20 800a130: 46bd mov sp, r7 800a132: bc80 pop {r7} 800a134: 4770 bx lr 800a136: bf00 nop 800a138: 51eb851f .word 0x51eb851f 800a13c: 20000201 .word 0x20000201 800a140: 20000ec8 .word 0x20000ec8 0800a144 : uint8_t CP_GetDuty(void) { 800a144: b480 push {r7} 800a146: af00 add r7, sp, #0 return cp_duty; 800a148: 4b02 ldr r3, [pc, #8] @ (800a154 ) 800a14a: 781b ldrb r3, [r3, #0] } 800a14c: 4618 mov r0, r3 800a14e: 46bd mov sp, r7 800a150: bc80 pop {r7} 800a152: 4770 bx lr 800a154: 20000201 .word 0x20000201 0800a158 : int32_t CP_GetVoltage(void) { return cp_voltage_mv; } CP_State_t CP_GetState(void) { 800a158: b590 push {r4, r7, lr} 800a15a: b085 sub sp, #20 800a15c: af00 add r7, sp, #0 int32_t voltage_real = cp_voltage_filt_mv; 800a15e: 4b22 ldr r3, [pc, #136] @ (800a1e8 ) 800a160: 681b ldr r3, [r3, #0] 800a162: 60fb str r3, [r7, #12] uint32_t now = HAL_GetTick(); 800a164: f003 fbfa bl 800d95c 800a168: 60b8 str r0, [r7, #8] if(fake_cp_state != EV_STATE_ACQUIRING) { 800a16a: 4b20 ldr r3, [pc, #128] @ (800a1ec ) 800a16c: 781b ldrb r3, [r3, #0] 800a16e: 2b06 cmp r3, #6 800a170: d002 beq.n 800a178 return fake_cp_state; 800a172: 4b1e ldr r3, [pc, #120] @ (800a1ec ) 800a174: 781b ldrb r3, [r3, #0] 800a176: e032 b.n 800a1de } CP_State_t instant_state = CP_ClassifyWithHysteresis(voltage_real, cp_stable_state); 800a178: 4b1d ldr r3, [pc, #116] @ (800a1f0 ) 800a17a: 781b ldrb r3, [r3, #0] 800a17c: 4619 mov r1, r3 800a17e: 68f8 ldr r0, [r7, #12] 800a180: f7ff fea2 bl 8009ec8 800a184: 4603 mov r3, r0 800a186: 71fb strb r3, [r7, #7] if (instant_state == cp_stable_state) { 800a188: 4b19 ldr r3, [pc, #100] @ (800a1f0 ) 800a18a: 781b ldrb r3, [r3, #0] 800a18c: 79fa ldrb r2, [r7, #7] 800a18e: 429a cmp r2, r3 800a190: d107 bne.n 800a1a2 cp_candidate_state = cp_stable_state; 800a192: 4b17 ldr r3, [pc, #92] @ (800a1f0 ) 800a194: 781a ldrb r2, [r3, #0] 800a196: 4b17 ldr r3, [pc, #92] @ (800a1f4 ) 800a198: 701a strb r2, [r3, #0] cp_candidate_since_ms = now; 800a19a: 4a17 ldr r2, [pc, #92] @ (800a1f8 ) 800a19c: 68bb ldr r3, [r7, #8] 800a19e: 6013 str r3, [r2, #0] 800a1a0: e01b b.n 800a1da } else { if (cp_candidate_state != instant_state) { 800a1a2: 4b14 ldr r3, [pc, #80] @ (800a1f4 ) 800a1a4: 781b ldrb r3, [r3, #0] 800a1a6: 79fa ldrb r2, [r7, #7] 800a1a8: 429a cmp r2, r3 800a1aa: d006 beq.n 800a1ba cp_candidate_state = instant_state; 800a1ac: 4a11 ldr r2, [pc, #68] @ (800a1f4 ) 800a1ae: 79fb ldrb r3, [r7, #7] 800a1b0: 7013 strb r3, [r2, #0] cp_candidate_since_ms = now; 800a1b2: 4a11 ldr r2, [pc, #68] @ (800a1f8 ) 800a1b4: 68bb ldr r3, [r7, #8] 800a1b6: 6013 str r3, [r2, #0] 800a1b8: e00f b.n 800a1da } else if ((now - cp_candidate_since_ms) >= CP_GetDebounceMs(cp_candidate_state)) { 800a1ba: 4b0f ldr r3, [pc, #60] @ (800a1f8 ) 800a1bc: 681b ldr r3, [r3, #0] 800a1be: 68ba ldr r2, [r7, #8] 800a1c0: 1ad4 subs r4, r2, r3 800a1c2: 4b0c ldr r3, [pc, #48] @ (800a1f4 ) 800a1c4: 781b ldrb r3, [r3, #0] 800a1c6: 4618 mov r0, r3 800a1c8: f7ff ff28 bl 800a01c 800a1cc: 4603 mov r3, r0 800a1ce: 429c cmp r4, r3 800a1d0: d303 bcc.n 800a1da cp_stable_state = cp_candidate_state; 800a1d2: 4b08 ldr r3, [pc, #32] @ (800a1f4 ) 800a1d4: 781a ldrb r2, [r3, #0] 800a1d6: 4b06 ldr r3, [pc, #24] @ (800a1f0 ) 800a1d8: 701a strb r2, [r3, #0] } } return cp_stable_state; 800a1da: 4b05 ldr r3, [pc, #20] @ (800a1f0 ) 800a1dc: 781b ldrb r3, [r3, #0] } 800a1de: 4618 mov r0, r3 800a1e0: 3714 adds r7, #20 800a1e2: 46bd mov sp, r7 800a1e4: bd90 pop {r4, r7, pc} 800a1e6: bf00 nop 800a1e8: 200001fc .word 0x200001fc 800a1ec: 20000004 .word 0x20000004 800a1f0: 20000005 .word 0x20000005 800a1f4: 20000006 .word 0x20000006 800a1f8: 20000204 .word 0x20000204 0800a1fc : void CP_Loop(void) { (void)CP_GetState(); } void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 800a1fc: b580 push {r7, lr} 800a1fe: b082 sub sp, #8 800a200: af00 add r7, sp, #0 800a202: 6078 str r0, [r7, #4] if (htim->Instance == TIM3 && htim->Channel == HAL_TIM_ACTIVE_CHANNEL_1) { 800a204: 687b ldr r3, [r7, #4] 800a206: 681b ldr r3, [r3, #0] 800a208: 4a0e ldr r2, [pc, #56] @ (800a244 ) 800a20a: 4293 cmp r3, r2 800a20c: d116 bne.n 800a23c 800a20e: 687b ldr r3, [r7, #4] 800a210: 7f1b ldrb r3, [r3, #28] 800a212: 2b01 cmp r3, #1 800a214: d112 bne.n 800a23c if (ADC_TryLock() == 0u) { 800a216: f7ff fb39 bl 800988c 800a21a: 4603 mov r3, r0 800a21c: 2b00 cmp r3, #0 800a21e: d00c beq.n 800a23a return; } cp_voltage_mv = CP_ReadVoltageMv(); 800a220: f7ff ff14 bl 800a04c 800a224: 4603 mov r3, r0 800a226: 4a08 ldr r2, [pc, #32] @ (800a248 ) 800a228: 6013 str r3, [r2, #0] (void)CP_ApplyEma(cp_voltage_mv); 800a22a: 4b07 ldr r3, [pc, #28] @ (800a248 ) 800a22c: 681b ldr r3, [r3, #0] 800a22e: 4618 mov r0, r3 800a230: f7ff fe1c bl 8009e6c ADC_Unlock(); 800a234: f7ff fb5c bl 80098f0 800a238: e000 b.n 800a23c return; 800a23a: bf00 nop } } 800a23c: 3708 adds r7, #8 800a23e: 46bd mov sp, r7 800a240: bd80 pop {r7, pc} 800a242: bf00 nop 800a244: 40000400 .word 0x40000400 800a248: 200001f8 .word 0x200001f8 0800a24c : CRC_HandleTypeDef hcrc; /* CRC init function */ void MX_CRC_Init(void) { 800a24c: b580 push {r7, lr} 800a24e: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 800a250: 4b06 ldr r3, [pc, #24] @ (800a26c ) 800a252: 4a07 ldr r2, [pc, #28] @ (800a270 ) 800a254: 601a str r2, [r3, #0] if (HAL_CRC_Init(&hcrc) != HAL_OK) 800a256: 4805 ldr r0, [pc, #20] @ (800a26c ) 800a258: f005 f897 bl 800f38a 800a25c: 4603 mov r3, r0 800a25e: 2b00 cmp r3, #0 800a260: d001 beq.n 800a266 { Error_Handler(); 800a262: f000 fbcb bl 800a9fc } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 800a266: bf00 nop 800a268: bd80 pop {r7, pc} 800a26a: bf00 nop 800a26c: 20000208 .word 0x20000208 800a270: 40023000 .word 0x40023000 0800a274 : void HAL_CRC_MspInit(CRC_HandleTypeDef* crcHandle) { 800a274: b480 push {r7} 800a276: b085 sub sp, #20 800a278: af00 add r7, sp, #0 800a27a: 6078 str r0, [r7, #4] if(crcHandle->Instance==CRC) 800a27c: 687b ldr r3, [r7, #4] 800a27e: 681b ldr r3, [r3, #0] 800a280: 4a09 ldr r2, [pc, #36] @ (800a2a8 ) 800a282: 4293 cmp r3, r2 800a284: d10b bne.n 800a29e { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* CRC clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 800a286: 4b09 ldr r3, [pc, #36] @ (800a2ac ) 800a288: 695b ldr r3, [r3, #20] 800a28a: 4a08 ldr r2, [pc, #32] @ (800a2ac ) 800a28c: f043 0340 orr.w r3, r3, #64 @ 0x40 800a290: 6153 str r3, [r2, #20] 800a292: 4b06 ldr r3, [pc, #24] @ (800a2ac ) 800a294: 695b ldr r3, [r3, #20] 800a296: f003 0340 and.w r3, r3, #64 @ 0x40 800a29a: 60fb str r3, [r7, #12] 800a29c: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 800a29e: bf00 nop 800a2a0: 3714 adds r7, #20 800a2a2: 46bd mov sp, r7 800a2a4: bc80 pop {r7} 800a2a6: 4770 bx lr 800a2a8: 40023000 .word 0x40023000 800a2ac: 40021000 .word 0x40021000 0800a2b0 <_write>: #if defined(__GNUC__) int _write(int fd, char * ptr, int len) { 800a2b0: b580 push {r7, lr} 800a2b2: b084 sub sp, #16 800a2b4: af00 add r7, sp, #0 800a2b6: 60f8 str r0, [r7, #12] 800a2b8: 60b9 str r1, [r7, #8] 800a2ba: 607a str r2, [r7, #4] debug_buffer_add((const uint8_t*)ptr, len); 800a2bc: 687b ldr r3, [r7, #4] 800a2be: b29b uxth r3, r3 800a2c0: 4619 mov r1, r3 800a2c2: 68b8 ldr r0, [r7, #8] 800a2c4: f000 f806 bl 800a2d4 return len; 800a2c8: 687b ldr r3, [r7, #4] } 800a2ca: 4618 mov r0, r3 800a2cc: 3710 adds r7, #16 800a2ce: 46bd mov sp, r7 800a2d0: bd80 pop {r7, pc} ... 0800a2d4 : #endif // Добавляет данные в кольцевой буфер void debug_buffer_add(const uint8_t* data, uint16_t len) { 800a2d4: b480 push {r7} 800a2d6: b085 sub sp, #20 800a2d8: af00 add r7, sp, #0 800a2da: 6078 str r0, [r7, #4] 800a2dc: 460b mov r3, r1 800a2de: 807b strh r3, [r7, #2] __ASM volatile ("cpsid i" : : : "memory"); 800a2e0: b672 cpsid i } 800a2e2: bf00 nop __disable_irq(); for (uint16_t i = 0; i < len; i++) { 800a2e4: 2300 movs r3, #0 800a2e6: 81fb strh r3, [r7, #14] 800a2e8: e045 b.n 800a376 // Если буфер полон, перезаписываем старые данные if (debug_buffer.count >= DEBUG_BUFFER_SIZE) { 800a2ea: 4b28 ldr r3, [pc, #160] @ (800a38c ) 800a2ec: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a2f0: b29b uxth r3, r3 800a2f2: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800a2f6: d318 bcc.n 800a32a debug_buffer.read_index = (debug_buffer.read_index + 1) % DEBUG_BUFFER_SIZE; 800a2f8: 4b24 ldr r3, [pc, #144] @ (800a38c ) 800a2fa: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a2fe: b29b uxth r3, r3 800a300: 3301 adds r3, #1 800a302: 425a negs r2, r3 800a304: f3c3 0309 ubfx r3, r3, #0, #10 800a308: f3c2 0209 ubfx r2, r2, #0, #10 800a30c: bf58 it pl 800a30e: 4253 negpl r3, r2 800a310: b29a uxth r2, r3 800a312: 4b1e ldr r3, [pc, #120] @ (800a38c ) 800a314: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count--; 800a318: 4b1c ldr r3, [pc, #112] @ (800a38c ) 800a31a: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a31e: b29b uxth r3, r3 800a320: 3b01 subs r3, #1 800a322: b29a uxth r2, r3 800a324: 4b19 ldr r3, [pc, #100] @ (800a38c ) 800a326: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 } debug_buffer.buffer[debug_buffer.write_index] = data[i]; 800a32a: 89fb ldrh r3, [r7, #14] 800a32c: 687a ldr r2, [r7, #4] 800a32e: 4413 add r3, r2 800a330: 4a16 ldr r2, [pc, #88] @ (800a38c ) 800a332: f8b2 2400 ldrh.w r2, [r2, #1024] @ 0x400 800a336: b292 uxth r2, r2 800a338: 7819 ldrb r1, [r3, #0] 800a33a: 4b14 ldr r3, [pc, #80] @ (800a38c ) 800a33c: 5499 strb r1, [r3, r2] debug_buffer.write_index = (debug_buffer.write_index + 1) % DEBUG_BUFFER_SIZE; 800a33e: 4b13 ldr r3, [pc, #76] @ (800a38c ) 800a340: f8b3 3400 ldrh.w r3, [r3, #1024] @ 0x400 800a344: b29b uxth r3, r3 800a346: 3301 adds r3, #1 800a348: 425a negs r2, r3 800a34a: f3c3 0309 ubfx r3, r3, #0, #10 800a34e: f3c2 0209 ubfx r2, r2, #0, #10 800a352: bf58 it pl 800a354: 4253 negpl r3, r2 800a356: b29a uxth r2, r3 800a358: 4b0c ldr r3, [pc, #48] @ (800a38c ) 800a35a: f8a3 2400 strh.w r2, [r3, #1024] @ 0x400 debug_buffer.count++; 800a35e: 4b0b ldr r3, [pc, #44] @ (800a38c ) 800a360: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a364: b29b uxth r3, r3 800a366: 3301 adds r3, #1 800a368: b29a uxth r2, r3 800a36a: 4b08 ldr r3, [pc, #32] @ (800a38c ) 800a36c: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 for (uint16_t i = 0; i < len; i++) { 800a370: 89fb ldrh r3, [r7, #14] 800a372: 3301 adds r3, #1 800a374: 81fb strh r3, [r7, #14] 800a376: 89fa ldrh r2, [r7, #14] 800a378: 887b ldrh r3, [r7, #2] 800a37a: 429a cmp r2, r3 800a37c: d3b5 bcc.n 800a2ea __ASM volatile ("cpsie i" : : : "memory"); 800a37e: b662 cpsie i } 800a380: bf00 nop } __enable_irq(); } 800a382: bf00 nop 800a384: 3714 adds r7, #20 800a386: 46bd mov sp, r7 800a388: bc80 pop {r7} 800a38a: 4770 bx lr 800a38c: 20000210 .word 0x20000210 0800a390 : // Возвращает количество доступных данных в буфере uint16_t debug_buffer_available(void) { 800a390: b480 push {r7} 800a392: b083 sub sp, #12 800a394: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a396: b672 cpsid i } 800a398: bf00 nop __disable_irq(); uint16_t count = debug_buffer.count; 800a39a: 4b06 ldr r3, [pc, #24] @ (800a3b4 ) 800a39c: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a3a0: 80fb strh r3, [r7, #6] __ASM volatile ("cpsie i" : : : "memory"); 800a3a2: b662 cpsie i } 800a3a4: bf00 nop __enable_irq(); return count; 800a3a6: 88fb ldrh r3, [r7, #6] } 800a3a8: 4618 mov r0, r3 800a3aa: 370c adds r7, #12 800a3ac: 46bd mov sp, r7 800a3ae: bc80 pop {r7} 800a3b0: 4770 bx lr 800a3b2: bf00 nop 800a3b4: 20000210 .word 0x20000210 0800a3b8 : // Отправляет один пакет данных из буфера через SC_SendPacket (не более 250 байт) void debug_buffer_send(void) { 800a3b8: b580 push {r7, lr} 800a3ba: b082 sub sp, #8 800a3bc: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a3be: b672 cpsid i } 800a3c0: bf00 nop __disable_irq(); // Если буфер пуст, ничего не делаем if (debug_buffer.count == 0) { 800a3c2: 4b2d ldr r3, [pc, #180] @ (800a478 ) 800a3c4: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a3c8: b29b uxth r3, r3 800a3ca: 2b00 cmp r3, #0 800a3cc: d102 bne.n 800a3d4 __ASM volatile ("cpsie i" : : : "memory"); 800a3ce: b662 cpsie i } 800a3d0: bf00 nop __enable_irq(); return; 800a3d2: e04e b.n 800a472 } // Определяем сколько байт можно отправить (не более 250) uint16_t bytes_to_send = debug_buffer.count; 800a3d4: 4b28 ldr r3, [pc, #160] @ (800a478 ) 800a3d6: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a3da: 80fb strh r3, [r7, #6] if (bytes_to_send > DEBUG_BUFFER_MAX_COUNT) { 800a3dc: 88fb ldrh r3, [r7, #6] 800a3de: 2b80 cmp r3, #128 @ 0x80 800a3e0: d901 bls.n 800a3e6 bytes_to_send = DEBUG_BUFFER_MAX_COUNT; 800a3e2: 2380 movs r3, #128 @ 0x80 800a3e4: 80fb strh r3, [r7, #6] } // Вычисляем сколько байт до конца буфера uint16_t bytes_to_end = DEBUG_BUFFER_SIZE - debug_buffer.read_index; 800a3e6: 4b24 ldr r3, [pc, #144] @ (800a478 ) 800a3e8: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a3ec: b29b uxth r3, r3 800a3ee: f5c3 6380 rsb r3, r3, #1024 @ 0x400 800a3f2: 80bb strh r3, [r7, #4] // Отправляем только непрерывный блок (до конца буфера или до bytes_to_send) if (bytes_to_send > bytes_to_end) { 800a3f4: 88fa ldrh r2, [r7, #6] 800a3f6: 88bb ldrh r3, [r7, #4] 800a3f8: 429a cmp r2, r3 800a3fa: d901 bls.n 800a400 bytes_to_send = bytes_to_end; 800a3fc: 88bb ldrh r3, [r7, #4] 800a3fe: 80fb strh r3, [r7, #6] } // Отправляем данные напрямую из буфера if(bytes_to_send == debug_buffer.count){ 800a400: 4b1d ldr r3, [pc, #116] @ (800a478 ) 800a402: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a406: b29b uxth r3, r3 800a408: 88fa ldrh r2, [r7, #6] 800a40a: 429a cmp r2, r3 800a40c: d10c bne.n 800a428 SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG); 800a40e: 4b1a ldr r3, [pc, #104] @ (800a478 ) 800a410: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a414: b29b uxth r3, r3 800a416: 461a mov r2, r3 800a418: 4b17 ldr r3, [pc, #92] @ (800a478 ) 800a41a: 4413 add r3, r2 800a41c: 88f9 ldrh r1, [r7, #6] 800a41e: 2250 movs r2, #80 @ 0x50 800a420: 4618 mov r0, r3 800a422: f002 f9d7 bl 800c7d4 800a426: e00b b.n 800a440 }else{ SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG_CONTINUE); 800a428: 4b13 ldr r3, [pc, #76] @ (800a478 ) 800a42a: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a42e: b29b uxth r3, r3 800a430: 461a mov r2, r3 800a432: 4b11 ldr r3, [pc, #68] @ (800a478 ) 800a434: 4413 add r3, r2 800a436: 88f9 ldrh r1, [r7, #6] 800a438: 2251 movs r2, #81 @ 0x51 800a43a: 4618 mov r0, r3 800a43c: f002 f9ca bl 800c7d4 } debug_buffer.read_index = (debug_buffer.read_index + bytes_to_send) % DEBUG_BUFFER_SIZE; 800a440: 4b0d ldr r3, [pc, #52] @ (800a478 ) 800a442: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a446: b29a uxth r2, r3 800a448: 88fb ldrh r3, [r7, #6] 800a44a: 4413 add r3, r2 800a44c: b29b uxth r3, r3 800a44e: f3c3 0309 ubfx r3, r3, #0, #10 800a452: b29a uxth r2, r3 800a454: 4b08 ldr r3, [pc, #32] @ (800a478 ) 800a456: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count -= bytes_to_send; 800a45a: 4b07 ldr r3, [pc, #28] @ (800a478 ) 800a45c: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a460: b29a uxth r2, r3 800a462: 88fb ldrh r3, [r7, #6] 800a464: 1ad3 subs r3, r2, r3 800a466: b29a uxth r2, r3 800a468: 4b03 ldr r3, [pc, #12] @ (800a478 ) 800a46a: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 __ASM volatile ("cpsie i" : : : "memory"); 800a46e: b662 cpsie i } 800a470: bf00 nop __enable_irq(); } 800a472: 3708 adds r7, #8 800a474: 46bd mov sp, r7 800a476: bd80 pop {r7, pc} 800a478: 20000210 .word 0x20000210 0800a47c : #define LOG_BUFFER_SIZE 128 uint8_t log_buffer[LOG_BUFFER_SIZE]; // Кастомный printf с приоритетом лога int log_printf(LogLevel_t level, const char *format, ...) { 800a47c: b40e push {r1, r2, r3} 800a47e: b580 push {r7, lr} 800a480: b085 sub sp, #20 800a482: af00 add r7, sp, #0 800a484: 4603 mov r3, r0 800a486: 71fb strb r3, [r7, #7] va_list args; int result; // Добавляем приоритет первым байтом log_buffer[0] = (uint8_t)level; 800a488: 4a15 ldr r2, [pc, #84] @ (800a4e0 ) 800a48a: 79fb ldrb r3, [r7, #7] 800a48c: 7013 strb r3, [r2, #0] // Форматируем строку начиная со второго байта va_start(args, format); 800a48e: f107 0320 add.w r3, r7, #32 800a492: 60bb str r3, [r7, #8] result = vsnprintf((char*)&log_buffer[1], LOG_BUFFER_SIZE - 2, format, args); 800a494: 68bb ldr r3, [r7, #8] 800a496: 69fa ldr r2, [r7, #28] 800a498: 217e movs r1, #126 @ 0x7e 800a49a: 4812 ldr r0, [pc, #72] @ (800a4e4 ) 800a49c: f008 fdc2 bl 8013024 800a4a0: 60f8 str r0, [r7, #12] va_end(args); // Проверяем, не переполнился ли буфер if (result < 0) { 800a4a2: 68fb ldr r3, [r7, #12] 800a4a4: 2b00 cmp r3, #0 800a4a6: da01 bge.n 800a4ac return result; 800a4a8: 68fb ldr r3, [r7, #12] 800a4aa: e012 b.n 800a4d2 } // Ограничиваем размер, чтобы оставить место для нуль-терминатора if (result >= (LOG_BUFFER_SIZE - 2)) { 800a4ac: 68fb ldr r3, [r7, #12] 800a4ae: 2b7d cmp r3, #125 @ 0x7d 800a4b0: dd01 ble.n 800a4b6 result = LOG_BUFFER_SIZE - 2; 800a4b2: 237e movs r3, #126 @ 0x7e 800a4b4: 60fb str r3, [r7, #12] } // Добавляем нуль-терминатор в конец log_buffer[result + 1] = '\0'; 800a4b6: 68fb ldr r3, [r7, #12] 800a4b8: 3301 adds r3, #1 800a4ba: 4a09 ldr r2, [pc, #36] @ (800a4e0 ) 800a4bc: 2100 movs r1, #0 800a4be: 54d1 strb r1, [r2, r3] // Отправляем в буфер (приоритет + строка + нуль-терминатор) debug_buffer_add(log_buffer, result + 2); 800a4c0: 68fb ldr r3, [r7, #12] 800a4c2: b29b uxth r3, r3 800a4c4: 3302 adds r3, #2 800a4c6: b29b uxth r3, r3 800a4c8: 4619 mov r1, r3 800a4ca: 4805 ldr r0, [pc, #20] @ (800a4e0 ) 800a4cc: f7ff ff02 bl 800a2d4 return result; 800a4d0: 68fb ldr r3, [r7, #12] } 800a4d2: 4618 mov r0, r3 800a4d4: 3714 adds r7, #20 800a4d6: 46bd mov sp, r7 800a4d8: e8bd 4080 ldmia.w sp!, {r7, lr} 800a4dc: b003 add sp, #12 800a4de: 4770 bx lr 800a4e0: 20000618 .word 0x20000618 800a4e4: 20000619 .word 0x20000619 0800a4e8 : * EXTI PB8 ------> I2C1_SCL PB9 ------> I2C1_SDA */ void MX_GPIO_Init(void) { 800a4e8: b580 push {r7, lr} 800a4ea: b08a sub sp, #40 @ 0x28 800a4ec: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800a4ee: f107 0314 add.w r3, r7, #20 800a4f2: 2200 movs r2, #0 800a4f4: 601a str r2, [r3, #0] 800a4f6: 605a str r2, [r3, #4] 800a4f8: 609a str r2, [r3, #8] 800a4fa: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 800a4fc: 4b7d ldr r3, [pc, #500] @ (800a6f4 ) 800a4fe: 699b ldr r3, [r3, #24] 800a500: 4a7c ldr r2, [pc, #496] @ (800a6f4 ) 800a502: f043 0310 orr.w r3, r3, #16 800a506: 6193 str r3, [r2, #24] 800a508: 4b7a ldr r3, [pc, #488] @ (800a6f4 ) 800a50a: 699b ldr r3, [r3, #24] 800a50c: f003 0310 and.w r3, r3, #16 800a510: 613b str r3, [r7, #16] 800a512: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800a514: 4b77 ldr r3, [pc, #476] @ (800a6f4 ) 800a516: 699b ldr r3, [r3, #24] 800a518: 4a76 ldr r2, [pc, #472] @ (800a6f4 ) 800a51a: f043 0304 orr.w r3, r3, #4 800a51e: 6193 str r3, [r2, #24] 800a520: 4b74 ldr r3, [pc, #464] @ (800a6f4 ) 800a522: 699b ldr r3, [r3, #24] 800a524: f003 0304 and.w r3, r3, #4 800a528: 60fb str r3, [r7, #12] 800a52a: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 800a52c: 4b71 ldr r3, [pc, #452] @ (800a6f4 ) 800a52e: 699b ldr r3, [r3, #24] 800a530: 4a70 ldr r2, [pc, #448] @ (800a6f4 ) 800a532: f043 0308 orr.w r3, r3, #8 800a536: 6193 str r3, [r2, #24] 800a538: 4b6e ldr r3, [pc, #440] @ (800a6f4 ) 800a53a: 699b ldr r3, [r3, #24] 800a53c: f003 0308 and.w r3, r3, #8 800a540: 60bb str r3, [r7, #8] 800a542: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOE_CLK_ENABLE(); 800a544: 4b6b ldr r3, [pc, #428] @ (800a6f4 ) 800a546: 699b ldr r3, [r3, #24] 800a548: 4a6a ldr r2, [pc, #424] @ (800a6f4 ) 800a54a: f043 0340 orr.w r3, r3, #64 @ 0x40 800a54e: 6193 str r3, [r2, #24] 800a550: 4b68 ldr r3, [pc, #416] @ (800a6f4 ) 800a552: 699b ldr r3, [r3, #24] 800a554: f003 0340 and.w r3, r3, #64 @ 0x40 800a558: 607b str r3, [r7, #4] 800a55a: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 800a55c: 4b65 ldr r3, [pc, #404] @ (800a6f4 ) 800a55e: 699b ldr r3, [r3, #24] 800a560: 4a64 ldr r2, [pc, #400] @ (800a6f4 ) 800a562: f043 0320 orr.w r3, r3, #32 800a566: 6193 str r3, [r2, #24] 800a568: 4b62 ldr r3, [pc, #392] @ (800a6f4 ) 800a56a: 699b ldr r3, [r3, #24] 800a56c: f003 0320 and.w r3, r3, #32 800a570: 603b str r3, [r7, #0] 800a572: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin, GPIO_PIN_RESET); 800a574: 2200 movs r2, #0 800a576: 2138 movs r1, #56 @ 0x38 800a578: 485f ldr r0, [pc, #380] @ (800a6f8 ) 800a57a: f005 fa00 bl 800f97e /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a57e: 2200 movs r2, #0 800a580: f44f 51f8 mov.w r1, #7936 @ 0x1f00 800a584: 485d ldr r0, [pc, #372] @ (800a6fc ) 800a586: f005 f9fa bl 800f97e |RELAY5_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, GPIO_PIN_RESET); 800a58a: 2200 movs r2, #0 800a58c: f44f 4100 mov.w r1, #32768 @ 0x8000 800a590: 485b ldr r0, [pc, #364] @ (800a700 ) 800a592: f005 f9f4 bl 800f97e /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, RELAY_DC_Pin|USART2_DIR_Pin, GPIO_PIN_RESET); 800a596: 2200 movs r2, #0 800a598: 2118 movs r1, #24 800a59a: 485a ldr r0, [pc, #360] @ (800a704 ) 800a59c: f005 f9ef bl 800f97e /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(EE_WP_GPIO_Port, EE_WP_Pin, GPIO_PIN_RESET); 800a5a0: 2200 movs r2, #0 800a5a2: 2180 movs r1, #128 @ 0x80 800a5a4: 4858 ldr r0, [pc, #352] @ (800a708 ) 800a5a6: f005 f9ea bl 800f97e /*Configure GPIO pins : RELAY_CP_Pin LOCK_A_Pin LOCK_B_Pin */ GPIO_InitStruct.Pin = RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin; 800a5aa: 2338 movs r3, #56 @ 0x38 800a5ac: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a5ae: 2301 movs r3, #1 800a5b0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a5b2: 2300 movs r3, #0 800a5b4: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a5b6: 2302 movs r3, #2 800a5b8: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800a5ba: f107 0314 add.w r3, r7, #20 800a5be: 4619 mov r1, r3 800a5c0: 484d ldr r0, [pc, #308] @ (800a6f8 ) 800a5c2: f005 f841 bl 800f648 /*Configure GPIO pin : IN_SW0_Pin */ GPIO_InitStruct.Pin = IN_SW0_Pin; 800a5c6: 2302 movs r3, #2 800a5c8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a5ca: 2300 movs r3, #0 800a5cc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a5ce: 2300 movs r3, #0 800a5d0: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW0_GPIO_Port, &GPIO_InitStruct); 800a5d2: f107 0314 add.w r3, r7, #20 800a5d6: 4619 mov r1, r3 800a5d8: 4849 ldr r0, [pc, #292] @ (800a700 ) 800a5da: f005 f835 bl 800f648 /*Configure GPIO pin : IN_SW1_Pin */ GPIO_InitStruct.Pin = IN_SW1_Pin; 800a5de: 2304 movs r3, #4 800a5e0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a5e2: 2300 movs r3, #0 800a5e4: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 800a5e6: 2302 movs r3, #2 800a5e8: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW1_GPIO_Port, &GPIO_InitStruct); 800a5ea: f107 0314 add.w r3, r7, #20 800a5ee: 4619 mov r1, r3 800a5f0: 4843 ldr r0, [pc, #268] @ (800a700 ) 800a5f2: f005 f829 bl 800f648 /*Configure GPIO pins : IN0_Pin AC_OK_Pin ISO_IN_Pin */ GPIO_InitStruct.Pin = IN0_Pin|AC_OK_Pin|ISO_IN_Pin; 800a5f6: f244 0382 movw r3, #16514 @ 0x4082 800a5fa: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a5fc: 2300 movs r3, #0 800a5fe: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a600: 2300 movs r3, #0 800a602: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a604: f107 0314 add.w r3, r7, #20 800a608: 4619 mov r1, r3 800a60a: 483c ldr r0, [pc, #240] @ (800a6fc ) 800a60c: f005 f81c bl 800f648 /*Configure GPIO pins : RELAY1_Pin RELAY2_Pin RELAY3_Pin RELAY4_Pin RELAY5_Pin */ GPIO_InitStruct.Pin = RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a610: f44f 53f8 mov.w r3, #7936 @ 0x1f00 800a614: 617b str r3, [r7, #20] |RELAY5_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a616: 2301 movs r3, #1 800a618: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a61a: 2300 movs r3, #0 800a61c: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a61e: 2302 movs r3, #2 800a620: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a622: f107 0314 add.w r3, r7, #20 800a626: 4619 mov r1, r3 800a628: 4834 ldr r0, [pc, #208] @ (800a6fc ) 800a62a: f005 f80d bl 800f648 /*Configure GPIO pin : RELAY_CC_Pin */ GPIO_InitStruct.Pin = RELAY_CC_Pin; 800a62e: f44f 4300 mov.w r3, #32768 @ 0x8000 800a632: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a634: 2301 movs r3, #1 800a636: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a638: 2300 movs r3, #0 800a63a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a63c: 2302 movs r3, #2 800a63e: 623b str r3, [r7, #32] HAL_GPIO_Init(RELAY_CC_GPIO_Port, &GPIO_InitStruct); 800a640: f107 0314 add.w r3, r7, #20 800a644: 4619 mov r1, r3 800a646: 482e ldr r0, [pc, #184] @ (800a700 ) 800a648: f004 fffe bl 800f648 /*Configure GPIO pins : RELAY_DC_Pin USART2_DIR_Pin */ GPIO_InitStruct.Pin = RELAY_DC_Pin|USART2_DIR_Pin; 800a64c: 2318 movs r3, #24 800a64e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a650: 2301 movs r3, #1 800a652: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a654: 2300 movs r3, #0 800a656: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a658: 2302 movs r3, #2 800a65a: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800a65c: f107 0314 add.w r3, r7, #20 800a660: 4619 mov r1, r3 800a662: 4828 ldr r0, [pc, #160] @ (800a704 ) 800a664: f004 fff0 bl 800f648 /*Configure GPIO pin : IN_ESTOP_Pin */ GPIO_InitStruct.Pin = IN_ESTOP_Pin; 800a668: 2380 movs r3, #128 @ 0x80 800a66a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a66c: 2300 movs r3, #0 800a66e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a670: 2300 movs r3, #0 800a672: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_ESTOP_GPIO_Port, &GPIO_InitStruct); 800a674: f107 0314 add.w r3, r7, #20 800a678: 4619 mov r1, r3 800a67a: 4822 ldr r0, [pc, #136] @ (800a704 ) 800a67c: f004 ffe4 bl 800f648 /*Configure GPIO pins : IN_FB2_Pin IN_FB1_Pin */ GPIO_InitStruct.Pin = IN_FB2_Pin|IN_FB1_Pin; 800a680: 2318 movs r3, #24 800a682: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a684: 2300 movs r3, #0 800a686: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a688: 2300 movs r3, #0 800a68a: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a68c: f107 0314 add.w r3, r7, #20 800a690: 4619 mov r1, r3 800a692: 481d ldr r0, [pc, #116] @ (800a708 ) 800a694: f004 ffd8 bl 800f648 /*Configure GPIO pin : EE_WP_Pin */ GPIO_InitStruct.Pin = EE_WP_Pin; 800a698: 2380 movs r3, #128 @ 0x80 800a69a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a69c: 2301 movs r3, #1 800a69e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a6a0: 2300 movs r3, #0 800a6a2: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a6a4: 2302 movs r3, #2 800a6a6: 623b str r3, [r7, #32] HAL_GPIO_Init(EE_WP_GPIO_Port, &GPIO_InitStruct); 800a6a8: f107 0314 add.w r3, r7, #20 800a6ac: 4619 mov r1, r3 800a6ae: 4816 ldr r0, [pc, #88] @ (800a708 ) 800a6b0: f004 ffca bl 800f648 /*Configure GPIO pins : PB8 PB9 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 800a6b4: f44f 7340 mov.w r3, #768 @ 0x300 800a6b8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 800a6ba: 2312 movs r3, #18 800a6bc: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a6be: 2303 movs r3, #3 800a6c0: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a6c2: f107 0314 add.w r3, r7, #20 800a6c6: 4619 mov r1, r3 800a6c8: 480f ldr r0, [pc, #60] @ (800a708 ) 800a6ca: f004 ffbd bl 800f648 /*Configure peripheral I/O remapping */ __HAL_AFIO_REMAP_I2C1_ENABLE(); 800a6ce: 4b0f ldr r3, [pc, #60] @ (800a70c ) 800a6d0: 685b ldr r3, [r3, #4] 800a6d2: 627b str r3, [r7, #36] @ 0x24 800a6d4: 6a7b ldr r3, [r7, #36] @ 0x24 800a6d6: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800a6da: 627b str r3, [r7, #36] @ 0x24 800a6dc: 6a7b ldr r3, [r7, #36] @ 0x24 800a6de: f043 0302 orr.w r3, r3, #2 800a6e2: 627b str r3, [r7, #36] @ 0x24 800a6e4: 4a09 ldr r2, [pc, #36] @ (800a70c ) 800a6e6: 6a7b ldr r3, [r7, #36] @ 0x24 800a6e8: 6053 str r3, [r2, #4] } 800a6ea: bf00 nop 800a6ec: 3728 adds r7, #40 @ 0x28 800a6ee: 46bd mov sp, r7 800a6f0: bd80 pop {r7, pc} 800a6f2: bf00 nop 800a6f4: 40021000 .word 0x40021000 800a6f8: 40011000 .word 0x40011000 800a6fc: 40011800 .word 0x40011800 800a700: 40010800 .word 0x40010800 800a704: 40011400 .word 0x40011400 800a708: 40010c00 .word 0x40010c00 800a70c: 40010000 .word 0x40010000 0800a710 : * bootloader before starting this program. Unfortunately, function * SystemInit() overwrites this change again. * @return none. */ static void VectorBase_Config(void) { 800a710: b480 push {r7} 800a712: af00 add r7, sp, #0 * c-startup code. */ extern const unsigned long g_pfnVectors[]; /* Remap the vector table to where the vector table is located for this program. */ SCB->VTOR = (unsigned long)&g_pfnVectors[0]; 800a714: 4b03 ldr r3, [pc, #12] @ (800a724 ) 800a716: 4a04 ldr r2, [pc, #16] @ (800a728 ) 800a718: 609a str r2, [r3, #8] } 800a71a: bf00 nop 800a71c: 46bd mov sp, r7 800a71e: bc80 pop {r7} 800a720: 4770 bx lr 800a722: bf00 nop 800a724: e000ed00 .word 0xe000ed00 800a728: 08008000 .word 0x08008000 0800a72c : uint8_t ED_TraceWarning(uint8_t flag, uint8_t id){ 800a72c: b480 push {r7} 800a72e: b085 sub sp, #20 800a730: af00 add r7, sp, #0 800a732: 4603 mov r3, r0 800a734: 460a mov r2, r1 800a736: 71fb strb r3, [r7, #7] 800a738: 4613 mov r3, r2 800a73a: 71bb strb r3, [r7, #6] static uint8_t memory[32]; if(id > 31) return 0; 800a73c: 79bb ldrb r3, [r7, #6] 800a73e: 2b1f cmp r3, #31 800a740: d901 bls.n 800a746 800a742: 2300 movs r3, #0 800a744: e00e b.n 800a764 uint8_t result = 0; 800a746: 2300 movs r3, #0 800a748: 73fb strb r3, [r7, #15] if(memory[id] != flag){ 800a74a: 79bb ldrb r3, [r7, #6] 800a74c: 4a08 ldr r2, [pc, #32] @ (800a770 ) 800a74e: 5cd3 ldrb r3, [r2, r3] 800a750: 79fa ldrb r2, [r7, #7] 800a752: 429a cmp r2, r3 800a754: d001 beq.n 800a75a result = 1; 800a756: 2301 movs r3, #1 800a758: 73fb strb r3, [r7, #15] } memory[id] = flag; 800a75a: 79bb ldrb r3, [r7, #6] 800a75c: 4904 ldr r1, [pc, #16] @ (800a770 ) 800a75e: 79fa ldrb r2, [r7, #7] 800a760: 54ca strb r2, [r1, r3] return result; 800a762: 7bfb ldrb r3, [r7, #15] } 800a764: 4618 mov r0, r3 800a766: 3714 adds r7, #20 800a768: 46bd mov sp, r7 800a76a: bc80 pop {r7} 800a76c: 4770 bx lr 800a76e: bf00 nop 800a770: 20000698 .word 0x20000698 0800a774 : void ED_Delay(uint32_t Delay) { 800a774: b580 push {r7, lr} 800a776: b084 sub sp, #16 800a778: af00 add r7, sp, #0 800a77a: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800a77c: f003 f8ee bl 800d95c 800a780: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800a782: 687b ldr r3, [r7, #4] 800a784: 60fb str r3, [r7, #12] if (wait < HAL_MAX_DELAY) 800a786: 68fb ldr r3, [r7, #12] 800a788: f1b3 3fff cmp.w r3, #4294967295 800a78c: d00e beq.n 800a7ac { wait += (uint32_t)(uwTickFreq); 800a78e: 4b0e ldr r3, [pc, #56] @ (800a7c8 ) 800a790: 781b ldrb r3, [r3, #0] 800a792: 461a mov r2, r3 800a794: 68fb ldr r3, [r7, #12] 800a796: 4413 add r3, r2 800a798: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait){ 800a79a: e007 b.n 800a7ac CCS_SerialLoop(); 800a79c: f001 f92c bl 800b9f8 // CP_Loop(); CONN_Task(); 800a7a0: f7ff fa60 bl 8009c64 LED_Task(); 800a7a4: f001 f810 bl 800b7c8 SC_Task(); 800a7a8: f001 fe9a bl 800c4e0 while ((HAL_GetTick() - tickstart) < wait){ 800a7ac: f003 f8d6 bl 800d95c 800a7b0: 4602 mov r2, r0 800a7b2: 68bb ldr r3, [r7, #8] 800a7b4: 1ad3 subs r3, r2, r3 800a7b6: 68fa ldr r2, [r7, #12] 800a7b8: 429a cmp r2, r3 800a7ba: d8ef bhi.n 800a79c } } 800a7bc: bf00 nop 800a7be: bf00 nop 800a7c0: 3710 adds r7, #16 800a7c2: 46bd mov sp, r7 800a7c4: bd80 pop {r7, pc} 800a7c6: bf00 nop 800a7c8: 20000074 .word 0x20000074 0800a7cc : void StopButtonControl(){ 800a7cc: b580 push {r7, lr} 800a7ce: af00 add r7, sp, #0 //Charging do nothing if(!IN_ReadInput(IN_ESTOP)){ 800a7d0: 2003 movs r0, #3 800a7d2: f7fe feed bl 80095b0 800a7d6: 4603 mov r3, r0 800a7d8: 2b00 cmp r3, #0 800a7da: d102 bne.n 800a7e2 CONN.connControl = CMD_STOP; 800a7dc: 4b02 ldr r3, [pc, #8] @ (800a7e8 ) 800a7de: 2201 movs r2, #1 800a7e0: 701a strb r2, [r3, #0] } } 800a7e2: bf00 nop 800a7e4: bd80 pop {r7, pc} 800a7e6: bf00 nop 800a7e8: 200001d4 .word 0x200001d4 0800a7ec : uint8_t temp0, temp1; static void CAN1_MinimalReInit(void) { 800a7ec: b580 push {r7, lr} 800a7ee: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan1); 800a7f0: 480b ldr r0, [pc, #44] @ (800a820 ) 800a7f2: f004 f807 bl 800e804 MX_CAN1_Init(); 800a7f6: f7ff f895 bl 8009924 if (HAL_CAN_Start(&hcan1) != HAL_OK) { 800a7fa: 4809 ldr r0, [pc, #36] @ (800a820 ) 800a7fc: f003 ffbe bl 800e77c 800a800: 4603 mov r3, r0 800a802: 2b00 cmp r3, #0 800a804: d001 beq.n 800a80a Error_Handler(); 800a806: f000 f8f9 bl 800a9fc } if (HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) { 800a80a: 2102 movs r1, #2 800a80c: 4804 ldr r0, [pc, #16] @ (800a820 ) 800a80e: f004 fa66 bl 800ecde 800a812: 4603 mov r3, r0 800a814: 2b00 cmp r3, #0 800a816: d001 beq.n 800a81c Error_Handler(); 800a818: f000 f8f0 bl 800a9fc } } 800a81c: bf00 nop 800a81e: bd80 pop {r7, pc} 800a820: 20000180 .word 0x20000180 0800a824
: /** * @brief The application entry point. * @retval int */ int main(void) { 800a824: b580 push {r7, lr} 800a826: b082 sub sp, #8 800a828: af02 add r7, sp, #8 /* USER CODE BEGIN 1 */ VectorBase_Config(); 800a82a: f7ff ff71 bl 800a710 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800a82e: f003 f83d bl 800d8ac /* USER CODE BEGIN Init */ HAL_RCC_DeInit(); 800a832: f005 f8c9 bl 800f9c8 /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800a836: f000 f871 bl 800a91c /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800a83a: f7ff fe55 bl 800a4e8 MX_ADC1_Init(); 800a83e: f7fe fda5 bl 800938c MX_CAN1_Init(); 800a842: f7ff f86f bl 8009924 MX_CAN2_Init(); 800a846: f7ff f8a3 bl 8009990 MX_RTC_Init(); 800a84a: f001 f85b bl 800b904 MX_TIM4_Init(); 800a84e: f002 fce9 bl 800d224 MX_USART2_UART_Init(); 800a852: f002 fe67 bl 800d524 MX_CRC_Init(); 800a856: f7ff fcf9 bl 800a24c MX_UART5_Init(); 800a85a: f002 fe0f bl 800d47c MX_USART1_UART_Init(); 800a85e: f002 fe37 bl 800d4d0 MX_USART3_UART_Init(); 800a862: f002 fe89 bl 800d578 MX_TIM3_Init(); 800a866: f002 fc67 bl 800d138 /* USER CODE BEGIN 2 */ Init_Peripheral(); 800a86a: f7fe fef3 bl 8009654 LED_Init(); 800a86e: f000 ff8b bl 800b788 HAL_Delay(300); 800a872: f44f 7096 mov.w r0, #300 @ 0x12c 800a876: f003 f87b bl 800d970 CCS_Init(); 800a87a: f001 facd bl 800be18 SC_Init(); 800a87e: f001 fe1b bl 800c4b8 log_printf(LOG_INFO, "CCS module start\n"); 800a882: 4921 ldr r1, [pc, #132] @ (800a908 ) 800a884: 2007 movs r0, #7 800a886: f7ff fdf9 bl 800a47c ReadVersion(); 800a88a: f001 fdf1 bl 800c470 log_printf(LOG_INFO, "Serial number: %d\n", infoPacket.serialNumber); 800a88e: 4b1f ldr r3, [pc, #124] @ (800a90c ) 800a890: 881b ldrh r3, [r3, #0] 800a892: b29b uxth r3, r3 800a894: 461a mov r2, r3 800a896: 491e ldr r1, [pc, #120] @ (800a910 ) 800a898: 2007 movs r0, #7 800a89a: f7ff fdef bl 800a47c log_printf(LOG_INFO, "Board revision: %d\n", infoPacket.boardVersion); 800a89e: 4b1b ldr r3, [pc, #108] @ (800a90c ) 800a8a0: 789b ldrb r3, [r3, #2] 800a8a2: 461a mov r2, r3 800a8a4: 491b ldr r1, [pc, #108] @ (800a914 ) 800a8a6: 2007 movs r0, #7 800a8a8: f7ff fde8 bl 800a47c log_printf(LOG_INFO, "FW version: %d.%d.%d\n", infoPacket.fw_version_major, infoPacket.fw_version_minor, infoPacket.fw_version_patch); 800a8ac: 4b17 ldr r3, [pc, #92] @ (800a90c ) 800a8ae: 889b ldrh r3, [r3, #4] 800a8b0: b29b uxth r3, r3 800a8b2: 461a mov r2, r3 800a8b4: 4b15 ldr r3, [pc, #84] @ (800a90c ) 800a8b6: 88db ldrh r3, [r3, #6] 800a8b8: b29b uxth r3, r3 800a8ba: 4619 mov r1, r3 800a8bc: 4b13 ldr r3, [pc, #76] @ (800a90c ) 800a8be: 891b ldrh r3, [r3, #8] 800a8c0: b29b uxth r3, r3 800a8c2: 9300 str r3, [sp, #0] 800a8c4: 460b mov r3, r1 800a8c6: 4914 ldr r1, [pc, #80] @ (800a918 ) 800a8c8: 2007 movs r0, #7 800a8ca: f7ff fdd7 bl 800a47c CAN1_MinimalReInit(); 800a8ce: f7ff ff8d bl 800a7ec PSU_Init(); 800a8d2: f000 fa7d bl 800add0 CONN_Init(); 800a8d6: f7ff f96f bl 8009bb8 /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ PSU_ReadWrite(); 800a8da: f000 fb87 bl 800afec PSU_Task(); 800a8de: f000 fc25 bl 800b12c ED_Delay(10); 800a8e2: 200a movs r0, #10 800a8e4: f7ff ff46 bl 800a774 METER_CalculateEnergy(); 800a8e8: f000 f88e bl 800aa08 CONN_Loop(); 800a8ec: f7ff f97a bl 8009be4 LED_Write(); 800a8f0: f000 fe10 bl 800b514 ED_Delay(10); 800a8f4: 200a movs r0, #10 800a8f6: f7ff ff3d bl 800a774 StopButtonControl(); 800a8fa: f7ff ff67 bl 800a7cc ED_Delay(50); 800a8fe: 2032 movs r0, #50 @ 0x32 800a900: f7ff ff38 bl 800a774 { 800a904: bf00 nop 800a906: e7e8 b.n 800a8da 800a908: 080141b8 .word 0x080141b8 800a90c: 20000eb8 .word 0x20000eb8 800a910: 080141cc .word 0x080141cc 800a914: 080141e0 .word 0x080141e0 800a918: 080141f4 .word 0x080141f4 0800a91c : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800a91c: b580 push {r7, lr} 800a91e: b09c sub sp, #112 @ 0x70 800a920: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800a922: f107 0338 add.w r3, r7, #56 @ 0x38 800a926: 2238 movs r2, #56 @ 0x38 800a928: 2100 movs r1, #0 800a92a: 4618 mov r0, r3 800a92c: f008 fb88 bl 8013040 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800a930: f107 0324 add.w r3, r7, #36 @ 0x24 800a934: 2200 movs r2, #0 800a936: 601a str r2, [r3, #0] 800a938: 605a str r2, [r3, #4] 800a93a: 609a str r2, [r3, #8] 800a93c: 60da str r2, [r3, #12] 800a93e: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 800a940: 1d3b adds r3, r7, #4 800a942: 2220 movs r2, #32 800a944: 2100 movs r1, #0 800a946: 4618 mov r0, r3 800a948: f008 fb7a bl 8013040 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; 800a94c: 2305 movs r3, #5 800a94e: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800a950: f44f 3380 mov.w r3, #65536 @ 0x10000 800a954: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV5; 800a956: 2304 movs r3, #4 800a958: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 800a95a: 2301 movs r3, #1 800a95c: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800a95e: 2301 movs r3, #1 800a960: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.Prediv1Source = RCC_PREDIV1_SOURCE_PLL2; 800a962: f44f 3380 mov.w r3, #65536 @ 0x10000 800a966: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800a968: 2302 movs r3, #2 800a96a: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800a96c: f44f 3380 mov.w r3, #65536 @ 0x10000 800a970: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 800a972: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000 800a976: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL2.PLL2State = RCC_PLL2_ON; 800a978: 2302 movs r3, #2 800a97a: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL2.PLL2MUL = RCC_PLL2_MUL8; 800a97c: f44f 63c0 mov.w r3, #1536 @ 0x600 800a980: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL2.HSEPrediv2Value = RCC_HSE_PREDIV2_DIV5; 800a982: 2340 movs r3, #64 @ 0x40 800a984: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800a986: f107 0338 add.w r3, r7, #56 @ 0x38 800a98a: 4618 mov r0, r3 800a98c: f005 f8ec bl 800fb68 800a990: 4603 mov r3, r0 800a992: 2b00 cmp r3, #0 800a994: d001 beq.n 800a99a { Error_Handler(); 800a996: f000 f831 bl 800a9fc } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800a99a: 230f movs r3, #15 800a99c: 627b str r3, [r7, #36] @ 0x24 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800a99e: 2302 movs r3, #2 800a9a0: 62bb str r3, [r7, #40] @ 0x28 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800a9a2: 2300 movs r3, #0 800a9a4: 62fb str r3, [r7, #44] @ 0x2c RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 800a9a6: f44f 6380 mov.w r3, #1024 @ 0x400 800a9aa: 633b str r3, [r7, #48] @ 0x30 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 800a9ac: 2300 movs r3, #0 800a9ae: 637b str r3, [r7, #52] @ 0x34 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800a9b0: f107 0324 add.w r3, r7, #36 @ 0x24 800a9b4: 2102 movs r1, #2 800a9b6: 4618 mov r0, r3 800a9b8: f005 fbec bl 8010194 800a9bc: 4603 mov r3, r0 800a9be: 2b00 cmp r3, #0 800a9c0: d001 beq.n 800a9c6 { Error_Handler(); 800a9c2: f000 f81b bl 800a9fc } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; 800a9c6: 2303 movs r3, #3 800a9c8: 607b str r3, [r7, #4] PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 800a9ca: f44f 7380 mov.w r3, #256 @ 0x100 800a9ce: 60bb str r3, [r7, #8] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 800a9d0: f44f 4300 mov.w r3, #32768 @ 0x8000 800a9d4: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 800a9d6: 1d3b adds r3, r7, #4 800a9d8: 4618 mov r0, r3 800a9da: f005 fdd1 bl 8010580 800a9de: 4603 mov r3, r0 800a9e0: 2b00 cmp r3, #0 800a9e2: d001 beq.n 800a9e8 { Error_Handler(); 800a9e4: f000 f80a bl 800a9fc } /** Configure the Systick interrupt time */ __HAL_RCC_PLLI2S_ENABLE(); 800a9e8: 4b03 ldr r3, [pc, #12] @ (800a9f8 ) 800a9ea: 2201 movs r2, #1 800a9ec: 601a str r2, [r3, #0] } 800a9ee: bf00 nop 800a9f0: 3770 adds r7, #112 @ 0x70 800a9f2: 46bd mov sp, r7 800a9f4: bd80 pop {r7, pc} 800a9f6: bf00 nop 800a9f8: 42420070 .word 0x42420070 0800a9fc : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800a9fc: b480 push {r7} 800a9fe: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800aa00: b672 cpsid i } 800aa02: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 800aa04: bf00 nop 800aa06: e7fd b.n 800aa04 0800aa08 : METER_t METER; // Функция для расчета и накопления энергии c дробной частью без счетчиков void METER_CalculateEnergy() { 800aa08: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} 800aa0c: b084 sub sp, #16 800aa0e: af00 add r7, sp, #0 // Проверяем, что индекс находится в пределах массива METER.online = 0; 800aa10: 4b2e ldr r3, [pc, #184] @ (800aacc ) 800aa12: 2200 movs r2, #0 800aa14: 711a strb r2, [r3, #4] if(CONN.connState == Charging){ 800aa16: 4b2e ldr r3, [pc, #184] @ (800aad0 ) 800aa18: 785b ldrb r3, [r3, #1] 800aa1a: 2b08 cmp r3, #8 800aa1c: d104 bne.n 800aa28 METER.enable = 1; 800aa1e: 4b2b ldr r3, [pc, #172] @ (800aacc ) 800aa20: 2201 movs r2, #1 800aa22: f883 2024 strb.w r2, [r3, #36] @ 0x24 800aa26: e003 b.n 800aa30 }else{ METER.enable = 0; 800aa28: 4b28 ldr r3, [pc, #160] @ (800aacc ) 800aa2a: 2200 movs r2, #0 800aa2c: f883 2024 strb.w r2, [r3, #36] @ 0x24 } uint32_t currentTick = HAL_GetTick(); // Получаем текущее время в миллисекундах 800aa30: f002 ff94 bl 800d95c 800aa34: 60f8 str r0, [r7, #12] uint32_t elapsedTimeMs = currentTick - METER.lastTick; // Вычисляем время, прошедшее с последнего вызова в секундах 800aa36: 4b25 ldr r3, [pc, #148] @ (800aacc ) 800aa38: 689b ldr r3, [r3, #8] 800aa3a: 68fa ldr r2, [r7, #12] 800aa3c: 1ad3 subs r3, r2, r3 800aa3e: 60bb str r3, [r7, #8] METER.lastTick = currentTick; // Обновляем время последнего вызова для текущего коннектора 800aa40: 4a22 ldr r2, [pc, #136] @ (800aacc ) 800aa42: 68fb ldr r3, [r7, #12] 800aa44: 6093 str r3, [r2, #8] uint32_t energyWs = CONN.Power * elapsedTimeMs / 1000; // Рассчитываем энергию в ватт-секундах за прошедший промежуток времени 800aa46: 4b22 ldr r3, [pc, #136] @ (800aad0 ) 800aa48: f8d3 3003 ldr.w r3, [r3, #3] 800aa4c: 68ba ldr r2, [r7, #8] 800aa4e: fb02 f303 mul.w r3, r2, r3 800aa52: 4a20 ldr r2, [pc, #128] @ (800aad4 ) 800aa54: fba2 2303 umull r2, r3, r2, r3 800aa58: 099b lsrs r3, r3, #6 800aa5a: 607b str r3, [r7, #4] //Расчет энергии теперь идет всегда, смещение берем суммарное METER.EnergyPSU_Ws += energyWs; 800aa5c: 4b1b ldr r3, [pc, #108] @ (800aacc ) 800aa5e: e9d3 2304 ldrd r2, r3, [r3, #16] 800aa62: 6879 ldr r1, [r7, #4] 800aa64: 2000 movs r0, #0 800aa66: 460c mov r4, r1 800aa68: 4605 mov r5, r0 800aa6a: eb12 0804 adds.w r8, r2, r4 800aa6e: eb43 0905 adc.w r9, r3, r5 800aa72: 4b16 ldr r3, [pc, #88] @ (800aacc ) 800aa74: e9c3 8904 strd r8, r9, [r3, #16] // Абсолютное значение энергии разъема складывается из накопленной дробной части и значения со счетчиков METER.AbsoluteEnergy = (uint32_t)METER.EnergyPSU_Ws/3600; //переводим в Вт*час 800aa78: 4b14 ldr r3, [pc, #80] @ (800aacc ) 800aa7a: e9d3 2304 ldrd r2, r3, [r3, #16] 800aa7e: 4b16 ldr r3, [pc, #88] @ (800aad8 ) 800aa80: fba3 2302 umull r2, r3, r3, r2 800aa84: 0adb lsrs r3, r3, #11 800aa86: 4a11 ldr r2, [pc, #68] @ (800aacc ) 800aa88: 6193 str r3, [r2, #24] if(METER.enable) { 800aa8a: 4b10 ldr r3, [pc, #64] @ (800aacc ) 800aa8c: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800aa90: 2b00 cmp r3, #0 800aa92: d008 beq.n 800aaa6 //enabled state CONN.Energy = METER.AbsoluteEnergy - METER.EnergyOffset;//переводим в Вт*час 800aa94: 4b0d ldr r3, [pc, #52] @ (800aacc ) 800aa96: 699a ldr r2, [r3, #24] 800aa98: 4b0c ldr r3, [pc, #48] @ (800aacc ) 800aa9a: 69db ldr r3, [r3, #28] 800aa9c: 1ad3 subs r3, r2, r3 800aa9e: 4a0c ldr r2, [pc, #48] @ (800aad0 ) 800aaa0: f8c2 3007 str.w r3, [r2, #7] METER.EnergyOffset = METER.AbsoluteEnergy; } } 800aaa4: e00c b.n 800aac0 CONN.Energy = 0; 800aaa6: 4b0a ldr r3, [pc, #40] @ (800aad0 ) 800aaa8: 2200 movs r2, #0 800aaaa: 71da strb r2, [r3, #7] 800aaac: 2200 movs r2, #0 800aaae: 721a strb r2, [r3, #8] 800aab0: 2200 movs r2, #0 800aab2: 725a strb r2, [r3, #9] 800aab4: 2200 movs r2, #0 800aab6: 729a strb r2, [r3, #10] METER.EnergyOffset = METER.AbsoluteEnergy; 800aab8: 4b04 ldr r3, [pc, #16] @ (800aacc ) 800aaba: 699b ldr r3, [r3, #24] 800aabc: 4a03 ldr r2, [pc, #12] @ (800aacc ) 800aabe: 61d3 str r3, [r2, #28] } 800aac0: bf00 nop 800aac2: 3710 adds r7, #16 800aac4: 46bd mov sp, r7 800aac6: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} 800aaca: bf00 nop 800aacc: 200006b8 .word 0x200006b8 800aad0: 200001d4 .word 0x200001d4 800aad4: 10624dd3 .word 0x10624dd3 800aad8: 91a2b3c5 .word 0x91a2b3c5 0800aadc : uint32_t can_lastpacket; extern CAN_HandleTypeDef hcan2; static void PSU_SwitchState(PSU_State_t state){ 800aadc: b580 push {r7, lr} 800aade: b082 sub sp, #8 800aae0: af00 add r7, sp, #0 800aae2: 4603 mov r3, r0 800aae4: 71fb strb r3, [r7, #7] PSU0.state = state; 800aae6: 4a06 ldr r2, [pc, #24] @ (800ab00 ) 800aae8: 79fb ldrb r3, [r7, #7] 800aaea: 71d3 strb r3, [r2, #7] PSU0.statetick = HAL_GetTick(); 800aaec: f002 ff36 bl 800d95c 800aaf0: 4603 mov r3, r0 800aaf2: 4a03 ldr r2, [pc, #12] @ (800ab00 ) 800aaf4: 6113 str r3, [r2, #16] } 800aaf6: bf00 nop 800aaf8: 3708 adds r7, #8 800aafa: 46bd mov sp, r7 800aafc: bd80 pop {r7, pc} 800aafe: bf00 nop 800ab00: 20000724 .word 0x20000724 0800ab04 : static uint32_t PSU_StateTime(void){ 800ab04: b580 push {r7, lr} 800ab06: af00 add r7, sp, #0 return HAL_GetTick() - PSU0.statetick; 800ab08: f002 ff28 bl 800d95c 800ab0c: 4602 mov r2, r0 800ab0e: 4b02 ldr r3, [pc, #8] @ (800ab18 ) 800ab10: 691b ldr r3, [r3, #16] 800ab12: 1ad3 subs r3, r2, r3 } 800ab14: 4618 mov r0, r3 800ab16: bd80 pop {r7, pc} 800ab18: 20000724 .word 0x20000724 0800ab1c : void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan){ 800ab1c: b580 push {r7, lr} 800ab1e: b084 sub sp, #16 800ab20: af00 add r7, sp, #0 800ab22: 6078 str r0, [r7, #4] static CAN_RxHeaderTypeDef RxHeader; static uint8_t RxData[8] = {0,}; CanId_t CanId; if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO1, &RxHeader, RxData) == HAL_OK) 800ab24: 4b88 ldr r3, [pc, #544] @ (800ad48 ) 800ab26: 4a89 ldr r2, [pc, #548] @ (800ad4c ) 800ab28: 2101 movs r1, #1 800ab2a: 6878 ldr r0, [r7, #4] 800ab2c: f003 ffb6 bl 800ea9c 800ab30: 4603 mov r3, r0 800ab32: 2b00 cmp r3, #0 800ab34: f040 8104 bne.w 800ad40 { memcpy(&CanId, &RxHeader.ExtId, sizeof(CanId_t)); 800ab38: 4b84 ldr r3, [pc, #528] @ (800ad4c ) 800ab3a: 685b ldr r3, [r3, #4] 800ab3c: 60bb str r3, [r7, #8] /* Для DC30 поддерживается только один силовой модуль (source == 0) */ if(CanId.source != 0) return; 800ab3e: 7a3b ldrb r3, [r7, #8] 800ab40: 2b00 cmp r3, #0 800ab42: f040 80fc bne.w 800ad3e can_lastpacket = HAL_GetTick(); 800ab46: f002 ff09 bl 800d95c 800ab4a: 4603 mov r3, r0 800ab4c: 4a80 ldr r2, [pc, #512] @ (800ad50 ) 800ab4e: 6013 str r3, [r2, #0] if(CanId.command==0x02){ 800ab50: 7abb ldrb r3, [r7, #10] 800ab52: f003 033f and.w r3, r3, #63 @ 0x3f 800ab56: b2db uxtb r3, r3 800ab58: 2b02 cmp r3, #2 800ab5a: d105 bne.n 800ab68 memcpy(&PSU_02, RxData, 8); 800ab5c: 4b7d ldr r3, [pc, #500] @ (800ad54 ) 800ab5e: 4a7a ldr r2, [pc, #488] @ (800ad48 ) 800ab60: e892 0003 ldmia.w r2, {r0, r1} 800ab64: e883 0003 stmia.w r3, {r0, r1} } if(CanId.command==0x04){ 800ab68: 7abb ldrb r3, [r7, #10] 800ab6a: f003 033f and.w r3, r3, #63 @ 0x3f 800ab6e: b2db uxtb r3, r3 800ab70: 2b04 cmp r3, #4 800ab72: d119 bne.n 800aba8 memcpy(&PSU_04, RxData, 8); 800ab74: 4b78 ldr r3, [pc, #480] @ (800ad58 ) 800ab76: 4a74 ldr r2, [pc, #464] @ (800ad48 ) 800ab78: e892 0003 ldmia.w r2, {r0, r1} 800ab7c: e883 0003 stmia.w r3, {r0, r1} PSU0.tempAmbient = PSU_04.moduleTemperature; 800ab80: 4b75 ldr r3, [pc, #468] @ (800ad58 ) 800ab82: 791b ldrb r3, [r3, #4] 800ab84: 461a mov r2, r3 800ab86: 4b75 ldr r3, [pc, #468] @ (800ad5c ) 800ab88: 61da str r2, [r3, #28] PSU0.status0.raw = PSU_04.modularForm0; 800ab8a: 4b73 ldr r3, [pc, #460] @ (800ad58 ) 800ab8c: 7a1a ldrb r2, [r3, #8] 800ab8e: 4b73 ldr r3, [pc, #460] @ (800ad5c ) 800ab90: f883 2020 strb.w r2, [r3, #32] PSU0.status1.raw = PSU_04.modularForm1; 800ab94: 4b70 ldr r3, [pc, #448] @ (800ad58 ) 800ab96: 79da ldrb r2, [r3, #7] 800ab98: 4b70 ldr r3, [pc, #448] @ (800ad5c ) 800ab9a: f883 2021 strb.w r2, [r3, #33] @ 0x21 PSU0.status2.raw = PSU_04.modularForm2; 800ab9e: 4b6e ldr r3, [pc, #440] @ (800ad58 ) 800aba0: 799a ldrb r2, [r3, #6] 800aba2: 4b6e ldr r3, [pc, #440] @ (800ad5c ) 800aba4: f883 2022 strb.w r2, [r3, #34] @ 0x22 } if(CanId.command==0x06){ 800aba8: 7abb ldrb r3, [r7, #10] 800abaa: f003 033f and.w r3, r3, #63 @ 0x3f 800abae: b2db uxtb r3, r3 800abb0: 2b06 cmp r3, #6 800abb2: d123 bne.n 800abfc memcpy(&PSU_06, RxData, 8); 800abb4: 4b6a ldr r3, [pc, #424] @ (800ad60 ) 800abb6: 4a64 ldr r2, [pc, #400] @ (800ad48 ) 800abb8: e892 0003 ldmia.w r2, {r0, r1} 800abbc: e883 0003 stmia.w r3, {r0, r1} PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800abc0: 4b67 ldr r3, [pc, #412] @ (800ad60 ) 800abc2: 785b ldrb r3, [r3, #1] 800abc4: 461a mov r2, r3 800abc6: 4b66 ldr r3, [pc, #408] @ (800ad60 ) 800abc8: 781b ldrb r3, [r3, #0] 800abca: 021b lsls r3, r3, #8 800abcc: 4413 add r3, r2 800abce: 461a mov r2, r3 800abd0: 4b63 ldr r3, [pc, #396] @ (800ad60 ) 800abd2: 609a str r2, [r3, #8] PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800abd4: 4b62 ldr r3, [pc, #392] @ (800ad60 ) 800abd6: 78db ldrb r3, [r3, #3] 800abd8: 461a mov r2, r3 800abda: 4b61 ldr r3, [pc, #388] @ (800ad60 ) 800abdc: 789b ldrb r3, [r3, #2] 800abde: 021b lsls r3, r3, #8 800abe0: 4413 add r3, r2 800abe2: 461a mov r2, r3 800abe4: 4b5e ldr r3, [pc, #376] @ (800ad60 ) 800abe6: 60da str r2, [r3, #12] PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800abe8: 4b5d ldr r3, [pc, #372] @ (800ad60 ) 800abea: 795b ldrb r3, [r3, #5] 800abec: 461a mov r2, r3 800abee: 4b5c ldr r3, [pc, #368] @ (800ad60 ) 800abf0: 791b ldrb r3, [r3, #4] 800abf2: 021b lsls r3, r3, #8 800abf4: 4413 add r3, r2 800abf6: 461a mov r2, r3 800abf8: 4b59 ldr r3, [pc, #356] @ (800ad60 ) 800abfa: 611a str r2, [r3, #16] } if(CanId.command==0x08){ 800abfc: 7abb ldrb r3, [r7, #10] 800abfe: f003 033f and.w r3, r3, #63 @ 0x3f 800ac02: b2db uxtb r3, r3 800ac04: 2b08 cmp r3, #8 800ac06: d105 bne.n 800ac14 memcpy(&PSU_08, RxData, 8); 800ac08: 4b56 ldr r3, [pc, #344] @ (800ad64 ) 800ac0a: 4a4f ldr r2, [pc, #316] @ (800ad48 ) 800ac0c: e892 0003 ldmia.w r2, {r0, r1} 800ac10: e883 0003 stmia.w r3, {r0, r1} } if(CanId.command==0x09){ 800ac14: 7abb ldrb r3, [r7, #10] 800ac16: f003 033f and.w r3, r3, #63 @ 0x3f 800ac1a: b2db uxtb r3, r3 800ac1c: 2b09 cmp r3, #9 800ac1e: f040 808f bne.w 800ad40 memcpy(&PSU_09, RxData, 8); 800ac22: 4b51 ldr r3, [pc, #324] @ (800ad68 ) 800ac24: 4a48 ldr r2, [pc, #288] @ (800ad48 ) 800ac26: e892 0003 ldmia.w r2, {r0, r1} 800ac2a: e883 0003 stmia.w r3, {r0, r1} PSU_09.moduleNCurrent = PSU_09.moduleNCurrent_[3]; 800ac2e: 4b4e ldr r3, [pc, #312] @ (800ad68 ) 800ac30: 79db ldrb r3, [r3, #7] 800ac32: 461a mov r2, r3 800ac34: 4b4c ldr r3, [pc, #304] @ (800ad68 ) 800ac36: 60da str r2, [r3, #12] PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[2]<<8; 800ac38: 4b4b ldr r3, [pc, #300] @ (800ad68 ) 800ac3a: 68da ldr r2, [r3, #12] 800ac3c: 4b4a ldr r3, [pc, #296] @ (800ad68 ) 800ac3e: 799b ldrb r3, [r3, #6] 800ac40: 021b lsls r3, r3, #8 800ac42: 4313 orrs r3, r2 800ac44: 4a48 ldr r2, [pc, #288] @ (800ad68 ) 800ac46: 60d3 str r3, [r2, #12] PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[1]<<16; 800ac48: 4b47 ldr r3, [pc, #284] @ (800ad68 ) 800ac4a: 68da ldr r2, [r3, #12] 800ac4c: 4b46 ldr r3, [pc, #280] @ (800ad68 ) 800ac4e: 795b ldrb r3, [r3, #5] 800ac50: 041b lsls r3, r3, #16 800ac52: 4313 orrs r3, r2 800ac54: 4a44 ldr r2, [pc, #272] @ (800ad68 ) 800ac56: 60d3 str r3, [r2, #12] PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[0]<<24; 800ac58: 4b43 ldr r3, [pc, #268] @ (800ad68 ) 800ac5a: 68da ldr r2, [r3, #12] 800ac5c: 4b42 ldr r3, [pc, #264] @ (800ad68 ) 800ac5e: 791b ldrb r3, [r3, #4] 800ac60: 061b lsls r3, r3, #24 800ac62: 4313 orrs r3, r2 800ac64: 4a40 ldr r2, [pc, #256] @ (800ad68 ) 800ac66: 60d3 str r3, [r2, #12] PSU_09.moduleNVoltage = PSU_09.moduleNVoltage_[3]; 800ac68: 4b3f ldr r3, [pc, #252] @ (800ad68 ) 800ac6a: 78db ldrb r3, [r3, #3] 800ac6c: 461a mov r2, r3 800ac6e: 4b3e ldr r3, [pc, #248] @ (800ad68 ) 800ac70: 609a str r2, [r3, #8] PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[2]<<8; 800ac72: 4b3d ldr r3, [pc, #244] @ (800ad68 ) 800ac74: 689a ldr r2, [r3, #8] 800ac76: 4b3c ldr r3, [pc, #240] @ (800ad68 ) 800ac78: 789b ldrb r3, [r3, #2] 800ac7a: 021b lsls r3, r3, #8 800ac7c: 4313 orrs r3, r2 800ac7e: 4a3a ldr r2, [pc, #232] @ (800ad68 ) 800ac80: 6093 str r3, [r2, #8] PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[1]<<16; 800ac82: 4b39 ldr r3, [pc, #228] @ (800ad68 ) 800ac84: 689a ldr r2, [r3, #8] 800ac86: 4b38 ldr r3, [pc, #224] @ (800ad68 ) 800ac88: 785b ldrb r3, [r3, #1] 800ac8a: 041b lsls r3, r3, #16 800ac8c: 4313 orrs r3, r2 800ac8e: 4a36 ldr r2, [pc, #216] @ (800ad68 ) 800ac90: 6093 str r3, [r2, #8] PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[0]<<24; 800ac92: 4b35 ldr r3, [pc, #212] @ (800ad68 ) 800ac94: 689a ldr r2, [r3, #8] 800ac96: 4b34 ldr r3, [pc, #208] @ (800ad68 ) 800ac98: 781b ldrb r3, [r3, #0] 800ac9a: 061b lsls r3, r3, #24 800ac9c: 4313 orrs r3, r2 800ac9e: 4a32 ldr r2, [pc, #200] @ (800ad68 ) 800aca0: 6093 str r3, [r2, #8] // PSU_09 -> PSU -> CONN (один модуль) { uint16_t v = PSU_09.moduleNVoltage / 1000; 800aca2: 4b31 ldr r3, [pc, #196] @ (800ad68 ) 800aca4: 689b ldr r3, [r3, #8] 800aca6: 4a31 ldr r2, [pc, #196] @ (800ad6c ) 800aca8: fba2 2303 umull r2, r3, r2, r3 800acac: 099b lsrs r3, r3, #6 800acae: 81fb strh r3, [r7, #14] int16_t i = PSU_09.moduleNCurrent / 100; 800acb0: 4b2d ldr r3, [pc, #180] @ (800ad68 ) 800acb2: 68db ldr r3, [r3, #12] 800acb4: 4a2e ldr r2, [pc, #184] @ (800ad70 ) 800acb6: fba2 2303 umull r2, r3, r2, r3 800acba: 095b lsrs r3, r3, #5 800acbc: 81bb strh r3, [r7, #12] // Обновляем модель PSU0 по телеметрии PSU0.outputVoltage = v; 800acbe: 4a27 ldr r2, [pc, #156] @ (800ad5c ) 800acc0: 89fb ldrh r3, [r7, #14] 800acc2: 8053 strh r3, [r2, #2] PSU0.outputCurrent = i; 800acc4: 4a25 ldr r2, [pc, #148] @ (800ad5c ) 800acc6: 89bb ldrh r3, [r7, #12] 800acc8: 8093 strh r3, [r2, #4] PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800acca: 89fb ldrh r3, [r7, #14] 800accc: 2b13 cmp r3, #19 800acce: bf8c ite hi 800acd0: 2301 movhi r3, #1 800acd2: 2300 movls r3, #0 800acd4: b2db uxtb r3, r3 800acd6: 461a mov r2, r3 800acd8: 4b20 ldr r3, [pc, #128] @ (800ad5c ) 800acda: 729a strb r2, [r3, #10] PSU0.online = 1; 800acdc: 4b1f ldr r3, [pc, #124] @ (800ad5c ) 800acde: 2201 movs r2, #1 800ace0: 721a strb r2, [r3, #8] PSU0.temperature = PSU_04.moduleTemperature; 800ace2: 4b1d ldr r3, [pc, #116] @ (800ad58 ) 800ace4: 791a ldrb r2, [r3, #4] 800ace6: 4b1d ldr r3, [pc, #116] @ (800ad5c ) 800ace8: 719a strb r2, [r3, #6] // Экспортируем значения из PSU0 в CONN только, // когда модуль хотя бы в состоянии READY и выше if(PSU0.state >= PSU_READY){ 800acea: 4b1c ldr r3, [pc, #112] @ (800ad5c ) 800acec: 79db ldrb r3, [r3, #7] 800acee: 2b01 cmp r3, #1 800acf0: d926 bls.n 800ad40 CONN.MeasuredVoltage = PSU0.outputVoltage; 800acf2: 4b1a ldr r3, [pc, #104] @ (800ad5c ) 800acf4: 885a ldrh r2, [r3, #2] 800acf6: 4b1f ldr r3, [pc, #124] @ (800ad74 ) 800acf8: f8a3 2013 strh.w r2, [r3, #19] CONN.MeasuredCurrent = PSU0.outputCurrent; 800acfc: 4b17 ldr r3, [pc, #92] @ (800ad5c ) 800acfe: f9b3 3004 ldrsh.w r3, [r3, #4] 800ad02: b29a uxth r2, r3 800ad04: 4b1b ldr r3, [pc, #108] @ (800ad74 ) 800ad06: f8a3 2015 strh.w r2, [r3, #21] CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800ad0a: 4b1a ldr r3, [pc, #104] @ (800ad74 ) 800ad0c: f8b3 3015 ldrh.w r3, [r3, #21] 800ad10: b29b uxth r3, r3 800ad12: 461a mov r2, r3 800ad14: 4b17 ldr r3, [pc, #92] @ (800ad74 ) 800ad16: f8b3 3013 ldrh.w r3, [r3, #19] 800ad1a: b29b uxth r3, r3 800ad1c: fb02 f303 mul.w r3, r2, r3 800ad20: 4a15 ldr r2, [pc, #84] @ (800ad78 ) 800ad22: fb82 1203 smull r1, r2, r2, r3 800ad26: 1092 asrs r2, r2, #2 800ad28: 17db asrs r3, r3, #31 800ad2a: 1ad3 subs r3, r2, r3 800ad2c: 461a mov r2, r3 800ad2e: 4b11 ldr r3, [pc, #68] @ (800ad74 ) 800ad30: f8c3 2003 str.w r2, [r3, #3] CONN.outputEnabled = PSU0.PSU_enabled; 800ad34: 4b09 ldr r3, [pc, #36] @ (800ad5c ) 800ad36: 7a9a ldrb r2, [r3, #10] 800ad38: 4b0e ldr r3, [pc, #56] @ (800ad74 ) 800ad3a: 761a strb r2, [r3, #24] 800ad3c: e000 b.n 800ad40 if(CanId.source != 0) return; 800ad3e: bf00 nop } } } } } 800ad40: 3710 adds r7, #16 800ad42: 46bd mov sp, r7 800ad44: bd80 pop {r7, pc} 800ad46: bf00 nop 800ad48: 20000768 .word 0x20000768 800ad4c: 2000074c .word 0x2000074c 800ad50: 20000748 .word 0x20000748 800ad54: 200006e0 .word 0x200006e0 800ad58: 200006ec .word 0x200006ec 800ad5c: 20000724 .word 0x20000724 800ad60: 200006f8 .word 0x200006f8 800ad64: 2000070c .word 0x2000070c 800ad68: 20000714 .word 0x20000714 800ad6c: 10624dd3 .word 0x10624dd3 800ad70: 51eb851f .word 0x51eb851f 800ad74: 200001d4 .word 0x200001d4 800ad78: 66666667 .word 0x66666667 0800ad7c : void PSU_CAN_FilterInit(){ 800ad7c: b580 push {r7, lr} 800ad7e: b08a sub sp, #40 @ 0x28 800ad80: af00 add r7, sp, #0 CAN_FilterTypeDef sFilterConfig; sFilterConfig.FilterBank = 14; 800ad82: 230e movs r3, #14 800ad84: 617b str r3, [r7, #20] sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; 800ad86: 2300 movs r3, #0 800ad88: 61bb str r3, [r7, #24] sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; 800ad8a: 2301 movs r3, #1 800ad8c: 61fb str r3, [r7, #28] sFilterConfig.FilterIdHigh = 0x0000; 800ad8e: 2300 movs r3, #0 800ad90: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = 0x0000; 800ad92: 2300 movs r3, #0 800ad94: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 800ad96: 2300 movs r3, #0 800ad98: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = 0x0000; 800ad9a: 2300 movs r3, #0 800ad9c: 60fb str r3, [r7, #12] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; 800ad9e: 2300 movs r3, #0 800ada0: 613b str r3, [r7, #16] sFilterConfig.FilterActivation = ENABLE; 800ada2: 2301 movs r3, #1 800ada4: 623b str r3, [r7, #32] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 800ada6: 2301 movs r3, #1 800ada8: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 800adaa: 230e movs r3, #14 800adac: 627b str r3, [r7, #36] @ 0x24 if(HAL_CAN_ConfigFilter(&hcan2, &sFilterConfig) != HAL_OK) 800adae: 463b mov r3, r7 800adb0: 4619 mov r1, r3 800adb2: 4806 ldr r0, [pc, #24] @ (800adcc ) 800adb4: f003 fc02 bl 800e5bc 800adb8: 4603 mov r3, r0 800adba: 2b00 cmp r3, #0 800adbc: d001 beq.n 800adc2 { Error_Handler(); 800adbe: f7ff fe1d bl 800a9fc } } 800adc2: bf00 nop 800adc4: 3728 adds r7, #40 @ 0x28 800adc6: 46bd mov sp, r7 800adc8: bd80 pop {r7, pc} 800adca: bf00 nop 800adcc: 200001a8 .word 0x200001a8 0800add0 : void PSU_Init(){ 800add0: b580 push {r7, lr} 800add2: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan2); 800add4: 4813 ldr r0, [pc, #76] @ (800ae24 ) 800add6: f003 fd15 bl 800e804 MX_CAN2_Init(); 800adda: f7fe fdd9 bl 8009990 PSU_CAN_FilterInit(); 800adde: f7ff ffcd bl 800ad7c HAL_CAN_Start(&hcan2); 800ade2: 4810 ldr r0, [pc, #64] @ (800ae24 ) 800ade4: f003 fcca bl 800e77c HAL_CAN_ActivateNotification(&hcan2, CAN_IT_RX_FIFO1_MSG_PENDING /* | CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | CAN_IT_TX_MAILBOX_EMPTY*/); 800ade8: 2110 movs r1, #16 800adea: 480e ldr r0, [pc, #56] @ (800ae24 ) 800adec: f003 ff77 bl 800ecde memset(&PSU0, 0, sizeof(PSU0)); 800adf0: 2224 movs r2, #36 @ 0x24 800adf2: 2100 movs r1, #0 800adf4: 480c ldr r0, [pc, #48] @ (800ae28 ) 800adf6: f008 f923 bl 8013040 PSU0.state = PSU_UNREADY; 800adfa: 4b0b ldr r3, [pc, #44] @ (800ae28 ) 800adfc: 2200 movs r2, #0 800adfe: 71da strb r2, [r3, #7] PSU0.statetick = HAL_GetTick(); 800ae00: f002 fdac bl 800d95c 800ae04: 4603 mov r3, r0 800ae06: 4a08 ldr r2, [pc, #32] @ (800ae28 ) 800ae08: 6113 str r3, [r2, #16] PSU0.power_limit = PSU_MAX_POWER; // kW 800ae0a: 4b07 ldr r3, [pc, #28] @ (800ae28 ) 800ae0c: f247 5230 movw r2, #30000 @ 0x7530 800ae10: 615a str r2, [r3, #20] PSU0.hv_mode = 0; 800ae12: 4b05 ldr r3, [pc, #20] @ (800ae28 ) 800ae14: 2200 movs r2, #0 800ae16: 761a strb r2, [r3, #24] PSU_Enable(0, 0); 800ae18: 2100 movs r1, #0 800ae1a: 2000 movs r0, #0 800ae1c: f000 f806 bl 800ae2c } 800ae20: bf00 nop 800ae22: bd80 pop {r7, pc} 800ae24: 200001a8 .word 0x200001a8 800ae28: 20000724 .word 0x20000724 0800ae2c : void PSU_Enable(uint8_t addr, uint8_t enable){ 800ae2c: b580 push {r7, lr} 800ae2e: b084 sub sp, #16 800ae30: af00 add r7, sp, #0 800ae32: 4603 mov r3, r0 800ae34: 460a mov r2, r1 800ae36: 71fb strb r3, [r7, #7] 800ae38: 4613 mov r3, r2 800ae3a: 71bb strb r3, [r7, #6] PSU_1A_t data; memset(&data, 0, sizeof(data)); 800ae3c: f107 0308 add.w r3, r7, #8 800ae40: 2208 movs r2, #8 800ae42: 2100 movs r1, #0 800ae44: 4618 mov r0, r3 800ae46: f008 f8fb bl 8013040 /* Для DC30 поддерживается только один модуль с адресом 0 */ if(addr != 0) return; 800ae4a: 79fb ldrb r3, [r7, #7] 800ae4c: 2b00 cmp r3, #0 800ae4e: d115 bne.n 800ae7c if(PSU0.online == 0) return; 800ae50: 4b0d ldr r3, [pc, #52] @ (800ae88 ) 800ae52: 7a1b ldrb r3, [r3, #8] 800ae54: 2b00 cmp r3, #0 800ae56: d013 beq.n 800ae80 data.enable = !enable; 800ae58: 79bb ldrb r3, [r7, #6] 800ae5a: 2b00 cmp r3, #0 800ae5c: bf0c ite eq 800ae5e: 2301 moveq r3, #1 800ae60: 2300 movne r3, #0 800ae62: b2db uxtb r3, r3 800ae64: 723b strb r3, [r7, #8] PSU_SendCmd(0xF0, addr, 0x1A, &data); 800ae66: 79f9 ldrb r1, [r7, #7] 800ae68: f107 0308 add.w r3, r7, #8 800ae6c: 221a movs r2, #26 800ae6e: 20f0 movs r0, #240 @ 0xf0 800ae70: f000 f866 bl 800af40 ED_Delay(CAN_DELAY); 800ae74: 2014 movs r0, #20 800ae76: f7ff fc7d bl 800a774 800ae7a: e002 b.n 800ae82 if(addr != 0) return; 800ae7c: bf00 nop 800ae7e: e000 b.n 800ae82 if(PSU0.online == 0) return; 800ae80: bf00 nop } 800ae82: 3710 adds r7, #16 800ae84: 46bd mov sp, r7 800ae86: bd80 pop {r7, pc} 800ae88: 20000724 .word 0x20000724 0800ae8c : memset(&data, 0, sizeof(data)); data.enable = !enable; if(addr != 0) return; PSU_SendCmd(0xF0, addr, 0x1D, &data); } void PSU_SetVoltageCurrent(uint8_t addr, uint16_t voltage, uint16_t current){ 800ae8c: b580 push {r7, lr} 800ae8e: b086 sub sp, #24 800ae90: af00 add r7, sp, #0 800ae92: 4603 mov r3, r0 800ae94: 71fb strb r3, [r7, #7] 800ae96: 460b mov r3, r1 800ae98: 80bb strh r3, [r7, #4] 800ae9a: 4613 mov r3, r2 800ae9c: 807b strh r3, [r7, #2] PSU_1C_t data; memset(&data, 0, sizeof(data)); 800ae9e: f107 0308 add.w r3, r7, #8 800aea2: 2208 movs r2, #8 800aea4: 2100 movs r1, #0 800aea6: 4618 mov r0, r3 800aea8: f008 f8ca bl 8013040 if(addr != 0) return; 800aeac: 79fb ldrb r3, [r7, #7] 800aeae: 2b00 cmp r3, #0 800aeb0: d140 bne.n 800af34 if(voltage 800aeb8: 2396 movs r3, #150 @ 0x96 800aeba: 80bb strh r3, [r7, #4] if((PSU0.hv_mode==0) && voltage>499) voltage = 499; 800aebc: 4b1f ldr r3, [pc, #124] @ (800af3c ) 800aebe: 7e1b ldrb r3, [r3, #24] 800aec0: 2b00 cmp r3, #0 800aec2: d106 bne.n 800aed2 800aec4: 88bb ldrh r3, [r7, #4] 800aec6: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800aeca: d302 bcc.n 800aed2 800aecc: f240 13f3 movw r3, #499 @ 0x1f3 800aed0: 80bb strh r3, [r7, #4] uint32_t current_ma = current * 100; 800aed2: 887b ldrh r3, [r7, #2] 800aed4: 2264 movs r2, #100 @ 0x64 800aed6: fb02 f303 mul.w r3, r2, r3 800aeda: 617b str r3, [r7, #20] uint32_t voltage_mv = voltage * 1000; 800aedc: 88bb ldrh r3, [r7, #4] 800aede: f44f 727a mov.w r2, #1000 @ 0x3e8 800aee2: fb02 f303 mul.w r3, r2, r3 800aee6: 613b str r3, [r7, #16] data.moduleCurrentTotal[0] = (current_ma >> 24) & 0xFF; 800aee8: 697b ldr r3, [r7, #20] 800aeea: 0e1b lsrs r3, r3, #24 800aeec: b2db uxtb r3, r3 800aeee: 733b strb r3, [r7, #12] data.moduleCurrentTotal[1] = (current_ma >> 16) & 0xFF; 800aef0: 697b ldr r3, [r7, #20] 800aef2: 0c1b lsrs r3, r3, #16 800aef4: b2db uxtb r3, r3 800aef6: 737b strb r3, [r7, #13] data.moduleCurrentTotal[2] = (current_ma >> 8) & 0xFF; 800aef8: 697b ldr r3, [r7, #20] 800aefa: 0a1b lsrs r3, r3, #8 800aefc: b2db uxtb r3, r3 800aefe: 73bb strb r3, [r7, #14] data.moduleCurrentTotal[3] = (current_ma >> 0) & 0xFF; 800af00: 697b ldr r3, [r7, #20] 800af02: b2db uxtb r3, r3 800af04: 73fb strb r3, [r7, #15] data.moduleVoltage[0] = (voltage_mv >> 24) & 0xFF; 800af06: 693b ldr r3, [r7, #16] 800af08: 0e1b lsrs r3, r3, #24 800af0a: b2db uxtb r3, r3 800af0c: 723b strb r3, [r7, #8] data.moduleVoltage[1] = (voltage_mv >> 16) & 0xFF; 800af0e: 693b ldr r3, [r7, #16] 800af10: 0c1b lsrs r3, r3, #16 800af12: b2db uxtb r3, r3 800af14: 727b strb r3, [r7, #9] data.moduleVoltage[2] = (voltage_mv >> 8) & 0xFF; 800af16: 693b ldr r3, [r7, #16] 800af18: 0a1b lsrs r3, r3, #8 800af1a: b2db uxtb r3, r3 800af1c: 72bb strb r3, [r7, #10] data.moduleVoltage[3] = (voltage_mv >> 0) & 0xFF; 800af1e: 693b ldr r3, [r7, #16] 800af20: b2db uxtb r3, r3 800af22: 72fb strb r3, [r7, #11] PSU_SendCmd(0xF0, addr, 0x1C, &data); 800af24: 79f9 ldrb r1, [r7, #7] 800af26: f107 0308 add.w r3, r7, #8 800af2a: 221c movs r2, #28 800af2c: 20f0 movs r0, #240 @ 0xf0 800af2e: f000 f807 bl 800af40 800af32: e000 b.n 800af36 if(addr != 0) return; 800af34: bf00 nop } 800af36: 3718 adds r7, #24 800af38: 46bd mov sp, r7 800af3a: bd80 pop {r7, pc} 800af3c: 20000724 .word 0x20000724 0800af40 : void PSU_SendCmd(uint8_t source, uint8_t destination, uint8_t cmd, void *data){ 800af40: b580 push {r7, lr} 800af42: b08c sub sp, #48 @ 0x30 800af44: af00 add r7, sp, #0 800af46: 603b str r3, [r7, #0] 800af48: 4603 mov r3, r0 800af4a: 71fb strb r3, [r7, #7] 800af4c: 460b mov r3, r1 800af4e: 71bb strb r3, [r7, #6] 800af50: 4613 mov r3, r2 800af52: 717b strb r3, [r7, #5] CanId_t CanId; CanId.source = source; 800af54: 79fb ldrb r3, [r7, #7] 800af56: f887 3028 strb.w r3, [r7, #40] @ 0x28 CanId.destination = destination; 800af5a: 79bb ldrb r3, [r7, #6] 800af5c: f887 3029 strb.w r3, [r7, #41] @ 0x29 CanId.command = cmd; 800af60: 797b ldrb r3, [r7, #5] 800af62: f003 033f and.w r3, r3, #63 @ 0x3f 800af66: b2da uxtb r2, r3 800af68: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 800af6c: f362 0305 bfi r3, r2, #0, #6 800af70: f887 302a strb.w r3, [r7, #42] @ 0x2a CanId.device = 0x0A; 800af74: 8d7b ldrh r3, [r7, #42] @ 0x2a 800af76: 220a movs r2, #10 800af78: f362 1389 bfi r3, r2, #6, #4 800af7c: 857b strh r3, [r7, #42] @ 0x2a int8_t retry_counter = 10; 800af7e: 230a movs r3, #10 800af80: f887 302f strb.w r3, [r7, #47] @ 0x2f CAN_TxHeaderTypeDef tx_header; uint32_t tx_mailbox; HAL_StatusTypeDef CAN_result; memcpy(&tx_header.ExtId, &CanId, sizeof(CanId_t)); 800af84: 6abb ldr r3, [r7, #40] @ 0x28 800af86: 617b str r3, [r7, #20] tx_header.RTR = CAN_RTR_DATA; 800af88: 2300 movs r3, #0 800af8a: 61fb str r3, [r7, #28] tx_header.IDE = CAN_ID_EXT; 800af8c: 2304 movs r3, #4 800af8e: 61bb str r3, [r7, #24] tx_header.DLC = 8; 800af90: 2308 movs r3, #8 800af92: 623b str r3, [r7, #32] while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800af94: e01e b.n 800afd4 if (HAL_CAN_GetTxMailboxesFreeLevel(&hcan2) > 0){ 800af96: 4814 ldr r0, [pc, #80] @ (800afe8 ) 800af98: f003 fd4c bl 800ea34 800af9c: 4603 mov r3, r0 800af9e: 2b00 cmp r3, #0 800afa0: d00e beq.n 800afc0 /* отправка сообщения */ CAN_result = HAL_CAN_AddTxMessage(&hcan2, &tx_header, (uint8_t*)data, &tx_mailbox); 800afa2: f107 030c add.w r3, r7, #12 800afa6: f107 0110 add.w r1, r7, #16 800afaa: 683a ldr r2, [r7, #0] 800afac: 480e ldr r0, [pc, #56] @ (800afe8 ) 800afae: f003 fc72 bl 800e896 800afb2: 4603 mov r3, r0 800afb4: f887 302e strb.w r3, [r7, #46] @ 0x2e /* если отправка удалась, выход */ if(CAN_result == HAL_OK) { 800afb8: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 800afbc: 2b00 cmp r3, #0 800afbe: d00e beq.n 800afde return; retry_counter = 0; } } ED_Delay(1); 800afc0: 2001 movs r0, #1 800afc2: f7ff fbd7 bl 800a774 retry_counter--; 800afc6: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800afca: b2db uxtb r3, r3 800afcc: 3b01 subs r3, #1 800afce: b2db uxtb r3, r3 800afd0: f887 302f strb.w r3, [r7, #47] @ 0x2f while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800afd4: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800afd8: 2b00 cmp r3, #0 800afda: dcdc bgt.n 800af96 800afdc: e000 b.n 800afe0 return; 800afde: bf00 nop } } 800afe0: 3730 adds r7, #48 @ 0x30 800afe2: 46bd mov sp, r7 800afe4: bd80 pop {r7, pc} 800afe6: bf00 nop 800afe8: 200001a8 .word 0x200001a8 0800afec : uint32_t max(uint32_t a, uint32_t b){ if(a>b) return a; else return b; } void PSU_ReadWrite(){ 800afec: b580 push {r7, lr} 800afee: b082 sub sp, #8 800aff0: af00 add r7, sp, #0 uint8_t zero_data[8] = {0,0,0,0,0,0,0,0}; 800aff2: 463b mov r3, r7 800aff4: 2200 movs r2, #0 800aff6: 601a str r2, [r3, #0] 800aff8: 605a str r2, [r3, #4] PSU_SendCmd(0xF0, 0, 0x04, zero_data);ED_Delay(CAN_DELAY); 800affa: 463b mov r3, r7 800affc: 2204 movs r2, #4 800affe: 2100 movs r1, #0 800b000: 20f0 movs r0, #240 @ 0xf0 800b002: f7ff ff9d bl 800af40 800b006: 2014 movs r0, #20 800b008: f7ff fbb4 bl 800a774 PSU_SendCmd(0xF0, 0, 0x06, zero_data);ED_Delay(CAN_DELAY); 800b00c: 463b mov r3, r7 800b00e: 2206 movs r2, #6 800b010: 2100 movs r1, #0 800b012: 20f0 movs r0, #240 @ 0xf0 800b014: f7ff ff94 bl 800af40 800b018: 2014 movs r0, #20 800b01a: f7ff fbab bl 800a774 // PSU_SendCmd(0xF0, 0, 0x08, zero_data);ED_Delay(CAN_DELAY); PSU_SendCmd(0xF0, 0, 0x09, zero_data);ED_Delay(CAN_DELAY); 800b01e: 463b mov r3, r7 800b020: 2209 movs r2, #9 800b022: 2100 movs r1, #0 800b024: 20f0 movs r0, #240 @ 0xf0 800b026: f7ff ff8b bl 800af40 800b02a: 2014 movs r0, #20 800b02c: f7ff fba2 bl 800a774 // Power Limit if ((CONN.WantedCurrent/10) * CONN.MeasuredVoltage > PSU0.power_limit){ 800b030: 4b3a ldr r3, [pc, #232] @ (800b11c ) 800b032: f8b3 301b ldrh.w r3, [r3, #27] 800b036: b29b uxth r3, r3 800b038: 4a39 ldr r2, [pc, #228] @ (800b120 ) 800b03a: fba2 2303 umull r2, r3, r2, r3 800b03e: 08db lsrs r3, r3, #3 800b040: b29b uxth r3, r3 800b042: 461a mov r2, r3 800b044: 4b35 ldr r3, [pc, #212] @ (800b11c ) 800b046: f8b3 3013 ldrh.w r3, [r3, #19] 800b04a: b29b uxth r3, r3 800b04c: fb02 f303 mul.w r3, r2, r3 800b050: 461a mov r2, r3 800b052: 4b34 ldr r3, [pc, #208] @ (800b124 ) 800b054: 695b ldr r3, [r3, #20] 800b056: 429a cmp r2, r3 800b058: d911 bls.n 800b07e CONN.RequestedCurrent = PSU0.power_limit * 10 / CONN.MeasuredVoltage; 800b05a: 4b32 ldr r3, [pc, #200] @ (800b124 ) 800b05c: 695a ldr r2, [r3, #20] 800b05e: 4613 mov r3, r2 800b060: 009b lsls r3, r3, #2 800b062: 4413 add r3, r2 800b064: 005b lsls r3, r3, #1 800b066: 461a mov r2, r3 800b068: 4b2c ldr r3, [pc, #176] @ (800b11c ) 800b06a: f8b3 3013 ldrh.w r3, [r3, #19] 800b06e: b29b uxth r3, r3 800b070: fbb2 f3f3 udiv r3, r2, r3 800b074: b29a uxth r2, r3 800b076: 4b29 ldr r3, [pc, #164] @ (800b11c ) 800b078: f8a3 2011 strh.w r2, [r3, #17] 800b07c: e006 b.n 800b08c }else{ CONN.RequestedCurrent = CONN.WantedCurrent; 800b07e: 4b27 ldr r3, [pc, #156] @ (800b11c ) 800b080: f8b3 301b ldrh.w r3, [r3, #27] 800b084: b29a uxth r2, r3 800b086: 4b25 ldr r3, [pc, #148] @ (800b11c ) 800b088: f8a3 2011 strh.w r2, [r3, #17] } if(CONN.RequestedCurrent > (PSU_MAX_CURRENT*10)){ 800b08c: 4b23 ldr r3, [pc, #140] @ (800b11c ) 800b08e: f8b3 3011 ldrh.w r3, [r3, #17] 800b092: b29b uxth r3, r3 800b094: f240 5232 movw r2, #1330 @ 0x532 800b098: 4293 cmp r3, r2 800b09a: d908 bls.n 800b0ae CONN.RequestedCurrent = PSU_MAX_CURRENT*10; 800b09c: 4b1f ldr r3, [pc, #124] @ (800b11c ) 800b09e: 2200 movs r2, #0 800b0a0: f042 0232 orr.w r2, r2, #50 @ 0x32 800b0a4: 745a strb r2, [r3, #17] 800b0a6: 2200 movs r2, #0 800b0a8: f042 0205 orr.w r2, r2, #5 800b0ac: 749a strb r2, [r3, #18] } CONN.RequestedPower = CONN.RequestedCurrent * CONN.RequestedVoltage / 10; 800b0ae: 4b1b ldr r3, [pc, #108] @ (800b11c ) 800b0b0: f8b3 3011 ldrh.w r3, [r3, #17] 800b0b4: b29b uxth r3, r3 800b0b6: 461a mov r2, r3 800b0b8: 4b18 ldr r3, [pc, #96] @ (800b11c ) 800b0ba: f8b3 300f ldrh.w r3, [r3, #15] 800b0be: b29b uxth r3, r3 800b0c0: fb02 f303 mul.w r3, r2, r3 800b0c4: 4a18 ldr r2, [pc, #96] @ (800b128 ) 800b0c6: fb82 1203 smull r1, r2, r2, r3 800b0ca: 1092 asrs r2, r2, #2 800b0cc: 17db asrs r3, r3, #31 800b0ce: 1ad3 subs r3, r2, r3 800b0d0: 461a mov r2, r3 800b0d2: 4b12 ldr r3, [pc, #72] @ (800b11c ) 800b0d4: f8c3 200b str.w r2, [r3, #11] if(PSU0.ready){ 800b0d8: 4b12 ldr r3, [pc, #72] @ (800b124 ) 800b0da: 7a5b ldrb r3, [r3, #9] 800b0dc: 2b00 cmp r3, #0 800b0de: d018 beq.n 800b112 PSU_SetVoltageCurrent(0, CONN.RequestedVoltage, CONN.RequestedCurrent); // Normal mode 800b0e0: 4b0e ldr r3, [pc, #56] @ (800b11c ) 800b0e2: f8b3 300f ldrh.w r3, [r3, #15] 800b0e6: b29b uxth r3, r3 800b0e8: 4a0c ldr r2, [pc, #48] @ (800b11c ) 800b0ea: f8b2 2011 ldrh.w r2, [r2, #17] 800b0ee: b292 uxth r2, r2 800b0f0: 4619 mov r1, r3 800b0f2: 2000 movs r0, #0 800b0f4: f7ff feca bl 800ae8c ED_Delay(CAN_DELAY); 800b0f8: 2014 movs r0, #20 800b0fa: f7ff fb3b bl 800a774 if(CONN.MeasuredVoltage>490) PSU0.hv_mode = 1; 800b0fe: 4b07 ldr r3, [pc, #28] @ (800b11c ) 800b100: f8b3 3013 ldrh.w r3, [r3, #19] 800b104: b29b uxth r3, r3 800b106: f5b3 7ff5 cmp.w r3, #490 @ 0x1ea 800b10a: d902 bls.n 800b112 800b10c: 4b05 ldr r3, [pc, #20] @ (800b124 ) 800b10e: 2201 movs r2, #1 800b110: 761a strb r2, [r3, #24] } // PSU_SetHVMode(0, PSU0.hv_mode); // auto set, no need // ED_Delay(CAN_DELAY); } 800b112: bf00 nop 800b114: 3708 adds r7, #8 800b116: 46bd mov sp, r7 800b118: bd80 pop {r7, pc} 800b11a: bf00 nop 800b11c: 200001d4 .word 0x200001d4 800b120: cccccccd .word 0xcccccccd 800b124: 20000724 .word 0x20000724 800b128: 66666667 .word 0x66666667 0800b12c : void PSU_Task(void){ 800b12c: b598 push {r3, r4, r7, lr} 800b12e: af00 add r7, sp, #0 static uint32_t psu_on_tick = 0; static uint32_t dc_on_tick = 0; static uint32_t cont_ok_tick = 0; // Обновляем ONLINE/READY по таймауту if((HAL_GetTick() - can_lastpacket) > PSU_ONLINE_TIMEOUT){ 800b130: f002 fc14 bl 800d95c 800b134: 4602 mov r2, r0 800b136: 4bb4 ldr r3, [pc, #720] @ (800b408 ) 800b138: 681b ldr r3, [r3, #0] 800b13a: 1ad3 subs r3, r2, r3 800b13c: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b140: d920 bls.n 800b184 PSU0.online = 0; 800b142: 4bb2 ldr r3, [pc, #712] @ (800b40c ) 800b144: 2200 movs r2, #0 800b146: 721a strb r2, [r3, #8] PSU0.PSU_enabled = 0; 800b148: 4bb0 ldr r3, [pc, #704] @ (800b40c ) 800b14a: 2200 movs r2, #0 800b14c: 729a strb r2, [r3, #10] PSU_04.moduleTemperature = 0; 800b14e: 4bb0 ldr r3, [pc, #704] @ (800b410 ) 800b150: 2200 movs r2, #0 800b152: 711a strb r2, [r3, #4] PSU_04.modularForm0 = 0; 800b154: 4bae ldr r3, [pc, #696] @ (800b410 ) 800b156: 2200 movs r2, #0 800b158: 721a strb r2, [r3, #8] PSU_04.modularForm1 = 0; 800b15a: 4bad ldr r3, [pc, #692] @ (800b410 ) 800b15c: 2200 movs r2, #0 800b15e: 71da strb r2, [r3, #7] PSU_04.modularForm2 = 0; 800b160: 4bab ldr r3, [pc, #684] @ (800b410 ) 800b162: 2200 movs r2, #0 800b164: 719a strb r2, [r3, #6] PSU_06.VAB = 0; 800b166: 4bab ldr r3, [pc, #684] @ (800b414 ) 800b168: 2200 movs r2, #0 800b16a: 609a str r2, [r3, #8] PSU_06.VBC = 0; 800b16c: 4ba9 ldr r3, [pc, #676] @ (800b414 ) 800b16e: 2200 movs r2, #0 800b170: 60da str r2, [r3, #12] PSU_06.VCA = 0; 800b172: 4ba8 ldr r3, [pc, #672] @ (800b414 ) 800b174: 2200 movs r2, #0 800b176: 611a str r2, [r3, #16] PSU_09.moduleNCurrent = 0; 800b178: 4ba7 ldr r3, [pc, #668] @ (800b418 ) 800b17a: 2200 movs r2, #0 800b17c: 60da str r2, [r3, #12] PSU_09.moduleNVoltage = 0; 800b17e: 4ba6 ldr r3, [pc, #664] @ (800b418 ) 800b180: 2200 movs r2, #0 800b182: 609a str r2, [r3, #8] } if(!PSU0.online || !PSU0.enableAC){ 800b184: 4ba1 ldr r3, [pc, #644] @ (800b40c ) 800b186: 7a1b ldrb r3, [r3, #8] 800b188: 2b00 cmp r3, #0 800b18a: d003 beq.n 800b194 800b18c: 4b9f ldr r3, [pc, #636] @ (800b40c ) 800b18e: 781b ldrb r3, [r3, #0] 800b190: 2b00 cmp r3, #0 800b192: d10c bne.n 800b1ae CONN.MeasuredVoltage = 0; 800b194: 4ba1 ldr r3, [pc, #644] @ (800b41c ) 800b196: 2200 movs r2, #0 800b198: 74da strb r2, [r3, #19] 800b19a: 2200 movs r2, #0 800b19c: 751a strb r2, [r3, #20] CONN.MeasuredCurrent = 0; 800b19e: 4b9f ldr r3, [pc, #636] @ (800b41c ) 800b1a0: 2200 movs r2, #0 800b1a2: 755a strb r2, [r3, #21] 800b1a4: 2200 movs r2, #0 800b1a6: 759a strb r2, [r3, #22] CONN.outputEnabled = 0; 800b1a8: 4b9c ldr r3, [pc, #624] @ (800b41c ) 800b1aa: 2200 movs r2, #0 800b1ac: 761a strb r2, [r3, #24] } // Управление AC-контактором с задержкой отключения 1 минута if(CONN.EvConnected){ 800b1ae: 4b9b ldr r3, [pc, #620] @ (800b41c ) 800b1b0: 7f9b ldrb r3, [r3, #30] 800b1b2: 2b00 cmp r3, #0 800b1b4: d00c beq.n 800b1d0 RELAY_Write(RELAY_AC, 1); 800b1b6: 2101 movs r1, #1 800b1b8: 2004 movs r0, #4 800b1ba: f7fe f979 bl 80094b0 psu_on_tick = HAL_GetTick(); 800b1be: f002 fbcd bl 800d95c 800b1c2: 4603 mov r3, r0 800b1c4: 4a96 ldr r2, [pc, #600] @ (800b420 ) 800b1c6: 6013 str r3, [r2, #0] PSU0.enableAC = 1; 800b1c8: 4b90 ldr r3, [pc, #576] @ (800b40c ) 800b1ca: 2201 movs r2, #1 800b1cc: 701a strb r2, [r3, #0] 800b1ce: e010 b.n 800b1f2 }else{ if((HAL_GetTick() - psu_on_tick) > 1 * 60000){ 800b1d0: f002 fbc4 bl 800d95c 800b1d4: 4602 mov r2, r0 800b1d6: 4b92 ldr r3, [pc, #584] @ (800b420 ) 800b1d8: 681b ldr r3, [r3, #0] 800b1da: 1ad3 subs r3, r2, r3 800b1dc: f64e 2260 movw r2, #60000 @ 0xea60 800b1e0: 4293 cmp r3, r2 800b1e2: d906 bls.n 800b1f2 RELAY_Write(RELAY_AC, 0); 800b1e4: 2100 movs r1, #0 800b1e6: 2004 movs r0, #4 800b1e8: f7fe f962 bl 80094b0 PSU0.enableAC = 0; 800b1ec: 4b87 ldr r3, [pc, #540] @ (800b40c ) 800b1ee: 2200 movs r2, #0 800b1f0: 701a strb r2, [r3, #0] } } // Текущее состояние DC-контактора по обратной связи PSU0.CONT_enabled = IN_ReadInput(IN_CONT_FB_DC); 800b1f2: 2005 movs r0, #5 800b1f4: f7fe f9dc bl 80095b0 800b1f8: 4603 mov r3, r0 800b1fa: 461a mov r2, r3 800b1fc: 4b83 ldr r3, [pc, #524] @ (800b40c ) 800b1fe: 72da strb r2, [r3, #11] // Обновляем ready с учётом ошибок if(PSU0.online && !PSU0.cont_fault && PSU0.enableAC){ 800b200: 4b82 ldr r3, [pc, #520] @ (800b40c ) 800b202: 7a1b ldrb r3, [r3, #8] 800b204: 2b00 cmp r3, #0 800b206: d007 beq.n 800b218 800b208: 4b80 ldr r3, [pc, #512] @ (800b40c ) 800b20a: 7b1b ldrb r3, [r3, #12] 800b20c: 2b00 cmp r3, #0 800b20e: d103 bne.n 800b218 800b210: 4b7e ldr r3, [pc, #504] @ (800b40c ) 800b212: 781b ldrb r3, [r3, #0] 800b214: 2b00 cmp r3, #0 800b216: d102 bne.n 800b21e // PSU0.ready = 1; }else{ PSU0.ready = 0; 800b218: 4b7c ldr r3, [pc, #496] @ (800b40c ) 800b21a: 2200 movs r2, #0 800b21c: 725a strb r2, [r3, #9] } switch(PSU0.state){ 800b21e: 4b7b ldr r3, [pc, #492] @ (800b40c ) 800b220: 79db ldrb r3, [r3, #7] 800b222: 2b09 cmp r3, #9 800b224: f200 8155 bhi.w 800b4d2 800b228: a201 add r2, pc, #4 @ (adr r2, 800b230 ) 800b22a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b22e: bf00 nop 800b230: 0800b259 .word 0x0800b259 800b234: 0800b28d .word 0x0800b28d 800b238: 0800b2a9 .word 0x0800b2a9 800b23c: 0800b2e1 .word 0x0800b2e1 800b240: 0800b32f .word 0x0800b32f 800b244: 0800b371 .word 0x0800b371 800b248: 0800b3db .word 0x0800b3db 800b24c: 0800b485 .word 0x0800b485 800b250: 0800b435 .word 0x0800b435 800b254: 0800b4bf .word 0x0800b4bf case PSU_UNREADY: PSU0.enableOutput = 0; 800b258: 4b6c ldr r3, [pc, #432] @ (800b40c ) 800b25a: 2200 movs r2, #0 800b25c: 705a strb r2, [r3, #1] RELAY_Write(RELAY_DC, 0); 800b25e: 2100 movs r1, #0 800b260: 2003 movs r0, #3 800b262: f7fe f925 bl 80094b0 if(PSU0.online && PSU0.enableAC && !PSU0.cont_fault){ 800b266: 4b69 ldr r3, [pc, #420] @ (800b40c ) 800b268: 7a1b ldrb r3, [r3, #8] 800b26a: 2b00 cmp r3, #0 800b26c: f000 8135 beq.w 800b4da 800b270: 4b66 ldr r3, [pc, #408] @ (800b40c ) 800b272: 781b ldrb r3, [r3, #0] 800b274: 2b00 cmp r3, #0 800b276: f000 8130 beq.w 800b4da 800b27a: 4b64 ldr r3, [pc, #400] @ (800b40c ) 800b27c: 7b1b ldrb r3, [r3, #12] 800b27e: 2b00 cmp r3, #0 800b280: f040 812b bne.w 800b4da PSU_SwitchState(PSU_INITIALIZING); 800b284: 2001 movs r0, #1 800b286: f7ff fc29 bl 800aadc } break; 800b28a: e126 b.n 800b4da case PSU_INITIALIZING: if(PSU_StateTime() > 4000){ // Wait 4s for PSU to initialize 800b28c: f7ff fc3a bl 800ab04 800b290: 4603 mov r3, r0 800b292: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b296: f240 8122 bls.w 800b4de PSU0.ready = 1; 800b29a: 4b5c ldr r3, [pc, #368] @ (800b40c ) 800b29c: 2201 movs r2, #1 800b29e: 725a strb r2, [r3, #9] PSU_SwitchState(PSU_READY); 800b2a0: 2002 movs r0, #2 800b2a2: f7ff fc1b bl 800aadc } break; 800b2a6: e11a b.n 800b4de case PSU_READY: // модуль готов, но выключен PSU0.hv_mode = 0; 800b2a8: 4b58 ldr r3, [pc, #352] @ (800b40c ) 800b2aa: 2200 movs r2, #0 800b2ac: 761a strb r2, [r3, #24] RELAY_Write(RELAY_DC, 0); 800b2ae: 2100 movs r1, #0 800b2b0: 2003 movs r0, #3 800b2b2: f7fe f8fd bl 80094b0 if(!PSU0.ready){ 800b2b6: 4b55 ldr r3, [pc, #340] @ (800b40c ) 800b2b8: 7a5b ldrb r3, [r3, #9] 800b2ba: 2b00 cmp r3, #0 800b2bc: d103 bne.n 800b2c6 PSU_SwitchState(PSU_UNREADY); 800b2be: 2000 movs r0, #0 800b2c0: f7ff fc0c bl 800aadc break; 800b2c4: e11c b.n 800b500 } if(CONN.EnableOutput){ 800b2c6: 4b55 ldr r3, [pc, #340] @ (800b41c ) 800b2c8: 7ddb ldrb r3, [r3, #23] 800b2ca: 2b00 cmp r3, #0 800b2cc: f000 8109 beq.w 800b4e2 PSU_Enable(0, 1); 800b2d0: 2101 movs r1, #1 800b2d2: 2000 movs r0, #0 800b2d4: f7ff fdaa bl 800ae2c PSU_SwitchState(PSU_WAIT_ACK_ON); 800b2d8: 2003 movs r0, #3 800b2da: f7ff fbff bl 800aadc } break; 800b2de: e100 b.n 800b4e2 case PSU_WAIT_ACK_ON: if(PSU0.PSU_enabled && PSU0.ready){ 800b2e0: 4b4a ldr r3, [pc, #296] @ (800b40c ) 800b2e2: 7a9b ldrb r3, [r3, #10] 800b2e4: 2b00 cmp r3, #0 800b2e6: d00c beq.n 800b302 800b2e8: 4b48 ldr r3, [pc, #288] @ (800b40c ) 800b2ea: 7a5b ldrb r3, [r3, #9] 800b2ec: 2b00 cmp r3, #0 800b2ee: d008 beq.n 800b302 dc_on_tick = HAL_GetTick(); 800b2f0: f002 fb34 bl 800d95c 800b2f4: 4603 mov r3, r0 800b2f6: 4a4b ldr r2, [pc, #300] @ (800b424 ) 800b2f8: 6013 str r3, [r2, #0] PSU_SwitchState(PSU_CONT_WAIT_ACK_ON); 800b2fa: 2004 movs r0, #4 800b2fc: f7ff fbee bl 800aadc PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU on timeout\n"); } break; 800b300: e0f1 b.n 800b4e6 }else if(PSU_StateTime() > 10000){ 800b302: f7ff fbff bl 800ab04 800b306: 4603 mov r3, r0 800b308: f242 7210 movw r2, #10000 @ 0x2710 800b30c: 4293 cmp r3, r2 800b30e: f240 80ea bls.w 800b4e6 PSU0.psu_fault = 1; 800b312: 4b3e ldr r3, [pc, #248] @ (800b40c ) 800b314: 2201 movs r2, #1 800b316: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b318: 4b40 ldr r3, [pc, #256] @ (800b41c ) 800b31a: 220a movs r2, #10 800b31c: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b31e: 2000 movs r0, #0 800b320: f7ff fbdc bl 800aadc log_printf(LOG_ERR, "PSU on timeout\n"); 800b324: 4940 ldr r1, [pc, #256] @ (800b428 ) 800b326: 2004 movs r0, #4 800b328: f7ff f8a8 bl 800a47c break; 800b32c: e0db b.n 800b4e6 case PSU_CONT_WAIT_ACK_ON: // замыкаем DC-контактор и ждём подтверждение RELAY_Write(RELAY_DC, 1); 800b32e: 2101 movs r1, #1 800b330: 2003 movs r0, #3 800b332: f7fe f8bd bl 80094b0 if(PSU0.CONT_enabled){ 800b336: 4b35 ldr r3, [pc, #212] @ (800b40c ) 800b338: 7adb ldrb r3, [r3, #11] 800b33a: 2b00 cmp r3, #0 800b33c: d003 beq.n 800b346 PSU_SwitchState(PSU_CONNECTED); 800b33e: 2005 movs r0, #5 800b340: f7ff fbcc bl 800aadc PSU0.cont_fault = 1; CONN.chargingError = CONN_ERR_CONTACTOR; PSU_SwitchState(PSU_CURRENT_DROP); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b344: e0d1 b.n 800b4ea }else if(PSU_StateTime() > 1000){ 800b346: f7ff fbdd bl 800ab04 800b34a: 4603 mov r3, r0 800b34c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b350: f240 80cb bls.w 800b4ea PSU0.cont_fault = 1; 800b354: 4b2d ldr r3, [pc, #180] @ (800b40c ) 800b356: 2201 movs r2, #1 800b358: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b35a: 4b30 ldr r3, [pc, #192] @ (800b41c ) 800b35c: 2207 movs r2, #7 800b35e: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_CURRENT_DROP); 800b360: 2006 movs r0, #6 800b362: f7ff fbbb bl 800aadc log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b366: 4931 ldr r1, [pc, #196] @ (800b42c ) 800b368: 2004 movs r0, #4 800b36a: f7ff f887 bl 800a47c break; 800b36e: e0bc b.n 800b4ea case PSU_CONNECTED: // Основное рабочее состояние if(!CONN.EnableOutput || !PSU0.ready){ 800b370: 4b2a ldr r3, [pc, #168] @ (800b41c ) 800b372: 7ddb ldrb r3, [r3, #23] 800b374: 2b00 cmp r3, #0 800b376: d003 beq.n 800b380 800b378: 4b24 ldr r3, [pc, #144] @ (800b40c ) 800b37a: 7a5b ldrb r3, [r3, #9] 800b37c: 2b00 cmp r3, #0 800b37e: d103 bne.n 800b388 PSU_SwitchState(PSU_CURRENT_DROP); 800b380: 2006 movs r0, #6 800b382: f7ff fbab bl 800aadc break; 800b386: e0bb b.n 800b500 } // контроль контактора: 1 c таймаут if (IN_ReadInput(IN_CONT_FB_DC) != RELAY_Read(RELAY_DC)){ 800b388: 2005 movs r0, #5 800b38a: f7fe f911 bl 80095b0 800b38e: 4603 mov r3, r0 800b390: 461c mov r4, r3 800b392: 2003 movs r0, #3 800b394: f7fe f8fc bl 8009590 800b398: 4603 mov r3, r0 800b39a: 429c cmp r4, r3 800b39c: d017 beq.n 800b3ce if((HAL_GetTick() - cont_ok_tick) > 1000){ 800b39e: f002 fadd bl 800d95c 800b3a2: 4602 mov r2, r0 800b3a4: 4b22 ldr r3, [pc, #136] @ (800b430 ) 800b3a6: 681b ldr r3, [r3, #0] 800b3a8: 1ad3 subs r3, r2, r3 800b3aa: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b3ae: f240 809e bls.w 800b4ee CONN.chargingError = CONN_ERR_CONTACTOR; 800b3b2: 4b1a ldr r3, [pc, #104] @ (800b41c ) 800b3b4: 2207 movs r2, #7 800b3b6: 775a strb r2, [r3, #29] PSU0.cont_fault = 1; 800b3b8: 4b14 ldr r3, [pc, #80] @ (800b40c ) 800b3ba: 2201 movs r2, #1 800b3bc: 731a strb r2, [r3, #12] PSU_SwitchState(PSU_CURRENT_DROP); 800b3be: 2006 movs r0, #6 800b3c0: f7ff fb8c bl 800aadc log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b3c4: 4919 ldr r1, [pc, #100] @ (800b42c ) 800b3c6: 2004 movs r0, #4 800b3c8: f7ff f858 bl 800a47c } }else{ cont_ok_tick = HAL_GetTick(); } break; 800b3cc: e08f b.n 800b4ee cont_ok_tick = HAL_GetTick(); 800b3ce: f002 fac5 bl 800d95c 800b3d2: 4603 mov r3, r0 800b3d4: 4a16 ldr r2, [pc, #88] @ (800b430 ) 800b3d6: 6013 str r3, [r2, #0] break; 800b3d8: e089 b.n 800b4ee case PSU_CURRENT_DROP: // снижаем ток до нуля перед отключением DC CONN.RequestedCurrent = 0; 800b3da: 4b10 ldr r3, [pc, #64] @ (800b41c ) 800b3dc: 2200 movs r2, #0 800b3de: 745a strb r2, [r3, #17] 800b3e0: 2200 movs r2, #0 800b3e2: 749a strb r2, [r3, #18] // если ток действительно упал или вышло время, отключаем DC if((CONN.MeasuredCurrent < 30) || (PSU_StateTime() > 5000)){ 800b3e4: 4b0d ldr r3, [pc, #52] @ (800b41c ) 800b3e6: f8b3 3015 ldrh.w r3, [r3, #21] 800b3ea: b29b uxth r3, r3 800b3ec: 2b1d cmp r3, #29 800b3ee: d906 bls.n 800b3fe 800b3f0: f7ff fb88 bl 800ab04 800b3f4: 4603 mov r3, r0 800b3f6: f241 3288 movw r2, #5000 @ 0x1388 800b3fa: 4293 cmp r3, r2 800b3fc: d979 bls.n 800b4f2 PSU_SwitchState(PSU_CONT_WAIT_ACK_OFF); 800b3fe: 2008 movs r0, #8 800b400: f7ff fb6c bl 800aadc } break; 800b404: e075 b.n 800b4f2 800b406: bf00 nop 800b408: 20000748 .word 0x20000748 800b40c: 20000724 .word 0x20000724 800b410: 200006ec .word 0x200006ec 800b414: 200006f8 .word 0x200006f8 800b418: 20000714 .word 0x20000714 800b41c: 200001d4 .word 0x200001d4 800b420: 20000770 .word 0x20000770 800b424: 20000774 .word 0x20000774 800b428: 0801420c .word 0x0801420c 800b42c: 0801421c .word 0x0801421c 800b430: 20000778 .word 0x20000778 case PSU_CONT_WAIT_ACK_OFF: RELAY_Write(RELAY_DC, 0); 800b434: 2100 movs r1, #0 800b436: 2003 movs r0, #3 800b438: f7fe f83a bl 80094b0 if(!PSU0.CONT_enabled){ 800b43c: 4b31 ldr r3, [pc, #196] @ (800b504 ) 800b43e: 7adb ldrb r3, [r3, #11] 800b440: 2b00 cmp r3, #0 800b442: d107 bne.n 800b454 PSU_Enable(0, 0); 800b444: 2100 movs r1, #0 800b446: 2000 movs r0, #0 800b448: f7ff fcf0 bl 800ae2c PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b44c: 2007 movs r0, #7 800b44e: f7ff fb45 bl 800aadc CONN.chargingError = CONN_ERR_CONTACTOR; PSU_Enable(0, 0); PSU_SwitchState(PSU_WAIT_ACK_OFF); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b452: e050 b.n 800b4f6 }else if(PSU_StateTime() > 1000){ 800b454: f7ff fb56 bl 800ab04 800b458: 4603 mov r3, r0 800b45a: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b45e: d94a bls.n 800b4f6 PSU0.cont_fault = 1; 800b460: 4b28 ldr r3, [pc, #160] @ (800b504 ) 800b462: 2201 movs r2, #1 800b464: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b466: 4b28 ldr r3, [pc, #160] @ (800b508 ) 800b468: 2207 movs r2, #7 800b46a: 775a strb r2, [r3, #29] PSU_Enable(0, 0); 800b46c: 2100 movs r1, #0 800b46e: 2000 movs r0, #0 800b470: f7ff fcdc bl 800ae2c PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b474: 2007 movs r0, #7 800b476: f7ff fb31 bl 800aadc log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b47a: 4924 ldr r1, [pc, #144] @ (800b50c ) 800b47c: 2004 movs r0, #4 800b47e: f7fe fffd bl 800a47c break; 800b482: e038 b.n 800b4f6 case PSU_WAIT_ACK_OFF: if(!PSU0.PSU_enabled){ 800b484: 4b1f ldr r3, [pc, #124] @ (800b504 ) 800b486: 7a9b ldrb r3, [r3, #10] 800b488: 2b00 cmp r3, #0 800b48a: d103 bne.n 800b494 PSU_SwitchState(PSU_OFF_PAUSE); 800b48c: 2009 movs r0, #9 800b48e: f7ff fb25 bl 800aadc PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU off timeout\n"); } break; 800b492: e032 b.n 800b4fa }else if(PSU_StateTime() > 10000){ 800b494: f7ff fb36 bl 800ab04 800b498: 4603 mov r3, r0 800b49a: f242 7210 movw r2, #10000 @ 0x2710 800b49e: 4293 cmp r3, r2 800b4a0: d92b bls.n 800b4fa PSU0.psu_fault = 1; 800b4a2: 4b18 ldr r3, [pc, #96] @ (800b504 ) 800b4a4: 2201 movs r2, #1 800b4a6: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b4a8: 4b17 ldr r3, [pc, #92] @ (800b508 ) 800b4aa: 220a movs r2, #10 800b4ac: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b4ae: 2000 movs r0, #0 800b4b0: f7ff fb14 bl 800aadc log_printf(LOG_ERR, "PSU off timeout\n"); 800b4b4: 4916 ldr r1, [pc, #88] @ (800b510 ) 800b4b6: 2004 movs r0, #4 800b4b8: f7fe ffe0 bl 800a47c break; 800b4bc: e01d b.n 800b4fa case PSU_OFF_PAUSE: if(PSU_StateTime() > 4000){ 800b4be: f7ff fb21 bl 800ab04 800b4c2: 4603 mov r3, r0 800b4c4: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b4c8: d919 bls.n 800b4fe PSU_SwitchState(PSU_READY); 800b4ca: 2002 movs r0, #2 800b4cc: f7ff fb06 bl 800aadc } break; 800b4d0: e015 b.n 800b4fe default: PSU_SwitchState(PSU_UNREADY); 800b4d2: 2000 movs r0, #0 800b4d4: f7ff fb02 bl 800aadc break; 800b4d8: e012 b.n 800b500 break; 800b4da: bf00 nop 800b4dc: e010 b.n 800b500 break; 800b4de: bf00 nop 800b4e0: e00e b.n 800b500 break; 800b4e2: bf00 nop 800b4e4: e00c b.n 800b500 break; 800b4e6: bf00 nop 800b4e8: e00a b.n 800b500 break; 800b4ea: bf00 nop 800b4ec: e008 b.n 800b500 break; 800b4ee: bf00 nop 800b4f0: e006 b.n 800b500 break; 800b4f2: bf00 nop 800b4f4: e004 b.n 800b500 break; 800b4f6: bf00 nop 800b4f8: e002 b.n 800b500 break; 800b4fa: bf00 nop 800b4fc: e000 b.n 800b500 break; 800b4fe: bf00 nop } } 800b500: bf00 nop 800b502: bd98 pop {r3, r4, r7, pc} 800b504: 20000724 .word 0x20000724 800b508: 200001d4 .word 0x200001d4 800b50c: 0801421c .word 0x0801421c 800b510: 0801423c .word 0x0801423c 0800b514 : .Th = 10, .Tf = 50, .Tl = 0, }; void LED_Write(){ 800b514: b580 push {r7, lr} 800b516: af00 add r7, sp, #0 if(CONN.chargingError != CONN_NO_ERROR){ 800b518: 4b34 ldr r3, [pc, #208] @ (800b5ec ) 800b51a: 7f5b ldrb r3, [r3, #29] 800b51c: 2b00 cmp r3, #0 800b51e: d003 beq.n 800b528 LED_SetColor(&color_error); 800b520: 4833 ldr r0, [pc, #204] @ (800b5f0 ) 800b522: f000 f91f bl 800b764 return; 800b526: e05f b.n 800b5e8 } switch(CONN.connState){ 800b528: 4b30 ldr r3, [pc, #192] @ (800b5ec ) 800b52a: 785b ldrb r3, [r3, #1] 800b52c: 2b0d cmp r3, #13 800b52e: d857 bhi.n 800b5e0 800b530: a201 add r2, pc, #4 @ (adr r2, 800b538 ) 800b532: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b536: bf00 nop 800b538: 0800b571 .word 0x0800b571 800b53c: 0800b579 .word 0x0800b579 800b540: 0800b581 .word 0x0800b581 800b544: 0800b589 .word 0x0800b589 800b548: 0800b591 .word 0x0800b591 800b54c: 0800b599 .word 0x0800b599 800b550: 0800b5a1 .word 0x0800b5a1 800b554: 0800b5a9 .word 0x0800b5a9 800b558: 0800b5b1 .word 0x0800b5b1 800b55c: 0800b5b9 .word 0x0800b5b9 800b560: 0800b5c1 .word 0x0800b5c1 800b564: 0800b5c9 .word 0x0800b5c9 800b568: 0800b5d1 .word 0x0800b5d1 800b56c: 0800b5d9 .word 0x0800b5d9 case Unknown: LED_SetColor(&color_unknown); 800b570: 4820 ldr r0, [pc, #128] @ (800b5f4 ) 800b572: f000 f8f7 bl 800b764 break; 800b576: e037 b.n 800b5e8 case Unplugged: LED_SetColor(&color_unplugged); 800b578: 481f ldr r0, [pc, #124] @ (800b5f8 ) 800b57a: f000 f8f3 bl 800b764 break; 800b57e: e033 b.n 800b5e8 case Disabled: LED_SetColor(&color_error); 800b580: 481b ldr r0, [pc, #108] @ (800b5f0 ) 800b582: f000 f8ef bl 800b764 break; 800b586: e02f b.n 800b5e8 case Preparing: LED_SetColor(&color_preparing); 800b588: 481c ldr r0, [pc, #112] @ (800b5fc ) 800b58a: f000 f8eb bl 800b764 break; 800b58e: e02b b.n 800b5e8 case AuthRequired: LED_SetColor(&color_preparing); 800b590: 481a ldr r0, [pc, #104] @ (800b5fc ) 800b592: f000 f8e7 bl 800b764 break; 800b596: e027 b.n 800b5e8 case WaitingForEnergy: LED_SetColor(&color_charging); 800b598: 4819 ldr r0, [pc, #100] @ (800b600 ) 800b59a: f000 f8e3 bl 800b764 break; 800b59e: e023 b.n 800b5e8 case ChargingPausedEV: LED_SetColor(&color_charging); 800b5a0: 4817 ldr r0, [pc, #92] @ (800b600 ) 800b5a2: f000 f8df bl 800b764 break; 800b5a6: e01f b.n 800b5e8 case ChargingPausedEVSE: LED_SetColor(&color_charging); 800b5a8: 4815 ldr r0, [pc, #84] @ (800b600 ) 800b5aa: f000 f8db bl 800b764 break; 800b5ae: e01b b.n 800b5e8 case Charging: LED_SetColor(&color_charging); 800b5b0: 4813 ldr r0, [pc, #76] @ (800b600 ) 800b5b2: f000 f8d7 bl 800b764 break; 800b5b6: e017 b.n 800b5e8 case AuthTimeout: LED_SetColor(&color_finished); 800b5b8: 4812 ldr r0, [pc, #72] @ (800b604 ) 800b5ba: f000 f8d3 bl 800b764 break; 800b5be: e013 b.n 800b5e8 case Finished: LED_SetColor(&color_finished); 800b5c0: 4810 ldr r0, [pc, #64] @ (800b604 ) 800b5c2: f000 f8cf bl 800b764 break; 800b5c6: e00f b.n 800b5e8 case FinishedEVSE: LED_SetColor(&color_finished); 800b5c8: 480e ldr r0, [pc, #56] @ (800b604 ) 800b5ca: f000 f8cb bl 800b764 break; 800b5ce: e00b b.n 800b5e8 case FinishedEV: LED_SetColor(&color_finished); 800b5d0: 480c ldr r0, [pc, #48] @ (800b604 ) 800b5d2: f000 f8c7 bl 800b764 break; 800b5d6: e007 b.n 800b5e8 case Replugging: LED_SetColor(&color_preparing); 800b5d8: 4808 ldr r0, [pc, #32] @ (800b5fc ) 800b5da: f000 f8c3 bl 800b764 break; 800b5de: e003 b.n 800b5e8 default: LED_SetColor(&color_unknown); 800b5e0: 4804 ldr r0, [pc, #16] @ (800b5f4 ) 800b5e2: f000 f8bf bl 800b764 break; 800b5e6: bf00 nop } } 800b5e8: bd80 pop {r7, pc} 800b5ea: bf00 nop 800b5ec: 200001d4 .word 0x200001d4 800b5f0: 20000044 .word 0x20000044 800b5f4: 20000008 .word 0x20000008 800b5f8: 20000014 .word 0x20000014 800b5fc: 20000020 .word 0x20000020 800b600: 2000002c .word 0x2000002c 800b604: 20000038 .word 0x20000038 0800b608 : void interpolateColors(RGB_t* color1, RGB_t* color2, uint16_t a, uint16_t b, RGB_t *result) { 800b608: b480 push {r7} 800b60a: b087 sub sp, #28 800b60c: af00 add r7, sp, #0 800b60e: 60f8 str r0, [r7, #12] 800b610: 60b9 str r1, [r7, #8] 800b612: 4611 mov r1, r2 800b614: 461a mov r2, r3 800b616: 460b mov r3, r1 800b618: 80fb strh r3, [r7, #6] 800b61a: 4613 mov r3, r2 800b61c: 80bb strh r3, [r7, #4] // Проверяем, чтобы a не выходила за пределы диапазона if (a > b) a = b; 800b61e: 88fa ldrh r2, [r7, #6] 800b620: 88bb ldrh r3, [r7, #4] 800b622: 429a cmp r2, r3 800b624: d901 bls.n 800b62a 800b626: 88bb ldrh r3, [r7, #4] 800b628: 80fb strh r3, [r7, #6] if(b==0) b = 1; 800b62a: 88bb ldrh r3, [r7, #4] 800b62c: 2b00 cmp r3, #0 800b62e: d101 bne.n 800b634 800b630: 2301 movs r3, #1 800b632: 80bb strh r3, [r7, #4] // Вычисляем коэффициент смешивания в виде целого числа uint16_t t = (a * 255) / b; // t будет от 0 до 255 800b634: 88fa ldrh r2, [r7, #6] 800b636: 4613 mov r3, r2 800b638: 021b lsls r3, r3, #8 800b63a: 1a9a subs r2, r3, r2 800b63c: 88bb ldrh r3, [r7, #4] 800b63e: fb92 f3f3 sdiv r3, r2, r3 800b642: 82fb strh r3, [r7, #22] // Линейная интерполяция с использованием целых чисел result->R = (color1->R * (255 - t) + color2->R * t) / 255; 800b644: 68fb ldr r3, [r7, #12] 800b646: 781b ldrb r3, [r3, #0] 800b648: 461a mov r2, r3 800b64a: 8afb ldrh r3, [r7, #22] 800b64c: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b650: fb03 f202 mul.w r2, r3, r2 800b654: 68bb ldr r3, [r7, #8] 800b656: 781b ldrb r3, [r3, #0] 800b658: 4619 mov r1, r3 800b65a: 8afb ldrh r3, [r7, #22] 800b65c: fb01 f303 mul.w r3, r1, r3 800b660: 4413 add r3, r2 800b662: 4a20 ldr r2, [pc, #128] @ (800b6e4 ) 800b664: fb82 1203 smull r1, r2, r2, r3 800b668: 441a add r2, r3 800b66a: 11d2 asrs r2, r2, #7 800b66c: 17db asrs r3, r3, #31 800b66e: 1ad3 subs r3, r2, r3 800b670: b2da uxtb r2, r3 800b672: 6a3b ldr r3, [r7, #32] 800b674: 701a strb r2, [r3, #0] result->G = (color1->G * (255 - t) + color2->G * t) / 255; 800b676: 68fb ldr r3, [r7, #12] 800b678: 785b ldrb r3, [r3, #1] 800b67a: 461a mov r2, r3 800b67c: 8afb ldrh r3, [r7, #22] 800b67e: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b682: fb03 f202 mul.w r2, r3, r2 800b686: 68bb ldr r3, [r7, #8] 800b688: 785b ldrb r3, [r3, #1] 800b68a: 4619 mov r1, r3 800b68c: 8afb ldrh r3, [r7, #22] 800b68e: fb01 f303 mul.w r3, r1, r3 800b692: 4413 add r3, r2 800b694: 4a13 ldr r2, [pc, #76] @ (800b6e4 ) 800b696: fb82 1203 smull r1, r2, r2, r3 800b69a: 441a add r2, r3 800b69c: 11d2 asrs r2, r2, #7 800b69e: 17db asrs r3, r3, #31 800b6a0: 1ad3 subs r3, r2, r3 800b6a2: b2da uxtb r2, r3 800b6a4: 6a3b ldr r3, [r7, #32] 800b6a6: 705a strb r2, [r3, #1] result->B = (color1->B * (255 - t) + color2->B * t) / 255; 800b6a8: 68fb ldr r3, [r7, #12] 800b6aa: 789b ldrb r3, [r3, #2] 800b6ac: 461a mov r2, r3 800b6ae: 8afb ldrh r3, [r7, #22] 800b6b0: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b6b4: fb03 f202 mul.w r2, r3, r2 800b6b8: 68bb ldr r3, [r7, #8] 800b6ba: 789b ldrb r3, [r3, #2] 800b6bc: 4619 mov r1, r3 800b6be: 8afb ldrh r3, [r7, #22] 800b6c0: fb01 f303 mul.w r3, r1, r3 800b6c4: 4413 add r3, r2 800b6c6: 4a07 ldr r2, [pc, #28] @ (800b6e4 ) 800b6c8: fb82 1203 smull r1, r2, r2, r3 800b6cc: 441a add r2, r3 800b6ce: 11d2 asrs r2, r2, #7 800b6d0: 17db asrs r3, r3, #31 800b6d2: 1ad3 subs r3, r2, r3 800b6d4: b2da uxtb r2, r3 800b6d6: 6a3b ldr r3, [r7, #32] 800b6d8: 709a strb r2, [r3, #2] } 800b6da: bf00 nop 800b6dc: 371c adds r7, #28 800b6de: 46bd mov sp, r7 800b6e0: bc80 pop {r7} 800b6e2: 4770 bx lr 800b6e4: 80808081 .word 0x80808081 0800b6e8 : void RGB_SetColor(RGB_t *color){ 800b6e8: b480 push {r7} 800b6ea: b083 sub sp, #12 800b6ec: af00 add r7, sp, #0 800b6ee: 6078 str r0, [r7, #4] htim4.Instance->CCR2 = color->R * 100 / 255; 800b6f0: 687b ldr r3, [r7, #4] 800b6f2: 781b ldrb r3, [r3, #0] 800b6f4: 461a mov r2, r3 800b6f6: 2364 movs r3, #100 @ 0x64 800b6f8: fb02 f303 mul.w r3, r2, r3 800b6fc: 4a17 ldr r2, [pc, #92] @ (800b75c ) 800b6fe: fb82 1203 smull r1, r2, r2, r3 800b702: 441a add r2, r3 800b704: 11d2 asrs r2, r2, #7 800b706: 17db asrs r3, r3, #31 800b708: 1ad2 subs r2, r2, r3 800b70a: 4b15 ldr r3, [pc, #84] @ (800b760 ) 800b70c: 681b ldr r3, [r3, #0] 800b70e: 639a str r2, [r3, #56] @ 0x38 htim4.Instance->CCR3 = color->G * 100 / 255; 800b710: 687b ldr r3, [r7, #4] 800b712: 785b ldrb r3, [r3, #1] 800b714: 461a mov r2, r3 800b716: 2364 movs r3, #100 @ 0x64 800b718: fb02 f303 mul.w r3, r2, r3 800b71c: 4a0f ldr r2, [pc, #60] @ (800b75c ) 800b71e: fb82 1203 smull r1, r2, r2, r3 800b722: 441a add r2, r3 800b724: 11d2 asrs r2, r2, #7 800b726: 17db asrs r3, r3, #31 800b728: 1ad2 subs r2, r2, r3 800b72a: 4b0d ldr r3, [pc, #52] @ (800b760 ) 800b72c: 681b ldr r3, [r3, #0] 800b72e: 63da str r2, [r3, #60] @ 0x3c htim4.Instance->CCR4 = color->B * 100 / 255; 800b730: 687b ldr r3, [r7, #4] 800b732: 789b ldrb r3, [r3, #2] 800b734: 461a mov r2, r3 800b736: 2364 movs r3, #100 @ 0x64 800b738: fb02 f303 mul.w r3, r2, r3 800b73c: 4a07 ldr r2, [pc, #28] @ (800b75c ) 800b73e: fb82 1203 smull r1, r2, r2, r3 800b742: 441a add r2, r3 800b744: 11d2 asrs r2, r2, #7 800b746: 17db asrs r3, r3, #31 800b748: 1ad2 subs r2, r2, r3 800b74a: 4b05 ldr r3, [pc, #20] @ (800b760 ) 800b74c: 681b ldr r3, [r3, #0] 800b74e: 641a str r2, [r3, #64] @ 0x40 } 800b750: bf00 nop 800b752: 370c adds r7, #12 800b754: 46bd mov sp, r7 800b756: bc80 pop {r7} 800b758: 4770 bx lr 800b75a: bf00 nop 800b75c: 80808081 .word 0x80808081 800b760: 20000f10 .word 0x20000f10 0800b764 : void LED_SetColor(RGB_Cycle_t *color){ 800b764: b480 push {r7} 800b766: b083 sub sp, #12 800b768: af00 add r7, sp, #0 800b76a: 6078 str r0, [r7, #4] memcpy(&LED_Cycle, color, sizeof(RGB_Cycle_t)); 800b76c: 4b05 ldr r3, [pc, #20] @ (800b784 ) 800b76e: 687a ldr r2, [r7, #4] 800b770: 6810 ldr r0, [r2, #0] 800b772: 6851 ldr r1, [r2, #4] 800b774: c303 stmia r3!, {r0, r1} 800b776: 8912 ldrh r2, [r2, #8] 800b778: 801a strh r2, [r3, #0] } 800b77a: bf00 nop 800b77c: 370c adds r7, #12 800b77e: 46bd mov sp, r7 800b780: bc80 pop {r7} 800b782: 4770 bx lr 800b784: 20000784 .word 0x20000784 0800b788 : void LED_Init(){ 800b788: b580 push {r7, lr} 800b78a: b082 sub sp, #8 800b78c: af00 add r7, sp, #0 RGB_t color = {.R=0, .G=0, .B=0}; 800b78e: 2300 movs r3, #0 800b790: 713b strb r3, [r7, #4] 800b792: 2300 movs r3, #0 800b794: 717b strb r3, [r7, #5] 800b796: 2300 movs r3, #0 800b798: 71bb strb r3, [r7, #6] HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_2); 800b79a: 2104 movs r1, #4 800b79c: 4809 ldr r0, [pc, #36] @ (800b7c4 ) 800b79e: f005 fc19 bl 8010fd4 HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); 800b7a2: 2108 movs r1, #8 800b7a4: 4807 ldr r0, [pc, #28] @ (800b7c4 ) 800b7a6: f005 fc15 bl 8010fd4 HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4); 800b7aa: 210c movs r1, #12 800b7ac: 4805 ldr r0, [pc, #20] @ (800b7c4 ) 800b7ae: f005 fc11 bl 8010fd4 RGB_SetColor(&color); 800b7b2: 1d3b adds r3, r7, #4 800b7b4: 4618 mov r0, r3 800b7b6: f7ff ff97 bl 800b6e8 } 800b7ba: bf00 nop 800b7bc: 3708 adds r7, #8 800b7be: 46bd mov sp, r7 800b7c0: bd80 pop {r7, pc} 800b7c2: bf00 nop 800b7c4: 20000f10 .word 0x20000f10 0800b7c8 : // } // } // } // } void LED_Task(){ 800b7c8: b580 push {r7, lr} 800b7ca: b082 sub sp, #8 800b7cc: af02 add r7, sp, #8 static uint32_t led_tick; if((HAL_GetTick() - led_tick) > 20){ 800b7ce: f002 f8c5 bl 800d95c 800b7d2: 4602 mov r2, r0 800b7d4: 4b46 ldr r3, [pc, #280] @ (800b8f0 ) 800b7d6: 681b ldr r3, [r3, #0] 800b7d8: 1ad3 subs r3, r2, r3 800b7da: 2b14 cmp r3, #20 800b7dc: f240 8085 bls.w 800b8ea led_tick = HAL_GetTick(); 800b7e0: f002 f8bc bl 800d95c 800b7e4: 4603 mov r3, r0 800b7e6: 4a42 ldr r2, [pc, #264] @ (800b8f0 ) 800b7e8: 6013 str r3, [r2, #0] LED_State.tick++; 800b7ea: 4b42 ldr r3, [pc, #264] @ (800b8f4 ) 800b7ec: 885b ldrh r3, [r3, #2] 800b7ee: 3301 adds r3, #1 800b7f0: b29a uxth r2, r3 800b7f2: 4b40 ldr r3, [pc, #256] @ (800b8f4 ) 800b7f4: 805a strh r2, [r3, #2] // LED_PhaseSync(led_n); switch(LED_State.state){ 800b7f6: 4b3f ldr r3, [pc, #252] @ (800b8f4 ) 800b7f8: 781b ldrb r3, [r3, #0] 800b7fa: 2b03 cmp r3, #3 800b7fc: d867 bhi.n 800b8ce 800b7fe: a201 add r2, pc, #4 @ (adr r2, 800b804 ) 800b800: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b804: 0800b815 .word 0x0800b815 800b808: 0800b847 .word 0x0800b847 800b80c: 0800b873 .word 0x0800b873 800b810: 0800b8a5 .word 0x0800b8a5 case LED_RISING: interpolateColors(&LED_Cycle.Color2, &LED_Cycle.Color1, LED_State.tick, LED_Cycle.Tr, &LED_State.color); 800b814: 4b37 ldr r3, [pc, #220] @ (800b8f4 ) 800b816: 885a ldrh r2, [r3, #2] 800b818: 4b37 ldr r3, [pc, #220] @ (800b8f8 ) 800b81a: 78db ldrb r3, [r3, #3] 800b81c: 4619 mov r1, r3 800b81e: 4b37 ldr r3, [pc, #220] @ (800b8fc ) 800b820: 9300 str r3, [sp, #0] 800b822: 460b mov r3, r1 800b824: 4934 ldr r1, [pc, #208] @ (800b8f8 ) 800b826: 4836 ldr r0, [pc, #216] @ (800b900 ) 800b828: f7ff feee bl 800b608 if(LED_State.tick>LED_Cycle.Tr){ 800b82c: 4b31 ldr r3, [pc, #196] @ (800b8f4 ) 800b82e: 885b ldrh r3, [r3, #2] 800b830: 4a31 ldr r2, [pc, #196] @ (800b8f8 ) 800b832: 78d2 ldrb r2, [r2, #3] 800b834: 4293 cmp r3, r2 800b836: d94e bls.n 800b8d6 LED_State.state = LED_HIGH; 800b838: 4b2e ldr r3, [pc, #184] @ (800b8f4 ) 800b83a: 2201 movs r2, #1 800b83c: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b83e: 4b2d ldr r3, [pc, #180] @ (800b8f4 ) 800b840: 2200 movs r2, #0 800b842: 805a strh r2, [r3, #2] } break; 800b844: e047 b.n 800b8d6 case LED_HIGH: memcpy(&LED_State.color, &LED_Cycle.Color1, sizeof(RGB_t)); 800b846: 4b2b ldr r3, [pc, #172] @ (800b8f4 ) 800b848: 4a2b ldr r2, [pc, #172] @ (800b8f8 ) 800b84a: 3304 adds r3, #4 800b84c: 6812 ldr r2, [r2, #0] 800b84e: 4611 mov r1, r2 800b850: 8019 strh r1, [r3, #0] 800b852: 3302 adds r3, #2 800b854: 0c12 lsrs r2, r2, #16 800b856: 701a strb r2, [r3, #0] if(LED_State.tick>LED_Cycle.Th){ 800b858: 4b26 ldr r3, [pc, #152] @ (800b8f4 ) 800b85a: 885b ldrh r3, [r3, #2] 800b85c: 4a26 ldr r2, [pc, #152] @ (800b8f8 ) 800b85e: 7912 ldrb r2, [r2, #4] 800b860: 4293 cmp r3, r2 800b862: d93a bls.n 800b8da LED_State.state = LED_FALLING; 800b864: 4b23 ldr r3, [pc, #140] @ (800b8f4 ) 800b866: 2202 movs r2, #2 800b868: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b86a: 4b22 ldr r3, [pc, #136] @ (800b8f4 ) 800b86c: 2200 movs r2, #0 800b86e: 805a strh r2, [r3, #2] } break; 800b870: e033 b.n 800b8da case LED_FALLING: interpolateColors(&LED_Cycle.Color1, &LED_Cycle.Color2, LED_State.tick, LED_Cycle.Tf, &LED_State.color); 800b872: 4b20 ldr r3, [pc, #128] @ (800b8f4 ) 800b874: 885a ldrh r2, [r3, #2] 800b876: 4b20 ldr r3, [pc, #128] @ (800b8f8 ) 800b878: 795b ldrb r3, [r3, #5] 800b87a: 4619 mov r1, r3 800b87c: 4b1f ldr r3, [pc, #124] @ (800b8fc ) 800b87e: 9300 str r3, [sp, #0] 800b880: 460b mov r3, r1 800b882: 491f ldr r1, [pc, #124] @ (800b900 ) 800b884: 481c ldr r0, [pc, #112] @ (800b8f8 ) 800b886: f7ff febf bl 800b608 if(LED_State.tick>LED_Cycle.Tf){ 800b88a: 4b1a ldr r3, [pc, #104] @ (800b8f4 ) 800b88c: 885b ldrh r3, [r3, #2] 800b88e: 4a1a ldr r2, [pc, #104] @ (800b8f8 ) 800b890: 7952 ldrb r2, [r2, #5] 800b892: 4293 cmp r3, r2 800b894: d923 bls.n 800b8de LED_State.state = LED_LOW; 800b896: 4b17 ldr r3, [pc, #92] @ (800b8f4 ) 800b898: 2203 movs r2, #3 800b89a: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b89c: 4b15 ldr r3, [pc, #84] @ (800b8f4 ) 800b89e: 2200 movs r2, #0 800b8a0: 805a strh r2, [r3, #2] } break; 800b8a2: e01c b.n 800b8de case LED_LOW: memcpy(&LED_State.color, &LED_Cycle.Color2, sizeof(RGB_t)); 800b8a4: 4b13 ldr r3, [pc, #76] @ (800b8f4 ) 800b8a6: 4a14 ldr r2, [pc, #80] @ (800b8f8 ) 800b8a8: 3304 adds r3, #4 800b8aa: 3207 adds r2, #7 800b8ac: 8811 ldrh r1, [r2, #0] 800b8ae: 7892 ldrb r2, [r2, #2] 800b8b0: 8019 strh r1, [r3, #0] 800b8b2: 709a strb r2, [r3, #2] if(LED_State.tick>LED_Cycle.Tl){ 800b8b4: 4b0f ldr r3, [pc, #60] @ (800b8f4 ) 800b8b6: 885b ldrh r3, [r3, #2] 800b8b8: 4a0f ldr r2, [pc, #60] @ (800b8f8 ) 800b8ba: 7992 ldrb r2, [r2, #6] 800b8bc: 4293 cmp r3, r2 800b8be: d910 bls.n 800b8e2 LED_State.state = LED_RISING; 800b8c0: 4b0c ldr r3, [pc, #48] @ (800b8f4 ) 800b8c2: 2200 movs r2, #0 800b8c4: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b8c6: 4b0b ldr r3, [pc, #44] @ (800b8f4 ) 800b8c8: 2200 movs r2, #0 800b8ca: 805a strh r2, [r3, #2] } break; 800b8cc: e009 b.n 800b8e2 default: LED_State.state = LED_RISING; 800b8ce: 4b09 ldr r3, [pc, #36] @ (800b8f4 ) 800b8d0: 2200 movs r2, #0 800b8d2: 701a strb r2, [r3, #0] 800b8d4: e006 b.n 800b8e4 break; 800b8d6: bf00 nop 800b8d8: e004 b.n 800b8e4 break; 800b8da: bf00 nop 800b8dc: e002 b.n 800b8e4 break; 800b8de: bf00 nop 800b8e0: e000 b.n 800b8e4 break; 800b8e2: bf00 nop } RGB_SetColor(&LED_State.color); 800b8e4: 4805 ldr r0, [pc, #20] @ (800b8fc ) 800b8e6: f7ff feff bl 800b6e8 } } 800b8ea: bf00 nop 800b8ec: 46bd mov sp, r7 800b8ee: bd80 pop {r7, pc} 800b8f0: 20000790 .word 0x20000790 800b8f4: 2000077c .word 0x2000077c 800b8f8: 20000784 .word 0x20000784 800b8fc: 20000780 .word 0x20000780 800b900: 2000078b .word 0x2000078b 0800b904 : RTC_HandleTypeDef hrtc; /* RTC init function */ void MX_RTC_Init(void) { 800b904: b580 push {r7, lr} 800b906: af00 add r7, sp, #0 /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 800b908: 4b0a ldr r3, [pc, #40] @ (800b934 ) 800b90a: 4a0b ldr r2, [pc, #44] @ (800b938 ) 800b90c: 601a str r2, [r3, #0] hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; 800b90e: 4b09 ldr r3, [pc, #36] @ (800b934 ) 800b910: f04f 32ff mov.w r2, #4294967295 800b914: 605a str r2, [r3, #4] hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; 800b916: 4b07 ldr r3, [pc, #28] @ (800b934 ) 800b918: f44f 7280 mov.w r2, #256 @ 0x100 800b91c: 609a str r2, [r3, #8] if (HAL_RTC_Init(&hrtc) != HAL_OK) 800b91e: 4805 ldr r0, [pc, #20] @ (800b934 ) 800b920: f005 f8b2 bl 8010a88 800b924: 4603 mov r3, r0 800b926: 2b00 cmp r3, #0 800b928: d001 beq.n 800b92e { Error_Handler(); 800b92a: f7ff f867 bl 800a9fc } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 800b92e: bf00 nop 800b930: bd80 pop {r7, pc} 800b932: bf00 nop 800b934: 20000794 .word 0x20000794 800b938: 40002800 .word 0x40002800 0800b93c : void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) { 800b93c: b580 push {r7, lr} 800b93e: b084 sub sp, #16 800b940: af00 add r7, sp, #0 800b942: 6078 str r0, [r7, #4] if(rtcHandle->Instance==RTC) 800b944: 687b ldr r3, [r7, #4] 800b946: 681b ldr r3, [r3, #0] 800b948: 4a0b ldr r2, [pc, #44] @ (800b978 ) 800b94a: 4293 cmp r3, r2 800b94c: d110 bne.n 800b970 { /* USER CODE BEGIN RTC_MspInit 0 */ /* USER CODE END RTC_MspInit 0 */ HAL_PWR_EnableBkUpAccess(); 800b94e: f004 f82f bl 800f9b0 /* Enable BKP CLK enable for backup registers */ __HAL_RCC_BKP_CLK_ENABLE(); 800b952: 4b0a ldr r3, [pc, #40] @ (800b97c ) 800b954: 69db ldr r3, [r3, #28] 800b956: 4a09 ldr r2, [pc, #36] @ (800b97c ) 800b958: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800b95c: 61d3 str r3, [r2, #28] 800b95e: 4b07 ldr r3, [pc, #28] @ (800b97c ) 800b960: 69db ldr r3, [r3, #28] 800b962: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800b966: 60fb str r3, [r7, #12] 800b968: 68fb ldr r3, [r7, #12] /* RTC clock enable */ __HAL_RCC_RTC_ENABLE(); 800b96a: 4b05 ldr r3, [pc, #20] @ (800b980 ) 800b96c: 2201 movs r2, #1 800b96e: 601a str r2, [r3, #0] /* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE END RTC_MspInit 1 */ } } 800b970: bf00 nop 800b972: 3710 adds r7, #16 800b974: 46bd mov sp, r7 800b976: bd80 pop {r7, pc} 800b978: 40002800 .word 0x40002800 800b97c: 40021000 .word 0x40021000 800b980: 4242043c .word 0x4242043c 0800b984 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 800b984: b480 push {r7} 800b986: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 800b988: f3bf 8f4f dsb sy } 800b98c: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800b98e: 4b06 ldr r3, [pc, #24] @ (800b9a8 <__NVIC_SystemReset+0x24>) 800b990: 68db ldr r3, [r3, #12] 800b992: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800b996: 4904 ldr r1, [pc, #16] @ (800b9a8 <__NVIC_SystemReset+0x24>) 800b998: 4b04 ldr r3, [pc, #16] @ (800b9ac <__NVIC_SystemReset+0x28>) 800b99a: 4313 orrs r3, r2 800b99c: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800b99e: f3bf 8f4f dsb sy } 800b9a2: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 800b9a4: bf00 nop 800b9a6: e7fd b.n 800b9a4 <__NVIC_SystemReset+0x20> 800b9a8: e000ed00 .word 0xe000ed00 800b9ac: 05fa0004 .word 0x05fa0004 0800b9b0 : CONN_State_t CCS_EvseState; CCS_ConnectorState_t CCS_ConnectorState = CCS_UNPLUGGED; static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len); void CCS_RxEventCallback(UART_HandleTypeDef *huart, uint16_t size) { 800b9b0: b580 push {r7, lr} 800b9b2: b082 sub sp, #8 800b9b4: af00 add r7, sp, #0 800b9b6: 6078 str r0, [r7, #4] 800b9b8: 460b mov r3, r1 800b9ba: 807b strh r3, [r7, #2] if (huart != &huart3) { 800b9bc: 687b ldr r3, [r7, #4] 800b9be: 4a0b ldr r2, [pc, #44] @ (800b9ec ) 800b9c0: 4293 cmp r3, r2 800b9c2: d10f bne.n 800b9e4 return; } rx_armed = 0; 800b9c4: 4b0a ldr r3, [pc, #40] @ (800b9f0 ) 800b9c6: 2200 movs r2, #0 800b9c8: 701a strb r2, [r3, #0] if (size > 0 && size <= sizeof(rx_buffer)) { 800b9ca: 887b ldrh r3, [r7, #2] 800b9cc: 2b00 cmp r3, #0 800b9ce: d00a beq.n 800b9e6 800b9d0: 887b ldrh r3, [r7, #2] 800b9d2: f5b3 7f80 cmp.w r3, #256 @ 0x100 800b9d6: d806 bhi.n 800b9e6 process_received_packet(rx_buffer, size); 800b9d8: 887b ldrh r3, [r7, #2] 800b9da: 4619 mov r1, r3 800b9dc: 4805 ldr r0, [pc, #20] @ (800b9f4 ) 800b9de: f000 fcd7 bl 800c390 800b9e2: e000 b.n 800b9e6 return; 800b9e4: bf00 nop } } 800b9e6: 3708 adds r7, #8 800b9e8: 46bd mov sp, r7 800b9ea: bd80 pop {r7, pc} 800b9ec: 20001030 .word 0x20001030 800b9f0: 200009cc .word 0x200009cc 800b9f4: 200007cc .word 0x200007cc 0800b9f8 : void CCS_SerialLoop(void) { 800b9f8: b580 push {r7, lr} 800b9fa: af00 add r7, sp, #0 static uint32_t replug_tick = 0; static uint32_t replug_watchdog_tick = 0; static uint32_t replug_watchdog1_tick = 0; static uint32_t last_state_sent = 0; if (!rx_armed && HAL_UART_GetState(&huart3) == HAL_UART_STATE_READY) { 800b9fc: 4ba6 ldr r3, [pc, #664] @ (800bc98 ) 800b9fe: 781b ldrb r3, [r3, #0] 800ba00: 2b00 cmp r3, #0 800ba02: d111 bne.n 800ba28 800ba04: 48a5 ldr r0, [pc, #660] @ (800bc9c ) 800ba06: f006 fe8e bl 8012726 800ba0a: 4603 mov r3, r0 800ba0c: 2b20 cmp r3, #32 800ba0e: d10b bne.n 800ba28 if (HAL_UARTEx_ReceiveToIdle_IT(&huart3, rx_buffer, sizeof(rx_buffer)) == HAL_OK) { 800ba10: f44f 7280 mov.w r2, #256 @ 0x100 800ba14: 49a2 ldr r1, [pc, #648] @ (800bca0 ) 800ba16: 48a1 ldr r0, [pc, #644] @ (800bc9c ) 800ba18: f006 fa66 bl 8011ee8 800ba1c: 4603 mov r3, r0 800ba1e: 2b00 cmp r3, #0 800ba20: d102 bne.n 800ba28 rx_armed = 1; 800ba22: 4b9d ldr r3, [pc, #628] @ (800bc98 ) 800ba24: 2201 movs r2, #1 800ba26: 701a strb r2, [r3, #0] } } /* Read CP once per loop and use buffered value below. */ cp_state_buffer = CP_GetState(); 800ba28: f7fe fb96 bl 800a158 800ba2c: 4603 mov r3, r0 800ba2e: 461a mov r2, r3 800ba30: 4b9c ldr r3, [pc, #624] @ (800bca4 ) 800ba32: 701a strb r2, [r3, #0] if (CONN.connControl != CMD_NONE) { 800ba34: 4b9c ldr r3, [pc, #624] @ (800bca8 ) 800ba36: 781b ldrb r3, [r3, #0] 800ba38: 2b00 cmp r3, #0 800ba3a: d003 beq.n 800ba44 last_cmd = CONN.connControl; 800ba3c: 4b9a ldr r3, [pc, #616] @ (800bca8 ) 800ba3e: 781a ldrb r2, [r3, #0] 800ba40: 4b9a ldr r3, [pc, #616] @ (800bcac ) 800ba42: 701a strb r2, [r3, #0] } if((HAL_GetTick() - last_cmd_sent) > CMD_INTERVAL){ 800ba44: f001 ff8a bl 800d95c 800ba48: 4602 mov r2, r0 800ba4a: 4b99 ldr r3, [pc, #612] @ (800bcb0 ) 800ba4c: 681b ldr r3, [r3, #0] 800ba4e: 1ad3 subs r3, r2, r3 800ba50: 2b0a cmp r3, #10 800ba52: d953 bls.n 800bafc if ((HAL_GetTick() - last_state_sent) >= 200) { 800ba54: f001 ff82 bl 800d95c 800ba58: 4602 mov r2, r0 800ba5a: 4b96 ldr r3, [pc, #600] @ (800bcb4 ) 800ba5c: 681b ldr r3, [r3, #0] 800ba5e: 1ad3 subs r3, r2, r3 800ba60: 2bc7 cmp r3, #199 @ 0xc7 800ba62: d906 bls.n 800ba72 send_state(); 800ba64: f000 fb0e bl 800c084 last_state_sent = HAL_GetTick(); 800ba68: f001 ff78 bl 800d95c 800ba6c: 4603 mov r3, r0 800ba6e: 4a91 ldr r2, [pc, #580] @ (800bcb4 ) 800ba70: 6013 str r3, [r2, #0] } if (ESTOP) { 800ba72: 4b91 ldr r3, [pc, #580] @ (800bcb8 ) 800ba74: 781b ldrb r3, [r3, #0] 800ba76: 2b00 cmp r3, #0 800ba78: d008 beq.n 800ba8c log_printf(LOG_ERR, "ESTOP triggered\n"); 800ba7a: 4990 ldr r1, [pc, #576] @ (800bcbc ) 800ba7c: 2004 movs r0, #4 800ba7e: f7fe fcfd bl 800a47c CCS_SendEmergencyStop(); 800ba82: f000 faa0 bl 800bfc6 ESTOP = 0; 800ba86: 4b8c ldr r3, [pc, #560] @ (800bcb8 ) 800ba88: 2200 movs r2, #0 800ba8a: 701a strb r2, [r3, #0] } if (((CONN.connControl == CMD_STOP) || 800ba8c: 4b86 ldr r3, [pc, #536] @ (800bca8 ) 800ba8e: 781b ldrb r3, [r3, #0] 800ba90: 2b01 cmp r3, #1 800ba92: d003 beq.n 800ba9c (CONN.chargingError != CONN_NO_ERROR)) && 800ba94: 4b84 ldr r3, [pc, #528] @ (800bca8 ) 800ba96: 7f5b ldrb r3, [r3, #29] if (((CONN.connControl == CMD_STOP) || 800ba98: 2b00 cmp r3, #0 800ba9a: d013 beq.n 800bac4 ((HAL_GetTick() - last_stop_sent) > 1000)) { 800ba9c: f001 ff5e bl 800d95c 800baa0: 4602 mov r2, r0 800baa2: 4b87 ldr r3, [pc, #540] @ (800bcc0 ) 800baa4: 681b ldr r3, [r3, #0] 800baa6: 1ad3 subs r3, r2, r3 (CONN.chargingError != CONN_NO_ERROR)) && 800baa8: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800baac: d90a bls.n 800bac4 last_stop_sent = HAL_GetTick(); 800baae: f001 ff55 bl 800d95c 800bab2: 4603 mov r3, r0 800bab4: 4a82 ldr r2, [pc, #520] @ (800bcc0 ) 800bab6: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "Stopping charging...\n"); 800bab8: 4982 ldr r1, [pc, #520] @ (800bcc4 ) 800baba: 2005 movs r0, #5 800babc: f7fe fcde bl 800a47c CCS_SendEmergencyStop(); 800bac0: f000 fa81 bl 800bfc6 } if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800bac4: 4b80 ldr r3, [pc, #512] @ (800bcc8 ) 800bac6: 781b ldrb r3, [r3, #0] 800bac8: 2b0c cmp r3, #12 800baca: d003 beq.n 800bad4 800bacc: 4b7e ldr r3, [pc, #504] @ (800bcc8 ) 800bace: 781b ldrb r3, [r3, #0] 800bad0: 2b0b cmp r3, #11 800bad2: d113 bne.n 800bafc ((HAL_GetTick() - last_stop_sent) > 1000)) { 800bad4: f001 ff42 bl 800d95c 800bad8: 4602 mov r2, r0 800bada: 4b79 ldr r3, [pc, #484] @ (800bcc0 ) 800badc: 681b ldr r3, [r3, #0] 800bade: 1ad3 subs r3, r2, r3 if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800bae0: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bae4: d90a bls.n 800bafc last_stop_sent = HAL_GetTick(); 800bae6: f001 ff39 bl 800d95c 800baea: 4603 mov r3, r0 800baec: 4a74 ldr r2, [pc, #464] @ (800bcc0 ) 800baee: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "FinishedEV, stopping...\n"); 800baf0: 4976 ldr r1, [pc, #472] @ (800bccc ) 800baf2: 2005 movs r0, #5 800baf4: f7fe fcc2 bl 800a47c CCS_SendEmergencyStop(); 800baf8: f000 fa65 bl 800bfc6 } (void)replug_watchdog_tick; (void)replug_watchdog1_tick; switch(CCS_ConnectorState){ 800bafc: 4b74 ldr r3, [pc, #464] @ (800bcd0 ) 800bafe: 781b ldrb r3, [r3, #0] 800bb00: 2b04 cmp r3, #4 800bb02: f200 80f8 bhi.w 800bcf6 800bb06: a201 add r2, pc, #4 @ (adr r2, 800bb0c ) 800bb08: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800bb0c: 0800bb21 .word 0x0800bb21 800bb10: 0800bb41 .word 0x0800bb41 800bb14: 0800bb85 .word 0x0800bb85 800bb18: 0800bbc1 .word 0x0800bbc1 800bb1c: 0800bc11 .word 0x0800bc11 case CCS_DISABLED: RELAY_Write(RELAY_CP, 0); 800bb20: 2100 movs r1, #0 800bb22: 2005 movs r0, #5 800bb24: f7fd fcc4 bl 80094b0 CONN_SetState(Disabled); 800bb28: 2002 movs r0, #2 800bb2a: f7fe f8c3 bl 8009cb4 if (CONN.chargingError == CONN_NO_ERROR){ 800bb2e: 4b5e ldr r3, [pc, #376] @ (800bca8 ) 800bb30: 7f5b ldrb r3, [r3, #29] 800bb32: 2b00 cmp r3, #0 800bb34: f040 80a7 bne.w 800bc86 CCS_ConnectorState = CCS_UNPLUGGED; 800bb38: 4b65 ldr r3, [pc, #404] @ (800bcd0 ) 800bb3a: 2201 movs r2, #1 800bb3c: 701a strb r2, [r3, #0] } break; 800bb3e: e0a2 b.n 800bc86 case CCS_UNPLUGGED: RELAY_Write(RELAY_CP, 1); 800bb40: 2101 movs r1, #1 800bb42: 2005 movs r0, #5 800bb44: f7fd fcb4 bl 80094b0 CONN_SetState(Unplugged); 800bb48: 2001 movs r0, #1 800bb4a: f7fe f8b3 bl 8009cb4 if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || (cp_state_buffer == EV_STATE_C_CONN_ACTIVE)){ 800bb4e: 4b55 ldr r3, [pc, #340] @ (800bca4 ) 800bb50: 781b ldrb r3, [r3, #0] 800bb52: 2b01 cmp r3, #1 800bb54: d003 beq.n 800bb5e 800bb56: 4b53 ldr r3, [pc, #332] @ (800bca4 ) 800bb58: 781b ldrb r3, [r3, #0] 800bb5a: 2b02 cmp r3, #2 800bb5c: d102 bne.n 800bb64 CCS_ConnectorState = CCS_AUTH_REQUIRED; 800bb5e: 4b5c ldr r3, [pc, #368] @ (800bcd0 ) 800bb60: 2202 movs r2, #2 800bb62: 701a strb r2, [r3, #0] } if (CONN.chargingError != CONN_NO_ERROR){ 800bb64: 4b50 ldr r3, [pc, #320] @ (800bca8 ) 800bb66: 7f5b ldrb r3, [r3, #29] 800bb68: 2b00 cmp r3, #0 800bb6a: f000 808e beq.w 800bc8a log_printf(LOG_ERR, "Charging error %d, state -> disabled\n", CONN.chargingError); 800bb6e: 4b4e ldr r3, [pc, #312] @ (800bca8 ) 800bb70: 7f5b ldrb r3, [r3, #29] 800bb72: 461a mov r2, r3 800bb74: 4957 ldr r1, [pc, #348] @ (800bcd4 ) 800bb76: 2004 movs r0, #4 800bb78: f7fe fc80 bl 800a47c CCS_ConnectorState = CCS_DISABLED; 800bb7c: 4b54 ldr r3, [pc, #336] @ (800bcd0 ) 800bb7e: 2200 movs r2, #0 800bb80: 701a strb r2, [r3, #0] } break; 800bb82: e082 b.n 800bc8a case CCS_AUTH_REQUIRED: RELAY_Write(RELAY_CP, 1); 800bb84: 2101 movs r1, #1 800bb86: 2005 movs r0, #5 800bb88: f7fd fc92 bl 80094b0 CONN_SetState(AuthRequired); 800bb8c: 2004 movs r0, #4 800bb8e: f7fe f891 bl 8009cb4 if(CONN.connControl == CMD_START){ 800bb92: 4b45 ldr r3, [pc, #276] @ (800bca8 ) 800bb94: 781b ldrb r3, [r3, #0] 800bb96: 2b02 cmp r3, #2 800bb98: d106 bne.n 800bba8 log_printf(LOG_INFO, "Charging permitted, start charging\n"); 800bb9a: 494f ldr r1, [pc, #316] @ (800bcd8 ) 800bb9c: 2007 movs r0, #7 800bb9e: f7fe fc6d bl 800a47c CCS_ConnectorState = CCS_CONNECTED; 800bba2: 4b4b ldr r3, [pc, #300] @ (800bcd0 ) 800bba4: 2203 movs r2, #3 800bba6: 701a strb r2, [r3, #0] } if (cp_state_buffer == EV_STATE_A_IDLE){ 800bba8: 4b3e ldr r3, [pc, #248] @ (800bca4 ) 800bbaa: 781b ldrb r3, [r3, #0] 800bbac: 2b00 cmp r3, #0 800bbae: d16e bne.n 800bc8e log_printf(LOG_INFO, "Car unplugged\n"); 800bbb0: 494a ldr r1, [pc, #296] @ (800bcdc ) 800bbb2: 2007 movs r0, #7 800bbb4: f7fe fc62 bl 800a47c CCS_ConnectorState = CCS_UNPLUGGED; 800bbb8: 4b45 ldr r3, [pc, #276] @ (800bcd0 ) 800bbba: 2201 movs r2, #1 800bbbc: 701a strb r2, [r3, #0] } break; 800bbbe: e066 b.n 800bc8e case CCS_CONNECTED: RELAY_Write(RELAY_CP, 1); 800bbc0: 2101 movs r1, #1 800bbc2: 2005 movs r0, #5 800bbc4: f7fd fc74 bl 80094b0 if(CCS_EvseState < Preparing) { 800bbc8: 4b3f ldr r3, [pc, #252] @ (800bcc8 ) 800bbca: 781b ldrb r3, [r3, #0] 800bbcc: 2b02 cmp r3, #2 800bbce: d803 bhi.n 800bbd8 CONN_SetState(Preparing); 800bbd0: 2003 movs r0, #3 800bbd2: f7fe f86f bl 8009cb4 800bbd6: e004 b.n 800bbe2 } else { CONN_SetState(CCS_EvseState); 800bbd8: 4b3b ldr r3, [pc, #236] @ (800bcc8 ) 800bbda: 781b ldrb r3, [r3, #0] 800bbdc: 4618 mov r0, r3 800bbde: f7fe f869 bl 8009cb4 } if (cp_state_buffer == EV_STATE_A_IDLE){ 800bbe2: 4b30 ldr r3, [pc, #192] @ (800bca4 ) 800bbe4: 781b ldrb r3, [r3, #0] 800bbe6: 2b00 cmp r3, #0 800bbe8: d106 bne.n 800bbf8 log_printf(LOG_INFO, "Car unplugged\n"); 800bbea: 493c ldr r1, [pc, #240] @ (800bcdc ) 800bbec: 2007 movs r0, #7 800bbee: f7fe fc45 bl 800a47c CCS_ConnectorState = CCS_UNPLUGGED; 800bbf2: 4b37 ldr r3, [pc, #220] @ (800bcd0 ) 800bbf4: 2201 movs r2, #1 800bbf6: 701a strb r2, [r3, #0] } if(REPLUG > 0){ 800bbf8: 4b39 ldr r3, [pc, #228] @ (800bce0 ) 800bbfa: 781b ldrb r3, [r3, #0] 800bbfc: 2b00 cmp r3, #0 800bbfe: d048 beq.n 800bc92 log_printf(LOG_INFO, "Replugging...\n"); 800bc00: 4938 ldr r1, [pc, #224] @ (800bce4 ) 800bc02: 2007 movs r0, #7 800bc04: f7fe fc3a bl 800a47c CCS_ConnectorState = CCS_REPLUGGING; 800bc08: 4b31 ldr r3, [pc, #196] @ (800bcd0 ) 800bc0a: 2204 movs r2, #4 800bc0c: 701a strb r2, [r3, #0] } break; 800bc0e: e040 b.n 800bc92 case CCS_REPLUGGING: RELAY_Write(RELAY_CP, 0); 800bc10: 2100 movs r1, #0 800bc12: 2005 movs r0, #5 800bc14: f7fd fc4c bl 80094b0 CONN_SetState(Replugging); 800bc18: 200d movs r0, #13 800bc1a: f7fe f84b bl 8009cb4 if((HAL_GetTick() - replug_tick) > 1000){ 800bc1e: f001 fe9d bl 800d95c 800bc22: 4602 mov r2, r0 800bc24: 4b30 ldr r3, [pc, #192] @ (800bce8 ) 800bc26: 681b ldr r3, [r3, #0] 800bc28: 1ad3 subs r3, r2, r3 800bc2a: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bc2e: d91a bls.n 800bc66 replug_tick = HAL_GetTick(); 800bc30: f001 fe94 bl 800d95c 800bc34: 4603 mov r3, r0 800bc36: 4a2c ldr r2, [pc, #176] @ (800bce8 ) 800bc38: 6013 str r3, [r2, #0] if(REPLUG > 0){ 800bc3a: 4b29 ldr r3, [pc, #164] @ (800bce0 ) 800bc3c: 781b ldrb r3, [r3, #0] 800bc3e: 2b00 cmp r3, #0 800bc40: d00a beq.n 800bc58 if (REPLUG != 0xFF) REPLUG--; 800bc42: 4b27 ldr r3, [pc, #156] @ (800bce0 ) 800bc44: 781b ldrb r3, [r3, #0] 800bc46: 2bff cmp r3, #255 @ 0xff 800bc48: d00d beq.n 800bc66 800bc4a: 4b25 ldr r3, [pc, #148] @ (800bce0 ) 800bc4c: 781b ldrb r3, [r3, #0] 800bc4e: 3b01 subs r3, #1 800bc50: b2da uxtb r2, r3 800bc52: 4b23 ldr r3, [pc, #140] @ (800bce0 ) 800bc54: 701a strb r2, [r3, #0] 800bc56: e006 b.n 800bc66 } else { log_printf(LOG_INFO, "Replugging finished, but car unplugged\n"); 800bc58: 4924 ldr r1, [pc, #144] @ (800bcec ) 800bc5a: 2007 movs r0, #7 800bc5c: f7fe fc0e bl 800a47c CCS_ConnectorState = CCS_UNPLUGGED; 800bc60: 4b1b ldr r3, [pc, #108] @ (800bcd0 ) 800bc62: 2201 movs r2, #1 800bc64: 701a strb r2, [r3, #0] } } if(REPLUG == 0){ 800bc66: 4b1e ldr r3, [pc, #120] @ (800bce0 ) 800bc68: 781b ldrb r3, [r3, #0] 800bc6a: 2b00 cmp r3, #0 800bc6c: d142 bne.n 800bcf4 if(cp_state_buffer == EV_STATE_B_CONN_PREP){ 800bc6e: 4b0d ldr r3, [pc, #52] @ (800bca4 ) 800bc70: 781b ldrb r3, [r3, #0] 800bc72: 2b01 cmp r3, #1 800bc74: d13e bne.n 800bcf4 log_printf(LOG_INFO, "Replugging finished, car plugged, state -> auth required\n"); 800bc76: 491e ldr r1, [pc, #120] @ (800bcf0 ) 800bc78: 2007 movs r0, #7 800bc7a: f7fe fbff bl 800a47c CCS_ConnectorState = CCS_AUTH_REQUIRED; 800bc7e: 4b14 ldr r3, [pc, #80] @ (800bcd0 ) 800bc80: 2202 movs r2, #2 800bc82: 701a strb r2, [r3, #0] } } break; 800bc84: e036 b.n 800bcf4 break; 800bc86: bf00 nop 800bc88: e035 b.n 800bcf6 break; 800bc8a: bf00 nop 800bc8c: e033 b.n 800bcf6 break; 800bc8e: bf00 nop 800bc90: e031 b.n 800bcf6 break; 800bc92: bf00 nop 800bc94: e02f b.n 800bcf6 800bc96: bf00 nop 800bc98: 200009cc .word 0x200009cc 800bc9c: 20001030 .word 0x20001030 800bca0: 200007cc .word 0x200007cc 800bca4: 2000004f .word 0x2000004f 800bca8: 200001d4 .word 0x200001d4 800bcac: 200007c8 .word 0x200007c8 800bcb0: 200007c0 .word 0x200007c0 800bcb4: 20000a30 .word 0x20000a30 800bcb8: 200009cd .word 0x200009cd 800bcbc: 08014250 .word 0x08014250 800bcc0: 200007c4 .word 0x200007c4 800bcc4: 08014264 .word 0x08014264 800bcc8: 20000a2c .word 0x20000a2c 800bccc: 0801427c .word 0x0801427c 800bcd0: 20000050 .word 0x20000050 800bcd4: 08014298 .word 0x08014298 800bcd8: 080142c0 .word 0x080142c0 800bcdc: 080142e4 .word 0x080142e4 800bce0: 200009ce .word 0x200009ce 800bce4: 080142f4 .word 0x080142f4 800bce8: 20000a34 .word 0x20000a34 800bcec: 08014304 .word 0x08014304 800bcf0: 0801432c .word 0x0801432c break; 800bcf4: bf00 nop } // If Everest timeout happened, keep safe-state and limit log frequency. // The safe-state must remain until we receive a valid packet from the host. if (everest_timed_out) { 800bcf6: 4b3f ldr r3, [pc, #252] @ (800bdf4 ) 800bcf8: 781b ldrb r3, [r3, #0] 800bcfa: 2b00 cmp r3, #0 800bcfc: d01f beq.n 800bd3e if (last_everest_timeout_log_tick == 0 || 800bcfe: 4b3e ldr r3, [pc, #248] @ (800bdf8 ) 800bd00: 681b ldr r3, [r3, #0] 800bd02: 2b00 cmp r3, #0 800bd04: d008 beq.n 800bd18 (HAL_GetTick() - last_everest_timeout_log_tick) >= EVEREST_TIMEOUT_MS) { 800bd06: f001 fe29 bl 800d95c 800bd0a: 4602 mov r2, r0 800bd0c: 4b3a ldr r3, [pc, #232] @ (800bdf8 ) 800bd0e: 681b ldr r3, [r3, #0] 800bd10: 1ad3 subs r3, r2, r3 if (last_everest_timeout_log_tick == 0 || 800bd12: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800bd16: d308 bcc.n 800bd2a log_printf(LOG_ERR, "Everest timeout\n"); 800bd18: 4938 ldr r1, [pc, #224] @ (800bdfc ) 800bd1a: 2004 movs r0, #4 800bd1c: f7fe fbae bl 800a47c last_everest_timeout_log_tick = HAL_GetTick(); 800bd20: f001 fe1c bl 800d95c 800bd24: 4603 mov r3, r0 800bd26: 4a34 ldr r2, [pc, #208] @ (800bdf8 ) 800bd28: 6013 str r3, [r2, #0] } CONN.EnableOutput = 0; 800bd2a: 4b35 ldr r3, [pc, #212] @ (800be00 ) 800bd2c: 2200 movs r2, #0 800bd2e: 75da strb r2, [r3, #23] CCS_EvseState = Unknown; 800bd30: 4b34 ldr r3, [pc, #208] @ (800be04 ) 800bd32: 2200 movs r2, #0 800bd34: 701a strb r2, [r3, #0] CP_SetDuty(100); 800bd36: 2064 movs r0, #100 @ 0x64 800bd38: f7fe f9dc bl 800a0f4 800bd3c: e044 b.n 800bdc8 } else if (last_host_seen > 0 && (HAL_GetTick() - last_host_seen) > EVEREST_TIMEOUT_MS) { 800bd3e: 4b32 ldr r3, [pc, #200] @ (800be08 ) 800bd40: 681b ldr r3, [r3, #0] 800bd42: 2b00 cmp r3, #0 800bd44: d023 beq.n 800bd8e 800bd46: f001 fe09 bl 800d95c 800bd4a: 4602 mov r2, r0 800bd4c: 4b2e ldr r3, [pc, #184] @ (800be08 ) 800bd4e: 681b ldr r3, [r3, #0] 800bd50: 1ad3 subs r3, r2, r3 800bd52: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800bd56: d91a bls.n 800bd8e log_printf(LOG_ERR, "Everest timeout\n"); 800bd58: 4928 ldr r1, [pc, #160] @ (800bdfc ) 800bd5a: 2004 movs r0, #4 800bd5c: f7fe fb8e bl 800a47c everest_timed_out = 1; 800bd60: 4b24 ldr r3, [pc, #144] @ (800bdf4 ) 800bd62: 2201 movs r2, #1 800bd64: 701a strb r2, [r3, #0] last_host_seen = HAL_GetTick(); // reset after the first timeout 800bd66: f001 fdf9 bl 800d95c 800bd6a: 4603 mov r3, r0 800bd6c: 4a26 ldr r2, [pc, #152] @ (800be08 ) 800bd6e: 6013 str r3, [r2, #0] last_everest_timeout_log_tick = HAL_GetTick(); 800bd70: f001 fdf4 bl 800d95c 800bd74: 4603 mov r3, r0 800bd76: 4a20 ldr r2, [pc, #128] @ (800bdf8 ) 800bd78: 6013 str r3, [r2, #0] CONN.EnableOutput = 0; 800bd7a: 4b21 ldr r3, [pc, #132] @ (800be00 ) 800bd7c: 2200 movs r2, #0 800bd7e: 75da strb r2, [r3, #23] CCS_EvseState = Unknown; 800bd80: 4b20 ldr r3, [pc, #128] @ (800be04 ) 800bd82: 2200 movs r2, #0 800bd84: 701a strb r2, [r3, #0] CP_SetDuty(100); 800bd86: 2064 movs r0, #100 @ 0x64 800bd88: f7fe f9b4 bl 800a0f4 800bd8c: e01c b.n 800bdc8 } else { if (last_cmd == CMD_STOP) { 800bd8e: 4b1f ldr r3, [pc, #124] @ (800be0c ) 800bd90: 781b ldrb r3, [r3, #0] 800bd92: 2b01 cmp r3, #1 800bd94: d103 bne.n 800bd9e CONN.EnableOutput = 0; 800bd96: 4b1a ldr r3, [pc, #104] @ (800be00 ) 800bd98: 2200 movs r2, #0 800bd9a: 75da strb r2, [r3, #23] 800bd9c: e014 b.n 800bdc8 } else { CONN.EnableOutput = ev_enable_output ? 1 : 0; 800bd9e: 4b1c ldr r3, [pc, #112] @ (800be10 ) 800bda0: 781b ldrb r3, [r3, #0] 800bda2: 2b00 cmp r3, #0 800bda4: bf14 ite ne 800bda6: 2301 movne r3, #1 800bda8: 2300 moveq r3, #0 800bdaa: b2db uxtb r3, r3 800bdac: 461a mov r2, r3 800bdae: 4b14 ldr r3, [pc, #80] @ (800be00 ) 800bdb0: 75da strb r2, [r3, #23] if((CONN.EnableOutput == 0) && (CONN.connState == Preparing)){ 800bdb2: 4b13 ldr r3, [pc, #76] @ (800be00 ) 800bdb4: 7ddb ldrb r3, [r3, #23] 800bdb6: 2b00 cmp r3, #0 800bdb8: d106 bne.n 800bdc8 800bdba: 4b11 ldr r3, [pc, #68] @ (800be00 ) 800bdbc: 785b ldrb r3, [r3, #1] 800bdbe: 2b03 cmp r3, #3 800bdc0: d102 bne.n 800bdc8 CONN.EnableOutput = 0; 800bdc2: 4b0f ldr r3, [pc, #60] @ (800be00 ) 800bdc4: 2200 movs r2, #0 800bdc6: 75da strb r2, [r3, #23] } } } if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800bdc8: 4b12 ldr r3, [pc, #72] @ (800be14 ) 800bdca: 781b ldrb r3, [r3, #0] 800bdcc: 2b01 cmp r3, #1 800bdce: d007 beq.n 800bde0 (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800bdd0: 4b10 ldr r3, [pc, #64] @ (800be14 ) 800bdd2: 781b ldrb r3, [r3, #0] if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800bdd4: 2b02 cmp r3, #2 800bdd6: d003 beq.n 800bde0 (cp_state_buffer == EV_STATE_D_CONN_ACT_VENT)) { 800bdd8: 4b0e ldr r3, [pc, #56] @ (800be14 ) 800bdda: 781b ldrb r3, [r3, #0] (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800bddc: 2b03 cmp r3, #3 800bdde: d103 bne.n 800bde8 CONN.EvConnected = 1; 800bde0: 4b07 ldr r3, [pc, #28] @ (800be00 ) 800bde2: 2201 movs r2, #1 800bde4: 779a strb r2, [r3, #30] 800bde6: e003 b.n 800bdf0 } else { CONN.EvConnected = 0; 800bde8: 4b05 ldr r3, [pc, #20] @ (800be00 ) 800bdea: 2200 movs r2, #0 800bdec: 779a strb r2, [r3, #30] } } 800bdee: bf00 nop 800bdf0: bf00 nop 800bdf2: bd80 pop {r7, pc} 800bdf4: 200009d8 .word 0x200009d8 800bdf8: 200009dc .word 0x200009dc 800bdfc: 08014368 .word 0x08014368 800be00: 200001d4 .word 0x200001d4 800be04: 20000a2c .word 0x20000a2c 800be08: 200009d4 .word 0x200009d4 800be0c: 200007c8 .word 0x200007c8 800be10: 200007c9 .word 0x200007c9 800be14: 2000004f .word 0x2000004f 0800be18 : void CCS_Init(void){ 800be18: b580 push {r7, lr} 800be1a: af00 add r7, sp, #0 CP_Init(); 800be1c: f7fe f948 bl 800a0b0 CP_SetDuty(100); 800be20: 2064 movs r0, #100 @ 0x64 800be22: f7fe f967 bl 800a0f4 CCS_MaxLoad.maxVoltage = PSU_MAX_VOLTAGE; // 1000V 800be26: 4b0d ldr r3, [pc, #52] @ (800be5c ) 800be28: f44f 727a mov.w r2, #1000 @ 0x3e8 800be2c: 801a strh r2, [r3, #0] CCS_MaxLoad.minVoltage = PSU_MIN_VOLTAGE; //150V 800be2e: 4b0b ldr r3, [pc, #44] @ (800be5c ) 800be30: 2296 movs r2, #150 @ 0x96 800be32: 805a strh r2, [r3, #2] CCS_MaxLoad.maxCurrent = PSU_MAX_CURRENT*10; //100A 800be34: 4b09 ldr r3, [pc, #36] @ (800be5c ) 800be36: f240 5232 movw r2, #1330 @ 0x532 800be3a: 809a strh r2, [r3, #4] CCS_MaxLoad.minCurrent = PSU_MIN_CURRENT*10; //1A 800be3c: 4b07 ldr r3, [pc, #28] @ (800be5c ) 800be3e: 220a movs r2, #10 800be40: 80da strh r2, [r3, #6] CCS_MaxLoad.maxPower = PSU_MAX_POWER; //30000W 800be42: 4b06 ldr r3, [pc, #24] @ (800be5c ) 800be44: f247 5230 movw r2, #30000 @ 0x7530 800be48: 609a str r2, [r3, #8] CCS_SendResetReason(); 800be4a: f000 f8b3 bl 800bfb4 log_printf(LOG_INFO, "CCS init\n"); 800be4e: 4904 ldr r1, [pc, #16] @ (800be60 ) 800be50: 2007 movs r0, #7 800be52: f7fe fb13 bl 800a47c } 800be56: bf00 nop 800be58: bd80 pop {r7, pc} 800be5a: bf00 nop 800be5c: 200007a8 .word 0x200007a8 800be60: 0801437c .word 0x0801437c 0800be64 : static uint16_t crc16_ibm(const uint8_t* data, uint16_t length) { 800be64: b480 push {r7} 800be66: b085 sub sp, #20 800be68: af00 add r7, sp, #0 800be6a: 6078 str r0, [r7, #4] 800be6c: 460b mov r3, r1 800be6e: 807b strh r3, [r7, #2] uint16_t crc = 0xFFFFu; 800be70: f64f 73ff movw r3, #65535 @ 0xffff 800be74: 81fb strh r3, [r7, #14] for (uint16_t i = 0; i < length; i++) { 800be76: 2300 movs r3, #0 800be78: 81bb strh r3, [r7, #12] 800be7a: e022 b.n 800bec2 crc ^= data[i]; 800be7c: 89bb ldrh r3, [r7, #12] 800be7e: 687a ldr r2, [r7, #4] 800be80: 4413 add r3, r2 800be82: 781b ldrb r3, [r3, #0] 800be84: 461a mov r2, r3 800be86: 89fb ldrh r3, [r7, #14] 800be88: 4053 eors r3, r2 800be8a: 81fb strh r3, [r7, #14] for (uint8_t j = 0; j < 8; j++) { 800be8c: 2300 movs r3, #0 800be8e: 72fb strb r3, [r7, #11] 800be90: e011 b.n 800beb6 if (crc & 1u) { 800be92: 89fb ldrh r3, [r7, #14] 800be94: f003 0301 and.w r3, r3, #1 800be98: 2b00 cmp r3, #0 800be9a: d006 beq.n 800beaa crc = (crc >> 1) ^ 0xA001u; 800be9c: 89fb ldrh r3, [r7, #14] 800be9e: 085b lsrs r3, r3, #1 800bea0: b29a uxth r2, r3 800bea2: 4b0d ldr r3, [pc, #52] @ (800bed8 ) 800bea4: 4053 eors r3, r2 800bea6: 81fb strh r3, [r7, #14] 800bea8: e002 b.n 800beb0 } else { crc >>= 1; 800beaa: 89fb ldrh r3, [r7, #14] 800beac: 085b lsrs r3, r3, #1 800beae: 81fb strh r3, [r7, #14] for (uint8_t j = 0; j < 8; j++) { 800beb0: 7afb ldrb r3, [r7, #11] 800beb2: 3301 adds r3, #1 800beb4: 72fb strb r3, [r7, #11] 800beb6: 7afb ldrb r3, [r7, #11] 800beb8: 2b07 cmp r3, #7 800beba: d9ea bls.n 800be92 for (uint16_t i = 0; i < length; i++) { 800bebc: 89bb ldrh r3, [r7, #12] 800bebe: 3301 adds r3, #1 800bec0: 81bb strh r3, [r7, #12] 800bec2: 89ba ldrh r2, [r7, #12] 800bec4: 887b ldrh r3, [r7, #2] 800bec6: 429a cmp r2, r3 800bec8: d3d8 bcc.n 800be7c } } } return crc; 800beca: 89fb ldrh r3, [r7, #14] } 800becc: 4618 mov r0, r3 800bece: 3714 adds r7, #20 800bed0: 46bd mov sp, r7 800bed2: bc80 pop {r7} 800bed4: 4770 bx lr 800bed6: bf00 nop 800bed8: ffffa001 .word 0xffffa001 0800bedc : static uint16_t CCS_BuildPacket(uint8_t cmd, const void* payload, uint16_t payload_len, uint8_t* out, uint16_t out_max) { 800bedc: b580 push {r7, lr} 800bede: b086 sub sp, #24 800bee0: af00 add r7, sp, #0 800bee2: 60b9 str r1, [r7, #8] 800bee4: 607b str r3, [r7, #4] 800bee6: 4603 mov r3, r0 800bee8: 73fb strb r3, [r7, #15] 800beea: 4613 mov r3, r2 800beec: 81bb strh r3, [r7, #12] uint16_t total_len = (uint16_t)(1u + payload_len + 2u); 800beee: 89bb ldrh r3, [r7, #12] 800bef0: 3303 adds r3, #3 800bef2: 82fb strh r3, [r7, #22] if (total_len > out_max) return 0; 800bef4: 8afa ldrh r2, [r7, #22] 800bef6: 8c3b ldrh r3, [r7, #32] 800bef8: 429a cmp r2, r3 800befa: d901 bls.n 800bf00 800befc: 2300 movs r3, #0 800befe: e029 b.n 800bf54 out[0] = cmd; 800bf00: 687b ldr r3, [r7, #4] 800bf02: 7bfa ldrb r2, [r7, #15] 800bf04: 701a strb r2, [r3, #0] if (payload_len && payload != NULL) { 800bf06: 89bb ldrh r3, [r7, #12] 800bf08: 2b00 cmp r3, #0 800bf0a: d009 beq.n 800bf20 800bf0c: 68bb ldr r3, [r7, #8] 800bf0e: 2b00 cmp r3, #0 800bf10: d006 beq.n 800bf20 memcpy(&out[1], payload, payload_len); 800bf12: 687b ldr r3, [r7, #4] 800bf14: 3301 adds r3, #1 800bf16: 89ba ldrh r2, [r7, #12] 800bf18: 68b9 ldr r1, [r7, #8] 800bf1a: 4618 mov r0, r3 800bf1c: f007 f90b bl 8013136 } uint16_t crc = crc16_ibm(out, (uint16_t)(1u + payload_len)); 800bf20: 89bb ldrh r3, [r7, #12] 800bf22: 3301 adds r3, #1 800bf24: b29b uxth r3, r3 800bf26: 4619 mov r1, r3 800bf28: 6878 ldr r0, [r7, #4] 800bf2a: f7ff ff9b bl 800be64 800bf2e: 4603 mov r3, r0 800bf30: 82bb strh r3, [r7, #20] out[1u + payload_len] = (uint8_t)(crc & 0xFFu); 800bf32: 89bb ldrh r3, [r7, #12] 800bf34: 3301 adds r3, #1 800bf36: 687a ldr r2, [r7, #4] 800bf38: 4413 add r3, r2 800bf3a: 8aba ldrh r2, [r7, #20] 800bf3c: b2d2 uxtb r2, r2 800bf3e: 701a strb r2, [r3, #0] out[1u + payload_len + 1u] = (uint8_t)((crc >> 8) & 0xFFu); 800bf40: 8abb ldrh r3, [r7, #20] 800bf42: 0a1b lsrs r3, r3, #8 800bf44: b299 uxth r1, r3 800bf46: 89bb ldrh r3, [r7, #12] 800bf48: 3302 adds r3, #2 800bf4a: 687a ldr r2, [r7, #4] 800bf4c: 4413 add r3, r2 800bf4e: b2ca uxtb r2, r1 800bf50: 701a strb r2, [r3, #0] return total_len; 800bf52: 8afb ldrh r3, [r7, #22] } 800bf54: 4618 mov r0, r3 800bf56: 3718 adds r7, #24 800bf58: 46bd mov sp, r7 800bf5a: bd80 pop {r7, pc} 0800bf5c : static void CCS_SendPacket(uint8_t cmd, const void* payload, uint16_t payload_len) { 800bf5c: b580 push {r7, lr} 800bf5e: b086 sub sp, #24 800bf60: af02 add r7, sp, #8 800bf62: 4603 mov r3, r0 800bf64: 6039 str r1, [r7, #0] 800bf66: 71fb strb r3, [r7, #7] 800bf68: 4613 mov r3, r2 800bf6a: 80bb strh r3, [r7, #4] uint16_t len = CCS_BuildPacket(cmd, payload, payload_len, tx_buffer, sizeof(tx_buffer)); 800bf6c: 88ba ldrh r2, [r7, #4] 800bf6e: 79f8 ldrb r0, [r7, #7] 800bf70: f44f 7380 mov.w r3, #256 @ 0x100 800bf74: 9300 str r3, [sp, #0] 800bf76: 4b0c ldr r3, [pc, #48] @ (800bfa8 ) 800bf78: 6839 ldr r1, [r7, #0] 800bf7a: f7ff ffaf bl 800bedc 800bf7e: 4603 mov r3, r0 800bf80: 81fb strh r3, [r7, #14] if (len > 0) { 800bf82: 89fb ldrh r3, [r7, #14] 800bf84: 2b00 cmp r3, #0 800bf86: d006 beq.n 800bf96 HAL_UART_Transmit(&huart3, tx_buffer, len, 1000); 800bf88: 89fa ldrh r2, [r7, #14] 800bf8a: f44f 737a mov.w r3, #1000 @ 0x3e8 800bf8e: 4906 ldr r1, [pc, #24] @ (800bfa8 ) 800bf90: 4806 ldr r0, [pc, #24] @ (800bfac ) 800bf92: f005 fee9 bl 8011d68 } last_cmd_sent = HAL_GetTick(); 800bf96: f001 fce1 bl 800d95c 800bf9a: 4603 mov r3, r0 800bf9c: 4a04 ldr r2, [pc, #16] @ (800bfb0 ) 800bf9e: 6013 str r3, [r2, #0] } 800bfa0: bf00 nop 800bfa2: 3710 adds r7, #16 800bfa4: 46bd mov sp, r7 800bfa6: bd80 pop {r7, pc} 800bfa8: 200008cc .word 0x200008cc 800bfac: 20001030 .word 0x20001030 800bfb0: 200007c0 .word 0x200007c0 0800bfb4 : static void CCS_SendResetReason(void) { 800bfb4: b580 push {r7, lr} 800bfb6: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_RESET, NULL, 0); 800bfb8: 2200 movs r2, #0 800bfba: 2100 movs r1, #0 800bfbc: 2052 movs r0, #82 @ 0x52 800bfbe: f7ff ffcd bl 800bf5c } 800bfc2: bf00 nop 800bfc4: bd80 pop {r7, pc} 0800bfc6 : void CCS_SendEmergencyStop(void) { 800bfc6: b580 push {r7, lr} 800bfc8: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_ESTOP, NULL, 0); 800bfca: 2200 movs r2, #0 800bfcc: 2100 movs r1, #0 800bfce: 2053 movs r0, #83 @ 0x53 800bfd0: f7ff ffc4 bl 800bf5c } 800bfd4: bf00 nop 800bfd6: bd80 pop {r7, pc} 0800bfd8 : void CCS_SendStart(void) { CCS_SendPacket(CMD_M2E_START, NULL, 0); } static void CCS_CalculateEnergy(void) { 800bfd8: b580 push {r7, lr} 800bfda: b082 sub sp, #8 800bfdc: af00 add r7, sp, #0 static uint32_t lastTick = 0; uint32_t currentTick = HAL_GetTick(); 800bfde: f001 fcbd bl 800d95c 800bfe2: 6078 str r0, [r7, #4] uint32_t elapsedTimeMs = currentTick - lastTick; 800bfe4: 4b1e ldr r3, [pc, #120] @ (800c060 ) 800bfe6: 681b ldr r3, [r3, #0] 800bfe8: 687a ldr r2, [r7, #4] 800bfea: 1ad3 subs r3, r2, r3 800bfec: 603b str r3, [r7, #0] lastTick = currentTick; 800bfee: 4a1c ldr r2, [pc, #112] @ (800c060 ) 800bff0: 687b ldr r3, [r7, #4] 800bff2: 6013 str r3, [r2, #0] CCS_Power = CONN.MeasuredVoltage * CONN.MeasuredCurrent / 10; 800bff4: 4b1b ldr r3, [pc, #108] @ (800c064 ) 800bff6: f8b3 3013 ldrh.w r3, [r3, #19] 800bffa: b29b uxth r3, r3 800bffc: 461a mov r2, r3 800bffe: 4b19 ldr r3, [pc, #100] @ (800c064 ) 800c000: f8b3 3015 ldrh.w r3, [r3, #21] 800c004: b29b uxth r3, r3 800c006: fb02 f303 mul.w r3, r2, r3 800c00a: 4a17 ldr r2, [pc, #92] @ (800c068 ) 800c00c: fb82 1203 smull r1, r2, r2, r3 800c010: 1092 asrs r2, r2, #2 800c012: 17db asrs r3, r3, #31 800c014: 1ad3 subs r3, r2, r3 800c016: 461a mov r2, r3 800c018: 4b14 ldr r3, [pc, #80] @ (800c06c ) 800c01a: 601a str r2, [r3, #0] CCS_EnergyWs += (CCS_Power * elapsedTimeMs) / 1000; 800c01c: 4b13 ldr r3, [pc, #76] @ (800c06c ) 800c01e: 681b ldr r3, [r3, #0] 800c020: 683a ldr r2, [r7, #0] 800c022: fb02 f303 mul.w r3, r2, r3 800c026: 4a12 ldr r2, [pc, #72] @ (800c070 ) 800c028: fba2 2303 umull r2, r3, r2, r3 800c02c: 099a lsrs r2, r3, #6 800c02e: 4b11 ldr r3, [pc, #68] @ (800c074 ) 800c030: 681b ldr r3, [r3, #0] 800c032: 4413 add r3, r2 800c034: 4a0f ldr r2, [pc, #60] @ (800c074 ) 800c036: 6013 str r3, [r2, #0] if(CCS_EvseState == Unplugged) { 800c038: 4b0f ldr r3, [pc, #60] @ (800c078 ) 800c03a: 781b ldrb r3, [r3, #0] 800c03c: 2b01 cmp r3, #1 800c03e: d102 bne.n 800c046 CCS_EnergyWs = 0; 800c040: 4b0c ldr r3, [pc, #48] @ (800c074 ) 800c042: 2200 movs r2, #0 800c044: 601a str r2, [r3, #0] } CCS_Energy = CCS_EnergyWs / 3600; 800c046: 4b0b ldr r3, [pc, #44] @ (800c074 ) 800c048: 681b ldr r3, [r3, #0] 800c04a: 4a0c ldr r2, [pc, #48] @ (800c07c ) 800c04c: fba2 2303 umull r2, r3, r2, r3 800c050: 0adb lsrs r3, r3, #11 800c052: 4a0b ldr r2, [pc, #44] @ (800c080 ) 800c054: 6013 str r3, [r2, #0] } 800c056: bf00 nop 800c058: 3708 adds r7, #8 800c05a: 46bd mov sp, r7 800c05c: bd80 pop {r7, pc} 800c05e: bf00 nop 800c060: 20000a38 .word 0x20000a38 800c064: 200001d4 .word 0x200001d4 800c068: 66666667 .word 0x66666667 800c06c: 200007b4 .word 0x200007b4 800c070: 10624dd3 .word 0x10624dd3 800c074: 200007b8 .word 0x200007b8 800c078: 20000a2c .word 0x20000a2c 800c07c: 91a2b3c5 .word 0x91a2b3c5 800c080: 200007bc .word 0x200007bc 0800c084 : static void send_state(void) { 800c084: b580 push {r7, lr} 800c086: af00 add r7, sp, #0 CCS_CalculateEnergy(); 800c088: f7ff ffa6 bl 800bfd8 CCS_State.DutyCycle = CP_GetDuty(); 800c08c: f7fe f85a bl 800a144 800c090: 4603 mov r3, r0 800c092: 461a mov r2, r3 800c094: 4b2a ldr r3, [pc, #168] @ (800c140 ) 800c096: 701a strb r2, [r3, #0] CCS_State.OutputEnabled = PSU0.CONT_enabled; 800c098: 4b2a ldr r3, [pc, #168] @ (800c144 ) 800c09a: 7ada ldrb r2, [r3, #11] 800c09c: 4b28 ldr r3, [pc, #160] @ (800c140 ) 800c09e: 705a strb r2, [r3, #1] CCS_State.MeasuredVoltage = (uint16_t)CONN.MeasuredVoltage; 800c0a0: 4b29 ldr r3, [pc, #164] @ (800c148 ) 800c0a2: f8b3 3013 ldrh.w r3, [r3, #19] 800c0a6: b29a uxth r2, r3 800c0a8: 4b25 ldr r3, [pc, #148] @ (800c140 ) 800c0aa: 805a strh r2, [r3, #2] CCS_State.MeasuredCurrent = (uint16_t)CONN.MeasuredCurrent; 800c0ac: 4b26 ldr r3, [pc, #152] @ (800c148 ) 800c0ae: f8b3 3015 ldrh.w r3, [r3, #21] 800c0b2: b29a uxth r2, r3 800c0b4: 4b22 ldr r3, [pc, #136] @ (800c140 ) 800c0b6: 809a strh r2, [r3, #4] CCS_State.Power = CCS_Power; 800c0b8: 4b24 ldr r3, [pc, #144] @ (800c14c ) 800c0ba: 681b ldr r3, [r3, #0] 800c0bc: 4a20 ldr r2, [pc, #128] @ (800c140 ) 800c0be: f8c2 3006 str.w r3, [r2, #6] CCS_State.Energy = CCS_Energy; 800c0c2: 4b23 ldr r3, [pc, #140] @ (800c150 ) 800c0c4: 681b ldr r3, [r3, #0] 800c0c6: 4a1e ldr r2, [pc, #120] @ (800c140 ) 800c0c8: f8c2 300a str.w r3, [r2, #10] if(CCS_ConnectorState == CCS_CONNECTED){ 800c0cc: 4b21 ldr r3, [pc, #132] @ (800c154 ) 800c0ce: 781b ldrb r3, [r3, #0] 800c0d0: 2b03 cmp r3, #3 800c0d2: d104 bne.n 800c0de CCS_State.CpState = cp_state_buffer; 800c0d4: 4b20 ldr r3, [pc, #128] @ (800c158 ) 800c0d6: 781a ldrb r2, [r3, #0] 800c0d8: 4b19 ldr r3, [pc, #100] @ (800c140 ) 800c0da: 74da strb r2, [r3, #19] 800c0dc: e002 b.n 800c0e4 } else { CCS_State.CpState = EV_STATE_A_IDLE; 800c0de: 4b18 ldr r3, [pc, #96] @ (800c140 ) 800c0e0: 2200 movs r2, #0 800c0e2: 74da strb r2, [r3, #19] } CCS_State.MaxVoltage = CCS_MaxLoad.maxVoltage; 800c0e4: 4b1d ldr r3, [pc, #116] @ (800c15c ) 800c0e6: 881a ldrh r2, [r3, #0] 800c0e8: 4b15 ldr r3, [pc, #84] @ (800c140 ) 800c0ea: 829a strh r2, [r3, #20] CCS_State.MinVoltage = CCS_MaxLoad.minVoltage; 800c0ec: 4b1b ldr r3, [pc, #108] @ (800c15c ) 800c0ee: 885a ldrh r2, [r3, #2] 800c0f0: 4b13 ldr r3, [pc, #76] @ (800c140 ) 800c0f2: 82da strh r2, [r3, #22] CCS_State.MaxCurrent = CCS_MaxLoad.maxCurrent; 800c0f4: 4b19 ldr r3, [pc, #100] @ (800c15c ) 800c0f6: 889a ldrh r2, [r3, #4] 800c0f8: 4b11 ldr r3, [pc, #68] @ (800c140 ) 800c0fa: 831a strh r2, [r3, #24] CCS_State.MinCurrent = CCS_MaxLoad.minCurrent; 800c0fc: 4b17 ldr r3, [pc, #92] @ (800c15c ) 800c0fe: 88da ldrh r2, [r3, #6] 800c100: 4b0f ldr r3, [pc, #60] @ (800c140 ) 800c102: 835a strh r2, [r3, #26] CCS_State.MaxPower = CCS_MaxLoad.maxPower; 800c104: 4b15 ldr r3, [pc, #84] @ (800c15c ) 800c106: 689b ldr r3, [r3, #8] 800c108: 4a0d ldr r2, [pc, #52] @ (800c140 ) 800c10a: 61d3 str r3, [r2, #28] CCS_State.IsolationValid = isolation_enable; 800c10c: 4b14 ldr r3, [pc, #80] @ (800c160 ) 800c10e: 781a ldrb r2, [r3, #0] 800c110: 4b0b ldr r3, [pc, #44] @ (800c140 ) 800c112: 749a strb r2, [r3, #18] CCS_State.IsolationResistance = 900000; 800c114: 4a0a ldr r2, [pc, #40] @ (800c140 ) 800c116: 2300 movs r3, #0 800c118: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800c11c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800c120: f443 433b orr.w r3, r3, #47872 @ 0xbb00 800c124: f043 03a0 orr.w r3, r3, #160 @ 0xa0 800c128: 81d3 strh r3, [r2, #14] 800c12a: 2300 movs r3, #0 800c12c: f043 030d orr.w r3, r3, #13 800c130: 8213 strh r3, [r2, #16] CCS_SendPacket(CMD_M2E_STATE, &CCS_State, sizeof(CCS_State)); 800c132: 2220 movs r2, #32 800c134: 4902 ldr r1, [pc, #8] @ (800c140 ) 800c136: 2050 movs r0, #80 @ 0x50 800c138: f7ff ff10 bl 800bf5c } 800c13c: bf00 nop 800c13e: bd80 pop {r7, pc} 800c140: 200009e0 .word 0x200009e0 800c144: 20000724 .word 0x20000724 800c148: 200001d4 .word 0x200001d4 800c14c: 200007b4 .word 0x200007b4 800c150: 200007bc .word 0x200007bc 800c154: 20000050 .word 0x20000050 800c158: 2000004f .word 0x2000004f 800c15c: 200007a8 .word 0x200007a8 800c160: 200009d0 .word 0x200009d0 0800c164 : static uint16_t expected_payload_len(uint8_t cmd) { 800c164: b480 push {r7} 800c166: b083 sub sp, #12 800c168: af00 add r7, sp, #0 800c16a: 4603 mov r3, r0 800c16c: 71fb strb r3, [r7, #7] switch (cmd) { 800c16e: 79fb ldrb r3, [r7, #7] 800c170: 3b40 subs r3, #64 @ 0x40 800c172: 2b09 cmp r3, #9 800c174: d82a bhi.n 800c1cc 800c176: a201 add r2, pc, #4 @ (adr r2, 800c17c ) 800c178: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c17c: 0800c1a5 .word 0x0800c1a5 800c180: 0800c1a9 .word 0x0800c1a9 800c184: 0800c1ad .word 0x0800c1ad 800c188: 0800c1b1 .word 0x0800c1b1 800c18c: 0800c1b5 .word 0x0800c1b5 800c190: 0800c1b9 .word 0x0800c1b9 800c194: 0800c1bd .word 0x0800c1bd 800c198: 0800c1c1 .word 0x0800c1c1 800c19c: 0800c1c5 .word 0x0800c1c5 800c1a0: 0800c1c9 .word 0x0800c1c9 case CMD_E2M_PWM_DUTY: return sizeof(e2m_pwm_duty_t); 800c1a4: 2301 movs r3, #1 800c1a6: e013 b.n 800c1d0 case CMD_E2M_ENABLE_OUTPUT: return sizeof(e2m_enable_output_t); 800c1a8: 2301 movs r3, #1 800c1aa: e011 b.n 800c1d0 case CMD_E2M_RESET: return sizeof(e2m_reset_t); 800c1ac: 2301 movs r3, #1 800c1ae: e00f b.n 800c1d0 case CMD_E2M_ENABLE: return sizeof(e2m_enable_t); 800c1b0: 2301 movs r3, #1 800c1b2: e00d b.n 800c1d0 case CMD_E2M_REPLUG: return sizeof(e2m_replug_t); 800c1b4: 2301 movs r3, #1 800c1b6: e00b b.n 800c1d0 case CMD_E2M_SET_OUTPUT_VOLTAGE: return sizeof(e2m_set_output_t); 800c1b8: 2304 movs r3, #4 800c1ba: e009 b.n 800c1d0 case CMD_E2M_ISOLATION_CONTROL: return sizeof(e2m_isolation_control_t); 800c1bc: 2301 movs r3, #1 800c1be: e007 b.n 800c1d0 case CMD_E2M_EV_INFO: return sizeof(CCS_EvInfo_t); 800c1c0: 232c movs r3, #44 @ 0x2c 800c1c2: e005 b.n 800c1d0 case CMD_E2M_EVSE_STATE: return sizeof(CONN_State_t); 800c1c4: 2301 movs r3, #1 800c1c6: e003 b.n 800c1d0 case CMD_E2M_KEEP_ALIVE: return 0; 800c1c8: 2300 movs r3, #0 800c1ca: e001 b.n 800c1d0 default: return 0xFFFFu; 800c1cc: f64f 73ff movw r3, #65535 @ 0xffff } } 800c1d0: 4618 mov r0, r3 800c1d2: 370c adds r7, #12 800c1d4: 46bd mov sp, r7 800c1d6: bc80 pop {r7} 800c1d8: 4770 bx lr 800c1da: bf00 nop 0800c1dc : static void apply_command(uint8_t cmd, const uint8_t* payload, uint16_t payload_len) { 800c1dc: b5f0 push {r4, r5, r6, r7, lr} 800c1de: b08b sub sp, #44 @ 0x2c 800c1e0: af00 add r7, sp, #0 800c1e2: 4603 mov r3, r0 800c1e4: 6039 str r1, [r7, #0] 800c1e6: 71fb strb r3, [r7, #7] 800c1e8: 4613 mov r3, r2 800c1ea: 80bb strh r3, [r7, #4] (void)payload_len; last_host_seen = HAL_GetTick(); 800c1ec: f001 fbb6 bl 800d95c 800c1f0: 4603 mov r3, r0 800c1f2: 4a5b ldr r2, [pc, #364] @ (800c360 ) 800c1f4: 6013 str r3, [r2, #0] everest_timed_out = 0; 800c1f6: 4b5b ldr r3, [pc, #364] @ (800c364 ) 800c1f8: 2200 movs r2, #0 800c1fa: 701a strb r2, [r3, #0] last_everest_timeout_log_tick = 0; 800c1fc: 4b5a ldr r3, [pc, #360] @ (800c368 ) 800c1fe: 2200 movs r2, #0 800c200: 601a str r2, [r3, #0] switch (cmd) { 800c202: 79fb ldrb r3, [r7, #7] 800c204: 3b40 subs r3, #64 @ 0x40 800c206: 2b09 cmp r3, #9 800c208: f200 80a3 bhi.w 800c352 800c20c: a201 add r2, pc, #4 @ (adr r2, 800c214 ) 800c20e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c212: bf00 nop 800c214: 0800c23d .word 0x0800c23d 800c218: 0800c26b .word 0x0800c26b 800c21c: 0800c285 .word 0x0800c285 800c220: 0800c2a7 .word 0x0800c2a7 800c224: 0800c33b .word 0x0800c33b 800c228: 0800c2c1 .word 0x0800c2c1 800c22c: 0800c2df .word 0x0800c2df 800c230: 0800c2ed .word 0x0800c2ed 800c234: 0800c331 .word 0x0800c331 800c238: 0800c347 .word 0x0800c347 case CMD_E2M_PWM_DUTY: { const e2m_pwm_duty_t* p = (const e2m_pwm_duty_t*)payload; 800c23c: 683b ldr r3, [r7, #0] 800c23e: 60fb str r3, [r7, #12] uint8_t duty = p->pwm_duty_percent; 800c240: 68fb ldr r3, [r7, #12] 800c242: 781b ldrb r3, [r3, #0] 800c244: f887 3027 strb.w r3, [r7, #39] @ 0x27 if (duty > 100) duty = 100; 800c248: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 800c24c: 2b64 cmp r3, #100 @ 0x64 800c24e: d902 bls.n 800c256 800c250: 2364 movs r3, #100 @ 0x64 800c252: f887 3027 strb.w r3, [r7, #39] @ 0x27 pwm_duty_percent = duty; 800c256: 4a45 ldr r2, [pc, #276] @ (800c36c ) 800c258: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 800c25c: 7013 strb r3, [r2, #0] CP_SetDuty(duty); 800c25e: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 800c262: 4618 mov r0, r3 800c264: f7fd ff46 bl 800a0f4 break; 800c268: e076 b.n 800c358 } case CMD_E2M_ENABLE_OUTPUT: { const e2m_enable_output_t* p = (const e2m_enable_output_t*)payload; 800c26a: 683b ldr r3, [r7, #0] 800c26c: 613b str r3, [r7, #16] ev_enable_output = (p->enable_output != 0); 800c26e: 693b ldr r3, [r7, #16] 800c270: 781b ldrb r3, [r3, #0] 800c272: 2b00 cmp r3, #0 800c274: bf14 ite ne 800c276: 2301 movne r3, #1 800c278: 2300 moveq r3, #0 800c27a: b2db uxtb r3, r3 800c27c: 461a mov r2, r3 800c27e: 4b3c ldr r3, [pc, #240] @ (800c370 ) 800c280: 701a strb r2, [r3, #0] break; 800c282: e069 b.n 800c358 } case CMD_E2M_RESET: { const e2m_reset_t* p = (const e2m_reset_t*)payload; 800c284: 683b ldr r3, [r7, #0] 800c286: 617b str r3, [r7, #20] if (p->reset) { 800c288: 697b ldr r3, [r7, #20] 800c28a: 781b ldrb r3, [r3, #0] 800c28c: 2b00 cmp r3, #0 800c28e: d062 beq.n 800c356 log_printf(LOG_WARN, "Everest reset command\n"); 800c290: 4938 ldr r1, [pc, #224] @ (800c374 ) 800c292: 2005 movs r0, #5 800c294: f7fe f8f2 bl 800a47c CCS_SendResetReason(); 800c298: f7ff fe8c bl 800bfb4 HAL_Delay(10); 800c29c: 200a movs r0, #10 800c29e: f001 fb67 bl 800d970 NVIC_SystemReset(); 800c2a2: f7ff fb6f bl 800b984 <__NVIC_SystemReset> } break; } case CMD_E2M_ENABLE: { const e2m_enable_t* p = (const e2m_enable_t*)payload; 800c2a6: 683b ldr r3, [r7, #0] 800c2a8: 61bb str r3, [r7, #24] enabled = (p->enable != 0); 800c2aa: 69bb ldr r3, [r7, #24] 800c2ac: 781b ldrb r3, [r3, #0] 800c2ae: 2b00 cmp r3, #0 800c2b0: bf14 ite ne 800c2b2: 2301 movne r3, #1 800c2b4: 2300 moveq r3, #0 800c2b6: b2db uxtb r3, r3 800c2b8: 461a mov r2, r3 800c2ba: 4b2f ldr r3, [pc, #188] @ (800c378 ) 800c2bc: 701a strb r2, [r3, #0] (void)enabled; break; 800c2be: e04b b.n 800c358 } case CMD_E2M_SET_OUTPUT_VOLTAGE: { const e2m_set_output_t* p = (const e2m_set_output_t*)payload; 800c2c0: 683b ldr r3, [r7, #0] 800c2c2: 61fb str r3, [r7, #28] CONN.RequestedVoltage = p->voltage_V; 800c2c4: 69fb ldr r3, [r7, #28] 800c2c6: 881b ldrh r3, [r3, #0] 800c2c8: b29a uxth r2, r3 800c2ca: 4b2c ldr r3, [pc, #176] @ (800c37c ) 800c2cc: f8a3 200f strh.w r2, [r3, #15] CONN.WantedCurrent = p->current_0p1A; 800c2d0: 69fb ldr r3, [r7, #28] 800c2d2: 885b ldrh r3, [r3, #2] 800c2d4: b29a uxth r2, r3 800c2d6: 4b29 ldr r3, [pc, #164] @ (800c37c ) 800c2d8: f8a3 201b strh.w r2, [r3, #27] break; 800c2dc: e03c b.n 800c358 } case CMD_E2M_ISOLATION_CONTROL: { const e2m_isolation_control_t* p = (const e2m_isolation_control_t*)payload; 800c2de: 683b ldr r3, [r7, #0] 800c2e0: 623b str r3, [r7, #32] isolation_enable = p->command; 800c2e2: 6a3b ldr r3, [r7, #32] 800c2e4: 781a ldrb r2, [r3, #0] 800c2e6: 4b26 ldr r3, [pc, #152] @ (800c380 ) 800c2e8: 701a strb r2, [r3, #0] break; 800c2ea: e035 b.n 800c358 } case CMD_E2M_EV_INFO: { memcpy(&CCS_EvInfo, payload, sizeof(CCS_EvInfo_t)); 800c2ec: 4a25 ldr r2, [pc, #148] @ (800c384 ) 800c2ee: 683b ldr r3, [r7, #0] 800c2f0: 461c mov r4, r3 800c2f2: 4616 mov r6, r2 800c2f4: f104 0c20 add.w ip, r4, #32 800c2f8: 4635 mov r5, r6 800c2fa: 4623 mov r3, r4 800c2fc: 6818 ldr r0, [r3, #0] 800c2fe: 6859 ldr r1, [r3, #4] 800c300: 689a ldr r2, [r3, #8] 800c302: 68db ldr r3, [r3, #12] 800c304: c50f stmia r5!, {r0, r1, r2, r3} 800c306: 3410 adds r4, #16 800c308: 3610 adds r6, #16 800c30a: 4564 cmp r4, ip 800c30c: d1f4 bne.n 800c2f8 800c30e: 4633 mov r3, r6 800c310: 4622 mov r2, r4 800c312: 6810 ldr r0, [r2, #0] 800c314: 6851 ldr r1, [r2, #4] 800c316: 6892 ldr r2, [r2, #8] 800c318: c307 stmia r3!, {r0, r1, r2} CONN.SOC = (uint8_t)(CCS_EvInfo.soc / 10); 800c31a: 4b1a ldr r3, [pc, #104] @ (800c384 ) 800c31c: 885b ldrh r3, [r3, #2] 800c31e: 4a1a ldr r2, [pc, #104] @ (800c388 ) 800c320: fba2 2303 umull r2, r3, r2, r3 800c324: 08db lsrs r3, r3, #3 800c326: b29b uxth r3, r3 800c328: b2da uxtb r2, r3 800c32a: 4b14 ldr r3, [pc, #80] @ (800c37c ) 800c32c: 709a strb r2, [r3, #2] break; 800c32e: e013 b.n 800c358 } case CMD_E2M_EVSE_STATE: { CCS_EvseState = (CONN_State_t)payload[0]; 800c330: 683b ldr r3, [r7, #0] 800c332: 781a ldrb r2, [r3, #0] 800c334: 4b15 ldr r3, [pc, #84] @ (800c38c ) 800c336: 701a strb r2, [r3, #0] break; 800c338: e00e b.n 800c358 } case CMD_E2M_REPLUG: { (void)payload; CP_SetDuty(pwm_duty_percent); 800c33a: 4b0c ldr r3, [pc, #48] @ (800c36c ) 800c33c: 781b ldrb r3, [r3, #0] 800c33e: 4618 mov r0, r3 800c340: f7fd fed8 bl 800a0f4 break; 800c344: e008 b.n 800c358 } case CMD_E2M_KEEP_ALIVE: { last_host_seen = HAL_GetTick(); 800c346: f001 fb09 bl 800d95c 800c34a: 4603 mov r3, r0 800c34c: 4a04 ldr r2, [pc, #16] @ (800c360 ) 800c34e: 6013 str r3, [r2, #0] break; 800c350: e002 b.n 800c358 } default: break; 800c352: bf00 nop 800c354: e000 b.n 800c358 break; 800c356: bf00 nop } } 800c358: bf00 nop 800c35a: 372c adds r7, #44 @ 0x2c 800c35c: 46bd mov sp, r7 800c35e: bdf0 pop {r4, r5, r6, r7, pc} 800c360: 200009d4 .word 0x200009d4 800c364: 200009d8 .word 0x200009d8 800c368: 200009dc .word 0x200009dc 800c36c: 2000004e .word 0x2000004e 800c370: 200007c9 .word 0x200007c9 800c374: 08014388 .word 0x08014388 800c378: 200009cf .word 0x200009cf 800c37c: 200001d4 .word 0x200001d4 800c380: 200009d0 .word 0x200009d0 800c384: 20000a00 .word 0x20000a00 800c388: cccccccd .word 0xcccccccd 800c38c: 20000a2c .word 0x20000a2c 0800c390 : static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len) { 800c390: b580 push {r7, lr} 800c392: b086 sub sp, #24 800c394: af00 add r7, sp, #0 800c396: 6078 str r0, [r7, #4] 800c398: 460b mov r3, r1 800c39a: 807b strh r3, [r7, #2] if (packet_len < 3) return 0; 800c39c: 887b ldrh r3, [r7, #2] 800c39e: 2b02 cmp r3, #2 800c3a0: d801 bhi.n 800c3a6 800c3a2: 2300 movs r3, #0 800c3a4: e05a b.n 800c45c uint8_t cmd = packet[0]; 800c3a6: 687b ldr r3, [r7, #4] 800c3a8: 781b ldrb r3, [r3, #0] 800c3aa: 75fb strb r3, [r7, #23] uint16_t payload_len = (uint16_t)(packet_len - 3); 800c3ac: 887b ldrh r3, [r7, #2] 800c3ae: 3b03 subs r3, #3 800c3b0: 82bb strh r3, [r7, #20] uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c3b2: 887b ldrh r3, [r7, #2] 800c3b4: 3b02 subs r3, #2 800c3b6: 687a ldr r2, [r7, #4] 800c3b8: 4413 add r3, r2 800c3ba: 781b ldrb r3, [r3, #0] 800c3bc: b21a sxth r2, r3 (uint16_t)packet[packet_len - 1u] << 8; 800c3be: 887b ldrh r3, [r7, #2] 800c3c0: 3b01 subs r3, #1 800c3c2: 6879 ldr r1, [r7, #4] 800c3c4: 440b add r3, r1 800c3c6: 781b ldrb r3, [r3, #0] uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c3c8: b21b sxth r3, r3 800c3ca: 021b lsls r3, r3, #8 800c3cc: b21b sxth r3, r3 800c3ce: 4313 orrs r3, r2 800c3d0: b21b sxth r3, r3 800c3d2: 827b strh r3, [r7, #18] uint16_t calculated_crc = crc16_ibm(packet, (uint16_t)(1 + payload_len)); 800c3d4: 8abb ldrh r3, [r7, #20] 800c3d6: 3301 adds r3, #1 800c3d8: b29b uxth r3, r3 800c3da: 4619 mov r1, r3 800c3dc: 6878 ldr r0, [r7, #4] 800c3de: f7ff fd41 bl 800be64 800c3e2: 4603 mov r3, r0 800c3e4: 823b strh r3, [r7, #16] if (received_crc != calculated_crc) { 800c3e6: 8a7a ldrh r2, [r7, #18] 800c3e8: 8a3b ldrh r3, [r7, #16] 800c3ea: 429a cmp r2, r3 800c3ec: d005 beq.n 800c3fa log_printf(LOG_ERR, "Packet CRC error\n"); 800c3ee: 491d ldr r1, [pc, #116] @ (800c464 ) 800c3f0: 2004 movs r0, #4 800c3f2: f7fe f843 bl 800a47c return 0; 800c3f6: 2300 movs r3, #0 800c3f8: e030 b.n 800c45c } uint16_t expected_len = expected_payload_len(cmd); 800c3fa: 7dfb ldrb r3, [r7, #23] 800c3fc: 4618 mov r0, r3 800c3fe: f7ff feb1 bl 800c164 800c402: 4603 mov r3, r0 800c404: 81fb strh r3, [r7, #14] if (expected_len == 0xFFFF) { 800c406: 89fb ldrh r3, [r7, #14] 800c408: f64f 72ff movw r2, #65535 @ 0xffff 800c40c: 4293 cmp r3, r2 800c40e: d107 bne.n 800c420 log_printf(LOG_WARN, "Unknown cmd 0x%02x\n", cmd); 800c410: 7dfb ldrb r3, [r7, #23] 800c412: 461a mov r2, r3 800c414: 4914 ldr r1, [pc, #80] @ (800c468 ) 800c416: 2005 movs r0, #5 800c418: f7fe f830 bl 800a47c return 0; 800c41c: 2300 movs r3, #0 800c41e: e01d b.n 800c45c } if (expected_len != payload_len) { 800c420: 89fa ldrh r2, [r7, #14] 800c422: 8abb ldrh r3, [r7, #20] 800c424: 429a cmp r2, r3 800c426: d007 beq.n 800c438 log_printf(LOG_ERR, "Packet len mismatch cmd=0x%02x\n", cmd); 800c428: 7dfb ldrb r3, [r7, #23] 800c42a: 461a mov r2, r3 800c42c: 490f ldr r1, [pc, #60] @ (800c46c ) 800c42e: 2004 movs r0, #4 800c430: f7fe f824 bl 800a47c return 0; 800c434: 2300 movs r3, #0 800c436: e011 b.n 800c45c } if (payload_len > 0) { 800c438: 8abb ldrh r3, [r7, #20] 800c43a: 2b00 cmp r3, #0 800c43c: d007 beq.n 800c44e apply_command(cmd, &packet[1], payload_len); 800c43e: 687b ldr r3, [r7, #4] 800c440: 1c59 adds r1, r3, #1 800c442: 8aba ldrh r2, [r7, #20] 800c444: 7dfb ldrb r3, [r7, #23] 800c446: 4618 mov r0, r3 800c448: f7ff fec8 bl 800c1dc 800c44c: e005 b.n 800c45a } else { apply_command(cmd, NULL, 0); 800c44e: 7dfb ldrb r3, [r7, #23] 800c450: 2200 movs r2, #0 800c452: 2100 movs r1, #0 800c454: 4618 mov r0, r3 800c456: f7ff fec1 bl 800c1dc } return 1; 800c45a: 2301 movs r3, #1 } 800c45c: 4618 mov r0, r3 800c45e: 3718 adds r7, #24 800c460: 46bd mov sp, r7 800c462: bd80 pop {r7, pc} 800c464: 080143a0 .word 0x080143a0 800c468: 080143b4 .word 0x080143b4 800c46c: 080143c8 .word 0x080143c8 0800c470 : .fw_version_major = 0, .fw_version_minor = 0, .fw_version_patch = 0, }; void ReadVersion(){ 800c470: b480 push {r7} 800c472: af00 add r7, sp, #0 infoPacket.serialNumber = InfoBlock->serialNumber; 800c474: 4b0e ldr r3, [pc, #56] @ (800c4b0 ) 800c476: 681b ldr r3, [r3, #0] 800c478: 681b ldr r3, [r3, #0] 800c47a: b29a uxth r2, r3 800c47c: 4b0d ldr r3, [pc, #52] @ (800c4b4 ) 800c47e: 801a strh r2, [r3, #0] infoPacket.boardVersion = InfoBlock->boardVersion; 800c480: 4b0b ldr r3, [pc, #44] @ (800c4b0 ) 800c482: 681b ldr r3, [r3, #0] 800c484: 795a ldrb r2, [r3, #5] 800c486: 4b0b ldr r3, [pc, #44] @ (800c4b4 ) 800c488: 709a strb r2, [r3, #2] infoPacket.stationType = InfoBlock->stationType; 800c48a: 4b09 ldr r3, [pc, #36] @ (800c4b0 ) 800c48c: 681b ldr r3, [r3, #0] 800c48e: 791a ldrb r2, [r3, #4] 800c490: 4b08 ldr r3, [pc, #32] @ (800c4b4 ) 800c492: 70da strb r2, [r3, #3] infoPacket.fw_version_major = FW_VERSION_MAJOR; 800c494: 4b07 ldr r3, [pc, #28] @ (800c4b4 ) 800c496: 2201 movs r2, #1 800c498: 809a strh r2, [r3, #4] infoPacket.fw_version_minor = FW_VERSION_MINOR; 800c49a: 4b06 ldr r3, [pc, #24] @ (800c4b4 ) 800c49c: 2200 movs r2, #0 800c49e: 80da strh r2, [r3, #6] infoPacket.fw_version_patch = FW_VERSION_PATCH; 800c4a0: 4b04 ldr r3, [pc, #16] @ (800c4b4 ) 800c4a2: 2205 movs r2, #5 800c4a4: 811a strh r2, [r3, #8] } 800c4a6: bf00 nop 800c4a8: 46bd mov sp, r7 800c4aa: bc80 pop {r7} 800c4ac: 4770 bx lr 800c4ae: bf00 nop 800c4b0: 20000000 .word 0x20000000 800c4b4: 20000eb8 .word 0x20000eb8 0800c4b8 : // Внешняя функция обработки команд (определена в serial_handler.c) extern void SC_CommandHandler(ReceivedCommand_t* cmd); void SC_Init() { 800c4b8: b580 push {r7, lr} 800c4ba: af00 add r7, sp, #0 // Обнуляем структуру memset(&serial_control, 0, sizeof(SerialControl_t)); 800c4bc: f44f 7204 mov.w r2, #528 @ 0x210 800c4c0: 2100 movs r1, #0 800c4c2: 4805 ldr r0, [pc, #20] @ (800c4d8 ) 800c4c4: f006 fdbc bl 8013040 memset(&serial_iso, 0, sizeof(serial_iso)); 800c4c8: f44f 7204 mov.w r2, #528 @ 0x210 800c4cc: 2100 movs r1, #0 800c4ce: 4803 ldr r0, [pc, #12] @ (800c4dc ) 800c4d0: f006 fdb6 bl 8013040 } 800c4d4: bf00 nop 800c4d6: bd80 pop {r7, pc} 800c4d8: 20000a3c .word 0x20000a3c 800c4dc: 20000c4c .word 0x20000c4c 0800c4e0 : void SC_Task() { 800c4e0: b580 push {r7, lr} 800c4e2: af00 add r7, sp, #0 // Запуск приема в режиме прерывания с ожиданием idle if((huart2.RxState == HAL_UART_STATE_READY) && (serial_control.command_ready == 0)) HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c4e4: 4b2a ldr r3, [pc, #168] @ (800c590 ) 800c4e6: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800c4ea: b2db uxtb r3, r3 800c4ec: 2b20 cmp r3, #32 800c4ee: d10a bne.n 800c506 800c4f0: 4b28 ldr r3, [pc, #160] @ (800c594 ) 800c4f2: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800c4f6: b2db uxtb r3, r3 800c4f8: 2b00 cmp r3, #0 800c4fa: d104 bne.n 800c506 800c4fc: 22ff movs r2, #255 @ 0xff 800c4fe: 4926 ldr r1, [pc, #152] @ (800c598 ) 800c500: 4823 ldr r0, [pc, #140] @ (800c590 ) 800c502: f005 fcf1 bl 8011ee8 if((huart5.RxState == HAL_UART_STATE_READY)) HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c506: 4b25 ldr r3, [pc, #148] @ (800c59c ) 800c508: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800c50c: b2db uxtb r3, r3 800c50e: 2b20 cmp r3, #32 800c510: d104 bne.n 800c51c 800c512: 22ff movs r2, #255 @ 0xff 800c514: 4922 ldr r1, [pc, #136] @ (800c5a0 ) 800c516: 4821 ldr r0, [pc, #132] @ (800c59c ) 800c518: f005 fce6 bl 8011ee8 // Проверка таймаута отправки пакета (больше 100 мс) if (huart2.gState == HAL_UART_STATE_BUSY_TX && serial_control.tx_tick != 0) { 800c51c: 4b1c ldr r3, [pc, #112] @ (800c590 ) 800c51e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800c522: b2db uxtb r3, r3 800c524: 2b21 cmp r3, #33 @ 0x21 800c526: d119 bne.n 800c55c 800c528: 4b1a ldr r3, [pc, #104] @ (800c594 ) 800c52a: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800c52e: 2b00 cmp r3, #0 800c530: d014 beq.n 800c55c if ((HAL_GetTick() - serial_control.tx_tick) > 100) { 800c532: f001 fa13 bl 800d95c 800c536: 4602 mov r2, r0 800c538: 4b16 ldr r3, [pc, #88] @ (800c594 ) 800c53a: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800c53e: 1ad3 subs r3, r2, r3 800c540: 2b64 cmp r3, #100 @ 0x64 800c542: d90b bls.n 800c55c // Таймаут: принудительно сбрасываем передачу HAL_UART_Abort_IT(&huart2); 800c544: 4812 ldr r0, [pc, #72] @ (800c590 ) 800c546: f005 fd2d bl 8011fa4 // Выключаем DIR при сбросе передачи HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800c54a: 2200 movs r2, #0 800c54c: 2110 movs r1, #16 800c54e: 4815 ldr r0, [pc, #84] @ (800c5a4 ) 800c550: f003 fa15 bl 800f97e serial_control.tx_tick = 0; // Сбрасываем tick 800c554: 4b0f ldr r3, [pc, #60] @ (800c594 ) 800c556: 2200 movs r2, #0 800c558: f8c3 220c str.w r2, [r3, #524] @ 0x20c } } // Проверка наличия принятой команды для обработки if (serial_control.command_ready && (huart2.gState != HAL_UART_STATE_BUSY_TX)) { 800c55c: 4b0d ldr r3, [pc, #52] @ (800c594 ) 800c55e: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800c562: b2db uxtb r3, r3 800c564: 2b00 cmp r3, #0 800c566: d011 beq.n 800c58c 800c568: 4b09 ldr r3, [pc, #36] @ (800c590 ) 800c56a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800c56e: b2db uxtb r3, r3 800c570: 2b21 cmp r3, #33 @ 0x21 800c572: d00b beq.n 800c58c // HAL_Delay(2); SC_CommandHandler(&serial_control.received_command); 800c574: 480c ldr r0, [pc, #48] @ (800c5a8 ) 800c576: f000 f9ed bl 800c954 HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c57a: 22ff movs r2, #255 @ 0xff 800c57c: 4906 ldr r1, [pc, #24] @ (800c598 ) 800c57e: 4804 ldr r0, [pc, #16] @ (800c590 ) 800c580: f005 fcb2 bl 8011ee8 serial_control.command_ready = 0; // Сбрасываем флаг 800c584: 4b03 ldr r3, [pc, #12] @ (800c594 ) 800c586: 2200 movs r2, #0 800c588: f883 2208 strb.w r2, [r3, #520] @ 0x208 } } 800c58c: bf00 nop 800c58e: bd80 pop {r7, pc} 800c590: 20000fe8 .word 0x20000fe8 800c594: 20000a3c .word 0x20000a3c 800c598: 20000b3c .word 0x20000b3c 800c59c: 20000f58 .word 0x20000f58 800c5a0: 20000d4c .word 0x20000d4c 800c5a4: 40011400 .word 0x40011400 800c5a8: 20000c3c .word 0x20000c3c 0800c5ac : void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800c5ac: b580 push {r7, lr} 800c5ae: b082 sub sp, #8 800c5b0: af00 add r7, sp, #0 800c5b2: 6078 str r0, [r7, #4] 800c5b4: 460b mov r3, r1 800c5b6: 807b strh r3, [r7, #2] if (huart->Instance == huart2.Instance) { 800c5b8: 687b ldr r3, [r7, #4] 800c5ba: 681a ldr r2, [r3, #0] 800c5bc: 4b22 ldr r3, [pc, #136] @ (800c648 ) 800c5be: 681b ldr r3, [r3, #0] 800c5c0: 429a cmp r2, r3 800c5c2: d116 bne.n 800c5f2 if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800c5c4: 887b ldrh r3, [r7, #2] 800c5c6: 461a mov r2, r3 800c5c8: 4920 ldr r1, [pc, #128] @ (800c64c ) 800c5ca: 4821 ldr r0, [pc, #132] @ (800c650 ) 800c5cc: f000 f98e bl 800c8ec 800c5d0: 4603 mov r3, r0 800c5d2: 2b00 cmp r3, #0 800c5d4: d104 bne.n 800c5e0 SC_SendPacket(NULL, 0, RESP_INVALID); 800c5d6: 2214 movs r2, #20 800c5d8: 2100 movs r1, #0 800c5da: 2000 movs r0, #0 800c5dc: f000 f8fa bl 800c7d4 } g_sc_command_source = SC_SOURCE_UART2; 800c5e0: 4b1c ldr r3, [pc, #112] @ (800c654 ) 800c5e2: 2200 movs r2, #0 800c5e4: 701a strb r2, [r3, #0] HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c5e6: 22ff movs r2, #255 @ 0xff 800c5e8: 4918 ldr r1, [pc, #96] @ (800c64c ) 800c5ea: 4817 ldr r0, [pc, #92] @ (800c648 ) 800c5ec: f005 fc7c bl 8011ee8 } HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1); } else if (huart->Instance == huart3.Instance) { CCS_RxEventCallback(huart, Size); } } 800c5f0: e025 b.n 800c63e } else if (huart->Instance == huart5.Instance) { 800c5f2: 687b ldr r3, [r7, #4] 800c5f4: 681a ldr r2, [r3, #0] 800c5f6: 4b18 ldr r3, [pc, #96] @ (800c658 ) 800c5f8: 681b ldr r3, [r3, #0] 800c5fa: 429a cmp r2, r3 800c5fc: d114 bne.n 800c628 if (process_received_packet(&serial_iso, serial_iso.rx_buffer, Size)) { 800c5fe: 887b ldrh r3, [r7, #2] 800c600: 461a mov r2, r3 800c602: 4916 ldr r1, [pc, #88] @ (800c65c ) 800c604: 4816 ldr r0, [pc, #88] @ (800c660 ) 800c606: f000 f971 bl 800c8ec 800c60a: 4603 mov r3, r0 800c60c: 2b00 cmp r3, #0 800c60e: d005 beq.n 800c61c g_sc_command_source = SC_SOURCE_UART5; 800c610: 4b10 ldr r3, [pc, #64] @ (800c654 ) 800c612: 2201 movs r2, #1 800c614: 701a strb r2, [r3, #0] SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); 800c616: 4813 ldr r0, [pc, #76] @ (800c664 ) 800c618: f000 f99c bl 800c954 HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c61c: 22ff movs r2, #255 @ 0xff 800c61e: 490f ldr r1, [pc, #60] @ (800c65c ) 800c620: 480d ldr r0, [pc, #52] @ (800c658 ) 800c622: f005 fc61 bl 8011ee8 } 800c626: e00a b.n 800c63e } else if (huart->Instance == huart3.Instance) { 800c628: 687b ldr r3, [r7, #4] 800c62a: 681a ldr r2, [r3, #0] 800c62c: 4b0e ldr r3, [pc, #56] @ (800c668 ) 800c62e: 681b ldr r3, [r3, #0] 800c630: 429a cmp r2, r3 800c632: d104 bne.n 800c63e CCS_RxEventCallback(huart, Size); 800c634: 887b ldrh r3, [r7, #2] 800c636: 4619 mov r1, r3 800c638: 6878 ldr r0, [r7, #4] 800c63a: f7ff f9b9 bl 800b9b0 } 800c63e: bf00 nop 800c640: 3708 adds r7, #8 800c642: 46bd mov sp, r7 800c644: bd80 pop {r7, pc} 800c646: bf00 nop 800c648: 20000fe8 .word 0x20000fe8 800c64c: 20000b3c .word 0x20000b3c 800c650: 20000a3c .word 0x20000a3c 800c654: 20000e5c .word 0x20000e5c 800c658: 20000f58 .word 0x20000f58 800c65c: 20000d4c .word 0x20000d4c 800c660: 20000c4c .word 0x20000c4c 800c664: 20000e4c .word 0x20000e4c 800c668: 20001030 .word 0x20001030 0800c66c : void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 800c66c: b580 push {r7, lr} 800c66e: b082 sub sp, #8 800c670: af00 add r7, sp, #0 800c672: 6078 str r0, [r7, #4] if (huart->Instance == huart2.Instance) { 800c674: 687b ldr r3, [r7, #4] 800c676: 681a ldr r2, [r3, #0] 800c678: 4b08 ldr r3, [pc, #32] @ (800c69c ) 800c67a: 681b ldr r3, [r3, #0] 800c67c: 429a cmp r2, r3 800c67e: d108 bne.n 800c692 HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800c680: 2200 movs r2, #0 800c682: 2110 movs r1, #16 800c684: 4806 ldr r0, [pc, #24] @ (800c6a0 ) 800c686: f003 f97a bl 800f97e serial_control.tx_tick = 0; 800c68a: 4b06 ldr r3, [pc, #24] @ (800c6a4 ) 800c68c: 2200 movs r2, #0 800c68e: f8c3 220c str.w r2, [r3, #524] @ 0x20c } } 800c692: bf00 nop 800c694: 3708 adds r7, #8 800c696: 46bd mov sp, r7 800c698: bd80 pop {r7, pc} 800c69a: bf00 nop 800c69c: 20000fe8 .word 0x20000fe8 800c6a0: 40011400 .word 0x40011400 800c6a4: 20000a3c .word 0x20000a3c 0800c6a8 : // Приватные функции реализации // Полностью программная реализация CRC-32 (полином CRC32_POLYNOMIAL, порядок little-endian) static uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { 800c6a8: b480 push {r7} 800c6aa: b085 sub sp, #20 800c6ac: af00 add r7, sp, #0 800c6ae: 6078 str r0, [r7, #4] 800c6b0: 460b mov r3, r1 800c6b2: 807b strh r3, [r7, #2] uint32_t crc = 0xFFFFFFFFu; 800c6b4: f04f 33ff mov.w r3, #4294967295 800c6b8: 60fb str r3, [r7, #12] for (uint16_t i = 0; i < length; i++) { 800c6ba: 2300 movs r3, #0 800c6bc: 817b strh r3, [r7, #10] 800c6be: e021 b.n 800c704 crc ^= data[i]; 800c6c0: 897b ldrh r3, [r7, #10] 800c6c2: 687a ldr r2, [r7, #4] 800c6c4: 4413 add r3, r2 800c6c6: 781b ldrb r3, [r3, #0] 800c6c8: 461a mov r2, r3 800c6ca: 68fb ldr r3, [r7, #12] 800c6cc: 4053 eors r3, r2 800c6ce: 60fb str r3, [r7, #12] for (uint8_t bit = 0; bit < 8; bit++) { 800c6d0: 2300 movs r3, #0 800c6d2: 727b strb r3, [r7, #9] 800c6d4: e010 b.n 800c6f8 if (crc & 0x1u) { 800c6d6: 68fb ldr r3, [r7, #12] 800c6d8: f003 0301 and.w r3, r3, #1 800c6dc: 2b00 cmp r3, #0 800c6de: d005 beq.n 800c6ec crc = (crc >> 1) ^ CRC32_POLYNOMIAL; 800c6e0: 68fb ldr r3, [r7, #12] 800c6e2: 085a lsrs r2, r3, #1 800c6e4: 4b0d ldr r3, [pc, #52] @ (800c71c ) 800c6e6: 4053 eors r3, r2 800c6e8: 60fb str r3, [r7, #12] 800c6ea: e002 b.n 800c6f2 } else { crc >>= 1; 800c6ec: 68fb ldr r3, [r7, #12] 800c6ee: 085b lsrs r3, r3, #1 800c6f0: 60fb str r3, [r7, #12] for (uint8_t bit = 0; bit < 8; bit++) { 800c6f2: 7a7b ldrb r3, [r7, #9] 800c6f4: 3301 adds r3, #1 800c6f6: 727b strb r3, [r7, #9] 800c6f8: 7a7b ldrb r3, [r7, #9] 800c6fa: 2b07 cmp r3, #7 800c6fc: d9eb bls.n 800c6d6 for (uint16_t i = 0; i < length; i++) { 800c6fe: 897b ldrh r3, [r7, #10] 800c700: 3301 adds r3, #1 800c702: 817b strh r3, [r7, #10] 800c704: 897a ldrh r2, [r7, #10] 800c706: 887b ldrh r3, [r7, #2] 800c708: 429a cmp r2, r3 800c70a: d3d9 bcc.n 800c6c0 } } } return crc ^ 0xFFFFFFFFu; 800c70c: 68fb ldr r3, [r7, #12] 800c70e: 43db mvns r3, r3 } 800c710: 4618 mov r0, r3 800c712: 3714 adds r7, #20 800c714: 46bd mov sp, r7 800c716: bc80 pop {r7} 800c718: 4770 bx lr 800c71a: bf00 nop 800c71c: edb88320 .word 0xedb88320 0800c720 : static uint16_t encode_packet(const uint8_t* payload, uint16_t payload_len, uint8_t* output, uint8_t response_code) { 800c720: b580 push {r7, lr} 800c722: b088 sub sp, #32 800c724: af00 add r7, sp, #0 800c726: 60f8 str r0, [r7, #12] 800c728: 607a str r2, [r7, #4] 800c72a: 461a mov r2, r3 800c72c: 460b mov r3, r1 800c72e: 817b strh r3, [r7, #10] 800c730: 4613 mov r3, r2 800c732: 727b strb r3, [r7, #9] uint16_t out_index = 0; 800c734: 2300 movs r3, #0 800c736: 83fb strh r3, [r7, #30] output[out_index++] = response_code; 800c738: 8bfb ldrh r3, [r7, #30] 800c73a: 1c5a adds r2, r3, #1 800c73c: 83fa strh r2, [r7, #30] 800c73e: 461a mov r2, r3 800c740: 687b ldr r3, [r7, #4] 800c742: 4413 add r3, r2 800c744: 7a7a ldrb r2, [r7, #9] 800c746: 701a strb r2, [r3, #0] if (payload != NULL) { 800c748: 68fb ldr r3, [r7, #12] 800c74a: 2b00 cmp r3, #0 800c74c: d019 beq.n 800c782 // Просто копируем полезную нагрузку без какого‑либо экранирования for (uint16_t i = 0; i < payload_len; i++) { 800c74e: 2300 movs r3, #0 800c750: 83bb strh r3, [r7, #28] 800c752: e012 b.n 800c77a output[out_index++] = payload[i]; 800c754: 8bbb ldrh r3, [r7, #28] 800c756: 68fa ldr r2, [r7, #12] 800c758: 441a add r2, r3 800c75a: 8bfb ldrh r3, [r7, #30] 800c75c: 1c59 adds r1, r3, #1 800c75e: 83f9 strh r1, [r7, #30] 800c760: 4619 mov r1, r3 800c762: 687b ldr r3, [r7, #4] 800c764: 440b add r3, r1 800c766: 7812 ldrb r2, [r2, #0] 800c768: 701a strb r2, [r3, #0] // Проверка переполнения if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800c76a: 8bfb ldrh r3, [r7, #30] 800c76c: 2bfa cmp r3, #250 @ 0xfa 800c76e: d901 bls.n 800c774 return 0; 800c770: 2300 movs r3, #0 800c772: e02a b.n 800c7ca for (uint16_t i = 0; i < payload_len; i++) { 800c774: 8bbb ldrh r3, [r7, #28] 800c776: 3301 adds r3, #1 800c778: 83bb strh r3, [r7, #28] 800c77a: 8bba ldrh r2, [r7, #28] 800c77c: 897b ldrh r3, [r7, #10] 800c77e: 429a cmp r2, r3 800c780: d3e8 bcc.n 800c754 } } } // Вычисляем CRC для всего содержимого (код ответа + полезная нагрузка) uint32_t crc = calculate_crc32(output, out_index); 800c782: 8bfb ldrh r3, [r7, #30] 800c784: 4619 mov r1, r3 800c786: 6878 ldr r0, [r7, #4] 800c788: f7ff ff8e bl 800c6a8 800c78c: 4603 mov r3, r0 800c78e: 613b str r3, [r7, #16] uint8_t* crc_bytes = (uint8_t*)&crc; 800c790: f107 0310 add.w r3, r7, #16 800c794: 617b str r3, [r7, #20] // Добавляем CRC без экранирования for (int i = 0; i < 4; i++) { 800c796: 2300 movs r3, #0 800c798: 61bb str r3, [r7, #24] 800c79a: e012 b.n 800c7c2 output[out_index++] = crc_bytes[i]; 800c79c: 69bb ldr r3, [r7, #24] 800c79e: 697a ldr r2, [r7, #20] 800c7a0: 441a add r2, r3 800c7a2: 8bfb ldrh r3, [r7, #30] 800c7a4: 1c59 adds r1, r3, #1 800c7a6: 83f9 strh r1, [r7, #30] 800c7a8: 4619 mov r1, r3 800c7aa: 687b ldr r3, [r7, #4] 800c7ac: 440b add r3, r1 800c7ae: 7812 ldrb r2, [r2, #0] 800c7b0: 701a strb r2, [r3, #0] if (out_index >= MAX_TX_BUFFER_SIZE - 1) { // место для END_BYTE 800c7b2: 8bfb ldrh r3, [r7, #30] 800c7b4: 2bfe cmp r3, #254 @ 0xfe 800c7b6: d901 bls.n 800c7bc return 0; 800c7b8: 2300 movs r3, #0 800c7ba: e006 b.n 800c7ca for (int i = 0; i < 4; i++) { 800c7bc: 69bb ldr r3, [r7, #24] 800c7be: 3301 adds r3, #1 800c7c0: 61bb str r3, [r7, #24] 800c7c2: 69bb ldr r3, [r7, #24] 800c7c4: 2b03 cmp r3, #3 800c7c6: dde9 ble.n 800c79c } } return out_index; 800c7c8: 8bfb ldrh r3, [r7, #30] } 800c7ca: 4618 mov r0, r3 800c7cc: 3720 adds r7, #32 800c7ce: 46bd mov sp, r7 800c7d0: bd80 pop {r7, pc} ... 0800c7d4 : void SC_SendPacket(const uint8_t* payload, uint16_t payload_len, uint8_t response_code) { 800c7d4: b580 push {r7, lr} 800c7d6: b084 sub sp, #16 800c7d8: af00 add r7, sp, #0 800c7da: 6078 str r0, [r7, #4] 800c7dc: 460b mov r3, r1 800c7de: 807b strh r3, [r7, #2] 800c7e0: 4613 mov r3, r2 800c7e2: 707b strb r3, [r7, #1] uint16_t packet_len = encode_packet(payload, payload_len, serial_control.tx_buffer, response_code); 800c7e4: 787b ldrb r3, [r7, #1] 800c7e6: 8879 ldrh r1, [r7, #2] 800c7e8: 4a15 ldr r2, [pc, #84] @ (800c840 ) 800c7ea: 6878 ldr r0, [r7, #4] 800c7ec: f7ff ff98 bl 800c720 800c7f0: 4603 mov r3, r0 800c7f2: 81fb strh r3, [r7, #14] if (packet_len > 0) { 800c7f4: 89fb ldrh r3, [r7, #14] 800c7f6: 2b00 cmp r3, #0 800c7f8: d01e beq.n 800c838 if (huart2.gState == HAL_UART_STATE_BUSY_TX) { 800c7fa: 4b12 ldr r3, [pc, #72] @ (800c844 ) 800c7fc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800c800: b2db uxtb r3, r3 800c802: 2b21 cmp r3, #33 @ 0x21 800c804: d107 bne.n 800c816 HAL_UART_Abort_IT(&huart2); 800c806: 480f ldr r0, [pc, #60] @ (800c844 ) 800c808: f005 fbcc bl 8011fa4 HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800c80c: 2200 movs r2, #0 800c80e: 2110 movs r1, #16 800c810: 480d ldr r0, [pc, #52] @ (800c848 ) 800c812: f003 f8b4 bl 800f97e } HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_SET); 800c816: 2201 movs r2, #1 800c818: 2110 movs r1, #16 800c81a: 480b ldr r0, [pc, #44] @ (800c848 ) 800c81c: f003 f8af bl 800f97e HAL_UART_Transmit_IT(&huart2, serial_control.tx_buffer, packet_len); 800c820: 89fb ldrh r3, [r7, #14] 800c822: 461a mov r2, r3 800c824: 4906 ldr r1, [pc, #24] @ (800c840 ) 800c826: 4807 ldr r0, [pc, #28] @ (800c844 ) 800c828: f005 fb29 bl 8011e7e serial_control.tx_tick = HAL_GetTick(); 800c82c: f001 f896 bl 800d95c 800c830: 4603 mov r3, r0 800c832: 4a03 ldr r2, [pc, #12] @ (800c840 ) 800c834: f8c2 320c str.w r3, [r2, #524] @ 0x20c } } 800c838: bf00 nop 800c83a: 3710 adds r7, #16 800c83c: 46bd mov sp, r7 800c83e: bd80 pop {r7, pc} 800c840: 20000a3c .word 0x20000a3c 800c844: 20000fe8 .word 0x20000fe8 800c848: 40011400 .word 0x40011400 0800c84c : static uint8_t parse_packet(const uint8_t* packet_data, uint16_t packet_len, ReceivedCommand_t* out_cmd) { 800c84c: b580 push {r7, lr} 800c84e: b088 sub sp, #32 800c850: af00 add r7, sp, #0 800c852: 60f8 str r0, [r7, #12] 800c854: 460b mov r3, r1 800c856: 607a str r2, [r7, #4] 800c858: 817b strh r3, [r7, #10] // }else{ // test_crc_invalid = 5; // } // Минимальный размер: 1 байт команды + 4 байта CRC if (packet_len < 5) return 0; 800c85a: 897b ldrh r3, [r7, #10] 800c85c: 2b04 cmp r3, #4 800c85e: d801 bhi.n 800c864 800c860: 2300 movs r3, #0 800c862: e03f b.n 800c8e4 if (packet_len > MAX_RX_BUFFER_SIZE) return 0; 800c864: 897b ldrh r3, [r7, #10] 800c866: f5b3 7f80 cmp.w r3, #256 @ 0x100 800c86a: d901 bls.n 800c870 800c86c: 2300 movs r3, #0 800c86e: e039 b.n 800c8e4 uint16_t payload_length = packet_len - 4; 800c870: 897b ldrh r3, [r7, #10] 800c872: 3b04 subs r3, #4 800c874: 83fb strh r3, [r7, #30] // Извлекаем принятую CRC (последние 4 байта, little-endian) uint32_t received_checksum = ((uint32_t)packet_data[payload_length] << 0) | 800c876: 8bfb ldrh r3, [r7, #30] 800c878: 68fa ldr r2, [r7, #12] 800c87a: 4413 add r3, r2 800c87c: 781b ldrb r3, [r3, #0] 800c87e: 4619 mov r1, r3 ((uint32_t)packet_data[payload_length + 1] << 8) | 800c880: 8bfb ldrh r3, [r7, #30] 800c882: 3301 adds r3, #1 800c884: 68fa ldr r2, [r7, #12] 800c886: 4413 add r3, r2 800c888: 781b ldrb r3, [r3, #0] 800c88a: 021b lsls r3, r3, #8 ((uint32_t)packet_data[payload_length] << 0) | 800c88c: ea41 0203 orr.w r2, r1, r3 ((uint32_t)packet_data[payload_length + 2] << 16) | 800c890: 8bfb ldrh r3, [r7, #30] 800c892: 3302 adds r3, #2 800c894: 68f9 ldr r1, [r7, #12] 800c896: 440b add r3, r1 800c898: 781b ldrb r3, [r3, #0] 800c89a: 041b lsls r3, r3, #16 ((uint32_t)packet_data[payload_length + 1] << 8) | 800c89c: 431a orrs r2, r3 ((uint32_t)packet_data[payload_length + 3] << 24); 800c89e: 8bfb ldrh r3, [r7, #30] 800c8a0: 3303 adds r3, #3 800c8a2: 68f9 ldr r1, [r7, #12] 800c8a4: 440b add r3, r1 800c8a6: 781b ldrb r3, [r3, #0] 800c8a8: 061b lsls r3, r3, #24 uint32_t received_checksum = 800c8aa: 4313 orrs r3, r2 800c8ac: 61bb str r3, [r7, #24] // Вычисляем CRC для полезной нагрузки uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); 800c8ae: 8bfb ldrh r3, [r7, #30] 800c8b0: 4619 mov r1, r3 800c8b2: 68f8 ldr r0, [r7, #12] 800c8b4: f7ff fef8 bl 800c6a8 800c8b8: 6178 str r0, [r7, #20] if (received_checksum != calculated_checksum) return 0; // CRC не совпадает 800c8ba: 69ba ldr r2, [r7, #24] 800c8bc: 697b ldr r3, [r7, #20] 800c8be: 429a cmp r2, r3 800c8c0: d001 beq.n 800c8c6 800c8c2: 2300 movs r3, #0 800c8c4: e00e b.n 800c8e4 out_cmd->argument = (void *)&packet_data[1]; 800c8c6: 68fb ldr r3, [r7, #12] 800c8c8: 1c5a adds r2, r3, #1 800c8ca: 687b ldr r3, [r7, #4] 800c8cc: 605a str r2, [r3, #4] out_cmd->command = packet_data[0]; 800c8ce: 68fb ldr r3, [r7, #12] 800c8d0: 781a ldrb r2, [r3, #0] 800c8d2: 687b ldr r3, [r7, #4] 800c8d4: 701a strb r2, [r3, #0] out_cmd->argument_length = (uint8_t)(payload_length - 1); 800c8d6: 8bfb ldrh r3, [r7, #30] 800c8d8: b2db uxtb r3, r3 800c8da: 3b01 subs r3, #1 800c8dc: b2da uxtb r2, r3 800c8de: 687b ldr r3, [r7, #4] 800c8e0: 705a strb r2, [r3, #1] return 1; 800c8e2: 2301 movs r3, #1 } 800c8e4: 4618 mov r0, r3 800c8e6: 3720 adds r7, #32 800c8e8: 46bd mov sp, r7 800c8ea: bd80 pop {r7, pc} 0800c8ec : static uint8_t process_received_packet(SerialControl_t *ctx, const uint8_t* packet_data, uint16_t packet_len) { 800c8ec: b580 push {r7, lr} 800c8ee: b084 sub sp, #16 800c8f0: af00 add r7, sp, #0 800c8f2: 60f8 str r0, [r7, #12] 800c8f4: 60b9 str r1, [r7, #8] 800c8f6: 4613 mov r3, r2 800c8f8: 80fb strh r3, [r7, #6] if (!parse_packet(packet_data, packet_len, (ReceivedCommand_t *)&ctx->received_command)) { 800c8fa: 68fb ldr r3, [r7, #12] 800c8fc: f503 7200 add.w r2, r3, #512 @ 0x200 800c900: 88fb ldrh r3, [r7, #6] 800c902: 4619 mov r1, r3 800c904: 68b8 ldr r0, [r7, #8] 800c906: f7ff ffa1 bl 800c84c 800c90a: 4603 mov r3, r0 800c90c: 2b00 cmp r3, #0 800c90e: d101 bne.n 800c914 return 0; 800c910: 2300 movs r3, #0 800c912: e004 b.n 800c91e } ctx->command_ready = 1; 800c914: 68fb ldr r3, [r7, #12] 800c916: 2201 movs r2, #1 800c918: f883 2208 strb.w r2, [r3, #520] @ 0x208 return 1; 800c91c: 2301 movs r3, #1 } 800c91e: 4618 mov r0, r3 800c920: 3710 adds r7, #16 800c922: 46bd mov sp, r7 800c924: bd80 pop {r7, pc} ... 0800c928 <__NVIC_SystemReset>: { 800c928: b480 push {r7} 800c92a: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 800c92c: f3bf 8f4f dsb sy } 800c930: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800c932: 4b06 ldr r3, [pc, #24] @ (800c94c <__NVIC_SystemReset+0x24>) 800c934: 68db ldr r3, [r3, #12] 800c936: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800c93a: 4904 ldr r1, [pc, #16] @ (800c94c <__NVIC_SystemReset+0x24>) 800c93c: 4b04 ldr r3, [pc, #16] @ (800c950 <__NVIC_SystemReset+0x28>) 800c93e: 4313 orrs r3, r2 800c940: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800c942: f3bf 8f4f dsb sy } 800c946: bf00 nop __NOP(); 800c948: bf00 nop 800c94a: e7fd b.n 800c948 <__NVIC_SystemReset+0x20> 800c94c: e000ed00 .word 0xe000ed00 800c950: 05fa0004 .word 0x05fa0004 0800c954 : .chargerNumber = 00001, .unixTime = 1721651966, }; // Единая функция-обработчик всех команд со switch-case void SC_CommandHandler(ReceivedCommand_t* cmd) { 800c954: b580 push {r7, lr} 800c956: b084 sub sp, #16 800c958: af00 add r7, sp, #0 800c95a: 6078 str r0, [r7, #4] uint8_t response_code = RESP_FAILED; 800c95c: 2313 movs r3, #19 800c95e: 73fb strb r3, [r7, #15] switch (cmd->command) { 800c960: 687b ldr r3, [r7, #4] 800c962: 781b ldrb r3, [r3, #0] 800c964: 2bc2 cmp r3, #194 @ 0xc2 800c966: f300 80cc bgt.w 800cb02 800c96a: 2bb0 cmp r3, #176 @ 0xb0 800c96c: da0f bge.n 800c98e 800c96e: 2b60 cmp r3, #96 @ 0x60 800c970: d042 beq.n 800c9f8 800c972: 2b60 cmp r3, #96 @ 0x60 800c974: f300 80c5 bgt.w 800cb02 800c978: 2b50 cmp r3, #80 @ 0x50 800c97a: d043 beq.n 800ca04 800c97c: 2b50 cmp r3, #80 @ 0x50 800c97e: f300 80c0 bgt.w 800cb02 800c982: 2b01 cmp r3, #1 800c984: f000 80a6 beq.w 800cad4 800c988: 2b40 cmp r3, #64 @ 0x40 800c98a: d02d beq.n 800c9e8 800c98c: e0b9 b.n 800cb02 800c98e: 3bb0 subs r3, #176 @ 0xb0 800c990: 2b12 cmp r3, #18 800c992: f200 80b6 bhi.w 800cb02 800c996: a201 add r2, pc, #4 @ (adr r2, 800c99c ) 800c998: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c99c: 0800ca0b .word 0x0800ca0b 800c9a0: 0800cb03 .word 0x0800cb03 800c9a4: 0800cb03 .word 0x0800cb03 800c9a8: 0800cb03 .word 0x0800cb03 800c9ac: 0800cb03 .word 0x0800cb03 800c9b0: 0800cab3 .word 0x0800cab3 800c9b4: 0800cb03 .word 0x0800cb03 800c9b8: 0800cb03 .word 0x0800cb03 800c9bc: 0800cb03 .word 0x0800cb03 800c9c0: 0800cb03 .word 0x0800cb03 800c9c4: 0800cb03 .word 0x0800cb03 800c9c8: 0800cb03 .word 0x0800cb03 800c9cc: 0800cb03 .word 0x0800cb03 800c9d0: 0800cb03 .word 0x0800cb03 800c9d4: 0800cb03 .word 0x0800cb03 800c9d8: 0800cb03 .word 0x0800cb03 800c9dc: 0800ca49 .word 0x0800ca49 800c9e0: 0800caad .word 0x0800caad 800c9e4: 0800ca81 .word 0x0800ca81 // Команды БЕЗ аргументов case CMD_GET_STATUS: // Логика получения информации monitoring_data_callback(); 800c9e8: f000 f8b2 bl 800cb50 // Отправляем с нормальным приоритетом SC_SendPacket((uint8_t*)&statusPacket, sizeof(statusPacket), CMD_GET_STATUS); 800c9ec: 2240 movs r2, #64 @ 0x40 800c9ee: 2158 movs r1, #88 @ 0x58 800c9f0: 484b ldr r0, [pc, #300] @ (800cb20 ) 800c9f2: f7ff feef bl 800c7d4 return; // Специальный ответ уже отправлен 800c9f6: e08f b.n 800cb18 case CMD_GET_INFO: SC_SendPacket((uint8_t*)&infoPacket, sizeof(infoPacket), CMD_GET_INFO); 800c9f8: 2260 movs r2, #96 @ 0x60 800c9fa: 210a movs r1, #10 800c9fc: 4849 ldr r0, [pc, #292] @ (800cb24 ) 800c9fe: f7ff fee9 bl 800c7d4 return; 800ca02: e089 b.n 800cb18 case CMD_GET_LOG: debug_buffer_send(); 800ca04: f7fd fcd8 bl 800a3b8 return; // Ответ формируется внутри debug_buffer_send 800ca08: e086 b.n 800cb18 // Команды С аргументами case CMD_SET_CONFIG: if (cmd->argument_length == sizeof(ConfigBlock_t)) { 800ca0a: 687b ldr r3, [r7, #4] 800ca0c: 785b ldrb r3, [r3, #1] 800ca0e: 2b0b cmp r3, #11 800ca10: d117 bne.n 800ca42 memcpy(&config, cmd->argument, sizeof(ConfigBlock_t)); 800ca12: 687b ldr r3, [r7, #4] 800ca14: 685a ldr r2, [r3, #4] 800ca16: 4b44 ldr r3, [pc, #272] @ (800cb28 ) 800ca18: 6810 ldr r0, [r2, #0] 800ca1a: 6851 ldr r1, [r2, #4] 800ca1c: c303 stmia r3!, {r0, r1} 800ca1e: 8911 ldrh r1, [r2, #8] 800ca20: 7a92 ldrb r2, [r2, #10] 800ca22: 8019 strh r1, [r3, #0] 800ca24: 709a strb r2, [r3, #2] config_initialized = 1; 800ca26: 4b41 ldr r3, [pc, #260] @ (800cb2c ) 800ca28: 2201 movs r2, #1 800ca2a: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Set Config: %s %d\n", config.location, config.chargerNumber); 800ca2c: 4b3e ldr r3, [pc, #248] @ (800cb28 ) 800ca2e: f8d3 3003 ldr.w r3, [r3, #3] 800ca32: 4a3d ldr r2, [pc, #244] @ (800cb28 ) 800ca34: 493e ldr r1, [pc, #248] @ (800cb30 ) 800ca36: 2007 movs r0, #7 800ca38: f7fd fd20 bl 800a47c response_code = RESP_SUCCESS; 800ca3c: 2312 movs r3, #18 800ca3e: 73fb strb r3, [r7, #15] break; 800ca40: e062 b.n 800cb08 } response_code = RESP_FAILED; 800ca42: 2313 movs r3, #19 800ca44: 73fb strb r3, [r7, #15] break; 800ca46: e05f b.n 800cb08 case CMD_SET_POWER_LIMIT: if (cmd->argument_length == 1) { 800ca48: 687b ldr r3, [r7, #4] 800ca4a: 785b ldrb r3, [r3, #1] 800ca4c: 2b01 cmp r3, #1 800ca4e: d114 bne.n 800ca7a PSU0.power_limit = ((uint8_t*)cmd->argument)[0] * 1000; 800ca50: 687b ldr r3, [r7, #4] 800ca52: 685b ldr r3, [r3, #4] 800ca54: 781b ldrb r3, [r3, #0] 800ca56: 461a mov r2, r3 800ca58: f44f 737a mov.w r3, #1000 @ 0x3e8 800ca5c: fb02 f303 mul.w r3, r2, r3 800ca60: 461a mov r2, r3 800ca62: 4b34 ldr r3, [pc, #208] @ (800cb34 ) 800ca64: 615a str r2, [r3, #20] log_printf(LOG_INFO, "Power limit: %d\n", PSU0.power_limit); 800ca66: 4b33 ldr r3, [pc, #204] @ (800cb34 ) 800ca68: 695b ldr r3, [r3, #20] 800ca6a: 461a mov r2, r3 800ca6c: 4932 ldr r1, [pc, #200] @ (800cb38 ) 800ca6e: 2007 movs r0, #7 800ca70: f7fd fd04 bl 800a47c //CONN.connState = (((uint8_t*)cmd->argument)[0])/4; response_code = RESP_SUCCESS; 800ca74: 2312 movs r3, #18 800ca76: 73fb strb r3, [r7, #15] break; 800ca78: e046 b.n 800cb08 } response_code = RESP_FAILED; 800ca7a: 2313 movs r3, #19 800ca7c: 73fb strb r3, [r7, #15] break; 800ca7e: e043 b.n 800cb08 case CMD_CHARGE_PERMIT: if (cmd->argument_length == 1) { 800ca80: 687b ldr r3, [r7, #4] 800ca82: 785b ldrb r3, [r3, #1] 800ca84: 2b01 cmp r3, #1 800ca86: d10e bne.n 800caa6 CONN.connControl = ((uint8_t*)cmd->argument)[0]; 800ca88: 687b ldr r3, [r7, #4] 800ca8a: 685b ldr r3, [r3, #4] 800ca8c: 781a ldrb r2, [r3, #0] 800ca8e: 4b2b ldr r3, [pc, #172] @ (800cb3c ) 800ca90: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Charge permit: %d\n", CONN.connControl); 800ca92: 4b2a ldr r3, [pc, #168] @ (800cb3c ) 800ca94: 781b ldrb r3, [r3, #0] 800ca96: 461a mov r2, r3 800ca98: 4929 ldr r1, [pc, #164] @ (800cb40 ) 800ca9a: 2007 movs r0, #7 800ca9c: f7fd fcee bl 800a47c response_code = RESP_SUCCESS; 800caa0: 2312 movs r3, #18 800caa2: 73fb strb r3, [r7, #15] break; 800caa4: e030 b.n 800cb08 } response_code = RESP_FAILED; 800caa6: 2313 movs r3, #19 800caa8: 73fb strb r3, [r7, #15] break; 800caaa: e02d b.n 800cb08 // memcpy(&PSU_TestMode, cmd->argument, sizeof(PSU_TestMode_t)); // log_printf(LOG_INFO, "Test PSU: %d %d %d\n", PSU_TestMode.enable, PSU_TestMode.voltage, PSU_TestMode.current); // response_code = RESP_SUCCESS; // break; // } response_code = RESP_FAILED; 800caac: 2313 movs r3, #19 800caae: 73fb strb r3, [r7, #15] break; 800cab0: e02a b.n 800cb08 case CMD_DEVICE_RESET: // 2. Отправляем SUCCESS (хост может успеть получить его перед ребутом) SC_SendPacket(NULL, 0, RESP_SUCCESS); 800cab2: 2212 movs r2, #18 800cab4: 2100 movs r1, #0 800cab6: 2000 movs r0, #0 800cab8: f7ff fe8c bl 800c7d4 while(huart2.gState == HAL_UART_STATE_BUSY_TX); // Ожидание завершения передачи 800cabc: bf00 nop 800cabe: 4b21 ldr r3, [pc, #132] @ (800cb44 ) 800cac0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800cac4: b2db uxtb r3, r3 800cac6: 2b21 cmp r3, #33 @ 0x21 800cac8: d0f9 beq.n 800cabe HAL_Delay(10); 800caca: 200a movs r0, #10 800cacc: f000 ff50 bl 800d970 // 3. Выполняем программный сброс NVIC_SystemReset(); 800cad0: f7ff ff2a bl 800c928 <__NVIC_SystemReset> return; // Сюда код уже не дойдет, но для компилятора нxужно case CMD_ISOLATION_STATUS: if (cmd->argument_length == sizeof(IsolationStatusPacket_t)) { 800cad4: 687b ldr r3, [r7, #4] 800cad6: 785b ldrb r3, [r3, #1] 800cad8: 2b09 cmp r3, #9 800cada: d10f bne.n 800cafc memcpy(&ISO, cmd->argument, sizeof(IsolationStatusPacket_t)); 800cadc: 687b ldr r3, [r7, #4] 800cade: 685a ldr r2, [r3, #4] 800cae0: 4b19 ldr r3, [pc, #100] @ (800cb48 ) 800cae2: 6810 ldr r0, [r2, #0] 800cae4: 6851 ldr r1, [r2, #4] 800cae6: c303 stmia r3!, {r0, r1} 800cae8: 7a12 ldrb r2, [r2, #8] 800caea: 701a strb r2, [r3, #0] // Для однонаправленного UART5 ответ не нужен if (g_sc_command_source == SC_SOURCE_UART5) { 800caec: 4b17 ldr r3, [pc, #92] @ (800cb4c ) 800caee: 781b ldrb r3, [r3, #0] 800caf0: b2db uxtb r3, r3 800caf2: 2b01 cmp r3, #1 800caf4: d00f beq.n 800cb16 return; } response_code = RESP_SUCCESS; 800caf6: 2312 movs r3, #18 800caf8: 73fb strb r3, [r7, #15] break; 800cafa: e005 b.n 800cb08 } response_code = RESP_FAILED; 800cafc: 2313 movs r3, #19 800cafe: 73fb strb r3, [r7, #15] break; 800cb00: e002 b.n 800cb08 default: // Неизвестная команда response_code = RESP_FAILED; 800cb02: 2313 movs r3, #19 800cb04: 73fb strb r3, [r7, #15] break; 800cb06: bf00 nop } // Отправляем финальный ответ (для команд без собственного ответа) SC_SendPacket(NULL, 0, response_code); 800cb08: 7bfb ldrb r3, [r7, #15] 800cb0a: 461a mov r2, r3 800cb0c: 2100 movs r1, #0 800cb0e: 2000 movs r0, #0 800cb10: f7ff fe60 bl 800c7d4 800cb14: e000 b.n 800cb18 return; 800cb16: bf00 nop } 800cb18: 3710 adds r7, #16 800cb1a: 46bd mov sp, r7 800cb1c: bd80 pop {r7, pc} 800cb1e: bf00 nop 800cb20: 20000e60 .word 0x20000e60 800cb24: 20000eb8 .word 0x20000eb8 800cb28: 20000060 .word 0x20000060 800cb2c: 20000ec2 .word 0x20000ec2 800cb30: 080143e8 .word 0x080143e8 800cb34: 20000724 .word 0x20000724 800cb38: 080143fc .word 0x080143fc 800cb3c: 200001d4 .word 0x200001d4 800cb40: 08014410 .word 0x08014410 800cb44: 20000fe8 .word 0x20000fe8 800cb48: 20000054 .word 0x20000054 800cb4c: 20000e5c .word 0x20000e5c 0800cb50 : // Колбэк для заполнения данных мониторинга void monitoring_data_callback() { 800cb50: b580 push {r7, lr} 800cb52: af00 add r7, sp, #0 // Информация о зарядной сессии statusPacket.SOC = CONN.SOC; 800cb54: 4b8f ldr r3, [pc, #572] @ (800cd94 ) 800cb56: 789a ldrb r2, [r3, #2] 800cb58: 4b8f ldr r3, [pc, #572] @ (800cd98 ) 800cb5a: 709a strb r2, [r3, #2] statusPacket.Energy = CONN.Energy; 800cb5c: 4b8d ldr r3, [pc, #564] @ (800cd94 ) 800cb5e: f8d3 3007 ldr.w r3, [r3, #7] 800cb62: 4a8d ldr r2, [pc, #564] @ (800cd98 ) 800cb64: f8c2 3003 str.w r3, [r2, #3] statusPacket.RequestedVoltage = CONN.RequestedVoltage; 800cb68: 4b8a ldr r3, [pc, #552] @ (800cd94 ) 800cb6a: f8b3 300f ldrh.w r3, [r3, #15] 800cb6e: b29a uxth r2, r3 800cb70: 4b89 ldr r3, [pc, #548] @ (800cd98 ) 800cb72: f8a3 2007 strh.w r2, [r3, #7] statusPacket.RequestedCurrent = CONN.WantedCurrent; 800cb76: 4b87 ldr r3, [pc, #540] @ (800cd94 ) 800cb78: f8b3 301b ldrh.w r3, [r3, #27] 800cb7c: b29a uxth r2, r3 800cb7e: 4b86 ldr r3, [pc, #536] @ (800cd98 ) 800cb80: f8a3 2009 strh.w r2, [r3, #9] statusPacket.MeasuredVoltage = CONN.MeasuredVoltage; 800cb84: 4b83 ldr r3, [pc, #524] @ (800cd94 ) 800cb86: f8b3 3013 ldrh.w r3, [r3, #19] 800cb8a: b29a uxth r2, r3 800cb8c: 4b82 ldr r3, [pc, #520] @ (800cd98 ) 800cb8e: f8a3 200b strh.w r2, [r3, #11] statusPacket.MeasuredCurrent = CONN.MeasuredCurrent; 800cb92: 4b80 ldr r3, [pc, #512] @ (800cd94 ) 800cb94: f8b3 3015 ldrh.w r3, [r3, #21] 800cb98: b29a uxth r2, r3 800cb9a: 4b7f ldr r3, [pc, #508] @ (800cd98 ) 800cb9c: f8a3 200d strh.w r2, [r3, #13] statusPacket.outputEnabled = CONN.outputEnabled; 800cba0: 4b7c ldr r3, [pc, #496] @ (800cd94 ) 800cba2: 7e1a ldrb r2, [r3, #24] 800cba4: 4b7c ldr r3, [pc, #496] @ (800cd98 ) 800cba6: 73da strb r2, [r3, #15] statusPacket.chargingError = CONN.chargingError; 800cba8: 4b7a ldr r3, [pc, #488] @ (800cd94 ) 800cbaa: 7f5a ldrb r2, [r3, #29] 800cbac: 4b7a ldr r3, [pc, #488] @ (800cd98 ) 800cbae: 705a strb r2, [r3, #1] statusPacket.connState = CONN.connState; 800cbb0: 4b78 ldr r3, [pc, #480] @ (800cd94 ) 800cbb2: 785a ldrb r2, [r3, #1] 800cbb4: 4b78 ldr r3, [pc, #480] @ (800cd98 ) 800cbb6: 701a strb r2, [r3, #0] statusPacket.chargingElapsedTimeMin = 0; 800cbb8: 4b77 ldr r3, [pc, #476] @ (800cd98 ) 800cbba: 2200 movs r2, #0 800cbbc: 741a strb r2, [r3, #16] 800cbbe: 2200 movs r2, #0 800cbc0: 745a strb r2, [r3, #17] statusPacket.chargingElapsedTimeSec = 0; 800cbc2: 4b75 ldr r3, [pc, #468] @ (800cd98 ) 800cbc4: 2200 movs r2, #0 800cbc6: 749a strb r2, [r3, #18] statusPacket.estimatedRemainingChargingTime = 0; 800cbc8: 4b73 ldr r3, [pc, #460] @ (800cd98 ) 800cbca: 2200 movs r2, #0 800cbcc: 74da strb r2, [r3, #19] 800cbce: 2200 movs r2, #0 800cbd0: 751a strb r2, [r3, #20] // состояние зарядной станции statusPacket.relayAC = RELAY_Read(RELAY_AC); 800cbd2: 2004 movs r0, #4 800cbd4: f7fc fcdc bl 8009590 800cbd8: 4603 mov r3, r0 800cbda: f003 0301 and.w r3, r3, #1 800cbde: b2d9 uxtb r1, r3 800cbe0: 4a6d ldr r2, [pc, #436] @ (800cd98 ) 800cbe2: 7d53 ldrb r3, [r2, #21] 800cbe4: f361 0300 bfi r3, r1, #0, #1 800cbe8: 7553 strb r3, [r2, #21] statusPacket.relayDC = RELAY_Read(RELAY_DC); 800cbea: 2003 movs r0, #3 800cbec: f7fc fcd0 bl 8009590 800cbf0: 4603 mov r3, r0 800cbf2: f003 0301 and.w r3, r3, #1 800cbf6: b2d9 uxtb r1, r3 800cbf8: 4a67 ldr r2, [pc, #412] @ (800cd98 ) 800cbfa: 7d53 ldrb r3, [r2, #21] 800cbfc: f361 0341 bfi r3, r1, #1, #1 800cc00: 7553 strb r3, [r2, #21] statusPacket.relayAUX = RELAY_Read(RELAY_AUX0); 800cc02: 2000 movs r0, #0 800cc04: f7fc fcc4 bl 8009590 800cc08: 4603 mov r3, r0 800cc0a: f003 0301 and.w r3, r3, #1 800cc0e: b2d9 uxtb r1, r3 800cc10: 4a61 ldr r2, [pc, #388] @ (800cd98 ) 800cc12: 7d53 ldrb r3, [r2, #21] 800cc14: f361 0382 bfi r3, r1, #2, #1 800cc18: 7553 strb r3, [r2, #21] statusPacket.lockState = 0; 800cc1a: 4a5f ldr r2, [pc, #380] @ (800cd98 ) 800cc1c: 7d53 ldrb r3, [r2, #21] 800cc1e: f023 0308 bic.w r3, r3, #8 800cc22: 7553 strb r3, [r2, #21] statusPacket.stopButton = !IN_ReadInput(IN_ESTOP); 800cc24: 2003 movs r0, #3 800cc26: f7fc fcc3 bl 80095b0 800cc2a: 4603 mov r3, r0 800cc2c: 2b00 cmp r3, #0 800cc2e: bf0c ite eq 800cc30: 2301 moveq r3, #1 800cc32: 2300 movne r3, #0 800cc34: b2d9 uxtb r1, r3 800cc36: 4a58 ldr r2, [pc, #352] @ (800cd98 ) 800cc38: 7d53 ldrb r3, [r2, #21] 800cc3a: f361 1304 bfi r3, r1, #4, #1 800cc3e: 7553 strb r3, [r2, #21] statusPacket.logAvailable = (debug_buffer_available()>0)?1:0; 800cc40: f7fd fba6 bl 800a390 800cc44: 4603 mov r3, r0 800cc46: 2b00 cmp r3, #0 800cc48: bf14 ite ne 800cc4a: 2301 movne r3, #1 800cc4c: 2300 moveq r3, #0 800cc4e: b2d9 uxtb r1, r3 800cc50: 4a51 ldr r2, [pc, #324] @ (800cd98 ) 800cc52: 7d53 ldrb r3, [r2, #21] 800cc54: f361 1345 bfi r3, r1, #5, #1 800cc58: 7553 strb r3, [r2, #21] statusPacket.evInfoAvailable = 0; 800cc5a: 4a4f ldr r2, [pc, #316] @ (800cd98 ) 800cc5c: 7d53 ldrb r3, [r2, #21] 800cc5e: f023 0340 bic.w r3, r3, #64 @ 0x40 800cc62: 7553 strb r3, [r2, #21] statusPacket.psuOnline = PSU0.online; 800cc64: 4b4d ldr r3, [pc, #308] @ (800cd9c ) 800cc66: 7a1b ldrb r3, [r3, #8] 800cc68: f003 0301 and.w r3, r3, #1 800cc6c: b2d9 uxtb r1, r3 800cc6e: 4a4a ldr r2, [pc, #296] @ (800cd98 ) 800cc70: 7d53 ldrb r3, [r2, #21] 800cc72: f361 13c7 bfi r3, r1, #7, #1 800cc76: 7553 strb r3, [r2, #21] statusPacket.tempConnector0 = CONN_ReadTemp(0); // температура коннектора 800cc78: 2000 movs r0, #0 800cc7a: f7fc fd8b bl 8009794 800cc7e: 4603 mov r3, r0 800cc80: b25a sxtb r2, r3 800cc82: 4b45 ldr r3, [pc, #276] @ (800cd98 ) 800cc84: 765a strb r2, [r3, #25] statusPacket.tempConnector1 = CONN_ReadTemp(1); 800cc86: 2001 movs r0, #1 800cc88: f7fc fd84 bl 8009794 800cc8c: 4603 mov r3, r0 800cc8e: b25a sxtb r2, r3 800cc90: 4b41 ldr r3, [pc, #260] @ (800cd98 ) 800cc92: 769a strb r2, [r3, #26] statusPacket.tempAmbient = PSU0.tempAmbient; // температура окружающего воздуха 800cc94: 4b41 ldr r3, [pc, #260] @ (800cd9c ) 800cc96: 69db ldr r3, [r3, #28] 800cc98: b25a sxtb r2, r3 800cc9a: 4b3f ldr r3, [pc, #252] @ (800cd98 ) 800cc9c: 76da strb r2, [r3, #27] statusPacket.tempBatteryMax = 0; 800cc9e: 4b3e ldr r3, [pc, #248] @ (800cd98 ) 800cca0: 2200 movs r2, #0 800cca2: 771a strb r2, [r3, #28] statusPacket.tempBatteryMin = 0; 800cca4: 4b3c ldr r3, [pc, #240] @ (800cd98 ) 800cca6: 2200 movs r2, #0 800cca8: 775a strb r2, [r3, #29] statusPacket.highestVoltageOfBatteryCell = 0; 800ccaa: 4b3b ldr r3, [pc, #236] @ (800cd98 ) 800ccac: 2200 movs r2, #0 800ccae: 779a strb r2, [r3, #30] 800ccb0: 2200 movs r2, #0 800ccb2: 77da strb r2, [r3, #31] statusPacket.batteryStatus = 0; 800ccb4: 4b38 ldr r3, [pc, #224] @ (800cd98 ) 800ccb6: 2200 movs r2, #0 800ccb8: f883 2020 strb.w r2, [r3, #32] statusPacket.phaseVoltageAB = PSU_06.VAB; 800ccbc: 4b38 ldr r3, [pc, #224] @ (800cda0 ) 800ccbe: 689b ldr r3, [r3, #8] 800ccc0: b29a uxth r2, r3 800ccc2: 4b35 ldr r3, [pc, #212] @ (800cd98 ) 800ccc4: f8a3 2021 strh.w r2, [r3, #33] @ 0x21 statusPacket.phaseVoltageBC = PSU_06.VBC; 800ccc8: 4b35 ldr r3, [pc, #212] @ (800cda0 ) 800ccca: 68db ldr r3, [r3, #12] 800cccc: b29a uxth r2, r3 800ccce: 4b32 ldr r3, [pc, #200] @ (800cd98 ) 800ccd0: f8a3 2023 strh.w r2, [r3, #35] @ 0x23 statusPacket.phaseVoltageCA = PSU_06.VCA; 800ccd4: 4b32 ldr r3, [pc, #200] @ (800cda0 ) 800ccd6: 691b ldr r3, [r3, #16] 800ccd8: b29a uxth r2, r3 800ccda: 4b2f ldr r3, [pc, #188] @ (800cd98 ) 800ccdc: f8a3 2025 strh.w r2, [r3, #37] @ 0x25 // GBT TODO memset(statusPacket.VIN, 0, sizeof(statusPacket.VIN)); 800cce0: 2211 movs r2, #17 800cce2: 2100 movs r1, #0 800cce4: 482f ldr r0, [pc, #188] @ (800cda4 ) 800cce6: f006 f9ab bl 8013040 // GBT TODO statusPacket.batteryType = 0; 800ccea: 4b2b ldr r3, [pc, #172] @ (800cd98 ) 800ccec: 2200 movs r2, #0 800ccee: f883 2038 strb.w r2, [r3, #56] @ 0x38 statusPacket.batteryCapacity = 0; 800ccf2: 4b29 ldr r3, [pc, #164] @ (800cd98 ) 800ccf4: 2200 movs r2, #0 800ccf6: f883 2039 strb.w r2, [r3, #57] @ 0x39 800ccfa: 2200 movs r2, #0 800ccfc: f883 203a strb.w r2, [r3, #58] @ 0x3a statusPacket.batteryVoltage = 0; 800cd00: 4b25 ldr r3, [pc, #148] @ (800cd98 ) 800cd02: 2200 movs r2, #0 800cd04: f883 203b strb.w r2, [r3, #59] @ 0x3b 800cd08: 2200 movs r2, #0 800cd0a: f883 203c strb.w r2, [r3, #60] @ 0x3c memset(statusPacket.batteryVendor, 0, sizeof(statusPacket.batteryVendor)); 800cd0e: 2204 movs r2, #4 800cd10: 2100 movs r1, #0 800cd12: 4825 ldr r0, [pc, #148] @ (800cda8 ) 800cd14: f006 f994 bl 8013040 statusPacket.batterySN = 0; 800cd18: 4b1f ldr r3, [pc, #124] @ (800cd98 ) 800cd1a: 2200 movs r2, #0 800cd1c: f883 2041 strb.w r2, [r3, #65] @ 0x41 800cd20: 2200 movs r2, #0 800cd22: f883 2042 strb.w r2, [r3, #66] @ 0x42 800cd26: 2200 movs r2, #0 800cd28: f883 2043 strb.w r2, [r3, #67] @ 0x43 800cd2c: 2200 movs r2, #0 800cd2e: f883 2044 strb.w r2, [r3, #68] @ 0x44 statusPacket.batteryManuD = 0; 800cd32: 4b19 ldr r3, [pc, #100] @ (800cd98 ) 800cd34: 2200 movs r2, #0 800cd36: f883 2047 strb.w r2, [r3, #71] @ 0x47 statusPacket.batteryManuM = 0; 800cd3a: 4b17 ldr r3, [pc, #92] @ (800cd98 ) 800cd3c: 2200 movs r2, #0 800cd3e: f883 2046 strb.w r2, [r3, #70] @ 0x46 statusPacket.batteryManuY = 0; 800cd42: 4b15 ldr r3, [pc, #84] @ (800cd98 ) 800cd44: 2200 movs r2, #0 800cd46: f883 2045 strb.w r2, [r3, #69] @ 0x45 statusPacket.batteryCycleCount = 0; 800cd4a: 4b13 ldr r3, [pc, #76] @ (800cd98 ) 800cd4c: 2200 movs r2, #0 800cd4e: f883 2048 strb.w r2, [r3, #72] @ 0x48 800cd52: 2200 movs r2, #0 800cd54: f883 2049 strb.w r2, [r3, #73] @ 0x49 statusPacket.ownAuto = 0; 800cd58: 4b0f ldr r3, [pc, #60] @ (800cd98 ) 800cd5a: 2200 movs r2, #0 800cd5c: f883 204a strb.w r2, [r3, #74] @ 0x4a memset(statusPacket.EV_SW_VER, 0, sizeof(statusPacket.EV_SW_VER)); 800cd60: 2208 movs r2, #8 800cd62: 2100 movs r1, #0 800cd64: 4811 ldr r0, [pc, #68] @ (800cdac ) 800cd66: f006 f96b bl 8013040 statusPacket.testMode = 0; 800cd6a: 4b0b ldr r3, [pc, #44] @ (800cd98 ) 800cd6c: 2200 movs r2, #0 800cd6e: f883 2053 strb.w r2, [r3, #83] @ 0x53 statusPacket.testVoltage = 0; 800cd72: 4b09 ldr r3, [pc, #36] @ (800cd98 ) 800cd74: 2200 movs r2, #0 800cd76: f883 2054 strb.w r2, [r3, #84] @ 0x54 800cd7a: 2200 movs r2, #0 800cd7c: f883 2055 strb.w r2, [r3, #85] @ 0x55 statusPacket.testCurrent = 0; 800cd80: 4b05 ldr r3, [pc, #20] @ (800cd98 ) 800cd82: 2200 movs r2, #0 800cd84: f883 2056 strb.w r2, [r3, #86] @ 0x56 800cd88: 2200 movs r2, #0 800cd8a: f883 2057 strb.w r2, [r3, #87] @ 0x57 // В debug.c есть CONN_SetState, предполагаем наличие CONN_GetState() // Если такой функции нет, закомментируйте следующую строку: // statusPacket.connState = CONN_GetState(); } 800cd8e: bf00 nop 800cd90: bd80 pop {r7, pc} 800cd92: bf00 nop 800cd94: 200001d4 .word 0x200001d4 800cd98: 20000e60 .word 0x20000e60 800cd9c: 20000724 .word 0x20000724 800cda0: 200006f8 .word 0x200006f8 800cda4: 20000e87 .word 0x20000e87 800cda8: 20000e9d .word 0x20000e9d 800cdac: 20000eab .word 0x20000eab 0800cdb0 : #include "sma_filter.h" void SMAFilter_Init(SMAFilter_t* f) { 800cdb0: b480 push {r7} 800cdb2: b085 sub sp, #20 800cdb4: af00 add r7, sp, #0 800cdb6: 6078 str r0, [r7, #4] if (f == 0) return; 800cdb8: 687b ldr r3, [r7, #4] 800cdba: 2b00 cmp r3, #0 800cdbc: d018 beq.n 800cdf0 f->sum = 0; 800cdbe: 687b ldr r3, [r7, #4] 800cdc0: 2200 movs r2, #0 800cdc2: 601a str r2, [r3, #0] f->idx = 0; 800cdc4: 687b ldr r3, [r7, #4] 800cdc6: 2200 movs r2, #0 800cdc8: 809a strh r2, [r3, #4] f->count = 0; 800cdca: 687b ldr r3, [r7, #4] 800cdcc: 2200 movs r2, #0 800cdce: 80da strh r2, [r3, #6] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800cdd0: 2300 movs r3, #0 800cdd2: 81fb strh r3, [r7, #14] 800cdd4: e008 b.n 800cde8 f->buffer[i] = 0; 800cdd6: 89fa ldrh r2, [r7, #14] 800cdd8: 687b ldr r3, [r7, #4] 800cdda: 3202 adds r2, #2 800cddc: 2100 movs r1, #0 800cdde: f843 1022 str.w r1, [r3, r2, lsl #2] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800cde2: 89fb ldrh r3, [r7, #14] 800cde4: 3301 adds r3, #1 800cde6: 81fb strh r3, [r7, #14] 800cde8: 89fb ldrh r3, [r7, #14] 800cdea: 2b07 cmp r3, #7 800cdec: d9f3 bls.n 800cdd6 800cdee: e000 b.n 800cdf2 if (f == 0) return; 800cdf0: bf00 nop } } 800cdf2: 3714 adds r7, #20 800cdf4: 46bd mov sp, r7 800cdf6: bc80 pop {r7} 800cdf8: 4770 bx lr 0800cdfa : int32_t SMAFilter_Update(SMAFilter_t* f, int32_t x) { 800cdfa: b480 push {r7} 800cdfc: b085 sub sp, #20 800cdfe: af00 add r7, sp, #0 800ce00: 6078 str r0, [r7, #4] 800ce02: 6039 str r1, [r7, #0] if (f == 0) return x; 800ce04: 687b ldr r3, [r7, #4] 800ce06: 2b00 cmp r3, #0 800ce08: d101 bne.n 800ce0e 800ce0a: 683b ldr r3, [r7, #0] 800ce0c: e056 b.n 800cebc // Пока окно не заполнено полностью, делим по фактическому count. if (f->count < SMA_FILTER_WINDOW) { 800ce0e: 687b ldr r3, [r7, #4] 800ce10: 88db ldrh r3, [r3, #6] 800ce12: 2b07 cmp r3, #7 800ce14: d827 bhi.n 800ce66 f->buffer[f->idx] = x; 800ce16: 687b ldr r3, [r7, #4] 800ce18: 889b ldrh r3, [r3, #4] 800ce1a: 461a mov r2, r3 800ce1c: 687b ldr r3, [r7, #4] 800ce1e: 3202 adds r2, #2 800ce20: 6839 ldr r1, [r7, #0] 800ce22: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += x; 800ce26: 687b ldr r3, [r7, #4] 800ce28: 681a ldr r2, [r3, #0] 800ce2a: 683b ldr r3, [r7, #0] 800ce2c: 441a add r2, r3 800ce2e: 687b ldr r3, [r7, #4] 800ce30: 601a str r2, [r3, #0] f->idx++; 800ce32: 687b ldr r3, [r7, #4] 800ce34: 889b ldrh r3, [r3, #4] 800ce36: 3301 adds r3, #1 800ce38: b29a uxth r2, r3 800ce3a: 687b ldr r3, [r7, #4] 800ce3c: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800ce3e: 687b ldr r3, [r7, #4] 800ce40: 889b ldrh r3, [r3, #4] 800ce42: 2b07 cmp r3, #7 800ce44: d902 bls.n 800ce4c 800ce46: 687b ldr r3, [r7, #4] 800ce48: 2200 movs r2, #0 800ce4a: 809a strh r2, [r3, #4] f->count++; 800ce4c: 687b ldr r3, [r7, #4] 800ce4e: 88db ldrh r3, [r3, #6] 800ce50: 3301 adds r3, #1 800ce52: b29a uxth r2, r3 800ce54: 687b ldr r3, [r7, #4] 800ce56: 80da strh r2, [r3, #6] return (int32_t)(f->sum / (int32_t)f->count); 800ce58: 687b ldr r3, [r7, #4] 800ce5a: 681b ldr r3, [r3, #0] 800ce5c: 687a ldr r2, [r7, #4] 800ce5e: 88d2 ldrh r2, [r2, #6] 800ce60: fb93 f3f2 sdiv r3, r3, r2 800ce64: e02a b.n 800cebc } // Окно заполнено: "вычитаем старое + добавляем новое". int32_t old = f->buffer[f->idx]; 800ce66: 687b ldr r3, [r7, #4] 800ce68: 889b ldrh r3, [r3, #4] 800ce6a: 461a mov r2, r3 800ce6c: 687b ldr r3, [r7, #4] 800ce6e: 3202 adds r2, #2 800ce70: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800ce74: 60fb str r3, [r7, #12] f->buffer[f->idx] = x; 800ce76: 687b ldr r3, [r7, #4] 800ce78: 889b ldrh r3, [r3, #4] 800ce7a: 461a mov r2, r3 800ce7c: 687b ldr r3, [r7, #4] 800ce7e: 3202 adds r2, #2 800ce80: 6839 ldr r1, [r7, #0] 800ce82: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += (x - old); 800ce86: 687b ldr r3, [r7, #4] 800ce88: 681a ldr r2, [r3, #0] 800ce8a: 6839 ldr r1, [r7, #0] 800ce8c: 68fb ldr r3, [r7, #12] 800ce8e: 1acb subs r3, r1, r3 800ce90: 441a add r2, r3 800ce92: 687b ldr r3, [r7, #4] 800ce94: 601a str r2, [r3, #0] f->idx++; 800ce96: 687b ldr r3, [r7, #4] 800ce98: 889b ldrh r3, [r3, #4] 800ce9a: 3301 adds r3, #1 800ce9c: b29a uxth r2, r3 800ce9e: 687b ldr r3, [r7, #4] 800cea0: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800cea2: 687b ldr r3, [r7, #4] 800cea4: 889b ldrh r3, [r3, #4] 800cea6: 2b07 cmp r3, #7 800cea8: d902 bls.n 800ceb0 800ceaa: 687b ldr r3, [r7, #4] 800ceac: 2200 movs r2, #0 800ceae: 809a strh r2, [r3, #4] return (int32_t)(f->sum / (int32_t)SMA_FILTER_WINDOW); 800ceb0: 687b ldr r3, [r7, #4] 800ceb2: 681b ldr r3, [r3, #0] 800ceb4: 2b00 cmp r3, #0 800ceb6: da00 bge.n 800ceba 800ceb8: 3307 adds r3, #7 800ceba: 10db asrs r3, r3, #3 } 800cebc: 4618 mov r0, r3 800cebe: 3714 adds r7, #20 800cec0: 46bd mov sp, r7 800cec2: bc80 pop {r7} 800cec4: 4770 bx lr ... 0800cec8 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800cec8: b480 push {r7} 800ceca: b085 sub sp, #20 800cecc: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 800cece: 4b15 ldr r3, [pc, #84] @ (800cf24 ) 800ced0: 699b ldr r3, [r3, #24] 800ced2: 4a14 ldr r2, [pc, #80] @ (800cf24 ) 800ced4: f043 0301 orr.w r3, r3, #1 800ced8: 6193 str r3, [r2, #24] 800ceda: 4b12 ldr r3, [pc, #72] @ (800cf24 ) 800cedc: 699b ldr r3, [r3, #24] 800cede: f003 0301 and.w r3, r3, #1 800cee2: 60bb str r3, [r7, #8] 800cee4: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800cee6: 4b0f ldr r3, [pc, #60] @ (800cf24 ) 800cee8: 69db ldr r3, [r3, #28] 800ceea: 4a0e ldr r2, [pc, #56] @ (800cf24 ) 800ceec: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800cef0: 61d3 str r3, [r2, #28] 800cef2: 4b0c ldr r3, [pc, #48] @ (800cf24 ) 800cef4: 69db ldr r3, [r3, #28] 800cef6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800cefa: 607b str r3, [r7, #4] 800cefc: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 800cefe: 4b0a ldr r3, [pc, #40] @ (800cf28 ) 800cf00: 685b ldr r3, [r3, #4] 800cf02: 60fb str r3, [r7, #12] 800cf04: 68fb ldr r3, [r7, #12] 800cf06: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 800cf0a: 60fb str r3, [r7, #12] 800cf0c: 68fb ldr r3, [r7, #12] 800cf0e: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 800cf12: 60fb str r3, [r7, #12] 800cf14: 4a04 ldr r2, [pc, #16] @ (800cf28 ) 800cf16: 68fb ldr r3, [r7, #12] 800cf18: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800cf1a: bf00 nop 800cf1c: 3714 adds r7, #20 800cf1e: 46bd mov sp, r7 800cf20: bc80 pop {r7} 800cf22: 4770 bx lr 800cf24: 40021000 .word 0x40021000 800cf28: 40010000 .word 0x40010000 0800cf2c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 800cf2c: b480 push {r7} 800cf2e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800cf30: bf00 nop 800cf32: e7fd b.n 800cf30 0800cf34 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800cf34: b480 push {r7} 800cf36: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800cf38: bf00 nop 800cf3a: e7fd b.n 800cf38 0800cf3c : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 800cf3c: b480 push {r7} 800cf3e: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800cf40: bf00 nop 800cf42: e7fd b.n 800cf40 0800cf44 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 800cf44: b480 push {r7} 800cf46: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800cf48: bf00 nop 800cf4a: e7fd b.n 800cf48 0800cf4c : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 800cf4c: b480 push {r7} 800cf4e: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 800cf50: bf00 nop 800cf52: e7fd b.n 800cf50 0800cf54 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 800cf54: b480 push {r7} 800cf56: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800cf58: bf00 nop 800cf5a: 46bd mov sp, r7 800cf5c: bc80 pop {r7} 800cf5e: 4770 bx lr 0800cf60 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 800cf60: b480 push {r7} 800cf62: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800cf64: bf00 nop 800cf66: 46bd mov sp, r7 800cf68: bc80 pop {r7} 800cf6a: 4770 bx lr 0800cf6c : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800cf6c: b480 push {r7} 800cf6e: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800cf70: bf00 nop 800cf72: 46bd mov sp, r7 800cf74: bc80 pop {r7} 800cf76: 4770 bx lr 0800cf78 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800cf78: b580 push {r7, lr} 800cf7a: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800cf7c: f000 fcdc bl 800d938 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 800cf80: bf00 nop 800cf82: bd80 pop {r7, pc} 0800cf84 : /** * @brief This function handles CAN1 RX0 interrupt. */ void CAN1_RX0_IRQHandler(void) { 800cf84: b580 push {r7, lr} 800cf86: af00 add r7, sp, #0 /* USER CODE BEGIN CAN1_RX0_IRQn 0 */ /* USER CODE END CAN1_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan1); 800cf88: 4802 ldr r0, [pc, #8] @ (800cf94 ) 800cf8a: f001 fecd bl 800ed28 /* USER CODE BEGIN CAN1_RX0_IRQn 1 */ /* USER CODE END CAN1_RX0_IRQn 1 */ } 800cf8e: bf00 nop 800cf90: bd80 pop {r7, pc} 800cf92: bf00 nop 800cf94: 20000180 .word 0x20000180 0800cf98 : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 800cf98: b580 push {r7, lr} 800cf9a: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_IRQn 0 */ /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 800cf9c: 4802 ldr r0, [pc, #8] @ (800cfa8 ) 800cf9e: f004 f8c3 bl 8011128 /* USER CODE BEGIN TIM3_IRQn 1 */ /* USER CODE END TIM3_IRQn 1 */ } 800cfa2: bf00 nop 800cfa4: bd80 pop {r7, pc} 800cfa6: bf00 nop 800cfa8: 20000ec8 .word 0x20000ec8 0800cfac : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 800cfac: b580 push {r7, lr} 800cfae: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 800cfb0: 4802 ldr r0, [pc, #8] @ (800cfbc ) 800cfb2: f005 f90b bl 80121cc /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 800cfb6: bf00 nop 800cfb8: bd80 pop {r7, pc} 800cfba: bf00 nop 800cfbc: 20000fa0 .word 0x20000fa0 0800cfc0 : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 800cfc0: b580 push {r7, lr} 800cfc2: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 800cfc4: 4802 ldr r0, [pc, #8] @ (800cfd0 ) 800cfc6: f005 f901 bl 80121cc /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 800cfca: bf00 nop 800cfcc: bd80 pop {r7, pc} 800cfce: bf00 nop 800cfd0: 20000fe8 .word 0x20000fe8 0800cfd4 : /** * @brief This function handles USART3 global interrupt. */ void USART3_IRQHandler(void) { 800cfd4: b580 push {r7, lr} 800cfd6: af00 add r7, sp, #0 /* USER CODE BEGIN USART3_IRQn 0 */ /* USER CODE END USART3_IRQn 0 */ HAL_UART_IRQHandler(&huart3); 800cfd8: 4802 ldr r0, [pc, #8] @ (800cfe4 ) 800cfda: f005 f8f7 bl 80121cc /* USER CODE BEGIN USART3_IRQn 1 */ /* USER CODE END USART3_IRQn 1 */ } 800cfde: bf00 nop 800cfe0: bd80 pop {r7, pc} 800cfe2: bf00 nop 800cfe4: 20001030 .word 0x20001030 0800cfe8 : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 800cfe8: b580 push {r7, lr} 800cfea: af00 add r7, sp, #0 /* USER CODE BEGIN UART5_IRQn 0 */ /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 800cfec: 4802 ldr r0, [pc, #8] @ (800cff8 ) 800cfee: f005 f8ed bl 80121cc /* USER CODE BEGIN UART5_IRQn 1 */ /* USER CODE END UART5_IRQn 1 */ } 800cff2: bf00 nop 800cff4: bd80 pop {r7, pc} 800cff6: bf00 nop 800cff8: 20000f58 .word 0x20000f58 0800cffc : /** * @brief This function handles CAN2 TX interrupt. */ void CAN2_TX_IRQHandler(void) { 800cffc: b580 push {r7, lr} 800cffe: af00 add r7, sp, #0 /* USER CODE BEGIN CAN2_TX_IRQn 0 */ /* USER CODE END CAN2_TX_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800d000: 4802 ldr r0, [pc, #8] @ (800d00c ) 800d002: f001 fe91 bl 800ed28 /* USER CODE BEGIN CAN2_TX_IRQn 1 */ /* USER CODE END CAN2_TX_IRQn 1 */ } 800d006: bf00 nop 800d008: bd80 pop {r7, pc} 800d00a: bf00 nop 800d00c: 200001a8 .word 0x200001a8 0800d010 : /** * @brief This function handles CAN2 RX1 interrupt. */ void CAN2_RX1_IRQHandler(void) { 800d010: b580 push {r7, lr} 800d012: af00 add r7, sp, #0 /* USER CODE BEGIN CAN2_RX1_IRQn 0 */ /* USER CODE END CAN2_RX1_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800d014: 4802 ldr r0, [pc, #8] @ (800d020 ) 800d016: f001 fe87 bl 800ed28 /* USER CODE BEGIN CAN2_RX1_IRQn 1 */ /* USER CODE END CAN2_RX1_IRQn 1 */ } 800d01a: bf00 nop 800d01c: bd80 pop {r7, pc} 800d01e: bf00 nop 800d020: 200001a8 .word 0x200001a8 0800d024 <_read>: _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { 800d024: b580 push {r7, lr} 800d026: b086 sub sp, #24 800d028: af00 add r7, sp, #0 800d02a: 60f8 str r0, [r7, #12] 800d02c: 60b9 str r1, [r7, #8] 800d02e: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800d030: 2300 movs r3, #0 800d032: 617b str r3, [r7, #20] 800d034: e00a b.n 800d04c <_read+0x28> { *ptr++ = __io_getchar(); 800d036: f3af 8000 nop.w 800d03a: 4601 mov r1, r0 800d03c: 68bb ldr r3, [r7, #8] 800d03e: 1c5a adds r2, r3, #1 800d040: 60ba str r2, [r7, #8] 800d042: b2ca uxtb r2, r1 800d044: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 800d046: 697b ldr r3, [r7, #20] 800d048: 3301 adds r3, #1 800d04a: 617b str r3, [r7, #20] 800d04c: 697a ldr r2, [r7, #20] 800d04e: 687b ldr r3, [r7, #4] 800d050: 429a cmp r2, r3 800d052: dbf0 blt.n 800d036 <_read+0x12> } return len; 800d054: 687b ldr r3, [r7, #4] } 800d056: 4618 mov r0, r3 800d058: 3718 adds r7, #24 800d05a: 46bd mov sp, r7 800d05c: bd80 pop {r7, pc} 0800d05e <_close>: } return len; } int _close(int file) { 800d05e: b480 push {r7} 800d060: b083 sub sp, #12 800d062: af00 add r7, sp, #0 800d064: 6078 str r0, [r7, #4] (void)file; return -1; 800d066: f04f 33ff mov.w r3, #4294967295 } 800d06a: 4618 mov r0, r3 800d06c: 370c adds r7, #12 800d06e: 46bd mov sp, r7 800d070: bc80 pop {r7} 800d072: 4770 bx lr 0800d074 <_fstat>: int _fstat(int file, struct stat *st) { 800d074: b480 push {r7} 800d076: b083 sub sp, #12 800d078: af00 add r7, sp, #0 800d07a: 6078 str r0, [r7, #4] 800d07c: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 800d07e: 683b ldr r3, [r7, #0] 800d080: f44f 5200 mov.w r2, #8192 @ 0x2000 800d084: 605a str r2, [r3, #4] return 0; 800d086: 2300 movs r3, #0 } 800d088: 4618 mov r0, r3 800d08a: 370c adds r7, #12 800d08c: 46bd mov sp, r7 800d08e: bc80 pop {r7} 800d090: 4770 bx lr 0800d092 <_isatty>: int _isatty(int file) { 800d092: b480 push {r7} 800d094: b083 sub sp, #12 800d096: af00 add r7, sp, #0 800d098: 6078 str r0, [r7, #4] (void)file; return 1; 800d09a: 2301 movs r3, #1 } 800d09c: 4618 mov r0, r3 800d09e: 370c adds r7, #12 800d0a0: 46bd mov sp, r7 800d0a2: bc80 pop {r7} 800d0a4: 4770 bx lr 0800d0a6 <_lseek>: int _lseek(int file, int ptr, int dir) { 800d0a6: b480 push {r7} 800d0a8: b085 sub sp, #20 800d0aa: af00 add r7, sp, #0 800d0ac: 60f8 str r0, [r7, #12] 800d0ae: 60b9 str r1, [r7, #8] 800d0b0: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 800d0b2: 2300 movs r3, #0 } 800d0b4: 4618 mov r0, r3 800d0b6: 3714 adds r7, #20 800d0b8: 46bd mov sp, r7 800d0ba: bc80 pop {r7} 800d0bc: 4770 bx lr ... 0800d0c0 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 800d0c0: b580 push {r7, lr} 800d0c2: b086 sub sp, #24 800d0c4: af00 add r7, sp, #0 800d0c6: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 800d0c8: 4a14 ldr r2, [pc, #80] @ (800d11c <_sbrk+0x5c>) 800d0ca: 4b15 ldr r3, [pc, #84] @ (800d120 <_sbrk+0x60>) 800d0cc: 1ad3 subs r3, r2, r3 800d0ce: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 800d0d0: 697b ldr r3, [r7, #20] 800d0d2: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 800d0d4: 4b13 ldr r3, [pc, #76] @ (800d124 <_sbrk+0x64>) 800d0d6: 681b ldr r3, [r3, #0] 800d0d8: 2b00 cmp r3, #0 800d0da: d102 bne.n 800d0e2 <_sbrk+0x22> { __sbrk_heap_end = &_end; 800d0dc: 4b11 ldr r3, [pc, #68] @ (800d124 <_sbrk+0x64>) 800d0de: 4a12 ldr r2, [pc, #72] @ (800d128 <_sbrk+0x68>) 800d0e0: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 800d0e2: 4b10 ldr r3, [pc, #64] @ (800d124 <_sbrk+0x64>) 800d0e4: 681a ldr r2, [r3, #0] 800d0e6: 687b ldr r3, [r7, #4] 800d0e8: 4413 add r3, r2 800d0ea: 693a ldr r2, [r7, #16] 800d0ec: 429a cmp r2, r3 800d0ee: d207 bcs.n 800d100 <_sbrk+0x40> { errno = ENOMEM; 800d0f0: f005 fff4 bl 80130dc <__errno> 800d0f4: 4603 mov r3, r0 800d0f6: 220c movs r2, #12 800d0f8: 601a str r2, [r3, #0] return (void *)-1; 800d0fa: f04f 33ff mov.w r3, #4294967295 800d0fe: e009 b.n 800d114 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 800d100: 4b08 ldr r3, [pc, #32] @ (800d124 <_sbrk+0x64>) 800d102: 681b ldr r3, [r3, #0] 800d104: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 800d106: 4b07 ldr r3, [pc, #28] @ (800d124 <_sbrk+0x64>) 800d108: 681a ldr r2, [r3, #0] 800d10a: 687b ldr r3, [r7, #4] 800d10c: 4413 add r3, r2 800d10e: 4a05 ldr r2, [pc, #20] @ (800d124 <_sbrk+0x64>) 800d110: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 800d112: 68fb ldr r3, [r7, #12] } 800d114: 4618 mov r0, r3 800d116: 3718 adds r7, #24 800d118: 46bd mov sp, r7 800d11a: bd80 pop {r7, pc} 800d11c: 20010000 .word 0x20010000 800d120: 00000400 .word 0x00000400 800d124: 20000ec4 .word 0x20000ec4 800d128: 200011c8 .word 0x200011c8 0800d12c : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 800d12c: b480 push {r7} 800d12e: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 800d130: bf00 nop 800d132: 46bd mov sp, r7 800d134: bc80 pop {r7} 800d136: 4770 bx lr 0800d138 : TIM_HandleTypeDef htim3; TIM_HandleTypeDef htim4; /* TIM3 init function */ void MX_TIM3_Init(void) { 800d138: b580 push {r7, lr} 800d13a: b08e sub sp, #56 @ 0x38 800d13c: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800d13e: f107 0328 add.w r3, r7, #40 @ 0x28 800d142: 2200 movs r2, #0 800d144: 601a str r2, [r3, #0] 800d146: 605a str r2, [r3, #4] 800d148: 609a str r2, [r3, #8] 800d14a: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800d14c: f107 0320 add.w r3, r7, #32 800d150: 2200 movs r2, #0 800d152: 601a str r2, [r3, #0] 800d154: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800d156: 1d3b adds r3, r7, #4 800d158: 2200 movs r2, #0 800d15a: 601a str r2, [r3, #0] 800d15c: 605a str r2, [r3, #4] 800d15e: 609a str r2, [r3, #8] 800d160: 60da str r2, [r3, #12] 800d162: 611a str r2, [r3, #16] 800d164: 615a str r2, [r3, #20] 800d166: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 800d168: 4b2c ldr r3, [pc, #176] @ (800d21c ) 800d16a: 4a2d ldr r2, [pc, #180] @ (800d220 ) 800d16c: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 800d16e: 4b2b ldr r3, [pc, #172] @ (800d21c ) 800d170: 2200 movs r2, #0 800d172: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 800d174: 4b29 ldr r3, [pc, #164] @ (800d21c ) 800d176: 2200 movs r2, #0 800d178: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 800d17a: 4b28 ldr r3, [pc, #160] @ (800d21c ) 800d17c: f64f 72ff movw r2, #65535 @ 0xffff 800d180: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800d182: 4b26 ldr r3, [pc, #152] @ (800d21c ) 800d184: 2200 movs r2, #0 800d186: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800d188: 4b24 ldr r3, [pc, #144] @ (800d21c ) 800d18a: 2200 movs r2, #0 800d18c: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 800d18e: 4823 ldr r0, [pc, #140] @ (800d21c ) 800d190: f003 fd83 bl 8010c9a 800d194: 4603 mov r3, r0 800d196: 2b00 cmp r3, #0 800d198: d001 beq.n 800d19e { Error_Handler(); 800d19a: f7fd fc2f bl 800a9fc } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800d19e: f44f 5380 mov.w r3, #4096 @ 0x1000 800d1a2: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 800d1a4: f107 0328 add.w r3, r7, #40 @ 0x28 800d1a8: 4619 mov r1, r3 800d1aa: 481c ldr r0, [pc, #112] @ (800d21c ) 800d1ac: f004 f96e bl 801148c 800d1b0: 4603 mov r3, r0 800d1b2: 2b00 cmp r3, #0 800d1b4: d001 beq.n 800d1ba { Error_Handler(); 800d1b6: f7fd fc21 bl 800a9fc } if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 800d1ba: 4818 ldr r0, [pc, #96] @ (800d21c ) 800d1bc: f003 feb2 bl 8010f24 800d1c0: 4603 mov r3, r0 800d1c2: 2b00 cmp r3, #0 800d1c4: d001 beq.n 800d1ca { Error_Handler(); 800d1c6: f7fd fc19 bl 800a9fc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800d1ca: 2300 movs r3, #0 800d1cc: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800d1ce: 2300 movs r3, #0 800d1d0: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800d1d2: f107 0320 add.w r3, r7, #32 800d1d6: 4619 mov r1, r3 800d1d8: 4810 ldr r0, [pc, #64] @ (800d21c ) 800d1da: f004 fcfd bl 8011bd8 800d1de: 4603 mov r3, r0 800d1e0: 2b00 cmp r3, #0 800d1e2: d001 beq.n 800d1e8 { Error_Handler(); 800d1e4: f7fd fc0a bl 800a9fc } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800d1e8: 2360 movs r3, #96 @ 0x60 800d1ea: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800d1ec: 2300 movs r3, #0 800d1ee: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800d1f0: 2300 movs r3, #0 800d1f2: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800d1f4: 2300 movs r3, #0 800d1f6: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800d1f8: 1d3b adds r3, r7, #4 800d1fa: 2204 movs r2, #4 800d1fc: 4619 mov r1, r3 800d1fe: 4807 ldr r0, [pc, #28] @ (800d21c ) 800d200: f004 f882 bl 8011308 800d204: 4603 mov r3, r0 800d206: 2b00 cmp r3, #0 800d208: d001 beq.n 800d20e { Error_Handler(); 800d20a: f7fd fbf7 bl 800a9fc } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 800d20e: 4803 ldr r0, [pc, #12] @ (800d21c ) 800d210: f000 f8ce bl 800d3b0 } 800d214: bf00 nop 800d216: 3738 adds r7, #56 @ 0x38 800d218: 46bd mov sp, r7 800d21a: bd80 pop {r7, pc} 800d21c: 20000ec8 .word 0x20000ec8 800d220: 40000400 .word 0x40000400 0800d224 : /* TIM4 init function */ void MX_TIM4_Init(void) { 800d224: b580 push {r7, lr} 800d226: b08e sub sp, #56 @ 0x38 800d228: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800d22a: f107 0328 add.w r3, r7, #40 @ 0x28 800d22e: 2200 movs r2, #0 800d230: 601a str r2, [r3, #0] 800d232: 605a str r2, [r3, #4] 800d234: 609a str r2, [r3, #8] 800d236: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800d238: f107 0320 add.w r3, r7, #32 800d23c: 2200 movs r2, #0 800d23e: 601a str r2, [r3, #0] 800d240: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800d242: 1d3b adds r3, r7, #4 800d244: 2200 movs r2, #0 800d246: 601a str r2, [r3, #0] 800d248: 605a str r2, [r3, #4] 800d24a: 609a str r2, [r3, #8] 800d24c: 60da str r2, [r3, #12] 800d24e: 611a str r2, [r3, #16] 800d250: 615a str r2, [r3, #20] 800d252: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM4_Init 1 */ /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; 800d254: 4b37 ldr r3, [pc, #220] @ (800d334 ) 800d256: 4a38 ldr r2, [pc, #224] @ (800d338 ) 800d258: 601a str r2, [r3, #0] htim4.Init.Prescaler = 720; 800d25a: 4b36 ldr r3, [pc, #216] @ (800d334 ) 800d25c: f44f 7234 mov.w r2, #720 @ 0x2d0 800d260: 605a str r2, [r3, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 800d262: 4b34 ldr r3, [pc, #208] @ (800d334 ) 800d264: 2200 movs r2, #0 800d266: 609a str r2, [r3, #8] htim4.Init.Period = 100; 800d268: 4b32 ldr r3, [pc, #200] @ (800d334 ) 800d26a: 2264 movs r2, #100 @ 0x64 800d26c: 60da str r2, [r3, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800d26e: 4b31 ldr r3, [pc, #196] @ (800d334 ) 800d270: 2200 movs r2, #0 800d272: 611a str r2, [r3, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800d274: 4b2f ldr r3, [pc, #188] @ (800d334 ) 800d276: 2200 movs r2, #0 800d278: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 800d27a: 482e ldr r0, [pc, #184] @ (800d334 ) 800d27c: f003 fd0d bl 8010c9a 800d280: 4603 mov r3, r0 800d282: 2b00 cmp r3, #0 800d284: d001 beq.n 800d28a { Error_Handler(); 800d286: f7fd fbb9 bl 800a9fc } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800d28a: f44f 5380 mov.w r3, #4096 @ 0x1000 800d28e: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 800d290: f107 0328 add.w r3, r7, #40 @ 0x28 800d294: 4619 mov r1, r3 800d296: 4827 ldr r0, [pc, #156] @ (800d334 ) 800d298: f004 f8f8 bl 801148c 800d29c: 4603 mov r3, r0 800d29e: 2b00 cmp r3, #0 800d2a0: d001 beq.n 800d2a6 { Error_Handler(); 800d2a2: f7fd fbab bl 800a9fc } if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) 800d2a6: 4823 ldr r0, [pc, #140] @ (800d334 ) 800d2a8: f003 fe3c bl 8010f24 800d2ac: 4603 mov r3, r0 800d2ae: 2b00 cmp r3, #0 800d2b0: d001 beq.n 800d2b6 { Error_Handler(); 800d2b2: f7fd fba3 bl 800a9fc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800d2b6: 2300 movs r3, #0 800d2b8: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800d2ba: 2300 movs r3, #0 800d2bc: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 800d2be: f107 0320 add.w r3, r7, #32 800d2c2: 4619 mov r1, r3 800d2c4: 481b ldr r0, [pc, #108] @ (800d334 ) 800d2c6: f004 fc87 bl 8011bd8 800d2ca: 4603 mov r3, r0 800d2cc: 2b00 cmp r3, #0 800d2ce: d001 beq.n 800d2d4 { Error_Handler(); 800d2d0: f7fd fb94 bl 800a9fc } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800d2d4: 2360 movs r3, #96 @ 0x60 800d2d6: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800d2d8: 2300 movs r3, #0 800d2da: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800d2dc: 2300 movs r3, #0 800d2de: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800d2e0: 2300 movs r3, #0 800d2e2: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800d2e4: 1d3b adds r3, r7, #4 800d2e6: 2204 movs r2, #4 800d2e8: 4619 mov r1, r3 800d2ea: 4812 ldr r0, [pc, #72] @ (800d334 ) 800d2ec: f004 f80c bl 8011308 800d2f0: 4603 mov r3, r0 800d2f2: 2b00 cmp r3, #0 800d2f4: d001 beq.n 800d2fa { Error_Handler(); 800d2f6: f7fd fb81 bl 800a9fc } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 800d2fa: 1d3b adds r3, r7, #4 800d2fc: 2208 movs r2, #8 800d2fe: 4619 mov r1, r3 800d300: 480c ldr r0, [pc, #48] @ (800d334 ) 800d302: f004 f801 bl 8011308 800d306: 4603 mov r3, r0 800d308: 2b00 cmp r3, #0 800d30a: d001 beq.n 800d310 { Error_Handler(); 800d30c: f7fd fb76 bl 800a9fc } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 800d310: 1d3b adds r3, r7, #4 800d312: 220c movs r2, #12 800d314: 4619 mov r1, r3 800d316: 4807 ldr r0, [pc, #28] @ (800d334 ) 800d318: f003 fff6 bl 8011308 800d31c: 4603 mov r3, r0 800d31e: 2b00 cmp r3, #0 800d320: d001 beq.n 800d326 { Error_Handler(); 800d322: f7fd fb6b bl 800a9fc } /* USER CODE BEGIN TIM4_Init 2 */ /* USER CODE END TIM4_Init 2 */ HAL_TIM_MspPostInit(&htim4); 800d326: 4803 ldr r0, [pc, #12] @ (800d334 ) 800d328: f000 f842 bl 800d3b0 } 800d32c: bf00 nop 800d32e: 3738 adds r7, #56 @ 0x38 800d330: 46bd mov sp, r7 800d332: bd80 pop {r7, pc} 800d334: 20000f10 .word 0x20000f10 800d338: 40000800 .word 0x40000800 0800d33c : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 800d33c: b580 push {r7, lr} 800d33e: b084 sub sp, #16 800d340: af00 add r7, sp, #0 800d342: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM3) 800d344: 687b ldr r3, [r7, #4] 800d346: 681b ldr r3, [r3, #0] 800d348: 4a16 ldr r2, [pc, #88] @ (800d3a4 ) 800d34a: 4293 cmp r3, r2 800d34c: d114 bne.n 800d378 { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 800d34e: 4b16 ldr r3, [pc, #88] @ (800d3a8 ) 800d350: 69db ldr r3, [r3, #28] 800d352: 4a15 ldr r2, [pc, #84] @ (800d3a8 ) 800d354: f043 0302 orr.w r3, r3, #2 800d358: 61d3 str r3, [r2, #28] 800d35a: 4b13 ldr r3, [pc, #76] @ (800d3a8 ) 800d35c: 69db ldr r3, [r3, #28] 800d35e: f003 0302 and.w r3, r3, #2 800d362: 60fb str r3, [r7, #12] 800d364: 68fb ldr r3, [r7, #12] /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); 800d366: 2200 movs r2, #0 800d368: 2100 movs r1, #0 800d36a: 201d movs r0, #29 800d36c: f001 ffd7 bl 800f31e HAL_NVIC_EnableIRQ(TIM3_IRQn); 800d370: 201d movs r0, #29 800d372: f001 fff0 bl 800f356 __HAL_RCC_TIM4_CLK_ENABLE(); /* USER CODE BEGIN TIM4_MspInit 1 */ /* USER CODE END TIM4_MspInit 1 */ } } 800d376: e010 b.n 800d39a else if(tim_baseHandle->Instance==TIM4) 800d378: 687b ldr r3, [r7, #4] 800d37a: 681b ldr r3, [r3, #0] 800d37c: 4a0b ldr r2, [pc, #44] @ (800d3ac ) 800d37e: 4293 cmp r3, r2 800d380: d10b bne.n 800d39a __HAL_RCC_TIM4_CLK_ENABLE(); 800d382: 4b09 ldr r3, [pc, #36] @ (800d3a8 ) 800d384: 69db ldr r3, [r3, #28] 800d386: 4a08 ldr r2, [pc, #32] @ (800d3a8 ) 800d388: f043 0304 orr.w r3, r3, #4 800d38c: 61d3 str r3, [r2, #28] 800d38e: 4b06 ldr r3, [pc, #24] @ (800d3a8 ) 800d390: 69db ldr r3, [r3, #28] 800d392: f003 0304 and.w r3, r3, #4 800d396: 60bb str r3, [r7, #8] 800d398: 68bb ldr r3, [r7, #8] } 800d39a: bf00 nop 800d39c: 3710 adds r7, #16 800d39e: 46bd mov sp, r7 800d3a0: bd80 pop {r7, pc} 800d3a2: bf00 nop 800d3a4: 40000400 .word 0x40000400 800d3a8: 40021000 .word 0x40021000 800d3ac: 40000800 .word 0x40000800 0800d3b0 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 800d3b0: b580 push {r7, lr} 800d3b2: b08a sub sp, #40 @ 0x28 800d3b4: af00 add r7, sp, #0 800d3b6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800d3b8: f107 0314 add.w r3, r7, #20 800d3bc: 2200 movs r2, #0 800d3be: 601a str r2, [r3, #0] 800d3c0: 605a str r2, [r3, #4] 800d3c2: 609a str r2, [r3, #8] 800d3c4: 60da str r2, [r3, #12] if(timHandle->Instance==TIM3) 800d3c6: 687b ldr r3, [r7, #4] 800d3c8: 681b ldr r3, [r3, #0] 800d3ca: 4a26 ldr r2, [pc, #152] @ (800d464 ) 800d3cc: 4293 cmp r3, r2 800d3ce: d118 bne.n 800d402 { /* USER CODE BEGIN TIM3_MspPostInit 0 */ /* USER CODE END TIM3_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800d3d0: 4b25 ldr r3, [pc, #148] @ (800d468 ) 800d3d2: 699b ldr r3, [r3, #24] 800d3d4: 4a24 ldr r2, [pc, #144] @ (800d468 ) 800d3d6: f043 0304 orr.w r3, r3, #4 800d3da: 6193 str r3, [r2, #24] 800d3dc: 4b22 ldr r3, [pc, #136] @ (800d468 ) 800d3de: 699b ldr r3, [r3, #24] 800d3e0: f003 0304 and.w r3, r3, #4 800d3e4: 613b str r3, [r7, #16] 800d3e6: 693b ldr r3, [r7, #16] /**TIM3 GPIO Configuration PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = CP_PWM_Pin; 800d3e8: 2380 movs r3, #128 @ 0x80 800d3ea: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d3ec: 2302 movs r3, #2 800d3ee: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800d3f0: 2302 movs r3, #2 800d3f2: 623b str r3, [r7, #32] HAL_GPIO_Init(CP_PWM_GPIO_Port, &GPIO_InitStruct); 800d3f4: f107 0314 add.w r3, r7, #20 800d3f8: 4619 mov r1, r3 800d3fa: 481c ldr r0, [pc, #112] @ (800d46c ) 800d3fc: f002 f924 bl 800f648 /* USER CODE BEGIN TIM4_MspPostInit 1 */ /* USER CODE END TIM4_MspPostInit 1 */ } } 800d400: e02b b.n 800d45a else if(timHandle->Instance==TIM4) 800d402: 687b ldr r3, [r7, #4] 800d404: 681b ldr r3, [r3, #0] 800d406: 4a1a ldr r2, [pc, #104] @ (800d470 ) 800d408: 4293 cmp r3, r2 800d40a: d126 bne.n 800d45a __HAL_RCC_GPIOD_CLK_ENABLE(); 800d40c: 4b16 ldr r3, [pc, #88] @ (800d468 ) 800d40e: 699b ldr r3, [r3, #24] 800d410: 4a15 ldr r2, [pc, #84] @ (800d468 ) 800d412: f043 0320 orr.w r3, r3, #32 800d416: 6193 str r3, [r2, #24] 800d418: 4b13 ldr r3, [pc, #76] @ (800d468 ) 800d41a: 699b ldr r3, [r3, #24] 800d41c: f003 0320 and.w r3, r3, #32 800d420: 60fb str r3, [r7, #12] 800d422: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; 800d424: f44f 4360 mov.w r3, #57344 @ 0xe000 800d428: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d42a: 2302 movs r3, #2 800d42c: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800d42e: 2302 movs r3, #2 800d430: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d432: f107 0314 add.w r3, r7, #20 800d436: 4619 mov r1, r3 800d438: 480e ldr r0, [pc, #56] @ (800d474 ) 800d43a: f002 f905 bl 800f648 __HAL_AFIO_REMAP_TIM4_ENABLE(); 800d43e: 4b0e ldr r3, [pc, #56] @ (800d478 ) 800d440: 685b ldr r3, [r3, #4] 800d442: 627b str r3, [r7, #36] @ 0x24 800d444: 6a7b ldr r3, [r7, #36] @ 0x24 800d446: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800d44a: 627b str r3, [r7, #36] @ 0x24 800d44c: 6a7b ldr r3, [r7, #36] @ 0x24 800d44e: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800d452: 627b str r3, [r7, #36] @ 0x24 800d454: 4a08 ldr r2, [pc, #32] @ (800d478 ) 800d456: 6a7b ldr r3, [r7, #36] @ 0x24 800d458: 6053 str r3, [r2, #4] } 800d45a: bf00 nop 800d45c: 3728 adds r7, #40 @ 0x28 800d45e: 46bd mov sp, r7 800d460: bd80 pop {r7, pc} 800d462: bf00 nop 800d464: 40000400 .word 0x40000400 800d468: 40021000 .word 0x40021000 800d46c: 40010800 .word 0x40010800 800d470: 40000800 .word 0x40000800 800d474: 40011400 .word 0x40011400 800d478: 40010000 .word 0x40010000 0800d47c : UART_HandleTypeDef huart2; UART_HandleTypeDef huart3; /* UART5 init function */ void MX_UART5_Init(void) { 800d47c: b580 push {r7, lr} 800d47e: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 800d480: 4b11 ldr r3, [pc, #68] @ (800d4c8 ) 800d482: 4a12 ldr r2, [pc, #72] @ (800d4cc ) 800d484: 601a str r2, [r3, #0] huart5.Init.BaudRate = 9600; 800d486: 4b10 ldr r3, [pc, #64] @ (800d4c8 ) 800d488: f44f 5216 mov.w r2, #9600 @ 0x2580 800d48c: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 800d48e: 4b0e ldr r3, [pc, #56] @ (800d4c8 ) 800d490: 2200 movs r2, #0 800d492: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 800d494: 4b0c ldr r3, [pc, #48] @ (800d4c8 ) 800d496: 2200 movs r2, #0 800d498: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 800d49a: 4b0b ldr r3, [pc, #44] @ (800d4c8 ) 800d49c: 2200 movs r2, #0 800d49e: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 800d4a0: 4b09 ldr r3, [pc, #36] @ (800d4c8 ) 800d4a2: 220c movs r2, #12 800d4a4: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d4a6: 4b08 ldr r3, [pc, #32] @ (800d4c8 ) 800d4a8: 2200 movs r2, #0 800d4aa: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 800d4ac: 4b06 ldr r3, [pc, #24] @ (800d4c8 ) 800d4ae: 2200 movs r2, #0 800d4b0: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 800d4b2: 4805 ldr r0, [pc, #20] @ (800d4c8 ) 800d4b4: f004 fc08 bl 8011cc8 800d4b8: 4603 mov r3, r0 800d4ba: 2b00 cmp r3, #0 800d4bc: d001 beq.n 800d4c2 { Error_Handler(); 800d4be: f7fd fa9d bl 800a9fc } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 800d4c2: bf00 nop 800d4c4: bd80 pop {r7, pc} 800d4c6: bf00 nop 800d4c8: 20000f58 .word 0x20000f58 800d4cc: 40005000 .word 0x40005000 0800d4d0 : /* USART1 init function */ void MX_USART1_UART_Init(void) { 800d4d0: b580 push {r7, lr} 800d4d2: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 800d4d4: 4b11 ldr r3, [pc, #68] @ (800d51c ) 800d4d6: 4a12 ldr r2, [pc, #72] @ (800d520 ) 800d4d8: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800d4da: 4b10 ldr r3, [pc, #64] @ (800d51c ) 800d4dc: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800d4e0: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800d4e2: 4b0e ldr r3, [pc, #56] @ (800d51c ) 800d4e4: 2200 movs r2, #0 800d4e6: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 800d4e8: 4b0c ldr r3, [pc, #48] @ (800d51c ) 800d4ea: 2200 movs r2, #0 800d4ec: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800d4ee: 4b0b ldr r3, [pc, #44] @ (800d51c ) 800d4f0: 2200 movs r2, #0 800d4f2: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 800d4f4: 4b09 ldr r3, [pc, #36] @ (800d51c ) 800d4f6: 220c movs r2, #12 800d4f8: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d4fa: 4b08 ldr r3, [pc, #32] @ (800d51c ) 800d4fc: 2200 movs r2, #0 800d4fe: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800d500: 4b06 ldr r3, [pc, #24] @ (800d51c ) 800d502: 2200 movs r2, #0 800d504: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 800d506: 4805 ldr r0, [pc, #20] @ (800d51c ) 800d508: f004 fbde bl 8011cc8 800d50c: 4603 mov r3, r0 800d50e: 2b00 cmp r3, #0 800d510: d001 beq.n 800d516 { Error_Handler(); 800d512: f7fd fa73 bl 800a9fc } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 800d516: bf00 nop 800d518: bd80 pop {r7, pc} 800d51a: bf00 nop 800d51c: 20000fa0 .word 0x20000fa0 800d520: 40013800 .word 0x40013800 0800d524 : /* USART2 init function */ void MX_USART2_UART_Init(void) { 800d524: b580 push {r7, lr} 800d526: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 800d528: 4b11 ldr r3, [pc, #68] @ (800d570 ) 800d52a: 4a12 ldr r2, [pc, #72] @ (800d574 ) 800d52c: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 800d52e: 4b10 ldr r3, [pc, #64] @ (800d570 ) 800d530: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800d534: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 800d536: 4b0e ldr r3, [pc, #56] @ (800d570 ) 800d538: 2200 movs r2, #0 800d53a: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 800d53c: 4b0c ldr r3, [pc, #48] @ (800d570 ) 800d53e: 2200 movs r2, #0 800d540: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800d542: 4b0b ldr r3, [pc, #44] @ (800d570 ) 800d544: 2200 movs r2, #0 800d546: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 800d548: 4b09 ldr r3, [pc, #36] @ (800d570 ) 800d54a: 220c movs r2, #12 800d54c: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d54e: 4b08 ldr r3, [pc, #32] @ (800d570 ) 800d550: 2200 movs r2, #0 800d552: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 800d554: 4b06 ldr r3, [pc, #24] @ (800d570 ) 800d556: 2200 movs r2, #0 800d558: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 800d55a: 4805 ldr r0, [pc, #20] @ (800d570 ) 800d55c: f004 fbb4 bl 8011cc8 800d560: 4603 mov r3, r0 800d562: 2b00 cmp r3, #0 800d564: d001 beq.n 800d56a { Error_Handler(); 800d566: f7fd fa49 bl 800a9fc } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 800d56a: bf00 nop 800d56c: bd80 pop {r7, pc} 800d56e: bf00 nop 800d570: 20000fe8 .word 0x20000fe8 800d574: 40004400 .word 0x40004400 0800d578 : /* USART3 init function */ void MX_USART3_UART_Init(void) { 800d578: b580 push {r7, lr} 800d57a: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 800d57c: 4b11 ldr r3, [pc, #68] @ (800d5c4 ) 800d57e: 4a12 ldr r2, [pc, #72] @ (800d5c8 ) 800d580: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 800d582: 4b10 ldr r3, [pc, #64] @ (800d5c4 ) 800d584: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800d588: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 800d58a: 4b0e ldr r3, [pc, #56] @ (800d5c4 ) 800d58c: 2200 movs r2, #0 800d58e: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 800d590: 4b0c ldr r3, [pc, #48] @ (800d5c4 ) 800d592: 2200 movs r2, #0 800d594: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 800d596: 4b0b ldr r3, [pc, #44] @ (800d5c4 ) 800d598: 2200 movs r2, #0 800d59a: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 800d59c: 4b09 ldr r3, [pc, #36] @ (800d5c4 ) 800d59e: 220c movs r2, #12 800d5a0: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d5a2: 4b08 ldr r3, [pc, #32] @ (800d5c4 ) 800d5a4: 2200 movs r2, #0 800d5a6: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 800d5a8: 4b06 ldr r3, [pc, #24] @ (800d5c4 ) 800d5aa: 2200 movs r2, #0 800d5ac: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart3) != HAL_OK) 800d5ae: 4805 ldr r0, [pc, #20] @ (800d5c4 ) 800d5b0: f004 fb8a bl 8011cc8 800d5b4: 4603 mov r3, r0 800d5b6: 2b00 cmp r3, #0 800d5b8: d001 beq.n 800d5be { Error_Handler(); 800d5ba: f7fd fa1f bl 800a9fc } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 800d5be: bf00 nop 800d5c0: bd80 pop {r7, pc} 800d5c2: bf00 nop 800d5c4: 20001030 .word 0x20001030 800d5c8: 40004800 .word 0x40004800 0800d5cc : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 800d5cc: b580 push {r7, lr} 800d5ce: b092 sub sp, #72 @ 0x48 800d5d0: af00 add r7, sp, #0 800d5d2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800d5d4: f107 0330 add.w r3, r7, #48 @ 0x30 800d5d8: 2200 movs r2, #0 800d5da: 601a str r2, [r3, #0] 800d5dc: 605a str r2, [r3, #4] 800d5de: 609a str r2, [r3, #8] 800d5e0: 60da str r2, [r3, #12] if(uartHandle->Instance==UART5) 800d5e2: 687b ldr r3, [r7, #4] 800d5e4: 681b ldr r3, [r3, #0] 800d5e6: 4a95 ldr r2, [pc, #596] @ (800d83c ) 800d5e8: 4293 cmp r3, r2 800d5ea: d145 bne.n 800d678 { /* USER CODE BEGIN UART5_MspInit 0 */ /* USER CODE END UART5_MspInit 0 */ /* UART5 clock enable */ __HAL_RCC_UART5_CLK_ENABLE(); 800d5ec: 4b94 ldr r3, [pc, #592] @ (800d840 ) 800d5ee: 69db ldr r3, [r3, #28] 800d5f0: 4a93 ldr r2, [pc, #588] @ (800d840 ) 800d5f2: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800d5f6: 61d3 str r3, [r2, #28] 800d5f8: 4b91 ldr r3, [pc, #580] @ (800d840 ) 800d5fa: 69db ldr r3, [r3, #28] 800d5fc: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800d600: 62fb str r3, [r7, #44] @ 0x2c 800d602: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 800d604: 4b8e ldr r3, [pc, #568] @ (800d840 ) 800d606: 699b ldr r3, [r3, #24] 800d608: 4a8d ldr r2, [pc, #564] @ (800d840 ) 800d60a: f043 0310 orr.w r3, r3, #16 800d60e: 6193 str r3, [r2, #24] 800d610: 4b8b ldr r3, [pc, #556] @ (800d840 ) 800d612: 699b ldr r3, [r3, #24] 800d614: f003 0310 and.w r3, r3, #16 800d618: 62bb str r3, [r7, #40] @ 0x28 800d61a: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOD_CLK_ENABLE(); 800d61c: 4b88 ldr r3, [pc, #544] @ (800d840 ) 800d61e: 699b ldr r3, [r3, #24] 800d620: 4a87 ldr r2, [pc, #540] @ (800d840 ) 800d622: f043 0320 orr.w r3, r3, #32 800d626: 6193 str r3, [r2, #24] 800d628: 4b85 ldr r3, [pc, #532] @ (800d840 ) 800d62a: 699b ldr r3, [r3, #24] 800d62c: f003 0320 and.w r3, r3, #32 800d630: 627b str r3, [r7, #36] @ 0x24 800d632: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART5 GPIO Configuration PC12 ------> UART5_TX PD2 ------> UART5_RX */ GPIO_InitStruct.Pin = GPIO_PIN_12; 800d634: f44f 5380 mov.w r3, #4096 @ 0x1000 800d638: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d63a: 2302 movs r3, #2 800d63c: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800d63e: 2303 movs r3, #3 800d640: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800d642: f107 0330 add.w r3, r7, #48 @ 0x30 800d646: 4619 mov r1, r3 800d648: 487e ldr r0, [pc, #504] @ (800d844 ) 800d64a: f001 fffd bl 800f648 GPIO_InitStruct.Pin = GPIO_PIN_2; 800d64e: 2304 movs r3, #4 800d650: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800d652: 2300 movs r3, #0 800d654: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800d656: 2300 movs r3, #0 800d658: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d65a: f107 0330 add.w r3, r7, #48 @ 0x30 800d65e: 4619 mov r1, r3 800d660: 4879 ldr r0, [pc, #484] @ (800d848 ) 800d662: f001 fff1 bl 800f648 /* UART5 interrupt Init */ HAL_NVIC_SetPriority(UART5_IRQn, 0, 0); 800d666: 2200 movs r2, #0 800d668: 2100 movs r1, #0 800d66a: 2035 movs r0, #53 @ 0x35 800d66c: f001 fe57 bl 800f31e HAL_NVIC_EnableIRQ(UART5_IRQn); 800d670: 2035 movs r0, #53 @ 0x35 800d672: f001 fe70 bl 800f356 HAL_NVIC_EnableIRQ(USART3_IRQn); /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 800d676: e0dc b.n 800d832 else if(uartHandle->Instance==USART1) 800d678: 687b ldr r3, [r7, #4] 800d67a: 681b ldr r3, [r3, #0] 800d67c: 4a73 ldr r2, [pc, #460] @ (800d84c ) 800d67e: 4293 cmp r3, r2 800d680: d13a bne.n 800d6f8 __HAL_RCC_USART1_CLK_ENABLE(); 800d682: 4b6f ldr r3, [pc, #444] @ (800d840 ) 800d684: 699b ldr r3, [r3, #24] 800d686: 4a6e ldr r2, [pc, #440] @ (800d840 ) 800d688: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800d68c: 6193 str r3, [r2, #24] 800d68e: 4b6c ldr r3, [pc, #432] @ (800d840 ) 800d690: 699b ldr r3, [r3, #24] 800d692: f403 4380 and.w r3, r3, #16384 @ 0x4000 800d696: 623b str r3, [r7, #32] 800d698: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 800d69a: 4b69 ldr r3, [pc, #420] @ (800d840 ) 800d69c: 699b ldr r3, [r3, #24] 800d69e: 4a68 ldr r2, [pc, #416] @ (800d840 ) 800d6a0: f043 0304 orr.w r3, r3, #4 800d6a4: 6193 str r3, [r2, #24] 800d6a6: 4b66 ldr r3, [pc, #408] @ (800d840 ) 800d6a8: 699b ldr r3, [r3, #24] 800d6aa: f003 0304 and.w r3, r3, #4 800d6ae: 61fb str r3, [r7, #28] 800d6b0: 69fb ldr r3, [r7, #28] GPIO_InitStruct.Pin = GPIO_PIN_9; 800d6b2: f44f 7300 mov.w r3, #512 @ 0x200 800d6b6: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d6b8: 2302 movs r3, #2 800d6ba: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800d6bc: 2303 movs r3, #3 800d6be: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800d6c0: f107 0330 add.w r3, r7, #48 @ 0x30 800d6c4: 4619 mov r1, r3 800d6c6: 4862 ldr r0, [pc, #392] @ (800d850 ) 800d6c8: f001 ffbe bl 800f648 GPIO_InitStruct.Pin = GPIO_PIN_10; 800d6cc: f44f 6380 mov.w r3, #1024 @ 0x400 800d6d0: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800d6d2: 2300 movs r3, #0 800d6d4: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800d6d6: 2300 movs r3, #0 800d6d8: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800d6da: f107 0330 add.w r3, r7, #48 @ 0x30 800d6de: 4619 mov r1, r3 800d6e0: 485b ldr r0, [pc, #364] @ (800d850 ) 800d6e2: f001 ffb1 bl 800f648 HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 800d6e6: 2200 movs r2, #0 800d6e8: 2100 movs r1, #0 800d6ea: 2025 movs r0, #37 @ 0x25 800d6ec: f001 fe17 bl 800f31e HAL_NVIC_EnableIRQ(USART1_IRQn); 800d6f0: 2025 movs r0, #37 @ 0x25 800d6f2: f001 fe30 bl 800f356 } 800d6f6: e09c b.n 800d832 else if(uartHandle->Instance==USART2) 800d6f8: 687b ldr r3, [r7, #4] 800d6fa: 681b ldr r3, [r3, #0] 800d6fc: 4a55 ldr r2, [pc, #340] @ (800d854 ) 800d6fe: 4293 cmp r3, r2 800d700: d146 bne.n 800d790 __HAL_RCC_USART2_CLK_ENABLE(); 800d702: 4b4f ldr r3, [pc, #316] @ (800d840 ) 800d704: 69db ldr r3, [r3, #28] 800d706: 4a4e ldr r2, [pc, #312] @ (800d840 ) 800d708: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d70c: 61d3 str r3, [r2, #28] 800d70e: 4b4c ldr r3, [pc, #304] @ (800d840 ) 800d710: 69db ldr r3, [r3, #28] 800d712: f403 3300 and.w r3, r3, #131072 @ 0x20000 800d716: 61bb str r3, [r7, #24] 800d718: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOD_CLK_ENABLE(); 800d71a: 4b49 ldr r3, [pc, #292] @ (800d840 ) 800d71c: 699b ldr r3, [r3, #24] 800d71e: 4a48 ldr r2, [pc, #288] @ (800d840 ) 800d720: f043 0320 orr.w r3, r3, #32 800d724: 6193 str r3, [r2, #24] 800d726: 4b46 ldr r3, [pc, #280] @ (800d840 ) 800d728: 699b ldr r3, [r3, #24] 800d72a: f003 0320 and.w r3, r3, #32 800d72e: 617b str r3, [r7, #20] 800d730: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_5; 800d732: 2320 movs r3, #32 800d734: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d736: 2302 movs r3, #2 800d738: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800d73a: 2303 movs r3, #3 800d73c: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d73e: f107 0330 add.w r3, r7, #48 @ 0x30 800d742: 4619 mov r1, r3 800d744: 4840 ldr r0, [pc, #256] @ (800d848 ) 800d746: f001 ff7f bl 800f648 GPIO_InitStruct.Pin = GPIO_PIN_6; 800d74a: 2340 movs r3, #64 @ 0x40 800d74c: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800d74e: 2300 movs r3, #0 800d750: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800d752: 2300 movs r3, #0 800d754: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d756: f107 0330 add.w r3, r7, #48 @ 0x30 800d75a: 4619 mov r1, r3 800d75c: 483a ldr r0, [pc, #232] @ (800d848 ) 800d75e: f001 ff73 bl 800f648 __HAL_AFIO_REMAP_USART2_ENABLE(); 800d762: 4b3d ldr r3, [pc, #244] @ (800d858 ) 800d764: 685b ldr r3, [r3, #4] 800d766: 643b str r3, [r7, #64] @ 0x40 800d768: 6c3b ldr r3, [r7, #64] @ 0x40 800d76a: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800d76e: 643b str r3, [r7, #64] @ 0x40 800d770: 6c3b ldr r3, [r7, #64] @ 0x40 800d772: f043 0308 orr.w r3, r3, #8 800d776: 643b str r3, [r7, #64] @ 0x40 800d778: 4a37 ldr r2, [pc, #220] @ (800d858 ) 800d77a: 6c3b ldr r3, [r7, #64] @ 0x40 800d77c: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); 800d77e: 2200 movs r2, #0 800d780: 2100 movs r1, #0 800d782: 2026 movs r0, #38 @ 0x26 800d784: f001 fdcb bl 800f31e HAL_NVIC_EnableIRQ(USART2_IRQn); 800d788: 2026 movs r0, #38 @ 0x26 800d78a: f001 fde4 bl 800f356 } 800d78e: e050 b.n 800d832 else if(uartHandle->Instance==USART3) 800d790: 687b ldr r3, [r7, #4] 800d792: 681b ldr r3, [r3, #0] 800d794: 4a31 ldr r2, [pc, #196] @ (800d85c ) 800d796: 4293 cmp r3, r2 800d798: d14b bne.n 800d832 __HAL_RCC_USART3_CLK_ENABLE(); 800d79a: 4b29 ldr r3, [pc, #164] @ (800d840 ) 800d79c: 69db ldr r3, [r3, #28] 800d79e: 4a28 ldr r2, [pc, #160] @ (800d840 ) 800d7a0: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800d7a4: 61d3 str r3, [r2, #28] 800d7a6: 4b26 ldr r3, [pc, #152] @ (800d840 ) 800d7a8: 69db ldr r3, [r3, #28] 800d7aa: f403 2380 and.w r3, r3, #262144 @ 0x40000 800d7ae: 613b str r3, [r7, #16] 800d7b0: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 800d7b2: 4b23 ldr r3, [pc, #140] @ (800d840 ) 800d7b4: 699b ldr r3, [r3, #24] 800d7b6: 4a22 ldr r2, [pc, #136] @ (800d840 ) 800d7b8: f043 0310 orr.w r3, r3, #16 800d7bc: 6193 str r3, [r2, #24] 800d7be: 4b20 ldr r3, [pc, #128] @ (800d840 ) 800d7c0: 699b ldr r3, [r3, #24] 800d7c2: f003 0310 and.w r3, r3, #16 800d7c6: 60fb str r3, [r7, #12] 800d7c8: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_10; 800d7ca: f44f 6380 mov.w r3, #1024 @ 0x400 800d7ce: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d7d0: 2302 movs r3, #2 800d7d2: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800d7d4: 2303 movs r3, #3 800d7d6: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800d7d8: f107 0330 add.w r3, r7, #48 @ 0x30 800d7dc: 4619 mov r1, r3 800d7de: 4819 ldr r0, [pc, #100] @ (800d844 ) 800d7e0: f001 ff32 bl 800f648 GPIO_InitStruct.Pin = GPIO_PIN_11; 800d7e4: f44f 6300 mov.w r3, #2048 @ 0x800 800d7e8: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800d7ea: 2300 movs r3, #0 800d7ec: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800d7ee: 2300 movs r3, #0 800d7f0: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800d7f2: f107 0330 add.w r3, r7, #48 @ 0x30 800d7f6: 4619 mov r1, r3 800d7f8: 4812 ldr r0, [pc, #72] @ (800d844 ) 800d7fa: f001 ff25 bl 800f648 __HAL_AFIO_REMAP_USART3_PARTIAL(); 800d7fe: 4b16 ldr r3, [pc, #88] @ (800d858 ) 800d800: 685b ldr r3, [r3, #4] 800d802: 647b str r3, [r7, #68] @ 0x44 800d804: 6c7b ldr r3, [r7, #68] @ 0x44 800d806: f023 0330 bic.w r3, r3, #48 @ 0x30 800d80a: 647b str r3, [r7, #68] @ 0x44 800d80c: 6c7b ldr r3, [r7, #68] @ 0x44 800d80e: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800d812: 647b str r3, [r7, #68] @ 0x44 800d814: 6c7b ldr r3, [r7, #68] @ 0x44 800d816: f043 0310 orr.w r3, r3, #16 800d81a: 647b str r3, [r7, #68] @ 0x44 800d81c: 4a0e ldr r2, [pc, #56] @ (800d858 ) 800d81e: 6c7b ldr r3, [r7, #68] @ 0x44 800d820: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); 800d822: 2200 movs r2, #0 800d824: 2100 movs r1, #0 800d826: 2027 movs r0, #39 @ 0x27 800d828: f001 fd79 bl 800f31e HAL_NVIC_EnableIRQ(USART3_IRQn); 800d82c: 2027 movs r0, #39 @ 0x27 800d82e: f001 fd92 bl 800f356 } 800d832: bf00 nop 800d834: 3748 adds r7, #72 @ 0x48 800d836: 46bd mov sp, r7 800d838: bd80 pop {r7, pc} 800d83a: bf00 nop 800d83c: 40005000 .word 0x40005000 800d840: 40021000 .word 0x40021000 800d844: 40011000 .word 0x40011000 800d848: 40011400 .word 0x40011400 800d84c: 40013800 .word 0x40013800 800d850: 40010800 .word 0x40010800 800d854: 40004400 .word 0x40004400 800d858: 40010000 .word 0x40010000 800d85c: 40004800 .word 0x40004800 0800d860 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 800d860: f7ff fc64 bl 800d12c /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 800d864: 480b ldr r0, [pc, #44] @ (800d894 ) ldr r1, =_edata 800d866: 490c ldr r1, [pc, #48] @ (800d898 ) ldr r2, =_sidata 800d868: 4a0c ldr r2, [pc, #48] @ (800d89c ) movs r3, #0 800d86a: 2300 movs r3, #0 b LoopCopyDataInit 800d86c: e002 b.n 800d874 0800d86e : CopyDataInit: ldr r4, [r2, r3] 800d86e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800d870: 50c4 str r4, [r0, r3] adds r3, r3, #4 800d872: 3304 adds r3, #4 0800d874 : LoopCopyDataInit: adds r4, r0, r3 800d874: 18c4 adds r4, r0, r3 cmp r4, r1 800d876: 428c cmp r4, r1 bcc CopyDataInit 800d878: d3f9 bcc.n 800d86e /* Zero fill the bss segment. */ ldr r2, =_sbss 800d87a: 4a09 ldr r2, [pc, #36] @ (800d8a0 ) ldr r4, =_ebss 800d87c: 4c09 ldr r4, [pc, #36] @ (800d8a4 ) movs r3, #0 800d87e: 2300 movs r3, #0 b LoopFillZerobss 800d880: e001 b.n 800d886 0800d882 : FillZerobss: str r3, [r2] 800d882: 6013 str r3, [r2, #0] adds r2, r2, #4 800d884: 3204 adds r2, #4 0800d886 : LoopFillZerobss: cmp r2, r4 800d886: 42a2 cmp r2, r4 bcc FillZerobss 800d888: d3fb bcc.n 800d882 /* Call static constructors */ bl __libc_init_array 800d88a: f005 fc2d bl 80130e8 <__libc_init_array> /* Call the application's entry point.*/ bl main 800d88e: f7fc ffc9 bl 800a824
bx lr 800d892: 4770 bx lr ldr r0, =_sdata 800d894: 20000000 .word 0x20000000 ldr r1, =_edata 800d898: 200000d4 .word 0x200000d4 ldr r2, =_sidata 800d89c: 080144c0 .word 0x080144c0 ldr r2, =_sbss 800d8a0: 200000d8 .word 0x200000d8 ldr r4, =_ebss 800d8a4: 200011c8 .word 0x200011c8 0800d8a8 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 800d8a8: e7fe b.n 800d8a8 ... 0800d8ac : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800d8ac: b580 push {r7, lr} 800d8ae: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 800d8b0: 4b08 ldr r3, [pc, #32] @ (800d8d4 ) 800d8b2: 681b ldr r3, [r3, #0] 800d8b4: 4a07 ldr r2, [pc, #28] @ (800d8d4 ) 800d8b6: f043 0310 orr.w r3, r3, #16 800d8ba: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800d8bc: 2003 movs r0, #3 800d8be: f001 fd23 bl 800f308 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800d8c2: 200f movs r0, #15 800d8c4: f000 f808 bl 800d8d8 /* Init the low level hardware */ HAL_MspInit(); 800d8c8: f7ff fafe bl 800cec8 /* Return function status */ return HAL_OK; 800d8cc: 2300 movs r3, #0 } 800d8ce: 4618 mov r0, r3 800d8d0: bd80 pop {r7, pc} 800d8d2: bf00 nop 800d8d4: 40022000 .word 0x40022000 0800d8d8 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800d8d8: b580 push {r7, lr} 800d8da: b082 sub sp, #8 800d8dc: af00 add r7, sp, #0 800d8de: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 800d8e0: 4b12 ldr r3, [pc, #72] @ (800d92c ) 800d8e2: 681a ldr r2, [r3, #0] 800d8e4: 4b12 ldr r3, [pc, #72] @ (800d930 ) 800d8e6: 781b ldrb r3, [r3, #0] 800d8e8: 4619 mov r1, r3 800d8ea: f44f 737a mov.w r3, #1000 @ 0x3e8 800d8ee: fbb3 f3f1 udiv r3, r3, r1 800d8f2: fbb2 f3f3 udiv r3, r2, r3 800d8f6: 4618 mov r0, r3 800d8f8: f001 fd3b bl 800f372 800d8fc: 4603 mov r3, r0 800d8fe: 2b00 cmp r3, #0 800d900: d001 beq.n 800d906 { return HAL_ERROR; 800d902: 2301 movs r3, #1 800d904: e00e b.n 800d924 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800d906: 687b ldr r3, [r7, #4] 800d908: 2b0f cmp r3, #15 800d90a: d80a bhi.n 800d922 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800d90c: 2200 movs r2, #0 800d90e: 6879 ldr r1, [r7, #4] 800d910: f04f 30ff mov.w r0, #4294967295 800d914: f001 fd03 bl 800f31e uwTickPrio = TickPriority; 800d918: 4a06 ldr r2, [pc, #24] @ (800d934 ) 800d91a: 687b ldr r3, [r7, #4] 800d91c: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800d91e: 2300 movs r3, #0 800d920: e000 b.n 800d924 return HAL_ERROR; 800d922: 2301 movs r3, #1 } 800d924: 4618 mov r0, r3 800d926: 3708 adds r7, #8 800d928: 46bd mov sp, r7 800d92a: bd80 pop {r7, pc} 800d92c: 2000006c .word 0x2000006c 800d930: 20000074 .word 0x20000074 800d934: 20000070 .word 0x20000070 0800d938 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800d938: b480 push {r7} 800d93a: af00 add r7, sp, #0 uwTick += uwTickFreq; 800d93c: 4b05 ldr r3, [pc, #20] @ (800d954 ) 800d93e: 781b ldrb r3, [r3, #0] 800d940: 461a mov r2, r3 800d942: 4b05 ldr r3, [pc, #20] @ (800d958 ) 800d944: 681b ldr r3, [r3, #0] 800d946: 4413 add r3, r2 800d948: 4a03 ldr r2, [pc, #12] @ (800d958 ) 800d94a: 6013 str r3, [r2, #0] } 800d94c: bf00 nop 800d94e: 46bd mov sp, r7 800d950: bc80 pop {r7} 800d952: 4770 bx lr 800d954: 20000074 .word 0x20000074 800d958: 20001078 .word 0x20001078 0800d95c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 800d95c: b480 push {r7} 800d95e: af00 add r7, sp, #0 return uwTick; 800d960: 4b02 ldr r3, [pc, #8] @ (800d96c ) 800d962: 681b ldr r3, [r3, #0] } 800d964: 4618 mov r0, r3 800d966: 46bd mov sp, r7 800d968: bc80 pop {r7} 800d96a: 4770 bx lr 800d96c: 20001078 .word 0x20001078 0800d970 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 800d970: b580 push {r7, lr} 800d972: b084 sub sp, #16 800d974: af00 add r7, sp, #0 800d976: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800d978: f7ff fff0 bl 800d95c 800d97c: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800d97e: 687b ldr r3, [r7, #4] 800d980: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800d982: 68fb ldr r3, [r7, #12] 800d984: f1b3 3fff cmp.w r3, #4294967295 800d988: d005 beq.n 800d996 { wait += (uint32_t)(uwTickFreq); 800d98a: 4b0a ldr r3, [pc, #40] @ (800d9b4 ) 800d98c: 781b ldrb r3, [r3, #0] 800d98e: 461a mov r2, r3 800d990: 68fb ldr r3, [r7, #12] 800d992: 4413 add r3, r2 800d994: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 800d996: bf00 nop 800d998: f7ff ffe0 bl 800d95c 800d99c: 4602 mov r2, r0 800d99e: 68bb ldr r3, [r7, #8] 800d9a0: 1ad3 subs r3, r2, r3 800d9a2: 68fa ldr r2, [r7, #12] 800d9a4: 429a cmp r2, r3 800d9a6: d8f7 bhi.n 800d998 { } } 800d9a8: bf00 nop 800d9aa: bf00 nop 800d9ac: 3710 adds r7, #16 800d9ae: 46bd mov sp, r7 800d9b0: bd80 pop {r7, pc} 800d9b2: bf00 nop 800d9b4: 20000074 .word 0x20000074 0800d9b8 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 800d9b8: b580 push {r7, lr} 800d9ba: b086 sub sp, #24 800d9bc: af00 add r7, sp, #0 800d9be: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800d9c0: 2300 movs r3, #0 800d9c2: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 800d9c4: 2300 movs r3, #0 800d9c6: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 800d9c8: 2300 movs r3, #0 800d9ca: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 800d9cc: 2300 movs r3, #0 800d9ce: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 800d9d0: 687b ldr r3, [r7, #4] 800d9d2: 2b00 cmp r3, #0 800d9d4: d101 bne.n 800d9da { return HAL_ERROR; 800d9d6: 2301 movs r3, #1 800d9d8: e0be b.n 800db58 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 800d9da: 687b ldr r3, [r7, #4] 800d9dc: 689b ldr r3, [r3, #8] 800d9de: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 800d9e0: 687b ldr r3, [r7, #4] 800d9e2: 6a9b ldr r3, [r3, #40] @ 0x28 800d9e4: 2b00 cmp r3, #0 800d9e6: d109 bne.n 800d9fc { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 800d9e8: 687b ldr r3, [r7, #4] 800d9ea: 2200 movs r2, #0 800d9ec: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 800d9ee: 687b ldr r3, [r7, #4] 800d9f0: 2200 movs r2, #0 800d9f2: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800d9f6: 6878 ldr r0, [r7, #4] 800d9f8: f7fb fd06 bl 8009408 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800d9fc: 6878 ldr r0, [r7, #4] 800d9fe: f000 fbf1 bl 800e1e4 800da02: 4603 mov r3, r0 800da04: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 800da06: 687b ldr r3, [r7, #4] 800da08: 6a9b ldr r3, [r3, #40] @ 0x28 800da0a: f003 0310 and.w r3, r3, #16 800da0e: 2b00 cmp r3, #0 800da10: f040 8099 bne.w 800db46 800da14: 7dfb ldrb r3, [r7, #23] 800da16: 2b00 cmp r3, #0 800da18: f040 8095 bne.w 800db46 (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800da1c: 687b ldr r3, [r7, #4] 800da1e: 6a9b ldr r3, [r3, #40] @ 0x28 800da20: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800da24: f023 0302 bic.w r3, r3, #2 800da28: f043 0202 orr.w r2, r3, #2 800da2c: 687b ldr r3, [r7, #4] 800da2e: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 800da30: 687b ldr r3, [r7, #4] 800da32: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800da34: 687b ldr r3, [r7, #4] 800da36: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 800da38: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 800da3a: 687b ldr r3, [r7, #4] 800da3c: 7b1b ldrb r3, [r3, #12] 800da3e: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800da40: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 800da42: 68ba ldr r2, [r7, #8] 800da44: 4313 orrs r3, r2 800da46: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 800da48: 687b ldr r3, [r7, #4] 800da4a: 689b ldr r3, [r3, #8] 800da4c: f5b3 7f80 cmp.w r3, #256 @ 0x100 800da50: d003 beq.n 800da5a 800da52: 687b ldr r3, [r7, #4] 800da54: 689b ldr r3, [r3, #8] 800da56: 2b01 cmp r3, #1 800da58: d102 bne.n 800da60 800da5a: f44f 7380 mov.w r3, #256 @ 0x100 800da5e: e000 b.n 800da62 800da60: 2300 movs r3, #0 800da62: 693a ldr r2, [r7, #16] 800da64: 4313 orrs r3, r2 800da66: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 800da68: 687b ldr r3, [r7, #4] 800da6a: 7d1b ldrb r3, [r3, #20] 800da6c: 2b01 cmp r3, #1 800da6e: d119 bne.n 800daa4 { if (hadc->Init.ContinuousConvMode == DISABLE) 800da70: 687b ldr r3, [r7, #4] 800da72: 7b1b ldrb r3, [r3, #12] 800da74: 2b00 cmp r3, #0 800da76: d109 bne.n 800da8c { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 800da78: 687b ldr r3, [r7, #4] 800da7a: 699b ldr r3, [r3, #24] 800da7c: 3b01 subs r3, #1 800da7e: 035a lsls r2, r3, #13 800da80: 693b ldr r3, [r7, #16] 800da82: 4313 orrs r3, r2 800da84: f443 6300 orr.w r3, r3, #2048 @ 0x800 800da88: 613b str r3, [r7, #16] 800da8a: e00b b.n 800daa4 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800da8c: 687b ldr r3, [r7, #4] 800da8e: 6a9b ldr r3, [r3, #40] @ 0x28 800da90: f043 0220 orr.w r2, r3, #32 800da94: 687b ldr r3, [r7, #4] 800da96: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800da98: 687b ldr r3, [r7, #4] 800da9a: 6adb ldr r3, [r3, #44] @ 0x2c 800da9c: f043 0201 orr.w r2, r3, #1 800daa0: 687b ldr r3, [r7, #4] 800daa2: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 800daa4: 687b ldr r3, [r7, #4] 800daa6: 681b ldr r3, [r3, #0] 800daa8: 685b ldr r3, [r3, #4] 800daaa: f423 4169 bic.w r1, r3, #59648 @ 0xe900 800daae: 687b ldr r3, [r7, #4] 800dab0: 681b ldr r3, [r3, #0] 800dab2: 693a ldr r2, [r7, #16] 800dab4: 430a orrs r2, r1 800dab6: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 800dab8: 687b ldr r3, [r7, #4] 800daba: 681b ldr r3, [r3, #0] 800dabc: 689a ldr r2, [r3, #8] 800dabe: 4b28 ldr r3, [pc, #160] @ (800db60 ) 800dac0: 4013 ands r3, r2 800dac2: 687a ldr r2, [r7, #4] 800dac4: 6812 ldr r2, [r2, #0] 800dac6: 68b9 ldr r1, [r7, #8] 800dac8: 430b orrs r3, r1 800daca: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 800dacc: 687b ldr r3, [r7, #4] 800dace: 689b ldr r3, [r3, #8] 800dad0: f5b3 7f80 cmp.w r3, #256 @ 0x100 800dad4: d003 beq.n 800dade 800dad6: 687b ldr r3, [r7, #4] 800dad8: 689b ldr r3, [r3, #8] 800dada: 2b01 cmp r3, #1 800dadc: d104 bne.n 800dae8 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 800dade: 687b ldr r3, [r7, #4] 800dae0: 691b ldr r3, [r3, #16] 800dae2: 3b01 subs r3, #1 800dae4: 051b lsls r3, r3, #20 800dae6: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 800dae8: 687b ldr r3, [r7, #4] 800daea: 681b ldr r3, [r3, #0] 800daec: 6adb ldr r3, [r3, #44] @ 0x2c 800daee: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 800daf2: 687b ldr r3, [r7, #4] 800daf4: 681b ldr r3, [r3, #0] 800daf6: 68fa ldr r2, [r7, #12] 800daf8: 430a orrs r2, r1 800dafa: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800dafc: 687b ldr r3, [r7, #4] 800dafe: 681b ldr r3, [r3, #0] 800db00: 689a ldr r2, [r3, #8] 800db02: 4b18 ldr r3, [pc, #96] @ (800db64 ) 800db04: 4013 ands r3, r2 800db06: 68ba ldr r2, [r7, #8] 800db08: 429a cmp r2, r3 800db0a: d10b bne.n 800db24 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 800db0c: 687b ldr r3, [r7, #4] 800db0e: 2200 movs r2, #0 800db10: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 800db12: 687b ldr r3, [r7, #4] 800db14: 6a9b ldr r3, [r3, #40] @ 0x28 800db16: f023 0303 bic.w r3, r3, #3 800db1a: f043 0201 orr.w r2, r3, #1 800db1e: 687b ldr r3, [r7, #4] 800db20: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800db22: e018 b.n 800db56 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800db24: 687b ldr r3, [r7, #4] 800db26: 6a9b ldr r3, [r3, #40] @ 0x28 800db28: f023 0312 bic.w r3, r3, #18 800db2c: f043 0210 orr.w r2, r3, #16 800db30: 687b ldr r3, [r7, #4] 800db32: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800db34: 687b ldr r3, [r7, #4] 800db36: 6adb ldr r3, [r3, #44] @ 0x2c 800db38: f043 0201 orr.w r2, r3, #1 800db3c: 687b ldr r3, [r7, #4] 800db3e: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 800db40: 2301 movs r3, #1 800db42: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800db44: e007 b.n 800db56 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800db46: 687b ldr r3, [r7, #4] 800db48: 6a9b ldr r3, [r3, #40] @ 0x28 800db4a: f043 0210 orr.w r2, r3, #16 800db4e: 687b ldr r3, [r7, #4] 800db50: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800db52: 2301 movs r3, #1 800db54: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800db56: 7dfb ldrb r3, [r7, #23] } 800db58: 4618 mov r0, r3 800db5a: 3718 adds r7, #24 800db5c: 46bd mov sp, r7 800db5e: bd80 pop {r7, pc} 800db60: ffe1f7fd .word 0xffe1f7fd 800db64: ff1f0efe .word 0xff1f0efe 0800db68 : * Interruptions enabled in this function: None. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { 800db68: b580 push {r7, lr} 800db6a: b084 sub sp, #16 800db6c: af00 add r7, sp, #0 800db6e: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800db70: 2300 movs r3, #0 800db72: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800db74: 687b ldr r3, [r7, #4] 800db76: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800db7a: 2b01 cmp r3, #1 800db7c: d101 bne.n 800db82 800db7e: 2302 movs r3, #2 800db80: e098 b.n 800dcb4 800db82: 687b ldr r3, [r7, #4] 800db84: 2201 movs r2, #1 800db86: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 800db8a: 6878 ldr r0, [r7, #4] 800db8c: f000 fad0 bl 800e130 800db90: 4603 mov r3, r0 800db92: 73fb strb r3, [r7, #15] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800db94: 7bfb ldrb r3, [r7, #15] 800db96: 2b00 cmp r3, #0 800db98: f040 8087 bne.w 800dcaa { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 800db9c: 687b ldr r3, [r7, #4] 800db9e: 6a9b ldr r3, [r3, #40] @ 0x28 800dba0: f423 7340 bic.w r3, r3, #768 @ 0x300 800dba4: f023 0301 bic.w r3, r3, #1 800dba8: f443 7280 orr.w r2, r3, #256 @ 0x100 800dbac: 687b ldr r3, [r7, #4] 800dbae: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 800dbb0: 687b ldr r3, [r7, #4] 800dbb2: 681b ldr r3, [r3, #0] 800dbb4: 4a41 ldr r2, [pc, #260] @ (800dcbc ) 800dbb6: 4293 cmp r3, r2 800dbb8: d105 bne.n 800dbc6 800dbba: 4b41 ldr r3, [pc, #260] @ (800dcc0 ) 800dbbc: 685b ldr r3, [r3, #4] 800dbbe: f403 2370 and.w r3, r3, #983040 @ 0xf0000 800dbc2: 2b00 cmp r3, #0 800dbc4: d115 bne.n 800dbf2 { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800dbc6: 687b ldr r3, [r7, #4] 800dbc8: 6a9b ldr r3, [r3, #40] @ 0x28 800dbca: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 800dbce: 687b ldr r3, [r7, #4] 800dbd0: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800dbd2: 687b ldr r3, [r7, #4] 800dbd4: 681b ldr r3, [r3, #0] 800dbd6: 685b ldr r3, [r3, #4] 800dbd8: f403 6380 and.w r3, r3, #1024 @ 0x400 800dbdc: 2b00 cmp r3, #0 800dbde: d026 beq.n 800dc2e { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800dbe0: 687b ldr r3, [r7, #4] 800dbe2: 6a9b ldr r3, [r3, #40] @ 0x28 800dbe4: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800dbe8: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800dbec: 687b ldr r3, [r7, #4] 800dbee: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800dbf0: e01d b.n 800dc2e } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800dbf2: 687b ldr r3, [r7, #4] 800dbf4: 6a9b ldr r3, [r3, #40] @ 0x28 800dbf6: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800dbfa: 687b ldr r3, [r7, #4] 800dbfc: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 800dbfe: 687b ldr r3, [r7, #4] 800dc00: 681b ldr r3, [r3, #0] 800dc02: 4a2f ldr r2, [pc, #188] @ (800dcc0 ) 800dc04: 4293 cmp r3, r2 800dc06: d004 beq.n 800dc12 800dc08: 687b ldr r3, [r7, #4] 800dc0a: 681b ldr r3, [r3, #0] 800dc0c: 4a2b ldr r2, [pc, #172] @ (800dcbc ) 800dc0e: 4293 cmp r3, r2 800dc10: d10d bne.n 800dc2e 800dc12: 4b2b ldr r3, [pc, #172] @ (800dcc0 ) 800dc14: 685b ldr r3, [r3, #4] 800dc16: f403 6380 and.w r3, r3, #1024 @ 0x400 800dc1a: 2b00 cmp r3, #0 800dc1c: d007 beq.n 800dc2e { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800dc1e: 687b ldr r3, [r7, #4] 800dc20: 6a9b ldr r3, [r3, #40] @ 0x28 800dc22: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800dc26: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800dc2a: 687b ldr r3, [r7, #4] 800dc2c: 629a str r2, [r3, #40] @ 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800dc2e: 687b ldr r3, [r7, #4] 800dc30: 6a9b ldr r3, [r3, #40] @ 0x28 800dc32: f403 5380 and.w r3, r3, #4096 @ 0x1000 800dc36: 2b00 cmp r3, #0 800dc38: d006 beq.n 800dc48 { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 800dc3a: 687b ldr r3, [r7, #4] 800dc3c: 6adb ldr r3, [r3, #44] @ 0x2c 800dc3e: f023 0206 bic.w r2, r3, #6 800dc42: 687b ldr r3, [r7, #4] 800dc44: 62da str r2, [r3, #44] @ 0x2c 800dc46: e002 b.n 800dc4e } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 800dc48: 687b ldr r3, [r7, #4] 800dc4a: 2200 movs r2, #0 800dc4c: 62da str r2, [r3, #44] @ 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 800dc4e: 687b ldr r3, [r7, #4] 800dc50: 2200 movs r2, #0 800dc52: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Clear regular group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 800dc56: 687b ldr r3, [r7, #4] 800dc58: 681b ldr r3, [r3, #0] 800dc5a: f06f 0202 mvn.w r2, #2 800dc5e: 601a str r2, [r3, #0] /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ /* If ADC is master, ADC is enabled and conversion is started. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800dc60: 687b ldr r3, [r7, #4] 800dc62: 681b ldr r3, [r3, #0] 800dc64: 689b ldr r3, [r3, #8] 800dc66: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800dc6a: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800dc6e: d113 bne.n 800dc98 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 800dc70: 687b ldr r3, [r7, #4] 800dc72: 681b ldr r3, [r3, #0] if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800dc74: 4a11 ldr r2, [pc, #68] @ (800dcbc ) 800dc76: 4293 cmp r3, r2 800dc78: d105 bne.n 800dc86 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 800dc7a: 4b11 ldr r3, [pc, #68] @ (800dcc0 ) 800dc7c: 685b ldr r3, [r3, #4] 800dc7e: f403 2370 and.w r3, r3, #983040 @ 0xf0000 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800dc82: 2b00 cmp r3, #0 800dc84: d108 bne.n 800dc98 { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 800dc86: 687b ldr r3, [r7, #4] 800dc88: 681b ldr r3, [r3, #0] 800dc8a: 689a ldr r2, [r3, #8] 800dc8c: 687b ldr r3, [r7, #4] 800dc8e: 681b ldr r3, [r3, #0] 800dc90: f442 02a0 orr.w r2, r2, #5242880 @ 0x500000 800dc94: 609a str r2, [r3, #8] 800dc96: e00c b.n 800dcb2 } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 800dc98: 687b ldr r3, [r7, #4] 800dc9a: 681b ldr r3, [r3, #0] 800dc9c: 689a ldr r2, [r3, #8] 800dc9e: 687b ldr r3, [r7, #4] 800dca0: 681b ldr r3, [r3, #0] 800dca2: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 800dca6: 609a str r2, [r3, #8] 800dca8: e003 b.n 800dcb2 } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 800dcaa: 687b ldr r3, [r7, #4] 800dcac: 2200 movs r2, #0 800dcae: f883 2024 strb.w r2, [r3, #36] @ 0x24 } /* Return function status */ return tmp_hal_status; 800dcb2: 7bfb ldrb r3, [r7, #15] } 800dcb4: 4618 mov r0, r3 800dcb6: 3710 adds r7, #16 800dcb8: 46bd mov sp, r7 800dcba: bd80 pop {r7, pc} 800dcbc: 40012800 .word 0x40012800 800dcc0: 40012400 .word 0x40012400 0800dcc4 : * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { 800dcc4: b580 push {r7, lr} 800dcc6: b084 sub sp, #16 800dcc8: af00 add r7, sp, #0 800dcca: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800dccc: 2300 movs r3, #0 800dcce: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800dcd0: 687b ldr r3, [r7, #4] 800dcd2: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800dcd6: 2b01 cmp r3, #1 800dcd8: d101 bne.n 800dcde 800dcda: 2302 movs r3, #2 800dcdc: e01a b.n 800dd14 800dcde: 687b ldr r3, [r7, #4] 800dce0: 2201 movs r2, #1 800dce2: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800dce6: 6878 ldr r0, [r7, #4] 800dce8: f000 fa7c bl 800e1e4 800dcec: 4603 mov r3, r0 800dcee: 73fb strb r3, [r7, #15] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 800dcf0: 7bfb ldrb r3, [r7, #15] 800dcf2: 2b00 cmp r3, #0 800dcf4: d109 bne.n 800dd0a { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800dcf6: 687b ldr r3, [r7, #4] 800dcf8: 6a9b ldr r3, [r3, #40] @ 0x28 800dcfa: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800dcfe: f023 0301 bic.w r3, r3, #1 800dd02: f043 0201 orr.w r2, r3, #1 800dd06: 687b ldr r3, [r7, #4] 800dd08: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 800dd0a: 687b ldr r3, [r7, #4] 800dd0c: 2200 movs r2, #0 800dd0e: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800dd12: 7bfb ldrb r3, [r7, #15] } 800dd14: 4618 mov r0, r3 800dd16: 3710 adds r7, #16 800dd18: 46bd mov sp, r7 800dd1a: bd80 pop {r7, pc} 0800dd1c : * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { 800dd1c: b590 push {r4, r7, lr} 800dd1e: b087 sub sp, #28 800dd20: af00 add r7, sp, #0 800dd22: 6078 str r0, [r7, #4] 800dd24: 6039 str r1, [r7, #0] uint32_t tickstart = 0U; 800dd26: 2300 movs r3, #0 800dd28: 617b str r3, [r7, #20] /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; 800dd2a: 2300 movs r3, #0 800dd2c: 60fb str r3, [r7, #12] uint32_t Conversion_Timeout_CPU_cycles_max = 0U; 800dd2e: 2300 movs r3, #0 800dd30: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Get tick count */ tickstart = HAL_GetTick(); 800dd32: f7ff fe13 bl 800d95c 800dd36: 6178 str r0, [r7, #20] /* Verification that ADC configuration is compliant with polling for */ /* each conversion: */ /* Particular case is ADC configured in DMA mode */ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) 800dd38: 687b ldr r3, [r7, #4] 800dd3a: 681b ldr r3, [r3, #0] 800dd3c: 689b ldr r3, [r3, #8] 800dd3e: f403 7380 and.w r3, r3, #256 @ 0x100 800dd42: 2b00 cmp r3, #0 800dd44: d00b beq.n 800dd5e { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800dd46: 687b ldr r3, [r7, #4] 800dd48: 6a9b ldr r3, [r3, #40] @ 0x28 800dd4a: f043 0220 orr.w r2, r3, #32 800dd4e: 687b ldr r3, [r7, #4] 800dd50: 629a str r2, [r3, #40] @ 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 800dd52: 687b ldr r3, [r7, #4] 800dd54: 2200 movs r2, #0 800dd56: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800dd5a: 2301 movs r3, #1 800dd5c: e0d3 b.n 800df06 /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ /* As flag EOC is not set after each conversion, no timeout status can */ /* be set. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 800dd5e: 687b ldr r3, [r7, #4] 800dd60: 681b ldr r3, [r3, #0] 800dd62: 685b ldr r3, [r3, #4] 800dd64: f403 7380 and.w r3, r3, #256 @ 0x100 800dd68: 2b00 cmp r3, #0 800dd6a: d131 bne.n 800ddd0 HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ) 800dd6c: 687b ldr r3, [r7, #4] 800dd6e: 681b ldr r3, [r3, #0] 800dd70: 6adb ldr r3, [r3, #44] @ 0x2c 800dd72: f403 0370 and.w r3, r3, #15728640 @ 0xf00000 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 800dd76: 2b00 cmp r3, #0 800dd78: d12a bne.n 800ddd0 { /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 800dd7a: e021 b.n 800ddc0 { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 800dd7c: 683b ldr r3, [r7, #0] 800dd7e: f1b3 3fff cmp.w r3, #4294967295 800dd82: d01d beq.n 800ddc0 { if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) 800dd84: 683b ldr r3, [r7, #0] 800dd86: 2b00 cmp r3, #0 800dd88: d007 beq.n 800dd9a 800dd8a: f7ff fde7 bl 800d95c 800dd8e: 4602 mov r2, r0 800dd90: 697b ldr r3, [r7, #20] 800dd92: 1ad3 subs r3, r2, r3 800dd94: 683a ldr r2, [r7, #0] 800dd96: 429a cmp r2, r3 800dd98: d212 bcs.n 800ddc0 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 800dd9a: 687b ldr r3, [r7, #4] 800dd9c: 681b ldr r3, [r3, #0] 800dd9e: 681b ldr r3, [r3, #0] 800dda0: f003 0302 and.w r3, r3, #2 800dda4: 2b00 cmp r3, #0 800dda6: d10b bne.n 800ddc0 { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 800dda8: 687b ldr r3, [r7, #4] 800ddaa: 6a9b ldr r3, [r3, #40] @ 0x28 800ddac: f043 0204 orr.w r2, r3, #4 800ddb0: 687b ldr r3, [r7, #4] 800ddb2: 629a str r2, [r3, #40] @ 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 800ddb4: 687b ldr r3, [r7, #4] 800ddb6: 2200 movs r2, #0 800ddb8: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_TIMEOUT; 800ddbc: 2303 movs r3, #3 800ddbe: e0a2 b.n 800df06 while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 800ddc0: 687b ldr r3, [r7, #4] 800ddc2: 681b ldr r3, [r3, #0] 800ddc4: 681b ldr r3, [r3, #0] 800ddc6: f003 0302 and.w r3, r3, #2 800ddca: 2b00 cmp r3, #0 800ddcc: d0d6 beq.n 800dd7c if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 800ddce: e070 b.n 800deb2 /* Replace polling by wait for maximum conversion time */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ /* and ADC maximum conversion cycles on all channels. */ /* - Wait for the expected ADC clock cycles delay */ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 800ddd0: 4b4f ldr r3, [pc, #316] @ (800df10 ) 800ddd2: 681c ldr r4, [r3, #0] 800ddd4: 2002 movs r0, #2 800ddd6: f002 fd05 bl 80107e4 800ddda: 4603 mov r3, r0 800dddc: fbb4 f2f3 udiv r2, r4, r3 * ADC_CONVCYCLES_MAX_RANGE(hadc) ); 800dde0: 687b ldr r3, [r7, #4] 800dde2: 681b ldr r3, [r3, #0] 800dde4: 6919 ldr r1, [r3, #16] 800dde6: 4b4b ldr r3, [pc, #300] @ (800df14 ) 800dde8: 400b ands r3, r1 800ddea: 2b00 cmp r3, #0 800ddec: d118 bne.n 800de20 800ddee: 687b ldr r3, [r7, #4] 800ddf0: 681b ldr r3, [r3, #0] 800ddf2: 68d9 ldr r1, [r3, #12] 800ddf4: 4b48 ldr r3, [pc, #288] @ (800df18 ) 800ddf6: 400b ands r3, r1 800ddf8: 2b00 cmp r3, #0 800ddfa: d111 bne.n 800de20 800ddfc: 687b ldr r3, [r7, #4] 800ddfe: 681b ldr r3, [r3, #0] 800de00: 6919 ldr r1, [r3, #16] 800de02: 4b46 ldr r3, [pc, #280] @ (800df1c ) 800de04: 400b ands r3, r1 800de06: 2b00 cmp r3, #0 800de08: d108 bne.n 800de1c 800de0a: 687b ldr r3, [r7, #4] 800de0c: 681b ldr r3, [r3, #0] 800de0e: 68d9 ldr r1, [r3, #12] 800de10: 4b43 ldr r3, [pc, #268] @ (800df20 ) 800de12: 400b ands r3, r1 800de14: 2b00 cmp r3, #0 800de16: d101 bne.n 800de1c 800de18: 2314 movs r3, #20 800de1a: e020 b.n 800de5e 800de1c: 2329 movs r3, #41 @ 0x29 800de1e: e01e b.n 800de5e 800de20: 687b ldr r3, [r7, #4] 800de22: 681b ldr r3, [r3, #0] 800de24: 6919 ldr r1, [r3, #16] 800de26: 4b3d ldr r3, [pc, #244] @ (800df1c ) 800de28: 400b ands r3, r1 800de2a: 2b00 cmp r3, #0 800de2c: d106 bne.n 800de3c 800de2e: 687b ldr r3, [r7, #4] 800de30: 681b ldr r3, [r3, #0] 800de32: 68d9 ldr r1, [r3, #12] 800de34: 4b3a ldr r3, [pc, #232] @ (800df20 ) 800de36: 400b ands r3, r1 800de38: 2b00 cmp r3, #0 800de3a: d00d beq.n 800de58 800de3c: 687b ldr r3, [r7, #4] 800de3e: 681b ldr r3, [r3, #0] 800de40: 6919 ldr r1, [r3, #16] 800de42: 4b38 ldr r3, [pc, #224] @ (800df24 ) 800de44: 400b ands r3, r1 800de46: 2b00 cmp r3, #0 800de48: d108 bne.n 800de5c 800de4a: 687b ldr r3, [r7, #4] 800de4c: 681b ldr r3, [r3, #0] 800de4e: 68d9 ldr r1, [r3, #12] 800de50: 4b34 ldr r3, [pc, #208] @ (800df24 ) 800de52: 400b ands r3, r1 800de54: 2b00 cmp r3, #0 800de56: d101 bne.n 800de5c 800de58: 2354 movs r3, #84 @ 0x54 800de5a: e000 b.n 800de5e 800de5c: 23fc movs r3, #252 @ 0xfc Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock 800de5e: fb02 f303 mul.w r3, r2, r3 800de62: 613b str r3, [r7, #16] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 800de64: e021 b.n 800deaa { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 800de66: 683b ldr r3, [r7, #0] 800de68: f1b3 3fff cmp.w r3, #4294967295 800de6c: d01a beq.n 800dea4 { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) 800de6e: 683b ldr r3, [r7, #0] 800de70: 2b00 cmp r3, #0 800de72: d007 beq.n 800de84 800de74: f7ff fd72 bl 800d95c 800de78: 4602 mov r2, r0 800de7a: 697b ldr r3, [r7, #20] 800de7c: 1ad3 subs r3, r2, r3 800de7e: 683a ldr r2, [r7, #0] 800de80: 429a cmp r2, r3 800de82: d20f bcs.n 800dea4 { /* New check to avoid false timeout detection in case of preemption */ if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 800de84: 68fb ldr r3, [r7, #12] 800de86: 693a ldr r2, [r7, #16] 800de88: 429a cmp r2, r3 800de8a: d90b bls.n 800dea4 { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 800de8c: 687b ldr r3, [r7, #4] 800de8e: 6a9b ldr r3, [r3, #40] @ 0x28 800de90: f043 0204 orr.w r2, r3, #4 800de94: 687b ldr r3, [r7, #4] 800de96: 629a str r2, [r3, #40] @ 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 800de98: 687b ldr r3, [r7, #4] 800de9a: 2200 movs r2, #0 800de9c: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_TIMEOUT; 800dea0: 2303 movs r3, #3 800dea2: e030 b.n 800df06 } } } Conversion_Timeout_CPU_cycles ++; 800dea4: 68fb ldr r3, [r7, #12] 800dea6: 3301 adds r3, #1 800dea8: 60fb str r3, [r7, #12] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 800deaa: 68fb ldr r3, [r7, #12] 800deac: 693a ldr r2, [r7, #16] 800deae: 429a cmp r2, r3 800deb0: d8d9 bhi.n 800de66 } } /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 800deb2: 687b ldr r3, [r7, #4] 800deb4: 681b ldr r3, [r3, #0] 800deb6: f06f 0212 mvn.w r2, #18 800deba: 601a str r2, [r3, #0] /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800debc: 687b ldr r3, [r7, #4] 800debe: 6a9b ldr r3, [r3, #40] @ 0x28 800dec0: f443 7200 orr.w r2, r3, #512 @ 0x200 800dec4: 687b ldr r3, [r7, #4] 800dec6: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800dec8: 687b ldr r3, [r7, #4] 800deca: 681b ldr r3, [r3, #0] 800decc: 689b ldr r3, [r3, #8] 800dece: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800ded2: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800ded6: d115 bne.n 800df04 (hadc->Init.ContinuousConvMode == DISABLE) ) 800ded8: 687b ldr r3, [r7, #4] 800deda: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800dedc: 2b00 cmp r3, #0 800dede: d111 bne.n 800df04 { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800dee0: 687b ldr r3, [r7, #4] 800dee2: 6a9b ldr r3, [r3, #40] @ 0x28 800dee4: f423 7280 bic.w r2, r3, #256 @ 0x100 800dee8: 687b ldr r3, [r7, #4] 800deea: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800deec: 687b ldr r3, [r7, #4] 800deee: 6a9b ldr r3, [r3, #40] @ 0x28 800def0: f403 5380 and.w r3, r3, #4096 @ 0x1000 800def4: 2b00 cmp r3, #0 800def6: d105 bne.n 800df04 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800def8: 687b ldr r3, [r7, #4] 800defa: 6a9b ldr r3, [r3, #40] @ 0x28 800defc: f043 0201 orr.w r2, r3, #1 800df00: 687b ldr r3, [r7, #4] 800df02: 629a str r2, [r3, #40] @ 0x28 } } /* Return ADC state */ return HAL_OK; 800df04: 2300 movs r3, #0 } 800df06: 4618 mov r0, r3 800df08: 371c adds r7, #28 800df0a: 46bd mov sp, r7 800df0c: bd90 pop {r4, r7, pc} 800df0e: bf00 nop 800df10: 2000006c .word 0x2000006c 800df14: 24924924 .word 0x24924924 800df18: 00924924 .word 0x00924924 800df1c: 12492492 .word 0x12492492 800df20: 00492492 .word 0x00492492 800df24: 00249249 .word 0x00249249 0800df28 : * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc: ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { 800df28: b480 push {r7} 800df2a: b083 sub sp, #12 800df2c: af00 add r7, sp, #0 800df2e: 6078 str r0, [r7, #4] /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; 800df30: 687b ldr r3, [r7, #4] 800df32: 681b ldr r3, [r3, #0] 800df34: 6cdb ldr r3, [r3, #76] @ 0x4c } 800df36: 4618 mov r0, r3 800df38: 370c adds r7, #12 800df3a: 46bd mov sp, r7 800df3c: bc80 pop {r7} 800df3e: 4770 bx lr 0800df40 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 800df40: b480 push {r7} 800df42: b085 sub sp, #20 800df44: af00 add r7, sp, #0 800df46: 6078 str r0, [r7, #4] 800df48: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800df4a: 2300 movs r3, #0 800df4c: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 800df4e: 2300 movs r3, #0 800df50: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 800df52: 687b ldr r3, [r7, #4] 800df54: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800df58: 2b01 cmp r3, #1 800df5a: d101 bne.n 800df60 800df5c: 2302 movs r3, #2 800df5e: e0dc b.n 800e11a 800df60: 687b ldr r3, [r7, #4] 800df62: 2201 movs r2, #1 800df64: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 800df68: 683b ldr r3, [r7, #0] 800df6a: 685b ldr r3, [r3, #4] 800df6c: 2b06 cmp r3, #6 800df6e: d81c bhi.n 800dfaa { MODIFY_REG(hadc->Instance->SQR3 , 800df70: 687b ldr r3, [r7, #4] 800df72: 681b ldr r3, [r3, #0] 800df74: 6b59 ldr r1, [r3, #52] @ 0x34 800df76: 683b ldr r3, [r7, #0] 800df78: 685a ldr r2, [r3, #4] 800df7a: 4613 mov r3, r2 800df7c: 009b lsls r3, r3, #2 800df7e: 4413 add r3, r2 800df80: 3b05 subs r3, #5 800df82: 221f movs r2, #31 800df84: fa02 f303 lsl.w r3, r2, r3 800df88: 43db mvns r3, r3 800df8a: 4019 ands r1, r3 800df8c: 683b ldr r3, [r7, #0] 800df8e: 6818 ldr r0, [r3, #0] 800df90: 683b ldr r3, [r7, #0] 800df92: 685a ldr r2, [r3, #4] 800df94: 4613 mov r3, r2 800df96: 009b lsls r3, r3, #2 800df98: 4413 add r3, r2 800df9a: 3b05 subs r3, #5 800df9c: fa00 f203 lsl.w r2, r0, r3 800dfa0: 687b ldr r3, [r7, #4] 800dfa2: 681b ldr r3, [r3, #0] 800dfa4: 430a orrs r2, r1 800dfa6: 635a str r2, [r3, #52] @ 0x34 800dfa8: e03c b.n 800e024 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 800dfaa: 683b ldr r3, [r7, #0] 800dfac: 685b ldr r3, [r3, #4] 800dfae: 2b0c cmp r3, #12 800dfb0: d81c bhi.n 800dfec { MODIFY_REG(hadc->Instance->SQR2 , 800dfb2: 687b ldr r3, [r7, #4] 800dfb4: 681b ldr r3, [r3, #0] 800dfb6: 6b19 ldr r1, [r3, #48] @ 0x30 800dfb8: 683b ldr r3, [r7, #0] 800dfba: 685a ldr r2, [r3, #4] 800dfbc: 4613 mov r3, r2 800dfbe: 009b lsls r3, r3, #2 800dfc0: 4413 add r3, r2 800dfc2: 3b23 subs r3, #35 @ 0x23 800dfc4: 221f movs r2, #31 800dfc6: fa02 f303 lsl.w r3, r2, r3 800dfca: 43db mvns r3, r3 800dfcc: 4019 ands r1, r3 800dfce: 683b ldr r3, [r7, #0] 800dfd0: 6818 ldr r0, [r3, #0] 800dfd2: 683b ldr r3, [r7, #0] 800dfd4: 685a ldr r2, [r3, #4] 800dfd6: 4613 mov r3, r2 800dfd8: 009b lsls r3, r3, #2 800dfda: 4413 add r3, r2 800dfdc: 3b23 subs r3, #35 @ 0x23 800dfde: fa00 f203 lsl.w r2, r0, r3 800dfe2: 687b ldr r3, [r7, #4] 800dfe4: 681b ldr r3, [r3, #0] 800dfe6: 430a orrs r2, r1 800dfe8: 631a str r2, [r3, #48] @ 0x30 800dfea: e01b b.n 800e024 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 800dfec: 687b ldr r3, [r7, #4] 800dfee: 681b ldr r3, [r3, #0] 800dff0: 6ad9 ldr r1, [r3, #44] @ 0x2c 800dff2: 683b ldr r3, [r7, #0] 800dff4: 685a ldr r2, [r3, #4] 800dff6: 4613 mov r3, r2 800dff8: 009b lsls r3, r3, #2 800dffa: 4413 add r3, r2 800dffc: 3b41 subs r3, #65 @ 0x41 800dffe: 221f movs r2, #31 800e000: fa02 f303 lsl.w r3, r2, r3 800e004: 43db mvns r3, r3 800e006: 4019 ands r1, r3 800e008: 683b ldr r3, [r7, #0] 800e00a: 6818 ldr r0, [r3, #0] 800e00c: 683b ldr r3, [r7, #0] 800e00e: 685a ldr r2, [r3, #4] 800e010: 4613 mov r3, r2 800e012: 009b lsls r3, r3, #2 800e014: 4413 add r3, r2 800e016: 3b41 subs r3, #65 @ 0x41 800e018: fa00 f203 lsl.w r2, r0, r3 800e01c: 687b ldr r3, [r7, #4] 800e01e: 681b ldr r3, [r3, #0] 800e020: 430a orrs r2, r1 800e022: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 800e024: 683b ldr r3, [r7, #0] 800e026: 681b ldr r3, [r3, #0] 800e028: 2b09 cmp r3, #9 800e02a: d91c bls.n 800e066 { MODIFY_REG(hadc->Instance->SMPR1 , 800e02c: 687b ldr r3, [r7, #4] 800e02e: 681b ldr r3, [r3, #0] 800e030: 68d9 ldr r1, [r3, #12] 800e032: 683b ldr r3, [r7, #0] 800e034: 681a ldr r2, [r3, #0] 800e036: 4613 mov r3, r2 800e038: 005b lsls r3, r3, #1 800e03a: 4413 add r3, r2 800e03c: 3b1e subs r3, #30 800e03e: 2207 movs r2, #7 800e040: fa02 f303 lsl.w r3, r2, r3 800e044: 43db mvns r3, r3 800e046: 4019 ands r1, r3 800e048: 683b ldr r3, [r7, #0] 800e04a: 6898 ldr r0, [r3, #8] 800e04c: 683b ldr r3, [r7, #0] 800e04e: 681a ldr r2, [r3, #0] 800e050: 4613 mov r3, r2 800e052: 005b lsls r3, r3, #1 800e054: 4413 add r3, r2 800e056: 3b1e subs r3, #30 800e058: fa00 f203 lsl.w r2, r0, r3 800e05c: 687b ldr r3, [r7, #4] 800e05e: 681b ldr r3, [r3, #0] 800e060: 430a orrs r2, r1 800e062: 60da str r2, [r3, #12] 800e064: e019 b.n 800e09a ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 800e066: 687b ldr r3, [r7, #4] 800e068: 681b ldr r3, [r3, #0] 800e06a: 6919 ldr r1, [r3, #16] 800e06c: 683b ldr r3, [r7, #0] 800e06e: 681a ldr r2, [r3, #0] 800e070: 4613 mov r3, r2 800e072: 005b lsls r3, r3, #1 800e074: 4413 add r3, r2 800e076: 2207 movs r2, #7 800e078: fa02 f303 lsl.w r3, r2, r3 800e07c: 43db mvns r3, r3 800e07e: 4019 ands r1, r3 800e080: 683b ldr r3, [r7, #0] 800e082: 6898 ldr r0, [r3, #8] 800e084: 683b ldr r3, [r7, #0] 800e086: 681a ldr r2, [r3, #0] 800e088: 4613 mov r3, r2 800e08a: 005b lsls r3, r3, #1 800e08c: 4413 add r3, r2 800e08e: fa00 f203 lsl.w r2, r0, r3 800e092: 687b ldr r3, [r7, #4] 800e094: 681b ldr r3, [r3, #0] 800e096: 430a orrs r2, r1 800e098: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800e09a: 683b ldr r3, [r7, #0] 800e09c: 681b ldr r3, [r3, #0] 800e09e: 2b10 cmp r3, #16 800e0a0: d003 beq.n 800e0aa (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 800e0a2: 683b ldr r3, [r7, #0] 800e0a4: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800e0a6: 2b11 cmp r3, #17 800e0a8: d132 bne.n 800e110 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 800e0aa: 687b ldr r3, [r7, #4] 800e0ac: 681b ldr r3, [r3, #0] 800e0ae: 4a1d ldr r2, [pc, #116] @ (800e124 ) 800e0b0: 4293 cmp r3, r2 800e0b2: d125 bne.n 800e100 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 800e0b4: 687b ldr r3, [r7, #4] 800e0b6: 681b ldr r3, [r3, #0] 800e0b8: 689b ldr r3, [r3, #8] 800e0ba: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800e0be: 2b00 cmp r3, #0 800e0c0: d126 bne.n 800e110 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 800e0c2: 687b ldr r3, [r7, #4] 800e0c4: 681b ldr r3, [r3, #0] 800e0c6: 689a ldr r2, [r3, #8] 800e0c8: 687b ldr r3, [r7, #4] 800e0ca: 681b ldr r3, [r3, #0] 800e0cc: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 800e0d0: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 800e0d2: 683b ldr r3, [r7, #0] 800e0d4: 681b ldr r3, [r3, #0] 800e0d6: 2b10 cmp r3, #16 800e0d8: d11a bne.n 800e110 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 800e0da: 4b13 ldr r3, [pc, #76] @ (800e128 ) 800e0dc: 681b ldr r3, [r3, #0] 800e0de: 4a13 ldr r2, [pc, #76] @ (800e12c ) 800e0e0: fba2 2303 umull r2, r3, r2, r3 800e0e4: 0c9a lsrs r2, r3, #18 800e0e6: 4613 mov r3, r2 800e0e8: 009b lsls r3, r3, #2 800e0ea: 4413 add r3, r2 800e0ec: 005b lsls r3, r3, #1 800e0ee: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e0f0: e002 b.n 800e0f8 { wait_loop_index--; 800e0f2: 68bb ldr r3, [r7, #8] 800e0f4: 3b01 subs r3, #1 800e0f6: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e0f8: 68bb ldr r3, [r7, #8] 800e0fa: 2b00 cmp r3, #0 800e0fc: d1f9 bne.n 800e0f2 800e0fe: e007 b.n 800e110 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800e100: 687b ldr r3, [r7, #4] 800e102: 6a9b ldr r3, [r3, #40] @ 0x28 800e104: f043 0220 orr.w r2, r3, #32 800e108: 687b ldr r3, [r7, #4] 800e10a: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800e10c: 2301 movs r3, #1 800e10e: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 800e110: 687b ldr r3, [r7, #4] 800e112: 2200 movs r2, #0 800e114: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800e118: 7bfb ldrb r3, [r7, #15] } 800e11a: 4618 mov r0, r3 800e11c: 3714 adds r7, #20 800e11e: 46bd mov sp, r7 800e120: bc80 pop {r7} 800e122: 4770 bx lr 800e124: 40012400 .word 0x40012400 800e128: 2000006c .word 0x2000006c 800e12c: 431bde83 .word 0x431bde83 0800e130 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 800e130: b580 push {r7, lr} 800e132: b084 sub sp, #16 800e134: af00 add r7, sp, #0 800e136: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800e138: 2300 movs r3, #0 800e13a: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 800e13c: 2300 movs r3, #0 800e13e: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 800e140: 687b ldr r3, [r7, #4] 800e142: 681b ldr r3, [r3, #0] 800e144: 689b ldr r3, [r3, #8] 800e146: f003 0301 and.w r3, r3, #1 800e14a: 2b01 cmp r3, #1 800e14c: d040 beq.n 800e1d0 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 800e14e: 687b ldr r3, [r7, #4] 800e150: 681b ldr r3, [r3, #0] 800e152: 689a ldr r2, [r3, #8] 800e154: 687b ldr r3, [r7, #4] 800e156: 681b ldr r3, [r3, #0] 800e158: f042 0201 orr.w r2, r2, #1 800e15c: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 800e15e: 4b1f ldr r3, [pc, #124] @ (800e1dc ) 800e160: 681b ldr r3, [r3, #0] 800e162: 4a1f ldr r2, [pc, #124] @ (800e1e0 ) 800e164: fba2 2303 umull r2, r3, r2, r3 800e168: 0c9b lsrs r3, r3, #18 800e16a: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e16c: e002 b.n 800e174 { wait_loop_index--; 800e16e: 68bb ldr r3, [r7, #8] 800e170: 3b01 subs r3, #1 800e172: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e174: 68bb ldr r3, [r7, #8] 800e176: 2b00 cmp r3, #0 800e178: d1f9 bne.n 800e16e } /* Get tick count */ tickstart = HAL_GetTick(); 800e17a: f7ff fbef bl 800d95c 800e17e: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 800e180: e01f b.n 800e1c2 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 800e182: f7ff fbeb bl 800d95c 800e186: 4602 mov r2, r0 800e188: 68fb ldr r3, [r7, #12] 800e18a: 1ad3 subs r3, r2, r3 800e18c: 2b02 cmp r3, #2 800e18e: d918 bls.n 800e1c2 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 800e190: 687b ldr r3, [r7, #4] 800e192: 681b ldr r3, [r3, #0] 800e194: 689b ldr r3, [r3, #8] 800e196: f003 0301 and.w r3, r3, #1 800e19a: 2b01 cmp r3, #1 800e19c: d011 beq.n 800e1c2 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800e19e: 687b ldr r3, [r7, #4] 800e1a0: 6a9b ldr r3, [r3, #40] @ 0x28 800e1a2: f043 0210 orr.w r2, r3, #16 800e1a6: 687b ldr r3, [r7, #4] 800e1a8: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e1aa: 687b ldr r3, [r7, #4] 800e1ac: 6adb ldr r3, [r3, #44] @ 0x2c 800e1ae: f043 0201 orr.w r2, r3, #1 800e1b2: 687b ldr r3, [r7, #4] 800e1b4: 62da str r2, [r3, #44] @ 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 800e1b6: 687b ldr r3, [r7, #4] 800e1b8: 2200 movs r2, #0 800e1ba: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e1be: 2301 movs r3, #1 800e1c0: e007 b.n 800e1d2 while(ADC_IS_ENABLE(hadc) == RESET) 800e1c2: 687b ldr r3, [r7, #4] 800e1c4: 681b ldr r3, [r3, #0] 800e1c6: 689b ldr r3, [r3, #8] 800e1c8: f003 0301 and.w r3, r3, #1 800e1cc: 2b01 cmp r3, #1 800e1ce: d1d8 bne.n 800e182 } } } /* Return HAL status */ return HAL_OK; 800e1d0: 2300 movs r3, #0 } 800e1d2: 4618 mov r0, r3 800e1d4: 3710 adds r7, #16 800e1d6: 46bd mov sp, r7 800e1d8: bd80 pop {r7, pc} 800e1da: bf00 nop 800e1dc: 2000006c .word 0x2000006c 800e1e0: 431bde83 .word 0x431bde83 0800e1e4 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 800e1e4: b580 push {r7, lr} 800e1e6: b084 sub sp, #16 800e1e8: af00 add r7, sp, #0 800e1ea: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800e1ec: 2300 movs r3, #0 800e1ee: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 800e1f0: 687b ldr r3, [r7, #4] 800e1f2: 681b ldr r3, [r3, #0] 800e1f4: 689b ldr r3, [r3, #8] 800e1f6: f003 0301 and.w r3, r3, #1 800e1fa: 2b01 cmp r3, #1 800e1fc: d12e bne.n 800e25c { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 800e1fe: 687b ldr r3, [r7, #4] 800e200: 681b ldr r3, [r3, #0] 800e202: 689a ldr r2, [r3, #8] 800e204: 687b ldr r3, [r7, #4] 800e206: 681b ldr r3, [r3, #0] 800e208: f022 0201 bic.w r2, r2, #1 800e20c: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 800e20e: f7ff fba5 bl 800d95c 800e212: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 800e214: e01b b.n 800e24e { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800e216: f7ff fba1 bl 800d95c 800e21a: 4602 mov r2, r0 800e21c: 68fb ldr r3, [r7, #12] 800e21e: 1ad3 subs r3, r2, r3 800e220: 2b02 cmp r3, #2 800e222: d914 bls.n 800e24e { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 800e224: 687b ldr r3, [r7, #4] 800e226: 681b ldr r3, [r3, #0] 800e228: 689b ldr r3, [r3, #8] 800e22a: f003 0301 and.w r3, r3, #1 800e22e: 2b01 cmp r3, #1 800e230: d10d bne.n 800e24e { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800e232: 687b ldr r3, [r7, #4] 800e234: 6a9b ldr r3, [r3, #40] @ 0x28 800e236: f043 0210 orr.w r2, r3, #16 800e23a: 687b ldr r3, [r7, #4] 800e23c: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e23e: 687b ldr r3, [r7, #4] 800e240: 6adb ldr r3, [r3, #44] @ 0x2c 800e242: f043 0201 orr.w r2, r3, #1 800e246: 687b ldr r3, [r7, #4] 800e248: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 800e24a: 2301 movs r3, #1 800e24c: e007 b.n 800e25e while(ADC_IS_ENABLE(hadc) != RESET) 800e24e: 687b ldr r3, [r7, #4] 800e250: 681b ldr r3, [r3, #0] 800e252: 689b ldr r3, [r3, #8] 800e254: f003 0301 and.w r3, r3, #1 800e258: 2b01 cmp r3, #1 800e25a: d0dc beq.n 800e216 } } } /* Return HAL status */ return HAL_OK; 800e25c: 2300 movs r3, #0 } 800e25e: 4618 mov r0, r3 800e260: 3710 adds r7, #16 800e262: 46bd mov sp, r7 800e264: bd80 pop {r7, pc} ... 0800e268 : * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { 800e268: b590 push {r4, r7, lr} 800e26a: b087 sub sp, #28 800e26c: af00 add r7, sp, #0 800e26e: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e270: 2300 movs r3, #0 800e272: 75fb strb r3, [r7, #23] uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; 800e274: 2300 movs r3, #0 800e276: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800e278: 687b ldr r3, [r7, #4] 800e27a: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e27e: 2b01 cmp r3, #1 800e280: d101 bne.n 800e286 800e282: 2302 movs r3, #2 800e284: e097 b.n 800e3b6 800e286: 687b ldr r3, [r7, #4] 800e288: 2201 movs r2, #1 800e28a: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* 1. Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800e28e: 6878 ldr r0, [r7, #4] 800e290: f7ff ffa8 bl 800e1e4 800e294: 4603 mov r3, r0 800e296: 75fb strb r3, [r7, #23] /* 2. Calibration prerequisite delay before starting the calibration. */ /* - ADC must be enabled for at least two ADC clock cycles */ tmp_hal_status = ADC_Enable(hadc); 800e298: 6878 ldr r0, [r7, #4] 800e29a: f7ff ff49 bl 800e130 800e29e: 4603 mov r3, r0 800e2a0: 75fb strb r3, [r7, #23] /* Check if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800e2a2: 7dfb ldrb r3, [r7, #23] 800e2a4: 2b00 cmp r3, #0 800e2a6: f040 8081 bne.w 800e3ac { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e2aa: 687b ldr r3, [r7, #4] 800e2ac: 6a9b ldr r3, [r3, #40] @ 0x28 800e2ae: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800e2b2: f023 0302 bic.w r3, r3, #2 800e2b6: f043 0202 orr.w r2, r3, #2 800e2ba: 687b ldr r3, [r7, #4] 800e2bc: 629a str r2, [r3, #40] @ 0x28 /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 800e2be: 4b40 ldr r3, [pc, #256] @ (800e3c0 ) 800e2c0: 681c ldr r4, [r3, #0] 800e2c2: 2002 movs r0, #2 800e2c4: f002 fa8e bl 80107e4 800e2c8: 4603 mov r3, r0 800e2ca: fbb4 f3f3 udiv r3, r4, r3 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 800e2ce: 005b lsls r3, r3, #1 wait_loop_index = ((SystemCoreClock 800e2d0: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800e2d2: e002 b.n 800e2da { wait_loop_index--; 800e2d4: 68fb ldr r3, [r7, #12] 800e2d6: 3b01 subs r3, #1 800e2d8: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800e2da: 68fb ldr r3, [r7, #12] 800e2dc: 2b00 cmp r3, #0 800e2de: d1f9 bne.n 800e2d4 } /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 800e2e0: 687b ldr r3, [r7, #4] 800e2e2: 681b ldr r3, [r3, #0] 800e2e4: 689a ldr r2, [r3, #8] 800e2e6: 687b ldr r3, [r7, #4] 800e2e8: 681b ldr r3, [r3, #0] 800e2ea: f042 0208 orr.w r2, r2, #8 800e2ee: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800e2f0: f7ff fb34 bl 800d95c 800e2f4: 6138 str r0, [r7, #16] /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800e2f6: e01b b.n 800e330 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800e2f8: f7ff fb30 bl 800d95c 800e2fc: 4602 mov r2, r0 800e2fe: 693b ldr r3, [r7, #16] 800e300: 1ad3 subs r3, r2, r3 800e302: 2b0a cmp r3, #10 800e304: d914 bls.n 800e330 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800e306: 687b ldr r3, [r7, #4] 800e308: 681b ldr r3, [r3, #0] 800e30a: 689b ldr r3, [r3, #8] 800e30c: f003 0308 and.w r3, r3, #8 800e310: 2b00 cmp r3, #0 800e312: d00d beq.n 800e330 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800e314: 687b ldr r3, [r7, #4] 800e316: 6a9b ldr r3, [r3, #40] @ 0x28 800e318: f023 0312 bic.w r3, r3, #18 800e31c: f043 0210 orr.w r2, r3, #16 800e320: 687b ldr r3, [r7, #4] 800e322: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800e324: 687b ldr r3, [r7, #4] 800e326: 2200 movs r2, #0 800e328: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e32c: 2301 movs r3, #1 800e32e: e042 b.n 800e3b6 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800e330: 687b ldr r3, [r7, #4] 800e332: 681b ldr r3, [r3, #0] 800e334: 689b ldr r3, [r3, #8] 800e336: f003 0308 and.w r3, r3, #8 800e33a: 2b00 cmp r3, #0 800e33c: d1dc bne.n 800e2f8 } } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 800e33e: 687b ldr r3, [r7, #4] 800e340: 681b ldr r3, [r3, #0] 800e342: 689a ldr r2, [r3, #8] 800e344: 687b ldr r3, [r7, #4] 800e346: 681b ldr r3, [r3, #0] 800e348: f042 0204 orr.w r2, r2, #4 800e34c: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800e34e: f7ff fb05 bl 800d95c 800e352: 6138 str r0, [r7, #16] /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800e354: e01b b.n 800e38e { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800e356: f7ff fb01 bl 800d95c 800e35a: 4602 mov r2, r0 800e35c: 693b ldr r3, [r7, #16] 800e35e: 1ad3 subs r3, r2, r3 800e360: 2b0a cmp r3, #10 800e362: d914 bls.n 800e38e { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800e364: 687b ldr r3, [r7, #4] 800e366: 681b ldr r3, [r3, #0] 800e368: 689b ldr r3, [r3, #8] 800e36a: f003 0304 and.w r3, r3, #4 800e36e: 2b00 cmp r3, #0 800e370: d00d beq.n 800e38e { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800e372: 687b ldr r3, [r7, #4] 800e374: 6a9b ldr r3, [r3, #40] @ 0x28 800e376: f023 0312 bic.w r3, r3, #18 800e37a: f043 0210 orr.w r2, r3, #16 800e37e: 687b ldr r3, [r7, #4] 800e380: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800e382: 687b ldr r3, [r7, #4] 800e384: 2200 movs r2, #0 800e386: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e38a: 2301 movs r3, #1 800e38c: e013 b.n 800e3b6 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800e38e: 687b ldr r3, [r7, #4] 800e390: 681b ldr r3, [r3, #0] 800e392: 689b ldr r3, [r3, #8] 800e394: f003 0304 and.w r3, r3, #4 800e398: 2b00 cmp r3, #0 800e39a: d1dc bne.n 800e356 } } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e39c: 687b ldr r3, [r7, #4] 800e39e: 6a9b ldr r3, [r3, #40] @ 0x28 800e3a0: f023 0303 bic.w r3, r3, #3 800e3a4: f043 0201 orr.w r2, r3, #1 800e3a8: 687b ldr r3, [r7, #4] 800e3aa: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 800e3ac: 687b ldr r3, [r7, #4] 800e3ae: 2200 movs r2, #0 800e3b0: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800e3b4: 7dfb ldrb r3, [r7, #23] } 800e3b6: 4618 mov r0, r3 800e3b8: 371c adds r7, #28 800e3ba: 46bd mov sp, r7 800e3bc: bd90 pop {r4, r7, pc} 800e3be: bf00 nop 800e3c0: 2000006c .word 0x2000006c 0800e3c4 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { 800e3c4: b580 push {r7, lr} 800e3c6: b084 sub sp, #16 800e3c8: af00 add r7, sp, #0 800e3ca: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) 800e3cc: 687b ldr r3, [r7, #4] 800e3ce: 2b00 cmp r3, #0 800e3d0: d101 bne.n 800e3d6 { return HAL_ERROR; 800e3d2: 2301 movs r3, #1 800e3d4: e0ed b.n 800e5b2 /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) 800e3d6: 687b ldr r3, [r7, #4] 800e3d8: f893 3020 ldrb.w r3, [r3, #32] 800e3dc: b2db uxtb r3, r3 800e3de: 2b00 cmp r3, #0 800e3e0: d102 bne.n 800e3e8 { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); 800e3e2: 6878 ldr r0, [r7, #4] 800e3e4: f7fb fb0a bl 80099fc } #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800e3e8: 687b ldr r3, [r7, #4] 800e3ea: 681b ldr r3, [r3, #0] 800e3ec: 681a ldr r2, [r3, #0] 800e3ee: 687b ldr r3, [r7, #4] 800e3f0: 681b ldr r3, [r3, #0] 800e3f2: f042 0201 orr.w r2, r2, #1 800e3f6: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800e3f8: f7ff fab0 bl 800d95c 800e3fc: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800e3fe: e012 b.n 800e426 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800e400: f7ff faac bl 800d95c 800e404: 4602 mov r2, r0 800e406: 68fb ldr r3, [r7, #12] 800e408: 1ad3 subs r3, r2, r3 800e40a: 2b0a cmp r3, #10 800e40c: d90b bls.n 800e426 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800e40e: 687b ldr r3, [r7, #4] 800e410: 6a5b ldr r3, [r3, #36] @ 0x24 800e412: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800e416: 687b ldr r3, [r7, #4] 800e418: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800e41a: 687b ldr r3, [r7, #4] 800e41c: 2205 movs r2, #5 800e41e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800e422: 2301 movs r3, #1 800e424: e0c5 b.n 800e5b2 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800e426: 687b ldr r3, [r7, #4] 800e428: 681b ldr r3, [r3, #0] 800e42a: 685b ldr r3, [r3, #4] 800e42c: f003 0301 and.w r3, r3, #1 800e430: 2b00 cmp r3, #0 800e432: d0e5 beq.n 800e400 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800e434: 687b ldr r3, [r7, #4] 800e436: 681b ldr r3, [r3, #0] 800e438: 681a ldr r2, [r3, #0] 800e43a: 687b ldr r3, [r7, #4] 800e43c: 681b ldr r3, [r3, #0] 800e43e: f022 0202 bic.w r2, r2, #2 800e442: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800e444: f7ff fa8a bl 800d95c 800e448: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800e44a: e012 b.n 800e472 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800e44c: f7ff fa86 bl 800d95c 800e450: 4602 mov r2, r0 800e452: 68fb ldr r3, [r7, #12] 800e454: 1ad3 subs r3, r2, r3 800e456: 2b0a cmp r3, #10 800e458: d90b bls.n 800e472 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800e45a: 687b ldr r3, [r7, #4] 800e45c: 6a5b ldr r3, [r3, #36] @ 0x24 800e45e: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800e462: 687b ldr r3, [r7, #4] 800e464: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800e466: 687b ldr r3, [r7, #4] 800e468: 2205 movs r2, #5 800e46a: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800e46e: 2301 movs r3, #1 800e470: e09f b.n 800e5b2 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800e472: 687b ldr r3, [r7, #4] 800e474: 681b ldr r3, [r3, #0] 800e476: 685b ldr r3, [r3, #4] 800e478: f003 0302 and.w r3, r3, #2 800e47c: 2b00 cmp r3, #0 800e47e: d1e5 bne.n 800e44c } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) 800e480: 687b ldr r3, [r7, #4] 800e482: 7e1b ldrb r3, [r3, #24] 800e484: 2b01 cmp r3, #1 800e486: d108 bne.n 800e49a { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800e488: 687b ldr r3, [r7, #4] 800e48a: 681b ldr r3, [r3, #0] 800e48c: 681a ldr r2, [r3, #0] 800e48e: 687b ldr r3, [r7, #4] 800e490: 681b ldr r3, [r3, #0] 800e492: f042 0280 orr.w r2, r2, #128 @ 0x80 800e496: 601a str r2, [r3, #0] 800e498: e007 b.n 800e4aa } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800e49a: 687b ldr r3, [r7, #4] 800e49c: 681b ldr r3, [r3, #0] 800e49e: 681a ldr r2, [r3, #0] 800e4a0: 687b ldr r3, [r7, #4] 800e4a2: 681b ldr r3, [r3, #0] 800e4a4: f022 0280 bic.w r2, r2, #128 @ 0x80 800e4a8: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) 800e4aa: 687b ldr r3, [r7, #4] 800e4ac: 7e5b ldrb r3, [r3, #25] 800e4ae: 2b01 cmp r3, #1 800e4b0: d108 bne.n 800e4c4 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800e4b2: 687b ldr r3, [r7, #4] 800e4b4: 681b ldr r3, [r3, #0] 800e4b6: 681a ldr r2, [r3, #0] 800e4b8: 687b ldr r3, [r7, #4] 800e4ba: 681b ldr r3, [r3, #0] 800e4bc: f042 0240 orr.w r2, r2, #64 @ 0x40 800e4c0: 601a str r2, [r3, #0] 800e4c2: e007 b.n 800e4d4 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800e4c4: 687b ldr r3, [r7, #4] 800e4c6: 681b ldr r3, [r3, #0] 800e4c8: 681a ldr r2, [r3, #0] 800e4ca: 687b ldr r3, [r7, #4] 800e4cc: 681b ldr r3, [r3, #0] 800e4ce: f022 0240 bic.w r2, r2, #64 @ 0x40 800e4d2: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) 800e4d4: 687b ldr r3, [r7, #4] 800e4d6: 7e9b ldrb r3, [r3, #26] 800e4d8: 2b01 cmp r3, #1 800e4da: d108 bne.n 800e4ee { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800e4dc: 687b ldr r3, [r7, #4] 800e4de: 681b ldr r3, [r3, #0] 800e4e0: 681a ldr r2, [r3, #0] 800e4e2: 687b ldr r3, [r7, #4] 800e4e4: 681b ldr r3, [r3, #0] 800e4e6: f042 0220 orr.w r2, r2, #32 800e4ea: 601a str r2, [r3, #0] 800e4ec: e007 b.n 800e4fe } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800e4ee: 687b ldr r3, [r7, #4] 800e4f0: 681b ldr r3, [r3, #0] 800e4f2: 681a ldr r2, [r3, #0] 800e4f4: 687b ldr r3, [r7, #4] 800e4f6: 681b ldr r3, [r3, #0] 800e4f8: f022 0220 bic.w r2, r2, #32 800e4fc: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) 800e4fe: 687b ldr r3, [r7, #4] 800e500: 7edb ldrb r3, [r3, #27] 800e502: 2b01 cmp r3, #1 800e504: d108 bne.n 800e518 { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800e506: 687b ldr r3, [r7, #4] 800e508: 681b ldr r3, [r3, #0] 800e50a: 681a ldr r2, [r3, #0] 800e50c: 687b ldr r3, [r7, #4] 800e50e: 681b ldr r3, [r3, #0] 800e510: f022 0210 bic.w r2, r2, #16 800e514: 601a str r2, [r3, #0] 800e516: e007 b.n 800e528 } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800e518: 687b ldr r3, [r7, #4] 800e51a: 681b ldr r3, [r3, #0] 800e51c: 681a ldr r2, [r3, #0] 800e51e: 687b ldr r3, [r7, #4] 800e520: 681b ldr r3, [r3, #0] 800e522: f042 0210 orr.w r2, r2, #16 800e526: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) 800e528: 687b ldr r3, [r7, #4] 800e52a: 7f1b ldrb r3, [r3, #28] 800e52c: 2b01 cmp r3, #1 800e52e: d108 bne.n 800e542 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800e530: 687b ldr r3, [r7, #4] 800e532: 681b ldr r3, [r3, #0] 800e534: 681a ldr r2, [r3, #0] 800e536: 687b ldr r3, [r7, #4] 800e538: 681b ldr r3, [r3, #0] 800e53a: f042 0208 orr.w r2, r2, #8 800e53e: 601a str r2, [r3, #0] 800e540: e007 b.n 800e552 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800e542: 687b ldr r3, [r7, #4] 800e544: 681b ldr r3, [r3, #0] 800e546: 681a ldr r2, [r3, #0] 800e548: 687b ldr r3, [r7, #4] 800e54a: 681b ldr r3, [r3, #0] 800e54c: f022 0208 bic.w r2, r2, #8 800e550: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) 800e552: 687b ldr r3, [r7, #4] 800e554: 7f5b ldrb r3, [r3, #29] 800e556: 2b01 cmp r3, #1 800e558: d108 bne.n 800e56c { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800e55a: 687b ldr r3, [r7, #4] 800e55c: 681b ldr r3, [r3, #0] 800e55e: 681a ldr r2, [r3, #0] 800e560: 687b ldr r3, [r7, #4] 800e562: 681b ldr r3, [r3, #0] 800e564: f042 0204 orr.w r2, r2, #4 800e568: 601a str r2, [r3, #0] 800e56a: e007 b.n 800e57c } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800e56c: 687b ldr r3, [r7, #4] 800e56e: 681b ldr r3, [r3, #0] 800e570: 681a ldr r2, [r3, #0] 800e572: 687b ldr r3, [r7, #4] 800e574: 681b ldr r3, [r3, #0] 800e576: f022 0204 bic.w r2, r2, #4 800e57a: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | 800e57c: 687b ldr r3, [r7, #4] 800e57e: 689a ldr r2, [r3, #8] 800e580: 687b ldr r3, [r7, #4] 800e582: 68db ldr r3, [r3, #12] 800e584: 431a orrs r2, r3 800e586: 687b ldr r3, [r7, #4] 800e588: 691b ldr r3, [r3, #16] 800e58a: 431a orrs r2, r3 800e58c: 687b ldr r3, [r7, #4] 800e58e: 695b ldr r3, [r3, #20] 800e590: ea42 0103 orr.w r1, r2, r3 800e594: 687b ldr r3, [r7, #4] 800e596: 685b ldr r3, [r3, #4] 800e598: 1e5a subs r2, r3, #1 800e59a: 687b ldr r3, [r7, #4] 800e59c: 681b ldr r3, [r3, #0] 800e59e: 430a orrs r2, r1 800e5a0: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800e5a2: 687b ldr r3, [r7, #4] 800e5a4: 2200 movs r2, #0 800e5a6: 625a str r2, [r3, #36] @ 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; 800e5a8: 687b ldr r3, [r7, #4] 800e5aa: 2201 movs r2, #1 800e5ac: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800e5b0: 2300 movs r3, #0 } 800e5b2: 4618 mov r0, r3 800e5b4: 3710 adds r7, #16 800e5b6: 46bd mov sp, r7 800e5b8: bd80 pop {r7, pc} ... 0800e5bc : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { 800e5bc: b480 push {r7} 800e5be: b087 sub sp, #28 800e5c0: af00 add r7, sp, #0 800e5c2: 6078 str r0, [r7, #4] 800e5c4: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; 800e5c6: 687b ldr r3, [r7, #4] 800e5c8: 681b ldr r3, [r3, #0] 800e5ca: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; 800e5cc: 687b ldr r3, [r7, #4] 800e5ce: f893 3020 ldrb.w r3, [r3, #32] 800e5d2: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || 800e5d4: 7cfb ldrb r3, [r7, #19] 800e5d6: 2b01 cmp r3, #1 800e5d8: d003 beq.n 800e5e2 800e5da: 7cfb ldrb r3, [r7, #19] 800e5dc: 2b02 cmp r3, #2 800e5de: f040 80be bne.w 800e75e assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); #if defined(CAN2) /* CAN1 and CAN2 are dual instances with 28 common filters banks */ /* Select master instance to access the filter banks */ can_ip = CAN1; 800e5e2: 4b65 ldr r3, [pc, #404] @ (800e778 ) 800e5e4: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); #endif /* CAN3 */ /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); 800e5e6: 697b ldr r3, [r7, #20] 800e5e8: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800e5ec: f043 0201 orr.w r2, r3, #1 800e5f0: 697b ldr r3, [r7, #20] 800e5f2: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #if defined(CAN2) /* Select the start filter number of CAN2 slave instance */ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); 800e5f6: 697b ldr r3, [r7, #20] 800e5f8: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800e5fc: f423 527c bic.w r2, r3, #16128 @ 0x3f00 800e600: 697b ldr r3, [r7, #20] 800e602: f8c3 2200 str.w r2, [r3, #512] @ 0x200 SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); 800e606: 697b ldr r3, [r7, #20] 800e608: f8d3 2200 ldr.w r2, [r3, #512] @ 0x200 800e60c: 683b ldr r3, [r7, #0] 800e60e: 6a5b ldr r3, [r3, #36] @ 0x24 800e610: 021b lsls r3, r3, #8 800e612: 431a orrs r2, r3 800e614: 697b ldr r3, [r7, #20] 800e616: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #endif /* CAN3 */ /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); 800e61a: 683b ldr r3, [r7, #0] 800e61c: 695b ldr r3, [r3, #20] 800e61e: f003 031f and.w r3, r3, #31 800e622: 2201 movs r2, #1 800e624: fa02 f303 lsl.w r3, r2, r3 800e628: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); 800e62a: 697b ldr r3, [r7, #20] 800e62c: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800e630: 68fb ldr r3, [r7, #12] 800e632: 43db mvns r3, r3 800e634: 401a ands r2, r3 800e636: 697b ldr r3, [r7, #20] 800e638: f8c3 221c str.w r2, [r3, #540] @ 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) 800e63c: 683b ldr r3, [r7, #0] 800e63e: 69db ldr r3, [r3, #28] 800e640: 2b00 cmp r3, #0 800e642: d123 bne.n 800e68c { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); 800e644: 697b ldr r3, [r7, #20] 800e646: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800e64a: 68fb ldr r3, [r7, #12] 800e64c: 43db mvns r3, r3 800e64e: 401a ands r2, r3 800e650: 697b ldr r3, [r7, #20] 800e652: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800e656: 683b ldr r3, [r7, #0] 800e658: 68db ldr r3, [r3, #12] 800e65a: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800e65c: 683b ldr r3, [r7, #0] 800e65e: 685b ldr r3, [r3, #4] 800e660: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800e662: 683a ldr r2, [r7, #0] 800e664: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800e666: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800e668: 697b ldr r3, [r7, #20] 800e66a: 3248 adds r2, #72 @ 0x48 800e66c: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800e670: 683b ldr r3, [r7, #0] 800e672: 689b ldr r3, [r3, #8] 800e674: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); 800e676: 683b ldr r3, [r7, #0] 800e678: 681b ldr r3, [r3, #0] 800e67a: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800e67c: 683b ldr r3, [r7, #0] 800e67e: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800e680: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800e682: 6979 ldr r1, [r7, #20] 800e684: 3348 adds r3, #72 @ 0x48 800e686: 00db lsls r3, r3, #3 800e688: 440b add r3, r1 800e68a: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) 800e68c: 683b ldr r3, [r7, #0] 800e68e: 69db ldr r3, [r3, #28] 800e690: 2b01 cmp r3, #1 800e692: d122 bne.n 800e6da { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); 800e694: 697b ldr r3, [r7, #20] 800e696: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800e69a: 68fb ldr r3, [r7, #12] 800e69c: 431a orrs r2, r3 800e69e: 697b ldr r3, [r7, #20] 800e6a0: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800e6a4: 683b ldr r3, [r7, #0] 800e6a6: 681b ldr r3, [r3, #0] 800e6a8: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800e6aa: 683b ldr r3, [r7, #0] 800e6ac: 685b ldr r3, [r3, #4] 800e6ae: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800e6b0: 683a ldr r2, [r7, #0] 800e6b2: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800e6b4: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800e6b6: 697b ldr r3, [r7, #20] 800e6b8: 3248 adds r2, #72 @ 0x48 800e6ba: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800e6be: 683b ldr r3, [r7, #0] 800e6c0: 689b ldr r3, [r3, #8] 800e6c2: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); 800e6c4: 683b ldr r3, [r7, #0] 800e6c6: 68db ldr r3, [r3, #12] 800e6c8: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800e6ca: 683b ldr r3, [r7, #0] 800e6cc: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800e6ce: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800e6d0: 6979 ldr r1, [r7, #20] 800e6d2: 3348 adds r3, #72 @ 0x48 800e6d4: 00db lsls r3, r3, #3 800e6d6: 440b add r3, r1 800e6d8: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) 800e6da: 683b ldr r3, [r7, #0] 800e6dc: 699b ldr r3, [r3, #24] 800e6de: 2b00 cmp r3, #0 800e6e0: d109 bne.n 800e6f6 { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); 800e6e2: 697b ldr r3, [r7, #20] 800e6e4: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800e6e8: 68fb ldr r3, [r7, #12] 800e6ea: 43db mvns r3, r3 800e6ec: 401a ands r2, r3 800e6ee: 697b ldr r3, [r7, #20] 800e6f0: f8c3 2204 str.w r2, [r3, #516] @ 0x204 800e6f4: e007 b.n 800e706 } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); 800e6f6: 697b ldr r3, [r7, #20] 800e6f8: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800e6fc: 68fb ldr r3, [r7, #12] 800e6fe: 431a orrs r2, r3 800e700: 697b ldr r3, [r7, #20] 800e702: f8c3 2204 str.w r2, [r3, #516] @ 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) 800e706: 683b ldr r3, [r7, #0] 800e708: 691b ldr r3, [r3, #16] 800e70a: 2b00 cmp r3, #0 800e70c: d109 bne.n 800e722 { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); 800e70e: 697b ldr r3, [r7, #20] 800e710: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800e714: 68fb ldr r3, [r7, #12] 800e716: 43db mvns r3, r3 800e718: 401a ands r2, r3 800e71a: 697b ldr r3, [r7, #20] 800e71c: f8c3 2214 str.w r2, [r3, #532] @ 0x214 800e720: e007 b.n 800e732 } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); 800e722: 697b ldr r3, [r7, #20] 800e724: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800e728: 68fb ldr r3, [r7, #12] 800e72a: 431a orrs r2, r3 800e72c: 697b ldr r3, [r7, #20] 800e72e: f8c3 2214 str.w r2, [r3, #532] @ 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) 800e732: 683b ldr r3, [r7, #0] 800e734: 6a1b ldr r3, [r3, #32] 800e736: 2b01 cmp r3, #1 800e738: d107 bne.n 800e74a { SET_BIT(can_ip->FA1R, filternbrbitpos); 800e73a: 697b ldr r3, [r7, #20] 800e73c: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800e740: 68fb ldr r3, [r7, #12] 800e742: 431a orrs r2, r3 800e744: 697b ldr r3, [r7, #20] 800e746: f8c3 221c str.w r2, [r3, #540] @ 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); 800e74a: 697b ldr r3, [r7, #20] 800e74c: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800e750: f023 0201 bic.w r2, r3, #1 800e754: 697b ldr r3, [r7, #20] 800e756: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Return function status */ return HAL_OK; 800e75a: 2300 movs r3, #0 800e75c: e006 b.n 800e76c } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800e75e: 687b ldr r3, [r7, #4] 800e760: 6a5b ldr r3, [r3, #36] @ 0x24 800e762: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800e766: 687b ldr r3, [r7, #4] 800e768: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e76a: 2301 movs r3, #1 } } 800e76c: 4618 mov r0, r3 800e76e: 371c adds r7, #28 800e770: 46bd mov sp, r7 800e772: bc80 pop {r7} 800e774: 4770 bx lr 800e776: bf00 nop 800e778: 40006400 .word 0x40006400 0800e77c : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { 800e77c: b580 push {r7, lr} 800e77e: b084 sub sp, #16 800e780: af00 add r7, sp, #0 800e782: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) 800e784: 687b ldr r3, [r7, #4] 800e786: f893 3020 ldrb.w r3, [r3, #32] 800e78a: b2db uxtb r3, r3 800e78c: 2b01 cmp r3, #1 800e78e: d12e bne.n 800e7ee { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; 800e790: 687b ldr r3, [r7, #4] 800e792: 2202 movs r2, #2 800e794: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800e798: 687b ldr r3, [r7, #4] 800e79a: 681b ldr r3, [r3, #0] 800e79c: 681a ldr r2, [r3, #0] 800e79e: 687b ldr r3, [r7, #4] 800e7a0: 681b ldr r3, [r3, #0] 800e7a2: f022 0201 bic.w r2, r2, #1 800e7a6: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800e7a8: f7ff f8d8 bl 800d95c 800e7ac: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800e7ae: e012 b.n 800e7d6 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800e7b0: f7ff f8d4 bl 800d95c 800e7b4: 4602 mov r2, r0 800e7b6: 68fb ldr r3, [r7, #12] 800e7b8: 1ad3 subs r3, r2, r3 800e7ba: 2b0a cmp r3, #10 800e7bc: d90b bls.n 800e7d6 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800e7be: 687b ldr r3, [r7, #4] 800e7c0: 6a5b ldr r3, [r3, #36] @ 0x24 800e7c2: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800e7c6: 687b ldr r3, [r7, #4] 800e7c8: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800e7ca: 687b ldr r3, [r7, #4] 800e7cc: 2205 movs r2, #5 800e7ce: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800e7d2: 2301 movs r3, #1 800e7d4: e012 b.n 800e7fc while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800e7d6: 687b ldr r3, [r7, #4] 800e7d8: 681b ldr r3, [r3, #0] 800e7da: 685b ldr r3, [r3, #4] 800e7dc: f003 0301 and.w r3, r3, #1 800e7e0: 2b00 cmp r3, #0 800e7e2: d1e5 bne.n 800e7b0 } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800e7e4: 687b ldr r3, [r7, #4] 800e7e6: 2200 movs r2, #0 800e7e8: 625a str r2, [r3, #36] @ 0x24 /* Return function status */ return HAL_OK; 800e7ea: 2300 movs r3, #0 800e7ec: e006 b.n 800e7fc } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; 800e7ee: 687b ldr r3, [r7, #4] 800e7f0: 6a5b ldr r3, [r3, #36] @ 0x24 800e7f2: f443 2200 orr.w r2, r3, #524288 @ 0x80000 800e7f6: 687b ldr r3, [r7, #4] 800e7f8: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e7fa: 2301 movs r3, #1 } } 800e7fc: 4618 mov r0, r3 800e7fe: 3710 adds r7, #16 800e800: 46bd mov sp, r7 800e802: bd80 pop {r7, pc} 0800e804 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { 800e804: b580 push {r7, lr} 800e806: b084 sub sp, #16 800e808: af00 add r7, sp, #0 800e80a: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_LISTENING) 800e80c: 687b ldr r3, [r7, #4] 800e80e: f893 3020 ldrb.w r3, [r3, #32] 800e812: b2db uxtb r3, r3 800e814: 2b02 cmp r3, #2 800e816: d133 bne.n 800e880 { /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800e818: 687b ldr r3, [r7, #4] 800e81a: 681b ldr r3, [r3, #0] 800e81c: 681a ldr r2, [r3, #0] 800e81e: 687b ldr r3, [r7, #4] 800e820: 681b ldr r3, [r3, #0] 800e822: f042 0201 orr.w r2, r2, #1 800e826: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800e828: f7ff f898 bl 800d95c 800e82c: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800e82e: e012 b.n 800e856 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800e830: f7ff f894 bl 800d95c 800e834: 4602 mov r2, r0 800e836: 68fb ldr r3, [r7, #12] 800e838: 1ad3 subs r3, r2, r3 800e83a: 2b0a cmp r3, #10 800e83c: d90b bls.n 800e856 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800e83e: 687b ldr r3, [r7, #4] 800e840: 6a5b ldr r3, [r3, #36] @ 0x24 800e842: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800e846: 687b ldr r3, [r7, #4] 800e848: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800e84a: 687b ldr r3, [r7, #4] 800e84c: 2205 movs r2, #5 800e84e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800e852: 2301 movs r3, #1 800e854: e01b b.n 800e88e while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800e856: 687b ldr r3, [r7, #4] 800e858: 681b ldr r3, [r3, #0] 800e85a: 685b ldr r3, [r3, #4] 800e85c: f003 0301 and.w r3, r3, #1 800e860: 2b00 cmp r3, #0 800e862: d0e5 beq.n 800e830 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800e864: 687b ldr r3, [r7, #4] 800e866: 681b ldr r3, [r3, #0] 800e868: 681a ldr r2, [r3, #0] 800e86a: 687b ldr r3, [r7, #4] 800e86c: 681b ldr r3, [r3, #0] 800e86e: f022 0202 bic.w r2, r2, #2 800e872: 601a str r2, [r3, #0] /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_READY; 800e874: 687b ldr r3, [r7, #4] 800e876: 2201 movs r2, #1 800e878: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800e87c: 2300 movs r3, #0 800e87e: e006 b.n 800e88e } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; 800e880: 687b ldr r3, [r7, #4] 800e882: 6a5b ldr r3, [r3, #36] @ 0x24 800e884: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800e888: 687b ldr r3, [r7, #4] 800e88a: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e88c: 2301 movs r3, #1 } } 800e88e: 4618 mov r0, r3 800e890: 3710 adds r7, #16 800e892: 46bd mov sp, r7 800e894: bd80 pop {r7, pc} 0800e896 : * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, const uint8_t aData[], uint32_t *pTxMailbox) { 800e896: b480 push {r7} 800e898: b089 sub sp, #36 @ 0x24 800e89a: af00 add r7, sp, #0 800e89c: 60f8 str r0, [r7, #12] 800e89e: 60b9 str r1, [r7, #8] 800e8a0: 607a str r2, [r7, #4] 800e8a2: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; 800e8a4: 68fb ldr r3, [r7, #12] 800e8a6: f893 3020 ldrb.w r3, [r3, #32] 800e8aa: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); 800e8ac: 68fb ldr r3, [r7, #12] 800e8ae: 681b ldr r3, [r3, #0] 800e8b0: 689b ldr r3, [r3, #8] 800e8b2: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || 800e8b4: 7ffb ldrb r3, [r7, #31] 800e8b6: 2b01 cmp r3, #1 800e8b8: d003 beq.n 800e8c2 800e8ba: 7ffb ldrb r3, [r7, #31] 800e8bc: 2b02 cmp r3, #2 800e8be: f040 80ad bne.w 800ea1c (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || 800e8c2: 69bb ldr r3, [r7, #24] 800e8c4: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800e8c8: 2b00 cmp r3, #0 800e8ca: d10a bne.n 800e8e2 ((tsr & CAN_TSR_TME1) != 0U) || 800e8cc: 69bb ldr r3, [r7, #24] 800e8ce: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || 800e8d2: 2b00 cmp r3, #0 800e8d4: d105 bne.n 800e8e2 ((tsr & CAN_TSR_TME2) != 0U)) 800e8d6: 69bb ldr r3, [r7, #24] 800e8d8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || 800e8dc: 2b00 cmp r3, #0 800e8de: f000 8095 beq.w 800ea0c { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; 800e8e2: 69bb ldr r3, [r7, #24] 800e8e4: 0e1b lsrs r3, r3, #24 800e8e6: f003 0303 and.w r3, r3, #3 800e8ea: 617b str r3, [r7, #20] /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; 800e8ec: 2201 movs r2, #1 800e8ee: 697b ldr r3, [r7, #20] 800e8f0: 409a lsls r2, r3 800e8f2: 683b ldr r3, [r7, #0] 800e8f4: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) 800e8f6: 68bb ldr r3, [r7, #8] 800e8f8: 689b ldr r3, [r3, #8] 800e8fa: 2b00 cmp r3, #0 800e8fc: d10d bne.n 800e91a { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800e8fe: 68bb ldr r3, [r7, #8] 800e900: 681b ldr r3, [r3, #0] 800e902: 055a lsls r2, r3, #21 pHeader->RTR); 800e904: 68bb ldr r3, [r7, #8] 800e906: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800e908: 68f9 ldr r1, [r7, #12] 800e90a: 6809 ldr r1, [r1, #0] 800e90c: 431a orrs r2, r3 800e90e: 697b ldr r3, [r7, #20] 800e910: 3318 adds r3, #24 800e912: 011b lsls r3, r3, #4 800e914: 440b add r3, r1 800e916: 601a str r2, [r3, #0] 800e918: e00f b.n 800e93a } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800e91a: 68bb ldr r3, [r7, #8] 800e91c: 685b ldr r3, [r3, #4] 800e91e: 00da lsls r2, r3, #3 pHeader->IDE | 800e920: 68bb ldr r3, [r7, #8] 800e922: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800e924: 431a orrs r2, r3 pHeader->RTR); 800e926: 68bb ldr r3, [r7, #8] 800e928: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800e92a: 68f9 ldr r1, [r7, #12] 800e92c: 6809 ldr r1, [r1, #0] pHeader->IDE | 800e92e: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800e930: 697b ldr r3, [r7, #20] 800e932: 3318 adds r3, #24 800e934: 011b lsls r3, r3, #4 800e936: 440b add r3, r1 800e938: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); 800e93a: 68fb ldr r3, [r7, #12] 800e93c: 6819 ldr r1, [r3, #0] 800e93e: 68bb ldr r3, [r7, #8] 800e940: 691a ldr r2, [r3, #16] 800e942: 697b ldr r3, [r7, #20] 800e944: 3318 adds r3, #24 800e946: 011b lsls r3, r3, #4 800e948: 440b add r3, r1 800e94a: 3304 adds r3, #4 800e94c: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) 800e94e: 68bb ldr r3, [r7, #8] 800e950: 7d1b ldrb r3, [r3, #20] 800e952: 2b01 cmp r3, #1 800e954: d111 bne.n 800e97a { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); 800e956: 68fb ldr r3, [r7, #12] 800e958: 681a ldr r2, [r3, #0] 800e95a: 697b ldr r3, [r7, #20] 800e95c: 3318 adds r3, #24 800e95e: 011b lsls r3, r3, #4 800e960: 4413 add r3, r2 800e962: 3304 adds r3, #4 800e964: 681b ldr r3, [r3, #0] 800e966: 68fa ldr r2, [r7, #12] 800e968: 6811 ldr r1, [r2, #0] 800e96a: f443 7280 orr.w r2, r3, #256 @ 0x100 800e96e: 697b ldr r3, [r7, #20] 800e970: 3318 adds r3, #24 800e972: 011b lsls r3, r3, #4 800e974: 440b add r3, r1 800e976: 3304 adds r3, #4 800e978: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, 800e97a: 687b ldr r3, [r7, #4] 800e97c: 3307 adds r3, #7 800e97e: 781b ldrb r3, [r3, #0] 800e980: 061a lsls r2, r3, #24 800e982: 687b ldr r3, [r7, #4] 800e984: 3306 adds r3, #6 800e986: 781b ldrb r3, [r3, #0] 800e988: 041b lsls r3, r3, #16 800e98a: 431a orrs r2, r3 800e98c: 687b ldr r3, [r7, #4] 800e98e: 3305 adds r3, #5 800e990: 781b ldrb r3, [r3, #0] 800e992: 021b lsls r3, r3, #8 800e994: 4313 orrs r3, r2 800e996: 687a ldr r2, [r7, #4] 800e998: 3204 adds r2, #4 800e99a: 7812 ldrb r2, [r2, #0] 800e99c: 4610 mov r0, r2 800e99e: 68fa ldr r2, [r7, #12] 800e9a0: 6811 ldr r1, [r2, #0] 800e9a2: ea43 0200 orr.w r2, r3, r0 800e9a6: 697b ldr r3, [r7, #20] 800e9a8: 011b lsls r3, r3, #4 800e9aa: 440b add r3, r1 800e9ac: f503 73c6 add.w r3, r3, #396 @ 0x18c 800e9b0: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, 800e9b2: 687b ldr r3, [r7, #4] 800e9b4: 3303 adds r3, #3 800e9b6: 781b ldrb r3, [r3, #0] 800e9b8: 061a lsls r2, r3, #24 800e9ba: 687b ldr r3, [r7, #4] 800e9bc: 3302 adds r3, #2 800e9be: 781b ldrb r3, [r3, #0] 800e9c0: 041b lsls r3, r3, #16 800e9c2: 431a orrs r2, r3 800e9c4: 687b ldr r3, [r7, #4] 800e9c6: 3301 adds r3, #1 800e9c8: 781b ldrb r3, [r3, #0] 800e9ca: 021b lsls r3, r3, #8 800e9cc: 4313 orrs r3, r2 800e9ce: 687a ldr r2, [r7, #4] 800e9d0: 7812 ldrb r2, [r2, #0] 800e9d2: 4610 mov r0, r2 800e9d4: 68fa ldr r2, [r7, #12] 800e9d6: 6811 ldr r1, [r2, #0] 800e9d8: ea43 0200 orr.w r2, r3, r0 800e9dc: 697b ldr r3, [r7, #20] 800e9de: 011b lsls r3, r3, #4 800e9e0: 440b add r3, r1 800e9e2: f503 73c4 add.w r3, r3, #392 @ 0x188 800e9e6: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); 800e9e8: 68fb ldr r3, [r7, #12] 800e9ea: 681a ldr r2, [r3, #0] 800e9ec: 697b ldr r3, [r7, #20] 800e9ee: 3318 adds r3, #24 800e9f0: 011b lsls r3, r3, #4 800e9f2: 4413 add r3, r2 800e9f4: 681b ldr r3, [r3, #0] 800e9f6: 68fa ldr r2, [r7, #12] 800e9f8: 6811 ldr r1, [r2, #0] 800e9fa: f043 0201 orr.w r2, r3, #1 800e9fe: 697b ldr r3, [r7, #20] 800ea00: 3318 adds r3, #24 800ea02: 011b lsls r3, r3, #4 800ea04: 440b add r3, r1 800ea06: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800ea08: 2300 movs r3, #0 800ea0a: e00e b.n 800ea2a } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800ea0c: 68fb ldr r3, [r7, #12] 800ea0e: 6a5b ldr r3, [r3, #36] @ 0x24 800ea10: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800ea14: 68fb ldr r3, [r7, #12] 800ea16: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ea18: 2301 movs r3, #1 800ea1a: e006 b.n 800ea2a } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800ea1c: 68fb ldr r3, [r7, #12] 800ea1e: 6a5b ldr r3, [r3, #36] @ 0x24 800ea20: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800ea24: 68fb ldr r3, [r7, #12] 800ea26: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ea28: 2301 movs r3, #1 } } 800ea2a: 4618 mov r0, r3 800ea2c: 3724 adds r7, #36 @ 0x24 800ea2e: 46bd mov sp, r7 800ea30: bc80 pop {r7} 800ea32: 4770 bx lr 0800ea34 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval Number of free Tx Mailboxes. */ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) { 800ea34: b480 push {r7} 800ea36: b085 sub sp, #20 800ea38: af00 add r7, sp, #0 800ea3a: 6078 str r0, [r7, #4] uint32_t freelevel = 0U; 800ea3c: 2300 movs r3, #0 800ea3e: 60fb str r3, [r7, #12] HAL_CAN_StateTypeDef state = hcan->State; 800ea40: 687b ldr r3, [r7, #4] 800ea42: f893 3020 ldrb.w r3, [r3, #32] 800ea46: 72fb strb r3, [r7, #11] if ((state == HAL_CAN_STATE_READY) || 800ea48: 7afb ldrb r3, [r7, #11] 800ea4a: 2b01 cmp r3, #1 800ea4c: d002 beq.n 800ea54 800ea4e: 7afb ldrb r3, [r7, #11] 800ea50: 2b02 cmp r3, #2 800ea52: d11d bne.n 800ea90 (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 status */ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) 800ea54: 687b ldr r3, [r7, #4] 800ea56: 681b ldr r3, [r3, #0] 800ea58: 689b ldr r3, [r3, #8] 800ea5a: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800ea5e: 2b00 cmp r3, #0 800ea60: d002 beq.n 800ea68 { freelevel++; 800ea62: 68fb ldr r3, [r7, #12] 800ea64: 3301 adds r3, #1 800ea66: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 1 status */ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) 800ea68: 687b ldr r3, [r7, #4] 800ea6a: 681b ldr r3, [r3, #0] 800ea6c: 689b ldr r3, [r3, #8] 800ea6e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800ea72: 2b00 cmp r3, #0 800ea74: d002 beq.n 800ea7c { freelevel++; 800ea76: 68fb ldr r3, [r7, #12] 800ea78: 3301 adds r3, #1 800ea7a: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 2 status */ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) 800ea7c: 687b ldr r3, [r7, #4] 800ea7e: 681b ldr r3, [r3, #0] 800ea80: 689b ldr r3, [r3, #8] 800ea82: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800ea86: 2b00 cmp r3, #0 800ea88: d002 beq.n 800ea90 { freelevel++; 800ea8a: 68fb ldr r3, [r7, #12] 800ea8c: 3301 adds r3, #1 800ea8e: 60fb str r3, [r7, #12] } } /* Return Tx Mailboxes free level */ return freelevel; 800ea90: 68fb ldr r3, [r7, #12] } 800ea92: 4618 mov r0, r3 800ea94: 3714 adds r7, #20 800ea96: 46bd mov sp, r7 800ea98: bc80 pop {r7} 800ea9a: 4770 bx lr 0800ea9c : * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { 800ea9c: b480 push {r7} 800ea9e: b087 sub sp, #28 800eaa0: af00 add r7, sp, #0 800eaa2: 60f8 str r0, [r7, #12] 800eaa4: 60b9 str r1, [r7, #8] 800eaa6: 607a str r2, [r7, #4] 800eaa8: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800eaaa: 68fb ldr r3, [r7, #12] 800eaac: f893 3020 ldrb.w r3, [r3, #32] 800eab0: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || 800eab2: 7dfb ldrb r3, [r7, #23] 800eab4: 2b01 cmp r3, #1 800eab6: d003 beq.n 800eac0 800eab8: 7dfb ldrb r3, [r7, #23] 800eaba: 2b02 cmp r3, #2 800eabc: f040 8103 bne.w 800ecc6 (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800eac0: 68bb ldr r3, [r7, #8] 800eac2: 2b00 cmp r3, #0 800eac4: d10e bne.n 800eae4 { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) 800eac6: 68fb ldr r3, [r7, #12] 800eac8: 681b ldr r3, [r3, #0] 800eaca: 68db ldr r3, [r3, #12] 800eacc: f003 0303 and.w r3, r3, #3 800ead0: 2b00 cmp r3, #0 800ead2: d116 bne.n 800eb02 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800ead4: 68fb ldr r3, [r7, #12] 800ead6: 6a5b ldr r3, [r3, #36] @ 0x24 800ead8: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800eadc: 68fb ldr r3, [r7, #12] 800eade: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800eae0: 2301 movs r3, #1 800eae2: e0f7 b.n 800ecd4 } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) 800eae4: 68fb ldr r3, [r7, #12] 800eae6: 681b ldr r3, [r3, #0] 800eae8: 691b ldr r3, [r3, #16] 800eaea: f003 0303 and.w r3, r3, #3 800eaee: 2b00 cmp r3, #0 800eaf0: d107 bne.n 800eb02 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800eaf2: 68fb ldr r3, [r7, #12] 800eaf4: 6a5b ldr r3, [r3, #36] @ 0x24 800eaf6: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800eafa: 68fb ldr r3, [r7, #12] 800eafc: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800eafe: 2301 movs r3, #1 800eb00: e0e8 b.n 800ecd4 } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; 800eb02: 68fb ldr r3, [r7, #12] 800eb04: 681a ldr r2, [r3, #0] 800eb06: 68bb ldr r3, [r7, #8] 800eb08: 331b adds r3, #27 800eb0a: 011b lsls r3, r3, #4 800eb0c: 4413 add r3, r2 800eb0e: 681b ldr r3, [r3, #0] 800eb10: f003 0204 and.w r2, r3, #4 800eb14: 687b ldr r3, [r7, #4] 800eb16: 609a str r2, [r3, #8] if (pHeader->IDE == CAN_ID_STD) 800eb18: 687b ldr r3, [r7, #4] 800eb1a: 689b ldr r3, [r3, #8] 800eb1c: 2b00 cmp r3, #0 800eb1e: d10c bne.n 800eb3a { pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; 800eb20: 68fb ldr r3, [r7, #12] 800eb22: 681a ldr r2, [r3, #0] 800eb24: 68bb ldr r3, [r7, #8] 800eb26: 331b adds r3, #27 800eb28: 011b lsls r3, r3, #4 800eb2a: 4413 add r3, r2 800eb2c: 681b ldr r3, [r3, #0] 800eb2e: 0d5b lsrs r3, r3, #21 800eb30: f3c3 020a ubfx r2, r3, #0, #11 800eb34: 687b ldr r3, [r7, #4] 800eb36: 601a str r2, [r3, #0] 800eb38: e00b b.n 800eb52 } else { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; 800eb3a: 68fb ldr r3, [r7, #12] 800eb3c: 681a ldr r2, [r3, #0] 800eb3e: 68bb ldr r3, [r7, #8] 800eb40: 331b adds r3, #27 800eb42: 011b lsls r3, r3, #4 800eb44: 4413 add r3, r2 800eb46: 681b ldr r3, [r3, #0] 800eb48: 08db lsrs r3, r3, #3 800eb4a: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & 800eb4e: 687b ldr r3, [r7, #4] 800eb50: 605a str r2, [r3, #4] } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); 800eb52: 68fb ldr r3, [r7, #12] 800eb54: 681a ldr r2, [r3, #0] 800eb56: 68bb ldr r3, [r7, #8] 800eb58: 331b adds r3, #27 800eb5a: 011b lsls r3, r3, #4 800eb5c: 4413 add r3, r2 800eb5e: 681b ldr r3, [r3, #0] 800eb60: f003 0202 and.w r2, r3, #2 800eb64: 687b ldr r3, [r7, #4] 800eb66: 60da str r2, [r3, #12] if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) 800eb68: 68fb ldr r3, [r7, #12] 800eb6a: 681a ldr r2, [r3, #0] 800eb6c: 68bb ldr r3, [r7, #8] 800eb6e: 331b adds r3, #27 800eb70: 011b lsls r3, r3, #4 800eb72: 4413 add r3, r2 800eb74: 3304 adds r3, #4 800eb76: 681b ldr r3, [r3, #0] 800eb78: f003 0308 and.w r3, r3, #8 800eb7c: 2b00 cmp r3, #0 800eb7e: d003 beq.n 800eb88 { /* Truncate DLC to 8 if received field is over range */ pHeader->DLC = 8U; 800eb80: 687b ldr r3, [r7, #4] 800eb82: 2208 movs r2, #8 800eb84: 611a str r2, [r3, #16] 800eb86: e00b b.n 800eba0 } else { pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; 800eb88: 68fb ldr r3, [r7, #12] 800eb8a: 681a ldr r2, [r3, #0] 800eb8c: 68bb ldr r3, [r7, #8] 800eb8e: 331b adds r3, #27 800eb90: 011b lsls r3, r3, #4 800eb92: 4413 add r3, r2 800eb94: 3304 adds r3, #4 800eb96: 681b ldr r3, [r3, #0] 800eb98: f003 020f and.w r2, r3, #15 800eb9c: 687b ldr r3, [r7, #4] 800eb9e: 611a str r2, [r3, #16] } pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; 800eba0: 68fb ldr r3, [r7, #12] 800eba2: 681a ldr r2, [r3, #0] 800eba4: 68bb ldr r3, [r7, #8] 800eba6: 331b adds r3, #27 800eba8: 011b lsls r3, r3, #4 800ebaa: 4413 add r3, r2 800ebac: 3304 adds r3, #4 800ebae: 681b ldr r3, [r3, #0] 800ebb0: 0a1b lsrs r3, r3, #8 800ebb2: b2da uxtb r2, r3 800ebb4: 687b ldr r3, [r7, #4] 800ebb6: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; 800ebb8: 68fb ldr r3, [r7, #12] 800ebba: 681a ldr r2, [r3, #0] 800ebbc: 68bb ldr r3, [r7, #8] 800ebbe: 331b adds r3, #27 800ebc0: 011b lsls r3, r3, #4 800ebc2: 4413 add r3, r2 800ebc4: 3304 adds r3, #4 800ebc6: 681b ldr r3, [r3, #0] 800ebc8: 0c1b lsrs r3, r3, #16 800ebca: b29a uxth r2, r3 800ebcc: 687b ldr r3, [r7, #4] 800ebce: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); 800ebd0: 68fb ldr r3, [r7, #12] 800ebd2: 681a ldr r2, [r3, #0] 800ebd4: 68bb ldr r3, [r7, #8] 800ebd6: 011b lsls r3, r3, #4 800ebd8: 4413 add r3, r2 800ebda: f503 73dc add.w r3, r3, #440 @ 0x1b8 800ebde: 681b ldr r3, [r3, #0] 800ebe0: b2da uxtb r2, r3 800ebe2: 683b ldr r3, [r7, #0] 800ebe4: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); 800ebe6: 68fb ldr r3, [r7, #12] 800ebe8: 681a ldr r2, [r3, #0] 800ebea: 68bb ldr r3, [r7, #8] 800ebec: 011b lsls r3, r3, #4 800ebee: 4413 add r3, r2 800ebf0: f503 73dc add.w r3, r3, #440 @ 0x1b8 800ebf4: 681b ldr r3, [r3, #0] 800ebf6: 0a1a lsrs r2, r3, #8 800ebf8: 683b ldr r3, [r7, #0] 800ebfa: 3301 adds r3, #1 800ebfc: b2d2 uxtb r2, r2 800ebfe: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); 800ec00: 68fb ldr r3, [r7, #12] 800ec02: 681a ldr r2, [r3, #0] 800ec04: 68bb ldr r3, [r7, #8] 800ec06: 011b lsls r3, r3, #4 800ec08: 4413 add r3, r2 800ec0a: f503 73dc add.w r3, r3, #440 @ 0x1b8 800ec0e: 681b ldr r3, [r3, #0] 800ec10: 0c1a lsrs r2, r3, #16 800ec12: 683b ldr r3, [r7, #0] 800ec14: 3302 adds r3, #2 800ec16: b2d2 uxtb r2, r2 800ec18: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); 800ec1a: 68fb ldr r3, [r7, #12] 800ec1c: 681a ldr r2, [r3, #0] 800ec1e: 68bb ldr r3, [r7, #8] 800ec20: 011b lsls r3, r3, #4 800ec22: 4413 add r3, r2 800ec24: f503 73dc add.w r3, r3, #440 @ 0x1b8 800ec28: 681b ldr r3, [r3, #0] 800ec2a: 0e1a lsrs r2, r3, #24 800ec2c: 683b ldr r3, [r7, #0] 800ec2e: 3303 adds r3, #3 800ec30: b2d2 uxtb r2, r2 800ec32: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); 800ec34: 68fb ldr r3, [r7, #12] 800ec36: 681a ldr r2, [r3, #0] 800ec38: 68bb ldr r3, [r7, #8] 800ec3a: 011b lsls r3, r3, #4 800ec3c: 4413 add r3, r2 800ec3e: f503 73de add.w r3, r3, #444 @ 0x1bc 800ec42: 681a ldr r2, [r3, #0] 800ec44: 683b ldr r3, [r7, #0] 800ec46: 3304 adds r3, #4 800ec48: b2d2 uxtb r2, r2 800ec4a: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); 800ec4c: 68fb ldr r3, [r7, #12] 800ec4e: 681a ldr r2, [r3, #0] 800ec50: 68bb ldr r3, [r7, #8] 800ec52: 011b lsls r3, r3, #4 800ec54: 4413 add r3, r2 800ec56: f503 73de add.w r3, r3, #444 @ 0x1bc 800ec5a: 681b ldr r3, [r3, #0] 800ec5c: 0a1a lsrs r2, r3, #8 800ec5e: 683b ldr r3, [r7, #0] 800ec60: 3305 adds r3, #5 800ec62: b2d2 uxtb r2, r2 800ec64: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); 800ec66: 68fb ldr r3, [r7, #12] 800ec68: 681a ldr r2, [r3, #0] 800ec6a: 68bb ldr r3, [r7, #8] 800ec6c: 011b lsls r3, r3, #4 800ec6e: 4413 add r3, r2 800ec70: f503 73de add.w r3, r3, #444 @ 0x1bc 800ec74: 681b ldr r3, [r3, #0] 800ec76: 0c1a lsrs r2, r3, #16 800ec78: 683b ldr r3, [r7, #0] 800ec7a: 3306 adds r3, #6 800ec7c: b2d2 uxtb r2, r2 800ec7e: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); 800ec80: 68fb ldr r3, [r7, #12] 800ec82: 681a ldr r2, [r3, #0] 800ec84: 68bb ldr r3, [r7, #8] 800ec86: 011b lsls r3, r3, #4 800ec88: 4413 add r3, r2 800ec8a: f503 73de add.w r3, r3, #444 @ 0x1bc 800ec8e: 681b ldr r3, [r3, #0] 800ec90: 0e1a lsrs r2, r3, #24 800ec92: 683b ldr r3, [r7, #0] 800ec94: 3307 adds r3, #7 800ec96: b2d2 uxtb r2, r2 800ec98: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800ec9a: 68bb ldr r3, [r7, #8] 800ec9c: 2b00 cmp r3, #0 800ec9e: d108 bne.n 800ecb2 { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); 800eca0: 68fb ldr r3, [r7, #12] 800eca2: 681b ldr r3, [r3, #0] 800eca4: 68da ldr r2, [r3, #12] 800eca6: 68fb ldr r3, [r7, #12] 800eca8: 681b ldr r3, [r3, #0] 800ecaa: f042 0220 orr.w r2, r2, #32 800ecae: 60da str r2, [r3, #12] 800ecb0: e007 b.n 800ecc2 } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); 800ecb2: 68fb ldr r3, [r7, #12] 800ecb4: 681b ldr r3, [r3, #0] 800ecb6: 691a ldr r2, [r3, #16] 800ecb8: 68fb ldr r3, [r7, #12] 800ecba: 681b ldr r3, [r3, #0] 800ecbc: f042 0220 orr.w r2, r2, #32 800ecc0: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; 800ecc2: 2300 movs r3, #0 800ecc4: e006 b.n 800ecd4 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800ecc6: 68fb ldr r3, [r7, #12] 800ecc8: 6a5b ldr r3, [r3, #36] @ 0x24 800ecca: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800ecce: 68fb ldr r3, [r7, #12] 800ecd0: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ecd2: 2301 movs r3, #1 } } 800ecd4: 4618 mov r0, r3 800ecd6: 371c adds r7, #28 800ecd8: 46bd mov sp, r7 800ecda: bc80 pop {r7} 800ecdc: 4770 bx lr 0800ecde : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { 800ecde: b480 push {r7} 800ece0: b085 sub sp, #20 800ece2: af00 add r7, sp, #0 800ece4: 6078 str r0, [r7, #4] 800ece6: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800ece8: 687b ldr r3, [r7, #4] 800ecea: f893 3020 ldrb.w r3, [r3, #32] 800ecee: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || 800ecf0: 7bfb ldrb r3, [r7, #15] 800ecf2: 2b01 cmp r3, #1 800ecf4: d002 beq.n 800ecfc 800ecf6: 7bfb ldrb r3, [r7, #15] 800ecf8: 2b02 cmp r3, #2 800ecfa: d109 bne.n 800ed10 (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); 800ecfc: 687b ldr r3, [r7, #4] 800ecfe: 681b ldr r3, [r3, #0] 800ed00: 6959 ldr r1, [r3, #20] 800ed02: 687b ldr r3, [r7, #4] 800ed04: 681b ldr r3, [r3, #0] 800ed06: 683a ldr r2, [r7, #0] 800ed08: 430a orrs r2, r1 800ed0a: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; 800ed0c: 2300 movs r3, #0 800ed0e: e006 b.n 800ed1e } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800ed10: 687b ldr r3, [r7, #4] 800ed12: 6a5b ldr r3, [r3, #36] @ 0x24 800ed14: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800ed18: 687b ldr r3, [r7, #4] 800ed1a: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ed1c: 2301 movs r3, #1 } } 800ed1e: 4618 mov r0, r3 800ed20: 3714 adds r7, #20 800ed22: 46bd mov sp, r7 800ed24: bc80 pop {r7} 800ed26: 4770 bx lr 0800ed28 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { 800ed28: b580 push {r7, lr} 800ed2a: b08a sub sp, #40 @ 0x28 800ed2c: af00 add r7, sp, #0 800ed2e: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; 800ed30: 2300 movs r3, #0 800ed32: 627b str r3, [r7, #36] @ 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); 800ed34: 687b ldr r3, [r7, #4] 800ed36: 681b ldr r3, [r3, #0] 800ed38: 695b ldr r3, [r3, #20] 800ed3a: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); 800ed3c: 687b ldr r3, [r7, #4] 800ed3e: 681b ldr r3, [r3, #0] 800ed40: 685b ldr r3, [r3, #4] 800ed42: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); 800ed44: 687b ldr r3, [r7, #4] 800ed46: 681b ldr r3, [r3, #0] 800ed48: 689b ldr r3, [r3, #8] 800ed4a: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); 800ed4c: 687b ldr r3, [r7, #4] 800ed4e: 681b ldr r3, [r3, #0] 800ed50: 68db ldr r3, [r3, #12] 800ed52: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); 800ed54: 687b ldr r3, [r7, #4] 800ed56: 681b ldr r3, [r3, #0] 800ed58: 691b ldr r3, [r3, #16] 800ed5a: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); 800ed5c: 687b ldr r3, [r7, #4] 800ed5e: 681b ldr r3, [r3, #0] 800ed60: 699b ldr r3, [r3, #24] 800ed62: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) 800ed64: 6a3b ldr r3, [r7, #32] 800ed66: f003 0301 and.w r3, r3, #1 800ed6a: 2b00 cmp r3, #0 800ed6c: d07c beq.n 800ee68 { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) 800ed6e: 69bb ldr r3, [r7, #24] 800ed70: f003 0301 and.w r3, r3, #1 800ed74: 2b00 cmp r3, #0 800ed76: d023 beq.n 800edc0 { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); 800ed78: 687b ldr r3, [r7, #4] 800ed7a: 681b ldr r3, [r3, #0] 800ed7c: 2201 movs r2, #1 800ed7e: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) 800ed80: 69bb ldr r3, [r7, #24] 800ed82: f003 0302 and.w r3, r3, #2 800ed86: 2b00 cmp r3, #0 800ed88: d003 beq.n 800ed92 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); 800ed8a: 6878 ldr r0, [r7, #4] 800ed8c: f000 f983 bl 800f096 800ed90: e016 b.n 800edc0 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) 800ed92: 69bb ldr r3, [r7, #24] 800ed94: f003 0304 and.w r3, r3, #4 800ed98: 2b00 cmp r3, #0 800ed9a: d004 beq.n 800eda6 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; 800ed9c: 6a7b ldr r3, [r7, #36] @ 0x24 800ed9e: f443 6300 orr.w r3, r3, #2048 @ 0x800 800eda2: 627b str r3, [r7, #36] @ 0x24 800eda4: e00c b.n 800edc0 } else if ((tsrflags & CAN_TSR_TERR0) != 0U) 800eda6: 69bb ldr r3, [r7, #24] 800eda8: f003 0308 and.w r3, r3, #8 800edac: 2b00 cmp r3, #0 800edae: d004 beq.n 800edba { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; 800edb0: 6a7b ldr r3, [r7, #36] @ 0x24 800edb2: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800edb6: 627b str r3, [r7, #36] @ 0x24 800edb8: e002 b.n 800edc0 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); 800edba: 6878 ldr r0, [r7, #4] 800edbc: f000 f986 bl 800f0cc } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) 800edc0: 69bb ldr r3, [r7, #24] 800edc2: f403 7380 and.w r3, r3, #256 @ 0x100 800edc6: 2b00 cmp r3, #0 800edc8: d024 beq.n 800ee14 { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); 800edca: 687b ldr r3, [r7, #4] 800edcc: 681b ldr r3, [r3, #0] 800edce: f44f 7280 mov.w r2, #256 @ 0x100 800edd2: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) 800edd4: 69bb ldr r3, [r7, #24] 800edd6: f403 7300 and.w r3, r3, #512 @ 0x200 800edda: 2b00 cmp r3, #0 800eddc: d003 beq.n 800ede6 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); 800edde: 6878 ldr r0, [r7, #4] 800ede0: f000 f962 bl 800f0a8 800ede4: e016 b.n 800ee14 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) 800ede6: 69bb ldr r3, [r7, #24] 800ede8: f403 6380 and.w r3, r3, #1024 @ 0x400 800edec: 2b00 cmp r3, #0 800edee: d004 beq.n 800edfa { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; 800edf0: 6a7b ldr r3, [r7, #36] @ 0x24 800edf2: f443 5300 orr.w r3, r3, #8192 @ 0x2000 800edf6: 627b str r3, [r7, #36] @ 0x24 800edf8: e00c b.n 800ee14 } else if ((tsrflags & CAN_TSR_TERR1) != 0U) 800edfa: 69bb ldr r3, [r7, #24] 800edfc: f403 6300 and.w r3, r3, #2048 @ 0x800 800ee00: 2b00 cmp r3, #0 800ee02: d004 beq.n 800ee0e { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; 800ee04: 6a7b ldr r3, [r7, #36] @ 0x24 800ee06: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800ee0a: 627b str r3, [r7, #36] @ 0x24 800ee0c: e002 b.n 800ee14 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); 800ee0e: 6878 ldr r0, [r7, #4] 800ee10: f000 f965 bl 800f0de } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) 800ee14: 69bb ldr r3, [r7, #24] 800ee16: f403 3380 and.w r3, r3, #65536 @ 0x10000 800ee1a: 2b00 cmp r3, #0 800ee1c: d024 beq.n 800ee68 { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); 800ee1e: 687b ldr r3, [r7, #4] 800ee20: 681b ldr r3, [r3, #0] 800ee22: f44f 3280 mov.w r2, #65536 @ 0x10000 800ee26: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) 800ee28: 69bb ldr r3, [r7, #24] 800ee2a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800ee2e: 2b00 cmp r3, #0 800ee30: d003 beq.n 800ee3a #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); 800ee32: 6878 ldr r0, [r7, #4] 800ee34: f000 f941 bl 800f0ba 800ee38: e016 b.n 800ee68 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) 800ee3a: 69bb ldr r3, [r7, #24] 800ee3c: f403 2380 and.w r3, r3, #262144 @ 0x40000 800ee40: 2b00 cmp r3, #0 800ee42: d004 beq.n 800ee4e { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; 800ee44: 6a7b ldr r3, [r7, #36] @ 0x24 800ee46: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800ee4a: 627b str r3, [r7, #36] @ 0x24 800ee4c: e00c b.n 800ee68 } else if ((tsrflags & CAN_TSR_TERR2) != 0U) 800ee4e: 69bb ldr r3, [r7, #24] 800ee50: f403 2300 and.w r3, r3, #524288 @ 0x80000 800ee54: 2b00 cmp r3, #0 800ee56: d004 beq.n 800ee62 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; 800ee58: 6a7b ldr r3, [r7, #36] @ 0x24 800ee5a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800ee5e: 627b str r3, [r7, #36] @ 0x24 800ee60: e002 b.n 800ee68 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); 800ee62: 6878 ldr r0, [r7, #4] 800ee64: f000 f944 bl 800f0f0 } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) 800ee68: 6a3b ldr r3, [r7, #32] 800ee6a: f003 0308 and.w r3, r3, #8 800ee6e: 2b00 cmp r3, #0 800ee70: d00c beq.n 800ee8c { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) 800ee72: 697b ldr r3, [r7, #20] 800ee74: f003 0310 and.w r3, r3, #16 800ee78: 2b00 cmp r3, #0 800ee7a: d007 beq.n 800ee8c { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; 800ee7c: 6a7b ldr r3, [r7, #36] @ 0x24 800ee7e: f443 7300 orr.w r3, r3, #512 @ 0x200 800ee82: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); 800ee84: 687b ldr r3, [r7, #4] 800ee86: 681b ldr r3, [r3, #0] 800ee88: 2210 movs r2, #16 800ee8a: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) 800ee8c: 6a3b ldr r3, [r7, #32] 800ee8e: f003 0304 and.w r3, r3, #4 800ee92: 2b00 cmp r3, #0 800ee94: d00b beq.n 800eeae { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) 800ee96: 697b ldr r3, [r7, #20] 800ee98: f003 0308 and.w r3, r3, #8 800ee9c: 2b00 cmp r3, #0 800ee9e: d006 beq.n 800eeae { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); 800eea0: 687b ldr r3, [r7, #4] 800eea2: 681b ldr r3, [r3, #0] 800eea4: 2208 movs r2, #8 800eea6: 60da str r2, [r3, #12] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); 800eea8: 6878 ldr r0, [r7, #4] 800eeaa: f000 f933 bl 800f114 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) 800eeae: 6a3b ldr r3, [r7, #32] 800eeb0: f003 0302 and.w r3, r3, #2 800eeb4: 2b00 cmp r3, #0 800eeb6: d009 beq.n 800eecc { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) 800eeb8: 687b ldr r3, [r7, #4] 800eeba: 681b ldr r3, [r3, #0] 800eebc: 68db ldr r3, [r3, #12] 800eebe: f003 0303 and.w r3, r3, #3 800eec2: 2b00 cmp r3, #0 800eec4: d002 beq.n 800eecc #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); 800eec6: 6878 ldr r0, [r7, #4] 800eec8: f000 f91b bl 800f102 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) 800eecc: 6a3b ldr r3, [r7, #32] 800eece: f003 0340 and.w r3, r3, #64 @ 0x40 800eed2: 2b00 cmp r3, #0 800eed4: d00c beq.n 800eef0 { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) 800eed6: 693b ldr r3, [r7, #16] 800eed8: f003 0310 and.w r3, r3, #16 800eedc: 2b00 cmp r3, #0 800eede: d007 beq.n 800eef0 { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; 800eee0: 6a7b ldr r3, [r7, #36] @ 0x24 800eee2: f443 6380 orr.w r3, r3, #1024 @ 0x400 800eee6: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); 800eee8: 687b ldr r3, [r7, #4] 800eeea: 681b ldr r3, [r3, #0] 800eeec: 2210 movs r2, #16 800eeee: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) 800eef0: 6a3b ldr r3, [r7, #32] 800eef2: f003 0320 and.w r3, r3, #32 800eef6: 2b00 cmp r3, #0 800eef8: d00b beq.n 800ef12 { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) 800eefa: 693b ldr r3, [r7, #16] 800eefc: f003 0308 and.w r3, r3, #8 800ef00: 2b00 cmp r3, #0 800ef02: d006 beq.n 800ef12 { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); 800ef04: 687b ldr r3, [r7, #4] 800ef06: 681b ldr r3, [r3, #0] 800ef08: 2208 movs r2, #8 800ef0a: 611a str r2, [r3, #16] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); 800ef0c: 6878 ldr r0, [r7, #4] 800ef0e: f000 f90a bl 800f126 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) 800ef12: 6a3b ldr r3, [r7, #32] 800ef14: f003 0310 and.w r3, r3, #16 800ef18: 2b00 cmp r3, #0 800ef1a: d009 beq.n 800ef30 { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) 800ef1c: 687b ldr r3, [r7, #4] 800ef1e: 681b ldr r3, [r3, #0] 800ef20: 691b ldr r3, [r3, #16] 800ef22: f003 0303 and.w r3, r3, #3 800ef26: 2b00 cmp r3, #0 800ef28: d002 beq.n 800ef30 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); 800ef2a: 6878 ldr r0, [r7, #4] 800ef2c: f7fb fdf6 bl 800ab1c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) 800ef30: 6a3b ldr r3, [r7, #32] 800ef32: f403 3300 and.w r3, r3, #131072 @ 0x20000 800ef36: 2b00 cmp r3, #0 800ef38: d00b beq.n 800ef52 { if ((msrflags & CAN_MSR_SLAKI) != 0U) 800ef3a: 69fb ldr r3, [r7, #28] 800ef3c: f003 0310 and.w r3, r3, #16 800ef40: 2b00 cmp r3, #0 800ef42: d006 beq.n 800ef52 { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); 800ef44: 687b ldr r3, [r7, #4] 800ef46: 681b ldr r3, [r3, #0] 800ef48: 2210 movs r2, #16 800ef4a: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->SleepCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); 800ef4c: 6878 ldr r0, [r7, #4] 800ef4e: f000 f8f3 bl 800f138 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ if ((interrupts & CAN_IT_WAKEUP) != 0U) 800ef52: 6a3b ldr r3, [r7, #32] 800ef54: f403 3380 and.w r3, r3, #65536 @ 0x10000 800ef58: 2b00 cmp r3, #0 800ef5a: d00b beq.n 800ef74 { if ((msrflags & CAN_MSR_WKUI) != 0U) 800ef5c: 69fb ldr r3, [r7, #28] 800ef5e: f003 0308 and.w r3, r3, #8 800ef62: 2b00 cmp r3, #0 800ef64: d006 beq.n 800ef74 { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); 800ef66: 687b ldr r3, [r7, #4] 800ef68: 681b ldr r3, [r3, #0] 800ef6a: 2208 movs r2, #8 800ef6c: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->WakeUpFromRxMsgCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); 800ef6e: 6878 ldr r0, [r7, #4] 800ef70: f000 f8eb bl 800f14a #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ if ((interrupts & CAN_IT_ERROR) != 0U) 800ef74: 6a3b ldr r3, [r7, #32] 800ef76: f403 4300 and.w r3, r3, #32768 @ 0x8000 800ef7a: 2b00 cmp r3, #0 800ef7c: d07b beq.n 800f076 { if ((msrflags & CAN_MSR_ERRI) != 0U) 800ef7e: 69fb ldr r3, [r7, #28] 800ef80: f003 0304 and.w r3, r3, #4 800ef84: 2b00 cmp r3, #0 800ef86: d072 beq.n 800f06e { /* Check Error Warning Flag */ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800ef88: 6a3b ldr r3, [r7, #32] 800ef8a: f403 7380 and.w r3, r3, #256 @ 0x100 800ef8e: 2b00 cmp r3, #0 800ef90: d008 beq.n 800efa4 ((esrflags & CAN_ESR_EWGF) != 0U)) 800ef92: 68fb ldr r3, [r7, #12] 800ef94: f003 0301 and.w r3, r3, #1 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800ef98: 2b00 cmp r3, #0 800ef9a: d003 beq.n 800efa4 { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; 800ef9c: 6a7b ldr r3, [r7, #36] @ 0x24 800ef9e: f043 0301 orr.w r3, r3, #1 800efa2: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Warning Flag as read-only */ } /* Check Error Passive Flag */ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800efa4: 6a3b ldr r3, [r7, #32] 800efa6: f403 7300 and.w r3, r3, #512 @ 0x200 800efaa: 2b00 cmp r3, #0 800efac: d008 beq.n 800efc0 ((esrflags & CAN_ESR_EPVF) != 0U)) 800efae: 68fb ldr r3, [r7, #12] 800efb0: f003 0302 and.w r3, r3, #2 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800efb4: 2b00 cmp r3, #0 800efb6: d003 beq.n 800efc0 { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; 800efb8: 6a7b ldr r3, [r7, #36] @ 0x24 800efba: f043 0302 orr.w r3, r3, #2 800efbe: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-off Flag */ if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800efc0: 6a3b ldr r3, [r7, #32] 800efc2: f403 6380 and.w r3, r3, #1024 @ 0x400 800efc6: 2b00 cmp r3, #0 800efc8: d008 beq.n 800efdc ((esrflags & CAN_ESR_BOFF) != 0U)) 800efca: 68fb ldr r3, [r7, #12] 800efcc: f003 0304 and.w r3, r3, #4 if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800efd0: 2b00 cmp r3, #0 800efd2: d003 beq.n 800efdc { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; 800efd4: 6a7b ldr r3, [r7, #36] @ 0x24 800efd6: f043 0304 orr.w r3, r3, #4 800efda: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Bus-Off as read-only */ } /* Check Last Error Code Flag */ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800efdc: 6a3b ldr r3, [r7, #32] 800efde: f403 6300 and.w r3, r3, #2048 @ 0x800 800efe2: 2b00 cmp r3, #0 800efe4: d043 beq.n 800f06e ((esrflags & CAN_ESR_LEC) != 0U)) 800efe6: 68fb ldr r3, [r7, #12] 800efe8: f003 0370 and.w r3, r3, #112 @ 0x70 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800efec: 2b00 cmp r3, #0 800efee: d03e beq.n 800f06e { switch (esrflags & CAN_ESR_LEC) 800eff0: 68fb ldr r3, [r7, #12] 800eff2: f003 0370 and.w r3, r3, #112 @ 0x70 800eff6: 2b60 cmp r3, #96 @ 0x60 800eff8: d02b beq.n 800f052 800effa: 2b60 cmp r3, #96 @ 0x60 800effc: d82e bhi.n 800f05c 800effe: 2b50 cmp r3, #80 @ 0x50 800f000: d022 beq.n 800f048 800f002: 2b50 cmp r3, #80 @ 0x50 800f004: d82a bhi.n 800f05c 800f006: 2b40 cmp r3, #64 @ 0x40 800f008: d019 beq.n 800f03e 800f00a: 2b40 cmp r3, #64 @ 0x40 800f00c: d826 bhi.n 800f05c 800f00e: 2b30 cmp r3, #48 @ 0x30 800f010: d010 beq.n 800f034 800f012: 2b30 cmp r3, #48 @ 0x30 800f014: d822 bhi.n 800f05c 800f016: 2b10 cmp r3, #16 800f018: d002 beq.n 800f020 800f01a: 2b20 cmp r3, #32 800f01c: d005 beq.n 800f02a case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): /* Set CAN error code to CRC error */ errorcode |= HAL_CAN_ERROR_CRC; break; default: break; 800f01e: e01d b.n 800f05c errorcode |= HAL_CAN_ERROR_STF; 800f020: 6a7b ldr r3, [r7, #36] @ 0x24 800f022: f043 0308 orr.w r3, r3, #8 800f026: 627b str r3, [r7, #36] @ 0x24 break; 800f028: e019 b.n 800f05e errorcode |= HAL_CAN_ERROR_FOR; 800f02a: 6a7b ldr r3, [r7, #36] @ 0x24 800f02c: f043 0310 orr.w r3, r3, #16 800f030: 627b str r3, [r7, #36] @ 0x24 break; 800f032: e014 b.n 800f05e errorcode |= HAL_CAN_ERROR_ACK; 800f034: 6a7b ldr r3, [r7, #36] @ 0x24 800f036: f043 0320 orr.w r3, r3, #32 800f03a: 627b str r3, [r7, #36] @ 0x24 break; 800f03c: e00f b.n 800f05e errorcode |= HAL_CAN_ERROR_BR; 800f03e: 6a7b ldr r3, [r7, #36] @ 0x24 800f040: f043 0340 orr.w r3, r3, #64 @ 0x40 800f044: 627b str r3, [r7, #36] @ 0x24 break; 800f046: e00a b.n 800f05e errorcode |= HAL_CAN_ERROR_BD; 800f048: 6a7b ldr r3, [r7, #36] @ 0x24 800f04a: f043 0380 orr.w r3, r3, #128 @ 0x80 800f04e: 627b str r3, [r7, #36] @ 0x24 break; 800f050: e005 b.n 800f05e errorcode |= HAL_CAN_ERROR_CRC; 800f052: 6a7b ldr r3, [r7, #36] @ 0x24 800f054: f443 7380 orr.w r3, r3, #256 @ 0x100 800f058: 627b str r3, [r7, #36] @ 0x24 break; 800f05a: e000 b.n 800f05e break; 800f05c: bf00 nop } /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); 800f05e: 687b ldr r3, [r7, #4] 800f060: 681b ldr r3, [r3, #0] 800f062: 699a ldr r2, [r3, #24] 800f064: 687b ldr r3, [r7, #4] 800f066: 681b ldr r3, [r3, #0] 800f068: f022 0270 bic.w r2, r2, #112 @ 0x70 800f06c: 619a str r2, [r3, #24] } } /* Clear ERRI Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); 800f06e: 687b ldr r3, [r7, #4] 800f070: 681b ldr r3, [r3, #0] 800f072: 2204 movs r2, #4 800f074: 605a str r2, [r3, #4] } /* Call the Error call Back in case of Errors */ if (errorcode != HAL_CAN_ERROR_NONE) 800f076: 6a7b ldr r3, [r7, #36] @ 0x24 800f078: 2b00 cmp r3, #0 800f07a: d008 beq.n 800f08e { /* Update error code in handle */ hcan->ErrorCode |= errorcode; 800f07c: 687b ldr r3, [r7, #4] 800f07e: 6a5a ldr r2, [r3, #36] @ 0x24 800f080: 6a7b ldr r3, [r7, #36] @ 0x24 800f082: 431a orrs r2, r3 800f084: 687b ldr r3, [r7, #4] 800f086: 625a str r2, [r3, #36] @ 0x24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->ErrorCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); 800f088: 6878 ldr r0, [r7, #4] 800f08a: f000 f867 bl 800f15c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } 800f08e: bf00 nop 800f090: 3728 adds r7, #40 @ 0x28 800f092: 46bd mov sp, r7 800f094: bd80 pop {r7, pc} 0800f096 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { 800f096: b480 push {r7} 800f098: b083 sub sp, #12 800f09a: af00 add r7, sp, #0 800f09c: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the user file */ } 800f09e: bf00 nop 800f0a0: 370c adds r7, #12 800f0a2: 46bd mov sp, r7 800f0a4: bc80 pop {r7} 800f0a6: 4770 bx lr 0800f0a8 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { 800f0a8: b480 push {r7} 800f0aa: b083 sub sp, #12 800f0ac: af00 add r7, sp, #0 800f0ae: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the user file */ } 800f0b0: bf00 nop 800f0b2: 370c adds r7, #12 800f0b4: 46bd mov sp, r7 800f0b6: bc80 pop {r7} 800f0b8: 4770 bx lr 0800f0ba : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) { 800f0ba: b480 push {r7} 800f0bc: b083 sub sp, #12 800f0be: af00 add r7, sp, #0 800f0c0: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the user file */ } 800f0c2: bf00 nop 800f0c4: 370c adds r7, #12 800f0c6: 46bd mov sp, r7 800f0c8: bc80 pop {r7} 800f0ca: 4770 bx lr 0800f0cc : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { 800f0cc: b480 push {r7} 800f0ce: b083 sub sp, #12 800f0d0: af00 add r7, sp, #0 800f0d2: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } 800f0d4: bf00 nop 800f0d6: 370c adds r7, #12 800f0d8: 46bd mov sp, r7 800f0da: bc80 pop {r7} 800f0dc: 4770 bx lr 0800f0de : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { 800f0de: b480 push {r7} 800f0e0: b083 sub sp, #12 800f0e2: af00 add r7, sp, #0 800f0e4: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } 800f0e6: bf00 nop 800f0e8: 370c adds r7, #12 800f0ea: 46bd mov sp, r7 800f0ec: bc80 pop {r7} 800f0ee: 4770 bx lr 0800f0f0 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { 800f0f0: b480 push {r7} 800f0f2: b083 sub sp, #12 800f0f4: af00 add r7, sp, #0 800f0f6: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } 800f0f8: bf00 nop 800f0fa: 370c adds r7, #12 800f0fc: 46bd mov sp, r7 800f0fe: bc80 pop {r7} 800f100: 4770 bx lr 0800f102 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { 800f102: b480 push {r7} 800f104: b083 sub sp, #12 800f106: af00 add r7, sp, #0 800f108: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the user file */ } 800f10a: bf00 nop 800f10c: 370c adds r7, #12 800f10e: 46bd mov sp, r7 800f110: bc80 pop {r7} 800f112: 4770 bx lr 0800f114 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { 800f114: b480 push {r7} 800f116: b083 sub sp, #12 800f118: af00 add r7, sp, #0 800f11a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } 800f11c: bf00 nop 800f11e: 370c adds r7, #12 800f120: 46bd mov sp, r7 800f122: bc80 pop {r7} 800f124: 4770 bx lr 0800f126 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { 800f126: b480 push {r7} 800f128: b083 sub sp, #12 800f12a: af00 add r7, sp, #0 800f12c: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } 800f12e: bf00 nop 800f130: 370c adds r7, #12 800f132: 46bd mov sp, r7 800f134: bc80 pop {r7} 800f136: 4770 bx lr 0800f138 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { 800f138: b480 push {r7} 800f13a: b083 sub sp, #12 800f13c: af00 add r7, sp, #0 800f13e: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } 800f140: bf00 nop 800f142: 370c adds r7, #12 800f144: 46bd mov sp, r7 800f146: bc80 pop {r7} 800f148: 4770 bx lr 0800f14a : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { 800f14a: b480 push {r7} 800f14c: b083 sub sp, #12 800f14e: af00 add r7, sp, #0 800f150: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } 800f152: bf00 nop 800f154: 370c adds r7, #12 800f156: 46bd mov sp, r7 800f158: bc80 pop {r7} 800f15a: 4770 bx lr 0800f15c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { 800f15c: b480 push {r7} 800f15e: b083 sub sp, #12 800f160: af00 add r7, sp, #0 800f162: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } 800f164: bf00 nop 800f166: 370c adds r7, #12 800f168: 46bd mov sp, r7 800f16a: bc80 pop {r7} 800f16c: 4770 bx lr ... 0800f170 <__NVIC_SetPriorityGrouping>: { 800f170: b480 push {r7} 800f172: b085 sub sp, #20 800f174: af00 add r7, sp, #0 800f176: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800f178: 687b ldr r3, [r7, #4] 800f17a: f003 0307 and.w r3, r3, #7 800f17e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 800f180: 4b0c ldr r3, [pc, #48] @ (800f1b4 <__NVIC_SetPriorityGrouping+0x44>) 800f182: 68db ldr r3, [r3, #12] 800f184: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800f186: 68ba ldr r2, [r7, #8] 800f188: f64f 03ff movw r3, #63743 @ 0xf8ff 800f18c: 4013 ands r3, r2 800f18e: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800f190: 68fb ldr r3, [r7, #12] 800f192: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800f194: 68bb ldr r3, [r7, #8] 800f196: 4313 orrs r3, r2 reg_value = (reg_value | 800f198: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 800f19c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800f1a0: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800f1a2: 4a04 ldr r2, [pc, #16] @ (800f1b4 <__NVIC_SetPriorityGrouping+0x44>) 800f1a4: 68bb ldr r3, [r7, #8] 800f1a6: 60d3 str r3, [r2, #12] } 800f1a8: bf00 nop 800f1aa: 3714 adds r7, #20 800f1ac: 46bd mov sp, r7 800f1ae: bc80 pop {r7} 800f1b0: 4770 bx lr 800f1b2: bf00 nop 800f1b4: e000ed00 .word 0xe000ed00 0800f1b8 <__NVIC_GetPriorityGrouping>: { 800f1b8: b480 push {r7} 800f1ba: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800f1bc: 4b04 ldr r3, [pc, #16] @ (800f1d0 <__NVIC_GetPriorityGrouping+0x18>) 800f1be: 68db ldr r3, [r3, #12] 800f1c0: 0a1b lsrs r3, r3, #8 800f1c2: f003 0307 and.w r3, r3, #7 } 800f1c6: 4618 mov r0, r3 800f1c8: 46bd mov sp, r7 800f1ca: bc80 pop {r7} 800f1cc: 4770 bx lr 800f1ce: bf00 nop 800f1d0: e000ed00 .word 0xe000ed00 0800f1d4 <__NVIC_EnableIRQ>: { 800f1d4: b480 push {r7} 800f1d6: b083 sub sp, #12 800f1d8: af00 add r7, sp, #0 800f1da: 4603 mov r3, r0 800f1dc: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800f1de: f997 3007 ldrsb.w r3, [r7, #7] 800f1e2: 2b00 cmp r3, #0 800f1e4: db0b blt.n 800f1fe <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800f1e6: 79fb ldrb r3, [r7, #7] 800f1e8: f003 021f and.w r2, r3, #31 800f1ec: 4906 ldr r1, [pc, #24] @ (800f208 <__NVIC_EnableIRQ+0x34>) 800f1ee: f997 3007 ldrsb.w r3, [r7, #7] 800f1f2: 095b lsrs r3, r3, #5 800f1f4: 2001 movs r0, #1 800f1f6: fa00 f202 lsl.w r2, r0, r2 800f1fa: f841 2023 str.w r2, [r1, r3, lsl #2] } 800f1fe: bf00 nop 800f200: 370c adds r7, #12 800f202: 46bd mov sp, r7 800f204: bc80 pop {r7} 800f206: 4770 bx lr 800f208: e000e100 .word 0xe000e100 0800f20c <__NVIC_SetPriority>: { 800f20c: b480 push {r7} 800f20e: b083 sub sp, #12 800f210: af00 add r7, sp, #0 800f212: 4603 mov r3, r0 800f214: 6039 str r1, [r7, #0] 800f216: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800f218: f997 3007 ldrsb.w r3, [r7, #7] 800f21c: 2b00 cmp r3, #0 800f21e: db0a blt.n 800f236 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800f220: 683b ldr r3, [r7, #0] 800f222: b2da uxtb r2, r3 800f224: 490c ldr r1, [pc, #48] @ (800f258 <__NVIC_SetPriority+0x4c>) 800f226: f997 3007 ldrsb.w r3, [r7, #7] 800f22a: 0112 lsls r2, r2, #4 800f22c: b2d2 uxtb r2, r2 800f22e: 440b add r3, r1 800f230: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 800f234: e00a b.n 800f24c <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800f236: 683b ldr r3, [r7, #0] 800f238: b2da uxtb r2, r3 800f23a: 4908 ldr r1, [pc, #32] @ (800f25c <__NVIC_SetPriority+0x50>) 800f23c: 79fb ldrb r3, [r7, #7] 800f23e: f003 030f and.w r3, r3, #15 800f242: 3b04 subs r3, #4 800f244: 0112 lsls r2, r2, #4 800f246: b2d2 uxtb r2, r2 800f248: 440b add r3, r1 800f24a: 761a strb r2, [r3, #24] } 800f24c: bf00 nop 800f24e: 370c adds r7, #12 800f250: 46bd mov sp, r7 800f252: bc80 pop {r7} 800f254: 4770 bx lr 800f256: bf00 nop 800f258: e000e100 .word 0xe000e100 800f25c: e000ed00 .word 0xe000ed00 0800f260 : { 800f260: b480 push {r7} 800f262: b089 sub sp, #36 @ 0x24 800f264: af00 add r7, sp, #0 800f266: 60f8 str r0, [r7, #12] 800f268: 60b9 str r1, [r7, #8] 800f26a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800f26c: 68fb ldr r3, [r7, #12] 800f26e: f003 0307 and.w r3, r3, #7 800f272: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 800f274: 69fb ldr r3, [r7, #28] 800f276: f1c3 0307 rsb r3, r3, #7 800f27a: 2b04 cmp r3, #4 800f27c: bf28 it cs 800f27e: 2304 movcs r3, #4 800f280: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800f282: 69fb ldr r3, [r7, #28] 800f284: 3304 adds r3, #4 800f286: 2b06 cmp r3, #6 800f288: d902 bls.n 800f290 800f28a: 69fb ldr r3, [r7, #28] 800f28c: 3b03 subs r3, #3 800f28e: e000 b.n 800f292 800f290: 2300 movs r3, #0 800f292: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800f294: f04f 32ff mov.w r2, #4294967295 800f298: 69bb ldr r3, [r7, #24] 800f29a: fa02 f303 lsl.w r3, r2, r3 800f29e: 43da mvns r2, r3 800f2a0: 68bb ldr r3, [r7, #8] 800f2a2: 401a ands r2, r3 800f2a4: 697b ldr r3, [r7, #20] 800f2a6: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800f2a8: f04f 31ff mov.w r1, #4294967295 800f2ac: 697b ldr r3, [r7, #20] 800f2ae: fa01 f303 lsl.w r3, r1, r3 800f2b2: 43d9 mvns r1, r3 800f2b4: 687b ldr r3, [r7, #4] 800f2b6: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800f2b8: 4313 orrs r3, r2 } 800f2ba: 4618 mov r0, r3 800f2bc: 3724 adds r7, #36 @ 0x24 800f2be: 46bd mov sp, r7 800f2c0: bc80 pop {r7} 800f2c2: 4770 bx lr 0800f2c4 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800f2c4: b580 push {r7, lr} 800f2c6: b082 sub sp, #8 800f2c8: af00 add r7, sp, #0 800f2ca: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 800f2cc: 687b ldr r3, [r7, #4] 800f2ce: 3b01 subs r3, #1 800f2d0: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800f2d4: d301 bcc.n 800f2da { return (1UL); /* Reload value impossible */ 800f2d6: 2301 movs r3, #1 800f2d8: e00f b.n 800f2fa } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800f2da: 4a0a ldr r2, [pc, #40] @ (800f304 ) 800f2dc: 687b ldr r3, [r7, #4] 800f2de: 3b01 subs r3, #1 800f2e0: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800f2e2: 210f movs r1, #15 800f2e4: f04f 30ff mov.w r0, #4294967295 800f2e8: f7ff ff90 bl 800f20c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800f2ec: 4b05 ldr r3, [pc, #20] @ (800f304 ) 800f2ee: 2200 movs r2, #0 800f2f0: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800f2f2: 4b04 ldr r3, [pc, #16] @ (800f304 ) 800f2f4: 2207 movs r2, #7 800f2f6: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 800f2f8: 2300 movs r3, #0 } 800f2fa: 4618 mov r0, r3 800f2fc: 3708 adds r7, #8 800f2fe: 46bd mov sp, r7 800f300: bd80 pop {r7, pc} 800f302: bf00 nop 800f304: e000e010 .word 0xe000e010 0800f308 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 800f308: b580 push {r7, lr} 800f30a: b082 sub sp, #8 800f30c: af00 add r7, sp, #0 800f30e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800f310: 6878 ldr r0, [r7, #4] 800f312: f7ff ff2d bl 800f170 <__NVIC_SetPriorityGrouping> } 800f316: bf00 nop 800f318: 3708 adds r7, #8 800f31a: 46bd mov sp, r7 800f31c: bd80 pop {r7, pc} 0800f31e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800f31e: b580 push {r7, lr} 800f320: b086 sub sp, #24 800f322: af00 add r7, sp, #0 800f324: 4603 mov r3, r0 800f326: 60b9 str r1, [r7, #8] 800f328: 607a str r2, [r7, #4] 800f32a: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 800f32c: 2300 movs r3, #0 800f32e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800f330: f7ff ff42 bl 800f1b8 <__NVIC_GetPriorityGrouping> 800f334: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800f336: 687a ldr r2, [r7, #4] 800f338: 68b9 ldr r1, [r7, #8] 800f33a: 6978 ldr r0, [r7, #20] 800f33c: f7ff ff90 bl 800f260 800f340: 4602 mov r2, r0 800f342: f997 300f ldrsb.w r3, [r7, #15] 800f346: 4611 mov r1, r2 800f348: 4618 mov r0, r3 800f34a: f7ff ff5f bl 800f20c <__NVIC_SetPriority> } 800f34e: bf00 nop 800f350: 3718 adds r7, #24 800f352: 46bd mov sp, r7 800f354: bd80 pop {r7, pc} 0800f356 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 800f356: b580 push {r7, lr} 800f358: b082 sub sp, #8 800f35a: af00 add r7, sp, #0 800f35c: 4603 mov r3, r0 800f35e: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800f360: f997 3007 ldrsb.w r3, [r7, #7] 800f364: 4618 mov r0, r3 800f366: f7ff ff35 bl 800f1d4 <__NVIC_EnableIRQ> } 800f36a: bf00 nop 800f36c: 3708 adds r7, #8 800f36e: 46bd mov sp, r7 800f370: bd80 pop {r7, pc} 0800f372 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800f372: b580 push {r7, lr} 800f374: b082 sub sp, #8 800f376: af00 add r7, sp, #0 800f378: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800f37a: 6878 ldr r0, [r7, #4] 800f37c: f7ff ffa2 bl 800f2c4 800f380: 4603 mov r3, r0 } 800f382: 4618 mov r0, r3 800f384: 3708 adds r7, #8 800f386: 46bd mov sp, r7 800f388: bd80 pop {r7, pc} 0800f38a : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 800f38a: b580 push {r7, lr} 800f38c: b082 sub sp, #8 800f38e: af00 add r7, sp, #0 800f390: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 800f392: 687b ldr r3, [r7, #4] 800f394: 2b00 cmp r3, #0 800f396: d101 bne.n 800f39c { return HAL_ERROR; 800f398: 2301 movs r3, #1 800f39a: e00e b.n 800f3ba } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 800f39c: 687b ldr r3, [r7, #4] 800f39e: 795b ldrb r3, [r3, #5] 800f3a0: b2db uxtb r3, r3 800f3a2: 2b00 cmp r3, #0 800f3a4: d105 bne.n 800f3b2 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 800f3a6: 687b ldr r3, [r7, #4] 800f3a8: 2200 movs r2, #0 800f3aa: 711a strb r2, [r3, #4] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 800f3ac: 6878 ldr r0, [r7, #4] 800f3ae: f7fa ff61 bl 800a274 } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 800f3b2: 687b ldr r3, [r7, #4] 800f3b4: 2201 movs r2, #1 800f3b6: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 800f3b8: 2300 movs r3, #0 } 800f3ba: 4618 mov r0, r3 800f3bc: 3708 adds r7, #8 800f3be: 46bd mov sp, r7 800f3c0: bd80 pop {r7, pc} 0800f3c2 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 800f3c2: b480 push {r7} 800f3c4: b085 sub sp, #20 800f3c6: af00 add r7, sp, #0 800f3c8: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800f3ca: 2300 movs r3, #0 800f3cc: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 800f3ce: 687b ldr r3, [r7, #4] 800f3d0: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800f3d4: b2db uxtb r3, r3 800f3d6: 2b02 cmp r3, #2 800f3d8: d008 beq.n 800f3ec { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800f3da: 687b ldr r3, [r7, #4] 800f3dc: 2204 movs r2, #4 800f3de: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800f3e0: 687b ldr r3, [r7, #4] 800f3e2: 2200 movs r2, #0 800f3e4: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800f3e8: 2301 movs r3, #1 800f3ea: e020 b.n 800f42e } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800f3ec: 687b ldr r3, [r7, #4] 800f3ee: 681b ldr r3, [r3, #0] 800f3f0: 681a ldr r2, [r3, #0] 800f3f2: 687b ldr r3, [r7, #4] 800f3f4: 681b ldr r3, [r3, #0] 800f3f6: f022 020e bic.w r2, r2, #14 800f3fa: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800f3fc: 687b ldr r3, [r7, #4] 800f3fe: 681b ldr r3, [r3, #0] 800f400: 681a ldr r2, [r3, #0] 800f402: 687b ldr r3, [r7, #4] 800f404: 681b ldr r3, [r3, #0] 800f406: f022 0201 bic.w r2, r2, #1 800f40a: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 800f40c: 687b ldr r3, [r7, #4] 800f40e: 6c1a ldr r2, [r3, #64] @ 0x40 800f410: 687b ldr r3, [r7, #4] 800f412: 6bdb ldr r3, [r3, #60] @ 0x3c 800f414: 2101 movs r1, #1 800f416: fa01 f202 lsl.w r2, r1, r2 800f41a: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800f41c: 687b ldr r3, [r7, #4] 800f41e: 2201 movs r2, #1 800f420: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800f424: 687b ldr r3, [r7, #4] 800f426: 2200 movs r2, #0 800f428: f883 2020 strb.w r2, [r3, #32] return status; 800f42c: 7bfb ldrb r3, [r7, #15] } 800f42e: 4618 mov r0, r3 800f430: 3714 adds r7, #20 800f432: 46bd mov sp, r7 800f434: bc80 pop {r7} 800f436: 4770 bx lr 0800f438 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 800f438: b580 push {r7, lr} 800f43a: b084 sub sp, #16 800f43c: af00 add r7, sp, #0 800f43e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800f440: 2300 movs r3, #0 800f442: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 800f444: 687b ldr r3, [r7, #4] 800f446: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800f44a: b2db uxtb r3, r3 800f44c: 2b02 cmp r3, #2 800f44e: d005 beq.n 800f45c { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800f450: 687b ldr r3, [r7, #4] 800f452: 2204 movs r2, #4 800f454: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 800f456: 2301 movs r3, #1 800f458: 73fb strb r3, [r7, #15] 800f45a: e0d6 b.n 800f60a } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800f45c: 687b ldr r3, [r7, #4] 800f45e: 681b ldr r3, [r3, #0] 800f460: 681a ldr r2, [r3, #0] 800f462: 687b ldr r3, [r7, #4] 800f464: 681b ldr r3, [r3, #0] 800f466: f022 020e bic.w r2, r2, #14 800f46a: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800f46c: 687b ldr r3, [r7, #4] 800f46e: 681b ldr r3, [r3, #0] 800f470: 681a ldr r2, [r3, #0] 800f472: 687b ldr r3, [r7, #4] 800f474: 681b ldr r3, [r3, #0] 800f476: f022 0201 bic.w r2, r2, #1 800f47a: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 800f47c: 687b ldr r3, [r7, #4] 800f47e: 681b ldr r3, [r3, #0] 800f480: 461a mov r2, r3 800f482: 4b64 ldr r3, [pc, #400] @ (800f614 ) 800f484: 429a cmp r2, r3 800f486: d958 bls.n 800f53a 800f488: 687b ldr r3, [r7, #4] 800f48a: 681b ldr r3, [r3, #0] 800f48c: 4a62 ldr r2, [pc, #392] @ (800f618 ) 800f48e: 4293 cmp r3, r2 800f490: d04f beq.n 800f532 800f492: 687b ldr r3, [r7, #4] 800f494: 681b ldr r3, [r3, #0] 800f496: 4a61 ldr r2, [pc, #388] @ (800f61c ) 800f498: 4293 cmp r3, r2 800f49a: d048 beq.n 800f52e 800f49c: 687b ldr r3, [r7, #4] 800f49e: 681b ldr r3, [r3, #0] 800f4a0: 4a5f ldr r2, [pc, #380] @ (800f620 ) 800f4a2: 4293 cmp r3, r2 800f4a4: d040 beq.n 800f528 800f4a6: 687b ldr r3, [r7, #4] 800f4a8: 681b ldr r3, [r3, #0] 800f4aa: 4a5e ldr r2, [pc, #376] @ (800f624 ) 800f4ac: 4293 cmp r3, r2 800f4ae: d038 beq.n 800f522 800f4b0: 687b ldr r3, [r7, #4] 800f4b2: 681b ldr r3, [r3, #0] 800f4b4: 4a5c ldr r2, [pc, #368] @ (800f628 ) 800f4b6: 4293 cmp r3, r2 800f4b8: d030 beq.n 800f51c 800f4ba: 687b ldr r3, [r7, #4] 800f4bc: 681b ldr r3, [r3, #0] 800f4be: 4a5b ldr r2, [pc, #364] @ (800f62c ) 800f4c0: 4293 cmp r3, r2 800f4c2: d028 beq.n 800f516 800f4c4: 687b ldr r3, [r7, #4] 800f4c6: 681b ldr r3, [r3, #0] 800f4c8: 4a52 ldr r2, [pc, #328] @ (800f614 ) 800f4ca: 4293 cmp r3, r2 800f4cc: d020 beq.n 800f510 800f4ce: 687b ldr r3, [r7, #4] 800f4d0: 681b ldr r3, [r3, #0] 800f4d2: 4a57 ldr r2, [pc, #348] @ (800f630 ) 800f4d4: 4293 cmp r3, r2 800f4d6: d019 beq.n 800f50c 800f4d8: 687b ldr r3, [r7, #4] 800f4da: 681b ldr r3, [r3, #0] 800f4dc: 4a55 ldr r2, [pc, #340] @ (800f634 ) 800f4de: 4293 cmp r3, r2 800f4e0: d012 beq.n 800f508 800f4e2: 687b ldr r3, [r7, #4] 800f4e4: 681b ldr r3, [r3, #0] 800f4e6: 4a54 ldr r2, [pc, #336] @ (800f638 ) 800f4e8: 4293 cmp r3, r2 800f4ea: d00a beq.n 800f502 800f4ec: 687b ldr r3, [r7, #4] 800f4ee: 681b ldr r3, [r3, #0] 800f4f0: 4a52 ldr r2, [pc, #328] @ (800f63c ) 800f4f2: 4293 cmp r3, r2 800f4f4: d102 bne.n 800f4fc 800f4f6: f44f 5380 mov.w r3, #4096 @ 0x1000 800f4fa: e01b b.n 800f534 800f4fc: f44f 3380 mov.w r3, #65536 @ 0x10000 800f500: e018 b.n 800f534 800f502: f44f 7380 mov.w r3, #256 @ 0x100 800f506: e015 b.n 800f534 800f508: 2310 movs r3, #16 800f50a: e013 b.n 800f534 800f50c: 2301 movs r3, #1 800f50e: e011 b.n 800f534 800f510: f04f 7380 mov.w r3, #16777216 @ 0x1000000 800f514: e00e b.n 800f534 800f516: f44f 1380 mov.w r3, #1048576 @ 0x100000 800f51a: e00b b.n 800f534 800f51c: f44f 3380 mov.w r3, #65536 @ 0x10000 800f520: e008 b.n 800f534 800f522: f44f 5380 mov.w r3, #4096 @ 0x1000 800f526: e005 b.n 800f534 800f528: f44f 7380 mov.w r3, #256 @ 0x100 800f52c: e002 b.n 800f534 800f52e: 2310 movs r3, #16 800f530: e000 b.n 800f534 800f532: 2301 movs r3, #1 800f534: 4a42 ldr r2, [pc, #264] @ (800f640 ) 800f536: 6053 str r3, [r2, #4] 800f538: e057 b.n 800f5ea 800f53a: 687b ldr r3, [r7, #4] 800f53c: 681b ldr r3, [r3, #0] 800f53e: 4a36 ldr r2, [pc, #216] @ (800f618 ) 800f540: 4293 cmp r3, r2 800f542: d04f beq.n 800f5e4 800f544: 687b ldr r3, [r7, #4] 800f546: 681b ldr r3, [r3, #0] 800f548: 4a34 ldr r2, [pc, #208] @ (800f61c ) 800f54a: 4293 cmp r3, r2 800f54c: d048 beq.n 800f5e0 800f54e: 687b ldr r3, [r7, #4] 800f550: 681b ldr r3, [r3, #0] 800f552: 4a33 ldr r2, [pc, #204] @ (800f620 ) 800f554: 4293 cmp r3, r2 800f556: d040 beq.n 800f5da 800f558: 687b ldr r3, [r7, #4] 800f55a: 681b ldr r3, [r3, #0] 800f55c: 4a31 ldr r2, [pc, #196] @ (800f624 ) 800f55e: 4293 cmp r3, r2 800f560: d038 beq.n 800f5d4 800f562: 687b ldr r3, [r7, #4] 800f564: 681b ldr r3, [r3, #0] 800f566: 4a30 ldr r2, [pc, #192] @ (800f628 ) 800f568: 4293 cmp r3, r2 800f56a: d030 beq.n 800f5ce 800f56c: 687b ldr r3, [r7, #4] 800f56e: 681b ldr r3, [r3, #0] 800f570: 4a2e ldr r2, [pc, #184] @ (800f62c ) 800f572: 4293 cmp r3, r2 800f574: d028 beq.n 800f5c8 800f576: 687b ldr r3, [r7, #4] 800f578: 681b ldr r3, [r3, #0] 800f57a: 4a26 ldr r2, [pc, #152] @ (800f614 ) 800f57c: 4293 cmp r3, r2 800f57e: d020 beq.n 800f5c2 800f580: 687b ldr r3, [r7, #4] 800f582: 681b ldr r3, [r3, #0] 800f584: 4a2a ldr r2, [pc, #168] @ (800f630 ) 800f586: 4293 cmp r3, r2 800f588: d019 beq.n 800f5be 800f58a: 687b ldr r3, [r7, #4] 800f58c: 681b ldr r3, [r3, #0] 800f58e: 4a29 ldr r2, [pc, #164] @ (800f634 ) 800f590: 4293 cmp r3, r2 800f592: d012 beq.n 800f5ba 800f594: 687b ldr r3, [r7, #4] 800f596: 681b ldr r3, [r3, #0] 800f598: 4a27 ldr r2, [pc, #156] @ (800f638 ) 800f59a: 4293 cmp r3, r2 800f59c: d00a beq.n 800f5b4 800f59e: 687b ldr r3, [r7, #4] 800f5a0: 681b ldr r3, [r3, #0] 800f5a2: 4a26 ldr r2, [pc, #152] @ (800f63c ) 800f5a4: 4293 cmp r3, r2 800f5a6: d102 bne.n 800f5ae 800f5a8: f44f 5380 mov.w r3, #4096 @ 0x1000 800f5ac: e01b b.n 800f5e6 800f5ae: f44f 3380 mov.w r3, #65536 @ 0x10000 800f5b2: e018 b.n 800f5e6 800f5b4: f44f 7380 mov.w r3, #256 @ 0x100 800f5b8: e015 b.n 800f5e6 800f5ba: 2310 movs r3, #16 800f5bc: e013 b.n 800f5e6 800f5be: 2301 movs r3, #1 800f5c0: e011 b.n 800f5e6 800f5c2: f04f 7380 mov.w r3, #16777216 @ 0x1000000 800f5c6: e00e b.n 800f5e6 800f5c8: f44f 1380 mov.w r3, #1048576 @ 0x100000 800f5cc: e00b b.n 800f5e6 800f5ce: f44f 3380 mov.w r3, #65536 @ 0x10000 800f5d2: e008 b.n 800f5e6 800f5d4: f44f 5380 mov.w r3, #4096 @ 0x1000 800f5d8: e005 b.n 800f5e6 800f5da: f44f 7380 mov.w r3, #256 @ 0x100 800f5de: e002 b.n 800f5e6 800f5e0: 2310 movs r3, #16 800f5e2: e000 b.n 800f5e6 800f5e4: 2301 movs r3, #1 800f5e6: 4a17 ldr r2, [pc, #92] @ (800f644 ) 800f5e8: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800f5ea: 687b ldr r3, [r7, #4] 800f5ec: 2201 movs r2, #1 800f5ee: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800f5f2: 687b ldr r3, [r7, #4] 800f5f4: 2200 movs r2, #0 800f5f6: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 800f5fa: 687b ldr r3, [r7, #4] 800f5fc: 6b5b ldr r3, [r3, #52] @ 0x34 800f5fe: 2b00 cmp r3, #0 800f600: d003 beq.n 800f60a { hdma->XferAbortCallback(hdma); 800f602: 687b ldr r3, [r7, #4] 800f604: 6b5b ldr r3, [r3, #52] @ 0x34 800f606: 6878 ldr r0, [r7, #4] 800f608: 4798 blx r3 } } return status; 800f60a: 7bfb ldrb r3, [r7, #15] } 800f60c: 4618 mov r0, r3 800f60e: 3710 adds r7, #16 800f610: 46bd mov sp, r7 800f612: bd80 pop {r7, pc} 800f614: 40020080 .word 0x40020080 800f618: 40020008 .word 0x40020008 800f61c: 4002001c .word 0x4002001c 800f620: 40020030 .word 0x40020030 800f624: 40020044 .word 0x40020044 800f628: 40020058 .word 0x40020058 800f62c: 4002006c .word 0x4002006c 800f630: 40020408 .word 0x40020408 800f634: 4002041c .word 0x4002041c 800f638: 40020430 .word 0x40020430 800f63c: 40020444 .word 0x40020444 800f640: 40020400 .word 0x40020400 800f644: 40020000 .word 0x40020000 0800f648 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800f648: b480 push {r7} 800f64a: b08b sub sp, #44 @ 0x2c 800f64c: af00 add r7, sp, #0 800f64e: 6078 str r0, [r7, #4] 800f650: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 800f652: 2300 movs r3, #0 800f654: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 800f656: 2300 movs r3, #0 800f658: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800f65a: e169 b.n 800f930 { /* Get the IO position */ ioposition = (0x01uL << position); 800f65c: 2201 movs r2, #1 800f65e: 6a7b ldr r3, [r7, #36] @ 0x24 800f660: fa02 f303 lsl.w r3, r2, r3 800f664: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 800f666: 683b ldr r3, [r7, #0] 800f668: 681b ldr r3, [r3, #0] 800f66a: 69fa ldr r2, [r7, #28] 800f66c: 4013 ands r3, r2 800f66e: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 800f670: 69ba ldr r2, [r7, #24] 800f672: 69fb ldr r3, [r7, #28] 800f674: 429a cmp r2, r3 800f676: f040 8158 bne.w 800f92a { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 800f67a: 683b ldr r3, [r7, #0] 800f67c: 685b ldr r3, [r3, #4] 800f67e: 4a9a ldr r2, [pc, #616] @ (800f8e8 ) 800f680: 4293 cmp r3, r2 800f682: d05e beq.n 800f742 800f684: 4a98 ldr r2, [pc, #608] @ (800f8e8 ) 800f686: 4293 cmp r3, r2 800f688: d875 bhi.n 800f776 800f68a: 4a98 ldr r2, [pc, #608] @ (800f8ec ) 800f68c: 4293 cmp r3, r2 800f68e: d058 beq.n 800f742 800f690: 4a96 ldr r2, [pc, #600] @ (800f8ec ) 800f692: 4293 cmp r3, r2 800f694: d86f bhi.n 800f776 800f696: 4a96 ldr r2, [pc, #600] @ (800f8f0 ) 800f698: 4293 cmp r3, r2 800f69a: d052 beq.n 800f742 800f69c: 4a94 ldr r2, [pc, #592] @ (800f8f0 ) 800f69e: 4293 cmp r3, r2 800f6a0: d869 bhi.n 800f776 800f6a2: 4a94 ldr r2, [pc, #592] @ (800f8f4 ) 800f6a4: 4293 cmp r3, r2 800f6a6: d04c beq.n 800f742 800f6a8: 4a92 ldr r2, [pc, #584] @ (800f8f4 ) 800f6aa: 4293 cmp r3, r2 800f6ac: d863 bhi.n 800f776 800f6ae: 4a92 ldr r2, [pc, #584] @ (800f8f8 ) 800f6b0: 4293 cmp r3, r2 800f6b2: d046 beq.n 800f742 800f6b4: 4a90 ldr r2, [pc, #576] @ (800f8f8 ) 800f6b6: 4293 cmp r3, r2 800f6b8: d85d bhi.n 800f776 800f6ba: 2b12 cmp r3, #18 800f6bc: d82a bhi.n 800f714 800f6be: 2b12 cmp r3, #18 800f6c0: d859 bhi.n 800f776 800f6c2: a201 add r2, pc, #4 @ (adr r2, 800f6c8 ) 800f6c4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800f6c8: 0800f743 .word 0x0800f743 800f6cc: 0800f71d .word 0x0800f71d 800f6d0: 0800f72f .word 0x0800f72f 800f6d4: 0800f771 .word 0x0800f771 800f6d8: 0800f777 .word 0x0800f777 800f6dc: 0800f777 .word 0x0800f777 800f6e0: 0800f777 .word 0x0800f777 800f6e4: 0800f777 .word 0x0800f777 800f6e8: 0800f777 .word 0x0800f777 800f6ec: 0800f777 .word 0x0800f777 800f6f0: 0800f777 .word 0x0800f777 800f6f4: 0800f777 .word 0x0800f777 800f6f8: 0800f777 .word 0x0800f777 800f6fc: 0800f777 .word 0x0800f777 800f700: 0800f777 .word 0x0800f777 800f704: 0800f777 .word 0x0800f777 800f708: 0800f777 .word 0x0800f777 800f70c: 0800f725 .word 0x0800f725 800f710: 0800f739 .word 0x0800f739 800f714: 4a79 ldr r2, [pc, #484] @ (800f8fc ) 800f716: 4293 cmp r3, r2 800f718: d013 beq.n 800f742 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 800f71a: e02c b.n 800f776 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 800f71c: 683b ldr r3, [r7, #0] 800f71e: 68db ldr r3, [r3, #12] 800f720: 623b str r3, [r7, #32] break; 800f722: e029 b.n 800f778 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 800f724: 683b ldr r3, [r7, #0] 800f726: 68db ldr r3, [r3, #12] 800f728: 3304 adds r3, #4 800f72a: 623b str r3, [r7, #32] break; 800f72c: e024 b.n 800f778 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 800f72e: 683b ldr r3, [r7, #0] 800f730: 68db ldr r3, [r3, #12] 800f732: 3308 adds r3, #8 800f734: 623b str r3, [r7, #32] break; 800f736: e01f b.n 800f778 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 800f738: 683b ldr r3, [r7, #0] 800f73a: 68db ldr r3, [r3, #12] 800f73c: 330c adds r3, #12 800f73e: 623b str r3, [r7, #32] break; 800f740: e01a b.n 800f778 if (GPIO_Init->Pull == GPIO_NOPULL) 800f742: 683b ldr r3, [r7, #0] 800f744: 689b ldr r3, [r3, #8] 800f746: 2b00 cmp r3, #0 800f748: d102 bne.n 800f750 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 800f74a: 2304 movs r3, #4 800f74c: 623b str r3, [r7, #32] break; 800f74e: e013 b.n 800f778 else if (GPIO_Init->Pull == GPIO_PULLUP) 800f750: 683b ldr r3, [r7, #0] 800f752: 689b ldr r3, [r3, #8] 800f754: 2b01 cmp r3, #1 800f756: d105 bne.n 800f764 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 800f758: 2308 movs r3, #8 800f75a: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 800f75c: 687b ldr r3, [r7, #4] 800f75e: 69fa ldr r2, [r7, #28] 800f760: 611a str r2, [r3, #16] break; 800f762: e009 b.n 800f778 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 800f764: 2308 movs r3, #8 800f766: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 800f768: 687b ldr r3, [r7, #4] 800f76a: 69fa ldr r2, [r7, #28] 800f76c: 615a str r2, [r3, #20] break; 800f76e: e003 b.n 800f778 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 800f770: 2300 movs r3, #0 800f772: 623b str r3, [r7, #32] break; 800f774: e000 b.n 800f778 break; 800f776: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 800f778: 69bb ldr r3, [r7, #24] 800f77a: 2bff cmp r3, #255 @ 0xff 800f77c: d801 bhi.n 800f782 800f77e: 687b ldr r3, [r7, #4] 800f780: e001 b.n 800f786 800f782: 687b ldr r3, [r7, #4] 800f784: 3304 adds r3, #4 800f786: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 800f788: 69bb ldr r3, [r7, #24] 800f78a: 2bff cmp r3, #255 @ 0xff 800f78c: d802 bhi.n 800f794 800f78e: 6a7b ldr r3, [r7, #36] @ 0x24 800f790: 009b lsls r3, r3, #2 800f792: e002 b.n 800f79a 800f794: 6a7b ldr r3, [r7, #36] @ 0x24 800f796: 3b08 subs r3, #8 800f798: 009b lsls r3, r3, #2 800f79a: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 800f79c: 697b ldr r3, [r7, #20] 800f79e: 681a ldr r2, [r3, #0] 800f7a0: 210f movs r1, #15 800f7a2: 693b ldr r3, [r7, #16] 800f7a4: fa01 f303 lsl.w r3, r1, r3 800f7a8: 43db mvns r3, r3 800f7aa: 401a ands r2, r3 800f7ac: 6a39 ldr r1, [r7, #32] 800f7ae: 693b ldr r3, [r7, #16] 800f7b0: fa01 f303 lsl.w r3, r1, r3 800f7b4: 431a orrs r2, r3 800f7b6: 697b ldr r3, [r7, #20] 800f7b8: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 800f7ba: 683b ldr r3, [r7, #0] 800f7bc: 685b ldr r3, [r3, #4] 800f7be: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800f7c2: 2b00 cmp r3, #0 800f7c4: f000 80b1 beq.w 800f92a { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 800f7c8: 4b4d ldr r3, [pc, #308] @ (800f900 ) 800f7ca: 699b ldr r3, [r3, #24] 800f7cc: 4a4c ldr r2, [pc, #304] @ (800f900 ) 800f7ce: f043 0301 orr.w r3, r3, #1 800f7d2: 6193 str r3, [r2, #24] 800f7d4: 4b4a ldr r3, [pc, #296] @ (800f900 ) 800f7d6: 699b ldr r3, [r3, #24] 800f7d8: f003 0301 and.w r3, r3, #1 800f7dc: 60bb str r3, [r7, #8] 800f7de: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 800f7e0: 4a48 ldr r2, [pc, #288] @ (800f904 ) 800f7e2: 6a7b ldr r3, [r7, #36] @ 0x24 800f7e4: 089b lsrs r3, r3, #2 800f7e6: 3302 adds r3, #2 800f7e8: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800f7ec: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 800f7ee: 6a7b ldr r3, [r7, #36] @ 0x24 800f7f0: f003 0303 and.w r3, r3, #3 800f7f4: 009b lsls r3, r3, #2 800f7f6: 220f movs r2, #15 800f7f8: fa02 f303 lsl.w r3, r2, r3 800f7fc: 43db mvns r3, r3 800f7fe: 68fa ldr r2, [r7, #12] 800f800: 4013 ands r3, r2 800f802: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 800f804: 687b ldr r3, [r7, #4] 800f806: 4a40 ldr r2, [pc, #256] @ (800f908 ) 800f808: 4293 cmp r3, r2 800f80a: d013 beq.n 800f834 800f80c: 687b ldr r3, [r7, #4] 800f80e: 4a3f ldr r2, [pc, #252] @ (800f90c ) 800f810: 4293 cmp r3, r2 800f812: d00d beq.n 800f830 800f814: 687b ldr r3, [r7, #4] 800f816: 4a3e ldr r2, [pc, #248] @ (800f910 ) 800f818: 4293 cmp r3, r2 800f81a: d007 beq.n 800f82c 800f81c: 687b ldr r3, [r7, #4] 800f81e: 4a3d ldr r2, [pc, #244] @ (800f914 ) 800f820: 4293 cmp r3, r2 800f822: d101 bne.n 800f828 800f824: 2303 movs r3, #3 800f826: e006 b.n 800f836 800f828: 2304 movs r3, #4 800f82a: e004 b.n 800f836 800f82c: 2302 movs r3, #2 800f82e: e002 b.n 800f836 800f830: 2301 movs r3, #1 800f832: e000 b.n 800f836 800f834: 2300 movs r3, #0 800f836: 6a7a ldr r2, [r7, #36] @ 0x24 800f838: f002 0203 and.w r2, r2, #3 800f83c: 0092 lsls r2, r2, #2 800f83e: 4093 lsls r3, r2 800f840: 68fa ldr r2, [r7, #12] 800f842: 4313 orrs r3, r2 800f844: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 800f846: 492f ldr r1, [pc, #188] @ (800f904 ) 800f848: 6a7b ldr r3, [r7, #36] @ 0x24 800f84a: 089b lsrs r3, r3, #2 800f84c: 3302 adds r3, #2 800f84e: 68fa ldr r2, [r7, #12] 800f850: f841 2023 str.w r2, [r1, r3, lsl #2] /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 800f854: 683b ldr r3, [r7, #0] 800f856: 685b ldr r3, [r3, #4] 800f858: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800f85c: 2b00 cmp r3, #0 800f85e: d006 beq.n 800f86e { SET_BIT(EXTI->RTSR, iocurrent); 800f860: 4b2d ldr r3, [pc, #180] @ (800f918 ) 800f862: 689a ldr r2, [r3, #8] 800f864: 492c ldr r1, [pc, #176] @ (800f918 ) 800f866: 69bb ldr r3, [r7, #24] 800f868: 4313 orrs r3, r2 800f86a: 608b str r3, [r1, #8] 800f86c: e006 b.n 800f87c } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 800f86e: 4b2a ldr r3, [pc, #168] @ (800f918 ) 800f870: 689a ldr r2, [r3, #8] 800f872: 69bb ldr r3, [r7, #24] 800f874: 43db mvns r3, r3 800f876: 4928 ldr r1, [pc, #160] @ (800f918 ) 800f878: 4013 ands r3, r2 800f87a: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 800f87c: 683b ldr r3, [r7, #0] 800f87e: 685b ldr r3, [r3, #4] 800f880: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800f884: 2b00 cmp r3, #0 800f886: d006 beq.n 800f896 { SET_BIT(EXTI->FTSR, iocurrent); 800f888: 4b23 ldr r3, [pc, #140] @ (800f918 ) 800f88a: 68da ldr r2, [r3, #12] 800f88c: 4922 ldr r1, [pc, #136] @ (800f918 ) 800f88e: 69bb ldr r3, [r7, #24] 800f890: 4313 orrs r3, r2 800f892: 60cb str r3, [r1, #12] 800f894: e006 b.n 800f8a4 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 800f896: 4b20 ldr r3, [pc, #128] @ (800f918 ) 800f898: 68da ldr r2, [r3, #12] 800f89a: 69bb ldr r3, [r7, #24] 800f89c: 43db mvns r3, r3 800f89e: 491e ldr r1, [pc, #120] @ (800f918 ) 800f8a0: 4013 ands r3, r2 800f8a2: 60cb str r3, [r1, #12] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 800f8a4: 683b ldr r3, [r7, #0] 800f8a6: 685b ldr r3, [r3, #4] 800f8a8: f403 3300 and.w r3, r3, #131072 @ 0x20000 800f8ac: 2b00 cmp r3, #0 800f8ae: d006 beq.n 800f8be { SET_BIT(EXTI->EMR, iocurrent); 800f8b0: 4b19 ldr r3, [pc, #100] @ (800f918 ) 800f8b2: 685a ldr r2, [r3, #4] 800f8b4: 4918 ldr r1, [pc, #96] @ (800f918 ) 800f8b6: 69bb ldr r3, [r7, #24] 800f8b8: 4313 orrs r3, r2 800f8ba: 604b str r3, [r1, #4] 800f8bc: e006 b.n 800f8cc } else { CLEAR_BIT(EXTI->EMR, iocurrent); 800f8be: 4b16 ldr r3, [pc, #88] @ (800f918 ) 800f8c0: 685a ldr r2, [r3, #4] 800f8c2: 69bb ldr r3, [r7, #24] 800f8c4: 43db mvns r3, r3 800f8c6: 4914 ldr r1, [pc, #80] @ (800f918 ) 800f8c8: 4013 ands r3, r2 800f8ca: 604b str r3, [r1, #4] } /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 800f8cc: 683b ldr r3, [r7, #0] 800f8ce: 685b ldr r3, [r3, #4] 800f8d0: f403 3380 and.w r3, r3, #65536 @ 0x10000 800f8d4: 2b00 cmp r3, #0 800f8d6: d021 beq.n 800f91c { SET_BIT(EXTI->IMR, iocurrent); 800f8d8: 4b0f ldr r3, [pc, #60] @ (800f918 ) 800f8da: 681a ldr r2, [r3, #0] 800f8dc: 490e ldr r1, [pc, #56] @ (800f918 ) 800f8de: 69bb ldr r3, [r7, #24] 800f8e0: 4313 orrs r3, r2 800f8e2: 600b str r3, [r1, #0] 800f8e4: e021 b.n 800f92a 800f8e6: bf00 nop 800f8e8: 10320000 .word 0x10320000 800f8ec: 10310000 .word 0x10310000 800f8f0: 10220000 .word 0x10220000 800f8f4: 10210000 .word 0x10210000 800f8f8: 10120000 .word 0x10120000 800f8fc: 10110000 .word 0x10110000 800f900: 40021000 .word 0x40021000 800f904: 40010000 .word 0x40010000 800f908: 40010800 .word 0x40010800 800f90c: 40010c00 .word 0x40010c00 800f910: 40011000 .word 0x40011000 800f914: 40011400 .word 0x40011400 800f918: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 800f91c: 4b0b ldr r3, [pc, #44] @ (800f94c ) 800f91e: 681a ldr r2, [r3, #0] 800f920: 69bb ldr r3, [r7, #24] 800f922: 43db mvns r3, r3 800f924: 4909 ldr r1, [pc, #36] @ (800f94c ) 800f926: 4013 ands r3, r2 800f928: 600b str r3, [r1, #0] } } } position++; 800f92a: 6a7b ldr r3, [r7, #36] @ 0x24 800f92c: 3301 adds r3, #1 800f92e: 627b str r3, [r7, #36] @ 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 800f930: 683b ldr r3, [r7, #0] 800f932: 681a ldr r2, [r3, #0] 800f934: 6a7b ldr r3, [r7, #36] @ 0x24 800f936: fa22 f303 lsr.w r3, r2, r3 800f93a: 2b00 cmp r3, #0 800f93c: f47f ae8e bne.w 800f65c } } 800f940: bf00 nop 800f942: bf00 nop 800f944: 372c adds r7, #44 @ 0x2c 800f946: 46bd mov sp, r7 800f948: bc80 pop {r7} 800f94a: 4770 bx lr 800f94c: 40010400 .word 0x40010400 0800f950 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800f950: b480 push {r7} 800f952: b085 sub sp, #20 800f954: af00 add r7, sp, #0 800f956: 6078 str r0, [r7, #4] 800f958: 460b mov r3, r1 800f95a: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 800f95c: 687b ldr r3, [r7, #4] 800f95e: 689a ldr r2, [r3, #8] 800f960: 887b ldrh r3, [r7, #2] 800f962: 4013 ands r3, r2 800f964: 2b00 cmp r3, #0 800f966: d002 beq.n 800f96e { bitstatus = GPIO_PIN_SET; 800f968: 2301 movs r3, #1 800f96a: 73fb strb r3, [r7, #15] 800f96c: e001 b.n 800f972 } else { bitstatus = GPIO_PIN_RESET; 800f96e: 2300 movs r3, #0 800f970: 73fb strb r3, [r7, #15] } return bitstatus; 800f972: 7bfb ldrb r3, [r7, #15] } 800f974: 4618 mov r0, r3 800f976: 3714 adds r7, #20 800f978: 46bd mov sp, r7 800f97a: bc80 pop {r7} 800f97c: 4770 bx lr 0800f97e : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800f97e: b480 push {r7} 800f980: b083 sub sp, #12 800f982: af00 add r7, sp, #0 800f984: 6078 str r0, [r7, #4] 800f986: 460b mov r3, r1 800f988: 807b strh r3, [r7, #2] 800f98a: 4613 mov r3, r2 800f98c: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800f98e: 787b ldrb r3, [r7, #1] 800f990: 2b00 cmp r3, #0 800f992: d003 beq.n 800f99c { GPIOx->BSRR = GPIO_Pin; 800f994: 887a ldrh r2, [r7, #2] 800f996: 687b ldr r3, [r7, #4] 800f998: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 800f99a: e003 b.n 800f9a4 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 800f99c: 887b ldrh r3, [r7, #2] 800f99e: 041a lsls r2, r3, #16 800f9a0: 687b ldr r3, [r7, #4] 800f9a2: 611a str r2, [r3, #16] } 800f9a4: bf00 nop 800f9a6: 370c adds r7, #12 800f9a8: 46bd mov sp, r7 800f9aa: bc80 pop {r7} 800f9ac: 4770 bx lr ... 0800f9b0 : * @note If the HSE divided by 128 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 800f9b0: b480 push {r7} 800f9b2: af00 add r7, sp, #0 /* Enable access to RTC and backup registers */ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 800f9b4: 4b03 ldr r3, [pc, #12] @ (800f9c4 ) 800f9b6: 2201 movs r2, #1 800f9b8: 601a str r2, [r3, #0] } 800f9ba: bf00 nop 800f9bc: 46bd mov sp, r7 800f9be: bc80 pop {r7} 800f9c0: 4770 bx lr 800f9c2: bf00 nop 800f9c4: 420e0020 .word 0x420e0020 0800f9c8 : * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval HAL_StatusTypeDef */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { 800f9c8: b580 push {r7, lr} 800f9ca: b082 sub sp, #8 800f9cc: af00 add r7, sp, #0 uint32_t tickstart; /* Get Start Tick */ tickstart = HAL_GetTick(); 800f9ce: f7fd ffc5 bl 800d95c 800f9d2: 6078 str r0, [r7, #4] /* Set HSION bit */ SET_BIT(RCC->CR, RCC_CR_HSION); 800f9d4: 4b60 ldr r3, [pc, #384] @ (800fb58 ) 800f9d6: 681b ldr r3, [r3, #0] 800f9d8: 4a5f ldr r2, [pc, #380] @ (800fb58 ) 800f9da: f043 0301 orr.w r3, r3, #1 800f9de: 6013 str r3, [r2, #0] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 800f9e0: e008 b.n 800f9f4 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800f9e2: f7fd ffbb bl 800d95c 800f9e6: 4602 mov r2, r0 800f9e8: 687b ldr r3, [r7, #4] 800f9ea: 1ad3 subs r3, r2, r3 800f9ec: 2b02 cmp r3, #2 800f9ee: d901 bls.n 800f9f4 { return HAL_TIMEOUT; 800f9f0: 2303 movs r3, #3 800f9f2: e0ac b.n 800fb4e while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 800f9f4: 4b58 ldr r3, [pc, #352] @ (800fb58 ) 800f9f6: 681b ldr r3, [r3, #0] 800f9f8: f003 0302 and.w r3, r3, #2 800f9fc: 2b00 cmp r3, #0 800f9fe: d0f0 beq.n 800f9e2 } } /* Set HSITRIM bits to the reset value */ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); 800fa00: 4b55 ldr r3, [pc, #340] @ (800fb58 ) 800fa02: 681b ldr r3, [r3, #0] 800fa04: f023 03f8 bic.w r3, r3, #248 @ 0xf8 800fa08: 4a53 ldr r2, [pc, #332] @ (800fb58 ) 800fa0a: f043 0380 orr.w r3, r3, #128 @ 0x80 800fa0e: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800fa10: f7fd ffa4 bl 800d95c 800fa14: 6078 str r0, [r7, #4] /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); 800fa16: 4b50 ldr r3, [pc, #320] @ (800fb58 ) 800fa18: 2200 movs r2, #0 800fa1a: 605a str r2, [r3, #4] /* Wait till clock switch is ready */ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 800fa1c: e00a b.n 800fa34 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800fa1e: f7fd ff9d bl 800d95c 800fa22: 4602 mov r2, r0 800fa24: 687b ldr r3, [r7, #4] 800fa26: 1ad3 subs r3, r2, r3 800fa28: f241 3288 movw r2, #5000 @ 0x1388 800fa2c: 4293 cmp r3, r2 800fa2e: d901 bls.n 800fa34 { return HAL_TIMEOUT; 800fa30: 2303 movs r3, #3 800fa32: e08c b.n 800fb4e while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 800fa34: 4b48 ldr r3, [pc, #288] @ (800fb58 ) 800fa36: 685b ldr r3, [r3, #4] 800fa38: f003 030c and.w r3, r3, #12 800fa3c: 2b00 cmp r3, #0 800fa3e: d1ee bne.n 800fa1e } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; 800fa40: 4b46 ldr r3, [pc, #280] @ (800fb5c ) 800fa42: 4a47 ldr r2, [pc, #284] @ (800fb60 ) 800fa44: 601a str r2, [r3, #0] /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 800fa46: 4b47 ldr r3, [pc, #284] @ (800fb64 ) 800fa48: 681b ldr r3, [r3, #0] 800fa4a: 4618 mov r0, r3 800fa4c: f7fd ff44 bl 800d8d8 800fa50: 4603 mov r3, r0 800fa52: 2b00 cmp r3, #0 800fa54: d001 beq.n 800fa5a { return HAL_ERROR; 800fa56: 2301 movs r3, #1 800fa58: e079 b.n 800fb4e } /* Get Start Tick */ tickstart = HAL_GetTick(); 800fa5a: f7fd ff7f bl 800d95c 800fa5e: 6078 str r0, [r7, #4] /* Second step is to clear PLLON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 800fa60: 4b3d ldr r3, [pc, #244] @ (800fb58 ) 800fa62: 681b ldr r3, [r3, #0] 800fa64: 4a3c ldr r2, [pc, #240] @ (800fb58 ) 800fa66: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800fa6a: 6013 str r3, [r2, #0] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 800fa6c: e008 b.n 800fa80 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800fa6e: f7fd ff75 bl 800d95c 800fa72: 4602 mov r2, r0 800fa74: 687b ldr r3, [r7, #4] 800fa76: 1ad3 subs r3, r2, r3 800fa78: 2b02 cmp r3, #2 800fa7a: d901 bls.n 800fa80 { return HAL_TIMEOUT; 800fa7c: 2303 movs r3, #3 800fa7e: e066 b.n 800fb4e while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 800fa80: 4b35 ldr r3, [pc, #212] @ (800fb58 ) 800fa82: 681b ldr r3, [r3, #0] 800fa84: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800fa88: 2b00 cmp r3, #0 800fa8a: d1f0 bne.n 800fa6e } } /* Ensure to reset PLLSRC and PLLMUL bits */ CLEAR_REG(RCC->CFGR); 800fa8c: 4b32 ldr r3, [pc, #200] @ (800fb58 ) 800fa8e: 2200 movs r2, #0 800fa90: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 800fa92: f7fd ff63 bl 800d95c 800fa96: 6078 str r0, [r7, #4] /* Reset HSEON & CSSON bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON); 800fa98: 4b2f ldr r3, [pc, #188] @ (800fb58 ) 800fa9a: 681b ldr r3, [r3, #0] 800fa9c: 4a2e ldr r2, [pc, #184] @ (800fb58 ) 800fa9e: f423 2310 bic.w r3, r3, #589824 @ 0x90000 800faa2: 6013 str r3, [r2, #0] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 800faa4: e008 b.n 800fab8 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800faa6: f7fd ff59 bl 800d95c 800faaa: 4602 mov r2, r0 800faac: 687b ldr r3, [r7, #4] 800faae: 1ad3 subs r3, r2, r3 800fab0: 2b64 cmp r3, #100 @ 0x64 800fab2: d901 bls.n 800fab8 { return HAL_TIMEOUT; 800fab4: 2303 movs r3, #3 800fab6: e04a b.n 800fb4e while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 800fab8: 4b27 ldr r3, [pc, #156] @ (800fb58 ) 800faba: 681b ldr r3, [r3, #0] 800fabc: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fac0: 2b00 cmp r3, #0 800fac2: d1f0 bne.n 800faa6 } } /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 800fac4: 4b24 ldr r3, [pc, #144] @ (800fb58 ) 800fac6: 681b ldr r3, [r3, #0] 800fac8: 4a23 ldr r2, [pc, #140] @ (800fb58 ) 800faca: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800face: 6013 str r3, [r2, #0] #if defined(RCC_PLL2_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 800fad0: f7fd ff44 bl 800d95c 800fad4: 6078 str r0, [r7, #4] /* Clear PLL2ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); 800fad6: 4b20 ldr r3, [pc, #128] @ (800fb58 ) 800fad8: 681b ldr r3, [r3, #0] 800fada: 4a1f ldr r2, [pc, #124] @ (800fb58 ) 800fadc: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800fae0: 6013 str r3, [r2, #0] /* Wait till PLL2 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 800fae2: e008 b.n 800faf6 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800fae4: f7fd ff3a bl 800d95c 800fae8: 4602 mov r2, r0 800faea: 687b ldr r3, [r7, #4] 800faec: 1ad3 subs r3, r2, r3 800faee: 2b64 cmp r3, #100 @ 0x64 800faf0: d901 bls.n 800faf6 { return HAL_TIMEOUT; 800faf2: 2303 movs r3, #3 800faf4: e02b b.n 800fb4e while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 800faf6: 4b18 ldr r3, [pc, #96] @ (800fb58 ) 800faf8: 681b ldr r3, [r3, #0] 800fafa: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800fafe: 2b00 cmp r3, #0 800fb00: d1f0 bne.n 800fae4 } #endif /* RCC_PLL2_SUPPORT */ #if defined(RCC_PLLI2S_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 800fb02: f7fd ff2b bl 800d95c 800fb06: 6078 str r0, [r7, #4] /* Clear PLL3ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); 800fb08: 4b13 ldr r3, [pc, #76] @ (800fb58 ) 800fb0a: 681b ldr r3, [r3, #0] 800fb0c: 4a12 ldr r2, [pc, #72] @ (800fb58 ) 800fb0e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800fb12: 6013 str r3, [r2, #0] /* Wait till PLL3 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 800fb14: e008 b.n 800fb28 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 800fb16: f7fd ff21 bl 800d95c 800fb1a: 4602 mov r2, r0 800fb1c: 687b ldr r3, [r7, #4] 800fb1e: 1ad3 subs r3, r2, r3 800fb20: 2b64 cmp r3, #100 @ 0x64 800fb22: d901 bls.n 800fb28 { return HAL_TIMEOUT; 800fb24: 2303 movs r3, #3 800fb26: e012 b.n 800fb4e while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 800fb28: 4b0b ldr r3, [pc, #44] @ (800fb58 ) 800fb2a: 681b ldr r3, [r3, #0] 800fb2c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800fb30: 2b00 cmp r3, #0 800fb32: d1f0 bne.n 800fb16 } #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_CFGR2_PREDIV1) /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); 800fb34: 4b08 ldr r3, [pc, #32] @ (800fb58 ) 800fb36: 2200 movs r2, #0 800fb38: 62da str r2, [r3, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1 */ /* Reset all CSR flags */ SET_BIT(RCC->CSR, RCC_CSR_RMVF); 800fb3a: 4b07 ldr r3, [pc, #28] @ (800fb58 ) 800fb3c: 6a5b ldr r3, [r3, #36] @ 0x24 800fb3e: 4a06 ldr r2, [pc, #24] @ (800fb58 ) 800fb40: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800fb44: 6253 str r3, [r2, #36] @ 0x24 /* Disable all interrupts */ CLEAR_REG(RCC->CIR); 800fb46: 4b04 ldr r3, [pc, #16] @ (800fb58 ) 800fb48: 2200 movs r2, #0 800fb4a: 609a str r2, [r3, #8] return HAL_OK; 800fb4c: 2300 movs r3, #0 } 800fb4e: 4618 mov r0, r3 800fb50: 3708 adds r7, #8 800fb52: 46bd mov sp, r7 800fb54: bd80 pop {r7, pc} 800fb56: bf00 nop 800fb58: 40021000 .word 0x40021000 800fb5c: 2000006c .word 0x2000006c 800fb60: 007a1200 .word 0x007a1200 800fb64: 20000070 .word 0x20000070 0800fb68 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800fb68: b580 push {r7, lr} 800fb6a: b086 sub sp, #24 800fb6c: af00 add r7, sp, #0 800fb6e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 800fb70: 687b ldr r3, [r7, #4] 800fb72: 2b00 cmp r3, #0 800fb74: d101 bne.n 800fb7a { return HAL_ERROR; 800fb76: 2301 movs r3, #1 800fb78: e304 b.n 8010184 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800fb7a: 687b ldr r3, [r7, #4] 800fb7c: 681b ldr r3, [r3, #0] 800fb7e: f003 0301 and.w r3, r3, #1 800fb82: 2b00 cmp r3, #0 800fb84: f000 8087 beq.w 800fc96 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 800fb88: 4b92 ldr r3, [pc, #584] @ (800fdd4 ) 800fb8a: 685b ldr r3, [r3, #4] 800fb8c: f003 030c and.w r3, r3, #12 800fb90: 2b04 cmp r3, #4 800fb92: d00c beq.n 800fbae || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 800fb94: 4b8f ldr r3, [pc, #572] @ (800fdd4 ) 800fb96: 685b ldr r3, [r3, #4] 800fb98: f003 030c and.w r3, r3, #12 800fb9c: 2b08 cmp r3, #8 800fb9e: d112 bne.n 800fbc6 800fba0: 4b8c ldr r3, [pc, #560] @ (800fdd4 ) 800fba2: 685b ldr r3, [r3, #4] 800fba4: f403 3380 and.w r3, r3, #65536 @ 0x10000 800fba8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800fbac: d10b bne.n 800fbc6 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800fbae: 4b89 ldr r3, [pc, #548] @ (800fdd4 ) 800fbb0: 681b ldr r3, [r3, #0] 800fbb2: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fbb6: 2b00 cmp r3, #0 800fbb8: d06c beq.n 800fc94 800fbba: 687b ldr r3, [r7, #4] 800fbbc: 689b ldr r3, [r3, #8] 800fbbe: 2b00 cmp r3, #0 800fbc0: d168 bne.n 800fc94 { return HAL_ERROR; 800fbc2: 2301 movs r3, #1 800fbc4: e2de b.n 8010184 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800fbc6: 687b ldr r3, [r7, #4] 800fbc8: 689b ldr r3, [r3, #8] 800fbca: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800fbce: d106 bne.n 800fbde 800fbd0: 4b80 ldr r3, [pc, #512] @ (800fdd4 ) 800fbd2: 681b ldr r3, [r3, #0] 800fbd4: 4a7f ldr r2, [pc, #508] @ (800fdd4 ) 800fbd6: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800fbda: 6013 str r3, [r2, #0] 800fbdc: e02e b.n 800fc3c 800fbde: 687b ldr r3, [r7, #4] 800fbe0: 689b ldr r3, [r3, #8] 800fbe2: 2b00 cmp r3, #0 800fbe4: d10c bne.n 800fc00 800fbe6: 4b7b ldr r3, [pc, #492] @ (800fdd4 ) 800fbe8: 681b ldr r3, [r3, #0] 800fbea: 4a7a ldr r2, [pc, #488] @ (800fdd4 ) 800fbec: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800fbf0: 6013 str r3, [r2, #0] 800fbf2: 4b78 ldr r3, [pc, #480] @ (800fdd4 ) 800fbf4: 681b ldr r3, [r3, #0] 800fbf6: 4a77 ldr r2, [pc, #476] @ (800fdd4 ) 800fbf8: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800fbfc: 6013 str r3, [r2, #0] 800fbfe: e01d b.n 800fc3c 800fc00: 687b ldr r3, [r7, #4] 800fc02: 689b ldr r3, [r3, #8] 800fc04: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800fc08: d10c bne.n 800fc24 800fc0a: 4b72 ldr r3, [pc, #456] @ (800fdd4 ) 800fc0c: 681b ldr r3, [r3, #0] 800fc0e: 4a71 ldr r2, [pc, #452] @ (800fdd4 ) 800fc10: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800fc14: 6013 str r3, [r2, #0] 800fc16: 4b6f ldr r3, [pc, #444] @ (800fdd4 ) 800fc18: 681b ldr r3, [r3, #0] 800fc1a: 4a6e ldr r2, [pc, #440] @ (800fdd4 ) 800fc1c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800fc20: 6013 str r3, [r2, #0] 800fc22: e00b b.n 800fc3c 800fc24: 4b6b ldr r3, [pc, #428] @ (800fdd4 ) 800fc26: 681b ldr r3, [r3, #0] 800fc28: 4a6a ldr r2, [pc, #424] @ (800fdd4 ) 800fc2a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800fc2e: 6013 str r3, [r2, #0] 800fc30: 4b68 ldr r3, [pc, #416] @ (800fdd4 ) 800fc32: 681b ldr r3, [r3, #0] 800fc34: 4a67 ldr r2, [pc, #412] @ (800fdd4 ) 800fc36: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800fc3a: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 800fc3c: 687b ldr r3, [r7, #4] 800fc3e: 689b ldr r3, [r3, #8] 800fc40: 2b00 cmp r3, #0 800fc42: d013 beq.n 800fc6c { /* Get Start Tick */ tickstart = HAL_GetTick(); 800fc44: f7fd fe8a bl 800d95c 800fc48: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800fc4a: e008 b.n 800fc5e { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800fc4c: f7fd fe86 bl 800d95c 800fc50: 4602 mov r2, r0 800fc52: 693b ldr r3, [r7, #16] 800fc54: 1ad3 subs r3, r2, r3 800fc56: 2b64 cmp r3, #100 @ 0x64 800fc58: d901 bls.n 800fc5e { return HAL_TIMEOUT; 800fc5a: 2303 movs r3, #3 800fc5c: e292 b.n 8010184 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800fc5e: 4b5d ldr r3, [pc, #372] @ (800fdd4 ) 800fc60: 681b ldr r3, [r3, #0] 800fc62: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fc66: 2b00 cmp r3, #0 800fc68: d0f0 beq.n 800fc4c 800fc6a: e014 b.n 800fc96 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 800fc6c: f7fd fe76 bl 800d95c 800fc70: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800fc72: e008 b.n 800fc86 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800fc74: f7fd fe72 bl 800d95c 800fc78: 4602 mov r2, r0 800fc7a: 693b ldr r3, [r7, #16] 800fc7c: 1ad3 subs r3, r2, r3 800fc7e: 2b64 cmp r3, #100 @ 0x64 800fc80: d901 bls.n 800fc86 { return HAL_TIMEOUT; 800fc82: 2303 movs r3, #3 800fc84: e27e b.n 8010184 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800fc86: 4b53 ldr r3, [pc, #332] @ (800fdd4 ) 800fc88: 681b ldr r3, [r3, #0] 800fc8a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fc8e: 2b00 cmp r3, #0 800fc90: d1f0 bne.n 800fc74 800fc92: e000 b.n 800fc96 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800fc94: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800fc96: 687b ldr r3, [r7, #4] 800fc98: 681b ldr r3, [r3, #0] 800fc9a: f003 0302 and.w r3, r3, #2 800fc9e: 2b00 cmp r3, #0 800fca0: d063 beq.n 800fd6a /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 800fca2: 4b4c ldr r3, [pc, #304] @ (800fdd4 ) 800fca4: 685b ldr r3, [r3, #4] 800fca6: f003 030c and.w r3, r3, #12 800fcaa: 2b00 cmp r3, #0 800fcac: d00b beq.n 800fcc6 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 800fcae: 4b49 ldr r3, [pc, #292] @ (800fdd4 ) 800fcb0: 685b ldr r3, [r3, #4] 800fcb2: f003 030c and.w r3, r3, #12 800fcb6: 2b08 cmp r3, #8 800fcb8: d11c bne.n 800fcf4 800fcba: 4b46 ldr r3, [pc, #280] @ (800fdd4 ) 800fcbc: 685b ldr r3, [r3, #4] 800fcbe: f403 3380 and.w r3, r3, #65536 @ 0x10000 800fcc2: 2b00 cmp r3, #0 800fcc4: d116 bne.n 800fcf4 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800fcc6: 4b43 ldr r3, [pc, #268] @ (800fdd4 ) 800fcc8: 681b ldr r3, [r3, #0] 800fcca: f003 0302 and.w r3, r3, #2 800fcce: 2b00 cmp r3, #0 800fcd0: d005 beq.n 800fcde 800fcd2: 687b ldr r3, [r7, #4] 800fcd4: 695b ldr r3, [r3, #20] 800fcd6: 2b01 cmp r3, #1 800fcd8: d001 beq.n 800fcde { return HAL_ERROR; 800fcda: 2301 movs r3, #1 800fcdc: e252 b.n 8010184 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800fcde: 4b3d ldr r3, [pc, #244] @ (800fdd4 ) 800fce0: 681b ldr r3, [r3, #0] 800fce2: f023 02f8 bic.w r2, r3, #248 @ 0xf8 800fce6: 687b ldr r3, [r7, #4] 800fce8: 699b ldr r3, [r3, #24] 800fcea: 00db lsls r3, r3, #3 800fcec: 4939 ldr r1, [pc, #228] @ (800fdd4 ) 800fcee: 4313 orrs r3, r2 800fcf0: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800fcf2: e03a b.n 800fd6a } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 800fcf4: 687b ldr r3, [r7, #4] 800fcf6: 695b ldr r3, [r3, #20] 800fcf8: 2b00 cmp r3, #0 800fcfa: d020 beq.n 800fd3e { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 800fcfc: 4b36 ldr r3, [pc, #216] @ (800fdd8 ) 800fcfe: 2201 movs r2, #1 800fd00: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800fd02: f7fd fe2b bl 800d95c 800fd06: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800fd08: e008 b.n 800fd1c { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800fd0a: f7fd fe27 bl 800d95c 800fd0e: 4602 mov r2, r0 800fd10: 693b ldr r3, [r7, #16] 800fd12: 1ad3 subs r3, r2, r3 800fd14: 2b02 cmp r3, #2 800fd16: d901 bls.n 800fd1c { return HAL_TIMEOUT; 800fd18: 2303 movs r3, #3 800fd1a: e233 b.n 8010184 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800fd1c: 4b2d ldr r3, [pc, #180] @ (800fdd4 ) 800fd1e: 681b ldr r3, [r3, #0] 800fd20: f003 0302 and.w r3, r3, #2 800fd24: 2b00 cmp r3, #0 800fd26: d0f0 beq.n 800fd0a } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800fd28: 4b2a ldr r3, [pc, #168] @ (800fdd4 ) 800fd2a: 681b ldr r3, [r3, #0] 800fd2c: f023 02f8 bic.w r2, r3, #248 @ 0xf8 800fd30: 687b ldr r3, [r7, #4] 800fd32: 699b ldr r3, [r3, #24] 800fd34: 00db lsls r3, r3, #3 800fd36: 4927 ldr r1, [pc, #156] @ (800fdd4 ) 800fd38: 4313 orrs r3, r2 800fd3a: 600b str r3, [r1, #0] 800fd3c: e015 b.n 800fd6a } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800fd3e: 4b26 ldr r3, [pc, #152] @ (800fdd8 ) 800fd40: 2200 movs r2, #0 800fd42: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800fd44: f7fd fe0a bl 800d95c 800fd48: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800fd4a: e008 b.n 800fd5e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800fd4c: f7fd fe06 bl 800d95c 800fd50: 4602 mov r2, r0 800fd52: 693b ldr r3, [r7, #16] 800fd54: 1ad3 subs r3, r2, r3 800fd56: 2b02 cmp r3, #2 800fd58: d901 bls.n 800fd5e { return HAL_TIMEOUT; 800fd5a: 2303 movs r3, #3 800fd5c: e212 b.n 8010184 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800fd5e: 4b1d ldr r3, [pc, #116] @ (800fdd4 ) 800fd60: 681b ldr r3, [r3, #0] 800fd62: f003 0302 and.w r3, r3, #2 800fd66: 2b00 cmp r3, #0 800fd68: d1f0 bne.n 800fd4c } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800fd6a: 687b ldr r3, [r7, #4] 800fd6c: 681b ldr r3, [r3, #0] 800fd6e: f003 0308 and.w r3, r3, #8 800fd72: 2b00 cmp r3, #0 800fd74: d03a beq.n 800fdec { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 800fd76: 687b ldr r3, [r7, #4] 800fd78: 69db ldr r3, [r3, #28] 800fd7a: 2b00 cmp r3, #0 800fd7c: d019 beq.n 800fdb2 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800fd7e: 4b17 ldr r3, [pc, #92] @ (800fddc ) 800fd80: 2201 movs r2, #1 800fd82: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800fd84: f7fd fdea bl 800d95c 800fd88: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800fd8a: e008 b.n 800fd9e { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800fd8c: f7fd fde6 bl 800d95c 800fd90: 4602 mov r2, r0 800fd92: 693b ldr r3, [r7, #16] 800fd94: 1ad3 subs r3, r2, r3 800fd96: 2b02 cmp r3, #2 800fd98: d901 bls.n 800fd9e { return HAL_TIMEOUT; 800fd9a: 2303 movs r3, #3 800fd9c: e1f2 b.n 8010184 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800fd9e: 4b0d ldr r3, [pc, #52] @ (800fdd4 ) 800fda0: 6a5b ldr r3, [r3, #36] @ 0x24 800fda2: f003 0302 and.w r3, r3, #2 800fda6: 2b00 cmp r3, #0 800fda8: d0f0 beq.n 800fd8c } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 800fdaa: 2001 movs r0, #1 800fdac: f000 fbca bl 8010544 800fdb0: e01c b.n 800fdec } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800fdb2: 4b0a ldr r3, [pc, #40] @ (800fddc ) 800fdb4: 2200 movs r2, #0 800fdb6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800fdb8: f7fd fdd0 bl 800d95c 800fdbc: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800fdbe: e00f b.n 800fde0 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800fdc0: f7fd fdcc bl 800d95c 800fdc4: 4602 mov r2, r0 800fdc6: 693b ldr r3, [r7, #16] 800fdc8: 1ad3 subs r3, r2, r3 800fdca: 2b02 cmp r3, #2 800fdcc: d908 bls.n 800fde0 { return HAL_TIMEOUT; 800fdce: 2303 movs r3, #3 800fdd0: e1d8 b.n 8010184 800fdd2: bf00 nop 800fdd4: 40021000 .word 0x40021000 800fdd8: 42420000 .word 0x42420000 800fddc: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800fde0: 4b9b ldr r3, [pc, #620] @ (8010050 ) 800fde2: 6a5b ldr r3, [r3, #36] @ 0x24 800fde4: f003 0302 and.w r3, r3, #2 800fde8: 2b00 cmp r3, #0 800fdea: d1e9 bne.n 800fdc0 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800fdec: 687b ldr r3, [r7, #4] 800fdee: 681b ldr r3, [r3, #0] 800fdf0: f003 0304 and.w r3, r3, #4 800fdf4: 2b00 cmp r3, #0 800fdf6: f000 80a6 beq.w 800ff46 { FlagStatus pwrclkchanged = RESET; 800fdfa: 2300 movs r3, #0 800fdfc: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 800fdfe: 4b94 ldr r3, [pc, #592] @ (8010050 ) 800fe00: 69db ldr r3, [r3, #28] 800fe02: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800fe06: 2b00 cmp r3, #0 800fe08: d10d bne.n 800fe26 { __HAL_RCC_PWR_CLK_ENABLE(); 800fe0a: 4b91 ldr r3, [pc, #580] @ (8010050 ) 800fe0c: 69db ldr r3, [r3, #28] 800fe0e: 4a90 ldr r2, [pc, #576] @ (8010050 ) 800fe10: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800fe14: 61d3 str r3, [r2, #28] 800fe16: 4b8e ldr r3, [pc, #568] @ (8010050 ) 800fe18: 69db ldr r3, [r3, #28] 800fe1a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800fe1e: 60bb str r3, [r7, #8] 800fe20: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 800fe22: 2301 movs r3, #1 800fe24: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800fe26: 4b8b ldr r3, [pc, #556] @ (8010054 ) 800fe28: 681b ldr r3, [r3, #0] 800fe2a: f403 7380 and.w r3, r3, #256 @ 0x100 800fe2e: 2b00 cmp r3, #0 800fe30: d118 bne.n 800fe64 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 800fe32: 4b88 ldr r3, [pc, #544] @ (8010054 ) 800fe34: 681b ldr r3, [r3, #0] 800fe36: 4a87 ldr r2, [pc, #540] @ (8010054 ) 800fe38: f443 7380 orr.w r3, r3, #256 @ 0x100 800fe3c: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800fe3e: f7fd fd8d bl 800d95c 800fe42: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800fe44: e008 b.n 800fe58 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800fe46: f7fd fd89 bl 800d95c 800fe4a: 4602 mov r2, r0 800fe4c: 693b ldr r3, [r7, #16] 800fe4e: 1ad3 subs r3, r2, r3 800fe50: 2b64 cmp r3, #100 @ 0x64 800fe52: d901 bls.n 800fe58 { return HAL_TIMEOUT; 800fe54: 2303 movs r3, #3 800fe56: e195 b.n 8010184 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800fe58: 4b7e ldr r3, [pc, #504] @ (8010054 ) 800fe5a: 681b ldr r3, [r3, #0] 800fe5c: f403 7380 and.w r3, r3, #256 @ 0x100 800fe60: 2b00 cmp r3, #0 800fe62: d0f0 beq.n 800fe46 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800fe64: 687b ldr r3, [r7, #4] 800fe66: 691b ldr r3, [r3, #16] 800fe68: 2b01 cmp r3, #1 800fe6a: d106 bne.n 800fe7a 800fe6c: 4b78 ldr r3, [pc, #480] @ (8010050 ) 800fe6e: 6a1b ldr r3, [r3, #32] 800fe70: 4a77 ldr r2, [pc, #476] @ (8010050 ) 800fe72: f043 0301 orr.w r3, r3, #1 800fe76: 6213 str r3, [r2, #32] 800fe78: e02d b.n 800fed6 800fe7a: 687b ldr r3, [r7, #4] 800fe7c: 691b ldr r3, [r3, #16] 800fe7e: 2b00 cmp r3, #0 800fe80: d10c bne.n 800fe9c 800fe82: 4b73 ldr r3, [pc, #460] @ (8010050 ) 800fe84: 6a1b ldr r3, [r3, #32] 800fe86: 4a72 ldr r2, [pc, #456] @ (8010050 ) 800fe88: f023 0301 bic.w r3, r3, #1 800fe8c: 6213 str r3, [r2, #32] 800fe8e: 4b70 ldr r3, [pc, #448] @ (8010050 ) 800fe90: 6a1b ldr r3, [r3, #32] 800fe92: 4a6f ldr r2, [pc, #444] @ (8010050 ) 800fe94: f023 0304 bic.w r3, r3, #4 800fe98: 6213 str r3, [r2, #32] 800fe9a: e01c b.n 800fed6 800fe9c: 687b ldr r3, [r7, #4] 800fe9e: 691b ldr r3, [r3, #16] 800fea0: 2b05 cmp r3, #5 800fea2: d10c bne.n 800febe 800fea4: 4b6a ldr r3, [pc, #424] @ (8010050 ) 800fea6: 6a1b ldr r3, [r3, #32] 800fea8: 4a69 ldr r2, [pc, #420] @ (8010050 ) 800feaa: f043 0304 orr.w r3, r3, #4 800feae: 6213 str r3, [r2, #32] 800feb0: 4b67 ldr r3, [pc, #412] @ (8010050 ) 800feb2: 6a1b ldr r3, [r3, #32] 800feb4: 4a66 ldr r2, [pc, #408] @ (8010050 ) 800feb6: f043 0301 orr.w r3, r3, #1 800feba: 6213 str r3, [r2, #32] 800febc: e00b b.n 800fed6 800febe: 4b64 ldr r3, [pc, #400] @ (8010050 ) 800fec0: 6a1b ldr r3, [r3, #32] 800fec2: 4a63 ldr r2, [pc, #396] @ (8010050 ) 800fec4: f023 0301 bic.w r3, r3, #1 800fec8: 6213 str r3, [r2, #32] 800feca: 4b61 ldr r3, [pc, #388] @ (8010050 ) 800fecc: 6a1b ldr r3, [r3, #32] 800fece: 4a60 ldr r2, [pc, #384] @ (8010050 ) 800fed0: f023 0304 bic.w r3, r3, #4 800fed4: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 800fed6: 687b ldr r3, [r7, #4] 800fed8: 691b ldr r3, [r3, #16] 800feda: 2b00 cmp r3, #0 800fedc: d015 beq.n 800ff0a { /* Get Start Tick */ tickstart = HAL_GetTick(); 800fede: f7fd fd3d bl 800d95c 800fee2: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800fee4: e00a b.n 800fefc { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800fee6: f7fd fd39 bl 800d95c 800feea: 4602 mov r2, r0 800feec: 693b ldr r3, [r7, #16] 800feee: 1ad3 subs r3, r2, r3 800fef0: f241 3288 movw r2, #5000 @ 0x1388 800fef4: 4293 cmp r3, r2 800fef6: d901 bls.n 800fefc { return HAL_TIMEOUT; 800fef8: 2303 movs r3, #3 800fefa: e143 b.n 8010184 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800fefc: 4b54 ldr r3, [pc, #336] @ (8010050 ) 800fefe: 6a1b ldr r3, [r3, #32] 800ff00: f003 0302 and.w r3, r3, #2 800ff04: 2b00 cmp r3, #0 800ff06: d0ee beq.n 800fee6 800ff08: e014 b.n 800ff34 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 800ff0a: f7fd fd27 bl 800d95c 800ff0e: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 800ff10: e00a b.n 800ff28 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800ff12: f7fd fd23 bl 800d95c 800ff16: 4602 mov r2, r0 800ff18: 693b ldr r3, [r7, #16] 800ff1a: 1ad3 subs r3, r2, r3 800ff1c: f241 3288 movw r2, #5000 @ 0x1388 800ff20: 4293 cmp r3, r2 800ff22: d901 bls.n 800ff28 { return HAL_TIMEOUT; 800ff24: 2303 movs r3, #3 800ff26: e12d b.n 8010184 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 800ff28: 4b49 ldr r3, [pc, #292] @ (8010050 ) 800ff2a: 6a1b ldr r3, [r3, #32] 800ff2c: f003 0302 and.w r3, r3, #2 800ff30: 2b00 cmp r3, #0 800ff32: d1ee bne.n 800ff12 } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 800ff34: 7dfb ldrb r3, [r7, #23] 800ff36: 2b01 cmp r3, #1 800ff38: d105 bne.n 800ff46 { __HAL_RCC_PWR_CLK_DISABLE(); 800ff3a: 4b45 ldr r3, [pc, #276] @ (8010050 ) 800ff3c: 69db ldr r3, [r3, #28] 800ff3e: 4a44 ldr r2, [pc, #272] @ (8010050 ) 800ff40: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800ff44: 61d3 str r3, [r2, #28] #if defined(RCC_CR_PLL2ON) /*-------------------------------- PLL2 Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) 800ff46: 687b ldr r3, [r7, #4] 800ff48: 6adb ldr r3, [r3, #44] @ 0x2c 800ff4a: 2b00 cmp r3, #0 800ff4c: f000 808c beq.w 8010068 { /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 800ff50: 4b3f ldr r3, [pc, #252] @ (8010050 ) 800ff52: 685b ldr r3, [r3, #4] 800ff54: f403 3380 and.w r3, r3, #65536 @ 0x10000 800ff58: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800ff5c: d10e bne.n 800ff7c (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 800ff5e: 4b3c ldr r3, [pc, #240] @ (8010050 ) 800ff60: 685b ldr r3, [r3, #4] 800ff62: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 800ff66: 2b08 cmp r3, #8 800ff68: d108 bne.n 800ff7c ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) 800ff6a: 4b39 ldr r3, [pc, #228] @ (8010050 ) 800ff6c: 6adb ldr r3, [r3, #44] @ 0x2c 800ff6e: f403 3380 and.w r3, r3, #65536 @ 0x10000 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 800ff72: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800ff76: d101 bne.n 800ff7c { return HAL_ERROR; 800ff78: 2301 movs r3, #1 800ff7a: e103 b.n 8010184 } else { if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) 800ff7c: 687b ldr r3, [r7, #4] 800ff7e: 6adb ldr r3, [r3, #44] @ 0x2c 800ff80: 2b02 cmp r3, #2 800ff82: d14e bne.n 8010022 assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); /* Prediv2 can be written only when the PLLI2S is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 800ff84: 4b32 ldr r3, [pc, #200] @ (8010050 ) 800ff86: 681b ldr r3, [r3, #0] 800ff88: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800ff8c: 2b00 cmp r3, #0 800ff8e: d009 beq.n 800ffa4 (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) 800ff90: 4b2f ldr r3, [pc, #188] @ (8010050 ) 800ff92: 6adb ldr r3, [r3, #44] @ 0x2c 800ff94: f003 02f0 and.w r2, r3, #240 @ 0xf0 800ff98: 687b ldr r3, [r7, #4] 800ff9a: 6b5b ldr r3, [r3, #52] @ 0x34 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 800ff9c: 429a cmp r2, r3 800ff9e: d001 beq.n 800ffa4 { return HAL_ERROR; 800ffa0: 2301 movs r3, #1 800ffa2: e0ef b.n 8010184 } /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 800ffa4: 4b2c ldr r3, [pc, #176] @ (8010058 ) 800ffa6: 2200 movs r2, #0 800ffa8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800ffaa: f7fd fcd7 bl 800d95c 800ffae: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 800ffb0: e008 b.n 800ffc4 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800ffb2: f7fd fcd3 bl 800d95c 800ffb6: 4602 mov r2, r0 800ffb8: 693b ldr r3, [r7, #16] 800ffba: 1ad3 subs r3, r2, r3 800ffbc: 2b64 cmp r3, #100 @ 0x64 800ffbe: d901 bls.n 800ffc4 { return HAL_TIMEOUT; 800ffc0: 2303 movs r3, #3 800ffc2: e0df b.n 8010184 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 800ffc4: 4b22 ldr r3, [pc, #136] @ (8010050 ) 800ffc6: 681b ldr r3, [r3, #0] 800ffc8: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800ffcc: 2b00 cmp r3, #0 800ffce: d1f0 bne.n 800ffb2 } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); 800ffd0: 4b1f ldr r3, [pc, #124] @ (8010050 ) 800ffd2: 6adb ldr r3, [r3, #44] @ 0x2c 800ffd4: f023 02f0 bic.w r2, r3, #240 @ 0xf0 800ffd8: 687b ldr r3, [r7, #4] 800ffda: 6b5b ldr r3, [r3, #52] @ 0x34 800ffdc: 491c ldr r1, [pc, #112] @ (8010050 ) 800ffde: 4313 orrs r3, r2 800ffe0: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); 800ffe2: 4b1b ldr r3, [pc, #108] @ (8010050 ) 800ffe4: 6adb ldr r3, [r3, #44] @ 0x2c 800ffe6: f423 6270 bic.w r2, r3, #3840 @ 0xf00 800ffea: 687b ldr r3, [r7, #4] 800ffec: 6b1b ldr r3, [r3, #48] @ 0x30 800ffee: 4918 ldr r1, [pc, #96] @ (8010050 ) 800fff0: 4313 orrs r3, r2 800fff2: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); 800fff4: 4b18 ldr r3, [pc, #96] @ (8010058 ) 800fff6: 2201 movs r2, #1 800fff8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800fffa: f7fd fcaf bl 800d95c 800fffe: 6138 str r0, [r7, #16] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8010000: e008 b.n 8010014 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8010002: f7fd fcab bl 800d95c 8010006: 4602 mov r2, r0 8010008: 693b ldr r3, [r7, #16] 801000a: 1ad3 subs r3, r2, r3 801000c: 2b64 cmp r3, #100 @ 0x64 801000e: d901 bls.n 8010014 { return HAL_TIMEOUT; 8010010: 2303 movs r3, #3 8010012: e0b7 b.n 8010184 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8010014: 4b0e ldr r3, [pc, #56] @ (8010050 ) 8010016: 681b ldr r3, [r3, #0] 8010018: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 801001c: 2b00 cmp r3, #0 801001e: d0f0 beq.n 8010002 8010020: e022 b.n 8010068 } } else { /* Set PREDIV1 source to HSE */ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); 8010022: 4b0b ldr r3, [pc, #44] @ (8010050 ) 8010024: 6adb ldr r3, [r3, #44] @ 0x2c 8010026: 4a0a ldr r2, [pc, #40] @ (8010050 ) 8010028: f423 3380 bic.w r3, r3, #65536 @ 0x10000 801002c: 62d3 str r3, [r2, #44] @ 0x2c /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 801002e: 4b0a ldr r3, [pc, #40] @ (8010058 ) 8010030: 2200 movs r2, #0 8010032: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010034: f7fd fc92 bl 800d95c 8010038: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 801003a: e00f b.n 801005c { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 801003c: f7fd fc8e bl 800d95c 8010040: 4602 mov r2, r0 8010042: 693b ldr r3, [r7, #16] 8010044: 1ad3 subs r3, r2, r3 8010046: 2b64 cmp r3, #100 @ 0x64 8010048: d908 bls.n 801005c { return HAL_TIMEOUT; 801004a: 2303 movs r3, #3 801004c: e09a b.n 8010184 801004e: bf00 nop 8010050: 40021000 .word 0x40021000 8010054: 40007000 .word 0x40007000 8010058: 42420068 .word 0x42420068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 801005c: 4b4b ldr r3, [pc, #300] @ (801018c ) 801005e: 681b ldr r3, [r3, #0] 8010060: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8010064: 2b00 cmp r3, #0 8010066: d1e9 bne.n 801003c #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8010068: 687b ldr r3, [r7, #4] 801006a: 6a1b ldr r3, [r3, #32] 801006c: 2b00 cmp r3, #0 801006e: f000 8088 beq.w 8010182 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8010072: 4b46 ldr r3, [pc, #280] @ (801018c ) 8010074: 685b ldr r3, [r3, #4] 8010076: f003 030c and.w r3, r3, #12 801007a: 2b08 cmp r3, #8 801007c: d068 beq.n 8010150 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 801007e: 687b ldr r3, [r7, #4] 8010080: 6a1b ldr r3, [r3, #32] 8010082: 2b02 cmp r3, #2 8010084: d14d bne.n 8010122 /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8010086: 4b42 ldr r3, [pc, #264] @ (8010190 ) 8010088: 2200 movs r2, #0 801008a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 801008c: f7fd fc66 bl 800d95c 8010090: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8010092: e008 b.n 80100a6 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8010094: f7fd fc62 bl 800d95c 8010098: 4602 mov r2, r0 801009a: 693b ldr r3, [r7, #16] 801009c: 1ad3 subs r3, r2, r3 801009e: 2b02 cmp r3, #2 80100a0: d901 bls.n 80100a6 { return HAL_TIMEOUT; 80100a2: 2303 movs r3, #3 80100a4: e06e b.n 8010184 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80100a6: 4b39 ldr r3, [pc, #228] @ (801018c ) 80100a8: 681b ldr r3, [r3, #0] 80100aa: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80100ae: 2b00 cmp r3, #0 80100b0: d1f0 bne.n 8010094 } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 80100b2: 687b ldr r3, [r7, #4] 80100b4: 6a5b ldr r3, [r3, #36] @ 0x24 80100b6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80100ba: d10f bne.n 80100dc assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); #if defined(RCC_CFGR2_PREDIV1SRC) assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); 80100bc: 4b33 ldr r3, [pc, #204] @ (801018c ) 80100be: 6ada ldr r2, [r3, #44] @ 0x2c 80100c0: 687b ldr r3, [r7, #4] 80100c2: 685b ldr r3, [r3, #4] 80100c4: 4931 ldr r1, [pc, #196] @ (801018c ) 80100c6: 4313 orrs r3, r2 80100c8: 62cb str r3, [r1, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 80100ca: 4b30 ldr r3, [pc, #192] @ (801018c ) 80100cc: 6adb ldr r3, [r3, #44] @ 0x2c 80100ce: f023 020f bic.w r2, r3, #15 80100d2: 687b ldr r3, [r7, #4] 80100d4: 68db ldr r3, [r3, #12] 80100d6: 492d ldr r1, [pc, #180] @ (801018c ) 80100d8: 4313 orrs r3, r2 80100da: 62cb str r3, [r1, #44] @ 0x2c } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80100dc: 4b2b ldr r3, [pc, #172] @ (801018c ) 80100de: 685b ldr r3, [r3, #4] 80100e0: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 80100e4: 687b ldr r3, [r7, #4] 80100e6: 6a59 ldr r1, [r3, #36] @ 0x24 80100e8: 687b ldr r3, [r7, #4] 80100ea: 6a9b ldr r3, [r3, #40] @ 0x28 80100ec: 430b orrs r3, r1 80100ee: 4927 ldr r1, [pc, #156] @ (801018c ) 80100f0: 4313 orrs r3, r2 80100f2: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 80100f4: 4b26 ldr r3, [pc, #152] @ (8010190 ) 80100f6: 2201 movs r2, #1 80100f8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80100fa: f7fd fc2f bl 800d95c 80100fe: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8010100: e008 b.n 8010114 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8010102: f7fd fc2b bl 800d95c 8010106: 4602 mov r2, r0 8010108: 693b ldr r3, [r7, #16] 801010a: 1ad3 subs r3, r2, r3 801010c: 2b02 cmp r3, #2 801010e: d901 bls.n 8010114 { return HAL_TIMEOUT; 8010110: 2303 movs r3, #3 8010112: e037 b.n 8010184 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8010114: 4b1d ldr r3, [pc, #116] @ (801018c ) 8010116: 681b ldr r3, [r3, #0] 8010118: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 801011c: 2b00 cmp r3, #0 801011e: d0f0 beq.n 8010102 8010120: e02f b.n 8010182 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8010122: 4b1b ldr r3, [pc, #108] @ (8010190 ) 8010124: 2200 movs r2, #0 8010126: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010128: f7fd fc18 bl 800d95c 801012c: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 801012e: e008 b.n 8010142 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8010130: f7fd fc14 bl 800d95c 8010134: 4602 mov r2, r0 8010136: 693b ldr r3, [r7, #16] 8010138: 1ad3 subs r3, r2, r3 801013a: 2b02 cmp r3, #2 801013c: d901 bls.n 8010142 { return HAL_TIMEOUT; 801013e: 2303 movs r3, #3 8010140: e020 b.n 8010184 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8010142: 4b12 ldr r3, [pc, #72] @ (801018c ) 8010144: 681b ldr r3, [r3, #0] 8010146: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 801014a: 2b00 cmp r3, #0 801014c: d1f0 bne.n 8010130 801014e: e018 b.n 8010182 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8010150: 687b ldr r3, [r7, #4] 8010152: 6a1b ldr r3, [r3, #32] 8010154: 2b01 cmp r3, #1 8010156: d101 bne.n 801015c { return HAL_ERROR; 8010158: 2301 movs r3, #1 801015a: e013 b.n 8010184 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 801015c: 4b0b ldr r3, [pc, #44] @ (801018c ) 801015e: 685b ldr r3, [r3, #4] 8010160: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8010162: 68fb ldr r3, [r7, #12] 8010164: f403 3280 and.w r2, r3, #65536 @ 0x10000 8010168: 687b ldr r3, [r7, #4] 801016a: 6a5b ldr r3, [r3, #36] @ 0x24 801016c: 429a cmp r2, r3 801016e: d106 bne.n 801017e (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8010170: 68fb ldr r3, [r7, #12] 8010172: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 8010176: 687b ldr r3, [r7, #4] 8010178: 6a9b ldr r3, [r3, #40] @ 0x28 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 801017a: 429a cmp r2, r3 801017c: d001 beq.n 8010182 { return HAL_ERROR; 801017e: 2301 movs r3, #1 8010180: e000 b.n 8010184 } } } } return HAL_OK; 8010182: 2300 movs r3, #0 } 8010184: 4618 mov r0, r3 8010186: 3718 adds r7, #24 8010188: 46bd mov sp, r7 801018a: bd80 pop {r7, pc} 801018c: 40021000 .word 0x40021000 8010190: 42420060 .word 0x42420060 08010194 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8010194: b580 push {r7, lr} 8010196: b084 sub sp, #16 8010198: af00 add r7, sp, #0 801019a: 6078 str r0, [r7, #4] 801019c: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 801019e: 687b ldr r3, [r7, #4] 80101a0: 2b00 cmp r3, #0 80101a2: d101 bne.n 80101a8 { return HAL_ERROR; 80101a4: 2301 movs r3, #1 80101a6: e0d0 b.n 801034a must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 80101a8: 4b6a ldr r3, [pc, #424] @ (8010354 ) 80101aa: 681b ldr r3, [r3, #0] 80101ac: f003 0307 and.w r3, r3, #7 80101b0: 683a ldr r2, [r7, #0] 80101b2: 429a cmp r2, r3 80101b4: d910 bls.n 80101d8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80101b6: 4b67 ldr r3, [pc, #412] @ (8010354 ) 80101b8: 681b ldr r3, [r3, #0] 80101ba: f023 0207 bic.w r2, r3, #7 80101be: 4965 ldr r1, [pc, #404] @ (8010354 ) 80101c0: 683b ldr r3, [r7, #0] 80101c2: 4313 orrs r3, r2 80101c4: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80101c6: 4b63 ldr r3, [pc, #396] @ (8010354 ) 80101c8: 681b ldr r3, [r3, #0] 80101ca: f003 0307 and.w r3, r3, #7 80101ce: 683a ldr r2, [r7, #0] 80101d0: 429a cmp r2, r3 80101d2: d001 beq.n 80101d8 { return HAL_ERROR; 80101d4: 2301 movs r3, #1 80101d6: e0b8 b.n 801034a } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 80101d8: 687b ldr r3, [r7, #4] 80101da: 681b ldr r3, [r3, #0] 80101dc: f003 0302 and.w r3, r3, #2 80101e0: 2b00 cmp r3, #0 80101e2: d020 beq.n 8010226 { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80101e4: 687b ldr r3, [r7, #4] 80101e6: 681b ldr r3, [r3, #0] 80101e8: f003 0304 and.w r3, r3, #4 80101ec: 2b00 cmp r3, #0 80101ee: d005 beq.n 80101fc { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 80101f0: 4b59 ldr r3, [pc, #356] @ (8010358 ) 80101f2: 685b ldr r3, [r3, #4] 80101f4: 4a58 ldr r2, [pc, #352] @ (8010358 ) 80101f6: f443 63e0 orr.w r3, r3, #1792 @ 0x700 80101fa: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80101fc: 687b ldr r3, [r7, #4] 80101fe: 681b ldr r3, [r3, #0] 8010200: f003 0308 and.w r3, r3, #8 8010204: 2b00 cmp r3, #0 8010206: d005 beq.n 8010214 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8010208: 4b53 ldr r3, [pc, #332] @ (8010358 ) 801020a: 685b ldr r3, [r3, #4] 801020c: 4a52 ldr r2, [pc, #328] @ (8010358 ) 801020e: f443 5360 orr.w r3, r3, #14336 @ 0x3800 8010212: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8010214: 4b50 ldr r3, [pc, #320] @ (8010358 ) 8010216: 685b ldr r3, [r3, #4] 8010218: f023 02f0 bic.w r2, r3, #240 @ 0xf0 801021c: 687b ldr r3, [r7, #4] 801021e: 689b ldr r3, [r3, #8] 8010220: 494d ldr r1, [pc, #308] @ (8010358 ) 8010222: 4313 orrs r3, r2 8010224: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8010226: 687b ldr r3, [r7, #4] 8010228: 681b ldr r3, [r3, #0] 801022a: f003 0301 and.w r3, r3, #1 801022e: 2b00 cmp r3, #0 8010230: d040 beq.n 80102b4 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8010232: 687b ldr r3, [r7, #4] 8010234: 685b ldr r3, [r3, #4] 8010236: 2b01 cmp r3, #1 8010238: d107 bne.n 801024a { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 801023a: 4b47 ldr r3, [pc, #284] @ (8010358 ) 801023c: 681b ldr r3, [r3, #0] 801023e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010242: 2b00 cmp r3, #0 8010244: d115 bne.n 8010272 { return HAL_ERROR; 8010246: 2301 movs r3, #1 8010248: e07f b.n 801034a } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 801024a: 687b ldr r3, [r7, #4] 801024c: 685b ldr r3, [r3, #4] 801024e: 2b02 cmp r3, #2 8010250: d107 bne.n 8010262 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8010252: 4b41 ldr r3, [pc, #260] @ (8010358 ) 8010254: 681b ldr r3, [r3, #0] 8010256: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 801025a: 2b00 cmp r3, #0 801025c: d109 bne.n 8010272 { return HAL_ERROR; 801025e: 2301 movs r3, #1 8010260: e073 b.n 801034a } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8010262: 4b3d ldr r3, [pc, #244] @ (8010358 ) 8010264: 681b ldr r3, [r3, #0] 8010266: f003 0302 and.w r3, r3, #2 801026a: 2b00 cmp r3, #0 801026c: d101 bne.n 8010272 { return HAL_ERROR; 801026e: 2301 movs r3, #1 8010270: e06b b.n 801034a } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8010272: 4b39 ldr r3, [pc, #228] @ (8010358 ) 8010274: 685b ldr r3, [r3, #4] 8010276: f023 0203 bic.w r2, r3, #3 801027a: 687b ldr r3, [r7, #4] 801027c: 685b ldr r3, [r3, #4] 801027e: 4936 ldr r1, [pc, #216] @ (8010358 ) 8010280: 4313 orrs r3, r2 8010282: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010284: f7fd fb6a bl 800d95c 8010288: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 801028a: e00a b.n 80102a2 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 801028c: f7fd fb66 bl 800d95c 8010290: 4602 mov r2, r0 8010292: 68fb ldr r3, [r7, #12] 8010294: 1ad3 subs r3, r2, r3 8010296: f241 3288 movw r2, #5000 @ 0x1388 801029a: 4293 cmp r3, r2 801029c: d901 bls.n 80102a2 { return HAL_TIMEOUT; 801029e: 2303 movs r3, #3 80102a0: e053 b.n 801034a while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80102a2: 4b2d ldr r3, [pc, #180] @ (8010358 ) 80102a4: 685b ldr r3, [r3, #4] 80102a6: f003 020c and.w r2, r3, #12 80102aa: 687b ldr r3, [r7, #4] 80102ac: 685b ldr r3, [r3, #4] 80102ae: 009b lsls r3, r3, #2 80102b0: 429a cmp r2, r3 80102b2: d1eb bne.n 801028c } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 80102b4: 4b27 ldr r3, [pc, #156] @ (8010354 ) 80102b6: 681b ldr r3, [r3, #0] 80102b8: f003 0307 and.w r3, r3, #7 80102bc: 683a ldr r2, [r7, #0] 80102be: 429a cmp r2, r3 80102c0: d210 bcs.n 80102e4 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80102c2: 4b24 ldr r3, [pc, #144] @ (8010354 ) 80102c4: 681b ldr r3, [r3, #0] 80102c6: f023 0207 bic.w r2, r3, #7 80102ca: 4922 ldr r1, [pc, #136] @ (8010354 ) 80102cc: 683b ldr r3, [r7, #0] 80102ce: 4313 orrs r3, r2 80102d0: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80102d2: 4b20 ldr r3, [pc, #128] @ (8010354 ) 80102d4: 681b ldr r3, [r3, #0] 80102d6: f003 0307 and.w r3, r3, #7 80102da: 683a ldr r2, [r7, #0] 80102dc: 429a cmp r2, r3 80102de: d001 beq.n 80102e4 { return HAL_ERROR; 80102e0: 2301 movs r3, #1 80102e2: e032 b.n 801034a } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80102e4: 687b ldr r3, [r7, #4] 80102e6: 681b ldr r3, [r3, #0] 80102e8: f003 0304 and.w r3, r3, #4 80102ec: 2b00 cmp r3, #0 80102ee: d008 beq.n 8010302 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 80102f0: 4b19 ldr r3, [pc, #100] @ (8010358 ) 80102f2: 685b ldr r3, [r3, #4] 80102f4: f423 62e0 bic.w r2, r3, #1792 @ 0x700 80102f8: 687b ldr r3, [r7, #4] 80102fa: 68db ldr r3, [r3, #12] 80102fc: 4916 ldr r1, [pc, #88] @ (8010358 ) 80102fe: 4313 orrs r3, r2 8010300: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8010302: 687b ldr r3, [r7, #4] 8010304: 681b ldr r3, [r3, #0] 8010306: f003 0308 and.w r3, r3, #8 801030a: 2b00 cmp r3, #0 801030c: d009 beq.n 8010322 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 801030e: 4b12 ldr r3, [pc, #72] @ (8010358 ) 8010310: 685b ldr r3, [r3, #4] 8010312: f423 5260 bic.w r2, r3, #14336 @ 0x3800 8010316: 687b ldr r3, [r7, #4] 8010318: 691b ldr r3, [r3, #16] 801031a: 00db lsls r3, r3, #3 801031c: 490e ldr r1, [pc, #56] @ (8010358 ) 801031e: 4313 orrs r3, r2 8010320: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8010322: f000 f821 bl 8010368 8010326: 4602 mov r2, r0 8010328: 4b0b ldr r3, [pc, #44] @ (8010358 ) 801032a: 685b ldr r3, [r3, #4] 801032c: 091b lsrs r3, r3, #4 801032e: f003 030f and.w r3, r3, #15 8010332: 490a ldr r1, [pc, #40] @ (801035c ) 8010334: 5ccb ldrb r3, [r1, r3] 8010336: fa22 f303 lsr.w r3, r2, r3 801033a: 4a09 ldr r2, [pc, #36] @ (8010360 ) 801033c: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 801033e: 4b09 ldr r3, [pc, #36] @ (8010364 ) 8010340: 681b ldr r3, [r3, #0] 8010342: 4618 mov r0, r3 8010344: f7fd fac8 bl 800d8d8 return HAL_OK; 8010348: 2300 movs r3, #0 } 801034a: 4618 mov r0, r3 801034c: 3710 adds r7, #16 801034e: 46bd mov sp, r7 8010350: bd80 pop {r7, pc} 8010352: bf00 nop 8010354: 40022000 .word 0x40022000 8010358: 40021000 .word 0x40021000 801035c: 08014424 .word 0x08014424 8010360: 2000006c .word 0x2000006c 8010364: 20000070 .word 0x20000070 08010368 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8010368: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 801036c: b08e sub sp, #56 @ 0x38 801036e: af00 add r7, sp, #0 #else static const uint8_t aPredivFactorTable[2U] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8010370: 2300 movs r3, #0 8010372: 62fb str r3, [r7, #44] @ 0x2c 8010374: 2300 movs r3, #0 8010376: 62bb str r3, [r7, #40] @ 0x28 8010378: 2300 movs r3, #0 801037a: 637b str r3, [r7, #52] @ 0x34 801037c: 2300 movs r3, #0 801037e: 627b str r3, [r7, #36] @ 0x24 uint32_t sysclockfreq = 0U; 8010380: 2300 movs r3, #0 8010382: 633b str r3, [r7, #48] @ 0x30 #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; 8010384: 2300 movs r3, #0 8010386: 623b str r3, [r7, #32] 8010388: 2300 movs r3, #0 801038a: 61fb str r3, [r7, #28] #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 801038c: 4b4e ldr r3, [pc, #312] @ (80104c8 ) 801038e: 685b ldr r3, [r3, #4] 8010390: 62fb str r3, [r7, #44] @ 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8010392: 6afb ldr r3, [r7, #44] @ 0x2c 8010394: f003 030c and.w r3, r3, #12 8010398: 2b04 cmp r3, #4 801039a: d002 beq.n 80103a2 801039c: 2b08 cmp r3, #8 801039e: d003 beq.n 80103a8 80103a0: e089 b.n 80104b6 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 80103a2: 4b4a ldr r3, [pc, #296] @ (80104cc ) 80103a4: 633b str r3, [r7, #48] @ 0x30 break; 80103a6: e089 b.n 80104bc } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 80103a8: 6afb ldr r3, [r7, #44] @ 0x2c 80103aa: 0c9b lsrs r3, r3, #18 80103ac: f003 020f and.w r2, r3, #15 80103b0: 4b47 ldr r3, [pc, #284] @ (80104d0 ) 80103b2: 5c9b ldrb r3, [r3, r2] 80103b4: 627b str r3, [r7, #36] @ 0x24 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 80103b6: 6afb ldr r3, [r7, #44] @ 0x2c 80103b8: f403 3380 and.w r3, r3, #65536 @ 0x10000 80103bc: 2b00 cmp r3, #0 80103be: d072 beq.n 80104a6 { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 80103c0: 4b41 ldr r3, [pc, #260] @ (80104c8 ) 80103c2: 6adb ldr r3, [r3, #44] @ 0x2c 80103c4: f003 020f and.w r2, r3, #15 80103c8: 4b42 ldr r3, [pc, #264] @ (80104d4 ) 80103ca: 5c9b ldrb r3, [r3, r2] 80103cc: 62bb str r3, [r7, #40] @ 0x28 #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /*RCC_CFGR2_PREDIV1*/ #if defined(RCC_CFGR2_PREDIV1SRC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 80103ce: 4b3e ldr r3, [pc, #248] @ (80104c8 ) 80103d0: 6adb ldr r3, [r3, #44] @ 0x2c 80103d2: f403 3380 and.w r3, r3, #65536 @ 0x10000 80103d6: 2b00 cmp r3, #0 80103d8: d053 beq.n 8010482 { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 80103da: 4b3b ldr r3, [pc, #236] @ (80104c8 ) 80103dc: 6adb ldr r3, [r3, #44] @ 0x2c 80103de: 091b lsrs r3, r3, #4 80103e0: f003 030f and.w r3, r3, #15 80103e4: 3301 adds r3, #1 80103e6: 623b str r3, [r7, #32] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 80103e8: 4b37 ldr r3, [pc, #220] @ (80104c8 ) 80103ea: 6adb ldr r3, [r3, #44] @ 0x2c 80103ec: 0a1b lsrs r3, r3, #8 80103ee: f003 030f and.w r3, r3, #15 80103f2: 3302 adds r3, #2 80103f4: 61fb str r3, [r7, #28] pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); 80103f6: 69fb ldr r3, [r7, #28] 80103f8: 2200 movs r2, #0 80103fa: 469a mov sl, r3 80103fc: 4693 mov fp, r2 80103fe: 6a7b ldr r3, [r7, #36] @ 0x24 8010400: 2200 movs r2, #0 8010402: 613b str r3, [r7, #16] 8010404: 617a str r2, [r7, #20] 8010406: 693b ldr r3, [r7, #16] 8010408: fb03 f20b mul.w r2, r3, fp 801040c: 697b ldr r3, [r7, #20] 801040e: fb0a f303 mul.w r3, sl, r3 8010412: 4413 add r3, r2 8010414: 693a ldr r2, [r7, #16] 8010416: fbaa 0102 umull r0, r1, sl, r2 801041a: 440b add r3, r1 801041c: 4619 mov r1, r3 801041e: 4b2b ldr r3, [pc, #172] @ (80104cc ) 8010420: fb03 f201 mul.w r2, r3, r1 8010424: 2300 movs r3, #0 8010426: fb00 f303 mul.w r3, r0, r3 801042a: 4413 add r3, r2 801042c: 4a27 ldr r2, [pc, #156] @ (80104cc ) 801042e: fba0 4502 umull r4, r5, r0, r2 8010432: 442b add r3, r5 8010434: 461d mov r5, r3 8010436: 6a3b ldr r3, [r7, #32] 8010438: 2200 movs r2, #0 801043a: 60bb str r3, [r7, #8] 801043c: 60fa str r2, [r7, #12] 801043e: 6abb ldr r3, [r7, #40] @ 0x28 8010440: 2200 movs r2, #0 8010442: 603b str r3, [r7, #0] 8010444: 607a str r2, [r7, #4] 8010446: e9d7 0102 ldrd r0, r1, [r7, #8] 801044a: 460b mov r3, r1 801044c: e9d7 ab00 ldrd sl, fp, [r7] 8010450: 4652 mov r2, sl 8010452: fb02 f203 mul.w r2, r2, r3 8010456: 465b mov r3, fp 8010458: 4684 mov ip, r0 801045a: fb0c f303 mul.w r3, ip, r3 801045e: 4413 add r3, r2 8010460: 4602 mov r2, r0 8010462: 4651 mov r1, sl 8010464: fba2 8901 umull r8, r9, r2, r1 8010468: 444b add r3, r9 801046a: 4699 mov r9, r3 801046c: 4642 mov r2, r8 801046e: 464b mov r3, r9 8010470: 4620 mov r0, r4 8010472: 4629 mov r1, r5 8010474: f7f8 fdf0 bl 8009058 <__aeabi_uldivmod> 8010478: 4602 mov r2, r0 801047a: 460b mov r3, r1 801047c: 4613 mov r3, r2 801047e: 637b str r3, [r7, #52] @ 0x34 8010480: e007 b.n 8010492 } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8010482: 6a7b ldr r3, [r7, #36] @ 0x24 8010484: 4a11 ldr r2, [pc, #68] @ (80104cc ) 8010486: fb03 f202 mul.w r2, r3, r2 801048a: 6abb ldr r3, [r7, #40] @ 0x28 801048c: fbb2 f3f3 udiv r3, r2, r3 8010490: 637b str r3, [r7, #52] @ 0x34 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 8010492: 4b0f ldr r3, [pc, #60] @ (80104d0 ) 8010494: 7b5b ldrb r3, [r3, #13] 8010496: 461a mov r2, r3 8010498: 6a7b ldr r3, [r7, #36] @ 0x24 801049a: 4293 cmp r3, r2 801049c: d108 bne.n 80104b0 { pllclk = pllclk / 2; 801049e: 6b7b ldr r3, [r7, #52] @ 0x34 80104a0: 085b lsrs r3, r3, #1 80104a2: 637b str r3, [r7, #52] @ 0x34 80104a4: e004 b.n 80104b0 #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 80104a6: 6a7b ldr r3, [r7, #36] @ 0x24 80104a8: 4a0b ldr r2, [pc, #44] @ (80104d8 ) 80104aa: fb02 f303 mul.w r3, r2, r3 80104ae: 637b str r3, [r7, #52] @ 0x34 } sysclockfreq = pllclk; 80104b0: 6b7b ldr r3, [r7, #52] @ 0x34 80104b2: 633b str r3, [r7, #48] @ 0x30 break; 80104b4: e002 b.n 80104bc } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 80104b6: 4b09 ldr r3, [pc, #36] @ (80104dc ) 80104b8: 633b str r3, [r7, #48] @ 0x30 break; 80104ba: bf00 nop } } return sysclockfreq; 80104bc: 6b3b ldr r3, [r7, #48] @ 0x30 } 80104be: 4618 mov r0, r3 80104c0: 3738 adds r7, #56 @ 0x38 80104c2: 46bd mov sp, r7 80104c4: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 80104c8: 40021000 .word 0x40021000 80104cc: 017d7840 .word 0x017d7840 80104d0: 0801443c .word 0x0801443c 80104d4: 0801444c .word 0x0801444c 80104d8: 003d0900 .word 0x003d0900 80104dc: 007a1200 .word 0x007a1200 080104e0 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 80104e0: b480 push {r7} 80104e2: af00 add r7, sp, #0 return SystemCoreClock; 80104e4: 4b02 ldr r3, [pc, #8] @ (80104f0 ) 80104e6: 681b ldr r3, [r3, #0] } 80104e8: 4618 mov r0, r3 80104ea: 46bd mov sp, r7 80104ec: bc80 pop {r7} 80104ee: 4770 bx lr 80104f0: 2000006c .word 0x2000006c 080104f4 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 80104f4: b580 push {r7, lr} 80104f6: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 80104f8: f7ff fff2 bl 80104e0 80104fc: 4602 mov r2, r0 80104fe: 4b05 ldr r3, [pc, #20] @ (8010514 ) 8010500: 685b ldr r3, [r3, #4] 8010502: 0a1b lsrs r3, r3, #8 8010504: f003 0307 and.w r3, r3, #7 8010508: 4903 ldr r1, [pc, #12] @ (8010518 ) 801050a: 5ccb ldrb r3, [r1, r3] 801050c: fa22 f303 lsr.w r3, r2, r3 } 8010510: 4618 mov r0, r3 8010512: bd80 pop {r7, pc} 8010514: 40021000 .word 0x40021000 8010518: 08014434 .word 0x08014434 0801051c : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 801051c: b580 push {r7, lr} 801051e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8010520: f7ff ffde bl 80104e0 8010524: 4602 mov r2, r0 8010526: 4b05 ldr r3, [pc, #20] @ (801053c ) 8010528: 685b ldr r3, [r3, #4] 801052a: 0adb lsrs r3, r3, #11 801052c: f003 0307 and.w r3, r3, #7 8010530: 4903 ldr r1, [pc, #12] @ (8010540 ) 8010532: 5ccb ldrb r3, [r1, r3] 8010534: fa22 f303 lsr.w r3, r2, r3 } 8010538: 4618 mov r0, r3 801053a: bd80 pop {r7, pc} 801053c: 40021000 .word 0x40021000 8010540: 08014434 .word 0x08014434 08010544 : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8010544: b480 push {r7} 8010546: b085 sub sp, #20 8010548: af00 add r7, sp, #0 801054a: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 801054c: 4b0a ldr r3, [pc, #40] @ (8010578 ) 801054e: 681b ldr r3, [r3, #0] 8010550: 4a0a ldr r2, [pc, #40] @ (801057c ) 8010552: fba2 2303 umull r2, r3, r2, r3 8010556: 0a5b lsrs r3, r3, #9 8010558: 687a ldr r2, [r7, #4] 801055a: fb02 f303 mul.w r3, r2, r3 801055e: 60fb str r3, [r7, #12] do { __NOP(); 8010560: bf00 nop } while (Delay --); 8010562: 68fb ldr r3, [r7, #12] 8010564: 1e5a subs r2, r3, #1 8010566: 60fa str r2, [r7, #12] 8010568: 2b00 cmp r3, #0 801056a: d1f9 bne.n 8010560 } 801056c: bf00 nop 801056e: bf00 nop 8010570: 3714 adds r7, #20 8010572: 46bd mov sp, r7 8010574: bc80 pop {r7} 8010576: 4770 bx lr 8010578: 2000006c .word 0x2000006c 801057c: 10624dd3 .word 0x10624dd3 08010580 : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8010580: b580 push {r7, lr} 8010582: b088 sub sp, #32 8010584: af00 add r7, sp, #0 8010586: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 8010588: 2300 movs r3, #0 801058a: 617b str r3, [r7, #20] 801058c: 2300 movs r3, #0 801058e: 613b str r3, [r7, #16] #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t pllactive = 0U; 8010590: 2300 movs r3, #0 8010592: 61fb str r3, [r7, #28] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 8010594: 687b ldr r3, [r7, #4] 8010596: 681b ldr r3, [r3, #0] 8010598: f003 0301 and.w r3, r3, #1 801059c: 2b00 cmp r3, #0 801059e: d07d beq.n 801069c { FlagStatus pwrclkchanged = RESET; 80105a0: 2300 movs r3, #0 80105a2: 76fb strb r3, [r7, #27] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80105a4: 4b8b ldr r3, [pc, #556] @ (80107d4 ) 80105a6: 69db ldr r3, [r3, #28] 80105a8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80105ac: 2b00 cmp r3, #0 80105ae: d10d bne.n 80105cc { __HAL_RCC_PWR_CLK_ENABLE(); 80105b0: 4b88 ldr r3, [pc, #544] @ (80107d4 ) 80105b2: 69db ldr r3, [r3, #28] 80105b4: 4a87 ldr r2, [pc, #540] @ (80107d4 ) 80105b6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80105ba: 61d3 str r3, [r2, #28] 80105bc: 4b85 ldr r3, [pc, #532] @ (80107d4 ) 80105be: 69db ldr r3, [r3, #28] 80105c0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80105c4: 60fb str r3, [r7, #12] 80105c6: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 80105c8: 2301 movs r3, #1 80105ca: 76fb strb r3, [r7, #27] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80105cc: 4b82 ldr r3, [pc, #520] @ (80107d8 ) 80105ce: 681b ldr r3, [r3, #0] 80105d0: f403 7380 and.w r3, r3, #256 @ 0x100 80105d4: 2b00 cmp r3, #0 80105d6: d118 bne.n 801060a { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80105d8: 4b7f ldr r3, [pc, #508] @ (80107d8 ) 80105da: 681b ldr r3, [r3, #0] 80105dc: 4a7e ldr r2, [pc, #504] @ (80107d8 ) 80105de: f443 7380 orr.w r3, r3, #256 @ 0x100 80105e2: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80105e4: f7fd f9ba bl 800d95c 80105e8: 6178 str r0, [r7, #20] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80105ea: e008 b.n 80105fe { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80105ec: f7fd f9b6 bl 800d95c 80105f0: 4602 mov r2, r0 80105f2: 697b ldr r3, [r7, #20] 80105f4: 1ad3 subs r3, r2, r3 80105f6: 2b64 cmp r3, #100 @ 0x64 80105f8: d901 bls.n 80105fe { return HAL_TIMEOUT; 80105fa: 2303 movs r3, #3 80105fc: e0e5 b.n 80107ca while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80105fe: 4b76 ldr r3, [pc, #472] @ (80107d8 ) 8010600: 681b ldr r3, [r3, #0] 8010602: f403 7380 and.w r3, r3, #256 @ 0x100 8010606: 2b00 cmp r3, #0 8010608: d0f0 beq.n 80105ec } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 801060a: 4b72 ldr r3, [pc, #456] @ (80107d4 ) 801060c: 6a1b ldr r3, [r3, #32] 801060e: f403 7340 and.w r3, r3, #768 @ 0x300 8010612: 613b str r3, [r7, #16] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8010614: 693b ldr r3, [r7, #16] 8010616: 2b00 cmp r3, #0 8010618: d02e beq.n 8010678 801061a: 687b ldr r3, [r7, #4] 801061c: 685b ldr r3, [r3, #4] 801061e: f403 7340 and.w r3, r3, #768 @ 0x300 8010622: 693a ldr r2, [r7, #16] 8010624: 429a cmp r2, r3 8010626: d027 beq.n 8010678 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8010628: 4b6a ldr r3, [pc, #424] @ (80107d4 ) 801062a: 6a1b ldr r3, [r3, #32] 801062c: f423 7340 bic.w r3, r3, #768 @ 0x300 8010630: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8010632: 4b6a ldr r3, [pc, #424] @ (80107dc ) 8010634: 2201 movs r2, #1 8010636: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8010638: 4b68 ldr r3, [pc, #416] @ (80107dc ) 801063a: 2200 movs r2, #0 801063c: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 801063e: 4a65 ldr r2, [pc, #404] @ (80107d4 ) 8010640: 693b ldr r3, [r7, #16] 8010642: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8010644: 693b ldr r3, [r7, #16] 8010646: f003 0301 and.w r3, r3, #1 801064a: 2b00 cmp r3, #0 801064c: d014 beq.n 8010678 { /* Get Start Tick */ tickstart = HAL_GetTick(); 801064e: f7fd f985 bl 800d95c 8010652: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8010654: e00a b.n 801066c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8010656: f7fd f981 bl 800d95c 801065a: 4602 mov r2, r0 801065c: 697b ldr r3, [r7, #20] 801065e: 1ad3 subs r3, r2, r3 8010660: f241 3288 movw r2, #5000 @ 0x1388 8010664: 4293 cmp r3, r2 8010666: d901 bls.n 801066c { return HAL_TIMEOUT; 8010668: 2303 movs r3, #3 801066a: e0ae b.n 80107ca while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 801066c: 4b59 ldr r3, [pc, #356] @ (80107d4 ) 801066e: 6a1b ldr r3, [r3, #32] 8010670: f003 0302 and.w r3, r3, #2 8010674: 2b00 cmp r3, #0 8010676: d0ee beq.n 8010656 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8010678: 4b56 ldr r3, [pc, #344] @ (80107d4 ) 801067a: 6a1b ldr r3, [r3, #32] 801067c: f423 7240 bic.w r2, r3, #768 @ 0x300 8010680: 687b ldr r3, [r7, #4] 8010682: 685b ldr r3, [r3, #4] 8010684: 4953 ldr r1, [pc, #332] @ (80107d4 ) 8010686: 4313 orrs r3, r2 8010688: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 801068a: 7efb ldrb r3, [r7, #27] 801068c: 2b01 cmp r3, #1 801068e: d105 bne.n 801069c { __HAL_RCC_PWR_CLK_DISABLE(); 8010690: 4b50 ldr r3, [pc, #320] @ (80107d4 ) 8010692: 69db ldr r3, [r3, #28] 8010694: 4a4f ldr r2, [pc, #316] @ (80107d4 ) 8010696: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 801069a: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 801069c: 687b ldr r3, [r7, #4] 801069e: 681b ldr r3, [r3, #0] 80106a0: f003 0302 and.w r3, r3, #2 80106a4: 2b00 cmp r3, #0 80106a6: d008 beq.n 80106ba { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 80106a8: 4b4a ldr r3, [pc, #296] @ (80107d4 ) 80106aa: 685b ldr r3, [r3, #4] 80106ac: f423 4240 bic.w r2, r3, #49152 @ 0xc000 80106b0: 687b ldr r3, [r7, #4] 80106b2: 689b ldr r3, [r3, #8] 80106b4: 4947 ldr r1, [pc, #284] @ (80107d4 ) 80106b6: 4313 orrs r3, r2 80106b8: 604b str r3, [r1, #4] } #if defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ I2S2 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) 80106ba: 687b ldr r3, [r7, #4] 80106bc: 681b ldr r3, [r3, #0] 80106be: f003 0304 and.w r3, r3, #4 80106c2: 2b00 cmp r3, #0 80106c4: d008 beq.n 80106d8 { /* Check the parameters */ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); /* Configure the I2S2 clock source */ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); 80106c6: 4b43 ldr r3, [pc, #268] @ (80107d4 ) 80106c8: 6adb ldr r3, [r3, #44] @ 0x2c 80106ca: f423 3200 bic.w r2, r3, #131072 @ 0x20000 80106ce: 687b ldr r3, [r7, #4] 80106d0: 68db ldr r3, [r3, #12] 80106d2: 4940 ldr r1, [pc, #256] @ (80107d4 ) 80106d4: 4313 orrs r3, r2 80106d6: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ I2S3 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) 80106d8: 687b ldr r3, [r7, #4] 80106da: 681b ldr r3, [r3, #0] 80106dc: f003 0308 and.w r3, r3, #8 80106e0: 2b00 cmp r3, #0 80106e2: d008 beq.n 80106f6 { /* Check the parameters */ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); /* Configure the I2S3 clock source */ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); 80106e4: 4b3b ldr r3, [pc, #236] @ (80107d4 ) 80106e6: 6adb ldr r3, [r3, #44] @ 0x2c 80106e8: f423 2280 bic.w r2, r3, #262144 @ 0x40000 80106ec: 687b ldr r3, [r7, #4] 80106ee: 691b ldr r3, [r3, #16] 80106f0: 4938 ldr r1, [pc, #224] @ (80107d4 ) 80106f2: 4313 orrs r3, r2 80106f4: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ PLL I2S Configuration ----------------------*/ /* Check that PLLI2S need to be enabled */ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) 80106f6: 4b37 ldr r3, [pc, #220] @ (80107d4 ) 80106f8: 6adb ldr r3, [r3, #44] @ 0x2c 80106fa: f403 3300 and.w r3, r3, #131072 @ 0x20000 80106fe: 2b00 cmp r3, #0 8010700: d105 bne.n 801070e 8010702: 4b34 ldr r3, [pc, #208] @ (80107d4 ) 8010704: 6adb ldr r3, [r3, #44] @ 0x2c 8010706: f403 2380 and.w r3, r3, #262144 @ 0x40000 801070a: 2b00 cmp r3, #0 801070c: d001 beq.n 8010712 { /* Update flag to indicate that PLL I2S should be active */ pllactive = 1; 801070e: 2301 movs r3, #1 8010710: 61fb str r3, [r7, #28] } /* Check if PLL I2S need to be enabled */ if (pllactive == 1) 8010712: 69fb ldr r3, [r7, #28] 8010714: 2b01 cmp r3, #1 8010716: d148 bne.n 80107aa { /* Enable PLL I2S only if not active */ if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) 8010718: 4b2e ldr r3, [pc, #184] @ (80107d4 ) 801071a: 681b ldr r3, [r3, #0] 801071c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010720: 2b00 cmp r3, #0 8010722: d138 bne.n 8010796 assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); /* Prediv2 can be written only when the PLL2 is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 8010724: 4b2b ldr r3, [pc, #172] @ (80107d4 ) 8010726: 681b ldr r3, [r3, #0] 8010728: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 801072c: 2b00 cmp r3, #0 801072e: d009 beq.n 8010744 (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) 8010730: 4b28 ldr r3, [pc, #160] @ (80107d4 ) 8010732: 6adb ldr r3, [r3, #44] @ 0x2c 8010734: f003 02f0 and.w r2, r3, #240 @ 0xf0 8010738: 687b ldr r3, [r7, #4] 801073a: 699b ldr r3, [r3, #24] if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 801073c: 429a cmp r2, r3 801073e: d001 beq.n 8010744 { return HAL_ERROR; 8010740: 2301 movs r3, #1 8010742: e042 b.n 80107ca } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); 8010744: 4b23 ldr r3, [pc, #140] @ (80107d4 ) 8010746: 6adb ldr r3, [r3, #44] @ 0x2c 8010748: f023 02f0 bic.w r2, r3, #240 @ 0xf0 801074c: 687b ldr r3, [r7, #4] 801074e: 699b ldr r3, [r3, #24] 8010750: 4920 ldr r1, [pc, #128] @ (80107d4 ) 8010752: 4313 orrs r3, r2 8010754: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); 8010756: 4b1f ldr r3, [pc, #124] @ (80107d4 ) 8010758: 6adb ldr r3, [r3, #44] @ 0x2c 801075a: f423 4270 bic.w r2, r3, #61440 @ 0xf000 801075e: 687b ldr r3, [r7, #4] 8010760: 695b ldr r3, [r3, #20] 8010762: 491c ldr r1, [pc, #112] @ (80107d4 ) 8010764: 4313 orrs r3, r2 8010766: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); 8010768: 4b1d ldr r3, [pc, #116] @ (80107e0 ) 801076a: 2201 movs r2, #1 801076c: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 801076e: f7fd f8f5 bl 800d95c 8010772: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8010774: e008 b.n 8010788 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8010776: f7fd f8f1 bl 800d95c 801077a: 4602 mov r2, r0 801077c: 697b ldr r3, [r7, #20] 801077e: 1ad3 subs r3, r2, r3 8010780: 2b64 cmp r3, #100 @ 0x64 8010782: d901 bls.n 8010788 { return HAL_TIMEOUT; 8010784: 2303 movs r3, #3 8010786: e020 b.n 80107ca while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8010788: 4b12 ldr r3, [pc, #72] @ (80107d4 ) 801078a: 681b ldr r3, [r3, #0] 801078c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8010790: 2b00 cmp r3, #0 8010792: d0f0 beq.n 8010776 8010794: e009 b.n 80107aa } } else { /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) 8010796: 4b0f ldr r3, [pc, #60] @ (80107d4 ) 8010798: 6adb ldr r3, [r3, #44] @ 0x2c 801079a: f403 4270 and.w r2, r3, #61440 @ 0xf000 801079e: 687b ldr r3, [r7, #4] 80107a0: 695b ldr r3, [r3, #20] 80107a2: 429a cmp r2, r3 80107a4: d001 beq.n 80107aa { return HAL_ERROR; 80107a6: 2301 movs r3, #1 80107a8: e00f b.n 80107ca #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 80107aa: 687b ldr r3, [r7, #4] 80107ac: 681b ldr r3, [r3, #0] 80107ae: f003 0310 and.w r3, r3, #16 80107b2: 2b00 cmp r3, #0 80107b4: d008 beq.n 80107c8 { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 80107b6: 4b07 ldr r3, [pc, #28] @ (80107d4 ) 80107b8: 685b ldr r3, [r3, #4] 80107ba: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 80107be: 687b ldr r3, [r7, #4] 80107c0: 69db ldr r3, [r3, #28] 80107c2: 4904 ldr r1, [pc, #16] @ (80107d4 ) 80107c4: 4313 orrs r3, r2 80107c6: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 80107c8: 2300 movs r3, #0 } 80107ca: 4618 mov r0, r3 80107cc: 3720 adds r7, #32 80107ce: 46bd mov sp, r7 80107d0: bd80 pop {r7, pc} 80107d2: bf00 nop 80107d4: 40021000 .word 0x40021000 80107d8: 40007000 .word 0x40007000 80107dc: 42420440 .word 0x42420440 80107e0: 42420070 .word 0x42420070 080107e4 : * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 80107e4: b580 push {r7, lr} 80107e6: b08a sub sp, #40 @ 0x28 80107e8: af00 add r7, sp, #0 80107ea: 6078 str r0, [r7, #4] #if defined(STM32F105xC) || defined(STM32F107xC) static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; 80107ec: 2300 movs r3, #0 80107ee: 61fb str r3, [r7, #28] 80107f0: 2300 movs r3, #0 80107f2: 627b str r3, [r7, #36] @ 0x24 80107f4: 2300 movs r3, #0 80107f6: 61bb str r3, [r7, #24] uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; 80107f8: 2300 movs r3, #0 80107fa: 617b str r3, [r7, #20] 80107fc: 2300 movs r3, #0 80107fe: 613b str r3, [r7, #16] 8010800: 2300 movs r3, #0 8010802: 60fb str r3, [r7, #12] static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; static const uint8_t aPredivFactorTable[2U] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 8010804: 2300 movs r3, #0 8010806: 60bb str r3, [r7, #8] 8010808: 2300 movs r3, #0 801080a: 623b str r3, [r7, #32] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 801080c: 687b ldr r3, [r7, #4] 801080e: 3b01 subs r3, #1 8010810: 2b0f cmp r3, #15 8010812: f200 811d bhi.w 8010a50 8010816: a201 add r2, pc, #4 @ (adr r2, 801081c ) 8010818: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801081c: 080109d1 .word 0x080109d1 8010820: 08010a35 .word 0x08010a35 8010824: 08010a51 .word 0x08010a51 8010828: 0801092f .word 0x0801092f 801082c: 08010a51 .word 0x08010a51 8010830: 08010a51 .word 0x08010a51 8010834: 08010a51 .word 0x08010a51 8010838: 08010981 .word 0x08010981 801083c: 08010a51 .word 0x08010a51 8010840: 08010a51 .word 0x08010a51 8010844: 08010a51 .word 0x08010a51 8010848: 08010a51 .word 0x08010a51 801084c: 08010a51 .word 0x08010a51 8010850: 08010a51 .word 0x08010a51 8010854: 08010a51 .word 0x08010a51 8010858: 0801085d .word 0x0801085d || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_USB: { /* Get RCC configuration ------------------------------------------------------*/ temp_reg = RCC->CFGR; 801085c: 4b83 ldr r3, [pc, #524] @ (8010a6c ) 801085e: 685b ldr r3, [r3, #4] 8010860: 60bb str r3, [r7, #8] /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) 8010862: 4b82 ldr r3, [pc, #520] @ (8010a6c ) 8010864: 681b ldr r3, [r3, #0] 8010866: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 801086a: 2b00 cmp r3, #0 801086c: f000 80f2 beq.w 8010a54 { pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8010870: 68bb ldr r3, [r7, #8] 8010872: 0c9b lsrs r3, r3, #18 8010874: f003 030f and.w r3, r3, #15 8010878: 4a7d ldr r2, [pc, #500] @ (8010a70 ) 801087a: 5cd3 ldrb r3, [r2, r3] 801087c: 61bb str r3, [r7, #24] if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 801087e: 68bb ldr r3, [r7, #8] 8010880: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010884: 2b00 cmp r3, #0 8010886: d03b beq.n 8010900 { #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ || defined(STM32F100xE) prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 8010888: 4b78 ldr r3, [pc, #480] @ (8010a6c ) 801088a: 6adb ldr r3, [r3, #44] @ 0x2c 801088c: f003 030f and.w r3, r3, #15 8010890: 4a78 ldr r2, [pc, #480] @ (8010a74 ) 8010892: 5cd3 ldrb r3, [r2, r3] 8010894: 61fb str r3, [r7, #28] #else prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 8010896: 4b75 ldr r3, [pc, #468] @ (8010a6c ) 8010898: 6adb ldr r3, [r3, #44] @ 0x2c 801089a: f403 3380 and.w r3, r3, #65536 @ 0x10000 801089e: 2b00 cmp r3, #0 80108a0: d01c beq.n 80108dc { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 80108a2: 4b72 ldr r3, [pc, #456] @ (8010a6c ) 80108a4: 6adb ldr r3, [r3, #44] @ 0x2c 80108a6: 091b lsrs r3, r3, #4 80108a8: f003 030f and.w r3, r3, #15 80108ac: 3301 adds r3, #1 80108ae: 60fb str r3, [r7, #12] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 80108b0: 4b6e ldr r3, [pc, #440] @ (8010a6c ) 80108b2: 6adb ldr r3, [r3, #44] @ 0x2c 80108b4: 0a1b lsrs r3, r3, #8 80108b6: f003 030f and.w r3, r3, #15 80108ba: 3302 adds r3, #2 80108bc: 617b str r3, [r7, #20] pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); 80108be: 4a6e ldr r2, [pc, #440] @ (8010a78 ) 80108c0: 68fb ldr r3, [r7, #12] 80108c2: fbb2 f3f3 udiv r3, r2, r3 80108c6: 697a ldr r2, [r7, #20] 80108c8: fb03 f202 mul.w r2, r3, r2 80108cc: 69fb ldr r3, [r7, #28] 80108ce: fbb2 f2f3 udiv r2, r2, r3 80108d2: 69bb ldr r3, [r7, #24] 80108d4: fb02 f303 mul.w r3, r2, r3 80108d8: 627b str r3, [r7, #36] @ 0x24 80108da: e007 b.n 80108ec } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); 80108dc: 4a66 ldr r2, [pc, #408] @ (8010a78 ) 80108de: 69fb ldr r3, [r7, #28] 80108e0: fbb2 f2f3 udiv r2, r2, r3 80108e4: 69bb ldr r3, [r7, #24] 80108e6: fb02 f303 mul.w r3, r2, r3 80108ea: 627b str r3, [r7, #36] @ 0x24 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 80108ec: 4b60 ldr r3, [pc, #384] @ (8010a70 ) 80108ee: 7b5b ldrb r3, [r3, #13] 80108f0: 461a mov r2, r3 80108f2: 69bb ldr r3, [r7, #24] 80108f4: 4293 cmp r3, r2 80108f6: d108 bne.n 801090a { pllclk = pllclk / 2; 80108f8: 6a7b ldr r3, [r7, #36] @ 0x24 80108fa: 085b lsrs r3, r3, #1 80108fc: 627b str r3, [r7, #36] @ 0x24 80108fe: e004 b.n 801090a #endif /* STM32F105xC || STM32F107xC */ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8010900: 69bb ldr r3, [r7, #24] 8010902: 4a5e ldr r2, [pc, #376] @ (8010a7c ) 8010904: fb02 f303 mul.w r3, r2, r3 8010908: 627b str r3, [r7, #36] @ 0x24 } /* Calcul of the USB frequency*/ #if defined(STM32F105xC) || defined(STM32F107xC) /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) 801090a: 4b58 ldr r3, [pc, #352] @ (8010a6c ) 801090c: 685b ldr r3, [r3, #4] 801090e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8010912: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8010916: d102 bne.n 801091e { /* Prescaler of 2 selected for USB */ frequency = pllclk; 8010918: 6a7b ldr r3, [r7, #36] @ 0x24 801091a: 623b str r3, [r7, #32] /* Prescaler of 1.5 selected for USB */ frequency = (pllclk * 2) / 3; } #endif } break; 801091c: e09a b.n 8010a54 frequency = (2 * pllclk) / 3; 801091e: 6a7b ldr r3, [r7, #36] @ 0x24 8010920: 005b lsls r3, r3, #1 8010922: 4a57 ldr r2, [pc, #348] @ (8010a80 ) 8010924: fba2 2303 umull r2, r3, r2, r3 8010928: 085b lsrs r3, r3, #1 801092a: 623b str r3, [r7, #32] break; 801092c: e092 b.n 8010a54 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) 801092e: 4b4f ldr r3, [pc, #316] @ (8010a6c ) 8010930: 6adb ldr r3, [r3, #44] @ 0x2c 8010932: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010936: 2b00 cmp r3, #0 8010938: d103 bne.n 8010942 { /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); 801093a: f7ff fd15 bl 8010368 801093e: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8010940: e08a b.n 8010a58 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8010942: 4b4a ldr r3, [pc, #296] @ (8010a6c ) 8010944: 681b ldr r3, [r3, #0] 8010946: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 801094a: 2b00 cmp r3, #0 801094c: f000 8084 beq.w 8010a58 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8010950: 4b46 ldr r3, [pc, #280] @ (8010a6c ) 8010952: 6adb ldr r3, [r3, #44] @ 0x2c 8010954: 091b lsrs r3, r3, #4 8010956: f003 030f and.w r3, r3, #15 801095a: 3301 adds r3, #1 801095c: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 801095e: 4b43 ldr r3, [pc, #268] @ (8010a6c ) 8010960: 6adb ldr r3, [r3, #44] @ 0x2c 8010962: 0b1b lsrs r3, r3, #12 8010964: f003 030f and.w r3, r3, #15 8010968: 3302 adds r3, #2 801096a: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 801096c: 4a42 ldr r2, [pc, #264] @ (8010a78 ) 801096e: 68fb ldr r3, [r7, #12] 8010970: fbb2 f3f3 udiv r3, r2, r3 8010974: 693a ldr r2, [r7, #16] 8010976: fb02 f303 mul.w r3, r2, r3 801097a: 005b lsls r3, r3, #1 801097c: 623b str r3, [r7, #32] break; 801097e: e06b b.n 8010a58 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) 8010980: 4b3a ldr r3, [pc, #232] @ (8010a6c ) 8010982: 6adb ldr r3, [r3, #44] @ 0x2c 8010984: f403 2380 and.w r3, r3, #262144 @ 0x40000 8010988: 2b00 cmp r3, #0 801098a: d103 bne.n 8010994 { /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); 801098c: f7ff fcec bl 8010368 8010990: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8010992: e063 b.n 8010a5c if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8010994: 4b35 ldr r3, [pc, #212] @ (8010a6c ) 8010996: 681b ldr r3, [r3, #0] 8010998: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 801099c: 2b00 cmp r3, #0 801099e: d05d beq.n 8010a5c prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 80109a0: 4b32 ldr r3, [pc, #200] @ (8010a6c ) 80109a2: 6adb ldr r3, [r3, #44] @ 0x2c 80109a4: 091b lsrs r3, r3, #4 80109a6: f003 030f and.w r3, r3, #15 80109aa: 3301 adds r3, #1 80109ac: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 80109ae: 4b2f ldr r3, [pc, #188] @ (8010a6c ) 80109b0: 6adb ldr r3, [r3, #44] @ 0x2c 80109b2: 0b1b lsrs r3, r3, #12 80109b4: f003 030f and.w r3, r3, #15 80109b8: 3302 adds r3, #2 80109ba: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 80109bc: 4a2e ldr r2, [pc, #184] @ (8010a78 ) 80109be: 68fb ldr r3, [r7, #12] 80109c0: fbb2 f3f3 udiv r3, r2, r3 80109c4: 693a ldr r2, [r7, #16] 80109c6: fb02 f303 mul.w r3, r2, r3 80109ca: 005b lsls r3, r3, #1 80109cc: 623b str r3, [r7, #32] break; 80109ce: e045 b.n 8010a5c } #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ case RCC_PERIPHCLK_RTC: { /* Get RCC BDCR configuration ------------------------------------------------------*/ temp_reg = RCC->BDCR; 80109d0: 4b26 ldr r3, [pc, #152] @ (8010a6c ) 80109d2: 6a1b ldr r3, [r3, #32] 80109d4: 60bb str r3, [r7, #8] /* Check if LSE is ready if RTC clock selection is LSE */ if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 80109d6: 68bb ldr r3, [r7, #8] 80109d8: f403 7340 and.w r3, r3, #768 @ 0x300 80109dc: f5b3 7f80 cmp.w r3, #256 @ 0x100 80109e0: d108 bne.n 80109f4 80109e2: 68bb ldr r3, [r7, #8] 80109e4: f003 0302 and.w r3, r3, #2 80109e8: 2b00 cmp r3, #0 80109ea: d003 beq.n 80109f4 { frequency = LSE_VALUE; 80109ec: f44f 4300 mov.w r3, #32768 @ 0x8000 80109f0: 623b str r3, [r7, #32] 80109f2: e01e b.n 8010a32 } /* Check if LSI is ready if RTC clock selection is LSI */ else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 80109f4: 68bb ldr r3, [r7, #8] 80109f6: f403 7340 and.w r3, r3, #768 @ 0x300 80109fa: f5b3 7f00 cmp.w r3, #512 @ 0x200 80109fe: d109 bne.n 8010a14 8010a00: 4b1a ldr r3, [pc, #104] @ (8010a6c ) 8010a02: 6a5b ldr r3, [r3, #36] @ 0x24 8010a04: f003 0302 and.w r3, r3, #2 8010a08: 2b00 cmp r3, #0 8010a0a: d003 beq.n 8010a14 { frequency = LSI_VALUE; 8010a0c: f649 4340 movw r3, #40000 @ 0x9c40 8010a10: 623b str r3, [r7, #32] 8010a12: e00e b.n 8010a32 } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 8010a14: 68bb ldr r3, [r7, #8] 8010a16: f403 7340 and.w r3, r3, #768 @ 0x300 8010a1a: f5b3 7f40 cmp.w r3, #768 @ 0x300 8010a1e: d11f bne.n 8010a60 8010a20: 4b12 ldr r3, [pc, #72] @ (8010a6c ) 8010a22: 681b ldr r3, [r3, #0] 8010a24: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010a28: 2b00 cmp r3, #0 8010a2a: d019 beq.n 8010a60 { frequency = HSE_VALUE / 128U; 8010a2c: 4b15 ldr r3, [pc, #84] @ (8010a84 ) 8010a2e: 623b str r3, [r7, #32] /* Clock not enabled for RTC*/ else { /* nothing to do: frequency already initialized to 0U */ } break; 8010a30: e016 b.n 8010a60 8010a32: e015 b.n 8010a60 } case RCC_PERIPHCLK_ADC: { frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 8010a34: f7ff fd72 bl 801051c 8010a38: 4602 mov r2, r0 8010a3a: 4b0c ldr r3, [pc, #48] @ (8010a6c ) 8010a3c: 685b ldr r3, [r3, #4] 8010a3e: 0b9b lsrs r3, r3, #14 8010a40: f003 0303 and.w r3, r3, #3 8010a44: 3301 adds r3, #1 8010a46: 005b lsls r3, r3, #1 8010a48: fbb2 f3f3 udiv r3, r2, r3 8010a4c: 623b str r3, [r7, #32] break; 8010a4e: e008 b.n 8010a62 } default: { break; 8010a50: bf00 nop 8010a52: e006 b.n 8010a62 break; 8010a54: bf00 nop 8010a56: e004 b.n 8010a62 break; 8010a58: bf00 nop 8010a5a: e002 b.n 8010a62 break; 8010a5c: bf00 nop 8010a5e: e000 b.n 8010a62 break; 8010a60: bf00 nop } } return (frequency); 8010a62: 6a3b ldr r3, [r7, #32] } 8010a64: 4618 mov r0, r3 8010a66: 3728 adds r7, #40 @ 0x28 8010a68: 46bd mov sp, r7 8010a6a: bd80 pop {r7, pc} 8010a6c: 40021000 .word 0x40021000 8010a70: 0801445c .word 0x0801445c 8010a74: 0801446c .word 0x0801446c 8010a78: 017d7840 .word 0x017d7840 8010a7c: 003d0900 .word 0x003d0900 8010a80: aaaaaaab .word 0xaaaaaaab 8010a84: 0002faf0 .word 0x0002faf0 08010a88 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { 8010a88: b580 push {r7, lr} 8010a8a: b084 sub sp, #16 8010a8c: af00 add r7, sp, #0 8010a8e: 6078 str r0, [r7, #4] uint32_t prescaler = 0U; 8010a90: 2300 movs r3, #0 8010a92: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8010a94: 687b ldr r3, [r7, #4] 8010a96: 2b00 cmp r3, #0 8010a98: d101 bne.n 8010a9e { return HAL_ERROR; 8010a9a: 2301 movs r3, #1 8010a9c: e07a b.n 8010b94 { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else if (hrtc->State == HAL_RTC_STATE_RESET) 8010a9e: 687b ldr r3, [r7, #4] 8010aa0: 7c5b ldrb r3, [r3, #17] 8010aa2: b2db uxtb r3, r3 8010aa4: 2b00 cmp r3, #0 8010aa6: d105 bne.n 8010ab4 { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; 8010aa8: 687b ldr r3, [r7, #4] 8010aaa: 2200 movs r2, #0 8010aac: 741a strb r2, [r3, #16] /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); 8010aae: 6878 ldr r0, [r7, #4] 8010ab0: f7fa ff44 bl 800b93c } #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; 8010ab4: 687b ldr r3, [r7, #4] 8010ab6: 2202 movs r2, #2 8010ab8: 745a strb r2, [r3, #17] /* Waiting for synchro */ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 8010aba: 6878 ldr r0, [r7, #4] 8010abc: f000 f870 bl 8010ba0 8010ac0: 4603 mov r3, r0 8010ac2: 2b00 cmp r3, #0 8010ac4: d004 beq.n 8010ad0 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8010ac6: 687b ldr r3, [r7, #4] 8010ac8: 2204 movs r2, #4 8010aca: 745a strb r2, [r3, #17] return HAL_ERROR; 8010acc: 2301 movs r3, #1 8010ace: e061 b.n 8010b94 } /* Set Initialization mode */ if (RTC_EnterInitMode(hrtc) != HAL_OK) 8010ad0: 6878 ldr r0, [r7, #4] 8010ad2: f000 f892 bl 8010bfa 8010ad6: 4603 mov r3, r0 8010ad8: 2b00 cmp r3, #0 8010ada: d004 beq.n 8010ae6 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8010adc: 687b ldr r3, [r7, #4] 8010ade: 2204 movs r2, #4 8010ae0: 745a strb r2, [r3, #17] return HAL_ERROR; 8010ae2: 2301 movs r3, #1 8010ae4: e056 b.n 8010b94 } else { /* Clear Flags Bits */ CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); 8010ae6: 687b ldr r3, [r7, #4] 8010ae8: 681b ldr r3, [r3, #0] 8010aea: 685a ldr r2, [r3, #4] 8010aec: 687b ldr r3, [r7, #4] 8010aee: 681b ldr r3, [r3, #0] 8010af0: f022 0207 bic.w r2, r2, #7 8010af4: 605a str r2, [r3, #4] if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) 8010af6: 687b ldr r3, [r7, #4] 8010af8: 689b ldr r3, [r3, #8] 8010afa: 2b00 cmp r3, #0 8010afc: d005 beq.n 8010b0a { /* Disable the selected Tamper pin */ CLEAR_BIT(BKP->CR, BKP_CR_TPE); 8010afe: 4b27 ldr r3, [pc, #156] @ (8010b9c ) 8010b00: 6b1b ldr r3, [r3, #48] @ 0x30 8010b02: 4a26 ldr r2, [pc, #152] @ (8010b9c ) 8010b04: f023 0301 bic.w r3, r3, #1 8010b08: 6313 str r3, [r2, #48] @ 0x30 } /* Set the signal which will be routed to RTC Tamper pin*/ MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); 8010b0a: 4b24 ldr r3, [pc, #144] @ (8010b9c ) 8010b0c: 6adb ldr r3, [r3, #44] @ 0x2c 8010b0e: f423 7260 bic.w r2, r3, #896 @ 0x380 8010b12: 687b ldr r3, [r7, #4] 8010b14: 689b ldr r3, [r3, #8] 8010b16: 4921 ldr r1, [pc, #132] @ (8010b9c ) 8010b18: 4313 orrs r3, r2 8010b1a: 62cb str r3, [r1, #44] @ 0x2c if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) 8010b1c: 687b ldr r3, [r7, #4] 8010b1e: 685b ldr r3, [r3, #4] 8010b20: f1b3 3fff cmp.w r3, #4294967295 8010b24: d003 beq.n 8010b2e { /* RTC Prescaler provided directly by end-user*/ prescaler = hrtc->Init.AsynchPrediv; 8010b26: 687b ldr r3, [r7, #4] 8010b28: 685b ldr r3, [r3, #4] 8010b2a: 60fb str r3, [r7, #12] 8010b2c: e00e b.n 8010b4c } else { /* RTC Prescaler will be automatically calculated to get 1 second timebase */ /* Get the RTCCLK frequency */ prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); 8010b2e: 2001 movs r0, #1 8010b30: f7ff fe58 bl 80107e4 8010b34: 60f8 str r0, [r7, #12] /* Check that RTC clock is enabled*/ if (prescaler == 0U) 8010b36: 68fb ldr r3, [r7, #12] 8010b38: 2b00 cmp r3, #0 8010b3a: d104 bne.n 8010b46 { /* Should not happen. Frequency is not available*/ hrtc->State = HAL_RTC_STATE_ERROR; 8010b3c: 687b ldr r3, [r7, #4] 8010b3e: 2204 movs r2, #4 8010b40: 745a strb r2, [r3, #17] return HAL_ERROR; 8010b42: 2301 movs r3, #1 8010b44: e026 b.n 8010b94 } else { /* RTC period = RTCCLK/(RTC_PR + 1) */ prescaler = prescaler - 1U; 8010b46: 68fb ldr r3, [r7, #12] 8010b48: 3b01 subs r3, #1 8010b4a: 60fb str r3, [r7, #12] } } /* Configure the RTC_PRLH / RTC_PRLL */ WRITE_REG(hrtc->Instance->PRLH, ((prescaler >> 16U) & RTC_PRLH_PRL)); 8010b4c: 68fb ldr r3, [r7, #12] 8010b4e: 0c1a lsrs r2, r3, #16 8010b50: 687b ldr r3, [r7, #4] 8010b52: 681b ldr r3, [r3, #0] 8010b54: f002 020f and.w r2, r2, #15 8010b58: 609a str r2, [r3, #8] WRITE_REG(hrtc->Instance->PRLL, (prescaler & RTC_PRLL_PRL)); 8010b5a: 687b ldr r3, [r7, #4] 8010b5c: 681b ldr r3, [r3, #0] 8010b5e: 68fa ldr r2, [r7, #12] 8010b60: b292 uxth r2, r2 8010b62: 60da str r2, [r3, #12] /* Wait for synchro */ if (RTC_ExitInitMode(hrtc) != HAL_OK) 8010b64: 6878 ldr r0, [r7, #4] 8010b66: f000 f870 bl 8010c4a 8010b6a: 4603 mov r3, r0 8010b6c: 2b00 cmp r3, #0 8010b6e: d004 beq.n 8010b7a { hrtc->State = HAL_RTC_STATE_ERROR; 8010b70: 687b ldr r3, [r7, #4] 8010b72: 2204 movs r2, #4 8010b74: 745a strb r2, [r3, #17] return HAL_ERROR; 8010b76: 2301 movs r3, #1 8010b78: e00c b.n 8010b94 } /* Initialize date to 1st of January 2000 */ hrtc->DateToUpdate.Year = 0x00U; 8010b7a: 687b ldr r3, [r7, #4] 8010b7c: 2200 movs r2, #0 8010b7e: 73da strb r2, [r3, #15] hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; 8010b80: 687b ldr r3, [r7, #4] 8010b82: 2201 movs r2, #1 8010b84: 735a strb r2, [r3, #13] hrtc->DateToUpdate.Date = 0x01U; 8010b86: 687b ldr r3, [r7, #4] 8010b88: 2201 movs r2, #1 8010b8a: 739a strb r2, [r3, #14] /* Set RTC state */ hrtc->State = HAL_RTC_STATE_READY; 8010b8c: 687b ldr r3, [r7, #4] 8010b8e: 2201 movs r2, #1 8010b90: 745a strb r2, [r3, #17] return HAL_OK; 8010b92: 2300 movs r3, #0 } } 8010b94: 4618 mov r0, r3 8010b96: 3710 adds r7, #16 8010b98: 46bd mov sp, r7 8010b9a: bd80 pop {r7, pc} 8010b9c: 40006c00 .word 0x40006c00 08010ba0 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { 8010ba0: b580 push {r7, lr} 8010ba2: b084 sub sp, #16 8010ba4: af00 add r7, sp, #0 8010ba6: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8010ba8: 2300 movs r3, #0 8010baa: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8010bac: 687b ldr r3, [r7, #4] 8010bae: 2b00 cmp r3, #0 8010bb0: d101 bne.n 8010bb6 { return HAL_ERROR; 8010bb2: 2301 movs r3, #1 8010bb4: e01d b.n 8010bf2 } /* Clear RSF flag */ CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); 8010bb6: 687b ldr r3, [r7, #4] 8010bb8: 681b ldr r3, [r3, #0] 8010bba: 685a ldr r2, [r3, #4] 8010bbc: 687b ldr r3, [r7, #4] 8010bbe: 681b ldr r3, [r3, #0] 8010bc0: f022 0208 bic.w r2, r2, #8 8010bc4: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8010bc6: f7fc fec9 bl 800d95c 8010bca: 60f8 str r0, [r7, #12] /* Wait the registers to be synchronised */ while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8010bcc: e009 b.n 8010be2 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8010bce: f7fc fec5 bl 800d95c 8010bd2: 4602 mov r2, r0 8010bd4: 68fb ldr r3, [r7, #12] 8010bd6: 1ad3 subs r3, r2, r3 8010bd8: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8010bdc: d901 bls.n 8010be2 { return HAL_TIMEOUT; 8010bde: 2303 movs r3, #3 8010be0: e007 b.n 8010bf2 while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8010be2: 687b ldr r3, [r7, #4] 8010be4: 681b ldr r3, [r3, #0] 8010be6: 685b ldr r3, [r3, #4] 8010be8: f003 0308 and.w r3, r3, #8 8010bec: 2b00 cmp r3, #0 8010bee: d0ee beq.n 8010bce } } return HAL_OK; 8010bf0: 2300 movs r3, #0 } 8010bf2: 4618 mov r0, r3 8010bf4: 3710 adds r7, #16 8010bf6: 46bd mov sp, r7 8010bf8: bd80 pop {r7, pc} 08010bfa : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { 8010bfa: b580 push {r7, lr} 8010bfc: b084 sub sp, #16 8010bfe: af00 add r7, sp, #0 8010c00: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8010c02: 2300 movs r3, #0 8010c04: 60fb str r3, [r7, #12] tickstart = HAL_GetTick(); 8010c06: f7fc fea9 bl 800d95c 8010c0a: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8010c0c: e009 b.n 8010c22 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8010c0e: f7fc fea5 bl 800d95c 8010c12: 4602 mov r2, r0 8010c14: 68fb ldr r3, [r7, #12] 8010c16: 1ad3 subs r3, r2, r3 8010c18: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8010c1c: d901 bls.n 8010c22 { return HAL_TIMEOUT; 8010c1e: 2303 movs r3, #3 8010c20: e00f b.n 8010c42 while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8010c22: 687b ldr r3, [r7, #4] 8010c24: 681b ldr r3, [r3, #0] 8010c26: 685b ldr r3, [r3, #4] 8010c28: f003 0320 and.w r3, r3, #32 8010c2c: 2b00 cmp r3, #0 8010c2e: d0ee beq.n 8010c0e } } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 8010c30: 687b ldr r3, [r7, #4] 8010c32: 681b ldr r3, [r3, #0] 8010c34: 685a ldr r2, [r3, #4] 8010c36: 687b ldr r3, [r7, #4] 8010c38: 681b ldr r3, [r3, #0] 8010c3a: f042 0210 orr.w r2, r2, #16 8010c3e: 605a str r2, [r3, #4] return HAL_OK; 8010c40: 2300 movs r3, #0 } 8010c42: 4618 mov r0, r3 8010c44: 3710 adds r7, #16 8010c46: 46bd mov sp, r7 8010c48: bd80 pop {r7, pc} 08010c4a : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) { 8010c4a: b580 push {r7, lr} 8010c4c: b084 sub sp, #16 8010c4e: af00 add r7, sp, #0 8010c50: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8010c52: 2300 movs r3, #0 8010c54: 60fb str r3, [r7, #12] /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 8010c56: 687b ldr r3, [r7, #4] 8010c58: 681b ldr r3, [r3, #0] 8010c5a: 685a ldr r2, [r3, #4] 8010c5c: 687b ldr r3, [r7, #4] 8010c5e: 681b ldr r3, [r3, #0] 8010c60: f022 0210 bic.w r2, r2, #16 8010c64: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8010c66: f7fc fe79 bl 800d95c 8010c6a: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8010c6c: e009 b.n 8010c82 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8010c6e: f7fc fe75 bl 800d95c 8010c72: 4602 mov r2, r0 8010c74: 68fb ldr r3, [r7, #12] 8010c76: 1ad3 subs r3, r2, r3 8010c78: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8010c7c: d901 bls.n 8010c82 { return HAL_TIMEOUT; 8010c7e: 2303 movs r3, #3 8010c80: e007 b.n 8010c92 while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8010c82: 687b ldr r3, [r7, #4] 8010c84: 681b ldr r3, [r3, #0] 8010c86: 685b ldr r3, [r3, #4] 8010c88: f003 0320 and.w r3, r3, #32 8010c8c: 2b00 cmp r3, #0 8010c8e: d0ee beq.n 8010c6e } } return HAL_OK; 8010c90: 2300 movs r3, #0 } 8010c92: 4618 mov r0, r3 8010c94: 3710 adds r7, #16 8010c96: 46bd mov sp, r7 8010c98: bd80 pop {r7, pc} 08010c9a : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8010c9a: b580 push {r7, lr} 8010c9c: b082 sub sp, #8 8010c9e: af00 add r7, sp, #0 8010ca0: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8010ca2: 687b ldr r3, [r7, #4] 8010ca4: 2b00 cmp r3, #0 8010ca6: d101 bne.n 8010cac { return HAL_ERROR; 8010ca8: 2301 movs r3, #1 8010caa: e041 b.n 8010d30 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8010cac: 687b ldr r3, [r7, #4] 8010cae: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8010cb2: b2db uxtb r3, r3 8010cb4: 2b00 cmp r3, #0 8010cb6: d106 bne.n 8010cc6 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8010cb8: 687b ldr r3, [r7, #4] 8010cba: 2200 movs r2, #0 8010cbc: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8010cc0: 6878 ldr r0, [r7, #4] 8010cc2: f7fc fb3b bl 800d33c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8010cc6: 687b ldr r3, [r7, #4] 8010cc8: 2202 movs r2, #2 8010cca: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8010cce: 687b ldr r3, [r7, #4] 8010cd0: 681a ldr r2, [r3, #0] 8010cd2: 687b ldr r3, [r7, #4] 8010cd4: 3304 adds r3, #4 8010cd6: 4619 mov r1, r3 8010cd8: 4610 mov r0, r2 8010cda: f000 fcc3 bl 8011664 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8010cde: 687b ldr r3, [r7, #4] 8010ce0: 2201 movs r2, #1 8010ce2: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8010ce6: 687b ldr r3, [r7, #4] 8010ce8: 2201 movs r2, #1 8010cea: f883 203e strb.w r2, [r3, #62] @ 0x3e 8010cee: 687b ldr r3, [r7, #4] 8010cf0: 2201 movs r2, #1 8010cf2: f883 203f strb.w r2, [r3, #63] @ 0x3f 8010cf6: 687b ldr r3, [r7, #4] 8010cf8: 2201 movs r2, #1 8010cfa: f883 2040 strb.w r2, [r3, #64] @ 0x40 8010cfe: 687b ldr r3, [r7, #4] 8010d00: 2201 movs r2, #1 8010d02: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8010d06: 687b ldr r3, [r7, #4] 8010d08: 2201 movs r2, #1 8010d0a: f883 2042 strb.w r2, [r3, #66] @ 0x42 8010d0e: 687b ldr r3, [r7, #4] 8010d10: 2201 movs r2, #1 8010d12: f883 2043 strb.w r2, [r3, #67] @ 0x43 8010d16: 687b ldr r3, [r7, #4] 8010d18: 2201 movs r2, #1 8010d1a: f883 2044 strb.w r2, [r3, #68] @ 0x44 8010d1e: 687b ldr r3, [r7, #4] 8010d20: 2201 movs r2, #1 8010d22: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8010d26: 687b ldr r3, [r7, #4] 8010d28: 2201 movs r2, #1 8010d2a: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8010d2e: 2300 movs r3, #0 } 8010d30: 4618 mov r0, r3 8010d32: 3708 adds r7, #8 8010d34: 46bd mov sp, r7 8010d36: bd80 pop {r7, pc} 08010d38 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { 8010d38: b580 push {r7, lr} 8010d3a: b084 sub sp, #16 8010d3c: af00 add r7, sp, #0 8010d3e: 6078 str r0, [r7, #4] 8010d40: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8010d42: 2300 movs r3, #0 8010d44: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 8010d46: 683b ldr r3, [r7, #0] 8010d48: 2b00 cmp r3, #0 8010d4a: d109 bne.n 8010d60 8010d4c: 687b ldr r3, [r7, #4] 8010d4e: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8010d52: b2db uxtb r3, r3 8010d54: 2b01 cmp r3, #1 8010d56: bf14 ite ne 8010d58: 2301 movne r3, #1 8010d5a: 2300 moveq r3, #0 8010d5c: b2db uxtb r3, r3 8010d5e: e022 b.n 8010da6 8010d60: 683b ldr r3, [r7, #0] 8010d62: 2b04 cmp r3, #4 8010d64: d109 bne.n 8010d7a 8010d66: 687b ldr r3, [r7, #4] 8010d68: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8010d6c: b2db uxtb r3, r3 8010d6e: 2b01 cmp r3, #1 8010d70: bf14 ite ne 8010d72: 2301 movne r3, #1 8010d74: 2300 moveq r3, #0 8010d76: b2db uxtb r3, r3 8010d78: e015 b.n 8010da6 8010d7a: 683b ldr r3, [r7, #0] 8010d7c: 2b08 cmp r3, #8 8010d7e: d109 bne.n 8010d94 8010d80: 687b ldr r3, [r7, #4] 8010d82: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8010d86: b2db uxtb r3, r3 8010d88: 2b01 cmp r3, #1 8010d8a: bf14 ite ne 8010d8c: 2301 movne r3, #1 8010d8e: 2300 moveq r3, #0 8010d90: b2db uxtb r3, r3 8010d92: e008 b.n 8010da6 8010d94: 687b ldr r3, [r7, #4] 8010d96: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8010d9a: b2db uxtb r3, r3 8010d9c: 2b01 cmp r3, #1 8010d9e: bf14 ite ne 8010da0: 2301 movne r3, #1 8010da2: 2300 moveq r3, #0 8010da4: b2db uxtb r3, r3 8010da6: 2b00 cmp r3, #0 8010da8: d001 beq.n 8010dae { return HAL_ERROR; 8010daa: 2301 movs r3, #1 8010dac: e0ae b.n 8010f0c } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8010dae: 683b ldr r3, [r7, #0] 8010db0: 2b00 cmp r3, #0 8010db2: d104 bne.n 8010dbe 8010db4: 687b ldr r3, [r7, #4] 8010db6: 2202 movs r2, #2 8010db8: f883 203e strb.w r2, [r3, #62] @ 0x3e 8010dbc: e013 b.n 8010de6 8010dbe: 683b ldr r3, [r7, #0] 8010dc0: 2b04 cmp r3, #4 8010dc2: d104 bne.n 8010dce 8010dc4: 687b ldr r3, [r7, #4] 8010dc6: 2202 movs r2, #2 8010dc8: f883 203f strb.w r2, [r3, #63] @ 0x3f 8010dcc: e00b b.n 8010de6 8010dce: 683b ldr r3, [r7, #0] 8010dd0: 2b08 cmp r3, #8 8010dd2: d104 bne.n 8010dde 8010dd4: 687b ldr r3, [r7, #4] 8010dd6: 2202 movs r2, #2 8010dd8: f883 2040 strb.w r2, [r3, #64] @ 0x40 8010ddc: e003 b.n 8010de6 8010dde: 687b ldr r3, [r7, #4] 8010de0: 2202 movs r2, #2 8010de2: f883 2041 strb.w r2, [r3, #65] @ 0x41 switch (Channel) 8010de6: 683b ldr r3, [r7, #0] 8010de8: 2b0c cmp r3, #12 8010dea: d841 bhi.n 8010e70 8010dec: a201 add r2, pc, #4 @ (adr r2, 8010df4 ) 8010dee: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8010df2: bf00 nop 8010df4: 08010e29 .word 0x08010e29 8010df8: 08010e71 .word 0x08010e71 8010dfc: 08010e71 .word 0x08010e71 8010e00: 08010e71 .word 0x08010e71 8010e04: 08010e3b .word 0x08010e3b 8010e08: 08010e71 .word 0x08010e71 8010e0c: 08010e71 .word 0x08010e71 8010e10: 08010e71 .word 0x08010e71 8010e14: 08010e4d .word 0x08010e4d 8010e18: 08010e71 .word 0x08010e71 8010e1c: 08010e71 .word 0x08010e71 8010e20: 08010e71 .word 0x08010e71 8010e24: 08010e5f .word 0x08010e5f { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 8010e28: 687b ldr r3, [r7, #4] 8010e2a: 681b ldr r3, [r3, #0] 8010e2c: 68da ldr r2, [r3, #12] 8010e2e: 687b ldr r3, [r7, #4] 8010e30: 681b ldr r3, [r3, #0] 8010e32: f042 0202 orr.w r2, r2, #2 8010e36: 60da str r2, [r3, #12] break; 8010e38: e01d b.n 8010e76 } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 8010e3a: 687b ldr r3, [r7, #4] 8010e3c: 681b ldr r3, [r3, #0] 8010e3e: 68da ldr r2, [r3, #12] 8010e40: 687b ldr r3, [r7, #4] 8010e42: 681b ldr r3, [r3, #0] 8010e44: f042 0204 orr.w r2, r2, #4 8010e48: 60da str r2, [r3, #12] break; 8010e4a: e014 b.n 8010e76 } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 8010e4c: 687b ldr r3, [r7, #4] 8010e4e: 681b ldr r3, [r3, #0] 8010e50: 68da ldr r2, [r3, #12] 8010e52: 687b ldr r3, [r7, #4] 8010e54: 681b ldr r3, [r3, #0] 8010e56: f042 0208 orr.w r2, r2, #8 8010e5a: 60da str r2, [r3, #12] break; 8010e5c: e00b b.n 8010e76 } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 8010e5e: 687b ldr r3, [r7, #4] 8010e60: 681b ldr r3, [r3, #0] 8010e62: 68da ldr r2, [r3, #12] 8010e64: 687b ldr r3, [r7, #4] 8010e66: 681b ldr r3, [r3, #0] 8010e68: f042 0210 orr.w r2, r2, #16 8010e6c: 60da str r2, [r3, #12] break; 8010e6e: e002 b.n 8010e76 } default: status = HAL_ERROR; 8010e70: 2301 movs r3, #1 8010e72: 73fb strb r3, [r7, #15] break; 8010e74: bf00 nop } if (status == HAL_OK) 8010e76: 7bfb ldrb r3, [r7, #15] 8010e78: 2b00 cmp r3, #0 8010e7a: d146 bne.n 8010f0a { /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 8010e7c: 687b ldr r3, [r7, #4] 8010e7e: 681b ldr r3, [r3, #0] 8010e80: 2201 movs r2, #1 8010e82: 6839 ldr r1, [r7, #0] 8010e84: 4618 mov r0, r3 8010e86: f000 fe83 bl 8011b90 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8010e8a: 687b ldr r3, [r7, #4] 8010e8c: 681b ldr r3, [r3, #0] 8010e8e: 4a21 ldr r2, [pc, #132] @ (8010f14 ) 8010e90: 4293 cmp r3, r2 8010e92: d107 bne.n 8010ea4 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8010e94: 687b ldr r3, [r7, #4] 8010e96: 681b ldr r3, [r3, #0] 8010e98: 6c5a ldr r2, [r3, #68] @ 0x44 8010e9a: 687b ldr r3, [r7, #4] 8010e9c: 681b ldr r3, [r3, #0] 8010e9e: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8010ea2: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8010ea4: 687b ldr r3, [r7, #4] 8010ea6: 681b ldr r3, [r3, #0] 8010ea8: 4a1a ldr r2, [pc, #104] @ (8010f14 ) 8010eaa: 4293 cmp r3, r2 8010eac: d013 beq.n 8010ed6 8010eae: 687b ldr r3, [r7, #4] 8010eb0: 681b ldr r3, [r3, #0] 8010eb2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8010eb6: d00e beq.n 8010ed6 8010eb8: 687b ldr r3, [r7, #4] 8010eba: 681b ldr r3, [r3, #0] 8010ebc: 4a16 ldr r2, [pc, #88] @ (8010f18 ) 8010ebe: 4293 cmp r3, r2 8010ec0: d009 beq.n 8010ed6 8010ec2: 687b ldr r3, [r7, #4] 8010ec4: 681b ldr r3, [r3, #0] 8010ec6: 4a15 ldr r2, [pc, #84] @ (8010f1c ) 8010ec8: 4293 cmp r3, r2 8010eca: d004 beq.n 8010ed6 8010ecc: 687b ldr r3, [r7, #4] 8010ece: 681b ldr r3, [r3, #0] 8010ed0: 4a13 ldr r2, [pc, #76] @ (8010f20 ) 8010ed2: 4293 cmp r3, r2 8010ed4: d111 bne.n 8010efa { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8010ed6: 687b ldr r3, [r7, #4] 8010ed8: 681b ldr r3, [r3, #0] 8010eda: 689b ldr r3, [r3, #8] 8010edc: f003 0307 and.w r3, r3, #7 8010ee0: 60bb str r3, [r7, #8] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8010ee2: 68bb ldr r3, [r7, #8] 8010ee4: 2b06 cmp r3, #6 8010ee6: d010 beq.n 8010f0a { __HAL_TIM_ENABLE(htim); 8010ee8: 687b ldr r3, [r7, #4] 8010eea: 681b ldr r3, [r3, #0] 8010eec: 681a ldr r2, [r3, #0] 8010eee: 687b ldr r3, [r7, #4] 8010ef0: 681b ldr r3, [r3, #0] 8010ef2: f042 0201 orr.w r2, r2, #1 8010ef6: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8010ef8: e007 b.n 8010f0a } } else { __HAL_TIM_ENABLE(htim); 8010efa: 687b ldr r3, [r7, #4] 8010efc: 681b ldr r3, [r3, #0] 8010efe: 681a ldr r2, [r3, #0] 8010f00: 687b ldr r3, [r7, #4] 8010f02: 681b ldr r3, [r3, #0] 8010f04: f042 0201 orr.w r2, r2, #1 8010f08: 601a str r2, [r3, #0] } } /* Return function status */ return status; 8010f0a: 7bfb ldrb r3, [r7, #15] } 8010f0c: 4618 mov r0, r3 8010f0e: 3710 adds r7, #16 8010f10: 46bd mov sp, r7 8010f12: bd80 pop {r7, pc} 8010f14: 40012c00 .word 0x40012c00 8010f18: 40000400 .word 0x40000400 8010f1c: 40000800 .word 0x40000800 8010f20: 40000c00 .word 0x40000c00 08010f24 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 8010f24: b580 push {r7, lr} 8010f26: b082 sub sp, #8 8010f28: af00 add r7, sp, #0 8010f2a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8010f2c: 687b ldr r3, [r7, #4] 8010f2e: 2b00 cmp r3, #0 8010f30: d101 bne.n 8010f36 { return HAL_ERROR; 8010f32: 2301 movs r3, #1 8010f34: e041 b.n 8010fba assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8010f36: 687b ldr r3, [r7, #4] 8010f38: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8010f3c: b2db uxtb r3, r3 8010f3e: 2b00 cmp r3, #0 8010f40: d106 bne.n 8010f50 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8010f42: 687b ldr r3, [r7, #4] 8010f44: 2200 movs r2, #0 8010f46: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 8010f4a: 6878 ldr r0, [r7, #4] 8010f4c: f000 f839 bl 8010fc2 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8010f50: 687b ldr r3, [r7, #4] 8010f52: 2202 movs r2, #2 8010f54: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8010f58: 687b ldr r3, [r7, #4] 8010f5a: 681a ldr r2, [r3, #0] 8010f5c: 687b ldr r3, [r7, #4] 8010f5e: 3304 adds r3, #4 8010f60: 4619 mov r1, r3 8010f62: 4610 mov r0, r2 8010f64: f000 fb7e bl 8011664 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8010f68: 687b ldr r3, [r7, #4] 8010f6a: 2201 movs r2, #1 8010f6c: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8010f70: 687b ldr r3, [r7, #4] 8010f72: 2201 movs r2, #1 8010f74: f883 203e strb.w r2, [r3, #62] @ 0x3e 8010f78: 687b ldr r3, [r7, #4] 8010f7a: 2201 movs r2, #1 8010f7c: f883 203f strb.w r2, [r3, #63] @ 0x3f 8010f80: 687b ldr r3, [r7, #4] 8010f82: 2201 movs r2, #1 8010f84: f883 2040 strb.w r2, [r3, #64] @ 0x40 8010f88: 687b ldr r3, [r7, #4] 8010f8a: 2201 movs r2, #1 8010f8c: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8010f90: 687b ldr r3, [r7, #4] 8010f92: 2201 movs r2, #1 8010f94: f883 2042 strb.w r2, [r3, #66] @ 0x42 8010f98: 687b ldr r3, [r7, #4] 8010f9a: 2201 movs r2, #1 8010f9c: f883 2043 strb.w r2, [r3, #67] @ 0x43 8010fa0: 687b ldr r3, [r7, #4] 8010fa2: 2201 movs r2, #1 8010fa4: f883 2044 strb.w r2, [r3, #68] @ 0x44 8010fa8: 687b ldr r3, [r7, #4] 8010faa: 2201 movs r2, #1 8010fac: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8010fb0: 687b ldr r3, [r7, #4] 8010fb2: 2201 movs r2, #1 8010fb4: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8010fb8: 2300 movs r3, #0 } 8010fba: 4618 mov r0, r3 8010fbc: 3708 adds r7, #8 8010fbe: 46bd mov sp, r7 8010fc0: bd80 pop {r7, pc} 08010fc2 : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 8010fc2: b480 push {r7} 8010fc4: b083 sub sp, #12 8010fc6: af00 add r7, sp, #0 8010fc8: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 8010fca: bf00 nop 8010fcc: 370c adds r7, #12 8010fce: 46bd mov sp, r7 8010fd0: bc80 pop {r7} 8010fd2: 4770 bx lr 08010fd4 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8010fd4: b580 push {r7, lr} 8010fd6: b084 sub sp, #16 8010fd8: af00 add r7, sp, #0 8010fda: 6078 str r0, [r7, #4] 8010fdc: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 8010fde: 683b ldr r3, [r7, #0] 8010fe0: 2b00 cmp r3, #0 8010fe2: d109 bne.n 8010ff8 8010fe4: 687b ldr r3, [r7, #4] 8010fe6: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8010fea: b2db uxtb r3, r3 8010fec: 2b01 cmp r3, #1 8010fee: bf14 ite ne 8010ff0: 2301 movne r3, #1 8010ff2: 2300 moveq r3, #0 8010ff4: b2db uxtb r3, r3 8010ff6: e022 b.n 801103e 8010ff8: 683b ldr r3, [r7, #0] 8010ffa: 2b04 cmp r3, #4 8010ffc: d109 bne.n 8011012 8010ffe: 687b ldr r3, [r7, #4] 8011000: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8011004: b2db uxtb r3, r3 8011006: 2b01 cmp r3, #1 8011008: bf14 ite ne 801100a: 2301 movne r3, #1 801100c: 2300 moveq r3, #0 801100e: b2db uxtb r3, r3 8011010: e015 b.n 801103e 8011012: 683b ldr r3, [r7, #0] 8011014: 2b08 cmp r3, #8 8011016: d109 bne.n 801102c 8011018: 687b ldr r3, [r7, #4] 801101a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 801101e: b2db uxtb r3, r3 8011020: 2b01 cmp r3, #1 8011022: bf14 ite ne 8011024: 2301 movne r3, #1 8011026: 2300 moveq r3, #0 8011028: b2db uxtb r3, r3 801102a: e008 b.n 801103e 801102c: 687b ldr r3, [r7, #4] 801102e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011032: b2db uxtb r3, r3 8011034: 2b01 cmp r3, #1 8011036: bf14 ite ne 8011038: 2301 movne r3, #1 801103a: 2300 moveq r3, #0 801103c: b2db uxtb r3, r3 801103e: 2b00 cmp r3, #0 8011040: d001 beq.n 8011046 { return HAL_ERROR; 8011042: 2301 movs r3, #1 8011044: e063 b.n 801110e } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8011046: 683b ldr r3, [r7, #0] 8011048: 2b00 cmp r3, #0 801104a: d104 bne.n 8011056 801104c: 687b ldr r3, [r7, #4] 801104e: 2202 movs r2, #2 8011050: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011054: e013 b.n 801107e 8011056: 683b ldr r3, [r7, #0] 8011058: 2b04 cmp r3, #4 801105a: d104 bne.n 8011066 801105c: 687b ldr r3, [r7, #4] 801105e: 2202 movs r2, #2 8011060: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011064: e00b b.n 801107e 8011066: 683b ldr r3, [r7, #0] 8011068: 2b08 cmp r3, #8 801106a: d104 bne.n 8011076 801106c: 687b ldr r3, [r7, #4] 801106e: 2202 movs r2, #2 8011070: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011074: e003 b.n 801107e 8011076: 687b ldr r3, [r7, #4] 8011078: 2202 movs r2, #2 801107a: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 801107e: 687b ldr r3, [r7, #4] 8011080: 681b ldr r3, [r3, #0] 8011082: 2201 movs r2, #1 8011084: 6839 ldr r1, [r7, #0] 8011086: 4618 mov r0, r3 8011088: f000 fd82 bl 8011b90 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 801108c: 687b ldr r3, [r7, #4] 801108e: 681b ldr r3, [r3, #0] 8011090: 4a21 ldr r2, [pc, #132] @ (8011118 ) 8011092: 4293 cmp r3, r2 8011094: d107 bne.n 80110a6 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8011096: 687b ldr r3, [r7, #4] 8011098: 681b ldr r3, [r3, #0] 801109a: 6c5a ldr r2, [r3, #68] @ 0x44 801109c: 687b ldr r3, [r7, #4] 801109e: 681b ldr r3, [r3, #0] 80110a0: f442 4200 orr.w r2, r2, #32768 @ 0x8000 80110a4: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80110a6: 687b ldr r3, [r7, #4] 80110a8: 681b ldr r3, [r3, #0] 80110aa: 4a1b ldr r2, [pc, #108] @ (8011118 ) 80110ac: 4293 cmp r3, r2 80110ae: d013 beq.n 80110d8 80110b0: 687b ldr r3, [r7, #4] 80110b2: 681b ldr r3, [r3, #0] 80110b4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80110b8: d00e beq.n 80110d8 80110ba: 687b ldr r3, [r7, #4] 80110bc: 681b ldr r3, [r3, #0] 80110be: 4a17 ldr r2, [pc, #92] @ (801111c ) 80110c0: 4293 cmp r3, r2 80110c2: d009 beq.n 80110d8 80110c4: 687b ldr r3, [r7, #4] 80110c6: 681b ldr r3, [r3, #0] 80110c8: 4a15 ldr r2, [pc, #84] @ (8011120 ) 80110ca: 4293 cmp r3, r2 80110cc: d004 beq.n 80110d8 80110ce: 687b ldr r3, [r7, #4] 80110d0: 681b ldr r3, [r3, #0] 80110d2: 4a14 ldr r2, [pc, #80] @ (8011124 ) 80110d4: 4293 cmp r3, r2 80110d6: d111 bne.n 80110fc { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 80110d8: 687b ldr r3, [r7, #4] 80110da: 681b ldr r3, [r3, #0] 80110dc: 689b ldr r3, [r3, #8] 80110de: f003 0307 and.w r3, r3, #7 80110e2: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80110e4: 68fb ldr r3, [r7, #12] 80110e6: 2b06 cmp r3, #6 80110e8: d010 beq.n 801110c { __HAL_TIM_ENABLE(htim); 80110ea: 687b ldr r3, [r7, #4] 80110ec: 681b ldr r3, [r3, #0] 80110ee: 681a ldr r2, [r3, #0] 80110f0: 687b ldr r3, [r7, #4] 80110f2: 681b ldr r3, [r3, #0] 80110f4: f042 0201 orr.w r2, r2, #1 80110f8: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80110fa: e007 b.n 801110c } } else { __HAL_TIM_ENABLE(htim); 80110fc: 687b ldr r3, [r7, #4] 80110fe: 681b ldr r3, [r3, #0] 8011100: 681a ldr r2, [r3, #0] 8011102: 687b ldr r3, [r7, #4] 8011104: 681b ldr r3, [r3, #0] 8011106: f042 0201 orr.w r2, r2, #1 801110a: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 801110c: 2300 movs r3, #0 } 801110e: 4618 mov r0, r3 8011110: 3710 adds r7, #16 8011112: 46bd mov sp, r7 8011114: bd80 pop {r7, pc} 8011116: bf00 nop 8011118: 40012c00 .word 0x40012c00 801111c: 40000400 .word 0x40000400 8011120: 40000800 .word 0x40000800 8011124: 40000c00 .word 0x40000c00 08011128 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8011128: b580 push {r7, lr} 801112a: b084 sub sp, #16 801112c: af00 add r7, sp, #0 801112e: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 8011130: 687b ldr r3, [r7, #4] 8011132: 681b ldr r3, [r3, #0] 8011134: 68db ldr r3, [r3, #12] 8011136: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 8011138: 687b ldr r3, [r7, #4] 801113a: 681b ldr r3, [r3, #0] 801113c: 691b ldr r3, [r3, #16] 801113e: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 8011140: 68bb ldr r3, [r7, #8] 8011142: f003 0302 and.w r3, r3, #2 8011146: 2b00 cmp r3, #0 8011148: d020 beq.n 801118c { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 801114a: 68fb ldr r3, [r7, #12] 801114c: f003 0302 and.w r3, r3, #2 8011150: 2b00 cmp r3, #0 8011152: d01b beq.n 801118c { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 8011154: 687b ldr r3, [r7, #4] 8011156: 681b ldr r3, [r3, #0] 8011158: f06f 0202 mvn.w r2, #2 801115c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 801115e: 687b ldr r3, [r7, #4] 8011160: 2201 movs r2, #1 8011162: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8011164: 687b ldr r3, [r7, #4] 8011166: 681b ldr r3, [r3, #0] 8011168: 699b ldr r3, [r3, #24] 801116a: f003 0303 and.w r3, r3, #3 801116e: 2b00 cmp r3, #0 8011170: d003 beq.n 801117a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8011172: 6878 ldr r0, [r7, #4] 8011174: f000 fa5a bl 801162c 8011178: e005 b.n 8011186 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 801117a: 6878 ldr r0, [r7, #4] 801117c: f7f9 f83e bl 800a1fc HAL_TIM_PWM_PulseFinishedCallback(htim); 8011180: 6878 ldr r0, [r7, #4] 8011182: f000 fa5c bl 801163e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8011186: 687b ldr r3, [r7, #4] 8011188: 2200 movs r2, #0 801118a: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 801118c: 68bb ldr r3, [r7, #8] 801118e: f003 0304 and.w r3, r3, #4 8011192: 2b00 cmp r3, #0 8011194: d020 beq.n 80111d8 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 8011196: 68fb ldr r3, [r7, #12] 8011198: f003 0304 and.w r3, r3, #4 801119c: 2b00 cmp r3, #0 801119e: d01b beq.n 80111d8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 80111a0: 687b ldr r3, [r7, #4] 80111a2: 681b ldr r3, [r3, #0] 80111a4: f06f 0204 mvn.w r2, #4 80111a8: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 80111aa: 687b ldr r3, [r7, #4] 80111ac: 2202 movs r2, #2 80111ae: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 80111b0: 687b ldr r3, [r7, #4] 80111b2: 681b ldr r3, [r3, #0] 80111b4: 699b ldr r3, [r3, #24] 80111b6: f403 7340 and.w r3, r3, #768 @ 0x300 80111ba: 2b00 cmp r3, #0 80111bc: d003 beq.n 80111c6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80111be: 6878 ldr r0, [r7, #4] 80111c0: f000 fa34 bl 801162c 80111c4: e005 b.n 80111d2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80111c6: 6878 ldr r0, [r7, #4] 80111c8: f7f9 f818 bl 800a1fc HAL_TIM_PWM_PulseFinishedCallback(htim); 80111cc: 6878 ldr r0, [r7, #4] 80111ce: f000 fa36 bl 801163e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80111d2: 687b ldr r3, [r7, #4] 80111d4: 2200 movs r2, #0 80111d6: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 80111d8: 68bb ldr r3, [r7, #8] 80111da: f003 0308 and.w r3, r3, #8 80111de: 2b00 cmp r3, #0 80111e0: d020 beq.n 8011224 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 80111e2: 68fb ldr r3, [r7, #12] 80111e4: f003 0308 and.w r3, r3, #8 80111e8: 2b00 cmp r3, #0 80111ea: d01b beq.n 8011224 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 80111ec: 687b ldr r3, [r7, #4] 80111ee: 681b ldr r3, [r3, #0] 80111f0: f06f 0208 mvn.w r2, #8 80111f4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 80111f6: 687b ldr r3, [r7, #4] 80111f8: 2204 movs r2, #4 80111fa: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 80111fc: 687b ldr r3, [r7, #4] 80111fe: 681b ldr r3, [r3, #0] 8011200: 69db ldr r3, [r3, #28] 8011202: f003 0303 and.w r3, r3, #3 8011206: 2b00 cmp r3, #0 8011208: d003 beq.n 8011212 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 801120a: 6878 ldr r0, [r7, #4] 801120c: f000 fa0e bl 801162c 8011210: e005 b.n 801121e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8011212: 6878 ldr r0, [r7, #4] 8011214: f7f8 fff2 bl 800a1fc HAL_TIM_PWM_PulseFinishedCallback(htim); 8011218: 6878 ldr r0, [r7, #4] 801121a: f000 fa10 bl 801163e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 801121e: 687b ldr r3, [r7, #4] 8011220: 2200 movs r2, #0 8011222: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 8011224: 68bb ldr r3, [r7, #8] 8011226: f003 0310 and.w r3, r3, #16 801122a: 2b00 cmp r3, #0 801122c: d020 beq.n 8011270 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 801122e: 68fb ldr r3, [r7, #12] 8011230: f003 0310 and.w r3, r3, #16 8011234: 2b00 cmp r3, #0 8011236: d01b beq.n 8011270 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 8011238: 687b ldr r3, [r7, #4] 801123a: 681b ldr r3, [r3, #0] 801123c: f06f 0210 mvn.w r2, #16 8011240: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8011242: 687b ldr r3, [r7, #4] 8011244: 2208 movs r2, #8 8011246: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8011248: 687b ldr r3, [r7, #4] 801124a: 681b ldr r3, [r3, #0] 801124c: 69db ldr r3, [r3, #28] 801124e: f403 7340 and.w r3, r3, #768 @ 0x300 8011252: 2b00 cmp r3, #0 8011254: d003 beq.n 801125e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8011256: 6878 ldr r0, [r7, #4] 8011258: f000 f9e8 bl 801162c 801125c: e005 b.n 801126a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 801125e: 6878 ldr r0, [r7, #4] 8011260: f7f8 ffcc bl 800a1fc HAL_TIM_PWM_PulseFinishedCallback(htim); 8011264: 6878 ldr r0, [r7, #4] 8011266: f000 f9ea bl 801163e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 801126a: 687b ldr r3, [r7, #4] 801126c: 2200 movs r2, #0 801126e: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 8011270: 68bb ldr r3, [r7, #8] 8011272: f003 0301 and.w r3, r3, #1 8011276: 2b00 cmp r3, #0 8011278: d00c beq.n 8011294 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 801127a: 68fb ldr r3, [r7, #12] 801127c: f003 0301 and.w r3, r3, #1 8011280: 2b00 cmp r3, #0 8011282: d007 beq.n 8011294 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 8011284: 687b ldr r3, [r7, #4] 8011286: 681b ldr r3, [r3, #0] 8011288: f06f 0201 mvn.w r2, #1 801128c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 801128e: 6878 ldr r0, [r7, #4] 8011290: f000 f9c3 bl 801161a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) 8011294: 68bb ldr r3, [r7, #8] 8011296: f003 0380 and.w r3, r3, #128 @ 0x80 801129a: 2b00 cmp r3, #0 801129c: d00c beq.n 80112b8 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 801129e: 68fb ldr r3, [r7, #12] 80112a0: f003 0380 and.w r3, r3, #128 @ 0x80 80112a4: 2b00 cmp r3, #0 80112a6: d007 beq.n 80112b8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); 80112a8: 687b ldr r3, [r7, #4] 80112aa: 681b ldr r3, [r3, #0] 80112ac: f06f 0280 mvn.w r2, #128 @ 0x80 80112b0: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 80112b2: 6878 ldr r0, [r7, #4] 80112b4: f000 fcff bl 8011cb6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 80112b8: 68bb ldr r3, [r7, #8] 80112ba: f003 0340 and.w r3, r3, #64 @ 0x40 80112be: 2b00 cmp r3, #0 80112c0: d00c beq.n 80112dc { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 80112c2: 68fb ldr r3, [r7, #12] 80112c4: f003 0340 and.w r3, r3, #64 @ 0x40 80112c8: 2b00 cmp r3, #0 80112ca: d007 beq.n 80112dc { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 80112cc: 687b ldr r3, [r7, #4] 80112ce: 681b ldr r3, [r3, #0] 80112d0: f06f 0240 mvn.w r2, #64 @ 0x40 80112d4: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 80112d6: 6878 ldr r0, [r7, #4] 80112d8: f000 f9ba bl 8011650 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 80112dc: 68bb ldr r3, [r7, #8] 80112de: f003 0320 and.w r3, r3, #32 80112e2: 2b00 cmp r3, #0 80112e4: d00c beq.n 8011300 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 80112e6: 68fb ldr r3, [r7, #12] 80112e8: f003 0320 and.w r3, r3, #32 80112ec: 2b00 cmp r3, #0 80112ee: d007 beq.n 8011300 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 80112f0: 687b ldr r3, [r7, #4] 80112f2: 681b ldr r3, [r3, #0] 80112f4: f06f 0220 mvn.w r2, #32 80112f8: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 80112fa: 6878 ldr r0, [r7, #4] 80112fc: f000 fcd2 bl 8011ca4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8011300: bf00 nop 8011302: 3710 adds r7, #16 8011304: 46bd mov sp, r7 8011306: bd80 pop {r7, pc} 08011308 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8011308: b580 push {r7, lr} 801130a: b086 sub sp, #24 801130c: af00 add r7, sp, #0 801130e: 60f8 str r0, [r7, #12] 8011310: 60b9 str r1, [r7, #8] 8011312: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8011314: 2300 movs r3, #0 8011316: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 8011318: 68fb ldr r3, [r7, #12] 801131a: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 801131e: 2b01 cmp r3, #1 8011320: d101 bne.n 8011326 8011322: 2302 movs r3, #2 8011324: e0ae b.n 8011484 8011326: 68fb ldr r3, [r7, #12] 8011328: 2201 movs r2, #1 801132a: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 801132e: 687b ldr r3, [r7, #4] 8011330: 2b0c cmp r3, #12 8011332: f200 809f bhi.w 8011474 8011336: a201 add r2, pc, #4 @ (adr r2, 801133c ) 8011338: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801133c: 08011371 .word 0x08011371 8011340: 08011475 .word 0x08011475 8011344: 08011475 .word 0x08011475 8011348: 08011475 .word 0x08011475 801134c: 080113b1 .word 0x080113b1 8011350: 08011475 .word 0x08011475 8011354: 08011475 .word 0x08011475 8011358: 08011475 .word 0x08011475 801135c: 080113f3 .word 0x080113f3 8011360: 08011475 .word 0x08011475 8011364: 08011475 .word 0x08011475 8011368: 08011475 .word 0x08011475 801136c: 08011433 .word 0x08011433 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8011370: 68fb ldr r3, [r7, #12] 8011372: 681b ldr r3, [r3, #0] 8011374: 68b9 ldr r1, [r7, #8] 8011376: 4618 mov r0, r3 8011378: f000 f9ec bl 8011754 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 801137c: 68fb ldr r3, [r7, #12] 801137e: 681b ldr r3, [r3, #0] 8011380: 699a ldr r2, [r3, #24] 8011382: 68fb ldr r3, [r7, #12] 8011384: 681b ldr r3, [r3, #0] 8011386: f042 0208 orr.w r2, r2, #8 801138a: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 801138c: 68fb ldr r3, [r7, #12] 801138e: 681b ldr r3, [r3, #0] 8011390: 699a ldr r2, [r3, #24] 8011392: 68fb ldr r3, [r7, #12] 8011394: 681b ldr r3, [r3, #0] 8011396: f022 0204 bic.w r2, r2, #4 801139a: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 801139c: 68fb ldr r3, [r7, #12] 801139e: 681b ldr r3, [r3, #0] 80113a0: 6999 ldr r1, [r3, #24] 80113a2: 68bb ldr r3, [r7, #8] 80113a4: 691a ldr r2, [r3, #16] 80113a6: 68fb ldr r3, [r7, #12] 80113a8: 681b ldr r3, [r3, #0] 80113aa: 430a orrs r2, r1 80113ac: 619a str r2, [r3, #24] break; 80113ae: e064 b.n 801147a { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 80113b0: 68fb ldr r3, [r7, #12] 80113b2: 681b ldr r3, [r3, #0] 80113b4: 68b9 ldr r1, [r7, #8] 80113b6: 4618 mov r0, r3 80113b8: f000 fa32 bl 8011820 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 80113bc: 68fb ldr r3, [r7, #12] 80113be: 681b ldr r3, [r3, #0] 80113c0: 699a ldr r2, [r3, #24] 80113c2: 68fb ldr r3, [r7, #12] 80113c4: 681b ldr r3, [r3, #0] 80113c6: f442 6200 orr.w r2, r2, #2048 @ 0x800 80113ca: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 80113cc: 68fb ldr r3, [r7, #12] 80113ce: 681b ldr r3, [r3, #0] 80113d0: 699a ldr r2, [r3, #24] 80113d2: 68fb ldr r3, [r7, #12] 80113d4: 681b ldr r3, [r3, #0] 80113d6: f422 6280 bic.w r2, r2, #1024 @ 0x400 80113da: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 80113dc: 68fb ldr r3, [r7, #12] 80113de: 681b ldr r3, [r3, #0] 80113e0: 6999 ldr r1, [r3, #24] 80113e2: 68bb ldr r3, [r7, #8] 80113e4: 691b ldr r3, [r3, #16] 80113e6: 021a lsls r2, r3, #8 80113e8: 68fb ldr r3, [r7, #12] 80113ea: 681b ldr r3, [r3, #0] 80113ec: 430a orrs r2, r1 80113ee: 619a str r2, [r3, #24] break; 80113f0: e043 b.n 801147a { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 80113f2: 68fb ldr r3, [r7, #12] 80113f4: 681b ldr r3, [r3, #0] 80113f6: 68b9 ldr r1, [r7, #8] 80113f8: 4618 mov r0, r3 80113fa: f000 fa7b bl 80118f4 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 80113fe: 68fb ldr r3, [r7, #12] 8011400: 681b ldr r3, [r3, #0] 8011402: 69da ldr r2, [r3, #28] 8011404: 68fb ldr r3, [r7, #12] 8011406: 681b ldr r3, [r3, #0] 8011408: f042 0208 orr.w r2, r2, #8 801140c: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 801140e: 68fb ldr r3, [r7, #12] 8011410: 681b ldr r3, [r3, #0] 8011412: 69da ldr r2, [r3, #28] 8011414: 68fb ldr r3, [r7, #12] 8011416: 681b ldr r3, [r3, #0] 8011418: f022 0204 bic.w r2, r2, #4 801141c: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 801141e: 68fb ldr r3, [r7, #12] 8011420: 681b ldr r3, [r3, #0] 8011422: 69d9 ldr r1, [r3, #28] 8011424: 68bb ldr r3, [r7, #8] 8011426: 691a ldr r2, [r3, #16] 8011428: 68fb ldr r3, [r7, #12] 801142a: 681b ldr r3, [r3, #0] 801142c: 430a orrs r2, r1 801142e: 61da str r2, [r3, #28] break; 8011430: e023 b.n 801147a { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8011432: 68fb ldr r3, [r7, #12] 8011434: 681b ldr r3, [r3, #0] 8011436: 68b9 ldr r1, [r7, #8] 8011438: 4618 mov r0, r3 801143a: f000 fac5 bl 80119c8 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 801143e: 68fb ldr r3, [r7, #12] 8011440: 681b ldr r3, [r3, #0] 8011442: 69da ldr r2, [r3, #28] 8011444: 68fb ldr r3, [r7, #12] 8011446: 681b ldr r3, [r3, #0] 8011448: f442 6200 orr.w r2, r2, #2048 @ 0x800 801144c: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 801144e: 68fb ldr r3, [r7, #12] 8011450: 681b ldr r3, [r3, #0] 8011452: 69da ldr r2, [r3, #28] 8011454: 68fb ldr r3, [r7, #12] 8011456: 681b ldr r3, [r3, #0] 8011458: f422 6280 bic.w r2, r2, #1024 @ 0x400 801145c: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 801145e: 68fb ldr r3, [r7, #12] 8011460: 681b ldr r3, [r3, #0] 8011462: 69d9 ldr r1, [r3, #28] 8011464: 68bb ldr r3, [r7, #8] 8011466: 691b ldr r3, [r3, #16] 8011468: 021a lsls r2, r3, #8 801146a: 68fb ldr r3, [r7, #12] 801146c: 681b ldr r3, [r3, #0] 801146e: 430a orrs r2, r1 8011470: 61da str r2, [r3, #28] break; 8011472: e002 b.n 801147a } default: status = HAL_ERROR; 8011474: 2301 movs r3, #1 8011476: 75fb strb r3, [r7, #23] break; 8011478: bf00 nop } __HAL_UNLOCK(htim); 801147a: 68fb ldr r3, [r7, #12] 801147c: 2200 movs r2, #0 801147e: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8011482: 7dfb ldrb r3, [r7, #23] } 8011484: 4618 mov r0, r3 8011486: 3718 adds r7, #24 8011488: 46bd mov sp, r7 801148a: bd80 pop {r7, pc} 0801148c : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 801148c: b580 push {r7, lr} 801148e: b084 sub sp, #16 8011490: af00 add r7, sp, #0 8011492: 6078 str r0, [r7, #4] 8011494: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8011496: 2300 movs r3, #0 8011498: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 801149a: 687b ldr r3, [r7, #4] 801149c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80114a0: 2b01 cmp r3, #1 80114a2: d101 bne.n 80114a8 80114a4: 2302 movs r3, #2 80114a6: e0b4 b.n 8011612 80114a8: 687b ldr r3, [r7, #4] 80114aa: 2201 movs r2, #1 80114ac: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 80114b0: 687b ldr r3, [r7, #4] 80114b2: 2202 movs r2, #2 80114b4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 80114b8: 687b ldr r3, [r7, #4] 80114ba: 681b ldr r3, [r3, #0] 80114bc: 689b ldr r3, [r3, #8] 80114be: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 80114c0: 68bb ldr r3, [r7, #8] 80114c2: f023 0377 bic.w r3, r3, #119 @ 0x77 80114c6: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80114c8: 68bb ldr r3, [r7, #8] 80114ca: f423 437f bic.w r3, r3, #65280 @ 0xff00 80114ce: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 80114d0: 687b ldr r3, [r7, #4] 80114d2: 681b ldr r3, [r3, #0] 80114d4: 68ba ldr r2, [r7, #8] 80114d6: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 80114d8: 683b ldr r3, [r7, #0] 80114da: 681b ldr r3, [r3, #0] 80114dc: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80114e0: d03e beq.n 8011560 80114e2: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80114e6: f200 8087 bhi.w 80115f8 80114ea: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80114ee: f000 8086 beq.w 80115fe 80114f2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80114f6: d87f bhi.n 80115f8 80114f8: 2b70 cmp r3, #112 @ 0x70 80114fa: d01a beq.n 8011532 80114fc: 2b70 cmp r3, #112 @ 0x70 80114fe: d87b bhi.n 80115f8 8011500: 2b60 cmp r3, #96 @ 0x60 8011502: d050 beq.n 80115a6 8011504: 2b60 cmp r3, #96 @ 0x60 8011506: d877 bhi.n 80115f8 8011508: 2b50 cmp r3, #80 @ 0x50 801150a: d03c beq.n 8011586 801150c: 2b50 cmp r3, #80 @ 0x50 801150e: d873 bhi.n 80115f8 8011510: 2b40 cmp r3, #64 @ 0x40 8011512: d058 beq.n 80115c6 8011514: 2b40 cmp r3, #64 @ 0x40 8011516: d86f bhi.n 80115f8 8011518: 2b30 cmp r3, #48 @ 0x30 801151a: d064 beq.n 80115e6 801151c: 2b30 cmp r3, #48 @ 0x30 801151e: d86b bhi.n 80115f8 8011520: 2b20 cmp r3, #32 8011522: d060 beq.n 80115e6 8011524: 2b20 cmp r3, #32 8011526: d867 bhi.n 80115f8 8011528: 2b00 cmp r3, #0 801152a: d05c beq.n 80115e6 801152c: 2b10 cmp r3, #16 801152e: d05a beq.n 80115e6 8011530: e062 b.n 80115f8 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8011532: 687b ldr r3, [r7, #4] 8011534: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8011536: 683b ldr r3, [r7, #0] 8011538: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 801153a: 683b ldr r3, [r7, #0] 801153c: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 801153e: 683b ldr r3, [r7, #0] 8011540: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8011542: f000 fb06 bl 8011b52 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 8011546: 687b ldr r3, [r7, #4] 8011548: 681b ldr r3, [r3, #0] 801154a: 689b ldr r3, [r3, #8] 801154c: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 801154e: 68bb ldr r3, [r7, #8] 8011550: f043 0377 orr.w r3, r3, #119 @ 0x77 8011554: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8011556: 687b ldr r3, [r7, #4] 8011558: 681b ldr r3, [r3, #0] 801155a: 68ba ldr r2, [r7, #8] 801155c: 609a str r2, [r3, #8] break; 801155e: e04f b.n 8011600 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8011560: 687b ldr r3, [r7, #4] 8011562: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8011564: 683b ldr r3, [r7, #0] 8011566: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 8011568: 683b ldr r3, [r7, #0] 801156a: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 801156c: 683b ldr r3, [r7, #0] 801156e: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8011570: f000 faef bl 8011b52 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 8011574: 687b ldr r3, [r7, #4] 8011576: 681b ldr r3, [r3, #0] 8011578: 689a ldr r2, [r3, #8] 801157a: 687b ldr r3, [r7, #4] 801157c: 681b ldr r3, [r3, #0] 801157e: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8011582: 609a str r2, [r3, #8] break; 8011584: e03c b.n 8011600 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8011586: 687b ldr r3, [r7, #4] 8011588: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 801158a: 683b ldr r3, [r7, #0] 801158c: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 801158e: 683b ldr r3, [r7, #0] 8011590: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 8011592: 461a mov r2, r3 8011594: f000 fa66 bl 8011a64 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 8011598: 687b ldr r3, [r7, #4] 801159a: 681b ldr r3, [r3, #0] 801159c: 2150 movs r1, #80 @ 0x50 801159e: 4618 mov r0, r3 80115a0: f000 fabd bl 8011b1e break; 80115a4: e02c b.n 8011600 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 80115a6: 687b ldr r3, [r7, #4] 80115a8: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80115aa: 683b ldr r3, [r7, #0] 80115ac: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80115ae: 683b ldr r3, [r7, #0] 80115b0: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 80115b2: 461a mov r2, r3 80115b4: f000 fa84 bl 8011ac0 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 80115b8: 687b ldr r3, [r7, #4] 80115ba: 681b ldr r3, [r3, #0] 80115bc: 2160 movs r1, #96 @ 0x60 80115be: 4618 mov r0, r3 80115c0: f000 faad bl 8011b1e break; 80115c4: e01c b.n 8011600 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 80115c6: 687b ldr r3, [r7, #4] 80115c8: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80115ca: 683b ldr r3, [r7, #0] 80115cc: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80115ce: 683b ldr r3, [r7, #0] 80115d0: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 80115d2: 461a mov r2, r3 80115d4: f000 fa46 bl 8011a64 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 80115d8: 687b ldr r3, [r7, #4] 80115da: 681b ldr r3, [r3, #0] 80115dc: 2140 movs r1, #64 @ 0x40 80115de: 4618 mov r0, r3 80115e0: f000 fa9d bl 8011b1e break; 80115e4: e00c b.n 8011600 case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 80115e6: 687b ldr r3, [r7, #4] 80115e8: 681a ldr r2, [r3, #0] 80115ea: 683b ldr r3, [r7, #0] 80115ec: 681b ldr r3, [r3, #0] 80115ee: 4619 mov r1, r3 80115f0: 4610 mov r0, r2 80115f2: f000 fa94 bl 8011b1e break; 80115f6: e003 b.n 8011600 } default: status = HAL_ERROR; 80115f8: 2301 movs r3, #1 80115fa: 73fb strb r3, [r7, #15] break; 80115fc: e000 b.n 8011600 break; 80115fe: bf00 nop } htim->State = HAL_TIM_STATE_READY; 8011600: 687b ldr r3, [r7, #4] 8011602: 2201 movs r2, #1 8011604: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8011608: 687b ldr r3, [r7, #4] 801160a: 2200 movs r2, #0 801160c: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8011610: 7bfb ldrb r3, [r7, #15] } 8011612: 4618 mov r0, r3 8011614: 3710 adds r7, #16 8011616: 46bd mov sp, r7 8011618: bd80 pop {r7, pc} 0801161a : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 801161a: b480 push {r7} 801161c: b083 sub sp, #12 801161e: af00 add r7, sp, #0 8011620: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } 8011622: bf00 nop 8011624: 370c adds r7, #12 8011626: 46bd mov sp, r7 8011628: bc80 pop {r7} 801162a: 4770 bx lr 0801162c : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 801162c: b480 push {r7} 801162e: b083 sub sp, #12 8011630: af00 add r7, sp, #0 8011632: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 8011634: bf00 nop 8011636: 370c adds r7, #12 8011638: 46bd mov sp, r7 801163a: bc80 pop {r7} 801163c: 4770 bx lr 0801163e : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 801163e: b480 push {r7} 8011640: b083 sub sp, #12 8011642: af00 add r7, sp, #0 8011644: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8011646: bf00 nop 8011648: 370c adds r7, #12 801164a: 46bd mov sp, r7 801164c: bc80 pop {r7} 801164e: 4770 bx lr 08011650 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8011650: b480 push {r7} 8011652: b083 sub sp, #12 8011654: af00 add r7, sp, #0 8011656: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 8011658: bf00 nop 801165a: 370c adds r7, #12 801165c: 46bd mov sp, r7 801165e: bc80 pop {r7} 8011660: 4770 bx lr ... 08011664 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8011664: b480 push {r7} 8011666: b085 sub sp, #20 8011668: af00 add r7, sp, #0 801166a: 6078 str r0, [r7, #4] 801166c: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 801166e: 687b ldr r3, [r7, #4] 8011670: 681b ldr r3, [r3, #0] 8011672: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8011674: 687b ldr r3, [r7, #4] 8011676: 4a33 ldr r2, [pc, #204] @ (8011744 ) 8011678: 4293 cmp r3, r2 801167a: d00f beq.n 801169c 801167c: 687b ldr r3, [r7, #4] 801167e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8011682: d00b beq.n 801169c 8011684: 687b ldr r3, [r7, #4] 8011686: 4a30 ldr r2, [pc, #192] @ (8011748 ) 8011688: 4293 cmp r3, r2 801168a: d007 beq.n 801169c 801168c: 687b ldr r3, [r7, #4] 801168e: 4a2f ldr r2, [pc, #188] @ (801174c ) 8011690: 4293 cmp r3, r2 8011692: d003 beq.n 801169c 8011694: 687b ldr r3, [r7, #4] 8011696: 4a2e ldr r2, [pc, #184] @ (8011750 ) 8011698: 4293 cmp r3, r2 801169a: d108 bne.n 80116ae { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 801169c: 68fb ldr r3, [r7, #12] 801169e: f023 0370 bic.w r3, r3, #112 @ 0x70 80116a2: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80116a4: 683b ldr r3, [r7, #0] 80116a6: 685b ldr r3, [r3, #4] 80116a8: 68fa ldr r2, [r7, #12] 80116aa: 4313 orrs r3, r2 80116ac: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80116ae: 687b ldr r3, [r7, #4] 80116b0: 4a24 ldr r2, [pc, #144] @ (8011744 ) 80116b2: 4293 cmp r3, r2 80116b4: d00f beq.n 80116d6 80116b6: 687b ldr r3, [r7, #4] 80116b8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80116bc: d00b beq.n 80116d6 80116be: 687b ldr r3, [r7, #4] 80116c0: 4a21 ldr r2, [pc, #132] @ (8011748 ) 80116c2: 4293 cmp r3, r2 80116c4: d007 beq.n 80116d6 80116c6: 687b ldr r3, [r7, #4] 80116c8: 4a20 ldr r2, [pc, #128] @ (801174c ) 80116ca: 4293 cmp r3, r2 80116cc: d003 beq.n 80116d6 80116ce: 687b ldr r3, [r7, #4] 80116d0: 4a1f ldr r2, [pc, #124] @ (8011750 ) 80116d2: 4293 cmp r3, r2 80116d4: d108 bne.n 80116e8 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 80116d6: 68fb ldr r3, [r7, #12] 80116d8: f423 7340 bic.w r3, r3, #768 @ 0x300 80116dc: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80116de: 683b ldr r3, [r7, #0] 80116e0: 68db ldr r3, [r3, #12] 80116e2: 68fa ldr r2, [r7, #12] 80116e4: 4313 orrs r3, r2 80116e6: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80116e8: 68fb ldr r3, [r7, #12] 80116ea: f023 0280 bic.w r2, r3, #128 @ 0x80 80116ee: 683b ldr r3, [r7, #0] 80116f0: 695b ldr r3, [r3, #20] 80116f2: 4313 orrs r3, r2 80116f4: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 80116f6: 687b ldr r3, [r7, #4] 80116f8: 68fa ldr r2, [r7, #12] 80116fa: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 80116fc: 683b ldr r3, [r7, #0] 80116fe: 689a ldr r2, [r3, #8] 8011700: 687b ldr r3, [r7, #4] 8011702: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8011704: 683b ldr r3, [r7, #0] 8011706: 681a ldr r2, [r3, #0] 8011708: 687b ldr r3, [r7, #4] 801170a: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 801170c: 687b ldr r3, [r7, #4] 801170e: 4a0d ldr r2, [pc, #52] @ (8011744 ) 8011710: 4293 cmp r3, r2 8011712: d103 bne.n 801171c { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8011714: 683b ldr r3, [r7, #0] 8011716: 691a ldr r2, [r3, #16] 8011718: 687b ldr r3, [r7, #4] 801171a: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 801171c: 687b ldr r3, [r7, #4] 801171e: 2201 movs r2, #1 8011720: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 8011722: 687b ldr r3, [r7, #4] 8011724: 691b ldr r3, [r3, #16] 8011726: f003 0301 and.w r3, r3, #1 801172a: 2b00 cmp r3, #0 801172c: d005 beq.n 801173a { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 801172e: 687b ldr r3, [r7, #4] 8011730: 691b ldr r3, [r3, #16] 8011732: f023 0201 bic.w r2, r3, #1 8011736: 687b ldr r3, [r7, #4] 8011738: 611a str r2, [r3, #16] } } 801173a: bf00 nop 801173c: 3714 adds r7, #20 801173e: 46bd mov sp, r7 8011740: bc80 pop {r7} 8011742: 4770 bx lr 8011744: 40012c00 .word 0x40012c00 8011748: 40000400 .word 0x40000400 801174c: 40000800 .word 0x40000800 8011750: 40000c00 .word 0x40000c00 08011754 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8011754: b480 push {r7} 8011756: b087 sub sp, #28 8011758: af00 add r7, sp, #0 801175a: 6078 str r0, [r7, #4] 801175c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 801175e: 687b ldr r3, [r7, #4] 8011760: 6a1b ldr r3, [r3, #32] 8011762: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 8011764: 687b ldr r3, [r7, #4] 8011766: 6a1b ldr r3, [r3, #32] 8011768: f023 0201 bic.w r2, r3, #1 801176c: 687b ldr r3, [r7, #4] 801176e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8011770: 687b ldr r3, [r7, #4] 8011772: 685b ldr r3, [r3, #4] 8011774: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8011776: 687b ldr r3, [r7, #4] 8011778: 699b ldr r3, [r3, #24] 801177a: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 801177c: 68fb ldr r3, [r7, #12] 801177e: f023 0370 bic.w r3, r3, #112 @ 0x70 8011782: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 8011784: 68fb ldr r3, [r7, #12] 8011786: f023 0303 bic.w r3, r3, #3 801178a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 801178c: 683b ldr r3, [r7, #0] 801178e: 681b ldr r3, [r3, #0] 8011790: 68fa ldr r2, [r7, #12] 8011792: 4313 orrs r3, r2 8011794: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 8011796: 697b ldr r3, [r7, #20] 8011798: f023 0302 bic.w r3, r3, #2 801179c: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 801179e: 683b ldr r3, [r7, #0] 80117a0: 689b ldr r3, [r3, #8] 80117a2: 697a ldr r2, [r7, #20] 80117a4: 4313 orrs r3, r2 80117a6: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 80117a8: 687b ldr r3, [r7, #4] 80117aa: 4a1c ldr r2, [pc, #112] @ (801181c ) 80117ac: 4293 cmp r3, r2 80117ae: d10c bne.n 80117ca { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 80117b0: 697b ldr r3, [r7, #20] 80117b2: f023 0308 bic.w r3, r3, #8 80117b6: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 80117b8: 683b ldr r3, [r7, #0] 80117ba: 68db ldr r3, [r3, #12] 80117bc: 697a ldr r2, [r7, #20] 80117be: 4313 orrs r3, r2 80117c0: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 80117c2: 697b ldr r3, [r7, #20] 80117c4: f023 0304 bic.w r3, r3, #4 80117c8: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80117ca: 687b ldr r3, [r7, #4] 80117cc: 4a13 ldr r2, [pc, #76] @ (801181c ) 80117ce: 4293 cmp r3, r2 80117d0: d111 bne.n 80117f6 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 80117d2: 693b ldr r3, [r7, #16] 80117d4: f423 7380 bic.w r3, r3, #256 @ 0x100 80117d8: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 80117da: 693b ldr r3, [r7, #16] 80117dc: f423 7300 bic.w r3, r3, #512 @ 0x200 80117e0: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 80117e2: 683b ldr r3, [r7, #0] 80117e4: 695b ldr r3, [r3, #20] 80117e6: 693a ldr r2, [r7, #16] 80117e8: 4313 orrs r3, r2 80117ea: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 80117ec: 683b ldr r3, [r7, #0] 80117ee: 699b ldr r3, [r3, #24] 80117f0: 693a ldr r2, [r7, #16] 80117f2: 4313 orrs r3, r2 80117f4: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80117f6: 687b ldr r3, [r7, #4] 80117f8: 693a ldr r2, [r7, #16] 80117fa: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80117fc: 687b ldr r3, [r7, #4] 80117fe: 68fa ldr r2, [r7, #12] 8011800: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 8011802: 683b ldr r3, [r7, #0] 8011804: 685a ldr r2, [r3, #4] 8011806: 687b ldr r3, [r7, #4] 8011808: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 801180a: 687b ldr r3, [r7, #4] 801180c: 697a ldr r2, [r7, #20] 801180e: 621a str r2, [r3, #32] } 8011810: bf00 nop 8011812: 371c adds r7, #28 8011814: 46bd mov sp, r7 8011816: bc80 pop {r7} 8011818: 4770 bx lr 801181a: bf00 nop 801181c: 40012c00 .word 0x40012c00 08011820 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8011820: b480 push {r7} 8011822: b087 sub sp, #28 8011824: af00 add r7, sp, #0 8011826: 6078 str r0, [r7, #4] 8011828: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 801182a: 687b ldr r3, [r7, #4] 801182c: 6a1b ldr r3, [r3, #32] 801182e: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8011830: 687b ldr r3, [r7, #4] 8011832: 6a1b ldr r3, [r3, #32] 8011834: f023 0210 bic.w r2, r3, #16 8011838: 687b ldr r3, [r7, #4] 801183a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 801183c: 687b ldr r3, [r7, #4] 801183e: 685b ldr r3, [r3, #4] 8011840: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8011842: 687b ldr r3, [r7, #4] 8011844: 699b ldr r3, [r3, #24] 8011846: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 8011848: 68fb ldr r3, [r7, #12] 801184a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 801184e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8011850: 68fb ldr r3, [r7, #12] 8011852: f423 7340 bic.w r3, r3, #768 @ 0x300 8011856: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8011858: 683b ldr r3, [r7, #0] 801185a: 681b ldr r3, [r3, #0] 801185c: 021b lsls r3, r3, #8 801185e: 68fa ldr r2, [r7, #12] 8011860: 4313 orrs r3, r2 8011862: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 8011864: 697b ldr r3, [r7, #20] 8011866: f023 0320 bic.w r3, r3, #32 801186a: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 801186c: 683b ldr r3, [r7, #0] 801186e: 689b ldr r3, [r3, #8] 8011870: 011b lsls r3, r3, #4 8011872: 697a ldr r2, [r7, #20] 8011874: 4313 orrs r3, r2 8011876: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 8011878: 687b ldr r3, [r7, #4] 801187a: 4a1d ldr r2, [pc, #116] @ (80118f0 ) 801187c: 4293 cmp r3, r2 801187e: d10d bne.n 801189c { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 8011880: 697b ldr r3, [r7, #20] 8011882: f023 0380 bic.w r3, r3, #128 @ 0x80 8011886: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8011888: 683b ldr r3, [r7, #0] 801188a: 68db ldr r3, [r3, #12] 801188c: 011b lsls r3, r3, #4 801188e: 697a ldr r2, [r7, #20] 8011890: 4313 orrs r3, r2 8011892: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8011894: 697b ldr r3, [r7, #20] 8011896: f023 0340 bic.w r3, r3, #64 @ 0x40 801189a: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 801189c: 687b ldr r3, [r7, #4] 801189e: 4a14 ldr r2, [pc, #80] @ (80118f0 ) 80118a0: 4293 cmp r3, r2 80118a2: d113 bne.n 80118cc /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 80118a4: 693b ldr r3, [r7, #16] 80118a6: f423 6380 bic.w r3, r3, #1024 @ 0x400 80118aa: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 80118ac: 693b ldr r3, [r7, #16] 80118ae: f423 6300 bic.w r3, r3, #2048 @ 0x800 80118b2: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 80118b4: 683b ldr r3, [r7, #0] 80118b6: 695b ldr r3, [r3, #20] 80118b8: 009b lsls r3, r3, #2 80118ba: 693a ldr r2, [r7, #16] 80118bc: 4313 orrs r3, r2 80118be: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 80118c0: 683b ldr r3, [r7, #0] 80118c2: 699b ldr r3, [r3, #24] 80118c4: 009b lsls r3, r3, #2 80118c6: 693a ldr r2, [r7, #16] 80118c8: 4313 orrs r3, r2 80118ca: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80118cc: 687b ldr r3, [r7, #4] 80118ce: 693a ldr r2, [r7, #16] 80118d0: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80118d2: 687b ldr r3, [r7, #4] 80118d4: 68fa ldr r2, [r7, #12] 80118d6: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 80118d8: 683b ldr r3, [r7, #0] 80118da: 685a ldr r2, [r3, #4] 80118dc: 687b ldr r3, [r7, #4] 80118de: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80118e0: 687b ldr r3, [r7, #4] 80118e2: 697a ldr r2, [r7, #20] 80118e4: 621a str r2, [r3, #32] } 80118e6: bf00 nop 80118e8: 371c adds r7, #28 80118ea: 46bd mov sp, r7 80118ec: bc80 pop {r7} 80118ee: 4770 bx lr 80118f0: 40012c00 .word 0x40012c00 080118f4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80118f4: b480 push {r7} 80118f6: b087 sub sp, #28 80118f8: af00 add r7, sp, #0 80118fa: 6078 str r0, [r7, #4] 80118fc: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80118fe: 687b ldr r3, [r7, #4] 8011900: 6a1b ldr r3, [r3, #32] 8011902: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8011904: 687b ldr r3, [r7, #4] 8011906: 6a1b ldr r3, [r3, #32] 8011908: f423 7280 bic.w r2, r3, #256 @ 0x100 801190c: 687b ldr r3, [r7, #4] 801190e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8011910: 687b ldr r3, [r7, #4] 8011912: 685b ldr r3, [r3, #4] 8011914: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8011916: 687b ldr r3, [r7, #4] 8011918: 69db ldr r3, [r3, #28] 801191a: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 801191c: 68fb ldr r3, [r7, #12] 801191e: f023 0370 bic.w r3, r3, #112 @ 0x70 8011922: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8011924: 68fb ldr r3, [r7, #12] 8011926: f023 0303 bic.w r3, r3, #3 801192a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 801192c: 683b ldr r3, [r7, #0] 801192e: 681b ldr r3, [r3, #0] 8011930: 68fa ldr r2, [r7, #12] 8011932: 4313 orrs r3, r2 8011934: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8011936: 697b ldr r3, [r7, #20] 8011938: f423 7300 bic.w r3, r3, #512 @ 0x200 801193c: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 801193e: 683b ldr r3, [r7, #0] 8011940: 689b ldr r3, [r3, #8] 8011942: 021b lsls r3, r3, #8 8011944: 697a ldr r2, [r7, #20] 8011946: 4313 orrs r3, r2 8011948: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 801194a: 687b ldr r3, [r7, #4] 801194c: 4a1d ldr r2, [pc, #116] @ (80119c4 ) 801194e: 4293 cmp r3, r2 8011950: d10d bne.n 801196e { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8011952: 697b ldr r3, [r7, #20] 8011954: f423 6300 bic.w r3, r3, #2048 @ 0x800 8011958: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 801195a: 683b ldr r3, [r7, #0] 801195c: 68db ldr r3, [r3, #12] 801195e: 021b lsls r3, r3, #8 8011960: 697a ldr r2, [r7, #20] 8011962: 4313 orrs r3, r2 8011964: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8011966: 697b ldr r3, [r7, #20] 8011968: f423 6380 bic.w r3, r3, #1024 @ 0x400 801196c: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 801196e: 687b ldr r3, [r7, #4] 8011970: 4a14 ldr r2, [pc, #80] @ (80119c4 ) 8011972: 4293 cmp r3, r2 8011974: d113 bne.n 801199e /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8011976: 693b ldr r3, [r7, #16] 8011978: f423 5380 bic.w r3, r3, #4096 @ 0x1000 801197c: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 801197e: 693b ldr r3, [r7, #16] 8011980: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8011984: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8011986: 683b ldr r3, [r7, #0] 8011988: 695b ldr r3, [r3, #20] 801198a: 011b lsls r3, r3, #4 801198c: 693a ldr r2, [r7, #16] 801198e: 4313 orrs r3, r2 8011990: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 8011992: 683b ldr r3, [r7, #0] 8011994: 699b ldr r3, [r3, #24] 8011996: 011b lsls r3, r3, #4 8011998: 693a ldr r2, [r7, #16] 801199a: 4313 orrs r3, r2 801199c: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 801199e: 687b ldr r3, [r7, #4] 80119a0: 693a ldr r2, [r7, #16] 80119a2: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 80119a4: 687b ldr r3, [r7, #4] 80119a6: 68fa ldr r2, [r7, #12] 80119a8: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 80119aa: 683b ldr r3, [r7, #0] 80119ac: 685a ldr r2, [r3, #4] 80119ae: 687b ldr r3, [r7, #4] 80119b0: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80119b2: 687b ldr r3, [r7, #4] 80119b4: 697a ldr r2, [r7, #20] 80119b6: 621a str r2, [r3, #32] } 80119b8: bf00 nop 80119ba: 371c adds r7, #28 80119bc: 46bd mov sp, r7 80119be: bc80 pop {r7} 80119c0: 4770 bx lr 80119c2: bf00 nop 80119c4: 40012c00 .word 0x40012c00 080119c8 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80119c8: b480 push {r7} 80119ca: b087 sub sp, #28 80119cc: af00 add r7, sp, #0 80119ce: 6078 str r0, [r7, #4] 80119d0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80119d2: 687b ldr r3, [r7, #4] 80119d4: 6a1b ldr r3, [r3, #32] 80119d6: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 80119d8: 687b ldr r3, [r7, #4] 80119da: 6a1b ldr r3, [r3, #32] 80119dc: f423 5280 bic.w r2, r3, #4096 @ 0x1000 80119e0: 687b ldr r3, [r7, #4] 80119e2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80119e4: 687b ldr r3, [r7, #4] 80119e6: 685b ldr r3, [r3, #4] 80119e8: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 80119ea: 687b ldr r3, [r7, #4] 80119ec: 69db ldr r3, [r3, #28] 80119ee: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 80119f0: 68fb ldr r3, [r7, #12] 80119f2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80119f6: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 80119f8: 68fb ldr r3, [r7, #12] 80119fa: f423 7340 bic.w r3, r3, #768 @ 0x300 80119fe: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8011a00: 683b ldr r3, [r7, #0] 8011a02: 681b ldr r3, [r3, #0] 8011a04: 021b lsls r3, r3, #8 8011a06: 68fa ldr r2, [r7, #12] 8011a08: 4313 orrs r3, r2 8011a0a: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8011a0c: 693b ldr r3, [r7, #16] 8011a0e: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8011a12: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8011a14: 683b ldr r3, [r7, #0] 8011a16: 689b ldr r3, [r3, #8] 8011a18: 031b lsls r3, r3, #12 8011a1a: 693a ldr r2, [r7, #16] 8011a1c: 4313 orrs r3, r2 8011a1e: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8011a20: 687b ldr r3, [r7, #4] 8011a22: 4a0f ldr r2, [pc, #60] @ (8011a60 ) 8011a24: 4293 cmp r3, r2 8011a26: d109 bne.n 8011a3c { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8011a28: 697b ldr r3, [r7, #20] 8011a2a: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8011a2e: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8011a30: 683b ldr r3, [r7, #0] 8011a32: 695b ldr r3, [r3, #20] 8011a34: 019b lsls r3, r3, #6 8011a36: 697a ldr r2, [r7, #20] 8011a38: 4313 orrs r3, r2 8011a3a: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8011a3c: 687b ldr r3, [r7, #4] 8011a3e: 697a ldr r2, [r7, #20] 8011a40: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8011a42: 687b ldr r3, [r7, #4] 8011a44: 68fa ldr r2, [r7, #12] 8011a46: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8011a48: 683b ldr r3, [r7, #0] 8011a4a: 685a ldr r2, [r3, #4] 8011a4c: 687b ldr r3, [r7, #4] 8011a4e: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8011a50: 687b ldr r3, [r7, #4] 8011a52: 693a ldr r2, [r7, #16] 8011a54: 621a str r2, [r3, #32] } 8011a56: bf00 nop 8011a58: 371c adds r7, #28 8011a5a: 46bd mov sp, r7 8011a5c: bc80 pop {r7} 8011a5e: 4770 bx lr 8011a60: 40012c00 .word 0x40012c00 08011a64 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8011a64: b480 push {r7} 8011a66: b087 sub sp, #28 8011a68: af00 add r7, sp, #0 8011a6a: 60f8 str r0, [r7, #12] 8011a6c: 60b9 str r1, [r7, #8] 8011a6e: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8011a70: 68fb ldr r3, [r7, #12] 8011a72: 6a1b ldr r3, [r3, #32] 8011a74: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8011a76: 68fb ldr r3, [r7, #12] 8011a78: 6a1b ldr r3, [r3, #32] 8011a7a: f023 0201 bic.w r2, r3, #1 8011a7e: 68fb ldr r3, [r7, #12] 8011a80: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8011a82: 68fb ldr r3, [r7, #12] 8011a84: 699b ldr r3, [r3, #24] 8011a86: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8011a88: 693b ldr r3, [r7, #16] 8011a8a: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8011a8e: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8011a90: 687b ldr r3, [r7, #4] 8011a92: 011b lsls r3, r3, #4 8011a94: 693a ldr r2, [r7, #16] 8011a96: 4313 orrs r3, r2 8011a98: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8011a9a: 697b ldr r3, [r7, #20] 8011a9c: f023 030a bic.w r3, r3, #10 8011aa0: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8011aa2: 697a ldr r2, [r7, #20] 8011aa4: 68bb ldr r3, [r7, #8] 8011aa6: 4313 orrs r3, r2 8011aa8: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8011aaa: 68fb ldr r3, [r7, #12] 8011aac: 693a ldr r2, [r7, #16] 8011aae: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8011ab0: 68fb ldr r3, [r7, #12] 8011ab2: 697a ldr r2, [r7, #20] 8011ab4: 621a str r2, [r3, #32] } 8011ab6: bf00 nop 8011ab8: 371c adds r7, #28 8011aba: 46bd mov sp, r7 8011abc: bc80 pop {r7} 8011abe: 4770 bx lr 08011ac0 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8011ac0: b480 push {r7} 8011ac2: b087 sub sp, #28 8011ac4: af00 add r7, sp, #0 8011ac6: 60f8 str r0, [r7, #12] 8011ac8: 60b9 str r1, [r7, #8] 8011aca: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8011acc: 68fb ldr r3, [r7, #12] 8011ace: 6a1b ldr r3, [r3, #32] 8011ad0: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8011ad2: 68fb ldr r3, [r7, #12] 8011ad4: 6a1b ldr r3, [r3, #32] 8011ad6: f023 0210 bic.w r2, r3, #16 8011ada: 68fb ldr r3, [r7, #12] 8011adc: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8011ade: 68fb ldr r3, [r7, #12] 8011ae0: 699b ldr r3, [r3, #24] 8011ae2: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8011ae4: 693b ldr r3, [r7, #16] 8011ae6: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8011aea: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8011aec: 687b ldr r3, [r7, #4] 8011aee: 031b lsls r3, r3, #12 8011af0: 693a ldr r2, [r7, #16] 8011af2: 4313 orrs r3, r2 8011af4: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8011af6: 697b ldr r3, [r7, #20] 8011af8: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8011afc: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8011afe: 68bb ldr r3, [r7, #8] 8011b00: 011b lsls r3, r3, #4 8011b02: 697a ldr r2, [r7, #20] 8011b04: 4313 orrs r3, r2 8011b06: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8011b08: 68fb ldr r3, [r7, #12] 8011b0a: 693a ldr r2, [r7, #16] 8011b0c: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8011b0e: 68fb ldr r3, [r7, #12] 8011b10: 697a ldr r2, [r7, #20] 8011b12: 621a str r2, [r3, #32] } 8011b14: bf00 nop 8011b16: 371c adds r7, #28 8011b18: 46bd mov sp, r7 8011b1a: bc80 pop {r7} 8011b1c: 4770 bx lr 08011b1e : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8011b1e: b480 push {r7} 8011b20: b085 sub sp, #20 8011b22: af00 add r7, sp, #0 8011b24: 6078 str r0, [r7, #4] 8011b26: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8011b28: 687b ldr r3, [r7, #4] 8011b2a: 689b ldr r3, [r3, #8] 8011b2c: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8011b2e: 68fb ldr r3, [r7, #12] 8011b30: f023 0370 bic.w r3, r3, #112 @ 0x70 8011b34: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8011b36: 683a ldr r2, [r7, #0] 8011b38: 68fb ldr r3, [r7, #12] 8011b3a: 4313 orrs r3, r2 8011b3c: f043 0307 orr.w r3, r3, #7 8011b40: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8011b42: 687b ldr r3, [r7, #4] 8011b44: 68fa ldr r2, [r7, #12] 8011b46: 609a str r2, [r3, #8] } 8011b48: bf00 nop 8011b4a: 3714 adds r7, #20 8011b4c: 46bd mov sp, r7 8011b4e: bc80 pop {r7} 8011b50: 4770 bx lr 08011b52 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8011b52: b480 push {r7} 8011b54: b087 sub sp, #28 8011b56: af00 add r7, sp, #0 8011b58: 60f8 str r0, [r7, #12] 8011b5a: 60b9 str r1, [r7, #8] 8011b5c: 607a str r2, [r7, #4] 8011b5e: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8011b60: 68fb ldr r3, [r7, #12] 8011b62: 689b ldr r3, [r3, #8] 8011b64: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8011b66: 697b ldr r3, [r7, #20] 8011b68: f423 437f bic.w r3, r3, #65280 @ 0xff00 8011b6c: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8011b6e: 683b ldr r3, [r7, #0] 8011b70: 021a lsls r2, r3, #8 8011b72: 687b ldr r3, [r7, #4] 8011b74: 431a orrs r2, r3 8011b76: 68bb ldr r3, [r7, #8] 8011b78: 4313 orrs r3, r2 8011b7a: 697a ldr r2, [r7, #20] 8011b7c: 4313 orrs r3, r2 8011b7e: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8011b80: 68fb ldr r3, [r7, #12] 8011b82: 697a ldr r2, [r7, #20] 8011b84: 609a str r2, [r3, #8] } 8011b86: bf00 nop 8011b88: 371c adds r7, #28 8011b8a: 46bd mov sp, r7 8011b8c: bc80 pop {r7} 8011b8e: 4770 bx lr 08011b90 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8011b90: b480 push {r7} 8011b92: b087 sub sp, #28 8011b94: af00 add r7, sp, #0 8011b96: 60f8 str r0, [r7, #12] 8011b98: 60b9 str r1, [r7, #8] 8011b9a: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8011b9c: 68bb ldr r3, [r7, #8] 8011b9e: f003 031f and.w r3, r3, #31 8011ba2: 2201 movs r2, #1 8011ba4: fa02 f303 lsl.w r3, r2, r3 8011ba8: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 8011baa: 68fb ldr r3, [r7, #12] 8011bac: 6a1a ldr r2, [r3, #32] 8011bae: 697b ldr r3, [r7, #20] 8011bb0: 43db mvns r3, r3 8011bb2: 401a ands r2, r3 8011bb4: 68fb ldr r3, [r7, #12] 8011bb6: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8011bb8: 68fb ldr r3, [r7, #12] 8011bba: 6a1a ldr r2, [r3, #32] 8011bbc: 68bb ldr r3, [r7, #8] 8011bbe: f003 031f and.w r3, r3, #31 8011bc2: 6879 ldr r1, [r7, #4] 8011bc4: fa01 f303 lsl.w r3, r1, r3 8011bc8: 431a orrs r2, r3 8011bca: 68fb ldr r3, [r7, #12] 8011bcc: 621a str r2, [r3, #32] } 8011bce: bf00 nop 8011bd0: 371c adds r7, #28 8011bd2: 46bd mov sp, r7 8011bd4: bc80 pop {r7} 8011bd6: 4770 bx lr 08011bd8 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8011bd8: b480 push {r7} 8011bda: b085 sub sp, #20 8011bdc: af00 add r7, sp, #0 8011bde: 6078 str r0, [r7, #4] 8011be0: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8011be2: 687b ldr r3, [r7, #4] 8011be4: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8011be8: 2b01 cmp r3, #1 8011bea: d101 bne.n 8011bf0 8011bec: 2302 movs r3, #2 8011bee: e04b b.n 8011c88 8011bf0: 687b ldr r3, [r7, #4] 8011bf2: 2201 movs r2, #1 8011bf4: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8011bf8: 687b ldr r3, [r7, #4] 8011bfa: 2202 movs r2, #2 8011bfc: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8011c00: 687b ldr r3, [r7, #4] 8011c02: 681b ldr r3, [r3, #0] 8011c04: 685b ldr r3, [r3, #4] 8011c06: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8011c08: 687b ldr r3, [r7, #4] 8011c0a: 681b ldr r3, [r3, #0] 8011c0c: 689b ldr r3, [r3, #8] 8011c0e: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8011c10: 68fb ldr r3, [r7, #12] 8011c12: f023 0370 bic.w r3, r3, #112 @ 0x70 8011c16: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8011c18: 683b ldr r3, [r7, #0] 8011c1a: 681b ldr r3, [r3, #0] 8011c1c: 68fa ldr r2, [r7, #12] 8011c1e: 4313 orrs r3, r2 8011c20: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8011c22: 687b ldr r3, [r7, #4] 8011c24: 681b ldr r3, [r3, #0] 8011c26: 68fa ldr r2, [r7, #12] 8011c28: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8011c2a: 687b ldr r3, [r7, #4] 8011c2c: 681b ldr r3, [r3, #0] 8011c2e: 4a19 ldr r2, [pc, #100] @ (8011c94 ) 8011c30: 4293 cmp r3, r2 8011c32: d013 beq.n 8011c5c 8011c34: 687b ldr r3, [r7, #4] 8011c36: 681b ldr r3, [r3, #0] 8011c38: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8011c3c: d00e beq.n 8011c5c 8011c3e: 687b ldr r3, [r7, #4] 8011c40: 681b ldr r3, [r3, #0] 8011c42: 4a15 ldr r2, [pc, #84] @ (8011c98 ) 8011c44: 4293 cmp r3, r2 8011c46: d009 beq.n 8011c5c 8011c48: 687b ldr r3, [r7, #4] 8011c4a: 681b ldr r3, [r3, #0] 8011c4c: 4a13 ldr r2, [pc, #76] @ (8011c9c ) 8011c4e: 4293 cmp r3, r2 8011c50: d004 beq.n 8011c5c 8011c52: 687b ldr r3, [r7, #4] 8011c54: 681b ldr r3, [r3, #0] 8011c56: 4a12 ldr r2, [pc, #72] @ (8011ca0 ) 8011c58: 4293 cmp r3, r2 8011c5a: d10c bne.n 8011c76 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8011c5c: 68bb ldr r3, [r7, #8] 8011c5e: f023 0380 bic.w r3, r3, #128 @ 0x80 8011c62: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8011c64: 683b ldr r3, [r7, #0] 8011c66: 685b ldr r3, [r3, #4] 8011c68: 68ba ldr r2, [r7, #8] 8011c6a: 4313 orrs r3, r2 8011c6c: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8011c6e: 687b ldr r3, [r7, #4] 8011c70: 681b ldr r3, [r3, #0] 8011c72: 68ba ldr r2, [r7, #8] 8011c74: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8011c76: 687b ldr r3, [r7, #4] 8011c78: 2201 movs r2, #1 8011c7a: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8011c7e: 687b ldr r3, [r7, #4] 8011c80: 2200 movs r2, #0 8011c82: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8011c86: 2300 movs r3, #0 } 8011c88: 4618 mov r0, r3 8011c8a: 3714 adds r7, #20 8011c8c: 46bd mov sp, r7 8011c8e: bc80 pop {r7} 8011c90: 4770 bx lr 8011c92: bf00 nop 8011c94: 40012c00 .word 0x40012c00 8011c98: 40000400 .word 0x40000400 8011c9c: 40000800 .word 0x40000800 8011ca0: 40000c00 .word 0x40000c00 08011ca4 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8011ca4: b480 push {r7} 8011ca6: b083 sub sp, #12 8011ca8: af00 add r7, sp, #0 8011caa: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8011cac: bf00 nop 8011cae: 370c adds r7, #12 8011cb0: 46bd mov sp, r7 8011cb2: bc80 pop {r7} 8011cb4: 4770 bx lr 08011cb6 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8011cb6: b480 push {r7} 8011cb8: b083 sub sp, #12 8011cba: af00 add r7, sp, #0 8011cbc: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8011cbe: bf00 nop 8011cc0: 370c adds r7, #12 8011cc2: 46bd mov sp, r7 8011cc4: bc80 pop {r7} 8011cc6: 4770 bx lr 08011cc8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8011cc8: b580 push {r7, lr} 8011cca: b082 sub sp, #8 8011ccc: af00 add r7, sp, #0 8011cce: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8011cd0: 687b ldr r3, [r7, #4] 8011cd2: 2b00 cmp r3, #0 8011cd4: d101 bne.n 8011cda { return HAL_ERROR; 8011cd6: 2301 movs r3, #1 8011cd8: e042 b.n 8011d60 assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 8011cda: 687b ldr r3, [r7, #4] 8011cdc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011ce0: b2db uxtb r3, r3 8011ce2: 2b00 cmp r3, #0 8011ce4: d106 bne.n 8011cf4 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8011ce6: 687b ldr r3, [r7, #4] 8011ce8: 2200 movs r2, #0 8011cea: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8011cee: 6878 ldr r0, [r7, #4] 8011cf0: f7fb fc6c bl 800d5cc #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8011cf4: 687b ldr r3, [r7, #4] 8011cf6: 2224 movs r2, #36 @ 0x24 8011cf8: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8011cfc: 687b ldr r3, [r7, #4] 8011cfe: 681b ldr r3, [r3, #0] 8011d00: 68da ldr r2, [r3, #12] 8011d02: 687b ldr r3, [r7, #4] 8011d04: 681b ldr r3, [r3, #0] 8011d06: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8011d0a: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8011d0c: 6878 ldr r0, [r7, #4] 8011d0e: f000 ffb5 bl 8012c7c /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8011d12: 687b ldr r3, [r7, #4] 8011d14: 681b ldr r3, [r3, #0] 8011d16: 691a ldr r2, [r3, #16] 8011d18: 687b ldr r3, [r7, #4] 8011d1a: 681b ldr r3, [r3, #0] 8011d1c: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8011d20: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8011d22: 687b ldr r3, [r7, #4] 8011d24: 681b ldr r3, [r3, #0] 8011d26: 695a ldr r2, [r3, #20] 8011d28: 687b ldr r3, [r7, #4] 8011d2a: 681b ldr r3, [r3, #0] 8011d2c: f022 022a bic.w r2, r2, #42 @ 0x2a 8011d30: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8011d32: 687b ldr r3, [r7, #4] 8011d34: 681b ldr r3, [r3, #0] 8011d36: 68da ldr r2, [r3, #12] 8011d38: 687b ldr r3, [r7, #4] 8011d3a: 681b ldr r3, [r3, #0] 8011d3c: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8011d40: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8011d42: 687b ldr r3, [r7, #4] 8011d44: 2200 movs r2, #0 8011d46: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8011d48: 687b ldr r3, [r7, #4] 8011d4a: 2220 movs r2, #32 8011d4c: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8011d50: 687b ldr r3, [r7, #4] 8011d52: 2220 movs r2, #32 8011d54: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8011d58: 687b ldr r3, [r7, #4] 8011d5a: 2200 movs r2, #0 8011d5c: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8011d5e: 2300 movs r3, #0 } 8011d60: 4618 mov r0, r3 8011d62: 3708 adds r7, #8 8011d64: 46bd mov sp, r7 8011d66: bd80 pop {r7, pc} 08011d68 : * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8011d68: b580 push {r7, lr} 8011d6a: b08a sub sp, #40 @ 0x28 8011d6c: af02 add r7, sp, #8 8011d6e: 60f8 str r0, [r7, #12] 8011d70: 60b9 str r1, [r7, #8] 8011d72: 603b str r3, [r7, #0] 8011d74: 4613 mov r3, r2 8011d76: 80fb strh r3, [r7, #6] const uint8_t *pdata8bits; const uint16_t *pdata16bits; uint32_t tickstart = 0U; 8011d78: 2300 movs r3, #0 8011d7a: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8011d7c: 68fb ldr r3, [r7, #12] 8011d7e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011d82: b2db uxtb r3, r3 8011d84: 2b20 cmp r3, #32 8011d86: d175 bne.n 8011e74 { if ((pData == NULL) || (Size == 0U)) 8011d88: 68bb ldr r3, [r7, #8] 8011d8a: 2b00 cmp r3, #0 8011d8c: d002 beq.n 8011d94 8011d8e: 88fb ldrh r3, [r7, #6] 8011d90: 2b00 cmp r3, #0 8011d92: d101 bne.n 8011d98 { return HAL_ERROR; 8011d94: 2301 movs r3, #1 8011d96: e06e b.n 8011e76 } huart->ErrorCode = HAL_UART_ERROR_NONE; 8011d98: 68fb ldr r3, [r7, #12] 8011d9a: 2200 movs r2, #0 8011d9c: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8011d9e: 68fb ldr r3, [r7, #12] 8011da0: 2221 movs r2, #33 @ 0x21 8011da2: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8011da6: f7fb fdd9 bl 800d95c 8011daa: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 8011dac: 68fb ldr r3, [r7, #12] 8011dae: 88fa ldrh r2, [r7, #6] 8011db0: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8011db2: 68fb ldr r3, [r7, #12] 8011db4: 88fa ldrh r2, [r7, #6] 8011db6: 84da strh r2, [r3, #38] @ 0x26 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8011db8: 68fb ldr r3, [r7, #12] 8011dba: 689b ldr r3, [r3, #8] 8011dbc: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8011dc0: d108 bne.n 8011dd4 8011dc2: 68fb ldr r3, [r7, #12] 8011dc4: 691b ldr r3, [r3, #16] 8011dc6: 2b00 cmp r3, #0 8011dc8: d104 bne.n 8011dd4 { pdata8bits = NULL; 8011dca: 2300 movs r3, #0 8011dcc: 61fb str r3, [r7, #28] pdata16bits = (const uint16_t *) pData; 8011dce: 68bb ldr r3, [r7, #8] 8011dd0: 61bb str r3, [r7, #24] 8011dd2: e003 b.n 8011ddc } else { pdata8bits = pData; 8011dd4: 68bb ldr r3, [r7, #8] 8011dd6: 61fb str r3, [r7, #28] pdata16bits = NULL; 8011dd8: 2300 movs r3, #0 8011dda: 61bb str r3, [r7, #24] } while (huart->TxXferCount > 0U) 8011ddc: e02e b.n 8011e3c { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8011dde: 683b ldr r3, [r7, #0] 8011de0: 9300 str r3, [sp, #0] 8011de2: 697b ldr r3, [r7, #20] 8011de4: 2200 movs r2, #0 8011de6: 2180 movs r1, #128 @ 0x80 8011de8: 68f8 ldr r0, [r7, #12] 8011dea: f000 fcb9 bl 8012760 8011dee: 4603 mov r3, r0 8011df0: 2b00 cmp r3, #0 8011df2: d005 beq.n 8011e00 { huart->gState = HAL_UART_STATE_READY; 8011df4: 68fb ldr r3, [r7, #12] 8011df6: 2220 movs r2, #32 8011df8: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_TIMEOUT; 8011dfc: 2303 movs r3, #3 8011dfe: e03a b.n 8011e76 } if (pdata8bits == NULL) 8011e00: 69fb ldr r3, [r7, #28] 8011e02: 2b00 cmp r3, #0 8011e04: d10b bne.n 8011e1e { huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); 8011e06: 69bb ldr r3, [r7, #24] 8011e08: 881b ldrh r3, [r3, #0] 8011e0a: 461a mov r2, r3 8011e0c: 68fb ldr r3, [r7, #12] 8011e0e: 681b ldr r3, [r3, #0] 8011e10: f3c2 0208 ubfx r2, r2, #0, #9 8011e14: 605a str r2, [r3, #4] pdata16bits++; 8011e16: 69bb ldr r3, [r7, #24] 8011e18: 3302 adds r3, #2 8011e1a: 61bb str r3, [r7, #24] 8011e1c: e007 b.n 8011e2e } else { huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); 8011e1e: 69fb ldr r3, [r7, #28] 8011e20: 781a ldrb r2, [r3, #0] 8011e22: 68fb ldr r3, [r7, #12] 8011e24: 681b ldr r3, [r3, #0] 8011e26: 605a str r2, [r3, #4] pdata8bits++; 8011e28: 69fb ldr r3, [r7, #28] 8011e2a: 3301 adds r3, #1 8011e2c: 61fb str r3, [r7, #28] } huart->TxXferCount--; 8011e2e: 68fb ldr r3, [r7, #12] 8011e30: 8cdb ldrh r3, [r3, #38] @ 0x26 8011e32: b29b uxth r3, r3 8011e34: 3b01 subs r3, #1 8011e36: b29a uxth r2, r3 8011e38: 68fb ldr r3, [r7, #12] 8011e3a: 84da strh r2, [r3, #38] @ 0x26 while (huart->TxXferCount > 0U) 8011e3c: 68fb ldr r3, [r7, #12] 8011e3e: 8cdb ldrh r3, [r3, #38] @ 0x26 8011e40: b29b uxth r3, r3 8011e42: 2b00 cmp r3, #0 8011e44: d1cb bne.n 8011dde } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8011e46: 683b ldr r3, [r7, #0] 8011e48: 9300 str r3, [sp, #0] 8011e4a: 697b ldr r3, [r7, #20] 8011e4c: 2200 movs r2, #0 8011e4e: 2140 movs r1, #64 @ 0x40 8011e50: 68f8 ldr r0, [r7, #12] 8011e52: f000 fc85 bl 8012760 8011e56: 4603 mov r3, r0 8011e58: 2b00 cmp r3, #0 8011e5a: d005 beq.n 8011e68 { huart->gState = HAL_UART_STATE_READY; 8011e5c: 68fb ldr r3, [r7, #12] 8011e5e: 2220 movs r2, #32 8011e60: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_TIMEOUT; 8011e64: 2303 movs r3, #3 8011e66: e006 b.n 8011e76 } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8011e68: 68fb ldr r3, [r7, #12] 8011e6a: 2220 movs r2, #32 8011e6c: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_OK; 8011e70: 2300 movs r3, #0 8011e72: e000 b.n 8011e76 } else { return HAL_BUSY; 8011e74: 2302 movs r3, #2 } } 8011e76: 4618 mov r0, r3 8011e78: 3720 adds r7, #32 8011e7a: 46bd mov sp, r7 8011e7c: bd80 pop {r7, pc} 08011e7e : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8011e7e: b480 push {r7} 8011e80: b085 sub sp, #20 8011e82: af00 add r7, sp, #0 8011e84: 60f8 str r0, [r7, #12] 8011e86: 60b9 str r1, [r7, #8] 8011e88: 4613 mov r3, r2 8011e8a: 80fb strh r3, [r7, #6] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8011e8c: 68fb ldr r3, [r7, #12] 8011e8e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011e92: b2db uxtb r3, r3 8011e94: 2b20 cmp r3, #32 8011e96: d121 bne.n 8011edc { if ((pData == NULL) || (Size == 0U)) 8011e98: 68bb ldr r3, [r7, #8] 8011e9a: 2b00 cmp r3, #0 8011e9c: d002 beq.n 8011ea4 8011e9e: 88fb ldrh r3, [r7, #6] 8011ea0: 2b00 cmp r3, #0 8011ea2: d101 bne.n 8011ea8 { return HAL_ERROR; 8011ea4: 2301 movs r3, #1 8011ea6: e01a b.n 8011ede } huart->pTxBuffPtr = pData; 8011ea8: 68fb ldr r3, [r7, #12] 8011eaa: 68ba ldr r2, [r7, #8] 8011eac: 621a str r2, [r3, #32] huart->TxXferSize = Size; 8011eae: 68fb ldr r3, [r7, #12] 8011eb0: 88fa ldrh r2, [r7, #6] 8011eb2: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8011eb4: 68fb ldr r3, [r7, #12] 8011eb6: 88fa ldrh r2, [r7, #6] 8011eb8: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 8011eba: 68fb ldr r3, [r7, #12] 8011ebc: 2200 movs r2, #0 8011ebe: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8011ec0: 68fb ldr r3, [r7, #12] 8011ec2: 2221 movs r2, #33 @ 0x21 8011ec4: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the UART Transmit data register empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); 8011ec8: 68fb ldr r3, [r7, #12] 8011eca: 681b ldr r3, [r3, #0] 8011ecc: 68da ldr r2, [r3, #12] 8011ece: 68fb ldr r3, [r7, #12] 8011ed0: 681b ldr r3, [r3, #0] 8011ed2: f042 0280 orr.w r2, r2, #128 @ 0x80 8011ed6: 60da str r2, [r3, #12] return HAL_OK; 8011ed8: 2300 movs r3, #0 8011eda: e000 b.n 8011ede } else { return HAL_BUSY; 8011edc: 2302 movs r3, #2 } } 8011ede: 4618 mov r0, r3 8011ee0: 3714 adds r7, #20 8011ee2: 46bd mov sp, r7 8011ee4: bc80 pop {r7} 8011ee6: 4770 bx lr 08011ee8 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8011ee8: b580 push {r7, lr} 8011eea: b08c sub sp, #48 @ 0x30 8011eec: af00 add r7, sp, #0 8011eee: 60f8 str r0, [r7, #12] 8011ef0: 60b9 str r1, [r7, #8] 8011ef2: 4613 mov r3, r2 8011ef4: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8011ef6: 68fb ldr r3, [r7, #12] 8011ef8: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8011efc: b2db uxtb r3, r3 8011efe: 2b20 cmp r3, #32 8011f00: d14a bne.n 8011f98 { if ((pData == NULL) || (Size == 0U)) 8011f02: 68bb ldr r3, [r7, #8] 8011f04: 2b00 cmp r3, #0 8011f06: d002 beq.n 8011f0e 8011f08: 88fb ldrh r3, [r7, #6] 8011f0a: 2b00 cmp r3, #0 8011f0c: d101 bne.n 8011f12 { return HAL_ERROR; 8011f0e: 2301 movs r3, #1 8011f10: e043 b.n 8011f9a } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8011f12: 68fb ldr r3, [r7, #12] 8011f14: 2201 movs r2, #1 8011f16: 631a str r2, [r3, #48] @ 0x30 huart->RxEventType = HAL_UART_RXEVENT_TC; 8011f18: 68fb ldr r3, [r7, #12] 8011f1a: 2200 movs r2, #0 8011f1c: 635a str r2, [r3, #52] @ 0x34 status = UART_Start_Receive_IT(huart, pData, Size); 8011f1e: 88fb ldrh r3, [r7, #6] 8011f20: 461a mov r2, r3 8011f22: 68b9 ldr r1, [r7, #8] 8011f24: 68f8 ldr r0, [r7, #12] 8011f26: f000 fc74 bl 8012812 8011f2a: 4603 mov r3, r0 8011f2c: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check Rx process has been successfully started */ if (status == HAL_OK) 8011f30: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8011f34: 2b00 cmp r3, #0 8011f36: d12c bne.n 8011f92 { if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8011f38: 68fb ldr r3, [r7, #12] 8011f3a: 6b1b ldr r3, [r3, #48] @ 0x30 8011f3c: 2b01 cmp r3, #1 8011f3e: d125 bne.n 8011f8c { __HAL_UART_CLEAR_IDLEFLAG(huart); 8011f40: 2300 movs r3, #0 8011f42: 613b str r3, [r7, #16] 8011f44: 68fb ldr r3, [r7, #12] 8011f46: 681b ldr r3, [r3, #0] 8011f48: 681b ldr r3, [r3, #0] 8011f4a: 613b str r3, [r7, #16] 8011f4c: 68fb ldr r3, [r7, #12] 8011f4e: 681b ldr r3, [r3, #0] 8011f50: 685b ldr r3, [r3, #4] 8011f52: 613b str r3, [r7, #16] 8011f54: 693b ldr r3, [r7, #16] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8011f56: 68fb ldr r3, [r7, #12] 8011f58: 681b ldr r3, [r3, #0] 8011f5a: 330c adds r3, #12 8011f5c: 61bb str r3, [r7, #24] */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011f5e: 69bb ldr r3, [r7, #24] 8011f60: e853 3f00 ldrex r3, [r3] 8011f64: 617b str r3, [r7, #20] return(result); 8011f66: 697b ldr r3, [r7, #20] 8011f68: f043 0310 orr.w r3, r3, #16 8011f6c: 62bb str r3, [r7, #40] @ 0x28 8011f6e: 68fb ldr r3, [r7, #12] 8011f70: 681b ldr r3, [r3, #0] 8011f72: 330c adds r3, #12 8011f74: 6aba ldr r2, [r7, #40] @ 0x28 8011f76: 627a str r2, [r7, #36] @ 0x24 8011f78: 623b str r3, [r7, #32] */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011f7a: 6a39 ldr r1, [r7, #32] 8011f7c: 6a7a ldr r2, [r7, #36] @ 0x24 8011f7e: e841 2300 strex r3, r2, [r1] 8011f82: 61fb str r3, [r7, #28] return(result); 8011f84: 69fb ldr r3, [r7, #28] 8011f86: 2b00 cmp r3, #0 8011f88: d1e5 bne.n 8011f56 8011f8a: e002 b.n 8011f92 { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8011f8c: 2301 movs r3, #1 8011f8e: f887 302f strb.w r3, [r7, #47] @ 0x2f } } return status; 8011f92: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8011f96: e000 b.n 8011f9a } else { return HAL_BUSY; 8011f98: 2302 movs r3, #2 } } 8011f9a: 4618 mov r0, r3 8011f9c: 3730 adds r7, #48 @ 0x30 8011f9e: 46bd mov sp, r7 8011fa0: bd80 pop {r7, pc} ... 08011fa4 : * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { 8011fa4: b580 push {r7, lr} 8011fa6: b0a2 sub sp, #136 @ 0x88 8011fa8: af00 add r7, sp, #0 8011faa: 6078 str r0, [r7, #4] uint32_t AbortCplt = 0x01U; 8011fac: 2301 movs r3, #1 8011fae: f8c7 3084 str.w r3, [r7, #132] @ 0x84 /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); 8011fb2: 687b ldr r3, [r7, #4] 8011fb4: 681b ldr r3, [r3, #0] 8011fb6: 330c adds r3, #12 8011fb8: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011fba: 6e3b ldr r3, [r7, #96] @ 0x60 8011fbc: e853 3f00 ldrex r3, [r3] 8011fc0: 65fb str r3, [r7, #92] @ 0x5c return(result); 8011fc2: 6dfb ldr r3, [r7, #92] @ 0x5c 8011fc4: f423 73f0 bic.w r3, r3, #480 @ 0x1e0 8011fc8: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8011fcc: 687b ldr r3, [r7, #4] 8011fce: 681b ldr r3, [r3, #0] 8011fd0: 330c adds r3, #12 8011fd2: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8011fd6: 66fa str r2, [r7, #108] @ 0x6c 8011fd8: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011fda: 6eb9 ldr r1, [r7, #104] @ 0x68 8011fdc: 6efa ldr r2, [r7, #108] @ 0x6c 8011fde: e841 2300 strex r3, r2, [r1] 8011fe2: 667b str r3, [r7, #100] @ 0x64 return(result); 8011fe4: 6e7b ldr r3, [r7, #100] @ 0x64 8011fe6: 2b00 cmp r3, #0 8011fe8: d1e3 bne.n 8011fb2 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8011fea: 687b ldr r3, [r7, #4] 8011fec: 681b ldr r3, [r3, #0] 8011fee: 3314 adds r3, #20 8011ff0: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011ff2: 6cfb ldr r3, [r7, #76] @ 0x4c 8011ff4: e853 3f00 ldrex r3, [r3] 8011ff8: 64bb str r3, [r7, #72] @ 0x48 return(result); 8011ffa: 6cbb ldr r3, [r7, #72] @ 0x48 8011ffc: f023 0301 bic.w r3, r3, #1 8012000: 67fb str r3, [r7, #124] @ 0x7c 8012002: 687b ldr r3, [r7, #4] 8012004: 681b ldr r3, [r3, #0] 8012006: 3314 adds r3, #20 8012008: 6ffa ldr r2, [r7, #124] @ 0x7c 801200a: 65ba str r2, [r7, #88] @ 0x58 801200c: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801200e: 6d79 ldr r1, [r7, #84] @ 0x54 8012010: 6dba ldr r2, [r7, #88] @ 0x58 8012012: e841 2300 strex r3, r2, [r1] 8012016: 653b str r3, [r7, #80] @ 0x50 return(result); 8012018: 6d3b ldr r3, [r7, #80] @ 0x50 801201a: 2b00 cmp r3, #0 801201c: d1e5 bne.n 8011fea /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 801201e: 687b ldr r3, [r7, #4] 8012020: 6b1b ldr r3, [r3, #48] @ 0x30 8012022: 2b01 cmp r3, #1 8012024: d119 bne.n 801205a { ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); 8012026: 687b ldr r3, [r7, #4] 8012028: 681b ldr r3, [r3, #0] 801202a: 330c adds r3, #12 801202c: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801202e: 6bbb ldr r3, [r7, #56] @ 0x38 8012030: e853 3f00 ldrex r3, [r3] 8012034: 637b str r3, [r7, #52] @ 0x34 return(result); 8012036: 6b7b ldr r3, [r7, #52] @ 0x34 8012038: f023 0310 bic.w r3, r3, #16 801203c: 67bb str r3, [r7, #120] @ 0x78 801203e: 687b ldr r3, [r7, #4] 8012040: 681b ldr r3, [r3, #0] 8012042: 330c adds r3, #12 8012044: 6fba ldr r2, [r7, #120] @ 0x78 8012046: 647a str r2, [r7, #68] @ 0x44 8012048: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801204a: 6c39 ldr r1, [r7, #64] @ 0x40 801204c: 6c7a ldr r2, [r7, #68] @ 0x44 801204e: e841 2300 strex r3, r2, [r1] 8012052: 63fb str r3, [r7, #60] @ 0x3c return(result); 8012054: 6bfb ldr r3, [r7, #60] @ 0x3c 8012056: 2b00 cmp r3, #0 8012058: d1e5 bne.n 8012026 } /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ if (huart->hdmatx != NULL) 801205a: 687b ldr r3, [r7, #4] 801205c: 6b9b ldr r3, [r3, #56] @ 0x38 801205e: 2b00 cmp r3, #0 8012060: d00f beq.n 8012082 { /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. Otherwise, set it to NULL */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) 8012062: 687b ldr r3, [r7, #4] 8012064: 681b ldr r3, [r3, #0] 8012066: 695b ldr r3, [r3, #20] 8012068: f003 0380 and.w r3, r3, #128 @ 0x80 801206c: 2b00 cmp r3, #0 801206e: d004 beq.n 801207a { huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; 8012070: 687b ldr r3, [r7, #4] 8012072: 6b9b ldr r3, [r3, #56] @ 0x38 8012074: 4a53 ldr r2, [pc, #332] @ (80121c4 ) 8012076: 635a str r2, [r3, #52] @ 0x34 8012078: e003 b.n 8012082 } else { huart->hdmatx->XferAbortCallback = NULL; 801207a: 687b ldr r3, [r7, #4] 801207c: 6b9b ldr r3, [r3, #56] @ 0x38 801207e: 2200 movs r2, #0 8012080: 635a str r2, [r3, #52] @ 0x34 } } /* DMA Rx Handle is valid */ if (huart->hdmarx != NULL) 8012082: 687b ldr r3, [r7, #4] 8012084: 6bdb ldr r3, [r3, #60] @ 0x3c 8012086: 2b00 cmp r3, #0 8012088: d00f beq.n 80120aa { /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. Otherwise, set it to NULL */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801208a: 687b ldr r3, [r7, #4] 801208c: 681b ldr r3, [r3, #0] 801208e: 695b ldr r3, [r3, #20] 8012090: f003 0340 and.w r3, r3, #64 @ 0x40 8012094: 2b00 cmp r3, #0 8012096: d004 beq.n 80120a2 { huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; 8012098: 687b ldr r3, [r7, #4] 801209a: 6bdb ldr r3, [r3, #60] @ 0x3c 801209c: 4a4a ldr r2, [pc, #296] @ (80121c8 ) 801209e: 635a str r2, [r3, #52] @ 0x34 80120a0: e003 b.n 80120aa } else { huart->hdmarx->XferAbortCallback = NULL; 80120a2: 687b ldr r3, [r7, #4] 80120a4: 6bdb ldr r3, [r3, #60] @ 0x3c 80120a6: 2200 movs r2, #0 80120a8: 635a str r2, [r3, #52] @ 0x34 } } /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) 80120aa: 687b ldr r3, [r7, #4] 80120ac: 681b ldr r3, [r3, #0] 80120ae: 695b ldr r3, [r3, #20] 80120b0: f003 0380 and.w r3, r3, #128 @ 0x80 80120b4: 2b00 cmp r3, #0 80120b6: d02d beq.n 8012114 { /* Disable DMA Tx at UART level */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 80120b8: 687b ldr r3, [r7, #4] 80120ba: 681b ldr r3, [r3, #0] 80120bc: 3314 adds r3, #20 80120be: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80120c0: 6a7b ldr r3, [r7, #36] @ 0x24 80120c2: e853 3f00 ldrex r3, [r3] 80120c6: 623b str r3, [r7, #32] return(result); 80120c8: 6a3b ldr r3, [r7, #32] 80120ca: f023 0380 bic.w r3, r3, #128 @ 0x80 80120ce: 677b str r3, [r7, #116] @ 0x74 80120d0: 687b ldr r3, [r7, #4] 80120d2: 681b ldr r3, [r3, #0] 80120d4: 3314 adds r3, #20 80120d6: 6f7a ldr r2, [r7, #116] @ 0x74 80120d8: 633a str r2, [r7, #48] @ 0x30 80120da: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80120dc: 6af9 ldr r1, [r7, #44] @ 0x2c 80120de: 6b3a ldr r2, [r7, #48] @ 0x30 80120e0: e841 2300 strex r3, r2, [r1] 80120e4: 62bb str r3, [r7, #40] @ 0x28 return(result); 80120e6: 6abb ldr r3, [r7, #40] @ 0x28 80120e8: 2b00 cmp r3, #0 80120ea: d1e5 bne.n 80120b8 /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) 80120ec: 687b ldr r3, [r7, #4] 80120ee: 6b9b ldr r3, [r3, #56] @ 0x38 80120f0: 2b00 cmp r3, #0 80120f2: d00f beq.n 8012114 { /* UART Tx DMA Abort callback has already been initialised : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA TX */ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) 80120f4: 687b ldr r3, [r7, #4] 80120f6: 6b9b ldr r3, [r3, #56] @ 0x38 80120f8: 4618 mov r0, r3 80120fa: f7fd f99d bl 800f438 80120fe: 4603 mov r3, r0 8012100: 2b00 cmp r3, #0 8012102: d004 beq.n 801210e { huart->hdmatx->XferAbortCallback = NULL; 8012104: 687b ldr r3, [r7, #4] 8012106: 6b9b ldr r3, [r3, #56] @ 0x38 8012108: 2200 movs r2, #0 801210a: 635a str r2, [r3, #52] @ 0x34 801210c: e002 b.n 8012114 } else { AbortCplt = 0x00U; 801210e: 2300 movs r3, #0 8012110: f8c7 3084 str.w r3, [r7, #132] @ 0x84 } } } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8012114: 687b ldr r3, [r7, #4] 8012116: 681b ldr r3, [r3, #0] 8012118: 695b ldr r3, [r3, #20] 801211a: f003 0340 and.w r3, r3, #64 @ 0x40 801211e: 2b00 cmp r3, #0 8012120: d030 beq.n 8012184 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8012122: 687b ldr r3, [r7, #4] 8012124: 681b ldr r3, [r3, #0] 8012126: 3314 adds r3, #20 8012128: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801212a: 693b ldr r3, [r7, #16] 801212c: e853 3f00 ldrex r3, [r3] 8012130: 60fb str r3, [r7, #12] return(result); 8012132: 68fb ldr r3, [r7, #12] 8012134: f023 0340 bic.w r3, r3, #64 @ 0x40 8012138: 673b str r3, [r7, #112] @ 0x70 801213a: 687b ldr r3, [r7, #4] 801213c: 681b ldr r3, [r3, #0] 801213e: 3314 adds r3, #20 8012140: 6f3a ldr r2, [r7, #112] @ 0x70 8012142: 61fa str r2, [r7, #28] 8012144: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012146: 69b9 ldr r1, [r7, #24] 8012148: 69fa ldr r2, [r7, #28] 801214a: e841 2300 strex r3, r2, [r1] 801214e: 617b str r3, [r7, #20] return(result); 8012150: 697b ldr r3, [r7, #20] 8012152: 2b00 cmp r3, #0 8012154: d1e5 bne.n 8012122 /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) 8012156: 687b ldr r3, [r7, #4] 8012158: 6bdb ldr r3, [r3, #60] @ 0x3c 801215a: 2b00 cmp r3, #0 801215c: d012 beq.n 8012184 { /* UART Rx DMA Abort callback has already been initialised : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 801215e: 687b ldr r3, [r7, #4] 8012160: 6bdb ldr r3, [r3, #60] @ 0x3c 8012162: 4618 mov r0, r3 8012164: f7fd f968 bl 800f438 8012168: 4603 mov r3, r0 801216a: 2b00 cmp r3, #0 801216c: d007 beq.n 801217e { huart->hdmarx->XferAbortCallback = NULL; 801216e: 687b ldr r3, [r7, #4] 8012170: 6bdb ldr r3, [r3, #60] @ 0x3c 8012172: 2200 movs r2, #0 8012174: 635a str r2, [r3, #52] @ 0x34 AbortCplt = 0x01U; 8012176: 2301 movs r3, #1 8012178: f8c7 3084 str.w r3, [r7, #132] @ 0x84 801217c: e002 b.n 8012184 } else { AbortCplt = 0x00U; 801217e: 2300 movs r3, #0 8012180: f8c7 3084 str.w r3, [r7, #132] @ 0x84 } } } /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (AbortCplt == 0x01U) 8012184: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8012188: 2b01 cmp r3, #1 801218a: d116 bne.n 80121ba { /* Reset Tx and Rx transfer counters */ huart->TxXferCount = 0x00U; 801218c: 687b ldr r3, [r7, #4] 801218e: 2200 movs r2, #0 8012190: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 8012192: 687b ldr r3, [r7, #4] 8012194: 2200 movs r2, #0 8012196: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012198: 687b ldr r3, [r7, #4] 801219a: 2200 movs r2, #0 801219c: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 801219e: 687b ldr r3, [r7, #4] 80121a0: 2220 movs r2, #32 80121a2: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 80121a6: 687b ldr r3, [r7, #4] 80121a8: 2220 movs r2, #32 80121aa: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80121ae: 687b ldr r3, [r7, #4] 80121b0: 2200 movs r2, #0 80121b2: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 80121b4: 6878 ldr r0, [r7, #4] 80121b6: f000 faad bl 8012714 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 80121ba: 2300 movs r3, #0 } 80121bc: 4618 mov r0, r3 80121be: 3788 adds r7, #136 @ 0x88 80121c0: 46bd mov sp, r7 80121c2: bd80 pop {r7, pc} 80121c4: 08012971 .word 0x08012971 80121c8: 080129d1 .word 0x080129d1 080121cc : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 80121cc: b580 push {r7, lr} 80121ce: b0ba sub sp, #232 @ 0xe8 80121d0: af00 add r7, sp, #0 80121d2: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 80121d4: 687b ldr r3, [r7, #4] 80121d6: 681b ldr r3, [r3, #0] 80121d8: 681b ldr r3, [r3, #0] 80121da: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 80121de: 687b ldr r3, [r7, #4] 80121e0: 681b ldr r3, [r3, #0] 80121e2: 68db ldr r3, [r3, #12] 80121e4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 80121e8: 687b ldr r3, [r7, #4] 80121ea: 681b ldr r3, [r3, #0] 80121ec: 695b ldr r3, [r3, #20] 80121ee: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 80121f2: 2300 movs r3, #0 80121f4: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 80121f8: 2300 movs r3, #0 80121fa: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 80121fe: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012202: f003 030f and.w r3, r3, #15 8012206: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 801220a: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 801220e: 2b00 cmp r3, #0 8012210: d10f bne.n 8012232 { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8012212: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012216: f003 0320 and.w r3, r3, #32 801221a: 2b00 cmp r3, #0 801221c: d009 beq.n 8012232 801221e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012222: f003 0320 and.w r3, r3, #32 8012226: 2b00 cmp r3, #0 8012228: d003 beq.n 8012232 { UART_Receive_IT(huart); 801222a: 6878 ldr r0, [r7, #4] 801222c: f000 fc67 bl 8012afe return; 8012230: e25b b.n 80126ea } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 8012232: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8012236: 2b00 cmp r3, #0 8012238: f000 80de beq.w 80123f8 801223c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8012240: f003 0301 and.w r3, r3, #1 8012244: 2b00 cmp r3, #0 8012246: d106 bne.n 8012256 || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8012248: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801224c: f403 7390 and.w r3, r3, #288 @ 0x120 8012250: 2b00 cmp r3, #0 8012252: f000 80d1 beq.w 80123f8 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 8012256: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801225a: f003 0301 and.w r3, r3, #1 801225e: 2b00 cmp r3, #0 8012260: d00b beq.n 801227a 8012262: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012266: f403 7380 and.w r3, r3, #256 @ 0x100 801226a: 2b00 cmp r3, #0 801226c: d005 beq.n 801227a { huart->ErrorCode |= HAL_UART_ERROR_PE; 801226e: 687b ldr r3, [r7, #4] 8012270: 6c5b ldr r3, [r3, #68] @ 0x44 8012272: f043 0201 orr.w r2, r3, #1 8012276: 687b ldr r3, [r7, #4] 8012278: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 801227a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801227e: f003 0304 and.w r3, r3, #4 8012282: 2b00 cmp r3, #0 8012284: d00b beq.n 801229e 8012286: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 801228a: f003 0301 and.w r3, r3, #1 801228e: 2b00 cmp r3, #0 8012290: d005 beq.n 801229e { huart->ErrorCode |= HAL_UART_ERROR_NE; 8012292: 687b ldr r3, [r7, #4] 8012294: 6c5b ldr r3, [r3, #68] @ 0x44 8012296: f043 0202 orr.w r2, r3, #2 801229a: 687b ldr r3, [r7, #4] 801229c: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 801229e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80122a2: f003 0302 and.w r3, r3, #2 80122a6: 2b00 cmp r3, #0 80122a8: d00b beq.n 80122c2 80122aa: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80122ae: f003 0301 and.w r3, r3, #1 80122b2: 2b00 cmp r3, #0 80122b4: d005 beq.n 80122c2 { huart->ErrorCode |= HAL_UART_ERROR_FE; 80122b6: 687b ldr r3, [r7, #4] 80122b8: 6c5b ldr r3, [r3, #68] @ 0x44 80122ba: f043 0204 orr.w r2, r3, #4 80122be: 687b ldr r3, [r7, #4] 80122c0: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 80122c2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80122c6: f003 0308 and.w r3, r3, #8 80122ca: 2b00 cmp r3, #0 80122cc: d011 beq.n 80122f2 80122ce: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80122d2: f003 0320 and.w r3, r3, #32 80122d6: 2b00 cmp r3, #0 80122d8: d105 bne.n 80122e6 || ((cr3its & USART_CR3_EIE) != RESET))) 80122da: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80122de: f003 0301 and.w r3, r3, #1 80122e2: 2b00 cmp r3, #0 80122e4: d005 beq.n 80122f2 { huart->ErrorCode |= HAL_UART_ERROR_ORE; 80122e6: 687b ldr r3, [r7, #4] 80122e8: 6c5b ldr r3, [r3, #68] @ 0x44 80122ea: f043 0208 orr.w r2, r3, #8 80122ee: 687b ldr r3, [r7, #4] 80122f0: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 80122f2: 687b ldr r3, [r7, #4] 80122f4: 6c5b ldr r3, [r3, #68] @ 0x44 80122f6: 2b00 cmp r3, #0 80122f8: f000 81f2 beq.w 80126e0 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 80122fc: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012300: f003 0320 and.w r3, r3, #32 8012304: 2b00 cmp r3, #0 8012306: d008 beq.n 801231a 8012308: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801230c: f003 0320 and.w r3, r3, #32 8012310: 2b00 cmp r3, #0 8012312: d002 beq.n 801231a { UART_Receive_IT(huart); 8012314: 6878 ldr r0, [r7, #4] 8012316: f000 fbf2 bl 8012afe } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 801231a: 687b ldr r3, [r7, #4] 801231c: 681b ldr r3, [r3, #0] 801231e: 695b ldr r3, [r3, #20] 8012320: f003 0340 and.w r3, r3, #64 @ 0x40 8012324: 2b00 cmp r3, #0 8012326: bf14 ite ne 8012328: 2301 movne r3, #1 801232a: 2300 moveq r3, #0 801232c: b2db uxtb r3, r3 801232e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8012332: 687b ldr r3, [r7, #4] 8012334: 6c5b ldr r3, [r3, #68] @ 0x44 8012336: f003 0308 and.w r3, r3, #8 801233a: 2b00 cmp r3, #0 801233c: d103 bne.n 8012346 801233e: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8012342: 2b00 cmp r3, #0 8012344: d04f beq.n 80123e6 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8012346: 6878 ldr r0, [r7, #4] 8012348: f000 fa9c bl 8012884 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801234c: 687b ldr r3, [r7, #4] 801234e: 681b ldr r3, [r3, #0] 8012350: 695b ldr r3, [r3, #20] 8012352: f003 0340 and.w r3, r3, #64 @ 0x40 8012356: 2b00 cmp r3, #0 8012358: d041 beq.n 80123de { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 801235a: 687b ldr r3, [r7, #4] 801235c: 681b ldr r3, [r3, #0] 801235e: 3314 adds r3, #20 8012360: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012364: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8012368: e853 3f00 ldrex r3, [r3] 801236c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8012370: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8012374: f023 0340 bic.w r3, r3, #64 @ 0x40 8012378: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 801237c: 687b ldr r3, [r7, #4] 801237e: 681b ldr r3, [r3, #0] 8012380: 3314 adds r3, #20 8012382: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8012386: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 801238a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801238e: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8012392: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8012396: e841 2300 strex r3, r2, [r1] 801239a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 801239e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80123a2: 2b00 cmp r3, #0 80123a4: d1d9 bne.n 801235a /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 80123a6: 687b ldr r3, [r7, #4] 80123a8: 6bdb ldr r3, [r3, #60] @ 0x3c 80123aa: 2b00 cmp r3, #0 80123ac: d013 beq.n 80123d6 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 80123ae: 687b ldr r3, [r7, #4] 80123b0: 6bdb ldr r3, [r3, #60] @ 0x3c 80123b2: 4a7e ldr r2, [pc, #504] @ (80125ac ) 80123b4: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 80123b6: 687b ldr r3, [r7, #4] 80123b8: 6bdb ldr r3, [r3, #60] @ 0x3c 80123ba: 4618 mov r0, r3 80123bc: f7fd f83c bl 800f438 80123c0: 4603 mov r3, r0 80123c2: 2b00 cmp r3, #0 80123c4: d016 beq.n 80123f4 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 80123c6: 687b ldr r3, [r7, #4] 80123c8: 6bdb ldr r3, [r3, #60] @ 0x3c 80123ca: 6b5b ldr r3, [r3, #52] @ 0x34 80123cc: 687a ldr r2, [r7, #4] 80123ce: 6bd2 ldr r2, [r2, #60] @ 0x3c 80123d0: 4610 mov r0, r2 80123d2: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80123d4: e00e b.n 80123f4 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80123d6: 6878 ldr r0, [r7, #4] 80123d8: f000 f993 bl 8012702 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80123dc: e00a b.n 80123f4 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80123de: 6878 ldr r0, [r7, #4] 80123e0: f000 f98f bl 8012702 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80123e4: e006 b.n 80123f4 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80123e6: 6878 ldr r0, [r7, #4] 80123e8: f000 f98b bl 8012702 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80123ec: 687b ldr r3, [r7, #4] 80123ee: 2200 movs r2, #0 80123f0: 645a str r2, [r3, #68] @ 0x44 } } return; 80123f2: e175 b.n 80126e0 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80123f4: bf00 nop return; 80123f6: e173 b.n 80126e0 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80123f8: 687b ldr r3, [r7, #4] 80123fa: 6b1b ldr r3, [r3, #48] @ 0x30 80123fc: 2b01 cmp r3, #1 80123fe: f040 814f bne.w 80126a0 && ((isrflags & USART_SR_IDLE) != 0U) 8012402: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012406: f003 0310 and.w r3, r3, #16 801240a: 2b00 cmp r3, #0 801240c: f000 8148 beq.w 80126a0 && ((cr1its & USART_SR_IDLE) != 0U)) 8012410: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012414: f003 0310 and.w r3, r3, #16 8012418: 2b00 cmp r3, #0 801241a: f000 8141 beq.w 80126a0 { __HAL_UART_CLEAR_IDLEFLAG(huart); 801241e: 2300 movs r3, #0 8012420: 60bb str r3, [r7, #8] 8012422: 687b ldr r3, [r7, #4] 8012424: 681b ldr r3, [r3, #0] 8012426: 681b ldr r3, [r3, #0] 8012428: 60bb str r3, [r7, #8] 801242a: 687b ldr r3, [r7, #4] 801242c: 681b ldr r3, [r3, #0] 801242e: 685b ldr r3, [r3, #4] 8012430: 60bb str r3, [r7, #8] 8012432: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8012434: 687b ldr r3, [r7, #4] 8012436: 681b ldr r3, [r3, #0] 8012438: 695b ldr r3, [r3, #20] 801243a: f003 0340 and.w r3, r3, #64 @ 0x40 801243e: 2b00 cmp r3, #0 8012440: f000 80b6 beq.w 80125b0 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8012444: 687b ldr r3, [r7, #4] 8012446: 6bdb ldr r3, [r3, #60] @ 0x3c 8012448: 681b ldr r3, [r3, #0] 801244a: 685b ldr r3, [r3, #4] 801244c: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8012450: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8012454: 2b00 cmp r3, #0 8012456: f000 8145 beq.w 80126e4 && (nb_remaining_rx_data < huart->RxXferSize)) 801245a: 687b ldr r3, [r7, #4] 801245c: 8d9b ldrh r3, [r3, #44] @ 0x2c 801245e: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8012462: 429a cmp r2, r3 8012464: f080 813e bcs.w 80126e4 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8012468: 687b ldr r3, [r7, #4] 801246a: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 801246e: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8012470: 687b ldr r3, [r7, #4] 8012472: 6bdb ldr r3, [r3, #60] @ 0x3c 8012474: 699b ldr r3, [r3, #24] 8012476: 2b20 cmp r3, #32 8012478: f000 8088 beq.w 801258c { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 801247c: 687b ldr r3, [r7, #4] 801247e: 681b ldr r3, [r3, #0] 8012480: 330c adds r3, #12 8012482: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012486: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 801248a: e853 3f00 ldrex r3, [r3] 801248e: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8012492: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8012496: f423 7380 bic.w r3, r3, #256 @ 0x100 801249a: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 801249e: 687b ldr r3, [r7, #4] 80124a0: 681b ldr r3, [r3, #0] 80124a2: 330c adds r3, #12 80124a4: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 80124a8: f8c7 2094 str.w r2, [r7, #148] @ 0x94 80124ac: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80124b0: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 80124b4: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 80124b8: e841 2300 strex r3, r2, [r1] 80124bc: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 80124c0: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 80124c4: 2b00 cmp r3, #0 80124c6: d1d9 bne.n 801247c ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80124c8: 687b ldr r3, [r7, #4] 80124ca: 681b ldr r3, [r3, #0] 80124cc: 3314 adds r3, #20 80124ce: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80124d0: 6f7b ldr r3, [r7, #116] @ 0x74 80124d2: e853 3f00 ldrex r3, [r3] 80124d6: 673b str r3, [r7, #112] @ 0x70 return(result); 80124d8: 6f3b ldr r3, [r7, #112] @ 0x70 80124da: f023 0301 bic.w r3, r3, #1 80124de: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 80124e2: 687b ldr r3, [r7, #4] 80124e4: 681b ldr r3, [r3, #0] 80124e6: 3314 adds r3, #20 80124e8: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 80124ec: f8c7 2080 str.w r2, [r7, #128] @ 0x80 80124f0: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80124f2: 6ff9 ldr r1, [r7, #124] @ 0x7c 80124f4: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 80124f8: e841 2300 strex r3, r2, [r1] 80124fc: 67bb str r3, [r7, #120] @ 0x78 return(result); 80124fe: 6fbb ldr r3, [r7, #120] @ 0x78 8012500: 2b00 cmp r3, #0 8012502: d1e1 bne.n 80124c8 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8012504: 687b ldr r3, [r7, #4] 8012506: 681b ldr r3, [r3, #0] 8012508: 3314 adds r3, #20 801250a: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801250c: 6e3b ldr r3, [r7, #96] @ 0x60 801250e: e853 3f00 ldrex r3, [r3] 8012512: 65fb str r3, [r7, #92] @ 0x5c return(result); 8012514: 6dfb ldr r3, [r7, #92] @ 0x5c 8012516: f023 0340 bic.w r3, r3, #64 @ 0x40 801251a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 801251e: 687b ldr r3, [r7, #4] 8012520: 681b ldr r3, [r3, #0] 8012522: 3314 adds r3, #20 8012524: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8012528: 66fa str r2, [r7, #108] @ 0x6c 801252a: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801252c: 6eb9 ldr r1, [r7, #104] @ 0x68 801252e: 6efa ldr r2, [r7, #108] @ 0x6c 8012530: e841 2300 strex r3, r2, [r1] 8012534: 667b str r3, [r7, #100] @ 0x64 return(result); 8012536: 6e7b ldr r3, [r7, #100] @ 0x64 8012538: 2b00 cmp r3, #0 801253a: d1e3 bne.n 8012504 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 801253c: 687b ldr r3, [r7, #4] 801253e: 2220 movs r2, #32 8012540: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012544: 687b ldr r3, [r7, #4] 8012546: 2200 movs r2, #0 8012548: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801254a: 687b ldr r3, [r7, #4] 801254c: 681b ldr r3, [r3, #0] 801254e: 330c adds r3, #12 8012550: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012552: 6cfb ldr r3, [r7, #76] @ 0x4c 8012554: e853 3f00 ldrex r3, [r3] 8012558: 64bb str r3, [r7, #72] @ 0x48 return(result); 801255a: 6cbb ldr r3, [r7, #72] @ 0x48 801255c: f023 0310 bic.w r3, r3, #16 8012560: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8012564: 687b ldr r3, [r7, #4] 8012566: 681b ldr r3, [r3, #0] 8012568: 330c adds r3, #12 801256a: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 801256e: 65ba str r2, [r7, #88] @ 0x58 8012570: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012572: 6d79 ldr r1, [r7, #84] @ 0x54 8012574: 6dba ldr r2, [r7, #88] @ 0x58 8012576: e841 2300 strex r3, r2, [r1] 801257a: 653b str r3, [r7, #80] @ 0x50 return(result); 801257c: 6d3b ldr r3, [r7, #80] @ 0x50 801257e: 2b00 cmp r3, #0 8012580: d1e3 bne.n 801254a /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8012582: 687b ldr r3, [r7, #4] 8012584: 6bdb ldr r3, [r3, #60] @ 0x3c 8012586: 4618 mov r0, r3 8012588: f7fc ff1b bl 800f3c2 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 801258c: 687b ldr r3, [r7, #4] 801258e: 2202 movs r2, #2 8012590: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8012592: 687b ldr r3, [r7, #4] 8012594: 8d9a ldrh r2, [r3, #44] @ 0x2c 8012596: 687b ldr r3, [r7, #4] 8012598: 8ddb ldrh r3, [r3, #46] @ 0x2e 801259a: b29b uxth r3, r3 801259c: 1ad3 subs r3, r2, r3 801259e: b29b uxth r3, r3 80125a0: 4619 mov r1, r3 80125a2: 6878 ldr r0, [r7, #4] 80125a4: f7fa f802 bl 800c5ac #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 80125a8: e09c b.n 80126e4 80125aa: bf00 nop 80125ac: 08012949 .word 0x08012949 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 80125b0: 687b ldr r3, [r7, #4] 80125b2: 8d9a ldrh r2, [r3, #44] @ 0x2c 80125b4: 687b ldr r3, [r7, #4] 80125b6: 8ddb ldrh r3, [r3, #46] @ 0x2e 80125b8: b29b uxth r3, r3 80125ba: 1ad3 subs r3, r2, r3 80125bc: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 80125c0: 687b ldr r3, [r7, #4] 80125c2: 8ddb ldrh r3, [r3, #46] @ 0x2e 80125c4: b29b uxth r3, r3 80125c6: 2b00 cmp r3, #0 80125c8: f000 808e beq.w 80126e8 && (nb_rx_data > 0U)) 80125cc: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 80125d0: 2b00 cmp r3, #0 80125d2: f000 8089 beq.w 80126e8 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 80125d6: 687b ldr r3, [r7, #4] 80125d8: 681b ldr r3, [r3, #0] 80125da: 330c adds r3, #12 80125dc: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80125de: 6bbb ldr r3, [r7, #56] @ 0x38 80125e0: e853 3f00 ldrex r3, [r3] 80125e4: 637b str r3, [r7, #52] @ 0x34 return(result); 80125e6: 6b7b ldr r3, [r7, #52] @ 0x34 80125e8: f423 7390 bic.w r3, r3, #288 @ 0x120 80125ec: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 80125f0: 687b ldr r3, [r7, #4] 80125f2: 681b ldr r3, [r3, #0] 80125f4: 330c adds r3, #12 80125f6: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 80125fa: 647a str r2, [r7, #68] @ 0x44 80125fc: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80125fe: 6c39 ldr r1, [r7, #64] @ 0x40 8012600: 6c7a ldr r2, [r7, #68] @ 0x44 8012602: e841 2300 strex r3, r2, [r1] 8012606: 63fb str r3, [r7, #60] @ 0x3c return(result); 8012608: 6bfb ldr r3, [r7, #60] @ 0x3c 801260a: 2b00 cmp r3, #0 801260c: d1e3 bne.n 80125d6 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 801260e: 687b ldr r3, [r7, #4] 8012610: 681b ldr r3, [r3, #0] 8012612: 3314 adds r3, #20 8012614: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012616: 6a7b ldr r3, [r7, #36] @ 0x24 8012618: e853 3f00 ldrex r3, [r3] 801261c: 623b str r3, [r7, #32] return(result); 801261e: 6a3b ldr r3, [r7, #32] 8012620: f023 0301 bic.w r3, r3, #1 8012624: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8012628: 687b ldr r3, [r7, #4] 801262a: 681b ldr r3, [r3, #0] 801262c: 3314 adds r3, #20 801262e: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8012632: 633a str r2, [r7, #48] @ 0x30 8012634: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012636: 6af9 ldr r1, [r7, #44] @ 0x2c 8012638: 6b3a ldr r2, [r7, #48] @ 0x30 801263a: e841 2300 strex r3, r2, [r1] 801263e: 62bb str r3, [r7, #40] @ 0x28 return(result); 8012640: 6abb ldr r3, [r7, #40] @ 0x28 8012642: 2b00 cmp r3, #0 8012644: d1e3 bne.n 801260e /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012646: 687b ldr r3, [r7, #4] 8012648: 2220 movs r2, #32 801264a: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801264e: 687b ldr r3, [r7, #4] 8012650: 2200 movs r2, #0 8012652: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012654: 687b ldr r3, [r7, #4] 8012656: 681b ldr r3, [r3, #0] 8012658: 330c adds r3, #12 801265a: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801265c: 693b ldr r3, [r7, #16] 801265e: e853 3f00 ldrex r3, [r3] 8012662: 60fb str r3, [r7, #12] return(result); 8012664: 68fb ldr r3, [r7, #12] 8012666: f023 0310 bic.w r3, r3, #16 801266a: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 801266e: 687b ldr r3, [r7, #4] 8012670: 681b ldr r3, [r3, #0] 8012672: 330c adds r3, #12 8012674: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 8012678: 61fa str r2, [r7, #28] 801267a: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801267c: 69b9 ldr r1, [r7, #24] 801267e: 69fa ldr r2, [r7, #28] 8012680: e841 2300 strex r3, r2, [r1] 8012684: 617b str r3, [r7, #20] return(result); 8012686: 697b ldr r3, [r7, #20] 8012688: 2b00 cmp r3, #0 801268a: d1e3 bne.n 8012654 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 801268c: 687b ldr r3, [r7, #4] 801268e: 2202 movs r2, #2 8012690: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8012692: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8012696: 4619 mov r1, r3 8012698: 6878 ldr r0, [r7, #4] 801269a: f7f9 ff87 bl 800c5ac #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 801269e: e023 b.n 80126e8 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 80126a0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80126a4: f003 0380 and.w r3, r3, #128 @ 0x80 80126a8: 2b00 cmp r3, #0 80126aa: d009 beq.n 80126c0 80126ac: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80126b0: f003 0380 and.w r3, r3, #128 @ 0x80 80126b4: 2b00 cmp r3, #0 80126b6: d003 beq.n 80126c0 { UART_Transmit_IT(huart); 80126b8: 6878 ldr r0, [r7, #4] 80126ba: f000 f9b9 bl 8012a30 return; 80126be: e014 b.n 80126ea } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 80126c0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80126c4: f003 0340 and.w r3, r3, #64 @ 0x40 80126c8: 2b00 cmp r3, #0 80126ca: d00e beq.n 80126ea 80126cc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80126d0: f003 0340 and.w r3, r3, #64 @ 0x40 80126d4: 2b00 cmp r3, #0 80126d6: d008 beq.n 80126ea { UART_EndTransmit_IT(huart); 80126d8: 6878 ldr r0, [r7, #4] 80126da: f000 f9f8 bl 8012ace return; 80126de: e004 b.n 80126ea return; 80126e0: bf00 nop 80126e2: e002 b.n 80126ea return; 80126e4: bf00 nop 80126e6: e000 b.n 80126ea return; 80126e8: bf00 nop } } 80126ea: 37e8 adds r7, #232 @ 0xe8 80126ec: 46bd mov sp, r7 80126ee: bd80 pop {r7, pc} 080126f0 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 80126f0: b480 push {r7} 80126f2: b083 sub sp, #12 80126f4: af00 add r7, sp, #0 80126f6: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback could be implemented in the user file */ } 80126f8: bf00 nop 80126fa: 370c adds r7, #12 80126fc: 46bd mov sp, r7 80126fe: bc80 pop {r7} 8012700: 4770 bx lr 08012702 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8012702: b480 push {r7} 8012704: b083 sub sp, #12 8012706: af00 add r7, sp, #0 8012708: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback could be implemented in the user file */ } 801270a: bf00 nop 801270c: 370c adds r7, #12 801270e: 46bd mov sp, r7 8012710: bc80 pop {r7} 8012712: 4770 bx lr 08012714 : * @brief UART Abort Complete callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) { 8012714: b480 push {r7} 8012716: b083 sub sp, #12 8012718: af00 add r7, sp, #0 801271a: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_AbortCpltCallback can be implemented in the user file. */ } 801271c: bf00 nop 801271e: 370c adds r7, #12 8012720: 46bd mov sp, r7 8012722: bc80 pop {r7} 8012724: 4770 bx lr 08012726 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL state */ HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) { 8012726: b480 push {r7} 8012728: b085 sub sp, #20 801272a: af00 add r7, sp, #0 801272c: 6078 str r0, [r7, #4] uint32_t temp1 = 0x00U, temp2 = 0x00U; 801272e: 2300 movs r3, #0 8012730: 60fb str r3, [r7, #12] 8012732: 2300 movs r3, #0 8012734: 60bb str r3, [r7, #8] temp1 = huart->gState; 8012736: 687b ldr r3, [r7, #4] 8012738: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 801273c: b2db uxtb r3, r3 801273e: 60fb str r3, [r7, #12] temp2 = huart->RxState; 8012740: 687b ldr r3, [r7, #4] 8012742: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8012746: b2db uxtb r3, r3 8012748: 60bb str r3, [r7, #8] return (HAL_UART_StateTypeDef)(temp1 | temp2); 801274a: 68fb ldr r3, [r7, #12] 801274c: b2da uxtb r2, r3 801274e: 68bb ldr r3, [r7, #8] 8012750: b2db uxtb r3, r3 8012752: 4313 orrs r3, r2 8012754: b2db uxtb r3, r3 } 8012756: 4618 mov r0, r3 8012758: 3714 adds r7, #20 801275a: 46bd mov sp, r7 801275c: bc80 pop {r7} 801275e: 4770 bx lr 08012760 : * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8012760: b580 push {r7, lr} 8012762: b086 sub sp, #24 8012764: af00 add r7, sp, #0 8012766: 60f8 str r0, [r7, #12] 8012768: 60b9 str r1, [r7, #8] 801276a: 603b str r3, [r7, #0] 801276c: 4613 mov r3, r2 801276e: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8012770: e03b b.n 80127ea { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8012772: 6a3b ldr r3, [r7, #32] 8012774: f1b3 3fff cmp.w r3, #4294967295 8012778: d037 beq.n 80127ea { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 801277a: f7fb f8ef bl 800d95c 801277e: 4602 mov r2, r0 8012780: 683b ldr r3, [r7, #0] 8012782: 1ad3 subs r3, r2, r3 8012784: 6a3a ldr r2, [r7, #32] 8012786: 429a cmp r2, r3 8012788: d302 bcc.n 8012790 801278a: 6a3b ldr r3, [r7, #32] 801278c: 2b00 cmp r3, #0 801278e: d101 bne.n 8012794 { return HAL_TIMEOUT; 8012790: 2303 movs r3, #3 8012792: e03a b.n 801280a } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 8012794: 68fb ldr r3, [r7, #12] 8012796: 681b ldr r3, [r3, #0] 8012798: 68db ldr r3, [r3, #12] 801279a: f003 0304 and.w r3, r3, #4 801279e: 2b00 cmp r3, #0 80127a0: d023 beq.n 80127ea 80127a2: 68bb ldr r3, [r7, #8] 80127a4: 2b80 cmp r3, #128 @ 0x80 80127a6: d020 beq.n 80127ea 80127a8: 68bb ldr r3, [r7, #8] 80127aa: 2b40 cmp r3, #64 @ 0x40 80127ac: d01d beq.n 80127ea { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 80127ae: 68fb ldr r3, [r7, #12] 80127b0: 681b ldr r3, [r3, #0] 80127b2: 681b ldr r3, [r3, #0] 80127b4: f003 0308 and.w r3, r3, #8 80127b8: 2b08 cmp r3, #8 80127ba: d116 bne.n 80127ea { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_OREFLAG(huart); 80127bc: 2300 movs r3, #0 80127be: 617b str r3, [r7, #20] 80127c0: 68fb ldr r3, [r7, #12] 80127c2: 681b ldr r3, [r3, #0] 80127c4: 681b ldr r3, [r3, #0] 80127c6: 617b str r3, [r7, #20] 80127c8: 68fb ldr r3, [r7, #12] 80127ca: 681b ldr r3, [r3, #0] 80127cc: 685b ldr r3, [r3, #4] 80127ce: 617b str r3, [r7, #20] 80127d0: 697b ldr r3, [r7, #20] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 80127d2: 68f8 ldr r0, [r7, #12] 80127d4: f000 f856 bl 8012884 huart->ErrorCode = HAL_UART_ERROR_ORE; 80127d8: 68fb ldr r3, [r7, #12] 80127da: 2208 movs r2, #8 80127dc: 645a str r2, [r3, #68] @ 0x44 /* Process Unlocked */ __HAL_UNLOCK(huart); 80127de: 68fb ldr r3, [r7, #12] 80127e0: 2200 movs r2, #0 80127e2: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_ERROR; 80127e6: 2301 movs r3, #1 80127e8: e00f b.n 801280a while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 80127ea: 68fb ldr r3, [r7, #12] 80127ec: 681b ldr r3, [r3, #0] 80127ee: 681a ldr r2, [r3, #0] 80127f0: 68bb ldr r3, [r7, #8] 80127f2: 4013 ands r3, r2 80127f4: 68ba ldr r2, [r7, #8] 80127f6: 429a cmp r2, r3 80127f8: bf0c ite eq 80127fa: 2301 moveq r3, #1 80127fc: 2300 movne r3, #0 80127fe: b2db uxtb r3, r3 8012800: 461a mov r2, r3 8012802: 79fb ldrb r3, [r7, #7] 8012804: 429a cmp r2, r3 8012806: d0b4 beq.n 8012772 } } } } return HAL_OK; 8012808: 2300 movs r3, #0 } 801280a: 4618 mov r0, r3 801280c: 3718 adds r7, #24 801280e: 46bd mov sp, r7 8012810: bd80 pop {r7, pc} 08012812 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8012812: b480 push {r7} 8012814: b085 sub sp, #20 8012816: af00 add r7, sp, #0 8012818: 60f8 str r0, [r7, #12] 801281a: 60b9 str r1, [r7, #8] 801281c: 4613 mov r3, r2 801281e: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 8012820: 68fb ldr r3, [r7, #12] 8012822: 68ba ldr r2, [r7, #8] 8012824: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 8012826: 68fb ldr r3, [r7, #12] 8012828: 88fa ldrh r2, [r7, #6] 801282a: 859a strh r2, [r3, #44] @ 0x2c huart->RxXferCount = Size; 801282c: 68fb ldr r3, [r7, #12] 801282e: 88fa ldrh r2, [r7, #6] 8012830: 85da strh r2, [r3, #46] @ 0x2e huart->ErrorCode = HAL_UART_ERROR_NONE; 8012832: 68fb ldr r3, [r7, #12] 8012834: 2200 movs r2, #0 8012836: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 8012838: 68fb ldr r3, [r7, #12] 801283a: 2222 movs r2, #34 @ 0x22 801283c: f883 2042 strb.w r2, [r3, #66] @ 0x42 if (huart->Init.Parity != UART_PARITY_NONE) 8012840: 68fb ldr r3, [r7, #12] 8012842: 691b ldr r3, [r3, #16] 8012844: 2b00 cmp r3, #0 8012846: d007 beq.n 8012858 { /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); 8012848: 68fb ldr r3, [r7, #12] 801284a: 681b ldr r3, [r3, #0] 801284c: 68da ldr r2, [r3, #12] 801284e: 68fb ldr r3, [r7, #12] 8012850: 681b ldr r3, [r3, #0] 8012852: f442 7280 orr.w r2, r2, #256 @ 0x100 8012856: 60da str r2, [r3, #12] } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); 8012858: 68fb ldr r3, [r7, #12] 801285a: 681b ldr r3, [r3, #0] 801285c: 695a ldr r2, [r3, #20] 801285e: 68fb ldr r3, [r7, #12] 8012860: 681b ldr r3, [r3, #0] 8012862: f042 0201 orr.w r2, r2, #1 8012866: 615a str r2, [r3, #20] /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); 8012868: 68fb ldr r3, [r7, #12] 801286a: 681b ldr r3, [r3, #0] 801286c: 68da ldr r2, [r3, #12] 801286e: 68fb ldr r3, [r7, #12] 8012870: 681b ldr r3, [r3, #0] 8012872: f042 0220 orr.w r2, r2, #32 8012876: 60da str r2, [r3, #12] return HAL_OK; 8012878: 2300 movs r3, #0 } 801287a: 4618 mov r0, r3 801287c: 3714 adds r7, #20 801287e: 46bd mov sp, r7 8012880: bc80 pop {r7} 8012882: 4770 bx lr 08012884 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8012884: b480 push {r7} 8012886: b095 sub sp, #84 @ 0x54 8012888: af00 add r7, sp, #0 801288a: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 801288c: 687b ldr r3, [r7, #4] 801288e: 681b ldr r3, [r3, #0] 8012890: 330c adds r3, #12 8012892: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012894: 6b7b ldr r3, [r7, #52] @ 0x34 8012896: e853 3f00 ldrex r3, [r3] 801289a: 633b str r3, [r7, #48] @ 0x30 return(result); 801289c: 6b3b ldr r3, [r7, #48] @ 0x30 801289e: f423 7390 bic.w r3, r3, #288 @ 0x120 80128a2: 64fb str r3, [r7, #76] @ 0x4c 80128a4: 687b ldr r3, [r7, #4] 80128a6: 681b ldr r3, [r3, #0] 80128a8: 330c adds r3, #12 80128aa: 6cfa ldr r2, [r7, #76] @ 0x4c 80128ac: 643a str r2, [r7, #64] @ 0x40 80128ae: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80128b0: 6bf9 ldr r1, [r7, #60] @ 0x3c 80128b2: 6c3a ldr r2, [r7, #64] @ 0x40 80128b4: e841 2300 strex r3, r2, [r1] 80128b8: 63bb str r3, [r7, #56] @ 0x38 return(result); 80128ba: 6bbb ldr r3, [r7, #56] @ 0x38 80128bc: 2b00 cmp r3, #0 80128be: d1e5 bne.n 801288c ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80128c0: 687b ldr r3, [r7, #4] 80128c2: 681b ldr r3, [r3, #0] 80128c4: 3314 adds r3, #20 80128c6: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80128c8: 6a3b ldr r3, [r7, #32] 80128ca: e853 3f00 ldrex r3, [r3] 80128ce: 61fb str r3, [r7, #28] return(result); 80128d0: 69fb ldr r3, [r7, #28] 80128d2: f023 0301 bic.w r3, r3, #1 80128d6: 64bb str r3, [r7, #72] @ 0x48 80128d8: 687b ldr r3, [r7, #4] 80128da: 681b ldr r3, [r3, #0] 80128dc: 3314 adds r3, #20 80128de: 6cba ldr r2, [r7, #72] @ 0x48 80128e0: 62fa str r2, [r7, #44] @ 0x2c 80128e2: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80128e4: 6ab9 ldr r1, [r7, #40] @ 0x28 80128e6: 6afa ldr r2, [r7, #44] @ 0x2c 80128e8: e841 2300 strex r3, r2, [r1] 80128ec: 627b str r3, [r7, #36] @ 0x24 return(result); 80128ee: 6a7b ldr r3, [r7, #36] @ 0x24 80128f0: 2b00 cmp r3, #0 80128f2: d1e5 bne.n 80128c0 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80128f4: 687b ldr r3, [r7, #4] 80128f6: 6b1b ldr r3, [r3, #48] @ 0x30 80128f8: 2b01 cmp r3, #1 80128fa: d119 bne.n 8012930 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80128fc: 687b ldr r3, [r7, #4] 80128fe: 681b ldr r3, [r3, #0] 8012900: 330c adds r3, #12 8012902: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012904: 68fb ldr r3, [r7, #12] 8012906: e853 3f00 ldrex r3, [r3] 801290a: 60bb str r3, [r7, #8] return(result); 801290c: 68bb ldr r3, [r7, #8] 801290e: f023 0310 bic.w r3, r3, #16 8012912: 647b str r3, [r7, #68] @ 0x44 8012914: 687b ldr r3, [r7, #4] 8012916: 681b ldr r3, [r3, #0] 8012918: 330c adds r3, #12 801291a: 6c7a ldr r2, [r7, #68] @ 0x44 801291c: 61ba str r2, [r7, #24] 801291e: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012920: 6979 ldr r1, [r7, #20] 8012922: 69ba ldr r2, [r7, #24] 8012924: e841 2300 strex r3, r2, [r1] 8012928: 613b str r3, [r7, #16] return(result); 801292a: 693b ldr r3, [r7, #16] 801292c: 2b00 cmp r3, #0 801292e: d1e5 bne.n 80128fc } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012930: 687b ldr r3, [r7, #4] 8012932: 2220 movs r2, #32 8012934: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012938: 687b ldr r3, [r7, #4] 801293a: 2200 movs r2, #0 801293c: 631a str r2, [r3, #48] @ 0x30 } 801293e: bf00 nop 8012940: 3754 adds r7, #84 @ 0x54 8012942: 46bd mov sp, r7 8012944: bc80 pop {r7} 8012946: 4770 bx lr 08012948 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8012948: b580 push {r7, lr} 801294a: b084 sub sp, #16 801294c: af00 add r7, sp, #0 801294e: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8012950: 687b ldr r3, [r7, #4] 8012952: 6a5b ldr r3, [r3, #36] @ 0x24 8012954: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8012956: 68fb ldr r3, [r7, #12] 8012958: 2200 movs r2, #0 801295a: 85da strh r2, [r3, #46] @ 0x2e huart->TxXferCount = 0x00U; 801295c: 68fb ldr r3, [r7, #12] 801295e: 2200 movs r2, #0 8012960: 84da strh r2, [r3, #38] @ 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8012962: 68f8 ldr r0, [r7, #12] 8012964: f7ff fecd bl 8012702 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8012968: bf00 nop 801296a: 3710 adds r7, #16 801296c: 46bd mov sp, r7 801296e: bd80 pop {r7, pc} 08012970 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { 8012970: b580 push {r7, lr} 8012972: b084 sub sp, #16 8012974: af00 add r7, sp, #0 8012976: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8012978: 687b ldr r3, [r7, #4] 801297a: 6a5b ldr r3, [r3, #36] @ 0x24 801297c: 60fb str r3, [r7, #12] huart->hdmatx->XferAbortCallback = NULL; 801297e: 68fb ldr r3, [r7, #12] 8012980: 6b9b ldr r3, [r3, #56] @ 0x38 8012982: 2200 movs r2, #0 8012984: 635a str r2, [r3, #52] @ 0x34 /* Check if an Abort process is still ongoing */ if (huart->hdmarx != NULL) 8012986: 68fb ldr r3, [r7, #12] 8012988: 6bdb ldr r3, [r3, #60] @ 0x3c 801298a: 2b00 cmp r3, #0 801298c: d004 beq.n 8012998 { if (huart->hdmarx->XferAbortCallback != NULL) 801298e: 68fb ldr r3, [r7, #12] 8012990: 6bdb ldr r3, [r3, #60] @ 0x3c 8012992: 6b5b ldr r3, [r3, #52] @ 0x34 8012994: 2b00 cmp r3, #0 8012996: d117 bne.n 80129c8 return; } } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ huart->TxXferCount = 0x00U; 8012998: 68fb ldr r3, [r7, #12] 801299a: 2200 movs r2, #0 801299c: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 801299e: 68fb ldr r3, [r7, #12] 80129a0: 2200 movs r2, #0 80129a2: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80129a4: 68fb ldr r3, [r7, #12] 80129a6: 2200 movs r2, #0 80129a8: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 80129aa: 68fb ldr r3, [r7, #12] 80129ac: 2220 movs r2, #32 80129ae: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 80129b2: 68fb ldr r3, [r7, #12] 80129b4: 2220 movs r2, #32 80129b6: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80129ba: 68fb ldr r3, [r7, #12] 80129bc: 2200 movs r2, #0 80129be: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 80129c0: 68f8 ldr r0, [r7, #12] 80129c2: f7ff fea7 bl 8012714 80129c6: e000 b.n 80129ca return; 80129c8: bf00 nop #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80129ca: 3710 adds r7, #16 80129cc: 46bd mov sp, r7 80129ce: bd80 pop {r7, pc} 080129d0 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { 80129d0: b580 push {r7, lr} 80129d2: b084 sub sp, #16 80129d4: af00 add r7, sp, #0 80129d6: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80129d8: 687b ldr r3, [r7, #4] 80129da: 6a5b ldr r3, [r3, #36] @ 0x24 80129dc: 60fb str r3, [r7, #12] huart->hdmarx->XferAbortCallback = NULL; 80129de: 68fb ldr r3, [r7, #12] 80129e0: 6bdb ldr r3, [r3, #60] @ 0x3c 80129e2: 2200 movs r2, #0 80129e4: 635a str r2, [r3, #52] @ 0x34 /* Check if an Abort process is still ongoing */ if (huart->hdmatx != NULL) 80129e6: 68fb ldr r3, [r7, #12] 80129e8: 6b9b ldr r3, [r3, #56] @ 0x38 80129ea: 2b00 cmp r3, #0 80129ec: d004 beq.n 80129f8 { if (huart->hdmatx->XferAbortCallback != NULL) 80129ee: 68fb ldr r3, [r7, #12] 80129f0: 6b9b ldr r3, [r3, #56] @ 0x38 80129f2: 6b5b ldr r3, [r3, #52] @ 0x34 80129f4: 2b00 cmp r3, #0 80129f6: d117 bne.n 8012a28 return; } } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ huart->TxXferCount = 0x00U; 80129f8: 68fb ldr r3, [r7, #12] 80129fa: 2200 movs r2, #0 80129fc: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 80129fe: 68fb ldr r3, [r7, #12] 8012a00: 2200 movs r2, #0 8012a02: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012a04: 68fb ldr r3, [r7, #12] 8012a06: 2200 movs r2, #0 8012a08: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 8012a0a: 68fb ldr r3, [r7, #12] 8012a0c: 2220 movs r2, #32 8012a0e: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8012a12: 68fb ldr r3, [r7, #12] 8012a14: 2220 movs r2, #32 8012a16: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012a1a: 68fb ldr r3, [r7, #12] 8012a1c: 2200 movs r2, #0 8012a1e: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 8012a20: 68f8 ldr r0, [r7, #12] 8012a22: f7ff fe77 bl 8012714 8012a26: e000 b.n 8012a2a return; 8012a28: bf00 nop #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8012a2a: 3710 adds r7, #16 8012a2c: 46bd mov sp, r7 8012a2e: bd80 pop {r7, pc} 08012a30 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 8012a30: b480 push {r7} 8012a32: b085 sub sp, #20 8012a34: af00 add r7, sp, #0 8012a36: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8012a38: 687b ldr r3, [r7, #4] 8012a3a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8012a3e: b2db uxtb r3, r3 8012a40: 2b21 cmp r3, #33 @ 0x21 8012a42: d13e bne.n 8012ac2 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012a44: 687b ldr r3, [r7, #4] 8012a46: 689b ldr r3, [r3, #8] 8012a48: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012a4c: d114 bne.n 8012a78 8012a4e: 687b ldr r3, [r7, #4] 8012a50: 691b ldr r3, [r3, #16] 8012a52: 2b00 cmp r3, #0 8012a54: d110 bne.n 8012a78 { tmp = (const uint16_t *) huart->pTxBuffPtr; 8012a56: 687b ldr r3, [r7, #4] 8012a58: 6a1b ldr r3, [r3, #32] 8012a5a: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8012a5c: 68fb ldr r3, [r7, #12] 8012a5e: 881b ldrh r3, [r3, #0] 8012a60: 461a mov r2, r3 8012a62: 687b ldr r3, [r7, #4] 8012a64: 681b ldr r3, [r3, #0] 8012a66: f3c2 0208 ubfx r2, r2, #0, #9 8012a6a: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 8012a6c: 687b ldr r3, [r7, #4] 8012a6e: 6a1b ldr r3, [r3, #32] 8012a70: 1c9a adds r2, r3, #2 8012a72: 687b ldr r3, [r7, #4] 8012a74: 621a str r2, [r3, #32] 8012a76: e008 b.n 8012a8a } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 8012a78: 687b ldr r3, [r7, #4] 8012a7a: 6a1b ldr r3, [r3, #32] 8012a7c: 1c59 adds r1, r3, #1 8012a7e: 687a ldr r2, [r7, #4] 8012a80: 6211 str r1, [r2, #32] 8012a82: 781a ldrb r2, [r3, #0] 8012a84: 687b ldr r3, [r7, #4] 8012a86: 681b ldr r3, [r3, #0] 8012a88: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 8012a8a: 687b ldr r3, [r7, #4] 8012a8c: 8cdb ldrh r3, [r3, #38] @ 0x26 8012a8e: b29b uxth r3, r3 8012a90: 3b01 subs r3, #1 8012a92: b29b uxth r3, r3 8012a94: 687a ldr r2, [r7, #4] 8012a96: 4619 mov r1, r3 8012a98: 84d1 strh r1, [r2, #38] @ 0x26 8012a9a: 2b00 cmp r3, #0 8012a9c: d10f bne.n 8012abe { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8012a9e: 687b ldr r3, [r7, #4] 8012aa0: 681b ldr r3, [r3, #0] 8012aa2: 68da ldr r2, [r3, #12] 8012aa4: 687b ldr r3, [r7, #4] 8012aa6: 681b ldr r3, [r3, #0] 8012aa8: f022 0280 bic.w r2, r2, #128 @ 0x80 8012aac: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8012aae: 687b ldr r3, [r7, #4] 8012ab0: 681b ldr r3, [r3, #0] 8012ab2: 68da ldr r2, [r3, #12] 8012ab4: 687b ldr r3, [r7, #4] 8012ab6: 681b ldr r3, [r3, #0] 8012ab8: f042 0240 orr.w r2, r2, #64 @ 0x40 8012abc: 60da str r2, [r3, #12] } return HAL_OK; 8012abe: 2300 movs r3, #0 8012ac0: e000 b.n 8012ac4 } else { return HAL_BUSY; 8012ac2: 2302 movs r3, #2 } } 8012ac4: 4618 mov r0, r3 8012ac6: 3714 adds r7, #20 8012ac8: 46bd mov sp, r7 8012aca: bc80 pop {r7} 8012acc: 4770 bx lr 08012ace : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8012ace: b580 push {r7, lr} 8012ad0: b082 sub sp, #8 8012ad2: af00 add r7, sp, #0 8012ad4: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 8012ad6: 687b ldr r3, [r7, #4] 8012ad8: 681b ldr r3, [r3, #0] 8012ada: 68da ldr r2, [r3, #12] 8012adc: 687b ldr r3, [r7, #4] 8012ade: 681b ldr r3, [r3, #0] 8012ae0: f022 0240 bic.w r2, r2, #64 @ 0x40 8012ae4: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8012ae6: 687b ldr r3, [r7, #4] 8012ae8: 2220 movs r2, #32 8012aea: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8012aee: 6878 ldr r0, [r7, #4] 8012af0: f7f9 fdbc bl 800c66c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8012af4: 2300 movs r3, #0 } 8012af6: 4618 mov r0, r3 8012af8: 3708 adds r7, #8 8012afa: 46bd mov sp, r7 8012afc: bd80 pop {r7, pc} 08012afe : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 8012afe: b580 push {r7, lr} 8012b00: b08c sub sp, #48 @ 0x30 8012b02: af00 add r7, sp, #0 8012b04: 6078 str r0, [r7, #4] uint8_t *pdata8bits; uint16_t *pdata16bits; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8012b06: 687b ldr r3, [r7, #4] 8012b08: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8012b0c: b2db uxtb r3, r3 8012b0e: 2b22 cmp r3, #34 @ 0x22 8012b10: f040 80ae bne.w 8012c70 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012b14: 687b ldr r3, [r7, #4] 8012b16: 689b ldr r3, [r3, #8] 8012b18: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012b1c: d117 bne.n 8012b4e 8012b1e: 687b ldr r3, [r7, #4] 8012b20: 691b ldr r3, [r3, #16] 8012b22: 2b00 cmp r3, #0 8012b24: d113 bne.n 8012b4e { pdata8bits = NULL; 8012b26: 2300 movs r3, #0 8012b28: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = (uint16_t *) huart->pRxBuffPtr; 8012b2a: 687b ldr r3, [r7, #4] 8012b2c: 6a9b ldr r3, [r3, #40] @ 0x28 8012b2e: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8012b30: 687b ldr r3, [r7, #4] 8012b32: 681b ldr r3, [r3, #0] 8012b34: 685b ldr r3, [r3, #4] 8012b36: b29b uxth r3, r3 8012b38: f3c3 0308 ubfx r3, r3, #0, #9 8012b3c: b29a uxth r2, r3 8012b3e: 6abb ldr r3, [r7, #40] @ 0x28 8012b40: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8012b42: 687b ldr r3, [r7, #4] 8012b44: 6a9b ldr r3, [r3, #40] @ 0x28 8012b46: 1c9a adds r2, r3, #2 8012b48: 687b ldr r3, [r7, #4] 8012b4a: 629a str r2, [r3, #40] @ 0x28 8012b4c: e026 b.n 8012b9c } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8012b4e: 687b ldr r3, [r7, #4] 8012b50: 6a9b ldr r3, [r3, #40] @ 0x28 8012b52: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = NULL; 8012b54: 2300 movs r3, #0 8012b56: 62bb str r3, [r7, #40] @ 0x28 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 8012b58: 687b ldr r3, [r7, #4] 8012b5a: 689b ldr r3, [r3, #8] 8012b5c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012b60: d007 beq.n 8012b72 8012b62: 687b ldr r3, [r7, #4] 8012b64: 689b ldr r3, [r3, #8] 8012b66: 2b00 cmp r3, #0 8012b68: d10a bne.n 8012b80 8012b6a: 687b ldr r3, [r7, #4] 8012b6c: 691b ldr r3, [r3, #16] 8012b6e: 2b00 cmp r3, #0 8012b70: d106 bne.n 8012b80 { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8012b72: 687b ldr r3, [r7, #4] 8012b74: 681b ldr r3, [r3, #0] 8012b76: 685b ldr r3, [r3, #4] 8012b78: b2da uxtb r2, r3 8012b7a: 6afb ldr r3, [r7, #44] @ 0x2c 8012b7c: 701a strb r2, [r3, #0] 8012b7e: e008 b.n 8012b92 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8012b80: 687b ldr r3, [r7, #4] 8012b82: 681b ldr r3, [r3, #0] 8012b84: 685b ldr r3, [r3, #4] 8012b86: b2db uxtb r3, r3 8012b88: f003 037f and.w r3, r3, #127 @ 0x7f 8012b8c: b2da uxtb r2, r3 8012b8e: 6afb ldr r3, [r7, #44] @ 0x2c 8012b90: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8012b92: 687b ldr r3, [r7, #4] 8012b94: 6a9b ldr r3, [r3, #40] @ 0x28 8012b96: 1c5a adds r2, r3, #1 8012b98: 687b ldr r3, [r7, #4] 8012b9a: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 8012b9c: 687b ldr r3, [r7, #4] 8012b9e: 8ddb ldrh r3, [r3, #46] @ 0x2e 8012ba0: b29b uxth r3, r3 8012ba2: 3b01 subs r3, #1 8012ba4: b29b uxth r3, r3 8012ba6: 687a ldr r2, [r7, #4] 8012ba8: 4619 mov r1, r3 8012baa: 85d1 strh r1, [r2, #46] @ 0x2e 8012bac: 2b00 cmp r3, #0 8012bae: d15d bne.n 8012c6c { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8012bb0: 687b ldr r3, [r7, #4] 8012bb2: 681b ldr r3, [r3, #0] 8012bb4: 68da ldr r2, [r3, #12] 8012bb6: 687b ldr r3, [r7, #4] 8012bb8: 681b ldr r3, [r3, #0] 8012bba: f022 0220 bic.w r2, r2, #32 8012bbe: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8012bc0: 687b ldr r3, [r7, #4] 8012bc2: 681b ldr r3, [r3, #0] 8012bc4: 68da ldr r2, [r3, #12] 8012bc6: 687b ldr r3, [r7, #4] 8012bc8: 681b ldr r3, [r3, #0] 8012bca: f422 7280 bic.w r2, r2, #256 @ 0x100 8012bce: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8012bd0: 687b ldr r3, [r7, #4] 8012bd2: 681b ldr r3, [r3, #0] 8012bd4: 695a ldr r2, [r3, #20] 8012bd6: 687b ldr r3, [r7, #4] 8012bd8: 681b ldr r3, [r3, #0] 8012bda: f022 0201 bic.w r2, r2, #1 8012bde: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012be0: 687b ldr r3, [r7, #4] 8012be2: 2220 movs r2, #32 8012be4: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8012be8: 687b ldr r3, [r7, #4] 8012bea: 2200 movs r2, #0 8012bec: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012bee: 687b ldr r3, [r7, #4] 8012bf0: 6b1b ldr r3, [r3, #48] @ 0x30 8012bf2: 2b01 cmp r3, #1 8012bf4: d135 bne.n 8012c62 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012bf6: 687b ldr r3, [r7, #4] 8012bf8: 2200 movs r2, #0 8012bfa: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012bfc: 687b ldr r3, [r7, #4] 8012bfe: 681b ldr r3, [r3, #0] 8012c00: 330c adds r3, #12 8012c02: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012c04: 697b ldr r3, [r7, #20] 8012c06: e853 3f00 ldrex r3, [r3] 8012c0a: 613b str r3, [r7, #16] return(result); 8012c0c: 693b ldr r3, [r7, #16] 8012c0e: f023 0310 bic.w r3, r3, #16 8012c12: 627b str r3, [r7, #36] @ 0x24 8012c14: 687b ldr r3, [r7, #4] 8012c16: 681b ldr r3, [r3, #0] 8012c18: 330c adds r3, #12 8012c1a: 6a7a ldr r2, [r7, #36] @ 0x24 8012c1c: 623a str r2, [r7, #32] 8012c1e: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012c20: 69f9 ldr r1, [r7, #28] 8012c22: 6a3a ldr r2, [r7, #32] 8012c24: e841 2300 strex r3, r2, [r1] 8012c28: 61bb str r3, [r7, #24] return(result); 8012c2a: 69bb ldr r3, [r7, #24] 8012c2c: 2b00 cmp r3, #0 8012c2e: d1e5 bne.n 8012bfc /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 8012c30: 687b ldr r3, [r7, #4] 8012c32: 681b ldr r3, [r3, #0] 8012c34: 681b ldr r3, [r3, #0] 8012c36: f003 0310 and.w r3, r3, #16 8012c3a: 2b10 cmp r3, #16 8012c3c: d10a bne.n 8012c54 { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 8012c3e: 2300 movs r3, #0 8012c40: 60fb str r3, [r7, #12] 8012c42: 687b ldr r3, [r7, #4] 8012c44: 681b ldr r3, [r3, #0] 8012c46: 681b ldr r3, [r3, #0] 8012c48: 60fb str r3, [r7, #12] 8012c4a: 687b ldr r3, [r7, #4] 8012c4c: 681b ldr r3, [r3, #0] 8012c4e: 685b ldr r3, [r3, #4] 8012c50: 60fb str r3, [r7, #12] 8012c52: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8012c54: 687b ldr r3, [r7, #4] 8012c56: 8d9b ldrh r3, [r3, #44] @ 0x2c 8012c58: 4619 mov r1, r3 8012c5a: 6878 ldr r0, [r7, #4] 8012c5c: f7f9 fca6 bl 800c5ac 8012c60: e002 b.n 8012c68 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8012c62: 6878 ldr r0, [r7, #4] 8012c64: f7ff fd44 bl 80126f0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8012c68: 2300 movs r3, #0 8012c6a: e002 b.n 8012c72 } return HAL_OK; 8012c6c: 2300 movs r3, #0 8012c6e: e000 b.n 8012c72 } else { return HAL_BUSY; 8012c70: 2302 movs r3, #2 } } 8012c72: 4618 mov r0, r3 8012c74: 3730 adds r7, #48 @ 0x30 8012c76: 46bd mov sp, r7 8012c78: bd80 pop {r7, pc} ... 08012c7c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8012c7c: b580 push {r7, lr} 8012c7e: b084 sub sp, #16 8012c80: af00 add r7, sp, #0 8012c82: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8012c84: 687b ldr r3, [r7, #4] 8012c86: 681b ldr r3, [r3, #0] 8012c88: 691b ldr r3, [r3, #16] 8012c8a: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8012c8e: 687b ldr r3, [r7, #4] 8012c90: 68da ldr r2, [r3, #12] 8012c92: 687b ldr r3, [r7, #4] 8012c94: 681b ldr r3, [r3, #0] 8012c96: 430a orrs r2, r1 8012c98: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 8012c9a: 687b ldr r3, [r7, #4] 8012c9c: 689a ldr r2, [r3, #8] 8012c9e: 687b ldr r3, [r7, #4] 8012ca0: 691b ldr r3, [r3, #16] 8012ca2: 431a orrs r2, r3 8012ca4: 687b ldr r3, [r7, #4] 8012ca6: 695b ldr r3, [r3, #20] 8012ca8: 4313 orrs r3, r2 8012caa: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 8012cac: 687b ldr r3, [r7, #4] 8012cae: 681b ldr r3, [r3, #0] 8012cb0: 68db ldr r3, [r3, #12] 8012cb2: f423 53b0 bic.w r3, r3, #5632 @ 0x1600 8012cb6: f023 030c bic.w r3, r3, #12 8012cba: 687a ldr r2, [r7, #4] 8012cbc: 6812 ldr r2, [r2, #0] 8012cbe: 68b9 ldr r1, [r7, #8] 8012cc0: 430b orrs r3, r1 8012cc2: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8012cc4: 687b ldr r3, [r7, #4] 8012cc6: 681b ldr r3, [r3, #0] 8012cc8: 695b ldr r3, [r3, #20] 8012cca: f423 7140 bic.w r1, r3, #768 @ 0x300 8012cce: 687b ldr r3, [r7, #4] 8012cd0: 699a ldr r2, [r3, #24] 8012cd2: 687b ldr r3, [r7, #4] 8012cd4: 681b ldr r3, [r3, #0] 8012cd6: 430a orrs r2, r1 8012cd8: 615a str r2, [r3, #20] if(huart->Instance == USART1) 8012cda: 687b ldr r3, [r7, #4] 8012cdc: 681b ldr r3, [r3, #0] 8012cde: 4a2c ldr r2, [pc, #176] @ (8012d90 ) 8012ce0: 4293 cmp r3, r2 8012ce2: d103 bne.n 8012cec { pclk = HAL_RCC_GetPCLK2Freq(); 8012ce4: f7fd fc1a bl 801051c 8012ce8: 60f8 str r0, [r7, #12] 8012cea: e002 b.n 8012cf2 } else { pclk = HAL_RCC_GetPCLK1Freq(); 8012cec: f7fd fc02 bl 80104f4 8012cf0: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8012cf2: 68fa ldr r2, [r7, #12] 8012cf4: 4613 mov r3, r2 8012cf6: 009b lsls r3, r3, #2 8012cf8: 4413 add r3, r2 8012cfa: 009a lsls r2, r3, #2 8012cfc: 441a add r2, r3 8012cfe: 687b ldr r3, [r7, #4] 8012d00: 685b ldr r3, [r3, #4] 8012d02: 009b lsls r3, r3, #2 8012d04: fbb2 f3f3 udiv r3, r2, r3 8012d08: 4a22 ldr r2, [pc, #136] @ (8012d94 ) 8012d0a: fba2 2303 umull r2, r3, r2, r3 8012d0e: 095b lsrs r3, r3, #5 8012d10: 0119 lsls r1, r3, #4 8012d12: 68fa ldr r2, [r7, #12] 8012d14: 4613 mov r3, r2 8012d16: 009b lsls r3, r3, #2 8012d18: 4413 add r3, r2 8012d1a: 009a lsls r2, r3, #2 8012d1c: 441a add r2, r3 8012d1e: 687b ldr r3, [r7, #4] 8012d20: 685b ldr r3, [r3, #4] 8012d22: 009b lsls r3, r3, #2 8012d24: fbb2 f2f3 udiv r2, r2, r3 8012d28: 4b1a ldr r3, [pc, #104] @ (8012d94 ) 8012d2a: fba3 0302 umull r0, r3, r3, r2 8012d2e: 095b lsrs r3, r3, #5 8012d30: 2064 movs r0, #100 @ 0x64 8012d32: fb00 f303 mul.w r3, r0, r3 8012d36: 1ad3 subs r3, r2, r3 8012d38: 011b lsls r3, r3, #4 8012d3a: 3332 adds r3, #50 @ 0x32 8012d3c: 4a15 ldr r2, [pc, #84] @ (8012d94 ) 8012d3e: fba2 2303 umull r2, r3, r2, r3 8012d42: 095b lsrs r3, r3, #5 8012d44: f003 03f0 and.w r3, r3, #240 @ 0xf0 8012d48: 4419 add r1, r3 8012d4a: 68fa ldr r2, [r7, #12] 8012d4c: 4613 mov r3, r2 8012d4e: 009b lsls r3, r3, #2 8012d50: 4413 add r3, r2 8012d52: 009a lsls r2, r3, #2 8012d54: 441a add r2, r3 8012d56: 687b ldr r3, [r7, #4] 8012d58: 685b ldr r3, [r3, #4] 8012d5a: 009b lsls r3, r3, #2 8012d5c: fbb2 f2f3 udiv r2, r2, r3 8012d60: 4b0c ldr r3, [pc, #48] @ (8012d94 ) 8012d62: fba3 0302 umull r0, r3, r3, r2 8012d66: 095b lsrs r3, r3, #5 8012d68: 2064 movs r0, #100 @ 0x64 8012d6a: fb00 f303 mul.w r3, r0, r3 8012d6e: 1ad3 subs r3, r2, r3 8012d70: 011b lsls r3, r3, #4 8012d72: 3332 adds r3, #50 @ 0x32 8012d74: 4a07 ldr r2, [pc, #28] @ (8012d94 ) 8012d76: fba2 2303 umull r2, r3, r2, r3 8012d7a: 095b lsrs r3, r3, #5 8012d7c: f003 020f and.w r2, r3, #15 8012d80: 687b ldr r3, [r7, #4] 8012d82: 681b ldr r3, [r3, #0] 8012d84: 440a add r2, r1 8012d86: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 8012d88: bf00 nop 8012d8a: 3710 adds r7, #16 8012d8c: 46bd mov sp, r7 8012d8e: bd80 pop {r7, pc} 8012d90: 40013800 .word 0x40013800 8012d94: 51eb851f .word 0x51eb851f 08012d98 : 8012d98: 2300 movs r3, #0 8012d9a: b510 push {r4, lr} 8012d9c: 4604 mov r4, r0 8012d9e: e9c0 3300 strd r3, r3, [r0] 8012da2: e9c0 3304 strd r3, r3, [r0, #16] 8012da6: 6083 str r3, [r0, #8] 8012da8: 8181 strh r1, [r0, #12] 8012daa: 6643 str r3, [r0, #100] @ 0x64 8012dac: 81c2 strh r2, [r0, #14] 8012dae: 6183 str r3, [r0, #24] 8012db0: 4619 mov r1, r3 8012db2: 2208 movs r2, #8 8012db4: 305c adds r0, #92 @ 0x5c 8012db6: f000 f943 bl 8013040 8012dba: 4b0d ldr r3, [pc, #52] @ (8012df0 ) 8012dbc: 6224 str r4, [r4, #32] 8012dbe: 6263 str r3, [r4, #36] @ 0x24 8012dc0: 4b0c ldr r3, [pc, #48] @ (8012df4 ) 8012dc2: 62a3 str r3, [r4, #40] @ 0x28 8012dc4: 4b0c ldr r3, [pc, #48] @ (8012df8 ) 8012dc6: 62e3 str r3, [r4, #44] @ 0x2c 8012dc8: 4b0c ldr r3, [pc, #48] @ (8012dfc ) 8012dca: 6323 str r3, [r4, #48] @ 0x30 8012dcc: 4b0c ldr r3, [pc, #48] @ (8012e00 ) 8012dce: 429c cmp r4, r3 8012dd0: d006 beq.n 8012de0 8012dd2: f103 0268 add.w r2, r3, #104 @ 0x68 8012dd6: 4294 cmp r4, r2 8012dd8: d002 beq.n 8012de0 8012dda: 33d0 adds r3, #208 @ 0xd0 8012ddc: 429c cmp r4, r3 8012dde: d105 bne.n 8012dec 8012de0: f104 0058 add.w r0, r4, #88 @ 0x58 8012de4: e8bd 4010 ldmia.w sp!, {r4, lr} 8012de8: f000 b9a2 b.w 8013130 <__retarget_lock_init_recursive> 8012dec: bd10 pop {r4, pc} 8012dee: bf00 nop 8012df0: 08012f41 .word 0x08012f41 8012df4: 08012f63 .word 0x08012f63 8012df8: 08012f9b .word 0x08012f9b 8012dfc: 08012fbf .word 0x08012fbf 8012e00: 2000107c .word 0x2000107c 08012e04 : 8012e04: 4a02 ldr r2, [pc, #8] @ (8012e10 ) 8012e06: 4903 ldr r1, [pc, #12] @ (8012e14 ) 8012e08: 4803 ldr r0, [pc, #12] @ (8012e18 ) 8012e0a: f000 b869 b.w 8012ee0 <_fwalk_sglue> 8012e0e: bf00 nop 8012e10: 20000078 .word 0x20000078 8012e14: 08013c91 .word 0x08013c91 8012e18: 20000088 .word 0x20000088 08012e1c : 8012e1c: 6841 ldr r1, [r0, #4] 8012e1e: 4b0c ldr r3, [pc, #48] @ (8012e50 ) 8012e20: b510 push {r4, lr} 8012e22: 4299 cmp r1, r3 8012e24: 4604 mov r4, r0 8012e26: d001 beq.n 8012e2c 8012e28: f000 ff32 bl 8013c90 <_fflush_r> 8012e2c: 68a1 ldr r1, [r4, #8] 8012e2e: 4b09 ldr r3, [pc, #36] @ (8012e54 ) 8012e30: 4299 cmp r1, r3 8012e32: d002 beq.n 8012e3a 8012e34: 4620 mov r0, r4 8012e36: f000 ff2b bl 8013c90 <_fflush_r> 8012e3a: 68e1 ldr r1, [r4, #12] 8012e3c: 4b06 ldr r3, [pc, #24] @ (8012e58 ) 8012e3e: 4299 cmp r1, r3 8012e40: d004 beq.n 8012e4c 8012e42: 4620 mov r0, r4 8012e44: e8bd 4010 ldmia.w sp!, {r4, lr} 8012e48: f000 bf22 b.w 8013c90 <_fflush_r> 8012e4c: bd10 pop {r4, pc} 8012e4e: bf00 nop 8012e50: 2000107c .word 0x2000107c 8012e54: 200010e4 .word 0x200010e4 8012e58: 2000114c .word 0x2000114c 08012e5c : 8012e5c: b510 push {r4, lr} 8012e5e: 4b0b ldr r3, [pc, #44] @ (8012e8c ) 8012e60: 4c0b ldr r4, [pc, #44] @ (8012e90 ) 8012e62: 4a0c ldr r2, [pc, #48] @ (8012e94 ) 8012e64: 4620 mov r0, r4 8012e66: 601a str r2, [r3, #0] 8012e68: 2104 movs r1, #4 8012e6a: 2200 movs r2, #0 8012e6c: f7ff ff94 bl 8012d98 8012e70: f104 0068 add.w r0, r4, #104 @ 0x68 8012e74: 2201 movs r2, #1 8012e76: 2109 movs r1, #9 8012e78: f7ff ff8e bl 8012d98 8012e7c: f104 00d0 add.w r0, r4, #208 @ 0xd0 8012e80: 2202 movs r2, #2 8012e82: e8bd 4010 ldmia.w sp!, {r4, lr} 8012e86: 2112 movs r1, #18 8012e88: f7ff bf86 b.w 8012d98 8012e8c: 200011b4 .word 0x200011b4 8012e90: 2000107c .word 0x2000107c 8012e94: 08012e05 .word 0x08012e05 08012e98 <__sfp_lock_acquire>: 8012e98: 4801 ldr r0, [pc, #4] @ (8012ea0 <__sfp_lock_acquire+0x8>) 8012e9a: f000 b94a b.w 8013132 <__retarget_lock_acquire_recursive> 8012e9e: bf00 nop 8012ea0: 200011bd .word 0x200011bd 08012ea4 <__sfp_lock_release>: 8012ea4: 4801 ldr r0, [pc, #4] @ (8012eac <__sfp_lock_release+0x8>) 8012ea6: f000 b945 b.w 8013134 <__retarget_lock_release_recursive> 8012eaa: bf00 nop 8012eac: 200011bd .word 0x200011bd 08012eb0 <__sinit>: 8012eb0: b510 push {r4, lr} 8012eb2: 4604 mov r4, r0 8012eb4: f7ff fff0 bl 8012e98 <__sfp_lock_acquire> 8012eb8: 6a23 ldr r3, [r4, #32] 8012eba: b11b cbz r3, 8012ec4 <__sinit+0x14> 8012ebc: e8bd 4010 ldmia.w sp!, {r4, lr} 8012ec0: f7ff bff0 b.w 8012ea4 <__sfp_lock_release> 8012ec4: 4b04 ldr r3, [pc, #16] @ (8012ed8 <__sinit+0x28>) 8012ec6: 6223 str r3, [r4, #32] 8012ec8: 4b04 ldr r3, [pc, #16] @ (8012edc <__sinit+0x2c>) 8012eca: 681b ldr r3, [r3, #0] 8012ecc: 2b00 cmp r3, #0 8012ece: d1f5 bne.n 8012ebc <__sinit+0xc> 8012ed0: f7ff ffc4 bl 8012e5c 8012ed4: e7f2 b.n 8012ebc <__sinit+0xc> 8012ed6: bf00 nop 8012ed8: 08012e1d .word 0x08012e1d 8012edc: 200011b4 .word 0x200011b4 08012ee0 <_fwalk_sglue>: 8012ee0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8012ee4: 4607 mov r7, r0 8012ee6: 4688 mov r8, r1 8012ee8: 4614 mov r4, r2 8012eea: 2600 movs r6, #0 8012eec: e9d4 9501 ldrd r9, r5, [r4, #4] 8012ef0: f1b9 0901 subs.w r9, r9, #1 8012ef4: d505 bpl.n 8012f02 <_fwalk_sglue+0x22> 8012ef6: 6824 ldr r4, [r4, #0] 8012ef8: 2c00 cmp r4, #0 8012efa: d1f7 bne.n 8012eec <_fwalk_sglue+0xc> 8012efc: 4630 mov r0, r6 8012efe: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8012f02: 89ab ldrh r3, [r5, #12] 8012f04: 2b01 cmp r3, #1 8012f06: d907 bls.n 8012f18 <_fwalk_sglue+0x38> 8012f08: f9b5 300e ldrsh.w r3, [r5, #14] 8012f0c: 3301 adds r3, #1 8012f0e: d003 beq.n 8012f18 <_fwalk_sglue+0x38> 8012f10: 4629 mov r1, r5 8012f12: 4638 mov r0, r7 8012f14: 47c0 blx r8 8012f16: 4306 orrs r6, r0 8012f18: 3568 adds r5, #104 @ 0x68 8012f1a: e7e9 b.n 8012ef0 <_fwalk_sglue+0x10> 08012f1c : 8012f1c: b40f push {r0, r1, r2, r3} 8012f1e: b507 push {r0, r1, r2, lr} 8012f20: 4906 ldr r1, [pc, #24] @ (8012f3c ) 8012f22: ab04 add r3, sp, #16 8012f24: 6808 ldr r0, [r1, #0] 8012f26: f853 2b04 ldr.w r2, [r3], #4 8012f2a: 6881 ldr r1, [r0, #8] 8012f2c: 9301 str r3, [sp, #4] 8012f2e: f000 fb87 bl 8013640 <_vfiprintf_r> 8012f32: b003 add sp, #12 8012f34: f85d eb04 ldr.w lr, [sp], #4 8012f38: b004 add sp, #16 8012f3a: 4770 bx lr 8012f3c: 20000084 .word 0x20000084 08012f40 <__sread>: 8012f40: b510 push {r4, lr} 8012f42: 460c mov r4, r1 8012f44: f9b1 100e ldrsh.w r1, [r1, #14] 8012f48: f000 f8a4 bl 8013094 <_read_r> 8012f4c: 2800 cmp r0, #0 8012f4e: bfab itete ge 8012f50: 6d63 ldrge r3, [r4, #84] @ 0x54 8012f52: 89a3 ldrhlt r3, [r4, #12] 8012f54: 181b addge r3, r3, r0 8012f56: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 8012f5a: bfac ite ge 8012f5c: 6563 strge r3, [r4, #84] @ 0x54 8012f5e: 81a3 strhlt r3, [r4, #12] 8012f60: bd10 pop {r4, pc} 08012f62 <__swrite>: 8012f62: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8012f66: 461f mov r7, r3 8012f68: 898b ldrh r3, [r1, #12] 8012f6a: 4605 mov r5, r0 8012f6c: 05db lsls r3, r3, #23 8012f6e: 460c mov r4, r1 8012f70: 4616 mov r6, r2 8012f72: d505 bpl.n 8012f80 <__swrite+0x1e> 8012f74: 2302 movs r3, #2 8012f76: 2200 movs r2, #0 8012f78: f9b1 100e ldrsh.w r1, [r1, #14] 8012f7c: f000 f878 bl 8013070 <_lseek_r> 8012f80: 89a3 ldrh r3, [r4, #12] 8012f82: 4632 mov r2, r6 8012f84: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8012f88: 81a3 strh r3, [r4, #12] 8012f8a: 4628 mov r0, r5 8012f8c: 463b mov r3, r7 8012f8e: f9b4 100e ldrsh.w r1, [r4, #14] 8012f92: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8012f96: f000 b88f b.w 80130b8 <_write_r> 08012f9a <__sseek>: 8012f9a: b510 push {r4, lr} 8012f9c: 460c mov r4, r1 8012f9e: f9b1 100e ldrsh.w r1, [r1, #14] 8012fa2: f000 f865 bl 8013070 <_lseek_r> 8012fa6: 1c43 adds r3, r0, #1 8012fa8: 89a3 ldrh r3, [r4, #12] 8012faa: bf15 itete ne 8012fac: 6560 strne r0, [r4, #84] @ 0x54 8012fae: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 8012fb2: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 8012fb6: 81a3 strheq r3, [r4, #12] 8012fb8: bf18 it ne 8012fba: 81a3 strhne r3, [r4, #12] 8012fbc: bd10 pop {r4, pc} 08012fbe <__sclose>: 8012fbe: f9b1 100e ldrsh.w r1, [r1, #14] 8012fc2: f000 b845 b.w 8013050 <_close_r> 08012fc6 <_vsniprintf_r>: 8012fc6: b530 push {r4, r5, lr} 8012fc8: 4614 mov r4, r2 8012fca: 2c00 cmp r4, #0 8012fcc: 4605 mov r5, r0 8012fce: 461a mov r2, r3 8012fd0: b09b sub sp, #108 @ 0x6c 8012fd2: da05 bge.n 8012fe0 <_vsniprintf_r+0x1a> 8012fd4: 238b movs r3, #139 @ 0x8b 8012fd6: 6003 str r3, [r0, #0] 8012fd8: f04f 30ff mov.w r0, #4294967295 8012fdc: b01b add sp, #108 @ 0x6c 8012fde: bd30 pop {r4, r5, pc} 8012fe0: f44f 7302 mov.w r3, #520 @ 0x208 8012fe4: f8ad 300c strh.w r3, [sp, #12] 8012fe8: f04f 0300 mov.w r3, #0 8012fec: 9319 str r3, [sp, #100] @ 0x64 8012fee: bf0c ite eq 8012ff0: 4623 moveq r3, r4 8012ff2: f104 33ff addne.w r3, r4, #4294967295 8012ff6: 9302 str r3, [sp, #8] 8012ff8: 9305 str r3, [sp, #20] 8012ffa: f64f 73ff movw r3, #65535 @ 0xffff 8012ffe: 9100 str r1, [sp, #0] 8013000: 9104 str r1, [sp, #16] 8013002: f8ad 300e strh.w r3, [sp, #14] 8013006: 4669 mov r1, sp 8013008: 9b1e ldr r3, [sp, #120] @ 0x78 801300a: f000 f9f5 bl 80133f8 <_svfiprintf_r> 801300e: 1c43 adds r3, r0, #1 8013010: bfbc itt lt 8013012: 238b movlt r3, #139 @ 0x8b 8013014: 602b strlt r3, [r5, #0] 8013016: 2c00 cmp r4, #0 8013018: d0e0 beq.n 8012fdc <_vsniprintf_r+0x16> 801301a: 2200 movs r2, #0 801301c: 9b00 ldr r3, [sp, #0] 801301e: 701a strb r2, [r3, #0] 8013020: e7dc b.n 8012fdc <_vsniprintf_r+0x16> ... 08013024 : 8013024: b507 push {r0, r1, r2, lr} 8013026: 9300 str r3, [sp, #0] 8013028: 4613 mov r3, r2 801302a: 460a mov r2, r1 801302c: 4601 mov r1, r0 801302e: 4803 ldr r0, [pc, #12] @ (801303c ) 8013030: 6800 ldr r0, [r0, #0] 8013032: f7ff ffc8 bl 8012fc6 <_vsniprintf_r> 8013036: b003 add sp, #12 8013038: f85d fb04 ldr.w pc, [sp], #4 801303c: 20000084 .word 0x20000084 08013040 : 8013040: 4603 mov r3, r0 8013042: 4402 add r2, r0 8013044: 4293 cmp r3, r2 8013046: d100 bne.n 801304a 8013048: 4770 bx lr 801304a: f803 1b01 strb.w r1, [r3], #1 801304e: e7f9 b.n 8013044 08013050 <_close_r>: 8013050: b538 push {r3, r4, r5, lr} 8013052: 2300 movs r3, #0 8013054: 4d05 ldr r5, [pc, #20] @ (801306c <_close_r+0x1c>) 8013056: 4604 mov r4, r0 8013058: 4608 mov r0, r1 801305a: 602b str r3, [r5, #0] 801305c: f7f9 ffff bl 800d05e <_close> 8013060: 1c43 adds r3, r0, #1 8013062: d102 bne.n 801306a <_close_r+0x1a> 8013064: 682b ldr r3, [r5, #0] 8013066: b103 cbz r3, 801306a <_close_r+0x1a> 8013068: 6023 str r3, [r4, #0] 801306a: bd38 pop {r3, r4, r5, pc} 801306c: 200011b8 .word 0x200011b8 08013070 <_lseek_r>: 8013070: b538 push {r3, r4, r5, lr} 8013072: 4604 mov r4, r0 8013074: 4608 mov r0, r1 8013076: 4611 mov r1, r2 8013078: 2200 movs r2, #0 801307a: 4d05 ldr r5, [pc, #20] @ (8013090 <_lseek_r+0x20>) 801307c: 602a str r2, [r5, #0] 801307e: 461a mov r2, r3 8013080: f7fa f811 bl 800d0a6 <_lseek> 8013084: 1c43 adds r3, r0, #1 8013086: d102 bne.n 801308e <_lseek_r+0x1e> 8013088: 682b ldr r3, [r5, #0] 801308a: b103 cbz r3, 801308e <_lseek_r+0x1e> 801308c: 6023 str r3, [r4, #0] 801308e: bd38 pop {r3, r4, r5, pc} 8013090: 200011b8 .word 0x200011b8 08013094 <_read_r>: 8013094: b538 push {r3, r4, r5, lr} 8013096: 4604 mov r4, r0 8013098: 4608 mov r0, r1 801309a: 4611 mov r1, r2 801309c: 2200 movs r2, #0 801309e: 4d05 ldr r5, [pc, #20] @ (80130b4 <_read_r+0x20>) 80130a0: 602a str r2, [r5, #0] 80130a2: 461a mov r2, r3 80130a4: f7f9 ffbe bl 800d024 <_read> 80130a8: 1c43 adds r3, r0, #1 80130aa: d102 bne.n 80130b2 <_read_r+0x1e> 80130ac: 682b ldr r3, [r5, #0] 80130ae: b103 cbz r3, 80130b2 <_read_r+0x1e> 80130b0: 6023 str r3, [r4, #0] 80130b2: bd38 pop {r3, r4, r5, pc} 80130b4: 200011b8 .word 0x200011b8 080130b8 <_write_r>: 80130b8: b538 push {r3, r4, r5, lr} 80130ba: 4604 mov r4, r0 80130bc: 4608 mov r0, r1 80130be: 4611 mov r1, r2 80130c0: 2200 movs r2, #0 80130c2: 4d05 ldr r5, [pc, #20] @ (80130d8 <_write_r+0x20>) 80130c4: 602a str r2, [r5, #0] 80130c6: 461a mov r2, r3 80130c8: f7f7 f8f2 bl 800a2b0 <_write> 80130cc: 1c43 adds r3, r0, #1 80130ce: d102 bne.n 80130d6 <_write_r+0x1e> 80130d0: 682b ldr r3, [r5, #0] 80130d2: b103 cbz r3, 80130d6 <_write_r+0x1e> 80130d4: 6023 str r3, [r4, #0] 80130d6: bd38 pop {r3, r4, r5, pc} 80130d8: 200011b8 .word 0x200011b8 080130dc <__errno>: 80130dc: 4b01 ldr r3, [pc, #4] @ (80130e4 <__errno+0x8>) 80130de: 6818 ldr r0, [r3, #0] 80130e0: 4770 bx lr 80130e2: bf00 nop 80130e4: 20000084 .word 0x20000084 080130e8 <__libc_init_array>: 80130e8: b570 push {r4, r5, r6, lr} 80130ea: 2600 movs r6, #0 80130ec: 4d0c ldr r5, [pc, #48] @ (8013120 <__libc_init_array+0x38>) 80130ee: 4c0d ldr r4, [pc, #52] @ (8013124 <__libc_init_array+0x3c>) 80130f0: 1b64 subs r4, r4, r5 80130f2: 10a4 asrs r4, r4, #2 80130f4: 42a6 cmp r6, r4 80130f6: d109 bne.n 801310c <__libc_init_array+0x24> 80130f8: f000 ff78 bl 8013fec <_init> 80130fc: 2600 movs r6, #0 80130fe: 4d0a ldr r5, [pc, #40] @ (8013128 <__libc_init_array+0x40>) 8013100: 4c0a ldr r4, [pc, #40] @ (801312c <__libc_init_array+0x44>) 8013102: 1b64 subs r4, r4, r5 8013104: 10a4 asrs r4, r4, #2 8013106: 42a6 cmp r6, r4 8013108: d105 bne.n 8013116 <__libc_init_array+0x2e> 801310a: bd70 pop {r4, r5, r6, pc} 801310c: f855 3b04 ldr.w r3, [r5], #4 8013110: 4798 blx r3 8013112: 3601 adds r6, #1 8013114: e7ee b.n 80130f4 <__libc_init_array+0xc> 8013116: f855 3b04 ldr.w r3, [r5], #4 801311a: 4798 blx r3 801311c: 3601 adds r6, #1 801311e: e7f2 b.n 8013106 <__libc_init_array+0x1e> 8013120: 080144b8 .word 0x080144b8 8013124: 080144b8 .word 0x080144b8 8013128: 080144b8 .word 0x080144b8 801312c: 080144bc .word 0x080144bc 08013130 <__retarget_lock_init_recursive>: 8013130: 4770 bx lr 08013132 <__retarget_lock_acquire_recursive>: 8013132: 4770 bx lr 08013134 <__retarget_lock_release_recursive>: 8013134: 4770 bx lr 08013136 : 8013136: 440a add r2, r1 8013138: 4291 cmp r1, r2 801313a: f100 33ff add.w r3, r0, #4294967295 801313e: d100 bne.n 8013142 8013140: 4770 bx lr 8013142: b510 push {r4, lr} 8013144: f811 4b01 ldrb.w r4, [r1], #1 8013148: 4291 cmp r1, r2 801314a: f803 4f01 strb.w r4, [r3, #1]! 801314e: d1f9 bne.n 8013144 8013150: bd10 pop {r4, pc} ... 08013154 <_free_r>: 8013154: b538 push {r3, r4, r5, lr} 8013156: 4605 mov r5, r0 8013158: 2900 cmp r1, #0 801315a: d040 beq.n 80131de <_free_r+0x8a> 801315c: f851 3c04 ldr.w r3, [r1, #-4] 8013160: 1f0c subs r4, r1, #4 8013162: 2b00 cmp r3, #0 8013164: bfb8 it lt 8013166: 18e4 addlt r4, r4, r3 8013168: f000 f8de bl 8013328 <__malloc_lock> 801316c: 4a1c ldr r2, [pc, #112] @ (80131e0 <_free_r+0x8c>) 801316e: 6813 ldr r3, [r2, #0] 8013170: b933 cbnz r3, 8013180 <_free_r+0x2c> 8013172: 6063 str r3, [r4, #4] 8013174: 6014 str r4, [r2, #0] 8013176: 4628 mov r0, r5 8013178: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 801317c: f000 b8da b.w 8013334 <__malloc_unlock> 8013180: 42a3 cmp r3, r4 8013182: d908 bls.n 8013196 <_free_r+0x42> 8013184: 6820 ldr r0, [r4, #0] 8013186: 1821 adds r1, r4, r0 8013188: 428b cmp r3, r1 801318a: bf01 itttt eq 801318c: 6819 ldreq r1, [r3, #0] 801318e: 685b ldreq r3, [r3, #4] 8013190: 1809 addeq r1, r1, r0 8013192: 6021 streq r1, [r4, #0] 8013194: e7ed b.n 8013172 <_free_r+0x1e> 8013196: 461a mov r2, r3 8013198: 685b ldr r3, [r3, #4] 801319a: b10b cbz r3, 80131a0 <_free_r+0x4c> 801319c: 42a3 cmp r3, r4 801319e: d9fa bls.n 8013196 <_free_r+0x42> 80131a0: 6811 ldr r1, [r2, #0] 80131a2: 1850 adds r0, r2, r1 80131a4: 42a0 cmp r0, r4 80131a6: d10b bne.n 80131c0 <_free_r+0x6c> 80131a8: 6820 ldr r0, [r4, #0] 80131aa: 4401 add r1, r0 80131ac: 1850 adds r0, r2, r1 80131ae: 4283 cmp r3, r0 80131b0: 6011 str r1, [r2, #0] 80131b2: d1e0 bne.n 8013176 <_free_r+0x22> 80131b4: 6818 ldr r0, [r3, #0] 80131b6: 685b ldr r3, [r3, #4] 80131b8: 4408 add r0, r1 80131ba: 6010 str r0, [r2, #0] 80131bc: 6053 str r3, [r2, #4] 80131be: e7da b.n 8013176 <_free_r+0x22> 80131c0: d902 bls.n 80131c8 <_free_r+0x74> 80131c2: 230c movs r3, #12 80131c4: 602b str r3, [r5, #0] 80131c6: e7d6 b.n 8013176 <_free_r+0x22> 80131c8: 6820 ldr r0, [r4, #0] 80131ca: 1821 adds r1, r4, r0 80131cc: 428b cmp r3, r1 80131ce: bf01 itttt eq 80131d0: 6819 ldreq r1, [r3, #0] 80131d2: 685b ldreq r3, [r3, #4] 80131d4: 1809 addeq r1, r1, r0 80131d6: 6021 streq r1, [r4, #0] 80131d8: 6063 str r3, [r4, #4] 80131da: 6054 str r4, [r2, #4] 80131dc: e7cb b.n 8013176 <_free_r+0x22> 80131de: bd38 pop {r3, r4, r5, pc} 80131e0: 200011c4 .word 0x200011c4 080131e4 : 80131e4: b570 push {r4, r5, r6, lr} 80131e6: 4e0f ldr r6, [pc, #60] @ (8013224 ) 80131e8: 460c mov r4, r1 80131ea: 6831 ldr r1, [r6, #0] 80131ec: 4605 mov r5, r0 80131ee: b911 cbnz r1, 80131f6 80131f0: f000 fe24 bl 8013e3c <_sbrk_r> 80131f4: 6030 str r0, [r6, #0] 80131f6: 4621 mov r1, r4 80131f8: 4628 mov r0, r5 80131fa: f000 fe1f bl 8013e3c <_sbrk_r> 80131fe: 1c43 adds r3, r0, #1 8013200: d103 bne.n 801320a 8013202: f04f 34ff mov.w r4, #4294967295 8013206: 4620 mov r0, r4 8013208: bd70 pop {r4, r5, r6, pc} 801320a: 1cc4 adds r4, r0, #3 801320c: f024 0403 bic.w r4, r4, #3 8013210: 42a0 cmp r0, r4 8013212: d0f8 beq.n 8013206 8013214: 1a21 subs r1, r4, r0 8013216: 4628 mov r0, r5 8013218: f000 fe10 bl 8013e3c <_sbrk_r> 801321c: 3001 adds r0, #1 801321e: d1f2 bne.n 8013206 8013220: e7ef b.n 8013202 8013222: bf00 nop 8013224: 200011c0 .word 0x200011c0 08013228 <_malloc_r>: 8013228: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 801322c: 1ccd adds r5, r1, #3 801322e: f025 0503 bic.w r5, r5, #3 8013232: 3508 adds r5, #8 8013234: 2d0c cmp r5, #12 8013236: bf38 it cc 8013238: 250c movcc r5, #12 801323a: 2d00 cmp r5, #0 801323c: 4606 mov r6, r0 801323e: db01 blt.n 8013244 <_malloc_r+0x1c> 8013240: 42a9 cmp r1, r5 8013242: d904 bls.n 801324e <_malloc_r+0x26> 8013244: 230c movs r3, #12 8013246: 6033 str r3, [r6, #0] 8013248: 2000 movs r0, #0 801324a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 801324e: f8df 80d4 ldr.w r8, [pc, #212] @ 8013324 <_malloc_r+0xfc> 8013252: f000 f869 bl 8013328 <__malloc_lock> 8013256: f8d8 3000 ldr.w r3, [r8] 801325a: 461c mov r4, r3 801325c: bb44 cbnz r4, 80132b0 <_malloc_r+0x88> 801325e: 4629 mov r1, r5 8013260: 4630 mov r0, r6 8013262: f7ff ffbf bl 80131e4 8013266: 1c43 adds r3, r0, #1 8013268: 4604 mov r4, r0 801326a: d158 bne.n 801331e <_malloc_r+0xf6> 801326c: f8d8 4000 ldr.w r4, [r8] 8013270: 4627 mov r7, r4 8013272: 2f00 cmp r7, #0 8013274: d143 bne.n 80132fe <_malloc_r+0xd6> 8013276: 2c00 cmp r4, #0 8013278: d04b beq.n 8013312 <_malloc_r+0xea> 801327a: 6823 ldr r3, [r4, #0] 801327c: 4639 mov r1, r7 801327e: 4630 mov r0, r6 8013280: eb04 0903 add.w r9, r4, r3 8013284: f000 fdda bl 8013e3c <_sbrk_r> 8013288: 4581 cmp r9, r0 801328a: d142 bne.n 8013312 <_malloc_r+0xea> 801328c: 6821 ldr r1, [r4, #0] 801328e: 4630 mov r0, r6 8013290: 1a6d subs r5, r5, r1 8013292: 4629 mov r1, r5 8013294: f7ff ffa6 bl 80131e4 8013298: 3001 adds r0, #1 801329a: d03a beq.n 8013312 <_malloc_r+0xea> 801329c: 6823 ldr r3, [r4, #0] 801329e: 442b add r3, r5 80132a0: 6023 str r3, [r4, #0] 80132a2: f8d8 3000 ldr.w r3, [r8] 80132a6: 685a ldr r2, [r3, #4] 80132a8: bb62 cbnz r2, 8013304 <_malloc_r+0xdc> 80132aa: f8c8 7000 str.w r7, [r8] 80132ae: e00f b.n 80132d0 <_malloc_r+0xa8> 80132b0: 6822 ldr r2, [r4, #0] 80132b2: 1b52 subs r2, r2, r5 80132b4: d420 bmi.n 80132f8 <_malloc_r+0xd0> 80132b6: 2a0b cmp r2, #11 80132b8: d917 bls.n 80132ea <_malloc_r+0xc2> 80132ba: 1961 adds r1, r4, r5 80132bc: 42a3 cmp r3, r4 80132be: 6025 str r5, [r4, #0] 80132c0: bf18 it ne 80132c2: 6059 strne r1, [r3, #4] 80132c4: 6863 ldr r3, [r4, #4] 80132c6: bf08 it eq 80132c8: f8c8 1000 streq.w r1, [r8] 80132cc: 5162 str r2, [r4, r5] 80132ce: 604b str r3, [r1, #4] 80132d0: 4630 mov r0, r6 80132d2: f000 f82f bl 8013334 <__malloc_unlock> 80132d6: f104 000b add.w r0, r4, #11 80132da: 1d23 adds r3, r4, #4 80132dc: f020 0007 bic.w r0, r0, #7 80132e0: 1ac2 subs r2, r0, r3 80132e2: bf1c itt ne 80132e4: 1a1b subne r3, r3, r0 80132e6: 50a3 strne r3, [r4, r2] 80132e8: e7af b.n 801324a <_malloc_r+0x22> 80132ea: 6862 ldr r2, [r4, #4] 80132ec: 42a3 cmp r3, r4 80132ee: bf0c ite eq 80132f0: f8c8 2000 streq.w r2, [r8] 80132f4: 605a strne r2, [r3, #4] 80132f6: e7eb b.n 80132d0 <_malloc_r+0xa8> 80132f8: 4623 mov r3, r4 80132fa: 6864 ldr r4, [r4, #4] 80132fc: e7ae b.n 801325c <_malloc_r+0x34> 80132fe: 463c mov r4, r7 8013300: 687f ldr r7, [r7, #4] 8013302: e7b6 b.n 8013272 <_malloc_r+0x4a> 8013304: 461a mov r2, r3 8013306: 685b ldr r3, [r3, #4] 8013308: 42a3 cmp r3, r4 801330a: d1fb bne.n 8013304 <_malloc_r+0xdc> 801330c: 2300 movs r3, #0 801330e: 6053 str r3, [r2, #4] 8013310: e7de b.n 80132d0 <_malloc_r+0xa8> 8013312: 230c movs r3, #12 8013314: 4630 mov r0, r6 8013316: 6033 str r3, [r6, #0] 8013318: f000 f80c bl 8013334 <__malloc_unlock> 801331c: e794 b.n 8013248 <_malloc_r+0x20> 801331e: 6005 str r5, [r0, #0] 8013320: e7d6 b.n 80132d0 <_malloc_r+0xa8> 8013322: bf00 nop 8013324: 200011c4 .word 0x200011c4 08013328 <__malloc_lock>: 8013328: 4801 ldr r0, [pc, #4] @ (8013330 <__malloc_lock+0x8>) 801332a: f7ff bf02 b.w 8013132 <__retarget_lock_acquire_recursive> 801332e: bf00 nop 8013330: 200011bc .word 0x200011bc 08013334 <__malloc_unlock>: 8013334: 4801 ldr r0, [pc, #4] @ (801333c <__malloc_unlock+0x8>) 8013336: f7ff befd b.w 8013134 <__retarget_lock_release_recursive> 801333a: bf00 nop 801333c: 200011bc .word 0x200011bc 08013340 <__ssputs_r>: 8013340: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8013344: 461f mov r7, r3 8013346: 688e ldr r6, [r1, #8] 8013348: 4682 mov sl, r0 801334a: 42be cmp r6, r7 801334c: 460c mov r4, r1 801334e: 4690 mov r8, r2 8013350: 680b ldr r3, [r1, #0] 8013352: d82d bhi.n 80133b0 <__ssputs_r+0x70> 8013354: f9b1 200c ldrsh.w r2, [r1, #12] 8013358: f412 6f90 tst.w r2, #1152 @ 0x480 801335c: d026 beq.n 80133ac <__ssputs_r+0x6c> 801335e: 6965 ldr r5, [r4, #20] 8013360: 6909 ldr r1, [r1, #16] 8013362: eb05 0545 add.w r5, r5, r5, lsl #1 8013366: eba3 0901 sub.w r9, r3, r1 801336a: eb05 75d5 add.w r5, r5, r5, lsr #31 801336e: 1c7b adds r3, r7, #1 8013370: 444b add r3, r9 8013372: 106d asrs r5, r5, #1 8013374: 429d cmp r5, r3 8013376: bf38 it cc 8013378: 461d movcc r5, r3 801337a: 0553 lsls r3, r2, #21 801337c: d527 bpl.n 80133ce <__ssputs_r+0x8e> 801337e: 4629 mov r1, r5 8013380: f7ff ff52 bl 8013228 <_malloc_r> 8013384: 4606 mov r6, r0 8013386: b360 cbz r0, 80133e2 <__ssputs_r+0xa2> 8013388: 464a mov r2, r9 801338a: 6921 ldr r1, [r4, #16] 801338c: f7ff fed3 bl 8013136 8013390: 89a3 ldrh r3, [r4, #12] 8013392: f423 6390 bic.w r3, r3, #1152 @ 0x480 8013396: f043 0380 orr.w r3, r3, #128 @ 0x80 801339a: 81a3 strh r3, [r4, #12] 801339c: 6126 str r6, [r4, #16] 801339e: 444e add r6, r9 80133a0: 6026 str r6, [r4, #0] 80133a2: 463e mov r6, r7 80133a4: 6165 str r5, [r4, #20] 80133a6: eba5 0509 sub.w r5, r5, r9 80133aa: 60a5 str r5, [r4, #8] 80133ac: 42be cmp r6, r7 80133ae: d900 bls.n 80133b2 <__ssputs_r+0x72> 80133b0: 463e mov r6, r7 80133b2: 4632 mov r2, r6 80133b4: 4641 mov r1, r8 80133b6: 6820 ldr r0, [r4, #0] 80133b8: f000 fd26 bl 8013e08 80133bc: 2000 movs r0, #0 80133be: 68a3 ldr r3, [r4, #8] 80133c0: 1b9b subs r3, r3, r6 80133c2: 60a3 str r3, [r4, #8] 80133c4: 6823 ldr r3, [r4, #0] 80133c6: 4433 add r3, r6 80133c8: 6023 str r3, [r4, #0] 80133ca: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80133ce: 462a mov r2, r5 80133d0: f000 fd52 bl 8013e78 <_realloc_r> 80133d4: 4606 mov r6, r0 80133d6: 2800 cmp r0, #0 80133d8: d1e0 bne.n 801339c <__ssputs_r+0x5c> 80133da: 4650 mov r0, sl 80133dc: 6921 ldr r1, [r4, #16] 80133de: f7ff feb9 bl 8013154 <_free_r> 80133e2: 230c movs r3, #12 80133e4: f8ca 3000 str.w r3, [sl] 80133e8: 89a3 ldrh r3, [r4, #12] 80133ea: f04f 30ff mov.w r0, #4294967295 80133ee: f043 0340 orr.w r3, r3, #64 @ 0x40 80133f2: 81a3 strh r3, [r4, #12] 80133f4: e7e9 b.n 80133ca <__ssputs_r+0x8a> ... 080133f8 <_svfiprintf_r>: 80133f8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80133fc: 4698 mov r8, r3 80133fe: 898b ldrh r3, [r1, #12] 8013400: 4607 mov r7, r0 8013402: 061b lsls r3, r3, #24 8013404: 460d mov r5, r1 8013406: 4614 mov r4, r2 8013408: b09d sub sp, #116 @ 0x74 801340a: d510 bpl.n 801342e <_svfiprintf_r+0x36> 801340c: 690b ldr r3, [r1, #16] 801340e: b973 cbnz r3, 801342e <_svfiprintf_r+0x36> 8013410: 2140 movs r1, #64 @ 0x40 8013412: f7ff ff09 bl 8013228 <_malloc_r> 8013416: 6028 str r0, [r5, #0] 8013418: 6128 str r0, [r5, #16] 801341a: b930 cbnz r0, 801342a <_svfiprintf_r+0x32> 801341c: 230c movs r3, #12 801341e: 603b str r3, [r7, #0] 8013420: f04f 30ff mov.w r0, #4294967295 8013424: b01d add sp, #116 @ 0x74 8013426: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801342a: 2340 movs r3, #64 @ 0x40 801342c: 616b str r3, [r5, #20] 801342e: 2300 movs r3, #0 8013430: 9309 str r3, [sp, #36] @ 0x24 8013432: 2320 movs r3, #32 8013434: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8013438: 2330 movs r3, #48 @ 0x30 801343a: f04f 0901 mov.w r9, #1 801343e: f8cd 800c str.w r8, [sp, #12] 8013442: f8df 8198 ldr.w r8, [pc, #408] @ 80135dc <_svfiprintf_r+0x1e4> 8013446: f88d 302a strb.w r3, [sp, #42] @ 0x2a 801344a: 4623 mov r3, r4 801344c: 469a mov sl, r3 801344e: f813 2b01 ldrb.w r2, [r3], #1 8013452: b10a cbz r2, 8013458 <_svfiprintf_r+0x60> 8013454: 2a25 cmp r2, #37 @ 0x25 8013456: d1f9 bne.n 801344c <_svfiprintf_r+0x54> 8013458: ebba 0b04 subs.w fp, sl, r4 801345c: d00b beq.n 8013476 <_svfiprintf_r+0x7e> 801345e: 465b mov r3, fp 8013460: 4622 mov r2, r4 8013462: 4629 mov r1, r5 8013464: 4638 mov r0, r7 8013466: f7ff ff6b bl 8013340 <__ssputs_r> 801346a: 3001 adds r0, #1 801346c: f000 80a7 beq.w 80135be <_svfiprintf_r+0x1c6> 8013470: 9a09 ldr r2, [sp, #36] @ 0x24 8013472: 445a add r2, fp 8013474: 9209 str r2, [sp, #36] @ 0x24 8013476: f89a 3000 ldrb.w r3, [sl] 801347a: 2b00 cmp r3, #0 801347c: f000 809f beq.w 80135be <_svfiprintf_r+0x1c6> 8013480: 2300 movs r3, #0 8013482: f04f 32ff mov.w r2, #4294967295 8013486: e9cd 2305 strd r2, r3, [sp, #20] 801348a: f10a 0a01 add.w sl, sl, #1 801348e: 9304 str r3, [sp, #16] 8013490: 9307 str r3, [sp, #28] 8013492: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8013496: 931a str r3, [sp, #104] @ 0x68 8013498: 4654 mov r4, sl 801349a: 2205 movs r2, #5 801349c: f814 1b01 ldrb.w r1, [r4], #1 80134a0: 484e ldr r0, [pc, #312] @ (80135dc <_svfiprintf_r+0x1e4>) 80134a2: f000 fcdb bl 8013e5c 80134a6: 9a04 ldr r2, [sp, #16] 80134a8: b9d8 cbnz r0, 80134e2 <_svfiprintf_r+0xea> 80134aa: 06d0 lsls r0, r2, #27 80134ac: bf44 itt mi 80134ae: 2320 movmi r3, #32 80134b0: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 80134b4: 0711 lsls r1, r2, #28 80134b6: bf44 itt mi 80134b8: 232b movmi r3, #43 @ 0x2b 80134ba: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 80134be: f89a 3000 ldrb.w r3, [sl] 80134c2: 2b2a cmp r3, #42 @ 0x2a 80134c4: d015 beq.n 80134f2 <_svfiprintf_r+0xfa> 80134c6: 4654 mov r4, sl 80134c8: 2000 movs r0, #0 80134ca: f04f 0c0a mov.w ip, #10 80134ce: 9a07 ldr r2, [sp, #28] 80134d0: 4621 mov r1, r4 80134d2: f811 3b01 ldrb.w r3, [r1], #1 80134d6: 3b30 subs r3, #48 @ 0x30 80134d8: 2b09 cmp r3, #9 80134da: d94b bls.n 8013574 <_svfiprintf_r+0x17c> 80134dc: b1b0 cbz r0, 801350c <_svfiprintf_r+0x114> 80134de: 9207 str r2, [sp, #28] 80134e0: e014 b.n 801350c <_svfiprintf_r+0x114> 80134e2: eba0 0308 sub.w r3, r0, r8 80134e6: fa09 f303 lsl.w r3, r9, r3 80134ea: 4313 orrs r3, r2 80134ec: 46a2 mov sl, r4 80134ee: 9304 str r3, [sp, #16] 80134f0: e7d2 b.n 8013498 <_svfiprintf_r+0xa0> 80134f2: 9b03 ldr r3, [sp, #12] 80134f4: 1d19 adds r1, r3, #4 80134f6: 681b ldr r3, [r3, #0] 80134f8: 9103 str r1, [sp, #12] 80134fa: 2b00 cmp r3, #0 80134fc: bfbb ittet lt 80134fe: 425b neglt r3, r3 8013500: f042 0202 orrlt.w r2, r2, #2 8013504: 9307 strge r3, [sp, #28] 8013506: 9307 strlt r3, [sp, #28] 8013508: bfb8 it lt 801350a: 9204 strlt r2, [sp, #16] 801350c: 7823 ldrb r3, [r4, #0] 801350e: 2b2e cmp r3, #46 @ 0x2e 8013510: d10a bne.n 8013528 <_svfiprintf_r+0x130> 8013512: 7863 ldrb r3, [r4, #1] 8013514: 2b2a cmp r3, #42 @ 0x2a 8013516: d132 bne.n 801357e <_svfiprintf_r+0x186> 8013518: 9b03 ldr r3, [sp, #12] 801351a: 3402 adds r4, #2 801351c: 1d1a adds r2, r3, #4 801351e: 681b ldr r3, [r3, #0] 8013520: 9203 str r2, [sp, #12] 8013522: ea43 73e3 orr.w r3, r3, r3, asr #31 8013526: 9305 str r3, [sp, #20] 8013528: f8df a0b4 ldr.w sl, [pc, #180] @ 80135e0 <_svfiprintf_r+0x1e8> 801352c: 2203 movs r2, #3 801352e: 4650 mov r0, sl 8013530: 7821 ldrb r1, [r4, #0] 8013532: f000 fc93 bl 8013e5c 8013536: b138 cbz r0, 8013548 <_svfiprintf_r+0x150> 8013538: 2240 movs r2, #64 @ 0x40 801353a: 9b04 ldr r3, [sp, #16] 801353c: eba0 000a sub.w r0, r0, sl 8013540: 4082 lsls r2, r0 8013542: 4313 orrs r3, r2 8013544: 3401 adds r4, #1 8013546: 9304 str r3, [sp, #16] 8013548: f814 1b01 ldrb.w r1, [r4], #1 801354c: 2206 movs r2, #6 801354e: 4825 ldr r0, [pc, #148] @ (80135e4 <_svfiprintf_r+0x1ec>) 8013550: f88d 1028 strb.w r1, [sp, #40] @ 0x28 8013554: f000 fc82 bl 8013e5c 8013558: 2800 cmp r0, #0 801355a: d036 beq.n 80135ca <_svfiprintf_r+0x1d2> 801355c: 4b22 ldr r3, [pc, #136] @ (80135e8 <_svfiprintf_r+0x1f0>) 801355e: bb1b cbnz r3, 80135a8 <_svfiprintf_r+0x1b0> 8013560: 9b03 ldr r3, [sp, #12] 8013562: 3307 adds r3, #7 8013564: f023 0307 bic.w r3, r3, #7 8013568: 3308 adds r3, #8 801356a: 9303 str r3, [sp, #12] 801356c: 9b09 ldr r3, [sp, #36] @ 0x24 801356e: 4433 add r3, r6 8013570: 9309 str r3, [sp, #36] @ 0x24 8013572: e76a b.n 801344a <_svfiprintf_r+0x52> 8013574: 460c mov r4, r1 8013576: 2001 movs r0, #1 8013578: fb0c 3202 mla r2, ip, r2, r3 801357c: e7a8 b.n 80134d0 <_svfiprintf_r+0xd8> 801357e: 2300 movs r3, #0 8013580: f04f 0c0a mov.w ip, #10 8013584: 4619 mov r1, r3 8013586: 3401 adds r4, #1 8013588: 9305 str r3, [sp, #20] 801358a: 4620 mov r0, r4 801358c: f810 2b01 ldrb.w r2, [r0], #1 8013590: 3a30 subs r2, #48 @ 0x30 8013592: 2a09 cmp r2, #9 8013594: d903 bls.n 801359e <_svfiprintf_r+0x1a6> 8013596: 2b00 cmp r3, #0 8013598: d0c6 beq.n 8013528 <_svfiprintf_r+0x130> 801359a: 9105 str r1, [sp, #20] 801359c: e7c4 b.n 8013528 <_svfiprintf_r+0x130> 801359e: 4604 mov r4, r0 80135a0: 2301 movs r3, #1 80135a2: fb0c 2101 mla r1, ip, r1, r2 80135a6: e7f0 b.n 801358a <_svfiprintf_r+0x192> 80135a8: ab03 add r3, sp, #12 80135aa: 9300 str r3, [sp, #0] 80135ac: 462a mov r2, r5 80135ae: 4638 mov r0, r7 80135b0: 4b0e ldr r3, [pc, #56] @ (80135ec <_svfiprintf_r+0x1f4>) 80135b2: a904 add r1, sp, #16 80135b4: f3af 8000 nop.w 80135b8: 1c42 adds r2, r0, #1 80135ba: 4606 mov r6, r0 80135bc: d1d6 bne.n 801356c <_svfiprintf_r+0x174> 80135be: 89ab ldrh r3, [r5, #12] 80135c0: 065b lsls r3, r3, #25 80135c2: f53f af2d bmi.w 8013420 <_svfiprintf_r+0x28> 80135c6: 9809 ldr r0, [sp, #36] @ 0x24 80135c8: e72c b.n 8013424 <_svfiprintf_r+0x2c> 80135ca: ab03 add r3, sp, #12 80135cc: 9300 str r3, [sp, #0] 80135ce: 462a mov r2, r5 80135d0: 4638 mov r0, r7 80135d2: 4b06 ldr r3, [pc, #24] @ (80135ec <_svfiprintf_r+0x1f4>) 80135d4: a904 add r1, sp, #16 80135d6: f000 f9bd bl 8013954 <_printf_i> 80135da: e7ed b.n 80135b8 <_svfiprintf_r+0x1c0> 80135dc: 0801447c .word 0x0801447c 80135e0: 08014482 .word 0x08014482 80135e4: 08014486 .word 0x08014486 80135e8: 00000000 .word 0x00000000 80135ec: 08013341 .word 0x08013341 080135f0 <__sfputc_r>: 80135f0: 6893 ldr r3, [r2, #8] 80135f2: b410 push {r4} 80135f4: 3b01 subs r3, #1 80135f6: 2b00 cmp r3, #0 80135f8: 6093 str r3, [r2, #8] 80135fa: da07 bge.n 801360c <__sfputc_r+0x1c> 80135fc: 6994 ldr r4, [r2, #24] 80135fe: 42a3 cmp r3, r4 8013600: db01 blt.n 8013606 <__sfputc_r+0x16> 8013602: 290a cmp r1, #10 8013604: d102 bne.n 801360c <__sfputc_r+0x1c> 8013606: bc10 pop {r4} 8013608: f000 bb6a b.w 8013ce0 <__swbuf_r> 801360c: 6813 ldr r3, [r2, #0] 801360e: 1c58 adds r0, r3, #1 8013610: 6010 str r0, [r2, #0] 8013612: 7019 strb r1, [r3, #0] 8013614: 4608 mov r0, r1 8013616: bc10 pop {r4} 8013618: 4770 bx lr 0801361a <__sfputs_r>: 801361a: b5f8 push {r3, r4, r5, r6, r7, lr} 801361c: 4606 mov r6, r0 801361e: 460f mov r7, r1 8013620: 4614 mov r4, r2 8013622: 18d5 adds r5, r2, r3 8013624: 42ac cmp r4, r5 8013626: d101 bne.n 801362c <__sfputs_r+0x12> 8013628: 2000 movs r0, #0 801362a: e007 b.n 801363c <__sfputs_r+0x22> 801362c: 463a mov r2, r7 801362e: 4630 mov r0, r6 8013630: f814 1b01 ldrb.w r1, [r4], #1 8013634: f7ff ffdc bl 80135f0 <__sfputc_r> 8013638: 1c43 adds r3, r0, #1 801363a: d1f3 bne.n 8013624 <__sfputs_r+0xa> 801363c: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 08013640 <_vfiprintf_r>: 8013640: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8013644: 460d mov r5, r1 8013646: 4614 mov r4, r2 8013648: 4698 mov r8, r3 801364a: 4606 mov r6, r0 801364c: b09d sub sp, #116 @ 0x74 801364e: b118 cbz r0, 8013658 <_vfiprintf_r+0x18> 8013650: 6a03 ldr r3, [r0, #32] 8013652: b90b cbnz r3, 8013658 <_vfiprintf_r+0x18> 8013654: f7ff fc2c bl 8012eb0 <__sinit> 8013658: 6e6b ldr r3, [r5, #100] @ 0x64 801365a: 07d9 lsls r1, r3, #31 801365c: d405 bmi.n 801366a <_vfiprintf_r+0x2a> 801365e: 89ab ldrh r3, [r5, #12] 8013660: 059a lsls r2, r3, #22 8013662: d402 bmi.n 801366a <_vfiprintf_r+0x2a> 8013664: 6da8 ldr r0, [r5, #88] @ 0x58 8013666: f7ff fd64 bl 8013132 <__retarget_lock_acquire_recursive> 801366a: 89ab ldrh r3, [r5, #12] 801366c: 071b lsls r3, r3, #28 801366e: d501 bpl.n 8013674 <_vfiprintf_r+0x34> 8013670: 692b ldr r3, [r5, #16] 8013672: b99b cbnz r3, 801369c <_vfiprintf_r+0x5c> 8013674: 4629 mov r1, r5 8013676: 4630 mov r0, r6 8013678: f000 fb70 bl 8013d5c <__swsetup_r> 801367c: b170 cbz r0, 801369c <_vfiprintf_r+0x5c> 801367e: 6e6b ldr r3, [r5, #100] @ 0x64 8013680: 07dc lsls r4, r3, #31 8013682: d504 bpl.n 801368e <_vfiprintf_r+0x4e> 8013684: f04f 30ff mov.w r0, #4294967295 8013688: b01d add sp, #116 @ 0x74 801368a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801368e: 89ab ldrh r3, [r5, #12] 8013690: 0598 lsls r0, r3, #22 8013692: d4f7 bmi.n 8013684 <_vfiprintf_r+0x44> 8013694: 6da8 ldr r0, [r5, #88] @ 0x58 8013696: f7ff fd4d bl 8013134 <__retarget_lock_release_recursive> 801369a: e7f3 b.n 8013684 <_vfiprintf_r+0x44> 801369c: 2300 movs r3, #0 801369e: 9309 str r3, [sp, #36] @ 0x24 80136a0: 2320 movs r3, #32 80136a2: f88d 3029 strb.w r3, [sp, #41] @ 0x29 80136a6: 2330 movs r3, #48 @ 0x30 80136a8: f04f 0901 mov.w r9, #1 80136ac: f8cd 800c str.w r8, [sp, #12] 80136b0: f8df 81a8 ldr.w r8, [pc, #424] @ 801385c <_vfiprintf_r+0x21c> 80136b4: f88d 302a strb.w r3, [sp, #42] @ 0x2a 80136b8: 4623 mov r3, r4 80136ba: 469a mov sl, r3 80136bc: f813 2b01 ldrb.w r2, [r3], #1 80136c0: b10a cbz r2, 80136c6 <_vfiprintf_r+0x86> 80136c2: 2a25 cmp r2, #37 @ 0x25 80136c4: d1f9 bne.n 80136ba <_vfiprintf_r+0x7a> 80136c6: ebba 0b04 subs.w fp, sl, r4 80136ca: d00b beq.n 80136e4 <_vfiprintf_r+0xa4> 80136cc: 465b mov r3, fp 80136ce: 4622 mov r2, r4 80136d0: 4629 mov r1, r5 80136d2: 4630 mov r0, r6 80136d4: f7ff ffa1 bl 801361a <__sfputs_r> 80136d8: 3001 adds r0, #1 80136da: f000 80a7 beq.w 801382c <_vfiprintf_r+0x1ec> 80136de: 9a09 ldr r2, [sp, #36] @ 0x24 80136e0: 445a add r2, fp 80136e2: 9209 str r2, [sp, #36] @ 0x24 80136e4: f89a 3000 ldrb.w r3, [sl] 80136e8: 2b00 cmp r3, #0 80136ea: f000 809f beq.w 801382c <_vfiprintf_r+0x1ec> 80136ee: 2300 movs r3, #0 80136f0: f04f 32ff mov.w r2, #4294967295 80136f4: e9cd 2305 strd r2, r3, [sp, #20] 80136f8: f10a 0a01 add.w sl, sl, #1 80136fc: 9304 str r3, [sp, #16] 80136fe: 9307 str r3, [sp, #28] 8013700: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8013704: 931a str r3, [sp, #104] @ 0x68 8013706: 4654 mov r4, sl 8013708: 2205 movs r2, #5 801370a: f814 1b01 ldrb.w r1, [r4], #1 801370e: 4853 ldr r0, [pc, #332] @ (801385c <_vfiprintf_r+0x21c>) 8013710: f000 fba4 bl 8013e5c 8013714: 9a04 ldr r2, [sp, #16] 8013716: b9d8 cbnz r0, 8013750 <_vfiprintf_r+0x110> 8013718: 06d1 lsls r1, r2, #27 801371a: bf44 itt mi 801371c: 2320 movmi r3, #32 801371e: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8013722: 0713 lsls r3, r2, #28 8013724: bf44 itt mi 8013726: 232b movmi r3, #43 @ 0x2b 8013728: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 801372c: f89a 3000 ldrb.w r3, [sl] 8013730: 2b2a cmp r3, #42 @ 0x2a 8013732: d015 beq.n 8013760 <_vfiprintf_r+0x120> 8013734: 4654 mov r4, sl 8013736: 2000 movs r0, #0 8013738: f04f 0c0a mov.w ip, #10 801373c: 9a07 ldr r2, [sp, #28] 801373e: 4621 mov r1, r4 8013740: f811 3b01 ldrb.w r3, [r1], #1 8013744: 3b30 subs r3, #48 @ 0x30 8013746: 2b09 cmp r3, #9 8013748: d94b bls.n 80137e2 <_vfiprintf_r+0x1a2> 801374a: b1b0 cbz r0, 801377a <_vfiprintf_r+0x13a> 801374c: 9207 str r2, [sp, #28] 801374e: e014 b.n 801377a <_vfiprintf_r+0x13a> 8013750: eba0 0308 sub.w r3, r0, r8 8013754: fa09 f303 lsl.w r3, r9, r3 8013758: 4313 orrs r3, r2 801375a: 46a2 mov sl, r4 801375c: 9304 str r3, [sp, #16] 801375e: e7d2 b.n 8013706 <_vfiprintf_r+0xc6> 8013760: 9b03 ldr r3, [sp, #12] 8013762: 1d19 adds r1, r3, #4 8013764: 681b ldr r3, [r3, #0] 8013766: 9103 str r1, [sp, #12] 8013768: 2b00 cmp r3, #0 801376a: bfbb ittet lt 801376c: 425b neglt r3, r3 801376e: f042 0202 orrlt.w r2, r2, #2 8013772: 9307 strge r3, [sp, #28] 8013774: 9307 strlt r3, [sp, #28] 8013776: bfb8 it lt 8013778: 9204 strlt r2, [sp, #16] 801377a: 7823 ldrb r3, [r4, #0] 801377c: 2b2e cmp r3, #46 @ 0x2e 801377e: d10a bne.n 8013796 <_vfiprintf_r+0x156> 8013780: 7863 ldrb r3, [r4, #1] 8013782: 2b2a cmp r3, #42 @ 0x2a 8013784: d132 bne.n 80137ec <_vfiprintf_r+0x1ac> 8013786: 9b03 ldr r3, [sp, #12] 8013788: 3402 adds r4, #2 801378a: 1d1a adds r2, r3, #4 801378c: 681b ldr r3, [r3, #0] 801378e: 9203 str r2, [sp, #12] 8013790: ea43 73e3 orr.w r3, r3, r3, asr #31 8013794: 9305 str r3, [sp, #20] 8013796: f8df a0c8 ldr.w sl, [pc, #200] @ 8013860 <_vfiprintf_r+0x220> 801379a: 2203 movs r2, #3 801379c: 4650 mov r0, sl 801379e: 7821 ldrb r1, [r4, #0] 80137a0: f000 fb5c bl 8013e5c 80137a4: b138 cbz r0, 80137b6 <_vfiprintf_r+0x176> 80137a6: 2240 movs r2, #64 @ 0x40 80137a8: 9b04 ldr r3, [sp, #16] 80137aa: eba0 000a sub.w r0, r0, sl 80137ae: 4082 lsls r2, r0 80137b0: 4313 orrs r3, r2 80137b2: 3401 adds r4, #1 80137b4: 9304 str r3, [sp, #16] 80137b6: f814 1b01 ldrb.w r1, [r4], #1 80137ba: 2206 movs r2, #6 80137bc: 4829 ldr r0, [pc, #164] @ (8013864 <_vfiprintf_r+0x224>) 80137be: f88d 1028 strb.w r1, [sp, #40] @ 0x28 80137c2: f000 fb4b bl 8013e5c 80137c6: 2800 cmp r0, #0 80137c8: d03f beq.n 801384a <_vfiprintf_r+0x20a> 80137ca: 4b27 ldr r3, [pc, #156] @ (8013868 <_vfiprintf_r+0x228>) 80137cc: bb1b cbnz r3, 8013816 <_vfiprintf_r+0x1d6> 80137ce: 9b03 ldr r3, [sp, #12] 80137d0: 3307 adds r3, #7 80137d2: f023 0307 bic.w r3, r3, #7 80137d6: 3308 adds r3, #8 80137d8: 9303 str r3, [sp, #12] 80137da: 9b09 ldr r3, [sp, #36] @ 0x24 80137dc: 443b add r3, r7 80137de: 9309 str r3, [sp, #36] @ 0x24 80137e0: e76a b.n 80136b8 <_vfiprintf_r+0x78> 80137e2: 460c mov r4, r1 80137e4: 2001 movs r0, #1 80137e6: fb0c 3202 mla r2, ip, r2, r3 80137ea: e7a8 b.n 801373e <_vfiprintf_r+0xfe> 80137ec: 2300 movs r3, #0 80137ee: f04f 0c0a mov.w ip, #10 80137f2: 4619 mov r1, r3 80137f4: 3401 adds r4, #1 80137f6: 9305 str r3, [sp, #20] 80137f8: 4620 mov r0, r4 80137fa: f810 2b01 ldrb.w r2, [r0], #1 80137fe: 3a30 subs r2, #48 @ 0x30 8013800: 2a09 cmp r2, #9 8013802: d903 bls.n 801380c <_vfiprintf_r+0x1cc> 8013804: 2b00 cmp r3, #0 8013806: d0c6 beq.n 8013796 <_vfiprintf_r+0x156> 8013808: 9105 str r1, [sp, #20] 801380a: e7c4 b.n 8013796 <_vfiprintf_r+0x156> 801380c: 4604 mov r4, r0 801380e: 2301 movs r3, #1 8013810: fb0c 2101 mla r1, ip, r1, r2 8013814: e7f0 b.n 80137f8 <_vfiprintf_r+0x1b8> 8013816: ab03 add r3, sp, #12 8013818: 9300 str r3, [sp, #0] 801381a: 462a mov r2, r5 801381c: 4630 mov r0, r6 801381e: 4b13 ldr r3, [pc, #76] @ (801386c <_vfiprintf_r+0x22c>) 8013820: a904 add r1, sp, #16 8013822: f3af 8000 nop.w 8013826: 4607 mov r7, r0 8013828: 1c78 adds r0, r7, #1 801382a: d1d6 bne.n 80137da <_vfiprintf_r+0x19a> 801382c: 6e6b ldr r3, [r5, #100] @ 0x64 801382e: 07d9 lsls r1, r3, #31 8013830: d405 bmi.n 801383e <_vfiprintf_r+0x1fe> 8013832: 89ab ldrh r3, [r5, #12] 8013834: 059a lsls r2, r3, #22 8013836: d402 bmi.n 801383e <_vfiprintf_r+0x1fe> 8013838: 6da8 ldr r0, [r5, #88] @ 0x58 801383a: f7ff fc7b bl 8013134 <__retarget_lock_release_recursive> 801383e: 89ab ldrh r3, [r5, #12] 8013840: 065b lsls r3, r3, #25 8013842: f53f af1f bmi.w 8013684 <_vfiprintf_r+0x44> 8013846: 9809 ldr r0, [sp, #36] @ 0x24 8013848: e71e b.n 8013688 <_vfiprintf_r+0x48> 801384a: ab03 add r3, sp, #12 801384c: 9300 str r3, [sp, #0] 801384e: 462a mov r2, r5 8013850: 4630 mov r0, r6 8013852: 4b06 ldr r3, [pc, #24] @ (801386c <_vfiprintf_r+0x22c>) 8013854: a904 add r1, sp, #16 8013856: f000 f87d bl 8013954 <_printf_i> 801385a: e7e4 b.n 8013826 <_vfiprintf_r+0x1e6> 801385c: 0801447c .word 0x0801447c 8013860: 08014482 .word 0x08014482 8013864: 08014486 .word 0x08014486 8013868: 00000000 .word 0x00000000 801386c: 0801361b .word 0x0801361b 08013870 <_printf_common>: 8013870: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8013874: 4616 mov r6, r2 8013876: 4698 mov r8, r3 8013878: 688a ldr r2, [r1, #8] 801387a: 690b ldr r3, [r1, #16] 801387c: 4607 mov r7, r0 801387e: 4293 cmp r3, r2 8013880: bfb8 it lt 8013882: 4613 movlt r3, r2 8013884: 6033 str r3, [r6, #0] 8013886: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 801388a: 460c mov r4, r1 801388c: f8dd 9020 ldr.w r9, [sp, #32] 8013890: b10a cbz r2, 8013896 <_printf_common+0x26> 8013892: 3301 adds r3, #1 8013894: 6033 str r3, [r6, #0] 8013896: 6823 ldr r3, [r4, #0] 8013898: 0699 lsls r1, r3, #26 801389a: bf42 ittt mi 801389c: 6833 ldrmi r3, [r6, #0] 801389e: 3302 addmi r3, #2 80138a0: 6033 strmi r3, [r6, #0] 80138a2: 6825 ldr r5, [r4, #0] 80138a4: f015 0506 ands.w r5, r5, #6 80138a8: d106 bne.n 80138b8 <_printf_common+0x48> 80138aa: f104 0a19 add.w sl, r4, #25 80138ae: 68e3 ldr r3, [r4, #12] 80138b0: 6832 ldr r2, [r6, #0] 80138b2: 1a9b subs r3, r3, r2 80138b4: 42ab cmp r3, r5 80138b6: dc2b bgt.n 8013910 <_printf_common+0xa0> 80138b8: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 80138bc: 6822 ldr r2, [r4, #0] 80138be: 3b00 subs r3, #0 80138c0: bf18 it ne 80138c2: 2301 movne r3, #1 80138c4: 0692 lsls r2, r2, #26 80138c6: d430 bmi.n 801392a <_printf_common+0xba> 80138c8: 4641 mov r1, r8 80138ca: 4638 mov r0, r7 80138cc: f104 0243 add.w r2, r4, #67 @ 0x43 80138d0: 47c8 blx r9 80138d2: 3001 adds r0, #1 80138d4: d023 beq.n 801391e <_printf_common+0xae> 80138d6: 6823 ldr r3, [r4, #0] 80138d8: 6922 ldr r2, [r4, #16] 80138da: f003 0306 and.w r3, r3, #6 80138de: 2b04 cmp r3, #4 80138e0: bf14 ite ne 80138e2: 2500 movne r5, #0 80138e4: 6833 ldreq r3, [r6, #0] 80138e6: f04f 0600 mov.w r6, #0 80138ea: bf08 it eq 80138ec: 68e5 ldreq r5, [r4, #12] 80138ee: f104 041a add.w r4, r4, #26 80138f2: bf08 it eq 80138f4: 1aed subeq r5, r5, r3 80138f6: f854 3c12 ldr.w r3, [r4, #-18] 80138fa: bf08 it eq 80138fc: ea25 75e5 biceq.w r5, r5, r5, asr #31 8013900: 4293 cmp r3, r2 8013902: bfc4 itt gt 8013904: 1a9b subgt r3, r3, r2 8013906: 18ed addgt r5, r5, r3 8013908: 42b5 cmp r5, r6 801390a: d11a bne.n 8013942 <_printf_common+0xd2> 801390c: 2000 movs r0, #0 801390e: e008 b.n 8013922 <_printf_common+0xb2> 8013910: 2301 movs r3, #1 8013912: 4652 mov r2, sl 8013914: 4641 mov r1, r8 8013916: 4638 mov r0, r7 8013918: 47c8 blx r9 801391a: 3001 adds r0, #1 801391c: d103 bne.n 8013926 <_printf_common+0xb6> 801391e: f04f 30ff mov.w r0, #4294967295 8013922: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8013926: 3501 adds r5, #1 8013928: e7c1 b.n 80138ae <_printf_common+0x3e> 801392a: 2030 movs r0, #48 @ 0x30 801392c: 18e1 adds r1, r4, r3 801392e: f881 0043 strb.w r0, [r1, #67] @ 0x43 8013932: 1c5a adds r2, r3, #1 8013934: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 8013938: 4422 add r2, r4 801393a: 3302 adds r3, #2 801393c: f882 1043 strb.w r1, [r2, #67] @ 0x43 8013940: e7c2 b.n 80138c8 <_printf_common+0x58> 8013942: 2301 movs r3, #1 8013944: 4622 mov r2, r4 8013946: 4641 mov r1, r8 8013948: 4638 mov r0, r7 801394a: 47c8 blx r9 801394c: 3001 adds r0, #1 801394e: d0e6 beq.n 801391e <_printf_common+0xae> 8013950: 3601 adds r6, #1 8013952: e7d9 b.n 8013908 <_printf_common+0x98> 08013954 <_printf_i>: 8013954: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8013958: 7e0f ldrb r7, [r1, #24] 801395a: 4691 mov r9, r2 801395c: 2f78 cmp r7, #120 @ 0x78 801395e: 4680 mov r8, r0 8013960: 460c mov r4, r1 8013962: 469a mov sl, r3 8013964: 9e0c ldr r6, [sp, #48] @ 0x30 8013966: f101 0243 add.w r2, r1, #67 @ 0x43 801396a: d807 bhi.n 801397c <_printf_i+0x28> 801396c: 2f62 cmp r7, #98 @ 0x62 801396e: d80a bhi.n 8013986 <_printf_i+0x32> 8013970: 2f00 cmp r7, #0 8013972: f000 80d1 beq.w 8013b18 <_printf_i+0x1c4> 8013976: 2f58 cmp r7, #88 @ 0x58 8013978: f000 80b8 beq.w 8013aec <_printf_i+0x198> 801397c: f104 0642 add.w r6, r4, #66 @ 0x42 8013980: f884 7042 strb.w r7, [r4, #66] @ 0x42 8013984: e03a b.n 80139fc <_printf_i+0xa8> 8013986: f1a7 0363 sub.w r3, r7, #99 @ 0x63 801398a: 2b15 cmp r3, #21 801398c: d8f6 bhi.n 801397c <_printf_i+0x28> 801398e: a101 add r1, pc, #4 @ (adr r1, 8013994 <_printf_i+0x40>) 8013990: f851 f023 ldr.w pc, [r1, r3, lsl #2] 8013994: 080139ed .word 0x080139ed 8013998: 08013a01 .word 0x08013a01 801399c: 0801397d .word 0x0801397d 80139a0: 0801397d .word 0x0801397d 80139a4: 0801397d .word 0x0801397d 80139a8: 0801397d .word 0x0801397d 80139ac: 08013a01 .word 0x08013a01 80139b0: 0801397d .word 0x0801397d 80139b4: 0801397d .word 0x0801397d 80139b8: 0801397d .word 0x0801397d 80139bc: 0801397d .word 0x0801397d 80139c0: 08013aff .word 0x08013aff 80139c4: 08013a2b .word 0x08013a2b 80139c8: 08013ab9 .word 0x08013ab9 80139cc: 0801397d .word 0x0801397d 80139d0: 0801397d .word 0x0801397d 80139d4: 08013b21 .word 0x08013b21 80139d8: 0801397d .word 0x0801397d 80139dc: 08013a2b .word 0x08013a2b 80139e0: 0801397d .word 0x0801397d 80139e4: 0801397d .word 0x0801397d 80139e8: 08013ac1 .word 0x08013ac1 80139ec: 6833 ldr r3, [r6, #0] 80139ee: 1d1a adds r2, r3, #4 80139f0: 681b ldr r3, [r3, #0] 80139f2: 6032 str r2, [r6, #0] 80139f4: f104 0642 add.w r6, r4, #66 @ 0x42 80139f8: f884 3042 strb.w r3, [r4, #66] @ 0x42 80139fc: 2301 movs r3, #1 80139fe: e09c b.n 8013b3a <_printf_i+0x1e6> 8013a00: 6833 ldr r3, [r6, #0] 8013a02: 6820 ldr r0, [r4, #0] 8013a04: 1d19 adds r1, r3, #4 8013a06: 6031 str r1, [r6, #0] 8013a08: 0606 lsls r6, r0, #24 8013a0a: d501 bpl.n 8013a10 <_printf_i+0xbc> 8013a0c: 681d ldr r5, [r3, #0] 8013a0e: e003 b.n 8013a18 <_printf_i+0xc4> 8013a10: 0645 lsls r5, r0, #25 8013a12: d5fb bpl.n 8013a0c <_printf_i+0xb8> 8013a14: f9b3 5000 ldrsh.w r5, [r3] 8013a18: 2d00 cmp r5, #0 8013a1a: da03 bge.n 8013a24 <_printf_i+0xd0> 8013a1c: 232d movs r3, #45 @ 0x2d 8013a1e: 426d negs r5, r5 8013a20: f884 3043 strb.w r3, [r4, #67] @ 0x43 8013a24: 230a movs r3, #10 8013a26: 4858 ldr r0, [pc, #352] @ (8013b88 <_printf_i+0x234>) 8013a28: e011 b.n 8013a4e <_printf_i+0xfa> 8013a2a: 6821 ldr r1, [r4, #0] 8013a2c: 6833 ldr r3, [r6, #0] 8013a2e: 0608 lsls r0, r1, #24 8013a30: f853 5b04 ldr.w r5, [r3], #4 8013a34: d402 bmi.n 8013a3c <_printf_i+0xe8> 8013a36: 0649 lsls r1, r1, #25 8013a38: bf48 it mi 8013a3a: b2ad uxthmi r5, r5 8013a3c: 2f6f cmp r7, #111 @ 0x6f 8013a3e: 6033 str r3, [r6, #0] 8013a40: bf14 ite ne 8013a42: 230a movne r3, #10 8013a44: 2308 moveq r3, #8 8013a46: 4850 ldr r0, [pc, #320] @ (8013b88 <_printf_i+0x234>) 8013a48: 2100 movs r1, #0 8013a4a: f884 1043 strb.w r1, [r4, #67] @ 0x43 8013a4e: 6866 ldr r6, [r4, #4] 8013a50: 2e00 cmp r6, #0 8013a52: 60a6 str r6, [r4, #8] 8013a54: db05 blt.n 8013a62 <_printf_i+0x10e> 8013a56: 6821 ldr r1, [r4, #0] 8013a58: 432e orrs r6, r5 8013a5a: f021 0104 bic.w r1, r1, #4 8013a5e: 6021 str r1, [r4, #0] 8013a60: d04b beq.n 8013afa <_printf_i+0x1a6> 8013a62: 4616 mov r6, r2 8013a64: fbb5 f1f3 udiv r1, r5, r3 8013a68: fb03 5711 mls r7, r3, r1, r5 8013a6c: 5dc7 ldrb r7, [r0, r7] 8013a6e: f806 7d01 strb.w r7, [r6, #-1]! 8013a72: 462f mov r7, r5 8013a74: 42bb cmp r3, r7 8013a76: 460d mov r5, r1 8013a78: d9f4 bls.n 8013a64 <_printf_i+0x110> 8013a7a: 2b08 cmp r3, #8 8013a7c: d10b bne.n 8013a96 <_printf_i+0x142> 8013a7e: 6823 ldr r3, [r4, #0] 8013a80: 07df lsls r7, r3, #31 8013a82: d508 bpl.n 8013a96 <_printf_i+0x142> 8013a84: 6923 ldr r3, [r4, #16] 8013a86: 6861 ldr r1, [r4, #4] 8013a88: 4299 cmp r1, r3 8013a8a: bfde ittt le 8013a8c: 2330 movle r3, #48 @ 0x30 8013a8e: f806 3c01 strble.w r3, [r6, #-1] 8013a92: f106 36ff addle.w r6, r6, #4294967295 8013a96: 1b92 subs r2, r2, r6 8013a98: 6122 str r2, [r4, #16] 8013a9a: 464b mov r3, r9 8013a9c: 4621 mov r1, r4 8013a9e: 4640 mov r0, r8 8013aa0: f8cd a000 str.w sl, [sp] 8013aa4: aa03 add r2, sp, #12 8013aa6: f7ff fee3 bl 8013870 <_printf_common> 8013aaa: 3001 adds r0, #1 8013aac: d14a bne.n 8013b44 <_printf_i+0x1f0> 8013aae: f04f 30ff mov.w r0, #4294967295 8013ab2: b004 add sp, #16 8013ab4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8013ab8: 6823 ldr r3, [r4, #0] 8013aba: f043 0320 orr.w r3, r3, #32 8013abe: 6023 str r3, [r4, #0] 8013ac0: 2778 movs r7, #120 @ 0x78 8013ac2: 4832 ldr r0, [pc, #200] @ (8013b8c <_printf_i+0x238>) 8013ac4: f884 7045 strb.w r7, [r4, #69] @ 0x45 8013ac8: 6823 ldr r3, [r4, #0] 8013aca: 6831 ldr r1, [r6, #0] 8013acc: 061f lsls r7, r3, #24 8013ace: f851 5b04 ldr.w r5, [r1], #4 8013ad2: d402 bmi.n 8013ada <_printf_i+0x186> 8013ad4: 065f lsls r7, r3, #25 8013ad6: bf48 it mi 8013ad8: b2ad uxthmi r5, r5 8013ada: 6031 str r1, [r6, #0] 8013adc: 07d9 lsls r1, r3, #31 8013ade: bf44 itt mi 8013ae0: f043 0320 orrmi.w r3, r3, #32 8013ae4: 6023 strmi r3, [r4, #0] 8013ae6: b11d cbz r5, 8013af0 <_printf_i+0x19c> 8013ae8: 2310 movs r3, #16 8013aea: e7ad b.n 8013a48 <_printf_i+0xf4> 8013aec: 4826 ldr r0, [pc, #152] @ (8013b88 <_printf_i+0x234>) 8013aee: e7e9 b.n 8013ac4 <_printf_i+0x170> 8013af0: 6823 ldr r3, [r4, #0] 8013af2: f023 0320 bic.w r3, r3, #32 8013af6: 6023 str r3, [r4, #0] 8013af8: e7f6 b.n 8013ae8 <_printf_i+0x194> 8013afa: 4616 mov r6, r2 8013afc: e7bd b.n 8013a7a <_printf_i+0x126> 8013afe: 6833 ldr r3, [r6, #0] 8013b00: 6825 ldr r5, [r4, #0] 8013b02: 1d18 adds r0, r3, #4 8013b04: 6961 ldr r1, [r4, #20] 8013b06: 6030 str r0, [r6, #0] 8013b08: 062e lsls r6, r5, #24 8013b0a: 681b ldr r3, [r3, #0] 8013b0c: d501 bpl.n 8013b12 <_printf_i+0x1be> 8013b0e: 6019 str r1, [r3, #0] 8013b10: e002 b.n 8013b18 <_printf_i+0x1c4> 8013b12: 0668 lsls r0, r5, #25 8013b14: d5fb bpl.n 8013b0e <_printf_i+0x1ba> 8013b16: 8019 strh r1, [r3, #0] 8013b18: 2300 movs r3, #0 8013b1a: 4616 mov r6, r2 8013b1c: 6123 str r3, [r4, #16] 8013b1e: e7bc b.n 8013a9a <_printf_i+0x146> 8013b20: 6833 ldr r3, [r6, #0] 8013b22: 2100 movs r1, #0 8013b24: 1d1a adds r2, r3, #4 8013b26: 6032 str r2, [r6, #0] 8013b28: 681e ldr r6, [r3, #0] 8013b2a: 6862 ldr r2, [r4, #4] 8013b2c: 4630 mov r0, r6 8013b2e: f000 f995 bl 8013e5c 8013b32: b108 cbz r0, 8013b38 <_printf_i+0x1e4> 8013b34: 1b80 subs r0, r0, r6 8013b36: 6060 str r0, [r4, #4] 8013b38: 6863 ldr r3, [r4, #4] 8013b3a: 6123 str r3, [r4, #16] 8013b3c: 2300 movs r3, #0 8013b3e: f884 3043 strb.w r3, [r4, #67] @ 0x43 8013b42: e7aa b.n 8013a9a <_printf_i+0x146> 8013b44: 4632 mov r2, r6 8013b46: 4649 mov r1, r9 8013b48: 4640 mov r0, r8 8013b4a: 6923 ldr r3, [r4, #16] 8013b4c: 47d0 blx sl 8013b4e: 3001 adds r0, #1 8013b50: d0ad beq.n 8013aae <_printf_i+0x15a> 8013b52: 6823 ldr r3, [r4, #0] 8013b54: 079b lsls r3, r3, #30 8013b56: d413 bmi.n 8013b80 <_printf_i+0x22c> 8013b58: 68e0 ldr r0, [r4, #12] 8013b5a: 9b03 ldr r3, [sp, #12] 8013b5c: 4298 cmp r0, r3 8013b5e: bfb8 it lt 8013b60: 4618 movlt r0, r3 8013b62: e7a6 b.n 8013ab2 <_printf_i+0x15e> 8013b64: 2301 movs r3, #1 8013b66: 4632 mov r2, r6 8013b68: 4649 mov r1, r9 8013b6a: 4640 mov r0, r8 8013b6c: 47d0 blx sl 8013b6e: 3001 adds r0, #1 8013b70: d09d beq.n 8013aae <_printf_i+0x15a> 8013b72: 3501 adds r5, #1 8013b74: 68e3 ldr r3, [r4, #12] 8013b76: 9903 ldr r1, [sp, #12] 8013b78: 1a5b subs r3, r3, r1 8013b7a: 42ab cmp r3, r5 8013b7c: dcf2 bgt.n 8013b64 <_printf_i+0x210> 8013b7e: e7eb b.n 8013b58 <_printf_i+0x204> 8013b80: 2500 movs r5, #0 8013b82: f104 0619 add.w r6, r4, #25 8013b86: e7f5 b.n 8013b74 <_printf_i+0x220> 8013b88: 0801448d .word 0x0801448d 8013b8c: 0801449e .word 0x0801449e 08013b90 <__sflush_r>: 8013b90: f9b1 200c ldrsh.w r2, [r1, #12] 8013b94: b5f8 push {r3, r4, r5, r6, r7, lr} 8013b96: 0716 lsls r6, r2, #28 8013b98: 4605 mov r5, r0 8013b9a: 460c mov r4, r1 8013b9c: d454 bmi.n 8013c48 <__sflush_r+0xb8> 8013b9e: 684b ldr r3, [r1, #4] 8013ba0: 2b00 cmp r3, #0 8013ba2: dc02 bgt.n 8013baa <__sflush_r+0x1a> 8013ba4: 6c0b ldr r3, [r1, #64] @ 0x40 8013ba6: 2b00 cmp r3, #0 8013ba8: dd48 ble.n 8013c3c <__sflush_r+0xac> 8013baa: 6ae6 ldr r6, [r4, #44] @ 0x2c 8013bac: 2e00 cmp r6, #0 8013bae: d045 beq.n 8013c3c <__sflush_r+0xac> 8013bb0: 2300 movs r3, #0 8013bb2: f412 5280 ands.w r2, r2, #4096 @ 0x1000 8013bb6: 682f ldr r7, [r5, #0] 8013bb8: 6a21 ldr r1, [r4, #32] 8013bba: 602b str r3, [r5, #0] 8013bbc: d030 beq.n 8013c20 <__sflush_r+0x90> 8013bbe: 6d62 ldr r2, [r4, #84] @ 0x54 8013bc0: 89a3 ldrh r3, [r4, #12] 8013bc2: 0759 lsls r1, r3, #29 8013bc4: d505 bpl.n 8013bd2 <__sflush_r+0x42> 8013bc6: 6863 ldr r3, [r4, #4] 8013bc8: 1ad2 subs r2, r2, r3 8013bca: 6b63 ldr r3, [r4, #52] @ 0x34 8013bcc: b10b cbz r3, 8013bd2 <__sflush_r+0x42> 8013bce: 6c23 ldr r3, [r4, #64] @ 0x40 8013bd0: 1ad2 subs r2, r2, r3 8013bd2: 2300 movs r3, #0 8013bd4: 4628 mov r0, r5 8013bd6: 6ae6 ldr r6, [r4, #44] @ 0x2c 8013bd8: 6a21 ldr r1, [r4, #32] 8013bda: 47b0 blx r6 8013bdc: 1c43 adds r3, r0, #1 8013bde: 89a3 ldrh r3, [r4, #12] 8013be0: d106 bne.n 8013bf0 <__sflush_r+0x60> 8013be2: 6829 ldr r1, [r5, #0] 8013be4: 291d cmp r1, #29 8013be6: d82b bhi.n 8013c40 <__sflush_r+0xb0> 8013be8: 4a28 ldr r2, [pc, #160] @ (8013c8c <__sflush_r+0xfc>) 8013bea: 40ca lsrs r2, r1 8013bec: 07d6 lsls r6, r2, #31 8013bee: d527 bpl.n 8013c40 <__sflush_r+0xb0> 8013bf0: 2200 movs r2, #0 8013bf2: 6062 str r2, [r4, #4] 8013bf4: 6922 ldr r2, [r4, #16] 8013bf6: 04d9 lsls r1, r3, #19 8013bf8: 6022 str r2, [r4, #0] 8013bfa: d504 bpl.n 8013c06 <__sflush_r+0x76> 8013bfc: 1c42 adds r2, r0, #1 8013bfe: d101 bne.n 8013c04 <__sflush_r+0x74> 8013c00: 682b ldr r3, [r5, #0] 8013c02: b903 cbnz r3, 8013c06 <__sflush_r+0x76> 8013c04: 6560 str r0, [r4, #84] @ 0x54 8013c06: 6b61 ldr r1, [r4, #52] @ 0x34 8013c08: 602f str r7, [r5, #0] 8013c0a: b1b9 cbz r1, 8013c3c <__sflush_r+0xac> 8013c0c: f104 0344 add.w r3, r4, #68 @ 0x44 8013c10: 4299 cmp r1, r3 8013c12: d002 beq.n 8013c1a <__sflush_r+0x8a> 8013c14: 4628 mov r0, r5 8013c16: f7ff fa9d bl 8013154 <_free_r> 8013c1a: 2300 movs r3, #0 8013c1c: 6363 str r3, [r4, #52] @ 0x34 8013c1e: e00d b.n 8013c3c <__sflush_r+0xac> 8013c20: 2301 movs r3, #1 8013c22: 4628 mov r0, r5 8013c24: 47b0 blx r6 8013c26: 4602 mov r2, r0 8013c28: 1c50 adds r0, r2, #1 8013c2a: d1c9 bne.n 8013bc0 <__sflush_r+0x30> 8013c2c: 682b ldr r3, [r5, #0] 8013c2e: 2b00 cmp r3, #0 8013c30: d0c6 beq.n 8013bc0 <__sflush_r+0x30> 8013c32: 2b1d cmp r3, #29 8013c34: d001 beq.n 8013c3a <__sflush_r+0xaa> 8013c36: 2b16 cmp r3, #22 8013c38: d11d bne.n 8013c76 <__sflush_r+0xe6> 8013c3a: 602f str r7, [r5, #0] 8013c3c: 2000 movs r0, #0 8013c3e: e021 b.n 8013c84 <__sflush_r+0xf4> 8013c40: f043 0340 orr.w r3, r3, #64 @ 0x40 8013c44: b21b sxth r3, r3 8013c46: e01a b.n 8013c7e <__sflush_r+0xee> 8013c48: 690f ldr r7, [r1, #16] 8013c4a: 2f00 cmp r7, #0 8013c4c: d0f6 beq.n 8013c3c <__sflush_r+0xac> 8013c4e: 0793 lsls r3, r2, #30 8013c50: bf18 it ne 8013c52: 2300 movne r3, #0 8013c54: 680e ldr r6, [r1, #0] 8013c56: bf08 it eq 8013c58: 694b ldreq r3, [r1, #20] 8013c5a: 1bf6 subs r6, r6, r7 8013c5c: 600f str r7, [r1, #0] 8013c5e: 608b str r3, [r1, #8] 8013c60: 2e00 cmp r6, #0 8013c62: ddeb ble.n 8013c3c <__sflush_r+0xac> 8013c64: 4633 mov r3, r6 8013c66: 463a mov r2, r7 8013c68: 4628 mov r0, r5 8013c6a: 6a21 ldr r1, [r4, #32] 8013c6c: f8d4 c028 ldr.w ip, [r4, #40] @ 0x28 8013c70: 47e0 blx ip 8013c72: 2800 cmp r0, #0 8013c74: dc07 bgt.n 8013c86 <__sflush_r+0xf6> 8013c76: f9b4 300c ldrsh.w r3, [r4, #12] 8013c7a: f043 0340 orr.w r3, r3, #64 @ 0x40 8013c7e: f04f 30ff mov.w r0, #4294967295 8013c82: 81a3 strh r3, [r4, #12] 8013c84: bdf8 pop {r3, r4, r5, r6, r7, pc} 8013c86: 4407 add r7, r0 8013c88: 1a36 subs r6, r6, r0 8013c8a: e7e9 b.n 8013c60 <__sflush_r+0xd0> 8013c8c: 20400001 .word 0x20400001 08013c90 <_fflush_r>: 8013c90: b538 push {r3, r4, r5, lr} 8013c92: 690b ldr r3, [r1, #16] 8013c94: 4605 mov r5, r0 8013c96: 460c mov r4, r1 8013c98: b913 cbnz r3, 8013ca0 <_fflush_r+0x10> 8013c9a: 2500 movs r5, #0 8013c9c: 4628 mov r0, r5 8013c9e: bd38 pop {r3, r4, r5, pc} 8013ca0: b118 cbz r0, 8013caa <_fflush_r+0x1a> 8013ca2: 6a03 ldr r3, [r0, #32] 8013ca4: b90b cbnz r3, 8013caa <_fflush_r+0x1a> 8013ca6: f7ff f903 bl 8012eb0 <__sinit> 8013caa: f9b4 300c ldrsh.w r3, [r4, #12] 8013cae: 2b00 cmp r3, #0 8013cb0: d0f3 beq.n 8013c9a <_fflush_r+0xa> 8013cb2: 6e62 ldr r2, [r4, #100] @ 0x64 8013cb4: 07d0 lsls r0, r2, #31 8013cb6: d404 bmi.n 8013cc2 <_fflush_r+0x32> 8013cb8: 0599 lsls r1, r3, #22 8013cba: d402 bmi.n 8013cc2 <_fflush_r+0x32> 8013cbc: 6da0 ldr r0, [r4, #88] @ 0x58 8013cbe: f7ff fa38 bl 8013132 <__retarget_lock_acquire_recursive> 8013cc2: 4628 mov r0, r5 8013cc4: 4621 mov r1, r4 8013cc6: f7ff ff63 bl 8013b90 <__sflush_r> 8013cca: 6e63 ldr r3, [r4, #100] @ 0x64 8013ccc: 4605 mov r5, r0 8013cce: 07da lsls r2, r3, #31 8013cd0: d4e4 bmi.n 8013c9c <_fflush_r+0xc> 8013cd2: 89a3 ldrh r3, [r4, #12] 8013cd4: 059b lsls r3, r3, #22 8013cd6: d4e1 bmi.n 8013c9c <_fflush_r+0xc> 8013cd8: 6da0 ldr r0, [r4, #88] @ 0x58 8013cda: f7ff fa2b bl 8013134 <__retarget_lock_release_recursive> 8013cde: e7dd b.n 8013c9c <_fflush_r+0xc> 08013ce0 <__swbuf_r>: 8013ce0: b5f8 push {r3, r4, r5, r6, r7, lr} 8013ce2: 460e mov r6, r1 8013ce4: 4614 mov r4, r2 8013ce6: 4605 mov r5, r0 8013ce8: b118 cbz r0, 8013cf2 <__swbuf_r+0x12> 8013cea: 6a03 ldr r3, [r0, #32] 8013cec: b90b cbnz r3, 8013cf2 <__swbuf_r+0x12> 8013cee: f7ff f8df bl 8012eb0 <__sinit> 8013cf2: 69a3 ldr r3, [r4, #24] 8013cf4: 60a3 str r3, [r4, #8] 8013cf6: 89a3 ldrh r3, [r4, #12] 8013cf8: 071a lsls r2, r3, #28 8013cfa: d501 bpl.n 8013d00 <__swbuf_r+0x20> 8013cfc: 6923 ldr r3, [r4, #16] 8013cfe: b943 cbnz r3, 8013d12 <__swbuf_r+0x32> 8013d00: 4621 mov r1, r4 8013d02: 4628 mov r0, r5 8013d04: f000 f82a bl 8013d5c <__swsetup_r> 8013d08: b118 cbz r0, 8013d12 <__swbuf_r+0x32> 8013d0a: f04f 37ff mov.w r7, #4294967295 8013d0e: 4638 mov r0, r7 8013d10: bdf8 pop {r3, r4, r5, r6, r7, pc} 8013d12: 6823 ldr r3, [r4, #0] 8013d14: 6922 ldr r2, [r4, #16] 8013d16: b2f6 uxtb r6, r6 8013d18: 1a98 subs r0, r3, r2 8013d1a: 6963 ldr r3, [r4, #20] 8013d1c: 4637 mov r7, r6 8013d1e: 4283 cmp r3, r0 8013d20: dc05 bgt.n 8013d2e <__swbuf_r+0x4e> 8013d22: 4621 mov r1, r4 8013d24: 4628 mov r0, r5 8013d26: f7ff ffb3 bl 8013c90 <_fflush_r> 8013d2a: 2800 cmp r0, #0 8013d2c: d1ed bne.n 8013d0a <__swbuf_r+0x2a> 8013d2e: 68a3 ldr r3, [r4, #8] 8013d30: 3b01 subs r3, #1 8013d32: 60a3 str r3, [r4, #8] 8013d34: 6823 ldr r3, [r4, #0] 8013d36: 1c5a adds r2, r3, #1 8013d38: 6022 str r2, [r4, #0] 8013d3a: 701e strb r6, [r3, #0] 8013d3c: 6962 ldr r2, [r4, #20] 8013d3e: 1c43 adds r3, r0, #1 8013d40: 429a cmp r2, r3 8013d42: d004 beq.n 8013d4e <__swbuf_r+0x6e> 8013d44: 89a3 ldrh r3, [r4, #12] 8013d46: 07db lsls r3, r3, #31 8013d48: d5e1 bpl.n 8013d0e <__swbuf_r+0x2e> 8013d4a: 2e0a cmp r6, #10 8013d4c: d1df bne.n 8013d0e <__swbuf_r+0x2e> 8013d4e: 4621 mov r1, r4 8013d50: 4628 mov r0, r5 8013d52: f7ff ff9d bl 8013c90 <_fflush_r> 8013d56: 2800 cmp r0, #0 8013d58: d0d9 beq.n 8013d0e <__swbuf_r+0x2e> 8013d5a: e7d6 b.n 8013d0a <__swbuf_r+0x2a> 08013d5c <__swsetup_r>: 8013d5c: b538 push {r3, r4, r5, lr} 8013d5e: 4b29 ldr r3, [pc, #164] @ (8013e04 <__swsetup_r+0xa8>) 8013d60: 4605 mov r5, r0 8013d62: 6818 ldr r0, [r3, #0] 8013d64: 460c mov r4, r1 8013d66: b118 cbz r0, 8013d70 <__swsetup_r+0x14> 8013d68: 6a03 ldr r3, [r0, #32] 8013d6a: b90b cbnz r3, 8013d70 <__swsetup_r+0x14> 8013d6c: f7ff f8a0 bl 8012eb0 <__sinit> 8013d70: f9b4 300c ldrsh.w r3, [r4, #12] 8013d74: 0719 lsls r1, r3, #28 8013d76: d422 bmi.n 8013dbe <__swsetup_r+0x62> 8013d78: 06da lsls r2, r3, #27 8013d7a: d407 bmi.n 8013d8c <__swsetup_r+0x30> 8013d7c: 2209 movs r2, #9 8013d7e: 602a str r2, [r5, #0] 8013d80: f043 0340 orr.w r3, r3, #64 @ 0x40 8013d84: f04f 30ff mov.w r0, #4294967295 8013d88: 81a3 strh r3, [r4, #12] 8013d8a: e033 b.n 8013df4 <__swsetup_r+0x98> 8013d8c: 0758 lsls r0, r3, #29 8013d8e: d512 bpl.n 8013db6 <__swsetup_r+0x5a> 8013d90: 6b61 ldr r1, [r4, #52] @ 0x34 8013d92: b141 cbz r1, 8013da6 <__swsetup_r+0x4a> 8013d94: f104 0344 add.w r3, r4, #68 @ 0x44 8013d98: 4299 cmp r1, r3 8013d9a: d002 beq.n 8013da2 <__swsetup_r+0x46> 8013d9c: 4628 mov r0, r5 8013d9e: f7ff f9d9 bl 8013154 <_free_r> 8013da2: 2300 movs r3, #0 8013da4: 6363 str r3, [r4, #52] @ 0x34 8013da6: 89a3 ldrh r3, [r4, #12] 8013da8: f023 0324 bic.w r3, r3, #36 @ 0x24 8013dac: 81a3 strh r3, [r4, #12] 8013dae: 2300 movs r3, #0 8013db0: 6063 str r3, [r4, #4] 8013db2: 6923 ldr r3, [r4, #16] 8013db4: 6023 str r3, [r4, #0] 8013db6: 89a3 ldrh r3, [r4, #12] 8013db8: f043 0308 orr.w r3, r3, #8 8013dbc: 81a3 strh r3, [r4, #12] 8013dbe: 6923 ldr r3, [r4, #16] 8013dc0: b94b cbnz r3, 8013dd6 <__swsetup_r+0x7a> 8013dc2: 89a3 ldrh r3, [r4, #12] 8013dc4: f403 7320 and.w r3, r3, #640 @ 0x280 8013dc8: f5b3 7f00 cmp.w r3, #512 @ 0x200 8013dcc: d003 beq.n 8013dd6 <__swsetup_r+0x7a> 8013dce: 4621 mov r1, r4 8013dd0: 4628 mov r0, r5 8013dd2: f000 f8a4 bl 8013f1e <__smakebuf_r> 8013dd6: f9b4 300c ldrsh.w r3, [r4, #12] 8013dda: f013 0201 ands.w r2, r3, #1 8013dde: d00a beq.n 8013df6 <__swsetup_r+0x9a> 8013de0: 2200 movs r2, #0 8013de2: 60a2 str r2, [r4, #8] 8013de4: 6962 ldr r2, [r4, #20] 8013de6: 4252 negs r2, r2 8013de8: 61a2 str r2, [r4, #24] 8013dea: 6922 ldr r2, [r4, #16] 8013dec: b942 cbnz r2, 8013e00 <__swsetup_r+0xa4> 8013dee: f013 0080 ands.w r0, r3, #128 @ 0x80 8013df2: d1c5 bne.n 8013d80 <__swsetup_r+0x24> 8013df4: bd38 pop {r3, r4, r5, pc} 8013df6: 0799 lsls r1, r3, #30 8013df8: bf58 it pl 8013dfa: 6962 ldrpl r2, [r4, #20] 8013dfc: 60a2 str r2, [r4, #8] 8013dfe: e7f4 b.n 8013dea <__swsetup_r+0x8e> 8013e00: 2000 movs r0, #0 8013e02: e7f7 b.n 8013df4 <__swsetup_r+0x98> 8013e04: 20000084 .word 0x20000084 08013e08 : 8013e08: 4288 cmp r0, r1 8013e0a: b510 push {r4, lr} 8013e0c: eb01 0402 add.w r4, r1, r2 8013e10: d902 bls.n 8013e18 8013e12: 4284 cmp r4, r0 8013e14: 4623 mov r3, r4 8013e16: d807 bhi.n 8013e28 8013e18: 1e43 subs r3, r0, #1 8013e1a: 42a1 cmp r1, r4 8013e1c: d008 beq.n 8013e30 8013e1e: f811 2b01 ldrb.w r2, [r1], #1 8013e22: f803 2f01 strb.w r2, [r3, #1]! 8013e26: e7f8 b.n 8013e1a 8013e28: 4601 mov r1, r0 8013e2a: 4402 add r2, r0 8013e2c: 428a cmp r2, r1 8013e2e: d100 bne.n 8013e32 8013e30: bd10 pop {r4, pc} 8013e32: f813 4d01 ldrb.w r4, [r3, #-1]! 8013e36: f802 4d01 strb.w r4, [r2, #-1]! 8013e3a: e7f7 b.n 8013e2c 08013e3c <_sbrk_r>: 8013e3c: b538 push {r3, r4, r5, lr} 8013e3e: 2300 movs r3, #0 8013e40: 4d05 ldr r5, [pc, #20] @ (8013e58 <_sbrk_r+0x1c>) 8013e42: 4604 mov r4, r0 8013e44: 4608 mov r0, r1 8013e46: 602b str r3, [r5, #0] 8013e48: f7f9 f93a bl 800d0c0 <_sbrk> 8013e4c: 1c43 adds r3, r0, #1 8013e4e: d102 bne.n 8013e56 <_sbrk_r+0x1a> 8013e50: 682b ldr r3, [r5, #0] 8013e52: b103 cbz r3, 8013e56 <_sbrk_r+0x1a> 8013e54: 6023 str r3, [r4, #0] 8013e56: bd38 pop {r3, r4, r5, pc} 8013e58: 200011b8 .word 0x200011b8 08013e5c : 8013e5c: 4603 mov r3, r0 8013e5e: b510 push {r4, lr} 8013e60: b2c9 uxtb r1, r1 8013e62: 4402 add r2, r0 8013e64: 4293 cmp r3, r2 8013e66: 4618 mov r0, r3 8013e68: d101 bne.n 8013e6e 8013e6a: 2000 movs r0, #0 8013e6c: e003 b.n 8013e76 8013e6e: 7804 ldrb r4, [r0, #0] 8013e70: 3301 adds r3, #1 8013e72: 428c cmp r4, r1 8013e74: d1f6 bne.n 8013e64 8013e76: bd10 pop {r4, pc} 08013e78 <_realloc_r>: 8013e78: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8013e7c: 4607 mov r7, r0 8013e7e: 4614 mov r4, r2 8013e80: 460d mov r5, r1 8013e82: b921 cbnz r1, 8013e8e <_realloc_r+0x16> 8013e84: 4611 mov r1, r2 8013e86: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8013e8a: f7ff b9cd b.w 8013228 <_malloc_r> 8013e8e: b92a cbnz r2, 8013e9c <_realloc_r+0x24> 8013e90: f7ff f960 bl 8013154 <_free_r> 8013e94: 4625 mov r5, r4 8013e96: 4628 mov r0, r5 8013e98: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8013e9c: f000 f89e bl 8013fdc <_malloc_usable_size_r> 8013ea0: 4284 cmp r4, r0 8013ea2: 4606 mov r6, r0 8013ea4: d802 bhi.n 8013eac <_realloc_r+0x34> 8013ea6: ebb4 0f50 cmp.w r4, r0, lsr #1 8013eaa: d8f4 bhi.n 8013e96 <_realloc_r+0x1e> 8013eac: 4621 mov r1, r4 8013eae: 4638 mov r0, r7 8013eb0: f7ff f9ba bl 8013228 <_malloc_r> 8013eb4: 4680 mov r8, r0 8013eb6: b908 cbnz r0, 8013ebc <_realloc_r+0x44> 8013eb8: 4645 mov r5, r8 8013eba: e7ec b.n 8013e96 <_realloc_r+0x1e> 8013ebc: 42b4 cmp r4, r6 8013ebe: 4622 mov r2, r4 8013ec0: 4629 mov r1, r5 8013ec2: bf28 it cs 8013ec4: 4632 movcs r2, r6 8013ec6: f7ff f936 bl 8013136 8013eca: 4629 mov r1, r5 8013ecc: 4638 mov r0, r7 8013ece: f7ff f941 bl 8013154 <_free_r> 8013ed2: e7f1 b.n 8013eb8 <_realloc_r+0x40> 08013ed4 <__swhatbuf_r>: 8013ed4: b570 push {r4, r5, r6, lr} 8013ed6: 460c mov r4, r1 8013ed8: f9b1 100e ldrsh.w r1, [r1, #14] 8013edc: 4615 mov r5, r2 8013ede: 2900 cmp r1, #0 8013ee0: 461e mov r6, r3 8013ee2: b096 sub sp, #88 @ 0x58 8013ee4: da0c bge.n 8013f00 <__swhatbuf_r+0x2c> 8013ee6: 89a3 ldrh r3, [r4, #12] 8013ee8: 2100 movs r1, #0 8013eea: f013 0f80 tst.w r3, #128 @ 0x80 8013eee: bf14 ite ne 8013ef0: 2340 movne r3, #64 @ 0x40 8013ef2: f44f 6380 moveq.w r3, #1024 @ 0x400 8013ef6: 2000 movs r0, #0 8013ef8: 6031 str r1, [r6, #0] 8013efa: 602b str r3, [r5, #0] 8013efc: b016 add sp, #88 @ 0x58 8013efe: bd70 pop {r4, r5, r6, pc} 8013f00: 466a mov r2, sp 8013f02: f000 f849 bl 8013f98 <_fstat_r> 8013f06: 2800 cmp r0, #0 8013f08: dbed blt.n 8013ee6 <__swhatbuf_r+0x12> 8013f0a: 9901 ldr r1, [sp, #4] 8013f0c: f401 4170 and.w r1, r1, #61440 @ 0xf000 8013f10: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 8013f14: 4259 negs r1, r3 8013f16: 4159 adcs r1, r3 8013f18: f44f 6380 mov.w r3, #1024 @ 0x400 8013f1c: e7eb b.n 8013ef6 <__swhatbuf_r+0x22> 08013f1e <__smakebuf_r>: 8013f1e: 898b ldrh r3, [r1, #12] 8013f20: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8013f22: 079d lsls r5, r3, #30 8013f24: 4606 mov r6, r0 8013f26: 460c mov r4, r1 8013f28: d507 bpl.n 8013f3a <__smakebuf_r+0x1c> 8013f2a: f104 0347 add.w r3, r4, #71 @ 0x47 8013f2e: 6023 str r3, [r4, #0] 8013f30: 6123 str r3, [r4, #16] 8013f32: 2301 movs r3, #1 8013f34: 6163 str r3, [r4, #20] 8013f36: b003 add sp, #12 8013f38: bdf0 pop {r4, r5, r6, r7, pc} 8013f3a: 466a mov r2, sp 8013f3c: ab01 add r3, sp, #4 8013f3e: f7ff ffc9 bl 8013ed4 <__swhatbuf_r> 8013f42: 9f00 ldr r7, [sp, #0] 8013f44: 4605 mov r5, r0 8013f46: 4639 mov r1, r7 8013f48: 4630 mov r0, r6 8013f4a: f7ff f96d bl 8013228 <_malloc_r> 8013f4e: b948 cbnz r0, 8013f64 <__smakebuf_r+0x46> 8013f50: f9b4 300c ldrsh.w r3, [r4, #12] 8013f54: 059a lsls r2, r3, #22 8013f56: d4ee bmi.n 8013f36 <__smakebuf_r+0x18> 8013f58: f023 0303 bic.w r3, r3, #3 8013f5c: f043 0302 orr.w r3, r3, #2 8013f60: 81a3 strh r3, [r4, #12] 8013f62: e7e2 b.n 8013f2a <__smakebuf_r+0xc> 8013f64: 89a3 ldrh r3, [r4, #12] 8013f66: e9c4 0704 strd r0, r7, [r4, #16] 8013f6a: f043 0380 orr.w r3, r3, #128 @ 0x80 8013f6e: 81a3 strh r3, [r4, #12] 8013f70: 9b01 ldr r3, [sp, #4] 8013f72: 6020 str r0, [r4, #0] 8013f74: b15b cbz r3, 8013f8e <__smakebuf_r+0x70> 8013f76: 4630 mov r0, r6 8013f78: f9b4 100e ldrsh.w r1, [r4, #14] 8013f7c: f000 f81e bl 8013fbc <_isatty_r> 8013f80: b128 cbz r0, 8013f8e <__smakebuf_r+0x70> 8013f82: 89a3 ldrh r3, [r4, #12] 8013f84: f023 0303 bic.w r3, r3, #3 8013f88: f043 0301 orr.w r3, r3, #1 8013f8c: 81a3 strh r3, [r4, #12] 8013f8e: 89a3 ldrh r3, [r4, #12] 8013f90: 431d orrs r5, r3 8013f92: 81a5 strh r5, [r4, #12] 8013f94: e7cf b.n 8013f36 <__smakebuf_r+0x18> ... 08013f98 <_fstat_r>: 8013f98: b538 push {r3, r4, r5, lr} 8013f9a: 2300 movs r3, #0 8013f9c: 4d06 ldr r5, [pc, #24] @ (8013fb8 <_fstat_r+0x20>) 8013f9e: 4604 mov r4, r0 8013fa0: 4608 mov r0, r1 8013fa2: 4611 mov r1, r2 8013fa4: 602b str r3, [r5, #0] 8013fa6: f7f9 f865 bl 800d074 <_fstat> 8013faa: 1c43 adds r3, r0, #1 8013fac: d102 bne.n 8013fb4 <_fstat_r+0x1c> 8013fae: 682b ldr r3, [r5, #0] 8013fb0: b103 cbz r3, 8013fb4 <_fstat_r+0x1c> 8013fb2: 6023 str r3, [r4, #0] 8013fb4: bd38 pop {r3, r4, r5, pc} 8013fb6: bf00 nop 8013fb8: 200011b8 .word 0x200011b8 08013fbc <_isatty_r>: 8013fbc: b538 push {r3, r4, r5, lr} 8013fbe: 2300 movs r3, #0 8013fc0: 4d05 ldr r5, [pc, #20] @ (8013fd8 <_isatty_r+0x1c>) 8013fc2: 4604 mov r4, r0 8013fc4: 4608 mov r0, r1 8013fc6: 602b str r3, [r5, #0] 8013fc8: f7f9 f863 bl 800d092 <_isatty> 8013fcc: 1c43 adds r3, r0, #1 8013fce: d102 bne.n 8013fd6 <_isatty_r+0x1a> 8013fd0: 682b ldr r3, [r5, #0] 8013fd2: b103 cbz r3, 8013fd6 <_isatty_r+0x1a> 8013fd4: 6023 str r3, [r4, #0] 8013fd6: bd38 pop {r3, r4, r5, pc} 8013fd8: 200011b8 .word 0x200011b8 08013fdc <_malloc_usable_size_r>: 8013fdc: f851 3c04 ldr.w r3, [r1, #-4] 8013fe0: 1f18 subs r0, r3, #4 8013fe2: 2b00 cmp r3, #0 8013fe4: bfbc itt lt 8013fe6: 580b ldrlt r3, [r1, r0] 8013fe8: 18c0 addlt r0, r0, r3 8013fea: 4770 bx lr 08013fec <_init>: 8013fec: b5f8 push {r3, r4, r5, r6, r7, lr} 8013fee: bf00 nop 8013ff0: bcf8 pop {r3, r4, r5, r6, r7} 8013ff2: bc08 pop {r3} 8013ff4: 469e mov lr, r3 8013ff6: 4770 bx lr 08013ff8 <_fini>: 8013ff8: b5f8 push {r3, r4, r5, r6, r7, lr} 8013ffa: bf00 nop 8013ffc: bcf8 pop {r3, r4, r5, r6, r7} 8013ffe: bc08 pop {r3} 8014000: 469e mov lr, r3 8014002: 4770 bx lr