CCSModuleSW30Web.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001e8 08008000 08008000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000f164 080081e8 080081e8 000011e8 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000de4 08017350 08017350 00010350 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08018134 08018134 00012258 2**0 CONTENTS 4 .ARM 00000008 08018134 08018134 00011134 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 0801813c 0801813c 00012258 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0801813c 0801813c 0001113c 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08018140 08018140 00011140 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000258 20000000 08018144 00012000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00001394 20000258 0801839c 00012258 2**3 ALLOC 10 ._user_heap_stack 00000604 200015ec 0801839c 000125ec 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 00012258 2**0 CONTENTS, READONLY 12 .debug_info 0001da83 00000000 00000000 00012281 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00005996 00000000 00000000 0002fd04 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_loclists 00000ff8 00000000 00000000 0003569a 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_aranges 00001798 00000000 00000000 00036698 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_rnglists 00001273 00000000 00000000 00037e30 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_macro 0002676b 00000000 00000000 000390a3 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_line 00021cc5 00000000 00000000 0005f80e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_str 000c9c93 00000000 00000000 000814d3 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .comment 00000043 00000000 00000000 0014b166 2**0 CONTENTS, READONLY 21 .debug_frame 00006ef8 00000000 00000000 0014b1ac 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 22 .debug_line_str 0000006e 00000000 00000000 001520a4 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080081e8 <__do_global_dtors_aux>: 80081e8: b510 push {r4, lr} 80081ea: 4c05 ldr r4, [pc, #20] @ (8008200 <__do_global_dtors_aux+0x18>) 80081ec: 7823 ldrb r3, [r4, #0] 80081ee: b933 cbnz r3, 80081fe <__do_global_dtors_aux+0x16> 80081f0: 4b04 ldr r3, [pc, #16] @ (8008204 <__do_global_dtors_aux+0x1c>) 80081f2: b113 cbz r3, 80081fa <__do_global_dtors_aux+0x12> 80081f4: 4804 ldr r0, [pc, #16] @ (8008208 <__do_global_dtors_aux+0x20>) 80081f6: f3af 8000 nop.w 80081fa: 2301 movs r3, #1 80081fc: 7023 strb r3, [r4, #0] 80081fe: bd10 pop {r4, pc} 8008200: 20000258 .word 0x20000258 8008204: 00000000 .word 0x00000000 8008208: 08017334 .word 0x08017334 0800820c : 800820c: b508 push {r3, lr} 800820e: 4b03 ldr r3, [pc, #12] @ (800821c ) 8008210: b11b cbz r3, 800821a 8008212: 4903 ldr r1, [pc, #12] @ (8008220 ) 8008214: 4803 ldr r0, [pc, #12] @ (8008224 ) 8008216: f3af 8000 nop.w 800821a: bd08 pop {r3, pc} 800821c: 00000000 .word 0x00000000 8008220: 2000025c .word 0x2000025c 8008224: 08017334 .word 0x08017334 08008228 : 8008228: 4603 mov r3, r0 800822a: f813 2b01 ldrb.w r2, [r3], #1 800822e: 2a00 cmp r2, #0 8008230: d1fb bne.n 800822a 8008232: 1a18 subs r0, r3, r0 8008234: 3801 subs r0, #1 8008236: 4770 bx lr 08008238 <__aeabi_drsub>: 8008238: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 800823c: e002 b.n 8008244 <__adddf3> 800823e: bf00 nop 08008240 <__aeabi_dsub>: 8008240: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 08008244 <__adddf3>: 8008244: b530 push {r4, r5, lr} 8008246: ea4f 0441 mov.w r4, r1, lsl #1 800824a: ea4f 0543 mov.w r5, r3, lsl #1 800824e: ea94 0f05 teq r4, r5 8008252: bf08 it eq 8008254: ea90 0f02 teqeq r0, r2 8008258: bf1f itttt ne 800825a: ea54 0c00 orrsne.w ip, r4, r0 800825e: ea55 0c02 orrsne.w ip, r5, r2 8008262: ea7f 5c64 mvnsne.w ip, r4, asr #21 8008266: ea7f 5c65 mvnsne.w ip, r5, asr #21 800826a: f000 80e2 beq.w 8008432 <__adddf3+0x1ee> 800826e: ea4f 5454 mov.w r4, r4, lsr #21 8008272: ebd4 5555 rsbs r5, r4, r5, lsr #21 8008276: bfb8 it lt 8008278: 426d neglt r5, r5 800827a: dd0c ble.n 8008296 <__adddf3+0x52> 800827c: 442c add r4, r5 800827e: ea80 0202 eor.w r2, r0, r2 8008282: ea81 0303 eor.w r3, r1, r3 8008286: ea82 0000 eor.w r0, r2, r0 800828a: ea83 0101 eor.w r1, r3, r1 800828e: ea80 0202 eor.w r2, r0, r2 8008292: ea81 0303 eor.w r3, r1, r3 8008296: 2d36 cmp r5, #54 @ 0x36 8008298: bf88 it hi 800829a: bd30 pophi {r4, r5, pc} 800829c: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 80082a0: ea4f 3101 mov.w r1, r1, lsl #12 80082a4: f44f 1c80 mov.w ip, #1048576 @ 0x100000 80082a8: ea4c 3111 orr.w r1, ip, r1, lsr #12 80082ac: d002 beq.n 80082b4 <__adddf3+0x70> 80082ae: 4240 negs r0, r0 80082b0: eb61 0141 sbc.w r1, r1, r1, lsl #1 80082b4: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 80082b8: ea4f 3303 mov.w r3, r3, lsl #12 80082bc: ea4c 3313 orr.w r3, ip, r3, lsr #12 80082c0: d002 beq.n 80082c8 <__adddf3+0x84> 80082c2: 4252 negs r2, r2 80082c4: eb63 0343 sbc.w r3, r3, r3, lsl #1 80082c8: ea94 0f05 teq r4, r5 80082cc: f000 80a7 beq.w 800841e <__adddf3+0x1da> 80082d0: f1a4 0401 sub.w r4, r4, #1 80082d4: f1d5 0e20 rsbs lr, r5, #32 80082d8: db0d blt.n 80082f6 <__adddf3+0xb2> 80082da: fa02 fc0e lsl.w ip, r2, lr 80082de: fa22 f205 lsr.w r2, r2, r5 80082e2: 1880 adds r0, r0, r2 80082e4: f141 0100 adc.w r1, r1, #0 80082e8: fa03 f20e lsl.w r2, r3, lr 80082ec: 1880 adds r0, r0, r2 80082ee: fa43 f305 asr.w r3, r3, r5 80082f2: 4159 adcs r1, r3 80082f4: e00e b.n 8008314 <__adddf3+0xd0> 80082f6: f1a5 0520 sub.w r5, r5, #32 80082fa: f10e 0e20 add.w lr, lr, #32 80082fe: 2a01 cmp r2, #1 8008300: fa03 fc0e lsl.w ip, r3, lr 8008304: bf28 it cs 8008306: f04c 0c02 orrcs.w ip, ip, #2 800830a: fa43 f305 asr.w r3, r3, r5 800830e: 18c0 adds r0, r0, r3 8008310: eb51 71e3 adcs.w r1, r1, r3, asr #31 8008314: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008318: d507 bpl.n 800832a <__adddf3+0xe6> 800831a: f04f 0e00 mov.w lr, #0 800831e: f1dc 0c00 rsbs ip, ip, #0 8008322: eb7e 0000 sbcs.w r0, lr, r0 8008326: eb6e 0101 sbc.w r1, lr, r1 800832a: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 800832e: d31b bcc.n 8008368 <__adddf3+0x124> 8008330: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 8008334: d30c bcc.n 8008350 <__adddf3+0x10c> 8008336: 0849 lsrs r1, r1, #1 8008338: ea5f 0030 movs.w r0, r0, rrx 800833c: ea4f 0c3c mov.w ip, ip, rrx 8008340: f104 0401 add.w r4, r4, #1 8008344: ea4f 5244 mov.w r2, r4, lsl #21 8008348: f512 0f80 cmn.w r2, #4194304 @ 0x400000 800834c: f080 809a bcs.w 8008484 <__adddf3+0x240> 8008350: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008354: bf08 it eq 8008356: ea5f 0c50 movseq.w ip, r0, lsr #1 800835a: f150 0000 adcs.w r0, r0, #0 800835e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008362: ea41 0105 orr.w r1, r1, r5 8008366: bd30 pop {r4, r5, pc} 8008368: ea5f 0c4c movs.w ip, ip, lsl #1 800836c: 4140 adcs r0, r0 800836e: eb41 0101 adc.w r1, r1, r1 8008372: 3c01 subs r4, #1 8008374: bf28 it cs 8008376: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 800837a: d2e9 bcs.n 8008350 <__adddf3+0x10c> 800837c: f091 0f00 teq r1, #0 8008380: bf04 itt eq 8008382: 4601 moveq r1, r0 8008384: 2000 moveq r0, #0 8008386: fab1 f381 clz r3, r1 800838a: bf08 it eq 800838c: 3320 addeq r3, #32 800838e: f1a3 030b sub.w r3, r3, #11 8008392: f1b3 0220 subs.w r2, r3, #32 8008396: da0c bge.n 80083b2 <__adddf3+0x16e> 8008398: 320c adds r2, #12 800839a: dd08 ble.n 80083ae <__adddf3+0x16a> 800839c: f102 0c14 add.w ip, r2, #20 80083a0: f1c2 020c rsb r2, r2, #12 80083a4: fa01 f00c lsl.w r0, r1, ip 80083a8: fa21 f102 lsr.w r1, r1, r2 80083ac: e00c b.n 80083c8 <__adddf3+0x184> 80083ae: f102 0214 add.w r2, r2, #20 80083b2: bfd8 it le 80083b4: f1c2 0c20 rsble ip, r2, #32 80083b8: fa01 f102 lsl.w r1, r1, r2 80083bc: fa20 fc0c lsr.w ip, r0, ip 80083c0: bfdc itt le 80083c2: ea41 010c orrle.w r1, r1, ip 80083c6: 4090 lslle r0, r2 80083c8: 1ae4 subs r4, r4, r3 80083ca: bfa2 ittt ge 80083cc: eb01 5104 addge.w r1, r1, r4, lsl #20 80083d0: 4329 orrge r1, r5 80083d2: bd30 popge {r4, r5, pc} 80083d4: ea6f 0404 mvn.w r4, r4 80083d8: 3c1f subs r4, #31 80083da: da1c bge.n 8008416 <__adddf3+0x1d2> 80083dc: 340c adds r4, #12 80083de: dc0e bgt.n 80083fe <__adddf3+0x1ba> 80083e0: f104 0414 add.w r4, r4, #20 80083e4: f1c4 0220 rsb r2, r4, #32 80083e8: fa20 f004 lsr.w r0, r0, r4 80083ec: fa01 f302 lsl.w r3, r1, r2 80083f0: ea40 0003 orr.w r0, r0, r3 80083f4: fa21 f304 lsr.w r3, r1, r4 80083f8: ea45 0103 orr.w r1, r5, r3 80083fc: bd30 pop {r4, r5, pc} 80083fe: f1c4 040c rsb r4, r4, #12 8008402: f1c4 0220 rsb r2, r4, #32 8008406: fa20 f002 lsr.w r0, r0, r2 800840a: fa01 f304 lsl.w r3, r1, r4 800840e: ea40 0003 orr.w r0, r0, r3 8008412: 4629 mov r1, r5 8008414: bd30 pop {r4, r5, pc} 8008416: fa21 f004 lsr.w r0, r1, r4 800841a: 4629 mov r1, r5 800841c: bd30 pop {r4, r5, pc} 800841e: f094 0f00 teq r4, #0 8008422: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 8008426: bf06 itte eq 8008428: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 800842c: 3401 addeq r4, #1 800842e: 3d01 subne r5, #1 8008430: e74e b.n 80082d0 <__adddf3+0x8c> 8008432: ea7f 5c64 mvns.w ip, r4, asr #21 8008436: bf18 it ne 8008438: ea7f 5c65 mvnsne.w ip, r5, asr #21 800843c: d029 beq.n 8008492 <__adddf3+0x24e> 800843e: ea94 0f05 teq r4, r5 8008442: bf08 it eq 8008444: ea90 0f02 teqeq r0, r2 8008448: d005 beq.n 8008456 <__adddf3+0x212> 800844a: ea54 0c00 orrs.w ip, r4, r0 800844e: bf04 itt eq 8008450: 4619 moveq r1, r3 8008452: 4610 moveq r0, r2 8008454: bd30 pop {r4, r5, pc} 8008456: ea91 0f03 teq r1, r3 800845a: bf1e ittt ne 800845c: 2100 movne r1, #0 800845e: 2000 movne r0, #0 8008460: bd30 popne {r4, r5, pc} 8008462: ea5f 5c54 movs.w ip, r4, lsr #21 8008466: d105 bne.n 8008474 <__adddf3+0x230> 8008468: 0040 lsls r0, r0, #1 800846a: 4149 adcs r1, r1 800846c: bf28 it cs 800846e: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 8008472: bd30 pop {r4, r5, pc} 8008474: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 8008478: bf3c itt cc 800847a: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 800847e: bd30 popcc {r4, r5, pc} 8008480: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008484: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 8008488: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 800848c: f04f 0000 mov.w r0, #0 8008490: bd30 pop {r4, r5, pc} 8008492: ea7f 5c64 mvns.w ip, r4, asr #21 8008496: bf1a itte ne 8008498: 4619 movne r1, r3 800849a: 4610 movne r0, r2 800849c: ea7f 5c65 mvnseq.w ip, r5, asr #21 80084a0: bf1c itt ne 80084a2: 460b movne r3, r1 80084a4: 4602 movne r2, r0 80084a6: ea50 3401 orrs.w r4, r0, r1, lsl #12 80084aa: bf06 itte eq 80084ac: ea52 3503 orrseq.w r5, r2, r3, lsl #12 80084b0: ea91 0f03 teqeq r1, r3 80084b4: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 80084b8: bd30 pop {r4, r5, pc} 80084ba: bf00 nop 080084bc <__aeabi_ui2d>: 80084bc: f090 0f00 teq r0, #0 80084c0: bf04 itt eq 80084c2: 2100 moveq r1, #0 80084c4: 4770 bxeq lr 80084c6: b530 push {r4, r5, lr} 80084c8: f44f 6480 mov.w r4, #1024 @ 0x400 80084cc: f104 0432 add.w r4, r4, #50 @ 0x32 80084d0: f04f 0500 mov.w r5, #0 80084d4: f04f 0100 mov.w r1, #0 80084d8: e750 b.n 800837c <__adddf3+0x138> 80084da: bf00 nop 080084dc <__aeabi_i2d>: 80084dc: f090 0f00 teq r0, #0 80084e0: bf04 itt eq 80084e2: 2100 moveq r1, #0 80084e4: 4770 bxeq lr 80084e6: b530 push {r4, r5, lr} 80084e8: f44f 6480 mov.w r4, #1024 @ 0x400 80084ec: f104 0432 add.w r4, r4, #50 @ 0x32 80084f0: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 80084f4: bf48 it mi 80084f6: 4240 negmi r0, r0 80084f8: f04f 0100 mov.w r1, #0 80084fc: e73e b.n 800837c <__adddf3+0x138> 80084fe: bf00 nop 08008500 <__aeabi_f2d>: 8008500: 0042 lsls r2, r0, #1 8008502: ea4f 01e2 mov.w r1, r2, asr #3 8008506: ea4f 0131 mov.w r1, r1, rrx 800850a: ea4f 7002 mov.w r0, r2, lsl #28 800850e: bf1f itttt ne 8008510: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 8008514: f093 4f7f teqne r3, #4278190080 @ 0xff000000 8008518: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 800851c: 4770 bxne lr 800851e: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 8008522: bf08 it eq 8008524: 4770 bxeq lr 8008526: f093 4f7f teq r3, #4278190080 @ 0xff000000 800852a: bf04 itt eq 800852c: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 8008530: 4770 bxeq lr 8008532: b530 push {r4, r5, lr} 8008534: f44f 7460 mov.w r4, #896 @ 0x380 8008538: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 800853c: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 8008540: e71c b.n 800837c <__adddf3+0x138> 8008542: bf00 nop 08008544 <__aeabi_ul2d>: 8008544: ea50 0201 orrs.w r2, r0, r1 8008548: bf08 it eq 800854a: 4770 bxeq lr 800854c: b530 push {r4, r5, lr} 800854e: f04f 0500 mov.w r5, #0 8008552: e00a b.n 800856a <__aeabi_l2d+0x16> 08008554 <__aeabi_l2d>: 8008554: ea50 0201 orrs.w r2, r0, r1 8008558: bf08 it eq 800855a: 4770 bxeq lr 800855c: b530 push {r4, r5, lr} 800855e: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 8008562: d502 bpl.n 800856a <__aeabi_l2d+0x16> 8008564: 4240 negs r0, r0 8008566: eb61 0141 sbc.w r1, r1, r1, lsl #1 800856a: f44f 6480 mov.w r4, #1024 @ 0x400 800856e: f104 0432 add.w r4, r4, #50 @ 0x32 8008572: ea5f 5c91 movs.w ip, r1, lsr #22 8008576: f43f aed8 beq.w 800832a <__adddf3+0xe6> 800857a: f04f 0203 mov.w r2, #3 800857e: ea5f 0cdc movs.w ip, ip, lsr #3 8008582: bf18 it ne 8008584: 3203 addne r2, #3 8008586: ea5f 0cdc movs.w ip, ip, lsr #3 800858a: bf18 it ne 800858c: 3203 addne r2, #3 800858e: eb02 02dc add.w r2, r2, ip, lsr #3 8008592: f1c2 0320 rsb r3, r2, #32 8008596: fa00 fc03 lsl.w ip, r0, r3 800859a: fa20 f002 lsr.w r0, r0, r2 800859e: fa01 fe03 lsl.w lr, r1, r3 80085a2: ea40 000e orr.w r0, r0, lr 80085a6: fa21 f102 lsr.w r1, r1, r2 80085aa: 4414 add r4, r2 80085ac: e6bd b.n 800832a <__adddf3+0xe6> 80085ae: bf00 nop 080085b0 <__aeabi_dmul>: 80085b0: b570 push {r4, r5, r6, lr} 80085b2: f04f 0cff mov.w ip, #255 @ 0xff 80085b6: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 80085ba: ea1c 5411 ands.w r4, ip, r1, lsr #20 80085be: bf1d ittte ne 80085c0: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80085c4: ea94 0f0c teqne r4, ip 80085c8: ea95 0f0c teqne r5, ip 80085cc: f000 f8de bleq 800878c <__aeabi_dmul+0x1dc> 80085d0: 442c add r4, r5 80085d2: ea81 0603 eor.w r6, r1, r3 80085d6: ea21 514c bic.w r1, r1, ip, lsl #21 80085da: ea23 534c bic.w r3, r3, ip, lsl #21 80085de: ea50 3501 orrs.w r5, r0, r1, lsl #12 80085e2: bf18 it ne 80085e4: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80085e8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 80085ec: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80085f0: d038 beq.n 8008664 <__aeabi_dmul+0xb4> 80085f2: fba0 ce02 umull ip, lr, r0, r2 80085f6: f04f 0500 mov.w r5, #0 80085fa: fbe1 e502 umlal lr, r5, r1, r2 80085fe: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 8008602: fbe0 e503 umlal lr, r5, r0, r3 8008606: f04f 0600 mov.w r6, #0 800860a: fbe1 5603 umlal r5, r6, r1, r3 800860e: f09c 0f00 teq ip, #0 8008612: bf18 it ne 8008614: f04e 0e01 orrne.w lr, lr, #1 8008618: f1a4 04ff sub.w r4, r4, #255 @ 0xff 800861c: f5b6 7f00 cmp.w r6, #512 @ 0x200 8008620: f564 7440 sbc.w r4, r4, #768 @ 0x300 8008624: d204 bcs.n 8008630 <__aeabi_dmul+0x80> 8008626: ea5f 0e4e movs.w lr, lr, lsl #1 800862a: 416d adcs r5, r5 800862c: eb46 0606 adc.w r6, r6, r6 8008630: ea42 21c6 orr.w r1, r2, r6, lsl #11 8008634: ea41 5155 orr.w r1, r1, r5, lsr #21 8008638: ea4f 20c5 mov.w r0, r5, lsl #11 800863c: ea40 505e orr.w r0, r0, lr, lsr #21 8008640: ea4f 2ece mov.w lr, lr, lsl #11 8008644: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008648: bf88 it hi 800864a: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800864e: d81e bhi.n 800868e <__aeabi_dmul+0xde> 8008650: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 8008654: bf08 it eq 8008656: ea5f 0e50 movseq.w lr, r0, lsr #1 800865a: f150 0000 adcs.w r0, r0, #0 800865e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008662: bd70 pop {r4, r5, r6, pc} 8008664: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 8008668: ea46 0101 orr.w r1, r6, r1 800866c: ea40 0002 orr.w r0, r0, r2 8008670: ea81 0103 eor.w r1, r1, r3 8008674: ebb4 045c subs.w r4, r4, ip, lsr #1 8008678: bfc2 ittt gt 800867a: ebd4 050c rsbsgt r5, r4, ip 800867e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8008682: bd70 popgt {r4, r5, r6, pc} 8008684: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008688: f04f 0e00 mov.w lr, #0 800868c: 3c01 subs r4, #1 800868e: f300 80ab bgt.w 80087e8 <__aeabi_dmul+0x238> 8008692: f114 0f36 cmn.w r4, #54 @ 0x36 8008696: bfde ittt le 8008698: 2000 movle r0, #0 800869a: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 800869e: bd70 pople {r4, r5, r6, pc} 80086a0: f1c4 0400 rsb r4, r4, #0 80086a4: 3c20 subs r4, #32 80086a6: da35 bge.n 8008714 <__aeabi_dmul+0x164> 80086a8: 340c adds r4, #12 80086aa: dc1b bgt.n 80086e4 <__aeabi_dmul+0x134> 80086ac: f104 0414 add.w r4, r4, #20 80086b0: f1c4 0520 rsb r5, r4, #32 80086b4: fa00 f305 lsl.w r3, r0, r5 80086b8: fa20 f004 lsr.w r0, r0, r4 80086bc: fa01 f205 lsl.w r2, r1, r5 80086c0: ea40 0002 orr.w r0, r0, r2 80086c4: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 80086c8: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 80086cc: eb10 70d3 adds.w r0, r0, r3, lsr #31 80086d0: fa21 f604 lsr.w r6, r1, r4 80086d4: eb42 0106 adc.w r1, r2, r6 80086d8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80086dc: bf08 it eq 80086de: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80086e2: bd70 pop {r4, r5, r6, pc} 80086e4: f1c4 040c rsb r4, r4, #12 80086e8: f1c4 0520 rsb r5, r4, #32 80086ec: fa00 f304 lsl.w r3, r0, r4 80086f0: fa20 f005 lsr.w r0, r0, r5 80086f4: fa01 f204 lsl.w r2, r1, r4 80086f8: ea40 0002 orr.w r0, r0, r2 80086fc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008700: eb10 70d3 adds.w r0, r0, r3, lsr #31 8008704: f141 0100 adc.w r1, r1, #0 8008708: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800870c: bf08 it eq 800870e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8008712: bd70 pop {r4, r5, r6, pc} 8008714: f1c4 0520 rsb r5, r4, #32 8008718: fa00 f205 lsl.w r2, r0, r5 800871c: ea4e 0e02 orr.w lr, lr, r2 8008720: fa20 f304 lsr.w r3, r0, r4 8008724: fa01 f205 lsl.w r2, r1, r5 8008728: ea43 0302 orr.w r3, r3, r2 800872c: fa21 f004 lsr.w r0, r1, r4 8008730: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008734: fa21 f204 lsr.w r2, r1, r4 8008738: ea20 0002 bic.w r0, r0, r2 800873c: eb00 70d3 add.w r0, r0, r3, lsr #31 8008740: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8008744: bf08 it eq 8008746: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800874a: bd70 pop {r4, r5, r6, pc} 800874c: f094 0f00 teq r4, #0 8008750: d10f bne.n 8008772 <__aeabi_dmul+0x1c2> 8008752: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 8008756: 0040 lsls r0, r0, #1 8008758: eb41 0101 adc.w r1, r1, r1 800875c: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008760: bf08 it eq 8008762: 3c01 subeq r4, #1 8008764: d0f7 beq.n 8008756 <__aeabi_dmul+0x1a6> 8008766: ea41 0106 orr.w r1, r1, r6 800876a: f095 0f00 teq r5, #0 800876e: bf18 it ne 8008770: 4770 bxne lr 8008772: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 8008776: 0052 lsls r2, r2, #1 8008778: eb43 0303 adc.w r3, r3, r3 800877c: f413 1f80 tst.w r3, #1048576 @ 0x100000 8008780: bf08 it eq 8008782: 3d01 subeq r5, #1 8008784: d0f7 beq.n 8008776 <__aeabi_dmul+0x1c6> 8008786: ea43 0306 orr.w r3, r3, r6 800878a: 4770 bx lr 800878c: ea94 0f0c teq r4, ip 8008790: ea0c 5513 and.w r5, ip, r3, lsr #20 8008794: bf18 it ne 8008796: ea95 0f0c teqne r5, ip 800879a: d00c beq.n 80087b6 <__aeabi_dmul+0x206> 800879c: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087a0: bf18 it ne 80087a2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087a6: d1d1 bne.n 800874c <__aeabi_dmul+0x19c> 80087a8: ea81 0103 eor.w r1, r1, r3 80087ac: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087b0: f04f 0000 mov.w r0, #0 80087b4: bd70 pop {r4, r5, r6, pc} 80087b6: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087ba: bf06 itte eq 80087bc: 4610 moveq r0, r2 80087be: 4619 moveq r1, r3 80087c0: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087c4: d019 beq.n 80087fa <__aeabi_dmul+0x24a> 80087c6: ea94 0f0c teq r4, ip 80087ca: d102 bne.n 80087d2 <__aeabi_dmul+0x222> 80087cc: ea50 3601 orrs.w r6, r0, r1, lsl #12 80087d0: d113 bne.n 80087fa <__aeabi_dmul+0x24a> 80087d2: ea95 0f0c teq r5, ip 80087d6: d105 bne.n 80087e4 <__aeabi_dmul+0x234> 80087d8: ea52 3603 orrs.w r6, r2, r3, lsl #12 80087dc: bf1c itt ne 80087de: 4610 movne r0, r2 80087e0: 4619 movne r1, r3 80087e2: d10a bne.n 80087fa <__aeabi_dmul+0x24a> 80087e4: ea81 0103 eor.w r1, r1, r3 80087e8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087ec: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087f0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 80087f4: f04f 0000 mov.w r0, #0 80087f8: bd70 pop {r4, r5, r6, pc} 80087fa: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087fe: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 8008802: bd70 pop {r4, r5, r6, pc} 08008804 <__aeabi_ddiv>: 8008804: b570 push {r4, r5, r6, lr} 8008806: f04f 0cff mov.w ip, #255 @ 0xff 800880a: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 800880e: ea1c 5411 ands.w r4, ip, r1, lsr #20 8008812: bf1d ittte ne 8008814: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8008818: ea94 0f0c teqne r4, ip 800881c: ea95 0f0c teqne r5, ip 8008820: f000 f8a7 bleq 8008972 <__aeabi_ddiv+0x16e> 8008824: eba4 0405 sub.w r4, r4, r5 8008828: ea81 0e03 eor.w lr, r1, r3 800882c: ea52 3503 orrs.w r5, r2, r3, lsl #12 8008830: ea4f 3101 mov.w r1, r1, lsl #12 8008834: f000 8088 beq.w 8008948 <__aeabi_ddiv+0x144> 8008838: ea4f 3303 mov.w r3, r3, lsl #12 800883c: f04f 5580 mov.w r5, #268435456 @ 0x10000000 8008840: ea45 1313 orr.w r3, r5, r3, lsr #4 8008844: ea43 6312 orr.w r3, r3, r2, lsr #24 8008848: ea4f 2202 mov.w r2, r2, lsl #8 800884c: ea45 1511 orr.w r5, r5, r1, lsr #4 8008850: ea45 6510 orr.w r5, r5, r0, lsr #24 8008854: ea4f 2600 mov.w r6, r0, lsl #8 8008858: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000 800885c: 429d cmp r5, r3 800885e: bf08 it eq 8008860: 4296 cmpeq r6, r2 8008862: f144 04fd adc.w r4, r4, #253 @ 0xfd 8008866: f504 7440 add.w r4, r4, #768 @ 0x300 800886a: d202 bcs.n 8008872 <__aeabi_ddiv+0x6e> 800886c: 085b lsrs r3, r3, #1 800886e: ea4f 0232 mov.w r2, r2, rrx 8008872: 1ab6 subs r6, r6, r2 8008874: eb65 0503 sbc.w r5, r5, r3 8008878: 085b lsrs r3, r3, #1 800887a: ea4f 0232 mov.w r2, r2, rrx 800887e: f44f 1080 mov.w r0, #1048576 @ 0x100000 8008882: f44f 2c00 mov.w ip, #524288 @ 0x80000 8008886: ebb6 0e02 subs.w lr, r6, r2 800888a: eb75 0e03 sbcs.w lr, r5, r3 800888e: bf22 ittt cs 8008890: 1ab6 subcs r6, r6, r2 8008892: 4675 movcs r5, lr 8008894: ea40 000c orrcs.w r0, r0, ip 8008898: 085b lsrs r3, r3, #1 800889a: ea4f 0232 mov.w r2, r2, rrx 800889e: ebb6 0e02 subs.w lr, r6, r2 80088a2: eb75 0e03 sbcs.w lr, r5, r3 80088a6: bf22 ittt cs 80088a8: 1ab6 subcs r6, r6, r2 80088aa: 4675 movcs r5, lr 80088ac: ea40 005c orrcs.w r0, r0, ip, lsr #1 80088b0: 085b lsrs r3, r3, #1 80088b2: ea4f 0232 mov.w r2, r2, rrx 80088b6: ebb6 0e02 subs.w lr, r6, r2 80088ba: eb75 0e03 sbcs.w lr, r5, r3 80088be: bf22 ittt cs 80088c0: 1ab6 subcs r6, r6, r2 80088c2: 4675 movcs r5, lr 80088c4: ea40 009c orrcs.w r0, r0, ip, lsr #2 80088c8: 085b lsrs r3, r3, #1 80088ca: ea4f 0232 mov.w r2, r2, rrx 80088ce: ebb6 0e02 subs.w lr, r6, r2 80088d2: eb75 0e03 sbcs.w lr, r5, r3 80088d6: bf22 ittt cs 80088d8: 1ab6 subcs r6, r6, r2 80088da: 4675 movcs r5, lr 80088dc: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80088e0: ea55 0e06 orrs.w lr, r5, r6 80088e4: d018 beq.n 8008918 <__aeabi_ddiv+0x114> 80088e6: ea4f 1505 mov.w r5, r5, lsl #4 80088ea: ea45 7516 orr.w r5, r5, r6, lsr #28 80088ee: ea4f 1606 mov.w r6, r6, lsl #4 80088f2: ea4f 03c3 mov.w r3, r3, lsl #3 80088f6: ea43 7352 orr.w r3, r3, r2, lsr #29 80088fa: ea4f 02c2 mov.w r2, r2, lsl #3 80088fe: ea5f 1c1c movs.w ip, ip, lsr #4 8008902: d1c0 bne.n 8008886 <__aeabi_ddiv+0x82> 8008904: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008908: d10b bne.n 8008922 <__aeabi_ddiv+0x11e> 800890a: ea41 0100 orr.w r1, r1, r0 800890e: f04f 0000 mov.w r0, #0 8008912: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000 8008916: e7b6 b.n 8008886 <__aeabi_ddiv+0x82> 8008918: f411 1f80 tst.w r1, #1048576 @ 0x100000 800891c: bf04 itt eq 800891e: 4301 orreq r1, r0 8008920: 2000 moveq r0, #0 8008922: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008926: bf88 it hi 8008928: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800892c: f63f aeaf bhi.w 800868e <__aeabi_dmul+0xde> 8008930: ebb5 0c03 subs.w ip, r5, r3 8008934: bf04 itt eq 8008936: ebb6 0c02 subseq.w ip, r6, r2 800893a: ea5f 0c50 movseq.w ip, r0, lsr #1 800893e: f150 0000 adcs.w r0, r0, #0 8008942: eb41 5104 adc.w r1, r1, r4, lsl #20 8008946: bd70 pop {r4, r5, r6, pc} 8008948: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000 800894c: ea4e 3111 orr.w r1, lr, r1, lsr #12 8008950: eb14 045c adds.w r4, r4, ip, lsr #1 8008954: bfc2 ittt gt 8008956: ebd4 050c rsbsgt r5, r4, ip 800895a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800895e: bd70 popgt {r4, r5, r6, pc} 8008960: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008964: f04f 0e00 mov.w lr, #0 8008968: 3c01 subs r4, #1 800896a: e690 b.n 800868e <__aeabi_dmul+0xde> 800896c: ea45 0e06 orr.w lr, r5, r6 8008970: e68d b.n 800868e <__aeabi_dmul+0xde> 8008972: ea0c 5513 and.w r5, ip, r3, lsr #20 8008976: ea94 0f0c teq r4, ip 800897a: bf08 it eq 800897c: ea95 0f0c teqeq r5, ip 8008980: f43f af3b beq.w 80087fa <__aeabi_dmul+0x24a> 8008984: ea94 0f0c teq r4, ip 8008988: d10a bne.n 80089a0 <__aeabi_ddiv+0x19c> 800898a: ea50 3401 orrs.w r4, r0, r1, lsl #12 800898e: f47f af34 bne.w 80087fa <__aeabi_dmul+0x24a> 8008992: ea95 0f0c teq r5, ip 8008996: f47f af25 bne.w 80087e4 <__aeabi_dmul+0x234> 800899a: 4610 mov r0, r2 800899c: 4619 mov r1, r3 800899e: e72c b.n 80087fa <__aeabi_dmul+0x24a> 80089a0: ea95 0f0c teq r5, ip 80089a4: d106 bne.n 80089b4 <__aeabi_ddiv+0x1b0> 80089a6: ea52 3503 orrs.w r5, r2, r3, lsl #12 80089aa: f43f aefd beq.w 80087a8 <__aeabi_dmul+0x1f8> 80089ae: 4610 mov r0, r2 80089b0: 4619 mov r1, r3 80089b2: e722 b.n 80087fa <__aeabi_dmul+0x24a> 80089b4: ea50 0641 orrs.w r6, r0, r1, lsl #1 80089b8: bf18 it ne 80089ba: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80089be: f47f aec5 bne.w 800874c <__aeabi_dmul+0x19c> 80089c2: ea50 0441 orrs.w r4, r0, r1, lsl #1 80089c6: f47f af0d bne.w 80087e4 <__aeabi_dmul+0x234> 80089ca: ea52 0543 orrs.w r5, r2, r3, lsl #1 80089ce: f47f aeeb bne.w 80087a8 <__aeabi_dmul+0x1f8> 80089d2: e712 b.n 80087fa <__aeabi_dmul+0x24a> 080089d4 <__gedf2>: 80089d4: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80089d8: e006 b.n 80089e8 <__cmpdf2+0x4> 80089da: bf00 nop 080089dc <__ledf2>: 80089dc: f04f 0c01 mov.w ip, #1 80089e0: e002 b.n 80089e8 <__cmpdf2+0x4> 80089e2: bf00 nop 080089e4 <__cmpdf2>: 80089e4: f04f 0c01 mov.w ip, #1 80089e8: f84d cd04 str.w ip, [sp, #-4]! 80089ec: ea4f 0c41 mov.w ip, r1, lsl #1 80089f0: ea7f 5c6c mvns.w ip, ip, asr #21 80089f4: ea4f 0c43 mov.w ip, r3, lsl #1 80089f8: bf18 it ne 80089fa: ea7f 5c6c mvnsne.w ip, ip, asr #21 80089fe: d01b beq.n 8008a38 <__cmpdf2+0x54> 8008a00: b001 add sp, #4 8008a02: ea50 0c41 orrs.w ip, r0, r1, lsl #1 8008a06: bf0c ite eq 8008a08: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 8008a0c: ea91 0f03 teqne r1, r3 8008a10: bf02 ittt eq 8008a12: ea90 0f02 teqeq r0, r2 8008a16: 2000 moveq r0, #0 8008a18: 4770 bxeq lr 8008a1a: f110 0f00 cmn.w r0, #0 8008a1e: ea91 0f03 teq r1, r3 8008a22: bf58 it pl 8008a24: 4299 cmppl r1, r3 8008a26: bf08 it eq 8008a28: 4290 cmpeq r0, r2 8008a2a: bf2c ite cs 8008a2c: 17d8 asrcs r0, r3, #31 8008a2e: ea6f 70e3 mvncc.w r0, r3, asr #31 8008a32: f040 0001 orr.w r0, r0, #1 8008a36: 4770 bx lr 8008a38: ea4f 0c41 mov.w ip, r1, lsl #1 8008a3c: ea7f 5c6c mvns.w ip, ip, asr #21 8008a40: d102 bne.n 8008a48 <__cmpdf2+0x64> 8008a42: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8008a46: d107 bne.n 8008a58 <__cmpdf2+0x74> 8008a48: ea4f 0c43 mov.w ip, r3, lsl #1 8008a4c: ea7f 5c6c mvns.w ip, ip, asr #21 8008a50: d1d6 bne.n 8008a00 <__cmpdf2+0x1c> 8008a52: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8008a56: d0d3 beq.n 8008a00 <__cmpdf2+0x1c> 8008a58: f85d 0b04 ldr.w r0, [sp], #4 8008a5c: 4770 bx lr 8008a5e: bf00 nop 08008a60 <__aeabi_cdrcmple>: 8008a60: 4684 mov ip, r0 8008a62: 4610 mov r0, r2 8008a64: 4662 mov r2, ip 8008a66: 468c mov ip, r1 8008a68: 4619 mov r1, r3 8008a6a: 4663 mov r3, ip 8008a6c: e000 b.n 8008a70 <__aeabi_cdcmpeq> 8008a6e: bf00 nop 08008a70 <__aeabi_cdcmpeq>: 8008a70: b501 push {r0, lr} 8008a72: f7ff ffb7 bl 80089e4 <__cmpdf2> 8008a76: 2800 cmp r0, #0 8008a78: bf48 it mi 8008a7a: f110 0f00 cmnmi.w r0, #0 8008a7e: bd01 pop {r0, pc} 08008a80 <__aeabi_dcmpeq>: 8008a80: f84d ed08 str.w lr, [sp, #-8]! 8008a84: f7ff fff4 bl 8008a70 <__aeabi_cdcmpeq> 8008a88: bf0c ite eq 8008a8a: 2001 moveq r0, #1 8008a8c: 2000 movne r0, #0 8008a8e: f85d fb08 ldr.w pc, [sp], #8 8008a92: bf00 nop 08008a94 <__aeabi_dcmplt>: 8008a94: f84d ed08 str.w lr, [sp, #-8]! 8008a98: f7ff ffea bl 8008a70 <__aeabi_cdcmpeq> 8008a9c: bf34 ite cc 8008a9e: 2001 movcc r0, #1 8008aa0: 2000 movcs r0, #0 8008aa2: f85d fb08 ldr.w pc, [sp], #8 8008aa6: bf00 nop 08008aa8 <__aeabi_dcmple>: 8008aa8: f84d ed08 str.w lr, [sp, #-8]! 8008aac: f7ff ffe0 bl 8008a70 <__aeabi_cdcmpeq> 8008ab0: bf94 ite ls 8008ab2: 2001 movls r0, #1 8008ab4: 2000 movhi r0, #0 8008ab6: f85d fb08 ldr.w pc, [sp], #8 8008aba: bf00 nop 08008abc <__aeabi_dcmpge>: 8008abc: f84d ed08 str.w lr, [sp, #-8]! 8008ac0: f7ff ffce bl 8008a60 <__aeabi_cdrcmple> 8008ac4: bf94 ite ls 8008ac6: 2001 movls r0, #1 8008ac8: 2000 movhi r0, #0 8008aca: f85d fb08 ldr.w pc, [sp], #8 8008ace: bf00 nop 08008ad0 <__aeabi_dcmpgt>: 8008ad0: f84d ed08 str.w lr, [sp, #-8]! 8008ad4: f7ff ffc4 bl 8008a60 <__aeabi_cdrcmple> 8008ad8: bf34 ite cc 8008ada: 2001 movcc r0, #1 8008adc: 2000 movcs r0, #0 8008ade: f85d fb08 ldr.w pc, [sp], #8 8008ae2: bf00 nop 08008ae4 <__aeabi_dcmpun>: 8008ae4: ea4f 0c41 mov.w ip, r1, lsl #1 8008ae8: ea7f 5c6c mvns.w ip, ip, asr #21 8008aec: d102 bne.n 8008af4 <__aeabi_dcmpun+0x10> 8008aee: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8008af2: d10a bne.n 8008b0a <__aeabi_dcmpun+0x26> 8008af4: ea4f 0c43 mov.w ip, r3, lsl #1 8008af8: ea7f 5c6c mvns.w ip, ip, asr #21 8008afc: d102 bne.n 8008b04 <__aeabi_dcmpun+0x20> 8008afe: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8008b02: d102 bne.n 8008b0a <__aeabi_dcmpun+0x26> 8008b04: f04f 0000 mov.w r0, #0 8008b08: 4770 bx lr 8008b0a: f04f 0001 mov.w r0, #1 8008b0e: 4770 bx lr 08008b10 <__aeabi_d2iz>: 8008b10: ea4f 0241 mov.w r2, r1, lsl #1 8008b14: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 8008b18: d215 bcs.n 8008b46 <__aeabi_d2iz+0x36> 8008b1a: d511 bpl.n 8008b40 <__aeabi_d2iz+0x30> 8008b1c: f46f 7378 mvn.w r3, #992 @ 0x3e0 8008b20: ebb3 5262 subs.w r2, r3, r2, asr #21 8008b24: d912 bls.n 8008b4c <__aeabi_d2iz+0x3c> 8008b26: ea4f 23c1 mov.w r3, r1, lsl #11 8008b2a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8008b2e: ea43 5350 orr.w r3, r3, r0, lsr #21 8008b32: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008b36: fa23 f002 lsr.w r0, r3, r2 8008b3a: bf18 it ne 8008b3c: 4240 negne r0, r0 8008b3e: 4770 bx lr 8008b40: f04f 0000 mov.w r0, #0 8008b44: 4770 bx lr 8008b46: ea50 3001 orrs.w r0, r0, r1, lsl #12 8008b4a: d105 bne.n 8008b58 <__aeabi_d2iz+0x48> 8008b4c: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000 8008b50: bf08 it eq 8008b52: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 8008b56: 4770 bx lr 8008b58: f04f 0000 mov.w r0, #0 8008b5c: 4770 bx lr 8008b5e: bf00 nop 08008b60 <__aeabi_d2f>: 8008b60: ea4f 0241 mov.w r2, r1, lsl #1 8008b64: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000 8008b68: bf24 itt cs 8008b6a: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000 8008b6e: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000 8008b72: d90d bls.n 8008b90 <__aeabi_d2f+0x30> 8008b74: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008b78: ea4f 02c0 mov.w r2, r0, lsl #3 8008b7c: ea4c 7050 orr.w r0, ip, r0, lsr #29 8008b80: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000 8008b84: eb40 0083 adc.w r0, r0, r3, lsl #2 8008b88: bf08 it eq 8008b8a: f020 0001 biceq.w r0, r0, #1 8008b8e: 4770 bx lr 8008b90: f011 4f80 tst.w r1, #1073741824 @ 0x40000000 8008b94: d121 bne.n 8008bda <__aeabi_d2f+0x7a> 8008b96: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000 8008b9a: bfbc itt lt 8008b9c: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000 8008ba0: 4770 bxlt lr 8008ba2: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008ba6: ea4f 5252 mov.w r2, r2, lsr #21 8008baa: f1c2 0218 rsb r2, r2, #24 8008bae: f1c2 0c20 rsb ip, r2, #32 8008bb2: fa10 f30c lsls.w r3, r0, ip 8008bb6: fa20 f002 lsr.w r0, r0, r2 8008bba: bf18 it ne 8008bbc: f040 0001 orrne.w r0, r0, #1 8008bc0: ea4f 23c1 mov.w r3, r1, lsl #11 8008bc4: ea4f 23d3 mov.w r3, r3, lsr #11 8008bc8: fa03 fc0c lsl.w ip, r3, ip 8008bcc: ea40 000c orr.w r0, r0, ip 8008bd0: fa23 f302 lsr.w r3, r3, r2 8008bd4: ea4f 0343 mov.w r3, r3, lsl #1 8008bd8: e7cc b.n 8008b74 <__aeabi_d2f+0x14> 8008bda: ea7f 5362 mvns.w r3, r2, asr #21 8008bde: d107 bne.n 8008bf0 <__aeabi_d2f+0x90> 8008be0: ea50 3301 orrs.w r3, r0, r1, lsl #12 8008be4: bf1e ittt ne 8008be6: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000 8008bea: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000 8008bee: 4770 bxne lr 8008bf0: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000 8008bf4: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008bf8: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008bfc: 4770 bx lr 8008bfe: bf00 nop 08008c00 <__aeabi_frsub>: 8008c00: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000 8008c04: e002 b.n 8008c0c <__addsf3> 8008c06: bf00 nop 08008c08 <__aeabi_fsub>: 8008c08: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 08008c0c <__addsf3>: 8008c0c: 0042 lsls r2, r0, #1 8008c0e: bf1f itttt ne 8008c10: ea5f 0341 movsne.w r3, r1, lsl #1 8008c14: ea92 0f03 teqne r2, r3 8008c18: ea7f 6c22 mvnsne.w ip, r2, asr #24 8008c1c: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008c20: d06a beq.n 8008cf8 <__addsf3+0xec> 8008c22: ea4f 6212 mov.w r2, r2, lsr #24 8008c26: ebd2 6313 rsbs r3, r2, r3, lsr #24 8008c2a: bfc1 itttt gt 8008c2c: 18d2 addgt r2, r2, r3 8008c2e: 4041 eorgt r1, r0 8008c30: 4048 eorgt r0, r1 8008c32: 4041 eorgt r1, r0 8008c34: bfb8 it lt 8008c36: 425b neglt r3, r3 8008c38: 2b19 cmp r3, #25 8008c3a: bf88 it hi 8008c3c: 4770 bxhi lr 8008c3e: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 8008c42: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008c46: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000 8008c4a: bf18 it ne 8008c4c: 4240 negne r0, r0 8008c4e: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008c52: f441 0100 orr.w r1, r1, #8388608 @ 0x800000 8008c56: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000 8008c5a: bf18 it ne 8008c5c: 4249 negne r1, r1 8008c5e: ea92 0f03 teq r2, r3 8008c62: d03f beq.n 8008ce4 <__addsf3+0xd8> 8008c64: f1a2 0201 sub.w r2, r2, #1 8008c68: fa41 fc03 asr.w ip, r1, r3 8008c6c: eb10 000c adds.w r0, r0, ip 8008c70: f1c3 0320 rsb r3, r3, #32 8008c74: fa01 f103 lsl.w r1, r1, r3 8008c78: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008c7c: d502 bpl.n 8008c84 <__addsf3+0x78> 8008c7e: 4249 negs r1, r1 8008c80: eb60 0040 sbc.w r0, r0, r0, lsl #1 8008c84: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000 8008c88: d313 bcc.n 8008cb2 <__addsf3+0xa6> 8008c8a: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000 8008c8e: d306 bcc.n 8008c9e <__addsf3+0x92> 8008c90: 0840 lsrs r0, r0, #1 8008c92: ea4f 0131 mov.w r1, r1, rrx 8008c96: f102 0201 add.w r2, r2, #1 8008c9a: 2afe cmp r2, #254 @ 0xfe 8008c9c: d251 bcs.n 8008d42 <__addsf3+0x136> 8008c9e: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000 8008ca2: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008ca6: bf08 it eq 8008ca8: f020 0001 biceq.w r0, r0, #1 8008cac: ea40 0003 orr.w r0, r0, r3 8008cb0: 4770 bx lr 8008cb2: 0049 lsls r1, r1, #1 8008cb4: eb40 0000 adc.w r0, r0, r0 8008cb8: 3a01 subs r2, #1 8008cba: bf28 it cs 8008cbc: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000 8008cc0: d2ed bcs.n 8008c9e <__addsf3+0x92> 8008cc2: fab0 fc80 clz ip, r0 8008cc6: f1ac 0c08 sub.w ip, ip, #8 8008cca: ebb2 020c subs.w r2, r2, ip 8008cce: fa00 f00c lsl.w r0, r0, ip 8008cd2: bfaa itet ge 8008cd4: eb00 50c2 addge.w r0, r0, r2, lsl #23 8008cd8: 4252 neglt r2, r2 8008cda: 4318 orrge r0, r3 8008cdc: bfbc itt lt 8008cde: 40d0 lsrlt r0, r2 8008ce0: 4318 orrlt r0, r3 8008ce2: 4770 bx lr 8008ce4: f092 0f00 teq r2, #0 8008ce8: f481 0100 eor.w r1, r1, #8388608 @ 0x800000 8008cec: bf06 itte eq 8008cee: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000 8008cf2: 3201 addeq r2, #1 8008cf4: 3b01 subne r3, #1 8008cf6: e7b5 b.n 8008c64 <__addsf3+0x58> 8008cf8: ea4f 0341 mov.w r3, r1, lsl #1 8008cfc: ea7f 6c22 mvns.w ip, r2, asr #24 8008d00: bf18 it ne 8008d02: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008d06: d021 beq.n 8008d4c <__addsf3+0x140> 8008d08: ea92 0f03 teq r2, r3 8008d0c: d004 beq.n 8008d18 <__addsf3+0x10c> 8008d0e: f092 0f00 teq r2, #0 8008d12: bf08 it eq 8008d14: 4608 moveq r0, r1 8008d16: 4770 bx lr 8008d18: ea90 0f01 teq r0, r1 8008d1c: bf1c itt ne 8008d1e: 2000 movne r0, #0 8008d20: 4770 bxne lr 8008d22: f012 4f7f tst.w r2, #4278190080 @ 0xff000000 8008d26: d104 bne.n 8008d32 <__addsf3+0x126> 8008d28: 0040 lsls r0, r0, #1 8008d2a: bf28 it cs 8008d2c: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000 8008d30: 4770 bx lr 8008d32: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000 8008d36: bf3c itt cc 8008d38: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000 8008d3c: 4770 bxcc lr 8008d3e: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008d42: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000 8008d46: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008d4a: 4770 bx lr 8008d4c: ea7f 6222 mvns.w r2, r2, asr #24 8008d50: bf16 itet ne 8008d52: 4608 movne r0, r1 8008d54: ea7f 6323 mvnseq.w r3, r3, asr #24 8008d58: 4601 movne r1, r0 8008d5a: 0242 lsls r2, r0, #9 8008d5c: bf06 itte eq 8008d5e: ea5f 2341 movseq.w r3, r1, lsl #9 8008d62: ea90 0f01 teqeq r0, r1 8008d66: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000 8008d6a: 4770 bx lr 08008d6c <__aeabi_ui2f>: 8008d6c: f04f 0300 mov.w r3, #0 8008d70: e004 b.n 8008d7c <__aeabi_i2f+0x8> 8008d72: bf00 nop 08008d74 <__aeabi_i2f>: 8008d74: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000 8008d78: bf48 it mi 8008d7a: 4240 negmi r0, r0 8008d7c: ea5f 0c00 movs.w ip, r0 8008d80: bf08 it eq 8008d82: 4770 bxeq lr 8008d84: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000 8008d88: 4601 mov r1, r0 8008d8a: f04f 0000 mov.w r0, #0 8008d8e: e01c b.n 8008dca <__aeabi_l2f+0x2a> 08008d90 <__aeabi_ul2f>: 8008d90: ea50 0201 orrs.w r2, r0, r1 8008d94: bf08 it eq 8008d96: 4770 bxeq lr 8008d98: f04f 0300 mov.w r3, #0 8008d9c: e00a b.n 8008db4 <__aeabi_l2f+0x14> 8008d9e: bf00 nop 08008da0 <__aeabi_l2f>: 8008da0: ea50 0201 orrs.w r2, r0, r1 8008da4: bf08 it eq 8008da6: 4770 bxeq lr 8008da8: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000 8008dac: d502 bpl.n 8008db4 <__aeabi_l2f+0x14> 8008dae: 4240 negs r0, r0 8008db0: eb61 0141 sbc.w r1, r1, r1, lsl #1 8008db4: ea5f 0c01 movs.w ip, r1 8008db8: bf02 ittt eq 8008dba: 4684 moveq ip, r0 8008dbc: 4601 moveq r1, r0 8008dbe: 2000 moveq r0, #0 8008dc0: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000 8008dc4: bf08 it eq 8008dc6: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000 8008dca: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 8008dce: fabc f28c clz r2, ip 8008dd2: 3a08 subs r2, #8 8008dd4: eba3 53c2 sub.w r3, r3, r2, lsl #23 8008dd8: db10 blt.n 8008dfc <__aeabi_l2f+0x5c> 8008dda: fa01 fc02 lsl.w ip, r1, r2 8008dde: 4463 add r3, ip 8008de0: fa00 fc02 lsl.w ip, r0, r2 8008de4: f1c2 0220 rsb r2, r2, #32 8008de8: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008dec: fa20 f202 lsr.w r2, r0, r2 8008df0: eb43 0002 adc.w r0, r3, r2 8008df4: bf08 it eq 8008df6: f020 0001 biceq.w r0, r0, #1 8008dfa: 4770 bx lr 8008dfc: f102 0220 add.w r2, r2, #32 8008e00: fa01 fc02 lsl.w ip, r1, r2 8008e04: f1c2 0220 rsb r2, r2, #32 8008e08: ea50 004c orrs.w r0, r0, ip, lsl #1 8008e0c: fa21 f202 lsr.w r2, r1, r2 8008e10: eb43 0002 adc.w r0, r3, r2 8008e14: bf08 it eq 8008e16: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008e1a: 4770 bx lr 08008e1c <__aeabi_fmul>: 8008e1c: f04f 0cff mov.w ip, #255 @ 0xff 8008e20: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008e24: bf1e ittt ne 8008e26: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008e2a: ea92 0f0c teqne r2, ip 8008e2e: ea93 0f0c teqne r3, ip 8008e32: d06f beq.n 8008f14 <__aeabi_fmul+0xf8> 8008e34: 441a add r2, r3 8008e36: ea80 0c01 eor.w ip, r0, r1 8008e3a: 0240 lsls r0, r0, #9 8008e3c: bf18 it ne 8008e3e: ea5f 2141 movsne.w r1, r1, lsl #9 8008e42: d01e beq.n 8008e82 <__aeabi_fmul+0x66> 8008e44: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8008e48: ea43 1050 orr.w r0, r3, r0, lsr #5 8008e4c: ea43 1151 orr.w r1, r3, r1, lsr #5 8008e50: fba0 3101 umull r3, r1, r0, r1 8008e54: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008e58: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000 8008e5c: bf3e ittt cc 8008e5e: 0049 lslcc r1, r1, #1 8008e60: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 8008e64: 005b lslcc r3, r3, #1 8008e66: ea40 0001 orr.w r0, r0, r1 8008e6a: f162 027f sbc.w r2, r2, #127 @ 0x7f 8008e6e: 2afd cmp r2, #253 @ 0xfd 8008e70: d81d bhi.n 8008eae <__aeabi_fmul+0x92> 8008e72: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008e76: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008e7a: bf08 it eq 8008e7c: f020 0001 biceq.w r0, r0, #1 8008e80: 4770 bx lr 8008e82: f090 0f00 teq r0, #0 8008e86: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8008e8a: bf08 it eq 8008e8c: 0249 lsleq r1, r1, #9 8008e8e: ea4c 2050 orr.w r0, ip, r0, lsr #9 8008e92: ea40 2051 orr.w r0, r0, r1, lsr #9 8008e96: 3a7f subs r2, #127 @ 0x7f 8008e98: bfc2 ittt gt 8008e9a: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 8008e9e: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8008ea2: 4770 bxgt lr 8008ea4: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008ea8: f04f 0300 mov.w r3, #0 8008eac: 3a01 subs r2, #1 8008eae: dc5d bgt.n 8008f6c <__aeabi_fmul+0x150> 8008eb0: f112 0f19 cmn.w r2, #25 8008eb4: bfdc itt le 8008eb6: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000 8008eba: 4770 bxle lr 8008ebc: f1c2 0200 rsb r2, r2, #0 8008ec0: 0041 lsls r1, r0, #1 8008ec2: fa21 f102 lsr.w r1, r1, r2 8008ec6: f1c2 0220 rsb r2, r2, #32 8008eca: fa00 fc02 lsl.w ip, r0, r2 8008ece: ea5f 0031 movs.w r0, r1, rrx 8008ed2: f140 0000 adc.w r0, r0, #0 8008ed6: ea53 034c orrs.w r3, r3, ip, lsl #1 8008eda: bf08 it eq 8008edc: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008ee0: 4770 bx lr 8008ee2: f092 0f00 teq r2, #0 8008ee6: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8008eea: bf02 ittt eq 8008eec: 0040 lsleq r0, r0, #1 8008eee: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 8008ef2: 3a01 subeq r2, #1 8008ef4: d0f9 beq.n 8008eea <__aeabi_fmul+0xce> 8008ef6: ea40 000c orr.w r0, r0, ip 8008efa: f093 0f00 teq r3, #0 8008efe: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008f02: bf02 ittt eq 8008f04: 0049 lsleq r1, r1, #1 8008f06: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8008f0a: 3b01 subeq r3, #1 8008f0c: d0f9 beq.n 8008f02 <__aeabi_fmul+0xe6> 8008f0e: ea41 010c orr.w r1, r1, ip 8008f12: e78f b.n 8008e34 <__aeabi_fmul+0x18> 8008f14: ea0c 53d1 and.w r3, ip, r1, lsr #23 8008f18: ea92 0f0c teq r2, ip 8008f1c: bf18 it ne 8008f1e: ea93 0f0c teqne r3, ip 8008f22: d00a beq.n 8008f3a <__aeabi_fmul+0x11e> 8008f24: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 8008f28: bf18 it ne 8008f2a: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 8008f2e: d1d8 bne.n 8008ee2 <__aeabi_fmul+0xc6> 8008f30: ea80 0001 eor.w r0, r0, r1 8008f34: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008f38: 4770 bx lr 8008f3a: f090 0f00 teq r0, #0 8008f3e: bf17 itett ne 8008f40: f090 4f00 teqne r0, #2147483648 @ 0x80000000 8008f44: 4608 moveq r0, r1 8008f46: f091 0f00 teqne r1, #0 8008f4a: f091 4f00 teqne r1, #2147483648 @ 0x80000000 8008f4e: d014 beq.n 8008f7a <__aeabi_fmul+0x15e> 8008f50: ea92 0f0c teq r2, ip 8008f54: d101 bne.n 8008f5a <__aeabi_fmul+0x13e> 8008f56: 0242 lsls r2, r0, #9 8008f58: d10f bne.n 8008f7a <__aeabi_fmul+0x15e> 8008f5a: ea93 0f0c teq r3, ip 8008f5e: d103 bne.n 8008f68 <__aeabi_fmul+0x14c> 8008f60: 024b lsls r3, r1, #9 8008f62: bf18 it ne 8008f64: 4608 movne r0, r1 8008f66: d108 bne.n 8008f7a <__aeabi_fmul+0x15e> 8008f68: ea80 0001 eor.w r0, r0, r1 8008f6c: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008f70: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008f74: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008f78: 4770 bx lr 8008f7a: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008f7e: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000 8008f82: 4770 bx lr 08008f84 <__aeabi_fdiv>: 8008f84: f04f 0cff mov.w ip, #255 @ 0xff 8008f88: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008f8c: bf1e ittt ne 8008f8e: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008f92: ea92 0f0c teqne r2, ip 8008f96: ea93 0f0c teqne r3, ip 8008f9a: d069 beq.n 8009070 <__aeabi_fdiv+0xec> 8008f9c: eba2 0203 sub.w r2, r2, r3 8008fa0: ea80 0c01 eor.w ip, r0, r1 8008fa4: 0249 lsls r1, r1, #9 8008fa6: ea4f 2040 mov.w r0, r0, lsl #9 8008faa: d037 beq.n 800901c <__aeabi_fdiv+0x98> 8008fac: f04f 5380 mov.w r3, #268435456 @ 0x10000000 8008fb0: ea43 1111 orr.w r1, r3, r1, lsr #4 8008fb4: ea43 1310 orr.w r3, r3, r0, lsr #4 8008fb8: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008fbc: 428b cmp r3, r1 8008fbe: bf38 it cc 8008fc0: 005b lslcc r3, r3, #1 8008fc2: f142 027d adc.w r2, r2, #125 @ 0x7d 8008fc6: f44f 0c00 mov.w ip, #8388608 @ 0x800000 8008fca: 428b cmp r3, r1 8008fcc: bf24 itt cs 8008fce: 1a5b subcs r3, r3, r1 8008fd0: ea40 000c orrcs.w r0, r0, ip 8008fd4: ebb3 0f51 cmp.w r3, r1, lsr #1 8008fd8: bf24 itt cs 8008fda: eba3 0351 subcs.w r3, r3, r1, lsr #1 8008fde: ea40 005c orrcs.w r0, r0, ip, lsr #1 8008fe2: ebb3 0f91 cmp.w r3, r1, lsr #2 8008fe6: bf24 itt cs 8008fe8: eba3 0391 subcs.w r3, r3, r1, lsr #2 8008fec: ea40 009c orrcs.w r0, r0, ip, lsr #2 8008ff0: ebb3 0fd1 cmp.w r3, r1, lsr #3 8008ff4: bf24 itt cs 8008ff6: eba3 03d1 subcs.w r3, r3, r1, lsr #3 8008ffa: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8008ffe: 011b lsls r3, r3, #4 8009000: bf18 it ne 8009002: ea5f 1c1c movsne.w ip, ip, lsr #4 8009006: d1e0 bne.n 8008fca <__aeabi_fdiv+0x46> 8009008: 2afd cmp r2, #253 @ 0xfd 800900a: f63f af50 bhi.w 8008eae <__aeabi_fmul+0x92> 800900e: 428b cmp r3, r1 8009010: eb40 50c2 adc.w r0, r0, r2, lsl #23 8009014: bf08 it eq 8009016: f020 0001 biceq.w r0, r0, #1 800901a: 4770 bx lr 800901c: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8009020: ea4c 2050 orr.w r0, ip, r0, lsr #9 8009024: 327f adds r2, #127 @ 0x7f 8009026: bfc2 ittt gt 8009028: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 800902c: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8009030: 4770 bxgt lr 8009032: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8009036: f04f 0300 mov.w r3, #0 800903a: 3a01 subs r2, #1 800903c: e737 b.n 8008eae <__aeabi_fmul+0x92> 800903e: f092 0f00 teq r2, #0 8009042: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8009046: bf02 ittt eq 8009048: 0040 lsleq r0, r0, #1 800904a: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 800904e: 3a01 subeq r2, #1 8009050: d0f9 beq.n 8009046 <__aeabi_fdiv+0xc2> 8009052: ea40 000c orr.w r0, r0, ip 8009056: f093 0f00 teq r3, #0 800905a: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 800905e: bf02 ittt eq 8009060: 0049 lsleq r1, r1, #1 8009062: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8009066: 3b01 subeq r3, #1 8009068: d0f9 beq.n 800905e <__aeabi_fdiv+0xda> 800906a: ea41 010c orr.w r1, r1, ip 800906e: e795 b.n 8008f9c <__aeabi_fdiv+0x18> 8009070: ea0c 53d1 and.w r3, ip, r1, lsr #23 8009074: ea92 0f0c teq r2, ip 8009078: d108 bne.n 800908c <__aeabi_fdiv+0x108> 800907a: 0242 lsls r2, r0, #9 800907c: f47f af7d bne.w 8008f7a <__aeabi_fmul+0x15e> 8009080: ea93 0f0c teq r3, ip 8009084: f47f af70 bne.w 8008f68 <__aeabi_fmul+0x14c> 8009088: 4608 mov r0, r1 800908a: e776 b.n 8008f7a <__aeabi_fmul+0x15e> 800908c: ea93 0f0c teq r3, ip 8009090: d104 bne.n 800909c <__aeabi_fdiv+0x118> 8009092: 024b lsls r3, r1, #9 8009094: f43f af4c beq.w 8008f30 <__aeabi_fmul+0x114> 8009098: 4608 mov r0, r1 800909a: e76e b.n 8008f7a <__aeabi_fmul+0x15e> 800909c: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 80090a0: bf18 it ne 80090a2: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 80090a6: d1ca bne.n 800903e <__aeabi_fdiv+0xba> 80090a8: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000 80090ac: f47f af5c bne.w 8008f68 <__aeabi_fmul+0x14c> 80090b0: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000 80090b4: f47f af3c bne.w 8008f30 <__aeabi_fmul+0x114> 80090b8: e75f b.n 8008f7a <__aeabi_fmul+0x15e> 80090ba: bf00 nop 080090bc <__gesf2>: 80090bc: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80090c0: e006 b.n 80090d0 <__cmpsf2+0x4> 80090c2: bf00 nop 080090c4 <__lesf2>: 80090c4: f04f 0c01 mov.w ip, #1 80090c8: e002 b.n 80090d0 <__cmpsf2+0x4> 80090ca: bf00 nop 080090cc <__cmpsf2>: 80090cc: f04f 0c01 mov.w ip, #1 80090d0: f84d cd04 str.w ip, [sp, #-4]! 80090d4: ea4f 0240 mov.w r2, r0, lsl #1 80090d8: ea4f 0341 mov.w r3, r1, lsl #1 80090dc: ea7f 6c22 mvns.w ip, r2, asr #24 80090e0: bf18 it ne 80090e2: ea7f 6c23 mvnsne.w ip, r3, asr #24 80090e6: d011 beq.n 800910c <__cmpsf2+0x40> 80090e8: b001 add sp, #4 80090ea: ea52 0c53 orrs.w ip, r2, r3, lsr #1 80090ee: bf18 it ne 80090f0: ea90 0f01 teqne r0, r1 80090f4: bf58 it pl 80090f6: ebb2 0003 subspl.w r0, r2, r3 80090fa: bf88 it hi 80090fc: 17c8 asrhi r0, r1, #31 80090fe: bf38 it cc 8009100: ea6f 70e1 mvncc.w r0, r1, asr #31 8009104: bf18 it ne 8009106: f040 0001 orrne.w r0, r0, #1 800910a: 4770 bx lr 800910c: ea7f 6c22 mvns.w ip, r2, asr #24 8009110: d102 bne.n 8009118 <__cmpsf2+0x4c> 8009112: ea5f 2c40 movs.w ip, r0, lsl #9 8009116: d105 bne.n 8009124 <__cmpsf2+0x58> 8009118: ea7f 6c23 mvns.w ip, r3, asr #24 800911c: d1e4 bne.n 80090e8 <__cmpsf2+0x1c> 800911e: ea5f 2c41 movs.w ip, r1, lsl #9 8009122: d0e1 beq.n 80090e8 <__cmpsf2+0x1c> 8009124: f85d 0b04 ldr.w r0, [sp], #4 8009128: 4770 bx lr 800912a: bf00 nop 0800912c <__aeabi_cfrcmple>: 800912c: 4684 mov ip, r0 800912e: 4608 mov r0, r1 8009130: 4661 mov r1, ip 8009132: e7ff b.n 8009134 <__aeabi_cfcmpeq> 08009134 <__aeabi_cfcmpeq>: 8009134: b50f push {r0, r1, r2, r3, lr} 8009136: f7ff ffc9 bl 80090cc <__cmpsf2> 800913a: 2800 cmp r0, #0 800913c: bf48 it mi 800913e: f110 0f00 cmnmi.w r0, #0 8009142: bd0f pop {r0, r1, r2, r3, pc} 08009144 <__aeabi_fcmpeq>: 8009144: f84d ed08 str.w lr, [sp, #-8]! 8009148: f7ff fff4 bl 8009134 <__aeabi_cfcmpeq> 800914c: bf0c ite eq 800914e: 2001 moveq r0, #1 8009150: 2000 movne r0, #0 8009152: f85d fb08 ldr.w pc, [sp], #8 8009156: bf00 nop 08009158 <__aeabi_fcmplt>: 8009158: f84d ed08 str.w lr, [sp, #-8]! 800915c: f7ff ffea bl 8009134 <__aeabi_cfcmpeq> 8009160: bf34 ite cc 8009162: 2001 movcc r0, #1 8009164: 2000 movcs r0, #0 8009166: f85d fb08 ldr.w pc, [sp], #8 800916a: bf00 nop 0800916c <__aeabi_fcmple>: 800916c: f84d ed08 str.w lr, [sp, #-8]! 8009170: f7ff ffe0 bl 8009134 <__aeabi_cfcmpeq> 8009174: bf94 ite ls 8009176: 2001 movls r0, #1 8009178: 2000 movhi r0, #0 800917a: f85d fb08 ldr.w pc, [sp], #8 800917e: bf00 nop 08009180 <__aeabi_fcmpge>: 8009180: f84d ed08 str.w lr, [sp, #-8]! 8009184: f7ff ffd2 bl 800912c <__aeabi_cfrcmple> 8009188: bf94 ite ls 800918a: 2001 movls r0, #1 800918c: 2000 movhi r0, #0 800918e: f85d fb08 ldr.w pc, [sp], #8 8009192: bf00 nop 08009194 <__aeabi_fcmpgt>: 8009194: f84d ed08 str.w lr, [sp, #-8]! 8009198: f7ff ffc8 bl 800912c <__aeabi_cfrcmple> 800919c: bf34 ite cc 800919e: 2001 movcc r0, #1 80091a0: 2000 movcs r0, #0 80091a2: f85d fb08 ldr.w pc, [sp], #8 80091a6: bf00 nop 080091a8 <__aeabi_f2iz>: 80091a8: ea4f 0240 mov.w r2, r0, lsl #1 80091ac: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000 80091b0: d30f bcc.n 80091d2 <__aeabi_f2iz+0x2a> 80091b2: f04f 039e mov.w r3, #158 @ 0x9e 80091b6: ebb3 6212 subs.w r2, r3, r2, lsr #24 80091ba: d90d bls.n 80091d8 <__aeabi_f2iz+0x30> 80091bc: ea4f 2300 mov.w r3, r0, lsl #8 80091c0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80091c4: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 80091c8: fa23 f002 lsr.w r0, r3, r2 80091cc: bf18 it ne 80091ce: 4240 negne r0, r0 80091d0: 4770 bx lr 80091d2: f04f 0000 mov.w r0, #0 80091d6: 4770 bx lr 80091d8: f112 0f61 cmn.w r2, #97 @ 0x61 80091dc: d101 bne.n 80091e2 <__aeabi_f2iz+0x3a> 80091de: 0242 lsls r2, r0, #9 80091e0: d105 bne.n 80091ee <__aeabi_f2iz+0x46> 80091e2: f010 4000 ands.w r0, r0, #2147483648 @ 0x80000000 80091e6: bf08 it eq 80091e8: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 80091ec: 4770 bx lr 80091ee: f04f 0000 mov.w r0, #0 80091f2: 4770 bx lr 080091f4 <__aeabi_uldivmod>: 80091f4: b953 cbnz r3, 800920c <__aeabi_uldivmod+0x18> 80091f6: b94a cbnz r2, 800920c <__aeabi_uldivmod+0x18> 80091f8: 2900 cmp r1, #0 80091fa: bf08 it eq 80091fc: 2800 cmpeq r0, #0 80091fe: bf1c itt ne 8009200: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8009204: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8009208: f000 b98c b.w 8009524 <__aeabi_idiv0> 800920c: f1ad 0c08 sub.w ip, sp, #8 8009210: e96d ce04 strd ip, lr, [sp, #-16]! 8009214: f000 f806 bl 8009224 <__udivmoddi4> 8009218: f8dd e004 ldr.w lr, [sp, #4] 800921c: e9dd 2302 ldrd r2, r3, [sp, #8] 8009220: b004 add sp, #16 8009222: 4770 bx lr 08009224 <__udivmoddi4>: 8009224: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8009228: 9d08 ldr r5, [sp, #32] 800922a: 468e mov lr, r1 800922c: 4604 mov r4, r0 800922e: 4688 mov r8, r1 8009230: 2b00 cmp r3, #0 8009232: d14a bne.n 80092ca <__udivmoddi4+0xa6> 8009234: 428a cmp r2, r1 8009236: 4617 mov r7, r2 8009238: d962 bls.n 8009300 <__udivmoddi4+0xdc> 800923a: fab2 f682 clz r6, r2 800923e: b14e cbz r6, 8009254 <__udivmoddi4+0x30> 8009240: f1c6 0320 rsb r3, r6, #32 8009244: fa01 f806 lsl.w r8, r1, r6 8009248: fa20 f303 lsr.w r3, r0, r3 800924c: 40b7 lsls r7, r6 800924e: ea43 0808 orr.w r8, r3, r8 8009252: 40b4 lsls r4, r6 8009254: ea4f 4e17 mov.w lr, r7, lsr #16 8009258: fbb8 f1fe udiv r1, r8, lr 800925c: fa1f fc87 uxth.w ip, r7 8009260: fb0e 8811 mls r8, lr, r1, r8 8009264: fb01 f20c mul.w r2, r1, ip 8009268: 0c23 lsrs r3, r4, #16 800926a: ea43 4308 orr.w r3, r3, r8, lsl #16 800926e: 429a cmp r2, r3 8009270: d909 bls.n 8009286 <__udivmoddi4+0x62> 8009272: 18fb adds r3, r7, r3 8009274: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8009278: f080 80eb bcs.w 8009452 <__udivmoddi4+0x22e> 800927c: 429a cmp r2, r3 800927e: f240 80e8 bls.w 8009452 <__udivmoddi4+0x22e> 8009282: 3902 subs r1, #2 8009284: 443b add r3, r7 8009286: 1a9a subs r2, r3, r2 8009288: fbb2 f0fe udiv r0, r2, lr 800928c: fb0e 2210 mls r2, lr, r0, r2 8009290: fb00 fc0c mul.w ip, r0, ip 8009294: b2a3 uxth r3, r4 8009296: ea43 4302 orr.w r3, r3, r2, lsl #16 800929a: 459c cmp ip, r3 800929c: d909 bls.n 80092b2 <__udivmoddi4+0x8e> 800929e: 18fb adds r3, r7, r3 80092a0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80092a4: f080 80d7 bcs.w 8009456 <__udivmoddi4+0x232> 80092a8: 459c cmp ip, r3 80092aa: f240 80d4 bls.w 8009456 <__udivmoddi4+0x232> 80092ae: 443b add r3, r7 80092b0: 3802 subs r0, #2 80092b2: ea40 4001 orr.w r0, r0, r1, lsl #16 80092b6: 2100 movs r1, #0 80092b8: eba3 030c sub.w r3, r3, ip 80092bc: b11d cbz r5, 80092c6 <__udivmoddi4+0xa2> 80092be: 2200 movs r2, #0 80092c0: 40f3 lsrs r3, r6 80092c2: e9c5 3200 strd r3, r2, [r5] 80092c6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80092ca: 428b cmp r3, r1 80092cc: d905 bls.n 80092da <__udivmoddi4+0xb6> 80092ce: b10d cbz r5, 80092d4 <__udivmoddi4+0xb0> 80092d0: e9c5 0100 strd r0, r1, [r5] 80092d4: 2100 movs r1, #0 80092d6: 4608 mov r0, r1 80092d8: e7f5 b.n 80092c6 <__udivmoddi4+0xa2> 80092da: fab3 f183 clz r1, r3 80092de: 2900 cmp r1, #0 80092e0: d146 bne.n 8009370 <__udivmoddi4+0x14c> 80092e2: 4573 cmp r3, lr 80092e4: d302 bcc.n 80092ec <__udivmoddi4+0xc8> 80092e6: 4282 cmp r2, r0 80092e8: f200 8108 bhi.w 80094fc <__udivmoddi4+0x2d8> 80092ec: 1a84 subs r4, r0, r2 80092ee: eb6e 0203 sbc.w r2, lr, r3 80092f2: 2001 movs r0, #1 80092f4: 4690 mov r8, r2 80092f6: 2d00 cmp r5, #0 80092f8: d0e5 beq.n 80092c6 <__udivmoddi4+0xa2> 80092fa: e9c5 4800 strd r4, r8, [r5] 80092fe: e7e2 b.n 80092c6 <__udivmoddi4+0xa2> 8009300: 2a00 cmp r2, #0 8009302: f000 8091 beq.w 8009428 <__udivmoddi4+0x204> 8009306: fab2 f682 clz r6, r2 800930a: 2e00 cmp r6, #0 800930c: f040 80a5 bne.w 800945a <__udivmoddi4+0x236> 8009310: 1a8a subs r2, r1, r2 8009312: 2101 movs r1, #1 8009314: 0c03 lsrs r3, r0, #16 8009316: ea4f 4e17 mov.w lr, r7, lsr #16 800931a: b280 uxth r0, r0 800931c: b2bc uxth r4, r7 800931e: fbb2 fcfe udiv ip, r2, lr 8009322: fb0e 221c mls r2, lr, ip, r2 8009326: ea43 4302 orr.w r3, r3, r2, lsl #16 800932a: fb04 f20c mul.w r2, r4, ip 800932e: 429a cmp r2, r3 8009330: d907 bls.n 8009342 <__udivmoddi4+0x11e> 8009332: 18fb adds r3, r7, r3 8009334: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8009338: d202 bcs.n 8009340 <__udivmoddi4+0x11c> 800933a: 429a cmp r2, r3 800933c: f200 80e3 bhi.w 8009506 <__udivmoddi4+0x2e2> 8009340: 46c4 mov ip, r8 8009342: 1a9b subs r3, r3, r2 8009344: fbb3 f2fe udiv r2, r3, lr 8009348: fb0e 3312 mls r3, lr, r2, r3 800934c: fb02 f404 mul.w r4, r2, r4 8009350: ea40 4303 orr.w r3, r0, r3, lsl #16 8009354: 429c cmp r4, r3 8009356: d907 bls.n 8009368 <__udivmoddi4+0x144> 8009358: 18fb adds r3, r7, r3 800935a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800935e: d202 bcs.n 8009366 <__udivmoddi4+0x142> 8009360: 429c cmp r4, r3 8009362: f200 80cd bhi.w 8009500 <__udivmoddi4+0x2dc> 8009366: 4602 mov r2, r0 8009368: 1b1b subs r3, r3, r4 800936a: ea42 400c orr.w r0, r2, ip, lsl #16 800936e: e7a5 b.n 80092bc <__udivmoddi4+0x98> 8009370: f1c1 0620 rsb r6, r1, #32 8009374: 408b lsls r3, r1 8009376: fa22 f706 lsr.w r7, r2, r6 800937a: 431f orrs r7, r3 800937c: fa2e fa06 lsr.w sl, lr, r6 8009380: ea4f 4917 mov.w r9, r7, lsr #16 8009384: fbba f8f9 udiv r8, sl, r9 8009388: fa0e fe01 lsl.w lr, lr, r1 800938c: fa20 f306 lsr.w r3, r0, r6 8009390: fb09 aa18 mls sl, r9, r8, sl 8009394: fa1f fc87 uxth.w ip, r7 8009398: ea43 030e orr.w r3, r3, lr 800939c: fa00 fe01 lsl.w lr, r0, r1 80093a0: fb08 f00c mul.w r0, r8, ip 80093a4: 0c1c lsrs r4, r3, #16 80093a6: ea44 440a orr.w r4, r4, sl, lsl #16 80093aa: 42a0 cmp r0, r4 80093ac: fa02 f201 lsl.w r2, r2, r1 80093b0: d90a bls.n 80093c8 <__udivmoddi4+0x1a4> 80093b2: 193c adds r4, r7, r4 80093b4: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff 80093b8: f080 809e bcs.w 80094f8 <__udivmoddi4+0x2d4> 80093bc: 42a0 cmp r0, r4 80093be: f240 809b bls.w 80094f8 <__udivmoddi4+0x2d4> 80093c2: f1a8 0802 sub.w r8, r8, #2 80093c6: 443c add r4, r7 80093c8: 1a24 subs r4, r4, r0 80093ca: b298 uxth r0, r3 80093cc: fbb4 f3f9 udiv r3, r4, r9 80093d0: fb09 4413 mls r4, r9, r3, r4 80093d4: fb03 fc0c mul.w ip, r3, ip 80093d8: ea40 4404 orr.w r4, r0, r4, lsl #16 80093dc: 45a4 cmp ip, r4 80093de: d909 bls.n 80093f4 <__udivmoddi4+0x1d0> 80093e0: 193c adds r4, r7, r4 80093e2: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 80093e6: f080 8085 bcs.w 80094f4 <__udivmoddi4+0x2d0> 80093ea: 45a4 cmp ip, r4 80093ec: f240 8082 bls.w 80094f4 <__udivmoddi4+0x2d0> 80093f0: 3b02 subs r3, #2 80093f2: 443c add r4, r7 80093f4: ea43 4008 orr.w r0, r3, r8, lsl #16 80093f8: eba4 040c sub.w r4, r4, ip 80093fc: fba0 8c02 umull r8, ip, r0, r2 8009400: 4564 cmp r4, ip 8009402: 4643 mov r3, r8 8009404: 46e1 mov r9, ip 8009406: d364 bcc.n 80094d2 <__udivmoddi4+0x2ae> 8009408: d061 beq.n 80094ce <__udivmoddi4+0x2aa> 800940a: b15d cbz r5, 8009424 <__udivmoddi4+0x200> 800940c: ebbe 0203 subs.w r2, lr, r3 8009410: eb64 0409 sbc.w r4, r4, r9 8009414: fa04 f606 lsl.w r6, r4, r6 8009418: fa22 f301 lsr.w r3, r2, r1 800941c: 431e orrs r6, r3 800941e: 40cc lsrs r4, r1 8009420: e9c5 6400 strd r6, r4, [r5] 8009424: 2100 movs r1, #0 8009426: e74e b.n 80092c6 <__udivmoddi4+0xa2> 8009428: fbb1 fcf2 udiv ip, r1, r2 800942c: 0c01 lsrs r1, r0, #16 800942e: ea41 410e orr.w r1, r1, lr, lsl #16 8009432: b280 uxth r0, r0 8009434: ea40 4201 orr.w r2, r0, r1, lsl #16 8009438: 463b mov r3, r7 800943a: fbb1 f1f7 udiv r1, r1, r7 800943e: 4638 mov r0, r7 8009440: 463c mov r4, r7 8009442: 46b8 mov r8, r7 8009444: 46be mov lr, r7 8009446: 2620 movs r6, #32 8009448: eba2 0208 sub.w r2, r2, r8 800944c: ea41 410c orr.w r1, r1, ip, lsl #16 8009450: e765 b.n 800931e <__udivmoddi4+0xfa> 8009452: 4601 mov r1, r0 8009454: e717 b.n 8009286 <__udivmoddi4+0x62> 8009456: 4610 mov r0, r2 8009458: e72b b.n 80092b2 <__udivmoddi4+0x8e> 800945a: f1c6 0120 rsb r1, r6, #32 800945e: fa2e fc01 lsr.w ip, lr, r1 8009462: 40b7 lsls r7, r6 8009464: fa0e fe06 lsl.w lr, lr, r6 8009468: fa20 f101 lsr.w r1, r0, r1 800946c: ea41 010e orr.w r1, r1, lr 8009470: ea4f 4e17 mov.w lr, r7, lsr #16 8009474: fbbc f8fe udiv r8, ip, lr 8009478: b2bc uxth r4, r7 800947a: fb0e cc18 mls ip, lr, r8, ip 800947e: fb08 f904 mul.w r9, r8, r4 8009482: 0c0a lsrs r2, r1, #16 8009484: ea42 420c orr.w r2, r2, ip, lsl #16 8009488: 40b0 lsls r0, r6 800948a: 4591 cmp r9, r2 800948c: ea4f 4310 mov.w r3, r0, lsr #16 8009490: b280 uxth r0, r0 8009492: d93e bls.n 8009512 <__udivmoddi4+0x2ee> 8009494: 18ba adds r2, r7, r2 8009496: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 800949a: d201 bcs.n 80094a0 <__udivmoddi4+0x27c> 800949c: 4591 cmp r9, r2 800949e: d81f bhi.n 80094e0 <__udivmoddi4+0x2bc> 80094a0: eba2 0209 sub.w r2, r2, r9 80094a4: fbb2 f9fe udiv r9, r2, lr 80094a8: fb09 f804 mul.w r8, r9, r4 80094ac: fb0e 2a19 mls sl, lr, r9, r2 80094b0: b28a uxth r2, r1 80094b2: ea42 420a orr.w r2, r2, sl, lsl #16 80094b6: 4542 cmp r2, r8 80094b8: d229 bcs.n 800950e <__udivmoddi4+0x2ea> 80094ba: 18ba adds r2, r7, r2 80094bc: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80094c0: d2c2 bcs.n 8009448 <__udivmoddi4+0x224> 80094c2: 4542 cmp r2, r8 80094c4: d2c0 bcs.n 8009448 <__udivmoddi4+0x224> 80094c6: f1a9 0102 sub.w r1, r9, #2 80094ca: 443a add r2, r7 80094cc: e7bc b.n 8009448 <__udivmoddi4+0x224> 80094ce: 45c6 cmp lr, r8 80094d0: d29b bcs.n 800940a <__udivmoddi4+0x1e6> 80094d2: ebb8 0302 subs.w r3, r8, r2 80094d6: eb6c 0c07 sbc.w ip, ip, r7 80094da: 3801 subs r0, #1 80094dc: 46e1 mov r9, ip 80094de: e794 b.n 800940a <__udivmoddi4+0x1e6> 80094e0: eba7 0909 sub.w r9, r7, r9 80094e4: 444a add r2, r9 80094e6: fbb2 f9fe udiv r9, r2, lr 80094ea: f1a8 0c02 sub.w ip, r8, #2 80094ee: fb09 f804 mul.w r8, r9, r4 80094f2: e7db b.n 80094ac <__udivmoddi4+0x288> 80094f4: 4603 mov r3, r0 80094f6: e77d b.n 80093f4 <__udivmoddi4+0x1d0> 80094f8: 46d0 mov r8, sl 80094fa: e765 b.n 80093c8 <__udivmoddi4+0x1a4> 80094fc: 4608 mov r0, r1 80094fe: e6fa b.n 80092f6 <__udivmoddi4+0xd2> 8009500: 443b add r3, r7 8009502: 3a02 subs r2, #2 8009504: e730 b.n 8009368 <__udivmoddi4+0x144> 8009506: f1ac 0c02 sub.w ip, ip, #2 800950a: 443b add r3, r7 800950c: e719 b.n 8009342 <__udivmoddi4+0x11e> 800950e: 4649 mov r1, r9 8009510: e79a b.n 8009448 <__udivmoddi4+0x224> 8009512: eba2 0209 sub.w r2, r2, r9 8009516: fbb2 f9fe udiv r9, r2, lr 800951a: 46c4 mov ip, r8 800951c: fb09 f804 mul.w r8, r9, r4 8009520: e7c4 b.n 80094ac <__udivmoddi4+0x288> 8009522: bf00 nop 08009524 <__aeabi_idiv0>: 8009524: 4770 bx lr 8009526: bf00 nop 08009528 : static volatile uint16_t adc_dma_raw[6]; volatile ADC_ScanData_t adc_data = {0}; static volatile uint8_t adc_scan_data_ready = 0u; void ADC_ScanStart(void) { 8009528: b580 push {r7, lr} 800952a: af00 add r7, sp, #0 if (HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc_dma_raw, 6u) != HAL_OK) 800952c: 2206 movs r2, #6 800952e: 4905 ldr r1, [pc, #20] @ (8009544 ) 8009530: 4805 ldr r0, [pc, #20] @ (8009548 ) 8009532: f005 fa2f bl 800e994 8009536: 4603 mov r3, r0 8009538: 2b00 cmp r3, #0 800953a: d001 beq.n 8009540 { Error_Handler(); 800953c: f001 fbca bl 800acd4 } } 8009540: bf00 nop 8009542: bd80 pop {r7, pc} 8009544: 20000274 .word 0x20000274 8009548: 20000290 .word 0x20000290 0800954c : ISR_FAST void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { if (hadc->Instance != ADC1) 800954c: 4b0e ldr r3, [pc, #56] @ (8009588 ) 800954e: 6802 ldr r2, [r0, #0] 8009550: 429a cmp r2, r3 8009552: d118 bne.n 8009586 adc_data.cp_raw = adc_dma_raw[1]; adc_data.ntc1_raw = adc_dma_raw[2]; adc_data.ntc2_raw = adc_dma_raw[3]; adc_data.temp_sensor_raw = adc_dma_raw[4]; adc_data.vrefint_raw = adc_dma_raw[5]; adc_scan_data_ready = 1u; 8009554: f04f 0c01 mov.w ip, #1 adc_data.in3_raw = adc_dma_raw[0]; 8009558: 4a0c ldr r2, [pc, #48] @ (800958c ) 800955a: 4b0d ldr r3, [pc, #52] @ (8009590 ) 800955c: 8811 ldrh r1, [r2, #0] adc_scan_data_ready = 1u; 800955e: 480d ldr r0, [pc, #52] @ (8009594 ) adc_data.in3_raw = adc_dma_raw[0]; 8009560: b289 uxth r1, r1 8009562: 8019 strh r1, [r3, #0] adc_data.cp_raw = adc_dma_raw[1]; 8009564: 8851 ldrh r1, [r2, #2] 8009566: b289 uxth r1, r1 8009568: 8059 strh r1, [r3, #2] adc_data.ntc1_raw = adc_dma_raw[2]; 800956a: 8891 ldrh r1, [r2, #4] 800956c: b289 uxth r1, r1 800956e: 8099 strh r1, [r3, #4] adc_data.ntc2_raw = adc_dma_raw[3]; 8009570: 88d1 ldrh r1, [r2, #6] 8009572: b289 uxth r1, r1 8009574: 80d9 strh r1, [r3, #6] adc_data.temp_sensor_raw = adc_dma_raw[4]; 8009576: 8911 ldrh r1, [r2, #8] 8009578: b289 uxth r1, r1 800957a: 8119 strh r1, [r3, #8] adc_data.vrefint_raw = adc_dma_raw[5]; 800957c: 8952 ldrh r2, [r2, #10] 800957e: b292 uxth r2, r2 8009580: 815a strh r2, [r3, #10] adc_scan_data_ready = 1u; 8009582: f880 c000 strb.w ip, [r0] } 8009586: 4770 bx lr 8009588: 40012400 .word 0x40012400 800958c: 20000274 .word 0x20000274 8009590: 20000280 .word 0x20000280 8009594: 2000028c .word 0x2000028c 08009598 : ADC_HandleTypeDef hadc1; DMA_HandleTypeDef hdma_adc1; /* ADC1 init function */ void MX_ADC1_Init(void) { 8009598: b580 push {r7, lr} 800959a: b084 sub sp, #16 800959c: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 800959e: 1d3b adds r3, r7, #4 80095a0: 2200 movs r2, #0 80095a2: 601a str r2, [r3, #0] 80095a4: 605a str r2, [r3, #4] 80095a6: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 80095a8: 4b3c ldr r3, [pc, #240] @ (800969c ) 80095aa: 4a3d ldr r2, [pc, #244] @ (80096a0 ) 80095ac: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 80095ae: 4b3b ldr r3, [pc, #236] @ (800969c ) 80095b0: f44f 7280 mov.w r2, #256 @ 0x100 80095b4: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = DISABLE; 80095b6: 4b39 ldr r3, [pc, #228] @ (800969c ) 80095b8: 2200 movs r2, #0 80095ba: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 80095bc: 4b37 ldr r3, [pc, #220] @ (800969c ) 80095be: 2200 movs r2, #0 80095c0: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T3_TRGO; 80095c2: 4b36 ldr r3, [pc, #216] @ (800969c ) 80095c4: f44f 2200 mov.w r2, #524288 @ 0x80000 80095c8: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80095ca: 4b34 ldr r3, [pc, #208] @ (800969c ) 80095cc: 2200 movs r2, #0 80095ce: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 6; 80095d0: 4b32 ldr r3, [pc, #200] @ (800969c ) 80095d2: 2206 movs r2, #6 80095d4: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 80095d6: 4831 ldr r0, [pc, #196] @ (800969c ) 80095d8: f005 f904 bl 800e7e4 80095dc: 4603 mov r3, r0 80095de: 2b00 cmp r3, #0 80095e0: d001 beq.n 80095e6 { Error_Handler(); 80095e2: f001 fb77 bl 800acd4 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 80095e6: 2303 movs r3, #3 80095e8: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 80095ea: 2301 movs r3, #1 80095ec: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_41CYCLES_5; 80095ee: 2304 movs r3, #4 80095f0: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80095f2: 1d3b adds r3, r7, #4 80095f4: 4619 mov r1, r3 80095f6: 4829 ldr r0, [pc, #164] @ (800969c ) 80095f8: f005 fb84 bl 800ed04 80095fc: 4603 mov r3, r0 80095fe: 2b00 cmp r3, #0 8009600: d001 beq.n 8009606 { Error_Handler(); 8009602: f001 fb67 bl 800acd4 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8009606: 2304 movs r3, #4 8009608: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 800960a: 2302 movs r3, #2 800960c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800960e: 1d3b adds r3, r7, #4 8009610: 4619 mov r1, r3 8009612: 4822 ldr r0, [pc, #136] @ (800969c ) 8009614: f005 fb76 bl 800ed04 8009618: 4603 mov r3, r0 800961a: 2b00 cmp r3, #0 800961c: d001 beq.n 8009622 { Error_Handler(); 800961e: f001 fb59 bl 800acd4 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8009622: 2308 movs r3, #8 8009624: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8009626: 2303 movs r3, #3 8009628: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800962a: 1d3b adds r3, r7, #4 800962c: 4619 mov r1, r3 800962e: 481b ldr r0, [pc, #108] @ (800969c ) 8009630: f005 fb68 bl 800ed04 8009634: 4603 mov r3, r0 8009636: 2b00 cmp r3, #0 8009638: d001 beq.n 800963e { Error_Handler(); 800963a: f001 fb4b bl 800acd4 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_9; 800963e: 2309 movs r3, #9 8009640: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_4; 8009642: 2304 movs r3, #4 8009644: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8009646: 1d3b adds r3, r7, #4 8009648: 4619 mov r1, r3 800964a: 4814 ldr r0, [pc, #80] @ (800969c ) 800964c: f005 fb5a bl 800ed04 8009650: 4603 mov r3, r0 8009652: 2b00 cmp r3, #0 8009654: d001 beq.n 800965a { Error_Handler(); 8009656: f001 fb3d bl 800acd4 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; 800965a: 2310 movs r3, #16 800965c: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_5; 800965e: 2305 movs r3, #5 8009660: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8009662: 1d3b adds r3, r7, #4 8009664: 4619 mov r1, r3 8009666: 480d ldr r0, [pc, #52] @ (800969c ) 8009668: f005 fb4c bl 800ed04 800966c: 4603 mov r3, r0 800966e: 2b00 cmp r3, #0 8009670: d001 beq.n 8009676 { Error_Handler(); 8009672: f001 fb2f bl 800acd4 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; 8009676: 2311 movs r3, #17 8009678: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_6; 800967a: 2306 movs r3, #6 800967c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800967e: 1d3b adds r3, r7, #4 8009680: 4619 mov r1, r3 8009682: 4806 ldr r0, [pc, #24] @ (800969c ) 8009684: f005 fb3e bl 800ed04 8009688: 4603 mov r3, r0 800968a: 2b00 cmp r3, #0 800968c: d001 beq.n 8009692 { Error_Handler(); 800968e: f001 fb21 bl 800acd4 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 8009692: bf00 nop 8009694: 3710 adds r7, #16 8009696: 46bd mov sp, r7 8009698: bd80 pop {r7, pc} 800969a: bf00 nop 800969c: 20000290 .word 0x20000290 80096a0: 40012400 .word 0x40012400 080096a4 : void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 80096a4: b580 push {r7, lr} 80096a6: b08a sub sp, #40 @ 0x28 80096a8: af00 add r7, sp, #0 80096aa: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80096ac: f107 0318 add.w r3, r7, #24 80096b0: 2200 movs r2, #0 80096b2: 601a str r2, [r3, #0] 80096b4: 605a str r2, [r3, #4] 80096b6: 609a str r2, [r3, #8] 80096b8: 60da str r2, [r3, #12] if(adcHandle->Instance==ADC1) 80096ba: 687b ldr r3, [r7, #4] 80096bc: 681b ldr r3, [r3, #0] 80096be: 4a38 ldr r2, [pc, #224] @ (80097a0 ) 80096c0: 4293 cmp r3, r2 80096c2: d168 bne.n 8009796 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 80096c4: 4b37 ldr r3, [pc, #220] @ (80097a4 ) 80096c6: 699b ldr r3, [r3, #24] 80096c8: 4a36 ldr r2, [pc, #216] @ (80097a4 ) 80096ca: f443 7300 orr.w r3, r3, #512 @ 0x200 80096ce: 6193 str r3, [r2, #24] 80096d0: 4b34 ldr r3, [pc, #208] @ (80097a4 ) 80096d2: 699b ldr r3, [r3, #24] 80096d4: f403 7300 and.w r3, r3, #512 @ 0x200 80096d8: 617b str r3, [r7, #20] 80096da: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 80096dc: 4b31 ldr r3, [pc, #196] @ (80097a4 ) 80096de: 699b ldr r3, [r3, #24] 80096e0: 4a30 ldr r2, [pc, #192] @ (80097a4 ) 80096e2: f043 0304 orr.w r3, r3, #4 80096e6: 6193 str r3, [r2, #24] 80096e8: 4b2e ldr r3, [pc, #184] @ (80097a4 ) 80096ea: 699b ldr r3, [r3, #24] 80096ec: f003 0304 and.w r3, r3, #4 80096f0: 613b str r3, [r7, #16] 80096f2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80096f4: 4b2b ldr r3, [pc, #172] @ (80097a4 ) 80096f6: 699b ldr r3, [r3, #24] 80096f8: 4a2a ldr r2, [pc, #168] @ (80097a4 ) 80096fa: f043 0308 orr.w r3, r3, #8 80096fe: 6193 str r3, [r2, #24] 8009700: 4b28 ldr r3, [pc, #160] @ (80097a4 ) 8009702: 699b ldr r3, [r3, #24] 8009704: f003 0308 and.w r3, r3, #8 8009708: 60fb str r3, [r7, #12] 800970a: 68fb ldr r3, [r7, #12] PA3 ------> ADC1_IN3 PA4 ------> ADC1_IN4 PB0 ------> ADC1_IN8 PB1 ------> ADC1_IN9 */ GPIO_InitStruct.Pin = GPIO_PIN_3|CP_ADC_Pin; 800970c: 2318 movs r3, #24 800970e: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009710: 2303 movs r3, #3 8009712: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8009714: f107 0318 add.w r3, r7, #24 8009718: 4619 mov r1, r3 800971a: 4823 ldr r0, [pc, #140] @ (80097a8 ) 800971c: f007 fa30 bl 8010b80 GPIO_InitStruct.Pin = ADC_NTC1_Pin|ADC_NTC2_Pin; 8009720: 2303 movs r3, #3 8009722: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009724: 2303 movs r3, #3 8009726: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009728: f107 0318 add.w r3, r7, #24 800972c: 4619 mov r1, r3 800972e: 481f ldr r0, [pc, #124] @ (80097ac ) 8009730: f007 fa26 bl 8010b80 /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; 8009734: 4b1e ldr r3, [pc, #120] @ (80097b0 ) 8009736: 4a1f ldr r2, [pc, #124] @ (80097b4 ) 8009738: 601a str r2, [r3, #0] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 800973a: 4b1d ldr r3, [pc, #116] @ (80097b0 ) 800973c: 2200 movs r2, #0 800973e: 605a str r2, [r3, #4] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8009740: 4b1b ldr r3, [pc, #108] @ (80097b0 ) 8009742: 2200 movs r2, #0 8009744: 609a str r2, [r3, #8] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8009746: 4b1a ldr r3, [pc, #104] @ (80097b0 ) 8009748: 2280 movs r2, #128 @ 0x80 800974a: 60da str r2, [r3, #12] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 800974c: 4b18 ldr r3, [pc, #96] @ (80097b0 ) 800974e: f44f 7280 mov.w r2, #256 @ 0x100 8009752: 611a str r2, [r3, #16] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8009754: 4b16 ldr r3, [pc, #88] @ (80097b0 ) 8009756: f44f 6280 mov.w r2, #1024 @ 0x400 800975a: 615a str r2, [r3, #20] hdma_adc1.Init.Mode = DMA_CIRCULAR; 800975c: 4b14 ldr r3, [pc, #80] @ (80097b0 ) 800975e: 2220 movs r2, #32 8009760: 619a str r2, [r3, #24] hdma_adc1.Init.Priority = DMA_PRIORITY_MEDIUM; 8009762: 4b13 ldr r3, [pc, #76] @ (80097b0 ) 8009764: f44f 5280 mov.w r2, #4096 @ 0x1000 8009768: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 800976a: 4811 ldr r0, [pc, #68] @ (80097b0 ) 800976c: f006 fd7a bl 8010264 8009770: 4603 mov r3, r0 8009772: 2b00 cmp r3, #0 8009774: d001 beq.n 800977a { Error_Handler(); 8009776: f001 faad bl 800acd4 } __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1); 800977a: 687b ldr r3, [r7, #4] 800977c: 4a0c ldr r2, [pc, #48] @ (80097b0 ) 800977e: 621a str r2, [r3, #32] 8009780: 4a0b ldr r2, [pc, #44] @ (80097b0 ) 8009782: 687b ldr r3, [r7, #4] 8009784: 6253 str r3, [r2, #36] @ 0x24 /* ADC1 interrupt Init */ HAL_NVIC_SetPriority(ADC1_2_IRQn, 7, 0); 8009786: 2200 movs r2, #0 8009788: 2107 movs r1, #7 800978a: 2012 movs r0, #18 800978c: f006 fd17 bl 80101be HAL_NVIC_EnableIRQ(ADC1_2_IRQn); 8009790: 2012 movs r0, #18 8009792: f006 fd30 bl 80101f6 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8009796: bf00 nop 8009798: 3728 adds r7, #40 @ 0x28 800979a: 46bd mov sp, r7 800979c: bd80 pop {r7, pc} 800979e: bf00 nop 80097a0: 40012400 .word 0x40012400 80097a4: 40021000 .word 0x40021000 80097a8: 40010800 .word 0x40010800 80097ac: 40010c00 .word 0x40010c00 80097b0: 200002c0 .word 0x200002c0 80097b4: 40020008 .word 0x40020008 080097b8 : uint8_t RELAY_State[RELAY_COUNT]; static volatile uint8_t adc_lock = 0; static SMAFilter_t conn_temp_adc_filter[2]; void RELAY_Write(relay_t num, uint8_t state){ 80097b8: b580 push {r7, lr} 80097ba: b082 sub sp, #8 80097bc: af00 add r7, sp, #0 80097be: 4603 mov r3, r0 80097c0: 460a mov r2, r1 80097c2: 71fb strb r3, [r7, #7] 80097c4: 4613 mov r3, r2 80097c6: 71bb strb r3, [r7, #6] switch (num) { 80097c8: 79fb ldrb r3, [r7, #7] 80097ca: 2b07 cmp r3, #7 80097cc: d850 bhi.n 8009870 80097ce: a201 add r2, pc, #4 @ (adr r2, 80097d4 ) 80097d0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80097d4: 080097f5 .word 0x080097f5 80097d8: 08009805 .word 0x08009805 80097dc: 08009815 .word 0x08009815 80097e0: 08009825 .word 0x08009825 80097e4: 08009835 .word 0x08009835 80097e8: 08009845 .word 0x08009845 80097ec: 08009853 .word 0x08009853 80097f0: 08009863 .word 0x08009863 case RELAY_AUX0: HAL_GPIO_WritePin(RELAY1_GPIO_Port, RELAY1_Pin, state); 80097f4: 79bb ldrb r3, [r7, #6] 80097f6: 461a mov r2, r3 80097f8: f44f 7180 mov.w r1, #256 @ 0x100 80097fc: 4821 ldr r0, [pc, #132] @ (8009884 ) 80097fe: f007 fb5a bl 8010eb6 break; 8009802: e036 b.n 8009872 case RELAY_AUX1: HAL_GPIO_WritePin(RELAY2_GPIO_Port, RELAY2_Pin, state); 8009804: 79bb ldrb r3, [r7, #6] 8009806: 461a mov r2, r3 8009808: f44f 7100 mov.w r1, #512 @ 0x200 800980c: 481d ldr r0, [pc, #116] @ (8009884 ) 800980e: f007 fb52 bl 8010eb6 break; 8009812: e02e b.n 8009872 case RELAY3: HAL_GPIO_WritePin(RELAY3_GPIO_Port, RELAY3_Pin, state); 8009814: 79bb ldrb r3, [r7, #6] 8009816: 461a mov r2, r3 8009818: f44f 6180 mov.w r1, #1024 @ 0x400 800981c: 4819 ldr r0, [pc, #100] @ (8009884 ) 800981e: f007 fb4a bl 8010eb6 break; 8009822: e026 b.n 8009872 case RELAY_DC: HAL_GPIO_WritePin(RELAY4_GPIO_Port, RELAY4_Pin, state); 8009824: 79bb ldrb r3, [r7, #6] 8009826: 461a mov r2, r3 8009828: f44f 6100 mov.w r1, #2048 @ 0x800 800982c: 4815 ldr r0, [pc, #84] @ (8009884 ) 800982e: f007 fb42 bl 8010eb6 break; 8009832: e01e b.n 8009872 case RELAY_AC: HAL_GPIO_WritePin(RELAY5_GPIO_Port, RELAY5_Pin, state); 8009834: 79bb ldrb r3, [r7, #6] 8009836: 461a mov r2, r3 8009838: f44f 5180 mov.w r1, #4096 @ 0x1000 800983c: 4811 ldr r0, [pc, #68] @ (8009884 ) 800983e: f007 fb3a bl 8010eb6 break; 8009842: e016 b.n 8009872 case RELAY_CP: HAL_GPIO_WritePin(RELAY_CP_GPIO_Port, RELAY_CP_Pin, state); 8009844: 79bb ldrb r3, [r7, #6] 8009846: 461a mov r2, r3 8009848: 2108 movs r1, #8 800984a: 480f ldr r0, [pc, #60] @ (8009888 ) 800984c: f007 fb33 bl 8010eb6 break; 8009850: e00f b.n 8009872 case RELAY_CC: HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, state); 8009852: 79bb ldrb r3, [r7, #6] 8009854: 461a mov r2, r3 8009856: f44f 4100 mov.w r1, #32768 @ 0x8000 800985a: 480c ldr r0, [pc, #48] @ (800988c ) 800985c: f007 fb2b bl 8010eb6 break; 8009860: e007 b.n 8009872 case RELAY_DC1: HAL_GPIO_WritePin(RELAY_DC_GPIO_Port, RELAY_DC_Pin, state); 8009862: 79bb ldrb r3, [r7, #6] 8009864: 461a mov r2, r3 8009866: 2108 movs r1, #8 8009868: 4809 ldr r0, [pc, #36] @ (8009890 ) 800986a: f007 fb24 bl 8010eb6 break; 800986e: e000 b.n 8009872 default: break; 8009870: bf00 nop } RELAY_State[num] = state; 8009872: 79fb ldrb r3, [r7, #7] 8009874: 4907 ldr r1, [pc, #28] @ (8009894 ) 8009876: 79ba ldrb r2, [r7, #6] 8009878: 54ca strb r2, [r1, r3] } 800987a: bf00 nop 800987c: 3708 adds r7, #8 800987e: 46bd mov sp, r7 8009880: bd80 pop {r7, pc} 8009882: bf00 nop 8009884: 40011800 .word 0x40011800 8009888: 40011000 .word 0x40011000 800988c: 40010800 .word 0x40010800 8009890: 40011400 .word 0x40011400 8009894: 20000304 .word 0x20000304 08009898 : uint8_t RELAY_Read(relay_t num){ 8009898: b480 push {r7} 800989a: b083 sub sp, #12 800989c: af00 add r7, sp, #0 800989e: 4603 mov r3, r0 80098a0: 71fb strb r3, [r7, #7] return RELAY_State[num]; 80098a2: 79fb ldrb r3, [r7, #7] 80098a4: 4a03 ldr r2, [pc, #12] @ (80098b4 ) 80098a6: 5cd3 ldrb r3, [r2, r3] } 80098a8: 4618 mov r0, r3 80098aa: 370c adds r7, #12 80098ac: 46bd mov sp, r7 80098ae: bc80 pop {r7} 80098b0: 4770 bx lr 80098b2: bf00 nop 80098b4: 20000304 .word 0x20000304 080098b8 : uint8_t IN_ReadInput(inputNum_t input_n){ 80098b8: b580 push {r7, lr} 80098ba: b082 sub sp, #8 80098bc: af00 add r7, sp, #0 80098be: 4603 mov r3, r0 80098c0: 71fb strb r3, [r7, #7] switch(input_n){ 80098c2: 79fb ldrb r3, [r7, #7] 80098c4: 2b06 cmp r3, #6 80098c6: d83b bhi.n 8009940 80098c8: a201 add r2, pc, #4 @ (adr r2, 80098d0 ) 80098ca: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80098ce: bf00 nop 80098d0: 080098ed .word 0x080098ed 80098d4: 080098f9 .word 0x080098f9 80098d8: 08009905 .word 0x08009905 80098dc: 08009911 .word 0x08009911 80098e0: 0800991d .word 0x0800991d 80098e4: 08009929 .word 0x08009929 80098e8: 08009935 .word 0x08009935 case IN_SW0: return HAL_GPIO_ReadPin(IN_SW0_GPIO_Port, IN_SW0_Pin); 80098ec: 2102 movs r1, #2 80098ee: 4817 ldr r0, [pc, #92] @ (800994c ) 80098f0: f007 faca bl 8010e88 80098f4: 4603 mov r3, r0 80098f6: e024 b.n 8009942 case IN_SW1: return HAL_GPIO_ReadPin(IN_SW1_GPIO_Port, IN_SW1_Pin); 80098f8: 2104 movs r1, #4 80098fa: 4814 ldr r0, [pc, #80] @ (800994c ) 80098fc: f007 fac4 bl 8010e88 8009900: 4603 mov r3, r0 8009902: e01e b.n 8009942 case IN0: return HAL_GPIO_ReadPin(IN0_GPIO_Port, IN0_Pin); 8009904: 2180 movs r1, #128 @ 0x80 8009906: 4812 ldr r0, [pc, #72] @ (8009950 ) 8009908: f007 fabe bl 8010e88 800990c: 4603 mov r3, r0 800990e: e018 b.n 8009942 case IN_ESTOP: return HAL_GPIO_ReadPin(IN_ESTOP_GPIO_Port, IN_ESTOP_Pin); 8009910: 2180 movs r1, #128 @ 0x80 8009912: 4810 ldr r0, [pc, #64] @ (8009954 ) 8009914: f007 fab8 bl 8010e88 8009918: 4603 mov r3, r0 800991a: e012 b.n 8009942 case IN_FB1: return HAL_GPIO_ReadPin(IN_FB1_GPIO_Port, IN_FB1_Pin); 800991c: 2110 movs r1, #16 800991e: 480e ldr r0, [pc, #56] @ (8009958 ) 8009920: f007 fab2 bl 8010e88 8009924: 4603 mov r3, r0 8009926: e00c b.n 8009942 case IN_CONT_FB_DC: return HAL_GPIO_ReadPin(IN_FB2_GPIO_Port, IN_FB2_Pin); 8009928: 2108 movs r1, #8 800992a: 480b ldr r0, [pc, #44] @ (8009958 ) 800992c: f007 faac bl 8010e88 8009930: 4603 mov r3, r0 8009932: e006 b.n 8009942 case ISO_IN: return HAL_GPIO_ReadPin(ISO_IN_GPIO_Port, ISO_IN_Pin); 8009934: 2102 movs r1, #2 8009936: 4806 ldr r0, [pc, #24] @ (8009950 ) 8009938: f007 faa6 bl 8010e88 800993c: 4603 mov r3, r0 800993e: e000 b.n 8009942 default: return 0; 8009940: 2300 movs r3, #0 } } 8009942: 4618 mov r0, r3 8009944: 3708 adds r7, #8 8009946: 46bd mov sp, r7 8009948: bd80 pop {r7, pc} 800994a: bf00 nop 800994c: 40010800 .word 0x40010800 8009950: 40011800 .word 0x40011800 8009954: 40011400 .word 0x40011400 8009958: 40010c00 .word 0x40010c00 0800995c : /** * @brief Force PC12 (HEATER) as GPIO output via CRH/ODR, overriding UART5 MspInit. * CubeMX assigns PC12 to UART5_TX; on the board it drives the heater relay. */ static void Heater_PinForceOutput(void) { 800995c: b480 push {r7} 800995e: b083 sub sp, #12 8009960: af00 add r7, sp, #0 const uint32_t pin_cfg = GPIO_SPEED_FREQ_LOW; /* MODE=10, CNF=00: GP output PP, 2 MHz */ 8009962: 2302 movs r3, #2 8009964: 607b str r3, [r7, #4] __HAL_RCC_GPIOC_CLK_ENABLE(); 8009966: 4b0f ldr r3, [pc, #60] @ (80099a4 ) 8009968: 699b ldr r3, [r3, #24] 800996a: 4a0e ldr r2, [pc, #56] @ (80099a4 ) 800996c: f043 0310 orr.w r3, r3, #16 8009970: 6193 str r3, [r2, #24] 8009972: 4b0c ldr r3, [pc, #48] @ (80099a4 ) 8009974: 699b ldr r3, [r3, #24] 8009976: f003 0310 and.w r3, r3, #16 800997a: 603b str r3, [r7, #0] 800997c: 683b ldr r3, [r7, #0] MODIFY_REG(HEATER_GPIO_Port->CRH, 800997e: 4b0a ldr r3, [pc, #40] @ (80099a8 ) 8009980: 685b ldr r3, [r3, #4] 8009982: f423 2270 bic.w r2, r3, #983040 @ 0xf0000 8009986: 687b ldr r3, [r7, #4] 8009988: 041b lsls r3, r3, #16 800998a: 4907 ldr r1, [pc, #28] @ (80099a8 ) 800998c: 4313 orrs r3, r2 800998e: 604b str r3, [r1, #4] (GPIO_CRH_MODE12 | GPIO_CRH_CNF12), (pin_cfg << GPIO_CRH_MODE12_Pos)); HEATER_GPIO_Port->BSRR = (uint32_t)HEATER_Pin << 16U; 8009990: 4b05 ldr r3, [pc, #20] @ (80099a8 ) 8009992: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8009996: 611a str r2, [r3, #16] } 8009998: bf00 nop 800999a: 370c adds r7, #12 800999c: 46bd mov sp, r7 800999e: bc80 pop {r7} 80099a0: 4770 bx lr 80099a2: bf00 nop 80099a4: 40021000 .word 0x40021000 80099a8: 40011000 .word 0x40011000 080099ac : void Init_Peripheral(){ 80099ac: b580 push {r7, lr} 80099ae: af00 add r7, sp, #0 Heater_PinForceOutput(); 80099b0: f7ff ffd4 bl 800995c HAL_GPIO_WritePin(HEATER_GPIO_Port, HEATER_Pin, GPIO_PIN_RESET); 80099b4: 2200 movs r2, #0 80099b6: f44f 5180 mov.w r1, #4096 @ 0x1000 80099ba: 4818 ldr r0, [pc, #96] @ (8009a1c ) 80099bc: f007 fa7b bl 8010eb6 HAL_ADCEx_Calibration_Start(&hadc1); 80099c0: 4817 ldr r0, [pc, #92] @ (8009a20 ) 80099c2: f005 fb99 bl 800f0f8 ADC_ScanStart(); 80099c6: f7ff fdaf bl 8009528 RELAY_Write(RELAY_AUX0, 0); 80099ca: 2100 movs r1, #0 80099cc: 2000 movs r0, #0 80099ce: f7ff fef3 bl 80097b8 RELAY_Write(RELAY_AUX1, 0); 80099d2: 2100 movs r1, #0 80099d4: 2001 movs r0, #1 80099d6: f7ff feef bl 80097b8 RELAY_Write(RELAY3, 0); 80099da: 2100 movs r1, #0 80099dc: 2002 movs r0, #2 80099de: f7ff feeb bl 80097b8 RELAY_Write(RELAY_DC, 0); 80099e2: 2100 movs r1, #0 80099e4: 2003 movs r0, #3 80099e6: f7ff fee7 bl 80097b8 RELAY_Write(RELAY_AC, 0); 80099ea: 2100 movs r1, #0 80099ec: 2004 movs r0, #4 80099ee: f7ff fee3 bl 80097b8 RELAY_Write(RELAY_CP, 0); 80099f2: 2100 movs r1, #0 80099f4: 2005 movs r0, #5 80099f6: f7ff fedf bl 80097b8 RELAY_Write(RELAY_CC, 0); 80099fa: 2100 movs r1, #0 80099fc: 2006 movs r0, #6 80099fe: f7ff fedb bl 80097b8 RELAY_Write(RELAY_DC1, 0); 8009a02: 2100 movs r1, #0 8009a04: 2007 movs r0, #7 8009a06: f7ff fed7 bl 80097b8 SMAFilter_Init(&conn_temp_adc_filter[0]); 8009a0a: 4806 ldr r0, [pc, #24] @ (8009a24 ) 8009a0c: f003 ff72 bl 800d8f4 SMAFilter_Init(&conn_temp_adc_filter[1]); 8009a10: 4805 ldr r0, [pc, #20] @ (8009a28 ) 8009a12: f003 ff6f bl 800d8f4 } 8009a16: bf00 nop 8009a18: bd80 pop {r7, pc} 8009a1a: bf00 nop 8009a1c: 40011000 .word 0x40011000 8009a20: 20000290 .word 0x20000290 8009a24: 2000030c .word 0x2000030c 8009a28: 20000334 .word 0x20000334 08009a2c : float pt1000_to_temperature(float resistance) { 8009a2c: b590 push {r4, r7, lr} 8009a2e: b087 sub sp, #28 8009a30: af00 add r7, sp, #0 8009a32: 6078 str r0, [r7, #4] // Константы для PT1000 const float R0 = 1000.0; // Сопротивление при 0 °C 8009a34: 4b0c ldr r3, [pc, #48] @ (8009a68 ) 8009a36: 617b str r3, [r7, #20] const float C_A = 3.9083E-3f; 8009a38: 4b0c ldr r3, [pc, #48] @ (8009a6c ) 8009a3a: 613b str r3, [r7, #16] float temperature = (resistance-R0) / ( R0 * C_A); 8009a3c: 6979 ldr r1, [r7, #20] 8009a3e: 6878 ldr r0, [r7, #4] 8009a40: f7ff f8e2 bl 8008c08 <__aeabi_fsub> 8009a44: 4603 mov r3, r0 8009a46: 461c mov r4, r3 8009a48: 6939 ldr r1, [r7, #16] 8009a4a: 6978 ldr r0, [r7, #20] 8009a4c: f7ff f9e6 bl 8008e1c <__aeabi_fmul> 8009a50: 4603 mov r3, r0 8009a52: 4619 mov r1, r3 8009a54: 4620 mov r0, r4 8009a56: f7ff fa95 bl 8008f84 <__aeabi_fdiv> 8009a5a: 4603 mov r3, r0 8009a5c: 60fb str r3, [r7, #12] return temperature; 8009a5e: 68fb ldr r3, [r7, #12] } 8009a60: 4618 mov r0, r3 8009a62: 371c adds r7, #28 8009a64: 46bd mov sp, r7 8009a66: bd90 pop {r4, r7, pc} 8009a68: 447a0000 .word 0x447a0000 8009a6c: 3b801132 .word 0x3b801132 08009a70 : float calculate_NTC_resistance(int adc_value, float Vref, float Vin, float R) { 8009a70: b5b0 push {r4, r5, r7, lr} 8009a72: b086 sub sp, #24 8009a74: af00 add r7, sp, #0 8009a76: 60f8 str r0, [r7, #12] 8009a78: 60b9 str r1, [r7, #8] 8009a7a: 607a str r2, [r7, #4] 8009a7c: 603b str r3, [r7, #0] // Преобразуем значение АЦП в выходное напряжение float Vout = (adc_value / 4095.0) * Vref; 8009a7e: 68f8 ldr r0, [r7, #12] 8009a80: f7fe fd2c bl 80084dc <__aeabi_i2d> 8009a84: a31c add r3, pc, #112 @ (adr r3, 8009af8 ) 8009a86: e9d3 2300 ldrd r2, r3, [r3] 8009a8a: f7fe febb bl 8008804 <__aeabi_ddiv> 8009a8e: 4602 mov r2, r0 8009a90: 460b mov r3, r1 8009a92: 4614 mov r4, r2 8009a94: 461d mov r5, r3 8009a96: 68b8 ldr r0, [r7, #8] 8009a98: f7fe fd32 bl 8008500 <__aeabi_f2d> 8009a9c: 4602 mov r2, r0 8009a9e: 460b mov r3, r1 8009aa0: 4620 mov r0, r4 8009aa2: 4629 mov r1, r5 8009aa4: f7fe fd84 bl 80085b0 <__aeabi_dmul> 8009aa8: 4602 mov r2, r0 8009aaa: 460b mov r3, r1 8009aac: 4610 mov r0, r2 8009aae: 4619 mov r1, r3 8009ab0: f7ff f856 bl 8008b60 <__aeabi_d2f> 8009ab4: 4603 mov r3, r0 8009ab6: 617b str r3, [r7, #20] // Проверяем, чтобы Vout не было равно Vin if (Vout >= Vin) { 8009ab8: 6879 ldr r1, [r7, #4] 8009aba: 6978 ldr r0, [r7, #20] 8009abc: f7ff fb60 bl 8009180 <__aeabi_fcmpge> 8009ac0: 4603 mov r3, r0 8009ac2: 2b00 cmp r3, #0 8009ac4: d001 beq.n 8009aca return -1; // Ошибка: Vout не может быть больше или равно Vin 8009ac6: 4b0e ldr r3, [pc, #56] @ (8009b00 ) 8009ac8: e010 b.n 8009aec } // Вычисляем сопротивление термистора float R_NTC = R * (Vout / (Vin - Vout)); 8009aca: 6979 ldr r1, [r7, #20] 8009acc: 6878 ldr r0, [r7, #4] 8009ace: f7ff f89b bl 8008c08 <__aeabi_fsub> 8009ad2: 4603 mov r3, r0 8009ad4: 4619 mov r1, r3 8009ad6: 6978 ldr r0, [r7, #20] 8009ad8: f7ff fa54 bl 8008f84 <__aeabi_fdiv> 8009adc: 4603 mov r3, r0 8009ade: 4619 mov r1, r3 8009ae0: 6838 ldr r0, [r7, #0] 8009ae2: f7ff f99b bl 8008e1c <__aeabi_fmul> 8009ae6: 4603 mov r3, r0 8009ae8: 613b str r3, [r7, #16] return R_NTC; 8009aea: 693b ldr r3, [r7, #16] } 8009aec: 4618 mov r0, r3 8009aee: 3718 adds r7, #24 8009af0: 46bd mov sp, r7 8009af2: bdb0 pop {r4, r5, r7, pc} 8009af4: f3af 8000 nop.w 8009af8: 00000000 .word 0x00000000 8009afc: 40affe00 .word 0x40affe00 8009b00: bf800000 .word 0xbf800000 08009b04 : int16_t CONN_ReadTemp(uint8_t ch){ 8009b04: b580 push {r7, lr} 8009b06: b088 sub sp, #32 8009b08: af00 add r7, sp, #0 8009b0a: 4603 mov r3, r0 8009b0c: 71fb strb r3, [r7, #7] uint32_t adcValue = 0u; 8009b0e: 2300 movs r3, #0 8009b10: 61fb str r3, [r7, #28] adcValue = ch ? adc_data.ntc2_raw : adc_data.ntc1_raw; 8009b12: 79fb ldrb r3, [r7, #7] 8009b14: 2b00 cmp r3, #0 8009b16: d003 beq.n 8009b20 8009b18: 4b1c ldr r3, [pc, #112] @ (8009b8c ) 8009b1a: 88db ldrh r3, [r3, #6] 8009b1c: b29b uxth r3, r3 8009b1e: e002 b.n 8009b26 8009b20: 4b1a ldr r3, [pc, #104] @ (8009b8c ) 8009b22: 889b ldrh r3, [r3, #4] 8009b24: b29b uxth r3, r3 8009b26: 61fb str r3, [r7, #28] int32_t adc_filtered = SMAFilter_Update(&conn_temp_adc_filter[ch ? 1u : 0u], (int32_t)adcValue); 8009b28: 79fb ldrb r3, [r7, #7] 8009b2a: 2b00 cmp r3, #0 8009b2c: d001 beq.n 8009b32 8009b2e: 2201 movs r2, #1 8009b30: e000 b.n 8009b34 8009b32: 2200 movs r2, #0 8009b34: 4613 mov r3, r2 8009b36: 009b lsls r3, r3, #2 8009b38: 4413 add r3, r2 8009b3a: 00db lsls r3, r3, #3 8009b3c: 4a14 ldr r2, [pc, #80] @ (8009b90 ) 8009b3e: 4413 add r3, r2 8009b40: 69fa ldr r2, [r7, #28] 8009b42: 4611 mov r1, r2 8009b44: 4618 mov r0, r3 8009b46: f003 fefa bl 800d93e 8009b4a: 61b8 str r0, [r7, #24] if((uint32_t)adc_filtered > 4000u) { 8009b4c: 69bb ldr r3, [r7, #24] 8009b4e: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 8009b52: d901 bls.n 8009b58 return 20; //Термодатчик не подключен 8009b54: 2314 movs r3, #20 8009b56: e015 b.n 8009b84 } float Vref = 3.3; // Напряжение опорное 8009b58: 4b0e ldr r3, [pc, #56] @ (8009b94 ) 8009b5a: 617b str r3, [r7, #20] float Vin = 5.0; // Входное напряжение 8009b5c: 4b0e ldr r3, [pc, #56] @ (8009b98 ) 8009b5e: 613b str r3, [r7, #16] float R = 1000; // Сопротивление резистора в Омах 8009b60: 4b0e ldr r3, [pc, #56] @ (8009b9c ) 8009b62: 60fb str r3, [r7, #12] float temp = pt1000_to_temperature(calculate_NTC_resistance((int)adc_filtered, Vref, Vin, R)); 8009b64: 68fb ldr r3, [r7, #12] 8009b66: 693a ldr r2, [r7, #16] 8009b68: 6979 ldr r1, [r7, #20] 8009b6a: 69b8 ldr r0, [r7, #24] 8009b6c: f7ff ff80 bl 8009a70 8009b70: 4603 mov r3, r0 8009b72: 4618 mov r0, r3 8009b74: f7ff ff5a bl 8009a2c 8009b78: 60b8 str r0, [r7, #8] return (int16_t)temp; 8009b7a: 68b8 ldr r0, [r7, #8] 8009b7c: f7ff fb14 bl 80091a8 <__aeabi_f2iz> 8009b80: 4603 mov r3, r0 8009b82: b21b sxth r3, r3 } 8009b84: 4618 mov r0, r3 8009b86: 3720 adds r7, #32 8009b88: 46bd mov sp, r7 8009b8a: bd80 pop {r7, pc} 8009b8c: 20000280 .word 0x20000280 8009b90: 2000030c .word 0x2000030c 8009b94: 40533333 .word 0x40533333 8009b98: 40a00000 .word 0x40a00000 8009b9c: 447a0000 .word 0x447a0000 08009ba0 : CAN_HandleTypeDef hcan1; CAN_HandleTypeDef hcan2; /* CAN1 init function */ void MX_CAN1_Init(void) { 8009ba0: b580 push {r7, lr} 8009ba2: af00 add r7, sp, #0 /* USER CODE END CAN1_Init 0 */ /* USER CODE BEGIN CAN1_Init 1 */ /* USER CODE END CAN1_Init 1 */ hcan1.Instance = CAN1; 8009ba4: 4b17 ldr r3, [pc, #92] @ (8009c04 ) 8009ba6: 4a18 ldr r2, [pc, #96] @ (8009c08 ) 8009ba8: 601a str r2, [r3, #0] hcan1.Init.Prescaler = 8; 8009baa: 4b16 ldr r3, [pc, #88] @ (8009c04 ) 8009bac: 2208 movs r2, #8 8009bae: 605a str r2, [r3, #4] hcan1.Init.Mode = CAN_MODE_NORMAL; 8009bb0: 4b14 ldr r3, [pc, #80] @ (8009c04 ) 8009bb2: 2200 movs r2, #0 8009bb4: 609a str r2, [r3, #8] hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; 8009bb6: 4b13 ldr r3, [pc, #76] @ (8009c04 ) 8009bb8: 2200 movs r2, #0 8009bba: 60da str r2, [r3, #12] hcan1.Init.TimeSeg1 = CAN_BS1_15TQ; 8009bbc: 4b11 ldr r3, [pc, #68] @ (8009c04 ) 8009bbe: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009bc2: 611a str r2, [r3, #16] hcan1.Init.TimeSeg2 = CAN_BS2_2TQ; 8009bc4: 4b0f ldr r3, [pc, #60] @ (8009c04 ) 8009bc6: f44f 1280 mov.w r2, #1048576 @ 0x100000 8009bca: 615a str r2, [r3, #20] hcan1.Init.TimeTriggeredMode = DISABLE; 8009bcc: 4b0d ldr r3, [pc, #52] @ (8009c04 ) 8009bce: 2200 movs r2, #0 8009bd0: 761a strb r2, [r3, #24] hcan1.Init.AutoBusOff = ENABLE; 8009bd2: 4b0c ldr r3, [pc, #48] @ (8009c04 ) 8009bd4: 2201 movs r2, #1 8009bd6: 765a strb r2, [r3, #25] hcan1.Init.AutoWakeUp = ENABLE; 8009bd8: 4b0a ldr r3, [pc, #40] @ (8009c04 ) 8009bda: 2201 movs r2, #1 8009bdc: 769a strb r2, [r3, #26] hcan1.Init.AutoRetransmission = ENABLE; 8009bde: 4b09 ldr r3, [pc, #36] @ (8009c04 ) 8009be0: 2201 movs r2, #1 8009be2: 76da strb r2, [r3, #27] hcan1.Init.ReceiveFifoLocked = DISABLE; 8009be4: 4b07 ldr r3, [pc, #28] @ (8009c04 ) 8009be6: 2200 movs r2, #0 8009be8: 771a strb r2, [r3, #28] hcan1.Init.TransmitFifoPriority = ENABLE; 8009bea: 4b06 ldr r3, [pc, #24] @ (8009c04 ) 8009bec: 2201 movs r2, #1 8009bee: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan1) != HAL_OK) 8009bf0: 4804 ldr r0, [pc, #16] @ (8009c04 ) 8009bf2: f005 fb38 bl 800f266 8009bf6: 4603 mov r3, r0 8009bf8: 2b00 cmp r3, #0 8009bfa: d001 beq.n 8009c00 { Error_Handler(); 8009bfc: f001 f86a bl 800acd4 } /* USER CODE BEGIN CAN1_Init 2 */ /* USER CODE END CAN1_Init 2 */ } 8009c00: bf00 nop 8009c02: bd80 pop {r7, pc} 8009c04: 2000035c .word 0x2000035c 8009c08: 40006400 .word 0x40006400 08009c0c : /* CAN2 init function */ void MX_CAN2_Init(void) { 8009c0c: b580 push {r7, lr} 8009c0e: af00 add r7, sp, #0 /* USER CODE END CAN2_Init 0 */ /* USER CODE BEGIN CAN2_Init 1 */ /* USER CODE END CAN2_Init 1 */ hcan2.Instance = CAN2; 8009c10: 4b17 ldr r3, [pc, #92] @ (8009c70 ) 8009c12: 4a18 ldr r2, [pc, #96] @ (8009c74 ) 8009c14: 601a str r2, [r3, #0] hcan2.Init.Prescaler = 16; 8009c16: 4b16 ldr r3, [pc, #88] @ (8009c70 ) 8009c18: 2210 movs r2, #16 8009c1a: 605a str r2, [r3, #4] hcan2.Init.Mode = CAN_MODE_NORMAL; 8009c1c: 4b14 ldr r3, [pc, #80] @ (8009c70 ) 8009c1e: 2200 movs r2, #0 8009c20: 609a str r2, [r3, #8] hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; 8009c22: 4b13 ldr r3, [pc, #76] @ (8009c70 ) 8009c24: 2200 movs r2, #0 8009c26: 60da str r2, [r3, #12] hcan2.Init.TimeSeg1 = CAN_BS1_15TQ; 8009c28: 4b11 ldr r3, [pc, #68] @ (8009c70 ) 8009c2a: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009c2e: 611a str r2, [r3, #16] hcan2.Init.TimeSeg2 = CAN_BS2_2TQ; 8009c30: 4b0f ldr r3, [pc, #60] @ (8009c70 ) 8009c32: f44f 1280 mov.w r2, #1048576 @ 0x100000 8009c36: 615a str r2, [r3, #20] hcan2.Init.TimeTriggeredMode = DISABLE; 8009c38: 4b0d ldr r3, [pc, #52] @ (8009c70 ) 8009c3a: 2200 movs r2, #0 8009c3c: 761a strb r2, [r3, #24] hcan2.Init.AutoBusOff = ENABLE; 8009c3e: 4b0c ldr r3, [pc, #48] @ (8009c70 ) 8009c40: 2201 movs r2, #1 8009c42: 765a strb r2, [r3, #25] hcan2.Init.AutoWakeUp = ENABLE; 8009c44: 4b0a ldr r3, [pc, #40] @ (8009c70 ) 8009c46: 2201 movs r2, #1 8009c48: 769a strb r2, [r3, #26] hcan2.Init.AutoRetransmission = ENABLE; 8009c4a: 4b09 ldr r3, [pc, #36] @ (8009c70 ) 8009c4c: 2201 movs r2, #1 8009c4e: 76da strb r2, [r3, #27] hcan2.Init.ReceiveFifoLocked = DISABLE; 8009c50: 4b07 ldr r3, [pc, #28] @ (8009c70 ) 8009c52: 2200 movs r2, #0 8009c54: 771a strb r2, [r3, #28] hcan2.Init.TransmitFifoPriority = ENABLE; 8009c56: 4b06 ldr r3, [pc, #24] @ (8009c70 ) 8009c58: 2201 movs r2, #1 8009c5a: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan2) != HAL_OK) 8009c5c: 4804 ldr r0, [pc, #16] @ (8009c70 ) 8009c5e: f005 fb02 bl 800f266 8009c62: 4603 mov r3, r0 8009c64: 2b00 cmp r3, #0 8009c66: d001 beq.n 8009c6c { Error_Handler(); 8009c68: f001 f834 bl 800acd4 } /* USER CODE BEGIN CAN2_Init 2 */ /* USER CODE END CAN2_Init 2 */ } 8009c6c: bf00 nop 8009c6e: bd80 pop {r7, pc} 8009c70: 20000384 .word 0x20000384 8009c74: 40006800 .word 0x40006800 08009c78 : static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0; void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) { 8009c78: b580 push {r7, lr} 8009c7a: b08e sub sp, #56 @ 0x38 8009c7c: af00 add r7, sp, #0 8009c7e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8009c80: f107 0320 add.w r3, r7, #32 8009c84: 2200 movs r2, #0 8009c86: 601a str r2, [r3, #0] 8009c88: 605a str r2, [r3, #4] 8009c8a: 609a str r2, [r3, #8] 8009c8c: 60da str r2, [r3, #12] if(canHandle->Instance==CAN1) 8009c8e: 687b ldr r3, [r7, #4] 8009c90: 681b ldr r3, [r3, #0] 8009c92: 4a61 ldr r2, [pc, #388] @ (8009e18 ) 8009c94: 4293 cmp r3, r2 8009c96: d153 bne.n 8009d40 { /* USER CODE BEGIN CAN1_MspInit 0 */ /* USER CODE END CAN1_MspInit 0 */ /* CAN1 clock enable */ HAL_RCC_CAN1_CLK_ENABLED++; 8009c98: 4b60 ldr r3, [pc, #384] @ (8009e1c ) 8009c9a: 681b ldr r3, [r3, #0] 8009c9c: 3301 adds r3, #1 8009c9e: 4a5f ldr r2, [pc, #380] @ (8009e1c ) 8009ca0: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009ca2: 4b5e ldr r3, [pc, #376] @ (8009e1c ) 8009ca4: 681b ldr r3, [r3, #0] 8009ca6: 2b01 cmp r3, #1 8009ca8: d10b bne.n 8009cc2 __HAL_RCC_CAN1_CLK_ENABLE(); 8009caa: 4b5d ldr r3, [pc, #372] @ (8009e20 ) 8009cac: 69db ldr r3, [r3, #28] 8009cae: 4a5c ldr r2, [pc, #368] @ (8009e20 ) 8009cb0: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009cb4: 61d3 str r3, [r2, #28] 8009cb6: 4b5a ldr r3, [pc, #360] @ (8009e20 ) 8009cb8: 69db ldr r3, [r3, #28] 8009cba: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009cbe: 61fb str r3, [r7, #28] 8009cc0: 69fb ldr r3, [r7, #28] } __HAL_RCC_GPIOD_CLK_ENABLE(); 8009cc2: 4b57 ldr r3, [pc, #348] @ (8009e20 ) 8009cc4: 699b ldr r3, [r3, #24] 8009cc6: 4a56 ldr r2, [pc, #344] @ (8009e20 ) 8009cc8: f043 0320 orr.w r3, r3, #32 8009ccc: 6193 str r3, [r2, #24] 8009cce: 4b54 ldr r3, [pc, #336] @ (8009e20 ) 8009cd0: 699b ldr r3, [r3, #24] 8009cd2: f003 0320 and.w r3, r3, #32 8009cd6: 61bb str r3, [r7, #24] 8009cd8: 69bb ldr r3, [r7, #24] /**CAN1 GPIO Configuration PD0 ------> CAN1_RX PD1 ------> CAN1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0; 8009cda: 2301 movs r3, #1 8009cdc: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009cde: 2300 movs r3, #0 8009ce0: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009ce2: 2300 movs r3, #0 8009ce4: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009ce6: f107 0320 add.w r3, r7, #32 8009cea: 4619 mov r1, r3 8009cec: 484d ldr r0, [pc, #308] @ (8009e24 ) 8009cee: f006 ff47 bl 8010b80 GPIO_InitStruct.Pin = GPIO_PIN_1; 8009cf2: 2302 movs r3, #2 8009cf4: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009cf6: 2302 movs r3, #2 8009cf8: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009cfa: 2303 movs r3, #3 8009cfc: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009cfe: f107 0320 add.w r3, r7, #32 8009d02: 4619 mov r1, r3 8009d04: 4847 ldr r0, [pc, #284] @ (8009e24 ) 8009d06: f006 ff3b bl 8010b80 __HAL_AFIO_REMAP_CAN1_3(); 8009d0a: 4b47 ldr r3, [pc, #284] @ (8009e28 ) 8009d0c: 685b ldr r3, [r3, #4] 8009d0e: 633b str r3, [r7, #48] @ 0x30 8009d10: 6b3b ldr r3, [r7, #48] @ 0x30 8009d12: f423 43c0 bic.w r3, r3, #24576 @ 0x6000 8009d16: 633b str r3, [r7, #48] @ 0x30 8009d18: 6b3b ldr r3, [r7, #48] @ 0x30 8009d1a: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009d1e: 633b str r3, [r7, #48] @ 0x30 8009d20: 6b3b ldr r3, [r7, #48] @ 0x30 8009d22: f443 43c0 orr.w r3, r3, #24576 @ 0x6000 8009d26: 633b str r3, [r7, #48] @ 0x30 8009d28: 4a3f ldr r2, [pc, #252] @ (8009e28 ) 8009d2a: 6b3b ldr r3, [r7, #48] @ 0x30 8009d2c: 6053 str r3, [r2, #4] /* CAN1 interrupt Init */ HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 3, 0); 8009d2e: 2200 movs r2, #0 8009d30: 2103 movs r1, #3 8009d32: 2014 movs r0, #20 8009d34: f006 fa43 bl 80101be HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn); 8009d38: 2014 movs r0, #20 8009d3a: f006 fa5c bl 80101f6 HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); /* USER CODE BEGIN CAN2_MspInit 1 */ /* USER CODE END CAN2_MspInit 1 */ } } 8009d3e: e067 b.n 8009e10 else if(canHandle->Instance==CAN2) 8009d40: 687b ldr r3, [r7, #4] 8009d42: 681b ldr r3, [r3, #0] 8009d44: 4a39 ldr r2, [pc, #228] @ (8009e2c ) 8009d46: 4293 cmp r3, r2 8009d48: d162 bne.n 8009e10 __HAL_RCC_CAN2_CLK_ENABLE(); 8009d4a: 4b35 ldr r3, [pc, #212] @ (8009e20 ) 8009d4c: 69db ldr r3, [r3, #28] 8009d4e: 4a34 ldr r2, [pc, #208] @ (8009e20 ) 8009d50: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 8009d54: 61d3 str r3, [r2, #28] 8009d56: 4b32 ldr r3, [pc, #200] @ (8009e20 ) 8009d58: 69db ldr r3, [r3, #28] 8009d5a: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8009d5e: 617b str r3, [r7, #20] 8009d60: 697b ldr r3, [r7, #20] HAL_RCC_CAN1_CLK_ENABLED++; 8009d62: 4b2e ldr r3, [pc, #184] @ (8009e1c ) 8009d64: 681b ldr r3, [r3, #0] 8009d66: 3301 adds r3, #1 8009d68: 4a2c ldr r2, [pc, #176] @ (8009e1c ) 8009d6a: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009d6c: 4b2b ldr r3, [pc, #172] @ (8009e1c ) 8009d6e: 681b ldr r3, [r3, #0] 8009d70: 2b01 cmp r3, #1 8009d72: d10b bne.n 8009d8c __HAL_RCC_CAN1_CLK_ENABLE(); 8009d74: 4b2a ldr r3, [pc, #168] @ (8009e20 ) 8009d76: 69db ldr r3, [r3, #28] 8009d78: 4a29 ldr r2, [pc, #164] @ (8009e20 ) 8009d7a: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009d7e: 61d3 str r3, [r2, #28] 8009d80: 4b27 ldr r3, [pc, #156] @ (8009e20 ) 8009d82: 69db ldr r3, [r3, #28] 8009d84: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009d88: 613b str r3, [r7, #16] 8009d8a: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8009d8c: 4b24 ldr r3, [pc, #144] @ (8009e20 ) 8009d8e: 699b ldr r3, [r3, #24] 8009d90: 4a23 ldr r2, [pc, #140] @ (8009e20 ) 8009d92: f043 0308 orr.w r3, r3, #8 8009d96: 6193 str r3, [r2, #24] 8009d98: 4b21 ldr r3, [pc, #132] @ (8009e20 ) 8009d9a: 699b ldr r3, [r3, #24] 8009d9c: f003 0308 and.w r3, r3, #8 8009da0: 60fb str r3, [r7, #12] 8009da2: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_5; 8009da4: 2320 movs r3, #32 8009da6: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009da8: 2300 movs r3, #0 8009daa: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009dac: 2300 movs r3, #0 8009dae: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009db0: f107 0320 add.w r3, r7, #32 8009db4: 4619 mov r1, r3 8009db6: 481e ldr r0, [pc, #120] @ (8009e30 ) 8009db8: f006 fee2 bl 8010b80 GPIO_InitStruct.Pin = GPIO_PIN_6; 8009dbc: 2340 movs r3, #64 @ 0x40 8009dbe: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009dc0: 2302 movs r3, #2 8009dc2: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009dc4: 2303 movs r3, #3 8009dc6: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009dc8: f107 0320 add.w r3, r7, #32 8009dcc: 4619 mov r1, r3 8009dce: 4818 ldr r0, [pc, #96] @ (8009e30 ) 8009dd0: f006 fed6 bl 8010b80 __HAL_AFIO_REMAP_CAN2_ENABLE(); 8009dd4: 4b14 ldr r3, [pc, #80] @ (8009e28 ) 8009dd6: 685b ldr r3, [r3, #4] 8009dd8: 637b str r3, [r7, #52] @ 0x34 8009dda: 6b7b ldr r3, [r7, #52] @ 0x34 8009ddc: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009de0: 637b str r3, [r7, #52] @ 0x34 8009de2: 6b7b ldr r3, [r7, #52] @ 0x34 8009de4: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8009de8: 637b str r3, [r7, #52] @ 0x34 8009dea: 4a0f ldr r2, [pc, #60] @ (8009e28 ) 8009dec: 6b7b ldr r3, [r7, #52] @ 0x34 8009dee: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(CAN2_TX_IRQn, 0, 0); 8009df0: 2200 movs r2, #0 8009df2: 2100 movs r1, #0 8009df4: 203f movs r0, #63 @ 0x3f 8009df6: f006 f9e2 bl 80101be HAL_NVIC_EnableIRQ(CAN2_TX_IRQn); 8009dfa: 203f movs r0, #63 @ 0x3f 8009dfc: f006 f9fb bl 80101f6 HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 3, 0); 8009e00: 2200 movs r2, #0 8009e02: 2103 movs r1, #3 8009e04: 2041 movs r0, #65 @ 0x41 8009e06: f006 f9da bl 80101be HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); 8009e0a: 2041 movs r0, #65 @ 0x41 8009e0c: f006 f9f3 bl 80101f6 } 8009e10: bf00 nop 8009e12: 3738 adds r7, #56 @ 0x38 8009e14: 46bd mov sp, r7 8009e16: bd80 pop {r7, pc} 8009e18: 40006400 .word 0x40006400 8009e1c: 200003ac .word 0x200003ac 8009e20: 40021000 .word 0x40021000 8009e24: 40011400 .word 0x40011400 8009e28: 40010000 .word 0x40010000 8009e2c: 40006800 .word 0x40006800 8009e30: 40010c00 .word 0x40010c00 08009e34 : #include "psu_control.h" ChargingConnector_t CONN; CONN_State_t connectorState; void CONN_Init(){ 8009e34: b480 push {r7} 8009e36: af00 add r7, sp, #0 CONN.connControl = CMD_NONE; 8009e38: 4b08 ldr r3, [pc, #32] @ (8009e5c ) 8009e3a: 2200 movs r2, #0 8009e3c: 701a strb r2, [r3, #0] CONN.connState = Unknown; 8009e3e: 4b07 ldr r3, [pc, #28] @ (8009e5c ) 8009e40: 2200 movs r2, #0 8009e42: 705a strb r2, [r3, #1] CONN.RequestedVoltage = PSU_MIN_VOLTAGE; 8009e44: 4b05 ldr r3, [pc, #20] @ (8009e5c ) 8009e46: 2200 movs r2, #0 8009e48: f062 0269 orn r2, r2, #105 @ 0x69 8009e4c: 73da strb r2, [r3, #15] 8009e4e: 2200 movs r2, #0 8009e50: 741a strb r2, [r3, #16] } 8009e52: bf00 nop 8009e54: 46bd mov sp, r7 8009e56: bc80 pop {r7} 8009e58: 4770 bx lr 8009e5a: bf00 nop 8009e5c: 200003b0 .word 0x200003b0 08009e60 : void CONN_Loop(){ 8009e60: b580 push {r7, lr} 8009e62: af00 add r7, sp, #0 static CONN_State_t last_connState = Unknown; if(last_connState != CONN.connState){ 8009e64: 4b1f ldr r3, [pc, #124] @ (8009ee4 ) 8009e66: 785a ldrb r2, [r3, #1] 8009e68: 4b1f ldr r3, [pc, #124] @ (8009ee8 ) 8009e6a: 781b ldrb r3, [r3, #0] 8009e6c: 429a cmp r2, r3 8009e6e: d006 beq.n 8009e7e last_connState = CONN.connState; 8009e70: 4b1c ldr r3, [pc, #112] @ (8009ee4 ) 8009e72: 785a ldrb r2, [r3, #1] 8009e74: 4b1c ldr r3, [pc, #112] @ (8009ee8 ) 8009e76: 701a strb r2, [r3, #0] CONN.connControl = CMD_NONE; 8009e78: 4b1a ldr r3, [pc, #104] @ (8009ee4 ) 8009e7a: 2200 movs r2, #0 8009e7c: 701a strb r2, [r3, #0] } if (FireAlarm_IsLatched()) { 8009e7e: f000 fbe7 bl 800a650 8009e82: 4603 mov r3, r0 8009e84: 2b00 cmp r3, #0 8009e86: d003 beq.n 8009e90 CONN.chargingError = CONN_ERR_FIRE_ALARM; 8009e88: 4b16 ldr r3, [pc, #88] @ (8009ee4 ) 8009e8a: 220b movs r2, #11 8009e8c: 775a strb r2, [r3, #29] 8009e8e: e016 b.n 8009ebe } else if(PSU0.cont_fault){ 8009e90: 4b16 ldr r3, [pc, #88] @ (8009eec ) 8009e92: 7b1b ldrb r3, [r3, #12] 8009e94: 2b00 cmp r3, #0 8009e96: d003 beq.n 8009ea0 CONN.chargingError = CONN_ERR_CONTACTOR; 8009e98: 4b12 ldr r3, [pc, #72] @ (8009ee4 ) 8009e9a: 2207 movs r2, #7 8009e9c: 775a strb r2, [r3, #29] 8009e9e: e00e b.n 8009ebe } else if(PSU0.psu_fault){ 8009ea0: 4b12 ldr r3, [pc, #72] @ (8009eec ) 8009ea2: 7b5b ldrb r3, [r3, #13] 8009ea4: 2b00 cmp r3, #0 8009ea6: d003 beq.n 8009eb0 CONN.chargingError = CONN_ERR_PSU_FAULT; 8009ea8: 4b0e ldr r3, [pc, #56] @ (8009ee4 ) 8009eaa: 220a movs r2, #10 8009eac: 775a strb r2, [r3, #29] 8009eae: e006 b.n 8009ebe }else if (CONN.EvConnected == 0){ 8009eb0: 4b0c ldr r3, [pc, #48] @ (8009ee4 ) 8009eb2: 7f9b ldrb r3, [r3, #30] 8009eb4: 2b00 cmp r3, #0 8009eb6: d102 bne.n 8009ebe CONN.chargingError = CONN_NO_ERROR; 8009eb8: 4b0a ldr r3, [pc, #40] @ (8009ee4 ) 8009eba: 2200 movs r2, #0 8009ebc: 775a strb r2, [r3, #29] } if(ED_TraceWarning(CONN.chargingError, 0)) { 8009ebe: 4b09 ldr r3, [pc, #36] @ (8009ee4 ) 8009ec0: 7f5b ldrb r3, [r3, #29] 8009ec2: 2100 movs r1, #0 8009ec4: 4618 mov r0, r3 8009ec6: f000 fd47 bl 800a958 8009eca: 4603 mov r3, r0 8009ecc: 2b00 cmp r3, #0 8009ece: d006 beq.n 8009ede log_printf(LOG_WARN, "CONN0 Error: %d\n", (int)CONN.chargingError); 8009ed0: 4b04 ldr r3, [pc, #16] @ (8009ee4 ) 8009ed2: 7f5b ldrb r3, [r3, #29] 8009ed4: 461a mov r2, r3 8009ed6: 4906 ldr r1, [pc, #24] @ (8009ef0 ) 8009ed8: 2005 movs r0, #5 8009eda: f000 fb45 bl 800a568 } } 8009ede: bf00 nop 8009ee0: bd80 pop {r7, pc} 8009ee2: bf00 nop 8009ee4: 200003b0 .word 0x200003b0 8009ee8: 200003d0 .word 0x200003d0 8009eec: 20000904 .word 0x20000904 8009ef0: 08017350 .word 0x08017350 08009ef4 : void CONN_SetState(CONN_State_t state){ 8009ef4: b580 push {r7, lr} 8009ef6: b082 sub sp, #8 8009ef8: af00 add r7, sp, #0 8009efa: 4603 mov r3, r0 8009efc: 71fb strb r3, [r7, #7] if (connectorState == state) { 8009efe: 4b41 ldr r3, [pc, #260] @ (800a004 ) 8009f00: 781b ldrb r3, [r3, #0] 8009f02: 79fa ldrb r2, [r7, #7] 8009f04: 429a cmp r2, r3 8009f06: d103 bne.n 8009f10 CONN.connState = state; 8009f08: 4a3f ldr r2, [pc, #252] @ (800a008 ) 8009f0a: 79fb ldrb r3, [r7, #7] 8009f0c: 7053 strb r3, [r2, #1] return; 8009f0e: e075 b.n 8009ffc } connectorState = state; 8009f10: 4a3c ldr r2, [pc, #240] @ (800a004 ) 8009f12: 79fb ldrb r3, [r7, #7] 8009f14: 7013 strb r3, [r2, #0] if(connectorState == Unknown) log_printf(LOG_INFO, "Connector: Unknown\n"); 8009f16: 4b3b ldr r3, [pc, #236] @ (800a004 ) 8009f18: 781b ldrb r3, [r3, #0] 8009f1a: 2b00 cmp r3, #0 8009f1c: d103 bne.n 8009f26 8009f1e: 493b ldr r1, [pc, #236] @ (800a00c ) 8009f20: 2007 movs r0, #7 8009f22: f000 fb21 bl 800a568 if(connectorState == Unplugged) log_printf(LOG_INFO, "Connector: Unplugged\n"); 8009f26: 4b37 ldr r3, [pc, #220] @ (800a004 ) 8009f28: 781b ldrb r3, [r3, #0] 8009f2a: 2b01 cmp r3, #1 8009f2c: d103 bne.n 8009f36 8009f2e: 4938 ldr r1, [pc, #224] @ (800a010 ) 8009f30: 2007 movs r0, #7 8009f32: f000 fb19 bl 800a568 if(connectorState == Disabled) log_printf(LOG_INFO, "Connector: Disabled\n"); 8009f36: 4b33 ldr r3, [pc, #204] @ (800a004 ) 8009f38: 781b ldrb r3, [r3, #0] 8009f3a: 2b02 cmp r3, #2 8009f3c: d103 bne.n 8009f46 8009f3e: 4935 ldr r1, [pc, #212] @ (800a014 ) 8009f40: 2007 movs r0, #7 8009f42: f000 fb11 bl 800a568 if(connectorState == Preparing) log_printf(LOG_INFO, "Connector: Preparing\n"); 8009f46: 4b2f ldr r3, [pc, #188] @ (800a004 ) 8009f48: 781b ldrb r3, [r3, #0] 8009f4a: 2b03 cmp r3, #3 8009f4c: d103 bne.n 8009f56 8009f4e: 4932 ldr r1, [pc, #200] @ (800a018 ) 8009f50: 2007 movs r0, #7 8009f52: f000 fb09 bl 800a568 if(connectorState == AuthRequired) log_printf(LOG_INFO, "Connector: AuthRequired\n"); 8009f56: 4b2b ldr r3, [pc, #172] @ (800a004 ) 8009f58: 781b ldrb r3, [r3, #0] 8009f5a: 2b04 cmp r3, #4 8009f5c: d103 bne.n 8009f66 8009f5e: 492f ldr r1, [pc, #188] @ (800a01c ) 8009f60: 2007 movs r0, #7 8009f62: f000 fb01 bl 800a568 if(connectorState == WaitingForEnergy) log_printf(LOG_INFO, "Connector: WaitingForEnergy\n"); 8009f66: 4b27 ldr r3, [pc, #156] @ (800a004 ) 8009f68: 781b ldrb r3, [r3, #0] 8009f6a: 2b05 cmp r3, #5 8009f6c: d103 bne.n 8009f76 8009f6e: 492c ldr r1, [pc, #176] @ (800a020 ) 8009f70: 2007 movs r0, #7 8009f72: f000 faf9 bl 800a568 if(connectorState == ChargingPausedEV) log_printf(LOG_INFO, "Connector: ChargingPausedEV\n"); 8009f76: 4b23 ldr r3, [pc, #140] @ (800a004 ) 8009f78: 781b ldrb r3, [r3, #0] 8009f7a: 2b06 cmp r3, #6 8009f7c: d103 bne.n 8009f86 8009f7e: 4929 ldr r1, [pc, #164] @ (800a024 ) 8009f80: 2007 movs r0, #7 8009f82: f000 faf1 bl 800a568 if(connectorState == ChargingPausedEVSE) log_printf(LOG_INFO, "Connector: ChargingPausedEVSE\n"); 8009f86: 4b1f ldr r3, [pc, #124] @ (800a004 ) 8009f88: 781b ldrb r3, [r3, #0] 8009f8a: 2b07 cmp r3, #7 8009f8c: d103 bne.n 8009f96 8009f8e: 4926 ldr r1, [pc, #152] @ (800a028 ) 8009f90: 2007 movs r0, #7 8009f92: f000 fae9 bl 800a568 if(connectorState == Charging) log_printf(LOG_INFO, "Connector: Charging\n"); 8009f96: 4b1b ldr r3, [pc, #108] @ (800a004 ) 8009f98: 781b ldrb r3, [r3, #0] 8009f9a: 2b08 cmp r3, #8 8009f9c: d103 bne.n 8009fa6 8009f9e: 4923 ldr r1, [pc, #140] @ (800a02c ) 8009fa0: 2007 movs r0, #7 8009fa2: f000 fae1 bl 800a568 if(connectorState == AuthTimeout) log_printf(LOG_INFO, "Connector: AuthTimeout\n"); 8009fa6: 4b17 ldr r3, [pc, #92] @ (800a004 ) 8009fa8: 781b ldrb r3, [r3, #0] 8009faa: 2b09 cmp r3, #9 8009fac: d103 bne.n 8009fb6 8009fae: 4920 ldr r1, [pc, #128] @ (800a030 ) 8009fb0: 2007 movs r0, #7 8009fb2: f000 fad9 bl 800a568 if(connectorState == Finished) log_printf(LOG_INFO, "Connector: Finished\n"); 8009fb6: 4b13 ldr r3, [pc, #76] @ (800a004 ) 8009fb8: 781b ldrb r3, [r3, #0] 8009fba: 2b0a cmp r3, #10 8009fbc: d103 bne.n 8009fc6 8009fbe: 491d ldr r1, [pc, #116] @ (800a034 ) 8009fc0: 2007 movs r0, #7 8009fc2: f000 fad1 bl 800a568 if(connectorState == FinishedEVSE) log_printf(LOG_INFO, "Connector: FinishedEVSE\n"); 8009fc6: 4b0f ldr r3, [pc, #60] @ (800a004 ) 8009fc8: 781b ldrb r3, [r3, #0] 8009fca: 2b0b cmp r3, #11 8009fcc: d103 bne.n 8009fd6 8009fce: 491a ldr r1, [pc, #104] @ (800a038 ) 8009fd0: 2007 movs r0, #7 8009fd2: f000 fac9 bl 800a568 if(connectorState == FinishedEV) log_printf(LOG_INFO, "Connector: FinishedEV\n"); 8009fd6: 4b0b ldr r3, [pc, #44] @ (800a004 ) 8009fd8: 781b ldrb r3, [r3, #0] 8009fda: 2b0c cmp r3, #12 8009fdc: d103 bne.n 8009fe6 8009fde: 4917 ldr r1, [pc, #92] @ (800a03c ) 8009fe0: 2007 movs r0, #7 8009fe2: f000 fac1 bl 800a568 if(connectorState == Replugging) log_printf(LOG_INFO, "Connector: Replugging\n"); 8009fe6: 4b07 ldr r3, [pc, #28] @ (800a004 ) 8009fe8: 781b ldrb r3, [r3, #0] 8009fea: 2b0d cmp r3, #13 8009fec: d103 bne.n 8009ff6 8009fee: 4914 ldr r1, [pc, #80] @ (800a040 ) 8009ff0: 2007 movs r0, #7 8009ff2: f000 fab9 bl 800a568 CONN.connState = state; 8009ff6: 4a04 ldr r2, [pc, #16] @ (800a008 ) 8009ff8: 79fb ldrb r3, [r7, #7] 8009ffa: 7053 strb r3, [r2, #1] } 8009ffc: 3708 adds r7, #8 8009ffe: 46bd mov sp, r7 800a000: bd80 pop {r7, pc} 800a002: bf00 nop 800a004: 200003cf .word 0x200003cf 800a008: 200003b0 .word 0x200003b0 800a00c: 08017364 .word 0x08017364 800a010: 08017378 .word 0x08017378 800a014: 08017390 .word 0x08017390 800a018: 080173a8 .word 0x080173a8 800a01c: 080173c0 .word 0x080173c0 800a020: 080173dc .word 0x080173dc 800a024: 080173fc .word 0x080173fc 800a028: 0801741c .word 0x0801741c 800a02c: 0801743c .word 0x0801743c 800a030: 08017454 .word 0x08017454 800a034: 0801746c .word 0x0801746c 800a038: 08017484 .word 0x08017484 800a03c: 080174a0 .word 0x080174a0 800a040: 080174b8 .word 0x080174b8 0800a044 : CP_State_t cp_state_buffer = EV_STATE_ACQUIRING; #define VREFINT_CAL_ADDR ((uint16_t*)0x1FFFF7BA) // для STM32F1! static int32_t CP_ReadVoltageMv(void) { 800a044: b480 push {r7} 800a046: b087 sub sp, #28 800a048: af00 add r7, sp, #0 uint32_t adc_cp = adc_data.cp_raw; 800a04a: 4b13 ldr r3, [pc, #76] @ (800a098 ) 800a04c: 885b ldrh r3, [r3, #2] 800a04e: b29b uxth r3, r3 800a050: 617b str r3, [r7, #20] uint32_t adc_vref = adc_data.vrefint_raw; // нужно измерять! 800a052: 4b11 ldr r3, [pc, #68] @ (800a098 ) 800a054: 895b ldrh r3, [r3, #10] 800a056: b29b uxth r3, r3 800a058: 613b str r3, [r7, #16] // VREFINT в мВ (берётся из даташита или калибровки MCU) const int32_t VREFINT_MV = 1210; 800a05a: f240 43ba movw r3, #1210 @ 0x4ba 800a05e: 60fb str r3, [r7, #12] // напряжение на входе АЦП int32_t v_adc_mv = (adc_cp * VREFINT_MV) / adc_vref; 800a060: 68fb ldr r3, [r7, #12] 800a062: 697a ldr r2, [r7, #20] 800a064: fb03 f202 mul.w r2, r3, r2 800a068: 693b ldr r3, [r7, #16] 800a06a: fbb2 f3f3 udiv r3, r2, r3 800a06e: 60bb str r3, [r7, #8] // дальше твоя формула int32_t v_out_mv = ((v_adc_mv - 1723) * 7704) / 1000; 800a070: 68bb ldr r3, [r7, #8] 800a072: f2a3 63bb subw r3, r3, #1723 @ 0x6bb 800a076: f641 6218 movw r2, #7704 @ 0x1e18 800a07a: fb02 f303 mul.w r3, r2, r3 800a07e: 4a07 ldr r2, [pc, #28] @ (800a09c ) 800a080: fb82 1203 smull r1, r2, r2, r3 800a084: 1192 asrs r2, r2, #6 800a086: 17db asrs r3, r3, #31 800a088: 1ad3 subs r3, r2, r3 800a08a: 607b str r3, [r7, #4] return v_out_mv; 800a08c: 687b ldr r3, [r7, #4] } 800a08e: 4618 mov r0, r3 800a090: 371c adds r7, #28 800a092: 46bd mov sp, r7 800a094: bc80 pop {r7} 800a096: 4770 bx lr 800a098: 20000280 .word 0x20000280 800a09c: 10624dd3 .word 0x10624dd3 0800a0a0 : void CP_Init(void) { 800a0a0: b580 push {r7, lr} 800a0a2: af00 add r7, sp, #0 /* TIM3_CH2 (PA7): set 1kHz PWM like original CCS logic. */ htim3.Instance->PSC = 160 - 1; 800a0a4: 4b0e ldr r3, [pc, #56] @ (800a0e0 ) 800a0a6: 681b ldr r3, [r3, #0] 800a0a8: 229f movs r2, #159 @ 0x9f 800a0aa: 629a str r2, [r3, #40] @ 0x28 htim3.Instance->ARR = MAX_DUTY - 1; 800a0ac: 4b0c ldr r3, [pc, #48] @ (800a0e0 ) 800a0ae: 681b ldr r3, [r3, #0] 800a0b0: f240 12c1 movw r2, #449 @ 0x1c1 800a0b4: 62da str r2, [r3, #44] @ 0x2c #if DUTY_INVERT == 0 htim3.Instance->CCR2 = MAX_DUTY; 800a0b6: 4b0a ldr r3, [pc, #40] @ (800a0e0 ) 800a0b8: 681b ldr r3, [r3, #0] 800a0ba: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a0be: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = MAX_DUTY + 5; 800a0c0: 4b07 ldr r3, [pc, #28] @ (800a0e0 ) 800a0c2: 681b ldr r3, [r3, #0] 800a0c4: f240 12c7 movw r2, #455 @ 0x1c7 800a0c8: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = 0; htim3.Instance->CCR1 = 0; #endif HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_2); 800a0ca: 2104 movs r1, #4 800a0cc: 4804 ldr r0, [pc, #16] @ (800a0e0 ) 800a0ce: f008 fa29 bl 8012524 HAL_TIM_OC_Start(&htim3, TIM_CHANNEL_1); 800a0d2: 2100 movs r1, #0 800a0d4: 4802 ldr r0, [pc, #8] @ (800a0e0 ) 800a0d6: f008 f923 bl 8012320 } 800a0da: bf00 nop 800a0dc: bd80 pop {r7, pc} 800a0de: bf00 nop 800a0e0: 200011dc .word 0x200011dc 0800a0e4 : void CP_SetDuty(uint8_t percentage) { 800a0e4: b480 push {r7} 800a0e6: b085 sub sp, #20 800a0e8: af00 add r7, sp, #0 800a0ea: 4603 mov r3, r0 800a0ec: 71fb strb r3, [r7, #7] uint32_t pwmduty = MAX_DUTY * percentage / 100; 800a0ee: 79fb ldrb r3, [r7, #7] 800a0f0: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a0f4: fb02 f303 mul.w r3, r2, r3 800a0f8: 4a0b ldr r2, [pc, #44] @ (800a128 ) 800a0fa: fb82 1203 smull r1, r2, r2, r3 800a0fe: 1152 asrs r2, r2, #5 800a100: 17db asrs r3, r3, #31 800a102: 1ad3 subs r3, r2, r3 800a104: 60fb str r3, [r7, #12] cp_duty = percentage; 800a106: 4a09 ldr r2, [pc, #36] @ (800a12c ) 800a108: 79fb ldrb r3, [r7, #7] 800a10a: 7013 strb r3, [r2, #0] #if DUTY_INVERT == 0 htim3.Instance->CCR2 = pwmduty; 800a10c: 4b08 ldr r3, [pc, #32] @ (800a130 ) 800a10e: 681b ldr r3, [r3, #0] 800a110: 68fa ldr r2, [r7, #12] 800a112: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = 0 + 1; 800a114: 4b06 ldr r3, [pc, #24] @ (800a130 ) 800a116: 681b ldr r3, [r3, #0] 800a118: 2201 movs r2, #1 800a11a: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = MAX_DUTY - pwmduty; htim3.Instance->CCR1 = MAX_DUTY - pwmduty + 5; #endif } 800a11c: bf00 nop 800a11e: 3714 adds r7, #20 800a120: 46bd mov sp, r7 800a122: bc80 pop {r7} 800a124: 4770 bx lr 800a126: bf00 nop 800a128: 51eb851f .word 0x51eb851f 800a12c: 200003d8 .word 0x200003d8 800a130: 200011dc .word 0x200011dc 0800a134 : uint8_t CP_GetDuty(void) { 800a134: b480 push {r7} 800a136: af00 add r7, sp, #0 return cp_duty; 800a138: 4b02 ldr r3, [pc, #8] @ (800a144 ) 800a13a: 781b ldrb r3, [r3, #0] } 800a13c: 4618 mov r0, r3 800a13e: 46bd mov sp, r7 800a140: bc80 pop {r7} 800a142: 4770 bx lr 800a144: 200003d8 .word 0x200003d8 0800a148 : int32_t CP_GetVoltage(void) { 800a148: b580 push {r7, lr} 800a14a: af00 add r7, sp, #0 cp_voltage_mv = CP_ReadVoltageMv(); 800a14c: f7ff ff7a bl 800a044 800a150: 4603 mov r3, r0 800a152: 4a03 ldr r2, [pc, #12] @ (800a160 ) 800a154: 6013 str r3, [r2, #0] return cp_voltage_mv; 800a156: 4b02 ldr r3, [pc, #8] @ (800a160 ) 800a158: 681b ldr r3, [r3, #0] } 800a15a: 4618 mov r0, r3 800a15c: bd80 pop {r7, pc} 800a15e: bf00 nop 800a160: 200003d4 .word 0x200003d4 0800a164 : CP_State_t CP_GetState(void) { 800a164: b580 push {r7, lr} 800a166: b082 sub sp, #8 800a168: af00 add r7, sp, #0 int32_t voltage_real = CP_GetVoltage(); 800a16a: f7ff ffed bl 800a148 800a16e: 6078 str r0, [r7, #4] if(fake_cp_state != EV_STATE_ACQUIRING) { 800a170: 4b21 ldr r3, [pc, #132] @ (800a1f8 ) 800a172: 781b ldrb r3, [r3, #0] 800a174: 2b06 cmp r3, #6 800a176: d002 beq.n 800a17e return fake_cp_state; 800a178: 4b1f ldr r3, [pc, #124] @ (800a1f8 ) 800a17a: 781b ldrb r3, [r3, #0] 800a17c: e038 b.n 800a1f0 } if (voltage_real >= (12000-1000)) { 800a17e: 687b ldr r3, [r7, #4] 800a180: f642 22f7 movw r2, #10999 @ 0x2af7 800a184: 4293 cmp r3, r2 800a186: dd01 ble.n 800a18c return EV_STATE_A_IDLE; 800a188: 2300 movs r3, #0 800a18a: e031 b.n 800a1f0 } else if (voltage_real >= (9000-1000) && voltage_real <= (9000+1000)) { 800a18c: 687b ldr r3, [r7, #4] 800a18e: f5b3 5ffa cmp.w r3, #8000 @ 0x1f40 800a192: db06 blt.n 800a1a2 800a194: 687b ldr r3, [r7, #4] 800a196: f242 7210 movw r2, #10000 @ 0x2710 800a19a: 4293 cmp r3, r2 800a19c: dc01 bgt.n 800a1a2 return EV_STATE_B_CONN_PREP; 800a19e: 2301 movs r3, #1 800a1a0: e026 b.n 800a1f0 } else if (voltage_real >= (6000-1000) && voltage_real <= (6000+1000)) { 800a1a2: 687b ldr r3, [r7, #4] 800a1a4: f241 3287 movw r2, #4999 @ 0x1387 800a1a8: 4293 cmp r3, r2 800a1aa: dd06 ble.n 800a1ba 800a1ac: 687b ldr r3, [r7, #4] 800a1ae: f641 3258 movw r2, #7000 @ 0x1b58 800a1b2: 4293 cmp r3, r2 800a1b4: dc01 bgt.n 800a1ba return EV_STATE_C_CONN_ACTIVE; 800a1b6: 2302 movs r3, #2 800a1b8: e01a b.n 800a1f0 } else if (voltage_real >= (3000-1000) && voltage_real <= (3000 + 1000)) { 800a1ba: 687b ldr r3, [r7, #4] 800a1bc: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800a1c0: db05 blt.n 800a1ce 800a1c2: 687b ldr r3, [r7, #4] 800a1c4: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800a1c8: dc01 bgt.n 800a1ce return EV_STATE_D_CONN_ACT_VENT; 800a1ca: 2303 movs r3, #3 800a1cc: e010 b.n 800a1f0 } else if (voltage_real >= (0-1000) && voltage_real <= (0+2000)){ 800a1ce: 687b ldr r3, [r7, #4] 800a1d0: f513 7f7a cmn.w r3, #1000 @ 0x3e8 800a1d4: db05 blt.n 800a1e2 800a1d6: 687b ldr r3, [r7, #4] 800a1d8: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800a1dc: dc01 bgt.n 800a1e2 return EV_STATE_E_NO_POWER; 800a1de: 2304 movs r3, #4 800a1e0: e006 b.n 800a1f0 } else if (voltage_real <= (-12000+1000)) { 800a1e2: 687b ldr r3, [r7, #4] 800a1e4: 4a05 ldr r2, [pc, #20] @ (800a1fc ) 800a1e6: 4293 cmp r3, r2 800a1e8: da01 bge.n 800a1ee return EV_STATE_F_ERROR; 800a1ea: 2305 movs r3, #5 800a1ec: e000 b.n 800a1f0 } else { return EV_STATE_ACQUIRING; 800a1ee: 2306 movs r3, #6 } } 800a1f0: 4618 mov r0, r3 800a1f2: 3708 adds r7, #8 800a1f4: 46bd mov sp, r7 800a1f6: bd80 pop {r7, pc} 800a1f8: 20000004 .word 0x20000004 800a1fc: ffffd509 .word 0xffffd509 0800a200 : CP_State_t CP_GetFilteredState(void) { 800a200: b480 push {r7} 800a202: af00 add r7, sp, #0 return cp_state_buffer; 800a204: 4b02 ldr r3, [pc, #8] @ (800a210 ) 800a206: 781b ldrb r3, [r3, #0] } 800a208: 4618 mov r0, r3 800a20a: 46bd mov sp, r7 800a20c: bc80 pop {r7} 800a20e: 4770 bx lr 800a210: 20000005 .word 0x20000005 0800a214 : void CP_FilterState(void) { 800a214: b580 push {r7, lr} 800a216: b082 sub sp, #8 800a218: af00 add r7, sp, #0 static CP_State_t pending_state = EV_STATE_ACQUIRING; static uint8_t stable_count = 0u; CP_State_t current_state = CP_GetState(); 800a21a: f7ff ffa3 bl 800a164 800a21e: 4603 mov r3, r0 800a220: 71fb strb r3, [r7, #7] /* Keep last accepted state while CP is still acquiring. */ if (current_state == EV_STATE_ACQUIRING) { 800a222: 79fb ldrb r3, [r7, #7] 800a224: 2b06 cmp r3, #6 800a226: d106 bne.n 800a236 pending_state = EV_STATE_ACQUIRING; 800a228: 4b13 ldr r3, [pc, #76] @ (800a278 ) 800a22a: 2206 movs r2, #6 800a22c: 701a strb r2, [r3, #0] stable_count = 0u; 800a22e: 4b13 ldr r3, [pc, #76] @ (800a27c ) 800a230: 2200 movs r2, #0 800a232: 701a strb r2, [r3, #0] return; 800a234: e01d b.n 800a272 } if (current_state != pending_state) { 800a236: 4b10 ldr r3, [pc, #64] @ (800a278 ) 800a238: 781b ldrb r3, [r3, #0] 800a23a: 79fa ldrb r2, [r7, #7] 800a23c: 429a cmp r2, r3 800a23e: d006 beq.n 800a24e pending_state = current_state; 800a240: 4a0d ldr r2, [pc, #52] @ (800a278 ) 800a242: 79fb ldrb r3, [r7, #7] 800a244: 7013 strb r3, [r2, #0] stable_count = 1u; 800a246: 4b0d ldr r3, [pc, #52] @ (800a27c ) 800a248: 2201 movs r2, #1 800a24a: 701a strb r2, [r3, #0] return; 800a24c: e011 b.n 800a272 } if (stable_count < FILTER_ORDER) { 800a24e: 4b0b ldr r3, [pc, #44] @ (800a27c ) 800a250: 781b ldrb r3, [r3, #0] 800a252: 2b63 cmp r3, #99 @ 0x63 800a254: d805 bhi.n 800a262 stable_count++; 800a256: 4b09 ldr r3, [pc, #36] @ (800a27c ) 800a258: 781b ldrb r3, [r3, #0] 800a25a: 3301 adds r3, #1 800a25c: b2da uxtb r2, r3 800a25e: 4b07 ldr r3, [pc, #28] @ (800a27c ) 800a260: 701a strb r2, [r3, #0] } if (stable_count >= FILTER_ORDER) { 800a262: 4b06 ldr r3, [pc, #24] @ (800a27c ) 800a264: 781b ldrb r3, [r3, #0] 800a266: 2b63 cmp r3, #99 @ 0x63 800a268: d903 bls.n 800a272 cp_state_buffer = pending_state; 800a26a: 4b03 ldr r3, [pc, #12] @ (800a278 ) 800a26c: 781a ldrb r2, [r3, #0] 800a26e: 4b04 ldr r3, [pc, #16] @ (800a280 ) 800a270: 701a strb r2, [r3, #0] } } 800a272: 3708 adds r7, #8 800a274: 46bd mov sp, r7 800a276: bd80 pop {r7, pc} 800a278: 20000006 .word 0x20000006 800a27c: 200003d9 .word 0x200003d9 800a280: 20000005 .word 0x20000005 0800a284 : void CP_Loop(void) { 800a284: b580 push {r7, lr} 800a286: b082 sub sp, #8 800a288: af00 add r7, sp, #0 static uint32_t tick; if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800a28a: f004 fa7d bl 800e788 800a28e: 4602 mov r2, r0 800a290: 4b22 ldr r3, [pc, #136] @ (800a31c ) 800a292: 681b ldr r3, [r3, #0] 800a294: 1ad3 subs r3, r2, r3 800a296: 2b00 cmp r3, #0 800a298: dd3c ble.n 800a314 tick = HAL_GetTick(); 800a29a: f004 fa75 bl 800e788 800a29e: 4603 mov r3, r0 800a2a0: 4a1e ldr r2, [pc, #120] @ (800a31c ) 800a2a2: 6013 str r3, [r2, #0] static uint8_t initialized = 0; static CP_State_t prev_state = EV_STATE_ACQUIRING; static uint8_t prev_duty = 0; CP_FilterState(); 800a2a4: f7ff ffb6 bl 800a214 CP_State_t current_state = CP_GetFilteredState(); 800a2a8: f7ff ffaa bl 800a200 800a2ac: 4603 mov r3, r0 800a2ae: 71fb strb r3, [r7, #7] uint8_t current_duty = cp_duty; 800a2b0: 4b1b ldr r3, [pc, #108] @ (800a320 ) 800a2b2: 781b ldrb r3, [r3, #0] 800a2b4: 71bb strb r3, [r7, #6] if (!initialized) { 800a2b6: 4b1b ldr r3, [pc, #108] @ (800a324 ) 800a2b8: 781b ldrb r3, [r3, #0] 800a2ba: 2b00 cmp r3, #0 800a2bc: d109 bne.n 800a2d2 prev_state = current_state; 800a2be: 4a1a ldr r2, [pc, #104] @ (800a328 ) 800a2c0: 79fb ldrb r3, [r7, #7] 800a2c2: 7013 strb r3, [r2, #0] prev_duty = current_duty; 800a2c4: 4a19 ldr r2, [pc, #100] @ (800a32c ) 800a2c6: 79bb ldrb r3, [r7, #6] 800a2c8: 7013 strb r3, [r2, #0] initialized = 1; 800a2ca: 4b16 ldr r3, [pc, #88] @ (800a324 ) 800a2cc: 2201 movs r2, #1 800a2ce: 701a strb r2, [r3, #0] return; 800a2d0: e021 b.n 800a316 } if (current_state != prev_state) { 800a2d2: 4b15 ldr r3, [pc, #84] @ (800a328 ) 800a2d4: 781b ldrb r3, [r3, #0] 800a2d6: 79fa ldrb r2, [r7, #7] 800a2d8: 429a cmp r2, r3 800a2da: d00a beq.n 800a2f2 log_printf(LOG_INFO, "CP state changed: %d -> %d\n", prev_state, current_state); 800a2dc: 4b12 ldr r3, [pc, #72] @ (800a328 ) 800a2de: 781b ldrb r3, [r3, #0] 800a2e0: 461a mov r2, r3 800a2e2: 79fb ldrb r3, [r7, #7] 800a2e4: 4912 ldr r1, [pc, #72] @ (800a330 ) 800a2e6: 2007 movs r0, #7 800a2e8: f000 f93e bl 800a568 prev_state = current_state; 800a2ec: 4a0e ldr r2, [pc, #56] @ (800a328 ) 800a2ee: 79fb ldrb r3, [r7, #7] 800a2f0: 7013 strb r3, [r2, #0] } if (current_duty != prev_duty) { 800a2f2: 4b0e ldr r3, [pc, #56] @ (800a32c ) 800a2f4: 781b ldrb r3, [r3, #0] 800a2f6: 79ba ldrb r2, [r7, #6] 800a2f8: 429a cmp r2, r3 800a2fa: d00c beq.n 800a316 log_printf(LOG_INFO, "CP duty changed: %u -> %u\n", prev_duty, current_duty); 800a2fc: 4b0b ldr r3, [pc, #44] @ (800a32c ) 800a2fe: 781b ldrb r3, [r3, #0] 800a300: 461a mov r2, r3 800a302: 79bb ldrb r3, [r7, #6] 800a304: 490b ldr r1, [pc, #44] @ (800a334 ) 800a306: 2007 movs r0, #7 800a308: f000 f92e bl 800a568 prev_duty = current_duty; 800a30c: 4a07 ldr r2, [pc, #28] @ (800a32c ) 800a30e: 79bb ldrb r3, [r7, #6] 800a310: 7013 strb r3, [r2, #0] 800a312: e000 b.n 800a316 if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800a314: bf00 nop } } 800a316: 3708 adds r7, #8 800a318: 46bd mov sp, r7 800a31a: bd80 pop {r7, pc} 800a31c: 200003dc .word 0x200003dc 800a320: 200003d8 .word 0x200003d8 800a324: 200003e0 .word 0x200003e0 800a328: 20000007 .word 0x20000007 800a32c: 200003e1 .word 0x200003e1 800a330: 080174d0 .word 0x080174d0 800a334: 080174ec .word 0x080174ec 0800a338 : CRC_HandleTypeDef hcrc; /* CRC init function */ void MX_CRC_Init(void) { 800a338: b580 push {r7, lr} 800a33a: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 800a33c: 4b06 ldr r3, [pc, #24] @ (800a358 ) 800a33e: 4a07 ldr r2, [pc, #28] @ (800a35c ) 800a340: 601a str r2, [r3, #0] if (HAL_CRC_Init(&hcrc) != HAL_OK) 800a342: 4805 ldr r0, [pc, #20] @ (800a358 ) 800a344: f005 ff71 bl 801022a 800a348: 4603 mov r3, r0 800a34a: 2b00 cmp r3, #0 800a34c: d001 beq.n 800a352 { Error_Handler(); 800a34e: f000 fcc1 bl 800acd4 } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 800a352: bf00 nop 800a354: bd80 pop {r7, pc} 800a356: bf00 nop 800a358: 200003e4 .word 0x200003e4 800a35c: 40023000 .word 0x40023000 0800a360 : void HAL_CRC_MspInit(CRC_HandleTypeDef* crcHandle) { 800a360: b480 push {r7} 800a362: b085 sub sp, #20 800a364: af00 add r7, sp, #0 800a366: 6078 str r0, [r7, #4] if(crcHandle->Instance==CRC) 800a368: 687b ldr r3, [r7, #4] 800a36a: 681b ldr r3, [r3, #0] 800a36c: 4a09 ldr r2, [pc, #36] @ (800a394 ) 800a36e: 4293 cmp r3, r2 800a370: d10b bne.n 800a38a { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* CRC clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 800a372: 4b09 ldr r3, [pc, #36] @ (800a398 ) 800a374: 695b ldr r3, [r3, #20] 800a376: 4a08 ldr r2, [pc, #32] @ (800a398 ) 800a378: f043 0340 orr.w r3, r3, #64 @ 0x40 800a37c: 6153 str r3, [r2, #20] 800a37e: 4b06 ldr r3, [pc, #24] @ (800a398 ) 800a380: 695b ldr r3, [r3, #20] 800a382: f003 0340 and.w r3, r3, #64 @ 0x40 800a386: 60fb str r3, [r7, #12] 800a388: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 800a38a: bf00 nop 800a38c: 3714 adds r7, #20 800a38e: 46bd mov sp, r7 800a390: bc80 pop {r7} 800a392: 4770 bx lr 800a394: 40023000 .word 0x40023000 800a398: 40021000 .word 0x40021000 0800a39c <_write>: #if defined(__GNUC__) int _write(int fd, char * ptr, int len) { 800a39c: b580 push {r7, lr} 800a39e: b084 sub sp, #16 800a3a0: af00 add r7, sp, #0 800a3a2: 60f8 str r0, [r7, #12] 800a3a4: 60b9 str r1, [r7, #8] 800a3a6: 607a str r2, [r7, #4] debug_buffer_add((const uint8_t*)ptr, len); 800a3a8: 687b ldr r3, [r7, #4] 800a3aa: b29b uxth r3, r3 800a3ac: 4619 mov r1, r3 800a3ae: 68b8 ldr r0, [r7, #8] 800a3b0: f000 f806 bl 800a3c0 return len; 800a3b4: 687b ldr r3, [r7, #4] } 800a3b6: 4618 mov r0, r3 800a3b8: 3710 adds r7, #16 800a3ba: 46bd mov sp, r7 800a3bc: bd80 pop {r7, pc} ... 0800a3c0 : #endif // Добавляет данные в кольцевой буфер void debug_buffer_add(const uint8_t* data, uint16_t len) { 800a3c0: b480 push {r7} 800a3c2: b085 sub sp, #20 800a3c4: af00 add r7, sp, #0 800a3c6: 6078 str r0, [r7, #4] 800a3c8: 460b mov r3, r1 800a3ca: 807b strh r3, [r7, #2] \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 800a3cc: b672 cpsid i } 800a3ce: bf00 nop __disable_irq(); for (uint16_t i = 0; i < len; i++) { 800a3d0: 2300 movs r3, #0 800a3d2: 81fb strh r3, [r7, #14] 800a3d4: e045 b.n 800a462 // Если буфер полон, перезаписываем старые данные if (debug_buffer.count >= DEBUG_BUFFER_SIZE) { 800a3d6: 4b28 ldr r3, [pc, #160] @ (800a478 ) 800a3d8: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a3dc: b29b uxth r3, r3 800a3de: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800a3e2: d318 bcc.n 800a416 debug_buffer.read_index = (debug_buffer.read_index + 1) % DEBUG_BUFFER_SIZE; 800a3e4: 4b24 ldr r3, [pc, #144] @ (800a478 ) 800a3e6: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a3ea: b29b uxth r3, r3 800a3ec: 3301 adds r3, #1 800a3ee: 425a negs r2, r3 800a3f0: f3c3 0309 ubfx r3, r3, #0, #10 800a3f4: f3c2 0209 ubfx r2, r2, #0, #10 800a3f8: bf58 it pl 800a3fa: 4253 negpl r3, r2 800a3fc: b29a uxth r2, r3 800a3fe: 4b1e ldr r3, [pc, #120] @ (800a478 ) 800a400: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count--; 800a404: 4b1c ldr r3, [pc, #112] @ (800a478 ) 800a406: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a40a: b29b uxth r3, r3 800a40c: 3b01 subs r3, #1 800a40e: b29a uxth r2, r3 800a410: 4b19 ldr r3, [pc, #100] @ (800a478 ) 800a412: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 } debug_buffer.buffer[debug_buffer.write_index] = data[i]; 800a416: 89fb ldrh r3, [r7, #14] 800a418: 687a ldr r2, [r7, #4] 800a41a: 4413 add r3, r2 800a41c: 4a16 ldr r2, [pc, #88] @ (800a478 ) 800a41e: f8b2 2400 ldrh.w r2, [r2, #1024] @ 0x400 800a422: b292 uxth r2, r2 800a424: 7819 ldrb r1, [r3, #0] 800a426: 4b14 ldr r3, [pc, #80] @ (800a478 ) 800a428: 5499 strb r1, [r3, r2] debug_buffer.write_index = (debug_buffer.write_index + 1) % DEBUG_BUFFER_SIZE; 800a42a: 4b13 ldr r3, [pc, #76] @ (800a478 ) 800a42c: f8b3 3400 ldrh.w r3, [r3, #1024] @ 0x400 800a430: b29b uxth r3, r3 800a432: 3301 adds r3, #1 800a434: 425a negs r2, r3 800a436: f3c3 0309 ubfx r3, r3, #0, #10 800a43a: f3c2 0209 ubfx r2, r2, #0, #10 800a43e: bf58 it pl 800a440: 4253 negpl r3, r2 800a442: b29a uxth r2, r3 800a444: 4b0c ldr r3, [pc, #48] @ (800a478 ) 800a446: f8a3 2400 strh.w r2, [r3, #1024] @ 0x400 debug_buffer.count++; 800a44a: 4b0b ldr r3, [pc, #44] @ (800a478 ) 800a44c: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a450: b29b uxth r3, r3 800a452: 3301 adds r3, #1 800a454: b29a uxth r2, r3 800a456: 4b08 ldr r3, [pc, #32] @ (800a478 ) 800a458: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 for (uint16_t i = 0; i < len; i++) { 800a45c: 89fb ldrh r3, [r7, #14] 800a45e: 3301 adds r3, #1 800a460: 81fb strh r3, [r7, #14] 800a462: 89fa ldrh r2, [r7, #14] 800a464: 887b ldrh r3, [r7, #2] 800a466: 429a cmp r2, r3 800a468: d3b5 bcc.n 800a3d6 __ASM volatile ("cpsie i" : : : "memory"); 800a46a: b662 cpsie i } 800a46c: bf00 nop } __enable_irq(); } 800a46e: bf00 nop 800a470: 3714 adds r7, #20 800a472: 46bd mov sp, r7 800a474: bc80 pop {r7} 800a476: 4770 bx lr 800a478: 200003ec .word 0x200003ec 0800a47c : // Возвращает количество доступных данных в буфере uint16_t debug_buffer_available(void) { 800a47c: b480 push {r7} 800a47e: b083 sub sp, #12 800a480: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a482: b672 cpsid i } 800a484: bf00 nop __disable_irq(); uint16_t count = debug_buffer.count; 800a486: 4b06 ldr r3, [pc, #24] @ (800a4a0 ) 800a488: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a48c: 80fb strh r3, [r7, #6] __ASM volatile ("cpsie i" : : : "memory"); 800a48e: b662 cpsie i } 800a490: bf00 nop __enable_irq(); return count; 800a492: 88fb ldrh r3, [r7, #6] } 800a494: 4618 mov r0, r3 800a496: 370c adds r7, #12 800a498: 46bd mov sp, r7 800a49a: bc80 pop {r7} 800a49c: 4770 bx lr 800a49e: bf00 nop 800a4a0: 200003ec .word 0x200003ec 0800a4a4 : // Отправляет один пакет данных из буфера через SC_SendPacket (не более 250 байт) void debug_buffer_send(void) { 800a4a4: b580 push {r7, lr} 800a4a6: b082 sub sp, #8 800a4a8: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a4aa: b672 cpsid i } 800a4ac: bf00 nop __disable_irq(); // Если буфер пуст, ничего не делаем if (debug_buffer.count == 0) { 800a4ae: 4b2d ldr r3, [pc, #180] @ (800a564 ) 800a4b0: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a4b4: b29b uxth r3, r3 800a4b6: 2b00 cmp r3, #0 800a4b8: d102 bne.n 800a4c0 __ASM volatile ("cpsie i" : : : "memory"); 800a4ba: b662 cpsie i } 800a4bc: bf00 nop __enable_irq(); return; 800a4be: e04e b.n 800a55e } // Определяем сколько байт можно отправить (не более 250) uint16_t bytes_to_send = debug_buffer.count; 800a4c0: 4b28 ldr r3, [pc, #160] @ (800a564 ) 800a4c2: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a4c6: 80fb strh r3, [r7, #6] if (bytes_to_send > DEBUG_BUFFER_MAX_COUNT) { 800a4c8: 88fb ldrh r3, [r7, #6] 800a4ca: 2b80 cmp r3, #128 @ 0x80 800a4cc: d901 bls.n 800a4d2 bytes_to_send = DEBUG_BUFFER_MAX_COUNT; 800a4ce: 2380 movs r3, #128 @ 0x80 800a4d0: 80fb strh r3, [r7, #6] } // Вычисляем сколько байт до конца буфера uint16_t bytes_to_end = DEBUG_BUFFER_SIZE - debug_buffer.read_index; 800a4d2: 4b24 ldr r3, [pc, #144] @ (800a564 ) 800a4d4: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a4d8: b29b uxth r3, r3 800a4da: f5c3 6380 rsb r3, r3, #1024 @ 0x400 800a4de: 80bb strh r3, [r7, #4] // Отправляем только непрерывный блок (до конца буфера или до bytes_to_send) if (bytes_to_send > bytes_to_end) { 800a4e0: 88fa ldrh r2, [r7, #6] 800a4e2: 88bb ldrh r3, [r7, #4] 800a4e4: 429a cmp r2, r3 800a4e6: d901 bls.n 800a4ec bytes_to_send = bytes_to_end; 800a4e8: 88bb ldrh r3, [r7, #4] 800a4ea: 80fb strh r3, [r7, #6] } // Отправляем данные напрямую из буфера if(bytes_to_send == debug_buffer.count){ 800a4ec: 4b1d ldr r3, [pc, #116] @ (800a564 ) 800a4ee: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a4f2: b29b uxth r3, r3 800a4f4: 88fa ldrh r2, [r7, #6] 800a4f6: 429a cmp r2, r3 800a4f8: d10c bne.n 800a514 SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG); 800a4fa: 4b1a ldr r3, [pc, #104] @ (800a564 ) 800a4fc: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a500: b29b uxth r3, r3 800a502: 461a mov r2, r3 800a504: 4b17 ldr r3, [pc, #92] @ (800a564 ) 800a506: 4413 add r3, r2 800a508: 88f9 ldrh r1, [r7, #6] 800a50a: 2250 movs r2, #80 @ 0x50 800a50c: 4618 mov r0, r3 800a50e: f002 fe53 bl 800d1b8 800a512: e00b b.n 800a52c }else{ SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG_CONTINUE); 800a514: 4b13 ldr r3, [pc, #76] @ (800a564 ) 800a516: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a51a: b29b uxth r3, r3 800a51c: 461a mov r2, r3 800a51e: 4b11 ldr r3, [pc, #68] @ (800a564 ) 800a520: 4413 add r3, r2 800a522: 88f9 ldrh r1, [r7, #6] 800a524: 2251 movs r2, #81 @ 0x51 800a526: 4618 mov r0, r3 800a528: f002 fe46 bl 800d1b8 } debug_buffer.read_index = (debug_buffer.read_index + bytes_to_send) % DEBUG_BUFFER_SIZE; 800a52c: 4b0d ldr r3, [pc, #52] @ (800a564 ) 800a52e: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a532: b29a uxth r2, r3 800a534: 88fb ldrh r3, [r7, #6] 800a536: 4413 add r3, r2 800a538: b29b uxth r3, r3 800a53a: f3c3 0309 ubfx r3, r3, #0, #10 800a53e: b29a uxth r2, r3 800a540: 4b08 ldr r3, [pc, #32] @ (800a564 ) 800a542: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count -= bytes_to_send; 800a546: 4b07 ldr r3, [pc, #28] @ (800a564 ) 800a548: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a54c: b29a uxth r2, r3 800a54e: 88fb ldrh r3, [r7, #6] 800a550: 1ad3 subs r3, r2, r3 800a552: b29a uxth r2, r3 800a554: 4b03 ldr r3, [pc, #12] @ (800a564 ) 800a556: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 __ASM volatile ("cpsie i" : : : "memory"); 800a55a: b662 cpsie i } 800a55c: bf00 nop __enable_irq(); } 800a55e: 3708 adds r7, #8 800a560: 46bd mov sp, r7 800a562: bd80 pop {r7, pc} 800a564: 200003ec .word 0x200003ec 0800a568 : #define LOG_BUFFER_SIZE 128 uint8_t log_buffer[LOG_BUFFER_SIZE]; // Кастомный printf с приоритетом лога int log_printf(LogLevel_t level, const char *format, ...) { 800a568: b40e push {r1, r2, r3} 800a56a: b580 push {r7, lr} 800a56c: b085 sub sp, #20 800a56e: af00 add r7, sp, #0 800a570: 4603 mov r3, r0 800a572: 71fb strb r3, [r7, #7] va_list args; int result; // Добавляем приоритет первым байтом log_buffer[0] = (uint8_t)level; 800a574: 4a15 ldr r2, [pc, #84] @ (800a5cc ) 800a576: 79fb ldrb r3, [r7, #7] 800a578: 7013 strb r3, [r2, #0] // Форматируем строку начиная со второго байта va_start(args, format); 800a57a: f107 0320 add.w r3, r7, #32 800a57e: 60bb str r3, [r7, #8] result = vsnprintf((char*)&log_buffer[1], LOG_BUFFER_SIZE - 2, format, args); 800a580: 68bb ldr r3, [r7, #8] 800a582: 69fa ldr r2, [r7, #28] 800a584: 217e movs r1, #126 @ 0x7e 800a586: 4812 ldr r0, [pc, #72] @ (800a5d0 ) 800a588: f00a fd8c bl 80150a4 800a58c: 60f8 str r0, [r7, #12] va_end(args); // Проверяем, не переполнился ли буфер if (result < 0) { 800a58e: 68fb ldr r3, [r7, #12] 800a590: 2b00 cmp r3, #0 800a592: da01 bge.n 800a598 return result; 800a594: 68fb ldr r3, [r7, #12] 800a596: e012 b.n 800a5be } // Ограничиваем размер, чтобы оставить место для нуль-терминатора if (result >= (LOG_BUFFER_SIZE - 2)) { 800a598: 68fb ldr r3, [r7, #12] 800a59a: 2b7d cmp r3, #125 @ 0x7d 800a59c: dd01 ble.n 800a5a2 result = LOG_BUFFER_SIZE - 2; 800a59e: 237e movs r3, #126 @ 0x7e 800a5a0: 60fb str r3, [r7, #12] } // Добавляем нуль-терминатор в конец log_buffer[result + 1] = '\0'; 800a5a2: 68fb ldr r3, [r7, #12] 800a5a4: 3301 adds r3, #1 800a5a6: 4a09 ldr r2, [pc, #36] @ (800a5cc ) 800a5a8: 2100 movs r1, #0 800a5aa: 54d1 strb r1, [r2, r3] // Отправляем в буфер (приоритет + строка + нуль-терминатор) debug_buffer_add(log_buffer, result + 2); 800a5ac: 68fb ldr r3, [r7, #12] 800a5ae: b29b uxth r3, r3 800a5b0: 3302 adds r3, #2 800a5b2: b29b uxth r3, r3 800a5b4: 4619 mov r1, r3 800a5b6: 4805 ldr r0, [pc, #20] @ (800a5cc ) 800a5b8: f7ff ff02 bl 800a3c0 return result; 800a5bc: 68fb ldr r3, [r7, #12] } 800a5be: 4618 mov r0, r3 800a5c0: 3714 adds r7, #20 800a5c2: 46bd mov sp, r7 800a5c4: e8bd 4080 ldmia.w sp!, {r7, lr} 800a5c8: b003 add sp, #12 800a5ca: 4770 bx lr 800a5cc: 200007f4 .word 0x200007f4 800a5d0: 200007f5 .word 0x200007f5 0800a5d4 : /** * Enable DMA controller clock */ void MX_DMA_Init(void) { 800a5d4: b580 push {r7, lr} 800a5d6: b082 sub sp, #8 800a5d8: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 800a5da: 4b1c ldr r3, [pc, #112] @ (800a64c ) 800a5dc: 695b ldr r3, [r3, #20] 800a5de: 4a1b ldr r2, [pc, #108] @ (800a64c ) 800a5e0: f043 0301 orr.w r3, r3, #1 800a5e4: 6153 str r3, [r2, #20] 800a5e6: 4b19 ldr r3, [pc, #100] @ (800a64c ) 800a5e8: 695b ldr r3, [r3, #20] 800a5ea: f003 0301 and.w r3, r3, #1 800a5ee: 607b str r3, [r7, #4] 800a5f0: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 1, 0); 800a5f2: 2200 movs r2, #0 800a5f4: 2101 movs r1, #1 800a5f6: 200b movs r0, #11 800a5f8: f005 fde1 bl 80101be HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 800a5fc: 200b movs r0, #11 800a5fe: f005 fdfa bl 80101f6 /* DMA1_Channel2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 4, 0); 800a602: 2200 movs r2, #0 800a604: 2104 movs r1, #4 800a606: 200c movs r0, #12 800a608: f005 fdd9 bl 80101be HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); 800a60c: 200c movs r0, #12 800a60e: f005 fdf2 bl 80101f6 /* DMA1_Channel3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 1, 0); 800a612: 2200 movs r2, #0 800a614: 2101 movs r1, #1 800a616: 200d movs r0, #13 800a618: f005 fdd1 bl 80101be HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn); 800a61c: 200d movs r0, #13 800a61e: f005 fdea bl 80101f6 /* DMA1_Channel6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel6_IRQn, 1, 0); 800a622: 2200 movs r2, #0 800a624: 2101 movs r1, #1 800a626: 2010 movs r0, #16 800a628: f005 fdc9 bl 80101be HAL_NVIC_EnableIRQ(DMA1_Channel6_IRQn); 800a62c: 2010 movs r0, #16 800a62e: f005 fde2 bl 80101f6 /* DMA1_Channel7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 4, 0); 800a632: 2200 movs r2, #0 800a634: 2104 movs r1, #4 800a636: 2011 movs r0, #17 800a638: f005 fdc1 bl 80101be HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn); 800a63c: 2011 movs r0, #17 800a63e: f005 fdda bl 80101f6 } 800a642: bf00 nop 800a644: 3708 adds r7, #8 800a646: 46bd mov sp, r7 800a648: bd80 pop {r7, pc} 800a64a: bf00 nop 800a64c: 40021000 .word 0x40021000 0800a650 : #include "debug.h" #include "serial.h" static uint8_t fire_alarm_latched = 0; uint8_t FireAlarm_IsLatched(void) { 800a650: b480 push {r7} 800a652: af00 add r7, sp, #0 return fire_alarm_latched; 800a654: 4b02 ldr r3, [pc, #8] @ (800a660 ) 800a656: 781b ldrb r3, [r3, #0] } 800a658: 4618 mov r0, r3 800a65a: 46bd mov sp, r7 800a65c: bc80 pop {r7} 800a65e: 4770 bx lr 800a660: 20000874 .word 0x20000874 0800a664 : void FireAlarm_Activate(void) { 800a664: b580 push {r7, lr} 800a666: af00 add r7, sp, #0 if (fire_alarm_latched) { 800a668: 4b06 ldr r3, [pc, #24] @ (800a684 ) 800a66a: 781b ldrb r3, [r3, #0] 800a66c: 2b00 cmp r3, #0 800a66e: d107 bne.n 800a680 return; } fire_alarm_latched = 1; 800a670: 4b04 ldr r3, [pc, #16] @ (800a684 ) 800a672: 2201 movs r2, #1 800a674: 701a strb r2, [r3, #0] log_printf(LOG_ERR, "FIRE ALARM activated\n"); 800a676: 4904 ldr r1, [pc, #16] @ (800a688 ) 800a678: 2004 movs r0, #4 800a67a: f7ff ff75 bl 800a568 800a67e: e000 b.n 800a682 return; 800a680: bf00 nop } 800a682: bd80 pop {r7, pc} 800a684: 20000874 .word 0x20000874 800a688: 08017508 .word 0x08017508 0800a68c : * EXTI PB8 ------> I2C1_SCL PB9 ------> I2C1_SDA */ void MX_GPIO_Init(void) { 800a68c: b580 push {r7, lr} 800a68e: b08a sub sp, #40 @ 0x28 800a690: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800a692: f107 0314 add.w r3, r7, #20 800a696: 2200 movs r2, #0 800a698: 601a str r2, [r3, #0] 800a69a: 605a str r2, [r3, #4] 800a69c: 609a str r2, [r3, #8] 800a69e: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 800a6a0: 4b94 ldr r3, [pc, #592] @ (800a8f4 ) 800a6a2: 699b ldr r3, [r3, #24] 800a6a4: 4a93 ldr r2, [pc, #588] @ (800a8f4 ) 800a6a6: f043 0310 orr.w r3, r3, #16 800a6aa: 6193 str r3, [r2, #24] 800a6ac: 4b91 ldr r3, [pc, #580] @ (800a8f4 ) 800a6ae: 699b ldr r3, [r3, #24] 800a6b0: f003 0310 and.w r3, r3, #16 800a6b4: 613b str r3, [r7, #16] 800a6b6: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800a6b8: 4b8e ldr r3, [pc, #568] @ (800a8f4 ) 800a6ba: 699b ldr r3, [r3, #24] 800a6bc: 4a8d ldr r2, [pc, #564] @ (800a8f4 ) 800a6be: f043 0304 orr.w r3, r3, #4 800a6c2: 6193 str r3, [r2, #24] 800a6c4: 4b8b ldr r3, [pc, #556] @ (800a8f4 ) 800a6c6: 699b ldr r3, [r3, #24] 800a6c8: f003 0304 and.w r3, r3, #4 800a6cc: 60fb str r3, [r7, #12] 800a6ce: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 800a6d0: 4b88 ldr r3, [pc, #544] @ (800a8f4 ) 800a6d2: 699b ldr r3, [r3, #24] 800a6d4: 4a87 ldr r2, [pc, #540] @ (800a8f4 ) 800a6d6: f043 0308 orr.w r3, r3, #8 800a6da: 6193 str r3, [r2, #24] 800a6dc: 4b85 ldr r3, [pc, #532] @ (800a8f4 ) 800a6de: 699b ldr r3, [r3, #24] 800a6e0: f003 0308 and.w r3, r3, #8 800a6e4: 60bb str r3, [r7, #8] 800a6e6: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOE_CLK_ENABLE(); 800a6e8: 4b82 ldr r3, [pc, #520] @ (800a8f4 ) 800a6ea: 699b ldr r3, [r3, #24] 800a6ec: 4a81 ldr r2, [pc, #516] @ (800a8f4 ) 800a6ee: f043 0340 orr.w r3, r3, #64 @ 0x40 800a6f2: 6193 str r3, [r2, #24] 800a6f4: 4b7f ldr r3, [pc, #508] @ (800a8f4 ) 800a6f6: 699b ldr r3, [r3, #24] 800a6f8: f003 0340 and.w r3, r3, #64 @ 0x40 800a6fc: 607b str r3, [r7, #4] 800a6fe: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 800a700: 4b7c ldr r3, [pc, #496] @ (800a8f4 ) 800a702: 699b ldr r3, [r3, #24] 800a704: 4a7b ldr r2, [pc, #492] @ (800a8f4 ) 800a706: f043 0320 orr.w r3, r3, #32 800a70a: 6193 str r3, [r2, #24] 800a70c: 4b79 ldr r3, [pc, #484] @ (800a8f4 ) 800a70e: 699b ldr r3, [r3, #24] 800a710: f003 0320 and.w r3, r3, #32 800a714: 603b str r3, [r7, #0] 800a716: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, DBG1_Pin|RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin 800a718: 2200 movs r2, #0 800a71a: f44f 710f mov.w r1, #572 @ 0x23c 800a71e: 4876 ldr r0, [pc, #472] @ (800a8f8 ) 800a720: f006 fbc9 bl 8010eb6 |LED_DATA_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, DBG2_Pin|DBG3_Pin|RELAY_CC_Pin, GPIO_PIN_RESET); 800a724: 2200 movs r2, #0 800a726: f248 0160 movw r1, #32864 @ 0x8060 800a72a: 4874 ldr r0, [pc, #464] @ (800a8fc ) 800a72c: f006 fbc3 bl 8010eb6 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a730: 2200 movs r2, #0 800a732: f44f 51f8 mov.w r1, #7936 @ 0x1f00 800a736: 4872 ldr r0, [pc, #456] @ (800a900 ) 800a738: f006 fbbd bl 8010eb6 |RELAY5_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, DBG5_Pin|DBG4_Pin|EE_WP_Pin, GPIO_PIN_RESET); 800a73c: 2200 movs r2, #0 800a73e: f44f 6148 mov.w r1, #3200 @ 0xc80 800a742: 4870 ldr r0, [pc, #448] @ (800a904 ) 800a744: f006 fbb7 bl 8010eb6 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, RELAY_DC_Pin|USART2_DIR_Pin, GPIO_PIN_RESET); 800a748: 2200 movs r2, #0 800a74a: 2118 movs r1, #24 800a74c: 486e ldr r0, [pc, #440] @ (800a908 ) 800a74e: f006 fbb2 bl 8010eb6 /*Configure GPIO pins : DBG1_Pin LED_DATA_Pin */ GPIO_InitStruct.Pin = DBG1_Pin|LED_DATA_Pin; 800a752: f44f 7301 mov.w r3, #516 @ 0x204 800a756: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a758: 2301 movs r3, #1 800a75a: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a75c: 2300 movs r3, #0 800a75e: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a760: 2303 movs r3, #3 800a762: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800a764: f107 0314 add.w r3, r7, #20 800a768: 4619 mov r1, r3 800a76a: 4863 ldr r0, [pc, #396] @ (800a8f8 ) 800a76c: f006 fa08 bl 8010b80 /*Configure GPIO pins : RELAY_CP_Pin LOCK_A_Pin LOCK_B_Pin */ GPIO_InitStruct.Pin = RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin; 800a770: 2338 movs r3, #56 @ 0x38 800a772: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a774: 2301 movs r3, #1 800a776: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a778: 2300 movs r3, #0 800a77a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a77c: 2302 movs r3, #2 800a77e: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800a780: f107 0314 add.w r3, r7, #20 800a784: 4619 mov r1, r3 800a786: 485c ldr r0, [pc, #368] @ (800a8f8 ) 800a788: f006 f9fa bl 8010b80 /*Configure GPIO pin : IN_SW0_Pin */ GPIO_InitStruct.Pin = IN_SW0_Pin; 800a78c: 2302 movs r3, #2 800a78e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a790: 2300 movs r3, #0 800a792: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a794: 2300 movs r3, #0 800a796: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW0_GPIO_Port, &GPIO_InitStruct); 800a798: f107 0314 add.w r3, r7, #20 800a79c: 4619 mov r1, r3 800a79e: 4857 ldr r0, [pc, #348] @ (800a8fc ) 800a7a0: f006 f9ee bl 8010b80 /*Configure GPIO pin : IN_SW1_Pin */ GPIO_InitStruct.Pin = IN_SW1_Pin; 800a7a4: 2304 movs r3, #4 800a7a6: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a7a8: 2300 movs r3, #0 800a7aa: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 800a7ac: 2302 movs r3, #2 800a7ae: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW1_GPIO_Port, &GPIO_InitStruct); 800a7b0: f107 0314 add.w r3, r7, #20 800a7b4: 4619 mov r1, r3 800a7b6: 4851 ldr r0, [pc, #324] @ (800a8fc ) 800a7b8: f006 f9e2 bl 8010b80 /*Configure GPIO pins : DBG2_Pin DBG3_Pin */ GPIO_InitStruct.Pin = DBG2_Pin|DBG3_Pin; 800a7bc: 2360 movs r3, #96 @ 0x60 800a7be: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a7c0: 2301 movs r3, #1 800a7c2: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a7c4: 2300 movs r3, #0 800a7c6: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a7c8: 2303 movs r3, #3 800a7ca: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800a7cc: f107 0314 add.w r3, r7, #20 800a7d0: 4619 mov r1, r3 800a7d2: 484a ldr r0, [pc, #296] @ (800a8fc ) 800a7d4: f006 f9d4 bl 8010b80 /*Configure GPIO pins : IN0_Pin AC_OK_Pin ISO_IN_Pin */ GPIO_InitStruct.Pin = IN0_Pin|AC_OK_Pin|ISO_IN_Pin; 800a7d8: f244 0382 movw r3, #16514 @ 0x4082 800a7dc: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a7de: 2300 movs r3, #0 800a7e0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a7e2: 2300 movs r3, #0 800a7e4: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a7e6: f107 0314 add.w r3, r7, #20 800a7ea: 4619 mov r1, r3 800a7ec: 4844 ldr r0, [pc, #272] @ (800a900 ) 800a7ee: f006 f9c7 bl 8010b80 /*Configure GPIO pins : RELAY1_Pin RELAY2_Pin RELAY3_Pin RELAY4_Pin RELAY5_Pin */ GPIO_InitStruct.Pin = RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a7f2: f44f 53f8 mov.w r3, #7936 @ 0x1f00 800a7f6: 617b str r3, [r7, #20] |RELAY5_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a7f8: 2301 movs r3, #1 800a7fa: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a7fc: 2300 movs r3, #0 800a7fe: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a800: 2302 movs r3, #2 800a802: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a804: f107 0314 add.w r3, r7, #20 800a808: 4619 mov r1, r3 800a80a: 483d ldr r0, [pc, #244] @ (800a900 ) 800a80c: f006 f9b8 bl 8010b80 /*Configure GPIO pins : DBG5_Pin DBG4_Pin */ GPIO_InitStruct.Pin = DBG5_Pin|DBG4_Pin; 800a810: f44f 6340 mov.w r3, #3072 @ 0xc00 800a814: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a816: 2301 movs r3, #1 800a818: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a81a: 2300 movs r3, #0 800a81c: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a81e: 2303 movs r3, #3 800a820: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a822: f107 0314 add.w r3, r7, #20 800a826: 4619 mov r1, r3 800a828: 4836 ldr r0, [pc, #216] @ (800a904 ) 800a82a: f006 f9a9 bl 8010b80 /*Configure GPIO pin : RELAY_CC_Pin */ GPIO_InitStruct.Pin = RELAY_CC_Pin; 800a82e: f44f 4300 mov.w r3, #32768 @ 0x8000 800a832: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a834: 2301 movs r3, #1 800a836: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a838: 2300 movs r3, #0 800a83a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a83c: 2302 movs r3, #2 800a83e: 623b str r3, [r7, #32] HAL_GPIO_Init(RELAY_CC_GPIO_Port, &GPIO_InitStruct); 800a840: f107 0314 add.w r3, r7, #20 800a844: 4619 mov r1, r3 800a846: 482d ldr r0, [pc, #180] @ (800a8fc ) 800a848: f006 f99a bl 8010b80 /*Configure GPIO pins : RELAY_DC_Pin USART2_DIR_Pin */ GPIO_InitStruct.Pin = RELAY_DC_Pin|USART2_DIR_Pin; 800a84c: 2318 movs r3, #24 800a84e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a850: 2301 movs r3, #1 800a852: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a854: 2300 movs r3, #0 800a856: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a858: 2302 movs r3, #2 800a85a: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800a85c: f107 0314 add.w r3, r7, #20 800a860: 4619 mov r1, r3 800a862: 4829 ldr r0, [pc, #164] @ (800a908 ) 800a864: f006 f98c bl 8010b80 /*Configure GPIO pin : IN_ESTOP_Pin */ GPIO_InitStruct.Pin = IN_ESTOP_Pin; 800a868: 2380 movs r3, #128 @ 0x80 800a86a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a86c: 2300 movs r3, #0 800a86e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a870: 2300 movs r3, #0 800a872: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_ESTOP_GPIO_Port, &GPIO_InitStruct); 800a874: f107 0314 add.w r3, r7, #20 800a878: 4619 mov r1, r3 800a87a: 4823 ldr r0, [pc, #140] @ (800a908 ) 800a87c: f006 f980 bl 8010b80 /*Configure GPIO pins : IN_FB2_Pin IN_FB1_Pin */ GPIO_InitStruct.Pin = IN_FB2_Pin|IN_FB1_Pin; 800a880: 2318 movs r3, #24 800a882: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a884: 2300 movs r3, #0 800a886: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a888: 2300 movs r3, #0 800a88a: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a88c: f107 0314 add.w r3, r7, #20 800a890: 4619 mov r1, r3 800a892: 481c ldr r0, [pc, #112] @ (800a904 ) 800a894: f006 f974 bl 8010b80 /*Configure GPIO pin : EE_WP_Pin */ GPIO_InitStruct.Pin = EE_WP_Pin; 800a898: 2380 movs r3, #128 @ 0x80 800a89a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a89c: 2301 movs r3, #1 800a89e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a8a0: 2300 movs r3, #0 800a8a2: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a8a4: 2302 movs r3, #2 800a8a6: 623b str r3, [r7, #32] HAL_GPIO_Init(EE_WP_GPIO_Port, &GPIO_InitStruct); 800a8a8: f107 0314 add.w r3, r7, #20 800a8ac: 4619 mov r1, r3 800a8ae: 4815 ldr r0, [pc, #84] @ (800a904 ) 800a8b0: f006 f966 bl 8010b80 /*Configure GPIO pins : PB8 PB9 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 800a8b4: f44f 7340 mov.w r3, #768 @ 0x300 800a8b8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 800a8ba: 2312 movs r3, #18 800a8bc: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a8be: 2303 movs r3, #3 800a8c0: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a8c2: f107 0314 add.w r3, r7, #20 800a8c6: 4619 mov r1, r3 800a8c8: 480e ldr r0, [pc, #56] @ (800a904 ) 800a8ca: f006 f959 bl 8010b80 /*Configure peripheral I/O remapping */ __HAL_AFIO_REMAP_I2C1_ENABLE(); 800a8ce: 4b0f ldr r3, [pc, #60] @ (800a90c ) 800a8d0: 685b ldr r3, [r3, #4] 800a8d2: 627b str r3, [r7, #36] @ 0x24 800a8d4: 6a7b ldr r3, [r7, #36] @ 0x24 800a8d6: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800a8da: 627b str r3, [r7, #36] @ 0x24 800a8dc: 6a7b ldr r3, [r7, #36] @ 0x24 800a8de: f043 0302 orr.w r3, r3, #2 800a8e2: 627b str r3, [r7, #36] @ 0x24 800a8e4: 4a09 ldr r2, [pc, #36] @ (800a90c ) 800a8e6: 6a7b ldr r3, [r7, #36] @ 0x24 800a8e8: 6053 str r3, [r2, #4] } 800a8ea: bf00 nop 800a8ec: 3728 adds r7, #40 @ 0x28 800a8ee: 46bd mov sp, r7 800a8f0: bd80 pop {r7, pc} 800a8f2: bf00 nop 800a8f4: 40021000 .word 0x40021000 800a8f8: 40011000 .word 0x40011000 800a8fc: 40010800 .word 0x40010800 800a900: 40011800 .word 0x40011800 800a904: 40010c00 .word 0x40010c00 800a908: 40011400 .word 0x40011400 800a90c: 40010000 .word 0x40010000 0800a910 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 800a910: b480 push {r7} 800a912: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 800a914: f3bf 8f4f dsb sy } 800a918: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800a91a: 4b06 ldr r3, [pc, #24] @ (800a934 <__NVIC_SystemReset+0x24>) 800a91c: 68db ldr r3, [r3, #12] 800a91e: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800a922: 4904 ldr r1, [pc, #16] @ (800a934 <__NVIC_SystemReset+0x24>) 800a924: 4b04 ldr r3, [pc, #16] @ (800a938 <__NVIC_SystemReset+0x28>) 800a926: 4313 orrs r3, r2 800a928: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800a92a: f3bf 8f4f dsb sy } 800a92e: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 800a930: bf00 nop 800a932: e7fd b.n 800a930 <__NVIC_SystemReset+0x20> 800a934: e000ed00 .word 0xe000ed00 800a938: 05fa0004 .word 0x05fa0004 0800a93c : * bootloader before starting this program. Unfortunately, function * SystemInit() overwrites this change again. * @return none. */ static void VectorBase_Config(void) { 800a93c: b480 push {r7} 800a93e: af00 add r7, sp, #0 * c-startup code. */ extern const unsigned long g_pfnVectors[]; /* Remap the vector table to where the vector table is located for this program. */ SCB->VTOR = (unsigned long)&g_pfnVectors[0]; 800a940: 4b03 ldr r3, [pc, #12] @ (800a950 ) 800a942: 4a04 ldr r2, [pc, #16] @ (800a954 ) 800a944: 609a str r2, [r3, #8] } 800a946: bf00 nop 800a948: 46bd mov sp, r7 800a94a: bc80 pop {r7} 800a94c: 4770 bx lr 800a94e: bf00 nop 800a950: e000ed00 .word 0xe000ed00 800a954: 08008000 .word 0x08008000 0800a958 : uint8_t ED_TraceWarning(uint8_t flag, uint8_t id){ 800a958: b480 push {r7} 800a95a: b085 sub sp, #20 800a95c: af00 add r7, sp, #0 800a95e: 4603 mov r3, r0 800a960: 460a mov r2, r1 800a962: 71fb strb r3, [r7, #7] 800a964: 4613 mov r3, r2 800a966: 71bb strb r3, [r7, #6] static uint8_t memory[32]; if(id > 31) return 0; 800a968: 79bb ldrb r3, [r7, #6] 800a96a: 2b1f cmp r3, #31 800a96c: d901 bls.n 800a972 800a96e: 2300 movs r3, #0 800a970: e00e b.n 800a990 uint8_t result = 0; 800a972: 2300 movs r3, #0 800a974: 73fb strb r3, [r7, #15] if(memory[id] != flag){ 800a976: 79bb ldrb r3, [r7, #6] 800a978: 4a08 ldr r2, [pc, #32] @ (800a99c ) 800a97a: 5cd3 ldrb r3, [r2, r3] 800a97c: 79fa ldrb r2, [r7, #7] 800a97e: 429a cmp r2, r3 800a980: d001 beq.n 800a986 result = 1; 800a982: 2301 movs r3, #1 800a984: 73fb strb r3, [r7, #15] } memory[id] = flag; 800a986: 79bb ldrb r3, [r7, #6] 800a988: 4904 ldr r1, [pc, #16] @ (800a99c ) 800a98a: 79fa ldrb r2, [r7, #7] 800a98c: 54ca strb r2, [r1, r3] return result; 800a98e: 7bfb ldrb r3, [r7, #15] } 800a990: 4618 mov r0, r3 800a992: 3714 adds r7, #20 800a994: 46bd mov sp, r7 800a996: bc80 pop {r7} 800a998: 4770 bx lr 800a99a: bf00 nop 800a99c: 20000878 .word 0x20000878 0800a9a0 : void ED_Delay(uint32_t Delay) { 800a9a0: b580 push {r7, lr} 800a9a2: b084 sub sp, #16 800a9a4: af00 add r7, sp, #0 800a9a6: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800a9a8: f003 feee bl 800e788 800a9ac: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800a9ae: 687b ldr r3, [r7, #4] 800a9b0: 60fb str r3, [r7, #12] if (wait < HAL_MAX_DELAY) 800a9b2: 68fb ldr r3, [r7, #12] 800a9b4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800a9b8: d010 beq.n 800a9dc { wait += (uint32_t)(uwTickFreq); 800a9ba: 4b0f ldr r3, [pc, #60] @ (800a9f8 ) 800a9bc: 781b ldrb r3, [r3, #0] 800a9be: 461a mov r2, r3 800a9c0: 68fb ldr r3, [r7, #12] 800a9c2: 4413 add r3, r2 800a9c4: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait){ 800a9c6: e009 b.n 800a9dc CCS_SerialLoop(); 800a9c8: f001 fc44 bl 800c254 StopButtonControl(); 800a9cc: f000 f816 bl 800a9fc CP_Loop(); 800a9d0: f7ff fc58 bl 800a284 LED_Task(); 800a9d4: f001 fa00 bl 800bdd8 SC_Task(); 800a9d8: f002 fa94 bl 800cf04 while ((HAL_GetTick() - tickstart) < wait){ 800a9dc: f003 fed4 bl 800e788 800a9e0: 4602 mov r2, r0 800a9e2: 68bb ldr r3, [r7, #8] 800a9e4: 1ad3 subs r3, r2, r3 800a9e6: 68fa ldr r2, [r7, #12] 800a9e8: 429a cmp r2, r3 800a9ea: d8ed bhi.n 800a9c8 } } 800a9ec: bf00 nop 800a9ee: bf00 nop 800a9f0: 3710 adds r7, #16 800a9f2: 46bd mov sp, r7 800a9f4: bd80 pop {r7, pc} 800a9f6: bf00 nop 800a9f8: 2000008c .word 0x2000008c 0800a9fc : static void StopButtonControl(void){ 800a9fc: b580 push {r7, lr} 800a9fe: b082 sub sp, #8 800aa00: af00 add r7, sp, #0 static uint32_t tick; static uint32_t hold_time; static uint8_t stop_btn_fault = 1; uint32_t now = HAL_GetTick(); 800aa02: f003 fec1 bl 800e788 800aa06: 6078 str r0, [r7, #4] /* Run no faster than once per 10 ms. */ if((now - tick) < 10){ 800aa08: 4b2a ldr r3, [pc, #168] @ (800aab4 ) 800aa0a: 681b ldr r3, [r3, #0] 800aa0c: 687a ldr r2, [r7, #4] 800aa0e: 1ad3 subs r3, r2, r3 800aa10: 2b09 cmp r3, #9 800aa12: d949 bls.n 800aaa8 return; } tick = now; 800aa14: 4a27 ldr r2, [pc, #156] @ (800aab4 ) 800aa16: 687b ldr r3, [r7, #4] 800aa18: 6013 str r3, [r2, #0] uint8_t pressed = !IN_ReadInput(IN_ESTOP); 800aa1a: 2003 movs r0, #3 800aa1c: f7fe ff4c bl 80098b8 800aa20: 4603 mov r3, r0 800aa22: 2b00 cmp r3, #0 800aa24: bf0c ite eq 800aa26: 2301 moveq r3, #1 800aa28: 2300 movne r3, #0 800aa2a: b2db uxtb r3, r3 800aa2c: 70fb strb r3, [r7, #3] if(!pressed){ 800aa2e: 78fb ldrb r3, [r7, #3] 800aa30: 2b00 cmp r3, #0 800aa32: d102 bne.n 800aa3a stop_btn_fault = 0; 800aa34: 4b20 ldr r3, [pc, #128] @ (800aab8 ) 800aa36: 2200 movs r2, #0 800aa38: 701a strb r2, [r3, #0] } if(stop_btn_fault){ 800aa3a: 4b1f ldr r3, [pc, #124] @ (800aab8 ) 800aa3c: 781b ldrb r3, [r3, #0] 800aa3e: 2b00 cmp r3, #0 800aa40: d134 bne.n 800aaac return; } if(pressed){ 800aa42: 78fb ldrb r3, [r7, #3] 800aa44: 2b00 cmp r3, #0 800aa46: d02b beq.n 800aaa0 if(hold_time == 0){ 800aa48: 4b1c ldr r3, [pc, #112] @ (800aabc ) 800aa4a: 681b ldr r3, [r3, #0] 800aa4c: 2b00 cmp r3, #0 800aa4e: d102 bne.n 800aa56 CONN.connControl = CMD_STOP; 800aa50: 4b1b ldr r3, [pc, #108] @ (800aac0 ) 800aa52: 2201 movs r2, #1 800aa54: 701a strb r2, [r3, #0] } hold_time += 10; 800aa56: 4b19 ldr r3, [pc, #100] @ (800aabc ) 800aa58: 681b ldr r3, [r3, #0] 800aa5a: 330a adds r3, #10 800aa5c: 4a17 ldr r2, [pc, #92] @ (800aabc ) 800aa5e: 6013 str r3, [r2, #0] if(hold_time == 5000){ 800aa60: 4b16 ldr r3, [pc, #88] @ (800aabc ) 800aa62: 681b ldr r3, [r3, #0] 800aa64: f241 3288 movw r2, #5000 @ 0x1388 800aa68: 4293 cmp r3, r2 800aa6a: d102 bne.n 800aa72 CONN.connControl = CMD_FORCE_UNLOCK; 800aa6c: 4b14 ldr r3, [pc, #80] @ (800aac0 ) 800aa6e: 2203 movs r2, #3 800aa70: 701a strb r2, [r3, #0] } if(hold_time > 40000){ 800aa72: 4b12 ldr r3, [pc, #72] @ (800aabc ) 800aa74: 681b ldr r3, [r3, #0] 800aa76: f649 4240 movw r2, #40000 @ 0x9c40 800aa7a: 4293 cmp r3, r2 800aa7c: d917 bls.n 800aaae SC_SendPacket(NULL, 0, RESP_SUCCESS); 800aa7e: 2212 movs r2, #18 800aa80: 2100 movs r1, #0 800aa82: 2000 movs r0, #0 800aa84: f002 fb98 bl 800d1b8 while(huart2.gState == HAL_UART_STATE_BUSY_TX); 800aa88: bf00 nop 800aa8a: 4b0e ldr r3, [pc, #56] @ (800aac4 ) 800aa8c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800aa90: b2db uxtb r3, r3 800aa92: 2b21 cmp r3, #33 @ 0x21 800aa94: d0f9 beq.n 800aa8a HAL_Delay(10); 800aa96: 200a movs r0, #10 800aa98: f003 fe80 bl 800e79c NVIC_SystemReset(); 800aa9c: f7ff ff38 bl 800a910 <__NVIC_SystemReset> } } else{ hold_time = 0; 800aaa0: 4b06 ldr r3, [pc, #24] @ (800aabc ) 800aaa2: 2200 movs r2, #0 800aaa4: 601a str r2, [r3, #0] 800aaa6: e002 b.n 800aaae return; 800aaa8: bf00 nop 800aaaa: e000 b.n 800aaae return; 800aaac: bf00 nop } } 800aaae: 3708 adds r7, #8 800aab0: 46bd mov sp, r7 800aab2: bd80 pop {r7, pc} 800aab4: 20000898 .word 0x20000898 800aab8: 20000008 .word 0x20000008 800aabc: 2000089c .word 0x2000089c 800aac0: 200003b0 .word 0x200003b0 800aac4: 200012fc .word 0x200012fc 0800aac8 : static void CAN1_MinimalReInit(void) { 800aac8: b580 push {r7, lr} 800aaca: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan1); 800aacc: 480b ldr r0, [pc, #44] @ (800aafc ) 800aace: f004 fde9 bl 800f6a4 MX_CAN1_Init(); 800aad2: f7ff f865 bl 8009ba0 if (HAL_CAN_Start(&hcan1) != HAL_OK) { 800aad6: 4809 ldr r0, [pc, #36] @ (800aafc ) 800aad8: f004 fda0 bl 800f61c 800aadc: 4603 mov r3, r0 800aade: 2b00 cmp r3, #0 800aae0: d001 beq.n 800aae6 Error_Handler(); 800aae2: f000 f8f7 bl 800acd4 } if (HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) { 800aae6: 2102 movs r1, #2 800aae8: 4804 ldr r0, [pc, #16] @ (800aafc ) 800aaea: f005 f848 bl 800fb7e 800aaee: 4603 mov r3, r0 800aaf0: 2b00 cmp r3, #0 800aaf2: d001 beq.n 800aaf8 Error_Handler(); 800aaf4: f000 f8ee bl 800acd4 } } 800aaf8: bf00 nop 800aafa: bd80 pop {r7, pc} 800aafc: 2000035c .word 0x2000035c 0800ab00
: /** * @brief The application entry point. * @retval int */ int main(void) { 800ab00: b580 push {r7, lr} 800ab02: b082 sub sp, #8 800ab04: af02 add r7, sp, #8 /* USER CODE BEGIN 1 */ VectorBase_Config(); 800ab06: f7ff ff19 bl 800a93c /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800ab0a: f003 fde5 bl 800e6d8 /* USER CODE BEGIN Init */ HAL_RCC_DeInit(); 800ab0e: f006 f9f7 bl 8010f00 /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800ab12: f000 f86f bl 800abf4 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800ab16: f7ff fdb9 bl 800a68c MX_DMA_Init(); 800ab1a: f7ff fd5b bl 800a5d4 MX_ADC1_Init(); 800ab1e: f7fe fd3b bl 8009598 MX_CAN1_Init(); 800ab22: f7ff f83d bl 8009ba0 MX_CAN2_Init(); 800ab26: f7ff f871 bl 8009c0c MX_RTC_Init(); 800ab2a: f001 f9f9 bl 800bf20 MX_TIM4_Init(); 800ab2e: f003 f9db bl 800dee8 MX_USART2_UART_Init(); 800ab32: f003 fb59 bl 800e1e8 MX_CRC_Init(); 800ab36: f7ff fbff bl 800a338 MX_UART5_Init(); 800ab3a: f003 fb01 bl 800e140 MX_USART1_UART_Init(); 800ab3e: f003 fb29 bl 800e194 MX_USART3_UART_Init(); 800ab42: f003 fb7b bl 800e23c MX_TIM3_Init(); 800ab46: f003 f941 bl 800ddcc /* USER CODE BEGIN 2 */ Init_Peripheral(); 800ab4a: f7fe ff2f bl 80099ac LED_Init(); 800ab4e: f001 f91f bl 800bd90 HAL_Delay(300); 800ab52: f44f 7096 mov.w r0, #300 @ 0x12c 800ab56: f003 fe21 bl 800e79c CCS_Init(); 800ab5a: f001 fe13 bl 800c784 SC_Init(); 800ab5e: f002 f9a7 bl 800ceb0 log_printf(LOG_INFO, "CCS module start\n"); 800ab62: 491f ldr r1, [pc, #124] @ (800abe0 ) 800ab64: 2007 movs r0, #7 800ab66: f7ff fcff bl 800a568 ReadVersion(); 800ab6a: f002 f97d bl 800ce68 log_printf(LOG_INFO, "Serial number: %d\n", infoPacket.serialNumber); 800ab6e: 4b1d ldr r3, [pc, #116] @ (800abe4 ) 800ab70: 881b ldrh r3, [r3, #0] 800ab72: b29b uxth r3, r3 800ab74: 461a mov r2, r3 800ab76: 491c ldr r1, [pc, #112] @ (800abe8 ) 800ab78: 2007 movs r0, #7 800ab7a: f7ff fcf5 bl 800a568 log_printf(LOG_INFO, "Board revision: %d\n", infoPacket.boardVersion); 800ab7e: 4b19 ldr r3, [pc, #100] @ (800abe4 ) 800ab80: 789b ldrb r3, [r3, #2] 800ab82: 461a mov r2, r3 800ab84: 4919 ldr r1, [pc, #100] @ (800abec ) 800ab86: 2007 movs r0, #7 800ab88: f7ff fcee bl 800a568 log_printf(LOG_INFO, "FW version: %d.%d.%d\n", infoPacket.fw_version_major, infoPacket.fw_version_minor, infoPacket.fw_version_patch); 800ab8c: 4b15 ldr r3, [pc, #84] @ (800abe4 ) 800ab8e: 889b ldrh r3, [r3, #4] 800ab90: b29b uxth r3, r3 800ab92: 461a mov r2, r3 800ab94: 4b13 ldr r3, [pc, #76] @ (800abe4 ) 800ab96: 88db ldrh r3, [r3, #6] 800ab98: b29b uxth r3, r3 800ab9a: 4619 mov r1, r3 800ab9c: 4b11 ldr r3, [pc, #68] @ (800abe4 ) 800ab9e: 891b ldrh r3, [r3, #8] 800aba0: b29b uxth r3, r3 800aba2: 9300 str r3, [sp, #0] 800aba4: 460b mov r3, r1 800aba6: 4912 ldr r1, [pc, #72] @ (800abf0 ) 800aba8: 2007 movs r0, #7 800abaa: f7ff fcdd bl 800a568 CAN1_MinimalReInit(); 800abae: f7ff ff8b bl 800aac8 PSU_Init(); 800abb2: f000 f9e5 bl 800af80 CONN_Init(); 800abb6: f7ff f93d bl 8009e34 /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ PSU_ReadWrite(); 800abba: f000 faf3 bl 800b1a4 PSU_Task(); 800abbe: f000 fbb7 bl 800b330 ED_Delay(10); 800abc2: 200a movs r0, #10 800abc4: f7ff feec bl 800a9a0 METER_CalculateEnergy(); 800abc8: f000 f88a bl 800ace0 CONN_Loop(); 800abcc: f7ff f948 bl 8009e60 LED_Write(); 800abd0: f000 fd9e bl 800b710 ED_Delay(10); 800abd4: 200a movs r0, #10 800abd6: f7ff fee3 bl 800a9a0 PSU_ReadWrite(); 800abda: bf00 nop 800abdc: e7ed b.n 800abba 800abde: bf00 nop 800abe0: 08017520 .word 0x08017520 800abe4: 200011c4 .word 0x200011c4 800abe8: 08017534 .word 0x08017534 800abec: 08017548 .word 0x08017548 800abf0: 0801755c .word 0x0801755c 0800abf4 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800abf4: b580 push {r7, lr} 800abf6: b09c sub sp, #112 @ 0x70 800abf8: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800abfa: f107 0338 add.w r3, r7, #56 @ 0x38 800abfe: 2238 movs r2, #56 @ 0x38 800ac00: 2100 movs r1, #0 800ac02: 4618 mov r0, r3 800ac04: f00a fa7a bl 80150fc RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800ac08: f107 0324 add.w r3, r7, #36 @ 0x24 800ac0c: 2200 movs r2, #0 800ac0e: 601a str r2, [r3, #0] 800ac10: 605a str r2, [r3, #4] 800ac12: 609a str r2, [r3, #8] 800ac14: 60da str r2, [r3, #12] 800ac16: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 800ac18: 1d3b adds r3, r7, #4 800ac1a: 2220 movs r2, #32 800ac1c: 2100 movs r1, #0 800ac1e: 4618 mov r0, r3 800ac20: f00a fa6c bl 80150fc /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; 800ac24: 2305 movs r3, #5 800ac26: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800ac28: f44f 3380 mov.w r3, #65536 @ 0x10000 800ac2c: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV5; 800ac2e: 2304 movs r3, #4 800ac30: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 800ac32: 2301 movs r3, #1 800ac34: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800ac36: 2301 movs r3, #1 800ac38: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.Prediv1Source = RCC_PREDIV1_SOURCE_PLL2; 800ac3a: f44f 3380 mov.w r3, #65536 @ 0x10000 800ac3e: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800ac40: 2302 movs r3, #2 800ac42: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800ac44: f44f 3380 mov.w r3, #65536 @ 0x10000 800ac48: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 800ac4a: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000 800ac4e: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL2.PLL2State = RCC_PLL2_ON; 800ac50: 2302 movs r3, #2 800ac52: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL2.PLL2MUL = RCC_PLL2_MUL8; 800ac54: f44f 63c0 mov.w r3, #1536 @ 0x600 800ac58: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL2.HSEPrediv2Value = RCC_HSE_PREDIV2_DIV5; 800ac5a: 2340 movs r3, #64 @ 0x40 800ac5c: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800ac5e: f107 0338 add.w r3, r7, #56 @ 0x38 800ac62: 4618 mov r0, r3 800ac64: f006 fa1c bl 80110a0 800ac68: 4603 mov r3, r0 800ac6a: 2b00 cmp r3, #0 800ac6c: d001 beq.n 800ac72 { Error_Handler(); 800ac6e: f000 f831 bl 800acd4 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800ac72: 230f movs r3, #15 800ac74: 627b str r3, [r7, #36] @ 0x24 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800ac76: 2302 movs r3, #2 800ac78: 62bb str r3, [r7, #40] @ 0x28 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800ac7a: 2300 movs r3, #0 800ac7c: 62fb str r3, [r7, #44] @ 0x2c RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 800ac7e: f44f 6380 mov.w r3, #1024 @ 0x400 800ac82: 633b str r3, [r7, #48] @ 0x30 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 800ac84: 2300 movs r3, #0 800ac86: 637b str r3, [r7, #52] @ 0x34 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800ac88: f107 0324 add.w r3, r7, #36 @ 0x24 800ac8c: 2102 movs r1, #2 800ac8e: 4618 mov r0, r3 800ac90: f006 fd1c bl 80116cc 800ac94: 4603 mov r3, r0 800ac96: 2b00 cmp r3, #0 800ac98: d001 beq.n 800ac9e { Error_Handler(); 800ac9a: f000 f81b bl 800acd4 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; 800ac9e: 2303 movs r3, #3 800aca0: 607b str r3, [r7, #4] PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 800aca2: f44f 7380 mov.w r3, #256 @ 0x100 800aca6: 60bb str r3, [r7, #8] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 800aca8: f44f 4300 mov.w r3, #32768 @ 0x8000 800acac: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 800acae: 1d3b adds r3, r7, #4 800acb0: 4618 mov r0, r3 800acb2: f006 ff01 bl 8011ab8 800acb6: 4603 mov r3, r0 800acb8: 2b00 cmp r3, #0 800acba: d001 beq.n 800acc0 { Error_Handler(); 800acbc: f000 f80a bl 800acd4 } /** Configure the Systick interrupt time */ __HAL_RCC_PLLI2S_ENABLE(); 800acc0: 4b03 ldr r3, [pc, #12] @ (800acd0 ) 800acc2: 2201 movs r2, #1 800acc4: 601a str r2, [r3, #0] } 800acc6: bf00 nop 800acc8: 3770 adds r7, #112 @ 0x70 800acca: 46bd mov sp, r7 800accc: bd80 pop {r7, pc} 800acce: bf00 nop 800acd0: 42420070 .word 0x42420070 0800acd4 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800acd4: b480 push {r7} 800acd6: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800acd8: b672 cpsid i } 800acda: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 800acdc: bf00 nop 800acde: e7fd b.n 800acdc 0800ace0 : METER_t METER; // Функция для расчета и накопления энергии c дробной частью без счетчиков void METER_CalculateEnergy() { 800ace0: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} 800ace4: b084 sub sp, #16 800ace6: af00 add r7, sp, #0 // Проверяем, что индекс находится в пределах массива METER.online = 0; 800ace8: 4b2c ldr r3, [pc, #176] @ (800ad9c ) 800acea: 2200 movs r2, #0 800acec: 701a strb r2, [r3, #0] if(CONN.connState == Charging){ 800acee: 4b2c ldr r3, [pc, #176] @ (800ada0 ) 800acf0: 785b ldrb r3, [r3, #1] 800acf2: 2b08 cmp r3, #8 800acf4: d103 bne.n 800acfe METER.enable = 1; 800acf6: 4b29 ldr r3, [pc, #164] @ (800ad9c ) 800acf8: 2201 movs r2, #1 800acfa: 761a strb r2, [r3, #24] 800acfc: e002 b.n 800ad04 }else{ METER.enable = 0; 800acfe: 4b27 ldr r3, [pc, #156] @ (800ad9c ) 800ad00: 2200 movs r2, #0 800ad02: 761a strb r2, [r3, #24] } uint32_t currentTick = HAL_GetTick(); // Получаем текущее время в миллисекундах 800ad04: f003 fd40 bl 800e788 800ad08: 60f8 str r0, [r7, #12] uint32_t elapsedTimeMs = currentTick - METER.lastTick; // Вычисляем время, прошедшее с последнего вызова в секундах 800ad0a: 4b24 ldr r3, [pc, #144] @ (800ad9c ) 800ad0c: 685b ldr r3, [r3, #4] 800ad0e: 68fa ldr r2, [r7, #12] 800ad10: 1ad3 subs r3, r2, r3 800ad12: 60bb str r3, [r7, #8] METER.lastTick = currentTick; // Обновляем время последнего вызова для текущего коннектора 800ad14: 4a21 ldr r2, [pc, #132] @ (800ad9c ) 800ad16: 68fb ldr r3, [r7, #12] 800ad18: 6053 str r3, [r2, #4] uint32_t energyWs = CONN.Power * elapsedTimeMs / 1000; // Рассчитываем энергию в ватт-секундах за прошедший промежуток времени 800ad1a: 4b21 ldr r3, [pc, #132] @ (800ada0 ) 800ad1c: f8d3 3003 ldr.w r3, [r3, #3] 800ad20: 68ba ldr r2, [r7, #8] 800ad22: fb02 f303 mul.w r3, r2, r3 800ad26: 4a1f ldr r2, [pc, #124] @ (800ada4 ) 800ad28: fba2 2303 umull r2, r3, r2, r3 800ad2c: 099b lsrs r3, r3, #6 800ad2e: 607b str r3, [r7, #4] //Расчет энергии теперь идет всегда, смещение берем суммарное METER.EnergyPSU_Ws += energyWs; 800ad30: 4b1a ldr r3, [pc, #104] @ (800ad9c ) 800ad32: e9d3 2302 ldrd r2, r3, [r3, #8] 800ad36: 6879 ldr r1, [r7, #4] 800ad38: 2000 movs r0, #0 800ad3a: 460c mov r4, r1 800ad3c: 4605 mov r5, r0 800ad3e: eb12 0804 adds.w r8, r2, r4 800ad42: eb43 0905 adc.w r9, r3, r5 800ad46: 4b15 ldr r3, [pc, #84] @ (800ad9c ) 800ad48: e9c3 8902 strd r8, r9, [r3, #8] // Абсолютное значение энергии разъема складывается из накопленной дробной части и значения со счетчиков METER.AbsoluteEnergy = (uint32_t)METER.EnergyPSU_Ws/3600; //переводим в Вт*час 800ad4c: 4b13 ldr r3, [pc, #76] @ (800ad9c ) 800ad4e: e9d3 2302 ldrd r2, r3, [r3, #8] 800ad52: 4b15 ldr r3, [pc, #84] @ (800ada8 ) 800ad54: fba3 2302 umull r2, r3, r3, r2 800ad58: 0adb lsrs r3, r3, #11 800ad5a: 4a10 ldr r2, [pc, #64] @ (800ad9c ) 800ad5c: 6113 str r3, [r2, #16] if(METER.enable) { 800ad5e: 4b0f ldr r3, [pc, #60] @ (800ad9c ) 800ad60: 7e1b ldrb r3, [r3, #24] 800ad62: 2b00 cmp r3, #0 800ad64: d008 beq.n 800ad78 //enabled state CONN.Energy = METER.AbsoluteEnergy - METER.EnergyOffset;//переводим в Вт*час 800ad66: 4b0d ldr r3, [pc, #52] @ (800ad9c ) 800ad68: 691a ldr r2, [r3, #16] 800ad6a: 4b0c ldr r3, [pc, #48] @ (800ad9c ) 800ad6c: 695b ldr r3, [r3, #20] 800ad6e: 1ad3 subs r3, r2, r3 800ad70: 4a0b ldr r2, [pc, #44] @ (800ada0 ) 800ad72: f8c2 3007 str.w r3, [r2, #7] METER.EnergyOffset = METER.AbsoluteEnergy; } } 800ad76: e00c b.n 800ad92 CONN.Energy = 0; 800ad78: 4b09 ldr r3, [pc, #36] @ (800ada0 ) 800ad7a: 2200 movs r2, #0 800ad7c: 71da strb r2, [r3, #7] 800ad7e: 2200 movs r2, #0 800ad80: 721a strb r2, [r3, #8] 800ad82: 2200 movs r2, #0 800ad84: 725a strb r2, [r3, #9] 800ad86: 2200 movs r2, #0 800ad88: 729a strb r2, [r3, #10] METER.EnergyOffset = METER.AbsoluteEnergy; 800ad8a: 4b04 ldr r3, [pc, #16] @ (800ad9c ) 800ad8c: 691b ldr r3, [r3, #16] 800ad8e: 4a03 ldr r2, [pc, #12] @ (800ad9c ) 800ad90: 6153 str r3, [r2, #20] } 800ad92: bf00 nop 800ad94: 3710 adds r7, #16 800ad96: 46bd mov sp, r7 800ad98: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} 800ad9c: 200008a0 .word 0x200008a0 800ada0: 200003b0 .word 0x200003b0 800ada4: 10624dd3 .word 0x10624dd3 800ada8: 91a2b3c5 .word 0x91a2b3c5 0800adac : extern CAN_HandleTypeDef hcan2; static void PSU_SendCmd(uint8_t source, uint8_t destination, uint8_t cmd, void *data); static void PSU_SwitchState(PSU_State_t state){ 800adac: b580 push {r7, lr} 800adae: b082 sub sp, #8 800adb0: af00 add r7, sp, #0 800adb2: 4603 mov r3, r0 800adb4: 71fb strb r3, [r7, #7] PSU0.state = state; 800adb6: 4a06 ldr r2, [pc, #24] @ (800add0 ) 800adb8: 79fb ldrb r3, [r7, #7] 800adba: 71d3 strb r3, [r2, #7] PSU0.statetick = HAL_GetTick(); 800adbc: f003 fce4 bl 800e788 800adc0: 4603 mov r3, r0 800adc2: 4a03 ldr r2, [pc, #12] @ (800add0 ) 800adc4: 6113 str r3, [r2, #16] } 800adc6: bf00 nop 800adc8: 3708 adds r7, #8 800adca: 46bd mov sp, r7 800adcc: bd80 pop {r7, pc} 800adce: bf00 nop 800add0: 20000904 .word 0x20000904 0800add4 : static uint32_t PSU_StateTime(void){ 800add4: b580 push {r7, lr} 800add6: af00 add r7, sp, #0 return HAL_GetTick() - PSU0.statetick; 800add8: f003 fcd6 bl 800e788 800addc: 4602 mov r2, r0 800adde: 4b02 ldr r3, [pc, #8] @ (800ade8 ) 800ade0: 691b ldr r3, [r3, #16] 800ade2: 1ad3 subs r3, r2, r3 } 800ade4: 4618 mov r0, r3 800ade6: bd80 pop {r7, pc} 800ade8: 20000904 .word 0x20000904 0800adec : ISR_FAST void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan){ 800adec: b538 push {r3, r4, r5, lr} static CAN_RxHeaderTypeDef RxHeader; static uint8_t RxData[8] = {0,}; CanId_t CanId; if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO1, &RxHeader, RxData) == HAL_OK) 800adee: 4c42 ldr r4, [pc, #264] @ (800aef8 ) 800adf0: 4d42 ldr r5, [pc, #264] @ (800aefc ) 800adf2: 4623 mov r3, r4 800adf4: 462a mov r2, r5 800adf6: 2101 movs r1, #1 800adf8: f004 fda0 bl 800f93c 800adfc: b910 cbnz r0, 800ae04 { memcpy(&CanId, &RxHeader.ExtId, sizeof(CanId_t)); 800adfe: 686d ldr r5, [r5, #4] /* Для DC30 поддерживается только один силовой модуль (source == 0) */ if(CanId.source != 0) return; 800ae00: b2eb uxtb r3, r5 800ae02: b103 cbz r3, 800ae06 CONN.outputEnabled = PSU0.PSU_enabled; } } } } } 800ae04: bd38 pop {r3, r4, r5, pc} can_lastpacket = HAL_GetTick(); 800ae06: f003 fcbf bl 800e788 if(CanId.command==0x02){ 800ae0a: f3c5 4505 ubfx r5, r5, #16, #6 can_lastpacket = HAL_GetTick(); 800ae0e: 4b3c ldr r3, [pc, #240] @ (800af00 ) if(CanId.command==0x02){ 800ae10: 2d02 cmp r5, #2 can_lastpacket = HAL_GetTick(); 800ae12: 6018 str r0, [r3, #0] if(CanId.command==0x02){ 800ae14: d013 beq.n 800ae3e if(CanId.command==0x04){ 800ae16: 2d04 cmp r5, #4 800ae18: d117 bne.n 800ae4a memcpy(&PSU_04, RxData, 8); 800ae1a: e894 0003 ldmia.w r4, {r0, r1} 800ae1e: 4b39 ldr r3, [pc, #228] @ (800af04 ) PSU0.tempAmbient = PSU_04.moduleTemperature; 800ae20: 4a39 ldr r2, [pc, #228] @ (800af08 ) memcpy(&PSU_04, RxData, 8); 800ae22: e883 0003 stmia.w r3, {r0, r1} PSU0.status0.raw = PSU_04.modularForm0; 800ae26: 7a18 ldrb r0, [r3, #8] PSU0.tempAmbient = PSU_04.moduleTemperature; 800ae28: 791c ldrb r4, [r3, #4] PSU0.status1.raw = PSU_04.modularForm1; 800ae2a: 79d9 ldrb r1, [r3, #7] PSU0.status2.raw = PSU_04.modularForm2; 800ae2c: 799b ldrb r3, [r3, #6] PSU0.tempAmbient = PSU_04.moduleTemperature; 800ae2e: 6214 str r4, [r2, #32] PSU0.status0.raw = PSU_04.modularForm0; 800ae30: f882 0024 strb.w r0, [r2, #36] @ 0x24 PSU0.status1.raw = PSU_04.modularForm1; 800ae34: f882 1025 strb.w r1, [r2, #37] @ 0x25 PSU0.status2.raw = PSU_04.modularForm2; 800ae38: f882 3026 strb.w r3, [r2, #38] @ 0x26 } 800ae3c: bd38 pop {r3, r4, r5, pc} memcpy(&PSU_02, RxData, 8); 800ae3e: 4b33 ldr r3, [pc, #204] @ (800af0c ) 800ae40: e894 0003 ldmia.w r4, {r0, r1} 800ae44: e883 0003 stmia.w r3, {r0, r1} } 800ae48: bd38 pop {r3, r4, r5, pc} if(CanId.command==0x06){ 800ae4a: 2d06 cmp r5, #6 800ae4c: d111 bne.n 800ae72 memcpy(&PSU_06, RxData, 8); 800ae4e: e894 0003 ldmia.w r4, {r0, r1} 800ae52: 4b2f ldr r3, [pc, #188] @ (800af10 ) 800ae54: e883 0003 stmia.w r3, {r0, r1} PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800ae58: 8818 ldrh r0, [r3, #0] PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ae5a: 8859 ldrh r1, [r3, #2] PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ae5c: 889a ldrh r2, [r3, #4] PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800ae5e: ba40 rev16 r0, r0 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ae60: ba49 rev16 r1, r1 PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ae62: ba52 rev16 r2, r2 PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800ae64: b280 uxth r0, r0 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ae66: b289 uxth r1, r1 PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ae68: b292 uxth r2, r2 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ae6a: e9c3 0102 strd r0, r1, [r3, #8] PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ae6e: 611a str r2, [r3, #16] } 800ae70: bd38 pop {r3, r4, r5, pc} if(CanId.command==0x08){ 800ae72: 2d08 cmp r5, #8 800ae74: d03a beq.n 800aeec if(CanId.command==0x09){ 800ae76: 2d09 cmp r5, #9 800ae78: d1c4 bne.n 800ae04 memcpy(&PSU_09, RxData, 8); 800ae7a: e894 0003 ldmia.w r4, {r0, r1} PSU0.temperature = PSU_04.moduleTemperature; 800ae7e: 4b21 ldr r3, [pc, #132] @ (800af04 ) memcpy(&PSU_09, RxData, 8); 800ae80: 4d24 ldr r5, [pc, #144] @ (800af14 ) PSU0.outputVoltage = v; 800ae82: 4c21 ldr r4, [pc, #132] @ (800af08 ) PSU0.temperature = PSU_04.moduleTemperature; 800ae84: f893 c004 ldrb.w ip, [r3, #4] uint16_t v = PSU_09.moduleNVoltage / 1000; 800ae88: 4a23 ldr r2, [pc, #140] @ (800af18 ) memcpy(&PSU_09, RxData, 8); 800ae8a: e885 0003 stmia.w r5, {r0, r1} PSU_09.moduleNCurrent = PSU_09.moduleNCurrent_[3]; 800ae8e: ba00 rev r0, r0 PSU0.temperature = PSU_04.moduleTemperature; 800ae90: f884 c006 strb.w ip, [r4, #6] uint16_t v = PSU_09.moduleNVoltage / 1000; 800ae94: fba2 c200 umull ip, r2, r2, r0 800ae98: ba09 rev r1, r1 PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[0]<<24; 800ae9a: e9c5 0102 strd r0, r1, [r5, #8] uint16_t v = PSU_09.moduleNVoltage / 1000; 800ae9e: f3c2 108f ubfx r0, r2, #6, #16 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800aea2: 2813 cmp r0, #19 PSU0.online = 1; 800aea4: f04f 0e01 mov.w lr, #1 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800aea8: bf94 ite ls 800aeaa: 2500 movls r5, #0 800aeac: 2501 movhi r5, #1 int16_t i = PSU_09.moduleNCurrent / 100; 800aeae: 4b1b ldr r3, [pc, #108] @ (800af1c ) PSU0.online = 1; 800aeb0: f884 e008 strb.w lr, [r4, #8] int16_t i = PSU_09.moduleNCurrent / 100; 800aeb4: fba3 c301 umull ip, r3, r3, r1 if(PSU0.state >= PSU_READY){ 800aeb8: 79e1 ldrb r1, [r4, #7] int16_t i = PSU_09.moduleNCurrent / 100; 800aeba: 095b lsrs r3, r3, #5 if(PSU0.state >= PSU_READY){ 800aebc: 4571 cmp r1, lr PSU0.outputVoltage = v; 800aebe: 8060 strh r0, [r4, #2] int16_t i = PSU_09.moduleNCurrent / 100; 800aec0: 80a3 strh r3, [r4, #4] uint16_t v = PSU_09.moduleNVoltage / 1000; 800aec2: ea4f 1292 mov.w r2, r2, lsr #6 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800aec6: 72a5 strb r5, [r4, #10] if(PSU0.state >= PSU_READY){ 800aec8: d99c bls.n 800ae04 CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800aeca: b299 uxth r1, r3 800aecc: b292 uxth r2, r2 800aece: fb01 f202 mul.w r2, r1, r2 800aed2: 4c13 ldr r4, [pc, #76] @ (800af20 ) CONN.MeasuredVoltage = PSU0.outputVoltage; 800aed4: 4913 ldr r1, [pc, #76] @ (800af24 ) CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800aed6: fba4 4202 umull r4, r2, r4, r2 CONN.MeasuredCurrent = PSU0.outputCurrent; 800aeda: f8a1 3015 strh.w r3, [r1, #21] CONN.outputEnabled = PSU0.PSU_enabled; 800aede: 760d strb r5, [r1, #24] CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800aee0: 08d3 lsrs r3, r2, #3 CONN.MeasuredVoltage = PSU0.outputVoltage; 800aee2: f8a1 0013 strh.w r0, [r1, #19] CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800aee6: f8c1 3003 str.w r3, [r1, #3] } 800aeea: bd38 pop {r3, r4, r5, pc} memcpy(&PSU_08, RxData, 8); 800aeec: 4b0e ldr r3, [pc, #56] @ (800af28 ) 800aeee: e894 0003 ldmia.w r4, {r0, r1} 800aef2: e883 0003 stmia.w r3, {r0, r1} } 800aef6: bd38 pop {r3, r4, r5, pc} 800aef8: 2000094c .word 0x2000094c 800aefc: 20000930 .word 0x20000930 800af00: 2000092c .word 0x2000092c 800af04: 200008cc .word 0x200008cc 800af08: 20000904 .word 0x20000904 800af0c: 200008c0 .word 0x200008c0 800af10: 200008d8 .word 0x200008d8 800af14: 200008f4 .word 0x200008f4 800af18: 10624dd3 .word 0x10624dd3 800af1c: 51eb851f .word 0x51eb851f 800af20: cccccccd .word 0xcccccccd 800af24: 200003b0 .word 0x200003b0 800af28: 200008ec .word 0x200008ec 0800af2c : void PSU_CAN_FilterInit(){ 800af2c: b580 push {r7, lr} 800af2e: b08a sub sp, #40 @ 0x28 800af30: af00 add r7, sp, #0 CAN_FilterTypeDef sFilterConfig; sFilterConfig.FilterBank = 14; 800af32: 230e movs r3, #14 800af34: 617b str r3, [r7, #20] sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; 800af36: 2300 movs r3, #0 800af38: 61bb str r3, [r7, #24] sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; 800af3a: 2301 movs r3, #1 800af3c: 61fb str r3, [r7, #28] sFilterConfig.FilterIdHigh = 0x0000; 800af3e: 2300 movs r3, #0 800af40: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = 0x0000; 800af42: 2300 movs r3, #0 800af44: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 800af46: 2300 movs r3, #0 800af48: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = 0x0000; 800af4a: 2300 movs r3, #0 800af4c: 60fb str r3, [r7, #12] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; 800af4e: 2300 movs r3, #0 800af50: 613b str r3, [r7, #16] sFilterConfig.FilterActivation = ENABLE; 800af52: 2301 movs r3, #1 800af54: 623b str r3, [r7, #32] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 800af56: 2301 movs r3, #1 800af58: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 800af5a: 230e movs r3, #14 800af5c: 627b str r3, [r7, #36] @ 0x24 if(HAL_CAN_ConfigFilter(&hcan2, &sFilterConfig) != HAL_OK) 800af5e: 463b mov r3, r7 800af60: 4619 mov r1, r3 800af62: 4806 ldr r0, [pc, #24] @ (800af7c ) 800af64: f004 fa7a bl 800f45c 800af68: 4603 mov r3, r0 800af6a: 2b00 cmp r3, #0 800af6c: d001 beq.n 800af72 { Error_Handler(); 800af6e: f7ff feb1 bl 800acd4 } } 800af72: bf00 nop 800af74: 3728 adds r7, #40 @ 0x28 800af76: 46bd mov sp, r7 800af78: bd80 pop {r7, pc} 800af7a: bf00 nop 800af7c: 20000384 .word 0x20000384 0800af80 : void PSU_Init(){ 800af80: b580 push {r7, lr} 800af82: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan2); 800af84: 4815 ldr r0, [pc, #84] @ (800afdc ) 800af86: f004 fb8d bl 800f6a4 MX_CAN2_Init(); 800af8a: f7fe fe3f bl 8009c0c PSU_CAN_FilterInit(); 800af8e: f7ff ffcd bl 800af2c HAL_CAN_Start(&hcan2); 800af92: 4812 ldr r0, [pc, #72] @ (800afdc ) 800af94: f004 fb42 bl 800f61c HAL_CAN_ActivateNotification(&hcan2, CAN_IT_RX_FIFO1_MSG_PENDING /* | CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | CAN_IT_TX_MAILBOX_EMPTY*/); 800af98: 2110 movs r1, #16 800af9a: 4810 ldr r0, [pc, #64] @ (800afdc ) 800af9c: f004 fdef bl 800fb7e memset(&PSU0, 0, sizeof(PSU0)); 800afa0: 2228 movs r2, #40 @ 0x28 800afa2: 2100 movs r1, #0 800afa4: 480e ldr r0, [pc, #56] @ (800afe0 ) 800afa6: f00a f8a9 bl 80150fc PSU0.state = PSU_UNREADY; 800afaa: 4b0d ldr r3, [pc, #52] @ (800afe0 ) 800afac: 2200 movs r2, #0 800afae: 71da strb r2, [r3, #7] PSU0.statetick = HAL_GetTick(); 800afb0: f003 fbea bl 800e788 800afb4: 4603 mov r3, r0 800afb6: 4a0a ldr r2, [pc, #40] @ (800afe0 ) 800afb8: 6113 str r3, [r2, #16] PSU0.power_limit = PSU_MAX_POWER; // kW 800afba: 4b09 ldr r3, [pc, #36] @ (800afe0 ) 800afbc: f649 4240 movw r2, #40000 @ 0x9c40 800afc0: 615a str r2, [r3, #20] PSU0.hv_mode = 0; 800afc2: 4b07 ldr r3, [pc, #28] @ (800afe0 ) 800afc4: 2200 movs r2, #0 800afc6: 761a strb r2, [r3, #24] PSU0.hv_tick = 0; 800afc8: 4b05 ldr r3, [pc, #20] @ (800afe0 ) 800afca: 2200 movs r2, #0 800afcc: 61da str r2, [r3, #28] PSU_Enable(0, 0); 800afce: 2100 movs r1, #0 800afd0: 2000 movs r0, #0 800afd2: f000 f807 bl 800afe4 } 800afd6: bf00 nop 800afd8: bd80 pop {r7, pc} 800afda: bf00 nop 800afdc: 20000384 .word 0x20000384 800afe0: 20000904 .word 0x20000904 0800afe4 : void PSU_Enable(uint8_t addr, uint8_t enable){ 800afe4: b580 push {r7, lr} 800afe6: b084 sub sp, #16 800afe8: af00 add r7, sp, #0 800afea: 4603 mov r3, r0 800afec: 460a mov r2, r1 800afee: 71fb strb r3, [r7, #7] 800aff0: 4613 mov r3, r2 800aff2: 71bb strb r3, [r7, #6] PSU_1A_t data; memset(&data, 0, sizeof(data)); 800aff4: f107 0308 add.w r3, r7, #8 800aff8: 2208 movs r2, #8 800affa: 2100 movs r1, #0 800affc: 4618 mov r0, r3 800affe: f00a f87d bl 80150fc /* Для DC30 поддерживается только один модуль с адресом 0 */ if(addr != 0) return; 800b002: 79fb ldrb r3, [r7, #7] 800b004: 2b00 cmp r3, #0 800b006: d115 bne.n 800b034 if(PSU0.online == 0) return; 800b008: 4b0d ldr r3, [pc, #52] @ (800b040 ) 800b00a: 7a1b ldrb r3, [r3, #8] 800b00c: 2b00 cmp r3, #0 800b00e: d013 beq.n 800b038 data.enable = !enable; 800b010: 79bb ldrb r3, [r7, #6] 800b012: 2b00 cmp r3, #0 800b014: bf0c ite eq 800b016: 2301 moveq r3, #1 800b018: 2300 movne r3, #0 800b01a: b2db uxtb r3, r3 800b01c: 723b strb r3, [r7, #8] PSU_SendCmd(0xF0, addr, 0x1A, &data); 800b01e: f107 0308 add.w r3, r7, #8 800b022: 79f9 ldrb r1, [r7, #7] 800b024: 221a movs r2, #26 800b026: 20f0 movs r0, #240 @ 0xf0 800b028: f000 f866 bl 800b0f8 ED_Delay(CAN_DELAY); 800b02c: 2014 movs r0, #20 800b02e: f7ff fcb7 bl 800a9a0 800b032: e002 b.n 800b03a if(addr != 0) return; 800b034: bf00 nop 800b036: e000 b.n 800b03a if(PSU0.online == 0) return; 800b038: bf00 nop } 800b03a: 3710 adds r7, #16 800b03c: 46bd mov sp, r7 800b03e: bd80 pop {r7, pc} 800b040: 20000904 .word 0x20000904 0800b044 : memset(&data, 0, sizeof(data)); data.enable = !enable; if(addr != 0) return; PSU_SendCmd(0xF0, addr, 0x1D, &data); } void PSU_SetVoltageCurrent(uint8_t addr, uint16_t voltage, uint16_t current){ 800b044: b580 push {r7, lr} 800b046: b086 sub sp, #24 800b048: af00 add r7, sp, #0 800b04a: 4603 mov r3, r0 800b04c: 71fb strb r3, [r7, #7] 800b04e: 460b mov r3, r1 800b050: 80bb strh r3, [r7, #4] 800b052: 4613 mov r3, r2 800b054: 807b strh r3, [r7, #2] PSU_1C_t data; memset(&data, 0, sizeof(data)); 800b056: f107 0308 add.w r3, r7, #8 800b05a: 2208 movs r2, #8 800b05c: 2100 movs r1, #0 800b05e: 4618 mov r0, r3 800b060: f00a f84c bl 80150fc if(addr != 0) return; 800b064: 79fb ldrb r3, [r7, #7] 800b066: 2b00 cmp r3, #0 800b068: d140 bne.n 800b0ec if(voltage 800b070: 2396 movs r3, #150 @ 0x96 800b072: 80bb strh r3, [r7, #4] if((PSU0.hv_mode==0) && voltage>499) voltage = 499; 800b074: 4b1f ldr r3, [pc, #124] @ (800b0f4 ) 800b076: 7e1b ldrb r3, [r3, #24] 800b078: 2b00 cmp r3, #0 800b07a: d106 bne.n 800b08a 800b07c: 88bb ldrh r3, [r7, #4] 800b07e: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b082: d302 bcc.n 800b08a 800b084: f240 13f3 movw r3, #499 @ 0x1f3 800b088: 80bb strh r3, [r7, #4] uint32_t current_ma = current * 100; 800b08a: 887b ldrh r3, [r7, #2] 800b08c: 2264 movs r2, #100 @ 0x64 800b08e: fb02 f303 mul.w r3, r2, r3 800b092: 617b str r3, [r7, #20] uint32_t voltage_mv = voltage * 1000; 800b094: 88bb ldrh r3, [r7, #4] 800b096: f44f 727a mov.w r2, #1000 @ 0x3e8 800b09a: fb02 f303 mul.w r3, r2, r3 800b09e: 613b str r3, [r7, #16] data.moduleCurrentTotal[0] = (current_ma >> 24) & 0xFF; 800b0a0: 697b ldr r3, [r7, #20] 800b0a2: 0e1b lsrs r3, r3, #24 800b0a4: b2db uxtb r3, r3 800b0a6: 733b strb r3, [r7, #12] data.moduleCurrentTotal[1] = (current_ma >> 16) & 0xFF; 800b0a8: 697b ldr r3, [r7, #20] 800b0aa: 0c1b lsrs r3, r3, #16 800b0ac: b2db uxtb r3, r3 800b0ae: 737b strb r3, [r7, #13] data.moduleCurrentTotal[2] = (current_ma >> 8) & 0xFF; 800b0b0: 697b ldr r3, [r7, #20] 800b0b2: 0a1b lsrs r3, r3, #8 800b0b4: b2db uxtb r3, r3 800b0b6: 73bb strb r3, [r7, #14] data.moduleCurrentTotal[3] = (current_ma >> 0) & 0xFF; 800b0b8: 697b ldr r3, [r7, #20] 800b0ba: b2db uxtb r3, r3 800b0bc: 73fb strb r3, [r7, #15] data.moduleVoltage[0] = (voltage_mv >> 24) & 0xFF; 800b0be: 693b ldr r3, [r7, #16] 800b0c0: 0e1b lsrs r3, r3, #24 800b0c2: b2db uxtb r3, r3 800b0c4: 723b strb r3, [r7, #8] data.moduleVoltage[1] = (voltage_mv >> 16) & 0xFF; 800b0c6: 693b ldr r3, [r7, #16] 800b0c8: 0c1b lsrs r3, r3, #16 800b0ca: b2db uxtb r3, r3 800b0cc: 727b strb r3, [r7, #9] data.moduleVoltage[2] = (voltage_mv >> 8) & 0xFF; 800b0ce: 693b ldr r3, [r7, #16] 800b0d0: 0a1b lsrs r3, r3, #8 800b0d2: b2db uxtb r3, r3 800b0d4: 72bb strb r3, [r7, #10] data.moduleVoltage[3] = (voltage_mv >> 0) & 0xFF; 800b0d6: 693b ldr r3, [r7, #16] 800b0d8: b2db uxtb r3, r3 800b0da: 72fb strb r3, [r7, #11] PSU_SendCmd(0xF0, addr, 0x1C, &data); 800b0dc: f107 0308 add.w r3, r7, #8 800b0e0: 79f9 ldrb r1, [r7, #7] 800b0e2: 221c movs r2, #28 800b0e4: 20f0 movs r0, #240 @ 0xf0 800b0e6: f000 f807 bl 800b0f8 800b0ea: e000 b.n 800b0ee if(addr != 0) return; 800b0ec: bf00 nop } 800b0ee: 3718 adds r7, #24 800b0f0: 46bd mov sp, r7 800b0f2: bd80 pop {r7, pc} 800b0f4: 20000904 .word 0x20000904 0800b0f8 : void PSU_SendCmd(uint8_t source, uint8_t destination, uint8_t cmd, void *data){ 800b0f8: b580 push {r7, lr} 800b0fa: b08c sub sp, #48 @ 0x30 800b0fc: af00 add r7, sp, #0 800b0fe: 603b str r3, [r7, #0] 800b100: 4603 mov r3, r0 800b102: 71fb strb r3, [r7, #7] 800b104: 460b mov r3, r1 800b106: 71bb strb r3, [r7, #6] 800b108: 4613 mov r3, r2 800b10a: 717b strb r3, [r7, #5] CanId_t CanId; CanId.source = source; 800b10c: 79fb ldrb r3, [r7, #7] 800b10e: f887 3028 strb.w r3, [r7, #40] @ 0x28 CanId.destination = destination; 800b112: 79bb ldrb r3, [r7, #6] 800b114: f887 3029 strb.w r3, [r7, #41] @ 0x29 CanId.command = cmd; 800b118: 797b ldrb r3, [r7, #5] 800b11a: f003 033f and.w r3, r3, #63 @ 0x3f 800b11e: b2da uxtb r2, r3 800b120: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 800b124: f362 0305 bfi r3, r2, #0, #6 800b128: f887 302a strb.w r3, [r7, #42] @ 0x2a CanId.device = 0x0A; 800b12c: 8d7b ldrh r3, [r7, #42] @ 0x2a 800b12e: 220a movs r2, #10 800b130: f362 1389 bfi r3, r2, #6, #4 800b134: 857b strh r3, [r7, #42] @ 0x2a int8_t retry_counter = 10; 800b136: 230a movs r3, #10 800b138: f887 302f strb.w r3, [r7, #47] @ 0x2f CAN_TxHeaderTypeDef tx_header; uint32_t tx_mailbox; HAL_StatusTypeDef CAN_result; memcpy(&tx_header.ExtId, &CanId, sizeof(CanId_t)); 800b13c: 6abb ldr r3, [r7, #40] @ 0x28 800b13e: 617b str r3, [r7, #20] tx_header.RTR = CAN_RTR_DATA; 800b140: 2300 movs r3, #0 800b142: 61fb str r3, [r7, #28] tx_header.IDE = CAN_ID_EXT; 800b144: 2304 movs r3, #4 800b146: 61bb str r3, [r7, #24] tx_header.DLC = 8; 800b148: 2308 movs r3, #8 800b14a: 623b str r3, [r7, #32] while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800b14c: e01e b.n 800b18c if (HAL_CAN_GetTxMailboxesFreeLevel(&hcan2) > 0){ 800b14e: 4814 ldr r0, [pc, #80] @ (800b1a0 ) 800b150: f004 fbc0 bl 800f8d4 800b154: 4603 mov r3, r0 800b156: 2b00 cmp r3, #0 800b158: d00e beq.n 800b178 /* отправка сообщения */ CAN_result = HAL_CAN_AddTxMessage(&hcan2, &tx_header, (uint8_t*)data, &tx_mailbox); 800b15a: f107 030c add.w r3, r7, #12 800b15e: f107 0110 add.w r1, r7, #16 800b162: 683a ldr r2, [r7, #0] 800b164: 480e ldr r0, [pc, #56] @ (800b1a0 ) 800b166: f004 fae6 bl 800f736 800b16a: 4603 mov r3, r0 800b16c: f887 302e strb.w r3, [r7, #46] @ 0x2e /* если отправка удалась, выход */ if(CAN_result == HAL_OK) { 800b170: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 800b174: 2b00 cmp r3, #0 800b176: d00e beq.n 800b196 return; } } ED_Delay(1); 800b178: 2001 movs r0, #1 800b17a: f7ff fc11 bl 800a9a0 retry_counter--; 800b17e: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800b182: b2db uxtb r3, r3 800b184: 3b01 subs r3, #1 800b186: b2db uxtb r3, r3 800b188: f887 302f strb.w r3, [r7, #47] @ 0x2f while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800b18c: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800b190: 2b00 cmp r3, #0 800b192: dcdc bgt.n 800b14e 800b194: e000 b.n 800b198 return; 800b196: bf00 nop } } 800b198: 3730 adds r7, #48 @ 0x30 800b19a: 46bd mov sp, r7 800b19c: bd80 pop {r7, pc} 800b19e: bf00 nop 800b1a0: 20000384 .word 0x20000384 0800b1a4 : void PSU_ReadWrite(){ 800b1a4: b580 push {r7, lr} 800b1a6: b082 sub sp, #8 800b1a8: af00 add r7, sp, #0 uint8_t zero_data[8] = {0,0,0,0,0,0,0,0}; 800b1aa: 463b mov r3, r7 800b1ac: 2200 movs r2, #0 800b1ae: 601a str r2, [r3, #0] 800b1b0: 605a str r2, [r3, #4] PSU_SendCmd(0xF0, 0, 0x04, zero_data);ED_Delay(CAN_DELAY); 800b1b2: 463b mov r3, r7 800b1b4: 2204 movs r2, #4 800b1b6: 2100 movs r1, #0 800b1b8: 20f0 movs r0, #240 @ 0xf0 800b1ba: f7ff ff9d bl 800b0f8 800b1be: 2014 movs r0, #20 800b1c0: f7ff fbee bl 800a9a0 PSU_SendCmd(0xF0, 0, 0x06, zero_data);ED_Delay(CAN_DELAY); 800b1c4: 463b mov r3, r7 800b1c6: 2206 movs r2, #6 800b1c8: 2100 movs r1, #0 800b1ca: 20f0 movs r0, #240 @ 0xf0 800b1cc: f7ff ff94 bl 800b0f8 800b1d0: 2014 movs r0, #20 800b1d2: f7ff fbe5 bl 800a9a0 // PSU_SendCmd(0xF0, 0, 0x08, zero_data);ED_Delay(CAN_DELAY); PSU_SendCmd(0xF0, 0, 0x09, zero_data);ED_Delay(CAN_DELAY); 800b1d6: 463b mov r3, r7 800b1d8: 2209 movs r2, #9 800b1da: 2100 movs r1, #0 800b1dc: 20f0 movs r0, #240 @ 0xf0 800b1de: f7ff ff8b bl 800b0f8 800b1e2: 2014 movs r0, #20 800b1e4: f7ff fbdc bl 800a9a0 // Power Limit if ((CONN.WantedCurrent/10) * CONN.MeasuredVoltage > PSU0.power_limit){ 800b1e8: 4b4d ldr r3, [pc, #308] @ (800b320 ) 800b1ea: f8b3 301b ldrh.w r3, [r3, #27] 800b1ee: b29b uxth r3, r3 800b1f0: 4a4c ldr r2, [pc, #304] @ (800b324 ) 800b1f2: fba2 2303 umull r2, r3, r2, r3 800b1f6: 08db lsrs r3, r3, #3 800b1f8: b29b uxth r3, r3 800b1fa: 461a mov r2, r3 800b1fc: 4b48 ldr r3, [pc, #288] @ (800b320 ) 800b1fe: f8b3 3013 ldrh.w r3, [r3, #19] 800b202: b29b uxth r3, r3 800b204: fb02 f303 mul.w r3, r2, r3 800b208: 461a mov r2, r3 800b20a: 4b47 ldr r3, [pc, #284] @ (800b328 ) 800b20c: 695b ldr r3, [r3, #20] 800b20e: 429a cmp r2, r3 800b210: d911 bls.n 800b236 CONN.RequestedCurrent = PSU0.power_limit * 10 / CONN.MeasuredVoltage; 800b212: 4b45 ldr r3, [pc, #276] @ (800b328 ) 800b214: 695a ldr r2, [r3, #20] 800b216: 4613 mov r3, r2 800b218: 009b lsls r3, r3, #2 800b21a: 4413 add r3, r2 800b21c: 005b lsls r3, r3, #1 800b21e: 461a mov r2, r3 800b220: 4b3f ldr r3, [pc, #252] @ (800b320 ) 800b222: f8b3 3013 ldrh.w r3, [r3, #19] 800b226: b29b uxth r3, r3 800b228: fbb2 f3f3 udiv r3, r2, r3 800b22c: b29a uxth r2, r3 800b22e: 4b3c ldr r3, [pc, #240] @ (800b320 ) 800b230: f8a3 2011 strh.w r2, [r3, #17] 800b234: e006 b.n 800b244 }else{ CONN.RequestedCurrent = CONN.WantedCurrent; 800b236: 4b3a ldr r3, [pc, #232] @ (800b320 ) 800b238: f8b3 301b ldrh.w r3, [r3, #27] 800b23c: b29a uxth r2, r3 800b23e: 4b38 ldr r3, [pc, #224] @ (800b320 ) 800b240: f8a3 2011 strh.w r2, [r3, #17] } if(CONN.RequestedCurrent > (PSU_MAX_CURRENT*10)){ 800b244: 4b36 ldr r3, [pc, #216] @ (800b320 ) 800b246: f8b3 3011 ldrh.w r3, [r3, #17] 800b24a: b29b uxth r3, r3 800b24c: f240 5232 movw r2, #1330 @ 0x532 800b250: 4293 cmp r3, r2 800b252: d908 bls.n 800b266 CONN.RequestedCurrent = PSU_MAX_CURRENT*10; 800b254: 4b32 ldr r3, [pc, #200] @ (800b320 ) 800b256: 2200 movs r2, #0 800b258: f042 0232 orr.w r2, r2, #50 @ 0x32 800b25c: 745a strb r2, [r3, #17] 800b25e: 2200 movs r2, #0 800b260: f042 0205 orr.w r2, r2, #5 800b264: 749a strb r2, [r3, #18] } CONN.RequestedPower = CONN.RequestedCurrent * CONN.RequestedVoltage / 10; 800b266: 4b2e ldr r3, [pc, #184] @ (800b320 ) 800b268: f8b3 3011 ldrh.w r3, [r3, #17] 800b26c: b29b uxth r3, r3 800b26e: 461a mov r2, r3 800b270: 4b2b ldr r3, [pc, #172] @ (800b320 ) 800b272: f8b3 300f ldrh.w r3, [r3, #15] 800b276: b29b uxth r3, r3 800b278: fb02 f303 mul.w r3, r2, r3 800b27c: 4a2b ldr r2, [pc, #172] @ (800b32c ) 800b27e: fb82 1203 smull r1, r2, r2, r3 800b282: 1092 asrs r2, r2, #2 800b284: 17db asrs r3, r3, #31 800b286: 1ad3 subs r3, r2, r3 800b288: 461a mov r2, r3 800b28a: 4b25 ldr r3, [pc, #148] @ (800b320 ) 800b28c: f8c3 200b str.w r2, [r3, #11] if(PSU0.ready){ 800b290: 4b25 ldr r3, [pc, #148] @ (800b328 ) 800b292: 7a5b ldrb r3, [r3, #9] 800b294: 2b00 cmp r3, #0 800b296: d03e beq.n 800b316 if (CONN.RequestedVoltage == FAKE_EVREQ_VOLTAGE_V) { 800b298: 4b21 ldr r3, [pc, #132] @ (800b320 ) 800b29a: f8b3 300f ldrh.w r3, [r3, #15] 800b29e: b29b uxth r3, r3 800b2a0: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b2a4: d106 bne.n 800b2b4 PSU_SetVoltageCurrent(0, (uint16_t)FAKE_PSU_VOLTAGE_V, (uint16_t)FAKE_PSU_CURRENT_0P1A); 800b2a6: 220a movs r2, #10 800b2a8: f44f 7196 mov.w r1, #300 @ 0x12c 800b2ac: 2000 movs r0, #0 800b2ae: f7ff fec9 bl 800b044 800b2b2: e00b b.n 800b2cc }else{ PSU_SetVoltageCurrent(0, CONN.RequestedVoltage, CONN.RequestedCurrent); // Normal mode 800b2b4: 4b1a ldr r3, [pc, #104] @ (800b320 ) 800b2b6: f8b3 300f ldrh.w r3, [r3, #15] 800b2ba: b29b uxth r3, r3 800b2bc: 4a18 ldr r2, [pc, #96] @ (800b320 ) 800b2be: f8b2 2011 ldrh.w r2, [r2, #17] 800b2c2: b292 uxth r2, r2 800b2c4: 4619 mov r1, r3 800b2c6: 2000 movs r0, #0 800b2c8: f7ff febc bl 800b044 } ED_Delay(CAN_DELAY); 800b2cc: 2014 movs r0, #20 800b2ce: f7ff fb67 bl 800a9a0 if(CONN.MeasuredVoltage > 490){ 800b2d2: 4b13 ldr r3, [pc, #76] @ (800b320 ) 800b2d4: f8b3 3013 ldrh.w r3, [r3, #19] 800b2d8: b29b uxth r3, r3 800b2da: f5b3 7ff5 cmp.w r3, #490 @ 0x1ea 800b2de: d917 bls.n 800b310 if(PSU0.hv_tick == 0){ 800b2e0: 4b11 ldr r3, [pc, #68] @ (800b328 ) 800b2e2: 69db ldr r3, [r3, #28] 800b2e4: 2b00 cmp r3, #0 800b2e6: d105 bne.n 800b2f4 PSU0.hv_tick = HAL_GetTick(); 800b2e8: f003 fa4e bl 800e788 800b2ec: 4603 mov r3, r0 800b2ee: 4a0e ldr r2, [pc, #56] @ (800b328 ) 800b2f0: 61d3 str r3, [r2, #28] } // PSU_SetHVMode(0, PSU0.hv_mode); // auto set, no need // ED_Delay(CAN_DELAY); } 800b2f2: e010 b.n 800b316 }else if((HAL_GetTick() - PSU0.hv_tick) >= 10000){ 800b2f4: f003 fa48 bl 800e788 800b2f8: 4602 mov r2, r0 800b2fa: 4b0b ldr r3, [pc, #44] @ (800b328 ) 800b2fc: 69db ldr r3, [r3, #28] 800b2fe: 1ad3 subs r3, r2, r3 800b300: f242 720f movw r2, #9999 @ 0x270f 800b304: 4293 cmp r3, r2 800b306: d906 bls.n 800b316 PSU0.hv_mode = 1; 800b308: 4b07 ldr r3, [pc, #28] @ (800b328 ) 800b30a: 2201 movs r2, #1 800b30c: 761a strb r2, [r3, #24] } 800b30e: e002 b.n 800b316 PSU0.hv_tick = 0; 800b310: 4b05 ldr r3, [pc, #20] @ (800b328 ) 800b312: 2200 movs r2, #0 800b314: 61da str r2, [r3, #28] } 800b316: bf00 nop 800b318: 3708 adds r7, #8 800b31a: 46bd mov sp, r7 800b31c: bd80 pop {r7, pc} 800b31e: bf00 nop 800b320: 200003b0 .word 0x200003b0 800b324: cccccccd .word 0xcccccccd 800b328: 20000904 .word 0x20000904 800b32c: 66666667 .word 0x66666667 0800b330 : void PSU_Task(void){ 800b330: b598 push {r3, r4, r7, lr} 800b332: af00 add r7, sp, #0 static uint32_t psu_on_tick = 0; static uint32_t cont_ok_tick = 0; // Обновляем ONLINE/READY по таймауту if((HAL_GetTick() - can_lastpacket) > PSU_ONLINE_TIMEOUT){ 800b334: f003 fa28 bl 800e788 800b338: 4602 mov r2, r0 800b33a: 4bb3 ldr r3, [pc, #716] @ (800b608 ) 800b33c: 681b ldr r3, [r3, #0] 800b33e: 1ad3 subs r3, r2, r3 800b340: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b344: d920 bls.n 800b388 PSU0.online = 0; 800b346: 4bb1 ldr r3, [pc, #708] @ (800b60c ) 800b348: 2200 movs r2, #0 800b34a: 721a strb r2, [r3, #8] PSU0.PSU_enabled = 0; 800b34c: 4baf ldr r3, [pc, #700] @ (800b60c ) 800b34e: 2200 movs r2, #0 800b350: 729a strb r2, [r3, #10] PSU_04.moduleTemperature = 0; 800b352: 4baf ldr r3, [pc, #700] @ (800b610 ) 800b354: 2200 movs r2, #0 800b356: 711a strb r2, [r3, #4] PSU_04.modularForm0 = 0; 800b358: 4bad ldr r3, [pc, #692] @ (800b610 ) 800b35a: 2200 movs r2, #0 800b35c: 721a strb r2, [r3, #8] PSU_04.modularForm1 = 0; 800b35e: 4bac ldr r3, [pc, #688] @ (800b610 ) 800b360: 2200 movs r2, #0 800b362: 71da strb r2, [r3, #7] PSU_04.modularForm2 = 0; 800b364: 4baa ldr r3, [pc, #680] @ (800b610 ) 800b366: 2200 movs r2, #0 800b368: 719a strb r2, [r3, #6] PSU_06.VAB = 0; 800b36a: 4baa ldr r3, [pc, #680] @ (800b614 ) 800b36c: 2200 movs r2, #0 800b36e: 609a str r2, [r3, #8] PSU_06.VBC = 0; 800b370: 4ba8 ldr r3, [pc, #672] @ (800b614 ) 800b372: 2200 movs r2, #0 800b374: 60da str r2, [r3, #12] PSU_06.VCA = 0; 800b376: 4ba7 ldr r3, [pc, #668] @ (800b614 ) 800b378: 2200 movs r2, #0 800b37a: 611a str r2, [r3, #16] PSU_09.moduleNCurrent = 0; 800b37c: 4ba6 ldr r3, [pc, #664] @ (800b618 ) 800b37e: 2200 movs r2, #0 800b380: 60da str r2, [r3, #12] PSU_09.moduleNVoltage = 0; 800b382: 4ba5 ldr r3, [pc, #660] @ (800b618 ) 800b384: 2200 movs r2, #0 800b386: 609a str r2, [r3, #8] } if(!PSU0.online || !PSU0.enableAC){ 800b388: 4ba0 ldr r3, [pc, #640] @ (800b60c ) 800b38a: 7a1b ldrb r3, [r3, #8] 800b38c: 2b00 cmp r3, #0 800b38e: d003 beq.n 800b398 800b390: 4b9e ldr r3, [pc, #632] @ (800b60c ) 800b392: 781b ldrb r3, [r3, #0] 800b394: 2b00 cmp r3, #0 800b396: d10c bne.n 800b3b2 CONN.MeasuredVoltage = 0; 800b398: 4ba0 ldr r3, [pc, #640] @ (800b61c ) 800b39a: 2200 movs r2, #0 800b39c: 74da strb r2, [r3, #19] 800b39e: 2200 movs r2, #0 800b3a0: 751a strb r2, [r3, #20] CONN.MeasuredCurrent = 0; 800b3a2: 4b9e ldr r3, [pc, #632] @ (800b61c ) 800b3a4: 2200 movs r2, #0 800b3a6: 755a strb r2, [r3, #21] 800b3a8: 2200 movs r2, #0 800b3aa: 759a strb r2, [r3, #22] CONN.outputEnabled = 0; 800b3ac: 4b9b ldr r3, [pc, #620] @ (800b61c ) 800b3ae: 2200 movs r2, #0 800b3b0: 761a strb r2, [r3, #24] } // Управление AC-контактором с задержкой отключения 1 минута if(CONN.EvConnected){ 800b3b2: 4b9a ldr r3, [pc, #616] @ (800b61c ) 800b3b4: 7f9b ldrb r3, [r3, #30] 800b3b6: 2b00 cmp r3, #0 800b3b8: d00c beq.n 800b3d4 RELAY_Write(RELAY_AC, 1); 800b3ba: 2101 movs r1, #1 800b3bc: 2004 movs r0, #4 800b3be: f7fe f9fb bl 80097b8 psu_on_tick = HAL_GetTick(); 800b3c2: f003 f9e1 bl 800e788 800b3c6: 4603 mov r3, r0 800b3c8: 4a95 ldr r2, [pc, #596] @ (800b620 ) 800b3ca: 6013 str r3, [r2, #0] PSU0.enableAC = 1; 800b3cc: 4b8f ldr r3, [pc, #572] @ (800b60c ) 800b3ce: 2201 movs r2, #1 800b3d0: 701a strb r2, [r3, #0] 800b3d2: e010 b.n 800b3f6 }else{ if((HAL_GetTick() - psu_on_tick) > 1 * 60000){ 800b3d4: f003 f9d8 bl 800e788 800b3d8: 4602 mov r2, r0 800b3da: 4b91 ldr r3, [pc, #580] @ (800b620 ) 800b3dc: 681b ldr r3, [r3, #0] 800b3de: 1ad3 subs r3, r2, r3 800b3e0: f64e 2260 movw r2, #60000 @ 0xea60 800b3e4: 4293 cmp r3, r2 800b3e6: d906 bls.n 800b3f6 RELAY_Write(RELAY_AC, 0); 800b3e8: 2100 movs r1, #0 800b3ea: 2004 movs r0, #4 800b3ec: f7fe f9e4 bl 80097b8 PSU0.enableAC = 0; 800b3f0: 4b86 ldr r3, [pc, #536] @ (800b60c ) 800b3f2: 2200 movs r2, #0 800b3f4: 701a strb r2, [r3, #0] } } // Текущее состояние DC-контактора по обратной связи PSU0.CONT_enabled = IN_ReadInput(IN_CONT_FB_DC); 800b3f6: 2005 movs r0, #5 800b3f8: f7fe fa5e bl 80098b8 800b3fc: 4603 mov r3, r0 800b3fe: 461a mov r2, r3 800b400: 4b82 ldr r3, [pc, #520] @ (800b60c ) 800b402: 72da strb r2, [r3, #11] // Обновляем ready с учётом ошибок if(PSU0.online && !PSU0.cont_fault && PSU0.enableAC){ 800b404: 4b81 ldr r3, [pc, #516] @ (800b60c ) 800b406: 7a1b ldrb r3, [r3, #8] 800b408: 2b00 cmp r3, #0 800b40a: d007 beq.n 800b41c 800b40c: 4b7f ldr r3, [pc, #508] @ (800b60c ) 800b40e: 7b1b ldrb r3, [r3, #12] 800b410: 2b00 cmp r3, #0 800b412: d103 bne.n 800b41c 800b414: 4b7d ldr r3, [pc, #500] @ (800b60c ) 800b416: 781b ldrb r3, [r3, #0] 800b418: 2b00 cmp r3, #0 800b41a: d102 bne.n 800b422 // PSU0.ready = 1; }else{ PSU0.ready = 0; 800b41c: 4b7b ldr r3, [pc, #492] @ (800b60c ) 800b41e: 2200 movs r2, #0 800b420: 725a strb r2, [r3, #9] } switch(PSU0.state){ 800b422: 4b7a ldr r3, [pc, #488] @ (800b60c ) 800b424: 79db ldrb r3, [r3, #7] 800b426: 2b09 cmp r3, #9 800b428: f200 8151 bhi.w 800b6ce 800b42c: a201 add r2, pc, #4 @ (adr r2, 800b434 ) 800b42e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b432: bf00 nop 800b434: 0800b45d .word 0x0800b45d 800b438: 0800b491 .word 0x0800b491 800b43c: 0800b4ad .word 0x0800b4ad 800b440: 0800b4eb .word 0x0800b4eb 800b444: 0800b52f .word 0x0800b52f 800b448: 0800b571 .word 0x0800b571 800b44c: 0800b5db .word 0x0800b5db 800b450: 0800b681 .word 0x0800b681 800b454: 0800b631 .word 0x0800b631 800b458: 0800b6bb .word 0x0800b6bb case PSU_UNREADY: PSU0.enableOutput = 0; 800b45c: 4b6b ldr r3, [pc, #428] @ (800b60c ) 800b45e: 2200 movs r2, #0 800b460: 705a strb r2, [r3, #1] RELAY_Write(RELAY_DC, 0); 800b462: 2100 movs r1, #0 800b464: 2003 movs r0, #3 800b466: f7fe f9a7 bl 80097b8 if(PSU0.online && PSU0.enableAC && !PSU0.cont_fault){ 800b46a: 4b68 ldr r3, [pc, #416] @ (800b60c ) 800b46c: 7a1b ldrb r3, [r3, #8] 800b46e: 2b00 cmp r3, #0 800b470: f000 8131 beq.w 800b6d6 800b474: 4b65 ldr r3, [pc, #404] @ (800b60c ) 800b476: 781b ldrb r3, [r3, #0] 800b478: 2b00 cmp r3, #0 800b47a: f000 812c beq.w 800b6d6 800b47e: 4b63 ldr r3, [pc, #396] @ (800b60c ) 800b480: 7b1b ldrb r3, [r3, #12] 800b482: 2b00 cmp r3, #0 800b484: f040 8127 bne.w 800b6d6 PSU_SwitchState(PSU_INITIALIZING); 800b488: 2001 movs r0, #1 800b48a: f7ff fc8f bl 800adac } break; 800b48e: e122 b.n 800b6d6 case PSU_INITIALIZING: if(PSU_StateTime() > 4000){ // Wait 4s for PSU to initialize 800b490: f7ff fca0 bl 800add4 800b494: 4603 mov r3, r0 800b496: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b49a: f240 811e bls.w 800b6da PSU0.ready = 1; 800b49e: 4b5b ldr r3, [pc, #364] @ (800b60c ) 800b4a0: 2201 movs r2, #1 800b4a2: 725a strb r2, [r3, #9] PSU_SwitchState(PSU_READY); 800b4a4: 2002 movs r0, #2 800b4a6: f7ff fc81 bl 800adac } break; 800b4aa: e116 b.n 800b6da case PSU_READY: // модуль готов, но выключен PSU0.hv_mode = 0; 800b4ac: 4b57 ldr r3, [pc, #348] @ (800b60c ) 800b4ae: 2200 movs r2, #0 800b4b0: 761a strb r2, [r3, #24] PSU0.hv_tick = 0; 800b4b2: 4b56 ldr r3, [pc, #344] @ (800b60c ) 800b4b4: 2200 movs r2, #0 800b4b6: 61da str r2, [r3, #28] RELAY_Write(RELAY_DC, 0); 800b4b8: 2100 movs r1, #0 800b4ba: 2003 movs r0, #3 800b4bc: f7fe f97c bl 80097b8 if(!PSU0.ready){ 800b4c0: 4b52 ldr r3, [pc, #328] @ (800b60c ) 800b4c2: 7a5b ldrb r3, [r3, #9] 800b4c4: 2b00 cmp r3, #0 800b4c6: d103 bne.n 800b4d0 PSU_SwitchState(PSU_UNREADY); 800b4c8: 2000 movs r0, #0 800b4ca: f7ff fc6f bl 800adac break; 800b4ce: e115 b.n 800b6fc } if(CONN.EnableOutput){ 800b4d0: 4b52 ldr r3, [pc, #328] @ (800b61c ) 800b4d2: 7ddb ldrb r3, [r3, #23] 800b4d4: 2b00 cmp r3, #0 800b4d6: f000 8102 beq.w 800b6de PSU_Enable(0, 1); 800b4da: 2101 movs r1, #1 800b4dc: 2000 movs r0, #0 800b4de: f7ff fd81 bl 800afe4 PSU_SwitchState(PSU_WAIT_ACK_ON); 800b4e2: 2003 movs r0, #3 800b4e4: f7ff fc62 bl 800adac } break; 800b4e8: e0f9 b.n 800b6de case PSU_WAIT_ACK_ON: if(PSU0.PSU_enabled && PSU0.ready){ 800b4ea: 4b48 ldr r3, [pc, #288] @ (800b60c ) 800b4ec: 7a9b ldrb r3, [r3, #10] 800b4ee: 2b00 cmp r3, #0 800b4f0: d007 beq.n 800b502 800b4f2: 4b46 ldr r3, [pc, #280] @ (800b60c ) 800b4f4: 7a5b ldrb r3, [r3, #9] 800b4f6: 2b00 cmp r3, #0 800b4f8: d003 beq.n 800b502 PSU_SwitchState(PSU_CONT_WAIT_ACK_ON); 800b4fa: 2004 movs r0, #4 800b4fc: f7ff fc56 bl 800adac PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU on timeout\n"); } break; 800b500: e0ef b.n 800b6e2 }else if(PSU_StateTime() > 10000){ 800b502: f7ff fc67 bl 800add4 800b506: 4603 mov r3, r0 800b508: f242 7210 movw r2, #10000 @ 0x2710 800b50c: 4293 cmp r3, r2 800b50e: f240 80e8 bls.w 800b6e2 PSU0.psu_fault = 1; 800b512: 4b3e ldr r3, [pc, #248] @ (800b60c ) 800b514: 2201 movs r2, #1 800b516: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b518: 4b40 ldr r3, [pc, #256] @ (800b61c ) 800b51a: 220a movs r2, #10 800b51c: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b51e: 2000 movs r0, #0 800b520: f7ff fc44 bl 800adac log_printf(LOG_ERR, "PSU on timeout\n"); 800b524: 493f ldr r1, [pc, #252] @ (800b624 ) 800b526: 2004 movs r0, #4 800b528: f7ff f81e bl 800a568 break; 800b52c: e0d9 b.n 800b6e2 case PSU_CONT_WAIT_ACK_ON: // замыкаем DC-контактор и ждём подтверждение RELAY_Write(RELAY_DC, 1); 800b52e: 2101 movs r1, #1 800b530: 2003 movs r0, #3 800b532: f7fe f941 bl 80097b8 if(PSU0.CONT_enabled){ 800b536: 4b35 ldr r3, [pc, #212] @ (800b60c ) 800b538: 7adb ldrb r3, [r3, #11] 800b53a: 2b00 cmp r3, #0 800b53c: d003 beq.n 800b546 PSU_SwitchState(PSU_CONNECTED); 800b53e: 2005 movs r0, #5 800b540: f7ff fc34 bl 800adac PSU0.cont_fault = 1; CONN.chargingError = CONN_ERR_CONTACTOR; PSU_SwitchState(PSU_CURRENT_DROP); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b544: e0cf b.n 800b6e6 }else if(PSU_StateTime() > 1000){ 800b546: f7ff fc45 bl 800add4 800b54a: 4603 mov r3, r0 800b54c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b550: f240 80c9 bls.w 800b6e6 PSU0.cont_fault = 1; 800b554: 4b2d ldr r3, [pc, #180] @ (800b60c ) 800b556: 2201 movs r2, #1 800b558: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b55a: 4b30 ldr r3, [pc, #192] @ (800b61c ) 800b55c: 2207 movs r2, #7 800b55e: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_CURRENT_DROP); 800b560: 2006 movs r0, #6 800b562: f7ff fc23 bl 800adac log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b566: 4930 ldr r1, [pc, #192] @ (800b628 ) 800b568: 2004 movs r0, #4 800b56a: f7fe fffd bl 800a568 break; 800b56e: e0ba b.n 800b6e6 case PSU_CONNECTED: // Основное рабочее состояние if(!CONN.EnableOutput || !PSU0.ready){ 800b570: 4b2a ldr r3, [pc, #168] @ (800b61c ) 800b572: 7ddb ldrb r3, [r3, #23] 800b574: 2b00 cmp r3, #0 800b576: d003 beq.n 800b580 800b578: 4b24 ldr r3, [pc, #144] @ (800b60c ) 800b57a: 7a5b ldrb r3, [r3, #9] 800b57c: 2b00 cmp r3, #0 800b57e: d103 bne.n 800b588 PSU_SwitchState(PSU_CURRENT_DROP); 800b580: 2006 movs r0, #6 800b582: f7ff fc13 bl 800adac break; 800b586: e0b9 b.n 800b6fc } // контроль контактора: 1 c таймаут if (IN_ReadInput(IN_CONT_FB_DC) != RELAY_Read(RELAY_DC)){ 800b588: 2005 movs r0, #5 800b58a: f7fe f995 bl 80098b8 800b58e: 4603 mov r3, r0 800b590: 461c mov r4, r3 800b592: 2003 movs r0, #3 800b594: f7fe f980 bl 8009898 800b598: 4603 mov r3, r0 800b59a: 429c cmp r4, r3 800b59c: d017 beq.n 800b5ce if((HAL_GetTick() - cont_ok_tick) > 1000){ 800b59e: f003 f8f3 bl 800e788 800b5a2: 4602 mov r2, r0 800b5a4: 4b21 ldr r3, [pc, #132] @ (800b62c ) 800b5a6: 681b ldr r3, [r3, #0] 800b5a8: 1ad3 subs r3, r2, r3 800b5aa: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b5ae: f240 809c bls.w 800b6ea CONN.chargingError = CONN_ERR_CONTACTOR; 800b5b2: 4b1a ldr r3, [pc, #104] @ (800b61c ) 800b5b4: 2207 movs r2, #7 800b5b6: 775a strb r2, [r3, #29] PSU0.cont_fault = 1; 800b5b8: 4b14 ldr r3, [pc, #80] @ (800b60c ) 800b5ba: 2201 movs r2, #1 800b5bc: 731a strb r2, [r3, #12] PSU_SwitchState(PSU_CURRENT_DROP); 800b5be: 2006 movs r0, #6 800b5c0: f7ff fbf4 bl 800adac log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b5c4: 4918 ldr r1, [pc, #96] @ (800b628 ) 800b5c6: 2004 movs r0, #4 800b5c8: f7fe ffce bl 800a568 } }else{ cont_ok_tick = HAL_GetTick(); } break; 800b5cc: e08d b.n 800b6ea cont_ok_tick = HAL_GetTick(); 800b5ce: f003 f8db bl 800e788 800b5d2: 4603 mov r3, r0 800b5d4: 4a15 ldr r2, [pc, #84] @ (800b62c ) 800b5d6: 6013 str r3, [r2, #0] break; 800b5d8: e087 b.n 800b6ea case PSU_CURRENT_DROP: // снижаем ток до нуля перед отключением DC CONN.RequestedCurrent = 0; 800b5da: 4b10 ldr r3, [pc, #64] @ (800b61c ) 800b5dc: 2200 movs r2, #0 800b5de: 745a strb r2, [r3, #17] 800b5e0: 2200 movs r2, #0 800b5e2: 749a strb r2, [r3, #18] // если ток действительно упал или вышло время, отключаем DC if((CONN.MeasuredCurrent < 30) || (PSU_StateTime() > 5000)){ 800b5e4: 4b0d ldr r3, [pc, #52] @ (800b61c ) 800b5e6: f8b3 3015 ldrh.w r3, [r3, #21] 800b5ea: b29b uxth r3, r3 800b5ec: 2b1d cmp r3, #29 800b5ee: d906 bls.n 800b5fe 800b5f0: f7ff fbf0 bl 800add4 800b5f4: 4603 mov r3, r0 800b5f6: f241 3288 movw r2, #5000 @ 0x1388 800b5fa: 4293 cmp r3, r2 800b5fc: d977 bls.n 800b6ee PSU_SwitchState(PSU_CONT_WAIT_ACK_OFF); 800b5fe: 2008 movs r0, #8 800b600: f7ff fbd4 bl 800adac } break; 800b604: e073 b.n 800b6ee 800b606: bf00 nop 800b608: 2000092c .word 0x2000092c 800b60c: 20000904 .word 0x20000904 800b610: 200008cc .word 0x200008cc 800b614: 200008d8 .word 0x200008d8 800b618: 200008f4 .word 0x200008f4 800b61c: 200003b0 .word 0x200003b0 800b620: 20000954 .word 0x20000954 800b624: 08017574 .word 0x08017574 800b628: 08017584 .word 0x08017584 800b62c: 20000958 .word 0x20000958 case PSU_CONT_WAIT_ACK_OFF: RELAY_Write(RELAY_DC, 0); 800b630: 2100 movs r1, #0 800b632: 2003 movs r0, #3 800b634: f7fe f8c0 bl 80097b8 if(!PSU0.CONT_enabled){ 800b638: 4b31 ldr r3, [pc, #196] @ (800b700 ) 800b63a: 7adb ldrb r3, [r3, #11] 800b63c: 2b00 cmp r3, #0 800b63e: d107 bne.n 800b650 PSU_Enable(0, 0); 800b640: 2100 movs r1, #0 800b642: 2000 movs r0, #0 800b644: f7ff fcce bl 800afe4 PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b648: 2007 movs r0, #7 800b64a: f7ff fbaf bl 800adac CONN.chargingError = CONN_ERR_CONTACTOR; PSU_Enable(0, 0); PSU_SwitchState(PSU_WAIT_ACK_OFF); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b64e: e050 b.n 800b6f2 }else if(PSU_StateTime() > 1000){ 800b650: f7ff fbc0 bl 800add4 800b654: 4603 mov r3, r0 800b656: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b65a: d94a bls.n 800b6f2 PSU0.cont_fault = 1; 800b65c: 4b28 ldr r3, [pc, #160] @ (800b700 ) 800b65e: 2201 movs r2, #1 800b660: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b662: 4b28 ldr r3, [pc, #160] @ (800b704 ) 800b664: 2207 movs r2, #7 800b666: 775a strb r2, [r3, #29] PSU_Enable(0, 0); 800b668: 2100 movs r1, #0 800b66a: 2000 movs r0, #0 800b66c: f7ff fcba bl 800afe4 PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b670: 2007 movs r0, #7 800b672: f7ff fb9b bl 800adac log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b676: 4924 ldr r1, [pc, #144] @ (800b708 ) 800b678: 2004 movs r0, #4 800b67a: f7fe ff75 bl 800a568 break; 800b67e: e038 b.n 800b6f2 case PSU_WAIT_ACK_OFF: if(!PSU0.PSU_enabled){ 800b680: 4b1f ldr r3, [pc, #124] @ (800b700 ) 800b682: 7a9b ldrb r3, [r3, #10] 800b684: 2b00 cmp r3, #0 800b686: d103 bne.n 800b690 PSU_SwitchState(PSU_OFF_PAUSE); 800b688: 2009 movs r0, #9 800b68a: f7ff fb8f bl 800adac PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU off timeout\n"); } break; 800b68e: e032 b.n 800b6f6 }else if(PSU_StateTime() > 10000){ 800b690: f7ff fba0 bl 800add4 800b694: 4603 mov r3, r0 800b696: f242 7210 movw r2, #10000 @ 0x2710 800b69a: 4293 cmp r3, r2 800b69c: d92b bls.n 800b6f6 PSU0.psu_fault = 1; 800b69e: 4b18 ldr r3, [pc, #96] @ (800b700 ) 800b6a0: 2201 movs r2, #1 800b6a2: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b6a4: 4b17 ldr r3, [pc, #92] @ (800b704 ) 800b6a6: 220a movs r2, #10 800b6a8: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b6aa: 2000 movs r0, #0 800b6ac: f7ff fb7e bl 800adac log_printf(LOG_ERR, "PSU off timeout\n"); 800b6b0: 4916 ldr r1, [pc, #88] @ (800b70c ) 800b6b2: 2004 movs r0, #4 800b6b4: f7fe ff58 bl 800a568 break; 800b6b8: e01d b.n 800b6f6 case PSU_OFF_PAUSE: if(PSU_StateTime() > 4000){ 800b6ba: f7ff fb8b bl 800add4 800b6be: 4603 mov r3, r0 800b6c0: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b6c4: d919 bls.n 800b6fa PSU_SwitchState(PSU_READY); 800b6c6: 2002 movs r0, #2 800b6c8: f7ff fb70 bl 800adac } break; 800b6cc: e015 b.n 800b6fa default: PSU_SwitchState(PSU_UNREADY); 800b6ce: 2000 movs r0, #0 800b6d0: f7ff fb6c bl 800adac break; 800b6d4: e012 b.n 800b6fc break; 800b6d6: bf00 nop 800b6d8: e010 b.n 800b6fc break; 800b6da: bf00 nop 800b6dc: e00e b.n 800b6fc break; 800b6de: bf00 nop 800b6e0: e00c b.n 800b6fc break; 800b6e2: bf00 nop 800b6e4: e00a b.n 800b6fc break; 800b6e6: bf00 nop 800b6e8: e008 b.n 800b6fc break; 800b6ea: bf00 nop 800b6ec: e006 b.n 800b6fc break; 800b6ee: bf00 nop 800b6f0: e004 b.n 800b6fc break; 800b6f2: bf00 nop 800b6f4: e002 b.n 800b6fc break; 800b6f6: bf00 nop 800b6f8: e000 b.n 800b6fc break; 800b6fa: bf00 nop } } 800b6fc: bf00 nop 800b6fe: bd98 pop {r3, r4, r7, pc} 800b700: 20000904 .word 0x20000904 800b704: 200003b0 .word 0x200003b0 800b708: 08017584 .word 0x08017584 800b70c: 080175a4 .word 0x080175a4 0800b710 : .Th = 10, .Tf = 50, .Tl = 0, }; void LED_Write(){ 800b710: b580 push {r7, lr} 800b712: af00 add r7, sp, #0 if(CONN.chargingError != CONN_NO_ERROR){ 800b714: 4b3c ldr r3, [pc, #240] @ (800b808 ) 800b716: 7f5b ldrb r3, [r3, #29] 800b718: 2b00 cmp r3, #0 800b71a: d003 beq.n 800b724 LED_SetColor(&color_error); 800b71c: 483b ldr r0, [pc, #236] @ (800b80c ) 800b71e: f000 fb25 bl 800bd6c return; 800b722: e06f b.n 800b804 } if(CONN.connControl == CMD_FORCE_UNLOCK){ 800b724: 4b38 ldr r3, [pc, #224] @ (800b808 ) 800b726: 781b ldrb r3, [r3, #0] 800b728: 2b03 cmp r3, #3 800b72a: d103 bne.n 800b734 LED_SetColor(&color_unlock); 800b72c: 4838 ldr r0, [pc, #224] @ (800b810 ) 800b72e: f000 fb1d bl 800bd6c return; 800b732: e067 b.n 800b804 } if(CONN.connControl == CMD_STOP){ 800b734: 4b34 ldr r3, [pc, #208] @ (800b808 ) 800b736: 781b ldrb r3, [r3, #0] 800b738: 2b01 cmp r3, #1 800b73a: d103 bne.n 800b744 LED_SetColor(&color_estop); 800b73c: 4835 ldr r0, [pc, #212] @ (800b814 ) 800b73e: f000 fb15 bl 800bd6c return; 800b742: e05f b.n 800b804 } switch(CONN.connState){ 800b744: 4b30 ldr r3, [pc, #192] @ (800b808 ) 800b746: 785b ldrb r3, [r3, #1] 800b748: 2b0d cmp r3, #13 800b74a: d857 bhi.n 800b7fc 800b74c: a201 add r2, pc, #4 @ (adr r2, 800b754 ) 800b74e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b752: bf00 nop 800b754: 0800b78d .word 0x0800b78d 800b758: 0800b795 .word 0x0800b795 800b75c: 0800b79d .word 0x0800b79d 800b760: 0800b7a5 .word 0x0800b7a5 800b764: 0800b7ad .word 0x0800b7ad 800b768: 0800b7b5 .word 0x0800b7b5 800b76c: 0800b7bd .word 0x0800b7bd 800b770: 0800b7c5 .word 0x0800b7c5 800b774: 0800b7cd .word 0x0800b7cd 800b778: 0800b7d5 .word 0x0800b7d5 800b77c: 0800b7dd .word 0x0800b7dd 800b780: 0800b7e5 .word 0x0800b7e5 800b784: 0800b7ed .word 0x0800b7ed 800b788: 0800b7f5 .word 0x0800b7f5 case Unknown: LED_SetColor(&color_unknown); 800b78c: 4822 ldr r0, [pc, #136] @ (800b818 ) 800b78e: f000 faed bl 800bd6c break; 800b792: e037 b.n 800b804 case Unplugged: LED_SetColor(&color_unplugged); 800b794: 4821 ldr r0, [pc, #132] @ (800b81c ) 800b796: f000 fae9 bl 800bd6c break; 800b79a: e033 b.n 800b804 case Disabled: LED_SetColor(&color_error); 800b79c: 481b ldr r0, [pc, #108] @ (800b80c ) 800b79e: f000 fae5 bl 800bd6c break; 800b7a2: e02f b.n 800b804 case Preparing: LED_SetColor(&color_preparing); 800b7a4: 481e ldr r0, [pc, #120] @ (800b820 ) 800b7a6: f000 fae1 bl 800bd6c break; 800b7aa: e02b b.n 800b804 case AuthRequired: LED_SetColor(&color_preparing); 800b7ac: 481c ldr r0, [pc, #112] @ (800b820 ) 800b7ae: f000 fadd bl 800bd6c break; 800b7b2: e027 b.n 800b804 case WaitingForEnergy: LED_SetColor(&color_charging); 800b7b4: 481b ldr r0, [pc, #108] @ (800b824 ) 800b7b6: f000 fad9 bl 800bd6c break; 800b7ba: e023 b.n 800b804 case ChargingPausedEV: LED_SetColor(&color_charging); 800b7bc: 4819 ldr r0, [pc, #100] @ (800b824 ) 800b7be: f000 fad5 bl 800bd6c break; 800b7c2: e01f b.n 800b804 case ChargingPausedEVSE: LED_SetColor(&color_charging); 800b7c4: 4817 ldr r0, [pc, #92] @ (800b824 ) 800b7c6: f000 fad1 bl 800bd6c break; 800b7ca: e01b b.n 800b804 case Charging: LED_SetColor(&color_charging); 800b7cc: 4815 ldr r0, [pc, #84] @ (800b824 ) 800b7ce: f000 facd bl 800bd6c break; 800b7d2: e017 b.n 800b804 case AuthTimeout: LED_SetColor(&color_finished); 800b7d4: 4814 ldr r0, [pc, #80] @ (800b828 ) 800b7d6: f000 fac9 bl 800bd6c break; 800b7da: e013 b.n 800b804 case Finished: LED_SetColor(&color_finished); 800b7dc: 4812 ldr r0, [pc, #72] @ (800b828 ) 800b7de: f000 fac5 bl 800bd6c break; 800b7e2: e00f b.n 800b804 case FinishedEVSE: LED_SetColor(&color_finished); 800b7e4: 4810 ldr r0, [pc, #64] @ (800b828 ) 800b7e6: f000 fac1 bl 800bd6c break; 800b7ea: e00b b.n 800b804 case FinishedEV: LED_SetColor(&color_finished); 800b7ec: 480e ldr r0, [pc, #56] @ (800b828 ) 800b7ee: f000 fabd bl 800bd6c break; 800b7f2: e007 b.n 800b804 case Replugging: LED_SetColor(&color_preparing); 800b7f4: 480a ldr r0, [pc, #40] @ (800b820 ) 800b7f6: f000 fab9 bl 800bd6c break; 800b7fa: e003 b.n 800b804 default: LED_SetColor(&color_unknown); 800b7fc: 4806 ldr r0, [pc, #24] @ (800b818 ) 800b7fe: f000 fab5 bl 800bd6c break; 800b802: bf00 nop } } 800b804: bd80 pop {r7, pc} 800b806: bf00 nop 800b808: 200003b0 .word 0x200003b0 800b80c: 20000060 .word 0x20000060 800b810: 20000018 .word 0x20000018 800b814: 2000000c .word 0x2000000c 800b818: 20000024 .word 0x20000024 800b81c: 20000030 .word 0x20000030 800b820: 2000003c .word 0x2000003c 800b824: 20000048 .word 0x20000048 800b828: 20000054 .word 0x20000054 0800b82c : void interpolateColors(RGB_t* color1, RGB_t* color2, uint16_t a, uint16_t b, RGB_t *result) { 800b82c: b480 push {r7} 800b82e: b087 sub sp, #28 800b830: af00 add r7, sp, #0 800b832: 60f8 str r0, [r7, #12] 800b834: 60b9 str r1, [r7, #8] 800b836: 4611 mov r1, r2 800b838: 461a mov r2, r3 800b83a: 460b mov r3, r1 800b83c: 80fb strh r3, [r7, #6] 800b83e: 4613 mov r3, r2 800b840: 80bb strh r3, [r7, #4] // Проверяем, чтобы a не выходила за пределы диапазона if (a > b) a = b; 800b842: 88fa ldrh r2, [r7, #6] 800b844: 88bb ldrh r3, [r7, #4] 800b846: 429a cmp r2, r3 800b848: d901 bls.n 800b84e 800b84a: 88bb ldrh r3, [r7, #4] 800b84c: 80fb strh r3, [r7, #6] if(b==0) b = 1; 800b84e: 88bb ldrh r3, [r7, #4] 800b850: 2b00 cmp r3, #0 800b852: d101 bne.n 800b858 800b854: 2301 movs r3, #1 800b856: 80bb strh r3, [r7, #4] // Вычисляем коэффициент смешивания в виде целого числа uint16_t t = (a * 255) / b; // t будет от 0 до 255 800b858: 88fa ldrh r2, [r7, #6] 800b85a: 4613 mov r3, r2 800b85c: 021b lsls r3, r3, #8 800b85e: 1a9a subs r2, r3, r2 800b860: 88bb ldrh r3, [r7, #4] 800b862: fb92 f3f3 sdiv r3, r2, r3 800b866: 82fb strh r3, [r7, #22] // Линейная интерполяция с использованием целых чисел result->R = (color1->R * (255 - t) + color2->R * t) / 255; 800b868: 68fb ldr r3, [r7, #12] 800b86a: 781b ldrb r3, [r3, #0] 800b86c: 461a mov r2, r3 800b86e: 8afb ldrh r3, [r7, #22] 800b870: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b874: fb03 f202 mul.w r2, r3, r2 800b878: 68bb ldr r3, [r7, #8] 800b87a: 781b ldrb r3, [r3, #0] 800b87c: 4619 mov r1, r3 800b87e: 8afb ldrh r3, [r7, #22] 800b880: fb01 f303 mul.w r3, r1, r3 800b884: 4413 add r3, r2 800b886: 4a20 ldr r2, [pc, #128] @ (800b908 ) 800b888: fb82 1203 smull r1, r2, r2, r3 800b88c: 441a add r2, r3 800b88e: 11d2 asrs r2, r2, #7 800b890: 17db asrs r3, r3, #31 800b892: 1ad3 subs r3, r2, r3 800b894: b2da uxtb r2, r3 800b896: 6a3b ldr r3, [r7, #32] 800b898: 701a strb r2, [r3, #0] result->G = (color1->G * (255 - t) + color2->G * t) / 255; 800b89a: 68fb ldr r3, [r7, #12] 800b89c: 785b ldrb r3, [r3, #1] 800b89e: 461a mov r2, r3 800b8a0: 8afb ldrh r3, [r7, #22] 800b8a2: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b8a6: fb03 f202 mul.w r2, r3, r2 800b8aa: 68bb ldr r3, [r7, #8] 800b8ac: 785b ldrb r3, [r3, #1] 800b8ae: 4619 mov r1, r3 800b8b0: 8afb ldrh r3, [r7, #22] 800b8b2: fb01 f303 mul.w r3, r1, r3 800b8b6: 4413 add r3, r2 800b8b8: 4a13 ldr r2, [pc, #76] @ (800b908 ) 800b8ba: fb82 1203 smull r1, r2, r2, r3 800b8be: 441a add r2, r3 800b8c0: 11d2 asrs r2, r2, #7 800b8c2: 17db asrs r3, r3, #31 800b8c4: 1ad3 subs r3, r2, r3 800b8c6: b2da uxtb r2, r3 800b8c8: 6a3b ldr r3, [r7, #32] 800b8ca: 705a strb r2, [r3, #1] result->B = (color1->B * (255 - t) + color2->B * t) / 255; 800b8cc: 68fb ldr r3, [r7, #12] 800b8ce: 789b ldrb r3, [r3, #2] 800b8d0: 461a mov r2, r3 800b8d2: 8afb ldrh r3, [r7, #22] 800b8d4: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b8d8: fb03 f202 mul.w r2, r3, r2 800b8dc: 68bb ldr r3, [r7, #8] 800b8de: 789b ldrb r3, [r3, #2] 800b8e0: 4619 mov r1, r3 800b8e2: 8afb ldrh r3, [r7, #22] 800b8e4: fb01 f303 mul.w r3, r1, r3 800b8e8: 4413 add r3, r2 800b8ea: 4a07 ldr r2, [pc, #28] @ (800b908 ) 800b8ec: fb82 1203 smull r1, r2, r2, r3 800b8f0: 441a add r2, r3 800b8f2: 11d2 asrs r2, r2, #7 800b8f4: 17db asrs r3, r3, #31 800b8f6: 1ad3 subs r3, r2, r3 800b8f8: b2da uxtb r2, r3 800b8fa: 6a3b ldr r3, [r7, #32] 800b8fc: 709a strb r2, [r3, #2] } 800b8fe: bf00 nop 800b900: 371c adds r7, #28 800b902: 46bd mov sp, r7 800b904: bc80 pop {r7} 800b906: 4770 bx lr 800b908: 80808081 .word 0x80808081 0800b90c : #define _WS2812_DELAY_NOPS(n) __asm volatile(".rept " #n "\nnop\n.endr" ::: "memory") #define WS2812_DELAY_NOPS(n) _WS2812_DELAY_NOPS(n) static void ws2812_send_pixel(uint8_t r, uint8_t g, uint8_t b) { uint32_t tmp = ~(((uint32_t)g << 16) | ((uint32_t)r << 8) | (uint32_t)b); 800b90c: ea42 2200 orr.w r2, r2, r0, lsl #8 800b910: ea42 4201 orr.w r2, r2, r1, lsl #16 { 800b914: b430 push {r4, r5} uint32_t tmp = ~(((uint32_t)g << 16) | ((uint32_t)r << 8) | (uint32_t)b); 800b916: f04f 0c18 mov.w ip, #24 for (int i = 0; i < 24; i++) { LED_DATA_GPIO_Port->BSRR = LED_DATA_Pin; 800b91a: f44f 7500 mov.w r5, #512 @ 0x200 uint32_t tmp = ~(((uint32_t)g << 16) | ((uint32_t)r << 8) | (uint32_t)b); 800b91e: 43d3 mvns r3, r2 LED_DATA_GPIO_Port->BSRR = LED_DATA_Pin; 800b920: 4c56 ldr r4, [pc, #344] @ (800ba7c ) 800b922: e052 b.n 800b9ca if (tmp & (1U << 23)) { WS2812_DELAY_NOPS(WS2812_T0H_NOP); 800b924: bf00 nop 800b926: bf00 nop 800b928: bf00 nop 800b92a: bf00 nop 800b92c: bf00 nop 800b92e: bf00 nop 800b930: bf00 nop 800b932: bf00 nop 800b934: bf00 nop 800b936: bf00 nop 800b938: bf00 nop 800b93a: bf00 nop 800b93c: bf00 nop 800b93e: bf00 nop 800b940: bf00 nop 800b942: bf00 nop 800b944: bf00 nop 800b946: bf00 nop 800b948: bf00 nop 800b94a: bf00 nop 800b94c: bf00 nop 800b94e: bf00 nop 800b950: bf00 nop 800b952: bf00 nop 800b954: bf00 nop LED_DATA_GPIO_Port->BRR = LED_DATA_Pin; 800b956: 6165 str r5, [r4, #20] WS2812_DELAY_NOPS(WS2812_T0L_NOP); 800b958: bf00 nop 800b95a: bf00 nop 800b95c: bf00 nop 800b95e: bf00 nop 800b960: bf00 nop 800b962: bf00 nop 800b964: bf00 nop 800b966: bf00 nop 800b968: bf00 nop 800b96a: bf00 nop 800b96c: bf00 nop 800b96e: bf00 nop 800b970: bf00 nop 800b972: bf00 nop 800b974: bf00 nop 800b976: bf00 nop 800b978: bf00 nop 800b97a: bf00 nop 800b97c: bf00 nop 800b97e: bf00 nop 800b980: bf00 nop 800b982: bf00 nop 800b984: bf00 nop 800b986: bf00 nop 800b988: bf00 nop 800b98a: bf00 nop 800b98c: bf00 nop 800b98e: bf00 nop 800b990: bf00 nop 800b992: bf00 nop 800b994: bf00 nop 800b996: bf00 nop 800b998: bf00 nop 800b99a: bf00 nop 800b99c: bf00 nop 800b99e: bf00 nop 800b9a0: bf00 nop 800b9a2: bf00 nop 800b9a4: bf00 nop 800b9a6: bf00 nop 800b9a8: bf00 nop 800b9aa: bf00 nop 800b9ac: bf00 nop 800b9ae: bf00 nop 800b9b0: bf00 nop 800b9b2: bf00 nop 800b9b4: bf00 nop 800b9b6: bf00 nop 800b9b8: bf00 nop 800b9ba: bf00 nop 800b9bc: bf00 nop 800b9be: bf00 nop for (int i = 0; i < 24; i++) { 800b9c0: f1bc 0c01 subs.w ip, ip, #1 } else { WS2812_DELAY_NOPS(WS2812_T1H_NOP); LED_DATA_GPIO_Port->BRR = LED_DATA_Pin; WS2812_DELAY_NOPS(WS2812_T1L_NOP); } tmp <<= 1; 800b9c4: ea4f 0343 mov.w r3, r3, lsl #1 for (int i = 0; i < 24; i++) { 800b9c8: d055 beq.n 800ba76 if (tmp & (1U << 23)) { 800b9ca: 021a lsls r2, r3, #8 LED_DATA_GPIO_Port->BSRR = LED_DATA_Pin; 800b9cc: 6125 str r5, [r4, #16] if (tmp & (1U << 23)) { 800b9ce: d4a9 bmi.n 800b924 WS2812_DELAY_NOPS(WS2812_T1H_NOP); 800b9d0: bf00 nop 800b9d2: bf00 nop 800b9d4: bf00 nop 800b9d6: bf00 nop 800b9d8: bf00 nop 800b9da: bf00 nop 800b9dc: bf00 nop 800b9de: bf00 nop 800b9e0: bf00 nop 800b9e2: bf00 nop 800b9e4: bf00 nop 800b9e6: bf00 nop 800b9e8: bf00 nop 800b9ea: bf00 nop 800b9ec: bf00 nop 800b9ee: bf00 nop 800b9f0: bf00 nop 800b9f2: bf00 nop 800b9f4: bf00 nop 800b9f6: bf00 nop 800b9f8: bf00 nop 800b9fa: bf00 nop 800b9fc: bf00 nop 800b9fe: bf00 nop 800ba00: bf00 nop 800ba02: bf00 nop 800ba04: bf00 nop 800ba06: bf00 nop 800ba08: bf00 nop 800ba0a: bf00 nop 800ba0c: bf00 nop 800ba0e: bf00 nop 800ba10: bf00 nop 800ba12: bf00 nop 800ba14: bf00 nop 800ba16: bf00 nop 800ba18: bf00 nop 800ba1a: bf00 nop 800ba1c: bf00 nop 800ba1e: bf00 nop 800ba20: bf00 nop 800ba22: bf00 nop 800ba24: bf00 nop 800ba26: bf00 nop 800ba28: bf00 nop 800ba2a: bf00 nop 800ba2c: bf00 nop 800ba2e: bf00 nop 800ba30: bf00 nop 800ba32: bf00 nop 800ba34: bf00 nop 800ba36: bf00 nop LED_DATA_GPIO_Port->BRR = LED_DATA_Pin; 800ba38: 6165 str r5, [r4, #20] WS2812_DELAY_NOPS(WS2812_T1L_NOP); 800ba3a: bf00 nop 800ba3c: bf00 nop 800ba3e: bf00 nop 800ba40: bf00 nop 800ba42: bf00 nop 800ba44: bf00 nop 800ba46: bf00 nop 800ba48: bf00 nop 800ba4a: bf00 nop 800ba4c: bf00 nop 800ba4e: bf00 nop 800ba50: bf00 nop 800ba52: bf00 nop 800ba54: bf00 nop 800ba56: bf00 nop 800ba58: bf00 nop 800ba5a: bf00 nop 800ba5c: bf00 nop 800ba5e: bf00 nop 800ba60: bf00 nop 800ba62: bf00 nop 800ba64: bf00 nop 800ba66: bf00 nop 800ba68: bf00 nop 800ba6a: bf00 nop for (int i = 0; i < 24; i++) { 800ba6c: f1bc 0c01 subs.w ip, ip, #1 tmp <<= 1; 800ba70: ea4f 0343 mov.w r3, r3, lsl #1 for (int i = 0; i < 24; i++) { 800ba74: d1a9 bne.n 800b9ca } } 800ba76: bc30 pop {r4, r5} 800ba78: 4770 bx lr 800ba7a: bf00 nop 800ba7c: 40011000 .word 0x40011000 0800ba80 : static void ws2812_update(RGB_t *led0, RGB_t *led1) { 800ba80: b538 push {r3, r4, r5, lr} 800ba82: 460c mov r4, r1 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800ba84: f3ef 8510 mrs r5, PRIMASK __ASM volatile ("cpsid i" : : : "memory"); 800ba88: b672 cpsid i uint32_t primask = __get_PRIMASK(); __disable_irq(); ws2812_send_pixel(led0->R, led0->G, led0->B); 800ba8a: 7882 ldrb r2, [r0, #2] 800ba8c: 7841 ldrb r1, [r0, #1] 800ba8e: 7800 ldrb r0, [r0, #0] 800ba90: f7ff ff3c bl 800b90c ws2812_send_pixel(led1->R, led1->G, led1->B); 800ba94: 78a2 ldrb r2, [r4, #2] 800ba96: 7861 ldrb r1, [r4, #1] 800ba98: 7820 ldrb r0, [r4, #0] 800ba9a: f7ff ff37 bl 800b90c __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800ba9e: f385 8810 msr PRIMASK, r5 __set_PRIMASK(primask); } 800baa2: bd38 pop {r3, r4, r5, pc} 0800baa4 : #pragma GCC pop_options static RGB_t RGB_ScaleBrightness(const RGB_t *color) { 800baa4: b480 push {r7} 800baa6: b085 sub sp, #20 800baa8: af00 add r7, sp, #0 800baaa: 6078 str r0, [r7, #4] RGB_t out = { .R = (uint8_t)((uint16_t)color->R * WS2812_BRIGHTNESS / 255), 800baac: 687b ldr r3, [r7, #4] 800baae: 781b ldrb r3, [r3, #0] 800bab0: 461a mov r2, r3 800bab2: 4613 mov r3, r2 800bab4: 011b lsls r3, r3, #4 800bab6: 1a9b subs r3, r3, r2 800bab8: 009b lsls r3, r3, #2 800baba: 4a21 ldr r2, [pc, #132] @ (800bb40 ) 800babc: fb82 1203 smull r1, r2, r2, r3 800bac0: 441a add r2, r3 800bac2: 11d2 asrs r2, r2, #7 800bac4: 17db asrs r3, r3, #31 800bac6: 1ad3 subs r3, r2, r3 800bac8: b2db uxtb r3, r3 RGB_t out = { 800baca: 723b strb r3, [r7, #8] .G = (uint8_t)((uint16_t)color->G * WS2812_BRIGHTNESS / 255), 800bacc: 687b ldr r3, [r7, #4] 800bace: 785b ldrb r3, [r3, #1] 800bad0: 461a mov r2, r3 800bad2: 4613 mov r3, r2 800bad4: 011b lsls r3, r3, #4 800bad6: 1a9b subs r3, r3, r2 800bad8: 009b lsls r3, r3, #2 800bada: 4a19 ldr r2, [pc, #100] @ (800bb40 ) 800badc: fb82 1203 smull r1, r2, r2, r3 800bae0: 441a add r2, r3 800bae2: 11d2 asrs r2, r2, #7 800bae4: 17db asrs r3, r3, #31 800bae6: 1ad3 subs r3, r2, r3 800bae8: b2db uxtb r3, r3 RGB_t out = { 800baea: 727b strb r3, [r7, #9] .B = (uint8_t)((uint16_t)color->B * WS2812_BRIGHTNESS / 255), 800baec: 687b ldr r3, [r7, #4] 800baee: 789b ldrb r3, [r3, #2] 800baf0: 461a mov r2, r3 800baf2: 4613 mov r3, r2 800baf4: 011b lsls r3, r3, #4 800baf6: 1a9b subs r3, r3, r2 800baf8: 009b lsls r3, r3, #2 800bafa: 4a11 ldr r2, [pc, #68] @ (800bb40 ) 800bafc: fb82 1203 smull r1, r2, r2, r3 800bb00: 441a add r2, r3 800bb02: 11d2 asrs r2, r2, #7 800bb04: 17db asrs r3, r3, #31 800bb06: 1ad3 subs r3, r2, r3 800bb08: b2db uxtb r3, r3 RGB_t out = { 800bb0a: 72bb strb r3, [r7, #10] }; return out; 800bb0c: f107 030c add.w r3, r7, #12 800bb10: f107 0208 add.w r2, r7, #8 800bb14: 6812 ldr r2, [r2, #0] 800bb16: 4611 mov r1, r2 800bb18: 8019 strh r1, [r3, #0] 800bb1a: 3302 adds r3, #2 800bb1c: 0c12 lsrs r2, r2, #16 800bb1e: 701a strb r2, [r3, #0] 800bb20: 2300 movs r3, #0 800bb22: 7b3a ldrb r2, [r7, #12] 800bb24: f362 0307 bfi r3, r2, #0, #8 800bb28: 7b7a ldrb r2, [r7, #13] 800bb2a: f362 230f bfi r3, r2, #8, #8 800bb2e: 7bba ldrb r2, [r7, #14] 800bb30: f362 4317 bfi r3, r2, #16, #8 } 800bb34: 4618 mov r0, r3 800bb36: 3714 adds r7, #20 800bb38: 46bd mov sp, r7 800bb3a: bc80 pop {r7} 800bb3c: 4770 bx lr 800bb3e: bf00 nop 800bb40: 80808081 .word 0x80808081 0800bb44 : * Моргание красным на втором WS2812 при chargingError > 0. * Логика как Slave-LB24 LED_Task: N вспышек = код ошибки, пауза 30×100 ms. * Вызывается из LED_Task каждые 20 ms; шаг FSM — 100 ms. */ static void LED_Ws2812ErrorBlinkUpdate(void) { 800bb44: b580 push {r7, lr} 800bb46: b082 sub sp, #8 800bb48: af00 add r7, sp, #0 static uint8_t led_pause; static uint32_t blink_tick; static uint32_t flash_until; static CONN_Error_t last_error = CONN_NO_ERROR; const CONN_Error_t err = CONN.chargingError; 800bb4a: 4b4c ldr r3, [pc, #304] @ (800bc7c ) 800bb4c: 7f5b ldrb r3, [r3, #29] 800bb4e: 71bb strb r3, [r7, #6] const uint32_t now = HAL_GetTick(); 800bb50: f002 fe1a bl 800e788 800bb54: 6038 str r0, [r7, #0] if (err == CONN_NO_ERROR) { 800bb56: 79bb ldrb r3, [r7, #6] 800bb58: 2b00 cmp r3, #0 800bb5a: d118 bne.n 800bb8e err_counter = 0; 800bb5c: 4b48 ldr r3, [pc, #288] @ (800bc80 ) 800bb5e: 2200 movs r2, #0 800bb60: 701a strb r2, [r3, #0] led_state = 0; 800bb62: 4b48 ldr r3, [pc, #288] @ (800bc84 ) 800bb64: 2200 movs r2, #0 800bb66: 701a strb r2, [r3, #0] led_pause = 0; 800bb68: 4b47 ldr r3, [pc, #284] @ (800bc88 ) 800bb6a: 2200 movs r2, #0 800bb6c: 701a strb r2, [r3, #0] flash_until = 0; 800bb6e: 4b47 ldr r3, [pc, #284] @ (800bc8c ) 800bb70: 2200 movs r2, #0 800bb72: 601a str r2, [r3, #0] last_error = CONN_NO_ERROR; 800bb74: 4b46 ldr r3, [pc, #280] @ (800bc90 ) 800bb76: 2200 movs r2, #0 800bb78: 701a strb r2, [r3, #0] ws2812_led1.R = 0; 800bb7a: 4b46 ldr r3, [pc, #280] @ (800bc94 ) 800bb7c: 2200 movs r2, #0 800bb7e: 701a strb r2, [r3, #0] ws2812_led1.G = 0; 800bb80: 4b44 ldr r3, [pc, #272] @ (800bc94 ) 800bb82: 2200 movs r2, #0 800bb84: 705a strb r2, [r3, #1] ws2812_led1.B = 0; 800bb86: 4b43 ldr r3, [pc, #268] @ (800bc94 ) 800bb88: 2200 movs r2, #0 800bb8a: 709a strb r2, [r3, #2] return; 800bb8c: e072 b.n 800bc74 } if (err != last_error) { 800bb8e: 4b40 ldr r3, [pc, #256] @ (800bc90 ) 800bb90: 781b ldrb r3, [r3, #0] 800bb92: 79ba ldrb r2, [r7, #6] 800bb94: 429a cmp r2, r3 800bb96: d00e beq.n 800bbb6 err_counter = 0; 800bb98: 4b39 ldr r3, [pc, #228] @ (800bc80 ) 800bb9a: 2200 movs r2, #0 800bb9c: 701a strb r2, [r3, #0] led_state = 0; 800bb9e: 4b39 ldr r3, [pc, #228] @ (800bc84 ) 800bba0: 2200 movs r2, #0 800bba2: 701a strb r2, [r3, #0] led_pause = 0; 800bba4: 4b38 ldr r3, [pc, #224] @ (800bc88 ) 800bba6: 2200 movs r2, #0 800bba8: 701a strb r2, [r3, #0] flash_until = 0; 800bbaa: 4b38 ldr r3, [pc, #224] @ (800bc8c ) 800bbac: 2200 movs r2, #0 800bbae: 601a str r2, [r3, #0] last_error = err; 800bbb0: 4a37 ldr r2, [pc, #220] @ (800bc90 ) 800bbb2: 79bb ldrb r3, [r7, #6] 800bbb4: 7013 strb r3, [r2, #0] } if (now < flash_until) { 800bbb6: 4b35 ldr r3, [pc, #212] @ (800bc8c ) 800bbb8: 681b ldr r3, [r3, #0] 800bbba: 683a ldr r2, [r7, #0] 800bbbc: 429a cmp r2, r3 800bbbe: d209 bcs.n 800bbd4 ws2812_led1.R = 255; 800bbc0: 4b34 ldr r3, [pc, #208] @ (800bc94 ) 800bbc2: 22ff movs r2, #255 @ 0xff 800bbc4: 701a strb r2, [r3, #0] ws2812_led1.G = 0; 800bbc6: 4b33 ldr r3, [pc, #204] @ (800bc94 ) 800bbc8: 2200 movs r2, #0 800bbca: 705a strb r2, [r3, #1] ws2812_led1.B = 0; 800bbcc: 4b31 ldr r3, [pc, #196] @ (800bc94 ) 800bbce: 2200 movs r2, #0 800bbd0: 709a strb r2, [r3, #2] return; 800bbd2: e04f b.n 800bc74 } ws2812_led1.R = 0; 800bbd4: 4b2f ldr r3, [pc, #188] @ (800bc94 ) 800bbd6: 2200 movs r2, #0 800bbd8: 701a strb r2, [r3, #0] ws2812_led1.G = 0; 800bbda: 4b2e ldr r3, [pc, #184] @ (800bc94 ) 800bbdc: 2200 movs r2, #0 800bbde: 705a strb r2, [r3, #1] ws2812_led1.B = 0; 800bbe0: 4b2c ldr r3, [pc, #176] @ (800bc94 ) 800bbe2: 2200 movs r2, #0 800bbe4: 709a strb r2, [r3, #2] if ((now - blink_tick) < WS2812_ERROR_BLINK_MS) { 800bbe6: 4b2c ldr r3, [pc, #176] @ (800bc98 ) 800bbe8: 681b ldr r3, [r3, #0] 800bbea: 683a ldr r2, [r7, #0] 800bbec: 1ad3 subs r3, r2, r3 800bbee: 2b63 cmp r3, #99 @ 0x63 800bbf0: d93f bls.n 800bc72 return; } blink_tick = now; 800bbf2: 4a29 ldr r2, [pc, #164] @ (800bc98 ) 800bbf4: 683b ldr r3, [r7, #0] 800bbf6: 6013 str r3, [r2, #0] uint8_t led_flash = 0; 800bbf8: 2300 movs r3, #0 800bbfa: 71fb strb r3, [r7, #7] if (led_pause > 0) { 800bbfc: 4b22 ldr r3, [pc, #136] @ (800bc88 ) 800bbfe: 781b ldrb r3, [r3, #0] 800bc00: 2b00 cmp r3, #0 800bc02: d006 beq.n 800bc12 led_pause--; 800bc04: 4b20 ldr r3, [pc, #128] @ (800bc88 ) 800bc06: 781b ldrb r3, [r3, #0] 800bc08: 3b01 subs r3, #1 800bc0a: b2da uxtb r2, r3 800bc0c: 4b1e ldr r3, [pc, #120] @ (800bc88 ) 800bc0e: 701a strb r2, [r3, #0] 800bc10: e01e b.n 800bc50 } else if (err_counter < (uint8_t)err) { 800bc12: 4b1b ldr r3, [pc, #108] @ (800bc80 ) 800bc14: 781b ldrb r3, [r3, #0] 800bc16: 79ba ldrb r2, [r7, #6] 800bc18: 429a cmp r2, r3 800bc1a: d913 bls.n 800bc44 if (led_state == 0) { 800bc1c: 4b19 ldr r3, [pc, #100] @ (800bc84 ) 800bc1e: 781b ldrb r3, [r3, #0] 800bc20: 2b00 cmp r3, #0 800bc22: d103 bne.n 800bc2c led_state = 1; 800bc24: 4b17 ldr r3, [pc, #92] @ (800bc84 ) 800bc26: 2201 movs r2, #1 800bc28: 701a strb r2, [r3, #0] 800bc2a: e011 b.n 800bc50 } else { led_flash = 1; 800bc2c: 2301 movs r3, #1 800bc2e: 71fb strb r3, [r7, #7] led_state = 0; 800bc30: 4b14 ldr r3, [pc, #80] @ (800bc84 ) 800bc32: 2200 movs r2, #0 800bc34: 701a strb r2, [r3, #0] err_counter++; 800bc36: 4b12 ldr r3, [pc, #72] @ (800bc80 ) 800bc38: 781b ldrb r3, [r3, #0] 800bc3a: 3301 adds r3, #1 800bc3c: b2da uxtb r2, r3 800bc3e: 4b10 ldr r3, [pc, #64] @ (800bc80 ) 800bc40: 701a strb r2, [r3, #0] 800bc42: e005 b.n 800bc50 } } else { err_counter = 0; 800bc44: 4b0e ldr r3, [pc, #56] @ (800bc80 ) 800bc46: 2200 movs r2, #0 800bc48: 701a strb r2, [r3, #0] led_pause = WS2812_ERROR_BLINK_PAUSE; 800bc4a: 4b0f ldr r3, [pc, #60] @ (800bc88 ) 800bc4c: 221e movs r2, #30 800bc4e: 701a strb r2, [r3, #0] } if (led_flash) { 800bc50: 79fb ldrb r3, [r7, #7] 800bc52: 2b00 cmp r3, #0 800bc54: d00e beq.n 800bc74 flash_until = now + WS2812_ERROR_BLINK_MS; 800bc56: 683b ldr r3, [r7, #0] 800bc58: 3364 adds r3, #100 @ 0x64 800bc5a: 4a0c ldr r2, [pc, #48] @ (800bc8c ) 800bc5c: 6013 str r3, [r2, #0] ws2812_led1.R = 255; 800bc5e: 4b0d ldr r3, [pc, #52] @ (800bc94 ) 800bc60: 22ff movs r2, #255 @ 0xff 800bc62: 701a strb r2, [r3, #0] ws2812_led1.G = 0; 800bc64: 4b0b ldr r3, [pc, #44] @ (800bc94 ) 800bc66: 2200 movs r2, #0 800bc68: 705a strb r2, [r3, #1] ws2812_led1.B = 0; 800bc6a: 4b0a ldr r3, [pc, #40] @ (800bc94 ) 800bc6c: 2200 movs r2, #0 800bc6e: 709a strb r2, [r3, #2] 800bc70: e000 b.n 800bc74 return; 800bc72: bf00 nop } } 800bc74: 3708 adds r7, #8 800bc76: 46bd mov sp, r7 800bc78: bd80 pop {r7, pc} 800bc7a: bf00 nop 800bc7c: 200003b0 .word 0x200003b0 800bc80: 20000972 .word 0x20000972 800bc84: 20000973 .word 0x20000973 800bc88: 20000974 .word 0x20000974 800bc8c: 20000978 .word 0x20000978 800bc90: 2000097c .word 0x2000097c 800bc94: 2000095c .word 0x2000095c 800bc98: 20000980 .word 0x20000980 0800bc9c : void RGB_SetColor(RGB_t *color){ 800bc9c: b480 push {r7} 800bc9e: b083 sub sp, #12 800bca0: af00 add r7, sp, #0 800bca2: 6078 str r0, [r7, #4] htim4.Instance->CCR2 = color->R * 100 / 255; 800bca4: 687b ldr r3, [r7, #4] 800bca6: 781b ldrb r3, [r3, #0] 800bca8: 461a mov r2, r3 800bcaa: 2364 movs r3, #100 @ 0x64 800bcac: fb02 f303 mul.w r3, r2, r3 800bcb0: 4a17 ldr r2, [pc, #92] @ (800bd10 ) 800bcb2: fb82 1203 smull r1, r2, r2, r3 800bcb6: 441a add r2, r3 800bcb8: 11d2 asrs r2, r2, #7 800bcba: 17db asrs r3, r3, #31 800bcbc: 1ad2 subs r2, r2, r3 800bcbe: 4b15 ldr r3, [pc, #84] @ (800bd14 ) 800bcc0: 681b ldr r3, [r3, #0] 800bcc2: 639a str r2, [r3, #56] @ 0x38 htim4.Instance->CCR3 = color->G * 100 / 255; 800bcc4: 687b ldr r3, [r7, #4] 800bcc6: 785b ldrb r3, [r3, #1] 800bcc8: 461a mov r2, r3 800bcca: 2364 movs r3, #100 @ 0x64 800bccc: fb02 f303 mul.w r3, r2, r3 800bcd0: 4a0f ldr r2, [pc, #60] @ (800bd10 ) 800bcd2: fb82 1203 smull r1, r2, r2, r3 800bcd6: 441a add r2, r3 800bcd8: 11d2 asrs r2, r2, #7 800bcda: 17db asrs r3, r3, #31 800bcdc: 1ad2 subs r2, r2, r3 800bcde: 4b0d ldr r3, [pc, #52] @ (800bd14 ) 800bce0: 681b ldr r3, [r3, #0] 800bce2: 63da str r2, [r3, #60] @ 0x3c htim4.Instance->CCR4 = color->B * 100 / 255; 800bce4: 687b ldr r3, [r7, #4] 800bce6: 789b ldrb r3, [r3, #2] 800bce8: 461a mov r2, r3 800bcea: 2364 movs r3, #100 @ 0x64 800bcec: fb02 f303 mul.w r3, r2, r3 800bcf0: 4a07 ldr r2, [pc, #28] @ (800bd10 ) 800bcf2: fb82 1203 smull r1, r2, r2, r3 800bcf6: 441a add r2, r3 800bcf8: 11d2 asrs r2, r2, #7 800bcfa: 17db asrs r3, r3, #31 800bcfc: 1ad2 subs r2, r2, r3 800bcfe: 4b05 ldr r3, [pc, #20] @ (800bd14 ) 800bd00: 681b ldr r3, [r3, #0] 800bd02: 641a str r2, [r3, #64] @ 0x40 } 800bd04: bf00 nop 800bd06: 370c adds r7, #12 800bd08: 46bd mov sp, r7 800bd0a: bc80 pop {r7} 800bd0c: 4770 bx lr 800bd0e: bf00 nop 800bd10: 80808081 .word 0x80808081 800bd14: 20001224 .word 0x20001224 0800bd18 : void WS2812_SetColor(RGB_t *color){ 800bd18: b580 push {r7, lr} 800bd1a: b084 sub sp, #16 800bd1c: af00 add r7, sp, #0 800bd1e: 6078 str r0, [r7, #4] RGB_t led0 = RGB_ScaleBrightness(color); 800bd20: 6878 ldr r0, [r7, #4] 800bd22: f7ff febf bl 800baa4 800bd26: 4603 mov r3, r0 800bd28: 461a mov r2, r3 800bd2a: 733a strb r2, [r7, #12] 800bd2c: f3c3 2207 ubfx r2, r3, #8, #8 800bd30: 737a strb r2, [r7, #13] 800bd32: f3c3 4307 ubfx r3, r3, #16, #8 800bd36: 73bb strb r3, [r7, #14] RGB_t led1 = RGB_ScaleBrightness(&ws2812_led1); 800bd38: 480b ldr r0, [pc, #44] @ (800bd68 ) 800bd3a: f7ff feb3 bl 800baa4 800bd3e: 4603 mov r3, r0 800bd40: 461a mov r2, r3 800bd42: 723a strb r2, [r7, #8] 800bd44: f3c3 2207 ubfx r2, r3, #8, #8 800bd48: 727a strb r2, [r7, #9] 800bd4a: f3c3 4307 ubfx r3, r3, #16, #8 800bd4e: 72bb strb r3, [r7, #10] ws2812_update(&led0, &led1); 800bd50: f107 0208 add.w r2, r7, #8 800bd54: f107 030c add.w r3, r7, #12 800bd58: 4611 mov r1, r2 800bd5a: 4618 mov r0, r3 800bd5c: f7ff fe90 bl 800ba80 } 800bd60: bf00 nop 800bd62: 3710 adds r7, #16 800bd64: 46bd mov sp, r7 800bd66: bd80 pop {r7, pc} 800bd68: 2000095c .word 0x2000095c 0800bd6c : void LED_SetColor(RGB_Cycle_t *color){ 800bd6c: b480 push {r7} 800bd6e: b083 sub sp, #12 800bd70: af00 add r7, sp, #0 800bd72: 6078 str r0, [r7, #4] memcpy(&LED_Cycle, color, sizeof(RGB_Cycle_t)); 800bd74: 4b05 ldr r3, [pc, #20] @ (800bd8c ) 800bd76: 687a ldr r2, [r7, #4] 800bd78: 6810 ldr r0, [r2, #0] 800bd7a: 6851 ldr r1, [r2, #4] 800bd7c: c303 stmia r3!, {r0, r1} 800bd7e: 8912 ldrh r2, [r2, #8] 800bd80: 801a strh r2, [r3, #0] } 800bd82: bf00 nop 800bd84: 370c adds r7, #12 800bd86: 46bd mov sp, r7 800bd88: bc80 pop {r7} 800bd8a: 4770 bx lr 800bd8c: 20000968 .word 0x20000968 0800bd90 : void LED_Init(){ 800bd90: b580 push {r7, lr} 800bd92: b082 sub sp, #8 800bd94: af00 add r7, sp, #0 RGB_t color = {.R=0, .G=0, .B=0}; 800bd96: 2300 movs r3, #0 800bd98: 713b strb r3, [r7, #4] 800bd9a: 2300 movs r3, #0 800bd9c: 717b strb r3, [r7, #5] 800bd9e: 2300 movs r3, #0 800bda0: 71bb strb r3, [r7, #6] HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_2); 800bda2: 2104 movs r1, #4 800bda4: 480b ldr r0, [pc, #44] @ (800bdd4 ) 800bda6: f006 fbbd bl 8012524 HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); 800bdaa: 2108 movs r1, #8 800bdac: 4809 ldr r0, [pc, #36] @ (800bdd4 ) 800bdae: f006 fbb9 bl 8012524 HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4); 800bdb2: 210c movs r1, #12 800bdb4: 4807 ldr r0, [pc, #28] @ (800bdd4 ) 800bdb6: f006 fbb5 bl 8012524 RGB_SetColor(&color); 800bdba: 1d3b adds r3, r7, #4 800bdbc: 4618 mov r0, r3 800bdbe: f7ff ff6d bl 800bc9c WS2812_SetColor(&color); 800bdc2: 1d3b adds r3, r7, #4 800bdc4: 4618 mov r0, r3 800bdc6: f7ff ffa7 bl 800bd18 } 800bdca: bf00 nop 800bdcc: 3708 adds r7, #8 800bdce: 46bd mov sp, r7 800bdd0: bd80 pop {r7, pc} 800bdd2: bf00 nop 800bdd4: 20001224 .word 0x20001224 0800bdd8 : void LED_Task(){ 800bdd8: b580 push {r7, lr} 800bdda: b082 sub sp, #8 800bddc: af02 add r7, sp, #8 static uint32_t led_tick; if((HAL_GetTick() - led_tick) > 20){ 800bdde: f002 fcd3 bl 800e788 800bde2: 4602 mov r2, r0 800bde4: 4b49 ldr r3, [pc, #292] @ (800bf0c ) 800bde6: 681b ldr r3, [r3, #0] 800bde8: 1ad3 subs r3, r2, r3 800bdea: 2b14 cmp r3, #20 800bdec: f240 808a bls.w 800bf04 led_tick = HAL_GetTick(); 800bdf0: f002 fcca bl 800e788 800bdf4: 4603 mov r3, r0 800bdf6: 4a45 ldr r2, [pc, #276] @ (800bf0c ) 800bdf8: 6013 str r3, [r2, #0] LED_State.tick++; 800bdfa: 4b45 ldr r3, [pc, #276] @ (800bf10 ) 800bdfc: 885b ldrh r3, [r3, #2] 800bdfe: 3301 adds r3, #1 800be00: b29a uxth r2, r3 800be02: 4b43 ldr r3, [pc, #268] @ (800bf10 ) 800be04: 805a strh r2, [r3, #2] switch(LED_State.state){ 800be06: 4b42 ldr r3, [pc, #264] @ (800bf10 ) 800be08: 781b ldrb r3, [r3, #0] 800be0a: 2b03 cmp r3, #3 800be0c: d867 bhi.n 800bede 800be0e: a201 add r2, pc, #4 @ (adr r2, 800be14 ) 800be10: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800be14: 0800be25 .word 0x0800be25 800be18: 0800be57 .word 0x0800be57 800be1c: 0800be83 .word 0x0800be83 800be20: 0800beb5 .word 0x0800beb5 case LED_RISING: interpolateColors(&LED_Cycle.Color2, &LED_Cycle.Color1, LED_State.tick, LED_Cycle.Tr, &LED_State.color); 800be24: 4b3a ldr r3, [pc, #232] @ (800bf10 ) 800be26: 885a ldrh r2, [r3, #2] 800be28: 4b3a ldr r3, [pc, #232] @ (800bf14 ) 800be2a: 78db ldrb r3, [r3, #3] 800be2c: 4619 mov r1, r3 800be2e: 4b3a ldr r3, [pc, #232] @ (800bf18 ) 800be30: 9300 str r3, [sp, #0] 800be32: 460b mov r3, r1 800be34: 4937 ldr r1, [pc, #220] @ (800bf14 ) 800be36: 4839 ldr r0, [pc, #228] @ (800bf1c ) 800be38: f7ff fcf8 bl 800b82c if(LED_State.tick>LED_Cycle.Tr){ 800be3c: 4b34 ldr r3, [pc, #208] @ (800bf10 ) 800be3e: 885b ldrh r3, [r3, #2] 800be40: 4a34 ldr r2, [pc, #208] @ (800bf14 ) 800be42: 78d2 ldrb r2, [r2, #3] 800be44: 4293 cmp r3, r2 800be46: d94e bls.n 800bee6 LED_State.state = LED_HIGH; 800be48: 4b31 ldr r3, [pc, #196] @ (800bf10 ) 800be4a: 2201 movs r2, #1 800be4c: 701a strb r2, [r3, #0] LED_State.tick = 0; 800be4e: 4b30 ldr r3, [pc, #192] @ (800bf10 ) 800be50: 2200 movs r2, #0 800be52: 805a strh r2, [r3, #2] } break; 800be54: e047 b.n 800bee6 case LED_HIGH: memcpy(&LED_State.color, &LED_Cycle.Color1, sizeof(RGB_t)); 800be56: 4b2e ldr r3, [pc, #184] @ (800bf10 ) 800be58: 4a2e ldr r2, [pc, #184] @ (800bf14 ) 800be5a: 3304 adds r3, #4 800be5c: 6812 ldr r2, [r2, #0] 800be5e: 4611 mov r1, r2 800be60: 8019 strh r1, [r3, #0] 800be62: 3302 adds r3, #2 800be64: 0c12 lsrs r2, r2, #16 800be66: 701a strb r2, [r3, #0] if(LED_State.tick>LED_Cycle.Th){ 800be68: 4b29 ldr r3, [pc, #164] @ (800bf10 ) 800be6a: 885b ldrh r3, [r3, #2] 800be6c: 4a29 ldr r2, [pc, #164] @ (800bf14 ) 800be6e: 7912 ldrb r2, [r2, #4] 800be70: 4293 cmp r3, r2 800be72: d93a bls.n 800beea LED_State.state = LED_FALLING; 800be74: 4b26 ldr r3, [pc, #152] @ (800bf10 ) 800be76: 2202 movs r2, #2 800be78: 701a strb r2, [r3, #0] LED_State.tick = 0; 800be7a: 4b25 ldr r3, [pc, #148] @ (800bf10 ) 800be7c: 2200 movs r2, #0 800be7e: 805a strh r2, [r3, #2] } break; 800be80: e033 b.n 800beea case LED_FALLING: interpolateColors(&LED_Cycle.Color1, &LED_Cycle.Color2, LED_State.tick, LED_Cycle.Tf, &LED_State.color); 800be82: 4b23 ldr r3, [pc, #140] @ (800bf10 ) 800be84: 885a ldrh r2, [r3, #2] 800be86: 4b23 ldr r3, [pc, #140] @ (800bf14 ) 800be88: 795b ldrb r3, [r3, #5] 800be8a: 4619 mov r1, r3 800be8c: 4b22 ldr r3, [pc, #136] @ (800bf18 ) 800be8e: 9300 str r3, [sp, #0] 800be90: 460b mov r3, r1 800be92: 4922 ldr r1, [pc, #136] @ (800bf1c ) 800be94: 481f ldr r0, [pc, #124] @ (800bf14 ) 800be96: f7ff fcc9 bl 800b82c if(LED_State.tick>LED_Cycle.Tf){ 800be9a: 4b1d ldr r3, [pc, #116] @ (800bf10 ) 800be9c: 885b ldrh r3, [r3, #2] 800be9e: 4a1d ldr r2, [pc, #116] @ (800bf14 ) 800bea0: 7952 ldrb r2, [r2, #5] 800bea2: 4293 cmp r3, r2 800bea4: d923 bls.n 800beee LED_State.state = LED_LOW; 800bea6: 4b1a ldr r3, [pc, #104] @ (800bf10 ) 800bea8: 2203 movs r2, #3 800beaa: 701a strb r2, [r3, #0] LED_State.tick = 0; 800beac: 4b18 ldr r3, [pc, #96] @ (800bf10 ) 800beae: 2200 movs r2, #0 800beb0: 805a strh r2, [r3, #2] } break; 800beb2: e01c b.n 800beee case LED_LOW: memcpy(&LED_State.color, &LED_Cycle.Color2, sizeof(RGB_t)); 800beb4: 4b16 ldr r3, [pc, #88] @ (800bf10 ) 800beb6: 4a17 ldr r2, [pc, #92] @ (800bf14 ) 800beb8: 3304 adds r3, #4 800beba: 3207 adds r2, #7 800bebc: 8811 ldrh r1, [r2, #0] 800bebe: 7892 ldrb r2, [r2, #2] 800bec0: 8019 strh r1, [r3, #0] 800bec2: 709a strb r2, [r3, #2] if(LED_State.tick>LED_Cycle.Tl){ 800bec4: 4b12 ldr r3, [pc, #72] @ (800bf10 ) 800bec6: 885b ldrh r3, [r3, #2] 800bec8: 4a12 ldr r2, [pc, #72] @ (800bf14 ) 800beca: 7992 ldrb r2, [r2, #6] 800becc: 4293 cmp r3, r2 800bece: d910 bls.n 800bef2 LED_State.state = LED_RISING; 800bed0: 4b0f ldr r3, [pc, #60] @ (800bf10 ) 800bed2: 2200 movs r2, #0 800bed4: 701a strb r2, [r3, #0] LED_State.tick = 0; 800bed6: 4b0e ldr r3, [pc, #56] @ (800bf10 ) 800bed8: 2200 movs r2, #0 800beda: 805a strh r2, [r3, #2] } break; 800bedc: e009 b.n 800bef2 default: LED_State.state = LED_RISING; 800bede: 4b0c ldr r3, [pc, #48] @ (800bf10 ) 800bee0: 2200 movs r2, #0 800bee2: 701a strb r2, [r3, #0] 800bee4: e006 b.n 800bef4 break; 800bee6: bf00 nop 800bee8: e004 b.n 800bef4 break; 800beea: bf00 nop 800beec: e002 b.n 800bef4 break; 800beee: bf00 nop 800bef0: e000 b.n 800bef4 break; 800bef2: bf00 nop } LED_Ws2812ErrorBlinkUpdate(); 800bef4: f7ff fe26 bl 800bb44 RGB_SetColor(&LED_State.color); 800bef8: 4807 ldr r0, [pc, #28] @ (800bf18 ) 800befa: f7ff fecf bl 800bc9c WS2812_SetColor(&LED_State.color); 800befe: 4806 ldr r0, [pc, #24] @ (800bf18 ) 800bf00: f7ff ff0a bl 800bd18 } } 800bf04: bf00 nop 800bf06: 46bd mov sp, r7 800bf08: bd80 pop {r7, pc} 800bf0a: bf00 nop 800bf0c: 20000984 .word 0x20000984 800bf10: 20000960 .word 0x20000960 800bf14: 20000968 .word 0x20000968 800bf18: 20000964 .word 0x20000964 800bf1c: 2000096f .word 0x2000096f 0800bf20 : RTC_HandleTypeDef hrtc; /* RTC init function */ void MX_RTC_Init(void) { 800bf20: b580 push {r7, lr} 800bf22: af00 add r7, sp, #0 /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 800bf24: 4b0a ldr r3, [pc, #40] @ (800bf50 ) 800bf26: 4a0b ldr r2, [pc, #44] @ (800bf54 ) 800bf28: 601a str r2, [r3, #0] hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; 800bf2a: 4b09 ldr r3, [pc, #36] @ (800bf50 ) 800bf2c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800bf30: 605a str r2, [r3, #4] hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; 800bf32: 4b07 ldr r3, [pc, #28] @ (800bf50 ) 800bf34: f44f 7280 mov.w r2, #256 @ 0x100 800bf38: 609a str r2, [r3, #8] if (HAL_RTC_Init(&hrtc) != HAL_OK) 800bf3a: 4805 ldr r0, [pc, #20] @ (800bf50 ) 800bf3c: f006 f840 bl 8011fc0 800bf40: 4603 mov r3, r0 800bf42: 2b00 cmp r3, #0 800bf44: d001 beq.n 800bf4a { Error_Handler(); 800bf46: f7fe fec5 bl 800acd4 } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 800bf4a: bf00 nop 800bf4c: bd80 pop {r7, pc} 800bf4e: bf00 nop 800bf50: 20000988 .word 0x20000988 800bf54: 40002800 .word 0x40002800 0800bf58 : void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) { 800bf58: b580 push {r7, lr} 800bf5a: b084 sub sp, #16 800bf5c: af00 add r7, sp, #0 800bf5e: 6078 str r0, [r7, #4] if(rtcHandle->Instance==RTC) 800bf60: 687b ldr r3, [r7, #4] 800bf62: 681b ldr r3, [r3, #0] 800bf64: 4a0b ldr r2, [pc, #44] @ (800bf94 ) 800bf66: 4293 cmp r3, r2 800bf68: d110 bne.n 800bf8c { /* USER CODE BEGIN RTC_MspInit 0 */ /* USER CODE END RTC_MspInit 0 */ HAL_PWR_EnableBkUpAccess(); 800bf6a: f004 ffbd bl 8010ee8 /* Enable BKP CLK enable for backup registers */ __HAL_RCC_BKP_CLK_ENABLE(); 800bf6e: 4b0a ldr r3, [pc, #40] @ (800bf98 ) 800bf70: 69db ldr r3, [r3, #28] 800bf72: 4a09 ldr r2, [pc, #36] @ (800bf98 ) 800bf74: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800bf78: 61d3 str r3, [r2, #28] 800bf7a: 4b07 ldr r3, [pc, #28] @ (800bf98 ) 800bf7c: 69db ldr r3, [r3, #28] 800bf7e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800bf82: 60fb str r3, [r7, #12] 800bf84: 68fb ldr r3, [r7, #12] /* RTC clock enable */ __HAL_RCC_RTC_ENABLE(); 800bf86: 4b05 ldr r3, [pc, #20] @ (800bf9c ) 800bf88: 2201 movs r2, #1 800bf8a: 601a str r2, [r3, #0] /* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE END RTC_MspInit 1 */ } } 800bf8c: bf00 nop 800bf8e: 3710 adds r7, #16 800bf90: 46bd mov sp, r7 800bf92: bd80 pop {r7, pc} 800bf94: 40002800 .word 0x40002800 800bf98: 40021000 .word 0x40021000 800bf9c: 4242043c .word 0x4242043c 0800bfa0 : ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len); static void CCS_UART3_Watchdog(void); static void CCS_LogUart3Error(const char *tag); ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800bfa0: 4602 mov r2, r0 if (err == HAL_UART_ERROR_NONE) { 800bfa2: b359 cbz r1, 800bffc ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800bfa4: b570 push {r4, r5, r6, lr} 800bfa6: 460c mov r4, r1 log_printf(LOG_ERR, "UART%u HAL error decode: NONE\n", uart_num); return; } log_printf(LOG_ERR, "UART%u HAL error decode: %s%s%s%s%s%s raw=0x%08lx\n", 800bfa8: 07cb lsls r3, r1, #31 800bfaa: bf58 it pl 800bfac: 4915 ldrpl r1, [pc, #84] @ (800c004 ) 800bfae: 4d15 ldr r5, [pc, #84] @ (800c004 ) 800bfb0: bf48 it mi 800bfb2: 4914 ldrmi r1, [pc, #80] @ (800c004 ) ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800bfb4: b086 sub sp, #24 log_printf(LOG_ERR, "UART%u HAL error decode: %s%s%s%s%s%s raw=0x%08lx\n", 800bfb6: bf54 ite pl 800bfb8: 460b movpl r3, r1 800bfba: 4b13 ldrmi r3, [pc, #76] @ (800c008 ) 800bfbc: f014 0f02 tst.w r4, #2 800bfc0: 9104 str r1, [sp, #16] 800bfc2: 4912 ldr r1, [pc, #72] @ (800c00c ) 800bfc4: bf08 it eq 800bfc6: 4629 moveq r1, r5 800bfc8: f014 0f04 tst.w r4, #4 800bfcc: 4810 ldr r0, [pc, #64] @ (800c010 ) 800bfce: bf08 it eq 800bfd0: 4628 moveq r0, r5 800bfd2: f014 0f08 tst.w r4, #8 800bfd6: 9001 str r0, [sp, #4] 800bfd8: 480e ldr r0, [pc, #56] @ (800c014 ) 800bfda: 4e0f ldr r6, [pc, #60] @ (800c018 ) 800bfdc: bf08 it eq 800bfde: 462e moveq r6, r5 800bfe0: f014 0f10 tst.w r4, #16 800bfe4: bf18 it ne 800bfe6: 4605 movne r5, r0 800bfe8: 9100 str r1, [sp, #0] 800bfea: e9cd 6502 strd r6, r5, [sp, #8] 800bfee: 490b ldr r1, [pc, #44] @ (800c01c ) 800bff0: 9405 str r4, [sp, #20] 800bff2: 2004 movs r0, #4 800bff4: f7fe fab8 bl 800a568 (err & HAL_UART_ERROR_INVALID_CALLBACK) ? "INV_CB " : "", #else "", #endif (unsigned long)err); } 800bff8: b006 add sp, #24 800bffa: bd70 pop {r4, r5, r6, pc} log_printf(LOG_ERR, "UART%u HAL error decode: NONE\n", uart_num); 800bffc: 2004 movs r0, #4 800bffe: 4908 ldr r1, [pc, #32] @ (800c020 ) 800c000: f7fe bab2 b.w 800a568 800c004: 080179b0 .word 0x080179b0 800c008: 080175b8 .word 0x080175b8 800c00c: 080175bc .word 0x080175bc 800c010: 080175c0 .word 0x080175c0 800c014: 080175cc .word 0x080175cc 800c018: 080175c4 .word 0x080175c4 800c01c: 080175f4 .word 0x080175f4 800c020: 080175d4 .word 0x080175d4 0800c024 : ISR_FAST static void uart3_arm_rx_or_log(const char *where) { 800c024: b530 push {r4, r5, lr} HAL_StatusTypeDef st = HAL_UARTEx_ReceiveToIdle_DMA(&huart3, rx_buffer, sizeof(rx_buffer)); 800c026: f44f 7280 mov.w r2, #256 @ 0x100 ISR_FAST static void uart3_arm_rx_or_log(const char *where) { 800c02a: 4605 mov r5, r0 800c02c: b083 sub sp, #12 HAL_StatusTypeDef st = HAL_UARTEx_ReceiveToIdle_DMA(&huart3, rx_buffer, sizeof(rx_buffer)); 800c02e: 4911 ldr r1, [pc, #68] @ (800c074 ) 800c030: 4811 ldr r0, [pc, #68] @ (800c078 ) 800c032: f007 fa72 bl 801351a if (st == HAL_OK) { 800c036: b908 cbnz r0, 800c03c uart3_log_hal_error(3u, err_after); CCS_LogUart3Error("UART3 RX arm failed details"); if (err_after != HAL_UART_ERROR_NONE) { (void)HAL_UART_AbortReceive(&huart3); } } 800c038: b003 add sp, #12 800c03a: bd30 pop {r4, r5, pc} uint32_t err_after = HAL_UART_GetError(&huart3); 800c03c: 4604 mov r4, r0 800c03e: 480e ldr r0, [pc, #56] @ (800c078 ) 800c040: f007 fe7d bl 8013d3e 800c044: 4602 mov r2, r0 log_printf(LOG_ERR, 800c046: 4623 mov r3, r4 uint32_t err_after = HAL_UART_GetError(&huart3); 800c048: 4614 mov r4, r2 log_printf(LOG_ERR, 800c04a: 490c ldr r1, [pc, #48] @ (800c07c ) 800c04c: 462a mov r2, r5 800c04e: 2004 movs r0, #4 800c050: 9400 str r4, [sp, #0] 800c052: f7fe fa89 bl 800a568 uart3_log_hal_error(3u, err_after); 800c056: 2003 movs r0, #3 800c058: 4621 mov r1, r4 800c05a: f7ff ffa1 bl 800bfa0 CCS_LogUart3Error("UART3 RX arm failed details"); 800c05e: 4808 ldr r0, [pc, #32] @ (800c080 ) 800c060: f000 fedc bl 800ce1c if (err_after != HAL_UART_ERROR_NONE) { 800c064: 2c00 cmp r4, #0 800c066: d0e7 beq.n 800c038 (void)HAL_UART_AbortReceive(&huart3); 800c068: 4803 ldr r0, [pc, #12] @ (800c078 ) } 800c06a: b003 add sp, #12 800c06c: e8bd 4030 ldmia.w sp!, {r4, r5, lr} (void)HAL_UART_AbortReceive(&huart3); 800c070: f007 bb14 b.w 801369c 800c074: 200009c0 .word 0x200009c0 800c078: 20001344 .word 0x20001344 800c07c: 08017628 .word 0x08017628 800c080: 08017664 .word 0x08017664 0800c084 : ISR_FAST void CCS_RxEventCallback(UART_HandleTypeDef *huart, uint16_t size) { 800c084: b538 push {r3, r4, r5, lr} if (huart != &huart3) { 800c086: 4b1a ldr r3, [pc, #104] @ (800c0f0 ) ISR_FAST void CCS_RxEventCallback(UART_HandleTypeDef *huart, uint16_t size) { 800c088: 460c mov r4, r1 if (huart != &huart3) { 800c08a: 4283 cmp r3, r0 800c08c: d113 bne.n 800c0b6 log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", (unsigned)size); return; } if (size == 0u) { 800c08e: b329 cbz r1, 800c0dc log_printf(LOG_WARN, "UART3 RX drop: RxEvent size=0 (idle, no payload)\n"); uart3_arm_rx_or_log("RxEventCallback"); return; } if (size > sizeof(rx_buffer)) { 800c090: f5b1 7f80 cmp.w r1, #256 @ 0x100 800c094: d816 bhi.n 800c0c4 log_printf(LOG_ERR, "UART3 RX drop: size=%u > rx_buffer %u (overflow, not parsed)\n", (unsigned)size, (unsigned)sizeof(rx_buffer)); uart3_arm_rx_or_log("RxEventCallback"); return; } uart3_last_packet_tick = HAL_GetTick(); 800c096: f002 fb77 bl 800e788 800c09a: 4603 mov r3, r0 800c09c: 4d15 ldr r5, [pc, #84] @ (800c0f4 ) uart3_last_reinit_tick = uart3_last_packet_tick; 800c09e: 4a16 ldr r2, [pc, #88] @ (800c0f8 ) process_received_packet(rx_buffer, size); 800c0a0: 4621 mov r1, r4 800c0a2: 4816 ldr r0, [pc, #88] @ (800c0fc ) uart3_last_packet_tick = HAL_GetTick(); 800c0a4: 602b str r3, [r5, #0] uart3_last_reinit_tick = uart3_last_packet_tick; 800c0a6: 6013 str r3, [r2, #0] process_received_packet(rx_buffer, size); 800c0a8: f000 fe10 bl 800cccc uart3_arm_rx_or_log("RxEventCallback"); } 800c0ac: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800c0b0: 4813 ldr r0, [pc, #76] @ (800c100 ) 800c0b2: f7ff bfb7 b.w 800c024 log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", 800c0b6: 460a mov r2, r1 } 800c0b8: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", 800c0bc: 2005 movs r0, #5 800c0be: 4911 ldr r1, [pc, #68] @ (800c104 ) 800c0c0: f7fe ba52 b.w 800a568 log_printf(LOG_ERR, "UART3 RX drop: size=%u > rx_buffer %u (overflow, not parsed)\n", 800c0c4: f44f 7380 mov.w r3, #256 @ 0x100 800c0c8: 460a mov r2, r1 800c0ca: 2004 movs r0, #4 800c0cc: 490e ldr r1, [pc, #56] @ (800c108 ) 800c0ce: f7fe fa4b bl 800a568 } 800c0d2: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800c0d6: 480a ldr r0, [pc, #40] @ (800c100 ) 800c0d8: f7ff bfa4 b.w 800c024 log_printf(LOG_WARN, "UART3 RX drop: RxEvent size=0 (idle, no payload)\n"); 800c0dc: 2005 movs r0, #5 800c0de: 490b ldr r1, [pc, #44] @ (800c10c ) 800c0e0: f7fe fa42 bl 800a568 } 800c0e4: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800c0e8: 4805 ldr r0, [pc, #20] @ (800c100 ) 800c0ea: f7ff bf9b b.w 800c024 800c0ee: bf00 nop 800c0f0: 20001344 .word 0x20001344 800c0f4: 20000cd0 .word 0x20000cd0 800c0f8: 20000cd4 .word 0x20000cd4 800c0fc: 200009c0 .word 0x200009c0 800c100: 080176f0 .word 0x080176f0 800c104: 08017680 .word 0x08017680 800c108: 08017700 .word 0x08017700 800c10c: 080176bc .word 0x080176bc 0800c110 : ISR_FAST void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 800c110: b5f8 push {r3, r4, r5, r6, r7, lr} 800c112: 4604 mov r4, r0 uint32_t error = HAL_UART_GetError(huart); 800c114: f007 fe13 bl 8013d3e uint8_t uart_num = 800c118: 4b29 ldr r3, [pc, #164] @ (800c1c0 ) uint32_t error = HAL_UART_GetError(huart); 800c11a: 4605 mov r5, r0 uint8_t uart_num = 800c11c: 429c cmp r4, r3 800c11e: d032 beq.n 800c186 800c120: 4e28 ldr r6, [pc, #160] @ (800c1c4 ) 800c122: 42b4 cmp r4, r6 800c124: d017 beq.n 800c156 800c126: 4b28 ldr r3, [pc, #160] @ (800c1c8 ) 800c128: 429c cmp r4, r3 800c12a: d045 beq.n 800c1b8 (huart == &huart2) ? 2 : (huart == &huart3) ? 3 : (huart == &huart5) ? 5 : 0; log_printf(LOG_ERR, 800c12c: 4603 mov r3, r0 800c12e: 2200 movs r2, #0 800c130: 4926 ldr r1, [pc, #152] @ (800c1cc ) 800c132: 2004 movs r0, #4 800c134: f7fe fa18 bl 800a568 "UART%u HAL error (ISR): raw=0x%08lx — RX may be corrupted until re-arm\n", uart_num, (unsigned long)error); uart3_log_hal_error(uart_num, error); 800c138: 4629 mov r1, r5 800c13a: 2000 movs r0, #0 800c13c: f7ff ff30 bl 800bfa0 (void)HAL_UART_AbortReceive(huart); 800c140: 4620 mov r0, r4 800c142: f007 faab bl 801369c (void)HAL_UART_AbortTransmit(huart); 800c146: 4620 mov r0, r4 800c148: f007 fa40 bl 80135cc if (huart == &huart3) { uart3_tx_busy = 0; uart3_arm_rx_or_log("ErrorCallback"); } else { SC_RecoverUartDma(huart); 800c14c: 4620 mov r0, r4 } } 800c14e: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} SC_RecoverUartDma(huart); 800c152: f001 b91f b.w 800d394 log_printf(LOG_ERR, 800c156: 4603 mov r3, r0 800c158: 2203 movs r2, #3 800c15a: 491c ldr r1, [pc, #112] @ (800c1cc ) 800c15c: 2004 movs r0, #4 800c15e: f7fe fa03 bl 800a568 uart3_log_hal_error(uart_num, error); 800c162: 4629 mov r1, r5 800c164: 2003 movs r0, #3 800c166: f7ff ff1b bl 800bfa0 (void)HAL_UART_AbortReceive(huart); 800c16a: 4620 mov r0, r4 800c16c: f007 fa96 bl 801369c (void)HAL_UART_AbortTransmit(huart); 800c170: 4620 mov r0, r4 800c172: f007 fa2b bl 80135cc uart3_tx_busy = 0; 800c176: 2200 movs r2, #0 800c178: 4b15 ldr r3, [pc, #84] @ (800c1d0 ) uart3_arm_rx_or_log("ErrorCallback"); 800c17a: 4816 ldr r0, [pc, #88] @ (800c1d4 ) uart3_tx_busy = 0; 800c17c: 701a strb r2, [r3, #0] } 800c17e: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} uart3_arm_rx_or_log("ErrorCallback"); 800c182: f7ff bf4f b.w 800c024 800c186: 2202 movs r2, #2 uint8_t uart_num = 800c188: 4617 mov r7, r2 800c18a: 4e0e ldr r6, [pc, #56] @ (800c1c4 ) log_printf(LOG_ERR, 800c18c: 462b mov r3, r5 800c18e: 490f ldr r1, [pc, #60] @ (800c1cc ) 800c190: 2004 movs r0, #4 800c192: f7fe f9e9 bl 800a568 uart3_log_hal_error(uart_num, error); 800c196: 4629 mov r1, r5 800c198: 4638 mov r0, r7 800c19a: f7ff ff01 bl 800bfa0 (void)HAL_UART_AbortReceive(huart); 800c19e: 4620 mov r0, r4 800c1a0: f007 fa7c bl 801369c (void)HAL_UART_AbortTransmit(huart); 800c1a4: 4620 mov r0, r4 800c1a6: f007 fa11 bl 80135cc if (huart == &huart3) { 800c1aa: 42b4 cmp r4, r6 800c1ac: d0e3 beq.n 800c176 SC_RecoverUartDma(huart); 800c1ae: 4620 mov r0, r4 } 800c1b0: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} SC_RecoverUartDma(huart); 800c1b4: f001 b8ee b.w 800d394 800c1b8: 2205 movs r2, #5 uint8_t uart_num = 800c1ba: 4617 mov r7, r2 800c1bc: e7e6 b.n 800c18c 800c1be: bf00 nop 800c1c0: 200012fc .word 0x200012fc 800c1c4: 20001344 .word 0x20001344 800c1c8: 2000126c .word 0x2000126c 800c1cc: 08017740 .word 0x08017740 800c1d0: 20000cc2 .word 0x20000cc2 800c1d4: 0801778c .word 0x0801778c 0800c1d8 : void CCS_TxCpltCallback(UART_HandleTypeDef *huart) { 800c1d8: b580 push {r7, lr} 800c1da: b082 sub sp, #8 800c1dc: af00 add r7, sp, #0 800c1de: 6078 str r0, [r7, #4] if (huart != &huart3) { 800c1e0: 687b ldr r3, [r7, #4] 800c1e2: 4a16 ldr r2, [pc, #88] @ (800c23c ) 800c1e4: 4293 cmp r3, r2 800c1e6: d124 bne.n 800c232 return; } uart3_tx_busy = 0; 800c1e8: 4b15 ldr r3, [pc, #84] @ (800c240 ) 800c1ea: 2200 movs r2, #0 800c1ec: 701a strb r2, [r3, #0] if (tx_pending_len > 0) { 800c1ee: 4b15 ldr r3, [pc, #84] @ (800c244 ) 800c1f0: 881b ldrh r3, [r3, #0] 800c1f2: 2b00 cmp r3, #0 800c1f4: d01e beq.n 800c234 memcpy(tx_buffer, tx_pending_buffer, tx_pending_len); 800c1f6: 4b13 ldr r3, [pc, #76] @ (800c244 ) 800c1f8: 881b ldrh r3, [r3, #0] 800c1fa: 461a mov r2, r3 800c1fc: 4912 ldr r1, [pc, #72] @ (800c248 ) 800c1fe: 4813 ldr r0, [pc, #76] @ (800c24c ) 800c200: f008 ffc4 bl 801518c uart3_tx_busy = 1; 800c204: 4b0e ldr r3, [pc, #56] @ (800c240 ) 800c206: 2201 movs r2, #1 800c208: 701a strb r2, [r3, #0] if (HAL_UART_Transmit_DMA(&huart3, tx_buffer, tx_pending_len) != HAL_OK) { 800c20a: 4b0e ldr r3, [pc, #56] @ (800c244 ) 800c20c: 881b ldrh r3, [r3, #0] 800c20e: 461a mov r2, r3 800c210: 490e ldr r1, [pc, #56] @ (800c24c ) 800c212: 480a ldr r0, [pc, #40] @ (800c23c ) 800c214: f007 f8b4 bl 8013380 800c218: 4603 mov r3, r0 800c21a: 2b00 cmp r3, #0 800c21c: d005 beq.n 800c22a uart3_tx_busy = 0; 800c21e: 4b08 ldr r3, [pc, #32] @ (800c240 ) 800c220: 2200 movs r2, #0 800c222: 701a strb r2, [r3, #0] CCS_LogUart3Error("UART3 TX DMA resend failed"); 800c224: 480a ldr r0, [pc, #40] @ (800c250 ) 800c226: f000 fdf9 bl 800ce1c } tx_pending_len = 0; 800c22a: 4b06 ldr r3, [pc, #24] @ (800c244 ) 800c22c: 2200 movs r2, #0 800c22e: 801a strh r2, [r3, #0] 800c230: e000 b.n 800c234 return; 800c232: bf00 nop } } 800c234: 3708 adds r7, #8 800c236: 46bd mov sp, r7 800c238: bd80 pop {r7, pc} 800c23a: bf00 nop 800c23c: 20001344 .word 0x20001344 800c240: 20000cc2 .word 0x20000cc2 800c244: 20000cc0 .word 0x20000cc0 800c248: 20000bc0 .word 0x20000bc0 800c24c: 20000ac0 .word 0x20000ac0 800c250: 0801779c .word 0x0801779c 0800c254 : void CCS_SerialLoop(void) { 800c254: b580 push {r7, lr} 800c256: b082 sub sp, #8 800c258: af00 add r7, sp, #0 static uint32_t tick; if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800c25a: f002 fa95 bl 800e788 800c25e: 4602 mov r2, r0 800c260: 4ba5 ldr r3, [pc, #660] @ (800c4f8 ) 800c262: 681b ldr r3, [r3, #0] 800c264: 1ad3 subs r3, r2, r3 800c266: 2b00 cmp r3, #0 800c268: f340 826b ble.w 800c742 tick = HAL_GetTick(); 800c26c: f002 fa8c bl 800e788 800c270: 4603 mov r3, r0 800c272: 4aa1 ldr r2, [pc, #644] @ (800c4f8 ) 800c274: 6013 str r3, [r2, #0] static uint32_t replug_watchdog1_tick = 0; static uint32_t last_state_sent = 0; static uint32_t force_unlock_tick = 0; static uint32_t stop_tick = 0; CCS_UART3_Watchdog(); 800c276: f000 fd97 bl 800cda8 if (CONN.connControl != CMD_NONE) { 800c27a: 4ba0 ldr r3, [pc, #640] @ (800c4fc ) 800c27c: 781b ldrb r3, [r3, #0] 800c27e: 2b00 cmp r3, #0 800c280: d003 beq.n 800c28a last_cmd = CONN.connControl; 800c282: 4b9e ldr r3, [pc, #632] @ (800c4fc ) 800c284: 781a ldrb r2, [r3, #0] 800c286: 4b9e ldr r3, [pc, #632] @ (800c500 ) 800c288: 701a strb r2, [r3, #0] } if (CONN.connControl == CMD_FORCE_UNLOCK) { 800c28a: 4b9c ldr r3, [pc, #624] @ (800c4fc ) 800c28c: 781b ldrb r3, [r3, #0] 800c28e: 2b03 cmp r3, #3 800c290: d11b bne.n 800c2ca if (force_unlock_tick == 0) { 800c292: 4b9c ldr r3, [pc, #624] @ (800c504 ) 800c294: 681b ldr r3, [r3, #0] 800c296: 2b00 cmp r3, #0 800c298: d105 bne.n 800c2a6 force_unlock_tick = HAL_GetTick(); 800c29a: f002 fa75 bl 800e788 800c29e: 4603 mov r3, r0 800c2a0: 4a98 ldr r2, [pc, #608] @ (800c504 ) 800c2a2: 6013 str r3, [r2, #0] 800c2a4: e014 b.n 800c2d0 } else if ((int32_t)(HAL_GetTick() - force_unlock_tick) >= 10000) { 800c2a6: f002 fa6f bl 800e788 800c2aa: 4602 mov r2, r0 800c2ac: 4b95 ldr r3, [pc, #596] @ (800c504 ) 800c2ae: 681b ldr r3, [r3, #0] 800c2b0: 1ad3 subs r3, r2, r3 800c2b2: 461a mov r2, r3 800c2b4: f242 730f movw r3, #9999 @ 0x270f 800c2b8: 429a cmp r2, r3 800c2ba: dd09 ble.n 800c2d0 CONN.connControl = CMD_NONE; 800c2bc: 4b8f ldr r3, [pc, #572] @ (800c4fc ) 800c2be: 2200 movs r2, #0 800c2c0: 701a strb r2, [r3, #0] force_unlock_tick = 0; 800c2c2: 4b90 ldr r3, [pc, #576] @ (800c504 ) 800c2c4: 2200 movs r2, #0 800c2c6: 601a str r2, [r3, #0] 800c2c8: e002 b.n 800c2d0 } } else { force_unlock_tick = 0; 800c2ca: 4b8e ldr r3, [pc, #568] @ (800c504 ) 800c2cc: 2200 movs r2, #0 800c2ce: 601a str r2, [r3, #0] } if (CONN.connControl == CMD_STOP) { 800c2d0: 4b8a ldr r3, [pc, #552] @ (800c4fc ) 800c2d2: 781b ldrb r3, [r3, #0] 800c2d4: 2b01 cmp r3, #1 800c2d6: d119 bne.n 800c30c if (stop_tick == 0) { 800c2d8: 4b8b ldr r3, [pc, #556] @ (800c508 ) 800c2da: 681b ldr r3, [r3, #0] 800c2dc: 2b00 cmp r3, #0 800c2de: d105 bne.n 800c2ec stop_tick = HAL_GetTick(); 800c2e0: f002 fa52 bl 800e788 800c2e4: 4603 mov r3, r0 800c2e6: 4a88 ldr r2, [pc, #544] @ (800c508 ) 800c2e8: 6013 str r3, [r2, #0] 800c2ea: e012 b.n 800c312 } else if ((int32_t)(HAL_GetTick() - stop_tick) >= 1000) { 800c2ec: f002 fa4c bl 800e788 800c2f0: 4602 mov r2, r0 800c2f2: 4b85 ldr r3, [pc, #532] @ (800c508 ) 800c2f4: 681b ldr r3, [r3, #0] 800c2f6: 1ad3 subs r3, r2, r3 800c2f8: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800c2fc: db09 blt.n 800c312 CONN.connControl = CMD_NONE; 800c2fe: 4b7f ldr r3, [pc, #508] @ (800c4fc ) 800c300: 2200 movs r2, #0 800c302: 701a strb r2, [r3, #0] stop_tick = 0; 800c304: 4b80 ldr r3, [pc, #512] @ (800c508 ) 800c306: 2200 movs r2, #0 800c308: 601a str r2, [r3, #0] 800c30a: e002 b.n 800c312 } } else { stop_tick = 0; 800c30c: 4b7e ldr r3, [pc, #504] @ (800c508 ) 800c30e: 2200 movs r2, #0 800c310: 601a str r2, [r3, #0] } if((int32_t)(HAL_GetTick() - last_cmd_sent) > (int32_t)CMD_INTERVAL){ 800c312: f002 fa39 bl 800e788 800c316: 4602 mov r2, r0 800c318: 4b7c ldr r3, [pc, #496] @ (800c50c ) 800c31a: 681b ldr r3, [r3, #0] 800c31c: 1ad3 subs r3, r2, r3 800c31e: 2b0a cmp r3, #10 800c320: dd5e ble.n 800c3e0 if ((int32_t)(HAL_GetTick() - last_state_sent) >= 200) { 800c322: f002 fa31 bl 800e788 800c326: 4602 mov r2, r0 800c328: 4b79 ldr r3, [pc, #484] @ (800c510 ) 800c32a: 681b ldr r3, [r3, #0] 800c32c: 1ad3 subs r3, r2, r3 800c32e: 2bc7 cmp r3, #199 @ 0xc7 800c330: dd06 ble.n 800c340 send_state(); 800c332: f000 fb9b bl 800ca6c last_state_sent = HAL_GetTick(); 800c336: f002 fa27 bl 800e788 800c33a: 4603 mov r3, r0 800c33c: 4a74 ldr r2, [pc, #464] @ (800c510 ) 800c33e: 6013 str r3, [r2, #0] } if (ESTOP) { 800c340: 4b74 ldr r3, [pc, #464] @ (800c514 ) 800c342: 781b ldrb r3, [r3, #0] 800c344: 2b00 cmp r3, #0 800c346: d008 beq.n 800c35a log_printf(LOG_ERR, "ESTOP triggered\n"); 800c348: 4973 ldr r1, [pc, #460] @ (800c518 ) 800c34a: 2004 movs r0, #4 800c34c: f7fe f90c bl 800a568 CCS_SendEmergencyStop(); 800c350: f000 fb2c bl 800c9ac ESTOP = 0; 800c354: 4b6f ldr r3, [pc, #444] @ (800c514 ) 800c356: 2200 movs r2, #0 800c358: 701a strb r2, [r3, #0] } if (((CONN.connControl == CMD_STOP) || 800c35a: 4b68 ldr r3, [pc, #416] @ (800c4fc ) 800c35c: 781b ldrb r3, [r3, #0] 800c35e: 2b01 cmp r3, #1 800c360: d007 beq.n 800c372 (CONN.connControl == CMD_FORCE_UNLOCK) || 800c362: 4b66 ldr r3, [pc, #408] @ (800c4fc ) 800c364: 781b ldrb r3, [r3, #0] if (((CONN.connControl == CMD_STOP) || 800c366: 2b03 cmp r3, #3 800c368: d003 beq.n 800c372 (CONN.chargingError != CONN_NO_ERROR)) && 800c36a: 4b64 ldr r3, [pc, #400] @ (800c4fc ) 800c36c: 7f5b ldrb r3, [r3, #29] (CONN.connControl == CMD_FORCE_UNLOCK) || 800c36e: 2b00 cmp r3, #0 800c370: d01a beq.n 800c3a8 ((int32_t)(HAL_GetTick() - last_stop_sent) > 1000)) { 800c372: f002 fa09 bl 800e788 800c376: 4602 mov r2, r0 800c378: 4b68 ldr r3, [pc, #416] @ (800c51c ) 800c37a: 681b ldr r3, [r3, #0] 800c37c: 1ad3 subs r3, r2, r3 (CONN.chargingError != CONN_NO_ERROR)) && 800c37e: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800c382: dd11 ble.n 800c3a8 last_stop_sent = HAL_GetTick(); 800c384: f002 fa00 bl 800e788 800c388: 4603 mov r3, r0 800c38a: 4a64 ldr r2, [pc, #400] @ (800c51c ) 800c38c: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "Stopping charging...\n"); 800c38e: 4964 ldr r1, [pc, #400] @ (800c520 ) 800c390: 2005 movs r0, #5 800c392: f7fe f8e9 bl 800a568 if (CONN.connControl == CMD_FORCE_UNLOCK) { 800c396: 4b59 ldr r3, [pc, #356] @ (800c4fc ) 800c398: 781b ldrb r3, [r3, #0] 800c39a: 2b03 cmp r3, #3 800c39c: d102 bne.n 800c3a4 CP_SetDuty(100); 800c39e: 2064 movs r0, #100 @ 0x64 800c3a0: f7fd fea0 bl 800a0e4 } CCS_SendEmergencyStop(); 800c3a4: f000 fb02 bl 800c9ac } if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800c3a8: 4b5e ldr r3, [pc, #376] @ (800c524 ) 800c3aa: 781b ldrb r3, [r3, #0] 800c3ac: 2b0c cmp r3, #12 800c3ae: d003 beq.n 800c3b8 800c3b0: 4b5c ldr r3, [pc, #368] @ (800c524 ) 800c3b2: 781b ldrb r3, [r3, #0] 800c3b4: 2b0b cmp r3, #11 800c3b6: d113 bne.n 800c3e0 ((int32_t)(HAL_GetTick() - last_stop_sent) > 1000)) { 800c3b8: f002 f9e6 bl 800e788 800c3bc: 4602 mov r2, r0 800c3be: 4b57 ldr r3, [pc, #348] @ (800c51c ) 800c3c0: 681b ldr r3, [r3, #0] 800c3c2: 1ad3 subs r3, r2, r3 if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800c3c4: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800c3c8: dd0a ble.n 800c3e0 last_stop_sent = HAL_GetTick(); 800c3ca: f002 f9dd bl 800e788 800c3ce: 4603 mov r3, r0 800c3d0: 4a52 ldr r2, [pc, #328] @ (800c51c ) 800c3d2: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "FinishedEV, stopping...\n"); 800c3d4: 4954 ldr r1, [pc, #336] @ (800c528 ) 800c3d6: 2005 movs r0, #5 800c3d8: f7fe f8c6 bl 800a568 CCS_SendEmergencyStop(); 800c3dc: f000 fae6 bl 800c9ac } (void)replug_watchdog_tick; (void)replug_watchdog1_tick; uint8_t host_timeout_warn = (last_host_seen > 0u) && ((int32_t)(HAL_GetTick() - last_host_seen) > (int32_t)EVEREST_TIMEOUT_WARN_MS); 800c3e0: 4b52 ldr r3, [pc, #328] @ (800c52c ) 800c3e2: 681b ldr r3, [r3, #0] 800c3e4: 2b00 cmp r3, #0 800c3e6: d00c beq.n 800c402 800c3e8: f002 f9ce bl 800e788 800c3ec: 4602 mov r2, r0 800c3ee: 4b4f ldr r3, [pc, #316] @ (800c52c ) 800c3f0: 681b ldr r3, [r3, #0] 800c3f2: 1ad3 subs r3, r2, r3 800c3f4: 461a mov r2, r3 800c3f6: f241 3388 movw r3, #5000 @ 0x1388 800c3fa: 429a cmp r2, r3 800c3fc: dd01 ble.n 800c402 800c3fe: 2301 movs r3, #1 800c400: e000 b.n 800c404 800c402: 2300 movs r3, #0 800c404: 71fb strb r3, [r7, #7] uint8_t host_timeout_stop = (last_host_seen > 0u) && ((int32_t)(HAL_GetTick() - last_host_seen) > (int32_t)EVEREST_TIMEOUT_STOP_MS); 800c406: 4b49 ldr r3, [pc, #292] @ (800c52c ) 800c408: 681b ldr r3, [r3, #0] 800c40a: 2b00 cmp r3, #0 800c40c: d00c beq.n 800c428 800c40e: f002 f9bb bl 800e788 800c412: 4602 mov r2, r0 800c414: 4b45 ldr r3, [pc, #276] @ (800c52c ) 800c416: 681b ldr r3, [r3, #0] 800c418: 1ad3 subs r3, r2, r3 800c41a: 461a mov r2, r3 800c41c: f242 7310 movw r3, #10000 @ 0x2710 800c420: 429a cmp r2, r3 800c422: dd01 ble.n 800c428 800c424: 2301 movs r3, #1 800c426: e000 b.n 800c42a 800c428: 2300 movs r3, #0 800c42a: 71bb strb r3, [r7, #6] uint8_t host_timed_out = host_timeout_stop; 800c42c: 79bb ldrb r3, [r7, #6] 800c42e: 717b strb r3, [r7, #5] if (host_timeout_warn && !everest_timeout_warn_latched) { 800c430: 79fb ldrb r3, [r7, #7] 800c432: 2b00 cmp r3, #0 800c434: d00a beq.n 800c44c 800c436: 4b3e ldr r3, [pc, #248] @ (800c530 ) 800c438: 781b ldrb r3, [r3, #0] 800c43a: 2b00 cmp r3, #0 800c43c: d106 bne.n 800c44c log_printf(LOG_ERR, "Everest timeout\n"); 800c43e: 493d ldr r1, [pc, #244] @ (800c534 ) 800c440: 2004 movs r0, #4 800c442: f7fe f891 bl 800a568 everest_timeout_warn_latched = 1; 800c446: 4b3a ldr r3, [pc, #232] @ (800c530 ) 800c448: 2201 movs r2, #1 800c44a: 701a strb r2, [r3, #0] } if (host_timeout_stop && !everest_timeout_stop_latched) { 800c44c: 79bb ldrb r3, [r7, #6] 800c44e: 2b00 cmp r3, #0 800c450: d00a beq.n 800c468 800c452: 4b39 ldr r3, [pc, #228] @ (800c538 ) 800c454: 781b ldrb r3, [r3, #0] 800c456: 2b00 cmp r3, #0 800c458: d106 bne.n 800c468 log_printf(LOG_ERR, "Everest timeout, stopping charging...\n"); 800c45a: 4938 ldr r1, [pc, #224] @ (800c53c ) 800c45c: 2004 movs r0, #4 800c45e: f7fe f883 bl 800a568 everest_timeout_stop_latched = 1; 800c462: 4b35 ldr r3, [pc, #212] @ (800c538 ) 800c464: 2201 movs r2, #1 800c466: 701a strb r2, [r3, #0] } if (!host_timeout_warn) { 800c468: 79fb ldrb r3, [r7, #7] 800c46a: 2b00 cmp r3, #0 800c46c: d105 bne.n 800c47a everest_timeout_warn_latched = 0; 800c46e: 4b30 ldr r3, [pc, #192] @ (800c530 ) 800c470: 2200 movs r2, #0 800c472: 701a strb r2, [r3, #0] everest_timeout_stop_latched = 0; 800c474: 4b30 ldr r3, [pc, #192] @ (800c538 ) 800c476: 2200 movs r2, #0 800c478: 701a strb r2, [r3, #0] } everest_timed_out = host_timeout_stop; 800c47a: 4a31 ldr r2, [pc, #196] @ (800c540 ) 800c47c: 79bb ldrb r3, [r7, #6] 800c47e: 7013 strb r3, [r2, #0] switch(CCS_ConnectorState){ 800c480: 4b30 ldr r3, [pc, #192] @ (800c544 ) 800c482: 781b ldrb r3, [r3, #0] 800c484: 2b05 cmp r3, #5 800c486: f200 8113 bhi.w 800c6b0 800c48a: a201 add r2, pc, #4 @ (adr r2, 800c490 ) 800c48c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c490: 0800c4a9 .word 0x0800c4a9 800c494: 0800c4d1 .word 0x0800c4d1 800c498: 0800c54d .word 0x0800c54d 800c49c: 0800c591 .word 0x0800c591 800c4a0: 0800c5cd .word 0x0800c5cd 800c4a4: 0800c625 .word 0x0800c625 case CCS_UNKNOWN: RELAY_Write(RELAY_CP, 0); 800c4a8: 2100 movs r1, #0 800c4aa: 2005 movs r0, #5 800c4ac: f7fd f984 bl 80097b8 CONN_SetState(Unknown); 800c4b0: 2000 movs r0, #0 800c4b2: f7fd fd1f bl 8009ef4 if (config_initialized && !host_timed_out) { 800c4b6: 4b24 ldr r3, [pc, #144] @ (800c548 ) 800c4b8: 781b ldrb r3, [r3, #0] 800c4ba: 2b00 cmp r3, #0 800c4bc: f000 80ed beq.w 800c69a 800c4c0: 797b ldrb r3, [r7, #5] 800c4c2: 2b00 cmp r3, #0 800c4c4: f040 80e9 bne.w 800c69a CCS_ConnectorState = CCS_UNPLUGGED; 800c4c8: 4b1e ldr r3, [pc, #120] @ (800c544 ) 800c4ca: 2202 movs r2, #2 800c4cc: 701a strb r2, [r3, #0] } break; 800c4ce: e0e4 b.n 800c69a case CCS_DISABLED: RELAY_Write(RELAY_CP, 0); 800c4d0: 2100 movs r1, #0 800c4d2: 2005 movs r0, #5 800c4d4: f7fd f970 bl 80097b8 CONN_SetState(Disabled); 800c4d8: 2002 movs r0, #2 800c4da: f7fd fd0b bl 8009ef4 if ((CONN.chargingError == CONN_NO_ERROR) && !host_timed_out){ 800c4de: 4b07 ldr r3, [pc, #28] @ (800c4fc ) 800c4e0: 7f5b ldrb r3, [r3, #29] 800c4e2: 2b00 cmp r3, #0 800c4e4: f040 80db bne.w 800c69e 800c4e8: 797b ldrb r3, [r7, #5] 800c4ea: 2b00 cmp r3, #0 800c4ec: f040 80d7 bne.w 800c69e CCS_ConnectorState = CCS_UNPLUGGED; 800c4f0: 4b14 ldr r3, [pc, #80] @ (800c544 ) 800c4f2: 2202 movs r2, #2 800c4f4: 701a strb r2, [r3, #0] } break; 800c4f6: e0d2 b.n 800c69e 800c4f8: 20000d28 .word 0x20000d28 800c4fc: 200003b0 .word 0x200003b0 800c500: 200009bc .word 0x200009bc 800c504: 20000d2c .word 0x20000d2c 800c508: 20000d30 .word 0x20000d30 800c50c: 200009b4 .word 0x200009b4 800c510: 20000d34 .word 0x20000d34 800c514: 20000cc3 .word 0x20000cc3 800c518: 080177b8 .word 0x080177b8 800c51c: 200009b8 .word 0x200009b8 800c520: 080177cc .word 0x080177cc 800c524: 20000d24 .word 0x20000d24 800c528: 080177e4 .word 0x080177e4 800c52c: 20000cc8 .word 0x20000cc8 800c530: 20000cce .word 0x20000cce 800c534: 08017800 .word 0x08017800 800c538: 20000ccf .word 0x20000ccf 800c53c: 08017814 .word 0x08017814 800c540: 20000ccd .word 0x20000ccd 800c544: 20000d25 .word 0x20000d25 800c548: 200011d4 .word 0x200011d4 case CCS_UNPLUGGED: RELAY_Write(RELAY_CP, 1); 800c54c: 2101 movs r1, #1 800c54e: 2005 movs r0, #5 800c550: f7fd f932 bl 80097b8 CONN_SetState(Unplugged); 800c554: 2001 movs r0, #1 800c556: f7fd fccd bl 8009ef4 if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || (cp_state_buffer == EV_STATE_C_CONN_ACTIVE)){ 800c55a: 4b7c ldr r3, [pc, #496] @ (800c74c ) 800c55c: 781b ldrb r3, [r3, #0] 800c55e: 2b01 cmp r3, #1 800c560: d003 beq.n 800c56a 800c562: 4b7a ldr r3, [pc, #488] @ (800c74c ) 800c564: 781b ldrb r3, [r3, #0] 800c566: 2b02 cmp r3, #2 800c568: d102 bne.n 800c570 CCS_ConnectorState = CCS_AUTH_REQUIRED; 800c56a: 4b79 ldr r3, [pc, #484] @ (800c750 ) 800c56c: 2203 movs r2, #3 800c56e: 701a strb r2, [r3, #0] } if (CONN.chargingError != CONN_NO_ERROR){ 800c570: 4b78 ldr r3, [pc, #480] @ (800c754 ) 800c572: 7f5b ldrb r3, [r3, #29] 800c574: 2b00 cmp r3, #0 800c576: f000 8094 beq.w 800c6a2 log_printf(LOG_ERR, "Charging error %d, state -> disabled\n", CONN.chargingError); 800c57a: 4b76 ldr r3, [pc, #472] @ (800c754 ) 800c57c: 7f5b ldrb r3, [r3, #29] 800c57e: 461a mov r2, r3 800c580: 4975 ldr r1, [pc, #468] @ (800c758 ) 800c582: 2004 movs r0, #4 800c584: f7fd fff0 bl 800a568 CCS_ConnectorState = CCS_DISABLED; 800c588: 4b71 ldr r3, [pc, #452] @ (800c750 ) 800c58a: 2201 movs r2, #1 800c58c: 701a strb r2, [r3, #0] } break; 800c58e: e088 b.n 800c6a2 case CCS_AUTH_REQUIRED: RELAY_Write(RELAY_CP, 1); 800c590: 2101 movs r1, #1 800c592: 2005 movs r0, #5 800c594: f7fd f910 bl 80097b8 CONN_SetState(AuthRequired); 800c598: 2004 movs r0, #4 800c59a: f7fd fcab bl 8009ef4 if(CONN.connControl == CMD_START){ 800c59e: 4b6d ldr r3, [pc, #436] @ (800c754 ) 800c5a0: 781b ldrb r3, [r3, #0] 800c5a2: 2b02 cmp r3, #2 800c5a4: d106 bne.n 800c5b4 log_printf(LOG_INFO, "Charging permitted, start charging\n"); 800c5a6: 496d ldr r1, [pc, #436] @ (800c75c ) 800c5a8: 2007 movs r0, #7 800c5aa: f7fd ffdd bl 800a568 CCS_ConnectorState = CCS_CONNECTED; 800c5ae: 4b68 ldr r3, [pc, #416] @ (800c750 ) 800c5b0: 2204 movs r2, #4 800c5b2: 701a strb r2, [r3, #0] } if (cp_state_buffer == EV_STATE_A_IDLE){ 800c5b4: 4b65 ldr r3, [pc, #404] @ (800c74c ) 800c5b6: 781b ldrb r3, [r3, #0] 800c5b8: 2b00 cmp r3, #0 800c5ba: d174 bne.n 800c6a6 log_printf(LOG_INFO, "Car unplugged\n"); 800c5bc: 4968 ldr r1, [pc, #416] @ (800c760 ) 800c5be: 2007 movs r0, #7 800c5c0: f7fd ffd2 bl 800a568 CCS_ConnectorState = CCS_UNPLUGGED; 800c5c4: 4b62 ldr r3, [pc, #392] @ (800c750 ) 800c5c6: 2202 movs r2, #2 800c5c8: 701a strb r2, [r3, #0] } break; 800c5ca: e06c b.n 800c6a6 case CCS_CONNECTED: RELAY_Write(RELAY_CP, 1); 800c5cc: 2101 movs r1, #1 800c5ce: 2005 movs r0, #5 800c5d0: f7fd f8f2 bl 80097b8 if((CCS_EvseState < Preparing) || (CCS_EvseState == AuthRequired)) { 800c5d4: 4b63 ldr r3, [pc, #396] @ (800c764 ) 800c5d6: 781b ldrb r3, [r3, #0] 800c5d8: 2b02 cmp r3, #2 800c5da: d903 bls.n 800c5e4 800c5dc: 4b61 ldr r3, [pc, #388] @ (800c764 ) 800c5de: 781b ldrb r3, [r3, #0] 800c5e0: 2b04 cmp r3, #4 800c5e2: d103 bne.n 800c5ec CONN_SetState(Preparing); 800c5e4: 2003 movs r0, #3 800c5e6: f7fd fc85 bl 8009ef4 800c5ea: e004 b.n 800c5f6 } else { CONN_SetState(CCS_EvseState); 800c5ec: 4b5d ldr r3, [pc, #372] @ (800c764 ) 800c5ee: 781b ldrb r3, [r3, #0] 800c5f0: 4618 mov r0, r3 800c5f2: f7fd fc7f bl 8009ef4 } if (cp_state_buffer == EV_STATE_A_IDLE){ 800c5f6: 4b55 ldr r3, [pc, #340] @ (800c74c ) 800c5f8: 781b ldrb r3, [r3, #0] 800c5fa: 2b00 cmp r3, #0 800c5fc: d106 bne.n 800c60c log_printf(LOG_INFO, "Car unplugged\n"); 800c5fe: 4958 ldr r1, [pc, #352] @ (800c760 ) 800c600: 2007 movs r0, #7 800c602: f7fd ffb1 bl 800a568 CCS_ConnectorState = CCS_UNPLUGGED; 800c606: 4b52 ldr r3, [pc, #328] @ (800c750 ) 800c608: 2202 movs r2, #2 800c60a: 701a strb r2, [r3, #0] } if(REPLUG > 0){ 800c60c: 4b56 ldr r3, [pc, #344] @ (800c768 ) 800c60e: 781b ldrb r3, [r3, #0] 800c610: 2b00 cmp r3, #0 800c612: d04a beq.n 800c6aa log_printf(LOG_INFO, "Replugging...\n"); 800c614: 4955 ldr r1, [pc, #340] @ (800c76c ) 800c616: 2007 movs r0, #7 800c618: f7fd ffa6 bl 800a568 CCS_ConnectorState = CCS_REPLUGGING; 800c61c: 4b4c ldr r3, [pc, #304] @ (800c750 ) 800c61e: 2205 movs r2, #5 800c620: 701a strb r2, [r3, #0] } break; 800c622: e042 b.n 800c6aa case CCS_REPLUGGING: RELAY_Write(RELAY_CP, 0); 800c624: 2100 movs r1, #0 800c626: 2005 movs r0, #5 800c628: f7fd f8c6 bl 80097b8 CONN_SetState(Replugging); 800c62c: 200d movs r0, #13 800c62e: f7fd fc61 bl 8009ef4 if((int32_t)(HAL_GetTick() - replug_tick) > 1000){ 800c632: f002 f8a9 bl 800e788 800c636: 4602 mov r2, r0 800c638: 4b4d ldr r3, [pc, #308] @ (800c770 ) 800c63a: 681b ldr r3, [r3, #0] 800c63c: 1ad3 subs r3, r2, r3 800c63e: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800c642: dd1a ble.n 800c67a replug_tick = HAL_GetTick(); 800c644: f002 f8a0 bl 800e788 800c648: 4603 mov r3, r0 800c64a: 4a49 ldr r2, [pc, #292] @ (800c770 ) 800c64c: 6013 str r3, [r2, #0] if(REPLUG > 0){ 800c64e: 4b46 ldr r3, [pc, #280] @ (800c768 ) 800c650: 781b ldrb r3, [r3, #0] 800c652: 2b00 cmp r3, #0 800c654: d00a beq.n 800c66c if (REPLUG != 0xFF) REPLUG--; 800c656: 4b44 ldr r3, [pc, #272] @ (800c768 ) 800c658: 781b ldrb r3, [r3, #0] 800c65a: 2bff cmp r3, #255 @ 0xff 800c65c: d00d beq.n 800c67a 800c65e: 4b42 ldr r3, [pc, #264] @ (800c768 ) 800c660: 781b ldrb r3, [r3, #0] 800c662: 3b01 subs r3, #1 800c664: b2da uxtb r2, r3 800c666: 4b40 ldr r3, [pc, #256] @ (800c768 ) 800c668: 701a strb r2, [r3, #0] 800c66a: e006 b.n 800c67a } else { log_printf(LOG_INFO, "Replugging finished, but car unplugged\n"); 800c66c: 4941 ldr r1, [pc, #260] @ (800c774 ) 800c66e: 2007 movs r0, #7 800c670: f7fd ff7a bl 800a568 CCS_ConnectorState = CCS_UNPLUGGED; 800c674: 4b36 ldr r3, [pc, #216] @ (800c750 ) 800c676: 2202 movs r2, #2 800c678: 701a strb r2, [r3, #0] } } if(REPLUG == 0){ 800c67a: 4b3b ldr r3, [pc, #236] @ (800c768 ) 800c67c: 781b ldrb r3, [r3, #0] 800c67e: 2b00 cmp r3, #0 800c680: d115 bne.n 800c6ae if(cp_state_buffer == EV_STATE_B_CONN_PREP){ 800c682: 4b32 ldr r3, [pc, #200] @ (800c74c ) 800c684: 781b ldrb r3, [r3, #0] 800c686: 2b01 cmp r3, #1 800c688: d111 bne.n 800c6ae log_printf(LOG_INFO, "Replugging finished, car plugged, state -> auth required\n"); 800c68a: 493b ldr r1, [pc, #236] @ (800c778 ) 800c68c: 2007 movs r0, #7 800c68e: f7fd ff6b bl 800a568 CCS_ConnectorState = CCS_AUTH_REQUIRED; 800c692: 4b2f ldr r3, [pc, #188] @ (800c750 ) 800c694: 2203 movs r2, #3 800c696: 701a strb r2, [r3, #0] } } break; 800c698: e009 b.n 800c6ae break; 800c69a: bf00 nop 800c69c: e008 b.n 800c6b0 break; 800c69e: bf00 nop 800c6a0: e006 b.n 800c6b0 break; 800c6a2: bf00 nop 800c6a4: e004 b.n 800c6b0 break; 800c6a6: bf00 nop 800c6a8: e002 b.n 800c6b0 break; 800c6aa: bf00 nop 800c6ac: e000 b.n 800c6b0 break; 800c6ae: bf00 nop } // 10s timeout: enforce safe-state until host communication recovers. if (host_timeout_stop) { 800c6b0: 79bb ldrb r3, [r7, #6] 800c6b2: 2b00 cmp r3, #0 800c6b4: d014 beq.n 800c6e0 CONN.EnableOutput = 0; 800c6b6: 4b27 ldr r3, [pc, #156] @ (800c754 ) 800c6b8: 2200 movs r2, #0 800c6ba: 75da strb r2, [r3, #23] CCS_EvseState = Unknown; 800c6bc: 4b29 ldr r3, [pc, #164] @ (800c764 ) 800c6be: 2200 movs r2, #0 800c6c0: 701a strb r2, [r3, #0] CP_SetDuty(100); 800c6c2: 2064 movs r0, #100 @ 0x64 800c6c4: f7fd fd0e bl 800a0e4 if (CCS_ConnectorState != CCS_DISABLED && CCS_ConnectorState != CCS_UNKNOWN) { 800c6c8: 4b21 ldr r3, [pc, #132] @ (800c750 ) 800c6ca: 781b ldrb r3, [r3, #0] 800c6cc: 2b01 cmp r3, #1 800c6ce: d024 beq.n 800c71a 800c6d0: 4b1f ldr r3, [pc, #124] @ (800c750 ) 800c6d2: 781b ldrb r3, [r3, #0] 800c6d4: 2b00 cmp r3, #0 800c6d6: d020 beq.n 800c71a CCS_ConnectorState = CCS_DISABLED; 800c6d8: 4b1d ldr r3, [pc, #116] @ (800c750 ) 800c6da: 2201 movs r2, #1 800c6dc: 701a strb r2, [r3, #0] 800c6de: e01c b.n 800c71a } } else { if (last_cmd == CMD_STOP) { 800c6e0: 4b26 ldr r3, [pc, #152] @ (800c77c ) 800c6e2: 781b ldrb r3, [r3, #0] 800c6e4: 2b01 cmp r3, #1 800c6e6: d103 bne.n 800c6f0 CONN.EnableOutput = 0; 800c6e8: 4b1a ldr r3, [pc, #104] @ (800c754 ) 800c6ea: 2200 movs r2, #0 800c6ec: 75da strb r2, [r3, #23] 800c6ee: e014 b.n 800c71a } else { CONN.EnableOutput = ev_enable_output ? 1 : 0; 800c6f0: 4b23 ldr r3, [pc, #140] @ (800c780 ) 800c6f2: 781b ldrb r3, [r3, #0] 800c6f4: 2b00 cmp r3, #0 800c6f6: bf14 ite ne 800c6f8: 2301 movne r3, #1 800c6fa: 2300 moveq r3, #0 800c6fc: b2db uxtb r3, r3 800c6fe: 461a mov r2, r3 800c700: 4b14 ldr r3, [pc, #80] @ (800c754 ) 800c702: 75da strb r2, [r3, #23] if((CONN.EnableOutput == 0) && (CONN.connState == Preparing)){ 800c704: 4b13 ldr r3, [pc, #76] @ (800c754 ) 800c706: 7ddb ldrb r3, [r3, #23] 800c708: 2b00 cmp r3, #0 800c70a: d106 bne.n 800c71a 800c70c: 4b11 ldr r3, [pc, #68] @ (800c754 ) 800c70e: 785b ldrb r3, [r3, #1] 800c710: 2b03 cmp r3, #3 800c712: d102 bne.n 800c71a CONN.EnableOutput = 0; 800c714: 4b0f ldr r3, [pc, #60] @ (800c754 ) 800c716: 2200 movs r2, #0 800c718: 75da strb r2, [r3, #23] } } } if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800c71a: 4b0c ldr r3, [pc, #48] @ (800c74c ) 800c71c: 781b ldrb r3, [r3, #0] 800c71e: 2b01 cmp r3, #1 800c720: d007 beq.n 800c732 (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800c722: 4b0a ldr r3, [pc, #40] @ (800c74c ) 800c724: 781b ldrb r3, [r3, #0] if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800c726: 2b02 cmp r3, #2 800c728: d003 beq.n 800c732 (cp_state_buffer == EV_STATE_D_CONN_ACT_VENT)) { 800c72a: 4b08 ldr r3, [pc, #32] @ (800c74c ) 800c72c: 781b ldrb r3, [r3, #0] (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800c72e: 2b03 cmp r3, #3 800c730: d103 bne.n 800c73a CONN.EvConnected = 1; 800c732: 4b08 ldr r3, [pc, #32] @ (800c754 ) 800c734: 2201 movs r2, #1 800c736: 779a strb r2, [r3, #30] 800c738: e004 b.n 800c744 } else { CONN.EvConnected = 0; 800c73a: 4b06 ldr r3, [pc, #24] @ (800c754 ) 800c73c: 2200 movs r2, #0 800c73e: 779a strb r2, [r3, #30] 800c740: e000 b.n 800c744 if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800c742: bf00 nop } } 800c744: 3708 adds r7, #8 800c746: 46bd mov sp, r7 800c748: bd80 pop {r7, pc} 800c74a: bf00 nop 800c74c: 20000005 .word 0x20000005 800c750: 20000d25 .word 0x20000d25 800c754: 200003b0 .word 0x200003b0 800c758: 0801783c .word 0x0801783c 800c75c: 08017864 .word 0x08017864 800c760: 08017888 .word 0x08017888 800c764: 20000d24 .word 0x20000d24 800c768: 20000cc4 .word 0x20000cc4 800c76c: 08017898 .word 0x08017898 800c770: 20000d38 .word 0x20000d38 800c774: 080178a8 .word 0x080178a8 800c778: 080178d0 .word 0x080178d0 800c77c: 200009bc .word 0x200009bc 800c780: 200009bd .word 0x200009bd 0800c784 : void CCS_Init(void){ 800c784: b580 push {r7, lr} 800c786: af00 add r7, sp, #0 CP_Init(); 800c788: f7fd fc8a bl 800a0a0 CP_SetDuty(100); 800c78c: 2064 movs r0, #100 @ 0x64 800c78e: f7fd fca9 bl 800a0e4 CCS_MaxLoad.maxVoltage = PSU_MAX_VOLTAGE; // 1000V 800c792: 4b13 ldr r3, [pc, #76] @ (800c7e0 ) 800c794: f44f 727a mov.w r2, #1000 @ 0x3e8 800c798: 801a strh r2, [r3, #0] CCS_MaxLoad.minVoltage = PSU_MIN_VOLTAGE; //150V 800c79a: 4b11 ldr r3, [pc, #68] @ (800c7e0 ) 800c79c: 2296 movs r2, #150 @ 0x96 800c79e: 805a strh r2, [r3, #2] CCS_MaxLoad.maxCurrent = PSU_MAX_CURRENT*10; //100A 800c7a0: 4b0f ldr r3, [pc, #60] @ (800c7e0 ) 800c7a2: f240 5232 movw r2, #1330 @ 0x532 800c7a6: 809a strh r2, [r3, #4] CCS_MaxLoad.minCurrent = PSU_MIN_CURRENT*10; //1A 800c7a8: 4b0d ldr r3, [pc, #52] @ (800c7e0 ) 800c7aa: 220a movs r2, #10 800c7ac: 80da strh r2, [r3, #6] CCS_MaxLoad.maxPower = PSU_MAX_POWER; //30000W 800c7ae: 4b0c ldr r3, [pc, #48] @ (800c7e0 ) 800c7b0: f649 4240 movw r2, #40000 @ 0x9c40 800c7b4: 609a str r2, [r3, #8] uart3_last_packet_tick = HAL_GetTick(); 800c7b6: f001 ffe7 bl 800e788 800c7ba: 4603 mov r3, r0 800c7bc: 4a09 ldr r2, [pc, #36] @ (800c7e4 ) 800c7be: 6013 str r3, [r2, #0] uart3_last_reinit_tick = uart3_last_packet_tick; 800c7c0: 4b08 ldr r3, [pc, #32] @ (800c7e4 ) 800c7c2: 681b ldr r3, [r3, #0] 800c7c4: 4a08 ldr r2, [pc, #32] @ (800c7e8 ) 800c7c6: 6013 str r3, [r2, #0] uart3_arm_rx_or_log("Init"); 800c7c8: 4808 ldr r0, [pc, #32] @ (800c7ec ) 800c7ca: f7ff fc2b bl 800c024 CCS_SendResetReason(); 800c7ce: f000 f8e3 bl 800c998 log_printf(LOG_INFO, "CCS init\n"); 800c7d2: 4907 ldr r1, [pc, #28] @ (800c7f0 ) 800c7d4: 2007 movs r0, #7 800c7d6: f7fd fec7 bl 800a568 } 800c7da: bf00 nop 800c7dc: bd80 pop {r7, pc} 800c7de: bf00 nop 800c7e0: 2000099c .word 0x2000099c 800c7e4: 20000cd0 .word 0x20000cd0 800c7e8: 20000cd4 .word 0x20000cd4 800c7ec: 0801790c .word 0x0801790c 800c7f0: 08017914 .word 0x08017914 0800c7f4 : ISR_FAST static uint16_t crc16_ibm(const uint8_t* data, uint16_t length) { uint16_t crc = 0xFFFFu; for (uint16_t i = 0; i < length; i++) { 800c7f4: b3e9 cbz r1, 800c872 800c7f6: 4684 mov ip, r0 ISR_FAST static uint16_t crc16_ibm(const uint8_t* data, uint16_t length) { 800c7f8: b500 push {lr} 800c7fa: 468e mov lr, r1 uint16_t crc = 0xFFFFu; 800c7fc: f64f 70ff movw r0, #65535 @ 0xffff crc ^= data[i]; for (uint8_t j = 0; j < 8; j++) { if (crc & 1u) { 800c800: 491d ldr r1, [pc, #116] @ (800c878 ) 800c802: 44e6 add lr, ip crc ^= data[i]; 800c804: f81c 2b01 ldrb.w r2, [ip], #1 800c808: 4042 eors r2, r0 if (crc & 1u) { 800c80a: f342 0300 sbfx r3, r2, #0, #1 800c80e: 400b ands r3, r1 800c810: ea83 0352 eor.w r3, r3, r2, lsr #1 800c814: f343 0200 sbfx r2, r3, #0, #1 800c818: 400a ands r2, r1 crc = (crc >> 1) ^ 0xA001u; } else { crc >>= 1; 800c81a: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c81e: 405a eors r2, r3 800c820: f342 0300 sbfx r3, r2, #0, #1 800c824: 400b ands r3, r1 crc >>= 1; 800c826: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800c82a: 4053 eors r3, r2 800c82c: f343 0200 sbfx r2, r3, #0, #1 800c830: 400a ands r2, r1 crc >>= 1; 800c832: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c836: 405a eors r2, r3 800c838: f342 0300 sbfx r3, r2, #0, #1 800c83c: 400b ands r3, r1 crc >>= 1; 800c83e: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800c842: 4053 eors r3, r2 800c844: f343 0200 sbfx r2, r3, #0, #1 800c848: 400a ands r2, r1 crc >>= 1; 800c84a: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c84e: 405a eors r2, r3 800c850: f342 0300 sbfx r3, r2, #0, #1 800c854: 400b ands r3, r1 crc >>= 1; 800c856: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800c85a: 4053 eors r3, r2 800c85c: f343 0000 sbfx r0, r3, #0, #1 800c860: 4008 ands r0, r1 crc >>= 1; 800c862: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c866: 4058 eors r0, r3 for (uint16_t i = 0; i < length; i++) { 800c868: 45e6 cmp lr, ip if (crc & 1u) { 800c86a: b280 uxth r0, r0 for (uint16_t i = 0; i < length; i++) { 800c86c: d1ca bne.n 800c804 } } } return crc; } 800c86e: f85d fb04 ldr.w pc, [sp], #4 uint16_t crc = 0xFFFFu; 800c872: f64f 70ff movw r0, #65535 @ 0xffff } 800c876: 4770 bx lr 800c878: ffffa001 .word 0xffffa001 0800c87c : static uint16_t CCS_BuildPacket(uint8_t cmd, const void* payload, uint16_t payload_len, uint8_t* out, uint16_t out_max) { 800c87c: b580 push {r7, lr} 800c87e: b086 sub sp, #24 800c880: af00 add r7, sp, #0 800c882: 60b9 str r1, [r7, #8] 800c884: 607b str r3, [r7, #4] 800c886: 4603 mov r3, r0 800c888: 73fb strb r3, [r7, #15] 800c88a: 4613 mov r3, r2 800c88c: 81bb strh r3, [r7, #12] uint16_t total_len = (uint16_t)(1u + payload_len + 2u); 800c88e: 89bb ldrh r3, [r7, #12] 800c890: 3303 adds r3, #3 800c892: 82fb strh r3, [r7, #22] if (total_len > out_max) return 0; 800c894: 8afa ldrh r2, [r7, #22] 800c896: 8c3b ldrh r3, [r7, #32] 800c898: 429a cmp r2, r3 800c89a: d901 bls.n 800c8a0 800c89c: 2300 movs r3, #0 800c89e: e029 b.n 800c8f4 out[0] = cmd; 800c8a0: 687b ldr r3, [r7, #4] 800c8a2: 7bfa ldrb r2, [r7, #15] 800c8a4: 701a strb r2, [r3, #0] if (payload_len && payload != NULL) { 800c8a6: 89bb ldrh r3, [r7, #12] 800c8a8: 2b00 cmp r3, #0 800c8aa: d009 beq.n 800c8c0 800c8ac: 68bb ldr r3, [r7, #8] 800c8ae: 2b00 cmp r3, #0 800c8b0: d006 beq.n 800c8c0 memcpy(&out[1], payload, payload_len); 800c8b2: 687b ldr r3, [r7, #4] 800c8b4: 3301 adds r3, #1 800c8b6: 89ba ldrh r2, [r7, #12] 800c8b8: 68b9 ldr r1, [r7, #8] 800c8ba: 4618 mov r0, r3 800c8bc: f008 fc66 bl 801518c } uint16_t crc = crc16_ibm(out, (uint16_t)(1u + payload_len)); 800c8c0: 89bb ldrh r3, [r7, #12] 800c8c2: 3301 adds r3, #1 800c8c4: b29b uxth r3, r3 800c8c6: 4619 mov r1, r3 800c8c8: 6878 ldr r0, [r7, #4] 800c8ca: f7ff ff93 bl 800c7f4 800c8ce: 4603 mov r3, r0 800c8d0: 82bb strh r3, [r7, #20] out[1u + payload_len] = (uint8_t)(crc & 0xFFu); 800c8d2: 89bb ldrh r3, [r7, #12] 800c8d4: 3301 adds r3, #1 800c8d6: 687a ldr r2, [r7, #4] 800c8d8: 4413 add r3, r2 800c8da: 8aba ldrh r2, [r7, #20] 800c8dc: b2d2 uxtb r2, r2 800c8de: 701a strb r2, [r3, #0] out[1u + payload_len + 1u] = (uint8_t)((crc >> 8) & 0xFFu); 800c8e0: 8abb ldrh r3, [r7, #20] 800c8e2: 0a1b lsrs r3, r3, #8 800c8e4: b299 uxth r1, r3 800c8e6: 89bb ldrh r3, [r7, #12] 800c8e8: 3302 adds r3, #2 800c8ea: 687a ldr r2, [r7, #4] 800c8ec: 4413 add r3, r2 800c8ee: b2ca uxtb r2, r1 800c8f0: 701a strb r2, [r3, #0] return total_len; 800c8f2: 8afb ldrh r3, [r7, #22] } 800c8f4: 4618 mov r0, r3 800c8f6: 3718 adds r7, #24 800c8f8: 46bd mov sp, r7 800c8fa: bd80 pop {r7, pc} 0800c8fc : static void CCS_SendPacket(uint8_t cmd, const void* payload, uint16_t payload_len) { 800c8fc: b580 push {r7, lr} 800c8fe: b086 sub sp, #24 800c900: af02 add r7, sp, #8 800c902: 4603 mov r3, r0 800c904: 6039 str r1, [r7, #0] 800c906: 71fb strb r3, [r7, #7] 800c908: 4613 mov r3, r2 800c90a: 80bb strh r3, [r7, #4] uint16_t len = CCS_BuildPacket(cmd, payload, payload_len, tx_buffer, sizeof(tx_buffer)); 800c90c: 88ba ldrh r2, [r7, #4] 800c90e: 79f8 ldrb r0, [r7, #7] 800c910: f44f 7380 mov.w r3, #256 @ 0x100 800c914: 9300 str r3, [sp, #0] 800c916: 4b19 ldr r3, [pc, #100] @ (800c97c ) 800c918: 6839 ldr r1, [r7, #0] 800c91a: f7ff ffaf bl 800c87c 800c91e: 4603 mov r3, r0 800c920: 81fb strh r3, [r7, #14] if (len > 0) { 800c922: 89fb ldrh r3, [r7, #14] 800c924: 2b00 cmp r3, #0 800c926: d01f beq.n 800c968 if (uart3_tx_busy) { 800c928: 4b15 ldr r3, [pc, #84] @ (800c980 ) 800c92a: 781b ldrb r3, [r3, #0] 800c92c: 2b00 cmp r3, #0 800c92e: d009 beq.n 800c944 memcpy(tx_pending_buffer, tx_buffer, len); 800c930: 89fb ldrh r3, [r7, #14] 800c932: 461a mov r2, r3 800c934: 4911 ldr r1, [pc, #68] @ (800c97c ) 800c936: 4813 ldr r0, [pc, #76] @ (800c984 ) 800c938: f008 fc28 bl 801518c tx_pending_len = len; 800c93c: 4a12 ldr r2, [pc, #72] @ (800c988 ) 800c93e: 89fb ldrh r3, [r7, #14] 800c940: 8013 strh r3, [r2, #0] 800c942: e011 b.n 800c968 } else { uart3_tx_busy = 1; 800c944: 4b0e ldr r3, [pc, #56] @ (800c980 ) 800c946: 2201 movs r2, #1 800c948: 701a strb r2, [r3, #0] if (HAL_UART_Transmit_DMA(&huart3, tx_buffer, len) != HAL_OK) { 800c94a: 89fb ldrh r3, [r7, #14] 800c94c: 461a mov r2, r3 800c94e: 490b ldr r1, [pc, #44] @ (800c97c ) 800c950: 480e ldr r0, [pc, #56] @ (800c98c ) 800c952: f006 fd15 bl 8013380 800c956: 4603 mov r3, r0 800c958: 2b00 cmp r3, #0 800c95a: d005 beq.n 800c968 uart3_tx_busy = 0; 800c95c: 4b08 ldr r3, [pc, #32] @ (800c980 ) 800c95e: 2200 movs r2, #0 800c960: 701a strb r2, [r3, #0] CCS_LogUart3Error("UART3 TX DMA start failed"); 800c962: 480b ldr r0, [pc, #44] @ (800c990 ) 800c964: f000 fa5a bl 800ce1c } } } last_cmd_sent = HAL_GetTick(); 800c968: f001 ff0e bl 800e788 800c96c: 4603 mov r3, r0 800c96e: 4a09 ldr r2, [pc, #36] @ (800c994 ) 800c970: 6013 str r3, [r2, #0] } 800c972: bf00 nop 800c974: 3710 adds r7, #16 800c976: 46bd mov sp, r7 800c978: bd80 pop {r7, pc} 800c97a: bf00 nop 800c97c: 20000ac0 .word 0x20000ac0 800c980: 20000cc2 .word 0x20000cc2 800c984: 20000bc0 .word 0x20000bc0 800c988: 20000cc0 .word 0x20000cc0 800c98c: 20001344 .word 0x20001344 800c990: 08017920 .word 0x08017920 800c994: 200009b4 .word 0x200009b4 0800c998 : static void CCS_SendResetReason(void) { 800c998: b580 push {r7, lr} 800c99a: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_RESET, NULL, 0); 800c99c: 2200 movs r2, #0 800c99e: 2100 movs r1, #0 800c9a0: 2052 movs r0, #82 @ 0x52 800c9a2: f7ff ffab bl 800c8fc } 800c9a6: bf00 nop 800c9a8: bd80 pop {r7, pc} 800c9aa: bf00 nop 0800c9ac : void CCS_SendEmergencyStop(void) { 800c9ac: b580 push {r7, lr} 800c9ae: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_ESTOP, NULL, 0); 800c9b0: 2200 movs r2, #0 800c9b2: 2100 movs r1, #0 800c9b4: 2053 movs r0, #83 @ 0x53 800c9b6: f7ff ffa1 bl 800c8fc } 800c9ba: bf00 nop 800c9bc: bd80 pop {r7, pc} 800c9be: bf00 nop 0800c9c0 : void CCS_SendStart(void) { CCS_SendPacket(CMD_M2E_START, NULL, 0); } static void CCS_CalculateEnergy(void) { 800c9c0: b580 push {r7, lr} 800c9c2: b082 sub sp, #8 800c9c4: af00 add r7, sp, #0 static uint32_t lastTick = 0; uint32_t currentTick = HAL_GetTick(); 800c9c6: f001 fedf bl 800e788 800c9ca: 6078 str r0, [r7, #4] uint32_t elapsedTimeMs = currentTick - lastTick; 800c9cc: 4b1e ldr r3, [pc, #120] @ (800ca48 ) 800c9ce: 681b ldr r3, [r3, #0] 800c9d0: 687a ldr r2, [r7, #4] 800c9d2: 1ad3 subs r3, r2, r3 800c9d4: 603b str r3, [r7, #0] lastTick = currentTick; 800c9d6: 4a1c ldr r2, [pc, #112] @ (800ca48 ) 800c9d8: 687b ldr r3, [r7, #4] 800c9da: 6013 str r3, [r2, #0] CCS_Power = CONN.MeasuredVoltage * CONN.MeasuredCurrent / 10; 800c9dc: 4b1b ldr r3, [pc, #108] @ (800ca4c ) 800c9de: f8b3 3013 ldrh.w r3, [r3, #19] 800c9e2: b29b uxth r3, r3 800c9e4: 461a mov r2, r3 800c9e6: 4b19 ldr r3, [pc, #100] @ (800ca4c ) 800c9e8: f8b3 3015 ldrh.w r3, [r3, #21] 800c9ec: b29b uxth r3, r3 800c9ee: fb02 f303 mul.w r3, r2, r3 800c9f2: 4a17 ldr r2, [pc, #92] @ (800ca50 ) 800c9f4: fb82 1203 smull r1, r2, r2, r3 800c9f8: 1092 asrs r2, r2, #2 800c9fa: 17db asrs r3, r3, #31 800c9fc: 1ad3 subs r3, r2, r3 800c9fe: 461a mov r2, r3 800ca00: 4b14 ldr r3, [pc, #80] @ (800ca54 ) 800ca02: 601a str r2, [r3, #0] CCS_EnergyWs += (CCS_Power * elapsedTimeMs) / 1000; 800ca04: 4b13 ldr r3, [pc, #76] @ (800ca54 ) 800ca06: 681b ldr r3, [r3, #0] 800ca08: 683a ldr r2, [r7, #0] 800ca0a: fb02 f303 mul.w r3, r2, r3 800ca0e: 4a12 ldr r2, [pc, #72] @ (800ca58 ) 800ca10: fba2 2303 umull r2, r3, r2, r3 800ca14: 099a lsrs r2, r3, #6 800ca16: 4b11 ldr r3, [pc, #68] @ (800ca5c ) 800ca18: 681b ldr r3, [r3, #0] 800ca1a: 4413 add r3, r2 800ca1c: 4a0f ldr r2, [pc, #60] @ (800ca5c ) 800ca1e: 6013 str r3, [r2, #0] if(CCS_EvseState == Unplugged) { 800ca20: 4b0f ldr r3, [pc, #60] @ (800ca60 ) 800ca22: 781b ldrb r3, [r3, #0] 800ca24: 2b01 cmp r3, #1 800ca26: d102 bne.n 800ca2e CCS_EnergyWs = 0; 800ca28: 4b0c ldr r3, [pc, #48] @ (800ca5c ) 800ca2a: 2200 movs r2, #0 800ca2c: 601a str r2, [r3, #0] } CCS_Energy = CCS_EnergyWs / 3600; 800ca2e: 4b0b ldr r3, [pc, #44] @ (800ca5c ) 800ca30: 681b ldr r3, [r3, #0] 800ca32: 4a0c ldr r2, [pc, #48] @ (800ca64 ) 800ca34: fba2 2303 umull r2, r3, r2, r3 800ca38: 0adb lsrs r3, r3, #11 800ca3a: 4a0b ldr r2, [pc, #44] @ (800ca68 ) 800ca3c: 6013 str r3, [r2, #0] } 800ca3e: bf00 nop 800ca40: 3708 adds r7, #8 800ca42: 46bd mov sp, r7 800ca44: bd80 pop {r7, pc} 800ca46: bf00 nop 800ca48: 20000d3c .word 0x20000d3c 800ca4c: 200003b0 .word 0x200003b0 800ca50: 66666667 .word 0x66666667 800ca54: 200009a8 .word 0x200009a8 800ca58: 10624dd3 .word 0x10624dd3 800ca5c: 200009ac .word 0x200009ac 800ca60: 20000d24 .word 0x20000d24 800ca64: 91a2b3c5 .word 0x91a2b3c5 800ca68: 200009b0 .word 0x200009b0 0800ca6c : static void send_state(void) { 800ca6c: b580 push {r7, lr} 800ca6e: af00 add r7, sp, #0 CCS_CalculateEnergy(); 800ca70: f7ff ffa6 bl 800c9c0 CCS_State.DutyCycle = CP_GetDuty(); 800ca74: f7fd fb5e bl 800a134 800ca78: 4603 mov r3, r0 800ca7a: 461a mov r2, r3 800ca7c: 4b2e ldr r3, [pc, #184] @ (800cb38 ) 800ca7e: 701a strb r2, [r3, #0] CCS_State.OutputEnabled = PSU0.CONT_enabled; 800ca80: 4b2e ldr r3, [pc, #184] @ (800cb3c ) 800ca82: 7ada ldrb r2, [r3, #11] 800ca84: 4b2c ldr r3, [pc, #176] @ (800cb38 ) 800ca86: 705a strb r2, [r3, #1] CCS_State.MeasuredVoltage = (uint16_t)CONN.MeasuredVoltage; 800ca88: 4b2d ldr r3, [pc, #180] @ (800cb40 ) 800ca8a: f8b3 3013 ldrh.w r3, [r3, #19] 800ca8e: b29a uxth r2, r3 800ca90: 4b29 ldr r3, [pc, #164] @ (800cb38 ) 800ca92: 805a strh r2, [r3, #2] if (fake_500_voltage_mode) { 800ca94: 4b2b ldr r3, [pc, #172] @ (800cb44 ) 800ca96: 781b ldrb r3, [r3, #0] 800ca98: 2b00 cmp r3, #0 800ca9a: d003 beq.n 800caa4 CCS_State.MeasuredVoltage = FAKE_EVREQ_VOLTAGE_V; 800ca9c: 4b26 ldr r3, [pc, #152] @ (800cb38 ) 800ca9e: f44f 72fa mov.w r2, #500 @ 0x1f4 800caa2: 805a strh r2, [r3, #2] } CCS_State.MeasuredCurrent = (uint16_t)CONN.MeasuredCurrent; 800caa4: 4b26 ldr r3, [pc, #152] @ (800cb40 ) 800caa6: f8b3 3015 ldrh.w r3, [r3, #21] 800caaa: b29a uxth r2, r3 800caac: 4b22 ldr r3, [pc, #136] @ (800cb38 ) 800caae: 809a strh r2, [r3, #4] CCS_State.Power = CCS_Power; 800cab0: 4b25 ldr r3, [pc, #148] @ (800cb48 ) 800cab2: 681b ldr r3, [r3, #0] 800cab4: 4a20 ldr r2, [pc, #128] @ (800cb38 ) 800cab6: f8c2 3006 str.w r3, [r2, #6] CCS_State.Energy = CCS_Energy; 800caba: 4b24 ldr r3, [pc, #144] @ (800cb4c ) 800cabc: 681b ldr r3, [r3, #0] 800cabe: 4a1e ldr r2, [pc, #120] @ (800cb38 ) 800cac0: f8c2 300a str.w r3, [r2, #10] if(CCS_ConnectorState == CCS_CONNECTED){ 800cac4: 4b22 ldr r3, [pc, #136] @ (800cb50 ) 800cac6: 781b ldrb r3, [r3, #0] 800cac8: 2b04 cmp r3, #4 800caca: d104 bne.n 800cad6 CCS_State.CpState = cp_state_buffer; 800cacc: 4b21 ldr r3, [pc, #132] @ (800cb54 ) 800cace: 781a ldrb r2, [r3, #0] 800cad0: 4b19 ldr r3, [pc, #100] @ (800cb38 ) 800cad2: 74da strb r2, [r3, #19] 800cad4: e002 b.n 800cadc } else { CCS_State.CpState = EV_STATE_A_IDLE; 800cad6: 4b18 ldr r3, [pc, #96] @ (800cb38 ) 800cad8: 2200 movs r2, #0 800cada: 74da strb r2, [r3, #19] } CCS_State.MaxVoltage = CCS_MaxLoad.maxVoltage; 800cadc: 4b1e ldr r3, [pc, #120] @ (800cb58 ) 800cade: 881a ldrh r2, [r3, #0] 800cae0: 4b15 ldr r3, [pc, #84] @ (800cb38 ) 800cae2: 829a strh r2, [r3, #20] CCS_State.MinVoltage = CCS_MaxLoad.minVoltage; 800cae4: 4b1c ldr r3, [pc, #112] @ (800cb58 ) 800cae6: 885a ldrh r2, [r3, #2] 800cae8: 4b13 ldr r3, [pc, #76] @ (800cb38 ) 800caea: 82da strh r2, [r3, #22] CCS_State.MaxCurrent = CCS_MaxLoad.maxCurrent; 800caec: 4b1a ldr r3, [pc, #104] @ (800cb58 ) 800caee: 889a ldrh r2, [r3, #4] 800caf0: 4b11 ldr r3, [pc, #68] @ (800cb38 ) 800caf2: 831a strh r2, [r3, #24] CCS_State.MinCurrent = CCS_MaxLoad.minCurrent; 800caf4: 4b18 ldr r3, [pc, #96] @ (800cb58 ) 800caf6: 88da ldrh r2, [r3, #6] 800caf8: 4b0f ldr r3, [pc, #60] @ (800cb38 ) 800cafa: 835a strh r2, [r3, #26] CCS_State.MaxPower = CCS_MaxLoad.maxPower; 800cafc: 4b16 ldr r3, [pc, #88] @ (800cb58 ) 800cafe: 689b ldr r3, [r3, #8] 800cb00: 4a0d ldr r2, [pc, #52] @ (800cb38 ) 800cb02: 61d3 str r3, [r2, #28] CCS_State.IsolationValid = isolation_enable; 800cb04: 4b15 ldr r3, [pc, #84] @ (800cb5c ) 800cb06: 781a ldrb r2, [r3, #0] 800cb08: 4b0b ldr r3, [pc, #44] @ (800cb38 ) 800cb0a: 749a strb r2, [r3, #18] CCS_State.IsolationResistance = 900000; 800cb0c: 4a0a ldr r2, [pc, #40] @ (800cb38 ) 800cb0e: 2300 movs r3, #0 800cb10: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800cb14: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800cb18: f443 433b orr.w r3, r3, #47872 @ 0xbb00 800cb1c: f043 03a0 orr.w r3, r3, #160 @ 0xa0 800cb20: 81d3 strh r3, [r2, #14] 800cb22: 2300 movs r3, #0 800cb24: f043 030d orr.w r3, r3, #13 800cb28: 8213 strh r3, [r2, #16] CCS_SendPacket(CMD_M2E_STATE, &CCS_State, sizeof(CCS_State)); 800cb2a: 2220 movs r2, #32 800cb2c: 4902 ldr r1, [pc, #8] @ (800cb38 ) 800cb2e: 2050 movs r0, #80 @ 0x50 800cb30: f7ff fee4 bl 800c8fc } 800cb34: bf00 nop 800cb36: bd80 pop {r7, pc} 800cb38: 20000cd8 .word 0x20000cd8 800cb3c: 20000904 .word 0x20000904 800cb40: 200003b0 .word 0x200003b0 800cb44: 20000ccc .word 0x20000ccc 800cb48: 200009a8 .word 0x200009a8 800cb4c: 200009b0 .word 0x200009b0 800cb50: 20000d25 .word 0x20000d25 800cb54: 20000005 .word 0x20000005 800cb58: 2000099c .word 0x2000099c 800cb5c: 20000cc6 .word 0x20000cc6 0800cb60 : ISR_FAST static uint16_t expected_payload_len(uint8_t cmd) { switch (cmd) { 800cb60: 3840 subs r0, #64 @ 0x40 800cb62: b2c0 uxtb r0, r0 800cb64: 2809 cmp r0, #9 800cb66: bf9a itte ls 800cb68: 4b02 ldrls r3, [pc, #8] @ (800cb74 ) 800cb6a: f833 0010 ldrhls.w r0, [r3, r0, lsl #1] ISR_FAST static uint16_t expected_payload_len(uint8_t cmd) { 800cb6e: f64f 70ff movwhi r0, #65535 @ 0xffff case CMD_E2M_EV_INFO: return sizeof(CCS_EvInfo_t); case CMD_E2M_EVSE_STATE: return sizeof(CONN_State_t); case CMD_E2M_KEEP_ALIVE: return 0; default: return 0xFFFFu; } } 800cb72: 4770 bx lr 800cb74: 08017d50 .word 0x08017d50 0800cb78 : ISR_FAST static void apply_command(uint8_t cmd, const uint8_t* payload, uint16_t payload_len) { 800cb78: b5f8 push {r3, r4, r5, r6, r7, lr} 800cb7a: 4604 mov r4, r0 800cb7c: 460d mov r5, r1 (void)payload_len; last_host_seen = HAL_GetTick(); 800cb7e: f001 fe03 bl 800e788 everest_timed_out = 0; 800cb82: 2300 movs r3, #0 800cb84: 4a42 ldr r2, [pc, #264] @ (800cc90 ) last_host_seen = HAL_GetTick(); 800cb86: 4e43 ldr r6, [pc, #268] @ (800cc94 ) everest_timed_out = 0; 800cb88: 7013 strb r3, [r2, #0] everest_timeout_warn_latched = 0; 800cb8a: 4a43 ldr r2, [pc, #268] @ (800cc98 ) last_host_seen = HAL_GetTick(); 800cb8c: 6030 str r0, [r6, #0] everest_timeout_warn_latched = 0; 800cb8e: 7013 strb r3, [r2, #0] everest_timeout_stop_latched = 0; 800cb90: 4a42 ldr r2, [pc, #264] @ (800cc9c ) 800cb92: 7013 strb r3, [r2, #0] switch (cmd) { 800cb94: f1a4 0340 sub.w r3, r4, #64 @ 0x40 800cb98: 2b09 cmp r3, #9 800cb9a: d871 bhi.n 800cc80 800cb9c: e8df f003 tbb [pc, r3] 800cba0: 4e5b1409 .word 0x4e5b1409 800cba4: 2e2a1b55 .word 0x2e2a1b55 800cba8: 054a .short 0x054a (void)payload; CP_SetDuty(pwm_duty_percent); break; } case CMD_E2M_KEEP_ALIVE: { last_host_seen = HAL_GetTick(); 800cbaa: f001 fded bl 800e788 800cbae: 6030 str r0, [r6, #0] log_printf(LOG_WARN, "UART3 RX warn: cmd 0x%02x CRC/len OK but no switch case (expected_payload vs apply_command)\n", cmd); break; } } 800cbb0: bdf8 pop {r3, r4, r5, r6, r7, pc} if (duty > 100) duty = 100; 800cbb2: 7828 ldrb r0, [r5, #0] if (CONN.connControl != CMD_FORCE_UNLOCK) { 800cbb4: 4b3a ldr r3, [pc, #232] @ (800cca0 ) if (duty > 100) duty = 100; 800cbb6: 2864 cmp r0, #100 @ 0x64 800cbb8: bf28 it cs 800cbba: 2064 movcs r0, #100 @ 0x64 if (CONN.connControl != CMD_FORCE_UNLOCK) { 800cbbc: 781b ldrb r3, [r3, #0] pwm_duty_percent = duty; 800cbbe: 4a39 ldr r2, [pc, #228] @ (800cca4 ) if (CONN.connControl != CMD_FORCE_UNLOCK) { 800cbc0: 2b03 cmp r3, #3 pwm_duty_percent = duty; 800cbc2: 7010 strb r0, [r2, #0] if (CONN.connControl != CMD_FORCE_UNLOCK) { 800cbc4: d143 bne.n 800cc4e } 800cbc6: bdf8 pop {r3, r4, r5, r6, r7, pc} ev_enable_output = (p->enable_output != 0); 800cbc8: 782b ldrb r3, [r5, #0] 800cbca: 4a37 ldr r2, [pc, #220] @ (800cca8 ) 800cbcc: 3b00 subs r3, #0 800cbce: bf18 it ne 800cbd0: 2301 movne r3, #1 800cbd2: 7013 strb r3, [r2, #0] } 800cbd4: bdf8 pop {r3, r4, r5, r6, r7, pc} if (p->voltage_V == FAKE_EVREQ_VOLTAGE_V) { 800cbd6: 882b ldrh r3, [r5, #0] 800cbd8: b29a uxth r2, r3 800cbda: f5b2 7ffa cmp.w r2, #500 @ 0x1f4 800cbde: d043 beq.n 800cc68 fake_500_voltage_mode = 0u; 800cbe0: 2000 movs r0, #0 CONN.RequestedVoltage = p->voltage_V; 800cbe2: 4a2f ldr r2, [pc, #188] @ (800cca0 ) fake_500_voltage_mode = 0u; 800cbe4: 4931 ldr r1, [pc, #196] @ (800ccac ) CONN.RequestedVoltage = p->voltage_V; 800cbe6: f8a2 300f strh.w r3, [r2, #15] fake_500_voltage_mode = 0u; 800cbea: 7008 strb r0, [r1, #0] CONN.WantedCurrent = p->current_0p1A; 800cbec: 886b ldrh r3, [r5, #2] 800cbee: f8a2 301b strh.w r3, [r2, #27] } 800cbf2: bdf8 pop {r3, r4, r5, r6, r7, pc} isolation_enable = p->command; 800cbf4: 782a ldrb r2, [r5, #0] 800cbf6: 4b2e ldr r3, [pc, #184] @ (800ccb0 ) 800cbf8: 701a strb r2, [r3, #0] } 800cbfa: bdf8 pop {r3, r4, r5, r6, r7, pc} memcpy(&CCS_EvInfo, payload, sizeof(CCS_EvInfo_t)); 800cbfc: 4f2d ldr r7, [pc, #180] @ (800ccb4 ) 800cbfe: 462c mov r4, r5 800cc00: 463e mov r6, r7 800cc02: f105 0c20 add.w ip, r5, #32 800cc06: 4635 mov r5, r6 800cc08: 6820 ldr r0, [r4, #0] 800cc0a: 6861 ldr r1, [r4, #4] 800cc0c: 68a2 ldr r2, [r4, #8] 800cc0e: 68e3 ldr r3, [r4, #12] 800cc10: 3410 adds r4, #16 800cc12: 4564 cmp r4, ip 800cc14: c50f stmia r5!, {r0, r1, r2, r3} 800cc16: f106 0610 add.w r6, r6, #16 800cc1a: d1f4 bne.n 800cc06 800cc1c: 6861 ldr r1, [r4, #4] 800cc1e: 68a2 ldr r2, [r4, #8] 800cc20: 6820 ldr r0, [r4, #0] 800cc22: c607 stmia r6!, {r0, r1, r2} CONN.SOC = (uint8_t)(CCS_EvInfo.soc / 10); 800cc24: 4a24 ldr r2, [pc, #144] @ (800ccb8 ) 800cc26: 887b ldrh r3, [r7, #2] 800cc28: 491d ldr r1, [pc, #116] @ (800cca0 ) 800cc2a: fba2 2303 umull r2, r3, r2, r3 800cc2e: 08db lsrs r3, r3, #3 800cc30: 708b strb r3, [r1, #2] } 800cc32: bdf8 pop {r3, r4, r5, r6, r7, pc} CCS_EvseState = (CONN_State_t)payload[0]; 800cc34: 782a ldrb r2, [r5, #0] 800cc36: 4b21 ldr r3, [pc, #132] @ (800ccbc ) 800cc38: 701a strb r2, [r3, #0] } 800cc3a: bdf8 pop {r3, r4, r5, r6, r7, pc} enabled = (p->enable != 0); 800cc3c: 782b ldrb r3, [r5, #0] 800cc3e: 4a20 ldr r2, [pc, #128] @ (800ccc0 ) 800cc40: 3b00 subs r3, #0 800cc42: bf18 it ne 800cc44: 2301 movne r3, #1 800cc46: 7013 strb r3, [r2, #0] } 800cc48: bdf8 pop {r3, r4, r5, r6, r7, pc} CP_SetDuty(pwm_duty_percent); 800cc4a: 4b16 ldr r3, [pc, #88] @ (800cca4 ) 800cc4c: 7818 ldrb r0, [r3, #0] } 800cc4e: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} CP_SetDuty(pwm_duty_percent); 800cc52: f7fd ba47 b.w 800a0e4 if (p->reset) { 800cc56: 782b ldrb r3, [r5, #0] 800cc58: 2b00 cmp r3, #0 800cc5a: d0a9 beq.n 800cbb0 } 800cc5c: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} log_printf(LOG_WARN, "Everest reset command\n"); 800cc60: 2005 movs r0, #5 800cc62: 4918 ldr r1, [pc, #96] @ (800ccc4 ) 800cc64: f7fd bc80 b.w 800a568 fake_500_voltage_mode = 1u; 800cc68: 2201 movs r2, #1 CONN.RequestedVoltage = FAKE_PSU_VOLTAGE_V; 800cc6a: 2100 movs r1, #0 800cc6c: 242c movs r4, #44 @ 0x2c CONN.WantedCurrent = FAKE_PSU_CURRENT_0P1A; 800cc6e: 200a movs r0, #10 fake_500_voltage_mode = 1u; 800cc70: 4d0e ldr r5, [pc, #56] @ (800ccac ) CONN.RequestedVoltage = FAKE_PSU_VOLTAGE_V; 800cc72: 4b0b ldr r3, [pc, #44] @ (800cca0 ) fake_500_voltage_mode = 1u; 800cc74: 702a strb r2, [r5, #0] CONN.RequestedVoltage = FAKE_PSU_VOLTAGE_V; 800cc76: 741a strb r2, [r3, #16] 800cc78: 73dc strb r4, [r3, #15] CONN.WantedCurrent = FAKE_PSU_CURRENT_0P1A; 800cc7a: 76d8 strb r0, [r3, #27] 800cc7c: 7719 strb r1, [r3, #28] } 800cc7e: bdf8 pop {r3, r4, r5, r6, r7, pc} log_printf(LOG_WARN, 800cc80: 4622 mov r2, r4 } 800cc82: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} log_printf(LOG_WARN, 800cc86: 2005 movs r0, #5 800cc88: 490f ldr r1, [pc, #60] @ (800ccc8 ) 800cc8a: f7fd bc6d b.w 800a568 800cc8e: bf00 nop 800cc90: 20000ccd .word 0x20000ccd 800cc94: 20000cc8 .word 0x20000cc8 800cc98: 20000cce .word 0x20000cce 800cc9c: 20000ccf .word 0x20000ccf 800cca0: 200003b0 .word 0x200003b0 800cca4: 2000006a .word 0x2000006a 800cca8: 200009bd .word 0x200009bd 800ccac: 20000ccc .word 0x20000ccc 800ccb0: 20000cc6 .word 0x20000cc6 800ccb4: 20000cf8 .word 0x20000cf8 800ccb8: cccccccd .word 0xcccccccd 800ccbc: 20000d24 .word 0x20000d24 800ccc0: 20000cc5 .word 0x20000cc5 800ccc4: 0801793c .word 0x0801793c 800ccc8: 08017954 .word 0x08017954 0800cccc : ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len) { 800cccc: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} if (packet_len < 3u) { 800ccd0: 2902 cmp r1, #2 ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len) { 800ccd2: 460c mov r4, r1 800ccd4: 4605 mov r5, r0 800ccd6: b084 sub sp, #16 if (packet_len < 3u) { 800ccd8: d930 bls.n 800cd3c uint8_t cmd = packet[0]; uint16_t payload_len = (uint16_t)(packet_len - 3u); uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | (uint16_t)packet[packet_len - 1u] << 8; 800ccda: 1843 adds r3, r0, r1 uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800ccdc: f813 2c01 ldrb.w r2, [r3, #-1] 800cce0: f813 7c02 ldrb.w r7, [r3, #-2] uint16_t payload_len = (uint16_t)(packet_len - 3u); 800cce4: 1ece subs r6, r1, #3 uint16_t calculated_crc = crc16_ibm(packet, (uint16_t)(1u + payload_len)); 800cce6: 3902 subs r1, #2 800cce8: b289 uxth r1, r1 uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800ccea: ea47 2702 orr.w r7, r7, r2, lsl #8 uint8_t cmd = packet[0]; 800ccee: f890 8000 ldrb.w r8, [r0] uint16_t calculated_crc = crc16_ibm(packet, (uint16_t)(1u + payload_len)); 800ccf2: f7ff fd7f bl 800c7f4 if (received_crc != calculated_crc) { 800ccf6: 4287 cmp r7, r0 uint16_t payload_len = (uint16_t)(packet_len - 3u); 800ccf8: b2b6 uxth r6, r6 if (received_crc != calculated_crc) { 800ccfa: d112 bne.n 800cd22 cmd, (unsigned)packet_len, (unsigned)payload_len, (unsigned)received_crc, (unsigned)calculated_crc); return 0; } uint16_t expected_len = expected_payload_len(cmd); 800ccfc: 4640 mov r0, r8 800ccfe: f7ff ff2f bl 800cb60 if (expected_len == 0xFFFFu) { 800cd02: f64f 72ff movw r2, #65535 @ 0xffff 800cd06: 4290 cmp r0, r2 800cd08: d03a beq.n 800cd80 log_printf(LOG_WARN, "UART3 RX drop: unknown_cmd cmd=0x%02x total_len=%u payload_len=%u\n", cmd, (unsigned)packet_len, (unsigned)payload_len); return 0; } if (expected_len != payload_len) { 800cd0a: 4286 cmp r6, r0 800cd0c: d12a bne.n 800cd64 cmd, (unsigned)expected_len, (unsigned)payload_len, (unsigned)packet_len); return 0; } if (payload_len > 0) { apply_command(cmd, &packet[1], payload_len); 800cd0e: 4632 mov r2, r6 if (payload_len > 0) { 800cd10: b9fe cbnz r6, 800cd52 } else { apply_command(cmd, NULL, 0); 800cd12: 4631 mov r1, r6 800cd14: 4640 mov r0, r8 800cd16: f7ff ff2f bl 800cb78 } return 1; 800cd1a: 2001 movs r0, #1 } 800cd1c: b004 add sp, #16 800cd1e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} log_printf(LOG_ERR, 800cd22: 9002 str r0, [sp, #8] 800cd24: 4623 mov r3, r4 800cd26: 4642 mov r2, r8 800cd28: 2004 movs r0, #4 800cd2a: e9cd 6700 strd r6, r7, [sp] 800cd2e: 4918 ldr r1, [pc, #96] @ (800cd90 ) 800cd30: f7fd fc1a bl 800a568 return 0; 800cd34: 2000 movs r0, #0 } 800cd36: b004 add sp, #16 800cd38: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} if (packet_len == 0u) { 800cd3c: b1d9 cbz r1, 800cd76 } else if (packet_len == 1u) { 800cd3e: 2901 cmp r1, #1 log_printf(LOG_WARN, "UART3 RX drop: too_short len=1 b0=0x%02x\n", packet[0]); 800cd40: 7802 ldrb r2, [r0, #0] 800cd42: f04f 0005 mov.w r0, #5 } else if (packet_len == 1u) { 800cd46: d009 beq.n 800cd5c log_printf(LOG_WARN, "UART3 RX drop: too_short len=2 b0=0x%02x b1=0x%02x\n", 800cd48: 786b ldrb r3, [r5, #1] 800cd4a: 4912 ldr r1, [pc, #72] @ (800cd94 ) 800cd4c: f7fd fc0c bl 800a568 800cd50: e7f0 b.n 800cd34 apply_command(cmd, &packet[1], payload_len); 800cd52: 4640 mov r0, r8 800cd54: 1c69 adds r1, r5, #1 800cd56: f7ff ff0f bl 800cb78 800cd5a: e7de b.n 800cd1a log_printf(LOG_WARN, "UART3 RX drop: too_short len=1 b0=0x%02x\n", packet[0]); 800cd5c: 490e ldr r1, [pc, #56] @ (800cd98 ) 800cd5e: f7fd fc03 bl 800a568 800cd62: e7e7 b.n 800cd34 log_printf(LOG_ERR, 800cd64: 4603 mov r3, r0 800cd66: 4642 mov r2, r8 800cd68: e9cd 6400 strd r6, r4, [sp] 800cd6c: 490b ldr r1, [pc, #44] @ (800cd9c ) 800cd6e: 2004 movs r0, #4 800cd70: f7fd fbfa bl 800a568 return 0; 800cd74: e7de b.n 800cd34 log_printf(LOG_WARN, "UART3 RX drop: too_short len=0 (empty chunk)\n"); 800cd76: 490a ldr r1, [pc, #40] @ (800cda0 ) 800cd78: 2005 movs r0, #5 800cd7a: f7fd fbf5 bl 800a568 800cd7e: e7d9 b.n 800cd34 log_printf(LOG_WARN, 800cd80: 4623 mov r3, r4 800cd82: 4642 mov r2, r8 800cd84: 4907 ldr r1, [pc, #28] @ (800cda4 ) 800cd86: 9600 str r6, [sp, #0] 800cd88: 2005 movs r0, #5 800cd8a: f7fd fbed bl 800a568 return 0; 800cd8e: e7d1 b.n 800cd34 800cd90: 08017a44 .word 0x08017a44 800cd94: 08017a10 .word 0x08017a10 800cd98: 080179e4 .word 0x080179e4 800cd9c: 08017aec .word 0x08017aec 800cda0: 080179b4 .word 0x080179b4 800cda4: 08017aa8 .word 0x08017aa8 0800cda8 : static void CCS_UART3_Watchdog(void) { 800cda8: b580 push {r7, lr} 800cdaa: b082 sub sp, #8 800cdac: af00 add r7, sp, #0 const int32_t since_last_packet = (int32_t)(HAL_GetTick() - uart3_last_packet_tick); 800cdae: f001 fceb bl 800e788 800cdb2: 4602 mov r2, r0 800cdb4: 4b14 ldr r3, [pc, #80] @ (800ce08 ) 800cdb6: 681b ldr r3, [r3, #0] 800cdb8: 1ad3 subs r3, r2, r3 800cdba: 607b str r3, [r7, #4] const int32_t since_last_reinit = (int32_t)(HAL_GetTick() - uart3_last_reinit_tick); 800cdbc: f001 fce4 bl 800e788 800cdc0: 4602 mov r2, r0 800cdc2: 4b12 ldr r3, [pc, #72] @ (800ce0c ) 800cdc4: 681b ldr r3, [r3, #0] 800cdc6: 1ad3 subs r3, r2, r3 800cdc8: 603b str r3, [r7, #0] if ((since_last_packet >= (int32_t)UART3_REINIT_TIMEOUT_MS) && 800cdca: 687b ldr r3, [r7, #4] 800cdcc: f240 52db movw r2, #1499 @ 0x5db 800cdd0: 4293 cmp r3, r2 800cdd2: dd15 ble.n 800ce00 800cdd4: 683b ldr r3, [r7, #0] 800cdd6: f240 52db movw r2, #1499 @ 0x5db 800cdda: 4293 cmp r3, r2 800cddc: dd10 ble.n 800ce00 (since_last_reinit >= (int32_t)UART3_REINIT_TIMEOUT_MS) && (huart3.RxState == HAL_UART_STATE_READY)) { 800cdde: 4b0c ldr r3, [pc, #48] @ (800ce10 ) 800cde0: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800cde4: b2db uxtb r3, r3 (since_last_reinit >= (int32_t)UART3_REINIT_TIMEOUT_MS) && 800cde6: 2b20 cmp r3, #32 800cde8: d10a bne.n 800ce00 uart3_arm_rx_or_log("Watchdog"); 800cdea: 480a ldr r0, [pc, #40] @ (800ce14 ) 800cdec: f7ff f91a bl 800c024 CCS_LogUart3Error("UART3 watchdog rearm"); 800cdf0: 4809 ldr r0, [pc, #36] @ (800ce18 ) 800cdf2: f000 f813 bl 800ce1c uart3_last_reinit_tick = HAL_GetTick(); 800cdf6: f001 fcc7 bl 800e788 800cdfa: 4603 mov r3, r0 800cdfc: 4a03 ldr r2, [pc, #12] @ (800ce0c ) 800cdfe: 6013 str r3, [r2, #0] } } 800ce00: bf00 nop 800ce02: 3708 adds r7, #8 800ce04: 46bd mov sp, r7 800ce06: bd80 pop {r7, pc} 800ce08: 20000cd0 .word 0x20000cd0 800ce0c: 20000cd4 .word 0x20000cd4 800ce10: 20001344 .word 0x20001344 800ce14: 08017b44 .word 0x08017b44 800ce18: 08017b50 .word 0x08017b50 0800ce1c : static void CCS_LogUart3Error(const char *tag) { 800ce1c: b580 push {r7, lr} 800ce1e: b086 sub sp, #24 800ce20: af04 add r7, sp, #16 800ce22: 6078 str r0, [r7, #4] log_printf(LOG_ERR, "%s: err=0x%08lx g=%lu rx=%lu tx_busy=%u\n", tag, (unsigned long)HAL_UART_GetError(&huart3), 800ce24: 480d ldr r0, [pc, #52] @ (800ce5c ) 800ce26: f006 ff8a bl 8013d3e 800ce2a: 4603 mov r3, r0 (unsigned long)huart3.gState, 800ce2c: 4a0b ldr r2, [pc, #44] @ (800ce5c ) 800ce2e: f892 2041 ldrb.w r2, [r2, #65] @ 0x41 800ce32: b2d2 uxtb r2, r2 log_printf(LOG_ERR, "%s: err=0x%08lx g=%lu rx=%lu tx_busy=%u\n", 800ce34: 4611 mov r1, r2 (unsigned long)huart3.RxState, 800ce36: 4a09 ldr r2, [pc, #36] @ (800ce5c ) 800ce38: f892 2042 ldrb.w r2, [r2, #66] @ 0x42 800ce3c: b2d2 uxtb r2, r2 log_printf(LOG_ERR, "%s: err=0x%08lx g=%lu rx=%lu tx_busy=%u\n", 800ce3e: 4610 mov r0, r2 800ce40: 4a07 ldr r2, [pc, #28] @ (800ce60 ) 800ce42: 7812 ldrb r2, [r2, #0] 800ce44: 9202 str r2, [sp, #8] 800ce46: 9001 str r0, [sp, #4] 800ce48: 9100 str r1, [sp, #0] 800ce4a: 687a ldr r2, [r7, #4] 800ce4c: 4905 ldr r1, [pc, #20] @ (800ce64 ) 800ce4e: 2004 movs r0, #4 800ce50: f7fd fb8a bl 800a568 (unsigned)uart3_tx_busy); } 800ce54: bf00 nop 800ce56: 3708 adds r7, #8 800ce58: 46bd mov sp, r7 800ce5a: bd80 pop {r7, pc} 800ce5c: 20001344 .word 0x20001344 800ce60: 20000cc2 .word 0x20000cc2 800ce64: 08017b68 .word 0x08017b68 0800ce68 : .fw_version_major = 0, .fw_version_minor = 0, .fw_version_patch = 0, }; void ReadVersion(){ 800ce68: b480 push {r7} 800ce6a: af00 add r7, sp, #0 infoPacket.serialNumber = InfoBlock->serialNumber; 800ce6c: 4b0e ldr r3, [pc, #56] @ (800cea8 ) 800ce6e: 681b ldr r3, [r3, #0] 800ce70: 681b ldr r3, [r3, #0] 800ce72: b29a uxth r2, r3 800ce74: 4b0d ldr r3, [pc, #52] @ (800ceac ) 800ce76: 801a strh r2, [r3, #0] infoPacket.boardVersion = InfoBlock->boardVersion; 800ce78: 4b0b ldr r3, [pc, #44] @ (800cea8 ) 800ce7a: 681b ldr r3, [r3, #0] 800ce7c: 795a ldrb r2, [r3, #5] 800ce7e: 4b0b ldr r3, [pc, #44] @ (800ceac ) 800ce80: 709a strb r2, [r3, #2] infoPacket.stationType = InfoBlock->stationType; 800ce82: 4b09 ldr r3, [pc, #36] @ (800cea8 ) 800ce84: 681b ldr r3, [r3, #0] 800ce86: 791a ldrb r2, [r3, #4] 800ce88: 4b08 ldr r3, [pc, #32] @ (800ceac ) 800ce8a: 70da strb r2, [r3, #3] infoPacket.fw_version_major = FW_VERSION_MAJOR; 800ce8c: 4b07 ldr r3, [pc, #28] @ (800ceac ) 800ce8e: 2201 movs r2, #1 800ce90: 809a strh r2, [r3, #4] infoPacket.fw_version_minor = FW_VERSION_MINOR; 800ce92: 4b06 ldr r3, [pc, #24] @ (800ceac ) 800ce94: 2200 movs r2, #0 800ce96: 80da strh r2, [r3, #6] infoPacket.fw_version_patch = FW_VERSION_PATCH; 800ce98: 4b04 ldr r3, [pc, #16] @ (800ceac ) 800ce9a: 2213 movs r2, #19 800ce9c: 811a strh r2, [r3, #8] } 800ce9e: bf00 nop 800cea0: 46bd mov sp, r7 800cea2: bc80 pop {r7} 800cea4: 4770 bx lr 800cea6: bf00 nop 800cea8: 20000000 .word 0x20000000 800ceac: 200011c4 .word 0x200011c4 0800ceb0 : // Внешняя функция обработки команд (определена в serial_handler.c) extern void SC_CommandHandler(ReceivedCommand_t* cmd); void SC_Init() { 800ceb0: b580 push {r7, lr} 800ceb2: af00 add r7, sp, #0 // Обнуляем структуру memset(&serial_control, 0, sizeof(SerialControl_t)); 800ceb4: f44f 7204 mov.w r2, #528 @ 0x210 800ceb8: 2100 movs r1, #0 800ceba: 480d ldr r0, [pc, #52] @ (800cef0 ) 800cebc: f008 f91e bl 80150fc memset(&serial_iso, 0, sizeof(serial_iso)); 800cec0: f44f 7204 mov.w r2, #528 @ 0x210 800cec4: 2100 movs r1, #0 800cec6: 480b ldr r0, [pc, #44] @ (800cef4 ) 800cec8: f008 f918 bl 80150fc sc_uart2_timed_out = 0; 800cecc: 4b0a ldr r3, [pc, #40] @ (800cef8 ) 800cece: 2200 movs r2, #0 800ced0: 701a strb r2, [r3, #0] sc_uart2_last_packet_tick = HAL_GetTick(); 800ced2: f001 fc59 bl 800e788 800ced6: 4603 mov r3, r0 800ced8: 4a08 ldr r2, [pc, #32] @ (800cefc ) 800ceda: 6013 str r3, [r2, #0] sc_uart2_last_recover_tick = sc_uart2_last_packet_tick; 800cedc: 4b07 ldr r3, [pc, #28] @ (800cefc ) 800cede: 681b ldr r3, [r3, #0] 800cee0: 4a07 ldr r2, [pc, #28] @ (800cf00 ) 800cee2: 6013 str r3, [r2, #0] SC_ArmUart2RxDma(); 800cee4: f000 fa14 bl 800d310 SC_ArmUart5RxDma(); 800cee8: f000 fa36 bl 800d358 } 800ceec: bf00 nop 800ceee: bd80 pop {r7, pc} 800cef0: 20000d40 .word 0x20000d40 800cef4: 20000f50 .word 0x20000f50 800cef8: 20001161 .word 0x20001161 800cefc: 20001164 .word 0x20001164 800cf00: 20001168 .word 0x20001168 0800cf04 : void SC_Task() { 800cf04: b580 push {r7, lr} 800cf06: af00 add r7, sp, #0 static uint32_t tick; if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800cf08: f001 fc3e bl 800e788 800cf0c: 4602 mov r2, r0 800cf0e: 4b21 ldr r3, [pc, #132] @ (800cf94 ) 800cf10: 681b ldr r3, [r3, #0] 800cf12: 1ad3 subs r3, r2, r3 800cf14: 2b00 cmp r3, #0 800cf16: dd3b ble.n 800cf90 tick = HAL_GetTick(); 800cf18: f001 fc36 bl 800e788 800cf1c: 4603 mov r3, r0 800cf1e: 4a1d ldr r2, [pc, #116] @ (800cf94 ) 800cf20: 6013 str r3, [r2, #0] SC_UART2_Watchdog(); 800cf22: f000 f9ad bl 800d280 // Запуск приема в режиме DMA + idle SC_ArmUart2RxDma(); 800cf26: f000 f9f3 bl 800d310 SC_ArmUart5RxDma(); 800cf2a: f000 fa15 bl 800d358 // Проверка таймаута отправки пакета (больше 100 мс) if (huart2.gState == HAL_UART_STATE_BUSY_TX && serial_control.tx_tick != 0) { 800cf2e: 4b1a ldr r3, [pc, #104] @ (800cf98 ) 800cf30: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800cf34: b2db uxtb r3, r3 800cf36: 2b21 cmp r3, #33 @ 0x21 800cf38: d114 bne.n 800cf64 800cf3a: 4b18 ldr r3, [pc, #96] @ (800cf9c ) 800cf3c: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800cf40: 2b00 cmp r3, #0 800cf42: d00f beq.n 800cf64 if ((int32_t)(HAL_GetTick() - serial_control.tx_tick) > 100) { 800cf44: f001 fc20 bl 800e788 800cf48: 4602 mov r2, r0 800cf4a: 4b14 ldr r3, [pc, #80] @ (800cf9c ) 800cf4c: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800cf50: 1ad3 subs r3, r2, r3 800cf52: 2b64 cmp r3, #100 @ 0x64 800cf54: dd06 ble.n 800cf64 // Таймаут: принудительно сбрасываем передачу (void)HAL_UART_AbortTransmit(&huart2); 800cf56: 4810 ldr r0, [pc, #64] @ (800cf98 ) 800cf58: f006 fb38 bl 80135cc serial_control.tx_tick = 0; // Сбрасываем tick 800cf5c: 4b0f ldr r3, [pc, #60] @ (800cf9c ) 800cf5e: 2200 movs r2, #0 800cf60: f8c3 220c str.w r2, [r3, #524] @ 0x20c } } // Проверка наличия принятой команды для обработки if (serial_control.command_ready && (huart2.gState != HAL_UART_STATE_BUSY_TX)) { 800cf64: 4b0d ldr r3, [pc, #52] @ (800cf9c ) 800cf66: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800cf6a: b2db uxtb r3, r3 800cf6c: 2b00 cmp r3, #0 800cf6e: d010 beq.n 800cf92 800cf70: 4b09 ldr r3, [pc, #36] @ (800cf98 ) 800cf72: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800cf76: b2db uxtb r3, r3 800cf78: 2b21 cmp r3, #33 @ 0x21 800cf7a: d00a beq.n 800cf92 // HAL_Delay(2); SC_CommandHandler((ReceivedCommand_t*)&serial_control.received_command); 800cf7c: 4808 ldr r0, [pc, #32] @ (800cfa0 ) 800cf7e: f000 fa87 bl 800d490 serial_control.command_ready = 0; // Сбрасываем флаг 800cf82: 4b06 ldr r3, [pc, #24] @ (800cf9c ) 800cf84: 2200 movs r2, #0 800cf86: f883 2208 strb.w r2, [r3, #520] @ 0x208 SC_ArmUart2RxDma(); 800cf8a: f000 f9c1 bl 800d310 800cf8e: e000 b.n 800cf92 if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800cf90: bf00 nop } } 800cf92: bd80 pop {r7, pc} 800cf94: 200011d0 .word 0x200011d0 800cf98: 200012fc .word 0x200012fc 800cf9c: 20000d40 .word 0x20000d40 800cfa0: 20000f40 .word 0x20000f40 0800cfa4 : ISR_FAST void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { if (huart->Instance == huart2.Instance) { 800cfa4: 4b2e ldr r3, [pc, #184] @ (800d060 ) ISR_FAST void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800cfa6: b570 push {r4, r5, r6, lr} if (huart->Instance == huart2.Instance) { 800cfa8: 681a ldr r2, [r3, #0] 800cfaa: 6803 ldr r3, [r0, #0] ISR_FAST void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800cfac: 460c mov r4, r1 if (huart->Instance == huart2.Instance) { 800cfae: 4293 cmp r3, r2 800cfb0: d019 beq.n 800cfe6 log_printf(LOG_WARN, "UART2 RX invalid packet len=%u\n", (unsigned)Size); SC_SendPacket(NULL, 0, RESP_INVALID); } g_sc_command_source = SC_SOURCE_UART2; SC_ArmUart2RxDma(); } else if (huart->Instance == huart5.Instance) { 800cfb2: 4a2c ldr r2, [pc, #176] @ (800d064 ) 800cfb4: 6812 ldr r2, [r2, #0] 800cfb6: 4293 cmp r3, r2 800cfb8: d004 beq.n 800cfc4 SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); } else { log_printf(LOG_WARN, "UART5 RX invalid packet len=%u\n", (unsigned)Size); } SC_ArmUart5RxDma(); } else if (huart->Instance == huart3.Instance) { 800cfba: 4a2b ldr r2, [pc, #172] @ (800d068 ) 800cfbc: 6812 ldr r2, [r2, #0] 800cfbe: 4293 cmp r3, r2 800cfc0: d04a beq.n 800d058 CCS_RxEventCallback(huart, Size); } } 800cfc2: bd70 pop {r4, r5, r6, pc} if (Size == 0u) { 800cfc4: b399 cbz r1, 800d02e if (process_received_packet(&serial_iso, serial_iso.rx_buffer, Size)) { 800cfc6: 4929 ldr r1, [pc, #164] @ (800d06c ) 800cfc8: 4622 mov r2, r4 800cfca: f5a1 7080 sub.w r0, r1, #256 @ 0x100 800cfce: f000 f949 bl 800d264 800cfd2: bb10 cbnz r0, 800d01a log_printf(LOG_WARN, "UART5 RX invalid packet len=%u\n", (unsigned)Size); 800cfd4: 4622 mov r2, r4 800cfd6: 2005 movs r0, #5 800cfd8: 4925 ldr r1, [pc, #148] @ (800d070 ) 800cfda: f7fd fac5 bl 800a568 } 800cfde: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} SC_ArmUart5RxDma(); 800cfe2: f000 b9b9 b.w 800d358 if (Size == 0u) { 800cfe6: b391 cbz r1, 800d04e sc_uart2_last_packet_tick = HAL_GetTick(); 800cfe8: f001 fbce bl 800e788 sc_uart2_timed_out = 0; 800cfec: 2200 movs r2, #0 800cfee: 4b21 ldr r3, [pc, #132] @ (800d074 ) if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800cff0: 4921 ldr r1, [pc, #132] @ (800d078 ) sc_uart2_timed_out = 0; 800cff2: 701a strb r2, [r3, #0] sc_uart2_last_packet_tick = HAL_GetTick(); 800cff4: 4603 mov r3, r0 sc_uart2_last_recover_tick = sc_uart2_last_packet_tick; 800cff6: 4d21 ldr r5, [pc, #132] @ (800d07c ) sc_uart2_last_packet_tick = HAL_GetTick(); 800cff8: 4e21 ldr r6, [pc, #132] @ (800d080 ) if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800cffa: 4622 mov r2, r4 800cffc: f5a1 7080 sub.w r0, r1, #256 @ 0x100 sc_uart2_last_recover_tick = sc_uart2_last_packet_tick; 800d000: 602b str r3, [r5, #0] sc_uart2_last_packet_tick = HAL_GetTick(); 800d002: 6033 str r3, [r6, #0] if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800d004: f000 f92e bl 800d264 800d008: 4605 mov r5, r0 800d00a: b1a8 cbz r0, 800d038 g_sc_command_source = SC_SOURCE_UART2; 800d00c: 2200 movs r2, #0 800d00e: 4b1d ldr r3, [pc, #116] @ (800d084 ) 800d010: 701a strb r2, [r3, #0] } 800d012: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} SC_ArmUart2RxDma(); 800d016: f000 b97b b.w 800d310 g_sc_command_source = SC_SOURCE_UART5; 800d01a: 2201 movs r2, #1 800d01c: 4b19 ldr r3, [pc, #100] @ (800d084 ) SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); 800d01e: 481a ldr r0, [pc, #104] @ (800d088 ) g_sc_command_source = SC_SOURCE_UART5; 800d020: 701a strb r2, [r3, #0] SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); 800d022: f000 fa35 bl 800d490 } 800d026: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} SC_ArmUart5RxDma(); 800d02a: f000 b995 b.w 800d358 log_printf(LOG_WARN, "UART5 RX idle event with zero size\n"); 800d02e: 4917 ldr r1, [pc, #92] @ (800d08c ) 800d030: 2005 movs r0, #5 800d032: f7fd fa99 bl 800a568 800d036: e7c6 b.n 800cfc6 log_printf(LOG_WARN, "UART2 RX invalid packet len=%u\n", (unsigned)Size); 800d038: 4622 mov r2, r4 800d03a: 4915 ldr r1, [pc, #84] @ (800d090 ) 800d03c: 2005 movs r0, #5 800d03e: f7fd fa93 bl 800a568 SC_SendPacket(NULL, 0, RESP_INVALID); 800d042: 2214 movs r2, #20 800d044: 4629 mov r1, r5 800d046: 4628 mov r0, r5 800d048: f000 f8b6 bl 800d1b8 800d04c: e7de b.n 800d00c log_printf(LOG_WARN, "UART2 RX idle event with zero size\n"); 800d04e: 4911 ldr r1, [pc, #68] @ (800d094 ) 800d050: 2005 movs r0, #5 800d052: f7fd fa89 bl 800a568 800d056: e7c7 b.n 800cfe8 } 800d058: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} CCS_RxEventCallback(huart, Size); 800d05c: f7ff b812 b.w 800c084 800d060: 200012fc .word 0x200012fc 800d064: 2000126c .word 0x2000126c 800d068: 20001344 .word 0x20001344 800d06c: 20001050 .word 0x20001050 800d070: 08017bfc .word 0x08017bfc 800d074: 20001161 .word 0x20001161 800d078: 20000e40 .word 0x20000e40 800d07c: 20001168 .word 0x20001168 800d080: 20001164 .word 0x20001164 800d084: 20001160 .word 0x20001160 800d088: 20001150 .word 0x20001150 800d08c: 08017bd8 .word 0x08017bd8 800d090: 08017bb8 .word 0x08017bb8 800d094: 08017b94 .word 0x08017b94 0800d098 : ISR_FAST void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { if (huart->Instance == huart2.Instance) { 800d098: 4b08 ldr r3, [pc, #32] @ (800d0bc ) 800d09a: 681a ldr r2, [r3, #0] 800d09c: 6803 ldr r3, [r0, #0] 800d09e: 4293 cmp r3, r2 800d0a0: d004 beq.n 800d0ac serial_control.tx_tick = 0; } else if (huart->Instance == huart3.Instance) { 800d0a2: 4a07 ldr r2, [pc, #28] @ (800d0c0 ) 800d0a4: 6812 ldr r2, [r2, #0] 800d0a6: 4293 cmp r3, r2 800d0a8: d005 beq.n 800d0b6 CCS_TxCpltCallback(huart); } } 800d0aa: 4770 bx lr serial_control.tx_tick = 0; 800d0ac: 2200 movs r2, #0 800d0ae: 4b05 ldr r3, [pc, #20] @ (800d0c4 ) 800d0b0: f8c3 220c str.w r2, [r3, #524] @ 0x20c 800d0b4: 4770 bx lr CCS_TxCpltCallback(huart); 800d0b6: f7ff b88f b.w 800c1d8 800d0ba: bf00 nop 800d0bc: 200012fc .word 0x200012fc 800d0c0: 20001344 .word 0x20001344 800d0c4: 20000d40 .word 0x20000d40 0800d0c8 : // Полностью программная реализация CRC-32 (полином CRC32_POLYNOMIAL, порядок little-endian) ISR_FAST static uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { uint32_t crc = 0xFFFFFFFFu; for (uint16_t i = 0; i < length; i++) { 800d0c8: b3c9 cbz r1, 800d13e uint32_t crc = 0xFFFFFFFFu; 800d0ca: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff ISR_FAST static uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { 800d0ce: b500 push {lr} crc ^= data[i]; for (uint8_t bit = 0; bit < 8; bit++) { if (crc & 0x1u) { 800d0d0: 4a1c ldr r2, [pc, #112] @ (800d144 ) 800d0d2: 4401 add r1, r0 crc ^= data[i]; 800d0d4: f810 eb01 ldrb.w lr, [r0], #1 800d0d8: ea8e 0e03 eor.w lr, lr, r3 if (crc & 0x1u) { 800d0dc: f34e 0300 sbfx r3, lr, #0, #1 800d0e0: f34e 0c40 sbfx ip, lr, #1, #1 800d0e4: 4013 ands r3, r2 800d0e6: ea83 035e eor.w r3, r3, lr, lsr #1 800d0ea: ea0c 0c02 and.w ip, ip, r2 800d0ee: ea8c 0c53 eor.w ip, ip, r3, lsr #1 800d0f2: f343 0340 sbfx r3, r3, #1, #1 800d0f6: f34c 0e40 sbfx lr, ip, #1, #1 800d0fa: 4013 ands r3, r2 800d0fc: ea83 035c eor.w r3, r3, ip, lsr #1 800d100: ea0e 0e02 and.w lr, lr, r2 800d104: ea8e 0e53 eor.w lr, lr, r3, lsr #1 800d108: f343 0340 sbfx r3, r3, #1, #1 800d10c: f34e 0c40 sbfx ip, lr, #1, #1 800d110: 4013 ands r3, r2 800d112: ea83 035e eor.w r3, r3, lr, lsr #1 800d116: ea0c 0c02 and.w ip, ip, r2 800d11a: ea8c 0c53 eor.w ip, ip, r3, lsr #1 800d11e: f343 0340 sbfx r3, r3, #1, #1 800d122: 4013 ands r3, r2 800d124: f34c 0e40 sbfx lr, ip, #1, #1 800d128: ea83 035c eor.w r3, r3, ip, lsr #1 for (uint16_t i = 0; i < length; i++) { 800d12c: 4281 cmp r1, r0 if (crc & 0x1u) { 800d12e: ea0e 0c02 and.w ip, lr, r2 800d132: ea8c 0353 eor.w r3, ip, r3, lsr #1 for (uint16_t i = 0; i < length; i++) { 800d136: d1cd bne.n 800d0d4 crc >>= 1; } } } return crc ^ 0xFFFFFFFFu; 800d138: 43d8 mvns r0, r3 } 800d13a: f85d fb04 ldr.w pc, [sp], #4 for (uint16_t i = 0; i < length; i++) { 800d13e: 4608 mov r0, r1 } 800d140: 4770 bx lr 800d142: bf00 nop 800d144: edb88320 .word 0xedb88320 0800d148 : ISR_FAST static uint16_t encode_packet(const uint8_t* payload, uint16_t payload_len, uint8_t* output, uint8_t response_code) { 800d148: b570 push {r4, r5, r6, lr} 800d14a: 4615 mov r5, r2 uint16_t out_index = 0; output[out_index++] = response_code; 800d14c: 7013 strb r3, [r2, #0] if (payload != NULL) { 800d14e: b360 cbz r0, 800d1aa // Просто копируем полезную нагрузку без какого‑либо экранирования for (uint16_t i = 0; i < payload_len; i++) { 800d150: b359 cbz r1, 800d1aa output[out_index++] = payload[i]; 800d152: 4694 mov ip, r2 800d154: 2302 movs r3, #2 800d156: 7802 ldrb r2, [r0, #0] 800d158: 1e4c subs r4, r1, #1 800d15a: b2a4 uxth r4, r4 800d15c: 441c add r4, r3 800d15e: f80c 2f01 strb.w r2, [ip, #1]! // Проверка переполнения if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800d162: e005 b.n 800d170 output[out_index++] = payload[i]; 800d164: f810 1f01 ldrb.w r1, [r0, #1]! if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800d168: 2bfb cmp r3, #251 @ 0xfb output[out_index++] = payload[i]; 800d16a: f80c 1f01 strb.w r1, [ip, #1]! if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800d16e: d020 beq.n 800d1b2 for (uint16_t i = 0; i < payload_len; i++) { 800d170: 42a3 cmp r3, r4 if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800d172: f103 0301 add.w r3, r3, #1 for (uint16_t i = 0; i < payload_len; i++) { 800d176: d1f5 bne.n 800d164 800d178: b2a1 uxth r1, r4 output[out_index++] = payload[i]; 800d17a: 1c4e adds r6, r1, #1 800d17c: b2b6 uxth r6, r6 } } } // Вычисляем CRC для всего содержимого (код ответа + полезная нагрузка) uint32_t crc = calculate_crc32(output, out_index); 800d17e: 4628 mov r0, r5 800d180: f7ff ffa2 bl 800d0c8 800d184: 4603 mov r3, r0 uint8_t* crc_bytes = (uint8_t*)&crc; // Добавляем CRC без экранирования for (int i = 0; i < 4; i++) { output[out_index++] = crc_bytes[i]; 800d186: 1c71 adds r1, r6, #1 800d188: 1cb2 adds r2, r6, #2 800d18a: 552b strb r3, [r5, r4] 800d18c: f3c3 2c07 ubfx ip, r3, #8, #8 800d190: f3c3 4407 ubfx r4, r3, #16, #8 800d194: b289 uxth r1, r1 800d196: b292 uxth r2, r2 800d198: f3c3 6307 ubfx r3, r3, #24, #8 800d19c: f805 c006 strb.w ip, [r5, r6] 800d1a0: 1cf0 adds r0, r6, #3 800d1a2: 546c strb r4, [r5, r1] 800d1a4: 54ab strb r3, [r5, r2] 800d1a6: b280 uxth r0, r0 return 0; } } return out_index; } 800d1a8: bd70 pop {r4, r5, r6, pc} for (uint16_t i = 0; i < payload_len; i++) { 800d1aa: 2401 movs r4, #1 800d1ac: 2602 movs r6, #2 output[out_index++] = response_code; 800d1ae: 4621 mov r1, r4 800d1b0: e7e5 b.n 800d17e return 0; 800d1b2: 2000 movs r0, #0 } 800d1b4: bd70 pop {r4, r5, r6, pc} 800d1b6: bf00 nop 0800d1b8 : ISR_FAST void SC_SendPacket(const uint8_t* payload, uint16_t payload_len, uint8_t response_code) { 800d1b8: b538 push {r3, r4, r5, lr} 800d1ba: 4613 mov r3, r2 uint16_t packet_len = encode_packet(payload, payload_len, serial_control.tx_buffer, response_code); 800d1bc: 4a11 ldr r2, [pc, #68] @ (800d204 ) 800d1be: f7ff ffc3 bl 800d148 if (packet_len > 0) { 800d1c2: b180 cbz r0, 800d1e6 if (huart2.gState != HAL_UART_STATE_READY) { 800d1c4: 4604 mov r4, r0 800d1c6: 4810 ldr r0, [pc, #64] @ (800d208 ) 800d1c8: f890 3041 ldrb.w r3, [r0, #65] @ 0x41 800d1cc: 2b20 cmp r3, #32 800d1ce: d10b bne.n 800d1e8 (void)HAL_UART_AbortTransmit(&huart2); log_printf(LOG_WARN, "UART2 TX busy, abort transmit before resend\n"); } if (HAL_UART_Transmit_DMA(&huart2, serial_control.tx_buffer, packet_len) != HAL_OK) { 800d1d0: 4d0c ldr r5, [pc, #48] @ (800d204 ) 800d1d2: 4622 mov r2, r4 800d1d4: 4629 mov r1, r5 800d1d6: 480c ldr r0, [pc, #48] @ (800d208 ) 800d1d8: f006 f8d2 bl 8013380 800d1dc: b958 cbnz r0, 800d1f6 SC_LogUartError("UART2 TX DMA start failed", &huart2); return; } serial_control.tx_tick = HAL_GetTick(); 800d1de: f001 fad3 bl 800e788 800d1e2: f8c5 020c str.w r0, [r5, #524] @ 0x20c } } 800d1e6: bd38 pop {r3, r4, r5, pc} (void)HAL_UART_AbortTransmit(&huart2); 800d1e8: f006 f9f0 bl 80135cc log_printf(LOG_WARN, "UART2 TX busy, abort transmit before resend\n"); 800d1ec: 4907 ldr r1, [pc, #28] @ (800d20c ) 800d1ee: 2005 movs r0, #5 800d1f0: f7fd f9ba bl 800a568 800d1f4: e7ec b.n 800d1d0 SC_LogUartError("UART2 TX DMA start failed", &huart2); 800d1f6: 4904 ldr r1, [pc, #16] @ (800d208 ) 800d1f8: 4805 ldr r0, [pc, #20] @ (800d210 ) } 800d1fa: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} SC_LogUartError("UART2 TX DMA start failed", &huart2); 800d1fe: f000 b905 b.w 800d40c 800d202: bf00 nop 800d204: 20000d40 .word 0x20000d40 800d208: 200012fc .word 0x200012fc 800d20c: 08017c1c .word 0x08017c1c 800d210: 08017c4c .word 0x08017c4c 0800d214 : ISR_FAST static uint8_t parse_packet(const uint8_t* packet_data, uint16_t packet_len, ReceivedCommand_t* out_cmd) { 800d214: e92d 4178 stmdb sp!, {r3, r4, r5, r6, r8, lr} // }else{ // test_crc_invalid = 5; // } // Минимальный размер: 1 байт команды + 4 байта CRC if (packet_len < 5) return 0; 800d218: 1f4b subs r3, r1, #5 800d21a: 2bfb cmp r3, #251 @ 0xfb 800d21c: d813 bhi.n 800d246 if (packet_len > MAX_RX_BUFFER_SIZE) return 0; uint16_t payload_length = packet_len - 4; 800d21e: 3904 subs r1, #4 800d220: b28c uxth r4, r1 // Извлекаем принятую CRC (последние 4 байта, little-endian) uint32_t received_checksum = ((uint32_t)packet_data[payload_length] << 0) | ((uint32_t)packet_data[payload_length + 1] << 8) | 800d222: 1903 adds r3, r0, r4 ((uint32_t)packet_data[payload_length + 2] << 16) | 800d224: 789d ldrb r5, [r3, #2] 800d226: 4690 mov r8, r2 ((uint32_t)packet_data[payload_length + 1] << 8) | 800d228: 785a ldrb r2, [r3, #1] ((uint32_t)packet_data[payload_length + 2] << 16) | 800d22a: 042d lsls r5, r5, #16 ((uint32_t)packet_data[payload_length + 1] << 8) | 800d22c: ea45 2502 orr.w r5, r5, r2, lsl #8 ((uint32_t)packet_data[payload_length] << 0) | 800d230: 5d02 ldrb r2, [r0, r4] ((uint32_t)packet_data[payload_length + 3] << 24); 800d232: 78db ldrb r3, [r3, #3] ((uint32_t)packet_data[payload_length + 1] << 8) | 800d234: 4315 orrs r5, r2 // Вычисляем CRC для полезной нагрузки uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); 800d236: 4621 mov r1, r4 uint32_t received_checksum = 800d238: ea45 6503 orr.w r5, r5, r3, lsl #24 uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); 800d23c: 4606 mov r6, r0 800d23e: f7ff ff43 bl 800d0c8 if (received_checksum != calculated_checksum) return 0; // CRC не совпадает 800d242: 4285 cmp r5, r0 800d244: d002 beq.n 800d24c if (packet_len < 5) return 0; 800d246: 2000 movs r0, #0 out_cmd->argument = (void *)&packet_data[1]; out_cmd->command = packet_data[0]; out_cmd->argument_length = (uint8_t)(payload_length - 1); return 1; } 800d248: e8bd 8178 ldmia.w sp!, {r3, r4, r5, r6, r8, pc} out_cmd->argument = (void *)&packet_data[1]; 800d24c: 1c73 adds r3, r6, #1 800d24e: f8c8 3004 str.w r3, [r8, #4] out_cmd->command = packet_data[0]; 800d252: 7833 ldrb r3, [r6, #0] out_cmd->argument_length = (uint8_t)(payload_length - 1); 800d254: 3c01 subs r4, #1 out_cmd->command = packet_data[0]; 800d256: f888 3000 strb.w r3, [r8] out_cmd->argument_length = (uint8_t)(payload_length - 1); 800d25a: f888 4001 strb.w r4, [r8, #1] return 1; 800d25e: 2001 movs r0, #1 } 800d260: e8bd 8178 ldmia.w sp!, {r3, r4, r5, r6, r8, pc} 0800d264 : ISR_FAST static uint8_t process_received_packet(SerialControl_t *ctx, const uint8_t* packet_data, uint16_t packet_len) { 800d264: b510 push {r4, lr} 800d266: 4604 mov r4, r0 if (!parse_packet(packet_data, packet_len, (ReceivedCommand_t *)&ctx->received_command)) { 800d268: 4608 mov r0, r1 800d26a: 4611 mov r1, r2 800d26c: f504 7200 add.w r2, r4, #512 @ 0x200 800d270: f7ff ffd0 bl 800d214 800d274: b118 cbz r0, 800d27e return 0; } ctx->command_ready = 1; 800d276: 2301 movs r3, #1 return 1; 800d278: 4618 mov r0, r3 ctx->command_ready = 1; 800d27a: f884 3208 strb.w r3, [r4, #520] @ 0x208 } 800d27e: bd10 pop {r4, pc} 0800d280 : static void SC_UART2_Watchdog(void) { 800d280: b580 push {r7, lr} 800d282: b082 sub sp, #8 800d284: af00 add r7, sp, #0 const uint32_t now = HAL_GetTick(); 800d286: f001 fa7f bl 800e788 800d28a: 6078 str r0, [r7, #4] const int32_t since_last_packet = (int32_t)(now - sc_uart2_last_packet_tick); 800d28c: 4b1a ldr r3, [pc, #104] @ (800d2f8 ) 800d28e: 681b ldr r3, [r3, #0] 800d290: 687a ldr r2, [r7, #4] 800d292: 1ad3 subs r3, r2, r3 800d294: 603b str r3, [r7, #0] if (since_last_packet >= (int32_t)SC_UART2_PACKET_TIMEOUT_MS) { 800d296: 683b ldr r3, [r7, #0] 800d298: f241 3287 movw r2, #4999 @ 0x1387 800d29c: 4293 cmp r3, r2 800d29e: dd12 ble.n 800d2c6 if (sc_uart2_timed_out == 0u) { 800d2a0: 4b16 ldr r3, [pc, #88] @ (800d2fc ) 800d2a2: 781b ldrb r3, [r3, #0] 800d2a4: b2db uxtb r3, r3 800d2a6: 2b00 cmp r3, #0 800d2a8: d109 bne.n 800d2be serial_control.command_ready = 0; 800d2aa: 4b15 ldr r3, [pc, #84] @ (800d300 ) 800d2ac: 2200 movs r2, #0 800d2ae: f883 2208 strb.w r2, [r3, #520] @ 0x208 log_printf(LOG_WARN, "UART2 RX packet timeout (%u ms)\n", (unsigned)SC_UART2_PACKET_TIMEOUT_MS); 800d2b2: f241 3288 movw r2, #5000 @ 0x1388 800d2b6: 4913 ldr r1, [pc, #76] @ (800d304 ) 800d2b8: 2005 movs r0, #5 800d2ba: f7fd f955 bl 800a568 } sc_uart2_timed_out = 1; 800d2be: 4b0f ldr r3, [pc, #60] @ (800d2fc ) 800d2c0: 2201 movs r2, #1 800d2c2: 701a strb r2, [r3, #0] 800d2c4: e002 b.n 800d2cc } else { sc_uart2_timed_out = 0; 800d2c6: 4b0d ldr r3, [pc, #52] @ (800d2fc ) 800d2c8: 2200 movs r2, #0 800d2ca: 701a strb r2, [r3, #0] } if ((huart2.RxState == HAL_UART_STATE_READY) && 800d2cc: 4b0e ldr r3, [pc, #56] @ (800d308 ) 800d2ce: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800d2d2: b2db uxtb r3, r3 800d2d4: 2b20 cmp r3, #32 800d2d6: d10a bne.n 800d2ee ((int32_t)(now - sc_uart2_last_recover_tick) >= (int32_t)SC_UART2_RECOVER_GUARD_MS)) { 800d2d8: 4b0c ldr r3, [pc, #48] @ (800d30c ) 800d2da: 681b ldr r3, [r3, #0] 800d2dc: 687a ldr r2, [r7, #4] 800d2de: 1ad3 subs r3, r2, r3 if ((huart2.RxState == HAL_UART_STATE_READY) && 800d2e0: 2bc7 cmp r3, #199 @ 0xc7 800d2e2: dd04 ble.n 800d2ee SC_ArmUart2RxDma(); 800d2e4: f000 f814 bl 800d310 sc_uart2_last_recover_tick = now; 800d2e8: 4a08 ldr r2, [pc, #32] @ (800d30c ) 800d2ea: 687b ldr r3, [r7, #4] 800d2ec: 6013 str r3, [r2, #0] } } 800d2ee: bf00 nop 800d2f0: 3708 adds r7, #8 800d2f2: 46bd mov sp, r7 800d2f4: bd80 pop {r7, pc} 800d2f6: bf00 nop 800d2f8: 20001164 .word 0x20001164 800d2fc: 20001161 .word 0x20001161 800d300: 20000d40 .word 0x20000d40 800d304: 08017c68 .word 0x08017c68 800d308: 200012fc .word 0x200012fc 800d30c: 20001168 .word 0x20001168 0800d310 : static void SC_ArmUart2RxDma(void) { 800d310: b580 push {r7, lr} 800d312: af00 add r7, sp, #0 if ((huart2.RxState == HAL_UART_STATE_READY) && (serial_control.command_ready == 0)) { 800d314: 4b0c ldr r3, [pc, #48] @ (800d348 ) 800d316: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800d31a: b2db uxtb r3, r3 800d31c: 2b20 cmp r3, #32 800d31e: d111 bne.n 800d344 800d320: 4b0a ldr r3, [pc, #40] @ (800d34c ) 800d322: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800d326: b2db uxtb r3, r3 800d328: 2b00 cmp r3, #0 800d32a: d10b bne.n 800d344 if (HAL_UARTEx_ReceiveToIdle_DMA(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1) != HAL_OK) { 800d32c: 22ff movs r2, #255 @ 0xff 800d32e: 4908 ldr r1, [pc, #32] @ (800d350 ) 800d330: 4805 ldr r0, [pc, #20] @ (800d348 ) 800d332: f006 f8f2 bl 801351a 800d336: 4603 mov r3, r0 800d338: 2b00 cmp r3, #0 800d33a: d003 beq.n 800d344 SC_LogUartError("UART2 RX DMA arm failed", &huart2); 800d33c: 4902 ldr r1, [pc, #8] @ (800d348 ) 800d33e: 4805 ldr r0, [pc, #20] @ (800d354 ) 800d340: f000 f864 bl 800d40c } } } 800d344: bf00 nop 800d346: bd80 pop {r7, pc} 800d348: 200012fc .word 0x200012fc 800d34c: 20000d40 .word 0x20000d40 800d350: 20000e40 .word 0x20000e40 800d354: 08017c8c .word 0x08017c8c 0800d358 : static void SC_ArmUart5RxDma(void) { 800d358: b580 push {r7, lr} 800d35a: af00 add r7, sp, #0 if (huart5.RxState == HAL_UART_STATE_READY) { 800d35c: 4b0a ldr r3, [pc, #40] @ (800d388 ) 800d35e: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800d362: b2db uxtb r3, r3 800d364: 2b20 cmp r3, #32 800d366: d10d bne.n 800d384 if (HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1) == HAL_OK) { 800d368: 22ff movs r2, #255 @ 0xff 800d36a: 4908 ldr r1, [pc, #32] @ (800d38c ) 800d36c: 4806 ldr r0, [pc, #24] @ (800d388 ) 800d36e: f006 f877 bl 8013460 800d372: 4603 mov r3, r0 800d374: 2b00 cmp r3, #0 800d376: d004 beq.n 800d382 return; } SC_LogUartError("UART5 RX IT arm failed", &huart5); 800d378: 4903 ldr r1, [pc, #12] @ (800d388 ) 800d37a: 4805 ldr r0, [pc, #20] @ (800d390 ) 800d37c: f000 f846 bl 800d40c 800d380: e000 b.n 800d384 return; 800d382: bf00 nop } } 800d384: bd80 pop {r7, pc} 800d386: bf00 nop 800d388: 2000126c .word 0x2000126c 800d38c: 20001050 .word 0x20001050 800d390: 08017ca4 .word 0x08017ca4 0800d394 : void SC_RecoverUartDma(UART_HandleTypeDef *huart) { 800d394: b580 push {r7, lr} 800d396: b082 sub sp, #8 800d398: af00 add r7, sp, #0 800d39a: 6078 str r0, [r7, #4] if (huart == &huart2) { 800d39c: 687b ldr r3, [r7, #4] 800d39e: 4a15 ldr r2, [pc, #84] @ (800d3f4 ) 800d3a0: 4293 cmp r3, r2 800d3a2: d115 bne.n 800d3d0 SC_LogUartError("UART2 recover start", &huart2); 800d3a4: 4913 ldr r1, [pc, #76] @ (800d3f4 ) 800d3a6: 4814 ldr r0, [pc, #80] @ (800d3f8 ) 800d3a8: f000 f830 bl 800d40c (void)HAL_UART_AbortReceive(&huart2); 800d3ac: 4811 ldr r0, [pc, #68] @ (800d3f4 ) 800d3ae: f006 f975 bl 801369c (void)HAL_UART_AbortTransmit(&huart2); 800d3b2: 4810 ldr r0, [pc, #64] @ (800d3f4 ) 800d3b4: f006 f90a bl 80135cc serial_control.tx_tick = 0; 800d3b8: 4b10 ldr r3, [pc, #64] @ (800d3fc ) 800d3ba: 2200 movs r2, #0 800d3bc: f8c3 220c str.w r2, [r3, #524] @ 0x20c SC_ArmUart2RxDma(); 800d3c0: f7ff ffa6 bl 800d310 sc_uart2_last_recover_tick = HAL_GetTick(); 800d3c4: f001 f9e0 bl 800e788 800d3c8: 4603 mov r3, r0 800d3ca: 4a0d ldr r2, [pc, #52] @ (800d400 ) 800d3cc: 6013 str r3, [r2, #0] } else if (huart == &huart5) { SC_LogUartError("UART5 recover start", &huart5); (void)HAL_UART_AbortReceive(&huart5); SC_ArmUart5RxDma(); } } 800d3ce: e00c b.n 800d3ea } else if (huart == &huart5) { 800d3d0: 687b ldr r3, [r7, #4] 800d3d2: 4a0c ldr r2, [pc, #48] @ (800d404 ) 800d3d4: 4293 cmp r3, r2 800d3d6: d108 bne.n 800d3ea SC_LogUartError("UART5 recover start", &huart5); 800d3d8: 490a ldr r1, [pc, #40] @ (800d404 ) 800d3da: 480b ldr r0, [pc, #44] @ (800d408 ) 800d3dc: f000 f816 bl 800d40c (void)HAL_UART_AbortReceive(&huart5); 800d3e0: 4808 ldr r0, [pc, #32] @ (800d404 ) 800d3e2: f006 f95b bl 801369c SC_ArmUart5RxDma(); 800d3e6: f7ff ffb7 bl 800d358 } 800d3ea: bf00 nop 800d3ec: 3708 adds r7, #8 800d3ee: 46bd mov sp, r7 800d3f0: bd80 pop {r7, pc} 800d3f2: bf00 nop 800d3f4: 200012fc .word 0x200012fc 800d3f8: 08017cbc .word 0x08017cbc 800d3fc: 20000d40 .word 0x20000d40 800d400: 20001168 .word 0x20001168 800d404: 2000126c .word 0x2000126c 800d408: 08017cd0 .word 0x08017cd0 0800d40c : static void SC_LogUartError(const char *tag, UART_HandleTypeDef *huart) { 800d40c: b590 push {r4, r7, lr} 800d40e: b087 sub sp, #28 800d410: af04 add r7, sp, #16 800d412: 6078 str r0, [r7, #4] 800d414: 6039 str r1, [r7, #0] if (tag == NULL || huart == NULL) { 800d416: 687b ldr r3, [r7, #4] 800d418: 2b00 cmp r3, #0 800d41a: d01c beq.n 800d456 800d41c: 683b ldr r3, [r7, #0] 800d41e: 2b00 cmp r3, #0 800d420: d019 beq.n 800d456 return; } log_printf(LOG_ERR, "%s: instance=0x%08lx err=0x%08lx g=%lu rx=%lu\n", tag, (unsigned long)huart->Instance, 800d422: 683b ldr r3, [r7, #0] 800d424: 681b ldr r3, [r3, #0] log_printf(LOG_ERR, "%s: instance=0x%08lx err=0x%08lx g=%lu rx=%lu\n", 800d426: 461c mov r4, r3 (unsigned long)HAL_UART_GetError(huart), 800d428: 6838 ldr r0, [r7, #0] 800d42a: f006 fc88 bl 8013d3e 800d42e: 4602 mov r2, r0 (unsigned long)huart->gState, 800d430: 683b ldr r3, [r7, #0] 800d432: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800d436: b2db uxtb r3, r3 log_printf(LOG_ERR, "%s: instance=0x%08lx err=0x%08lx g=%lu rx=%lu\n", 800d438: 4619 mov r1, r3 (unsigned long)huart->RxState); 800d43a: 683b ldr r3, [r7, #0] 800d43c: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800d440: b2db uxtb r3, r3 log_printf(LOG_ERR, "%s: instance=0x%08lx err=0x%08lx g=%lu rx=%lu\n", 800d442: 9302 str r3, [sp, #8] 800d444: 9101 str r1, [sp, #4] 800d446: 9200 str r2, [sp, #0] 800d448: 4623 mov r3, r4 800d44a: 687a ldr r2, [r7, #4] 800d44c: 4904 ldr r1, [pc, #16] @ (800d460 ) 800d44e: 2004 movs r0, #4 800d450: f7fd f88a bl 800a568 800d454: e000 b.n 800d458 return; 800d456: bf00 nop } 800d458: 370c adds r7, #12 800d45a: 46bd mov sp, r7 800d45c: bd90 pop {r4, r7, pc} 800d45e: bf00 nop 800d460: 08017ce4 .word 0x08017ce4 0800d464 <__NVIC_SystemReset>: { 800d464: b480 push {r7} 800d466: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 800d468: f3bf 8f4f dsb sy } 800d46c: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800d46e: 4b06 ldr r3, [pc, #24] @ (800d488 <__NVIC_SystemReset+0x24>) 800d470: 68db ldr r3, [r3, #12] 800d472: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800d476: 4904 ldr r1, [pc, #16] @ (800d488 <__NVIC_SystemReset+0x24>) 800d478: 4b04 ldr r3, [pc, #16] @ (800d48c <__NVIC_SystemReset+0x28>) 800d47a: 4313 orrs r3, r2 800d47c: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800d47e: f3bf 8f4f dsb sy } 800d482: bf00 nop __NOP(); 800d484: bf00 nop 800d486: e7fd b.n 800d484 <__NVIC_SystemReset+0x20> 800d488: e000ed00 .word 0xe000ed00 800d48c: 05fa0004 .word 0x05fa0004 0800d490 : .chargerNumber = 00001, .unixTime = 1721651966, }; // Единая функция-обработчик всех команд со switch-case void SC_CommandHandler(ReceivedCommand_t* cmd) { 800d490: b580 push {r7, lr} 800d492: b084 sub sp, #16 800d494: af00 add r7, sp, #0 800d496: 6078 str r0, [r7, #4] uint8_t response_code = RESP_FAILED; 800d498: 2313 movs r3, #19 800d49a: 73fb strb r3, [r7, #15] switch (cmd->command) { 800d49c: 687b ldr r3, [r7, #4] 800d49e: 781b ldrb r3, [r3, #0] 800d4a0: 2bc2 cmp r3, #194 @ 0xc2 800d4a2: f300 80d1 bgt.w 800d648 800d4a6: 2bb0 cmp r3, #176 @ 0xb0 800d4a8: da0f bge.n 800d4ca 800d4aa: 2b60 cmp r3, #96 @ 0x60 800d4ac: d042 beq.n 800d534 800d4ae: 2b60 cmp r3, #96 @ 0x60 800d4b0: f300 80ca bgt.w 800d648 800d4b4: 2b50 cmp r3, #80 @ 0x50 800d4b6: d043 beq.n 800d540 800d4b8: 2b50 cmp r3, #80 @ 0x50 800d4ba: f300 80c5 bgt.w 800d648 800d4be: 2b01 cmp r3, #1 800d4c0: f000 80ab beq.w 800d61a 800d4c4: 2b40 cmp r3, #64 @ 0x40 800d4c6: d02d beq.n 800d524 800d4c8: e0be b.n 800d648 800d4ca: 3bb0 subs r3, #176 @ 0xb0 800d4cc: 2b12 cmp r3, #18 800d4ce: f200 80bb bhi.w 800d648 800d4d2: a201 add r2, pc, #4 @ (adr r2, 800d4d8 ) 800d4d4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d4d8: 0800d547 .word 0x0800d547 800d4dc: 0800d649 .word 0x0800d649 800d4e0: 0800d649 .word 0x0800d649 800d4e4: 0800d649 .word 0x0800d649 800d4e8: 0800d649 .word 0x0800d649 800d4ec: 0800d5f9 .word 0x0800d5f9 800d4f0: 0800d649 .word 0x0800d649 800d4f4: 0800d5ef .word 0x0800d5ef 800d4f8: 0800d649 .word 0x0800d649 800d4fc: 0800d649 .word 0x0800d649 800d500: 0800d649 .word 0x0800d649 800d504: 0800d649 .word 0x0800d649 800d508: 0800d649 .word 0x0800d649 800d50c: 0800d649 .word 0x0800d649 800d510: 0800d649 .word 0x0800d649 800d514: 0800d649 .word 0x0800d649 800d518: 0800d585 .word 0x0800d585 800d51c: 0800d5e9 .word 0x0800d5e9 800d520: 0800d5bd .word 0x0800d5bd // Команды БЕЗ аргументов case CMD_GET_STATUS: // Логика получения информации monitoring_data_callback(); 800d524: f000 f8b6 bl 800d694 // Отправляем с нормальным приоритетом SC_SendPacket((uint8_t*)&statusPacket, sizeof(statusPacket), CMD_GET_STATUS); 800d528: 2240 movs r2, #64 @ 0x40 800d52a: 2158 movs r1, #88 @ 0x58 800d52c: 484d ldr r0, [pc, #308] @ (800d664 ) 800d52e: f7ff fe43 bl 800d1b8 return; // Специальный ответ уже отправлен 800d532: e094 b.n 800d65e case CMD_GET_INFO: SC_SendPacket((uint8_t*)&infoPacket, sizeof(infoPacket), CMD_GET_INFO); 800d534: 2260 movs r2, #96 @ 0x60 800d536: 210a movs r1, #10 800d538: 484b ldr r0, [pc, #300] @ (800d668 ) 800d53a: f7ff fe3d bl 800d1b8 return; 800d53e: e08e b.n 800d65e case CMD_GET_LOG: debug_buffer_send(); 800d540: f7fc ffb0 bl 800a4a4 return; // Ответ формируется внутри debug_buffer_send 800d544: e08b b.n 800d65e // Команды С аргументами case CMD_SET_CONFIG: if (cmd->argument_length == sizeof(ConfigBlock_t)) { 800d546: 687b ldr r3, [r7, #4] 800d548: 785b ldrb r3, [r3, #1] 800d54a: 2b0b cmp r3, #11 800d54c: d117 bne.n 800d57e memcpy(&config, cmd->argument, sizeof(ConfigBlock_t)); 800d54e: 687b ldr r3, [r7, #4] 800d550: 685a ldr r2, [r3, #4] 800d552: 4b46 ldr r3, [pc, #280] @ (800d66c ) 800d554: 6810 ldr r0, [r2, #0] 800d556: 6851 ldr r1, [r2, #4] 800d558: c303 stmia r3!, {r0, r1} 800d55a: 8911 ldrh r1, [r2, #8] 800d55c: 7a92 ldrb r2, [r2, #10] 800d55e: 8019 strh r1, [r3, #0] 800d560: 709a strb r2, [r3, #2] config_initialized = 1; 800d562: 4b43 ldr r3, [pc, #268] @ (800d670 ) 800d564: 2201 movs r2, #1 800d566: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Set Config: %s %d\n", config.location, config.chargerNumber); 800d568: 4b40 ldr r3, [pc, #256] @ (800d66c ) 800d56a: f8d3 3003 ldr.w r3, [r3, #3] 800d56e: 4a3f ldr r2, [pc, #252] @ (800d66c ) 800d570: 4940 ldr r1, [pc, #256] @ (800d674 ) 800d572: 2007 movs r0, #7 800d574: f7fc fff8 bl 800a568 response_code = RESP_SUCCESS; 800d578: 2312 movs r3, #18 800d57a: 73fb strb r3, [r7, #15] break; 800d57c: e067 b.n 800d64e } response_code = RESP_FAILED; 800d57e: 2313 movs r3, #19 800d580: 73fb strb r3, [r7, #15] break; 800d582: e064 b.n 800d64e case CMD_SET_POWER_LIMIT: if (cmd->argument_length == 1) { 800d584: 687b ldr r3, [r7, #4] 800d586: 785b ldrb r3, [r3, #1] 800d588: 2b01 cmp r3, #1 800d58a: d114 bne.n 800d5b6 PSU0.power_limit = ((uint8_t*)cmd->argument)[0] * 1000; 800d58c: 687b ldr r3, [r7, #4] 800d58e: 685b ldr r3, [r3, #4] 800d590: 781b ldrb r3, [r3, #0] 800d592: 461a mov r2, r3 800d594: f44f 737a mov.w r3, #1000 @ 0x3e8 800d598: fb02 f303 mul.w r3, r2, r3 800d59c: 461a mov r2, r3 800d59e: 4b36 ldr r3, [pc, #216] @ (800d678 ) 800d5a0: 615a str r2, [r3, #20] log_printf(LOG_INFO, "Power limit: %d\n", PSU0.power_limit); 800d5a2: 4b35 ldr r3, [pc, #212] @ (800d678 ) 800d5a4: 695b ldr r3, [r3, #20] 800d5a6: 461a mov r2, r3 800d5a8: 4934 ldr r1, [pc, #208] @ (800d67c ) 800d5aa: 2007 movs r0, #7 800d5ac: f7fc ffdc bl 800a568 //CONN.connState = (((uint8_t*)cmd->argument)[0])/4; response_code = RESP_SUCCESS; 800d5b0: 2312 movs r3, #18 800d5b2: 73fb strb r3, [r7, #15] break; 800d5b4: e04b b.n 800d64e } response_code = RESP_FAILED; 800d5b6: 2313 movs r3, #19 800d5b8: 73fb strb r3, [r7, #15] break; 800d5ba: e048 b.n 800d64e case CMD_CHARGE_PERMIT: if (cmd->argument_length == 1) { 800d5bc: 687b ldr r3, [r7, #4] 800d5be: 785b ldrb r3, [r3, #1] 800d5c0: 2b01 cmp r3, #1 800d5c2: d10e bne.n 800d5e2 CONN.connControl = ((uint8_t*)cmd->argument)[0]; 800d5c4: 687b ldr r3, [r7, #4] 800d5c6: 685b ldr r3, [r3, #4] 800d5c8: 781a ldrb r2, [r3, #0] 800d5ca: 4b2d ldr r3, [pc, #180] @ (800d680 ) 800d5cc: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Charge permit: %d\n", CONN.connControl); 800d5ce: 4b2c ldr r3, [pc, #176] @ (800d680 ) 800d5d0: 781b ldrb r3, [r3, #0] 800d5d2: 461a mov r2, r3 800d5d4: 492b ldr r1, [pc, #172] @ (800d684 ) 800d5d6: 2007 movs r0, #7 800d5d8: f7fc ffc6 bl 800a568 response_code = RESP_SUCCESS; 800d5dc: 2312 movs r3, #18 800d5de: 73fb strb r3, [r7, #15] break; 800d5e0: e035 b.n 800d64e } response_code = RESP_FAILED; 800d5e2: 2313 movs r3, #19 800d5e4: 73fb strb r3, [r7, #15] break; 800d5e6: e032 b.n 800d64e // memcpy(&PSU_TestMode, cmd->argument, sizeof(PSU_TestMode_t)); // log_printf(LOG_INFO, "Test PSU: %d %d %d\n", PSU_TestMode.enable, PSU_TestMode.voltage, PSU_TestMode.current); // response_code = RESP_SUCCESS; // break; // } response_code = RESP_FAILED; 800d5e8: 2313 movs r3, #19 800d5ea: 73fb strb r3, [r7, #15] break; 800d5ec: e02f b.n 800d64e case CMD_FIRE_ALARM: FireAlarm_Activate(); 800d5ee: f7fd f839 bl 800a664 response_code = RESP_SUCCESS; 800d5f2: 2312 movs r3, #18 800d5f4: 73fb strb r3, [r7, #15] break; 800d5f6: e02a b.n 800d64e case CMD_DEVICE_RESET: // 2. Отправляем SUCCESS (хост может успеть получить его перед ребутом) SC_SendPacket(NULL, 0, RESP_SUCCESS); 800d5f8: 2212 movs r2, #18 800d5fa: 2100 movs r1, #0 800d5fc: 2000 movs r0, #0 800d5fe: f7ff fddb bl 800d1b8 while(huart2.gState == HAL_UART_STATE_BUSY_TX); // Ожидание завершения передачи 800d602: bf00 nop 800d604: 4b20 ldr r3, [pc, #128] @ (800d688 ) 800d606: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800d60a: b2db uxtb r3, r3 800d60c: 2b21 cmp r3, #33 @ 0x21 800d60e: d0f9 beq.n 800d604 HAL_Delay(10); 800d610: 200a movs r0, #10 800d612: f001 f8c3 bl 800e79c // 3. Выполняем программный сброс NVIC_SystemReset(); 800d616: f7ff ff25 bl 800d464 <__NVIC_SystemReset> return; // Сюда код уже не дойдет, но для компилятора нxужно case CMD_ISOLATION_STATUS: if (cmd->argument_length == sizeof(IsolationStatusPacket_t)) { 800d61a: 687b ldr r3, [r7, #4] 800d61c: 785b ldrb r3, [r3, #1] 800d61e: 2b09 cmp r3, #9 800d620: d10f bne.n 800d642 memcpy(&ISO, cmd->argument, sizeof(IsolationStatusPacket_t)); 800d622: 687b ldr r3, [r7, #4] 800d624: 685a ldr r2, [r3, #4] 800d626: 4b19 ldr r3, [pc, #100] @ (800d68c ) 800d628: 6810 ldr r0, [r2, #0] 800d62a: 6851 ldr r1, [r2, #4] 800d62c: c303 stmia r3!, {r0, r1} 800d62e: 7a12 ldrb r2, [r2, #8] 800d630: 701a strb r2, [r3, #0] // Для однонаправленного UART5 ответ не нужен if (g_sc_command_source == SC_SOURCE_UART5) { 800d632: 4b17 ldr r3, [pc, #92] @ (800d690 ) 800d634: 781b ldrb r3, [r3, #0] 800d636: b2db uxtb r3, r3 800d638: 2b01 cmp r3, #1 800d63a: d00f beq.n 800d65c return; } response_code = RESP_SUCCESS; 800d63c: 2312 movs r3, #18 800d63e: 73fb strb r3, [r7, #15] break; 800d640: e005 b.n 800d64e } response_code = RESP_FAILED; 800d642: 2313 movs r3, #19 800d644: 73fb strb r3, [r7, #15] break; 800d646: e002 b.n 800d64e default: // Неизвестная команда response_code = RESP_FAILED; 800d648: 2313 movs r3, #19 800d64a: 73fb strb r3, [r7, #15] break; 800d64c: bf00 nop } // Отправляем финальный ответ (для команд без собственного ответа) SC_SendPacket(NULL, 0, response_code); 800d64e: 7bfb ldrb r3, [r7, #15] 800d650: 461a mov r2, r3 800d652: 2100 movs r1, #0 800d654: 2000 movs r0, #0 800d656: f7ff fdaf bl 800d1b8 800d65a: e000 b.n 800d65e return; 800d65c: bf00 nop } 800d65e: 3710 adds r7, #16 800d660: 46bd mov sp, r7 800d662: bd80 pop {r7, pc} 800d664: 2000116c .word 0x2000116c 800d668: 200011c4 .word 0x200011c4 800d66c: 20000078 .word 0x20000078 800d670: 200011d4 .word 0x200011d4 800d674: 08017d14 .word 0x08017d14 800d678: 20000904 .word 0x20000904 800d67c: 08017d28 .word 0x08017d28 800d680: 200003b0 .word 0x200003b0 800d684: 08017d3c .word 0x08017d3c 800d688: 200012fc .word 0x200012fc 800d68c: 2000006c .word 0x2000006c 800d690: 20001160 .word 0x20001160 0800d694 : // Колбэк для заполнения данных мониторинга static void monitoring_data_callback(void) { 800d694: b580 push {r7, lr} 800d696: af00 add r7, sp, #0 // Информация о зарядной сессии statusPacket.SOC = CONN.SOC; 800d698: 4b8f ldr r3, [pc, #572] @ (800d8d8 ) 800d69a: 789a ldrb r2, [r3, #2] 800d69c: 4b8f ldr r3, [pc, #572] @ (800d8dc ) 800d69e: 709a strb r2, [r3, #2] statusPacket.Energy = CONN.Energy; 800d6a0: 4b8d ldr r3, [pc, #564] @ (800d8d8 ) 800d6a2: f8d3 3007 ldr.w r3, [r3, #7] 800d6a6: 4a8d ldr r2, [pc, #564] @ (800d8dc ) 800d6a8: f8c2 3003 str.w r3, [r2, #3] statusPacket.RequestedVoltage = CONN.RequestedVoltage; 800d6ac: 4b8a ldr r3, [pc, #552] @ (800d8d8 ) 800d6ae: f8b3 300f ldrh.w r3, [r3, #15] 800d6b2: b29a uxth r2, r3 800d6b4: 4b89 ldr r3, [pc, #548] @ (800d8dc ) 800d6b6: f8a3 2007 strh.w r2, [r3, #7] statusPacket.RequestedCurrent = CONN.WantedCurrent; 800d6ba: 4b87 ldr r3, [pc, #540] @ (800d8d8 ) 800d6bc: f8b3 301b ldrh.w r3, [r3, #27] 800d6c0: b29a uxth r2, r3 800d6c2: 4b86 ldr r3, [pc, #536] @ (800d8dc ) 800d6c4: f8a3 2009 strh.w r2, [r3, #9] statusPacket.MeasuredVoltage = CONN.MeasuredVoltage; 800d6c8: 4b83 ldr r3, [pc, #524] @ (800d8d8 ) 800d6ca: f8b3 3013 ldrh.w r3, [r3, #19] 800d6ce: b29a uxth r2, r3 800d6d0: 4b82 ldr r3, [pc, #520] @ (800d8dc ) 800d6d2: f8a3 200b strh.w r2, [r3, #11] statusPacket.MeasuredCurrent = CONN.MeasuredCurrent; 800d6d6: 4b80 ldr r3, [pc, #512] @ (800d8d8 ) 800d6d8: f8b3 3015 ldrh.w r3, [r3, #21] 800d6dc: b29a uxth r2, r3 800d6de: 4b7f ldr r3, [pc, #508] @ (800d8dc ) 800d6e0: f8a3 200d strh.w r2, [r3, #13] statusPacket.outputEnabled = CONN.outputEnabled; 800d6e4: 4b7c ldr r3, [pc, #496] @ (800d8d8 ) 800d6e6: 7e1a ldrb r2, [r3, #24] 800d6e8: 4b7c ldr r3, [pc, #496] @ (800d8dc ) 800d6ea: 73da strb r2, [r3, #15] statusPacket.chargingError = CONN.chargingError; 800d6ec: 4b7a ldr r3, [pc, #488] @ (800d8d8 ) 800d6ee: 7f5a ldrb r2, [r3, #29] 800d6f0: 4b7a ldr r3, [pc, #488] @ (800d8dc ) 800d6f2: 705a strb r2, [r3, #1] statusPacket.connState = CONN.connState; 800d6f4: 4b78 ldr r3, [pc, #480] @ (800d8d8 ) 800d6f6: 785a ldrb r2, [r3, #1] 800d6f8: 4b78 ldr r3, [pc, #480] @ (800d8dc ) 800d6fa: 701a strb r2, [r3, #0] statusPacket.chargingElapsedTimeMin = 0; 800d6fc: 4b77 ldr r3, [pc, #476] @ (800d8dc ) 800d6fe: 2200 movs r2, #0 800d700: 741a strb r2, [r3, #16] 800d702: 2200 movs r2, #0 800d704: 745a strb r2, [r3, #17] statusPacket.chargingElapsedTimeSec = 0; 800d706: 4b75 ldr r3, [pc, #468] @ (800d8dc ) 800d708: 2200 movs r2, #0 800d70a: 749a strb r2, [r3, #18] statusPacket.estimatedRemainingChargingTime = 0; 800d70c: 4b73 ldr r3, [pc, #460] @ (800d8dc ) 800d70e: 2200 movs r2, #0 800d710: 74da strb r2, [r3, #19] 800d712: 2200 movs r2, #0 800d714: 751a strb r2, [r3, #20] // состояние зарядной станции statusPacket.relayAC = RELAY_Read(RELAY_AC); 800d716: 2004 movs r0, #4 800d718: f7fc f8be bl 8009898 800d71c: 4603 mov r3, r0 800d71e: f003 0301 and.w r3, r3, #1 800d722: b2d9 uxtb r1, r3 800d724: 4a6d ldr r2, [pc, #436] @ (800d8dc ) 800d726: 7d53 ldrb r3, [r2, #21] 800d728: f361 0300 bfi r3, r1, #0, #1 800d72c: 7553 strb r3, [r2, #21] statusPacket.relayDC = RELAY_Read(RELAY_DC); 800d72e: 2003 movs r0, #3 800d730: f7fc f8b2 bl 8009898 800d734: 4603 mov r3, r0 800d736: f003 0301 and.w r3, r3, #1 800d73a: b2d9 uxtb r1, r3 800d73c: 4a67 ldr r2, [pc, #412] @ (800d8dc ) 800d73e: 7d53 ldrb r3, [r2, #21] 800d740: f361 0341 bfi r3, r1, #1, #1 800d744: 7553 strb r3, [r2, #21] statusPacket.relayAUX = RELAY_Read(RELAY_AUX0); 800d746: 2000 movs r0, #0 800d748: f7fc f8a6 bl 8009898 800d74c: 4603 mov r3, r0 800d74e: f003 0301 and.w r3, r3, #1 800d752: b2d9 uxtb r1, r3 800d754: 4a61 ldr r2, [pc, #388] @ (800d8dc ) 800d756: 7d53 ldrb r3, [r2, #21] 800d758: f361 0382 bfi r3, r1, #2, #1 800d75c: 7553 strb r3, [r2, #21] statusPacket.lockState = 0; 800d75e: 4a5f ldr r2, [pc, #380] @ (800d8dc ) 800d760: 7d53 ldrb r3, [r2, #21] 800d762: f023 0308 bic.w r3, r3, #8 800d766: 7553 strb r3, [r2, #21] statusPacket.stopButton = !IN_ReadInput(IN_ESTOP); 800d768: 2003 movs r0, #3 800d76a: f7fc f8a5 bl 80098b8 800d76e: 4603 mov r3, r0 800d770: 2b00 cmp r3, #0 800d772: bf0c ite eq 800d774: 2301 moveq r3, #1 800d776: 2300 movne r3, #0 800d778: b2d9 uxtb r1, r3 800d77a: 4a58 ldr r2, [pc, #352] @ (800d8dc ) 800d77c: 7d53 ldrb r3, [r2, #21] 800d77e: f361 1304 bfi r3, r1, #4, #1 800d782: 7553 strb r3, [r2, #21] statusPacket.logAvailable = (debug_buffer_available()>0)?1:0; 800d784: f7fc fe7a bl 800a47c 800d788: 4603 mov r3, r0 800d78a: 2b00 cmp r3, #0 800d78c: bf14 ite ne 800d78e: 2301 movne r3, #1 800d790: 2300 moveq r3, #0 800d792: b2d9 uxtb r1, r3 800d794: 4a51 ldr r2, [pc, #324] @ (800d8dc ) 800d796: 7d53 ldrb r3, [r2, #21] 800d798: f361 1345 bfi r3, r1, #5, #1 800d79c: 7553 strb r3, [r2, #21] statusPacket.evInfoAvailable = 0; 800d79e: 4a4f ldr r2, [pc, #316] @ (800d8dc ) 800d7a0: 7d53 ldrb r3, [r2, #21] 800d7a2: f023 0340 bic.w r3, r3, #64 @ 0x40 800d7a6: 7553 strb r3, [r2, #21] statusPacket.psuOnline = PSU0.online; 800d7a8: 4b4d ldr r3, [pc, #308] @ (800d8e0 ) 800d7aa: 7a1b ldrb r3, [r3, #8] 800d7ac: f003 0301 and.w r3, r3, #1 800d7b0: b2d9 uxtb r1, r3 800d7b2: 4a4a ldr r2, [pc, #296] @ (800d8dc ) 800d7b4: 7d53 ldrb r3, [r2, #21] 800d7b6: f361 13c7 bfi r3, r1, #7, #1 800d7ba: 7553 strb r3, [r2, #21] statusPacket.tempConnector0 = CONN_ReadTemp(0); // температура коннектора 800d7bc: 2000 movs r0, #0 800d7be: f7fc f9a1 bl 8009b04 800d7c2: 4603 mov r3, r0 800d7c4: b25a sxtb r2, r3 800d7c6: 4b45 ldr r3, [pc, #276] @ (800d8dc ) 800d7c8: 765a strb r2, [r3, #25] statusPacket.tempConnector1 = CONN_ReadTemp(1); 800d7ca: 2001 movs r0, #1 800d7cc: f7fc f99a bl 8009b04 800d7d0: 4603 mov r3, r0 800d7d2: b25a sxtb r2, r3 800d7d4: 4b41 ldr r3, [pc, #260] @ (800d8dc ) 800d7d6: 769a strb r2, [r3, #26] statusPacket.tempAmbient = PSU0.tempAmbient; // температура окружающего воздуха 800d7d8: 4b41 ldr r3, [pc, #260] @ (800d8e0 ) 800d7da: 6a1b ldr r3, [r3, #32] 800d7dc: b25a sxtb r2, r3 800d7de: 4b3f ldr r3, [pc, #252] @ (800d8dc ) 800d7e0: 76da strb r2, [r3, #27] statusPacket.tempBatteryMax = 0; 800d7e2: 4b3e ldr r3, [pc, #248] @ (800d8dc ) 800d7e4: 2200 movs r2, #0 800d7e6: 771a strb r2, [r3, #28] statusPacket.tempBatteryMin = 0; 800d7e8: 4b3c ldr r3, [pc, #240] @ (800d8dc ) 800d7ea: 2200 movs r2, #0 800d7ec: 775a strb r2, [r3, #29] statusPacket.highestVoltageOfBatteryCell = 0; 800d7ee: 4b3b ldr r3, [pc, #236] @ (800d8dc ) 800d7f0: 2200 movs r2, #0 800d7f2: 779a strb r2, [r3, #30] 800d7f4: 2200 movs r2, #0 800d7f6: 77da strb r2, [r3, #31] statusPacket.batteryStatus = 0; 800d7f8: 4b38 ldr r3, [pc, #224] @ (800d8dc ) 800d7fa: 2200 movs r2, #0 800d7fc: f883 2020 strb.w r2, [r3, #32] statusPacket.phaseVoltageAB = PSU_06.VAB; 800d800: 4b38 ldr r3, [pc, #224] @ (800d8e4 ) 800d802: 689b ldr r3, [r3, #8] 800d804: b29a uxth r2, r3 800d806: 4b35 ldr r3, [pc, #212] @ (800d8dc ) 800d808: f8a3 2021 strh.w r2, [r3, #33] @ 0x21 statusPacket.phaseVoltageBC = PSU_06.VBC; 800d80c: 4b35 ldr r3, [pc, #212] @ (800d8e4 ) 800d80e: 68db ldr r3, [r3, #12] 800d810: b29a uxth r2, r3 800d812: 4b32 ldr r3, [pc, #200] @ (800d8dc ) 800d814: f8a3 2023 strh.w r2, [r3, #35] @ 0x23 statusPacket.phaseVoltageCA = PSU_06.VCA; 800d818: 4b32 ldr r3, [pc, #200] @ (800d8e4 ) 800d81a: 691b ldr r3, [r3, #16] 800d81c: b29a uxth r2, r3 800d81e: 4b2f ldr r3, [pc, #188] @ (800d8dc ) 800d820: f8a3 2025 strh.w r2, [r3, #37] @ 0x25 // GBT TODO memset(statusPacket.VIN, 0, sizeof(statusPacket.VIN)); 800d824: 2211 movs r2, #17 800d826: 2100 movs r1, #0 800d828: 482f ldr r0, [pc, #188] @ (800d8e8 ) 800d82a: f007 fc67 bl 80150fc // GBT TODO statusPacket.batteryType = 0; 800d82e: 4b2b ldr r3, [pc, #172] @ (800d8dc ) 800d830: 2200 movs r2, #0 800d832: f883 2038 strb.w r2, [r3, #56] @ 0x38 statusPacket.batteryCapacity = 0; 800d836: 4b29 ldr r3, [pc, #164] @ (800d8dc ) 800d838: 2200 movs r2, #0 800d83a: f883 2039 strb.w r2, [r3, #57] @ 0x39 800d83e: 2200 movs r2, #0 800d840: f883 203a strb.w r2, [r3, #58] @ 0x3a statusPacket.batteryVoltage = 0; 800d844: 4b25 ldr r3, [pc, #148] @ (800d8dc ) 800d846: 2200 movs r2, #0 800d848: f883 203b strb.w r2, [r3, #59] @ 0x3b 800d84c: 2200 movs r2, #0 800d84e: f883 203c strb.w r2, [r3, #60] @ 0x3c memset(statusPacket.batteryVendor, 0, sizeof(statusPacket.batteryVendor)); 800d852: 2204 movs r2, #4 800d854: 2100 movs r1, #0 800d856: 4825 ldr r0, [pc, #148] @ (800d8ec ) 800d858: f007 fc50 bl 80150fc statusPacket.batterySN = 0; 800d85c: 4b1f ldr r3, [pc, #124] @ (800d8dc ) 800d85e: 2200 movs r2, #0 800d860: f883 2041 strb.w r2, [r3, #65] @ 0x41 800d864: 2200 movs r2, #0 800d866: f883 2042 strb.w r2, [r3, #66] @ 0x42 800d86a: 2200 movs r2, #0 800d86c: f883 2043 strb.w r2, [r3, #67] @ 0x43 800d870: 2200 movs r2, #0 800d872: f883 2044 strb.w r2, [r3, #68] @ 0x44 statusPacket.batteryManuD = 0; 800d876: 4b19 ldr r3, [pc, #100] @ (800d8dc ) 800d878: 2200 movs r2, #0 800d87a: f883 2047 strb.w r2, [r3, #71] @ 0x47 statusPacket.batteryManuM = 0; 800d87e: 4b17 ldr r3, [pc, #92] @ (800d8dc ) 800d880: 2200 movs r2, #0 800d882: f883 2046 strb.w r2, [r3, #70] @ 0x46 statusPacket.batteryManuY = 0; 800d886: 4b15 ldr r3, [pc, #84] @ (800d8dc ) 800d888: 2200 movs r2, #0 800d88a: f883 2045 strb.w r2, [r3, #69] @ 0x45 statusPacket.batteryCycleCount = 0; 800d88e: 4b13 ldr r3, [pc, #76] @ (800d8dc ) 800d890: 2200 movs r2, #0 800d892: f883 2048 strb.w r2, [r3, #72] @ 0x48 800d896: 2200 movs r2, #0 800d898: f883 2049 strb.w r2, [r3, #73] @ 0x49 statusPacket.ownAuto = 0; 800d89c: 4b0f ldr r3, [pc, #60] @ (800d8dc ) 800d89e: 2200 movs r2, #0 800d8a0: f883 204a strb.w r2, [r3, #74] @ 0x4a memset(statusPacket.EV_SW_VER, 0, sizeof(statusPacket.EV_SW_VER)); 800d8a4: 2208 movs r2, #8 800d8a6: 2100 movs r1, #0 800d8a8: 4811 ldr r0, [pc, #68] @ (800d8f0 ) 800d8aa: f007 fc27 bl 80150fc statusPacket.testMode = 0; 800d8ae: 4b0b ldr r3, [pc, #44] @ (800d8dc ) 800d8b0: 2200 movs r2, #0 800d8b2: f883 2053 strb.w r2, [r3, #83] @ 0x53 statusPacket.testVoltage = 0; 800d8b6: 4b09 ldr r3, [pc, #36] @ (800d8dc ) 800d8b8: 2200 movs r2, #0 800d8ba: f883 2054 strb.w r2, [r3, #84] @ 0x54 800d8be: 2200 movs r2, #0 800d8c0: f883 2055 strb.w r2, [r3, #85] @ 0x55 statusPacket.testCurrent = 0; 800d8c4: 4b05 ldr r3, [pc, #20] @ (800d8dc ) 800d8c6: 2200 movs r2, #0 800d8c8: f883 2056 strb.w r2, [r3, #86] @ 0x56 800d8cc: 2200 movs r2, #0 800d8ce: f883 2057 strb.w r2, [r3, #87] @ 0x57 // В debug.c есть CONN_SetState, предполагаем наличие CONN_GetState() // Если такой функции нет, закомментируйте следующую строку: // statusPacket.connState = CONN_GetState(); } 800d8d2: bf00 nop 800d8d4: bd80 pop {r7, pc} 800d8d6: bf00 nop 800d8d8: 200003b0 .word 0x200003b0 800d8dc: 2000116c .word 0x2000116c 800d8e0: 20000904 .word 0x20000904 800d8e4: 200008d8 .word 0x200008d8 800d8e8: 20001193 .word 0x20001193 800d8ec: 200011a9 .word 0x200011a9 800d8f0: 200011b7 .word 0x200011b7 0800d8f4 : #include "sma_filter.h" void SMAFilter_Init(SMAFilter_t* f) { 800d8f4: b480 push {r7} 800d8f6: b085 sub sp, #20 800d8f8: af00 add r7, sp, #0 800d8fa: 6078 str r0, [r7, #4] if (f == 0) return; 800d8fc: 687b ldr r3, [r7, #4] 800d8fe: 2b00 cmp r3, #0 800d900: d018 beq.n 800d934 f->sum = 0; 800d902: 687b ldr r3, [r7, #4] 800d904: 2200 movs r2, #0 800d906: 601a str r2, [r3, #0] f->idx = 0; 800d908: 687b ldr r3, [r7, #4] 800d90a: 2200 movs r2, #0 800d90c: 809a strh r2, [r3, #4] f->count = 0; 800d90e: 687b ldr r3, [r7, #4] 800d910: 2200 movs r2, #0 800d912: 80da strh r2, [r3, #6] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800d914: 2300 movs r3, #0 800d916: 81fb strh r3, [r7, #14] 800d918: e008 b.n 800d92c f->buffer[i] = 0; 800d91a: 89fa ldrh r2, [r7, #14] 800d91c: 687b ldr r3, [r7, #4] 800d91e: 3202 adds r2, #2 800d920: 2100 movs r1, #0 800d922: f843 1022 str.w r1, [r3, r2, lsl #2] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800d926: 89fb ldrh r3, [r7, #14] 800d928: 3301 adds r3, #1 800d92a: 81fb strh r3, [r7, #14] 800d92c: 89fb ldrh r3, [r7, #14] 800d92e: 2b07 cmp r3, #7 800d930: d9f3 bls.n 800d91a 800d932: e000 b.n 800d936 if (f == 0) return; 800d934: bf00 nop } } 800d936: 3714 adds r7, #20 800d938: 46bd mov sp, r7 800d93a: bc80 pop {r7} 800d93c: 4770 bx lr 0800d93e : int32_t SMAFilter_Update(SMAFilter_t* f, int32_t x) { 800d93e: b480 push {r7} 800d940: b085 sub sp, #20 800d942: af00 add r7, sp, #0 800d944: 6078 str r0, [r7, #4] 800d946: 6039 str r1, [r7, #0] if (f == 0) return x; 800d948: 687b ldr r3, [r7, #4] 800d94a: 2b00 cmp r3, #0 800d94c: d101 bne.n 800d952 800d94e: 683b ldr r3, [r7, #0] 800d950: e056 b.n 800da00 // Пока окно не заполнено полностью, делим по фактическому count. if (f->count < SMA_FILTER_WINDOW) { 800d952: 687b ldr r3, [r7, #4] 800d954: 88db ldrh r3, [r3, #6] 800d956: 2b07 cmp r3, #7 800d958: d827 bhi.n 800d9aa f->buffer[f->idx] = x; 800d95a: 687b ldr r3, [r7, #4] 800d95c: 889b ldrh r3, [r3, #4] 800d95e: 461a mov r2, r3 800d960: 687b ldr r3, [r7, #4] 800d962: 3202 adds r2, #2 800d964: 6839 ldr r1, [r7, #0] 800d966: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += x; 800d96a: 687b ldr r3, [r7, #4] 800d96c: 681a ldr r2, [r3, #0] 800d96e: 683b ldr r3, [r7, #0] 800d970: 441a add r2, r3 800d972: 687b ldr r3, [r7, #4] 800d974: 601a str r2, [r3, #0] f->idx++; 800d976: 687b ldr r3, [r7, #4] 800d978: 889b ldrh r3, [r3, #4] 800d97a: 3301 adds r3, #1 800d97c: b29a uxth r2, r3 800d97e: 687b ldr r3, [r7, #4] 800d980: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800d982: 687b ldr r3, [r7, #4] 800d984: 889b ldrh r3, [r3, #4] 800d986: 2b07 cmp r3, #7 800d988: d902 bls.n 800d990 800d98a: 687b ldr r3, [r7, #4] 800d98c: 2200 movs r2, #0 800d98e: 809a strh r2, [r3, #4] f->count++; 800d990: 687b ldr r3, [r7, #4] 800d992: 88db ldrh r3, [r3, #6] 800d994: 3301 adds r3, #1 800d996: b29a uxth r2, r3 800d998: 687b ldr r3, [r7, #4] 800d99a: 80da strh r2, [r3, #6] return (int32_t)(f->sum / (int32_t)f->count); 800d99c: 687b ldr r3, [r7, #4] 800d99e: 681b ldr r3, [r3, #0] 800d9a0: 687a ldr r2, [r7, #4] 800d9a2: 88d2 ldrh r2, [r2, #6] 800d9a4: fb93 f3f2 sdiv r3, r3, r2 800d9a8: e02a b.n 800da00 } // Окно заполнено: "вычитаем старое + добавляем новое". int32_t old = f->buffer[f->idx]; 800d9aa: 687b ldr r3, [r7, #4] 800d9ac: 889b ldrh r3, [r3, #4] 800d9ae: 461a mov r2, r3 800d9b0: 687b ldr r3, [r7, #4] 800d9b2: 3202 adds r2, #2 800d9b4: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800d9b8: 60fb str r3, [r7, #12] f->buffer[f->idx] = x; 800d9ba: 687b ldr r3, [r7, #4] 800d9bc: 889b ldrh r3, [r3, #4] 800d9be: 461a mov r2, r3 800d9c0: 687b ldr r3, [r7, #4] 800d9c2: 3202 adds r2, #2 800d9c4: 6839 ldr r1, [r7, #0] 800d9c6: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += (x - old); 800d9ca: 687b ldr r3, [r7, #4] 800d9cc: 681a ldr r2, [r3, #0] 800d9ce: 6839 ldr r1, [r7, #0] 800d9d0: 68fb ldr r3, [r7, #12] 800d9d2: 1acb subs r3, r1, r3 800d9d4: 441a add r2, r3 800d9d6: 687b ldr r3, [r7, #4] 800d9d8: 601a str r2, [r3, #0] f->idx++; 800d9da: 687b ldr r3, [r7, #4] 800d9dc: 889b ldrh r3, [r3, #4] 800d9de: 3301 adds r3, #1 800d9e0: b29a uxth r2, r3 800d9e2: 687b ldr r3, [r7, #4] 800d9e4: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800d9e6: 687b ldr r3, [r7, #4] 800d9e8: 889b ldrh r3, [r3, #4] 800d9ea: 2b07 cmp r3, #7 800d9ec: d902 bls.n 800d9f4 800d9ee: 687b ldr r3, [r7, #4] 800d9f0: 2200 movs r2, #0 800d9f2: 809a strh r2, [r3, #4] return (int32_t)(f->sum / (int32_t)SMA_FILTER_WINDOW); 800d9f4: 687b ldr r3, [r7, #4] 800d9f6: 681b ldr r3, [r3, #0] 800d9f8: 2b00 cmp r3, #0 800d9fa: da00 bge.n 800d9fe 800d9fc: 3307 adds r3, #7 800d9fe: 10db asrs r3, r3, #3 } 800da00: 4618 mov r0, r3 800da02: 3714 adds r7, #20 800da04: 46bd mov sp, r7 800da06: bc80 pop {r7} 800da08: 4770 bx lr ... 0800da0c : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800da0c: b480 push {r7} 800da0e: b085 sub sp, #20 800da10: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 800da12: 4b15 ldr r3, [pc, #84] @ (800da68 ) 800da14: 699b ldr r3, [r3, #24] 800da16: 4a14 ldr r2, [pc, #80] @ (800da68 ) 800da18: f043 0301 orr.w r3, r3, #1 800da1c: 6193 str r3, [r2, #24] 800da1e: 4b12 ldr r3, [pc, #72] @ (800da68 ) 800da20: 699b ldr r3, [r3, #24] 800da22: f003 0301 and.w r3, r3, #1 800da26: 60bb str r3, [r7, #8] 800da28: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800da2a: 4b0f ldr r3, [pc, #60] @ (800da68 ) 800da2c: 69db ldr r3, [r3, #28] 800da2e: 4a0e ldr r2, [pc, #56] @ (800da68 ) 800da30: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800da34: 61d3 str r3, [r2, #28] 800da36: 4b0c ldr r3, [pc, #48] @ (800da68 ) 800da38: 69db ldr r3, [r3, #28] 800da3a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800da3e: 607b str r3, [r7, #4] 800da40: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 800da42: 4b0a ldr r3, [pc, #40] @ (800da6c ) 800da44: 685b ldr r3, [r3, #4] 800da46: 60fb str r3, [r7, #12] 800da48: 68fb ldr r3, [r7, #12] 800da4a: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 800da4e: 60fb str r3, [r7, #12] 800da50: 68fb ldr r3, [r7, #12] 800da52: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 800da56: 60fb str r3, [r7, #12] 800da58: 4a04 ldr r2, [pc, #16] @ (800da6c ) 800da5a: 68fb ldr r3, [r7, #12] 800da5c: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800da5e: bf00 nop 800da60: 3714 adds r7, #20 800da62: 46bd mov sp, r7 800da64: bc80 pop {r7} 800da66: 4770 bx lr 800da68: 40021000 .word 0x40021000 800da6c: 40010000 .word 0x40010000 0800da70 : { /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800da70: e7fe b.n 800da70 800da72: bf00 nop 0800da74 : void HardFault_Handler(void) { /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800da74: e7fe b.n 800da74 800da76: bf00 nop 0800da78 : void MemManage_Handler(void) { /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800da78: e7fe b.n 800da78 800da7a: bf00 nop 0800da7c : void BusFault_Handler(void) { /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800da7c: e7fe b.n 800da7c 800da7e: bf00 nop 0800da80 : void UsageFault_Handler(void) { /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 800da80: e7fe b.n 800da80 800da82: bf00 nop 0800da84 : /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800da84: 4770 bx lr 800da86: bf00 nop 0800da88 : /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800da88: 4770 bx lr 800da8a: bf00 nop 0800da8c : /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800da8c: 4770 bx lr 800da8e: bf00 nop 0800da90 : void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800da90: f000 be68 b.w 800e764 0800da94 : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { 800da94: b510 push {r4, lr} /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800da96: 4c09 ldr r4, [pc, #36] @ (800dabc ) 800da98: 2201 movs r2, #1 800da9a: f44f 6100 mov.w r1, #2048 @ 0x800 800da9e: 4620 mov r0, r4 800daa0: f003 fa09 bl 8010eb6 /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 800daa4: 4806 ldr r0, [pc, #24] @ (800dac0 ) 800daa6: f002 fdf7 bl 8010698 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800daaa: 4620 mov r0, r4 /* USER CODE END DMA1_Channel1_IRQn 1 */ } 800daac: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800dab0: 2200 movs r2, #0 800dab2: f44f 6100 mov.w r1, #2048 @ 0x800 800dab6: f003 b9fe b.w 8010eb6 800daba: bf00 nop 800dabc: 40010c00 .word 0x40010c00 800dac0: 200002c0 .word 0x200002c0 0800dac4 : void DMA1_Channel2_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ /* USER CODE END DMA1_Channel2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart3_tx); 800dac4: 4801 ldr r0, [pc, #4] @ (800dacc ) 800dac6: f002 bde7 b.w 8010698 800daca: bf00 nop 800dacc: 20001458 .word 0x20001458 0800dad0 : void DMA1_Channel3_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel3_IRQn 0 */ /* USER CODE END DMA1_Channel3_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart3_rx); 800dad0: 4801 ldr r0, [pc, #4] @ (800dad8 ) 800dad2: f002 bde1 b.w 8010698 800dad6: bf00 nop 800dad8: 20001414 .word 0x20001414 0800dadc : void DMA1_Channel6_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel6_IRQn 0 */ /* USER CODE END DMA1_Channel6_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_rx); 800dadc: 4801 ldr r0, [pc, #4] @ (800dae4 ) 800dade: f002 bddb b.w 8010698 800dae2: bf00 nop 800dae4: 2000138c .word 0x2000138c 0800dae8 : void DMA1_Channel7_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel7_IRQn 0 */ /* USER CODE END DMA1_Channel7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_tx); 800dae8: 4801 ldr r0, [pc, #4] @ (800daf0 ) 800daea: f002 bdd5 b.w 8010698 800daee: bf00 nop 800daf0: 200013d0 .word 0x200013d0 0800daf4 : /** * @brief This function handles ADC1 and ADC2 global interrupts. */ void ADC1_2_IRQHandler(void) { 800daf4: b510 push {r4, lr} /* USER CODE BEGIN ADC1_2_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800daf6: 4c09 ldr r4, [pc, #36] @ (800db1c ) 800daf8: 2201 movs r2, #1 800dafa: f44f 6100 mov.w r1, #2048 @ 0x800 800dafe: 4620 mov r0, r4 800db00: f003 f9d9 bl 8010eb6 /* USER CODE END ADC1_2_IRQn 0 */ HAL_ADC_IRQHandler(&hadc1); 800db04: 4806 ldr r0, [pc, #24] @ (800db20 ) 800db06: f001 f823 bl 800eb50 /* USER CODE BEGIN ADC1_2_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800db0a: 4620 mov r0, r4 /* USER CODE END ADC1_2_IRQn 1 */ } 800db0c: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800db10: 2200 movs r2, #0 800db12: f44f 6100 mov.w r1, #2048 @ 0x800 800db16: f003 b9ce b.w 8010eb6 800db1a: bf00 nop 800db1c: 40010c00 .word 0x40010c00 800db20: 20000290 .word 0x20000290 0800db24 : /** * @brief This function handles CAN1 RX0 interrupt. */ void CAN1_RX0_IRQHandler(void) { 800db24: b510 push {r4, lr} /* USER CODE BEGIN CAN1_RX0_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800db26: 4c09 ldr r4, [pc, #36] @ (800db4c ) 800db28: 2201 movs r2, #1 800db2a: f44f 6180 mov.w r1, #1024 @ 0x400 800db2e: 4620 mov r0, r4 800db30: f003 f9c1 bl 8010eb6 /* USER CODE END CAN1_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan1); 800db34: 4806 ldr r0, [pc, #24] @ (800db50 ) 800db36: f002 f847 bl 800fbc8 /* USER CODE BEGIN CAN1_RX0_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800db3a: 4620 mov r0, r4 /* USER CODE END CAN1_RX0_IRQn 1 */ } 800db3c: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800db40: 2200 movs r2, #0 800db42: f44f 6180 mov.w r1, #1024 @ 0x400 800db46: f003 b9b6 b.w 8010eb6 800db4a: bf00 nop 800db4c: 40010c00 .word 0x40010c00 800db50: 2000035c .word 0x2000035c 0800db54 : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 800db54: b510 push {r4, lr} /* USER CODE BEGIN TIM3_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800db56: 4c09 ldr r4, [pc, #36] @ (800db7c ) 800db58: 2201 movs r2, #1 800db5a: f44f 6100 mov.w r1, #2048 @ 0x800 800db5e: 4620 mov r0, r4 800db60: f003 f9a9 bl 8010eb6 /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 800db64: 4806 ldr r0, [pc, #24] @ (800db80 ) 800db66: f004 fd87 bl 8012678 /* USER CODE BEGIN TIM3_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800db6a: 4620 mov r0, r4 /* USER CODE END TIM3_IRQn 1 */ } 800db6c: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800db70: 2200 movs r2, #0 800db72: f44f 6100 mov.w r1, #2048 @ 0x800 800db76: f003 b99e b.w 8010eb6 800db7a: bf00 nop 800db7c: 40010c00 .word 0x40010c00 800db80: 200011dc .word 0x200011dc 0800db84 : void USART1_IRQHandler(void) { /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 800db84: 4801 ldr r0, [pc, #4] @ (800db8c ) 800db86: f005 be2d b.w 80137e4 800db8a: bf00 nop 800db8c: 200012b4 .word 0x200012b4 0800db90 : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 800db90: b510 push {r4, lr} /* USER CODE BEGIN USART2_IRQn 0 */ HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_SET); 800db92: 4c08 ldr r4, [pc, #32] @ (800dbb4 ) 800db94: 2201 movs r2, #1 800db96: 2120 movs r1, #32 800db98: 4620 mov r0, r4 800db9a: f003 f98c bl 8010eb6 /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 800db9e: 4806 ldr r0, [pc, #24] @ (800dbb8 ) 800dba0: f005 fe20 bl 80137e4 /* USER CODE BEGIN USART2_IRQn 1 */ HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_RESET); 800dba4: 4620 mov r0, r4 /* USER CODE END USART2_IRQn 1 */ } 800dba6: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_RESET); 800dbaa: 2200 movs r2, #0 800dbac: 2120 movs r1, #32 800dbae: f003 b982 b.w 8010eb6 800dbb2: bf00 nop 800dbb4: 40010800 .word 0x40010800 800dbb8: 200012fc .word 0x200012fc 0800dbbc : /** * @brief This function handles USART3 global interrupt. */ void USART3_IRQHandler(void) { 800dbbc: b510 push {r4, lr} /* USER CODE BEGIN USART3_IRQn 0 */ HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_SET); 800dbbe: 4c08 ldr r4, [pc, #32] @ (800dbe0 ) 800dbc0: 2201 movs r2, #1 800dbc2: 2140 movs r1, #64 @ 0x40 800dbc4: 4620 mov r0, r4 800dbc6: f003 f976 bl 8010eb6 /* USER CODE END USART3_IRQn 0 */ HAL_UART_IRQHandler(&huart3); 800dbca: 4806 ldr r0, [pc, #24] @ (800dbe4 ) 800dbcc: f005 fe0a bl 80137e4 /* USER CODE BEGIN USART3_IRQn 1 */ HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_RESET); 800dbd0: 4620 mov r0, r4 /* USER CODE END USART3_IRQn 1 */ } 800dbd2: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_RESET); 800dbd6: 2200 movs r2, #0 800dbd8: 2140 movs r1, #64 @ 0x40 800dbda: f003 b96c b.w 8010eb6 800dbde: bf00 nop 800dbe0: 40010800 .word 0x40010800 800dbe4: 20001344 .word 0x20001344 0800dbe8 : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 800dbe8: b510 push {r4, lr} /* USER CODE BEGIN UART5_IRQn 0 */ HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_SET); 800dbea: 4c08 ldr r4, [pc, #32] @ (800dc0c ) 800dbec: 2201 movs r2, #1 800dbee: 2104 movs r1, #4 800dbf0: 4620 mov r0, r4 800dbf2: f003 f960 bl 8010eb6 /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 800dbf6: 4806 ldr r0, [pc, #24] @ (800dc10 ) 800dbf8: f005 fdf4 bl 80137e4 /* USER CODE BEGIN UART5_IRQn 1 */ HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_RESET); 800dbfc: 4620 mov r0, r4 /* USER CODE END UART5_IRQn 1 */ } 800dbfe: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_RESET); 800dc02: 2200 movs r2, #0 800dc04: 2104 movs r1, #4 800dc06: f003 b956 b.w 8010eb6 800dc0a: bf00 nop 800dc0c: 40011000 .word 0x40011000 800dc10: 2000126c .word 0x2000126c 0800dc14 : /** * @brief This function handles CAN2 TX interrupt. */ void CAN2_TX_IRQHandler(void) { 800dc14: b510 push {r4, lr} /* USER CODE BEGIN CAN2_TX_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800dc16: 4c09 ldr r4, [pc, #36] @ (800dc3c ) 800dc18: 2201 movs r2, #1 800dc1a: f44f 6180 mov.w r1, #1024 @ 0x400 800dc1e: 4620 mov r0, r4 800dc20: f003 f949 bl 8010eb6 /* USER CODE END CAN2_TX_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800dc24: 4806 ldr r0, [pc, #24] @ (800dc40 ) 800dc26: f001 ffcf bl 800fbc8 /* USER CODE BEGIN CAN2_TX_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800dc2a: 4620 mov r0, r4 /* USER CODE END CAN2_TX_IRQn 1 */ } 800dc2c: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800dc30: 2200 movs r2, #0 800dc32: f44f 6180 mov.w r1, #1024 @ 0x400 800dc36: f003 b93e b.w 8010eb6 800dc3a: bf00 nop 800dc3c: 40010c00 .word 0x40010c00 800dc40: 20000384 .word 0x20000384 0800dc44 : /** * @brief This function handles CAN2 RX1 interrupt. */ void CAN2_RX1_IRQHandler(void) { 800dc44: b510 push {r4, lr} /* USER CODE BEGIN CAN2_RX1_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800dc46: 4c09 ldr r4, [pc, #36] @ (800dc6c ) 800dc48: 2201 movs r2, #1 800dc4a: f44f 6180 mov.w r1, #1024 @ 0x400 800dc4e: 4620 mov r0, r4 800dc50: f003 f931 bl 8010eb6 /* USER CODE END CAN2_RX1_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800dc54: 4806 ldr r0, [pc, #24] @ (800dc70 ) 800dc56: f001 ffb7 bl 800fbc8 /* USER CODE BEGIN CAN2_RX1_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800dc5a: 4620 mov r0, r4 /* USER CODE END CAN2_RX1_IRQn 1 */ } 800dc5c: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800dc60: 2200 movs r2, #0 800dc62: f44f 6180 mov.w r1, #1024 @ 0x400 800dc66: f003 b926 b.w 8010eb6 800dc6a: bf00 nop 800dc6c: 40010c00 .word 0x40010c00 800dc70: 20000384 .word 0x20000384 0800dc74 <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 800dc74: b480 push {r7} 800dc76: af00 add r7, sp, #0 return 1; 800dc78: 2301 movs r3, #1 } 800dc7a: 4618 mov r0, r3 800dc7c: 46bd mov sp, r7 800dc7e: bc80 pop {r7} 800dc80: 4770 bx lr 0800dc82 <_kill>: int _kill(int pid, int sig) { 800dc82: b580 push {r7, lr} 800dc84: b082 sub sp, #8 800dc86: af00 add r7, sp, #0 800dc88: 6078 str r0, [r7, #4] 800dc8a: 6039 str r1, [r7, #0] (void)pid; (void)sig; errno = EINVAL; 800dc8c: f007 fa3e bl 801510c <__errno> 800dc90: 4603 mov r3, r0 800dc92: 2216 movs r2, #22 800dc94: 601a str r2, [r3, #0] return -1; 800dc96: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800dc9a: 4618 mov r0, r3 800dc9c: 3708 adds r7, #8 800dc9e: 46bd mov sp, r7 800dca0: bd80 pop {r7, pc} 0800dca2 <_exit>: void _exit (int status) { 800dca2: b580 push {r7, lr} 800dca4: b082 sub sp, #8 800dca6: af00 add r7, sp, #0 800dca8: 6078 str r0, [r7, #4] _kill(status, -1); 800dcaa: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800dcae: 6878 ldr r0, [r7, #4] 800dcb0: f7ff ffe7 bl 800dc82 <_kill> while (1) {} /* Make sure we hang here */ 800dcb4: bf00 nop 800dcb6: e7fd b.n 800dcb4 <_exit+0x12> 0800dcb8 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 800dcb8: b580 push {r7, lr} 800dcba: b086 sub sp, #24 800dcbc: af00 add r7, sp, #0 800dcbe: 60f8 str r0, [r7, #12] 800dcc0: 60b9 str r1, [r7, #8] 800dcc2: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800dcc4: 2300 movs r3, #0 800dcc6: 617b str r3, [r7, #20] 800dcc8: e00a b.n 800dce0 <_read+0x28> { *ptr++ = __io_getchar(); 800dcca: f3af 8000 nop.w 800dcce: 4601 mov r1, r0 800dcd0: 68bb ldr r3, [r7, #8] 800dcd2: 1c5a adds r2, r3, #1 800dcd4: 60ba str r2, [r7, #8] 800dcd6: b2ca uxtb r2, r1 800dcd8: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 800dcda: 697b ldr r3, [r7, #20] 800dcdc: 3301 adds r3, #1 800dcde: 617b str r3, [r7, #20] 800dce0: 697a ldr r2, [r7, #20] 800dce2: 687b ldr r3, [r7, #4] 800dce4: 429a cmp r2, r3 800dce6: dbf0 blt.n 800dcca <_read+0x12> } return len; 800dce8: 687b ldr r3, [r7, #4] } 800dcea: 4618 mov r0, r3 800dcec: 3718 adds r7, #24 800dcee: 46bd mov sp, r7 800dcf0: bd80 pop {r7, pc} 0800dcf2 <_close>: } return len; } int _close(int file) { 800dcf2: b480 push {r7} 800dcf4: b083 sub sp, #12 800dcf6: af00 add r7, sp, #0 800dcf8: 6078 str r0, [r7, #4] (void)file; return -1; 800dcfa: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800dcfe: 4618 mov r0, r3 800dd00: 370c adds r7, #12 800dd02: 46bd mov sp, r7 800dd04: bc80 pop {r7} 800dd06: 4770 bx lr 0800dd08 <_fstat>: int _fstat(int file, struct stat *st) { 800dd08: b480 push {r7} 800dd0a: b083 sub sp, #12 800dd0c: af00 add r7, sp, #0 800dd0e: 6078 str r0, [r7, #4] 800dd10: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 800dd12: 683b ldr r3, [r7, #0] 800dd14: f44f 5200 mov.w r2, #8192 @ 0x2000 800dd18: 605a str r2, [r3, #4] return 0; 800dd1a: 2300 movs r3, #0 } 800dd1c: 4618 mov r0, r3 800dd1e: 370c adds r7, #12 800dd20: 46bd mov sp, r7 800dd22: bc80 pop {r7} 800dd24: 4770 bx lr 0800dd26 <_isatty>: int _isatty(int file) { 800dd26: b480 push {r7} 800dd28: b083 sub sp, #12 800dd2a: af00 add r7, sp, #0 800dd2c: 6078 str r0, [r7, #4] (void)file; return 1; 800dd2e: 2301 movs r3, #1 } 800dd30: 4618 mov r0, r3 800dd32: 370c adds r7, #12 800dd34: 46bd mov sp, r7 800dd36: bc80 pop {r7} 800dd38: 4770 bx lr 0800dd3a <_lseek>: int _lseek(int file, int ptr, int dir) { 800dd3a: b480 push {r7} 800dd3c: b085 sub sp, #20 800dd3e: af00 add r7, sp, #0 800dd40: 60f8 str r0, [r7, #12] 800dd42: 60b9 str r1, [r7, #8] 800dd44: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 800dd46: 2300 movs r3, #0 } 800dd48: 4618 mov r0, r3 800dd4a: 3714 adds r7, #20 800dd4c: 46bd mov sp, r7 800dd4e: bc80 pop {r7} 800dd50: 4770 bx lr ... 0800dd54 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 800dd54: b580 push {r7, lr} 800dd56: b086 sub sp, #24 800dd58: af00 add r7, sp, #0 800dd5a: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 800dd5c: 4a14 ldr r2, [pc, #80] @ (800ddb0 <_sbrk+0x5c>) 800dd5e: 4b15 ldr r3, [pc, #84] @ (800ddb4 <_sbrk+0x60>) 800dd60: 1ad3 subs r3, r2, r3 800dd62: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 800dd64: 697b ldr r3, [r7, #20] 800dd66: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 800dd68: 4b13 ldr r3, [pc, #76] @ (800ddb8 <_sbrk+0x64>) 800dd6a: 681b ldr r3, [r3, #0] 800dd6c: 2b00 cmp r3, #0 800dd6e: d102 bne.n 800dd76 <_sbrk+0x22> { __sbrk_heap_end = &_end; 800dd70: 4b11 ldr r3, [pc, #68] @ (800ddb8 <_sbrk+0x64>) 800dd72: 4a12 ldr r2, [pc, #72] @ (800ddbc <_sbrk+0x68>) 800dd74: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 800dd76: 4b10 ldr r3, [pc, #64] @ (800ddb8 <_sbrk+0x64>) 800dd78: 681a ldr r2, [r3, #0] 800dd7a: 687b ldr r3, [r7, #4] 800dd7c: 4413 add r3, r2 800dd7e: 693a ldr r2, [r7, #16] 800dd80: 429a cmp r2, r3 800dd82: d207 bcs.n 800dd94 <_sbrk+0x40> { errno = ENOMEM; 800dd84: f007 f9c2 bl 801510c <__errno> 800dd88: 4603 mov r3, r0 800dd8a: 220c movs r2, #12 800dd8c: 601a str r2, [r3, #0] return (void *)-1; 800dd8e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800dd92: e009 b.n 800dda8 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 800dd94: 4b08 ldr r3, [pc, #32] @ (800ddb8 <_sbrk+0x64>) 800dd96: 681b ldr r3, [r3, #0] 800dd98: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 800dd9a: 4b07 ldr r3, [pc, #28] @ (800ddb8 <_sbrk+0x64>) 800dd9c: 681a ldr r2, [r3, #0] 800dd9e: 687b ldr r3, [r7, #4] 800dda0: 4413 add r3, r2 800dda2: 4a05 ldr r2, [pc, #20] @ (800ddb8 <_sbrk+0x64>) 800dda4: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 800dda6: 68fb ldr r3, [r7, #12] } 800dda8: 4618 mov r0, r3 800ddaa: 3718 adds r7, #24 800ddac: 46bd mov sp, r7 800ddae: bd80 pop {r7, pc} 800ddb0: 20010000 .word 0x20010000 800ddb4: 00000400 .word 0x00000400 800ddb8: 200011d8 .word 0x200011d8 800ddbc: 200015f0 .word 0x200015f0 0800ddc0 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 800ddc0: b480 push {r7} 800ddc2: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 800ddc4: bf00 nop 800ddc6: 46bd mov sp, r7 800ddc8: bc80 pop {r7} 800ddca: 4770 bx lr 0800ddcc : TIM_HandleTypeDef htim3; TIM_HandleTypeDef htim4; /* TIM3 init function */ void MX_TIM3_Init(void) { 800ddcc: b580 push {r7, lr} 800ddce: b08e sub sp, #56 @ 0x38 800ddd0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800ddd2: f107 0328 add.w r3, r7, #40 @ 0x28 800ddd6: 2200 movs r2, #0 800ddd8: 601a str r2, [r3, #0] 800ddda: 605a str r2, [r3, #4] 800dddc: 609a str r2, [r3, #8] 800ddde: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800dde0: f107 0320 add.w r3, r7, #32 800dde4: 2200 movs r2, #0 800dde6: 601a str r2, [r3, #0] 800dde8: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800ddea: 1d3b adds r3, r7, #4 800ddec: 2200 movs r2, #0 800ddee: 601a str r2, [r3, #0] 800ddf0: 605a str r2, [r3, #4] 800ddf2: 609a str r2, [r3, #8] 800ddf4: 60da str r2, [r3, #12] 800ddf6: 611a str r2, [r3, #16] 800ddf8: 615a str r2, [r3, #20] 800ddfa: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 800ddfc: 4b38 ldr r3, [pc, #224] @ (800dee0 ) 800ddfe: 4a39 ldr r2, [pc, #228] @ (800dee4 ) 800de00: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 800de02: 4b37 ldr r3, [pc, #220] @ (800dee0 ) 800de04: 2200 movs r2, #0 800de06: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 800de08: 4b35 ldr r3, [pc, #212] @ (800dee0 ) 800de0a: 2200 movs r2, #0 800de0c: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 800de0e: 4b34 ldr r3, [pc, #208] @ (800dee0 ) 800de10: f64f 72ff movw r2, #65535 @ 0xffff 800de14: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800de16: 4b32 ldr r3, [pc, #200] @ (800dee0 ) 800de18: 2200 movs r2, #0 800de1a: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800de1c: 4b30 ldr r3, [pc, #192] @ (800dee0 ) 800de1e: 2200 movs r2, #0 800de20: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 800de22: 482f ldr r0, [pc, #188] @ (800dee0 ) 800de24: f004 f9d5 bl 80121d2 800de28: 4603 mov r3, r0 800de2a: 2b00 cmp r3, #0 800de2c: d001 beq.n 800de32 { Error_Handler(); 800de2e: f7fc ff51 bl 800acd4 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800de32: f44f 5380 mov.w r3, #4096 @ 0x1000 800de36: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 800de38: f107 0328 add.w r3, r7, #40 @ 0x28 800de3c: 4619 mov r1, r3 800de3e: 4828 ldr r0, [pc, #160] @ (800dee0 ) 800de40: f004 fe28 bl 8012a94 800de44: 4603 mov r3, r0 800de46: 2b00 cmp r3, #0 800de48: d001 beq.n 800de4e { Error_Handler(); 800de4a: f7fc ff43 bl 800acd4 } if (HAL_TIM_OC_Init(&htim3) != HAL_OK) 800de4e: 4824 ldr r0, [pc, #144] @ (800dee0 ) 800de50: f004 fa0e bl 8012270 800de54: 4603 mov r3, r0 800de56: 2b00 cmp r3, #0 800de58: d001 beq.n 800de5e { Error_Handler(); 800de5a: f7fc ff3b bl 800acd4 } if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 800de5e: 4820 ldr r0, [pc, #128] @ (800dee0 ) 800de60: f004 fb08 bl 8012474 800de64: 4603 mov r3, r0 800de66: 2b00 cmp r3, #0 800de68: d001 beq.n 800de6e { Error_Handler(); 800de6a: f7fc ff33 bl 800acd4 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_OC1; 800de6e: 2330 movs r3, #48 @ 0x30 800de70: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800de72: 2300 movs r3, #0 800de74: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800de76: f107 0320 add.w r3, r7, #32 800de7a: 4619 mov r1, r3 800de7c: 4818 ldr r0, [pc, #96] @ (800dee0 ) 800de7e: f005 f9b7 bl 80131f0 800de82: 4603 mov r3, r0 800de84: 2b00 cmp r3, #0 800de86: d001 beq.n 800de8c { Error_Handler(); 800de88: f7fc ff24 bl 800acd4 } sConfigOC.OCMode = TIM_OCMODE_TIMING; 800de8c: 2300 movs r3, #0 800de8e: 607b str r3, [r7, #4] sConfigOC.Pulse = 1; 800de90: 2301 movs r3, #1 800de92: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800de94: 2300 movs r3, #0 800de96: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800de98: 2300 movs r3, #0 800de9a: 617b str r3, [r7, #20] if (HAL_TIM_OC_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 800de9c: 1d3b adds r3, r7, #4 800de9e: 2200 movs r2, #0 800dea0: 4619 mov r1, r3 800dea2: 480f ldr r0, [pc, #60] @ (800dee0 ) 800dea4: f004 fcd8 bl 8012858 800dea8: 4603 mov r3, r0 800deaa: 2b00 cmp r3, #0 800deac: d001 beq.n 800deb2 { Error_Handler(); 800deae: f7fc ff11 bl 800acd4 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800deb2: 2360 movs r3, #96 @ 0x60 800deb4: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800deb6: 2300 movs r3, #0 800deb8: 60bb str r3, [r7, #8] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800deba: 1d3b adds r3, r7, #4 800debc: 2204 movs r2, #4 800debe: 4619 mov r1, r3 800dec0: 4807 ldr r0, [pc, #28] @ (800dee0 ) 800dec2: f004 fd25 bl 8012910 800dec6: 4603 mov r3, r0 800dec8: 2b00 cmp r3, #0 800deca: d001 beq.n 800ded0 { Error_Handler(); 800decc: f7fc ff02 bl 800acd4 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 800ded0: 4803 ldr r0, [pc, #12] @ (800dee0 ) 800ded2: f000 f8cf bl 800e074 } 800ded6: bf00 nop 800ded8: 3738 adds r7, #56 @ 0x38 800deda: 46bd mov sp, r7 800dedc: bd80 pop {r7, pc} 800dede: bf00 nop 800dee0: 200011dc .word 0x200011dc 800dee4: 40000400 .word 0x40000400 0800dee8 : /* TIM4 init function */ void MX_TIM4_Init(void) { 800dee8: b580 push {r7, lr} 800deea: b08e sub sp, #56 @ 0x38 800deec: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800deee: f107 0328 add.w r3, r7, #40 @ 0x28 800def2: 2200 movs r2, #0 800def4: 601a str r2, [r3, #0] 800def6: 605a str r2, [r3, #4] 800def8: 609a str r2, [r3, #8] 800defa: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800defc: f107 0320 add.w r3, r7, #32 800df00: 2200 movs r2, #0 800df02: 601a str r2, [r3, #0] 800df04: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800df06: 1d3b adds r3, r7, #4 800df08: 2200 movs r2, #0 800df0a: 601a str r2, [r3, #0] 800df0c: 605a str r2, [r3, #4] 800df0e: 609a str r2, [r3, #8] 800df10: 60da str r2, [r3, #12] 800df12: 611a str r2, [r3, #16] 800df14: 615a str r2, [r3, #20] 800df16: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM4_Init 1 */ /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; 800df18: 4b37 ldr r3, [pc, #220] @ (800dff8 ) 800df1a: 4a38 ldr r2, [pc, #224] @ (800dffc ) 800df1c: 601a str r2, [r3, #0] htim4.Init.Prescaler = 720; 800df1e: 4b36 ldr r3, [pc, #216] @ (800dff8 ) 800df20: f44f 7234 mov.w r2, #720 @ 0x2d0 800df24: 605a str r2, [r3, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 800df26: 4b34 ldr r3, [pc, #208] @ (800dff8 ) 800df28: 2200 movs r2, #0 800df2a: 609a str r2, [r3, #8] htim4.Init.Period = 100; 800df2c: 4b32 ldr r3, [pc, #200] @ (800dff8 ) 800df2e: 2264 movs r2, #100 @ 0x64 800df30: 60da str r2, [r3, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800df32: 4b31 ldr r3, [pc, #196] @ (800dff8 ) 800df34: 2200 movs r2, #0 800df36: 611a str r2, [r3, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800df38: 4b2f ldr r3, [pc, #188] @ (800dff8 ) 800df3a: 2200 movs r2, #0 800df3c: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 800df3e: 482e ldr r0, [pc, #184] @ (800dff8 ) 800df40: f004 f947 bl 80121d2 800df44: 4603 mov r3, r0 800df46: 2b00 cmp r3, #0 800df48: d001 beq.n 800df4e { Error_Handler(); 800df4a: f7fc fec3 bl 800acd4 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800df4e: f44f 5380 mov.w r3, #4096 @ 0x1000 800df52: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 800df54: f107 0328 add.w r3, r7, #40 @ 0x28 800df58: 4619 mov r1, r3 800df5a: 4827 ldr r0, [pc, #156] @ (800dff8 ) 800df5c: f004 fd9a bl 8012a94 800df60: 4603 mov r3, r0 800df62: 2b00 cmp r3, #0 800df64: d001 beq.n 800df6a { Error_Handler(); 800df66: f7fc feb5 bl 800acd4 } if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) 800df6a: 4823 ldr r0, [pc, #140] @ (800dff8 ) 800df6c: f004 fa82 bl 8012474 800df70: 4603 mov r3, r0 800df72: 2b00 cmp r3, #0 800df74: d001 beq.n 800df7a { Error_Handler(); 800df76: f7fc fead bl 800acd4 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800df7a: 2300 movs r3, #0 800df7c: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800df7e: 2300 movs r3, #0 800df80: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 800df82: f107 0320 add.w r3, r7, #32 800df86: 4619 mov r1, r3 800df88: 481b ldr r0, [pc, #108] @ (800dff8 ) 800df8a: f005 f931 bl 80131f0 800df8e: 4603 mov r3, r0 800df90: 2b00 cmp r3, #0 800df92: d001 beq.n 800df98 { Error_Handler(); 800df94: f7fc fe9e bl 800acd4 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800df98: 2360 movs r3, #96 @ 0x60 800df9a: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800df9c: 2300 movs r3, #0 800df9e: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800dfa0: 2300 movs r3, #0 800dfa2: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800dfa4: 2300 movs r3, #0 800dfa6: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800dfa8: 1d3b adds r3, r7, #4 800dfaa: 2204 movs r2, #4 800dfac: 4619 mov r1, r3 800dfae: 4812 ldr r0, [pc, #72] @ (800dff8 ) 800dfb0: f004 fcae bl 8012910 800dfb4: 4603 mov r3, r0 800dfb6: 2b00 cmp r3, #0 800dfb8: d001 beq.n 800dfbe { Error_Handler(); 800dfba: f7fc fe8b bl 800acd4 } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 800dfbe: 1d3b adds r3, r7, #4 800dfc0: 2208 movs r2, #8 800dfc2: 4619 mov r1, r3 800dfc4: 480c ldr r0, [pc, #48] @ (800dff8 ) 800dfc6: f004 fca3 bl 8012910 800dfca: 4603 mov r3, r0 800dfcc: 2b00 cmp r3, #0 800dfce: d001 beq.n 800dfd4 { Error_Handler(); 800dfd0: f7fc fe80 bl 800acd4 } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 800dfd4: 1d3b adds r3, r7, #4 800dfd6: 220c movs r2, #12 800dfd8: 4619 mov r1, r3 800dfda: 4807 ldr r0, [pc, #28] @ (800dff8 ) 800dfdc: f004 fc98 bl 8012910 800dfe0: 4603 mov r3, r0 800dfe2: 2b00 cmp r3, #0 800dfe4: d001 beq.n 800dfea { Error_Handler(); 800dfe6: f7fc fe75 bl 800acd4 } /* USER CODE BEGIN TIM4_Init 2 */ /* USER CODE END TIM4_Init 2 */ HAL_TIM_MspPostInit(&htim4); 800dfea: 4803 ldr r0, [pc, #12] @ (800dff8 ) 800dfec: f000 f842 bl 800e074 } 800dff0: bf00 nop 800dff2: 3738 adds r7, #56 @ 0x38 800dff4: 46bd mov sp, r7 800dff6: bd80 pop {r7, pc} 800dff8: 20001224 .word 0x20001224 800dffc: 40000800 .word 0x40000800 0800e000 : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 800e000: b580 push {r7, lr} 800e002: b084 sub sp, #16 800e004: af00 add r7, sp, #0 800e006: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM3) 800e008: 687b ldr r3, [r7, #4] 800e00a: 681b ldr r3, [r3, #0] 800e00c: 4a16 ldr r2, [pc, #88] @ (800e068 ) 800e00e: 4293 cmp r3, r2 800e010: d114 bne.n 800e03c { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 800e012: 4b16 ldr r3, [pc, #88] @ (800e06c ) 800e014: 69db ldr r3, [r3, #28] 800e016: 4a15 ldr r2, [pc, #84] @ (800e06c ) 800e018: f043 0302 orr.w r3, r3, #2 800e01c: 61d3 str r3, [r2, #28] 800e01e: 4b13 ldr r3, [pc, #76] @ (800e06c ) 800e020: 69db ldr r3, [r3, #28] 800e022: f003 0302 and.w r3, r3, #2 800e026: 60fb str r3, [r7, #12] 800e028: 68fb ldr r3, [r7, #12] /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 6, 0); 800e02a: 2200 movs r2, #0 800e02c: 2106 movs r1, #6 800e02e: 201d movs r0, #29 800e030: f002 f8c5 bl 80101be HAL_NVIC_EnableIRQ(TIM3_IRQn); 800e034: 201d movs r0, #29 800e036: f002 f8de bl 80101f6 __HAL_RCC_TIM4_CLK_ENABLE(); /* USER CODE BEGIN TIM4_MspInit 1 */ /* USER CODE END TIM4_MspInit 1 */ } } 800e03a: e010 b.n 800e05e else if(tim_baseHandle->Instance==TIM4) 800e03c: 687b ldr r3, [r7, #4] 800e03e: 681b ldr r3, [r3, #0] 800e040: 4a0b ldr r2, [pc, #44] @ (800e070 ) 800e042: 4293 cmp r3, r2 800e044: d10b bne.n 800e05e __HAL_RCC_TIM4_CLK_ENABLE(); 800e046: 4b09 ldr r3, [pc, #36] @ (800e06c ) 800e048: 69db ldr r3, [r3, #28] 800e04a: 4a08 ldr r2, [pc, #32] @ (800e06c ) 800e04c: f043 0304 orr.w r3, r3, #4 800e050: 61d3 str r3, [r2, #28] 800e052: 4b06 ldr r3, [pc, #24] @ (800e06c ) 800e054: 69db ldr r3, [r3, #28] 800e056: f003 0304 and.w r3, r3, #4 800e05a: 60bb str r3, [r7, #8] 800e05c: 68bb ldr r3, [r7, #8] } 800e05e: bf00 nop 800e060: 3710 adds r7, #16 800e062: 46bd mov sp, r7 800e064: bd80 pop {r7, pc} 800e066: bf00 nop 800e068: 40000400 .word 0x40000400 800e06c: 40021000 .word 0x40021000 800e070: 40000800 .word 0x40000800 0800e074 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 800e074: b580 push {r7, lr} 800e076: b08a sub sp, #40 @ 0x28 800e078: af00 add r7, sp, #0 800e07a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800e07c: f107 0314 add.w r3, r7, #20 800e080: 2200 movs r2, #0 800e082: 601a str r2, [r3, #0] 800e084: 605a str r2, [r3, #4] 800e086: 609a str r2, [r3, #8] 800e088: 60da str r2, [r3, #12] if(timHandle->Instance==TIM3) 800e08a: 687b ldr r3, [r7, #4] 800e08c: 681b ldr r3, [r3, #0] 800e08e: 4a26 ldr r2, [pc, #152] @ (800e128 ) 800e090: 4293 cmp r3, r2 800e092: d118 bne.n 800e0c6 { /* USER CODE BEGIN TIM3_MspPostInit 0 */ /* USER CODE END TIM3_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800e094: 4b25 ldr r3, [pc, #148] @ (800e12c ) 800e096: 699b ldr r3, [r3, #24] 800e098: 4a24 ldr r2, [pc, #144] @ (800e12c ) 800e09a: f043 0304 orr.w r3, r3, #4 800e09e: 6193 str r3, [r2, #24] 800e0a0: 4b22 ldr r3, [pc, #136] @ (800e12c ) 800e0a2: 699b ldr r3, [r3, #24] 800e0a4: f003 0304 and.w r3, r3, #4 800e0a8: 613b str r3, [r7, #16] 800e0aa: 693b ldr r3, [r7, #16] /**TIM3 GPIO Configuration PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = CP_PWM_Pin; 800e0ac: 2380 movs r3, #128 @ 0x80 800e0ae: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800e0b0: 2302 movs r3, #2 800e0b2: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800e0b4: 2302 movs r3, #2 800e0b6: 623b str r3, [r7, #32] HAL_GPIO_Init(CP_PWM_GPIO_Port, &GPIO_InitStruct); 800e0b8: f107 0314 add.w r3, r7, #20 800e0bc: 4619 mov r1, r3 800e0be: 481c ldr r0, [pc, #112] @ (800e130 ) 800e0c0: f002 fd5e bl 8010b80 /* USER CODE BEGIN TIM4_MspPostInit 1 */ /* USER CODE END TIM4_MspPostInit 1 */ } } 800e0c4: e02b b.n 800e11e else if(timHandle->Instance==TIM4) 800e0c6: 687b ldr r3, [r7, #4] 800e0c8: 681b ldr r3, [r3, #0] 800e0ca: 4a1a ldr r2, [pc, #104] @ (800e134 ) 800e0cc: 4293 cmp r3, r2 800e0ce: d126 bne.n 800e11e __HAL_RCC_GPIOD_CLK_ENABLE(); 800e0d0: 4b16 ldr r3, [pc, #88] @ (800e12c ) 800e0d2: 699b ldr r3, [r3, #24] 800e0d4: 4a15 ldr r2, [pc, #84] @ (800e12c ) 800e0d6: f043 0320 orr.w r3, r3, #32 800e0da: 6193 str r3, [r2, #24] 800e0dc: 4b13 ldr r3, [pc, #76] @ (800e12c ) 800e0de: 699b ldr r3, [r3, #24] 800e0e0: f003 0320 and.w r3, r3, #32 800e0e4: 60fb str r3, [r7, #12] 800e0e6: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; 800e0e8: f44f 4360 mov.w r3, #57344 @ 0xe000 800e0ec: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800e0ee: 2302 movs r3, #2 800e0f0: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800e0f2: 2302 movs r3, #2 800e0f4: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800e0f6: f107 0314 add.w r3, r7, #20 800e0fa: 4619 mov r1, r3 800e0fc: 480e ldr r0, [pc, #56] @ (800e138 ) 800e0fe: f002 fd3f bl 8010b80 __HAL_AFIO_REMAP_TIM4_ENABLE(); 800e102: 4b0e ldr r3, [pc, #56] @ (800e13c ) 800e104: 685b ldr r3, [r3, #4] 800e106: 627b str r3, [r7, #36] @ 0x24 800e108: 6a7b ldr r3, [r7, #36] @ 0x24 800e10a: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800e10e: 627b str r3, [r7, #36] @ 0x24 800e110: 6a7b ldr r3, [r7, #36] @ 0x24 800e112: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800e116: 627b str r3, [r7, #36] @ 0x24 800e118: 4a08 ldr r2, [pc, #32] @ (800e13c ) 800e11a: 6a7b ldr r3, [r7, #36] @ 0x24 800e11c: 6053 str r3, [r2, #4] } 800e11e: bf00 nop 800e120: 3728 adds r7, #40 @ 0x28 800e122: 46bd mov sp, r7 800e124: bd80 pop {r7, pc} 800e126: bf00 nop 800e128: 40000400 .word 0x40000400 800e12c: 40021000 .word 0x40021000 800e130: 40010800 .word 0x40010800 800e134: 40000800 .word 0x40000800 800e138: 40011400 .word 0x40011400 800e13c: 40010000 .word 0x40010000 0800e140 : DMA_HandleTypeDef hdma_usart3_rx; DMA_HandleTypeDef hdma_usart3_tx; /* UART5 init function */ void MX_UART5_Init(void) { 800e140: b580 push {r7, lr} 800e142: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 800e144: 4b11 ldr r3, [pc, #68] @ (800e18c ) 800e146: 4a12 ldr r2, [pc, #72] @ (800e190 ) 800e148: 601a str r2, [r3, #0] huart5.Init.BaudRate = 9600; 800e14a: 4b10 ldr r3, [pc, #64] @ (800e18c ) 800e14c: f44f 5216 mov.w r2, #9600 @ 0x2580 800e150: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 800e152: 4b0e ldr r3, [pc, #56] @ (800e18c ) 800e154: 2200 movs r2, #0 800e156: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 800e158: 4b0c ldr r3, [pc, #48] @ (800e18c ) 800e15a: 2200 movs r2, #0 800e15c: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 800e15e: 4b0b ldr r3, [pc, #44] @ (800e18c ) 800e160: 2200 movs r2, #0 800e162: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 800e164: 4b09 ldr r3, [pc, #36] @ (800e18c ) 800e166: 220c movs r2, #12 800e168: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800e16a: 4b08 ldr r3, [pc, #32] @ (800e18c ) 800e16c: 2200 movs r2, #0 800e16e: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 800e170: 4b06 ldr r3, [pc, #24] @ (800e18c ) 800e172: 2200 movs r2, #0 800e174: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 800e176: 4805 ldr r0, [pc, #20] @ (800e18c ) 800e178: f005 f8b2 bl 80132e0 800e17c: 4603 mov r3, r0 800e17e: 2b00 cmp r3, #0 800e180: d001 beq.n 800e186 { Error_Handler(); 800e182: f7fc fda7 bl 800acd4 } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 800e186: bf00 nop 800e188: bd80 pop {r7, pc} 800e18a: bf00 nop 800e18c: 2000126c .word 0x2000126c 800e190: 40005000 .word 0x40005000 0800e194 : /* USART1 init function */ void MX_USART1_UART_Init(void) { 800e194: b580 push {r7, lr} 800e196: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 800e198: 4b11 ldr r3, [pc, #68] @ (800e1e0 ) 800e19a: 4a12 ldr r2, [pc, #72] @ (800e1e4 ) 800e19c: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800e19e: 4b10 ldr r3, [pc, #64] @ (800e1e0 ) 800e1a0: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800e1a4: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800e1a6: 4b0e ldr r3, [pc, #56] @ (800e1e0 ) 800e1a8: 2200 movs r2, #0 800e1aa: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 800e1ac: 4b0c ldr r3, [pc, #48] @ (800e1e0 ) 800e1ae: 2200 movs r2, #0 800e1b0: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800e1b2: 4b0b ldr r3, [pc, #44] @ (800e1e0 ) 800e1b4: 2200 movs r2, #0 800e1b6: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 800e1b8: 4b09 ldr r3, [pc, #36] @ (800e1e0 ) 800e1ba: 220c movs r2, #12 800e1bc: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800e1be: 4b08 ldr r3, [pc, #32] @ (800e1e0 ) 800e1c0: 2200 movs r2, #0 800e1c2: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800e1c4: 4b06 ldr r3, [pc, #24] @ (800e1e0 ) 800e1c6: 2200 movs r2, #0 800e1c8: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 800e1ca: 4805 ldr r0, [pc, #20] @ (800e1e0 ) 800e1cc: f005 f888 bl 80132e0 800e1d0: 4603 mov r3, r0 800e1d2: 2b00 cmp r3, #0 800e1d4: d001 beq.n 800e1da { Error_Handler(); 800e1d6: f7fc fd7d bl 800acd4 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 800e1da: bf00 nop 800e1dc: bd80 pop {r7, pc} 800e1de: bf00 nop 800e1e0: 200012b4 .word 0x200012b4 800e1e4: 40013800 .word 0x40013800 0800e1e8 : /* USART2 init function */ void MX_USART2_UART_Init(void) { 800e1e8: b580 push {r7, lr} 800e1ea: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 800e1ec: 4b11 ldr r3, [pc, #68] @ (800e234 ) 800e1ee: 4a12 ldr r2, [pc, #72] @ (800e238 ) 800e1f0: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 800e1f2: 4b10 ldr r3, [pc, #64] @ (800e234 ) 800e1f4: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800e1f8: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 800e1fa: 4b0e ldr r3, [pc, #56] @ (800e234 ) 800e1fc: 2200 movs r2, #0 800e1fe: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 800e200: 4b0c ldr r3, [pc, #48] @ (800e234 ) 800e202: 2200 movs r2, #0 800e204: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800e206: 4b0b ldr r3, [pc, #44] @ (800e234 ) 800e208: 2200 movs r2, #0 800e20a: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 800e20c: 4b09 ldr r3, [pc, #36] @ (800e234 ) 800e20e: 220c movs r2, #12 800e210: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800e212: 4b08 ldr r3, [pc, #32] @ (800e234 ) 800e214: 2200 movs r2, #0 800e216: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 800e218: 4b06 ldr r3, [pc, #24] @ (800e234 ) 800e21a: 2200 movs r2, #0 800e21c: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 800e21e: 4805 ldr r0, [pc, #20] @ (800e234 ) 800e220: f005 f85e bl 80132e0 800e224: 4603 mov r3, r0 800e226: 2b00 cmp r3, #0 800e228: d001 beq.n 800e22e { Error_Handler(); 800e22a: f7fc fd53 bl 800acd4 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 800e22e: bf00 nop 800e230: bd80 pop {r7, pc} 800e232: bf00 nop 800e234: 200012fc .word 0x200012fc 800e238: 40004400 .word 0x40004400 0800e23c : /* USART3 init function */ void MX_USART3_UART_Init(void) { 800e23c: b580 push {r7, lr} 800e23e: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 800e240: 4b11 ldr r3, [pc, #68] @ (800e288 ) 800e242: 4a12 ldr r2, [pc, #72] @ (800e28c ) 800e244: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 800e246: 4b10 ldr r3, [pc, #64] @ (800e288 ) 800e248: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800e24c: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 800e24e: 4b0e ldr r3, [pc, #56] @ (800e288 ) 800e250: 2200 movs r2, #0 800e252: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 800e254: 4b0c ldr r3, [pc, #48] @ (800e288 ) 800e256: 2200 movs r2, #0 800e258: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 800e25a: 4b0b ldr r3, [pc, #44] @ (800e288 ) 800e25c: 2200 movs r2, #0 800e25e: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 800e260: 4b09 ldr r3, [pc, #36] @ (800e288 ) 800e262: 220c movs r2, #12 800e264: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800e266: 4b08 ldr r3, [pc, #32] @ (800e288 ) 800e268: 2200 movs r2, #0 800e26a: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 800e26c: 4b06 ldr r3, [pc, #24] @ (800e288 ) 800e26e: 2200 movs r2, #0 800e270: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart3) != HAL_OK) 800e272: 4805 ldr r0, [pc, #20] @ (800e288 ) 800e274: f005 f834 bl 80132e0 800e278: 4603 mov r3, r0 800e27a: 2b00 cmp r3, #0 800e27c: d001 beq.n 800e282 { Error_Handler(); 800e27e: f7fc fd29 bl 800acd4 } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 800e282: bf00 nop 800e284: bd80 pop {r7, pc} 800e286: bf00 nop 800e288: 20001344 .word 0x20001344 800e28c: 40004800 .word 0x40004800 0800e290 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 800e290: b580 push {r7, lr} 800e292: b092 sub sp, #72 @ 0x48 800e294: af00 add r7, sp, #0 800e296: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800e298: f107 0330 add.w r3, r7, #48 @ 0x30 800e29c: 2200 movs r2, #0 800e29e: 601a str r2, [r3, #0] 800e2a0: 605a str r2, [r3, #4] 800e2a2: 609a str r2, [r3, #8] 800e2a4: 60da str r2, [r3, #12] if(uartHandle->Instance==UART5) 800e2a6: 687b ldr r3, [r7, #4] 800e2a8: 681b ldr r3, [r3, #0] 800e2aa: 4a92 ldr r2, [pc, #584] @ (800e4f4 ) 800e2ac: 4293 cmp r3, r2 800e2ae: d145 bne.n 800e33c { /* USER CODE BEGIN UART5_MspInit 0 */ /* USER CODE END UART5_MspInit 0 */ /* UART5 clock enable */ __HAL_RCC_UART5_CLK_ENABLE(); 800e2b0: 4b91 ldr r3, [pc, #580] @ (800e4f8 ) 800e2b2: 69db ldr r3, [r3, #28] 800e2b4: 4a90 ldr r2, [pc, #576] @ (800e4f8 ) 800e2b6: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800e2ba: 61d3 str r3, [r2, #28] 800e2bc: 4b8e ldr r3, [pc, #568] @ (800e4f8 ) 800e2be: 69db ldr r3, [r3, #28] 800e2c0: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800e2c4: 62fb str r3, [r7, #44] @ 0x2c 800e2c6: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 800e2c8: 4b8b ldr r3, [pc, #556] @ (800e4f8 ) 800e2ca: 699b ldr r3, [r3, #24] 800e2cc: 4a8a ldr r2, [pc, #552] @ (800e4f8 ) 800e2ce: f043 0310 orr.w r3, r3, #16 800e2d2: 6193 str r3, [r2, #24] 800e2d4: 4b88 ldr r3, [pc, #544] @ (800e4f8 ) 800e2d6: 699b ldr r3, [r3, #24] 800e2d8: f003 0310 and.w r3, r3, #16 800e2dc: 62bb str r3, [r7, #40] @ 0x28 800e2de: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOD_CLK_ENABLE(); 800e2e0: 4b85 ldr r3, [pc, #532] @ (800e4f8 ) 800e2e2: 699b ldr r3, [r3, #24] 800e2e4: 4a84 ldr r2, [pc, #528] @ (800e4f8 ) 800e2e6: f043 0320 orr.w r3, r3, #32 800e2ea: 6193 str r3, [r2, #24] 800e2ec: 4b82 ldr r3, [pc, #520] @ (800e4f8 ) 800e2ee: 699b ldr r3, [r3, #24] 800e2f0: f003 0320 and.w r3, r3, #32 800e2f4: 627b str r3, [r7, #36] @ 0x24 800e2f6: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART5 GPIO Configuration PC12 ------> UART5_TX PD2 ------> UART5_RX */ GPIO_InitStruct.Pin = HEATER_Pin; 800e2f8: f44f 5380 mov.w r3, #4096 @ 0x1000 800e2fc: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800e2fe: 2302 movs r3, #2 800e300: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800e302: 2303 movs r3, #3 800e304: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(HEATER_GPIO_Port, &GPIO_InitStruct); 800e306: f107 0330 add.w r3, r7, #48 @ 0x30 800e30a: 4619 mov r1, r3 800e30c: 487b ldr r0, [pc, #492] @ (800e4fc ) 800e30e: f002 fc37 bl 8010b80 GPIO_InitStruct.Pin = GPIO_PIN_2; 800e312: 2304 movs r3, #4 800e314: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800e316: 2300 movs r3, #0 800e318: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800e31a: 2300 movs r3, #0 800e31c: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800e31e: f107 0330 add.w r3, r7, #48 @ 0x30 800e322: 4619 mov r1, r3 800e324: 4876 ldr r0, [pc, #472] @ (800e500 ) 800e326: f002 fc2b bl 8010b80 /* UART5 interrupt Init */ HAL_NVIC_SetPriority(UART5_IRQn, 5, 0); 800e32a: 2200 movs r2, #0 800e32c: 2105 movs r1, #5 800e32e: 2035 movs r0, #53 @ 0x35 800e330: f001 ff45 bl 80101be HAL_NVIC_EnableIRQ(UART5_IRQn); 800e334: 2035 movs r0, #53 @ 0x35 800e336: f001 ff5e bl 80101f6 HAL_NVIC_EnableIRQ(USART3_IRQn); /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 800e33a: e193 b.n 800e664 else if(uartHandle->Instance==USART1) 800e33c: 687b ldr r3, [r7, #4] 800e33e: 681b ldr r3, [r3, #0] 800e340: 4a70 ldr r2, [pc, #448] @ (800e504 ) 800e342: 4293 cmp r3, r2 800e344: d13a bne.n 800e3bc __HAL_RCC_USART1_CLK_ENABLE(); 800e346: 4b6c ldr r3, [pc, #432] @ (800e4f8 ) 800e348: 699b ldr r3, [r3, #24] 800e34a: 4a6b ldr r2, [pc, #428] @ (800e4f8 ) 800e34c: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800e350: 6193 str r3, [r2, #24] 800e352: 4b69 ldr r3, [pc, #420] @ (800e4f8 ) 800e354: 699b ldr r3, [r3, #24] 800e356: f403 4380 and.w r3, r3, #16384 @ 0x4000 800e35a: 623b str r3, [r7, #32] 800e35c: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 800e35e: 4b66 ldr r3, [pc, #408] @ (800e4f8 ) 800e360: 699b ldr r3, [r3, #24] 800e362: 4a65 ldr r2, [pc, #404] @ (800e4f8 ) 800e364: f043 0304 orr.w r3, r3, #4 800e368: 6193 str r3, [r2, #24] 800e36a: 4b63 ldr r3, [pc, #396] @ (800e4f8 ) 800e36c: 699b ldr r3, [r3, #24] 800e36e: f003 0304 and.w r3, r3, #4 800e372: 61fb str r3, [r7, #28] 800e374: 69fb ldr r3, [r7, #28] GPIO_InitStruct.Pin = GPIO_PIN_9; 800e376: f44f 7300 mov.w r3, #512 @ 0x200 800e37a: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800e37c: 2302 movs r3, #2 800e37e: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800e380: 2303 movs r3, #3 800e382: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800e384: f107 0330 add.w r3, r7, #48 @ 0x30 800e388: 4619 mov r1, r3 800e38a: 485f ldr r0, [pc, #380] @ (800e508 ) 800e38c: f002 fbf8 bl 8010b80 GPIO_InitStruct.Pin = GPIO_PIN_10; 800e390: f44f 6380 mov.w r3, #1024 @ 0x400 800e394: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800e396: 2300 movs r3, #0 800e398: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800e39a: 2300 movs r3, #0 800e39c: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800e39e: f107 0330 add.w r3, r7, #48 @ 0x30 800e3a2: 4619 mov r1, r3 800e3a4: 4858 ldr r0, [pc, #352] @ (800e508 ) 800e3a6: f002 fbeb bl 8010b80 HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 800e3aa: 2200 movs r2, #0 800e3ac: 2105 movs r1, #5 800e3ae: 2025 movs r0, #37 @ 0x25 800e3b0: f001 ff05 bl 80101be HAL_NVIC_EnableIRQ(USART1_IRQn); 800e3b4: 2025 movs r0, #37 @ 0x25 800e3b6: f001 ff1e bl 80101f6 } 800e3ba: e153 b.n 800e664 else if(uartHandle->Instance==USART2) 800e3bc: 687b ldr r3, [r7, #4] 800e3be: 681b ldr r3, [r3, #0] 800e3c0: 4a52 ldr r2, [pc, #328] @ (800e50c ) 800e3c2: 4293 cmp r3, r2 800e3c4: f040 80ae bne.w 800e524 __HAL_RCC_USART2_CLK_ENABLE(); 800e3c8: 4b4b ldr r3, [pc, #300] @ (800e4f8 ) 800e3ca: 69db ldr r3, [r3, #28] 800e3cc: 4a4a ldr r2, [pc, #296] @ (800e4f8 ) 800e3ce: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800e3d2: 61d3 str r3, [r2, #28] 800e3d4: 4b48 ldr r3, [pc, #288] @ (800e4f8 ) 800e3d6: 69db ldr r3, [r3, #28] 800e3d8: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e3dc: 61bb str r3, [r7, #24] 800e3de: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOD_CLK_ENABLE(); 800e3e0: 4b45 ldr r3, [pc, #276] @ (800e4f8 ) 800e3e2: 699b ldr r3, [r3, #24] 800e3e4: 4a44 ldr r2, [pc, #272] @ (800e4f8 ) 800e3e6: f043 0320 orr.w r3, r3, #32 800e3ea: 6193 str r3, [r2, #24] 800e3ec: 4b42 ldr r3, [pc, #264] @ (800e4f8 ) 800e3ee: 699b ldr r3, [r3, #24] 800e3f0: f003 0320 and.w r3, r3, #32 800e3f4: 617b str r3, [r7, #20] 800e3f6: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_5; 800e3f8: 2320 movs r3, #32 800e3fa: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800e3fc: 2302 movs r3, #2 800e3fe: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800e400: 2303 movs r3, #3 800e402: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800e404: f107 0330 add.w r3, r7, #48 @ 0x30 800e408: 4619 mov r1, r3 800e40a: 483d ldr r0, [pc, #244] @ (800e500 ) 800e40c: f002 fbb8 bl 8010b80 GPIO_InitStruct.Pin = GPIO_PIN_6; 800e410: 2340 movs r3, #64 @ 0x40 800e412: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800e414: 2300 movs r3, #0 800e416: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800e418: 2300 movs r3, #0 800e41a: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800e41c: f107 0330 add.w r3, r7, #48 @ 0x30 800e420: 4619 mov r1, r3 800e422: 4837 ldr r0, [pc, #220] @ (800e500 ) 800e424: f002 fbac bl 8010b80 __HAL_AFIO_REMAP_USART2_ENABLE(); 800e428: 4b39 ldr r3, [pc, #228] @ (800e510 ) 800e42a: 685b ldr r3, [r3, #4] 800e42c: 643b str r3, [r7, #64] @ 0x40 800e42e: 6c3b ldr r3, [r7, #64] @ 0x40 800e430: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800e434: 643b str r3, [r7, #64] @ 0x40 800e436: 6c3b ldr r3, [r7, #64] @ 0x40 800e438: f043 0308 orr.w r3, r3, #8 800e43c: 643b str r3, [r7, #64] @ 0x40 800e43e: 4a34 ldr r2, [pc, #208] @ (800e510 ) 800e440: 6c3b ldr r3, [r7, #64] @ 0x40 800e442: 6053 str r3, [r2, #4] hdma_usart2_rx.Instance = DMA1_Channel6; 800e444: 4b33 ldr r3, [pc, #204] @ (800e514 ) 800e446: 4a34 ldr r2, [pc, #208] @ (800e518 ) 800e448: 601a str r2, [r3, #0] hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 800e44a: 4b32 ldr r3, [pc, #200] @ (800e514 ) 800e44c: 2200 movs r2, #0 800e44e: 605a str r2, [r3, #4] hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 800e450: 4b30 ldr r3, [pc, #192] @ (800e514 ) 800e452: 2200 movs r2, #0 800e454: 609a str r2, [r3, #8] hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; 800e456: 4b2f ldr r3, [pc, #188] @ (800e514 ) 800e458: 2280 movs r2, #128 @ 0x80 800e45a: 60da str r2, [r3, #12] hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800e45c: 4b2d ldr r3, [pc, #180] @ (800e514 ) 800e45e: 2200 movs r2, #0 800e460: 611a str r2, [r3, #16] hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800e462: 4b2c ldr r3, [pc, #176] @ (800e514 ) 800e464: 2200 movs r2, #0 800e466: 615a str r2, [r3, #20] hdma_usart2_rx.Init.Mode = DMA_NORMAL; 800e468: 4b2a ldr r3, [pc, #168] @ (800e514 ) 800e46a: 2200 movs r2, #0 800e46c: 619a str r2, [r3, #24] hdma_usart2_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH; 800e46e: 4b29 ldr r3, [pc, #164] @ (800e514 ) 800e470: f44f 5240 mov.w r2, #12288 @ 0x3000 800e474: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) 800e476: 4827 ldr r0, [pc, #156] @ (800e514 ) 800e478: f001 fef4 bl 8010264 800e47c: 4603 mov r3, r0 800e47e: 2b00 cmp r3, #0 800e480: d001 beq.n 800e486 Error_Handler(); 800e482: f7fc fc27 bl 800acd4 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); 800e486: 687b ldr r3, [r7, #4] 800e488: 4a22 ldr r2, [pc, #136] @ (800e514 ) 800e48a: 63da str r2, [r3, #60] @ 0x3c 800e48c: 4a21 ldr r2, [pc, #132] @ (800e514 ) 800e48e: 687b ldr r3, [r7, #4] 800e490: 6253 str r3, [r2, #36] @ 0x24 hdma_usart2_tx.Instance = DMA1_Channel7; 800e492: 4b22 ldr r3, [pc, #136] @ (800e51c ) 800e494: 4a22 ldr r2, [pc, #136] @ (800e520 ) 800e496: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 800e498: 4b20 ldr r3, [pc, #128] @ (800e51c ) 800e49a: 2210 movs r2, #16 800e49c: 605a str r2, [r3, #4] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800e49e: 4b1f ldr r3, [pc, #124] @ (800e51c ) 800e4a0: 2200 movs r2, #0 800e4a2: 609a str r2, [r3, #8] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; 800e4a4: 4b1d ldr r3, [pc, #116] @ (800e51c ) 800e4a6: 2280 movs r2, #128 @ 0x80 800e4a8: 60da str r2, [r3, #12] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800e4aa: 4b1c ldr r3, [pc, #112] @ (800e51c ) 800e4ac: 2200 movs r2, #0 800e4ae: 611a str r2, [r3, #16] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800e4b0: 4b1a ldr r3, [pc, #104] @ (800e51c ) 800e4b2: 2200 movs r2, #0 800e4b4: 615a str r2, [r3, #20] hdma_usart2_tx.Init.Mode = DMA_NORMAL; 800e4b6: 4b19 ldr r3, [pc, #100] @ (800e51c ) 800e4b8: 2200 movs r2, #0 800e4ba: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_HIGH; 800e4bc: 4b17 ldr r3, [pc, #92] @ (800e51c ) 800e4be: f44f 5200 mov.w r2, #8192 @ 0x2000 800e4c2: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 800e4c4: 4815 ldr r0, [pc, #84] @ (800e51c ) 800e4c6: f001 fecd bl 8010264 800e4ca: 4603 mov r3, r0 800e4cc: 2b00 cmp r3, #0 800e4ce: d001 beq.n 800e4d4 Error_Handler(); 800e4d0: f7fc fc00 bl 800acd4 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); 800e4d4: 687b ldr r3, [r7, #4] 800e4d6: 4a11 ldr r2, [pc, #68] @ (800e51c ) 800e4d8: 639a str r2, [r3, #56] @ 0x38 800e4da: 4a10 ldr r2, [pc, #64] @ (800e51c ) 800e4dc: 687b ldr r3, [r7, #4] 800e4de: 6253 str r3, [r2, #36] @ 0x24 HAL_NVIC_SetPriority(USART2_IRQn, 2, 0); 800e4e0: 2200 movs r2, #0 800e4e2: 2102 movs r1, #2 800e4e4: 2026 movs r0, #38 @ 0x26 800e4e6: f001 fe6a bl 80101be HAL_NVIC_EnableIRQ(USART2_IRQn); 800e4ea: 2026 movs r0, #38 @ 0x26 800e4ec: f001 fe83 bl 80101f6 } 800e4f0: e0b8 b.n 800e664 800e4f2: bf00 nop 800e4f4: 40005000 .word 0x40005000 800e4f8: 40021000 .word 0x40021000 800e4fc: 40011000 .word 0x40011000 800e500: 40011400 .word 0x40011400 800e504: 40013800 .word 0x40013800 800e508: 40010800 .word 0x40010800 800e50c: 40004400 .word 0x40004400 800e510: 40010000 .word 0x40010000 800e514: 2000138c .word 0x2000138c 800e518: 4002006c .word 0x4002006c 800e51c: 200013d0 .word 0x200013d0 800e520: 40020080 .word 0x40020080 else if(uartHandle->Instance==USART3) 800e524: 687b ldr r3, [r7, #4] 800e526: 681b ldr r3, [r3, #0] 800e528: 4a50 ldr r2, [pc, #320] @ (800e66c ) 800e52a: 4293 cmp r3, r2 800e52c: f040 809a bne.w 800e664 __HAL_RCC_USART3_CLK_ENABLE(); 800e530: 4b4f ldr r3, [pc, #316] @ (800e670 ) 800e532: 69db ldr r3, [r3, #28] 800e534: 4a4e ldr r2, [pc, #312] @ (800e670 ) 800e536: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800e53a: 61d3 str r3, [r2, #28] 800e53c: 4b4c ldr r3, [pc, #304] @ (800e670 ) 800e53e: 69db ldr r3, [r3, #28] 800e540: f403 2380 and.w r3, r3, #262144 @ 0x40000 800e544: 613b str r3, [r7, #16] 800e546: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 800e548: 4b49 ldr r3, [pc, #292] @ (800e670 ) 800e54a: 699b ldr r3, [r3, #24] 800e54c: 4a48 ldr r2, [pc, #288] @ (800e670 ) 800e54e: f043 0310 orr.w r3, r3, #16 800e552: 6193 str r3, [r2, #24] 800e554: 4b46 ldr r3, [pc, #280] @ (800e670 ) 800e556: 699b ldr r3, [r3, #24] 800e558: f003 0310 and.w r3, r3, #16 800e55c: 60fb str r3, [r7, #12] 800e55e: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_10; 800e560: f44f 6380 mov.w r3, #1024 @ 0x400 800e564: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800e566: 2302 movs r3, #2 800e568: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800e56a: 2303 movs r3, #3 800e56c: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800e56e: f107 0330 add.w r3, r7, #48 @ 0x30 800e572: 4619 mov r1, r3 800e574: 483f ldr r0, [pc, #252] @ (800e674 ) 800e576: f002 fb03 bl 8010b80 GPIO_InitStruct.Pin = GPIO_PIN_11; 800e57a: f44f 6300 mov.w r3, #2048 @ 0x800 800e57e: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800e580: 2300 movs r3, #0 800e582: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800e584: 2300 movs r3, #0 800e586: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800e588: f107 0330 add.w r3, r7, #48 @ 0x30 800e58c: 4619 mov r1, r3 800e58e: 4839 ldr r0, [pc, #228] @ (800e674 ) 800e590: f002 faf6 bl 8010b80 __HAL_AFIO_REMAP_USART3_PARTIAL(); 800e594: 4b38 ldr r3, [pc, #224] @ (800e678 ) 800e596: 685b ldr r3, [r3, #4] 800e598: 647b str r3, [r7, #68] @ 0x44 800e59a: 6c7b ldr r3, [r7, #68] @ 0x44 800e59c: f023 0330 bic.w r3, r3, #48 @ 0x30 800e5a0: 647b str r3, [r7, #68] @ 0x44 800e5a2: 6c7b ldr r3, [r7, #68] @ 0x44 800e5a4: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800e5a8: 647b str r3, [r7, #68] @ 0x44 800e5aa: 6c7b ldr r3, [r7, #68] @ 0x44 800e5ac: f043 0310 orr.w r3, r3, #16 800e5b0: 647b str r3, [r7, #68] @ 0x44 800e5b2: 4a31 ldr r2, [pc, #196] @ (800e678 ) 800e5b4: 6c7b ldr r3, [r7, #68] @ 0x44 800e5b6: 6053 str r3, [r2, #4] hdma_usart3_rx.Instance = DMA1_Channel3; 800e5b8: 4b30 ldr r3, [pc, #192] @ (800e67c ) 800e5ba: 4a31 ldr r2, [pc, #196] @ (800e680 ) 800e5bc: 601a str r2, [r3, #0] hdma_usart3_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 800e5be: 4b2f ldr r3, [pc, #188] @ (800e67c ) 800e5c0: 2200 movs r2, #0 800e5c2: 605a str r2, [r3, #4] hdma_usart3_rx.Init.PeriphInc = DMA_PINC_DISABLE; 800e5c4: 4b2d ldr r3, [pc, #180] @ (800e67c ) 800e5c6: 2200 movs r2, #0 800e5c8: 609a str r2, [r3, #8] hdma_usart3_rx.Init.MemInc = DMA_MINC_ENABLE; 800e5ca: 4b2c ldr r3, [pc, #176] @ (800e67c ) 800e5cc: 2280 movs r2, #128 @ 0x80 800e5ce: 60da str r2, [r3, #12] hdma_usart3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800e5d0: 4b2a ldr r3, [pc, #168] @ (800e67c ) 800e5d2: 2200 movs r2, #0 800e5d4: 611a str r2, [r3, #16] hdma_usart3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800e5d6: 4b29 ldr r3, [pc, #164] @ (800e67c ) 800e5d8: 2200 movs r2, #0 800e5da: 615a str r2, [r3, #20] hdma_usart3_rx.Init.Mode = DMA_NORMAL; 800e5dc: 4b27 ldr r3, [pc, #156] @ (800e67c ) 800e5de: 2200 movs r2, #0 800e5e0: 619a str r2, [r3, #24] hdma_usart3_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH; 800e5e2: 4b26 ldr r3, [pc, #152] @ (800e67c ) 800e5e4: f44f 5240 mov.w r2, #12288 @ 0x3000 800e5e8: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart3_rx) != HAL_OK) 800e5ea: 4824 ldr r0, [pc, #144] @ (800e67c ) 800e5ec: f001 fe3a bl 8010264 800e5f0: 4603 mov r3, r0 800e5f2: 2b00 cmp r3, #0 800e5f4: d001 beq.n 800e5fa Error_Handler(); 800e5f6: f7fc fb6d bl 800acd4 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart3_rx); 800e5fa: 687b ldr r3, [r7, #4] 800e5fc: 4a1f ldr r2, [pc, #124] @ (800e67c ) 800e5fe: 63da str r2, [r3, #60] @ 0x3c 800e600: 4a1e ldr r2, [pc, #120] @ (800e67c ) 800e602: 687b ldr r3, [r7, #4] 800e604: 6253 str r3, [r2, #36] @ 0x24 hdma_usart3_tx.Instance = DMA1_Channel2; 800e606: 4b1f ldr r3, [pc, #124] @ (800e684 ) 800e608: 4a1f ldr r2, [pc, #124] @ (800e688 ) 800e60a: 601a str r2, [r3, #0] hdma_usart3_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 800e60c: 4b1d ldr r3, [pc, #116] @ (800e684 ) 800e60e: 2210 movs r2, #16 800e610: 605a str r2, [r3, #4] hdma_usart3_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800e612: 4b1c ldr r3, [pc, #112] @ (800e684 ) 800e614: 2200 movs r2, #0 800e616: 609a str r2, [r3, #8] hdma_usart3_tx.Init.MemInc = DMA_MINC_ENABLE; 800e618: 4b1a ldr r3, [pc, #104] @ (800e684 ) 800e61a: 2280 movs r2, #128 @ 0x80 800e61c: 60da str r2, [r3, #12] hdma_usart3_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800e61e: 4b19 ldr r3, [pc, #100] @ (800e684 ) 800e620: 2200 movs r2, #0 800e622: 611a str r2, [r3, #16] hdma_usart3_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800e624: 4b17 ldr r3, [pc, #92] @ (800e684 ) 800e626: 2200 movs r2, #0 800e628: 615a str r2, [r3, #20] hdma_usart3_tx.Init.Mode = DMA_NORMAL; 800e62a: 4b16 ldr r3, [pc, #88] @ (800e684 ) 800e62c: 2200 movs r2, #0 800e62e: 619a str r2, [r3, #24] hdma_usart3_tx.Init.Priority = DMA_PRIORITY_HIGH; 800e630: 4b14 ldr r3, [pc, #80] @ (800e684 ) 800e632: f44f 5200 mov.w r2, #8192 @ 0x2000 800e636: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart3_tx) != HAL_OK) 800e638: 4812 ldr r0, [pc, #72] @ (800e684 ) 800e63a: f001 fe13 bl 8010264 800e63e: 4603 mov r3, r0 800e640: 2b00 cmp r3, #0 800e642: d001 beq.n 800e648 Error_Handler(); 800e644: f7fc fb46 bl 800acd4 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart3_tx); 800e648: 687b ldr r3, [r7, #4] 800e64a: 4a0e ldr r2, [pc, #56] @ (800e684 ) 800e64c: 639a str r2, [r3, #56] @ 0x38 800e64e: 4a0d ldr r2, [pc, #52] @ (800e684 ) 800e650: 687b ldr r3, [r7, #4] 800e652: 6253 str r3, [r2, #36] @ 0x24 HAL_NVIC_SetPriority(USART3_IRQn, 2, 0); 800e654: 2200 movs r2, #0 800e656: 2102 movs r1, #2 800e658: 2027 movs r0, #39 @ 0x27 800e65a: f001 fdb0 bl 80101be HAL_NVIC_EnableIRQ(USART3_IRQn); 800e65e: 2027 movs r0, #39 @ 0x27 800e660: f001 fdc9 bl 80101f6 } 800e664: bf00 nop 800e666: 3748 adds r7, #72 @ 0x48 800e668: 46bd mov sp, r7 800e66a: bd80 pop {r7, pc} 800e66c: 40004800 .word 0x40004800 800e670: 40021000 .word 0x40021000 800e674: 40011000 .word 0x40011000 800e678: 40010000 .word 0x40010000 800e67c: 20001414 .word 0x20001414 800e680: 40020030 .word 0x40020030 800e684: 20001458 .word 0x20001458 800e688: 4002001c .word 0x4002001c 0800e68c : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 800e68c: f7ff fb98 bl 800ddc0 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 800e690: 480b ldr r0, [pc, #44] @ (800e6c0 ) ldr r1, =_edata 800e692: 490c ldr r1, [pc, #48] @ (800e6c4 ) ldr r2, =_sidata 800e694: 4a0c ldr r2, [pc, #48] @ (800e6c8 ) movs r3, #0 800e696: 2300 movs r3, #0 b LoopCopyDataInit 800e698: e002 b.n 800e6a0 0800e69a : CopyDataInit: ldr r4, [r2, r3] 800e69a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800e69c: 50c4 str r4, [r0, r3] adds r3, r3, #4 800e69e: 3304 adds r3, #4 0800e6a0 : LoopCopyDataInit: adds r4, r0, r3 800e6a0: 18c4 adds r4, r0, r3 cmp r4, r1 800e6a2: 428c cmp r4, r1 bcc CopyDataInit 800e6a4: d3f9 bcc.n 800e69a /* Zero fill the bss segment. */ ldr r2, =_sbss 800e6a6: 4a09 ldr r2, [pc, #36] @ (800e6cc ) ldr r4, =_ebss 800e6a8: 4c09 ldr r4, [pc, #36] @ (800e6d0 ) movs r3, #0 800e6aa: 2300 movs r3, #0 b LoopFillZerobss 800e6ac: e001 b.n 800e6b2 0800e6ae : FillZerobss: str r3, [r2] 800e6ae: 6013 str r3, [r2, #0] adds r2, r2, #4 800e6b0: 3204 adds r2, #4 0800e6b2 : LoopFillZerobss: cmp r2, r4 800e6b2: 42a2 cmp r2, r4 bcc FillZerobss 800e6b4: d3fb bcc.n 800e6ae /* Call static constructors */ bl __libc_init_array 800e6b6: f006 fd2f bl 8015118 <__libc_init_array> /* Call the application's entry point.*/ bl main 800e6ba: f7fc fa21 bl 800ab00
bx lr 800e6be: 4770 bx lr ldr r0, =_sdata 800e6c0: 20000000 .word 0x20000000 ldr r1, =_edata 800e6c4: 20000258 .word 0x20000258 ldr r2, =_sidata 800e6c8: 08018144 .word 0x08018144 ldr r2, =_sbss 800e6cc: 20000258 .word 0x20000258 ldr r4, =_ebss 800e6d0: 200015ec .word 0x200015ec 0800e6d4 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 800e6d4: e7fe b.n 800e6d4 ... 0800e6d8 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800e6d8: b580 push {r7, lr} 800e6da: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 800e6dc: 4b08 ldr r3, [pc, #32] @ (800e700 ) 800e6de: 681b ldr r3, [r3, #0] 800e6e0: 4a07 ldr r2, [pc, #28] @ (800e700 ) 800e6e2: f043 0310 orr.w r3, r3, #16 800e6e6: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800e6e8: 2003 movs r0, #3 800e6ea: f001 fd5d bl 80101a8 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800e6ee: 200f movs r0, #15 800e6f0: f000 f808 bl 800e704 /* Init the low level hardware */ HAL_MspInit(); 800e6f4: f7ff f98a bl 800da0c /* Return function status */ return HAL_OK; 800e6f8: 2300 movs r3, #0 } 800e6fa: 4618 mov r0, r3 800e6fc: bd80 pop {r7, pc} 800e6fe: bf00 nop 800e700: 40022000 .word 0x40022000 0800e704 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800e704: b580 push {r7, lr} 800e706: b082 sub sp, #8 800e708: af00 add r7, sp, #0 800e70a: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 800e70c: 4b12 ldr r3, [pc, #72] @ (800e758 ) 800e70e: 681a ldr r2, [r3, #0] 800e710: 4b12 ldr r3, [pc, #72] @ (800e75c ) 800e712: 781b ldrb r3, [r3, #0] 800e714: 4619 mov r1, r3 800e716: f44f 737a mov.w r3, #1000 @ 0x3e8 800e71a: fbb3 f3f1 udiv r3, r3, r1 800e71e: fbb2 f3f3 udiv r3, r2, r3 800e722: 4618 mov r0, r3 800e724: f001 fd75 bl 8010212 800e728: 4603 mov r3, r0 800e72a: 2b00 cmp r3, #0 800e72c: d001 beq.n 800e732 { return HAL_ERROR; 800e72e: 2301 movs r3, #1 800e730: e00e b.n 800e750 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800e732: 687b ldr r3, [r7, #4] 800e734: 2b0f cmp r3, #15 800e736: d80a bhi.n 800e74e { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800e738: 2200 movs r2, #0 800e73a: 6879 ldr r1, [r7, #4] 800e73c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800e740: f001 fd3d bl 80101be uwTickPrio = TickPriority; 800e744: 4a06 ldr r2, [pc, #24] @ (800e760 ) 800e746: 687b ldr r3, [r7, #4] 800e748: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800e74a: 2300 movs r3, #0 800e74c: e000 b.n 800e750 return HAL_ERROR; 800e74e: 2301 movs r3, #1 } 800e750: 4618 mov r0, r3 800e752: 3708 adds r7, #8 800e754: 46bd mov sp, r7 800e756: bd80 pop {r7, pc} 800e758: 20000084 .word 0x20000084 800e75c: 2000008c .word 0x2000008c 800e760: 20000088 .word 0x20000088 0800e764 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800e764: b480 push {r7} 800e766: af00 add r7, sp, #0 uwTick += uwTickFreq; 800e768: 4b05 ldr r3, [pc, #20] @ (800e780 ) 800e76a: 781b ldrb r3, [r3, #0] 800e76c: 461a mov r2, r3 800e76e: 4b05 ldr r3, [pc, #20] @ (800e784 ) 800e770: 681b ldr r3, [r3, #0] 800e772: 4413 add r3, r2 800e774: 4a03 ldr r2, [pc, #12] @ (800e784 ) 800e776: 6013 str r3, [r2, #0] } 800e778: bf00 nop 800e77a: 46bd mov sp, r7 800e77c: bc80 pop {r7} 800e77e: 4770 bx lr 800e780: 2000008c .word 0x2000008c 800e784: 2000149c .word 0x2000149c 0800e788 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 800e788: b480 push {r7} 800e78a: af00 add r7, sp, #0 return uwTick; 800e78c: 4b02 ldr r3, [pc, #8] @ (800e798 ) 800e78e: 681b ldr r3, [r3, #0] } 800e790: 4618 mov r0, r3 800e792: 46bd mov sp, r7 800e794: bc80 pop {r7} 800e796: 4770 bx lr 800e798: 2000149c .word 0x2000149c 0800e79c : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 800e79c: b580 push {r7, lr} 800e79e: b084 sub sp, #16 800e7a0: af00 add r7, sp, #0 800e7a2: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800e7a4: f7ff fff0 bl 800e788 800e7a8: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800e7aa: 687b ldr r3, [r7, #4] 800e7ac: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800e7ae: 68fb ldr r3, [r7, #12] 800e7b0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800e7b4: d005 beq.n 800e7c2 { wait += (uint32_t)(uwTickFreq); 800e7b6: 4b0a ldr r3, [pc, #40] @ (800e7e0 ) 800e7b8: 781b ldrb r3, [r3, #0] 800e7ba: 461a mov r2, r3 800e7bc: 68fb ldr r3, [r7, #12] 800e7be: 4413 add r3, r2 800e7c0: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 800e7c2: bf00 nop 800e7c4: f7ff ffe0 bl 800e788 800e7c8: 4602 mov r2, r0 800e7ca: 68bb ldr r3, [r7, #8] 800e7cc: 1ad3 subs r3, r2, r3 800e7ce: 68fa ldr r2, [r7, #12] 800e7d0: 429a cmp r2, r3 800e7d2: d8f7 bhi.n 800e7c4 { } } 800e7d4: bf00 nop 800e7d6: bf00 nop 800e7d8: 3710 adds r7, #16 800e7da: 46bd mov sp, r7 800e7dc: bd80 pop {r7, pc} 800e7de: bf00 nop 800e7e0: 2000008c .word 0x2000008c 0800e7e4 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 800e7e4: b580 push {r7, lr} 800e7e6: b086 sub sp, #24 800e7e8: af00 add r7, sp, #0 800e7ea: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e7ec: 2300 movs r3, #0 800e7ee: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 800e7f0: 2300 movs r3, #0 800e7f2: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 800e7f4: 2300 movs r3, #0 800e7f6: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 800e7f8: 2300 movs r3, #0 800e7fa: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 800e7fc: 687b ldr r3, [r7, #4] 800e7fe: 2b00 cmp r3, #0 800e800: d101 bne.n 800e806 { return HAL_ERROR; 800e802: 2301 movs r3, #1 800e804: e0be b.n 800e984 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 800e806: 687b ldr r3, [r7, #4] 800e808: 689b ldr r3, [r3, #8] 800e80a: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 800e80c: 687b ldr r3, [r7, #4] 800e80e: 6a9b ldr r3, [r3, #40] @ 0x28 800e810: 2b00 cmp r3, #0 800e812: d109 bne.n 800e828 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 800e814: 687b ldr r3, [r7, #4] 800e816: 2200 movs r2, #0 800e818: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 800e81a: 687b ldr r3, [r7, #4] 800e81c: 2200 movs r2, #0 800e81e: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800e822: 6878 ldr r0, [r7, #4] 800e824: f7fa ff3e bl 80096a4 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800e828: 6878 ldr r0, [r7, #4] 800e82a: f000 fbbd bl 800efa8 800e82e: 4603 mov r3, r0 800e830: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 800e832: 687b ldr r3, [r7, #4] 800e834: 6a9b ldr r3, [r3, #40] @ 0x28 800e836: f003 0310 and.w r3, r3, #16 800e83a: 2b00 cmp r3, #0 800e83c: f040 8099 bne.w 800e972 800e840: 7dfb ldrb r3, [r7, #23] 800e842: 2b00 cmp r3, #0 800e844: f040 8095 bne.w 800e972 (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e848: 687b ldr r3, [r7, #4] 800e84a: 6a9b ldr r3, [r3, #40] @ 0x28 800e84c: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800e850: f023 0302 bic.w r3, r3, #2 800e854: f043 0202 orr.w r2, r3, #2 800e858: 687b ldr r3, [r7, #4] 800e85a: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 800e85c: 687b ldr r3, [r7, #4] 800e85e: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800e860: 687b ldr r3, [r7, #4] 800e862: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 800e864: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 800e866: 687b ldr r3, [r7, #4] 800e868: 7b1b ldrb r3, [r3, #12] 800e86a: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800e86c: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 800e86e: 68ba ldr r2, [r7, #8] 800e870: 4313 orrs r3, r2 800e872: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 800e874: 687b ldr r3, [r7, #4] 800e876: 689b ldr r3, [r3, #8] 800e878: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e87c: d003 beq.n 800e886 800e87e: 687b ldr r3, [r7, #4] 800e880: 689b ldr r3, [r3, #8] 800e882: 2b01 cmp r3, #1 800e884: d102 bne.n 800e88c 800e886: f44f 7380 mov.w r3, #256 @ 0x100 800e88a: e000 b.n 800e88e 800e88c: 2300 movs r3, #0 800e88e: 693a ldr r2, [r7, #16] 800e890: 4313 orrs r3, r2 800e892: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 800e894: 687b ldr r3, [r7, #4] 800e896: 7d1b ldrb r3, [r3, #20] 800e898: 2b01 cmp r3, #1 800e89a: d119 bne.n 800e8d0 { if (hadc->Init.ContinuousConvMode == DISABLE) 800e89c: 687b ldr r3, [r7, #4] 800e89e: 7b1b ldrb r3, [r3, #12] 800e8a0: 2b00 cmp r3, #0 800e8a2: d109 bne.n 800e8b8 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 800e8a4: 687b ldr r3, [r7, #4] 800e8a6: 699b ldr r3, [r3, #24] 800e8a8: 3b01 subs r3, #1 800e8aa: 035a lsls r2, r3, #13 800e8ac: 693b ldr r3, [r7, #16] 800e8ae: 4313 orrs r3, r2 800e8b0: f443 6300 orr.w r3, r3, #2048 @ 0x800 800e8b4: 613b str r3, [r7, #16] 800e8b6: e00b b.n 800e8d0 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800e8b8: 687b ldr r3, [r7, #4] 800e8ba: 6a9b ldr r3, [r3, #40] @ 0x28 800e8bc: f043 0220 orr.w r2, r3, #32 800e8c0: 687b ldr r3, [r7, #4] 800e8c2: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e8c4: 687b ldr r3, [r7, #4] 800e8c6: 6adb ldr r3, [r3, #44] @ 0x2c 800e8c8: f043 0201 orr.w r2, r3, #1 800e8cc: 687b ldr r3, [r7, #4] 800e8ce: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 800e8d0: 687b ldr r3, [r7, #4] 800e8d2: 681b ldr r3, [r3, #0] 800e8d4: 685b ldr r3, [r3, #4] 800e8d6: f423 4169 bic.w r1, r3, #59648 @ 0xe900 800e8da: 687b ldr r3, [r7, #4] 800e8dc: 681b ldr r3, [r3, #0] 800e8de: 693a ldr r2, [r7, #16] 800e8e0: 430a orrs r2, r1 800e8e2: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 800e8e4: 687b ldr r3, [r7, #4] 800e8e6: 681b ldr r3, [r3, #0] 800e8e8: 689a ldr r2, [r3, #8] 800e8ea: 4b28 ldr r3, [pc, #160] @ (800e98c ) 800e8ec: 4013 ands r3, r2 800e8ee: 687a ldr r2, [r7, #4] 800e8f0: 6812 ldr r2, [r2, #0] 800e8f2: 68b9 ldr r1, [r7, #8] 800e8f4: 430b orrs r3, r1 800e8f6: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 800e8f8: 687b ldr r3, [r7, #4] 800e8fa: 689b ldr r3, [r3, #8] 800e8fc: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e900: d003 beq.n 800e90a 800e902: 687b ldr r3, [r7, #4] 800e904: 689b ldr r3, [r3, #8] 800e906: 2b01 cmp r3, #1 800e908: d104 bne.n 800e914 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 800e90a: 687b ldr r3, [r7, #4] 800e90c: 691b ldr r3, [r3, #16] 800e90e: 3b01 subs r3, #1 800e910: 051b lsls r3, r3, #20 800e912: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 800e914: 687b ldr r3, [r7, #4] 800e916: 681b ldr r3, [r3, #0] 800e918: 6adb ldr r3, [r3, #44] @ 0x2c 800e91a: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 800e91e: 687b ldr r3, [r7, #4] 800e920: 681b ldr r3, [r3, #0] 800e922: 68fa ldr r2, [r7, #12] 800e924: 430a orrs r2, r1 800e926: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800e928: 687b ldr r3, [r7, #4] 800e92a: 681b ldr r3, [r3, #0] 800e92c: 689a ldr r2, [r3, #8] 800e92e: 4b18 ldr r3, [pc, #96] @ (800e990 ) 800e930: 4013 ands r3, r2 800e932: 68ba ldr r2, [r7, #8] 800e934: 429a cmp r2, r3 800e936: d10b bne.n 800e950 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 800e938: 687b ldr r3, [r7, #4] 800e93a: 2200 movs r2, #0 800e93c: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e93e: 687b ldr r3, [r7, #4] 800e940: 6a9b ldr r3, [r3, #40] @ 0x28 800e942: f023 0303 bic.w r3, r3, #3 800e946: f043 0201 orr.w r2, r3, #1 800e94a: 687b ldr r3, [r7, #4] 800e94c: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800e94e: e018 b.n 800e982 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800e950: 687b ldr r3, [r7, #4] 800e952: 6a9b ldr r3, [r3, #40] @ 0x28 800e954: f023 0312 bic.w r3, r3, #18 800e958: f043 0210 orr.w r2, r3, #16 800e95c: 687b ldr r3, [r7, #4] 800e95e: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e960: 687b ldr r3, [r7, #4] 800e962: 6adb ldr r3, [r3, #44] @ 0x2c 800e964: f043 0201 orr.w r2, r3, #1 800e968: 687b ldr r3, [r7, #4] 800e96a: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 800e96c: 2301 movs r3, #1 800e96e: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800e970: e007 b.n 800e982 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800e972: 687b ldr r3, [r7, #4] 800e974: 6a9b ldr r3, [r3, #40] @ 0x28 800e976: f043 0210 orr.w r2, r3, #16 800e97a: 687b ldr r3, [r7, #4] 800e97c: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800e97e: 2301 movs r3, #1 800e980: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800e982: 7dfb ldrb r3, [r7, #23] } 800e984: 4618 mov r0, r3 800e986: 3718 adds r7, #24 800e988: 46bd mov sp, r7 800e98a: bd80 pop {r7, pc} 800e98c: ffe1f7fd .word 0xffe1f7fd 800e990: ff1f0efe .word 0xff1f0efe 0800e994 : * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { 800e994: b580 push {r7, lr} 800e996: b086 sub sp, #24 800e998: af00 add r7, sp, #0 800e99a: 60f8 str r0, [r7, #12] 800e99c: 60b9 str r1, [r7, #8] 800e99e: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e9a0: 2300 movs r3, #0 800e9a2: 75fb strb r3, [r7, #23] assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); /* Verification if multimode is disabled (for devices with several ADC) */ /* If multimode is enabled, dedicated function multimode conversion */ /* start DMA must be used. */ if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) 800e9a4: 68fb ldr r3, [r7, #12] 800e9a6: 681b ldr r3, [r3, #0] 800e9a8: 4a64 ldr r2, [pc, #400] @ (800eb3c ) 800e9aa: 4293 cmp r3, r2 800e9ac: d004 beq.n 800e9b8 800e9ae: 68fb ldr r3, [r7, #12] 800e9b0: 681b ldr r3, [r3, #0] 800e9b2: 4a63 ldr r2, [pc, #396] @ (800eb40 ) 800e9b4: 4293 cmp r3, r2 800e9b6: d106 bne.n 800e9c6 800e9b8: 4b60 ldr r3, [pc, #384] @ (800eb3c ) 800e9ba: 685b ldr r3, [r3, #4] 800e9bc: f403 2370 and.w r3, r3, #983040 @ 0xf0000 800e9c0: 2b00 cmp r3, #0 800e9c2: f040 80b3 bne.w 800eb2c { /* Process locked */ __HAL_LOCK(hadc); 800e9c6: 68fb ldr r3, [r7, #12] 800e9c8: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e9cc: 2b01 cmp r3, #1 800e9ce: d101 bne.n 800e9d4 800e9d0: 2302 movs r3, #2 800e9d2: e0ae b.n 800eb32 800e9d4: 68fb ldr r3, [r7, #12] 800e9d6: 2201 movs r2, #1 800e9d8: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 800e9dc: 68f8 ldr r0, [r7, #12] 800e9de: f000 fa89 bl 800eef4 800e9e2: 4603 mov r3, r0 800e9e4: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800e9e6: 7dfb ldrb r3, [r7, #23] 800e9e8: 2b00 cmp r3, #0 800e9ea: f040 809a bne.w 800eb22 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 800e9ee: 68fb ldr r3, [r7, #12] 800e9f0: 6a9b ldr r3, [r3, #40] @ 0x28 800e9f2: f423 6370 bic.w r3, r3, #3840 @ 0xf00 800e9f6: f023 0301 bic.w r3, r3, #1 800e9fa: f443 7280 orr.w r2, r3, #256 @ 0x100 800e9fe: 68fb ldr r3, [r7, #12] 800ea00: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 800ea02: 68fb ldr r3, [r7, #12] 800ea04: 681b ldr r3, [r3, #0] 800ea06: 4a4e ldr r2, [pc, #312] @ (800eb40 ) 800ea08: 4293 cmp r3, r2 800ea0a: d105 bne.n 800ea18 800ea0c: 4b4b ldr r3, [pc, #300] @ (800eb3c ) 800ea0e: 685b ldr r3, [r3, #4] 800ea10: f403 2370 and.w r3, r3, #983040 @ 0xf0000 800ea14: 2b00 cmp r3, #0 800ea16: d115 bne.n 800ea44 { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800ea18: 68fb ldr r3, [r7, #12] 800ea1a: 6a9b ldr r3, [r3, #40] @ 0x28 800ea1c: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 800ea20: 68fb ldr r3, [r7, #12] 800ea22: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800ea24: 68fb ldr r3, [r7, #12] 800ea26: 681b ldr r3, [r3, #0] 800ea28: 685b ldr r3, [r3, #4] 800ea2a: f403 6380 and.w r3, r3, #1024 @ 0x400 800ea2e: 2b00 cmp r3, #0 800ea30: d026 beq.n 800ea80 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800ea32: 68fb ldr r3, [r7, #12] 800ea34: 6a9b ldr r3, [r3, #40] @ 0x28 800ea36: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800ea3a: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800ea3e: 68fb ldr r3, [r7, #12] 800ea40: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800ea42: e01d b.n 800ea80 } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800ea44: 68fb ldr r3, [r7, #12] 800ea46: 6a9b ldr r3, [r3, #40] @ 0x28 800ea48: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800ea4c: 68fb ldr r3, [r7, #12] 800ea4e: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 800ea50: 68fb ldr r3, [r7, #12] 800ea52: 681b ldr r3, [r3, #0] 800ea54: 4a39 ldr r2, [pc, #228] @ (800eb3c ) 800ea56: 4293 cmp r3, r2 800ea58: d004 beq.n 800ea64 800ea5a: 68fb ldr r3, [r7, #12] 800ea5c: 681b ldr r3, [r3, #0] 800ea5e: 4a38 ldr r2, [pc, #224] @ (800eb40 ) 800ea60: 4293 cmp r3, r2 800ea62: d10d bne.n 800ea80 800ea64: 4b35 ldr r3, [pc, #212] @ (800eb3c ) 800ea66: 685b ldr r3, [r3, #4] 800ea68: f403 6380 and.w r3, r3, #1024 @ 0x400 800ea6c: 2b00 cmp r3, #0 800ea6e: d007 beq.n 800ea80 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800ea70: 68fb ldr r3, [r7, #12] 800ea72: 6a9b ldr r3, [r3, #40] @ 0x28 800ea74: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800ea78: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800ea7c: 68fb ldr r3, [r7, #12] 800ea7e: 629a str r2, [r3, #40] @ 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800ea80: 68fb ldr r3, [r7, #12] 800ea82: 6a9b ldr r3, [r3, #40] @ 0x28 800ea84: f403 5380 and.w r3, r3, #4096 @ 0x1000 800ea88: 2b00 cmp r3, #0 800ea8a: d006 beq.n 800ea9a { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 800ea8c: 68fb ldr r3, [r7, #12] 800ea8e: 6adb ldr r3, [r3, #44] @ 0x2c 800ea90: f023 0206 bic.w r2, r3, #6 800ea94: 68fb ldr r3, [r7, #12] 800ea96: 62da str r2, [r3, #44] @ 0x2c 800ea98: e002 b.n 800eaa0 } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 800ea9a: 68fb ldr r3, [r7, #12] 800ea9c: 2200 movs r2, #0 800ea9e: 62da str r2, [r3, #44] @ 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 800eaa0: 68fb ldr r3, [r7, #12] 800eaa2: 2200 movs r2, #0 800eaa4: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 800eaa8: 68fb ldr r3, [r7, #12] 800eaaa: 6a1b ldr r3, [r3, #32] 800eaac: 4a25 ldr r2, [pc, #148] @ (800eb44 ) 800eaae: 629a str r2, [r3, #40] @ 0x28 /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 800eab0: 68fb ldr r3, [r7, #12] 800eab2: 6a1b ldr r3, [r3, #32] 800eab4: 4a24 ldr r2, [pc, #144] @ (800eb48 ) 800eab6: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 800eab8: 68fb ldr r3, [r7, #12] 800eaba: 6a1b ldr r3, [r3, #32] 800eabc: 4a23 ldr r2, [pc, #140] @ (800eb4c ) 800eabe: 631a str r2, [r3, #48] @ 0x30 /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 800eac0: 68fb ldr r3, [r7, #12] 800eac2: 681b ldr r3, [r3, #0] 800eac4: f06f 0202 mvn.w r2, #2 800eac8: 601a str r2, [r3, #0] /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); 800eaca: 68fb ldr r3, [r7, #12] 800eacc: 681b ldr r3, [r3, #0] 800eace: 689a ldr r2, [r3, #8] 800ead0: 68fb ldr r3, [r7, #12] 800ead2: 681b ldr r3, [r3, #0] 800ead4: f442 7280 orr.w r2, r2, #256 @ 0x100 800ead8: 609a str r2, [r3, #8] /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 800eada: 68fb ldr r3, [r7, #12] 800eadc: 6a18 ldr r0, [r3, #32] 800eade: 68fb ldr r3, [r7, #12] 800eae0: 681b ldr r3, [r3, #0] 800eae2: 334c adds r3, #76 @ 0x4c 800eae4: 4619 mov r1, r3 800eae6: 68ba ldr r2, [r7, #8] 800eae8: 687b ldr r3, [r7, #4] 800eaea: f001 fc31 bl 8010350 /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) 800eaee: 68fb ldr r3, [r7, #12] 800eaf0: 681b ldr r3, [r3, #0] 800eaf2: 689b ldr r3, [r3, #8] 800eaf4: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800eaf8: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800eafc: d108 bne.n 800eb10 { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 800eafe: 68fb ldr r3, [r7, #12] 800eb00: 681b ldr r3, [r3, #0] 800eb02: 689a ldr r2, [r3, #8] 800eb04: 68fb ldr r3, [r7, #12] 800eb06: 681b ldr r3, [r3, #0] 800eb08: f442 02a0 orr.w r2, r2, #5242880 @ 0x500000 800eb0c: 609a str r2, [r3, #8] if (tmp_hal_status == HAL_OK) 800eb0e: e00f b.n 800eb30 } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 800eb10: 68fb ldr r3, [r7, #12] 800eb12: 681b ldr r3, [r3, #0] 800eb14: 689a ldr r2, [r3, #8] 800eb16: 68fb ldr r3, [r7, #12] 800eb18: 681b ldr r3, [r3, #0] 800eb1a: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 800eb1e: 609a str r2, [r3, #8] if (tmp_hal_status == HAL_OK) 800eb20: e006 b.n 800eb30 } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 800eb22: 68fb ldr r3, [r7, #12] 800eb24: 2200 movs r2, #0 800eb26: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (tmp_hal_status == HAL_OK) 800eb2a: e001 b.n 800eb30 } } else { tmp_hal_status = HAL_ERROR; 800eb2c: 2301 movs r3, #1 800eb2e: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800eb30: 7dfb ldrb r3, [r7, #23] } 800eb32: 4618 mov r0, r3 800eb34: 3718 adds r7, #24 800eb36: 46bd mov sp, r7 800eb38: bd80 pop {r7, pc} 800eb3a: bf00 nop 800eb3c: 40012400 .word 0x40012400 800eb40: 40012800 .word 0x40012800 800eb44: 0800f02b .word 0x0800f02b 800eb48: 0800f0a7 .word 0x0800f0a7 800eb4c: 0800f0c3 .word 0x0800f0c3 0800eb50 : * @brief Handles ADC interrupt request * @param hadc: ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { 800eb50: b580 push {r7, lr} 800eb52: b084 sub sp, #16 800eb54: af00 add r7, sp, #0 800eb56: 6078 str r0, [r7, #4] uint32_t tmp_sr = hadc->Instance->SR; 800eb58: 687b ldr r3, [r7, #4] 800eb5a: 681b ldr r3, [r3, #0] 800eb5c: 681b ldr r3, [r3, #0] 800eb5e: 60fb str r3, [r7, #12] uint32_t tmp_cr1 = hadc->Instance->CR1; 800eb60: 687b ldr r3, [r7, #4] 800eb62: 681b ldr r3, [r3, #0] 800eb64: 685b ldr r3, [r3, #4] 800eb66: 60bb str r3, [r7, #8] assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); /* ========== Check End of Conversion flag for regular group ========== */ if((tmp_cr1 & ADC_IT_EOC) == ADC_IT_EOC) 800eb68: 68bb ldr r3, [r7, #8] 800eb6a: f003 0320 and.w r3, r3, #32 800eb6e: 2b00 cmp r3, #0 800eb70: d03e beq.n 800ebf0 { if((tmp_sr & ADC_FLAG_EOC) == ADC_FLAG_EOC) 800eb72: 68fb ldr r3, [r7, #12] 800eb74: f003 0302 and.w r3, r3, #2 800eb78: 2b00 cmp r3, #0 800eb7a: d039 beq.n 800ebf0 { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 800eb7c: 687b ldr r3, [r7, #4] 800eb7e: 6a9b ldr r3, [r3, #40] @ 0x28 800eb80: f003 0310 and.w r3, r3, #16 800eb84: 2b00 cmp r3, #0 800eb86: d105 bne.n 800eb94 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800eb88: 687b ldr r3, [r7, #4] 800eb8a: 6a9b ldr r3, [r3, #40] @ 0x28 800eb8c: f443 7200 orr.w r2, r3, #512 @ 0x200 800eb90: 687b ldr r3, [r7, #4] 800eb92: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800eb94: 687b ldr r3, [r7, #4] 800eb96: 681b ldr r3, [r3, #0] 800eb98: 689b ldr r3, [r3, #8] 800eb9a: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800eb9e: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800eba2: d11d bne.n 800ebe0 (hadc->Init.ContinuousConvMode == DISABLE) ) 800eba4: 687b ldr r3, [r7, #4] 800eba6: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800eba8: 2b00 cmp r3, #0 800ebaa: d119 bne.n 800ebe0 { /* Disable ADC end of conversion interrupt on group regular */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); 800ebac: 687b ldr r3, [r7, #4] 800ebae: 681b ldr r3, [r3, #0] 800ebb0: 685a ldr r2, [r3, #4] 800ebb2: 687b ldr r3, [r7, #4] 800ebb4: 681b ldr r3, [r3, #0] 800ebb6: f022 0220 bic.w r2, r2, #32 800ebba: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800ebbc: 687b ldr r3, [r7, #4] 800ebbe: 6a9b ldr r3, [r3, #40] @ 0x28 800ebc0: f423 7280 bic.w r2, r3, #256 @ 0x100 800ebc4: 687b ldr r3, [r7, #4] 800ebc6: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800ebc8: 687b ldr r3, [r7, #4] 800ebca: 6a9b ldr r3, [r3, #40] @ 0x28 800ebcc: f403 5380 and.w r3, r3, #4096 @ 0x1000 800ebd0: 2b00 cmp r3, #0 800ebd2: d105 bne.n 800ebe0 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800ebd4: 687b ldr r3, [r7, #4] 800ebd6: 6a9b ldr r3, [r3, #40] @ 0x28 800ebd8: f043 0201 orr.w r2, r3, #1 800ebdc: 687b ldr r3, [r7, #4] 800ebde: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800ebe0: 6878 ldr r0, [r7, #4] 800ebe2: f7fa fcb3 bl 800954c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 800ebe6: 687b ldr r3, [r7, #4] 800ebe8: 681b ldr r3, [r3, #0] 800ebea: f06f 0212 mvn.w r2, #18 800ebee: 601a str r2, [r3, #0] } } /* ========== Check End of Conversion flag for injected group ========== */ if((tmp_cr1 & ADC_IT_JEOC) == ADC_IT_JEOC) 800ebf0: 68bb ldr r3, [r7, #8] 800ebf2: f003 0380 and.w r3, r3, #128 @ 0x80 800ebf6: 2b00 cmp r3, #0 800ebf8: d04d beq.n 800ec96 { if((tmp_sr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) 800ebfa: 68fb ldr r3, [r7, #12] 800ebfc: f003 0304 and.w r3, r3, #4 800ec00: 2b00 cmp r3, #0 800ec02: d048 beq.n 800ec96 { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 800ec04: 687b ldr r3, [r7, #4] 800ec06: 6a9b ldr r3, [r3, #40] @ 0x28 800ec08: f003 0310 and.w r3, r3, #16 800ec0c: 2b00 cmp r3, #0 800ec0e: d105 bne.n 800ec1c { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 800ec10: 687b ldr r3, [r7, #4] 800ec12: 6a9b ldr r3, [r3, #40] @ 0x28 800ec14: f443 5200 orr.w r2, r3, #8192 @ 0x2000 800ec18: 687b ldr r3, [r7, #4] 800ec1a: 629a str r2, [r3, #40] @ 0x28 /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 800ec1c: 687b ldr r3, [r7, #4] 800ec1e: 681b ldr r3, [r3, #0] 800ec20: 689b ldr r3, [r3, #8] 800ec22: f403 43e0 and.w r3, r3, #28672 @ 0x7000 800ec26: f5b3 4fe0 cmp.w r3, #28672 @ 0x7000 800ec2a: d012 beq.n 800ec52 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 800ec2c: 687b ldr r3, [r7, #4] 800ec2e: 681b ldr r3, [r3, #0] 800ec30: 685b ldr r3, [r3, #4] 800ec32: f403 6380 and.w r3, r3, #1024 @ 0x400 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 800ec36: 2b00 cmp r3, #0 800ec38: d125 bne.n 800ec86 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800ec3a: 687b ldr r3, [r7, #4] 800ec3c: 681b ldr r3, [r3, #0] 800ec3e: 689b ldr r3, [r3, #8] 800ec40: f403 2360 and.w r3, r3, #917504 @ 0xe0000 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 800ec44: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800ec48: d11d bne.n 800ec86 (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) 800ec4a: 687b ldr r3, [r7, #4] 800ec4c: 7b1b ldrb r3, [r3, #12] (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800ec4e: 2b00 cmp r3, #0 800ec50: d119 bne.n 800ec86 { /* Disable ADC end of conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 800ec52: 687b ldr r3, [r7, #4] 800ec54: 681b ldr r3, [r3, #0] 800ec56: 685a ldr r2, [r3, #4] 800ec58: 687b ldr r3, [r7, #4] 800ec5a: 681b ldr r3, [r3, #0] 800ec5c: f022 0280 bic.w r2, r2, #128 @ 0x80 800ec60: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 800ec62: 687b ldr r3, [r7, #4] 800ec64: 6a9b ldr r3, [r3, #40] @ 0x28 800ec66: f423 5280 bic.w r2, r3, #4096 @ 0x1000 800ec6a: 687b ldr r3, [r7, #4] 800ec6c: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 800ec6e: 687b ldr r3, [r7, #4] 800ec70: 6a9b ldr r3, [r3, #40] @ 0x28 800ec72: f403 7380 and.w r3, r3, #256 @ 0x100 800ec76: 2b00 cmp r3, #0 800ec78: d105 bne.n 800ec86 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800ec7a: 687b ldr r3, [r7, #4] 800ec7c: 6a9b ldr r3, [r3, #40] @ 0x28 800ec7e: f043 0201 orr.w r2, r3, #1 800ec82: 687b ldr r3, [r7, #4] 800ec84: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); 800ec86: 6878 ldr r0, [r7, #4] 800ec88: f000 fae4 bl 800f254 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); 800ec8c: 687b ldr r3, [r7, #4] 800ec8e: 681b ldr r3, [r3, #0] 800ec90: f06f 020c mvn.w r2, #12 800ec94: 601a str r2, [r3, #0] } } /* ========== Check Analog watchdog flags ========== */ if((tmp_cr1 & ADC_IT_AWD) == ADC_IT_AWD) 800ec96: 68bb ldr r3, [r7, #8] 800ec98: f003 0340 and.w r3, r3, #64 @ 0x40 800ec9c: 2b00 cmp r3, #0 800ec9e: d012 beq.n 800ecc6 { if((tmp_sr & ADC_FLAG_AWD) == ADC_FLAG_AWD) 800eca0: 68fb ldr r3, [r7, #12] 800eca2: f003 0301 and.w r3, r3, #1 800eca6: 2b00 cmp r3, #0 800eca8: d00d beq.n 800ecc6 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 800ecaa: 687b ldr r3, [r7, #4] 800ecac: 6a9b ldr r3, [r3, #40] @ 0x28 800ecae: f443 3280 orr.w r2, r3, #65536 @ 0x10000 800ecb2: 687b ldr r3, [r7, #4] 800ecb4: 629a str r2, [r3, #40] @ 0x28 /* Level out of window callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); 800ecb6: 6878 ldr r0, [r7, #4] 800ecb8: f000 f812 bl 800ece0 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear the ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); 800ecbc: 687b ldr r3, [r7, #4] 800ecbe: 681b ldr r3, [r3, #0] 800ecc0: f06f 0201 mvn.w r2, #1 800ecc4: 601a str r2, [r3, #0] } } } 800ecc6: bf00 nop 800ecc8: 3710 adds r7, #16 800ecca: 46bd mov sp, r7 800eccc: bd80 pop {r7, pc} 0800ecce : * @brief Conversion DMA half-transfer callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) { 800ecce: b480 push {r7} 800ecd0: b083 sub sp, #12 800ecd2: af00 add r7, sp, #0 800ecd4: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 800ecd6: bf00 nop 800ecd8: 370c adds r7, #12 800ecda: 46bd mov sp, r7 800ecdc: bc80 pop {r7} 800ecde: 4770 bx lr 0800ece0 : * @brief Analog watchdog callback in non blocking mode. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { 800ece0: b480 push {r7} 800ece2: b083 sub sp, #12 800ece4: af00 add r7, sp, #0 800ece6: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } 800ece8: bf00 nop 800ecea: 370c adds r7, #12 800ecec: 46bd mov sp, r7 800ecee: bc80 pop {r7} 800ecf0: 4770 bx lr 0800ecf2 : * (ADC conversion with interruption or transfer by DMA) * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 800ecf2: b480 push {r7} 800ecf4: b083 sub sp, #12 800ecf6: af00 add r7, sp, #0 800ecf8: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 800ecfa: bf00 nop 800ecfc: 370c adds r7, #12 800ecfe: 46bd mov sp, r7 800ed00: bc80 pop {r7} 800ed02: 4770 bx lr 0800ed04 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 800ed04: b480 push {r7} 800ed06: b085 sub sp, #20 800ed08: af00 add r7, sp, #0 800ed0a: 6078 str r0, [r7, #4] 800ed0c: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800ed0e: 2300 movs r3, #0 800ed10: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 800ed12: 2300 movs r3, #0 800ed14: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 800ed16: 687b ldr r3, [r7, #4] 800ed18: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800ed1c: 2b01 cmp r3, #1 800ed1e: d101 bne.n 800ed24 800ed20: 2302 movs r3, #2 800ed22: e0dc b.n 800eede 800ed24: 687b ldr r3, [r7, #4] 800ed26: 2201 movs r2, #1 800ed28: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 800ed2c: 683b ldr r3, [r7, #0] 800ed2e: 685b ldr r3, [r3, #4] 800ed30: 2b06 cmp r3, #6 800ed32: d81c bhi.n 800ed6e { MODIFY_REG(hadc->Instance->SQR3 , 800ed34: 687b ldr r3, [r7, #4] 800ed36: 681b ldr r3, [r3, #0] 800ed38: 6b59 ldr r1, [r3, #52] @ 0x34 800ed3a: 683b ldr r3, [r7, #0] 800ed3c: 685a ldr r2, [r3, #4] 800ed3e: 4613 mov r3, r2 800ed40: 009b lsls r3, r3, #2 800ed42: 4413 add r3, r2 800ed44: 3b05 subs r3, #5 800ed46: 221f movs r2, #31 800ed48: fa02 f303 lsl.w r3, r2, r3 800ed4c: 43db mvns r3, r3 800ed4e: 4019 ands r1, r3 800ed50: 683b ldr r3, [r7, #0] 800ed52: 6818 ldr r0, [r3, #0] 800ed54: 683b ldr r3, [r7, #0] 800ed56: 685a ldr r2, [r3, #4] 800ed58: 4613 mov r3, r2 800ed5a: 009b lsls r3, r3, #2 800ed5c: 4413 add r3, r2 800ed5e: 3b05 subs r3, #5 800ed60: fa00 f203 lsl.w r2, r0, r3 800ed64: 687b ldr r3, [r7, #4] 800ed66: 681b ldr r3, [r3, #0] 800ed68: 430a orrs r2, r1 800ed6a: 635a str r2, [r3, #52] @ 0x34 800ed6c: e03c b.n 800ede8 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 800ed6e: 683b ldr r3, [r7, #0] 800ed70: 685b ldr r3, [r3, #4] 800ed72: 2b0c cmp r3, #12 800ed74: d81c bhi.n 800edb0 { MODIFY_REG(hadc->Instance->SQR2 , 800ed76: 687b ldr r3, [r7, #4] 800ed78: 681b ldr r3, [r3, #0] 800ed7a: 6b19 ldr r1, [r3, #48] @ 0x30 800ed7c: 683b ldr r3, [r7, #0] 800ed7e: 685a ldr r2, [r3, #4] 800ed80: 4613 mov r3, r2 800ed82: 009b lsls r3, r3, #2 800ed84: 4413 add r3, r2 800ed86: 3b23 subs r3, #35 @ 0x23 800ed88: 221f movs r2, #31 800ed8a: fa02 f303 lsl.w r3, r2, r3 800ed8e: 43db mvns r3, r3 800ed90: 4019 ands r1, r3 800ed92: 683b ldr r3, [r7, #0] 800ed94: 6818 ldr r0, [r3, #0] 800ed96: 683b ldr r3, [r7, #0] 800ed98: 685a ldr r2, [r3, #4] 800ed9a: 4613 mov r3, r2 800ed9c: 009b lsls r3, r3, #2 800ed9e: 4413 add r3, r2 800eda0: 3b23 subs r3, #35 @ 0x23 800eda2: fa00 f203 lsl.w r2, r0, r3 800eda6: 687b ldr r3, [r7, #4] 800eda8: 681b ldr r3, [r3, #0] 800edaa: 430a orrs r2, r1 800edac: 631a str r2, [r3, #48] @ 0x30 800edae: e01b b.n 800ede8 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 800edb0: 687b ldr r3, [r7, #4] 800edb2: 681b ldr r3, [r3, #0] 800edb4: 6ad9 ldr r1, [r3, #44] @ 0x2c 800edb6: 683b ldr r3, [r7, #0] 800edb8: 685a ldr r2, [r3, #4] 800edba: 4613 mov r3, r2 800edbc: 009b lsls r3, r3, #2 800edbe: 4413 add r3, r2 800edc0: 3b41 subs r3, #65 @ 0x41 800edc2: 221f movs r2, #31 800edc4: fa02 f303 lsl.w r3, r2, r3 800edc8: 43db mvns r3, r3 800edca: 4019 ands r1, r3 800edcc: 683b ldr r3, [r7, #0] 800edce: 6818 ldr r0, [r3, #0] 800edd0: 683b ldr r3, [r7, #0] 800edd2: 685a ldr r2, [r3, #4] 800edd4: 4613 mov r3, r2 800edd6: 009b lsls r3, r3, #2 800edd8: 4413 add r3, r2 800edda: 3b41 subs r3, #65 @ 0x41 800eddc: fa00 f203 lsl.w r2, r0, r3 800ede0: 687b ldr r3, [r7, #4] 800ede2: 681b ldr r3, [r3, #0] 800ede4: 430a orrs r2, r1 800ede6: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 800ede8: 683b ldr r3, [r7, #0] 800edea: 681b ldr r3, [r3, #0] 800edec: 2b09 cmp r3, #9 800edee: d91c bls.n 800ee2a { MODIFY_REG(hadc->Instance->SMPR1 , 800edf0: 687b ldr r3, [r7, #4] 800edf2: 681b ldr r3, [r3, #0] 800edf4: 68d9 ldr r1, [r3, #12] 800edf6: 683b ldr r3, [r7, #0] 800edf8: 681a ldr r2, [r3, #0] 800edfa: 4613 mov r3, r2 800edfc: 005b lsls r3, r3, #1 800edfe: 4413 add r3, r2 800ee00: 3b1e subs r3, #30 800ee02: 2207 movs r2, #7 800ee04: fa02 f303 lsl.w r3, r2, r3 800ee08: 43db mvns r3, r3 800ee0a: 4019 ands r1, r3 800ee0c: 683b ldr r3, [r7, #0] 800ee0e: 6898 ldr r0, [r3, #8] 800ee10: 683b ldr r3, [r7, #0] 800ee12: 681a ldr r2, [r3, #0] 800ee14: 4613 mov r3, r2 800ee16: 005b lsls r3, r3, #1 800ee18: 4413 add r3, r2 800ee1a: 3b1e subs r3, #30 800ee1c: fa00 f203 lsl.w r2, r0, r3 800ee20: 687b ldr r3, [r7, #4] 800ee22: 681b ldr r3, [r3, #0] 800ee24: 430a orrs r2, r1 800ee26: 60da str r2, [r3, #12] 800ee28: e019 b.n 800ee5e ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 800ee2a: 687b ldr r3, [r7, #4] 800ee2c: 681b ldr r3, [r3, #0] 800ee2e: 6919 ldr r1, [r3, #16] 800ee30: 683b ldr r3, [r7, #0] 800ee32: 681a ldr r2, [r3, #0] 800ee34: 4613 mov r3, r2 800ee36: 005b lsls r3, r3, #1 800ee38: 4413 add r3, r2 800ee3a: 2207 movs r2, #7 800ee3c: fa02 f303 lsl.w r3, r2, r3 800ee40: 43db mvns r3, r3 800ee42: 4019 ands r1, r3 800ee44: 683b ldr r3, [r7, #0] 800ee46: 6898 ldr r0, [r3, #8] 800ee48: 683b ldr r3, [r7, #0] 800ee4a: 681a ldr r2, [r3, #0] 800ee4c: 4613 mov r3, r2 800ee4e: 005b lsls r3, r3, #1 800ee50: 4413 add r3, r2 800ee52: fa00 f203 lsl.w r2, r0, r3 800ee56: 687b ldr r3, [r7, #4] 800ee58: 681b ldr r3, [r3, #0] 800ee5a: 430a orrs r2, r1 800ee5c: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800ee5e: 683b ldr r3, [r7, #0] 800ee60: 681b ldr r3, [r3, #0] 800ee62: 2b10 cmp r3, #16 800ee64: d003 beq.n 800ee6e (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 800ee66: 683b ldr r3, [r7, #0] 800ee68: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800ee6a: 2b11 cmp r3, #17 800ee6c: d132 bne.n 800eed4 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 800ee6e: 687b ldr r3, [r7, #4] 800ee70: 681b ldr r3, [r3, #0] 800ee72: 4a1d ldr r2, [pc, #116] @ (800eee8 ) 800ee74: 4293 cmp r3, r2 800ee76: d125 bne.n 800eec4 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 800ee78: 687b ldr r3, [r7, #4] 800ee7a: 681b ldr r3, [r3, #0] 800ee7c: 689b ldr r3, [r3, #8] 800ee7e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800ee82: 2b00 cmp r3, #0 800ee84: d126 bne.n 800eed4 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 800ee86: 687b ldr r3, [r7, #4] 800ee88: 681b ldr r3, [r3, #0] 800ee8a: 689a ldr r2, [r3, #8] 800ee8c: 687b ldr r3, [r7, #4] 800ee8e: 681b ldr r3, [r3, #0] 800ee90: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 800ee94: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 800ee96: 683b ldr r3, [r7, #0] 800ee98: 681b ldr r3, [r3, #0] 800ee9a: 2b10 cmp r3, #16 800ee9c: d11a bne.n 800eed4 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 800ee9e: 4b13 ldr r3, [pc, #76] @ (800eeec ) 800eea0: 681b ldr r3, [r3, #0] 800eea2: 4a13 ldr r2, [pc, #76] @ (800eef0 ) 800eea4: fba2 2303 umull r2, r3, r2, r3 800eea8: 0c9a lsrs r2, r3, #18 800eeaa: 4613 mov r3, r2 800eeac: 009b lsls r3, r3, #2 800eeae: 4413 add r3, r2 800eeb0: 005b lsls r3, r3, #1 800eeb2: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800eeb4: e002 b.n 800eebc { wait_loop_index--; 800eeb6: 68bb ldr r3, [r7, #8] 800eeb8: 3b01 subs r3, #1 800eeba: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800eebc: 68bb ldr r3, [r7, #8] 800eebe: 2b00 cmp r3, #0 800eec0: d1f9 bne.n 800eeb6 800eec2: e007 b.n 800eed4 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800eec4: 687b ldr r3, [r7, #4] 800eec6: 6a9b ldr r3, [r3, #40] @ 0x28 800eec8: f043 0220 orr.w r2, r3, #32 800eecc: 687b ldr r3, [r7, #4] 800eece: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800eed0: 2301 movs r3, #1 800eed2: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 800eed4: 687b ldr r3, [r7, #4] 800eed6: 2200 movs r2, #0 800eed8: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800eedc: 7bfb ldrb r3, [r7, #15] } 800eede: 4618 mov r0, r3 800eee0: 3714 adds r7, #20 800eee2: 46bd mov sp, r7 800eee4: bc80 pop {r7} 800eee6: 4770 bx lr 800eee8: 40012400 .word 0x40012400 800eeec: 20000084 .word 0x20000084 800eef0: 431bde83 .word 0x431bde83 0800eef4 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 800eef4: b580 push {r7, lr} 800eef6: b084 sub sp, #16 800eef8: af00 add r7, sp, #0 800eefa: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800eefc: 2300 movs r3, #0 800eefe: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 800ef00: 2300 movs r3, #0 800ef02: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 800ef04: 687b ldr r3, [r7, #4] 800ef06: 681b ldr r3, [r3, #0] 800ef08: 689b ldr r3, [r3, #8] 800ef0a: f003 0301 and.w r3, r3, #1 800ef0e: 2b01 cmp r3, #1 800ef10: d040 beq.n 800ef94 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 800ef12: 687b ldr r3, [r7, #4] 800ef14: 681b ldr r3, [r3, #0] 800ef16: 689a ldr r2, [r3, #8] 800ef18: 687b ldr r3, [r7, #4] 800ef1a: 681b ldr r3, [r3, #0] 800ef1c: f042 0201 orr.w r2, r2, #1 800ef20: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 800ef22: 4b1f ldr r3, [pc, #124] @ (800efa0 ) 800ef24: 681b ldr r3, [r3, #0] 800ef26: 4a1f ldr r2, [pc, #124] @ (800efa4 ) 800ef28: fba2 2303 umull r2, r3, r2, r3 800ef2c: 0c9b lsrs r3, r3, #18 800ef2e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800ef30: e002 b.n 800ef38 { wait_loop_index--; 800ef32: 68bb ldr r3, [r7, #8] 800ef34: 3b01 subs r3, #1 800ef36: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800ef38: 68bb ldr r3, [r7, #8] 800ef3a: 2b00 cmp r3, #0 800ef3c: d1f9 bne.n 800ef32 } /* Get tick count */ tickstart = HAL_GetTick(); 800ef3e: f7ff fc23 bl 800e788 800ef42: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 800ef44: e01f b.n 800ef86 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 800ef46: f7ff fc1f bl 800e788 800ef4a: 4602 mov r2, r0 800ef4c: 68fb ldr r3, [r7, #12] 800ef4e: 1ad3 subs r3, r2, r3 800ef50: 2b02 cmp r3, #2 800ef52: d918 bls.n 800ef86 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 800ef54: 687b ldr r3, [r7, #4] 800ef56: 681b ldr r3, [r3, #0] 800ef58: 689b ldr r3, [r3, #8] 800ef5a: f003 0301 and.w r3, r3, #1 800ef5e: 2b01 cmp r3, #1 800ef60: d011 beq.n 800ef86 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800ef62: 687b ldr r3, [r7, #4] 800ef64: 6a9b ldr r3, [r3, #40] @ 0x28 800ef66: f043 0210 orr.w r2, r3, #16 800ef6a: 687b ldr r3, [r7, #4] 800ef6c: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800ef6e: 687b ldr r3, [r7, #4] 800ef70: 6adb ldr r3, [r3, #44] @ 0x2c 800ef72: f043 0201 orr.w r2, r3, #1 800ef76: 687b ldr r3, [r7, #4] 800ef78: 62da str r2, [r3, #44] @ 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 800ef7a: 687b ldr r3, [r7, #4] 800ef7c: 2200 movs r2, #0 800ef7e: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ef82: 2301 movs r3, #1 800ef84: e007 b.n 800ef96 while(ADC_IS_ENABLE(hadc) == RESET) 800ef86: 687b ldr r3, [r7, #4] 800ef88: 681b ldr r3, [r3, #0] 800ef8a: 689b ldr r3, [r3, #8] 800ef8c: f003 0301 and.w r3, r3, #1 800ef90: 2b01 cmp r3, #1 800ef92: d1d8 bne.n 800ef46 } } } /* Return HAL status */ return HAL_OK; 800ef94: 2300 movs r3, #0 } 800ef96: 4618 mov r0, r3 800ef98: 3710 adds r7, #16 800ef9a: 46bd mov sp, r7 800ef9c: bd80 pop {r7, pc} 800ef9e: bf00 nop 800efa0: 20000084 .word 0x20000084 800efa4: 431bde83 .word 0x431bde83 0800efa8 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 800efa8: b580 push {r7, lr} 800efaa: b084 sub sp, #16 800efac: af00 add r7, sp, #0 800efae: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800efb0: 2300 movs r3, #0 800efb2: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 800efb4: 687b ldr r3, [r7, #4] 800efb6: 681b ldr r3, [r3, #0] 800efb8: 689b ldr r3, [r3, #8] 800efba: f003 0301 and.w r3, r3, #1 800efbe: 2b01 cmp r3, #1 800efc0: d12e bne.n 800f020 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 800efc2: 687b ldr r3, [r7, #4] 800efc4: 681b ldr r3, [r3, #0] 800efc6: 689a ldr r2, [r3, #8] 800efc8: 687b ldr r3, [r7, #4] 800efca: 681b ldr r3, [r3, #0] 800efcc: f022 0201 bic.w r2, r2, #1 800efd0: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 800efd2: f7ff fbd9 bl 800e788 800efd6: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 800efd8: e01b b.n 800f012 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800efda: f7ff fbd5 bl 800e788 800efde: 4602 mov r2, r0 800efe0: 68fb ldr r3, [r7, #12] 800efe2: 1ad3 subs r3, r2, r3 800efe4: 2b02 cmp r3, #2 800efe6: d914 bls.n 800f012 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 800efe8: 687b ldr r3, [r7, #4] 800efea: 681b ldr r3, [r3, #0] 800efec: 689b ldr r3, [r3, #8] 800efee: f003 0301 and.w r3, r3, #1 800eff2: 2b01 cmp r3, #1 800eff4: d10d bne.n 800f012 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800eff6: 687b ldr r3, [r7, #4] 800eff8: 6a9b ldr r3, [r3, #40] @ 0x28 800effa: f043 0210 orr.w r2, r3, #16 800effe: 687b ldr r3, [r7, #4] 800f000: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800f002: 687b ldr r3, [r7, #4] 800f004: 6adb ldr r3, [r3, #44] @ 0x2c 800f006: f043 0201 orr.w r2, r3, #1 800f00a: 687b ldr r3, [r7, #4] 800f00c: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 800f00e: 2301 movs r3, #1 800f010: e007 b.n 800f022 while(ADC_IS_ENABLE(hadc) != RESET) 800f012: 687b ldr r3, [r7, #4] 800f014: 681b ldr r3, [r3, #0] 800f016: 689b ldr r3, [r3, #8] 800f018: f003 0301 and.w r3, r3, #1 800f01c: 2b01 cmp r3, #1 800f01e: d0dc beq.n 800efda } } } /* Return HAL status */ return HAL_OK; 800f020: 2300 movs r3, #0 } 800f022: 4618 mov r0, r3 800f024: 3710 adds r7, #16 800f026: 46bd mov sp, r7 800f028: bd80 pop {r7, pc} 0800f02a : * @brief DMA transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 800f02a: b580 push {r7, lr} 800f02c: b084 sub sp, #16 800f02e: af00 add r7, sp, #0 800f030: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800f032: 687b ldr r3, [r7, #4] 800f034: 6a5b ldr r3, [r3, #36] @ 0x24 800f036: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) 800f038: 68fb ldr r3, [r7, #12] 800f03a: 6a9b ldr r3, [r3, #40] @ 0x28 800f03c: f003 0350 and.w r3, r3, #80 @ 0x50 800f040: 2b00 cmp r3, #0 800f042: d127 bne.n 800f094 { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800f044: 68fb ldr r3, [r7, #12] 800f046: 6a9b ldr r3, [r3, #40] @ 0x28 800f048: f443 7200 orr.w r2, r3, #512 @ 0x200 800f04c: 68fb ldr r3, [r7, #12] 800f04e: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800f050: 68fb ldr r3, [r7, #12] 800f052: 681b ldr r3, [r3, #0] 800f054: 689b ldr r3, [r3, #8] 800f056: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800f05a: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800f05e: d115 bne.n 800f08c (hadc->Init.ContinuousConvMode == DISABLE) ) 800f060: 68fb ldr r3, [r7, #12] 800f062: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800f064: 2b00 cmp r3, #0 800f066: d111 bne.n 800f08c { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800f068: 68fb ldr r3, [r7, #12] 800f06a: 6a9b ldr r3, [r3, #40] @ 0x28 800f06c: f423 7280 bic.w r2, r3, #256 @ 0x100 800f070: 68fb ldr r3, [r7, #12] 800f072: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800f074: 68fb ldr r3, [r7, #12] 800f076: 6a9b ldr r3, [r3, #40] @ 0x28 800f078: f403 5380 and.w r3, r3, #4096 @ 0x1000 800f07c: 2b00 cmp r3, #0 800f07e: d105 bne.n 800f08c { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800f080: 68fb ldr r3, [r7, #12] 800f082: 6a9b ldr r3, [r3, #40] @ 0x28 800f084: f043 0201 orr.w r2, r3, #1 800f088: 68fb ldr r3, [r7, #12] 800f08a: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800f08c: 68f8 ldr r0, [r7, #12] 800f08e: f7fa fa5d bl 800954c else { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } 800f092: e004 b.n 800f09e hadc->DMA_Handle->XferErrorCallback(hdma); 800f094: 68fb ldr r3, [r7, #12] 800f096: 6a1b ldr r3, [r3, #32] 800f098: 6b1b ldr r3, [r3, #48] @ 0x30 800f09a: 6878 ldr r0, [r7, #4] 800f09c: 4798 blx r3 } 800f09e: bf00 nop 800f0a0: 3710 adds r7, #16 800f0a2: 46bd mov sp, r7 800f0a4: bd80 pop {r7, pc} 0800f0a6 : * @brief DMA half transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 800f0a6: b580 push {r7, lr} 800f0a8: b084 sub sp, #16 800f0aa: af00 add r7, sp, #0 800f0ac: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800f0ae: 687b ldr r3, [r7, #4] 800f0b0: 6a5b ldr r3, [r3, #36] @ 0x24 800f0b2: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 800f0b4: 68f8 ldr r0, [r7, #12] 800f0b6: f7ff fe0a bl 800ecce #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800f0ba: bf00 nop 800f0bc: 3710 adds r7, #16 800f0be: 46bd mov sp, r7 800f0c0: bd80 pop {r7, pc} 0800f0c2 : * @brief DMA error callback * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 800f0c2: b580 push {r7, lr} 800f0c4: b084 sub sp, #16 800f0c6: af00 add r7, sp, #0 800f0c8: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800f0ca: 687b ldr r3, [r7, #4] 800f0cc: 6a5b ldr r3, [r3, #36] @ 0x24 800f0ce: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 800f0d0: 68fb ldr r3, [r7, #12] 800f0d2: 6a9b ldr r3, [r3, #40] @ 0x28 800f0d4: f043 0240 orr.w r2, r3, #64 @ 0x40 800f0d8: 68fb ldr r3, [r7, #12] 800f0da: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 800f0dc: 68fb ldr r3, [r7, #12] 800f0de: 6adb ldr r3, [r3, #44] @ 0x2c 800f0e0: f043 0204 orr.w r2, r3, #4 800f0e4: 68fb ldr r3, [r7, #12] 800f0e6: 62da str r2, [r3, #44] @ 0x2c /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 800f0e8: 68f8 ldr r0, [r7, #12] 800f0ea: f7ff fe02 bl 800ecf2 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800f0ee: bf00 nop 800f0f0: 3710 adds r7, #16 800f0f2: 46bd mov sp, r7 800f0f4: bd80 pop {r7, pc} ... 0800f0f8 : * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { 800f0f8: b590 push {r4, r7, lr} 800f0fa: b087 sub sp, #28 800f0fc: af00 add r7, sp, #0 800f0fe: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800f100: 2300 movs r3, #0 800f102: 75fb strb r3, [r7, #23] uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; 800f104: 2300 movs r3, #0 800f106: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800f108: 687b ldr r3, [r7, #4] 800f10a: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800f10e: 2b01 cmp r3, #1 800f110: d101 bne.n 800f116 800f112: 2302 movs r3, #2 800f114: e097 b.n 800f246 800f116: 687b ldr r3, [r7, #4] 800f118: 2201 movs r2, #1 800f11a: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* 1. Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800f11e: 6878 ldr r0, [r7, #4] 800f120: f7ff ff42 bl 800efa8 800f124: 4603 mov r3, r0 800f126: 75fb strb r3, [r7, #23] /* 2. Calibration prerequisite delay before starting the calibration. */ /* - ADC must be enabled for at least two ADC clock cycles */ tmp_hal_status = ADC_Enable(hadc); 800f128: 6878 ldr r0, [r7, #4] 800f12a: f7ff fee3 bl 800eef4 800f12e: 4603 mov r3, r0 800f130: 75fb strb r3, [r7, #23] /* Check if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800f132: 7dfb ldrb r3, [r7, #23] 800f134: 2b00 cmp r3, #0 800f136: f040 8081 bne.w 800f23c { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800f13a: 687b ldr r3, [r7, #4] 800f13c: 6a9b ldr r3, [r3, #40] @ 0x28 800f13e: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800f142: f023 0302 bic.w r3, r3, #2 800f146: f043 0202 orr.w r2, r3, #2 800f14a: 687b ldr r3, [r7, #4] 800f14c: 629a str r2, [r3, #40] @ 0x28 /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 800f14e: 4b40 ldr r3, [pc, #256] @ (800f250 ) 800f150: 681c ldr r4, [r3, #0] 800f152: 2002 movs r0, #2 800f154: f002 fde2 bl 8011d1c 800f158: 4603 mov r3, r0 800f15a: fbb4 f3f3 udiv r3, r4, r3 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 800f15e: 005b lsls r3, r3, #1 wait_loop_index = ((SystemCoreClock 800f160: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800f162: e002 b.n 800f16a { wait_loop_index--; 800f164: 68fb ldr r3, [r7, #12] 800f166: 3b01 subs r3, #1 800f168: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800f16a: 68fb ldr r3, [r7, #12] 800f16c: 2b00 cmp r3, #0 800f16e: d1f9 bne.n 800f164 } /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 800f170: 687b ldr r3, [r7, #4] 800f172: 681b ldr r3, [r3, #0] 800f174: 689a ldr r2, [r3, #8] 800f176: 687b ldr r3, [r7, #4] 800f178: 681b ldr r3, [r3, #0] 800f17a: f042 0208 orr.w r2, r2, #8 800f17e: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800f180: f7ff fb02 bl 800e788 800f184: 6138 str r0, [r7, #16] /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800f186: e01b b.n 800f1c0 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800f188: f7ff fafe bl 800e788 800f18c: 4602 mov r2, r0 800f18e: 693b ldr r3, [r7, #16] 800f190: 1ad3 subs r3, r2, r3 800f192: 2b0a cmp r3, #10 800f194: d914 bls.n 800f1c0 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800f196: 687b ldr r3, [r7, #4] 800f198: 681b ldr r3, [r3, #0] 800f19a: 689b ldr r3, [r3, #8] 800f19c: f003 0308 and.w r3, r3, #8 800f1a0: 2b00 cmp r3, #0 800f1a2: d00d beq.n 800f1c0 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800f1a4: 687b ldr r3, [r7, #4] 800f1a6: 6a9b ldr r3, [r3, #40] @ 0x28 800f1a8: f023 0312 bic.w r3, r3, #18 800f1ac: f043 0210 orr.w r2, r3, #16 800f1b0: 687b ldr r3, [r7, #4] 800f1b2: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800f1b4: 687b ldr r3, [r7, #4] 800f1b6: 2200 movs r2, #0 800f1b8: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f1bc: 2301 movs r3, #1 800f1be: e042 b.n 800f246 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800f1c0: 687b ldr r3, [r7, #4] 800f1c2: 681b ldr r3, [r3, #0] 800f1c4: 689b ldr r3, [r3, #8] 800f1c6: f003 0308 and.w r3, r3, #8 800f1ca: 2b00 cmp r3, #0 800f1cc: d1dc bne.n 800f188 } } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 800f1ce: 687b ldr r3, [r7, #4] 800f1d0: 681b ldr r3, [r3, #0] 800f1d2: 689a ldr r2, [r3, #8] 800f1d4: 687b ldr r3, [r7, #4] 800f1d6: 681b ldr r3, [r3, #0] 800f1d8: f042 0204 orr.w r2, r2, #4 800f1dc: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800f1de: f7ff fad3 bl 800e788 800f1e2: 6138 str r0, [r7, #16] /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800f1e4: e01b b.n 800f21e { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800f1e6: f7ff facf bl 800e788 800f1ea: 4602 mov r2, r0 800f1ec: 693b ldr r3, [r7, #16] 800f1ee: 1ad3 subs r3, r2, r3 800f1f0: 2b0a cmp r3, #10 800f1f2: d914 bls.n 800f21e { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800f1f4: 687b ldr r3, [r7, #4] 800f1f6: 681b ldr r3, [r3, #0] 800f1f8: 689b ldr r3, [r3, #8] 800f1fa: f003 0304 and.w r3, r3, #4 800f1fe: 2b00 cmp r3, #0 800f200: d00d beq.n 800f21e { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800f202: 687b ldr r3, [r7, #4] 800f204: 6a9b ldr r3, [r3, #40] @ 0x28 800f206: f023 0312 bic.w r3, r3, #18 800f20a: f043 0210 orr.w r2, r3, #16 800f20e: 687b ldr r3, [r7, #4] 800f210: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800f212: 687b ldr r3, [r7, #4] 800f214: 2200 movs r2, #0 800f216: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f21a: 2301 movs r3, #1 800f21c: e013 b.n 800f246 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800f21e: 687b ldr r3, [r7, #4] 800f220: 681b ldr r3, [r3, #0] 800f222: 689b ldr r3, [r3, #8] 800f224: f003 0304 and.w r3, r3, #4 800f228: 2b00 cmp r3, #0 800f22a: d1dc bne.n 800f1e6 } } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800f22c: 687b ldr r3, [r7, #4] 800f22e: 6a9b ldr r3, [r3, #40] @ 0x28 800f230: f023 0303 bic.w r3, r3, #3 800f234: f043 0201 orr.w r2, r3, #1 800f238: 687b ldr r3, [r7, #4] 800f23a: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 800f23c: 687b ldr r3, [r7, #4] 800f23e: 2200 movs r2, #0 800f240: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800f244: 7dfb ldrb r3, [r7, #23] } 800f246: 4618 mov r0, r3 800f248: 371c adds r7, #28 800f24a: 46bd mov sp, r7 800f24c: bd90 pop {r4, r7, pc} 800f24e: bf00 nop 800f250: 20000084 .word 0x20000084 0800f254 : * @brief Injected conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { 800f254: b480 push {r7} 800f256: b083 sub sp, #12 800f258: af00 add r7, sp, #0 800f25a: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } 800f25c: bf00 nop 800f25e: 370c adds r7, #12 800f260: 46bd mov sp, r7 800f262: bc80 pop {r7} 800f264: 4770 bx lr 0800f266 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { 800f266: b580 push {r7, lr} 800f268: b084 sub sp, #16 800f26a: af00 add r7, sp, #0 800f26c: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) 800f26e: 687b ldr r3, [r7, #4] 800f270: 2b00 cmp r3, #0 800f272: d101 bne.n 800f278 { return HAL_ERROR; 800f274: 2301 movs r3, #1 800f276: e0ed b.n 800f454 /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) 800f278: 687b ldr r3, [r7, #4] 800f27a: f893 3020 ldrb.w r3, [r3, #32] 800f27e: b2db uxtb r3, r3 800f280: 2b00 cmp r3, #0 800f282: d102 bne.n 800f28a { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); 800f284: 6878 ldr r0, [r7, #4] 800f286: f7fa fcf7 bl 8009c78 } #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800f28a: 687b ldr r3, [r7, #4] 800f28c: 681b ldr r3, [r3, #0] 800f28e: 681a ldr r2, [r3, #0] 800f290: 687b ldr r3, [r7, #4] 800f292: 681b ldr r3, [r3, #0] 800f294: f042 0201 orr.w r2, r2, #1 800f298: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800f29a: f7ff fa75 bl 800e788 800f29e: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800f2a0: e012 b.n 800f2c8 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800f2a2: f7ff fa71 bl 800e788 800f2a6: 4602 mov r2, r0 800f2a8: 68fb ldr r3, [r7, #12] 800f2aa: 1ad3 subs r3, r2, r3 800f2ac: 2b0a cmp r3, #10 800f2ae: d90b bls.n 800f2c8 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800f2b0: 687b ldr r3, [r7, #4] 800f2b2: 6a5b ldr r3, [r3, #36] @ 0x24 800f2b4: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800f2b8: 687b ldr r3, [r7, #4] 800f2ba: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800f2bc: 687b ldr r3, [r7, #4] 800f2be: 2205 movs r2, #5 800f2c0: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800f2c4: 2301 movs r3, #1 800f2c6: e0c5 b.n 800f454 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800f2c8: 687b ldr r3, [r7, #4] 800f2ca: 681b ldr r3, [r3, #0] 800f2cc: 685b ldr r3, [r3, #4] 800f2ce: f003 0301 and.w r3, r3, #1 800f2d2: 2b00 cmp r3, #0 800f2d4: d0e5 beq.n 800f2a2 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800f2d6: 687b ldr r3, [r7, #4] 800f2d8: 681b ldr r3, [r3, #0] 800f2da: 681a ldr r2, [r3, #0] 800f2dc: 687b ldr r3, [r7, #4] 800f2de: 681b ldr r3, [r3, #0] 800f2e0: f022 0202 bic.w r2, r2, #2 800f2e4: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800f2e6: f7ff fa4f bl 800e788 800f2ea: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800f2ec: e012 b.n 800f314 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800f2ee: f7ff fa4b bl 800e788 800f2f2: 4602 mov r2, r0 800f2f4: 68fb ldr r3, [r7, #12] 800f2f6: 1ad3 subs r3, r2, r3 800f2f8: 2b0a cmp r3, #10 800f2fa: d90b bls.n 800f314 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800f2fc: 687b ldr r3, [r7, #4] 800f2fe: 6a5b ldr r3, [r3, #36] @ 0x24 800f300: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800f304: 687b ldr r3, [r7, #4] 800f306: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800f308: 687b ldr r3, [r7, #4] 800f30a: 2205 movs r2, #5 800f30c: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800f310: 2301 movs r3, #1 800f312: e09f b.n 800f454 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800f314: 687b ldr r3, [r7, #4] 800f316: 681b ldr r3, [r3, #0] 800f318: 685b ldr r3, [r3, #4] 800f31a: f003 0302 and.w r3, r3, #2 800f31e: 2b00 cmp r3, #0 800f320: d1e5 bne.n 800f2ee } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) 800f322: 687b ldr r3, [r7, #4] 800f324: 7e1b ldrb r3, [r3, #24] 800f326: 2b01 cmp r3, #1 800f328: d108 bne.n 800f33c { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800f32a: 687b ldr r3, [r7, #4] 800f32c: 681b ldr r3, [r3, #0] 800f32e: 681a ldr r2, [r3, #0] 800f330: 687b ldr r3, [r7, #4] 800f332: 681b ldr r3, [r3, #0] 800f334: f042 0280 orr.w r2, r2, #128 @ 0x80 800f338: 601a str r2, [r3, #0] 800f33a: e007 b.n 800f34c } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800f33c: 687b ldr r3, [r7, #4] 800f33e: 681b ldr r3, [r3, #0] 800f340: 681a ldr r2, [r3, #0] 800f342: 687b ldr r3, [r7, #4] 800f344: 681b ldr r3, [r3, #0] 800f346: f022 0280 bic.w r2, r2, #128 @ 0x80 800f34a: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) 800f34c: 687b ldr r3, [r7, #4] 800f34e: 7e5b ldrb r3, [r3, #25] 800f350: 2b01 cmp r3, #1 800f352: d108 bne.n 800f366 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800f354: 687b ldr r3, [r7, #4] 800f356: 681b ldr r3, [r3, #0] 800f358: 681a ldr r2, [r3, #0] 800f35a: 687b ldr r3, [r7, #4] 800f35c: 681b ldr r3, [r3, #0] 800f35e: f042 0240 orr.w r2, r2, #64 @ 0x40 800f362: 601a str r2, [r3, #0] 800f364: e007 b.n 800f376 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800f366: 687b ldr r3, [r7, #4] 800f368: 681b ldr r3, [r3, #0] 800f36a: 681a ldr r2, [r3, #0] 800f36c: 687b ldr r3, [r7, #4] 800f36e: 681b ldr r3, [r3, #0] 800f370: f022 0240 bic.w r2, r2, #64 @ 0x40 800f374: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) 800f376: 687b ldr r3, [r7, #4] 800f378: 7e9b ldrb r3, [r3, #26] 800f37a: 2b01 cmp r3, #1 800f37c: d108 bne.n 800f390 { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800f37e: 687b ldr r3, [r7, #4] 800f380: 681b ldr r3, [r3, #0] 800f382: 681a ldr r2, [r3, #0] 800f384: 687b ldr r3, [r7, #4] 800f386: 681b ldr r3, [r3, #0] 800f388: f042 0220 orr.w r2, r2, #32 800f38c: 601a str r2, [r3, #0] 800f38e: e007 b.n 800f3a0 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800f390: 687b ldr r3, [r7, #4] 800f392: 681b ldr r3, [r3, #0] 800f394: 681a ldr r2, [r3, #0] 800f396: 687b ldr r3, [r7, #4] 800f398: 681b ldr r3, [r3, #0] 800f39a: f022 0220 bic.w r2, r2, #32 800f39e: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) 800f3a0: 687b ldr r3, [r7, #4] 800f3a2: 7edb ldrb r3, [r3, #27] 800f3a4: 2b01 cmp r3, #1 800f3a6: d108 bne.n 800f3ba { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800f3a8: 687b ldr r3, [r7, #4] 800f3aa: 681b ldr r3, [r3, #0] 800f3ac: 681a ldr r2, [r3, #0] 800f3ae: 687b ldr r3, [r7, #4] 800f3b0: 681b ldr r3, [r3, #0] 800f3b2: f022 0210 bic.w r2, r2, #16 800f3b6: 601a str r2, [r3, #0] 800f3b8: e007 b.n 800f3ca } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800f3ba: 687b ldr r3, [r7, #4] 800f3bc: 681b ldr r3, [r3, #0] 800f3be: 681a ldr r2, [r3, #0] 800f3c0: 687b ldr r3, [r7, #4] 800f3c2: 681b ldr r3, [r3, #0] 800f3c4: f042 0210 orr.w r2, r2, #16 800f3c8: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) 800f3ca: 687b ldr r3, [r7, #4] 800f3cc: 7f1b ldrb r3, [r3, #28] 800f3ce: 2b01 cmp r3, #1 800f3d0: d108 bne.n 800f3e4 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800f3d2: 687b ldr r3, [r7, #4] 800f3d4: 681b ldr r3, [r3, #0] 800f3d6: 681a ldr r2, [r3, #0] 800f3d8: 687b ldr r3, [r7, #4] 800f3da: 681b ldr r3, [r3, #0] 800f3dc: f042 0208 orr.w r2, r2, #8 800f3e0: 601a str r2, [r3, #0] 800f3e2: e007 b.n 800f3f4 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800f3e4: 687b ldr r3, [r7, #4] 800f3e6: 681b ldr r3, [r3, #0] 800f3e8: 681a ldr r2, [r3, #0] 800f3ea: 687b ldr r3, [r7, #4] 800f3ec: 681b ldr r3, [r3, #0] 800f3ee: f022 0208 bic.w r2, r2, #8 800f3f2: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) 800f3f4: 687b ldr r3, [r7, #4] 800f3f6: 7f5b ldrb r3, [r3, #29] 800f3f8: 2b01 cmp r3, #1 800f3fa: d108 bne.n 800f40e { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800f3fc: 687b ldr r3, [r7, #4] 800f3fe: 681b ldr r3, [r3, #0] 800f400: 681a ldr r2, [r3, #0] 800f402: 687b ldr r3, [r7, #4] 800f404: 681b ldr r3, [r3, #0] 800f406: f042 0204 orr.w r2, r2, #4 800f40a: 601a str r2, [r3, #0] 800f40c: e007 b.n 800f41e } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800f40e: 687b ldr r3, [r7, #4] 800f410: 681b ldr r3, [r3, #0] 800f412: 681a ldr r2, [r3, #0] 800f414: 687b ldr r3, [r7, #4] 800f416: 681b ldr r3, [r3, #0] 800f418: f022 0204 bic.w r2, r2, #4 800f41c: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | 800f41e: 687b ldr r3, [r7, #4] 800f420: 689a ldr r2, [r3, #8] 800f422: 687b ldr r3, [r7, #4] 800f424: 68db ldr r3, [r3, #12] 800f426: 431a orrs r2, r3 800f428: 687b ldr r3, [r7, #4] 800f42a: 691b ldr r3, [r3, #16] 800f42c: 431a orrs r2, r3 800f42e: 687b ldr r3, [r7, #4] 800f430: 695b ldr r3, [r3, #20] 800f432: ea42 0103 orr.w r1, r2, r3 800f436: 687b ldr r3, [r7, #4] 800f438: 685b ldr r3, [r3, #4] 800f43a: 1e5a subs r2, r3, #1 800f43c: 687b ldr r3, [r7, #4] 800f43e: 681b ldr r3, [r3, #0] 800f440: 430a orrs r2, r1 800f442: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800f444: 687b ldr r3, [r7, #4] 800f446: 2200 movs r2, #0 800f448: 625a str r2, [r3, #36] @ 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; 800f44a: 687b ldr r3, [r7, #4] 800f44c: 2201 movs r2, #1 800f44e: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800f452: 2300 movs r3, #0 } 800f454: 4618 mov r0, r3 800f456: 3710 adds r7, #16 800f458: 46bd mov sp, r7 800f45a: bd80 pop {r7, pc} 0800f45c : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { 800f45c: b480 push {r7} 800f45e: b087 sub sp, #28 800f460: af00 add r7, sp, #0 800f462: 6078 str r0, [r7, #4] 800f464: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; 800f466: 687b ldr r3, [r7, #4] 800f468: 681b ldr r3, [r3, #0] 800f46a: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; 800f46c: 687b ldr r3, [r7, #4] 800f46e: f893 3020 ldrb.w r3, [r3, #32] 800f472: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || 800f474: 7cfb ldrb r3, [r7, #19] 800f476: 2b01 cmp r3, #1 800f478: d003 beq.n 800f482 800f47a: 7cfb ldrb r3, [r7, #19] 800f47c: 2b02 cmp r3, #2 800f47e: f040 80be bne.w 800f5fe assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); #if defined(CAN2) /* CAN1 and CAN2 are dual instances with 28 common filters banks */ /* Select master instance to access the filter banks */ can_ip = CAN1; 800f482: 4b65 ldr r3, [pc, #404] @ (800f618 ) 800f484: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); #endif /* CAN3 */ /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); 800f486: 697b ldr r3, [r7, #20] 800f488: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800f48c: f043 0201 orr.w r2, r3, #1 800f490: 697b ldr r3, [r7, #20] 800f492: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #if defined(CAN2) /* Select the start filter number of CAN2 slave instance */ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); 800f496: 697b ldr r3, [r7, #20] 800f498: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800f49c: f423 527c bic.w r2, r3, #16128 @ 0x3f00 800f4a0: 697b ldr r3, [r7, #20] 800f4a2: f8c3 2200 str.w r2, [r3, #512] @ 0x200 SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); 800f4a6: 697b ldr r3, [r7, #20] 800f4a8: f8d3 2200 ldr.w r2, [r3, #512] @ 0x200 800f4ac: 683b ldr r3, [r7, #0] 800f4ae: 6a5b ldr r3, [r3, #36] @ 0x24 800f4b0: 021b lsls r3, r3, #8 800f4b2: 431a orrs r2, r3 800f4b4: 697b ldr r3, [r7, #20] 800f4b6: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #endif /* CAN3 */ /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); 800f4ba: 683b ldr r3, [r7, #0] 800f4bc: 695b ldr r3, [r3, #20] 800f4be: f003 031f and.w r3, r3, #31 800f4c2: 2201 movs r2, #1 800f4c4: fa02 f303 lsl.w r3, r2, r3 800f4c8: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); 800f4ca: 697b ldr r3, [r7, #20] 800f4cc: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800f4d0: 68fb ldr r3, [r7, #12] 800f4d2: 43db mvns r3, r3 800f4d4: 401a ands r2, r3 800f4d6: 697b ldr r3, [r7, #20] 800f4d8: f8c3 221c str.w r2, [r3, #540] @ 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) 800f4dc: 683b ldr r3, [r7, #0] 800f4de: 69db ldr r3, [r3, #28] 800f4e0: 2b00 cmp r3, #0 800f4e2: d123 bne.n 800f52c { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); 800f4e4: 697b ldr r3, [r7, #20] 800f4e6: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800f4ea: 68fb ldr r3, [r7, #12] 800f4ec: 43db mvns r3, r3 800f4ee: 401a ands r2, r3 800f4f0: 697b ldr r3, [r7, #20] 800f4f2: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800f4f6: 683b ldr r3, [r7, #0] 800f4f8: 68db ldr r3, [r3, #12] 800f4fa: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800f4fc: 683b ldr r3, [r7, #0] 800f4fe: 685b ldr r3, [r3, #4] 800f500: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800f502: 683a ldr r2, [r7, #0] 800f504: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800f506: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800f508: 697b ldr r3, [r7, #20] 800f50a: 3248 adds r2, #72 @ 0x48 800f50c: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800f510: 683b ldr r3, [r7, #0] 800f512: 689b ldr r3, [r3, #8] 800f514: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); 800f516: 683b ldr r3, [r7, #0] 800f518: 681b ldr r3, [r3, #0] 800f51a: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800f51c: 683b ldr r3, [r7, #0] 800f51e: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800f520: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800f522: 6979 ldr r1, [r7, #20] 800f524: 3348 adds r3, #72 @ 0x48 800f526: 00db lsls r3, r3, #3 800f528: 440b add r3, r1 800f52a: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) 800f52c: 683b ldr r3, [r7, #0] 800f52e: 69db ldr r3, [r3, #28] 800f530: 2b01 cmp r3, #1 800f532: d122 bne.n 800f57a { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); 800f534: 697b ldr r3, [r7, #20] 800f536: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800f53a: 68fb ldr r3, [r7, #12] 800f53c: 431a orrs r2, r3 800f53e: 697b ldr r3, [r7, #20] 800f540: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800f544: 683b ldr r3, [r7, #0] 800f546: 681b ldr r3, [r3, #0] 800f548: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800f54a: 683b ldr r3, [r7, #0] 800f54c: 685b ldr r3, [r3, #4] 800f54e: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800f550: 683a ldr r2, [r7, #0] 800f552: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800f554: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800f556: 697b ldr r3, [r7, #20] 800f558: 3248 adds r2, #72 @ 0x48 800f55a: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800f55e: 683b ldr r3, [r7, #0] 800f560: 689b ldr r3, [r3, #8] 800f562: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); 800f564: 683b ldr r3, [r7, #0] 800f566: 68db ldr r3, [r3, #12] 800f568: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800f56a: 683b ldr r3, [r7, #0] 800f56c: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800f56e: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800f570: 6979 ldr r1, [r7, #20] 800f572: 3348 adds r3, #72 @ 0x48 800f574: 00db lsls r3, r3, #3 800f576: 440b add r3, r1 800f578: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) 800f57a: 683b ldr r3, [r7, #0] 800f57c: 699b ldr r3, [r3, #24] 800f57e: 2b00 cmp r3, #0 800f580: d109 bne.n 800f596 { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); 800f582: 697b ldr r3, [r7, #20] 800f584: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800f588: 68fb ldr r3, [r7, #12] 800f58a: 43db mvns r3, r3 800f58c: 401a ands r2, r3 800f58e: 697b ldr r3, [r7, #20] 800f590: f8c3 2204 str.w r2, [r3, #516] @ 0x204 800f594: e007 b.n 800f5a6 } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); 800f596: 697b ldr r3, [r7, #20] 800f598: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800f59c: 68fb ldr r3, [r7, #12] 800f59e: 431a orrs r2, r3 800f5a0: 697b ldr r3, [r7, #20] 800f5a2: f8c3 2204 str.w r2, [r3, #516] @ 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) 800f5a6: 683b ldr r3, [r7, #0] 800f5a8: 691b ldr r3, [r3, #16] 800f5aa: 2b00 cmp r3, #0 800f5ac: d109 bne.n 800f5c2 { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); 800f5ae: 697b ldr r3, [r7, #20] 800f5b0: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800f5b4: 68fb ldr r3, [r7, #12] 800f5b6: 43db mvns r3, r3 800f5b8: 401a ands r2, r3 800f5ba: 697b ldr r3, [r7, #20] 800f5bc: f8c3 2214 str.w r2, [r3, #532] @ 0x214 800f5c0: e007 b.n 800f5d2 } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); 800f5c2: 697b ldr r3, [r7, #20] 800f5c4: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800f5c8: 68fb ldr r3, [r7, #12] 800f5ca: 431a orrs r2, r3 800f5cc: 697b ldr r3, [r7, #20] 800f5ce: f8c3 2214 str.w r2, [r3, #532] @ 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) 800f5d2: 683b ldr r3, [r7, #0] 800f5d4: 6a1b ldr r3, [r3, #32] 800f5d6: 2b01 cmp r3, #1 800f5d8: d107 bne.n 800f5ea { SET_BIT(can_ip->FA1R, filternbrbitpos); 800f5da: 697b ldr r3, [r7, #20] 800f5dc: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800f5e0: 68fb ldr r3, [r7, #12] 800f5e2: 431a orrs r2, r3 800f5e4: 697b ldr r3, [r7, #20] 800f5e6: f8c3 221c str.w r2, [r3, #540] @ 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); 800f5ea: 697b ldr r3, [r7, #20] 800f5ec: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800f5f0: f023 0201 bic.w r2, r3, #1 800f5f4: 697b ldr r3, [r7, #20] 800f5f6: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Return function status */ return HAL_OK; 800f5fa: 2300 movs r3, #0 800f5fc: e006 b.n 800f60c } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f5fe: 687b ldr r3, [r7, #4] 800f600: 6a5b ldr r3, [r3, #36] @ 0x24 800f602: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f606: 687b ldr r3, [r7, #4] 800f608: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f60a: 2301 movs r3, #1 } } 800f60c: 4618 mov r0, r3 800f60e: 371c adds r7, #28 800f610: 46bd mov sp, r7 800f612: bc80 pop {r7} 800f614: 4770 bx lr 800f616: bf00 nop 800f618: 40006400 .word 0x40006400 0800f61c : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { 800f61c: b580 push {r7, lr} 800f61e: b084 sub sp, #16 800f620: af00 add r7, sp, #0 800f622: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) 800f624: 687b ldr r3, [r7, #4] 800f626: f893 3020 ldrb.w r3, [r3, #32] 800f62a: b2db uxtb r3, r3 800f62c: 2b01 cmp r3, #1 800f62e: d12e bne.n 800f68e { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; 800f630: 687b ldr r3, [r7, #4] 800f632: 2202 movs r2, #2 800f634: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800f638: 687b ldr r3, [r7, #4] 800f63a: 681b ldr r3, [r3, #0] 800f63c: 681a ldr r2, [r3, #0] 800f63e: 687b ldr r3, [r7, #4] 800f640: 681b ldr r3, [r3, #0] 800f642: f022 0201 bic.w r2, r2, #1 800f646: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800f648: f7ff f89e bl 800e788 800f64c: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800f64e: e012 b.n 800f676 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800f650: f7ff f89a bl 800e788 800f654: 4602 mov r2, r0 800f656: 68fb ldr r3, [r7, #12] 800f658: 1ad3 subs r3, r2, r3 800f65a: 2b0a cmp r3, #10 800f65c: d90b bls.n 800f676 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800f65e: 687b ldr r3, [r7, #4] 800f660: 6a5b ldr r3, [r3, #36] @ 0x24 800f662: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800f666: 687b ldr r3, [r7, #4] 800f668: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800f66a: 687b ldr r3, [r7, #4] 800f66c: 2205 movs r2, #5 800f66e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800f672: 2301 movs r3, #1 800f674: e012 b.n 800f69c while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800f676: 687b ldr r3, [r7, #4] 800f678: 681b ldr r3, [r3, #0] 800f67a: 685b ldr r3, [r3, #4] 800f67c: f003 0301 and.w r3, r3, #1 800f680: 2b00 cmp r3, #0 800f682: d1e5 bne.n 800f650 } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800f684: 687b ldr r3, [r7, #4] 800f686: 2200 movs r2, #0 800f688: 625a str r2, [r3, #36] @ 0x24 /* Return function status */ return HAL_OK; 800f68a: 2300 movs r3, #0 800f68c: e006 b.n 800f69c } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; 800f68e: 687b ldr r3, [r7, #4] 800f690: 6a5b ldr r3, [r3, #36] @ 0x24 800f692: f443 2200 orr.w r2, r3, #524288 @ 0x80000 800f696: 687b ldr r3, [r7, #4] 800f698: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f69a: 2301 movs r3, #1 } } 800f69c: 4618 mov r0, r3 800f69e: 3710 adds r7, #16 800f6a0: 46bd mov sp, r7 800f6a2: bd80 pop {r7, pc} 0800f6a4 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { 800f6a4: b580 push {r7, lr} 800f6a6: b084 sub sp, #16 800f6a8: af00 add r7, sp, #0 800f6aa: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_LISTENING) 800f6ac: 687b ldr r3, [r7, #4] 800f6ae: f893 3020 ldrb.w r3, [r3, #32] 800f6b2: b2db uxtb r3, r3 800f6b4: 2b02 cmp r3, #2 800f6b6: d133 bne.n 800f720 { /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800f6b8: 687b ldr r3, [r7, #4] 800f6ba: 681b ldr r3, [r3, #0] 800f6bc: 681a ldr r2, [r3, #0] 800f6be: 687b ldr r3, [r7, #4] 800f6c0: 681b ldr r3, [r3, #0] 800f6c2: f042 0201 orr.w r2, r2, #1 800f6c6: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800f6c8: f7ff f85e bl 800e788 800f6cc: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800f6ce: e012 b.n 800f6f6 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800f6d0: f7ff f85a bl 800e788 800f6d4: 4602 mov r2, r0 800f6d6: 68fb ldr r3, [r7, #12] 800f6d8: 1ad3 subs r3, r2, r3 800f6da: 2b0a cmp r3, #10 800f6dc: d90b bls.n 800f6f6 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800f6de: 687b ldr r3, [r7, #4] 800f6e0: 6a5b ldr r3, [r3, #36] @ 0x24 800f6e2: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800f6e6: 687b ldr r3, [r7, #4] 800f6e8: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800f6ea: 687b ldr r3, [r7, #4] 800f6ec: 2205 movs r2, #5 800f6ee: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800f6f2: 2301 movs r3, #1 800f6f4: e01b b.n 800f72e while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800f6f6: 687b ldr r3, [r7, #4] 800f6f8: 681b ldr r3, [r3, #0] 800f6fa: 685b ldr r3, [r3, #4] 800f6fc: f003 0301 and.w r3, r3, #1 800f700: 2b00 cmp r3, #0 800f702: d0e5 beq.n 800f6d0 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800f704: 687b ldr r3, [r7, #4] 800f706: 681b ldr r3, [r3, #0] 800f708: 681a ldr r2, [r3, #0] 800f70a: 687b ldr r3, [r7, #4] 800f70c: 681b ldr r3, [r3, #0] 800f70e: f022 0202 bic.w r2, r2, #2 800f712: 601a str r2, [r3, #0] /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_READY; 800f714: 687b ldr r3, [r7, #4] 800f716: 2201 movs r2, #1 800f718: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800f71c: 2300 movs r3, #0 800f71e: e006 b.n 800f72e } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; 800f720: 687b ldr r3, [r7, #4] 800f722: 6a5b ldr r3, [r3, #36] @ 0x24 800f724: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800f728: 687b ldr r3, [r7, #4] 800f72a: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f72c: 2301 movs r3, #1 } } 800f72e: 4618 mov r0, r3 800f730: 3710 adds r7, #16 800f732: 46bd mov sp, r7 800f734: bd80 pop {r7, pc} 0800f736 : * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, const uint8_t aData[], uint32_t *pTxMailbox) { 800f736: b480 push {r7} 800f738: b089 sub sp, #36 @ 0x24 800f73a: af00 add r7, sp, #0 800f73c: 60f8 str r0, [r7, #12] 800f73e: 60b9 str r1, [r7, #8] 800f740: 607a str r2, [r7, #4] 800f742: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; 800f744: 68fb ldr r3, [r7, #12] 800f746: f893 3020 ldrb.w r3, [r3, #32] 800f74a: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); 800f74c: 68fb ldr r3, [r7, #12] 800f74e: 681b ldr r3, [r3, #0] 800f750: 689b ldr r3, [r3, #8] 800f752: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || 800f754: 7ffb ldrb r3, [r7, #31] 800f756: 2b01 cmp r3, #1 800f758: d003 beq.n 800f762 800f75a: 7ffb ldrb r3, [r7, #31] 800f75c: 2b02 cmp r3, #2 800f75e: f040 80ad bne.w 800f8bc (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || 800f762: 69bb ldr r3, [r7, #24] 800f764: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800f768: 2b00 cmp r3, #0 800f76a: d10a bne.n 800f782 ((tsr & CAN_TSR_TME1) != 0U) || 800f76c: 69bb ldr r3, [r7, #24] 800f76e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || 800f772: 2b00 cmp r3, #0 800f774: d105 bne.n 800f782 ((tsr & CAN_TSR_TME2) != 0U)) 800f776: 69bb ldr r3, [r7, #24] 800f778: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || 800f77c: 2b00 cmp r3, #0 800f77e: f000 8095 beq.w 800f8ac { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; 800f782: 69bb ldr r3, [r7, #24] 800f784: 0e1b lsrs r3, r3, #24 800f786: f003 0303 and.w r3, r3, #3 800f78a: 617b str r3, [r7, #20] /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; 800f78c: 2201 movs r2, #1 800f78e: 697b ldr r3, [r7, #20] 800f790: 409a lsls r2, r3 800f792: 683b ldr r3, [r7, #0] 800f794: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) 800f796: 68bb ldr r3, [r7, #8] 800f798: 689b ldr r3, [r3, #8] 800f79a: 2b00 cmp r3, #0 800f79c: d10d bne.n 800f7ba { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800f79e: 68bb ldr r3, [r7, #8] 800f7a0: 681b ldr r3, [r3, #0] 800f7a2: 055a lsls r2, r3, #21 pHeader->RTR); 800f7a4: 68bb ldr r3, [r7, #8] 800f7a6: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800f7a8: 68f9 ldr r1, [r7, #12] 800f7aa: 6809 ldr r1, [r1, #0] 800f7ac: 431a orrs r2, r3 800f7ae: 697b ldr r3, [r7, #20] 800f7b0: 3318 adds r3, #24 800f7b2: 011b lsls r3, r3, #4 800f7b4: 440b add r3, r1 800f7b6: 601a str r2, [r3, #0] 800f7b8: e00f b.n 800f7da } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f7ba: 68bb ldr r3, [r7, #8] 800f7bc: 685b ldr r3, [r3, #4] 800f7be: 00da lsls r2, r3, #3 pHeader->IDE | 800f7c0: 68bb ldr r3, [r7, #8] 800f7c2: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f7c4: 431a orrs r2, r3 pHeader->RTR); 800f7c6: 68bb ldr r3, [r7, #8] 800f7c8: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f7ca: 68f9 ldr r1, [r7, #12] 800f7cc: 6809 ldr r1, [r1, #0] pHeader->IDE | 800f7ce: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f7d0: 697b ldr r3, [r7, #20] 800f7d2: 3318 adds r3, #24 800f7d4: 011b lsls r3, r3, #4 800f7d6: 440b add r3, r1 800f7d8: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); 800f7da: 68fb ldr r3, [r7, #12] 800f7dc: 6819 ldr r1, [r3, #0] 800f7de: 68bb ldr r3, [r7, #8] 800f7e0: 691a ldr r2, [r3, #16] 800f7e2: 697b ldr r3, [r7, #20] 800f7e4: 3318 adds r3, #24 800f7e6: 011b lsls r3, r3, #4 800f7e8: 440b add r3, r1 800f7ea: 3304 adds r3, #4 800f7ec: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) 800f7ee: 68bb ldr r3, [r7, #8] 800f7f0: 7d1b ldrb r3, [r3, #20] 800f7f2: 2b01 cmp r3, #1 800f7f4: d111 bne.n 800f81a { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); 800f7f6: 68fb ldr r3, [r7, #12] 800f7f8: 681a ldr r2, [r3, #0] 800f7fa: 697b ldr r3, [r7, #20] 800f7fc: 3318 adds r3, #24 800f7fe: 011b lsls r3, r3, #4 800f800: 4413 add r3, r2 800f802: 3304 adds r3, #4 800f804: 681b ldr r3, [r3, #0] 800f806: 68fa ldr r2, [r7, #12] 800f808: 6811 ldr r1, [r2, #0] 800f80a: f443 7280 orr.w r2, r3, #256 @ 0x100 800f80e: 697b ldr r3, [r7, #20] 800f810: 3318 adds r3, #24 800f812: 011b lsls r3, r3, #4 800f814: 440b add r3, r1 800f816: 3304 adds r3, #4 800f818: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, 800f81a: 687b ldr r3, [r7, #4] 800f81c: 3307 adds r3, #7 800f81e: 781b ldrb r3, [r3, #0] 800f820: 061a lsls r2, r3, #24 800f822: 687b ldr r3, [r7, #4] 800f824: 3306 adds r3, #6 800f826: 781b ldrb r3, [r3, #0] 800f828: 041b lsls r3, r3, #16 800f82a: 431a orrs r2, r3 800f82c: 687b ldr r3, [r7, #4] 800f82e: 3305 adds r3, #5 800f830: 781b ldrb r3, [r3, #0] 800f832: 021b lsls r3, r3, #8 800f834: 4313 orrs r3, r2 800f836: 687a ldr r2, [r7, #4] 800f838: 3204 adds r2, #4 800f83a: 7812 ldrb r2, [r2, #0] 800f83c: 4610 mov r0, r2 800f83e: 68fa ldr r2, [r7, #12] 800f840: 6811 ldr r1, [r2, #0] 800f842: ea43 0200 orr.w r2, r3, r0 800f846: 697b ldr r3, [r7, #20] 800f848: 011b lsls r3, r3, #4 800f84a: 440b add r3, r1 800f84c: f503 73c6 add.w r3, r3, #396 @ 0x18c 800f850: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, 800f852: 687b ldr r3, [r7, #4] 800f854: 3303 adds r3, #3 800f856: 781b ldrb r3, [r3, #0] 800f858: 061a lsls r2, r3, #24 800f85a: 687b ldr r3, [r7, #4] 800f85c: 3302 adds r3, #2 800f85e: 781b ldrb r3, [r3, #0] 800f860: 041b lsls r3, r3, #16 800f862: 431a orrs r2, r3 800f864: 687b ldr r3, [r7, #4] 800f866: 3301 adds r3, #1 800f868: 781b ldrb r3, [r3, #0] 800f86a: 021b lsls r3, r3, #8 800f86c: 4313 orrs r3, r2 800f86e: 687a ldr r2, [r7, #4] 800f870: 7812 ldrb r2, [r2, #0] 800f872: 4610 mov r0, r2 800f874: 68fa ldr r2, [r7, #12] 800f876: 6811 ldr r1, [r2, #0] 800f878: ea43 0200 orr.w r2, r3, r0 800f87c: 697b ldr r3, [r7, #20] 800f87e: 011b lsls r3, r3, #4 800f880: 440b add r3, r1 800f882: f503 73c4 add.w r3, r3, #392 @ 0x188 800f886: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); 800f888: 68fb ldr r3, [r7, #12] 800f88a: 681a ldr r2, [r3, #0] 800f88c: 697b ldr r3, [r7, #20] 800f88e: 3318 adds r3, #24 800f890: 011b lsls r3, r3, #4 800f892: 4413 add r3, r2 800f894: 681b ldr r3, [r3, #0] 800f896: 68fa ldr r2, [r7, #12] 800f898: 6811 ldr r1, [r2, #0] 800f89a: f043 0201 orr.w r2, r3, #1 800f89e: 697b ldr r3, [r7, #20] 800f8a0: 3318 adds r3, #24 800f8a2: 011b lsls r3, r3, #4 800f8a4: 440b add r3, r1 800f8a6: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800f8a8: 2300 movs r3, #0 800f8aa: e00e b.n 800f8ca } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800f8ac: 68fb ldr r3, [r7, #12] 800f8ae: 6a5b ldr r3, [r3, #36] @ 0x24 800f8b0: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800f8b4: 68fb ldr r3, [r7, #12] 800f8b6: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f8b8: 2301 movs r3, #1 800f8ba: e006 b.n 800f8ca } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f8bc: 68fb ldr r3, [r7, #12] 800f8be: 6a5b ldr r3, [r3, #36] @ 0x24 800f8c0: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f8c4: 68fb ldr r3, [r7, #12] 800f8c6: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f8c8: 2301 movs r3, #1 } } 800f8ca: 4618 mov r0, r3 800f8cc: 3724 adds r7, #36 @ 0x24 800f8ce: 46bd mov sp, r7 800f8d0: bc80 pop {r7} 800f8d2: 4770 bx lr 0800f8d4 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval Number of free Tx Mailboxes. */ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) { 800f8d4: b480 push {r7} 800f8d6: b085 sub sp, #20 800f8d8: af00 add r7, sp, #0 800f8da: 6078 str r0, [r7, #4] uint32_t freelevel = 0U; 800f8dc: 2300 movs r3, #0 800f8de: 60fb str r3, [r7, #12] HAL_CAN_StateTypeDef state = hcan->State; 800f8e0: 687b ldr r3, [r7, #4] 800f8e2: f893 3020 ldrb.w r3, [r3, #32] 800f8e6: 72fb strb r3, [r7, #11] if ((state == HAL_CAN_STATE_READY) || 800f8e8: 7afb ldrb r3, [r7, #11] 800f8ea: 2b01 cmp r3, #1 800f8ec: d002 beq.n 800f8f4 800f8ee: 7afb ldrb r3, [r7, #11] 800f8f0: 2b02 cmp r3, #2 800f8f2: d11d bne.n 800f930 (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 status */ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) 800f8f4: 687b ldr r3, [r7, #4] 800f8f6: 681b ldr r3, [r3, #0] 800f8f8: 689b ldr r3, [r3, #8] 800f8fa: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800f8fe: 2b00 cmp r3, #0 800f900: d002 beq.n 800f908 { freelevel++; 800f902: 68fb ldr r3, [r7, #12] 800f904: 3301 adds r3, #1 800f906: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 1 status */ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) 800f908: 687b ldr r3, [r7, #4] 800f90a: 681b ldr r3, [r3, #0] 800f90c: 689b ldr r3, [r3, #8] 800f90e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800f912: 2b00 cmp r3, #0 800f914: d002 beq.n 800f91c { freelevel++; 800f916: 68fb ldr r3, [r7, #12] 800f918: 3301 adds r3, #1 800f91a: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 2 status */ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) 800f91c: 687b ldr r3, [r7, #4] 800f91e: 681b ldr r3, [r3, #0] 800f920: 689b ldr r3, [r3, #8] 800f922: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800f926: 2b00 cmp r3, #0 800f928: d002 beq.n 800f930 { freelevel++; 800f92a: 68fb ldr r3, [r7, #12] 800f92c: 3301 adds r3, #1 800f92e: 60fb str r3, [r7, #12] } } /* Return Tx Mailboxes free level */ return freelevel; 800f930: 68fb ldr r3, [r7, #12] } 800f932: 4618 mov r0, r3 800f934: 3714 adds r7, #20 800f936: 46bd mov sp, r7 800f938: bc80 pop {r7} 800f93a: 4770 bx lr 0800f93c : * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { 800f93c: b480 push {r7} 800f93e: b087 sub sp, #28 800f940: af00 add r7, sp, #0 800f942: 60f8 str r0, [r7, #12] 800f944: 60b9 str r1, [r7, #8] 800f946: 607a str r2, [r7, #4] 800f948: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800f94a: 68fb ldr r3, [r7, #12] 800f94c: f893 3020 ldrb.w r3, [r3, #32] 800f950: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || 800f952: 7dfb ldrb r3, [r7, #23] 800f954: 2b01 cmp r3, #1 800f956: d003 beq.n 800f960 800f958: 7dfb ldrb r3, [r7, #23] 800f95a: 2b02 cmp r3, #2 800f95c: f040 8103 bne.w 800fb66 (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800f960: 68bb ldr r3, [r7, #8] 800f962: 2b00 cmp r3, #0 800f964: d10e bne.n 800f984 { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) 800f966: 68fb ldr r3, [r7, #12] 800f968: 681b ldr r3, [r3, #0] 800f96a: 68db ldr r3, [r3, #12] 800f96c: f003 0303 and.w r3, r3, #3 800f970: 2b00 cmp r3, #0 800f972: d116 bne.n 800f9a2 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800f974: 68fb ldr r3, [r7, #12] 800f976: 6a5b ldr r3, [r3, #36] @ 0x24 800f978: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800f97c: 68fb ldr r3, [r7, #12] 800f97e: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f980: 2301 movs r3, #1 800f982: e0f7 b.n 800fb74 } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) 800f984: 68fb ldr r3, [r7, #12] 800f986: 681b ldr r3, [r3, #0] 800f988: 691b ldr r3, [r3, #16] 800f98a: f003 0303 and.w r3, r3, #3 800f98e: 2b00 cmp r3, #0 800f990: d107 bne.n 800f9a2 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800f992: 68fb ldr r3, [r7, #12] 800f994: 6a5b ldr r3, [r3, #36] @ 0x24 800f996: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800f99a: 68fb ldr r3, [r7, #12] 800f99c: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f99e: 2301 movs r3, #1 800f9a0: e0e8 b.n 800fb74 } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; 800f9a2: 68fb ldr r3, [r7, #12] 800f9a4: 681a ldr r2, [r3, #0] 800f9a6: 68bb ldr r3, [r7, #8] 800f9a8: 331b adds r3, #27 800f9aa: 011b lsls r3, r3, #4 800f9ac: 4413 add r3, r2 800f9ae: 681b ldr r3, [r3, #0] 800f9b0: f003 0204 and.w r2, r3, #4 800f9b4: 687b ldr r3, [r7, #4] 800f9b6: 609a str r2, [r3, #8] if (pHeader->IDE == CAN_ID_STD) 800f9b8: 687b ldr r3, [r7, #4] 800f9ba: 689b ldr r3, [r3, #8] 800f9bc: 2b00 cmp r3, #0 800f9be: d10c bne.n 800f9da { pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; 800f9c0: 68fb ldr r3, [r7, #12] 800f9c2: 681a ldr r2, [r3, #0] 800f9c4: 68bb ldr r3, [r7, #8] 800f9c6: 331b adds r3, #27 800f9c8: 011b lsls r3, r3, #4 800f9ca: 4413 add r3, r2 800f9cc: 681b ldr r3, [r3, #0] 800f9ce: 0d5b lsrs r3, r3, #21 800f9d0: f3c3 020a ubfx r2, r3, #0, #11 800f9d4: 687b ldr r3, [r7, #4] 800f9d6: 601a str r2, [r3, #0] 800f9d8: e00b b.n 800f9f2 } else { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; 800f9da: 68fb ldr r3, [r7, #12] 800f9dc: 681a ldr r2, [r3, #0] 800f9de: 68bb ldr r3, [r7, #8] 800f9e0: 331b adds r3, #27 800f9e2: 011b lsls r3, r3, #4 800f9e4: 4413 add r3, r2 800f9e6: 681b ldr r3, [r3, #0] 800f9e8: 08db lsrs r3, r3, #3 800f9ea: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & 800f9ee: 687b ldr r3, [r7, #4] 800f9f0: 605a str r2, [r3, #4] } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); 800f9f2: 68fb ldr r3, [r7, #12] 800f9f4: 681a ldr r2, [r3, #0] 800f9f6: 68bb ldr r3, [r7, #8] 800f9f8: 331b adds r3, #27 800f9fa: 011b lsls r3, r3, #4 800f9fc: 4413 add r3, r2 800f9fe: 681b ldr r3, [r3, #0] 800fa00: f003 0202 and.w r2, r3, #2 800fa04: 687b ldr r3, [r7, #4] 800fa06: 60da str r2, [r3, #12] if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) 800fa08: 68fb ldr r3, [r7, #12] 800fa0a: 681a ldr r2, [r3, #0] 800fa0c: 68bb ldr r3, [r7, #8] 800fa0e: 331b adds r3, #27 800fa10: 011b lsls r3, r3, #4 800fa12: 4413 add r3, r2 800fa14: 3304 adds r3, #4 800fa16: 681b ldr r3, [r3, #0] 800fa18: f003 0308 and.w r3, r3, #8 800fa1c: 2b00 cmp r3, #0 800fa1e: d003 beq.n 800fa28 { /* Truncate DLC to 8 if received field is over range */ pHeader->DLC = 8U; 800fa20: 687b ldr r3, [r7, #4] 800fa22: 2208 movs r2, #8 800fa24: 611a str r2, [r3, #16] 800fa26: e00b b.n 800fa40 } else { pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; 800fa28: 68fb ldr r3, [r7, #12] 800fa2a: 681a ldr r2, [r3, #0] 800fa2c: 68bb ldr r3, [r7, #8] 800fa2e: 331b adds r3, #27 800fa30: 011b lsls r3, r3, #4 800fa32: 4413 add r3, r2 800fa34: 3304 adds r3, #4 800fa36: 681b ldr r3, [r3, #0] 800fa38: f003 020f and.w r2, r3, #15 800fa3c: 687b ldr r3, [r7, #4] 800fa3e: 611a str r2, [r3, #16] } pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; 800fa40: 68fb ldr r3, [r7, #12] 800fa42: 681a ldr r2, [r3, #0] 800fa44: 68bb ldr r3, [r7, #8] 800fa46: 331b adds r3, #27 800fa48: 011b lsls r3, r3, #4 800fa4a: 4413 add r3, r2 800fa4c: 3304 adds r3, #4 800fa4e: 681b ldr r3, [r3, #0] 800fa50: 0a1b lsrs r3, r3, #8 800fa52: b2da uxtb r2, r3 800fa54: 687b ldr r3, [r7, #4] 800fa56: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; 800fa58: 68fb ldr r3, [r7, #12] 800fa5a: 681a ldr r2, [r3, #0] 800fa5c: 68bb ldr r3, [r7, #8] 800fa5e: 331b adds r3, #27 800fa60: 011b lsls r3, r3, #4 800fa62: 4413 add r3, r2 800fa64: 3304 adds r3, #4 800fa66: 681b ldr r3, [r3, #0] 800fa68: 0c1b lsrs r3, r3, #16 800fa6a: b29a uxth r2, r3 800fa6c: 687b ldr r3, [r7, #4] 800fa6e: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); 800fa70: 68fb ldr r3, [r7, #12] 800fa72: 681a ldr r2, [r3, #0] 800fa74: 68bb ldr r3, [r7, #8] 800fa76: 011b lsls r3, r3, #4 800fa78: 4413 add r3, r2 800fa7a: f503 73dc add.w r3, r3, #440 @ 0x1b8 800fa7e: 681b ldr r3, [r3, #0] 800fa80: b2da uxtb r2, r3 800fa82: 683b ldr r3, [r7, #0] 800fa84: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); 800fa86: 68fb ldr r3, [r7, #12] 800fa88: 681a ldr r2, [r3, #0] 800fa8a: 68bb ldr r3, [r7, #8] 800fa8c: 011b lsls r3, r3, #4 800fa8e: 4413 add r3, r2 800fa90: f503 73dc add.w r3, r3, #440 @ 0x1b8 800fa94: 681b ldr r3, [r3, #0] 800fa96: 0a1a lsrs r2, r3, #8 800fa98: 683b ldr r3, [r7, #0] 800fa9a: 3301 adds r3, #1 800fa9c: b2d2 uxtb r2, r2 800fa9e: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); 800faa0: 68fb ldr r3, [r7, #12] 800faa2: 681a ldr r2, [r3, #0] 800faa4: 68bb ldr r3, [r7, #8] 800faa6: 011b lsls r3, r3, #4 800faa8: 4413 add r3, r2 800faaa: f503 73dc add.w r3, r3, #440 @ 0x1b8 800faae: 681b ldr r3, [r3, #0] 800fab0: 0c1a lsrs r2, r3, #16 800fab2: 683b ldr r3, [r7, #0] 800fab4: 3302 adds r3, #2 800fab6: b2d2 uxtb r2, r2 800fab8: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); 800faba: 68fb ldr r3, [r7, #12] 800fabc: 681a ldr r2, [r3, #0] 800fabe: 68bb ldr r3, [r7, #8] 800fac0: 011b lsls r3, r3, #4 800fac2: 4413 add r3, r2 800fac4: f503 73dc add.w r3, r3, #440 @ 0x1b8 800fac8: 681b ldr r3, [r3, #0] 800faca: 0e1a lsrs r2, r3, #24 800facc: 683b ldr r3, [r7, #0] 800face: 3303 adds r3, #3 800fad0: b2d2 uxtb r2, r2 800fad2: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); 800fad4: 68fb ldr r3, [r7, #12] 800fad6: 681a ldr r2, [r3, #0] 800fad8: 68bb ldr r3, [r7, #8] 800fada: 011b lsls r3, r3, #4 800fadc: 4413 add r3, r2 800fade: f503 73de add.w r3, r3, #444 @ 0x1bc 800fae2: 681a ldr r2, [r3, #0] 800fae4: 683b ldr r3, [r7, #0] 800fae6: 3304 adds r3, #4 800fae8: b2d2 uxtb r2, r2 800faea: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); 800faec: 68fb ldr r3, [r7, #12] 800faee: 681a ldr r2, [r3, #0] 800faf0: 68bb ldr r3, [r7, #8] 800faf2: 011b lsls r3, r3, #4 800faf4: 4413 add r3, r2 800faf6: f503 73de add.w r3, r3, #444 @ 0x1bc 800fafa: 681b ldr r3, [r3, #0] 800fafc: 0a1a lsrs r2, r3, #8 800fafe: 683b ldr r3, [r7, #0] 800fb00: 3305 adds r3, #5 800fb02: b2d2 uxtb r2, r2 800fb04: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); 800fb06: 68fb ldr r3, [r7, #12] 800fb08: 681a ldr r2, [r3, #0] 800fb0a: 68bb ldr r3, [r7, #8] 800fb0c: 011b lsls r3, r3, #4 800fb0e: 4413 add r3, r2 800fb10: f503 73de add.w r3, r3, #444 @ 0x1bc 800fb14: 681b ldr r3, [r3, #0] 800fb16: 0c1a lsrs r2, r3, #16 800fb18: 683b ldr r3, [r7, #0] 800fb1a: 3306 adds r3, #6 800fb1c: b2d2 uxtb r2, r2 800fb1e: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); 800fb20: 68fb ldr r3, [r7, #12] 800fb22: 681a ldr r2, [r3, #0] 800fb24: 68bb ldr r3, [r7, #8] 800fb26: 011b lsls r3, r3, #4 800fb28: 4413 add r3, r2 800fb2a: f503 73de add.w r3, r3, #444 @ 0x1bc 800fb2e: 681b ldr r3, [r3, #0] 800fb30: 0e1a lsrs r2, r3, #24 800fb32: 683b ldr r3, [r7, #0] 800fb34: 3307 adds r3, #7 800fb36: b2d2 uxtb r2, r2 800fb38: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800fb3a: 68bb ldr r3, [r7, #8] 800fb3c: 2b00 cmp r3, #0 800fb3e: d108 bne.n 800fb52 { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); 800fb40: 68fb ldr r3, [r7, #12] 800fb42: 681b ldr r3, [r3, #0] 800fb44: 68da ldr r2, [r3, #12] 800fb46: 68fb ldr r3, [r7, #12] 800fb48: 681b ldr r3, [r3, #0] 800fb4a: f042 0220 orr.w r2, r2, #32 800fb4e: 60da str r2, [r3, #12] 800fb50: e007 b.n 800fb62 } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); 800fb52: 68fb ldr r3, [r7, #12] 800fb54: 681b ldr r3, [r3, #0] 800fb56: 691a ldr r2, [r3, #16] 800fb58: 68fb ldr r3, [r7, #12] 800fb5a: 681b ldr r3, [r3, #0] 800fb5c: f042 0220 orr.w r2, r2, #32 800fb60: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; 800fb62: 2300 movs r3, #0 800fb64: e006 b.n 800fb74 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800fb66: 68fb ldr r3, [r7, #12] 800fb68: 6a5b ldr r3, [r3, #36] @ 0x24 800fb6a: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800fb6e: 68fb ldr r3, [r7, #12] 800fb70: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800fb72: 2301 movs r3, #1 } } 800fb74: 4618 mov r0, r3 800fb76: 371c adds r7, #28 800fb78: 46bd mov sp, r7 800fb7a: bc80 pop {r7} 800fb7c: 4770 bx lr 0800fb7e : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { 800fb7e: b480 push {r7} 800fb80: b085 sub sp, #20 800fb82: af00 add r7, sp, #0 800fb84: 6078 str r0, [r7, #4] 800fb86: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800fb88: 687b ldr r3, [r7, #4] 800fb8a: f893 3020 ldrb.w r3, [r3, #32] 800fb8e: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || 800fb90: 7bfb ldrb r3, [r7, #15] 800fb92: 2b01 cmp r3, #1 800fb94: d002 beq.n 800fb9c 800fb96: 7bfb ldrb r3, [r7, #15] 800fb98: 2b02 cmp r3, #2 800fb9a: d109 bne.n 800fbb0 (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); 800fb9c: 687b ldr r3, [r7, #4] 800fb9e: 681b ldr r3, [r3, #0] 800fba0: 6959 ldr r1, [r3, #20] 800fba2: 687b ldr r3, [r7, #4] 800fba4: 681b ldr r3, [r3, #0] 800fba6: 683a ldr r2, [r7, #0] 800fba8: 430a orrs r2, r1 800fbaa: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; 800fbac: 2300 movs r3, #0 800fbae: e006 b.n 800fbbe } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800fbb0: 687b ldr r3, [r7, #4] 800fbb2: 6a5b ldr r3, [r3, #36] @ 0x24 800fbb4: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800fbb8: 687b ldr r3, [r7, #4] 800fbba: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800fbbc: 2301 movs r3, #1 } } 800fbbe: 4618 mov r0, r3 800fbc0: 3714 adds r7, #20 800fbc2: 46bd mov sp, r7 800fbc4: bc80 pop {r7} 800fbc6: 4770 bx lr 0800fbc8 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { 800fbc8: b580 push {r7, lr} 800fbca: b08a sub sp, #40 @ 0x28 800fbcc: af00 add r7, sp, #0 800fbce: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; 800fbd0: 2300 movs r3, #0 800fbd2: 627b str r3, [r7, #36] @ 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); 800fbd4: 687b ldr r3, [r7, #4] 800fbd6: 681b ldr r3, [r3, #0] 800fbd8: 695b ldr r3, [r3, #20] 800fbda: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); 800fbdc: 687b ldr r3, [r7, #4] 800fbde: 681b ldr r3, [r3, #0] 800fbe0: 685b ldr r3, [r3, #4] 800fbe2: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); 800fbe4: 687b ldr r3, [r7, #4] 800fbe6: 681b ldr r3, [r3, #0] 800fbe8: 689b ldr r3, [r3, #8] 800fbea: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); 800fbec: 687b ldr r3, [r7, #4] 800fbee: 681b ldr r3, [r3, #0] 800fbf0: 68db ldr r3, [r3, #12] 800fbf2: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); 800fbf4: 687b ldr r3, [r7, #4] 800fbf6: 681b ldr r3, [r3, #0] 800fbf8: 691b ldr r3, [r3, #16] 800fbfa: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); 800fbfc: 687b ldr r3, [r7, #4] 800fbfe: 681b ldr r3, [r3, #0] 800fc00: 699b ldr r3, [r3, #24] 800fc02: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) 800fc04: 6a3b ldr r3, [r7, #32] 800fc06: f003 0301 and.w r3, r3, #1 800fc0a: 2b00 cmp r3, #0 800fc0c: d07c beq.n 800fd08 { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) 800fc0e: 69bb ldr r3, [r7, #24] 800fc10: f003 0301 and.w r3, r3, #1 800fc14: 2b00 cmp r3, #0 800fc16: d023 beq.n 800fc60 { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); 800fc18: 687b ldr r3, [r7, #4] 800fc1a: 681b ldr r3, [r3, #0] 800fc1c: 2201 movs r2, #1 800fc1e: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) 800fc20: 69bb ldr r3, [r7, #24] 800fc22: f003 0302 and.w r3, r3, #2 800fc26: 2b00 cmp r3, #0 800fc28: d003 beq.n 800fc32 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); 800fc2a: 6878 ldr r0, [r7, #4] 800fc2c: f000 f983 bl 800ff36 800fc30: e016 b.n 800fc60 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) 800fc32: 69bb ldr r3, [r7, #24] 800fc34: f003 0304 and.w r3, r3, #4 800fc38: 2b00 cmp r3, #0 800fc3a: d004 beq.n 800fc46 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; 800fc3c: 6a7b ldr r3, [r7, #36] @ 0x24 800fc3e: f443 6300 orr.w r3, r3, #2048 @ 0x800 800fc42: 627b str r3, [r7, #36] @ 0x24 800fc44: e00c b.n 800fc60 } else if ((tsrflags & CAN_TSR_TERR0) != 0U) 800fc46: 69bb ldr r3, [r7, #24] 800fc48: f003 0308 and.w r3, r3, #8 800fc4c: 2b00 cmp r3, #0 800fc4e: d004 beq.n 800fc5a { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; 800fc50: 6a7b ldr r3, [r7, #36] @ 0x24 800fc52: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800fc56: 627b str r3, [r7, #36] @ 0x24 800fc58: e002 b.n 800fc60 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); 800fc5a: 6878 ldr r0, [r7, #4] 800fc5c: f000 f986 bl 800ff6c } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) 800fc60: 69bb ldr r3, [r7, #24] 800fc62: f403 7380 and.w r3, r3, #256 @ 0x100 800fc66: 2b00 cmp r3, #0 800fc68: d024 beq.n 800fcb4 { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); 800fc6a: 687b ldr r3, [r7, #4] 800fc6c: 681b ldr r3, [r3, #0] 800fc6e: f44f 7280 mov.w r2, #256 @ 0x100 800fc72: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) 800fc74: 69bb ldr r3, [r7, #24] 800fc76: f403 7300 and.w r3, r3, #512 @ 0x200 800fc7a: 2b00 cmp r3, #0 800fc7c: d003 beq.n 800fc86 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); 800fc7e: 6878 ldr r0, [r7, #4] 800fc80: f000 f962 bl 800ff48 800fc84: e016 b.n 800fcb4 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) 800fc86: 69bb ldr r3, [r7, #24] 800fc88: f403 6380 and.w r3, r3, #1024 @ 0x400 800fc8c: 2b00 cmp r3, #0 800fc8e: d004 beq.n 800fc9a { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; 800fc90: 6a7b ldr r3, [r7, #36] @ 0x24 800fc92: f443 5300 orr.w r3, r3, #8192 @ 0x2000 800fc96: 627b str r3, [r7, #36] @ 0x24 800fc98: e00c b.n 800fcb4 } else if ((tsrflags & CAN_TSR_TERR1) != 0U) 800fc9a: 69bb ldr r3, [r7, #24] 800fc9c: f403 6300 and.w r3, r3, #2048 @ 0x800 800fca0: 2b00 cmp r3, #0 800fca2: d004 beq.n 800fcae { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; 800fca4: 6a7b ldr r3, [r7, #36] @ 0x24 800fca6: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800fcaa: 627b str r3, [r7, #36] @ 0x24 800fcac: e002 b.n 800fcb4 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); 800fcae: 6878 ldr r0, [r7, #4] 800fcb0: f000 f965 bl 800ff7e } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) 800fcb4: 69bb ldr r3, [r7, #24] 800fcb6: f403 3380 and.w r3, r3, #65536 @ 0x10000 800fcba: 2b00 cmp r3, #0 800fcbc: d024 beq.n 800fd08 { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); 800fcbe: 687b ldr r3, [r7, #4] 800fcc0: 681b ldr r3, [r3, #0] 800fcc2: f44f 3280 mov.w r2, #65536 @ 0x10000 800fcc6: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) 800fcc8: 69bb ldr r3, [r7, #24] 800fcca: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fcce: 2b00 cmp r3, #0 800fcd0: d003 beq.n 800fcda #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); 800fcd2: 6878 ldr r0, [r7, #4] 800fcd4: f000 f941 bl 800ff5a 800fcd8: e016 b.n 800fd08 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) 800fcda: 69bb ldr r3, [r7, #24] 800fcdc: f403 2380 and.w r3, r3, #262144 @ 0x40000 800fce0: 2b00 cmp r3, #0 800fce2: d004 beq.n 800fcee { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; 800fce4: 6a7b ldr r3, [r7, #36] @ 0x24 800fce6: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800fcea: 627b str r3, [r7, #36] @ 0x24 800fcec: e00c b.n 800fd08 } else if ((tsrflags & CAN_TSR_TERR2) != 0U) 800fcee: 69bb ldr r3, [r7, #24] 800fcf0: f403 2300 and.w r3, r3, #524288 @ 0x80000 800fcf4: 2b00 cmp r3, #0 800fcf6: d004 beq.n 800fd02 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; 800fcf8: 6a7b ldr r3, [r7, #36] @ 0x24 800fcfa: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800fcfe: 627b str r3, [r7, #36] @ 0x24 800fd00: e002 b.n 800fd08 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); 800fd02: 6878 ldr r0, [r7, #4] 800fd04: f000 f944 bl 800ff90 } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) 800fd08: 6a3b ldr r3, [r7, #32] 800fd0a: f003 0308 and.w r3, r3, #8 800fd0e: 2b00 cmp r3, #0 800fd10: d00c beq.n 800fd2c { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) 800fd12: 697b ldr r3, [r7, #20] 800fd14: f003 0310 and.w r3, r3, #16 800fd18: 2b00 cmp r3, #0 800fd1a: d007 beq.n 800fd2c { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; 800fd1c: 6a7b ldr r3, [r7, #36] @ 0x24 800fd1e: f443 7300 orr.w r3, r3, #512 @ 0x200 800fd22: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); 800fd24: 687b ldr r3, [r7, #4] 800fd26: 681b ldr r3, [r3, #0] 800fd28: 2210 movs r2, #16 800fd2a: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) 800fd2c: 6a3b ldr r3, [r7, #32] 800fd2e: f003 0304 and.w r3, r3, #4 800fd32: 2b00 cmp r3, #0 800fd34: d00b beq.n 800fd4e { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) 800fd36: 697b ldr r3, [r7, #20] 800fd38: f003 0308 and.w r3, r3, #8 800fd3c: 2b00 cmp r3, #0 800fd3e: d006 beq.n 800fd4e { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); 800fd40: 687b ldr r3, [r7, #4] 800fd42: 681b ldr r3, [r3, #0] 800fd44: 2208 movs r2, #8 800fd46: 60da str r2, [r3, #12] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); 800fd48: 6878 ldr r0, [r7, #4] 800fd4a: f000 f933 bl 800ffb4 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) 800fd4e: 6a3b ldr r3, [r7, #32] 800fd50: f003 0302 and.w r3, r3, #2 800fd54: 2b00 cmp r3, #0 800fd56: d009 beq.n 800fd6c { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) 800fd58: 687b ldr r3, [r7, #4] 800fd5a: 681b ldr r3, [r3, #0] 800fd5c: 68db ldr r3, [r3, #12] 800fd5e: f003 0303 and.w r3, r3, #3 800fd62: 2b00 cmp r3, #0 800fd64: d002 beq.n 800fd6c #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); 800fd66: 6878 ldr r0, [r7, #4] 800fd68: f000 f91b bl 800ffa2 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) 800fd6c: 6a3b ldr r3, [r7, #32] 800fd6e: f003 0340 and.w r3, r3, #64 @ 0x40 800fd72: 2b00 cmp r3, #0 800fd74: d00c beq.n 800fd90 { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) 800fd76: 693b ldr r3, [r7, #16] 800fd78: f003 0310 and.w r3, r3, #16 800fd7c: 2b00 cmp r3, #0 800fd7e: d007 beq.n 800fd90 { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; 800fd80: 6a7b ldr r3, [r7, #36] @ 0x24 800fd82: f443 6380 orr.w r3, r3, #1024 @ 0x400 800fd86: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); 800fd88: 687b ldr r3, [r7, #4] 800fd8a: 681b ldr r3, [r3, #0] 800fd8c: 2210 movs r2, #16 800fd8e: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) 800fd90: 6a3b ldr r3, [r7, #32] 800fd92: f003 0320 and.w r3, r3, #32 800fd96: 2b00 cmp r3, #0 800fd98: d00b beq.n 800fdb2 { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) 800fd9a: 693b ldr r3, [r7, #16] 800fd9c: f003 0308 and.w r3, r3, #8 800fda0: 2b00 cmp r3, #0 800fda2: d006 beq.n 800fdb2 { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); 800fda4: 687b ldr r3, [r7, #4] 800fda6: 681b ldr r3, [r3, #0] 800fda8: 2208 movs r2, #8 800fdaa: 611a str r2, [r3, #16] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); 800fdac: 6878 ldr r0, [r7, #4] 800fdae: f000 f90a bl 800ffc6 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) 800fdb2: 6a3b ldr r3, [r7, #32] 800fdb4: f003 0310 and.w r3, r3, #16 800fdb8: 2b00 cmp r3, #0 800fdba: d009 beq.n 800fdd0 { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) 800fdbc: 687b ldr r3, [r7, #4] 800fdbe: 681b ldr r3, [r3, #0] 800fdc0: 691b ldr r3, [r3, #16] 800fdc2: f003 0303 and.w r3, r3, #3 800fdc6: 2b00 cmp r3, #0 800fdc8: d002 beq.n 800fdd0 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); 800fdca: 6878 ldr r0, [r7, #4] 800fdcc: f7fb f80e bl 800adec #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) 800fdd0: 6a3b ldr r3, [r7, #32] 800fdd2: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fdd6: 2b00 cmp r3, #0 800fdd8: d00b beq.n 800fdf2 { if ((msrflags & CAN_MSR_SLAKI) != 0U) 800fdda: 69fb ldr r3, [r7, #28] 800fddc: f003 0310 and.w r3, r3, #16 800fde0: 2b00 cmp r3, #0 800fde2: d006 beq.n 800fdf2 { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); 800fde4: 687b ldr r3, [r7, #4] 800fde6: 681b ldr r3, [r3, #0] 800fde8: 2210 movs r2, #16 800fdea: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->SleepCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); 800fdec: 6878 ldr r0, [r7, #4] 800fdee: f000 f8f3 bl 800ffd8 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ if ((interrupts & CAN_IT_WAKEUP) != 0U) 800fdf2: 6a3b ldr r3, [r7, #32] 800fdf4: f403 3380 and.w r3, r3, #65536 @ 0x10000 800fdf8: 2b00 cmp r3, #0 800fdfa: d00b beq.n 800fe14 { if ((msrflags & CAN_MSR_WKUI) != 0U) 800fdfc: 69fb ldr r3, [r7, #28] 800fdfe: f003 0308 and.w r3, r3, #8 800fe02: 2b00 cmp r3, #0 800fe04: d006 beq.n 800fe14 { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); 800fe06: 687b ldr r3, [r7, #4] 800fe08: 681b ldr r3, [r3, #0] 800fe0a: 2208 movs r2, #8 800fe0c: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->WakeUpFromRxMsgCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); 800fe0e: 6878 ldr r0, [r7, #4] 800fe10: f000 f8eb bl 800ffea #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ if ((interrupts & CAN_IT_ERROR) != 0U) 800fe14: 6a3b ldr r3, [r7, #32] 800fe16: f403 4300 and.w r3, r3, #32768 @ 0x8000 800fe1a: 2b00 cmp r3, #0 800fe1c: d07b beq.n 800ff16 { if ((msrflags & CAN_MSR_ERRI) != 0U) 800fe1e: 69fb ldr r3, [r7, #28] 800fe20: f003 0304 and.w r3, r3, #4 800fe24: 2b00 cmp r3, #0 800fe26: d072 beq.n 800ff0e { /* Check Error Warning Flag */ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800fe28: 6a3b ldr r3, [r7, #32] 800fe2a: f403 7380 and.w r3, r3, #256 @ 0x100 800fe2e: 2b00 cmp r3, #0 800fe30: d008 beq.n 800fe44 ((esrflags & CAN_ESR_EWGF) != 0U)) 800fe32: 68fb ldr r3, [r7, #12] 800fe34: f003 0301 and.w r3, r3, #1 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800fe38: 2b00 cmp r3, #0 800fe3a: d003 beq.n 800fe44 { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; 800fe3c: 6a7b ldr r3, [r7, #36] @ 0x24 800fe3e: f043 0301 orr.w r3, r3, #1 800fe42: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Warning Flag as read-only */ } /* Check Error Passive Flag */ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800fe44: 6a3b ldr r3, [r7, #32] 800fe46: f403 7300 and.w r3, r3, #512 @ 0x200 800fe4a: 2b00 cmp r3, #0 800fe4c: d008 beq.n 800fe60 ((esrflags & CAN_ESR_EPVF) != 0U)) 800fe4e: 68fb ldr r3, [r7, #12] 800fe50: f003 0302 and.w r3, r3, #2 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800fe54: 2b00 cmp r3, #0 800fe56: d003 beq.n 800fe60 { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; 800fe58: 6a7b ldr r3, [r7, #36] @ 0x24 800fe5a: f043 0302 orr.w r3, r3, #2 800fe5e: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-off Flag */ if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800fe60: 6a3b ldr r3, [r7, #32] 800fe62: f403 6380 and.w r3, r3, #1024 @ 0x400 800fe66: 2b00 cmp r3, #0 800fe68: d008 beq.n 800fe7c ((esrflags & CAN_ESR_BOFF) != 0U)) 800fe6a: 68fb ldr r3, [r7, #12] 800fe6c: f003 0304 and.w r3, r3, #4 if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800fe70: 2b00 cmp r3, #0 800fe72: d003 beq.n 800fe7c { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; 800fe74: 6a7b ldr r3, [r7, #36] @ 0x24 800fe76: f043 0304 orr.w r3, r3, #4 800fe7a: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Bus-Off as read-only */ } /* Check Last Error Code Flag */ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800fe7c: 6a3b ldr r3, [r7, #32] 800fe7e: f403 6300 and.w r3, r3, #2048 @ 0x800 800fe82: 2b00 cmp r3, #0 800fe84: d043 beq.n 800ff0e ((esrflags & CAN_ESR_LEC) != 0U)) 800fe86: 68fb ldr r3, [r7, #12] 800fe88: f003 0370 and.w r3, r3, #112 @ 0x70 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800fe8c: 2b00 cmp r3, #0 800fe8e: d03e beq.n 800ff0e { switch (esrflags & CAN_ESR_LEC) 800fe90: 68fb ldr r3, [r7, #12] 800fe92: f003 0370 and.w r3, r3, #112 @ 0x70 800fe96: 2b60 cmp r3, #96 @ 0x60 800fe98: d02b beq.n 800fef2 800fe9a: 2b60 cmp r3, #96 @ 0x60 800fe9c: d82e bhi.n 800fefc 800fe9e: 2b50 cmp r3, #80 @ 0x50 800fea0: d022 beq.n 800fee8 800fea2: 2b50 cmp r3, #80 @ 0x50 800fea4: d82a bhi.n 800fefc 800fea6: 2b40 cmp r3, #64 @ 0x40 800fea8: d019 beq.n 800fede 800feaa: 2b40 cmp r3, #64 @ 0x40 800feac: d826 bhi.n 800fefc 800feae: 2b30 cmp r3, #48 @ 0x30 800feb0: d010 beq.n 800fed4 800feb2: 2b30 cmp r3, #48 @ 0x30 800feb4: d822 bhi.n 800fefc 800feb6: 2b10 cmp r3, #16 800feb8: d002 beq.n 800fec0 800feba: 2b20 cmp r3, #32 800febc: d005 beq.n 800feca case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): /* Set CAN error code to CRC error */ errorcode |= HAL_CAN_ERROR_CRC; break; default: break; 800febe: e01d b.n 800fefc errorcode |= HAL_CAN_ERROR_STF; 800fec0: 6a7b ldr r3, [r7, #36] @ 0x24 800fec2: f043 0308 orr.w r3, r3, #8 800fec6: 627b str r3, [r7, #36] @ 0x24 break; 800fec8: e019 b.n 800fefe errorcode |= HAL_CAN_ERROR_FOR; 800feca: 6a7b ldr r3, [r7, #36] @ 0x24 800fecc: f043 0310 orr.w r3, r3, #16 800fed0: 627b str r3, [r7, #36] @ 0x24 break; 800fed2: e014 b.n 800fefe errorcode |= HAL_CAN_ERROR_ACK; 800fed4: 6a7b ldr r3, [r7, #36] @ 0x24 800fed6: f043 0320 orr.w r3, r3, #32 800feda: 627b str r3, [r7, #36] @ 0x24 break; 800fedc: e00f b.n 800fefe errorcode |= HAL_CAN_ERROR_BR; 800fede: 6a7b ldr r3, [r7, #36] @ 0x24 800fee0: f043 0340 orr.w r3, r3, #64 @ 0x40 800fee4: 627b str r3, [r7, #36] @ 0x24 break; 800fee6: e00a b.n 800fefe errorcode |= HAL_CAN_ERROR_BD; 800fee8: 6a7b ldr r3, [r7, #36] @ 0x24 800feea: f043 0380 orr.w r3, r3, #128 @ 0x80 800feee: 627b str r3, [r7, #36] @ 0x24 break; 800fef0: e005 b.n 800fefe errorcode |= HAL_CAN_ERROR_CRC; 800fef2: 6a7b ldr r3, [r7, #36] @ 0x24 800fef4: f443 7380 orr.w r3, r3, #256 @ 0x100 800fef8: 627b str r3, [r7, #36] @ 0x24 break; 800fefa: e000 b.n 800fefe break; 800fefc: bf00 nop } /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); 800fefe: 687b ldr r3, [r7, #4] 800ff00: 681b ldr r3, [r3, #0] 800ff02: 699a ldr r2, [r3, #24] 800ff04: 687b ldr r3, [r7, #4] 800ff06: 681b ldr r3, [r3, #0] 800ff08: f022 0270 bic.w r2, r2, #112 @ 0x70 800ff0c: 619a str r2, [r3, #24] } } /* Clear ERRI Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); 800ff0e: 687b ldr r3, [r7, #4] 800ff10: 681b ldr r3, [r3, #0] 800ff12: 2204 movs r2, #4 800ff14: 605a str r2, [r3, #4] } /* Call the Error call Back in case of Errors */ if (errorcode != HAL_CAN_ERROR_NONE) 800ff16: 6a7b ldr r3, [r7, #36] @ 0x24 800ff18: 2b00 cmp r3, #0 800ff1a: d008 beq.n 800ff2e { /* Update error code in handle */ hcan->ErrorCode |= errorcode; 800ff1c: 687b ldr r3, [r7, #4] 800ff1e: 6a5a ldr r2, [r3, #36] @ 0x24 800ff20: 6a7b ldr r3, [r7, #36] @ 0x24 800ff22: 431a orrs r2, r3 800ff24: 687b ldr r3, [r7, #4] 800ff26: 625a str r2, [r3, #36] @ 0x24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->ErrorCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); 800ff28: 6878 ldr r0, [r7, #4] 800ff2a: f000 f867 bl 800fffc #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } 800ff2e: bf00 nop 800ff30: 3728 adds r7, #40 @ 0x28 800ff32: 46bd mov sp, r7 800ff34: bd80 pop {r7, pc} 0800ff36 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { 800ff36: b480 push {r7} 800ff38: b083 sub sp, #12 800ff3a: af00 add r7, sp, #0 800ff3c: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the user file */ } 800ff3e: bf00 nop 800ff40: 370c adds r7, #12 800ff42: 46bd mov sp, r7 800ff44: bc80 pop {r7} 800ff46: 4770 bx lr 0800ff48 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { 800ff48: b480 push {r7} 800ff4a: b083 sub sp, #12 800ff4c: af00 add r7, sp, #0 800ff4e: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the user file */ } 800ff50: bf00 nop 800ff52: 370c adds r7, #12 800ff54: 46bd mov sp, r7 800ff56: bc80 pop {r7} 800ff58: 4770 bx lr 0800ff5a : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) { 800ff5a: b480 push {r7} 800ff5c: b083 sub sp, #12 800ff5e: af00 add r7, sp, #0 800ff60: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the user file */ } 800ff62: bf00 nop 800ff64: 370c adds r7, #12 800ff66: 46bd mov sp, r7 800ff68: bc80 pop {r7} 800ff6a: 4770 bx lr 0800ff6c : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { 800ff6c: b480 push {r7} 800ff6e: b083 sub sp, #12 800ff70: af00 add r7, sp, #0 800ff72: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } 800ff74: bf00 nop 800ff76: 370c adds r7, #12 800ff78: 46bd mov sp, r7 800ff7a: bc80 pop {r7} 800ff7c: 4770 bx lr 0800ff7e : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { 800ff7e: b480 push {r7} 800ff80: b083 sub sp, #12 800ff82: af00 add r7, sp, #0 800ff84: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } 800ff86: bf00 nop 800ff88: 370c adds r7, #12 800ff8a: 46bd mov sp, r7 800ff8c: bc80 pop {r7} 800ff8e: 4770 bx lr 0800ff90 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { 800ff90: b480 push {r7} 800ff92: b083 sub sp, #12 800ff94: af00 add r7, sp, #0 800ff96: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } 800ff98: bf00 nop 800ff9a: 370c adds r7, #12 800ff9c: 46bd mov sp, r7 800ff9e: bc80 pop {r7} 800ffa0: 4770 bx lr 0800ffa2 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { 800ffa2: b480 push {r7} 800ffa4: b083 sub sp, #12 800ffa6: af00 add r7, sp, #0 800ffa8: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the user file */ } 800ffaa: bf00 nop 800ffac: 370c adds r7, #12 800ffae: 46bd mov sp, r7 800ffb0: bc80 pop {r7} 800ffb2: 4770 bx lr 0800ffb4 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { 800ffb4: b480 push {r7} 800ffb6: b083 sub sp, #12 800ffb8: af00 add r7, sp, #0 800ffba: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } 800ffbc: bf00 nop 800ffbe: 370c adds r7, #12 800ffc0: 46bd mov sp, r7 800ffc2: bc80 pop {r7} 800ffc4: 4770 bx lr 0800ffc6 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { 800ffc6: b480 push {r7} 800ffc8: b083 sub sp, #12 800ffca: af00 add r7, sp, #0 800ffcc: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } 800ffce: bf00 nop 800ffd0: 370c adds r7, #12 800ffd2: 46bd mov sp, r7 800ffd4: bc80 pop {r7} 800ffd6: 4770 bx lr 0800ffd8 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { 800ffd8: b480 push {r7} 800ffda: b083 sub sp, #12 800ffdc: af00 add r7, sp, #0 800ffde: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } 800ffe0: bf00 nop 800ffe2: 370c adds r7, #12 800ffe4: 46bd mov sp, r7 800ffe6: bc80 pop {r7} 800ffe8: 4770 bx lr 0800ffea : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { 800ffea: b480 push {r7} 800ffec: b083 sub sp, #12 800ffee: af00 add r7, sp, #0 800fff0: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } 800fff2: bf00 nop 800fff4: 370c adds r7, #12 800fff6: 46bd mov sp, r7 800fff8: bc80 pop {r7} 800fffa: 4770 bx lr 0800fffc : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { 800fffc: b480 push {r7} 800fffe: b083 sub sp, #12 8010000: af00 add r7, sp, #0 8010002: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } 8010004: bf00 nop 8010006: 370c adds r7, #12 8010008: 46bd mov sp, r7 801000a: bc80 pop {r7} 801000c: 4770 bx lr ... 08010010 <__NVIC_SetPriorityGrouping>: { 8010010: b480 push {r7} 8010012: b085 sub sp, #20 8010014: af00 add r7, sp, #0 8010016: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8010018: 687b ldr r3, [r7, #4] 801001a: f003 0307 and.w r3, r3, #7 801001e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8010020: 4b0c ldr r3, [pc, #48] @ (8010054 <__NVIC_SetPriorityGrouping+0x44>) 8010022: 68db ldr r3, [r3, #12] 8010024: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8010026: 68ba ldr r2, [r7, #8] 8010028: f64f 03ff movw r3, #63743 @ 0xf8ff 801002c: 4013 ands r3, r2 801002e: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8010030: 68fb ldr r3, [r7, #12] 8010032: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8010034: 68bb ldr r3, [r7, #8] 8010036: 4313 orrs r3, r2 reg_value = (reg_value | 8010038: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 801003c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8010040: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8010042: 4a04 ldr r2, [pc, #16] @ (8010054 <__NVIC_SetPriorityGrouping+0x44>) 8010044: 68bb ldr r3, [r7, #8] 8010046: 60d3 str r3, [r2, #12] } 8010048: bf00 nop 801004a: 3714 adds r7, #20 801004c: 46bd mov sp, r7 801004e: bc80 pop {r7} 8010050: 4770 bx lr 8010052: bf00 nop 8010054: e000ed00 .word 0xe000ed00 08010058 <__NVIC_GetPriorityGrouping>: { 8010058: b480 push {r7} 801005a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 801005c: 4b04 ldr r3, [pc, #16] @ (8010070 <__NVIC_GetPriorityGrouping+0x18>) 801005e: 68db ldr r3, [r3, #12] 8010060: 0a1b lsrs r3, r3, #8 8010062: f003 0307 and.w r3, r3, #7 } 8010066: 4618 mov r0, r3 8010068: 46bd mov sp, r7 801006a: bc80 pop {r7} 801006c: 4770 bx lr 801006e: bf00 nop 8010070: e000ed00 .word 0xe000ed00 08010074 <__NVIC_EnableIRQ>: { 8010074: b480 push {r7} 8010076: b083 sub sp, #12 8010078: af00 add r7, sp, #0 801007a: 4603 mov r3, r0 801007c: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 801007e: f997 3007 ldrsb.w r3, [r7, #7] 8010082: 2b00 cmp r3, #0 8010084: db0b blt.n 801009e <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8010086: 79fb ldrb r3, [r7, #7] 8010088: f003 021f and.w r2, r3, #31 801008c: 4906 ldr r1, [pc, #24] @ (80100a8 <__NVIC_EnableIRQ+0x34>) 801008e: f997 3007 ldrsb.w r3, [r7, #7] 8010092: 095b lsrs r3, r3, #5 8010094: 2001 movs r0, #1 8010096: fa00 f202 lsl.w r2, r0, r2 801009a: f841 2023 str.w r2, [r1, r3, lsl #2] } 801009e: bf00 nop 80100a0: 370c adds r7, #12 80100a2: 46bd mov sp, r7 80100a4: bc80 pop {r7} 80100a6: 4770 bx lr 80100a8: e000e100 .word 0xe000e100 080100ac <__NVIC_SetPriority>: { 80100ac: b480 push {r7} 80100ae: b083 sub sp, #12 80100b0: af00 add r7, sp, #0 80100b2: 4603 mov r3, r0 80100b4: 6039 str r1, [r7, #0] 80100b6: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80100b8: f997 3007 ldrsb.w r3, [r7, #7] 80100bc: 2b00 cmp r3, #0 80100be: db0a blt.n 80100d6 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80100c0: 683b ldr r3, [r7, #0] 80100c2: b2da uxtb r2, r3 80100c4: 490c ldr r1, [pc, #48] @ (80100f8 <__NVIC_SetPriority+0x4c>) 80100c6: f997 3007 ldrsb.w r3, [r7, #7] 80100ca: 0112 lsls r2, r2, #4 80100cc: b2d2 uxtb r2, r2 80100ce: 440b add r3, r1 80100d0: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 80100d4: e00a b.n 80100ec <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80100d6: 683b ldr r3, [r7, #0] 80100d8: b2da uxtb r2, r3 80100da: 4908 ldr r1, [pc, #32] @ (80100fc <__NVIC_SetPriority+0x50>) 80100dc: 79fb ldrb r3, [r7, #7] 80100de: f003 030f and.w r3, r3, #15 80100e2: 3b04 subs r3, #4 80100e4: 0112 lsls r2, r2, #4 80100e6: b2d2 uxtb r2, r2 80100e8: 440b add r3, r1 80100ea: 761a strb r2, [r3, #24] } 80100ec: bf00 nop 80100ee: 370c adds r7, #12 80100f0: 46bd mov sp, r7 80100f2: bc80 pop {r7} 80100f4: 4770 bx lr 80100f6: bf00 nop 80100f8: e000e100 .word 0xe000e100 80100fc: e000ed00 .word 0xe000ed00 08010100 : { 8010100: b480 push {r7} 8010102: b089 sub sp, #36 @ 0x24 8010104: af00 add r7, sp, #0 8010106: 60f8 str r0, [r7, #12] 8010108: 60b9 str r1, [r7, #8] 801010a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 801010c: 68fb ldr r3, [r7, #12] 801010e: f003 0307 and.w r3, r3, #7 8010112: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8010114: 69fb ldr r3, [r7, #28] 8010116: f1c3 0307 rsb r3, r3, #7 801011a: 2b04 cmp r3, #4 801011c: bf28 it cs 801011e: 2304 movcs r3, #4 8010120: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8010122: 69fb ldr r3, [r7, #28] 8010124: 3304 adds r3, #4 8010126: 2b06 cmp r3, #6 8010128: d902 bls.n 8010130 801012a: 69fb ldr r3, [r7, #28] 801012c: 3b03 subs r3, #3 801012e: e000 b.n 8010132 8010130: 2300 movs r3, #0 8010132: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8010134: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8010138: 69bb ldr r3, [r7, #24] 801013a: fa02 f303 lsl.w r3, r2, r3 801013e: 43da mvns r2, r3 8010140: 68bb ldr r3, [r7, #8] 8010142: 401a ands r2, r3 8010144: 697b ldr r3, [r7, #20] 8010146: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8010148: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 801014c: 697b ldr r3, [r7, #20] 801014e: fa01 f303 lsl.w r3, r1, r3 8010152: 43d9 mvns r1, r3 8010154: 687b ldr r3, [r7, #4] 8010156: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8010158: 4313 orrs r3, r2 } 801015a: 4618 mov r0, r3 801015c: 3724 adds r7, #36 @ 0x24 801015e: 46bd mov sp, r7 8010160: bc80 pop {r7} 8010162: 4770 bx lr 08010164 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8010164: b580 push {r7, lr} 8010166: b082 sub sp, #8 8010168: af00 add r7, sp, #0 801016a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 801016c: 687b ldr r3, [r7, #4] 801016e: 3b01 subs r3, #1 8010170: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8010174: d301 bcc.n 801017a { return (1UL); /* Reload value impossible */ 8010176: 2301 movs r3, #1 8010178: e00f b.n 801019a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 801017a: 4a0a ldr r2, [pc, #40] @ (80101a4 ) 801017c: 687b ldr r3, [r7, #4] 801017e: 3b01 subs r3, #1 8010180: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8010182: 210f movs r1, #15 8010184: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8010188: f7ff ff90 bl 80100ac <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 801018c: 4b05 ldr r3, [pc, #20] @ (80101a4 ) 801018e: 2200 movs r2, #0 8010190: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8010192: 4b04 ldr r3, [pc, #16] @ (80101a4 ) 8010194: 2207 movs r2, #7 8010196: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8010198: 2300 movs r3, #0 } 801019a: 4618 mov r0, r3 801019c: 3708 adds r7, #8 801019e: 46bd mov sp, r7 80101a0: bd80 pop {r7, pc} 80101a2: bf00 nop 80101a4: e000e010 .word 0xe000e010 080101a8 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80101a8: b580 push {r7, lr} 80101aa: b082 sub sp, #8 80101ac: af00 add r7, sp, #0 80101ae: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80101b0: 6878 ldr r0, [r7, #4] 80101b2: f7ff ff2d bl 8010010 <__NVIC_SetPriorityGrouping> } 80101b6: bf00 nop 80101b8: 3708 adds r7, #8 80101ba: 46bd mov sp, r7 80101bc: bd80 pop {r7, pc} 080101be : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80101be: b580 push {r7, lr} 80101c0: b086 sub sp, #24 80101c2: af00 add r7, sp, #0 80101c4: 4603 mov r3, r0 80101c6: 60b9 str r1, [r7, #8] 80101c8: 607a str r2, [r7, #4] 80101ca: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 80101cc: 2300 movs r3, #0 80101ce: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 80101d0: f7ff ff42 bl 8010058 <__NVIC_GetPriorityGrouping> 80101d4: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80101d6: 687a ldr r2, [r7, #4] 80101d8: 68b9 ldr r1, [r7, #8] 80101da: 6978 ldr r0, [r7, #20] 80101dc: f7ff ff90 bl 8010100 80101e0: 4602 mov r2, r0 80101e2: f997 300f ldrsb.w r3, [r7, #15] 80101e6: 4611 mov r1, r2 80101e8: 4618 mov r0, r3 80101ea: f7ff ff5f bl 80100ac <__NVIC_SetPriority> } 80101ee: bf00 nop 80101f0: 3718 adds r7, #24 80101f2: 46bd mov sp, r7 80101f4: bd80 pop {r7, pc} 080101f6 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80101f6: b580 push {r7, lr} 80101f8: b082 sub sp, #8 80101fa: af00 add r7, sp, #0 80101fc: 4603 mov r3, r0 80101fe: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8010200: f997 3007 ldrsb.w r3, [r7, #7] 8010204: 4618 mov r0, r3 8010206: f7ff ff35 bl 8010074 <__NVIC_EnableIRQ> } 801020a: bf00 nop 801020c: 3708 adds r7, #8 801020e: 46bd mov sp, r7 8010210: bd80 pop {r7, pc} 08010212 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8010212: b580 push {r7, lr} 8010214: b082 sub sp, #8 8010216: af00 add r7, sp, #0 8010218: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 801021a: 6878 ldr r0, [r7, #4] 801021c: f7ff ffa2 bl 8010164 8010220: 4603 mov r3, r0 } 8010222: 4618 mov r0, r3 8010224: 3708 adds r7, #8 8010226: 46bd mov sp, r7 8010228: bd80 pop {r7, pc} 0801022a : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 801022a: b580 push {r7, lr} 801022c: b082 sub sp, #8 801022e: af00 add r7, sp, #0 8010230: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 8010232: 687b ldr r3, [r7, #4] 8010234: 2b00 cmp r3, #0 8010236: d101 bne.n 801023c { return HAL_ERROR; 8010238: 2301 movs r3, #1 801023a: e00e b.n 801025a } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 801023c: 687b ldr r3, [r7, #4] 801023e: 795b ldrb r3, [r3, #5] 8010240: b2db uxtb r3, r3 8010242: 2b00 cmp r3, #0 8010244: d105 bne.n 8010252 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 8010246: 687b ldr r3, [r7, #4] 8010248: 2200 movs r2, #0 801024a: 711a strb r2, [r3, #4] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 801024c: 6878 ldr r0, [r7, #4] 801024e: f7fa f887 bl 800a360 } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 8010252: 687b ldr r3, [r7, #4] 8010254: 2201 movs r2, #1 8010256: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 8010258: 2300 movs r3, #0 } 801025a: 4618 mov r0, r3 801025c: 3708 adds r7, #8 801025e: 46bd mov sp, r7 8010260: bd80 pop {r7, pc} ... 08010264 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8010264: b480 push {r7} 8010266: b085 sub sp, #20 8010268: af00 add r7, sp, #0 801026a: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 801026c: 2300 movs r3, #0 801026e: 60fb str r3, [r7, #12] /* Check the DMA handle allocation */ if(hdma == NULL) 8010270: 687b ldr r3, [r7, #4] 8010272: 2b00 cmp r3, #0 8010274: d101 bne.n 801027a { return HAL_ERROR; 8010276: 2301 movs r3, #1 8010278: e059 b.n 801032e assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); #if defined (DMA2) /* calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 801027a: 687b ldr r3, [r7, #4] 801027c: 681b ldr r3, [r3, #0] 801027e: 461a mov r2, r3 8010280: 4b2d ldr r3, [pc, #180] @ (8010338 ) 8010282: 429a cmp r2, r3 8010284: d80f bhi.n 80102a6 { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 8010286: 687b ldr r3, [r7, #4] 8010288: 681b ldr r3, [r3, #0] 801028a: 461a mov r2, r3 801028c: 4b2b ldr r3, [pc, #172] @ (801033c ) 801028e: 4413 add r3, r2 8010290: 4a2b ldr r2, [pc, #172] @ (8010340 ) 8010292: fba2 2303 umull r2, r3, r2, r3 8010296: 091b lsrs r3, r3, #4 8010298: 009a lsls r2, r3, #2 801029a: 687b ldr r3, [r7, #4] 801029c: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA1; 801029e: 687b ldr r3, [r7, #4] 80102a0: 4a28 ldr r2, [pc, #160] @ (8010344 ) 80102a2: 63da str r2, [r3, #60] @ 0x3c 80102a4: e00e b.n 80102c4 } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; 80102a6: 687b ldr r3, [r7, #4] 80102a8: 681b ldr r3, [r3, #0] 80102aa: 461a mov r2, r3 80102ac: 4b26 ldr r3, [pc, #152] @ (8010348 ) 80102ae: 4413 add r3, r2 80102b0: 4a23 ldr r2, [pc, #140] @ (8010340 ) 80102b2: fba2 2303 umull r2, r3, r2, r3 80102b6: 091b lsrs r3, r3, #4 80102b8: 009a lsls r2, r3, #2 80102ba: 687b ldr r3, [r7, #4] 80102bc: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA2; 80102be: 687b ldr r3, [r7, #4] 80102c0: 4a22 ldr r2, [pc, #136] @ (801034c ) 80102c2: 63da str r2, [r3, #60] @ 0x3c hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; #endif /* DMA2 */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80102c4: 687b ldr r3, [r7, #4] 80102c6: 2202 movs r2, #2 80102c8: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Get the CR register value */ tmp = hdma->Instance->CCR; 80102cc: 687b ldr r3, [r7, #4] 80102ce: 681b ldr r3, [r3, #0] 80102d0: 681b ldr r3, [r3, #0] 80102d2: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 80102d4: 68fb ldr r3, [r7, #12] 80102d6: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 80102da: f023 0330 bic.w r3, r3, #48 @ 0x30 80102de: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 80102e0: 687b ldr r3, [r7, #4] 80102e2: 685a ldr r2, [r3, #4] hdma->Init.PeriphInc | hdma->Init.MemInc | 80102e4: 687b ldr r3, [r7, #4] 80102e6: 689b ldr r3, [r3, #8] tmp |= hdma->Init.Direction | 80102e8: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 80102ea: 687b ldr r3, [r7, #4] 80102ec: 68db ldr r3, [r3, #12] 80102ee: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80102f0: 687b ldr r3, [r7, #4] 80102f2: 691b ldr r3, [r3, #16] hdma->Init.PeriphInc | hdma->Init.MemInc | 80102f4: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80102f6: 687b ldr r3, [r7, #4] 80102f8: 695b ldr r3, [r3, #20] 80102fa: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 80102fc: 687b ldr r3, [r7, #4] 80102fe: 699b ldr r3, [r3, #24] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8010300: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8010302: 687b ldr r3, [r7, #4] 8010304: 69db ldr r3, [r3, #28] 8010306: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | 8010308: 68fa ldr r2, [r7, #12] 801030a: 4313 orrs r3, r2 801030c: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; 801030e: 687b ldr r3, [r7, #4] 8010310: 681b ldr r3, [r3, #0] 8010312: 68fa ldr r2, [r7, #12] 8010314: 601a str r2, [r3, #0] /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8010316: 687b ldr r3, [r7, #4] 8010318: 2200 movs r2, #0 801031a: 639a str r2, [r3, #56] @ 0x38 /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 801031c: 687b ldr r3, [r7, #4] 801031e: 2201 movs r2, #1 8010320: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; 8010324: 687b ldr r3, [r7, #4] 8010326: 2200 movs r2, #0 8010328: f883 2020 strb.w r2, [r3, #32] return HAL_OK; 801032c: 2300 movs r3, #0 } 801032e: 4618 mov r0, r3 8010330: 3714 adds r7, #20 8010332: 46bd mov sp, r7 8010334: bc80 pop {r7} 8010336: 4770 bx lr 8010338: 40020407 .word 0x40020407 801033c: bffdfff8 .word 0xbffdfff8 8010340: cccccccd .word 0xcccccccd 8010344: 40020000 .word 0x40020000 8010348: bffdfbf8 .word 0xbffdfbf8 801034c: 40020400 .word 0x40020400 08010350 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8010350: b580 push {r7, lr} 8010352: b086 sub sp, #24 8010354: af00 add r7, sp, #0 8010356: 60f8 str r0, [r7, #12] 8010358: 60b9 str r1, [r7, #8] 801035a: 607a str r2, [r7, #4] 801035c: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 801035e: 2300 movs r3, #0 8010360: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8010362: 68fb ldr r3, [r7, #12] 8010364: f893 3020 ldrb.w r3, [r3, #32] 8010368: 2b01 cmp r3, #1 801036a: d101 bne.n 8010370 801036c: 2302 movs r3, #2 801036e: e04b b.n 8010408 8010370: 68fb ldr r3, [r7, #12] 8010372: 2201 movs r2, #1 8010374: f883 2020 strb.w r2, [r3, #32] if(HAL_DMA_STATE_READY == hdma->State) 8010378: 68fb ldr r3, [r7, #12] 801037a: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 801037e: b2db uxtb r3, r3 8010380: 2b01 cmp r3, #1 8010382: d13a bne.n 80103fa { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8010384: 68fb ldr r3, [r7, #12] 8010386: 2202 movs r2, #2 8010388: f883 2021 strb.w r2, [r3, #33] @ 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 801038c: 68fb ldr r3, [r7, #12] 801038e: 2200 movs r2, #0 8010390: 639a str r2, [r3, #56] @ 0x38 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8010392: 68fb ldr r3, [r7, #12] 8010394: 681b ldr r3, [r3, #0] 8010396: 681a ldr r2, [r3, #0] 8010398: 68fb ldr r3, [r7, #12] 801039a: 681b ldr r3, [r3, #0] 801039c: f022 0201 bic.w r2, r2, #1 80103a0: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 80103a2: 683b ldr r3, [r7, #0] 80103a4: 687a ldr r2, [r7, #4] 80103a6: 68b9 ldr r1, [r7, #8] 80103a8: 68f8 ldr r0, [r7, #12] 80103aa: f000 fbbc bl 8010b26 /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if(NULL != hdma->XferHalfCpltCallback) 80103ae: 68fb ldr r3, [r7, #12] 80103b0: 6adb ldr r3, [r3, #44] @ 0x2c 80103b2: 2b00 cmp r3, #0 80103b4: d008 beq.n 80103c8 { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80103b6: 68fb ldr r3, [r7, #12] 80103b8: 681b ldr r3, [r3, #0] 80103ba: 681a ldr r2, [r3, #0] 80103bc: 68fb ldr r3, [r7, #12] 80103be: 681b ldr r3, [r3, #0] 80103c0: f042 020e orr.w r2, r2, #14 80103c4: 601a str r2, [r3, #0] 80103c6: e00f b.n 80103e8 } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 80103c8: 68fb ldr r3, [r7, #12] 80103ca: 681b ldr r3, [r3, #0] 80103cc: 681a ldr r2, [r3, #0] 80103ce: 68fb ldr r3, [r7, #12] 80103d0: 681b ldr r3, [r3, #0] 80103d2: f022 0204 bic.w r2, r2, #4 80103d6: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 80103d8: 68fb ldr r3, [r7, #12] 80103da: 681b ldr r3, [r3, #0] 80103dc: 681a ldr r2, [r3, #0] 80103de: 68fb ldr r3, [r7, #12] 80103e0: 681b ldr r3, [r3, #0] 80103e2: f042 020a orr.w r2, r2, #10 80103e6: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 80103e8: 68fb ldr r3, [r7, #12] 80103ea: 681b ldr r3, [r3, #0] 80103ec: 681a ldr r2, [r3, #0] 80103ee: 68fb ldr r3, [r7, #12] 80103f0: 681b ldr r3, [r3, #0] 80103f2: f042 0201 orr.w r2, r2, #1 80103f6: 601a str r2, [r3, #0] 80103f8: e005 b.n 8010406 } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); 80103fa: 68fb ldr r3, [r7, #12] 80103fc: 2200 movs r2, #0 80103fe: f883 2020 strb.w r2, [r3, #32] /* Remain BUSY */ status = HAL_BUSY; 8010402: 2302 movs r3, #2 8010404: 75fb strb r3, [r7, #23] } return status; 8010406: 7dfb ldrb r3, [r7, #23] } 8010408: 4618 mov r0, r3 801040a: 3718 adds r7, #24 801040c: 46bd mov sp, r7 801040e: bd80 pop {r7, pc} 08010410 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8010410: b480 push {r7} 8010412: b085 sub sp, #20 8010414: af00 add r7, sp, #0 8010416: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8010418: 2300 movs r3, #0 801041a: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 801041c: 687b ldr r3, [r7, #4] 801041e: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 8010422: b2db uxtb r3, r3 8010424: 2b02 cmp r3, #2 8010426: d008 beq.n 801043a { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8010428: 687b ldr r3, [r7, #4] 801042a: 2204 movs r2, #4 801042c: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 801042e: 687b ldr r3, [r7, #4] 8010430: 2200 movs r2, #0 8010432: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8010436: 2301 movs r3, #1 8010438: e020 b.n 801047c } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 801043a: 687b ldr r3, [r7, #4] 801043c: 681b ldr r3, [r3, #0] 801043e: 681a ldr r2, [r3, #0] 8010440: 687b ldr r3, [r7, #4] 8010442: 681b ldr r3, [r3, #0] 8010444: f022 020e bic.w r2, r2, #14 8010448: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 801044a: 687b ldr r3, [r7, #4] 801044c: 681b ldr r3, [r3, #0] 801044e: 681a ldr r2, [r3, #0] 8010450: 687b ldr r3, [r7, #4] 8010452: 681b ldr r3, [r3, #0] 8010454: f022 0201 bic.w r2, r2, #1 8010458: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 801045a: 687b ldr r3, [r7, #4] 801045c: 6c1a ldr r2, [r3, #64] @ 0x40 801045e: 687b ldr r3, [r7, #4] 8010460: 6bdb ldr r3, [r3, #60] @ 0x3c 8010462: 2101 movs r1, #1 8010464: fa01 f202 lsl.w r2, r1, r2 8010468: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 801046a: 687b ldr r3, [r7, #4] 801046c: 2201 movs r2, #1 801046e: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8010472: 687b ldr r3, [r7, #4] 8010474: 2200 movs r2, #0 8010476: f883 2020 strb.w r2, [r3, #32] return status; 801047a: 7bfb ldrb r3, [r7, #15] } 801047c: 4618 mov r0, r3 801047e: 3714 adds r7, #20 8010480: 46bd mov sp, r7 8010482: bc80 pop {r7} 8010484: 4770 bx lr ... 08010488 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8010488: b580 push {r7, lr} 801048a: b084 sub sp, #16 801048c: af00 add r7, sp, #0 801048e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8010490: 2300 movs r3, #0 8010492: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 8010494: 687b ldr r3, [r7, #4] 8010496: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 801049a: b2db uxtb r3, r3 801049c: 2b02 cmp r3, #2 801049e: d005 beq.n 80104ac { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80104a0: 687b ldr r3, [r7, #4] 80104a2: 2204 movs r2, #4 80104a4: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 80104a6: 2301 movs r3, #1 80104a8: 73fb strb r3, [r7, #15] 80104aa: e0d6 b.n 801065a } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80104ac: 687b ldr r3, [r7, #4] 80104ae: 681b ldr r3, [r3, #0] 80104b0: 681a ldr r2, [r3, #0] 80104b2: 687b ldr r3, [r7, #4] 80104b4: 681b ldr r3, [r3, #0] 80104b6: f022 020e bic.w r2, r2, #14 80104ba: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 80104bc: 687b ldr r3, [r7, #4] 80104be: 681b ldr r3, [r3, #0] 80104c0: 681a ldr r2, [r3, #0] 80104c2: 687b ldr r3, [r7, #4] 80104c4: 681b ldr r3, [r3, #0] 80104c6: f022 0201 bic.w r2, r2, #1 80104ca: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 80104cc: 687b ldr r3, [r7, #4] 80104ce: 681b ldr r3, [r3, #0] 80104d0: 461a mov r2, r3 80104d2: 4b64 ldr r3, [pc, #400] @ (8010664 ) 80104d4: 429a cmp r2, r3 80104d6: d958 bls.n 801058a 80104d8: 687b ldr r3, [r7, #4] 80104da: 681b ldr r3, [r3, #0] 80104dc: 4a62 ldr r2, [pc, #392] @ (8010668 ) 80104de: 4293 cmp r3, r2 80104e0: d04f beq.n 8010582 80104e2: 687b ldr r3, [r7, #4] 80104e4: 681b ldr r3, [r3, #0] 80104e6: 4a61 ldr r2, [pc, #388] @ (801066c ) 80104e8: 4293 cmp r3, r2 80104ea: d048 beq.n 801057e 80104ec: 687b ldr r3, [r7, #4] 80104ee: 681b ldr r3, [r3, #0] 80104f0: 4a5f ldr r2, [pc, #380] @ (8010670 ) 80104f2: 4293 cmp r3, r2 80104f4: d040 beq.n 8010578 80104f6: 687b ldr r3, [r7, #4] 80104f8: 681b ldr r3, [r3, #0] 80104fa: 4a5e ldr r2, [pc, #376] @ (8010674 ) 80104fc: 4293 cmp r3, r2 80104fe: d038 beq.n 8010572 8010500: 687b ldr r3, [r7, #4] 8010502: 681b ldr r3, [r3, #0] 8010504: 4a5c ldr r2, [pc, #368] @ (8010678 ) 8010506: 4293 cmp r3, r2 8010508: d030 beq.n 801056c 801050a: 687b ldr r3, [r7, #4] 801050c: 681b ldr r3, [r3, #0] 801050e: 4a5b ldr r2, [pc, #364] @ (801067c ) 8010510: 4293 cmp r3, r2 8010512: d028 beq.n 8010566 8010514: 687b ldr r3, [r7, #4] 8010516: 681b ldr r3, [r3, #0] 8010518: 4a52 ldr r2, [pc, #328] @ (8010664 ) 801051a: 4293 cmp r3, r2 801051c: d020 beq.n 8010560 801051e: 687b ldr r3, [r7, #4] 8010520: 681b ldr r3, [r3, #0] 8010522: 4a57 ldr r2, [pc, #348] @ (8010680 ) 8010524: 4293 cmp r3, r2 8010526: d019 beq.n 801055c 8010528: 687b ldr r3, [r7, #4] 801052a: 681b ldr r3, [r3, #0] 801052c: 4a55 ldr r2, [pc, #340] @ (8010684 ) 801052e: 4293 cmp r3, r2 8010530: d012 beq.n 8010558 8010532: 687b ldr r3, [r7, #4] 8010534: 681b ldr r3, [r3, #0] 8010536: 4a54 ldr r2, [pc, #336] @ (8010688 ) 8010538: 4293 cmp r3, r2 801053a: d00a beq.n 8010552 801053c: 687b ldr r3, [r7, #4] 801053e: 681b ldr r3, [r3, #0] 8010540: 4a52 ldr r2, [pc, #328] @ (801068c ) 8010542: 4293 cmp r3, r2 8010544: d102 bne.n 801054c 8010546: f44f 5380 mov.w r3, #4096 @ 0x1000 801054a: e01b b.n 8010584 801054c: f44f 3380 mov.w r3, #65536 @ 0x10000 8010550: e018 b.n 8010584 8010552: f44f 7380 mov.w r3, #256 @ 0x100 8010556: e015 b.n 8010584 8010558: 2310 movs r3, #16 801055a: e013 b.n 8010584 801055c: 2301 movs r3, #1 801055e: e011 b.n 8010584 8010560: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8010564: e00e b.n 8010584 8010566: f44f 1380 mov.w r3, #1048576 @ 0x100000 801056a: e00b b.n 8010584 801056c: f44f 3380 mov.w r3, #65536 @ 0x10000 8010570: e008 b.n 8010584 8010572: f44f 5380 mov.w r3, #4096 @ 0x1000 8010576: e005 b.n 8010584 8010578: f44f 7380 mov.w r3, #256 @ 0x100 801057c: e002 b.n 8010584 801057e: 2310 movs r3, #16 8010580: e000 b.n 8010584 8010582: 2301 movs r3, #1 8010584: 4a42 ldr r2, [pc, #264] @ (8010690 ) 8010586: 6053 str r3, [r2, #4] 8010588: e057 b.n 801063a 801058a: 687b ldr r3, [r7, #4] 801058c: 681b ldr r3, [r3, #0] 801058e: 4a36 ldr r2, [pc, #216] @ (8010668 ) 8010590: 4293 cmp r3, r2 8010592: d04f beq.n 8010634 8010594: 687b ldr r3, [r7, #4] 8010596: 681b ldr r3, [r3, #0] 8010598: 4a34 ldr r2, [pc, #208] @ (801066c ) 801059a: 4293 cmp r3, r2 801059c: d048 beq.n 8010630 801059e: 687b ldr r3, [r7, #4] 80105a0: 681b ldr r3, [r3, #0] 80105a2: 4a33 ldr r2, [pc, #204] @ (8010670 ) 80105a4: 4293 cmp r3, r2 80105a6: d040 beq.n 801062a 80105a8: 687b ldr r3, [r7, #4] 80105aa: 681b ldr r3, [r3, #0] 80105ac: 4a31 ldr r2, [pc, #196] @ (8010674 ) 80105ae: 4293 cmp r3, r2 80105b0: d038 beq.n 8010624 80105b2: 687b ldr r3, [r7, #4] 80105b4: 681b ldr r3, [r3, #0] 80105b6: 4a30 ldr r2, [pc, #192] @ (8010678 ) 80105b8: 4293 cmp r3, r2 80105ba: d030 beq.n 801061e 80105bc: 687b ldr r3, [r7, #4] 80105be: 681b ldr r3, [r3, #0] 80105c0: 4a2e ldr r2, [pc, #184] @ (801067c ) 80105c2: 4293 cmp r3, r2 80105c4: d028 beq.n 8010618 80105c6: 687b ldr r3, [r7, #4] 80105c8: 681b ldr r3, [r3, #0] 80105ca: 4a26 ldr r2, [pc, #152] @ (8010664 ) 80105cc: 4293 cmp r3, r2 80105ce: d020 beq.n 8010612 80105d0: 687b ldr r3, [r7, #4] 80105d2: 681b ldr r3, [r3, #0] 80105d4: 4a2a ldr r2, [pc, #168] @ (8010680 ) 80105d6: 4293 cmp r3, r2 80105d8: d019 beq.n 801060e 80105da: 687b ldr r3, [r7, #4] 80105dc: 681b ldr r3, [r3, #0] 80105de: 4a29 ldr r2, [pc, #164] @ (8010684 ) 80105e0: 4293 cmp r3, r2 80105e2: d012 beq.n 801060a 80105e4: 687b ldr r3, [r7, #4] 80105e6: 681b ldr r3, [r3, #0] 80105e8: 4a27 ldr r2, [pc, #156] @ (8010688 ) 80105ea: 4293 cmp r3, r2 80105ec: d00a beq.n 8010604 80105ee: 687b ldr r3, [r7, #4] 80105f0: 681b ldr r3, [r3, #0] 80105f2: 4a26 ldr r2, [pc, #152] @ (801068c ) 80105f4: 4293 cmp r3, r2 80105f6: d102 bne.n 80105fe 80105f8: f44f 5380 mov.w r3, #4096 @ 0x1000 80105fc: e01b b.n 8010636 80105fe: f44f 3380 mov.w r3, #65536 @ 0x10000 8010602: e018 b.n 8010636 8010604: f44f 7380 mov.w r3, #256 @ 0x100 8010608: e015 b.n 8010636 801060a: 2310 movs r3, #16 801060c: e013 b.n 8010636 801060e: 2301 movs r3, #1 8010610: e011 b.n 8010636 8010612: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8010616: e00e b.n 8010636 8010618: f44f 1380 mov.w r3, #1048576 @ 0x100000 801061c: e00b b.n 8010636 801061e: f44f 3380 mov.w r3, #65536 @ 0x10000 8010622: e008 b.n 8010636 8010624: f44f 5380 mov.w r3, #4096 @ 0x1000 8010628: e005 b.n 8010636 801062a: f44f 7380 mov.w r3, #256 @ 0x100 801062e: e002 b.n 8010636 8010630: 2310 movs r3, #16 8010632: e000 b.n 8010636 8010634: 2301 movs r3, #1 8010636: 4a17 ldr r2, [pc, #92] @ (8010694 ) 8010638: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 801063a: 687b ldr r3, [r7, #4] 801063c: 2201 movs r2, #1 801063e: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8010642: 687b ldr r3, [r7, #4] 8010644: 2200 movs r2, #0 8010646: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 801064a: 687b ldr r3, [r7, #4] 801064c: 6b5b ldr r3, [r3, #52] @ 0x34 801064e: 2b00 cmp r3, #0 8010650: d003 beq.n 801065a { hdma->XferAbortCallback(hdma); 8010652: 687b ldr r3, [r7, #4] 8010654: 6b5b ldr r3, [r3, #52] @ 0x34 8010656: 6878 ldr r0, [r7, #4] 8010658: 4798 blx r3 } } return status; 801065a: 7bfb ldrb r3, [r7, #15] } 801065c: 4618 mov r0, r3 801065e: 3710 adds r7, #16 8010660: 46bd mov sp, r7 8010662: bd80 pop {r7, pc} 8010664: 40020080 .word 0x40020080 8010668: 40020008 .word 0x40020008 801066c: 4002001c .word 0x4002001c 8010670: 40020030 .word 0x40020030 8010674: 40020044 .word 0x40020044 8010678: 40020058 .word 0x40020058 801067c: 4002006c .word 0x4002006c 8010680: 40020408 .word 0x40020408 8010684: 4002041c .word 0x4002041c 8010688: 40020430 .word 0x40020430 801068c: 40020444 .word 0x40020444 8010690: 40020400 .word 0x40020400 8010694: 40020000 .word 0x40020000 08010698 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8010698: b580 push {r7, lr} 801069a: b084 sub sp, #16 801069c: af00 add r7, sp, #0 801069e: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; 80106a0: 687b ldr r3, [r7, #4] 80106a2: 6bdb ldr r3, [r3, #60] @ 0x3c 80106a4: 681b ldr r3, [r3, #0] 80106a6: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; 80106a8: 687b ldr r3, [r7, #4] 80106aa: 681b ldr r3, [r3, #0] 80106ac: 681b ldr r3, [r3, #0] 80106ae: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 80106b0: 687b ldr r3, [r7, #4] 80106b2: 6c1b ldr r3, [r3, #64] @ 0x40 80106b4: 2204 movs r2, #4 80106b6: 409a lsls r2, r3 80106b8: 68fb ldr r3, [r7, #12] 80106ba: 4013 ands r3, r2 80106bc: 2b00 cmp r3, #0 80106be: f000 80f1 beq.w 80108a4 80106c2: 68bb ldr r3, [r7, #8] 80106c4: f003 0304 and.w r3, r3, #4 80106c8: 2b00 cmp r3, #0 80106ca: f000 80eb beq.w 80108a4 { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 80106ce: 687b ldr r3, [r7, #4] 80106d0: 681b ldr r3, [r3, #0] 80106d2: 681b ldr r3, [r3, #0] 80106d4: f003 0320 and.w r3, r3, #32 80106d8: 2b00 cmp r3, #0 80106da: d107 bne.n 80106ec { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 80106dc: 687b ldr r3, [r7, #4] 80106de: 681b ldr r3, [r3, #0] 80106e0: 681a ldr r2, [r3, #0] 80106e2: 687b ldr r3, [r7, #4] 80106e4: 681b ldr r3, [r3, #0] 80106e6: f022 0204 bic.w r2, r2, #4 80106ea: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); 80106ec: 687b ldr r3, [r7, #4] 80106ee: 681b ldr r3, [r3, #0] 80106f0: 461a mov r2, r3 80106f2: 4b5f ldr r3, [pc, #380] @ (8010870 ) 80106f4: 429a cmp r2, r3 80106f6: d958 bls.n 80107aa 80106f8: 687b ldr r3, [r7, #4] 80106fa: 681b ldr r3, [r3, #0] 80106fc: 4a5d ldr r2, [pc, #372] @ (8010874 ) 80106fe: 4293 cmp r3, r2 8010700: d04f beq.n 80107a2 8010702: 687b ldr r3, [r7, #4] 8010704: 681b ldr r3, [r3, #0] 8010706: 4a5c ldr r2, [pc, #368] @ (8010878 ) 8010708: 4293 cmp r3, r2 801070a: d048 beq.n 801079e 801070c: 687b ldr r3, [r7, #4] 801070e: 681b ldr r3, [r3, #0] 8010710: 4a5a ldr r2, [pc, #360] @ (801087c ) 8010712: 4293 cmp r3, r2 8010714: d040 beq.n 8010798 8010716: 687b ldr r3, [r7, #4] 8010718: 681b ldr r3, [r3, #0] 801071a: 4a59 ldr r2, [pc, #356] @ (8010880 ) 801071c: 4293 cmp r3, r2 801071e: d038 beq.n 8010792 8010720: 687b ldr r3, [r7, #4] 8010722: 681b ldr r3, [r3, #0] 8010724: 4a57 ldr r2, [pc, #348] @ (8010884 ) 8010726: 4293 cmp r3, r2 8010728: d030 beq.n 801078c 801072a: 687b ldr r3, [r7, #4] 801072c: 681b ldr r3, [r3, #0] 801072e: 4a56 ldr r2, [pc, #344] @ (8010888 ) 8010730: 4293 cmp r3, r2 8010732: d028 beq.n 8010786 8010734: 687b ldr r3, [r7, #4] 8010736: 681b ldr r3, [r3, #0] 8010738: 4a4d ldr r2, [pc, #308] @ (8010870 ) 801073a: 4293 cmp r3, r2 801073c: d020 beq.n 8010780 801073e: 687b ldr r3, [r7, #4] 8010740: 681b ldr r3, [r3, #0] 8010742: 4a52 ldr r2, [pc, #328] @ (801088c ) 8010744: 4293 cmp r3, r2 8010746: d019 beq.n 801077c 8010748: 687b ldr r3, [r7, #4] 801074a: 681b ldr r3, [r3, #0] 801074c: 4a50 ldr r2, [pc, #320] @ (8010890 ) 801074e: 4293 cmp r3, r2 8010750: d012 beq.n 8010778 8010752: 687b ldr r3, [r7, #4] 8010754: 681b ldr r3, [r3, #0] 8010756: 4a4f ldr r2, [pc, #316] @ (8010894 ) 8010758: 4293 cmp r3, r2 801075a: d00a beq.n 8010772 801075c: 687b ldr r3, [r7, #4] 801075e: 681b ldr r3, [r3, #0] 8010760: 4a4d ldr r2, [pc, #308] @ (8010898 ) 8010762: 4293 cmp r3, r2 8010764: d102 bne.n 801076c 8010766: f44f 4380 mov.w r3, #16384 @ 0x4000 801076a: e01b b.n 80107a4 801076c: f44f 2380 mov.w r3, #262144 @ 0x40000 8010770: e018 b.n 80107a4 8010772: f44f 6380 mov.w r3, #1024 @ 0x400 8010776: e015 b.n 80107a4 8010778: 2340 movs r3, #64 @ 0x40 801077a: e013 b.n 80107a4 801077c: 2304 movs r3, #4 801077e: e011 b.n 80107a4 8010780: f04f 6380 mov.w r3, #67108864 @ 0x4000000 8010784: e00e b.n 80107a4 8010786: f44f 0380 mov.w r3, #4194304 @ 0x400000 801078a: e00b b.n 80107a4 801078c: f44f 2380 mov.w r3, #262144 @ 0x40000 8010790: e008 b.n 80107a4 8010792: f44f 4380 mov.w r3, #16384 @ 0x4000 8010796: e005 b.n 80107a4 8010798: f44f 6380 mov.w r3, #1024 @ 0x400 801079c: e002 b.n 80107a4 801079e: 2340 movs r3, #64 @ 0x40 80107a0: e000 b.n 80107a4 80107a2: 2304 movs r3, #4 80107a4: 4a3d ldr r2, [pc, #244] @ (801089c ) 80107a6: 6053 str r3, [r2, #4] 80107a8: e057 b.n 801085a 80107aa: 687b ldr r3, [r7, #4] 80107ac: 681b ldr r3, [r3, #0] 80107ae: 4a31 ldr r2, [pc, #196] @ (8010874 ) 80107b0: 4293 cmp r3, r2 80107b2: d04f beq.n 8010854 80107b4: 687b ldr r3, [r7, #4] 80107b6: 681b ldr r3, [r3, #0] 80107b8: 4a2f ldr r2, [pc, #188] @ (8010878 ) 80107ba: 4293 cmp r3, r2 80107bc: d048 beq.n 8010850 80107be: 687b ldr r3, [r7, #4] 80107c0: 681b ldr r3, [r3, #0] 80107c2: 4a2e ldr r2, [pc, #184] @ (801087c ) 80107c4: 4293 cmp r3, r2 80107c6: d040 beq.n 801084a 80107c8: 687b ldr r3, [r7, #4] 80107ca: 681b ldr r3, [r3, #0] 80107cc: 4a2c ldr r2, [pc, #176] @ (8010880 ) 80107ce: 4293 cmp r3, r2 80107d0: d038 beq.n 8010844 80107d2: 687b ldr r3, [r7, #4] 80107d4: 681b ldr r3, [r3, #0] 80107d6: 4a2b ldr r2, [pc, #172] @ (8010884 ) 80107d8: 4293 cmp r3, r2 80107da: d030 beq.n 801083e 80107dc: 687b ldr r3, [r7, #4] 80107de: 681b ldr r3, [r3, #0] 80107e0: 4a29 ldr r2, [pc, #164] @ (8010888 ) 80107e2: 4293 cmp r3, r2 80107e4: d028 beq.n 8010838 80107e6: 687b ldr r3, [r7, #4] 80107e8: 681b ldr r3, [r3, #0] 80107ea: 4a21 ldr r2, [pc, #132] @ (8010870 ) 80107ec: 4293 cmp r3, r2 80107ee: d020 beq.n 8010832 80107f0: 687b ldr r3, [r7, #4] 80107f2: 681b ldr r3, [r3, #0] 80107f4: 4a25 ldr r2, [pc, #148] @ (801088c ) 80107f6: 4293 cmp r3, r2 80107f8: d019 beq.n 801082e 80107fa: 687b ldr r3, [r7, #4] 80107fc: 681b ldr r3, [r3, #0] 80107fe: 4a24 ldr r2, [pc, #144] @ (8010890 ) 8010800: 4293 cmp r3, r2 8010802: d012 beq.n 801082a 8010804: 687b ldr r3, [r7, #4] 8010806: 681b ldr r3, [r3, #0] 8010808: 4a22 ldr r2, [pc, #136] @ (8010894 ) 801080a: 4293 cmp r3, r2 801080c: d00a beq.n 8010824 801080e: 687b ldr r3, [r7, #4] 8010810: 681b ldr r3, [r3, #0] 8010812: 4a21 ldr r2, [pc, #132] @ (8010898 ) 8010814: 4293 cmp r3, r2 8010816: d102 bne.n 801081e 8010818: f44f 4380 mov.w r3, #16384 @ 0x4000 801081c: e01b b.n 8010856 801081e: f44f 2380 mov.w r3, #262144 @ 0x40000 8010822: e018 b.n 8010856 8010824: f44f 6380 mov.w r3, #1024 @ 0x400 8010828: e015 b.n 8010856 801082a: 2340 movs r3, #64 @ 0x40 801082c: e013 b.n 8010856 801082e: 2304 movs r3, #4 8010830: e011 b.n 8010856 8010832: f04f 6380 mov.w r3, #67108864 @ 0x4000000 8010836: e00e b.n 8010856 8010838: f44f 0380 mov.w r3, #4194304 @ 0x400000 801083c: e00b b.n 8010856 801083e: f44f 2380 mov.w r3, #262144 @ 0x40000 8010842: e008 b.n 8010856 8010844: f44f 4380 mov.w r3, #16384 @ 0x4000 8010848: e005 b.n 8010856 801084a: f44f 6380 mov.w r3, #1024 @ 0x400 801084e: e002 b.n 8010856 8010850: 2340 movs r3, #64 @ 0x40 8010852: e000 b.n 8010856 8010854: 2304 movs r3, #4 8010856: 4a12 ldr r2, [pc, #72] @ (80108a0 ) 8010858: 6053 str r3, [r2, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 801085a: 687b ldr r3, [r7, #4] 801085c: 6adb ldr r3, [r3, #44] @ 0x2c 801085e: 2b00 cmp r3, #0 8010860: f000 8136 beq.w 8010ad0 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8010864: 687b ldr r3, [r7, #4] 8010866: 6adb ldr r3, [r3, #44] @ 0x2c 8010868: 6878 ldr r0, [r7, #4] 801086a: 4798 blx r3 if(hdma->XferHalfCpltCallback != NULL) 801086c: e130 b.n 8010ad0 801086e: bf00 nop 8010870: 40020080 .word 0x40020080 8010874: 40020008 .word 0x40020008 8010878: 4002001c .word 0x4002001c 801087c: 40020030 .word 0x40020030 8010880: 40020044 .word 0x40020044 8010884: 40020058 .word 0x40020058 8010888: 4002006c .word 0x4002006c 801088c: 40020408 .word 0x40020408 8010890: 4002041c .word 0x4002041c 8010894: 40020430 .word 0x40020430 8010898: 40020444 .word 0x40020444 801089c: 40020400 .word 0x40020400 80108a0: 40020000 .word 0x40020000 } } /* Transfer Complete Interrupt management ***********************************/ else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) 80108a4: 687b ldr r3, [r7, #4] 80108a6: 6c1b ldr r3, [r3, #64] @ 0x40 80108a8: 2202 movs r2, #2 80108aa: 409a lsls r2, r3 80108ac: 68fb ldr r3, [r7, #12] 80108ae: 4013 ands r3, r2 80108b0: 2b00 cmp r3, #0 80108b2: f000 80dd beq.w 8010a70 80108b6: 68bb ldr r3, [r7, #8] 80108b8: f003 0302 and.w r3, r3, #2 80108bc: 2b00 cmp r3, #0 80108be: f000 80d7 beq.w 8010a70 { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 80108c2: 687b ldr r3, [r7, #4] 80108c4: 681b ldr r3, [r3, #0] 80108c6: 681b ldr r3, [r3, #0] 80108c8: f003 0320 and.w r3, r3, #32 80108cc: 2b00 cmp r3, #0 80108ce: d10b bne.n 80108e8 { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 80108d0: 687b ldr r3, [r7, #4] 80108d2: 681b ldr r3, [r3, #0] 80108d4: 681a ldr r2, [r3, #0] 80108d6: 687b ldr r3, [r7, #4] 80108d8: 681b ldr r3, [r3, #0] 80108da: f022 020a bic.w r2, r2, #10 80108de: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80108e0: 687b ldr r3, [r7, #4] 80108e2: 2201 movs r2, #1 80108e4: f883 2021 strb.w r2, [r3, #33] @ 0x21 } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 80108e8: 687b ldr r3, [r7, #4] 80108ea: 681b ldr r3, [r3, #0] 80108ec: 461a mov r2, r3 80108ee: 4b7b ldr r3, [pc, #492] @ (8010adc ) 80108f0: 429a cmp r2, r3 80108f2: d958 bls.n 80109a6 80108f4: 687b ldr r3, [r7, #4] 80108f6: 681b ldr r3, [r3, #0] 80108f8: 4a79 ldr r2, [pc, #484] @ (8010ae0 ) 80108fa: 4293 cmp r3, r2 80108fc: d04f beq.n 801099e 80108fe: 687b ldr r3, [r7, #4] 8010900: 681b ldr r3, [r3, #0] 8010902: 4a78 ldr r2, [pc, #480] @ (8010ae4 ) 8010904: 4293 cmp r3, r2 8010906: d048 beq.n 801099a 8010908: 687b ldr r3, [r7, #4] 801090a: 681b ldr r3, [r3, #0] 801090c: 4a76 ldr r2, [pc, #472] @ (8010ae8 ) 801090e: 4293 cmp r3, r2 8010910: d040 beq.n 8010994 8010912: 687b ldr r3, [r7, #4] 8010914: 681b ldr r3, [r3, #0] 8010916: 4a75 ldr r2, [pc, #468] @ (8010aec ) 8010918: 4293 cmp r3, r2 801091a: d038 beq.n 801098e 801091c: 687b ldr r3, [r7, #4] 801091e: 681b ldr r3, [r3, #0] 8010920: 4a73 ldr r2, [pc, #460] @ (8010af0 ) 8010922: 4293 cmp r3, r2 8010924: d030 beq.n 8010988 8010926: 687b ldr r3, [r7, #4] 8010928: 681b ldr r3, [r3, #0] 801092a: 4a72 ldr r2, [pc, #456] @ (8010af4 ) 801092c: 4293 cmp r3, r2 801092e: d028 beq.n 8010982 8010930: 687b ldr r3, [r7, #4] 8010932: 681b ldr r3, [r3, #0] 8010934: 4a69 ldr r2, [pc, #420] @ (8010adc ) 8010936: 4293 cmp r3, r2 8010938: d020 beq.n 801097c 801093a: 687b ldr r3, [r7, #4] 801093c: 681b ldr r3, [r3, #0] 801093e: 4a6e ldr r2, [pc, #440] @ (8010af8 ) 8010940: 4293 cmp r3, r2 8010942: d019 beq.n 8010978 8010944: 687b ldr r3, [r7, #4] 8010946: 681b ldr r3, [r3, #0] 8010948: 4a6c ldr r2, [pc, #432] @ (8010afc ) 801094a: 4293 cmp r3, r2 801094c: d012 beq.n 8010974 801094e: 687b ldr r3, [r7, #4] 8010950: 681b ldr r3, [r3, #0] 8010952: 4a6b ldr r2, [pc, #428] @ (8010b00 ) 8010954: 4293 cmp r3, r2 8010956: d00a beq.n 801096e 8010958: 687b ldr r3, [r7, #4] 801095a: 681b ldr r3, [r3, #0] 801095c: 4a69 ldr r2, [pc, #420] @ (8010b04 ) 801095e: 4293 cmp r3, r2 8010960: d102 bne.n 8010968 8010962: f44f 5300 mov.w r3, #8192 @ 0x2000 8010966: e01b b.n 80109a0 8010968: f44f 3300 mov.w r3, #131072 @ 0x20000 801096c: e018 b.n 80109a0 801096e: f44f 7300 mov.w r3, #512 @ 0x200 8010972: e015 b.n 80109a0 8010974: 2320 movs r3, #32 8010976: e013 b.n 80109a0 8010978: 2302 movs r3, #2 801097a: e011 b.n 80109a0 801097c: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8010980: e00e b.n 80109a0 8010982: f44f 1300 mov.w r3, #2097152 @ 0x200000 8010986: e00b b.n 80109a0 8010988: f44f 3300 mov.w r3, #131072 @ 0x20000 801098c: e008 b.n 80109a0 801098e: f44f 5300 mov.w r3, #8192 @ 0x2000 8010992: e005 b.n 80109a0 8010994: f44f 7300 mov.w r3, #512 @ 0x200 8010998: e002 b.n 80109a0 801099a: 2320 movs r3, #32 801099c: e000 b.n 80109a0 801099e: 2302 movs r3, #2 80109a0: 4a59 ldr r2, [pc, #356] @ (8010b08 ) 80109a2: 6053 str r3, [r2, #4] 80109a4: e057 b.n 8010a56 80109a6: 687b ldr r3, [r7, #4] 80109a8: 681b ldr r3, [r3, #0] 80109aa: 4a4d ldr r2, [pc, #308] @ (8010ae0 ) 80109ac: 4293 cmp r3, r2 80109ae: d04f beq.n 8010a50 80109b0: 687b ldr r3, [r7, #4] 80109b2: 681b ldr r3, [r3, #0] 80109b4: 4a4b ldr r2, [pc, #300] @ (8010ae4 ) 80109b6: 4293 cmp r3, r2 80109b8: d048 beq.n 8010a4c 80109ba: 687b ldr r3, [r7, #4] 80109bc: 681b ldr r3, [r3, #0] 80109be: 4a4a ldr r2, [pc, #296] @ (8010ae8 ) 80109c0: 4293 cmp r3, r2 80109c2: d040 beq.n 8010a46 80109c4: 687b ldr r3, [r7, #4] 80109c6: 681b ldr r3, [r3, #0] 80109c8: 4a48 ldr r2, [pc, #288] @ (8010aec ) 80109ca: 4293 cmp r3, r2 80109cc: d038 beq.n 8010a40 80109ce: 687b ldr r3, [r7, #4] 80109d0: 681b ldr r3, [r3, #0] 80109d2: 4a47 ldr r2, [pc, #284] @ (8010af0 ) 80109d4: 4293 cmp r3, r2 80109d6: d030 beq.n 8010a3a 80109d8: 687b ldr r3, [r7, #4] 80109da: 681b ldr r3, [r3, #0] 80109dc: 4a45 ldr r2, [pc, #276] @ (8010af4 ) 80109de: 4293 cmp r3, r2 80109e0: d028 beq.n 8010a34 80109e2: 687b ldr r3, [r7, #4] 80109e4: 681b ldr r3, [r3, #0] 80109e6: 4a3d ldr r2, [pc, #244] @ (8010adc ) 80109e8: 4293 cmp r3, r2 80109ea: d020 beq.n 8010a2e 80109ec: 687b ldr r3, [r7, #4] 80109ee: 681b ldr r3, [r3, #0] 80109f0: 4a41 ldr r2, [pc, #260] @ (8010af8 ) 80109f2: 4293 cmp r3, r2 80109f4: d019 beq.n 8010a2a 80109f6: 687b ldr r3, [r7, #4] 80109f8: 681b ldr r3, [r3, #0] 80109fa: 4a40 ldr r2, [pc, #256] @ (8010afc ) 80109fc: 4293 cmp r3, r2 80109fe: d012 beq.n 8010a26 8010a00: 687b ldr r3, [r7, #4] 8010a02: 681b ldr r3, [r3, #0] 8010a04: 4a3e ldr r2, [pc, #248] @ (8010b00 ) 8010a06: 4293 cmp r3, r2 8010a08: d00a beq.n 8010a20 8010a0a: 687b ldr r3, [r7, #4] 8010a0c: 681b ldr r3, [r3, #0] 8010a0e: 4a3d ldr r2, [pc, #244] @ (8010b04 ) 8010a10: 4293 cmp r3, r2 8010a12: d102 bne.n 8010a1a 8010a14: f44f 5300 mov.w r3, #8192 @ 0x2000 8010a18: e01b b.n 8010a52 8010a1a: f44f 3300 mov.w r3, #131072 @ 0x20000 8010a1e: e018 b.n 8010a52 8010a20: f44f 7300 mov.w r3, #512 @ 0x200 8010a24: e015 b.n 8010a52 8010a26: 2320 movs r3, #32 8010a28: e013 b.n 8010a52 8010a2a: 2302 movs r3, #2 8010a2c: e011 b.n 8010a52 8010a2e: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8010a32: e00e b.n 8010a52 8010a34: f44f 1300 mov.w r3, #2097152 @ 0x200000 8010a38: e00b b.n 8010a52 8010a3a: f44f 3300 mov.w r3, #131072 @ 0x20000 8010a3e: e008 b.n 8010a52 8010a40: f44f 5300 mov.w r3, #8192 @ 0x2000 8010a44: e005 b.n 8010a52 8010a46: f44f 7300 mov.w r3, #512 @ 0x200 8010a4a: e002 b.n 8010a52 8010a4c: 2320 movs r3, #32 8010a4e: e000 b.n 8010a52 8010a50: 2302 movs r3, #2 8010a52: 4a2e ldr r2, [pc, #184] @ (8010b0c ) 8010a54: 6053 str r3, [r2, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 8010a56: 687b ldr r3, [r7, #4] 8010a58: 2200 movs r2, #0 8010a5a: f883 2020 strb.w r2, [r3, #32] if(hdma->XferCpltCallback != NULL) 8010a5e: 687b ldr r3, [r7, #4] 8010a60: 6a9b ldr r3, [r3, #40] @ 0x28 8010a62: 2b00 cmp r3, #0 8010a64: d034 beq.n 8010ad0 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8010a66: 687b ldr r3, [r7, #4] 8010a68: 6a9b ldr r3, [r3, #40] @ 0x28 8010a6a: 6878 ldr r0, [r7, #4] 8010a6c: 4798 blx r3 if(hdma->XferCpltCallback != NULL) 8010a6e: e02f b.n 8010ad0 } } /* Transfer Error Interrupt management **************************************/ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) 8010a70: 687b ldr r3, [r7, #4] 8010a72: 6c1b ldr r3, [r3, #64] @ 0x40 8010a74: 2208 movs r2, #8 8010a76: 409a lsls r2, r3 8010a78: 68fb ldr r3, [r7, #12] 8010a7a: 4013 ands r3, r2 8010a7c: 2b00 cmp r3, #0 8010a7e: d028 beq.n 8010ad2 8010a80: 68bb ldr r3, [r7, #8] 8010a82: f003 0308 and.w r3, r3, #8 8010a86: 2b00 cmp r3, #0 8010a88: d023 beq.n 8010ad2 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8010a8a: 687b ldr r3, [r7, #4] 8010a8c: 681b ldr r3, [r3, #0] 8010a8e: 681a ldr r2, [r3, #0] 8010a90: 687b ldr r3, [r7, #4] 8010a92: 681b ldr r3, [r3, #0] 8010a94: f022 020e bic.w r2, r2, #14 8010a98: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8010a9a: 687b ldr r3, [r7, #4] 8010a9c: 6c1a ldr r2, [r3, #64] @ 0x40 8010a9e: 687b ldr r3, [r7, #4] 8010aa0: 6bdb ldr r3, [r3, #60] @ 0x3c 8010aa2: 2101 movs r1, #1 8010aa4: fa01 f202 lsl.w r2, r1, r2 8010aa8: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 8010aaa: 687b ldr r3, [r7, #4] 8010aac: 2201 movs r2, #1 8010aae: 639a str r2, [r3, #56] @ 0x38 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8010ab0: 687b ldr r3, [r7, #4] 8010ab2: 2201 movs r2, #1 8010ab4: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8010ab8: 687b ldr r3, [r7, #4] 8010aba: 2200 movs r2, #0 8010abc: f883 2020 strb.w r2, [r3, #32] if (hdma->XferErrorCallback != NULL) 8010ac0: 687b ldr r3, [r7, #4] 8010ac2: 6b1b ldr r3, [r3, #48] @ 0x30 8010ac4: 2b00 cmp r3, #0 8010ac6: d004 beq.n 8010ad2 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8010ac8: 687b ldr r3, [r7, #4] 8010aca: 6b1b ldr r3, [r3, #48] @ 0x30 8010acc: 6878 ldr r0, [r7, #4] 8010ace: 4798 blx r3 } } return; 8010ad0: bf00 nop 8010ad2: bf00 nop } 8010ad4: 3710 adds r7, #16 8010ad6: 46bd mov sp, r7 8010ad8: bd80 pop {r7, pc} 8010ada: bf00 nop 8010adc: 40020080 .word 0x40020080 8010ae0: 40020008 .word 0x40020008 8010ae4: 4002001c .word 0x4002001c 8010ae8: 40020030 .word 0x40020030 8010aec: 40020044 .word 0x40020044 8010af0: 40020058 .word 0x40020058 8010af4: 4002006c .word 0x4002006c 8010af8: 40020408 .word 0x40020408 8010afc: 4002041c .word 0x4002041c 8010b00: 40020430 .word 0x40020430 8010b04: 40020444 .word 0x40020444 8010b08: 40020400 .word 0x40020400 8010b0c: 40020000 .word 0x40020000 08010b10 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval DMA Error Code */ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { 8010b10: b480 push {r7} 8010b12: b083 sub sp, #12 8010b14: af00 add r7, sp, #0 8010b16: 6078 str r0, [r7, #4] return hdma->ErrorCode; 8010b18: 687b ldr r3, [r7, #4] 8010b1a: 6b9b ldr r3, [r3, #56] @ 0x38 } 8010b1c: 4618 mov r0, r3 8010b1e: 370c adds r7, #12 8010b20: 46bd mov sp, r7 8010b22: bc80 pop {r7} 8010b24: 4770 bx lr 08010b26 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8010b26: b480 push {r7} 8010b28: b085 sub sp, #20 8010b2a: af00 add r7, sp, #0 8010b2c: 60f8 str r0, [r7, #12] 8010b2e: 60b9 str r1, [r7, #8] 8010b30: 607a str r2, [r7, #4] 8010b32: 603b str r3, [r7, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8010b34: 68fb ldr r3, [r7, #12] 8010b36: 6c1a ldr r2, [r3, #64] @ 0x40 8010b38: 68fb ldr r3, [r7, #12] 8010b3a: 6bdb ldr r3, [r3, #60] @ 0x3c 8010b3c: 2101 movs r1, #1 8010b3e: fa01 f202 lsl.w r2, r1, r2 8010b42: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 8010b44: 68fb ldr r3, [r7, #12] 8010b46: 681b ldr r3, [r3, #0] 8010b48: 683a ldr r2, [r7, #0] 8010b4a: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8010b4c: 68fb ldr r3, [r7, #12] 8010b4e: 685b ldr r3, [r3, #4] 8010b50: 2b10 cmp r3, #16 8010b52: d108 bne.n 8010b66 { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 8010b54: 68fb ldr r3, [r7, #12] 8010b56: 681b ldr r3, [r3, #0] 8010b58: 687a ldr r2, [r7, #4] 8010b5a: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; 8010b5c: 68fb ldr r3, [r7, #12] 8010b5e: 681b ldr r3, [r3, #0] 8010b60: 68ba ldr r2, [r7, #8] 8010b62: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } 8010b64: e007 b.n 8010b76 hdma->Instance->CPAR = SrcAddress; 8010b66: 68fb ldr r3, [r7, #12] 8010b68: 681b ldr r3, [r3, #0] 8010b6a: 68ba ldr r2, [r7, #8] 8010b6c: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; 8010b6e: 68fb ldr r3, [r7, #12] 8010b70: 681b ldr r3, [r3, #0] 8010b72: 687a ldr r2, [r7, #4] 8010b74: 60da str r2, [r3, #12] } 8010b76: bf00 nop 8010b78: 3714 adds r7, #20 8010b7a: 46bd mov sp, r7 8010b7c: bc80 pop {r7} 8010b7e: 4770 bx lr 08010b80 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8010b80: b480 push {r7} 8010b82: b08b sub sp, #44 @ 0x2c 8010b84: af00 add r7, sp, #0 8010b86: 6078 str r0, [r7, #4] 8010b88: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8010b8a: 2300 movs r3, #0 8010b8c: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8010b8e: 2300 movs r3, #0 8010b90: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8010b92: e169 b.n 8010e68 { /* Get the IO position */ ioposition = (0x01uL << position); 8010b94: 2201 movs r2, #1 8010b96: 6a7b ldr r3, [r7, #36] @ 0x24 8010b98: fa02 f303 lsl.w r3, r2, r3 8010b9c: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8010b9e: 683b ldr r3, [r7, #0] 8010ba0: 681b ldr r3, [r3, #0] 8010ba2: 69fa ldr r2, [r7, #28] 8010ba4: 4013 ands r3, r2 8010ba6: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8010ba8: 69ba ldr r2, [r7, #24] 8010baa: 69fb ldr r3, [r7, #28] 8010bac: 429a cmp r2, r3 8010bae: f040 8158 bne.w 8010e62 { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 8010bb2: 683b ldr r3, [r7, #0] 8010bb4: 685b ldr r3, [r3, #4] 8010bb6: 4a9a ldr r2, [pc, #616] @ (8010e20 ) 8010bb8: 4293 cmp r3, r2 8010bba: d05e beq.n 8010c7a 8010bbc: 4a98 ldr r2, [pc, #608] @ (8010e20 ) 8010bbe: 4293 cmp r3, r2 8010bc0: d875 bhi.n 8010cae 8010bc2: 4a98 ldr r2, [pc, #608] @ (8010e24 ) 8010bc4: 4293 cmp r3, r2 8010bc6: d058 beq.n 8010c7a 8010bc8: 4a96 ldr r2, [pc, #600] @ (8010e24 ) 8010bca: 4293 cmp r3, r2 8010bcc: d86f bhi.n 8010cae 8010bce: 4a96 ldr r2, [pc, #600] @ (8010e28 ) 8010bd0: 4293 cmp r3, r2 8010bd2: d052 beq.n 8010c7a 8010bd4: 4a94 ldr r2, [pc, #592] @ (8010e28 ) 8010bd6: 4293 cmp r3, r2 8010bd8: d869 bhi.n 8010cae 8010bda: 4a94 ldr r2, [pc, #592] @ (8010e2c ) 8010bdc: 4293 cmp r3, r2 8010bde: d04c beq.n 8010c7a 8010be0: 4a92 ldr r2, [pc, #584] @ (8010e2c ) 8010be2: 4293 cmp r3, r2 8010be4: d863 bhi.n 8010cae 8010be6: 4a92 ldr r2, [pc, #584] @ (8010e30 ) 8010be8: 4293 cmp r3, r2 8010bea: d046 beq.n 8010c7a 8010bec: 4a90 ldr r2, [pc, #576] @ (8010e30 ) 8010bee: 4293 cmp r3, r2 8010bf0: d85d bhi.n 8010cae 8010bf2: 2b12 cmp r3, #18 8010bf4: d82a bhi.n 8010c4c 8010bf6: 2b12 cmp r3, #18 8010bf8: d859 bhi.n 8010cae 8010bfa: a201 add r2, pc, #4 @ (adr r2, 8010c00 ) 8010bfc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8010c00: 08010c7b .word 0x08010c7b 8010c04: 08010c55 .word 0x08010c55 8010c08: 08010c67 .word 0x08010c67 8010c0c: 08010ca9 .word 0x08010ca9 8010c10: 08010caf .word 0x08010caf 8010c14: 08010caf .word 0x08010caf 8010c18: 08010caf .word 0x08010caf 8010c1c: 08010caf .word 0x08010caf 8010c20: 08010caf .word 0x08010caf 8010c24: 08010caf .word 0x08010caf 8010c28: 08010caf .word 0x08010caf 8010c2c: 08010caf .word 0x08010caf 8010c30: 08010caf .word 0x08010caf 8010c34: 08010caf .word 0x08010caf 8010c38: 08010caf .word 0x08010caf 8010c3c: 08010caf .word 0x08010caf 8010c40: 08010caf .word 0x08010caf 8010c44: 08010c5d .word 0x08010c5d 8010c48: 08010c71 .word 0x08010c71 8010c4c: 4a79 ldr r2, [pc, #484] @ (8010e34 ) 8010c4e: 4293 cmp r3, r2 8010c50: d013 beq.n 8010c7a config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8010c52: e02c b.n 8010cae config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8010c54: 683b ldr r3, [r7, #0] 8010c56: 68db ldr r3, [r3, #12] 8010c58: 623b str r3, [r7, #32] break; 8010c5a: e029 b.n 8010cb0 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8010c5c: 683b ldr r3, [r7, #0] 8010c5e: 68db ldr r3, [r3, #12] 8010c60: 3304 adds r3, #4 8010c62: 623b str r3, [r7, #32] break; 8010c64: e024 b.n 8010cb0 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8010c66: 683b ldr r3, [r7, #0] 8010c68: 68db ldr r3, [r3, #12] 8010c6a: 3308 adds r3, #8 8010c6c: 623b str r3, [r7, #32] break; 8010c6e: e01f b.n 8010cb0 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8010c70: 683b ldr r3, [r7, #0] 8010c72: 68db ldr r3, [r3, #12] 8010c74: 330c adds r3, #12 8010c76: 623b str r3, [r7, #32] break; 8010c78: e01a b.n 8010cb0 if (GPIO_Init->Pull == GPIO_NOPULL) 8010c7a: 683b ldr r3, [r7, #0] 8010c7c: 689b ldr r3, [r3, #8] 8010c7e: 2b00 cmp r3, #0 8010c80: d102 bne.n 8010c88 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8010c82: 2304 movs r3, #4 8010c84: 623b str r3, [r7, #32] break; 8010c86: e013 b.n 8010cb0 else if (GPIO_Init->Pull == GPIO_PULLUP) 8010c88: 683b ldr r3, [r7, #0] 8010c8a: 689b ldr r3, [r3, #8] 8010c8c: 2b01 cmp r3, #1 8010c8e: d105 bne.n 8010c9c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8010c90: 2308 movs r3, #8 8010c92: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8010c94: 687b ldr r3, [r7, #4] 8010c96: 69fa ldr r2, [r7, #28] 8010c98: 611a str r2, [r3, #16] break; 8010c9a: e009 b.n 8010cb0 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8010c9c: 2308 movs r3, #8 8010c9e: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 8010ca0: 687b ldr r3, [r7, #4] 8010ca2: 69fa ldr r2, [r7, #28] 8010ca4: 615a str r2, [r3, #20] break; 8010ca6: e003 b.n 8010cb0 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8010ca8: 2300 movs r3, #0 8010caa: 623b str r3, [r7, #32] break; 8010cac: e000 b.n 8010cb0 break; 8010cae: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8010cb0: 69bb ldr r3, [r7, #24] 8010cb2: 2bff cmp r3, #255 @ 0xff 8010cb4: d801 bhi.n 8010cba 8010cb6: 687b ldr r3, [r7, #4] 8010cb8: e001 b.n 8010cbe 8010cba: 687b ldr r3, [r7, #4] 8010cbc: 3304 adds r3, #4 8010cbe: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8010cc0: 69bb ldr r3, [r7, #24] 8010cc2: 2bff cmp r3, #255 @ 0xff 8010cc4: d802 bhi.n 8010ccc 8010cc6: 6a7b ldr r3, [r7, #36] @ 0x24 8010cc8: 009b lsls r3, r3, #2 8010cca: e002 b.n 8010cd2 8010ccc: 6a7b ldr r3, [r7, #36] @ 0x24 8010cce: 3b08 subs r3, #8 8010cd0: 009b lsls r3, r3, #2 8010cd2: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8010cd4: 697b ldr r3, [r7, #20] 8010cd6: 681a ldr r2, [r3, #0] 8010cd8: 210f movs r1, #15 8010cda: 693b ldr r3, [r7, #16] 8010cdc: fa01 f303 lsl.w r3, r1, r3 8010ce0: 43db mvns r3, r3 8010ce2: 401a ands r2, r3 8010ce4: 6a39 ldr r1, [r7, #32] 8010ce6: 693b ldr r3, [r7, #16] 8010ce8: fa01 f303 lsl.w r3, r1, r3 8010cec: 431a orrs r2, r3 8010cee: 697b ldr r3, [r7, #20] 8010cf0: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8010cf2: 683b ldr r3, [r7, #0] 8010cf4: 685b ldr r3, [r3, #4] 8010cf6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010cfa: 2b00 cmp r3, #0 8010cfc: f000 80b1 beq.w 8010e62 { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8010d00: 4b4d ldr r3, [pc, #308] @ (8010e38 ) 8010d02: 699b ldr r3, [r3, #24] 8010d04: 4a4c ldr r2, [pc, #304] @ (8010e38 ) 8010d06: f043 0301 orr.w r3, r3, #1 8010d0a: 6193 str r3, [r2, #24] 8010d0c: 4b4a ldr r3, [pc, #296] @ (8010e38 ) 8010d0e: 699b ldr r3, [r3, #24] 8010d10: f003 0301 and.w r3, r3, #1 8010d14: 60bb str r3, [r7, #8] 8010d16: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8010d18: 4a48 ldr r2, [pc, #288] @ (8010e3c ) 8010d1a: 6a7b ldr r3, [r7, #36] @ 0x24 8010d1c: 089b lsrs r3, r3, #2 8010d1e: 3302 adds r3, #2 8010d20: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8010d24: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8010d26: 6a7b ldr r3, [r7, #36] @ 0x24 8010d28: f003 0303 and.w r3, r3, #3 8010d2c: 009b lsls r3, r3, #2 8010d2e: 220f movs r2, #15 8010d30: fa02 f303 lsl.w r3, r2, r3 8010d34: 43db mvns r3, r3 8010d36: 68fa ldr r2, [r7, #12] 8010d38: 4013 ands r3, r2 8010d3a: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8010d3c: 687b ldr r3, [r7, #4] 8010d3e: 4a40 ldr r2, [pc, #256] @ (8010e40 ) 8010d40: 4293 cmp r3, r2 8010d42: d013 beq.n 8010d6c 8010d44: 687b ldr r3, [r7, #4] 8010d46: 4a3f ldr r2, [pc, #252] @ (8010e44 ) 8010d48: 4293 cmp r3, r2 8010d4a: d00d beq.n 8010d68 8010d4c: 687b ldr r3, [r7, #4] 8010d4e: 4a3e ldr r2, [pc, #248] @ (8010e48 ) 8010d50: 4293 cmp r3, r2 8010d52: d007 beq.n 8010d64 8010d54: 687b ldr r3, [r7, #4] 8010d56: 4a3d ldr r2, [pc, #244] @ (8010e4c ) 8010d58: 4293 cmp r3, r2 8010d5a: d101 bne.n 8010d60 8010d5c: 2303 movs r3, #3 8010d5e: e006 b.n 8010d6e 8010d60: 2304 movs r3, #4 8010d62: e004 b.n 8010d6e 8010d64: 2302 movs r3, #2 8010d66: e002 b.n 8010d6e 8010d68: 2301 movs r3, #1 8010d6a: e000 b.n 8010d6e 8010d6c: 2300 movs r3, #0 8010d6e: 6a7a ldr r2, [r7, #36] @ 0x24 8010d70: f002 0203 and.w r2, r2, #3 8010d74: 0092 lsls r2, r2, #2 8010d76: 4093 lsls r3, r2 8010d78: 68fa ldr r2, [r7, #12] 8010d7a: 4313 orrs r3, r2 8010d7c: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8010d7e: 492f ldr r1, [pc, #188] @ (8010e3c ) 8010d80: 6a7b ldr r3, [r7, #36] @ 0x24 8010d82: 089b lsrs r3, r3, #2 8010d84: 3302 adds r3, #2 8010d86: 68fa ldr r2, [r7, #12] 8010d88: f841 2023 str.w r2, [r1, r3, lsl #2] /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8010d8c: 683b ldr r3, [r7, #0] 8010d8e: 685b ldr r3, [r3, #4] 8010d90: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8010d94: 2b00 cmp r3, #0 8010d96: d006 beq.n 8010da6 { SET_BIT(EXTI->RTSR, iocurrent); 8010d98: 4b2d ldr r3, [pc, #180] @ (8010e50 ) 8010d9a: 689a ldr r2, [r3, #8] 8010d9c: 492c ldr r1, [pc, #176] @ (8010e50 ) 8010d9e: 69bb ldr r3, [r7, #24] 8010da0: 4313 orrs r3, r2 8010da2: 608b str r3, [r1, #8] 8010da4: e006 b.n 8010db4 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8010da6: 4b2a ldr r3, [pc, #168] @ (8010e50 ) 8010da8: 689a ldr r2, [r3, #8] 8010daa: 69bb ldr r3, [r7, #24] 8010dac: 43db mvns r3, r3 8010dae: 4928 ldr r1, [pc, #160] @ (8010e50 ) 8010db0: 4013 ands r3, r2 8010db2: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8010db4: 683b ldr r3, [r7, #0] 8010db6: 685b ldr r3, [r3, #4] 8010db8: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8010dbc: 2b00 cmp r3, #0 8010dbe: d006 beq.n 8010dce { SET_BIT(EXTI->FTSR, iocurrent); 8010dc0: 4b23 ldr r3, [pc, #140] @ (8010e50 ) 8010dc2: 68da ldr r2, [r3, #12] 8010dc4: 4922 ldr r1, [pc, #136] @ (8010e50 ) 8010dc6: 69bb ldr r3, [r7, #24] 8010dc8: 4313 orrs r3, r2 8010dca: 60cb str r3, [r1, #12] 8010dcc: e006 b.n 8010ddc } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8010dce: 4b20 ldr r3, [pc, #128] @ (8010e50 ) 8010dd0: 68da ldr r2, [r3, #12] 8010dd2: 69bb ldr r3, [r7, #24] 8010dd4: 43db mvns r3, r3 8010dd6: 491e ldr r1, [pc, #120] @ (8010e50 ) 8010dd8: 4013 ands r3, r2 8010dda: 60cb str r3, [r1, #12] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8010ddc: 683b ldr r3, [r7, #0] 8010dde: 685b ldr r3, [r3, #4] 8010de0: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010de4: 2b00 cmp r3, #0 8010de6: d006 beq.n 8010df6 { SET_BIT(EXTI->EMR, iocurrent); 8010de8: 4b19 ldr r3, [pc, #100] @ (8010e50 ) 8010dea: 685a ldr r2, [r3, #4] 8010dec: 4918 ldr r1, [pc, #96] @ (8010e50 ) 8010dee: 69bb ldr r3, [r7, #24] 8010df0: 4313 orrs r3, r2 8010df2: 604b str r3, [r1, #4] 8010df4: e006 b.n 8010e04 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8010df6: 4b16 ldr r3, [pc, #88] @ (8010e50 ) 8010df8: 685a ldr r2, [r3, #4] 8010dfa: 69bb ldr r3, [r7, #24] 8010dfc: 43db mvns r3, r3 8010dfe: 4914 ldr r1, [pc, #80] @ (8010e50 ) 8010e00: 4013 ands r3, r2 8010e02: 604b str r3, [r1, #4] } /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8010e04: 683b ldr r3, [r7, #0] 8010e06: 685b ldr r3, [r3, #4] 8010e08: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010e0c: 2b00 cmp r3, #0 8010e0e: d021 beq.n 8010e54 { SET_BIT(EXTI->IMR, iocurrent); 8010e10: 4b0f ldr r3, [pc, #60] @ (8010e50 ) 8010e12: 681a ldr r2, [r3, #0] 8010e14: 490e ldr r1, [pc, #56] @ (8010e50 ) 8010e16: 69bb ldr r3, [r7, #24] 8010e18: 4313 orrs r3, r2 8010e1a: 600b str r3, [r1, #0] 8010e1c: e021 b.n 8010e62 8010e1e: bf00 nop 8010e20: 10320000 .word 0x10320000 8010e24: 10310000 .word 0x10310000 8010e28: 10220000 .word 0x10220000 8010e2c: 10210000 .word 0x10210000 8010e30: 10120000 .word 0x10120000 8010e34: 10110000 .word 0x10110000 8010e38: 40021000 .word 0x40021000 8010e3c: 40010000 .word 0x40010000 8010e40: 40010800 .word 0x40010800 8010e44: 40010c00 .word 0x40010c00 8010e48: 40011000 .word 0x40011000 8010e4c: 40011400 .word 0x40011400 8010e50: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8010e54: 4b0b ldr r3, [pc, #44] @ (8010e84 ) 8010e56: 681a ldr r2, [r3, #0] 8010e58: 69bb ldr r3, [r7, #24] 8010e5a: 43db mvns r3, r3 8010e5c: 4909 ldr r1, [pc, #36] @ (8010e84 ) 8010e5e: 4013 ands r3, r2 8010e60: 600b str r3, [r1, #0] } } } position++; 8010e62: 6a7b ldr r3, [r7, #36] @ 0x24 8010e64: 3301 adds r3, #1 8010e66: 627b str r3, [r7, #36] @ 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8010e68: 683b ldr r3, [r7, #0] 8010e6a: 681a ldr r2, [r3, #0] 8010e6c: 6a7b ldr r3, [r7, #36] @ 0x24 8010e6e: fa22 f303 lsr.w r3, r2, r3 8010e72: 2b00 cmp r3, #0 8010e74: f47f ae8e bne.w 8010b94 } } 8010e78: bf00 nop 8010e7a: bf00 nop 8010e7c: 372c adds r7, #44 @ 0x2c 8010e7e: 46bd mov sp, r7 8010e80: bc80 pop {r7} 8010e82: 4770 bx lr 8010e84: 40010400 .word 0x40010400 08010e88 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8010e88: b480 push {r7} 8010e8a: b085 sub sp, #20 8010e8c: af00 add r7, sp, #0 8010e8e: 6078 str r0, [r7, #4] 8010e90: 460b mov r3, r1 8010e92: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8010e94: 687b ldr r3, [r7, #4] 8010e96: 689a ldr r2, [r3, #8] 8010e98: 887b ldrh r3, [r7, #2] 8010e9a: 4013 ands r3, r2 8010e9c: 2b00 cmp r3, #0 8010e9e: d002 beq.n 8010ea6 { bitstatus = GPIO_PIN_SET; 8010ea0: 2301 movs r3, #1 8010ea2: 73fb strb r3, [r7, #15] 8010ea4: e001 b.n 8010eaa } else { bitstatus = GPIO_PIN_RESET; 8010ea6: 2300 movs r3, #0 8010ea8: 73fb strb r3, [r7, #15] } return bitstatus; 8010eaa: 7bfb ldrb r3, [r7, #15] } 8010eac: 4618 mov r0, r3 8010eae: 3714 adds r7, #20 8010eb0: 46bd mov sp, r7 8010eb2: bc80 pop {r7} 8010eb4: 4770 bx lr 08010eb6 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8010eb6: b480 push {r7} 8010eb8: b083 sub sp, #12 8010eba: af00 add r7, sp, #0 8010ebc: 6078 str r0, [r7, #4] 8010ebe: 460b mov r3, r1 8010ec0: 807b strh r3, [r7, #2] 8010ec2: 4613 mov r3, r2 8010ec4: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8010ec6: 787b ldrb r3, [r7, #1] 8010ec8: 2b00 cmp r3, #0 8010eca: d003 beq.n 8010ed4 { GPIOx->BSRR = GPIO_Pin; 8010ecc: 887a ldrh r2, [r7, #2] 8010ece: 687b ldr r3, [r7, #4] 8010ed0: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8010ed2: e003 b.n 8010edc GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8010ed4: 887b ldrh r3, [r7, #2] 8010ed6: 041a lsls r2, r3, #16 8010ed8: 687b ldr r3, [r7, #4] 8010eda: 611a str r2, [r3, #16] } 8010edc: bf00 nop 8010ede: 370c adds r7, #12 8010ee0: 46bd mov sp, r7 8010ee2: bc80 pop {r7} 8010ee4: 4770 bx lr ... 08010ee8 : * @note If the HSE divided by 128 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 8010ee8: b480 push {r7} 8010eea: af00 add r7, sp, #0 /* Enable access to RTC and backup registers */ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 8010eec: 4b03 ldr r3, [pc, #12] @ (8010efc ) 8010eee: 2201 movs r2, #1 8010ef0: 601a str r2, [r3, #0] } 8010ef2: bf00 nop 8010ef4: 46bd mov sp, r7 8010ef6: bc80 pop {r7} 8010ef8: 4770 bx lr 8010efa: bf00 nop 8010efc: 420e0020 .word 0x420e0020 08010f00 : * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval HAL_StatusTypeDef */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { 8010f00: b580 push {r7, lr} 8010f02: b082 sub sp, #8 8010f04: af00 add r7, sp, #0 uint32_t tickstart; /* Get Start Tick */ tickstart = HAL_GetTick(); 8010f06: f7fd fc3f bl 800e788 8010f0a: 6078 str r0, [r7, #4] /* Set HSION bit */ SET_BIT(RCC->CR, RCC_CR_HSION); 8010f0c: 4b60 ldr r3, [pc, #384] @ (8011090 ) 8010f0e: 681b ldr r3, [r3, #0] 8010f10: 4a5f ldr r2, [pc, #380] @ (8011090 ) 8010f12: f043 0301 orr.w r3, r3, #1 8010f16: 6013 str r3, [r2, #0] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 8010f18: e008 b.n 8010f2c { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8010f1a: f7fd fc35 bl 800e788 8010f1e: 4602 mov r2, r0 8010f20: 687b ldr r3, [r7, #4] 8010f22: 1ad3 subs r3, r2, r3 8010f24: 2b02 cmp r3, #2 8010f26: d901 bls.n 8010f2c { return HAL_TIMEOUT; 8010f28: 2303 movs r3, #3 8010f2a: e0ac b.n 8011086 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 8010f2c: 4b58 ldr r3, [pc, #352] @ (8011090 ) 8010f2e: 681b ldr r3, [r3, #0] 8010f30: f003 0302 and.w r3, r3, #2 8010f34: 2b00 cmp r3, #0 8010f36: d0f0 beq.n 8010f1a } } /* Set HSITRIM bits to the reset value */ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); 8010f38: 4b55 ldr r3, [pc, #340] @ (8011090 ) 8010f3a: 681b ldr r3, [r3, #0] 8010f3c: f023 03f8 bic.w r3, r3, #248 @ 0xf8 8010f40: 4a53 ldr r2, [pc, #332] @ (8011090 ) 8010f42: f043 0380 orr.w r3, r3, #128 @ 0x80 8010f46: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010f48: f7fd fc1e bl 800e788 8010f4c: 6078 str r0, [r7, #4] /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); 8010f4e: 4b50 ldr r3, [pc, #320] @ (8011090 ) 8010f50: 2200 movs r2, #0 8010f52: 605a str r2, [r3, #4] /* Wait till clock switch is ready */ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 8010f54: e00a b.n 8010f6c { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8010f56: f7fd fc17 bl 800e788 8010f5a: 4602 mov r2, r0 8010f5c: 687b ldr r3, [r7, #4] 8010f5e: 1ad3 subs r3, r2, r3 8010f60: f241 3288 movw r2, #5000 @ 0x1388 8010f64: 4293 cmp r3, r2 8010f66: d901 bls.n 8010f6c { return HAL_TIMEOUT; 8010f68: 2303 movs r3, #3 8010f6a: e08c b.n 8011086 while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 8010f6c: 4b48 ldr r3, [pc, #288] @ (8011090 ) 8010f6e: 685b ldr r3, [r3, #4] 8010f70: f003 030c and.w r3, r3, #12 8010f74: 2b00 cmp r3, #0 8010f76: d1ee bne.n 8010f56 } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; 8010f78: 4b46 ldr r3, [pc, #280] @ (8011094 ) 8010f7a: 4a47 ldr r2, [pc, #284] @ (8011098 ) 8010f7c: 601a str r2, [r3, #0] /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 8010f7e: 4b47 ldr r3, [pc, #284] @ (801109c ) 8010f80: 681b ldr r3, [r3, #0] 8010f82: 4618 mov r0, r3 8010f84: f7fd fbbe bl 800e704 8010f88: 4603 mov r3, r0 8010f8a: 2b00 cmp r3, #0 8010f8c: d001 beq.n 8010f92 { return HAL_ERROR; 8010f8e: 2301 movs r3, #1 8010f90: e079 b.n 8011086 } /* Get Start Tick */ tickstart = HAL_GetTick(); 8010f92: f7fd fbf9 bl 800e788 8010f96: 6078 str r0, [r7, #4] /* Second step is to clear PLLON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 8010f98: 4b3d ldr r3, [pc, #244] @ (8011090 ) 8010f9a: 681b ldr r3, [r3, #0] 8010f9c: 4a3c ldr r2, [pc, #240] @ (8011090 ) 8010f9e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 8010fa2: 6013 str r3, [r2, #0] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 8010fa4: e008 b.n 8010fb8 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8010fa6: f7fd fbef bl 800e788 8010faa: 4602 mov r2, r0 8010fac: 687b ldr r3, [r7, #4] 8010fae: 1ad3 subs r3, r2, r3 8010fb0: 2b02 cmp r3, #2 8010fb2: d901 bls.n 8010fb8 { return HAL_TIMEOUT; 8010fb4: 2303 movs r3, #3 8010fb6: e066 b.n 8011086 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 8010fb8: 4b35 ldr r3, [pc, #212] @ (8011090 ) 8010fba: 681b ldr r3, [r3, #0] 8010fbc: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8010fc0: 2b00 cmp r3, #0 8010fc2: d1f0 bne.n 8010fa6 } } /* Ensure to reset PLLSRC and PLLMUL bits */ CLEAR_REG(RCC->CFGR); 8010fc4: 4b32 ldr r3, [pc, #200] @ (8011090 ) 8010fc6: 2200 movs r2, #0 8010fc8: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010fca: f7fd fbdd bl 800e788 8010fce: 6078 str r0, [r7, #4] /* Reset HSEON & CSSON bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON); 8010fd0: 4b2f ldr r3, [pc, #188] @ (8011090 ) 8010fd2: 681b ldr r3, [r3, #0] 8010fd4: 4a2e ldr r2, [pc, #184] @ (8011090 ) 8010fd6: f423 2310 bic.w r3, r3, #589824 @ 0x90000 8010fda: 6013 str r3, [r2, #0] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 8010fdc: e008 b.n 8010ff0 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8010fde: f7fd fbd3 bl 800e788 8010fe2: 4602 mov r2, r0 8010fe4: 687b ldr r3, [r7, #4] 8010fe6: 1ad3 subs r3, r2, r3 8010fe8: 2b64 cmp r3, #100 @ 0x64 8010fea: d901 bls.n 8010ff0 { return HAL_TIMEOUT; 8010fec: 2303 movs r3, #3 8010fee: e04a b.n 8011086 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 8010ff0: 4b27 ldr r3, [pc, #156] @ (8011090 ) 8010ff2: 681b ldr r3, [r3, #0] 8010ff4: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010ff8: 2b00 cmp r3, #0 8010ffa: d1f0 bne.n 8010fde } } /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 8010ffc: 4b24 ldr r3, [pc, #144] @ (8011090 ) 8010ffe: 681b ldr r3, [r3, #0] 8011000: 4a23 ldr r2, [pc, #140] @ (8011090 ) 8011002: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8011006: 6013 str r3, [r2, #0] #if defined(RCC_PLL2_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 8011008: f7fd fbbe bl 800e788 801100c: 6078 str r0, [r7, #4] /* Clear PLL2ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); 801100e: 4b20 ldr r3, [pc, #128] @ (8011090 ) 8011010: 681b ldr r3, [r3, #0] 8011012: 4a1f ldr r2, [pc, #124] @ (8011090 ) 8011014: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8011018: 6013 str r3, [r2, #0] /* Wait till PLL2 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 801101a: e008 b.n 801102e { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 801101c: f7fd fbb4 bl 800e788 8011020: 4602 mov r2, r0 8011022: 687b ldr r3, [r7, #4] 8011024: 1ad3 subs r3, r2, r3 8011026: 2b64 cmp r3, #100 @ 0x64 8011028: d901 bls.n 801102e { return HAL_TIMEOUT; 801102a: 2303 movs r3, #3 801102c: e02b b.n 8011086 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 801102e: 4b18 ldr r3, [pc, #96] @ (8011090 ) 8011030: 681b ldr r3, [r3, #0] 8011032: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8011036: 2b00 cmp r3, #0 8011038: d1f0 bne.n 801101c } #endif /* RCC_PLL2_SUPPORT */ #if defined(RCC_PLLI2S_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 801103a: f7fd fba5 bl 800e788 801103e: 6078 str r0, [r7, #4] /* Clear PLL3ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); 8011040: 4b13 ldr r3, [pc, #76] @ (8011090 ) 8011042: 681b ldr r3, [r3, #0] 8011044: 4a12 ldr r2, [pc, #72] @ (8011090 ) 8011046: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 801104a: 6013 str r3, [r2, #0] /* Wait till PLL3 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 801104c: e008 b.n 8011060 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 801104e: f7fd fb9b bl 800e788 8011052: 4602 mov r2, r0 8011054: 687b ldr r3, [r7, #4] 8011056: 1ad3 subs r3, r2, r3 8011058: 2b64 cmp r3, #100 @ 0x64 801105a: d901 bls.n 8011060 { return HAL_TIMEOUT; 801105c: 2303 movs r3, #3 801105e: e012 b.n 8011086 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 8011060: 4b0b ldr r3, [pc, #44] @ (8011090 ) 8011062: 681b ldr r3, [r3, #0] 8011064: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8011068: 2b00 cmp r3, #0 801106a: d1f0 bne.n 801104e } #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_CFGR2_PREDIV1) /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); 801106c: 4b08 ldr r3, [pc, #32] @ (8011090 ) 801106e: 2200 movs r2, #0 8011070: 62da str r2, [r3, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1 */ /* Reset all CSR flags */ SET_BIT(RCC->CSR, RCC_CSR_RMVF); 8011072: 4b07 ldr r3, [pc, #28] @ (8011090 ) 8011074: 6a5b ldr r3, [r3, #36] @ 0x24 8011076: 4a06 ldr r2, [pc, #24] @ (8011090 ) 8011078: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 801107c: 6253 str r3, [r2, #36] @ 0x24 /* Disable all interrupts */ CLEAR_REG(RCC->CIR); 801107e: 4b04 ldr r3, [pc, #16] @ (8011090 ) 8011080: 2200 movs r2, #0 8011082: 609a str r2, [r3, #8] return HAL_OK; 8011084: 2300 movs r3, #0 } 8011086: 4618 mov r0, r3 8011088: 3708 adds r7, #8 801108a: 46bd mov sp, r7 801108c: bd80 pop {r7, pc} 801108e: bf00 nop 8011090: 40021000 .word 0x40021000 8011094: 20000084 .word 0x20000084 8011098: 007a1200 .word 0x007a1200 801109c: 20000088 .word 0x20000088 080110a0 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 80110a0: b580 push {r7, lr} 80110a2: b086 sub sp, #24 80110a4: af00 add r7, sp, #0 80110a6: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 80110a8: 687b ldr r3, [r7, #4] 80110aa: 2b00 cmp r3, #0 80110ac: d101 bne.n 80110b2 { return HAL_ERROR; 80110ae: 2301 movs r3, #1 80110b0: e304 b.n 80116bc /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 80110b2: 687b ldr r3, [r7, #4] 80110b4: 681b ldr r3, [r3, #0] 80110b6: f003 0301 and.w r3, r3, #1 80110ba: 2b00 cmp r3, #0 80110bc: f000 8087 beq.w 80111ce { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 80110c0: 4b92 ldr r3, [pc, #584] @ (801130c ) 80110c2: 685b ldr r3, [r3, #4] 80110c4: f003 030c and.w r3, r3, #12 80110c8: 2b04 cmp r3, #4 80110ca: d00c beq.n 80110e6 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 80110cc: 4b8f ldr r3, [pc, #572] @ (801130c ) 80110ce: 685b ldr r3, [r3, #4] 80110d0: f003 030c and.w r3, r3, #12 80110d4: 2b08 cmp r3, #8 80110d6: d112 bne.n 80110fe 80110d8: 4b8c ldr r3, [pc, #560] @ (801130c ) 80110da: 685b ldr r3, [r3, #4] 80110dc: f403 3380 and.w r3, r3, #65536 @ 0x10000 80110e0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80110e4: d10b bne.n 80110fe { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80110e6: 4b89 ldr r3, [pc, #548] @ (801130c ) 80110e8: 681b ldr r3, [r3, #0] 80110ea: f403 3300 and.w r3, r3, #131072 @ 0x20000 80110ee: 2b00 cmp r3, #0 80110f0: d06c beq.n 80111cc 80110f2: 687b ldr r3, [r7, #4] 80110f4: 689b ldr r3, [r3, #8] 80110f6: 2b00 cmp r3, #0 80110f8: d168 bne.n 80111cc { return HAL_ERROR; 80110fa: 2301 movs r3, #1 80110fc: e2de b.n 80116bc } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80110fe: 687b ldr r3, [r7, #4] 8011100: 689b ldr r3, [r3, #8] 8011102: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8011106: d106 bne.n 8011116 8011108: 4b80 ldr r3, [pc, #512] @ (801130c ) 801110a: 681b ldr r3, [r3, #0] 801110c: 4a7f ldr r2, [pc, #508] @ (801130c ) 801110e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8011112: 6013 str r3, [r2, #0] 8011114: e02e b.n 8011174 8011116: 687b ldr r3, [r7, #4] 8011118: 689b ldr r3, [r3, #8] 801111a: 2b00 cmp r3, #0 801111c: d10c bne.n 8011138 801111e: 4b7b ldr r3, [pc, #492] @ (801130c ) 8011120: 681b ldr r3, [r3, #0] 8011122: 4a7a ldr r2, [pc, #488] @ (801130c ) 8011124: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8011128: 6013 str r3, [r2, #0] 801112a: 4b78 ldr r3, [pc, #480] @ (801130c ) 801112c: 681b ldr r3, [r3, #0] 801112e: 4a77 ldr r2, [pc, #476] @ (801130c ) 8011130: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8011134: 6013 str r3, [r2, #0] 8011136: e01d b.n 8011174 8011138: 687b ldr r3, [r7, #4] 801113a: 689b ldr r3, [r3, #8] 801113c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8011140: d10c bne.n 801115c 8011142: 4b72 ldr r3, [pc, #456] @ (801130c ) 8011144: 681b ldr r3, [r3, #0] 8011146: 4a71 ldr r2, [pc, #452] @ (801130c ) 8011148: f443 2380 orr.w r3, r3, #262144 @ 0x40000 801114c: 6013 str r3, [r2, #0] 801114e: 4b6f ldr r3, [pc, #444] @ (801130c ) 8011150: 681b ldr r3, [r3, #0] 8011152: 4a6e ldr r2, [pc, #440] @ (801130c ) 8011154: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8011158: 6013 str r3, [r2, #0] 801115a: e00b b.n 8011174 801115c: 4b6b ldr r3, [pc, #428] @ (801130c ) 801115e: 681b ldr r3, [r3, #0] 8011160: 4a6a ldr r2, [pc, #424] @ (801130c ) 8011162: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8011166: 6013 str r3, [r2, #0] 8011168: 4b68 ldr r3, [pc, #416] @ (801130c ) 801116a: 681b ldr r3, [r3, #0] 801116c: 4a67 ldr r2, [pc, #412] @ (801130c ) 801116e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8011172: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8011174: 687b ldr r3, [r7, #4] 8011176: 689b ldr r3, [r3, #8] 8011178: 2b00 cmp r3, #0 801117a: d013 beq.n 80111a4 { /* Get Start Tick */ tickstart = HAL_GetTick(); 801117c: f7fd fb04 bl 800e788 8011180: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8011182: e008 b.n 8011196 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8011184: f7fd fb00 bl 800e788 8011188: 4602 mov r2, r0 801118a: 693b ldr r3, [r7, #16] 801118c: 1ad3 subs r3, r2, r3 801118e: 2b64 cmp r3, #100 @ 0x64 8011190: d901 bls.n 8011196 { return HAL_TIMEOUT; 8011192: 2303 movs r3, #3 8011194: e292 b.n 80116bc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8011196: 4b5d ldr r3, [pc, #372] @ (801130c ) 8011198: 681b ldr r3, [r3, #0] 801119a: f403 3300 and.w r3, r3, #131072 @ 0x20000 801119e: 2b00 cmp r3, #0 80111a0: d0f0 beq.n 8011184 80111a2: e014 b.n 80111ce } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80111a4: f7fd faf0 bl 800e788 80111a8: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80111aa: e008 b.n 80111be { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80111ac: f7fd faec bl 800e788 80111b0: 4602 mov r2, r0 80111b2: 693b ldr r3, [r7, #16] 80111b4: 1ad3 subs r3, r2, r3 80111b6: 2b64 cmp r3, #100 @ 0x64 80111b8: d901 bls.n 80111be { return HAL_TIMEOUT; 80111ba: 2303 movs r3, #3 80111bc: e27e b.n 80116bc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80111be: 4b53 ldr r3, [pc, #332] @ (801130c ) 80111c0: 681b ldr r3, [r3, #0] 80111c2: f403 3300 and.w r3, r3, #131072 @ 0x20000 80111c6: 2b00 cmp r3, #0 80111c8: d1f0 bne.n 80111ac 80111ca: e000 b.n 80111ce if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80111cc: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 80111ce: 687b ldr r3, [r7, #4] 80111d0: 681b ldr r3, [r3, #0] 80111d2: f003 0302 and.w r3, r3, #2 80111d6: 2b00 cmp r3, #0 80111d8: d063 beq.n 80112a2 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 80111da: 4b4c ldr r3, [pc, #304] @ (801130c ) 80111dc: 685b ldr r3, [r3, #4] 80111de: f003 030c and.w r3, r3, #12 80111e2: 2b00 cmp r3, #0 80111e4: d00b beq.n 80111fe || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 80111e6: 4b49 ldr r3, [pc, #292] @ (801130c ) 80111e8: 685b ldr r3, [r3, #4] 80111ea: f003 030c and.w r3, r3, #12 80111ee: 2b08 cmp r3, #8 80111f0: d11c bne.n 801122c 80111f2: 4b46 ldr r3, [pc, #280] @ (801130c ) 80111f4: 685b ldr r3, [r3, #4] 80111f6: f403 3380 and.w r3, r3, #65536 @ 0x10000 80111fa: 2b00 cmp r3, #0 80111fc: d116 bne.n 801122c { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80111fe: 4b43 ldr r3, [pc, #268] @ (801130c ) 8011200: 681b ldr r3, [r3, #0] 8011202: f003 0302 and.w r3, r3, #2 8011206: 2b00 cmp r3, #0 8011208: d005 beq.n 8011216 801120a: 687b ldr r3, [r7, #4] 801120c: 695b ldr r3, [r3, #20] 801120e: 2b01 cmp r3, #1 8011210: d001 beq.n 8011216 { return HAL_ERROR; 8011212: 2301 movs r3, #1 8011214: e252 b.n 80116bc } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8011216: 4b3d ldr r3, [pc, #244] @ (801130c ) 8011218: 681b ldr r3, [r3, #0] 801121a: f023 02f8 bic.w r2, r3, #248 @ 0xf8 801121e: 687b ldr r3, [r7, #4] 8011220: 699b ldr r3, [r3, #24] 8011222: 00db lsls r3, r3, #3 8011224: 4939 ldr r1, [pc, #228] @ (801130c ) 8011226: 4313 orrs r3, r2 8011228: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 801122a: e03a b.n 80112a2 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 801122c: 687b ldr r3, [r7, #4] 801122e: 695b ldr r3, [r3, #20] 8011230: 2b00 cmp r3, #0 8011232: d020 beq.n 8011276 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8011234: 4b36 ldr r3, [pc, #216] @ (8011310 ) 8011236: 2201 movs r2, #1 8011238: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 801123a: f7fd faa5 bl 800e788 801123e: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8011240: e008 b.n 8011254 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8011242: f7fd faa1 bl 800e788 8011246: 4602 mov r2, r0 8011248: 693b ldr r3, [r7, #16] 801124a: 1ad3 subs r3, r2, r3 801124c: 2b02 cmp r3, #2 801124e: d901 bls.n 8011254 { return HAL_TIMEOUT; 8011250: 2303 movs r3, #3 8011252: e233 b.n 80116bc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8011254: 4b2d ldr r3, [pc, #180] @ (801130c ) 8011256: 681b ldr r3, [r3, #0] 8011258: f003 0302 and.w r3, r3, #2 801125c: 2b00 cmp r3, #0 801125e: d0f0 beq.n 8011242 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8011260: 4b2a ldr r3, [pc, #168] @ (801130c ) 8011262: 681b ldr r3, [r3, #0] 8011264: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8011268: 687b ldr r3, [r7, #4] 801126a: 699b ldr r3, [r3, #24] 801126c: 00db lsls r3, r3, #3 801126e: 4927 ldr r1, [pc, #156] @ (801130c ) 8011270: 4313 orrs r3, r2 8011272: 600b str r3, [r1, #0] 8011274: e015 b.n 80112a2 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8011276: 4b26 ldr r3, [pc, #152] @ (8011310 ) 8011278: 2200 movs r2, #0 801127a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 801127c: f7fd fa84 bl 800e788 8011280: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8011282: e008 b.n 8011296 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8011284: f7fd fa80 bl 800e788 8011288: 4602 mov r2, r0 801128a: 693b ldr r3, [r7, #16] 801128c: 1ad3 subs r3, r2, r3 801128e: 2b02 cmp r3, #2 8011290: d901 bls.n 8011296 { return HAL_TIMEOUT; 8011292: 2303 movs r3, #3 8011294: e212 b.n 80116bc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8011296: 4b1d ldr r3, [pc, #116] @ (801130c ) 8011298: 681b ldr r3, [r3, #0] 801129a: f003 0302 and.w r3, r3, #2 801129e: 2b00 cmp r3, #0 80112a0: d1f0 bne.n 8011284 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80112a2: 687b ldr r3, [r7, #4] 80112a4: 681b ldr r3, [r3, #0] 80112a6: f003 0308 and.w r3, r3, #8 80112aa: 2b00 cmp r3, #0 80112ac: d03a beq.n 8011324 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 80112ae: 687b ldr r3, [r7, #4] 80112b0: 69db ldr r3, [r3, #28] 80112b2: 2b00 cmp r3, #0 80112b4: d019 beq.n 80112ea { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 80112b6: 4b17 ldr r3, [pc, #92] @ (8011314 ) 80112b8: 2201 movs r2, #1 80112ba: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80112bc: f7fd fa64 bl 800e788 80112c0: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 80112c2: e008 b.n 80112d6 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80112c4: f7fd fa60 bl 800e788 80112c8: 4602 mov r2, r0 80112ca: 693b ldr r3, [r7, #16] 80112cc: 1ad3 subs r3, r2, r3 80112ce: 2b02 cmp r3, #2 80112d0: d901 bls.n 80112d6 { return HAL_TIMEOUT; 80112d2: 2303 movs r3, #3 80112d4: e1f2 b.n 80116bc while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 80112d6: 4b0d ldr r3, [pc, #52] @ (801130c ) 80112d8: 6a5b ldr r3, [r3, #36] @ 0x24 80112da: f003 0302 and.w r3, r3, #2 80112de: 2b00 cmp r3, #0 80112e0: d0f0 beq.n 80112c4 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 80112e2: 2001 movs r0, #1 80112e4: f000 fbca bl 8011a7c 80112e8: e01c b.n 8011324 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80112ea: 4b0a ldr r3, [pc, #40] @ (8011314 ) 80112ec: 2200 movs r2, #0 80112ee: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80112f0: f7fd fa4a bl 800e788 80112f4: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80112f6: e00f b.n 8011318 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80112f8: f7fd fa46 bl 800e788 80112fc: 4602 mov r2, r0 80112fe: 693b ldr r3, [r7, #16] 8011300: 1ad3 subs r3, r2, r3 8011302: 2b02 cmp r3, #2 8011304: d908 bls.n 8011318 { return HAL_TIMEOUT; 8011306: 2303 movs r3, #3 8011308: e1d8 b.n 80116bc 801130a: bf00 nop 801130c: 40021000 .word 0x40021000 8011310: 42420000 .word 0x42420000 8011314: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8011318: 4b9b ldr r3, [pc, #620] @ (8011588 ) 801131a: 6a5b ldr r3, [r3, #36] @ 0x24 801131c: f003 0302 and.w r3, r3, #2 8011320: 2b00 cmp r3, #0 8011322: d1e9 bne.n 80112f8 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8011324: 687b ldr r3, [r7, #4] 8011326: 681b ldr r3, [r3, #0] 8011328: f003 0304 and.w r3, r3, #4 801132c: 2b00 cmp r3, #0 801132e: f000 80a6 beq.w 801147e { FlagStatus pwrclkchanged = RESET; 8011332: 2300 movs r3, #0 8011334: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8011336: 4b94 ldr r3, [pc, #592] @ (8011588 ) 8011338: 69db ldr r3, [r3, #28] 801133a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 801133e: 2b00 cmp r3, #0 8011340: d10d bne.n 801135e { __HAL_RCC_PWR_CLK_ENABLE(); 8011342: 4b91 ldr r3, [pc, #580] @ (8011588 ) 8011344: 69db ldr r3, [r3, #28] 8011346: 4a90 ldr r2, [pc, #576] @ (8011588 ) 8011348: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 801134c: 61d3 str r3, [r2, #28] 801134e: 4b8e ldr r3, [pc, #568] @ (8011588 ) 8011350: 69db ldr r3, [r3, #28] 8011352: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011356: 60bb str r3, [r7, #8] 8011358: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 801135a: 2301 movs r3, #1 801135c: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 801135e: 4b8b ldr r3, [pc, #556] @ (801158c ) 8011360: 681b ldr r3, [r3, #0] 8011362: f403 7380 and.w r3, r3, #256 @ 0x100 8011366: 2b00 cmp r3, #0 8011368: d118 bne.n 801139c { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 801136a: 4b88 ldr r3, [pc, #544] @ (801158c ) 801136c: 681b ldr r3, [r3, #0] 801136e: 4a87 ldr r2, [pc, #540] @ (801158c ) 8011370: f443 7380 orr.w r3, r3, #256 @ 0x100 8011374: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8011376: f7fd fa07 bl 800e788 801137a: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 801137c: e008 b.n 8011390 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 801137e: f7fd fa03 bl 800e788 8011382: 4602 mov r2, r0 8011384: 693b ldr r3, [r7, #16] 8011386: 1ad3 subs r3, r2, r3 8011388: 2b64 cmp r3, #100 @ 0x64 801138a: d901 bls.n 8011390 { return HAL_TIMEOUT; 801138c: 2303 movs r3, #3 801138e: e195 b.n 80116bc while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8011390: 4b7e ldr r3, [pc, #504] @ (801158c ) 8011392: 681b ldr r3, [r3, #0] 8011394: f403 7380 and.w r3, r3, #256 @ 0x100 8011398: 2b00 cmp r3, #0 801139a: d0f0 beq.n 801137e } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 801139c: 687b ldr r3, [r7, #4] 801139e: 691b ldr r3, [r3, #16] 80113a0: 2b01 cmp r3, #1 80113a2: d106 bne.n 80113b2 80113a4: 4b78 ldr r3, [pc, #480] @ (8011588 ) 80113a6: 6a1b ldr r3, [r3, #32] 80113a8: 4a77 ldr r2, [pc, #476] @ (8011588 ) 80113aa: f043 0301 orr.w r3, r3, #1 80113ae: 6213 str r3, [r2, #32] 80113b0: e02d b.n 801140e 80113b2: 687b ldr r3, [r7, #4] 80113b4: 691b ldr r3, [r3, #16] 80113b6: 2b00 cmp r3, #0 80113b8: d10c bne.n 80113d4 80113ba: 4b73 ldr r3, [pc, #460] @ (8011588 ) 80113bc: 6a1b ldr r3, [r3, #32] 80113be: 4a72 ldr r2, [pc, #456] @ (8011588 ) 80113c0: f023 0301 bic.w r3, r3, #1 80113c4: 6213 str r3, [r2, #32] 80113c6: 4b70 ldr r3, [pc, #448] @ (8011588 ) 80113c8: 6a1b ldr r3, [r3, #32] 80113ca: 4a6f ldr r2, [pc, #444] @ (8011588 ) 80113cc: f023 0304 bic.w r3, r3, #4 80113d0: 6213 str r3, [r2, #32] 80113d2: e01c b.n 801140e 80113d4: 687b ldr r3, [r7, #4] 80113d6: 691b ldr r3, [r3, #16] 80113d8: 2b05 cmp r3, #5 80113da: d10c bne.n 80113f6 80113dc: 4b6a ldr r3, [pc, #424] @ (8011588 ) 80113de: 6a1b ldr r3, [r3, #32] 80113e0: 4a69 ldr r2, [pc, #420] @ (8011588 ) 80113e2: f043 0304 orr.w r3, r3, #4 80113e6: 6213 str r3, [r2, #32] 80113e8: 4b67 ldr r3, [pc, #412] @ (8011588 ) 80113ea: 6a1b ldr r3, [r3, #32] 80113ec: 4a66 ldr r2, [pc, #408] @ (8011588 ) 80113ee: f043 0301 orr.w r3, r3, #1 80113f2: 6213 str r3, [r2, #32] 80113f4: e00b b.n 801140e 80113f6: 4b64 ldr r3, [pc, #400] @ (8011588 ) 80113f8: 6a1b ldr r3, [r3, #32] 80113fa: 4a63 ldr r2, [pc, #396] @ (8011588 ) 80113fc: f023 0301 bic.w r3, r3, #1 8011400: 6213 str r3, [r2, #32] 8011402: 4b61 ldr r3, [pc, #388] @ (8011588 ) 8011404: 6a1b ldr r3, [r3, #32] 8011406: 4a60 ldr r2, [pc, #384] @ (8011588 ) 8011408: f023 0304 bic.w r3, r3, #4 801140c: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 801140e: 687b ldr r3, [r7, #4] 8011410: 691b ldr r3, [r3, #16] 8011412: 2b00 cmp r3, #0 8011414: d015 beq.n 8011442 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8011416: f7fd f9b7 bl 800e788 801141a: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 801141c: e00a b.n 8011434 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 801141e: f7fd f9b3 bl 800e788 8011422: 4602 mov r2, r0 8011424: 693b ldr r3, [r7, #16] 8011426: 1ad3 subs r3, r2, r3 8011428: f241 3288 movw r2, #5000 @ 0x1388 801142c: 4293 cmp r3, r2 801142e: d901 bls.n 8011434 { return HAL_TIMEOUT; 8011430: 2303 movs r3, #3 8011432: e143 b.n 80116bc while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8011434: 4b54 ldr r3, [pc, #336] @ (8011588 ) 8011436: 6a1b ldr r3, [r3, #32] 8011438: f003 0302 and.w r3, r3, #2 801143c: 2b00 cmp r3, #0 801143e: d0ee beq.n 801141e 8011440: e014 b.n 801146c } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8011442: f7fd f9a1 bl 800e788 8011446: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8011448: e00a b.n 8011460 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 801144a: f7fd f99d bl 800e788 801144e: 4602 mov r2, r0 8011450: 693b ldr r3, [r7, #16] 8011452: 1ad3 subs r3, r2, r3 8011454: f241 3288 movw r2, #5000 @ 0x1388 8011458: 4293 cmp r3, r2 801145a: d901 bls.n 8011460 { return HAL_TIMEOUT; 801145c: 2303 movs r3, #3 801145e: e12d b.n 80116bc while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8011460: 4b49 ldr r3, [pc, #292] @ (8011588 ) 8011462: 6a1b ldr r3, [r3, #32] 8011464: f003 0302 and.w r3, r3, #2 8011468: 2b00 cmp r3, #0 801146a: d1ee bne.n 801144a } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 801146c: 7dfb ldrb r3, [r7, #23] 801146e: 2b01 cmp r3, #1 8011470: d105 bne.n 801147e { __HAL_RCC_PWR_CLK_DISABLE(); 8011472: 4b45 ldr r3, [pc, #276] @ (8011588 ) 8011474: 69db ldr r3, [r3, #28] 8011476: 4a44 ldr r2, [pc, #272] @ (8011588 ) 8011478: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 801147c: 61d3 str r3, [r2, #28] #if defined(RCC_CR_PLL2ON) /*-------------------------------- PLL2 Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) 801147e: 687b ldr r3, [r7, #4] 8011480: 6adb ldr r3, [r3, #44] @ 0x2c 8011482: 2b00 cmp r3, #0 8011484: f000 808c beq.w 80115a0 { /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 8011488: 4b3f ldr r3, [pc, #252] @ (8011588 ) 801148a: 685b ldr r3, [r3, #4] 801148c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8011490: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8011494: d10e bne.n 80114b4 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 8011496: 4b3c ldr r3, [pc, #240] @ (8011588 ) 8011498: 685b ldr r3, [r3, #4] 801149a: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 801149e: 2b08 cmp r3, #8 80114a0: d108 bne.n 80114b4 ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) 80114a2: 4b39 ldr r3, [pc, #228] @ (8011588 ) 80114a4: 6adb ldr r3, [r3, #44] @ 0x2c 80114a6: f403 3380 and.w r3, r3, #65536 @ 0x10000 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 80114aa: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80114ae: d101 bne.n 80114b4 { return HAL_ERROR; 80114b0: 2301 movs r3, #1 80114b2: e103 b.n 80116bc } else { if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) 80114b4: 687b ldr r3, [r7, #4] 80114b6: 6adb ldr r3, [r3, #44] @ 0x2c 80114b8: 2b02 cmp r3, #2 80114ba: d14e bne.n 801155a assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); /* Prediv2 can be written only when the PLLI2S is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 80114bc: 4b32 ldr r3, [pc, #200] @ (8011588 ) 80114be: 681b ldr r3, [r3, #0] 80114c0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80114c4: 2b00 cmp r3, #0 80114c6: d009 beq.n 80114dc (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) 80114c8: 4b2f ldr r3, [pc, #188] @ (8011588 ) 80114ca: 6adb ldr r3, [r3, #44] @ 0x2c 80114cc: f003 02f0 and.w r2, r3, #240 @ 0xf0 80114d0: 687b ldr r3, [r7, #4] 80114d2: 6b5b ldr r3, [r3, #52] @ 0x34 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 80114d4: 429a cmp r2, r3 80114d6: d001 beq.n 80114dc { return HAL_ERROR; 80114d8: 2301 movs r3, #1 80114da: e0ef b.n 80116bc } /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 80114dc: 4b2c ldr r3, [pc, #176] @ (8011590 ) 80114de: 2200 movs r2, #0 80114e0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80114e2: f7fd f951 bl 800e788 80114e6: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 80114e8: e008 b.n 80114fc { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 80114ea: f7fd f94d bl 800e788 80114ee: 4602 mov r2, r0 80114f0: 693b ldr r3, [r7, #16] 80114f2: 1ad3 subs r3, r2, r3 80114f4: 2b64 cmp r3, #100 @ 0x64 80114f6: d901 bls.n 80114fc { return HAL_TIMEOUT; 80114f8: 2303 movs r3, #3 80114fa: e0df b.n 80116bc while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 80114fc: 4b22 ldr r3, [pc, #136] @ (8011588 ) 80114fe: 681b ldr r3, [r3, #0] 8011500: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8011504: 2b00 cmp r3, #0 8011506: d1f0 bne.n 80114ea } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); 8011508: 4b1f ldr r3, [pc, #124] @ (8011588 ) 801150a: 6adb ldr r3, [r3, #44] @ 0x2c 801150c: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8011510: 687b ldr r3, [r7, #4] 8011512: 6b5b ldr r3, [r3, #52] @ 0x34 8011514: 491c ldr r1, [pc, #112] @ (8011588 ) 8011516: 4313 orrs r3, r2 8011518: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); 801151a: 4b1b ldr r3, [pc, #108] @ (8011588 ) 801151c: 6adb ldr r3, [r3, #44] @ 0x2c 801151e: f423 6270 bic.w r2, r3, #3840 @ 0xf00 8011522: 687b ldr r3, [r7, #4] 8011524: 6b1b ldr r3, [r3, #48] @ 0x30 8011526: 4918 ldr r1, [pc, #96] @ (8011588 ) 8011528: 4313 orrs r3, r2 801152a: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); 801152c: 4b18 ldr r3, [pc, #96] @ (8011590 ) 801152e: 2201 movs r2, #1 8011530: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8011532: f7fd f929 bl 800e788 8011536: 6138 str r0, [r7, #16] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8011538: e008 b.n 801154c { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 801153a: f7fd f925 bl 800e788 801153e: 4602 mov r2, r0 8011540: 693b ldr r3, [r7, #16] 8011542: 1ad3 subs r3, r2, r3 8011544: 2b64 cmp r3, #100 @ 0x64 8011546: d901 bls.n 801154c { return HAL_TIMEOUT; 8011548: 2303 movs r3, #3 801154a: e0b7 b.n 80116bc while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 801154c: 4b0e ldr r3, [pc, #56] @ (8011588 ) 801154e: 681b ldr r3, [r3, #0] 8011550: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8011554: 2b00 cmp r3, #0 8011556: d0f0 beq.n 801153a 8011558: e022 b.n 80115a0 } } else { /* Set PREDIV1 source to HSE */ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); 801155a: 4b0b ldr r3, [pc, #44] @ (8011588 ) 801155c: 6adb ldr r3, [r3, #44] @ 0x2c 801155e: 4a0a ldr r2, [pc, #40] @ (8011588 ) 8011560: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8011564: 62d3 str r3, [r2, #44] @ 0x2c /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 8011566: 4b0a ldr r3, [pc, #40] @ (8011590 ) 8011568: 2200 movs r2, #0 801156a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 801156c: f7fd f90c bl 800e788 8011570: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8011572: e00f b.n 8011594 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8011574: f7fd f908 bl 800e788 8011578: 4602 mov r2, r0 801157a: 693b ldr r3, [r7, #16] 801157c: 1ad3 subs r3, r2, r3 801157e: 2b64 cmp r3, #100 @ 0x64 8011580: d908 bls.n 8011594 { return HAL_TIMEOUT; 8011582: 2303 movs r3, #3 8011584: e09a b.n 80116bc 8011586: bf00 nop 8011588: 40021000 .word 0x40021000 801158c: 40007000 .word 0x40007000 8011590: 42420068 .word 0x42420068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8011594: 4b4b ldr r3, [pc, #300] @ (80116c4 ) 8011596: 681b ldr r3, [r3, #0] 8011598: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 801159c: 2b00 cmp r3, #0 801159e: d1e9 bne.n 8011574 #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 80115a0: 687b ldr r3, [r7, #4] 80115a2: 6a1b ldr r3, [r3, #32] 80115a4: 2b00 cmp r3, #0 80115a6: f000 8088 beq.w 80116ba { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 80115aa: 4b46 ldr r3, [pc, #280] @ (80116c4 ) 80115ac: 685b ldr r3, [r3, #4] 80115ae: f003 030c and.w r3, r3, #12 80115b2: 2b08 cmp r3, #8 80115b4: d068 beq.n 8011688 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 80115b6: 687b ldr r3, [r7, #4] 80115b8: 6a1b ldr r3, [r3, #32] 80115ba: 2b02 cmp r3, #2 80115bc: d14d bne.n 801165a /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80115be: 4b42 ldr r3, [pc, #264] @ (80116c8 ) 80115c0: 2200 movs r2, #0 80115c2: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80115c4: f7fd f8e0 bl 800e788 80115c8: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80115ca: e008 b.n 80115de { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80115cc: f7fd f8dc bl 800e788 80115d0: 4602 mov r2, r0 80115d2: 693b ldr r3, [r7, #16] 80115d4: 1ad3 subs r3, r2, r3 80115d6: 2b02 cmp r3, #2 80115d8: d901 bls.n 80115de { return HAL_TIMEOUT; 80115da: 2303 movs r3, #3 80115dc: e06e b.n 80116bc while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80115de: 4b39 ldr r3, [pc, #228] @ (80116c4 ) 80115e0: 681b ldr r3, [r3, #0] 80115e2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80115e6: 2b00 cmp r3, #0 80115e8: d1f0 bne.n 80115cc } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 80115ea: 687b ldr r3, [r7, #4] 80115ec: 6a5b ldr r3, [r3, #36] @ 0x24 80115ee: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80115f2: d10f bne.n 8011614 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); #if defined(RCC_CFGR2_PREDIV1SRC) assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); 80115f4: 4b33 ldr r3, [pc, #204] @ (80116c4 ) 80115f6: 6ada ldr r2, [r3, #44] @ 0x2c 80115f8: 687b ldr r3, [r7, #4] 80115fa: 685b ldr r3, [r3, #4] 80115fc: 4931 ldr r1, [pc, #196] @ (80116c4 ) 80115fe: 4313 orrs r3, r2 8011600: 62cb str r3, [r1, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8011602: 4b30 ldr r3, [pc, #192] @ (80116c4 ) 8011604: 6adb ldr r3, [r3, #44] @ 0x2c 8011606: f023 020f bic.w r2, r3, #15 801160a: 687b ldr r3, [r7, #4] 801160c: 68db ldr r3, [r3, #12] 801160e: 492d ldr r1, [pc, #180] @ (80116c4 ) 8011610: 4313 orrs r3, r2 8011612: 62cb str r3, [r1, #44] @ 0x2c } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8011614: 4b2b ldr r3, [pc, #172] @ (80116c4 ) 8011616: 685b ldr r3, [r3, #4] 8011618: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 801161c: 687b ldr r3, [r7, #4] 801161e: 6a59 ldr r1, [r3, #36] @ 0x24 8011620: 687b ldr r3, [r7, #4] 8011622: 6a9b ldr r3, [r3, #40] @ 0x28 8011624: 430b orrs r3, r1 8011626: 4927 ldr r1, [pc, #156] @ (80116c4 ) 8011628: 4313 orrs r3, r2 801162a: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 801162c: 4b26 ldr r3, [pc, #152] @ (80116c8 ) 801162e: 2201 movs r2, #1 8011630: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8011632: f7fd f8a9 bl 800e788 8011636: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8011638: e008 b.n 801164c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 801163a: f7fd f8a5 bl 800e788 801163e: 4602 mov r2, r0 8011640: 693b ldr r3, [r7, #16] 8011642: 1ad3 subs r3, r2, r3 8011644: 2b02 cmp r3, #2 8011646: d901 bls.n 801164c { return HAL_TIMEOUT; 8011648: 2303 movs r3, #3 801164a: e037 b.n 80116bc while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 801164c: 4b1d ldr r3, [pc, #116] @ (80116c4 ) 801164e: 681b ldr r3, [r3, #0] 8011650: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8011654: 2b00 cmp r3, #0 8011656: d0f0 beq.n 801163a 8011658: e02f b.n 80116ba } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 801165a: 4b1b ldr r3, [pc, #108] @ (80116c8 ) 801165c: 2200 movs r2, #0 801165e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8011660: f7fd f892 bl 800e788 8011664: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8011666: e008 b.n 801167a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8011668: f7fd f88e bl 800e788 801166c: 4602 mov r2, r0 801166e: 693b ldr r3, [r7, #16] 8011670: 1ad3 subs r3, r2, r3 8011672: 2b02 cmp r3, #2 8011674: d901 bls.n 801167a { return HAL_TIMEOUT; 8011676: 2303 movs r3, #3 8011678: e020 b.n 80116bc while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 801167a: 4b12 ldr r3, [pc, #72] @ (80116c4 ) 801167c: 681b ldr r3, [r3, #0] 801167e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8011682: 2b00 cmp r3, #0 8011684: d1f0 bne.n 8011668 8011686: e018 b.n 80116ba } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8011688: 687b ldr r3, [r7, #4] 801168a: 6a1b ldr r3, [r3, #32] 801168c: 2b01 cmp r3, #1 801168e: d101 bne.n 8011694 { return HAL_ERROR; 8011690: 2301 movs r3, #1 8011692: e013 b.n 80116bc } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8011694: 4b0b ldr r3, [pc, #44] @ (80116c4 ) 8011696: 685b ldr r3, [r3, #4] 8011698: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 801169a: 68fb ldr r3, [r7, #12] 801169c: f403 3280 and.w r2, r3, #65536 @ 0x10000 80116a0: 687b ldr r3, [r7, #4] 80116a2: 6a5b ldr r3, [r3, #36] @ 0x24 80116a4: 429a cmp r2, r3 80116a6: d106 bne.n 80116b6 (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 80116a8: 68fb ldr r3, [r7, #12] 80116aa: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 80116ae: 687b ldr r3, [r7, #4] 80116b0: 6a9b ldr r3, [r3, #40] @ 0x28 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80116b2: 429a cmp r2, r3 80116b4: d001 beq.n 80116ba { return HAL_ERROR; 80116b6: 2301 movs r3, #1 80116b8: e000 b.n 80116bc } } } } return HAL_OK; 80116ba: 2300 movs r3, #0 } 80116bc: 4618 mov r0, r3 80116be: 3718 adds r7, #24 80116c0: 46bd mov sp, r7 80116c2: bd80 pop {r7, pc} 80116c4: 40021000 .word 0x40021000 80116c8: 42420060 .word 0x42420060 080116cc : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 80116cc: b580 push {r7, lr} 80116ce: b084 sub sp, #16 80116d0: af00 add r7, sp, #0 80116d2: 6078 str r0, [r7, #4] 80116d4: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 80116d6: 687b ldr r3, [r7, #4] 80116d8: 2b00 cmp r3, #0 80116da: d101 bne.n 80116e0 { return HAL_ERROR; 80116dc: 2301 movs r3, #1 80116de: e0d0 b.n 8011882 must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 80116e0: 4b6a ldr r3, [pc, #424] @ (801188c ) 80116e2: 681b ldr r3, [r3, #0] 80116e4: f003 0307 and.w r3, r3, #7 80116e8: 683a ldr r2, [r7, #0] 80116ea: 429a cmp r2, r3 80116ec: d910 bls.n 8011710 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80116ee: 4b67 ldr r3, [pc, #412] @ (801188c ) 80116f0: 681b ldr r3, [r3, #0] 80116f2: f023 0207 bic.w r2, r3, #7 80116f6: 4965 ldr r1, [pc, #404] @ (801188c ) 80116f8: 683b ldr r3, [r7, #0] 80116fa: 4313 orrs r3, r2 80116fc: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80116fe: 4b63 ldr r3, [pc, #396] @ (801188c ) 8011700: 681b ldr r3, [r3, #0] 8011702: f003 0307 and.w r3, r3, #7 8011706: 683a ldr r2, [r7, #0] 8011708: 429a cmp r2, r3 801170a: d001 beq.n 8011710 { return HAL_ERROR; 801170c: 2301 movs r3, #1 801170e: e0b8 b.n 8011882 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8011710: 687b ldr r3, [r7, #4] 8011712: 681b ldr r3, [r3, #0] 8011714: f003 0302 and.w r3, r3, #2 8011718: 2b00 cmp r3, #0 801171a: d020 beq.n 801175e { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 801171c: 687b ldr r3, [r7, #4] 801171e: 681b ldr r3, [r3, #0] 8011720: f003 0304 and.w r3, r3, #4 8011724: 2b00 cmp r3, #0 8011726: d005 beq.n 8011734 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8011728: 4b59 ldr r3, [pc, #356] @ (8011890 ) 801172a: 685b ldr r3, [r3, #4] 801172c: 4a58 ldr r2, [pc, #352] @ (8011890 ) 801172e: f443 63e0 orr.w r3, r3, #1792 @ 0x700 8011732: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8011734: 687b ldr r3, [r7, #4] 8011736: 681b ldr r3, [r3, #0] 8011738: f003 0308 and.w r3, r3, #8 801173c: 2b00 cmp r3, #0 801173e: d005 beq.n 801174c { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8011740: 4b53 ldr r3, [pc, #332] @ (8011890 ) 8011742: 685b ldr r3, [r3, #4] 8011744: 4a52 ldr r2, [pc, #328] @ (8011890 ) 8011746: f443 5360 orr.w r3, r3, #14336 @ 0x3800 801174a: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 801174c: 4b50 ldr r3, [pc, #320] @ (8011890 ) 801174e: 685b ldr r3, [r3, #4] 8011750: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8011754: 687b ldr r3, [r7, #4] 8011756: 689b ldr r3, [r3, #8] 8011758: 494d ldr r1, [pc, #308] @ (8011890 ) 801175a: 4313 orrs r3, r2 801175c: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 801175e: 687b ldr r3, [r7, #4] 8011760: 681b ldr r3, [r3, #0] 8011762: f003 0301 and.w r3, r3, #1 8011766: 2b00 cmp r3, #0 8011768: d040 beq.n 80117ec { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 801176a: 687b ldr r3, [r7, #4] 801176c: 685b ldr r3, [r3, #4] 801176e: 2b01 cmp r3, #1 8011770: d107 bne.n 8011782 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8011772: 4b47 ldr r3, [pc, #284] @ (8011890 ) 8011774: 681b ldr r3, [r3, #0] 8011776: f403 3300 and.w r3, r3, #131072 @ 0x20000 801177a: 2b00 cmp r3, #0 801177c: d115 bne.n 80117aa { return HAL_ERROR; 801177e: 2301 movs r3, #1 8011780: e07f b.n 8011882 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8011782: 687b ldr r3, [r7, #4] 8011784: 685b ldr r3, [r3, #4] 8011786: 2b02 cmp r3, #2 8011788: d107 bne.n 801179a { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 801178a: 4b41 ldr r3, [pc, #260] @ (8011890 ) 801178c: 681b ldr r3, [r3, #0] 801178e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8011792: 2b00 cmp r3, #0 8011794: d109 bne.n 80117aa { return HAL_ERROR; 8011796: 2301 movs r3, #1 8011798: e073 b.n 8011882 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 801179a: 4b3d ldr r3, [pc, #244] @ (8011890 ) 801179c: 681b ldr r3, [r3, #0] 801179e: f003 0302 and.w r3, r3, #2 80117a2: 2b00 cmp r3, #0 80117a4: d101 bne.n 80117aa { return HAL_ERROR; 80117a6: 2301 movs r3, #1 80117a8: e06b b.n 8011882 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 80117aa: 4b39 ldr r3, [pc, #228] @ (8011890 ) 80117ac: 685b ldr r3, [r3, #4] 80117ae: f023 0203 bic.w r2, r3, #3 80117b2: 687b ldr r3, [r7, #4] 80117b4: 685b ldr r3, [r3, #4] 80117b6: 4936 ldr r1, [pc, #216] @ (8011890 ) 80117b8: 4313 orrs r3, r2 80117ba: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 80117bc: f7fc ffe4 bl 800e788 80117c0: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80117c2: e00a b.n 80117da { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80117c4: f7fc ffe0 bl 800e788 80117c8: 4602 mov r2, r0 80117ca: 68fb ldr r3, [r7, #12] 80117cc: 1ad3 subs r3, r2, r3 80117ce: f241 3288 movw r2, #5000 @ 0x1388 80117d2: 4293 cmp r3, r2 80117d4: d901 bls.n 80117da { return HAL_TIMEOUT; 80117d6: 2303 movs r3, #3 80117d8: e053 b.n 8011882 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80117da: 4b2d ldr r3, [pc, #180] @ (8011890 ) 80117dc: 685b ldr r3, [r3, #4] 80117de: f003 020c and.w r2, r3, #12 80117e2: 687b ldr r3, [r7, #4] 80117e4: 685b ldr r3, [r3, #4] 80117e6: 009b lsls r3, r3, #2 80117e8: 429a cmp r2, r3 80117ea: d1eb bne.n 80117c4 } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 80117ec: 4b27 ldr r3, [pc, #156] @ (801188c ) 80117ee: 681b ldr r3, [r3, #0] 80117f0: f003 0307 and.w r3, r3, #7 80117f4: 683a ldr r2, [r7, #0] 80117f6: 429a cmp r2, r3 80117f8: d210 bcs.n 801181c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80117fa: 4b24 ldr r3, [pc, #144] @ (801188c ) 80117fc: 681b ldr r3, [r3, #0] 80117fe: f023 0207 bic.w r2, r3, #7 8011802: 4922 ldr r1, [pc, #136] @ (801188c ) 8011804: 683b ldr r3, [r7, #0] 8011806: 4313 orrs r3, r2 8011808: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 801180a: 4b20 ldr r3, [pc, #128] @ (801188c ) 801180c: 681b ldr r3, [r3, #0] 801180e: f003 0307 and.w r3, r3, #7 8011812: 683a ldr r2, [r7, #0] 8011814: 429a cmp r2, r3 8011816: d001 beq.n 801181c { return HAL_ERROR; 8011818: 2301 movs r3, #1 801181a: e032 b.n 8011882 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 801181c: 687b ldr r3, [r7, #4] 801181e: 681b ldr r3, [r3, #0] 8011820: f003 0304 and.w r3, r3, #4 8011824: 2b00 cmp r3, #0 8011826: d008 beq.n 801183a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8011828: 4b19 ldr r3, [pc, #100] @ (8011890 ) 801182a: 685b ldr r3, [r3, #4] 801182c: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8011830: 687b ldr r3, [r7, #4] 8011832: 68db ldr r3, [r3, #12] 8011834: 4916 ldr r1, [pc, #88] @ (8011890 ) 8011836: 4313 orrs r3, r2 8011838: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 801183a: 687b ldr r3, [r7, #4] 801183c: 681b ldr r3, [r3, #0] 801183e: f003 0308 and.w r3, r3, #8 8011842: 2b00 cmp r3, #0 8011844: d009 beq.n 801185a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 8011846: 4b12 ldr r3, [pc, #72] @ (8011890 ) 8011848: 685b ldr r3, [r3, #4] 801184a: f423 5260 bic.w r2, r3, #14336 @ 0x3800 801184e: 687b ldr r3, [r7, #4] 8011850: 691b ldr r3, [r3, #16] 8011852: 00db lsls r3, r3, #3 8011854: 490e ldr r1, [pc, #56] @ (8011890 ) 8011856: 4313 orrs r3, r2 8011858: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 801185a: f000 f821 bl 80118a0 801185e: 4602 mov r2, r0 8011860: 4b0b ldr r3, [pc, #44] @ (8011890 ) 8011862: 685b ldr r3, [r3, #4] 8011864: 091b lsrs r3, r3, #4 8011866: f003 030f and.w r3, r3, #15 801186a: 490a ldr r1, [pc, #40] @ (8011894 ) 801186c: 5ccb ldrb r3, [r1, r3] 801186e: fa22 f303 lsr.w r3, r2, r3 8011872: 4a09 ldr r2, [pc, #36] @ (8011898 ) 8011874: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 8011876: 4b09 ldr r3, [pc, #36] @ (801189c ) 8011878: 681b ldr r3, [r3, #0] 801187a: 4618 mov r0, r3 801187c: f7fc ff42 bl 800e704 return HAL_OK; 8011880: 2300 movs r3, #0 } 8011882: 4618 mov r0, r3 8011884: 3710 adds r7, #16 8011886: 46bd mov sp, r7 8011888: bd80 pop {r7, pc} 801188a: bf00 nop 801188c: 40022000 .word 0x40022000 8011890: 40021000 .word 0x40021000 8011894: 08017d64 .word 0x08017d64 8011898: 20000084 .word 0x20000084 801189c: 20000088 .word 0x20000088 080118a0 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 80118a0: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 80118a4: b08e sub sp, #56 @ 0x38 80118a6: af00 add r7, sp, #0 #else static const uint8_t aPredivFactorTable[2U] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 80118a8: 2300 movs r3, #0 80118aa: 62fb str r3, [r7, #44] @ 0x2c 80118ac: 2300 movs r3, #0 80118ae: 62bb str r3, [r7, #40] @ 0x28 80118b0: 2300 movs r3, #0 80118b2: 637b str r3, [r7, #52] @ 0x34 80118b4: 2300 movs r3, #0 80118b6: 627b str r3, [r7, #36] @ 0x24 uint32_t sysclockfreq = 0U; 80118b8: 2300 movs r3, #0 80118ba: 633b str r3, [r7, #48] @ 0x30 #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; 80118bc: 2300 movs r3, #0 80118be: 623b str r3, [r7, #32] 80118c0: 2300 movs r3, #0 80118c2: 61fb str r3, [r7, #28] #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 80118c4: 4b4e ldr r3, [pc, #312] @ (8011a00 ) 80118c6: 685b ldr r3, [r3, #4] 80118c8: 62fb str r3, [r7, #44] @ 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 80118ca: 6afb ldr r3, [r7, #44] @ 0x2c 80118cc: f003 030c and.w r3, r3, #12 80118d0: 2b04 cmp r3, #4 80118d2: d002 beq.n 80118da 80118d4: 2b08 cmp r3, #8 80118d6: d003 beq.n 80118e0 80118d8: e089 b.n 80119ee { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 80118da: 4b4a ldr r3, [pc, #296] @ (8011a04 ) 80118dc: 633b str r3, [r7, #48] @ 0x30 break; 80118de: e089 b.n 80119f4 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 80118e0: 6afb ldr r3, [r7, #44] @ 0x2c 80118e2: 0c9b lsrs r3, r3, #18 80118e4: f003 020f and.w r2, r3, #15 80118e8: 4b47 ldr r3, [pc, #284] @ (8011a08 ) 80118ea: 5c9b ldrb r3, [r3, r2] 80118ec: 627b str r3, [r7, #36] @ 0x24 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 80118ee: 6afb ldr r3, [r7, #44] @ 0x2c 80118f0: f403 3380 and.w r3, r3, #65536 @ 0x10000 80118f4: 2b00 cmp r3, #0 80118f6: d072 beq.n 80119de { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 80118f8: 4b41 ldr r3, [pc, #260] @ (8011a00 ) 80118fa: 6adb ldr r3, [r3, #44] @ 0x2c 80118fc: f003 020f and.w r2, r3, #15 8011900: 4b42 ldr r3, [pc, #264] @ (8011a0c ) 8011902: 5c9b ldrb r3, [r3, r2] 8011904: 62bb str r3, [r7, #40] @ 0x28 #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /*RCC_CFGR2_PREDIV1*/ #if defined(RCC_CFGR2_PREDIV1SRC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 8011906: 4b3e ldr r3, [pc, #248] @ (8011a00 ) 8011908: 6adb ldr r3, [r3, #44] @ 0x2c 801190a: f403 3380 and.w r3, r3, #65536 @ 0x10000 801190e: 2b00 cmp r3, #0 8011910: d053 beq.n 80119ba { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8011912: 4b3b ldr r3, [pc, #236] @ (8011a00 ) 8011914: 6adb ldr r3, [r3, #44] @ 0x2c 8011916: 091b lsrs r3, r3, #4 8011918: f003 030f and.w r3, r3, #15 801191c: 3301 adds r3, #1 801191e: 623b str r3, [r7, #32] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 8011920: 4b37 ldr r3, [pc, #220] @ (8011a00 ) 8011922: 6adb ldr r3, [r3, #44] @ 0x2c 8011924: 0a1b lsrs r3, r3, #8 8011926: f003 030f and.w r3, r3, #15 801192a: 3302 adds r3, #2 801192c: 61fb str r3, [r7, #28] pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); 801192e: 69fb ldr r3, [r7, #28] 8011930: 2200 movs r2, #0 8011932: 469a mov sl, r3 8011934: 4693 mov fp, r2 8011936: 6a7b ldr r3, [r7, #36] @ 0x24 8011938: 2200 movs r2, #0 801193a: 613b str r3, [r7, #16] 801193c: 617a str r2, [r7, #20] 801193e: 693b ldr r3, [r7, #16] 8011940: fb03 f20b mul.w r2, r3, fp 8011944: 697b ldr r3, [r7, #20] 8011946: fb0a f303 mul.w r3, sl, r3 801194a: 4413 add r3, r2 801194c: 693a ldr r2, [r7, #16] 801194e: fbaa 0102 umull r0, r1, sl, r2 8011952: 440b add r3, r1 8011954: 4619 mov r1, r3 8011956: 4b2b ldr r3, [pc, #172] @ (8011a04 ) 8011958: fb03 f201 mul.w r2, r3, r1 801195c: 2300 movs r3, #0 801195e: fb00 f303 mul.w r3, r0, r3 8011962: 4413 add r3, r2 8011964: 4a27 ldr r2, [pc, #156] @ (8011a04 ) 8011966: fba0 4502 umull r4, r5, r0, r2 801196a: 442b add r3, r5 801196c: 461d mov r5, r3 801196e: 6a3b ldr r3, [r7, #32] 8011970: 2200 movs r2, #0 8011972: 60bb str r3, [r7, #8] 8011974: 60fa str r2, [r7, #12] 8011976: 6abb ldr r3, [r7, #40] @ 0x28 8011978: 2200 movs r2, #0 801197a: 603b str r3, [r7, #0] 801197c: 607a str r2, [r7, #4] 801197e: e9d7 0102 ldrd r0, r1, [r7, #8] 8011982: 460b mov r3, r1 8011984: e9d7 ab00 ldrd sl, fp, [r7] 8011988: 4652 mov r2, sl 801198a: fb02 f203 mul.w r2, r2, r3 801198e: 465b mov r3, fp 8011990: 4684 mov ip, r0 8011992: fb0c f303 mul.w r3, ip, r3 8011996: 4413 add r3, r2 8011998: 4602 mov r2, r0 801199a: 4651 mov r1, sl 801199c: fba2 8901 umull r8, r9, r2, r1 80119a0: 444b add r3, r9 80119a2: 4699 mov r9, r3 80119a4: 4642 mov r2, r8 80119a6: 464b mov r3, r9 80119a8: 4620 mov r0, r4 80119aa: 4629 mov r1, r5 80119ac: f7f7 fc22 bl 80091f4 <__aeabi_uldivmod> 80119b0: 4602 mov r2, r0 80119b2: 460b mov r3, r1 80119b4: 4613 mov r3, r2 80119b6: 637b str r3, [r7, #52] @ 0x34 80119b8: e007 b.n 80119ca } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 80119ba: 6a7b ldr r3, [r7, #36] @ 0x24 80119bc: 4a11 ldr r2, [pc, #68] @ (8011a04 ) 80119be: fb03 f202 mul.w r2, r3, r2 80119c2: 6abb ldr r3, [r7, #40] @ 0x28 80119c4: fbb2 f3f3 udiv r3, r2, r3 80119c8: 637b str r3, [r7, #52] @ 0x34 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 80119ca: 4b0f ldr r3, [pc, #60] @ (8011a08 ) 80119cc: 7b5b ldrb r3, [r3, #13] 80119ce: 461a mov r2, r3 80119d0: 6a7b ldr r3, [r7, #36] @ 0x24 80119d2: 4293 cmp r3, r2 80119d4: d108 bne.n 80119e8 { pllclk = pllclk / 2; 80119d6: 6b7b ldr r3, [r7, #52] @ 0x34 80119d8: 085b lsrs r3, r3, #1 80119da: 637b str r3, [r7, #52] @ 0x34 80119dc: e004 b.n 80119e8 #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 80119de: 6a7b ldr r3, [r7, #36] @ 0x24 80119e0: 4a0b ldr r2, [pc, #44] @ (8011a10 ) 80119e2: fb02 f303 mul.w r3, r2, r3 80119e6: 637b str r3, [r7, #52] @ 0x34 } sysclockfreq = pllclk; 80119e8: 6b7b ldr r3, [r7, #52] @ 0x34 80119ea: 633b str r3, [r7, #48] @ 0x30 break; 80119ec: e002 b.n 80119f4 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 80119ee: 4b09 ldr r3, [pc, #36] @ (8011a14 ) 80119f0: 633b str r3, [r7, #48] @ 0x30 break; 80119f2: bf00 nop } } return sysclockfreq; 80119f4: 6b3b ldr r3, [r7, #48] @ 0x30 } 80119f6: 4618 mov r0, r3 80119f8: 3738 adds r7, #56 @ 0x38 80119fa: 46bd mov sp, r7 80119fc: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8011a00: 40021000 .word 0x40021000 8011a04: 017d7840 .word 0x017d7840 8011a08: 08017d7c .word 0x08017d7c 8011a0c: 08017d8c .word 0x08017d8c 8011a10: 003d0900 .word 0x003d0900 8011a14: 007a1200 .word 0x007a1200 08011a18 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8011a18: b480 push {r7} 8011a1a: af00 add r7, sp, #0 return SystemCoreClock; 8011a1c: 4b02 ldr r3, [pc, #8] @ (8011a28 ) 8011a1e: 681b ldr r3, [r3, #0] } 8011a20: 4618 mov r0, r3 8011a22: 46bd mov sp, r7 8011a24: bc80 pop {r7} 8011a26: 4770 bx lr 8011a28: 20000084 .word 0x20000084 08011a2c : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8011a2c: b580 push {r7, lr} 8011a2e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8011a30: f7ff fff2 bl 8011a18 8011a34: 4602 mov r2, r0 8011a36: 4b05 ldr r3, [pc, #20] @ (8011a4c ) 8011a38: 685b ldr r3, [r3, #4] 8011a3a: 0a1b lsrs r3, r3, #8 8011a3c: f003 0307 and.w r3, r3, #7 8011a40: 4903 ldr r1, [pc, #12] @ (8011a50 ) 8011a42: 5ccb ldrb r3, [r1, r3] 8011a44: fa22 f303 lsr.w r3, r2, r3 } 8011a48: 4618 mov r0, r3 8011a4a: bd80 pop {r7, pc} 8011a4c: 40021000 .word 0x40021000 8011a50: 08017d74 .word 0x08017d74 08011a54 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8011a54: b580 push {r7, lr} 8011a56: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8011a58: f7ff ffde bl 8011a18 8011a5c: 4602 mov r2, r0 8011a5e: 4b05 ldr r3, [pc, #20] @ (8011a74 ) 8011a60: 685b ldr r3, [r3, #4] 8011a62: 0adb lsrs r3, r3, #11 8011a64: f003 0307 and.w r3, r3, #7 8011a68: 4903 ldr r1, [pc, #12] @ (8011a78 ) 8011a6a: 5ccb ldrb r3, [r1, r3] 8011a6c: fa22 f303 lsr.w r3, r2, r3 } 8011a70: 4618 mov r0, r3 8011a72: bd80 pop {r7, pc} 8011a74: 40021000 .word 0x40021000 8011a78: 08017d74 .word 0x08017d74 08011a7c : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8011a7c: b480 push {r7} 8011a7e: b085 sub sp, #20 8011a80: af00 add r7, sp, #0 8011a82: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8011a84: 4b0a ldr r3, [pc, #40] @ (8011ab0 ) 8011a86: 681b ldr r3, [r3, #0] 8011a88: 4a0a ldr r2, [pc, #40] @ (8011ab4 ) 8011a8a: fba2 2303 umull r2, r3, r2, r3 8011a8e: 0a5b lsrs r3, r3, #9 8011a90: 687a ldr r2, [r7, #4] 8011a92: fb02 f303 mul.w r3, r2, r3 8011a96: 60fb str r3, [r7, #12] do { __NOP(); 8011a98: bf00 nop } while (Delay --); 8011a9a: 68fb ldr r3, [r7, #12] 8011a9c: 1e5a subs r2, r3, #1 8011a9e: 60fa str r2, [r7, #12] 8011aa0: 2b00 cmp r3, #0 8011aa2: d1f9 bne.n 8011a98 } 8011aa4: bf00 nop 8011aa6: bf00 nop 8011aa8: 3714 adds r7, #20 8011aaa: 46bd mov sp, r7 8011aac: bc80 pop {r7} 8011aae: 4770 bx lr 8011ab0: 20000084 .word 0x20000084 8011ab4: 10624dd3 .word 0x10624dd3 08011ab8 : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8011ab8: b580 push {r7, lr} 8011aba: b088 sub sp, #32 8011abc: af00 add r7, sp, #0 8011abe: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 8011ac0: 2300 movs r3, #0 8011ac2: 617b str r3, [r7, #20] 8011ac4: 2300 movs r3, #0 8011ac6: 613b str r3, [r7, #16] #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t pllactive = 0U; 8011ac8: 2300 movs r3, #0 8011aca: 61fb str r3, [r7, #28] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 8011acc: 687b ldr r3, [r7, #4] 8011ace: 681b ldr r3, [r3, #0] 8011ad0: f003 0301 and.w r3, r3, #1 8011ad4: 2b00 cmp r3, #0 8011ad6: d07d beq.n 8011bd4 { FlagStatus pwrclkchanged = RESET; 8011ad8: 2300 movs r3, #0 8011ada: 76fb strb r3, [r7, #27] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8011adc: 4b8b ldr r3, [pc, #556] @ (8011d0c ) 8011ade: 69db ldr r3, [r3, #28] 8011ae0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011ae4: 2b00 cmp r3, #0 8011ae6: d10d bne.n 8011b04 { __HAL_RCC_PWR_CLK_ENABLE(); 8011ae8: 4b88 ldr r3, [pc, #544] @ (8011d0c ) 8011aea: 69db ldr r3, [r3, #28] 8011aec: 4a87 ldr r2, [pc, #540] @ (8011d0c ) 8011aee: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8011af2: 61d3 str r3, [r2, #28] 8011af4: 4b85 ldr r3, [pc, #532] @ (8011d0c ) 8011af6: 69db ldr r3, [r3, #28] 8011af8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011afc: 60fb str r3, [r7, #12] 8011afe: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8011b00: 2301 movs r3, #1 8011b02: 76fb strb r3, [r7, #27] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8011b04: 4b82 ldr r3, [pc, #520] @ (8011d10 ) 8011b06: 681b ldr r3, [r3, #0] 8011b08: f403 7380 and.w r3, r3, #256 @ 0x100 8011b0c: 2b00 cmp r3, #0 8011b0e: d118 bne.n 8011b42 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8011b10: 4b7f ldr r3, [pc, #508] @ (8011d10 ) 8011b12: 681b ldr r3, [r3, #0] 8011b14: 4a7e ldr r2, [pc, #504] @ (8011d10 ) 8011b16: f443 7380 orr.w r3, r3, #256 @ 0x100 8011b1a: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8011b1c: f7fc fe34 bl 800e788 8011b20: 6178 str r0, [r7, #20] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8011b22: e008 b.n 8011b36 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8011b24: f7fc fe30 bl 800e788 8011b28: 4602 mov r2, r0 8011b2a: 697b ldr r3, [r7, #20] 8011b2c: 1ad3 subs r3, r2, r3 8011b2e: 2b64 cmp r3, #100 @ 0x64 8011b30: d901 bls.n 8011b36 { return HAL_TIMEOUT; 8011b32: 2303 movs r3, #3 8011b34: e0e5 b.n 8011d02 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8011b36: 4b76 ldr r3, [pc, #472] @ (8011d10 ) 8011b38: 681b ldr r3, [r3, #0] 8011b3a: f403 7380 and.w r3, r3, #256 @ 0x100 8011b3e: 2b00 cmp r3, #0 8011b40: d0f0 beq.n 8011b24 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 8011b42: 4b72 ldr r3, [pc, #456] @ (8011d0c ) 8011b44: 6a1b ldr r3, [r3, #32] 8011b46: f403 7340 and.w r3, r3, #768 @ 0x300 8011b4a: 613b str r3, [r7, #16] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8011b4c: 693b ldr r3, [r7, #16] 8011b4e: 2b00 cmp r3, #0 8011b50: d02e beq.n 8011bb0 8011b52: 687b ldr r3, [r7, #4] 8011b54: 685b ldr r3, [r3, #4] 8011b56: f403 7340 and.w r3, r3, #768 @ 0x300 8011b5a: 693a ldr r2, [r7, #16] 8011b5c: 429a cmp r2, r3 8011b5e: d027 beq.n 8011bb0 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8011b60: 4b6a ldr r3, [pc, #424] @ (8011d0c ) 8011b62: 6a1b ldr r3, [r3, #32] 8011b64: f423 7340 bic.w r3, r3, #768 @ 0x300 8011b68: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8011b6a: 4b6a ldr r3, [pc, #424] @ (8011d14 ) 8011b6c: 2201 movs r2, #1 8011b6e: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8011b70: 4b68 ldr r3, [pc, #416] @ (8011d14 ) 8011b72: 2200 movs r2, #0 8011b74: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 8011b76: 4a65 ldr r2, [pc, #404] @ (8011d0c ) 8011b78: 693b ldr r3, [r7, #16] 8011b7a: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8011b7c: 693b ldr r3, [r7, #16] 8011b7e: f003 0301 and.w r3, r3, #1 8011b82: 2b00 cmp r3, #0 8011b84: d014 beq.n 8011bb0 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8011b86: f7fc fdff bl 800e788 8011b8a: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8011b8c: e00a b.n 8011ba4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8011b8e: f7fc fdfb bl 800e788 8011b92: 4602 mov r2, r0 8011b94: 697b ldr r3, [r7, #20] 8011b96: 1ad3 subs r3, r2, r3 8011b98: f241 3288 movw r2, #5000 @ 0x1388 8011b9c: 4293 cmp r3, r2 8011b9e: d901 bls.n 8011ba4 { return HAL_TIMEOUT; 8011ba0: 2303 movs r3, #3 8011ba2: e0ae b.n 8011d02 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8011ba4: 4b59 ldr r3, [pc, #356] @ (8011d0c ) 8011ba6: 6a1b ldr r3, [r3, #32] 8011ba8: f003 0302 and.w r3, r3, #2 8011bac: 2b00 cmp r3, #0 8011bae: d0ee beq.n 8011b8e } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8011bb0: 4b56 ldr r3, [pc, #344] @ (8011d0c ) 8011bb2: 6a1b ldr r3, [r3, #32] 8011bb4: f423 7240 bic.w r2, r3, #768 @ 0x300 8011bb8: 687b ldr r3, [r7, #4] 8011bba: 685b ldr r3, [r3, #4] 8011bbc: 4953 ldr r1, [pc, #332] @ (8011d0c ) 8011bbe: 4313 orrs r3, r2 8011bc0: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8011bc2: 7efb ldrb r3, [r7, #27] 8011bc4: 2b01 cmp r3, #1 8011bc6: d105 bne.n 8011bd4 { __HAL_RCC_PWR_CLK_DISABLE(); 8011bc8: 4b50 ldr r3, [pc, #320] @ (8011d0c ) 8011bca: 69db ldr r3, [r3, #28] 8011bcc: 4a4f ldr r2, [pc, #316] @ (8011d0c ) 8011bce: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8011bd2: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8011bd4: 687b ldr r3, [r7, #4] 8011bd6: 681b ldr r3, [r3, #0] 8011bd8: f003 0302 and.w r3, r3, #2 8011bdc: 2b00 cmp r3, #0 8011bde: d008 beq.n 8011bf2 { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8011be0: 4b4a ldr r3, [pc, #296] @ (8011d0c ) 8011be2: 685b ldr r3, [r3, #4] 8011be4: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8011be8: 687b ldr r3, [r7, #4] 8011bea: 689b ldr r3, [r3, #8] 8011bec: 4947 ldr r1, [pc, #284] @ (8011d0c ) 8011bee: 4313 orrs r3, r2 8011bf0: 604b str r3, [r1, #4] } #if defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ I2S2 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) 8011bf2: 687b ldr r3, [r7, #4] 8011bf4: 681b ldr r3, [r3, #0] 8011bf6: f003 0304 and.w r3, r3, #4 8011bfa: 2b00 cmp r3, #0 8011bfc: d008 beq.n 8011c10 { /* Check the parameters */ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); /* Configure the I2S2 clock source */ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); 8011bfe: 4b43 ldr r3, [pc, #268] @ (8011d0c ) 8011c00: 6adb ldr r3, [r3, #44] @ 0x2c 8011c02: f423 3200 bic.w r2, r3, #131072 @ 0x20000 8011c06: 687b ldr r3, [r7, #4] 8011c08: 68db ldr r3, [r3, #12] 8011c0a: 4940 ldr r1, [pc, #256] @ (8011d0c ) 8011c0c: 4313 orrs r3, r2 8011c0e: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ I2S3 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) 8011c10: 687b ldr r3, [r7, #4] 8011c12: 681b ldr r3, [r3, #0] 8011c14: f003 0308 and.w r3, r3, #8 8011c18: 2b00 cmp r3, #0 8011c1a: d008 beq.n 8011c2e { /* Check the parameters */ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); /* Configure the I2S3 clock source */ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); 8011c1c: 4b3b ldr r3, [pc, #236] @ (8011d0c ) 8011c1e: 6adb ldr r3, [r3, #44] @ 0x2c 8011c20: f423 2280 bic.w r2, r3, #262144 @ 0x40000 8011c24: 687b ldr r3, [r7, #4] 8011c26: 691b ldr r3, [r3, #16] 8011c28: 4938 ldr r1, [pc, #224] @ (8011d0c ) 8011c2a: 4313 orrs r3, r2 8011c2c: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ PLL I2S Configuration ----------------------*/ /* Check that PLLI2S need to be enabled */ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) 8011c2e: 4b37 ldr r3, [pc, #220] @ (8011d0c ) 8011c30: 6adb ldr r3, [r3, #44] @ 0x2c 8011c32: f403 3300 and.w r3, r3, #131072 @ 0x20000 8011c36: 2b00 cmp r3, #0 8011c38: d105 bne.n 8011c46 8011c3a: 4b34 ldr r3, [pc, #208] @ (8011d0c ) 8011c3c: 6adb ldr r3, [r3, #44] @ 0x2c 8011c3e: f403 2380 and.w r3, r3, #262144 @ 0x40000 8011c42: 2b00 cmp r3, #0 8011c44: d001 beq.n 8011c4a { /* Update flag to indicate that PLL I2S should be active */ pllactive = 1; 8011c46: 2301 movs r3, #1 8011c48: 61fb str r3, [r7, #28] } /* Check if PLL I2S need to be enabled */ if (pllactive == 1) 8011c4a: 69fb ldr r3, [r7, #28] 8011c4c: 2b01 cmp r3, #1 8011c4e: d148 bne.n 8011ce2 { /* Enable PLL I2S only if not active */ if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) 8011c50: 4b2e ldr r3, [pc, #184] @ (8011d0c ) 8011c52: 681b ldr r3, [r3, #0] 8011c54: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011c58: 2b00 cmp r3, #0 8011c5a: d138 bne.n 8011cce assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); /* Prediv2 can be written only when the PLL2 is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 8011c5c: 4b2b ldr r3, [pc, #172] @ (8011d0c ) 8011c5e: 681b ldr r3, [r3, #0] 8011c60: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8011c64: 2b00 cmp r3, #0 8011c66: d009 beq.n 8011c7c (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) 8011c68: 4b28 ldr r3, [pc, #160] @ (8011d0c ) 8011c6a: 6adb ldr r3, [r3, #44] @ 0x2c 8011c6c: f003 02f0 and.w r2, r3, #240 @ 0xf0 8011c70: 687b ldr r3, [r7, #4] 8011c72: 699b ldr r3, [r3, #24] if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 8011c74: 429a cmp r2, r3 8011c76: d001 beq.n 8011c7c { return HAL_ERROR; 8011c78: 2301 movs r3, #1 8011c7a: e042 b.n 8011d02 } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); 8011c7c: 4b23 ldr r3, [pc, #140] @ (8011d0c ) 8011c7e: 6adb ldr r3, [r3, #44] @ 0x2c 8011c80: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8011c84: 687b ldr r3, [r7, #4] 8011c86: 699b ldr r3, [r3, #24] 8011c88: 4920 ldr r1, [pc, #128] @ (8011d0c ) 8011c8a: 4313 orrs r3, r2 8011c8c: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); 8011c8e: 4b1f ldr r3, [pc, #124] @ (8011d0c ) 8011c90: 6adb ldr r3, [r3, #44] @ 0x2c 8011c92: f423 4270 bic.w r2, r3, #61440 @ 0xf000 8011c96: 687b ldr r3, [r7, #4] 8011c98: 695b ldr r3, [r3, #20] 8011c9a: 491c ldr r1, [pc, #112] @ (8011d0c ) 8011c9c: 4313 orrs r3, r2 8011c9e: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); 8011ca0: 4b1d ldr r3, [pc, #116] @ (8011d18 ) 8011ca2: 2201 movs r2, #1 8011ca4: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8011ca6: f7fc fd6f bl 800e788 8011caa: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8011cac: e008 b.n 8011cc0 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8011cae: f7fc fd6b bl 800e788 8011cb2: 4602 mov r2, r0 8011cb4: 697b ldr r3, [r7, #20] 8011cb6: 1ad3 subs r3, r2, r3 8011cb8: 2b64 cmp r3, #100 @ 0x64 8011cba: d901 bls.n 8011cc0 { return HAL_TIMEOUT; 8011cbc: 2303 movs r3, #3 8011cbe: e020 b.n 8011d02 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8011cc0: 4b12 ldr r3, [pc, #72] @ (8011d0c ) 8011cc2: 681b ldr r3, [r3, #0] 8011cc4: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8011cc8: 2b00 cmp r3, #0 8011cca: d0f0 beq.n 8011cae 8011ccc: e009 b.n 8011ce2 } } else { /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) 8011cce: 4b0f ldr r3, [pc, #60] @ (8011d0c ) 8011cd0: 6adb ldr r3, [r3, #44] @ 0x2c 8011cd2: f403 4270 and.w r2, r3, #61440 @ 0xf000 8011cd6: 687b ldr r3, [r7, #4] 8011cd8: 695b ldr r3, [r3, #20] 8011cda: 429a cmp r2, r3 8011cdc: d001 beq.n 8011ce2 { return HAL_ERROR; 8011cde: 2301 movs r3, #1 8011ce0: e00f b.n 8011d02 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8011ce2: 687b ldr r3, [r7, #4] 8011ce4: 681b ldr r3, [r3, #0] 8011ce6: f003 0310 and.w r3, r3, #16 8011cea: 2b00 cmp r3, #0 8011cec: d008 beq.n 8011d00 { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8011cee: 4b07 ldr r3, [pc, #28] @ (8011d0c ) 8011cf0: 685b ldr r3, [r3, #4] 8011cf2: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 8011cf6: 687b ldr r3, [r7, #4] 8011cf8: 69db ldr r3, [r3, #28] 8011cfa: 4904 ldr r1, [pc, #16] @ (8011d0c ) 8011cfc: 4313 orrs r3, r2 8011cfe: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 8011d00: 2300 movs r3, #0 } 8011d02: 4618 mov r0, r3 8011d04: 3720 adds r7, #32 8011d06: 46bd mov sp, r7 8011d08: bd80 pop {r7, pc} 8011d0a: bf00 nop 8011d0c: 40021000 .word 0x40021000 8011d10: 40007000 .word 0x40007000 8011d14: 42420440 .word 0x42420440 8011d18: 42420070 .word 0x42420070 08011d1c : * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 8011d1c: b580 push {r7, lr} 8011d1e: b08a sub sp, #40 @ 0x28 8011d20: af00 add r7, sp, #0 8011d22: 6078 str r0, [r7, #4] #if defined(STM32F105xC) || defined(STM32F107xC) static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; 8011d24: 2300 movs r3, #0 8011d26: 61fb str r3, [r7, #28] 8011d28: 2300 movs r3, #0 8011d2a: 627b str r3, [r7, #36] @ 0x24 8011d2c: 2300 movs r3, #0 8011d2e: 61bb str r3, [r7, #24] uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; 8011d30: 2300 movs r3, #0 8011d32: 617b str r3, [r7, #20] 8011d34: 2300 movs r3, #0 8011d36: 613b str r3, [r7, #16] 8011d38: 2300 movs r3, #0 8011d3a: 60fb str r3, [r7, #12] static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; static const uint8_t aPredivFactorTable[2U] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 8011d3c: 2300 movs r3, #0 8011d3e: 60bb str r3, [r7, #8] 8011d40: 2300 movs r3, #0 8011d42: 623b str r3, [r7, #32] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 8011d44: 687b ldr r3, [r7, #4] 8011d46: 3b01 subs r3, #1 8011d48: 2b0f cmp r3, #15 8011d4a: f200 811d bhi.w 8011f88 8011d4e: a201 add r2, pc, #4 @ (adr r2, 8011d54 ) 8011d50: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011d54: 08011f09 .word 0x08011f09 8011d58: 08011f6d .word 0x08011f6d 8011d5c: 08011f89 .word 0x08011f89 8011d60: 08011e67 .word 0x08011e67 8011d64: 08011f89 .word 0x08011f89 8011d68: 08011f89 .word 0x08011f89 8011d6c: 08011f89 .word 0x08011f89 8011d70: 08011eb9 .word 0x08011eb9 8011d74: 08011f89 .word 0x08011f89 8011d78: 08011f89 .word 0x08011f89 8011d7c: 08011f89 .word 0x08011f89 8011d80: 08011f89 .word 0x08011f89 8011d84: 08011f89 .word 0x08011f89 8011d88: 08011f89 .word 0x08011f89 8011d8c: 08011f89 .word 0x08011f89 8011d90: 08011d95 .word 0x08011d95 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_USB: { /* Get RCC configuration ------------------------------------------------------*/ temp_reg = RCC->CFGR; 8011d94: 4b83 ldr r3, [pc, #524] @ (8011fa4 ) 8011d96: 685b ldr r3, [r3, #4] 8011d98: 60bb str r3, [r7, #8] /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) 8011d9a: 4b82 ldr r3, [pc, #520] @ (8011fa4 ) 8011d9c: 681b ldr r3, [r3, #0] 8011d9e: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8011da2: 2b00 cmp r3, #0 8011da4: f000 80f2 beq.w 8011f8c { pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8011da8: 68bb ldr r3, [r7, #8] 8011daa: 0c9b lsrs r3, r3, #18 8011dac: f003 030f and.w r3, r3, #15 8011db0: 4a7d ldr r2, [pc, #500] @ (8011fa8 ) 8011db2: 5cd3 ldrb r3, [r2, r3] 8011db4: 61bb str r3, [r7, #24] if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8011db6: 68bb ldr r3, [r7, #8] 8011db8: f403 3380 and.w r3, r3, #65536 @ 0x10000 8011dbc: 2b00 cmp r3, #0 8011dbe: d03b beq.n 8011e38 { #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ || defined(STM32F100xE) prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 8011dc0: 4b78 ldr r3, [pc, #480] @ (8011fa4 ) 8011dc2: 6adb ldr r3, [r3, #44] @ 0x2c 8011dc4: f003 030f and.w r3, r3, #15 8011dc8: 4a78 ldr r2, [pc, #480] @ (8011fac ) 8011dca: 5cd3 ldrb r3, [r2, r3] 8011dcc: 61fb str r3, [r7, #28] #else prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 8011dce: 4b75 ldr r3, [pc, #468] @ (8011fa4 ) 8011dd0: 6adb ldr r3, [r3, #44] @ 0x2c 8011dd2: f403 3380 and.w r3, r3, #65536 @ 0x10000 8011dd6: 2b00 cmp r3, #0 8011dd8: d01c beq.n 8011e14 { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8011dda: 4b72 ldr r3, [pc, #456] @ (8011fa4 ) 8011ddc: 6adb ldr r3, [r3, #44] @ 0x2c 8011dde: 091b lsrs r3, r3, #4 8011de0: f003 030f and.w r3, r3, #15 8011de4: 3301 adds r3, #1 8011de6: 60fb str r3, [r7, #12] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 8011de8: 4b6e ldr r3, [pc, #440] @ (8011fa4 ) 8011dea: 6adb ldr r3, [r3, #44] @ 0x2c 8011dec: 0a1b lsrs r3, r3, #8 8011dee: f003 030f and.w r3, r3, #15 8011df2: 3302 adds r3, #2 8011df4: 617b str r3, [r7, #20] pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); 8011df6: 4a6e ldr r2, [pc, #440] @ (8011fb0 ) 8011df8: 68fb ldr r3, [r7, #12] 8011dfa: fbb2 f3f3 udiv r3, r2, r3 8011dfe: 697a ldr r2, [r7, #20] 8011e00: fb03 f202 mul.w r2, r3, r2 8011e04: 69fb ldr r3, [r7, #28] 8011e06: fbb2 f2f3 udiv r2, r2, r3 8011e0a: 69bb ldr r3, [r7, #24] 8011e0c: fb02 f303 mul.w r3, r2, r3 8011e10: 627b str r3, [r7, #36] @ 0x24 8011e12: e007 b.n 8011e24 } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); 8011e14: 4a66 ldr r2, [pc, #408] @ (8011fb0 ) 8011e16: 69fb ldr r3, [r7, #28] 8011e18: fbb2 f2f3 udiv r2, r2, r3 8011e1c: 69bb ldr r3, [r7, #24] 8011e1e: fb02 f303 mul.w r3, r2, r3 8011e22: 627b str r3, [r7, #36] @ 0x24 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 8011e24: 4b60 ldr r3, [pc, #384] @ (8011fa8 ) 8011e26: 7b5b ldrb r3, [r3, #13] 8011e28: 461a mov r2, r3 8011e2a: 69bb ldr r3, [r7, #24] 8011e2c: 4293 cmp r3, r2 8011e2e: d108 bne.n 8011e42 { pllclk = pllclk / 2; 8011e30: 6a7b ldr r3, [r7, #36] @ 0x24 8011e32: 085b lsrs r3, r3, #1 8011e34: 627b str r3, [r7, #36] @ 0x24 8011e36: e004 b.n 8011e42 #endif /* STM32F105xC || STM32F107xC */ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8011e38: 69bb ldr r3, [r7, #24] 8011e3a: 4a5e ldr r2, [pc, #376] @ (8011fb4 ) 8011e3c: fb02 f303 mul.w r3, r2, r3 8011e40: 627b str r3, [r7, #36] @ 0x24 } /* Calcul of the USB frequency*/ #if defined(STM32F105xC) || defined(STM32F107xC) /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) 8011e42: 4b58 ldr r3, [pc, #352] @ (8011fa4 ) 8011e44: 685b ldr r3, [r3, #4] 8011e46: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8011e4a: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8011e4e: d102 bne.n 8011e56 { /* Prescaler of 2 selected for USB */ frequency = pllclk; 8011e50: 6a7b ldr r3, [r7, #36] @ 0x24 8011e52: 623b str r3, [r7, #32] /* Prescaler of 1.5 selected for USB */ frequency = (pllclk * 2) / 3; } #endif } break; 8011e54: e09a b.n 8011f8c frequency = (2 * pllclk) / 3; 8011e56: 6a7b ldr r3, [r7, #36] @ 0x24 8011e58: 005b lsls r3, r3, #1 8011e5a: 4a57 ldr r2, [pc, #348] @ (8011fb8 ) 8011e5c: fba2 2303 umull r2, r3, r2, r3 8011e60: 085b lsrs r3, r3, #1 8011e62: 623b str r3, [r7, #32] break; 8011e64: e092 b.n 8011f8c { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) 8011e66: 4b4f ldr r3, [pc, #316] @ (8011fa4 ) 8011e68: 6adb ldr r3, [r3, #44] @ 0x2c 8011e6a: f403 3300 and.w r3, r3, #131072 @ 0x20000 8011e6e: 2b00 cmp r3, #0 8011e70: d103 bne.n 8011e7a { /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); 8011e72: f7ff fd15 bl 80118a0 8011e76: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8011e78: e08a b.n 8011f90 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8011e7a: 4b4a ldr r3, [pc, #296] @ (8011fa4 ) 8011e7c: 681b ldr r3, [r3, #0] 8011e7e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011e82: 2b00 cmp r3, #0 8011e84: f000 8084 beq.w 8011f90 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8011e88: 4b46 ldr r3, [pc, #280] @ (8011fa4 ) 8011e8a: 6adb ldr r3, [r3, #44] @ 0x2c 8011e8c: 091b lsrs r3, r3, #4 8011e8e: f003 030f and.w r3, r3, #15 8011e92: 3301 adds r3, #1 8011e94: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 8011e96: 4b43 ldr r3, [pc, #268] @ (8011fa4 ) 8011e98: 6adb ldr r3, [r3, #44] @ 0x2c 8011e9a: 0b1b lsrs r3, r3, #12 8011e9c: f003 030f and.w r3, r3, #15 8011ea0: 3302 adds r3, #2 8011ea2: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8011ea4: 4a42 ldr r2, [pc, #264] @ (8011fb0 ) 8011ea6: 68fb ldr r3, [r7, #12] 8011ea8: fbb2 f3f3 udiv r3, r2, r3 8011eac: 693a ldr r2, [r7, #16] 8011eae: fb02 f303 mul.w r3, r2, r3 8011eb2: 005b lsls r3, r3, #1 8011eb4: 623b str r3, [r7, #32] break; 8011eb6: e06b b.n 8011f90 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) 8011eb8: 4b3a ldr r3, [pc, #232] @ (8011fa4 ) 8011eba: 6adb ldr r3, [r3, #44] @ 0x2c 8011ebc: f403 2380 and.w r3, r3, #262144 @ 0x40000 8011ec0: 2b00 cmp r3, #0 8011ec2: d103 bne.n 8011ecc { /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); 8011ec4: f7ff fcec bl 80118a0 8011ec8: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8011eca: e063 b.n 8011f94 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8011ecc: 4b35 ldr r3, [pc, #212] @ (8011fa4 ) 8011ece: 681b ldr r3, [r3, #0] 8011ed0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011ed4: 2b00 cmp r3, #0 8011ed6: d05d beq.n 8011f94 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8011ed8: 4b32 ldr r3, [pc, #200] @ (8011fa4 ) 8011eda: 6adb ldr r3, [r3, #44] @ 0x2c 8011edc: 091b lsrs r3, r3, #4 8011ede: f003 030f and.w r3, r3, #15 8011ee2: 3301 adds r3, #1 8011ee4: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 8011ee6: 4b2f ldr r3, [pc, #188] @ (8011fa4 ) 8011ee8: 6adb ldr r3, [r3, #44] @ 0x2c 8011eea: 0b1b lsrs r3, r3, #12 8011eec: f003 030f and.w r3, r3, #15 8011ef0: 3302 adds r3, #2 8011ef2: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8011ef4: 4a2e ldr r2, [pc, #184] @ (8011fb0 ) 8011ef6: 68fb ldr r3, [r7, #12] 8011ef8: fbb2 f3f3 udiv r3, r2, r3 8011efc: 693a ldr r2, [r7, #16] 8011efe: fb02 f303 mul.w r3, r2, r3 8011f02: 005b lsls r3, r3, #1 8011f04: 623b str r3, [r7, #32] break; 8011f06: e045 b.n 8011f94 } #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ case RCC_PERIPHCLK_RTC: { /* Get RCC BDCR configuration ------------------------------------------------------*/ temp_reg = RCC->BDCR; 8011f08: 4b26 ldr r3, [pc, #152] @ (8011fa4 ) 8011f0a: 6a1b ldr r3, [r3, #32] 8011f0c: 60bb str r3, [r7, #8] /* Check if LSE is ready if RTC clock selection is LSE */ if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 8011f0e: 68bb ldr r3, [r7, #8] 8011f10: f403 7340 and.w r3, r3, #768 @ 0x300 8011f14: f5b3 7f80 cmp.w r3, #256 @ 0x100 8011f18: d108 bne.n 8011f2c 8011f1a: 68bb ldr r3, [r7, #8] 8011f1c: f003 0302 and.w r3, r3, #2 8011f20: 2b00 cmp r3, #0 8011f22: d003 beq.n 8011f2c { frequency = LSE_VALUE; 8011f24: f44f 4300 mov.w r3, #32768 @ 0x8000 8011f28: 623b str r3, [r7, #32] 8011f2a: e01e b.n 8011f6a } /* Check if LSI is ready if RTC clock selection is LSI */ else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 8011f2c: 68bb ldr r3, [r7, #8] 8011f2e: f403 7340 and.w r3, r3, #768 @ 0x300 8011f32: f5b3 7f00 cmp.w r3, #512 @ 0x200 8011f36: d109 bne.n 8011f4c 8011f38: 4b1a ldr r3, [pc, #104] @ (8011fa4 ) 8011f3a: 6a5b ldr r3, [r3, #36] @ 0x24 8011f3c: f003 0302 and.w r3, r3, #2 8011f40: 2b00 cmp r3, #0 8011f42: d003 beq.n 8011f4c { frequency = LSI_VALUE; 8011f44: f649 4340 movw r3, #40000 @ 0x9c40 8011f48: 623b str r3, [r7, #32] 8011f4a: e00e b.n 8011f6a } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 8011f4c: 68bb ldr r3, [r7, #8] 8011f4e: f403 7340 and.w r3, r3, #768 @ 0x300 8011f52: f5b3 7f40 cmp.w r3, #768 @ 0x300 8011f56: d11f bne.n 8011f98 8011f58: 4b12 ldr r3, [pc, #72] @ (8011fa4 ) 8011f5a: 681b ldr r3, [r3, #0] 8011f5c: f403 3300 and.w r3, r3, #131072 @ 0x20000 8011f60: 2b00 cmp r3, #0 8011f62: d019 beq.n 8011f98 { frequency = HSE_VALUE / 128U; 8011f64: 4b15 ldr r3, [pc, #84] @ (8011fbc ) 8011f66: 623b str r3, [r7, #32] /* Clock not enabled for RTC*/ else { /* nothing to do: frequency already initialized to 0U */ } break; 8011f68: e016 b.n 8011f98 8011f6a: e015 b.n 8011f98 } case RCC_PERIPHCLK_ADC: { frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 8011f6c: f7ff fd72 bl 8011a54 8011f70: 4602 mov r2, r0 8011f72: 4b0c ldr r3, [pc, #48] @ (8011fa4 ) 8011f74: 685b ldr r3, [r3, #4] 8011f76: 0b9b lsrs r3, r3, #14 8011f78: f003 0303 and.w r3, r3, #3 8011f7c: 3301 adds r3, #1 8011f7e: 005b lsls r3, r3, #1 8011f80: fbb2 f3f3 udiv r3, r2, r3 8011f84: 623b str r3, [r7, #32] break; 8011f86: e008 b.n 8011f9a } default: { break; 8011f88: bf00 nop 8011f8a: e006 b.n 8011f9a break; 8011f8c: bf00 nop 8011f8e: e004 b.n 8011f9a break; 8011f90: bf00 nop 8011f92: e002 b.n 8011f9a break; 8011f94: bf00 nop 8011f96: e000 b.n 8011f9a break; 8011f98: bf00 nop } } return (frequency); 8011f9a: 6a3b ldr r3, [r7, #32] } 8011f9c: 4618 mov r0, r3 8011f9e: 3728 adds r7, #40 @ 0x28 8011fa0: 46bd mov sp, r7 8011fa2: bd80 pop {r7, pc} 8011fa4: 40021000 .word 0x40021000 8011fa8: 08017d9c .word 0x08017d9c 8011fac: 08017dac .word 0x08017dac 8011fb0: 017d7840 .word 0x017d7840 8011fb4: 003d0900 .word 0x003d0900 8011fb8: aaaaaaab .word 0xaaaaaaab 8011fbc: 0002faf0 .word 0x0002faf0 08011fc0 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { 8011fc0: b580 push {r7, lr} 8011fc2: b084 sub sp, #16 8011fc4: af00 add r7, sp, #0 8011fc6: 6078 str r0, [r7, #4] uint32_t prescaler = 0U; 8011fc8: 2300 movs r3, #0 8011fca: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8011fcc: 687b ldr r3, [r7, #4] 8011fce: 2b00 cmp r3, #0 8011fd0: d101 bne.n 8011fd6 { return HAL_ERROR; 8011fd2: 2301 movs r3, #1 8011fd4: e07a b.n 80120cc { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else if (hrtc->State == HAL_RTC_STATE_RESET) 8011fd6: 687b ldr r3, [r7, #4] 8011fd8: 7c5b ldrb r3, [r3, #17] 8011fda: b2db uxtb r3, r3 8011fdc: 2b00 cmp r3, #0 8011fde: d105 bne.n 8011fec { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; 8011fe0: 687b ldr r3, [r7, #4] 8011fe2: 2200 movs r2, #0 8011fe4: 741a strb r2, [r3, #16] /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); 8011fe6: 6878 ldr r0, [r7, #4] 8011fe8: f7f9 ffb6 bl 800bf58 } #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; 8011fec: 687b ldr r3, [r7, #4] 8011fee: 2202 movs r2, #2 8011ff0: 745a strb r2, [r3, #17] /* Waiting for synchro */ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 8011ff2: 6878 ldr r0, [r7, #4] 8011ff4: f000 f870 bl 80120d8 8011ff8: 4603 mov r3, r0 8011ffa: 2b00 cmp r3, #0 8011ffc: d004 beq.n 8012008 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8011ffe: 687b ldr r3, [r7, #4] 8012000: 2204 movs r2, #4 8012002: 745a strb r2, [r3, #17] return HAL_ERROR; 8012004: 2301 movs r3, #1 8012006: e061 b.n 80120cc } /* Set Initialization mode */ if (RTC_EnterInitMode(hrtc) != HAL_OK) 8012008: 6878 ldr r0, [r7, #4] 801200a: f000 f892 bl 8012132 801200e: 4603 mov r3, r0 8012010: 2b00 cmp r3, #0 8012012: d004 beq.n 801201e { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8012014: 687b ldr r3, [r7, #4] 8012016: 2204 movs r2, #4 8012018: 745a strb r2, [r3, #17] return HAL_ERROR; 801201a: 2301 movs r3, #1 801201c: e056 b.n 80120cc } else { /* Clear Flags Bits */ CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); 801201e: 687b ldr r3, [r7, #4] 8012020: 681b ldr r3, [r3, #0] 8012022: 685a ldr r2, [r3, #4] 8012024: 687b ldr r3, [r7, #4] 8012026: 681b ldr r3, [r3, #0] 8012028: f022 0207 bic.w r2, r2, #7 801202c: 605a str r2, [r3, #4] if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) 801202e: 687b ldr r3, [r7, #4] 8012030: 689b ldr r3, [r3, #8] 8012032: 2b00 cmp r3, #0 8012034: d005 beq.n 8012042 { /* Disable the selected Tamper pin */ CLEAR_BIT(BKP->CR, BKP_CR_TPE); 8012036: 4b27 ldr r3, [pc, #156] @ (80120d4 ) 8012038: 6b1b ldr r3, [r3, #48] @ 0x30 801203a: 4a26 ldr r2, [pc, #152] @ (80120d4 ) 801203c: f023 0301 bic.w r3, r3, #1 8012040: 6313 str r3, [r2, #48] @ 0x30 } /* Set the signal which will be routed to RTC Tamper pin*/ MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); 8012042: 4b24 ldr r3, [pc, #144] @ (80120d4 ) 8012044: 6adb ldr r3, [r3, #44] @ 0x2c 8012046: f423 7260 bic.w r2, r3, #896 @ 0x380 801204a: 687b ldr r3, [r7, #4] 801204c: 689b ldr r3, [r3, #8] 801204e: 4921 ldr r1, [pc, #132] @ (80120d4 ) 8012050: 4313 orrs r3, r2 8012052: 62cb str r3, [r1, #44] @ 0x2c if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) 8012054: 687b ldr r3, [r7, #4] 8012056: 685b ldr r3, [r3, #4] 8012058: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801205c: d003 beq.n 8012066 { /* RTC Prescaler provided directly by end-user*/ prescaler = hrtc->Init.AsynchPrediv; 801205e: 687b ldr r3, [r7, #4] 8012060: 685b ldr r3, [r3, #4] 8012062: 60fb str r3, [r7, #12] 8012064: e00e b.n 8012084 } else { /* RTC Prescaler will be automatically calculated to get 1 second timebase */ /* Get the RTCCLK frequency */ prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); 8012066: 2001 movs r0, #1 8012068: f7ff fe58 bl 8011d1c 801206c: 60f8 str r0, [r7, #12] /* Check that RTC clock is enabled*/ if (prescaler == 0U) 801206e: 68fb ldr r3, [r7, #12] 8012070: 2b00 cmp r3, #0 8012072: d104 bne.n 801207e { /* Should not happen. Frequency is not available*/ hrtc->State = HAL_RTC_STATE_ERROR; 8012074: 687b ldr r3, [r7, #4] 8012076: 2204 movs r2, #4 8012078: 745a strb r2, [r3, #17] return HAL_ERROR; 801207a: 2301 movs r3, #1 801207c: e026 b.n 80120cc } else { /* RTC period = RTCCLK/(RTC_PR + 1) */ prescaler = prescaler - 1U; 801207e: 68fb ldr r3, [r7, #12] 8012080: 3b01 subs r3, #1 8012082: 60fb str r3, [r7, #12] } } /* Configure the RTC_PRLH / RTC_PRLL */ WRITE_REG(hrtc->Instance->PRLH, ((prescaler >> 16U) & RTC_PRLH_PRL)); 8012084: 68fb ldr r3, [r7, #12] 8012086: 0c1a lsrs r2, r3, #16 8012088: 687b ldr r3, [r7, #4] 801208a: 681b ldr r3, [r3, #0] 801208c: f002 020f and.w r2, r2, #15 8012090: 609a str r2, [r3, #8] WRITE_REG(hrtc->Instance->PRLL, (prescaler & RTC_PRLL_PRL)); 8012092: 687b ldr r3, [r7, #4] 8012094: 681b ldr r3, [r3, #0] 8012096: 68fa ldr r2, [r7, #12] 8012098: b292 uxth r2, r2 801209a: 60da str r2, [r3, #12] /* Wait for synchro */ if (RTC_ExitInitMode(hrtc) != HAL_OK) 801209c: 6878 ldr r0, [r7, #4] 801209e: f000 f870 bl 8012182 80120a2: 4603 mov r3, r0 80120a4: 2b00 cmp r3, #0 80120a6: d004 beq.n 80120b2 { hrtc->State = HAL_RTC_STATE_ERROR; 80120a8: 687b ldr r3, [r7, #4] 80120aa: 2204 movs r2, #4 80120ac: 745a strb r2, [r3, #17] return HAL_ERROR; 80120ae: 2301 movs r3, #1 80120b0: e00c b.n 80120cc } /* Initialize date to 1st of January 2000 */ hrtc->DateToUpdate.Year = 0x00U; 80120b2: 687b ldr r3, [r7, #4] 80120b4: 2200 movs r2, #0 80120b6: 73da strb r2, [r3, #15] hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; 80120b8: 687b ldr r3, [r7, #4] 80120ba: 2201 movs r2, #1 80120bc: 735a strb r2, [r3, #13] hrtc->DateToUpdate.Date = 0x01U; 80120be: 687b ldr r3, [r7, #4] 80120c0: 2201 movs r2, #1 80120c2: 739a strb r2, [r3, #14] /* Set RTC state */ hrtc->State = HAL_RTC_STATE_READY; 80120c4: 687b ldr r3, [r7, #4] 80120c6: 2201 movs r2, #1 80120c8: 745a strb r2, [r3, #17] return HAL_OK; 80120ca: 2300 movs r3, #0 } } 80120cc: 4618 mov r0, r3 80120ce: 3710 adds r7, #16 80120d0: 46bd mov sp, r7 80120d2: bd80 pop {r7, pc} 80120d4: 40006c00 .word 0x40006c00 080120d8 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { 80120d8: b580 push {r7, lr} 80120da: b084 sub sp, #16 80120dc: af00 add r7, sp, #0 80120de: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80120e0: 2300 movs r3, #0 80120e2: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 80120e4: 687b ldr r3, [r7, #4] 80120e6: 2b00 cmp r3, #0 80120e8: d101 bne.n 80120ee { return HAL_ERROR; 80120ea: 2301 movs r3, #1 80120ec: e01d b.n 801212a } /* Clear RSF flag */ CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); 80120ee: 687b ldr r3, [r7, #4] 80120f0: 681b ldr r3, [r3, #0] 80120f2: 685a ldr r2, [r3, #4] 80120f4: 687b ldr r3, [r7, #4] 80120f6: 681b ldr r3, [r3, #0] 80120f8: f022 0208 bic.w r2, r2, #8 80120fc: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 80120fe: f7fc fb43 bl 800e788 8012102: 60f8 str r0, [r7, #12] /* Wait the registers to be synchronised */ while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8012104: e009 b.n 801211a { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8012106: f7fc fb3f bl 800e788 801210a: 4602 mov r2, r0 801210c: 68fb ldr r3, [r7, #12] 801210e: 1ad3 subs r3, r2, r3 8012110: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8012114: d901 bls.n 801211a { return HAL_TIMEOUT; 8012116: 2303 movs r3, #3 8012118: e007 b.n 801212a while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 801211a: 687b ldr r3, [r7, #4] 801211c: 681b ldr r3, [r3, #0] 801211e: 685b ldr r3, [r3, #4] 8012120: f003 0308 and.w r3, r3, #8 8012124: 2b00 cmp r3, #0 8012126: d0ee beq.n 8012106 } } return HAL_OK; 8012128: 2300 movs r3, #0 } 801212a: 4618 mov r0, r3 801212c: 3710 adds r7, #16 801212e: 46bd mov sp, r7 8012130: bd80 pop {r7, pc} 08012132 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { 8012132: b580 push {r7, lr} 8012134: b084 sub sp, #16 8012136: af00 add r7, sp, #0 8012138: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 801213a: 2300 movs r3, #0 801213c: 60fb str r3, [r7, #12] tickstart = HAL_GetTick(); 801213e: f7fc fb23 bl 800e788 8012142: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8012144: e009 b.n 801215a { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8012146: f7fc fb1f bl 800e788 801214a: 4602 mov r2, r0 801214c: 68fb ldr r3, [r7, #12] 801214e: 1ad3 subs r3, r2, r3 8012150: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8012154: d901 bls.n 801215a { return HAL_TIMEOUT; 8012156: 2303 movs r3, #3 8012158: e00f b.n 801217a while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 801215a: 687b ldr r3, [r7, #4] 801215c: 681b ldr r3, [r3, #0] 801215e: 685b ldr r3, [r3, #4] 8012160: f003 0320 and.w r3, r3, #32 8012164: 2b00 cmp r3, #0 8012166: d0ee beq.n 8012146 } } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 8012168: 687b ldr r3, [r7, #4] 801216a: 681b ldr r3, [r3, #0] 801216c: 685a ldr r2, [r3, #4] 801216e: 687b ldr r3, [r7, #4] 8012170: 681b ldr r3, [r3, #0] 8012172: f042 0210 orr.w r2, r2, #16 8012176: 605a str r2, [r3, #4] return HAL_OK; 8012178: 2300 movs r3, #0 } 801217a: 4618 mov r0, r3 801217c: 3710 adds r7, #16 801217e: 46bd mov sp, r7 8012180: bd80 pop {r7, pc} 08012182 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) { 8012182: b580 push {r7, lr} 8012184: b084 sub sp, #16 8012186: af00 add r7, sp, #0 8012188: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 801218a: 2300 movs r3, #0 801218c: 60fb str r3, [r7, #12] /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 801218e: 687b ldr r3, [r7, #4] 8012190: 681b ldr r3, [r3, #0] 8012192: 685a ldr r2, [r3, #4] 8012194: 687b ldr r3, [r7, #4] 8012196: 681b ldr r3, [r3, #0] 8012198: f022 0210 bic.w r2, r2, #16 801219c: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 801219e: f7fc faf3 bl 800e788 80121a2: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 80121a4: e009 b.n 80121ba { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 80121a6: f7fc faef bl 800e788 80121aa: 4602 mov r2, r0 80121ac: 68fb ldr r3, [r7, #12] 80121ae: 1ad3 subs r3, r2, r3 80121b0: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 80121b4: d901 bls.n 80121ba { return HAL_TIMEOUT; 80121b6: 2303 movs r3, #3 80121b8: e007 b.n 80121ca while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 80121ba: 687b ldr r3, [r7, #4] 80121bc: 681b ldr r3, [r3, #0] 80121be: 685b ldr r3, [r3, #4] 80121c0: f003 0320 and.w r3, r3, #32 80121c4: 2b00 cmp r3, #0 80121c6: d0ee beq.n 80121a6 } } return HAL_OK; 80121c8: 2300 movs r3, #0 } 80121ca: 4618 mov r0, r3 80121cc: 3710 adds r7, #16 80121ce: 46bd mov sp, r7 80121d0: bd80 pop {r7, pc} 080121d2 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 80121d2: b580 push {r7, lr} 80121d4: b082 sub sp, #8 80121d6: af00 add r7, sp, #0 80121d8: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 80121da: 687b ldr r3, [r7, #4] 80121dc: 2b00 cmp r3, #0 80121de: d101 bne.n 80121e4 { return HAL_ERROR; 80121e0: 2301 movs r3, #1 80121e2: e041 b.n 8012268 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 80121e4: 687b ldr r3, [r7, #4] 80121e6: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 80121ea: b2db uxtb r3, r3 80121ec: 2b00 cmp r3, #0 80121ee: d106 bne.n 80121fe { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 80121f0: 687b ldr r3, [r7, #4] 80121f2: 2200 movs r2, #0 80121f4: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 80121f8: 6878 ldr r0, [r7, #4] 80121fa: f7fb ff01 bl 800e000 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80121fe: 687b ldr r3, [r7, #4] 8012200: 2202 movs r2, #2 8012202: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8012206: 687b ldr r3, [r7, #4] 8012208: 681a ldr r2, [r3, #0] 801220a: 687b ldr r3, [r7, #4] 801220c: 3304 adds r3, #4 801220e: 4619 mov r1, r3 8012210: 4610 mov r0, r2 8012212: f000 fd33 bl 8012c7c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8012216: 687b ldr r3, [r7, #4] 8012218: 2201 movs r2, #1 801221a: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 801221e: 687b ldr r3, [r7, #4] 8012220: 2201 movs r2, #1 8012222: f883 203e strb.w r2, [r3, #62] @ 0x3e 8012226: 687b ldr r3, [r7, #4] 8012228: 2201 movs r2, #1 801222a: f883 203f strb.w r2, [r3, #63] @ 0x3f 801222e: 687b ldr r3, [r7, #4] 8012230: 2201 movs r2, #1 8012232: f883 2040 strb.w r2, [r3, #64] @ 0x40 8012236: 687b ldr r3, [r7, #4] 8012238: 2201 movs r2, #1 801223a: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 801223e: 687b ldr r3, [r7, #4] 8012240: 2201 movs r2, #1 8012242: f883 2042 strb.w r2, [r3, #66] @ 0x42 8012246: 687b ldr r3, [r7, #4] 8012248: 2201 movs r2, #1 801224a: f883 2043 strb.w r2, [r3, #67] @ 0x43 801224e: 687b ldr r3, [r7, #4] 8012250: 2201 movs r2, #1 8012252: f883 2044 strb.w r2, [r3, #68] @ 0x44 8012256: 687b ldr r3, [r7, #4] 8012258: 2201 movs r2, #1 801225a: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 801225e: 687b ldr r3, [r7, #4] 8012260: 2201 movs r2, #1 8012262: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8012266: 2300 movs r3, #0 } 8012268: 4618 mov r0, r3 801226a: 3708 adds r7, #8 801226c: 46bd mov sp, r7 801226e: bd80 pop {r7, pc} 08012270 : * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { 8012270: b580 push {r7, lr} 8012272: b082 sub sp, #8 8012274: af00 add r7, sp, #0 8012276: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8012278: 687b ldr r3, [r7, #4] 801227a: 2b00 cmp r3, #0 801227c: d101 bne.n 8012282 { return HAL_ERROR; 801227e: 2301 movs r3, #1 8012280: e041 b.n 8012306 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8012282: 687b ldr r3, [r7, #4] 8012284: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8012288: b2db uxtb r3, r3 801228a: 2b00 cmp r3, #0 801228c: d106 bne.n 801229c { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 801228e: 687b ldr r3, [r7, #4] 8012290: 2200 movs r2, #0 8012292: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); 8012296: 6878 ldr r0, [r7, #4] 8012298: f000 f839 bl 801230e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 801229c: 687b ldr r3, [r7, #4] 801229e: 2202 movs r2, #2 80122a0: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 80122a4: 687b ldr r3, [r7, #4] 80122a6: 681a ldr r2, [r3, #0] 80122a8: 687b ldr r3, [r7, #4] 80122aa: 3304 adds r3, #4 80122ac: 4619 mov r1, r3 80122ae: 4610 mov r0, r2 80122b0: f000 fce4 bl 8012c7c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 80122b4: 687b ldr r3, [r7, #4] 80122b6: 2201 movs r2, #1 80122b8: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80122bc: 687b ldr r3, [r7, #4] 80122be: 2201 movs r2, #1 80122c0: f883 203e strb.w r2, [r3, #62] @ 0x3e 80122c4: 687b ldr r3, [r7, #4] 80122c6: 2201 movs r2, #1 80122c8: f883 203f strb.w r2, [r3, #63] @ 0x3f 80122cc: 687b ldr r3, [r7, #4] 80122ce: 2201 movs r2, #1 80122d0: f883 2040 strb.w r2, [r3, #64] @ 0x40 80122d4: 687b ldr r3, [r7, #4] 80122d6: 2201 movs r2, #1 80122d8: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80122dc: 687b ldr r3, [r7, #4] 80122de: 2201 movs r2, #1 80122e0: f883 2042 strb.w r2, [r3, #66] @ 0x42 80122e4: 687b ldr r3, [r7, #4] 80122e6: 2201 movs r2, #1 80122e8: f883 2043 strb.w r2, [r3, #67] @ 0x43 80122ec: 687b ldr r3, [r7, #4] 80122ee: 2201 movs r2, #1 80122f0: f883 2044 strb.w r2, [r3, #68] @ 0x44 80122f4: 687b ldr r3, [r7, #4] 80122f6: 2201 movs r2, #1 80122f8: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80122fc: 687b ldr r3, [r7, #4] 80122fe: 2201 movs r2, #1 8012300: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8012304: 2300 movs r3, #0 } 8012306: 4618 mov r0, r3 8012308: 3708 adds r7, #8 801230a: 46bd mov sp, r7 801230c: bd80 pop {r7, pc} 0801230e : * @brief Initializes the TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) { 801230e: b480 push {r7} 8012310: b083 sub sp, #12 8012312: af00 add r7, sp, #0 8012314: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspInit could be implemented in the user file */ } 8012316: bf00 nop 8012318: 370c adds r7, #12 801231a: 46bd mov sp, r7 801231c: bc80 pop {r7} 801231e: 4770 bx lr 08012320 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8012320: b580 push {r7, lr} 8012322: b084 sub sp, #16 8012324: af00 add r7, sp, #0 8012326: 6078 str r0, [r7, #4] 8012328: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 801232a: 683b ldr r3, [r7, #0] 801232c: 2b00 cmp r3, #0 801232e: d109 bne.n 8012344 8012330: 687b ldr r3, [r7, #4] 8012332: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8012336: b2db uxtb r3, r3 8012338: 2b01 cmp r3, #1 801233a: bf14 ite ne 801233c: 2301 movne r3, #1 801233e: 2300 moveq r3, #0 8012340: b2db uxtb r3, r3 8012342: e022 b.n 801238a 8012344: 683b ldr r3, [r7, #0] 8012346: 2b04 cmp r3, #4 8012348: d109 bne.n 801235e 801234a: 687b ldr r3, [r7, #4] 801234c: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8012350: b2db uxtb r3, r3 8012352: 2b01 cmp r3, #1 8012354: bf14 ite ne 8012356: 2301 movne r3, #1 8012358: 2300 moveq r3, #0 801235a: b2db uxtb r3, r3 801235c: e015 b.n 801238a 801235e: 683b ldr r3, [r7, #0] 8012360: 2b08 cmp r3, #8 8012362: d109 bne.n 8012378 8012364: 687b ldr r3, [r7, #4] 8012366: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 801236a: b2db uxtb r3, r3 801236c: 2b01 cmp r3, #1 801236e: bf14 ite ne 8012370: 2301 movne r3, #1 8012372: 2300 moveq r3, #0 8012374: b2db uxtb r3, r3 8012376: e008 b.n 801238a 8012378: 687b ldr r3, [r7, #4] 801237a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 801237e: b2db uxtb r3, r3 8012380: 2b01 cmp r3, #1 8012382: bf14 ite ne 8012384: 2301 movne r3, #1 8012386: 2300 moveq r3, #0 8012388: b2db uxtb r3, r3 801238a: 2b00 cmp r3, #0 801238c: d001 beq.n 8012392 { return HAL_ERROR; 801238e: 2301 movs r3, #1 8012390: e063 b.n 801245a } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8012392: 683b ldr r3, [r7, #0] 8012394: 2b00 cmp r3, #0 8012396: d104 bne.n 80123a2 8012398: 687b ldr r3, [r7, #4] 801239a: 2202 movs r2, #2 801239c: f883 203e strb.w r2, [r3, #62] @ 0x3e 80123a0: e013 b.n 80123ca 80123a2: 683b ldr r3, [r7, #0] 80123a4: 2b04 cmp r3, #4 80123a6: d104 bne.n 80123b2 80123a8: 687b ldr r3, [r7, #4] 80123aa: 2202 movs r2, #2 80123ac: f883 203f strb.w r2, [r3, #63] @ 0x3f 80123b0: e00b b.n 80123ca 80123b2: 683b ldr r3, [r7, #0] 80123b4: 2b08 cmp r3, #8 80123b6: d104 bne.n 80123c2 80123b8: 687b ldr r3, [r7, #4] 80123ba: 2202 movs r2, #2 80123bc: f883 2040 strb.w r2, [r3, #64] @ 0x40 80123c0: e003 b.n 80123ca 80123c2: 687b ldr r3, [r7, #4] 80123c4: 2202 movs r2, #2 80123c6: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 80123ca: 687b ldr r3, [r7, #4] 80123cc: 681b ldr r3, [r3, #0] 80123ce: 2201 movs r2, #1 80123d0: 6839 ldr r1, [r7, #0] 80123d2: 4618 mov r0, r3 80123d4: f000 fee8 bl 80131a8 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 80123d8: 687b ldr r3, [r7, #4] 80123da: 681b ldr r3, [r3, #0] 80123dc: 4a21 ldr r2, [pc, #132] @ (8012464 ) 80123de: 4293 cmp r3, r2 80123e0: d107 bne.n 80123f2 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 80123e2: 687b ldr r3, [r7, #4] 80123e4: 681b ldr r3, [r3, #0] 80123e6: 6c5a ldr r2, [r3, #68] @ 0x44 80123e8: 687b ldr r3, [r7, #4] 80123ea: 681b ldr r3, [r3, #0] 80123ec: f442 4200 orr.w r2, r2, #32768 @ 0x8000 80123f0: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80123f2: 687b ldr r3, [r7, #4] 80123f4: 681b ldr r3, [r3, #0] 80123f6: 4a1b ldr r2, [pc, #108] @ (8012464 ) 80123f8: 4293 cmp r3, r2 80123fa: d013 beq.n 8012424 80123fc: 687b ldr r3, [r7, #4] 80123fe: 681b ldr r3, [r3, #0] 8012400: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8012404: d00e beq.n 8012424 8012406: 687b ldr r3, [r7, #4] 8012408: 681b ldr r3, [r3, #0] 801240a: 4a17 ldr r2, [pc, #92] @ (8012468 ) 801240c: 4293 cmp r3, r2 801240e: d009 beq.n 8012424 8012410: 687b ldr r3, [r7, #4] 8012412: 681b ldr r3, [r3, #0] 8012414: 4a15 ldr r2, [pc, #84] @ (801246c ) 8012416: 4293 cmp r3, r2 8012418: d004 beq.n 8012424 801241a: 687b ldr r3, [r7, #4] 801241c: 681b ldr r3, [r3, #0] 801241e: 4a14 ldr r2, [pc, #80] @ (8012470 ) 8012420: 4293 cmp r3, r2 8012422: d111 bne.n 8012448 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8012424: 687b ldr r3, [r7, #4] 8012426: 681b ldr r3, [r3, #0] 8012428: 689b ldr r3, [r3, #8] 801242a: f003 0307 and.w r3, r3, #7 801242e: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8012430: 68fb ldr r3, [r7, #12] 8012432: 2b06 cmp r3, #6 8012434: d010 beq.n 8012458 { __HAL_TIM_ENABLE(htim); 8012436: 687b ldr r3, [r7, #4] 8012438: 681b ldr r3, [r3, #0] 801243a: 681a ldr r2, [r3, #0] 801243c: 687b ldr r3, [r7, #4] 801243e: 681b ldr r3, [r3, #0] 8012440: f042 0201 orr.w r2, r2, #1 8012444: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8012446: e007 b.n 8012458 } } else { __HAL_TIM_ENABLE(htim); 8012448: 687b ldr r3, [r7, #4] 801244a: 681b ldr r3, [r3, #0] 801244c: 681a ldr r2, [r3, #0] 801244e: 687b ldr r3, [r7, #4] 8012450: 681b ldr r3, [r3, #0] 8012452: f042 0201 orr.w r2, r2, #1 8012456: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8012458: 2300 movs r3, #0 } 801245a: 4618 mov r0, r3 801245c: 3710 adds r7, #16 801245e: 46bd mov sp, r7 8012460: bd80 pop {r7, pc} 8012462: bf00 nop 8012464: 40012c00 .word 0x40012c00 8012468: 40000400 .word 0x40000400 801246c: 40000800 .word 0x40000800 8012470: 40000c00 .word 0x40000c00 08012474 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 8012474: b580 push {r7, lr} 8012476: b082 sub sp, #8 8012478: af00 add r7, sp, #0 801247a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 801247c: 687b ldr r3, [r7, #4] 801247e: 2b00 cmp r3, #0 8012480: d101 bne.n 8012486 { return HAL_ERROR; 8012482: 2301 movs r3, #1 8012484: e041 b.n 801250a assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8012486: 687b ldr r3, [r7, #4] 8012488: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 801248c: b2db uxtb r3, r3 801248e: 2b00 cmp r3, #0 8012490: d106 bne.n 80124a0 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8012492: 687b ldr r3, [r7, #4] 8012494: 2200 movs r2, #0 8012496: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 801249a: 6878 ldr r0, [r7, #4] 801249c: f000 f839 bl 8012512 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80124a0: 687b ldr r3, [r7, #4] 80124a2: 2202 movs r2, #2 80124a4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 80124a8: 687b ldr r3, [r7, #4] 80124aa: 681a ldr r2, [r3, #0] 80124ac: 687b ldr r3, [r7, #4] 80124ae: 3304 adds r3, #4 80124b0: 4619 mov r1, r3 80124b2: 4610 mov r0, r2 80124b4: f000 fbe2 bl 8012c7c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 80124b8: 687b ldr r3, [r7, #4] 80124ba: 2201 movs r2, #1 80124bc: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80124c0: 687b ldr r3, [r7, #4] 80124c2: 2201 movs r2, #1 80124c4: f883 203e strb.w r2, [r3, #62] @ 0x3e 80124c8: 687b ldr r3, [r7, #4] 80124ca: 2201 movs r2, #1 80124cc: f883 203f strb.w r2, [r3, #63] @ 0x3f 80124d0: 687b ldr r3, [r7, #4] 80124d2: 2201 movs r2, #1 80124d4: f883 2040 strb.w r2, [r3, #64] @ 0x40 80124d8: 687b ldr r3, [r7, #4] 80124da: 2201 movs r2, #1 80124dc: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80124e0: 687b ldr r3, [r7, #4] 80124e2: 2201 movs r2, #1 80124e4: f883 2042 strb.w r2, [r3, #66] @ 0x42 80124e8: 687b ldr r3, [r7, #4] 80124ea: 2201 movs r2, #1 80124ec: f883 2043 strb.w r2, [r3, #67] @ 0x43 80124f0: 687b ldr r3, [r7, #4] 80124f2: 2201 movs r2, #1 80124f4: f883 2044 strb.w r2, [r3, #68] @ 0x44 80124f8: 687b ldr r3, [r7, #4] 80124fa: 2201 movs r2, #1 80124fc: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8012500: 687b ldr r3, [r7, #4] 8012502: 2201 movs r2, #1 8012504: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8012508: 2300 movs r3, #0 } 801250a: 4618 mov r0, r3 801250c: 3708 adds r7, #8 801250e: 46bd mov sp, r7 8012510: bd80 pop {r7, pc} 08012512 : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 8012512: b480 push {r7} 8012514: b083 sub sp, #12 8012516: af00 add r7, sp, #0 8012518: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 801251a: bf00 nop 801251c: 370c adds r7, #12 801251e: 46bd mov sp, r7 8012520: bc80 pop {r7} 8012522: 4770 bx lr 08012524 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8012524: b580 push {r7, lr} 8012526: b084 sub sp, #16 8012528: af00 add r7, sp, #0 801252a: 6078 str r0, [r7, #4] 801252c: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 801252e: 683b ldr r3, [r7, #0] 8012530: 2b00 cmp r3, #0 8012532: d109 bne.n 8012548 8012534: 687b ldr r3, [r7, #4] 8012536: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 801253a: b2db uxtb r3, r3 801253c: 2b01 cmp r3, #1 801253e: bf14 ite ne 8012540: 2301 movne r3, #1 8012542: 2300 moveq r3, #0 8012544: b2db uxtb r3, r3 8012546: e022 b.n 801258e 8012548: 683b ldr r3, [r7, #0] 801254a: 2b04 cmp r3, #4 801254c: d109 bne.n 8012562 801254e: 687b ldr r3, [r7, #4] 8012550: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8012554: b2db uxtb r3, r3 8012556: 2b01 cmp r3, #1 8012558: bf14 ite ne 801255a: 2301 movne r3, #1 801255c: 2300 moveq r3, #0 801255e: b2db uxtb r3, r3 8012560: e015 b.n 801258e 8012562: 683b ldr r3, [r7, #0] 8012564: 2b08 cmp r3, #8 8012566: d109 bne.n 801257c 8012568: 687b ldr r3, [r7, #4] 801256a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 801256e: b2db uxtb r3, r3 8012570: 2b01 cmp r3, #1 8012572: bf14 ite ne 8012574: 2301 movne r3, #1 8012576: 2300 moveq r3, #0 8012578: b2db uxtb r3, r3 801257a: e008 b.n 801258e 801257c: 687b ldr r3, [r7, #4] 801257e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8012582: b2db uxtb r3, r3 8012584: 2b01 cmp r3, #1 8012586: bf14 ite ne 8012588: 2301 movne r3, #1 801258a: 2300 moveq r3, #0 801258c: b2db uxtb r3, r3 801258e: 2b00 cmp r3, #0 8012590: d001 beq.n 8012596 { return HAL_ERROR; 8012592: 2301 movs r3, #1 8012594: e063 b.n 801265e } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8012596: 683b ldr r3, [r7, #0] 8012598: 2b00 cmp r3, #0 801259a: d104 bne.n 80125a6 801259c: 687b ldr r3, [r7, #4] 801259e: 2202 movs r2, #2 80125a0: f883 203e strb.w r2, [r3, #62] @ 0x3e 80125a4: e013 b.n 80125ce 80125a6: 683b ldr r3, [r7, #0] 80125a8: 2b04 cmp r3, #4 80125aa: d104 bne.n 80125b6 80125ac: 687b ldr r3, [r7, #4] 80125ae: 2202 movs r2, #2 80125b0: f883 203f strb.w r2, [r3, #63] @ 0x3f 80125b4: e00b b.n 80125ce 80125b6: 683b ldr r3, [r7, #0] 80125b8: 2b08 cmp r3, #8 80125ba: d104 bne.n 80125c6 80125bc: 687b ldr r3, [r7, #4] 80125be: 2202 movs r2, #2 80125c0: f883 2040 strb.w r2, [r3, #64] @ 0x40 80125c4: e003 b.n 80125ce 80125c6: 687b ldr r3, [r7, #4] 80125c8: 2202 movs r2, #2 80125ca: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 80125ce: 687b ldr r3, [r7, #4] 80125d0: 681b ldr r3, [r3, #0] 80125d2: 2201 movs r2, #1 80125d4: 6839 ldr r1, [r7, #0] 80125d6: 4618 mov r0, r3 80125d8: f000 fde6 bl 80131a8 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 80125dc: 687b ldr r3, [r7, #4] 80125de: 681b ldr r3, [r3, #0] 80125e0: 4a21 ldr r2, [pc, #132] @ (8012668 ) 80125e2: 4293 cmp r3, r2 80125e4: d107 bne.n 80125f6 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 80125e6: 687b ldr r3, [r7, #4] 80125e8: 681b ldr r3, [r3, #0] 80125ea: 6c5a ldr r2, [r3, #68] @ 0x44 80125ec: 687b ldr r3, [r7, #4] 80125ee: 681b ldr r3, [r3, #0] 80125f0: f442 4200 orr.w r2, r2, #32768 @ 0x8000 80125f4: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80125f6: 687b ldr r3, [r7, #4] 80125f8: 681b ldr r3, [r3, #0] 80125fa: 4a1b ldr r2, [pc, #108] @ (8012668 ) 80125fc: 4293 cmp r3, r2 80125fe: d013 beq.n 8012628 8012600: 687b ldr r3, [r7, #4] 8012602: 681b ldr r3, [r3, #0] 8012604: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8012608: d00e beq.n 8012628 801260a: 687b ldr r3, [r7, #4] 801260c: 681b ldr r3, [r3, #0] 801260e: 4a17 ldr r2, [pc, #92] @ (801266c ) 8012610: 4293 cmp r3, r2 8012612: d009 beq.n 8012628 8012614: 687b ldr r3, [r7, #4] 8012616: 681b ldr r3, [r3, #0] 8012618: 4a15 ldr r2, [pc, #84] @ (8012670 ) 801261a: 4293 cmp r3, r2 801261c: d004 beq.n 8012628 801261e: 687b ldr r3, [r7, #4] 8012620: 681b ldr r3, [r3, #0] 8012622: 4a14 ldr r2, [pc, #80] @ (8012674 ) 8012624: 4293 cmp r3, r2 8012626: d111 bne.n 801264c { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8012628: 687b ldr r3, [r7, #4] 801262a: 681b ldr r3, [r3, #0] 801262c: 689b ldr r3, [r3, #8] 801262e: f003 0307 and.w r3, r3, #7 8012632: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8012634: 68fb ldr r3, [r7, #12] 8012636: 2b06 cmp r3, #6 8012638: d010 beq.n 801265c { __HAL_TIM_ENABLE(htim); 801263a: 687b ldr r3, [r7, #4] 801263c: 681b ldr r3, [r3, #0] 801263e: 681a ldr r2, [r3, #0] 8012640: 687b ldr r3, [r7, #4] 8012642: 681b ldr r3, [r3, #0] 8012644: f042 0201 orr.w r2, r2, #1 8012648: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 801264a: e007 b.n 801265c } } else { __HAL_TIM_ENABLE(htim); 801264c: 687b ldr r3, [r7, #4] 801264e: 681b ldr r3, [r3, #0] 8012650: 681a ldr r2, [r3, #0] 8012652: 687b ldr r3, [r7, #4] 8012654: 681b ldr r3, [r3, #0] 8012656: f042 0201 orr.w r2, r2, #1 801265a: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 801265c: 2300 movs r3, #0 } 801265e: 4618 mov r0, r3 8012660: 3710 adds r7, #16 8012662: 46bd mov sp, r7 8012664: bd80 pop {r7, pc} 8012666: bf00 nop 8012668: 40012c00 .word 0x40012c00 801266c: 40000400 .word 0x40000400 8012670: 40000800 .word 0x40000800 8012674: 40000c00 .word 0x40000c00 08012678 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8012678: b580 push {r7, lr} 801267a: b084 sub sp, #16 801267c: af00 add r7, sp, #0 801267e: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 8012680: 687b ldr r3, [r7, #4] 8012682: 681b ldr r3, [r3, #0] 8012684: 68db ldr r3, [r3, #12] 8012686: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 8012688: 687b ldr r3, [r7, #4] 801268a: 681b ldr r3, [r3, #0] 801268c: 691b ldr r3, [r3, #16] 801268e: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 8012690: 68bb ldr r3, [r7, #8] 8012692: f003 0302 and.w r3, r3, #2 8012696: 2b00 cmp r3, #0 8012698: d020 beq.n 80126dc { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 801269a: 68fb ldr r3, [r7, #12] 801269c: f003 0302 and.w r3, r3, #2 80126a0: 2b00 cmp r3, #0 80126a2: d01b beq.n 80126dc { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 80126a4: 687b ldr r3, [r7, #4] 80126a6: 681b ldr r3, [r3, #0] 80126a8: f06f 0202 mvn.w r2, #2 80126ac: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 80126ae: 687b ldr r3, [r7, #4] 80126b0: 2201 movs r2, #1 80126b2: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 80126b4: 687b ldr r3, [r7, #4] 80126b6: 681b ldr r3, [r3, #0] 80126b8: 699b ldr r3, [r3, #24] 80126ba: f003 0303 and.w r3, r3, #3 80126be: 2b00 cmp r3, #0 80126c0: d003 beq.n 80126ca { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80126c2: 6878 ldr r0, [r7, #4] 80126c4: f000 fabf bl 8012c46 80126c8: e005 b.n 80126d6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80126ca: 6878 ldr r0, [r7, #4] 80126cc: f000 fab2 bl 8012c34 HAL_TIM_PWM_PulseFinishedCallback(htim); 80126d0: 6878 ldr r0, [r7, #4] 80126d2: f000 fac1 bl 8012c58 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80126d6: 687b ldr r3, [r7, #4] 80126d8: 2200 movs r2, #0 80126da: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 80126dc: 68bb ldr r3, [r7, #8] 80126de: f003 0304 and.w r3, r3, #4 80126e2: 2b00 cmp r3, #0 80126e4: d020 beq.n 8012728 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 80126e6: 68fb ldr r3, [r7, #12] 80126e8: f003 0304 and.w r3, r3, #4 80126ec: 2b00 cmp r3, #0 80126ee: d01b beq.n 8012728 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 80126f0: 687b ldr r3, [r7, #4] 80126f2: 681b ldr r3, [r3, #0] 80126f4: f06f 0204 mvn.w r2, #4 80126f8: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 80126fa: 687b ldr r3, [r7, #4] 80126fc: 2202 movs r2, #2 80126fe: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8012700: 687b ldr r3, [r7, #4] 8012702: 681b ldr r3, [r3, #0] 8012704: 699b ldr r3, [r3, #24] 8012706: f403 7340 and.w r3, r3, #768 @ 0x300 801270a: 2b00 cmp r3, #0 801270c: d003 beq.n 8012716 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 801270e: 6878 ldr r0, [r7, #4] 8012710: f000 fa99 bl 8012c46 8012714: e005 b.n 8012722 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8012716: 6878 ldr r0, [r7, #4] 8012718: f000 fa8c bl 8012c34 HAL_TIM_PWM_PulseFinishedCallback(htim); 801271c: 6878 ldr r0, [r7, #4] 801271e: f000 fa9b bl 8012c58 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8012722: 687b ldr r3, [r7, #4] 8012724: 2200 movs r2, #0 8012726: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 8012728: 68bb ldr r3, [r7, #8] 801272a: f003 0308 and.w r3, r3, #8 801272e: 2b00 cmp r3, #0 8012730: d020 beq.n 8012774 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 8012732: 68fb ldr r3, [r7, #12] 8012734: f003 0308 and.w r3, r3, #8 8012738: 2b00 cmp r3, #0 801273a: d01b beq.n 8012774 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 801273c: 687b ldr r3, [r7, #4] 801273e: 681b ldr r3, [r3, #0] 8012740: f06f 0208 mvn.w r2, #8 8012744: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8012746: 687b ldr r3, [r7, #4] 8012748: 2204 movs r2, #4 801274a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 801274c: 687b ldr r3, [r7, #4] 801274e: 681b ldr r3, [r3, #0] 8012750: 69db ldr r3, [r3, #28] 8012752: f003 0303 and.w r3, r3, #3 8012756: 2b00 cmp r3, #0 8012758: d003 beq.n 8012762 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 801275a: 6878 ldr r0, [r7, #4] 801275c: f000 fa73 bl 8012c46 8012760: e005 b.n 801276e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8012762: 6878 ldr r0, [r7, #4] 8012764: f000 fa66 bl 8012c34 HAL_TIM_PWM_PulseFinishedCallback(htim); 8012768: 6878 ldr r0, [r7, #4] 801276a: f000 fa75 bl 8012c58 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 801276e: 687b ldr r3, [r7, #4] 8012770: 2200 movs r2, #0 8012772: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 8012774: 68bb ldr r3, [r7, #8] 8012776: f003 0310 and.w r3, r3, #16 801277a: 2b00 cmp r3, #0 801277c: d020 beq.n 80127c0 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 801277e: 68fb ldr r3, [r7, #12] 8012780: f003 0310 and.w r3, r3, #16 8012784: 2b00 cmp r3, #0 8012786: d01b beq.n 80127c0 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 8012788: 687b ldr r3, [r7, #4] 801278a: 681b ldr r3, [r3, #0] 801278c: f06f 0210 mvn.w r2, #16 8012790: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8012792: 687b ldr r3, [r7, #4] 8012794: 2208 movs r2, #8 8012796: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8012798: 687b ldr r3, [r7, #4] 801279a: 681b ldr r3, [r3, #0] 801279c: 69db ldr r3, [r3, #28] 801279e: f403 7340 and.w r3, r3, #768 @ 0x300 80127a2: 2b00 cmp r3, #0 80127a4: d003 beq.n 80127ae { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80127a6: 6878 ldr r0, [r7, #4] 80127a8: f000 fa4d bl 8012c46 80127ac: e005 b.n 80127ba { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80127ae: 6878 ldr r0, [r7, #4] 80127b0: f000 fa40 bl 8012c34 HAL_TIM_PWM_PulseFinishedCallback(htim); 80127b4: 6878 ldr r0, [r7, #4] 80127b6: f000 fa4f bl 8012c58 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80127ba: 687b ldr r3, [r7, #4] 80127bc: 2200 movs r2, #0 80127be: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 80127c0: 68bb ldr r3, [r7, #8] 80127c2: f003 0301 and.w r3, r3, #1 80127c6: 2b00 cmp r3, #0 80127c8: d00c beq.n 80127e4 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 80127ca: 68fb ldr r3, [r7, #12] 80127cc: f003 0301 and.w r3, r3, #1 80127d0: 2b00 cmp r3, #0 80127d2: d007 beq.n 80127e4 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 80127d4: 687b ldr r3, [r7, #4] 80127d6: 681b ldr r3, [r3, #0] 80127d8: f06f 0201 mvn.w r2, #1 80127dc: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 80127de: 6878 ldr r0, [r7, #4] 80127e0: f000 fa1f bl 8012c22 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) 80127e4: 68bb ldr r3, [r7, #8] 80127e6: f003 0380 and.w r3, r3, #128 @ 0x80 80127ea: 2b00 cmp r3, #0 80127ec: d00c beq.n 8012808 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 80127ee: 68fb ldr r3, [r7, #12] 80127f0: f003 0380 and.w r3, r3, #128 @ 0x80 80127f4: 2b00 cmp r3, #0 80127f6: d007 beq.n 8012808 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); 80127f8: 687b ldr r3, [r7, #4] 80127fa: 681b ldr r3, [r3, #0] 80127fc: f06f 0280 mvn.w r2, #128 @ 0x80 8012800: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8012802: 6878 ldr r0, [r7, #4] 8012804: f000 fd63 bl 80132ce #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 8012808: 68bb ldr r3, [r7, #8] 801280a: f003 0340 and.w r3, r3, #64 @ 0x40 801280e: 2b00 cmp r3, #0 8012810: d00c beq.n 801282c { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 8012812: 68fb ldr r3, [r7, #12] 8012814: f003 0340 and.w r3, r3, #64 @ 0x40 8012818: 2b00 cmp r3, #0 801281a: d007 beq.n 801282c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 801281c: 687b ldr r3, [r7, #4] 801281e: 681b ldr r3, [r3, #0] 8012820: f06f 0240 mvn.w r2, #64 @ 0x40 8012824: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 8012826: 6878 ldr r0, [r7, #4] 8012828: f000 fa1f bl 8012c6a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 801282c: 68bb ldr r3, [r7, #8] 801282e: f003 0320 and.w r3, r3, #32 8012832: 2b00 cmp r3, #0 8012834: d00c beq.n 8012850 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 8012836: 68fb ldr r3, [r7, #12] 8012838: f003 0320 and.w r3, r3, #32 801283c: 2b00 cmp r3, #0 801283e: d007 beq.n 8012850 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 8012840: 687b ldr r3, [r7, #4] 8012842: 681b ldr r3, [r3, #0] 8012844: f06f 0220 mvn.w r2, #32 8012848: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 801284a: 6878 ldr r0, [r7, #4] 801284c: f000 fd36 bl 80132bc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8012850: bf00 nop 8012852: 3710 adds r7, #16 8012854: 46bd mov sp, r7 8012856: bd80 pop {r7, pc} 08012858 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8012858: b580 push {r7, lr} 801285a: b086 sub sp, #24 801285c: af00 add r7, sp, #0 801285e: 60f8 str r0, [r7, #12] 8012860: 60b9 str r1, [r7, #8] 8012862: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8012864: 2300 movs r3, #0 8012866: 75fb strb r3, [r7, #23] assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); 8012868: 68fb ldr r3, [r7, #12] 801286a: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 801286e: 2b01 cmp r3, #1 8012870: d101 bne.n 8012876 8012872: 2302 movs r3, #2 8012874: e048 b.n 8012908 8012876: 68fb ldr r3, [r7, #12] 8012878: 2201 movs r2, #1 801287a: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 801287e: 687b ldr r3, [r7, #4] 8012880: 2b0c cmp r3, #12 8012882: d839 bhi.n 80128f8 8012884: a201 add r2, pc, #4 @ (adr r2, 801288c ) 8012886: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801288a: bf00 nop 801288c: 080128c1 .word 0x080128c1 8012890: 080128f9 .word 0x080128f9 8012894: 080128f9 .word 0x080128f9 8012898: 080128f9 .word 0x080128f9 801289c: 080128cf .word 0x080128cf 80128a0: 080128f9 .word 0x080128f9 80128a4: 080128f9 .word 0x080128f9 80128a8: 080128f9 .word 0x080128f9 80128ac: 080128dd .word 0x080128dd 80128b0: 080128f9 .word 0x080128f9 80128b4: 080128f9 .word 0x080128f9 80128b8: 080128f9 .word 0x080128f9 80128bc: 080128eb .word 0x080128eb { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); 80128c0: 68fb ldr r3, [r7, #12] 80128c2: 681b ldr r3, [r3, #0] 80128c4: 68b9 ldr r1, [r7, #8] 80128c6: 4618 mov r0, r3 80128c8: f000 fa50 bl 8012d6c break; 80128cc: e017 b.n 80128fe { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); 80128ce: 68fb ldr r3, [r7, #12] 80128d0: 681b ldr r3, [r3, #0] 80128d2: 68b9 ldr r1, [r7, #8] 80128d4: 4618 mov r0, r3 80128d6: f000 faaf bl 8012e38 break; 80128da: e010 b.n 80128fe { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); 80128dc: 68fb ldr r3, [r7, #12] 80128de: 681b ldr r3, [r3, #0] 80128e0: 68b9 ldr r1, [r7, #8] 80128e2: 4618 mov r0, r3 80128e4: f000 fb12 bl 8012f0c break; 80128e8: e009 b.n 80128fe { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); 80128ea: 68fb ldr r3, [r7, #12] 80128ec: 681b ldr r3, [r3, #0] 80128ee: 68b9 ldr r1, [r7, #8] 80128f0: 4618 mov r0, r3 80128f2: f000 fb75 bl 8012fe0 break; 80128f6: e002 b.n 80128fe } default: status = HAL_ERROR; 80128f8: 2301 movs r3, #1 80128fa: 75fb strb r3, [r7, #23] break; 80128fc: bf00 nop } __HAL_UNLOCK(htim); 80128fe: 68fb ldr r3, [r7, #12] 8012900: 2200 movs r2, #0 8012902: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8012906: 7dfb ldrb r3, [r7, #23] } 8012908: 4618 mov r0, r3 801290a: 3718 adds r7, #24 801290c: 46bd mov sp, r7 801290e: bd80 pop {r7, pc} 08012910 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8012910: b580 push {r7, lr} 8012912: b086 sub sp, #24 8012914: af00 add r7, sp, #0 8012916: 60f8 str r0, [r7, #12] 8012918: 60b9 str r1, [r7, #8] 801291a: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 801291c: 2300 movs r3, #0 801291e: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 8012920: 68fb ldr r3, [r7, #12] 8012922: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8012926: 2b01 cmp r3, #1 8012928: d101 bne.n 801292e 801292a: 2302 movs r3, #2 801292c: e0ae b.n 8012a8c 801292e: 68fb ldr r3, [r7, #12] 8012930: 2201 movs r2, #1 8012932: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 8012936: 687b ldr r3, [r7, #4] 8012938: 2b0c cmp r3, #12 801293a: f200 809f bhi.w 8012a7c 801293e: a201 add r2, pc, #4 @ (adr r2, 8012944 ) 8012940: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012944: 08012979 .word 0x08012979 8012948: 08012a7d .word 0x08012a7d 801294c: 08012a7d .word 0x08012a7d 8012950: 08012a7d .word 0x08012a7d 8012954: 080129b9 .word 0x080129b9 8012958: 08012a7d .word 0x08012a7d 801295c: 08012a7d .word 0x08012a7d 8012960: 08012a7d .word 0x08012a7d 8012964: 080129fb .word 0x080129fb 8012968: 08012a7d .word 0x08012a7d 801296c: 08012a7d .word 0x08012a7d 8012970: 08012a7d .word 0x08012a7d 8012974: 08012a3b .word 0x08012a3b { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8012978: 68fb ldr r3, [r7, #12] 801297a: 681b ldr r3, [r3, #0] 801297c: 68b9 ldr r1, [r7, #8] 801297e: 4618 mov r0, r3 8012980: f000 f9f4 bl 8012d6c /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 8012984: 68fb ldr r3, [r7, #12] 8012986: 681b ldr r3, [r3, #0] 8012988: 699a ldr r2, [r3, #24] 801298a: 68fb ldr r3, [r7, #12] 801298c: 681b ldr r3, [r3, #0] 801298e: f042 0208 orr.w r2, r2, #8 8012992: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 8012994: 68fb ldr r3, [r7, #12] 8012996: 681b ldr r3, [r3, #0] 8012998: 699a ldr r2, [r3, #24] 801299a: 68fb ldr r3, [r7, #12] 801299c: 681b ldr r3, [r3, #0] 801299e: f022 0204 bic.w r2, r2, #4 80129a2: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 80129a4: 68fb ldr r3, [r7, #12] 80129a6: 681b ldr r3, [r3, #0] 80129a8: 6999 ldr r1, [r3, #24] 80129aa: 68bb ldr r3, [r7, #8] 80129ac: 691a ldr r2, [r3, #16] 80129ae: 68fb ldr r3, [r7, #12] 80129b0: 681b ldr r3, [r3, #0] 80129b2: 430a orrs r2, r1 80129b4: 619a str r2, [r3, #24] break; 80129b6: e064 b.n 8012a82 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 80129b8: 68fb ldr r3, [r7, #12] 80129ba: 681b ldr r3, [r3, #0] 80129bc: 68b9 ldr r1, [r7, #8] 80129be: 4618 mov r0, r3 80129c0: f000 fa3a bl 8012e38 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 80129c4: 68fb ldr r3, [r7, #12] 80129c6: 681b ldr r3, [r3, #0] 80129c8: 699a ldr r2, [r3, #24] 80129ca: 68fb ldr r3, [r7, #12] 80129cc: 681b ldr r3, [r3, #0] 80129ce: f442 6200 orr.w r2, r2, #2048 @ 0x800 80129d2: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 80129d4: 68fb ldr r3, [r7, #12] 80129d6: 681b ldr r3, [r3, #0] 80129d8: 699a ldr r2, [r3, #24] 80129da: 68fb ldr r3, [r7, #12] 80129dc: 681b ldr r3, [r3, #0] 80129de: f422 6280 bic.w r2, r2, #1024 @ 0x400 80129e2: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 80129e4: 68fb ldr r3, [r7, #12] 80129e6: 681b ldr r3, [r3, #0] 80129e8: 6999 ldr r1, [r3, #24] 80129ea: 68bb ldr r3, [r7, #8] 80129ec: 691b ldr r3, [r3, #16] 80129ee: 021a lsls r2, r3, #8 80129f0: 68fb ldr r3, [r7, #12] 80129f2: 681b ldr r3, [r3, #0] 80129f4: 430a orrs r2, r1 80129f6: 619a str r2, [r3, #24] break; 80129f8: e043 b.n 8012a82 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 80129fa: 68fb ldr r3, [r7, #12] 80129fc: 681b ldr r3, [r3, #0] 80129fe: 68b9 ldr r1, [r7, #8] 8012a00: 4618 mov r0, r3 8012a02: f000 fa83 bl 8012f0c /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 8012a06: 68fb ldr r3, [r7, #12] 8012a08: 681b ldr r3, [r3, #0] 8012a0a: 69da ldr r2, [r3, #28] 8012a0c: 68fb ldr r3, [r7, #12] 8012a0e: 681b ldr r3, [r3, #0] 8012a10: f042 0208 orr.w r2, r2, #8 8012a14: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 8012a16: 68fb ldr r3, [r7, #12] 8012a18: 681b ldr r3, [r3, #0] 8012a1a: 69da ldr r2, [r3, #28] 8012a1c: 68fb ldr r3, [r7, #12] 8012a1e: 681b ldr r3, [r3, #0] 8012a20: f022 0204 bic.w r2, r2, #4 8012a24: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 8012a26: 68fb ldr r3, [r7, #12] 8012a28: 681b ldr r3, [r3, #0] 8012a2a: 69d9 ldr r1, [r3, #28] 8012a2c: 68bb ldr r3, [r7, #8] 8012a2e: 691a ldr r2, [r3, #16] 8012a30: 68fb ldr r3, [r7, #12] 8012a32: 681b ldr r3, [r3, #0] 8012a34: 430a orrs r2, r1 8012a36: 61da str r2, [r3, #28] break; 8012a38: e023 b.n 8012a82 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8012a3a: 68fb ldr r3, [r7, #12] 8012a3c: 681b ldr r3, [r3, #0] 8012a3e: 68b9 ldr r1, [r7, #8] 8012a40: 4618 mov r0, r3 8012a42: f000 facd bl 8012fe0 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 8012a46: 68fb ldr r3, [r7, #12] 8012a48: 681b ldr r3, [r3, #0] 8012a4a: 69da ldr r2, [r3, #28] 8012a4c: 68fb ldr r3, [r7, #12] 8012a4e: 681b ldr r3, [r3, #0] 8012a50: f442 6200 orr.w r2, r2, #2048 @ 0x800 8012a54: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 8012a56: 68fb ldr r3, [r7, #12] 8012a58: 681b ldr r3, [r3, #0] 8012a5a: 69da ldr r2, [r3, #28] 8012a5c: 68fb ldr r3, [r7, #12] 8012a5e: 681b ldr r3, [r3, #0] 8012a60: f422 6280 bic.w r2, r2, #1024 @ 0x400 8012a64: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 8012a66: 68fb ldr r3, [r7, #12] 8012a68: 681b ldr r3, [r3, #0] 8012a6a: 69d9 ldr r1, [r3, #28] 8012a6c: 68bb ldr r3, [r7, #8] 8012a6e: 691b ldr r3, [r3, #16] 8012a70: 021a lsls r2, r3, #8 8012a72: 68fb ldr r3, [r7, #12] 8012a74: 681b ldr r3, [r3, #0] 8012a76: 430a orrs r2, r1 8012a78: 61da str r2, [r3, #28] break; 8012a7a: e002 b.n 8012a82 } default: status = HAL_ERROR; 8012a7c: 2301 movs r3, #1 8012a7e: 75fb strb r3, [r7, #23] break; 8012a80: bf00 nop } __HAL_UNLOCK(htim); 8012a82: 68fb ldr r3, [r7, #12] 8012a84: 2200 movs r2, #0 8012a86: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8012a8a: 7dfb ldrb r3, [r7, #23] } 8012a8c: 4618 mov r0, r3 8012a8e: 3718 adds r7, #24 8012a90: 46bd mov sp, r7 8012a92: bd80 pop {r7, pc} 08012a94 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 8012a94: b580 push {r7, lr} 8012a96: b084 sub sp, #16 8012a98: af00 add r7, sp, #0 8012a9a: 6078 str r0, [r7, #4] 8012a9c: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8012a9e: 2300 movs r3, #0 8012aa0: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 8012aa2: 687b ldr r3, [r7, #4] 8012aa4: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8012aa8: 2b01 cmp r3, #1 8012aaa: d101 bne.n 8012ab0 8012aac: 2302 movs r3, #2 8012aae: e0b4 b.n 8012c1a 8012ab0: 687b ldr r3, [r7, #4] 8012ab2: 2201 movs r2, #1 8012ab4: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 8012ab8: 687b ldr r3, [r7, #4] 8012aba: 2202 movs r2, #2 8012abc: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 8012ac0: 687b ldr r3, [r7, #4] 8012ac2: 681b ldr r3, [r3, #0] 8012ac4: 689b ldr r3, [r3, #8] 8012ac6: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 8012ac8: 68bb ldr r3, [r7, #8] 8012aca: f023 0377 bic.w r3, r3, #119 @ 0x77 8012ace: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8012ad0: 68bb ldr r3, [r7, #8] 8012ad2: f423 437f bic.w r3, r3, #65280 @ 0xff00 8012ad6: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 8012ad8: 687b ldr r3, [r7, #4] 8012ada: 681b ldr r3, [r3, #0] 8012adc: 68ba ldr r2, [r7, #8] 8012ade: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 8012ae0: 683b ldr r3, [r7, #0] 8012ae2: 681b ldr r3, [r3, #0] 8012ae4: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8012ae8: d03e beq.n 8012b68 8012aea: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8012aee: f200 8087 bhi.w 8012c00 8012af2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012af6: f000 8086 beq.w 8012c06 8012afa: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012afe: d87f bhi.n 8012c00 8012b00: 2b70 cmp r3, #112 @ 0x70 8012b02: d01a beq.n 8012b3a 8012b04: 2b70 cmp r3, #112 @ 0x70 8012b06: d87b bhi.n 8012c00 8012b08: 2b60 cmp r3, #96 @ 0x60 8012b0a: d050 beq.n 8012bae 8012b0c: 2b60 cmp r3, #96 @ 0x60 8012b0e: d877 bhi.n 8012c00 8012b10: 2b50 cmp r3, #80 @ 0x50 8012b12: d03c beq.n 8012b8e 8012b14: 2b50 cmp r3, #80 @ 0x50 8012b16: d873 bhi.n 8012c00 8012b18: 2b40 cmp r3, #64 @ 0x40 8012b1a: d058 beq.n 8012bce 8012b1c: 2b40 cmp r3, #64 @ 0x40 8012b1e: d86f bhi.n 8012c00 8012b20: 2b30 cmp r3, #48 @ 0x30 8012b22: d064 beq.n 8012bee 8012b24: 2b30 cmp r3, #48 @ 0x30 8012b26: d86b bhi.n 8012c00 8012b28: 2b20 cmp r3, #32 8012b2a: d060 beq.n 8012bee 8012b2c: 2b20 cmp r3, #32 8012b2e: d867 bhi.n 8012c00 8012b30: 2b00 cmp r3, #0 8012b32: d05c beq.n 8012bee 8012b34: 2b10 cmp r3, #16 8012b36: d05a beq.n 8012bee 8012b38: e062 b.n 8012c00 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8012b3a: 687b ldr r3, [r7, #4] 8012b3c: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8012b3e: 683b ldr r3, [r7, #0] 8012b40: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 8012b42: 683b ldr r3, [r7, #0] 8012b44: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8012b46: 683b ldr r3, [r7, #0] 8012b48: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8012b4a: f000 fb0e bl 801316a /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 8012b4e: 687b ldr r3, [r7, #4] 8012b50: 681b ldr r3, [r3, #0] 8012b52: 689b ldr r3, [r3, #8] 8012b54: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 8012b56: 68bb ldr r3, [r7, #8] 8012b58: f043 0377 orr.w r3, r3, #119 @ 0x77 8012b5c: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8012b5e: 687b ldr r3, [r7, #4] 8012b60: 681b ldr r3, [r3, #0] 8012b62: 68ba ldr r2, [r7, #8] 8012b64: 609a str r2, [r3, #8] break; 8012b66: e04f b.n 8012c08 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8012b68: 687b ldr r3, [r7, #4] 8012b6a: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8012b6c: 683b ldr r3, [r7, #0] 8012b6e: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 8012b70: 683b ldr r3, [r7, #0] 8012b72: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8012b74: 683b ldr r3, [r7, #0] 8012b76: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8012b78: f000 faf7 bl 801316a /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 8012b7c: 687b ldr r3, [r7, #4] 8012b7e: 681b ldr r3, [r3, #0] 8012b80: 689a ldr r2, [r3, #8] 8012b82: 687b ldr r3, [r7, #4] 8012b84: 681b ldr r3, [r3, #0] 8012b86: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8012b8a: 609a str r2, [r3, #8] break; 8012b8c: e03c b.n 8012c08 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8012b8e: 687b ldr r3, [r7, #4] 8012b90: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8012b92: 683b ldr r3, [r7, #0] 8012b94: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8012b96: 683b ldr r3, [r7, #0] 8012b98: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 8012b9a: 461a mov r2, r3 8012b9c: f000 fa6e bl 801307c TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 8012ba0: 687b ldr r3, [r7, #4] 8012ba2: 681b ldr r3, [r3, #0] 8012ba4: 2150 movs r1, #80 @ 0x50 8012ba6: 4618 mov r0, r3 8012ba8: f000 fac5 bl 8013136 break; 8012bac: e02c b.n 8012c08 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 8012bae: 687b ldr r3, [r7, #4] 8012bb0: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8012bb2: 683b ldr r3, [r7, #0] 8012bb4: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8012bb6: 683b ldr r3, [r7, #0] 8012bb8: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 8012bba: 461a mov r2, r3 8012bbc: f000 fa8c bl 80130d8 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 8012bc0: 687b ldr r3, [r7, #4] 8012bc2: 681b ldr r3, [r3, #0] 8012bc4: 2160 movs r1, #96 @ 0x60 8012bc6: 4618 mov r0, r3 8012bc8: f000 fab5 bl 8013136 break; 8012bcc: e01c b.n 8012c08 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8012bce: 687b ldr r3, [r7, #4] 8012bd0: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8012bd2: 683b ldr r3, [r7, #0] 8012bd4: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8012bd6: 683b ldr r3, [r7, #0] 8012bd8: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 8012bda: 461a mov r2, r3 8012bdc: f000 fa4e bl 801307c TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 8012be0: 687b ldr r3, [r7, #4] 8012be2: 681b ldr r3, [r3, #0] 8012be4: 2140 movs r1, #64 @ 0x40 8012be6: 4618 mov r0, r3 8012be8: f000 faa5 bl 8013136 break; 8012bec: e00c b.n 8012c08 case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 8012bee: 687b ldr r3, [r7, #4] 8012bf0: 681a ldr r2, [r3, #0] 8012bf2: 683b ldr r3, [r7, #0] 8012bf4: 681b ldr r3, [r3, #0] 8012bf6: 4619 mov r1, r3 8012bf8: 4610 mov r0, r2 8012bfa: f000 fa9c bl 8013136 break; 8012bfe: e003 b.n 8012c08 } default: status = HAL_ERROR; 8012c00: 2301 movs r3, #1 8012c02: 73fb strb r3, [r7, #15] break; 8012c04: e000 b.n 8012c08 break; 8012c06: bf00 nop } htim->State = HAL_TIM_STATE_READY; 8012c08: 687b ldr r3, [r7, #4] 8012c0a: 2201 movs r2, #1 8012c0c: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8012c10: 687b ldr r3, [r7, #4] 8012c12: 2200 movs r2, #0 8012c14: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8012c18: 7bfb ldrb r3, [r7, #15] } 8012c1a: 4618 mov r0, r3 8012c1c: 3710 adds r7, #16 8012c1e: 46bd mov sp, r7 8012c20: bd80 pop {r7, pc} 08012c22 : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8012c22: b480 push {r7} 8012c24: b083 sub sp, #12 8012c26: af00 add r7, sp, #0 8012c28: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } 8012c2a: bf00 nop 8012c2c: 370c adds r7, #12 8012c2e: 46bd mov sp, r7 8012c30: bc80 pop {r7} 8012c32: 4770 bx lr 08012c34 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 8012c34: b480 push {r7} 8012c36: b083 sub sp, #12 8012c38: af00 add r7, sp, #0 8012c3a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 8012c3c: bf00 nop 8012c3e: 370c adds r7, #12 8012c40: 46bd mov sp, r7 8012c42: bc80 pop {r7} 8012c44: 4770 bx lr 08012c46 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 8012c46: b480 push {r7} 8012c48: b083 sub sp, #12 8012c4a: af00 add r7, sp, #0 8012c4c: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 8012c4e: bf00 nop 8012c50: 370c adds r7, #12 8012c52: 46bd mov sp, r7 8012c54: bc80 pop {r7} 8012c56: 4770 bx lr 08012c58 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8012c58: b480 push {r7} 8012c5a: b083 sub sp, #12 8012c5c: af00 add r7, sp, #0 8012c5e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8012c60: bf00 nop 8012c62: 370c adds r7, #12 8012c64: 46bd mov sp, r7 8012c66: bc80 pop {r7} 8012c68: 4770 bx lr 08012c6a : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8012c6a: b480 push {r7} 8012c6c: b083 sub sp, #12 8012c6e: af00 add r7, sp, #0 8012c70: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 8012c72: bf00 nop 8012c74: 370c adds r7, #12 8012c76: 46bd mov sp, r7 8012c78: bc80 pop {r7} 8012c7a: 4770 bx lr 08012c7c : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8012c7c: b480 push {r7} 8012c7e: b085 sub sp, #20 8012c80: af00 add r7, sp, #0 8012c82: 6078 str r0, [r7, #4] 8012c84: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8012c86: 687b ldr r3, [r7, #4] 8012c88: 681b ldr r3, [r3, #0] 8012c8a: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8012c8c: 687b ldr r3, [r7, #4] 8012c8e: 4a33 ldr r2, [pc, #204] @ (8012d5c ) 8012c90: 4293 cmp r3, r2 8012c92: d00f beq.n 8012cb4 8012c94: 687b ldr r3, [r7, #4] 8012c96: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8012c9a: d00b beq.n 8012cb4 8012c9c: 687b ldr r3, [r7, #4] 8012c9e: 4a30 ldr r2, [pc, #192] @ (8012d60 ) 8012ca0: 4293 cmp r3, r2 8012ca2: d007 beq.n 8012cb4 8012ca4: 687b ldr r3, [r7, #4] 8012ca6: 4a2f ldr r2, [pc, #188] @ (8012d64 ) 8012ca8: 4293 cmp r3, r2 8012caa: d003 beq.n 8012cb4 8012cac: 687b ldr r3, [r7, #4] 8012cae: 4a2e ldr r2, [pc, #184] @ (8012d68 ) 8012cb0: 4293 cmp r3, r2 8012cb2: d108 bne.n 8012cc6 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8012cb4: 68fb ldr r3, [r7, #12] 8012cb6: f023 0370 bic.w r3, r3, #112 @ 0x70 8012cba: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8012cbc: 683b ldr r3, [r7, #0] 8012cbe: 685b ldr r3, [r3, #4] 8012cc0: 68fa ldr r2, [r7, #12] 8012cc2: 4313 orrs r3, r2 8012cc4: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8012cc6: 687b ldr r3, [r7, #4] 8012cc8: 4a24 ldr r2, [pc, #144] @ (8012d5c ) 8012cca: 4293 cmp r3, r2 8012ccc: d00f beq.n 8012cee 8012cce: 687b ldr r3, [r7, #4] 8012cd0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8012cd4: d00b beq.n 8012cee 8012cd6: 687b ldr r3, [r7, #4] 8012cd8: 4a21 ldr r2, [pc, #132] @ (8012d60 ) 8012cda: 4293 cmp r3, r2 8012cdc: d007 beq.n 8012cee 8012cde: 687b ldr r3, [r7, #4] 8012ce0: 4a20 ldr r2, [pc, #128] @ (8012d64 ) 8012ce2: 4293 cmp r3, r2 8012ce4: d003 beq.n 8012cee 8012ce6: 687b ldr r3, [r7, #4] 8012ce8: 4a1f ldr r2, [pc, #124] @ (8012d68 ) 8012cea: 4293 cmp r3, r2 8012cec: d108 bne.n 8012d00 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8012cee: 68fb ldr r3, [r7, #12] 8012cf0: f423 7340 bic.w r3, r3, #768 @ 0x300 8012cf4: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8012cf6: 683b ldr r3, [r7, #0] 8012cf8: 68db ldr r3, [r3, #12] 8012cfa: 68fa ldr r2, [r7, #12] 8012cfc: 4313 orrs r3, r2 8012cfe: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8012d00: 68fb ldr r3, [r7, #12] 8012d02: f023 0280 bic.w r2, r3, #128 @ 0x80 8012d06: 683b ldr r3, [r7, #0] 8012d08: 695b ldr r3, [r3, #20] 8012d0a: 4313 orrs r3, r2 8012d0c: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 8012d0e: 687b ldr r3, [r7, #4] 8012d10: 68fa ldr r2, [r7, #12] 8012d12: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8012d14: 683b ldr r3, [r7, #0] 8012d16: 689a ldr r2, [r3, #8] 8012d18: 687b ldr r3, [r7, #4] 8012d1a: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8012d1c: 683b ldr r3, [r7, #0] 8012d1e: 681a ldr r2, [r3, #0] 8012d20: 687b ldr r3, [r7, #4] 8012d22: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8012d24: 687b ldr r3, [r7, #4] 8012d26: 4a0d ldr r2, [pc, #52] @ (8012d5c ) 8012d28: 4293 cmp r3, r2 8012d2a: d103 bne.n 8012d34 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8012d2c: 683b ldr r3, [r7, #0] 8012d2e: 691a ldr r2, [r3, #16] 8012d30: 687b ldr r3, [r7, #4] 8012d32: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8012d34: 687b ldr r3, [r7, #4] 8012d36: 2201 movs r2, #1 8012d38: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 8012d3a: 687b ldr r3, [r7, #4] 8012d3c: 691b ldr r3, [r3, #16] 8012d3e: f003 0301 and.w r3, r3, #1 8012d42: 2b00 cmp r3, #0 8012d44: d005 beq.n 8012d52 { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 8012d46: 687b ldr r3, [r7, #4] 8012d48: 691b ldr r3, [r3, #16] 8012d4a: f023 0201 bic.w r2, r3, #1 8012d4e: 687b ldr r3, [r7, #4] 8012d50: 611a str r2, [r3, #16] } } 8012d52: bf00 nop 8012d54: 3714 adds r7, #20 8012d56: 46bd mov sp, r7 8012d58: bc80 pop {r7} 8012d5a: 4770 bx lr 8012d5c: 40012c00 .word 0x40012c00 8012d60: 40000400 .word 0x40000400 8012d64: 40000800 .word 0x40000800 8012d68: 40000c00 .word 0x40000c00 08012d6c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012d6c: b480 push {r7} 8012d6e: b087 sub sp, #28 8012d70: af00 add r7, sp, #0 8012d72: 6078 str r0, [r7, #4] 8012d74: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8012d76: 687b ldr r3, [r7, #4] 8012d78: 6a1b ldr r3, [r3, #32] 8012d7a: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 8012d7c: 687b ldr r3, [r7, #4] 8012d7e: 6a1b ldr r3, [r3, #32] 8012d80: f023 0201 bic.w r2, r3, #1 8012d84: 687b ldr r3, [r7, #4] 8012d86: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8012d88: 687b ldr r3, [r7, #4] 8012d8a: 685b ldr r3, [r3, #4] 8012d8c: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8012d8e: 687b ldr r3, [r7, #4] 8012d90: 699b ldr r3, [r3, #24] 8012d92: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 8012d94: 68fb ldr r3, [r7, #12] 8012d96: f023 0370 bic.w r3, r3, #112 @ 0x70 8012d9a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 8012d9c: 68fb ldr r3, [r7, #12] 8012d9e: f023 0303 bic.w r3, r3, #3 8012da2: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8012da4: 683b ldr r3, [r7, #0] 8012da6: 681b ldr r3, [r3, #0] 8012da8: 68fa ldr r2, [r7, #12] 8012daa: 4313 orrs r3, r2 8012dac: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 8012dae: 697b ldr r3, [r7, #20] 8012db0: f023 0302 bic.w r3, r3, #2 8012db4: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 8012db6: 683b ldr r3, [r7, #0] 8012db8: 689b ldr r3, [r3, #8] 8012dba: 697a ldr r2, [r7, #20] 8012dbc: 4313 orrs r3, r2 8012dbe: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8012dc0: 687b ldr r3, [r7, #4] 8012dc2: 4a1c ldr r2, [pc, #112] @ (8012e34 ) 8012dc4: 4293 cmp r3, r2 8012dc6: d10c bne.n 8012de2 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8012dc8: 697b ldr r3, [r7, #20] 8012dca: f023 0308 bic.w r3, r3, #8 8012dce: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8012dd0: 683b ldr r3, [r7, #0] 8012dd2: 68db ldr r3, [r3, #12] 8012dd4: 697a ldr r2, [r7, #20] 8012dd6: 4313 orrs r3, r2 8012dd8: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 8012dda: 697b ldr r3, [r7, #20] 8012ddc: f023 0304 bic.w r3, r3, #4 8012de0: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8012de2: 687b ldr r3, [r7, #4] 8012de4: 4a13 ldr r2, [pc, #76] @ (8012e34 ) 8012de6: 4293 cmp r3, r2 8012de8: d111 bne.n 8012e0e /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 8012dea: 693b ldr r3, [r7, #16] 8012dec: f423 7380 bic.w r3, r3, #256 @ 0x100 8012df0: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 8012df2: 693b ldr r3, [r7, #16] 8012df4: f423 7300 bic.w r3, r3, #512 @ 0x200 8012df8: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8012dfa: 683b ldr r3, [r7, #0] 8012dfc: 695b ldr r3, [r3, #20] 8012dfe: 693a ldr r2, [r7, #16] 8012e00: 4313 orrs r3, r2 8012e02: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8012e04: 683b ldr r3, [r7, #0] 8012e06: 699b ldr r3, [r3, #24] 8012e08: 693a ldr r2, [r7, #16] 8012e0a: 4313 orrs r3, r2 8012e0c: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012e0e: 687b ldr r3, [r7, #4] 8012e10: 693a ldr r2, [r7, #16] 8012e12: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8012e14: 687b ldr r3, [r7, #4] 8012e16: 68fa ldr r2, [r7, #12] 8012e18: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 8012e1a: 683b ldr r3, [r7, #0] 8012e1c: 685a ldr r2, [r3, #4] 8012e1e: 687b ldr r3, [r7, #4] 8012e20: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012e22: 687b ldr r3, [r7, #4] 8012e24: 697a ldr r2, [r7, #20] 8012e26: 621a str r2, [r3, #32] } 8012e28: bf00 nop 8012e2a: 371c adds r7, #28 8012e2c: 46bd mov sp, r7 8012e2e: bc80 pop {r7} 8012e30: 4770 bx lr 8012e32: bf00 nop 8012e34: 40012c00 .word 0x40012c00 08012e38 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012e38: b480 push {r7} 8012e3a: b087 sub sp, #28 8012e3c: af00 add r7, sp, #0 8012e3e: 6078 str r0, [r7, #4] 8012e40: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8012e42: 687b ldr r3, [r7, #4] 8012e44: 6a1b ldr r3, [r3, #32] 8012e46: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8012e48: 687b ldr r3, [r7, #4] 8012e4a: 6a1b ldr r3, [r3, #32] 8012e4c: f023 0210 bic.w r2, r3, #16 8012e50: 687b ldr r3, [r7, #4] 8012e52: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8012e54: 687b ldr r3, [r7, #4] 8012e56: 685b ldr r3, [r3, #4] 8012e58: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8012e5a: 687b ldr r3, [r7, #4] 8012e5c: 699b ldr r3, [r3, #24] 8012e5e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 8012e60: 68fb ldr r3, [r7, #12] 8012e62: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8012e66: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8012e68: 68fb ldr r3, [r7, #12] 8012e6a: f423 7340 bic.w r3, r3, #768 @ 0x300 8012e6e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8012e70: 683b ldr r3, [r7, #0] 8012e72: 681b ldr r3, [r3, #0] 8012e74: 021b lsls r3, r3, #8 8012e76: 68fa ldr r2, [r7, #12] 8012e78: 4313 orrs r3, r2 8012e7a: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 8012e7c: 697b ldr r3, [r7, #20] 8012e7e: f023 0320 bic.w r3, r3, #32 8012e82: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 8012e84: 683b ldr r3, [r7, #0] 8012e86: 689b ldr r3, [r3, #8] 8012e88: 011b lsls r3, r3, #4 8012e8a: 697a ldr r2, [r7, #20] 8012e8c: 4313 orrs r3, r2 8012e8e: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 8012e90: 687b ldr r3, [r7, #4] 8012e92: 4a1d ldr r2, [pc, #116] @ (8012f08 ) 8012e94: 4293 cmp r3, r2 8012e96: d10d bne.n 8012eb4 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 8012e98: 697b ldr r3, [r7, #20] 8012e9a: f023 0380 bic.w r3, r3, #128 @ 0x80 8012e9e: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8012ea0: 683b ldr r3, [r7, #0] 8012ea2: 68db ldr r3, [r3, #12] 8012ea4: 011b lsls r3, r3, #4 8012ea6: 697a ldr r2, [r7, #20] 8012ea8: 4313 orrs r3, r2 8012eaa: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8012eac: 697b ldr r3, [r7, #20] 8012eae: f023 0340 bic.w r3, r3, #64 @ 0x40 8012eb2: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8012eb4: 687b ldr r3, [r7, #4] 8012eb6: 4a14 ldr r2, [pc, #80] @ (8012f08 ) 8012eb8: 4293 cmp r3, r2 8012eba: d113 bne.n 8012ee4 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8012ebc: 693b ldr r3, [r7, #16] 8012ebe: f423 6380 bic.w r3, r3, #1024 @ 0x400 8012ec2: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8012ec4: 693b ldr r3, [r7, #16] 8012ec6: f423 6300 bic.w r3, r3, #2048 @ 0x800 8012eca: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8012ecc: 683b ldr r3, [r7, #0] 8012ece: 695b ldr r3, [r3, #20] 8012ed0: 009b lsls r3, r3, #2 8012ed2: 693a ldr r2, [r7, #16] 8012ed4: 4313 orrs r3, r2 8012ed6: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8012ed8: 683b ldr r3, [r7, #0] 8012eda: 699b ldr r3, [r3, #24] 8012edc: 009b lsls r3, r3, #2 8012ede: 693a ldr r2, [r7, #16] 8012ee0: 4313 orrs r3, r2 8012ee2: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012ee4: 687b ldr r3, [r7, #4] 8012ee6: 693a ldr r2, [r7, #16] 8012ee8: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8012eea: 687b ldr r3, [r7, #4] 8012eec: 68fa ldr r2, [r7, #12] 8012eee: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8012ef0: 683b ldr r3, [r7, #0] 8012ef2: 685a ldr r2, [r3, #4] 8012ef4: 687b ldr r3, [r7, #4] 8012ef6: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012ef8: 687b ldr r3, [r7, #4] 8012efa: 697a ldr r2, [r7, #20] 8012efc: 621a str r2, [r3, #32] } 8012efe: bf00 nop 8012f00: 371c adds r7, #28 8012f02: 46bd mov sp, r7 8012f04: bc80 pop {r7} 8012f06: 4770 bx lr 8012f08: 40012c00 .word 0x40012c00 08012f0c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012f0c: b480 push {r7} 8012f0e: b087 sub sp, #28 8012f10: af00 add r7, sp, #0 8012f12: 6078 str r0, [r7, #4] 8012f14: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8012f16: 687b ldr r3, [r7, #4] 8012f18: 6a1b ldr r3, [r3, #32] 8012f1a: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8012f1c: 687b ldr r3, [r7, #4] 8012f1e: 6a1b ldr r3, [r3, #32] 8012f20: f423 7280 bic.w r2, r3, #256 @ 0x100 8012f24: 687b ldr r3, [r7, #4] 8012f26: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8012f28: 687b ldr r3, [r7, #4] 8012f2a: 685b ldr r3, [r3, #4] 8012f2c: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8012f2e: 687b ldr r3, [r7, #4] 8012f30: 69db ldr r3, [r3, #28] 8012f32: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8012f34: 68fb ldr r3, [r7, #12] 8012f36: f023 0370 bic.w r3, r3, #112 @ 0x70 8012f3a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8012f3c: 68fb ldr r3, [r7, #12] 8012f3e: f023 0303 bic.w r3, r3, #3 8012f42: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8012f44: 683b ldr r3, [r7, #0] 8012f46: 681b ldr r3, [r3, #0] 8012f48: 68fa ldr r2, [r7, #12] 8012f4a: 4313 orrs r3, r2 8012f4c: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8012f4e: 697b ldr r3, [r7, #20] 8012f50: f423 7300 bic.w r3, r3, #512 @ 0x200 8012f54: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 8012f56: 683b ldr r3, [r7, #0] 8012f58: 689b ldr r3, [r3, #8] 8012f5a: 021b lsls r3, r3, #8 8012f5c: 697a ldr r2, [r7, #20] 8012f5e: 4313 orrs r3, r2 8012f60: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8012f62: 687b ldr r3, [r7, #4] 8012f64: 4a1d ldr r2, [pc, #116] @ (8012fdc ) 8012f66: 4293 cmp r3, r2 8012f68: d10d bne.n 8012f86 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8012f6a: 697b ldr r3, [r7, #20] 8012f6c: f423 6300 bic.w r3, r3, #2048 @ 0x800 8012f70: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 8012f72: 683b ldr r3, [r7, #0] 8012f74: 68db ldr r3, [r3, #12] 8012f76: 021b lsls r3, r3, #8 8012f78: 697a ldr r2, [r7, #20] 8012f7a: 4313 orrs r3, r2 8012f7c: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8012f7e: 697b ldr r3, [r7, #20] 8012f80: f423 6380 bic.w r3, r3, #1024 @ 0x400 8012f84: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8012f86: 687b ldr r3, [r7, #4] 8012f88: 4a14 ldr r2, [pc, #80] @ (8012fdc ) 8012f8a: 4293 cmp r3, r2 8012f8c: d113 bne.n 8012fb6 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8012f8e: 693b ldr r3, [r7, #16] 8012f90: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8012f94: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8012f96: 693b ldr r3, [r7, #16] 8012f98: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8012f9c: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8012f9e: 683b ldr r3, [r7, #0] 8012fa0: 695b ldr r3, [r3, #20] 8012fa2: 011b lsls r3, r3, #4 8012fa4: 693a ldr r2, [r7, #16] 8012fa6: 4313 orrs r3, r2 8012fa8: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 8012faa: 683b ldr r3, [r7, #0] 8012fac: 699b ldr r3, [r3, #24] 8012fae: 011b lsls r3, r3, #4 8012fb0: 693a ldr r2, [r7, #16] 8012fb2: 4313 orrs r3, r2 8012fb4: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012fb6: 687b ldr r3, [r7, #4] 8012fb8: 693a ldr r2, [r7, #16] 8012fba: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8012fbc: 687b ldr r3, [r7, #4] 8012fbe: 68fa ldr r2, [r7, #12] 8012fc0: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8012fc2: 683b ldr r3, [r7, #0] 8012fc4: 685a ldr r2, [r3, #4] 8012fc6: 687b ldr r3, [r7, #4] 8012fc8: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012fca: 687b ldr r3, [r7, #4] 8012fcc: 697a ldr r2, [r7, #20] 8012fce: 621a str r2, [r3, #32] } 8012fd0: bf00 nop 8012fd2: 371c adds r7, #28 8012fd4: 46bd mov sp, r7 8012fd6: bc80 pop {r7} 8012fd8: 4770 bx lr 8012fda: bf00 nop 8012fdc: 40012c00 .word 0x40012c00 08012fe0 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012fe0: b480 push {r7} 8012fe2: b087 sub sp, #28 8012fe4: af00 add r7, sp, #0 8012fe6: 6078 str r0, [r7, #4] 8012fe8: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8012fea: 687b ldr r3, [r7, #4] 8012fec: 6a1b ldr r3, [r3, #32] 8012fee: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8012ff0: 687b ldr r3, [r7, #4] 8012ff2: 6a1b ldr r3, [r3, #32] 8012ff4: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8012ff8: 687b ldr r3, [r7, #4] 8012ffa: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8012ffc: 687b ldr r3, [r7, #4] 8012ffe: 685b ldr r3, [r3, #4] 8013000: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8013002: 687b ldr r3, [r7, #4] 8013004: 69db ldr r3, [r3, #28] 8013006: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8013008: 68fb ldr r3, [r7, #12] 801300a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 801300e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8013010: 68fb ldr r3, [r7, #12] 8013012: f423 7340 bic.w r3, r3, #768 @ 0x300 8013016: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8013018: 683b ldr r3, [r7, #0] 801301a: 681b ldr r3, [r3, #0] 801301c: 021b lsls r3, r3, #8 801301e: 68fa ldr r2, [r7, #12] 8013020: 4313 orrs r3, r2 8013022: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8013024: 693b ldr r3, [r7, #16] 8013026: f423 5300 bic.w r3, r3, #8192 @ 0x2000 801302a: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 801302c: 683b ldr r3, [r7, #0] 801302e: 689b ldr r3, [r3, #8] 8013030: 031b lsls r3, r3, #12 8013032: 693a ldr r2, [r7, #16] 8013034: 4313 orrs r3, r2 8013036: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8013038: 687b ldr r3, [r7, #4] 801303a: 4a0f ldr r2, [pc, #60] @ (8013078 ) 801303c: 4293 cmp r3, r2 801303e: d109 bne.n 8013054 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8013040: 697b ldr r3, [r7, #20] 8013042: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8013046: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8013048: 683b ldr r3, [r7, #0] 801304a: 695b ldr r3, [r3, #20] 801304c: 019b lsls r3, r3, #6 801304e: 697a ldr r2, [r7, #20] 8013050: 4313 orrs r3, r2 8013052: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8013054: 687b ldr r3, [r7, #4] 8013056: 697a ldr r2, [r7, #20] 8013058: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 801305a: 687b ldr r3, [r7, #4] 801305c: 68fa ldr r2, [r7, #12] 801305e: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8013060: 683b ldr r3, [r7, #0] 8013062: 685a ldr r2, [r3, #4] 8013064: 687b ldr r3, [r7, #4] 8013066: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8013068: 687b ldr r3, [r7, #4] 801306a: 693a ldr r2, [r7, #16] 801306c: 621a str r2, [r3, #32] } 801306e: bf00 nop 8013070: 371c adds r7, #28 8013072: 46bd mov sp, r7 8013074: bc80 pop {r7} 8013076: 4770 bx lr 8013078: 40012c00 .word 0x40012c00 0801307c : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 801307c: b480 push {r7} 801307e: b087 sub sp, #28 8013080: af00 add r7, sp, #0 8013082: 60f8 str r0, [r7, #12] 8013084: 60b9 str r1, [r7, #8] 8013086: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8013088: 68fb ldr r3, [r7, #12] 801308a: 6a1b ldr r3, [r3, #32] 801308c: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 801308e: 68fb ldr r3, [r7, #12] 8013090: 6a1b ldr r3, [r3, #32] 8013092: f023 0201 bic.w r2, r3, #1 8013096: 68fb ldr r3, [r7, #12] 8013098: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 801309a: 68fb ldr r3, [r7, #12] 801309c: 699b ldr r3, [r3, #24] 801309e: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 80130a0: 693b ldr r3, [r7, #16] 80130a2: f023 03f0 bic.w r3, r3, #240 @ 0xf0 80130a6: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 80130a8: 687b ldr r3, [r7, #4] 80130aa: 011b lsls r3, r3, #4 80130ac: 693a ldr r2, [r7, #16] 80130ae: 4313 orrs r3, r2 80130b0: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 80130b2: 697b ldr r3, [r7, #20] 80130b4: f023 030a bic.w r3, r3, #10 80130b8: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 80130ba: 697a ldr r2, [r7, #20] 80130bc: 68bb ldr r3, [r7, #8] 80130be: 4313 orrs r3, r2 80130c0: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 80130c2: 68fb ldr r3, [r7, #12] 80130c4: 693a ldr r2, [r7, #16] 80130c6: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 80130c8: 68fb ldr r3, [r7, #12] 80130ca: 697a ldr r2, [r7, #20] 80130cc: 621a str r2, [r3, #32] } 80130ce: bf00 nop 80130d0: 371c adds r7, #28 80130d2: 46bd mov sp, r7 80130d4: bc80 pop {r7} 80130d6: 4770 bx lr 080130d8 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 80130d8: b480 push {r7} 80130da: b087 sub sp, #28 80130dc: af00 add r7, sp, #0 80130de: 60f8 str r0, [r7, #12] 80130e0: 60b9 str r1, [r7, #8] 80130e2: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 80130e4: 68fb ldr r3, [r7, #12] 80130e6: 6a1b ldr r3, [r3, #32] 80130e8: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 80130ea: 68fb ldr r3, [r7, #12] 80130ec: 6a1b ldr r3, [r3, #32] 80130ee: f023 0210 bic.w r2, r3, #16 80130f2: 68fb ldr r3, [r7, #12] 80130f4: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 80130f6: 68fb ldr r3, [r7, #12] 80130f8: 699b ldr r3, [r3, #24] 80130fa: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 80130fc: 693b ldr r3, [r7, #16] 80130fe: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8013102: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8013104: 687b ldr r3, [r7, #4] 8013106: 031b lsls r3, r3, #12 8013108: 693a ldr r2, [r7, #16] 801310a: 4313 orrs r3, r2 801310c: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 801310e: 697b ldr r3, [r7, #20] 8013110: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8013114: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8013116: 68bb ldr r3, [r7, #8] 8013118: 011b lsls r3, r3, #4 801311a: 697a ldr r2, [r7, #20] 801311c: 4313 orrs r3, r2 801311e: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8013120: 68fb ldr r3, [r7, #12] 8013122: 693a ldr r2, [r7, #16] 8013124: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8013126: 68fb ldr r3, [r7, #12] 8013128: 697a ldr r2, [r7, #20] 801312a: 621a str r2, [r3, #32] } 801312c: bf00 nop 801312e: 371c adds r7, #28 8013130: 46bd mov sp, r7 8013132: bc80 pop {r7} 8013134: 4770 bx lr 08013136 : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8013136: b480 push {r7} 8013138: b085 sub sp, #20 801313a: af00 add r7, sp, #0 801313c: 6078 str r0, [r7, #4] 801313e: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8013140: 687b ldr r3, [r7, #4] 8013142: 689b ldr r3, [r3, #8] 8013144: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8013146: 68fb ldr r3, [r7, #12] 8013148: f023 0370 bic.w r3, r3, #112 @ 0x70 801314c: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 801314e: 683a ldr r2, [r7, #0] 8013150: 68fb ldr r3, [r7, #12] 8013152: 4313 orrs r3, r2 8013154: f043 0307 orr.w r3, r3, #7 8013158: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 801315a: 687b ldr r3, [r7, #4] 801315c: 68fa ldr r2, [r7, #12] 801315e: 609a str r2, [r3, #8] } 8013160: bf00 nop 8013162: 3714 adds r7, #20 8013164: 46bd mov sp, r7 8013166: bc80 pop {r7} 8013168: 4770 bx lr 0801316a : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 801316a: b480 push {r7} 801316c: b087 sub sp, #28 801316e: af00 add r7, sp, #0 8013170: 60f8 str r0, [r7, #12] 8013172: 60b9 str r1, [r7, #8] 8013174: 607a str r2, [r7, #4] 8013176: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8013178: 68fb ldr r3, [r7, #12] 801317a: 689b ldr r3, [r3, #8] 801317c: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 801317e: 697b ldr r3, [r7, #20] 8013180: f423 437f bic.w r3, r3, #65280 @ 0xff00 8013184: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8013186: 683b ldr r3, [r7, #0] 8013188: 021a lsls r2, r3, #8 801318a: 687b ldr r3, [r7, #4] 801318c: 431a orrs r2, r3 801318e: 68bb ldr r3, [r7, #8] 8013190: 4313 orrs r3, r2 8013192: 697a ldr r2, [r7, #20] 8013194: 4313 orrs r3, r2 8013196: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8013198: 68fb ldr r3, [r7, #12] 801319a: 697a ldr r2, [r7, #20] 801319c: 609a str r2, [r3, #8] } 801319e: bf00 nop 80131a0: 371c adds r7, #28 80131a2: 46bd mov sp, r7 80131a4: bc80 pop {r7} 80131a6: 4770 bx lr 080131a8 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 80131a8: b480 push {r7} 80131aa: b087 sub sp, #28 80131ac: af00 add r7, sp, #0 80131ae: 60f8 str r0, [r7, #12] 80131b0: 60b9 str r1, [r7, #8] 80131b2: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 80131b4: 68bb ldr r3, [r7, #8] 80131b6: f003 031f and.w r3, r3, #31 80131ba: 2201 movs r2, #1 80131bc: fa02 f303 lsl.w r3, r2, r3 80131c0: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 80131c2: 68fb ldr r3, [r7, #12] 80131c4: 6a1a ldr r2, [r3, #32] 80131c6: 697b ldr r3, [r7, #20] 80131c8: 43db mvns r3, r3 80131ca: 401a ands r2, r3 80131cc: 68fb ldr r3, [r7, #12] 80131ce: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 80131d0: 68fb ldr r3, [r7, #12] 80131d2: 6a1a ldr r2, [r3, #32] 80131d4: 68bb ldr r3, [r7, #8] 80131d6: f003 031f and.w r3, r3, #31 80131da: 6879 ldr r1, [r7, #4] 80131dc: fa01 f303 lsl.w r3, r1, r3 80131e0: 431a orrs r2, r3 80131e2: 68fb ldr r3, [r7, #12] 80131e4: 621a str r2, [r3, #32] } 80131e6: bf00 nop 80131e8: 371c adds r7, #28 80131ea: 46bd mov sp, r7 80131ec: bc80 pop {r7} 80131ee: 4770 bx lr 080131f0 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 80131f0: b480 push {r7} 80131f2: b085 sub sp, #20 80131f4: af00 add r7, sp, #0 80131f6: 6078 str r0, [r7, #4] 80131f8: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 80131fa: 687b ldr r3, [r7, #4] 80131fc: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8013200: 2b01 cmp r3, #1 8013202: d101 bne.n 8013208 8013204: 2302 movs r3, #2 8013206: e04b b.n 80132a0 8013208: 687b ldr r3, [r7, #4] 801320a: 2201 movs r2, #1 801320c: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8013210: 687b ldr r3, [r7, #4] 8013212: 2202 movs r2, #2 8013214: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8013218: 687b ldr r3, [r7, #4] 801321a: 681b ldr r3, [r3, #0] 801321c: 685b ldr r3, [r3, #4] 801321e: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8013220: 687b ldr r3, [r7, #4] 8013222: 681b ldr r3, [r3, #0] 8013224: 689b ldr r3, [r3, #8] 8013226: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8013228: 68fb ldr r3, [r7, #12] 801322a: f023 0370 bic.w r3, r3, #112 @ 0x70 801322e: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8013230: 683b ldr r3, [r7, #0] 8013232: 681b ldr r3, [r3, #0] 8013234: 68fa ldr r2, [r7, #12] 8013236: 4313 orrs r3, r2 8013238: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 801323a: 687b ldr r3, [r7, #4] 801323c: 681b ldr r3, [r3, #0] 801323e: 68fa ldr r2, [r7, #12] 8013240: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8013242: 687b ldr r3, [r7, #4] 8013244: 681b ldr r3, [r3, #0] 8013246: 4a19 ldr r2, [pc, #100] @ (80132ac ) 8013248: 4293 cmp r3, r2 801324a: d013 beq.n 8013274 801324c: 687b ldr r3, [r7, #4] 801324e: 681b ldr r3, [r3, #0] 8013250: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8013254: d00e beq.n 8013274 8013256: 687b ldr r3, [r7, #4] 8013258: 681b ldr r3, [r3, #0] 801325a: 4a15 ldr r2, [pc, #84] @ (80132b0 ) 801325c: 4293 cmp r3, r2 801325e: d009 beq.n 8013274 8013260: 687b ldr r3, [r7, #4] 8013262: 681b ldr r3, [r3, #0] 8013264: 4a13 ldr r2, [pc, #76] @ (80132b4 ) 8013266: 4293 cmp r3, r2 8013268: d004 beq.n 8013274 801326a: 687b ldr r3, [r7, #4] 801326c: 681b ldr r3, [r3, #0] 801326e: 4a12 ldr r2, [pc, #72] @ (80132b8 ) 8013270: 4293 cmp r3, r2 8013272: d10c bne.n 801328e { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8013274: 68bb ldr r3, [r7, #8] 8013276: f023 0380 bic.w r3, r3, #128 @ 0x80 801327a: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 801327c: 683b ldr r3, [r7, #0] 801327e: 685b ldr r3, [r3, #4] 8013280: 68ba ldr r2, [r7, #8] 8013282: 4313 orrs r3, r2 8013284: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8013286: 687b ldr r3, [r7, #4] 8013288: 681b ldr r3, [r3, #0] 801328a: 68ba ldr r2, [r7, #8] 801328c: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 801328e: 687b ldr r3, [r7, #4] 8013290: 2201 movs r2, #1 8013292: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8013296: 687b ldr r3, [r7, #4] 8013298: 2200 movs r2, #0 801329a: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 801329e: 2300 movs r3, #0 } 80132a0: 4618 mov r0, r3 80132a2: 3714 adds r7, #20 80132a4: 46bd mov sp, r7 80132a6: bc80 pop {r7} 80132a8: 4770 bx lr 80132aa: bf00 nop 80132ac: 40012c00 .word 0x40012c00 80132b0: 40000400 .word 0x40000400 80132b4: 40000800 .word 0x40000800 80132b8: 40000c00 .word 0x40000c00 080132bc : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 80132bc: b480 push {r7} 80132be: b083 sub sp, #12 80132c0: af00 add r7, sp, #0 80132c2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 80132c4: bf00 nop 80132c6: 370c adds r7, #12 80132c8: 46bd mov sp, r7 80132ca: bc80 pop {r7} 80132cc: 4770 bx lr 080132ce : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 80132ce: b480 push {r7} 80132d0: b083 sub sp, #12 80132d2: af00 add r7, sp, #0 80132d4: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 80132d6: bf00 nop 80132d8: 370c adds r7, #12 80132da: 46bd mov sp, r7 80132dc: bc80 pop {r7} 80132de: 4770 bx lr 080132e0 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 80132e0: b580 push {r7, lr} 80132e2: b082 sub sp, #8 80132e4: af00 add r7, sp, #0 80132e6: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 80132e8: 687b ldr r3, [r7, #4] 80132ea: 2b00 cmp r3, #0 80132ec: d101 bne.n 80132f2 { return HAL_ERROR; 80132ee: 2301 movs r3, #1 80132f0: e042 b.n 8013378 assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 80132f2: 687b ldr r3, [r7, #4] 80132f4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80132f8: b2db uxtb r3, r3 80132fa: 2b00 cmp r3, #0 80132fc: d106 bne.n 801330c { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 80132fe: 687b ldr r3, [r7, #4] 8013300: 2200 movs r2, #0 8013302: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8013306: 6878 ldr r0, [r7, #4] 8013308: f7fa ffc2 bl 800e290 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 801330c: 687b ldr r3, [r7, #4] 801330e: 2224 movs r2, #36 @ 0x24 8013310: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8013314: 687b ldr r3, [r7, #4] 8013316: 681b ldr r3, [r3, #0] 8013318: 68da ldr r2, [r3, #12] 801331a: 687b ldr r3, [r7, #4] 801331c: 681b ldr r3, [r3, #0] 801331e: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8013322: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8013324: 6878 ldr r0, [r7, #4] 8013326: f001 f903 bl 8014530 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 801332a: 687b ldr r3, [r7, #4] 801332c: 681b ldr r3, [r3, #0] 801332e: 691a ldr r2, [r3, #16] 8013330: 687b ldr r3, [r7, #4] 8013332: 681b ldr r3, [r3, #0] 8013334: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8013338: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 801333a: 687b ldr r3, [r7, #4] 801333c: 681b ldr r3, [r3, #0] 801333e: 695a ldr r2, [r3, #20] 8013340: 687b ldr r3, [r7, #4] 8013342: 681b ldr r3, [r3, #0] 8013344: f022 022a bic.w r2, r2, #42 @ 0x2a 8013348: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 801334a: 687b ldr r3, [r7, #4] 801334c: 681b ldr r3, [r3, #0] 801334e: 68da ldr r2, [r3, #12] 8013350: 687b ldr r3, [r7, #4] 8013352: 681b ldr r3, [r3, #0] 8013354: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8013358: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 801335a: 687b ldr r3, [r7, #4] 801335c: 2200 movs r2, #0 801335e: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8013360: 687b ldr r3, [r7, #4] 8013362: 2220 movs r2, #32 8013364: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8013368: 687b ldr r3, [r7, #4] 801336a: 2220 movs r2, #32 801336c: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8013370: 687b ldr r3, [r7, #4] 8013372: 2200 movs r2, #0 8013374: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8013376: 2300 movs r3, #0 } 8013378: 4618 mov r0, r3 801337a: 3708 adds r7, #8 801337c: 46bd mov sp, r7 801337e: bd80 pop {r7, pc} 08013380 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8013380: b580 push {r7, lr} 8013382: b08c sub sp, #48 @ 0x30 8013384: af00 add r7, sp, #0 8013386: 60f8 str r0, [r7, #12] 8013388: 60b9 str r1, [r7, #8] 801338a: 4613 mov r3, r2 801338c: 80fb strh r3, [r7, #6] const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 801338e: 68fb ldr r3, [r7, #12] 8013390: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8013394: b2db uxtb r3, r3 8013396: 2b20 cmp r3, #32 8013398: d156 bne.n 8013448 { if ((pData == NULL) || (Size == 0U)) 801339a: 68bb ldr r3, [r7, #8] 801339c: 2b00 cmp r3, #0 801339e: d002 beq.n 80133a6 80133a0: 88fb ldrh r3, [r7, #6] 80133a2: 2b00 cmp r3, #0 80133a4: d101 bne.n 80133aa { return HAL_ERROR; 80133a6: 2301 movs r3, #1 80133a8: e04f b.n 801344a } huart->pTxBuffPtr = pData; 80133aa: 68ba ldr r2, [r7, #8] 80133ac: 68fb ldr r3, [r7, #12] 80133ae: 621a str r2, [r3, #32] huart->TxXferSize = Size; 80133b0: 68fb ldr r3, [r7, #12] 80133b2: 88fa ldrh r2, [r7, #6] 80133b4: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 80133b6: 68fb ldr r3, [r7, #12] 80133b8: 88fa ldrh r2, [r7, #6] 80133ba: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 80133bc: 68fb ldr r3, [r7, #12] 80133be: 2200 movs r2, #0 80133c0: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 80133c2: 68fb ldr r3, [r7, #12] 80133c4: 2221 movs r2, #33 @ 0x21 80133c6: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 80133ca: 68fb ldr r3, [r7, #12] 80133cc: 6b9b ldr r3, [r3, #56] @ 0x38 80133ce: 4a21 ldr r2, [pc, #132] @ (8013454 ) 80133d0: 629a str r2, [r3, #40] @ 0x28 /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 80133d2: 68fb ldr r3, [r7, #12] 80133d4: 6b9b ldr r3, [r3, #56] @ 0x38 80133d6: 4a20 ldr r2, [pc, #128] @ (8013458 ) 80133d8: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 80133da: 68fb ldr r3, [r7, #12] 80133dc: 6b9b ldr r3, [r3, #56] @ 0x38 80133de: 4a1f ldr r2, [pc, #124] @ (801345c ) 80133e0: 631a str r2, [r3, #48] @ 0x30 /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 80133e2: 68fb ldr r3, [r7, #12] 80133e4: 6b9b ldr r3, [r3, #56] @ 0x38 80133e6: 2200 movs r2, #0 80133e8: 635a str r2, [r3, #52] @ 0x34 /* Enable the UART transmit DMA channel */ tmp = (const uint32_t *)&pData; 80133ea: f107 0308 add.w r3, r7, #8 80133ee: 62fb str r3, [r7, #44] @ 0x2c HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size); 80133f0: 68fb ldr r3, [r7, #12] 80133f2: 6b98 ldr r0, [r3, #56] @ 0x38 80133f4: 6afb ldr r3, [r7, #44] @ 0x2c 80133f6: 6819 ldr r1, [r3, #0] 80133f8: 68fb ldr r3, [r7, #12] 80133fa: 681b ldr r3, [r3, #0] 80133fc: 3304 adds r3, #4 80133fe: 461a mov r2, r3 8013400: 88fb ldrh r3, [r7, #6] 8013402: f7fc ffa5 bl 8010350 /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); 8013406: 68fb ldr r3, [r7, #12] 8013408: 681b ldr r3, [r3, #0] 801340a: f06f 0240 mvn.w r2, #64 @ 0x40 801340e: 601a str r2, [r3, #0] /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8013410: 68fb ldr r3, [r7, #12] 8013412: 681b ldr r3, [r3, #0] 8013414: 3314 adds r3, #20 8013416: 61bb str r3, [r7, #24] */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013418: 69bb ldr r3, [r7, #24] 801341a: e853 3f00 ldrex r3, [r3] 801341e: 617b str r3, [r7, #20] return(result); 8013420: 697b ldr r3, [r7, #20] 8013422: f043 0380 orr.w r3, r3, #128 @ 0x80 8013426: 62bb str r3, [r7, #40] @ 0x28 8013428: 68fb ldr r3, [r7, #12] 801342a: 681b ldr r3, [r3, #0] 801342c: 3314 adds r3, #20 801342e: 6aba ldr r2, [r7, #40] @ 0x28 8013430: 627a str r2, [r7, #36] @ 0x24 8013432: 623b str r3, [r7, #32] */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013434: 6a39 ldr r1, [r7, #32] 8013436: 6a7a ldr r2, [r7, #36] @ 0x24 8013438: e841 2300 strex r3, r2, [r1] 801343c: 61fb str r3, [r7, #28] return(result); 801343e: 69fb ldr r3, [r7, #28] 8013440: 2b00 cmp r3, #0 8013442: d1e5 bne.n 8013410 return HAL_OK; 8013444: 2300 movs r3, #0 8013446: e000 b.n 801344a } else { return HAL_BUSY; 8013448: 2302 movs r3, #2 } } 801344a: 4618 mov r0, r3 801344c: 3730 adds r7, #48 @ 0x30 801344e: 46bd mov sp, r7 8013450: bd80 pop {r7, pc} 8013452: bf00 nop 8013454: 08013d55 .word 0x08013d55 8013458: 08013def .word 0x08013def 801345c: 08013f73 .word 0x08013f73 08013460 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8013460: b580 push {r7, lr} 8013462: b08c sub sp, #48 @ 0x30 8013464: af00 add r7, sp, #0 8013466: 60f8 str r0, [r7, #12] 8013468: 60b9 str r1, [r7, #8] 801346a: 4613 mov r3, r2 801346c: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 801346e: 68fb ldr r3, [r7, #12] 8013470: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8013474: b2db uxtb r3, r3 8013476: 2b20 cmp r3, #32 8013478: d14a bne.n 8013510 { if ((pData == NULL) || (Size == 0U)) 801347a: 68bb ldr r3, [r7, #8] 801347c: 2b00 cmp r3, #0 801347e: d002 beq.n 8013486 8013480: 88fb ldrh r3, [r7, #6] 8013482: 2b00 cmp r3, #0 8013484: d101 bne.n 801348a { return HAL_ERROR; 8013486: 2301 movs r3, #1 8013488: e043 b.n 8013512 } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 801348a: 68fb ldr r3, [r7, #12] 801348c: 2201 movs r2, #1 801348e: 631a str r2, [r3, #48] @ 0x30 huart->RxEventType = HAL_UART_RXEVENT_TC; 8013490: 68fb ldr r3, [r7, #12] 8013492: 2200 movs r2, #0 8013494: 635a str r2, [r3, #52] @ 0x34 status = UART_Start_Receive_IT(huart, pData, Size); 8013496: 88fb ldrh r3, [r7, #6] 8013498: 461a mov r2, r3 801349a: 68b9 ldr r1, [r7, #8] 801349c: 68f8 ldr r0, [r7, #12] 801349e: f000 fdb2 bl 8014006 80134a2: 4603 mov r3, r0 80134a4: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check Rx process has been successfully started */ if (status == HAL_OK) 80134a8: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 80134ac: 2b00 cmp r3, #0 80134ae: d12c bne.n 801350a { if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80134b0: 68fb ldr r3, [r7, #12] 80134b2: 6b1b ldr r3, [r3, #48] @ 0x30 80134b4: 2b01 cmp r3, #1 80134b6: d125 bne.n 8013504 { __HAL_UART_CLEAR_IDLEFLAG(huart); 80134b8: 2300 movs r3, #0 80134ba: 613b str r3, [r7, #16] 80134bc: 68fb ldr r3, [r7, #12] 80134be: 681b ldr r3, [r3, #0] 80134c0: 681b ldr r3, [r3, #0] 80134c2: 613b str r3, [r7, #16] 80134c4: 68fb ldr r3, [r7, #12] 80134c6: 681b ldr r3, [r3, #0] 80134c8: 685b ldr r3, [r3, #4] 80134ca: 613b str r3, [r7, #16] 80134cc: 693b ldr r3, [r7, #16] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80134ce: 68fb ldr r3, [r7, #12] 80134d0: 681b ldr r3, [r3, #0] 80134d2: 330c adds r3, #12 80134d4: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80134d6: 69bb ldr r3, [r7, #24] 80134d8: e853 3f00 ldrex r3, [r3] 80134dc: 617b str r3, [r7, #20] return(result); 80134de: 697b ldr r3, [r7, #20] 80134e0: f043 0310 orr.w r3, r3, #16 80134e4: 62bb str r3, [r7, #40] @ 0x28 80134e6: 68fb ldr r3, [r7, #12] 80134e8: 681b ldr r3, [r3, #0] 80134ea: 330c adds r3, #12 80134ec: 6aba ldr r2, [r7, #40] @ 0x28 80134ee: 627a str r2, [r7, #36] @ 0x24 80134f0: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80134f2: 6a39 ldr r1, [r7, #32] 80134f4: 6a7a ldr r2, [r7, #36] @ 0x24 80134f6: e841 2300 strex r3, r2, [r1] 80134fa: 61fb str r3, [r7, #28] return(result); 80134fc: 69fb ldr r3, [r7, #28] 80134fe: 2b00 cmp r3, #0 8013500: d1e5 bne.n 80134ce 8013502: e002 b.n 801350a { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8013504: 2301 movs r3, #1 8013506: f887 302f strb.w r3, [r7, #47] @ 0x2f } } return status; 801350a: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 801350e: e000 b.n 8013512 } else { return HAL_BUSY; 8013510: 2302 movs r3, #2 } } 8013512: 4618 mov r0, r3 8013514: 3730 adds r7, #48 @ 0x30 8013516: 46bd mov sp, r7 8013518: bd80 pop {r7, pc} 0801351a : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 801351a: b580 push {r7, lr} 801351c: b08c sub sp, #48 @ 0x30 801351e: af00 add r7, sp, #0 8013520: 60f8 str r0, [r7, #12] 8013522: 60b9 str r1, [r7, #8] 8013524: 4613 mov r3, r2 8013526: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8013528: 68fb ldr r3, [r7, #12] 801352a: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 801352e: b2db uxtb r3, r3 8013530: 2b20 cmp r3, #32 8013532: d146 bne.n 80135c2 { if ((pData == NULL) || (Size == 0U)) 8013534: 68bb ldr r3, [r7, #8] 8013536: 2b00 cmp r3, #0 8013538: d002 beq.n 8013540 801353a: 88fb ldrh r3, [r7, #6] 801353c: 2b00 cmp r3, #0 801353e: d101 bne.n 8013544 { return HAL_ERROR; 8013540: 2301 movs r3, #1 8013542: e03f b.n 80135c4 } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8013544: 68fb ldr r3, [r7, #12] 8013546: 2201 movs r2, #1 8013548: 631a str r2, [r3, #48] @ 0x30 huart->RxEventType = HAL_UART_RXEVENT_TC; 801354a: 68fb ldr r3, [r7, #12] 801354c: 2200 movs r2, #0 801354e: 635a str r2, [r3, #52] @ 0x34 status = UART_Start_Receive_DMA(huart, pData, Size); 8013550: 88fb ldrh r3, [r7, #6] 8013552: 461a mov r2, r3 8013554: 68b9 ldr r1, [r7, #8] 8013556: 68f8 ldr r0, [r7, #12] 8013558: f000 fd8e bl 8014078 801355c: 4603 mov r3, r0 801355e: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check Rx process has been successfully started */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013562: 68fb ldr r3, [r7, #12] 8013564: 6b1b ldr r3, [r3, #48] @ 0x30 8013566: 2b01 cmp r3, #1 8013568: d125 bne.n 80135b6 { __HAL_UART_CLEAR_IDLEFLAG(huart); 801356a: 2300 movs r3, #0 801356c: 613b str r3, [r7, #16] 801356e: 68fb ldr r3, [r7, #12] 8013570: 681b ldr r3, [r3, #0] 8013572: 681b ldr r3, [r3, #0] 8013574: 613b str r3, [r7, #16] 8013576: 68fb ldr r3, [r7, #12] 8013578: 681b ldr r3, [r3, #0] 801357a: 685b ldr r3, [r3, #4] 801357c: 613b str r3, [r7, #16] 801357e: 693b ldr r3, [r7, #16] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013580: 68fb ldr r3, [r7, #12] 8013582: 681b ldr r3, [r3, #0] 8013584: 330c adds r3, #12 8013586: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013588: 69bb ldr r3, [r7, #24] 801358a: e853 3f00 ldrex r3, [r3] 801358e: 617b str r3, [r7, #20] return(result); 8013590: 697b ldr r3, [r7, #20] 8013592: f043 0310 orr.w r3, r3, #16 8013596: 62bb str r3, [r7, #40] @ 0x28 8013598: 68fb ldr r3, [r7, #12] 801359a: 681b ldr r3, [r3, #0] 801359c: 330c adds r3, #12 801359e: 6aba ldr r2, [r7, #40] @ 0x28 80135a0: 627a str r2, [r7, #36] @ 0x24 80135a2: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80135a4: 6a39 ldr r1, [r7, #32] 80135a6: 6a7a ldr r2, [r7, #36] @ 0x24 80135a8: e841 2300 strex r3, r2, [r1] 80135ac: 61fb str r3, [r7, #28] return(result); 80135ae: 69fb ldr r3, [r7, #28] 80135b0: 2b00 cmp r3, #0 80135b2: d1e5 bne.n 8013580 80135b4: e002 b.n 80135bc { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 80135b6: 2301 movs r3, #1 80135b8: f887 302f strb.w r3, [r7, #47] @ 0x2f } return status; 80135bc: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 80135c0: e000 b.n 80135c4 } else { return HAL_BUSY; 80135c2: 2302 movs r3, #2 } } 80135c4: 4618 mov r0, r3 80135c6: 3730 adds r7, #48 @ 0x30 80135c8: 46bd mov sp, r7 80135ca: bd80 pop {r7, pc} 080135cc : * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { 80135cc: b580 push {r7, lr} 80135ce: b08e sub sp, #56 @ 0x38 80135d0: af00 add r7, sp, #0 80135d2: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 80135d4: 687b ldr r3, [r7, #4] 80135d6: 681b ldr r3, [r3, #0] 80135d8: 330c adds r3, #12 80135da: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80135dc: 6a3b ldr r3, [r7, #32] 80135de: e853 3f00 ldrex r3, [r3] 80135e2: 61fb str r3, [r7, #28] return(result); 80135e4: 69fb ldr r3, [r7, #28] 80135e6: f023 03c0 bic.w r3, r3, #192 @ 0xc0 80135ea: 637b str r3, [r7, #52] @ 0x34 80135ec: 687b ldr r3, [r7, #4] 80135ee: 681b ldr r3, [r3, #0] 80135f0: 330c adds r3, #12 80135f2: 6b7a ldr r2, [r7, #52] @ 0x34 80135f4: 62fa str r2, [r7, #44] @ 0x2c 80135f6: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80135f8: 6ab9 ldr r1, [r7, #40] @ 0x28 80135fa: 6afa ldr r2, [r7, #44] @ 0x2c 80135fc: e841 2300 strex r3, r2, [r1] 8013600: 627b str r3, [r7, #36] @ 0x24 return(result); 8013602: 6a7b ldr r3, [r7, #36] @ 0x24 8013604: 2b00 cmp r3, #0 8013606: d1e5 bne.n 80135d4 /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) 8013608: 687b ldr r3, [r7, #4] 801360a: 681b ldr r3, [r3, #0] 801360c: 695b ldr r3, [r3, #20] 801360e: f003 0380 and.w r3, r3, #128 @ 0x80 8013612: 2b00 cmp r3, #0 8013614: d036 beq.n 8013684 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8013616: 687b ldr r3, [r7, #4] 8013618: 681b ldr r3, [r3, #0] 801361a: 3314 adds r3, #20 801361c: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801361e: 68fb ldr r3, [r7, #12] 8013620: e853 3f00 ldrex r3, [r3] 8013624: 60bb str r3, [r7, #8] return(result); 8013626: 68bb ldr r3, [r7, #8] 8013628: f023 0380 bic.w r3, r3, #128 @ 0x80 801362c: 633b str r3, [r7, #48] @ 0x30 801362e: 687b ldr r3, [r7, #4] 8013630: 681b ldr r3, [r3, #0] 8013632: 3314 adds r3, #20 8013634: 6b3a ldr r2, [r7, #48] @ 0x30 8013636: 61ba str r2, [r7, #24] 8013638: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801363a: 6979 ldr r1, [r7, #20] 801363c: 69ba ldr r2, [r7, #24] 801363e: e841 2300 strex r3, r2, [r1] 8013642: 613b str r3, [r7, #16] return(result); 8013644: 693b ldr r3, [r7, #16] 8013646: 2b00 cmp r3, #0 8013648: d1e5 bne.n 8013616 /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) 801364a: 687b ldr r3, [r7, #4] 801364c: 6b9b ldr r3, [r3, #56] @ 0x38 801364e: 2b00 cmp r3, #0 8013650: d018 beq.n 8013684 { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = NULL; 8013652: 687b ldr r3, [r7, #4] 8013654: 6b9b ldr r3, [r3, #56] @ 0x38 8013656: 2200 movs r2, #0 8013658: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) 801365a: 687b ldr r3, [r7, #4] 801365c: 6b9b ldr r3, [r3, #56] @ 0x38 801365e: 4618 mov r0, r3 8013660: f7fc fed6 bl 8010410 8013664: 4603 mov r3, r0 8013666: 2b00 cmp r3, #0 8013668: d00c beq.n 8013684 { if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) 801366a: 687b ldr r3, [r7, #4] 801366c: 6b9b ldr r3, [r3, #56] @ 0x38 801366e: 4618 mov r0, r3 8013670: f7fd fa4e bl 8010b10 8013674: 4603 mov r3, r0 8013676: 2b20 cmp r3, #32 8013678: d104 bne.n 8013684 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 801367a: 687b ldr r3, [r7, #4] 801367c: 2210 movs r2, #16 801367e: 645a str r2, [r3, #68] @ 0x44 return HAL_TIMEOUT; 8013680: 2303 movs r3, #3 8013682: e007 b.n 8013694 } } } /* Reset Tx transfer counter */ huart->TxXferCount = 0x00U; 8013684: 687b ldr r3, [r7, #4] 8013686: 2200 movs r2, #0 8013688: 84da strh r2, [r3, #38] @ 0x26 /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 801368a: 687b ldr r3, [r7, #4] 801368c: 2220 movs r2, #32 801368e: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_OK; 8013692: 2300 movs r3, #0 } 8013694: 4618 mov r0, r3 8013696: 3738 adds r7, #56 @ 0x38 8013698: 46bd mov sp, r7 801369a: bd80 pop {r7, pc} 0801369c : * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { 801369c: b580 push {r7, lr} 801369e: b09a sub sp, #104 @ 0x68 80136a0: af00 add r7, sp, #0 80136a2: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 80136a4: 687b ldr r3, [r7, #4] 80136a6: 681b ldr r3, [r3, #0] 80136a8: 330c adds r3, #12 80136aa: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80136ac: 6cbb ldr r3, [r7, #72] @ 0x48 80136ae: e853 3f00 ldrex r3, [r3] 80136b2: 647b str r3, [r7, #68] @ 0x44 return(result); 80136b4: 6c7b ldr r3, [r7, #68] @ 0x44 80136b6: f423 7390 bic.w r3, r3, #288 @ 0x120 80136ba: 667b str r3, [r7, #100] @ 0x64 80136bc: 687b ldr r3, [r7, #4] 80136be: 681b ldr r3, [r3, #0] 80136c0: 330c adds r3, #12 80136c2: 6e7a ldr r2, [r7, #100] @ 0x64 80136c4: 657a str r2, [r7, #84] @ 0x54 80136c6: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80136c8: 6d39 ldr r1, [r7, #80] @ 0x50 80136ca: 6d7a ldr r2, [r7, #84] @ 0x54 80136cc: e841 2300 strex r3, r2, [r1] 80136d0: 64fb str r3, [r7, #76] @ 0x4c return(result); 80136d2: 6cfb ldr r3, [r7, #76] @ 0x4c 80136d4: 2b00 cmp r3, #0 80136d6: d1e5 bne.n 80136a4 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80136d8: 687b ldr r3, [r7, #4] 80136da: 681b ldr r3, [r3, #0] 80136dc: 3314 adds r3, #20 80136de: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80136e0: 6b7b ldr r3, [r7, #52] @ 0x34 80136e2: e853 3f00 ldrex r3, [r3] 80136e6: 633b str r3, [r7, #48] @ 0x30 return(result); 80136e8: 6b3b ldr r3, [r7, #48] @ 0x30 80136ea: f023 0301 bic.w r3, r3, #1 80136ee: 663b str r3, [r7, #96] @ 0x60 80136f0: 687b ldr r3, [r7, #4] 80136f2: 681b ldr r3, [r3, #0] 80136f4: 3314 adds r3, #20 80136f6: 6e3a ldr r2, [r7, #96] @ 0x60 80136f8: 643a str r2, [r7, #64] @ 0x40 80136fa: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80136fc: 6bf9 ldr r1, [r7, #60] @ 0x3c 80136fe: 6c3a ldr r2, [r7, #64] @ 0x40 8013700: e841 2300 strex r3, r2, [r1] 8013704: 63bb str r3, [r7, #56] @ 0x38 return(result); 8013706: 6bbb ldr r3, [r7, #56] @ 0x38 8013708: 2b00 cmp r3, #0 801370a: d1e5 bne.n 80136d8 /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 801370c: 687b ldr r3, [r7, #4] 801370e: 6b1b ldr r3, [r3, #48] @ 0x30 8013710: 2b01 cmp r3, #1 8013712: d119 bne.n 8013748 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); 8013714: 687b ldr r3, [r7, #4] 8013716: 681b ldr r3, [r3, #0] 8013718: 330c adds r3, #12 801371a: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801371c: 6a3b ldr r3, [r7, #32] 801371e: e853 3f00 ldrex r3, [r3] 8013722: 61fb str r3, [r7, #28] return(result); 8013724: 69fb ldr r3, [r7, #28] 8013726: f023 0310 bic.w r3, r3, #16 801372a: 65fb str r3, [r7, #92] @ 0x5c 801372c: 687b ldr r3, [r7, #4] 801372e: 681b ldr r3, [r3, #0] 8013730: 330c adds r3, #12 8013732: 6dfa ldr r2, [r7, #92] @ 0x5c 8013734: 62fa str r2, [r7, #44] @ 0x2c 8013736: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013738: 6ab9 ldr r1, [r7, #40] @ 0x28 801373a: 6afa ldr r2, [r7, #44] @ 0x2c 801373c: e841 2300 strex r3, r2, [r1] 8013740: 627b str r3, [r7, #36] @ 0x24 return(result); 8013742: 6a7b ldr r3, [r7, #36] @ 0x24 8013744: 2b00 cmp r3, #0 8013746: d1e5 bne.n 8013714 } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013748: 687b ldr r3, [r7, #4] 801374a: 681b ldr r3, [r3, #0] 801374c: 695b ldr r3, [r3, #20] 801374e: f003 0340 and.w r3, r3, #64 @ 0x40 8013752: 2b00 cmp r3, #0 8013754: d036 beq.n 80137c4 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8013756: 687b ldr r3, [r7, #4] 8013758: 681b ldr r3, [r3, #0] 801375a: 3314 adds r3, #20 801375c: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801375e: 68fb ldr r3, [r7, #12] 8013760: e853 3f00 ldrex r3, [r3] 8013764: 60bb str r3, [r7, #8] return(result); 8013766: 68bb ldr r3, [r7, #8] 8013768: f023 0340 bic.w r3, r3, #64 @ 0x40 801376c: 65bb str r3, [r7, #88] @ 0x58 801376e: 687b ldr r3, [r7, #4] 8013770: 681b ldr r3, [r3, #0] 8013772: 3314 adds r3, #20 8013774: 6dba ldr r2, [r7, #88] @ 0x58 8013776: 61ba str r2, [r7, #24] 8013778: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801377a: 6979 ldr r1, [r7, #20] 801377c: 69ba ldr r2, [r7, #24] 801377e: e841 2300 strex r3, r2, [r1] 8013782: 613b str r3, [r7, #16] return(result); 8013784: 693b ldr r3, [r7, #16] 8013786: 2b00 cmp r3, #0 8013788: d1e5 bne.n 8013756 /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) 801378a: 687b ldr r3, [r7, #4] 801378c: 6bdb ldr r3, [r3, #60] @ 0x3c 801378e: 2b00 cmp r3, #0 8013790: d018 beq.n 80137c4 { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = NULL; 8013792: 687b ldr r3, [r7, #4] 8013794: 6bdb ldr r3, [r3, #60] @ 0x3c 8013796: 2200 movs r2, #0 8013798: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) 801379a: 687b ldr r3, [r7, #4] 801379c: 6bdb ldr r3, [r3, #60] @ 0x3c 801379e: 4618 mov r0, r3 80137a0: f7fc fe36 bl 8010410 80137a4: 4603 mov r3, r0 80137a6: 2b00 cmp r3, #0 80137a8: d00c beq.n 80137c4 { if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) 80137aa: 687b ldr r3, [r7, #4] 80137ac: 6bdb ldr r3, [r3, #60] @ 0x3c 80137ae: 4618 mov r0, r3 80137b0: f7fd f9ae bl 8010b10 80137b4: 4603 mov r3, r0 80137b6: 2b20 cmp r3, #32 80137b8: d104 bne.n 80137c4 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 80137ba: 687b ldr r3, [r7, #4] 80137bc: 2210 movs r2, #16 80137be: 645a str r2, [r3, #68] @ 0x44 return HAL_TIMEOUT; 80137c0: 2303 movs r3, #3 80137c2: e00a b.n 80137da } } } /* Reset Rx transfer counter */ huart->RxXferCount = 0x00U; 80137c4: 687b ldr r3, [r7, #4] 80137c6: 2200 movs r2, #0 80137c8: 85da strh r2, [r3, #46] @ 0x2e /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80137ca: 687b ldr r3, [r7, #4] 80137cc: 2220 movs r2, #32 80137ce: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80137d2: 687b ldr r3, [r7, #4] 80137d4: 2200 movs r2, #0 80137d6: 631a str r2, [r3, #48] @ 0x30 return HAL_OK; 80137d8: 2300 movs r3, #0 } 80137da: 4618 mov r0, r3 80137dc: 3768 adds r7, #104 @ 0x68 80137de: 46bd mov sp, r7 80137e0: bd80 pop {r7, pc} ... 080137e4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 80137e4: b580 push {r7, lr} 80137e6: b0ba sub sp, #232 @ 0xe8 80137e8: af00 add r7, sp, #0 80137ea: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 80137ec: 687b ldr r3, [r7, #4] 80137ee: 681b ldr r3, [r3, #0] 80137f0: 681b ldr r3, [r3, #0] 80137f2: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 80137f6: 687b ldr r3, [r7, #4] 80137f8: 681b ldr r3, [r3, #0] 80137fa: 68db ldr r3, [r3, #12] 80137fc: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8013800: 687b ldr r3, [r7, #4] 8013802: 681b ldr r3, [r3, #0] 8013804: 695b ldr r3, [r3, #20] 8013806: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 801380a: 2300 movs r3, #0 801380c: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 8013810: 2300 movs r3, #0 8013812: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8013816: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801381a: f003 030f and.w r3, r3, #15 801381e: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 8013822: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8013826: 2b00 cmp r3, #0 8013828: d10f bne.n 801384a { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 801382a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801382e: f003 0320 and.w r3, r3, #32 8013832: 2b00 cmp r3, #0 8013834: d009 beq.n 801384a 8013836: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801383a: f003 0320 and.w r3, r3, #32 801383e: 2b00 cmp r3, #0 8013840: d003 beq.n 801384a { UART_Receive_IT(huart); 8013842: 6878 ldr r0, [r7, #4] 8013844: f000 fdb6 bl 80143b4 return; 8013848: e25b b.n 8013d02 } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 801384a: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 801384e: 2b00 cmp r3, #0 8013850: f000 80de beq.w 8013a10 8013854: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8013858: f003 0301 and.w r3, r3, #1 801385c: 2b00 cmp r3, #0 801385e: d106 bne.n 801386e || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8013860: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013864: f403 7390 and.w r3, r3, #288 @ 0x120 8013868: 2b00 cmp r3, #0 801386a: f000 80d1 beq.w 8013a10 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 801386e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013872: f003 0301 and.w r3, r3, #1 8013876: 2b00 cmp r3, #0 8013878: d00b beq.n 8013892 801387a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801387e: f403 7380 and.w r3, r3, #256 @ 0x100 8013882: 2b00 cmp r3, #0 8013884: d005 beq.n 8013892 { huart->ErrorCode |= HAL_UART_ERROR_PE; 8013886: 687b ldr r3, [r7, #4] 8013888: 6c5b ldr r3, [r3, #68] @ 0x44 801388a: f043 0201 orr.w r2, r3, #1 801388e: 687b ldr r3, [r7, #4] 8013890: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8013892: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013896: f003 0304 and.w r3, r3, #4 801389a: 2b00 cmp r3, #0 801389c: d00b beq.n 80138b6 801389e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80138a2: f003 0301 and.w r3, r3, #1 80138a6: 2b00 cmp r3, #0 80138a8: d005 beq.n 80138b6 { huart->ErrorCode |= HAL_UART_ERROR_NE; 80138aa: 687b ldr r3, [r7, #4] 80138ac: 6c5b ldr r3, [r3, #68] @ 0x44 80138ae: f043 0202 orr.w r2, r3, #2 80138b2: 687b ldr r3, [r7, #4] 80138b4: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 80138b6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80138ba: f003 0302 and.w r3, r3, #2 80138be: 2b00 cmp r3, #0 80138c0: d00b beq.n 80138da 80138c2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80138c6: f003 0301 and.w r3, r3, #1 80138ca: 2b00 cmp r3, #0 80138cc: d005 beq.n 80138da { huart->ErrorCode |= HAL_UART_ERROR_FE; 80138ce: 687b ldr r3, [r7, #4] 80138d0: 6c5b ldr r3, [r3, #68] @ 0x44 80138d2: f043 0204 orr.w r2, r3, #4 80138d6: 687b ldr r3, [r7, #4] 80138d8: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 80138da: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80138de: f003 0308 and.w r3, r3, #8 80138e2: 2b00 cmp r3, #0 80138e4: d011 beq.n 801390a 80138e6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80138ea: f003 0320 and.w r3, r3, #32 80138ee: 2b00 cmp r3, #0 80138f0: d105 bne.n 80138fe || ((cr3its & USART_CR3_EIE) != RESET))) 80138f2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80138f6: f003 0301 and.w r3, r3, #1 80138fa: 2b00 cmp r3, #0 80138fc: d005 beq.n 801390a { huart->ErrorCode |= HAL_UART_ERROR_ORE; 80138fe: 687b ldr r3, [r7, #4] 8013900: 6c5b ldr r3, [r3, #68] @ 0x44 8013902: f043 0208 orr.w r2, r3, #8 8013906: 687b ldr r3, [r7, #4] 8013908: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 801390a: 687b ldr r3, [r7, #4] 801390c: 6c5b ldr r3, [r3, #68] @ 0x44 801390e: 2b00 cmp r3, #0 8013910: f000 81f2 beq.w 8013cf8 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8013914: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013918: f003 0320 and.w r3, r3, #32 801391c: 2b00 cmp r3, #0 801391e: d008 beq.n 8013932 8013920: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013924: f003 0320 and.w r3, r3, #32 8013928: 2b00 cmp r3, #0 801392a: d002 beq.n 8013932 { UART_Receive_IT(huart); 801392c: 6878 ldr r0, [r7, #4] 801392e: f000 fd41 bl 80143b4 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8013932: 687b ldr r3, [r7, #4] 8013934: 681b ldr r3, [r3, #0] 8013936: 695b ldr r3, [r3, #20] 8013938: f003 0340 and.w r3, r3, #64 @ 0x40 801393c: 2b00 cmp r3, #0 801393e: bf14 ite ne 8013940: 2301 movne r3, #1 8013942: 2300 moveq r3, #0 8013944: b2db uxtb r3, r3 8013946: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 801394a: 687b ldr r3, [r7, #4] 801394c: 6c5b ldr r3, [r3, #68] @ 0x44 801394e: f003 0308 and.w r3, r3, #8 8013952: 2b00 cmp r3, #0 8013954: d103 bne.n 801395e 8013956: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 801395a: 2b00 cmp r3, #0 801395c: d04f beq.n 80139fe { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 801395e: 6878 ldr r0, [r7, #4] 8013960: f000 fc4b bl 80141fa /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013964: 687b ldr r3, [r7, #4] 8013966: 681b ldr r3, [r3, #0] 8013968: 695b ldr r3, [r3, #20] 801396a: f003 0340 and.w r3, r3, #64 @ 0x40 801396e: 2b00 cmp r3, #0 8013970: d041 beq.n 80139f6 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8013972: 687b ldr r3, [r7, #4] 8013974: 681b ldr r3, [r3, #0] 8013976: 3314 adds r3, #20 8013978: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801397c: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8013980: e853 3f00 ldrex r3, [r3] 8013984: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8013988: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 801398c: f023 0340 bic.w r3, r3, #64 @ 0x40 8013990: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8013994: 687b ldr r3, [r7, #4] 8013996: 681b ldr r3, [r3, #0] 8013998: 3314 adds r3, #20 801399a: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 801399e: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 80139a2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80139a6: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 80139aa: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 80139ae: e841 2300 strex r3, r2, [r1] 80139b2: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 80139b6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80139ba: 2b00 cmp r3, #0 80139bc: d1d9 bne.n 8013972 /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 80139be: 687b ldr r3, [r7, #4] 80139c0: 6bdb ldr r3, [r3, #60] @ 0x3c 80139c2: 2b00 cmp r3, #0 80139c4: d013 beq.n 80139ee { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 80139c6: 687b ldr r3, [r7, #4] 80139c8: 6bdb ldr r3, [r3, #60] @ 0x3c 80139ca: 4a7e ldr r2, [pc, #504] @ (8013bc4 ) 80139cc: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 80139ce: 687b ldr r3, [r7, #4] 80139d0: 6bdb ldr r3, [r3, #60] @ 0x3c 80139d2: 4618 mov r0, r3 80139d4: f7fc fd58 bl 8010488 80139d8: 4603 mov r3, r0 80139da: 2b00 cmp r3, #0 80139dc: d016 beq.n 8013a0c { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 80139de: 687b ldr r3, [r7, #4] 80139e0: 6bdb ldr r3, [r3, #60] @ 0x3c 80139e2: 6b5b ldr r3, [r3, #52] @ 0x34 80139e4: 687a ldr r2, [r7, #4] 80139e6: 6bd2 ldr r2, [r2, #60] @ 0x3c 80139e8: 4610 mov r0, r2 80139ea: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80139ec: e00e b.n 8013a0c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80139ee: 6878 ldr r0, [r7, #4] 80139f0: f7f8 fb8e bl 800c110 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80139f4: e00a b.n 8013a0c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80139f6: 6878 ldr r0, [r7, #4] 80139f8: f7f8 fb8a bl 800c110 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80139fc: e006 b.n 8013a0c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80139fe: 6878 ldr r0, [r7, #4] 8013a00: f7f8 fb86 bl 800c110 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8013a04: 687b ldr r3, [r7, #4] 8013a06: 2200 movs r2, #0 8013a08: 645a str r2, [r3, #68] @ 0x44 } } return; 8013a0a: e175 b.n 8013cf8 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013a0c: bf00 nop return; 8013a0e: e173 b.n 8013cf8 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013a10: 687b ldr r3, [r7, #4] 8013a12: 6b1b ldr r3, [r3, #48] @ 0x30 8013a14: 2b01 cmp r3, #1 8013a16: f040 814f bne.w 8013cb8 && ((isrflags & USART_SR_IDLE) != 0U) 8013a1a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013a1e: f003 0310 and.w r3, r3, #16 8013a22: 2b00 cmp r3, #0 8013a24: f000 8148 beq.w 8013cb8 && ((cr1its & USART_SR_IDLE) != 0U)) 8013a28: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013a2c: f003 0310 and.w r3, r3, #16 8013a30: 2b00 cmp r3, #0 8013a32: f000 8141 beq.w 8013cb8 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8013a36: 2300 movs r3, #0 8013a38: 60bb str r3, [r7, #8] 8013a3a: 687b ldr r3, [r7, #4] 8013a3c: 681b ldr r3, [r3, #0] 8013a3e: 681b ldr r3, [r3, #0] 8013a40: 60bb str r3, [r7, #8] 8013a42: 687b ldr r3, [r7, #4] 8013a44: 681b ldr r3, [r3, #0] 8013a46: 685b ldr r3, [r3, #4] 8013a48: 60bb str r3, [r7, #8] 8013a4a: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013a4c: 687b ldr r3, [r7, #4] 8013a4e: 681b ldr r3, [r3, #0] 8013a50: 695b ldr r3, [r3, #20] 8013a52: f003 0340 and.w r3, r3, #64 @ 0x40 8013a56: 2b00 cmp r3, #0 8013a58: f000 80b6 beq.w 8013bc8 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8013a5c: 687b ldr r3, [r7, #4] 8013a5e: 6bdb ldr r3, [r3, #60] @ 0x3c 8013a60: 681b ldr r3, [r3, #0] 8013a62: 685b ldr r3, [r3, #4] 8013a64: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8013a68: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8013a6c: 2b00 cmp r3, #0 8013a6e: f000 8145 beq.w 8013cfc && (nb_remaining_rx_data < huart->RxXferSize)) 8013a72: 687b ldr r3, [r7, #4] 8013a74: 8d9b ldrh r3, [r3, #44] @ 0x2c 8013a76: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8013a7a: 429a cmp r2, r3 8013a7c: f080 813e bcs.w 8013cfc { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8013a80: 687b ldr r3, [r7, #4] 8013a82: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8013a86: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8013a88: 687b ldr r3, [r7, #4] 8013a8a: 6bdb ldr r3, [r3, #60] @ 0x3c 8013a8c: 699b ldr r3, [r3, #24] 8013a8e: 2b20 cmp r3, #32 8013a90: f000 8088 beq.w 8013ba4 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8013a94: 687b ldr r3, [r7, #4] 8013a96: 681b ldr r3, [r3, #0] 8013a98: 330c adds r3, #12 8013a9a: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013a9e: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8013aa2: e853 3f00 ldrex r3, [r3] 8013aa6: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8013aaa: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8013aae: f423 7380 bic.w r3, r3, #256 @ 0x100 8013ab2: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8013ab6: 687b ldr r3, [r7, #4] 8013ab8: 681b ldr r3, [r3, #0] 8013aba: 330c adds r3, #12 8013abc: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 8013ac0: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8013ac4: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013ac8: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8013acc: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8013ad0: e841 2300 strex r3, r2, [r1] 8013ad4: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8013ad8: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8013adc: 2b00 cmp r3, #0 8013ade: d1d9 bne.n 8013a94 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013ae0: 687b ldr r3, [r7, #4] 8013ae2: 681b ldr r3, [r3, #0] 8013ae4: 3314 adds r3, #20 8013ae6: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013ae8: 6f7b ldr r3, [r7, #116] @ 0x74 8013aea: e853 3f00 ldrex r3, [r3] 8013aee: 673b str r3, [r7, #112] @ 0x70 return(result); 8013af0: 6f3b ldr r3, [r7, #112] @ 0x70 8013af2: f023 0301 bic.w r3, r3, #1 8013af6: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8013afa: 687b ldr r3, [r7, #4] 8013afc: 681b ldr r3, [r3, #0] 8013afe: 3314 adds r3, #20 8013b00: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8013b04: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8013b08: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013b0a: 6ff9 ldr r1, [r7, #124] @ 0x7c 8013b0c: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8013b10: e841 2300 strex r3, r2, [r1] 8013b14: 67bb str r3, [r7, #120] @ 0x78 return(result); 8013b16: 6fbb ldr r3, [r7, #120] @ 0x78 8013b18: 2b00 cmp r3, #0 8013b1a: d1e1 bne.n 8013ae0 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8013b1c: 687b ldr r3, [r7, #4] 8013b1e: 681b ldr r3, [r3, #0] 8013b20: 3314 adds r3, #20 8013b22: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013b24: 6e3b ldr r3, [r7, #96] @ 0x60 8013b26: e853 3f00 ldrex r3, [r3] 8013b2a: 65fb str r3, [r7, #92] @ 0x5c return(result); 8013b2c: 6dfb ldr r3, [r7, #92] @ 0x5c 8013b2e: f023 0340 bic.w r3, r3, #64 @ 0x40 8013b32: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8013b36: 687b ldr r3, [r7, #4] 8013b38: 681b ldr r3, [r3, #0] 8013b3a: 3314 adds r3, #20 8013b3c: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8013b40: 66fa str r2, [r7, #108] @ 0x6c 8013b42: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013b44: 6eb9 ldr r1, [r7, #104] @ 0x68 8013b46: 6efa ldr r2, [r7, #108] @ 0x6c 8013b48: e841 2300 strex r3, r2, [r1] 8013b4c: 667b str r3, [r7, #100] @ 0x64 return(result); 8013b4e: 6e7b ldr r3, [r7, #100] @ 0x64 8013b50: 2b00 cmp r3, #0 8013b52: d1e3 bne.n 8013b1c /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013b54: 687b ldr r3, [r7, #4] 8013b56: 2220 movs r2, #32 8013b58: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013b5c: 687b ldr r3, [r7, #4] 8013b5e: 2200 movs r2, #0 8013b60: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013b62: 687b ldr r3, [r7, #4] 8013b64: 681b ldr r3, [r3, #0] 8013b66: 330c adds r3, #12 8013b68: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013b6a: 6cfb ldr r3, [r7, #76] @ 0x4c 8013b6c: e853 3f00 ldrex r3, [r3] 8013b70: 64bb str r3, [r7, #72] @ 0x48 return(result); 8013b72: 6cbb ldr r3, [r7, #72] @ 0x48 8013b74: f023 0310 bic.w r3, r3, #16 8013b78: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8013b7c: 687b ldr r3, [r7, #4] 8013b7e: 681b ldr r3, [r3, #0] 8013b80: 330c adds r3, #12 8013b82: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 8013b86: 65ba str r2, [r7, #88] @ 0x58 8013b88: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013b8a: 6d79 ldr r1, [r7, #84] @ 0x54 8013b8c: 6dba ldr r2, [r7, #88] @ 0x58 8013b8e: e841 2300 strex r3, r2, [r1] 8013b92: 653b str r3, [r7, #80] @ 0x50 return(result); 8013b94: 6d3b ldr r3, [r7, #80] @ 0x50 8013b96: 2b00 cmp r3, #0 8013b98: d1e3 bne.n 8013b62 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8013b9a: 687b ldr r3, [r7, #4] 8013b9c: 6bdb ldr r3, [r3, #60] @ 0x3c 8013b9e: 4618 mov r0, r3 8013ba0: f7fc fc36 bl 8010410 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8013ba4: 687b ldr r3, [r7, #4] 8013ba6: 2202 movs r2, #2 8013ba8: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8013baa: 687b ldr r3, [r7, #4] 8013bac: 8d9a ldrh r2, [r3, #44] @ 0x2c 8013bae: 687b ldr r3, [r7, #4] 8013bb0: 8ddb ldrh r3, [r3, #46] @ 0x2e 8013bb2: b29b uxth r3, r3 8013bb4: 1ad3 subs r3, r2, r3 8013bb6: b29b uxth r3, r3 8013bb8: 4619 mov r1, r3 8013bba: 6878 ldr r0, [r7, #4] 8013bbc: f7f9 f9f2 bl 800cfa4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8013bc0: e09c b.n 8013cfc 8013bc2: bf00 nop 8013bc4: 080142bf .word 0x080142bf else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8013bc8: 687b ldr r3, [r7, #4] 8013bca: 8d9a ldrh r2, [r3, #44] @ 0x2c 8013bcc: 687b ldr r3, [r7, #4] 8013bce: 8ddb ldrh r3, [r3, #46] @ 0x2e 8013bd0: b29b uxth r3, r3 8013bd2: 1ad3 subs r3, r2, r3 8013bd4: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8013bd8: 687b ldr r3, [r7, #4] 8013bda: 8ddb ldrh r3, [r3, #46] @ 0x2e 8013bdc: b29b uxth r3, r3 8013bde: 2b00 cmp r3, #0 8013be0: f000 808e beq.w 8013d00 && (nb_rx_data > 0U)) 8013be4: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8013be8: 2b00 cmp r3, #0 8013bea: f000 8089 beq.w 8013d00 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8013bee: 687b ldr r3, [r7, #4] 8013bf0: 681b ldr r3, [r3, #0] 8013bf2: 330c adds r3, #12 8013bf4: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013bf6: 6bbb ldr r3, [r7, #56] @ 0x38 8013bf8: e853 3f00 ldrex r3, [r3] 8013bfc: 637b str r3, [r7, #52] @ 0x34 return(result); 8013bfe: 6b7b ldr r3, [r7, #52] @ 0x34 8013c00: f423 7390 bic.w r3, r3, #288 @ 0x120 8013c04: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8013c08: 687b ldr r3, [r7, #4] 8013c0a: 681b ldr r3, [r3, #0] 8013c0c: 330c adds r3, #12 8013c0e: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 8013c12: 647a str r2, [r7, #68] @ 0x44 8013c14: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013c16: 6c39 ldr r1, [r7, #64] @ 0x40 8013c18: 6c7a ldr r2, [r7, #68] @ 0x44 8013c1a: e841 2300 strex r3, r2, [r1] 8013c1e: 63fb str r3, [r7, #60] @ 0x3c return(result); 8013c20: 6bfb ldr r3, [r7, #60] @ 0x3c 8013c22: 2b00 cmp r3, #0 8013c24: d1e3 bne.n 8013bee /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013c26: 687b ldr r3, [r7, #4] 8013c28: 681b ldr r3, [r3, #0] 8013c2a: 3314 adds r3, #20 8013c2c: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013c2e: 6a7b ldr r3, [r7, #36] @ 0x24 8013c30: e853 3f00 ldrex r3, [r3] 8013c34: 623b str r3, [r7, #32] return(result); 8013c36: 6a3b ldr r3, [r7, #32] 8013c38: f023 0301 bic.w r3, r3, #1 8013c3c: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8013c40: 687b ldr r3, [r7, #4] 8013c42: 681b ldr r3, [r3, #0] 8013c44: 3314 adds r3, #20 8013c46: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8013c4a: 633a str r2, [r7, #48] @ 0x30 8013c4c: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013c4e: 6af9 ldr r1, [r7, #44] @ 0x2c 8013c50: 6b3a ldr r2, [r7, #48] @ 0x30 8013c52: e841 2300 strex r3, r2, [r1] 8013c56: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013c58: 6abb ldr r3, [r7, #40] @ 0x28 8013c5a: 2b00 cmp r3, #0 8013c5c: d1e3 bne.n 8013c26 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013c5e: 687b ldr r3, [r7, #4] 8013c60: 2220 movs r2, #32 8013c62: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013c66: 687b ldr r3, [r7, #4] 8013c68: 2200 movs r2, #0 8013c6a: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013c6c: 687b ldr r3, [r7, #4] 8013c6e: 681b ldr r3, [r3, #0] 8013c70: 330c adds r3, #12 8013c72: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013c74: 693b ldr r3, [r7, #16] 8013c76: e853 3f00 ldrex r3, [r3] 8013c7a: 60fb str r3, [r7, #12] return(result); 8013c7c: 68fb ldr r3, [r7, #12] 8013c7e: f023 0310 bic.w r3, r3, #16 8013c82: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8013c86: 687b ldr r3, [r7, #4] 8013c88: 681b ldr r3, [r3, #0] 8013c8a: 330c adds r3, #12 8013c8c: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 8013c90: 61fa str r2, [r7, #28] 8013c92: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013c94: 69b9 ldr r1, [r7, #24] 8013c96: 69fa ldr r2, [r7, #28] 8013c98: e841 2300 strex r3, r2, [r1] 8013c9c: 617b str r3, [r7, #20] return(result); 8013c9e: 697b ldr r3, [r7, #20] 8013ca0: 2b00 cmp r3, #0 8013ca2: d1e3 bne.n 8013c6c /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8013ca4: 687b ldr r3, [r7, #4] 8013ca6: 2202 movs r2, #2 8013ca8: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8013caa: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8013cae: 4619 mov r1, r3 8013cb0: 6878 ldr r0, [r7, #4] 8013cb2: f7f9 f977 bl 800cfa4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8013cb6: e023 b.n 8013d00 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8013cb8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013cbc: f003 0380 and.w r3, r3, #128 @ 0x80 8013cc0: 2b00 cmp r3, #0 8013cc2: d009 beq.n 8013cd8 8013cc4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013cc8: f003 0380 and.w r3, r3, #128 @ 0x80 8013ccc: 2b00 cmp r3, #0 8013cce: d003 beq.n 8013cd8 { UART_Transmit_IT(huart); 8013cd0: 6878 ldr r0, [r7, #4] 8013cd2: f000 fb08 bl 80142e6 return; 8013cd6: e014 b.n 8013d02 } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8013cd8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013cdc: f003 0340 and.w r3, r3, #64 @ 0x40 8013ce0: 2b00 cmp r3, #0 8013ce2: d00e beq.n 8013d02 8013ce4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013ce8: f003 0340 and.w r3, r3, #64 @ 0x40 8013cec: 2b00 cmp r3, #0 8013cee: d008 beq.n 8013d02 { UART_EndTransmit_IT(huart); 8013cf0: 6878 ldr r0, [r7, #4] 8013cf2: f000 fb47 bl 8014384 return; 8013cf6: e004 b.n 8013d02 return; 8013cf8: bf00 nop 8013cfa: e002 b.n 8013d02 return; 8013cfc: bf00 nop 8013cfe: e000 b.n 8013d02 return; 8013d00: bf00 nop } } 8013d02: 37e8 adds r7, #232 @ 0xe8 8013d04: 46bd mov sp, r7 8013d06: bd80 pop {r7, pc} 08013d08 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 8013d08: b480 push {r7} 8013d0a: b083 sub sp, #12 8013d0c: af00 add r7, sp, #0 8013d0e: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } 8013d10: bf00 nop 8013d12: 370c adds r7, #12 8013d14: 46bd mov sp, r7 8013d16: bc80 pop {r7} 8013d18: 4770 bx lr 08013d1a : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8013d1a: b480 push {r7} 8013d1c: b083 sub sp, #12 8013d1e: af00 add r7, sp, #0 8013d20: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback could be implemented in the user file */ } 8013d22: bf00 nop 8013d24: 370c adds r7, #12 8013d26: 46bd mov sp, r7 8013d28: bc80 pop {r7} 8013d2a: 4770 bx lr 08013d2c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { 8013d2c: b480 push {r7} 8013d2e: b083 sub sp, #12 8013d30: af00 add r7, sp, #0 8013d32: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback could be implemented in the user file */ } 8013d34: bf00 nop 8013d36: 370c adds r7, #12 8013d38: 46bd mov sp, r7 8013d3a: bc80 pop {r7} 8013d3c: 4770 bx lr 08013d3e : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. * @retval UART Error Code */ uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) { 8013d3e: b480 push {r7} 8013d40: b083 sub sp, #12 8013d42: af00 add r7, sp, #0 8013d44: 6078 str r0, [r7, #4] return huart->ErrorCode; 8013d46: 687b ldr r3, [r7, #4] 8013d48: 6c5b ldr r3, [r3, #68] @ 0x44 } 8013d4a: 4618 mov r0, r3 8013d4c: 370c adds r7, #12 8013d4e: 46bd mov sp, r7 8013d50: bc80 pop {r7} 8013d52: 4770 bx lr 08013d54 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 8013d54: b580 push {r7, lr} 8013d56: b090 sub sp, #64 @ 0x40 8013d58: af00 add r7, sp, #0 8013d5a: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013d5c: 687b ldr r3, [r7, #4] 8013d5e: 6a5b ldr r3, [r3, #36] @ 0x24 8013d60: 63fb str r3, [r7, #60] @ 0x3c /* DMA Normal mode*/ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8013d62: 687b ldr r3, [r7, #4] 8013d64: 681b ldr r3, [r3, #0] 8013d66: 681b ldr r3, [r3, #0] 8013d68: f003 0320 and.w r3, r3, #32 8013d6c: 2b00 cmp r3, #0 8013d6e: d137 bne.n 8013de0 { huart->TxXferCount = 0x00U; 8013d70: 6bfb ldr r3, [r7, #60] @ 0x3c 8013d72: 2200 movs r2, #0 8013d74: 84da strh r2, [r3, #38] @ 0x26 /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8013d76: 6bfb ldr r3, [r7, #60] @ 0x3c 8013d78: 681b ldr r3, [r3, #0] 8013d7a: 3314 adds r3, #20 8013d7c: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013d7e: 6a7b ldr r3, [r7, #36] @ 0x24 8013d80: e853 3f00 ldrex r3, [r3] 8013d84: 623b str r3, [r7, #32] return(result); 8013d86: 6a3b ldr r3, [r7, #32] 8013d88: f023 0380 bic.w r3, r3, #128 @ 0x80 8013d8c: 63bb str r3, [r7, #56] @ 0x38 8013d8e: 6bfb ldr r3, [r7, #60] @ 0x3c 8013d90: 681b ldr r3, [r3, #0] 8013d92: 3314 adds r3, #20 8013d94: 6bba ldr r2, [r7, #56] @ 0x38 8013d96: 633a str r2, [r7, #48] @ 0x30 8013d98: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013d9a: 6af9 ldr r1, [r7, #44] @ 0x2c 8013d9c: 6b3a ldr r2, [r7, #48] @ 0x30 8013d9e: e841 2300 strex r3, r2, [r1] 8013da2: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013da4: 6abb ldr r3, [r7, #40] @ 0x28 8013da6: 2b00 cmp r3, #0 8013da8: d1e5 bne.n 8013d76 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8013daa: 6bfb ldr r3, [r7, #60] @ 0x3c 8013dac: 681b ldr r3, [r3, #0] 8013dae: 330c adds r3, #12 8013db0: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013db2: 693b ldr r3, [r7, #16] 8013db4: e853 3f00 ldrex r3, [r3] 8013db8: 60fb str r3, [r7, #12] return(result); 8013dba: 68fb ldr r3, [r7, #12] 8013dbc: f043 0340 orr.w r3, r3, #64 @ 0x40 8013dc0: 637b str r3, [r7, #52] @ 0x34 8013dc2: 6bfb ldr r3, [r7, #60] @ 0x3c 8013dc4: 681b ldr r3, [r3, #0] 8013dc6: 330c adds r3, #12 8013dc8: 6b7a ldr r2, [r7, #52] @ 0x34 8013dca: 61fa str r2, [r7, #28] 8013dcc: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013dce: 69b9 ldr r1, [r7, #24] 8013dd0: 69fa ldr r2, [r7, #28] 8013dd2: e841 2300 strex r3, r2, [r1] 8013dd6: 617b str r3, [r7, #20] return(result); 8013dd8: 697b ldr r3, [r7, #20] 8013dda: 2b00 cmp r3, #0 8013ddc: d1e5 bne.n 8013daa #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8013dde: e002 b.n 8013de6 HAL_UART_TxCpltCallback(huart); 8013de0: 6bf8 ldr r0, [r7, #60] @ 0x3c 8013de2: f7f9 f959 bl 800d098 } 8013de6: bf00 nop 8013de8: 3740 adds r7, #64 @ 0x40 8013dea: 46bd mov sp, r7 8013dec: bd80 pop {r7, pc} 08013dee : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 8013dee: b580 push {r7, lr} 8013df0: b084 sub sp, #16 8013df2: af00 add r7, sp, #0 8013df4: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013df6: 687b ldr r3, [r7, #4] 8013df8: 6a5b ldr r3, [r3, #36] @ 0x24 8013dfa: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 8013dfc: 68f8 ldr r0, [r7, #12] 8013dfe: f7ff ff83 bl 8013d08 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8013e02: bf00 nop 8013e04: 3710 adds r7, #16 8013e06: 46bd mov sp, r7 8013e08: bd80 pop {r7, pc} 08013e0a : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 8013e0a: b580 push {r7, lr} 8013e0c: b09c sub sp, #112 @ 0x70 8013e0e: af00 add r7, sp, #0 8013e10: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013e12: 687b ldr r3, [r7, #4] 8013e14: 6a5b ldr r3, [r3, #36] @ 0x24 8013e16: 66fb str r3, [r7, #108] @ 0x6c /* DMA Normal mode*/ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8013e18: 687b ldr r3, [r7, #4] 8013e1a: 681b ldr r3, [r3, #0] 8013e1c: 681b ldr r3, [r3, #0] 8013e1e: f003 0320 and.w r3, r3, #32 8013e22: 2b00 cmp r3, #0 8013e24: d172 bne.n 8013f0c { huart->RxXferCount = 0U; 8013e26: 6efb ldr r3, [r7, #108] @ 0x6c 8013e28: 2200 movs r2, #0 8013e2a: 85da strh r2, [r3, #46] @ 0x2e /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8013e2c: 6efb ldr r3, [r7, #108] @ 0x6c 8013e2e: 681b ldr r3, [r3, #0] 8013e30: 330c adds r3, #12 8013e32: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013e34: 6cfb ldr r3, [r7, #76] @ 0x4c 8013e36: e853 3f00 ldrex r3, [r3] 8013e3a: 64bb str r3, [r7, #72] @ 0x48 return(result); 8013e3c: 6cbb ldr r3, [r7, #72] @ 0x48 8013e3e: f423 7380 bic.w r3, r3, #256 @ 0x100 8013e42: 66bb str r3, [r7, #104] @ 0x68 8013e44: 6efb ldr r3, [r7, #108] @ 0x6c 8013e46: 681b ldr r3, [r3, #0] 8013e48: 330c adds r3, #12 8013e4a: 6eba ldr r2, [r7, #104] @ 0x68 8013e4c: 65ba str r2, [r7, #88] @ 0x58 8013e4e: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013e50: 6d79 ldr r1, [r7, #84] @ 0x54 8013e52: 6dba ldr r2, [r7, #88] @ 0x58 8013e54: e841 2300 strex r3, r2, [r1] 8013e58: 653b str r3, [r7, #80] @ 0x50 return(result); 8013e5a: 6d3b ldr r3, [r7, #80] @ 0x50 8013e5c: 2b00 cmp r3, #0 8013e5e: d1e5 bne.n 8013e2c ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013e60: 6efb ldr r3, [r7, #108] @ 0x6c 8013e62: 681b ldr r3, [r3, #0] 8013e64: 3314 adds r3, #20 8013e66: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013e68: 6bbb ldr r3, [r7, #56] @ 0x38 8013e6a: e853 3f00 ldrex r3, [r3] 8013e6e: 637b str r3, [r7, #52] @ 0x34 return(result); 8013e70: 6b7b ldr r3, [r7, #52] @ 0x34 8013e72: f023 0301 bic.w r3, r3, #1 8013e76: 667b str r3, [r7, #100] @ 0x64 8013e78: 6efb ldr r3, [r7, #108] @ 0x6c 8013e7a: 681b ldr r3, [r3, #0] 8013e7c: 3314 adds r3, #20 8013e7e: 6e7a ldr r2, [r7, #100] @ 0x64 8013e80: 647a str r2, [r7, #68] @ 0x44 8013e82: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013e84: 6c39 ldr r1, [r7, #64] @ 0x40 8013e86: 6c7a ldr r2, [r7, #68] @ 0x44 8013e88: e841 2300 strex r3, r2, [r1] 8013e8c: 63fb str r3, [r7, #60] @ 0x3c return(result); 8013e8e: 6bfb ldr r3, [r7, #60] @ 0x3c 8013e90: 2b00 cmp r3, #0 8013e92: d1e5 bne.n 8013e60 /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8013e94: 6efb ldr r3, [r7, #108] @ 0x6c 8013e96: 681b ldr r3, [r3, #0] 8013e98: 3314 adds r3, #20 8013e9a: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013e9c: 6a7b ldr r3, [r7, #36] @ 0x24 8013e9e: e853 3f00 ldrex r3, [r3] 8013ea2: 623b str r3, [r7, #32] return(result); 8013ea4: 6a3b ldr r3, [r7, #32] 8013ea6: f023 0340 bic.w r3, r3, #64 @ 0x40 8013eaa: 663b str r3, [r7, #96] @ 0x60 8013eac: 6efb ldr r3, [r7, #108] @ 0x6c 8013eae: 681b ldr r3, [r3, #0] 8013eb0: 3314 adds r3, #20 8013eb2: 6e3a ldr r2, [r7, #96] @ 0x60 8013eb4: 633a str r2, [r7, #48] @ 0x30 8013eb6: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013eb8: 6af9 ldr r1, [r7, #44] @ 0x2c 8013eba: 6b3a ldr r2, [r7, #48] @ 0x30 8013ebc: e841 2300 strex r3, r2, [r1] 8013ec0: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013ec2: 6abb ldr r3, [r7, #40] @ 0x28 8013ec4: 2b00 cmp r3, #0 8013ec6: d1e5 bne.n 8013e94 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013ec8: 6efb ldr r3, [r7, #108] @ 0x6c 8013eca: 2220 movs r2, #32 8013ecc: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013ed0: 6efb ldr r3, [r7, #108] @ 0x6c 8013ed2: 6b1b ldr r3, [r3, #48] @ 0x30 8013ed4: 2b01 cmp r3, #1 8013ed6: d119 bne.n 8013f0c { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013ed8: 6efb ldr r3, [r7, #108] @ 0x6c 8013eda: 681b ldr r3, [r3, #0] 8013edc: 330c adds r3, #12 8013ede: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013ee0: 693b ldr r3, [r7, #16] 8013ee2: e853 3f00 ldrex r3, [r3] 8013ee6: 60fb str r3, [r7, #12] return(result); 8013ee8: 68fb ldr r3, [r7, #12] 8013eea: f023 0310 bic.w r3, r3, #16 8013eee: 65fb str r3, [r7, #92] @ 0x5c 8013ef0: 6efb ldr r3, [r7, #108] @ 0x6c 8013ef2: 681b ldr r3, [r3, #0] 8013ef4: 330c adds r3, #12 8013ef6: 6dfa ldr r2, [r7, #92] @ 0x5c 8013ef8: 61fa str r2, [r7, #28] 8013efa: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013efc: 69b9 ldr r1, [r7, #24] 8013efe: 69fa ldr r2, [r7, #28] 8013f00: e841 2300 strex r3, r2, [r1] 8013f04: 617b str r3, [r7, #20] return(result); 8013f06: 697b ldr r3, [r7, #20] 8013f08: 2b00 cmp r3, #0 8013f0a: d1e5 bne.n 8013ed8 } } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8013f0c: 6efb ldr r3, [r7, #108] @ 0x6c 8013f0e: 2200 movs r2, #0 8013f10: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013f12: 6efb ldr r3, [r7, #108] @ 0x6c 8013f14: 6b1b ldr r3, [r3, #48] @ 0x30 8013f16: 2b01 cmp r3, #1 8013f18: d106 bne.n 8013f28 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8013f1a: 6efb ldr r3, [r7, #108] @ 0x6c 8013f1c: 8d9b ldrh r3, [r3, #44] @ 0x2c 8013f1e: 4619 mov r1, r3 8013f20: 6ef8 ldr r0, [r7, #108] @ 0x6c 8013f22: f7f9 f83f bl 800cfa4 #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8013f26: e002 b.n 8013f2e HAL_UART_RxCpltCallback(huart); 8013f28: 6ef8 ldr r0, [r7, #108] @ 0x6c 8013f2a: f7ff fef6 bl 8013d1a } 8013f2e: bf00 nop 8013f30: 3770 adds r7, #112 @ 0x70 8013f32: 46bd mov sp, r7 8013f34: bd80 pop {r7, pc} 08013f36 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { 8013f36: b580 push {r7, lr} 8013f38: b084 sub sp, #16 8013f3a: af00 add r7, sp, #0 8013f3c: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013f3e: 687b ldr r3, [r7, #4] 8013f40: 6a5b ldr r3, [r3, #36] @ 0x24 8013f42: 60fb str r3, [r7, #12] /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Half Transfer */ huart->RxEventType = HAL_UART_RXEVENT_HT; 8013f44: 68fb ldr r3, [r7, #12] 8013f46: 2201 movs r2, #1 8013f48: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013f4a: 68fb ldr r3, [r7, #12] 8013f4c: 6b1b ldr r3, [r3, #48] @ 0x30 8013f4e: 2b01 cmp r3, #1 8013f50: d108 bne.n 8013f64 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); 8013f52: 68fb ldr r3, [r7, #12] 8013f54: 8d9b ldrh r3, [r3, #44] @ 0x2c 8013f56: 085b lsrs r3, r3, #1 8013f58: b29b uxth r3, r3 8013f5a: 4619 mov r1, r3 8013f5c: 68f8 ldr r0, [r7, #12] 8013f5e: f7f9 f821 bl 800cfa4 #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8013f62: e002 b.n 8013f6a HAL_UART_RxHalfCpltCallback(huart); 8013f64: 68f8 ldr r0, [r7, #12] 8013f66: f7ff fee1 bl 8013d2c } 8013f6a: bf00 nop 8013f6c: 3710 adds r7, #16 8013f6e: 46bd mov sp, r7 8013f70: bd80 pop {r7, pc} 08013f72 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 8013f72: b580 push {r7, lr} 8013f74: b084 sub sp, #16 8013f76: af00 add r7, sp, #0 8013f78: 6078 str r0, [r7, #4] uint32_t dmarequest = 0x00U; 8013f7a: 2300 movs r3, #0 8013f7c: 60fb str r3, [r7, #12] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013f7e: 687b ldr r3, [r7, #4] 8013f80: 6a5b ldr r3, [r3, #36] @ 0x24 8013f82: 60bb str r3, [r7, #8] /* Stop UART DMA Tx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 8013f84: 68bb ldr r3, [r7, #8] 8013f86: 681b ldr r3, [r3, #0] 8013f88: 695b ldr r3, [r3, #20] 8013f8a: f003 0380 and.w r3, r3, #128 @ 0x80 8013f8e: 2b00 cmp r3, #0 8013f90: bf14 ite ne 8013f92: 2301 movne r3, #1 8013f94: 2300 moveq r3, #0 8013f96: b2db uxtb r3, r3 8013f98: 60fb str r3, [r7, #12] if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 8013f9a: 68bb ldr r3, [r7, #8] 8013f9c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8013fa0: b2db uxtb r3, r3 8013fa2: 2b21 cmp r3, #33 @ 0x21 8013fa4: d108 bne.n 8013fb8 8013fa6: 68fb ldr r3, [r7, #12] 8013fa8: 2b00 cmp r3, #0 8013faa: d005 beq.n 8013fb8 { huart->TxXferCount = 0x00U; 8013fac: 68bb ldr r3, [r7, #8] 8013fae: 2200 movs r2, #0 8013fb0: 84da strh r2, [r3, #38] @ 0x26 UART_EndTxTransfer(huart); 8013fb2: 68b8 ldr r0, [r7, #8] 8013fb4: f000 f8fa bl 80141ac } /* Stop UART DMA Rx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8013fb8: 68bb ldr r3, [r7, #8] 8013fba: 681b ldr r3, [r3, #0] 8013fbc: 695b ldr r3, [r3, #20] 8013fbe: f003 0340 and.w r3, r3, #64 @ 0x40 8013fc2: 2b00 cmp r3, #0 8013fc4: bf14 ite ne 8013fc6: 2301 movne r3, #1 8013fc8: 2300 moveq r3, #0 8013fca: b2db uxtb r3, r3 8013fcc: 60fb str r3, [r7, #12] if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 8013fce: 68bb ldr r3, [r7, #8] 8013fd0: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8013fd4: b2db uxtb r3, r3 8013fd6: 2b22 cmp r3, #34 @ 0x22 8013fd8: d108 bne.n 8013fec 8013fda: 68fb ldr r3, [r7, #12] 8013fdc: 2b00 cmp r3, #0 8013fde: d005 beq.n 8013fec { huart->RxXferCount = 0x00U; 8013fe0: 68bb ldr r3, [r7, #8] 8013fe2: 2200 movs r2, #0 8013fe4: 85da strh r2, [r3, #46] @ 0x2e UART_EndRxTransfer(huart); 8013fe6: 68b8 ldr r0, [r7, #8] 8013fe8: f000 f907 bl 80141fa } huart->ErrorCode |= HAL_UART_ERROR_DMA; 8013fec: 68bb ldr r3, [r7, #8] 8013fee: 6c5b ldr r3, [r3, #68] @ 0x44 8013ff0: f043 0210 orr.w r2, r3, #16 8013ff4: 68bb ldr r3, [r7, #8] 8013ff6: 645a str r2, [r3, #68] @ 0x44 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013ff8: 68b8 ldr r0, [r7, #8] 8013ffa: f7f8 f889 bl 800c110 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8013ffe: bf00 nop 8014000: 3710 adds r7, #16 8014002: 46bd mov sp, r7 8014004: bd80 pop {r7, pc} 08014006 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8014006: b480 push {r7} 8014008: b085 sub sp, #20 801400a: af00 add r7, sp, #0 801400c: 60f8 str r0, [r7, #12] 801400e: 60b9 str r1, [r7, #8] 8014010: 4613 mov r3, r2 8014012: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 8014014: 68fb ldr r3, [r7, #12] 8014016: 68ba ldr r2, [r7, #8] 8014018: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 801401a: 68fb ldr r3, [r7, #12] 801401c: 88fa ldrh r2, [r7, #6] 801401e: 859a strh r2, [r3, #44] @ 0x2c huart->RxXferCount = Size; 8014020: 68fb ldr r3, [r7, #12] 8014022: 88fa ldrh r2, [r7, #6] 8014024: 85da strh r2, [r3, #46] @ 0x2e huart->ErrorCode = HAL_UART_ERROR_NONE; 8014026: 68fb ldr r3, [r7, #12] 8014028: 2200 movs r2, #0 801402a: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 801402c: 68fb ldr r3, [r7, #12] 801402e: 2222 movs r2, #34 @ 0x22 8014030: f883 2042 strb.w r2, [r3, #66] @ 0x42 if (huart->Init.Parity != UART_PARITY_NONE) 8014034: 68fb ldr r3, [r7, #12] 8014036: 691b ldr r3, [r3, #16] 8014038: 2b00 cmp r3, #0 801403a: d007 beq.n 801404c { /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); 801403c: 68fb ldr r3, [r7, #12] 801403e: 681b ldr r3, [r3, #0] 8014040: 68da ldr r2, [r3, #12] 8014042: 68fb ldr r3, [r7, #12] 8014044: 681b ldr r3, [r3, #0] 8014046: f442 7280 orr.w r2, r2, #256 @ 0x100 801404a: 60da str r2, [r3, #12] } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); 801404c: 68fb ldr r3, [r7, #12] 801404e: 681b ldr r3, [r3, #0] 8014050: 695a ldr r2, [r3, #20] 8014052: 68fb ldr r3, [r7, #12] 8014054: 681b ldr r3, [r3, #0] 8014056: f042 0201 orr.w r2, r2, #1 801405a: 615a str r2, [r3, #20] /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); 801405c: 68fb ldr r3, [r7, #12] 801405e: 681b ldr r3, [r3, #0] 8014060: 68da ldr r2, [r3, #12] 8014062: 68fb ldr r3, [r7, #12] 8014064: 681b ldr r3, [r3, #0] 8014066: f042 0220 orr.w r2, r2, #32 801406a: 60da str r2, [r3, #12] return HAL_OK; 801406c: 2300 movs r3, #0 } 801406e: 4618 mov r0, r3 8014070: 3714 adds r7, #20 8014072: 46bd mov sp, r7 8014074: bc80 pop {r7} 8014076: 4770 bx lr 08014078 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8014078: b580 push {r7, lr} 801407a: b098 sub sp, #96 @ 0x60 801407c: af00 add r7, sp, #0 801407e: 60f8 str r0, [r7, #12] 8014080: 60b9 str r1, [r7, #8] 8014082: 4613 mov r3, r2 8014084: 80fb strh r3, [r7, #6] uint32_t *tmp; huart->pRxBuffPtr = pData; 8014086: 68ba ldr r2, [r7, #8] 8014088: 68fb ldr r3, [r7, #12] 801408a: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 801408c: 68fb ldr r3, [r7, #12] 801408e: 88fa ldrh r2, [r7, #6] 8014090: 859a strh r2, [r3, #44] @ 0x2c huart->ErrorCode = HAL_UART_ERROR_NONE; 8014092: 68fb ldr r3, [r7, #12] 8014094: 2200 movs r2, #0 8014096: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 8014098: 68fb ldr r3, [r7, #12] 801409a: 2222 movs r2, #34 @ 0x22 801409c: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 80140a0: 68fb ldr r3, [r7, #12] 80140a2: 6bdb ldr r3, [r3, #60] @ 0x3c 80140a4: 4a3e ldr r2, [pc, #248] @ (80141a0 ) 80140a6: 629a str r2, [r3, #40] @ 0x28 /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 80140a8: 68fb ldr r3, [r7, #12] 80140aa: 6bdb ldr r3, [r3, #60] @ 0x3c 80140ac: 4a3d ldr r2, [pc, #244] @ (80141a4 ) 80140ae: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; 80140b0: 68fb ldr r3, [r7, #12] 80140b2: 6bdb ldr r3, [r3, #60] @ 0x3c 80140b4: 4a3c ldr r2, [pc, #240] @ (80141a8 ) 80140b6: 631a str r2, [r3, #48] @ 0x30 /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; 80140b8: 68fb ldr r3, [r7, #12] 80140ba: 6bdb ldr r3, [r3, #60] @ 0x3c 80140bc: 2200 movs r2, #0 80140be: 635a str r2, [r3, #52] @ 0x34 /* Enable the DMA stream */ tmp = (uint32_t *)&pData; 80140c0: f107 0308 add.w r3, r7, #8 80140c4: 65fb str r3, [r7, #92] @ 0x5c HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size); 80140c6: 68fb ldr r3, [r7, #12] 80140c8: 6bd8 ldr r0, [r3, #60] @ 0x3c 80140ca: 68fb ldr r3, [r7, #12] 80140cc: 681b ldr r3, [r3, #0] 80140ce: 3304 adds r3, #4 80140d0: 4619 mov r1, r3 80140d2: 6dfb ldr r3, [r7, #92] @ 0x5c 80140d4: 681a ldr r2, [r3, #0] 80140d6: 88fb ldrh r3, [r7, #6] 80140d8: f7fc f93a bl 8010350 /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); 80140dc: 2300 movs r3, #0 80140de: 613b str r3, [r7, #16] 80140e0: 68fb ldr r3, [r7, #12] 80140e2: 681b ldr r3, [r3, #0] 80140e4: 681b ldr r3, [r3, #0] 80140e6: 613b str r3, [r7, #16] 80140e8: 68fb ldr r3, [r7, #12] 80140ea: 681b ldr r3, [r3, #0] 80140ec: 685b ldr r3, [r3, #4] 80140ee: 613b str r3, [r7, #16] 80140f0: 693b ldr r3, [r7, #16] if (huart->Init.Parity != UART_PARITY_NONE) 80140f2: 68fb ldr r3, [r7, #12] 80140f4: 691b ldr r3, [r3, #16] 80140f6: 2b00 cmp r3, #0 80140f8: d019 beq.n 801412e { /* Enable the UART Parity Error Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80140fa: 68fb ldr r3, [r7, #12] 80140fc: 681b ldr r3, [r3, #0] 80140fe: 330c adds r3, #12 8014100: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8014102: 6c3b ldr r3, [r7, #64] @ 0x40 8014104: e853 3f00 ldrex r3, [r3] 8014108: 63fb str r3, [r7, #60] @ 0x3c return(result); 801410a: 6bfb ldr r3, [r7, #60] @ 0x3c 801410c: f443 7380 orr.w r3, r3, #256 @ 0x100 8014110: 65bb str r3, [r7, #88] @ 0x58 8014112: 68fb ldr r3, [r7, #12] 8014114: 681b ldr r3, [r3, #0] 8014116: 330c adds r3, #12 8014118: 6dba ldr r2, [r7, #88] @ 0x58 801411a: 64fa str r2, [r7, #76] @ 0x4c 801411c: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801411e: 6cb9 ldr r1, [r7, #72] @ 0x48 8014120: 6cfa ldr r2, [r7, #76] @ 0x4c 8014122: e841 2300 strex r3, r2, [r1] 8014126: 647b str r3, [r7, #68] @ 0x44 return(result); 8014128: 6c7b ldr r3, [r7, #68] @ 0x44 801412a: 2b00 cmp r3, #0 801412c: d1e5 bne.n 80140fa } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 801412e: 68fb ldr r3, [r7, #12] 8014130: 681b ldr r3, [r3, #0] 8014132: 3314 adds r3, #20 8014134: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8014136: 6afb ldr r3, [r7, #44] @ 0x2c 8014138: e853 3f00 ldrex r3, [r3] 801413c: 62bb str r3, [r7, #40] @ 0x28 return(result); 801413e: 6abb ldr r3, [r7, #40] @ 0x28 8014140: f043 0301 orr.w r3, r3, #1 8014144: 657b str r3, [r7, #84] @ 0x54 8014146: 68fb ldr r3, [r7, #12] 8014148: 681b ldr r3, [r3, #0] 801414a: 3314 adds r3, #20 801414c: 6d7a ldr r2, [r7, #84] @ 0x54 801414e: 63ba str r2, [r7, #56] @ 0x38 8014150: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8014152: 6b79 ldr r1, [r7, #52] @ 0x34 8014154: 6bba ldr r2, [r7, #56] @ 0x38 8014156: e841 2300 strex r3, r2, [r1] 801415a: 633b str r3, [r7, #48] @ 0x30 return(result); 801415c: 6b3b ldr r3, [r7, #48] @ 0x30 801415e: 2b00 cmp r3, #0 8014160: d1e5 bne.n 801412e /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8014162: 68fb ldr r3, [r7, #12] 8014164: 681b ldr r3, [r3, #0] 8014166: 3314 adds r3, #20 8014168: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801416a: 69bb ldr r3, [r7, #24] 801416c: e853 3f00 ldrex r3, [r3] 8014170: 617b str r3, [r7, #20] return(result); 8014172: 697b ldr r3, [r7, #20] 8014174: f043 0340 orr.w r3, r3, #64 @ 0x40 8014178: 653b str r3, [r7, #80] @ 0x50 801417a: 68fb ldr r3, [r7, #12] 801417c: 681b ldr r3, [r3, #0] 801417e: 3314 adds r3, #20 8014180: 6d3a ldr r2, [r7, #80] @ 0x50 8014182: 627a str r2, [r7, #36] @ 0x24 8014184: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8014186: 6a39 ldr r1, [r7, #32] 8014188: 6a7a ldr r2, [r7, #36] @ 0x24 801418a: e841 2300 strex r3, r2, [r1] 801418e: 61fb str r3, [r7, #28] return(result); 8014190: 69fb ldr r3, [r7, #28] 8014192: 2b00 cmp r3, #0 8014194: d1e5 bne.n 8014162 return HAL_OK; 8014196: 2300 movs r3, #0 } 8014198: 4618 mov r0, r3 801419a: 3760 adds r7, #96 @ 0x60 801419c: 46bd mov sp, r7 801419e: bd80 pop {r7, pc} 80141a0: 08013e0b .word 0x08013e0b 80141a4: 08013f37 .word 0x08013f37 80141a8: 08013f73 .word 0x08013f73 080141ac : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 80141ac: b480 push {r7} 80141ae: b089 sub sp, #36 @ 0x24 80141b0: af00 add r7, sp, #0 80141b2: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 80141b4: 687b ldr r3, [r7, #4] 80141b6: 681b ldr r3, [r3, #0] 80141b8: 330c adds r3, #12 80141ba: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80141bc: 68fb ldr r3, [r7, #12] 80141be: e853 3f00 ldrex r3, [r3] 80141c2: 60bb str r3, [r7, #8] return(result); 80141c4: 68bb ldr r3, [r7, #8] 80141c6: f023 03c0 bic.w r3, r3, #192 @ 0xc0 80141ca: 61fb str r3, [r7, #28] 80141cc: 687b ldr r3, [r7, #4] 80141ce: 681b ldr r3, [r3, #0] 80141d0: 330c adds r3, #12 80141d2: 69fa ldr r2, [r7, #28] 80141d4: 61ba str r2, [r7, #24] 80141d6: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80141d8: 6979 ldr r1, [r7, #20] 80141da: 69ba ldr r2, [r7, #24] 80141dc: e841 2300 strex r3, r2, [r1] 80141e0: 613b str r3, [r7, #16] return(result); 80141e2: 693b ldr r3, [r7, #16] 80141e4: 2b00 cmp r3, #0 80141e6: d1e5 bne.n 80141b4 /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80141e8: 687b ldr r3, [r7, #4] 80141ea: 2220 movs r2, #32 80141ec: f883 2041 strb.w r2, [r3, #65] @ 0x41 } 80141f0: bf00 nop 80141f2: 3724 adds r7, #36 @ 0x24 80141f4: 46bd mov sp, r7 80141f6: bc80 pop {r7} 80141f8: 4770 bx lr 080141fa : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 80141fa: b480 push {r7} 80141fc: b095 sub sp, #84 @ 0x54 80141fe: af00 add r7, sp, #0 8014200: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8014202: 687b ldr r3, [r7, #4] 8014204: 681b ldr r3, [r3, #0] 8014206: 330c adds r3, #12 8014208: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801420a: 6b7b ldr r3, [r7, #52] @ 0x34 801420c: e853 3f00 ldrex r3, [r3] 8014210: 633b str r3, [r7, #48] @ 0x30 return(result); 8014212: 6b3b ldr r3, [r7, #48] @ 0x30 8014214: f423 7390 bic.w r3, r3, #288 @ 0x120 8014218: 64fb str r3, [r7, #76] @ 0x4c 801421a: 687b ldr r3, [r7, #4] 801421c: 681b ldr r3, [r3, #0] 801421e: 330c adds r3, #12 8014220: 6cfa ldr r2, [r7, #76] @ 0x4c 8014222: 643a str r2, [r7, #64] @ 0x40 8014224: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8014226: 6bf9 ldr r1, [r7, #60] @ 0x3c 8014228: 6c3a ldr r2, [r7, #64] @ 0x40 801422a: e841 2300 strex r3, r2, [r1] 801422e: 63bb str r3, [r7, #56] @ 0x38 return(result); 8014230: 6bbb ldr r3, [r7, #56] @ 0x38 8014232: 2b00 cmp r3, #0 8014234: d1e5 bne.n 8014202 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8014236: 687b ldr r3, [r7, #4] 8014238: 681b ldr r3, [r3, #0] 801423a: 3314 adds r3, #20 801423c: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801423e: 6a3b ldr r3, [r7, #32] 8014240: e853 3f00 ldrex r3, [r3] 8014244: 61fb str r3, [r7, #28] return(result); 8014246: 69fb ldr r3, [r7, #28] 8014248: f023 0301 bic.w r3, r3, #1 801424c: 64bb str r3, [r7, #72] @ 0x48 801424e: 687b ldr r3, [r7, #4] 8014250: 681b ldr r3, [r3, #0] 8014252: 3314 adds r3, #20 8014254: 6cba ldr r2, [r7, #72] @ 0x48 8014256: 62fa str r2, [r7, #44] @ 0x2c 8014258: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801425a: 6ab9 ldr r1, [r7, #40] @ 0x28 801425c: 6afa ldr r2, [r7, #44] @ 0x2c 801425e: e841 2300 strex r3, r2, [r1] 8014262: 627b str r3, [r7, #36] @ 0x24 return(result); 8014264: 6a7b ldr r3, [r7, #36] @ 0x24 8014266: 2b00 cmp r3, #0 8014268: d1e5 bne.n 8014236 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 801426a: 687b ldr r3, [r7, #4] 801426c: 6b1b ldr r3, [r3, #48] @ 0x30 801426e: 2b01 cmp r3, #1 8014270: d119 bne.n 80142a6 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8014272: 687b ldr r3, [r7, #4] 8014274: 681b ldr r3, [r3, #0] 8014276: 330c adds r3, #12 8014278: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801427a: 68fb ldr r3, [r7, #12] 801427c: e853 3f00 ldrex r3, [r3] 8014280: 60bb str r3, [r7, #8] return(result); 8014282: 68bb ldr r3, [r7, #8] 8014284: f023 0310 bic.w r3, r3, #16 8014288: 647b str r3, [r7, #68] @ 0x44 801428a: 687b ldr r3, [r7, #4] 801428c: 681b ldr r3, [r3, #0] 801428e: 330c adds r3, #12 8014290: 6c7a ldr r2, [r7, #68] @ 0x44 8014292: 61ba str r2, [r7, #24] 8014294: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8014296: 6979 ldr r1, [r7, #20] 8014298: 69ba ldr r2, [r7, #24] 801429a: e841 2300 strex r3, r2, [r1] 801429e: 613b str r3, [r7, #16] return(result); 80142a0: 693b ldr r3, [r7, #16] 80142a2: 2b00 cmp r3, #0 80142a4: d1e5 bne.n 8014272 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80142a6: 687b ldr r3, [r7, #4] 80142a8: 2220 movs r2, #32 80142aa: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80142ae: 687b ldr r3, [r7, #4] 80142b0: 2200 movs r2, #0 80142b2: 631a str r2, [r3, #48] @ 0x30 } 80142b4: bf00 nop 80142b6: 3754 adds r7, #84 @ 0x54 80142b8: 46bd mov sp, r7 80142ba: bc80 pop {r7} 80142bc: 4770 bx lr 080142be : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 80142be: b580 push {r7, lr} 80142c0: b084 sub sp, #16 80142c2: af00 add r7, sp, #0 80142c4: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80142c6: 687b ldr r3, [r7, #4] 80142c8: 6a5b ldr r3, [r3, #36] @ 0x24 80142ca: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 80142cc: 68fb ldr r3, [r7, #12] 80142ce: 2200 movs r2, #0 80142d0: 85da strh r2, [r3, #46] @ 0x2e huart->TxXferCount = 0x00U; 80142d2: 68fb ldr r3, [r7, #12] 80142d4: 2200 movs r2, #0 80142d6: 84da strh r2, [r3, #38] @ 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80142d8: 68f8 ldr r0, [r7, #12] 80142da: f7f7 ff19 bl 800c110 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80142de: bf00 nop 80142e0: 3710 adds r7, #16 80142e2: 46bd mov sp, r7 80142e4: bd80 pop {r7, pc} 080142e6 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 80142e6: b480 push {r7} 80142e8: b085 sub sp, #20 80142ea: af00 add r7, sp, #0 80142ec: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 80142ee: 687b ldr r3, [r7, #4] 80142f0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80142f4: b2db uxtb r3, r3 80142f6: 2b21 cmp r3, #33 @ 0x21 80142f8: d13e bne.n 8014378 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80142fa: 687b ldr r3, [r7, #4] 80142fc: 689b ldr r3, [r3, #8] 80142fe: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8014302: d114 bne.n 801432e 8014304: 687b ldr r3, [r7, #4] 8014306: 691b ldr r3, [r3, #16] 8014308: 2b00 cmp r3, #0 801430a: d110 bne.n 801432e { tmp = (const uint16_t *) huart->pTxBuffPtr; 801430c: 687b ldr r3, [r7, #4] 801430e: 6a1b ldr r3, [r3, #32] 8014310: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8014312: 68fb ldr r3, [r7, #12] 8014314: 881b ldrh r3, [r3, #0] 8014316: 461a mov r2, r3 8014318: 687b ldr r3, [r7, #4] 801431a: 681b ldr r3, [r3, #0] 801431c: f3c2 0208 ubfx r2, r2, #0, #9 8014320: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 8014322: 687b ldr r3, [r7, #4] 8014324: 6a1b ldr r3, [r3, #32] 8014326: 1c9a adds r2, r3, #2 8014328: 687b ldr r3, [r7, #4] 801432a: 621a str r2, [r3, #32] 801432c: e008 b.n 8014340 } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 801432e: 687b ldr r3, [r7, #4] 8014330: 6a1b ldr r3, [r3, #32] 8014332: 1c59 adds r1, r3, #1 8014334: 687a ldr r2, [r7, #4] 8014336: 6211 str r1, [r2, #32] 8014338: 781a ldrb r2, [r3, #0] 801433a: 687b ldr r3, [r7, #4] 801433c: 681b ldr r3, [r3, #0] 801433e: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 8014340: 687b ldr r3, [r7, #4] 8014342: 8cdb ldrh r3, [r3, #38] @ 0x26 8014344: b29b uxth r3, r3 8014346: 3b01 subs r3, #1 8014348: b29b uxth r3, r3 801434a: 687a ldr r2, [r7, #4] 801434c: 4619 mov r1, r3 801434e: 84d1 strh r1, [r2, #38] @ 0x26 8014350: 2b00 cmp r3, #0 8014352: d10f bne.n 8014374 { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8014354: 687b ldr r3, [r7, #4] 8014356: 681b ldr r3, [r3, #0] 8014358: 68da ldr r2, [r3, #12] 801435a: 687b ldr r3, [r7, #4] 801435c: 681b ldr r3, [r3, #0] 801435e: f022 0280 bic.w r2, r2, #128 @ 0x80 8014362: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8014364: 687b ldr r3, [r7, #4] 8014366: 681b ldr r3, [r3, #0] 8014368: 68da ldr r2, [r3, #12] 801436a: 687b ldr r3, [r7, #4] 801436c: 681b ldr r3, [r3, #0] 801436e: f042 0240 orr.w r2, r2, #64 @ 0x40 8014372: 60da str r2, [r3, #12] } return HAL_OK; 8014374: 2300 movs r3, #0 8014376: e000 b.n 801437a } else { return HAL_BUSY; 8014378: 2302 movs r3, #2 } } 801437a: 4618 mov r0, r3 801437c: 3714 adds r7, #20 801437e: 46bd mov sp, r7 8014380: bc80 pop {r7} 8014382: 4770 bx lr 08014384 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8014384: b580 push {r7, lr} 8014386: b082 sub sp, #8 8014388: af00 add r7, sp, #0 801438a: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 801438c: 687b ldr r3, [r7, #4] 801438e: 681b ldr r3, [r3, #0] 8014390: 68da ldr r2, [r3, #12] 8014392: 687b ldr r3, [r7, #4] 8014394: 681b ldr r3, [r3, #0] 8014396: f022 0240 bic.w r2, r2, #64 @ 0x40 801439a: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 801439c: 687b ldr r3, [r7, #4] 801439e: 2220 movs r2, #32 80143a0: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 80143a4: 6878 ldr r0, [r7, #4] 80143a6: f7f8 fe77 bl 800d098 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 80143aa: 2300 movs r3, #0 } 80143ac: 4618 mov r0, r3 80143ae: 3708 adds r7, #8 80143b0: 46bd mov sp, r7 80143b2: bd80 pop {r7, pc} 080143b4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 80143b4: b580 push {r7, lr} 80143b6: b08c sub sp, #48 @ 0x30 80143b8: af00 add r7, sp, #0 80143ba: 6078 str r0, [r7, #4] uint8_t *pdata8bits; uint16_t *pdata16bits; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80143bc: 687b ldr r3, [r7, #4] 80143be: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 80143c2: b2db uxtb r3, r3 80143c4: 2b22 cmp r3, #34 @ 0x22 80143c6: f040 80ae bne.w 8014526 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80143ca: 687b ldr r3, [r7, #4] 80143cc: 689b ldr r3, [r3, #8] 80143ce: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80143d2: d117 bne.n 8014404 80143d4: 687b ldr r3, [r7, #4] 80143d6: 691b ldr r3, [r3, #16] 80143d8: 2b00 cmp r3, #0 80143da: d113 bne.n 8014404 { pdata8bits = NULL; 80143dc: 2300 movs r3, #0 80143de: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = (uint16_t *) huart->pRxBuffPtr; 80143e0: 687b ldr r3, [r7, #4] 80143e2: 6a9b ldr r3, [r3, #40] @ 0x28 80143e4: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 80143e6: 687b ldr r3, [r7, #4] 80143e8: 681b ldr r3, [r3, #0] 80143ea: 685b ldr r3, [r3, #4] 80143ec: b29b uxth r3, r3 80143ee: f3c3 0308 ubfx r3, r3, #0, #9 80143f2: b29a uxth r2, r3 80143f4: 6abb ldr r3, [r7, #40] @ 0x28 80143f6: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 80143f8: 687b ldr r3, [r7, #4] 80143fa: 6a9b ldr r3, [r3, #40] @ 0x28 80143fc: 1c9a adds r2, r3, #2 80143fe: 687b ldr r3, [r7, #4] 8014400: 629a str r2, [r3, #40] @ 0x28 8014402: e026 b.n 8014452 } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8014404: 687b ldr r3, [r7, #4] 8014406: 6a9b ldr r3, [r3, #40] @ 0x28 8014408: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = NULL; 801440a: 2300 movs r3, #0 801440c: 62bb str r3, [r7, #40] @ 0x28 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 801440e: 687b ldr r3, [r7, #4] 8014410: 689b ldr r3, [r3, #8] 8014412: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8014416: d007 beq.n 8014428 8014418: 687b ldr r3, [r7, #4] 801441a: 689b ldr r3, [r3, #8] 801441c: 2b00 cmp r3, #0 801441e: d10a bne.n 8014436 8014420: 687b ldr r3, [r7, #4] 8014422: 691b ldr r3, [r3, #16] 8014424: 2b00 cmp r3, #0 8014426: d106 bne.n 8014436 { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8014428: 687b ldr r3, [r7, #4] 801442a: 681b ldr r3, [r3, #0] 801442c: 685b ldr r3, [r3, #4] 801442e: b2da uxtb r2, r3 8014430: 6afb ldr r3, [r7, #44] @ 0x2c 8014432: 701a strb r2, [r3, #0] 8014434: e008 b.n 8014448 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8014436: 687b ldr r3, [r7, #4] 8014438: 681b ldr r3, [r3, #0] 801443a: 685b ldr r3, [r3, #4] 801443c: b2db uxtb r3, r3 801443e: f003 037f and.w r3, r3, #127 @ 0x7f 8014442: b2da uxtb r2, r3 8014444: 6afb ldr r3, [r7, #44] @ 0x2c 8014446: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8014448: 687b ldr r3, [r7, #4] 801444a: 6a9b ldr r3, [r3, #40] @ 0x28 801444c: 1c5a adds r2, r3, #1 801444e: 687b ldr r3, [r7, #4] 8014450: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 8014452: 687b ldr r3, [r7, #4] 8014454: 8ddb ldrh r3, [r3, #46] @ 0x2e 8014456: b29b uxth r3, r3 8014458: 3b01 subs r3, #1 801445a: b29b uxth r3, r3 801445c: 687a ldr r2, [r7, #4] 801445e: 4619 mov r1, r3 8014460: 85d1 strh r1, [r2, #46] @ 0x2e 8014462: 2b00 cmp r3, #0 8014464: d15d bne.n 8014522 { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8014466: 687b ldr r3, [r7, #4] 8014468: 681b ldr r3, [r3, #0] 801446a: 68da ldr r2, [r3, #12] 801446c: 687b ldr r3, [r7, #4] 801446e: 681b ldr r3, [r3, #0] 8014470: f022 0220 bic.w r2, r2, #32 8014474: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8014476: 687b ldr r3, [r7, #4] 8014478: 681b ldr r3, [r3, #0] 801447a: 68da ldr r2, [r3, #12] 801447c: 687b ldr r3, [r7, #4] 801447e: 681b ldr r3, [r3, #0] 8014480: f422 7280 bic.w r2, r2, #256 @ 0x100 8014484: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8014486: 687b ldr r3, [r7, #4] 8014488: 681b ldr r3, [r3, #0] 801448a: 695a ldr r2, [r3, #20] 801448c: 687b ldr r3, [r7, #4] 801448e: 681b ldr r3, [r3, #0] 8014490: f022 0201 bic.w r2, r2, #1 8014494: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8014496: 687b ldr r3, [r7, #4] 8014498: 2220 movs r2, #32 801449a: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 801449e: 687b ldr r3, [r7, #4] 80144a0: 2200 movs r2, #0 80144a2: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80144a4: 687b ldr r3, [r7, #4] 80144a6: 6b1b ldr r3, [r3, #48] @ 0x30 80144a8: 2b01 cmp r3, #1 80144aa: d135 bne.n 8014518 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80144ac: 687b ldr r3, [r7, #4] 80144ae: 2200 movs r2, #0 80144b0: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80144b2: 687b ldr r3, [r7, #4] 80144b4: 681b ldr r3, [r3, #0] 80144b6: 330c adds r3, #12 80144b8: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80144ba: 697b ldr r3, [r7, #20] 80144bc: e853 3f00 ldrex r3, [r3] 80144c0: 613b str r3, [r7, #16] return(result); 80144c2: 693b ldr r3, [r7, #16] 80144c4: f023 0310 bic.w r3, r3, #16 80144c8: 627b str r3, [r7, #36] @ 0x24 80144ca: 687b ldr r3, [r7, #4] 80144cc: 681b ldr r3, [r3, #0] 80144ce: 330c adds r3, #12 80144d0: 6a7a ldr r2, [r7, #36] @ 0x24 80144d2: 623a str r2, [r7, #32] 80144d4: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80144d6: 69f9 ldr r1, [r7, #28] 80144d8: 6a3a ldr r2, [r7, #32] 80144da: e841 2300 strex r3, r2, [r1] 80144de: 61bb str r3, [r7, #24] return(result); 80144e0: 69bb ldr r3, [r7, #24] 80144e2: 2b00 cmp r3, #0 80144e4: d1e5 bne.n 80144b2 /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 80144e6: 687b ldr r3, [r7, #4] 80144e8: 681b ldr r3, [r3, #0] 80144ea: 681b ldr r3, [r3, #0] 80144ec: f003 0310 and.w r3, r3, #16 80144f0: 2b10 cmp r3, #16 80144f2: d10a bne.n 801450a { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 80144f4: 2300 movs r3, #0 80144f6: 60fb str r3, [r7, #12] 80144f8: 687b ldr r3, [r7, #4] 80144fa: 681b ldr r3, [r3, #0] 80144fc: 681b ldr r3, [r3, #0] 80144fe: 60fb str r3, [r7, #12] 8014500: 687b ldr r3, [r7, #4] 8014502: 681b ldr r3, [r3, #0] 8014504: 685b ldr r3, [r3, #4] 8014506: 60fb str r3, [r7, #12] 8014508: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 801450a: 687b ldr r3, [r7, #4] 801450c: 8d9b ldrh r3, [r3, #44] @ 0x2c 801450e: 4619 mov r1, r3 8014510: 6878 ldr r0, [r7, #4] 8014512: f7f8 fd47 bl 800cfa4 8014516: e002 b.n 801451e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8014518: 6878 ldr r0, [r7, #4] 801451a: f7ff fbfe bl 8013d1a #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 801451e: 2300 movs r3, #0 8014520: e002 b.n 8014528 } return HAL_OK; 8014522: 2300 movs r3, #0 8014524: e000 b.n 8014528 } else { return HAL_BUSY; 8014526: 2302 movs r3, #2 } } 8014528: 4618 mov r0, r3 801452a: 3730 adds r7, #48 @ 0x30 801452c: 46bd mov sp, r7 801452e: bd80 pop {r7, pc} 08014530 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8014530: b580 push {r7, lr} 8014532: b084 sub sp, #16 8014534: af00 add r7, sp, #0 8014536: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8014538: 687b ldr r3, [r7, #4] 801453a: 681b ldr r3, [r3, #0] 801453c: 691b ldr r3, [r3, #16] 801453e: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8014542: 687b ldr r3, [r7, #4] 8014544: 68da ldr r2, [r3, #12] 8014546: 687b ldr r3, [r7, #4] 8014548: 681b ldr r3, [r3, #0] 801454a: 430a orrs r2, r1 801454c: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 801454e: 687b ldr r3, [r7, #4] 8014550: 689a ldr r2, [r3, #8] 8014552: 687b ldr r3, [r7, #4] 8014554: 691b ldr r3, [r3, #16] 8014556: 431a orrs r2, r3 8014558: 687b ldr r3, [r7, #4] 801455a: 695b ldr r3, [r3, #20] 801455c: 4313 orrs r3, r2 801455e: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 8014560: 687b ldr r3, [r7, #4] 8014562: 681b ldr r3, [r3, #0] 8014564: 68db ldr r3, [r3, #12] 8014566: f423 53b0 bic.w r3, r3, #5632 @ 0x1600 801456a: f023 030c bic.w r3, r3, #12 801456e: 687a ldr r2, [r7, #4] 8014570: 6812 ldr r2, [r2, #0] 8014572: 68b9 ldr r1, [r7, #8] 8014574: 430b orrs r3, r1 8014576: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8014578: 687b ldr r3, [r7, #4] 801457a: 681b ldr r3, [r3, #0] 801457c: 695b ldr r3, [r3, #20] 801457e: f423 7140 bic.w r1, r3, #768 @ 0x300 8014582: 687b ldr r3, [r7, #4] 8014584: 699a ldr r2, [r3, #24] 8014586: 687b ldr r3, [r7, #4] 8014588: 681b ldr r3, [r3, #0] 801458a: 430a orrs r2, r1 801458c: 615a str r2, [r3, #20] if(huart->Instance == USART1) 801458e: 687b ldr r3, [r7, #4] 8014590: 681b ldr r3, [r3, #0] 8014592: 4a2c ldr r2, [pc, #176] @ (8014644 ) 8014594: 4293 cmp r3, r2 8014596: d103 bne.n 80145a0 { pclk = HAL_RCC_GetPCLK2Freq(); 8014598: f7fd fa5c bl 8011a54 801459c: 60f8 str r0, [r7, #12] 801459e: e002 b.n 80145a6 } else { pclk = HAL_RCC_GetPCLK1Freq(); 80145a0: f7fd fa44 bl 8011a2c 80145a4: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 80145a6: 68fa ldr r2, [r7, #12] 80145a8: 4613 mov r3, r2 80145aa: 009b lsls r3, r3, #2 80145ac: 4413 add r3, r2 80145ae: 009a lsls r2, r3, #2 80145b0: 441a add r2, r3 80145b2: 687b ldr r3, [r7, #4] 80145b4: 685b ldr r3, [r3, #4] 80145b6: 009b lsls r3, r3, #2 80145b8: fbb2 f3f3 udiv r3, r2, r3 80145bc: 4a22 ldr r2, [pc, #136] @ (8014648 ) 80145be: fba2 2303 umull r2, r3, r2, r3 80145c2: 095b lsrs r3, r3, #5 80145c4: 0119 lsls r1, r3, #4 80145c6: 68fa ldr r2, [r7, #12] 80145c8: 4613 mov r3, r2 80145ca: 009b lsls r3, r3, #2 80145cc: 4413 add r3, r2 80145ce: 009a lsls r2, r3, #2 80145d0: 441a add r2, r3 80145d2: 687b ldr r3, [r7, #4] 80145d4: 685b ldr r3, [r3, #4] 80145d6: 009b lsls r3, r3, #2 80145d8: fbb2 f2f3 udiv r2, r2, r3 80145dc: 4b1a ldr r3, [pc, #104] @ (8014648 ) 80145de: fba3 0302 umull r0, r3, r3, r2 80145e2: 095b lsrs r3, r3, #5 80145e4: 2064 movs r0, #100 @ 0x64 80145e6: fb00 f303 mul.w r3, r0, r3 80145ea: 1ad3 subs r3, r2, r3 80145ec: 011b lsls r3, r3, #4 80145ee: 3332 adds r3, #50 @ 0x32 80145f0: 4a15 ldr r2, [pc, #84] @ (8014648 ) 80145f2: fba2 2303 umull r2, r3, r2, r3 80145f6: 095b lsrs r3, r3, #5 80145f8: f003 03f0 and.w r3, r3, #240 @ 0xf0 80145fc: 4419 add r1, r3 80145fe: 68fa ldr r2, [r7, #12] 8014600: 4613 mov r3, r2 8014602: 009b lsls r3, r3, #2 8014604: 4413 add r3, r2 8014606: 009a lsls r2, r3, #2 8014608: 441a add r2, r3 801460a: 687b ldr r3, [r7, #4] 801460c: 685b ldr r3, [r3, #4] 801460e: 009b lsls r3, r3, #2 8014610: fbb2 f2f3 udiv r2, r2, r3 8014614: 4b0c ldr r3, [pc, #48] @ (8014648 ) 8014616: fba3 0302 umull r0, r3, r3, r2 801461a: 095b lsrs r3, r3, #5 801461c: 2064 movs r0, #100 @ 0x64 801461e: fb00 f303 mul.w r3, r0, r3 8014622: 1ad3 subs r3, r2, r3 8014624: 011b lsls r3, r3, #4 8014626: 3332 adds r3, #50 @ 0x32 8014628: 4a07 ldr r2, [pc, #28] @ (8014648 ) 801462a: fba2 2303 umull r2, r3, r2, r3 801462e: 095b lsrs r3, r3, #5 8014630: f003 020f and.w r2, r3, #15 8014634: 687b ldr r3, [r7, #4] 8014636: 681b ldr r3, [r3, #0] 8014638: 440a add r2, r1 801463a: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 801463c: bf00 nop 801463e: 3710 adds r7, #16 8014640: 46bd mov sp, r7 8014642: bd80 pop {r7, pc} 8014644: 40013800 .word 0x40013800 8014648: 51eb851f .word 0x51eb851f 0801464c <__cvt>: 801464c: 2b00 cmp r3, #0 801464e: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8014652: 461d mov r5, r3 8014654: bfbb ittet lt 8014656: f103 4300 addlt.w r3, r3, #2147483648 @ 0x80000000 801465a: 461d movlt r5, r3 801465c: 2300 movge r3, #0 801465e: 232d movlt r3, #45 @ 0x2d 8014660: b088 sub sp, #32 8014662: 4614 mov r4, r2 8014664: bfb8 it lt 8014666: 4614 movlt r4, r2 8014668: 9a12 ldr r2, [sp, #72] @ 0x48 801466a: 9e10 ldr r6, [sp, #64] @ 0x40 801466c: 7013 strb r3, [r2, #0] 801466e: 9b14 ldr r3, [sp, #80] @ 0x50 8014670: f8dd a04c ldr.w sl, [sp, #76] @ 0x4c 8014674: f023 0820 bic.w r8, r3, #32 8014678: f1b8 0f46 cmp.w r8, #70 @ 0x46 801467c: d005 beq.n 801468a <__cvt+0x3e> 801467e: f1b8 0f45 cmp.w r8, #69 @ 0x45 8014682: d100 bne.n 8014686 <__cvt+0x3a> 8014684: 3601 adds r6, #1 8014686: 2302 movs r3, #2 8014688: e000 b.n 801468c <__cvt+0x40> 801468a: 2303 movs r3, #3 801468c: aa07 add r2, sp, #28 801468e: 9204 str r2, [sp, #16] 8014690: aa06 add r2, sp, #24 8014692: e9cd a202 strd sl, r2, [sp, #8] 8014696: e9cd 3600 strd r3, r6, [sp] 801469a: 4622 mov r2, r4 801469c: 462b mov r3, r5 801469e: f000 fe2b bl 80152f8 <_dtoa_r> 80146a2: f1b8 0f47 cmp.w r8, #71 @ 0x47 80146a6: 4607 mov r7, r0 80146a8: d119 bne.n 80146de <__cvt+0x92> 80146aa: 9b11 ldr r3, [sp, #68] @ 0x44 80146ac: 07db lsls r3, r3, #31 80146ae: d50e bpl.n 80146ce <__cvt+0x82> 80146b0: eb00 0906 add.w r9, r0, r6 80146b4: 2200 movs r2, #0 80146b6: 2300 movs r3, #0 80146b8: 4620 mov r0, r4 80146ba: 4629 mov r1, r5 80146bc: f7f4 f9e0 bl 8008a80 <__aeabi_dcmpeq> 80146c0: b108 cbz r0, 80146c6 <__cvt+0x7a> 80146c2: f8cd 901c str.w r9, [sp, #28] 80146c6: 2230 movs r2, #48 @ 0x30 80146c8: 9b07 ldr r3, [sp, #28] 80146ca: 454b cmp r3, r9 80146cc: d31e bcc.n 801470c <__cvt+0xc0> 80146ce: 4638 mov r0, r7 80146d0: 9b07 ldr r3, [sp, #28] 80146d2: 9a15 ldr r2, [sp, #84] @ 0x54 80146d4: 1bdb subs r3, r3, r7 80146d6: 6013 str r3, [r2, #0] 80146d8: b008 add sp, #32 80146da: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80146de: f1b8 0f46 cmp.w r8, #70 @ 0x46 80146e2: eb00 0906 add.w r9, r0, r6 80146e6: d1e5 bne.n 80146b4 <__cvt+0x68> 80146e8: 7803 ldrb r3, [r0, #0] 80146ea: 2b30 cmp r3, #48 @ 0x30 80146ec: d10a bne.n 8014704 <__cvt+0xb8> 80146ee: 2200 movs r2, #0 80146f0: 2300 movs r3, #0 80146f2: 4620 mov r0, r4 80146f4: 4629 mov r1, r5 80146f6: f7f4 f9c3 bl 8008a80 <__aeabi_dcmpeq> 80146fa: b918 cbnz r0, 8014704 <__cvt+0xb8> 80146fc: f1c6 0601 rsb r6, r6, #1 8014700: f8ca 6000 str.w r6, [sl] 8014704: f8da 3000 ldr.w r3, [sl] 8014708: 4499 add r9, r3 801470a: e7d3 b.n 80146b4 <__cvt+0x68> 801470c: 1c59 adds r1, r3, #1 801470e: 9107 str r1, [sp, #28] 8014710: 701a strb r2, [r3, #0] 8014712: e7d9 b.n 80146c8 <__cvt+0x7c> 08014714 <__exponent>: 8014714: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8014716: 2900 cmp r1, #0 8014718: bfb6 itet lt 801471a: 232d movlt r3, #45 @ 0x2d 801471c: 232b movge r3, #43 @ 0x2b 801471e: 4249 neglt r1, r1 8014720: 2909 cmp r1, #9 8014722: 7002 strb r2, [r0, #0] 8014724: 7043 strb r3, [r0, #1] 8014726: dd29 ble.n 801477c <__exponent+0x68> 8014728: f10d 0307 add.w r3, sp, #7 801472c: 461d mov r5, r3 801472e: 270a movs r7, #10 8014730: fbb1 f6f7 udiv r6, r1, r7 8014734: 461a mov r2, r3 8014736: fb07 1416 mls r4, r7, r6, r1 801473a: 3430 adds r4, #48 @ 0x30 801473c: f802 4c01 strb.w r4, [r2, #-1] 8014740: 460c mov r4, r1 8014742: 2c63 cmp r4, #99 @ 0x63 8014744: 4631 mov r1, r6 8014746: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff 801474a: dcf1 bgt.n 8014730 <__exponent+0x1c> 801474c: 3130 adds r1, #48 @ 0x30 801474e: 1e94 subs r4, r2, #2 8014750: f803 1c01 strb.w r1, [r3, #-1] 8014754: 4623 mov r3, r4 8014756: 1c41 adds r1, r0, #1 8014758: 42ab cmp r3, r5 801475a: d30a bcc.n 8014772 <__exponent+0x5e> 801475c: f10d 0309 add.w r3, sp, #9 8014760: 1a9b subs r3, r3, r2 8014762: 42ac cmp r4, r5 8014764: bf88 it hi 8014766: 2300 movhi r3, #0 8014768: 3302 adds r3, #2 801476a: 4403 add r3, r0 801476c: 1a18 subs r0, r3, r0 801476e: b003 add sp, #12 8014770: bdf0 pop {r4, r5, r6, r7, pc} 8014772: f813 6b01 ldrb.w r6, [r3], #1 8014776: f801 6f01 strb.w r6, [r1, #1]! 801477a: e7ed b.n 8014758 <__exponent+0x44> 801477c: 2330 movs r3, #48 @ 0x30 801477e: 3130 adds r1, #48 @ 0x30 8014780: 7083 strb r3, [r0, #2] 8014782: 70c1 strb r1, [r0, #3] 8014784: 1d03 adds r3, r0, #4 8014786: e7f1 b.n 801476c <__exponent+0x58> 08014788 <_printf_float>: 8014788: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801478c: b091 sub sp, #68 @ 0x44 801478e: 460c mov r4, r1 8014790: f8dd 8068 ldr.w r8, [sp, #104] @ 0x68 8014794: 4616 mov r6, r2 8014796: 461f mov r7, r3 8014798: 4605 mov r5, r0 801479a: f000 fce5 bl 8015168 <_localeconv_r> 801479e: 6803 ldr r3, [r0, #0] 80147a0: 4618 mov r0, r3 80147a2: 9308 str r3, [sp, #32] 80147a4: f7f3 fd40 bl 8008228 80147a8: 2300 movs r3, #0 80147aa: 930e str r3, [sp, #56] @ 0x38 80147ac: f8d8 3000 ldr.w r3, [r8] 80147b0: 9009 str r0, [sp, #36] @ 0x24 80147b2: 3307 adds r3, #7 80147b4: f023 0307 bic.w r3, r3, #7 80147b8: f103 0208 add.w r2, r3, #8 80147bc: f894 a018 ldrb.w sl, [r4, #24] 80147c0: f8d4 b000 ldr.w fp, [r4] 80147c4: f8c8 2000 str.w r2, [r8] 80147c8: e9d3 8900 ldrd r8, r9, [r3] 80147cc: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000 80147d0: 930b str r3, [sp, #44] @ 0x2c 80147d2: f8cd 8028 str.w r8, [sp, #40] @ 0x28 80147d6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80147da: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 80147de: e9c4 8912 strd r8, r9, [r4, #72] @ 0x48 80147e2: 4b9c ldr r3, [pc, #624] @ (8014a54 <_printf_float+0x2cc>) 80147e4: f7f4 f97e bl 8008ae4 <__aeabi_dcmpun> 80147e8: bb70 cbnz r0, 8014848 <_printf_float+0xc0> 80147ea: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 80147ee: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80147f2: 4b98 ldr r3, [pc, #608] @ (8014a54 <_printf_float+0x2cc>) 80147f4: f7f4 f958 bl 8008aa8 <__aeabi_dcmple> 80147f8: bb30 cbnz r0, 8014848 <_printf_float+0xc0> 80147fa: 2200 movs r2, #0 80147fc: 2300 movs r3, #0 80147fe: 4640 mov r0, r8 8014800: 4649 mov r1, r9 8014802: f7f4 f947 bl 8008a94 <__aeabi_dcmplt> 8014806: b110 cbz r0, 801480e <_printf_float+0x86> 8014808: 232d movs r3, #45 @ 0x2d 801480a: f884 3043 strb.w r3, [r4, #67] @ 0x43 801480e: 4a92 ldr r2, [pc, #584] @ (8014a58 <_printf_float+0x2d0>) 8014810: 4b92 ldr r3, [pc, #584] @ (8014a5c <_printf_float+0x2d4>) 8014812: f1ba 0f47 cmp.w sl, #71 @ 0x47 8014816: bf8c ite hi 8014818: 4690 movhi r8, r2 801481a: 4698 movls r8, r3 801481c: 2303 movs r3, #3 801481e: f04f 0900 mov.w r9, #0 8014822: 6123 str r3, [r4, #16] 8014824: f02b 0304 bic.w r3, fp, #4 8014828: 6023 str r3, [r4, #0] 801482a: 4633 mov r3, r6 801482c: 4621 mov r1, r4 801482e: 4628 mov r0, r5 8014830: 9700 str r7, [sp, #0] 8014832: aa0f add r2, sp, #60 @ 0x3c 8014834: f000 f9d4 bl 8014be0 <_printf_common> 8014838: 3001 adds r0, #1 801483a: f040 8090 bne.w 801495e <_printf_float+0x1d6> 801483e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8014842: b011 add sp, #68 @ 0x44 8014844: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8014848: 4642 mov r2, r8 801484a: 464b mov r3, r9 801484c: 4640 mov r0, r8 801484e: 4649 mov r1, r9 8014850: f7f4 f948 bl 8008ae4 <__aeabi_dcmpun> 8014854: b148 cbz r0, 801486a <_printf_float+0xe2> 8014856: 464b mov r3, r9 8014858: 2b00 cmp r3, #0 801485a: bfb8 it lt 801485c: 232d movlt r3, #45 @ 0x2d 801485e: 4a80 ldr r2, [pc, #512] @ (8014a60 <_printf_float+0x2d8>) 8014860: bfb8 it lt 8014862: f884 3043 strblt.w r3, [r4, #67] @ 0x43 8014866: 4b7f ldr r3, [pc, #508] @ (8014a64 <_printf_float+0x2dc>) 8014868: e7d3 b.n 8014812 <_printf_float+0x8a> 801486a: 6863 ldr r3, [r4, #4] 801486c: f00a 01df and.w r1, sl, #223 @ 0xdf 8014870: 1c5a adds r2, r3, #1 8014872: d13f bne.n 80148f4 <_printf_float+0x16c> 8014874: 2306 movs r3, #6 8014876: 6063 str r3, [r4, #4] 8014878: 2200 movs r2, #0 801487a: f44b 6380 orr.w r3, fp, #1024 @ 0x400 801487e: 6023 str r3, [r4, #0] 8014880: 9206 str r2, [sp, #24] 8014882: aa0e add r2, sp, #56 @ 0x38 8014884: e9cd a204 strd sl, r2, [sp, #16] 8014888: aa0d add r2, sp, #52 @ 0x34 801488a: 9203 str r2, [sp, #12] 801488c: f10d 0233 add.w r2, sp, #51 @ 0x33 8014890: e9cd 3201 strd r3, r2, [sp, #4] 8014894: 6863 ldr r3, [r4, #4] 8014896: 4642 mov r2, r8 8014898: 9300 str r3, [sp, #0] 801489a: 4628 mov r0, r5 801489c: 464b mov r3, r9 801489e: 910a str r1, [sp, #40] @ 0x28 80148a0: f7ff fed4 bl 801464c <__cvt> 80148a4: 990a ldr r1, [sp, #40] @ 0x28 80148a6: 4680 mov r8, r0 80148a8: 2947 cmp r1, #71 @ 0x47 80148aa: 990d ldr r1, [sp, #52] @ 0x34 80148ac: d128 bne.n 8014900 <_printf_float+0x178> 80148ae: 1cc8 adds r0, r1, #3 80148b0: db02 blt.n 80148b8 <_printf_float+0x130> 80148b2: 6863 ldr r3, [r4, #4] 80148b4: 4299 cmp r1, r3 80148b6: dd40 ble.n 801493a <_printf_float+0x1b2> 80148b8: f1aa 0a02 sub.w sl, sl, #2 80148bc: fa5f fa8a uxtb.w sl, sl 80148c0: 4652 mov r2, sl 80148c2: 3901 subs r1, #1 80148c4: f104 0050 add.w r0, r4, #80 @ 0x50 80148c8: 910d str r1, [sp, #52] @ 0x34 80148ca: f7ff ff23 bl 8014714 <__exponent> 80148ce: 9a0e ldr r2, [sp, #56] @ 0x38 80148d0: 4681 mov r9, r0 80148d2: 1813 adds r3, r2, r0 80148d4: 2a01 cmp r2, #1 80148d6: 6123 str r3, [r4, #16] 80148d8: dc02 bgt.n 80148e0 <_printf_float+0x158> 80148da: 6822 ldr r2, [r4, #0] 80148dc: 07d2 lsls r2, r2, #31 80148de: d501 bpl.n 80148e4 <_printf_float+0x15c> 80148e0: 3301 adds r3, #1 80148e2: 6123 str r3, [r4, #16] 80148e4: f89d 3033 ldrb.w r3, [sp, #51] @ 0x33 80148e8: 2b00 cmp r3, #0 80148ea: d09e beq.n 801482a <_printf_float+0xa2> 80148ec: 232d movs r3, #45 @ 0x2d 80148ee: f884 3043 strb.w r3, [r4, #67] @ 0x43 80148f2: e79a b.n 801482a <_printf_float+0xa2> 80148f4: 2947 cmp r1, #71 @ 0x47 80148f6: d1bf bne.n 8014878 <_printf_float+0xf0> 80148f8: 2b00 cmp r3, #0 80148fa: d1bd bne.n 8014878 <_printf_float+0xf0> 80148fc: 2301 movs r3, #1 80148fe: e7ba b.n 8014876 <_printf_float+0xee> 8014900: f1ba 0f65 cmp.w sl, #101 @ 0x65 8014904: d9dc bls.n 80148c0 <_printf_float+0x138> 8014906: f1ba 0f66 cmp.w sl, #102 @ 0x66 801490a: d118 bne.n 801493e <_printf_float+0x1b6> 801490c: 2900 cmp r1, #0 801490e: 6863 ldr r3, [r4, #4] 8014910: dd0b ble.n 801492a <_printf_float+0x1a2> 8014912: 6121 str r1, [r4, #16] 8014914: b913 cbnz r3, 801491c <_printf_float+0x194> 8014916: 6822 ldr r2, [r4, #0] 8014918: 07d0 lsls r0, r2, #31 801491a: d502 bpl.n 8014922 <_printf_float+0x19a> 801491c: 3301 adds r3, #1 801491e: 440b add r3, r1 8014920: 6123 str r3, [r4, #16] 8014922: f04f 0900 mov.w r9, #0 8014926: 65a1 str r1, [r4, #88] @ 0x58 8014928: e7dc b.n 80148e4 <_printf_float+0x15c> 801492a: b913 cbnz r3, 8014932 <_printf_float+0x1aa> 801492c: 6822 ldr r2, [r4, #0] 801492e: 07d2 lsls r2, r2, #31 8014930: d501 bpl.n 8014936 <_printf_float+0x1ae> 8014932: 3302 adds r3, #2 8014934: e7f4 b.n 8014920 <_printf_float+0x198> 8014936: 2301 movs r3, #1 8014938: e7f2 b.n 8014920 <_printf_float+0x198> 801493a: f04f 0a67 mov.w sl, #103 @ 0x67 801493e: 9b0e ldr r3, [sp, #56] @ 0x38 8014940: 4299 cmp r1, r3 8014942: db05 blt.n 8014950 <_printf_float+0x1c8> 8014944: 6823 ldr r3, [r4, #0] 8014946: 6121 str r1, [r4, #16] 8014948: 07d8 lsls r0, r3, #31 801494a: d5ea bpl.n 8014922 <_printf_float+0x19a> 801494c: 1c4b adds r3, r1, #1 801494e: e7e7 b.n 8014920 <_printf_float+0x198> 8014950: 2900 cmp r1, #0 8014952: bfcc ite gt 8014954: 2201 movgt r2, #1 8014956: f1c1 0202 rsble r2, r1, #2 801495a: 4413 add r3, r2 801495c: e7e0 b.n 8014920 <_printf_float+0x198> 801495e: 6823 ldr r3, [r4, #0] 8014960: 055a lsls r2, r3, #21 8014962: d407 bmi.n 8014974 <_printf_float+0x1ec> 8014964: 6923 ldr r3, [r4, #16] 8014966: 4642 mov r2, r8 8014968: 4631 mov r1, r6 801496a: 4628 mov r0, r5 801496c: 47b8 blx r7 801496e: 3001 adds r0, #1 8014970: d12b bne.n 80149ca <_printf_float+0x242> 8014972: e764 b.n 801483e <_printf_float+0xb6> 8014974: f1ba 0f65 cmp.w sl, #101 @ 0x65 8014978: f240 80dc bls.w 8014b34 <_printf_float+0x3ac> 801497c: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 8014980: 2200 movs r2, #0 8014982: 2300 movs r3, #0 8014984: f7f4 f87c bl 8008a80 <__aeabi_dcmpeq> 8014988: 2800 cmp r0, #0 801498a: d033 beq.n 80149f4 <_printf_float+0x26c> 801498c: 2301 movs r3, #1 801498e: 4631 mov r1, r6 8014990: 4628 mov r0, r5 8014992: 4a35 ldr r2, [pc, #212] @ (8014a68 <_printf_float+0x2e0>) 8014994: 47b8 blx r7 8014996: 3001 adds r0, #1 8014998: f43f af51 beq.w 801483e <_printf_float+0xb6> 801499c: e9dd 380d ldrd r3, r8, [sp, #52] @ 0x34 80149a0: 4543 cmp r3, r8 80149a2: db02 blt.n 80149aa <_printf_float+0x222> 80149a4: 6823 ldr r3, [r4, #0] 80149a6: 07d8 lsls r0, r3, #31 80149a8: d50f bpl.n 80149ca <_printf_float+0x242> 80149aa: e9dd 2308 ldrd r2, r3, [sp, #32] 80149ae: 4631 mov r1, r6 80149b0: 4628 mov r0, r5 80149b2: 47b8 blx r7 80149b4: 3001 adds r0, #1 80149b6: f43f af42 beq.w 801483e <_printf_float+0xb6> 80149ba: f04f 0900 mov.w r9, #0 80149be: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 80149c2: f104 0a1a add.w sl, r4, #26 80149c6: 45c8 cmp r8, r9 80149c8: dc09 bgt.n 80149de <_printf_float+0x256> 80149ca: 6823 ldr r3, [r4, #0] 80149cc: 079b lsls r3, r3, #30 80149ce: f100 8102 bmi.w 8014bd6 <_printf_float+0x44e> 80149d2: 68e0 ldr r0, [r4, #12] 80149d4: 9b0f ldr r3, [sp, #60] @ 0x3c 80149d6: 4298 cmp r0, r3 80149d8: bfb8 it lt 80149da: 4618 movlt r0, r3 80149dc: e731 b.n 8014842 <_printf_float+0xba> 80149de: 2301 movs r3, #1 80149e0: 4652 mov r2, sl 80149e2: 4631 mov r1, r6 80149e4: 4628 mov r0, r5 80149e6: 47b8 blx r7 80149e8: 3001 adds r0, #1 80149ea: f43f af28 beq.w 801483e <_printf_float+0xb6> 80149ee: f109 0901 add.w r9, r9, #1 80149f2: e7e8 b.n 80149c6 <_printf_float+0x23e> 80149f4: 9b0d ldr r3, [sp, #52] @ 0x34 80149f6: 2b00 cmp r3, #0 80149f8: dc38 bgt.n 8014a6c <_printf_float+0x2e4> 80149fa: 2301 movs r3, #1 80149fc: 4631 mov r1, r6 80149fe: 4628 mov r0, r5 8014a00: 4a19 ldr r2, [pc, #100] @ (8014a68 <_printf_float+0x2e0>) 8014a02: 47b8 blx r7 8014a04: 3001 adds r0, #1 8014a06: f43f af1a beq.w 801483e <_printf_float+0xb6> 8014a0a: e9dd 390d ldrd r3, r9, [sp, #52] @ 0x34 8014a0e: ea59 0303 orrs.w r3, r9, r3 8014a12: d102 bne.n 8014a1a <_printf_float+0x292> 8014a14: 6823 ldr r3, [r4, #0] 8014a16: 07d9 lsls r1, r3, #31 8014a18: d5d7 bpl.n 80149ca <_printf_float+0x242> 8014a1a: e9dd 2308 ldrd r2, r3, [sp, #32] 8014a1e: 4631 mov r1, r6 8014a20: 4628 mov r0, r5 8014a22: 47b8 blx r7 8014a24: 3001 adds r0, #1 8014a26: f43f af0a beq.w 801483e <_printf_float+0xb6> 8014a2a: f04f 0a00 mov.w sl, #0 8014a2e: f104 0b1a add.w fp, r4, #26 8014a32: 9b0d ldr r3, [sp, #52] @ 0x34 8014a34: 425b negs r3, r3 8014a36: 4553 cmp r3, sl 8014a38: dc01 bgt.n 8014a3e <_printf_float+0x2b6> 8014a3a: 464b mov r3, r9 8014a3c: e793 b.n 8014966 <_printf_float+0x1de> 8014a3e: 2301 movs r3, #1 8014a40: 465a mov r2, fp 8014a42: 4631 mov r1, r6 8014a44: 4628 mov r0, r5 8014a46: 47b8 blx r7 8014a48: 3001 adds r0, #1 8014a4a: f43f aef8 beq.w 801483e <_printf_float+0xb6> 8014a4e: f10a 0a01 add.w sl, sl, #1 8014a52: e7ee b.n 8014a32 <_printf_float+0x2aa> 8014a54: 7fefffff .word 0x7fefffff 8014a58: 08017dc0 .word 0x08017dc0 8014a5c: 08017dbc .word 0x08017dbc 8014a60: 08017dc8 .word 0x08017dc8 8014a64: 08017dc4 .word 0x08017dc4 8014a68: 08017dcc .word 0x08017dcc 8014a6c: 6da3 ldr r3, [r4, #88] @ 0x58 8014a6e: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 8014a72: 4553 cmp r3, sl 8014a74: bfa8 it ge 8014a76: 4653 movge r3, sl 8014a78: 2b00 cmp r3, #0 8014a7a: 4699 mov r9, r3 8014a7c: dc36 bgt.n 8014aec <_printf_float+0x364> 8014a7e: f04f 0b00 mov.w fp, #0 8014a82: ea29 79e9 bic.w r9, r9, r9, asr #31 8014a86: f104 021a add.w r2, r4, #26 8014a8a: 6da3 ldr r3, [r4, #88] @ 0x58 8014a8c: 930a str r3, [sp, #40] @ 0x28 8014a8e: eba3 0309 sub.w r3, r3, r9 8014a92: 455b cmp r3, fp 8014a94: dc31 bgt.n 8014afa <_printf_float+0x372> 8014a96: 9b0d ldr r3, [sp, #52] @ 0x34 8014a98: 459a cmp sl, r3 8014a9a: dc3a bgt.n 8014b12 <_printf_float+0x38a> 8014a9c: 6823 ldr r3, [r4, #0] 8014a9e: 07da lsls r2, r3, #31 8014aa0: d437 bmi.n 8014b12 <_printf_float+0x38a> 8014aa2: 9b0d ldr r3, [sp, #52] @ 0x34 8014aa4: ebaa 0903 sub.w r9, sl, r3 8014aa8: 9b0a ldr r3, [sp, #40] @ 0x28 8014aaa: ebaa 0303 sub.w r3, sl, r3 8014aae: 4599 cmp r9, r3 8014ab0: bfa8 it ge 8014ab2: 4699 movge r9, r3 8014ab4: f1b9 0f00 cmp.w r9, #0 8014ab8: dc33 bgt.n 8014b22 <_printf_float+0x39a> 8014aba: f04f 0800 mov.w r8, #0 8014abe: ea29 79e9 bic.w r9, r9, r9, asr #31 8014ac2: f104 0b1a add.w fp, r4, #26 8014ac6: 9b0d ldr r3, [sp, #52] @ 0x34 8014ac8: ebaa 0303 sub.w r3, sl, r3 8014acc: eba3 0309 sub.w r3, r3, r9 8014ad0: 4543 cmp r3, r8 8014ad2: f77f af7a ble.w 80149ca <_printf_float+0x242> 8014ad6: 2301 movs r3, #1 8014ad8: 465a mov r2, fp 8014ada: 4631 mov r1, r6 8014adc: 4628 mov r0, r5 8014ade: 47b8 blx r7 8014ae0: 3001 adds r0, #1 8014ae2: f43f aeac beq.w 801483e <_printf_float+0xb6> 8014ae6: f108 0801 add.w r8, r8, #1 8014aea: e7ec b.n 8014ac6 <_printf_float+0x33e> 8014aec: 4642 mov r2, r8 8014aee: 4631 mov r1, r6 8014af0: 4628 mov r0, r5 8014af2: 47b8 blx r7 8014af4: 3001 adds r0, #1 8014af6: d1c2 bne.n 8014a7e <_printf_float+0x2f6> 8014af8: e6a1 b.n 801483e <_printf_float+0xb6> 8014afa: 2301 movs r3, #1 8014afc: 4631 mov r1, r6 8014afe: 4628 mov r0, r5 8014b00: 920a str r2, [sp, #40] @ 0x28 8014b02: 47b8 blx r7 8014b04: 3001 adds r0, #1 8014b06: f43f ae9a beq.w 801483e <_printf_float+0xb6> 8014b0a: 9a0a ldr r2, [sp, #40] @ 0x28 8014b0c: f10b 0b01 add.w fp, fp, #1 8014b10: e7bb b.n 8014a8a <_printf_float+0x302> 8014b12: 4631 mov r1, r6 8014b14: e9dd 2308 ldrd r2, r3, [sp, #32] 8014b18: 4628 mov r0, r5 8014b1a: 47b8 blx r7 8014b1c: 3001 adds r0, #1 8014b1e: d1c0 bne.n 8014aa2 <_printf_float+0x31a> 8014b20: e68d b.n 801483e <_printf_float+0xb6> 8014b22: 9a0a ldr r2, [sp, #40] @ 0x28 8014b24: 464b mov r3, r9 8014b26: 4631 mov r1, r6 8014b28: 4628 mov r0, r5 8014b2a: 4442 add r2, r8 8014b2c: 47b8 blx r7 8014b2e: 3001 adds r0, #1 8014b30: d1c3 bne.n 8014aba <_printf_float+0x332> 8014b32: e684 b.n 801483e <_printf_float+0xb6> 8014b34: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 8014b38: f1ba 0f01 cmp.w sl, #1 8014b3c: dc01 bgt.n 8014b42 <_printf_float+0x3ba> 8014b3e: 07db lsls r3, r3, #31 8014b40: d536 bpl.n 8014bb0 <_printf_float+0x428> 8014b42: 2301 movs r3, #1 8014b44: 4642 mov r2, r8 8014b46: 4631 mov r1, r6 8014b48: 4628 mov r0, r5 8014b4a: 47b8 blx r7 8014b4c: 3001 adds r0, #1 8014b4e: f43f ae76 beq.w 801483e <_printf_float+0xb6> 8014b52: e9dd 2308 ldrd r2, r3, [sp, #32] 8014b56: 4631 mov r1, r6 8014b58: 4628 mov r0, r5 8014b5a: 47b8 blx r7 8014b5c: 3001 adds r0, #1 8014b5e: f43f ae6e beq.w 801483e <_printf_float+0xb6> 8014b62: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 8014b66: 2200 movs r2, #0 8014b68: 2300 movs r3, #0 8014b6a: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff 8014b6e: f7f3 ff87 bl 8008a80 <__aeabi_dcmpeq> 8014b72: b9c0 cbnz r0, 8014ba6 <_printf_float+0x41e> 8014b74: 4653 mov r3, sl 8014b76: f108 0201 add.w r2, r8, #1 8014b7a: 4631 mov r1, r6 8014b7c: 4628 mov r0, r5 8014b7e: 47b8 blx r7 8014b80: 3001 adds r0, #1 8014b82: d10c bne.n 8014b9e <_printf_float+0x416> 8014b84: e65b b.n 801483e <_printf_float+0xb6> 8014b86: 2301 movs r3, #1 8014b88: 465a mov r2, fp 8014b8a: 4631 mov r1, r6 8014b8c: 4628 mov r0, r5 8014b8e: 47b8 blx r7 8014b90: 3001 adds r0, #1 8014b92: f43f ae54 beq.w 801483e <_printf_float+0xb6> 8014b96: f108 0801 add.w r8, r8, #1 8014b9a: 45d0 cmp r8, sl 8014b9c: dbf3 blt.n 8014b86 <_printf_float+0x3fe> 8014b9e: 464b mov r3, r9 8014ba0: f104 0250 add.w r2, r4, #80 @ 0x50 8014ba4: e6e0 b.n 8014968 <_printf_float+0x1e0> 8014ba6: f04f 0800 mov.w r8, #0 8014baa: f104 0b1a add.w fp, r4, #26 8014bae: e7f4 b.n 8014b9a <_printf_float+0x412> 8014bb0: 2301 movs r3, #1 8014bb2: 4642 mov r2, r8 8014bb4: e7e1 b.n 8014b7a <_printf_float+0x3f2> 8014bb6: 2301 movs r3, #1 8014bb8: 464a mov r2, r9 8014bba: 4631 mov r1, r6 8014bbc: 4628 mov r0, r5 8014bbe: 47b8 blx r7 8014bc0: 3001 adds r0, #1 8014bc2: f43f ae3c beq.w 801483e <_printf_float+0xb6> 8014bc6: f108 0801 add.w r8, r8, #1 8014bca: 68e3 ldr r3, [r4, #12] 8014bcc: 990f ldr r1, [sp, #60] @ 0x3c 8014bce: 1a5b subs r3, r3, r1 8014bd0: 4543 cmp r3, r8 8014bd2: dcf0 bgt.n 8014bb6 <_printf_float+0x42e> 8014bd4: e6fd b.n 80149d2 <_printf_float+0x24a> 8014bd6: f04f 0800 mov.w r8, #0 8014bda: f104 0919 add.w r9, r4, #25 8014bde: e7f4 b.n 8014bca <_printf_float+0x442> 08014be0 <_printf_common>: 8014be0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8014be4: 4616 mov r6, r2 8014be6: 4698 mov r8, r3 8014be8: 688a ldr r2, [r1, #8] 8014bea: 690b ldr r3, [r1, #16] 8014bec: 4607 mov r7, r0 8014bee: 4293 cmp r3, r2 8014bf0: bfb8 it lt 8014bf2: 4613 movlt r3, r2 8014bf4: 6033 str r3, [r6, #0] 8014bf6: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 8014bfa: 460c mov r4, r1 8014bfc: f8dd 9020 ldr.w r9, [sp, #32] 8014c00: b10a cbz r2, 8014c06 <_printf_common+0x26> 8014c02: 3301 adds r3, #1 8014c04: 6033 str r3, [r6, #0] 8014c06: 6823 ldr r3, [r4, #0] 8014c08: 0699 lsls r1, r3, #26 8014c0a: bf42 ittt mi 8014c0c: 6833 ldrmi r3, [r6, #0] 8014c0e: 3302 addmi r3, #2 8014c10: 6033 strmi r3, [r6, #0] 8014c12: 6825 ldr r5, [r4, #0] 8014c14: f015 0506 ands.w r5, r5, #6 8014c18: d106 bne.n 8014c28 <_printf_common+0x48> 8014c1a: f104 0a19 add.w sl, r4, #25 8014c1e: 68e3 ldr r3, [r4, #12] 8014c20: 6832 ldr r2, [r6, #0] 8014c22: 1a9b subs r3, r3, r2 8014c24: 42ab cmp r3, r5 8014c26: dc2b bgt.n 8014c80 <_printf_common+0xa0> 8014c28: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 8014c2c: 6822 ldr r2, [r4, #0] 8014c2e: 3b00 subs r3, #0 8014c30: bf18 it ne 8014c32: 2301 movne r3, #1 8014c34: 0692 lsls r2, r2, #26 8014c36: d430 bmi.n 8014c9a <_printf_common+0xba> 8014c38: 4641 mov r1, r8 8014c3a: 4638 mov r0, r7 8014c3c: f104 0243 add.w r2, r4, #67 @ 0x43 8014c40: 47c8 blx r9 8014c42: 3001 adds r0, #1 8014c44: d023 beq.n 8014c8e <_printf_common+0xae> 8014c46: 6823 ldr r3, [r4, #0] 8014c48: 6922 ldr r2, [r4, #16] 8014c4a: f003 0306 and.w r3, r3, #6 8014c4e: 2b04 cmp r3, #4 8014c50: bf14 ite ne 8014c52: 2500 movne r5, #0 8014c54: 6833 ldreq r3, [r6, #0] 8014c56: f04f 0600 mov.w r6, #0 8014c5a: bf08 it eq 8014c5c: 68e5 ldreq r5, [r4, #12] 8014c5e: f104 041a add.w r4, r4, #26 8014c62: bf08 it eq 8014c64: 1aed subeq r5, r5, r3 8014c66: f854 3c12 ldr.w r3, [r4, #-18] 8014c6a: bf08 it eq 8014c6c: ea25 75e5 biceq.w r5, r5, r5, asr #31 8014c70: 4293 cmp r3, r2 8014c72: bfc4 itt gt 8014c74: 1a9b subgt r3, r3, r2 8014c76: 18ed addgt r5, r5, r3 8014c78: 42b5 cmp r5, r6 8014c7a: d11a bne.n 8014cb2 <_printf_common+0xd2> 8014c7c: 2000 movs r0, #0 8014c7e: e008 b.n 8014c92 <_printf_common+0xb2> 8014c80: 2301 movs r3, #1 8014c82: 4652 mov r2, sl 8014c84: 4641 mov r1, r8 8014c86: 4638 mov r0, r7 8014c88: 47c8 blx r9 8014c8a: 3001 adds r0, #1 8014c8c: d103 bne.n 8014c96 <_printf_common+0xb6> 8014c8e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8014c92: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8014c96: 3501 adds r5, #1 8014c98: e7c1 b.n 8014c1e <_printf_common+0x3e> 8014c9a: 2030 movs r0, #48 @ 0x30 8014c9c: 18e1 adds r1, r4, r3 8014c9e: f881 0043 strb.w r0, [r1, #67] @ 0x43 8014ca2: 1c5a adds r2, r3, #1 8014ca4: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 8014ca8: 4422 add r2, r4 8014caa: 3302 adds r3, #2 8014cac: f882 1043 strb.w r1, [r2, #67] @ 0x43 8014cb0: e7c2 b.n 8014c38 <_printf_common+0x58> 8014cb2: 2301 movs r3, #1 8014cb4: 4622 mov r2, r4 8014cb6: 4641 mov r1, r8 8014cb8: 4638 mov r0, r7 8014cba: 47c8 blx r9 8014cbc: 3001 adds r0, #1 8014cbe: d0e6 beq.n 8014c8e <_printf_common+0xae> 8014cc0: 3601 adds r6, #1 8014cc2: e7d9 b.n 8014c78 <_printf_common+0x98> 08014cc4 <_printf_i>: 8014cc4: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8014cc8: 7e0f ldrb r7, [r1, #24] 8014cca: 4691 mov r9, r2 8014ccc: 2f78 cmp r7, #120 @ 0x78 8014cce: 4680 mov r8, r0 8014cd0: 460c mov r4, r1 8014cd2: 469a mov sl, r3 8014cd4: 9e0c ldr r6, [sp, #48] @ 0x30 8014cd6: f101 0243 add.w r2, r1, #67 @ 0x43 8014cda: d807 bhi.n 8014cec <_printf_i+0x28> 8014cdc: 2f62 cmp r7, #98 @ 0x62 8014cde: d80a bhi.n 8014cf6 <_printf_i+0x32> 8014ce0: 2f00 cmp r7, #0 8014ce2: f000 80d1 beq.w 8014e88 <_printf_i+0x1c4> 8014ce6: 2f58 cmp r7, #88 @ 0x58 8014ce8: f000 80b8 beq.w 8014e5c <_printf_i+0x198> 8014cec: f104 0642 add.w r6, r4, #66 @ 0x42 8014cf0: f884 7042 strb.w r7, [r4, #66] @ 0x42 8014cf4: e03a b.n 8014d6c <_printf_i+0xa8> 8014cf6: f1a7 0363 sub.w r3, r7, #99 @ 0x63 8014cfa: 2b15 cmp r3, #21 8014cfc: d8f6 bhi.n 8014cec <_printf_i+0x28> 8014cfe: a101 add r1, pc, #4 @ (adr r1, 8014d04 <_printf_i+0x40>) 8014d00: f851 f023 ldr.w pc, [r1, r3, lsl #2] 8014d04: 08014d5d .word 0x08014d5d 8014d08: 08014d71 .word 0x08014d71 8014d0c: 08014ced .word 0x08014ced 8014d10: 08014ced .word 0x08014ced 8014d14: 08014ced .word 0x08014ced 8014d18: 08014ced .word 0x08014ced 8014d1c: 08014d71 .word 0x08014d71 8014d20: 08014ced .word 0x08014ced 8014d24: 08014ced .word 0x08014ced 8014d28: 08014ced .word 0x08014ced 8014d2c: 08014ced .word 0x08014ced 8014d30: 08014e6f .word 0x08014e6f 8014d34: 08014d9b .word 0x08014d9b 8014d38: 08014e29 .word 0x08014e29 8014d3c: 08014ced .word 0x08014ced 8014d40: 08014ced .word 0x08014ced 8014d44: 08014e91 .word 0x08014e91 8014d48: 08014ced .word 0x08014ced 8014d4c: 08014d9b .word 0x08014d9b 8014d50: 08014ced .word 0x08014ced 8014d54: 08014ced .word 0x08014ced 8014d58: 08014e31 .word 0x08014e31 8014d5c: 6833 ldr r3, [r6, #0] 8014d5e: 1d1a adds r2, r3, #4 8014d60: 681b ldr r3, [r3, #0] 8014d62: 6032 str r2, [r6, #0] 8014d64: f104 0642 add.w r6, r4, #66 @ 0x42 8014d68: f884 3042 strb.w r3, [r4, #66] @ 0x42 8014d6c: 2301 movs r3, #1 8014d6e: e09c b.n 8014eaa <_printf_i+0x1e6> 8014d70: 6833 ldr r3, [r6, #0] 8014d72: 6820 ldr r0, [r4, #0] 8014d74: 1d19 adds r1, r3, #4 8014d76: 6031 str r1, [r6, #0] 8014d78: 0606 lsls r6, r0, #24 8014d7a: d501 bpl.n 8014d80 <_printf_i+0xbc> 8014d7c: 681d ldr r5, [r3, #0] 8014d7e: e003 b.n 8014d88 <_printf_i+0xc4> 8014d80: 0645 lsls r5, r0, #25 8014d82: d5fb bpl.n 8014d7c <_printf_i+0xb8> 8014d84: f9b3 5000 ldrsh.w r5, [r3] 8014d88: 2d00 cmp r5, #0 8014d8a: da03 bge.n 8014d94 <_printf_i+0xd0> 8014d8c: 232d movs r3, #45 @ 0x2d 8014d8e: 426d negs r5, r5 8014d90: f884 3043 strb.w r3, [r4, #67] @ 0x43 8014d94: 230a movs r3, #10 8014d96: 4858 ldr r0, [pc, #352] @ (8014ef8 <_printf_i+0x234>) 8014d98: e011 b.n 8014dbe <_printf_i+0xfa> 8014d9a: 6821 ldr r1, [r4, #0] 8014d9c: 6833 ldr r3, [r6, #0] 8014d9e: 0608 lsls r0, r1, #24 8014da0: f853 5b04 ldr.w r5, [r3], #4 8014da4: d402 bmi.n 8014dac <_printf_i+0xe8> 8014da6: 0649 lsls r1, r1, #25 8014da8: bf48 it mi 8014daa: b2ad uxthmi r5, r5 8014dac: 2f6f cmp r7, #111 @ 0x6f 8014dae: 6033 str r3, [r6, #0] 8014db0: bf14 ite ne 8014db2: 230a movne r3, #10 8014db4: 2308 moveq r3, #8 8014db6: 4850 ldr r0, [pc, #320] @ (8014ef8 <_printf_i+0x234>) 8014db8: 2100 movs r1, #0 8014dba: f884 1043 strb.w r1, [r4, #67] @ 0x43 8014dbe: 6866 ldr r6, [r4, #4] 8014dc0: 2e00 cmp r6, #0 8014dc2: 60a6 str r6, [r4, #8] 8014dc4: db05 blt.n 8014dd2 <_printf_i+0x10e> 8014dc6: 6821 ldr r1, [r4, #0] 8014dc8: 432e orrs r6, r5 8014dca: f021 0104 bic.w r1, r1, #4 8014dce: 6021 str r1, [r4, #0] 8014dd0: d04b beq.n 8014e6a <_printf_i+0x1a6> 8014dd2: 4616 mov r6, r2 8014dd4: fbb5 f1f3 udiv r1, r5, r3 8014dd8: fb03 5711 mls r7, r3, r1, r5 8014ddc: 5dc7 ldrb r7, [r0, r7] 8014dde: f806 7d01 strb.w r7, [r6, #-1]! 8014de2: 462f mov r7, r5 8014de4: 42bb cmp r3, r7 8014de6: 460d mov r5, r1 8014de8: d9f4 bls.n 8014dd4 <_printf_i+0x110> 8014dea: 2b08 cmp r3, #8 8014dec: d10b bne.n 8014e06 <_printf_i+0x142> 8014dee: 6823 ldr r3, [r4, #0] 8014df0: 07df lsls r7, r3, #31 8014df2: d508 bpl.n 8014e06 <_printf_i+0x142> 8014df4: 6923 ldr r3, [r4, #16] 8014df6: 6861 ldr r1, [r4, #4] 8014df8: 4299 cmp r1, r3 8014dfa: bfde ittt le 8014dfc: 2330 movle r3, #48 @ 0x30 8014dfe: f806 3c01 strble.w r3, [r6, #-1] 8014e02: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 8014e06: 1b92 subs r2, r2, r6 8014e08: 6122 str r2, [r4, #16] 8014e0a: 464b mov r3, r9 8014e0c: 4621 mov r1, r4 8014e0e: 4640 mov r0, r8 8014e10: f8cd a000 str.w sl, [sp] 8014e14: aa03 add r2, sp, #12 8014e16: f7ff fee3 bl 8014be0 <_printf_common> 8014e1a: 3001 adds r0, #1 8014e1c: d14a bne.n 8014eb4 <_printf_i+0x1f0> 8014e1e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8014e22: b004 add sp, #16 8014e24: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8014e28: 6823 ldr r3, [r4, #0] 8014e2a: f043 0320 orr.w r3, r3, #32 8014e2e: 6023 str r3, [r4, #0] 8014e30: 2778 movs r7, #120 @ 0x78 8014e32: 4832 ldr r0, [pc, #200] @ (8014efc <_printf_i+0x238>) 8014e34: f884 7045 strb.w r7, [r4, #69] @ 0x45 8014e38: 6823 ldr r3, [r4, #0] 8014e3a: 6831 ldr r1, [r6, #0] 8014e3c: 061f lsls r7, r3, #24 8014e3e: f851 5b04 ldr.w r5, [r1], #4 8014e42: d402 bmi.n 8014e4a <_printf_i+0x186> 8014e44: 065f lsls r7, r3, #25 8014e46: bf48 it mi 8014e48: b2ad uxthmi r5, r5 8014e4a: 6031 str r1, [r6, #0] 8014e4c: 07d9 lsls r1, r3, #31 8014e4e: bf44 itt mi 8014e50: f043 0320 orrmi.w r3, r3, #32 8014e54: 6023 strmi r3, [r4, #0] 8014e56: b11d cbz r5, 8014e60 <_printf_i+0x19c> 8014e58: 2310 movs r3, #16 8014e5a: e7ad b.n 8014db8 <_printf_i+0xf4> 8014e5c: 4826 ldr r0, [pc, #152] @ (8014ef8 <_printf_i+0x234>) 8014e5e: e7e9 b.n 8014e34 <_printf_i+0x170> 8014e60: 6823 ldr r3, [r4, #0] 8014e62: f023 0320 bic.w r3, r3, #32 8014e66: 6023 str r3, [r4, #0] 8014e68: e7f6 b.n 8014e58 <_printf_i+0x194> 8014e6a: 4616 mov r6, r2 8014e6c: e7bd b.n 8014dea <_printf_i+0x126> 8014e6e: 6833 ldr r3, [r6, #0] 8014e70: 6825 ldr r5, [r4, #0] 8014e72: 1d18 adds r0, r3, #4 8014e74: 6961 ldr r1, [r4, #20] 8014e76: 6030 str r0, [r6, #0] 8014e78: 062e lsls r6, r5, #24 8014e7a: 681b ldr r3, [r3, #0] 8014e7c: d501 bpl.n 8014e82 <_printf_i+0x1be> 8014e7e: 6019 str r1, [r3, #0] 8014e80: e002 b.n 8014e88 <_printf_i+0x1c4> 8014e82: 0668 lsls r0, r5, #25 8014e84: d5fb bpl.n 8014e7e <_printf_i+0x1ba> 8014e86: 8019 strh r1, [r3, #0] 8014e88: 2300 movs r3, #0 8014e8a: 4616 mov r6, r2 8014e8c: 6123 str r3, [r4, #16] 8014e8e: e7bc b.n 8014e0a <_printf_i+0x146> 8014e90: 6833 ldr r3, [r6, #0] 8014e92: 2100 movs r1, #0 8014e94: 1d1a adds r2, r3, #4 8014e96: 6032 str r2, [r6, #0] 8014e98: 681e ldr r6, [r3, #0] 8014e9a: 6862 ldr r2, [r4, #4] 8014e9c: 4630 mov r0, r6 8014e9e: f000 f967 bl 8015170 8014ea2: b108 cbz r0, 8014ea8 <_printf_i+0x1e4> 8014ea4: 1b80 subs r0, r0, r6 8014ea6: 6060 str r0, [r4, #4] 8014ea8: 6863 ldr r3, [r4, #4] 8014eaa: 6123 str r3, [r4, #16] 8014eac: 2300 movs r3, #0 8014eae: f884 3043 strb.w r3, [r4, #67] @ 0x43 8014eb2: e7aa b.n 8014e0a <_printf_i+0x146> 8014eb4: 4632 mov r2, r6 8014eb6: 4649 mov r1, r9 8014eb8: 4640 mov r0, r8 8014eba: 6923 ldr r3, [r4, #16] 8014ebc: 47d0 blx sl 8014ebe: 3001 adds r0, #1 8014ec0: d0ad beq.n 8014e1e <_printf_i+0x15a> 8014ec2: 6823 ldr r3, [r4, #0] 8014ec4: 079b lsls r3, r3, #30 8014ec6: d413 bmi.n 8014ef0 <_printf_i+0x22c> 8014ec8: 68e0 ldr r0, [r4, #12] 8014eca: 9b03 ldr r3, [sp, #12] 8014ecc: 4298 cmp r0, r3 8014ece: bfb8 it lt 8014ed0: 4618 movlt r0, r3 8014ed2: e7a6 b.n 8014e22 <_printf_i+0x15e> 8014ed4: 2301 movs r3, #1 8014ed6: 4632 mov r2, r6 8014ed8: 4649 mov r1, r9 8014eda: 4640 mov r0, r8 8014edc: 47d0 blx sl 8014ede: 3001 adds r0, #1 8014ee0: d09d beq.n 8014e1e <_printf_i+0x15a> 8014ee2: 3501 adds r5, #1 8014ee4: 68e3 ldr r3, [r4, #12] 8014ee6: 9903 ldr r1, [sp, #12] 8014ee8: 1a5b subs r3, r3, r1 8014eea: 42ab cmp r3, r5 8014eec: dcf2 bgt.n 8014ed4 <_printf_i+0x210> 8014eee: e7eb b.n 8014ec8 <_printf_i+0x204> 8014ef0: 2500 movs r5, #0 8014ef2: f104 0619 add.w r6, r4, #25 8014ef6: e7f5 b.n 8014ee4 <_printf_i+0x220> 8014ef8: 08017dce .word 0x08017dce 8014efc: 08017ddf .word 0x08017ddf 08014f00 : 8014f00: 2300 movs r3, #0 8014f02: b510 push {r4, lr} 8014f04: 4604 mov r4, r0 8014f06: e9c0 3300 strd r3, r3, [r0] 8014f0a: e9c0 3304 strd r3, r3, [r0, #16] 8014f0e: 6083 str r3, [r0, #8] 8014f10: 8181 strh r1, [r0, #12] 8014f12: 6643 str r3, [r0, #100] @ 0x64 8014f14: 81c2 strh r2, [r0, #14] 8014f16: 6183 str r3, [r0, #24] 8014f18: 4619 mov r1, r3 8014f1a: 2208 movs r2, #8 8014f1c: 305c adds r0, #92 @ 0x5c 8014f1e: f000 f8ed bl 80150fc 8014f22: 4b0d ldr r3, [pc, #52] @ (8014f58 ) 8014f24: 6224 str r4, [r4, #32] 8014f26: 6263 str r3, [r4, #36] @ 0x24 8014f28: 4b0c ldr r3, [pc, #48] @ (8014f5c ) 8014f2a: 62a3 str r3, [r4, #40] @ 0x28 8014f2c: 4b0c ldr r3, [pc, #48] @ (8014f60 ) 8014f2e: 62e3 str r3, [r4, #44] @ 0x2c 8014f30: 4b0c ldr r3, [pc, #48] @ (8014f64 ) 8014f32: 6323 str r3, [r4, #48] @ 0x30 8014f34: 4b0c ldr r3, [pc, #48] @ (8014f68 ) 8014f36: 429c cmp r4, r3 8014f38: d006 beq.n 8014f48 8014f3a: f103 0268 add.w r2, r3, #104 @ 0x68 8014f3e: 4294 cmp r4, r2 8014f40: d002 beq.n 8014f48 8014f42: 33d0 adds r3, #208 @ 0xd0 8014f44: 429c cmp r4, r3 8014f46: d105 bne.n 8014f54 8014f48: f104 0058 add.w r0, r4, #88 @ 0x58 8014f4c: e8bd 4010 ldmia.w sp!, {r4, lr} 8014f50: f000 b906 b.w 8015160 <__retarget_lock_init_recursive> 8014f54: bd10 pop {r4, pc} 8014f56: bf00 nop 8014f58: 08016b01 .word 0x08016b01 8014f5c: 08016b23 .word 0x08016b23 8014f60: 08016b5b .word 0x08016b5b 8014f64: 08016b7f .word 0x08016b7f 8014f68: 200014a0 .word 0x200014a0 08014f6c : 8014f6c: 4a02 ldr r2, [pc, #8] @ (8014f78 ) 8014f6e: 4903 ldr r1, [pc, #12] @ (8014f7c ) 8014f70: 4803 ldr r0, [pc, #12] @ (8014f80 ) 8014f72: f000 b8a5 b.w 80150c0 <_fwalk_sglue> 8014f76: bf00 nop 8014f78: 20000090 .word 0x20000090 8014f7c: 080163a5 .word 0x080163a5 8014f80: 200000a0 .word 0x200000a0 08014f84 : 8014f84: 6841 ldr r1, [r0, #4] 8014f86: 4b0c ldr r3, [pc, #48] @ (8014fb8 ) 8014f88: b510 push {r4, lr} 8014f8a: 4299 cmp r1, r3 8014f8c: 4604 mov r4, r0 8014f8e: d001 beq.n 8014f94 8014f90: f001 fa08 bl 80163a4 <_fflush_r> 8014f94: 68a1 ldr r1, [r4, #8] 8014f96: 4b09 ldr r3, [pc, #36] @ (8014fbc ) 8014f98: 4299 cmp r1, r3 8014f9a: d002 beq.n 8014fa2 8014f9c: 4620 mov r0, r4 8014f9e: f001 fa01 bl 80163a4 <_fflush_r> 8014fa2: 68e1 ldr r1, [r4, #12] 8014fa4: 4b06 ldr r3, [pc, #24] @ (8014fc0 ) 8014fa6: 4299 cmp r1, r3 8014fa8: d004 beq.n 8014fb4 8014faa: 4620 mov r0, r4 8014fac: e8bd 4010 ldmia.w sp!, {r4, lr} 8014fb0: f001 b9f8 b.w 80163a4 <_fflush_r> 8014fb4: bd10 pop {r4, pc} 8014fb6: bf00 nop 8014fb8: 200014a0 .word 0x200014a0 8014fbc: 20001508 .word 0x20001508 8014fc0: 20001570 .word 0x20001570 08014fc4 : 8014fc4: b510 push {r4, lr} 8014fc6: 4b0b ldr r3, [pc, #44] @ (8014ff4 ) 8014fc8: 4c0b ldr r4, [pc, #44] @ (8014ff8 ) 8014fca: 4a0c ldr r2, [pc, #48] @ (8014ffc ) 8014fcc: 4620 mov r0, r4 8014fce: 601a str r2, [r3, #0] 8014fd0: 2104 movs r1, #4 8014fd2: 2200 movs r2, #0 8014fd4: f7ff ff94 bl 8014f00 8014fd8: f104 0068 add.w r0, r4, #104 @ 0x68 8014fdc: 2201 movs r2, #1 8014fde: 2109 movs r1, #9 8014fe0: f7ff ff8e bl 8014f00 8014fe4: f104 00d0 add.w r0, r4, #208 @ 0xd0 8014fe8: 2202 movs r2, #2 8014fea: e8bd 4010 ldmia.w sp!, {r4, lr} 8014fee: 2112 movs r1, #18 8014ff0: f7ff bf86 b.w 8014f00 8014ff4: 200015d8 .word 0x200015d8 8014ff8: 200014a0 .word 0x200014a0 8014ffc: 08014f6d .word 0x08014f6d 08015000 <__sfp_lock_acquire>: 8015000: 4801 ldr r0, [pc, #4] @ (8015008 <__sfp_lock_acquire+0x8>) 8015002: f000 b8ae b.w 8015162 <__retarget_lock_acquire_recursive> 8015006: bf00 nop 8015008: 200015dd .word 0x200015dd 0801500c <__sfp_lock_release>: 801500c: 4801 ldr r0, [pc, #4] @ (8015014 <__sfp_lock_release+0x8>) 801500e: f000 b8a9 b.w 8015164 <__retarget_lock_release_recursive> 8015012: bf00 nop 8015014: 200015dd .word 0x200015dd 08015018 <__sinit>: 8015018: b510 push {r4, lr} 801501a: 4604 mov r4, r0 801501c: f7ff fff0 bl 8015000 <__sfp_lock_acquire> 8015020: 6a23 ldr r3, [r4, #32] 8015022: b11b cbz r3, 801502c <__sinit+0x14> 8015024: e8bd 4010 ldmia.w sp!, {r4, lr} 8015028: f7ff bff0 b.w 801500c <__sfp_lock_release> 801502c: 4b04 ldr r3, [pc, #16] @ (8015040 <__sinit+0x28>) 801502e: 6223 str r3, [r4, #32] 8015030: 4b04 ldr r3, [pc, #16] @ (8015044 <__sinit+0x2c>) 8015032: 681b ldr r3, [r3, #0] 8015034: 2b00 cmp r3, #0 8015036: d1f5 bne.n 8015024 <__sinit+0xc> 8015038: f7ff ffc4 bl 8014fc4 801503c: e7f2 b.n 8015024 <__sinit+0xc> 801503e: bf00 nop 8015040: 08014f85 .word 0x08014f85 8015044: 200015d8 .word 0x200015d8 08015048 <_vsniprintf_r>: 8015048: b530 push {r4, r5, lr} 801504a: 4614 mov r4, r2 801504c: 2c00 cmp r4, #0 801504e: 4605 mov r5, r0 8015050: 461a mov r2, r3 8015052: b09b sub sp, #108 @ 0x6c 8015054: da05 bge.n 8015062 <_vsniprintf_r+0x1a> 8015056: 238b movs r3, #139 @ 0x8b 8015058: 6003 str r3, [r0, #0] 801505a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801505e: b01b add sp, #108 @ 0x6c 8015060: bd30 pop {r4, r5, pc} 8015062: f44f 7302 mov.w r3, #520 @ 0x208 8015066: f8ad 300c strh.w r3, [sp, #12] 801506a: f04f 0300 mov.w r3, #0 801506e: 9319 str r3, [sp, #100] @ 0x64 8015070: bf0c ite eq 8015072: 4623 moveq r3, r4 8015074: f104 33ff addne.w r3, r4, #4294967295 @ 0xffffffff 8015078: 9302 str r3, [sp, #8] 801507a: 9305 str r3, [sp, #20] 801507c: f64f 73ff movw r3, #65535 @ 0xffff 8015080: 9100 str r1, [sp, #0] 8015082: 9104 str r1, [sp, #16] 8015084: f8ad 300e strh.w r3, [sp, #14] 8015088: 4669 mov r1, sp 801508a: 9b1e ldr r3, [sp, #120] @ 0x78 801508c: f000 ff64 bl 8015f58 <_svfiprintf_r> 8015090: 1c43 adds r3, r0, #1 8015092: bfbc itt lt 8015094: 238b movlt r3, #139 @ 0x8b 8015096: 602b strlt r3, [r5, #0] 8015098: 2c00 cmp r4, #0 801509a: d0e0 beq.n 801505e <_vsniprintf_r+0x16> 801509c: 2200 movs r2, #0 801509e: 9b00 ldr r3, [sp, #0] 80150a0: 701a strb r2, [r3, #0] 80150a2: e7dc b.n 801505e <_vsniprintf_r+0x16> 080150a4 : 80150a4: b507 push {r0, r1, r2, lr} 80150a6: 9300 str r3, [sp, #0] 80150a8: 4613 mov r3, r2 80150aa: 460a mov r2, r1 80150ac: 4601 mov r1, r0 80150ae: 4803 ldr r0, [pc, #12] @ (80150bc ) 80150b0: 6800 ldr r0, [r0, #0] 80150b2: f7ff ffc9 bl 8015048 <_vsniprintf_r> 80150b6: b003 add sp, #12 80150b8: f85d fb04 ldr.w pc, [sp], #4 80150bc: 2000009c .word 0x2000009c 080150c0 <_fwalk_sglue>: 80150c0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 80150c4: 4607 mov r7, r0 80150c6: 4688 mov r8, r1 80150c8: 4614 mov r4, r2 80150ca: 2600 movs r6, #0 80150cc: e9d4 9501 ldrd r9, r5, [r4, #4] 80150d0: f1b9 0901 subs.w r9, r9, #1 80150d4: d505 bpl.n 80150e2 <_fwalk_sglue+0x22> 80150d6: 6824 ldr r4, [r4, #0] 80150d8: 2c00 cmp r4, #0 80150da: d1f7 bne.n 80150cc <_fwalk_sglue+0xc> 80150dc: 4630 mov r0, r6 80150de: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 80150e2: 89ab ldrh r3, [r5, #12] 80150e4: 2b01 cmp r3, #1 80150e6: d907 bls.n 80150f8 <_fwalk_sglue+0x38> 80150e8: f9b5 300e ldrsh.w r3, [r5, #14] 80150ec: 3301 adds r3, #1 80150ee: d003 beq.n 80150f8 <_fwalk_sglue+0x38> 80150f0: 4629 mov r1, r5 80150f2: 4638 mov r0, r7 80150f4: 47c0 blx r8 80150f6: 4306 orrs r6, r0 80150f8: 3568 adds r5, #104 @ 0x68 80150fa: e7e9 b.n 80150d0 <_fwalk_sglue+0x10> 080150fc : 80150fc: 4603 mov r3, r0 80150fe: 4402 add r2, r0 8015100: 4293 cmp r3, r2 8015102: d100 bne.n 8015106 8015104: 4770 bx lr 8015106: f803 1b01 strb.w r1, [r3], #1 801510a: e7f9 b.n 8015100 0801510c <__errno>: 801510c: 4b01 ldr r3, [pc, #4] @ (8015114 <__errno+0x8>) 801510e: 6818 ldr r0, [r3, #0] 8015110: 4770 bx lr 8015112: bf00 nop 8015114: 2000009c .word 0x2000009c 08015118 <__libc_init_array>: 8015118: b570 push {r4, r5, r6, lr} 801511a: 2600 movs r6, #0 801511c: 4d0c ldr r5, [pc, #48] @ (8015150 <__libc_init_array+0x38>) 801511e: 4c0d ldr r4, [pc, #52] @ (8015154 <__libc_init_array+0x3c>) 8015120: 1b64 subs r4, r4, r5 8015122: 10a4 asrs r4, r4, #2 8015124: 42a6 cmp r6, r4 8015126: d109 bne.n 801513c <__libc_init_array+0x24> 8015128: f002 f904 bl 8017334 <_init> 801512c: 2600 movs r6, #0 801512e: 4d0a ldr r5, [pc, #40] @ (8015158 <__libc_init_array+0x40>) 8015130: 4c0a ldr r4, [pc, #40] @ (801515c <__libc_init_array+0x44>) 8015132: 1b64 subs r4, r4, r5 8015134: 10a4 asrs r4, r4, #2 8015136: 42a6 cmp r6, r4 8015138: d105 bne.n 8015146 <__libc_init_array+0x2e> 801513a: bd70 pop {r4, r5, r6, pc} 801513c: f855 3b04 ldr.w r3, [r5], #4 8015140: 4798 blx r3 8015142: 3601 adds r6, #1 8015144: e7ee b.n 8015124 <__libc_init_array+0xc> 8015146: f855 3b04 ldr.w r3, [r5], #4 801514a: 4798 blx r3 801514c: 3601 adds r6, #1 801514e: e7f2 b.n 8015136 <__libc_init_array+0x1e> 8015150: 0801813c .word 0x0801813c 8015154: 0801813c .word 0x0801813c 8015158: 0801813c .word 0x0801813c 801515c: 08018140 .word 0x08018140 08015160 <__retarget_lock_init_recursive>: 8015160: 4770 bx lr 08015162 <__retarget_lock_acquire_recursive>: 8015162: 4770 bx lr 08015164 <__retarget_lock_release_recursive>: 8015164: 4770 bx lr ... 08015168 <_localeconv_r>: 8015168: 4800 ldr r0, [pc, #0] @ (801516c <_localeconv_r+0x4>) 801516a: 4770 bx lr 801516c: 200001dc .word 0x200001dc 08015170 : 8015170: 4603 mov r3, r0 8015172: b510 push {r4, lr} 8015174: b2c9 uxtb r1, r1 8015176: 4402 add r2, r0 8015178: 4293 cmp r3, r2 801517a: 4618 mov r0, r3 801517c: d101 bne.n 8015182 801517e: 2000 movs r0, #0 8015180: e003 b.n 801518a 8015182: 7804 ldrb r4, [r0, #0] 8015184: 3301 adds r3, #1 8015186: 428c cmp r4, r1 8015188: d1f6 bne.n 8015178 801518a: bd10 pop {r4, pc} 0801518c : 801518c: 440a add r2, r1 801518e: 4291 cmp r1, r2 8015190: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8015194: d100 bne.n 8015198 8015196: 4770 bx lr 8015198: b510 push {r4, lr} 801519a: f811 4b01 ldrb.w r4, [r1], #1 801519e: 4291 cmp r1, r2 80151a0: f803 4f01 strb.w r4, [r3, #1]! 80151a4: d1f9 bne.n 801519a 80151a6: bd10 pop {r4, pc} 080151a8 <__assert_func>: 80151a8: b51f push {r0, r1, r2, r3, r4, lr} 80151aa: 4614 mov r4, r2 80151ac: 461a mov r2, r3 80151ae: 4b09 ldr r3, [pc, #36] @ (80151d4 <__assert_func+0x2c>) 80151b0: 4605 mov r5, r0 80151b2: 681b ldr r3, [r3, #0] 80151b4: 68d8 ldr r0, [r3, #12] 80151b6: b14c cbz r4, 80151cc <__assert_func+0x24> 80151b8: 4b07 ldr r3, [pc, #28] @ (80151d8 <__assert_func+0x30>) 80151ba: e9cd 3401 strd r3, r4, [sp, #4] 80151be: 9100 str r1, [sp, #0] 80151c0: 462b mov r3, r5 80151c2: 4906 ldr r1, [pc, #24] @ (80151dc <__assert_func+0x34>) 80151c4: f001 fce0 bl 8016b88 80151c8: f001 fd8e bl 8016ce8 80151cc: 4b04 ldr r3, [pc, #16] @ (80151e0 <__assert_func+0x38>) 80151ce: 461c mov r4, r3 80151d0: e7f3 b.n 80151ba <__assert_func+0x12> 80151d2: bf00 nop 80151d4: 2000009c .word 0x2000009c 80151d8: 08017df0 .word 0x08017df0 80151dc: 08017dfd .word 0x08017dfd 80151e0: 08017e2b .word 0x08017e2b 080151e4 : 80151e4: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 80151e8: 6903 ldr r3, [r0, #16] 80151ea: 690c ldr r4, [r1, #16] 80151ec: 4607 mov r7, r0 80151ee: 42a3 cmp r3, r4 80151f0: db7e blt.n 80152f0 80151f2: 3c01 subs r4, #1 80151f4: 00a3 lsls r3, r4, #2 80151f6: f100 0514 add.w r5, r0, #20 80151fa: f101 0814 add.w r8, r1, #20 80151fe: 9300 str r3, [sp, #0] 8015200: eb05 0384 add.w r3, r5, r4, lsl #2 8015204: 9301 str r3, [sp, #4] 8015206: f858 3024 ldr.w r3, [r8, r4, lsl #2] 801520a: f855 2024 ldr.w r2, [r5, r4, lsl #2] 801520e: 3301 adds r3, #1 8015210: 429a cmp r2, r3 8015212: fbb2 f6f3 udiv r6, r2, r3 8015216: eb08 0984 add.w r9, r8, r4, lsl #2 801521a: d32e bcc.n 801527a 801521c: f04f 0a00 mov.w sl, #0 8015220: 46c4 mov ip, r8 8015222: 46ae mov lr, r5 8015224: 46d3 mov fp, sl 8015226: f85c 3b04 ldr.w r3, [ip], #4 801522a: b298 uxth r0, r3 801522c: fb06 a000 mla r0, r6, r0, sl 8015230: 0c1b lsrs r3, r3, #16 8015232: 0c02 lsrs r2, r0, #16 8015234: fb06 2303 mla r3, r6, r3, r2 8015238: f8de 2000 ldr.w r2, [lr] 801523c: b280 uxth r0, r0 801523e: b292 uxth r2, r2 8015240: 1a12 subs r2, r2, r0 8015242: 445a add r2, fp 8015244: f8de 0000 ldr.w r0, [lr] 8015248: ea4f 4a13 mov.w sl, r3, lsr #16 801524c: b29b uxth r3, r3 801524e: ebc3 4322 rsb r3, r3, r2, asr #16 8015252: eb03 4310 add.w r3, r3, r0, lsr #16 8015256: b292 uxth r2, r2 8015258: ea42 4203 orr.w r2, r2, r3, lsl #16 801525c: 45e1 cmp r9, ip 801525e: ea4f 4b23 mov.w fp, r3, asr #16 8015262: f84e 2b04 str.w r2, [lr], #4 8015266: d2de bcs.n 8015226 8015268: 9b00 ldr r3, [sp, #0] 801526a: 58eb ldr r3, [r5, r3] 801526c: b92b cbnz r3, 801527a 801526e: 9b01 ldr r3, [sp, #4] 8015270: 3b04 subs r3, #4 8015272: 429d cmp r5, r3 8015274: 461a mov r2, r3 8015276: d32f bcc.n 80152d8 8015278: 613c str r4, [r7, #16] 801527a: 4638 mov r0, r7 801527c: f001 fb38 bl 80168f0 <__mcmp> 8015280: 2800 cmp r0, #0 8015282: db25 blt.n 80152d0 8015284: 4629 mov r1, r5 8015286: 2000 movs r0, #0 8015288: f858 2b04 ldr.w r2, [r8], #4 801528c: f8d1 c000 ldr.w ip, [r1] 8015290: fa1f fe82 uxth.w lr, r2 8015294: fa1f f38c uxth.w r3, ip 8015298: eba3 030e sub.w r3, r3, lr 801529c: 4403 add r3, r0 801529e: 0c12 lsrs r2, r2, #16 80152a0: ebc2 4223 rsb r2, r2, r3, asr #16 80152a4: eb02 421c add.w r2, r2, ip, lsr #16 80152a8: b29b uxth r3, r3 80152aa: ea43 4302 orr.w r3, r3, r2, lsl #16 80152ae: 45c1 cmp r9, r8 80152b0: ea4f 4022 mov.w r0, r2, asr #16 80152b4: f841 3b04 str.w r3, [r1], #4 80152b8: d2e6 bcs.n 8015288 80152ba: f855 2024 ldr.w r2, [r5, r4, lsl #2] 80152be: eb05 0384 add.w r3, r5, r4, lsl #2 80152c2: b922 cbnz r2, 80152ce 80152c4: 3b04 subs r3, #4 80152c6: 429d cmp r5, r3 80152c8: 461a mov r2, r3 80152ca: d30b bcc.n 80152e4 80152cc: 613c str r4, [r7, #16] 80152ce: 3601 adds r6, #1 80152d0: 4630 mov r0, r6 80152d2: b003 add sp, #12 80152d4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80152d8: 6812 ldr r2, [r2, #0] 80152da: 3b04 subs r3, #4 80152dc: 2a00 cmp r2, #0 80152de: d1cb bne.n 8015278 80152e0: 3c01 subs r4, #1 80152e2: e7c6 b.n 8015272 80152e4: 6812 ldr r2, [r2, #0] 80152e6: 3b04 subs r3, #4 80152e8: 2a00 cmp r2, #0 80152ea: d1ef bne.n 80152cc 80152ec: 3c01 subs r4, #1 80152ee: e7ea b.n 80152c6 80152f0: 2000 movs r0, #0 80152f2: e7ee b.n 80152d2 80152f4: 0000 movs r0, r0 ... 080152f8 <_dtoa_r>: 80152f8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80152fc: 4614 mov r4, r2 80152fe: 461d mov r5, r3 8015300: 69c7 ldr r7, [r0, #28] 8015302: b097 sub sp, #92 @ 0x5c 8015304: 4681 mov r9, r0 8015306: e9cd 4506 strd r4, r5, [sp, #24] 801530a: 9e23 ldr r6, [sp, #140] @ 0x8c 801530c: b97f cbnz r7, 801532e <_dtoa_r+0x36> 801530e: 2010 movs r0, #16 8015310: f000 ff1e bl 8016150 8015314: 4602 mov r2, r0 8015316: f8c9 001c str.w r0, [r9, #28] 801531a: b920 cbnz r0, 8015326 <_dtoa_r+0x2e> 801531c: 21ef movs r1, #239 @ 0xef 801531e: 4bac ldr r3, [pc, #688] @ (80155d0 <_dtoa_r+0x2d8>) 8015320: 48ac ldr r0, [pc, #688] @ (80155d4 <_dtoa_r+0x2dc>) 8015322: f7ff ff41 bl 80151a8 <__assert_func> 8015326: e9c0 7701 strd r7, r7, [r0, #4] 801532a: 6007 str r7, [r0, #0] 801532c: 60c7 str r7, [r0, #12] 801532e: f8d9 301c ldr.w r3, [r9, #28] 8015332: 6819 ldr r1, [r3, #0] 8015334: b159 cbz r1, 801534e <_dtoa_r+0x56> 8015336: 685a ldr r2, [r3, #4] 8015338: 2301 movs r3, #1 801533a: 4093 lsls r3, r2 801533c: 604a str r2, [r1, #4] 801533e: 608b str r3, [r1, #8] 8015340: 4648 mov r0, r9 8015342: f001 f8a3 bl 801648c <_Bfree> 8015346: 2200 movs r2, #0 8015348: f8d9 301c ldr.w r3, [r9, #28] 801534c: 601a str r2, [r3, #0] 801534e: 1e2b subs r3, r5, #0 8015350: bfaf iteee ge 8015352: 2300 movge r3, #0 8015354: 2201 movlt r2, #1 8015356: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000 801535a: 9307 strlt r3, [sp, #28] 801535c: bfa8 it ge 801535e: 6033 strge r3, [r6, #0] 8015360: f8dd 801c ldr.w r8, [sp, #28] 8015364: 4b9c ldr r3, [pc, #624] @ (80155d8 <_dtoa_r+0x2e0>) 8015366: bfb8 it lt 8015368: 6032 strlt r2, [r6, #0] 801536a: ea33 0308 bics.w r3, r3, r8 801536e: d112 bne.n 8015396 <_dtoa_r+0x9e> 8015370: f242 730f movw r3, #9999 @ 0x270f 8015374: 9a22 ldr r2, [sp, #136] @ 0x88 8015376: 6013 str r3, [r2, #0] 8015378: f3c8 0313 ubfx r3, r8, #0, #20 801537c: 4323 orrs r3, r4 801537e: f000 855e beq.w 8015e3e <_dtoa_r+0xb46> 8015382: 9b24 ldr r3, [sp, #144] @ 0x90 8015384: f8df a254 ldr.w sl, [pc, #596] @ 80155dc <_dtoa_r+0x2e4> 8015388: 2b00 cmp r3, #0 801538a: f000 8560 beq.w 8015e4e <_dtoa_r+0xb56> 801538e: f10a 0303 add.w r3, sl, #3 8015392: f000 bd5a b.w 8015e4a <_dtoa_r+0xb52> 8015396: e9dd 2306 ldrd r2, r3, [sp, #24] 801539a: e9cd 230c strd r2, r3, [sp, #48] @ 0x30 801539e: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 80153a2: 2200 movs r2, #0 80153a4: 2300 movs r3, #0 80153a6: f7f3 fb6b bl 8008a80 <__aeabi_dcmpeq> 80153aa: 4607 mov r7, r0 80153ac: b158 cbz r0, 80153c6 <_dtoa_r+0xce> 80153ae: 2301 movs r3, #1 80153b0: 9a22 ldr r2, [sp, #136] @ 0x88 80153b2: 6013 str r3, [r2, #0] 80153b4: 9b24 ldr r3, [sp, #144] @ 0x90 80153b6: b113 cbz r3, 80153be <_dtoa_r+0xc6> 80153b8: 4b89 ldr r3, [pc, #548] @ (80155e0 <_dtoa_r+0x2e8>) 80153ba: 9a24 ldr r2, [sp, #144] @ 0x90 80153bc: 6013 str r3, [r2, #0] 80153be: f8df a224 ldr.w sl, [pc, #548] @ 80155e4 <_dtoa_r+0x2ec> 80153c2: f000 bd44 b.w 8015e4e <_dtoa_r+0xb56> 80153c6: ab14 add r3, sp, #80 @ 0x50 80153c8: 9301 str r3, [sp, #4] 80153ca: ab15 add r3, sp, #84 @ 0x54 80153cc: 9300 str r3, [sp, #0] 80153ce: 4648 mov r0, r9 80153d0: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30 80153d4: f001 fb3c bl 8016a50 <__d2b> 80153d8: f3c8 560a ubfx r6, r8, #20, #11 80153dc: 9003 str r0, [sp, #12] 80153de: 2e00 cmp r6, #0 80153e0: d078 beq.n 80154d4 <_dtoa_r+0x1dc> 80153e2: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 80153e6: 9b0d ldr r3, [sp, #52] @ 0x34 80153e8: f2a6 36ff subw r6, r6, #1023 @ 0x3ff 80153ec: f3c3 0313 ubfx r3, r3, #0, #20 80153f0: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000 80153f4: f443 1340 orr.w r3, r3, #3145728 @ 0x300000 80153f8: 9712 str r7, [sp, #72] @ 0x48 80153fa: 4619 mov r1, r3 80153fc: 2200 movs r2, #0 80153fe: 4b7a ldr r3, [pc, #488] @ (80155e8 <_dtoa_r+0x2f0>) 8015400: f7f2 ff1e bl 8008240 <__aeabi_dsub> 8015404: a36c add r3, pc, #432 @ (adr r3, 80155b8 <_dtoa_r+0x2c0>) 8015406: e9d3 2300 ldrd r2, r3, [r3] 801540a: f7f3 f8d1 bl 80085b0 <__aeabi_dmul> 801540e: a36c add r3, pc, #432 @ (adr r3, 80155c0 <_dtoa_r+0x2c8>) 8015410: e9d3 2300 ldrd r2, r3, [r3] 8015414: f7f2 ff16 bl 8008244 <__adddf3> 8015418: 4604 mov r4, r0 801541a: 4630 mov r0, r6 801541c: 460d mov r5, r1 801541e: f7f3 f85d bl 80084dc <__aeabi_i2d> 8015422: a369 add r3, pc, #420 @ (adr r3, 80155c8 <_dtoa_r+0x2d0>) 8015424: e9d3 2300 ldrd r2, r3, [r3] 8015428: f7f3 f8c2 bl 80085b0 <__aeabi_dmul> 801542c: 4602 mov r2, r0 801542e: 460b mov r3, r1 8015430: 4620 mov r0, r4 8015432: 4629 mov r1, r5 8015434: f7f2 ff06 bl 8008244 <__adddf3> 8015438: 4604 mov r4, r0 801543a: 460d mov r5, r1 801543c: f7f3 fb68 bl 8008b10 <__aeabi_d2iz> 8015440: 2200 movs r2, #0 8015442: 4607 mov r7, r0 8015444: 2300 movs r3, #0 8015446: 4620 mov r0, r4 8015448: 4629 mov r1, r5 801544a: f7f3 fb23 bl 8008a94 <__aeabi_dcmplt> 801544e: b140 cbz r0, 8015462 <_dtoa_r+0x16a> 8015450: 4638 mov r0, r7 8015452: f7f3 f843 bl 80084dc <__aeabi_i2d> 8015456: 4622 mov r2, r4 8015458: 462b mov r3, r5 801545a: f7f3 fb11 bl 8008a80 <__aeabi_dcmpeq> 801545e: b900 cbnz r0, 8015462 <_dtoa_r+0x16a> 8015460: 3f01 subs r7, #1 8015462: 2f16 cmp r7, #22 8015464: d854 bhi.n 8015510 <_dtoa_r+0x218> 8015466: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 801546a: 4b60 ldr r3, [pc, #384] @ (80155ec <_dtoa_r+0x2f4>) 801546c: eb03 03c7 add.w r3, r3, r7, lsl #3 8015470: e9d3 2300 ldrd r2, r3, [r3] 8015474: f7f3 fb0e bl 8008a94 <__aeabi_dcmplt> 8015478: 2800 cmp r0, #0 801547a: d04b beq.n 8015514 <_dtoa_r+0x21c> 801547c: 2300 movs r3, #0 801547e: 3f01 subs r7, #1 8015480: 930f str r3, [sp, #60] @ 0x3c 8015482: 9b14 ldr r3, [sp, #80] @ 0x50 8015484: 1b9b subs r3, r3, r6 8015486: 1e5a subs r2, r3, #1 8015488: bf49 itett mi 801548a: f1c3 0301 rsbmi r3, r3, #1 801548e: 2300 movpl r3, #0 8015490: 9304 strmi r3, [sp, #16] 8015492: 2300 movmi r3, #0 8015494: 9209 str r2, [sp, #36] @ 0x24 8015496: bf54 ite pl 8015498: 9304 strpl r3, [sp, #16] 801549a: 9309 strmi r3, [sp, #36] @ 0x24 801549c: 2f00 cmp r7, #0 801549e: db3b blt.n 8015518 <_dtoa_r+0x220> 80154a0: 9b09 ldr r3, [sp, #36] @ 0x24 80154a2: 970e str r7, [sp, #56] @ 0x38 80154a4: 443b add r3, r7 80154a6: 9309 str r3, [sp, #36] @ 0x24 80154a8: 2300 movs r3, #0 80154aa: 930a str r3, [sp, #40] @ 0x28 80154ac: 9b20 ldr r3, [sp, #128] @ 0x80 80154ae: 2b09 cmp r3, #9 80154b0: d865 bhi.n 801557e <_dtoa_r+0x286> 80154b2: 2b05 cmp r3, #5 80154b4: bfc4 itt gt 80154b6: 3b04 subgt r3, #4 80154b8: 9320 strgt r3, [sp, #128] @ 0x80 80154ba: 9b20 ldr r3, [sp, #128] @ 0x80 80154bc: bfc8 it gt 80154be: 2400 movgt r4, #0 80154c0: f1a3 0302 sub.w r3, r3, #2 80154c4: bfd8 it le 80154c6: 2401 movle r4, #1 80154c8: 2b03 cmp r3, #3 80154ca: d864 bhi.n 8015596 <_dtoa_r+0x29e> 80154cc: e8df f003 tbb [pc, r3] 80154d0: 2c385553 .word 0x2c385553 80154d4: e9dd 6314 ldrd r6, r3, [sp, #80] @ 0x50 80154d8: 441e add r6, r3 80154da: f206 4332 addw r3, r6, #1074 @ 0x432 80154de: 2b20 cmp r3, #32 80154e0: bfc1 itttt gt 80154e2: f1c3 0340 rsbgt r3, r3, #64 @ 0x40 80154e6: fa08 f803 lslgt.w r8, r8, r3 80154ea: f206 4312 addwgt r3, r6, #1042 @ 0x412 80154ee: fa24 f303 lsrgt.w r3, r4, r3 80154f2: bfd6 itet le 80154f4: f1c3 0320 rsble r3, r3, #32 80154f8: ea48 0003 orrgt.w r0, r8, r3 80154fc: fa04 f003 lslle.w r0, r4, r3 8015500: f7f2 ffdc bl 80084bc <__aeabi_ui2d> 8015504: 2201 movs r2, #1 8015506: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000 801550a: 3e01 subs r6, #1 801550c: 9212 str r2, [sp, #72] @ 0x48 801550e: e774 b.n 80153fa <_dtoa_r+0x102> 8015510: 2301 movs r3, #1 8015512: e7b5 b.n 8015480 <_dtoa_r+0x188> 8015514: 900f str r0, [sp, #60] @ 0x3c 8015516: e7b4 b.n 8015482 <_dtoa_r+0x18a> 8015518: 9b04 ldr r3, [sp, #16] 801551a: 1bdb subs r3, r3, r7 801551c: 9304 str r3, [sp, #16] 801551e: 427b negs r3, r7 8015520: 930a str r3, [sp, #40] @ 0x28 8015522: 2300 movs r3, #0 8015524: 930e str r3, [sp, #56] @ 0x38 8015526: e7c1 b.n 80154ac <_dtoa_r+0x1b4> 8015528: 2301 movs r3, #1 801552a: 930b str r3, [sp, #44] @ 0x2c 801552c: 9b21 ldr r3, [sp, #132] @ 0x84 801552e: eb07 0b03 add.w fp, r7, r3 8015532: f10b 0301 add.w r3, fp, #1 8015536: 2b01 cmp r3, #1 8015538: 9308 str r3, [sp, #32] 801553a: bfb8 it lt 801553c: 2301 movlt r3, #1 801553e: e006 b.n 801554e <_dtoa_r+0x256> 8015540: 2301 movs r3, #1 8015542: 930b str r3, [sp, #44] @ 0x2c 8015544: 9b21 ldr r3, [sp, #132] @ 0x84 8015546: 2b00 cmp r3, #0 8015548: dd28 ble.n 801559c <_dtoa_r+0x2a4> 801554a: 469b mov fp, r3 801554c: 9308 str r3, [sp, #32] 801554e: 2100 movs r1, #0 8015550: 2204 movs r2, #4 8015552: f8d9 001c ldr.w r0, [r9, #28] 8015556: f102 0514 add.w r5, r2, #20 801555a: 429d cmp r5, r3 801555c: d926 bls.n 80155ac <_dtoa_r+0x2b4> 801555e: 6041 str r1, [r0, #4] 8015560: 4648 mov r0, r9 8015562: f000 ff53 bl 801640c <_Balloc> 8015566: 4682 mov sl, r0 8015568: 2800 cmp r0, #0 801556a: d143 bne.n 80155f4 <_dtoa_r+0x2fc> 801556c: 4602 mov r2, r0 801556e: f240 11af movw r1, #431 @ 0x1af 8015572: 4b1f ldr r3, [pc, #124] @ (80155f0 <_dtoa_r+0x2f8>) 8015574: e6d4 b.n 8015320 <_dtoa_r+0x28> 8015576: 2300 movs r3, #0 8015578: e7e3 b.n 8015542 <_dtoa_r+0x24a> 801557a: 2300 movs r3, #0 801557c: e7d5 b.n 801552a <_dtoa_r+0x232> 801557e: 2401 movs r4, #1 8015580: 2300 movs r3, #0 8015582: 940b str r4, [sp, #44] @ 0x2c 8015584: 9320 str r3, [sp, #128] @ 0x80 8015586: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff 801558a: 2200 movs r2, #0 801558c: 2312 movs r3, #18 801558e: f8cd b020 str.w fp, [sp, #32] 8015592: 9221 str r2, [sp, #132] @ 0x84 8015594: e7db b.n 801554e <_dtoa_r+0x256> 8015596: 2301 movs r3, #1 8015598: 930b str r3, [sp, #44] @ 0x2c 801559a: e7f4 b.n 8015586 <_dtoa_r+0x28e> 801559c: f04f 0b01 mov.w fp, #1 80155a0: 465b mov r3, fp 80155a2: f8cd b020 str.w fp, [sp, #32] 80155a6: f8cd b084 str.w fp, [sp, #132] @ 0x84 80155aa: e7d0 b.n 801554e <_dtoa_r+0x256> 80155ac: 3101 adds r1, #1 80155ae: 0052 lsls r2, r2, #1 80155b0: e7d1 b.n 8015556 <_dtoa_r+0x25e> 80155b2: bf00 nop 80155b4: f3af 8000 nop.w 80155b8: 636f4361 .word 0x636f4361 80155bc: 3fd287a7 .word 0x3fd287a7 80155c0: 8b60c8b3 .word 0x8b60c8b3 80155c4: 3fc68a28 .word 0x3fc68a28 80155c8: 509f79fb .word 0x509f79fb 80155cc: 3fd34413 .word 0x3fd34413 80155d0: 08017e39 .word 0x08017e39 80155d4: 08017e50 .word 0x08017e50 80155d8: 7ff00000 .word 0x7ff00000 80155dc: 08017e35 .word 0x08017e35 80155e0: 08017dcd .word 0x08017dcd 80155e4: 08017dcc .word 0x08017dcc 80155e8: 3ff80000 .word 0x3ff80000 80155ec: 08017f68 .word 0x08017f68 80155f0: 08017ea8 .word 0x08017ea8 80155f4: f8d9 301c ldr.w r3, [r9, #28] 80155f8: 6018 str r0, [r3, #0] 80155fa: 9b08 ldr r3, [sp, #32] 80155fc: 2b0e cmp r3, #14 80155fe: f200 80a1 bhi.w 8015744 <_dtoa_r+0x44c> 8015602: 2c00 cmp r4, #0 8015604: f000 809e beq.w 8015744 <_dtoa_r+0x44c> 8015608: 2f00 cmp r7, #0 801560a: dd33 ble.n 8015674 <_dtoa_r+0x37c> 801560c: 4b9c ldr r3, [pc, #624] @ (8015880 <_dtoa_r+0x588>) 801560e: f007 020f and.w r2, r7, #15 8015612: eb03 03c2 add.w r3, r3, r2, lsl #3 8015616: 05f8 lsls r0, r7, #23 8015618: e9d3 3400 ldrd r3, r4, [r3] 801561c: e9cd 3410 strd r3, r4, [sp, #64] @ 0x40 8015620: ea4f 1427 mov.w r4, r7, asr #4 8015624: d516 bpl.n 8015654 <_dtoa_r+0x35c> 8015626: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 801562a: 4b96 ldr r3, [pc, #600] @ (8015884 <_dtoa_r+0x58c>) 801562c: 2603 movs r6, #3 801562e: e9d3 2308 ldrd r2, r3, [r3, #32] 8015632: f7f3 f8e7 bl 8008804 <__aeabi_ddiv> 8015636: e9cd 0106 strd r0, r1, [sp, #24] 801563a: f004 040f and.w r4, r4, #15 801563e: 4d91 ldr r5, [pc, #580] @ (8015884 <_dtoa_r+0x58c>) 8015640: b954 cbnz r4, 8015658 <_dtoa_r+0x360> 8015642: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8015646: e9dd 0106 ldrd r0, r1, [sp, #24] 801564a: f7f3 f8db bl 8008804 <__aeabi_ddiv> 801564e: e9cd 0106 strd r0, r1, [sp, #24] 8015652: e028 b.n 80156a6 <_dtoa_r+0x3ae> 8015654: 2602 movs r6, #2 8015656: e7f2 b.n 801563e <_dtoa_r+0x346> 8015658: 07e1 lsls r1, r4, #31 801565a: d508 bpl.n 801566e <_dtoa_r+0x376> 801565c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8015660: e9d5 2300 ldrd r2, r3, [r5] 8015664: f7f2 ffa4 bl 80085b0 <__aeabi_dmul> 8015668: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 801566c: 3601 adds r6, #1 801566e: 1064 asrs r4, r4, #1 8015670: 3508 adds r5, #8 8015672: e7e5 b.n 8015640 <_dtoa_r+0x348> 8015674: f000 80af beq.w 80157d6 <_dtoa_r+0x4de> 8015678: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 801567c: 427c negs r4, r7 801567e: 4b80 ldr r3, [pc, #512] @ (8015880 <_dtoa_r+0x588>) 8015680: f004 020f and.w r2, r4, #15 8015684: eb03 03c2 add.w r3, r3, r2, lsl #3 8015688: e9d3 2300 ldrd r2, r3, [r3] 801568c: f7f2 ff90 bl 80085b0 <__aeabi_dmul> 8015690: 2602 movs r6, #2 8015692: 2300 movs r3, #0 8015694: e9cd 0106 strd r0, r1, [sp, #24] 8015698: 4d7a ldr r5, [pc, #488] @ (8015884 <_dtoa_r+0x58c>) 801569a: 1124 asrs r4, r4, #4 801569c: 2c00 cmp r4, #0 801569e: f040 808f bne.w 80157c0 <_dtoa_r+0x4c8> 80156a2: 2b00 cmp r3, #0 80156a4: d1d3 bne.n 801564e <_dtoa_r+0x356> 80156a6: e9dd 4506 ldrd r4, r5, [sp, #24] 80156aa: 9b0f ldr r3, [sp, #60] @ 0x3c 80156ac: 2b00 cmp r3, #0 80156ae: f000 8094 beq.w 80157da <_dtoa_r+0x4e2> 80156b2: 2200 movs r2, #0 80156b4: 4620 mov r0, r4 80156b6: 4629 mov r1, r5 80156b8: 4b73 ldr r3, [pc, #460] @ (8015888 <_dtoa_r+0x590>) 80156ba: f7f3 f9eb bl 8008a94 <__aeabi_dcmplt> 80156be: 2800 cmp r0, #0 80156c0: f000 808b beq.w 80157da <_dtoa_r+0x4e2> 80156c4: 9b08 ldr r3, [sp, #32] 80156c6: 2b00 cmp r3, #0 80156c8: f000 8087 beq.w 80157da <_dtoa_r+0x4e2> 80156cc: f1bb 0f00 cmp.w fp, #0 80156d0: dd34 ble.n 801573c <_dtoa_r+0x444> 80156d2: 4620 mov r0, r4 80156d4: 2200 movs r2, #0 80156d6: 4629 mov r1, r5 80156d8: 4b6c ldr r3, [pc, #432] @ (801588c <_dtoa_r+0x594>) 80156da: f7f2 ff69 bl 80085b0 <__aeabi_dmul> 80156de: 465c mov r4, fp 80156e0: e9cd 0106 strd r0, r1, [sp, #24] 80156e4: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 80156e8: 3601 adds r6, #1 80156ea: 4630 mov r0, r6 80156ec: f7f2 fef6 bl 80084dc <__aeabi_i2d> 80156f0: e9dd 2306 ldrd r2, r3, [sp, #24] 80156f4: f7f2 ff5c bl 80085b0 <__aeabi_dmul> 80156f8: 2200 movs r2, #0 80156fa: 4b65 ldr r3, [pc, #404] @ (8015890 <_dtoa_r+0x598>) 80156fc: f7f2 fda2 bl 8008244 <__adddf3> 8015700: 4605 mov r5, r0 8015702: f1a1 7650 sub.w r6, r1, #54525952 @ 0x3400000 8015706: 2c00 cmp r4, #0 8015708: d16a bne.n 80157e0 <_dtoa_r+0x4e8> 801570a: e9dd 0106 ldrd r0, r1, [sp, #24] 801570e: 2200 movs r2, #0 8015710: 4b60 ldr r3, [pc, #384] @ (8015894 <_dtoa_r+0x59c>) 8015712: f7f2 fd95 bl 8008240 <__aeabi_dsub> 8015716: 4602 mov r2, r0 8015718: 460b mov r3, r1 801571a: e9cd 2306 strd r2, r3, [sp, #24] 801571e: 462a mov r2, r5 8015720: 4633 mov r3, r6 8015722: f7f3 f9d5 bl 8008ad0 <__aeabi_dcmpgt> 8015726: 2800 cmp r0, #0 8015728: f040 8298 bne.w 8015c5c <_dtoa_r+0x964> 801572c: e9dd 0106 ldrd r0, r1, [sp, #24] 8015730: 462a mov r2, r5 8015732: f106 4300 add.w r3, r6, #2147483648 @ 0x80000000 8015736: f7f3 f9ad bl 8008a94 <__aeabi_dcmplt> 801573a: bb38 cbnz r0, 801578c <_dtoa_r+0x494> 801573c: e9dd 340c ldrd r3, r4, [sp, #48] @ 0x30 8015740: e9cd 3406 strd r3, r4, [sp, #24] 8015744: 9b15 ldr r3, [sp, #84] @ 0x54 8015746: 2b00 cmp r3, #0 8015748: f2c0 8157 blt.w 80159fa <_dtoa_r+0x702> 801574c: 2f0e cmp r7, #14 801574e: f300 8154 bgt.w 80159fa <_dtoa_r+0x702> 8015752: 4b4b ldr r3, [pc, #300] @ (8015880 <_dtoa_r+0x588>) 8015754: eb03 03c7 add.w r3, r3, r7, lsl #3 8015758: e9d3 3400 ldrd r3, r4, [r3] 801575c: e9cd 3404 strd r3, r4, [sp, #16] 8015760: 9b21 ldr r3, [sp, #132] @ 0x84 8015762: 2b00 cmp r3, #0 8015764: f280 80e5 bge.w 8015932 <_dtoa_r+0x63a> 8015768: 9b08 ldr r3, [sp, #32] 801576a: 2b00 cmp r3, #0 801576c: f300 80e1 bgt.w 8015932 <_dtoa_r+0x63a> 8015770: d10c bne.n 801578c <_dtoa_r+0x494> 8015772: e9dd 0104 ldrd r0, r1, [sp, #16] 8015776: 2200 movs r2, #0 8015778: 4b46 ldr r3, [pc, #280] @ (8015894 <_dtoa_r+0x59c>) 801577a: f7f2 ff19 bl 80085b0 <__aeabi_dmul> 801577e: e9dd 2306 ldrd r2, r3, [sp, #24] 8015782: f7f3 f99b bl 8008abc <__aeabi_dcmpge> 8015786: 2800 cmp r0, #0 8015788: f000 8266 beq.w 8015c58 <_dtoa_r+0x960> 801578c: 2400 movs r4, #0 801578e: 4625 mov r5, r4 8015790: 9b21 ldr r3, [sp, #132] @ 0x84 8015792: 4656 mov r6, sl 8015794: ea6f 0803 mvn.w r8, r3 8015798: 2700 movs r7, #0 801579a: 4621 mov r1, r4 801579c: 4648 mov r0, r9 801579e: f000 fe75 bl 801648c <_Bfree> 80157a2: 2d00 cmp r5, #0 80157a4: f000 80bd beq.w 8015922 <_dtoa_r+0x62a> 80157a8: b12f cbz r7, 80157b6 <_dtoa_r+0x4be> 80157aa: 42af cmp r7, r5 80157ac: d003 beq.n 80157b6 <_dtoa_r+0x4be> 80157ae: 4639 mov r1, r7 80157b0: 4648 mov r0, r9 80157b2: f000 fe6b bl 801648c <_Bfree> 80157b6: 4629 mov r1, r5 80157b8: 4648 mov r0, r9 80157ba: f000 fe67 bl 801648c <_Bfree> 80157be: e0b0 b.n 8015922 <_dtoa_r+0x62a> 80157c0: 07e2 lsls r2, r4, #31 80157c2: d505 bpl.n 80157d0 <_dtoa_r+0x4d8> 80157c4: e9d5 2300 ldrd r2, r3, [r5] 80157c8: f7f2 fef2 bl 80085b0 <__aeabi_dmul> 80157cc: 2301 movs r3, #1 80157ce: 3601 adds r6, #1 80157d0: 1064 asrs r4, r4, #1 80157d2: 3508 adds r5, #8 80157d4: e762 b.n 801569c <_dtoa_r+0x3a4> 80157d6: 2602 movs r6, #2 80157d8: e765 b.n 80156a6 <_dtoa_r+0x3ae> 80157da: 46b8 mov r8, r7 80157dc: 9c08 ldr r4, [sp, #32] 80157de: e784 b.n 80156ea <_dtoa_r+0x3f2> 80157e0: 4b27 ldr r3, [pc, #156] @ (8015880 <_dtoa_r+0x588>) 80157e2: 990b ldr r1, [sp, #44] @ 0x2c 80157e4: eb03 03c4 add.w r3, r3, r4, lsl #3 80157e8: e953 2302 ldrd r2, r3, [r3, #-8] 80157ec: 4454 add r4, sl 80157ee: 2900 cmp r1, #0 80157f0: d054 beq.n 801589c <_dtoa_r+0x5a4> 80157f2: 2000 movs r0, #0 80157f4: 4928 ldr r1, [pc, #160] @ (8015898 <_dtoa_r+0x5a0>) 80157f6: f7f3 f805 bl 8008804 <__aeabi_ddiv> 80157fa: 4633 mov r3, r6 80157fc: 462a mov r2, r5 80157fe: f7f2 fd1f bl 8008240 <__aeabi_dsub> 8015802: 4656 mov r6, sl 8015804: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 8015808: e9dd 0106 ldrd r0, r1, [sp, #24] 801580c: f7f3 f980 bl 8008b10 <__aeabi_d2iz> 8015810: 4605 mov r5, r0 8015812: f7f2 fe63 bl 80084dc <__aeabi_i2d> 8015816: 4602 mov r2, r0 8015818: 460b mov r3, r1 801581a: e9dd 0106 ldrd r0, r1, [sp, #24] 801581e: f7f2 fd0f bl 8008240 <__aeabi_dsub> 8015822: 4602 mov r2, r0 8015824: 460b mov r3, r1 8015826: 3530 adds r5, #48 @ 0x30 8015828: e9cd 2306 strd r2, r3, [sp, #24] 801582c: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8015830: f806 5b01 strb.w r5, [r6], #1 8015834: f7f3 f92e bl 8008a94 <__aeabi_dcmplt> 8015838: 2800 cmp r0, #0 801583a: d172 bne.n 8015922 <_dtoa_r+0x62a> 801583c: e9dd 2306 ldrd r2, r3, [sp, #24] 8015840: 2000 movs r0, #0 8015842: 4911 ldr r1, [pc, #68] @ (8015888 <_dtoa_r+0x590>) 8015844: f7f2 fcfc bl 8008240 <__aeabi_dsub> 8015848: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 801584c: f7f3 f922 bl 8008a94 <__aeabi_dcmplt> 8015850: 2800 cmp r0, #0 8015852: f040 80b4 bne.w 80159be <_dtoa_r+0x6c6> 8015856: 42a6 cmp r6, r4 8015858: f43f af70 beq.w 801573c <_dtoa_r+0x444> 801585c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8015860: 2200 movs r2, #0 8015862: 4b0a ldr r3, [pc, #40] @ (801588c <_dtoa_r+0x594>) 8015864: f7f2 fea4 bl 80085b0 <__aeabi_dmul> 8015868: 2200 movs r2, #0 801586a: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 801586e: e9dd 0106 ldrd r0, r1, [sp, #24] 8015872: 4b06 ldr r3, [pc, #24] @ (801588c <_dtoa_r+0x594>) 8015874: f7f2 fe9c bl 80085b0 <__aeabi_dmul> 8015878: e9cd 0106 strd r0, r1, [sp, #24] 801587c: e7c4 b.n 8015808 <_dtoa_r+0x510> 801587e: bf00 nop 8015880: 08017f68 .word 0x08017f68 8015884: 08017f40 .word 0x08017f40 8015888: 3ff00000 .word 0x3ff00000 801588c: 40240000 .word 0x40240000 8015890: 401c0000 .word 0x401c0000 8015894: 40140000 .word 0x40140000 8015898: 3fe00000 .word 0x3fe00000 801589c: 4631 mov r1, r6 801589e: 4628 mov r0, r5 80158a0: f7f2 fe86 bl 80085b0 <__aeabi_dmul> 80158a4: 4656 mov r6, sl 80158a6: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 80158aa: 9413 str r4, [sp, #76] @ 0x4c 80158ac: e9dd 0106 ldrd r0, r1, [sp, #24] 80158b0: f7f3 f92e bl 8008b10 <__aeabi_d2iz> 80158b4: 4605 mov r5, r0 80158b6: f7f2 fe11 bl 80084dc <__aeabi_i2d> 80158ba: 4602 mov r2, r0 80158bc: 460b mov r3, r1 80158be: e9dd 0106 ldrd r0, r1, [sp, #24] 80158c2: f7f2 fcbd bl 8008240 <__aeabi_dsub> 80158c6: 4602 mov r2, r0 80158c8: 460b mov r3, r1 80158ca: 3530 adds r5, #48 @ 0x30 80158cc: f806 5b01 strb.w r5, [r6], #1 80158d0: 42a6 cmp r6, r4 80158d2: e9cd 2306 strd r2, r3, [sp, #24] 80158d6: f04f 0200 mov.w r2, #0 80158da: d124 bne.n 8015926 <_dtoa_r+0x62e> 80158dc: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 80158e0: 4bae ldr r3, [pc, #696] @ (8015b9c <_dtoa_r+0x8a4>) 80158e2: f7f2 fcaf bl 8008244 <__adddf3> 80158e6: 4602 mov r2, r0 80158e8: 460b mov r3, r1 80158ea: e9dd 0106 ldrd r0, r1, [sp, #24] 80158ee: f7f3 f8ef bl 8008ad0 <__aeabi_dcmpgt> 80158f2: 2800 cmp r0, #0 80158f4: d163 bne.n 80159be <_dtoa_r+0x6c6> 80158f6: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 80158fa: 2000 movs r0, #0 80158fc: 49a7 ldr r1, [pc, #668] @ (8015b9c <_dtoa_r+0x8a4>) 80158fe: f7f2 fc9f bl 8008240 <__aeabi_dsub> 8015902: 4602 mov r2, r0 8015904: 460b mov r3, r1 8015906: e9dd 0106 ldrd r0, r1, [sp, #24] 801590a: f7f3 f8c3 bl 8008a94 <__aeabi_dcmplt> 801590e: 2800 cmp r0, #0 8015910: f43f af14 beq.w 801573c <_dtoa_r+0x444> 8015914: 9e13 ldr r6, [sp, #76] @ 0x4c 8015916: 1e73 subs r3, r6, #1 8015918: 9313 str r3, [sp, #76] @ 0x4c 801591a: f816 3c01 ldrb.w r3, [r6, #-1] 801591e: 2b30 cmp r3, #48 @ 0x30 8015920: d0f8 beq.n 8015914 <_dtoa_r+0x61c> 8015922: 4647 mov r7, r8 8015924: e03b b.n 801599e <_dtoa_r+0x6a6> 8015926: 4b9e ldr r3, [pc, #632] @ (8015ba0 <_dtoa_r+0x8a8>) 8015928: f7f2 fe42 bl 80085b0 <__aeabi_dmul> 801592c: e9cd 0106 strd r0, r1, [sp, #24] 8015930: e7bc b.n 80158ac <_dtoa_r+0x5b4> 8015932: 4656 mov r6, sl 8015934: e9dd 4506 ldrd r4, r5, [sp, #24] 8015938: e9dd 2304 ldrd r2, r3, [sp, #16] 801593c: 4620 mov r0, r4 801593e: 4629 mov r1, r5 8015940: f7f2 ff60 bl 8008804 <__aeabi_ddiv> 8015944: f7f3 f8e4 bl 8008b10 <__aeabi_d2iz> 8015948: 4680 mov r8, r0 801594a: f7f2 fdc7 bl 80084dc <__aeabi_i2d> 801594e: e9dd 2304 ldrd r2, r3, [sp, #16] 8015952: f7f2 fe2d bl 80085b0 <__aeabi_dmul> 8015956: 4602 mov r2, r0 8015958: 460b mov r3, r1 801595a: 4620 mov r0, r4 801595c: 4629 mov r1, r5 801595e: f7f2 fc6f bl 8008240 <__aeabi_dsub> 8015962: f108 0430 add.w r4, r8, #48 @ 0x30 8015966: 9d08 ldr r5, [sp, #32] 8015968: f806 4b01 strb.w r4, [r6], #1 801596c: eba6 040a sub.w r4, r6, sl 8015970: 42a5 cmp r5, r4 8015972: 4602 mov r2, r0 8015974: 460b mov r3, r1 8015976: d133 bne.n 80159e0 <_dtoa_r+0x6e8> 8015978: f7f2 fc64 bl 8008244 <__adddf3> 801597c: e9dd 2304 ldrd r2, r3, [sp, #16] 8015980: 4604 mov r4, r0 8015982: 460d mov r5, r1 8015984: f7f3 f8a4 bl 8008ad0 <__aeabi_dcmpgt> 8015988: b9c0 cbnz r0, 80159bc <_dtoa_r+0x6c4> 801598a: e9dd 2304 ldrd r2, r3, [sp, #16] 801598e: 4620 mov r0, r4 8015990: 4629 mov r1, r5 8015992: f7f3 f875 bl 8008a80 <__aeabi_dcmpeq> 8015996: b110 cbz r0, 801599e <_dtoa_r+0x6a6> 8015998: f018 0f01 tst.w r8, #1 801599c: d10e bne.n 80159bc <_dtoa_r+0x6c4> 801599e: 4648 mov r0, r9 80159a0: 9903 ldr r1, [sp, #12] 80159a2: f000 fd73 bl 801648c <_Bfree> 80159a6: 2300 movs r3, #0 80159a8: 7033 strb r3, [r6, #0] 80159aa: 9b22 ldr r3, [sp, #136] @ 0x88 80159ac: 3701 adds r7, #1 80159ae: 601f str r7, [r3, #0] 80159b0: 9b24 ldr r3, [sp, #144] @ 0x90 80159b2: 2b00 cmp r3, #0 80159b4: f000 824b beq.w 8015e4e <_dtoa_r+0xb56> 80159b8: 601e str r6, [r3, #0] 80159ba: e248 b.n 8015e4e <_dtoa_r+0xb56> 80159bc: 46b8 mov r8, r7 80159be: 4633 mov r3, r6 80159c0: 461e mov r6, r3 80159c2: f813 2d01 ldrb.w r2, [r3, #-1]! 80159c6: 2a39 cmp r2, #57 @ 0x39 80159c8: d106 bne.n 80159d8 <_dtoa_r+0x6e0> 80159ca: 459a cmp sl, r3 80159cc: d1f8 bne.n 80159c0 <_dtoa_r+0x6c8> 80159ce: 2230 movs r2, #48 @ 0x30 80159d0: f108 0801 add.w r8, r8, #1 80159d4: f88a 2000 strb.w r2, [sl] 80159d8: 781a ldrb r2, [r3, #0] 80159da: 3201 adds r2, #1 80159dc: 701a strb r2, [r3, #0] 80159de: e7a0 b.n 8015922 <_dtoa_r+0x62a> 80159e0: 2200 movs r2, #0 80159e2: 4b6f ldr r3, [pc, #444] @ (8015ba0 <_dtoa_r+0x8a8>) 80159e4: f7f2 fde4 bl 80085b0 <__aeabi_dmul> 80159e8: 2200 movs r2, #0 80159ea: 2300 movs r3, #0 80159ec: 4604 mov r4, r0 80159ee: 460d mov r5, r1 80159f0: f7f3 f846 bl 8008a80 <__aeabi_dcmpeq> 80159f4: 2800 cmp r0, #0 80159f6: d09f beq.n 8015938 <_dtoa_r+0x640> 80159f8: e7d1 b.n 801599e <_dtoa_r+0x6a6> 80159fa: 9a0b ldr r2, [sp, #44] @ 0x2c 80159fc: 2a00 cmp r2, #0 80159fe: f000 80ea beq.w 8015bd6 <_dtoa_r+0x8de> 8015a02: 9a20 ldr r2, [sp, #128] @ 0x80 8015a04: 2a01 cmp r2, #1 8015a06: f300 80cd bgt.w 8015ba4 <_dtoa_r+0x8ac> 8015a0a: 9a12 ldr r2, [sp, #72] @ 0x48 8015a0c: 2a00 cmp r2, #0 8015a0e: f000 80c1 beq.w 8015b94 <_dtoa_r+0x89c> 8015a12: f203 4333 addw r3, r3, #1075 @ 0x433 8015a16: 9c0a ldr r4, [sp, #40] @ 0x28 8015a18: 9e04 ldr r6, [sp, #16] 8015a1a: 9a04 ldr r2, [sp, #16] 8015a1c: 2101 movs r1, #1 8015a1e: 441a add r2, r3 8015a20: 9204 str r2, [sp, #16] 8015a22: 9a09 ldr r2, [sp, #36] @ 0x24 8015a24: 4648 mov r0, r9 8015a26: 441a add r2, r3 8015a28: 9209 str r2, [sp, #36] @ 0x24 8015a2a: f000 fde3 bl 80165f4 <__i2b> 8015a2e: 4605 mov r5, r0 8015a30: b166 cbz r6, 8015a4c <_dtoa_r+0x754> 8015a32: 9b09 ldr r3, [sp, #36] @ 0x24 8015a34: 2b00 cmp r3, #0 8015a36: dd09 ble.n 8015a4c <_dtoa_r+0x754> 8015a38: 42b3 cmp r3, r6 8015a3a: bfa8 it ge 8015a3c: 4633 movge r3, r6 8015a3e: 9a04 ldr r2, [sp, #16] 8015a40: 1af6 subs r6, r6, r3 8015a42: 1ad2 subs r2, r2, r3 8015a44: 9204 str r2, [sp, #16] 8015a46: 9a09 ldr r2, [sp, #36] @ 0x24 8015a48: 1ad3 subs r3, r2, r3 8015a4a: 9309 str r3, [sp, #36] @ 0x24 8015a4c: 9b0a ldr r3, [sp, #40] @ 0x28 8015a4e: b30b cbz r3, 8015a94 <_dtoa_r+0x79c> 8015a50: 9b0b ldr r3, [sp, #44] @ 0x2c 8015a52: 2b00 cmp r3, #0 8015a54: f000 80c6 beq.w 8015be4 <_dtoa_r+0x8ec> 8015a58: 2c00 cmp r4, #0 8015a5a: f000 80c0 beq.w 8015bde <_dtoa_r+0x8e6> 8015a5e: 4629 mov r1, r5 8015a60: 4622 mov r2, r4 8015a62: 4648 mov r0, r9 8015a64: f000 fe7e bl 8016764 <__pow5mult> 8015a68: 9a03 ldr r2, [sp, #12] 8015a6a: 4601 mov r1, r0 8015a6c: 4605 mov r5, r0 8015a6e: 4648 mov r0, r9 8015a70: f000 fdd6 bl 8016620 <__multiply> 8015a74: 9903 ldr r1, [sp, #12] 8015a76: 4680 mov r8, r0 8015a78: 4648 mov r0, r9 8015a7a: f000 fd07 bl 801648c <_Bfree> 8015a7e: 9b0a ldr r3, [sp, #40] @ 0x28 8015a80: 1b1b subs r3, r3, r4 8015a82: 930a str r3, [sp, #40] @ 0x28 8015a84: f000 80b1 beq.w 8015bea <_dtoa_r+0x8f2> 8015a88: 4641 mov r1, r8 8015a8a: 9a0a ldr r2, [sp, #40] @ 0x28 8015a8c: 4648 mov r0, r9 8015a8e: f000 fe69 bl 8016764 <__pow5mult> 8015a92: 9003 str r0, [sp, #12] 8015a94: 2101 movs r1, #1 8015a96: 4648 mov r0, r9 8015a98: f000 fdac bl 80165f4 <__i2b> 8015a9c: 9b0e ldr r3, [sp, #56] @ 0x38 8015a9e: 4604 mov r4, r0 8015aa0: 2b00 cmp r3, #0 8015aa2: f000 81d8 beq.w 8015e56 <_dtoa_r+0xb5e> 8015aa6: 461a mov r2, r3 8015aa8: 4601 mov r1, r0 8015aaa: 4648 mov r0, r9 8015aac: f000 fe5a bl 8016764 <__pow5mult> 8015ab0: 9b20 ldr r3, [sp, #128] @ 0x80 8015ab2: 4604 mov r4, r0 8015ab4: 2b01 cmp r3, #1 8015ab6: f300 809f bgt.w 8015bf8 <_dtoa_r+0x900> 8015aba: 9b06 ldr r3, [sp, #24] 8015abc: 2b00 cmp r3, #0 8015abe: f040 8097 bne.w 8015bf0 <_dtoa_r+0x8f8> 8015ac2: 9b07 ldr r3, [sp, #28] 8015ac4: f3c3 0313 ubfx r3, r3, #0, #20 8015ac8: 2b00 cmp r3, #0 8015aca: f040 8093 bne.w 8015bf4 <_dtoa_r+0x8fc> 8015ace: 9b07 ldr r3, [sp, #28] 8015ad0: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8015ad4: 0d1b lsrs r3, r3, #20 8015ad6: 051b lsls r3, r3, #20 8015ad8: b133 cbz r3, 8015ae8 <_dtoa_r+0x7f0> 8015ada: 9b04 ldr r3, [sp, #16] 8015adc: 3301 adds r3, #1 8015ade: 9304 str r3, [sp, #16] 8015ae0: 9b09 ldr r3, [sp, #36] @ 0x24 8015ae2: 3301 adds r3, #1 8015ae4: 9309 str r3, [sp, #36] @ 0x24 8015ae6: 2301 movs r3, #1 8015ae8: 930a str r3, [sp, #40] @ 0x28 8015aea: 9b0e ldr r3, [sp, #56] @ 0x38 8015aec: 2b00 cmp r3, #0 8015aee: f000 81b8 beq.w 8015e62 <_dtoa_r+0xb6a> 8015af2: 6923 ldr r3, [r4, #16] 8015af4: eb04 0383 add.w r3, r4, r3, lsl #2 8015af8: 6918 ldr r0, [r3, #16] 8015afa: f000 fd2f bl 801655c <__hi0bits> 8015afe: f1c0 0020 rsb r0, r0, #32 8015b02: 9b09 ldr r3, [sp, #36] @ 0x24 8015b04: 4418 add r0, r3 8015b06: f010 001f ands.w r0, r0, #31 8015b0a: f000 8082 beq.w 8015c12 <_dtoa_r+0x91a> 8015b0e: f1c0 0320 rsb r3, r0, #32 8015b12: 2b04 cmp r3, #4 8015b14: dd73 ble.n 8015bfe <_dtoa_r+0x906> 8015b16: 9b04 ldr r3, [sp, #16] 8015b18: f1c0 001c rsb r0, r0, #28 8015b1c: 4403 add r3, r0 8015b1e: 9304 str r3, [sp, #16] 8015b20: 9b09 ldr r3, [sp, #36] @ 0x24 8015b22: 4406 add r6, r0 8015b24: 4403 add r3, r0 8015b26: 9309 str r3, [sp, #36] @ 0x24 8015b28: 9b04 ldr r3, [sp, #16] 8015b2a: 2b00 cmp r3, #0 8015b2c: dd05 ble.n 8015b3a <_dtoa_r+0x842> 8015b2e: 461a mov r2, r3 8015b30: 4648 mov r0, r9 8015b32: 9903 ldr r1, [sp, #12] 8015b34: f000 fe70 bl 8016818 <__lshift> 8015b38: 9003 str r0, [sp, #12] 8015b3a: 9b09 ldr r3, [sp, #36] @ 0x24 8015b3c: 2b00 cmp r3, #0 8015b3e: dd05 ble.n 8015b4c <_dtoa_r+0x854> 8015b40: 4621 mov r1, r4 8015b42: 461a mov r2, r3 8015b44: 4648 mov r0, r9 8015b46: f000 fe67 bl 8016818 <__lshift> 8015b4a: 4604 mov r4, r0 8015b4c: 9b0f ldr r3, [sp, #60] @ 0x3c 8015b4e: 2b00 cmp r3, #0 8015b50: d061 beq.n 8015c16 <_dtoa_r+0x91e> 8015b52: 4621 mov r1, r4 8015b54: 9803 ldr r0, [sp, #12] 8015b56: f000 fecb bl 80168f0 <__mcmp> 8015b5a: 2800 cmp r0, #0 8015b5c: da5b bge.n 8015c16 <_dtoa_r+0x91e> 8015b5e: 2300 movs r3, #0 8015b60: 220a movs r2, #10 8015b62: 4648 mov r0, r9 8015b64: 9903 ldr r1, [sp, #12] 8015b66: f000 fcb3 bl 80164d0 <__multadd> 8015b6a: 9b0b ldr r3, [sp, #44] @ 0x2c 8015b6c: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 8015b70: 9003 str r0, [sp, #12] 8015b72: 2b00 cmp r3, #0 8015b74: f000 8177 beq.w 8015e66 <_dtoa_r+0xb6e> 8015b78: 4629 mov r1, r5 8015b7a: 2300 movs r3, #0 8015b7c: 220a movs r2, #10 8015b7e: 4648 mov r0, r9 8015b80: f000 fca6 bl 80164d0 <__multadd> 8015b84: f1bb 0f00 cmp.w fp, #0 8015b88: 4605 mov r5, r0 8015b8a: dc6f bgt.n 8015c6c <_dtoa_r+0x974> 8015b8c: 9b20 ldr r3, [sp, #128] @ 0x80 8015b8e: 2b02 cmp r3, #2 8015b90: dc49 bgt.n 8015c26 <_dtoa_r+0x92e> 8015b92: e06b b.n 8015c6c <_dtoa_r+0x974> 8015b94: 9b14 ldr r3, [sp, #80] @ 0x50 8015b96: f1c3 0336 rsb r3, r3, #54 @ 0x36 8015b9a: e73c b.n 8015a16 <_dtoa_r+0x71e> 8015b9c: 3fe00000 .word 0x3fe00000 8015ba0: 40240000 .word 0x40240000 8015ba4: 9b08 ldr r3, [sp, #32] 8015ba6: 1e5c subs r4, r3, #1 8015ba8: 9b0a ldr r3, [sp, #40] @ 0x28 8015baa: 42a3 cmp r3, r4 8015bac: db09 blt.n 8015bc2 <_dtoa_r+0x8ca> 8015bae: 1b1c subs r4, r3, r4 8015bb0: 9b08 ldr r3, [sp, #32] 8015bb2: 2b00 cmp r3, #0 8015bb4: f6bf af30 bge.w 8015a18 <_dtoa_r+0x720> 8015bb8: 9b04 ldr r3, [sp, #16] 8015bba: 9a08 ldr r2, [sp, #32] 8015bbc: 1a9e subs r6, r3, r2 8015bbe: 2300 movs r3, #0 8015bc0: e72b b.n 8015a1a <_dtoa_r+0x722> 8015bc2: 9b0a ldr r3, [sp, #40] @ 0x28 8015bc4: 9a0e ldr r2, [sp, #56] @ 0x38 8015bc6: 1ae3 subs r3, r4, r3 8015bc8: 441a add r2, r3 8015bca: 940a str r4, [sp, #40] @ 0x28 8015bcc: 9e04 ldr r6, [sp, #16] 8015bce: 2400 movs r4, #0 8015bd0: 9b08 ldr r3, [sp, #32] 8015bd2: 920e str r2, [sp, #56] @ 0x38 8015bd4: e721 b.n 8015a1a <_dtoa_r+0x722> 8015bd6: 9c0a ldr r4, [sp, #40] @ 0x28 8015bd8: 9e04 ldr r6, [sp, #16] 8015bda: 9d0b ldr r5, [sp, #44] @ 0x2c 8015bdc: e728 b.n 8015a30 <_dtoa_r+0x738> 8015bde: f8dd 800c ldr.w r8, [sp, #12] 8015be2: e751 b.n 8015a88 <_dtoa_r+0x790> 8015be4: 9a0a ldr r2, [sp, #40] @ 0x28 8015be6: 9903 ldr r1, [sp, #12] 8015be8: e750 b.n 8015a8c <_dtoa_r+0x794> 8015bea: f8cd 800c str.w r8, [sp, #12] 8015bee: e751 b.n 8015a94 <_dtoa_r+0x79c> 8015bf0: 2300 movs r3, #0 8015bf2: e779 b.n 8015ae8 <_dtoa_r+0x7f0> 8015bf4: 9b06 ldr r3, [sp, #24] 8015bf6: e777 b.n 8015ae8 <_dtoa_r+0x7f0> 8015bf8: 2300 movs r3, #0 8015bfa: 930a str r3, [sp, #40] @ 0x28 8015bfc: e779 b.n 8015af2 <_dtoa_r+0x7fa> 8015bfe: d093 beq.n 8015b28 <_dtoa_r+0x830> 8015c00: 9a04 ldr r2, [sp, #16] 8015c02: 331c adds r3, #28 8015c04: 441a add r2, r3 8015c06: 9204 str r2, [sp, #16] 8015c08: 9a09 ldr r2, [sp, #36] @ 0x24 8015c0a: 441e add r6, r3 8015c0c: 441a add r2, r3 8015c0e: 9209 str r2, [sp, #36] @ 0x24 8015c10: e78a b.n 8015b28 <_dtoa_r+0x830> 8015c12: 4603 mov r3, r0 8015c14: e7f4 b.n 8015c00 <_dtoa_r+0x908> 8015c16: 9b08 ldr r3, [sp, #32] 8015c18: 46b8 mov r8, r7 8015c1a: 2b00 cmp r3, #0 8015c1c: dc20 bgt.n 8015c60 <_dtoa_r+0x968> 8015c1e: 469b mov fp, r3 8015c20: 9b20 ldr r3, [sp, #128] @ 0x80 8015c22: 2b02 cmp r3, #2 8015c24: dd1e ble.n 8015c64 <_dtoa_r+0x96c> 8015c26: f1bb 0f00 cmp.w fp, #0 8015c2a: f47f adb1 bne.w 8015790 <_dtoa_r+0x498> 8015c2e: 4621 mov r1, r4 8015c30: 465b mov r3, fp 8015c32: 2205 movs r2, #5 8015c34: 4648 mov r0, r9 8015c36: f000 fc4b bl 80164d0 <__multadd> 8015c3a: 4601 mov r1, r0 8015c3c: 4604 mov r4, r0 8015c3e: 9803 ldr r0, [sp, #12] 8015c40: f000 fe56 bl 80168f0 <__mcmp> 8015c44: 2800 cmp r0, #0 8015c46: f77f ada3 ble.w 8015790 <_dtoa_r+0x498> 8015c4a: 4656 mov r6, sl 8015c4c: 2331 movs r3, #49 @ 0x31 8015c4e: f108 0801 add.w r8, r8, #1 8015c52: f806 3b01 strb.w r3, [r6], #1 8015c56: e59f b.n 8015798 <_dtoa_r+0x4a0> 8015c58: 46b8 mov r8, r7 8015c5a: 9c08 ldr r4, [sp, #32] 8015c5c: 4625 mov r5, r4 8015c5e: e7f4 b.n 8015c4a <_dtoa_r+0x952> 8015c60: f8dd b020 ldr.w fp, [sp, #32] 8015c64: 9b0b ldr r3, [sp, #44] @ 0x2c 8015c66: 2b00 cmp r3, #0 8015c68: f000 8101 beq.w 8015e6e <_dtoa_r+0xb76> 8015c6c: 2e00 cmp r6, #0 8015c6e: dd05 ble.n 8015c7c <_dtoa_r+0x984> 8015c70: 4629 mov r1, r5 8015c72: 4632 mov r2, r6 8015c74: 4648 mov r0, r9 8015c76: f000 fdcf bl 8016818 <__lshift> 8015c7a: 4605 mov r5, r0 8015c7c: 9b0a ldr r3, [sp, #40] @ 0x28 8015c7e: 2b00 cmp r3, #0 8015c80: d05c beq.n 8015d3c <_dtoa_r+0xa44> 8015c82: 4648 mov r0, r9 8015c84: 6869 ldr r1, [r5, #4] 8015c86: f000 fbc1 bl 801640c <_Balloc> 8015c8a: 4606 mov r6, r0 8015c8c: b928 cbnz r0, 8015c9a <_dtoa_r+0x9a2> 8015c8e: 4602 mov r2, r0 8015c90: f240 21ef movw r1, #751 @ 0x2ef 8015c94: 4b80 ldr r3, [pc, #512] @ (8015e98 <_dtoa_r+0xba0>) 8015c96: f7ff bb43 b.w 8015320 <_dtoa_r+0x28> 8015c9a: 692a ldr r2, [r5, #16] 8015c9c: f105 010c add.w r1, r5, #12 8015ca0: 3202 adds r2, #2 8015ca2: 0092 lsls r2, r2, #2 8015ca4: 300c adds r0, #12 8015ca6: f7ff fa71 bl 801518c 8015caa: 2201 movs r2, #1 8015cac: 4631 mov r1, r6 8015cae: 4648 mov r0, r9 8015cb0: f000 fdb2 bl 8016818 <__lshift> 8015cb4: 462f mov r7, r5 8015cb6: 4605 mov r5, r0 8015cb8: f10a 0301 add.w r3, sl, #1 8015cbc: 9304 str r3, [sp, #16] 8015cbe: eb0a 030b add.w r3, sl, fp 8015cc2: 930a str r3, [sp, #40] @ 0x28 8015cc4: 9b06 ldr r3, [sp, #24] 8015cc6: f003 0301 and.w r3, r3, #1 8015cca: 9309 str r3, [sp, #36] @ 0x24 8015ccc: 9b04 ldr r3, [sp, #16] 8015cce: 4621 mov r1, r4 8015cd0: 9803 ldr r0, [sp, #12] 8015cd2: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff 8015cd6: f7ff fa85 bl 80151e4 8015cda: 4603 mov r3, r0 8015cdc: 4639 mov r1, r7 8015cde: 3330 adds r3, #48 @ 0x30 8015ce0: 9006 str r0, [sp, #24] 8015ce2: 9803 ldr r0, [sp, #12] 8015ce4: 930b str r3, [sp, #44] @ 0x2c 8015ce6: f000 fe03 bl 80168f0 <__mcmp> 8015cea: 462a mov r2, r5 8015cec: 9008 str r0, [sp, #32] 8015cee: 4621 mov r1, r4 8015cf0: 4648 mov r0, r9 8015cf2: f000 fe19 bl 8016928 <__mdiff> 8015cf6: 68c2 ldr r2, [r0, #12] 8015cf8: 4606 mov r6, r0 8015cfa: 9b0b ldr r3, [sp, #44] @ 0x2c 8015cfc: bb02 cbnz r2, 8015d40 <_dtoa_r+0xa48> 8015cfe: 4601 mov r1, r0 8015d00: 9803 ldr r0, [sp, #12] 8015d02: f000 fdf5 bl 80168f0 <__mcmp> 8015d06: 4602 mov r2, r0 8015d08: 9b0b ldr r3, [sp, #44] @ 0x2c 8015d0a: 4631 mov r1, r6 8015d0c: 4648 mov r0, r9 8015d0e: e9cd 320b strd r3, r2, [sp, #44] @ 0x2c 8015d12: f000 fbbb bl 801648c <_Bfree> 8015d16: 9b20 ldr r3, [sp, #128] @ 0x80 8015d18: 9a0c ldr r2, [sp, #48] @ 0x30 8015d1a: 9e04 ldr r6, [sp, #16] 8015d1c: ea42 0103 orr.w r1, r2, r3 8015d20: 9b09 ldr r3, [sp, #36] @ 0x24 8015d22: 4319 orrs r1, r3 8015d24: 9b0b ldr r3, [sp, #44] @ 0x2c 8015d26: d10d bne.n 8015d44 <_dtoa_r+0xa4c> 8015d28: 2b39 cmp r3, #57 @ 0x39 8015d2a: d027 beq.n 8015d7c <_dtoa_r+0xa84> 8015d2c: 9a08 ldr r2, [sp, #32] 8015d2e: 2a00 cmp r2, #0 8015d30: dd01 ble.n 8015d36 <_dtoa_r+0xa3e> 8015d32: 9b06 ldr r3, [sp, #24] 8015d34: 3331 adds r3, #49 @ 0x31 8015d36: f88b 3000 strb.w r3, [fp] 8015d3a: e52e b.n 801579a <_dtoa_r+0x4a2> 8015d3c: 4628 mov r0, r5 8015d3e: e7b9 b.n 8015cb4 <_dtoa_r+0x9bc> 8015d40: 2201 movs r2, #1 8015d42: e7e2 b.n 8015d0a <_dtoa_r+0xa12> 8015d44: 9908 ldr r1, [sp, #32] 8015d46: 2900 cmp r1, #0 8015d48: db04 blt.n 8015d54 <_dtoa_r+0xa5c> 8015d4a: 9820 ldr r0, [sp, #128] @ 0x80 8015d4c: 4301 orrs r1, r0 8015d4e: 9809 ldr r0, [sp, #36] @ 0x24 8015d50: 4301 orrs r1, r0 8015d52: d120 bne.n 8015d96 <_dtoa_r+0xa9e> 8015d54: 2a00 cmp r2, #0 8015d56: ddee ble.n 8015d36 <_dtoa_r+0xa3e> 8015d58: 2201 movs r2, #1 8015d5a: 9903 ldr r1, [sp, #12] 8015d5c: 4648 mov r0, r9 8015d5e: 9304 str r3, [sp, #16] 8015d60: f000 fd5a bl 8016818 <__lshift> 8015d64: 4621 mov r1, r4 8015d66: 9003 str r0, [sp, #12] 8015d68: f000 fdc2 bl 80168f0 <__mcmp> 8015d6c: 2800 cmp r0, #0 8015d6e: 9b04 ldr r3, [sp, #16] 8015d70: dc02 bgt.n 8015d78 <_dtoa_r+0xa80> 8015d72: d1e0 bne.n 8015d36 <_dtoa_r+0xa3e> 8015d74: 07da lsls r2, r3, #31 8015d76: d5de bpl.n 8015d36 <_dtoa_r+0xa3e> 8015d78: 2b39 cmp r3, #57 @ 0x39 8015d7a: d1da bne.n 8015d32 <_dtoa_r+0xa3a> 8015d7c: 2339 movs r3, #57 @ 0x39 8015d7e: f88b 3000 strb.w r3, [fp] 8015d82: 4633 mov r3, r6 8015d84: 461e mov r6, r3 8015d86: f816 2c01 ldrb.w r2, [r6, #-1] 8015d8a: 3b01 subs r3, #1 8015d8c: 2a39 cmp r2, #57 @ 0x39 8015d8e: d04e beq.n 8015e2e <_dtoa_r+0xb36> 8015d90: 3201 adds r2, #1 8015d92: 701a strb r2, [r3, #0] 8015d94: e501 b.n 801579a <_dtoa_r+0x4a2> 8015d96: 2a00 cmp r2, #0 8015d98: dd03 ble.n 8015da2 <_dtoa_r+0xaaa> 8015d9a: 2b39 cmp r3, #57 @ 0x39 8015d9c: d0ee beq.n 8015d7c <_dtoa_r+0xa84> 8015d9e: 3301 adds r3, #1 8015da0: e7c9 b.n 8015d36 <_dtoa_r+0xa3e> 8015da2: 9a04 ldr r2, [sp, #16] 8015da4: 990a ldr r1, [sp, #40] @ 0x28 8015da6: f802 3c01 strb.w r3, [r2, #-1] 8015daa: 428a cmp r2, r1 8015dac: d028 beq.n 8015e00 <_dtoa_r+0xb08> 8015dae: 2300 movs r3, #0 8015db0: 220a movs r2, #10 8015db2: 9903 ldr r1, [sp, #12] 8015db4: 4648 mov r0, r9 8015db6: f000 fb8b bl 80164d0 <__multadd> 8015dba: 42af cmp r7, r5 8015dbc: 9003 str r0, [sp, #12] 8015dbe: f04f 0300 mov.w r3, #0 8015dc2: f04f 020a mov.w r2, #10 8015dc6: 4639 mov r1, r7 8015dc8: 4648 mov r0, r9 8015dca: d107 bne.n 8015ddc <_dtoa_r+0xae4> 8015dcc: f000 fb80 bl 80164d0 <__multadd> 8015dd0: 4607 mov r7, r0 8015dd2: 4605 mov r5, r0 8015dd4: 9b04 ldr r3, [sp, #16] 8015dd6: 3301 adds r3, #1 8015dd8: 9304 str r3, [sp, #16] 8015dda: e777 b.n 8015ccc <_dtoa_r+0x9d4> 8015ddc: f000 fb78 bl 80164d0 <__multadd> 8015de0: 4629 mov r1, r5 8015de2: 4607 mov r7, r0 8015de4: 2300 movs r3, #0 8015de6: 220a movs r2, #10 8015de8: 4648 mov r0, r9 8015dea: f000 fb71 bl 80164d0 <__multadd> 8015dee: 4605 mov r5, r0 8015df0: e7f0 b.n 8015dd4 <_dtoa_r+0xadc> 8015df2: f1bb 0f00 cmp.w fp, #0 8015df6: bfcc ite gt 8015df8: 465e movgt r6, fp 8015dfa: 2601 movle r6, #1 8015dfc: 2700 movs r7, #0 8015dfe: 4456 add r6, sl 8015e00: 2201 movs r2, #1 8015e02: 9903 ldr r1, [sp, #12] 8015e04: 4648 mov r0, r9 8015e06: 9304 str r3, [sp, #16] 8015e08: f000 fd06 bl 8016818 <__lshift> 8015e0c: 4621 mov r1, r4 8015e0e: 9003 str r0, [sp, #12] 8015e10: f000 fd6e bl 80168f0 <__mcmp> 8015e14: 2800 cmp r0, #0 8015e16: dcb4 bgt.n 8015d82 <_dtoa_r+0xa8a> 8015e18: d102 bne.n 8015e20 <_dtoa_r+0xb28> 8015e1a: 9b04 ldr r3, [sp, #16] 8015e1c: 07db lsls r3, r3, #31 8015e1e: d4b0 bmi.n 8015d82 <_dtoa_r+0xa8a> 8015e20: 4633 mov r3, r6 8015e22: 461e mov r6, r3 8015e24: f813 2d01 ldrb.w r2, [r3, #-1]! 8015e28: 2a30 cmp r2, #48 @ 0x30 8015e2a: d0fa beq.n 8015e22 <_dtoa_r+0xb2a> 8015e2c: e4b5 b.n 801579a <_dtoa_r+0x4a2> 8015e2e: 459a cmp sl, r3 8015e30: d1a8 bne.n 8015d84 <_dtoa_r+0xa8c> 8015e32: 2331 movs r3, #49 @ 0x31 8015e34: f108 0801 add.w r8, r8, #1 8015e38: f88a 3000 strb.w r3, [sl] 8015e3c: e4ad b.n 801579a <_dtoa_r+0x4a2> 8015e3e: 9b24 ldr r3, [sp, #144] @ 0x90 8015e40: f8df a058 ldr.w sl, [pc, #88] @ 8015e9c <_dtoa_r+0xba4> 8015e44: b11b cbz r3, 8015e4e <_dtoa_r+0xb56> 8015e46: f10a 0308 add.w r3, sl, #8 8015e4a: 9a24 ldr r2, [sp, #144] @ 0x90 8015e4c: 6013 str r3, [r2, #0] 8015e4e: 4650 mov r0, sl 8015e50: b017 add sp, #92 @ 0x5c 8015e52: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8015e56: 9b20 ldr r3, [sp, #128] @ 0x80 8015e58: 2b01 cmp r3, #1 8015e5a: f77f ae2e ble.w 8015aba <_dtoa_r+0x7c2> 8015e5e: 9b0e ldr r3, [sp, #56] @ 0x38 8015e60: 930a str r3, [sp, #40] @ 0x28 8015e62: 2001 movs r0, #1 8015e64: e64d b.n 8015b02 <_dtoa_r+0x80a> 8015e66: f1bb 0f00 cmp.w fp, #0 8015e6a: f77f aed9 ble.w 8015c20 <_dtoa_r+0x928> 8015e6e: 4656 mov r6, sl 8015e70: 4621 mov r1, r4 8015e72: 9803 ldr r0, [sp, #12] 8015e74: f7ff f9b6 bl 80151e4 8015e78: f100 0330 add.w r3, r0, #48 @ 0x30 8015e7c: f806 3b01 strb.w r3, [r6], #1 8015e80: eba6 020a sub.w r2, r6, sl 8015e84: 4593 cmp fp, r2 8015e86: ddb4 ble.n 8015df2 <_dtoa_r+0xafa> 8015e88: 2300 movs r3, #0 8015e8a: 220a movs r2, #10 8015e8c: 4648 mov r0, r9 8015e8e: 9903 ldr r1, [sp, #12] 8015e90: f000 fb1e bl 80164d0 <__multadd> 8015e94: 9003 str r0, [sp, #12] 8015e96: e7eb b.n 8015e70 <_dtoa_r+0xb78> 8015e98: 08017ea8 .word 0x08017ea8 8015e9c: 08017e2c .word 0x08017e2c 08015ea0 <__ssputs_r>: 8015ea0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8015ea4: 461f mov r7, r3 8015ea6: 688e ldr r6, [r1, #8] 8015ea8: 4682 mov sl, r0 8015eaa: 42be cmp r6, r7 8015eac: 460c mov r4, r1 8015eae: 4690 mov r8, r2 8015eb0: 680b ldr r3, [r1, #0] 8015eb2: d82d bhi.n 8015f10 <__ssputs_r+0x70> 8015eb4: f9b1 200c ldrsh.w r2, [r1, #12] 8015eb8: f412 6f90 tst.w r2, #1152 @ 0x480 8015ebc: d026 beq.n 8015f0c <__ssputs_r+0x6c> 8015ebe: 6965 ldr r5, [r4, #20] 8015ec0: 6909 ldr r1, [r1, #16] 8015ec2: eb05 0545 add.w r5, r5, r5, lsl #1 8015ec6: eba3 0901 sub.w r9, r3, r1 8015eca: eb05 75d5 add.w r5, r5, r5, lsr #31 8015ece: 1c7b adds r3, r7, #1 8015ed0: 444b add r3, r9 8015ed2: 106d asrs r5, r5, #1 8015ed4: 429d cmp r5, r3 8015ed6: bf38 it cc 8015ed8: 461d movcc r5, r3 8015eda: 0553 lsls r3, r2, #21 8015edc: d527 bpl.n 8015f2e <__ssputs_r+0x8e> 8015ede: 4629 mov r1, r5 8015ee0: f000 f960 bl 80161a4 <_malloc_r> 8015ee4: 4606 mov r6, r0 8015ee6: b360 cbz r0, 8015f42 <__ssputs_r+0xa2> 8015ee8: 464a mov r2, r9 8015eea: 6921 ldr r1, [r4, #16] 8015eec: f7ff f94e bl 801518c 8015ef0: 89a3 ldrh r3, [r4, #12] 8015ef2: f423 6390 bic.w r3, r3, #1152 @ 0x480 8015ef6: f043 0380 orr.w r3, r3, #128 @ 0x80 8015efa: 81a3 strh r3, [r4, #12] 8015efc: 6126 str r6, [r4, #16] 8015efe: 444e add r6, r9 8015f00: 6026 str r6, [r4, #0] 8015f02: 463e mov r6, r7 8015f04: 6165 str r5, [r4, #20] 8015f06: eba5 0509 sub.w r5, r5, r9 8015f0a: 60a5 str r5, [r4, #8] 8015f0c: 42be cmp r6, r7 8015f0e: d900 bls.n 8015f12 <__ssputs_r+0x72> 8015f10: 463e mov r6, r7 8015f12: 4632 mov r2, r6 8015f14: 4641 mov r1, r8 8015f16: 6820 ldr r0, [r4, #0] 8015f18: f000 fe76 bl 8016c08 8015f1c: 2000 movs r0, #0 8015f1e: 68a3 ldr r3, [r4, #8] 8015f20: 1b9b subs r3, r3, r6 8015f22: 60a3 str r3, [r4, #8] 8015f24: 6823 ldr r3, [r4, #0] 8015f26: 4433 add r3, r6 8015f28: 6023 str r3, [r4, #0] 8015f2a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8015f2e: 462a mov r2, r5 8015f30: f000 fe3c bl 8016bac <_realloc_r> 8015f34: 4606 mov r6, r0 8015f36: 2800 cmp r0, #0 8015f38: d1e0 bne.n 8015efc <__ssputs_r+0x5c> 8015f3a: 4650 mov r0, sl 8015f3c: 6921 ldr r1, [r4, #16] 8015f3e: f000 feef bl 8016d20 <_free_r> 8015f42: 230c movs r3, #12 8015f44: f8ca 3000 str.w r3, [sl] 8015f48: 89a3 ldrh r3, [r4, #12] 8015f4a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015f4e: f043 0340 orr.w r3, r3, #64 @ 0x40 8015f52: 81a3 strh r3, [r4, #12] 8015f54: e7e9 b.n 8015f2a <__ssputs_r+0x8a> ... 08015f58 <_svfiprintf_r>: 8015f58: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8015f5c: 4698 mov r8, r3 8015f5e: 898b ldrh r3, [r1, #12] 8015f60: 4607 mov r7, r0 8015f62: 061b lsls r3, r3, #24 8015f64: 460d mov r5, r1 8015f66: 4614 mov r4, r2 8015f68: b09d sub sp, #116 @ 0x74 8015f6a: d510 bpl.n 8015f8e <_svfiprintf_r+0x36> 8015f6c: 690b ldr r3, [r1, #16] 8015f6e: b973 cbnz r3, 8015f8e <_svfiprintf_r+0x36> 8015f70: 2140 movs r1, #64 @ 0x40 8015f72: f000 f917 bl 80161a4 <_malloc_r> 8015f76: 6028 str r0, [r5, #0] 8015f78: 6128 str r0, [r5, #16] 8015f7a: b930 cbnz r0, 8015f8a <_svfiprintf_r+0x32> 8015f7c: 230c movs r3, #12 8015f7e: 603b str r3, [r7, #0] 8015f80: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015f84: b01d add sp, #116 @ 0x74 8015f86: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8015f8a: 2340 movs r3, #64 @ 0x40 8015f8c: 616b str r3, [r5, #20] 8015f8e: 2300 movs r3, #0 8015f90: 9309 str r3, [sp, #36] @ 0x24 8015f92: 2320 movs r3, #32 8015f94: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8015f98: 2330 movs r3, #48 @ 0x30 8015f9a: f04f 0901 mov.w r9, #1 8015f9e: f8cd 800c str.w r8, [sp, #12] 8015fa2: f8df 8198 ldr.w r8, [pc, #408] @ 801613c <_svfiprintf_r+0x1e4> 8015fa6: f88d 302a strb.w r3, [sp, #42] @ 0x2a 8015faa: 4623 mov r3, r4 8015fac: 469a mov sl, r3 8015fae: f813 2b01 ldrb.w r2, [r3], #1 8015fb2: b10a cbz r2, 8015fb8 <_svfiprintf_r+0x60> 8015fb4: 2a25 cmp r2, #37 @ 0x25 8015fb6: d1f9 bne.n 8015fac <_svfiprintf_r+0x54> 8015fb8: ebba 0b04 subs.w fp, sl, r4 8015fbc: d00b beq.n 8015fd6 <_svfiprintf_r+0x7e> 8015fbe: 465b mov r3, fp 8015fc0: 4622 mov r2, r4 8015fc2: 4629 mov r1, r5 8015fc4: 4638 mov r0, r7 8015fc6: f7ff ff6b bl 8015ea0 <__ssputs_r> 8015fca: 3001 adds r0, #1 8015fcc: f000 80a7 beq.w 801611e <_svfiprintf_r+0x1c6> 8015fd0: 9a09 ldr r2, [sp, #36] @ 0x24 8015fd2: 445a add r2, fp 8015fd4: 9209 str r2, [sp, #36] @ 0x24 8015fd6: f89a 3000 ldrb.w r3, [sl] 8015fda: 2b00 cmp r3, #0 8015fdc: f000 809f beq.w 801611e <_svfiprintf_r+0x1c6> 8015fe0: 2300 movs r3, #0 8015fe2: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8015fe6: e9cd 2305 strd r2, r3, [sp, #20] 8015fea: f10a 0a01 add.w sl, sl, #1 8015fee: 9304 str r3, [sp, #16] 8015ff0: 9307 str r3, [sp, #28] 8015ff2: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8015ff6: 931a str r3, [sp, #104] @ 0x68 8015ff8: 4654 mov r4, sl 8015ffa: 2205 movs r2, #5 8015ffc: f814 1b01 ldrb.w r1, [r4], #1 8016000: 484e ldr r0, [pc, #312] @ (801613c <_svfiprintf_r+0x1e4>) 8016002: f7ff f8b5 bl 8015170 8016006: 9a04 ldr r2, [sp, #16] 8016008: b9d8 cbnz r0, 8016042 <_svfiprintf_r+0xea> 801600a: 06d0 lsls r0, r2, #27 801600c: bf44 itt mi 801600e: 2320 movmi r3, #32 8016010: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8016014: 0711 lsls r1, r2, #28 8016016: bf44 itt mi 8016018: 232b movmi r3, #43 @ 0x2b 801601a: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 801601e: f89a 3000 ldrb.w r3, [sl] 8016022: 2b2a cmp r3, #42 @ 0x2a 8016024: d015 beq.n 8016052 <_svfiprintf_r+0xfa> 8016026: 4654 mov r4, sl 8016028: 2000 movs r0, #0 801602a: f04f 0c0a mov.w ip, #10 801602e: 9a07 ldr r2, [sp, #28] 8016030: 4621 mov r1, r4 8016032: f811 3b01 ldrb.w r3, [r1], #1 8016036: 3b30 subs r3, #48 @ 0x30 8016038: 2b09 cmp r3, #9 801603a: d94b bls.n 80160d4 <_svfiprintf_r+0x17c> 801603c: b1b0 cbz r0, 801606c <_svfiprintf_r+0x114> 801603e: 9207 str r2, [sp, #28] 8016040: e014 b.n 801606c <_svfiprintf_r+0x114> 8016042: eba0 0308 sub.w r3, r0, r8 8016046: fa09 f303 lsl.w r3, r9, r3 801604a: 4313 orrs r3, r2 801604c: 46a2 mov sl, r4 801604e: 9304 str r3, [sp, #16] 8016050: e7d2 b.n 8015ff8 <_svfiprintf_r+0xa0> 8016052: 9b03 ldr r3, [sp, #12] 8016054: 1d19 adds r1, r3, #4 8016056: 681b ldr r3, [r3, #0] 8016058: 9103 str r1, [sp, #12] 801605a: 2b00 cmp r3, #0 801605c: bfbb ittet lt 801605e: 425b neglt r3, r3 8016060: f042 0202 orrlt.w r2, r2, #2 8016064: 9307 strge r3, [sp, #28] 8016066: 9307 strlt r3, [sp, #28] 8016068: bfb8 it lt 801606a: 9204 strlt r2, [sp, #16] 801606c: 7823 ldrb r3, [r4, #0] 801606e: 2b2e cmp r3, #46 @ 0x2e 8016070: d10a bne.n 8016088 <_svfiprintf_r+0x130> 8016072: 7863 ldrb r3, [r4, #1] 8016074: 2b2a cmp r3, #42 @ 0x2a 8016076: d132 bne.n 80160de <_svfiprintf_r+0x186> 8016078: 9b03 ldr r3, [sp, #12] 801607a: 3402 adds r4, #2 801607c: 1d1a adds r2, r3, #4 801607e: 681b ldr r3, [r3, #0] 8016080: 9203 str r2, [sp, #12] 8016082: ea43 73e3 orr.w r3, r3, r3, asr #31 8016086: 9305 str r3, [sp, #20] 8016088: f8df a0b4 ldr.w sl, [pc, #180] @ 8016140 <_svfiprintf_r+0x1e8> 801608c: 2203 movs r2, #3 801608e: 4650 mov r0, sl 8016090: 7821 ldrb r1, [r4, #0] 8016092: f7ff f86d bl 8015170 8016096: b138 cbz r0, 80160a8 <_svfiprintf_r+0x150> 8016098: 2240 movs r2, #64 @ 0x40 801609a: 9b04 ldr r3, [sp, #16] 801609c: eba0 000a sub.w r0, r0, sl 80160a0: 4082 lsls r2, r0 80160a2: 4313 orrs r3, r2 80160a4: 3401 adds r4, #1 80160a6: 9304 str r3, [sp, #16] 80160a8: f814 1b01 ldrb.w r1, [r4], #1 80160ac: 2206 movs r2, #6 80160ae: 4825 ldr r0, [pc, #148] @ (8016144 <_svfiprintf_r+0x1ec>) 80160b0: f88d 1028 strb.w r1, [sp, #40] @ 0x28 80160b4: f7ff f85c bl 8015170 80160b8: 2800 cmp r0, #0 80160ba: d036 beq.n 801612a <_svfiprintf_r+0x1d2> 80160bc: 4b22 ldr r3, [pc, #136] @ (8016148 <_svfiprintf_r+0x1f0>) 80160be: bb1b cbnz r3, 8016108 <_svfiprintf_r+0x1b0> 80160c0: 9b03 ldr r3, [sp, #12] 80160c2: 3307 adds r3, #7 80160c4: f023 0307 bic.w r3, r3, #7 80160c8: 3308 adds r3, #8 80160ca: 9303 str r3, [sp, #12] 80160cc: 9b09 ldr r3, [sp, #36] @ 0x24 80160ce: 4433 add r3, r6 80160d0: 9309 str r3, [sp, #36] @ 0x24 80160d2: e76a b.n 8015faa <_svfiprintf_r+0x52> 80160d4: 460c mov r4, r1 80160d6: 2001 movs r0, #1 80160d8: fb0c 3202 mla r2, ip, r2, r3 80160dc: e7a8 b.n 8016030 <_svfiprintf_r+0xd8> 80160de: 2300 movs r3, #0 80160e0: f04f 0c0a mov.w ip, #10 80160e4: 4619 mov r1, r3 80160e6: 3401 adds r4, #1 80160e8: 9305 str r3, [sp, #20] 80160ea: 4620 mov r0, r4 80160ec: f810 2b01 ldrb.w r2, [r0], #1 80160f0: 3a30 subs r2, #48 @ 0x30 80160f2: 2a09 cmp r2, #9 80160f4: d903 bls.n 80160fe <_svfiprintf_r+0x1a6> 80160f6: 2b00 cmp r3, #0 80160f8: d0c6 beq.n 8016088 <_svfiprintf_r+0x130> 80160fa: 9105 str r1, [sp, #20] 80160fc: e7c4 b.n 8016088 <_svfiprintf_r+0x130> 80160fe: 4604 mov r4, r0 8016100: 2301 movs r3, #1 8016102: fb0c 2101 mla r1, ip, r1, r2 8016106: e7f0 b.n 80160ea <_svfiprintf_r+0x192> 8016108: ab03 add r3, sp, #12 801610a: 9300 str r3, [sp, #0] 801610c: 462a mov r2, r5 801610e: 4638 mov r0, r7 8016110: 4b0e ldr r3, [pc, #56] @ (801614c <_svfiprintf_r+0x1f4>) 8016112: a904 add r1, sp, #16 8016114: f7fe fb38 bl 8014788 <_printf_float> 8016118: 1c42 adds r2, r0, #1 801611a: 4606 mov r6, r0 801611c: d1d6 bne.n 80160cc <_svfiprintf_r+0x174> 801611e: 89ab ldrh r3, [r5, #12] 8016120: 065b lsls r3, r3, #25 8016122: f53f af2d bmi.w 8015f80 <_svfiprintf_r+0x28> 8016126: 9809 ldr r0, [sp, #36] @ 0x24 8016128: e72c b.n 8015f84 <_svfiprintf_r+0x2c> 801612a: ab03 add r3, sp, #12 801612c: 9300 str r3, [sp, #0] 801612e: 462a mov r2, r5 8016130: 4638 mov r0, r7 8016132: 4b06 ldr r3, [pc, #24] @ (801614c <_svfiprintf_r+0x1f4>) 8016134: a904 add r1, sp, #16 8016136: f7fe fdc5 bl 8014cc4 <_printf_i> 801613a: e7ed b.n 8016118 <_svfiprintf_r+0x1c0> 801613c: 08017eb9 .word 0x08017eb9 8016140: 08017ebf .word 0x08017ebf 8016144: 08017ec3 .word 0x08017ec3 8016148: 08014789 .word 0x08014789 801614c: 08015ea1 .word 0x08015ea1 08016150 : 8016150: 4b02 ldr r3, [pc, #8] @ (801615c ) 8016152: 4601 mov r1, r0 8016154: 6818 ldr r0, [r3, #0] 8016156: f000 b825 b.w 80161a4 <_malloc_r> 801615a: bf00 nop 801615c: 2000009c .word 0x2000009c 08016160 : 8016160: b570 push {r4, r5, r6, lr} 8016162: 4e0f ldr r6, [pc, #60] @ (80161a0 ) 8016164: 460c mov r4, r1 8016166: 6831 ldr r1, [r6, #0] 8016168: 4605 mov r5, r0 801616a: b911 cbnz r1, 8016172 801616c: f000 fd8a bl 8016c84 <_sbrk_r> 8016170: 6030 str r0, [r6, #0] 8016172: 4621 mov r1, r4 8016174: 4628 mov r0, r5 8016176: f000 fd85 bl 8016c84 <_sbrk_r> 801617a: 1c43 adds r3, r0, #1 801617c: d103 bne.n 8016186 801617e: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 8016182: 4620 mov r0, r4 8016184: bd70 pop {r4, r5, r6, pc} 8016186: 1cc4 adds r4, r0, #3 8016188: f024 0403 bic.w r4, r4, #3 801618c: 42a0 cmp r0, r4 801618e: d0f8 beq.n 8016182 8016190: 1a21 subs r1, r4, r0 8016192: 4628 mov r0, r5 8016194: f000 fd76 bl 8016c84 <_sbrk_r> 8016198: 3001 adds r0, #1 801619a: d1f2 bne.n 8016182 801619c: e7ef b.n 801617e 801619e: bf00 nop 80161a0: 200015e0 .word 0x200015e0 080161a4 <_malloc_r>: 80161a4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 80161a8: 1ccd adds r5, r1, #3 80161aa: f025 0503 bic.w r5, r5, #3 80161ae: 3508 adds r5, #8 80161b0: 2d0c cmp r5, #12 80161b2: bf38 it cc 80161b4: 250c movcc r5, #12 80161b6: 2d00 cmp r5, #0 80161b8: 4606 mov r6, r0 80161ba: db01 blt.n 80161c0 <_malloc_r+0x1c> 80161bc: 42a9 cmp r1, r5 80161be: d904 bls.n 80161ca <_malloc_r+0x26> 80161c0: 230c movs r3, #12 80161c2: 6033 str r3, [r6, #0] 80161c4: 2000 movs r0, #0 80161c6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 80161ca: f8df 80d4 ldr.w r8, [pc, #212] @ 80162a0 <_malloc_r+0xfc> 80161ce: f000 f911 bl 80163f4 <__malloc_lock> 80161d2: f8d8 3000 ldr.w r3, [r8] 80161d6: 461c mov r4, r3 80161d8: bb44 cbnz r4, 801622c <_malloc_r+0x88> 80161da: 4629 mov r1, r5 80161dc: 4630 mov r0, r6 80161de: f7ff ffbf bl 8016160 80161e2: 1c43 adds r3, r0, #1 80161e4: 4604 mov r4, r0 80161e6: d158 bne.n 801629a <_malloc_r+0xf6> 80161e8: f8d8 4000 ldr.w r4, [r8] 80161ec: 4627 mov r7, r4 80161ee: 2f00 cmp r7, #0 80161f0: d143 bne.n 801627a <_malloc_r+0xd6> 80161f2: 2c00 cmp r4, #0 80161f4: d04b beq.n 801628e <_malloc_r+0xea> 80161f6: 6823 ldr r3, [r4, #0] 80161f8: 4639 mov r1, r7 80161fa: 4630 mov r0, r6 80161fc: eb04 0903 add.w r9, r4, r3 8016200: f000 fd40 bl 8016c84 <_sbrk_r> 8016204: 4581 cmp r9, r0 8016206: d142 bne.n 801628e <_malloc_r+0xea> 8016208: 6821 ldr r1, [r4, #0] 801620a: 4630 mov r0, r6 801620c: 1a6d subs r5, r5, r1 801620e: 4629 mov r1, r5 8016210: f7ff ffa6 bl 8016160 8016214: 3001 adds r0, #1 8016216: d03a beq.n 801628e <_malloc_r+0xea> 8016218: 6823 ldr r3, [r4, #0] 801621a: 442b add r3, r5 801621c: 6023 str r3, [r4, #0] 801621e: f8d8 3000 ldr.w r3, [r8] 8016222: 685a ldr r2, [r3, #4] 8016224: bb62 cbnz r2, 8016280 <_malloc_r+0xdc> 8016226: f8c8 7000 str.w r7, [r8] 801622a: e00f b.n 801624c <_malloc_r+0xa8> 801622c: 6822 ldr r2, [r4, #0] 801622e: 1b52 subs r2, r2, r5 8016230: d420 bmi.n 8016274 <_malloc_r+0xd0> 8016232: 2a0b cmp r2, #11 8016234: d917 bls.n 8016266 <_malloc_r+0xc2> 8016236: 1961 adds r1, r4, r5 8016238: 42a3 cmp r3, r4 801623a: 6025 str r5, [r4, #0] 801623c: bf18 it ne 801623e: 6059 strne r1, [r3, #4] 8016240: 6863 ldr r3, [r4, #4] 8016242: bf08 it eq 8016244: f8c8 1000 streq.w r1, [r8] 8016248: 5162 str r2, [r4, r5] 801624a: 604b str r3, [r1, #4] 801624c: 4630 mov r0, r6 801624e: f000 f8d7 bl 8016400 <__malloc_unlock> 8016252: f104 000b add.w r0, r4, #11 8016256: 1d23 adds r3, r4, #4 8016258: f020 0007 bic.w r0, r0, #7 801625c: 1ac2 subs r2, r0, r3 801625e: bf1c itt ne 8016260: 1a1b subne r3, r3, r0 8016262: 50a3 strne r3, [r4, r2] 8016264: e7af b.n 80161c6 <_malloc_r+0x22> 8016266: 6862 ldr r2, [r4, #4] 8016268: 42a3 cmp r3, r4 801626a: bf0c ite eq 801626c: f8c8 2000 streq.w r2, [r8] 8016270: 605a strne r2, [r3, #4] 8016272: e7eb b.n 801624c <_malloc_r+0xa8> 8016274: 4623 mov r3, r4 8016276: 6864 ldr r4, [r4, #4] 8016278: e7ae b.n 80161d8 <_malloc_r+0x34> 801627a: 463c mov r4, r7 801627c: 687f ldr r7, [r7, #4] 801627e: e7b6 b.n 80161ee <_malloc_r+0x4a> 8016280: 461a mov r2, r3 8016282: 685b ldr r3, [r3, #4] 8016284: 42a3 cmp r3, r4 8016286: d1fb bne.n 8016280 <_malloc_r+0xdc> 8016288: 2300 movs r3, #0 801628a: 6053 str r3, [r2, #4] 801628c: e7de b.n 801624c <_malloc_r+0xa8> 801628e: 230c movs r3, #12 8016290: 4630 mov r0, r6 8016292: 6033 str r3, [r6, #0] 8016294: f000 f8b4 bl 8016400 <__malloc_unlock> 8016298: e794 b.n 80161c4 <_malloc_r+0x20> 801629a: 6005 str r5, [r0, #0] 801629c: e7d6 b.n 801624c <_malloc_r+0xa8> 801629e: bf00 nop 80162a0: 200015e4 .word 0x200015e4 080162a4 <__sflush_r>: 80162a4: f9b1 200c ldrsh.w r2, [r1, #12] 80162a8: b5f8 push {r3, r4, r5, r6, r7, lr} 80162aa: 0716 lsls r6, r2, #28 80162ac: 4605 mov r5, r0 80162ae: 460c mov r4, r1 80162b0: d454 bmi.n 801635c <__sflush_r+0xb8> 80162b2: 684b ldr r3, [r1, #4] 80162b4: 2b00 cmp r3, #0 80162b6: dc02 bgt.n 80162be <__sflush_r+0x1a> 80162b8: 6c0b ldr r3, [r1, #64] @ 0x40 80162ba: 2b00 cmp r3, #0 80162bc: dd48 ble.n 8016350 <__sflush_r+0xac> 80162be: 6ae6 ldr r6, [r4, #44] @ 0x2c 80162c0: 2e00 cmp r6, #0 80162c2: d045 beq.n 8016350 <__sflush_r+0xac> 80162c4: 2300 movs r3, #0 80162c6: f412 5280 ands.w r2, r2, #4096 @ 0x1000 80162ca: 682f ldr r7, [r5, #0] 80162cc: 6a21 ldr r1, [r4, #32] 80162ce: 602b str r3, [r5, #0] 80162d0: d030 beq.n 8016334 <__sflush_r+0x90> 80162d2: 6d62 ldr r2, [r4, #84] @ 0x54 80162d4: 89a3 ldrh r3, [r4, #12] 80162d6: 0759 lsls r1, r3, #29 80162d8: d505 bpl.n 80162e6 <__sflush_r+0x42> 80162da: 6863 ldr r3, [r4, #4] 80162dc: 1ad2 subs r2, r2, r3 80162de: 6b63 ldr r3, [r4, #52] @ 0x34 80162e0: b10b cbz r3, 80162e6 <__sflush_r+0x42> 80162e2: 6c23 ldr r3, [r4, #64] @ 0x40 80162e4: 1ad2 subs r2, r2, r3 80162e6: 2300 movs r3, #0 80162e8: 4628 mov r0, r5 80162ea: 6ae6 ldr r6, [r4, #44] @ 0x2c 80162ec: 6a21 ldr r1, [r4, #32] 80162ee: 47b0 blx r6 80162f0: 1c43 adds r3, r0, #1 80162f2: 89a3 ldrh r3, [r4, #12] 80162f4: d106 bne.n 8016304 <__sflush_r+0x60> 80162f6: 6829 ldr r1, [r5, #0] 80162f8: 291d cmp r1, #29 80162fa: d82b bhi.n 8016354 <__sflush_r+0xb0> 80162fc: 4a28 ldr r2, [pc, #160] @ (80163a0 <__sflush_r+0xfc>) 80162fe: 40ca lsrs r2, r1 8016300: 07d6 lsls r6, r2, #31 8016302: d527 bpl.n 8016354 <__sflush_r+0xb0> 8016304: 2200 movs r2, #0 8016306: 6062 str r2, [r4, #4] 8016308: 6922 ldr r2, [r4, #16] 801630a: 04d9 lsls r1, r3, #19 801630c: 6022 str r2, [r4, #0] 801630e: d504 bpl.n 801631a <__sflush_r+0x76> 8016310: 1c42 adds r2, r0, #1 8016312: d101 bne.n 8016318 <__sflush_r+0x74> 8016314: 682b ldr r3, [r5, #0] 8016316: b903 cbnz r3, 801631a <__sflush_r+0x76> 8016318: 6560 str r0, [r4, #84] @ 0x54 801631a: 6b61 ldr r1, [r4, #52] @ 0x34 801631c: 602f str r7, [r5, #0] 801631e: b1b9 cbz r1, 8016350 <__sflush_r+0xac> 8016320: f104 0344 add.w r3, r4, #68 @ 0x44 8016324: 4299 cmp r1, r3 8016326: d002 beq.n 801632e <__sflush_r+0x8a> 8016328: 4628 mov r0, r5 801632a: f000 fcf9 bl 8016d20 <_free_r> 801632e: 2300 movs r3, #0 8016330: 6363 str r3, [r4, #52] @ 0x34 8016332: e00d b.n 8016350 <__sflush_r+0xac> 8016334: 2301 movs r3, #1 8016336: 4628 mov r0, r5 8016338: 47b0 blx r6 801633a: 4602 mov r2, r0 801633c: 1c50 adds r0, r2, #1 801633e: d1c9 bne.n 80162d4 <__sflush_r+0x30> 8016340: 682b ldr r3, [r5, #0] 8016342: 2b00 cmp r3, #0 8016344: d0c6 beq.n 80162d4 <__sflush_r+0x30> 8016346: 2b1d cmp r3, #29 8016348: d001 beq.n 801634e <__sflush_r+0xaa> 801634a: 2b16 cmp r3, #22 801634c: d11d bne.n 801638a <__sflush_r+0xe6> 801634e: 602f str r7, [r5, #0] 8016350: 2000 movs r0, #0 8016352: e021 b.n 8016398 <__sflush_r+0xf4> 8016354: f043 0340 orr.w r3, r3, #64 @ 0x40 8016358: b21b sxth r3, r3 801635a: e01a b.n 8016392 <__sflush_r+0xee> 801635c: 690f ldr r7, [r1, #16] 801635e: 2f00 cmp r7, #0 8016360: d0f6 beq.n 8016350 <__sflush_r+0xac> 8016362: 0793 lsls r3, r2, #30 8016364: bf18 it ne 8016366: 2300 movne r3, #0 8016368: 680e ldr r6, [r1, #0] 801636a: bf08 it eq 801636c: 694b ldreq r3, [r1, #20] 801636e: 1bf6 subs r6, r6, r7 8016370: 600f str r7, [r1, #0] 8016372: 608b str r3, [r1, #8] 8016374: 2e00 cmp r6, #0 8016376: ddeb ble.n 8016350 <__sflush_r+0xac> 8016378: 4633 mov r3, r6 801637a: 463a mov r2, r7 801637c: 4628 mov r0, r5 801637e: 6a21 ldr r1, [r4, #32] 8016380: f8d4 c028 ldr.w ip, [r4, #40] @ 0x28 8016384: 47e0 blx ip 8016386: 2800 cmp r0, #0 8016388: dc07 bgt.n 801639a <__sflush_r+0xf6> 801638a: f9b4 300c ldrsh.w r3, [r4, #12] 801638e: f043 0340 orr.w r3, r3, #64 @ 0x40 8016392: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016396: 81a3 strh r3, [r4, #12] 8016398: bdf8 pop {r3, r4, r5, r6, r7, pc} 801639a: 4407 add r7, r0 801639c: 1a36 subs r6, r6, r0 801639e: e7e9 b.n 8016374 <__sflush_r+0xd0> 80163a0: 20400001 .word 0x20400001 080163a4 <_fflush_r>: 80163a4: b538 push {r3, r4, r5, lr} 80163a6: 690b ldr r3, [r1, #16] 80163a8: 4605 mov r5, r0 80163aa: 460c mov r4, r1 80163ac: b913 cbnz r3, 80163b4 <_fflush_r+0x10> 80163ae: 2500 movs r5, #0 80163b0: 4628 mov r0, r5 80163b2: bd38 pop {r3, r4, r5, pc} 80163b4: b118 cbz r0, 80163be <_fflush_r+0x1a> 80163b6: 6a03 ldr r3, [r0, #32] 80163b8: b90b cbnz r3, 80163be <_fflush_r+0x1a> 80163ba: f7fe fe2d bl 8015018 <__sinit> 80163be: f9b4 300c ldrsh.w r3, [r4, #12] 80163c2: 2b00 cmp r3, #0 80163c4: d0f3 beq.n 80163ae <_fflush_r+0xa> 80163c6: 6e62 ldr r2, [r4, #100] @ 0x64 80163c8: 07d0 lsls r0, r2, #31 80163ca: d404 bmi.n 80163d6 <_fflush_r+0x32> 80163cc: 0599 lsls r1, r3, #22 80163ce: d402 bmi.n 80163d6 <_fflush_r+0x32> 80163d0: 6da0 ldr r0, [r4, #88] @ 0x58 80163d2: f7fe fec6 bl 8015162 <__retarget_lock_acquire_recursive> 80163d6: 4628 mov r0, r5 80163d8: 4621 mov r1, r4 80163da: f7ff ff63 bl 80162a4 <__sflush_r> 80163de: 6e63 ldr r3, [r4, #100] @ 0x64 80163e0: 4605 mov r5, r0 80163e2: 07da lsls r2, r3, #31 80163e4: d4e4 bmi.n 80163b0 <_fflush_r+0xc> 80163e6: 89a3 ldrh r3, [r4, #12] 80163e8: 059b lsls r3, r3, #22 80163ea: d4e1 bmi.n 80163b0 <_fflush_r+0xc> 80163ec: 6da0 ldr r0, [r4, #88] @ 0x58 80163ee: f7fe feb9 bl 8015164 <__retarget_lock_release_recursive> 80163f2: e7dd b.n 80163b0 <_fflush_r+0xc> 080163f4 <__malloc_lock>: 80163f4: 4801 ldr r0, [pc, #4] @ (80163fc <__malloc_lock+0x8>) 80163f6: f7fe beb4 b.w 8015162 <__retarget_lock_acquire_recursive> 80163fa: bf00 nop 80163fc: 200015dc .word 0x200015dc 08016400 <__malloc_unlock>: 8016400: 4801 ldr r0, [pc, #4] @ (8016408 <__malloc_unlock+0x8>) 8016402: f7fe beaf b.w 8015164 <__retarget_lock_release_recursive> 8016406: bf00 nop 8016408: 200015dc .word 0x200015dc 0801640c <_Balloc>: 801640c: b570 push {r4, r5, r6, lr} 801640e: 69c6 ldr r6, [r0, #28] 8016410: 4604 mov r4, r0 8016412: 460d mov r5, r1 8016414: b976 cbnz r6, 8016434 <_Balloc+0x28> 8016416: 2010 movs r0, #16 8016418: f7ff fe9a bl 8016150 801641c: 4602 mov r2, r0 801641e: 61e0 str r0, [r4, #28] 8016420: b920 cbnz r0, 801642c <_Balloc+0x20> 8016422: 216b movs r1, #107 @ 0x6b 8016424: 4b17 ldr r3, [pc, #92] @ (8016484 <_Balloc+0x78>) 8016426: 4818 ldr r0, [pc, #96] @ (8016488 <_Balloc+0x7c>) 8016428: f7fe febe bl 80151a8 <__assert_func> 801642c: e9c0 6601 strd r6, r6, [r0, #4] 8016430: 6006 str r6, [r0, #0] 8016432: 60c6 str r6, [r0, #12] 8016434: 69e6 ldr r6, [r4, #28] 8016436: 68f3 ldr r3, [r6, #12] 8016438: b183 cbz r3, 801645c <_Balloc+0x50> 801643a: 69e3 ldr r3, [r4, #28] 801643c: 68db ldr r3, [r3, #12] 801643e: f853 0025 ldr.w r0, [r3, r5, lsl #2] 8016442: b9b8 cbnz r0, 8016474 <_Balloc+0x68> 8016444: 2101 movs r1, #1 8016446: fa01 f605 lsl.w r6, r1, r5 801644a: 1d72 adds r2, r6, #5 801644c: 4620 mov r0, r4 801644e: 0092 lsls r2, r2, #2 8016450: f000 fc51 bl 8016cf6 <_calloc_r> 8016454: b160 cbz r0, 8016470 <_Balloc+0x64> 8016456: e9c0 5601 strd r5, r6, [r0, #4] 801645a: e00e b.n 801647a <_Balloc+0x6e> 801645c: 2221 movs r2, #33 @ 0x21 801645e: 2104 movs r1, #4 8016460: 4620 mov r0, r4 8016462: f000 fc48 bl 8016cf6 <_calloc_r> 8016466: 69e3 ldr r3, [r4, #28] 8016468: 60f0 str r0, [r6, #12] 801646a: 68db ldr r3, [r3, #12] 801646c: 2b00 cmp r3, #0 801646e: d1e4 bne.n 801643a <_Balloc+0x2e> 8016470: 2000 movs r0, #0 8016472: bd70 pop {r4, r5, r6, pc} 8016474: 6802 ldr r2, [r0, #0] 8016476: f843 2025 str.w r2, [r3, r5, lsl #2] 801647a: 2300 movs r3, #0 801647c: e9c0 3303 strd r3, r3, [r0, #12] 8016480: e7f7 b.n 8016472 <_Balloc+0x66> 8016482: bf00 nop 8016484: 08017e39 .word 0x08017e39 8016488: 08017eca .word 0x08017eca 0801648c <_Bfree>: 801648c: b570 push {r4, r5, r6, lr} 801648e: 69c6 ldr r6, [r0, #28] 8016490: 4605 mov r5, r0 8016492: 460c mov r4, r1 8016494: b976 cbnz r6, 80164b4 <_Bfree+0x28> 8016496: 2010 movs r0, #16 8016498: f7ff fe5a bl 8016150 801649c: 4602 mov r2, r0 801649e: 61e8 str r0, [r5, #28] 80164a0: b920 cbnz r0, 80164ac <_Bfree+0x20> 80164a2: 218f movs r1, #143 @ 0x8f 80164a4: 4b08 ldr r3, [pc, #32] @ (80164c8 <_Bfree+0x3c>) 80164a6: 4809 ldr r0, [pc, #36] @ (80164cc <_Bfree+0x40>) 80164a8: f7fe fe7e bl 80151a8 <__assert_func> 80164ac: e9c0 6601 strd r6, r6, [r0, #4] 80164b0: 6006 str r6, [r0, #0] 80164b2: 60c6 str r6, [r0, #12] 80164b4: b13c cbz r4, 80164c6 <_Bfree+0x3a> 80164b6: 69eb ldr r3, [r5, #28] 80164b8: 6862 ldr r2, [r4, #4] 80164ba: 68db ldr r3, [r3, #12] 80164bc: f853 1022 ldr.w r1, [r3, r2, lsl #2] 80164c0: 6021 str r1, [r4, #0] 80164c2: f843 4022 str.w r4, [r3, r2, lsl #2] 80164c6: bd70 pop {r4, r5, r6, pc} 80164c8: 08017e39 .word 0x08017e39 80164cc: 08017eca .word 0x08017eca 080164d0 <__multadd>: 80164d0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80164d4: 4607 mov r7, r0 80164d6: 460c mov r4, r1 80164d8: 461e mov r6, r3 80164da: 2000 movs r0, #0 80164dc: 690d ldr r5, [r1, #16] 80164de: f101 0c14 add.w ip, r1, #20 80164e2: f8dc 3000 ldr.w r3, [ip] 80164e6: 3001 adds r0, #1 80164e8: b299 uxth r1, r3 80164ea: fb02 6101 mla r1, r2, r1, r6 80164ee: 0c1e lsrs r6, r3, #16 80164f0: 0c0b lsrs r3, r1, #16 80164f2: fb02 3306 mla r3, r2, r6, r3 80164f6: b289 uxth r1, r1 80164f8: eb01 4103 add.w r1, r1, r3, lsl #16 80164fc: 4285 cmp r5, r0 80164fe: ea4f 4613 mov.w r6, r3, lsr #16 8016502: f84c 1b04 str.w r1, [ip], #4 8016506: dcec bgt.n 80164e2 <__multadd+0x12> 8016508: b30e cbz r6, 801654e <__multadd+0x7e> 801650a: 68a3 ldr r3, [r4, #8] 801650c: 42ab cmp r3, r5 801650e: dc19 bgt.n 8016544 <__multadd+0x74> 8016510: 6861 ldr r1, [r4, #4] 8016512: 4638 mov r0, r7 8016514: 3101 adds r1, #1 8016516: f7ff ff79 bl 801640c <_Balloc> 801651a: 4680 mov r8, r0 801651c: b928 cbnz r0, 801652a <__multadd+0x5a> 801651e: 4602 mov r2, r0 8016520: 21ba movs r1, #186 @ 0xba 8016522: 4b0c ldr r3, [pc, #48] @ (8016554 <__multadd+0x84>) 8016524: 480c ldr r0, [pc, #48] @ (8016558 <__multadd+0x88>) 8016526: f7fe fe3f bl 80151a8 <__assert_func> 801652a: 6922 ldr r2, [r4, #16] 801652c: f104 010c add.w r1, r4, #12 8016530: 3202 adds r2, #2 8016532: 0092 lsls r2, r2, #2 8016534: 300c adds r0, #12 8016536: f7fe fe29 bl 801518c 801653a: 4621 mov r1, r4 801653c: 4638 mov r0, r7 801653e: f7ff ffa5 bl 801648c <_Bfree> 8016542: 4644 mov r4, r8 8016544: eb04 0385 add.w r3, r4, r5, lsl #2 8016548: 3501 adds r5, #1 801654a: 615e str r6, [r3, #20] 801654c: 6125 str r5, [r4, #16] 801654e: 4620 mov r0, r4 8016550: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8016554: 08017ea8 .word 0x08017ea8 8016558: 08017eca .word 0x08017eca 0801655c <__hi0bits>: 801655c: 4603 mov r3, r0 801655e: f5b0 3f80 cmp.w r0, #65536 @ 0x10000 8016562: bf3a itte cc 8016564: 0403 lslcc r3, r0, #16 8016566: 2010 movcc r0, #16 8016568: 2000 movcs r0, #0 801656a: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 801656e: bf3c itt cc 8016570: 021b lslcc r3, r3, #8 8016572: 3008 addcc r0, #8 8016574: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8016578: bf3c itt cc 801657a: 011b lslcc r3, r3, #4 801657c: 3004 addcc r0, #4 801657e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8016582: bf3c itt cc 8016584: 009b lslcc r3, r3, #2 8016586: 3002 addcc r0, #2 8016588: 2b00 cmp r3, #0 801658a: db05 blt.n 8016598 <__hi0bits+0x3c> 801658c: f013 4f80 tst.w r3, #1073741824 @ 0x40000000 8016590: f100 0001 add.w r0, r0, #1 8016594: bf08 it eq 8016596: 2020 moveq r0, #32 8016598: 4770 bx lr 0801659a <__lo0bits>: 801659a: 6803 ldr r3, [r0, #0] 801659c: 4602 mov r2, r0 801659e: f013 0007 ands.w r0, r3, #7 80165a2: d00b beq.n 80165bc <__lo0bits+0x22> 80165a4: 07d9 lsls r1, r3, #31 80165a6: d421 bmi.n 80165ec <__lo0bits+0x52> 80165a8: 0798 lsls r0, r3, #30 80165aa: bf49 itett mi 80165ac: 085b lsrmi r3, r3, #1 80165ae: 089b lsrpl r3, r3, #2 80165b0: 2001 movmi r0, #1 80165b2: 6013 strmi r3, [r2, #0] 80165b4: bf5c itt pl 80165b6: 2002 movpl r0, #2 80165b8: 6013 strpl r3, [r2, #0] 80165ba: 4770 bx lr 80165bc: b299 uxth r1, r3 80165be: b909 cbnz r1, 80165c4 <__lo0bits+0x2a> 80165c0: 2010 movs r0, #16 80165c2: 0c1b lsrs r3, r3, #16 80165c4: b2d9 uxtb r1, r3 80165c6: b909 cbnz r1, 80165cc <__lo0bits+0x32> 80165c8: 3008 adds r0, #8 80165ca: 0a1b lsrs r3, r3, #8 80165cc: 0719 lsls r1, r3, #28 80165ce: bf04 itt eq 80165d0: 091b lsreq r3, r3, #4 80165d2: 3004 addeq r0, #4 80165d4: 0799 lsls r1, r3, #30 80165d6: bf04 itt eq 80165d8: 089b lsreq r3, r3, #2 80165da: 3002 addeq r0, #2 80165dc: 07d9 lsls r1, r3, #31 80165de: d403 bmi.n 80165e8 <__lo0bits+0x4e> 80165e0: 085b lsrs r3, r3, #1 80165e2: f100 0001 add.w r0, r0, #1 80165e6: d003 beq.n 80165f0 <__lo0bits+0x56> 80165e8: 6013 str r3, [r2, #0] 80165ea: 4770 bx lr 80165ec: 2000 movs r0, #0 80165ee: 4770 bx lr 80165f0: 2020 movs r0, #32 80165f2: 4770 bx lr 080165f4 <__i2b>: 80165f4: b510 push {r4, lr} 80165f6: 460c mov r4, r1 80165f8: 2101 movs r1, #1 80165fa: f7ff ff07 bl 801640c <_Balloc> 80165fe: 4602 mov r2, r0 8016600: b928 cbnz r0, 801660e <__i2b+0x1a> 8016602: f240 1145 movw r1, #325 @ 0x145 8016606: 4b04 ldr r3, [pc, #16] @ (8016618 <__i2b+0x24>) 8016608: 4804 ldr r0, [pc, #16] @ (801661c <__i2b+0x28>) 801660a: f7fe fdcd bl 80151a8 <__assert_func> 801660e: 2301 movs r3, #1 8016610: 6144 str r4, [r0, #20] 8016612: 6103 str r3, [r0, #16] 8016614: bd10 pop {r4, pc} 8016616: bf00 nop 8016618: 08017ea8 .word 0x08017ea8 801661c: 08017eca .word 0x08017eca 08016620 <__multiply>: 8016620: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8016624: 4617 mov r7, r2 8016626: 690a ldr r2, [r1, #16] 8016628: 693b ldr r3, [r7, #16] 801662a: 4689 mov r9, r1 801662c: 429a cmp r2, r3 801662e: bfa2 ittt ge 8016630: 463b movge r3, r7 8016632: 460f movge r7, r1 8016634: 4699 movge r9, r3 8016636: 693d ldr r5, [r7, #16] 8016638: f8d9 a010 ldr.w sl, [r9, #16] 801663c: 68bb ldr r3, [r7, #8] 801663e: 6879 ldr r1, [r7, #4] 8016640: eb05 060a add.w r6, r5, sl 8016644: 42b3 cmp r3, r6 8016646: b085 sub sp, #20 8016648: bfb8 it lt 801664a: 3101 addlt r1, #1 801664c: f7ff fede bl 801640c <_Balloc> 8016650: b930 cbnz r0, 8016660 <__multiply+0x40> 8016652: 4602 mov r2, r0 8016654: f44f 71b1 mov.w r1, #354 @ 0x162 8016658: 4b40 ldr r3, [pc, #256] @ (801675c <__multiply+0x13c>) 801665a: 4841 ldr r0, [pc, #260] @ (8016760 <__multiply+0x140>) 801665c: f7fe fda4 bl 80151a8 <__assert_func> 8016660: f100 0414 add.w r4, r0, #20 8016664: 4623 mov r3, r4 8016666: 2200 movs r2, #0 8016668: eb04 0e86 add.w lr, r4, r6, lsl #2 801666c: 4573 cmp r3, lr 801666e: d320 bcc.n 80166b2 <__multiply+0x92> 8016670: f107 0814 add.w r8, r7, #20 8016674: f109 0114 add.w r1, r9, #20 8016678: eb08 0585 add.w r5, r8, r5, lsl #2 801667c: eb01 038a add.w r3, r1, sl, lsl #2 8016680: 9302 str r3, [sp, #8] 8016682: 1beb subs r3, r5, r7 8016684: 3b15 subs r3, #21 8016686: f023 0303 bic.w r3, r3, #3 801668a: 3304 adds r3, #4 801668c: 3715 adds r7, #21 801668e: 42bd cmp r5, r7 8016690: bf38 it cc 8016692: 2304 movcc r3, #4 8016694: 9301 str r3, [sp, #4] 8016696: 9b02 ldr r3, [sp, #8] 8016698: 9103 str r1, [sp, #12] 801669a: 428b cmp r3, r1 801669c: d80c bhi.n 80166b8 <__multiply+0x98> 801669e: 2e00 cmp r6, #0 80166a0: dd03 ble.n 80166aa <__multiply+0x8a> 80166a2: f85e 3d04 ldr.w r3, [lr, #-4]! 80166a6: 2b00 cmp r3, #0 80166a8: d055 beq.n 8016756 <__multiply+0x136> 80166aa: 6106 str r6, [r0, #16] 80166ac: b005 add sp, #20 80166ae: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80166b2: f843 2b04 str.w r2, [r3], #4 80166b6: e7d9 b.n 801666c <__multiply+0x4c> 80166b8: f8b1 a000 ldrh.w sl, [r1] 80166bc: f1ba 0f00 cmp.w sl, #0 80166c0: d01f beq.n 8016702 <__multiply+0xe2> 80166c2: 46c4 mov ip, r8 80166c4: 46a1 mov r9, r4 80166c6: 2700 movs r7, #0 80166c8: f85c 2b04 ldr.w r2, [ip], #4 80166cc: f8d9 3000 ldr.w r3, [r9] 80166d0: fa1f fb82 uxth.w fp, r2 80166d4: b29b uxth r3, r3 80166d6: fb0a 330b mla r3, sl, fp, r3 80166da: 443b add r3, r7 80166dc: f8d9 7000 ldr.w r7, [r9] 80166e0: 0c12 lsrs r2, r2, #16 80166e2: 0c3f lsrs r7, r7, #16 80166e4: fb0a 7202 mla r2, sl, r2, r7 80166e8: eb02 4213 add.w r2, r2, r3, lsr #16 80166ec: b29b uxth r3, r3 80166ee: ea43 4302 orr.w r3, r3, r2, lsl #16 80166f2: 4565 cmp r5, ip 80166f4: ea4f 4712 mov.w r7, r2, lsr #16 80166f8: f849 3b04 str.w r3, [r9], #4 80166fc: d8e4 bhi.n 80166c8 <__multiply+0xa8> 80166fe: 9b01 ldr r3, [sp, #4] 8016700: 50e7 str r7, [r4, r3] 8016702: 9b03 ldr r3, [sp, #12] 8016704: 3104 adds r1, #4 8016706: f8b3 9002 ldrh.w r9, [r3, #2] 801670a: f1b9 0f00 cmp.w r9, #0 801670e: d020 beq.n 8016752 <__multiply+0x132> 8016710: 4647 mov r7, r8 8016712: 46a4 mov ip, r4 8016714: f04f 0a00 mov.w sl, #0 8016718: 6823 ldr r3, [r4, #0] 801671a: f8b7 b000 ldrh.w fp, [r7] 801671e: f8bc 2002 ldrh.w r2, [ip, #2] 8016722: b29b uxth r3, r3 8016724: fb09 220b mla r2, r9, fp, r2 8016728: 4452 add r2, sl 801672a: ea43 4302 orr.w r3, r3, r2, lsl #16 801672e: f84c 3b04 str.w r3, [ip], #4 8016732: f857 3b04 ldr.w r3, [r7], #4 8016736: ea4f 4a13 mov.w sl, r3, lsr #16 801673a: f8bc 3000 ldrh.w r3, [ip] 801673e: 42bd cmp r5, r7 8016740: fb09 330a mla r3, r9, sl, r3 8016744: eb03 4312 add.w r3, r3, r2, lsr #16 8016748: ea4f 4a13 mov.w sl, r3, lsr #16 801674c: d8e5 bhi.n 801671a <__multiply+0xfa> 801674e: 9a01 ldr r2, [sp, #4] 8016750: 50a3 str r3, [r4, r2] 8016752: 3404 adds r4, #4 8016754: e79f b.n 8016696 <__multiply+0x76> 8016756: 3e01 subs r6, #1 8016758: e7a1 b.n 801669e <__multiply+0x7e> 801675a: bf00 nop 801675c: 08017ea8 .word 0x08017ea8 8016760: 08017eca .word 0x08017eca 08016764 <__pow5mult>: 8016764: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8016768: 4615 mov r5, r2 801676a: f012 0203 ands.w r2, r2, #3 801676e: 4607 mov r7, r0 8016770: 460e mov r6, r1 8016772: d007 beq.n 8016784 <__pow5mult+0x20> 8016774: 4c25 ldr r4, [pc, #148] @ (801680c <__pow5mult+0xa8>) 8016776: 3a01 subs r2, #1 8016778: 2300 movs r3, #0 801677a: f854 2022 ldr.w r2, [r4, r2, lsl #2] 801677e: f7ff fea7 bl 80164d0 <__multadd> 8016782: 4606 mov r6, r0 8016784: 10ad asrs r5, r5, #2 8016786: d03d beq.n 8016804 <__pow5mult+0xa0> 8016788: 69fc ldr r4, [r7, #28] 801678a: b97c cbnz r4, 80167ac <__pow5mult+0x48> 801678c: 2010 movs r0, #16 801678e: f7ff fcdf bl 8016150 8016792: 4602 mov r2, r0 8016794: 61f8 str r0, [r7, #28] 8016796: b928 cbnz r0, 80167a4 <__pow5mult+0x40> 8016798: f240 11b3 movw r1, #435 @ 0x1b3 801679c: 4b1c ldr r3, [pc, #112] @ (8016810 <__pow5mult+0xac>) 801679e: 481d ldr r0, [pc, #116] @ (8016814 <__pow5mult+0xb0>) 80167a0: f7fe fd02 bl 80151a8 <__assert_func> 80167a4: e9c0 4401 strd r4, r4, [r0, #4] 80167a8: 6004 str r4, [r0, #0] 80167aa: 60c4 str r4, [r0, #12] 80167ac: f8d7 801c ldr.w r8, [r7, #28] 80167b0: f8d8 4008 ldr.w r4, [r8, #8] 80167b4: b94c cbnz r4, 80167ca <__pow5mult+0x66> 80167b6: f240 2171 movw r1, #625 @ 0x271 80167ba: 4638 mov r0, r7 80167bc: f7ff ff1a bl 80165f4 <__i2b> 80167c0: 2300 movs r3, #0 80167c2: 4604 mov r4, r0 80167c4: f8c8 0008 str.w r0, [r8, #8] 80167c8: 6003 str r3, [r0, #0] 80167ca: f04f 0900 mov.w r9, #0 80167ce: 07eb lsls r3, r5, #31 80167d0: d50a bpl.n 80167e8 <__pow5mult+0x84> 80167d2: 4631 mov r1, r6 80167d4: 4622 mov r2, r4 80167d6: 4638 mov r0, r7 80167d8: f7ff ff22 bl 8016620 <__multiply> 80167dc: 4680 mov r8, r0 80167de: 4631 mov r1, r6 80167e0: 4638 mov r0, r7 80167e2: f7ff fe53 bl 801648c <_Bfree> 80167e6: 4646 mov r6, r8 80167e8: 106d asrs r5, r5, #1 80167ea: d00b beq.n 8016804 <__pow5mult+0xa0> 80167ec: 6820 ldr r0, [r4, #0] 80167ee: b938 cbnz r0, 8016800 <__pow5mult+0x9c> 80167f0: 4622 mov r2, r4 80167f2: 4621 mov r1, r4 80167f4: 4638 mov r0, r7 80167f6: f7ff ff13 bl 8016620 <__multiply> 80167fa: 6020 str r0, [r4, #0] 80167fc: f8c0 9000 str.w r9, [r0] 8016800: 4604 mov r4, r0 8016802: e7e4 b.n 80167ce <__pow5mult+0x6a> 8016804: 4630 mov r0, r6 8016806: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 801680a: bf00 nop 801680c: 08017f30 .word 0x08017f30 8016810: 08017e39 .word 0x08017e39 8016814: 08017eca .word 0x08017eca 08016818 <__lshift>: 8016818: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 801681c: 460c mov r4, r1 801681e: 4607 mov r7, r0 8016820: 4691 mov r9, r2 8016822: 6923 ldr r3, [r4, #16] 8016824: 6849 ldr r1, [r1, #4] 8016826: eb03 1862 add.w r8, r3, r2, asr #5 801682a: 68a3 ldr r3, [r4, #8] 801682c: ea4f 1a62 mov.w sl, r2, asr #5 8016830: f108 0601 add.w r6, r8, #1 8016834: 42b3 cmp r3, r6 8016836: db0b blt.n 8016850 <__lshift+0x38> 8016838: 4638 mov r0, r7 801683a: f7ff fde7 bl 801640c <_Balloc> 801683e: 4605 mov r5, r0 8016840: b948 cbnz r0, 8016856 <__lshift+0x3e> 8016842: 4602 mov r2, r0 8016844: f44f 71ef mov.w r1, #478 @ 0x1de 8016848: 4b27 ldr r3, [pc, #156] @ (80168e8 <__lshift+0xd0>) 801684a: 4828 ldr r0, [pc, #160] @ (80168ec <__lshift+0xd4>) 801684c: f7fe fcac bl 80151a8 <__assert_func> 8016850: 3101 adds r1, #1 8016852: 005b lsls r3, r3, #1 8016854: e7ee b.n 8016834 <__lshift+0x1c> 8016856: 2300 movs r3, #0 8016858: f100 0114 add.w r1, r0, #20 801685c: f100 0210 add.w r2, r0, #16 8016860: 4618 mov r0, r3 8016862: 4553 cmp r3, sl 8016864: db33 blt.n 80168ce <__lshift+0xb6> 8016866: 6920 ldr r0, [r4, #16] 8016868: ea2a 7aea bic.w sl, sl, sl, asr #31 801686c: f104 0314 add.w r3, r4, #20 8016870: f019 091f ands.w r9, r9, #31 8016874: eb01 018a add.w r1, r1, sl, lsl #2 8016878: eb03 0c80 add.w ip, r3, r0, lsl #2 801687c: d02b beq.n 80168d6 <__lshift+0xbe> 801687e: 468a mov sl, r1 8016880: 2200 movs r2, #0 8016882: f1c9 0e20 rsb lr, r9, #32 8016886: 6818 ldr r0, [r3, #0] 8016888: fa00 f009 lsl.w r0, r0, r9 801688c: 4310 orrs r0, r2 801688e: f84a 0b04 str.w r0, [sl], #4 8016892: f853 2b04 ldr.w r2, [r3], #4 8016896: 459c cmp ip, r3 8016898: fa22 f20e lsr.w r2, r2, lr 801689c: d8f3 bhi.n 8016886 <__lshift+0x6e> 801689e: ebac 0304 sub.w r3, ip, r4 80168a2: 3b15 subs r3, #21 80168a4: f023 0303 bic.w r3, r3, #3 80168a8: 3304 adds r3, #4 80168aa: f104 0015 add.w r0, r4, #21 80168ae: 4560 cmp r0, ip 80168b0: bf88 it hi 80168b2: 2304 movhi r3, #4 80168b4: 50ca str r2, [r1, r3] 80168b6: b10a cbz r2, 80168bc <__lshift+0xa4> 80168b8: f108 0602 add.w r6, r8, #2 80168bc: 3e01 subs r6, #1 80168be: 4638 mov r0, r7 80168c0: 4621 mov r1, r4 80168c2: 612e str r6, [r5, #16] 80168c4: f7ff fde2 bl 801648c <_Bfree> 80168c8: 4628 mov r0, r5 80168ca: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80168ce: f842 0f04 str.w r0, [r2, #4]! 80168d2: 3301 adds r3, #1 80168d4: e7c5 b.n 8016862 <__lshift+0x4a> 80168d6: 3904 subs r1, #4 80168d8: f853 2b04 ldr.w r2, [r3], #4 80168dc: 459c cmp ip, r3 80168de: f841 2f04 str.w r2, [r1, #4]! 80168e2: d8f9 bhi.n 80168d8 <__lshift+0xc0> 80168e4: e7ea b.n 80168bc <__lshift+0xa4> 80168e6: bf00 nop 80168e8: 08017ea8 .word 0x08017ea8 80168ec: 08017eca .word 0x08017eca 080168f0 <__mcmp>: 80168f0: 4603 mov r3, r0 80168f2: 690a ldr r2, [r1, #16] 80168f4: 6900 ldr r0, [r0, #16] 80168f6: b530 push {r4, r5, lr} 80168f8: 1a80 subs r0, r0, r2 80168fa: d10e bne.n 801691a <__mcmp+0x2a> 80168fc: 3314 adds r3, #20 80168fe: 3114 adds r1, #20 8016900: eb03 0482 add.w r4, r3, r2, lsl #2 8016904: eb01 0182 add.w r1, r1, r2, lsl #2 8016908: f854 5d04 ldr.w r5, [r4, #-4]! 801690c: f851 2d04 ldr.w r2, [r1, #-4]! 8016910: 4295 cmp r5, r2 8016912: d003 beq.n 801691c <__mcmp+0x2c> 8016914: d205 bcs.n 8016922 <__mcmp+0x32> 8016916: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801691a: bd30 pop {r4, r5, pc} 801691c: 42a3 cmp r3, r4 801691e: d3f3 bcc.n 8016908 <__mcmp+0x18> 8016920: e7fb b.n 801691a <__mcmp+0x2a> 8016922: 2001 movs r0, #1 8016924: e7f9 b.n 801691a <__mcmp+0x2a> ... 08016928 <__mdiff>: 8016928: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 801692c: 4689 mov r9, r1 801692e: 4606 mov r6, r0 8016930: 4611 mov r1, r2 8016932: 4648 mov r0, r9 8016934: 4614 mov r4, r2 8016936: f7ff ffdb bl 80168f0 <__mcmp> 801693a: 1e05 subs r5, r0, #0 801693c: d112 bne.n 8016964 <__mdiff+0x3c> 801693e: 4629 mov r1, r5 8016940: 4630 mov r0, r6 8016942: f7ff fd63 bl 801640c <_Balloc> 8016946: 4602 mov r2, r0 8016948: b928 cbnz r0, 8016956 <__mdiff+0x2e> 801694a: f240 2137 movw r1, #567 @ 0x237 801694e: 4b3e ldr r3, [pc, #248] @ (8016a48 <__mdiff+0x120>) 8016950: 483e ldr r0, [pc, #248] @ (8016a4c <__mdiff+0x124>) 8016952: f7fe fc29 bl 80151a8 <__assert_func> 8016956: 2301 movs r3, #1 8016958: e9c0 3504 strd r3, r5, [r0, #16] 801695c: 4610 mov r0, r2 801695e: b003 add sp, #12 8016960: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8016964: bfbc itt lt 8016966: 464b movlt r3, r9 8016968: 46a1 movlt r9, r4 801696a: 4630 mov r0, r6 801696c: f8d9 1004 ldr.w r1, [r9, #4] 8016970: bfba itte lt 8016972: 461c movlt r4, r3 8016974: 2501 movlt r5, #1 8016976: 2500 movge r5, #0 8016978: f7ff fd48 bl 801640c <_Balloc> 801697c: 4602 mov r2, r0 801697e: b918 cbnz r0, 8016988 <__mdiff+0x60> 8016980: f240 2145 movw r1, #581 @ 0x245 8016984: 4b30 ldr r3, [pc, #192] @ (8016a48 <__mdiff+0x120>) 8016986: e7e3 b.n 8016950 <__mdiff+0x28> 8016988: f100 0b14 add.w fp, r0, #20 801698c: f8d9 7010 ldr.w r7, [r9, #16] 8016990: f109 0310 add.w r3, r9, #16 8016994: 60c5 str r5, [r0, #12] 8016996: f04f 0c00 mov.w ip, #0 801699a: f109 0514 add.w r5, r9, #20 801699e: 46d9 mov r9, fp 80169a0: 6926 ldr r6, [r4, #16] 80169a2: f104 0e14 add.w lr, r4, #20 80169a6: eb05 0887 add.w r8, r5, r7, lsl #2 80169aa: eb0e 0686 add.w r6, lr, r6, lsl #2 80169ae: 9301 str r3, [sp, #4] 80169b0: 9b01 ldr r3, [sp, #4] 80169b2: f85e 0b04 ldr.w r0, [lr], #4 80169b6: f853 af04 ldr.w sl, [r3, #4]! 80169ba: b281 uxth r1, r0 80169bc: 9301 str r3, [sp, #4] 80169be: fa1f f38a uxth.w r3, sl 80169c2: 1a5b subs r3, r3, r1 80169c4: 0c00 lsrs r0, r0, #16 80169c6: 4463 add r3, ip 80169c8: ebc0 401a rsb r0, r0, sl, lsr #16 80169cc: eb00 4023 add.w r0, r0, r3, asr #16 80169d0: b29b uxth r3, r3 80169d2: ea43 4300 orr.w r3, r3, r0, lsl #16 80169d6: 4576 cmp r6, lr 80169d8: ea4f 4c20 mov.w ip, r0, asr #16 80169dc: f849 3b04 str.w r3, [r9], #4 80169e0: d8e6 bhi.n 80169b0 <__mdiff+0x88> 80169e2: 1b33 subs r3, r6, r4 80169e4: 3b15 subs r3, #21 80169e6: f023 0303 bic.w r3, r3, #3 80169ea: 3415 adds r4, #21 80169ec: 3304 adds r3, #4 80169ee: 42a6 cmp r6, r4 80169f0: bf38 it cc 80169f2: 2304 movcc r3, #4 80169f4: 441d add r5, r3 80169f6: 445b add r3, fp 80169f8: 461e mov r6, r3 80169fa: 462c mov r4, r5 80169fc: 4544 cmp r4, r8 80169fe: d30e bcc.n 8016a1e <__mdiff+0xf6> 8016a00: f108 0103 add.w r1, r8, #3 8016a04: 1b49 subs r1, r1, r5 8016a06: f021 0103 bic.w r1, r1, #3 8016a0a: 3d03 subs r5, #3 8016a0c: 45a8 cmp r8, r5 8016a0e: bf38 it cc 8016a10: 2100 movcc r1, #0 8016a12: 440b add r3, r1 8016a14: f853 1d04 ldr.w r1, [r3, #-4]! 8016a18: b199 cbz r1, 8016a42 <__mdiff+0x11a> 8016a1a: 6117 str r7, [r2, #16] 8016a1c: e79e b.n 801695c <__mdiff+0x34> 8016a1e: 46e6 mov lr, ip 8016a20: f854 1b04 ldr.w r1, [r4], #4 8016a24: fa1f fc81 uxth.w ip, r1 8016a28: 44f4 add ip, lr 8016a2a: 0c08 lsrs r0, r1, #16 8016a2c: 4471 add r1, lr 8016a2e: eb00 402c add.w r0, r0, ip, asr #16 8016a32: b289 uxth r1, r1 8016a34: ea41 4100 orr.w r1, r1, r0, lsl #16 8016a38: ea4f 4c20 mov.w ip, r0, asr #16 8016a3c: f846 1b04 str.w r1, [r6], #4 8016a40: e7dc b.n 80169fc <__mdiff+0xd4> 8016a42: 3f01 subs r7, #1 8016a44: e7e6 b.n 8016a14 <__mdiff+0xec> 8016a46: bf00 nop 8016a48: 08017ea8 .word 0x08017ea8 8016a4c: 08017eca .word 0x08017eca 08016a50 <__d2b>: 8016a50: e92d 4373 stmdb sp!, {r0, r1, r4, r5, r6, r8, r9, lr} 8016a54: 2101 movs r1, #1 8016a56: 4690 mov r8, r2 8016a58: 4699 mov r9, r3 8016a5a: 9e08 ldr r6, [sp, #32] 8016a5c: f7ff fcd6 bl 801640c <_Balloc> 8016a60: 4604 mov r4, r0 8016a62: b930 cbnz r0, 8016a72 <__d2b+0x22> 8016a64: 4602 mov r2, r0 8016a66: f240 310f movw r1, #783 @ 0x30f 8016a6a: 4b23 ldr r3, [pc, #140] @ (8016af8 <__d2b+0xa8>) 8016a6c: 4823 ldr r0, [pc, #140] @ (8016afc <__d2b+0xac>) 8016a6e: f7fe fb9b bl 80151a8 <__assert_func> 8016a72: f3c9 550a ubfx r5, r9, #20, #11 8016a76: f3c9 0313 ubfx r3, r9, #0, #20 8016a7a: b10d cbz r5, 8016a80 <__d2b+0x30> 8016a7c: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8016a80: 9301 str r3, [sp, #4] 8016a82: f1b8 0300 subs.w r3, r8, #0 8016a86: d024 beq.n 8016ad2 <__d2b+0x82> 8016a88: 4668 mov r0, sp 8016a8a: 9300 str r3, [sp, #0] 8016a8c: f7ff fd85 bl 801659a <__lo0bits> 8016a90: e9dd 1200 ldrd r1, r2, [sp] 8016a94: b1d8 cbz r0, 8016ace <__d2b+0x7e> 8016a96: f1c0 0320 rsb r3, r0, #32 8016a9a: fa02 f303 lsl.w r3, r2, r3 8016a9e: 430b orrs r3, r1 8016aa0: 40c2 lsrs r2, r0 8016aa2: 6163 str r3, [r4, #20] 8016aa4: 9201 str r2, [sp, #4] 8016aa6: 9b01 ldr r3, [sp, #4] 8016aa8: 2b00 cmp r3, #0 8016aaa: bf0c ite eq 8016aac: 2201 moveq r2, #1 8016aae: 2202 movne r2, #2 8016ab0: 61a3 str r3, [r4, #24] 8016ab2: 6122 str r2, [r4, #16] 8016ab4: b1ad cbz r5, 8016ae2 <__d2b+0x92> 8016ab6: f2a5 4533 subw r5, r5, #1075 @ 0x433 8016aba: 4405 add r5, r0 8016abc: 6035 str r5, [r6, #0] 8016abe: f1c0 0035 rsb r0, r0, #53 @ 0x35 8016ac2: 9b09 ldr r3, [sp, #36] @ 0x24 8016ac4: 6018 str r0, [r3, #0] 8016ac6: 4620 mov r0, r4 8016ac8: b002 add sp, #8 8016aca: e8bd 8370 ldmia.w sp!, {r4, r5, r6, r8, r9, pc} 8016ace: 6161 str r1, [r4, #20] 8016ad0: e7e9 b.n 8016aa6 <__d2b+0x56> 8016ad2: a801 add r0, sp, #4 8016ad4: f7ff fd61 bl 801659a <__lo0bits> 8016ad8: 9b01 ldr r3, [sp, #4] 8016ada: 2201 movs r2, #1 8016adc: 6163 str r3, [r4, #20] 8016ade: 3020 adds r0, #32 8016ae0: e7e7 b.n 8016ab2 <__d2b+0x62> 8016ae2: f2a0 4032 subw r0, r0, #1074 @ 0x432 8016ae6: eb04 0382 add.w r3, r4, r2, lsl #2 8016aea: 6030 str r0, [r6, #0] 8016aec: 6918 ldr r0, [r3, #16] 8016aee: f7ff fd35 bl 801655c <__hi0bits> 8016af2: ebc0 1042 rsb r0, r0, r2, lsl #5 8016af6: e7e4 b.n 8016ac2 <__d2b+0x72> 8016af8: 08017ea8 .word 0x08017ea8 8016afc: 08017eca .word 0x08017eca 08016b00 <__sread>: 8016b00: b510 push {r4, lr} 8016b02: 460c mov r4, r1 8016b04: f9b1 100e ldrsh.w r1, [r1, #14] 8016b08: f000 f8aa bl 8016c60 <_read_r> 8016b0c: 2800 cmp r0, #0 8016b0e: bfab itete ge 8016b10: 6d63 ldrge r3, [r4, #84] @ 0x54 8016b12: 89a3 ldrhlt r3, [r4, #12] 8016b14: 181b addge r3, r3, r0 8016b16: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 8016b1a: bfac ite ge 8016b1c: 6563 strge r3, [r4, #84] @ 0x54 8016b1e: 81a3 strhlt r3, [r4, #12] 8016b20: bd10 pop {r4, pc} 08016b22 <__swrite>: 8016b22: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8016b26: 461f mov r7, r3 8016b28: 898b ldrh r3, [r1, #12] 8016b2a: 4605 mov r5, r0 8016b2c: 05db lsls r3, r3, #23 8016b2e: 460c mov r4, r1 8016b30: 4616 mov r6, r2 8016b32: d505 bpl.n 8016b40 <__swrite+0x1e> 8016b34: 2302 movs r3, #2 8016b36: 2200 movs r2, #0 8016b38: f9b1 100e ldrsh.w r1, [r1, #14] 8016b3c: f000 f87e bl 8016c3c <_lseek_r> 8016b40: 89a3 ldrh r3, [r4, #12] 8016b42: 4632 mov r2, r6 8016b44: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8016b48: 81a3 strh r3, [r4, #12] 8016b4a: 4628 mov r0, r5 8016b4c: 463b mov r3, r7 8016b4e: f9b4 100e ldrsh.w r1, [r4, #14] 8016b52: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8016b56: f000 b8a5 b.w 8016ca4 <_write_r> 08016b5a <__sseek>: 8016b5a: b510 push {r4, lr} 8016b5c: 460c mov r4, r1 8016b5e: f9b1 100e ldrsh.w r1, [r1, #14] 8016b62: f000 f86b bl 8016c3c <_lseek_r> 8016b66: 1c43 adds r3, r0, #1 8016b68: 89a3 ldrh r3, [r4, #12] 8016b6a: bf15 itete ne 8016b6c: 6560 strne r0, [r4, #84] @ 0x54 8016b6e: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 8016b72: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 8016b76: 81a3 strheq r3, [r4, #12] 8016b78: bf18 it ne 8016b7a: 81a3 strhne r3, [r4, #12] 8016b7c: bd10 pop {r4, pc} 08016b7e <__sclose>: 8016b7e: f9b1 100e ldrsh.w r1, [r1, #14] 8016b82: f000 b8a1 b.w 8016cc8 <_close_r> ... 08016b88 : 8016b88: b40e push {r1, r2, r3} 8016b8a: b503 push {r0, r1, lr} 8016b8c: 4601 mov r1, r0 8016b8e: ab03 add r3, sp, #12 8016b90: 4805 ldr r0, [pc, #20] @ (8016ba8 ) 8016b92: f853 2b04 ldr.w r2, [r3], #4 8016b96: 6800 ldr r0, [r0, #0] 8016b98: 9301 str r3, [sp, #4] 8016b9a: f000 f931 bl 8016e00 <_vfiprintf_r> 8016b9e: b002 add sp, #8 8016ba0: f85d eb04 ldr.w lr, [sp], #4 8016ba4: b003 add sp, #12 8016ba6: 4770 bx lr 8016ba8: 2000009c .word 0x2000009c 08016bac <_realloc_r>: 8016bac: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8016bb0: 4607 mov r7, r0 8016bb2: 4614 mov r4, r2 8016bb4: 460d mov r5, r1 8016bb6: b921 cbnz r1, 8016bc2 <_realloc_r+0x16> 8016bb8: 4611 mov r1, r2 8016bba: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8016bbe: f7ff baf1 b.w 80161a4 <_malloc_r> 8016bc2: b92a cbnz r2, 8016bd0 <_realloc_r+0x24> 8016bc4: f000 f8ac bl 8016d20 <_free_r> 8016bc8: 4625 mov r5, r4 8016bca: 4628 mov r0, r5 8016bcc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8016bd0: f000 fa40 bl 8017054 <_malloc_usable_size_r> 8016bd4: 4284 cmp r4, r0 8016bd6: 4606 mov r6, r0 8016bd8: d802 bhi.n 8016be0 <_realloc_r+0x34> 8016bda: ebb4 0f50 cmp.w r4, r0, lsr #1 8016bde: d8f4 bhi.n 8016bca <_realloc_r+0x1e> 8016be0: 4621 mov r1, r4 8016be2: 4638 mov r0, r7 8016be4: f7ff fade bl 80161a4 <_malloc_r> 8016be8: 4680 mov r8, r0 8016bea: b908 cbnz r0, 8016bf0 <_realloc_r+0x44> 8016bec: 4645 mov r5, r8 8016bee: e7ec b.n 8016bca <_realloc_r+0x1e> 8016bf0: 42b4 cmp r4, r6 8016bf2: 4622 mov r2, r4 8016bf4: 4629 mov r1, r5 8016bf6: bf28 it cs 8016bf8: 4632 movcs r2, r6 8016bfa: f7fe fac7 bl 801518c 8016bfe: 4629 mov r1, r5 8016c00: 4638 mov r0, r7 8016c02: f000 f88d bl 8016d20 <_free_r> 8016c06: e7f1 b.n 8016bec <_realloc_r+0x40> 08016c08 : 8016c08: 4288 cmp r0, r1 8016c0a: b510 push {r4, lr} 8016c0c: eb01 0402 add.w r4, r1, r2 8016c10: d902 bls.n 8016c18 8016c12: 4284 cmp r4, r0 8016c14: 4623 mov r3, r4 8016c16: d807 bhi.n 8016c28 8016c18: 1e43 subs r3, r0, #1 8016c1a: 42a1 cmp r1, r4 8016c1c: d008 beq.n 8016c30 8016c1e: f811 2b01 ldrb.w r2, [r1], #1 8016c22: f803 2f01 strb.w r2, [r3, #1]! 8016c26: e7f8 b.n 8016c1a 8016c28: 4601 mov r1, r0 8016c2a: 4402 add r2, r0 8016c2c: 428a cmp r2, r1 8016c2e: d100 bne.n 8016c32 8016c30: bd10 pop {r4, pc} 8016c32: f813 4d01 ldrb.w r4, [r3, #-1]! 8016c36: f802 4d01 strb.w r4, [r2, #-1]! 8016c3a: e7f7 b.n 8016c2c 08016c3c <_lseek_r>: 8016c3c: b538 push {r3, r4, r5, lr} 8016c3e: 4604 mov r4, r0 8016c40: 4608 mov r0, r1 8016c42: 4611 mov r1, r2 8016c44: 2200 movs r2, #0 8016c46: 4d05 ldr r5, [pc, #20] @ (8016c5c <_lseek_r+0x20>) 8016c48: 602a str r2, [r5, #0] 8016c4a: 461a mov r2, r3 8016c4c: f7f7 f875 bl 800dd3a <_lseek> 8016c50: 1c43 adds r3, r0, #1 8016c52: d102 bne.n 8016c5a <_lseek_r+0x1e> 8016c54: 682b ldr r3, [r5, #0] 8016c56: b103 cbz r3, 8016c5a <_lseek_r+0x1e> 8016c58: 6023 str r3, [r4, #0] 8016c5a: bd38 pop {r3, r4, r5, pc} 8016c5c: 200015e8 .word 0x200015e8 08016c60 <_read_r>: 8016c60: b538 push {r3, r4, r5, lr} 8016c62: 4604 mov r4, r0 8016c64: 4608 mov r0, r1 8016c66: 4611 mov r1, r2 8016c68: 2200 movs r2, #0 8016c6a: 4d05 ldr r5, [pc, #20] @ (8016c80 <_read_r+0x20>) 8016c6c: 602a str r2, [r5, #0] 8016c6e: 461a mov r2, r3 8016c70: f7f7 f822 bl 800dcb8 <_read> 8016c74: 1c43 adds r3, r0, #1 8016c76: d102 bne.n 8016c7e <_read_r+0x1e> 8016c78: 682b ldr r3, [r5, #0] 8016c7a: b103 cbz r3, 8016c7e <_read_r+0x1e> 8016c7c: 6023 str r3, [r4, #0] 8016c7e: bd38 pop {r3, r4, r5, pc} 8016c80: 200015e8 .word 0x200015e8 08016c84 <_sbrk_r>: 8016c84: b538 push {r3, r4, r5, lr} 8016c86: 2300 movs r3, #0 8016c88: 4d05 ldr r5, [pc, #20] @ (8016ca0 <_sbrk_r+0x1c>) 8016c8a: 4604 mov r4, r0 8016c8c: 4608 mov r0, r1 8016c8e: 602b str r3, [r5, #0] 8016c90: f7f7 f860 bl 800dd54 <_sbrk> 8016c94: 1c43 adds r3, r0, #1 8016c96: d102 bne.n 8016c9e <_sbrk_r+0x1a> 8016c98: 682b ldr r3, [r5, #0] 8016c9a: b103 cbz r3, 8016c9e <_sbrk_r+0x1a> 8016c9c: 6023 str r3, [r4, #0] 8016c9e: bd38 pop {r3, r4, r5, pc} 8016ca0: 200015e8 .word 0x200015e8 08016ca4 <_write_r>: 8016ca4: b538 push {r3, r4, r5, lr} 8016ca6: 4604 mov r4, r0 8016ca8: 4608 mov r0, r1 8016caa: 4611 mov r1, r2 8016cac: 2200 movs r2, #0 8016cae: 4d05 ldr r5, [pc, #20] @ (8016cc4 <_write_r+0x20>) 8016cb0: 602a str r2, [r5, #0] 8016cb2: 461a mov r2, r3 8016cb4: f7f3 fb72 bl 800a39c <_write> 8016cb8: 1c43 adds r3, r0, #1 8016cba: d102 bne.n 8016cc2 <_write_r+0x1e> 8016cbc: 682b ldr r3, [r5, #0] 8016cbe: b103 cbz r3, 8016cc2 <_write_r+0x1e> 8016cc0: 6023 str r3, [r4, #0] 8016cc2: bd38 pop {r3, r4, r5, pc} 8016cc4: 200015e8 .word 0x200015e8 08016cc8 <_close_r>: 8016cc8: b538 push {r3, r4, r5, lr} 8016cca: 2300 movs r3, #0 8016ccc: 4d05 ldr r5, [pc, #20] @ (8016ce4 <_close_r+0x1c>) 8016cce: 4604 mov r4, r0 8016cd0: 4608 mov r0, r1 8016cd2: 602b str r3, [r5, #0] 8016cd4: f7f7 f80d bl 800dcf2 <_close> 8016cd8: 1c43 adds r3, r0, #1 8016cda: d102 bne.n 8016ce2 <_close_r+0x1a> 8016cdc: 682b ldr r3, [r5, #0] 8016cde: b103 cbz r3, 8016ce2 <_close_r+0x1a> 8016ce0: 6023 str r3, [r4, #0] 8016ce2: bd38 pop {r3, r4, r5, pc} 8016ce4: 200015e8 .word 0x200015e8 08016ce8 : 8016ce8: 2006 movs r0, #6 8016cea: b508 push {r3, lr} 8016cec: f000 fae4 bl 80172b8 8016cf0: 2001 movs r0, #1 8016cf2: f7f6 ffd6 bl 800dca2 <_exit> 08016cf6 <_calloc_r>: 8016cf6: b570 push {r4, r5, r6, lr} 8016cf8: fba1 5402 umull r5, r4, r1, r2 8016cfc: b934 cbnz r4, 8016d0c <_calloc_r+0x16> 8016cfe: 4629 mov r1, r5 8016d00: f7ff fa50 bl 80161a4 <_malloc_r> 8016d04: 4606 mov r6, r0 8016d06: b928 cbnz r0, 8016d14 <_calloc_r+0x1e> 8016d08: 4630 mov r0, r6 8016d0a: bd70 pop {r4, r5, r6, pc} 8016d0c: 220c movs r2, #12 8016d0e: 2600 movs r6, #0 8016d10: 6002 str r2, [r0, #0] 8016d12: e7f9 b.n 8016d08 <_calloc_r+0x12> 8016d14: 462a mov r2, r5 8016d16: 4621 mov r1, r4 8016d18: f7fe f9f0 bl 80150fc 8016d1c: e7f4 b.n 8016d08 <_calloc_r+0x12> ... 08016d20 <_free_r>: 8016d20: b538 push {r3, r4, r5, lr} 8016d22: 4605 mov r5, r0 8016d24: 2900 cmp r1, #0 8016d26: d040 beq.n 8016daa <_free_r+0x8a> 8016d28: f851 3c04 ldr.w r3, [r1, #-4] 8016d2c: 1f0c subs r4, r1, #4 8016d2e: 2b00 cmp r3, #0 8016d30: bfb8 it lt 8016d32: 18e4 addlt r4, r4, r3 8016d34: f7ff fb5e bl 80163f4 <__malloc_lock> 8016d38: 4a1c ldr r2, [pc, #112] @ (8016dac <_free_r+0x8c>) 8016d3a: 6813 ldr r3, [r2, #0] 8016d3c: b933 cbnz r3, 8016d4c <_free_r+0x2c> 8016d3e: 6063 str r3, [r4, #4] 8016d40: 6014 str r4, [r2, #0] 8016d42: 4628 mov r0, r5 8016d44: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8016d48: f7ff bb5a b.w 8016400 <__malloc_unlock> 8016d4c: 42a3 cmp r3, r4 8016d4e: d908 bls.n 8016d62 <_free_r+0x42> 8016d50: 6820 ldr r0, [r4, #0] 8016d52: 1821 adds r1, r4, r0 8016d54: 428b cmp r3, r1 8016d56: bf01 itttt eq 8016d58: 6819 ldreq r1, [r3, #0] 8016d5a: 685b ldreq r3, [r3, #4] 8016d5c: 1809 addeq r1, r1, r0 8016d5e: 6021 streq r1, [r4, #0] 8016d60: e7ed b.n 8016d3e <_free_r+0x1e> 8016d62: 461a mov r2, r3 8016d64: 685b ldr r3, [r3, #4] 8016d66: b10b cbz r3, 8016d6c <_free_r+0x4c> 8016d68: 42a3 cmp r3, r4 8016d6a: d9fa bls.n 8016d62 <_free_r+0x42> 8016d6c: 6811 ldr r1, [r2, #0] 8016d6e: 1850 adds r0, r2, r1 8016d70: 42a0 cmp r0, r4 8016d72: d10b bne.n 8016d8c <_free_r+0x6c> 8016d74: 6820 ldr r0, [r4, #0] 8016d76: 4401 add r1, r0 8016d78: 1850 adds r0, r2, r1 8016d7a: 4283 cmp r3, r0 8016d7c: 6011 str r1, [r2, #0] 8016d7e: d1e0 bne.n 8016d42 <_free_r+0x22> 8016d80: 6818 ldr r0, [r3, #0] 8016d82: 685b ldr r3, [r3, #4] 8016d84: 4408 add r0, r1 8016d86: 6010 str r0, [r2, #0] 8016d88: 6053 str r3, [r2, #4] 8016d8a: e7da b.n 8016d42 <_free_r+0x22> 8016d8c: d902 bls.n 8016d94 <_free_r+0x74> 8016d8e: 230c movs r3, #12 8016d90: 602b str r3, [r5, #0] 8016d92: e7d6 b.n 8016d42 <_free_r+0x22> 8016d94: 6820 ldr r0, [r4, #0] 8016d96: 1821 adds r1, r4, r0 8016d98: 428b cmp r3, r1 8016d9a: bf01 itttt eq 8016d9c: 6819 ldreq r1, [r3, #0] 8016d9e: 685b ldreq r3, [r3, #4] 8016da0: 1809 addeq r1, r1, r0 8016da2: 6021 streq r1, [r4, #0] 8016da4: 6063 str r3, [r4, #4] 8016da6: 6054 str r4, [r2, #4] 8016da8: e7cb b.n 8016d42 <_free_r+0x22> 8016daa: bd38 pop {r3, r4, r5, pc} 8016dac: 200015e4 .word 0x200015e4 08016db0 <__sfputc_r>: 8016db0: 6893 ldr r3, [r2, #8] 8016db2: b410 push {r4} 8016db4: 3b01 subs r3, #1 8016db6: 2b00 cmp r3, #0 8016db8: 6093 str r3, [r2, #8] 8016dba: da07 bge.n 8016dcc <__sfputc_r+0x1c> 8016dbc: 6994 ldr r4, [r2, #24] 8016dbe: 42a3 cmp r3, r4 8016dc0: db01 blt.n 8016dc6 <__sfputc_r+0x16> 8016dc2: 290a cmp r1, #10 8016dc4: d102 bne.n 8016dcc <__sfputc_r+0x1c> 8016dc6: bc10 pop {r4} 8016dc8: f000 b94c b.w 8017064 <__swbuf_r> 8016dcc: 6813 ldr r3, [r2, #0] 8016dce: 1c58 adds r0, r3, #1 8016dd0: 6010 str r0, [r2, #0] 8016dd2: 7019 strb r1, [r3, #0] 8016dd4: 4608 mov r0, r1 8016dd6: bc10 pop {r4} 8016dd8: 4770 bx lr 08016dda <__sfputs_r>: 8016dda: b5f8 push {r3, r4, r5, r6, r7, lr} 8016ddc: 4606 mov r6, r0 8016dde: 460f mov r7, r1 8016de0: 4614 mov r4, r2 8016de2: 18d5 adds r5, r2, r3 8016de4: 42ac cmp r4, r5 8016de6: d101 bne.n 8016dec <__sfputs_r+0x12> 8016de8: 2000 movs r0, #0 8016dea: e007 b.n 8016dfc <__sfputs_r+0x22> 8016dec: 463a mov r2, r7 8016dee: 4630 mov r0, r6 8016df0: f814 1b01 ldrb.w r1, [r4], #1 8016df4: f7ff ffdc bl 8016db0 <__sfputc_r> 8016df8: 1c43 adds r3, r0, #1 8016dfa: d1f3 bne.n 8016de4 <__sfputs_r+0xa> 8016dfc: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 08016e00 <_vfiprintf_r>: 8016e00: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8016e04: 460d mov r5, r1 8016e06: 4614 mov r4, r2 8016e08: 4698 mov r8, r3 8016e0a: 4606 mov r6, r0 8016e0c: b09d sub sp, #116 @ 0x74 8016e0e: b118 cbz r0, 8016e18 <_vfiprintf_r+0x18> 8016e10: 6a03 ldr r3, [r0, #32] 8016e12: b90b cbnz r3, 8016e18 <_vfiprintf_r+0x18> 8016e14: f7fe f900 bl 8015018 <__sinit> 8016e18: 6e6b ldr r3, [r5, #100] @ 0x64 8016e1a: 07d9 lsls r1, r3, #31 8016e1c: d405 bmi.n 8016e2a <_vfiprintf_r+0x2a> 8016e1e: 89ab ldrh r3, [r5, #12] 8016e20: 059a lsls r2, r3, #22 8016e22: d402 bmi.n 8016e2a <_vfiprintf_r+0x2a> 8016e24: 6da8 ldr r0, [r5, #88] @ 0x58 8016e26: f7fe f99c bl 8015162 <__retarget_lock_acquire_recursive> 8016e2a: 89ab ldrh r3, [r5, #12] 8016e2c: 071b lsls r3, r3, #28 8016e2e: d501 bpl.n 8016e34 <_vfiprintf_r+0x34> 8016e30: 692b ldr r3, [r5, #16] 8016e32: b99b cbnz r3, 8016e5c <_vfiprintf_r+0x5c> 8016e34: 4629 mov r1, r5 8016e36: 4630 mov r0, r6 8016e38: f000 f952 bl 80170e0 <__swsetup_r> 8016e3c: b170 cbz r0, 8016e5c <_vfiprintf_r+0x5c> 8016e3e: 6e6b ldr r3, [r5, #100] @ 0x64 8016e40: 07dc lsls r4, r3, #31 8016e42: d504 bpl.n 8016e4e <_vfiprintf_r+0x4e> 8016e44: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016e48: b01d add sp, #116 @ 0x74 8016e4a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8016e4e: 89ab ldrh r3, [r5, #12] 8016e50: 0598 lsls r0, r3, #22 8016e52: d4f7 bmi.n 8016e44 <_vfiprintf_r+0x44> 8016e54: 6da8 ldr r0, [r5, #88] @ 0x58 8016e56: f7fe f985 bl 8015164 <__retarget_lock_release_recursive> 8016e5a: e7f3 b.n 8016e44 <_vfiprintf_r+0x44> 8016e5c: 2300 movs r3, #0 8016e5e: 9309 str r3, [sp, #36] @ 0x24 8016e60: 2320 movs r3, #32 8016e62: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8016e66: 2330 movs r3, #48 @ 0x30 8016e68: f04f 0901 mov.w r9, #1 8016e6c: f8cd 800c str.w r8, [sp, #12] 8016e70: f8df 81a8 ldr.w r8, [pc, #424] @ 801701c <_vfiprintf_r+0x21c> 8016e74: f88d 302a strb.w r3, [sp, #42] @ 0x2a 8016e78: 4623 mov r3, r4 8016e7a: 469a mov sl, r3 8016e7c: f813 2b01 ldrb.w r2, [r3], #1 8016e80: b10a cbz r2, 8016e86 <_vfiprintf_r+0x86> 8016e82: 2a25 cmp r2, #37 @ 0x25 8016e84: d1f9 bne.n 8016e7a <_vfiprintf_r+0x7a> 8016e86: ebba 0b04 subs.w fp, sl, r4 8016e8a: d00b beq.n 8016ea4 <_vfiprintf_r+0xa4> 8016e8c: 465b mov r3, fp 8016e8e: 4622 mov r2, r4 8016e90: 4629 mov r1, r5 8016e92: 4630 mov r0, r6 8016e94: f7ff ffa1 bl 8016dda <__sfputs_r> 8016e98: 3001 adds r0, #1 8016e9a: f000 80a7 beq.w 8016fec <_vfiprintf_r+0x1ec> 8016e9e: 9a09 ldr r2, [sp, #36] @ 0x24 8016ea0: 445a add r2, fp 8016ea2: 9209 str r2, [sp, #36] @ 0x24 8016ea4: f89a 3000 ldrb.w r3, [sl] 8016ea8: 2b00 cmp r3, #0 8016eaa: f000 809f beq.w 8016fec <_vfiprintf_r+0x1ec> 8016eae: 2300 movs r3, #0 8016eb0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8016eb4: e9cd 2305 strd r2, r3, [sp, #20] 8016eb8: f10a 0a01 add.w sl, sl, #1 8016ebc: 9304 str r3, [sp, #16] 8016ebe: 9307 str r3, [sp, #28] 8016ec0: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8016ec4: 931a str r3, [sp, #104] @ 0x68 8016ec6: 4654 mov r4, sl 8016ec8: 2205 movs r2, #5 8016eca: f814 1b01 ldrb.w r1, [r4], #1 8016ece: 4853 ldr r0, [pc, #332] @ (801701c <_vfiprintf_r+0x21c>) 8016ed0: f7fe f94e bl 8015170 8016ed4: 9a04 ldr r2, [sp, #16] 8016ed6: b9d8 cbnz r0, 8016f10 <_vfiprintf_r+0x110> 8016ed8: 06d1 lsls r1, r2, #27 8016eda: bf44 itt mi 8016edc: 2320 movmi r3, #32 8016ede: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8016ee2: 0713 lsls r3, r2, #28 8016ee4: bf44 itt mi 8016ee6: 232b movmi r3, #43 @ 0x2b 8016ee8: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8016eec: f89a 3000 ldrb.w r3, [sl] 8016ef0: 2b2a cmp r3, #42 @ 0x2a 8016ef2: d015 beq.n 8016f20 <_vfiprintf_r+0x120> 8016ef4: 4654 mov r4, sl 8016ef6: 2000 movs r0, #0 8016ef8: f04f 0c0a mov.w ip, #10 8016efc: 9a07 ldr r2, [sp, #28] 8016efe: 4621 mov r1, r4 8016f00: f811 3b01 ldrb.w r3, [r1], #1 8016f04: 3b30 subs r3, #48 @ 0x30 8016f06: 2b09 cmp r3, #9 8016f08: d94b bls.n 8016fa2 <_vfiprintf_r+0x1a2> 8016f0a: b1b0 cbz r0, 8016f3a <_vfiprintf_r+0x13a> 8016f0c: 9207 str r2, [sp, #28] 8016f0e: e014 b.n 8016f3a <_vfiprintf_r+0x13a> 8016f10: eba0 0308 sub.w r3, r0, r8 8016f14: fa09 f303 lsl.w r3, r9, r3 8016f18: 4313 orrs r3, r2 8016f1a: 46a2 mov sl, r4 8016f1c: 9304 str r3, [sp, #16] 8016f1e: e7d2 b.n 8016ec6 <_vfiprintf_r+0xc6> 8016f20: 9b03 ldr r3, [sp, #12] 8016f22: 1d19 adds r1, r3, #4 8016f24: 681b ldr r3, [r3, #0] 8016f26: 9103 str r1, [sp, #12] 8016f28: 2b00 cmp r3, #0 8016f2a: bfbb ittet lt 8016f2c: 425b neglt r3, r3 8016f2e: f042 0202 orrlt.w r2, r2, #2 8016f32: 9307 strge r3, [sp, #28] 8016f34: 9307 strlt r3, [sp, #28] 8016f36: bfb8 it lt 8016f38: 9204 strlt r2, [sp, #16] 8016f3a: 7823 ldrb r3, [r4, #0] 8016f3c: 2b2e cmp r3, #46 @ 0x2e 8016f3e: d10a bne.n 8016f56 <_vfiprintf_r+0x156> 8016f40: 7863 ldrb r3, [r4, #1] 8016f42: 2b2a cmp r3, #42 @ 0x2a 8016f44: d132 bne.n 8016fac <_vfiprintf_r+0x1ac> 8016f46: 9b03 ldr r3, [sp, #12] 8016f48: 3402 adds r4, #2 8016f4a: 1d1a adds r2, r3, #4 8016f4c: 681b ldr r3, [r3, #0] 8016f4e: 9203 str r2, [sp, #12] 8016f50: ea43 73e3 orr.w r3, r3, r3, asr #31 8016f54: 9305 str r3, [sp, #20] 8016f56: f8df a0c8 ldr.w sl, [pc, #200] @ 8017020 <_vfiprintf_r+0x220> 8016f5a: 2203 movs r2, #3 8016f5c: 4650 mov r0, sl 8016f5e: 7821 ldrb r1, [r4, #0] 8016f60: f7fe f906 bl 8015170 8016f64: b138 cbz r0, 8016f76 <_vfiprintf_r+0x176> 8016f66: 2240 movs r2, #64 @ 0x40 8016f68: 9b04 ldr r3, [sp, #16] 8016f6a: eba0 000a sub.w r0, r0, sl 8016f6e: 4082 lsls r2, r0 8016f70: 4313 orrs r3, r2 8016f72: 3401 adds r4, #1 8016f74: 9304 str r3, [sp, #16] 8016f76: f814 1b01 ldrb.w r1, [r4], #1 8016f7a: 2206 movs r2, #6 8016f7c: 4829 ldr r0, [pc, #164] @ (8017024 <_vfiprintf_r+0x224>) 8016f7e: f88d 1028 strb.w r1, [sp, #40] @ 0x28 8016f82: f7fe f8f5 bl 8015170 8016f86: 2800 cmp r0, #0 8016f88: d03f beq.n 801700a <_vfiprintf_r+0x20a> 8016f8a: 4b27 ldr r3, [pc, #156] @ (8017028 <_vfiprintf_r+0x228>) 8016f8c: bb1b cbnz r3, 8016fd6 <_vfiprintf_r+0x1d6> 8016f8e: 9b03 ldr r3, [sp, #12] 8016f90: 3307 adds r3, #7 8016f92: f023 0307 bic.w r3, r3, #7 8016f96: 3308 adds r3, #8 8016f98: 9303 str r3, [sp, #12] 8016f9a: 9b09 ldr r3, [sp, #36] @ 0x24 8016f9c: 443b add r3, r7 8016f9e: 9309 str r3, [sp, #36] @ 0x24 8016fa0: e76a b.n 8016e78 <_vfiprintf_r+0x78> 8016fa2: 460c mov r4, r1 8016fa4: 2001 movs r0, #1 8016fa6: fb0c 3202 mla r2, ip, r2, r3 8016faa: e7a8 b.n 8016efe <_vfiprintf_r+0xfe> 8016fac: 2300 movs r3, #0 8016fae: f04f 0c0a mov.w ip, #10 8016fb2: 4619 mov r1, r3 8016fb4: 3401 adds r4, #1 8016fb6: 9305 str r3, [sp, #20] 8016fb8: 4620 mov r0, r4 8016fba: f810 2b01 ldrb.w r2, [r0], #1 8016fbe: 3a30 subs r2, #48 @ 0x30 8016fc0: 2a09 cmp r2, #9 8016fc2: d903 bls.n 8016fcc <_vfiprintf_r+0x1cc> 8016fc4: 2b00 cmp r3, #0 8016fc6: d0c6 beq.n 8016f56 <_vfiprintf_r+0x156> 8016fc8: 9105 str r1, [sp, #20] 8016fca: e7c4 b.n 8016f56 <_vfiprintf_r+0x156> 8016fcc: 4604 mov r4, r0 8016fce: 2301 movs r3, #1 8016fd0: fb0c 2101 mla r1, ip, r1, r2 8016fd4: e7f0 b.n 8016fb8 <_vfiprintf_r+0x1b8> 8016fd6: ab03 add r3, sp, #12 8016fd8: 9300 str r3, [sp, #0] 8016fda: 462a mov r2, r5 8016fdc: 4630 mov r0, r6 8016fde: 4b13 ldr r3, [pc, #76] @ (801702c <_vfiprintf_r+0x22c>) 8016fe0: a904 add r1, sp, #16 8016fe2: f7fd fbd1 bl 8014788 <_printf_float> 8016fe6: 4607 mov r7, r0 8016fe8: 1c78 adds r0, r7, #1 8016fea: d1d6 bne.n 8016f9a <_vfiprintf_r+0x19a> 8016fec: 6e6b ldr r3, [r5, #100] @ 0x64 8016fee: 07d9 lsls r1, r3, #31 8016ff0: d405 bmi.n 8016ffe <_vfiprintf_r+0x1fe> 8016ff2: 89ab ldrh r3, [r5, #12] 8016ff4: 059a lsls r2, r3, #22 8016ff6: d402 bmi.n 8016ffe <_vfiprintf_r+0x1fe> 8016ff8: 6da8 ldr r0, [r5, #88] @ 0x58 8016ffa: f7fe f8b3 bl 8015164 <__retarget_lock_release_recursive> 8016ffe: 89ab ldrh r3, [r5, #12] 8017000: 065b lsls r3, r3, #25 8017002: f53f af1f bmi.w 8016e44 <_vfiprintf_r+0x44> 8017006: 9809 ldr r0, [sp, #36] @ 0x24 8017008: e71e b.n 8016e48 <_vfiprintf_r+0x48> 801700a: ab03 add r3, sp, #12 801700c: 9300 str r3, [sp, #0] 801700e: 462a mov r2, r5 8017010: 4630 mov r0, r6 8017012: 4b06 ldr r3, [pc, #24] @ (801702c <_vfiprintf_r+0x22c>) 8017014: a904 add r1, sp, #16 8017016: f7fd fe55 bl 8014cc4 <_printf_i> 801701a: e7e4 b.n 8016fe6 <_vfiprintf_r+0x1e6> 801701c: 08017eb9 .word 0x08017eb9 8017020: 08017ebf .word 0x08017ebf 8017024: 08017ec3 .word 0x08017ec3 8017028: 08014789 .word 0x08014789 801702c: 08016ddb .word 0x08016ddb 08017030 <__ascii_mbtowc>: 8017030: b082 sub sp, #8 8017032: b901 cbnz r1, 8017036 <__ascii_mbtowc+0x6> 8017034: a901 add r1, sp, #4 8017036: b142 cbz r2, 801704a <__ascii_mbtowc+0x1a> 8017038: b14b cbz r3, 801704e <__ascii_mbtowc+0x1e> 801703a: 7813 ldrb r3, [r2, #0] 801703c: 600b str r3, [r1, #0] 801703e: 7812 ldrb r2, [r2, #0] 8017040: 1e10 subs r0, r2, #0 8017042: bf18 it ne 8017044: 2001 movne r0, #1 8017046: b002 add sp, #8 8017048: 4770 bx lr 801704a: 4610 mov r0, r2 801704c: e7fb b.n 8017046 <__ascii_mbtowc+0x16> 801704e: f06f 0001 mvn.w r0, #1 8017052: e7f8 b.n 8017046 <__ascii_mbtowc+0x16> 08017054 <_malloc_usable_size_r>: 8017054: f851 3c04 ldr.w r3, [r1, #-4] 8017058: 1f18 subs r0, r3, #4 801705a: 2b00 cmp r3, #0 801705c: bfbc itt lt 801705e: 580b ldrlt r3, [r1, r0] 8017060: 18c0 addlt r0, r0, r3 8017062: 4770 bx lr 08017064 <__swbuf_r>: 8017064: b5f8 push {r3, r4, r5, r6, r7, lr} 8017066: 460e mov r6, r1 8017068: 4614 mov r4, r2 801706a: 4605 mov r5, r0 801706c: b118 cbz r0, 8017076 <__swbuf_r+0x12> 801706e: 6a03 ldr r3, [r0, #32] 8017070: b90b cbnz r3, 8017076 <__swbuf_r+0x12> 8017072: f7fd ffd1 bl 8015018 <__sinit> 8017076: 69a3 ldr r3, [r4, #24] 8017078: 60a3 str r3, [r4, #8] 801707a: 89a3 ldrh r3, [r4, #12] 801707c: 071a lsls r2, r3, #28 801707e: d501 bpl.n 8017084 <__swbuf_r+0x20> 8017080: 6923 ldr r3, [r4, #16] 8017082: b943 cbnz r3, 8017096 <__swbuf_r+0x32> 8017084: 4621 mov r1, r4 8017086: 4628 mov r0, r5 8017088: f000 f82a bl 80170e0 <__swsetup_r> 801708c: b118 cbz r0, 8017096 <__swbuf_r+0x32> 801708e: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff 8017092: 4638 mov r0, r7 8017094: bdf8 pop {r3, r4, r5, r6, r7, pc} 8017096: 6823 ldr r3, [r4, #0] 8017098: 6922 ldr r2, [r4, #16] 801709a: b2f6 uxtb r6, r6 801709c: 1a98 subs r0, r3, r2 801709e: 6963 ldr r3, [r4, #20] 80170a0: 4637 mov r7, r6 80170a2: 4283 cmp r3, r0 80170a4: dc05 bgt.n 80170b2 <__swbuf_r+0x4e> 80170a6: 4621 mov r1, r4 80170a8: 4628 mov r0, r5 80170aa: f7ff f97b bl 80163a4 <_fflush_r> 80170ae: 2800 cmp r0, #0 80170b0: d1ed bne.n 801708e <__swbuf_r+0x2a> 80170b2: 68a3 ldr r3, [r4, #8] 80170b4: 3b01 subs r3, #1 80170b6: 60a3 str r3, [r4, #8] 80170b8: 6823 ldr r3, [r4, #0] 80170ba: 1c5a adds r2, r3, #1 80170bc: 6022 str r2, [r4, #0] 80170be: 701e strb r6, [r3, #0] 80170c0: 6962 ldr r2, [r4, #20] 80170c2: 1c43 adds r3, r0, #1 80170c4: 429a cmp r2, r3 80170c6: d004 beq.n 80170d2 <__swbuf_r+0x6e> 80170c8: 89a3 ldrh r3, [r4, #12] 80170ca: 07db lsls r3, r3, #31 80170cc: d5e1 bpl.n 8017092 <__swbuf_r+0x2e> 80170ce: 2e0a cmp r6, #10 80170d0: d1df bne.n 8017092 <__swbuf_r+0x2e> 80170d2: 4621 mov r1, r4 80170d4: 4628 mov r0, r5 80170d6: f7ff f965 bl 80163a4 <_fflush_r> 80170da: 2800 cmp r0, #0 80170dc: d0d9 beq.n 8017092 <__swbuf_r+0x2e> 80170de: e7d6 b.n 801708e <__swbuf_r+0x2a> 080170e0 <__swsetup_r>: 80170e0: b538 push {r3, r4, r5, lr} 80170e2: 4b29 ldr r3, [pc, #164] @ (8017188 <__swsetup_r+0xa8>) 80170e4: 4605 mov r5, r0 80170e6: 6818 ldr r0, [r3, #0] 80170e8: 460c mov r4, r1 80170ea: b118 cbz r0, 80170f4 <__swsetup_r+0x14> 80170ec: 6a03 ldr r3, [r0, #32] 80170ee: b90b cbnz r3, 80170f4 <__swsetup_r+0x14> 80170f0: f7fd ff92 bl 8015018 <__sinit> 80170f4: f9b4 300c ldrsh.w r3, [r4, #12] 80170f8: 0719 lsls r1, r3, #28 80170fa: d422 bmi.n 8017142 <__swsetup_r+0x62> 80170fc: 06da lsls r2, r3, #27 80170fe: d407 bmi.n 8017110 <__swsetup_r+0x30> 8017100: 2209 movs r2, #9 8017102: 602a str r2, [r5, #0] 8017104: f043 0340 orr.w r3, r3, #64 @ 0x40 8017108: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801710c: 81a3 strh r3, [r4, #12] 801710e: e033 b.n 8017178 <__swsetup_r+0x98> 8017110: 0758 lsls r0, r3, #29 8017112: d512 bpl.n 801713a <__swsetup_r+0x5a> 8017114: 6b61 ldr r1, [r4, #52] @ 0x34 8017116: b141 cbz r1, 801712a <__swsetup_r+0x4a> 8017118: f104 0344 add.w r3, r4, #68 @ 0x44 801711c: 4299 cmp r1, r3 801711e: d002 beq.n 8017126 <__swsetup_r+0x46> 8017120: 4628 mov r0, r5 8017122: f7ff fdfd bl 8016d20 <_free_r> 8017126: 2300 movs r3, #0 8017128: 6363 str r3, [r4, #52] @ 0x34 801712a: 89a3 ldrh r3, [r4, #12] 801712c: f023 0324 bic.w r3, r3, #36 @ 0x24 8017130: 81a3 strh r3, [r4, #12] 8017132: 2300 movs r3, #0 8017134: 6063 str r3, [r4, #4] 8017136: 6923 ldr r3, [r4, #16] 8017138: 6023 str r3, [r4, #0] 801713a: 89a3 ldrh r3, [r4, #12] 801713c: f043 0308 orr.w r3, r3, #8 8017140: 81a3 strh r3, [r4, #12] 8017142: 6923 ldr r3, [r4, #16] 8017144: b94b cbnz r3, 801715a <__swsetup_r+0x7a> 8017146: 89a3 ldrh r3, [r4, #12] 8017148: f403 7320 and.w r3, r3, #640 @ 0x280 801714c: f5b3 7f00 cmp.w r3, #512 @ 0x200 8017150: d003 beq.n 801715a <__swsetup_r+0x7a> 8017152: 4621 mov r1, r4 8017154: 4628 mov r0, r5 8017156: f000 f84b bl 80171f0 <__smakebuf_r> 801715a: f9b4 300c ldrsh.w r3, [r4, #12] 801715e: f013 0201 ands.w r2, r3, #1 8017162: d00a beq.n 801717a <__swsetup_r+0x9a> 8017164: 2200 movs r2, #0 8017166: 60a2 str r2, [r4, #8] 8017168: 6962 ldr r2, [r4, #20] 801716a: 4252 negs r2, r2 801716c: 61a2 str r2, [r4, #24] 801716e: 6922 ldr r2, [r4, #16] 8017170: b942 cbnz r2, 8017184 <__swsetup_r+0xa4> 8017172: f013 0080 ands.w r0, r3, #128 @ 0x80 8017176: d1c5 bne.n 8017104 <__swsetup_r+0x24> 8017178: bd38 pop {r3, r4, r5, pc} 801717a: 0799 lsls r1, r3, #30 801717c: bf58 it pl 801717e: 6962 ldrpl r2, [r4, #20] 8017180: 60a2 str r2, [r4, #8] 8017182: e7f4 b.n 801716e <__swsetup_r+0x8e> 8017184: 2000 movs r0, #0 8017186: e7f7 b.n 8017178 <__swsetup_r+0x98> 8017188: 2000009c .word 0x2000009c 0801718c <__ascii_wctomb>: 801718c: 4603 mov r3, r0 801718e: 4608 mov r0, r1 8017190: b141 cbz r1, 80171a4 <__ascii_wctomb+0x18> 8017192: 2aff cmp r2, #255 @ 0xff 8017194: d904 bls.n 80171a0 <__ascii_wctomb+0x14> 8017196: 228a movs r2, #138 @ 0x8a 8017198: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801719c: 601a str r2, [r3, #0] 801719e: 4770 bx lr 80171a0: 2001 movs r0, #1 80171a2: 700a strb r2, [r1, #0] 80171a4: 4770 bx lr 080171a6 <__swhatbuf_r>: 80171a6: b570 push {r4, r5, r6, lr} 80171a8: 460c mov r4, r1 80171aa: f9b1 100e ldrsh.w r1, [r1, #14] 80171ae: 4615 mov r5, r2 80171b0: 2900 cmp r1, #0 80171b2: 461e mov r6, r3 80171b4: b096 sub sp, #88 @ 0x58 80171b6: da0c bge.n 80171d2 <__swhatbuf_r+0x2c> 80171b8: 89a3 ldrh r3, [r4, #12] 80171ba: 2100 movs r1, #0 80171bc: f013 0f80 tst.w r3, #128 @ 0x80 80171c0: bf14 ite ne 80171c2: 2340 movne r3, #64 @ 0x40 80171c4: f44f 6380 moveq.w r3, #1024 @ 0x400 80171c8: 2000 movs r0, #0 80171ca: 6031 str r1, [r6, #0] 80171cc: 602b str r3, [r5, #0] 80171ce: b016 add sp, #88 @ 0x58 80171d0: bd70 pop {r4, r5, r6, pc} 80171d2: 466a mov r2, sp 80171d4: f000 f89c bl 8017310 <_fstat_r> 80171d8: 2800 cmp r0, #0 80171da: dbed blt.n 80171b8 <__swhatbuf_r+0x12> 80171dc: 9901 ldr r1, [sp, #4] 80171de: f401 4170 and.w r1, r1, #61440 @ 0xf000 80171e2: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 80171e6: 4259 negs r1, r3 80171e8: 4159 adcs r1, r3 80171ea: f44f 6380 mov.w r3, #1024 @ 0x400 80171ee: e7eb b.n 80171c8 <__swhatbuf_r+0x22> 080171f0 <__smakebuf_r>: 80171f0: 898b ldrh r3, [r1, #12] 80171f2: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 80171f4: 079d lsls r5, r3, #30 80171f6: 4606 mov r6, r0 80171f8: 460c mov r4, r1 80171fa: d507 bpl.n 801720c <__smakebuf_r+0x1c> 80171fc: f104 0347 add.w r3, r4, #71 @ 0x47 8017200: 6023 str r3, [r4, #0] 8017202: 6123 str r3, [r4, #16] 8017204: 2301 movs r3, #1 8017206: 6163 str r3, [r4, #20] 8017208: b003 add sp, #12 801720a: bdf0 pop {r4, r5, r6, r7, pc} 801720c: 466a mov r2, sp 801720e: ab01 add r3, sp, #4 8017210: f7ff ffc9 bl 80171a6 <__swhatbuf_r> 8017214: 9f00 ldr r7, [sp, #0] 8017216: 4605 mov r5, r0 8017218: 4639 mov r1, r7 801721a: 4630 mov r0, r6 801721c: f7fe ffc2 bl 80161a4 <_malloc_r> 8017220: b948 cbnz r0, 8017236 <__smakebuf_r+0x46> 8017222: f9b4 300c ldrsh.w r3, [r4, #12] 8017226: 059a lsls r2, r3, #22 8017228: d4ee bmi.n 8017208 <__smakebuf_r+0x18> 801722a: f023 0303 bic.w r3, r3, #3 801722e: f043 0302 orr.w r3, r3, #2 8017232: 81a3 strh r3, [r4, #12] 8017234: e7e2 b.n 80171fc <__smakebuf_r+0xc> 8017236: 89a3 ldrh r3, [r4, #12] 8017238: e9c4 0704 strd r0, r7, [r4, #16] 801723c: f043 0380 orr.w r3, r3, #128 @ 0x80 8017240: 81a3 strh r3, [r4, #12] 8017242: 9b01 ldr r3, [sp, #4] 8017244: 6020 str r0, [r4, #0] 8017246: b15b cbz r3, 8017260 <__smakebuf_r+0x70> 8017248: 4630 mov r0, r6 801724a: f9b4 100e ldrsh.w r1, [r4, #14] 801724e: f000 f83b bl 80172c8 <_isatty_r> 8017252: b128 cbz r0, 8017260 <__smakebuf_r+0x70> 8017254: 89a3 ldrh r3, [r4, #12] 8017256: f023 0303 bic.w r3, r3, #3 801725a: f043 0301 orr.w r3, r3, #1 801725e: 81a3 strh r3, [r4, #12] 8017260: 89a3 ldrh r3, [r4, #12] 8017262: 431d orrs r5, r3 8017264: 81a5 strh r5, [r4, #12] 8017266: e7cf b.n 8017208 <__smakebuf_r+0x18> 08017268 <_raise_r>: 8017268: 291f cmp r1, #31 801726a: b538 push {r3, r4, r5, lr} 801726c: 4605 mov r5, r0 801726e: 460c mov r4, r1 8017270: d904 bls.n 801727c <_raise_r+0x14> 8017272: 2316 movs r3, #22 8017274: 6003 str r3, [r0, #0] 8017276: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801727a: bd38 pop {r3, r4, r5, pc} 801727c: 6bc2 ldr r2, [r0, #60] @ 0x3c 801727e: b112 cbz r2, 8017286 <_raise_r+0x1e> 8017280: f852 3021 ldr.w r3, [r2, r1, lsl #2] 8017284: b94b cbnz r3, 801729a <_raise_r+0x32> 8017286: 4628 mov r0, r5 8017288: f000 f840 bl 801730c <_getpid_r> 801728c: 4622 mov r2, r4 801728e: 4601 mov r1, r0 8017290: 4628 mov r0, r5 8017292: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8017296: f000 b827 b.w 80172e8 <_kill_r> 801729a: 2b01 cmp r3, #1 801729c: d00a beq.n 80172b4 <_raise_r+0x4c> 801729e: 1c59 adds r1, r3, #1 80172a0: d103 bne.n 80172aa <_raise_r+0x42> 80172a2: 2316 movs r3, #22 80172a4: 6003 str r3, [r0, #0] 80172a6: 2001 movs r0, #1 80172a8: e7e7 b.n 801727a <_raise_r+0x12> 80172aa: 2100 movs r1, #0 80172ac: 4620 mov r0, r4 80172ae: f842 1024 str.w r1, [r2, r4, lsl #2] 80172b2: 4798 blx r3 80172b4: 2000 movs r0, #0 80172b6: e7e0 b.n 801727a <_raise_r+0x12> 080172b8 : 80172b8: 4b02 ldr r3, [pc, #8] @ (80172c4 ) 80172ba: 4601 mov r1, r0 80172bc: 6818 ldr r0, [r3, #0] 80172be: f7ff bfd3 b.w 8017268 <_raise_r> 80172c2: bf00 nop 80172c4: 2000009c .word 0x2000009c 080172c8 <_isatty_r>: 80172c8: b538 push {r3, r4, r5, lr} 80172ca: 2300 movs r3, #0 80172cc: 4d05 ldr r5, [pc, #20] @ (80172e4 <_isatty_r+0x1c>) 80172ce: 4604 mov r4, r0 80172d0: 4608 mov r0, r1 80172d2: 602b str r3, [r5, #0] 80172d4: f7f6 fd27 bl 800dd26 <_isatty> 80172d8: 1c43 adds r3, r0, #1 80172da: d102 bne.n 80172e2 <_isatty_r+0x1a> 80172dc: 682b ldr r3, [r5, #0] 80172de: b103 cbz r3, 80172e2 <_isatty_r+0x1a> 80172e0: 6023 str r3, [r4, #0] 80172e2: bd38 pop {r3, r4, r5, pc} 80172e4: 200015e8 .word 0x200015e8 080172e8 <_kill_r>: 80172e8: b538 push {r3, r4, r5, lr} 80172ea: 2300 movs r3, #0 80172ec: 4d06 ldr r5, [pc, #24] @ (8017308 <_kill_r+0x20>) 80172ee: 4604 mov r4, r0 80172f0: 4608 mov r0, r1 80172f2: 4611 mov r1, r2 80172f4: 602b str r3, [r5, #0] 80172f6: f7f6 fcc4 bl 800dc82 <_kill> 80172fa: 1c43 adds r3, r0, #1 80172fc: d102 bne.n 8017304 <_kill_r+0x1c> 80172fe: 682b ldr r3, [r5, #0] 8017300: b103 cbz r3, 8017304 <_kill_r+0x1c> 8017302: 6023 str r3, [r4, #0] 8017304: bd38 pop {r3, r4, r5, pc} 8017306: bf00 nop 8017308: 200015e8 .word 0x200015e8 0801730c <_getpid_r>: 801730c: f7f6 bcb2 b.w 800dc74 <_getpid> 08017310 <_fstat_r>: 8017310: b538 push {r3, r4, r5, lr} 8017312: 2300 movs r3, #0 8017314: 4d06 ldr r5, [pc, #24] @ (8017330 <_fstat_r+0x20>) 8017316: 4604 mov r4, r0 8017318: 4608 mov r0, r1 801731a: 4611 mov r1, r2 801731c: 602b str r3, [r5, #0] 801731e: f7f6 fcf3 bl 800dd08 <_fstat> 8017322: 1c43 adds r3, r0, #1 8017324: d102 bne.n 801732c <_fstat_r+0x1c> 8017326: 682b ldr r3, [r5, #0] 8017328: b103 cbz r3, 801732c <_fstat_r+0x1c> 801732a: 6023 str r3, [r4, #0] 801732c: bd38 pop {r3, r4, r5, pc} 801732e: bf00 nop 8017330: 200015e8 .word 0x200015e8 08017334 <_init>: 8017334: b5f8 push {r3, r4, r5, r6, r7, lr} 8017336: bf00 nop 8017338: bcf8 pop {r3, r4, r5, r6, r7} 801733a: bc08 pop {r3} 801733c: 469e mov lr, r3 801733e: 4770 bx lr 08017340 <_fini>: 8017340: b5f8 push {r3, r4, r5, r6, r7, lr} 8017342: bf00 nop 8017344: bcf8 pop {r3, r4, r5, r6, r7} 8017346: bc08 pop {r3} 8017348: 469e mov lr, r3 801734a: 4770 bx lr