GbTModuleSW.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001e4 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000caa0 080001e8 080001e8 000101e8 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000b6c 0800cc88 0800cc88 0001cc88 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 0800d7f4 0800d7f4 00020244 2**0 CONTENTS 4 .ARM 00000008 0800d7f4 0800d7f4 0001d7f4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 0800d7fc 0800d7fc 00020244 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0800d7fc 0800d7fc 0001d7fc 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 0800d800 0800d800 0001d800 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000244 20000000 0800d804 00020000 2**3 CONTENTS, ALLOC, LOAD, DATA 9 .bss 0000318c 20000244 0800da48 00020244 2**2 ALLOC 10 ._user_heap_stack 00000600 200033d0 0800da48 000233d0 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 00020244 2**0 CONTENTS, READONLY 12 .debug_info 0001235b 00000000 00000000 0002026d 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 0000409f 00000000 00000000 000325c8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00001098 00000000 00000000 00036668 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 00000ed8 00000000 00000000 00037700 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00024996 00000000 00000000 000385d8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 00017e64 00000000 00000000 0005cf6e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000bf7e8 00000000 00000000 00074dd2 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000050 00000000 00000000 001345ba 2**0 CONTENTS, READONLY 20 .debug_frame 0000581c 00000000 00000000 0013460c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001e8 <__do_global_dtors_aux>: 80001e8: b510 push {r4, lr} 80001ea: 4c05 ldr r4, [pc, #20] ; (8000200 <__do_global_dtors_aux+0x18>) 80001ec: 7823 ldrb r3, [r4, #0] 80001ee: b933 cbnz r3, 80001fe <__do_global_dtors_aux+0x16> 80001f0: 4b04 ldr r3, [pc, #16] ; (8000204 <__do_global_dtors_aux+0x1c>) 80001f2: b113 cbz r3, 80001fa <__do_global_dtors_aux+0x12> 80001f4: 4804 ldr r0, [pc, #16] ; (8000208 <__do_global_dtors_aux+0x20>) 80001f6: f3af 8000 nop.w 80001fa: 2301 movs r3, #1 80001fc: 7023 strb r3, [r4, #0] 80001fe: bd10 pop {r4, pc} 8000200: 20000244 .word 0x20000244 8000204: 00000000 .word 0x00000000 8000208: 0800cc70 .word 0x0800cc70 0800020c : 800020c: b508 push {r3, lr} 800020e: 4b03 ldr r3, [pc, #12] ; (800021c ) 8000210: b11b cbz r3, 800021a 8000212: 4903 ldr r1, [pc, #12] ; (8000220 ) 8000214: 4803 ldr r0, [pc, #12] ; (8000224 ) 8000216: f3af 8000 nop.w 800021a: bd08 pop {r3, pc} 800021c: 00000000 .word 0x00000000 8000220: 20000248 .word 0x20000248 8000224: 0800cc70 .word 0x0800cc70 08000228 : 8000228: 4603 mov r3, r0 800022a: f813 2b01 ldrb.w r2, [r3], #1 800022e: 2a00 cmp r2, #0 8000230: d1fb bne.n 800022a 8000232: 1a18 subs r0, r3, r0 8000234: 3801 subs r0, #1 8000236: 4770 bx lr 08000238 : 8000238: f810 2b01 ldrb.w r2, [r0], #1 800023c: f811 3b01 ldrb.w r3, [r1], #1 8000240: 2a01 cmp r2, #1 8000242: bf28 it cs 8000244: 429a cmpcs r2, r3 8000246: d0f7 beq.n 8000238 8000248: 1ad0 subs r0, r2, r3 800024a: 4770 bx lr 0800024c <__aeabi_drsub>: 800024c: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 8000250: e002 b.n 8000258 <__adddf3> 8000252: bf00 nop 08000254 <__aeabi_dsub>: 8000254: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 08000258 <__adddf3>: 8000258: b530 push {r4, r5, lr} 800025a: ea4f 0441 mov.w r4, r1, lsl #1 800025e: ea4f 0543 mov.w r5, r3, lsl #1 8000262: ea94 0f05 teq r4, r5 8000266: bf08 it eq 8000268: ea90 0f02 teqeq r0, r2 800026c: bf1f itttt ne 800026e: ea54 0c00 orrsne.w ip, r4, r0 8000272: ea55 0c02 orrsne.w ip, r5, r2 8000276: ea7f 5c64 mvnsne.w ip, r4, asr #21 800027a: ea7f 5c65 mvnsne.w ip, r5, asr #21 800027e: f000 80e2 beq.w 8000446 <__adddf3+0x1ee> 8000282: ea4f 5454 mov.w r4, r4, lsr #21 8000286: ebd4 5555 rsbs r5, r4, r5, lsr #21 800028a: bfb8 it lt 800028c: 426d neglt r5, r5 800028e: dd0c ble.n 80002aa <__adddf3+0x52> 8000290: 442c add r4, r5 8000292: ea80 0202 eor.w r2, r0, r2 8000296: ea81 0303 eor.w r3, r1, r3 800029a: ea82 0000 eor.w r0, r2, r0 800029e: ea83 0101 eor.w r1, r3, r1 80002a2: ea80 0202 eor.w r2, r0, r2 80002a6: ea81 0303 eor.w r3, r1, r3 80002aa: 2d36 cmp r5, #54 ; 0x36 80002ac: bf88 it hi 80002ae: bd30 pophi {r4, r5, pc} 80002b0: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 80002b4: ea4f 3101 mov.w r1, r1, lsl #12 80002b8: f44f 1c80 mov.w ip, #1048576 ; 0x100000 80002bc: ea4c 3111 orr.w r1, ip, r1, lsr #12 80002c0: d002 beq.n 80002c8 <__adddf3+0x70> 80002c2: 4240 negs r0, r0 80002c4: eb61 0141 sbc.w r1, r1, r1, lsl #1 80002c8: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 80002cc: ea4f 3303 mov.w r3, r3, lsl #12 80002d0: ea4c 3313 orr.w r3, ip, r3, lsr #12 80002d4: d002 beq.n 80002dc <__adddf3+0x84> 80002d6: 4252 negs r2, r2 80002d8: eb63 0343 sbc.w r3, r3, r3, lsl #1 80002dc: ea94 0f05 teq r4, r5 80002e0: f000 80a7 beq.w 8000432 <__adddf3+0x1da> 80002e4: f1a4 0401 sub.w r4, r4, #1 80002e8: f1d5 0e20 rsbs lr, r5, #32 80002ec: db0d blt.n 800030a <__adddf3+0xb2> 80002ee: fa02 fc0e lsl.w ip, r2, lr 80002f2: fa22 f205 lsr.w r2, r2, r5 80002f6: 1880 adds r0, r0, r2 80002f8: f141 0100 adc.w r1, r1, #0 80002fc: fa03 f20e lsl.w r2, r3, lr 8000300: 1880 adds r0, r0, r2 8000302: fa43 f305 asr.w r3, r3, r5 8000306: 4159 adcs r1, r3 8000308: e00e b.n 8000328 <__adddf3+0xd0> 800030a: f1a5 0520 sub.w r5, r5, #32 800030e: f10e 0e20 add.w lr, lr, #32 8000312: 2a01 cmp r2, #1 8000314: fa03 fc0e lsl.w ip, r3, lr 8000318: bf28 it cs 800031a: f04c 0c02 orrcs.w ip, ip, #2 800031e: fa43 f305 asr.w r3, r3, r5 8000322: 18c0 adds r0, r0, r3 8000324: eb51 71e3 adcs.w r1, r1, r3, asr #31 8000328: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 800032c: d507 bpl.n 800033e <__adddf3+0xe6> 800032e: f04f 0e00 mov.w lr, #0 8000332: f1dc 0c00 rsbs ip, ip, #0 8000336: eb7e 0000 sbcs.w r0, lr, r0 800033a: eb6e 0101 sbc.w r1, lr, r1 800033e: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 8000342: d31b bcc.n 800037c <__adddf3+0x124> 8000344: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 8000348: d30c bcc.n 8000364 <__adddf3+0x10c> 800034a: 0849 lsrs r1, r1, #1 800034c: ea5f 0030 movs.w r0, r0, rrx 8000350: ea4f 0c3c mov.w ip, ip, rrx 8000354: f104 0401 add.w r4, r4, #1 8000358: ea4f 5244 mov.w r2, r4, lsl #21 800035c: f512 0f80 cmn.w r2, #4194304 ; 0x400000 8000360: f080 809a bcs.w 8000498 <__adddf3+0x240> 8000364: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 8000368: bf08 it eq 800036a: ea5f 0c50 movseq.w ip, r0, lsr #1 800036e: f150 0000 adcs.w r0, r0, #0 8000372: eb41 5104 adc.w r1, r1, r4, lsl #20 8000376: ea41 0105 orr.w r1, r1, r5 800037a: bd30 pop {r4, r5, pc} 800037c: ea5f 0c4c movs.w ip, ip, lsl #1 8000380: 4140 adcs r0, r0 8000382: eb41 0101 adc.w r1, r1, r1 8000386: 3c01 subs r4, #1 8000388: bf28 it cs 800038a: f5b1 1f80 cmpcs.w r1, #1048576 ; 0x100000 800038e: d2e9 bcs.n 8000364 <__adddf3+0x10c> 8000390: f091 0f00 teq r1, #0 8000394: bf04 itt eq 8000396: 4601 moveq r1, r0 8000398: 2000 moveq r0, #0 800039a: fab1 f381 clz r3, r1 800039e: bf08 it eq 80003a0: 3320 addeq r3, #32 80003a2: f1a3 030b sub.w r3, r3, #11 80003a6: f1b3 0220 subs.w r2, r3, #32 80003aa: da0c bge.n 80003c6 <__adddf3+0x16e> 80003ac: 320c adds r2, #12 80003ae: dd08 ble.n 80003c2 <__adddf3+0x16a> 80003b0: f102 0c14 add.w ip, r2, #20 80003b4: f1c2 020c rsb r2, r2, #12 80003b8: fa01 f00c lsl.w r0, r1, ip 80003bc: fa21 f102 lsr.w r1, r1, r2 80003c0: e00c b.n 80003dc <__adddf3+0x184> 80003c2: f102 0214 add.w r2, r2, #20 80003c6: bfd8 it le 80003c8: f1c2 0c20 rsble ip, r2, #32 80003cc: fa01 f102 lsl.w r1, r1, r2 80003d0: fa20 fc0c lsr.w ip, r0, ip 80003d4: bfdc itt le 80003d6: ea41 010c orrle.w r1, r1, ip 80003da: 4090 lslle r0, r2 80003dc: 1ae4 subs r4, r4, r3 80003de: bfa2 ittt ge 80003e0: eb01 5104 addge.w r1, r1, r4, lsl #20 80003e4: 4329 orrge r1, r5 80003e6: bd30 popge {r4, r5, pc} 80003e8: ea6f 0404 mvn.w r4, r4 80003ec: 3c1f subs r4, #31 80003ee: da1c bge.n 800042a <__adddf3+0x1d2> 80003f0: 340c adds r4, #12 80003f2: dc0e bgt.n 8000412 <__adddf3+0x1ba> 80003f4: f104 0414 add.w r4, r4, #20 80003f8: f1c4 0220 rsb r2, r4, #32 80003fc: fa20 f004 lsr.w r0, r0, r4 8000400: fa01 f302 lsl.w r3, r1, r2 8000404: ea40 0003 orr.w r0, r0, r3 8000408: fa21 f304 lsr.w r3, r1, r4 800040c: ea45 0103 orr.w r1, r5, r3 8000410: bd30 pop {r4, r5, pc} 8000412: f1c4 040c rsb r4, r4, #12 8000416: f1c4 0220 rsb r2, r4, #32 800041a: fa20 f002 lsr.w r0, r0, r2 800041e: fa01 f304 lsl.w r3, r1, r4 8000422: ea40 0003 orr.w r0, r0, r3 8000426: 4629 mov r1, r5 8000428: bd30 pop {r4, r5, pc} 800042a: fa21 f004 lsr.w r0, r1, r4 800042e: 4629 mov r1, r5 8000430: bd30 pop {r4, r5, pc} 8000432: f094 0f00 teq r4, #0 8000436: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 800043a: bf06 itte eq 800043c: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 8000440: 3401 addeq r4, #1 8000442: 3d01 subne r5, #1 8000444: e74e b.n 80002e4 <__adddf3+0x8c> 8000446: ea7f 5c64 mvns.w ip, r4, asr #21 800044a: bf18 it ne 800044c: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000450: d029 beq.n 80004a6 <__adddf3+0x24e> 8000452: ea94 0f05 teq r4, r5 8000456: bf08 it eq 8000458: ea90 0f02 teqeq r0, r2 800045c: d005 beq.n 800046a <__adddf3+0x212> 800045e: ea54 0c00 orrs.w ip, r4, r0 8000462: bf04 itt eq 8000464: 4619 moveq r1, r3 8000466: 4610 moveq r0, r2 8000468: bd30 pop {r4, r5, pc} 800046a: ea91 0f03 teq r1, r3 800046e: bf1e ittt ne 8000470: 2100 movne r1, #0 8000472: 2000 movne r0, #0 8000474: bd30 popne {r4, r5, pc} 8000476: ea5f 5c54 movs.w ip, r4, lsr #21 800047a: d105 bne.n 8000488 <__adddf3+0x230> 800047c: 0040 lsls r0, r0, #1 800047e: 4149 adcs r1, r1 8000480: bf28 it cs 8000482: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 8000486: bd30 pop {r4, r5, pc} 8000488: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 800048c: bf3c itt cc 800048e: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 8000492: bd30 popcc {r4, r5, pc} 8000494: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000498: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 800049c: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 80004a0: f04f 0000 mov.w r0, #0 80004a4: bd30 pop {r4, r5, pc} 80004a6: ea7f 5c64 mvns.w ip, r4, asr #21 80004aa: bf1a itte ne 80004ac: 4619 movne r1, r3 80004ae: 4610 movne r0, r2 80004b0: ea7f 5c65 mvnseq.w ip, r5, asr #21 80004b4: bf1c itt ne 80004b6: 460b movne r3, r1 80004b8: 4602 movne r2, r0 80004ba: ea50 3401 orrs.w r4, r0, r1, lsl #12 80004be: bf06 itte eq 80004c0: ea52 3503 orrseq.w r5, r2, r3, lsl #12 80004c4: ea91 0f03 teqeq r1, r3 80004c8: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 80004cc: bd30 pop {r4, r5, pc} 80004ce: bf00 nop 080004d0 <__aeabi_ui2d>: 80004d0: f090 0f00 teq r0, #0 80004d4: bf04 itt eq 80004d6: 2100 moveq r1, #0 80004d8: 4770 bxeq lr 80004da: b530 push {r4, r5, lr} 80004dc: f44f 6480 mov.w r4, #1024 ; 0x400 80004e0: f104 0432 add.w r4, r4, #50 ; 0x32 80004e4: f04f 0500 mov.w r5, #0 80004e8: f04f 0100 mov.w r1, #0 80004ec: e750 b.n 8000390 <__adddf3+0x138> 80004ee: bf00 nop 080004f0 <__aeabi_i2d>: 80004f0: f090 0f00 teq r0, #0 80004f4: bf04 itt eq 80004f6: 2100 moveq r1, #0 80004f8: 4770 bxeq lr 80004fa: b530 push {r4, r5, lr} 80004fc: f44f 6480 mov.w r4, #1024 ; 0x400 8000500: f104 0432 add.w r4, r4, #50 ; 0x32 8000504: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 8000508: bf48 it mi 800050a: 4240 negmi r0, r0 800050c: f04f 0100 mov.w r1, #0 8000510: e73e b.n 8000390 <__adddf3+0x138> 8000512: bf00 nop 08000514 <__aeabi_f2d>: 8000514: 0042 lsls r2, r0, #1 8000516: ea4f 01e2 mov.w r1, r2, asr #3 800051a: ea4f 0131 mov.w r1, r1, rrx 800051e: ea4f 7002 mov.w r0, r2, lsl #28 8000522: bf1f itttt ne 8000524: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 8000528: f093 4f7f teqne r3, #4278190080 ; 0xff000000 800052c: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 8000530: 4770 bxne lr 8000532: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 8000536: bf08 it eq 8000538: 4770 bxeq lr 800053a: f093 4f7f teq r3, #4278190080 ; 0xff000000 800053e: bf04 itt eq 8000540: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 8000544: 4770 bxeq lr 8000546: b530 push {r4, r5, lr} 8000548: f44f 7460 mov.w r4, #896 ; 0x380 800054c: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000550: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 8000554: e71c b.n 8000390 <__adddf3+0x138> 8000556: bf00 nop 08000558 <__aeabi_ul2d>: 8000558: ea50 0201 orrs.w r2, r0, r1 800055c: bf08 it eq 800055e: 4770 bxeq lr 8000560: b530 push {r4, r5, lr} 8000562: f04f 0500 mov.w r5, #0 8000566: e00a b.n 800057e <__aeabi_l2d+0x16> 08000568 <__aeabi_l2d>: 8000568: ea50 0201 orrs.w r2, r0, r1 800056c: bf08 it eq 800056e: 4770 bxeq lr 8000570: b530 push {r4, r5, lr} 8000572: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 8000576: d502 bpl.n 800057e <__aeabi_l2d+0x16> 8000578: 4240 negs r0, r0 800057a: eb61 0141 sbc.w r1, r1, r1, lsl #1 800057e: f44f 6480 mov.w r4, #1024 ; 0x400 8000582: f104 0432 add.w r4, r4, #50 ; 0x32 8000586: ea5f 5c91 movs.w ip, r1, lsr #22 800058a: f43f aed8 beq.w 800033e <__adddf3+0xe6> 800058e: f04f 0203 mov.w r2, #3 8000592: ea5f 0cdc movs.w ip, ip, lsr #3 8000596: bf18 it ne 8000598: 3203 addne r2, #3 800059a: ea5f 0cdc movs.w ip, ip, lsr #3 800059e: bf18 it ne 80005a0: 3203 addne r2, #3 80005a2: eb02 02dc add.w r2, r2, ip, lsr #3 80005a6: f1c2 0320 rsb r3, r2, #32 80005aa: fa00 fc03 lsl.w ip, r0, r3 80005ae: fa20 f002 lsr.w r0, r0, r2 80005b2: fa01 fe03 lsl.w lr, r1, r3 80005b6: ea40 000e orr.w r0, r0, lr 80005ba: fa21 f102 lsr.w r1, r1, r2 80005be: 4414 add r4, r2 80005c0: e6bd b.n 800033e <__adddf3+0xe6> 80005c2: bf00 nop 080005c4 <__aeabi_dmul>: 80005c4: b570 push {r4, r5, r6, lr} 80005c6: f04f 0cff mov.w ip, #255 ; 0xff 80005ca: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 80005ce: ea1c 5411 ands.w r4, ip, r1, lsr #20 80005d2: bf1d ittte ne 80005d4: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80005d8: ea94 0f0c teqne r4, ip 80005dc: ea95 0f0c teqne r5, ip 80005e0: f000 f8de bleq 80007a0 <__aeabi_dmul+0x1dc> 80005e4: 442c add r4, r5 80005e6: ea81 0603 eor.w r6, r1, r3 80005ea: ea21 514c bic.w r1, r1, ip, lsl #21 80005ee: ea23 534c bic.w r3, r3, ip, lsl #21 80005f2: ea50 3501 orrs.w r5, r0, r1, lsl #12 80005f6: bf18 it ne 80005f8: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80005fc: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000600: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 8000604: d038 beq.n 8000678 <__aeabi_dmul+0xb4> 8000606: fba0 ce02 umull ip, lr, r0, r2 800060a: f04f 0500 mov.w r5, #0 800060e: fbe1 e502 umlal lr, r5, r1, r2 8000612: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 8000616: fbe0 e503 umlal lr, r5, r0, r3 800061a: f04f 0600 mov.w r6, #0 800061e: fbe1 5603 umlal r5, r6, r1, r3 8000622: f09c 0f00 teq ip, #0 8000626: bf18 it ne 8000628: f04e 0e01 orrne.w lr, lr, #1 800062c: f1a4 04ff sub.w r4, r4, #255 ; 0xff 8000630: f5b6 7f00 cmp.w r6, #512 ; 0x200 8000634: f564 7440 sbc.w r4, r4, #768 ; 0x300 8000638: d204 bcs.n 8000644 <__aeabi_dmul+0x80> 800063a: ea5f 0e4e movs.w lr, lr, lsl #1 800063e: 416d adcs r5, r5 8000640: eb46 0606 adc.w r6, r6, r6 8000644: ea42 21c6 orr.w r1, r2, r6, lsl #11 8000648: ea41 5155 orr.w r1, r1, r5, lsr #21 800064c: ea4f 20c5 mov.w r0, r5, lsl #11 8000650: ea40 505e orr.w r0, r0, lr, lsr #21 8000654: ea4f 2ece mov.w lr, lr, lsl #11 8000658: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 800065c: bf88 it hi 800065e: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 8000662: d81e bhi.n 80006a2 <__aeabi_dmul+0xde> 8000664: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 8000668: bf08 it eq 800066a: ea5f 0e50 movseq.w lr, r0, lsr #1 800066e: f150 0000 adcs.w r0, r0, #0 8000672: eb41 5104 adc.w r1, r1, r4, lsl #20 8000676: bd70 pop {r4, r5, r6, pc} 8000678: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 800067c: ea46 0101 orr.w r1, r6, r1 8000680: ea40 0002 orr.w r0, r0, r2 8000684: ea81 0103 eor.w r1, r1, r3 8000688: ebb4 045c subs.w r4, r4, ip, lsr #1 800068c: bfc2 ittt gt 800068e: ebd4 050c rsbsgt r5, r4, ip 8000692: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8000696: bd70 popgt {r4, r5, r6, pc} 8000698: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 800069c: f04f 0e00 mov.w lr, #0 80006a0: 3c01 subs r4, #1 80006a2: f300 80ab bgt.w 80007fc <__aeabi_dmul+0x238> 80006a6: f114 0f36 cmn.w r4, #54 ; 0x36 80006aa: bfde ittt le 80006ac: 2000 movle r0, #0 80006ae: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 80006b2: bd70 pople {r4, r5, r6, pc} 80006b4: f1c4 0400 rsb r4, r4, #0 80006b8: 3c20 subs r4, #32 80006ba: da35 bge.n 8000728 <__aeabi_dmul+0x164> 80006bc: 340c adds r4, #12 80006be: dc1b bgt.n 80006f8 <__aeabi_dmul+0x134> 80006c0: f104 0414 add.w r4, r4, #20 80006c4: f1c4 0520 rsb r5, r4, #32 80006c8: fa00 f305 lsl.w r3, r0, r5 80006cc: fa20 f004 lsr.w r0, r0, r4 80006d0: fa01 f205 lsl.w r2, r1, r5 80006d4: ea40 0002 orr.w r0, r0, r2 80006d8: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 80006dc: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 80006e0: eb10 70d3 adds.w r0, r0, r3, lsr #31 80006e4: fa21 f604 lsr.w r6, r1, r4 80006e8: eb42 0106 adc.w r1, r2, r6 80006ec: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80006f0: bf08 it eq 80006f2: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80006f6: bd70 pop {r4, r5, r6, pc} 80006f8: f1c4 040c rsb r4, r4, #12 80006fc: f1c4 0520 rsb r5, r4, #32 8000700: fa00 f304 lsl.w r3, r0, r4 8000704: fa20 f005 lsr.w r0, r0, r5 8000708: fa01 f204 lsl.w r2, r1, r4 800070c: ea40 0002 orr.w r0, r0, r2 8000710: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8000714: eb10 70d3 adds.w r0, r0, r3, lsr #31 8000718: f141 0100 adc.w r1, r1, #0 800071c: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8000720: bf08 it eq 8000722: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8000726: bd70 pop {r4, r5, r6, pc} 8000728: f1c4 0520 rsb r5, r4, #32 800072c: fa00 f205 lsl.w r2, r0, r5 8000730: ea4e 0e02 orr.w lr, lr, r2 8000734: fa20 f304 lsr.w r3, r0, r4 8000738: fa01 f205 lsl.w r2, r1, r5 800073c: ea43 0302 orr.w r3, r3, r2 8000740: fa21 f004 lsr.w r0, r1, r4 8000744: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8000748: fa21 f204 lsr.w r2, r1, r4 800074c: ea20 0002 bic.w r0, r0, r2 8000750: eb00 70d3 add.w r0, r0, r3, lsr #31 8000754: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8000758: bf08 it eq 800075a: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800075e: bd70 pop {r4, r5, r6, pc} 8000760: f094 0f00 teq r4, #0 8000764: d10f bne.n 8000786 <__aeabi_dmul+0x1c2> 8000766: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 800076a: 0040 lsls r0, r0, #1 800076c: eb41 0101 adc.w r1, r1, r1 8000770: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000774: bf08 it eq 8000776: 3c01 subeq r4, #1 8000778: d0f7 beq.n 800076a <__aeabi_dmul+0x1a6> 800077a: ea41 0106 orr.w r1, r1, r6 800077e: f095 0f00 teq r5, #0 8000782: bf18 it ne 8000784: 4770 bxne lr 8000786: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 800078a: 0052 lsls r2, r2, #1 800078c: eb43 0303 adc.w r3, r3, r3 8000790: f413 1f80 tst.w r3, #1048576 ; 0x100000 8000794: bf08 it eq 8000796: 3d01 subeq r5, #1 8000798: d0f7 beq.n 800078a <__aeabi_dmul+0x1c6> 800079a: ea43 0306 orr.w r3, r3, r6 800079e: 4770 bx lr 80007a0: ea94 0f0c teq r4, ip 80007a4: ea0c 5513 and.w r5, ip, r3, lsr #20 80007a8: bf18 it ne 80007aa: ea95 0f0c teqne r5, ip 80007ae: d00c beq.n 80007ca <__aeabi_dmul+0x206> 80007b0: ea50 0641 orrs.w r6, r0, r1, lsl #1 80007b4: bf18 it ne 80007b6: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80007ba: d1d1 bne.n 8000760 <__aeabi_dmul+0x19c> 80007bc: ea81 0103 eor.w r1, r1, r3 80007c0: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 80007c4: f04f 0000 mov.w r0, #0 80007c8: bd70 pop {r4, r5, r6, pc} 80007ca: ea50 0641 orrs.w r6, r0, r1, lsl #1 80007ce: bf06 itte eq 80007d0: 4610 moveq r0, r2 80007d2: 4619 moveq r1, r3 80007d4: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80007d8: d019 beq.n 800080e <__aeabi_dmul+0x24a> 80007da: ea94 0f0c teq r4, ip 80007de: d102 bne.n 80007e6 <__aeabi_dmul+0x222> 80007e0: ea50 3601 orrs.w r6, r0, r1, lsl #12 80007e4: d113 bne.n 800080e <__aeabi_dmul+0x24a> 80007e6: ea95 0f0c teq r5, ip 80007ea: d105 bne.n 80007f8 <__aeabi_dmul+0x234> 80007ec: ea52 3603 orrs.w r6, r2, r3, lsl #12 80007f0: bf1c itt ne 80007f2: 4610 movne r0, r2 80007f4: 4619 movne r1, r3 80007f6: d10a bne.n 800080e <__aeabi_dmul+0x24a> 80007f8: ea81 0103 eor.w r1, r1, r3 80007fc: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8000800: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 8000804: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 8000808: f04f 0000 mov.w r0, #0 800080c: bd70 pop {r4, r5, r6, pc} 800080e: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 8000812: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 8000816: bd70 pop {r4, r5, r6, pc} 08000818 <__aeabi_ddiv>: 8000818: b570 push {r4, r5, r6, lr} 800081a: f04f 0cff mov.w ip, #255 ; 0xff 800081e: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 8000822: ea1c 5411 ands.w r4, ip, r1, lsr #20 8000826: bf1d ittte ne 8000828: ea1c 5513 andsne.w r5, ip, r3, lsr #20 800082c: ea94 0f0c teqne r4, ip 8000830: ea95 0f0c teqne r5, ip 8000834: f000 f8a7 bleq 8000986 <__aeabi_ddiv+0x16e> 8000838: eba4 0405 sub.w r4, r4, r5 800083c: ea81 0e03 eor.w lr, r1, r3 8000840: ea52 3503 orrs.w r5, r2, r3, lsl #12 8000844: ea4f 3101 mov.w r1, r1, lsl #12 8000848: f000 8088 beq.w 800095c <__aeabi_ddiv+0x144> 800084c: ea4f 3303 mov.w r3, r3, lsl #12 8000850: f04f 5580 mov.w r5, #268435456 ; 0x10000000 8000854: ea45 1313 orr.w r3, r5, r3, lsr #4 8000858: ea43 6312 orr.w r3, r3, r2, lsr #24 800085c: ea4f 2202 mov.w r2, r2, lsl #8 8000860: ea45 1511 orr.w r5, r5, r1, lsr #4 8000864: ea45 6510 orr.w r5, r5, r0, lsr #24 8000868: ea4f 2600 mov.w r6, r0, lsl #8 800086c: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000 8000870: 429d cmp r5, r3 8000872: bf08 it eq 8000874: 4296 cmpeq r6, r2 8000876: f144 04fd adc.w r4, r4, #253 ; 0xfd 800087a: f504 7440 add.w r4, r4, #768 ; 0x300 800087e: d202 bcs.n 8000886 <__aeabi_ddiv+0x6e> 8000880: 085b lsrs r3, r3, #1 8000882: ea4f 0232 mov.w r2, r2, rrx 8000886: 1ab6 subs r6, r6, r2 8000888: eb65 0503 sbc.w r5, r5, r3 800088c: 085b lsrs r3, r3, #1 800088e: ea4f 0232 mov.w r2, r2, rrx 8000892: f44f 1080 mov.w r0, #1048576 ; 0x100000 8000896: f44f 2c00 mov.w ip, #524288 ; 0x80000 800089a: ebb6 0e02 subs.w lr, r6, r2 800089e: eb75 0e03 sbcs.w lr, r5, r3 80008a2: bf22 ittt cs 80008a4: 1ab6 subcs r6, r6, r2 80008a6: 4675 movcs r5, lr 80008a8: ea40 000c orrcs.w r0, r0, ip 80008ac: 085b lsrs r3, r3, #1 80008ae: ea4f 0232 mov.w r2, r2, rrx 80008b2: ebb6 0e02 subs.w lr, r6, r2 80008b6: eb75 0e03 sbcs.w lr, r5, r3 80008ba: bf22 ittt cs 80008bc: 1ab6 subcs r6, r6, r2 80008be: 4675 movcs r5, lr 80008c0: ea40 005c orrcs.w r0, r0, ip, lsr #1 80008c4: 085b lsrs r3, r3, #1 80008c6: ea4f 0232 mov.w r2, r2, rrx 80008ca: ebb6 0e02 subs.w lr, r6, r2 80008ce: eb75 0e03 sbcs.w lr, r5, r3 80008d2: bf22 ittt cs 80008d4: 1ab6 subcs r6, r6, r2 80008d6: 4675 movcs r5, lr 80008d8: ea40 009c orrcs.w r0, r0, ip, lsr #2 80008dc: 085b lsrs r3, r3, #1 80008de: ea4f 0232 mov.w r2, r2, rrx 80008e2: ebb6 0e02 subs.w lr, r6, r2 80008e6: eb75 0e03 sbcs.w lr, r5, r3 80008ea: bf22 ittt cs 80008ec: 1ab6 subcs r6, r6, r2 80008ee: 4675 movcs r5, lr 80008f0: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80008f4: ea55 0e06 orrs.w lr, r5, r6 80008f8: d018 beq.n 800092c <__aeabi_ddiv+0x114> 80008fa: ea4f 1505 mov.w r5, r5, lsl #4 80008fe: ea45 7516 orr.w r5, r5, r6, lsr #28 8000902: ea4f 1606 mov.w r6, r6, lsl #4 8000906: ea4f 03c3 mov.w r3, r3, lsl #3 800090a: ea43 7352 orr.w r3, r3, r2, lsr #29 800090e: ea4f 02c2 mov.w r2, r2, lsl #3 8000912: ea5f 1c1c movs.w ip, ip, lsr #4 8000916: d1c0 bne.n 800089a <__aeabi_ddiv+0x82> 8000918: f411 1f80 tst.w r1, #1048576 ; 0x100000 800091c: d10b bne.n 8000936 <__aeabi_ddiv+0x11e> 800091e: ea41 0100 orr.w r1, r1, r0 8000922: f04f 0000 mov.w r0, #0 8000926: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000 800092a: e7b6 b.n 800089a <__aeabi_ddiv+0x82> 800092c: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000930: bf04 itt eq 8000932: 4301 orreq r1, r0 8000934: 2000 moveq r0, #0 8000936: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 800093a: bf88 it hi 800093c: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 8000940: f63f aeaf bhi.w 80006a2 <__aeabi_dmul+0xde> 8000944: ebb5 0c03 subs.w ip, r5, r3 8000948: bf04 itt eq 800094a: ebb6 0c02 subseq.w ip, r6, r2 800094e: ea5f 0c50 movseq.w ip, r0, lsr #1 8000952: f150 0000 adcs.w r0, r0, #0 8000956: eb41 5104 adc.w r1, r1, r4, lsl #20 800095a: bd70 pop {r4, r5, r6, pc} 800095c: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000 8000960: ea4e 3111 orr.w r1, lr, r1, lsr #12 8000964: eb14 045c adds.w r4, r4, ip, lsr #1 8000968: bfc2 ittt gt 800096a: ebd4 050c rsbsgt r5, r4, ip 800096e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8000972: bd70 popgt {r4, r5, r6, pc} 8000974: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000978: f04f 0e00 mov.w lr, #0 800097c: 3c01 subs r4, #1 800097e: e690 b.n 80006a2 <__aeabi_dmul+0xde> 8000980: ea45 0e06 orr.w lr, r5, r6 8000984: e68d b.n 80006a2 <__aeabi_dmul+0xde> 8000986: ea0c 5513 and.w r5, ip, r3, lsr #20 800098a: ea94 0f0c teq r4, ip 800098e: bf08 it eq 8000990: ea95 0f0c teqeq r5, ip 8000994: f43f af3b beq.w 800080e <__aeabi_dmul+0x24a> 8000998: ea94 0f0c teq r4, ip 800099c: d10a bne.n 80009b4 <__aeabi_ddiv+0x19c> 800099e: ea50 3401 orrs.w r4, r0, r1, lsl #12 80009a2: f47f af34 bne.w 800080e <__aeabi_dmul+0x24a> 80009a6: ea95 0f0c teq r5, ip 80009aa: f47f af25 bne.w 80007f8 <__aeabi_dmul+0x234> 80009ae: 4610 mov r0, r2 80009b0: 4619 mov r1, r3 80009b2: e72c b.n 800080e <__aeabi_dmul+0x24a> 80009b4: ea95 0f0c teq r5, ip 80009b8: d106 bne.n 80009c8 <__aeabi_ddiv+0x1b0> 80009ba: ea52 3503 orrs.w r5, r2, r3, lsl #12 80009be: f43f aefd beq.w 80007bc <__aeabi_dmul+0x1f8> 80009c2: 4610 mov r0, r2 80009c4: 4619 mov r1, r3 80009c6: e722 b.n 800080e <__aeabi_dmul+0x24a> 80009c8: ea50 0641 orrs.w r6, r0, r1, lsl #1 80009cc: bf18 it ne 80009ce: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80009d2: f47f aec5 bne.w 8000760 <__aeabi_dmul+0x19c> 80009d6: ea50 0441 orrs.w r4, r0, r1, lsl #1 80009da: f47f af0d bne.w 80007f8 <__aeabi_dmul+0x234> 80009de: ea52 0543 orrs.w r5, r2, r3, lsl #1 80009e2: f47f aeeb bne.w 80007bc <__aeabi_dmul+0x1f8> 80009e6: e712 b.n 800080e <__aeabi_dmul+0x24a> 080009e8 <__gedf2>: 80009e8: f04f 3cff mov.w ip, #4294967295 ; 0xffffffff 80009ec: e006 b.n 80009fc <__cmpdf2+0x4> 80009ee: bf00 nop 080009f0 <__ledf2>: 80009f0: f04f 0c01 mov.w ip, #1 80009f4: e002 b.n 80009fc <__cmpdf2+0x4> 80009f6: bf00 nop 080009f8 <__cmpdf2>: 80009f8: f04f 0c01 mov.w ip, #1 80009fc: f84d cd04 str.w ip, [sp, #-4]! 8000a00: ea4f 0c41 mov.w ip, r1, lsl #1 8000a04: ea7f 5c6c mvns.w ip, ip, asr #21 8000a08: ea4f 0c43 mov.w ip, r3, lsl #1 8000a0c: bf18 it ne 8000a0e: ea7f 5c6c mvnsne.w ip, ip, asr #21 8000a12: d01b beq.n 8000a4c <__cmpdf2+0x54> 8000a14: b001 add sp, #4 8000a16: ea50 0c41 orrs.w ip, r0, r1, lsl #1 8000a1a: bf0c ite eq 8000a1c: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 8000a20: ea91 0f03 teqne r1, r3 8000a24: bf02 ittt eq 8000a26: ea90 0f02 teqeq r0, r2 8000a2a: 2000 moveq r0, #0 8000a2c: 4770 bxeq lr 8000a2e: f110 0f00 cmn.w r0, #0 8000a32: ea91 0f03 teq r1, r3 8000a36: bf58 it pl 8000a38: 4299 cmppl r1, r3 8000a3a: bf08 it eq 8000a3c: 4290 cmpeq r0, r2 8000a3e: bf2c ite cs 8000a40: 17d8 asrcs r0, r3, #31 8000a42: ea6f 70e3 mvncc.w r0, r3, asr #31 8000a46: f040 0001 orr.w r0, r0, #1 8000a4a: 4770 bx lr 8000a4c: ea4f 0c41 mov.w ip, r1, lsl #1 8000a50: ea7f 5c6c mvns.w ip, ip, asr #21 8000a54: d102 bne.n 8000a5c <__cmpdf2+0x64> 8000a56: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000a5a: d107 bne.n 8000a6c <__cmpdf2+0x74> 8000a5c: ea4f 0c43 mov.w ip, r3, lsl #1 8000a60: ea7f 5c6c mvns.w ip, ip, asr #21 8000a64: d1d6 bne.n 8000a14 <__cmpdf2+0x1c> 8000a66: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000a6a: d0d3 beq.n 8000a14 <__cmpdf2+0x1c> 8000a6c: f85d 0b04 ldr.w r0, [sp], #4 8000a70: 4770 bx lr 8000a72: bf00 nop 08000a74 <__aeabi_cdrcmple>: 8000a74: 4684 mov ip, r0 8000a76: 4610 mov r0, r2 8000a78: 4662 mov r2, ip 8000a7a: 468c mov ip, r1 8000a7c: 4619 mov r1, r3 8000a7e: 4663 mov r3, ip 8000a80: e000 b.n 8000a84 <__aeabi_cdcmpeq> 8000a82: bf00 nop 08000a84 <__aeabi_cdcmpeq>: 8000a84: b501 push {r0, lr} 8000a86: f7ff ffb7 bl 80009f8 <__cmpdf2> 8000a8a: 2800 cmp r0, #0 8000a8c: bf48 it mi 8000a8e: f110 0f00 cmnmi.w r0, #0 8000a92: bd01 pop {r0, pc} 08000a94 <__aeabi_dcmpeq>: 8000a94: f84d ed08 str.w lr, [sp, #-8]! 8000a98: f7ff fff4 bl 8000a84 <__aeabi_cdcmpeq> 8000a9c: bf0c ite eq 8000a9e: 2001 moveq r0, #1 8000aa0: 2000 movne r0, #0 8000aa2: f85d fb08 ldr.w pc, [sp], #8 8000aa6: bf00 nop 08000aa8 <__aeabi_dcmplt>: 8000aa8: f84d ed08 str.w lr, [sp, #-8]! 8000aac: f7ff ffea bl 8000a84 <__aeabi_cdcmpeq> 8000ab0: bf34 ite cc 8000ab2: 2001 movcc r0, #1 8000ab4: 2000 movcs r0, #0 8000ab6: f85d fb08 ldr.w pc, [sp], #8 8000aba: bf00 nop 08000abc <__aeabi_dcmple>: 8000abc: f84d ed08 str.w lr, [sp, #-8]! 8000ac0: f7ff ffe0 bl 8000a84 <__aeabi_cdcmpeq> 8000ac4: bf94 ite ls 8000ac6: 2001 movls r0, #1 8000ac8: 2000 movhi r0, #0 8000aca: f85d fb08 ldr.w pc, [sp], #8 8000ace: bf00 nop 08000ad0 <__aeabi_dcmpge>: 8000ad0: f84d ed08 str.w lr, [sp, #-8]! 8000ad4: f7ff ffce bl 8000a74 <__aeabi_cdrcmple> 8000ad8: bf94 ite ls 8000ada: 2001 movls r0, #1 8000adc: 2000 movhi r0, #0 8000ade: f85d fb08 ldr.w pc, [sp], #8 8000ae2: bf00 nop 08000ae4 <__aeabi_dcmpgt>: 8000ae4: f84d ed08 str.w lr, [sp, #-8]! 8000ae8: f7ff ffc4 bl 8000a74 <__aeabi_cdrcmple> 8000aec: bf34 ite cc 8000aee: 2001 movcc r0, #1 8000af0: 2000 movcs r0, #0 8000af2: f85d fb08 ldr.w pc, [sp], #8 8000af6: bf00 nop 08000af8 <__aeabi_dcmpun>: 8000af8: ea4f 0c41 mov.w ip, r1, lsl #1 8000afc: ea7f 5c6c mvns.w ip, ip, asr #21 8000b00: d102 bne.n 8000b08 <__aeabi_dcmpun+0x10> 8000b02: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000b06: d10a bne.n 8000b1e <__aeabi_dcmpun+0x26> 8000b08: ea4f 0c43 mov.w ip, r3, lsl #1 8000b0c: ea7f 5c6c mvns.w ip, ip, asr #21 8000b10: d102 bne.n 8000b18 <__aeabi_dcmpun+0x20> 8000b12: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000b16: d102 bne.n 8000b1e <__aeabi_dcmpun+0x26> 8000b18: f04f 0000 mov.w r0, #0 8000b1c: 4770 bx lr 8000b1e: f04f 0001 mov.w r0, #1 8000b22: 4770 bx lr 08000b24 <__aeabi_d2iz>: 8000b24: ea4f 0241 mov.w r2, r1, lsl #1 8000b28: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 8000b2c: d215 bcs.n 8000b5a <__aeabi_d2iz+0x36> 8000b2e: d511 bpl.n 8000b54 <__aeabi_d2iz+0x30> 8000b30: f46f 7378 mvn.w r3, #992 ; 0x3e0 8000b34: ebb3 5262 subs.w r2, r3, r2, asr #21 8000b38: d912 bls.n 8000b60 <__aeabi_d2iz+0x3c> 8000b3a: ea4f 23c1 mov.w r3, r1, lsl #11 8000b3e: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8000b42: ea43 5350 orr.w r3, r3, r0, lsr #21 8000b46: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000b4a: fa23 f002 lsr.w r0, r3, r2 8000b4e: bf18 it ne 8000b50: 4240 negne r0, r0 8000b52: 4770 bx lr 8000b54: f04f 0000 mov.w r0, #0 8000b58: 4770 bx lr 8000b5a: ea50 3001 orrs.w r0, r0, r1, lsl #12 8000b5e: d105 bne.n 8000b6c <__aeabi_d2iz+0x48> 8000b60: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000 8000b64: bf08 it eq 8000b66: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 8000b6a: 4770 bx lr 8000b6c: f04f 0000 mov.w r0, #0 8000b70: 4770 bx lr 8000b72: bf00 nop 08000b74 <__aeabi_d2f>: 8000b74: ea4f 0241 mov.w r2, r1, lsl #1 8000b78: f1b2 43e0 subs.w r3, r2, #1879048192 ; 0x70000000 8000b7c: bf24 itt cs 8000b7e: f5b3 1c00 subscs.w ip, r3, #2097152 ; 0x200000 8000b82: f1dc 5cfe rsbscs ip, ip, #532676608 ; 0x1fc00000 8000b86: d90d bls.n 8000ba4 <__aeabi_d2f+0x30> 8000b88: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 8000b8c: ea4f 02c0 mov.w r2, r0, lsl #3 8000b90: ea4c 7050 orr.w r0, ip, r0, lsr #29 8000b94: f1b2 4f00 cmp.w r2, #2147483648 ; 0x80000000 8000b98: eb40 0083 adc.w r0, r0, r3, lsl #2 8000b9c: bf08 it eq 8000b9e: f020 0001 biceq.w r0, r0, #1 8000ba2: 4770 bx lr 8000ba4: f011 4f80 tst.w r1, #1073741824 ; 0x40000000 8000ba8: d121 bne.n 8000bee <__aeabi_d2f+0x7a> 8000baa: f113 7238 adds.w r2, r3, #48234496 ; 0x2e00000 8000bae: bfbc itt lt 8000bb0: f001 4000 andlt.w r0, r1, #2147483648 ; 0x80000000 8000bb4: 4770 bxlt lr 8000bb6: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000bba: ea4f 5252 mov.w r2, r2, lsr #21 8000bbe: f1c2 0218 rsb r2, r2, #24 8000bc2: f1c2 0c20 rsb ip, r2, #32 8000bc6: fa10 f30c lsls.w r3, r0, ip 8000bca: fa20 f002 lsr.w r0, r0, r2 8000bce: bf18 it ne 8000bd0: f040 0001 orrne.w r0, r0, #1 8000bd4: ea4f 23c1 mov.w r3, r1, lsl #11 8000bd8: ea4f 23d3 mov.w r3, r3, lsr #11 8000bdc: fa03 fc0c lsl.w ip, r3, ip 8000be0: ea40 000c orr.w r0, r0, ip 8000be4: fa23 f302 lsr.w r3, r3, r2 8000be8: ea4f 0343 mov.w r3, r3, lsl #1 8000bec: e7cc b.n 8000b88 <__aeabi_d2f+0x14> 8000bee: ea7f 5362 mvns.w r3, r2, asr #21 8000bf2: d107 bne.n 8000c04 <__aeabi_d2f+0x90> 8000bf4: ea50 3301 orrs.w r3, r0, r1, lsl #12 8000bf8: bf1e ittt ne 8000bfa: f04f 40fe movne.w r0, #2130706432 ; 0x7f000000 8000bfe: f440 0040 orrne.w r0, r0, #12582912 ; 0xc00000 8000c02: 4770 bxne lr 8000c04: f001 4000 and.w r0, r1, #2147483648 ; 0x80000000 8000c08: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 8000c0c: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000c10: 4770 bx lr 8000c12: bf00 nop 08000c14 <__aeabi_frsub>: 8000c14: f080 4000 eor.w r0, r0, #2147483648 ; 0x80000000 8000c18: e002 b.n 8000c20 <__addsf3> 8000c1a: bf00 nop 08000c1c <__aeabi_fsub>: 8000c1c: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 08000c20 <__addsf3>: 8000c20: 0042 lsls r2, r0, #1 8000c22: bf1f itttt ne 8000c24: ea5f 0341 movsne.w r3, r1, lsl #1 8000c28: ea92 0f03 teqne r2, r3 8000c2c: ea7f 6c22 mvnsne.w ip, r2, asr #24 8000c30: ea7f 6c23 mvnsne.w ip, r3, asr #24 8000c34: d06a beq.n 8000d0c <__addsf3+0xec> 8000c36: ea4f 6212 mov.w r2, r2, lsr #24 8000c3a: ebd2 6313 rsbs r3, r2, r3, lsr #24 8000c3e: bfc1 itttt gt 8000c40: 18d2 addgt r2, r2, r3 8000c42: 4041 eorgt r1, r0 8000c44: 4048 eorgt r0, r1 8000c46: 4041 eorgt r1, r0 8000c48: bfb8 it lt 8000c4a: 425b neglt r3, r3 8000c4c: 2b19 cmp r3, #25 8000c4e: bf88 it hi 8000c50: 4770 bxhi lr 8000c52: f010 4f00 tst.w r0, #2147483648 ; 0x80000000 8000c56: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000c5a: f020 407f bic.w r0, r0, #4278190080 ; 0xff000000 8000c5e: bf18 it ne 8000c60: 4240 negne r0, r0 8000c62: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000c66: f441 0100 orr.w r1, r1, #8388608 ; 0x800000 8000c6a: f021 417f bic.w r1, r1, #4278190080 ; 0xff000000 8000c6e: bf18 it ne 8000c70: 4249 negne r1, r1 8000c72: ea92 0f03 teq r2, r3 8000c76: d03f beq.n 8000cf8 <__addsf3+0xd8> 8000c78: f1a2 0201 sub.w r2, r2, #1 8000c7c: fa41 fc03 asr.w ip, r1, r3 8000c80: eb10 000c adds.w r0, r0, ip 8000c84: f1c3 0320 rsb r3, r3, #32 8000c88: fa01 f103 lsl.w r1, r1, r3 8000c8c: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000 8000c90: d502 bpl.n 8000c98 <__addsf3+0x78> 8000c92: 4249 negs r1, r1 8000c94: eb60 0040 sbc.w r0, r0, r0, lsl #1 8000c98: f5b0 0f00 cmp.w r0, #8388608 ; 0x800000 8000c9c: d313 bcc.n 8000cc6 <__addsf3+0xa6> 8000c9e: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000 8000ca2: d306 bcc.n 8000cb2 <__addsf3+0x92> 8000ca4: 0840 lsrs r0, r0, #1 8000ca6: ea4f 0131 mov.w r1, r1, rrx 8000caa: f102 0201 add.w r2, r2, #1 8000cae: 2afe cmp r2, #254 ; 0xfe 8000cb0: d251 bcs.n 8000d56 <__addsf3+0x136> 8000cb2: f1b1 4f00 cmp.w r1, #2147483648 ; 0x80000000 8000cb6: eb40 50c2 adc.w r0, r0, r2, lsl #23 8000cba: bf08 it eq 8000cbc: f020 0001 biceq.w r0, r0, #1 8000cc0: ea40 0003 orr.w r0, r0, r3 8000cc4: 4770 bx lr 8000cc6: 0049 lsls r1, r1, #1 8000cc8: eb40 0000 adc.w r0, r0, r0 8000ccc: 3a01 subs r2, #1 8000cce: bf28 it cs 8000cd0: f5b0 0f00 cmpcs.w r0, #8388608 ; 0x800000 8000cd4: d2ed bcs.n 8000cb2 <__addsf3+0x92> 8000cd6: fab0 fc80 clz ip, r0 8000cda: f1ac 0c08 sub.w ip, ip, #8 8000cde: ebb2 020c subs.w r2, r2, ip 8000ce2: fa00 f00c lsl.w r0, r0, ip 8000ce6: bfaa itet ge 8000ce8: eb00 50c2 addge.w r0, r0, r2, lsl #23 8000cec: 4252 neglt r2, r2 8000cee: 4318 orrge r0, r3 8000cf0: bfbc itt lt 8000cf2: 40d0 lsrlt r0, r2 8000cf4: 4318 orrlt r0, r3 8000cf6: 4770 bx lr 8000cf8: f092 0f00 teq r2, #0 8000cfc: f481 0100 eor.w r1, r1, #8388608 ; 0x800000 8000d00: bf06 itte eq 8000d02: f480 0000 eoreq.w r0, r0, #8388608 ; 0x800000 8000d06: 3201 addeq r2, #1 8000d08: 3b01 subne r3, #1 8000d0a: e7b5 b.n 8000c78 <__addsf3+0x58> 8000d0c: ea4f 0341 mov.w r3, r1, lsl #1 8000d10: ea7f 6c22 mvns.w ip, r2, asr #24 8000d14: bf18 it ne 8000d16: ea7f 6c23 mvnsne.w ip, r3, asr #24 8000d1a: d021 beq.n 8000d60 <__addsf3+0x140> 8000d1c: ea92 0f03 teq r2, r3 8000d20: d004 beq.n 8000d2c <__addsf3+0x10c> 8000d22: f092 0f00 teq r2, #0 8000d26: bf08 it eq 8000d28: 4608 moveq r0, r1 8000d2a: 4770 bx lr 8000d2c: ea90 0f01 teq r0, r1 8000d30: bf1c itt ne 8000d32: 2000 movne r0, #0 8000d34: 4770 bxne lr 8000d36: f012 4f7f tst.w r2, #4278190080 ; 0xff000000 8000d3a: d104 bne.n 8000d46 <__addsf3+0x126> 8000d3c: 0040 lsls r0, r0, #1 8000d3e: bf28 it cs 8000d40: f040 4000 orrcs.w r0, r0, #2147483648 ; 0x80000000 8000d44: 4770 bx lr 8000d46: f112 7200 adds.w r2, r2, #33554432 ; 0x2000000 8000d4a: bf3c itt cc 8000d4c: f500 0000 addcc.w r0, r0, #8388608 ; 0x800000 8000d50: 4770 bxcc lr 8000d52: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000 8000d56: f043 40fe orr.w r0, r3, #2130706432 ; 0x7f000000 8000d5a: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000d5e: 4770 bx lr 8000d60: ea7f 6222 mvns.w r2, r2, asr #24 8000d64: bf16 itet ne 8000d66: 4608 movne r0, r1 8000d68: ea7f 6323 mvnseq.w r3, r3, asr #24 8000d6c: 4601 movne r1, r0 8000d6e: 0242 lsls r2, r0, #9 8000d70: bf06 itte eq 8000d72: ea5f 2341 movseq.w r3, r1, lsl #9 8000d76: ea90 0f01 teqeq r0, r1 8000d7a: f440 0080 orrne.w r0, r0, #4194304 ; 0x400000 8000d7e: 4770 bx lr 08000d80 <__aeabi_ui2f>: 8000d80: f04f 0300 mov.w r3, #0 8000d84: e004 b.n 8000d90 <__aeabi_i2f+0x8> 8000d86: bf00 nop 08000d88 <__aeabi_i2f>: 8000d88: f010 4300 ands.w r3, r0, #2147483648 ; 0x80000000 8000d8c: bf48 it mi 8000d8e: 4240 negmi r0, r0 8000d90: ea5f 0c00 movs.w ip, r0 8000d94: bf08 it eq 8000d96: 4770 bxeq lr 8000d98: f043 4396 orr.w r3, r3, #1258291200 ; 0x4b000000 8000d9c: 4601 mov r1, r0 8000d9e: f04f 0000 mov.w r0, #0 8000da2: e01c b.n 8000dde <__aeabi_l2f+0x2a> 08000da4 <__aeabi_ul2f>: 8000da4: ea50 0201 orrs.w r2, r0, r1 8000da8: bf08 it eq 8000daa: 4770 bxeq lr 8000dac: f04f 0300 mov.w r3, #0 8000db0: e00a b.n 8000dc8 <__aeabi_l2f+0x14> 8000db2: bf00 nop 08000db4 <__aeabi_l2f>: 8000db4: ea50 0201 orrs.w r2, r0, r1 8000db8: bf08 it eq 8000dba: 4770 bxeq lr 8000dbc: f011 4300 ands.w r3, r1, #2147483648 ; 0x80000000 8000dc0: d502 bpl.n 8000dc8 <__aeabi_l2f+0x14> 8000dc2: 4240 negs r0, r0 8000dc4: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000dc8: ea5f 0c01 movs.w ip, r1 8000dcc: bf02 ittt eq 8000dce: 4684 moveq ip, r0 8000dd0: 4601 moveq r1, r0 8000dd2: 2000 moveq r0, #0 8000dd4: f043 43b6 orr.w r3, r3, #1526726656 ; 0x5b000000 8000dd8: bf08 it eq 8000dda: f1a3 5380 subeq.w r3, r3, #268435456 ; 0x10000000 8000dde: f5a3 0300 sub.w r3, r3, #8388608 ; 0x800000 8000de2: fabc f28c clz r2, ip 8000de6: 3a08 subs r2, #8 8000de8: eba3 53c2 sub.w r3, r3, r2, lsl #23 8000dec: db10 blt.n 8000e10 <__aeabi_l2f+0x5c> 8000dee: fa01 fc02 lsl.w ip, r1, r2 8000df2: 4463 add r3, ip 8000df4: fa00 fc02 lsl.w ip, r0, r2 8000df8: f1c2 0220 rsb r2, r2, #32 8000dfc: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 8000e00: fa20 f202 lsr.w r2, r0, r2 8000e04: eb43 0002 adc.w r0, r3, r2 8000e08: bf08 it eq 8000e0a: f020 0001 biceq.w r0, r0, #1 8000e0e: 4770 bx lr 8000e10: f102 0220 add.w r2, r2, #32 8000e14: fa01 fc02 lsl.w ip, r1, r2 8000e18: f1c2 0220 rsb r2, r2, #32 8000e1c: ea50 004c orrs.w r0, r0, ip, lsl #1 8000e20: fa21 f202 lsr.w r2, r1, r2 8000e24: eb43 0002 adc.w r0, r3, r2 8000e28: bf08 it eq 8000e2a: ea20 70dc biceq.w r0, r0, ip, lsr #31 8000e2e: 4770 bx lr 08000e30 <__aeabi_fmul>: 8000e30: f04f 0cff mov.w ip, #255 ; 0xff 8000e34: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8000e38: bf1e ittt ne 8000e3a: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8000e3e: ea92 0f0c teqne r2, ip 8000e42: ea93 0f0c teqne r3, ip 8000e46: d06f beq.n 8000f28 <__aeabi_fmul+0xf8> 8000e48: 441a add r2, r3 8000e4a: ea80 0c01 eor.w ip, r0, r1 8000e4e: 0240 lsls r0, r0, #9 8000e50: bf18 it ne 8000e52: ea5f 2141 movsne.w r1, r1, lsl #9 8000e56: d01e beq.n 8000e96 <__aeabi_fmul+0x66> 8000e58: f04f 6300 mov.w r3, #134217728 ; 0x8000000 8000e5c: ea43 1050 orr.w r0, r3, r0, lsr #5 8000e60: ea43 1151 orr.w r1, r3, r1, lsr #5 8000e64: fba0 3101 umull r3, r1, r0, r1 8000e68: f00c 4000 and.w r0, ip, #2147483648 ; 0x80000000 8000e6c: f5b1 0f00 cmp.w r1, #8388608 ; 0x800000 8000e70: bf3e ittt cc 8000e72: 0049 lslcc r1, r1, #1 8000e74: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 8000e78: 005b lslcc r3, r3, #1 8000e7a: ea40 0001 orr.w r0, r0, r1 8000e7e: f162 027f sbc.w r2, r2, #127 ; 0x7f 8000e82: 2afd cmp r2, #253 ; 0xfd 8000e84: d81d bhi.n 8000ec2 <__aeabi_fmul+0x92> 8000e86: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 8000e8a: eb40 50c2 adc.w r0, r0, r2, lsl #23 8000e8e: bf08 it eq 8000e90: f020 0001 biceq.w r0, r0, #1 8000e94: 4770 bx lr 8000e96: f090 0f00 teq r0, #0 8000e9a: f00c 4c00 and.w ip, ip, #2147483648 ; 0x80000000 8000e9e: bf08 it eq 8000ea0: 0249 lsleq r1, r1, #9 8000ea2: ea4c 2050 orr.w r0, ip, r0, lsr #9 8000ea6: ea40 2051 orr.w r0, r0, r1, lsr #9 8000eaa: 3a7f subs r2, #127 ; 0x7f 8000eac: bfc2 ittt gt 8000eae: f1d2 03ff rsbsgt r3, r2, #255 ; 0xff 8000eb2: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8000eb6: 4770 bxgt lr 8000eb8: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000ebc: f04f 0300 mov.w r3, #0 8000ec0: 3a01 subs r2, #1 8000ec2: dc5d bgt.n 8000f80 <__aeabi_fmul+0x150> 8000ec4: f112 0f19 cmn.w r2, #25 8000ec8: bfdc itt le 8000eca: f000 4000 andle.w r0, r0, #2147483648 ; 0x80000000 8000ece: 4770 bxle lr 8000ed0: f1c2 0200 rsb r2, r2, #0 8000ed4: 0041 lsls r1, r0, #1 8000ed6: fa21 f102 lsr.w r1, r1, r2 8000eda: f1c2 0220 rsb r2, r2, #32 8000ede: fa00 fc02 lsl.w ip, r0, r2 8000ee2: ea5f 0031 movs.w r0, r1, rrx 8000ee6: f140 0000 adc.w r0, r0, #0 8000eea: ea53 034c orrs.w r3, r3, ip, lsl #1 8000eee: bf08 it eq 8000ef0: ea20 70dc biceq.w r0, r0, ip, lsr #31 8000ef4: 4770 bx lr 8000ef6: f092 0f00 teq r2, #0 8000efa: f000 4c00 and.w ip, r0, #2147483648 ; 0x80000000 8000efe: bf02 ittt eq 8000f00: 0040 lsleq r0, r0, #1 8000f02: f410 0f00 tsteq.w r0, #8388608 ; 0x800000 8000f06: 3a01 subeq r2, #1 8000f08: d0f9 beq.n 8000efe <__aeabi_fmul+0xce> 8000f0a: ea40 000c orr.w r0, r0, ip 8000f0e: f093 0f00 teq r3, #0 8000f12: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 8000f16: bf02 ittt eq 8000f18: 0049 lsleq r1, r1, #1 8000f1a: f411 0f00 tsteq.w r1, #8388608 ; 0x800000 8000f1e: 3b01 subeq r3, #1 8000f20: d0f9 beq.n 8000f16 <__aeabi_fmul+0xe6> 8000f22: ea41 010c orr.w r1, r1, ip 8000f26: e78f b.n 8000e48 <__aeabi_fmul+0x18> 8000f28: ea0c 53d1 and.w r3, ip, r1, lsr #23 8000f2c: ea92 0f0c teq r2, ip 8000f30: bf18 it ne 8000f32: ea93 0f0c teqne r3, ip 8000f36: d00a beq.n 8000f4e <__aeabi_fmul+0x11e> 8000f38: f030 4c00 bics.w ip, r0, #2147483648 ; 0x80000000 8000f3c: bf18 it ne 8000f3e: f031 4c00 bicsne.w ip, r1, #2147483648 ; 0x80000000 8000f42: d1d8 bne.n 8000ef6 <__aeabi_fmul+0xc6> 8000f44: ea80 0001 eor.w r0, r0, r1 8000f48: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000 8000f4c: 4770 bx lr 8000f4e: f090 0f00 teq r0, #0 8000f52: bf17 itett ne 8000f54: f090 4f00 teqne r0, #2147483648 ; 0x80000000 8000f58: 4608 moveq r0, r1 8000f5a: f091 0f00 teqne r1, #0 8000f5e: f091 4f00 teqne r1, #2147483648 ; 0x80000000 8000f62: d014 beq.n 8000f8e <__aeabi_fmul+0x15e> 8000f64: ea92 0f0c teq r2, ip 8000f68: d101 bne.n 8000f6e <__aeabi_fmul+0x13e> 8000f6a: 0242 lsls r2, r0, #9 8000f6c: d10f bne.n 8000f8e <__aeabi_fmul+0x15e> 8000f6e: ea93 0f0c teq r3, ip 8000f72: d103 bne.n 8000f7c <__aeabi_fmul+0x14c> 8000f74: 024b lsls r3, r1, #9 8000f76: bf18 it ne 8000f78: 4608 movne r0, r1 8000f7a: d108 bne.n 8000f8e <__aeabi_fmul+0x15e> 8000f7c: ea80 0001 eor.w r0, r0, r1 8000f80: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000 8000f84: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 8000f88: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000f8c: 4770 bx lr 8000f8e: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 8000f92: f440 0040 orr.w r0, r0, #12582912 ; 0xc00000 8000f96: 4770 bx lr 08000f98 <__aeabi_fdiv>: 8000f98: f04f 0cff mov.w ip, #255 ; 0xff 8000f9c: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8000fa0: bf1e ittt ne 8000fa2: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8000fa6: ea92 0f0c teqne r2, ip 8000faa: ea93 0f0c teqne r3, ip 8000fae: d069 beq.n 8001084 <__aeabi_fdiv+0xec> 8000fb0: eba2 0203 sub.w r2, r2, r3 8000fb4: ea80 0c01 eor.w ip, r0, r1 8000fb8: 0249 lsls r1, r1, #9 8000fba: ea4f 2040 mov.w r0, r0, lsl #9 8000fbe: d037 beq.n 8001030 <__aeabi_fdiv+0x98> 8000fc0: f04f 5380 mov.w r3, #268435456 ; 0x10000000 8000fc4: ea43 1111 orr.w r1, r3, r1, lsr #4 8000fc8: ea43 1310 orr.w r3, r3, r0, lsr #4 8000fcc: f00c 4000 and.w r0, ip, #2147483648 ; 0x80000000 8000fd0: 428b cmp r3, r1 8000fd2: bf38 it cc 8000fd4: 005b lslcc r3, r3, #1 8000fd6: f142 027d adc.w r2, r2, #125 ; 0x7d 8000fda: f44f 0c00 mov.w ip, #8388608 ; 0x800000 8000fde: 428b cmp r3, r1 8000fe0: bf24 itt cs 8000fe2: 1a5b subcs r3, r3, r1 8000fe4: ea40 000c orrcs.w r0, r0, ip 8000fe8: ebb3 0f51 cmp.w r3, r1, lsr #1 8000fec: bf24 itt cs 8000fee: eba3 0351 subcs.w r3, r3, r1, lsr #1 8000ff2: ea40 005c orrcs.w r0, r0, ip, lsr #1 8000ff6: ebb3 0f91 cmp.w r3, r1, lsr #2 8000ffa: bf24 itt cs 8000ffc: eba3 0391 subcs.w r3, r3, r1, lsr #2 8001000: ea40 009c orrcs.w r0, r0, ip, lsr #2 8001004: ebb3 0fd1 cmp.w r3, r1, lsr #3 8001008: bf24 itt cs 800100a: eba3 03d1 subcs.w r3, r3, r1, lsr #3 800100e: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8001012: 011b lsls r3, r3, #4 8001014: bf18 it ne 8001016: ea5f 1c1c movsne.w ip, ip, lsr #4 800101a: d1e0 bne.n 8000fde <__aeabi_fdiv+0x46> 800101c: 2afd cmp r2, #253 ; 0xfd 800101e: f63f af50 bhi.w 8000ec2 <__aeabi_fmul+0x92> 8001022: 428b cmp r3, r1 8001024: eb40 50c2 adc.w r0, r0, r2, lsl #23 8001028: bf08 it eq 800102a: f020 0001 biceq.w r0, r0, #1 800102e: 4770 bx lr 8001030: f00c 4c00 and.w ip, ip, #2147483648 ; 0x80000000 8001034: ea4c 2050 orr.w r0, ip, r0, lsr #9 8001038: 327f adds r2, #127 ; 0x7f 800103a: bfc2 ittt gt 800103c: f1d2 03ff rsbsgt r3, r2, #255 ; 0xff 8001040: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8001044: 4770 bxgt lr 8001046: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 800104a: f04f 0300 mov.w r3, #0 800104e: 3a01 subs r2, #1 8001050: e737 b.n 8000ec2 <__aeabi_fmul+0x92> 8001052: f092 0f00 teq r2, #0 8001056: f000 4c00 and.w ip, r0, #2147483648 ; 0x80000000 800105a: bf02 ittt eq 800105c: 0040 lsleq r0, r0, #1 800105e: f410 0f00 tsteq.w r0, #8388608 ; 0x800000 8001062: 3a01 subeq r2, #1 8001064: d0f9 beq.n 800105a <__aeabi_fdiv+0xc2> 8001066: ea40 000c orr.w r0, r0, ip 800106a: f093 0f00 teq r3, #0 800106e: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 8001072: bf02 ittt eq 8001074: 0049 lsleq r1, r1, #1 8001076: f411 0f00 tsteq.w r1, #8388608 ; 0x800000 800107a: 3b01 subeq r3, #1 800107c: d0f9 beq.n 8001072 <__aeabi_fdiv+0xda> 800107e: ea41 010c orr.w r1, r1, ip 8001082: e795 b.n 8000fb0 <__aeabi_fdiv+0x18> 8001084: ea0c 53d1 and.w r3, ip, r1, lsr #23 8001088: ea92 0f0c teq r2, ip 800108c: d108 bne.n 80010a0 <__aeabi_fdiv+0x108> 800108e: 0242 lsls r2, r0, #9 8001090: f47f af7d bne.w 8000f8e <__aeabi_fmul+0x15e> 8001094: ea93 0f0c teq r3, ip 8001098: f47f af70 bne.w 8000f7c <__aeabi_fmul+0x14c> 800109c: 4608 mov r0, r1 800109e: e776 b.n 8000f8e <__aeabi_fmul+0x15e> 80010a0: ea93 0f0c teq r3, ip 80010a4: d104 bne.n 80010b0 <__aeabi_fdiv+0x118> 80010a6: 024b lsls r3, r1, #9 80010a8: f43f af4c beq.w 8000f44 <__aeabi_fmul+0x114> 80010ac: 4608 mov r0, r1 80010ae: e76e b.n 8000f8e <__aeabi_fmul+0x15e> 80010b0: f030 4c00 bics.w ip, r0, #2147483648 ; 0x80000000 80010b4: bf18 it ne 80010b6: f031 4c00 bicsne.w ip, r1, #2147483648 ; 0x80000000 80010ba: d1ca bne.n 8001052 <__aeabi_fdiv+0xba> 80010bc: f030 4200 bics.w r2, r0, #2147483648 ; 0x80000000 80010c0: f47f af5c bne.w 8000f7c <__aeabi_fmul+0x14c> 80010c4: f031 4300 bics.w r3, r1, #2147483648 ; 0x80000000 80010c8: f47f af3c bne.w 8000f44 <__aeabi_fmul+0x114> 80010cc: e75f b.n 8000f8e <__aeabi_fmul+0x15e> 80010ce: bf00 nop 080010d0 <__gesf2>: 80010d0: f04f 3cff mov.w ip, #4294967295 ; 0xffffffff 80010d4: e006 b.n 80010e4 <__cmpsf2+0x4> 80010d6: bf00 nop 080010d8 <__lesf2>: 80010d8: f04f 0c01 mov.w ip, #1 80010dc: e002 b.n 80010e4 <__cmpsf2+0x4> 80010de: bf00 nop 080010e0 <__cmpsf2>: 80010e0: f04f 0c01 mov.w ip, #1 80010e4: f84d cd04 str.w ip, [sp, #-4]! 80010e8: ea4f 0240 mov.w r2, r0, lsl #1 80010ec: ea4f 0341 mov.w r3, r1, lsl #1 80010f0: ea7f 6c22 mvns.w ip, r2, asr #24 80010f4: bf18 it ne 80010f6: ea7f 6c23 mvnsne.w ip, r3, asr #24 80010fa: d011 beq.n 8001120 <__cmpsf2+0x40> 80010fc: b001 add sp, #4 80010fe: ea52 0c53 orrs.w ip, r2, r3, lsr #1 8001102: bf18 it ne 8001104: ea90 0f01 teqne r0, r1 8001108: bf58 it pl 800110a: ebb2 0003 subspl.w r0, r2, r3 800110e: bf88 it hi 8001110: 17c8 asrhi r0, r1, #31 8001112: bf38 it cc 8001114: ea6f 70e1 mvncc.w r0, r1, asr #31 8001118: bf18 it ne 800111a: f040 0001 orrne.w r0, r0, #1 800111e: 4770 bx lr 8001120: ea7f 6c22 mvns.w ip, r2, asr #24 8001124: d102 bne.n 800112c <__cmpsf2+0x4c> 8001126: ea5f 2c40 movs.w ip, r0, lsl #9 800112a: d105 bne.n 8001138 <__cmpsf2+0x58> 800112c: ea7f 6c23 mvns.w ip, r3, asr #24 8001130: d1e4 bne.n 80010fc <__cmpsf2+0x1c> 8001132: ea5f 2c41 movs.w ip, r1, lsl #9 8001136: d0e1 beq.n 80010fc <__cmpsf2+0x1c> 8001138: f85d 0b04 ldr.w r0, [sp], #4 800113c: 4770 bx lr 800113e: bf00 nop 08001140 <__aeabi_cfrcmple>: 8001140: 4684 mov ip, r0 8001142: 4608 mov r0, r1 8001144: 4661 mov r1, ip 8001146: e7ff b.n 8001148 <__aeabi_cfcmpeq> 08001148 <__aeabi_cfcmpeq>: 8001148: b50f push {r0, r1, r2, r3, lr} 800114a: f7ff ffc9 bl 80010e0 <__cmpsf2> 800114e: 2800 cmp r0, #0 8001150: bf48 it mi 8001152: f110 0f00 cmnmi.w r0, #0 8001156: bd0f pop {r0, r1, r2, r3, pc} 08001158 <__aeabi_fcmpeq>: 8001158: f84d ed08 str.w lr, [sp, #-8]! 800115c: f7ff fff4 bl 8001148 <__aeabi_cfcmpeq> 8001160: bf0c ite eq 8001162: 2001 moveq r0, #1 8001164: 2000 movne r0, #0 8001166: f85d fb08 ldr.w pc, [sp], #8 800116a: bf00 nop 0800116c <__aeabi_fcmplt>: 800116c: f84d ed08 str.w lr, [sp, #-8]! 8001170: f7ff ffea bl 8001148 <__aeabi_cfcmpeq> 8001174: bf34 ite cc 8001176: 2001 movcc r0, #1 8001178: 2000 movcs r0, #0 800117a: f85d fb08 ldr.w pc, [sp], #8 800117e: bf00 nop 08001180 <__aeabi_fcmple>: 8001180: f84d ed08 str.w lr, [sp, #-8]! 8001184: f7ff ffe0 bl 8001148 <__aeabi_cfcmpeq> 8001188: bf94 ite ls 800118a: 2001 movls r0, #1 800118c: 2000 movhi r0, #0 800118e: f85d fb08 ldr.w pc, [sp], #8 8001192: bf00 nop 08001194 <__aeabi_fcmpge>: 8001194: f84d ed08 str.w lr, [sp, #-8]! 8001198: f7ff ffd2 bl 8001140 <__aeabi_cfrcmple> 800119c: bf94 ite ls 800119e: 2001 movls r0, #1 80011a0: 2000 movhi r0, #0 80011a2: f85d fb08 ldr.w pc, [sp], #8 80011a6: bf00 nop 080011a8 <__aeabi_fcmpgt>: 80011a8: f84d ed08 str.w lr, [sp, #-8]! 80011ac: f7ff ffc8 bl 8001140 <__aeabi_cfrcmple> 80011b0: bf34 ite cc 80011b2: 2001 movcc r0, #1 80011b4: 2000 movcs r0, #0 80011b6: f85d fb08 ldr.w pc, [sp], #8 80011ba: bf00 nop 080011bc <__aeabi_f2iz>: 80011bc: ea4f 0240 mov.w r2, r0, lsl #1 80011c0: f1b2 4ffe cmp.w r2, #2130706432 ; 0x7f000000 80011c4: d30f bcc.n 80011e6 <__aeabi_f2iz+0x2a> 80011c6: f04f 039e mov.w r3, #158 ; 0x9e 80011ca: ebb3 6212 subs.w r2, r3, r2, lsr #24 80011ce: d90d bls.n 80011ec <__aeabi_f2iz+0x30> 80011d0: ea4f 2300 mov.w r3, r0, lsl #8 80011d4: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 80011d8: f010 4f00 tst.w r0, #2147483648 ; 0x80000000 80011dc: fa23 f002 lsr.w r0, r3, r2 80011e0: bf18 it ne 80011e2: 4240 negne r0, r0 80011e4: 4770 bx lr 80011e6: f04f 0000 mov.w r0, #0 80011ea: 4770 bx lr 80011ec: f112 0f61 cmn.w r2, #97 ; 0x61 80011f0: d101 bne.n 80011f6 <__aeabi_f2iz+0x3a> 80011f2: 0242 lsls r2, r0, #9 80011f4: d105 bne.n 8001202 <__aeabi_f2iz+0x46> 80011f6: f010 4000 ands.w r0, r0, #2147483648 ; 0x80000000 80011fa: bf08 it eq 80011fc: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 8001200: 4770 bx lr 8001202: f04f 0000 mov.w r0, #0 8001206: 4770 bx lr 08001208 <__aeabi_ldivmod>: 8001208: b97b cbnz r3, 800122a <__aeabi_ldivmod+0x22> 800120a: b972 cbnz r2, 800122a <__aeabi_ldivmod+0x22> 800120c: 2900 cmp r1, #0 800120e: bfbe ittt lt 8001210: 2000 movlt r0, #0 8001212: f04f 4100 movlt.w r1, #2147483648 ; 0x80000000 8001216: e006 blt.n 8001226 <__aeabi_ldivmod+0x1e> 8001218: bf08 it eq 800121a: 2800 cmpeq r0, #0 800121c: bf1c itt ne 800121e: f06f 4100 mvnne.w r1, #2147483648 ; 0x80000000 8001222: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff 8001226: f000 b9c1 b.w 80015ac <__aeabi_idiv0> 800122a: f1ad 0c08 sub.w ip, sp, #8 800122e: e96d ce04 strd ip, lr, [sp, #-16]! 8001232: 2900 cmp r1, #0 8001234: db09 blt.n 800124a <__aeabi_ldivmod+0x42> 8001236: 2b00 cmp r3, #0 8001238: db1a blt.n 8001270 <__aeabi_ldivmod+0x68> 800123a: f000 f84d bl 80012d8 <__udivmoddi4> 800123e: f8dd e004 ldr.w lr, [sp, #4] 8001242: e9dd 2302 ldrd r2, r3, [sp, #8] 8001246: b004 add sp, #16 8001248: 4770 bx lr 800124a: 4240 negs r0, r0 800124c: eb61 0141 sbc.w r1, r1, r1, lsl #1 8001250: 2b00 cmp r3, #0 8001252: db1b blt.n 800128c <__aeabi_ldivmod+0x84> 8001254: f000 f840 bl 80012d8 <__udivmoddi4> 8001258: f8dd e004 ldr.w lr, [sp, #4] 800125c: e9dd 2302 ldrd r2, r3, [sp, #8] 8001260: b004 add sp, #16 8001262: 4240 negs r0, r0 8001264: eb61 0141 sbc.w r1, r1, r1, lsl #1 8001268: 4252 negs r2, r2 800126a: eb63 0343 sbc.w r3, r3, r3, lsl #1 800126e: 4770 bx lr 8001270: 4252 negs r2, r2 8001272: eb63 0343 sbc.w r3, r3, r3, lsl #1 8001276: f000 f82f bl 80012d8 <__udivmoddi4> 800127a: f8dd e004 ldr.w lr, [sp, #4] 800127e: e9dd 2302 ldrd r2, r3, [sp, #8] 8001282: b004 add sp, #16 8001284: 4240 negs r0, r0 8001286: eb61 0141 sbc.w r1, r1, r1, lsl #1 800128a: 4770 bx lr 800128c: 4252 negs r2, r2 800128e: eb63 0343 sbc.w r3, r3, r3, lsl #1 8001292: f000 f821 bl 80012d8 <__udivmoddi4> 8001296: f8dd e004 ldr.w lr, [sp, #4] 800129a: e9dd 2302 ldrd r2, r3, [sp, #8] 800129e: b004 add sp, #16 80012a0: 4252 negs r2, r2 80012a2: eb63 0343 sbc.w r3, r3, r3, lsl #1 80012a6: 4770 bx lr 080012a8 <__aeabi_uldivmod>: 80012a8: b953 cbnz r3, 80012c0 <__aeabi_uldivmod+0x18> 80012aa: b94a cbnz r2, 80012c0 <__aeabi_uldivmod+0x18> 80012ac: 2900 cmp r1, #0 80012ae: bf08 it eq 80012b0: 2800 cmpeq r0, #0 80012b2: bf1c itt ne 80012b4: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff 80012b8: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff 80012bc: f000 b976 b.w 80015ac <__aeabi_idiv0> 80012c0: f1ad 0c08 sub.w ip, sp, #8 80012c4: e96d ce04 strd ip, lr, [sp, #-16]! 80012c8: f000 f806 bl 80012d8 <__udivmoddi4> 80012cc: f8dd e004 ldr.w lr, [sp, #4] 80012d0: e9dd 2302 ldrd r2, r3, [sp, #8] 80012d4: b004 add sp, #16 80012d6: 4770 bx lr 080012d8 <__udivmoddi4>: 80012d8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80012dc: 9e08 ldr r6, [sp, #32] 80012de: 460d mov r5, r1 80012e0: 4604 mov r4, r0 80012e2: 4688 mov r8, r1 80012e4: 2b00 cmp r3, #0 80012e6: d14d bne.n 8001384 <__udivmoddi4+0xac> 80012e8: 428a cmp r2, r1 80012ea: 4694 mov ip, r2 80012ec: d968 bls.n 80013c0 <__udivmoddi4+0xe8> 80012ee: fab2 f282 clz r2, r2 80012f2: b152 cbz r2, 800130a <__udivmoddi4+0x32> 80012f4: fa01 f302 lsl.w r3, r1, r2 80012f8: f1c2 0120 rsb r1, r2, #32 80012fc: fa20 f101 lsr.w r1, r0, r1 8001300: fa0c fc02 lsl.w ip, ip, r2 8001304: ea41 0803 orr.w r8, r1, r3 8001308: 4094 lsls r4, r2 800130a: ea4f 411c mov.w r1, ip, lsr #16 800130e: fbb8 f7f1 udiv r7, r8, r1 8001312: fa1f fe8c uxth.w lr, ip 8001316: fb01 8817 mls r8, r1, r7, r8 800131a: fb07 f00e mul.w r0, r7, lr 800131e: 0c23 lsrs r3, r4, #16 8001320: ea43 4308 orr.w r3, r3, r8, lsl #16 8001324: 4298 cmp r0, r3 8001326: d90a bls.n 800133e <__udivmoddi4+0x66> 8001328: eb1c 0303 adds.w r3, ip, r3 800132c: f107 35ff add.w r5, r7, #4294967295 ; 0xffffffff 8001330: f080 811e bcs.w 8001570 <__udivmoddi4+0x298> 8001334: 4298 cmp r0, r3 8001336: f240 811b bls.w 8001570 <__udivmoddi4+0x298> 800133a: 3f02 subs r7, #2 800133c: 4463 add r3, ip 800133e: 1a1b subs r3, r3, r0 8001340: fbb3 f0f1 udiv r0, r3, r1 8001344: fb01 3310 mls r3, r1, r0, r3 8001348: fb00 fe0e mul.w lr, r0, lr 800134c: b2a4 uxth r4, r4 800134e: ea44 4403 orr.w r4, r4, r3, lsl #16 8001352: 45a6 cmp lr, r4 8001354: d90a bls.n 800136c <__udivmoddi4+0x94> 8001356: eb1c 0404 adds.w r4, ip, r4 800135a: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff 800135e: f080 8109 bcs.w 8001574 <__udivmoddi4+0x29c> 8001362: 45a6 cmp lr, r4 8001364: f240 8106 bls.w 8001574 <__udivmoddi4+0x29c> 8001368: 4464 add r4, ip 800136a: 3802 subs r0, #2 800136c: 2100 movs r1, #0 800136e: eba4 040e sub.w r4, r4, lr 8001372: ea40 4007 orr.w r0, r0, r7, lsl #16 8001376: b11e cbz r6, 8001380 <__udivmoddi4+0xa8> 8001378: 2300 movs r3, #0 800137a: 40d4 lsrs r4, r2 800137c: e9c6 4300 strd r4, r3, [r6] 8001380: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8001384: 428b cmp r3, r1 8001386: d908 bls.n 800139a <__udivmoddi4+0xc2> 8001388: 2e00 cmp r6, #0 800138a: f000 80ee beq.w 800156a <__udivmoddi4+0x292> 800138e: 2100 movs r1, #0 8001390: e9c6 0500 strd r0, r5, [r6] 8001394: 4608 mov r0, r1 8001396: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800139a: fab3 f183 clz r1, r3 800139e: 2900 cmp r1, #0 80013a0: d14a bne.n 8001438 <__udivmoddi4+0x160> 80013a2: 42ab cmp r3, r5 80013a4: d302 bcc.n 80013ac <__udivmoddi4+0xd4> 80013a6: 4282 cmp r2, r0 80013a8: f200 80fc bhi.w 80015a4 <__udivmoddi4+0x2cc> 80013ac: 1a84 subs r4, r0, r2 80013ae: eb65 0303 sbc.w r3, r5, r3 80013b2: 2001 movs r0, #1 80013b4: 4698 mov r8, r3 80013b6: 2e00 cmp r6, #0 80013b8: d0e2 beq.n 8001380 <__udivmoddi4+0xa8> 80013ba: e9c6 4800 strd r4, r8, [r6] 80013be: e7df b.n 8001380 <__udivmoddi4+0xa8> 80013c0: b902 cbnz r2, 80013c4 <__udivmoddi4+0xec> 80013c2: deff udf #255 ; 0xff 80013c4: fab2 f282 clz r2, r2 80013c8: 2a00 cmp r2, #0 80013ca: f040 8091 bne.w 80014f0 <__udivmoddi4+0x218> 80013ce: eba1 000c sub.w r0, r1, ip 80013d2: 2101 movs r1, #1 80013d4: ea4f 471c mov.w r7, ip, lsr #16 80013d8: fa1f fe8c uxth.w lr, ip 80013dc: fbb0 f3f7 udiv r3, r0, r7 80013e0: fb07 0013 mls r0, r7, r3, r0 80013e4: 0c25 lsrs r5, r4, #16 80013e6: ea45 4500 orr.w r5, r5, r0, lsl #16 80013ea: fb0e f003 mul.w r0, lr, r3 80013ee: 42a8 cmp r0, r5 80013f0: d908 bls.n 8001404 <__udivmoddi4+0x12c> 80013f2: eb1c 0505 adds.w r5, ip, r5 80013f6: f103 38ff add.w r8, r3, #4294967295 ; 0xffffffff 80013fa: d202 bcs.n 8001402 <__udivmoddi4+0x12a> 80013fc: 42a8 cmp r0, r5 80013fe: f200 80ce bhi.w 800159e <__udivmoddi4+0x2c6> 8001402: 4643 mov r3, r8 8001404: 1a2d subs r5, r5, r0 8001406: fbb5 f0f7 udiv r0, r5, r7 800140a: fb07 5510 mls r5, r7, r0, r5 800140e: fb0e fe00 mul.w lr, lr, r0 8001412: b2a4 uxth r4, r4 8001414: ea44 4405 orr.w r4, r4, r5, lsl #16 8001418: 45a6 cmp lr, r4 800141a: d908 bls.n 800142e <__udivmoddi4+0x156> 800141c: eb1c 0404 adds.w r4, ip, r4 8001420: f100 35ff add.w r5, r0, #4294967295 ; 0xffffffff 8001424: d202 bcs.n 800142c <__udivmoddi4+0x154> 8001426: 45a6 cmp lr, r4 8001428: f200 80b6 bhi.w 8001598 <__udivmoddi4+0x2c0> 800142c: 4628 mov r0, r5 800142e: eba4 040e sub.w r4, r4, lr 8001432: ea40 4003 orr.w r0, r0, r3, lsl #16 8001436: e79e b.n 8001376 <__udivmoddi4+0x9e> 8001438: f1c1 0720 rsb r7, r1, #32 800143c: 408b lsls r3, r1 800143e: fa22 fc07 lsr.w ip, r2, r7 8001442: ea4c 0c03 orr.w ip, ip, r3 8001446: fa25 fa07 lsr.w sl, r5, r7 800144a: ea4f 491c mov.w r9, ip, lsr #16 800144e: fbba f8f9 udiv r8, sl, r9 8001452: fa20 f307 lsr.w r3, r0, r7 8001456: fb09 aa18 mls sl, r9, r8, sl 800145a: 408d lsls r5, r1 800145c: fa1f fe8c uxth.w lr, ip 8001460: 431d orrs r5, r3 8001462: fa00 f301 lsl.w r3, r0, r1 8001466: fb08 f00e mul.w r0, r8, lr 800146a: 0c2c lsrs r4, r5, #16 800146c: ea44 440a orr.w r4, r4, sl, lsl #16 8001470: 42a0 cmp r0, r4 8001472: fa02 f201 lsl.w r2, r2, r1 8001476: d90b bls.n 8001490 <__udivmoddi4+0x1b8> 8001478: eb1c 0404 adds.w r4, ip, r4 800147c: f108 3aff add.w sl, r8, #4294967295 ; 0xffffffff 8001480: f080 8088 bcs.w 8001594 <__udivmoddi4+0x2bc> 8001484: 42a0 cmp r0, r4 8001486: f240 8085 bls.w 8001594 <__udivmoddi4+0x2bc> 800148a: f1a8 0802 sub.w r8, r8, #2 800148e: 4464 add r4, ip 8001490: 1a24 subs r4, r4, r0 8001492: fbb4 f0f9 udiv r0, r4, r9 8001496: fb09 4410 mls r4, r9, r0, r4 800149a: fb00 fe0e mul.w lr, r0, lr 800149e: b2ad uxth r5, r5 80014a0: ea45 4404 orr.w r4, r5, r4, lsl #16 80014a4: 45a6 cmp lr, r4 80014a6: d908 bls.n 80014ba <__udivmoddi4+0x1e2> 80014a8: eb1c 0404 adds.w r4, ip, r4 80014ac: f100 35ff add.w r5, r0, #4294967295 ; 0xffffffff 80014b0: d26c bcs.n 800158c <__udivmoddi4+0x2b4> 80014b2: 45a6 cmp lr, r4 80014b4: d96a bls.n 800158c <__udivmoddi4+0x2b4> 80014b6: 3802 subs r0, #2 80014b8: 4464 add r4, ip 80014ba: ea40 4008 orr.w r0, r0, r8, lsl #16 80014be: fba0 9502 umull r9, r5, r0, r2 80014c2: eba4 040e sub.w r4, r4, lr 80014c6: 42ac cmp r4, r5 80014c8: 46c8 mov r8, r9 80014ca: 46ae mov lr, r5 80014cc: d356 bcc.n 800157c <__udivmoddi4+0x2a4> 80014ce: d053 beq.n 8001578 <__udivmoddi4+0x2a0> 80014d0: 2e00 cmp r6, #0 80014d2: d069 beq.n 80015a8 <__udivmoddi4+0x2d0> 80014d4: ebb3 0208 subs.w r2, r3, r8 80014d8: eb64 040e sbc.w r4, r4, lr 80014dc: fa22 f301 lsr.w r3, r2, r1 80014e0: fa04 f707 lsl.w r7, r4, r7 80014e4: 431f orrs r7, r3 80014e6: 40cc lsrs r4, r1 80014e8: e9c6 7400 strd r7, r4, [r6] 80014ec: 2100 movs r1, #0 80014ee: e747 b.n 8001380 <__udivmoddi4+0xa8> 80014f0: fa0c fc02 lsl.w ip, ip, r2 80014f4: f1c2 0120 rsb r1, r2, #32 80014f8: fa25 f301 lsr.w r3, r5, r1 80014fc: ea4f 471c mov.w r7, ip, lsr #16 8001500: fa20 f101 lsr.w r1, r0, r1 8001504: 4095 lsls r5, r2 8001506: 430d orrs r5, r1 8001508: fbb3 f1f7 udiv r1, r3, r7 800150c: fb07 3311 mls r3, r7, r1, r3 8001510: fa1f fe8c uxth.w lr, ip 8001514: 0c28 lsrs r0, r5, #16 8001516: ea40 4003 orr.w r0, r0, r3, lsl #16 800151a: fb01 f30e mul.w r3, r1, lr 800151e: 4283 cmp r3, r0 8001520: fa04 f402 lsl.w r4, r4, r2 8001524: d908 bls.n 8001538 <__udivmoddi4+0x260> 8001526: eb1c 0000 adds.w r0, ip, r0 800152a: f101 38ff add.w r8, r1, #4294967295 ; 0xffffffff 800152e: d22f bcs.n 8001590 <__udivmoddi4+0x2b8> 8001530: 4283 cmp r3, r0 8001532: d92d bls.n 8001590 <__udivmoddi4+0x2b8> 8001534: 3902 subs r1, #2 8001536: 4460 add r0, ip 8001538: 1ac0 subs r0, r0, r3 800153a: fbb0 f3f7 udiv r3, r0, r7 800153e: fb07 0013 mls r0, r7, r3, r0 8001542: b2ad uxth r5, r5 8001544: ea45 4500 orr.w r5, r5, r0, lsl #16 8001548: fb03 f00e mul.w r0, r3, lr 800154c: 42a8 cmp r0, r5 800154e: d908 bls.n 8001562 <__udivmoddi4+0x28a> 8001550: eb1c 0505 adds.w r5, ip, r5 8001554: f103 38ff add.w r8, r3, #4294967295 ; 0xffffffff 8001558: d216 bcs.n 8001588 <__udivmoddi4+0x2b0> 800155a: 42a8 cmp r0, r5 800155c: d914 bls.n 8001588 <__udivmoddi4+0x2b0> 800155e: 3b02 subs r3, #2 8001560: 4465 add r5, ip 8001562: 1a28 subs r0, r5, r0 8001564: ea43 4101 orr.w r1, r3, r1, lsl #16 8001568: e738 b.n 80013dc <__udivmoddi4+0x104> 800156a: 4631 mov r1, r6 800156c: 4630 mov r0, r6 800156e: e707 b.n 8001380 <__udivmoddi4+0xa8> 8001570: 462f mov r7, r5 8001572: e6e4 b.n 800133e <__udivmoddi4+0x66> 8001574: 4618 mov r0, r3 8001576: e6f9 b.n 800136c <__udivmoddi4+0x94> 8001578: 454b cmp r3, r9 800157a: d2a9 bcs.n 80014d0 <__udivmoddi4+0x1f8> 800157c: ebb9 0802 subs.w r8, r9, r2 8001580: eb65 0e0c sbc.w lr, r5, ip 8001584: 3801 subs r0, #1 8001586: e7a3 b.n 80014d0 <__udivmoddi4+0x1f8> 8001588: 4643 mov r3, r8 800158a: e7ea b.n 8001562 <__udivmoddi4+0x28a> 800158c: 4628 mov r0, r5 800158e: e794 b.n 80014ba <__udivmoddi4+0x1e2> 8001590: 4641 mov r1, r8 8001592: e7d1 b.n 8001538 <__udivmoddi4+0x260> 8001594: 46d0 mov r8, sl 8001596: e77b b.n 8001490 <__udivmoddi4+0x1b8> 8001598: 4464 add r4, ip 800159a: 3802 subs r0, #2 800159c: e747 b.n 800142e <__udivmoddi4+0x156> 800159e: 3b02 subs r3, #2 80015a0: 4465 add r5, ip 80015a2: e72f b.n 8001404 <__udivmoddi4+0x12c> 80015a4: 4608 mov r0, r1 80015a6: e706 b.n 80013b6 <__udivmoddi4+0xde> 80015a8: 4631 mov r1, r6 80015aa: e6e9 b.n 8001380 <__udivmoddi4+0xa8> 080015ac <__aeabi_idiv0>: 80015ac: 4770 bx lr 80015ae: bf00 nop 080015b0 : ADC_HandleTypeDef hadc1; /* ADC1 init function */ void MX_ADC1_Init(void) { 80015b0: b580 push {r7, lr} 80015b2: b084 sub sp, #16 80015b4: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 80015b6: 1d3b adds r3, r7, #4 80015b8: 2200 movs r2, #0 80015ba: 601a str r2, [r3, #0] 80015bc: 605a str r2, [r3, #4] 80015be: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 80015c0: 4b18 ldr r3, [pc, #96] ; (8001624 ) 80015c2: 4a19 ldr r2, [pc, #100] ; (8001628 ) 80015c4: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 80015c6: 4b17 ldr r3, [pc, #92] ; (8001624 ) 80015c8: 2200 movs r2, #0 80015ca: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = DISABLE; 80015cc: 4b15 ldr r3, [pc, #84] ; (8001624 ) 80015ce: 2200 movs r2, #0 80015d0: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 80015d2: 4b14 ldr r3, [pc, #80] ; (8001624 ) 80015d4: 2200 movs r2, #0 80015d6: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 80015d8: 4b12 ldr r3, [pc, #72] ; (8001624 ) 80015da: f44f 2260 mov.w r2, #917504 ; 0xe0000 80015de: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80015e0: 4b10 ldr r3, [pc, #64] ; (8001624 ) 80015e2: 2200 movs r2, #0 80015e4: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 1; 80015e6: 4b0f ldr r3, [pc, #60] ; (8001624 ) 80015e8: 2201 movs r2, #1 80015ea: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 80015ec: 480d ldr r0, [pc, #52] ; (8001624 ) 80015ee: f003 fdff bl 80051f0 80015f2: 4603 mov r3, r0 80015f4: 2b00 cmp r3, #0 80015f6: d001 beq.n 80015fc { Error_Handler(); 80015f8: f003 f9a8 bl 800494c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 80015fc: 2308 movs r3, #8 80015fe: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8001600: 2301 movs r3, #1 8001602: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 8001604: 2300 movs r3, #0 8001606: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8001608: 1d3b adds r3, r7, #4 800160a: 4619 mov r1, r3 800160c: 4805 ldr r0, [pc, #20] ; (8001624 ) 800160e: f004 f8b3 bl 8005778 8001612: 4603 mov r3, r0 8001614: 2b00 cmp r3, #0 8001616: d001 beq.n 800161c { Error_Handler(); 8001618: f003 f998 bl 800494c } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 800161c: bf00 nop 800161e: 3710 adds r7, #16 8001620: 46bd mov sp, r7 8001622: bd80 pop {r7, pc} 8001624: 20000260 .word 0x20000260 8001628: 40012400 .word 0x40012400 0800162c : void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 800162c: b580 push {r7, lr} 800162e: b08a sub sp, #40 ; 0x28 8001630: af00 add r7, sp, #0 8001632: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001634: f107 0318 add.w r3, r7, #24 8001638: 2200 movs r2, #0 800163a: 601a str r2, [r3, #0] 800163c: 605a str r2, [r3, #4] 800163e: 609a str r2, [r3, #8] 8001640: 60da str r2, [r3, #12] if(adcHandle->Instance==ADC1) 8001642: 687b ldr r3, [r7, #4] 8001644: 681b ldr r3, [r3, #0] 8001646: 4a1f ldr r2, [pc, #124] ; (80016c4 ) 8001648: 4293 cmp r3, r2 800164a: d137 bne.n 80016bc { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 800164c: 4b1e ldr r3, [pc, #120] ; (80016c8 ) 800164e: 699b ldr r3, [r3, #24] 8001650: 4a1d ldr r2, [pc, #116] ; (80016c8 ) 8001652: f443 7300 orr.w r3, r3, #512 ; 0x200 8001656: 6193 str r3, [r2, #24] 8001658: 4b1b ldr r3, [pc, #108] ; (80016c8 ) 800165a: 699b ldr r3, [r3, #24] 800165c: f403 7300 and.w r3, r3, #512 ; 0x200 8001660: 617b str r3, [r7, #20] 8001662: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001664: 4b18 ldr r3, [pc, #96] ; (80016c8 ) 8001666: 699b ldr r3, [r3, #24] 8001668: 4a17 ldr r2, [pc, #92] ; (80016c8 ) 800166a: f043 0304 orr.w r3, r3, #4 800166e: 6193 str r3, [r2, #24] 8001670: 4b15 ldr r3, [pc, #84] ; (80016c8 ) 8001672: 699b ldr r3, [r3, #24] 8001674: f003 0304 and.w r3, r3, #4 8001678: 613b str r3, [r7, #16] 800167a: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 800167c: 4b12 ldr r3, [pc, #72] ; (80016c8 ) 800167e: 699b ldr r3, [r3, #24] 8001680: 4a11 ldr r2, [pc, #68] ; (80016c8 ) 8001682: f043 0308 orr.w r3, r3, #8 8001686: 6193 str r3, [r2, #24] 8001688: 4b0f ldr r3, [pc, #60] ; (80016c8 ) 800168a: 699b ldr r3, [r3, #24] 800168c: f003 0308 and.w r3, r3, #8 8001690: 60fb str r3, [r7, #12] 8001692: 68fb ldr r3, [r7, #12] /**ADC1 GPIO Configuration PA6 ------> ADC1_IN6 PB0 ------> ADC1_IN8 PB1 ------> ADC1_IN9 */ GPIO_InitStruct.Pin = ADC_CC1_Pin; 8001694: 2340 movs r3, #64 ; 0x40 8001696: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8001698: 2303 movs r3, #3 800169a: 61fb str r3, [r7, #28] HAL_GPIO_Init(ADC_CC1_GPIO_Port, &GPIO_InitStruct); 800169c: f107 0318 add.w r3, r7, #24 80016a0: 4619 mov r1, r3 80016a2: 480a ldr r0, [pc, #40] ; (80016cc ) 80016a4: f005 fba4 bl 8006df0 GPIO_InitStruct.Pin = ADC_NTC1_Pin|ADC_NTC2_Pin; 80016a8: 2303 movs r3, #3 80016aa: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80016ac: 2303 movs r3, #3 80016ae: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80016b0: f107 0318 add.w r3, r7, #24 80016b4: 4619 mov r1, r3 80016b6: 4806 ldr r0, [pc, #24] ; (80016d0 ) 80016b8: f005 fb9a bl 8006df0 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 80016bc: bf00 nop 80016be: 3728 adds r7, #40 ; 0x28 80016c0: 46bd mov sp, r7 80016c2: bd80 pop {r7, pc} 80016c4: 40012400 .word 0x40012400 80016c8: 40021000 .word 0x40021000 80016cc: 40010800 .word 0x40010800 80016d0: 40010c00 .word 0x40010c00 080016d4 : //TODO: //TEMP READ //GBT_TEMP_SENSORS void RELAY_Write(relay_t num, uint8_t state){ 80016d4: b580 push {r7, lr} 80016d6: b082 sub sp, #8 80016d8: af00 add r7, sp, #0 80016da: 4603 mov r3, r0 80016dc: 460a mov r2, r1 80016de: 71fb strb r3, [r7, #7] 80016e0: 4613 mov r3, r2 80016e2: 71bb strb r3, [r7, #6] if(num==RELAY_AUX)HAL_GPIO_WritePin(RELAY_AUX_GPIO_Port, RELAY_AUX_Pin, state); 80016e4: 79fb ldrb r3, [r7, #7] 80016e6: 2b00 cmp r3, #0 80016e8: d105 bne.n 80016f6 80016ea: 79bb ldrb r3, [r7, #6] 80016ec: 461a mov r2, r3 80016ee: 2110 movs r1, #16 80016f0: 4808 ldr r0, [pc, #32] ; (8001714 ) 80016f2: f005 fd18 bl 8007126 if(num==RELAY_CC)HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, state); 80016f6: 79fb ldrb r3, [r7, #7] 80016f8: 2b01 cmp r3, #1 80016fa: d106 bne.n 800170a 80016fc: 79bb ldrb r3, [r7, #6] 80016fe: 461a mov r2, r3 8001700: f44f 4100 mov.w r1, #32768 ; 0x8000 8001704: 4804 ldr r0, [pc, #16] ; (8001718 ) 8001706: f005 fd0e bl 8007126 } 800170a: bf00 nop 800170c: 3708 adds r7, #8 800170e: 46bd mov sp, r7 8001710: bd80 pop {r7, pc} 8001712: bf00 nop 8001714: 40010c00 .word 0x40010c00 8001718: 40011800 .word 0x40011800 0800171c : // // HAL_ADC_Stop(&hadc1); // stop adc return 0; } void Init_Peripheral(){ 800171c: b580 push {r7, lr} 800171e: af00 add r7, sp, #0 HAL_ADCEx_Calibration_Start(&hadc1); 8001720: 4806 ldr r0, [pc, #24] ; (800173c ) 8001722: f004 f9bd bl 8005aa0 RELAY_Write(RELAY_AUX, 0); 8001726: 2100 movs r1, #0 8001728: 2000 movs r0, #0 800172a: f7ff ffd3 bl 80016d4 RELAY_Write(RELAY_CC, 1); 800172e: 2101 movs r1, #1 8001730: 2001 movs r0, #1 8001732: f7ff ffcf bl 80016d4 } 8001736: bf00 nop 8001738: bd80 pop {r7, pc} 800173a: bf00 nop 800173c: 20000260 .word 0x20000260 08001740 : float pt1000_to_temperature(float resistance) { 8001740: b590 push {r4, r7, lr} 8001742: b087 sub sp, #28 8001744: af00 add r7, sp, #0 8001746: 6078 str r0, [r7, #4] // Константы для PT1000 const float R0 = 1000.0; // Сопротивление при 0 °C 8001748: 4b0c ldr r3, [pc, #48] ; (800177c ) 800174a: 617b str r3, [r7, #20] const float C_A = 3.9083E-3f; 800174c: 4b0c ldr r3, [pc, #48] ; (8001780 ) 800174e: 613b str r3, [r7, #16] // const float B = -5.775e-07; // Второй коэффициент (°C^-2) // // // Расчет температуры по формуле // float temperature = -A / (B - (R0 / resistance - 1) * A); float temperature = (resistance-R0) / ( R0 * C_A); 8001750: 6979 ldr r1, [r7, #20] 8001752: 6878 ldr r0, [r7, #4] 8001754: f7ff fa62 bl 8000c1c <__aeabi_fsub> 8001758: 4603 mov r3, r0 800175a: 461c mov r4, r3 800175c: 6939 ldr r1, [r7, #16] 800175e: 6978 ldr r0, [r7, #20] 8001760: f7ff fb66 bl 8000e30 <__aeabi_fmul> 8001764: 4603 mov r3, r0 8001766: 4619 mov r1, r3 8001768: 4620 mov r0, r4 800176a: f7ff fc15 bl 8000f98 <__aeabi_fdiv> 800176e: 4603 mov r3, r0 8001770: 60fb str r3, [r7, #12] return temperature; 8001772: 68fb ldr r3, [r7, #12] } 8001774: 4618 mov r0, r3 8001776: 371c adds r7, #28 8001778: 46bd mov sp, r7 800177a: bd90 pop {r4, r7, pc} 800177c: 447a0000 .word 0x447a0000 8001780: 3b801132 .word 0x3b801132 8001784: 00000000 .word 0x00000000 08001788 : float calculate_NTC_resistance(int adc_value, float Vref, float Vin, float R) { 8001788: b5b0 push {r4, r5, r7, lr} 800178a: b086 sub sp, #24 800178c: af00 add r7, sp, #0 800178e: 60f8 str r0, [r7, #12] 8001790: 60b9 str r1, [r7, #8] 8001792: 607a str r2, [r7, #4] 8001794: 603b str r3, [r7, #0] // Преобразуем значение АЦП в выходное напряжение float Vout = (adc_value / 4095.0) * Vref; 8001796: 68f8 ldr r0, [r7, #12] 8001798: f7fe feaa bl 80004f0 <__aeabi_i2d> 800179c: a31c add r3, pc, #112 ; (adr r3, 8001810 ) 800179e: e9d3 2300 ldrd r2, r3, [r3] 80017a2: f7ff f839 bl 8000818 <__aeabi_ddiv> 80017a6: 4602 mov r2, r0 80017a8: 460b mov r3, r1 80017aa: 4614 mov r4, r2 80017ac: 461d mov r5, r3 80017ae: 68b8 ldr r0, [r7, #8] 80017b0: f7fe feb0 bl 8000514 <__aeabi_f2d> 80017b4: 4602 mov r2, r0 80017b6: 460b mov r3, r1 80017b8: 4620 mov r0, r4 80017ba: 4629 mov r1, r5 80017bc: f7fe ff02 bl 80005c4 <__aeabi_dmul> 80017c0: 4602 mov r2, r0 80017c2: 460b mov r3, r1 80017c4: 4610 mov r0, r2 80017c6: 4619 mov r1, r3 80017c8: f7ff f9d4 bl 8000b74 <__aeabi_d2f> 80017cc: 4603 mov r3, r0 80017ce: 617b str r3, [r7, #20] // Проверяем, чтобы Vout не было равно Vin if (Vout >= Vin) { 80017d0: 6879 ldr r1, [r7, #4] 80017d2: 6978 ldr r0, [r7, #20] 80017d4: f7ff fcde bl 8001194 <__aeabi_fcmpge> 80017d8: 4603 mov r3, r0 80017da: 2b00 cmp r3, #0 80017dc: d001 beq.n 80017e2 return -1; // Ошибка: Vout не может быть больше или равно Vin 80017de: 4b0e ldr r3, [pc, #56] ; (8001818 ) 80017e0: e010 b.n 8001804 } // Вычисляем сопротивление термистора float R_NTC = R * (Vout / (Vin - Vout)); 80017e2: 6979 ldr r1, [r7, #20] 80017e4: 6878 ldr r0, [r7, #4] 80017e6: f7ff fa19 bl 8000c1c <__aeabi_fsub> 80017ea: 4603 mov r3, r0 80017ec: 4619 mov r1, r3 80017ee: 6978 ldr r0, [r7, #20] 80017f0: f7ff fbd2 bl 8000f98 <__aeabi_fdiv> 80017f4: 4603 mov r3, r0 80017f6: 4619 mov r1, r3 80017f8: 6838 ldr r0, [r7, #0] 80017fa: f7ff fb19 bl 8000e30 <__aeabi_fmul> 80017fe: 4603 mov r3, r0 8001800: 613b str r3, [r7, #16] return R_NTC; 8001802: 693b ldr r3, [r7, #16] } 8001804: 4618 mov r0, r3 8001806: 3718 adds r7, #24 8001808: 46bd mov sp, r7 800180a: bdb0 pop {r4, r5, r7, pc} 800180c: f3af 8000 nop.w 8001810: 00000000 .word 0x00000000 8001814: 40affe00 .word 0x40affe00 8001818: bf800000 .word 0xbf800000 0800181c : int16_t GBT_ReadTemp(uint8_t ch){ 800181c: b580 push {r7, lr} 800181e: b088 sub sp, #32 8001820: af00 add r7, sp, #0 8001822: 4603 mov r3, r0 8001824: 71fb strb r3, [r7, #7] //TODO if(ch)ADC_Select_Channel(ADC_CHANNEL_8); 8001826: 79fb ldrb r3, [r7, #7] 8001828: 2b00 cmp r3, #0 800182a: d003 beq.n 8001834 800182c: 2008 movs r0, #8 800182e: f000 f835 bl 800189c 8001832: e002 b.n 800183a else ADC_Select_Channel(ADC_CHANNEL_9); 8001834: 2009 movs r0, #9 8001836: f000 f831 bl 800189c // Начало конверсии HAL_ADC_Start(&hadc1); 800183a: 4814 ldr r0, [pc, #80] ; (800188c ) 800183c: f003 fdb0 bl 80053a0 // Ожидание окончания конверсии HAL_ADC_PollForConversion(&hadc1, HAL_MAX_DELAY); 8001840: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8001844: 4811 ldr r0, [pc, #68] ; (800188c ) 8001846: f003 fe85 bl 8005554 // Получение значения uint32_t adcValue = HAL_ADC_GetValue(&hadc1); 800184a: 4810 ldr r0, [pc, #64] ; (800188c ) 800184c: f003 ff88 bl 8005760 8001850: 61f8 str r0, [r7, #28] // Остановка АЦП (по желанию) HAL_ADC_Stop(&hadc1); 8001852: 480e ldr r0, [pc, #56] ; (800188c ) 8001854: f003 fe52 bl 80054fc // int adc_value = 2048; // Пример значения АЦП float Vref = 3.3; // Напряжение опорное 8001858: 4b0d ldr r3, [pc, #52] ; (8001890 ) 800185a: 61bb str r3, [r7, #24] float Vin = 5.0; // Входное напряжение 800185c: 4b0d ldr r3, [pc, #52] ; (8001894 ) 800185e: 617b str r3, [r7, #20] float R = 1000; // Сопротивление резистора в Омах 8001860: 4b0d ldr r3, [pc, #52] ; (8001898 ) 8001862: 613b str r3, [r7, #16] float temp = pt1000_to_temperature(calculate_NTC_resistance(adcValue, Vref, Vin, R)); 8001864: 69f8 ldr r0, [r7, #28] 8001866: 693b ldr r3, [r7, #16] 8001868: 697a ldr r2, [r7, #20] 800186a: 69b9 ldr r1, [r7, #24] 800186c: f7ff ff8c bl 8001788 8001870: 4603 mov r3, r0 8001872: 4618 mov r0, r3 8001874: f7ff ff64 bl 8001740 8001878: 60f8 str r0, [r7, #12] return (int16_t)temp; 800187a: 68f8 ldr r0, [r7, #12] 800187c: f7ff fc9e bl 80011bc <__aeabi_f2iz> 8001880: 4603 mov r3, r0 8001882: b21b sxth r3, r3 } 8001884: 4618 mov r0, r3 8001886: 3720 adds r7, #32 8001888: 46bd mov sp, r7 800188a: bd80 pop {r7, pc} 800188c: 20000260 .word 0x20000260 8001890: 40533333 .word 0x40533333 8001894: 40a00000 .word 0x40a00000 8001898: 447a0000 .word 0x447a0000 0800189c : void ADC_Select_Channel(uint32_t ch) { 800189c: b580 push {r7, lr} 800189e: b086 sub sp, #24 80018a0: af00 add r7, sp, #0 80018a2: 6078 str r0, [r7, #4] ADC_ChannelConfTypeDef conf = { 80018a4: 687b ldr r3, [r7, #4] 80018a6: 60fb str r3, [r7, #12] 80018a8: 2301 movs r3, #1 80018aa: 613b str r3, [r7, #16] 80018ac: 2303 movs r3, #3 80018ae: 617b str r3, [r7, #20] .Channel = ch, .Rank = 1, .SamplingTime = ADC_SAMPLETIME_28CYCLES_5, }; if (HAL_ADC_ConfigChannel(&hadc1, &conf) != HAL_OK) { 80018b0: f107 030c add.w r3, r7, #12 80018b4: 4619 mov r1, r3 80018b6: 4806 ldr r0, [pc, #24] ; (80018d0 ) 80018b8: f003 ff5e bl 8005778 80018bc: 4603 mov r3, r0 80018be: 2b00 cmp r3, #0 80018c0: d001 beq.n 80018c6 Error_Handler(); 80018c2: f003 f843 bl 800494c } } 80018c6: bf00 nop 80018c8: 3718 adds r7, #24 80018ca: 46bd mov sp, r7 80018cc: bd80 pop {r7, pc} 80018ce: bf00 nop 80018d0: 20000260 .word 0x20000260 080018d4 : uint8_t SW_GetAddr(){ 80018d4: b580 push {r7, lr} 80018d6: af00 add r7, sp, #0 if(!HAL_GPIO_ReadPin(ADDR_0_GPIO_Port, ADDR_0_Pin)){ 80018d8: f44f 6180 mov.w r1, #1024 ; 0x400 80018dc: 480f ldr r0, [pc, #60] ; (800191c ) 80018de: f005 fc0b bl 80070f8 80018e2: 4603 mov r3, r0 80018e4: 2b00 cmp r3, #0 80018e6: d10b bne.n 8001900 if(!HAL_GPIO_ReadPin(ADDR_1_GPIO_Port, ADDR_1_Pin)){ 80018e8: f44f 6100 mov.w r1, #2048 ; 0x800 80018ec: 480b ldr r0, [pc, #44] ; (800191c ) 80018ee: f005 fc03 bl 80070f8 80018f2: 4603 mov r3, r0 80018f4: 2b00 cmp r3, #0 80018f6: d101 bne.n 80018fc return 0x23; 80018f8: 2323 movs r3, #35 ; 0x23 80018fa: e00c b.n 8001916 }else{ return 0x21; 80018fc: 2321 movs r3, #33 ; 0x21 80018fe: e00a b.n 8001916 } }else{ if(!HAL_GPIO_ReadPin(ADDR_1_GPIO_Port, ADDR_1_Pin)){ 8001900: f44f 6100 mov.w r1, #2048 ; 0x800 8001904: 4805 ldr r0, [pc, #20] ; (800191c ) 8001906: f005 fbf7 bl 80070f8 800190a: 4603 mov r3, r0 800190c: 2b00 cmp r3, #0 800190e: d101 bne.n 8001914 return 0x22; 8001910: 2322 movs r3, #34 ; 0x22 8001912: e000 b.n 8001916 }else{ return 0x20; 8001914: 2320 movs r3, #32 } } } 8001916: 4618 mov r0, r3 8001918: bd80 pop {r7, pc} 800191a: bf00 nop 800191c: 40011800 .word 0x40011800 08001920 : CAN_HandleTypeDef hcan1; CAN_HandleTypeDef hcan2; /* CAN1 init function */ void MX_CAN1_Init(void) { 8001920: b580 push {r7, lr} 8001922: af00 add r7, sp, #0 /* USER CODE END CAN1_Init 0 */ /* USER CODE BEGIN CAN1_Init 1 */ /* USER CODE END CAN1_Init 1 */ hcan1.Instance = CAN1; 8001924: 4b17 ldr r3, [pc, #92] ; (8001984 ) 8001926: 4a18 ldr r2, [pc, #96] ; (8001988 ) 8001928: 601a str r2, [r3, #0] hcan1.Init.Prescaler = 8; 800192a: 4b16 ldr r3, [pc, #88] ; (8001984 ) 800192c: 2208 movs r2, #8 800192e: 605a str r2, [r3, #4] hcan1.Init.Mode = CAN_MODE_NORMAL; 8001930: 4b14 ldr r3, [pc, #80] ; (8001984 ) 8001932: 2200 movs r2, #0 8001934: 609a str r2, [r3, #8] hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; 8001936: 4b13 ldr r3, [pc, #76] ; (8001984 ) 8001938: 2200 movs r2, #0 800193a: 60da str r2, [r3, #12] hcan1.Init.TimeSeg1 = CAN_BS1_15TQ; 800193c: 4b11 ldr r3, [pc, #68] ; (8001984 ) 800193e: f44f 2260 mov.w r2, #917504 ; 0xe0000 8001942: 611a str r2, [r3, #16] hcan1.Init.TimeSeg2 = CAN_BS2_2TQ; 8001944: 4b0f ldr r3, [pc, #60] ; (8001984 ) 8001946: f44f 1280 mov.w r2, #1048576 ; 0x100000 800194a: 615a str r2, [r3, #20] hcan1.Init.TimeTriggeredMode = DISABLE; 800194c: 4b0d ldr r3, [pc, #52] ; (8001984 ) 800194e: 2200 movs r2, #0 8001950: 761a strb r2, [r3, #24] hcan1.Init.AutoBusOff = ENABLE; 8001952: 4b0c ldr r3, [pc, #48] ; (8001984 ) 8001954: 2201 movs r2, #1 8001956: 765a strb r2, [r3, #25] hcan1.Init.AutoWakeUp = ENABLE; 8001958: 4b0a ldr r3, [pc, #40] ; (8001984 ) 800195a: 2201 movs r2, #1 800195c: 769a strb r2, [r3, #26] hcan1.Init.AutoRetransmission = DISABLE; 800195e: 4b09 ldr r3, [pc, #36] ; (8001984 ) 8001960: 2200 movs r2, #0 8001962: 76da strb r2, [r3, #27] hcan1.Init.ReceiveFifoLocked = DISABLE; 8001964: 4b07 ldr r3, [pc, #28] ; (8001984 ) 8001966: 2200 movs r2, #0 8001968: 771a strb r2, [r3, #28] hcan1.Init.TransmitFifoPriority = ENABLE; 800196a: 4b06 ldr r3, [pc, #24] ; (8001984 ) 800196c: 2201 movs r2, #1 800196e: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan1) != HAL_OK) 8001970: 4804 ldr r0, [pc, #16] ; (8001984 ) 8001972: f004 f941 bl 8005bf8 8001976: 4603 mov r3, r0 8001978: 2b00 cmp r3, #0 800197a: d001 beq.n 8001980 { Error_Handler(); 800197c: f002 ffe6 bl 800494c } /* USER CODE BEGIN CAN1_Init 2 */ /* USER CODE END CAN1_Init 2 */ } 8001980: bf00 nop 8001982: bd80 pop {r7, pc} 8001984: 20000290 .word 0x20000290 8001988: 40006400 .word 0x40006400 0800198c : /* CAN2 init function */ void MX_CAN2_Init(void) { 800198c: b580 push {r7, lr} 800198e: af00 add r7, sp, #0 /* USER CODE END CAN2_Init 0 */ /* USER CODE BEGIN CAN2_Init 1 */ /* USER CODE END CAN2_Init 1 */ hcan2.Instance = CAN2; 8001990: 4b17 ldr r3, [pc, #92] ; (80019f0 ) 8001992: 4a18 ldr r2, [pc, #96] ; (80019f4 ) 8001994: 601a str r2, [r3, #0] hcan2.Init.Prescaler = 16; 8001996: 4b16 ldr r3, [pc, #88] ; (80019f0 ) 8001998: 2210 movs r2, #16 800199a: 605a str r2, [r3, #4] hcan2.Init.Mode = CAN_MODE_NORMAL; 800199c: 4b14 ldr r3, [pc, #80] ; (80019f0 ) 800199e: 2200 movs r2, #0 80019a0: 609a str r2, [r3, #8] hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; 80019a2: 4b13 ldr r3, [pc, #76] ; (80019f0 ) 80019a4: 2200 movs r2, #0 80019a6: 60da str r2, [r3, #12] hcan2.Init.TimeSeg1 = CAN_BS1_15TQ; 80019a8: 4b11 ldr r3, [pc, #68] ; (80019f0 ) 80019aa: f44f 2260 mov.w r2, #917504 ; 0xe0000 80019ae: 611a str r2, [r3, #16] hcan2.Init.TimeSeg2 = CAN_BS2_2TQ; 80019b0: 4b0f ldr r3, [pc, #60] ; (80019f0 ) 80019b2: f44f 1280 mov.w r2, #1048576 ; 0x100000 80019b6: 615a str r2, [r3, #20] hcan2.Init.TimeTriggeredMode = DISABLE; 80019b8: 4b0d ldr r3, [pc, #52] ; (80019f0 ) 80019ba: 2200 movs r2, #0 80019bc: 761a strb r2, [r3, #24] hcan2.Init.AutoBusOff = ENABLE; 80019be: 4b0c ldr r3, [pc, #48] ; (80019f0 ) 80019c0: 2201 movs r2, #1 80019c2: 765a strb r2, [r3, #25] hcan2.Init.AutoWakeUp = ENABLE; 80019c4: 4b0a ldr r3, [pc, #40] ; (80019f0 ) 80019c6: 2201 movs r2, #1 80019c8: 769a strb r2, [r3, #26] hcan2.Init.AutoRetransmission = ENABLE; 80019ca: 4b09 ldr r3, [pc, #36] ; (80019f0 ) 80019cc: 2201 movs r2, #1 80019ce: 76da strb r2, [r3, #27] hcan2.Init.ReceiveFifoLocked = DISABLE; 80019d0: 4b07 ldr r3, [pc, #28] ; (80019f0 ) 80019d2: 2200 movs r2, #0 80019d4: 771a strb r2, [r3, #28] hcan2.Init.TransmitFifoPriority = ENABLE; 80019d6: 4b06 ldr r3, [pc, #24] ; (80019f0 ) 80019d8: 2201 movs r2, #1 80019da: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan2) != HAL_OK) 80019dc: 4804 ldr r0, [pc, #16] ; (80019f0 ) 80019de: f004 f90b bl 8005bf8 80019e2: 4603 mov r3, r0 80019e4: 2b00 cmp r3, #0 80019e6: d001 beq.n 80019ec { Error_Handler(); 80019e8: f002 ffb0 bl 800494c } /* USER CODE BEGIN CAN2_Init 2 */ /* USER CODE END CAN2_Init 2 */ } 80019ec: bf00 nop 80019ee: bd80 pop {r7, pc} 80019f0: 200002b8 .word 0x200002b8 80019f4: 40006800 .word 0x40006800 080019f8 : static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0; void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) { 80019f8: b580 push {r7, lr} 80019fa: b08e sub sp, #56 ; 0x38 80019fc: af00 add r7, sp, #0 80019fe: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001a00: f107 0320 add.w r3, r7, #32 8001a04: 2200 movs r2, #0 8001a06: 601a str r2, [r3, #0] 8001a08: 605a str r2, [r3, #4] 8001a0a: 609a str r2, [r3, #8] 8001a0c: 60da str r2, [r3, #12] if(canHandle->Instance==CAN1) 8001a0e: 687b ldr r3, [r7, #4] 8001a10: 681b ldr r3, [r3, #0] 8001a12: 4a61 ldr r2, [pc, #388] ; (8001b98 ) 8001a14: 4293 cmp r3, r2 8001a16: d153 bne.n 8001ac0 { /* USER CODE BEGIN CAN1_MspInit 0 */ /* USER CODE END CAN1_MspInit 0 */ /* CAN1 clock enable */ HAL_RCC_CAN1_CLK_ENABLED++; 8001a18: 4b60 ldr r3, [pc, #384] ; (8001b9c ) 8001a1a: 681b ldr r3, [r3, #0] 8001a1c: 3301 adds r3, #1 8001a1e: 4a5f ldr r2, [pc, #380] ; (8001b9c ) 8001a20: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8001a22: 4b5e ldr r3, [pc, #376] ; (8001b9c ) 8001a24: 681b ldr r3, [r3, #0] 8001a26: 2b01 cmp r3, #1 8001a28: d10b bne.n 8001a42 __HAL_RCC_CAN1_CLK_ENABLE(); 8001a2a: 4b5d ldr r3, [pc, #372] ; (8001ba0 ) 8001a2c: 69db ldr r3, [r3, #28] 8001a2e: 4a5c ldr r2, [pc, #368] ; (8001ba0 ) 8001a30: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 8001a34: 61d3 str r3, [r2, #28] 8001a36: 4b5a ldr r3, [pc, #360] ; (8001ba0 ) 8001a38: 69db ldr r3, [r3, #28] 8001a3a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8001a3e: 61fb str r3, [r7, #28] 8001a40: 69fb ldr r3, [r7, #28] } __HAL_RCC_GPIOD_CLK_ENABLE(); 8001a42: 4b57 ldr r3, [pc, #348] ; (8001ba0 ) 8001a44: 699b ldr r3, [r3, #24] 8001a46: 4a56 ldr r2, [pc, #344] ; (8001ba0 ) 8001a48: f043 0320 orr.w r3, r3, #32 8001a4c: 6193 str r3, [r2, #24] 8001a4e: 4b54 ldr r3, [pc, #336] ; (8001ba0 ) 8001a50: 699b ldr r3, [r3, #24] 8001a52: f003 0320 and.w r3, r3, #32 8001a56: 61bb str r3, [r7, #24] 8001a58: 69bb ldr r3, [r7, #24] /**CAN1 GPIO Configuration PD0 ------> CAN1_RX PD1 ------> CAN1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0; 8001a5a: 2301 movs r3, #1 8001a5c: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001a5e: 2300 movs r3, #0 8001a60: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001a62: 2300 movs r3, #0 8001a64: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001a66: f107 0320 add.w r3, r7, #32 8001a6a: 4619 mov r1, r3 8001a6c: 484d ldr r0, [pc, #308] ; (8001ba4 ) 8001a6e: f005 f9bf bl 8006df0 GPIO_InitStruct.Pin = GPIO_PIN_1; 8001a72: 2302 movs r3, #2 8001a74: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001a76: 2302 movs r3, #2 8001a78: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001a7a: 2303 movs r3, #3 8001a7c: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001a7e: f107 0320 add.w r3, r7, #32 8001a82: 4619 mov r1, r3 8001a84: 4847 ldr r0, [pc, #284] ; (8001ba4 ) 8001a86: f005 f9b3 bl 8006df0 __HAL_AFIO_REMAP_CAN1_3(); 8001a8a: 4b47 ldr r3, [pc, #284] ; (8001ba8 ) 8001a8c: 685b ldr r3, [r3, #4] 8001a8e: 633b str r3, [r7, #48] ; 0x30 8001a90: 6b3b ldr r3, [r7, #48] ; 0x30 8001a92: f423 43c0 bic.w r3, r3, #24576 ; 0x6000 8001a96: 633b str r3, [r7, #48] ; 0x30 8001a98: 6b3b ldr r3, [r7, #48] ; 0x30 8001a9a: f043 63e0 orr.w r3, r3, #117440512 ; 0x7000000 8001a9e: 633b str r3, [r7, #48] ; 0x30 8001aa0: 6b3b ldr r3, [r7, #48] ; 0x30 8001aa2: f443 43c0 orr.w r3, r3, #24576 ; 0x6000 8001aa6: 633b str r3, [r7, #48] ; 0x30 8001aa8: 4a3f ldr r2, [pc, #252] ; (8001ba8 ) 8001aaa: 6b3b ldr r3, [r7, #48] ; 0x30 8001aac: 6053 str r3, [r2, #4] /* CAN1 interrupt Init */ HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0); 8001aae: 2200 movs r2, #0 8001ab0: 2100 movs r1, #0 8001ab2: 2014 movs r0, #20 8001ab4: f005 f823 bl 8006afe HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn); 8001ab8: 2014 movs r0, #20 8001aba: f005 f83c bl 8006b36 HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); /* USER CODE BEGIN CAN2_MspInit 1 */ /* USER CODE END CAN2_MspInit 1 */ } } 8001abe: e067 b.n 8001b90 else if(canHandle->Instance==CAN2) 8001ac0: 687b ldr r3, [r7, #4] 8001ac2: 681b ldr r3, [r3, #0] 8001ac4: 4a39 ldr r2, [pc, #228] ; (8001bac ) 8001ac6: 4293 cmp r3, r2 8001ac8: d162 bne.n 8001b90 __HAL_RCC_CAN2_CLK_ENABLE(); 8001aca: 4b35 ldr r3, [pc, #212] ; (8001ba0 ) 8001acc: 69db ldr r3, [r3, #28] 8001ace: 4a34 ldr r2, [pc, #208] ; (8001ba0 ) 8001ad0: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 8001ad4: 61d3 str r3, [r2, #28] 8001ad6: 4b32 ldr r3, [pc, #200] ; (8001ba0 ) 8001ad8: 69db ldr r3, [r3, #28] 8001ada: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 8001ade: 617b str r3, [r7, #20] 8001ae0: 697b ldr r3, [r7, #20] HAL_RCC_CAN1_CLK_ENABLED++; 8001ae2: 4b2e ldr r3, [pc, #184] ; (8001b9c ) 8001ae4: 681b ldr r3, [r3, #0] 8001ae6: 3301 adds r3, #1 8001ae8: 4a2c ldr r2, [pc, #176] ; (8001b9c ) 8001aea: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8001aec: 4b2b ldr r3, [pc, #172] ; (8001b9c ) 8001aee: 681b ldr r3, [r3, #0] 8001af0: 2b01 cmp r3, #1 8001af2: d10b bne.n 8001b0c __HAL_RCC_CAN1_CLK_ENABLE(); 8001af4: 4b2a ldr r3, [pc, #168] ; (8001ba0 ) 8001af6: 69db ldr r3, [r3, #28] 8001af8: 4a29 ldr r2, [pc, #164] ; (8001ba0 ) 8001afa: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 8001afe: 61d3 str r3, [r2, #28] 8001b00: 4b27 ldr r3, [pc, #156] ; (8001ba0 ) 8001b02: 69db ldr r3, [r3, #28] 8001b04: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8001b08: 613b str r3, [r7, #16] 8001b0a: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001b0c: 4b24 ldr r3, [pc, #144] ; (8001ba0 ) 8001b0e: 699b ldr r3, [r3, #24] 8001b10: 4a23 ldr r2, [pc, #140] ; (8001ba0 ) 8001b12: f043 0308 orr.w r3, r3, #8 8001b16: 6193 str r3, [r2, #24] 8001b18: 4b21 ldr r3, [pc, #132] ; (8001ba0 ) 8001b1a: 699b ldr r3, [r3, #24] 8001b1c: f003 0308 and.w r3, r3, #8 8001b20: 60fb str r3, [r7, #12] 8001b22: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_5; 8001b24: 2320 movs r3, #32 8001b26: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001b28: 2300 movs r3, #0 8001b2a: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001b2c: 2300 movs r3, #0 8001b2e: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001b30: f107 0320 add.w r3, r7, #32 8001b34: 4619 mov r1, r3 8001b36: 481e ldr r0, [pc, #120] ; (8001bb0 ) 8001b38: f005 f95a bl 8006df0 GPIO_InitStruct.Pin = GPIO_PIN_6; 8001b3c: 2340 movs r3, #64 ; 0x40 8001b3e: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001b40: 2302 movs r3, #2 8001b42: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001b44: 2303 movs r3, #3 8001b46: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001b48: f107 0320 add.w r3, r7, #32 8001b4c: 4619 mov r1, r3 8001b4e: 4818 ldr r0, [pc, #96] ; (8001bb0 ) 8001b50: f005 f94e bl 8006df0 __HAL_AFIO_REMAP_CAN2_ENABLE(); 8001b54: 4b14 ldr r3, [pc, #80] ; (8001ba8 ) 8001b56: 685b ldr r3, [r3, #4] 8001b58: 637b str r3, [r7, #52] ; 0x34 8001b5a: 6b7b ldr r3, [r7, #52] ; 0x34 8001b5c: f043 63e0 orr.w r3, r3, #117440512 ; 0x7000000 8001b60: 637b str r3, [r7, #52] ; 0x34 8001b62: 6b7b ldr r3, [r7, #52] ; 0x34 8001b64: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 8001b68: 637b str r3, [r7, #52] ; 0x34 8001b6a: 4a0f ldr r2, [pc, #60] ; (8001ba8 ) 8001b6c: 6b7b ldr r3, [r7, #52] ; 0x34 8001b6e: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(CAN2_TX_IRQn, 0, 0); 8001b70: 2200 movs r2, #0 8001b72: 2100 movs r1, #0 8001b74: 203f movs r0, #63 ; 0x3f 8001b76: f004 ffc2 bl 8006afe HAL_NVIC_EnableIRQ(CAN2_TX_IRQn); 8001b7a: 203f movs r0, #63 ; 0x3f 8001b7c: f004 ffdb bl 8006b36 HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 0, 0); 8001b80: 2200 movs r2, #0 8001b82: 2100 movs r1, #0 8001b84: 2041 movs r0, #65 ; 0x41 8001b86: f004 ffba bl 8006afe HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); 8001b8a: 2041 movs r0, #65 ; 0x41 8001b8c: f004 ffd3 bl 8006b36 } 8001b90: bf00 nop 8001b92: 3738 adds r7, #56 ; 0x38 8001b94: 46bd mov sp, r7 8001b96: bd80 pop {r7, pc} 8001b98: 40006400 .word 0x40006400 8001b9c: 200002e0 .word 0x200002e0 8001ba0: 40021000 .word 0x40021000 8001ba4: 40011400 .word 0x40011400 8001ba8: 40010000 .word 0x40010000 8001bac: 40006800 .word 0x40006800 8001bb0: 40010c00 .word 0x40010c00 08001bb4 : extern GBT_EDCAN_Output_t GBT_EDCAN_Output; extern GBT_EDCAN_Input_t GBT_EDCAN_Input; void GBT_Init(){ 8001bb4: b580 push {r7, lr} 8001bb6: af00 add r7, sp, #0 GBT_State = GBT_DISABLED; 8001bb8: 4b03 ldr r3, [pc, #12] ; (8001bc8 ) 8001bba: 2210 movs r2, #16 8001bbc: 701a strb r2, [r3, #0] GBT_EDCAN_Input.chargeControl == CHARGING_NOT_ALLOWED; GBT_Reset(); 8001bbe: f000 fbff bl 80023c0 } 8001bc2: bf00 nop 8001bc4: bd80 pop {r7, pc} 8001bc6: bf00 nop 8001bc8: 200002e4 .word 0x200002e4 08001bcc : void GBT_ChargerTask(){ 8001bcc: b5b0 push {r4, r5, r7, lr} 8001bce: b082 sub sp, #8 8001bd0: af00 add r7, sp, #0 //GBT_LockTask(); if(j_rx.state == 2){ 8001bd2: 4baf ldr r3, [pc, #700] ; (8001e90 ) 8001bd4: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 8001bd8: 2b02 cmp r3, #2 8001bda: f040 80c1 bne.w 8001d60 switch (j_rx.PGN){ 8001bde: 4bac ldr r3, [pc, #688] ; (8001e90 ) 8001be0: f8d3 3100 ldr.w r3, [r3, #256] ; 0x100 8001be4: f5b3 5f1c cmp.w r3, #9984 ; 0x2700 8001be8: d044 beq.n 8001c74 8001bea: f5b3 5f1c cmp.w r3, #9984 ; 0x2700 8001bee: f200 80b3 bhi.w 8001d58 8001bf2: f5b3 5fe0 cmp.w r3, #7168 ; 0x1c00 8001bf6: f000 80a6 beq.w 8001d46 8001bfa: f5b3 5fe0 cmp.w r3, #7168 ; 0x1c00 8001bfe: f200 80ab bhi.w 8001d58 8001c02: f5b3 5fb8 cmp.w r3, #5888 ; 0x1700 8001c06: f000 80a2 beq.w 8001d4e 8001c0a: f5b3 5fb8 cmp.w r3, #5888 ; 0x1700 8001c0e: f200 80a3 bhi.w 8001d58 8001c12: f5b3 5fb0 cmp.w r3, #5632 ; 0x1600 8001c16: f000 809c beq.w 8001d52 8001c1a: f5b3 5fb0 cmp.w r3, #5632 ; 0x1600 8001c1e: f200 809b bhi.w 8001d58 8001c22: f5b3 5fa8 cmp.w r3, #5376 ; 0x1500 8001c26: f000 8096 beq.w 8001d56 8001c2a: f5b3 5fa8 cmp.w r3, #5376 ; 0x1500 8001c2e: f200 8093 bhi.w 8001d58 8001c32: f5b3 5f98 cmp.w r3, #4864 ; 0x1300 8001c36: d07b beq.n 8001d30 8001c38: f5b3 5f98 cmp.w r3, #4864 ; 0x1300 8001c3c: f200 808c bhi.w 8001d58 8001c40: f5b3 5f88 cmp.w r3, #4352 ; 0x1100 8001c44: d063 beq.n 8001d0e 8001c46: f5b3 5f88 cmp.w r3, #4352 ; 0x1100 8001c4a: f200 8085 bhi.w 8001d58 8001c4e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8001c52: d044 beq.n 8001cde 8001c54: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8001c58: d87e bhi.n 8001d58 8001c5a: f5b3 6f10 cmp.w r3, #2304 ; 0x900 8001c5e: d02b beq.n 8001cb8 8001c60: f5b3 6f10 cmp.w r3, #2304 ; 0x900 8001c64: d878 bhi.n 8001d58 8001c66: f5b3 7f00 cmp.w r3, #512 ; 0x200 8001c6a: d00b beq.n 8001c84 8001c6c: f5b3 6fc0 cmp.w r3, #1536 ; 0x600 8001c70: d018 beq.n 8001ca4 8001c72: e071 b.n 8001d58 case 0x2700: //PGN BHM GBT_BHM_recv = 1; 8001c74: 4b87 ldr r3, [pc, #540] ; (8001e94 ) 8001c76: 2201 movs r2, #1 8001c78: 701a strb r2, [r3, #0] 8001c7a: 4b85 ldr r3, [pc, #532] ; (8001e90 ) 8001c7c: 881a ldrh r2, [r3, #0] memcpy (&GBT_MaxVoltage, j_rx.data, sizeof(GBT_MaxVoltage)); 8001c7e: 4b86 ldr r3, [pc, #536] ; (8001e98 ) 8001c80: 801a strh r2, [r3, #0] break; 8001c82: e069 b.n 8001d58 case 0x0200: //PGN BRM LONG GBT_BAT_INFO_recv = 1; 8001c84: 4b85 ldr r3, [pc, #532] ; (8001e9c ) 8001c86: 2201 movs r2, #1 8001c88: 701a strb r2, [r3, #0] memcpy (&GBT_EVInfo, j_rx.data, sizeof(GBT_EVInfo)); 8001c8a: 4a85 ldr r2, [pc, #532] ; (8001ea0 ) 8001c8c: 4b80 ldr r3, [pc, #512] ; (8001e90 ) 8001c8e: 4614 mov r4, r2 8001c90: 461d mov r5, r3 8001c92: cd0f ldmia r5!, {r0, r1, r2, r3} 8001c94: c40f stmia r4!, {r0, r1, r2, r3} 8001c96: cd0f ldmia r5!, {r0, r1, r2, r3} 8001c98: c40f stmia r4!, {r0, r1, r2, r3} 8001c9a: cd0f ldmia r5!, {r0, r1, r2, r3} 8001c9c: c40f stmia r4!, {r0, r1, r2, r3} 8001c9e: 682b ldr r3, [r5, #0] 8001ca0: 7023 strb r3, [r4, #0] break; 8001ca2: e059 b.n 8001d58 case 0x0600: //PGN BCP LONG GBT_BAT_STAT_recv = 1; 8001ca4: 4b7f ldr r3, [pc, #508] ; (8001ea4 ) 8001ca6: 2201 movs r2, #1 8001ca8: 701a strb r2, [r3, #0] memcpy (&GBT_BATStat, j_rx.data, sizeof(GBT_BATStat)); 8001caa: 4a7f ldr r2, [pc, #508] ; (8001ea8 ) 8001cac: 4b78 ldr r3, [pc, #480] ; (8001e90 ) 8001cae: 4614 mov r4, r2 8001cb0: cb0f ldmia r3, {r0, r1, r2, r3} 8001cb2: c407 stmia r4!, {r0, r1, r2} 8001cb4: 7023 strb r3, [r4, #0] break; 8001cb6: e04f b.n 8001d58 case 0x0900: //PGN BRO GBT_BRO_recv = 1; 8001cb8: 4b7c ldr r3, [pc, #496] ; (8001eac ) 8001cba: 2201 movs r2, #1 8001cbc: 701a strb r2, [r3, #0] if(j_rx.data[0] == 0xAA) EV_ready = 1; 8001cbe: 4b74 ldr r3, [pc, #464] ; (8001e90 ) 8001cc0: 781b ldrb r3, [r3, #0] 8001cc2: 2baa cmp r3, #170 ; 0xaa 8001cc4: d103 bne.n 8001cce 8001cc6: 4b7a ldr r3, [pc, #488] ; (8001eb0 ) 8001cc8: 2201 movs r2, #1 8001cca: 701a strb r2, [r3, #0] 8001ccc: e002 b.n 8001cd4 else EV_ready = 0; 8001cce: 4b78 ldr r3, [pc, #480] ; (8001eb0 ) 8001cd0: 2200 movs r2, #0 8001cd2: 701a strb r2, [r3, #0] GBT_BRO = j_rx.data[0]; 8001cd4: 4b6e ldr r3, [pc, #440] ; (8001e90 ) 8001cd6: 781a ldrb r2, [r3, #0] 8001cd8: 4b76 ldr r3, [pc, #472] ; (8001eb4 ) 8001cda: 701a strb r2, [r3, #0] break; 8001cdc: e03c b.n 8001d58 case 0x1000: //PGN BCL //TODO: power block memcpy (&GBT_ReqPower, j_rx.data, sizeof(GBT_ReqPower)); 8001cde: 4b76 ldr r3, [pc, #472] ; (8001eb8 ) 8001ce0: 4a6b ldr r2, [pc, #428] ; (8001e90 ) 8001ce2: e892 0003 ldmia.w r2, {r0, r1} 8001ce6: 6018 str r0, [r3, #0] 8001ce8: 3304 adds r3, #4 8001cea: 7019 strb r1, [r3, #0] uint16_t volt=GBT_ReqPower.requestedVoltage; 8001cec: 4b72 ldr r3, [pc, #456] ; (8001eb8 ) 8001cee: 881b ldrh r3, [r3, #0] 8001cf0: 80fb strh r3, [r7, #6] GBT_EDCAN_Output.requestedVoltage = volt; 8001cf2: 4b72 ldr r3, [pc, #456] ; (8001ebc ) 8001cf4: 88fa ldrh r2, [r7, #6] 8001cf6: f8a3 2001 strh.w r2, [r3, #1] uint16_t curr=4000-GBT_ReqPower.requestedCurrent; 8001cfa: 4b6f ldr r3, [pc, #444] ; (8001eb8 ) 8001cfc: 885b ldrh r3, [r3, #2] 8001cfe: f5c3 637a rsb r3, r3, #4000 ; 0xfa0 8001d02: 80bb strh r3, [r7, #4] GBT_EDCAN_Output.requestedCurrent = curr; 8001d04: 4b6d ldr r3, [pc, #436] ; (8001ebc ) 8001d06: 88ba ldrh r2, [r7, #4] 8001d08: f8a3 2003 strh.w r2, [r3, #3] break; 8001d0c: e024 b.n 8001d58 case 0x1100: //PGN BCS //TODO memcpy (&GBT_ChargingStatus, j_rx.data, sizeof(GBT_ChargingStatus)); 8001d0e: 4b6c ldr r3, [pc, #432] ; (8001ec0 ) 8001d10: 4a5f ldr r2, [pc, #380] ; (8001e90 ) 8001d12: ca07 ldmia r2, {r0, r1, r2} 8001d14: c303 stmia r3!, {r0, r1} 8001d16: 701a strb r2, [r3, #0] GBT_EDCAN_Output.chargingRemainingTimeMin = GBT_ChargingStatus.estimatedRemainingChargingTime; 8001d18: 4b69 ldr r3, [pc, #420] ; (8001ec0 ) 8001d1a: f8b3 3007 ldrh.w r3, [r3, #7] 8001d1e: b29a uxth r2, r3 8001d20: 4b66 ldr r3, [pc, #408] ; (8001ebc ) 8001d22: f8a3 2007 strh.w r2, [r3, #7] GBT_EDCAN_Output.chargingPercentage = GBT_ChargingStatus.currentChargeState; 8001d26: 4b66 ldr r3, [pc, #408] ; (8001ec0 ) 8001d28: 799a ldrb r2, [r3, #6] 8001d2a: 4b64 ldr r3, [pc, #400] ; (8001ebc ) 8001d2c: 719a strb r2, [r3, #6] break; 8001d2e: e013 b.n 8001d58 case 0x1300: //PGN BSM //TODO memcpy (&GBT_BatteryStatus, j_rx.data, sizeof(GBT_BatteryStatus)); 8001d30: 4b64 ldr r3, [pc, #400] ; (8001ec4 ) 8001d32: 4a57 ldr r2, [pc, #348] ; (8001e90 ) 8001d34: e892 0003 ldmia.w r2, {r0, r1} 8001d38: 6018 str r0, [r3, #0] 8001d3a: 3304 adds r3, #4 8001d3c: 8019 strh r1, [r3, #0] 8001d3e: 3302 adds r3, #2 8001d40: 0c0a lsrs r2, r1, #16 8001d42: 701a strb r2, [r3, #0] break; 8001d44: e008 b.n 8001d58 // case 0x1900: //PGN BST // break; case 0x1C00: //PGN BSD //TODO SOC Voltage Temp GBT_BSD_recv = 1; 8001d46: 4b60 ldr r3, [pc, #384] ; (8001ec8 ) 8001d48: 2201 movs r2, #1 8001d4a: 701a strb r2, [r3, #0] break; 8001d4c: e004 b.n 8001d58 break; 8001d4e: bf00 nop 8001d50: e002 b.n 8001d58 break; 8001d52: bf00 nop 8001d54: e000 b.n 8001d58 break; 8001d56: bf00 nop // break; //BSM BMV BMT BSP BST BSD BEM } j_rx.state = 0; 8001d58: 4b4d ldr r3, [pc, #308] ; (8001e90 ) 8001d5a: 2200 movs r2, #0 8001d5c: f883 210a strb.w r2, [r3, #266] ; 0x10a } if(GBT_delay>HAL_GetTick()){ 8001d60: f003 fa18 bl 8005194 8001d64: 4602 mov r2, r0 8001d66: 4b59 ldr r3, [pc, #356] ; (8001ecc ) 8001d68: 681b ldr r3, [r3, #0] 8001d6a: 429a cmp r2, r3 8001d6c: f0c0 8216 bcc.w 800219c //waiting }else switch (GBT_State){ 8001d70: 4b57 ldr r3, [pc, #348] ; (8001ed0 ) 8001d72: 781b ldrb r3, [r3, #0] 8001d74: 3b10 subs r3, #16 8001d76: 2b14 cmp r3, #20 8001d78: f200 81f9 bhi.w 800216e 8001d7c: a201 add r2, pc, #4 ; (adr r2, 8001d84 ) 8001d7e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8001d82: bf00 nop 8001d84: 08001dd9 .word 0x08001dd9 8001d88: 0800216f .word 0x0800216f 8001d8c: 0800216f .word 0x0800216f 8001d90: 08001df5 .word 0x08001df5 8001d94: 08001e05 .word 0x08001e05 8001d98: 08001e49 .word 0x08001e49 8001d9c: 08001ee1 .word 0x08001ee1 8001da0: 08001f27 .word 0x08001f27 8001da4: 08001f9d .word 0x08001f9d 8001da8: 08001fcb .word 0x08001fcb 8001dac: 0800216f .word 0x0800216f 8001db0: 0800216f .word 0x0800216f 8001db4: 0800216f .word 0x0800216f 8001db8: 0800216f .word 0x0800216f 8001dbc: 0800216f .word 0x0800216f 8001dc0: 0800216f .word 0x0800216f 8001dc4: 0800202b .word 0x0800202b 8001dc8: 080020f3 .word 0x080020f3 8001dcc: 0800212d .word 0x0800212d 8001dd0: 0800214d .word 0x0800214d 8001dd4: 0800215f .word 0x0800215f case GBT_DISABLED: RELAY_Write(RELAY_AUX, 0); 8001dd8: 2100 movs r1, #0 8001dda: 2000 movs r0, #0 8001ddc: f7ff fc7a bl 80016d4 if(connectorState == CONN_Occupied_charging){ 8001de0: 4b3c ldr r3, [pc, #240] ; (8001ed4 ) 8001de2: 781b ldrb r3, [r3, #0] 8001de4: 2b05 cmp r3, #5 8001de6: f040 81c6 bne.w 8002176 GBT_Reset(); 8001dea: f000 fae9 bl 80023c0 GBT_Start();//TODO IF protections (maybe not needed) 8001dee: f000 fb59 bl 80024a4 } break; 8001df2: e1c0 b.n 8002176 // GBT_Delay(500); // } // break; case GBT_S3_STARTED: GBT_SwitchState(GBT_S4_ISOTEST); 8001df4: 2014 movs r0, #20 8001df6: f000 f9fb bl 80021f0 GBT_Delay(500); 8001dfa: f44f 70fa mov.w r0, #500 ; 0x1f4 8001dfe: f000 fa93 bl 8002328 break; 8001e02: e1cb b.n 800219c case GBT_S4_ISOTEST: if(j_rx.state == 0) GBT_SendCHM(); 8001e04: 4b22 ldr r3, [pc, #136] ; (8001e90 ) 8001e06: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 8001e0a: 2b00 cmp r3, #0 8001e0c: d101 bne.n 8001e12 8001e0e: f001 fb41 bl 8003494 GBT_Delay(250); 8001e12: 20fa movs r0, #250 ; 0xfa 8001e14: f000 fa88 bl 8002328 //TODO: Isolation test //if(isolation test fail) {send CST} if(GBT_BHM_recv) { 8001e18: 4b1e ldr r3, [pc, #120] ; (8001e94 ) 8001e1a: 781b ldrb r3, [r3, #0] 8001e1c: 2b00 cmp r3, #0 8001e1e: d002 beq.n 8001e26 //Isolation test finish GBT_SwitchState(GBT_S5_BAT_INFO); 8001e20: 2015 movs r0, #21 8001e22: f000 f9e5 bl 80021f0 } //Timeout 10S if((GBT_BHM_recv == 0) && (GBT_StateTick()>10000)) { //BHM Timeout 8001e26: 4b1b ldr r3, [pc, #108] ; (8001e94 ) 8001e28: 781b ldrb r3, [r3, #0] 8001e2a: 2b00 cmp r3, #0 8001e2c: f040 81a5 bne.w 800217a 8001e30: f000 fa6e bl 8002310 8001e34: 4603 mov r3, r0 8001e36: f242 7210 movw r2, #10000 ; 0x2710 8001e3a: 4293 cmp r3, r2 8001e3c: f240 819d bls.w 800217a GBT_Error(0xFCF0C0FC); 8001e40: 4825 ldr r0, [pc, #148] ; (8001ed8 ) 8001e42: f000 fa99 bl 8002378 } break; 8001e46: e198 b.n 800217a case GBT_S5_BAT_INFO: if(j_rx.state == 0) GBT_SendCRM(0x00); 8001e48: 4b11 ldr r3, [pc, #68] ; (8001e90 ) 8001e4a: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 8001e4e: 2b00 cmp r3, #0 8001e50: d102 bne.n 8001e58 8001e52: 2000 movs r0, #0 8001e54: f001 fb32 bl 80034bc GBT_Delay(250); 8001e58: 20fa movs r0, #250 ; 0xfa 8001e5a: f000 fa65 bl 8002328 if(GBT_BAT_INFO_recv){ //BRM 8001e5e: 4b0f ldr r3, [pc, #60] ; (8001e9c ) 8001e60: 781b ldrb r3, [r3, #0] 8001e62: 2b00 cmp r3, #0 8001e64: d002 beq.n 8001e6c //Got battery info GBT_SwitchState(GBT_S6_BAT_STAT); 8001e66: 2016 movs r0, #22 8001e68: f000 f9c2 bl 80021f0 } //Timeout if((GBT_StateTick()>5000) && (GBT_BAT_INFO_recv == 0)){ 8001e6c: f000 fa50 bl 8002310 8001e70: 4603 mov r3, r0 8001e72: f241 3288 movw r2, #5000 ; 0x1388 8001e76: 4293 cmp r3, r2 8001e78: f240 8181 bls.w 800217e 8001e7c: 4b07 ldr r3, [pc, #28] ; (8001e9c ) 8001e7e: 781b ldrb r3, [r3, #0] 8001e80: 2b00 cmp r3, #0 8001e82: f040 817c bne.w 800217e GBT_Error(0xFDF0C0FC); //BRM Timeout 8001e86: 4815 ldr r0, [pc, #84] ; (8001edc ) 8001e88: f000 fa76 bl 8002378 } break; 8001e8c: e177 b.n 800217e 8001e8e: bf00 nop 8001e90: 200004c0 .word 0x200004c0 8001e94: 200002f3 .word 0x200002f3 8001e98: 20000308 .word 0x20000308 8001e9c: 200002f0 .word 0x200002f0 8001ea0: 2000030c .word 0x2000030c 8001ea4: 200002f1 .word 0x200002f1 8001ea8: 20000340 .word 0x20000340 8001eac: 200002f2 .word 0x200002f2 8001eb0: 200002f5 .word 0x200002f5 8001eb4: 20000384 .word 0x20000384 8001eb8: 20000350 .word 0x20000350 8001ebc: 200004a8 .word 0x200004a8 8001ec0: 20000360 .word 0x20000360 8001ec4: 2000036c .word 0x2000036c 8001ec8: 200002f4 .word 0x200002f4 8001ecc: 200002ec .word 0x200002ec 8001ed0: 200002e4 .word 0x200002e4 8001ed4: 20000394 .word 0x20000394 8001ed8: fcf0c0fc .word 0xfcf0c0fc 8001edc: fdf0c0fc .word 0xfdf0c0fc case GBT_S6_BAT_STAT: if(j_rx.state == 0) GBT_SendCRM(0xAA); 8001ee0: 4bb0 ldr r3, [pc, #704] ; (80021a4 ) 8001ee2: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 8001ee6: 2b00 cmp r3, #0 8001ee8: d102 bne.n 8001ef0 8001eea: 20aa movs r0, #170 ; 0xaa 8001eec: f001 fae6 bl 80034bc GBT_Delay(250); 8001ef0: 20fa movs r0, #250 ; 0xfa 8001ef2: f000 fa19 bl 8002328 if(GBT_BAT_STAT_recv){ 8001ef6: 4bac ldr r3, [pc, #688] ; (80021a8 ) 8001ef8: 781b ldrb r3, [r3, #0] 8001efa: 2b00 cmp r3, #0 8001efc: d002 beq.n 8001f04 //Got battery status GBT_SwitchState(GBT_S7_BMS_WAIT); 8001efe: 2017 movs r0, #23 8001f00: f000 f976 bl 80021f0 } if((GBT_StateTick()>5000) && (GBT_BAT_STAT_recv == 0)){ 8001f04: f000 fa04 bl 8002310 8001f08: 4603 mov r3, r0 8001f0a: f241 3288 movw r2, #5000 ; 0x1388 8001f0e: 4293 cmp r3, r2 8001f10: f240 8137 bls.w 8002182 8001f14: 4ba4 ldr r3, [pc, #656] ; (80021a8 ) 8001f16: 781b ldrb r3, [r3, #0] 8001f18: 2b00 cmp r3, #0 8001f1a: f040 8132 bne.w 8002182 GBT_Error(0xFCF1C0FC); //BCP Timeout 8001f1e: 48a3 ldr r0, [pc, #652] ; (80021ac ) 8001f20: f000 fa2a bl 8002378 } break; 8001f24: e12d b.n 8002182 case GBT_S7_BMS_WAIT: if(j_rx.state == 0) GBT_SendCTS(); 8001f26: 4b9f ldr r3, [pc, #636] ; (80021a4 ) 8001f28: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 8001f2c: 2b00 cmp r3, #0 8001f2e: d101 bne.n 8001f34 8001f30: f001 fa8c bl 800344c HAL_Delay(2); 8001f34: 2002 movs r0, #2 8001f36: f003 f937 bl 80051a8 if(j_rx.state == 0) GBT_SendCML(); 8001f3a: 4b9a ldr r3, [pc, #616] ; (80021a4 ) 8001f3c: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 8001f40: 2b00 cmp r3, #0 8001f42: d101 bne.n 8001f48 8001f44: f001 fa98 bl 8003478 GBT_Delay(250); 8001f48: 20fa movs r0, #250 ; 0xfa 8001f4a: f000 f9ed bl 8002328 if((GBT_StateTick()>5000) && (GBT_BRO_recv == 0)){ 8001f4e: f000 f9df bl 8002310 8001f52: 4603 mov r3, r0 8001f54: f241 3288 movw r2, #5000 ; 0x1388 8001f58: 4293 cmp r3, r2 8001f5a: d906 bls.n 8001f6a 8001f5c: 4b94 ldr r3, [pc, #592] ; (80021b0 ) 8001f5e: 781b ldrb r3, [r3, #0] 8001f60: 2b00 cmp r3, #0 8001f62: d102 bne.n 8001f6a GBT_Error(0xFCF4C0FC); //BRO Timeout 8001f64: 4893 ldr r0, [pc, #588] ; (80021b4 ) 8001f66: f000 fa07 bl 8002378 } if(EV_ready){ 8001f6a: 4b93 ldr r3, [pc, #588] ; (80021b8 ) 8001f6c: 781b ldrb r3, [r3, #0] 8001f6e: 2b00 cmp r3, #0 8001f70: d003 beq.n 8001f7a //EV ready (AA) GBT_SwitchState(GBT_S8_INIT_CHARGER); 8001f72: 2018 movs r0, #24 8001f74: f000 f93c bl 80021f0 }else{ if((GBT_StateTick()>60000) && (GBT_BRO_recv == 1)){ GBT_Error(0xFCF4C0FC); //BRO Timeout } } break; 8001f78: e105 b.n 8002186 if((GBT_StateTick()>60000) && (GBT_BRO_recv == 1)){ 8001f7a: f000 f9c9 bl 8002310 8001f7e: 4603 mov r3, r0 8001f80: f64e 2260 movw r2, #60000 ; 0xea60 8001f84: 4293 cmp r3, r2 8001f86: f240 80fe bls.w 8002186 8001f8a: 4b89 ldr r3, [pc, #548] ; (80021b0 ) 8001f8c: 781b ldrb r3, [r3, #0] 8001f8e: 2b01 cmp r3, #1 8001f90: f040 80f9 bne.w 8002186 GBT_Error(0xFCF4C0FC); //BRO Timeout 8001f94: 4887 ldr r0, [pc, #540] ; (80021b4 ) 8001f96: f000 f9ef bl 8002378 break; 8001f9a: e0f4 b.n 8002186 case GBT_S8_INIT_CHARGER: if(j_rx.state == 0) GBT_SendCRO(0x00); 8001f9c: 4b81 ldr r3, [pc, #516] ; (80021a4 ) 8001f9e: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 8001fa2: 2b00 cmp r3, #0 8001fa4: d102 bne.n 8001fac 8001fa6: 2000 movs r0, #0 8001fa8: f001 fa9e bl 80034e8 //TODO GBT_Delay(250); 8001fac: 20fa movs r0, #250 ; 0xfa 8001fae: f000 f9bb bl 8002328 if(GBT_StateTick()>1500){ 8001fb2: f000 f9ad bl 8002310 8001fb6: 4603 mov r3, r0 8001fb8: f240 52dc movw r2, #1500 ; 0x5dc 8001fbc: 4293 cmp r3, r2 8001fbe: f240 80e4 bls.w 800218a //Power Modules initiated GBT_SwitchState(GBT_S9_WAIT_BCL); 8001fc2: 2019 movs r0, #25 8001fc4: f000 f914 bl 80021f0 } break; 8001fc8: e0df b.n 800218a case GBT_S9_WAIT_BCL: if(j_rx.state == 0) GBT_SendCRO(0xAA); 8001fca: 4b76 ldr r3, [pc, #472] ; (80021a4 ) 8001fcc: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 8001fd0: 2b00 cmp r3, #0 8001fd2: d102 bne.n 8001fda 8001fd4: 20aa movs r0, #170 ; 0xaa 8001fd6: f001 fa87 bl 80034e8 GBT_Delay(250); 8001fda: 20fa movs r0, #250 ; 0xfa 8001fdc: f000 f9a4 bl 8002328 if(GBT_ReqPower.chargingMode != 0){ //REFACTORING 8001fe0: 4b76 ldr r3, [pc, #472] ; (80021bc ) 8001fe2: 791b ldrb r3, [r3, #4] 8001fe4: 2b00 cmp r3, #0 8001fe6: f000 80d2 beq.w 800218e //BCL power requirements received GBT_SwitchState(GBT_S10_CHARGING); 8001fea: 2020 movs r0, #32 8001fec: f000 f900 bl 80021f0 CONN_SetState(CONN_Occupied_charging); 8001ff0: 2005 movs r0, #5 8001ff2: f000 fae7 bl 80025c4 uint16_t curr=4000-GBT_ReqPower.requestedCurrent; 8001ff6: 4b71 ldr r3, [pc, #452] ; (80021bc ) 8001ff8: 885b ldrh r3, [r3, #2] 8001ffa: f5c3 637a rsb r3, r3, #4000 ; 0xfa0 8001ffe: 807b strh r3, [r7, #2] uint16_t volt=GBT_ReqPower.requestedVoltage; 8002000: 4b6e ldr r3, [pc, #440] ; (80021bc ) 8002002: 881b ldrh r3, [r3, #0] 8002004: 803b strh r3, [r7, #0] //TODO Limits GBT_EDCAN_Output.requestedVoltage = volt; 8002006: 4b6e ldr r3, [pc, #440] ; (80021c0 ) 8002008: 883a ldrh r2, [r7, #0] 800200a: f8a3 2001 strh.w r2, [r3, #1] GBT_EDCAN_Output.requestedCurrent = curr; 800200e: 4b6c ldr r3, [pc, #432] ; (80021c0 ) 8002010: 887a ldrh r2, [r7, #2] 8002012: f8a3 2003 strh.w r2, [r3, #3] GBT_EDCAN_Output.enablePSU = 1; 8002016: 4b6a ldr r3, [pc, #424] ; (80021c0 ) 8002018: 2201 movs r2, #1 800201a: 701a strb r2, [r3, #0] GBT_TimeChargingStarted = get_Current_Time(); 800201c: f002 fcdc bl 80049d8 8002020: 4603 mov r3, r0 8002022: 461a mov r2, r3 8002024: 4b67 ldr r3, [pc, #412] ; (80021c4 ) 8002026: 601a str r2, [r3, #0] //TODO: EDCAN_SendPacketRead } break; 8002028: e0b1 b.n 800218e case GBT_S10_CHARGING: //CHARGING //TODO BCL BCS BSM missing ERRORS if(GBT_EDCAN_Input.chargeControl == CHARGING_NOT_ALLOWED) GBT_Stop(GBT_CST_SUSPENDS_ARTIFICIALLY); 800202a: 4b67 ldr r3, [pc, #412] ; (80021c8 ) 800202c: 795b ldrb r3, [r3, #5] 800202e: 2b01 cmp r3, #1 8002030: d102 bne.n 8002038 8002032: 4866 ldr r0, [pc, #408] ; (80021cc ) 8002034: f000 f98a bl 800234c if(GBT_EDCAN_Input.chargeControl == FORCE_UNLOCK) GBT_Stop(GBT_CST_SUSPENDS_ARTIFICIALLY);//GBT_ForceStop(); 8002038: 4b63 ldr r3, [pc, #396] ; (80021c8 ) 800203a: 795b ldrb r3, [r3, #5] 800203c: 2b03 cmp r3, #3 800203e: d102 bne.n 8002046 8002040: 4862 ldr r0, [pc, #392] ; (80021cc ) 8002042: f000 f983 bl 800234c if(GBT_LockState.error) GBT_Stop(GBT_CST_OTHERFALUT); 8002046: 4b62 ldr r3, [pc, #392] ; (80021d0 ) 8002048: 785b ldrb r3, [r3, #1] 800204a: 2b00 cmp r3, #0 800204c: d003 beq.n 8002056 800204e: f24f 40f0 movw r0, #62704 ; 0xf4f0 8002052: f000 f97b bl 800234c //GBT_ChargerCurrentStatus.chargingPermissible = 0b1111111111111100;//NOT PERMITTED GBT_ChargerCurrentStatus.chargingPermissible = 0b1111111111111101; 8002056: 4b5f ldr r3, [pc, #380] ; (80021d4 ) 8002058: f64f 72fd movw r2, #65533 ; 0xfffd 800205c: 80da strh r2, [r3, #6] GBT_ChargerCurrentStatus.chargingTime = (get_Current_Time() - GBT_TimeChargingStarted)/60; 800205e: f002 fcbb bl 80049d8 8002062: 4603 mov r3, r0 8002064: 461a mov r2, r3 8002066: 4b57 ldr r3, [pc, #348] ; (80021c4 ) 8002068: 681b ldr r3, [r3, #0] 800206a: 1ad3 subs r3, r2, r3 800206c: 4a5a ldr r2, [pc, #360] ; (80021d8 ) 800206e: fba2 2303 umull r2, r3, r2, r3 8002072: 095b lsrs r3, r3, #5 8002074: b29a uxth r2, r3 8002076: 4b57 ldr r3, [pc, #348] ; (80021d4 ) 8002078: 809a strh r2, [r3, #4] // GBT_ChargerCurrentStatus.outputCurrent = 4000 - GBT_EDCAN_Output.requestedCurrent; // GBT_ChargerCurrentStatus.outputVoltage = GBT_EDCAN_Output.requestedVoltage; GBT_ChargerCurrentStatus.outputCurrent = 4000 - GBT_EDCAN_Input.measuredCurrent; 800207a: 4b53 ldr r3, [pc, #332] ; (80021c8 ) 800207c: f8b3 3003 ldrh.w r3, [r3, #3] 8002080: b29b uxth r3, r3 8002082: f5c3 637a rsb r3, r3, #4000 ; 0xfa0 8002086: b29a uxth r2, r3 8002088: 4b52 ldr r3, [pc, #328] ; (80021d4 ) 800208a: 805a strh r2, [r3, #2] GBT_ChargerCurrentStatus.outputVoltage = GBT_EDCAN_Input.measuredVoltage; 800208c: 4b4e ldr r3, [pc, #312] ; (80021c8 ) 800208e: f8b3 3001 ldrh.w r3, [r3, #1] 8002092: b29a uxth r2, r3 8002094: 4b4f ldr r3, [pc, #316] ; (80021d4 ) 8002096: 801a strh r2, [r3, #0] GBT_EDCAN_Output.chargingElapsedTimeMin = (get_Current_Time() - GBT_TimeChargingStarted)/60; 8002098: f002 fc9e bl 80049d8 800209c: 4603 mov r3, r0 800209e: 461a mov r2, r3 80020a0: 4b48 ldr r3, [pc, #288] ; (80021c4 ) 80020a2: 681b ldr r3, [r3, #0] 80020a4: 1ad3 subs r3, r2, r3 80020a6: 4a4c ldr r2, [pc, #304] ; (80021d8 ) 80020a8: fba2 2303 umull r2, r3, r2, r3 80020ac: 095b lsrs r3, r3, #5 80020ae: b29a uxth r2, r3 80020b0: 4b43 ldr r3, [pc, #268] ; (80021c0 ) 80020b2: f8a3 2009 strh.w r2, [r3, #9] GBT_EDCAN_Output.chargingElapsedTimeSec = (get_Current_Time() - GBT_TimeChargingStarted)%60; 80020b6: f002 fc8f bl 80049d8 80020ba: 4603 mov r3, r0 80020bc: 461a mov r2, r3 80020be: 4b41 ldr r3, [pc, #260] ; (80021c4 ) 80020c0: 681b ldr r3, [r3, #0] 80020c2: 1ad1 subs r1, r2, r3 80020c4: 4b44 ldr r3, [pc, #272] ; (80021d8 ) 80020c6: fba3 2301 umull r2, r3, r3, r1 80020ca: 095a lsrs r2, r3, #5 80020cc: 4613 mov r3, r2 80020ce: 011b lsls r3, r3, #4 80020d0: 1a9b subs r3, r3, r2 80020d2: 009b lsls r3, r3, #2 80020d4: 1aca subs r2, r1, r3 80020d6: b2d2 uxtb r2, r2 80020d8: 4b39 ldr r3, [pc, #228] ; (80021c0 ) 80020da: 72da strb r2, [r3, #11] if(j_rx.state == 0) GBT_SendCCS(); 80020dc: 4b31 ldr r3, [pc, #196] ; (80021a4 ) 80020de: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 80020e2: 2b00 cmp r3, #0 80020e4: d101 bne.n 80020ea 80020e6: f001 fa13 bl 8003510 GBT_Delay(50); 80020ea: 2032 movs r0, #50 ; 0x32 80020ec: f000 f91c bl 8002328 break; 80020f0: e054 b.n 800219c case GBT_STOP: GBT_Delay(10); 80020f2: 200a movs r0, #10 80020f4: f000 f918 bl 8002328 GBT_EDCAN_Output.enablePSU = 0; 80020f8: 4b31 ldr r3, [pc, #196] ; (80021c0 ) 80020fa: 2200 movs r2, #0 80020fc: 701a strb r2, [r3, #0] GBT_SendCST(GBT_StopCauseCode); 80020fe: 4b37 ldr r3, [pc, #220] ; (80021dc ) 8002100: 681b ldr r3, [r3, #0] 8002102: 4618 mov r0, r3 8002104: f001 fa12 bl 800352c //RELAY_Write(RELAY_OUTPUT, 0); //GBT_SwitchState(GBT_DISABLED); if(GBT_StateTick()>10000){ 8002108: f000 f902 bl 8002310 800210c: 4603 mov r3, r0 800210e: f242 7210 movw r2, #10000 ; 0x2710 8002112: 4293 cmp r3, r2 8002114: d902 bls.n 800211c GBT_Error(0xFCF0C0FD); //BSD Timeout 8002116: 4832 ldr r0, [pc, #200] ; (80021e0 ) 8002118: f000 f92e bl 8002378 } if(GBT_BSD_recv != 0){ 800211c: 4b31 ldr r3, [pc, #196] ; (80021e4 ) 800211e: 781b ldrb r3, [r3, #0] 8002120: 2b00 cmp r3, #0 8002122: d036 beq.n 8002192 GBT_SwitchState(GBT_STOP_CSD); 8002124: 2022 movs r0, #34 ; 0x22 8002126: f000 f863 bl 80021f0 } break; 800212a: e032 b.n 8002192 case GBT_STOP_CSD: GBT_Delay(250); 800212c: 20fa movs r0, #250 ; 0xfa 800212e: f000 f8fb bl 8002328 GBT_SendCSD(); 8002132: f001 fa1b bl 800356c if(GBT_StateTick()>2500){ //2.5S 8002136: f000 f8eb bl 8002310 800213a: 4603 mov r3, r0 800213c: f640 12c4 movw r2, #2500 ; 0x9c4 8002140: 4293 cmp r3, r2 8002142: d928 bls.n 8002196 GBT_SwitchState(GBT_COMPLETE); 8002144: 2024 movs r0, #36 ; 0x24 8002146: f000 f853 bl 80021f0 // GBT_Reset(); //CONN_SetState(CONN_Occupied_complete); //if(connectorState == CONN_Occupied_charging) //PSU_Mode(0x0100); } break; 800214a: e024 b.n 8002196 case GBT_ERROR: GBT_SendCEM(GBT_ErrorCode); //2.5S 800214c: 4b26 ldr r3, [pc, #152] ; (80021e8 ) 800214e: 681b ldr r3, [r3, #0] 8002150: 4618 mov r0, r3 8002152: f001 fa2b bl 80035ac GBT_SwitchState(GBT_COMPLETE); 8002156: 2024 movs r0, #36 ; 0x24 8002158: f000 f84a bl 80021f0 // GBT_Reset(); // break; 800215c: e01e b.n 800219c case GBT_COMPLETE: if(connectorState != CONN_Occupied_complete) GBT_SwitchState(GBT_DISABLED); 800215e: 4b23 ldr r3, [pc, #140] ; (80021ec ) 8002160: 781b ldrb r3, [r3, #0] 8002162: 2b06 cmp r3, #6 8002164: d019 beq.n 800219a 8002166: 2010 movs r0, #16 8002168: f000 f842 bl 80021f0 break; 800216c: e015 b.n 800219a default: GBT_SwitchState(GBT_DISABLED); 800216e: 2010 movs r0, #16 8002170: f000 f83e bl 80021f0 } } 8002174: e012 b.n 800219c break; 8002176: bf00 nop 8002178: e010 b.n 800219c break; 800217a: bf00 nop 800217c: e00e b.n 800219c break; 800217e: bf00 nop 8002180: e00c b.n 800219c break; 8002182: bf00 nop 8002184: e00a b.n 800219c break; 8002186: bf00 nop 8002188: e008 b.n 800219c break; 800218a: bf00 nop 800218c: e006 b.n 800219c break; 800218e: bf00 nop 8002190: e004 b.n 800219c break; 8002192: bf00 nop 8002194: e002 b.n 800219c break; 8002196: bf00 nop 8002198: e000 b.n 800219c break; 800219a: bf00 nop } 800219c: bf00 nop 800219e: 3708 adds r7, #8 80021a0: 46bd mov sp, r7 80021a2: bdb0 pop {r4, r5, r7, pc} 80021a4: 200004c0 .word 0x200004c0 80021a8: 200002f1 .word 0x200002f1 80021ac: fcf1c0fc .word 0xfcf1c0fc 80021b0: 200002f2 .word 0x200002f2 80021b4: fcf4c0fc .word 0xfcf4c0fc 80021b8: 200002f5 .word 0x200002f5 80021bc: 20000350 .word 0x20000350 80021c0: 200004a8 .word 0x200004a8 80021c4: 20000388 .word 0x20000388 80021c8: 200004b8 .word 0x200004b8 80021cc: 0400f0f0 .word 0x0400f0f0 80021d0: 200005d0 .word 0x200005d0 80021d4: 20000374 .word 0x20000374 80021d8: 88888889 .word 0x88888889 80021dc: 2000038c .word 0x2000038c 80021e0: fcf0c0fd .word 0xfcf0c0fd 80021e4: 200002f4 .word 0x200002f4 80021e8: 20000390 .word 0x20000390 80021ec: 20000394 .word 0x20000394 080021f0 : void GBT_SwitchState(gbtState_t state){ 80021f0: b580 push {r7, lr} 80021f2: b082 sub sp, #8 80021f4: af00 add r7, sp, #0 80021f6: 4603 mov r3, r0 80021f8: 71fb strb r3, [r7, #7] GBT_State = state; 80021fa: 4a35 ldr r2, [pc, #212] ; (80022d0 ) 80021fc: 79fb ldrb r3, [r7, #7] 80021fe: 7013 strb r3, [r2, #0] ED_status = state; 8002200: 4a34 ldr r2, [pc, #208] ; (80022d4 ) 8002202: 79fb ldrb r3, [r7, #7] 8002204: 7013 strb r3, [r2, #0] GBT_state_tick = HAL_GetTick(); 8002206: f002 ffc5 bl 8005194 800220a: 4603 mov r3, r0 800220c: 4a32 ldr r2, [pc, #200] ; (80022d8 ) 800220e: 6013 str r3, [r2, #0] if(GBT_State == GBT_DISABLED) printf ("GBT_DISABLED\n"); 8002210: 4b2f ldr r3, [pc, #188] ; (80022d0 ) 8002212: 781b ldrb r3, [r3, #0] 8002214: 2b10 cmp r3, #16 8002216: d102 bne.n 800221e 8002218: 4830 ldr r0, [pc, #192] ; (80022dc ) 800221a: f007 fdc1 bl 8009da0 // if(GBT_State == GBT_S0_UNCONNECTED) printf ("GBT_S0_UNCONNECTED\n"); // if(GBT_State == GBT_S1_CONNECTED) printf ("GBT_S1_CONNECTED\n"); // if(GBT_State == GBT_S2_LOCKED) printf ("GBT_S2_LOCKED\n"); if(GBT_State == GBT_S3_STARTED) printf ("GBT_S3_STARTED\n"); 800221e: 4b2c ldr r3, [pc, #176] ; (80022d0 ) 8002220: 781b ldrb r3, [r3, #0] 8002222: 2b13 cmp r3, #19 8002224: d102 bne.n 800222c 8002226: 482e ldr r0, [pc, #184] ; (80022e0 ) 8002228: f007 fdba bl 8009da0 if(GBT_State == GBT_S4_ISOTEST) printf ("GBT_S4_ISOTEST\n"); 800222c: 4b28 ldr r3, [pc, #160] ; (80022d0 ) 800222e: 781b ldrb r3, [r3, #0] 8002230: 2b14 cmp r3, #20 8002232: d102 bne.n 800223a 8002234: 482b ldr r0, [pc, #172] ; (80022e4 ) 8002236: f007 fdb3 bl 8009da0 if(GBT_State == GBT_S5_BAT_INFO) printf ("GBT_S5_BAT_INFO\n"); 800223a: 4b25 ldr r3, [pc, #148] ; (80022d0 ) 800223c: 781b ldrb r3, [r3, #0] 800223e: 2b15 cmp r3, #21 8002240: d102 bne.n 8002248 8002242: 4829 ldr r0, [pc, #164] ; (80022e8 ) 8002244: f007 fdac bl 8009da0 if(GBT_State == GBT_S6_BAT_STAT) printf ("GBT_S6_BAT_STAT\n"); 8002248: 4b21 ldr r3, [pc, #132] ; (80022d0 ) 800224a: 781b ldrb r3, [r3, #0] 800224c: 2b16 cmp r3, #22 800224e: d102 bne.n 8002256 8002250: 4826 ldr r0, [pc, #152] ; (80022ec ) 8002252: f007 fda5 bl 8009da0 if(GBT_State == GBT_S7_BMS_WAIT) printf ("GBT_S7_BMS_WAIT\n"); 8002256: 4b1e ldr r3, [pc, #120] ; (80022d0 ) 8002258: 781b ldrb r3, [r3, #0] 800225a: 2b17 cmp r3, #23 800225c: d102 bne.n 8002264 800225e: 4824 ldr r0, [pc, #144] ; (80022f0 ) 8002260: f007 fd9e bl 8009da0 if(GBT_State == GBT_S8_INIT_CHARGER)printf ("GBT_S8_INIT_CHARGER\n"); 8002264: 4b1a ldr r3, [pc, #104] ; (80022d0 ) 8002266: 781b ldrb r3, [r3, #0] 8002268: 2b18 cmp r3, #24 800226a: d102 bne.n 8002272 800226c: 4821 ldr r0, [pc, #132] ; (80022f4 ) 800226e: f007 fd97 bl 8009da0 if(GBT_State == GBT_S9_WAIT_BCL) printf ("GBT_S9_WAIT_BCL\n"); 8002272: 4b17 ldr r3, [pc, #92] ; (80022d0 ) 8002274: 781b ldrb r3, [r3, #0] 8002276: 2b19 cmp r3, #25 8002278: d102 bne.n 8002280 800227a: 481f ldr r0, [pc, #124] ; (80022f8 ) 800227c: f007 fd90 bl 8009da0 if(GBT_State == GBT_S10_CHARGING) printf ("GBT_S10_CHARGING\n"); 8002280: 4b13 ldr r3, [pc, #76] ; (80022d0 ) 8002282: 781b ldrb r3, [r3, #0] 8002284: 2b20 cmp r3, #32 8002286: d102 bne.n 800228e 8002288: 481c ldr r0, [pc, #112] ; (80022fc ) 800228a: f007 fd89 bl 8009da0 if(GBT_State == GBT_STOP) printf ("GBT_STOP\n"); 800228e: 4b10 ldr r3, [pc, #64] ; (80022d0 ) 8002290: 781b ldrb r3, [r3, #0] 8002292: 2b21 cmp r3, #33 ; 0x21 8002294: d102 bne.n 800229c 8002296: 481a ldr r0, [pc, #104] ; (8002300 ) 8002298: f007 fd82 bl 8009da0 if(GBT_State == GBT_STOP_CSD) printf ("GBT_STOP_CSD\n"); 800229c: 4b0c ldr r3, [pc, #48] ; (80022d0 ) 800229e: 781b ldrb r3, [r3, #0] 80022a0: 2b22 cmp r3, #34 ; 0x22 80022a2: d102 bne.n 80022aa 80022a4: 4817 ldr r0, [pc, #92] ; (8002304 ) 80022a6: f007 fd7b bl 8009da0 if(GBT_State == GBT_ERROR) printf ("GBT_ERROR\n"); 80022aa: 4b09 ldr r3, [pc, #36] ; (80022d0 ) 80022ac: 781b ldrb r3, [r3, #0] 80022ae: 2b23 cmp r3, #35 ; 0x23 80022b0: d102 bne.n 80022b8 80022b2: 4815 ldr r0, [pc, #84] ; (8002308 ) 80022b4: f007 fd74 bl 8009da0 if(GBT_State == GBT_COMPLETE) printf ("GBT_COMPLETE\n"); 80022b8: 4b05 ldr r3, [pc, #20] ; (80022d0 ) 80022ba: 781b ldrb r3, [r3, #0] 80022bc: 2b24 cmp r3, #36 ; 0x24 80022be: d102 bne.n 80022c6 80022c0: 4812 ldr r0, [pc, #72] ; (800230c ) 80022c2: f007 fd6d bl 8009da0 } 80022c6: bf00 nop 80022c8: 3708 adds r7, #8 80022ca: 46bd mov sp, r7 80022cc: bd80 pop {r7, pc} 80022ce: bf00 nop 80022d0: 200002e4 .word 0x200002e4 80022d4: 20003326 .word 0x20003326 80022d8: 200002e8 .word 0x200002e8 80022dc: 0800cc88 .word 0x0800cc88 80022e0: 0800cc98 .word 0x0800cc98 80022e4: 0800cca8 .word 0x0800cca8 80022e8: 0800ccb8 .word 0x0800ccb8 80022ec: 0800ccc8 .word 0x0800ccc8 80022f0: 0800ccd8 .word 0x0800ccd8 80022f4: 0800cce8 .word 0x0800cce8 80022f8: 0800ccfc .word 0x0800ccfc 80022fc: 0800cd0c .word 0x0800cd0c 8002300: 0800cd20 .word 0x0800cd20 8002304: 0800cd2c .word 0x0800cd2c 8002308: 0800cd3c .word 0x0800cd3c 800230c: 0800cd48 .word 0x0800cd48 08002310 : uint32_t GBT_StateTick(){ 8002310: b580 push {r7, lr} 8002312: af00 add r7, sp, #0 return HAL_GetTick() - GBT_state_tick; 8002314: f002 ff3e bl 8005194 8002318: 4602 mov r2, r0 800231a: 4b02 ldr r3, [pc, #8] ; (8002324 ) 800231c: 681b ldr r3, [r3, #0] 800231e: 1ad3 subs r3, r2, r3 } 8002320: 4618 mov r0, r3 8002322: bd80 pop {r7, pc} 8002324: 200002e8 .word 0x200002e8 08002328 : void GBT_Delay(uint32_t delay){ 8002328: b580 push {r7, lr} 800232a: b082 sub sp, #8 800232c: af00 add r7, sp, #0 800232e: 6078 str r0, [r7, #4] GBT_delay = HAL_GetTick()+delay; 8002330: f002 ff30 bl 8005194 8002334: 4602 mov r2, r0 8002336: 687b ldr r3, [r7, #4] 8002338: 4413 add r3, r2 800233a: 4a03 ldr r2, [pc, #12] ; (8002348 ) 800233c: 6013 str r3, [r2, #0] } 800233e: bf00 nop 8002340: 3708 adds r7, #8 8002342: 46bd mov sp, r7 8002344: bd80 pop {r7, pc} 8002346: bf00 nop 8002348: 200002ec .word 0x200002ec 0800234c : void GBT_Stop(uint32_t causecode){ 800234c: b580 push {r7, lr} 800234e: b082 sub sp, #8 8002350: af00 add r7, sp, #0 8002352: 6078 str r0, [r7, #4] GBT_StopCauseCode = causecode; 8002354: 4a06 ldr r2, [pc, #24] ; (8002370 ) 8002356: 687b ldr r3, [r7, #4] 8002358: 6013 str r3, [r2, #0] if(GBT_State != GBT_STOP) GBT_SwitchState(GBT_STOP); 800235a: 4b06 ldr r3, [pc, #24] ; (8002374 ) 800235c: 781b ldrb r3, [r3, #0] 800235e: 2b21 cmp r3, #33 ; 0x21 8002360: d002 beq.n 8002368 8002362: 2021 movs r0, #33 ; 0x21 8002364: f7ff ff44 bl 80021f0 } 8002368: bf00 nop 800236a: 3708 adds r7, #8 800236c: 46bd mov sp, r7 800236e: bd80 pop {r7, pc} 8002370: 2000038c .word 0x2000038c 8002374: 200002e4 .word 0x200002e4 08002378 : void GBT_Error(uint32_t errorcode){ 8002378: b580 push {r7, lr} 800237a: b082 sub sp, #8 800237c: af00 add r7, sp, #0 800237e: 6078 str r0, [r7, #4] GBT_ErrorCode = errorcode; 8002380: 4a04 ldr r2, [pc, #16] ; (8002394 ) 8002382: 687b ldr r3, [r7, #4] 8002384: 6013 str r3, [r2, #0] GBT_SwitchState(GBT_ERROR); 8002386: 2023 movs r0, #35 ; 0x23 8002388: f7ff ff32 bl 80021f0 } 800238c: bf00 nop 800238e: 3708 adds r7, #8 8002390: 46bd mov sp, r7 8002392: bd80 pop {r7, pc} 8002394: 20000390 .word 0x20000390 08002398 : void GBT_ForceStop(){ 8002398: b580 push {r7, lr} 800239a: af00 add r7, sp, #0 GBT_EDCAN_Output.enablePSU = 0; 800239c: 4b07 ldr r3, [pc, #28] ; (80023bc ) 800239e: 2200 movs r2, #0 80023a0: 701a strb r2, [r3, #0] GBT_SwitchState(GBT_COMPLETE); 80023a2: 2024 movs r0, #36 ; 0x24 80023a4: f7ff ff24 bl 80021f0 GBT_Lock(0); 80023a8: 2000 movs r0, #0 80023aa: f001 fc61 bl 8003c70 RELAY_Write(RELAY_AUX, 0); 80023ae: 2100 movs r1, #0 80023b0: 2000 movs r0, #0 80023b2: f7ff f98f bl 80016d4 } 80023b6: bf00 nop 80023b8: bd80 pop {r7, pc} 80023ba: bf00 nop 80023bc: 200004a8 .word 0x200004a8 080023c0 : void GBT_Reset(){ 80023c0: b580 push {r7, lr} 80023c2: af00 add r7, sp, #0 GBT_BAT_INFO_recv = 0; 80023c4: 4b26 ldr r3, [pc, #152] ; (8002460 ) 80023c6: 2200 movs r2, #0 80023c8: 701a strb r2, [r3, #0] GBT_BAT_STAT_recv = 0; 80023ca: 4b26 ldr r3, [pc, #152] ; (8002464 ) 80023cc: 2200 movs r2, #0 80023ce: 701a strb r2, [r3, #0] GBT_BRO_recv = 0; 80023d0: 4b25 ldr r3, [pc, #148] ; (8002468 ) 80023d2: 2200 movs r2, #0 80023d4: 701a strb r2, [r3, #0] GBT_BHM_recv = 0; 80023d6: 4b25 ldr r3, [pc, #148] ; (800246c ) 80023d8: 2200 movs r2, #0 80023da: 701a strb r2, [r3, #0] GBT_BSD_recv = 0; 80023dc: 4b24 ldr r3, [pc, #144] ; (8002470 ) 80023de: 2200 movs r2, #0 80023e0: 701a strb r2, [r3, #0] EV_ready = 0; 80023e2: 4b24 ldr r3, [pc, #144] ; (8002474 ) 80023e4: 2200 movs r2, #0 80023e6: 701a strb r2, [r3, #0] memset(&GBT_EVInfo, 0, sizeof (GBT_EVInfo)); 80023e8: 2231 movs r2, #49 ; 0x31 80023ea: 2100 movs r1, #0 80023ec: 4822 ldr r0, [pc, #136] ; (8002478 ) 80023ee: f006 ff0d bl 800920c memset(&GBT_BATStat, 0, sizeof (GBT_BATStat)); 80023f2: 220d movs r2, #13 80023f4: 2100 movs r1, #0 80023f6: 4821 ldr r0, [pc, #132] ; (800247c ) 80023f8: f006 ff08 bl 800920c memset(&GBT_ReqPower, 0, sizeof (GBT_ReqPower)); 80023fc: 2205 movs r2, #5 80023fe: 2100 movs r1, #0 8002400: 481f ldr r0, [pc, #124] ; (8002480 ) 8002402: f006 ff03 bl 800920c memset(&GBT_CurrPower, 0, sizeof (GBT_CurrPower)); 8002406: 2205 movs r2, #5 8002408: 2100 movs r1, #0 800240a: 481e ldr r0, [pc, #120] ; (8002484 ) 800240c: f006 fefe bl 800920c memset(&GBT_MaxVoltage, 0, sizeof (GBT_MaxVoltage)); 8002410: 2202 movs r2, #2 8002412: 2100 movs r1, #0 8002414: 481c ldr r0, [pc, #112] ; (8002488 ) 8002416: f006 fef9 bl 800920c memset(&GBT_ChargingStatus, 0, sizeof (GBT_ChargingStatus)); 800241a: 2209 movs r2, #9 800241c: 2100 movs r1, #0 800241e: 481b ldr r0, [pc, #108] ; (800248c ) 8002420: f006 fef4 bl 800920c memset(&GBT_BatteryStatus, 0, sizeof (GBT_BatteryStatus)); 8002424: 2207 movs r2, #7 8002426: 2100 movs r1, #0 8002428: 4819 ldr r0, [pc, #100] ; (8002490 ) 800242a: f006 feef bl 800920c memset(&GBT_ChargerCurrentStatus, 0, sizeof (GBT_ChargerCurrentStatus)); 800242e: 2208 movs r2, #8 8002430: 2100 movs r1, #0 8002432: 4818 ldr r0, [pc, #96] ; (8002494 ) 8002434: f006 feea bl 800920c memset(&GBT_ChargerStop, 0, sizeof (GBT_ChargerStop)); 8002438: 2208 movs r2, #8 800243a: 2100 movs r1, #0 800243c: 4816 ldr r0, [pc, #88] ; (8002498 ) 800243e: f006 fee5 bl 800920c GBT_CurrPower.requestedCurrent = 4000; //0A 8002442: 4b10 ldr r3, [pc, #64] ; (8002484 ) 8002444: f44f 627a mov.w r2, #4000 ; 0xfa0 8002448: 805a strh r2, [r3, #2] GBT_CurrPower.requestedVoltage = 0; //0V 800244a: 4b0e ldr r3, [pc, #56] ; (8002484 ) 800244c: 2200 movs r2, #0 800244e: 801a strh r2, [r3, #0] GBT_TimeChargingStarted = 0; 8002450: 4b12 ldr r3, [pc, #72] ; (800249c ) 8002452: 2200 movs r2, #0 8002454: 601a str r2, [r3, #0] GBT_BRO = 0x00; 8002456: 4b12 ldr r3, [pc, #72] ; (80024a0 ) 8002458: 2200 movs r2, #0 800245a: 701a strb r2, [r3, #0] } 800245c: bf00 nop 800245e: bd80 pop {r7, pc} 8002460: 200002f0 .word 0x200002f0 8002464: 200002f1 .word 0x200002f1 8002468: 200002f2 .word 0x200002f2 800246c: 200002f3 .word 0x200002f3 8002470: 200002f4 .word 0x200002f4 8002474: 200002f5 .word 0x200002f5 8002478: 2000030c .word 0x2000030c 800247c: 20000340 .word 0x20000340 8002480: 20000350 .word 0x20000350 8002484: 20000358 .word 0x20000358 8002488: 20000308 .word 0x20000308 800248c: 20000360 .word 0x20000360 8002490: 2000036c .word 0x2000036c 8002494: 20000374 .word 0x20000374 8002498: 2000037c .word 0x2000037c 800249c: 20000388 .word 0x20000388 80024a0: 20000384 .word 0x20000384 080024a4 : void GBT_Start(){ 80024a4: b580 push {r7, lr} 80024a6: af00 add r7, sp, #0 RELAY_Write(RELAY_AUX, 1); 80024a8: 2101 movs r1, #1 80024aa: 2000 movs r0, #0 80024ac: f7ff f912 bl 80016d4 GBT_SwitchState(GBT_S3_STARTED); 80024b0: 2013 movs r0, #19 80024b2: f7ff fe9d bl 80021f0 } 80024b6: bf00 nop 80024b8: bd80 pop {r7, pc} 080024ba : extern GBT_EDCAN_Output_t GBT_EDCAN_Output; extern GBT_EDCAN_Input_t GBT_EDCAN_Input; uint8_t CC_STATE_FILTERED; void CONN_Init(){ 80024ba: b580 push {r7, lr} 80024bc: af00 add r7, sp, #0 CONN_SetState(CONN_Initializing); 80024be: 2001 movs r0, #1 80024c0: f000 f880 bl 80025c4 } 80024c4: bf00 nop 80024c6: bd80 pop {r7, pc} 080024c8 : void CONN_Task(){ 80024c8: b580 push {r7, lr} 80024ca: af00 add r7, sp, #0 switch (connectorState){ 80024cc: 4b39 ldr r3, [pc, #228] ; (80025b4 ) 80024ce: 781b ldrb r3, [r3, #0] 80024d0: 3b01 subs r3, #1 80024d2: 2b05 cmp r3, #5 80024d4: d861 bhi.n 800259a 80024d6: a201 add r2, pc, #4 ; (adr r2, 80024dc ) 80024d8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80024dc: 080024f5 .word 0x080024f5 80024e0: 08002509 .word 0x08002509 80024e4: 08002511 .word 0x08002511 80024e8: 08002537 .word 0x08002537 80024ec: 0800256d .word 0x0800256d 80024f0: 08002583 .word 0x08002583 case CONN_Initializing: // unlocked GBT_Lock(0); 80024f4: 2000 movs r0, #0 80024f6: f001 fbbb bl 8003c70 CONN_SetState(CONN_Available); 80024fa: 2003 movs r0, #3 80024fc: f000 f862 bl 80025c4 GBT_LockState.error = 0; 8002500: 4b2d ldr r3, [pc, #180] ; (80025b8 ) 8002502: 2200 movs r2, #0 8002504: 705a strb r2, [r3, #1] break; 8002506: e053 b.n 80025b0 case CONN_Error: //unlocked GBT_Lock(0); 8002508: 2000 movs r0, #0 800250a: f001 fbb1 bl 8003c70 break; 800250e: e04f b.n 80025b0 case CONN_Available: //unlocked, waiting to connect GBT_Lock(0); 8002510: 2000 movs r0, #0 8002512: f001 fbad bl 8003c70 if((CONN_CC_GetState()==GBT_CC_4V) && (GBT_EDCAN_Input.chargeControl != FORCE_UNLOCK)){ 8002516: f000 f8dd bl 80026d4 800251a: 4603 mov r3, r0 800251c: 2b03 cmp r3, #3 800251e: d140 bne.n 80025a2 8002520: 4b26 ldr r3, [pc, #152] ; (80025bc ) 8002522: 795b ldrb r3, [r3, #5] 8002524: 2b03 cmp r3, #3 8002526: d03c beq.n 80025a2 CONN_SetState(CONN_Occupied_waiting); 8002528: 2004 movs r0, #4 800252a: f000 f84b bl 80025c4 GBT_Lock(1); 800252e: 2001 movs r0, #1 8002530: f001 fb9e bl 8003c70 } break; 8002534: e035 b.n 80025a2 case CONN_Occupied_waiting: //locked, waiting to charge GBT_Lock(1); 8002536: 2001 movs r0, #1 8002538: f001 fb9a bl 8003c70 if(CONN_CC_GetState()==GBT_CC_4V){ 800253c: f000 f8ca bl 80026d4 8002540: 4603 mov r3, r0 8002542: 2b03 cmp r3, #3 8002544: d10e bne.n 8002564 if(GBT_EDCAN_Input.chargeControl == CHARGING_ALLOWED){ 8002546: 4b1d ldr r3, [pc, #116] ; (80025bc ) 8002548: 795b ldrb r3, [r3, #5] 800254a: 2b02 cmp r3, #2 800254c: d102 bne.n 8002554 // RELAY_Write(RELAY_AUX, 1); // GBT_Start(); CONN_SetState(CONN_Occupied_charging); 800254e: 2005 movs r0, #5 8002550: f000 f838 bl 80025c4 } if(GBT_EDCAN_Input.chargeControl == FORCE_UNLOCK){ 8002554: 4b19 ldr r3, [pc, #100] ; (80025bc ) 8002556: 795b ldrb r3, [r3, #5] 8002558: 2b03 cmp r3, #3 800255a: d124 bne.n 80025a6 CONN_SetState(CONN_Available); 800255c: 2003 movs r0, #3 800255e: f000 f831 bl 80025c4 } //if (CHARGING_NOT_ALLOWED) stay here }else{ CONN_SetState(CONN_Available); } break; 8002562: e020 b.n 80025a6 CONN_SetState(CONN_Available); 8002564: 2003 movs r0, #3 8002566: f000 f82d bl 80025c4 break; 800256a: e01c b.n 80025a6 case CONN_Occupied_charging://charging, locked GBT_Lock(1); 800256c: 2001 movs r0, #1 800256e: f001 fb7f bl 8003c70 if(GBT_State == GBT_COMPLETE){ 8002572: 4b13 ldr r3, [pc, #76] ; (80025c0 ) 8002574: 781b ldrb r3, [r3, #0] 8002576: 2b24 cmp r3, #36 ; 0x24 8002578: d117 bne.n 80025aa CONN_SetState(CONN_Occupied_complete); 800257a: 2006 movs r0, #6 800257c: f000 f822 bl 80025c4 } // break; 8002580: e013 b.n 80025aa case CONN_Occupied_complete://charging completed, waiting to disconnect, unlocked GBT_Lock(0); 8002582: 2000 movs r0, #0 8002584: f001 fb74 bl 8003c70 // RELAY_Write(RELAY_AUX, 0); //TODO: Reconnection // if(GBT_EDCAN_Input.chargeControl == CHARGING_NOT_ALLOWED){ // CONN_SetState(CONN_Initializing); // } if(CONN_CC_GetState()==GBT_CC_6V){ 8002588: f000 f8a4 bl 80026d4 800258c: 4603 mov r3, r0 800258e: 2b02 cmp r3, #2 8002590: d10d bne.n 80025ae CONN_SetState(CONN_Initializing); 8002592: 2001 movs r0, #1 8002594: f000 f816 bl 80025c4 } //Проблема, если нажать кнопку и не вынуть пистолет, то он снова блочится break; 8002598: e009 b.n 80025ae default: CONN_SetState(CONN_Initializing); 800259a: 2001 movs r0, #1 800259c: f000 f812 bl 80025c4 } } 80025a0: e006 b.n 80025b0 break; 80025a2: bf00 nop 80025a4: e004 b.n 80025b0 break; 80025a6: bf00 nop 80025a8: e002 b.n 80025b0 break; 80025aa: bf00 nop 80025ac: e000 b.n 80025b0 break; 80025ae: bf00 nop } 80025b0: bf00 nop 80025b2: bd80 pop {r7, pc} 80025b4: 20000394 .word 0x20000394 80025b8: 200005d0 .word 0x200005d0 80025bc: 200004b8 .word 0x200004b8 80025c0: 200002e4 .word 0x200002e4 080025c4 : //external //CONN_SetState(CONN_Error); //CONN_SetState(CONN_Occupied_charging); //CONN_SetState(CONN_Occupied_Complete); void CONN_SetState(CONN_State_t state){ 80025c4: b580 push {r7, lr} 80025c6: b082 sub sp, #8 80025c8: af00 add r7, sp, #0 80025ca: 4603 mov r3, r0 80025cc: 71fb strb r3, [r7, #7] connectorState = state; 80025ce: 4a1a ldr r2, [pc, #104] ; (8002638 ) 80025d0: 79fb ldrb r3, [r7, #7] 80025d2: 7013 strb r3, [r2, #0] if(connectorState == CONN_Initializing) printf ("CONN_Initializing\n"); 80025d4: 4b18 ldr r3, [pc, #96] ; (8002638 ) 80025d6: 781b ldrb r3, [r3, #0] 80025d8: 2b01 cmp r3, #1 80025da: d102 bne.n 80025e2 80025dc: 4817 ldr r0, [pc, #92] ; (800263c ) 80025de: f007 fbdf bl 8009da0 if(connectorState == CONN_Error) printf ("CONN_Error\n"); 80025e2: 4b15 ldr r3, [pc, #84] ; (8002638 ) 80025e4: 781b ldrb r3, [r3, #0] 80025e6: 2b02 cmp r3, #2 80025e8: d102 bne.n 80025f0 80025ea: 4815 ldr r0, [pc, #84] ; (8002640 ) 80025ec: f007 fbd8 bl 8009da0 if(connectorState == CONN_Available) printf ("CONN_Available\n"); 80025f0: 4b11 ldr r3, [pc, #68] ; (8002638 ) 80025f2: 781b ldrb r3, [r3, #0] 80025f4: 2b03 cmp r3, #3 80025f6: d102 bne.n 80025fe 80025f8: 4812 ldr r0, [pc, #72] ; (8002644 ) 80025fa: f007 fbd1 bl 8009da0 if(connectorState == CONN_Occupied_waiting) printf ("CONN_Occupied_waiting\n"); 80025fe: 4b0e ldr r3, [pc, #56] ; (8002638 ) 8002600: 781b ldrb r3, [r3, #0] 8002602: 2b04 cmp r3, #4 8002604: d102 bne.n 800260c 8002606: 4810 ldr r0, [pc, #64] ; (8002648 ) 8002608: f007 fbca bl 8009da0 if(connectorState == CONN_Occupied_charging) printf ("CONN_Occupied_charging\n"); 800260c: 4b0a ldr r3, [pc, #40] ; (8002638 ) 800260e: 781b ldrb r3, [r3, #0] 8002610: 2b05 cmp r3, #5 8002612: d102 bne.n 800261a 8002614: 480d ldr r0, [pc, #52] ; (800264c ) 8002616: f007 fbc3 bl 8009da0 if(connectorState == CONN_Occupied_complete) printf ("CONN_Occupied_complete\n"); 800261a: 4b07 ldr r3, [pc, #28] ; (8002638 ) 800261c: 781b ldrb r3, [r3, #0] 800261e: 2b06 cmp r3, #6 8002620: d102 bne.n 8002628 8002622: 480b ldr r0, [pc, #44] ; (8002650 ) 8002624: f007 fbbc bl 8009da0 GBT_EDCAN_Output.connectorState = state; 8002628: 4a0a ldr r2, [pc, #40] ; (8002654 ) 800262a: 79fb ldrb r3, [r7, #7] 800262c: 7313 strb r3, [r2, #12] } 800262e: bf00 nop 8002630: 3708 adds r7, #8 8002632: 46bd mov sp, r7 8002634: bd80 pop {r7, pc} 8002636: bf00 nop 8002638: 20000394 .word 0x20000394 800263c: 0800cd58 .word 0x0800cd58 8002640: 0800cd6c .word 0x0800cd6c 8002644: 0800cd78 .word 0x0800cd78 8002648: 0800cd88 .word 0x0800cd88 800264c: 0800cda0 .word 0x0800cda0 8002650: 0800cdb8 .word 0x0800cdb8 8002654: 200004a8 .word 0x200004a8 08002658 : void CONN_CC_ReadStateFiltered() { 8002658: b590 push {r4, r7, lr} 800265a: b083 sub sp, #12 800265c: af00 add r7, sp, #0 static uint32_t last_change_time; static uint32_t last_check_time; static uint8_t prev_state; if((last_check_time+100)>HAL_GetTick()) return; 800265e: 4b19 ldr r3, [pc, #100] ; (80026c4 ) 8002660: 681b ldr r3, [r3, #0] 8002662: f103 0464 add.w r4, r3, #100 ; 0x64 8002666: f002 fd95 bl 8005194 800266a: 4603 mov r3, r0 800266c: 429c cmp r4, r3 800266e: d824 bhi.n 80026ba last_check_time = HAL_GetTick(); 8002670: f002 fd90 bl 8005194 8002674: 4603 mov r3, r0 8002676: 4a13 ldr r2, [pc, #76] ; (80026c4 ) 8002678: 6013 str r3, [r2, #0] uint8_t new_state = CONN_CC_GetStateRaw(); 800267a: f000 f835 bl 80026e8 800267e: 4603 mov r3, r0 8002680: 71fb strb r3, [r7, #7] if (new_state != prev_state) { 8002682: 4b11 ldr r3, [pc, #68] ; (80026c8 ) 8002684: 781b ldrb r3, [r3, #0] 8002686: 79fa ldrb r2, [r7, #7] 8002688: 429a cmp r2, r3 800268a: d008 beq.n 800269e last_change_time = HAL_GetTick(); 800268c: f002 fd82 bl 8005194 8002690: 4603 mov r3, r0 8002692: 4a0e ldr r2, [pc, #56] ; (80026cc ) 8002694: 6013 str r3, [r2, #0] prev_state = new_state; 8002696: 4a0c ldr r2, [pc, #48] ; (80026c8 ) 8002698: 79fb ldrb r3, [r7, #7] 800269a: 7013 strb r3, [r2, #0] 800269c: e00e b.n 80026bc } else if ((HAL_GetTick() - last_change_time) >= 300) { 800269e: f002 fd79 bl 8005194 80026a2: 4602 mov r2, r0 80026a4: 4b09 ldr r3, [pc, #36] ; (80026cc ) 80026a6: 681b ldr r3, [r3, #0] 80026a8: 1ad3 subs r3, r2, r3 80026aa: f5b3 7f96 cmp.w r3, #300 ; 0x12c 80026ae: d305 bcc.n 80026bc CC_STATE_FILTERED = prev_state; 80026b0: 4b05 ldr r3, [pc, #20] ; (80026c8 ) 80026b2: 781a ldrb r2, [r3, #0] 80026b4: 4b06 ldr r3, [pc, #24] ; (80026d0 ) 80026b6: 701a strb r2, [r3, #0] 80026b8: e000 b.n 80026bc if((last_check_time+100)>HAL_GetTick()) return; 80026ba: bf00 nop // case GBT_CC_2V: // printf("FGBT_CC_2V\n"); // break; // // } } 80026bc: 370c adds r7, #12 80026be: 46bd mov sp, r7 80026c0: bd90 pop {r4, r7, pc} 80026c2: bf00 nop 80026c4: 20000398 .word 0x20000398 80026c8: 2000039c .word 0x2000039c 80026cc: 200003a0 .word 0x200003a0 80026d0: 20000395 .word 0x20000395 080026d4 : uint8_t CONN_CC_GetState(){ 80026d4: b480 push {r7} 80026d6: af00 add r7, sp, #0 return CC_STATE_FILTERED; 80026d8: 4b02 ldr r3, [pc, #8] ; (80026e4 ) 80026da: 781b ldrb r3, [r3, #0] } 80026dc: 4618 mov r0, r3 80026de: 46bd mov sp, r7 80026e0: bc80 pop {r7} 80026e2: 4770 bx lr 80026e4: 20000395 .word 0x20000395 080026e8 : uint8_t CONN_CC_GetStateRaw(){ 80026e8: b580 push {r7, lr} 80026ea: b082 sub sp, #8 80026ec: af00 add r7, sp, #0 //Vin*k= 1.09v //12vin = 1353 ADC //TODO: Filter 100ms uint32_t adc; float volt; ADC_Select_Channel(ADC_CHANNEL_6); 80026ee: 2006 movs r0, #6 80026f0: f7ff f8d4 bl 800189c HAL_ADC_Start(&hadc1); 80026f4: 482e ldr r0, [pc, #184] ; (80027b0 ) 80026f6: f002 fe53 bl 80053a0 HAL_ADC_PollForConversion(&hadc1, 100); 80026fa: 2164 movs r1, #100 ; 0x64 80026fc: 482c ldr r0, [pc, #176] ; (80027b0 ) 80026fe: f002 ff29 bl 8005554 adc = HAL_ADC_GetValue(&hadc1); 8002702: 482b ldr r0, [pc, #172] ; (80027b0 ) 8002704: f003 f82c bl 8005760 8002708: 6078 str r0, [r7, #4] HAL_ADC_Stop(&hadc1); 800270a: 4829 ldr r0, [pc, #164] ; (80027b0 ) 800270c: f002 fef6 bl 80054fc volt = (float)adc/113.4f; 8002710: 6878 ldr r0, [r7, #4] 8002712: f7fe fb35 bl 8000d80 <__aeabi_ui2f> 8002716: 4603 mov r3, r0 8002718: 4926 ldr r1, [pc, #152] ; (80027b4 ) 800271a: 4618 mov r0, r3 800271c: f7fe fc3c bl 8000f98 <__aeabi_fdiv> 8002720: 4603 mov r3, r0 8002722: 603b str r3, [r7, #0] // if((volt<12.6f) && (volt>11.4f)) return GBT_CC_12V; // if((volt<6.8f) && (volt>5.2f)) return GBT_CC_6V; // if((volt<4.8f) && (volt>3.2f)) return GBT_CC_4V; // if((volt<2.8f) && (volt>1.2f)) return GBT_CC_2V; if((volt<13.0f) && (volt>11.0f)) return GBT_CC_12V; 8002724: 4924 ldr r1, [pc, #144] ; (80027b8 ) 8002726: 6838 ldr r0, [r7, #0] 8002728: f7fe fd20 bl 800116c <__aeabi_fcmplt> 800272c: 4603 mov r3, r0 800272e: 2b00 cmp r3, #0 8002730: d008 beq.n 8002744 8002732: 4922 ldr r1, [pc, #136] ; (80027bc ) 8002734: 6838 ldr r0, [r7, #0] 8002736: f7fe fd37 bl 80011a8 <__aeabi_fcmpgt> 800273a: 4603 mov r3, r0 800273c: 2b00 cmp r3, #0 800273e: d001 beq.n 8002744 8002740: 2301 movs r3, #1 8002742: e031 b.n 80027a8 if((volt<7.2f) && (volt>4.8f)) return GBT_CC_6V; 8002744: 491e ldr r1, [pc, #120] ; (80027c0 ) 8002746: 6838 ldr r0, [r7, #0] 8002748: f7fe fd10 bl 800116c <__aeabi_fcmplt> 800274c: 4603 mov r3, r0 800274e: 2b00 cmp r3, #0 8002750: d008 beq.n 8002764 8002752: 491c ldr r1, [pc, #112] ; (80027c4 ) 8002754: 6838 ldr r0, [r7, #0] 8002756: f7fe fd27 bl 80011a8 <__aeabi_fcmpgt> 800275a: 4603 mov r3, r0 800275c: 2b00 cmp r3, #0 800275e: d001 beq.n 8002764 8002760: 2302 movs r3, #2 8002762: e021 b.n 80027a8 if((volt<4.8f) && (volt>3.0f)) return GBT_CC_4V; 8002764: 4917 ldr r1, [pc, #92] ; (80027c4 ) 8002766: 6838 ldr r0, [r7, #0] 8002768: f7fe fd00 bl 800116c <__aeabi_fcmplt> 800276c: 4603 mov r3, r0 800276e: 2b00 cmp r3, #0 8002770: d008 beq.n 8002784 8002772: 4915 ldr r1, [pc, #84] ; (80027c8 ) 8002774: 6838 ldr r0, [r7, #0] 8002776: f7fe fd17 bl 80011a8 <__aeabi_fcmpgt> 800277a: 4603 mov r3, r0 800277c: 2b00 cmp r3, #0 800277e: d001 beq.n 8002784 8002780: 2303 movs r3, #3 8002782: e011 b.n 80027a8 if((volt<3.0f) && (volt>1.0f)) return GBT_CC_2V; 8002784: 4910 ldr r1, [pc, #64] ; (80027c8 ) 8002786: 6838 ldr r0, [r7, #0] 8002788: f7fe fcf0 bl 800116c <__aeabi_fcmplt> 800278c: 4603 mov r3, r0 800278e: 2b00 cmp r3, #0 8002790: d009 beq.n 80027a6 8002792: f04f 517e mov.w r1, #1065353216 ; 0x3f800000 8002796: 6838 ldr r0, [r7, #0] 8002798: f7fe fd06 bl 80011a8 <__aeabi_fcmpgt> 800279c: 4603 mov r3, r0 800279e: 2b00 cmp r3, #0 80027a0: d001 beq.n 80027a6 80027a2: 2304 movs r3, #4 80027a4: e000 b.n 80027a8 return GBT_CC_UNKNOWN; 80027a6: 2300 movs r3, #0 } 80027a8: 4618 mov r0, r3 80027aa: 3708 adds r7, #8 80027ac: 46bd mov sp, r7 80027ae: bd80 pop {r7, pc} 80027b0: 20000260 .word 0x20000260 80027b4: 42e2cccd .word 0x42e2cccd 80027b8: 41500000 .word 0x41500000 80027bc: 41300000 .word 0x41300000 80027c0: 40e66666 .word 0x40e66666 80027c4: 4099999a .word 0x4099999a 80027c8: 40400000 .word 0x40400000 080027cc : float CONN_CC_GetAdc(){ 80027cc: b580 push {r7, lr} 80027ce: b082 sub sp, #8 80027d0: af00 add r7, sp, #0 //Vin*k= 1.09v //12vin = 1353 ADC uint32_t adc; float volt; ADC_Select_Channel(ADC_CHANNEL_6); 80027d2: 2006 movs r0, #6 80027d4: f7ff f862 bl 800189c HAL_ADC_Start(&hadc1); 80027d8: 480e ldr r0, [pc, #56] ; (8002814 ) 80027da: f002 fde1 bl 80053a0 HAL_ADC_PollForConversion(&hadc1, 100); 80027de: 2164 movs r1, #100 ; 0x64 80027e0: 480c ldr r0, [pc, #48] ; (8002814 ) 80027e2: f002 feb7 bl 8005554 adc = HAL_ADC_GetValue(&hadc1); 80027e6: 480b ldr r0, [pc, #44] ; (8002814 ) 80027e8: f002 ffba bl 8005760 80027ec: 6078 str r0, [r7, #4] HAL_ADC_Stop(&hadc1); 80027ee: 4809 ldr r0, [pc, #36] ; (8002814 ) 80027f0: f002 fe84 bl 80054fc volt = (float)adc/113.4f; 80027f4: 6878 ldr r0, [r7, #4] 80027f6: f7fe fac3 bl 8000d80 <__aeabi_ui2f> 80027fa: 4603 mov r3, r0 80027fc: 4906 ldr r1, [pc, #24] ; (8002818 ) 80027fe: 4618 mov r0, r3 8002800: f7fe fbca bl 8000f98 <__aeabi_fdiv> 8002804: 4603 mov r3, r0 8002806: 603b str r3, [r7, #0] return volt; 8002808: 683b ldr r3, [r7, #0] } 800280a: 4618 mov r0, r3 800280c: 3708 adds r7, #8 800280e: 46bd mov sp, r7 8002810: bd80 pop {r7, pc} 8002812: bf00 nop 8002814: 20000260 .word 0x20000260 8002818: 42e2cccd .word 0x42e2cccd 0800281c <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 800281c: b480 push {r7} 800281e: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 8002820: f3bf 8f4f dsb sy } 8002824: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 8002826: 4b06 ldr r3, [pc, #24] ; (8002840 <__NVIC_SystemReset+0x24>) 8002828: 68db ldr r3, [r3, #12] 800282a: f403 62e0 and.w r2, r3, #1792 ; 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800282e: 4904 ldr r1, [pc, #16] ; (8002840 <__NVIC_SystemReset+0x24>) 8002830: 4b04 ldr r3, [pc, #16] ; (8002844 <__NVIC_SystemReset+0x28>) 8002832: 4313 orrs r3, r2 8002834: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 8002836: f3bf 8f4f dsb sy } 800283a: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 800283c: bf00 nop 800283e: e7fd b.n 800283c <__NVIC_SystemReset+0x20> 8002840: e000ed00 .word 0xe000ed00 8002844: 05fa0004 .word 0x05fa0004 08002848 <_write>: extern UART_HandleTypeDef huart2; #if defined(__GNUC__) int _write(int fd, char * ptr, int len) { 8002848: b580 push {r7, lr} 800284a: b084 sub sp, #16 800284c: af00 add r7, sp, #0 800284e: 60f8 str r0, [r7, #12] 8002850: 60b9 str r1, [r7, #8] 8002852: 607a str r2, [r7, #4] HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, 1); 8002854: 2201 movs r2, #1 8002856: 2110 movs r1, #16 8002858: 480a ldr r0, [pc, #40] ; (8002884 <_write+0x3c>) 800285a: f004 fc64 bl 8007126 HAL_UART_Transmit(&huart2, (uint8_t *) ptr, len, HAL_MAX_DELAY); 800285e: 687b ldr r3, [r7, #4] 8002860: b29a uxth r2, r3 8002862: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff 8002866: 68b9 ldr r1, [r7, #8] 8002868: 4807 ldr r0, [pc, #28] ; (8002888 <_write+0x40>) 800286a: f005 fda3 bl 80083b4 HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, 0); 800286e: 2200 movs r2, #0 8002870: 2110 movs r1, #16 8002872: 4804 ldr r0, [pc, #16] ; (8002884 <_write+0x3c>) 8002874: f004 fc57 bl 8007126 return len; 8002878: 687b ldr r3, [r7, #4] } 800287a: 4618 mov r0, r3 800287c: 3710 adds r7, #16 800287e: 46bd mov sp, r7 8002880: bd80 pop {r7, pc} 8002882: bf00 nop 8002884: 40011400 .word 0x40011400 8002888: 20003350 .word 0x20003350 0800288c : #endif void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size){ 800288c: b580 push {r7, lr} 800288e: b082 sub sp, #8 8002890: af00 add r7, sp, #0 8002892: 6078 str r0, [r7, #4] 8002894: 460b mov r3, r1 8002896: 807b strh r3, [r7, #2] // if(huart->Instance == USART1){ // mm_rx_interrupt(huart, Size); // } if(huart->Instance == USART2){ 8002898: 687b ldr r3, [r7, #4] 800289a: 681b ldr r3, [r3, #0] 800289c: 4a05 ldr r2, [pc, #20] ; (80028b4 ) 800289e: 4293 cmp r3, r2 80028a0: d104 bne.n 80028ac debug_rx_interrupt(huart, Size); 80028a2: 887b ldrh r3, [r7, #2] 80028a4: 4619 mov r1, r3 80028a6: 6878 ldr r0, [r7, #4] 80028a8: f000 f806 bl 80028b8 } } 80028ac: bf00 nop 80028ae: 3708 adds r7, #8 80028b0: 46bd mov sp, r7 80028b2: bd80 pop {r7, pc} 80028b4: 40004400 .word 0x40004400 080028b8 : void debug_rx_interrupt(UART_HandleTypeDef *huart, uint16_t Size){ 80028b8: b480 push {r7} 80028ba: b083 sub sp, #12 80028bc: af00 add r7, sp, #0 80028be: 6078 str r0, [r7, #4] 80028c0: 460b mov r3, r1 80028c2: 807b strh r3, [r7, #2] debug_rx_buffer[Size] = '\0'; 80028c4: 887b ldrh r3, [r7, #2] 80028c6: 4a07 ldr r2, [pc, #28] ; (80028e4 ) 80028c8: 2100 movs r1, #0 80028ca: 54d1 strb r1, [r2, r3] debug_rx_buffer_size = Size; 80028cc: 887b ldrh r3, [r7, #2] 80028ce: b2da uxtb r2, r3 80028d0: 4b05 ldr r3, [pc, #20] ; (80028e8 ) 80028d2: 701a strb r2, [r3, #0] debug_cmd_received = 1; 80028d4: 4b05 ldr r3, [pc, #20] ; (80028ec ) 80028d6: 2201 movs r2, #1 80028d8: 701a strb r2, [r3, #0] } 80028da: bf00 nop 80028dc: 370c adds r7, #12 80028de: 46bd mov sp, r7 80028e0: bc80 pop {r7} 80028e2: 4770 bx lr 80028e4: 200003a4 .word 0x200003a4 80028e8: 200004a5 .word 0x200004a5 80028ec: 200004a4 .word 0x200004a4 080028f0 : void debug_init(){ 80028f0: b580 push {r7, lr} 80028f2: af00 add r7, sp, #0 HAL_UARTEx_ReceiveToIdle_IT(&huart2,debug_rx_buffer,255); 80028f4: 22ff movs r2, #255 ; 0xff 80028f6: 4903 ldr r1, [pc, #12] ; (8002904 ) 80028f8: 4803 ldr r0, [pc, #12] ; (8002908 ) 80028fa: f005 fded bl 80084d8 // mm_schedule_write(0x02, 0x00FF, 0xFFFF); //for (int i=0;i<60;i++) // mm_schedule_write(0x02, 0x0000, 0xFF00); // mm_schedule_write(0x01, 0x0000, 0x0100); // mm_schedule_write(0x01, 0x0000, 0x0100); } 80028fe: bf00 nop 8002900: bd80 pop {r7, pc} 8002902: bf00 nop 8002904: 200003a4 .word 0x200003a4 8002908: 20003350 .word 0x20003350 0800290c : void parse_command(uint8_t* buffer, size_t length) { 800290c: b5b0 push {r4, r5, r7, lr} 800290e: b086 sub sp, #24 8002910: af00 add r7, sp, #0 8002912: 6078 str r0, [r7, #4] 8002914: 6039 str r1, [r7, #0] // ignore \r \n symbols size_t i = 0; 8002916: 2300 movs r3, #0 8002918: 617b str r3, [r7, #20] for (i = 0; i < length; i++) { 800291a: 2300 movs r3, #0 800291c: 617b str r3, [r7, #20] 800291e: e016 b.n 800294e if (buffer[i] == '\r' || buffer[i] == '\n') { 8002920: 687a ldr r2, [r7, #4] 8002922: 697b ldr r3, [r7, #20] 8002924: 4413 add r3, r2 8002926: 781b ldrb r3, [r3, #0] 8002928: 2b0d cmp r3, #13 800292a: d005 beq.n 8002938 800292c: 687a ldr r2, [r7, #4] 800292e: 697b ldr r3, [r7, #20] 8002930: 4413 add r3, r2 8002932: 781b ldrb r3, [r3, #0] 8002934: 2b0a cmp r3, #10 8002936: d107 bne.n 8002948 buffer[i] = '\0'; 8002938: 687a ldr r2, [r7, #4] 800293a: 697b ldr r3, [r7, #20] 800293c: 4413 add r3, r2 800293e: 2200 movs r2, #0 8002940: 701a strb r2, [r3, #0] length = i; 8002942: 697b ldr r3, [r7, #20] 8002944: 603b str r3, [r7, #0] break; 8002946: e006 b.n 8002956 for (i = 0; i < length; i++) { 8002948: 697b ldr r3, [r7, #20] 800294a: 3301 adds r3, #1 800294c: 617b str r3, [r7, #20] 800294e: 697a ldr r2, [r7, #20] 8002950: 683b ldr r3, [r7, #0] 8002952: 429a cmp r2, r3 8002954: d3e4 bcc.n 8002920 } } if (buffer[0] == 0) return; 8002956: 687b ldr r3, [r7, #4] 8002958: 781b ldrb r3, [r3, #0] 800295a: 2b00 cmp r3, #0 800295c: f000 82d4 beq.w 8002f08 if (strncmp((const char*)buffer, "reset", length) == 0) { 8002960: 683a ldr r2, [r7, #0] 8002962: 49ad ldr r1, [pc, #692] ; (8002c18 ) 8002964: 6878 ldr r0, [r7, #4] 8002966: f007 fa33 bl 8009dd0 800296a: 4603 mov r3, r0 800296c: 2b00 cmp r3, #0 800296e: d104 bne.n 800297a printf("Resetting...\n"); 8002970: 48aa ldr r0, [pc, #680] ; (8002c1c ) 8002972: f007 fa15 bl 8009da0 NVIC_SystemReset(); 8002976: f7ff ff51 bl 800281c <__NVIC_SystemReset> } else if (strncmp((const char*)buffer, "relayaux", length) == 0) { 800297a: 683a ldr r2, [r7, #0] 800297c: 49a8 ldr r1, [pc, #672] ; (8002c20 ) 800297e: 6878 ldr r0, [r7, #4] 8002980: f007 fa26 bl 8009dd0 8002984: 4603 mov r3, r0 8002986: 2b00 cmp r3, #0 8002988: d10e bne.n 80029a8 printf("Relaying...\n"); 800298a: 48a6 ldr r0, [pc, #664] ; (8002c24 ) 800298c: f007 fa08 bl 8009da0 RELAY_Write(RELAY_AUX, 1); 8002990: 2101 movs r1, #1 8002992: 2000 movs r0, #0 8002994: f7fe fe9e bl 80016d4 HAL_Delay(200); 8002998: 20c8 movs r0, #200 ; 0xc8 800299a: f002 fc05 bl 80051a8 RELAY_Write(RELAY_AUX, 0); 800299e: 2100 movs r1, #0 80029a0: 2000 movs r0, #0 80029a2: f7fe fe97 bl 80016d4 80029a6: e2b0 b.n 8002f0a } else if (strncmp((const char*)buffer, "relaycc", length) == 0) { 80029a8: 683a ldr r2, [r7, #0] 80029aa: 499f ldr r1, [pc, #636] ; (8002c28 ) 80029ac: 6878 ldr r0, [r7, #4] 80029ae: f007 fa0f bl 8009dd0 80029b2: 4603 mov r3, r0 80029b4: 2b00 cmp r3, #0 80029b6: d10e bne.n 80029d6 printf("Relaying...\n"); 80029b8: 489a ldr r0, [pc, #616] ; (8002c24 ) 80029ba: f007 f9f1 bl 8009da0 RELAY_Write(RELAY_CC, 1); 80029be: 2101 movs r1, #1 80029c0: 2001 movs r0, #1 80029c2: f7fe fe87 bl 80016d4 HAL_Delay(200); 80029c6: 20c8 movs r0, #200 ; 0xc8 80029c8: f002 fbee bl 80051a8 RELAY_Write(RELAY_CC, 0); 80029cc: 2100 movs r1, #0 80029ce: 2001 movs r0, #1 80029d0: f7fe fe80 bl 80016d4 80029d4: e299 b.n 8002f0a // } else if (strncmp((const char*)buffer, "voltage", length) == 0) { // printf("Voltaging...\n"); // mm_schedule_read(0x02, 0x0001); } else if (strncmp((const char*)buffer, "adc", length) == 0) { 80029d6: 683a ldr r2, [r7, #0] 80029d8: 4994 ldr r1, [pc, #592] ; (8002c2c ) 80029da: 6878 ldr r0, [r7, #4] 80029dc: f007 f9f8 bl 8009dd0 80029e0: 4603 mov r3, r0 80029e2: 2b00 cmp r3, #0 80029e4: d10b bne.n 80029fe printf("CC1=%.2f\n", CONN_CC_GetAdc()); 80029e6: f7ff fef1 bl 80027cc 80029ea: 4603 mov r3, r0 80029ec: 4618 mov r0, r3 80029ee: f7fd fd91 bl 8000514 <__aeabi_f2d> 80029f2: 4602 mov r2, r0 80029f4: 460b mov r3, r1 80029f6: 488e ldr r0, [pc, #568] ; (8002c30 ) 80029f8: f007 f94c bl 8009c94 80029fc: e285 b.n 8002f0a } else if (strncmp((const char*)buffer, "lock_state", length) == 0) { 80029fe: 683a ldr r2, [r7, #0] 8002a00: 498c ldr r1, [pc, #560] ; (8002c34 ) 8002a02: 6878 ldr r0, [r7, #4] 8002a04: f007 f9e4 bl 8009dd0 8002a08: 4603 mov r3, r0 8002a0a: 2b00 cmp r3, #0 8002a0c: d107 bne.n 8002a1e printf("Lock state=%d\n", GBT_LockGetState()); 8002a0e: f001 f911 bl 8003c34 8002a12: 4603 mov r3, r0 8002a14: 4619 mov r1, r3 8002a16: 4888 ldr r0, [pc, #544] ; (8002c38 ) 8002a18: f007 f93c bl 8009c94 8002a1c: e275 b.n 8002f0a } else if (strncmp((const char*)buffer, "lock_lock", length) == 0) { 8002a1e: 683a ldr r2, [r7, #0] 8002a20: 4986 ldr r1, [pc, #536] ; (8002c3c ) 8002a22: 6878 ldr r0, [r7, #4] 8002a24: f007 f9d4 bl 8009dd0 8002a28: 4603 mov r3, r0 8002a2a: 2b00 cmp r3, #0 8002a2c: d106 bne.n 8002a3c printf("Locked\n"); 8002a2e: 4884 ldr r0, [pc, #528] ; (8002c40 ) 8002a30: f007 f9b6 bl 8009da0 GBT_Lock(1); 8002a34: 2001 movs r0, #1 8002a36: f001 f91b bl 8003c70 8002a3a: e266 b.n 8002f0a } else if (strncmp((const char*)buffer, "lock_unlock", length) == 0) { 8002a3c: 683a ldr r2, [r7, #0] 8002a3e: 4981 ldr r1, [pc, #516] ; (8002c44 ) 8002a40: 6878 ldr r0, [r7, #4] 8002a42: f007 f9c5 bl 8009dd0 8002a46: 4603 mov r3, r0 8002a48: 2b00 cmp r3, #0 8002a4a: d106 bne.n 8002a5a printf("Unlocked\n"); 8002a4c: 487e ldr r0, [pc, #504] ; (8002c48 ) 8002a4e: f007 f9a7 bl 8009da0 GBT_Lock(0); 8002a52: 2000 movs r0, #0 8002a54: f001 f90c bl 8003c70 8002a58: e257 b.n 8002f0a } else if (strncmp((const char*)buffer, "complete", length) == 0) { 8002a5a: 683a ldr r2, [r7, #0] 8002a5c: 497b ldr r1, [pc, #492] ; (8002c4c ) 8002a5e: 6878 ldr r0, [r7, #4] 8002a60: f007 f9b6 bl 8009dd0 8002a64: 4603 mov r3, r0 8002a66: 2b00 cmp r3, #0 8002a68: d103 bne.n 8002a72 CONN_SetState(CONN_Occupied_complete); 8002a6a: 2006 movs r0, #6 8002a6c: f7ff fdaa bl 80025c4 8002a70: e24b b.n 8002f0a } else if (strncmp((const char*)buffer, "start", length) == 0) { 8002a72: 683a ldr r2, [r7, #0] 8002a74: 4976 ldr r1, [pc, #472] ; (8002c50 ) 8002a76: 6878 ldr r0, [r7, #4] 8002a78: f007 f9aa bl 8009dd0 8002a7c: 4603 mov r3, r0 8002a7e: 2b00 cmp r3, #0 8002a80: d105 bne.n 8002a8e printf("Started\n"); 8002a82: 4874 ldr r0, [pc, #464] ; (8002c54 ) 8002a84: f007 f98c bl 8009da0 GBT_Start(); 8002a88: f7ff fd0c bl 80024a4 8002a8c: e23d b.n 8002f0a } else if (strncmp((const char*)buffer, "stop", length) == 0) { 8002a8e: 683a ldr r2, [r7, #0] 8002a90: 4971 ldr r1, [pc, #452] ; (8002c58 ) 8002a92: 6878 ldr r0, [r7, #4] 8002a94: f007 f99c bl 8009dd0 8002a98: 4603 mov r3, r0 8002a9a: 2b00 cmp r3, #0 8002a9c: d106 bne.n 8002aac printf("Stopped\n"); 8002a9e: 486f ldr r0, [pc, #444] ; (8002c5c ) 8002aa0: f007 f97e bl 8009da0 GBT_Stop(GBT_CST_SUSPENDS_ARTIFICIALLY); 8002aa4: 486e ldr r0, [pc, #440] ; (8002c60 ) 8002aa6: f7ff fc51 bl 800234c 8002aaa: e22e b.n 8002f0a } else if (strncmp((const char*)buffer, "stop1", length) == 0) { 8002aac: 683a ldr r2, [r7, #0] 8002aae: 496d ldr r1, [pc, #436] ; (8002c64 ) 8002ab0: 6878 ldr r0, [r7, #4] 8002ab2: f007 f98d bl 8009dd0 8002ab6: 4603 mov r3, r0 8002ab8: 2b00 cmp r3, #0 8002aba: d105 bne.n 8002ac8 printf("Stopped\n"); 8002abc: 4867 ldr r0, [pc, #412] ; (8002c5c ) 8002abe: f007 f96f bl 8009da0 GBT_ForceStop(); 8002ac2: f7ff fc69 bl 8002398 8002ac6: e220 b.n 8002f0a // printf("Stopped\n"); // GBT_Lock(1); // GBT_SwitchState(GBT_S2_LOCKED); // GBT_Delay(500); } else if (strncmp((const char*)buffer, "cc_state", length) == 0) { 8002ac8: 683a ldr r2, [r7, #0] 8002aca: 4967 ldr r1, [pc, #412] ; (8002c68 ) 8002acc: 6878 ldr r0, [r7, #4] 8002ace: f007 f97f bl 8009dd0 8002ad2: 4603 mov r3, r0 8002ad4: 2b00 cmp r3, #0 8002ad6: d127 bne.n 8002b28 switch(CONN_CC_GetState()){ 8002ad8: f7ff fdfc bl 80026d4 8002adc: 4603 mov r3, r0 8002ade: 2b04 cmp r3, #4 8002ae0: f200 8213 bhi.w 8002f0a 8002ae4: a201 add r2, pc, #4 ; (adr r2, 8002aec ) 8002ae6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8002aea: bf00 nop 8002aec: 08002b01 .word 0x08002b01 8002af0: 08002b09 .word 0x08002b09 8002af4: 08002b11 .word 0x08002b11 8002af8: 08002b19 .word 0x08002b19 8002afc: 08002b21 .word 0x08002b21 case GBT_CC_UNKNOWN: printf("GBT_CC_UNKNOWN\n"); 8002b00: 485a ldr r0, [pc, #360] ; (8002c6c ) 8002b02: f007 f94d bl 8009da0 break; 8002b06: e200 b.n 8002f0a case GBT_CC_12V: printf("GBT_CC_12V\n"); 8002b08: 4859 ldr r0, [pc, #356] ; (8002c70 ) 8002b0a: f007 f949 bl 8009da0 break; 8002b0e: e1fc b.n 8002f0a case GBT_CC_6V: printf("GBT_CC_6V\n"); 8002b10: 4858 ldr r0, [pc, #352] ; (8002c74 ) 8002b12: f007 f945 bl 8009da0 break; 8002b16: e1f8 b.n 8002f0a case GBT_CC_4V: printf("GBT_CC_4V\n"); 8002b18: 4857 ldr r0, [pc, #348] ; (8002c78 ) 8002b1a: f007 f941 bl 8009da0 break; 8002b1e: e1f4 b.n 8002f0a case GBT_CC_2V: printf("GBT_CC_2V\n"); 8002b20: 4856 ldr r0, [pc, #344] ; (8002c7c ) 8002b22: f007 f93d bl 8009da0 break; 8002b26: e1f0 b.n 8002f0a } } else if (strncmp((const char*)buffer, "temp", length) == 0) { 8002b28: 683a ldr r2, [r7, #0] 8002b2a: 4955 ldr r1, [pc, #340] ; (8002c80 ) 8002b2c: 6878 ldr r0, [r7, #4] 8002b2e: f007 f94f bl 8009dd0 8002b32: 4603 mov r3, r0 8002b34: 2b00 cmp r3, #0 8002b36: d110 bne.n 8002b5a printf("temp1 %d\n",GBT_ReadTemp(0)); 8002b38: 2000 movs r0, #0 8002b3a: f7fe fe6f bl 800181c 8002b3e: 4603 mov r3, r0 8002b40: 4619 mov r1, r3 8002b42: 4850 ldr r0, [pc, #320] ; (8002c84 ) 8002b44: f007 f8a6 bl 8009c94 printf("temp2 %d\n",GBT_ReadTemp(1)); 8002b48: 2001 movs r0, #1 8002b4a: f7fe fe67 bl 800181c 8002b4e: 4603 mov r3, r0 8002b50: 4619 mov r1, r3 8002b52: 484d ldr r0, [pc, #308] ; (8002c88 ) 8002b54: f007 f89e bl 8009c94 8002b58: e1d7 b.n 8002f0a } else if (strncmp((const char*)buffer, "info1", length) == 0) { 8002b5a: 683a ldr r2, [r7, #0] 8002b5c: 494b ldr r1, [pc, #300] ; (8002c8c ) 8002b5e: 6878 ldr r0, [r7, #4] 8002b60: f007 f936 bl 8009dd0 8002b64: 4603 mov r3, r0 8002b66: 2b00 cmp r3, #0 8002b68: f040 80a6 bne.w 8002cb8 printf("Battery info:\n"); 8002b6c: 4848 ldr r0, [pc, #288] ; (8002c90 ) 8002b6e: f007 f917 bl 8009da0 printf("maxCV %dV\n",GBT_BATStat.maxCellVoltage/100); // 0.01v/bit 8002b72: 4b48 ldr r3, [pc, #288] ; (8002c94 ) 8002b74: 881b ldrh r3, [r3, #0] 8002b76: b29b uxth r3, r3 8002b78: 4a47 ldr r2, [pc, #284] ; (8002c98 ) 8002b7a: fba2 2303 umull r2, r3, r2, r3 8002b7e: 095b lsrs r3, r3, #5 8002b80: b29b uxth r3, r3 8002b82: 4619 mov r1, r3 8002b84: 4845 ldr r0, [pc, #276] ; (8002c9c ) 8002b86: f007 f885 bl 8009c94 printf("maxCC %dA\n",GBT_BATStat.maxChargingCurrent/10); // 0.1A/bit 8002b8a: 4b42 ldr r3, [pc, #264] ; (8002c94 ) 8002b8c: 885b ldrh r3, [r3, #2] 8002b8e: b29b uxth r3, r3 8002b90: 4a43 ldr r2, [pc, #268] ; (8002ca0 ) 8002b92: fba2 2303 umull r2, r3, r2, r3 8002b96: 08db lsrs r3, r3, #3 8002b98: b29b uxth r3, r3 8002b9a: 4619 mov r1, r3 8002b9c: 4841 ldr r0, [pc, #260] ; (8002ca4 ) 8002b9e: f007 f879 bl 8009c94 printf("totE %dkWh\n",GBT_BATStat.totalEnergy/10); // 0.1kWh 8002ba2: 4b3c ldr r3, [pc, #240] ; (8002c94 ) 8002ba4: 889b ldrh r3, [r3, #4] 8002ba6: b29b uxth r3, r3 8002ba8: 4a3d ldr r2, [pc, #244] ; (8002ca0 ) 8002baa: fba2 2303 umull r2, r3, r2, r3 8002bae: 08db lsrs r3, r3, #3 8002bb0: b29b uxth r3, r3 8002bb2: 4619 mov r1, r3 8002bb4: 483c ldr r0, [pc, #240] ; (8002ca8 ) 8002bb6: f007 f86d bl 8009c94 printf("maxCV %dV\n",GBT_BATStat.maxChargingVoltage/10); // 0.1V/ bit 8002bba: 4b36 ldr r3, [pc, #216] ; (8002c94 ) 8002bbc: 88db ldrh r3, [r3, #6] 8002bbe: b29b uxth r3, r3 8002bc0: 4a37 ldr r2, [pc, #220] ; (8002ca0 ) 8002bc2: fba2 2303 umull r2, r3, r2, r3 8002bc6: 08db lsrs r3, r3, #3 8002bc8: b29b uxth r3, r3 8002bca: 4619 mov r1, r3 8002bcc: 4833 ldr r0, [pc, #204] ; (8002c9c ) 8002bce: f007 f861 bl 8009c94 printf("maxT %dC\n",(int16_t)GBT_BATStat.maxTemp-50); // 1C/bit, -50C offset 8002bd2: 4b30 ldr r3, [pc, #192] ; (8002c94 ) 8002bd4: 7a1b ldrb r3, [r3, #8] 8002bd6: 3b32 subs r3, #50 ; 0x32 8002bd8: 4619 mov r1, r3 8002bda: 4834 ldr r0, [pc, #208] ; (8002cac ) 8002bdc: f007 f85a bl 8009c94 printf("SOC %dp\n",GBT_BATStat.SOC/10); // 0.1%/bit , 0..100% 8002be0: 4b2c ldr r3, [pc, #176] ; (8002c94 ) 8002be2: f8b3 3009 ldrh.w r3, [r3, #9] 8002be6: b29b uxth r3, r3 8002be8: 4a2d ldr r2, [pc, #180] ; (8002ca0 ) 8002bea: fba2 2303 umull r2, r3, r2, r3 8002bee: 08db lsrs r3, r3, #3 8002bf0: b29b uxth r3, r3 8002bf2: 4619 mov r1, r3 8002bf4: 482e ldr r0, [pc, #184] ; (8002cb0 ) 8002bf6: f007 f84d bl 8009c94 printf("Volt. %dV\n",GBT_BATStat.measVoltage/10); // 0.1V/bit 8002bfa: 4b26 ldr r3, [pc, #152] ; (8002c94 ) 8002bfc: f8b3 300b ldrh.w r3, [r3, #11] 8002c00: b29b uxth r3, r3 8002c02: 4a27 ldr r2, [pc, #156] ; (8002ca0 ) 8002c04: fba2 2303 umull r2, r3, r2, r3 8002c08: 08db lsrs r3, r3, #3 8002c0a: b29b uxth r3, r3 8002c0c: 4619 mov r1, r3 8002c0e: 4829 ldr r0, [pc, #164] ; (8002cb4 ) 8002c10: f007 f840 bl 8009c94 8002c14: e179 b.n 8002f0a 8002c16: bf00 nop 8002c18: 0800cdd0 .word 0x0800cdd0 8002c1c: 0800cdd8 .word 0x0800cdd8 8002c20: 0800cde8 .word 0x0800cde8 8002c24: 0800cdf4 .word 0x0800cdf4 8002c28: 0800ce00 .word 0x0800ce00 8002c2c: 0800ce08 .word 0x0800ce08 8002c30: 0800ce0c .word 0x0800ce0c 8002c34: 0800ce18 .word 0x0800ce18 8002c38: 0800ce24 .word 0x0800ce24 8002c3c: 0800ce34 .word 0x0800ce34 8002c40: 0800ce40 .word 0x0800ce40 8002c44: 0800ce48 .word 0x0800ce48 8002c48: 0800ce54 .word 0x0800ce54 8002c4c: 0800ce60 .word 0x0800ce60 8002c50: 0800ce6c .word 0x0800ce6c 8002c54: 0800ce74 .word 0x0800ce74 8002c58: 0800ce7c .word 0x0800ce7c 8002c5c: 0800ce84 .word 0x0800ce84 8002c60: 0400f0f0 .word 0x0400f0f0 8002c64: 0800ce8c .word 0x0800ce8c 8002c68: 0800ce94 .word 0x0800ce94 8002c6c: 0800cea0 .word 0x0800cea0 8002c70: 0800ceb0 .word 0x0800ceb0 8002c74: 0800cebc .word 0x0800cebc 8002c78: 0800cec8 .word 0x0800cec8 8002c7c: 0800ced4 .word 0x0800ced4 8002c80: 0800cee0 .word 0x0800cee0 8002c84: 0800cee8 .word 0x0800cee8 8002c88: 0800cef4 .word 0x0800cef4 8002c8c: 0800cf00 .word 0x0800cf00 8002c90: 0800cf08 .word 0x0800cf08 8002c94: 20000340 .word 0x20000340 8002c98: 51eb851f .word 0x51eb851f 8002c9c: 0800cf18 .word 0x0800cf18 8002ca0: cccccccd .word 0xcccccccd 8002ca4: 0800cf24 .word 0x0800cf24 8002ca8: 0800cf30 .word 0x0800cf30 8002cac: 0800cf3c .word 0x0800cf3c 8002cb0: 0800cf48 .word 0x0800cf48 8002cb4: 0800cf54 .word 0x0800cf54 } else if (strncmp((const char*)buffer, "info2", length) == 0) { 8002cb8: 683a ldr r2, [r7, #0] 8002cba: 4995 ldr r1, [pc, #596] ; (8002f10 ) 8002cbc: 6878 ldr r0, [r7, #4] 8002cbe: f007 f887 bl 8009dd0 8002cc2: 4603 mov r3, r0 8002cc4: 2b00 cmp r3, #0 8002cc6: d153 bne.n 8002d70 printf("EV info:\n"); 8002cc8: 4892 ldr r0, [pc, #584] ; (8002f14 ) 8002cca: f007 f869 bl 8009da0 printf("GBT_ver V%d.%d%d\n",GBT_EVInfo.version[0],GBT_EVInfo.version[1],GBT_EVInfo.version[2]); 8002cce: 4b92 ldr r3, [pc, #584] ; (8002f18 ) 8002cd0: 781b ldrb r3, [r3, #0] 8002cd2: 4619 mov r1, r3 8002cd4: 4b90 ldr r3, [pc, #576] ; (8002f18 ) 8002cd6: 785b ldrb r3, [r3, #1] 8002cd8: 461a mov r2, r3 8002cda: 4b8f ldr r3, [pc, #572] ; (8002f18 ) 8002cdc: 789b ldrb r3, [r3, #2] 8002cde: 488f ldr r0, [pc, #572] ; (8002f1c ) 8002ce0: f006 ffd8 bl 8009c94 printf("Battery type: %d\n",GBT_EVInfo.batteryType); 8002ce4: 4b8c ldr r3, [pc, #560] ; (8002f18 ) 8002ce6: 78db ldrb r3, [r3, #3] 8002ce8: 4619 mov r1, r3 8002cea: 488d ldr r0, [pc, #564] ; (8002f20 ) 8002cec: f006 ffd2 bl 8009c94 printf("Battery capacity: %d\n", GBT_EVInfo.batteryCapacity); // 0.1Ah/bit 8002cf0: 4b89 ldr r3, [pc, #548] ; (8002f18 ) 8002cf2: 889b ldrh r3, [r3, #4] 8002cf4: b29b uxth r3, r3 8002cf6: 4619 mov r1, r3 8002cf8: 488a ldr r0, [pc, #552] ; (8002f24 ) 8002cfa: f006 ffcb bl 8009c94 printf("Battery voltage: %d\n", GBT_EVInfo.batteryVoltage); // 0.1V/bit 8002cfe: 4b86 ldr r3, [pc, #536] ; (8002f18 ) 8002d00: 88db ldrh r3, [r3, #6] 8002d02: b29b uxth r3, r3 8002d04: 4619 mov r1, r3 8002d06: 4888 ldr r0, [pc, #544] ; (8002f28 ) 8002d08: f006 ffc4 bl 8009c94 printf("Battery vendor: %.4s\n", GBT_EVInfo.batteryVendor); // Battery vendor (ASCII string) 8002d0c: 4987 ldr r1, [pc, #540] ; (8002f2c ) 8002d0e: 4888 ldr r0, [pc, #544] ; (8002f30 ) 8002d10: f006 ffc0 bl 8009c94 printf("Battery SN: %lu\n", GBT_EVInfo.batterySN); // int 8002d14: 4b80 ldr r3, [pc, #512] ; (8002f18 ) 8002d16: 68db ldr r3, [r3, #12] 8002d18: 4619 mov r1, r3 8002d1a: 4886 ldr r0, [pc, #536] ; (8002f34 ) 8002d1c: f006 ffba bl 8009c94 printf("Battery manufacture date: %02d.%02d.%04d\n", GBT_EVInfo.batteryManuD, GBT_EVInfo.batteryManuM ,GBT_EVInfo.batteryManuY+1985); // year (offset 1985) 8002d20: 4b7d ldr r3, [pc, #500] ; (8002f18 ) 8002d22: 7c9b ldrb r3, [r3, #18] 8002d24: 4619 mov r1, r3 8002d26: 4b7c ldr r3, [pc, #496] ; (8002f18 ) 8002d28: 7c5b ldrb r3, [r3, #17] 8002d2a: 461a mov r2, r3 8002d2c: 4b7a ldr r3, [pc, #488] ; (8002f18 ) 8002d2e: 7c1b ldrb r3, [r3, #16] 8002d30: f203 73c1 addw r3, r3, #1985 ; 0x7c1 8002d34: 4880 ldr r0, [pc, #512] ; (8002f38 ) 8002d36: f006 ffad bl 8009c94 printf("Battery cycles: %d\n", GBT_EVInfo.batteryCycleCount); //uint24_t 8002d3a: 4b77 ldr r3, [pc, #476] ; (8002f18 ) 8002d3c: 7cda ldrb r2, [r3, #19] 8002d3e: 7d19 ldrb r1, [r3, #20] 8002d40: 0209 lsls r1, r1, #8 8002d42: 430a orrs r2, r1 8002d44: 7d5b ldrb r3, [r3, #21] 8002d46: 041b lsls r3, r3, #16 8002d48: 4313 orrs r3, r2 8002d4a: 4619 mov r1, r3 8002d4c: 487b ldr r0, [pc, #492] ; (8002f3c ) 8002d4e: f006 ffa1 bl 8009c94 printf("Own auto: %d\n", GBT_EVInfo.ownAuto); // 0 = lizing, 1 = own auto 8002d52: 4b71 ldr r3, [pc, #452] ; (8002f18 ) 8002d54: 7d9b ldrb r3, [r3, #22] 8002d56: 4619 mov r1, r3 8002d58: 4879 ldr r0, [pc, #484] ; (8002f40 ) 8002d5a: f006 ff9b bl 8009c94 printf("EVIN: %.17s\n", GBT_EVInfo.EVIN); //EVIN 8002d5e: 4979 ldr r1, [pc, #484] ; (8002f44 ) 8002d60: 4879 ldr r0, [pc, #484] ; (8002f48 ) 8002d62: f006 ff97 bl 8009c94 printf("EV_SW_VER: %.8s\n", GBT_EVInfo.EV_SW_VER); 8002d66: 4979 ldr r1, [pc, #484] ; (8002f4c ) 8002d68: 4879 ldr r0, [pc, #484] ; (8002f50 ) 8002d6a: f006 ff93 bl 8009c94 8002d6e: e0cc b.n 8002f0a } else if (strncmp((const char*)buffer, "info3", length) == 0) { 8002d70: 683a ldr r2, [r7, #0] 8002d72: 4978 ldr r1, [pc, #480] ; (8002f54 ) 8002d74: 6878 ldr r0, [r7, #4] 8002d76: f007 f82b bl 8009dd0 8002d7a: 4603 mov r3, r0 8002d7c: 2b00 cmp r3, #0 8002d7e: d133 bne.n 8002de8 printf("GBT_MaxLoad info:\n"); 8002d80: 4875 ldr r0, [pc, #468] ; (8002f58 ) 8002d82: f007 f80d bl 8009da0 printf("Output max current: %d\n",GBT_MaxLoad.maxOutputCurrent); 8002d86: 4b75 ldr r3, [pc, #468] ; (8002f5c ) 8002d88: 889b ldrh r3, [r3, #4] 8002d8a: b29b uxth r3, r3 8002d8c: 4619 mov r1, r3 8002d8e: 4874 ldr r0, [pc, #464] ; (8002f60 ) 8002d90: f006 ff80 bl 8009c94 printf("Output min current: %d\n",GBT_MaxLoad.minOutputCurrent); 8002d94: 4b71 ldr r3, [pc, #452] ; (8002f5c ) 8002d96: 88db ldrh r3, [r3, #6] 8002d98: b29b uxth r3, r3 8002d9a: 4619 mov r1, r3 8002d9c: 4871 ldr r0, [pc, #452] ; (8002f64 ) 8002d9e: f006 ff79 bl 8009c94 printf("Output max voltage: %d\n",GBT_MaxLoad.maxOutputVoltage); 8002da2: 4b6e ldr r3, [pc, #440] ; (8002f5c ) 8002da4: 881b ldrh r3, [r3, #0] 8002da6: b29b uxth r3, r3 8002da8: 4619 mov r1, r3 8002daa: 486f ldr r0, [pc, #444] ; (8002f68 ) 8002dac: f006 ff72 bl 8009c94 printf("Output min voltage: %d\n",GBT_MaxLoad.minOutputVoltage); 8002db0: 4b6a ldr r3, [pc, #424] ; (8002f5c ) 8002db2: 885b ldrh r3, [r3, #2] 8002db4: b29b uxth r3, r3 8002db6: 4619 mov r1, r3 8002db8: 486c ldr r0, [pc, #432] ; (8002f6c ) 8002dba: f006 ff6b bl 8009c94 printf("\nGBT_ChargerInfo info:\n"); 8002dbe: 486c ldr r0, [pc, #432] ; (8002f70 ) 8002dc0: f006 ffee bl 8009da0 printf("BMS Recognized: %d\n",GBT_ChargerInfo.bmsIdentified); 8002dc4: 4b6b ldr r3, [pc, #428] ; (8002f74 ) 8002dc6: 781b ldrb r3, [r3, #0] 8002dc8: 4619 mov r1, r3 8002dca: 486b ldr r0, [pc, #428] ; (8002f78 ) 8002dcc: f006 ff62 bl 8009c94 printf("Charger location: %.3s\n",GBT_ChargerInfo.chargerLocation); 8002dd0: 496a ldr r1, [pc, #424] ; (8002f7c ) 8002dd2: 486b ldr r0, [pc, #428] ; (8002f80 ) 8002dd4: f006 ff5e bl 8009c94 printf("Charger number: %lu\n",GBT_ChargerInfo.chargerNumber); 8002dd8: 4b66 ldr r3, [pc, #408] ; (8002f74 ) 8002dda: f8d3 3001 ldr.w r3, [r3, #1] 8002dde: 4619 mov r1, r3 8002de0: 4868 ldr r0, [pc, #416] ; (8002f84 ) 8002de2: f006 ff57 bl 8009c94 8002de6: e090 b.n 8002f0a } else if (strncmp((const char*)buffer, "help", length) == 0) { 8002de8: 683a ldr r2, [r7, #0] 8002dea: 4967 ldr r1, [pc, #412] ; (8002f88 ) 8002dec: 6878 ldr r0, [r7, #4] 8002dee: f006 ffef bl 8009dd0 8002df2: 4603 mov r3, r0 8002df4: 2b00 cmp r3, #0 8002df6: d136 bne.n 8002e66 printf("Command list:\n"); 8002df8: 4864 ldr r0, [pc, #400] ; (8002f8c ) 8002dfa: f006 ffd1 bl 8009da0 printf("reset\n"); 8002dfe: 4864 ldr r0, [pc, #400] ; (8002f90 ) 8002e00: f006 ffce bl 8009da0 printf("help\n"); 8002e04: 4860 ldr r0, [pc, #384] ; (8002f88 ) 8002e06: f006 ffcb bl 8009da0 printf("cc_state\n"); 8002e0a: 4862 ldr r0, [pc, #392] ; (8002f94 ) 8002e0c: f006 ffc8 bl 8009da0 printf("lock_lock\n"); 8002e10: 4861 ldr r0, [pc, #388] ; (8002f98 ) 8002e12: f006 ffc5 bl 8009da0 printf("lock_unlock\n"); 8002e16: 4861 ldr r0, [pc, #388] ; (8002f9c ) 8002e18: f006 ffc2 bl 8009da0 printf("lock_state\n"); 8002e1c: 4860 ldr r0, [pc, #384] ; (8002fa0 ) 8002e1e: f006 ffbf bl 8009da0 printf("adc\n"); 8002e22: 4860 ldr r0, [pc, #384] ; (8002fa4 ) 8002e24: f006 ffbc bl 8009da0 printf("relay(cc,aux)\n"); 8002e28: 485f ldr r0, [pc, #380] ; (8002fa8 ) 8002e2a: f006 ffb9 bl 8009da0 printf("start\n"); 8002e2e: 485f ldr r0, [pc, #380] ; (8002fac ) 8002e30: f006 ffb6 bl 8009da0 printf("stop\n"); 8002e34: 485e ldr r0, [pc, #376] ; (8002fb0 ) 8002e36: f006 ffb3 bl 8009da0 printf("stop1\n"); 8002e3a: 485e ldr r0, [pc, #376] ; (8002fb4 ) 8002e3c: f006 ffb0 bl 8009da0 // printf("force\n"); printf("temp\n"); 8002e40: 485d ldr r0, [pc, #372] ; (8002fb8 ) 8002e42: f006 ffad bl 8009da0 printf("info1\n"); 8002e46: 485d ldr r0, [pc, #372] ; (8002fbc ) 8002e48: f006 ffaa bl 8009da0 printf("info2\n"); 8002e4c: 4830 ldr r0, [pc, #192] ; (8002f10 ) 8002e4e: f006 ffa7 bl 8009da0 printf("info3\n"); 8002e52: 4840 ldr r0, [pc, #256] ; (8002f54 ) 8002e54: f006 ffa4 bl 8009da0 printf("time\n"); 8002e58: 4859 ldr r0, [pc, #356] ; (8002fc0 ) 8002e5a: f006 ffa1 bl 8009da0 printf("cantest\n"); 8002e5e: 4859 ldr r0, [pc, #356] ; (8002fc4 ) 8002e60: f006 ff9e bl 8009da0 8002e64: e051 b.n 8002f0a //TODO: info commands } else if (strncmp((const char*)buffer, "time", length) == 0) { 8002e66: 683a ldr r2, [r7, #0] 8002e68: 4955 ldr r1, [pc, #340] ; (8002fc0 ) 8002e6a: 6878 ldr r0, [r7, #4] 8002e6c: f006 ffb0 bl 8009dd0 8002e70: 4603 mov r3, r0 8002e72: 2b00 cmp r3, #0 8002e74: d135 bne.n 8002ee2 time_t unix_time = (time_t)get_Current_Time(); 8002e76: f001 fdaf bl 80049d8 8002e7a: 4603 mov r3, r0 8002e7c: 17da asrs r2, r3, #31 8002e7e: 461c mov r4, r3 8002e80: 4615 mov r5, r2 8002e82: e9c7 4502 strd r4, r5, [r7, #8] struct tm *parts = localtime(&unix_time); 8002e86: f107 0308 add.w r3, r7, #8 8002e8a: 4618 mov r0, r3 8002e8c: f006 f890 bl 8008fb0 8002e90: 6138 str r0, [r7, #16] printf("Year: %d\n", parts->tm_year + 1900); 8002e92: 693b ldr r3, [r7, #16] 8002e94: 695b ldr r3, [r3, #20] 8002e96: f203 736c addw r3, r3, #1900 ; 0x76c 8002e9a: 4619 mov r1, r3 8002e9c: 484a ldr r0, [pc, #296] ; (8002fc8 ) 8002e9e: f006 fef9 bl 8009c94 printf("Month: %d\n", parts->tm_mon + 1); 8002ea2: 693b ldr r3, [r7, #16] 8002ea4: 691b ldr r3, [r3, #16] 8002ea6: 3301 adds r3, #1 8002ea8: 4619 mov r1, r3 8002eaa: 4848 ldr r0, [pc, #288] ; (8002fcc ) 8002eac: f006 fef2 bl 8009c94 printf("Day: %d\n", parts->tm_mday); 8002eb0: 693b ldr r3, [r7, #16] 8002eb2: 68db ldr r3, [r3, #12] 8002eb4: 4619 mov r1, r3 8002eb6: 4846 ldr r0, [pc, #280] ; (8002fd0 ) 8002eb8: f006 feec bl 8009c94 printf("Hour: %d\n", parts->tm_hour); 8002ebc: 693b ldr r3, [r7, #16] 8002ebe: 689b ldr r3, [r3, #8] 8002ec0: 4619 mov r1, r3 8002ec2: 4844 ldr r0, [pc, #272] ; (8002fd4 ) 8002ec4: f006 fee6 bl 8009c94 printf("Minute: %d\n", parts->tm_min); 8002ec8: 693b ldr r3, [r7, #16] 8002eca: 685b ldr r3, [r3, #4] 8002ecc: 4619 mov r1, r3 8002ece: 4842 ldr r0, [pc, #264] ; (8002fd8 ) 8002ed0: f006 fee0 bl 8009c94 printf("Second: %d\n", parts->tm_sec); 8002ed4: 693b ldr r3, [r7, #16] 8002ed6: 681b ldr r3, [r3, #0] 8002ed8: 4619 mov r1, r3 8002eda: 4840 ldr r0, [pc, #256] ; (8002fdc ) 8002edc: f006 feda bl 8009c94 8002ee0: e013 b.n 8002f0a } else if (strncmp((const char*)buffer, "cantest", length) == 0) { 8002ee2: 683a ldr r2, [r7, #0] 8002ee4: 4937 ldr r1, [pc, #220] ; (8002fc4 ) 8002ee6: 6878 ldr r0, [r7, #4] 8002ee8: f006 ff72 bl 8009dd0 8002eec: 4603 mov r3, r0 8002eee: 2b00 cmp r3, #0 8002ef0: d106 bne.n 8002f00 //GBT_SendCHM(); GBT_Error(0xFDF0C0FC); //BRM Timeout 8002ef2: 483b ldr r0, [pc, #236] ; (8002fe0 ) 8002ef4: f7ff fa40 bl 8002378 printf("can test\n"); 8002ef8: 483a ldr r0, [pc, #232] ; (8002fe4 ) 8002efa: f006 ff51 bl 8009da0 8002efe: e004 b.n 8002f0a } else { printf("Unknown command\n"); 8002f00: 4839 ldr r0, [pc, #228] ; (8002fe8 ) 8002f02: f006 ff4d bl 8009da0 8002f06: e000 b.n 8002f0a if (buffer[0] == 0) return; 8002f08: bf00 nop } } 8002f0a: 3718 adds r7, #24 8002f0c: 46bd mov sp, r7 8002f0e: bdb0 pop {r4, r5, r7, pc} 8002f10: 0800cf60 .word 0x0800cf60 8002f14: 0800cf68 .word 0x0800cf68 8002f18: 2000030c .word 0x2000030c 8002f1c: 0800cf74 .word 0x0800cf74 8002f20: 0800cf88 .word 0x0800cf88 8002f24: 0800cf9c .word 0x0800cf9c 8002f28: 0800cfb4 .word 0x0800cfb4 8002f2c: 20000314 .word 0x20000314 8002f30: 0800cfcc .word 0x0800cfcc 8002f34: 0800cfe4 .word 0x0800cfe4 8002f38: 0800cff8 .word 0x0800cff8 8002f3c: 0800d024 .word 0x0800d024 8002f40: 0800d038 .word 0x0800d038 8002f44: 20000324 .word 0x20000324 8002f48: 0800d048 .word 0x0800d048 8002f4c: 20000335 .word 0x20000335 8002f50: 0800d058 .word 0x0800d058 8002f54: 0800d06c .word 0x0800d06c 8002f58: 0800d074 .word 0x0800d074 8002f5c: 200002f8 .word 0x200002f8 8002f60: 0800d088 .word 0x0800d088 8002f64: 0800d0a0 .word 0x0800d0a0 8002f68: 0800d0b8 .word 0x0800d0b8 8002f6c: 0800d0d0 .word 0x0800d0d0 8002f70: 0800d0e8 .word 0x0800d0e8 8002f74: 20000300 .word 0x20000300 8002f78: 0800d100 .word 0x0800d100 8002f7c: 20000305 .word 0x20000305 8002f80: 0800d114 .word 0x0800d114 8002f84: 0800d12c .word 0x0800d12c 8002f88: 0800d144 .word 0x0800d144 8002f8c: 0800d14c .word 0x0800d14c 8002f90: 0800cdd0 .word 0x0800cdd0 8002f94: 0800ce94 .word 0x0800ce94 8002f98: 0800ce34 .word 0x0800ce34 8002f9c: 0800ce48 .word 0x0800ce48 8002fa0: 0800ce18 .word 0x0800ce18 8002fa4: 0800ce08 .word 0x0800ce08 8002fa8: 0800d15c .word 0x0800d15c 8002fac: 0800ce6c .word 0x0800ce6c 8002fb0: 0800ce7c .word 0x0800ce7c 8002fb4: 0800ce8c .word 0x0800ce8c 8002fb8: 0800cee0 .word 0x0800cee0 8002fbc: 0800cf00 .word 0x0800cf00 8002fc0: 0800d16c .word 0x0800d16c 8002fc4: 0800d174 .word 0x0800d174 8002fc8: 0800d17c .word 0x0800d17c 8002fcc: 0800d188 .word 0x0800d188 8002fd0: 0800d194 .word 0x0800d194 8002fd4: 0800d1a0 .word 0x0800d1a0 8002fd8: 0800d1ac .word 0x0800d1ac 8002fdc: 0800d1b8 .word 0x0800d1b8 8002fe0: fdf0c0fc .word 0xfdf0c0fc 8002fe4: 0800d1c4 .word 0x0800d1c4 8002fe8: 0800d1d0 .word 0x0800d1d0 08002fec : void debug_task(){ 8002fec: b580 push {r7, lr} 8002fee: af00 add r7, sp, #0 if(debug_cmd_received){ 8002ff0: 4b09 ldr r3, [pc, #36] ; (8003018 ) 8002ff2: 781b ldrb r3, [r3, #0] 8002ff4: 2b00 cmp r3, #0 8002ff6: d00d beq.n 8003014 parse_command(debug_rx_buffer, debug_rx_buffer_size); 8002ff8: 4b08 ldr r3, [pc, #32] ; (800301c ) 8002ffa: 781b ldrb r3, [r3, #0] 8002ffc: 4619 mov r1, r3 8002ffe: 4808 ldr r0, [pc, #32] ; (8003020 ) 8003000: f7ff fc84 bl 800290c HAL_UARTEx_ReceiveToIdle_IT(&huart2,debug_rx_buffer,255); 8003004: 22ff movs r2, #255 ; 0xff 8003006: 4906 ldr r1, [pc, #24] ; (8003020 ) 8003008: 4806 ldr r0, [pc, #24] ; (8003024 ) 800300a: f005 fa65 bl 80084d8 debug_cmd_received = 0; 800300e: 4b02 ldr r3, [pc, #8] ; (8003018 ) 8003010: 2200 movs r2, #0 8003012: 701a strb r2, [r3, #0] } } 8003014: bf00 nop 8003016: bd80 pop {r7, pc} 8003018: 200004a4 .word 0x200004a4 800301c: 200004a5 .word 0x200004a5 8003020: 200003a4 .word 0x200003a4 8003024: 20003350 .word 0x20003350 08003028 : * DestinationID: Packet Destination ID * Addr: First register address in sequence * *data: pointer for data array * len: length of data (1..255) */ void EDCAN_ReadHandler(uint8_t SourceID, uint8_t DestinationID, uint16_t Addr, uint8_t *data, uint8_t len){ 8003028: b480 push {r7} 800302a: b085 sub sp, #20 800302c: af00 add r7, sp, #0 800302e: 603b str r3, [r7, #0] 8003030: 4603 mov r3, r0 8003032: 71fb strb r3, [r7, #7] 8003034: 460b mov r3, r1 8003036: 71bb strb r3, [r7, #6] 8003038: 4613 mov r3, r2 800303a: 80bb strh r3, [r7, #4] // printf("Destination ID = %d\n", DestinationID); // printf("Address = %d\n", Addr); // printf("Len = %d\n", len); // printf("\n"); for (uint16_t AddrOffset = 0; AddrOffset < len; AddrOffset++){ //по очереди перебираем все полученные регистры через Handler 800303c: 2300 movs r3, #0 800303e: 81fb strh r3, [r7, #14] 8003040: e002 b.n 8003048 8003042: 89fb ldrh r3, [r7, #14] 8003044: 3301 adds r3, #1 8003046: 81fb strh r3, [r7, #14] 8003048: 7e3b ldrb r3, [r7, #24] 800304a: b29b uxth r3, r3 800304c: 89fa ldrh r2, [r7, #14] 800304e: 429a cmp r2, r3 8003050: d3f7 bcc.n 8003042 // } // } } // printf("\n"); } 8003052: bf00 nop 8003054: bf00 nop 8003056: 3714 adds r7, #20 8003058: 46bd mov sp, r7 800305a: bc80 pop {r7} 800305c: 4770 bx lr ... 08003060 : * DestinationID: Packet Destination ID * Addr: First register address in sequence * *data: pointer for data array * len: length of data (1..255) */ void EDCAN_WriteUserRegister(uint16_t addr, uint8_t value){ 8003060: b580 push {r7, lr} 8003062: b082 sub sp, #8 8003064: af00 add r7, sp, #0 8003066: 4603 mov r3, r0 8003068: 460a mov r2, r1 800306a: 80fb strh r3, [r7, #6] 800306c: 4613 mov r3, r2 800306e: 717b strb r3, [r7, #5] switch(addr){ 8003070: 88fb ldrh r3, [r7, #6] 8003072: f5b3 7f0a cmp.w r3, #552 ; 0x228 8003076: dc5d bgt.n 8003134 8003078: f5b3 7f00 cmp.w r3, #512 ; 0x200 800307c: f2c0 808f blt.w 800319e 8003080: f5a3 7300 sub.w r3, r3, #512 ; 0x200 8003084: 2b28 cmp r3, #40 ; 0x28 8003086: f200 808a bhi.w 800319e 800308a: a201 add r2, pc, #4 ; (adr r2, 8003090 ) 800308c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003090: 0800317f .word 0x0800317f 8003094: 0800317f .word 0x0800317f 8003098: 0800317f .word 0x0800317f 800309c: 0800317f .word 0x0800317f 80030a0: 0800317f .word 0x0800317f 80030a4: 0800317f .word 0x0800317f 80030a8: 0800317f .word 0x0800317f 80030ac: 0800317f .word 0x0800317f 80030b0: 0800317f .word 0x0800317f 80030b4: 0800319f .word 0x0800319f 80030b8: 0800319f .word 0x0800319f 80030bc: 0800319f .word 0x0800319f 80030c0: 0800319f .word 0x0800319f 80030c4: 0800319f .word 0x0800319f 80030c8: 0800319f .word 0x0800319f 80030cc: 0800319f .word 0x0800319f 80030d0: 0800313f .word 0x0800313f 80030d4: 0800314b .word 0x0800314b 80030d8: 08003157 .word 0x08003157 80030dc: 08003163 .word 0x08003163 80030e0: 0800319f .word 0x0800319f 80030e4: 0800319f .word 0x0800319f 80030e8: 0800319f .word 0x0800319f 80030ec: 0800319f .word 0x0800319f 80030f0: 0800319f .word 0x0800319f 80030f4: 0800319f .word 0x0800319f 80030f8: 0800319f .word 0x0800319f 80030fc: 0800319f .word 0x0800319f 8003100: 0800319f .word 0x0800319f 8003104: 0800319f .word 0x0800319f 8003108: 0800319f .word 0x0800319f 800310c: 0800319f .word 0x0800319f 8003110: 0800316f .word 0x0800316f 8003114: 0800316f .word 0x0800316f 8003118: 0800316f .word 0x0800316f 800311c: 0800316f .word 0x0800316f 8003120: 0800316f .word 0x0800316f 8003124: 0800316f .word 0x0800316f 8003128: 0800316f .word 0x0800316f 800312c: 0800316f .word 0x0800316f 8003130: 0800316f .word 0x0800316f 8003134: f5a3 63b0 sub.w r3, r3, #1408 ; 0x580 8003138: 2b06 cmp r3, #6 800313a: d830 bhi.n 800319e 800313c: e027 b.n 800318e // if(value)GBT_Charger_Enable = 1; // else GBT_Charger_Enable = 0; // break; case EDCAN_REG_TIME_0: writeTimeReg(0, value); 800313e: 797b ldrb r3, [r7, #5] 8003140: 4619 mov r1, r3 8003142: 2000 movs r0, #0 8003144: f001 fcf0 bl 8004b28 break; 8003148: e02d b.n 80031a6 case EDCAN_REG_TIME_1: writeTimeReg(1, value); 800314a: 797b ldrb r3, [r7, #5] 800314c: 4619 mov r1, r3 800314e: 2001 movs r0, #1 8003150: f001 fcea bl 8004b28 break; 8003154: e027 b.n 80031a6 case EDCAN_REG_TIME_2: writeTimeReg(2, value); 8003156: 797b ldrb r3, [r7, #5] 8003158: 4619 mov r1, r3 800315a: 2002 movs r0, #2 800315c: f001 fce4 bl 8004b28 break; 8003160: e021 b.n 80031a6 case EDCAN_REG_TIME_3: writeTimeReg(3, value); 8003162: 797b ldrb r3, [r7, #5] 8003164: 4619 mov r1, r3 8003166: 2003 movs r0, #3 8003168: f001 fcde bl 8004b28 break; 800316c: e01b b.n 80031a6 //0x220 case EDCAN_REG_MAX_LOAD ... (EDCAN_REG_MAX_LOAD+sizeof(GBT_CML_t)): ((uint8_t*)&GBT_MaxLoad)[addr - EDCAN_REG_MAX_LOAD] = value; 800316e: 88fb ldrh r3, [r7, #6] 8003170: f5a3 7308 sub.w r3, r3, #544 ; 0x220 8003174: 4a0e ldr r2, [pc, #56] ; (80031b0 ) 8003176: 4413 add r3, r2 8003178: 797a ldrb r2, [r7, #5] 800317a: 701a strb r2, [r3, #0] break; 800317c: e013 b.n 80031a6 //0x200 case EDCAN_REG_CHARGER_INFO ... (EDCAN_REG_CHARGER_INFO+sizeof(GBT_CRM_t)): ((uint8_t*)&GBT_ChargerInfo)[addr - EDCAN_REG_CHARGER_INFO] = value; 800317e: 88fb ldrh r3, [r7, #6] 8003180: f5a3 7300 sub.w r3, r3, #512 ; 0x200 8003184: 4a0b ldr r2, [pc, #44] ; (80031b4 ) 8003186: 4413 add r3, r2 8003188: 797a ldrb r2, [r7, #5] 800318a: 701a strb r2, [r3, #0] break; 800318c: e00b b.n 80031a6 //0x580 case EDCAN_REG_INPUT ... (EDCAN_REG_INPUT+sizeof(GBT_EDCAN_Input_t)): ((uint8_t*)&GBT_EDCAN_Input)[addr - EDCAN_REG_INPUT] = value; 800318e: 88fb ldrh r3, [r7, #6] 8003190: f5a3 63b0 sub.w r3, r3, #1408 ; 0x580 8003194: 4a08 ldr r2, [pc, #32] ; (80031b8 ) 8003196: 4413 add r3, r2 8003198: 797a ldrb r2, [r7, #5] 800319a: 701a strb r2, [r3, #0] //TODO //GBT_EDCAN_Input.measuredCurrent; break; 800319c: e003 b.n 80031a6 default: printf ("Unknown register\n"); 800319e: 4807 ldr r0, [pc, #28] ; (80031bc ) 80031a0: f006 fdfe bl 8009da0 } } 80031a4: bf00 nop 80031a6: bf00 nop 80031a8: 3708 adds r7, #8 80031aa: 46bd mov sp, r7 80031ac: bd80 pop {r7, pc} 80031ae: bf00 nop 80031b0: 200002f8 .word 0x200002f8 80031b4: 20000300 .word 0x20000300 80031b8: 200004b8 .word 0x200004b8 80031bc: 0800d1e0 .word 0x0800d1e0 080031c0 : uint8_t EDCAN_GetUserRegisterValue(uint16_t addr){ 80031c0: b580 push {r7, lr} 80031c2: b082 sub sp, #8 80031c4: af00 add r7, sp, #0 80031c6: 4603 mov r3, r0 80031c8: 80fb strh r3, [r7, #6] switch (addr){ 80031ca: 88fb ldrh r3, [r7, #6] 80031cc: f240 5286 movw r2, #1414 ; 0x586 80031d0: 4293 cmp r3, r2 80031d2: f300 8123 bgt.w 800341c 80031d6: f5b3 6fb0 cmp.w r3, #1408 ; 0x580 80031da: f280 8118 bge.w 800340e 80031de: f240 520d movw r2, #1293 ; 0x50d 80031e2: 4293 cmp r3, r2 80031e4: f300 811a bgt.w 800341c 80031e8: f5b3 6fa0 cmp.w r3, #1280 ; 0x500 80031ec: f280 8108 bge.w 8003400 80031f0: f5b3 7f62 cmp.w r3, #904 ; 0x388 80031f4: f280 8112 bge.w 800341c 80031f8: f5b3 7f54 cmp.w r3, #848 ; 0x350 80031fc: da07 bge.n 800320e 80031fe: f5b3 7f0a cmp.w r3, #552 ; 0x228 8003202: f300 80b7 bgt.w 8003374 8003206: f5b3 7f04 cmp.w r3, #528 ; 0x210 800320a: da79 bge.n 8003300 800320c: e106 b.n 800341c 800320e: f5a3 7354 sub.w r3, r3, #848 ; 0x350 8003212: 2b37 cmp r3, #55 ; 0x37 8003214: f200 8102 bhi.w 800341c 8003218: a201 add r2, pc, #4 ; (adr r2, 8003220 ) 800321a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800321e: bf00 nop 8003220: 080033c3 .word 0x080033c3 8003224: 080033c3 .word 0x080033c3 8003228: 080033c3 .word 0x080033c3 800322c: 080033c3 .word 0x080033c3 8003230: 080033c3 .word 0x080033c3 8003234: 080033c3 .word 0x080033c3 8003238: 080033c3 .word 0x080033c3 800323c: 080033c3 .word 0x080033c3 8003240: 080033c3 .word 0x080033c3 8003244: 080033c3 .word 0x080033c3 8003248: 080033c3 .word 0x080033c3 800324c: 080033c3 .word 0x080033c3 8003250: 080033c3 .word 0x080033c3 8003254: 080033c3 .word 0x080033c3 8003258: 0800341d .word 0x0800341d 800325c: 080033d1 .word 0x080033d1 8003260: 080033d7 .word 0x080033d7 8003264: 080033d7 .word 0x080033d7 8003268: 080033d7 .word 0x080033d7 800326c: 080033d7 .word 0x080033d7 8003270: 080033d7 .word 0x080033d7 8003274: 080033d7 .word 0x080033d7 8003278: 0800341d .word 0x0800341d 800327c: 0800341d .word 0x0800341d 8003280: 0800341d .word 0x0800341d 8003284: 0800341d .word 0x0800341d 8003288: 0800341d .word 0x0800341d 800328c: 0800341d .word 0x0800341d 8003290: 0800341d .word 0x0800341d 8003294: 0800341d .word 0x0800341d 8003298: 0800341d .word 0x0800341d 800329c: 0800341d .word 0x0800341d 80032a0: 080033e5 .word 0x080033e5 80032a4: 080033e5 .word 0x080033e5 80032a8: 080033e5 .word 0x080033e5 80032ac: 080033e5 .word 0x080033e5 80032b0: 080033e5 .word 0x080033e5 80032b4: 080033e5 .word 0x080033e5 80032b8: 080033e5 .word 0x080033e5 80032bc: 080033e5 .word 0x080033e5 80032c0: 080033e5 .word 0x080033e5 80032c4: 080033e5 .word 0x080033e5 80032c8: 0800341d .word 0x0800341d 80032cc: 0800341d .word 0x0800341d 80032d0: 0800341d .word 0x0800341d 80032d4: 0800341d .word 0x0800341d 80032d8: 0800341d .word 0x0800341d 80032dc: 0800341d .word 0x0800341d 80032e0: 080033f3 .word 0x080033f3 80032e4: 080033f3 .word 0x080033f3 80032e8: 080033f3 .word 0x080033f3 80032ec: 080033f3 .word 0x080033f3 80032f0: 080033f3 .word 0x080033f3 80032f4: 080033f3 .word 0x080033f3 80032f8: 080033f3 .word 0x080033f3 80032fc: 080033f3 .word 0x080033f3 8003300: f5a3 7304 sub.w r3, r3, #528 ; 0x210 8003304: 2b18 cmp r3, #24 8003306: f200 8089 bhi.w 800341c 800330a: a201 add r2, pc, #4 ; (adr r2, 8003310 ) 800330c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003310: 0800337f .word 0x0800337f 8003314: 08003389 .word 0x08003389 8003318: 08003393 .word 0x08003393 800331c: 0800339d .word 0x0800339d 8003320: 0800341d .word 0x0800341d 8003324: 0800341d .word 0x0800341d 8003328: 0800341d .word 0x0800341d 800332c: 0800341d .word 0x0800341d 8003330: 0800341d .word 0x0800341d 8003334: 0800341d .word 0x0800341d 8003338: 0800341d .word 0x0800341d 800333c: 0800341d .word 0x0800341d 8003340: 0800341d .word 0x0800341d 8003344: 0800341d .word 0x0800341d 8003348: 0800341d .word 0x0800341d 800334c: 0800341d .word 0x0800341d 8003350: 080033a7 .word 0x080033a7 8003354: 080033a7 .word 0x080033a7 8003358: 080033a7 .word 0x080033a7 800335c: 080033a7 .word 0x080033a7 8003360: 080033a7 .word 0x080033a7 8003364: 080033a7 .word 0x080033a7 8003368: 080033a7 .word 0x080033a7 800336c: 080033a7 .word 0x080033a7 8003370: 080033a7 .word 0x080033a7 8003374: f5a3 7344 sub.w r3, r3, #784 ; 0x310 8003378: 2b30 cmp r3, #48 ; 0x30 800337a: d84f bhi.n 800341c 800337c: e01a b.n 80033b4 // /* регистры 256..2047 используются пользовательских нужд */ // 0x400 case EDCAN_REG_TIME_0: return getTimeReg(0); 800337e: 2000 movs r0, #0 8003380: f001 fbfa bl 8004b78 8003384: 4603 mov r3, r0 8003386: e04a b.n 800341e break; case EDCAN_REG_TIME_1: return getTimeReg(1); 8003388: 2001 movs r0, #1 800338a: f001 fbf5 bl 8004b78 800338e: 4603 mov r3, r0 8003390: e045 b.n 800341e break; case EDCAN_REG_TIME_2: return getTimeReg(2); 8003392: 2002 movs r0, #2 8003394: f001 fbf0 bl 8004b78 8003398: 4603 mov r3, r0 800339a: e040 b.n 800341e break; case EDCAN_REG_TIME_3: return getTimeReg(3); 800339c: 2003 movs r0, #3 800339e: f001 fbeb bl 8004b78 80033a2: 4603 mov r3, r0 80033a4: e03b b.n 800341e break; //0x220 case EDCAN_REG_MAX_LOAD ... (EDCAN_REG_MAX_LOAD+sizeof(GBT_CML_t)): return ((uint8_t*)&GBT_MaxLoad)[addr - EDCAN_REG_MAX_LOAD]; 80033a6: 88fb ldrh r3, [r7, #6] 80033a8: f5a3 7308 sub.w r3, r3, #544 ; 0x220 80033ac: 4a1e ldr r2, [pc, #120] ; (8003428 ) 80033ae: 4413 add r3, r2 80033b0: 781b ldrb r3, [r3, #0] 80033b2: e034 b.n 800341e //0x310 case EDCAN_REG_BRM ... (EDCAN_REG_BRM+sizeof(GBT_BRM_t)-1): return ((uint8_t*)&GBT_EVInfo)[addr - EDCAN_REG_BRM]; 80033b4: 88fb ldrh r3, [r7, #6] 80033b6: f5a3 7344 sub.w r3, r3, #784 ; 0x310 80033ba: 4a1c ldr r2, [pc, #112] ; (800342c ) 80033bc: 4413 add r3, r2 80033be: 781b ldrb r3, [r3, #0] 80033c0: e02d b.n 800341e //0x340 case EDCAN_REG_BCP ... (EDCAN_REG_BCP+sizeof(GBT_BCP_t)): return ((uint8_t*)&GBT_BATStat)[addr - EDCAN_REG_BCP]; 80033c2: 88fb ldrh r3, [r7, #6] 80033c4: f5a3 7354 sub.w r3, r3, #848 ; 0x350 80033c8: 4a19 ldr r2, [pc, #100] ; (8003430 ) 80033ca: 4413 add r3, r2 80033cc: 781b ldrb r3, [r3, #0] 80033ce: e026 b.n 800341e //0x34F case EDCAN_REG_BRO: return GBT_BRO; 80033d0: 4b18 ldr r3, [pc, #96] ; (8003434 ) 80033d2: 781b ldrb r3, [r3, #0] 80033d4: e023 b.n 800341e //0x350 case EDCAN_REG_BCL ... (EDCAN_REG_BCL+sizeof(GBT_BCL_t)): return ((uint8_t*)&GBT_ReqPower)[addr - EDCAN_REG_BCL]; 80033d6: 88fb ldrh r3, [r7, #6] 80033d8: f5a3 7358 sub.w r3, r3, #864 ; 0x360 80033dc: 4a16 ldr r2, [pc, #88] ; (8003438 ) 80033de: 4413 add r3, r2 80033e0: 781b ldrb r3, [r3, #0] 80033e2: e01c b.n 800341e //0x360 case EDCAN_REG_BCS ... (EDCAN_REG_BCS+sizeof(GBT_BCS_t)): return ((uint8_t*)&GBT_ChargingStatus)[addr - EDCAN_REG_BCS]; 80033e4: 88fb ldrh r3, [r7, #6] 80033e6: f5a3 735c sub.w r3, r3, #880 ; 0x370 80033ea: 4a14 ldr r2, [pc, #80] ; (800343c ) 80033ec: 4413 add r3, r2 80033ee: 781b ldrb r3, [r3, #0] 80033f0: e015 b.n 800341e //0x370 case EDCAN_REG_BSM ... (EDCAN_REG_BSM+sizeof(GBT_BSM_t)): return ((uint8_t*)&GBT_BatteryStatus)[addr - EDCAN_REG_BSM]; 80033f2: 88fb ldrh r3, [r7, #6] 80033f4: f5a3 7360 sub.w r3, r3, #896 ; 0x380 80033f8: 4a11 ldr r2, [pc, #68] ; (8003440 ) 80033fa: 4413 add r3, r2 80033fc: 781b ldrb r3, [r3, #0] 80033fe: e00e b.n 800341e //0x500 case EDCAN_REG_OUTPUT ... (EDCAN_REG_OUTPUT+sizeof(GBT_EDCAN_Output_t)): return ((uint8_t*)&GBT_EDCAN_Output)[addr - EDCAN_REG_OUTPUT]; 8003400: 88fb ldrh r3, [r7, #6] 8003402: f5a3 63a0 sub.w r3, r3, #1280 ; 0x500 8003406: 4a0f ldr r2, [pc, #60] ; (8003444 ) 8003408: 4413 add r3, r2 800340a: 781b ldrb r3, [r3, #0] 800340c: e007 b.n 800341e //0x580 case EDCAN_REG_INPUT ... (EDCAN_REG_INPUT+sizeof(GBT_EDCAN_Input_t)): return ((uint8_t*)&GBT_EDCAN_Input)[addr - EDCAN_REG_INPUT]; 800340e: 88fb ldrh r3, [r7, #6] 8003410: f5a3 63b0 sub.w r3, r3, #1408 ; 0x580 8003414: 4a0c ldr r2, [pc, #48] ; (8003448 ) 8003416: 4413 add r3, r2 8003418: 781b ldrb r3, [r3, #0] 800341a: e000 b.n 800341e default: return 0x00; 800341c: 2300 movs r3, #0 } } 800341e: 4618 mov r0, r3 8003420: 3708 adds r7, #8 8003422: 46bd mov sp, r7 8003424: bd80 pop {r7, pc} 8003426: bf00 nop 8003428: 200002f8 .word 0x200002f8 800342c: 2000030c .word 0x2000030c 8003430: 20000340 .word 0x20000340 8003434: 20000384 .word 0x20000384 8003438: 20000350 .word 0x20000350 800343c: 20000360 .word 0x20000360 8003440: 2000036c .word 0x2000036c 8003444: 200004a8 .word 0x200004a8 8003448: 200004b8 .word 0x200004b8 0800344c : // GB/T Time Synchronization Packet #include "main.h" #include "soft_rtc.h" #include "charger_gbt.h" void GBT_SendCTS(){ 800344c: b580 push {r7, lr} 800344e: b082 sub sp, #8 8003450: af00 add r7, sp, #0 uint8_t data[7]; unix_to_bcd(get_Current_Time(), data); 8003452: f001 fac1 bl 80049d8 8003456: 4602 mov r2, r0 8003458: 463b mov r3, r7 800345a: 4619 mov r1, r3 800345c: 4610 mov r0, r2 800345e: f001 faf7 bl 8004a50 // data[3] = 0x05; //days // data[4] = 0x05; //month // data[5] = 0x24; //years // data[6] = 0x20; //centuries J_SendPacket(0x000700, 6, 7, data); 8003462: 463b mov r3, r7 8003464: 2207 movs r2, #7 8003466: 2106 movs r1, #6 8003468: f44f 60e0 mov.w r0, #1792 ; 0x700 800346c: f000 fabc bl 80039e8 } 8003470: bf00 nop 8003472: 3708 adds r7, #8 8003474: 46bd mov sp, r7 8003476: bd80 pop {r7, pc} 08003478 : //GB/T Max Load Packet void GBT_SendCML(){ 8003478: b580 push {r7, lr} 800347a: af00 add r7, sp, #0 // data[4] = 0xC4; //-150A maximum output current // data[5] = 0x09; // // data[6] = 0x8C; //-2A minimum output current // data[7] = 0x0F; // J_SendPacket(0x000800, 6, 8, (uint8_t*)&GBT_MaxLoad); 800347c: 4b04 ldr r3, [pc, #16] ; (8003490 ) 800347e: 2208 movs r2, #8 8003480: 2106 movs r1, #6 8003482: f44f 6000 mov.w r0, #2048 ; 0x800 8003486: f000 faaf bl 80039e8 } 800348a: bf00 nop 800348c: bd80 pop {r7, pc} 800348e: bf00 nop 8003490: 200002f8 .word 0x200002f8 08003494 : //GB/T Version packet void GBT_SendCHM(){ 8003494: b580 push {r7, lr} 8003496: b082 sub sp, #8 8003498: af00 add r7, sp, #0 uint8_t data[3]; data[0] = 0x01; 800349a: 2301 movs r3, #1 800349c: 713b strb r3, [r7, #4] data[1] = 0x01; 800349e: 2301 movs r3, #1 80034a0: 717b strb r3, [r7, #5] data[2] = 0x00; 80034a2: 2300 movs r3, #0 80034a4: 71bb strb r3, [r7, #6] J_SendPacket(0x2600, 6, 3, data); 80034a6: 1d3b adds r3, r7, #4 80034a8: 2203 movs r2, #3 80034aa: 2106 movs r1, #6 80034ac: f44f 5018 mov.w r0, #9728 ; 0x2600 80034b0: f000 fa9a bl 80039e8 } 80034b4: bf00 nop 80034b6: 3708 adds r7, #8 80034b8: 46bd mov sp, r7 80034ba: bd80 pop {r7, pc} 080034bc : //GB/T CRM Packet (state=BMS identified) void GBT_SendCRM(uint8_t state){ 80034bc: b580 push {r7, lr} 80034be: b082 sub sp, #8 80034c0: af00 add r7, sp, #0 80034c2: 4603 mov r3, r0 80034c4: 71fb strb r3, [r7, #7] // data[3] = 0x01; // data[4] = 0x00; // data[5] = 0x42; //TODO: location BFG // data[6] = 0x46; // data[7] = 0x47; GBT_ChargerInfo.bmsIdentified = state; 80034c6: 4a07 ldr r2, [pc, #28] ; (80034e4 ) 80034c8: 79fb ldrb r3, [r7, #7] 80034ca: 7013 strb r3, [r2, #0] J_SendPacket(0x100, 6, 8, (uint8_t *)&GBT_ChargerInfo); 80034cc: 4b05 ldr r3, [pc, #20] ; (80034e4 ) 80034ce: 2208 movs r2, #8 80034d0: 2106 movs r1, #6 80034d2: f44f 7080 mov.w r0, #256 ; 0x100 80034d6: f000 fa87 bl 80039e8 } 80034da: bf00 nop 80034dc: 3708 adds r7, #8 80034de: 46bd mov sp, r7 80034e0: bd80 pop {r7, pc} 80034e2: bf00 nop 80034e4: 20000300 .word 0x20000300 080034e8 : //GB/T CRO packet (Charger ready) void GBT_SendCRO(uint8_t state){ 80034e8: b580 push {r7, lr} 80034ea: b084 sub sp, #16 80034ec: af00 add r7, sp, #0 80034ee: 4603 mov r3, r0 80034f0: 71fb strb r3, [r7, #7] uint8_t data[1]; data[0] = state; 80034f2: 79fb ldrb r3, [r7, #7] 80034f4: 733b strb r3, [r7, #12] J_SendPacket(0xA00, 4, 1, data); 80034f6: f107 030c add.w r3, r7, #12 80034fa: 2201 movs r2, #1 80034fc: 2104 movs r1, #4 80034fe: f44f 6020 mov.w r0, #2560 ; 0xa00 8003502: f000 fa71 bl 80039e8 } 8003506: bf00 nop 8003508: 3710 adds r7, #16 800350a: 46bd mov sp, r7 800350c: bd80 pop {r7, pc} ... 08003510 : //GB/T CCS packet (Charger current status) void GBT_SendCCS(){ 8003510: b580 push {r7, lr} 8003512: af00 add r7, sp, #0 // data[3] = GBT_CurrPower.requestedCurrent>>8; //TODO: current // data[4] = GBT_StateTick()/60000; //charging time (min) // data[5] = 0; //TODO: 255 min+ // data[6] = 0b11111101; //charging not permitted // data[7] = 0xFF; J_SendPacket(0x1200, 6, 8, (uint8_t *)&GBT_ChargerCurrentStatus); 8003514: 4b04 ldr r3, [pc, #16] ; (8003528 ) 8003516: 2208 movs r2, #8 8003518: 2106 movs r1, #6 800351a: f44f 5090 mov.w r0, #4608 ; 0x1200 800351e: f000 fa63 bl 80039e8 } 8003522: bf00 nop 8003524: bd80 pop {r7, pc} 8003526: bf00 nop 8003528: 20000374 .word 0x20000374 0800352c : // GB/T Charging Stop packet void GBT_SendCST(uint32_t Cause){ 800352c: b580 push {r7, lr} 800352e: b084 sub sp, #16 8003530: af00 add r7, sp, #0 8003532: 6078 str r0, [r7, #4] uint8_t data[8]; data[0] = (Cause>>24) & 0xFF; // Error 8003534: 687b ldr r3, [r7, #4] 8003536: 0e1b lsrs r3, r3, #24 8003538: b2db uxtb r3, r3 800353a: 723b strb r3, [r7, #8] data[1] = (Cause>>16) & 0xFF; // 800353c: 687b ldr r3, [r7, #4] 800353e: 0c1b lsrs r3, r3, #16 8003540: b2db uxtb r3, r3 8003542: 727b strb r3, [r7, #9] data[2] = (Cause>>8) & 0xFF; // 8003544: 687b ldr r3, [r7, #4] 8003546: 0a1b lsrs r3, r3, #8 8003548: b2db uxtb r3, r3 800354a: 72bb strb r3, [r7, #10] data[3] = Cause & 0xFF; // 800354c: 687b ldr r3, [r7, #4] 800354e: b2db uxtb r3, r3 8003550: 72fb strb r3, [r7, #11] J_SendPacket(0x1A00, 4, 4, data); 8003552: f107 0308 add.w r3, r7, #8 8003556: 2204 movs r2, #4 8003558: 2104 movs r1, #4 800355a: f44f 50d0 mov.w r0, #6656 ; 0x1a00 800355e: f000 fa43 bl 80039e8 } 8003562: bf00 nop 8003564: 3710 adds r7, #16 8003566: 46bd mov sp, r7 8003568: bd80 pop {r7, pc} ... 0800356c : void GBT_SendCSD(){ 800356c: b580 push {r7, lr} 800356e: af00 add r7, sp, #0 GBT_ChargerStop.chargerNumber = GBT_ChargerInfo.chargerNumber; 8003570: 4b0b ldr r3, [pc, #44] ; (80035a0 ) 8003572: f8d3 3001 ldr.w r3, [r3, #1] 8003576: 4a0b ldr r2, [pc, #44] ; (80035a4 ) 8003578: 6053 str r3, [r2, #4] GBT_ChargerStop.outputEnergy = 0; //TODO Energy meters 800357a: 4b0a ldr r3, [pc, #40] ; (80035a4 ) 800357c: 2200 movs r2, #0 800357e: 709a strb r2, [r3, #2] 8003580: 2200 movs r2, #0 8003582: 70da strb r2, [r3, #3] GBT_ChargerStop.chargingTime = GBT_ChargerCurrentStatus.chargingTime; 8003584: 4b08 ldr r3, [pc, #32] ; (80035a8 ) 8003586: 889b ldrh r3, [r3, #4] 8003588: b29a uxth r2, r3 800358a: 4b06 ldr r3, [pc, #24] ; (80035a4 ) 800358c: 801a strh r2, [r3, #0] J_SendPacket(0x1D00, 6, 7, (uint8_t *)&GBT_ChargerStop); 800358e: 4b05 ldr r3, [pc, #20] ; (80035a4 ) 8003590: 2207 movs r2, #7 8003592: 2106 movs r1, #6 8003594: f44f 50e8 mov.w r0, #7424 ; 0x1d00 8003598: f000 fa26 bl 80039e8 } 800359c: bf00 nop 800359e: bd80 pop {r7, pc} 80035a0: 20000300 .word 0x20000300 80035a4: 2000037c .word 0x2000037c 80035a8: 20000374 .word 0x20000374 080035ac : void GBT_SendCEM(uint32_t ErrorCode){ 80035ac: b580 push {r7, lr} 80035ae: b084 sub sp, #16 80035b0: af00 add r7, sp, #0 80035b2: 6078 str r0, [r7, #4] uint8_t data[8]; data[0] = (ErrorCode>>24) & 0xFF; // Error 80035b4: 687b ldr r3, [r7, #4] 80035b6: 0e1b lsrs r3, r3, #24 80035b8: b2db uxtb r3, r3 80035ba: 723b strb r3, [r7, #8] data[1] = (ErrorCode>>16) & 0xFF; // 80035bc: 687b ldr r3, [r7, #4] 80035be: 0c1b lsrs r3, r3, #16 80035c0: b2db uxtb r3, r3 80035c2: 727b strb r3, [r7, #9] data[2] = (ErrorCode>>8) & 0xFF; // 80035c4: 687b ldr r3, [r7, #4] 80035c6: 0a1b lsrs r3, r3, #8 80035c8: b2db uxtb r3, r3 80035ca: 72bb strb r3, [r7, #10] data[3] = ErrorCode & 0xFF; // 80035cc: 687b ldr r3, [r7, #4] 80035ce: b2db uxtb r3, r3 80035d0: 72fb strb r3, [r7, #11] J_SendPacket(0x1F00, 4, 4, data); 80035d2: f107 0308 add.w r3, r7, #8 80035d6: 2204 movs r2, #4 80035d8: 2104 movs r1, #4 80035da: f44f 50f8 mov.w r0, #7936 ; 0x1f00 80035de: f000 fa03 bl 80039e8 } 80035e2: bf00 nop 80035e4: 3710 adds r7, #16 80035e6: 46bd mov sp, r7 80035e8: bd80 pop {r7, pc} ... 080035ec : * Output * EVENT_OUT * EXTI */ void MX_GPIO_Init(void) { 80035ec: b580 push {r7, lr} 80035ee: b08a sub sp, #40 ; 0x28 80035f0: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80035f2: f107 0318 add.w r3, r7, #24 80035f6: 2200 movs r2, #0 80035f8: 601a str r2, [r3, #0] 80035fa: 605a str r2, [r3, #4] 80035fc: 609a str r2, [r3, #8] 80035fe: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8003600: 4b53 ldr r3, [pc, #332] ; (8003750 ) 8003602: 699b ldr r3, [r3, #24] 8003604: 4a52 ldr r2, [pc, #328] ; (8003750 ) 8003606: f043 0310 orr.w r3, r3, #16 800360a: 6193 str r3, [r2, #24] 800360c: 4b50 ldr r3, [pc, #320] ; (8003750 ) 800360e: 699b ldr r3, [r3, #24] 8003610: f003 0310 and.w r3, r3, #16 8003614: 617b str r3, [r7, #20] 8003616: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8003618: 4b4d ldr r3, [pc, #308] ; (8003750 ) 800361a: 699b ldr r3, [r3, #24] 800361c: 4a4c ldr r2, [pc, #304] ; (8003750 ) 800361e: f043 0304 orr.w r3, r3, #4 8003622: 6193 str r3, [r2, #24] 8003624: 4b4a ldr r3, [pc, #296] ; (8003750 ) 8003626: 699b ldr r3, [r3, #24] 8003628: f003 0304 and.w r3, r3, #4 800362c: 613b str r3, [r7, #16] 800362e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8003630: 4b47 ldr r3, [pc, #284] ; (8003750 ) 8003632: 699b ldr r3, [r3, #24] 8003634: 4a46 ldr r2, [pc, #280] ; (8003750 ) 8003636: f043 0308 orr.w r3, r3, #8 800363a: 6193 str r3, [r2, #24] 800363c: 4b44 ldr r3, [pc, #272] ; (8003750 ) 800363e: 699b ldr r3, [r3, #24] 8003640: f003 0308 and.w r3, r3, #8 8003644: 60fb str r3, [r7, #12] 8003646: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 8003648: 4b41 ldr r3, [pc, #260] ; (8003750 ) 800364a: 699b ldr r3, [r3, #24] 800364c: 4a40 ldr r2, [pc, #256] ; (8003750 ) 800364e: f043 0340 orr.w r3, r3, #64 ; 0x40 8003652: 6193 str r3, [r2, #24] 8003654: 4b3e ldr r3, [pc, #248] ; (8003750 ) 8003656: 699b ldr r3, [r3, #24] 8003658: f003 0340 and.w r3, r3, #64 ; 0x40 800365c: 60bb str r3, [r7, #8] 800365e: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 8003660: 4b3b ldr r3, [pc, #236] ; (8003750 ) 8003662: 699b ldr r3, [r3, #24] 8003664: 4a3a ldr r2, [pc, #232] ; (8003750 ) 8003666: f043 0320 orr.w r3, r3, #32 800366a: 6193 str r3, [r2, #24] 800366c: 4b38 ldr r3, [pc, #224] ; (8003750 ) 800366e: 699b ldr r3, [r3, #24] 8003670: f003 0320 and.w r3, r3, #32 8003674: 607b str r3, [r7, #4] 8003676: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, LOCK_A_Pin|LOCK_B_Pin, GPIO_PIN_RESET); 8003678: 2200 movs r2, #0 800367a: 2130 movs r1, #48 ; 0x30 800367c: 4835 ldr r0, [pc, #212] ; (8003754 ) 800367e: f003 fd52 bl 8007126 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, GPIO_PIN_RESET); 8003682: 2200 movs r2, #0 8003684: f44f 4100 mov.w r1, #32768 ; 0x8000 8003688: 4833 ldr r0, [pc, #204] ; (8003758 ) 800368a: f003 fd4c bl 8007126 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800368e: 2200 movs r2, #0 8003690: 2110 movs r1, #16 8003692: 4832 ldr r0, [pc, #200] ; (800375c ) 8003694: f003 fd47 bl 8007126 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(RELAY_AUX_GPIO_Port, RELAY_AUX_Pin, GPIO_PIN_RESET); 8003698: 2200 movs r2, #0 800369a: 2110 movs r1, #16 800369c: 4830 ldr r0, [pc, #192] ; (8003760 ) 800369e: f003 fd42 bl 8007126 /*Configure GPIO pins : PCPin PCPin */ GPIO_InitStruct.Pin = LOCK_A_Pin|LOCK_B_Pin; 80036a2: 2330 movs r3, #48 ; 0x30 80036a4: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80036a6: 2301 movs r3, #1 80036a8: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80036aa: 2300 movs r3, #0 80036ac: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80036ae: 2302 movs r3, #2 80036b0: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80036b2: f107 0318 add.w r3, r7, #24 80036b6: 4619 mov r1, r3 80036b8: 4826 ldr r0, [pc, #152] ; (8003754 ) 80036ba: f003 fb99 bl 8006df0 /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = LOCK_FB_Pin; 80036be: f44f 7300 mov.w r3, #512 ; 0x200 80036c2: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80036c4: 2300 movs r3, #0 80036c6: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80036c8: 2300 movs r3, #0 80036ca: 623b str r3, [r7, #32] HAL_GPIO_Init(LOCK_FB_GPIO_Port, &GPIO_InitStruct); 80036cc: f107 0318 add.w r3, r7, #24 80036d0: 4619 mov r1, r3 80036d2: 4821 ldr r0, [pc, #132] ; (8003758 ) 80036d4: f003 fb8c bl 8006df0 /*Configure GPIO pins : PEPin PEPin */ GPIO_InitStruct.Pin = ADDR_0_Pin|ADDR_1_Pin; 80036d8: f44f 6340 mov.w r3, #3072 ; 0xc00 80036dc: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80036de: 2300 movs r3, #0 80036e0: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_PULLUP; 80036e2: 2301 movs r3, #1 80036e4: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 80036e6: f107 0318 add.w r3, r7, #24 80036ea: 4619 mov r1, r3 80036ec: 481a ldr r0, [pc, #104] ; (8003758 ) 80036ee: f003 fb7f bl 8006df0 /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = RELAY_CC_Pin; 80036f2: f44f 4300 mov.w r3, #32768 ; 0x8000 80036f6: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80036f8: 2301 movs r3, #1 80036fa: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80036fc: 2300 movs r3, #0 80036fe: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003700: 2302 movs r3, #2 8003702: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(RELAY_CC_GPIO_Port, &GPIO_InitStruct); 8003704: f107 0318 add.w r3, r7, #24 8003708: 4619 mov r1, r3 800370a: 4813 ldr r0, [pc, #76] ; (8003758 ) 800370c: f003 fb70 bl 8006df0 /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = USART2_DIR_Pin; 8003710: 2310 movs r3, #16 8003712: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8003714: 2301 movs r3, #1 8003716: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003718: 2300 movs r3, #0 800371a: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800371c: 2302 movs r3, #2 800371e: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(USART2_DIR_GPIO_Port, &GPIO_InitStruct); 8003720: f107 0318 add.w r3, r7, #24 8003724: 4619 mov r1, r3 8003726: 480d ldr r0, [pc, #52] ; (800375c ) 8003728: f003 fb62 bl 8006df0 /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = RELAY_AUX_Pin; 800372c: 2310 movs r3, #16 800372e: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8003730: 2301 movs r3, #1 8003732: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003734: 2300 movs r3, #0 8003736: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003738: 2302 movs r3, #2 800373a: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(RELAY_AUX_GPIO_Port, &GPIO_InitStruct); 800373c: f107 0318 add.w r3, r7, #24 8003740: 4619 mov r1, r3 8003742: 4807 ldr r0, [pc, #28] ; (8003760 ) 8003744: f003 fb54 bl 8006df0 } 8003748: bf00 nop 800374a: 3728 adds r7, #40 ; 0x28 800374c: 46bd mov sp, r7 800374e: bd80 pop {r7, pc} 8003750: 40021000 .word 0x40021000 8003754: 40011000 .word 0x40011000 8003758: 40011800 .word 0x40011800 800375c: 40011400 .word 0x40011400 8003760: 40010c00 .word 0x40010c00 08003764 : extern GBT_BCL_t GBT_CurrPower; j_receive_t j_rx; void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { 8003764: b590 push {r4, r7, lr} 8003766: b0cd sub sp, #308 ; 0x134 8003768: af40 add r7, sp, #256 ; 0x100 800376a: 6078 str r0, [r7, #4] CAN_RxHeaderTypeDef RxHeader; uint8_t RxData[8] = {0,}; 800376c: 2300 movs r3, #0 800376e: 60fb str r3, [r7, #12] 8003770: 2300 movs r3, #0 8003772: 613b str r3, [r7, #16] if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &RxHeader, RxData) == HAL_OK) 8003774: f107 030c add.w r3, r7, #12 8003778: f107 0214 add.w r2, r7, #20 800377c: 2100 movs r1, #0 800377e: 6878 ldr r0, [r7, #4] 8003780: f002 fdb1 bl 80062e6 8003784: 4603 mov r3, r0 8003786: 2b00 cmp r3, #0 8003788: f040 8111 bne.w 80039ae { if((RxHeader.ExtId & 0x00FFFF) == ((J_ID_SE << 8) | J_ID_EV)){ // SA, DA match 800378c: 69bb ldr r3, [r7, #24] 800378e: b29b uxth r3, r3 8003790: f245 62f4 movw r2, #22260 ; 0x56f4 8003794: 4293 cmp r3, r2 8003796: f040 810a bne.w 80039ae switch ((RxHeader.ExtId>>8) & 0x00FF00){ 800379a: 69bb ldr r3, [r7, #24] 800379c: 0a1b lsrs r3, r3, #8 800379e: f403 437f and.w r3, r3, #65280 ; 0xff00 80037a2: f5b3 4f6c cmp.w r3, #60416 ; 0xec00 80037a6: d013 beq.n 80037d0 80037a8: f5b3 4f6c cmp.w r3, #60416 ; 0xec00 80037ac: f200 80ca bhi.w 8003944 80037b0: f5b3 4f6b cmp.w r3, #60160 ; 0xeb00 80037b4: d056 beq.n 8003864 80037b6: f5b3 4f6b cmp.w r3, #60160 ; 0xeb00 80037ba: f200 80c3 bhi.w 8003944 80037be: f5b3 5fc8 cmp.w r3, #6400 ; 0x1900 80037c2: f000 80bb beq.w 800393c 80037c6: f5b3 5ff0 cmp.w r3, #7680 ; 0x1e00 80037ca: f000 80b4 beq.w 8003936 80037ce: e0b9 b.n 8003944 case 0xEC00: //PGN Connection Management Message if(RxData[0] == 16){ //Request to Send 80037d0: 7b3b ldrb r3, [r7, #12] 80037d2: 2b10 cmp r3, #16 80037d4: d13d bne.n 8003852 /* Set the RTS values */ j_rx.size = RxData[1] | (RxData[2]<<8); 80037d6: 7b7b ldrb r3, [r7, #13] 80037d8: b21a sxth r2, r3 80037da: 7bbb ldrb r3, [r7, #14] 80037dc: 021b lsls r3, r3, #8 80037de: b21b sxth r3, r3 80037e0: 4313 orrs r3, r2 80037e2: b21b sxth r3, r3 80037e4: b29a uxth r2, r3 80037e6: 4b74 ldr r3, [pc, #464] ; (80039b8 ) 80037e8: f8a3 2104 strh.w r2, [r3, #260] ; 0x104 j_rx.packet = 1; 80037ec: 4b72 ldr r3, [pc, #456] ; (80039b8 ) 80037ee: 2201 movs r2, #1 80037f0: f883 2107 strb.w r2, [r3, #263] ; 0x107 j_rx.packets = RxData[3]; 80037f4: 7bfa ldrb r2, [r7, #15] 80037f6: 4b70 ldr r3, [pc, #448] ; (80039b8 ) 80037f8: f883 2106 strb.w r2, [r3, #262] ; 0x106 j_rx.step = 2; //TODO 80037fc: 4b6e ldr r3, [pc, #440] ; (80039b8 ) 80037fe: 2202 movs r2, #2 8003800: f883 2108 strb.w r2, [r3, #264] ; 0x108 j_rx.step_cts_remain = j_rx.step; 8003804: 4b6c ldr r3, [pc, #432] ; (80039b8 ) 8003806: f893 2108 ldrb.w r2, [r3, #264] ; 0x108 800380a: 4b6b ldr r3, [pc, #428] ; (80039b8 ) 800380c: f883 2109 strb.w r2, [r3, #265] ; 0x109 j_rx.PGN = (RxData[7] << 16) | (RxData[6] << 8) | RxData[5]; 8003810: 7cfb ldrb r3, [r7, #19] 8003812: 041a lsls r2, r3, #16 8003814: 7cbb ldrb r3, [r7, #18] 8003816: 021b lsls r3, r3, #8 8003818: 4313 orrs r3, r2 800381a: 7c7a ldrb r2, [r7, #17] 800381c: 4313 orrs r3, r2 800381e: 461a mov r2, r3 8003820: 4b65 ldr r3, [pc, #404] ; (80039b8 ) 8003822: f8c3 2100 str.w r2, [r3, #256] ; 0x100 if(j_rx.size<256) { //TODO: valid check 8003826: 4b64 ldr r3, [pc, #400] ; (80039b8 ) 8003828: f8b3 3104 ldrh.w r3, [r3, #260] ; 0x104 800382c: 2bff cmp r3, #255 ; 0xff 800382e: d810 bhi.n 8003852 J_SendCTS(j_rx); 8003830: 4c61 ldr r4, [pc, #388] ; (80039b8 ) 8003832: 4668 mov r0, sp 8003834: f104 0310 add.w r3, r4, #16 8003838: f44f 7280 mov.w r2, #256 ; 0x100 800383c: 4619 mov r1, r3 800383e: f005 fcd7 bl 80091f0 8003842: e894 000f ldmia.w r4, {r0, r1, r2, r3} 8003846: f000 f8f7 bl 8003a38 j_rx.state = 1; 800384a: 4b5b ldr r3, [pc, #364] ; (80039b8 ) 800384c: 2201 movs r2, #1 800384e: f883 210a strb.w r2, [r3, #266] ; 0x10a } } if(RxData[0] == 255){ //Connection Abort 8003852: 7b3b ldrb r3, [r7, #12] 8003854: 2bff cmp r3, #255 ; 0xff 8003856: f040 80a5 bne.w 80039a4 j_rx.state = 0; 800385a: 4b57 ldr r3, [pc, #348] ; (80039b8 ) 800385c: 2200 movs r2, #0 800385e: f883 210a strb.w r2, [r3, #266] ; 0x10a * 1CECF456 11 02 01 FF FF 00 02 00 * 1CEB56F4 01 01 01 00 03 46 05 40 * 1CEC56F4 FF FF FF FF FF 00 00 00 */ break; 8003862: e09f b.n 80039a4 case 0xEB00: //PGN Data Message if(j_rx.state != 1) break; 8003864: 4b54 ldr r3, [pc, #336] ; (80039b8 ) 8003866: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 800386a: 2b01 cmp r3, #1 800386c: f040 809c bne.w 80039a8 if((RxData[0]>0) && (RxData[0]<35)){ //Array limit check 8003870: 7b3b ldrb r3, [r7, #12] 8003872: 2b00 cmp r3, #0 8003874: f000 809a beq.w 80039ac 8003878: 7b3b ldrb r3, [r7, #12] 800387a: 2b22 cmp r3, #34 ; 0x22 800387c: f200 8096 bhi.w 80039ac if(j_rx.packet == RxData[0]){ //step check 8003880: 4b4d ldr r3, [pc, #308] ; (80039b8 ) 8003882: f893 2107 ldrb.w r2, [r3, #263] ; 0x107 8003886: 7b3b ldrb r3, [r7, #12] 8003888: 429a cmp r2, r3 800388a: f040 808f bne.w 80039ac memcpy (&j_rx.data[(RxData[0]-1)*7], &RxData[1],7); 800388e: 7b3b ldrb r3, [r7, #12] 8003890: 1e5a subs r2, r3, #1 8003892: 4613 mov r3, r2 8003894: 00db lsls r3, r3, #3 8003896: 1a9b subs r3, r3, r2 8003898: 4a47 ldr r2, [pc, #284] ; (80039b8 ) 800389a: 1898 adds r0, r3, r2 800389c: f107 030c add.w r3, r7, #12 80038a0: 3301 adds r3, #1 80038a2: 2207 movs r2, #7 80038a4: 4619 mov r1, r3 80038a6: f005 fca3 bl 80091f0 j_rx.packet++; 80038aa: 4b43 ldr r3, [pc, #268] ; (80039b8 ) 80038ac: f893 3107 ldrb.w r3, [r3, #263] ; 0x107 80038b0: 3301 adds r3, #1 80038b2: b2da uxtb r2, r3 80038b4: 4b40 ldr r3, [pc, #256] ; (80039b8 ) 80038b6: f883 2107 strb.w r2, [r3, #263] ; 0x107 if(j_rx.packet > j_rx.packets){ 80038ba: 4b3f ldr r3, [pc, #252] ; (80039b8 ) 80038bc: f893 2107 ldrb.w r2, [r3, #263] ; 0x107 80038c0: 4b3d ldr r3, [pc, #244] ; (80039b8 ) 80038c2: f893 3106 ldrb.w r3, [r3, #262] ; 0x106 80038c6: 429a cmp r2, r3 80038c8: d911 bls.n 80038ee //End of transmission J_SendACK(j_rx); 80038ca: 4c3b ldr r4, [pc, #236] ; (80039b8 ) 80038cc: 4668 mov r0, sp 80038ce: f104 0310 add.w r3, r4, #16 80038d2: f44f 7280 mov.w r2, #256 ; 0x100 80038d6: 4619 mov r1, r3 80038d8: f005 fc8a bl 80091f0 80038dc: e894 000f ldmia.w r4, {r0, r1, r2, r3} 80038e0: f000 f8f0 bl 8003ac4 j_rx.state = 2; 80038e4: 4b34 ldr r3, [pc, #208] ; (80039b8 ) 80038e6: 2202 movs r2, #2 80038e8: f883 210a strb.w r2, [r3, #266] ; 0x10a j_rx.step_cts_remain = 2; } } } } break; 80038ec: e05e b.n 80039ac if(j_rx.step_cts_remain > 0) j_rx.step_cts_remain--; 80038ee: 4b32 ldr r3, [pc, #200] ; (80039b8 ) 80038f0: f893 3109 ldrb.w r3, [r3, #265] ; 0x109 80038f4: 2b00 cmp r3, #0 80038f6: d007 beq.n 8003908 80038f8: 4b2f ldr r3, [pc, #188] ; (80039b8 ) 80038fa: f893 3109 ldrb.w r3, [r3, #265] ; 0x109 80038fe: 3b01 subs r3, #1 8003900: b2da uxtb r2, r3 8003902: 4b2d ldr r3, [pc, #180] ; (80039b8 ) 8003904: f883 2109 strb.w r2, [r3, #265] ; 0x109 if(j_rx.step_cts_remain == 0){ 8003908: 4b2b ldr r3, [pc, #172] ; (80039b8 ) 800390a: f893 3109 ldrb.w r3, [r3, #265] ; 0x109 800390e: 2b00 cmp r3, #0 8003910: d14c bne.n 80039ac J_SendCTS(j_rx); 8003912: 4c29 ldr r4, [pc, #164] ; (80039b8 ) 8003914: 4668 mov r0, sp 8003916: f104 0310 add.w r3, r4, #16 800391a: f44f 7280 mov.w r2, #256 ; 0x100 800391e: 4619 mov r1, r3 8003920: f005 fc66 bl 80091f0 8003924: e894 000f ldmia.w r4, {r0, r1, r2, r3} 8003928: f000 f886 bl 8003a38 j_rx.step_cts_remain = 2; 800392c: 4b22 ldr r3, [pc, #136] ; (80039b8 ) 800392e: 2202 movs r2, #2 8003930: f883 2109 strb.w r2, [r3, #265] ; 0x109 break; 8003934: e03a b.n 80039ac case 0x1E00: //PGN BEM (ERROR) //Error force stop GBT_ForceStop(); 8003936: f7fe fd2f bl 8002398 break; 800393a: e038 b.n 80039ae case 0x1900: //PGN BST (STOP) //Normal stop GBT_Stop(GBT_CST_BMS_ACTIVELY_SUSPENDS); 800393c: 481f ldr r0, [pc, #124] ; (80039bc ) 800393e: f7fe fd05 bl 800234c break; 8003942: e034 b.n 80039ae default: if(j_rx.state == 0){//TODO protections 8003944: 4b1c ldr r3, [pc, #112] ; (80039b8 ) 8003946: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 800394a: 2b00 cmp r3, #0 800394c: d12f bne.n 80039ae //Short packet j_rx.size = RxHeader.DLC; 800394e: 6a7b ldr r3, [r7, #36] ; 0x24 8003950: b29a uxth r2, r3 8003952: 4b19 ldr r3, [pc, #100] ; (80039b8 ) 8003954: f8a3 2104 strh.w r2, [r3, #260] ; 0x104 j_rx.packet = 1; 8003958: 4b17 ldr r3, [pc, #92] ; (80039b8 ) 800395a: 2201 movs r2, #1 800395c: f883 2107 strb.w r2, [r3, #263] ; 0x107 j_rx.packets = 1; 8003960: 4b15 ldr r3, [pc, #84] ; (80039b8 ) 8003962: 2201 movs r2, #1 8003964: f883 2106 strb.w r2, [r3, #262] ; 0x106 j_rx.step = 1; 8003968: 4b13 ldr r3, [pc, #76] ; (80039b8 ) 800396a: 2201 movs r2, #1 800396c: f883 2108 strb.w r2, [r3, #264] ; 0x108 j_rx.step_cts_remain = 0; 8003970: 4b11 ldr r3, [pc, #68] ; (80039b8 ) 8003972: 2200 movs r2, #0 8003974: f883 2109 strb.w r2, [r3, #265] ; 0x109 j_rx.PGN = (RxHeader.ExtId>>8) & 0x00FF00; 8003978: 69bb ldr r3, [r7, #24] 800397a: 0a1b lsrs r3, r3, #8 800397c: f403 437f and.w r3, r3, #65280 ; 0xff00 8003980: 4a0d ldr r2, [pc, #52] ; (80039b8 ) 8003982: f8c2 3100 str.w r3, [r2, #256] ; 0x100 j_rx.state = 2; 8003986: 4b0c ldr r3, [pc, #48] ; (80039b8 ) 8003988: 2202 movs r2, #2 800398a: f883 210a strb.w r2, [r3, #266] ; 0x10a memcpy (j_rx.data, RxData, j_rx.size); 800398e: 4b0a ldr r3, [pc, #40] ; (80039b8 ) 8003990: f8b3 3104 ldrh.w r3, [r3, #260] ; 0x104 8003994: 461a mov r2, r3 8003996: f107 030c add.w r3, r7, #12 800399a: 4619 mov r1, r3 800399c: 4806 ldr r0, [pc, #24] ; (80039b8 ) 800399e: f005 fc27 bl 80091f0 } } } } } 80039a2: e004 b.n 80039ae break; 80039a4: bf00 nop 80039a6: e002 b.n 80039ae if(j_rx.state != 1) break; 80039a8: bf00 nop 80039aa: e000 b.n 80039ae break; 80039ac: bf00 nop } 80039ae: bf00 nop 80039b0: 3734 adds r7, #52 ; 0x34 80039b2: 46bd mov sp, r7 80039b4: bd90 pop {r4, r7, pc} 80039b6: bf00 nop 80039b8: 200004c0 .word 0x200004c0 80039bc: 4000f0f0 .word 0x4000f0f0 080039c0 : void GBT_CAN_ReInit(){ 80039c0: b580 push {r7, lr} 80039c2: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan1); 80039c4: 4807 ldr r0, [pc, #28] ; (80039e4 ) 80039c6: f002 fb37 bl 8006038 MX_CAN1_Init(); 80039ca: f7fd ffa9 bl 8001920 HAL_CAN_Start(&hcan1); 80039ce: 4805 ldr r0, [pc, #20] ; (80039e4 ) 80039d0: f002 faee bl 8005fb0 HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING); 80039d4: 2102 movs r1, #2 80039d6: 4803 ldr r0, [pc, #12] ; (80039e4 ) 80039d8: f002 fd96 bl 8006508 GBT_CAN_FilterInit(); 80039dc: f000 f8ac bl 8003b38 } 80039e0: bf00 nop 80039e2: bd80 pop {r7, pc} 80039e4: 20000290 .word 0x20000290 080039e8 : void J_SendPacket(uint32_t PGN, uint8_t pri, uint8_t DLC, uint8_t *data){ 80039e8: b580 push {r7, lr} 80039ea: b08c sub sp, #48 ; 0x30 80039ec: af00 add r7, sp, #0 80039ee: 60f8 str r0, [r7, #12] 80039f0: 607b str r3, [r7, #4] 80039f2: 460b mov r3, r1 80039f4: 72fb strb r3, [r7, #11] 80039f6: 4613 mov r3, r2 80039f8: 72bb strb r3, [r7, #10] CAN_TxHeaderTypeDef tx_header; uint32_t tx_mailbox; tx_header.ExtId = (pri << 26) | (PGN << 8) | (J_ID_EV << 8) | J_ID_SE; 80039fa: 7afb ldrb r3, [r7, #11] 80039fc: 069b lsls r3, r3, #26 80039fe: 461a mov r2, r3 8003a00: 68fb ldr r3, [r7, #12] 8003a02: 021b lsls r3, r3, #8 8003a04: 4313 orrs r3, r2 8003a06: f443 4374 orr.w r3, r3, #62464 ; 0xf400 8003a0a: f043 0356 orr.w r3, r3, #86 ; 0x56 8003a0e: 61fb str r3, [r7, #28] tx_header.RTR = CAN_RTR_DATA; 8003a10: 2300 movs r3, #0 8003a12: 627b str r3, [r7, #36] ; 0x24 tx_header.IDE = CAN_ID_EXT; 8003a14: 2304 movs r3, #4 8003a16: 623b str r3, [r7, #32] tx_header.DLC = DLC; 8003a18: 7abb ldrb r3, [r7, #10] 8003a1a: 62bb str r3, [r7, #40] ; 0x28 HAL_CAN_AddTxMessage(&hcan1, &tx_header, data, &tx_mailbox); 8003a1c: f107 0314 add.w r3, r7, #20 8003a20: f107 0118 add.w r1, r7, #24 8003a24: 687a ldr r2, [r7, #4] 8003a26: 4803 ldr r0, [pc, #12] ; (8003a34 ) 8003a28: f002 fb4f bl 80060ca //HAL_Delay(2); } 8003a2c: bf00 nop 8003a2e: 3730 adds r7, #48 ; 0x30 8003a30: 46bd mov sp, r7 8003a32: bd80 pop {r7, pc} 8003a34: 20000290 .word 0x20000290 08003a38 : //void J_SendPacketLong(){ // //TODO (no need) //} // J1939 sequence Clear To Send packet void J_SendCTS(j_receive_t rx){ 8003a38: b084 sub sp, #16 8003a3a: b580 push {r7, lr} 8003a3c: b082 sub sp, #8 8003a3e: af00 add r7, sp, #0 8003a40: f107 0c10 add.w ip, r7, #16 8003a44: e88c 000f stmia.w ip, {r0, r1, r2, r3} //if(rx.packets <= rx.packet) return; TODO uint8_t data[8]; data[0] = 17; //CONTROL_BYTE_TP_CM_CTS 8003a48: 2311 movs r3, #17 8003a4a: 703b strb r3, [r7, #0] data[1] = rx.step;//total_number_of_packages_transmitted 8003a4c: f897 3118 ldrb.w r3, [r7, #280] ; 0x118 8003a50: 707b strb r3, [r7, #1] if (rx.step > (rx.packets - rx.packet+1)) data[1] = rx.packets - rx.packet+1; 8003a52: f897 3118 ldrb.w r3, [r7, #280] ; 0x118 8003a56: 461a mov r2, r3 8003a58: f897 3116 ldrb.w r3, [r7, #278] ; 0x116 8003a5c: 4619 mov r1, r3 8003a5e: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8003a62: 1acb subs r3, r1, r3 8003a64: 3301 adds r3, #1 8003a66: 429a cmp r2, r3 8003a68: dd08 ble.n 8003a7c 8003a6a: f897 2116 ldrb.w r2, [r7, #278] ; 0x116 8003a6e: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8003a72: 1ad3 subs r3, r2, r3 8003a74: b2db uxtb r3, r3 8003a76: 3301 adds r3, #1 8003a78: b2db uxtb r3, r3 8003a7a: 707b strb r3, [r7, #1] data[2] = rx.packet;//next_packet_number_transmitted 8003a7c: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8003a80: 70bb strb r3, [r7, #2] data[3] = 0xFF; /* Reserved */ 8003a82: 23ff movs r3, #255 ; 0xff 8003a84: 70fb strb r3, [r7, #3] data[4] = 0xFF; 8003a86: 23ff movs r3, #255 ; 0xff 8003a88: 713b strb r3, [r7, #4] data[5] = rx.PGN; 8003a8a: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 8003a8e: b2db uxtb r3, r3 8003a90: 717b strb r3, [r7, #5] data[6] = rx.PGN >> 8; 8003a92: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 8003a96: 0a1b lsrs r3, r3, #8 8003a98: b2db uxtb r3, r3 8003a9a: 71bb strb r3, [r7, #6] data[7] = rx.PGN >> 16; 8003a9c: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 8003aa0: 0c1b lsrs r3, r3, #16 8003aa2: b2db uxtb r3, r3 8003aa4: 71fb strb r3, [r7, #7] J_SendPacket(0x00EC00, 7, 8, data); 8003aa6: 463b mov r3, r7 8003aa8: 2208 movs r2, #8 8003aaa: 2107 movs r1, #7 8003aac: f44f 406c mov.w r0, #60416 ; 0xec00 8003ab0: f7ff ff9a bl 80039e8 } 8003ab4: bf00 nop 8003ab6: 3708 adds r7, #8 8003ab8: 46bd mov sp, r7 8003aba: e8bd 4080 ldmia.w sp!, {r7, lr} 8003abe: b004 add sp, #16 8003ac0: 4770 bx lr ... 08003ac4 : // J1939 sequence ACK packet void J_SendACK(j_receive_t rx){//uint32_t PGN, uint8_t step, uint8_t packet){ 8003ac4: b084 sub sp, #16 8003ac6: b580 push {r7, lr} 8003ac8: b082 sub sp, #8 8003aca: af00 add r7, sp, #0 8003acc: f107 0c10 add.w ip, r7, #16 8003ad0: e88c 000f stmia.w ip, {r0, r1, r2, r3} uint8_t data[8]; data[0] = 19; //CONTROL_BYTE_TP_CM_ACK 8003ad4: 2313 movs r3, #19 8003ad6: 703b strb r3, [r7, #0] data[1] = j_rx.size; 8003ad8: 4b16 ldr r3, [pc, #88] ; (8003b34 ) 8003ada: f8b3 3104 ldrh.w r3, [r3, #260] ; 0x104 8003ade: b2db uxtb r3, r3 8003ae0: 707b strb r3, [r7, #1] data[2] = j_rx.size>>8; 8003ae2: 4b14 ldr r3, [pc, #80] ; (8003b34 ) 8003ae4: f8b3 3104 ldrh.w r3, [r3, #260] ; 0x104 8003ae8: 0a1b lsrs r3, r3, #8 8003aea: b29b uxth r3, r3 8003aec: b2db uxtb r3, r3 8003aee: 70bb strb r3, [r7, #2] data[3] = j_rx.packets; 8003af0: 4b10 ldr r3, [pc, #64] ; (8003b34 ) 8003af2: f893 3106 ldrb.w r3, [r3, #262] ; 0x106 8003af6: 70fb strb r3, [r7, #3] data[4] = 0xFF;//TODO 8003af8: 23ff movs r3, #255 ; 0xff 8003afa: 713b strb r3, [r7, #4] data[5] = rx.PGN; 8003afc: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 8003b00: b2db uxtb r3, r3 8003b02: 717b strb r3, [r7, #5] data[6] = rx.PGN >> 8; 8003b04: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 8003b08: 0a1b lsrs r3, r3, #8 8003b0a: b2db uxtb r3, r3 8003b0c: 71bb strb r3, [r7, #6] data[7] = rx.PGN >> 16; 8003b0e: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 8003b12: 0c1b lsrs r3, r3, #16 8003b14: b2db uxtb r3, r3 8003b16: 71fb strb r3, [r7, #7] J_SendPacket(0x00EC00, 7, 8, data); 8003b18: 463b mov r3, r7 8003b1a: 2208 movs r2, #8 8003b1c: 2107 movs r1, #7 8003b1e: f44f 406c mov.w r0, #60416 ; 0xec00 8003b22: f7ff ff61 bl 80039e8 } 8003b26: bf00 nop 8003b28: 3708 adds r7, #8 8003b2a: 46bd mov sp, r7 8003b2c: e8bd 4080 ldmia.w sp!, {r7, lr} 8003b30: b004 add sp, #16 8003b32: 4770 bx lr 8003b34: 200004c0 .word 0x200004c0 08003b38 : void GBT_CAN_FilterInit(){ 8003b38: b580 push {r7, lr} 8003b3a: b08a sub sp, #40 ; 0x28 8003b3c: af00 add r7, sp, #0 CAN_FilterTypeDef sFilterConfig; sFilterConfig.FilterBank = 0; 8003b3e: 2300 movs r3, #0 8003b40: 617b str r3, [r7, #20] sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; 8003b42: 2300 movs r3, #0 8003b44: 61bb str r3, [r7, #24] sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; 8003b46: 2301 movs r3, #1 8003b48: 61fb str r3, [r7, #28] sFilterConfig.FilterIdHigh = 0x0000; 8003b4a: 2300 movs r3, #0 8003b4c: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = 0x0000; 8003b4e: 2300 movs r3, #0 8003b50: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 8003b52: 2300 movs r3, #0 8003b54: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = 0x0000; 8003b56: 2300 movs r3, #0 8003b58: 60fb str r3, [r7, #12] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; 8003b5a: 2300 movs r3, #0 8003b5c: 613b str r3, [r7, #16] sFilterConfig.FilterActivation = ENABLE; 8003b5e: 2301 movs r3, #1 8003b60: 623b str r3, [r7, #32] //sFilterConfig.SlaveStartFilterBank = 14; if(HAL_CAN_ConfigFilter(&hcan1, &sFilterConfig) != HAL_OK) 8003b62: 463b mov r3, r7 8003b64: 4619 mov r1, r3 8003b66: 4806 ldr r0, [pc, #24] ; (8003b80 ) 8003b68: f002 f942 bl 8005df0 8003b6c: 4603 mov r3, r0 8003b6e: 2b00 cmp r3, #0 8003b70: d001 beq.n 8003b76 { Error_Handler(); 8003b72: f000 feeb bl 800494c } } 8003b76: bf00 nop 8003b78: 3728 adds r7, #40 ; 0x28 8003b7a: 46bd mov sp, r7 8003b7c: bd80 pop {r7, pc} 8003b7e: bf00 nop 8003b80: 20000290 .word 0x20000290 08003b84 : uint8_t LOCK_DELAY = 50; GBT_LockState_t GBT_LockState; void GBT_ForceLock(uint8_t state){ 8003b84: b580 push {r7, lr} 8003b86: b082 sub sp, #8 8003b88: af00 add r7, sp, #0 8003b8a: 4603 mov r3, r0 8003b8c: 71fb strb r3, [r7, #7] if(LOCK_MOTOR_POLARITY){ 8003b8e: 4b26 ldr r3, [pc, #152] ; (8003c28 ) 8003b90: 781b ldrb r3, [r3, #0] 8003b92: 2b00 cmp r3, #0 8003b94: d022 beq.n 8003bdc if(state){//LOCK 8003b96: 79fb ldrb r3, [r7, #7] 8003b98: 2b00 cmp r3, #0 8003b9a: d00f beq.n 8003bbc HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 1); 8003b9c: 2201 movs r2, #1 8003b9e: 2120 movs r1, #32 8003ba0: 4822 ldr r0, [pc, #136] ; (8003c2c ) 8003ba2: f003 fac0 bl 8007126 HAL_Delay(LOCK_DELAY); 8003ba6: 4b22 ldr r3, [pc, #136] ; (8003c30 ) 8003ba8: 781b ldrb r3, [r3, #0] 8003baa: 4618 mov r0, r3 8003bac: f001 fafc bl 80051a8 HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 0); 8003bb0: 2200 movs r2, #0 8003bb2: 2120 movs r1, #32 8003bb4: 481d ldr r0, [pc, #116] ; (8003c2c ) 8003bb6: f003 fab6 bl 8007126 HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 1); HAL_Delay(LOCK_DELAY); HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 0); } } } 8003bba: e031 b.n 8003c20 HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 1); 8003bbc: 2201 movs r2, #1 8003bbe: 2110 movs r1, #16 8003bc0: 481a ldr r0, [pc, #104] ; (8003c2c ) 8003bc2: f003 fab0 bl 8007126 HAL_Delay(LOCK_DELAY); 8003bc6: 4b1a ldr r3, [pc, #104] ; (8003c30 ) 8003bc8: 781b ldrb r3, [r3, #0] 8003bca: 4618 mov r0, r3 8003bcc: f001 faec bl 80051a8 HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 0); 8003bd0: 2200 movs r2, #0 8003bd2: 2110 movs r1, #16 8003bd4: 4815 ldr r0, [pc, #84] ; (8003c2c ) 8003bd6: f003 faa6 bl 8007126 } 8003bda: e021 b.n 8003c20 if(state){//LOCK 8003bdc: 79fb ldrb r3, [r7, #7] 8003bde: 2b00 cmp r3, #0 8003be0: d00f beq.n 8003c02 HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 1); 8003be2: 2201 movs r2, #1 8003be4: 2110 movs r1, #16 8003be6: 4811 ldr r0, [pc, #68] ; (8003c2c ) 8003be8: f003 fa9d bl 8007126 HAL_Delay(LOCK_DELAY); 8003bec: 4b10 ldr r3, [pc, #64] ; (8003c30 ) 8003bee: 781b ldrb r3, [r3, #0] 8003bf0: 4618 mov r0, r3 8003bf2: f001 fad9 bl 80051a8 HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 0); 8003bf6: 2200 movs r2, #0 8003bf8: 2110 movs r1, #16 8003bfa: 480c ldr r0, [pc, #48] ; (8003c2c ) 8003bfc: f003 fa93 bl 8007126 } 8003c00: e00e b.n 8003c20 HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 1); 8003c02: 2201 movs r2, #1 8003c04: 2120 movs r1, #32 8003c06: 4809 ldr r0, [pc, #36] ; (8003c2c ) 8003c08: f003 fa8d bl 8007126 HAL_Delay(LOCK_DELAY); 8003c0c: 4b08 ldr r3, [pc, #32] ; (8003c30 ) 8003c0e: 781b ldrb r3, [r3, #0] 8003c10: 4618 mov r0, r3 8003c12: f001 fac9 bl 80051a8 HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 0); 8003c16: 2200 movs r2, #0 8003c18: 2120 movs r1, #32 8003c1a: 4804 ldr r0, [pc, #16] ; (8003c2c ) 8003c1c: f003 fa83 bl 8007126 } 8003c20: bf00 nop 8003c22: 3708 adds r7, #8 8003c24: 46bd mov sp, r7 8003c26: bd80 pop {r7, pc} 8003c28: 20000001 .word 0x20000001 8003c2c: 40011000 .word 0x40011000 8003c30: 20000002 .word 0x20000002 08003c34 : uint8_t GBT_LockGetState(){ 8003c34: b580 push {r7, lr} 8003c36: af00 add r7, sp, #0 //1 = locked //0 = unlocked if(LOCK_POLARITY){ 8003c38: 4b0b ldr r3, [pc, #44] ; (8003c68 ) 8003c3a: 781b ldrb r3, [r3, #0] 8003c3c: 2b00 cmp r3, #0 8003c3e: d006 beq.n 8003c4e return HAL_GPIO_ReadPin(LOCK_FB_GPIO_Port, LOCK_FB_Pin); 8003c40: f44f 7100 mov.w r1, #512 ; 0x200 8003c44: 4809 ldr r0, [pc, #36] ; (8003c6c ) 8003c46: f003 fa57 bl 80070f8 8003c4a: 4603 mov r3, r0 8003c4c: e00a b.n 8003c64 }else{ return !HAL_GPIO_ReadPin(LOCK_FB_GPIO_Port, LOCK_FB_Pin); 8003c4e: f44f 7100 mov.w r1, #512 ; 0x200 8003c52: 4806 ldr r0, [pc, #24] ; (8003c6c ) 8003c54: f003 fa50 bl 80070f8 8003c58: 4603 mov r3, r0 8003c5a: 2b00 cmp r3, #0 8003c5c: bf0c ite eq 8003c5e: 2301 moveq r3, #1 8003c60: 2300 movne r3, #0 8003c62: b2db uxtb r3, r3 } } 8003c64: 4618 mov r0, r3 8003c66: bd80 pop {r7, pc} 8003c68: 20000000 .word 0x20000000 8003c6c: 40011800 .word 0x40011800 08003c70 : void GBT_Lock(uint8_t state){ 8003c70: b480 push {r7} 8003c72: b083 sub sp, #12 8003c74: af00 add r7, sp, #0 8003c76: 4603 mov r3, r0 8003c78: 71fb strb r3, [r7, #7] GBT_LockState.demand = state; 8003c7a: 4a04 ldr r2, [pc, #16] ; (8003c8c ) 8003c7c: 79fb ldrb r3, [r7, #7] 8003c7e: 7013 strb r3, [r2, #0] } 8003c80: bf00 nop 8003c82: 370c adds r7, #12 8003c84: 46bd mov sp, r7 8003c86: bc80 pop {r7} 8003c88: 4770 bx lr 8003c8a: bf00 nop 8003c8c: 200005d0 .word 0x200005d0 08003c90 : void GBT_ManageLock(){ 8003c90: b580 push {r7, lr} 8003c92: b082 sub sp, #8 8003c94: af00 add r7, sp, #0 uint8_t MAX_RETRIES = 5; 8003c96: 2305 movs r3, #5 8003c98: 71bb strb r3, [r7, #6] if (GBT_LockState.error) { 8003c9a: 4b25 ldr r3, [pc, #148] ; (8003d30 ) 8003c9c: 785b ldrb r3, [r3, #1] 8003c9e: 2b00 cmp r3, #0 8003ca0: d142 bne.n 8003d28 return; } bool lock_is_open = GBT_LockGetState() == 0; 8003ca2: f7ff ffc7 bl 8003c34 8003ca6: 4603 mov r3, r0 8003ca8: 2b00 cmp r3, #0 8003caa: bf0c ite eq 8003cac: 2301 moveq r3, #1 8003cae: 2300 movne r3, #0 8003cb0: 717b strb r3, [r7, #5] bool lock_should_be_open = GBT_LockState.demand == 0; 8003cb2: 4b1f ldr r3, [pc, #124] ; (8003d30 ) 8003cb4: 781b ldrb r3, [r3, #0] 8003cb6: 2b00 cmp r3, #0 8003cb8: bf0c ite eq 8003cba: 2301 moveq r3, #1 8003cbc: 2300 movne r3, #0 8003cbe: 713b strb r3, [r7, #4] uint8_t retry_count = 0; 8003cc0: 2300 movs r3, #0 8003cc2: 71fb strb r3, [r7, #7] if (lock_is_open != lock_should_be_open) { 8003cc4: 797a ldrb r2, [r7, #5] 8003cc6: 793b ldrb r3, [r7, #4] 8003cc8: 429a cmp r2, r3 8003cca: d02e beq.n 8003d2a while (retry_count < MAX_RETRIES) { 8003ccc: e018 b.n 8003d00 if (lock_should_be_open) { 8003cce: 793b ldrb r3, [r7, #4] 8003cd0: 2b00 cmp r3, #0 8003cd2: d003 beq.n 8003cdc GBT_ForceLock(0); 8003cd4: 2000 movs r0, #0 8003cd6: f7ff ff55 bl 8003b84 8003cda: e002 b.n 8003ce2 } else { GBT_ForceLock(1); 8003cdc: 2001 movs r0, #1 8003cde: f7ff ff51 bl 8003b84 } lock_is_open = GBT_LockGetState() == 0; 8003ce2: f7ff ffa7 bl 8003c34 8003ce6: 4603 mov r3, r0 8003ce8: 2b00 cmp r3, #0 8003cea: bf0c ite eq 8003cec: 2301 moveq r3, #1 8003cee: 2300 movne r3, #0 8003cf0: 717b strb r3, [r7, #5] if (lock_is_open == lock_should_be_open) { 8003cf2: 797a ldrb r2, [r7, #5] 8003cf4: 793b ldrb r3, [r7, #4] 8003cf6: 429a cmp r2, r3 8003cf8: d007 beq.n 8003d0a break; } retry_count++; 8003cfa: 79fb ldrb r3, [r7, #7] 8003cfc: 3301 adds r3, #1 8003cfe: 71fb strb r3, [r7, #7] while (retry_count < MAX_RETRIES) { 8003d00: 79fa ldrb r2, [r7, #7] 8003d02: 79bb ldrb r3, [r7, #6] 8003d04: 429a cmp r2, r3 8003d06: d3e2 bcc.n 8003cce 8003d08: e000 b.n 8003d0c break; 8003d0a: bf00 nop } if (retry_count >= MAX_RETRIES) { 8003d0c: 79fa ldrb r2, [r7, #7] 8003d0e: 79bb ldrb r3, [r7, #6] 8003d10: 429a cmp r2, r3 8003d12: d30a bcc.n 8003d2a GBT_LockState.error = 1; 8003d14: 4b06 ldr r3, [pc, #24] ; (8003d30 ) 8003d16: 2201 movs r2, #1 8003d18: 705a strb r2, [r3, #1] GBT_ForceLock(0); 8003d1a: 2000 movs r0, #0 8003d1c: f7ff ff32 bl 8003b84 printf ("Lock error\n"); 8003d20: 4804 ldr r0, [pc, #16] ; (8003d34 ) 8003d22: f006 f83d bl 8009da0 8003d26: e000 b.n 8003d2a return; 8003d28: bf00 nop } } } 8003d2a: 3708 adds r7, #8 8003d2c: 46bd mov sp, r7 8003d2e: bd80 pop {r7, pc} 8003d30: 200005d0 .word 0x200005d0 8003d34: 0800d1f4 .word 0x0800d1f4 08003d38 <__NVIC_SystemReset>: { 8003d38: b480 push {r7} 8003d3a: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 8003d3c: f3bf 8f4f dsb sy } 8003d40: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 8003d42: 4b06 ldr r3, [pc, #24] ; (8003d5c <__NVIC_SystemReset+0x24>) 8003d44: 68db ldr r3, [r3, #12] 8003d46: f403 62e0 and.w r2, r3, #1792 ; 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8003d4a: 4904 ldr r1, [pc, #16] ; (8003d5c <__NVIC_SystemReset+0x24>) 8003d4c: 4b04 ldr r3, [pc, #16] ; (8003d60 <__NVIC_SystemReset+0x28>) 8003d4e: 4313 orrs r3, r2 8003d50: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 8003d52: f3bf 8f4f dsb sy } 8003d56: bf00 nop __NOP(); 8003d58: bf00 nop 8003d5a: e7fd b.n 8003d58 <__NVIC_SystemReset+0x20> 8003d5c: e000ed00 .word 0xe000ed00 8003d60: 05fa0004 .word 0x05fa0004 08003d64 : /** * @brief CAN Interrupt Handler for EDCAN (CAN2) * */ void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan){ 8003d64: b580 push {r7, lr} 8003d66: b082 sub sp, #8 8003d68: af00 add r7, sp, #0 8003d6a: 6078 str r0, [r7, #4] if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO1, &RxHeader, RxData) == HAL_OK) 8003d6c: 4b21 ldr r3, [pc, #132] ; (8003df4 ) 8003d6e: 4a22 ldr r2, [pc, #136] ; (8003df8 ) 8003d70: 2101 movs r1, #1 8003d72: 6878 ldr r0, [r7, #4] 8003d74: f002 fab7 bl 80062e6 8003d78: 4603 mov r3, r0 8003d7a: 2b00 cmp r3, #0 8003d7c: d136 bne.n 8003dec 8003d7e: 4b1e ldr r3, [pc, #120] ; (8003df8 ) 8003d80: 685b ldr r3, [r3, #4] { memcpy(&RxFrame.ExtID, &RxHeader.ExtId, sizeof(RxFrame.ExtID)); 8003d82: 4a1e ldr r2, [pc, #120] ; (8003dfc ) 8003d84: 6013 str r3, [r2, #0] RxFrame.DLC = RxHeader.DLC; 8003d86: 4b1c ldr r3, [pc, #112] ; (8003df8 ) 8003d88: 691b ldr r3, [r3, #16] 8003d8a: b2da uxtb r2, r3 8003d8c: 4b1b ldr r3, [pc, #108] ; (8003dfc ) 8003d8e: 731a strb r2, [r3, #12] memcpy(RxFrame.data, RxData, RxHeader.DLC); 8003d90: 4b19 ldr r3, [pc, #100] ; (8003df8 ) 8003d92: 691b ldr r3, [r3, #16] 8003d94: 461a mov r2, r3 8003d96: 4917 ldr r1, [pc, #92] ; (8003df4 ) 8003d98: 4819 ldr r0, [pc, #100] ; (8003e00 ) 8003d9a: f005 fa29 bl 80091f0 if((RxFrame.ExtID.DestinationID == ED_OwnID) || (RxFrame.ExtID.DestinationID == 0xFF) || (RxFrame.ExtID.DestinationID == ED_SecondID)){ 8003d9e: 4b17 ldr r3, [pc, #92] ; (8003dfc ) 8003da0: 781a ldrb r2, [r3, #0] 8003da2: 4b18 ldr r3, [pc, #96] ; (8003e04 ) 8003da4: 781b ldrb r3, [r3, #0] 8003da6: 429a cmp r2, r3 8003da8: d009 beq.n 8003dbe 8003daa: 4b14 ldr r3, [pc, #80] ; (8003dfc ) 8003dac: 781b ldrb r3, [r3, #0] 8003dae: 2bff cmp r3, #255 ; 0xff 8003db0: d005 beq.n 8003dbe 8003db2: 4b12 ldr r3, [pc, #72] ; (8003dfc ) 8003db4: 781a ldrb r2, [r3, #0] 8003db6: 4b14 ldr r3, [pc, #80] ; (8003e08 ) 8003db8: 781b ldrb r3, [r3, #0] 8003dba: 429a cmp r2, r3 8003dbc: d116 bne.n 8003dec //Мгновенная перезагрузка if(RxFrame.ExtID.RegisterAddress == 0x26){ 8003dbe: 4b0f ldr r3, [pc, #60] ; (8003dfc ) 8003dc0: 885b ldrh r3, [r3, #2] 8003dc2: f3c3 030a ubfx r3, r3, #0, #11 8003dc6: b29b uxth r3, r3 8003dc8: 2b26 cmp r3, #38 ; 0x26 8003dca: d105 bne.n 8003dd8 if(RxFrame.data[0] == 0x66) NVIC_SystemReset(); 8003dcc: 4b0b ldr r3, [pc, #44] ; (8003dfc ) 8003dce: 791b ldrb r3, [r3, #4] 8003dd0: 2b66 cmp r3, #102 ; 0x66 8003dd2: d101 bne.n 8003dd8 8003dd4: f7ff ffb0 bl 8003d38 <__NVIC_SystemReset> } //Выходим из Silent Mode сразу после получения любого пакета if(silentmode_enable) EDCAN_EnterSilentMode(0); 8003dd8: 4b0c ldr r3, [pc, #48] ; (8003e0c ) 8003dda: 681b ldr r3, [r3, #0] 8003ddc: 2b00 cmp r3, #0 8003dde: d002 beq.n 8003de6 8003de0: 2000 movs r0, #0 8003de2: f000 f99d bl 8004120 EDCAN_RxBufferAdd (&RxFrame); 8003de6: 4805 ldr r0, [pc, #20] ; (8003dfc ) 8003de8: f000 fadc bl 80043a4 // EDCAN_ExchangeRxBuffer(); } } } 8003dec: bf00 nop 8003dee: 3708 adds r7, #8 8003df0: 46bd mov sp, r7 8003df2: bd80 pop {r7, pc} 8003df4: 200005d4 .word 0x200005d4 8003df8: 200005dc .word 0x200005dc 8003dfc: 200005f8 .word 0x200005f8 8003e00: 200005fc .word 0x200005fc 8003e04: 200005d2 .word 0x200005d2 8003e08: 20000003 .word 0x20000003 8003e0c: 2000060c .word 0x2000060c 08003e10 : #endif void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan_){ 8003e10: b580 push {r7, lr} 8003e12: b082 sub sp, #8 8003e14: af00 add r7, sp, #0 8003e16: 6078 str r0, [r7, #4] if (hcan_->Instance == ED_CAN_INSTANCE.Instance){ 8003e18: 687b ldr r3, [r7, #4] 8003e1a: 681a ldr r2, [r3, #0] 8003e1c: 4b07 ldr r3, [pc, #28] ; (8003e3c ) 8003e1e: 681b ldr r3, [r3, #0] 8003e20: 429a cmp r2, r3 8003e22: d107 bne.n 8003e34 lasttxexchangetime = HAL_GetTick() + 1; 8003e24: f001 f9b6 bl 8005194 8003e28: 4603 mov r3, r0 8003e2a: 3301 adds r3, #1 8003e2c: 4a04 ldr r2, [pc, #16] ; (8003e40 ) 8003e2e: 6013 str r3, [r2, #0] EDCAN_ExchangeTxBuffer(); 8003e30: f000 f9ca bl 80041c8 } } 8003e34: bf00 nop 8003e36: 3708 adds r7, #8 8003e38: 46bd mov sp, r7 8003e3a: bd80 pop {r7, pc} 8003e3c: 200002b8 .word 0x200002b8 8003e40: 20000610 .word 0x20000610 08003e44 : void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan_){ 8003e44: b580 push {r7, lr} 8003e46: b082 sub sp, #8 8003e48: af00 add r7, sp, #0 8003e4a: 6078 str r0, [r7, #4] if (hcan_->Instance == ED_CAN_INSTANCE.Instance){ 8003e4c: 687b ldr r3, [r7, #4] 8003e4e: 681a ldr r2, [r3, #0] 8003e50: 4b07 ldr r3, [pc, #28] ; (8003e70 ) 8003e52: 681b ldr r3, [r3, #0] 8003e54: 429a cmp r2, r3 8003e56: d107 bne.n 8003e68 lasttxexchangetime = HAL_GetTick() + 1; 8003e58: f001 f99c bl 8005194 8003e5c: 4603 mov r3, r0 8003e5e: 3301 adds r3, #1 8003e60: 4a04 ldr r2, [pc, #16] ; (8003e74 ) 8003e62: 6013 str r3, [r2, #0] EDCAN_ExchangeTxBuffer(); 8003e64: f000 f9b0 bl 80041c8 } } 8003e68: bf00 nop 8003e6a: 3708 adds r7, #8 8003e6c: 46bd mov sp, r7 8003e6e: bd80 pop {r7, pc} 8003e70: 200002b8 .word 0x200002b8 8003e74: 20000610 .word 0x20000610 08003e78 : void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan_){ 8003e78: b580 push {r7, lr} 8003e7a: b082 sub sp, #8 8003e7c: af00 add r7, sp, #0 8003e7e: 6078 str r0, [r7, #4] if (hcan_->Instance == ED_CAN_INSTANCE.Instance){ 8003e80: 687b ldr r3, [r7, #4] 8003e82: 681a ldr r2, [r3, #0] 8003e84: 4b07 ldr r3, [pc, #28] ; (8003ea4 ) 8003e86: 681b ldr r3, [r3, #0] 8003e88: 429a cmp r2, r3 8003e8a: d107 bne.n 8003e9c lasttxexchangetime = HAL_GetTick() + 1; 8003e8c: f001 f982 bl 8005194 8003e90: 4603 mov r3, r0 8003e92: 3301 adds r3, #1 8003e94: 4a04 ldr r2, [pc, #16] ; (8003ea8 ) 8003e96: 6013 str r3, [r2, #0] EDCAN_ExchangeTxBuffer(); 8003e98: f000 f996 bl 80041c8 } } 8003e9c: bf00 nop 8003e9e: 3708 adds r7, #8 8003ea0: 46bd mov sp, r7 8003ea2: bd80 pop {r7, pc} 8003ea4: 200002b8 .word 0x200002b8 8003ea8: 20000610 .word 0x20000610 08003eac : /** * @brief EDCAN Initialization function * * @param _OwnID: EDCAN Device ID */ void EDCAN_Init(uint8_t _OwnID){ 8003eac: b480 push {r7} 8003eae: b083 sub sp, #12 8003eb0: af00 add r7, sp, #0 8003eb2: 4603 mov r3, r0 8003eb4: 71fb strb r3, [r7, #7] ED_OwnID = _OwnID; 8003eb6: 4a04 ldr r2, [pc, #16] ; (8003ec8 ) 8003eb8: 79fb ldrb r3, [r7, #7] 8003eba: 7013 strb r3, [r2, #0] }; 8003ebc: bf00 nop 8003ebe: 370c adds r7, #12 8003ec0: 46bd mov sp, r7 8003ec2: bc80 pop {r7} 8003ec4: 4770 bx lr 8003ec6: bf00 nop 8003ec8: 200005d2 .word 0x200005d2 08003ecc : /** * @brief CAN Reinitialization function * * */ void CAN_ReInit(){ 8003ecc: b580 push {r7, lr} 8003ece: af00 add r7, sp, #0 HAL_CAN_Stop(&ED_CAN_INSTANCE); 8003ed0: 4807 ldr r0, [pc, #28] ; (8003ef0 ) 8003ed2: f002 f8b1 bl 8006038 #ifdef ED_CAN1 MX_CAN1_Init(); #endif #ifdef ED_CAN2 MX_CAN2_Init(); 8003ed6: f7fd fd59 bl 800198c #endif EDCAN_FilterInit(); 8003eda: f000 f80b bl 8003ef4 HAL_CAN_Start(&ED_CAN_INSTANCE); 8003ede: 4804 ldr r0, [pc, #16] ; (8003ef0 ) 8003ee0: f002 f866 bl 8005fb0 #ifdef ED_CAN1 HAL_CAN_ActivateNotification(&ED_CAN_INSTANCE, CAN_IT_RX_FIFO0_MSG_PENDING | /*CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE |*/ CAN_IT_TX_MAILBOX_EMPTY); #endif #ifdef ED_CAN2 HAL_CAN_ActivateNotification(&ED_CAN_INSTANCE, CAN_IT_RX_FIFO1_MSG_PENDING | /*CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE |*/ CAN_IT_TX_MAILBOX_EMPTY); 8003ee4: 2111 movs r1, #17 8003ee6: 4802 ldr r0, [pc, #8] ; (8003ef0 ) 8003ee8: f002 fb0e bl 8006508 #endif } 8003eec: bf00 nop 8003eee: bd80 pop {r7, pc} 8003ef0: 200002b8 .word 0x200002b8 08003ef4 : * * @param _OwnID: EDCAN Device ID * * @retval HAL status */ void EDCAN_FilterInit(){ 8003ef4: b580 push {r7, lr} 8003ef6: b08a sub sp, #40 ; 0x28 8003ef8: af00 add r7, sp, #0 CAN_FilterTypeDef sFilterConfig; //Filter for Own ID sFilterConfig.FilterBank = 0; 8003efa: 2300 movs r3, #0 8003efc: 617b str r3, [r7, #20] sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; 8003efe: 2300 movs r3, #0 8003f00: 61bb str r3, [r7, #24] sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; 8003f02: 2301 movs r3, #1 8003f04: 61fb str r3, [r7, #28] sFilterConfig.FilterIdHigh = 0x0000; 8003f06: 2300 movs r3, #0 8003f08: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = (uint16_t)(ED_OwnID<<3)|0b100; 8003f0a: 4b34 ldr r3, [pc, #208] ; (8003fdc ) 8003f0c: 781b ldrb r3, [r3, #0] 8003f0e: b29b uxth r3, r3 8003f10: 00db lsls r3, r3, #3 8003f12: b29b uxth r3, r3 8003f14: f043 0304 orr.w r3, r3, #4 8003f18: b29b uxth r3, r3 8003f1a: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 8003f1c: 2300 movs r3, #0 8003f1e: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = (uint16_t)(0xFF<<3)|0b100; 8003f20: f240 73fc movw r3, #2044 ; 0x7fc 8003f24: 60fb str r3, [r7, #12] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; 8003f26: 2300 movs r3, #0 8003f28: 613b str r3, [r7, #16] sFilterConfig.FilterActivation = ENABLE; 8003f2a: 2301 movs r3, #1 8003f2c: 623b str r3, [r7, #32] #ifdef ED_CAN2 sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 8003f2e: 2301 movs r3, #1 8003f30: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 8003f32: 230e movs r3, #14 8003f34: 627b str r3, [r7, #36] ; 0x24 sFilterConfig.FilterBank = 14; 8003f36: 230e movs r3, #14 8003f38: 617b str r3, [r7, #20] #endif if(HAL_CAN_ConfigFilter(&ED_CAN_INSTANCE, &sFilterConfig) != HAL_OK){ 8003f3a: 463b mov r3, r7 8003f3c: 4619 mov r1, r3 8003f3e: 4828 ldr r0, [pc, #160] ; (8003fe0 ) 8003f40: f001 ff56 bl 8005df0 8003f44: 4603 mov r3, r0 8003f46: 2b00 cmp r3, #0 8003f48: d001 beq.n 8003f4e Error_Handler(); 8003f4a: f000 fcff bl 800494c } // Filter for broadcast ID sFilterConfig.FilterBank = 1; 8003f4e: 2301 movs r3, #1 8003f50: 617b str r3, [r7, #20] sFilterConfig.FilterIdHigh = 0x0000; 8003f52: 2300 movs r3, #0 8003f54: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = (uint16_t)(0xFF<<3)|0b100; 8003f56: f240 73fc movw r3, #2044 ; 0x7fc 8003f5a: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 8003f5c: 2300 movs r3, #0 8003f5e: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = (uint16_t)(0xFF<<3)|0b100; 8003f60: f240 73fc movw r3, #2044 ; 0x7fc 8003f64: 60fb str r3, [r7, #12] #ifdef ED_CAN2 sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 8003f66: 2301 movs r3, #1 8003f68: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 8003f6a: 230e movs r3, #14 8003f6c: 627b str r3, [r7, #36] ; 0x24 sFilterConfig.FilterBank = 15; 8003f6e: 230f movs r3, #15 8003f70: 617b str r3, [r7, #20] #endif if(HAL_CAN_ConfigFilter(&ED_CAN_INSTANCE, &sFilterConfig) != HAL_OK) 8003f72: 463b mov r3, r7 8003f74: 4619 mov r1, r3 8003f76: 481a ldr r0, [pc, #104] ; (8003fe0 ) 8003f78: f001 ff3a bl 8005df0 8003f7c: 4603 mov r3, r0 8003f7e: 2b00 cmp r3, #0 8003f80: d001 beq.n 8003f86 { Error_Handler(); 8003f82: f000 fce3 bl 800494c } // Filter for second ID if(ED_SecondID != 0xFF){ 8003f86: 4b17 ldr r3, [pc, #92] ; (8003fe4 ) 8003f88: 781b ldrb r3, [r3, #0] 8003f8a: 2bff cmp r3, #255 ; 0xff 8003f8c: d021 beq.n 8003fd2 sFilterConfig.FilterBank = 2; 8003f8e: 2302 movs r3, #2 8003f90: 617b str r3, [r7, #20] sFilterConfig.FilterIdHigh = 0x0000; 8003f92: 2300 movs r3, #0 8003f94: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = (uint16_t)(ED_SecondID<<3)|0b100; 8003f96: 4b13 ldr r3, [pc, #76] ; (8003fe4 ) 8003f98: 781b ldrb r3, [r3, #0] 8003f9a: b29b uxth r3, r3 8003f9c: 00db lsls r3, r3, #3 8003f9e: b29b uxth r3, r3 8003fa0: f043 0304 orr.w r3, r3, #4 8003fa4: b29b uxth r3, r3 8003fa6: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 8003fa8: 2300 movs r3, #0 8003faa: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = (uint16_t)(0xFF<<3)|0b100; 8003fac: f240 73fc movw r3, #2044 ; 0x7fc 8003fb0: 60fb str r3, [r7, #12] #ifdef ED_CAN2 sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 8003fb2: 2301 movs r3, #1 8003fb4: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 8003fb6: 230e movs r3, #14 8003fb8: 627b str r3, [r7, #36] ; 0x24 sFilterConfig.FilterBank = 16; 8003fba: 2310 movs r3, #16 8003fbc: 617b str r3, [r7, #20] #endif if(HAL_CAN_ConfigFilter(&ED_CAN_INSTANCE, &sFilterConfig) != HAL_OK) 8003fbe: 463b mov r3, r7 8003fc0: 4619 mov r1, r3 8003fc2: 4807 ldr r0, [pc, #28] ; (8003fe0 ) 8003fc4: f001 ff14 bl 8005df0 8003fc8: 4603 mov r3, r0 8003fca: 2b00 cmp r3, #0 8003fcc: d001 beq.n 8003fd2 { Error_Handler(); 8003fce: f000 fcbd bl 800494c } } } 8003fd2: bf00 nop 8003fd4: 3728 adds r7, #40 ; 0x28 8003fd6: 46bd mov sp, r7 8003fd8: bd80 pop {r7, pc} 8003fda: bf00 nop 8003fdc: 200005d2 .word 0x200005d2 8003fe0: 200002b8 .word 0x200002b8 8003fe4: 20000003 .word 0x20000003 08003fe8 : * @param DestinationID: Packet Destination ID * @param RegAddr: First register address in sequence * @param *data: pointer to data array to be send * @param len: length of data (1..8) */ void EDCAN_SendPacketRead(uint8_t DestinationID, uint16_t RegAddr, uint8_t *data, uint8_t len){ 8003fe8: b580 push {r7, lr} 8003fea: b08c sub sp, #48 ; 0x30 8003fec: af00 add r7, sp, #0 8003fee: 603a str r2, [r7, #0] 8003ff0: 461a mov r2, r3 8003ff2: 4603 mov r3, r0 8003ff4: 71fb strb r3, [r7, #7] 8003ff6: 460b mov r3, r1 8003ff8: 80bb strh r3, [r7, #4] 8003ffa: 4613 mov r3, r2 8003ffc: 71bb strb r3, [r7, #6] EDCAN_TxFrame_t tx_frame; EDCAN_frameId_t ExtID; //CAN_TxHeaderTypeDef tx_header; //uint32_t tx_mailbox; ExtID.DestinationID = DestinationID; 8003ffe: 79fb ldrb r3, [r7, #7] 8004000: 733b strb r3, [r7, #12] ExtID.SourceID = ED_OwnID; 8004002: 4b15 ldr r3, [pc, #84] ; (8004058 ) 8004004: 781b ldrb r3, [r3, #0] 8004006: 737b strb r3, [r7, #13] ExtID.RegisterAddress = RegAddr; 8004008: 88bb ldrh r3, [r7, #4] 800400a: f3c3 030a ubfx r3, r3, #0, #11 800400e: b29a uxth r2, r3 8004010: 89fb ldrh r3, [r7, #14] 8004012: f362 030a bfi r3, r2, #0, #11 8004016: 81fb strh r3, [r7, #14] ExtID.PacketType = ED_READ; 8004018: 7bfb ldrb r3, [r7, #15] 800401a: 2202 movs r2, #2 800401c: f362 03c4 bfi r3, r2, #3, #2 8004020: 73fb strb r3, [r7, #15] 8004022: 68fb ldr r3, [r7, #12] memcpy(&tx_frame.tx_header.ExtId, &ExtID, sizeof(ExtID)); 8004024: 617b str r3, [r7, #20] tx_frame.tx_header.RTR = CAN_RTR_DATA; 8004026: 2300 movs r3, #0 8004028: 61fb str r3, [r7, #28] tx_frame.tx_header.IDE = CAN_ID_EXT; 800402a: 2304 movs r3, #4 800402c: 61bb str r3, [r7, #24] tx_frame.tx_header.DLC = len; 800402e: 79bb ldrb r3, [r7, #6] 8004030: 623b str r3, [r7, #32] memcpy(&tx_frame.data, data, len); 8004032: 79ba ldrb r2, [r7, #6] 8004034: f107 0310 add.w r3, r7, #16 8004038: 3318 adds r3, #24 800403a: 6839 ldr r1, [r7, #0] 800403c: 4618 mov r0, r3 800403e: f005 f8d7 bl 80091f0 //EDCAN_AddTxMessage(&ED_CAN_INSTANCE, &tx_header, data, &tx_mailbox); //Добавление пакета в буфер EDCAN_TxBufferAdd(&tx_frame); 8004042: f107 0310 add.w r3, r7, #16 8004046: 4618 mov r0, r3 8004048: f000 f90c bl 8004264 //Также, попытаемся сразу перенести пакет в CAN (если там есть свободное место) //Если свободного места нету, то пакет перенесется в CAN позже по прерыванию освобождения буфера EDCAN_ExchangeTxBuffer(); 800404c: f000 f8bc bl 80041c8 } 8004050: bf00 nop 8004052: 3730 adds r7, #48 ; 0x30 8004054: 46bd mov sp, r7 8004056: bd80 pop {r7, pc} 8004058: 200005d2 .word 0x200005d2 0800405c : /** * @brief EDCAN loop function * Функция для управления буферами, должна быть в while(1) * */ void EDCAN_Loop(){ 800405c: b580 push {r7, lr} 800405e: af00 add r7, sp, #0 //Функция переинициализации пока что не используется // if(can_error){ // CAN_ReInit(); // can_error=0; // } if(silentmode_enable){ 8004060: 4b21 ldr r3, [pc, #132] ; (80040e8 ) 8004062: 681b ldr r3, [r3, #0] 8004064: 2b00 cmp r3, #0 8004066: d00c beq.n 8004082 if(silentmode_time < HAL_GetTick()){ 8004068: f001 f894 bl 8005194 800406c: 4602 mov r2, r0 800406e: 4b1f ldr r3, [pc, #124] ; (80040ec ) 8004070: 681b ldr r3, [r3, #0] 8004072: 429a cmp r2, r3 8004074: d905 bls.n 8004082 silentmode_enable = 0; 8004076: 4b1c ldr r3, [pc, #112] ; (80040e8 ) 8004078: 2200 movs r2, #0 800407a: 601a str r2, [r3, #0] EDCAN_SetSilentMode(0); 800407c: 2000 movs r0, #0 800407e: f000 f87d bl 800417c } } //every 2ms exchange buffer if (HAL_GetTick() > lasttxexchangetime){ 8004082: f001 f887 bl 8005194 8004086: 4602 mov r2, r0 8004088: 4b19 ldr r3, [pc, #100] ; (80040f0 ) 800408a: 681b ldr r3, [r3, #0] 800408c: 429a cmp r2, r3 800408e: d90c bls.n 80040aa if(EDCAN_getTxBufferElementCount()>0){ 8004090: f000 f932 bl 80042f8 8004094: 4603 mov r3, r0 8004096: 2b00 cmp r3, #0 8004098: d007 beq.n 80040aa lasttxexchangetime = HAL_GetTick() + 1; 800409a: f001 f87b bl 8005194 800409e: 4603 mov r3, r0 80040a0: 3301 adds r3, #1 80040a2: 4a13 ldr r2, [pc, #76] ; (80040f0 ) 80040a4: 6013 str r3, [r2, #0] EDCAN_ExchangeTxBuffer(); 80040a6: f000 f88f bl 80041c8 } } //every 1s alive packet if (HAL_GetTick() > lastalivepackettime){ 80040aa: f001 f873 bl 8005194 80040ae: 4602 mov r2, r0 80040b0: 4b10 ldr r3, [pc, #64] ; (80040f4 ) 80040b2: 681b ldr r3, [r3, #0] 80040b4: 429a cmp r2, r3 80040b6: d908 bls.n 80040ca lastalivepackettime = HAL_GetTick() + 1000; 80040b8: f001 f86c bl 8005194 80040bc: 4603 mov r3, r0 80040be: f503 737a add.w r3, r3, #1000 ; 0x3e8 80040c2: 4a0c ldr r2, [pc, #48] ; (80040f4 ) 80040c4: 6013 str r3, [r2, #0] EDCAN_SendAlivePacket(); 80040c6: f000 f817 bl 80040f8 } //exchange buffer // if (HAL_GetTick() > lastrxexchangetime){ if((EDCAN_getRxBufferElementCount()>0)&&(EDCAN_getTxBufferElementCount()<(BUFFER_SIZE*3/4))){ 80040ca: f000 f9eb bl 80044a4 80040ce: 4603 mov r3, r0 80040d0: 2b00 cmp r3, #0 80040d2: d006 beq.n 80040e2 80040d4: f000 f910 bl 80042f8 80040d8: 4603 mov r3, r0 80040da: 2bbf cmp r3, #191 ; 0xbf 80040dc: d801 bhi.n 80040e2 // lastrxexchangetime = HAL_GetTick() + 1; EDCAN_ExchangeRxBuffer(); 80040de: f000 f9ed bl 80044bc } // } } 80040e2: bf00 nop 80040e4: bd80 pop {r7, pc} 80040e6: bf00 nop 80040e8: 2000060c .word 0x2000060c 80040ec: 20000608 .word 0x20000608 80040f0: 20000610 .word 0x20000610 80040f4: 20000614 .word 0x20000614 080040f8 : void EDCAN_SendAlivePacket(){ 80040f8: b580 push {r7, lr} 80040fa: b082 sub sp, #8 80040fc: af00 add r7, sp, #0 uint8_t data[1]; uint8_t DestinationID = 0x00; 80040fe: 2300 movs r3, #0 8004100: 71fb strb r3, [r7, #7] data[0] = EDCAN_GetOwnRegisterValue(EDCAN_REG_SYS_STATUS); 8004102: 2000 movs r0, #0 8004104: f000 faec bl 80046e0 8004108: 4603 mov r3, r0 800410a: 713b strb r3, [r7, #4] EDCAN_SendPacketRead(DestinationID, EDCAN_REG_SYS_STATUS, data, 1); 800410c: 1d3a adds r2, r7, #4 800410e: 79f8 ldrb r0, [r7, #7] 8004110: 2301 movs r3, #1 8004112: 2100 movs r1, #0 8004114: f7ff ff68 bl 8003fe8 } 8004118: bf00 nop 800411a: 3708 adds r7, #8 800411c: 46bd mov sp, r7 800411e: bd80 pop {r7, pc} 08004120 : //функция установки таймера для входа в Silent режим //По истечении времени time выход из режима silent //если time = 0, выход из режима silent и сброс таймера void EDCAN_EnterSilentMode(uint8_t time){ 8004120: b580 push {r7, lr} 8004122: b082 sub sp, #8 8004124: af00 add r7, sp, #0 8004126: 4603 mov r3, r0 8004128: 71fb strb r3, [r7, #7] if(time==0){ 800412a: 79fb ldrb r3, [r7, #7] 800412c: 2b00 cmp r3, #0 800412e: d10b bne.n 8004148 EDCAN_SetSilentMode(0); 8004130: 2000 movs r0, #0 8004132: f000 f823 bl 800417c silentmode_time = HAL_GetTick(); 8004136: f001 f82d bl 8005194 800413a: 4603 mov r3, r0 800413c: 4a0d ldr r2, [pc, #52] ; (8004174 ) 800413e: 6013 str r3, [r2, #0] silentmode_enable = 0; 8004140: 4b0d ldr r3, [pc, #52] ; (8004178 ) 8004142: 2200 movs r2, #0 8004144: 601a str r2, [r3, #0] }else{ EDCAN_SetSilentMode(1); silentmode_time = HAL_GetTick()+((uint32_t)time * 1000); silentmode_enable = 1; } } 8004146: e010 b.n 800416a EDCAN_SetSilentMode(1); 8004148: 2001 movs r0, #1 800414a: f000 f817 bl 800417c silentmode_time = HAL_GetTick()+((uint32_t)time * 1000); 800414e: f001 f821 bl 8005194 8004152: 4602 mov r2, r0 8004154: 79fb ldrb r3, [r7, #7] 8004156: f44f 717a mov.w r1, #1000 ; 0x3e8 800415a: fb01 f303 mul.w r3, r1, r3 800415e: 4413 add r3, r2 8004160: 4a04 ldr r2, [pc, #16] ; (8004174 ) 8004162: 6013 str r3, [r2, #0] silentmode_enable = 1; 8004164: 4b04 ldr r3, [pc, #16] ; (8004178 ) 8004166: 2201 movs r2, #1 8004168: 601a str r2, [r3, #0] } 800416a: bf00 nop 800416c: 3708 adds r7, #8 800416e: 46bd mov sp, r7 8004170: bd80 pop {r7, pc} 8004172: bf00 nop 8004174: 20000608 .word 0x20000608 8004178: 2000060c .word 0x2000060c 0800417c : //Функция входа в Silent Режим void EDCAN_SetSilentMode(uint8_t state){ 800417c: b580 push {r7, lr} 800417e: b082 sub sp, #8 8004180: af00 add r7, sp, #0 8004182: 4603 mov r3, r0 8004184: 71fb strb r3, [r7, #7] HAL_CAN_Stop(&ED_CAN_INSTANCE); 8004186: 480f ldr r0, [pc, #60] ; (80041c4 ) 8004188: f001 ff56 bl 8006038 if(state){ 800418c: 79fb ldrb r3, [r7, #7] 800418e: 2b00 cmp r3, #0 8004190: d008 beq.n 80041a4 ED_CAN_INSTANCE.Instance->BTR |= CAN_MODE_SILENT; 8004192: 4b0c ldr r3, [pc, #48] ; (80041c4 ) 8004194: 681b ldr r3, [r3, #0] 8004196: 69da ldr r2, [r3, #28] 8004198: 4b0a ldr r3, [pc, #40] ; (80041c4 ) 800419a: 681b ldr r3, [r3, #0] 800419c: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000 80041a0: 61da str r2, [r3, #28] 80041a2: e007 b.n 80041b4 }else{ ED_CAN_INSTANCE.Instance->BTR &= ~CAN_MODE_SILENT; 80041a4: 4b07 ldr r3, [pc, #28] ; (80041c4 ) 80041a6: 681b ldr r3, [r3, #0] 80041a8: 69da ldr r2, [r3, #28] 80041aa: 4b06 ldr r3, [pc, #24] ; (80041c4 ) 80041ac: 681b ldr r3, [r3, #0] 80041ae: f022 4200 bic.w r2, r2, #2147483648 ; 0x80000000 80041b2: 61da str r2, [r3, #28] } HAL_CAN_Start(&ED_CAN_INSTANCE); 80041b4: 4803 ldr r0, [pc, #12] ; (80041c4 ) 80041b6: f001 fefb bl 8005fb0 } 80041ba: bf00 nop 80041bc: 3708 adds r7, #8 80041be: 46bd mov sp, r7 80041c0: bd80 pop {r7, pc} 80041c2: bf00 nop 80041c4: 200002b8 .word 0x200002b8 080041c8 : // Инициализация глобальных буферов TxCircularBuffer_t txBuffer = { .head = 0, .tail = 0, .count = 0 }; RxCircularBuffer_t rxBuffer = { .head = 0, .tail = 0, .count = 0 }; //Функция для передачи данных из буфера в mailbox CAN шины void EDCAN_ExchangeTxBuffer(){ 80041c8: b580 push {r7, lr} 80041ca: b08a sub sp, #40 ; 0x28 80041cc: af00 add r7, sp, #0 uint32_t tx_mailbox; HAL_StatusTypeDef CAN_result; // //если в буфере что-то есть и есть свободные Mailbox if((EDCAN_getTxBufferElementCount()>0) && (HAL_CAN_GetTxMailboxesFreeLevel(&ED_CAN_INSTANCE) > 0)){ 80041ce: f000 f893 bl 80042f8 80041d2: 4603 mov r3, r0 80041d4: 2b00 cmp r3, #0 80041d6: d03c beq.n 8004252 80041d8: 481f ldr r0, [pc, #124] ; (8004258 ) 80041da: f002 f850 bl 800627e 80041de: 4603 mov r3, r0 80041e0: 2b00 cmp r3, #0 80041e2: d036 beq.n 8004252 //Извлечь первый элемент буфера if(EDCAN_TxBufferPeekFirst(&TxFrame) == false) return; 80041e4: 1d3b adds r3, r7, #4 80041e6: 4618 mov r0, r3 80041e8: f000 f892 bl 8004310 80041ec: 4603 mov r3, r0 80041ee: f083 0301 eor.w r3, r3, #1 80041f2: b2db uxtb r3, r3 80041f4: 2b00 cmp r3, #0 80041f6: d12b bne.n 8004250 /* отправка сообщения */ CAN_result = HAL_CAN_AddTxMessage(&ED_CAN_INSTANCE, &TxFrame.tx_header, TxFrame.data, &tx_mailbox); 80041f8: 4638 mov r0, r7 80041fa: 1d3b adds r3, r7, #4 80041fc: f103 0218 add.w r2, r3, #24 8004200: 1d39 adds r1, r7, #4 8004202: 4603 mov r3, r0 8004204: 4814 ldr r0, [pc, #80] ; (8004258 ) 8004206: f001 ff60 bl 80060ca 800420a: 4603 mov r3, r0 800420c: f887 3027 strb.w r3, [r7, #39] ; 0x27 /* если отправка удалась, выход */ if(CAN_result == HAL_OK) { 8004210: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 8004214: 2b00 cmp r3, #0 8004216: d102 bne.n 800421e //Удаление элемента буфера в случае успешной передачи EDCAN_TxBufferRemoveFirst(); 8004218: f000 f89a bl 8004350 return; 800421c: e019 b.n 8004252 //TODO: retry counter management //HAL_Delay(1); //retry_counter--; /* если ошибка, обработка ошибки */ if(CAN_result == HAL_ERROR) { 800421e: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 8004222: 2b01 cmp r3, #1 8004224: d115 bne.n 8004252 if(ED_CAN_INSTANCE.ErrorCode & HAL_CAN_ERROR_NOT_INITIALIZED) { 8004226: 4b0c ldr r3, [pc, #48] ; (8004258 ) 8004228: 6a5b ldr r3, [r3, #36] ; 0x24 800422a: f403 2380 and.w r3, r3, #262144 ; 0x40000 800422e: 2b00 cmp r3, #0 8004230: d004 beq.n 800423c CAN_ReInit(); //CAN не инициализирован, переинициализация 8004232: f7ff fe4b bl 8003ecc printf("CAN Reinit\n"); 8004236: 4809 ldr r0, [pc, #36] ; (800425c ) 8004238: f005 fdb2 bl 8009da0 } //if(ED_CAN_INSTANCE.ErrorCode & HAL_CAN_ERROR_PARAM) printf("tx full\n"); printf("CAN.ErrorCode = %d\n",(int)ED_CAN_INSTANCE.ErrorCode); 800423c: 4b06 ldr r3, [pc, #24] ; (8004258 ) 800423e: 6a5b ldr r3, [r3, #36] ; 0x24 8004240: 4619 mov r1, r3 8004242: 4807 ldr r0, [pc, #28] ; (8004260 ) 8004244: f005 fd26 bl 8009c94 ED_CAN_INSTANCE.ErrorCode = 0; //Clear errors 8004248: 4b03 ldr r3, [pc, #12] ; (8004258 ) 800424a: 2200 movs r2, #0 800424c: 625a str r2, [r3, #36] ; 0x24 800424e: e000 b.n 8004252 if(EDCAN_TxBufferPeekFirst(&TxFrame) == false) return; 8004250: bf00 nop } } // __enable_irq(); } 8004252: 3728 adds r7, #40 ; 0x28 8004254: 46bd mov sp, r7 8004256: bd80 pop {r7, pc} 8004258: 200002b8 .word 0x200002b8 800425c: 0800d200 .word 0x0800d200 8004260: 0800d20c .word 0x0800d20c 08004264 : // Добавление элемента в буфер void EDCAN_TxBufferAdd(EDCAN_TxFrame_t *frame) { 8004264: b580 push {r7, lr} 8004266: b082 sub sp, #8 8004268: af00 add r7, sp, #0 800426a: 6078 str r0, [r7, #4] __ASM volatile ("cpsid i" : : : "memory"); 800426c: b672 cpsid i } 800426e: bf00 nop __disable_irq(); memcpy(&txBuffer.buffer[txBuffer.head], frame, sizeof(EDCAN_TxFrame_t)); 8004270: 4b20 ldr r3, [pc, #128] ; (80042f4 ) 8004272: f503 5300 add.w r3, r3, #8192 ; 0x2000 8004276: 881b ldrh r3, [r3, #0] 8004278: 015b lsls r3, r3, #5 800427a: 4a1e ldr r2, [pc, #120] ; (80042f4 ) 800427c: 4413 add r3, r2 800427e: 2220 movs r2, #32 8004280: 6879 ldr r1, [r7, #4] 8004282: 4618 mov r0, r3 8004284: f004 ffb4 bl 80091f0 txBuffer.head = (txBuffer.head + 1) % BUFFER_SIZE; 8004288: 4b1a ldr r3, [pc, #104] ; (80042f4 ) 800428a: f503 5300 add.w r3, r3, #8192 ; 0x2000 800428e: 881b ldrh r3, [r3, #0] 8004290: 3301 adds r3, #1 8004292: 425a negs r2, r3 8004294: b2db uxtb r3, r3 8004296: b2d2 uxtb r2, r2 8004298: bf58 it pl 800429a: 4253 negpl r3, r2 800429c: b29a uxth r2, r3 800429e: 4b15 ldr r3, [pc, #84] ; (80042f4 ) 80042a0: f503 5300 add.w r3, r3, #8192 ; 0x2000 80042a4: 801a strh r2, [r3, #0] if (txBuffer.count == BUFFER_SIZE) { 80042a6: 4b13 ldr r3, [pc, #76] ; (80042f4 ) 80042a8: f503 5300 add.w r3, r3, #8192 ; 0x2000 80042ac: 889b ldrh r3, [r3, #4] 80042ae: f5b3 7f80 cmp.w r3, #256 ; 0x100 80042b2: d10f bne.n 80042d4 txBuffer.tail = (txBuffer.tail + 1) % BUFFER_SIZE; // Перезапись старых данных 80042b4: 4b0f ldr r3, [pc, #60] ; (80042f4 ) 80042b6: f503 5300 add.w r3, r3, #8192 ; 0x2000 80042ba: 885b ldrh r3, [r3, #2] 80042bc: 3301 adds r3, #1 80042be: 425a negs r2, r3 80042c0: b2db uxtb r3, r3 80042c2: b2d2 uxtb r2, r2 80042c4: bf58 it pl 80042c6: 4253 negpl r3, r2 80042c8: b29a uxth r2, r3 80042ca: 4b0a ldr r3, [pc, #40] ; (80042f4 ) 80042cc: f503 5300 add.w r3, r3, #8192 ; 0x2000 80042d0: 805a strh r2, [r3, #2] 80042d2: e009 b.n 80042e8 } else { txBuffer.count++; 80042d4: 4b07 ldr r3, [pc, #28] ; (80042f4 ) 80042d6: f503 5300 add.w r3, r3, #8192 ; 0x2000 80042da: 889b ldrh r3, [r3, #4] 80042dc: 3301 adds r3, #1 80042de: b29a uxth r2, r3 80042e0: 4b04 ldr r3, [pc, #16] ; (80042f4 ) 80042e2: f503 5300 add.w r3, r3, #8192 ; 0x2000 80042e6: 809a strh r2, [r3, #4] __ASM volatile ("cpsie i" : : : "memory"); 80042e8: b662 cpsie i } 80042ea: bf00 nop } __enable_irq(); } 80042ec: bf00 nop 80042ee: 3708 adds r7, #8 80042f0: 46bd mov sp, r7 80042f2: bd80 pop {r7, pc} 80042f4: 20000618 .word 0x20000618 080042f8 : return false; } } //Количество элементов в буфере uint16_t EDCAN_getTxBufferElementCount() { 80042f8: b480 push {r7} 80042fa: af00 add r7, sp, #0 return txBuffer.count; 80042fc: 4b03 ldr r3, [pc, #12] ; (800430c ) 80042fe: f503 5300 add.w r3, r3, #8192 ; 0x2000 8004302: 889b ldrh r3, [r3, #4] } 8004304: 4618 mov r0, r3 8004306: 46bd mov sp, r7 8004308: bc80 pop {r7} 800430a: 4770 bx lr 800430c: 20000618 .word 0x20000618 08004310 : // функция для получения первого элемента без удаления его из буфера bool EDCAN_TxBufferPeekFirst(EDCAN_TxFrame_t *frame) { 8004310: b580 push {r7, lr} 8004312: b082 sub sp, #8 8004314: af00 add r7, sp, #0 8004316: 6078 str r0, [r7, #4] //__disable_irq(); if (txBuffer.count > 0) { 8004318: 4b0c ldr r3, [pc, #48] ; (800434c ) 800431a: f503 5300 add.w r3, r3, #8192 ; 0x2000 800431e: 889b ldrh r3, [r3, #4] 8004320: 2b00 cmp r3, #0 8004322: d00d beq.n 8004340 memcpy(frame, &txBuffer.buffer[txBuffer.tail], sizeof(EDCAN_TxFrame_t)); 8004324: 4b09 ldr r3, [pc, #36] ; (800434c ) 8004326: f503 5300 add.w r3, r3, #8192 ; 0x2000 800432a: 885b ldrh r3, [r3, #2] 800432c: 015b lsls r3, r3, #5 800432e: 4a07 ldr r2, [pc, #28] ; (800434c ) 8004330: 4413 add r3, r2 8004332: 2220 movs r2, #32 8004334: 4619 mov r1, r3 8004336: 6878 ldr r0, [r7, #4] 8004338: f004 ff5a bl 80091f0 return true; 800433c: 2301 movs r3, #1 800433e: e000 b.n 8004342 } else { // Буфер пуст, можно добавить обработку ошибки return false; 8004340: 2300 movs r3, #0 } //__enable_irq(); } 8004342: 4618 mov r0, r3 8004344: 3708 adds r7, #8 8004346: 46bd mov sp, r7 8004348: bd80 pop {r7, pc} 800434a: bf00 nop 800434c: 20000618 .word 0x20000618 08004350 : // функция для удаления первого элемента из буфера bool EDCAN_TxBufferRemoveFirst() { 8004350: b480 push {r7} 8004352: af00 add r7, sp, #0 if (txBuffer.count > 0) { 8004354: 4b12 ldr r3, [pc, #72] ; (80043a0 ) 8004356: f503 5300 add.w r3, r3, #8192 ; 0x2000 800435a: 889b ldrh r3, [r3, #4] 800435c: 2b00 cmp r3, #0 800435e: d01a beq.n 8004396 txBuffer.tail = (txBuffer.tail + 1) % BUFFER_SIZE; 8004360: 4b0f ldr r3, [pc, #60] ; (80043a0 ) 8004362: f503 5300 add.w r3, r3, #8192 ; 0x2000 8004366: 885b ldrh r3, [r3, #2] 8004368: 3301 adds r3, #1 800436a: 425a negs r2, r3 800436c: b2db uxtb r3, r3 800436e: b2d2 uxtb r2, r2 8004370: bf58 it pl 8004372: 4253 negpl r3, r2 8004374: b29a uxth r2, r3 8004376: 4b0a ldr r3, [pc, #40] ; (80043a0 ) 8004378: f503 5300 add.w r3, r3, #8192 ; 0x2000 800437c: 805a strh r2, [r3, #2] txBuffer.count--; 800437e: 4b08 ldr r3, [pc, #32] ; (80043a0 ) 8004380: f503 5300 add.w r3, r3, #8192 ; 0x2000 8004384: 889b ldrh r3, [r3, #4] 8004386: 3b01 subs r3, #1 8004388: b29a uxth r2, r3 800438a: 4b05 ldr r3, [pc, #20] ; (80043a0 ) 800438c: f503 5300 add.w r3, r3, #8192 ; 0x2000 8004390: 809a strh r2, [r3, #4] return true; 8004392: 2301 movs r3, #1 8004394: e000 b.n 8004398 } else { // Буфер пуст, можно добавить обработку ошибки return false; 8004396: 2300 movs r3, #0 } } 8004398: 4618 mov r0, r3 800439a: 46bd mov sp, r7 800439c: bc80 pop {r7} 800439e: 4770 bx lr 80043a0: 20000618 .word 0x20000618 080043a4 : // Функции работы с Rx буфером void EDCAN_RxBufferAdd(EDCAN_RxFrame_t *frame) { 80043a4: b580 push {r7, lr} 80043a6: b082 sub sp, #8 80043a8: af00 add r7, sp, #0 80043aa: 6078 str r0, [r7, #4] __ASM volatile ("cpsid i" : : : "memory"); 80043ac: b672 cpsid i } 80043ae: bf00 nop __disable_irq(); memcpy(&rxBuffer.buffer[rxBuffer.head], frame, sizeof(EDCAN_RxFrame_t)); 80043b0: 4b1f ldr r3, [pc, #124] ; (8004430 ) 80043b2: f8b3 3d00 ldrh.w r3, [r3, #3328] ; 0xd00 80043b6: 461a mov r2, r3 80043b8: 4613 mov r3, r2 80043ba: 005b lsls r3, r3, #1 80043bc: 4413 add r3, r2 80043be: 009b lsls r3, r3, #2 80043c0: 4413 add r3, r2 80043c2: 4a1b ldr r2, [pc, #108] ; (8004430 ) 80043c4: 4413 add r3, r2 80043c6: 220d movs r2, #13 80043c8: 6879 ldr r1, [r7, #4] 80043ca: 4618 mov r0, r3 80043cc: f004 ff10 bl 80091f0 rxBuffer.head = (rxBuffer.head + 1) % BUFFER_SIZE; 80043d0: 4b17 ldr r3, [pc, #92] ; (8004430 ) 80043d2: f8b3 3d00 ldrh.w r3, [r3, #3328] ; 0xd00 80043d6: 3301 adds r3, #1 80043d8: 425a negs r2, r3 80043da: b2db uxtb r3, r3 80043dc: b2d2 uxtb r2, r2 80043de: bf58 it pl 80043e0: 4253 negpl r3, r2 80043e2: b29a uxth r2, r3 80043e4: 4b12 ldr r3, [pc, #72] ; (8004430 ) 80043e6: f8a3 2d00 strh.w r2, [r3, #3328] ; 0xd00 if (rxBuffer.count == BUFFER_SIZE) { 80043ea: 4b11 ldr r3, [pc, #68] ; (8004430 ) 80043ec: f8b3 3d04 ldrh.w r3, [r3, #3332] ; 0xd04 80043f0: f5b3 7f80 cmp.w r3, #256 ; 0x100 80043f4: d10d bne.n 8004412 rxBuffer.tail = (rxBuffer.tail + 1) % BUFFER_SIZE; // Перезапись старых данных 80043f6: 4b0e ldr r3, [pc, #56] ; (8004430 ) 80043f8: f8b3 3d02 ldrh.w r3, [r3, #3330] ; 0xd02 80043fc: 3301 adds r3, #1 80043fe: 425a negs r2, r3 8004400: b2db uxtb r3, r3 8004402: b2d2 uxtb r2, r2 8004404: bf58 it pl 8004406: 4253 negpl r3, r2 8004408: b29a uxth r2, r3 800440a: 4b09 ldr r3, [pc, #36] ; (8004430 ) 800440c: f8a3 2d02 strh.w r2, [r3, #3330] ; 0xd02 8004410: e007 b.n 8004422 } else { rxBuffer.count++; 8004412: 4b07 ldr r3, [pc, #28] ; (8004430 ) 8004414: f8b3 3d04 ldrh.w r3, [r3, #3332] ; 0xd04 8004418: 3301 adds r3, #1 800441a: b29a uxth r2, r3 800441c: 4b04 ldr r3, [pc, #16] ; (8004430 ) 800441e: f8a3 2d04 strh.w r2, [r3, #3332] ; 0xd04 __ASM volatile ("cpsie i" : : : "memory"); 8004422: b662 cpsie i } 8004424: bf00 nop } __enable_irq(); } 8004426: bf00 nop 8004428: 3708 adds r7, #8 800442a: 46bd mov sp, r7 800442c: bd80 pop {r7, pc} 800442e: bf00 nop 8004430: 20002620 .word 0x20002620 08004434 : //Извлечь и удалить первый элемент буфера bool EDCAN_RxBufferGet(EDCAN_RxFrame_t *frame) { 8004434: b580 push {r7, lr} 8004436: b082 sub sp, #8 8004438: af00 add r7, sp, #0 800443a: 6078 str r0, [r7, #4] if (rxBuffer.count > 0) { 800443c: 4b18 ldr r3, [pc, #96] ; (80044a0 ) 800443e: f8b3 3d04 ldrh.w r3, [r3, #3332] ; 0xd04 8004442: 2b00 cmp r3, #0 8004444: d026 beq.n 8004494 memcpy(frame, &rxBuffer.buffer[rxBuffer.tail], sizeof(EDCAN_RxFrame_t)); 8004446: 4b16 ldr r3, [pc, #88] ; (80044a0 ) 8004448: f8b3 3d02 ldrh.w r3, [r3, #3330] ; 0xd02 800444c: 461a mov r2, r3 800444e: 4613 mov r3, r2 8004450: 005b lsls r3, r3, #1 8004452: 4413 add r3, r2 8004454: 009b lsls r3, r3, #2 8004456: 4413 add r3, r2 8004458: 4a11 ldr r2, [pc, #68] ; (80044a0 ) 800445a: 4413 add r3, r2 800445c: 220d movs r2, #13 800445e: 4619 mov r1, r3 8004460: 6878 ldr r0, [r7, #4] 8004462: f004 fec5 bl 80091f0 rxBuffer.tail = (rxBuffer.tail + 1) % BUFFER_SIZE; 8004466: 4b0e ldr r3, [pc, #56] ; (80044a0 ) 8004468: f8b3 3d02 ldrh.w r3, [r3, #3330] ; 0xd02 800446c: 3301 adds r3, #1 800446e: 425a negs r2, r3 8004470: b2db uxtb r3, r3 8004472: b2d2 uxtb r2, r2 8004474: bf58 it pl 8004476: 4253 negpl r3, r2 8004478: b29a uxth r2, r3 800447a: 4b09 ldr r3, [pc, #36] ; (80044a0 ) 800447c: f8a3 2d02 strh.w r2, [r3, #3330] ; 0xd02 rxBuffer.count--; 8004480: 4b07 ldr r3, [pc, #28] ; (80044a0 ) 8004482: f8b3 3d04 ldrh.w r3, [r3, #3332] ; 0xd04 8004486: 3b01 subs r3, #1 8004488: b29a uxth r2, r3 800448a: 4b05 ldr r3, [pc, #20] ; (80044a0 ) 800448c: f8a3 2d04 strh.w r2, [r3, #3332] ; 0xd04 return true; 8004490: 2301 movs r3, #1 8004492: e000 b.n 8004496 } else { // Буфер пуст, можно добавить обработку ошибки return false; 8004494: 2300 movs r3, #0 } } 8004496: 4618 mov r0, r3 8004498: 3708 adds r7, #8 800449a: 46bd mov sp, r7 800449c: bd80 pop {r7, pc} 800449e: bf00 nop 80044a0: 20002620 .word 0x20002620 080044a4 : //Количество элементов в буфере uint16_t EDCAN_getRxBufferElementCount() { 80044a4: b480 push {r7} 80044a6: af00 add r7, sp, #0 return rxBuffer.count; 80044a8: 4b03 ldr r3, [pc, #12] ; (80044b8 ) 80044aa: f8b3 3d04 ldrh.w r3, [r3, #3332] ; 0xd04 } 80044ae: 4618 mov r0, r3 80044b0: 46bd mov sp, r7 80044b2: bc80 pop {r7} 80044b4: 4770 bx lr 80044b6: bf00 nop 80044b8: 20002620 .word 0x20002620 080044bc : return false; } } //Функция для обработки входящих пакетов из буфера void EDCAN_ExchangeRxBuffer(){ 80044bc: b590 push {r4, r7, lr} 80044be: b087 sub sp, #28 80044c0: af02 add r7, sp, #8 __ASM volatile ("cpsid i" : : : "memory"); 80044c2: b672 cpsid i } 80044c4: bf00 nop EDCAN_RxFrame_t Rxframe; __disable_irq(); if(EDCAN_getRxBufferElementCount()>0){ 80044c6: f7ff ffed bl 80044a4 80044ca: 4603 mov r3, r0 80044cc: 2b00 cmp r3, #0 80044ce: d040 beq.n 8004552 if (EDCAN_RxBufferGet(&Rxframe)){ 80044d0: 463b mov r3, r7 80044d2: 4618 mov r0, r3 80044d4: f7ff ffae bl 8004434 80044d8: 4603 mov r3, r0 80044da: 2b00 cmp r3, #0 80044dc: d039 beq.n 8004552 if(Rxframe.ExtID.PacketType == ED_WRITE){ 80044de: 78fb ldrb r3, [r7, #3] 80044e0: f003 0318 and.w r3, r3, #24 80044e4: b2db uxtb r3, r3 80044e6: 2b00 cmp r3, #0 80044e8: d10e bne.n 8004508 EDCAN_WriteHandler(Rxframe.ExtID.SourceID, Rxframe.ExtID.DestinationID, Rxframe.ExtID.RegisterAddress, Rxframe.data, Rxframe.DLC); 80044ea: 7878 ldrb r0, [r7, #1] 80044ec: 7839 ldrb r1, [r7, #0] 80044ee: 887b ldrh r3, [r7, #2] 80044f0: f3c3 030a ubfx r3, r3, #0, #11 80044f4: b29b uxth r3, r3 80044f6: 461c mov r4, r3 80044f8: 7b3b ldrb r3, [r7, #12] 80044fa: 463a mov r2, r7 80044fc: 3204 adds r2, #4 80044fe: 9300 str r3, [sp, #0] 8004500: 4613 mov r3, r2 8004502: 4622 mov r2, r4 8004504: f000 f82b bl 800455e } if(Rxframe.ExtID.PacketType == ED_READREQ){ 8004508: 78fb ldrb r3, [r7, #3] 800450a: f003 0318 and.w r3, r3, #24 800450e: b2db uxtb r3, r3 8004510: 2b08 cmp r3, #8 8004512: d109 bne.n 8004528 EDCAN_ReadRequestHandler(Rxframe.ExtID.SourceID, Rxframe.ExtID.DestinationID, Rxframe.ExtID.RegisterAddress, Rxframe.data[0]); 8004514: 7878 ldrb r0, [r7, #1] 8004516: 7839 ldrb r1, [r7, #0] 8004518: 887b ldrh r3, [r7, #2] 800451a: f3c3 030a ubfx r3, r3, #0, #11 800451e: b29b uxth r3, r3 8004520: 461a mov r2, r3 8004522: 793b ldrb r3, [r7, #4] 8004524: f000 f8f3 bl 800470e } if(Rxframe.ExtID.PacketType == ED_READ){ 8004528: 78fb ldrb r3, [r7, #3] 800452a: f003 0318 and.w r3, r3, #24 800452e: b2db uxtb r3, r3 8004530: 2b10 cmp r3, #16 8004532: d10e bne.n 8004552 EDCAN_ReadHandler(Rxframe.ExtID.SourceID, Rxframe.ExtID.DestinationID, Rxframe.ExtID.RegisterAddress, Rxframe.data, Rxframe.DLC); 8004534: 7878 ldrb r0, [r7, #1] 8004536: 7839 ldrb r1, [r7, #0] 8004538: 887b ldrh r3, [r7, #2] 800453a: f3c3 030a ubfx r3, r3, #0, #11 800453e: b29b uxth r3, r3 8004540: 461c mov r4, r3 8004542: 7b3b ldrb r3, [r7, #12] 8004544: 463a mov r2, r7 8004546: 3204 adds r2, #4 8004548: 9300 str r3, [sp, #0] 800454a: 4613 mov r3, r2 800454c: 4622 mov r2, r4 800454e: f7fe fd6b bl 8003028 __ASM volatile ("cpsie i" : : : "memory"); 8004552: b662 cpsie i } 8004554: bf00 nop } } } __enable_irq(); } 8004556: bf00 nop 8004558: 3714 adds r7, #20 800455a: 46bd mov sp, r7 800455c: bd90 pop {r4, r7, pc} 0800455e : * DestinationID: Packet Destination ID * Addr: First register address in sequence * *data: pointer for data array * len: length of data (1..255) */ void EDCAN_WriteHandler(uint8_t SourceID, uint8_t DestinationID, uint16_t Addr, uint8_t *data, uint8_t len){ 800455e: b580 push {r7, lr} 8004560: b084 sub sp, #16 8004562: af00 add r7, sp, #0 8004564: 603b str r3, [r7, #0] 8004566: 4603 mov r3, r0 8004568: 71fb strb r3, [r7, #7] 800456a: 460b mov r3, r1 800456c: 71bb strb r3, [r7, #6] 800456e: 4613 mov r3, r2 8004570: 80bb strh r3, [r7, #4] // printf("Destination ID = %d\n", DestinationID); // printf("Address = %d\n", Addr); // printf("Len = %d\n", len); // printf("\n"); for (uint16_t AddrOffset = 0; AddrOffset < len; AddrOffset++){ //по очереди перебираем все полученные регистры через Handler 8004572: 2300 movs r3, #0 8004574: 81fb strh r3, [r7, #14] 8004576: e01e b.n 80045b6 // printf ("register[%d] = %d\n", Addr+AddrOffset, data[AddrOffset]); if((Addr+AddrOffset)>=256){ 8004578: 88ba ldrh r2, [r7, #4] 800457a: 89fb ldrh r3, [r7, #14] 800457c: 4413 add r3, r2 800457e: 2bff cmp r3, #255 ; 0xff 8004580: dd0b ble.n 800459a EDCAN_WriteUserRegister(Addr+AddrOffset, data[AddrOffset]); 8004582: 88ba ldrh r2, [r7, #4] 8004584: 89fb ldrh r3, [r7, #14] 8004586: 4413 add r3, r2 8004588: b298 uxth r0, r3 800458a: 89fb ldrh r3, [r7, #14] 800458c: 683a ldr r2, [r7, #0] 800458e: 4413 add r3, r2 8004590: 781b ldrb r3, [r3, #0] 8004592: 4619 mov r1, r3 8004594: f7fe fd64 bl 8003060 8004598: e00a b.n 80045b0 }else{ EDCAN_WriteSystemRegister(Addr+AddrOffset, data[AddrOffset]); 800459a: 88ba ldrh r2, [r7, #4] 800459c: 89fb ldrh r3, [r7, #14] 800459e: 4413 add r3, r2 80045a0: b298 uxth r0, r3 80045a2: 89fb ldrh r3, [r7, #14] 80045a4: 683a ldr r2, [r7, #0] 80045a6: 4413 add r3, r2 80045a8: 781b ldrb r3, [r3, #0] 80045aa: 4619 mov r1, r3 80045ac: f000 f80e bl 80045cc for (uint16_t AddrOffset = 0; AddrOffset < len; AddrOffset++){ //по очереди перебираем все полученные регистры через Handler 80045b0: 89fb ldrh r3, [r7, #14] 80045b2: 3301 adds r3, #1 80045b4: 81fb strh r3, [r7, #14] 80045b6: 7e3b ldrb r3, [r7, #24] 80045b8: b29b uxth r3, r3 80045ba: 89fa ldrh r2, [r7, #14] 80045bc: 429a cmp r2, r3 80045be: d3db bcc.n 8004578 } } } 80045c0: bf00 nop 80045c2: bf00 nop 80045c4: 3710 adds r7, #16 80045c6: 46bd mov sp, r7 80045c8: bd80 pop {r7, pc} ... 080045cc : void EDCAN_WriteSystemRegister(uint16_t addr, uint8_t value){ 80045cc: b580 push {r7, lr} 80045ce: b082 sub sp, #8 80045d0: af00 add r7, sp, #0 80045d2: 4603 mov r3, r0 80045d4: 460a mov r2, r1 80045d6: 80fb strh r3, [r7, #6] 80045d8: 4613 mov r3, r2 80045da: 717b strb r3, [r7, #5] switch(addr){ 80045dc: 88fb ldrh r3, [r7, #6] 80045de: 2b00 cmp r3, #0 80045e0: d002 beq.n 80045e8 80045e2: 2b20 cmp r3, #32 80045e4: d00b beq.n 80045fe // break; //default: // printf ("Unknown register\n"); } } 80045e6: e010 b.n 800460a if(value == 0x10){ 80045e8: 797b ldrb r3, [r7, #5] 80045ea: 2b10 cmp r3, #16 80045ec: d10c bne.n 8004608 if(ED_status==0)ED_status = 0x10; 80045ee: 4b09 ldr r3, [pc, #36] ; (8004614 ) 80045f0: 781b ldrb r3, [r3, #0] 80045f2: 2b00 cmp r3, #0 80045f4: d108 bne.n 8004608 80045f6: 4b07 ldr r3, [pc, #28] ; (8004614 ) 80045f8: 2210 movs r2, #16 80045fa: 701a strb r2, [r3, #0] break; 80045fc: e004 b.n 8004608 EDCAN_EnterSilentMode(value); 80045fe: 797b ldrb r3, [r7, #5] 8004600: 4618 mov r0, r3 8004602: f7ff fd8d bl 8004120 break; 8004606: e000 b.n 800460a break; 8004608: bf00 nop } 800460a: bf00 nop 800460c: 3708 adds r7, #8 800460e: 46bd mov sp, r7 8004610: bd80 pop {r7, pc} 8004612: bf00 nop 8004614: 20003326 .word 0x20003326 08004618 : * @brief Handler to get System register values (0..255) * * @param addr: register address * @retval register value (uint8_t) */ uint8_t EDCAN_GetSystemRegisterValue(uint16_t addr){ 8004618: b580 push {r7, lr} 800461a: b082 sub sp, #8 800461c: af00 add r7, sp, #0 800461e: 4603 mov r3, r0 8004620: 80fb strh r3, [r7, #6] static uint32_t uptime_buffer; switch (addr){ 8004622: 88fb ldrh r3, [r7, #6] 8004624: 2b17 cmp r3, #23 8004626: d852 bhi.n 80046ce 8004628: a201 add r2, pc, #4 ; (adr r2, 8004630 ) 800462a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800462e: bf00 nop 8004630: 08004691 .word 0x08004691 8004634: 0800469b .word 0x0800469b 8004638: 08004697 .word 0x08004697 800463c: 080046cf .word 0x080046cf 8004640: 080046cf .word 0x080046cf 8004644: 080046cf .word 0x080046cf 8004648: 080046cf .word 0x080046cf 800464c: 080046cf .word 0x080046cf 8004650: 080046cf .word 0x080046cf 8004654: 080046cf .word 0x080046cf 8004658: 080046cf .word 0x080046cf 800465c: 080046cf .word 0x080046cf 8004660: 080046cf .word 0x080046cf 8004664: 080046cf .word 0x080046cf 8004668: 080046cf .word 0x080046cf 800466c: 080046cf .word 0x080046cf 8004670: 080046cf .word 0x080046cf 8004674: 080046cf .word 0x080046cf 8004678: 080046cf .word 0x080046cf 800467c: 080046cf .word 0x080046cf 8004680: 0800469f .word 0x0800469f 8004684: 080046b1 .word 0x080046b1 8004688: 080046bb .word 0x080046bb 800468c: 080046c5 .word 0x080046c5 /* регистры 0..255 используются для Системных регистров*/ case EDCAN_REG_SYS_STATUS: return ED_status; 8004690: 4b11 ldr r3, [pc, #68] ; (80046d8 ) 8004692: 781b ldrb r3, [r3, #0] 8004694: e01c b.n 80046d0 break; case EDCAN_REG_SYS_FWVER: return FWVER; 8004696: 2301 movs r3, #1 8004698: e01a b.n 80046d0 break; case EDCAN_REG_SYS_DEVICEID: return DEVICE_ID; 800469a: 2320 movs r3, #32 800469c: e018 b.n 80046d0 break; case EDCAN_REG_SYS_UPTIME0: uptime_buffer = HAL_GetTick(); 800469e: f000 fd79 bl 8005194 80046a2: 4603 mov r3, r0 80046a4: 4a0d ldr r2, [pc, #52] ; (80046dc ) 80046a6: 6013 str r3, [r2, #0] return uptime_buffer & 0xFF; 80046a8: 4b0c ldr r3, [pc, #48] ; (80046dc ) 80046aa: 681b ldr r3, [r3, #0] 80046ac: b2db uxtb r3, r3 80046ae: e00f b.n 80046d0 break; case EDCAN_REG_SYS_UPTIME1: return (uptime_buffer>>8) & 0xFF; 80046b0: 4b0a ldr r3, [pc, #40] ; (80046dc ) 80046b2: 681b ldr r3, [r3, #0] 80046b4: 0a1b lsrs r3, r3, #8 80046b6: b2db uxtb r3, r3 80046b8: e00a b.n 80046d0 break; case EDCAN_REG_SYS_UPTIME2: return (uptime_buffer>>16) & 0xFF; 80046ba: 4b08 ldr r3, [pc, #32] ; (80046dc ) 80046bc: 681b ldr r3, [r3, #0] 80046be: 0c1b lsrs r3, r3, #16 80046c0: b2db uxtb r3, r3 80046c2: e005 b.n 80046d0 break; case EDCAN_REG_SYS_UPTIME3: return (uptime_buffer>>24) & 0xFF; 80046c4: 4b05 ldr r3, [pc, #20] ; (80046dc ) 80046c6: 681b ldr r3, [r3, #0] 80046c8: 0e1b lsrs r3, r3, #24 80046ca: b2db uxtb r3, r3 80046cc: e000 b.n 80046d0 break; default: return 0x00; 80046ce: 2300 movs r3, #0 } } 80046d0: 4618 mov r0, r3 80046d2: 3708 adds r7, #8 80046d4: 46bd mov sp, r7 80046d6: bd80 pop {r7, pc} 80046d8: 20003326 .word 0x20003326 80046dc: 20003328 .word 0x20003328 080046e0 : * @brief Handler to get own register values * * @param addr: register address * @retval register value (uint8_t) */ uint8_t EDCAN_GetOwnRegisterValue (uint16_t addr){ 80046e0: b580 push {r7, lr} 80046e2: b082 sub sp, #8 80046e4: af00 add r7, sp, #0 80046e6: 4603 mov r3, r0 80046e8: 80fb strh r3, [r7, #6] if(addr<256){ 80046ea: 88fb ldrh r3, [r7, #6] 80046ec: 2bff cmp r3, #255 ; 0xff 80046ee: d805 bhi.n 80046fc return EDCAN_GetSystemRegisterValue(addr); // 0..255 80046f0: 88fb ldrh r3, [r7, #6] 80046f2: 4618 mov r0, r3 80046f4: f7ff ff90 bl 8004618 80046f8: 4603 mov r3, r0 80046fa: e004 b.n 8004706 }else { return EDCAN_GetUserRegisterValue(addr); // 256..2047 80046fc: 88fb ldrh r3, [r7, #6] 80046fe: 4618 mov r0, r3 8004700: f7fe fd5e bl 80031c0 8004704: 4603 mov r3, r0 } } 8004706: 4618 mov r0, r3 8004708: 3708 adds r7, #8 800470a: 46bd mov sp, r7 800470c: bd80 pop {r7, pc} 0800470e : * DestinationID: Packet Destination ID * Addr: First register address in sequence * *data: pointer for data array * len: length of data (1..255) */ void EDCAN_ReadRequestHandler(uint8_t SourceID, uint8_t DestinationID, uint16_t Addr, uint8_t len){ 800470e: b590 push {r4, r7, lr} 8004710: b087 sub sp, #28 8004712: af00 add r7, sp, #0 8004714: 4604 mov r4, r0 8004716: 4608 mov r0, r1 8004718: 4611 mov r1, r2 800471a: 461a mov r2, r3 800471c: 4623 mov r3, r4 800471e: 71fb strb r3, [r7, #7] 8004720: 4603 mov r3, r0 8004722: 71bb strb r3, [r7, #6] 8004724: 460b mov r3, r1 8004726: 80bb strh r3, [r7, #4] 8004728: 4613 mov r3, r2 800472a: 70fb strb r3, [r7, #3] //Получили пакет Read (запрошенное значение регистров) uint8_t TxData[8]; uint16_t AddrOffset = Addr; 800472c: 88bb ldrh r3, [r7, #4] 800472e: 82fb strh r3, [r7, #22] // printf("Destination ID = %d\n", DestinationID); // printf("Address = %d\n", Addr); // printf("Len = %d\n", len); // printf("\n"); while (len>0){ //по очереди перебираем все полученные регистры через Handler 8004730: e051 b.n 80047d6 if(len>=8){ //если количество регистров больше 8, отправляем 8 и разбиваем на несколько пакетов 8004732: 78fb ldrb r3, [r7, #3] 8004734: 2b07 cmp r3, #7 8004736: d926 bls.n 8004786 for(uint8_t n = 0; n < 8; n++){ 8004738: 2300 movs r3, #0 800473a: 757b strb r3, [r7, #21] 800473c: e012 b.n 8004764 TxData[n] = EDCAN_GetOwnRegisterValue(n+AddrOffset); 800473e: 7d7b ldrb r3, [r7, #21] 8004740: b29a uxth r2, r3 8004742: 8afb ldrh r3, [r7, #22] 8004744: 4413 add r3, r2 8004746: b29b uxth r3, r3 8004748: 7d7c ldrb r4, [r7, #21] 800474a: 4618 mov r0, r3 800474c: f7ff ffc8 bl 80046e0 8004750: 4603 mov r3, r0 8004752: 461a mov r2, r3 8004754: f104 0318 add.w r3, r4, #24 8004758: 443b add r3, r7 800475a: f803 2c0c strb.w r2, [r3, #-12] for(uint8_t n = 0; n < 8; n++){ 800475e: 7d7b ldrb r3, [r7, #21] 8004760: 3301 adds r3, #1 8004762: 757b strb r3, [r7, #21] 8004764: 7d7b ldrb r3, [r7, #21] 8004766: 2b07 cmp r3, #7 8004768: d9e9 bls.n 800473e //printf ("register[%d] = %d\n", n+AddrOffset, TxData[n]); } EDCAN_SendPacketRead(SourceID, AddrOffset, TxData, 8); /* отправляем ответный пакет со значениями собственных регистров */ 800476a: f107 020c add.w r2, r7, #12 800476e: 8af9 ldrh r1, [r7, #22] 8004770: 79f8 ldrb r0, [r7, #7] 8004772: 2308 movs r3, #8 8004774: f7ff fc38 bl 8003fe8 //printf ("sent%d, %d\n", AddrOffset, len); AddrOffset +=8; 8004778: 8afb ldrh r3, [r7, #22] 800477a: 3308 adds r3, #8 800477c: 82fb strh r3, [r7, #22] len -=8; 800477e: 78fb ldrb r3, [r7, #3] 8004780: 3b08 subs r3, #8 8004782: 70fb strb r3, [r7, #3] 8004784: e027 b.n 80047d6 }else{ for(uint8_t n = 0; n < len; n++){ 8004786: 2300 movs r3, #0 8004788: 753b strb r3, [r7, #20] 800478a: e012 b.n 80047b2 TxData[n] = EDCAN_GetOwnRegisterValue(n+AddrOffset); 800478c: 7d3b ldrb r3, [r7, #20] 800478e: b29a uxth r2, r3 8004790: 8afb ldrh r3, [r7, #22] 8004792: 4413 add r3, r2 8004794: b29b uxth r3, r3 8004796: 7d3c ldrb r4, [r7, #20] 8004798: 4618 mov r0, r3 800479a: f7ff ffa1 bl 80046e0 800479e: 4603 mov r3, r0 80047a0: 461a mov r2, r3 80047a2: f104 0318 add.w r3, r4, #24 80047a6: 443b add r3, r7 80047a8: f803 2c0c strb.w r2, [r3, #-12] for(uint8_t n = 0; n < len; n++){ 80047ac: 7d3b ldrb r3, [r7, #20] 80047ae: 3301 adds r3, #1 80047b0: 753b strb r3, [r7, #20] 80047b2: 7d3a ldrb r2, [r7, #20] 80047b4: 78fb ldrb r3, [r7, #3] 80047b6: 429a cmp r2, r3 80047b8: d3e8 bcc.n 800478c //printf ("register[%d] = %d\n", n+AddrOffset, TxData[n]); } EDCAN_SendPacketRead(SourceID, AddrOffset, TxData, len); /* отправляем ответный пакет со значениями собственных регистров */ 80047ba: 78fb ldrb r3, [r7, #3] 80047bc: f107 020c add.w r2, r7, #12 80047c0: 8af9 ldrh r1, [r7, #22] 80047c2: 79f8 ldrb r0, [r7, #7] 80047c4: f7ff fc10 bl 8003fe8 //printf ("sent%d, %d\n", AddrOffset, len); AddrOffset +=len; 80047c8: 78fb ldrb r3, [r7, #3] 80047ca: b29a uxth r2, r3 80047cc: 8afb ldrh r3, [r7, #22] 80047ce: 4413 add r3, r2 80047d0: 82fb strh r3, [r7, #22] len = 0; 80047d2: 2300 movs r3, #0 80047d4: 70fb strb r3, [r7, #3] while (len>0){ //по очереди перебираем все полученные регистры через Handler 80047d6: 78fb ldrb r3, [r7, #3] 80047d8: 2b00 cmp r3, #0 80047da: d1aa bne.n 8004732 } } // printf("\n"); } 80047dc: bf00 nop 80047de: bf00 nop 80047e0: 371c adds r7, #28 80047e2: 46bd mov sp, r7 80047e4: bd90 pop {r4, r7, pc} ... 080047e8
: /** * @brief The application entry point. * @retval int */ int main(void) { 80047e8: b580 push {r7, lr} 80047ea: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80047ec: f000 fc7a bl 80050e4 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80047f0: f000 f83c bl 800486c /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80047f4: f7fe fefa bl 80035ec MX_ADC1_Init(); 80047f8: f7fc feda bl 80015b0 MX_CAN1_Init(); 80047fc: f7fd f890 bl 8001920 MX_CAN2_Init(); 8004800: f7fd f8c4 bl 800198c MX_USART2_UART_Init(); 8004804: f000 fbbc bl 8004f80 MX_RTC_Init(); 8004808: f000 f8a6 bl 8004958 /* USER CODE BEGIN 2 */ CAN_ReInit(); 800480c: f7ff fb5e bl 8003ecc Init_Peripheral(); 8004810: f7fc ff84 bl 800171c HAL_Delay(300); 8004814: f44f 7096 mov.w r0, #300 ; 0x12c 8004818: f000 fcc6 bl 80051a8 GBT_Init(); 800481c: f7fd f9ca bl 8001bb4 set_Time(1721651966); //2024-07-22T12:39:26+00:00 8004820: 4810 ldr r0, [pc, #64] ; (8004864 ) 8004822: f000 f8e3 bl 80049ec printf("Startup (type \'help\' for command list)\n"); 8004826: 4810 ldr r0, [pc, #64] ; (8004868 ) 8004828: f005 faba bl 8009da0 debug_init(); 800482c: f7fe f860 bl 80028f0 EDCAN_Init(SW_GetAddr()); //0x20..0x23 8004830: f7fd f850 bl 80018d4 8004834: 4603 mov r3, r0 8004836: 4618 mov r0, r3 8004838: f7ff fb38 bl 8003eac //EDCAN_Init(0x20); //Адрес EDCAN GBT_CAN_ReInit(); 800483c: f7ff f8c0 bl 80039c0 CAN_ReInit(); 8004840: f7ff fb44 bl 8003ecc CONN_Init(); 8004844: f7fd fe39 bl 80024ba { /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ // HAL_Delay(1); EDCAN_Loop(); 8004848: f7ff fc08 bl 800405c //can_task(); debug_task(); 800484c: f7fe fbce bl 8002fec CONN_CC_ReadStateFiltered(); 8004850: f7fd ff02 bl 8002658 GBT_ManageLock(); 8004854: f7ff fa1c bl 8003c90 CONN_Task(); 8004858: f7fd fe36 bl 80024c8 GBT_ChargerTask(); 800485c: f7fd f9b6 bl 8001bcc { 8004860: e7f2 b.n 8004848 8004862: bf00 nop 8004864: 669e52fe .word 0x669e52fe 8004868: 0800d220 .word 0x0800d220 0800486c : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800486c: b580 push {r7, lr} 800486e: b09c sub sp, #112 ; 0x70 8004870: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8004872: f107 0338 add.w r3, r7, #56 ; 0x38 8004876: 2238 movs r2, #56 ; 0x38 8004878: 2100 movs r1, #0 800487a: 4618 mov r0, r3 800487c: f004 fcc6 bl 800920c RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8004880: f107 0324 add.w r3, r7, #36 ; 0x24 8004884: 2200 movs r2, #0 8004886: 601a str r2, [r3, #0] 8004888: 605a str r2, [r3, #4] 800488a: 609a str r2, [r3, #8] 800488c: 60da str r2, [r3, #12] 800488e: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8004890: 1d3b adds r3, r7, #4 8004892: 2220 movs r2, #32 8004894: 2100 movs r1, #0 8004896: 4618 mov r0, r3 8004898: f004 fcb8 bl 800920c /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; 800489c: 2305 movs r3, #5 800489e: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 80048a0: f44f 3380 mov.w r3, #65536 ; 0x10000 80048a4: 643b str r3, [r7, #64] ; 0x40 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV5; 80048a6: 2304 movs r3, #4 80048a8: 647b str r3, [r7, #68] ; 0x44 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 80048aa: 2301 movs r3, #1 80048ac: 64bb str r3, [r7, #72] ; 0x48 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 80048ae: 2301 movs r3, #1 80048b0: 64fb str r3, [r7, #76] ; 0x4c RCC_OscInitStruct.Prediv1Source = RCC_PREDIV1_SOURCE_PLL2; 80048b2: f44f 3380 mov.w r3, #65536 ; 0x10000 80048b6: 63fb str r3, [r7, #60] ; 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80048b8: 2302 movs r3, #2 80048ba: 65bb str r3, [r7, #88] ; 0x58 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 80048bc: f44f 3380 mov.w r3, #65536 ; 0x10000 80048c0: 65fb str r3, [r7, #92] ; 0x5c RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 80048c2: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000 80048c6: 663b str r3, [r7, #96] ; 0x60 RCC_OscInitStruct.PLL2.PLL2State = RCC_PLL2_ON; 80048c8: 2302 movs r3, #2 80048ca: 667b str r3, [r7, #100] ; 0x64 RCC_OscInitStruct.PLL2.PLL2MUL = RCC_PLL2_MUL8; 80048cc: f44f 63c0 mov.w r3, #1536 ; 0x600 80048d0: 66bb str r3, [r7, #104] ; 0x68 RCC_OscInitStruct.PLL2.HSEPrediv2Value = RCC_HSE_PREDIV2_DIV5; 80048d2: 2340 movs r3, #64 ; 0x40 80048d4: 66fb str r3, [r7, #108] ; 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80048d6: f107 0338 add.w r3, r7, #56 ; 0x38 80048da: 4618 mov r0, r3 80048dc: f002 fc48 bl 8007170 80048e0: 4603 mov r3, r0 80048e2: 2b00 cmp r3, #0 80048e4: d001 beq.n 80048ea { Error_Handler(); 80048e6: f000 f831 bl 800494c } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80048ea: 230f movs r3, #15 80048ec: 627b str r3, [r7, #36] ; 0x24 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80048ee: 2302 movs r3, #2 80048f0: 62bb str r3, [r7, #40] ; 0x28 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80048f2: 2300 movs r3, #0 80048f4: 62fb str r3, [r7, #44] ; 0x2c RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 80048f6: f44f 6380 mov.w r3, #1024 ; 0x400 80048fa: 633b str r3, [r7, #48] ; 0x30 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80048fc: 2300 movs r3, #0 80048fe: 637b str r3, [r7, #52] ; 0x34 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8004900: f107 0324 add.w r3, r7, #36 ; 0x24 8004904: 2102 movs r1, #2 8004906: 4618 mov r0, r3 8004908: f002 ff48 bl 800779c 800490c: 4603 mov r3, r0 800490e: 2b00 cmp r3, #0 8004910: d001 beq.n 8004916 { Error_Handler(); 8004912: f000 f81b bl 800494c } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; 8004916: 2303 movs r3, #3 8004918: 607b str r3, [r7, #4] PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 800491a: f44f 7380 mov.w r3, #256 ; 0x100 800491e: 60bb str r3, [r7, #8] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 8004920: f44f 4300 mov.w r3, #32768 ; 0x8000 8004924: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8004926: 1d3b adds r3, r7, #4 8004928: 4618 mov r0, r3 800492a: f003 f94f bl 8007bcc 800492e: 4603 mov r3, r0 8004930: 2b00 cmp r3, #0 8004932: d001 beq.n 8004938 { Error_Handler(); 8004934: f000 f80a bl 800494c } /** Configure the Systick interrupt time */ __HAL_RCC_PLLI2S_ENABLE(); 8004938: 4b03 ldr r3, [pc, #12] ; (8004948 ) 800493a: 2201 movs r2, #1 800493c: 601a str r2, [r3, #0] } 800493e: bf00 nop 8004940: 3770 adds r7, #112 ; 0x70 8004942: 46bd mov sp, r7 8004944: bd80 pop {r7, pc} 8004946: bf00 nop 8004948: 42420070 .word 0x42420070 0800494c : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800494c: b480 push {r7} 800494e: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 8004950: b672 cpsid i } 8004952: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8004954: e7fe b.n 8004954 ... 08004958 : RTC_HandleTypeDef hrtc; /* RTC init function */ void MX_RTC_Init(void) { 8004958: b580 push {r7, lr} 800495a: af00 add r7, sp, #0 /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 800495c: 4b0a ldr r3, [pc, #40] ; (8004988 ) 800495e: 4a0b ldr r2, [pc, #44] ; (800498c ) 8004960: 601a str r2, [r3, #0] hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; 8004962: 4b09 ldr r3, [pc, #36] ; (8004988 ) 8004964: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 8004968: 605a str r2, [r3, #4] hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; 800496a: 4b07 ldr r3, [pc, #28] ; (8004988 ) 800496c: f44f 7280 mov.w r2, #256 ; 0x100 8004970: 609a str r2, [r3, #8] if (HAL_RTC_Init(&hrtc) != HAL_OK) 8004972: 4805 ldr r0, [pc, #20] ; (8004988 ) 8004974: f003 fbbe bl 80080f4 8004978: 4603 mov r3, r0 800497a: 2b00 cmp r3, #0 800497c: d001 beq.n 8004982 { Error_Handler(); 800497e: f7ff ffe5 bl 800494c } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 8004982: bf00 nop 8004984: bd80 pop {r7, pc} 8004986: bf00 nop 8004988: 2000332c .word 0x2000332c 800498c: 40002800 .word 0x40002800 08004990 : void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) { 8004990: b580 push {r7, lr} 8004992: b084 sub sp, #16 8004994: af00 add r7, sp, #0 8004996: 6078 str r0, [r7, #4] if(rtcHandle->Instance==RTC) 8004998: 687b ldr r3, [r7, #4] 800499a: 681b ldr r3, [r3, #0] 800499c: 4a0b ldr r2, [pc, #44] ; (80049cc ) 800499e: 4293 cmp r3, r2 80049a0: d110 bne.n 80049c4 { /* USER CODE BEGIN RTC_MspInit 0 */ /* USER CODE END RTC_MspInit 0 */ HAL_PWR_EnableBkUpAccess(); 80049a2: f002 fbd9 bl 8007158 /* Enable BKP CLK enable for backup registers */ __HAL_RCC_BKP_CLK_ENABLE(); 80049a6: 4b0a ldr r3, [pc, #40] ; (80049d0 ) 80049a8: 69db ldr r3, [r3, #28] 80049aa: 4a09 ldr r2, [pc, #36] ; (80049d0 ) 80049ac: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000 80049b0: 61d3 str r3, [r2, #28] 80049b2: 4b07 ldr r3, [pc, #28] ; (80049d0 ) 80049b4: 69db ldr r3, [r3, #28] 80049b6: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 80049ba: 60fb str r3, [r7, #12] 80049bc: 68fb ldr r3, [r7, #12] /* RTC clock enable */ __HAL_RCC_RTC_ENABLE(); 80049be: 4b05 ldr r3, [pc, #20] ; (80049d4 ) 80049c0: 2201 movs r2, #1 80049c2: 601a str r2, [r3, #0] /* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE END RTC_MspInit 1 */ } } 80049c4: bf00 nop 80049c6: 3710 adds r7, #16 80049c8: 46bd mov sp, r7 80049ca: bd80 pop {r7, pc} 80049cc: 40002800 .word 0x40002800 80049d0: 40021000 .word 0x40021000 80049d4: 4242043c .word 0x4242043c 080049d8 : static uint32_t RTC1_ReadTimeCounter(RTC_HandleTypeDef *hrtc); static HAL_StatusTypeDef RTC1_ExitInitMode(RTC_HandleTypeDef *hrtc); static HAL_StatusTypeDef RTC1_EnterInitMode(RTC_HandleTypeDef *hrtc); uint32_t get_Current_Time(){ 80049d8: b580 push {r7, lr} 80049da: af00 add r7, sp, #0 return RTC1_ReadTimeCounter(&hrtc); 80049dc: 4802 ldr r0, [pc, #8] ; (80049e8 ) 80049de: f000 f8fb bl 8004bd8 80049e2: 4603 mov r3, r0 } 80049e4: 4618 mov r0, r3 80049e6: bd80 pop {r7, pc} 80049e8: 2000332c .word 0x2000332c 080049ec : void set_Time(uint32_t unix_time){ 80049ec: b580 push {r7, lr} 80049ee: b082 sub sp, #8 80049f0: af00 add r7, sp, #0 80049f2: 6078 str r0, [r7, #4] RTC1_WriteTimeCounter(&hrtc, unix_time); 80049f4: 6879 ldr r1, [r7, #4] 80049f6: 4803 ldr r0, [pc, #12] ; (8004a04 ) 80049f8: f000 f91e bl 8004c38 } 80049fc: bf00 nop 80049fe: 3708 adds r7, #8 8004a00: 46bd mov sp, r7 8004a02: bd80 pop {r7, pc} 8004a04: 2000332c .word 0x2000332c 08004a08 : uint8_t to_bcd(int value) { 8004a08: b480 push {r7} 8004a0a: b083 sub sp, #12 8004a0c: af00 add r7, sp, #0 8004a0e: 6078 str r0, [r7, #4] return ((value / 10) << 4) | (value % 10); 8004a10: 687b ldr r3, [r7, #4] 8004a12: 4a0e ldr r2, [pc, #56] ; (8004a4c ) 8004a14: fb82 1203 smull r1, r2, r2, r3 8004a18: 1092 asrs r2, r2, #2 8004a1a: 17db asrs r3, r3, #31 8004a1c: 1ad3 subs r3, r2, r3 8004a1e: 011b lsls r3, r3, #4 8004a20: b258 sxtb r0, r3 8004a22: 687a ldr r2, [r7, #4] 8004a24: 4b09 ldr r3, [pc, #36] ; (8004a4c ) 8004a26: fb83 1302 smull r1, r3, r3, r2 8004a2a: 1099 asrs r1, r3, #2 8004a2c: 17d3 asrs r3, r2, #31 8004a2e: 1ac9 subs r1, r1, r3 8004a30: 460b mov r3, r1 8004a32: 009b lsls r3, r3, #2 8004a34: 440b add r3, r1 8004a36: 005b lsls r3, r3, #1 8004a38: 1ad1 subs r1, r2, r3 8004a3a: b24b sxtb r3, r1 8004a3c: 4303 orrs r3, r0 8004a3e: b25b sxtb r3, r3 8004a40: b2db uxtb r3, r3 } 8004a42: 4618 mov r0, r3 8004a44: 370c adds r7, #12 8004a46: 46bd mov sp, r7 8004a48: bc80 pop {r7} 8004a4a: 4770 bx lr 8004a4c: 66666667 .word 0x66666667 08004a50 : void unix_to_bcd(uint32_t unix_time, uint8_t *time) { 8004a50: b590 push {r4, r7, lr} 8004a52: b087 sub sp, #28 8004a54: af00 add r7, sp, #0 8004a56: 6078 str r0, [r7, #4] 8004a58: 6039 str r1, [r7, #0] struct tm *tm_info; time_t raw_time = (time_t)unix_time; 8004a5a: 6879 ldr r1, [r7, #4] 8004a5c: 2000 movs r0, #0 8004a5e: 460a mov r2, r1 8004a60: 4603 mov r3, r0 8004a62: e9c7 2302 strd r2, r3, [r7, #8] tm_info = gmtime(&raw_time); 8004a66: f107 0308 add.w r3, r7, #8 8004a6a: 4618 mov r0, r3 8004a6c: f004 f9b0 bl 8008dd0 8004a70: 6178 str r0, [r7, #20] time[0] = to_bcd(tm_info->tm_sec); 8004a72: 697b ldr r3, [r7, #20] 8004a74: 681b ldr r3, [r3, #0] 8004a76: 4618 mov r0, r3 8004a78: f7ff ffc6 bl 8004a08 8004a7c: 4603 mov r3, r0 8004a7e: 461a mov r2, r3 8004a80: 683b ldr r3, [r7, #0] 8004a82: 701a strb r2, [r3, #0] time[1] = to_bcd(tm_info->tm_min); 8004a84: 697b ldr r3, [r7, #20] 8004a86: 685a ldr r2, [r3, #4] 8004a88: 683b ldr r3, [r7, #0] 8004a8a: 1c5c adds r4, r3, #1 8004a8c: 4610 mov r0, r2 8004a8e: f7ff ffbb bl 8004a08 8004a92: 4603 mov r3, r0 8004a94: 7023 strb r3, [r4, #0] time[2] = to_bcd(tm_info->tm_hour); 8004a96: 697b ldr r3, [r7, #20] 8004a98: 689a ldr r2, [r3, #8] 8004a9a: 683b ldr r3, [r7, #0] 8004a9c: 1c9c adds r4, r3, #2 8004a9e: 4610 mov r0, r2 8004aa0: f7ff ffb2 bl 8004a08 8004aa4: 4603 mov r3, r0 8004aa6: 7023 strb r3, [r4, #0] time[3] = to_bcd(tm_info->tm_mday); 8004aa8: 697b ldr r3, [r7, #20] 8004aaa: 68da ldr r2, [r3, #12] 8004aac: 683b ldr r3, [r7, #0] 8004aae: 1cdc adds r4, r3, #3 8004ab0: 4610 mov r0, r2 8004ab2: f7ff ffa9 bl 8004a08 8004ab6: 4603 mov r3, r0 8004ab8: 7023 strb r3, [r4, #0] time[4] = to_bcd(tm_info->tm_mon + 1); // tm_mon is 0-11 8004aba: 697b ldr r3, [r7, #20] 8004abc: 691b ldr r3, [r3, #16] 8004abe: 1c5a adds r2, r3, #1 8004ac0: 683b ldr r3, [r7, #0] 8004ac2: 1d1c adds r4, r3, #4 8004ac4: 4610 mov r0, r2 8004ac6: f7ff ff9f bl 8004a08 8004aca: 4603 mov r3, r0 8004acc: 7023 strb r3, [r4, #0] time[5] = to_bcd((tm_info->tm_year + 1900) % 100); // Year in 2 digits 8004ace: 697b ldr r3, [r7, #20] 8004ad0: 695b ldr r3, [r3, #20] 8004ad2: f203 736c addw r3, r3, #1900 ; 0x76c 8004ad6: 4a13 ldr r2, [pc, #76] ; (8004b24 ) 8004ad8: fb82 1203 smull r1, r2, r2, r3 8004adc: 1151 asrs r1, r2, #5 8004ade: 17da asrs r2, r3, #31 8004ae0: 1a8a subs r2, r1, r2 8004ae2: 2164 movs r1, #100 ; 0x64 8004ae4: fb01 f202 mul.w r2, r1, r2 8004ae8: 1a9a subs r2, r3, r2 8004aea: 683b ldr r3, [r7, #0] 8004aec: 1d5c adds r4, r3, #5 8004aee: 4610 mov r0, r2 8004af0: f7ff ff8a bl 8004a08 8004af4: 4603 mov r3, r0 8004af6: 7023 strb r3, [r4, #0] time[6] = to_bcd((tm_info->tm_year + 1900) / 100); // Century in 2 digits 8004af8: 697b ldr r3, [r7, #20] 8004afa: 695b ldr r3, [r3, #20] 8004afc: f203 736c addw r3, r3, #1900 ; 0x76c 8004b00: 4a08 ldr r2, [pc, #32] ; (8004b24 ) 8004b02: fb82 1203 smull r1, r2, r2, r3 8004b06: 1152 asrs r2, r2, #5 8004b08: 17db asrs r3, r3, #31 8004b0a: 1ad2 subs r2, r2, r3 8004b0c: 683b ldr r3, [r7, #0] 8004b0e: 1d9c adds r4, r3, #6 8004b10: 4610 mov r0, r2 8004b12: f7ff ff79 bl 8004a08 8004b16: 4603 mov r3, r0 8004b18: 7023 strb r3, [r4, #0] } 8004b1a: bf00 nop 8004b1c: 371c adds r7, #28 8004b1e: 46bd mov sp, r7 8004b20: bd90 pop {r4, r7, pc} 8004b22: bf00 nop 8004b24: 51eb851f .word 0x51eb851f 08004b28 : void writeTimeReg(uint8_t reg_number, uint8_t value){ 8004b28: b580 push {r7, lr} 8004b2a: b082 sub sp, #8 8004b2c: af00 add r7, sp, #0 8004b2e: 4603 mov r3, r0 8004b30: 460a mov r2, r1 8004b32: 71fb strb r3, [r7, #7] 8004b34: 4613 mov r3, r2 8004b36: 71bb strb r3, [r7, #6] tmp_time[reg_number] = value; 8004b38: 79fb ldrb r3, [r7, #7] 8004b3a: 490e ldr r1, [pc, #56] ; (8004b74 ) 8004b3c: 79ba ldrb r2, [r7, #6] 8004b3e: 54ca strb r2, [r1, r3] if(reg_number == 3) set_Time((tmp_time[0])+(tmp_time[1]<<8)+(tmp_time[2]<<16)+(tmp_time[3]<<24)); 8004b40: 79fb ldrb r3, [r7, #7] 8004b42: 2b03 cmp r3, #3 8004b44: d111 bne.n 8004b6a 8004b46: 4b0b ldr r3, [pc, #44] ; (8004b74 ) 8004b48: 781b ldrb r3, [r3, #0] 8004b4a: 461a mov r2, r3 8004b4c: 4b09 ldr r3, [pc, #36] ; (8004b74 ) 8004b4e: 785b ldrb r3, [r3, #1] 8004b50: 021b lsls r3, r3, #8 8004b52: 441a add r2, r3 8004b54: 4b07 ldr r3, [pc, #28] ; (8004b74 ) 8004b56: 789b ldrb r3, [r3, #2] 8004b58: 041b lsls r3, r3, #16 8004b5a: 441a add r2, r3 8004b5c: 4b05 ldr r3, [pc, #20] ; (8004b74 ) 8004b5e: 78db ldrb r3, [r3, #3] 8004b60: 061b lsls r3, r3, #24 8004b62: 4413 add r3, r2 8004b64: 4618 mov r0, r3 8004b66: f7ff ff41 bl 80049ec }; 8004b6a: bf00 nop 8004b6c: 3708 adds r7, #8 8004b6e: 46bd mov sp, r7 8004b70: bd80 pop {r7, pc} 8004b72: bf00 nop 8004b74: 20003340 .word 0x20003340 08004b78 : uint8_t getTimeReg(uint8_t reg_number){ 8004b78: b580 push {r7, lr} 8004b7a: b082 sub sp, #8 8004b7c: af00 add r7, sp, #0 8004b7e: 4603 mov r3, r0 8004b80: 71fb strb r3, [r7, #7] if(reg_number == 0){ 8004b82: 79fb ldrb r3, [r7, #7] 8004b84: 2b00 cmp r3, #0 8004b86: d108 bne.n 8004b9a tmp_time32 = get_Current_Time(); 8004b88: f7ff ff26 bl 80049d8 8004b8c: 4603 mov r3, r0 8004b8e: 4a11 ldr r2, [pc, #68] ; (8004bd4 ) 8004b90: 6013 str r3, [r2, #0] return tmp_time32 & 0xFF; 8004b92: 4b10 ldr r3, [pc, #64] ; (8004bd4 ) 8004b94: 681b ldr r3, [r3, #0] 8004b96: b2db uxtb r3, r3 8004b98: e018 b.n 8004bcc }else if(reg_number == 1){ 8004b9a: 79fb ldrb r3, [r7, #7] 8004b9c: 2b01 cmp r3, #1 8004b9e: d104 bne.n 8004baa return (tmp_time32>>8) & 0xFF; 8004ba0: 4b0c ldr r3, [pc, #48] ; (8004bd4 ) 8004ba2: 681b ldr r3, [r3, #0] 8004ba4: 0a1b lsrs r3, r3, #8 8004ba6: b2db uxtb r3, r3 8004ba8: e010 b.n 8004bcc }else if(reg_number == 2){ 8004baa: 79fb ldrb r3, [r7, #7] 8004bac: 2b02 cmp r3, #2 8004bae: d104 bne.n 8004bba return (tmp_time32>>16) & 0xFF; 8004bb0: 4b08 ldr r3, [pc, #32] ; (8004bd4 ) 8004bb2: 681b ldr r3, [r3, #0] 8004bb4: 0c1b lsrs r3, r3, #16 8004bb6: b2db uxtb r3, r3 8004bb8: e008 b.n 8004bcc }else if(reg_number == 3){ 8004bba: 79fb ldrb r3, [r7, #7] 8004bbc: 2b03 cmp r3, #3 8004bbe: d104 bne.n 8004bca return (tmp_time32>>24) & 0xFF; 8004bc0: 4b04 ldr r3, [pc, #16] ; (8004bd4 ) 8004bc2: 681b ldr r3, [r3, #0] 8004bc4: 0e1b lsrs r3, r3, #24 8004bc6: b2db uxtb r3, r3 8004bc8: e000 b.n 8004bcc }else{ return 0x00; 8004bca: 2300 movs r3, #0 } }; 8004bcc: 4618 mov r0, r3 8004bce: 3708 adds r7, #8 8004bd0: 46bd mov sp, r7 8004bd2: bd80 pop {r7, pc} 8004bd4: 20003344 .word 0x20003344 08004bd8 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval Time counter */ static uint32_t RTC1_ReadTimeCounter(RTC_HandleTypeDef *hrtc) { 8004bd8: b480 push {r7} 8004bda: b087 sub sp, #28 8004bdc: af00 add r7, sp, #0 8004bde: 6078 str r0, [r7, #4] uint16_t high1 = 0U, high2 = 0U, low = 0U; 8004be0: 2300 movs r3, #0 8004be2: 827b strh r3, [r7, #18] 8004be4: 2300 movs r3, #0 8004be6: 823b strh r3, [r7, #16] 8004be8: 2300 movs r3, #0 8004bea: 81fb strh r3, [r7, #14] uint32_t timecounter = 0U; 8004bec: 2300 movs r3, #0 8004bee: 617b str r3, [r7, #20] high1 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT); 8004bf0: 687b ldr r3, [r7, #4] 8004bf2: 681b ldr r3, [r3, #0] 8004bf4: 699b ldr r3, [r3, #24] 8004bf6: 827b strh r3, [r7, #18] low = READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT); 8004bf8: 687b ldr r3, [r7, #4] 8004bfa: 681b ldr r3, [r3, #0] 8004bfc: 69db ldr r3, [r3, #28] 8004bfe: 81fb strh r3, [r7, #14] high2 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT); 8004c00: 687b ldr r3, [r7, #4] 8004c02: 681b ldr r3, [r3, #0] 8004c04: 699b ldr r3, [r3, #24] 8004c06: 823b strh r3, [r7, #16] if (high1 != high2) 8004c08: 8a7a ldrh r2, [r7, #18] 8004c0a: 8a3b ldrh r3, [r7, #16] 8004c0c: 429a cmp r2, r3 8004c0e: d008 beq.n 8004c22 { /* In this case the counter roll over during reading of CNTL and CNTH registers, read again CNTL register then return the counter value */ timecounter = (((uint32_t) high2 << 16U) | READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT)); 8004c10: 8a3b ldrh r3, [r7, #16] 8004c12: 041a lsls r2, r3, #16 8004c14: 687b ldr r3, [r7, #4] 8004c16: 681b ldr r3, [r3, #0] 8004c18: 69db ldr r3, [r3, #28] 8004c1a: b29b uxth r3, r3 8004c1c: 4313 orrs r3, r2 8004c1e: 617b str r3, [r7, #20] 8004c20: e004 b.n 8004c2c } else { /* No counter roll over during reading of CNTL and CNTH registers, counter value is equal to first value of CNTL and CNTH */ timecounter = (((uint32_t) high1 << 16U) | low); 8004c22: 8a7b ldrh r3, [r7, #18] 8004c24: 041a lsls r2, r3, #16 8004c26: 89fb ldrh r3, [r7, #14] 8004c28: 4313 orrs r3, r2 8004c2a: 617b str r3, [r7, #20] } return timecounter; 8004c2c: 697b ldr r3, [r7, #20] } 8004c2e: 4618 mov r0, r3 8004c30: 371c adds r7, #28 8004c32: 46bd mov sp, r7 8004c34: bc80 pop {r7} 8004c36: 4770 bx lr 08004c38 : * the configuration information for RTC. * @param TimeCounter: Counter to write in RTC_CNT registers * @retval HAL status */ static HAL_StatusTypeDef RTC1_WriteTimeCounter(RTC_HandleTypeDef *hrtc, uint32_t TimeCounter) { 8004c38: b580 push {r7, lr} 8004c3a: b084 sub sp, #16 8004c3c: af00 add r7, sp, #0 8004c3e: 6078 str r0, [r7, #4] 8004c40: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8004c42: 2300 movs r3, #0 8004c44: 73fb strb r3, [r7, #15] /* Set Initialization mode */ if (RTC1_EnterInitMode(hrtc) != HAL_OK) 8004c46: 6878 ldr r0, [r7, #4] 8004c48: f000 f81d bl 8004c86 8004c4c: 4603 mov r3, r0 8004c4e: 2b00 cmp r3, #0 8004c50: d002 beq.n 8004c58 { status = HAL_ERROR; 8004c52: 2301 movs r3, #1 8004c54: 73fb strb r3, [r7, #15] 8004c56: e011 b.n 8004c7c } else { /* Set RTC COUNTER MSB word */ WRITE_REG(hrtc->Instance->CNTH, (TimeCounter >> 16U)); 8004c58: 687b ldr r3, [r7, #4] 8004c5a: 681b ldr r3, [r3, #0] 8004c5c: 683a ldr r2, [r7, #0] 8004c5e: 0c12 lsrs r2, r2, #16 8004c60: 619a str r2, [r3, #24] /* Set RTC COUNTER LSB word */ WRITE_REG(hrtc->Instance->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT)); 8004c62: 687b ldr r3, [r7, #4] 8004c64: 681b ldr r3, [r3, #0] 8004c66: 683a ldr r2, [r7, #0] 8004c68: b292 uxth r2, r2 8004c6a: 61da str r2, [r3, #28] /* Wait for synchro */ if (RTC1_ExitInitMode(hrtc) != HAL_OK) 8004c6c: 6878 ldr r0, [r7, #4] 8004c6e: f000 f832 bl 8004cd6 8004c72: 4603 mov r3, r0 8004c74: 2b00 cmp r3, #0 8004c76: d001 beq.n 8004c7c { status = HAL_ERROR; 8004c78: 2301 movs r3, #1 8004c7a: 73fb strb r3, [r7, #15] } } return status; 8004c7c: 7bfb ldrb r3, [r7, #15] } 8004c7e: 4618 mov r0, r3 8004c80: 3710 adds r7, #16 8004c82: 46bd mov sp, r7 8004c84: bd80 pop {r7, pc} 08004c86 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC1_EnterInitMode(RTC_HandleTypeDef *hrtc) { 8004c86: b580 push {r7, lr} 8004c88: b084 sub sp, #16 8004c8a: af00 add r7, sp, #0 8004c8c: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8004c8e: 2300 movs r3, #0 8004c90: 60fb str r3, [r7, #12] tickstart = HAL_GetTick(); 8004c92: f000 fa7f bl 8005194 8004c96: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8004c98: e009 b.n 8004cae { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8004c9a: f000 fa7b bl 8005194 8004c9e: 4602 mov r2, r0 8004ca0: 68fb ldr r3, [r7, #12] 8004ca2: 1ad3 subs r3, r2, r3 8004ca4: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 8004ca8: d901 bls.n 8004cae { return HAL_TIMEOUT; 8004caa: 2303 movs r3, #3 8004cac: e00f b.n 8004cce while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8004cae: 687b ldr r3, [r7, #4] 8004cb0: 681b ldr r3, [r3, #0] 8004cb2: 685b ldr r3, [r3, #4] 8004cb4: f003 0320 and.w r3, r3, #32 8004cb8: 2b00 cmp r3, #0 8004cba: d0ee beq.n 8004c9a } } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 8004cbc: 687b ldr r3, [r7, #4] 8004cbe: 681b ldr r3, [r3, #0] 8004cc0: 685a ldr r2, [r3, #4] 8004cc2: 687b ldr r3, [r7, #4] 8004cc4: 681b ldr r3, [r3, #0] 8004cc6: f042 0210 orr.w r2, r2, #16 8004cca: 605a str r2, [r3, #4] return HAL_OK; 8004ccc: 2300 movs r3, #0 } 8004cce: 4618 mov r0, r3 8004cd0: 3710 adds r7, #16 8004cd2: 46bd mov sp, r7 8004cd4: bd80 pop {r7, pc} 08004cd6 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC1_ExitInitMode(RTC_HandleTypeDef *hrtc) { 8004cd6: b580 push {r7, lr} 8004cd8: b084 sub sp, #16 8004cda: af00 add r7, sp, #0 8004cdc: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8004cde: 2300 movs r3, #0 8004ce0: 60fb str r3, [r7, #12] /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 8004ce2: 687b ldr r3, [r7, #4] 8004ce4: 681b ldr r3, [r3, #0] 8004ce6: 685a ldr r2, [r3, #4] 8004ce8: 687b ldr r3, [r7, #4] 8004cea: 681b ldr r3, [r3, #0] 8004cec: f022 0210 bic.w r2, r2, #16 8004cf0: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8004cf2: f000 fa4f bl 8005194 8004cf6: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8004cf8: e009 b.n 8004d0e { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8004cfa: f000 fa4b bl 8005194 8004cfe: 4602 mov r2, r0 8004d00: 68fb ldr r3, [r7, #12] 8004d02: 1ad3 subs r3, r2, r3 8004d04: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 8004d08: d901 bls.n 8004d0e { return HAL_TIMEOUT; 8004d0a: 2303 movs r3, #3 8004d0c: e007 b.n 8004d1e while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8004d0e: 687b ldr r3, [r7, #4] 8004d10: 681b ldr r3, [r3, #0] 8004d12: 685b ldr r3, [r3, #4] 8004d14: f003 0320 and.w r3, r3, #32 8004d18: 2b00 cmp r3, #0 8004d1a: d0ee beq.n 8004cfa } } return HAL_OK; 8004d1c: 2300 movs r3, #0 } 8004d1e: 4618 mov r0, r3 8004d20: 3710 adds r7, #16 8004d22: 46bd mov sp, r7 8004d24: bd80 pop {r7, pc} ... 08004d28 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8004d28: b480 push {r7} 8004d2a: b085 sub sp, #20 8004d2c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8004d2e: 4b15 ldr r3, [pc, #84] ; (8004d84 ) 8004d30: 699b ldr r3, [r3, #24] 8004d32: 4a14 ldr r2, [pc, #80] ; (8004d84 ) 8004d34: f043 0301 orr.w r3, r3, #1 8004d38: 6193 str r3, [r2, #24] 8004d3a: 4b12 ldr r3, [pc, #72] ; (8004d84 ) 8004d3c: 699b ldr r3, [r3, #24] 8004d3e: f003 0301 and.w r3, r3, #1 8004d42: 60bb str r3, [r7, #8] 8004d44: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 8004d46: 4b0f ldr r3, [pc, #60] ; (8004d84 ) 8004d48: 69db ldr r3, [r3, #28] 8004d4a: 4a0e ldr r2, [pc, #56] ; (8004d84 ) 8004d4c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8004d50: 61d3 str r3, [r2, #28] 8004d52: 4b0c ldr r3, [pc, #48] ; (8004d84 ) 8004d54: 69db ldr r3, [r3, #28] 8004d56: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8004d5a: 607b str r3, [r7, #4] 8004d5c: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 8004d5e: 4b0a ldr r3, [pc, #40] ; (8004d88 ) 8004d60: 685b ldr r3, [r3, #4] 8004d62: 60fb str r3, [r7, #12] 8004d64: 68fb ldr r3, [r7, #12] 8004d66: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 8004d6a: 60fb str r3, [r7, #12] 8004d6c: 68fb ldr r3, [r7, #12] 8004d6e: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 8004d72: 60fb str r3, [r7, #12] 8004d74: 4a04 ldr r2, [pc, #16] ; (8004d88 ) 8004d76: 68fb ldr r3, [r7, #12] 8004d78: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8004d7a: bf00 nop 8004d7c: 3714 adds r7, #20 8004d7e: 46bd mov sp, r7 8004d80: bc80 pop {r7} 8004d82: 4770 bx lr 8004d84: 40021000 .word 0x40021000 8004d88: 40010000 .word 0x40010000 08004d8c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8004d8c: b480 push {r7} 8004d8e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8004d90: e7fe b.n 8004d90 08004d92 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8004d92: b480 push {r7} 8004d94: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8004d96: e7fe b.n 8004d96 08004d98 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8004d98: b480 push {r7} 8004d9a: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8004d9c: e7fe b.n 8004d9c 08004d9e : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8004d9e: b480 push {r7} 8004da0: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8004da2: e7fe b.n 8004da2 08004da4 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8004da4: b480 push {r7} 8004da6: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8004da8: e7fe b.n 8004da8 08004daa : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8004daa: b480 push {r7} 8004dac: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8004dae: bf00 nop 8004db0: 46bd mov sp, r7 8004db2: bc80 pop {r7} 8004db4: 4770 bx lr 08004db6 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8004db6: b480 push {r7} 8004db8: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8004dba: bf00 nop 8004dbc: 46bd mov sp, r7 8004dbe: bc80 pop {r7} 8004dc0: 4770 bx lr 08004dc2 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8004dc2: b480 push {r7} 8004dc4: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8004dc6: bf00 nop 8004dc8: 46bd mov sp, r7 8004dca: bc80 pop {r7} 8004dcc: 4770 bx lr 08004dce : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8004dce: b580 push {r7, lr} 8004dd0: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8004dd2: f000 f9cd bl 8005170 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8004dd6: bf00 nop 8004dd8: bd80 pop {r7, pc} ... 08004ddc : /** * @brief This function handles CAN1 RX0 interrupt. */ void CAN1_RX0_IRQHandler(void) { 8004ddc: b580 push {r7, lr} 8004dde: af00 add r7, sp, #0 /* USER CODE BEGIN CAN1_RX0_IRQn 0 */ /* USER CODE END CAN1_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan1); 8004de0: 4802 ldr r0, [pc, #8] ; (8004dec ) 8004de2: f001 fbb6 bl 8006552 /* USER CODE BEGIN CAN1_RX0_IRQn 1 */ /* USER CODE END CAN1_RX0_IRQn 1 */ } 8004de6: bf00 nop 8004de8: bd80 pop {r7, pc} 8004dea: bf00 nop 8004dec: 20000290 .word 0x20000290 08004df0 : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 8004df0: b580 push {r7, lr} 8004df2: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 8004df4: 4802 ldr r0, [pc, #8] ; (8004e00 ) 8004df6: f003 fbbf bl 8008578 /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 8004dfa: bf00 nop 8004dfc: bd80 pop {r7, pc} 8004dfe: bf00 nop 8004e00: 20003350 .word 0x20003350 08004e04 : /** * @brief This function handles CAN2 TX interrupt. */ void CAN2_TX_IRQHandler(void) { 8004e04: b580 push {r7, lr} 8004e06: af00 add r7, sp, #0 /* USER CODE BEGIN CAN2_TX_IRQn 0 */ /* USER CODE END CAN2_TX_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 8004e08: 4802 ldr r0, [pc, #8] ; (8004e14 ) 8004e0a: f001 fba2 bl 8006552 /* USER CODE BEGIN CAN2_TX_IRQn 1 */ /* USER CODE END CAN2_TX_IRQn 1 */ } 8004e0e: bf00 nop 8004e10: bd80 pop {r7, pc} 8004e12: bf00 nop 8004e14: 200002b8 .word 0x200002b8 08004e18 : /** * @brief This function handles CAN2 RX1 interrupt. */ void CAN2_RX1_IRQHandler(void) { 8004e18: b580 push {r7, lr} 8004e1a: af00 add r7, sp, #0 /* USER CODE BEGIN CAN2_RX1_IRQn 0 */ /* USER CODE END CAN2_RX1_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 8004e1c: 4802 ldr r0, [pc, #8] ; (8004e28 ) 8004e1e: f001 fb98 bl 8006552 /* USER CODE BEGIN CAN2_RX1_IRQn 1 */ /* USER CODE END CAN2_RX1_IRQn 1 */ } 8004e22: bf00 nop 8004e24: bd80 pop {r7, pc} 8004e26: bf00 nop 8004e28: 200002b8 .word 0x200002b8 08004e2c <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 8004e2c: b480 push {r7} 8004e2e: af00 add r7, sp, #0 return 1; 8004e30: 2301 movs r3, #1 } 8004e32: 4618 mov r0, r3 8004e34: 46bd mov sp, r7 8004e36: bc80 pop {r7} 8004e38: 4770 bx lr 08004e3a <_kill>: int _kill(int pid, int sig) { 8004e3a: b580 push {r7, lr} 8004e3c: b082 sub sp, #8 8004e3e: af00 add r7, sp, #0 8004e40: 6078 str r0, [r7, #4] 8004e42: 6039 str r1, [r7, #0] (void)pid; (void)sig; errno = EINVAL; 8004e44: f003 ffbe bl 8008dc4 <__errno> 8004e48: 4603 mov r3, r0 8004e4a: 2216 movs r2, #22 8004e4c: 601a str r2, [r3, #0] return -1; 8004e4e: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 8004e52: 4618 mov r0, r3 8004e54: 3708 adds r7, #8 8004e56: 46bd mov sp, r7 8004e58: bd80 pop {r7, pc} 08004e5a <_exit>: void _exit (int status) { 8004e5a: b580 push {r7, lr} 8004e5c: b082 sub sp, #8 8004e5e: af00 add r7, sp, #0 8004e60: 6078 str r0, [r7, #4] _kill(status, -1); 8004e62: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8004e66: 6878 ldr r0, [r7, #4] 8004e68: f7ff ffe7 bl 8004e3a <_kill> while (1) {} /* Make sure we hang here */ 8004e6c: e7fe b.n 8004e6c <_exit+0x12> 08004e6e <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8004e6e: b580 push {r7, lr} 8004e70: b086 sub sp, #24 8004e72: af00 add r7, sp, #0 8004e74: 60f8 str r0, [r7, #12] 8004e76: 60b9 str r1, [r7, #8] 8004e78: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8004e7a: 2300 movs r3, #0 8004e7c: 617b str r3, [r7, #20] 8004e7e: e00a b.n 8004e96 <_read+0x28> { *ptr++ = __io_getchar(); 8004e80: f3af 8000 nop.w 8004e84: 4601 mov r1, r0 8004e86: 68bb ldr r3, [r7, #8] 8004e88: 1c5a adds r2, r3, #1 8004e8a: 60ba str r2, [r7, #8] 8004e8c: b2ca uxtb r2, r1 8004e8e: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 8004e90: 697b ldr r3, [r7, #20] 8004e92: 3301 adds r3, #1 8004e94: 617b str r3, [r7, #20] 8004e96: 697a ldr r2, [r7, #20] 8004e98: 687b ldr r3, [r7, #4] 8004e9a: 429a cmp r2, r3 8004e9c: dbf0 blt.n 8004e80 <_read+0x12> } return len; 8004e9e: 687b ldr r3, [r7, #4] } 8004ea0: 4618 mov r0, r3 8004ea2: 3718 adds r7, #24 8004ea4: 46bd mov sp, r7 8004ea6: bd80 pop {r7, pc} 08004ea8 <_close>: } return len; } int _close(int file) { 8004ea8: b480 push {r7} 8004eaa: b083 sub sp, #12 8004eac: af00 add r7, sp, #0 8004eae: 6078 str r0, [r7, #4] (void)file; return -1; 8004eb0: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 8004eb4: 4618 mov r0, r3 8004eb6: 370c adds r7, #12 8004eb8: 46bd mov sp, r7 8004eba: bc80 pop {r7} 8004ebc: 4770 bx lr 08004ebe <_fstat>: int _fstat(int file, struct stat *st) { 8004ebe: b480 push {r7} 8004ec0: b083 sub sp, #12 8004ec2: af00 add r7, sp, #0 8004ec4: 6078 str r0, [r7, #4] 8004ec6: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 8004ec8: 683b ldr r3, [r7, #0] 8004eca: f44f 5200 mov.w r2, #8192 ; 0x2000 8004ece: 605a str r2, [r3, #4] return 0; 8004ed0: 2300 movs r3, #0 } 8004ed2: 4618 mov r0, r3 8004ed4: 370c adds r7, #12 8004ed6: 46bd mov sp, r7 8004ed8: bc80 pop {r7} 8004eda: 4770 bx lr 08004edc <_isatty>: int _isatty(int file) { 8004edc: b480 push {r7} 8004ede: b083 sub sp, #12 8004ee0: af00 add r7, sp, #0 8004ee2: 6078 str r0, [r7, #4] (void)file; return 1; 8004ee4: 2301 movs r3, #1 } 8004ee6: 4618 mov r0, r3 8004ee8: 370c adds r7, #12 8004eea: 46bd mov sp, r7 8004eec: bc80 pop {r7} 8004eee: 4770 bx lr 08004ef0 <_lseek>: int _lseek(int file, int ptr, int dir) { 8004ef0: b480 push {r7} 8004ef2: b085 sub sp, #20 8004ef4: af00 add r7, sp, #0 8004ef6: 60f8 str r0, [r7, #12] 8004ef8: 60b9 str r1, [r7, #8] 8004efa: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 8004efc: 2300 movs r3, #0 } 8004efe: 4618 mov r0, r3 8004f00: 3714 adds r7, #20 8004f02: 46bd mov sp, r7 8004f04: bc80 pop {r7} 8004f06: 4770 bx lr 08004f08 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8004f08: b580 push {r7, lr} 8004f0a: b086 sub sp, #24 8004f0c: af00 add r7, sp, #0 8004f0e: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 8004f10: 4a14 ldr r2, [pc, #80] ; (8004f64 <_sbrk+0x5c>) 8004f12: 4b15 ldr r3, [pc, #84] ; (8004f68 <_sbrk+0x60>) 8004f14: 1ad3 subs r3, r2, r3 8004f16: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8004f18: 697b ldr r3, [r7, #20] 8004f1a: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 8004f1c: 4b13 ldr r3, [pc, #76] ; (8004f6c <_sbrk+0x64>) 8004f1e: 681b ldr r3, [r3, #0] 8004f20: 2b00 cmp r3, #0 8004f22: d102 bne.n 8004f2a <_sbrk+0x22> { __sbrk_heap_end = &_end; 8004f24: 4b11 ldr r3, [pc, #68] ; (8004f6c <_sbrk+0x64>) 8004f26: 4a12 ldr r2, [pc, #72] ; (8004f70 <_sbrk+0x68>) 8004f28: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 8004f2a: 4b10 ldr r3, [pc, #64] ; (8004f6c <_sbrk+0x64>) 8004f2c: 681a ldr r2, [r3, #0] 8004f2e: 687b ldr r3, [r7, #4] 8004f30: 4413 add r3, r2 8004f32: 693a ldr r2, [r7, #16] 8004f34: 429a cmp r2, r3 8004f36: d207 bcs.n 8004f48 <_sbrk+0x40> { errno = ENOMEM; 8004f38: f003 ff44 bl 8008dc4 <__errno> 8004f3c: 4603 mov r3, r0 8004f3e: 220c movs r2, #12 8004f40: 601a str r2, [r3, #0] return (void *)-1; 8004f42: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff 8004f46: e009 b.n 8004f5c <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 8004f48: 4b08 ldr r3, [pc, #32] ; (8004f6c <_sbrk+0x64>) 8004f4a: 681b ldr r3, [r3, #0] 8004f4c: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 8004f4e: 4b07 ldr r3, [pc, #28] ; (8004f6c <_sbrk+0x64>) 8004f50: 681a ldr r2, [r3, #0] 8004f52: 687b ldr r3, [r7, #4] 8004f54: 4413 add r3, r2 8004f56: 4a05 ldr r2, [pc, #20] ; (8004f6c <_sbrk+0x64>) 8004f58: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 8004f5a: 68fb ldr r3, [r7, #12] } 8004f5c: 4618 mov r0, r3 8004f5e: 3718 adds r7, #24 8004f60: 46bd mov sp, r7 8004f62: bd80 pop {r7, pc} 8004f64: 20010000 .word 0x20010000 8004f68: 00000400 .word 0x00000400 8004f6c: 2000334c .word 0x2000334c 8004f70: 200033d0 .word 0x200033d0 08004f74 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8004f74: b480 push {r7} 8004f76: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 8004f78: bf00 nop 8004f7a: 46bd mov sp, r7 8004f7c: bc80 pop {r7} 8004f7e: 4770 bx lr 08004f80 : UART_HandleTypeDef huart2; /* USART2 init function */ void MX_USART2_UART_Init(void) { 8004f80: b580 push {r7, lr} 8004f82: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 8004f84: 4b11 ldr r3, [pc, #68] ; (8004fcc ) 8004f86: 4a12 ldr r2, [pc, #72] ; (8004fd0 ) 8004f88: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 8004f8a: 4b10 ldr r3, [pc, #64] ; (8004fcc ) 8004f8c: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8004f90: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 8004f92: 4b0e ldr r3, [pc, #56] ; (8004fcc ) 8004f94: 2200 movs r2, #0 8004f96: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 8004f98: 4b0c ldr r3, [pc, #48] ; (8004fcc ) 8004f9a: 2200 movs r2, #0 8004f9c: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 8004f9e: 4b0b ldr r3, [pc, #44] ; (8004fcc ) 8004fa0: 2200 movs r2, #0 8004fa2: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 8004fa4: 4b09 ldr r3, [pc, #36] ; (8004fcc ) 8004fa6: 220c movs r2, #12 8004fa8: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8004faa: 4b08 ldr r3, [pc, #32] ; (8004fcc ) 8004fac: 2200 movs r2, #0 8004fae: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 8004fb0: 4b06 ldr r3, [pc, #24] ; (8004fcc ) 8004fb2: 2200 movs r2, #0 8004fb4: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 8004fb6: 4805 ldr r0, [pc, #20] ; (8004fcc ) 8004fb8: f003 f9af bl 800831a 8004fbc: 4603 mov r3, r0 8004fbe: 2b00 cmp r3, #0 8004fc0: d001 beq.n 8004fc6 { Error_Handler(); 8004fc2: f7ff fcc3 bl 800494c } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 8004fc6: bf00 nop 8004fc8: bd80 pop {r7, pc} 8004fca: bf00 nop 8004fcc: 20003350 .word 0x20003350 8004fd0: 40004400 .word 0x40004400 08004fd4 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 8004fd4: b580 push {r7, lr} 8004fd6: b08a sub sp, #40 ; 0x28 8004fd8: af00 add r7, sp, #0 8004fda: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004fdc: f107 0314 add.w r3, r7, #20 8004fe0: 2200 movs r2, #0 8004fe2: 601a str r2, [r3, #0] 8004fe4: 605a str r2, [r3, #4] 8004fe6: 609a str r2, [r3, #8] 8004fe8: 60da str r2, [r3, #12] if(uartHandle->Instance==USART2) 8004fea: 687b ldr r3, [r7, #4] 8004fec: 681b ldr r3, [r3, #0] 8004fee: 4a26 ldr r2, [pc, #152] ; (8005088 ) 8004ff0: 4293 cmp r3, r2 8004ff2: d145 bne.n 8005080 { /* USER CODE BEGIN USART2_MspInit 0 */ /* USER CODE END USART2_MspInit 0 */ /* USART2 clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); 8004ff4: 4b25 ldr r3, [pc, #148] ; (800508c ) 8004ff6: 69db ldr r3, [r3, #28] 8004ff8: 4a24 ldr r2, [pc, #144] ; (800508c ) 8004ffa: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8004ffe: 61d3 str r3, [r2, #28] 8005000: 4b22 ldr r3, [pc, #136] ; (800508c ) 8005002: 69db ldr r3, [r3, #28] 8005004: f403 3300 and.w r3, r3, #131072 ; 0x20000 8005008: 613b str r3, [r7, #16] 800500a: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOD_CLK_ENABLE(); 800500c: 4b1f ldr r3, [pc, #124] ; (800508c ) 800500e: 699b ldr r3, [r3, #24] 8005010: 4a1e ldr r2, [pc, #120] ; (800508c ) 8005012: f043 0320 orr.w r3, r3, #32 8005016: 6193 str r3, [r2, #24] 8005018: 4b1c ldr r3, [pc, #112] ; (800508c ) 800501a: 699b ldr r3, [r3, #24] 800501c: f003 0320 and.w r3, r3, #32 8005020: 60fb str r3, [r7, #12] 8005022: 68fb ldr r3, [r7, #12] /**USART2 GPIO Configuration PD5 ------> USART2_TX PD6 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_5; 8005024: 2320 movs r3, #32 8005026: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8005028: 2302 movs r3, #2 800502a: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800502c: 2303 movs r3, #3 800502e: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8005030: f107 0314 add.w r3, r7, #20 8005034: 4619 mov r1, r3 8005036: 4816 ldr r0, [pc, #88] ; (8005090 ) 8005038: f001 feda bl 8006df0 GPIO_InitStruct.Pin = GPIO_PIN_6; 800503c: 2340 movs r3, #64 ; 0x40 800503e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8005040: 2300 movs r3, #0 8005042: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005044: 2300 movs r3, #0 8005046: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8005048: f107 0314 add.w r3, r7, #20 800504c: 4619 mov r1, r3 800504e: 4810 ldr r0, [pc, #64] ; (8005090 ) 8005050: f001 fece bl 8006df0 __HAL_AFIO_REMAP_USART2_ENABLE(); 8005054: 4b0f ldr r3, [pc, #60] ; (8005094 ) 8005056: 685b ldr r3, [r3, #4] 8005058: 627b str r3, [r7, #36] ; 0x24 800505a: 6a7b ldr r3, [r7, #36] ; 0x24 800505c: f043 63e0 orr.w r3, r3, #117440512 ; 0x7000000 8005060: 627b str r3, [r7, #36] ; 0x24 8005062: 6a7b ldr r3, [r7, #36] ; 0x24 8005064: f043 0308 orr.w r3, r3, #8 8005068: 627b str r3, [r7, #36] ; 0x24 800506a: 4a0a ldr r2, [pc, #40] ; (8005094 ) 800506c: 6a7b ldr r3, [r7, #36] ; 0x24 800506e: 6053 str r3, [r2, #4] /* USART2 interrupt Init */ HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); 8005070: 2200 movs r2, #0 8005072: 2100 movs r1, #0 8005074: 2026 movs r0, #38 ; 0x26 8005076: f001 fd42 bl 8006afe HAL_NVIC_EnableIRQ(USART2_IRQn); 800507a: 2026 movs r0, #38 ; 0x26 800507c: f001 fd5b bl 8006b36 /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 8005080: bf00 nop 8005082: 3728 adds r7, #40 ; 0x28 8005084: 46bd mov sp, r7 8005086: bd80 pop {r7, pc} 8005088: 40004400 .word 0x40004400 800508c: 40021000 .word 0x40021000 8005090: 40011400 .word 0x40011400 8005094: 40010000 .word 0x40010000 08005098 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 8005098: f7ff ff6c bl 8004f74 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 800509c: 480b ldr r0, [pc, #44] ; (80050cc ) ldr r1, =_edata 800509e: 490c ldr r1, [pc, #48] ; (80050d0 ) ldr r2, =_sidata 80050a0: 4a0c ldr r2, [pc, #48] ; (80050d4 ) movs r3, #0 80050a2: 2300 movs r3, #0 b LoopCopyDataInit 80050a4: e002 b.n 80050ac 080050a6 : CopyDataInit: ldr r4, [r2, r3] 80050a6: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80050a8: 50c4 str r4, [r0, r3] adds r3, r3, #4 80050aa: 3304 adds r3, #4 080050ac : LoopCopyDataInit: adds r4, r0, r3 80050ac: 18c4 adds r4, r0, r3 cmp r4, r1 80050ae: 428c cmp r4, r1 bcc CopyDataInit 80050b0: d3f9 bcc.n 80050a6 /* Zero fill the bss segment. */ ldr r2, =_sbss 80050b2: 4a09 ldr r2, [pc, #36] ; (80050d8 ) ldr r4, =_ebss 80050b4: 4c09 ldr r4, [pc, #36] ; (80050dc ) movs r3, #0 80050b6: 2300 movs r3, #0 b LoopFillZerobss 80050b8: e001 b.n 80050be 080050ba : FillZerobss: str r3, [r2] 80050ba: 6013 str r3, [r2, #0] adds r2, r2, #4 80050bc: 3204 adds r2, #4 080050be : LoopFillZerobss: cmp r2, r4 80050be: 42a2 cmp r2, r4 bcc FillZerobss 80050c0: d3fb bcc.n 80050ba /* Call static constructors */ bl __libc_init_array 80050c2: f003 ff51 bl 8008f68 <__libc_init_array> /* Call the application's entry point.*/ bl main 80050c6: f7ff fb8f bl 80047e8
bx lr 80050ca: 4770 bx lr ldr r0, =_sdata 80050cc: 20000000 .word 0x20000000 ldr r1, =_edata 80050d0: 20000244 .word 0x20000244 ldr r2, =_sidata 80050d4: 0800d804 .word 0x0800d804 ldr r2, =_sbss 80050d8: 20000244 .word 0x20000244 ldr r4, =_ebss 80050dc: 200033d0 .word 0x200033d0 080050e0 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80050e0: e7fe b.n 80050e0 ... 080050e4 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80050e4: b580 push {r7, lr} 80050e6: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80050e8: 4b08 ldr r3, [pc, #32] ; (800510c ) 80050ea: 681b ldr r3, [r3, #0] 80050ec: 4a07 ldr r2, [pc, #28] ; (800510c ) 80050ee: f043 0310 orr.w r3, r3, #16 80050f2: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80050f4: 2003 movs r0, #3 80050f6: f001 fcf7 bl 8006ae8 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 80050fa: 200f movs r0, #15 80050fc: f000 f808 bl 8005110 /* Init the low level hardware */ HAL_MspInit(); 8005100: f7ff fe12 bl 8004d28 /* Return function status */ return HAL_OK; 8005104: 2300 movs r3, #0 } 8005106: 4618 mov r0, r3 8005108: bd80 pop {r7, pc} 800510a: bf00 nop 800510c: 40022000 .word 0x40022000 08005110 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8005110: b580 push {r7, lr} 8005112: b082 sub sp, #8 8005114: af00 add r7, sp, #0 8005116: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8005118: 4b12 ldr r3, [pc, #72] ; (8005164 ) 800511a: 681a ldr r2, [r3, #0] 800511c: 4b12 ldr r3, [pc, #72] ; (8005168 ) 800511e: 781b ldrb r3, [r3, #0] 8005120: 4619 mov r1, r3 8005122: f44f 737a mov.w r3, #1000 ; 0x3e8 8005126: fbb3 f3f1 udiv r3, r3, r1 800512a: fbb2 f3f3 udiv r3, r2, r3 800512e: 4618 mov r0, r3 8005130: f001 fd0f bl 8006b52 8005134: 4603 mov r3, r0 8005136: 2b00 cmp r3, #0 8005138: d001 beq.n 800513e { return HAL_ERROR; 800513a: 2301 movs r3, #1 800513c: e00e b.n 800515c } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800513e: 687b ldr r3, [r7, #4] 8005140: 2b0f cmp r3, #15 8005142: d80a bhi.n 800515a { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8005144: 2200 movs r2, #0 8005146: 6879 ldr r1, [r7, #4] 8005148: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800514c: f001 fcd7 bl 8006afe uwTickPrio = TickPriority; 8005150: 4a06 ldr r2, [pc, #24] ; (800516c ) 8005152: 687b ldr r3, [r7, #4] 8005154: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8005156: 2300 movs r3, #0 8005158: e000 b.n 800515c return HAL_ERROR; 800515a: 2301 movs r3, #1 } 800515c: 4618 mov r0, r3 800515e: 3708 adds r7, #8 8005160: 46bd mov sp, r7 8005162: bd80 pop {r7, pc} 8005164: 20000008 .word 0x20000008 8005168: 20000010 .word 0x20000010 800516c: 2000000c .word 0x2000000c 08005170 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8005170: b480 push {r7} 8005172: af00 add r7, sp, #0 uwTick += uwTickFreq; 8005174: 4b05 ldr r3, [pc, #20] ; (800518c ) 8005176: 781b ldrb r3, [r3, #0] 8005178: 461a mov r2, r3 800517a: 4b05 ldr r3, [pc, #20] ; (8005190 ) 800517c: 681b ldr r3, [r3, #0] 800517e: 4413 add r3, r2 8005180: 4a03 ldr r2, [pc, #12] ; (8005190 ) 8005182: 6013 str r3, [r2, #0] } 8005184: bf00 nop 8005186: 46bd mov sp, r7 8005188: bc80 pop {r7} 800518a: 4770 bx lr 800518c: 20000010 .word 0x20000010 8005190: 20003394 .word 0x20003394 08005194 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8005194: b480 push {r7} 8005196: af00 add r7, sp, #0 return uwTick; 8005198: 4b02 ldr r3, [pc, #8] ; (80051a4 ) 800519a: 681b ldr r3, [r3, #0] } 800519c: 4618 mov r0, r3 800519e: 46bd mov sp, r7 80051a0: bc80 pop {r7} 80051a2: 4770 bx lr 80051a4: 20003394 .word 0x20003394 080051a8 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80051a8: b580 push {r7, lr} 80051aa: b084 sub sp, #16 80051ac: af00 add r7, sp, #0 80051ae: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 80051b0: f7ff fff0 bl 8005194 80051b4: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 80051b6: 687b ldr r3, [r7, #4] 80051b8: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80051ba: 68fb ldr r3, [r7, #12] 80051bc: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 80051c0: d005 beq.n 80051ce { wait += (uint32_t)(uwTickFreq); 80051c2: 4b0a ldr r3, [pc, #40] ; (80051ec ) 80051c4: 781b ldrb r3, [r3, #0] 80051c6: 461a mov r2, r3 80051c8: 68fb ldr r3, [r7, #12] 80051ca: 4413 add r3, r2 80051cc: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 80051ce: bf00 nop 80051d0: f7ff ffe0 bl 8005194 80051d4: 4602 mov r2, r0 80051d6: 68bb ldr r3, [r7, #8] 80051d8: 1ad3 subs r3, r2, r3 80051da: 68fa ldr r2, [r7, #12] 80051dc: 429a cmp r2, r3 80051de: d8f7 bhi.n 80051d0 { } } 80051e0: bf00 nop 80051e2: bf00 nop 80051e4: 3710 adds r7, #16 80051e6: 46bd mov sp, r7 80051e8: bd80 pop {r7, pc} 80051ea: bf00 nop 80051ec: 20000010 .word 0x20000010 080051f0 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 80051f0: b580 push {r7, lr} 80051f2: b086 sub sp, #24 80051f4: af00 add r7, sp, #0 80051f6: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80051f8: 2300 movs r3, #0 80051fa: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 80051fc: 2300 movs r3, #0 80051fe: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 8005200: 2300 movs r3, #0 8005202: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 8005204: 2300 movs r3, #0 8005206: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 8005208: 687b ldr r3, [r7, #4] 800520a: 2b00 cmp r3, #0 800520c: d101 bne.n 8005212 { return HAL_ERROR; 800520e: 2301 movs r3, #1 8005210: e0be b.n 8005390 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 8005212: 687b ldr r3, [r7, #4] 8005214: 689b ldr r3, [r3, #8] 8005216: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8005218: 687b ldr r3, [r7, #4] 800521a: 6a9b ldr r3, [r3, #40] ; 0x28 800521c: 2b00 cmp r3, #0 800521e: d109 bne.n 8005234 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 8005220: 687b ldr r3, [r7, #4] 8005222: 2200 movs r2, #0 8005224: 62da str r2, [r3, #44] ; 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8005226: 687b ldr r3, [r7, #4] 8005228: 2200 movs r2, #0 800522a: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800522e: 6878 ldr r0, [r7, #4] 8005230: f7fc f9fc bl 800162c /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8005234: 6878 ldr r0, [r7, #4] 8005236: f000 fbf1 bl 8005a1c 800523a: 4603 mov r3, r0 800523c: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 800523e: 687b ldr r3, [r7, #4] 8005240: 6a9b ldr r3, [r3, #40] ; 0x28 8005242: f003 0310 and.w r3, r3, #16 8005246: 2b00 cmp r3, #0 8005248: f040 8099 bne.w 800537e 800524c: 7dfb ldrb r3, [r7, #23] 800524e: 2b00 cmp r3, #0 8005250: f040 8095 bne.w 800537e (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8005254: 687b ldr r3, [r7, #4] 8005256: 6a9b ldr r3, [r3, #40] ; 0x28 8005258: f423 5388 bic.w r3, r3, #4352 ; 0x1100 800525c: f023 0302 bic.w r3, r3, #2 8005260: f043 0202 orr.w r2, r3, #2 8005264: 687b ldr r3, [r7, #4] 8005266: 629a str r2, [r3, #40] ; 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 8005268: 687b ldr r3, [r7, #4] 800526a: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800526c: 687b ldr r3, [r7, #4] 800526e: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 8005270: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 8005272: 687b ldr r3, [r7, #4] 8005274: 7b1b ldrb r3, [r3, #12] 8005276: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8005278: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 800527a: 68ba ldr r2, [r7, #8] 800527c: 4313 orrs r3, r2 800527e: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 8005280: 687b ldr r3, [r7, #4] 8005282: 689b ldr r3, [r3, #8] 8005284: f5b3 7f80 cmp.w r3, #256 ; 0x100 8005288: d003 beq.n 8005292 800528a: 687b ldr r3, [r7, #4] 800528c: 689b ldr r3, [r3, #8] 800528e: 2b01 cmp r3, #1 8005290: d102 bne.n 8005298 8005292: f44f 7380 mov.w r3, #256 ; 0x100 8005296: e000 b.n 800529a 8005298: 2300 movs r3, #0 800529a: 693a ldr r2, [r7, #16] 800529c: 4313 orrs r3, r2 800529e: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 80052a0: 687b ldr r3, [r7, #4] 80052a2: 7d1b ldrb r3, [r3, #20] 80052a4: 2b01 cmp r3, #1 80052a6: d119 bne.n 80052dc { if (hadc->Init.ContinuousConvMode == DISABLE) 80052a8: 687b ldr r3, [r7, #4] 80052aa: 7b1b ldrb r3, [r3, #12] 80052ac: 2b00 cmp r3, #0 80052ae: d109 bne.n 80052c4 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 80052b0: 687b ldr r3, [r7, #4] 80052b2: 699b ldr r3, [r3, #24] 80052b4: 3b01 subs r3, #1 80052b6: 035a lsls r2, r3, #13 80052b8: 693b ldr r3, [r7, #16] 80052ba: 4313 orrs r3, r2 80052bc: f443 6300 orr.w r3, r3, #2048 ; 0x800 80052c0: 613b str r3, [r7, #16] 80052c2: e00b b.n 80052dc { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80052c4: 687b ldr r3, [r7, #4] 80052c6: 6a9b ldr r3, [r3, #40] ; 0x28 80052c8: f043 0220 orr.w r2, r3, #32 80052cc: 687b ldr r3, [r7, #4] 80052ce: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80052d0: 687b ldr r3, [r7, #4] 80052d2: 6adb ldr r3, [r3, #44] ; 0x2c 80052d4: f043 0201 orr.w r2, r3, #1 80052d8: 687b ldr r3, [r7, #4] 80052da: 62da str r2, [r3, #44] ; 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 80052dc: 687b ldr r3, [r7, #4] 80052de: 681b ldr r3, [r3, #0] 80052e0: 685b ldr r3, [r3, #4] 80052e2: f423 4169 bic.w r1, r3, #59648 ; 0xe900 80052e6: 687b ldr r3, [r7, #4] 80052e8: 681b ldr r3, [r3, #0] 80052ea: 693a ldr r2, [r7, #16] 80052ec: 430a orrs r2, r1 80052ee: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 80052f0: 687b ldr r3, [r7, #4] 80052f2: 681b ldr r3, [r3, #0] 80052f4: 689a ldr r2, [r3, #8] 80052f6: 4b28 ldr r3, [pc, #160] ; (8005398 ) 80052f8: 4013 ands r3, r2 80052fa: 687a ldr r2, [r7, #4] 80052fc: 6812 ldr r2, [r2, #0] 80052fe: 68b9 ldr r1, [r7, #8] 8005300: 430b orrs r3, r1 8005302: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 8005304: 687b ldr r3, [r7, #4] 8005306: 689b ldr r3, [r3, #8] 8005308: f5b3 7f80 cmp.w r3, #256 ; 0x100 800530c: d003 beq.n 8005316 800530e: 687b ldr r3, [r7, #4] 8005310: 689b ldr r3, [r3, #8] 8005312: 2b01 cmp r3, #1 8005314: d104 bne.n 8005320 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 8005316: 687b ldr r3, [r7, #4] 8005318: 691b ldr r3, [r3, #16] 800531a: 3b01 subs r3, #1 800531c: 051b lsls r3, r3, #20 800531e: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 8005320: 687b ldr r3, [r7, #4] 8005322: 681b ldr r3, [r3, #0] 8005324: 6adb ldr r3, [r3, #44] ; 0x2c 8005326: f423 0170 bic.w r1, r3, #15728640 ; 0xf00000 800532a: 687b ldr r3, [r7, #4] 800532c: 681b ldr r3, [r3, #0] 800532e: 68fa ldr r2, [r7, #12] 8005330: 430a orrs r2, r1 8005332: 62da str r2, [r3, #44] ; 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8005334: 687b ldr r3, [r7, #4] 8005336: 681b ldr r3, [r3, #0] 8005338: 689a ldr r2, [r3, #8] 800533a: 4b18 ldr r3, [pc, #96] ; (800539c ) 800533c: 4013 ands r3, r2 800533e: 68ba ldr r2, [r7, #8] 8005340: 429a cmp r2, r3 8005342: d10b bne.n 800535c ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8005344: 687b ldr r3, [r7, #4] 8005346: 2200 movs r2, #0 8005348: 62da str r2, [r3, #44] ; 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 800534a: 687b ldr r3, [r7, #4] 800534c: 6a9b ldr r3, [r3, #40] ; 0x28 800534e: f023 0303 bic.w r3, r3, #3 8005352: f043 0201 orr.w r2, r3, #1 8005356: 687b ldr r3, [r7, #4] 8005358: 629a str r2, [r3, #40] ; 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800535a: e018 b.n 800538e HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800535c: 687b ldr r3, [r7, #4] 800535e: 6a9b ldr r3, [r3, #40] ; 0x28 8005360: f023 0312 bic.w r3, r3, #18 8005364: f043 0210 orr.w r2, r3, #16 8005368: 687b ldr r3, [r7, #4] 800536a: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800536c: 687b ldr r3, [r7, #4] 800536e: 6adb ldr r3, [r3, #44] ; 0x2c 8005370: f043 0201 orr.w r2, r3, #1 8005374: 687b ldr r3, [r7, #4] 8005376: 62da str r2, [r3, #44] ; 0x2c tmp_hal_status = HAL_ERROR; 8005378: 2301 movs r3, #1 800537a: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800537c: e007 b.n 800538e } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800537e: 687b ldr r3, [r7, #4] 8005380: 6a9b ldr r3, [r3, #40] ; 0x28 8005382: f043 0210 orr.w r2, r3, #16 8005386: 687b ldr r3, [r7, #4] 8005388: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 800538a: 2301 movs r3, #1 800538c: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800538e: 7dfb ldrb r3, [r7, #23] } 8005390: 4618 mov r0, r3 8005392: 3718 adds r7, #24 8005394: 46bd mov sp, r7 8005396: bd80 pop {r7, pc} 8005398: ffe1f7fd .word 0xffe1f7fd 800539c: ff1f0efe .word 0xff1f0efe 080053a0 : * Interruptions enabled in this function: None. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { 80053a0: b580 push {r7, lr} 80053a2: b084 sub sp, #16 80053a4: af00 add r7, sp, #0 80053a6: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80053a8: 2300 movs r3, #0 80053aa: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 80053ac: 687b ldr r3, [r7, #4] 80053ae: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 80053b2: 2b01 cmp r3, #1 80053b4: d101 bne.n 80053ba 80053b6: 2302 movs r3, #2 80053b8: e098 b.n 80054ec 80053ba: 687b ldr r3, [r7, #4] 80053bc: 2201 movs r2, #1 80053be: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 80053c2: 6878 ldr r0, [r7, #4] 80053c4: f000 fad0 bl 8005968 80053c8: 4603 mov r3, r0 80053ca: 73fb strb r3, [r7, #15] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 80053cc: 7bfb ldrb r3, [r7, #15] 80053ce: 2b00 cmp r3, #0 80053d0: f040 8087 bne.w 80054e2 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 80053d4: 687b ldr r3, [r7, #4] 80053d6: 6a9b ldr r3, [r3, #40] ; 0x28 80053d8: f423 7340 bic.w r3, r3, #768 ; 0x300 80053dc: f023 0301 bic.w r3, r3, #1 80053e0: f443 7280 orr.w r2, r3, #256 ; 0x100 80053e4: 687b ldr r3, [r7, #4] 80053e6: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 80053e8: 687b ldr r3, [r7, #4] 80053ea: 681b ldr r3, [r3, #0] 80053ec: 4a41 ldr r2, [pc, #260] ; (80054f4 ) 80053ee: 4293 cmp r3, r2 80053f0: d105 bne.n 80053fe 80053f2: 4b41 ldr r3, [pc, #260] ; (80054f8 ) 80053f4: 685b ldr r3, [r3, #4] 80053f6: f403 2370 and.w r3, r3, #983040 ; 0xf0000 80053fa: 2b00 cmp r3, #0 80053fc: d115 bne.n 800542a { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 80053fe: 687b ldr r3, [r7, #4] 8005400: 6a9b ldr r3, [r3, #40] ; 0x28 8005402: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 8005406: 687b ldr r3, [r7, #4] 8005408: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800540a: 687b ldr r3, [r7, #4] 800540c: 681b ldr r3, [r3, #0] 800540e: 685b ldr r3, [r3, #4] 8005410: f403 6380 and.w r3, r3, #1024 ; 0x400 8005414: 2b00 cmp r3, #0 8005416: d026 beq.n 8005466 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8005418: 687b ldr r3, [r7, #4] 800541a: 6a9b ldr r3, [r3, #40] ; 0x28 800541c: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8005420: f443 5280 orr.w r2, r3, #4096 ; 0x1000 8005424: 687b ldr r3, [r7, #4] 8005426: 629a str r2, [r3, #40] ; 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 8005428: e01d b.n 8005466 } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800542a: 687b ldr r3, [r7, #4] 800542c: 6a9b ldr r3, [r3, #40] ; 0x28 800542e: f443 1280 orr.w r2, r3, #1048576 ; 0x100000 8005432: 687b ldr r3, [r7, #4] 8005434: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 8005436: 687b ldr r3, [r7, #4] 8005438: 681b ldr r3, [r3, #0] 800543a: 4a2f ldr r2, [pc, #188] ; (80054f8 ) 800543c: 4293 cmp r3, r2 800543e: d004 beq.n 800544a 8005440: 687b ldr r3, [r7, #4] 8005442: 681b ldr r3, [r3, #0] 8005444: 4a2b ldr r2, [pc, #172] ; (80054f4 ) 8005446: 4293 cmp r3, r2 8005448: d10d bne.n 8005466 800544a: 4b2b ldr r3, [pc, #172] ; (80054f8 ) 800544c: 685b ldr r3, [r3, #4] 800544e: f403 6380 and.w r3, r3, #1024 ; 0x400 8005452: 2b00 cmp r3, #0 8005454: d007 beq.n 8005466 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8005456: 687b ldr r3, [r7, #4] 8005458: 6a9b ldr r3, [r3, #40] ; 0x28 800545a: f423 5340 bic.w r3, r3, #12288 ; 0x3000 800545e: f443 5280 orr.w r2, r3, #4096 ; 0x1000 8005462: 687b ldr r3, [r7, #4] 8005464: 629a str r2, [r3, #40] ; 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8005466: 687b ldr r3, [r7, #4] 8005468: 6a9b ldr r3, [r3, #40] ; 0x28 800546a: f403 5380 and.w r3, r3, #4096 ; 0x1000 800546e: 2b00 cmp r3, #0 8005470: d006 beq.n 8005480 { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8005472: 687b ldr r3, [r7, #4] 8005474: 6adb ldr r3, [r3, #44] ; 0x2c 8005476: f023 0206 bic.w r2, r3, #6 800547a: 687b ldr r3, [r7, #4] 800547c: 62da str r2, [r3, #44] ; 0x2c 800547e: e002 b.n 8005486 } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8005480: 687b ldr r3, [r7, #4] 8005482: 2200 movs r2, #0 8005484: 62da str r2, [r3, #44] ; 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8005486: 687b ldr r3, [r7, #4] 8005488: 2200 movs r2, #0 800548a: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Clear regular group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 800548e: 687b ldr r3, [r7, #4] 8005490: 681b ldr r3, [r3, #0] 8005492: f06f 0202 mvn.w r2, #2 8005496: 601a str r2, [r3, #0] /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ /* If ADC is master, ADC is enabled and conversion is started. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8005498: 687b ldr r3, [r7, #4] 800549a: 681b ldr r3, [r3, #0] 800549c: 689b ldr r3, [r3, #8] 800549e: f403 2360 and.w r3, r3, #917504 ; 0xe0000 80054a2: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 80054a6: d113 bne.n 80054d0 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 80054a8: 687b ldr r3, [r7, #4] 80054aa: 681b ldr r3, [r3, #0] if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80054ac: 4a11 ldr r2, [pc, #68] ; (80054f4 ) 80054ae: 4293 cmp r3, r2 80054b0: d105 bne.n 80054be ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 80054b2: 4b11 ldr r3, [pc, #68] ; (80054f8 ) 80054b4: 685b ldr r3, [r3, #4] 80054b6: f403 2370 and.w r3, r3, #983040 ; 0xf0000 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80054ba: 2b00 cmp r3, #0 80054bc: d108 bne.n 80054d0 { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 80054be: 687b ldr r3, [r7, #4] 80054c0: 681b ldr r3, [r3, #0] 80054c2: 689a ldr r2, [r3, #8] 80054c4: 687b ldr r3, [r7, #4] 80054c6: 681b ldr r3, [r3, #0] 80054c8: f442 02a0 orr.w r2, r2, #5242880 ; 0x500000 80054cc: 609a str r2, [r3, #8] 80054ce: e00c b.n 80054ea } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 80054d0: 687b ldr r3, [r7, #4] 80054d2: 681b ldr r3, [r3, #0] 80054d4: 689a ldr r2, [r3, #8] 80054d6: 687b ldr r3, [r7, #4] 80054d8: 681b ldr r3, [r3, #0] 80054da: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 80054de: 609a str r2, [r3, #8] 80054e0: e003 b.n 80054ea } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 80054e2: 687b ldr r3, [r7, #4] 80054e4: 2200 movs r2, #0 80054e6: f883 2024 strb.w r2, [r3, #36] ; 0x24 } /* Return function status */ return tmp_hal_status; 80054ea: 7bfb ldrb r3, [r7, #15] } 80054ec: 4618 mov r0, r3 80054ee: 3710 adds r7, #16 80054f0: 46bd mov sp, r7 80054f2: bd80 pop {r7, pc} 80054f4: 40012800 .word 0x40012800 80054f8: 40012400 .word 0x40012400 080054fc : * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { 80054fc: b580 push {r7, lr} 80054fe: b084 sub sp, #16 8005500: af00 add r7, sp, #0 8005502: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8005504: 2300 movs r3, #0 8005506: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 8005508: 687b ldr r3, [r7, #4] 800550a: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 800550e: 2b01 cmp r3, #1 8005510: d101 bne.n 8005516 8005512: 2302 movs r3, #2 8005514: e01a b.n 800554c 8005516: 687b ldr r3, [r7, #4] 8005518: 2201 movs r2, #1 800551a: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800551e: 6878 ldr r0, [r7, #4] 8005520: f000 fa7c bl 8005a1c 8005524: 4603 mov r3, r0 8005526: 73fb strb r3, [r7, #15] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8005528: 7bfb ldrb r3, [r7, #15] 800552a: 2b00 cmp r3, #0 800552c: d109 bne.n 8005542 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800552e: 687b ldr r3, [r7, #4] 8005530: 6a9b ldr r3, [r3, #40] ; 0x28 8005532: f423 5388 bic.w r3, r3, #4352 ; 0x1100 8005536: f023 0301 bic.w r3, r3, #1 800553a: f043 0201 orr.w r2, r3, #1 800553e: 687b ldr r3, [r7, #4] 8005540: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 8005542: 687b ldr r3, [r7, #4] 8005544: 2200 movs r2, #0 8005546: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 800554a: 7bfb ldrb r3, [r7, #15] } 800554c: 4618 mov r0, r3 800554e: 3710 adds r7, #16 8005550: 46bd mov sp, r7 8005552: bd80 pop {r7, pc} 08005554 : * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { 8005554: b590 push {r4, r7, lr} 8005556: b087 sub sp, #28 8005558: af00 add r7, sp, #0 800555a: 6078 str r0, [r7, #4] 800555c: 6039 str r1, [r7, #0] uint32_t tickstart = 0U; 800555e: 2300 movs r3, #0 8005560: 617b str r3, [r7, #20] /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; 8005562: 2300 movs r3, #0 8005564: 60fb str r3, [r7, #12] uint32_t Conversion_Timeout_CPU_cycles_max = 0U; 8005566: 2300 movs r3, #0 8005568: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Get tick count */ tickstart = HAL_GetTick(); 800556a: f7ff fe13 bl 8005194 800556e: 6178 str r0, [r7, #20] /* Verification that ADC configuration is compliant with polling for */ /* each conversion: */ /* Particular case is ADC configured in DMA mode */ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) 8005570: 687b ldr r3, [r7, #4] 8005572: 681b ldr r3, [r3, #0] 8005574: 689b ldr r3, [r3, #8] 8005576: f403 7380 and.w r3, r3, #256 ; 0x100 800557a: 2b00 cmp r3, #0 800557c: d00b beq.n 8005596 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800557e: 687b ldr r3, [r7, #4] 8005580: 6a9b ldr r3, [r3, #40] ; 0x28 8005582: f043 0220 orr.w r2, r3, #32 8005586: 687b ldr r3, [r7, #4] 8005588: 629a str r2, [r3, #40] ; 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 800558a: 687b ldr r3, [r7, #4] 800558c: 2200 movs r2, #0 800558e: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 8005592: 2301 movs r3, #1 8005594: e0d3 b.n 800573e /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ /* As flag EOC is not set after each conversion, no timeout status can */ /* be set. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 8005596: 687b ldr r3, [r7, #4] 8005598: 681b ldr r3, [r3, #0] 800559a: 685b ldr r3, [r3, #4] 800559c: f403 7380 and.w r3, r3, #256 ; 0x100 80055a0: 2b00 cmp r3, #0 80055a2: d131 bne.n 8005608 HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ) 80055a4: 687b ldr r3, [r7, #4] 80055a6: 681b ldr r3, [r3, #0] 80055a8: 6adb ldr r3, [r3, #44] ; 0x2c 80055aa: f403 0370 and.w r3, r3, #15728640 ; 0xf00000 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 80055ae: 2b00 cmp r3, #0 80055b0: d12a bne.n 8005608 { /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 80055b2: e021 b.n 80055f8 { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 80055b4: 683b ldr r3, [r7, #0] 80055b6: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 80055ba: d01d beq.n 80055f8 { if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) 80055bc: 683b ldr r3, [r7, #0] 80055be: 2b00 cmp r3, #0 80055c0: d007 beq.n 80055d2 80055c2: f7ff fde7 bl 8005194 80055c6: 4602 mov r2, r0 80055c8: 697b ldr r3, [r7, #20] 80055ca: 1ad3 subs r3, r2, r3 80055cc: 683a ldr r2, [r7, #0] 80055ce: 429a cmp r2, r3 80055d0: d212 bcs.n 80055f8 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 80055d2: 687b ldr r3, [r7, #4] 80055d4: 681b ldr r3, [r3, #0] 80055d6: 681b ldr r3, [r3, #0] 80055d8: f003 0302 and.w r3, r3, #2 80055dc: 2b00 cmp r3, #0 80055de: d10b bne.n 80055f8 { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 80055e0: 687b ldr r3, [r7, #4] 80055e2: 6a9b ldr r3, [r3, #40] ; 0x28 80055e4: f043 0204 orr.w r2, r3, #4 80055e8: 687b ldr r3, [r7, #4] 80055ea: 629a str r2, [r3, #40] ; 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 80055ec: 687b ldr r3, [r7, #4] 80055ee: 2200 movs r2, #0 80055f0: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_TIMEOUT; 80055f4: 2303 movs r3, #3 80055f6: e0a2 b.n 800573e while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 80055f8: 687b ldr r3, [r7, #4] 80055fa: 681b ldr r3, [r3, #0] 80055fc: 681b ldr r3, [r3, #0] 80055fe: f003 0302 and.w r3, r3, #2 8005602: 2b00 cmp r3, #0 8005604: d0d6 beq.n 80055b4 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 8005606: e070 b.n 80056ea /* Replace polling by wait for maximum conversion time */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ /* and ADC maximum conversion cycles on all channels. */ /* - Wait for the expected ADC clock cycles delay */ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 8005608: 4b4f ldr r3, [pc, #316] ; (8005748 ) 800560a: 681c ldr r4, [r3, #0] 800560c: 2002 movs r0, #2 800560e: f002 fc0f bl 8007e30 8005612: 4603 mov r3, r0 8005614: fbb4 f2f3 udiv r2, r4, r3 * ADC_CONVCYCLES_MAX_RANGE(hadc) ); 8005618: 687b ldr r3, [r7, #4] 800561a: 681b ldr r3, [r3, #0] 800561c: 6919 ldr r1, [r3, #16] 800561e: 4b4b ldr r3, [pc, #300] ; (800574c ) 8005620: 400b ands r3, r1 8005622: 2b00 cmp r3, #0 8005624: d118 bne.n 8005658 8005626: 687b ldr r3, [r7, #4] 8005628: 681b ldr r3, [r3, #0] 800562a: 68d9 ldr r1, [r3, #12] 800562c: 4b48 ldr r3, [pc, #288] ; (8005750 ) 800562e: 400b ands r3, r1 8005630: 2b00 cmp r3, #0 8005632: d111 bne.n 8005658 8005634: 687b ldr r3, [r7, #4] 8005636: 681b ldr r3, [r3, #0] 8005638: 6919 ldr r1, [r3, #16] 800563a: 4b46 ldr r3, [pc, #280] ; (8005754 ) 800563c: 400b ands r3, r1 800563e: 2b00 cmp r3, #0 8005640: d108 bne.n 8005654 8005642: 687b ldr r3, [r7, #4] 8005644: 681b ldr r3, [r3, #0] 8005646: 68d9 ldr r1, [r3, #12] 8005648: 4b43 ldr r3, [pc, #268] ; (8005758 ) 800564a: 400b ands r3, r1 800564c: 2b00 cmp r3, #0 800564e: d101 bne.n 8005654 8005650: 2314 movs r3, #20 8005652: e020 b.n 8005696 8005654: 2329 movs r3, #41 ; 0x29 8005656: e01e b.n 8005696 8005658: 687b ldr r3, [r7, #4] 800565a: 681b ldr r3, [r3, #0] 800565c: 6919 ldr r1, [r3, #16] 800565e: 4b3d ldr r3, [pc, #244] ; (8005754 ) 8005660: 400b ands r3, r1 8005662: 2b00 cmp r3, #0 8005664: d106 bne.n 8005674 8005666: 687b ldr r3, [r7, #4] 8005668: 681b ldr r3, [r3, #0] 800566a: 68d9 ldr r1, [r3, #12] 800566c: 4b3a ldr r3, [pc, #232] ; (8005758 ) 800566e: 400b ands r3, r1 8005670: 2b00 cmp r3, #0 8005672: d00d beq.n 8005690 8005674: 687b ldr r3, [r7, #4] 8005676: 681b ldr r3, [r3, #0] 8005678: 6919 ldr r1, [r3, #16] 800567a: 4b38 ldr r3, [pc, #224] ; (800575c ) 800567c: 400b ands r3, r1 800567e: 2b00 cmp r3, #0 8005680: d108 bne.n 8005694 8005682: 687b ldr r3, [r7, #4] 8005684: 681b ldr r3, [r3, #0] 8005686: 68d9 ldr r1, [r3, #12] 8005688: 4b34 ldr r3, [pc, #208] ; (800575c ) 800568a: 400b ands r3, r1 800568c: 2b00 cmp r3, #0 800568e: d101 bne.n 8005694 8005690: 2354 movs r3, #84 ; 0x54 8005692: e000 b.n 8005696 8005694: 23fc movs r3, #252 ; 0xfc Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock 8005696: fb02 f303 mul.w r3, r2, r3 800569a: 613b str r3, [r7, #16] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 800569c: e021 b.n 80056e2 { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 800569e: 683b ldr r3, [r7, #0] 80056a0: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 80056a4: d01a beq.n 80056dc { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) 80056a6: 683b ldr r3, [r7, #0] 80056a8: 2b00 cmp r3, #0 80056aa: d007 beq.n 80056bc 80056ac: f7ff fd72 bl 8005194 80056b0: 4602 mov r2, r0 80056b2: 697b ldr r3, [r7, #20] 80056b4: 1ad3 subs r3, r2, r3 80056b6: 683a ldr r2, [r7, #0] 80056b8: 429a cmp r2, r3 80056ba: d20f bcs.n 80056dc { /* New check to avoid false timeout detection in case of preemption */ if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 80056bc: 68fb ldr r3, [r7, #12] 80056be: 693a ldr r2, [r7, #16] 80056c0: 429a cmp r2, r3 80056c2: d90b bls.n 80056dc { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 80056c4: 687b ldr r3, [r7, #4] 80056c6: 6a9b ldr r3, [r3, #40] ; 0x28 80056c8: f043 0204 orr.w r2, r3, #4 80056cc: 687b ldr r3, [r7, #4] 80056ce: 629a str r2, [r3, #40] ; 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 80056d0: 687b ldr r3, [r7, #4] 80056d2: 2200 movs r2, #0 80056d4: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_TIMEOUT; 80056d8: 2303 movs r3, #3 80056da: e030 b.n 800573e } } } Conversion_Timeout_CPU_cycles ++; 80056dc: 68fb ldr r3, [r7, #12] 80056de: 3301 adds r3, #1 80056e0: 60fb str r3, [r7, #12] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 80056e2: 68fb ldr r3, [r7, #12] 80056e4: 693a ldr r2, [r7, #16] 80056e6: 429a cmp r2, r3 80056e8: d8d9 bhi.n 800569e } } /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 80056ea: 687b ldr r3, [r7, #4] 80056ec: 681b ldr r3, [r3, #0] 80056ee: f06f 0212 mvn.w r2, #18 80056f2: 601a str r2, [r3, #0] /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 80056f4: 687b ldr r3, [r7, #4] 80056f6: 6a9b ldr r3, [r3, #40] ; 0x28 80056f8: f443 7200 orr.w r2, r3, #512 ; 0x200 80056fc: 687b ldr r3, [r7, #4] 80056fe: 629a str r2, [r3, #40] ; 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8005700: 687b ldr r3, [r7, #4] 8005702: 681b ldr r3, [r3, #0] 8005704: 689b ldr r3, [r3, #8] 8005706: f403 2360 and.w r3, r3, #917504 ; 0xe0000 800570a: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 800570e: d115 bne.n 800573c (hadc->Init.ContinuousConvMode == DISABLE) ) 8005710: 687b ldr r3, [r7, #4] 8005712: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8005714: 2b00 cmp r3, #0 8005716: d111 bne.n 800573c { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8005718: 687b ldr r3, [r7, #4] 800571a: 6a9b ldr r3, [r3, #40] ; 0x28 800571c: f423 7280 bic.w r2, r3, #256 ; 0x100 8005720: 687b ldr r3, [r7, #4] 8005722: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8005724: 687b ldr r3, [r7, #4] 8005726: 6a9b ldr r3, [r3, #40] ; 0x28 8005728: f403 5380 and.w r3, r3, #4096 ; 0x1000 800572c: 2b00 cmp r3, #0 800572e: d105 bne.n 800573c { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8005730: 687b ldr r3, [r7, #4] 8005732: 6a9b ldr r3, [r3, #40] ; 0x28 8005734: f043 0201 orr.w r2, r3, #1 8005738: 687b ldr r3, [r7, #4] 800573a: 629a str r2, [r3, #40] ; 0x28 } } /* Return ADC state */ return HAL_OK; 800573c: 2300 movs r3, #0 } 800573e: 4618 mov r0, r3 8005740: 371c adds r7, #28 8005742: 46bd mov sp, r7 8005744: bd90 pop {r4, r7, pc} 8005746: bf00 nop 8005748: 20000008 .word 0x20000008 800574c: 24924924 .word 0x24924924 8005750: 00924924 .word 0x00924924 8005754: 12492492 .word 0x12492492 8005758: 00492492 .word 0x00492492 800575c: 00249249 .word 0x00249249 08005760 : * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc: ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { 8005760: b480 push {r7} 8005762: b083 sub sp, #12 8005764: af00 add r7, sp, #0 8005766: 6078 str r0, [r7, #4] /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; 8005768: 687b ldr r3, [r7, #4] 800576a: 681b ldr r3, [r3, #0] 800576c: 6cdb ldr r3, [r3, #76] ; 0x4c } 800576e: 4618 mov r0, r3 8005770: 370c adds r7, #12 8005772: 46bd mov sp, r7 8005774: bc80 pop {r7} 8005776: 4770 bx lr 08005778 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8005778: b480 push {r7} 800577a: b085 sub sp, #20 800577c: af00 add r7, sp, #0 800577e: 6078 str r0, [r7, #4] 8005780: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8005782: 2300 movs r3, #0 8005784: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 8005786: 2300 movs r3, #0 8005788: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 800578a: 687b ldr r3, [r7, #4] 800578c: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8005790: 2b01 cmp r3, #1 8005792: d101 bne.n 8005798 8005794: 2302 movs r3, #2 8005796: e0dc b.n 8005952 8005798: 687b ldr r3, [r7, #4] 800579a: 2201 movs r2, #1 800579c: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 80057a0: 683b ldr r3, [r7, #0] 80057a2: 685b ldr r3, [r3, #4] 80057a4: 2b06 cmp r3, #6 80057a6: d81c bhi.n 80057e2 { MODIFY_REG(hadc->Instance->SQR3 , 80057a8: 687b ldr r3, [r7, #4] 80057aa: 681b ldr r3, [r3, #0] 80057ac: 6b59 ldr r1, [r3, #52] ; 0x34 80057ae: 683b ldr r3, [r7, #0] 80057b0: 685a ldr r2, [r3, #4] 80057b2: 4613 mov r3, r2 80057b4: 009b lsls r3, r3, #2 80057b6: 4413 add r3, r2 80057b8: 3b05 subs r3, #5 80057ba: 221f movs r2, #31 80057bc: fa02 f303 lsl.w r3, r2, r3 80057c0: 43db mvns r3, r3 80057c2: 4019 ands r1, r3 80057c4: 683b ldr r3, [r7, #0] 80057c6: 6818 ldr r0, [r3, #0] 80057c8: 683b ldr r3, [r7, #0] 80057ca: 685a ldr r2, [r3, #4] 80057cc: 4613 mov r3, r2 80057ce: 009b lsls r3, r3, #2 80057d0: 4413 add r3, r2 80057d2: 3b05 subs r3, #5 80057d4: fa00 f203 lsl.w r2, r0, r3 80057d8: 687b ldr r3, [r7, #4] 80057da: 681b ldr r3, [r3, #0] 80057dc: 430a orrs r2, r1 80057de: 635a str r2, [r3, #52] ; 0x34 80057e0: e03c b.n 800585c ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 80057e2: 683b ldr r3, [r7, #0] 80057e4: 685b ldr r3, [r3, #4] 80057e6: 2b0c cmp r3, #12 80057e8: d81c bhi.n 8005824 { MODIFY_REG(hadc->Instance->SQR2 , 80057ea: 687b ldr r3, [r7, #4] 80057ec: 681b ldr r3, [r3, #0] 80057ee: 6b19 ldr r1, [r3, #48] ; 0x30 80057f0: 683b ldr r3, [r7, #0] 80057f2: 685a ldr r2, [r3, #4] 80057f4: 4613 mov r3, r2 80057f6: 009b lsls r3, r3, #2 80057f8: 4413 add r3, r2 80057fa: 3b23 subs r3, #35 ; 0x23 80057fc: 221f movs r2, #31 80057fe: fa02 f303 lsl.w r3, r2, r3 8005802: 43db mvns r3, r3 8005804: 4019 ands r1, r3 8005806: 683b ldr r3, [r7, #0] 8005808: 6818 ldr r0, [r3, #0] 800580a: 683b ldr r3, [r7, #0] 800580c: 685a ldr r2, [r3, #4] 800580e: 4613 mov r3, r2 8005810: 009b lsls r3, r3, #2 8005812: 4413 add r3, r2 8005814: 3b23 subs r3, #35 ; 0x23 8005816: fa00 f203 lsl.w r2, r0, r3 800581a: 687b ldr r3, [r7, #4] 800581c: 681b ldr r3, [r3, #0] 800581e: 430a orrs r2, r1 8005820: 631a str r2, [r3, #48] ; 0x30 8005822: e01b b.n 800585c ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 8005824: 687b ldr r3, [r7, #4] 8005826: 681b ldr r3, [r3, #0] 8005828: 6ad9 ldr r1, [r3, #44] ; 0x2c 800582a: 683b ldr r3, [r7, #0] 800582c: 685a ldr r2, [r3, #4] 800582e: 4613 mov r3, r2 8005830: 009b lsls r3, r3, #2 8005832: 4413 add r3, r2 8005834: 3b41 subs r3, #65 ; 0x41 8005836: 221f movs r2, #31 8005838: fa02 f303 lsl.w r3, r2, r3 800583c: 43db mvns r3, r3 800583e: 4019 ands r1, r3 8005840: 683b ldr r3, [r7, #0] 8005842: 6818 ldr r0, [r3, #0] 8005844: 683b ldr r3, [r7, #0] 8005846: 685a ldr r2, [r3, #4] 8005848: 4613 mov r3, r2 800584a: 009b lsls r3, r3, #2 800584c: 4413 add r3, r2 800584e: 3b41 subs r3, #65 ; 0x41 8005850: fa00 f203 lsl.w r2, r0, r3 8005854: 687b ldr r3, [r7, #4] 8005856: 681b ldr r3, [r3, #0] 8005858: 430a orrs r2, r1 800585a: 62da str r2, [r3, #44] ; 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 800585c: 683b ldr r3, [r7, #0] 800585e: 681b ldr r3, [r3, #0] 8005860: 2b09 cmp r3, #9 8005862: d91c bls.n 800589e { MODIFY_REG(hadc->Instance->SMPR1 , 8005864: 687b ldr r3, [r7, #4] 8005866: 681b ldr r3, [r3, #0] 8005868: 68d9 ldr r1, [r3, #12] 800586a: 683b ldr r3, [r7, #0] 800586c: 681a ldr r2, [r3, #0] 800586e: 4613 mov r3, r2 8005870: 005b lsls r3, r3, #1 8005872: 4413 add r3, r2 8005874: 3b1e subs r3, #30 8005876: 2207 movs r2, #7 8005878: fa02 f303 lsl.w r3, r2, r3 800587c: 43db mvns r3, r3 800587e: 4019 ands r1, r3 8005880: 683b ldr r3, [r7, #0] 8005882: 6898 ldr r0, [r3, #8] 8005884: 683b ldr r3, [r7, #0] 8005886: 681a ldr r2, [r3, #0] 8005888: 4613 mov r3, r2 800588a: 005b lsls r3, r3, #1 800588c: 4413 add r3, r2 800588e: 3b1e subs r3, #30 8005890: fa00 f203 lsl.w r2, r0, r3 8005894: 687b ldr r3, [r7, #4] 8005896: 681b ldr r3, [r3, #0] 8005898: 430a orrs r2, r1 800589a: 60da str r2, [r3, #12] 800589c: e019 b.n 80058d2 ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 800589e: 687b ldr r3, [r7, #4] 80058a0: 681b ldr r3, [r3, #0] 80058a2: 6919 ldr r1, [r3, #16] 80058a4: 683b ldr r3, [r7, #0] 80058a6: 681a ldr r2, [r3, #0] 80058a8: 4613 mov r3, r2 80058aa: 005b lsls r3, r3, #1 80058ac: 4413 add r3, r2 80058ae: 2207 movs r2, #7 80058b0: fa02 f303 lsl.w r3, r2, r3 80058b4: 43db mvns r3, r3 80058b6: 4019 ands r1, r3 80058b8: 683b ldr r3, [r7, #0] 80058ba: 6898 ldr r0, [r3, #8] 80058bc: 683b ldr r3, [r7, #0] 80058be: 681a ldr r2, [r3, #0] 80058c0: 4613 mov r3, r2 80058c2: 005b lsls r3, r3, #1 80058c4: 4413 add r3, r2 80058c6: fa00 f203 lsl.w r2, r0, r3 80058ca: 687b ldr r3, [r7, #4] 80058cc: 681b ldr r3, [r3, #0] 80058ce: 430a orrs r2, r1 80058d0: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 80058d2: 683b ldr r3, [r7, #0] 80058d4: 681b ldr r3, [r3, #0] 80058d6: 2b10 cmp r3, #16 80058d8: d003 beq.n 80058e2 (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 80058da: 683b ldr r3, [r7, #0] 80058dc: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 80058de: 2b11 cmp r3, #17 80058e0: d132 bne.n 8005948 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 80058e2: 687b ldr r3, [r7, #4] 80058e4: 681b ldr r3, [r3, #0] 80058e6: 4a1d ldr r2, [pc, #116] ; (800595c ) 80058e8: 4293 cmp r3, r2 80058ea: d125 bne.n 8005938 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 80058ec: 687b ldr r3, [r7, #4] 80058ee: 681b ldr r3, [r3, #0] 80058f0: 689b ldr r3, [r3, #8] 80058f2: f403 0300 and.w r3, r3, #8388608 ; 0x800000 80058f6: 2b00 cmp r3, #0 80058f8: d126 bne.n 8005948 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 80058fa: 687b ldr r3, [r7, #4] 80058fc: 681b ldr r3, [r3, #0] 80058fe: 689a ldr r2, [r3, #8] 8005900: 687b ldr r3, [r7, #4] 8005902: 681b ldr r3, [r3, #0] 8005904: f442 0200 orr.w r2, r2, #8388608 ; 0x800000 8005908: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 800590a: 683b ldr r3, [r7, #0] 800590c: 681b ldr r3, [r3, #0] 800590e: 2b10 cmp r3, #16 8005910: d11a bne.n 8005948 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 8005912: 4b13 ldr r3, [pc, #76] ; (8005960 ) 8005914: 681b ldr r3, [r3, #0] 8005916: 4a13 ldr r2, [pc, #76] ; (8005964 ) 8005918: fba2 2303 umull r2, r3, r2, r3 800591c: 0c9a lsrs r2, r3, #18 800591e: 4613 mov r3, r2 8005920: 009b lsls r3, r3, #2 8005922: 4413 add r3, r2 8005924: 005b lsls r3, r3, #1 8005926: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8005928: e002 b.n 8005930 { wait_loop_index--; 800592a: 68bb ldr r3, [r7, #8] 800592c: 3b01 subs r3, #1 800592e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8005930: 68bb ldr r3, [r7, #8] 8005932: 2b00 cmp r3, #0 8005934: d1f9 bne.n 800592a 8005936: e007 b.n 8005948 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8005938: 687b ldr r3, [r7, #4] 800593a: 6a9b ldr r3, [r3, #40] ; 0x28 800593c: f043 0220 orr.w r2, r3, #32 8005940: 687b ldr r3, [r7, #4] 8005942: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 8005944: 2301 movs r3, #1 8005946: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8005948: 687b ldr r3, [r7, #4] 800594a: 2200 movs r2, #0 800594c: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 8005950: 7bfb ldrb r3, [r7, #15] } 8005952: 4618 mov r0, r3 8005954: 3714 adds r7, #20 8005956: 46bd mov sp, r7 8005958: bc80 pop {r7} 800595a: 4770 bx lr 800595c: 40012400 .word 0x40012400 8005960: 20000008 .word 0x20000008 8005964: 431bde83 .word 0x431bde83 08005968 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 8005968: b580 push {r7, lr} 800596a: b084 sub sp, #16 800596c: af00 add r7, sp, #0 800596e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8005970: 2300 movs r3, #0 8005972: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 8005974: 2300 movs r3, #0 8005976: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 8005978: 687b ldr r3, [r7, #4] 800597a: 681b ldr r3, [r3, #0] 800597c: 689b ldr r3, [r3, #8] 800597e: f003 0301 and.w r3, r3, #1 8005982: 2b01 cmp r3, #1 8005984: d040 beq.n 8005a08 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 8005986: 687b ldr r3, [r7, #4] 8005988: 681b ldr r3, [r3, #0] 800598a: 689a ldr r2, [r3, #8] 800598c: 687b ldr r3, [r7, #4] 800598e: 681b ldr r3, [r3, #0] 8005990: f042 0201 orr.w r2, r2, #1 8005994: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 8005996: 4b1f ldr r3, [pc, #124] ; (8005a14 ) 8005998: 681b ldr r3, [r3, #0] 800599a: 4a1f ldr r2, [pc, #124] ; (8005a18 ) 800599c: fba2 2303 umull r2, r3, r2, r3 80059a0: 0c9b lsrs r3, r3, #18 80059a2: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80059a4: e002 b.n 80059ac { wait_loop_index--; 80059a6: 68bb ldr r3, [r7, #8] 80059a8: 3b01 subs r3, #1 80059aa: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80059ac: 68bb ldr r3, [r7, #8] 80059ae: 2b00 cmp r3, #0 80059b0: d1f9 bne.n 80059a6 } /* Get tick count */ tickstart = HAL_GetTick(); 80059b2: f7ff fbef bl 8005194 80059b6: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 80059b8: e01f b.n 80059fa { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 80059ba: f7ff fbeb bl 8005194 80059be: 4602 mov r2, r0 80059c0: 68fb ldr r3, [r7, #12] 80059c2: 1ad3 subs r3, r2, r3 80059c4: 2b02 cmp r3, #2 80059c6: d918 bls.n 80059fa { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 80059c8: 687b ldr r3, [r7, #4] 80059ca: 681b ldr r3, [r3, #0] 80059cc: 689b ldr r3, [r3, #8] 80059ce: f003 0301 and.w r3, r3, #1 80059d2: 2b01 cmp r3, #1 80059d4: d011 beq.n 80059fa { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80059d6: 687b ldr r3, [r7, #4] 80059d8: 6a9b ldr r3, [r3, #40] ; 0x28 80059da: f043 0210 orr.w r2, r3, #16 80059de: 687b ldr r3, [r7, #4] 80059e0: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80059e2: 687b ldr r3, [r7, #4] 80059e4: 6adb ldr r3, [r3, #44] ; 0x2c 80059e6: f043 0201 orr.w r2, r3, #1 80059ea: 687b ldr r3, [r7, #4] 80059ec: 62da str r2, [r3, #44] ; 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 80059ee: 687b ldr r3, [r7, #4] 80059f0: 2200 movs r2, #0 80059f2: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 80059f6: 2301 movs r3, #1 80059f8: e007 b.n 8005a0a while(ADC_IS_ENABLE(hadc) == RESET) 80059fa: 687b ldr r3, [r7, #4] 80059fc: 681b ldr r3, [r3, #0] 80059fe: 689b ldr r3, [r3, #8] 8005a00: f003 0301 and.w r3, r3, #1 8005a04: 2b01 cmp r3, #1 8005a06: d1d8 bne.n 80059ba } } } /* Return HAL status */ return HAL_OK; 8005a08: 2300 movs r3, #0 } 8005a0a: 4618 mov r0, r3 8005a0c: 3710 adds r7, #16 8005a0e: 46bd mov sp, r7 8005a10: bd80 pop {r7, pc} 8005a12: bf00 nop 8005a14: 20000008 .word 0x20000008 8005a18: 431bde83 .word 0x431bde83 08005a1c : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 8005a1c: b580 push {r7, lr} 8005a1e: b084 sub sp, #16 8005a20: af00 add r7, sp, #0 8005a22: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8005a24: 2300 movs r3, #0 8005a26: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 8005a28: 687b ldr r3, [r7, #4] 8005a2a: 681b ldr r3, [r3, #0] 8005a2c: 689b ldr r3, [r3, #8] 8005a2e: f003 0301 and.w r3, r3, #1 8005a32: 2b01 cmp r3, #1 8005a34: d12e bne.n 8005a94 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 8005a36: 687b ldr r3, [r7, #4] 8005a38: 681b ldr r3, [r3, #0] 8005a3a: 689a ldr r2, [r3, #8] 8005a3c: 687b ldr r3, [r7, #4] 8005a3e: 681b ldr r3, [r3, #0] 8005a40: f022 0201 bic.w r2, r2, #1 8005a44: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 8005a46: f7ff fba5 bl 8005194 8005a4a: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 8005a4c: e01b b.n 8005a86 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8005a4e: f7ff fba1 bl 8005194 8005a52: 4602 mov r2, r0 8005a54: 68fb ldr r3, [r7, #12] 8005a56: 1ad3 subs r3, r2, r3 8005a58: 2b02 cmp r3, #2 8005a5a: d914 bls.n 8005a86 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 8005a5c: 687b ldr r3, [r7, #4] 8005a5e: 681b ldr r3, [r3, #0] 8005a60: 689b ldr r3, [r3, #8] 8005a62: f003 0301 and.w r3, r3, #1 8005a66: 2b01 cmp r3, #1 8005a68: d10d bne.n 8005a86 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8005a6a: 687b ldr r3, [r7, #4] 8005a6c: 6a9b ldr r3, [r3, #40] ; 0x28 8005a6e: f043 0210 orr.w r2, r3, #16 8005a72: 687b ldr r3, [r7, #4] 8005a74: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8005a76: 687b ldr r3, [r7, #4] 8005a78: 6adb ldr r3, [r3, #44] ; 0x2c 8005a7a: f043 0201 orr.w r2, r3, #1 8005a7e: 687b ldr r3, [r7, #4] 8005a80: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 8005a82: 2301 movs r3, #1 8005a84: e007 b.n 8005a96 while(ADC_IS_ENABLE(hadc) != RESET) 8005a86: 687b ldr r3, [r7, #4] 8005a88: 681b ldr r3, [r3, #0] 8005a8a: 689b ldr r3, [r3, #8] 8005a8c: f003 0301 and.w r3, r3, #1 8005a90: 2b01 cmp r3, #1 8005a92: d0dc beq.n 8005a4e } } } /* Return HAL status */ return HAL_OK; 8005a94: 2300 movs r3, #0 } 8005a96: 4618 mov r0, r3 8005a98: 3710 adds r7, #16 8005a9a: 46bd mov sp, r7 8005a9c: bd80 pop {r7, pc} ... 08005aa0 : * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { 8005aa0: b590 push {r4, r7, lr} 8005aa2: b087 sub sp, #28 8005aa4: af00 add r7, sp, #0 8005aa6: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8005aa8: 2300 movs r3, #0 8005aaa: 75fb strb r3, [r7, #23] uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; 8005aac: 2300 movs r3, #0 8005aae: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 8005ab0: 687b ldr r3, [r7, #4] 8005ab2: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8005ab6: 2b01 cmp r3, #1 8005ab8: d101 bne.n 8005abe 8005aba: 2302 movs r3, #2 8005abc: e095 b.n 8005bea 8005abe: 687b ldr r3, [r7, #4] 8005ac0: 2201 movs r2, #1 8005ac2: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* 1. Calibration prerequisite: */ /* - ADC must be disabled for at least two ADC clock cycles in disable */ /* mode before ADC enable */ /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8005ac6: 6878 ldr r0, [r7, #4] 8005ac8: f7ff ffa8 bl 8005a1c 8005acc: 4603 mov r3, r0 8005ace: 75fb strb r3, [r7, #23] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8005ad0: 7dfb ldrb r3, [r7, #23] 8005ad2: 2b00 cmp r3, #0 8005ad4: f040 8084 bne.w 8005be0 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8005ad8: 687b ldr r3, [r7, #4] 8005ada: 6a9b ldr r3, [r3, #40] ; 0x28 8005adc: f423 5388 bic.w r3, r3, #4352 ; 0x1100 8005ae0: f023 0302 bic.w r3, r3, #2 8005ae4: f043 0202 orr.w r2, r3, #2 8005ae8: 687b ldr r3, [r7, #4] 8005aea: 629a str r2, [r3, #40] ; 0x28 /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 8005aec: 4b41 ldr r3, [pc, #260] ; (8005bf4 ) 8005aee: 681c ldr r4, [r3, #0] 8005af0: 2002 movs r0, #2 8005af2: f002 f99d bl 8007e30 8005af6: 4603 mov r3, r0 8005af8: fbb4 f3f3 udiv r3, r4, r3 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 8005afc: 005b lsls r3, r3, #1 wait_loop_index = ((SystemCoreClock 8005afe: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 8005b00: e002 b.n 8005b08 { wait_loop_index--; 8005b02: 68fb ldr r3, [r7, #12] 8005b04: 3b01 subs r3, #1 8005b06: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 8005b08: 68fb ldr r3, [r7, #12] 8005b0a: 2b00 cmp r3, #0 8005b0c: d1f9 bne.n 8005b02 } /* 2. Enable the ADC peripheral */ ADC_Enable(hadc); 8005b0e: 6878 ldr r0, [r7, #4] 8005b10: f7ff ff2a bl 8005968 /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 8005b14: 687b ldr r3, [r7, #4] 8005b16: 681b ldr r3, [r3, #0] 8005b18: 689a ldr r2, [r3, #8] 8005b1a: 687b ldr r3, [r7, #4] 8005b1c: 681b ldr r3, [r3, #0] 8005b1e: f042 0208 orr.w r2, r2, #8 8005b22: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 8005b24: f7ff fb36 bl 8005194 8005b28: 6138 str r0, [r7, #16] /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 8005b2a: e01b b.n 8005b64 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 8005b2c: f7ff fb32 bl 8005194 8005b30: 4602 mov r2, r0 8005b32: 693b ldr r3, [r7, #16] 8005b34: 1ad3 subs r3, r2, r3 8005b36: 2b0a cmp r3, #10 8005b38: d914 bls.n 8005b64 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 8005b3a: 687b ldr r3, [r7, #4] 8005b3c: 681b ldr r3, [r3, #0] 8005b3e: 689b ldr r3, [r3, #8] 8005b40: f003 0308 and.w r3, r3, #8 8005b44: 2b00 cmp r3, #0 8005b46: d00d beq.n 8005b64 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8005b48: 687b ldr r3, [r7, #4] 8005b4a: 6a9b ldr r3, [r3, #40] ; 0x28 8005b4c: f023 0312 bic.w r3, r3, #18 8005b50: f043 0210 orr.w r2, r3, #16 8005b54: 687b ldr r3, [r7, #4] 8005b56: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 8005b58: 687b ldr r3, [r7, #4] 8005b5a: 2200 movs r2, #0 8005b5c: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 8005b60: 2301 movs r3, #1 8005b62: e042 b.n 8005bea while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 8005b64: 687b ldr r3, [r7, #4] 8005b66: 681b ldr r3, [r3, #0] 8005b68: 689b ldr r3, [r3, #8] 8005b6a: f003 0308 and.w r3, r3, #8 8005b6e: 2b00 cmp r3, #0 8005b70: d1dc bne.n 8005b2c } } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 8005b72: 687b ldr r3, [r7, #4] 8005b74: 681b ldr r3, [r3, #0] 8005b76: 689a ldr r2, [r3, #8] 8005b78: 687b ldr r3, [r7, #4] 8005b7a: 681b ldr r3, [r3, #0] 8005b7c: f042 0204 orr.w r2, r2, #4 8005b80: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 8005b82: f7ff fb07 bl 8005194 8005b86: 6138 str r0, [r7, #16] /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 8005b88: e01b b.n 8005bc2 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 8005b8a: f7ff fb03 bl 8005194 8005b8e: 4602 mov r2, r0 8005b90: 693b ldr r3, [r7, #16] 8005b92: 1ad3 subs r3, r2, r3 8005b94: 2b0a cmp r3, #10 8005b96: d914 bls.n 8005bc2 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 8005b98: 687b ldr r3, [r7, #4] 8005b9a: 681b ldr r3, [r3, #0] 8005b9c: 689b ldr r3, [r3, #8] 8005b9e: f003 0304 and.w r3, r3, #4 8005ba2: 2b00 cmp r3, #0 8005ba4: d00d beq.n 8005bc2 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8005ba6: 687b ldr r3, [r7, #4] 8005ba8: 6a9b ldr r3, [r3, #40] ; 0x28 8005baa: f023 0312 bic.w r3, r3, #18 8005bae: f043 0210 orr.w r2, r3, #16 8005bb2: 687b ldr r3, [r7, #4] 8005bb4: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 8005bb6: 687b ldr r3, [r7, #4] 8005bb8: 2200 movs r2, #0 8005bba: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 8005bbe: 2301 movs r3, #1 8005bc0: e013 b.n 8005bea while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 8005bc2: 687b ldr r3, [r7, #4] 8005bc4: 681b ldr r3, [r3, #0] 8005bc6: 689b ldr r3, [r3, #8] 8005bc8: f003 0304 and.w r3, r3, #4 8005bcc: 2b00 cmp r3, #0 8005bce: d1dc bne.n 8005b8a } } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8005bd0: 687b ldr r3, [r7, #4] 8005bd2: 6a9b ldr r3, [r3, #40] ; 0x28 8005bd4: f023 0303 bic.w r3, r3, #3 8005bd8: f043 0201 orr.w r2, r3, #1 8005bdc: 687b ldr r3, [r7, #4] 8005bde: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 8005be0: 687b ldr r3, [r7, #4] 8005be2: 2200 movs r2, #0 8005be4: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 8005be8: 7dfb ldrb r3, [r7, #23] } 8005bea: 4618 mov r0, r3 8005bec: 371c adds r7, #28 8005bee: 46bd mov sp, r7 8005bf0: bd90 pop {r4, r7, pc} 8005bf2: bf00 nop 8005bf4: 20000008 .word 0x20000008 08005bf8 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { 8005bf8: b580 push {r7, lr} 8005bfa: b084 sub sp, #16 8005bfc: af00 add r7, sp, #0 8005bfe: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) 8005c00: 687b ldr r3, [r7, #4] 8005c02: 2b00 cmp r3, #0 8005c04: d101 bne.n 8005c0a { return HAL_ERROR; 8005c06: 2301 movs r3, #1 8005c08: e0ed b.n 8005de6 /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) 8005c0a: 687b ldr r3, [r7, #4] 8005c0c: f893 3020 ldrb.w r3, [r3, #32] 8005c10: b2db uxtb r3, r3 8005c12: 2b00 cmp r3, #0 8005c14: d102 bne.n 8005c1c { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); 8005c16: 6878 ldr r0, [r7, #4] 8005c18: f7fb feee bl 80019f8 } #endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 8005c1c: 687b ldr r3, [r7, #4] 8005c1e: 681b ldr r3, [r3, #0] 8005c20: 681a ldr r2, [r3, #0] 8005c22: 687b ldr r3, [r7, #4] 8005c24: 681b ldr r3, [r3, #0] 8005c26: f042 0201 orr.w r2, r2, #1 8005c2a: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8005c2c: f7ff fab2 bl 8005194 8005c30: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 8005c32: e012 b.n 8005c5a { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 8005c34: f7ff faae bl 8005194 8005c38: 4602 mov r2, r0 8005c3a: 68fb ldr r3, [r7, #12] 8005c3c: 1ad3 subs r3, r2, r3 8005c3e: 2b0a cmp r3, #10 8005c40: d90b bls.n 8005c5a { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 8005c42: 687b ldr r3, [r7, #4] 8005c44: 6a5b ldr r3, [r3, #36] ; 0x24 8005c46: f443 3200 orr.w r2, r3, #131072 ; 0x20000 8005c4a: 687b ldr r3, [r7, #4] 8005c4c: 625a str r2, [r3, #36] ; 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 8005c4e: 687b ldr r3, [r7, #4] 8005c50: 2205 movs r2, #5 8005c52: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8005c56: 2301 movs r3, #1 8005c58: e0c5 b.n 8005de6 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 8005c5a: 687b ldr r3, [r7, #4] 8005c5c: 681b ldr r3, [r3, #0] 8005c5e: 685b ldr r3, [r3, #4] 8005c60: f003 0301 and.w r3, r3, #1 8005c64: 2b00 cmp r3, #0 8005c66: d0e5 beq.n 8005c34 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 8005c68: 687b ldr r3, [r7, #4] 8005c6a: 681b ldr r3, [r3, #0] 8005c6c: 681a ldr r2, [r3, #0] 8005c6e: 687b ldr r3, [r7, #4] 8005c70: 681b ldr r3, [r3, #0] 8005c72: f022 0202 bic.w r2, r2, #2 8005c76: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8005c78: f7ff fa8c bl 8005194 8005c7c: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 8005c7e: e012 b.n 8005ca6 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 8005c80: f7ff fa88 bl 8005194 8005c84: 4602 mov r2, r0 8005c86: 68fb ldr r3, [r7, #12] 8005c88: 1ad3 subs r3, r2, r3 8005c8a: 2b0a cmp r3, #10 8005c8c: d90b bls.n 8005ca6 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 8005c8e: 687b ldr r3, [r7, #4] 8005c90: 6a5b ldr r3, [r3, #36] ; 0x24 8005c92: f443 3200 orr.w r2, r3, #131072 ; 0x20000 8005c96: 687b ldr r3, [r7, #4] 8005c98: 625a str r2, [r3, #36] ; 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 8005c9a: 687b ldr r3, [r7, #4] 8005c9c: 2205 movs r2, #5 8005c9e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8005ca2: 2301 movs r3, #1 8005ca4: e09f b.n 8005de6 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 8005ca6: 687b ldr r3, [r7, #4] 8005ca8: 681b ldr r3, [r3, #0] 8005caa: 685b ldr r3, [r3, #4] 8005cac: f003 0302 and.w r3, r3, #2 8005cb0: 2b00 cmp r3, #0 8005cb2: d1e5 bne.n 8005c80 } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) 8005cb4: 687b ldr r3, [r7, #4] 8005cb6: 7e1b ldrb r3, [r3, #24] 8005cb8: 2b01 cmp r3, #1 8005cba: d108 bne.n 8005cce { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 8005cbc: 687b ldr r3, [r7, #4] 8005cbe: 681b ldr r3, [r3, #0] 8005cc0: 681a ldr r2, [r3, #0] 8005cc2: 687b ldr r3, [r7, #4] 8005cc4: 681b ldr r3, [r3, #0] 8005cc6: f042 0280 orr.w r2, r2, #128 ; 0x80 8005cca: 601a str r2, [r3, #0] 8005ccc: e007 b.n 8005cde } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 8005cce: 687b ldr r3, [r7, #4] 8005cd0: 681b ldr r3, [r3, #0] 8005cd2: 681a ldr r2, [r3, #0] 8005cd4: 687b ldr r3, [r7, #4] 8005cd6: 681b ldr r3, [r3, #0] 8005cd8: f022 0280 bic.w r2, r2, #128 ; 0x80 8005cdc: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) 8005cde: 687b ldr r3, [r7, #4] 8005ce0: 7e5b ldrb r3, [r3, #25] 8005ce2: 2b01 cmp r3, #1 8005ce4: d108 bne.n 8005cf8 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 8005ce6: 687b ldr r3, [r7, #4] 8005ce8: 681b ldr r3, [r3, #0] 8005cea: 681a ldr r2, [r3, #0] 8005cec: 687b ldr r3, [r7, #4] 8005cee: 681b ldr r3, [r3, #0] 8005cf0: f042 0240 orr.w r2, r2, #64 ; 0x40 8005cf4: 601a str r2, [r3, #0] 8005cf6: e007 b.n 8005d08 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 8005cf8: 687b ldr r3, [r7, #4] 8005cfa: 681b ldr r3, [r3, #0] 8005cfc: 681a ldr r2, [r3, #0] 8005cfe: 687b ldr r3, [r7, #4] 8005d00: 681b ldr r3, [r3, #0] 8005d02: f022 0240 bic.w r2, r2, #64 ; 0x40 8005d06: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) 8005d08: 687b ldr r3, [r7, #4] 8005d0a: 7e9b ldrb r3, [r3, #26] 8005d0c: 2b01 cmp r3, #1 8005d0e: d108 bne.n 8005d22 { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 8005d10: 687b ldr r3, [r7, #4] 8005d12: 681b ldr r3, [r3, #0] 8005d14: 681a ldr r2, [r3, #0] 8005d16: 687b ldr r3, [r7, #4] 8005d18: 681b ldr r3, [r3, #0] 8005d1a: f042 0220 orr.w r2, r2, #32 8005d1e: 601a str r2, [r3, #0] 8005d20: e007 b.n 8005d32 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 8005d22: 687b ldr r3, [r7, #4] 8005d24: 681b ldr r3, [r3, #0] 8005d26: 681a ldr r2, [r3, #0] 8005d28: 687b ldr r3, [r7, #4] 8005d2a: 681b ldr r3, [r3, #0] 8005d2c: f022 0220 bic.w r2, r2, #32 8005d30: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) 8005d32: 687b ldr r3, [r7, #4] 8005d34: 7edb ldrb r3, [r3, #27] 8005d36: 2b01 cmp r3, #1 8005d38: d108 bne.n 8005d4c { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); 8005d3a: 687b ldr r3, [r7, #4] 8005d3c: 681b ldr r3, [r3, #0] 8005d3e: 681a ldr r2, [r3, #0] 8005d40: 687b ldr r3, [r7, #4] 8005d42: 681b ldr r3, [r3, #0] 8005d44: f022 0210 bic.w r2, r2, #16 8005d48: 601a str r2, [r3, #0] 8005d4a: e007 b.n 8005d5c } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); 8005d4c: 687b ldr r3, [r7, #4] 8005d4e: 681b ldr r3, [r3, #0] 8005d50: 681a ldr r2, [r3, #0] 8005d52: 687b ldr r3, [r7, #4] 8005d54: 681b ldr r3, [r3, #0] 8005d56: f042 0210 orr.w r2, r2, #16 8005d5a: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) 8005d5c: 687b ldr r3, [r7, #4] 8005d5e: 7f1b ldrb r3, [r3, #28] 8005d60: 2b01 cmp r3, #1 8005d62: d108 bne.n 8005d76 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 8005d64: 687b ldr r3, [r7, #4] 8005d66: 681b ldr r3, [r3, #0] 8005d68: 681a ldr r2, [r3, #0] 8005d6a: 687b ldr r3, [r7, #4] 8005d6c: 681b ldr r3, [r3, #0] 8005d6e: f042 0208 orr.w r2, r2, #8 8005d72: 601a str r2, [r3, #0] 8005d74: e007 b.n 8005d86 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 8005d76: 687b ldr r3, [r7, #4] 8005d78: 681b ldr r3, [r3, #0] 8005d7a: 681a ldr r2, [r3, #0] 8005d7c: 687b ldr r3, [r7, #4] 8005d7e: 681b ldr r3, [r3, #0] 8005d80: f022 0208 bic.w r2, r2, #8 8005d84: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) 8005d86: 687b ldr r3, [r7, #4] 8005d88: 7f5b ldrb r3, [r3, #29] 8005d8a: 2b01 cmp r3, #1 8005d8c: d108 bne.n 8005da0 { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 8005d8e: 687b ldr r3, [r7, #4] 8005d90: 681b ldr r3, [r3, #0] 8005d92: 681a ldr r2, [r3, #0] 8005d94: 687b ldr r3, [r7, #4] 8005d96: 681b ldr r3, [r3, #0] 8005d98: f042 0204 orr.w r2, r2, #4 8005d9c: 601a str r2, [r3, #0] 8005d9e: e007 b.n 8005db0 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 8005da0: 687b ldr r3, [r7, #4] 8005da2: 681b ldr r3, [r3, #0] 8005da4: 681a ldr r2, [r3, #0] 8005da6: 687b ldr r3, [r7, #4] 8005da8: 681b ldr r3, [r3, #0] 8005daa: f022 0204 bic.w r2, r2, #4 8005dae: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | 8005db0: 687b ldr r3, [r7, #4] 8005db2: 689a ldr r2, [r3, #8] 8005db4: 687b ldr r3, [r7, #4] 8005db6: 68db ldr r3, [r3, #12] 8005db8: 431a orrs r2, r3 8005dba: 687b ldr r3, [r7, #4] 8005dbc: 691b ldr r3, [r3, #16] 8005dbe: 431a orrs r2, r3 8005dc0: 687b ldr r3, [r7, #4] 8005dc2: 695b ldr r3, [r3, #20] 8005dc4: ea42 0103 orr.w r1, r2, r3 8005dc8: 687b ldr r3, [r7, #4] 8005dca: 685b ldr r3, [r3, #4] 8005dcc: 1e5a subs r2, r3, #1 8005dce: 687b ldr r3, [r7, #4] 8005dd0: 681b ldr r3, [r3, #0] 8005dd2: 430a orrs r2, r1 8005dd4: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 8005dd6: 687b ldr r3, [r7, #4] 8005dd8: 2200 movs r2, #0 8005dda: 625a str r2, [r3, #36] ; 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; 8005ddc: 687b ldr r3, [r7, #4] 8005dde: 2201 movs r2, #1 8005de0: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 8005de4: 2300 movs r3, #0 } 8005de6: 4618 mov r0, r3 8005de8: 3710 adds r7, #16 8005dea: 46bd mov sp, r7 8005dec: bd80 pop {r7, pc} ... 08005df0 : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) { 8005df0: b480 push {r7} 8005df2: b087 sub sp, #28 8005df4: af00 add r7, sp, #0 8005df6: 6078 str r0, [r7, #4] 8005df8: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; 8005dfa: 687b ldr r3, [r7, #4] 8005dfc: 681b ldr r3, [r3, #0] 8005dfe: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; 8005e00: 687b ldr r3, [r7, #4] 8005e02: f893 3020 ldrb.w r3, [r3, #32] 8005e06: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || 8005e08: 7cfb ldrb r3, [r7, #19] 8005e0a: 2b01 cmp r3, #1 8005e0c: d003 beq.n 8005e16 8005e0e: 7cfb ldrb r3, [r7, #19] 8005e10: 2b02 cmp r3, #2 8005e12: f040 80be bne.w 8005f92 assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); #if defined(CAN2) /* CAN1 and CAN2 are dual instances with 28 common filters banks */ /* Select master instance to access the filter banks */ can_ip = CAN1; 8005e16: 4b65 ldr r3, [pc, #404] ; (8005fac ) 8005e18: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); #endif /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); 8005e1a: 697b ldr r3, [r7, #20] 8005e1c: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 8005e20: f043 0201 orr.w r2, r3, #1 8005e24: 697b ldr r3, [r7, #20] 8005e26: f8c3 2200 str.w r2, [r3, #512] ; 0x200 #if defined(CAN2) /* Select the start filter number of CAN2 slave instance */ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); 8005e2a: 697b ldr r3, [r7, #20] 8005e2c: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 8005e30: f423 527c bic.w r2, r3, #16128 ; 0x3f00 8005e34: 697b ldr r3, [r7, #20] 8005e36: f8c3 2200 str.w r2, [r3, #512] ; 0x200 SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); 8005e3a: 697b ldr r3, [r7, #20] 8005e3c: f8d3 2200 ldr.w r2, [r3, #512] ; 0x200 8005e40: 683b ldr r3, [r7, #0] 8005e42: 6a5b ldr r3, [r3, #36] ; 0x24 8005e44: 021b lsls r3, r3, #8 8005e46: 431a orrs r2, r3 8005e48: 697b ldr r3, [r7, #20] 8005e4a: f8c3 2200 str.w r2, [r3, #512] ; 0x200 #endif /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); 8005e4e: 683b ldr r3, [r7, #0] 8005e50: 695b ldr r3, [r3, #20] 8005e52: f003 031f and.w r3, r3, #31 8005e56: 2201 movs r2, #1 8005e58: fa02 f303 lsl.w r3, r2, r3 8005e5c: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); 8005e5e: 697b ldr r3, [r7, #20] 8005e60: f8d3 221c ldr.w r2, [r3, #540] ; 0x21c 8005e64: 68fb ldr r3, [r7, #12] 8005e66: 43db mvns r3, r3 8005e68: 401a ands r2, r3 8005e6a: 697b ldr r3, [r7, #20] 8005e6c: f8c3 221c str.w r2, [r3, #540] ; 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) 8005e70: 683b ldr r3, [r7, #0] 8005e72: 69db ldr r3, [r3, #28] 8005e74: 2b00 cmp r3, #0 8005e76: d123 bne.n 8005ec0 { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); 8005e78: 697b ldr r3, [r7, #20] 8005e7a: f8d3 220c ldr.w r2, [r3, #524] ; 0x20c 8005e7e: 68fb ldr r3, [r7, #12] 8005e80: 43db mvns r3, r3 8005e82: 401a ands r2, r3 8005e84: 697b ldr r3, [r7, #20] 8005e86: f8c3 220c str.w r2, [r3, #524] ; 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 8005e8a: 683b ldr r3, [r7, #0] 8005e8c: 68db ldr r3, [r3, #12] 8005e8e: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 8005e90: 683b ldr r3, [r7, #0] 8005e92: 685b ldr r3, [r3, #4] 8005e94: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 8005e96: 683a ldr r2, [r7, #0] 8005e98: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 8005e9a: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 8005e9c: 697b ldr r3, [r7, #20] 8005e9e: 3248 adds r2, #72 ; 0x48 8005ea0: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 8005ea4: 683b ldr r3, [r7, #0] 8005ea6: 689b ldr r3, [r3, #8] 8005ea8: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); 8005eaa: 683b ldr r3, [r7, #0] 8005eac: 681b ldr r3, [r3, #0] 8005eae: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 8005eb0: 683b ldr r3, [r7, #0] 8005eb2: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 8005eb4: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 8005eb6: 6979 ldr r1, [r7, #20] 8005eb8: 3348 adds r3, #72 ; 0x48 8005eba: 00db lsls r3, r3, #3 8005ebc: 440b add r3, r1 8005ebe: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) 8005ec0: 683b ldr r3, [r7, #0] 8005ec2: 69db ldr r3, [r3, #28] 8005ec4: 2b01 cmp r3, #1 8005ec6: d122 bne.n 8005f0e { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); 8005ec8: 697b ldr r3, [r7, #20] 8005eca: f8d3 220c ldr.w r2, [r3, #524] ; 0x20c 8005ece: 68fb ldr r3, [r7, #12] 8005ed0: 431a orrs r2, r3 8005ed2: 697b ldr r3, [r7, #20] 8005ed4: f8c3 220c str.w r2, [r3, #524] ; 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 8005ed8: 683b ldr r3, [r7, #0] 8005eda: 681b ldr r3, [r3, #0] 8005edc: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 8005ede: 683b ldr r3, [r7, #0] 8005ee0: 685b ldr r3, [r3, #4] 8005ee2: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 8005ee4: 683a ldr r2, [r7, #0] 8005ee6: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 8005ee8: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 8005eea: 697b ldr r3, [r7, #20] 8005eec: 3248 adds r2, #72 ; 0x48 8005eee: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 8005ef2: 683b ldr r3, [r7, #0] 8005ef4: 689b ldr r3, [r3, #8] 8005ef6: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); 8005ef8: 683b ldr r3, [r7, #0] 8005efa: 68db ldr r3, [r3, #12] 8005efc: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 8005efe: 683b ldr r3, [r7, #0] 8005f00: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 8005f02: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 8005f04: 6979 ldr r1, [r7, #20] 8005f06: 3348 adds r3, #72 ; 0x48 8005f08: 00db lsls r3, r3, #3 8005f0a: 440b add r3, r1 8005f0c: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) 8005f0e: 683b ldr r3, [r7, #0] 8005f10: 699b ldr r3, [r3, #24] 8005f12: 2b00 cmp r3, #0 8005f14: d109 bne.n 8005f2a { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); 8005f16: 697b ldr r3, [r7, #20] 8005f18: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 8005f1c: 68fb ldr r3, [r7, #12] 8005f1e: 43db mvns r3, r3 8005f20: 401a ands r2, r3 8005f22: 697b ldr r3, [r7, #20] 8005f24: f8c3 2204 str.w r2, [r3, #516] ; 0x204 8005f28: e007 b.n 8005f3a } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); 8005f2a: 697b ldr r3, [r7, #20] 8005f2c: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 8005f30: 68fb ldr r3, [r7, #12] 8005f32: 431a orrs r2, r3 8005f34: 697b ldr r3, [r7, #20] 8005f36: f8c3 2204 str.w r2, [r3, #516] ; 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) 8005f3a: 683b ldr r3, [r7, #0] 8005f3c: 691b ldr r3, [r3, #16] 8005f3e: 2b00 cmp r3, #0 8005f40: d109 bne.n 8005f56 { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); 8005f42: 697b ldr r3, [r7, #20] 8005f44: f8d3 2214 ldr.w r2, [r3, #532] ; 0x214 8005f48: 68fb ldr r3, [r7, #12] 8005f4a: 43db mvns r3, r3 8005f4c: 401a ands r2, r3 8005f4e: 697b ldr r3, [r7, #20] 8005f50: f8c3 2214 str.w r2, [r3, #532] ; 0x214 8005f54: e007 b.n 8005f66 } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); 8005f56: 697b ldr r3, [r7, #20] 8005f58: f8d3 2214 ldr.w r2, [r3, #532] ; 0x214 8005f5c: 68fb ldr r3, [r7, #12] 8005f5e: 431a orrs r2, r3 8005f60: 697b ldr r3, [r7, #20] 8005f62: f8c3 2214 str.w r2, [r3, #532] ; 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) 8005f66: 683b ldr r3, [r7, #0] 8005f68: 6a1b ldr r3, [r3, #32] 8005f6a: 2b01 cmp r3, #1 8005f6c: d107 bne.n 8005f7e { SET_BIT(can_ip->FA1R, filternbrbitpos); 8005f6e: 697b ldr r3, [r7, #20] 8005f70: f8d3 221c ldr.w r2, [r3, #540] ; 0x21c 8005f74: 68fb ldr r3, [r7, #12] 8005f76: 431a orrs r2, r3 8005f78: 697b ldr r3, [r7, #20] 8005f7a: f8c3 221c str.w r2, [r3, #540] ; 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); 8005f7e: 697b ldr r3, [r7, #20] 8005f80: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 8005f84: f023 0201 bic.w r2, r3, #1 8005f88: 697b ldr r3, [r7, #20] 8005f8a: f8c3 2200 str.w r2, [r3, #512] ; 0x200 /* Return function status */ return HAL_OK; 8005f8e: 2300 movs r3, #0 8005f90: e006 b.n 8005fa0 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8005f92: 687b ldr r3, [r7, #4] 8005f94: 6a5b ldr r3, [r3, #36] ; 0x24 8005f96: f443 2280 orr.w r2, r3, #262144 ; 0x40000 8005f9a: 687b ldr r3, [r7, #4] 8005f9c: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8005f9e: 2301 movs r3, #1 } } 8005fa0: 4618 mov r0, r3 8005fa2: 371c adds r7, #28 8005fa4: 46bd mov sp, r7 8005fa6: bc80 pop {r7} 8005fa8: 4770 bx lr 8005faa: bf00 nop 8005fac: 40006400 .word 0x40006400 08005fb0 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { 8005fb0: b580 push {r7, lr} 8005fb2: b084 sub sp, #16 8005fb4: af00 add r7, sp, #0 8005fb6: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) 8005fb8: 687b ldr r3, [r7, #4] 8005fba: f893 3020 ldrb.w r3, [r3, #32] 8005fbe: b2db uxtb r3, r3 8005fc0: 2b01 cmp r3, #1 8005fc2: d12e bne.n 8006022 { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; 8005fc4: 687b ldr r3, [r7, #4] 8005fc6: 2202 movs r2, #2 8005fc8: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 8005fcc: 687b ldr r3, [r7, #4] 8005fce: 681b ldr r3, [r3, #0] 8005fd0: 681a ldr r2, [r3, #0] 8005fd2: 687b ldr r3, [r7, #4] 8005fd4: 681b ldr r3, [r3, #0] 8005fd6: f022 0201 bic.w r2, r2, #1 8005fda: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8005fdc: f7ff f8da bl 8005194 8005fe0: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 8005fe2: e012 b.n 800600a { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 8005fe4: f7ff f8d6 bl 8005194 8005fe8: 4602 mov r2, r0 8005fea: 68fb ldr r3, [r7, #12] 8005fec: 1ad3 subs r3, r2, r3 8005fee: 2b0a cmp r3, #10 8005ff0: d90b bls.n 800600a { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 8005ff2: 687b ldr r3, [r7, #4] 8005ff4: 6a5b ldr r3, [r3, #36] ; 0x24 8005ff6: f443 3200 orr.w r2, r3, #131072 ; 0x20000 8005ffa: 687b ldr r3, [r7, #4] 8005ffc: 625a str r2, [r3, #36] ; 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 8005ffe: 687b ldr r3, [r7, #4] 8006000: 2205 movs r2, #5 8006002: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8006006: 2301 movs r3, #1 8006008: e012 b.n 8006030 while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800600a: 687b ldr r3, [r7, #4] 800600c: 681b ldr r3, [r3, #0] 800600e: 685b ldr r3, [r3, #4] 8006010: f003 0301 and.w r3, r3, #1 8006014: 2b00 cmp r3, #0 8006016: d1e5 bne.n 8005fe4 } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 8006018: 687b ldr r3, [r7, #4] 800601a: 2200 movs r2, #0 800601c: 625a str r2, [r3, #36] ; 0x24 /* Return function status */ return HAL_OK; 800601e: 2300 movs r3, #0 8006020: e006 b.n 8006030 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; 8006022: 687b ldr r3, [r7, #4] 8006024: 6a5b ldr r3, [r3, #36] ; 0x24 8006026: f443 2200 orr.w r2, r3, #524288 ; 0x80000 800602a: 687b ldr r3, [r7, #4] 800602c: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 800602e: 2301 movs r3, #1 } } 8006030: 4618 mov r0, r3 8006032: 3710 adds r7, #16 8006034: 46bd mov sp, r7 8006036: bd80 pop {r7, pc} 08006038 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { 8006038: b580 push {r7, lr} 800603a: b084 sub sp, #16 800603c: af00 add r7, sp, #0 800603e: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_LISTENING) 8006040: 687b ldr r3, [r7, #4] 8006042: f893 3020 ldrb.w r3, [r3, #32] 8006046: b2db uxtb r3, r3 8006048: 2b02 cmp r3, #2 800604a: d133 bne.n 80060b4 { /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800604c: 687b ldr r3, [r7, #4] 800604e: 681b ldr r3, [r3, #0] 8006050: 681a ldr r2, [r3, #0] 8006052: 687b ldr r3, [r7, #4] 8006054: 681b ldr r3, [r3, #0] 8006056: f042 0201 orr.w r2, r2, #1 800605a: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800605c: f7ff f89a bl 8005194 8006060: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 8006062: e012 b.n 800608a { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 8006064: f7ff f896 bl 8005194 8006068: 4602 mov r2, r0 800606a: 68fb ldr r3, [r7, #12] 800606c: 1ad3 subs r3, r2, r3 800606e: 2b0a cmp r3, #10 8006070: d90b bls.n 800608a { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 8006072: 687b ldr r3, [r7, #4] 8006074: 6a5b ldr r3, [r3, #36] ; 0x24 8006076: f443 3200 orr.w r2, r3, #131072 ; 0x20000 800607a: 687b ldr r3, [r7, #4] 800607c: 625a str r2, [r3, #36] ; 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800607e: 687b ldr r3, [r7, #4] 8006080: 2205 movs r2, #5 8006082: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8006086: 2301 movs r3, #1 8006088: e01b b.n 80060c2 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800608a: 687b ldr r3, [r7, #4] 800608c: 681b ldr r3, [r3, #0] 800608e: 685b ldr r3, [r3, #4] 8006090: f003 0301 and.w r3, r3, #1 8006094: 2b00 cmp r3, #0 8006096: d0e5 beq.n 8006064 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 8006098: 687b ldr r3, [r7, #4] 800609a: 681b ldr r3, [r3, #0] 800609c: 681a ldr r2, [r3, #0] 800609e: 687b ldr r3, [r7, #4] 80060a0: 681b ldr r3, [r3, #0] 80060a2: f022 0202 bic.w r2, r2, #2 80060a6: 601a str r2, [r3, #0] /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_READY; 80060a8: 687b ldr r3, [r7, #4] 80060aa: 2201 movs r2, #1 80060ac: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 80060b0: 2300 movs r3, #0 80060b2: e006 b.n 80060c2 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; 80060b4: 687b ldr r3, [r7, #4] 80060b6: 6a5b ldr r3, [r3, #36] ; 0x24 80060b8: f443 1280 orr.w r2, r3, #1048576 ; 0x100000 80060bc: 687b ldr r3, [r7, #4] 80060be: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 80060c0: 2301 movs r3, #1 } } 80060c2: 4618 mov r0, r3 80060c4: 3710 adds r7, #16 80060c6: 46bd mov sp, r7 80060c8: bd80 pop {r7, pc} 080060ca : * the TxMailbox used to store the Tx message. * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) { 80060ca: b480 push {r7} 80060cc: b089 sub sp, #36 ; 0x24 80060ce: af00 add r7, sp, #0 80060d0: 60f8 str r0, [r7, #12] 80060d2: 60b9 str r1, [r7, #8] 80060d4: 607a str r2, [r7, #4] 80060d6: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; 80060d8: 68fb ldr r3, [r7, #12] 80060da: f893 3020 ldrb.w r3, [r3, #32] 80060de: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); 80060e0: 68fb ldr r3, [r7, #12] 80060e2: 681b ldr r3, [r3, #0] 80060e4: 689b ldr r3, [r3, #8] 80060e6: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || 80060e8: 7ffb ldrb r3, [r7, #31] 80060ea: 2b01 cmp r3, #1 80060ec: d003 beq.n 80060f6 80060ee: 7ffb ldrb r3, [r7, #31] 80060f0: 2b02 cmp r3, #2 80060f2: f040 80b8 bne.w 8006266 (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || 80060f6: 69bb ldr r3, [r7, #24] 80060f8: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 80060fc: 2b00 cmp r3, #0 80060fe: d10a bne.n 8006116 ((tsr & CAN_TSR_TME1) != 0U) || 8006100: 69bb ldr r3, [r7, #24] 8006102: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || 8006106: 2b00 cmp r3, #0 8006108: d105 bne.n 8006116 ((tsr & CAN_TSR_TME2) != 0U)) 800610a: 69bb ldr r3, [r7, #24] 800610c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || 8006110: 2b00 cmp r3, #0 8006112: f000 80a0 beq.w 8006256 { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; 8006116: 69bb ldr r3, [r7, #24] 8006118: 0e1b lsrs r3, r3, #24 800611a: f003 0303 and.w r3, r3, #3 800611e: 617b str r3, [r7, #20] /* Check transmit mailbox value */ if (transmitmailbox > 2U) 8006120: 697b ldr r3, [r7, #20] 8006122: 2b02 cmp r3, #2 8006124: d907 bls.n 8006136 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL; 8006126: 68fb ldr r3, [r7, #12] 8006128: 6a5b ldr r3, [r3, #36] ; 0x24 800612a: f443 0200 orr.w r2, r3, #8388608 ; 0x800000 800612e: 68fb ldr r3, [r7, #12] 8006130: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8006132: 2301 movs r3, #1 8006134: e09e b.n 8006274 } /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; 8006136: 2201 movs r2, #1 8006138: 697b ldr r3, [r7, #20] 800613a: 409a lsls r2, r3 800613c: 683b ldr r3, [r7, #0] 800613e: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) 8006140: 68bb ldr r3, [r7, #8] 8006142: 689b ldr r3, [r3, #8] 8006144: 2b00 cmp r3, #0 8006146: d10d bne.n 8006164 { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 8006148: 68bb ldr r3, [r7, #8] 800614a: 681b ldr r3, [r3, #0] 800614c: 055a lsls r2, r3, #21 pHeader->RTR); 800614e: 68bb ldr r3, [r7, #8] 8006150: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 8006152: 68f9 ldr r1, [r7, #12] 8006154: 6809 ldr r1, [r1, #0] 8006156: 431a orrs r2, r3 8006158: 697b ldr r3, [r7, #20] 800615a: 3318 adds r3, #24 800615c: 011b lsls r3, r3, #4 800615e: 440b add r3, r1 8006160: 601a str r2, [r3, #0] 8006162: e00f b.n 8006184 } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8006164: 68bb ldr r3, [r7, #8] 8006166: 685b ldr r3, [r3, #4] 8006168: 00da lsls r2, r3, #3 pHeader->IDE | 800616a: 68bb ldr r3, [r7, #8] 800616c: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800616e: 431a orrs r2, r3 pHeader->RTR); 8006170: 68bb ldr r3, [r7, #8] 8006172: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8006174: 68f9 ldr r1, [r7, #12] 8006176: 6809 ldr r1, [r1, #0] pHeader->IDE | 8006178: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800617a: 697b ldr r3, [r7, #20] 800617c: 3318 adds r3, #24 800617e: 011b lsls r3, r3, #4 8006180: 440b add r3, r1 8006182: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); 8006184: 68fb ldr r3, [r7, #12] 8006186: 6819 ldr r1, [r3, #0] 8006188: 68bb ldr r3, [r7, #8] 800618a: 691a ldr r2, [r3, #16] 800618c: 697b ldr r3, [r7, #20] 800618e: 3318 adds r3, #24 8006190: 011b lsls r3, r3, #4 8006192: 440b add r3, r1 8006194: 3304 adds r3, #4 8006196: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) 8006198: 68bb ldr r3, [r7, #8] 800619a: 7d1b ldrb r3, [r3, #20] 800619c: 2b01 cmp r3, #1 800619e: d111 bne.n 80061c4 { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); 80061a0: 68fb ldr r3, [r7, #12] 80061a2: 681a ldr r2, [r3, #0] 80061a4: 697b ldr r3, [r7, #20] 80061a6: 3318 adds r3, #24 80061a8: 011b lsls r3, r3, #4 80061aa: 4413 add r3, r2 80061ac: 3304 adds r3, #4 80061ae: 681b ldr r3, [r3, #0] 80061b0: 68fa ldr r2, [r7, #12] 80061b2: 6811 ldr r1, [r2, #0] 80061b4: f443 7280 orr.w r2, r3, #256 ; 0x100 80061b8: 697b ldr r3, [r7, #20] 80061ba: 3318 adds r3, #24 80061bc: 011b lsls r3, r3, #4 80061be: 440b add r3, r1 80061c0: 3304 adds r3, #4 80061c2: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, 80061c4: 687b ldr r3, [r7, #4] 80061c6: 3307 adds r3, #7 80061c8: 781b ldrb r3, [r3, #0] 80061ca: 061a lsls r2, r3, #24 80061cc: 687b ldr r3, [r7, #4] 80061ce: 3306 adds r3, #6 80061d0: 781b ldrb r3, [r3, #0] 80061d2: 041b lsls r3, r3, #16 80061d4: 431a orrs r2, r3 80061d6: 687b ldr r3, [r7, #4] 80061d8: 3305 adds r3, #5 80061da: 781b ldrb r3, [r3, #0] 80061dc: 021b lsls r3, r3, #8 80061de: 4313 orrs r3, r2 80061e0: 687a ldr r2, [r7, #4] 80061e2: 3204 adds r2, #4 80061e4: 7812 ldrb r2, [r2, #0] 80061e6: 4610 mov r0, r2 80061e8: 68fa ldr r2, [r7, #12] 80061ea: 6811 ldr r1, [r2, #0] 80061ec: ea43 0200 orr.w r2, r3, r0 80061f0: 697b ldr r3, [r7, #20] 80061f2: 011b lsls r3, r3, #4 80061f4: 440b add r3, r1 80061f6: f503 73c6 add.w r3, r3, #396 ; 0x18c 80061fa: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, 80061fc: 687b ldr r3, [r7, #4] 80061fe: 3303 adds r3, #3 8006200: 781b ldrb r3, [r3, #0] 8006202: 061a lsls r2, r3, #24 8006204: 687b ldr r3, [r7, #4] 8006206: 3302 adds r3, #2 8006208: 781b ldrb r3, [r3, #0] 800620a: 041b lsls r3, r3, #16 800620c: 431a orrs r2, r3 800620e: 687b ldr r3, [r7, #4] 8006210: 3301 adds r3, #1 8006212: 781b ldrb r3, [r3, #0] 8006214: 021b lsls r3, r3, #8 8006216: 4313 orrs r3, r2 8006218: 687a ldr r2, [r7, #4] 800621a: 7812 ldrb r2, [r2, #0] 800621c: 4610 mov r0, r2 800621e: 68fa ldr r2, [r7, #12] 8006220: 6811 ldr r1, [r2, #0] 8006222: ea43 0200 orr.w r2, r3, r0 8006226: 697b ldr r3, [r7, #20] 8006228: 011b lsls r3, r3, #4 800622a: 440b add r3, r1 800622c: f503 73c4 add.w r3, r3, #392 ; 0x188 8006230: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); 8006232: 68fb ldr r3, [r7, #12] 8006234: 681a ldr r2, [r3, #0] 8006236: 697b ldr r3, [r7, #20] 8006238: 3318 adds r3, #24 800623a: 011b lsls r3, r3, #4 800623c: 4413 add r3, r2 800623e: 681b ldr r3, [r3, #0] 8006240: 68fa ldr r2, [r7, #12] 8006242: 6811 ldr r1, [r2, #0] 8006244: f043 0201 orr.w r2, r3, #1 8006248: 697b ldr r3, [r7, #20] 800624a: 3318 adds r3, #24 800624c: 011b lsls r3, r3, #4 800624e: 440b add r3, r1 8006250: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 8006252: 2300 movs r3, #0 8006254: e00e b.n 8006274 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 8006256: 68fb ldr r3, [r7, #12] 8006258: 6a5b ldr r3, [r3, #36] ; 0x24 800625a: f443 1200 orr.w r2, r3, #2097152 ; 0x200000 800625e: 68fb ldr r3, [r7, #12] 8006260: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8006262: 2301 movs r3, #1 8006264: e006 b.n 8006274 } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8006266: 68fb ldr r3, [r7, #12] 8006268: 6a5b ldr r3, [r3, #36] ; 0x24 800626a: f443 2280 orr.w r2, r3, #262144 ; 0x40000 800626e: 68fb ldr r3, [r7, #12] 8006270: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8006272: 2301 movs r3, #1 } } 8006274: 4618 mov r0, r3 8006276: 3724 adds r7, #36 ; 0x24 8006278: 46bd mov sp, r7 800627a: bc80 pop {r7} 800627c: 4770 bx lr 0800627e : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval Number of free Tx Mailboxes. */ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) { 800627e: b480 push {r7} 8006280: b085 sub sp, #20 8006282: af00 add r7, sp, #0 8006284: 6078 str r0, [r7, #4] uint32_t freelevel = 0U; 8006286: 2300 movs r3, #0 8006288: 60fb str r3, [r7, #12] HAL_CAN_StateTypeDef state = hcan->State; 800628a: 687b ldr r3, [r7, #4] 800628c: f893 3020 ldrb.w r3, [r3, #32] 8006290: 72fb strb r3, [r7, #11] if ((state == HAL_CAN_STATE_READY) || 8006292: 7afb ldrb r3, [r7, #11] 8006294: 2b01 cmp r3, #1 8006296: d002 beq.n 800629e 8006298: 7afb ldrb r3, [r7, #11] 800629a: 2b02 cmp r3, #2 800629c: d11d bne.n 80062da (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 status */ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) 800629e: 687b ldr r3, [r7, #4] 80062a0: 681b ldr r3, [r3, #0] 80062a2: 689b ldr r3, [r3, #8] 80062a4: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 80062a8: 2b00 cmp r3, #0 80062aa: d002 beq.n 80062b2 { freelevel++; 80062ac: 68fb ldr r3, [r7, #12] 80062ae: 3301 adds r3, #1 80062b0: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 1 status */ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) 80062b2: 687b ldr r3, [r7, #4] 80062b4: 681b ldr r3, [r3, #0] 80062b6: 689b ldr r3, [r3, #8] 80062b8: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 80062bc: 2b00 cmp r3, #0 80062be: d002 beq.n 80062c6 { freelevel++; 80062c0: 68fb ldr r3, [r7, #12] 80062c2: 3301 adds r3, #1 80062c4: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 2 status */ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) 80062c6: 687b ldr r3, [r7, #4] 80062c8: 681b ldr r3, [r3, #0] 80062ca: 689b ldr r3, [r3, #8] 80062cc: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80062d0: 2b00 cmp r3, #0 80062d2: d002 beq.n 80062da { freelevel++; 80062d4: 68fb ldr r3, [r7, #12] 80062d6: 3301 adds r3, #1 80062d8: 60fb str r3, [r7, #12] } } /* Return Tx Mailboxes free level */ return freelevel; 80062da: 68fb ldr r3, [r7, #12] } 80062dc: 4618 mov r0, r3 80062de: 3714 adds r7, #20 80062e0: 46bd mov sp, r7 80062e2: bc80 pop {r7} 80062e4: 4770 bx lr 080062e6 : * of the Rx frame will be stored. * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { 80062e6: b480 push {r7} 80062e8: b087 sub sp, #28 80062ea: af00 add r7, sp, #0 80062ec: 60f8 str r0, [r7, #12] 80062ee: 60b9 str r1, [r7, #8] 80062f0: 607a str r2, [r7, #4] 80062f2: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 80062f4: 68fb ldr r3, [r7, #12] 80062f6: f893 3020 ldrb.w r3, [r3, #32] 80062fa: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || 80062fc: 7dfb ldrb r3, [r7, #23] 80062fe: 2b01 cmp r3, #1 8006300: d003 beq.n 800630a 8006302: 7dfb ldrb r3, [r7, #23] 8006304: 2b02 cmp r3, #2 8006306: f040 80f3 bne.w 80064f0 (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800630a: 68bb ldr r3, [r7, #8] 800630c: 2b00 cmp r3, #0 800630e: d10e bne.n 800632e { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) 8006310: 68fb ldr r3, [r7, #12] 8006312: 681b ldr r3, [r3, #0] 8006314: 68db ldr r3, [r3, #12] 8006316: f003 0303 and.w r3, r3, #3 800631a: 2b00 cmp r3, #0 800631c: d116 bne.n 800634c { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800631e: 68fb ldr r3, [r7, #12] 8006320: 6a5b ldr r3, [r3, #36] ; 0x24 8006322: f443 1200 orr.w r2, r3, #2097152 ; 0x200000 8006326: 68fb ldr r3, [r7, #12] 8006328: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 800632a: 2301 movs r3, #1 800632c: e0e7 b.n 80064fe } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) 800632e: 68fb ldr r3, [r7, #12] 8006330: 681b ldr r3, [r3, #0] 8006332: 691b ldr r3, [r3, #16] 8006334: f003 0303 and.w r3, r3, #3 8006338: 2b00 cmp r3, #0 800633a: d107 bne.n 800634c { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800633c: 68fb ldr r3, [r7, #12] 800633e: 6a5b ldr r3, [r3, #36] ; 0x24 8006340: f443 1200 orr.w r2, r3, #2097152 ; 0x200000 8006344: 68fb ldr r3, [r7, #12] 8006346: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8006348: 2301 movs r3, #1 800634a: e0d8 b.n 80064fe } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; 800634c: 68fb ldr r3, [r7, #12] 800634e: 681a ldr r2, [r3, #0] 8006350: 68bb ldr r3, [r7, #8] 8006352: 331b adds r3, #27 8006354: 011b lsls r3, r3, #4 8006356: 4413 add r3, r2 8006358: 681b ldr r3, [r3, #0] 800635a: f003 0204 and.w r2, r3, #4 800635e: 687b ldr r3, [r7, #4] 8006360: 609a str r2, [r3, #8] if (pHeader->IDE == CAN_ID_STD) 8006362: 687b ldr r3, [r7, #4] 8006364: 689b ldr r3, [r3, #8] 8006366: 2b00 cmp r3, #0 8006368: d10c bne.n 8006384 { pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; 800636a: 68fb ldr r3, [r7, #12] 800636c: 681a ldr r2, [r3, #0] 800636e: 68bb ldr r3, [r7, #8] 8006370: 331b adds r3, #27 8006372: 011b lsls r3, r3, #4 8006374: 4413 add r3, r2 8006376: 681b ldr r3, [r3, #0] 8006378: 0d5b lsrs r3, r3, #21 800637a: f3c3 020a ubfx r2, r3, #0, #11 800637e: 687b ldr r3, [r7, #4] 8006380: 601a str r2, [r3, #0] 8006382: e00b b.n 800639c } else { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; 8006384: 68fb ldr r3, [r7, #12] 8006386: 681a ldr r2, [r3, #0] 8006388: 68bb ldr r3, [r7, #8] 800638a: 331b adds r3, #27 800638c: 011b lsls r3, r3, #4 800638e: 4413 add r3, r2 8006390: 681b ldr r3, [r3, #0] 8006392: 08db lsrs r3, r3, #3 8006394: f023 4260 bic.w r2, r3, #3758096384 ; 0xe0000000 8006398: 687b ldr r3, [r7, #4] 800639a: 605a str r2, [r3, #4] } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); 800639c: 68fb ldr r3, [r7, #12] 800639e: 681a ldr r2, [r3, #0] 80063a0: 68bb ldr r3, [r7, #8] 80063a2: 331b adds r3, #27 80063a4: 011b lsls r3, r3, #4 80063a6: 4413 add r3, r2 80063a8: 681b ldr r3, [r3, #0] 80063aa: f003 0202 and.w r2, r3, #2 80063ae: 687b ldr r3, [r7, #4] 80063b0: 60da str r2, [r3, #12] pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; 80063b2: 68fb ldr r3, [r7, #12] 80063b4: 681a ldr r2, [r3, #0] 80063b6: 68bb ldr r3, [r7, #8] 80063b8: 331b adds r3, #27 80063ba: 011b lsls r3, r3, #4 80063bc: 4413 add r3, r2 80063be: 3304 adds r3, #4 80063c0: 681b ldr r3, [r3, #0] 80063c2: f003 020f and.w r2, r3, #15 80063c6: 687b ldr r3, [r7, #4] 80063c8: 611a str r2, [r3, #16] pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; 80063ca: 68fb ldr r3, [r7, #12] 80063cc: 681a ldr r2, [r3, #0] 80063ce: 68bb ldr r3, [r7, #8] 80063d0: 331b adds r3, #27 80063d2: 011b lsls r3, r3, #4 80063d4: 4413 add r3, r2 80063d6: 3304 adds r3, #4 80063d8: 681b ldr r3, [r3, #0] 80063da: 0a1b lsrs r3, r3, #8 80063dc: b2da uxtb r2, r3 80063de: 687b ldr r3, [r7, #4] 80063e0: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; 80063e2: 68fb ldr r3, [r7, #12] 80063e4: 681a ldr r2, [r3, #0] 80063e6: 68bb ldr r3, [r7, #8] 80063e8: 331b adds r3, #27 80063ea: 011b lsls r3, r3, #4 80063ec: 4413 add r3, r2 80063ee: 3304 adds r3, #4 80063f0: 681b ldr r3, [r3, #0] 80063f2: 0c1b lsrs r3, r3, #16 80063f4: b29a uxth r2, r3 80063f6: 687b ldr r3, [r7, #4] 80063f8: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); 80063fa: 68fb ldr r3, [r7, #12] 80063fc: 681a ldr r2, [r3, #0] 80063fe: 68bb ldr r3, [r7, #8] 8006400: 011b lsls r3, r3, #4 8006402: 4413 add r3, r2 8006404: f503 73dc add.w r3, r3, #440 ; 0x1b8 8006408: 681b ldr r3, [r3, #0] 800640a: b2da uxtb r2, r3 800640c: 683b ldr r3, [r7, #0] 800640e: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); 8006410: 68fb ldr r3, [r7, #12] 8006412: 681a ldr r2, [r3, #0] 8006414: 68bb ldr r3, [r7, #8] 8006416: 011b lsls r3, r3, #4 8006418: 4413 add r3, r2 800641a: f503 73dc add.w r3, r3, #440 ; 0x1b8 800641e: 681b ldr r3, [r3, #0] 8006420: 0a1a lsrs r2, r3, #8 8006422: 683b ldr r3, [r7, #0] 8006424: 3301 adds r3, #1 8006426: b2d2 uxtb r2, r2 8006428: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); 800642a: 68fb ldr r3, [r7, #12] 800642c: 681a ldr r2, [r3, #0] 800642e: 68bb ldr r3, [r7, #8] 8006430: 011b lsls r3, r3, #4 8006432: 4413 add r3, r2 8006434: f503 73dc add.w r3, r3, #440 ; 0x1b8 8006438: 681b ldr r3, [r3, #0] 800643a: 0c1a lsrs r2, r3, #16 800643c: 683b ldr r3, [r7, #0] 800643e: 3302 adds r3, #2 8006440: b2d2 uxtb r2, r2 8006442: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); 8006444: 68fb ldr r3, [r7, #12] 8006446: 681a ldr r2, [r3, #0] 8006448: 68bb ldr r3, [r7, #8] 800644a: 011b lsls r3, r3, #4 800644c: 4413 add r3, r2 800644e: f503 73dc add.w r3, r3, #440 ; 0x1b8 8006452: 681b ldr r3, [r3, #0] 8006454: 0e1a lsrs r2, r3, #24 8006456: 683b ldr r3, [r7, #0] 8006458: 3303 adds r3, #3 800645a: b2d2 uxtb r2, r2 800645c: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); 800645e: 68fb ldr r3, [r7, #12] 8006460: 681a ldr r2, [r3, #0] 8006462: 68bb ldr r3, [r7, #8] 8006464: 011b lsls r3, r3, #4 8006466: 4413 add r3, r2 8006468: f503 73de add.w r3, r3, #444 ; 0x1bc 800646c: 681a ldr r2, [r3, #0] 800646e: 683b ldr r3, [r7, #0] 8006470: 3304 adds r3, #4 8006472: b2d2 uxtb r2, r2 8006474: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); 8006476: 68fb ldr r3, [r7, #12] 8006478: 681a ldr r2, [r3, #0] 800647a: 68bb ldr r3, [r7, #8] 800647c: 011b lsls r3, r3, #4 800647e: 4413 add r3, r2 8006480: f503 73de add.w r3, r3, #444 ; 0x1bc 8006484: 681b ldr r3, [r3, #0] 8006486: 0a1a lsrs r2, r3, #8 8006488: 683b ldr r3, [r7, #0] 800648a: 3305 adds r3, #5 800648c: b2d2 uxtb r2, r2 800648e: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); 8006490: 68fb ldr r3, [r7, #12] 8006492: 681a ldr r2, [r3, #0] 8006494: 68bb ldr r3, [r7, #8] 8006496: 011b lsls r3, r3, #4 8006498: 4413 add r3, r2 800649a: f503 73de add.w r3, r3, #444 ; 0x1bc 800649e: 681b ldr r3, [r3, #0] 80064a0: 0c1a lsrs r2, r3, #16 80064a2: 683b ldr r3, [r7, #0] 80064a4: 3306 adds r3, #6 80064a6: b2d2 uxtb r2, r2 80064a8: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); 80064aa: 68fb ldr r3, [r7, #12] 80064ac: 681a ldr r2, [r3, #0] 80064ae: 68bb ldr r3, [r7, #8] 80064b0: 011b lsls r3, r3, #4 80064b2: 4413 add r3, r2 80064b4: f503 73de add.w r3, r3, #444 ; 0x1bc 80064b8: 681b ldr r3, [r3, #0] 80064ba: 0e1a lsrs r2, r3, #24 80064bc: 683b ldr r3, [r7, #0] 80064be: 3307 adds r3, #7 80064c0: b2d2 uxtb r2, r2 80064c2: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 80064c4: 68bb ldr r3, [r7, #8] 80064c6: 2b00 cmp r3, #0 80064c8: d108 bne.n 80064dc { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); 80064ca: 68fb ldr r3, [r7, #12] 80064cc: 681b ldr r3, [r3, #0] 80064ce: 68da ldr r2, [r3, #12] 80064d0: 68fb ldr r3, [r7, #12] 80064d2: 681b ldr r3, [r3, #0] 80064d4: f042 0220 orr.w r2, r2, #32 80064d8: 60da str r2, [r3, #12] 80064da: e007 b.n 80064ec } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); 80064dc: 68fb ldr r3, [r7, #12] 80064de: 681b ldr r3, [r3, #0] 80064e0: 691a ldr r2, [r3, #16] 80064e2: 68fb ldr r3, [r7, #12] 80064e4: 681b ldr r3, [r3, #0] 80064e6: f042 0220 orr.w r2, r2, #32 80064ea: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; 80064ec: 2300 movs r3, #0 80064ee: e006 b.n 80064fe } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 80064f0: 68fb ldr r3, [r7, #12] 80064f2: 6a5b ldr r3, [r3, #36] ; 0x24 80064f4: f443 2280 orr.w r2, r3, #262144 ; 0x40000 80064f8: 68fb ldr r3, [r7, #12] 80064fa: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 80064fc: 2301 movs r3, #1 } } 80064fe: 4618 mov r0, r3 8006500: 371c adds r7, #28 8006502: 46bd mov sp, r7 8006504: bc80 pop {r7} 8006506: 4770 bx lr 08006508 : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { 8006508: b480 push {r7} 800650a: b085 sub sp, #20 800650c: af00 add r7, sp, #0 800650e: 6078 str r0, [r7, #4] 8006510: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 8006512: 687b ldr r3, [r7, #4] 8006514: f893 3020 ldrb.w r3, [r3, #32] 8006518: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || 800651a: 7bfb ldrb r3, [r7, #15] 800651c: 2b01 cmp r3, #1 800651e: d002 beq.n 8006526 8006520: 7bfb ldrb r3, [r7, #15] 8006522: 2b02 cmp r3, #2 8006524: d109 bne.n 800653a (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); 8006526: 687b ldr r3, [r7, #4] 8006528: 681b ldr r3, [r3, #0] 800652a: 6959 ldr r1, [r3, #20] 800652c: 687b ldr r3, [r7, #4] 800652e: 681b ldr r3, [r3, #0] 8006530: 683a ldr r2, [r7, #0] 8006532: 430a orrs r2, r1 8006534: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; 8006536: 2300 movs r3, #0 8006538: e006 b.n 8006548 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800653a: 687b ldr r3, [r7, #4] 800653c: 6a5b ldr r3, [r3, #36] ; 0x24 800653e: f443 2280 orr.w r2, r3, #262144 ; 0x40000 8006542: 687b ldr r3, [r7, #4] 8006544: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8006546: 2301 movs r3, #1 } } 8006548: 4618 mov r0, r3 800654a: 3714 adds r7, #20 800654c: 46bd mov sp, r7 800654e: bc80 pop {r7} 8006550: 4770 bx lr 08006552 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { 8006552: b580 push {r7, lr} 8006554: b08a sub sp, #40 ; 0x28 8006556: af00 add r7, sp, #0 8006558: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; 800655a: 2300 movs r3, #0 800655c: 627b str r3, [r7, #36] ; 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); 800655e: 687b ldr r3, [r7, #4] 8006560: 681b ldr r3, [r3, #0] 8006562: 695b ldr r3, [r3, #20] 8006564: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); 8006566: 687b ldr r3, [r7, #4] 8006568: 681b ldr r3, [r3, #0] 800656a: 685b ldr r3, [r3, #4] 800656c: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); 800656e: 687b ldr r3, [r7, #4] 8006570: 681b ldr r3, [r3, #0] 8006572: 689b ldr r3, [r3, #8] 8006574: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); 8006576: 687b ldr r3, [r7, #4] 8006578: 681b ldr r3, [r3, #0] 800657a: 68db ldr r3, [r3, #12] 800657c: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); 800657e: 687b ldr r3, [r7, #4] 8006580: 681b ldr r3, [r3, #0] 8006582: 691b ldr r3, [r3, #16] 8006584: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); 8006586: 687b ldr r3, [r7, #4] 8006588: 681b ldr r3, [r3, #0] 800658a: 699b ldr r3, [r3, #24] 800658c: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) 800658e: 6a3b ldr r3, [r7, #32] 8006590: f003 0301 and.w r3, r3, #1 8006594: 2b00 cmp r3, #0 8006596: d07c beq.n 8006692 { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) 8006598: 69bb ldr r3, [r7, #24] 800659a: f003 0301 and.w r3, r3, #1 800659e: 2b00 cmp r3, #0 80065a0: d023 beq.n 80065ea { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); 80065a2: 687b ldr r3, [r7, #4] 80065a4: 681b ldr r3, [r3, #0] 80065a6: 2201 movs r2, #1 80065a8: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) 80065aa: 69bb ldr r3, [r7, #24] 80065ac: f003 0302 and.w r3, r3, #2 80065b0: 2b00 cmp r3, #0 80065b2: d003 beq.n 80065bc #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); 80065b4: 6878 ldr r0, [r7, #4] 80065b6: f7fd fc2b bl 8003e10 80065ba: e016 b.n 80065ea #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) 80065bc: 69bb ldr r3, [r7, #24] 80065be: f003 0304 and.w r3, r3, #4 80065c2: 2b00 cmp r3, #0 80065c4: d004 beq.n 80065d0 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; 80065c6: 6a7b ldr r3, [r7, #36] ; 0x24 80065c8: f443 6300 orr.w r3, r3, #2048 ; 0x800 80065cc: 627b str r3, [r7, #36] ; 0x24 80065ce: e00c b.n 80065ea } else if ((tsrflags & CAN_TSR_TERR0) != 0U) 80065d0: 69bb ldr r3, [r7, #24] 80065d2: f003 0308 and.w r3, r3, #8 80065d6: 2b00 cmp r3, #0 80065d8: d004 beq.n 80065e4 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; 80065da: 6a7b ldr r3, [r7, #36] ; 0x24 80065dc: f443 5380 orr.w r3, r3, #4096 ; 0x1000 80065e0: 627b str r3, [r7, #36] ; 0x24 80065e2: e002 b.n 80065ea #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); 80065e4: 6878 ldr r0, [r7, #4] 80065e6: f000 f96b bl 80068c0 } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) 80065ea: 69bb ldr r3, [r7, #24] 80065ec: f403 7380 and.w r3, r3, #256 ; 0x100 80065f0: 2b00 cmp r3, #0 80065f2: d024 beq.n 800663e { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); 80065f4: 687b ldr r3, [r7, #4] 80065f6: 681b ldr r3, [r3, #0] 80065f8: f44f 7280 mov.w r2, #256 ; 0x100 80065fc: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) 80065fe: 69bb ldr r3, [r7, #24] 8006600: f403 7300 and.w r3, r3, #512 ; 0x200 8006604: 2b00 cmp r3, #0 8006606: d003 beq.n 8006610 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); 8006608: 6878 ldr r0, [r7, #4] 800660a: f7fd fc1b bl 8003e44 800660e: e016 b.n 800663e #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) 8006610: 69bb ldr r3, [r7, #24] 8006612: f403 6380 and.w r3, r3, #1024 ; 0x400 8006616: 2b00 cmp r3, #0 8006618: d004 beq.n 8006624 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; 800661a: 6a7b ldr r3, [r7, #36] ; 0x24 800661c: f443 5300 orr.w r3, r3, #8192 ; 0x2000 8006620: 627b str r3, [r7, #36] ; 0x24 8006622: e00c b.n 800663e } else if ((tsrflags & CAN_TSR_TERR1) != 0U) 8006624: 69bb ldr r3, [r7, #24] 8006626: f403 6300 and.w r3, r3, #2048 ; 0x800 800662a: 2b00 cmp r3, #0 800662c: d004 beq.n 8006638 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; 800662e: 6a7b ldr r3, [r7, #36] ; 0x24 8006630: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8006634: 627b str r3, [r7, #36] ; 0x24 8006636: e002 b.n 800663e #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); 8006638: 6878 ldr r0, [r7, #4] 800663a: f000 f94a bl 80068d2 } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) 800663e: 69bb ldr r3, [r7, #24] 8006640: f403 3380 and.w r3, r3, #65536 ; 0x10000 8006644: 2b00 cmp r3, #0 8006646: d024 beq.n 8006692 { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); 8006648: 687b ldr r3, [r7, #4] 800664a: 681b ldr r3, [r3, #0] 800664c: f44f 3280 mov.w r2, #65536 ; 0x10000 8006650: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) 8006652: 69bb ldr r3, [r7, #24] 8006654: f403 3300 and.w r3, r3, #131072 ; 0x20000 8006658: 2b00 cmp r3, #0 800665a: d003 beq.n 8006664 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); 800665c: 6878 ldr r0, [r7, #4] 800665e: f7fd fc0b bl 8003e78 8006662: e016 b.n 8006692 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) 8006664: 69bb ldr r3, [r7, #24] 8006666: f403 2380 and.w r3, r3, #262144 ; 0x40000 800666a: 2b00 cmp r3, #0 800666c: d004 beq.n 8006678 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; 800666e: 6a7b ldr r3, [r7, #36] ; 0x24 8006670: f443 4300 orr.w r3, r3, #32768 ; 0x8000 8006674: 627b str r3, [r7, #36] ; 0x24 8006676: e00c b.n 8006692 } else if ((tsrflags & CAN_TSR_TERR2) != 0U) 8006678: 69bb ldr r3, [r7, #24] 800667a: f403 2300 and.w r3, r3, #524288 ; 0x80000 800667e: 2b00 cmp r3, #0 8006680: d004 beq.n 800668c { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; 8006682: 6a7b ldr r3, [r7, #36] ; 0x24 8006684: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8006688: 627b str r3, [r7, #36] ; 0x24 800668a: e002 b.n 8006692 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); 800668c: 6878 ldr r0, [r7, #4] 800668e: f000 f929 bl 80068e4 } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) 8006692: 6a3b ldr r3, [r7, #32] 8006694: f003 0308 and.w r3, r3, #8 8006698: 2b00 cmp r3, #0 800669a: d00c beq.n 80066b6 { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) 800669c: 697b ldr r3, [r7, #20] 800669e: f003 0310 and.w r3, r3, #16 80066a2: 2b00 cmp r3, #0 80066a4: d007 beq.n 80066b6 { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; 80066a6: 6a7b ldr r3, [r7, #36] ; 0x24 80066a8: f443 7300 orr.w r3, r3, #512 ; 0x200 80066ac: 627b str r3, [r7, #36] ; 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); 80066ae: 687b ldr r3, [r7, #4] 80066b0: 681b ldr r3, [r3, #0] 80066b2: 2210 movs r2, #16 80066b4: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) 80066b6: 6a3b ldr r3, [r7, #32] 80066b8: f003 0304 and.w r3, r3, #4 80066bc: 2b00 cmp r3, #0 80066be: d00b beq.n 80066d8 { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) 80066c0: 697b ldr r3, [r7, #20] 80066c2: f003 0308 and.w r3, r3, #8 80066c6: 2b00 cmp r3, #0 80066c8: d006 beq.n 80066d8 { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); 80066ca: 687b ldr r3, [r7, #4] 80066cc: 681b ldr r3, [r3, #0] 80066ce: 2208 movs r2, #8 80066d0: 60da str r2, [r3, #12] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); 80066d2: 6878 ldr r0, [r7, #4] 80066d4: f000 f90f bl 80068f6 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) 80066d8: 6a3b ldr r3, [r7, #32] 80066da: f003 0302 and.w r3, r3, #2 80066de: 2b00 cmp r3, #0 80066e0: d009 beq.n 80066f6 { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) 80066e2: 687b ldr r3, [r7, #4] 80066e4: 681b ldr r3, [r3, #0] 80066e6: 68db ldr r3, [r3, #12] 80066e8: f003 0303 and.w r3, r3, #3 80066ec: 2b00 cmp r3, #0 80066ee: d002 beq.n 80066f6 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); 80066f0: 6878 ldr r0, [r7, #4] 80066f2: f7fd f837 bl 8003764 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) 80066f6: 6a3b ldr r3, [r7, #32] 80066f8: f003 0340 and.w r3, r3, #64 ; 0x40 80066fc: 2b00 cmp r3, #0 80066fe: d00c beq.n 800671a { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) 8006700: 693b ldr r3, [r7, #16] 8006702: f003 0310 and.w r3, r3, #16 8006706: 2b00 cmp r3, #0 8006708: d007 beq.n 800671a { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; 800670a: 6a7b ldr r3, [r7, #36] ; 0x24 800670c: f443 6380 orr.w r3, r3, #1024 ; 0x400 8006710: 627b str r3, [r7, #36] ; 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); 8006712: 687b ldr r3, [r7, #4] 8006714: 681b ldr r3, [r3, #0] 8006716: 2210 movs r2, #16 8006718: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) 800671a: 6a3b ldr r3, [r7, #32] 800671c: f003 0320 and.w r3, r3, #32 8006720: 2b00 cmp r3, #0 8006722: d00b beq.n 800673c { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) 8006724: 693b ldr r3, [r7, #16] 8006726: f003 0308 and.w r3, r3, #8 800672a: 2b00 cmp r3, #0 800672c: d006 beq.n 800673c { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); 800672e: 687b ldr r3, [r7, #4] 8006730: 681b ldr r3, [r3, #0] 8006732: 2208 movs r2, #8 8006734: 611a str r2, [r3, #16] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); 8006736: 6878 ldr r0, [r7, #4] 8006738: f000 f8e6 bl 8006908 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) 800673c: 6a3b ldr r3, [r7, #32] 800673e: f003 0310 and.w r3, r3, #16 8006742: 2b00 cmp r3, #0 8006744: d009 beq.n 800675a { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) 8006746: 687b ldr r3, [r7, #4] 8006748: 681b ldr r3, [r3, #0] 800674a: 691b ldr r3, [r3, #16] 800674c: f003 0303 and.w r3, r3, #3 8006750: 2b00 cmp r3, #0 8006752: d002 beq.n 800675a #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); 8006754: 6878 ldr r0, [r7, #4] 8006756: f7fd fb05 bl 8003d64 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) 800675a: 6a3b ldr r3, [r7, #32] 800675c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8006760: 2b00 cmp r3, #0 8006762: d00b beq.n 800677c { if ((msrflags & CAN_MSR_SLAKI) != 0U) 8006764: 69fb ldr r3, [r7, #28] 8006766: f003 0310 and.w r3, r3, #16 800676a: 2b00 cmp r3, #0 800676c: d006 beq.n 800677c { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); 800676e: 687b ldr r3, [r7, #4] 8006770: 681b ldr r3, [r3, #0] 8006772: 2210 movs r2, #16 8006774: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->SleepCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); 8006776: 6878 ldr r0, [r7, #4] 8006778: f000 f8cf bl 800691a #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ if ((interrupts & CAN_IT_WAKEUP) != 0U) 800677c: 6a3b ldr r3, [r7, #32] 800677e: f403 3380 and.w r3, r3, #65536 ; 0x10000 8006782: 2b00 cmp r3, #0 8006784: d00b beq.n 800679e { if ((msrflags & CAN_MSR_WKUI) != 0U) 8006786: 69fb ldr r3, [r7, #28] 8006788: f003 0308 and.w r3, r3, #8 800678c: 2b00 cmp r3, #0 800678e: d006 beq.n 800679e { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); 8006790: 687b ldr r3, [r7, #4] 8006792: 681b ldr r3, [r3, #0] 8006794: 2208 movs r2, #8 8006796: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->WakeUpFromRxMsgCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); 8006798: 6878 ldr r0, [r7, #4] 800679a: f000 f8c7 bl 800692c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ if ((interrupts & CAN_IT_ERROR) != 0U) 800679e: 6a3b ldr r3, [r7, #32] 80067a0: f403 4300 and.w r3, r3, #32768 ; 0x8000 80067a4: 2b00 cmp r3, #0 80067a6: d07b beq.n 80068a0 { if ((msrflags & CAN_MSR_ERRI) != 0U) 80067a8: 69fb ldr r3, [r7, #28] 80067aa: f003 0304 and.w r3, r3, #4 80067ae: 2b00 cmp r3, #0 80067b0: d072 beq.n 8006898 { /* Check Error Warning Flag */ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 80067b2: 6a3b ldr r3, [r7, #32] 80067b4: f403 7380 and.w r3, r3, #256 ; 0x100 80067b8: 2b00 cmp r3, #0 80067ba: d008 beq.n 80067ce ((esrflags & CAN_ESR_EWGF) != 0U)) 80067bc: 68fb ldr r3, [r7, #12] 80067be: f003 0301 and.w r3, r3, #1 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 80067c2: 2b00 cmp r3, #0 80067c4: d003 beq.n 80067ce { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; 80067c6: 6a7b ldr r3, [r7, #36] ; 0x24 80067c8: f043 0301 orr.w r3, r3, #1 80067cc: 627b str r3, [r7, #36] ; 0x24 /* No need for clear of Error Warning Flag as read-only */ } /* Check Error Passive Flag */ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 80067ce: 6a3b ldr r3, [r7, #32] 80067d0: f403 7300 and.w r3, r3, #512 ; 0x200 80067d4: 2b00 cmp r3, #0 80067d6: d008 beq.n 80067ea ((esrflags & CAN_ESR_EPVF) != 0U)) 80067d8: 68fb ldr r3, [r7, #12] 80067da: f003 0302 and.w r3, r3, #2 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 80067de: 2b00 cmp r3, #0 80067e0: d003 beq.n 80067ea { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; 80067e2: 6a7b ldr r3, [r7, #36] ; 0x24 80067e4: f043 0302 orr.w r3, r3, #2 80067e8: 627b str r3, [r7, #36] ; 0x24 /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-off Flag */ if (((interrupts & CAN_IT_BUSOFF) != 0U) && 80067ea: 6a3b ldr r3, [r7, #32] 80067ec: f403 6380 and.w r3, r3, #1024 ; 0x400 80067f0: 2b00 cmp r3, #0 80067f2: d008 beq.n 8006806 ((esrflags & CAN_ESR_BOFF) != 0U)) 80067f4: 68fb ldr r3, [r7, #12] 80067f6: f003 0304 and.w r3, r3, #4 if (((interrupts & CAN_IT_BUSOFF) != 0U) && 80067fa: 2b00 cmp r3, #0 80067fc: d003 beq.n 8006806 { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; 80067fe: 6a7b ldr r3, [r7, #36] ; 0x24 8006800: f043 0304 orr.w r3, r3, #4 8006804: 627b str r3, [r7, #36] ; 0x24 /* No need for clear of Error Bus-Off as read-only */ } /* Check Last Error Code Flag */ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 8006806: 6a3b ldr r3, [r7, #32] 8006808: f403 6300 and.w r3, r3, #2048 ; 0x800 800680c: 2b00 cmp r3, #0 800680e: d043 beq.n 8006898 ((esrflags & CAN_ESR_LEC) != 0U)) 8006810: 68fb ldr r3, [r7, #12] 8006812: f003 0370 and.w r3, r3, #112 ; 0x70 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 8006816: 2b00 cmp r3, #0 8006818: d03e beq.n 8006898 { switch (esrflags & CAN_ESR_LEC) 800681a: 68fb ldr r3, [r7, #12] 800681c: f003 0370 and.w r3, r3, #112 ; 0x70 8006820: 2b60 cmp r3, #96 ; 0x60 8006822: d02b beq.n 800687c 8006824: 2b60 cmp r3, #96 ; 0x60 8006826: d82e bhi.n 8006886 8006828: 2b50 cmp r3, #80 ; 0x50 800682a: d022 beq.n 8006872 800682c: 2b50 cmp r3, #80 ; 0x50 800682e: d82a bhi.n 8006886 8006830: 2b40 cmp r3, #64 ; 0x40 8006832: d019 beq.n 8006868 8006834: 2b40 cmp r3, #64 ; 0x40 8006836: d826 bhi.n 8006886 8006838: 2b30 cmp r3, #48 ; 0x30 800683a: d010 beq.n 800685e 800683c: 2b30 cmp r3, #48 ; 0x30 800683e: d822 bhi.n 8006886 8006840: 2b10 cmp r3, #16 8006842: d002 beq.n 800684a 8006844: 2b20 cmp r3, #32 8006846: d005 beq.n 8006854 case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): /* Set CAN error code to CRC error */ errorcode |= HAL_CAN_ERROR_CRC; break; default: break; 8006848: e01d b.n 8006886 errorcode |= HAL_CAN_ERROR_STF; 800684a: 6a7b ldr r3, [r7, #36] ; 0x24 800684c: f043 0308 orr.w r3, r3, #8 8006850: 627b str r3, [r7, #36] ; 0x24 break; 8006852: e019 b.n 8006888 errorcode |= HAL_CAN_ERROR_FOR; 8006854: 6a7b ldr r3, [r7, #36] ; 0x24 8006856: f043 0310 orr.w r3, r3, #16 800685a: 627b str r3, [r7, #36] ; 0x24 break; 800685c: e014 b.n 8006888 errorcode |= HAL_CAN_ERROR_ACK; 800685e: 6a7b ldr r3, [r7, #36] ; 0x24 8006860: f043 0320 orr.w r3, r3, #32 8006864: 627b str r3, [r7, #36] ; 0x24 break; 8006866: e00f b.n 8006888 errorcode |= HAL_CAN_ERROR_BR; 8006868: 6a7b ldr r3, [r7, #36] ; 0x24 800686a: f043 0340 orr.w r3, r3, #64 ; 0x40 800686e: 627b str r3, [r7, #36] ; 0x24 break; 8006870: e00a b.n 8006888 errorcode |= HAL_CAN_ERROR_BD; 8006872: 6a7b ldr r3, [r7, #36] ; 0x24 8006874: f043 0380 orr.w r3, r3, #128 ; 0x80 8006878: 627b str r3, [r7, #36] ; 0x24 break; 800687a: e005 b.n 8006888 errorcode |= HAL_CAN_ERROR_CRC; 800687c: 6a7b ldr r3, [r7, #36] ; 0x24 800687e: f443 7380 orr.w r3, r3, #256 ; 0x100 8006882: 627b str r3, [r7, #36] ; 0x24 break; 8006884: e000 b.n 8006888 break; 8006886: bf00 nop } /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); 8006888: 687b ldr r3, [r7, #4] 800688a: 681b ldr r3, [r3, #0] 800688c: 699a ldr r2, [r3, #24] 800688e: 687b ldr r3, [r7, #4] 8006890: 681b ldr r3, [r3, #0] 8006892: f022 0270 bic.w r2, r2, #112 ; 0x70 8006896: 619a str r2, [r3, #24] } } /* Clear ERRI Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); 8006898: 687b ldr r3, [r7, #4] 800689a: 681b ldr r3, [r3, #0] 800689c: 2204 movs r2, #4 800689e: 605a str r2, [r3, #4] } /* Call the Error call Back in case of Errors */ if (errorcode != HAL_CAN_ERROR_NONE) 80068a0: 6a7b ldr r3, [r7, #36] ; 0x24 80068a2: 2b00 cmp r3, #0 80068a4: d008 beq.n 80068b8 { /* Update error code in handle */ hcan->ErrorCode |= errorcode; 80068a6: 687b ldr r3, [r7, #4] 80068a8: 6a5a ldr r2, [r3, #36] ; 0x24 80068aa: 6a7b ldr r3, [r7, #36] ; 0x24 80068ac: 431a orrs r2, r3 80068ae: 687b ldr r3, [r7, #4] 80068b0: 625a str r2, [r3, #36] ; 0x24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->ErrorCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); 80068b2: 6878 ldr r0, [r7, #4] 80068b4: f000 f843 bl 800693e #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } 80068b8: bf00 nop 80068ba: 3728 adds r7, #40 ; 0x28 80068bc: 46bd mov sp, r7 80068be: bd80 pop {r7, pc} 080068c0 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { 80068c0: b480 push {r7} 80068c2: b083 sub sp, #12 80068c4: af00 add r7, sp, #0 80068c6: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } 80068c8: bf00 nop 80068ca: 370c adds r7, #12 80068cc: 46bd mov sp, r7 80068ce: bc80 pop {r7} 80068d0: 4770 bx lr 080068d2 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { 80068d2: b480 push {r7} 80068d4: b083 sub sp, #12 80068d6: af00 add r7, sp, #0 80068d8: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } 80068da: bf00 nop 80068dc: 370c adds r7, #12 80068de: 46bd mov sp, r7 80068e0: bc80 pop {r7} 80068e2: 4770 bx lr 080068e4 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { 80068e4: b480 push {r7} 80068e6: b083 sub sp, #12 80068e8: af00 add r7, sp, #0 80068ea: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } 80068ec: bf00 nop 80068ee: 370c adds r7, #12 80068f0: 46bd mov sp, r7 80068f2: bc80 pop {r7} 80068f4: 4770 bx lr 080068f6 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { 80068f6: b480 push {r7} 80068f8: b083 sub sp, #12 80068fa: af00 add r7, sp, #0 80068fc: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } 80068fe: bf00 nop 8006900: 370c adds r7, #12 8006902: 46bd mov sp, r7 8006904: bc80 pop {r7} 8006906: 4770 bx lr 08006908 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { 8006908: b480 push {r7} 800690a: b083 sub sp, #12 800690c: af00 add r7, sp, #0 800690e: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } 8006910: bf00 nop 8006912: 370c adds r7, #12 8006914: 46bd mov sp, r7 8006916: bc80 pop {r7} 8006918: 4770 bx lr 0800691a : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { 800691a: b480 push {r7} 800691c: b083 sub sp, #12 800691e: af00 add r7, sp, #0 8006920: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } 8006922: bf00 nop 8006924: 370c adds r7, #12 8006926: 46bd mov sp, r7 8006928: bc80 pop {r7} 800692a: 4770 bx lr 0800692c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { 800692c: b480 push {r7} 800692e: b083 sub sp, #12 8006930: af00 add r7, sp, #0 8006932: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } 8006934: bf00 nop 8006936: 370c adds r7, #12 8006938: 46bd mov sp, r7 800693a: bc80 pop {r7} 800693c: 4770 bx lr 0800693e : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { 800693e: b480 push {r7} 8006940: b083 sub sp, #12 8006942: af00 add r7, sp, #0 8006944: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } 8006946: bf00 nop 8006948: 370c adds r7, #12 800694a: 46bd mov sp, r7 800694c: bc80 pop {r7} 800694e: 4770 bx lr 08006950 <__NVIC_SetPriorityGrouping>: { 8006950: b480 push {r7} 8006952: b085 sub sp, #20 8006954: af00 add r7, sp, #0 8006956: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8006958: 687b ldr r3, [r7, #4] 800695a: f003 0307 and.w r3, r3, #7 800695e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8006960: 4b0c ldr r3, [pc, #48] ; (8006994 <__NVIC_SetPriorityGrouping+0x44>) 8006962: 68db ldr r3, [r3, #12] 8006964: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8006966: 68ba ldr r2, [r7, #8] 8006968: f64f 03ff movw r3, #63743 ; 0xf8ff 800696c: 4013 ands r3, r2 800696e: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8006970: 68fb ldr r3, [r7, #12] 8006972: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8006974: 68bb ldr r3, [r7, #8] 8006976: 4313 orrs r3, r2 reg_value = (reg_value | 8006978: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 800697c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8006980: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8006982: 4a04 ldr r2, [pc, #16] ; (8006994 <__NVIC_SetPriorityGrouping+0x44>) 8006984: 68bb ldr r3, [r7, #8] 8006986: 60d3 str r3, [r2, #12] } 8006988: bf00 nop 800698a: 3714 adds r7, #20 800698c: 46bd mov sp, r7 800698e: bc80 pop {r7} 8006990: 4770 bx lr 8006992: bf00 nop 8006994: e000ed00 .word 0xe000ed00 08006998 <__NVIC_GetPriorityGrouping>: { 8006998: b480 push {r7} 800699a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800699c: 4b04 ldr r3, [pc, #16] ; (80069b0 <__NVIC_GetPriorityGrouping+0x18>) 800699e: 68db ldr r3, [r3, #12] 80069a0: 0a1b lsrs r3, r3, #8 80069a2: f003 0307 and.w r3, r3, #7 } 80069a6: 4618 mov r0, r3 80069a8: 46bd mov sp, r7 80069aa: bc80 pop {r7} 80069ac: 4770 bx lr 80069ae: bf00 nop 80069b0: e000ed00 .word 0xe000ed00 080069b4 <__NVIC_EnableIRQ>: { 80069b4: b480 push {r7} 80069b6: b083 sub sp, #12 80069b8: af00 add r7, sp, #0 80069ba: 4603 mov r3, r0 80069bc: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80069be: f997 3007 ldrsb.w r3, [r7, #7] 80069c2: 2b00 cmp r3, #0 80069c4: db0b blt.n 80069de <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80069c6: 79fb ldrb r3, [r7, #7] 80069c8: f003 021f and.w r2, r3, #31 80069cc: 4906 ldr r1, [pc, #24] ; (80069e8 <__NVIC_EnableIRQ+0x34>) 80069ce: f997 3007 ldrsb.w r3, [r7, #7] 80069d2: 095b lsrs r3, r3, #5 80069d4: 2001 movs r0, #1 80069d6: fa00 f202 lsl.w r2, r0, r2 80069da: f841 2023 str.w r2, [r1, r3, lsl #2] } 80069de: bf00 nop 80069e0: 370c adds r7, #12 80069e2: 46bd mov sp, r7 80069e4: bc80 pop {r7} 80069e6: 4770 bx lr 80069e8: e000e100 .word 0xe000e100 080069ec <__NVIC_SetPriority>: { 80069ec: b480 push {r7} 80069ee: b083 sub sp, #12 80069f0: af00 add r7, sp, #0 80069f2: 4603 mov r3, r0 80069f4: 6039 str r1, [r7, #0] 80069f6: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80069f8: f997 3007 ldrsb.w r3, [r7, #7] 80069fc: 2b00 cmp r3, #0 80069fe: db0a blt.n 8006a16 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8006a00: 683b ldr r3, [r7, #0] 8006a02: b2da uxtb r2, r3 8006a04: 490c ldr r1, [pc, #48] ; (8006a38 <__NVIC_SetPriority+0x4c>) 8006a06: f997 3007 ldrsb.w r3, [r7, #7] 8006a0a: 0112 lsls r2, r2, #4 8006a0c: b2d2 uxtb r2, r2 8006a0e: 440b add r3, r1 8006a10: f883 2300 strb.w r2, [r3, #768] ; 0x300 } 8006a14: e00a b.n 8006a2c <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8006a16: 683b ldr r3, [r7, #0] 8006a18: b2da uxtb r2, r3 8006a1a: 4908 ldr r1, [pc, #32] ; (8006a3c <__NVIC_SetPriority+0x50>) 8006a1c: 79fb ldrb r3, [r7, #7] 8006a1e: f003 030f and.w r3, r3, #15 8006a22: 3b04 subs r3, #4 8006a24: 0112 lsls r2, r2, #4 8006a26: b2d2 uxtb r2, r2 8006a28: 440b add r3, r1 8006a2a: 761a strb r2, [r3, #24] } 8006a2c: bf00 nop 8006a2e: 370c adds r7, #12 8006a30: 46bd mov sp, r7 8006a32: bc80 pop {r7} 8006a34: 4770 bx lr 8006a36: bf00 nop 8006a38: e000e100 .word 0xe000e100 8006a3c: e000ed00 .word 0xe000ed00 08006a40 : { 8006a40: b480 push {r7} 8006a42: b089 sub sp, #36 ; 0x24 8006a44: af00 add r7, sp, #0 8006a46: 60f8 str r0, [r7, #12] 8006a48: 60b9 str r1, [r7, #8] 8006a4a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8006a4c: 68fb ldr r3, [r7, #12] 8006a4e: f003 0307 and.w r3, r3, #7 8006a52: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8006a54: 69fb ldr r3, [r7, #28] 8006a56: f1c3 0307 rsb r3, r3, #7 8006a5a: 2b04 cmp r3, #4 8006a5c: bf28 it cs 8006a5e: 2304 movcs r3, #4 8006a60: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8006a62: 69fb ldr r3, [r7, #28] 8006a64: 3304 adds r3, #4 8006a66: 2b06 cmp r3, #6 8006a68: d902 bls.n 8006a70 8006a6a: 69fb ldr r3, [r7, #28] 8006a6c: 3b03 subs r3, #3 8006a6e: e000 b.n 8006a72 8006a70: 2300 movs r3, #0 8006a72: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8006a74: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 8006a78: 69bb ldr r3, [r7, #24] 8006a7a: fa02 f303 lsl.w r3, r2, r3 8006a7e: 43da mvns r2, r3 8006a80: 68bb ldr r3, [r7, #8] 8006a82: 401a ands r2, r3 8006a84: 697b ldr r3, [r7, #20] 8006a86: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8006a88: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8006a8c: 697b ldr r3, [r7, #20] 8006a8e: fa01 f303 lsl.w r3, r1, r3 8006a92: 43d9 mvns r1, r3 8006a94: 687b ldr r3, [r7, #4] 8006a96: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8006a98: 4313 orrs r3, r2 } 8006a9a: 4618 mov r0, r3 8006a9c: 3724 adds r7, #36 ; 0x24 8006a9e: 46bd mov sp, r7 8006aa0: bc80 pop {r7} 8006aa2: 4770 bx lr 08006aa4 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8006aa4: b580 push {r7, lr} 8006aa6: b082 sub sp, #8 8006aa8: af00 add r7, sp, #0 8006aaa: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8006aac: 687b ldr r3, [r7, #4] 8006aae: 3b01 subs r3, #1 8006ab0: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8006ab4: d301 bcc.n 8006aba { return (1UL); /* Reload value impossible */ 8006ab6: 2301 movs r3, #1 8006ab8: e00f b.n 8006ada } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8006aba: 4a0a ldr r2, [pc, #40] ; (8006ae4 ) 8006abc: 687b ldr r3, [r7, #4] 8006abe: 3b01 subs r3, #1 8006ac0: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8006ac2: 210f movs r1, #15 8006ac4: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8006ac8: f7ff ff90 bl 80069ec <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8006acc: 4b05 ldr r3, [pc, #20] ; (8006ae4 ) 8006ace: 2200 movs r2, #0 8006ad0: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8006ad2: 4b04 ldr r3, [pc, #16] ; (8006ae4 ) 8006ad4: 2207 movs r2, #7 8006ad6: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8006ad8: 2300 movs r3, #0 } 8006ada: 4618 mov r0, r3 8006adc: 3708 adds r7, #8 8006ade: 46bd mov sp, r7 8006ae0: bd80 pop {r7, pc} 8006ae2: bf00 nop 8006ae4: e000e010 .word 0xe000e010 08006ae8 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8006ae8: b580 push {r7, lr} 8006aea: b082 sub sp, #8 8006aec: af00 add r7, sp, #0 8006aee: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8006af0: 6878 ldr r0, [r7, #4] 8006af2: f7ff ff2d bl 8006950 <__NVIC_SetPriorityGrouping> } 8006af6: bf00 nop 8006af8: 3708 adds r7, #8 8006afa: 46bd mov sp, r7 8006afc: bd80 pop {r7, pc} 08006afe : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8006afe: b580 push {r7, lr} 8006b00: b086 sub sp, #24 8006b02: af00 add r7, sp, #0 8006b04: 4603 mov r3, r0 8006b06: 60b9 str r1, [r7, #8] 8006b08: 607a str r2, [r7, #4] 8006b0a: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8006b0c: 2300 movs r3, #0 8006b0e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8006b10: f7ff ff42 bl 8006998 <__NVIC_GetPriorityGrouping> 8006b14: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8006b16: 687a ldr r2, [r7, #4] 8006b18: 68b9 ldr r1, [r7, #8] 8006b1a: 6978 ldr r0, [r7, #20] 8006b1c: f7ff ff90 bl 8006a40 8006b20: 4602 mov r2, r0 8006b22: f997 300f ldrsb.w r3, [r7, #15] 8006b26: 4611 mov r1, r2 8006b28: 4618 mov r0, r3 8006b2a: f7ff ff5f bl 80069ec <__NVIC_SetPriority> } 8006b2e: bf00 nop 8006b30: 3718 adds r7, #24 8006b32: 46bd mov sp, r7 8006b34: bd80 pop {r7, pc} 08006b36 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8006b36: b580 push {r7, lr} 8006b38: b082 sub sp, #8 8006b3a: af00 add r7, sp, #0 8006b3c: 4603 mov r3, r0 8006b3e: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8006b40: f997 3007 ldrsb.w r3, [r7, #7] 8006b44: 4618 mov r0, r3 8006b46: f7ff ff35 bl 80069b4 <__NVIC_EnableIRQ> } 8006b4a: bf00 nop 8006b4c: 3708 adds r7, #8 8006b4e: 46bd mov sp, r7 8006b50: bd80 pop {r7, pc} 08006b52 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8006b52: b580 push {r7, lr} 8006b54: b082 sub sp, #8 8006b56: af00 add r7, sp, #0 8006b58: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8006b5a: 6878 ldr r0, [r7, #4] 8006b5c: f7ff ffa2 bl 8006aa4 8006b60: 4603 mov r3, r0 } 8006b62: 4618 mov r0, r3 8006b64: 3708 adds r7, #8 8006b66: 46bd mov sp, r7 8006b68: bd80 pop {r7, pc} 08006b6a : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8006b6a: b480 push {r7} 8006b6c: b085 sub sp, #20 8006b6e: af00 add r7, sp, #0 8006b70: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8006b72: 2300 movs r3, #0 8006b74: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 8006b76: 687b ldr r3, [r7, #4] 8006b78: f893 3021 ldrb.w r3, [r3, #33] ; 0x21 8006b7c: 2b02 cmp r3, #2 8006b7e: d008 beq.n 8006b92 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8006b80: 687b ldr r3, [r7, #4] 8006b82: 2204 movs r2, #4 8006b84: 639a str r2, [r3, #56] ; 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8006b86: 687b ldr r3, [r7, #4] 8006b88: 2200 movs r2, #0 8006b8a: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8006b8e: 2301 movs r3, #1 8006b90: e020 b.n 8006bd4 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8006b92: 687b ldr r3, [r7, #4] 8006b94: 681b ldr r3, [r3, #0] 8006b96: 681a ldr r2, [r3, #0] 8006b98: 687b ldr r3, [r7, #4] 8006b9a: 681b ldr r3, [r3, #0] 8006b9c: f022 020e bic.w r2, r2, #14 8006ba0: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8006ba2: 687b ldr r3, [r7, #4] 8006ba4: 681b ldr r3, [r3, #0] 8006ba6: 681a ldr r2, [r3, #0] 8006ba8: 687b ldr r3, [r7, #4] 8006baa: 681b ldr r3, [r3, #0] 8006bac: f022 0201 bic.w r2, r2, #1 8006bb0: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8006bb2: 687b ldr r3, [r7, #4] 8006bb4: 6c1a ldr r2, [r3, #64] ; 0x40 8006bb6: 687b ldr r3, [r7, #4] 8006bb8: 6bdb ldr r3, [r3, #60] ; 0x3c 8006bba: 2101 movs r1, #1 8006bbc: fa01 f202 lsl.w r2, r1, r2 8006bc0: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8006bc2: 687b ldr r3, [r7, #4] 8006bc4: 2201 movs r2, #1 8006bc6: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8006bca: 687b ldr r3, [r7, #4] 8006bcc: 2200 movs r2, #0 8006bce: f883 2020 strb.w r2, [r3, #32] return status; 8006bd2: 7bfb ldrb r3, [r7, #15] } 8006bd4: 4618 mov r0, r3 8006bd6: 3714 adds r7, #20 8006bd8: 46bd mov sp, r7 8006bda: bc80 pop {r7} 8006bdc: 4770 bx lr ... 08006be0 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8006be0: b580 push {r7, lr} 8006be2: b084 sub sp, #16 8006be4: af00 add r7, sp, #0 8006be6: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8006be8: 2300 movs r3, #0 8006bea: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 8006bec: 687b ldr r3, [r7, #4] 8006bee: f893 3021 ldrb.w r3, [r3, #33] ; 0x21 8006bf2: 2b02 cmp r3, #2 8006bf4: d005 beq.n 8006c02 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8006bf6: 687b ldr r3, [r7, #4] 8006bf8: 2204 movs r2, #4 8006bfa: 639a str r2, [r3, #56] ; 0x38 status = HAL_ERROR; 8006bfc: 2301 movs r3, #1 8006bfe: 73fb strb r3, [r7, #15] 8006c00: e0d6 b.n 8006db0 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8006c02: 687b ldr r3, [r7, #4] 8006c04: 681b ldr r3, [r3, #0] 8006c06: 681a ldr r2, [r3, #0] 8006c08: 687b ldr r3, [r7, #4] 8006c0a: 681b ldr r3, [r3, #0] 8006c0c: f022 020e bic.w r2, r2, #14 8006c10: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8006c12: 687b ldr r3, [r7, #4] 8006c14: 681b ldr r3, [r3, #0] 8006c16: 681a ldr r2, [r3, #0] 8006c18: 687b ldr r3, [r7, #4] 8006c1a: 681b ldr r3, [r3, #0] 8006c1c: f022 0201 bic.w r2, r2, #1 8006c20: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 8006c22: 687b ldr r3, [r7, #4] 8006c24: 681b ldr r3, [r3, #0] 8006c26: 461a mov r2, r3 8006c28: 4b64 ldr r3, [pc, #400] ; (8006dbc ) 8006c2a: 429a cmp r2, r3 8006c2c: d958 bls.n 8006ce0 8006c2e: 687b ldr r3, [r7, #4] 8006c30: 681b ldr r3, [r3, #0] 8006c32: 4a63 ldr r2, [pc, #396] ; (8006dc0 ) 8006c34: 4293 cmp r3, r2 8006c36: d04f beq.n 8006cd8 8006c38: 687b ldr r3, [r7, #4] 8006c3a: 681b ldr r3, [r3, #0] 8006c3c: 4a61 ldr r2, [pc, #388] ; (8006dc4 ) 8006c3e: 4293 cmp r3, r2 8006c40: d048 beq.n 8006cd4 8006c42: 687b ldr r3, [r7, #4] 8006c44: 681b ldr r3, [r3, #0] 8006c46: 4a60 ldr r2, [pc, #384] ; (8006dc8 ) 8006c48: 4293 cmp r3, r2 8006c4a: d040 beq.n 8006cce 8006c4c: 687b ldr r3, [r7, #4] 8006c4e: 681b ldr r3, [r3, #0] 8006c50: 4a5e ldr r2, [pc, #376] ; (8006dcc ) 8006c52: 4293 cmp r3, r2 8006c54: d038 beq.n 8006cc8 8006c56: 687b ldr r3, [r7, #4] 8006c58: 681b ldr r3, [r3, #0] 8006c5a: 4a5d ldr r2, [pc, #372] ; (8006dd0 ) 8006c5c: 4293 cmp r3, r2 8006c5e: d030 beq.n 8006cc2 8006c60: 687b ldr r3, [r7, #4] 8006c62: 681b ldr r3, [r3, #0] 8006c64: 4a5b ldr r2, [pc, #364] ; (8006dd4 ) 8006c66: 4293 cmp r3, r2 8006c68: d028 beq.n 8006cbc 8006c6a: 687b ldr r3, [r7, #4] 8006c6c: 681b ldr r3, [r3, #0] 8006c6e: 4a53 ldr r2, [pc, #332] ; (8006dbc ) 8006c70: 4293 cmp r3, r2 8006c72: d020 beq.n 8006cb6 8006c74: 687b ldr r3, [r7, #4] 8006c76: 681b ldr r3, [r3, #0] 8006c78: 4a57 ldr r2, [pc, #348] ; (8006dd8 ) 8006c7a: 4293 cmp r3, r2 8006c7c: d019 beq.n 8006cb2 8006c7e: 687b ldr r3, [r7, #4] 8006c80: 681b ldr r3, [r3, #0] 8006c82: 4a56 ldr r2, [pc, #344] ; (8006ddc ) 8006c84: 4293 cmp r3, r2 8006c86: d012 beq.n 8006cae 8006c88: 687b ldr r3, [r7, #4] 8006c8a: 681b ldr r3, [r3, #0] 8006c8c: 4a54 ldr r2, [pc, #336] ; (8006de0 ) 8006c8e: 4293 cmp r3, r2 8006c90: d00a beq.n 8006ca8 8006c92: 687b ldr r3, [r7, #4] 8006c94: 681b ldr r3, [r3, #0] 8006c96: 4a53 ldr r2, [pc, #332] ; (8006de4 ) 8006c98: 4293 cmp r3, r2 8006c9a: d102 bne.n 8006ca2 8006c9c: f44f 5380 mov.w r3, #4096 ; 0x1000 8006ca0: e01b b.n 8006cda 8006ca2: f44f 3380 mov.w r3, #65536 ; 0x10000 8006ca6: e018 b.n 8006cda 8006ca8: f44f 7380 mov.w r3, #256 ; 0x100 8006cac: e015 b.n 8006cda 8006cae: 2310 movs r3, #16 8006cb0: e013 b.n 8006cda 8006cb2: 2301 movs r3, #1 8006cb4: e011 b.n 8006cda 8006cb6: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8006cba: e00e b.n 8006cda 8006cbc: f44f 1380 mov.w r3, #1048576 ; 0x100000 8006cc0: e00b b.n 8006cda 8006cc2: f44f 3380 mov.w r3, #65536 ; 0x10000 8006cc6: e008 b.n 8006cda 8006cc8: f44f 5380 mov.w r3, #4096 ; 0x1000 8006ccc: e005 b.n 8006cda 8006cce: f44f 7380 mov.w r3, #256 ; 0x100 8006cd2: e002 b.n 8006cda 8006cd4: 2310 movs r3, #16 8006cd6: e000 b.n 8006cda 8006cd8: 2301 movs r3, #1 8006cda: 4a43 ldr r2, [pc, #268] ; (8006de8 ) 8006cdc: 6053 str r3, [r2, #4] 8006cde: e057 b.n 8006d90 8006ce0: 687b ldr r3, [r7, #4] 8006ce2: 681b ldr r3, [r3, #0] 8006ce4: 4a36 ldr r2, [pc, #216] ; (8006dc0 ) 8006ce6: 4293 cmp r3, r2 8006ce8: d04f beq.n 8006d8a 8006cea: 687b ldr r3, [r7, #4] 8006cec: 681b ldr r3, [r3, #0] 8006cee: 4a35 ldr r2, [pc, #212] ; (8006dc4 ) 8006cf0: 4293 cmp r3, r2 8006cf2: d048 beq.n 8006d86 8006cf4: 687b ldr r3, [r7, #4] 8006cf6: 681b ldr r3, [r3, #0] 8006cf8: 4a33 ldr r2, [pc, #204] ; (8006dc8 ) 8006cfa: 4293 cmp r3, r2 8006cfc: d040 beq.n 8006d80 8006cfe: 687b ldr r3, [r7, #4] 8006d00: 681b ldr r3, [r3, #0] 8006d02: 4a32 ldr r2, [pc, #200] ; (8006dcc ) 8006d04: 4293 cmp r3, r2 8006d06: d038 beq.n 8006d7a 8006d08: 687b ldr r3, [r7, #4] 8006d0a: 681b ldr r3, [r3, #0] 8006d0c: 4a30 ldr r2, [pc, #192] ; (8006dd0 ) 8006d0e: 4293 cmp r3, r2 8006d10: d030 beq.n 8006d74 8006d12: 687b ldr r3, [r7, #4] 8006d14: 681b ldr r3, [r3, #0] 8006d16: 4a2f ldr r2, [pc, #188] ; (8006dd4 ) 8006d18: 4293 cmp r3, r2 8006d1a: d028 beq.n 8006d6e 8006d1c: 687b ldr r3, [r7, #4] 8006d1e: 681b ldr r3, [r3, #0] 8006d20: 4a26 ldr r2, [pc, #152] ; (8006dbc ) 8006d22: 4293 cmp r3, r2 8006d24: d020 beq.n 8006d68 8006d26: 687b ldr r3, [r7, #4] 8006d28: 681b ldr r3, [r3, #0] 8006d2a: 4a2b ldr r2, [pc, #172] ; (8006dd8 ) 8006d2c: 4293 cmp r3, r2 8006d2e: d019 beq.n 8006d64 8006d30: 687b ldr r3, [r7, #4] 8006d32: 681b ldr r3, [r3, #0] 8006d34: 4a29 ldr r2, [pc, #164] ; (8006ddc ) 8006d36: 4293 cmp r3, r2 8006d38: d012 beq.n 8006d60 8006d3a: 687b ldr r3, [r7, #4] 8006d3c: 681b ldr r3, [r3, #0] 8006d3e: 4a28 ldr r2, [pc, #160] ; (8006de0 ) 8006d40: 4293 cmp r3, r2 8006d42: d00a beq.n 8006d5a 8006d44: 687b ldr r3, [r7, #4] 8006d46: 681b ldr r3, [r3, #0] 8006d48: 4a26 ldr r2, [pc, #152] ; (8006de4 ) 8006d4a: 4293 cmp r3, r2 8006d4c: d102 bne.n 8006d54 8006d4e: f44f 5380 mov.w r3, #4096 ; 0x1000 8006d52: e01b b.n 8006d8c 8006d54: f44f 3380 mov.w r3, #65536 ; 0x10000 8006d58: e018 b.n 8006d8c 8006d5a: f44f 7380 mov.w r3, #256 ; 0x100 8006d5e: e015 b.n 8006d8c 8006d60: 2310 movs r3, #16 8006d62: e013 b.n 8006d8c 8006d64: 2301 movs r3, #1 8006d66: e011 b.n 8006d8c 8006d68: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8006d6c: e00e b.n 8006d8c 8006d6e: f44f 1380 mov.w r3, #1048576 ; 0x100000 8006d72: e00b b.n 8006d8c 8006d74: f44f 3380 mov.w r3, #65536 ; 0x10000 8006d78: e008 b.n 8006d8c 8006d7a: f44f 5380 mov.w r3, #4096 ; 0x1000 8006d7e: e005 b.n 8006d8c 8006d80: f44f 7380 mov.w r3, #256 ; 0x100 8006d84: e002 b.n 8006d8c 8006d86: 2310 movs r3, #16 8006d88: e000 b.n 8006d8c 8006d8a: 2301 movs r3, #1 8006d8c: 4a17 ldr r2, [pc, #92] ; (8006dec ) 8006d8e: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8006d90: 687b ldr r3, [r7, #4] 8006d92: 2201 movs r2, #1 8006d94: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8006d98: 687b ldr r3, [r7, #4] 8006d9a: 2200 movs r2, #0 8006d9c: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8006da0: 687b ldr r3, [r7, #4] 8006da2: 6b5b ldr r3, [r3, #52] ; 0x34 8006da4: 2b00 cmp r3, #0 8006da6: d003 beq.n 8006db0 { hdma->XferAbortCallback(hdma); 8006da8: 687b ldr r3, [r7, #4] 8006daa: 6b5b ldr r3, [r3, #52] ; 0x34 8006dac: 6878 ldr r0, [r7, #4] 8006dae: 4798 blx r3 } } return status; 8006db0: 7bfb ldrb r3, [r7, #15] } 8006db2: 4618 mov r0, r3 8006db4: 3710 adds r7, #16 8006db6: 46bd mov sp, r7 8006db8: bd80 pop {r7, pc} 8006dba: bf00 nop 8006dbc: 40020080 .word 0x40020080 8006dc0: 40020008 .word 0x40020008 8006dc4: 4002001c .word 0x4002001c 8006dc8: 40020030 .word 0x40020030 8006dcc: 40020044 .word 0x40020044 8006dd0: 40020058 .word 0x40020058 8006dd4: 4002006c .word 0x4002006c 8006dd8: 40020408 .word 0x40020408 8006ddc: 4002041c .word 0x4002041c 8006de0: 40020430 .word 0x40020430 8006de4: 40020444 .word 0x40020444 8006de8: 40020400 .word 0x40020400 8006dec: 40020000 .word 0x40020000 08006df0 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8006df0: b480 push {r7} 8006df2: b08b sub sp, #44 ; 0x2c 8006df4: af00 add r7, sp, #0 8006df6: 6078 str r0, [r7, #4] 8006df8: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8006dfa: 2300 movs r3, #0 8006dfc: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8006dfe: 2300 movs r3, #0 8006e00: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8006e02: e169 b.n 80070d8 { /* Get the IO position */ ioposition = (0x01uL << position); 8006e04: 2201 movs r2, #1 8006e06: 6a7b ldr r3, [r7, #36] ; 0x24 8006e08: fa02 f303 lsl.w r3, r2, r3 8006e0c: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8006e0e: 683b ldr r3, [r7, #0] 8006e10: 681b ldr r3, [r3, #0] 8006e12: 69fa ldr r2, [r7, #28] 8006e14: 4013 ands r3, r2 8006e16: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8006e18: 69ba ldr r2, [r7, #24] 8006e1a: 69fb ldr r3, [r7, #28] 8006e1c: 429a cmp r2, r3 8006e1e: f040 8158 bne.w 80070d2 { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 8006e22: 683b ldr r3, [r7, #0] 8006e24: 685b ldr r3, [r3, #4] 8006e26: 4a9a ldr r2, [pc, #616] ; (8007090 ) 8006e28: 4293 cmp r3, r2 8006e2a: d05e beq.n 8006eea 8006e2c: 4a98 ldr r2, [pc, #608] ; (8007090 ) 8006e2e: 4293 cmp r3, r2 8006e30: d875 bhi.n 8006f1e 8006e32: 4a98 ldr r2, [pc, #608] ; (8007094 ) 8006e34: 4293 cmp r3, r2 8006e36: d058 beq.n 8006eea 8006e38: 4a96 ldr r2, [pc, #600] ; (8007094 ) 8006e3a: 4293 cmp r3, r2 8006e3c: d86f bhi.n 8006f1e 8006e3e: 4a96 ldr r2, [pc, #600] ; (8007098 ) 8006e40: 4293 cmp r3, r2 8006e42: d052 beq.n 8006eea 8006e44: 4a94 ldr r2, [pc, #592] ; (8007098 ) 8006e46: 4293 cmp r3, r2 8006e48: d869 bhi.n 8006f1e 8006e4a: 4a94 ldr r2, [pc, #592] ; (800709c ) 8006e4c: 4293 cmp r3, r2 8006e4e: d04c beq.n 8006eea 8006e50: 4a92 ldr r2, [pc, #584] ; (800709c ) 8006e52: 4293 cmp r3, r2 8006e54: d863 bhi.n 8006f1e 8006e56: 4a92 ldr r2, [pc, #584] ; (80070a0 ) 8006e58: 4293 cmp r3, r2 8006e5a: d046 beq.n 8006eea 8006e5c: 4a90 ldr r2, [pc, #576] ; (80070a0 ) 8006e5e: 4293 cmp r3, r2 8006e60: d85d bhi.n 8006f1e 8006e62: 2b12 cmp r3, #18 8006e64: d82a bhi.n 8006ebc 8006e66: 2b12 cmp r3, #18 8006e68: d859 bhi.n 8006f1e 8006e6a: a201 add r2, pc, #4 ; (adr r2, 8006e70 ) 8006e6c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8006e70: 08006eeb .word 0x08006eeb 8006e74: 08006ec5 .word 0x08006ec5 8006e78: 08006ed7 .word 0x08006ed7 8006e7c: 08006f19 .word 0x08006f19 8006e80: 08006f1f .word 0x08006f1f 8006e84: 08006f1f .word 0x08006f1f 8006e88: 08006f1f .word 0x08006f1f 8006e8c: 08006f1f .word 0x08006f1f 8006e90: 08006f1f .word 0x08006f1f 8006e94: 08006f1f .word 0x08006f1f 8006e98: 08006f1f .word 0x08006f1f 8006e9c: 08006f1f .word 0x08006f1f 8006ea0: 08006f1f .word 0x08006f1f 8006ea4: 08006f1f .word 0x08006f1f 8006ea8: 08006f1f .word 0x08006f1f 8006eac: 08006f1f .word 0x08006f1f 8006eb0: 08006f1f .word 0x08006f1f 8006eb4: 08006ecd .word 0x08006ecd 8006eb8: 08006ee1 .word 0x08006ee1 8006ebc: 4a79 ldr r2, [pc, #484] ; (80070a4 ) 8006ebe: 4293 cmp r3, r2 8006ec0: d013 beq.n 8006eea config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8006ec2: e02c b.n 8006f1e config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8006ec4: 683b ldr r3, [r7, #0] 8006ec6: 68db ldr r3, [r3, #12] 8006ec8: 623b str r3, [r7, #32] break; 8006eca: e029 b.n 8006f20 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8006ecc: 683b ldr r3, [r7, #0] 8006ece: 68db ldr r3, [r3, #12] 8006ed0: 3304 adds r3, #4 8006ed2: 623b str r3, [r7, #32] break; 8006ed4: e024 b.n 8006f20 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8006ed6: 683b ldr r3, [r7, #0] 8006ed8: 68db ldr r3, [r3, #12] 8006eda: 3308 adds r3, #8 8006edc: 623b str r3, [r7, #32] break; 8006ede: e01f b.n 8006f20 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8006ee0: 683b ldr r3, [r7, #0] 8006ee2: 68db ldr r3, [r3, #12] 8006ee4: 330c adds r3, #12 8006ee6: 623b str r3, [r7, #32] break; 8006ee8: e01a b.n 8006f20 if (GPIO_Init->Pull == GPIO_NOPULL) 8006eea: 683b ldr r3, [r7, #0] 8006eec: 689b ldr r3, [r3, #8] 8006eee: 2b00 cmp r3, #0 8006ef0: d102 bne.n 8006ef8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8006ef2: 2304 movs r3, #4 8006ef4: 623b str r3, [r7, #32] break; 8006ef6: e013 b.n 8006f20 else if (GPIO_Init->Pull == GPIO_PULLUP) 8006ef8: 683b ldr r3, [r7, #0] 8006efa: 689b ldr r3, [r3, #8] 8006efc: 2b01 cmp r3, #1 8006efe: d105 bne.n 8006f0c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8006f00: 2308 movs r3, #8 8006f02: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8006f04: 687b ldr r3, [r7, #4] 8006f06: 69fa ldr r2, [r7, #28] 8006f08: 611a str r2, [r3, #16] break; 8006f0a: e009 b.n 8006f20 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8006f0c: 2308 movs r3, #8 8006f0e: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 8006f10: 687b ldr r3, [r7, #4] 8006f12: 69fa ldr r2, [r7, #28] 8006f14: 615a str r2, [r3, #20] break; 8006f16: e003 b.n 8006f20 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8006f18: 2300 movs r3, #0 8006f1a: 623b str r3, [r7, #32] break; 8006f1c: e000 b.n 8006f20 break; 8006f1e: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8006f20: 69bb ldr r3, [r7, #24] 8006f22: 2bff cmp r3, #255 ; 0xff 8006f24: d801 bhi.n 8006f2a 8006f26: 687b ldr r3, [r7, #4] 8006f28: e001 b.n 8006f2e 8006f2a: 687b ldr r3, [r7, #4] 8006f2c: 3304 adds r3, #4 8006f2e: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8006f30: 69bb ldr r3, [r7, #24] 8006f32: 2bff cmp r3, #255 ; 0xff 8006f34: d802 bhi.n 8006f3c 8006f36: 6a7b ldr r3, [r7, #36] ; 0x24 8006f38: 009b lsls r3, r3, #2 8006f3a: e002 b.n 8006f42 8006f3c: 6a7b ldr r3, [r7, #36] ; 0x24 8006f3e: 3b08 subs r3, #8 8006f40: 009b lsls r3, r3, #2 8006f42: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8006f44: 697b ldr r3, [r7, #20] 8006f46: 681a ldr r2, [r3, #0] 8006f48: 210f movs r1, #15 8006f4a: 693b ldr r3, [r7, #16] 8006f4c: fa01 f303 lsl.w r3, r1, r3 8006f50: 43db mvns r3, r3 8006f52: 401a ands r2, r3 8006f54: 6a39 ldr r1, [r7, #32] 8006f56: 693b ldr r3, [r7, #16] 8006f58: fa01 f303 lsl.w r3, r1, r3 8006f5c: 431a orrs r2, r3 8006f5e: 697b ldr r3, [r7, #20] 8006f60: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8006f62: 683b ldr r3, [r7, #0] 8006f64: 685b ldr r3, [r3, #4] 8006f66: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8006f6a: 2b00 cmp r3, #0 8006f6c: f000 80b1 beq.w 80070d2 { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8006f70: 4b4d ldr r3, [pc, #308] ; (80070a8 ) 8006f72: 699b ldr r3, [r3, #24] 8006f74: 4a4c ldr r2, [pc, #304] ; (80070a8 ) 8006f76: f043 0301 orr.w r3, r3, #1 8006f7a: 6193 str r3, [r2, #24] 8006f7c: 4b4a ldr r3, [pc, #296] ; (80070a8 ) 8006f7e: 699b ldr r3, [r3, #24] 8006f80: f003 0301 and.w r3, r3, #1 8006f84: 60bb str r3, [r7, #8] 8006f86: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8006f88: 4a48 ldr r2, [pc, #288] ; (80070ac ) 8006f8a: 6a7b ldr r3, [r7, #36] ; 0x24 8006f8c: 089b lsrs r3, r3, #2 8006f8e: 3302 adds r3, #2 8006f90: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8006f94: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8006f96: 6a7b ldr r3, [r7, #36] ; 0x24 8006f98: f003 0303 and.w r3, r3, #3 8006f9c: 009b lsls r3, r3, #2 8006f9e: 220f movs r2, #15 8006fa0: fa02 f303 lsl.w r3, r2, r3 8006fa4: 43db mvns r3, r3 8006fa6: 68fa ldr r2, [r7, #12] 8006fa8: 4013 ands r3, r2 8006faa: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8006fac: 687b ldr r3, [r7, #4] 8006fae: 4a40 ldr r2, [pc, #256] ; (80070b0 ) 8006fb0: 4293 cmp r3, r2 8006fb2: d013 beq.n 8006fdc 8006fb4: 687b ldr r3, [r7, #4] 8006fb6: 4a3f ldr r2, [pc, #252] ; (80070b4 ) 8006fb8: 4293 cmp r3, r2 8006fba: d00d beq.n 8006fd8 8006fbc: 687b ldr r3, [r7, #4] 8006fbe: 4a3e ldr r2, [pc, #248] ; (80070b8 ) 8006fc0: 4293 cmp r3, r2 8006fc2: d007 beq.n 8006fd4 8006fc4: 687b ldr r3, [r7, #4] 8006fc6: 4a3d ldr r2, [pc, #244] ; (80070bc ) 8006fc8: 4293 cmp r3, r2 8006fca: d101 bne.n 8006fd0 8006fcc: 2303 movs r3, #3 8006fce: e006 b.n 8006fde 8006fd0: 2304 movs r3, #4 8006fd2: e004 b.n 8006fde 8006fd4: 2302 movs r3, #2 8006fd6: e002 b.n 8006fde 8006fd8: 2301 movs r3, #1 8006fda: e000 b.n 8006fde 8006fdc: 2300 movs r3, #0 8006fde: 6a7a ldr r2, [r7, #36] ; 0x24 8006fe0: f002 0203 and.w r2, r2, #3 8006fe4: 0092 lsls r2, r2, #2 8006fe6: 4093 lsls r3, r2 8006fe8: 68fa ldr r2, [r7, #12] 8006fea: 4313 orrs r3, r2 8006fec: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8006fee: 492f ldr r1, [pc, #188] ; (80070ac ) 8006ff0: 6a7b ldr r3, [r7, #36] ; 0x24 8006ff2: 089b lsrs r3, r3, #2 8006ff4: 3302 adds r3, #2 8006ff6: 68fa ldr r2, [r7, #12] 8006ff8: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8006ffc: 683b ldr r3, [r7, #0] 8006ffe: 685b ldr r3, [r3, #4] 8007000: f403 3380 and.w r3, r3, #65536 ; 0x10000 8007004: 2b00 cmp r3, #0 8007006: d006 beq.n 8007016 { SET_BIT(EXTI->IMR, iocurrent); 8007008: 4b2d ldr r3, [pc, #180] ; (80070c0 ) 800700a: 681a ldr r2, [r3, #0] 800700c: 492c ldr r1, [pc, #176] ; (80070c0 ) 800700e: 69bb ldr r3, [r7, #24] 8007010: 4313 orrs r3, r2 8007012: 600b str r3, [r1, #0] 8007014: e006 b.n 8007024 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8007016: 4b2a ldr r3, [pc, #168] ; (80070c0 ) 8007018: 681a ldr r2, [r3, #0] 800701a: 69bb ldr r3, [r7, #24] 800701c: 43db mvns r3, r3 800701e: 4928 ldr r1, [pc, #160] ; (80070c0 ) 8007020: 4013 ands r3, r2 8007022: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8007024: 683b ldr r3, [r7, #0] 8007026: 685b ldr r3, [r3, #4] 8007028: f403 3300 and.w r3, r3, #131072 ; 0x20000 800702c: 2b00 cmp r3, #0 800702e: d006 beq.n 800703e { SET_BIT(EXTI->EMR, iocurrent); 8007030: 4b23 ldr r3, [pc, #140] ; (80070c0 ) 8007032: 685a ldr r2, [r3, #4] 8007034: 4922 ldr r1, [pc, #136] ; (80070c0 ) 8007036: 69bb ldr r3, [r7, #24] 8007038: 4313 orrs r3, r2 800703a: 604b str r3, [r1, #4] 800703c: e006 b.n 800704c } else { CLEAR_BIT(EXTI->EMR, iocurrent); 800703e: 4b20 ldr r3, [pc, #128] ; (80070c0 ) 8007040: 685a ldr r2, [r3, #4] 8007042: 69bb ldr r3, [r7, #24] 8007044: 43db mvns r3, r3 8007046: 491e ldr r1, [pc, #120] ; (80070c0 ) 8007048: 4013 ands r3, r2 800704a: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 800704c: 683b ldr r3, [r7, #0] 800704e: 685b ldr r3, [r3, #4] 8007050: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8007054: 2b00 cmp r3, #0 8007056: d006 beq.n 8007066 { SET_BIT(EXTI->RTSR, iocurrent); 8007058: 4b19 ldr r3, [pc, #100] ; (80070c0 ) 800705a: 689a ldr r2, [r3, #8] 800705c: 4918 ldr r1, [pc, #96] ; (80070c0 ) 800705e: 69bb ldr r3, [r7, #24] 8007060: 4313 orrs r3, r2 8007062: 608b str r3, [r1, #8] 8007064: e006 b.n 8007074 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8007066: 4b16 ldr r3, [pc, #88] ; (80070c0 ) 8007068: 689a ldr r2, [r3, #8] 800706a: 69bb ldr r3, [r7, #24] 800706c: 43db mvns r3, r3 800706e: 4914 ldr r1, [pc, #80] ; (80070c0 ) 8007070: 4013 ands r3, r2 8007072: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8007074: 683b ldr r3, [r7, #0] 8007076: 685b ldr r3, [r3, #4] 8007078: f403 1300 and.w r3, r3, #2097152 ; 0x200000 800707c: 2b00 cmp r3, #0 800707e: d021 beq.n 80070c4 { SET_BIT(EXTI->FTSR, iocurrent); 8007080: 4b0f ldr r3, [pc, #60] ; (80070c0 ) 8007082: 68da ldr r2, [r3, #12] 8007084: 490e ldr r1, [pc, #56] ; (80070c0 ) 8007086: 69bb ldr r3, [r7, #24] 8007088: 4313 orrs r3, r2 800708a: 60cb str r3, [r1, #12] 800708c: e021 b.n 80070d2 800708e: bf00 nop 8007090: 10320000 .word 0x10320000 8007094: 10310000 .word 0x10310000 8007098: 10220000 .word 0x10220000 800709c: 10210000 .word 0x10210000 80070a0: 10120000 .word 0x10120000 80070a4: 10110000 .word 0x10110000 80070a8: 40021000 .word 0x40021000 80070ac: 40010000 .word 0x40010000 80070b0: 40010800 .word 0x40010800 80070b4: 40010c00 .word 0x40010c00 80070b8: 40011000 .word 0x40011000 80070bc: 40011400 .word 0x40011400 80070c0: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 80070c4: 4b0b ldr r3, [pc, #44] ; (80070f4 ) 80070c6: 68da ldr r2, [r3, #12] 80070c8: 69bb ldr r3, [r7, #24] 80070ca: 43db mvns r3, r3 80070cc: 4909 ldr r1, [pc, #36] ; (80070f4 ) 80070ce: 4013 ands r3, r2 80070d0: 60cb str r3, [r1, #12] } } } position++; 80070d2: 6a7b ldr r3, [r7, #36] ; 0x24 80070d4: 3301 adds r3, #1 80070d6: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 80070d8: 683b ldr r3, [r7, #0] 80070da: 681a ldr r2, [r3, #0] 80070dc: 6a7b ldr r3, [r7, #36] ; 0x24 80070de: fa22 f303 lsr.w r3, r2, r3 80070e2: 2b00 cmp r3, #0 80070e4: f47f ae8e bne.w 8006e04 } } 80070e8: bf00 nop 80070ea: bf00 nop 80070ec: 372c adds r7, #44 ; 0x2c 80070ee: 46bd mov sp, r7 80070f0: bc80 pop {r7} 80070f2: 4770 bx lr 80070f4: 40010400 .word 0x40010400 080070f8 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 80070f8: b480 push {r7} 80070fa: b085 sub sp, #20 80070fc: af00 add r7, sp, #0 80070fe: 6078 str r0, [r7, #4] 8007100: 460b mov r3, r1 8007102: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8007104: 687b ldr r3, [r7, #4] 8007106: 689a ldr r2, [r3, #8] 8007108: 887b ldrh r3, [r7, #2] 800710a: 4013 ands r3, r2 800710c: 2b00 cmp r3, #0 800710e: d002 beq.n 8007116 { bitstatus = GPIO_PIN_SET; 8007110: 2301 movs r3, #1 8007112: 73fb strb r3, [r7, #15] 8007114: e001 b.n 800711a } else { bitstatus = GPIO_PIN_RESET; 8007116: 2300 movs r3, #0 8007118: 73fb strb r3, [r7, #15] } return bitstatus; 800711a: 7bfb ldrb r3, [r7, #15] } 800711c: 4618 mov r0, r3 800711e: 3714 adds r7, #20 8007120: 46bd mov sp, r7 8007122: bc80 pop {r7} 8007124: 4770 bx lr 08007126 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8007126: b480 push {r7} 8007128: b083 sub sp, #12 800712a: af00 add r7, sp, #0 800712c: 6078 str r0, [r7, #4] 800712e: 460b mov r3, r1 8007130: 807b strh r3, [r7, #2] 8007132: 4613 mov r3, r2 8007134: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8007136: 787b ldrb r3, [r7, #1] 8007138: 2b00 cmp r3, #0 800713a: d003 beq.n 8007144 { GPIOx->BSRR = GPIO_Pin; 800713c: 887a ldrh r2, [r7, #2] 800713e: 687b ldr r3, [r7, #4] 8007140: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8007142: e003 b.n 800714c GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8007144: 887b ldrh r3, [r7, #2] 8007146: 041a lsls r2, r3, #16 8007148: 687b ldr r3, [r7, #4] 800714a: 611a str r2, [r3, #16] } 800714c: bf00 nop 800714e: 370c adds r7, #12 8007150: 46bd mov sp, r7 8007152: bc80 pop {r7} 8007154: 4770 bx lr ... 08007158 : * @note If the HSE divided by 128 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 8007158: b480 push {r7} 800715a: af00 add r7, sp, #0 /* Enable access to RTC and backup registers */ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 800715c: 4b03 ldr r3, [pc, #12] ; (800716c ) 800715e: 2201 movs r2, #1 8007160: 601a str r2, [r3, #0] } 8007162: bf00 nop 8007164: 46bd mov sp, r7 8007166: bc80 pop {r7} 8007168: 4770 bx lr 800716a: bf00 nop 800716c: 420e0020 .word 0x420e0020 08007170 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8007170: b580 push {r7, lr} 8007172: b086 sub sp, #24 8007174: af00 add r7, sp, #0 8007176: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8007178: 687b ldr r3, [r7, #4] 800717a: 2b00 cmp r3, #0 800717c: d101 bne.n 8007182 { return HAL_ERROR; 800717e: 2301 movs r3, #1 8007180: e304 b.n 800778c /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8007182: 687b ldr r3, [r7, #4] 8007184: 681b ldr r3, [r3, #0] 8007186: f003 0301 and.w r3, r3, #1 800718a: 2b00 cmp r3, #0 800718c: f000 8087 beq.w 800729e { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8007190: 4b92 ldr r3, [pc, #584] ; (80073dc ) 8007192: 685b ldr r3, [r3, #4] 8007194: f003 030c and.w r3, r3, #12 8007198: 2b04 cmp r3, #4 800719a: d00c beq.n 80071b6 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 800719c: 4b8f ldr r3, [pc, #572] ; (80073dc ) 800719e: 685b ldr r3, [r3, #4] 80071a0: f003 030c and.w r3, r3, #12 80071a4: 2b08 cmp r3, #8 80071a6: d112 bne.n 80071ce 80071a8: 4b8c ldr r3, [pc, #560] ; (80073dc ) 80071aa: 685b ldr r3, [r3, #4] 80071ac: f403 3380 and.w r3, r3, #65536 ; 0x10000 80071b0: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80071b4: d10b bne.n 80071ce { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80071b6: 4b89 ldr r3, [pc, #548] ; (80073dc ) 80071b8: 681b ldr r3, [r3, #0] 80071ba: f403 3300 and.w r3, r3, #131072 ; 0x20000 80071be: 2b00 cmp r3, #0 80071c0: d06c beq.n 800729c 80071c2: 687b ldr r3, [r7, #4] 80071c4: 689b ldr r3, [r3, #8] 80071c6: 2b00 cmp r3, #0 80071c8: d168 bne.n 800729c { return HAL_ERROR; 80071ca: 2301 movs r3, #1 80071cc: e2de b.n 800778c } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80071ce: 687b ldr r3, [r7, #4] 80071d0: 689b ldr r3, [r3, #8] 80071d2: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80071d6: d106 bne.n 80071e6 80071d8: 4b80 ldr r3, [pc, #512] ; (80073dc ) 80071da: 681b ldr r3, [r3, #0] 80071dc: 4a7f ldr r2, [pc, #508] ; (80073dc ) 80071de: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80071e2: 6013 str r3, [r2, #0] 80071e4: e02e b.n 8007244 80071e6: 687b ldr r3, [r7, #4] 80071e8: 689b ldr r3, [r3, #8] 80071ea: 2b00 cmp r3, #0 80071ec: d10c bne.n 8007208 80071ee: 4b7b ldr r3, [pc, #492] ; (80073dc ) 80071f0: 681b ldr r3, [r3, #0] 80071f2: 4a7a ldr r2, [pc, #488] ; (80073dc ) 80071f4: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80071f8: 6013 str r3, [r2, #0] 80071fa: 4b78 ldr r3, [pc, #480] ; (80073dc ) 80071fc: 681b ldr r3, [r3, #0] 80071fe: 4a77 ldr r2, [pc, #476] ; (80073dc ) 8007200: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8007204: 6013 str r3, [r2, #0] 8007206: e01d b.n 8007244 8007208: 687b ldr r3, [r7, #4] 800720a: 689b ldr r3, [r3, #8] 800720c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8007210: d10c bne.n 800722c 8007212: 4b72 ldr r3, [pc, #456] ; (80073dc ) 8007214: 681b ldr r3, [r3, #0] 8007216: 4a71 ldr r2, [pc, #452] ; (80073dc ) 8007218: f443 2380 orr.w r3, r3, #262144 ; 0x40000 800721c: 6013 str r3, [r2, #0] 800721e: 4b6f ldr r3, [pc, #444] ; (80073dc ) 8007220: 681b ldr r3, [r3, #0] 8007222: 4a6e ldr r2, [pc, #440] ; (80073dc ) 8007224: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8007228: 6013 str r3, [r2, #0] 800722a: e00b b.n 8007244 800722c: 4b6b ldr r3, [pc, #428] ; (80073dc ) 800722e: 681b ldr r3, [r3, #0] 8007230: 4a6a ldr r2, [pc, #424] ; (80073dc ) 8007232: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8007236: 6013 str r3, [r2, #0] 8007238: 4b68 ldr r3, [pc, #416] ; (80073dc ) 800723a: 681b ldr r3, [r3, #0] 800723c: 4a67 ldr r2, [pc, #412] ; (80073dc ) 800723e: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8007242: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8007244: 687b ldr r3, [r7, #4] 8007246: 689b ldr r3, [r3, #8] 8007248: 2b00 cmp r3, #0 800724a: d013 beq.n 8007274 { /* Get Start Tick */ tickstart = HAL_GetTick(); 800724c: f7fd ffa2 bl 8005194 8007250: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8007252: e008 b.n 8007266 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8007254: f7fd ff9e bl 8005194 8007258: 4602 mov r2, r0 800725a: 693b ldr r3, [r7, #16] 800725c: 1ad3 subs r3, r2, r3 800725e: 2b64 cmp r3, #100 ; 0x64 8007260: d901 bls.n 8007266 { return HAL_TIMEOUT; 8007262: 2303 movs r3, #3 8007264: e292 b.n 800778c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8007266: 4b5d ldr r3, [pc, #372] ; (80073dc ) 8007268: 681b ldr r3, [r3, #0] 800726a: f403 3300 and.w r3, r3, #131072 ; 0x20000 800726e: 2b00 cmp r3, #0 8007270: d0f0 beq.n 8007254 8007272: e014 b.n 800729e } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8007274: f7fd ff8e bl 8005194 8007278: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800727a: e008 b.n 800728e { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800727c: f7fd ff8a bl 8005194 8007280: 4602 mov r2, r0 8007282: 693b ldr r3, [r7, #16] 8007284: 1ad3 subs r3, r2, r3 8007286: 2b64 cmp r3, #100 ; 0x64 8007288: d901 bls.n 800728e { return HAL_TIMEOUT; 800728a: 2303 movs r3, #3 800728c: e27e b.n 800778c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800728e: 4b53 ldr r3, [pc, #332] ; (80073dc ) 8007290: 681b ldr r3, [r3, #0] 8007292: f403 3300 and.w r3, r3, #131072 ; 0x20000 8007296: 2b00 cmp r3, #0 8007298: d1f0 bne.n 800727c 800729a: e000 b.n 800729e if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800729c: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800729e: 687b ldr r3, [r7, #4] 80072a0: 681b ldr r3, [r3, #0] 80072a2: f003 0302 and.w r3, r3, #2 80072a6: 2b00 cmp r3, #0 80072a8: d063 beq.n 8007372 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 80072aa: 4b4c ldr r3, [pc, #304] ; (80073dc ) 80072ac: 685b ldr r3, [r3, #4] 80072ae: f003 030c and.w r3, r3, #12 80072b2: 2b00 cmp r3, #0 80072b4: d00b beq.n 80072ce || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 80072b6: 4b49 ldr r3, [pc, #292] ; (80073dc ) 80072b8: 685b ldr r3, [r3, #4] 80072ba: f003 030c and.w r3, r3, #12 80072be: 2b08 cmp r3, #8 80072c0: d11c bne.n 80072fc 80072c2: 4b46 ldr r3, [pc, #280] ; (80073dc ) 80072c4: 685b ldr r3, [r3, #4] 80072c6: f403 3380 and.w r3, r3, #65536 ; 0x10000 80072ca: 2b00 cmp r3, #0 80072cc: d116 bne.n 80072fc { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80072ce: 4b43 ldr r3, [pc, #268] ; (80073dc ) 80072d0: 681b ldr r3, [r3, #0] 80072d2: f003 0302 and.w r3, r3, #2 80072d6: 2b00 cmp r3, #0 80072d8: d005 beq.n 80072e6 80072da: 687b ldr r3, [r7, #4] 80072dc: 695b ldr r3, [r3, #20] 80072de: 2b01 cmp r3, #1 80072e0: d001 beq.n 80072e6 { return HAL_ERROR; 80072e2: 2301 movs r3, #1 80072e4: e252 b.n 800778c } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80072e6: 4b3d ldr r3, [pc, #244] ; (80073dc ) 80072e8: 681b ldr r3, [r3, #0] 80072ea: f023 02f8 bic.w r2, r3, #248 ; 0xf8 80072ee: 687b ldr r3, [r7, #4] 80072f0: 699b ldr r3, [r3, #24] 80072f2: 00db lsls r3, r3, #3 80072f4: 4939 ldr r1, [pc, #228] ; (80073dc ) 80072f6: 4313 orrs r3, r2 80072f8: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80072fa: e03a b.n 8007372 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 80072fc: 687b ldr r3, [r7, #4] 80072fe: 695b ldr r3, [r3, #20] 8007300: 2b00 cmp r3, #0 8007302: d020 beq.n 8007346 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8007304: 4b36 ldr r3, [pc, #216] ; (80073e0 ) 8007306: 2201 movs r2, #1 8007308: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800730a: f7fd ff43 bl 8005194 800730e: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8007310: e008 b.n 8007324 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8007312: f7fd ff3f bl 8005194 8007316: 4602 mov r2, r0 8007318: 693b ldr r3, [r7, #16] 800731a: 1ad3 subs r3, r2, r3 800731c: 2b02 cmp r3, #2 800731e: d901 bls.n 8007324 { return HAL_TIMEOUT; 8007320: 2303 movs r3, #3 8007322: e233 b.n 800778c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8007324: 4b2d ldr r3, [pc, #180] ; (80073dc ) 8007326: 681b ldr r3, [r3, #0] 8007328: f003 0302 and.w r3, r3, #2 800732c: 2b00 cmp r3, #0 800732e: d0f0 beq.n 8007312 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8007330: 4b2a ldr r3, [pc, #168] ; (80073dc ) 8007332: 681b ldr r3, [r3, #0] 8007334: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8007338: 687b ldr r3, [r7, #4] 800733a: 699b ldr r3, [r3, #24] 800733c: 00db lsls r3, r3, #3 800733e: 4927 ldr r1, [pc, #156] ; (80073dc ) 8007340: 4313 orrs r3, r2 8007342: 600b str r3, [r1, #0] 8007344: e015 b.n 8007372 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8007346: 4b26 ldr r3, [pc, #152] ; (80073e0 ) 8007348: 2200 movs r2, #0 800734a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800734c: f7fd ff22 bl 8005194 8007350: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8007352: e008 b.n 8007366 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8007354: f7fd ff1e bl 8005194 8007358: 4602 mov r2, r0 800735a: 693b ldr r3, [r7, #16] 800735c: 1ad3 subs r3, r2, r3 800735e: 2b02 cmp r3, #2 8007360: d901 bls.n 8007366 { return HAL_TIMEOUT; 8007362: 2303 movs r3, #3 8007364: e212 b.n 800778c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8007366: 4b1d ldr r3, [pc, #116] ; (80073dc ) 8007368: 681b ldr r3, [r3, #0] 800736a: f003 0302 and.w r3, r3, #2 800736e: 2b00 cmp r3, #0 8007370: d1f0 bne.n 8007354 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8007372: 687b ldr r3, [r7, #4] 8007374: 681b ldr r3, [r3, #0] 8007376: f003 0308 and.w r3, r3, #8 800737a: 2b00 cmp r3, #0 800737c: d03a beq.n 80073f4 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 800737e: 687b ldr r3, [r7, #4] 8007380: 69db ldr r3, [r3, #28] 8007382: 2b00 cmp r3, #0 8007384: d019 beq.n 80073ba { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8007386: 4b17 ldr r3, [pc, #92] ; (80073e4 ) 8007388: 2201 movs r2, #1 800738a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800738c: f7fd ff02 bl 8005194 8007390: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8007392: e008 b.n 80073a6 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8007394: f7fd fefe bl 8005194 8007398: 4602 mov r2, r0 800739a: 693b ldr r3, [r7, #16] 800739c: 1ad3 subs r3, r2, r3 800739e: 2b02 cmp r3, #2 80073a0: d901 bls.n 80073a6 { return HAL_TIMEOUT; 80073a2: 2303 movs r3, #3 80073a4: e1f2 b.n 800778c while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 80073a6: 4b0d ldr r3, [pc, #52] ; (80073dc ) 80073a8: 6a5b ldr r3, [r3, #36] ; 0x24 80073aa: f003 0302 and.w r3, r3, #2 80073ae: 2b00 cmp r3, #0 80073b0: d0f0 beq.n 8007394 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 80073b2: 2001 movs r0, #1 80073b4: f000 fbec bl 8007b90 80073b8: e01c b.n 80073f4 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80073ba: 4b0a ldr r3, [pc, #40] ; (80073e4 ) 80073bc: 2200 movs r2, #0 80073be: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80073c0: f7fd fee8 bl 8005194 80073c4: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80073c6: e00f b.n 80073e8 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80073c8: f7fd fee4 bl 8005194 80073cc: 4602 mov r2, r0 80073ce: 693b ldr r3, [r7, #16] 80073d0: 1ad3 subs r3, r2, r3 80073d2: 2b02 cmp r3, #2 80073d4: d908 bls.n 80073e8 { return HAL_TIMEOUT; 80073d6: 2303 movs r3, #3 80073d8: e1d8 b.n 800778c 80073da: bf00 nop 80073dc: 40021000 .word 0x40021000 80073e0: 42420000 .word 0x42420000 80073e4: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80073e8: 4b9b ldr r3, [pc, #620] ; (8007658 ) 80073ea: 6a5b ldr r3, [r3, #36] ; 0x24 80073ec: f003 0302 and.w r3, r3, #2 80073f0: 2b00 cmp r3, #0 80073f2: d1e9 bne.n 80073c8 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80073f4: 687b ldr r3, [r7, #4] 80073f6: 681b ldr r3, [r3, #0] 80073f8: f003 0304 and.w r3, r3, #4 80073fc: 2b00 cmp r3, #0 80073fe: f000 80a6 beq.w 800754e { FlagStatus pwrclkchanged = RESET; 8007402: 2300 movs r3, #0 8007404: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8007406: 4b94 ldr r3, [pc, #592] ; (8007658 ) 8007408: 69db ldr r3, [r3, #28] 800740a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800740e: 2b00 cmp r3, #0 8007410: d10d bne.n 800742e { __HAL_RCC_PWR_CLK_ENABLE(); 8007412: 4b91 ldr r3, [pc, #580] ; (8007658 ) 8007414: 69db ldr r3, [r3, #28] 8007416: 4a90 ldr r2, [pc, #576] ; (8007658 ) 8007418: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 800741c: 61d3 str r3, [r2, #28] 800741e: 4b8e ldr r3, [pc, #568] ; (8007658 ) 8007420: 69db ldr r3, [r3, #28] 8007422: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8007426: 60bb str r3, [r7, #8] 8007428: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 800742a: 2301 movs r3, #1 800742c: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800742e: 4b8b ldr r3, [pc, #556] ; (800765c ) 8007430: 681b ldr r3, [r3, #0] 8007432: f403 7380 and.w r3, r3, #256 ; 0x100 8007436: 2b00 cmp r3, #0 8007438: d118 bne.n 800746c { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 800743a: 4b88 ldr r3, [pc, #544] ; (800765c ) 800743c: 681b ldr r3, [r3, #0] 800743e: 4a87 ldr r2, [pc, #540] ; (800765c ) 8007440: f443 7380 orr.w r3, r3, #256 ; 0x100 8007444: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8007446: f7fd fea5 bl 8005194 800744a: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800744c: e008 b.n 8007460 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800744e: f7fd fea1 bl 8005194 8007452: 4602 mov r2, r0 8007454: 693b ldr r3, [r7, #16] 8007456: 1ad3 subs r3, r2, r3 8007458: 2b64 cmp r3, #100 ; 0x64 800745a: d901 bls.n 8007460 { return HAL_TIMEOUT; 800745c: 2303 movs r3, #3 800745e: e195 b.n 800778c while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8007460: 4b7e ldr r3, [pc, #504] ; (800765c ) 8007462: 681b ldr r3, [r3, #0] 8007464: f403 7380 and.w r3, r3, #256 ; 0x100 8007468: 2b00 cmp r3, #0 800746a: d0f0 beq.n 800744e } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800746c: 687b ldr r3, [r7, #4] 800746e: 691b ldr r3, [r3, #16] 8007470: 2b01 cmp r3, #1 8007472: d106 bne.n 8007482 8007474: 4b78 ldr r3, [pc, #480] ; (8007658 ) 8007476: 6a1b ldr r3, [r3, #32] 8007478: 4a77 ldr r2, [pc, #476] ; (8007658 ) 800747a: f043 0301 orr.w r3, r3, #1 800747e: 6213 str r3, [r2, #32] 8007480: e02d b.n 80074de 8007482: 687b ldr r3, [r7, #4] 8007484: 691b ldr r3, [r3, #16] 8007486: 2b00 cmp r3, #0 8007488: d10c bne.n 80074a4 800748a: 4b73 ldr r3, [pc, #460] ; (8007658 ) 800748c: 6a1b ldr r3, [r3, #32] 800748e: 4a72 ldr r2, [pc, #456] ; (8007658 ) 8007490: f023 0301 bic.w r3, r3, #1 8007494: 6213 str r3, [r2, #32] 8007496: 4b70 ldr r3, [pc, #448] ; (8007658 ) 8007498: 6a1b ldr r3, [r3, #32] 800749a: 4a6f ldr r2, [pc, #444] ; (8007658 ) 800749c: f023 0304 bic.w r3, r3, #4 80074a0: 6213 str r3, [r2, #32] 80074a2: e01c b.n 80074de 80074a4: 687b ldr r3, [r7, #4] 80074a6: 691b ldr r3, [r3, #16] 80074a8: 2b05 cmp r3, #5 80074aa: d10c bne.n 80074c6 80074ac: 4b6a ldr r3, [pc, #424] ; (8007658 ) 80074ae: 6a1b ldr r3, [r3, #32] 80074b0: 4a69 ldr r2, [pc, #420] ; (8007658 ) 80074b2: f043 0304 orr.w r3, r3, #4 80074b6: 6213 str r3, [r2, #32] 80074b8: 4b67 ldr r3, [pc, #412] ; (8007658 ) 80074ba: 6a1b ldr r3, [r3, #32] 80074bc: 4a66 ldr r2, [pc, #408] ; (8007658 ) 80074be: f043 0301 orr.w r3, r3, #1 80074c2: 6213 str r3, [r2, #32] 80074c4: e00b b.n 80074de 80074c6: 4b64 ldr r3, [pc, #400] ; (8007658 ) 80074c8: 6a1b ldr r3, [r3, #32] 80074ca: 4a63 ldr r2, [pc, #396] ; (8007658 ) 80074cc: f023 0301 bic.w r3, r3, #1 80074d0: 6213 str r3, [r2, #32] 80074d2: 4b61 ldr r3, [pc, #388] ; (8007658 ) 80074d4: 6a1b ldr r3, [r3, #32] 80074d6: 4a60 ldr r2, [pc, #384] ; (8007658 ) 80074d8: f023 0304 bic.w r3, r3, #4 80074dc: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 80074de: 687b ldr r3, [r7, #4] 80074e0: 691b ldr r3, [r3, #16] 80074e2: 2b00 cmp r3, #0 80074e4: d015 beq.n 8007512 { /* Get Start Tick */ tickstart = HAL_GetTick(); 80074e6: f7fd fe55 bl 8005194 80074ea: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80074ec: e00a b.n 8007504 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80074ee: f7fd fe51 bl 8005194 80074f2: 4602 mov r2, r0 80074f4: 693b ldr r3, [r7, #16] 80074f6: 1ad3 subs r3, r2, r3 80074f8: f241 3288 movw r2, #5000 ; 0x1388 80074fc: 4293 cmp r3, r2 80074fe: d901 bls.n 8007504 { return HAL_TIMEOUT; 8007500: 2303 movs r3, #3 8007502: e143 b.n 800778c while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8007504: 4b54 ldr r3, [pc, #336] ; (8007658 ) 8007506: 6a1b ldr r3, [r3, #32] 8007508: f003 0302 and.w r3, r3, #2 800750c: 2b00 cmp r3, #0 800750e: d0ee beq.n 80074ee 8007510: e014 b.n 800753c } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8007512: f7fd fe3f bl 8005194 8007516: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8007518: e00a b.n 8007530 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800751a: f7fd fe3b bl 8005194 800751e: 4602 mov r2, r0 8007520: 693b ldr r3, [r7, #16] 8007522: 1ad3 subs r3, r2, r3 8007524: f241 3288 movw r2, #5000 ; 0x1388 8007528: 4293 cmp r3, r2 800752a: d901 bls.n 8007530 { return HAL_TIMEOUT; 800752c: 2303 movs r3, #3 800752e: e12d b.n 800778c while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8007530: 4b49 ldr r3, [pc, #292] ; (8007658 ) 8007532: 6a1b ldr r3, [r3, #32] 8007534: f003 0302 and.w r3, r3, #2 8007538: 2b00 cmp r3, #0 800753a: d1ee bne.n 800751a } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 800753c: 7dfb ldrb r3, [r7, #23] 800753e: 2b01 cmp r3, #1 8007540: d105 bne.n 800754e { __HAL_RCC_PWR_CLK_DISABLE(); 8007542: 4b45 ldr r3, [pc, #276] ; (8007658 ) 8007544: 69db ldr r3, [r3, #28] 8007546: 4a44 ldr r2, [pc, #272] ; (8007658 ) 8007548: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 800754c: 61d3 str r3, [r2, #28] #if defined(RCC_CR_PLL2ON) /*-------------------------------- PLL2 Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) 800754e: 687b ldr r3, [r7, #4] 8007550: 6adb ldr r3, [r3, #44] ; 0x2c 8007552: 2b00 cmp r3, #0 8007554: f000 808c beq.w 8007670 { /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 8007558: 4b3f ldr r3, [pc, #252] ; (8007658 ) 800755a: 685b ldr r3, [r3, #4] 800755c: f403 3380 and.w r3, r3, #65536 ; 0x10000 8007560: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8007564: d10e bne.n 8007584 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 8007566: 4b3c ldr r3, [pc, #240] ; (8007658 ) 8007568: 685b ldr r3, [r3, #4] 800756a: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 800756e: 2b08 cmp r3, #8 8007570: d108 bne.n 8007584 ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) 8007572: 4b39 ldr r3, [pc, #228] ; (8007658 ) 8007574: 6adb ldr r3, [r3, #44] ; 0x2c 8007576: f403 3380 and.w r3, r3, #65536 ; 0x10000 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 800757a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800757e: d101 bne.n 8007584 { return HAL_ERROR; 8007580: 2301 movs r3, #1 8007582: e103 b.n 800778c } else { if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) 8007584: 687b ldr r3, [r7, #4] 8007586: 6adb ldr r3, [r3, #44] ; 0x2c 8007588: 2b02 cmp r3, #2 800758a: d14e bne.n 800762a assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); /* Prediv2 can be written only when the PLLI2S is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 800758c: 4b32 ldr r3, [pc, #200] ; (8007658 ) 800758e: 681b ldr r3, [r3, #0] 8007590: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8007594: 2b00 cmp r3, #0 8007596: d009 beq.n 80075ac (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) 8007598: 4b2f ldr r3, [pc, #188] ; (8007658 ) 800759a: 6adb ldr r3, [r3, #44] ; 0x2c 800759c: f003 02f0 and.w r2, r3, #240 ; 0xf0 80075a0: 687b ldr r3, [r7, #4] 80075a2: 6b5b ldr r3, [r3, #52] ; 0x34 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 80075a4: 429a cmp r2, r3 80075a6: d001 beq.n 80075ac { return HAL_ERROR; 80075a8: 2301 movs r3, #1 80075aa: e0ef b.n 800778c } /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 80075ac: 4b2c ldr r3, [pc, #176] ; (8007660 ) 80075ae: 2200 movs r2, #0 80075b0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80075b2: f7fd fdef bl 8005194 80075b6: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 80075b8: e008 b.n 80075cc { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 80075ba: f7fd fdeb bl 8005194 80075be: 4602 mov r2, r0 80075c0: 693b ldr r3, [r7, #16] 80075c2: 1ad3 subs r3, r2, r3 80075c4: 2b64 cmp r3, #100 ; 0x64 80075c6: d901 bls.n 80075cc { return HAL_TIMEOUT; 80075c8: 2303 movs r3, #3 80075ca: e0df b.n 800778c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 80075cc: 4b22 ldr r3, [pc, #136] ; (8007658 ) 80075ce: 681b ldr r3, [r3, #0] 80075d0: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 80075d4: 2b00 cmp r3, #0 80075d6: d1f0 bne.n 80075ba } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); 80075d8: 4b1f ldr r3, [pc, #124] ; (8007658 ) 80075da: 6adb ldr r3, [r3, #44] ; 0x2c 80075dc: f023 02f0 bic.w r2, r3, #240 ; 0xf0 80075e0: 687b ldr r3, [r7, #4] 80075e2: 6b5b ldr r3, [r3, #52] ; 0x34 80075e4: 491c ldr r1, [pc, #112] ; (8007658 ) 80075e6: 4313 orrs r3, r2 80075e8: 62cb str r3, [r1, #44] ; 0x2c /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); 80075ea: 4b1b ldr r3, [pc, #108] ; (8007658 ) 80075ec: 6adb ldr r3, [r3, #44] ; 0x2c 80075ee: f423 6270 bic.w r2, r3, #3840 ; 0xf00 80075f2: 687b ldr r3, [r7, #4] 80075f4: 6b1b ldr r3, [r3, #48] ; 0x30 80075f6: 4918 ldr r1, [pc, #96] ; (8007658 ) 80075f8: 4313 orrs r3, r2 80075fa: 62cb str r3, [r1, #44] ; 0x2c /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); 80075fc: 4b18 ldr r3, [pc, #96] ; (8007660 ) 80075fe: 2201 movs r2, #1 8007600: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8007602: f7fd fdc7 bl 8005194 8007606: 6138 str r0, [r7, #16] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8007608: e008 b.n 800761c { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800760a: f7fd fdc3 bl 8005194 800760e: 4602 mov r2, r0 8007610: 693b ldr r3, [r7, #16] 8007612: 1ad3 subs r3, r2, r3 8007614: 2b64 cmp r3, #100 ; 0x64 8007616: d901 bls.n 800761c { return HAL_TIMEOUT; 8007618: 2303 movs r3, #3 800761a: e0b7 b.n 800778c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 800761c: 4b0e ldr r3, [pc, #56] ; (8007658 ) 800761e: 681b ldr r3, [r3, #0] 8007620: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8007624: 2b00 cmp r3, #0 8007626: d0f0 beq.n 800760a 8007628: e022 b.n 8007670 } } else { /* Set PREDIV1 source to HSE */ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); 800762a: 4b0b ldr r3, [pc, #44] ; (8007658 ) 800762c: 6adb ldr r3, [r3, #44] ; 0x2c 800762e: 4a0a ldr r2, [pc, #40] ; (8007658 ) 8007630: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8007634: 62d3 str r3, [r2, #44] ; 0x2c /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 8007636: 4b0a ldr r3, [pc, #40] ; (8007660 ) 8007638: 2200 movs r2, #0 800763a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800763c: f7fd fdaa bl 8005194 8007640: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8007642: e00f b.n 8007664 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8007644: f7fd fda6 bl 8005194 8007648: 4602 mov r2, r0 800764a: 693b ldr r3, [r7, #16] 800764c: 1ad3 subs r3, r2, r3 800764e: 2b64 cmp r3, #100 ; 0x64 8007650: d908 bls.n 8007664 { return HAL_TIMEOUT; 8007652: 2303 movs r3, #3 8007654: e09a b.n 800778c 8007656: bf00 nop 8007658: 40021000 .word 0x40021000 800765c: 40007000 .word 0x40007000 8007660: 42420068 .word 0x42420068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8007664: 4b4b ldr r3, [pc, #300] ; (8007794 ) 8007666: 681b ldr r3, [r3, #0] 8007668: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 800766c: 2b00 cmp r3, #0 800766e: d1e9 bne.n 8007644 #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8007670: 687b ldr r3, [r7, #4] 8007672: 6a1b ldr r3, [r3, #32] 8007674: 2b00 cmp r3, #0 8007676: f000 8088 beq.w 800778a { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 800767a: 4b46 ldr r3, [pc, #280] ; (8007794 ) 800767c: 685b ldr r3, [r3, #4] 800767e: f003 030c and.w r3, r3, #12 8007682: 2b08 cmp r3, #8 8007684: d068 beq.n 8007758 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8007686: 687b ldr r3, [r7, #4] 8007688: 6a1b ldr r3, [r3, #32] 800768a: 2b02 cmp r3, #2 800768c: d14d bne.n 800772a /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800768e: 4b42 ldr r3, [pc, #264] ; (8007798 ) 8007690: 2200 movs r2, #0 8007692: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8007694: f7fd fd7e bl 8005194 8007698: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800769a: e008 b.n 80076ae { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800769c: f7fd fd7a bl 8005194 80076a0: 4602 mov r2, r0 80076a2: 693b ldr r3, [r7, #16] 80076a4: 1ad3 subs r3, r2, r3 80076a6: 2b02 cmp r3, #2 80076a8: d901 bls.n 80076ae { return HAL_TIMEOUT; 80076aa: 2303 movs r3, #3 80076ac: e06e b.n 800778c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80076ae: 4b39 ldr r3, [pc, #228] ; (8007794 ) 80076b0: 681b ldr r3, [r3, #0] 80076b2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80076b6: 2b00 cmp r3, #0 80076b8: d1f0 bne.n 800769c } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 80076ba: 687b ldr r3, [r7, #4] 80076bc: 6a5b ldr r3, [r3, #36] ; 0x24 80076be: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80076c2: d10f bne.n 80076e4 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); #if defined(RCC_CFGR2_PREDIV1SRC) assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); 80076c4: 4b33 ldr r3, [pc, #204] ; (8007794 ) 80076c6: 6ada ldr r2, [r3, #44] ; 0x2c 80076c8: 687b ldr r3, [r7, #4] 80076ca: 685b ldr r3, [r3, #4] 80076cc: 4931 ldr r1, [pc, #196] ; (8007794 ) 80076ce: 4313 orrs r3, r2 80076d0: 62cb str r3, [r1, #44] ; 0x2c #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 80076d2: 4b30 ldr r3, [pc, #192] ; (8007794 ) 80076d4: 6adb ldr r3, [r3, #44] ; 0x2c 80076d6: f023 020f bic.w r2, r3, #15 80076da: 687b ldr r3, [r7, #4] 80076dc: 68db ldr r3, [r3, #12] 80076de: 492d ldr r1, [pc, #180] ; (8007794 ) 80076e0: 4313 orrs r3, r2 80076e2: 62cb str r3, [r1, #44] ; 0x2c } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80076e4: 4b2b ldr r3, [pc, #172] ; (8007794 ) 80076e6: 685b ldr r3, [r3, #4] 80076e8: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000 80076ec: 687b ldr r3, [r7, #4] 80076ee: 6a59 ldr r1, [r3, #36] ; 0x24 80076f0: 687b ldr r3, [r7, #4] 80076f2: 6a9b ldr r3, [r3, #40] ; 0x28 80076f4: 430b orrs r3, r1 80076f6: 4927 ldr r1, [pc, #156] ; (8007794 ) 80076f8: 4313 orrs r3, r2 80076fa: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 80076fc: 4b26 ldr r3, [pc, #152] ; (8007798 ) 80076fe: 2201 movs r2, #1 8007700: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8007702: f7fd fd47 bl 8005194 8007706: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8007708: e008 b.n 800771c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800770a: f7fd fd43 bl 8005194 800770e: 4602 mov r2, r0 8007710: 693b ldr r3, [r7, #16] 8007712: 1ad3 subs r3, r2, r3 8007714: 2b02 cmp r3, #2 8007716: d901 bls.n 800771c { return HAL_TIMEOUT; 8007718: 2303 movs r3, #3 800771a: e037 b.n 800778c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800771c: 4b1d ldr r3, [pc, #116] ; (8007794 ) 800771e: 681b ldr r3, [r3, #0] 8007720: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8007724: 2b00 cmp r3, #0 8007726: d0f0 beq.n 800770a 8007728: e02f b.n 800778a } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800772a: 4b1b ldr r3, [pc, #108] ; (8007798 ) 800772c: 2200 movs r2, #0 800772e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8007730: f7fd fd30 bl 8005194 8007734: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8007736: e008 b.n 800774a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8007738: f7fd fd2c bl 8005194 800773c: 4602 mov r2, r0 800773e: 693b ldr r3, [r7, #16] 8007740: 1ad3 subs r3, r2, r3 8007742: 2b02 cmp r3, #2 8007744: d901 bls.n 800774a { return HAL_TIMEOUT; 8007746: 2303 movs r3, #3 8007748: e020 b.n 800778c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800774a: 4b12 ldr r3, [pc, #72] ; (8007794 ) 800774c: 681b ldr r3, [r3, #0] 800774e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8007752: 2b00 cmp r3, #0 8007754: d1f0 bne.n 8007738 8007756: e018 b.n 800778a } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8007758: 687b ldr r3, [r7, #4] 800775a: 6a1b ldr r3, [r3, #32] 800775c: 2b01 cmp r3, #1 800775e: d101 bne.n 8007764 { return HAL_ERROR; 8007760: 2301 movs r3, #1 8007762: e013 b.n 800778c } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8007764: 4b0b ldr r3, [pc, #44] ; (8007794 ) 8007766: 685b ldr r3, [r3, #4] 8007768: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800776a: 68fb ldr r3, [r7, #12] 800776c: f403 3280 and.w r2, r3, #65536 ; 0x10000 8007770: 687b ldr r3, [r7, #4] 8007772: 6a5b ldr r3, [r3, #36] ; 0x24 8007774: 429a cmp r2, r3 8007776: d106 bne.n 8007786 (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8007778: 68fb ldr r3, [r7, #12] 800777a: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 800777e: 687b ldr r3, [r7, #4] 8007780: 6a9b ldr r3, [r3, #40] ; 0x28 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8007782: 429a cmp r2, r3 8007784: d001 beq.n 800778a { return HAL_ERROR; 8007786: 2301 movs r3, #1 8007788: e000 b.n 800778c } } } } return HAL_OK; 800778a: 2300 movs r3, #0 } 800778c: 4618 mov r0, r3 800778e: 3718 adds r7, #24 8007790: 46bd mov sp, r7 8007792: bd80 pop {r7, pc} 8007794: 40021000 .word 0x40021000 8007798: 42420060 .word 0x42420060 0800779c : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800779c: b580 push {r7, lr} 800779e: b084 sub sp, #16 80077a0: af00 add r7, sp, #0 80077a2: 6078 str r0, [r7, #4] 80077a4: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 80077a6: 687b ldr r3, [r7, #4] 80077a8: 2b00 cmp r3, #0 80077aa: d101 bne.n 80077b0 { return HAL_ERROR; 80077ac: 2301 movs r3, #1 80077ae: e0d0 b.n 8007952 must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 80077b0: 4b6a ldr r3, [pc, #424] ; (800795c ) 80077b2: 681b ldr r3, [r3, #0] 80077b4: f003 0307 and.w r3, r3, #7 80077b8: 683a ldr r2, [r7, #0] 80077ba: 429a cmp r2, r3 80077bc: d910 bls.n 80077e0 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80077be: 4b67 ldr r3, [pc, #412] ; (800795c ) 80077c0: 681b ldr r3, [r3, #0] 80077c2: f023 0207 bic.w r2, r3, #7 80077c6: 4965 ldr r1, [pc, #404] ; (800795c ) 80077c8: 683b ldr r3, [r7, #0] 80077ca: 4313 orrs r3, r2 80077cc: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80077ce: 4b63 ldr r3, [pc, #396] ; (800795c ) 80077d0: 681b ldr r3, [r3, #0] 80077d2: f003 0307 and.w r3, r3, #7 80077d6: 683a ldr r2, [r7, #0] 80077d8: 429a cmp r2, r3 80077da: d001 beq.n 80077e0 { return HAL_ERROR; 80077dc: 2301 movs r3, #1 80077de: e0b8 b.n 8007952 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 80077e0: 687b ldr r3, [r7, #4] 80077e2: 681b ldr r3, [r3, #0] 80077e4: f003 0302 and.w r3, r3, #2 80077e8: 2b00 cmp r3, #0 80077ea: d020 beq.n 800782e { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80077ec: 687b ldr r3, [r7, #4] 80077ee: 681b ldr r3, [r3, #0] 80077f0: f003 0304 and.w r3, r3, #4 80077f4: 2b00 cmp r3, #0 80077f6: d005 beq.n 8007804 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 80077f8: 4b59 ldr r3, [pc, #356] ; (8007960 ) 80077fa: 685b ldr r3, [r3, #4] 80077fc: 4a58 ldr r2, [pc, #352] ; (8007960 ) 80077fe: f443 63e0 orr.w r3, r3, #1792 ; 0x700 8007802: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8007804: 687b ldr r3, [r7, #4] 8007806: 681b ldr r3, [r3, #0] 8007808: f003 0308 and.w r3, r3, #8 800780c: 2b00 cmp r3, #0 800780e: d005 beq.n 800781c { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8007810: 4b53 ldr r3, [pc, #332] ; (8007960 ) 8007812: 685b ldr r3, [r3, #4] 8007814: 4a52 ldr r2, [pc, #328] ; (8007960 ) 8007816: f443 5360 orr.w r3, r3, #14336 ; 0x3800 800781a: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800781c: 4b50 ldr r3, [pc, #320] ; (8007960 ) 800781e: 685b ldr r3, [r3, #4] 8007820: f023 02f0 bic.w r2, r3, #240 ; 0xf0 8007824: 687b ldr r3, [r7, #4] 8007826: 689b ldr r3, [r3, #8] 8007828: 494d ldr r1, [pc, #308] ; (8007960 ) 800782a: 4313 orrs r3, r2 800782c: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800782e: 687b ldr r3, [r7, #4] 8007830: 681b ldr r3, [r3, #0] 8007832: f003 0301 and.w r3, r3, #1 8007836: 2b00 cmp r3, #0 8007838: d040 beq.n 80078bc { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800783a: 687b ldr r3, [r7, #4] 800783c: 685b ldr r3, [r3, #4] 800783e: 2b01 cmp r3, #1 8007840: d107 bne.n 8007852 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8007842: 4b47 ldr r3, [pc, #284] ; (8007960 ) 8007844: 681b ldr r3, [r3, #0] 8007846: f403 3300 and.w r3, r3, #131072 ; 0x20000 800784a: 2b00 cmp r3, #0 800784c: d115 bne.n 800787a { return HAL_ERROR; 800784e: 2301 movs r3, #1 8007850: e07f b.n 8007952 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8007852: 687b ldr r3, [r7, #4] 8007854: 685b ldr r3, [r3, #4] 8007856: 2b02 cmp r3, #2 8007858: d107 bne.n 800786a { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800785a: 4b41 ldr r3, [pc, #260] ; (8007960 ) 800785c: 681b ldr r3, [r3, #0] 800785e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8007862: 2b00 cmp r3, #0 8007864: d109 bne.n 800787a { return HAL_ERROR; 8007866: 2301 movs r3, #1 8007868: e073 b.n 8007952 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800786a: 4b3d ldr r3, [pc, #244] ; (8007960 ) 800786c: 681b ldr r3, [r3, #0] 800786e: f003 0302 and.w r3, r3, #2 8007872: 2b00 cmp r3, #0 8007874: d101 bne.n 800787a { return HAL_ERROR; 8007876: 2301 movs r3, #1 8007878: e06b b.n 8007952 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 800787a: 4b39 ldr r3, [pc, #228] ; (8007960 ) 800787c: 685b ldr r3, [r3, #4] 800787e: f023 0203 bic.w r2, r3, #3 8007882: 687b ldr r3, [r7, #4] 8007884: 685b ldr r3, [r3, #4] 8007886: 4936 ldr r1, [pc, #216] ; (8007960 ) 8007888: 4313 orrs r3, r2 800788a: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 800788c: f7fd fc82 bl 8005194 8007890: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8007892: e00a b.n 80078aa { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8007894: f7fd fc7e bl 8005194 8007898: 4602 mov r2, r0 800789a: 68fb ldr r3, [r7, #12] 800789c: 1ad3 subs r3, r2, r3 800789e: f241 3288 movw r2, #5000 ; 0x1388 80078a2: 4293 cmp r3, r2 80078a4: d901 bls.n 80078aa { return HAL_TIMEOUT; 80078a6: 2303 movs r3, #3 80078a8: e053 b.n 8007952 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80078aa: 4b2d ldr r3, [pc, #180] ; (8007960 ) 80078ac: 685b ldr r3, [r3, #4] 80078ae: f003 020c and.w r2, r3, #12 80078b2: 687b ldr r3, [r7, #4] 80078b4: 685b ldr r3, [r3, #4] 80078b6: 009b lsls r3, r3, #2 80078b8: 429a cmp r2, r3 80078ba: d1eb bne.n 8007894 } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 80078bc: 4b27 ldr r3, [pc, #156] ; (800795c ) 80078be: 681b ldr r3, [r3, #0] 80078c0: f003 0307 and.w r3, r3, #7 80078c4: 683a ldr r2, [r7, #0] 80078c6: 429a cmp r2, r3 80078c8: d210 bcs.n 80078ec { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80078ca: 4b24 ldr r3, [pc, #144] ; (800795c ) 80078cc: 681b ldr r3, [r3, #0] 80078ce: f023 0207 bic.w r2, r3, #7 80078d2: 4922 ldr r1, [pc, #136] ; (800795c ) 80078d4: 683b ldr r3, [r7, #0] 80078d6: 4313 orrs r3, r2 80078d8: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80078da: 4b20 ldr r3, [pc, #128] ; (800795c ) 80078dc: 681b ldr r3, [r3, #0] 80078de: f003 0307 and.w r3, r3, #7 80078e2: 683a ldr r2, [r7, #0] 80078e4: 429a cmp r2, r3 80078e6: d001 beq.n 80078ec { return HAL_ERROR; 80078e8: 2301 movs r3, #1 80078ea: e032 b.n 8007952 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80078ec: 687b ldr r3, [r7, #4] 80078ee: 681b ldr r3, [r3, #0] 80078f0: f003 0304 and.w r3, r3, #4 80078f4: 2b00 cmp r3, #0 80078f6: d008 beq.n 800790a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 80078f8: 4b19 ldr r3, [pc, #100] ; (8007960 ) 80078fa: 685b ldr r3, [r3, #4] 80078fc: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8007900: 687b ldr r3, [r7, #4] 8007902: 68db ldr r3, [r3, #12] 8007904: 4916 ldr r1, [pc, #88] ; (8007960 ) 8007906: 4313 orrs r3, r2 8007908: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800790a: 687b ldr r3, [r7, #4] 800790c: 681b ldr r3, [r3, #0] 800790e: f003 0308 and.w r3, r3, #8 8007912: 2b00 cmp r3, #0 8007914: d009 beq.n 800792a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 8007916: 4b12 ldr r3, [pc, #72] ; (8007960 ) 8007918: 685b ldr r3, [r3, #4] 800791a: f423 5260 bic.w r2, r3, #14336 ; 0x3800 800791e: 687b ldr r3, [r7, #4] 8007920: 691b ldr r3, [r3, #16] 8007922: 00db lsls r3, r3, #3 8007924: 490e ldr r1, [pc, #56] ; (8007960 ) 8007926: 4313 orrs r3, r2 8007928: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 800792a: f000 f821 bl 8007970 800792e: 4602 mov r2, r0 8007930: 4b0b ldr r3, [pc, #44] ; (8007960 ) 8007932: 685b ldr r3, [r3, #4] 8007934: 091b lsrs r3, r3, #4 8007936: f003 030f and.w r3, r3, #15 800793a: 490a ldr r1, [pc, #40] ; (8007964 ) 800793c: 5ccb ldrb r3, [r1, r3] 800793e: fa22 f303 lsr.w r3, r2, r3 8007942: 4a09 ldr r2, [pc, #36] ; (8007968 ) 8007944: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 8007946: 4b09 ldr r3, [pc, #36] ; (800796c ) 8007948: 681b ldr r3, [r3, #0] 800794a: 4618 mov r0, r3 800794c: f7fd fbe0 bl 8005110 return HAL_OK; 8007950: 2300 movs r3, #0 } 8007952: 4618 mov r0, r3 8007954: 3710 adds r7, #16 8007956: 46bd mov sp, r7 8007958: bd80 pop {r7, pc} 800795a: bf00 nop 800795c: 40022000 .word 0x40022000 8007960: 40021000 .word 0x40021000 8007964: 0800d294 .word 0x0800d294 8007968: 20000008 .word 0x20000008 800796c: 2000000c .word 0x2000000c 08007970 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8007970: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8007974: b099 sub sp, #100 ; 0x64 8007976: af00 add r7, sp, #0 #if defined(RCC_CFGR2_PREDIV1SRC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; 8007978: 4b66 ldr r3, [pc, #408] ; (8007b14 ) 800797a: f107 0434 add.w r4, r7, #52 ; 0x34 800797e: cb0f ldmia r3, {r0, r1, r2, r3} 8007980: c407 stmia r4!, {r0, r1, r2} 8007982: 8023 strh r3, [r4, #0] const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; 8007984: 4b64 ldr r3, [pc, #400] ; (8007b18 ) 8007986: f107 0424 add.w r4, r7, #36 ; 0x24 800798a: cb0f ldmia r3, {r0, r1, r2, r3} 800798c: e884 000f stmia.w r4, {r0, r1, r2, r3} #else const uint8_t aPredivFactorTable[2] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8007990: 2300 movs r3, #0 8007992: 657b str r3, [r7, #84] ; 0x54 8007994: 2300 movs r3, #0 8007996: 653b str r3, [r7, #80] ; 0x50 8007998: 2300 movs r3, #0 800799a: 65fb str r3, [r7, #92] ; 0x5c 800799c: 2300 movs r3, #0 800799e: 64fb str r3, [r7, #76] ; 0x4c uint32_t sysclockfreq = 0U; 80079a0: 2300 movs r3, #0 80079a2: 65bb str r3, [r7, #88] ; 0x58 #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; 80079a4: 2300 movs r3, #0 80079a6: 64bb str r3, [r7, #72] ; 0x48 80079a8: 2300 movs r3, #0 80079aa: 647b str r3, [r7, #68] ; 0x44 #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 80079ac: 4b5b ldr r3, [pc, #364] ; (8007b1c ) 80079ae: 685b ldr r3, [r3, #4] 80079b0: 657b str r3, [r7, #84] ; 0x54 /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 80079b2: 6d7b ldr r3, [r7, #84] ; 0x54 80079b4: f003 030c and.w r3, r3, #12 80079b8: 2b04 cmp r3, #4 80079ba: d002 beq.n 80079c2 80079bc: 2b08 cmp r3, #8 80079be: d003 beq.n 80079c8 80079c0: e09f b.n 8007b02 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 80079c2: 4b57 ldr r3, [pc, #348] ; (8007b20 ) 80079c4: 65bb str r3, [r7, #88] ; 0x58 break; 80079c6: e09f b.n 8007b08 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 80079c8: 6d7b ldr r3, [r7, #84] ; 0x54 80079ca: 0c9b lsrs r3, r3, #18 80079cc: f003 030f and.w r3, r3, #15 80079d0: 3340 adds r3, #64 ; 0x40 80079d2: f107 0220 add.w r2, r7, #32 80079d6: 4413 add r3, r2 80079d8: f813 3c2c ldrb.w r3, [r3, #-44] 80079dc: 64fb str r3, [r7, #76] ; 0x4c if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 80079de: 6d7b ldr r3, [r7, #84] ; 0x54 80079e0: f403 3380 and.w r3, r3, #65536 ; 0x10000 80079e4: 2b00 cmp r3, #0 80079e6: f000 8084 beq.w 8007af2 { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 80079ea: 4b4c ldr r3, [pc, #304] ; (8007b1c ) 80079ec: 6adb ldr r3, [r3, #44] ; 0x2c 80079ee: f003 030f and.w r3, r3, #15 80079f2: 3340 adds r3, #64 ; 0x40 80079f4: f107 0220 add.w r2, r7, #32 80079f8: 4413 add r3, r2 80079fa: f813 3c3c ldrb.w r3, [r3, #-60] 80079fe: 653b str r3, [r7, #80] ; 0x50 #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /*RCC_CFGR2_PREDIV1*/ #if defined(RCC_CFGR2_PREDIV1SRC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 8007a00: 4b46 ldr r3, [pc, #280] ; (8007b1c ) 8007a02: 6adb ldr r3, [r3, #44] ; 0x2c 8007a04: f403 3380 and.w r3, r3, #65536 ; 0x10000 8007a08: 2b00 cmp r3, #0 8007a0a: d060 beq.n 8007ace { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8007a0c: 4b43 ldr r3, [pc, #268] ; (8007b1c ) 8007a0e: 6adb ldr r3, [r3, #44] ; 0x2c 8007a10: 091b lsrs r3, r3, #4 8007a12: f003 030f and.w r3, r3, #15 8007a16: 3301 adds r3, #1 8007a18: 64bb str r3, [r7, #72] ; 0x48 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 8007a1a: 4b40 ldr r3, [pc, #256] ; (8007b1c ) 8007a1c: 6adb ldr r3, [r3, #44] ; 0x2c 8007a1e: 0a1b lsrs r3, r3, #8 8007a20: f003 030f and.w r3, r3, #15 8007a24: 3302 adds r3, #2 8007a26: 647b str r3, [r7, #68] ; 0x44 pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); 8007a28: 6c7b ldr r3, [r7, #68] ; 0x44 8007a2a: 2200 movs r2, #0 8007a2c: 613b str r3, [r7, #16] 8007a2e: 617a str r2, [r7, #20] 8007a30: 6cfb ldr r3, [r7, #76] ; 0x4c 8007a32: 2200 movs r2, #0 8007a34: 61bb str r3, [r7, #24] 8007a36: 61fa str r2, [r7, #28] 8007a38: e9d7 3404 ldrd r3, r4, [r7, #16] 8007a3c: 4622 mov r2, r4 8007a3e: e9d7 0106 ldrd r0, r1, [r7, #24] 8007a42: 4684 mov ip, r0 8007a44: fb0c f202 mul.w r2, ip, r2 8007a48: e9c7 0106 strd r0, r1, [r7, #24] 8007a4c: 468c mov ip, r1 8007a4e: 4618 mov r0, r3 8007a50: 4621 mov r1, r4 8007a52: 4603 mov r3, r0 8007a54: fb03 f30c mul.w r3, r3, ip 8007a58: 4413 add r3, r2 8007a5a: 4602 mov r2, r0 8007a5c: 69b9 ldr r1, [r7, #24] 8007a5e: fba2 8901 umull r8, r9, r2, r1 8007a62: 444b add r3, r9 8007a64: 4699 mov r9, r3 8007a66: 4b2e ldr r3, [pc, #184] ; (8007b20 ) 8007a68: fb03 f209 mul.w r2, r3, r9 8007a6c: 2300 movs r3, #0 8007a6e: fb03 f308 mul.w r3, r3, r8 8007a72: 4413 add r3, r2 8007a74: 4a2a ldr r2, [pc, #168] ; (8007b20 ) 8007a76: fba8 ab02 umull sl, fp, r8, r2 8007a7a: 445b add r3, fp 8007a7c: 469b mov fp, r3 8007a7e: 6cbb ldr r3, [r7, #72] ; 0x48 8007a80: 2200 movs r2, #0 8007a82: 60bb str r3, [r7, #8] 8007a84: 60fa str r2, [r7, #12] 8007a86: 6d3b ldr r3, [r7, #80] ; 0x50 8007a88: 2200 movs r2, #0 8007a8a: 603b str r3, [r7, #0] 8007a8c: 607a str r2, [r7, #4] 8007a8e: e9d7 3402 ldrd r3, r4, [r7, #8] 8007a92: 4622 mov r2, r4 8007a94: e9d7 8900 ldrd r8, r9, [r7] 8007a98: 4641 mov r1, r8 8007a9a: fb01 f202 mul.w r2, r1, r2 8007a9e: 46cc mov ip, r9 8007aa0: 4618 mov r0, r3 8007aa2: 4621 mov r1, r4 8007aa4: 4603 mov r3, r0 8007aa6: fb03 f30c mul.w r3, r3, ip 8007aaa: 4413 add r3, r2 8007aac: 4602 mov r2, r0 8007aae: 4641 mov r1, r8 8007ab0: fba2 5601 umull r5, r6, r2, r1 8007ab4: 4433 add r3, r6 8007ab6: 461e mov r6, r3 8007ab8: 462a mov r2, r5 8007aba: 4633 mov r3, r6 8007abc: 4650 mov r0, sl 8007abe: 4659 mov r1, fp 8007ac0: f7f9 fbf2 bl 80012a8 <__aeabi_uldivmod> 8007ac4: 4602 mov r2, r0 8007ac6: 460b mov r3, r1 8007ac8: 4613 mov r3, r2 8007aca: 65fb str r3, [r7, #92] ; 0x5c 8007acc: e007 b.n 8007ade } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8007ace: 6cfb ldr r3, [r7, #76] ; 0x4c 8007ad0: 4a13 ldr r2, [pc, #76] ; (8007b20 ) 8007ad2: fb03 f202 mul.w r2, r3, r2 8007ad6: 6d3b ldr r3, [r7, #80] ; 0x50 8007ad8: fbb2 f3f3 udiv r3, r2, r3 8007adc: 65fb str r3, [r7, #92] ; 0x5c } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 8007ade: f897 3041 ldrb.w r3, [r7, #65] ; 0x41 8007ae2: 461a mov r2, r3 8007ae4: 6cfb ldr r3, [r7, #76] ; 0x4c 8007ae6: 4293 cmp r3, r2 8007ae8: d108 bne.n 8007afc { pllclk = pllclk / 2; 8007aea: 6dfb ldr r3, [r7, #92] ; 0x5c 8007aec: 085b lsrs r3, r3, #1 8007aee: 65fb str r3, [r7, #92] ; 0x5c 8007af0: e004 b.n 8007afc #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8007af2: 6cfb ldr r3, [r7, #76] ; 0x4c 8007af4: 4a0b ldr r2, [pc, #44] ; (8007b24 ) 8007af6: fb02 f303 mul.w r3, r2, r3 8007afa: 65fb str r3, [r7, #92] ; 0x5c } sysclockfreq = pllclk; 8007afc: 6dfb ldr r3, [r7, #92] ; 0x5c 8007afe: 65bb str r3, [r7, #88] ; 0x58 break; 8007b00: e002 b.n 8007b08 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8007b02: 4b09 ldr r3, [pc, #36] ; (8007b28 ) 8007b04: 65bb str r3, [r7, #88] ; 0x58 break; 8007b06: bf00 nop } } return sysclockfreq; 8007b08: 6dbb ldr r3, [r7, #88] ; 0x58 } 8007b0a: 4618 mov r0, r3 8007b0c: 3764 adds r7, #100 ; 0x64 8007b0e: 46bd mov sp, r7 8007b10: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8007b14: 0800d248 .word 0x0800d248 8007b18: 0800d258 .word 0x0800d258 8007b1c: 40021000 .word 0x40021000 8007b20: 017d7840 .word 0x017d7840 8007b24: 003d0900 .word 0x003d0900 8007b28: 007a1200 .word 0x007a1200 08007b2c : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8007b2c: b480 push {r7} 8007b2e: af00 add r7, sp, #0 return SystemCoreClock; 8007b30: 4b02 ldr r3, [pc, #8] ; (8007b3c ) 8007b32: 681b ldr r3, [r3, #0] } 8007b34: 4618 mov r0, r3 8007b36: 46bd mov sp, r7 8007b38: bc80 pop {r7} 8007b3a: 4770 bx lr 8007b3c: 20000008 .word 0x20000008 08007b40 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8007b40: b580 push {r7, lr} 8007b42: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8007b44: f7ff fff2 bl 8007b2c 8007b48: 4602 mov r2, r0 8007b4a: 4b05 ldr r3, [pc, #20] ; (8007b60 ) 8007b4c: 685b ldr r3, [r3, #4] 8007b4e: 0a1b lsrs r3, r3, #8 8007b50: f003 0307 and.w r3, r3, #7 8007b54: 4903 ldr r1, [pc, #12] ; (8007b64 ) 8007b56: 5ccb ldrb r3, [r1, r3] 8007b58: fa22 f303 lsr.w r3, r2, r3 } 8007b5c: 4618 mov r0, r3 8007b5e: bd80 pop {r7, pc} 8007b60: 40021000 .word 0x40021000 8007b64: 0800d2a4 .word 0x0800d2a4 08007b68 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8007b68: b580 push {r7, lr} 8007b6a: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8007b6c: f7ff ffde bl 8007b2c 8007b70: 4602 mov r2, r0 8007b72: 4b05 ldr r3, [pc, #20] ; (8007b88 ) 8007b74: 685b ldr r3, [r3, #4] 8007b76: 0adb lsrs r3, r3, #11 8007b78: f003 0307 and.w r3, r3, #7 8007b7c: 4903 ldr r1, [pc, #12] ; (8007b8c ) 8007b7e: 5ccb ldrb r3, [r1, r3] 8007b80: fa22 f303 lsr.w r3, r2, r3 } 8007b84: 4618 mov r0, r3 8007b86: bd80 pop {r7, pc} 8007b88: 40021000 .word 0x40021000 8007b8c: 0800d2a4 .word 0x0800d2a4 08007b90 : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8007b90: b480 push {r7} 8007b92: b085 sub sp, #20 8007b94: af00 add r7, sp, #0 8007b96: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8007b98: 4b0a ldr r3, [pc, #40] ; (8007bc4 ) 8007b9a: 681b ldr r3, [r3, #0] 8007b9c: 4a0a ldr r2, [pc, #40] ; (8007bc8 ) 8007b9e: fba2 2303 umull r2, r3, r2, r3 8007ba2: 0a5b lsrs r3, r3, #9 8007ba4: 687a ldr r2, [r7, #4] 8007ba6: fb02 f303 mul.w r3, r2, r3 8007baa: 60fb str r3, [r7, #12] do { __NOP(); 8007bac: bf00 nop } while (Delay --); 8007bae: 68fb ldr r3, [r7, #12] 8007bb0: 1e5a subs r2, r3, #1 8007bb2: 60fa str r2, [r7, #12] 8007bb4: 2b00 cmp r3, #0 8007bb6: d1f9 bne.n 8007bac } 8007bb8: bf00 nop 8007bba: bf00 nop 8007bbc: 3714 adds r7, #20 8007bbe: 46bd mov sp, r7 8007bc0: bc80 pop {r7} 8007bc2: 4770 bx lr 8007bc4: 20000008 .word 0x20000008 8007bc8: 10624dd3 .word 0x10624dd3 08007bcc : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8007bcc: b580 push {r7, lr} 8007bce: b088 sub sp, #32 8007bd0: af00 add r7, sp, #0 8007bd2: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 8007bd4: 2300 movs r3, #0 8007bd6: 617b str r3, [r7, #20] 8007bd8: 2300 movs r3, #0 8007bda: 613b str r3, [r7, #16] #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t pllactive = 0U; 8007bdc: 2300 movs r3, #0 8007bde: 61fb str r3, [r7, #28] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 8007be0: 687b ldr r3, [r7, #4] 8007be2: 681b ldr r3, [r3, #0] 8007be4: f003 0301 and.w r3, r3, #1 8007be8: 2b00 cmp r3, #0 8007bea: d07d beq.n 8007ce8 { FlagStatus pwrclkchanged = RESET; 8007bec: 2300 movs r3, #0 8007bee: 76fb strb r3, [r7, #27] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8007bf0: 4b8b ldr r3, [pc, #556] ; (8007e20 ) 8007bf2: 69db ldr r3, [r3, #28] 8007bf4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8007bf8: 2b00 cmp r3, #0 8007bfa: d10d bne.n 8007c18 { __HAL_RCC_PWR_CLK_ENABLE(); 8007bfc: 4b88 ldr r3, [pc, #544] ; (8007e20 ) 8007bfe: 69db ldr r3, [r3, #28] 8007c00: 4a87 ldr r2, [pc, #540] ; (8007e20 ) 8007c02: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8007c06: 61d3 str r3, [r2, #28] 8007c08: 4b85 ldr r3, [pc, #532] ; (8007e20 ) 8007c0a: 69db ldr r3, [r3, #28] 8007c0c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8007c10: 60fb str r3, [r7, #12] 8007c12: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8007c14: 2301 movs r3, #1 8007c16: 76fb strb r3, [r7, #27] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8007c18: 4b82 ldr r3, [pc, #520] ; (8007e24 ) 8007c1a: 681b ldr r3, [r3, #0] 8007c1c: f403 7380 and.w r3, r3, #256 ; 0x100 8007c20: 2b00 cmp r3, #0 8007c22: d118 bne.n 8007c56 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8007c24: 4b7f ldr r3, [pc, #508] ; (8007e24 ) 8007c26: 681b ldr r3, [r3, #0] 8007c28: 4a7e ldr r2, [pc, #504] ; (8007e24 ) 8007c2a: f443 7380 orr.w r3, r3, #256 ; 0x100 8007c2e: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8007c30: f7fd fab0 bl 8005194 8007c34: 6178 str r0, [r7, #20] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8007c36: e008 b.n 8007c4a { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8007c38: f7fd faac bl 8005194 8007c3c: 4602 mov r2, r0 8007c3e: 697b ldr r3, [r7, #20] 8007c40: 1ad3 subs r3, r2, r3 8007c42: 2b64 cmp r3, #100 ; 0x64 8007c44: d901 bls.n 8007c4a { return HAL_TIMEOUT; 8007c46: 2303 movs r3, #3 8007c48: e0e5 b.n 8007e16 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8007c4a: 4b76 ldr r3, [pc, #472] ; (8007e24 ) 8007c4c: 681b ldr r3, [r3, #0] 8007c4e: f403 7380 and.w r3, r3, #256 ; 0x100 8007c52: 2b00 cmp r3, #0 8007c54: d0f0 beq.n 8007c38 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 8007c56: 4b72 ldr r3, [pc, #456] ; (8007e20 ) 8007c58: 6a1b ldr r3, [r3, #32] 8007c5a: f403 7340 and.w r3, r3, #768 ; 0x300 8007c5e: 613b str r3, [r7, #16] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8007c60: 693b ldr r3, [r7, #16] 8007c62: 2b00 cmp r3, #0 8007c64: d02e beq.n 8007cc4 8007c66: 687b ldr r3, [r7, #4] 8007c68: 685b ldr r3, [r3, #4] 8007c6a: f403 7340 and.w r3, r3, #768 ; 0x300 8007c6e: 693a ldr r2, [r7, #16] 8007c70: 429a cmp r2, r3 8007c72: d027 beq.n 8007cc4 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8007c74: 4b6a ldr r3, [pc, #424] ; (8007e20 ) 8007c76: 6a1b ldr r3, [r3, #32] 8007c78: f423 7340 bic.w r3, r3, #768 ; 0x300 8007c7c: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8007c7e: 4b6a ldr r3, [pc, #424] ; (8007e28 ) 8007c80: 2201 movs r2, #1 8007c82: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8007c84: 4b68 ldr r3, [pc, #416] ; (8007e28 ) 8007c86: 2200 movs r2, #0 8007c88: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 8007c8a: 4a65 ldr r2, [pc, #404] ; (8007e20 ) 8007c8c: 693b ldr r3, [r7, #16] 8007c8e: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8007c90: 693b ldr r3, [r7, #16] 8007c92: f003 0301 and.w r3, r3, #1 8007c96: 2b00 cmp r3, #0 8007c98: d014 beq.n 8007cc4 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8007c9a: f7fd fa7b bl 8005194 8007c9e: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8007ca0: e00a b.n 8007cb8 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8007ca2: f7fd fa77 bl 8005194 8007ca6: 4602 mov r2, r0 8007ca8: 697b ldr r3, [r7, #20] 8007caa: 1ad3 subs r3, r2, r3 8007cac: f241 3288 movw r2, #5000 ; 0x1388 8007cb0: 4293 cmp r3, r2 8007cb2: d901 bls.n 8007cb8 { return HAL_TIMEOUT; 8007cb4: 2303 movs r3, #3 8007cb6: e0ae b.n 8007e16 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8007cb8: 4b59 ldr r3, [pc, #356] ; (8007e20 ) 8007cba: 6a1b ldr r3, [r3, #32] 8007cbc: f003 0302 and.w r3, r3, #2 8007cc0: 2b00 cmp r3, #0 8007cc2: d0ee beq.n 8007ca2 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8007cc4: 4b56 ldr r3, [pc, #344] ; (8007e20 ) 8007cc6: 6a1b ldr r3, [r3, #32] 8007cc8: f423 7240 bic.w r2, r3, #768 ; 0x300 8007ccc: 687b ldr r3, [r7, #4] 8007cce: 685b ldr r3, [r3, #4] 8007cd0: 4953 ldr r1, [pc, #332] ; (8007e20 ) 8007cd2: 4313 orrs r3, r2 8007cd4: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8007cd6: 7efb ldrb r3, [r7, #27] 8007cd8: 2b01 cmp r3, #1 8007cda: d105 bne.n 8007ce8 { __HAL_RCC_PWR_CLK_DISABLE(); 8007cdc: 4b50 ldr r3, [pc, #320] ; (8007e20 ) 8007cde: 69db ldr r3, [r3, #28] 8007ce0: 4a4f ldr r2, [pc, #316] ; (8007e20 ) 8007ce2: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8007ce6: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8007ce8: 687b ldr r3, [r7, #4] 8007cea: 681b ldr r3, [r3, #0] 8007cec: f003 0302 and.w r3, r3, #2 8007cf0: 2b00 cmp r3, #0 8007cf2: d008 beq.n 8007d06 { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8007cf4: 4b4a ldr r3, [pc, #296] ; (8007e20 ) 8007cf6: 685b ldr r3, [r3, #4] 8007cf8: f423 4240 bic.w r2, r3, #49152 ; 0xc000 8007cfc: 687b ldr r3, [r7, #4] 8007cfe: 689b ldr r3, [r3, #8] 8007d00: 4947 ldr r1, [pc, #284] ; (8007e20 ) 8007d02: 4313 orrs r3, r2 8007d04: 604b str r3, [r1, #4] } #if defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ I2S2 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) 8007d06: 687b ldr r3, [r7, #4] 8007d08: 681b ldr r3, [r3, #0] 8007d0a: f003 0304 and.w r3, r3, #4 8007d0e: 2b00 cmp r3, #0 8007d10: d008 beq.n 8007d24 { /* Check the parameters */ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); /* Configure the I2S2 clock source */ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); 8007d12: 4b43 ldr r3, [pc, #268] ; (8007e20 ) 8007d14: 6adb ldr r3, [r3, #44] ; 0x2c 8007d16: f423 3200 bic.w r2, r3, #131072 ; 0x20000 8007d1a: 687b ldr r3, [r7, #4] 8007d1c: 68db ldr r3, [r3, #12] 8007d1e: 4940 ldr r1, [pc, #256] ; (8007e20 ) 8007d20: 4313 orrs r3, r2 8007d22: 62cb str r3, [r1, #44] ; 0x2c } /*------------------------------ I2S3 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) 8007d24: 687b ldr r3, [r7, #4] 8007d26: 681b ldr r3, [r3, #0] 8007d28: f003 0308 and.w r3, r3, #8 8007d2c: 2b00 cmp r3, #0 8007d2e: d008 beq.n 8007d42 { /* Check the parameters */ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); /* Configure the I2S3 clock source */ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); 8007d30: 4b3b ldr r3, [pc, #236] ; (8007e20 ) 8007d32: 6adb ldr r3, [r3, #44] ; 0x2c 8007d34: f423 2280 bic.w r2, r3, #262144 ; 0x40000 8007d38: 687b ldr r3, [r7, #4] 8007d3a: 691b ldr r3, [r3, #16] 8007d3c: 4938 ldr r1, [pc, #224] ; (8007e20 ) 8007d3e: 4313 orrs r3, r2 8007d40: 62cb str r3, [r1, #44] ; 0x2c } /*------------------------------ PLL I2S Configuration ----------------------*/ /* Check that PLLI2S need to be enabled */ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) 8007d42: 4b37 ldr r3, [pc, #220] ; (8007e20 ) 8007d44: 6adb ldr r3, [r3, #44] ; 0x2c 8007d46: f403 3300 and.w r3, r3, #131072 ; 0x20000 8007d4a: 2b00 cmp r3, #0 8007d4c: d105 bne.n 8007d5a 8007d4e: 4b34 ldr r3, [pc, #208] ; (8007e20 ) 8007d50: 6adb ldr r3, [r3, #44] ; 0x2c 8007d52: f403 2380 and.w r3, r3, #262144 ; 0x40000 8007d56: 2b00 cmp r3, #0 8007d58: d001 beq.n 8007d5e { /* Update flag to indicate that PLL I2S should be active */ pllactive = 1; 8007d5a: 2301 movs r3, #1 8007d5c: 61fb str r3, [r7, #28] } /* Check if PLL I2S need to be enabled */ if (pllactive == 1) 8007d5e: 69fb ldr r3, [r7, #28] 8007d60: 2b01 cmp r3, #1 8007d62: d148 bne.n 8007df6 { /* Enable PLL I2S only if not active */ if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) 8007d64: 4b2e ldr r3, [pc, #184] ; (8007e20 ) 8007d66: 681b ldr r3, [r3, #0] 8007d68: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8007d6c: 2b00 cmp r3, #0 8007d6e: d138 bne.n 8007de2 assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); /* Prediv2 can be written only when the PLL2 is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 8007d70: 4b2b ldr r3, [pc, #172] ; (8007e20 ) 8007d72: 681b ldr r3, [r3, #0] 8007d74: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 8007d78: 2b00 cmp r3, #0 8007d7a: d009 beq.n 8007d90 (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) 8007d7c: 4b28 ldr r3, [pc, #160] ; (8007e20 ) 8007d7e: 6adb ldr r3, [r3, #44] ; 0x2c 8007d80: f003 02f0 and.w r2, r3, #240 ; 0xf0 8007d84: 687b ldr r3, [r7, #4] 8007d86: 699b ldr r3, [r3, #24] if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 8007d88: 429a cmp r2, r3 8007d8a: d001 beq.n 8007d90 { return HAL_ERROR; 8007d8c: 2301 movs r3, #1 8007d8e: e042 b.n 8007e16 } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); 8007d90: 4b23 ldr r3, [pc, #140] ; (8007e20 ) 8007d92: 6adb ldr r3, [r3, #44] ; 0x2c 8007d94: f023 02f0 bic.w r2, r3, #240 ; 0xf0 8007d98: 687b ldr r3, [r7, #4] 8007d9a: 699b ldr r3, [r3, #24] 8007d9c: 4920 ldr r1, [pc, #128] ; (8007e20 ) 8007d9e: 4313 orrs r3, r2 8007da0: 62cb str r3, [r1, #44] ; 0x2c /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); 8007da2: 4b1f ldr r3, [pc, #124] ; (8007e20 ) 8007da4: 6adb ldr r3, [r3, #44] ; 0x2c 8007da6: f423 4270 bic.w r2, r3, #61440 ; 0xf000 8007daa: 687b ldr r3, [r7, #4] 8007dac: 695b ldr r3, [r3, #20] 8007dae: 491c ldr r1, [pc, #112] ; (8007e20 ) 8007db0: 4313 orrs r3, r2 8007db2: 62cb str r3, [r1, #44] ; 0x2c /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); 8007db4: 4b1d ldr r3, [pc, #116] ; (8007e2c ) 8007db6: 2201 movs r2, #1 8007db8: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007dba: f7fd f9eb bl 8005194 8007dbe: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8007dc0: e008 b.n 8007dd4 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8007dc2: f7fd f9e7 bl 8005194 8007dc6: 4602 mov r2, r0 8007dc8: 697b ldr r3, [r7, #20] 8007dca: 1ad3 subs r3, r2, r3 8007dcc: 2b64 cmp r3, #100 ; 0x64 8007dce: d901 bls.n 8007dd4 { return HAL_TIMEOUT; 8007dd0: 2303 movs r3, #3 8007dd2: e020 b.n 8007e16 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8007dd4: 4b12 ldr r3, [pc, #72] ; (8007e20 ) 8007dd6: 681b ldr r3, [r3, #0] 8007dd8: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8007ddc: 2b00 cmp r3, #0 8007dde: d0f0 beq.n 8007dc2 8007de0: e009 b.n 8007df6 } } else { /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) 8007de2: 4b0f ldr r3, [pc, #60] ; (8007e20 ) 8007de4: 6adb ldr r3, [r3, #44] ; 0x2c 8007de6: f403 4270 and.w r2, r3, #61440 ; 0xf000 8007dea: 687b ldr r3, [r7, #4] 8007dec: 695b ldr r3, [r3, #20] 8007dee: 429a cmp r2, r3 8007df0: d001 beq.n 8007df6 { return HAL_ERROR; 8007df2: 2301 movs r3, #1 8007df4: e00f b.n 8007e16 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8007df6: 687b ldr r3, [r7, #4] 8007df8: 681b ldr r3, [r3, #0] 8007dfa: f003 0310 and.w r3, r3, #16 8007dfe: 2b00 cmp r3, #0 8007e00: d008 beq.n 8007e14 { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8007e02: 4b07 ldr r3, [pc, #28] ; (8007e20 ) 8007e04: 685b ldr r3, [r3, #4] 8007e06: f423 0280 bic.w r2, r3, #4194304 ; 0x400000 8007e0a: 687b ldr r3, [r7, #4] 8007e0c: 69db ldr r3, [r3, #28] 8007e0e: 4904 ldr r1, [pc, #16] ; (8007e20 ) 8007e10: 4313 orrs r3, r2 8007e12: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 8007e14: 2300 movs r3, #0 } 8007e16: 4618 mov r0, r3 8007e18: 3720 adds r7, #32 8007e1a: 46bd mov sp, r7 8007e1c: bd80 pop {r7, pc} 8007e1e: bf00 nop 8007e20: 40021000 .word 0x40021000 8007e24: 40007000 .word 0x40007000 8007e28: 42420440 .word 0x42420440 8007e2c: 42420070 .word 0x42420070 08007e30 : * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 8007e30: b590 push {r4, r7, lr} 8007e32: b093 sub sp, #76 ; 0x4c 8007e34: af00 add r7, sp, #0 8007e36: 6078 str r0, [r7, #4] #if defined(STM32F105xC) || defined(STM32F107xC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; 8007e38: 4ba7 ldr r3, [pc, #668] ; (80080d8 ) 8007e3a: f107 0418 add.w r4, r7, #24 8007e3e: cb0f ldmia r3, {r0, r1, r2, r3} 8007e40: c407 stmia r4!, {r0, r1, r2} 8007e42: 8023 strh r3, [r4, #0] const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; 8007e44: 4ba5 ldr r3, [pc, #660] ; (80080dc ) 8007e46: f107 0408 add.w r4, r7, #8 8007e4a: cb0f ldmia r3, {r0, r1, r2, r3} 8007e4c: e884 000f stmia.w r4, {r0, r1, r2, r3} uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; 8007e50: 2300 movs r3, #0 8007e52: 63fb str r3, [r7, #60] ; 0x3c 8007e54: 2300 movs r3, #0 8007e56: 647b str r3, [r7, #68] ; 0x44 8007e58: 2300 movs r3, #0 8007e5a: 63bb str r3, [r7, #56] ; 0x38 uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; 8007e5c: 2300 movs r3, #0 8007e5e: 637b str r3, [r7, #52] ; 0x34 8007e60: 2300 movs r3, #0 8007e62: 633b str r3, [r7, #48] ; 0x30 8007e64: 2300 movs r3, #0 8007e66: 62fb str r3, [r7, #44] ; 0x2c const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; const uint8_t aPredivFactorTable[2] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 8007e68: 2300 movs r3, #0 8007e6a: 62bb str r3, [r7, #40] ; 0x28 8007e6c: 2300 movs r3, #0 8007e6e: 643b str r3, [r7, #64] ; 0x40 /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 8007e70: 687b ldr r3, [r7, #4] 8007e72: 3b01 subs r3, #1 8007e74: 2b0f cmp r3, #15 8007e76: f200 8121 bhi.w 80080bc 8007e7a: a201 add r2, pc, #4 ; (adr r2, 8007e80 ) 8007e7c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007e80: 0800803d .word 0x0800803d 8007e84: 080080a1 .word 0x080080a1 8007e88: 080080bd .word 0x080080bd 8007e8c: 08007f9b .word 0x08007f9b 8007e90: 080080bd .word 0x080080bd 8007e94: 080080bd .word 0x080080bd 8007e98: 080080bd .word 0x080080bd 8007e9c: 08007fed .word 0x08007fed 8007ea0: 080080bd .word 0x080080bd 8007ea4: 080080bd .word 0x080080bd 8007ea8: 080080bd .word 0x080080bd 8007eac: 080080bd .word 0x080080bd 8007eb0: 080080bd .word 0x080080bd 8007eb4: 080080bd .word 0x080080bd 8007eb8: 080080bd .word 0x080080bd 8007ebc: 08007ec1 .word 0x08007ec1 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_USB: { /* Get RCC configuration ------------------------------------------------------*/ temp_reg = RCC->CFGR; 8007ec0: 4b87 ldr r3, [pc, #540] ; (80080e0 ) 8007ec2: 685b ldr r3, [r3, #4] 8007ec4: 62bb str r3, [r7, #40] ; 0x28 /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) 8007ec6: 4b86 ldr r3, [pc, #536] ; (80080e0 ) 8007ec8: 681b ldr r3, [r3, #0] 8007eca: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 8007ece: 2b00 cmp r3, #0 8007ed0: f000 80f6 beq.w 80080c0 { pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8007ed4: 6abb ldr r3, [r7, #40] ; 0x28 8007ed6: 0c9b lsrs r3, r3, #18 8007ed8: f003 030f and.w r3, r3, #15 8007edc: 3348 adds r3, #72 ; 0x48 8007ede: 443b add r3, r7 8007ee0: f813 3c30 ldrb.w r3, [r3, #-48] 8007ee4: 63bb str r3, [r7, #56] ; 0x38 if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8007ee6: 6abb ldr r3, [r7, #40] ; 0x28 8007ee8: f403 3380 and.w r3, r3, #65536 ; 0x10000 8007eec: 2b00 cmp r3, #0 8007eee: d03d beq.n 8007f6c { #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ || defined(STM32F100xE) prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 8007ef0: 4b7b ldr r3, [pc, #492] ; (80080e0 ) 8007ef2: 6adb ldr r3, [r3, #44] ; 0x2c 8007ef4: f003 030f and.w r3, r3, #15 8007ef8: 3348 adds r3, #72 ; 0x48 8007efa: 443b add r3, r7 8007efc: f813 3c40 ldrb.w r3, [r3, #-64] 8007f00: 63fb str r3, [r7, #60] ; 0x3c #else prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 8007f02: 4b77 ldr r3, [pc, #476] ; (80080e0 ) 8007f04: 6adb ldr r3, [r3, #44] ; 0x2c 8007f06: f403 3380 and.w r3, r3, #65536 ; 0x10000 8007f0a: 2b00 cmp r3, #0 8007f0c: d01c beq.n 8007f48 { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8007f0e: 4b74 ldr r3, [pc, #464] ; (80080e0 ) 8007f10: 6adb ldr r3, [r3, #44] ; 0x2c 8007f12: 091b lsrs r3, r3, #4 8007f14: f003 030f and.w r3, r3, #15 8007f18: 3301 adds r3, #1 8007f1a: 62fb str r3, [r7, #44] ; 0x2c pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 8007f1c: 4b70 ldr r3, [pc, #448] ; (80080e0 ) 8007f1e: 6adb ldr r3, [r3, #44] ; 0x2c 8007f20: 0a1b lsrs r3, r3, #8 8007f22: f003 030f and.w r3, r3, #15 8007f26: 3302 adds r3, #2 8007f28: 637b str r3, [r7, #52] ; 0x34 pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); 8007f2a: 4a6e ldr r2, [pc, #440] ; (80080e4 ) 8007f2c: 6afb ldr r3, [r7, #44] ; 0x2c 8007f2e: fbb2 f3f3 udiv r3, r2, r3 8007f32: 6b7a ldr r2, [r7, #52] ; 0x34 8007f34: fb03 f202 mul.w r2, r3, r2 8007f38: 6bfb ldr r3, [r7, #60] ; 0x3c 8007f3a: fbb2 f2f3 udiv r2, r2, r3 8007f3e: 6bbb ldr r3, [r7, #56] ; 0x38 8007f40: fb02 f303 mul.w r3, r2, r3 8007f44: 647b str r3, [r7, #68] ; 0x44 8007f46: e007 b.n 8007f58 } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); 8007f48: 4a66 ldr r2, [pc, #408] ; (80080e4 ) 8007f4a: 6bfb ldr r3, [r7, #60] ; 0x3c 8007f4c: fbb2 f2f3 udiv r2, r2, r3 8007f50: 6bbb ldr r3, [r7, #56] ; 0x38 8007f52: fb02 f303 mul.w r3, r2, r3 8007f56: 647b str r3, [r7, #68] ; 0x44 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 8007f58: f897 3025 ldrb.w r3, [r7, #37] ; 0x25 8007f5c: 461a mov r2, r3 8007f5e: 6bbb ldr r3, [r7, #56] ; 0x38 8007f60: 4293 cmp r3, r2 8007f62: d108 bne.n 8007f76 { pllclk = pllclk / 2; 8007f64: 6c7b ldr r3, [r7, #68] ; 0x44 8007f66: 085b lsrs r3, r3, #1 8007f68: 647b str r3, [r7, #68] ; 0x44 8007f6a: e004 b.n 8007f76 #endif /* STM32F105xC || STM32F107xC */ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8007f6c: 6bbb ldr r3, [r7, #56] ; 0x38 8007f6e: 4a5e ldr r2, [pc, #376] ; (80080e8 ) 8007f70: fb02 f303 mul.w r3, r2, r3 8007f74: 647b str r3, [r7, #68] ; 0x44 } /* Calcul of the USB frequency*/ #if defined(STM32F105xC) || defined(STM32F107xC) /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) 8007f76: 4b5a ldr r3, [pc, #360] ; (80080e0 ) 8007f78: 685b ldr r3, [r3, #4] 8007f7a: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8007f7e: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8007f82: d102 bne.n 8007f8a { /* Prescaler of 2 selected for USB */ frequency = pllclk; 8007f84: 6c7b ldr r3, [r7, #68] ; 0x44 8007f86: 643b str r3, [r7, #64] ; 0x40 /* Prescaler of 1.5 selected for USB */ frequency = (pllclk * 2) / 3; } #endif } break; 8007f88: e09a b.n 80080c0 frequency = (2 * pllclk) / 3; 8007f8a: 6c7b ldr r3, [r7, #68] ; 0x44 8007f8c: 005b lsls r3, r3, #1 8007f8e: 4a57 ldr r2, [pc, #348] ; (80080ec ) 8007f90: fba2 2303 umull r2, r3, r2, r3 8007f94: 085b lsrs r3, r3, #1 8007f96: 643b str r3, [r7, #64] ; 0x40 break; 8007f98: e092 b.n 80080c0 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) 8007f9a: 4b51 ldr r3, [pc, #324] ; (80080e0 ) 8007f9c: 6adb ldr r3, [r3, #44] ; 0x2c 8007f9e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8007fa2: 2b00 cmp r3, #0 8007fa4: d103 bne.n 8007fae { /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); 8007fa6: f7ff fce3 bl 8007970 8007faa: 6438 str r0, [r7, #64] ; 0x40 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8007fac: e08a b.n 80080c4 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8007fae: 4b4c ldr r3, [pc, #304] ; (80080e0 ) 8007fb0: 681b ldr r3, [r3, #0] 8007fb2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8007fb6: 2b00 cmp r3, #0 8007fb8: f000 8084 beq.w 80080c4 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8007fbc: 4b48 ldr r3, [pc, #288] ; (80080e0 ) 8007fbe: 6adb ldr r3, [r3, #44] ; 0x2c 8007fc0: 091b lsrs r3, r3, #4 8007fc2: f003 030f and.w r3, r3, #15 8007fc6: 3301 adds r3, #1 8007fc8: 62fb str r3, [r7, #44] ; 0x2c pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 8007fca: 4b45 ldr r3, [pc, #276] ; (80080e0 ) 8007fcc: 6adb ldr r3, [r3, #44] ; 0x2c 8007fce: 0b1b lsrs r3, r3, #12 8007fd0: f003 030f and.w r3, r3, #15 8007fd4: 3302 adds r3, #2 8007fd6: 633b str r3, [r7, #48] ; 0x30 frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8007fd8: 4a42 ldr r2, [pc, #264] ; (80080e4 ) 8007fda: 6afb ldr r3, [r7, #44] ; 0x2c 8007fdc: fbb2 f3f3 udiv r3, r2, r3 8007fe0: 6b3a ldr r2, [r7, #48] ; 0x30 8007fe2: fb02 f303 mul.w r3, r2, r3 8007fe6: 005b lsls r3, r3, #1 8007fe8: 643b str r3, [r7, #64] ; 0x40 break; 8007fea: e06b b.n 80080c4 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) 8007fec: 4b3c ldr r3, [pc, #240] ; (80080e0 ) 8007fee: 6adb ldr r3, [r3, #44] ; 0x2c 8007ff0: f403 2380 and.w r3, r3, #262144 ; 0x40000 8007ff4: 2b00 cmp r3, #0 8007ff6: d103 bne.n 8008000 { /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); 8007ff8: f7ff fcba bl 8007970 8007ffc: 6438 str r0, [r7, #64] ; 0x40 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8007ffe: e063 b.n 80080c8 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8008000: 4b37 ldr r3, [pc, #220] ; (80080e0 ) 8008002: 681b ldr r3, [r3, #0] 8008004: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8008008: 2b00 cmp r3, #0 800800a: d05d beq.n 80080c8 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 800800c: 4b34 ldr r3, [pc, #208] ; (80080e0 ) 800800e: 6adb ldr r3, [r3, #44] ; 0x2c 8008010: 091b lsrs r3, r3, #4 8008012: f003 030f and.w r3, r3, #15 8008016: 3301 adds r3, #1 8008018: 62fb str r3, [r7, #44] ; 0x2c pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 800801a: 4b31 ldr r3, [pc, #196] ; (80080e0 ) 800801c: 6adb ldr r3, [r3, #44] ; 0x2c 800801e: 0b1b lsrs r3, r3, #12 8008020: f003 030f and.w r3, r3, #15 8008024: 3302 adds r3, #2 8008026: 633b str r3, [r7, #48] ; 0x30 frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8008028: 4a2e ldr r2, [pc, #184] ; (80080e4 ) 800802a: 6afb ldr r3, [r7, #44] ; 0x2c 800802c: fbb2 f3f3 udiv r3, r2, r3 8008030: 6b3a ldr r2, [r7, #48] ; 0x30 8008032: fb02 f303 mul.w r3, r2, r3 8008036: 005b lsls r3, r3, #1 8008038: 643b str r3, [r7, #64] ; 0x40 break; 800803a: e045 b.n 80080c8 } #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ case RCC_PERIPHCLK_RTC: { /* Get RCC BDCR configuration ------------------------------------------------------*/ temp_reg = RCC->BDCR; 800803c: 4b28 ldr r3, [pc, #160] ; (80080e0 ) 800803e: 6a1b ldr r3, [r3, #32] 8008040: 62bb str r3, [r7, #40] ; 0x28 /* Check if LSE is ready if RTC clock selection is LSE */ if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 8008042: 6abb ldr r3, [r7, #40] ; 0x28 8008044: f403 7340 and.w r3, r3, #768 ; 0x300 8008048: f5b3 7f80 cmp.w r3, #256 ; 0x100 800804c: d108 bne.n 8008060 800804e: 6abb ldr r3, [r7, #40] ; 0x28 8008050: f003 0302 and.w r3, r3, #2 8008054: 2b00 cmp r3, #0 8008056: d003 beq.n 8008060 { frequency = LSE_VALUE; 8008058: f44f 4300 mov.w r3, #32768 ; 0x8000 800805c: 643b str r3, [r7, #64] ; 0x40 800805e: e01e b.n 800809e } /* Check if LSI is ready if RTC clock selection is LSI */ else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 8008060: 6abb ldr r3, [r7, #40] ; 0x28 8008062: f403 7340 and.w r3, r3, #768 ; 0x300 8008066: f5b3 7f00 cmp.w r3, #512 ; 0x200 800806a: d109 bne.n 8008080 800806c: 4b1c ldr r3, [pc, #112] ; (80080e0 ) 800806e: 6a5b ldr r3, [r3, #36] ; 0x24 8008070: f003 0302 and.w r3, r3, #2 8008074: 2b00 cmp r3, #0 8008076: d003 beq.n 8008080 { frequency = LSI_VALUE; 8008078: f649 4340 movw r3, #40000 ; 0x9c40 800807c: 643b str r3, [r7, #64] ; 0x40 800807e: e00e b.n 800809e } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 8008080: 6abb ldr r3, [r7, #40] ; 0x28 8008082: f403 7340 and.w r3, r3, #768 ; 0x300 8008086: f5b3 7f40 cmp.w r3, #768 ; 0x300 800808a: d11f bne.n 80080cc 800808c: 4b14 ldr r3, [pc, #80] ; (80080e0 ) 800808e: 681b ldr r3, [r3, #0] 8008090: f403 3300 and.w r3, r3, #131072 ; 0x20000 8008094: 2b00 cmp r3, #0 8008096: d019 beq.n 80080cc { frequency = HSE_VALUE / 128U; 8008098: 4b15 ldr r3, [pc, #84] ; (80080f0 ) 800809a: 643b str r3, [r7, #64] ; 0x40 /* Clock not enabled for RTC*/ else { /* nothing to do: frequency already initialized to 0U */ } break; 800809c: e016 b.n 80080cc 800809e: e015 b.n 80080cc } case RCC_PERIPHCLK_ADC: { frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 80080a0: f7ff fd62 bl 8007b68 80080a4: 4602 mov r2, r0 80080a6: 4b0e ldr r3, [pc, #56] ; (80080e0 ) 80080a8: 685b ldr r3, [r3, #4] 80080aa: 0b9b lsrs r3, r3, #14 80080ac: f003 0303 and.w r3, r3, #3 80080b0: 3301 adds r3, #1 80080b2: 005b lsls r3, r3, #1 80080b4: fbb2 f3f3 udiv r3, r2, r3 80080b8: 643b str r3, [r7, #64] ; 0x40 break; 80080ba: e008 b.n 80080ce } default: { break; 80080bc: bf00 nop 80080be: e006 b.n 80080ce break; 80080c0: bf00 nop 80080c2: e004 b.n 80080ce break; 80080c4: bf00 nop 80080c6: e002 b.n 80080ce break; 80080c8: bf00 nop 80080ca: e000 b.n 80080ce break; 80080cc: bf00 nop } } return (frequency); 80080ce: 6c3b ldr r3, [r7, #64] ; 0x40 } 80080d0: 4618 mov r0, r3 80080d2: 374c adds r7, #76 ; 0x4c 80080d4: 46bd mov sp, r7 80080d6: bd90 pop {r4, r7, pc} 80080d8: 0800d268 .word 0x0800d268 80080dc: 0800d278 .word 0x0800d278 80080e0: 40021000 .word 0x40021000 80080e4: 017d7840 .word 0x017d7840 80080e8: 003d0900 .word 0x003d0900 80080ec: aaaaaaab .word 0xaaaaaaab 80080f0: 0002faf0 .word 0x0002faf0 080080f4 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { 80080f4: b580 push {r7, lr} 80080f6: b084 sub sp, #16 80080f8: af00 add r7, sp, #0 80080fa: 6078 str r0, [r7, #4] uint32_t prescaler = 0U; 80080fc: 2300 movs r3, #0 80080fe: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8008100: 687b ldr r3, [r7, #4] 8008102: 2b00 cmp r3, #0 8008104: d101 bne.n 800810a { return HAL_ERROR; 8008106: 2301 movs r3, #1 8008108: e084 b.n 8008214 { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else if (hrtc->State == HAL_RTC_STATE_RESET) 800810a: 687b ldr r3, [r7, #4] 800810c: 7c5b ldrb r3, [r3, #17] 800810e: b2db uxtb r3, r3 8008110: 2b00 cmp r3, #0 8008112: d105 bne.n 8008120 { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; 8008114: 687b ldr r3, [r7, #4] 8008116: 2200 movs r2, #0 8008118: 741a strb r2, [r3, #16] /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); 800811a: 6878 ldr r0, [r7, #4] 800811c: f7fc fc38 bl 8004990 } #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; 8008120: 687b ldr r3, [r7, #4] 8008122: 2202 movs r2, #2 8008124: 745a strb r2, [r3, #17] /* Waiting for synchro */ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 8008126: 6878 ldr r0, [r7, #4] 8008128: f000 f87a bl 8008220 800812c: 4603 mov r3, r0 800812e: 2b00 cmp r3, #0 8008130: d004 beq.n 800813c { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8008132: 687b ldr r3, [r7, #4] 8008134: 2204 movs r2, #4 8008136: 745a strb r2, [r3, #17] return HAL_ERROR; 8008138: 2301 movs r3, #1 800813a: e06b b.n 8008214 } /* Set Initialization mode */ if (RTC_EnterInitMode(hrtc) != HAL_OK) 800813c: 6878 ldr r0, [r7, #4] 800813e: f000 f89c bl 800827a 8008142: 4603 mov r3, r0 8008144: 2b00 cmp r3, #0 8008146: d004 beq.n 8008152 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8008148: 687b ldr r3, [r7, #4] 800814a: 2204 movs r2, #4 800814c: 745a strb r2, [r3, #17] return HAL_ERROR; 800814e: 2301 movs r3, #1 8008150: e060 b.n 8008214 } else { /* Clear Flags Bits */ CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); 8008152: 687b ldr r3, [r7, #4] 8008154: 681b ldr r3, [r3, #0] 8008156: 685a ldr r2, [r3, #4] 8008158: 687b ldr r3, [r7, #4] 800815a: 681b ldr r3, [r3, #0] 800815c: f022 0207 bic.w r2, r2, #7 8008160: 605a str r2, [r3, #4] if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) 8008162: 687b ldr r3, [r7, #4] 8008164: 689b ldr r3, [r3, #8] 8008166: 2b00 cmp r3, #0 8008168: d005 beq.n 8008176 { /* Disable the selected Tamper pin */ CLEAR_BIT(BKP->CR, BKP_CR_TPE); 800816a: 4b2c ldr r3, [pc, #176] ; (800821c ) 800816c: 6b1b ldr r3, [r3, #48] ; 0x30 800816e: 4a2b ldr r2, [pc, #172] ; (800821c ) 8008170: f023 0301 bic.w r3, r3, #1 8008174: 6313 str r3, [r2, #48] ; 0x30 } /* Set the signal which will be routed to RTC Tamper pin*/ MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); 8008176: 4b29 ldr r3, [pc, #164] ; (800821c ) 8008178: 6adb ldr r3, [r3, #44] ; 0x2c 800817a: f423 7260 bic.w r2, r3, #896 ; 0x380 800817e: 687b ldr r3, [r7, #4] 8008180: 689b ldr r3, [r3, #8] 8008182: 4926 ldr r1, [pc, #152] ; (800821c ) 8008184: 4313 orrs r3, r2 8008186: 62cb str r3, [r1, #44] ; 0x2c if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) 8008188: 687b ldr r3, [r7, #4] 800818a: 685b ldr r3, [r3, #4] 800818c: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 8008190: d003 beq.n 800819a { /* RTC Prescaler provided directly by end-user*/ prescaler = hrtc->Init.AsynchPrediv; 8008192: 687b ldr r3, [r7, #4] 8008194: 685b ldr r3, [r3, #4] 8008196: 60fb str r3, [r7, #12] 8008198: e00e b.n 80081b8 } else { /* RTC Prescaler will be automatically calculated to get 1 second timebase */ /* Get the RTCCLK frequency */ prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); 800819a: 2001 movs r0, #1 800819c: f7ff fe48 bl 8007e30 80081a0: 60f8 str r0, [r7, #12] /* Check that RTC clock is enabled*/ if (prescaler == 0U) 80081a2: 68fb ldr r3, [r7, #12] 80081a4: 2b00 cmp r3, #0 80081a6: d104 bne.n 80081b2 { /* Should not happen. Frequency is not available*/ hrtc->State = HAL_RTC_STATE_ERROR; 80081a8: 687b ldr r3, [r7, #4] 80081aa: 2204 movs r2, #4 80081ac: 745a strb r2, [r3, #17] return HAL_ERROR; 80081ae: 2301 movs r3, #1 80081b0: e030 b.n 8008214 } else { /* RTC period = RTCCLK/(RTC_PR + 1) */ prescaler = prescaler - 1U; 80081b2: 68fb ldr r3, [r7, #12] 80081b4: 3b01 subs r3, #1 80081b6: 60fb str r3, [r7, #12] } } /* Configure the RTC_PRLH / RTC_PRLL */ MODIFY_REG(hrtc->Instance->PRLH, RTC_PRLH_PRL, (prescaler >> 16U)); 80081b8: 687b ldr r3, [r7, #4] 80081ba: 681b ldr r3, [r3, #0] 80081bc: 689b ldr r3, [r3, #8] 80081be: f023 010f bic.w r1, r3, #15 80081c2: 68fb ldr r3, [r7, #12] 80081c4: 0c1a lsrs r2, r3, #16 80081c6: 687b ldr r3, [r7, #4] 80081c8: 681b ldr r3, [r3, #0] 80081ca: 430a orrs r2, r1 80081cc: 609a str r2, [r3, #8] MODIFY_REG(hrtc->Instance->PRLL, RTC_PRLL_PRL, (prescaler & RTC_PRLL_PRL)); 80081ce: 687b ldr r3, [r7, #4] 80081d0: 681b ldr r3, [r3, #0] 80081d2: 68db ldr r3, [r3, #12] 80081d4: 0c1b lsrs r3, r3, #16 80081d6: 041b lsls r3, r3, #16 80081d8: 68fa ldr r2, [r7, #12] 80081da: b291 uxth r1, r2 80081dc: 687a ldr r2, [r7, #4] 80081de: 6812 ldr r2, [r2, #0] 80081e0: 430b orrs r3, r1 80081e2: 60d3 str r3, [r2, #12] /* Wait for synchro */ if (RTC_ExitInitMode(hrtc) != HAL_OK) 80081e4: 6878 ldr r0, [r7, #4] 80081e6: f000 f870 bl 80082ca 80081ea: 4603 mov r3, r0 80081ec: 2b00 cmp r3, #0 80081ee: d004 beq.n 80081fa { hrtc->State = HAL_RTC_STATE_ERROR; 80081f0: 687b ldr r3, [r7, #4] 80081f2: 2204 movs r2, #4 80081f4: 745a strb r2, [r3, #17] return HAL_ERROR; 80081f6: 2301 movs r3, #1 80081f8: e00c b.n 8008214 } /* Initialize date to 1st of January 2000 */ hrtc->DateToUpdate.Year = 0x00U; 80081fa: 687b ldr r3, [r7, #4] 80081fc: 2200 movs r2, #0 80081fe: 73da strb r2, [r3, #15] hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; 8008200: 687b ldr r3, [r7, #4] 8008202: 2201 movs r2, #1 8008204: 735a strb r2, [r3, #13] hrtc->DateToUpdate.Date = 0x01U; 8008206: 687b ldr r3, [r7, #4] 8008208: 2201 movs r2, #1 800820a: 739a strb r2, [r3, #14] /* Set RTC state */ hrtc->State = HAL_RTC_STATE_READY; 800820c: 687b ldr r3, [r7, #4] 800820e: 2201 movs r2, #1 8008210: 745a strb r2, [r3, #17] return HAL_OK; 8008212: 2300 movs r3, #0 } } 8008214: 4618 mov r0, r3 8008216: 3710 adds r7, #16 8008218: 46bd mov sp, r7 800821a: bd80 pop {r7, pc} 800821c: 40006c00 .word 0x40006c00 08008220 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { 8008220: b580 push {r7, lr} 8008222: b084 sub sp, #16 8008224: af00 add r7, sp, #0 8008226: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8008228: 2300 movs r3, #0 800822a: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 800822c: 687b ldr r3, [r7, #4] 800822e: 2b00 cmp r3, #0 8008230: d101 bne.n 8008236 { return HAL_ERROR; 8008232: 2301 movs r3, #1 8008234: e01d b.n 8008272 } /* Clear RSF flag */ CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); 8008236: 687b ldr r3, [r7, #4] 8008238: 681b ldr r3, [r3, #0] 800823a: 685a ldr r2, [r3, #4] 800823c: 687b ldr r3, [r7, #4] 800823e: 681b ldr r3, [r3, #0] 8008240: f022 0208 bic.w r2, r2, #8 8008244: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8008246: f7fc ffa5 bl 8005194 800824a: 60f8 str r0, [r7, #12] /* Wait the registers to be synchronised */ while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 800824c: e009 b.n 8008262 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 800824e: f7fc ffa1 bl 8005194 8008252: 4602 mov r2, r0 8008254: 68fb ldr r3, [r7, #12] 8008256: 1ad3 subs r3, r2, r3 8008258: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 800825c: d901 bls.n 8008262 { return HAL_TIMEOUT; 800825e: 2303 movs r3, #3 8008260: e007 b.n 8008272 while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8008262: 687b ldr r3, [r7, #4] 8008264: 681b ldr r3, [r3, #0] 8008266: 685b ldr r3, [r3, #4] 8008268: f003 0308 and.w r3, r3, #8 800826c: 2b00 cmp r3, #0 800826e: d0ee beq.n 800824e } } return HAL_OK; 8008270: 2300 movs r3, #0 } 8008272: 4618 mov r0, r3 8008274: 3710 adds r7, #16 8008276: 46bd mov sp, r7 8008278: bd80 pop {r7, pc} 0800827a : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { 800827a: b580 push {r7, lr} 800827c: b084 sub sp, #16 800827e: af00 add r7, sp, #0 8008280: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8008282: 2300 movs r3, #0 8008284: 60fb str r3, [r7, #12] tickstart = HAL_GetTick(); 8008286: f7fc ff85 bl 8005194 800828a: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 800828c: e009 b.n 80082a2 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 800828e: f7fc ff81 bl 8005194 8008292: 4602 mov r2, r0 8008294: 68fb ldr r3, [r7, #12] 8008296: 1ad3 subs r3, r2, r3 8008298: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 800829c: d901 bls.n 80082a2 { return HAL_TIMEOUT; 800829e: 2303 movs r3, #3 80082a0: e00f b.n 80082c2 while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 80082a2: 687b ldr r3, [r7, #4] 80082a4: 681b ldr r3, [r3, #0] 80082a6: 685b ldr r3, [r3, #4] 80082a8: f003 0320 and.w r3, r3, #32 80082ac: 2b00 cmp r3, #0 80082ae: d0ee beq.n 800828e } } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 80082b0: 687b ldr r3, [r7, #4] 80082b2: 681b ldr r3, [r3, #0] 80082b4: 685a ldr r2, [r3, #4] 80082b6: 687b ldr r3, [r7, #4] 80082b8: 681b ldr r3, [r3, #0] 80082ba: f042 0210 orr.w r2, r2, #16 80082be: 605a str r2, [r3, #4] return HAL_OK; 80082c0: 2300 movs r3, #0 } 80082c2: 4618 mov r0, r3 80082c4: 3710 adds r7, #16 80082c6: 46bd mov sp, r7 80082c8: bd80 pop {r7, pc} 080082ca : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) { 80082ca: b580 push {r7, lr} 80082cc: b084 sub sp, #16 80082ce: af00 add r7, sp, #0 80082d0: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80082d2: 2300 movs r3, #0 80082d4: 60fb str r3, [r7, #12] /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 80082d6: 687b ldr r3, [r7, #4] 80082d8: 681b ldr r3, [r3, #0] 80082da: 685a ldr r2, [r3, #4] 80082dc: 687b ldr r3, [r7, #4] 80082de: 681b ldr r3, [r3, #0] 80082e0: f022 0210 bic.w r2, r2, #16 80082e4: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 80082e6: f7fc ff55 bl 8005194 80082ea: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 80082ec: e009 b.n 8008302 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 80082ee: f7fc ff51 bl 8005194 80082f2: 4602 mov r2, r0 80082f4: 68fb ldr r3, [r7, #12] 80082f6: 1ad3 subs r3, r2, r3 80082f8: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 80082fc: d901 bls.n 8008302 { return HAL_TIMEOUT; 80082fe: 2303 movs r3, #3 8008300: e007 b.n 8008312 while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8008302: 687b ldr r3, [r7, #4] 8008304: 681b ldr r3, [r3, #0] 8008306: 685b ldr r3, [r3, #4] 8008308: f003 0320 and.w r3, r3, #32 800830c: 2b00 cmp r3, #0 800830e: d0ee beq.n 80082ee } } return HAL_OK; 8008310: 2300 movs r3, #0 } 8008312: 4618 mov r0, r3 8008314: 3710 adds r7, #16 8008316: 46bd mov sp, r7 8008318: bd80 pop {r7, pc} 0800831a : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 800831a: b580 push {r7, lr} 800831c: b082 sub sp, #8 800831e: af00 add r7, sp, #0 8008320: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8008322: 687b ldr r3, [r7, #4] 8008324: 2b00 cmp r3, #0 8008326: d101 bne.n 800832c { return HAL_ERROR; 8008328: 2301 movs r3, #1 800832a: e03f b.n 80083ac assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 800832c: 687b ldr r3, [r7, #4] 800832e: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8008332: b2db uxtb r3, r3 8008334: 2b00 cmp r3, #0 8008336: d106 bne.n 8008346 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8008338: 687b ldr r3, [r7, #4] 800833a: 2200 movs r2, #0 800833c: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8008340: 6878 ldr r0, [r7, #4] 8008342: f7fc fe47 bl 8004fd4 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8008346: 687b ldr r3, [r7, #4] 8008348: 2224 movs r2, #36 ; 0x24 800834a: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 800834e: 687b ldr r3, [r7, #4] 8008350: 681b ldr r3, [r3, #0] 8008352: 68da ldr r2, [r3, #12] 8008354: 687b ldr r3, [r7, #4] 8008356: 681b ldr r3, [r3, #0] 8008358: f422 5200 bic.w r2, r2, #8192 ; 0x2000 800835c: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 800835e: 6878 ldr r0, [r7, #4] 8008360: f000 fca2 bl 8008ca8 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8008364: 687b ldr r3, [r7, #4] 8008366: 681b ldr r3, [r3, #0] 8008368: 691a ldr r2, [r3, #16] 800836a: 687b ldr r3, [r7, #4] 800836c: 681b ldr r3, [r3, #0] 800836e: f422 4290 bic.w r2, r2, #18432 ; 0x4800 8008372: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8008374: 687b ldr r3, [r7, #4] 8008376: 681b ldr r3, [r3, #0] 8008378: 695a ldr r2, [r3, #20] 800837a: 687b ldr r3, [r7, #4] 800837c: 681b ldr r3, [r3, #0] 800837e: f022 022a bic.w r2, r2, #42 ; 0x2a 8008382: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8008384: 687b ldr r3, [r7, #4] 8008386: 681b ldr r3, [r3, #0] 8008388: 68da ldr r2, [r3, #12] 800838a: 687b ldr r3, [r7, #4] 800838c: 681b ldr r3, [r3, #0] 800838e: f442 5200 orr.w r2, r2, #8192 ; 0x2000 8008392: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8008394: 687b ldr r3, [r7, #4] 8008396: 2200 movs r2, #0 8008398: 641a str r2, [r3, #64] ; 0x40 huart->gState = HAL_UART_STATE_READY; 800839a: 687b ldr r3, [r7, #4] 800839c: 2220 movs r2, #32 800839e: f883 203d strb.w r2, [r3, #61] ; 0x3d huart->RxState = HAL_UART_STATE_READY; 80083a2: 687b ldr r3, [r7, #4] 80083a4: 2220 movs r2, #32 80083a6: f883 203e strb.w r2, [r3, #62] ; 0x3e return HAL_OK; 80083aa: 2300 movs r3, #0 } 80083ac: 4618 mov r0, r3 80083ae: 3708 adds r7, #8 80083b0: 46bd mov sp, r7 80083b2: bd80 pop {r7, pc} 080083b4 : * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 80083b4: b580 push {r7, lr} 80083b6: b08a sub sp, #40 ; 0x28 80083b8: af02 add r7, sp, #8 80083ba: 60f8 str r0, [r7, #12] 80083bc: 60b9 str r1, [r7, #8] 80083be: 603b str r3, [r7, #0] 80083c0: 4613 mov r3, r2 80083c2: 80fb strh r3, [r7, #6] uint8_t *pdata8bits; uint16_t *pdata16bits; uint32_t tickstart = 0U; 80083c4: 2300 movs r3, #0 80083c6: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 80083c8: 68fb ldr r3, [r7, #12] 80083ca: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 80083ce: b2db uxtb r3, r3 80083d0: 2b20 cmp r3, #32 80083d2: d17c bne.n 80084ce { if ((pData == NULL) || (Size == 0U)) 80083d4: 68bb ldr r3, [r7, #8] 80083d6: 2b00 cmp r3, #0 80083d8: d002 beq.n 80083e0 80083da: 88fb ldrh r3, [r7, #6] 80083dc: 2b00 cmp r3, #0 80083de: d101 bne.n 80083e4 { return HAL_ERROR; 80083e0: 2301 movs r3, #1 80083e2: e075 b.n 80084d0 } /* Process Locked */ __HAL_LOCK(huart); 80083e4: 68fb ldr r3, [r7, #12] 80083e6: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 80083ea: 2b01 cmp r3, #1 80083ec: d101 bne.n 80083f2 80083ee: 2302 movs r3, #2 80083f0: e06e b.n 80084d0 80083f2: 68fb ldr r3, [r7, #12] 80083f4: 2201 movs r2, #1 80083f6: f883 203c strb.w r2, [r3, #60] ; 0x3c huart->ErrorCode = HAL_UART_ERROR_NONE; 80083fa: 68fb ldr r3, [r7, #12] 80083fc: 2200 movs r2, #0 80083fe: 641a str r2, [r3, #64] ; 0x40 huart->gState = HAL_UART_STATE_BUSY_TX; 8008400: 68fb ldr r3, [r7, #12] 8008402: 2221 movs r2, #33 ; 0x21 8008404: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8008408: f7fc fec4 bl 8005194 800840c: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 800840e: 68fb ldr r3, [r7, #12] 8008410: 88fa ldrh r2, [r7, #6] 8008412: 849a strh r2, [r3, #36] ; 0x24 huart->TxXferCount = Size; 8008414: 68fb ldr r3, [r7, #12] 8008416: 88fa ldrh r2, [r7, #6] 8008418: 84da strh r2, [r3, #38] ; 0x26 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800841a: 68fb ldr r3, [r7, #12] 800841c: 689b ldr r3, [r3, #8] 800841e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8008422: d108 bne.n 8008436 8008424: 68fb ldr r3, [r7, #12] 8008426: 691b ldr r3, [r3, #16] 8008428: 2b00 cmp r3, #0 800842a: d104 bne.n 8008436 { pdata8bits = NULL; 800842c: 2300 movs r3, #0 800842e: 61fb str r3, [r7, #28] pdata16bits = (uint16_t *) pData; 8008430: 68bb ldr r3, [r7, #8] 8008432: 61bb str r3, [r7, #24] 8008434: e003 b.n 800843e } else { pdata8bits = pData; 8008436: 68bb ldr r3, [r7, #8] 8008438: 61fb str r3, [r7, #28] pdata16bits = NULL; 800843a: 2300 movs r3, #0 800843c: 61bb str r3, [r7, #24] } /* Process Unlocked */ __HAL_UNLOCK(huart); 800843e: 68fb ldr r3, [r7, #12] 8008440: 2200 movs r2, #0 8008442: f883 203c strb.w r2, [r3, #60] ; 0x3c while (huart->TxXferCount > 0U) 8008446: e02a b.n 800849e { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8008448: 683b ldr r3, [r7, #0] 800844a: 9300 str r3, [sp, #0] 800844c: 697b ldr r3, [r7, #20] 800844e: 2200 movs r2, #0 8008450: 2180 movs r1, #128 ; 0x80 8008452: 68f8 ldr r0, [r7, #12] 8008454: f000 fa55 bl 8008902 8008458: 4603 mov r3, r0 800845a: 2b00 cmp r3, #0 800845c: d001 beq.n 8008462 { return HAL_TIMEOUT; 800845e: 2303 movs r3, #3 8008460: e036 b.n 80084d0 } if (pdata8bits == NULL) 8008462: 69fb ldr r3, [r7, #28] 8008464: 2b00 cmp r3, #0 8008466: d10b bne.n 8008480 { huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); 8008468: 69bb ldr r3, [r7, #24] 800846a: 881b ldrh r3, [r3, #0] 800846c: 461a mov r2, r3 800846e: 68fb ldr r3, [r7, #12] 8008470: 681b ldr r3, [r3, #0] 8008472: f3c2 0208 ubfx r2, r2, #0, #9 8008476: 605a str r2, [r3, #4] pdata16bits++; 8008478: 69bb ldr r3, [r7, #24] 800847a: 3302 adds r3, #2 800847c: 61bb str r3, [r7, #24] 800847e: e007 b.n 8008490 } else { huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); 8008480: 69fb ldr r3, [r7, #28] 8008482: 781a ldrb r2, [r3, #0] 8008484: 68fb ldr r3, [r7, #12] 8008486: 681b ldr r3, [r3, #0] 8008488: 605a str r2, [r3, #4] pdata8bits++; 800848a: 69fb ldr r3, [r7, #28] 800848c: 3301 adds r3, #1 800848e: 61fb str r3, [r7, #28] } huart->TxXferCount--; 8008490: 68fb ldr r3, [r7, #12] 8008492: 8cdb ldrh r3, [r3, #38] ; 0x26 8008494: b29b uxth r3, r3 8008496: 3b01 subs r3, #1 8008498: b29a uxth r2, r3 800849a: 68fb ldr r3, [r7, #12] 800849c: 84da strh r2, [r3, #38] ; 0x26 while (huart->TxXferCount > 0U) 800849e: 68fb ldr r3, [r7, #12] 80084a0: 8cdb ldrh r3, [r3, #38] ; 0x26 80084a2: b29b uxth r3, r3 80084a4: 2b00 cmp r3, #0 80084a6: d1cf bne.n 8008448 } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 80084a8: 683b ldr r3, [r7, #0] 80084aa: 9300 str r3, [sp, #0] 80084ac: 697b ldr r3, [r7, #20] 80084ae: 2200 movs r2, #0 80084b0: 2140 movs r1, #64 ; 0x40 80084b2: 68f8 ldr r0, [r7, #12] 80084b4: f000 fa25 bl 8008902 80084b8: 4603 mov r3, r0 80084ba: 2b00 cmp r3, #0 80084bc: d001 beq.n 80084c2 { return HAL_TIMEOUT; 80084be: 2303 movs r3, #3 80084c0: e006 b.n 80084d0 } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80084c2: 68fb ldr r3, [r7, #12] 80084c4: 2220 movs r2, #32 80084c6: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 80084ca: 2300 movs r3, #0 80084cc: e000 b.n 80084d0 } else { return HAL_BUSY; 80084ce: 2302 movs r3, #2 } } 80084d0: 4618 mov r0, r3 80084d2: 3720 adds r7, #32 80084d4: 46bd mov sp, r7 80084d6: bd80 pop {r7, pc} 080084d8 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80084d8: b580 push {r7, lr} 80084da: b086 sub sp, #24 80084dc: af00 add r7, sp, #0 80084de: 60f8 str r0, [r7, #12] 80084e0: 60b9 str r1, [r7, #8] 80084e2: 4613 mov r3, r2 80084e4: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 80084e6: 68fb ldr r3, [r7, #12] 80084e8: f893 303e ldrb.w r3, [r3, #62] ; 0x3e 80084ec: b2db uxtb r3, r3 80084ee: 2b20 cmp r3, #32 80084f0: d13c bne.n 800856c { if ((pData == NULL) || (Size == 0U)) 80084f2: 68bb ldr r3, [r7, #8] 80084f4: 2b00 cmp r3, #0 80084f6: d002 beq.n 80084fe 80084f8: 88fb ldrh r3, [r7, #6] 80084fa: 2b00 cmp r3, #0 80084fc: d101 bne.n 8008502 { return HAL_ERROR; 80084fe: 2301 movs r3, #1 8008500: e035 b.n 800856e } __HAL_LOCK(huart); 8008502: 68fb ldr r3, [r7, #12] 8008504: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8008508: 2b01 cmp r3, #1 800850a: d101 bne.n 8008510 800850c: 2302 movs r3, #2 800850e: e02e b.n 800856e 8008510: 68fb ldr r3, [r7, #12] 8008512: 2201 movs r2, #1 8008514: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8008518: 68fb ldr r3, [r7, #12] 800851a: 2201 movs r2, #1 800851c: 631a str r2, [r3, #48] ; 0x30 status = UART_Start_Receive_IT(huart, pData, Size); 800851e: 88fb ldrh r3, [r7, #6] 8008520: 461a mov r2, r3 8008522: 68b9 ldr r1, [r7, #8] 8008524: 68f8 ldr r0, [r7, #12] 8008526: f000 fa36 bl 8008996 800852a: 4603 mov r3, r0 800852c: 75fb strb r3, [r7, #23] /* Check Rx process has been successfully started */ if (status == HAL_OK) 800852e: 7dfb ldrb r3, [r7, #23] 8008530: 2b00 cmp r3, #0 8008532: d119 bne.n 8008568 { if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8008534: 68fb ldr r3, [r7, #12] 8008536: 6b1b ldr r3, [r3, #48] ; 0x30 8008538: 2b01 cmp r3, #1 800853a: d113 bne.n 8008564 { __HAL_UART_CLEAR_IDLEFLAG(huart); 800853c: 2300 movs r3, #0 800853e: 613b str r3, [r7, #16] 8008540: 68fb ldr r3, [r7, #12] 8008542: 681b ldr r3, [r3, #0] 8008544: 681b ldr r3, [r3, #0] 8008546: 613b str r3, [r7, #16] 8008548: 68fb ldr r3, [r7, #12] 800854a: 681b ldr r3, [r3, #0] 800854c: 685b ldr r3, [r3, #4] 800854e: 613b str r3, [r7, #16] 8008550: 693b ldr r3, [r7, #16] SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8008552: 68fb ldr r3, [r7, #12] 8008554: 681b ldr r3, [r3, #0] 8008556: 68da ldr r2, [r3, #12] 8008558: 68fb ldr r3, [r7, #12] 800855a: 681b ldr r3, [r3, #0] 800855c: f042 0210 orr.w r2, r2, #16 8008560: 60da str r2, [r3, #12] 8008562: e001 b.n 8008568 { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8008564: 2301 movs r3, #1 8008566: 75fb strb r3, [r7, #23] } } return status; 8008568: 7dfb ldrb r3, [r7, #23] 800856a: e000 b.n 800856e } else { return HAL_BUSY; 800856c: 2302 movs r3, #2 } } 800856e: 4618 mov r0, r3 8008570: 3718 adds r7, #24 8008572: 46bd mov sp, r7 8008574: bd80 pop {r7, pc} ... 08008578 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8008578: b580 push {r7, lr} 800857a: b08a sub sp, #40 ; 0x28 800857c: af00 add r7, sp, #0 800857e: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 8008580: 687b ldr r3, [r7, #4] 8008582: 681b ldr r3, [r3, #0] 8008584: 681b ldr r3, [r3, #0] 8008586: 627b str r3, [r7, #36] ; 0x24 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8008588: 687b ldr r3, [r7, #4] 800858a: 681b ldr r3, [r3, #0] 800858c: 68db ldr r3, [r3, #12] 800858e: 623b str r3, [r7, #32] uint32_t cr3its = READ_REG(huart->Instance->CR3); 8008590: 687b ldr r3, [r7, #4] 8008592: 681b ldr r3, [r3, #0] 8008594: 695b ldr r3, [r3, #20] 8008596: 61fb str r3, [r7, #28] uint32_t errorflags = 0x00U; 8008598: 2300 movs r3, #0 800859a: 61bb str r3, [r7, #24] uint32_t dmarequest = 0x00U; 800859c: 2300 movs r3, #0 800859e: 617b str r3, [r7, #20] /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 80085a0: 6a7b ldr r3, [r7, #36] ; 0x24 80085a2: f003 030f and.w r3, r3, #15 80085a6: 61bb str r3, [r7, #24] if (errorflags == RESET) 80085a8: 69bb ldr r3, [r7, #24] 80085aa: 2b00 cmp r3, #0 80085ac: d10d bne.n 80085ca { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 80085ae: 6a7b ldr r3, [r7, #36] ; 0x24 80085b0: f003 0320 and.w r3, r3, #32 80085b4: 2b00 cmp r3, #0 80085b6: d008 beq.n 80085ca 80085b8: 6a3b ldr r3, [r7, #32] 80085ba: f003 0320 and.w r3, r3, #32 80085be: 2b00 cmp r3, #0 80085c0: d003 beq.n 80085ca { UART_Receive_IT(huart); 80085c2: 6878 ldr r0, [r7, #4] 80085c4: f000 fac7 bl 8008b56 return; 80085c8: e17b b.n 80088c2 } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 80085ca: 69bb ldr r3, [r7, #24] 80085cc: 2b00 cmp r3, #0 80085ce: f000 80b1 beq.w 8008734 80085d2: 69fb ldr r3, [r7, #28] 80085d4: f003 0301 and.w r3, r3, #1 80085d8: 2b00 cmp r3, #0 80085da: d105 bne.n 80085e8 80085dc: 6a3b ldr r3, [r7, #32] 80085de: f403 7390 and.w r3, r3, #288 ; 0x120 80085e2: 2b00 cmp r3, #0 80085e4: f000 80a6 beq.w 8008734 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 80085e8: 6a7b ldr r3, [r7, #36] ; 0x24 80085ea: f003 0301 and.w r3, r3, #1 80085ee: 2b00 cmp r3, #0 80085f0: d00a beq.n 8008608 80085f2: 6a3b ldr r3, [r7, #32] 80085f4: f403 7380 and.w r3, r3, #256 ; 0x100 80085f8: 2b00 cmp r3, #0 80085fa: d005 beq.n 8008608 { huart->ErrorCode |= HAL_UART_ERROR_PE; 80085fc: 687b ldr r3, [r7, #4] 80085fe: 6c1b ldr r3, [r3, #64] ; 0x40 8008600: f043 0201 orr.w r2, r3, #1 8008604: 687b ldr r3, [r7, #4] 8008606: 641a str r2, [r3, #64] ; 0x40 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8008608: 6a7b ldr r3, [r7, #36] ; 0x24 800860a: f003 0304 and.w r3, r3, #4 800860e: 2b00 cmp r3, #0 8008610: d00a beq.n 8008628 8008612: 69fb ldr r3, [r7, #28] 8008614: f003 0301 and.w r3, r3, #1 8008618: 2b00 cmp r3, #0 800861a: d005 beq.n 8008628 { huart->ErrorCode |= HAL_UART_ERROR_NE; 800861c: 687b ldr r3, [r7, #4] 800861e: 6c1b ldr r3, [r3, #64] ; 0x40 8008620: f043 0202 orr.w r2, r3, #2 8008624: 687b ldr r3, [r7, #4] 8008626: 641a str r2, [r3, #64] ; 0x40 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8008628: 6a7b ldr r3, [r7, #36] ; 0x24 800862a: f003 0302 and.w r3, r3, #2 800862e: 2b00 cmp r3, #0 8008630: d00a beq.n 8008648 8008632: 69fb ldr r3, [r7, #28] 8008634: f003 0301 and.w r3, r3, #1 8008638: 2b00 cmp r3, #0 800863a: d005 beq.n 8008648 { huart->ErrorCode |= HAL_UART_ERROR_FE; 800863c: 687b ldr r3, [r7, #4] 800863e: 6c1b ldr r3, [r3, #64] ; 0x40 8008640: f043 0204 orr.w r2, r3, #4 8008644: 687b ldr r3, [r7, #4] 8008646: 641a str r2, [r3, #64] ; 0x40 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) 8008648: 6a7b ldr r3, [r7, #36] ; 0x24 800864a: f003 0308 and.w r3, r3, #8 800864e: 2b00 cmp r3, #0 8008650: d00f beq.n 8008672 8008652: 6a3b ldr r3, [r7, #32] 8008654: f003 0320 and.w r3, r3, #32 8008658: 2b00 cmp r3, #0 800865a: d104 bne.n 8008666 800865c: 69fb ldr r3, [r7, #28] 800865e: f003 0301 and.w r3, r3, #1 8008662: 2b00 cmp r3, #0 8008664: d005 beq.n 8008672 { huart->ErrorCode |= HAL_UART_ERROR_ORE; 8008666: 687b ldr r3, [r7, #4] 8008668: 6c1b ldr r3, [r3, #64] ; 0x40 800866a: f043 0208 orr.w r2, r3, #8 800866e: 687b ldr r3, [r7, #4] 8008670: 641a str r2, [r3, #64] ; 0x40 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8008672: 687b ldr r3, [r7, #4] 8008674: 6c1b ldr r3, [r3, #64] ; 0x40 8008676: 2b00 cmp r3, #0 8008678: f000 811e beq.w 80088b8 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 800867c: 6a7b ldr r3, [r7, #36] ; 0x24 800867e: f003 0320 and.w r3, r3, #32 8008682: 2b00 cmp r3, #0 8008684: d007 beq.n 8008696 8008686: 6a3b ldr r3, [r7, #32] 8008688: f003 0320 and.w r3, r3, #32 800868c: 2b00 cmp r3, #0 800868e: d002 beq.n 8008696 { UART_Receive_IT(huart); 8008690: 6878 ldr r0, [r7, #4] 8008692: f000 fa60 bl 8008b56 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8008696: 687b ldr r3, [r7, #4] 8008698: 681b ldr r3, [r3, #0] 800869a: 695b ldr r3, [r3, #20] 800869c: f003 0340 and.w r3, r3, #64 ; 0x40 80086a0: 2b00 cmp r3, #0 80086a2: bf14 ite ne 80086a4: 2301 movne r3, #1 80086a6: 2300 moveq r3, #0 80086a8: b2db uxtb r3, r3 80086aa: 617b str r3, [r7, #20] if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 80086ac: 687b ldr r3, [r7, #4] 80086ae: 6c1b ldr r3, [r3, #64] ; 0x40 80086b0: f003 0308 and.w r3, r3, #8 80086b4: 2b00 cmp r3, #0 80086b6: d102 bne.n 80086be 80086b8: 697b ldr r3, [r7, #20] 80086ba: 2b00 cmp r3, #0 80086bc: d031 beq.n 8008722 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 80086be: 6878 ldr r0, [r7, #4] 80086c0: f000 f9a2 bl 8008a08 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80086c4: 687b ldr r3, [r7, #4] 80086c6: 681b ldr r3, [r3, #0] 80086c8: 695b ldr r3, [r3, #20] 80086ca: f003 0340 and.w r3, r3, #64 ; 0x40 80086ce: 2b00 cmp r3, #0 80086d0: d023 beq.n 800871a { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80086d2: 687b ldr r3, [r7, #4] 80086d4: 681b ldr r3, [r3, #0] 80086d6: 695a ldr r2, [r3, #20] 80086d8: 687b ldr r3, [r7, #4] 80086da: 681b ldr r3, [r3, #0] 80086dc: f022 0240 bic.w r2, r2, #64 ; 0x40 80086e0: 615a str r2, [r3, #20] /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 80086e2: 687b ldr r3, [r7, #4] 80086e4: 6b9b ldr r3, [r3, #56] ; 0x38 80086e6: 2b00 cmp r3, #0 80086e8: d013 beq.n 8008712 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 80086ea: 687b ldr r3, [r7, #4] 80086ec: 6b9b ldr r3, [r3, #56] ; 0x38 80086ee: 4a76 ldr r2, [pc, #472] ; (80088c8 ) 80086f0: 635a str r2, [r3, #52] ; 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 80086f2: 687b ldr r3, [r7, #4] 80086f4: 6b9b ldr r3, [r3, #56] ; 0x38 80086f6: 4618 mov r0, r3 80086f8: f7fe fa72 bl 8006be0 80086fc: 4603 mov r3, r0 80086fe: 2b00 cmp r3, #0 8008700: d016 beq.n 8008730 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8008702: 687b ldr r3, [r7, #4] 8008704: 6b9b ldr r3, [r3, #56] ; 0x38 8008706: 6b5b ldr r3, [r3, #52] ; 0x34 8008708: 687a ldr r2, [r7, #4] 800870a: 6b92 ldr r2, [r2, #56] ; 0x38 800870c: 4610 mov r0, r2 800870e: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8008710: e00e b.n 8008730 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8008712: 6878 ldr r0, [r7, #4] 8008714: f000 f8ec bl 80088f0 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8008718: e00a b.n 8008730 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800871a: 6878 ldr r0, [r7, #4] 800871c: f000 f8e8 bl 80088f0 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8008720: e006 b.n 8008730 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8008722: 6878 ldr r0, [r7, #4] 8008724: f000 f8e4 bl 80088f0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8008728: 687b ldr r3, [r7, #4] 800872a: 2200 movs r2, #0 800872c: 641a str r2, [r3, #64] ; 0x40 } } return; 800872e: e0c3 b.n 80088b8 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8008730: bf00 nop return; 8008732: e0c1 b.n 80088b8 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8008734: 687b ldr r3, [r7, #4] 8008736: 6b1b ldr r3, [r3, #48] ; 0x30 8008738: 2b01 cmp r3, #1 800873a: f040 80a1 bne.w 8008880 &&((isrflags & USART_SR_IDLE) != 0U) 800873e: 6a7b ldr r3, [r7, #36] ; 0x24 8008740: f003 0310 and.w r3, r3, #16 8008744: 2b00 cmp r3, #0 8008746: f000 809b beq.w 8008880 &&((cr1its & USART_SR_IDLE) != 0U)) 800874a: 6a3b ldr r3, [r7, #32] 800874c: f003 0310 and.w r3, r3, #16 8008750: 2b00 cmp r3, #0 8008752: f000 8095 beq.w 8008880 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8008756: 2300 movs r3, #0 8008758: 60fb str r3, [r7, #12] 800875a: 687b ldr r3, [r7, #4] 800875c: 681b ldr r3, [r3, #0] 800875e: 681b ldr r3, [r3, #0] 8008760: 60fb str r3, [r7, #12] 8008762: 687b ldr r3, [r7, #4] 8008764: 681b ldr r3, [r3, #0] 8008766: 685b ldr r3, [r3, #4] 8008768: 60fb str r3, [r7, #12] 800876a: 68fb ldr r3, [r7, #12] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800876c: 687b ldr r3, [r7, #4] 800876e: 681b ldr r3, [r3, #0] 8008770: 695b ldr r3, [r3, #20] 8008772: f003 0340 and.w r3, r3, #64 ; 0x40 8008776: 2b00 cmp r3, #0 8008778: d04e beq.n 8008818 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 800877a: 687b ldr r3, [r7, #4] 800877c: 6b9b ldr r3, [r3, #56] ; 0x38 800877e: 681b ldr r3, [r3, #0] 8008780: 685b ldr r3, [r3, #4] 8008782: 823b strh r3, [r7, #16] if ( (nb_remaining_rx_data > 0U) 8008784: 8a3b ldrh r3, [r7, #16] 8008786: 2b00 cmp r3, #0 8008788: f000 8098 beq.w 80088bc &&(nb_remaining_rx_data < huart->RxXferSize)) 800878c: 687b ldr r3, [r7, #4] 800878e: 8d9b ldrh r3, [r3, #44] ; 0x2c 8008790: 8a3a ldrh r2, [r7, #16] 8008792: 429a cmp r2, r3 8008794: f080 8092 bcs.w 80088bc { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8008798: 687b ldr r3, [r7, #4] 800879a: 8a3a ldrh r2, [r7, #16] 800879c: 85da strh r2, [r3, #46] ; 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 800879e: 687b ldr r3, [r7, #4] 80087a0: 6b9b ldr r3, [r3, #56] ; 0x38 80087a2: 699b ldr r3, [r3, #24] 80087a4: 2b20 cmp r3, #32 80087a6: d02b beq.n 8008800 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80087a8: 687b ldr r3, [r7, #4] 80087aa: 681b ldr r3, [r3, #0] 80087ac: 68da ldr r2, [r3, #12] 80087ae: 687b ldr r3, [r7, #4] 80087b0: 681b ldr r3, [r3, #0] 80087b2: f422 7280 bic.w r2, r2, #256 ; 0x100 80087b6: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80087b8: 687b ldr r3, [r7, #4] 80087ba: 681b ldr r3, [r3, #0] 80087bc: 695a ldr r2, [r3, #20] 80087be: 687b ldr r3, [r7, #4] 80087c0: 681b ldr r3, [r3, #0] 80087c2: f022 0201 bic.w r2, r2, #1 80087c6: 615a str r2, [r3, #20] /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80087c8: 687b ldr r3, [r7, #4] 80087ca: 681b ldr r3, [r3, #0] 80087cc: 695a ldr r2, [r3, #20] 80087ce: 687b ldr r3, [r7, #4] 80087d0: 681b ldr r3, [r3, #0] 80087d2: f022 0240 bic.w r2, r2, #64 ; 0x40 80087d6: 615a str r2, [r3, #20] /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80087d8: 687b ldr r3, [r7, #4] 80087da: 2220 movs r2, #32 80087dc: f883 203e strb.w r2, [r3, #62] ; 0x3e huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80087e0: 687b ldr r3, [r7, #4] 80087e2: 2200 movs r2, #0 80087e4: 631a str r2, [r3, #48] ; 0x30 CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80087e6: 687b ldr r3, [r7, #4] 80087e8: 681b ldr r3, [r3, #0] 80087ea: 68da ldr r2, [r3, #12] 80087ec: 687b ldr r3, [r7, #4] 80087ee: 681b ldr r3, [r3, #0] 80087f0: f022 0210 bic.w r2, r2, #16 80087f4: 60da str r2, [r3, #12] /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 80087f6: 687b ldr r3, [r7, #4] 80087f8: 6b9b ldr r3, [r3, #56] ; 0x38 80087fa: 4618 mov r0, r3 80087fc: f7fe f9b5 bl 8006b6a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8008800: 687b ldr r3, [r7, #4] 8008802: 8d9a ldrh r2, [r3, #44] ; 0x2c 8008804: 687b ldr r3, [r7, #4] 8008806: 8ddb ldrh r3, [r3, #46] ; 0x2e 8008808: b29b uxth r3, r3 800880a: 1ad3 subs r3, r2, r3 800880c: b29b uxth r3, r3 800880e: 4619 mov r1, r3 8008810: 6878 ldr r0, [r7, #4] 8008812: f7fa f83b bl 800288c #endif } return; 8008816: e051 b.n 80088bc else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8008818: 687b ldr r3, [r7, #4] 800881a: 8d9a ldrh r2, [r3, #44] ; 0x2c 800881c: 687b ldr r3, [r7, #4] 800881e: 8ddb ldrh r3, [r3, #46] ; 0x2e 8008820: b29b uxth r3, r3 8008822: 1ad3 subs r3, r2, r3 8008824: 827b strh r3, [r7, #18] if ( (huart->RxXferCount > 0U) 8008826: 687b ldr r3, [r7, #4] 8008828: 8ddb ldrh r3, [r3, #46] ; 0x2e 800882a: b29b uxth r3, r3 800882c: 2b00 cmp r3, #0 800882e: d047 beq.n 80088c0 &&(nb_rx_data > 0U) ) 8008830: 8a7b ldrh r3, [r7, #18] 8008832: 2b00 cmp r3, #0 8008834: d044 beq.n 80088c0 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8008836: 687b ldr r3, [r7, #4] 8008838: 681b ldr r3, [r3, #0] 800883a: 68da ldr r2, [r3, #12] 800883c: 687b ldr r3, [r7, #4] 800883e: 681b ldr r3, [r3, #0] 8008840: f422 7290 bic.w r2, r2, #288 ; 0x120 8008844: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8008846: 687b ldr r3, [r7, #4] 8008848: 681b ldr r3, [r3, #0] 800884a: 695a ldr r2, [r3, #20] 800884c: 687b ldr r3, [r7, #4] 800884e: 681b ldr r3, [r3, #0] 8008850: f022 0201 bic.w r2, r2, #1 8008854: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8008856: 687b ldr r3, [r7, #4] 8008858: 2220 movs r2, #32 800885a: f883 203e strb.w r2, [r3, #62] ; 0x3e huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800885e: 687b ldr r3, [r7, #4] 8008860: 2200 movs r2, #0 8008862: 631a str r2, [r3, #48] ; 0x30 CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8008864: 687b ldr r3, [r7, #4] 8008866: 681b ldr r3, [r3, #0] 8008868: 68da ldr r2, [r3, #12] 800886a: 687b ldr r3, [r7, #4] 800886c: 681b ldr r3, [r3, #0] 800886e: f022 0210 bic.w r2, r2, #16 8008872: 60da str r2, [r3, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8008874: 8a7b ldrh r3, [r7, #18] 8008876: 4619 mov r1, r3 8008878: 6878 ldr r0, [r7, #4] 800887a: f7fa f807 bl 800288c #endif } return; 800887e: e01f b.n 80088c0 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8008880: 6a7b ldr r3, [r7, #36] ; 0x24 8008882: f003 0380 and.w r3, r3, #128 ; 0x80 8008886: 2b00 cmp r3, #0 8008888: d008 beq.n 800889c 800888a: 6a3b ldr r3, [r7, #32] 800888c: f003 0380 and.w r3, r3, #128 ; 0x80 8008890: 2b00 cmp r3, #0 8008892: d003 beq.n 800889c { UART_Transmit_IT(huart); 8008894: 6878 ldr r0, [r7, #4] 8008896: f000 f8f7 bl 8008a88 return; 800889a: e012 b.n 80088c2 } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 800889c: 6a7b ldr r3, [r7, #36] ; 0x24 800889e: f003 0340 and.w r3, r3, #64 ; 0x40 80088a2: 2b00 cmp r3, #0 80088a4: d00d beq.n 80088c2 80088a6: 6a3b ldr r3, [r7, #32] 80088a8: f003 0340 and.w r3, r3, #64 ; 0x40 80088ac: 2b00 cmp r3, #0 80088ae: d008 beq.n 80088c2 { UART_EndTransmit_IT(huart); 80088b0: 6878 ldr r0, [r7, #4] 80088b2: f000 f938 bl 8008b26 return; 80088b6: e004 b.n 80088c2 return; 80088b8: bf00 nop 80088ba: e002 b.n 80088c2 return; 80088bc: bf00 nop 80088be: e000 b.n 80088c2 return; 80088c0: bf00 nop } } 80088c2: 3728 adds r7, #40 ; 0x28 80088c4: 46bd mov sp, r7 80088c6: bd80 pop {r7, pc} 80088c8: 08008a61 .word 0x08008a61 080088cc : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 80088cc: b480 push {r7} 80088ce: b083 sub sp, #12 80088d0: af00 add r7, sp, #0 80088d2: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 80088d4: bf00 nop 80088d6: 370c adds r7, #12 80088d8: 46bd mov sp, r7 80088da: bc80 pop {r7} 80088dc: 4770 bx lr 080088de : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 80088de: b480 push {r7} 80088e0: b083 sub sp, #12 80088e2: af00 add r7, sp, #0 80088e4: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback could be implemented in the user file */ } 80088e6: bf00 nop 80088e8: 370c adds r7, #12 80088ea: 46bd mov sp, r7 80088ec: bc80 pop {r7} 80088ee: 4770 bx lr 080088f0 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 80088f0: b480 push {r7} 80088f2: b083 sub sp, #12 80088f4: af00 add r7, sp, #0 80088f6: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback could be implemented in the user file */ } 80088f8: bf00 nop 80088fa: 370c adds r7, #12 80088fc: 46bd mov sp, r7 80088fe: bc80 pop {r7} 8008900: 4770 bx lr 08008902 : * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8008902: b580 push {r7, lr} 8008904: b084 sub sp, #16 8008906: af00 add r7, sp, #0 8008908: 60f8 str r0, [r7, #12] 800890a: 60b9 str r1, [r7, #8] 800890c: 603b str r3, [r7, #0] 800890e: 4613 mov r3, r2 8008910: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8008912: e02c b.n 800896e { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8008914: 69bb ldr r3, [r7, #24] 8008916: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 800891a: d028 beq.n 800896e { if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) 800891c: 69bb ldr r3, [r7, #24] 800891e: 2b00 cmp r3, #0 8008920: d007 beq.n 8008932 8008922: f7fc fc37 bl 8005194 8008926: 4602 mov r2, r0 8008928: 683b ldr r3, [r7, #0] 800892a: 1ad3 subs r3, r2, r3 800892c: 69ba ldr r2, [r7, #24] 800892e: 429a cmp r2, r3 8008930: d21d bcs.n 800896e { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); 8008932: 68fb ldr r3, [r7, #12] 8008934: 681b ldr r3, [r3, #0] 8008936: 68da ldr r2, [r3, #12] 8008938: 68fb ldr r3, [r7, #12] 800893a: 681b ldr r3, [r3, #0] 800893c: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 8008940: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8008942: 68fb ldr r3, [r7, #12] 8008944: 681b ldr r3, [r3, #0] 8008946: 695a ldr r2, [r3, #20] 8008948: 68fb ldr r3, [r7, #12] 800894a: 681b ldr r3, [r3, #0] 800894c: f022 0201 bic.w r2, r2, #1 8008950: 615a str r2, [r3, #20] huart->gState = HAL_UART_STATE_READY; 8008952: 68fb ldr r3, [r7, #12] 8008954: 2220 movs r2, #32 8008956: f883 203d strb.w r2, [r3, #61] ; 0x3d huart->RxState = HAL_UART_STATE_READY; 800895a: 68fb ldr r3, [r7, #12] 800895c: 2220 movs r2, #32 800895e: f883 203e strb.w r2, [r3, #62] ; 0x3e /* Process Unlocked */ __HAL_UNLOCK(huart); 8008962: 68fb ldr r3, [r7, #12] 8008964: 2200 movs r2, #0 8008966: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_TIMEOUT; 800896a: 2303 movs r3, #3 800896c: e00f b.n 800898e while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800896e: 68fb ldr r3, [r7, #12] 8008970: 681b ldr r3, [r3, #0] 8008972: 681a ldr r2, [r3, #0] 8008974: 68bb ldr r3, [r7, #8] 8008976: 4013 ands r3, r2 8008978: 68ba ldr r2, [r7, #8] 800897a: 429a cmp r2, r3 800897c: bf0c ite eq 800897e: 2301 moveq r3, #1 8008980: 2300 movne r3, #0 8008982: b2db uxtb r3, r3 8008984: 461a mov r2, r3 8008986: 79fb ldrb r3, [r7, #7] 8008988: 429a cmp r2, r3 800898a: d0c3 beq.n 8008914 } } } return HAL_OK; 800898c: 2300 movs r3, #0 } 800898e: 4618 mov r0, r3 8008990: 3710 adds r7, #16 8008992: 46bd mov sp, r7 8008994: bd80 pop {r7, pc} 08008996 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8008996: b480 push {r7} 8008998: b085 sub sp, #20 800899a: af00 add r7, sp, #0 800899c: 60f8 str r0, [r7, #12] 800899e: 60b9 str r1, [r7, #8] 80089a0: 4613 mov r3, r2 80089a2: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 80089a4: 68fb ldr r3, [r7, #12] 80089a6: 68ba ldr r2, [r7, #8] 80089a8: 629a str r2, [r3, #40] ; 0x28 huart->RxXferSize = Size; 80089aa: 68fb ldr r3, [r7, #12] 80089ac: 88fa ldrh r2, [r7, #6] 80089ae: 859a strh r2, [r3, #44] ; 0x2c huart->RxXferCount = Size; 80089b0: 68fb ldr r3, [r7, #12] 80089b2: 88fa ldrh r2, [r7, #6] 80089b4: 85da strh r2, [r3, #46] ; 0x2e huart->ErrorCode = HAL_UART_ERROR_NONE; 80089b6: 68fb ldr r3, [r7, #12] 80089b8: 2200 movs r2, #0 80089ba: 641a str r2, [r3, #64] ; 0x40 huart->RxState = HAL_UART_STATE_BUSY_RX; 80089bc: 68fb ldr r3, [r7, #12] 80089be: 2222 movs r2, #34 ; 0x22 80089c0: f883 203e strb.w r2, [r3, #62] ; 0x3e /* Process Unlocked */ __HAL_UNLOCK(huart); 80089c4: 68fb ldr r3, [r7, #12] 80089c6: 2200 movs r2, #0 80089c8: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); 80089cc: 68fb ldr r3, [r7, #12] 80089ce: 681b ldr r3, [r3, #0] 80089d0: 68da ldr r2, [r3, #12] 80089d2: 68fb ldr r3, [r7, #12] 80089d4: 681b ldr r3, [r3, #0] 80089d6: f442 7280 orr.w r2, r2, #256 ; 0x100 80089da: 60da str r2, [r3, #12] /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); 80089dc: 68fb ldr r3, [r7, #12] 80089de: 681b ldr r3, [r3, #0] 80089e0: 695a ldr r2, [r3, #20] 80089e2: 68fb ldr r3, [r7, #12] 80089e4: 681b ldr r3, [r3, #0] 80089e6: f042 0201 orr.w r2, r2, #1 80089ea: 615a str r2, [r3, #20] /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); 80089ec: 68fb ldr r3, [r7, #12] 80089ee: 681b ldr r3, [r3, #0] 80089f0: 68da ldr r2, [r3, #12] 80089f2: 68fb ldr r3, [r7, #12] 80089f4: 681b ldr r3, [r3, #0] 80089f6: f042 0220 orr.w r2, r2, #32 80089fa: 60da str r2, [r3, #12] return HAL_OK; 80089fc: 2300 movs r3, #0 } 80089fe: 4618 mov r0, r3 8008a00: 3714 adds r7, #20 8008a02: 46bd mov sp, r7 8008a04: bc80 pop {r7} 8008a06: 4770 bx lr 08008a08 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8008a08: b480 push {r7} 8008a0a: b083 sub sp, #12 8008a0c: af00 add r7, sp, #0 8008a0e: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8008a10: 687b ldr r3, [r7, #4] 8008a12: 681b ldr r3, [r3, #0] 8008a14: 68da ldr r2, [r3, #12] 8008a16: 687b ldr r3, [r7, #4] 8008a18: 681b ldr r3, [r3, #0] 8008a1a: f422 7290 bic.w r2, r2, #288 ; 0x120 8008a1e: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8008a20: 687b ldr r3, [r7, #4] 8008a22: 681b ldr r3, [r3, #0] 8008a24: 695a ldr r2, [r3, #20] 8008a26: 687b ldr r3, [r7, #4] 8008a28: 681b ldr r3, [r3, #0] 8008a2a: f022 0201 bic.w r2, r2, #1 8008a2e: 615a str r2, [r3, #20] /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8008a30: 687b ldr r3, [r7, #4] 8008a32: 6b1b ldr r3, [r3, #48] ; 0x30 8008a34: 2b01 cmp r3, #1 8008a36: d107 bne.n 8008a48 { CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8008a38: 687b ldr r3, [r7, #4] 8008a3a: 681b ldr r3, [r3, #0] 8008a3c: 68da ldr r2, [r3, #12] 8008a3e: 687b ldr r3, [r7, #4] 8008a40: 681b ldr r3, [r3, #0] 8008a42: f022 0210 bic.w r2, r2, #16 8008a46: 60da str r2, [r3, #12] } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8008a48: 687b ldr r3, [r7, #4] 8008a4a: 2220 movs r2, #32 8008a4c: f883 203e strb.w r2, [r3, #62] ; 0x3e huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8008a50: 687b ldr r3, [r7, #4] 8008a52: 2200 movs r2, #0 8008a54: 631a str r2, [r3, #48] ; 0x30 } 8008a56: bf00 nop 8008a58: 370c adds r7, #12 8008a5a: 46bd mov sp, r7 8008a5c: bc80 pop {r7} 8008a5e: 4770 bx lr 08008a60 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8008a60: b580 push {r7, lr} 8008a62: b084 sub sp, #16 8008a64: af00 add r7, sp, #0 8008a66: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8008a68: 687b ldr r3, [r7, #4] 8008a6a: 6a5b ldr r3, [r3, #36] ; 0x24 8008a6c: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8008a6e: 68fb ldr r3, [r7, #12] 8008a70: 2200 movs r2, #0 8008a72: 85da strh r2, [r3, #46] ; 0x2e huart->TxXferCount = 0x00U; 8008a74: 68fb ldr r3, [r7, #12] 8008a76: 2200 movs r2, #0 8008a78: 84da strh r2, [r3, #38] ; 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8008a7a: 68f8 ldr r0, [r7, #12] 8008a7c: f7ff ff38 bl 80088f0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8008a80: bf00 nop 8008a82: 3710 adds r7, #16 8008a84: 46bd mov sp, r7 8008a86: bd80 pop {r7, pc} 08008a88 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 8008a88: b480 push {r7} 8008a8a: b085 sub sp, #20 8008a8c: af00 add r7, sp, #0 8008a8e: 6078 str r0, [r7, #4] uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8008a90: 687b ldr r3, [r7, #4] 8008a92: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8008a96: b2db uxtb r3, r3 8008a98: 2b21 cmp r3, #33 ; 0x21 8008a9a: d13e bne.n 8008b1a { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8008a9c: 687b ldr r3, [r7, #4] 8008a9e: 689b ldr r3, [r3, #8] 8008aa0: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8008aa4: d114 bne.n 8008ad0 8008aa6: 687b ldr r3, [r7, #4] 8008aa8: 691b ldr r3, [r3, #16] 8008aaa: 2b00 cmp r3, #0 8008aac: d110 bne.n 8008ad0 { tmp = (uint16_t *) huart->pTxBuffPtr; 8008aae: 687b ldr r3, [r7, #4] 8008ab0: 6a1b ldr r3, [r3, #32] 8008ab2: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8008ab4: 68fb ldr r3, [r7, #12] 8008ab6: 881b ldrh r3, [r3, #0] 8008ab8: 461a mov r2, r3 8008aba: 687b ldr r3, [r7, #4] 8008abc: 681b ldr r3, [r3, #0] 8008abe: f3c2 0208 ubfx r2, r2, #0, #9 8008ac2: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 8008ac4: 687b ldr r3, [r7, #4] 8008ac6: 6a1b ldr r3, [r3, #32] 8008ac8: 1c9a adds r2, r3, #2 8008aca: 687b ldr r3, [r7, #4] 8008acc: 621a str r2, [r3, #32] 8008ace: e008 b.n 8008ae2 } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 8008ad0: 687b ldr r3, [r7, #4] 8008ad2: 6a1b ldr r3, [r3, #32] 8008ad4: 1c59 adds r1, r3, #1 8008ad6: 687a ldr r2, [r7, #4] 8008ad8: 6211 str r1, [r2, #32] 8008ada: 781a ldrb r2, [r3, #0] 8008adc: 687b ldr r3, [r7, #4] 8008ade: 681b ldr r3, [r3, #0] 8008ae0: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 8008ae2: 687b ldr r3, [r7, #4] 8008ae4: 8cdb ldrh r3, [r3, #38] ; 0x26 8008ae6: b29b uxth r3, r3 8008ae8: 3b01 subs r3, #1 8008aea: b29b uxth r3, r3 8008aec: 687a ldr r2, [r7, #4] 8008aee: 4619 mov r1, r3 8008af0: 84d1 strh r1, [r2, #38] ; 0x26 8008af2: 2b00 cmp r3, #0 8008af4: d10f bne.n 8008b16 { /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8008af6: 687b ldr r3, [r7, #4] 8008af8: 681b ldr r3, [r3, #0] 8008afa: 68da ldr r2, [r3, #12] 8008afc: 687b ldr r3, [r7, #4] 8008afe: 681b ldr r3, [r3, #0] 8008b00: f022 0280 bic.w r2, r2, #128 ; 0x80 8008b04: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8008b06: 687b ldr r3, [r7, #4] 8008b08: 681b ldr r3, [r3, #0] 8008b0a: 68da ldr r2, [r3, #12] 8008b0c: 687b ldr r3, [r7, #4] 8008b0e: 681b ldr r3, [r3, #0] 8008b10: f042 0240 orr.w r2, r2, #64 ; 0x40 8008b14: 60da str r2, [r3, #12] } return HAL_OK; 8008b16: 2300 movs r3, #0 8008b18: e000 b.n 8008b1c } else { return HAL_BUSY; 8008b1a: 2302 movs r3, #2 } } 8008b1c: 4618 mov r0, r3 8008b1e: 3714 adds r7, #20 8008b20: 46bd mov sp, r7 8008b22: bc80 pop {r7} 8008b24: 4770 bx lr 08008b26 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8008b26: b580 push {r7, lr} 8008b28: b082 sub sp, #8 8008b2a: af00 add r7, sp, #0 8008b2c: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 8008b2e: 687b ldr r3, [r7, #4] 8008b30: 681b ldr r3, [r3, #0] 8008b32: 68da ldr r2, [r3, #12] 8008b34: 687b ldr r3, [r7, #4] 8008b36: 681b ldr r3, [r3, #0] 8008b38: f022 0240 bic.w r2, r2, #64 ; 0x40 8008b3c: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8008b3e: 687b ldr r3, [r7, #4] 8008b40: 2220 movs r2, #32 8008b42: f883 203d strb.w r2, [r3, #61] ; 0x3d #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8008b46: 6878 ldr r0, [r7, #4] 8008b48: f7ff fec0 bl 80088cc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8008b4c: 2300 movs r3, #0 } 8008b4e: 4618 mov r0, r3 8008b50: 3708 adds r7, #8 8008b52: 46bd mov sp, r7 8008b54: bd80 pop {r7, pc} 08008b56 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 8008b56: b580 push {r7, lr} 8008b58: b086 sub sp, #24 8008b5a: af00 add r7, sp, #0 8008b5c: 6078 str r0, [r7, #4] uint8_t *pdata8bits; uint16_t *pdata16bits; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8008b5e: 687b ldr r3, [r7, #4] 8008b60: f893 303e ldrb.w r3, [r3, #62] ; 0x3e 8008b64: b2db uxtb r3, r3 8008b66: 2b22 cmp r3, #34 ; 0x22 8008b68: f040 8099 bne.w 8008c9e { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8008b6c: 687b ldr r3, [r7, #4] 8008b6e: 689b ldr r3, [r3, #8] 8008b70: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8008b74: d117 bne.n 8008ba6 8008b76: 687b ldr r3, [r7, #4] 8008b78: 691b ldr r3, [r3, #16] 8008b7a: 2b00 cmp r3, #0 8008b7c: d113 bne.n 8008ba6 { pdata8bits = NULL; 8008b7e: 2300 movs r3, #0 8008b80: 617b str r3, [r7, #20] pdata16bits = (uint16_t *) huart->pRxBuffPtr; 8008b82: 687b ldr r3, [r7, #4] 8008b84: 6a9b ldr r3, [r3, #40] ; 0x28 8008b86: 613b str r3, [r7, #16] *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8008b88: 687b ldr r3, [r7, #4] 8008b8a: 681b ldr r3, [r3, #0] 8008b8c: 685b ldr r3, [r3, #4] 8008b8e: b29b uxth r3, r3 8008b90: f3c3 0308 ubfx r3, r3, #0, #9 8008b94: b29a uxth r2, r3 8008b96: 693b ldr r3, [r7, #16] 8008b98: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8008b9a: 687b ldr r3, [r7, #4] 8008b9c: 6a9b ldr r3, [r3, #40] ; 0x28 8008b9e: 1c9a adds r2, r3, #2 8008ba0: 687b ldr r3, [r7, #4] 8008ba2: 629a str r2, [r3, #40] ; 0x28 8008ba4: e026 b.n 8008bf4 } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8008ba6: 687b ldr r3, [r7, #4] 8008ba8: 6a9b ldr r3, [r3, #40] ; 0x28 8008baa: 617b str r3, [r7, #20] pdata16bits = NULL; 8008bac: 2300 movs r3, #0 8008bae: 613b str r3, [r7, #16] if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 8008bb0: 687b ldr r3, [r7, #4] 8008bb2: 689b ldr r3, [r3, #8] 8008bb4: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8008bb8: d007 beq.n 8008bca 8008bba: 687b ldr r3, [r7, #4] 8008bbc: 689b ldr r3, [r3, #8] 8008bbe: 2b00 cmp r3, #0 8008bc0: d10a bne.n 8008bd8 8008bc2: 687b ldr r3, [r7, #4] 8008bc4: 691b ldr r3, [r3, #16] 8008bc6: 2b00 cmp r3, #0 8008bc8: d106 bne.n 8008bd8 { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8008bca: 687b ldr r3, [r7, #4] 8008bcc: 681b ldr r3, [r3, #0] 8008bce: 685b ldr r3, [r3, #4] 8008bd0: b2da uxtb r2, r3 8008bd2: 697b ldr r3, [r7, #20] 8008bd4: 701a strb r2, [r3, #0] 8008bd6: e008 b.n 8008bea } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8008bd8: 687b ldr r3, [r7, #4] 8008bda: 681b ldr r3, [r3, #0] 8008bdc: 685b ldr r3, [r3, #4] 8008bde: b2db uxtb r3, r3 8008be0: f003 037f and.w r3, r3, #127 ; 0x7f 8008be4: b2da uxtb r2, r3 8008be6: 697b ldr r3, [r7, #20] 8008be8: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8008bea: 687b ldr r3, [r7, #4] 8008bec: 6a9b ldr r3, [r3, #40] ; 0x28 8008bee: 1c5a adds r2, r3, #1 8008bf0: 687b ldr r3, [r7, #4] 8008bf2: 629a str r2, [r3, #40] ; 0x28 } if (--huart->RxXferCount == 0U) 8008bf4: 687b ldr r3, [r7, #4] 8008bf6: 8ddb ldrh r3, [r3, #46] ; 0x2e 8008bf8: b29b uxth r3, r3 8008bfa: 3b01 subs r3, #1 8008bfc: b29b uxth r3, r3 8008bfe: 687a ldr r2, [r7, #4] 8008c00: 4619 mov r1, r3 8008c02: 85d1 strh r1, [r2, #46] ; 0x2e 8008c04: 2b00 cmp r3, #0 8008c06: d148 bne.n 8008c9a { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8008c08: 687b ldr r3, [r7, #4] 8008c0a: 681b ldr r3, [r3, #0] 8008c0c: 68da ldr r2, [r3, #12] 8008c0e: 687b ldr r3, [r7, #4] 8008c10: 681b ldr r3, [r3, #0] 8008c12: f022 0220 bic.w r2, r2, #32 8008c16: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8008c18: 687b ldr r3, [r7, #4] 8008c1a: 681b ldr r3, [r3, #0] 8008c1c: 68da ldr r2, [r3, #12] 8008c1e: 687b ldr r3, [r7, #4] 8008c20: 681b ldr r3, [r3, #0] 8008c22: f422 7280 bic.w r2, r2, #256 ; 0x100 8008c26: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8008c28: 687b ldr r3, [r7, #4] 8008c2a: 681b ldr r3, [r3, #0] 8008c2c: 695a ldr r2, [r3, #20] 8008c2e: 687b ldr r3, [r7, #4] 8008c30: 681b ldr r3, [r3, #0] 8008c32: f022 0201 bic.w r2, r2, #1 8008c36: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8008c38: 687b ldr r3, [r7, #4] 8008c3a: 2220 movs r2, #32 8008c3c: f883 203e strb.w r2, [r3, #62] ; 0x3e /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8008c40: 687b ldr r3, [r7, #4] 8008c42: 6b1b ldr r3, [r3, #48] ; 0x30 8008c44: 2b01 cmp r3, #1 8008c46: d123 bne.n 8008c90 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8008c48: 687b ldr r3, [r7, #4] 8008c4a: 2200 movs r2, #0 8008c4c: 631a str r2, [r3, #48] ; 0x30 /* Disable IDLE interrupt */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8008c4e: 687b ldr r3, [r7, #4] 8008c50: 681b ldr r3, [r3, #0] 8008c52: 68da ldr r2, [r3, #12] 8008c54: 687b ldr r3, [r7, #4] 8008c56: 681b ldr r3, [r3, #0] 8008c58: f022 0210 bic.w r2, r2, #16 8008c5c: 60da str r2, [r3, #12] /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 8008c5e: 687b ldr r3, [r7, #4] 8008c60: 681b ldr r3, [r3, #0] 8008c62: 681b ldr r3, [r3, #0] 8008c64: f003 0310 and.w r3, r3, #16 8008c68: 2b10 cmp r3, #16 8008c6a: d10a bne.n 8008c82 { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 8008c6c: 2300 movs r3, #0 8008c6e: 60fb str r3, [r7, #12] 8008c70: 687b ldr r3, [r7, #4] 8008c72: 681b ldr r3, [r3, #0] 8008c74: 681b ldr r3, [r3, #0] 8008c76: 60fb str r3, [r7, #12] 8008c78: 687b ldr r3, [r7, #4] 8008c7a: 681b ldr r3, [r3, #0] 8008c7c: 685b ldr r3, [r3, #4] 8008c7e: 60fb str r3, [r7, #12] 8008c80: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8008c82: 687b ldr r3, [r7, #4] 8008c84: 8d9b ldrh r3, [r3, #44] ; 0x2c 8008c86: 4619 mov r1, r3 8008c88: 6878 ldr r0, [r7, #4] 8008c8a: f7f9 fdff bl 800288c 8008c8e: e002 b.n 8008c96 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8008c90: 6878 ldr r0, [r7, #4] 8008c92: f7ff fe24 bl 80088de #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8008c96: 2300 movs r3, #0 8008c98: e002 b.n 8008ca0 } return HAL_OK; 8008c9a: 2300 movs r3, #0 8008c9c: e000 b.n 8008ca0 } else { return HAL_BUSY; 8008c9e: 2302 movs r3, #2 } } 8008ca0: 4618 mov r0, r3 8008ca2: 3718 adds r7, #24 8008ca4: 46bd mov sp, r7 8008ca6: bd80 pop {r7, pc} 08008ca8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8008ca8: b580 push {r7, lr} 8008caa: b084 sub sp, #16 8008cac: af00 add r7, sp, #0 8008cae: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8008cb0: 687b ldr r3, [r7, #4] 8008cb2: 681b ldr r3, [r3, #0] 8008cb4: 691b ldr r3, [r3, #16] 8008cb6: f423 5140 bic.w r1, r3, #12288 ; 0x3000 8008cba: 687b ldr r3, [r7, #4] 8008cbc: 68da ldr r2, [r3, #12] 8008cbe: 687b ldr r3, [r7, #4] 8008cc0: 681b ldr r3, [r3, #0] 8008cc2: 430a orrs r2, r1 8008cc4: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 8008cc6: 687b ldr r3, [r7, #4] 8008cc8: 689a ldr r2, [r3, #8] 8008cca: 687b ldr r3, [r7, #4] 8008ccc: 691b ldr r3, [r3, #16] 8008cce: 431a orrs r2, r3 8008cd0: 687b ldr r3, [r7, #4] 8008cd2: 695b ldr r3, [r3, #20] 8008cd4: 4313 orrs r3, r2 8008cd6: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 8008cd8: 687b ldr r3, [r7, #4] 8008cda: 681b ldr r3, [r3, #0] 8008cdc: 68db ldr r3, [r3, #12] 8008cde: f423 53b0 bic.w r3, r3, #5632 ; 0x1600 8008ce2: f023 030c bic.w r3, r3, #12 8008ce6: 687a ldr r2, [r7, #4] 8008ce8: 6812 ldr r2, [r2, #0] 8008cea: 68b9 ldr r1, [r7, #8] 8008cec: 430b orrs r3, r1 8008cee: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8008cf0: 687b ldr r3, [r7, #4] 8008cf2: 681b ldr r3, [r3, #0] 8008cf4: 695b ldr r3, [r3, #20] 8008cf6: f423 7140 bic.w r1, r3, #768 ; 0x300 8008cfa: 687b ldr r3, [r7, #4] 8008cfc: 699a ldr r2, [r3, #24] 8008cfe: 687b ldr r3, [r7, #4] 8008d00: 681b ldr r3, [r3, #0] 8008d02: 430a orrs r2, r1 8008d04: 615a str r2, [r3, #20] if(huart->Instance == USART1) 8008d06: 687b ldr r3, [r7, #4] 8008d08: 681b ldr r3, [r3, #0] 8008d0a: 4a2c ldr r2, [pc, #176] ; (8008dbc ) 8008d0c: 4293 cmp r3, r2 8008d0e: d103 bne.n 8008d18 { pclk = HAL_RCC_GetPCLK2Freq(); 8008d10: f7fe ff2a bl 8007b68 8008d14: 60f8 str r0, [r7, #12] 8008d16: e002 b.n 8008d1e } else { pclk = HAL_RCC_GetPCLK1Freq(); 8008d18: f7fe ff12 bl 8007b40 8008d1c: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8008d1e: 68fa ldr r2, [r7, #12] 8008d20: 4613 mov r3, r2 8008d22: 009b lsls r3, r3, #2 8008d24: 4413 add r3, r2 8008d26: 009a lsls r2, r3, #2 8008d28: 441a add r2, r3 8008d2a: 687b ldr r3, [r7, #4] 8008d2c: 685b ldr r3, [r3, #4] 8008d2e: 009b lsls r3, r3, #2 8008d30: fbb2 f3f3 udiv r3, r2, r3 8008d34: 4a22 ldr r2, [pc, #136] ; (8008dc0 ) 8008d36: fba2 2303 umull r2, r3, r2, r3 8008d3a: 095b lsrs r3, r3, #5 8008d3c: 0119 lsls r1, r3, #4 8008d3e: 68fa ldr r2, [r7, #12] 8008d40: 4613 mov r3, r2 8008d42: 009b lsls r3, r3, #2 8008d44: 4413 add r3, r2 8008d46: 009a lsls r2, r3, #2 8008d48: 441a add r2, r3 8008d4a: 687b ldr r3, [r7, #4] 8008d4c: 685b ldr r3, [r3, #4] 8008d4e: 009b lsls r3, r3, #2 8008d50: fbb2 f2f3 udiv r2, r2, r3 8008d54: 4b1a ldr r3, [pc, #104] ; (8008dc0 ) 8008d56: fba3 0302 umull r0, r3, r3, r2 8008d5a: 095b lsrs r3, r3, #5 8008d5c: 2064 movs r0, #100 ; 0x64 8008d5e: fb00 f303 mul.w r3, r0, r3 8008d62: 1ad3 subs r3, r2, r3 8008d64: 011b lsls r3, r3, #4 8008d66: 3332 adds r3, #50 ; 0x32 8008d68: 4a15 ldr r2, [pc, #84] ; (8008dc0 ) 8008d6a: fba2 2303 umull r2, r3, r2, r3 8008d6e: 095b lsrs r3, r3, #5 8008d70: f003 03f0 and.w r3, r3, #240 ; 0xf0 8008d74: 4419 add r1, r3 8008d76: 68fa ldr r2, [r7, #12] 8008d78: 4613 mov r3, r2 8008d7a: 009b lsls r3, r3, #2 8008d7c: 4413 add r3, r2 8008d7e: 009a lsls r2, r3, #2 8008d80: 441a add r2, r3 8008d82: 687b ldr r3, [r7, #4] 8008d84: 685b ldr r3, [r3, #4] 8008d86: 009b lsls r3, r3, #2 8008d88: fbb2 f2f3 udiv r2, r2, r3 8008d8c: 4b0c ldr r3, [pc, #48] ; (8008dc0 ) 8008d8e: fba3 0302 umull r0, r3, r3, r2 8008d92: 095b lsrs r3, r3, #5 8008d94: 2064 movs r0, #100 ; 0x64 8008d96: fb00 f303 mul.w r3, r0, r3 8008d9a: 1ad3 subs r3, r2, r3 8008d9c: 011b lsls r3, r3, #4 8008d9e: 3332 adds r3, #50 ; 0x32 8008da0: 4a07 ldr r2, [pc, #28] ; (8008dc0 ) 8008da2: fba2 2303 umull r2, r3, r2, r3 8008da6: 095b lsrs r3, r3, #5 8008da8: f003 020f and.w r2, r3, #15 8008dac: 687b ldr r3, [r7, #4] 8008dae: 681b ldr r3, [r3, #0] 8008db0: 440a add r2, r1 8008db2: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 8008db4: bf00 nop 8008db6: 3710 adds r7, #16 8008db8: 46bd mov sp, r7 8008dba: bd80 pop {r7, pc} 8008dbc: 40013800 .word 0x40013800 8008dc0: 51eb851f .word 0x51eb851f 08008dc4 <__errno>: 8008dc4: 4b01 ldr r3, [pc, #4] ; (8008dcc <__errno+0x8>) 8008dc6: 6818 ldr r0, [r3, #0] 8008dc8: 4770 bx lr 8008dca: bf00 nop 8008dcc: 20000014 .word 0x20000014 08008dd0 : 8008dd0: b538 push {r3, r4, r5, lr} 8008dd2: 4b0b ldr r3, [pc, #44] ; (8008e00 ) 8008dd4: 4604 mov r4, r0 8008dd6: 681d ldr r5, [r3, #0] 8008dd8: 6beb ldr r3, [r5, #60] ; 0x3c 8008dda: b953 cbnz r3, 8008df2 8008ddc: 2024 movs r0, #36 ; 0x24 8008dde: f000 f9f7 bl 80091d0 8008de2: 4602 mov r2, r0 8008de4: 63e8 str r0, [r5, #60] ; 0x3c 8008de6: b920 cbnz r0, 8008df2 8008de8: 2139 movs r1, #57 ; 0x39 8008dea: 4b06 ldr r3, [pc, #24] ; (8008e04 ) 8008dec: 4806 ldr r0, [pc, #24] ; (8008e08 ) 8008dee: f001 fb01 bl 800a3f4 <__assert_func> 8008df2: 4620 mov r0, r4 8008df4: 6be9 ldr r1, [r5, #60] ; 0x3c 8008df6: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8008dfa: f000 b807 b.w 8008e0c 8008dfe: bf00 nop 8008e00: 20000014 .word 0x20000014 8008e04: 0800d2ac .word 0x0800d2ac 8008e08: 0800d2c3 .word 0x0800d2c3 08008e0c : 8008e0c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8008e10: e9d0 6700 ldrd r6, r7, [r0] 8008e14: 460c mov r4, r1 8008e16: 2300 movs r3, #0 8008e18: 4630 mov r0, r6 8008e1a: 4639 mov r1, r7 8008e1c: 4a4e ldr r2, [pc, #312] ; (8008f58 ) 8008e1e: f7f8 f9f3 bl 8001208 <__aeabi_ldivmod> 8008e22: 4639 mov r1, r7 8008e24: 4605 mov r5, r0 8008e26: 2300 movs r3, #0 8008e28: 4630 mov r0, r6 8008e2a: 4a4b ldr r2, [pc, #300] ; (8008f58 ) 8008e2c: f7f8 f9ec bl 8001208 <__aeabi_ldivmod> 8008e30: f44f 6061 mov.w r0, #3600 ; 0xe10 8008e34: 2a00 cmp r2, #0 8008e36: bfbc itt lt 8008e38: f502 32a8 addlt.w r2, r2, #86016 ; 0x15000 8008e3c: f502 72c0 addlt.w r2, r2, #384 ; 0x180 8008e40: fbb2 f1f0 udiv r1, r2, r0 8008e44: fb00 2211 mls r2, r0, r1, r2 8008e48: f04f 003c mov.w r0, #60 ; 0x3c 8008e4c: 60a1 str r1, [r4, #8] 8008e4e: fbb2 f1f0 udiv r1, r2, r0 8008e52: fb00 2211 mls r2, r0, r1, r2 8008e56: 6061 str r1, [r4, #4] 8008e58: f04f 0107 mov.w r1, #7 8008e5c: f505 232f add.w r3, r5, #716800 ; 0xaf000 8008e60: bfac ite ge 8008e62: f603 236c addwge r3, r3, #2668 ; 0xa6c 8008e66: f603 236b addwlt r3, r3, #2667 ; 0xa6b 8008e6a: 6022 str r2, [r4, #0] 8008e6c: 1cda adds r2, r3, #3 8008e6e: fb92 f1f1 sdiv r1, r2, r1 8008e72: ebc1 01c1 rsb r1, r1, r1, lsl #3 8008e76: 1a52 subs r2, r2, r1 8008e78: bf48 it mi 8008e7a: 3207 addmi r2, #7 8008e7c: 2b00 cmp r3, #0 8008e7e: 4d37 ldr r5, [pc, #220] ; (8008f5c ) 8008e80: 61a2 str r2, [r4, #24] 8008e82: bfbd ittte lt 8008e84: f5a3 320e sublt.w r2, r3, #145408 ; 0x23800 8008e88: f5a2 722c sublt.w r2, r2, #688 ; 0x2b0 8008e8c: fb92 f5f5 sdivlt r5, r2, r5 8008e90: fb93 f5f5 sdivge r5, r3, r5 8008e94: 4832 ldr r0, [pc, #200] ; (8008f60 ) 8008e96: f648 62ac movw r2, #36524 ; 0x8eac 8008e9a: fb00 3005 mla r0, r0, r5, r3 8008e9e: f240 53b4 movw r3, #1460 ; 0x5b4 8008ea2: fbb0 f2f2 udiv r2, r0, r2 8008ea6: fbb0 f1f3 udiv r1, r0, r3 8008eaa: 4402 add r2, r0 8008eac: 1a52 subs r2, r2, r1 8008eae: 492d ldr r1, [pc, #180] ; (8008f64 ) 8008eb0: f240 1c6d movw ip, #365 ; 0x16d 8008eb4: fbb0 f1f1 udiv r1, r0, r1 8008eb8: 1a52 subs r2, r2, r1 8008eba: fbb2 f1fc udiv r1, r2, ip 8008ebe: 2764 movs r7, #100 ; 0x64 8008ec0: fbb2 f3f3 udiv r3, r2, r3 8008ec4: fbb1 f6f7 udiv r6, r1, r7 8008ec8: 2299 movs r2, #153 ; 0x99 8008eca: 1af3 subs r3, r6, r3 8008ecc: 4403 add r3, r0 8008ece: fb0c 3311 mls r3, ip, r1, r3 8008ed2: eb03 0e83 add.w lr, r3, r3, lsl #2 8008ed6: f10e 0e02 add.w lr, lr, #2 8008eda: fbbe f0f2 udiv r0, lr, r2 8008ede: f04f 0805 mov.w r8, #5 8008ee2: 4342 muls r2, r0 8008ee4: 3202 adds r2, #2 8008ee6: fbb2 f2f8 udiv r2, r2, r8 8008eea: f103 0c01 add.w ip, r3, #1 8008eee: ebac 0c02 sub.w ip, ip, r2 8008ef2: f240 52f9 movw r2, #1529 ; 0x5f9 8008ef6: 4596 cmp lr, r2 8008ef8: bf94 ite ls 8008efa: 2202 movls r2, #2 8008efc: f06f 0209 mvnhi.w r2, #9 8008f00: 4410 add r0, r2 8008f02: f44f 72c8 mov.w r2, #400 ; 0x190 8008f06: fb02 1505 mla r5, r2, r5, r1 8008f0a: 2801 cmp r0, #1 8008f0c: bf98 it ls 8008f0e: 3501 addls r5, #1 8008f10: f5b3 7f99 cmp.w r3, #306 ; 0x132 8008f14: d30d bcc.n 8008f32 8008f16: f5a3 7399 sub.w r3, r3, #306 ; 0x132 8008f1a: 61e3 str r3, [r4, #28] 8008f1c: 2300 movs r3, #0 8008f1e: f2a5 756c subw r5, r5, #1900 ; 0x76c 8008f22: e9c4 0504 strd r0, r5, [r4, #16] 8008f26: f8c4 c00c str.w ip, [r4, #12] 8008f2a: 4620 mov r0, r4 8008f2c: 6223 str r3, [r4, #32] 8008f2e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8008f32: 078a lsls r2, r1, #30 8008f34: d102 bne.n 8008f3c 8008f36: fb07 1616 mls r6, r7, r6, r1 8008f3a: b95e cbnz r6, 8008f54 8008f3c: f44f 72c8 mov.w r2, #400 ; 0x190 8008f40: fbb1 f6f2 udiv r6, r1, r2 8008f44: fb02 1216 mls r2, r2, r6, r1 8008f48: fab2 f282 clz r2, r2 8008f4c: 0952 lsrs r2, r2, #5 8008f4e: 333b adds r3, #59 ; 0x3b 8008f50: 4413 add r3, r2 8008f52: e7e2 b.n 8008f1a 8008f54: 2201 movs r2, #1 8008f56: e7fa b.n 8008f4e 8008f58: 00015180 .word 0x00015180 8008f5c: 00023ab1 .word 0x00023ab1 8008f60: fffdc54f .word 0xfffdc54f 8008f64: 00023ab0 .word 0x00023ab0 08008f68 <__libc_init_array>: 8008f68: b570 push {r4, r5, r6, lr} 8008f6a: 2600 movs r6, #0 8008f6c: 4d0c ldr r5, [pc, #48] ; (8008fa0 <__libc_init_array+0x38>) 8008f6e: 4c0d ldr r4, [pc, #52] ; (8008fa4 <__libc_init_array+0x3c>) 8008f70: 1b64 subs r4, r4, r5 8008f72: 10a4 asrs r4, r4, #2 8008f74: 42a6 cmp r6, r4 8008f76: d109 bne.n 8008f8c <__libc_init_array+0x24> 8008f78: f003 fe7a bl 800cc70 <_init> 8008f7c: 2600 movs r6, #0 8008f7e: 4d0a ldr r5, [pc, #40] ; (8008fa8 <__libc_init_array+0x40>) 8008f80: 4c0a ldr r4, [pc, #40] ; (8008fac <__libc_init_array+0x44>) 8008f82: 1b64 subs r4, r4, r5 8008f84: 10a4 asrs r4, r4, #2 8008f86: 42a6 cmp r6, r4 8008f88: d105 bne.n 8008f96 <__libc_init_array+0x2e> 8008f8a: bd70 pop {r4, r5, r6, pc} 8008f8c: f855 3b04 ldr.w r3, [r5], #4 8008f90: 4798 blx r3 8008f92: 3601 adds r6, #1 8008f94: e7ee b.n 8008f74 <__libc_init_array+0xc> 8008f96: f855 3b04 ldr.w r3, [r5], #4 8008f9a: 4798 blx r3 8008f9c: 3601 adds r6, #1 8008f9e: e7f2 b.n 8008f86 <__libc_init_array+0x1e> 8008fa0: 0800d7fc .word 0x0800d7fc 8008fa4: 0800d7fc .word 0x0800d7fc 8008fa8: 0800d7fc .word 0x0800d7fc 8008fac: 0800d800 .word 0x0800d800 08008fb0 : 8008fb0: b538 push {r3, r4, r5, lr} 8008fb2: 4b0b ldr r3, [pc, #44] ; (8008fe0 ) 8008fb4: 4604 mov r4, r0 8008fb6: 681d ldr r5, [r3, #0] 8008fb8: 6beb ldr r3, [r5, #60] ; 0x3c 8008fba: b953 cbnz r3, 8008fd2 8008fbc: 2024 movs r0, #36 ; 0x24 8008fbe: f000 f907 bl 80091d0 8008fc2: 4602 mov r2, r0 8008fc4: 63e8 str r0, [r5, #60] ; 0x3c 8008fc6: b920 cbnz r0, 8008fd2 8008fc8: 2132 movs r1, #50 ; 0x32 8008fca: 4b06 ldr r3, [pc, #24] ; (8008fe4 ) 8008fcc: 4806 ldr r0, [pc, #24] ; (8008fe8 ) 8008fce: f001 fa11 bl 800a3f4 <__assert_func> 8008fd2: 4620 mov r0, r4 8008fd4: 6be9 ldr r1, [r5, #60] ; 0x3c 8008fd6: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8008fda: f000 b807 b.w 8008fec 8008fde: bf00 nop 8008fe0: 20000014 .word 0x20000014 8008fe4: 0800d2ac .word 0x0800d2ac 8008fe8: 0800d324 .word 0x0800d324 08008fec : 8008fec: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8008ff0: 460c mov r4, r1 8008ff2: 4680 mov r8, r0 8008ff4: f002 faa0 bl 800b538 <__gettzinfo> 8008ff8: 4621 mov r1, r4 8008ffa: 4605 mov r5, r0 8008ffc: 4640 mov r0, r8 8008ffe: f7ff ff05 bl 8008e0c 8009002: 6943 ldr r3, [r0, #20] 8009004: 4604 mov r4, r0 8009006: 0799 lsls r1, r3, #30 8009008: f203 776c addw r7, r3, #1900 ; 0x76c 800900c: d105 bne.n 800901a 800900e: 2264 movs r2, #100 ; 0x64 8009010: fb97 f3f2 sdiv r3, r7, r2 8009014: fb02 7313 mls r3, r2, r3, r7 8009018: bb73 cbnz r3, 8009078 800901a: f44f 73c8 mov.w r3, #400 ; 0x190 800901e: fb97 f6f3 sdiv r6, r7, r3 8009022: fb03 7616 mls r6, r3, r6, r7 8009026: fab6 f386 clz r3, r6 800902a: 095b lsrs r3, r3, #5 800902c: 2230 movs r2, #48 ; 0x30 800902e: 4e66 ldr r6, [pc, #408] ; (80091c8 ) 8009030: fb02 6603 mla r6, r2, r3, r6 8009034: f000 ff8a bl 8009f4c <__tz_lock> 8009038: f000 ff94 bl 8009f64 <_tzset_unlocked> 800903c: 4b63 ldr r3, [pc, #396] ; (80091cc ) 800903e: 681b ldr r3, [r3, #0] 8009040: b34b cbz r3, 8009096 8009042: 686b ldr r3, [r5, #4] 8009044: 42bb cmp r3, r7 8009046: d119 bne.n 800907c 8009048: e9d8 2300 ldrd r2, r3, [r8] 800904c: e9d5 0108 ldrd r0, r1, [r5, #32] 8009050: 682f ldr r7, [r5, #0] 8009052: b9df cbnz r7, 800908c 8009054: 4282 cmp r2, r0 8009056: eb73 0101 sbcs.w r1, r3, r1 800905a: da23 bge.n 80090a4 800905c: e9d5 0112 ldrd r0, r1, [r5, #72] ; 0x48 8009060: 4282 cmp r2, r0 8009062: eb73 0701 sbcs.w r7, r3, r1 8009066: bfb4 ite lt 8009068: 2701 movlt r7, #1 800906a: 2700 movge r7, #0 800906c: 4282 cmp r2, r0 800906e: 418b sbcs r3, r1 8009070: 6227 str r7, [r4, #32] 8009072: db19 blt.n 80090a8 8009074: 6aab ldr r3, [r5, #40] ; 0x28 8009076: e018 b.n 80090aa 8009078: 2301 movs r3, #1 800907a: e7d7 b.n 800902c 800907c: 4638 mov r0, r7 800907e: f000 febb bl 8009df8 <__tzcalc_limits> 8009082: 2800 cmp r0, #0 8009084: d1e0 bne.n 8009048 8009086: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff 800908a: e004 b.n 8009096 800908c: 4282 cmp r2, r0 800908e: eb73 0101 sbcs.w r1, r3, r1 8009092: da02 bge.n 800909a 8009094: 2300 movs r3, #0 8009096: 6223 str r3, [r4, #32] 8009098: e7ec b.n 8009074 800909a: e9d5 0112 ldrd r0, r1, [r5, #72] ; 0x48 800909e: 4282 cmp r2, r0 80090a0: 418b sbcs r3, r1 80090a2: daf7 bge.n 8009094 80090a4: 2301 movs r3, #1 80090a6: 6223 str r3, [r4, #32] 80090a8: 6d2b ldr r3, [r5, #80] ; 0x50 80090aa: f44f 6261 mov.w r2, #3600 ; 0xe10 80090ae: fb93 f5f2 sdiv r5, r3, r2 80090b2: 203c movs r0, #60 ; 0x3c 80090b4: fb02 3315 mls r3, r2, r5, r3 80090b8: fb93 f2f0 sdiv r2, r3, r0 80090bc: fb00 3012 mls r0, r0, r2, r3 80090c0: 6861 ldr r1, [r4, #4] 80090c2: 6823 ldr r3, [r4, #0] 80090c4: 1a89 subs r1, r1, r2 80090c6: 68a2 ldr r2, [r4, #8] 80090c8: 1a1b subs r3, r3, r0 80090ca: 1b52 subs r2, r2, r5 80090cc: 2b3b cmp r3, #59 ; 0x3b 80090ce: 6023 str r3, [r4, #0] 80090d0: 6061 str r1, [r4, #4] 80090d2: 60a2 str r2, [r4, #8] 80090d4: dd34 ble.n 8009140 80090d6: 3101 adds r1, #1 80090d8: 6061 str r1, [r4, #4] 80090da: 3b3c subs r3, #60 ; 0x3c 80090dc: 6023 str r3, [r4, #0] 80090de: 6863 ldr r3, [r4, #4] 80090e0: 2b3b cmp r3, #59 ; 0x3b 80090e2: dd33 ble.n 800914c 80090e4: 3201 adds r2, #1 80090e6: 60a2 str r2, [r4, #8] 80090e8: 3b3c subs r3, #60 ; 0x3c 80090ea: 6063 str r3, [r4, #4] 80090ec: 68a3 ldr r3, [r4, #8] 80090ee: 2b17 cmp r3, #23 80090f0: dd32 ble.n 8009158 80090f2: 69e2 ldr r2, [r4, #28] 80090f4: 3b18 subs r3, #24 80090f6: 3201 adds r2, #1 80090f8: 61e2 str r2, [r4, #28] 80090fa: 69a2 ldr r2, [r4, #24] 80090fc: 60a3 str r3, [r4, #8] 80090fe: 3201 adds r2, #1 8009100: 2a06 cmp r2, #6 8009102: bfc8 it gt 8009104: 2200 movgt r2, #0 8009106: 61a2 str r2, [r4, #24] 8009108: 68e2 ldr r2, [r4, #12] 800910a: 6923 ldr r3, [r4, #16] 800910c: 3201 adds r2, #1 800910e: 60e2 str r2, [r4, #12] 8009110: f856 1023 ldr.w r1, [r6, r3, lsl #2] 8009114: 428a cmp r2, r1 8009116: dd0e ble.n 8009136 8009118: 2b0b cmp r3, #11 800911a: eba2 0201 sub.w r2, r2, r1 800911e: 60e2 str r2, [r4, #12] 8009120: f103 0201 add.w r2, r3, #1 8009124: bf05 ittet eq 8009126: 2200 moveq r2, #0 8009128: 6963 ldreq r3, [r4, #20] 800912a: 6122 strne r2, [r4, #16] 800912c: 3301 addeq r3, #1 800912e: bf02 ittt eq 8009130: 6122 streq r2, [r4, #16] 8009132: 6163 streq r3, [r4, #20] 8009134: 61e2 streq r2, [r4, #28] 8009136: f000 ff0f bl 8009f58 <__tz_unlock> 800913a: 4620 mov r0, r4 800913c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8009140: 2b00 cmp r3, #0 8009142: dacc bge.n 80090de 8009144: 3901 subs r1, #1 8009146: 6061 str r1, [r4, #4] 8009148: 333c adds r3, #60 ; 0x3c 800914a: e7c7 b.n 80090dc 800914c: 2b00 cmp r3, #0 800914e: dacd bge.n 80090ec 8009150: 3a01 subs r2, #1 8009152: 60a2 str r2, [r4, #8] 8009154: 333c adds r3, #60 ; 0x3c 8009156: e7c8 b.n 80090ea 8009158: 2b00 cmp r3, #0 800915a: daec bge.n 8009136 800915c: 69e2 ldr r2, [r4, #28] 800915e: 3318 adds r3, #24 8009160: 3a01 subs r2, #1 8009162: 61e2 str r2, [r4, #28] 8009164: 69a2 ldr r2, [r4, #24] 8009166: 60a3 str r3, [r4, #8] 8009168: 3a01 subs r2, #1 800916a: bf48 it mi 800916c: 2206 movmi r2, #6 800916e: 61a2 str r2, [r4, #24] 8009170: 68e2 ldr r2, [r4, #12] 8009172: 3a01 subs r2, #1 8009174: 60e2 str r2, [r4, #12] 8009176: 2a00 cmp r2, #0 8009178: d1dd bne.n 8009136 800917a: 6923 ldr r3, [r4, #16] 800917c: 3b01 subs r3, #1 800917e: d405 bmi.n 800918c 8009180: 6123 str r3, [r4, #16] 8009182: 6923 ldr r3, [r4, #16] 8009184: f856 3023 ldr.w r3, [r6, r3, lsl #2] 8009188: 60e3 str r3, [r4, #12] 800918a: e7d4 b.n 8009136 800918c: 230b movs r3, #11 800918e: 6123 str r3, [r4, #16] 8009190: 6963 ldr r3, [r4, #20] 8009192: 1e5a subs r2, r3, #1 8009194: f203 736b addw r3, r3, #1899 ; 0x76b 8009198: 6162 str r2, [r4, #20] 800919a: 079a lsls r2, r3, #30 800919c: d105 bne.n 80091aa 800919e: 2164 movs r1, #100 ; 0x64 80091a0: fb93 f2f1 sdiv r2, r3, r1 80091a4: fb01 3212 mls r2, r1, r2, r3 80091a8: b962 cbnz r2, 80091c4 80091aa: f44f 72c8 mov.w r2, #400 ; 0x190 80091ae: fb93 f1f2 sdiv r1, r3, r2 80091b2: fb02 3311 mls r3, r2, r1, r3 80091b6: fab3 f383 clz r3, r3 80091ba: 095b lsrs r3, r3, #5 80091bc: f503 73b6 add.w r3, r3, #364 ; 0x16c 80091c0: 61e3 str r3, [r4, #28] 80091c2: e7de b.n 8009182 80091c4: 2301 movs r3, #1 80091c6: e7f9 b.n 80091bc 80091c8: 0800d380 .word 0x0800d380 80091cc: 200033bc .word 0x200033bc 080091d0 : 80091d0: 4b02 ldr r3, [pc, #8] ; (80091dc ) 80091d2: 4601 mov r1, r0 80091d4: 6818 ldr r0, [r3, #0] 80091d6: f000 b889 b.w 80092ec <_malloc_r> 80091da: bf00 nop 80091dc: 20000014 .word 0x20000014 080091e0 : 80091e0: 4b02 ldr r3, [pc, #8] ; (80091ec ) 80091e2: 4601 mov r1, r0 80091e4: 6818 ldr r0, [r3, #0] 80091e6: f000 b819 b.w 800921c <_free_r> 80091ea: bf00 nop 80091ec: 20000014 .word 0x20000014 080091f0 : 80091f0: 440a add r2, r1 80091f2: 4291 cmp r1, r2 80091f4: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff 80091f8: d100 bne.n 80091fc 80091fa: 4770 bx lr 80091fc: b510 push {r4, lr} 80091fe: f811 4b01 ldrb.w r4, [r1], #1 8009202: 4291 cmp r1, r2 8009204: f803 4f01 strb.w r4, [r3, #1]! 8009208: d1f9 bne.n 80091fe 800920a: bd10 pop {r4, pc} 0800920c : 800920c: 4603 mov r3, r0 800920e: 4402 add r2, r0 8009210: 4293 cmp r3, r2 8009212: d100 bne.n 8009216 8009214: 4770 bx lr 8009216: f803 1b01 strb.w r1, [r3], #1 800921a: e7f9 b.n 8009210 0800921c <_free_r>: 800921c: b538 push {r3, r4, r5, lr} 800921e: 4605 mov r5, r0 8009220: 2900 cmp r1, #0 8009222: d040 beq.n 80092a6 <_free_r+0x8a> 8009224: f851 3c04 ldr.w r3, [r1, #-4] 8009228: 1f0c subs r4, r1, #4 800922a: 2b00 cmp r3, #0 800922c: bfb8 it lt 800922e: 18e4 addlt r4, r4, r3 8009230: f002 fa02 bl 800b638 <__malloc_lock> 8009234: 4a1c ldr r2, [pc, #112] ; (80092a8 <_free_r+0x8c>) 8009236: 6813 ldr r3, [r2, #0] 8009238: b933 cbnz r3, 8009248 <_free_r+0x2c> 800923a: 6063 str r3, [r4, #4] 800923c: 6014 str r4, [r2, #0] 800923e: 4628 mov r0, r5 8009240: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8009244: f002 b9fe b.w 800b644 <__malloc_unlock> 8009248: 42a3 cmp r3, r4 800924a: d908 bls.n 800925e <_free_r+0x42> 800924c: 6820 ldr r0, [r4, #0] 800924e: 1821 adds r1, r4, r0 8009250: 428b cmp r3, r1 8009252: bf01 itttt eq 8009254: 6819 ldreq r1, [r3, #0] 8009256: 685b ldreq r3, [r3, #4] 8009258: 1809 addeq r1, r1, r0 800925a: 6021 streq r1, [r4, #0] 800925c: e7ed b.n 800923a <_free_r+0x1e> 800925e: 461a mov r2, r3 8009260: 685b ldr r3, [r3, #4] 8009262: b10b cbz r3, 8009268 <_free_r+0x4c> 8009264: 42a3 cmp r3, r4 8009266: d9fa bls.n 800925e <_free_r+0x42> 8009268: 6811 ldr r1, [r2, #0] 800926a: 1850 adds r0, r2, r1 800926c: 42a0 cmp r0, r4 800926e: d10b bne.n 8009288 <_free_r+0x6c> 8009270: 6820 ldr r0, [r4, #0] 8009272: 4401 add r1, r0 8009274: 1850 adds r0, r2, r1 8009276: 4283 cmp r3, r0 8009278: 6011 str r1, [r2, #0] 800927a: d1e0 bne.n 800923e <_free_r+0x22> 800927c: 6818 ldr r0, [r3, #0] 800927e: 685b ldr r3, [r3, #4] 8009280: 4401 add r1, r0 8009282: 6011 str r1, [r2, #0] 8009284: 6053 str r3, [r2, #4] 8009286: e7da b.n 800923e <_free_r+0x22> 8009288: d902 bls.n 8009290 <_free_r+0x74> 800928a: 230c movs r3, #12 800928c: 602b str r3, [r5, #0] 800928e: e7d6 b.n 800923e <_free_r+0x22> 8009290: 6820 ldr r0, [r4, #0] 8009292: 1821 adds r1, r4, r0 8009294: 428b cmp r3, r1 8009296: bf01 itttt eq 8009298: 6819 ldreq r1, [r3, #0] 800929a: 685b ldreq r3, [r3, #4] 800929c: 1809 addeq r1, r1, r0 800929e: 6021 streq r1, [r4, #0] 80092a0: 6063 str r3, [r4, #4] 80092a2: 6054 str r4, [r2, #4] 80092a4: e7cb b.n 800923e <_free_r+0x22> 80092a6: bd38 pop {r3, r4, r5, pc} 80092a8: 20003398 .word 0x20003398 080092ac : 80092ac: b570 push {r4, r5, r6, lr} 80092ae: 4e0e ldr r6, [pc, #56] ; (80092e8 ) 80092b0: 460c mov r4, r1 80092b2: 6831 ldr r1, [r6, #0] 80092b4: 4605 mov r5, r0 80092b6: b911 cbnz r1, 80092be 80092b8: f000 fd7a bl 8009db0 <_sbrk_r> 80092bc: 6030 str r0, [r6, #0] 80092be: 4621 mov r1, r4 80092c0: 4628 mov r0, r5 80092c2: f000 fd75 bl 8009db0 <_sbrk_r> 80092c6: 1c43 adds r3, r0, #1 80092c8: d00a beq.n 80092e0 80092ca: 1cc4 adds r4, r0, #3 80092cc: f024 0403 bic.w r4, r4, #3 80092d0: 42a0 cmp r0, r4 80092d2: d007 beq.n 80092e4 80092d4: 1a21 subs r1, r4, r0 80092d6: 4628 mov r0, r5 80092d8: f000 fd6a bl 8009db0 <_sbrk_r> 80092dc: 3001 adds r0, #1 80092de: d101 bne.n 80092e4 80092e0: f04f 34ff mov.w r4, #4294967295 ; 0xffffffff 80092e4: 4620 mov r0, r4 80092e6: bd70 pop {r4, r5, r6, pc} 80092e8: 2000339c .word 0x2000339c 080092ec <_malloc_r>: 80092ec: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80092f0: 1ccd adds r5, r1, #3 80092f2: f025 0503 bic.w r5, r5, #3 80092f6: 3508 adds r5, #8 80092f8: 2d0c cmp r5, #12 80092fa: bf38 it cc 80092fc: 250c movcc r5, #12 80092fe: 2d00 cmp r5, #0 8009300: 4607 mov r7, r0 8009302: db01 blt.n 8009308 <_malloc_r+0x1c> 8009304: 42a9 cmp r1, r5 8009306: d905 bls.n 8009314 <_malloc_r+0x28> 8009308: 230c movs r3, #12 800930a: 2600 movs r6, #0 800930c: 603b str r3, [r7, #0] 800930e: 4630 mov r0, r6 8009310: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8009314: 4e2e ldr r6, [pc, #184] ; (80093d0 <_malloc_r+0xe4>) 8009316: f002 f98f bl 800b638 <__malloc_lock> 800931a: 6833 ldr r3, [r6, #0] 800931c: 461c mov r4, r3 800931e: bb34 cbnz r4, 800936e <_malloc_r+0x82> 8009320: 4629 mov r1, r5 8009322: 4638 mov r0, r7 8009324: f7ff ffc2 bl 80092ac 8009328: 1c43 adds r3, r0, #1 800932a: 4604 mov r4, r0 800932c: d14d bne.n 80093ca <_malloc_r+0xde> 800932e: 6834 ldr r4, [r6, #0] 8009330: 4626 mov r6, r4 8009332: 2e00 cmp r6, #0 8009334: d140 bne.n 80093b8 <_malloc_r+0xcc> 8009336: 6823 ldr r3, [r4, #0] 8009338: 4631 mov r1, r6 800933a: 4638 mov r0, r7 800933c: eb04 0803 add.w r8, r4, r3 8009340: f000 fd36 bl 8009db0 <_sbrk_r> 8009344: 4580 cmp r8, r0 8009346: d13a bne.n 80093be <_malloc_r+0xd2> 8009348: 6821 ldr r1, [r4, #0] 800934a: 3503 adds r5, #3 800934c: 1a6d subs r5, r5, r1 800934e: f025 0503 bic.w r5, r5, #3 8009352: 3508 adds r5, #8 8009354: 2d0c cmp r5, #12 8009356: bf38 it cc 8009358: 250c movcc r5, #12 800935a: 4638 mov r0, r7 800935c: 4629 mov r1, r5 800935e: f7ff ffa5 bl 80092ac 8009362: 3001 adds r0, #1 8009364: d02b beq.n 80093be <_malloc_r+0xd2> 8009366: 6823 ldr r3, [r4, #0] 8009368: 442b add r3, r5 800936a: 6023 str r3, [r4, #0] 800936c: e00e b.n 800938c <_malloc_r+0xa0> 800936e: 6822 ldr r2, [r4, #0] 8009370: 1b52 subs r2, r2, r5 8009372: d41e bmi.n 80093b2 <_malloc_r+0xc6> 8009374: 2a0b cmp r2, #11 8009376: d916 bls.n 80093a6 <_malloc_r+0xba> 8009378: 1961 adds r1, r4, r5 800937a: 42a3 cmp r3, r4 800937c: 6025 str r5, [r4, #0] 800937e: bf18 it ne 8009380: 6059 strne r1, [r3, #4] 8009382: 6863 ldr r3, [r4, #4] 8009384: bf08 it eq 8009386: 6031 streq r1, [r6, #0] 8009388: 5162 str r2, [r4, r5] 800938a: 604b str r3, [r1, #4] 800938c: 4638 mov r0, r7 800938e: f104 060b add.w r6, r4, #11 8009392: f002 f957 bl 800b644 <__malloc_unlock> 8009396: f026 0607 bic.w r6, r6, #7 800939a: 1d23 adds r3, r4, #4 800939c: 1af2 subs r2, r6, r3 800939e: d0b6 beq.n 800930e <_malloc_r+0x22> 80093a0: 1b9b subs r3, r3, r6 80093a2: 50a3 str r3, [r4, r2] 80093a4: e7b3 b.n 800930e <_malloc_r+0x22> 80093a6: 6862 ldr r2, [r4, #4] 80093a8: 42a3 cmp r3, r4 80093aa: bf0c ite eq 80093ac: 6032 streq r2, [r6, #0] 80093ae: 605a strne r2, [r3, #4] 80093b0: e7ec b.n 800938c <_malloc_r+0xa0> 80093b2: 4623 mov r3, r4 80093b4: 6864 ldr r4, [r4, #4] 80093b6: e7b2 b.n 800931e <_malloc_r+0x32> 80093b8: 4634 mov r4, r6 80093ba: 6876 ldr r6, [r6, #4] 80093bc: e7b9 b.n 8009332 <_malloc_r+0x46> 80093be: 230c movs r3, #12 80093c0: 4638 mov r0, r7 80093c2: 603b str r3, [r7, #0] 80093c4: f002 f93e bl 800b644 <__malloc_unlock> 80093c8: e7a1 b.n 800930e <_malloc_r+0x22> 80093ca: 6025 str r5, [r4, #0] 80093cc: e7de b.n 800938c <_malloc_r+0xa0> 80093ce: bf00 nop 80093d0: 20003398 .word 0x20003398 080093d4 <__cvt>: 80093d4: 2b00 cmp r3, #0 80093d6: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80093da: 461f mov r7, r3 80093dc: bfbb ittet lt 80093de: f103 4300 addlt.w r3, r3, #2147483648 ; 0x80000000 80093e2: 461f movlt r7, r3 80093e4: 2300 movge r3, #0 80093e6: 232d movlt r3, #45 ; 0x2d 80093e8: b088 sub sp, #32 80093ea: 4614 mov r4, r2 80093ec: 9a12 ldr r2, [sp, #72] ; 0x48 80093ee: 9d10 ldr r5, [sp, #64] ; 0x40 80093f0: 7013 strb r3, [r2, #0] 80093f2: 9b14 ldr r3, [sp, #80] ; 0x50 80093f4: f8dd a04c ldr.w sl, [sp, #76] ; 0x4c 80093f8: f023 0820 bic.w r8, r3, #32 80093fc: f1b8 0f46 cmp.w r8, #70 ; 0x46 8009400: d005 beq.n 800940e <__cvt+0x3a> 8009402: f1b8 0f45 cmp.w r8, #69 ; 0x45 8009406: d100 bne.n 800940a <__cvt+0x36> 8009408: 3501 adds r5, #1 800940a: 2302 movs r3, #2 800940c: e000 b.n 8009410 <__cvt+0x3c> 800940e: 2303 movs r3, #3 8009410: aa07 add r2, sp, #28 8009412: 9204 str r2, [sp, #16] 8009414: aa06 add r2, sp, #24 8009416: e9cd a202 strd sl, r2, [sp, #8] 800941a: e9cd 3500 strd r3, r5, [sp] 800941e: 4622 mov r2, r4 8009420: 463b mov r3, r7 8009422: f001 f891 bl 800a548 <_dtoa_r> 8009426: f1b8 0f47 cmp.w r8, #71 ; 0x47 800942a: 4606 mov r6, r0 800942c: d102 bne.n 8009434 <__cvt+0x60> 800942e: 9b11 ldr r3, [sp, #68] ; 0x44 8009430: 07db lsls r3, r3, #31 8009432: d522 bpl.n 800947a <__cvt+0xa6> 8009434: f1b8 0f46 cmp.w r8, #70 ; 0x46 8009438: eb06 0905 add.w r9, r6, r5 800943c: d110 bne.n 8009460 <__cvt+0x8c> 800943e: 7833 ldrb r3, [r6, #0] 8009440: 2b30 cmp r3, #48 ; 0x30 8009442: d10a bne.n 800945a <__cvt+0x86> 8009444: 2200 movs r2, #0 8009446: 2300 movs r3, #0 8009448: 4620 mov r0, r4 800944a: 4639 mov r1, r7 800944c: f7f7 fb22 bl 8000a94 <__aeabi_dcmpeq> 8009450: b918 cbnz r0, 800945a <__cvt+0x86> 8009452: f1c5 0501 rsb r5, r5, #1 8009456: f8ca 5000 str.w r5, [sl] 800945a: f8da 3000 ldr.w r3, [sl] 800945e: 4499 add r9, r3 8009460: 2200 movs r2, #0 8009462: 2300 movs r3, #0 8009464: 4620 mov r0, r4 8009466: 4639 mov r1, r7 8009468: f7f7 fb14 bl 8000a94 <__aeabi_dcmpeq> 800946c: b108 cbz r0, 8009472 <__cvt+0x9e> 800946e: f8cd 901c str.w r9, [sp, #28] 8009472: 2230 movs r2, #48 ; 0x30 8009474: 9b07 ldr r3, [sp, #28] 8009476: 454b cmp r3, r9 8009478: d307 bcc.n 800948a <__cvt+0xb6> 800947a: 4630 mov r0, r6 800947c: 9b07 ldr r3, [sp, #28] 800947e: 9a15 ldr r2, [sp, #84] ; 0x54 8009480: 1b9b subs r3, r3, r6 8009482: 6013 str r3, [r2, #0] 8009484: b008 add sp, #32 8009486: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800948a: 1c59 adds r1, r3, #1 800948c: 9107 str r1, [sp, #28] 800948e: 701a strb r2, [r3, #0] 8009490: e7f0 b.n 8009474 <__cvt+0xa0> 08009492 <__exponent>: 8009492: 4603 mov r3, r0 8009494: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8009496: 2900 cmp r1, #0 8009498: f803 2b02 strb.w r2, [r3], #2 800949c: bfb6 itet lt 800949e: 222d movlt r2, #45 ; 0x2d 80094a0: 222b movge r2, #43 ; 0x2b 80094a2: 4249 neglt r1, r1 80094a4: 2909 cmp r1, #9 80094a6: 7042 strb r2, [r0, #1] 80094a8: dd2b ble.n 8009502 <__exponent+0x70> 80094aa: f10d 0407 add.w r4, sp, #7 80094ae: 46a4 mov ip, r4 80094b0: 270a movs r7, #10 80094b2: fb91 f6f7 sdiv r6, r1, r7 80094b6: 460a mov r2, r1 80094b8: 46a6 mov lr, r4 80094ba: fb07 1516 mls r5, r7, r6, r1 80094be: 2a63 cmp r2, #99 ; 0x63 80094c0: f105 0530 add.w r5, r5, #48 ; 0x30 80094c4: 4631 mov r1, r6 80094c6: f104 34ff add.w r4, r4, #4294967295 ; 0xffffffff 80094ca: f80e 5c01 strb.w r5, [lr, #-1] 80094ce: dcf0 bgt.n 80094b2 <__exponent+0x20> 80094d0: 3130 adds r1, #48 ; 0x30 80094d2: f1ae 0502 sub.w r5, lr, #2 80094d6: f804 1c01 strb.w r1, [r4, #-1] 80094da: 4629 mov r1, r5 80094dc: 1c44 adds r4, r0, #1 80094de: 4561 cmp r1, ip 80094e0: d30a bcc.n 80094f8 <__exponent+0x66> 80094e2: f10d 0209 add.w r2, sp, #9 80094e6: eba2 020e sub.w r2, r2, lr 80094ea: 4565 cmp r5, ip 80094ec: bf88 it hi 80094ee: 2200 movhi r2, #0 80094f0: 4413 add r3, r2 80094f2: 1a18 subs r0, r3, r0 80094f4: b003 add sp, #12 80094f6: bdf0 pop {r4, r5, r6, r7, pc} 80094f8: f811 2b01 ldrb.w r2, [r1], #1 80094fc: f804 2f01 strb.w r2, [r4, #1]! 8009500: e7ed b.n 80094de <__exponent+0x4c> 8009502: 2330 movs r3, #48 ; 0x30 8009504: 3130 adds r1, #48 ; 0x30 8009506: 7083 strb r3, [r0, #2] 8009508: 70c1 strb r1, [r0, #3] 800950a: 1d03 adds r3, r0, #4 800950c: e7f1 b.n 80094f2 <__exponent+0x60> ... 08009510 <_printf_float>: 8009510: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8009514: b091 sub sp, #68 ; 0x44 8009516: 460c mov r4, r1 8009518: f8dd 8068 ldr.w r8, [sp, #104] ; 0x68 800951c: 4616 mov r6, r2 800951e: 461f mov r7, r3 8009520: 4605 mov r5, r0 8009522: f002 f80d bl 800b540 <_localeconv_r> 8009526: 6803 ldr r3, [r0, #0] 8009528: 4618 mov r0, r3 800952a: 9309 str r3, [sp, #36] ; 0x24 800952c: f7f6 fe7c bl 8000228 8009530: 2300 movs r3, #0 8009532: 930e str r3, [sp, #56] ; 0x38 8009534: f8d8 3000 ldr.w r3, [r8] 8009538: 900a str r0, [sp, #40] ; 0x28 800953a: 3307 adds r3, #7 800953c: f023 0307 bic.w r3, r3, #7 8009540: f103 0208 add.w r2, r3, #8 8009544: f894 9018 ldrb.w r9, [r4, #24] 8009548: f8d4 b000 ldr.w fp, [r4] 800954c: f8c8 2000 str.w r2, [r8] 8009550: e9d3 2300 ldrd r2, r3, [r3] 8009554: e9c4 2312 strd r2, r3, [r4, #72] ; 0x48 8009558: e9d4 8a12 ldrd r8, sl, [r4, #72] ; 0x48 800955c: f02a 4300 bic.w r3, sl, #2147483648 ; 0x80000000 8009560: 930b str r3, [sp, #44] ; 0x2c 8009562: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 8009566: 4640 mov r0, r8 8009568: 4b9c ldr r3, [pc, #624] ; (80097dc <_printf_float+0x2cc>) 800956a: 990b ldr r1, [sp, #44] ; 0x2c 800956c: f7f7 fac4 bl 8000af8 <__aeabi_dcmpun> 8009570: bb70 cbnz r0, 80095d0 <_printf_float+0xc0> 8009572: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 8009576: 4640 mov r0, r8 8009578: 4b98 ldr r3, [pc, #608] ; (80097dc <_printf_float+0x2cc>) 800957a: 990b ldr r1, [sp, #44] ; 0x2c 800957c: f7f7 fa9e bl 8000abc <__aeabi_dcmple> 8009580: bb30 cbnz r0, 80095d0 <_printf_float+0xc0> 8009582: 2200 movs r2, #0 8009584: 2300 movs r3, #0 8009586: 4640 mov r0, r8 8009588: 4651 mov r1, sl 800958a: f7f7 fa8d bl 8000aa8 <__aeabi_dcmplt> 800958e: b110 cbz r0, 8009596 <_printf_float+0x86> 8009590: 232d movs r3, #45 ; 0x2d 8009592: f884 3043 strb.w r3, [r4, #67] ; 0x43 8009596: 4b92 ldr r3, [pc, #584] ; (80097e0 <_printf_float+0x2d0>) 8009598: 4892 ldr r0, [pc, #584] ; (80097e4 <_printf_float+0x2d4>) 800959a: f1b9 0f47 cmp.w r9, #71 ; 0x47 800959e: bf94 ite ls 80095a0: 4698 movls r8, r3 80095a2: 4680 movhi r8, r0 80095a4: 2303 movs r3, #3 80095a6: f04f 0a00 mov.w sl, #0 80095aa: 6123 str r3, [r4, #16] 80095ac: f02b 0304 bic.w r3, fp, #4 80095b0: 6023 str r3, [r4, #0] 80095b2: 4633 mov r3, r6 80095b4: 4621 mov r1, r4 80095b6: 4628 mov r0, r5 80095b8: 9700 str r7, [sp, #0] 80095ba: aa0f add r2, sp, #60 ; 0x3c 80095bc: f000 f9d4 bl 8009968 <_printf_common> 80095c0: 3001 adds r0, #1 80095c2: f040 8090 bne.w 80096e6 <_printf_float+0x1d6> 80095c6: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 80095ca: b011 add sp, #68 ; 0x44 80095cc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80095d0: 4642 mov r2, r8 80095d2: 4653 mov r3, sl 80095d4: 4640 mov r0, r8 80095d6: 4651 mov r1, sl 80095d8: f7f7 fa8e bl 8000af8 <__aeabi_dcmpun> 80095dc: b148 cbz r0, 80095f2 <_printf_float+0xe2> 80095de: f1ba 0f00 cmp.w sl, #0 80095e2: bfb8 it lt 80095e4: 232d movlt r3, #45 ; 0x2d 80095e6: 4880 ldr r0, [pc, #512] ; (80097e8 <_printf_float+0x2d8>) 80095e8: bfb8 it lt 80095ea: f884 3043 strblt.w r3, [r4, #67] ; 0x43 80095ee: 4b7f ldr r3, [pc, #508] ; (80097ec <_printf_float+0x2dc>) 80095f0: e7d3 b.n 800959a <_printf_float+0x8a> 80095f2: 6863 ldr r3, [r4, #4] 80095f4: f009 01df and.w r1, r9, #223 ; 0xdf 80095f8: 1c5a adds r2, r3, #1 80095fa: d142 bne.n 8009682 <_printf_float+0x172> 80095fc: 2306 movs r3, #6 80095fe: 6063 str r3, [r4, #4] 8009600: 2200 movs r2, #0 8009602: 9206 str r2, [sp, #24] 8009604: aa0e add r2, sp, #56 ; 0x38 8009606: e9cd 9204 strd r9, r2, [sp, #16] 800960a: aa0d add r2, sp, #52 ; 0x34 800960c: f44b 6380 orr.w r3, fp, #1024 ; 0x400 8009610: 9203 str r2, [sp, #12] 8009612: f10d 0233 add.w r2, sp, #51 ; 0x33 8009616: e9cd 3201 strd r3, r2, [sp, #4] 800961a: 6023 str r3, [r4, #0] 800961c: 6863 ldr r3, [r4, #4] 800961e: 4642 mov r2, r8 8009620: 9300 str r3, [sp, #0] 8009622: 4628 mov r0, r5 8009624: 4653 mov r3, sl 8009626: 910b str r1, [sp, #44] ; 0x2c 8009628: f7ff fed4 bl 80093d4 <__cvt> 800962c: 990b ldr r1, [sp, #44] ; 0x2c 800962e: 4680 mov r8, r0 8009630: 2947 cmp r1, #71 ; 0x47 8009632: 990d ldr r1, [sp, #52] ; 0x34 8009634: d108 bne.n 8009648 <_printf_float+0x138> 8009636: 1cc8 adds r0, r1, #3 8009638: db02 blt.n 8009640 <_printf_float+0x130> 800963a: 6863 ldr r3, [r4, #4] 800963c: 4299 cmp r1, r3 800963e: dd40 ble.n 80096c2 <_printf_float+0x1b2> 8009640: f1a9 0902 sub.w r9, r9, #2 8009644: fa5f f989 uxtb.w r9, r9 8009648: f1b9 0f65 cmp.w r9, #101 ; 0x65 800964c: d81f bhi.n 800968e <_printf_float+0x17e> 800964e: 464a mov r2, r9 8009650: 3901 subs r1, #1 8009652: f104 0050 add.w r0, r4, #80 ; 0x50 8009656: 910d str r1, [sp, #52] ; 0x34 8009658: f7ff ff1b bl 8009492 <__exponent> 800965c: 9a0e ldr r2, [sp, #56] ; 0x38 800965e: 4682 mov sl, r0 8009660: 1813 adds r3, r2, r0 8009662: 2a01 cmp r2, #1 8009664: 6123 str r3, [r4, #16] 8009666: dc02 bgt.n 800966e <_printf_float+0x15e> 8009668: 6822 ldr r2, [r4, #0] 800966a: 07d2 lsls r2, r2, #31 800966c: d501 bpl.n 8009672 <_printf_float+0x162> 800966e: 3301 adds r3, #1 8009670: 6123 str r3, [r4, #16] 8009672: f89d 3033 ldrb.w r3, [sp, #51] ; 0x33 8009676: 2b00 cmp r3, #0 8009678: d09b beq.n 80095b2 <_printf_float+0xa2> 800967a: 232d movs r3, #45 ; 0x2d 800967c: f884 3043 strb.w r3, [r4, #67] ; 0x43 8009680: e797 b.n 80095b2 <_printf_float+0xa2> 8009682: 2947 cmp r1, #71 ; 0x47 8009684: d1bc bne.n 8009600 <_printf_float+0xf0> 8009686: 2b00 cmp r3, #0 8009688: d1ba bne.n 8009600 <_printf_float+0xf0> 800968a: 2301 movs r3, #1 800968c: e7b7 b.n 80095fe <_printf_float+0xee> 800968e: f1b9 0f66 cmp.w r9, #102 ; 0x66 8009692: d118 bne.n 80096c6 <_printf_float+0x1b6> 8009694: 2900 cmp r1, #0 8009696: 6863 ldr r3, [r4, #4] 8009698: dd0b ble.n 80096b2 <_printf_float+0x1a2> 800969a: 6121 str r1, [r4, #16] 800969c: b913 cbnz r3, 80096a4 <_printf_float+0x194> 800969e: 6822 ldr r2, [r4, #0] 80096a0: 07d0 lsls r0, r2, #31 80096a2: d502 bpl.n 80096aa <_printf_float+0x19a> 80096a4: 3301 adds r3, #1 80096a6: 440b add r3, r1 80096a8: 6123 str r3, [r4, #16] 80096aa: f04f 0a00 mov.w sl, #0 80096ae: 65a1 str r1, [r4, #88] ; 0x58 80096b0: e7df b.n 8009672 <_printf_float+0x162> 80096b2: b913 cbnz r3, 80096ba <_printf_float+0x1aa> 80096b4: 6822 ldr r2, [r4, #0] 80096b6: 07d2 lsls r2, r2, #31 80096b8: d501 bpl.n 80096be <_printf_float+0x1ae> 80096ba: 3302 adds r3, #2 80096bc: e7f4 b.n 80096a8 <_printf_float+0x198> 80096be: 2301 movs r3, #1 80096c0: e7f2 b.n 80096a8 <_printf_float+0x198> 80096c2: f04f 0967 mov.w r9, #103 ; 0x67 80096c6: 9b0e ldr r3, [sp, #56] ; 0x38 80096c8: 4299 cmp r1, r3 80096ca: db05 blt.n 80096d8 <_printf_float+0x1c8> 80096cc: 6823 ldr r3, [r4, #0] 80096ce: 6121 str r1, [r4, #16] 80096d0: 07d8 lsls r0, r3, #31 80096d2: d5ea bpl.n 80096aa <_printf_float+0x19a> 80096d4: 1c4b adds r3, r1, #1 80096d6: e7e7 b.n 80096a8 <_printf_float+0x198> 80096d8: 2900 cmp r1, #0 80096da: bfcc ite gt 80096dc: 2201 movgt r2, #1 80096de: f1c1 0202 rsble r2, r1, #2 80096e2: 4413 add r3, r2 80096e4: e7e0 b.n 80096a8 <_printf_float+0x198> 80096e6: 6823 ldr r3, [r4, #0] 80096e8: 055a lsls r2, r3, #21 80096ea: d407 bmi.n 80096fc <_printf_float+0x1ec> 80096ec: 6923 ldr r3, [r4, #16] 80096ee: 4642 mov r2, r8 80096f0: 4631 mov r1, r6 80096f2: 4628 mov r0, r5 80096f4: 47b8 blx r7 80096f6: 3001 adds r0, #1 80096f8: d12b bne.n 8009752 <_printf_float+0x242> 80096fa: e764 b.n 80095c6 <_printf_float+0xb6> 80096fc: f1b9 0f65 cmp.w r9, #101 ; 0x65 8009700: f240 80dd bls.w 80098be <_printf_float+0x3ae> 8009704: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 8009708: 2200 movs r2, #0 800970a: 2300 movs r3, #0 800970c: f7f7 f9c2 bl 8000a94 <__aeabi_dcmpeq> 8009710: 2800 cmp r0, #0 8009712: d033 beq.n 800977c <_printf_float+0x26c> 8009714: 2301 movs r3, #1 8009716: 4631 mov r1, r6 8009718: 4628 mov r0, r5 800971a: 4a35 ldr r2, [pc, #212] ; (80097f0 <_printf_float+0x2e0>) 800971c: 47b8 blx r7 800971e: 3001 adds r0, #1 8009720: f43f af51 beq.w 80095c6 <_printf_float+0xb6> 8009724: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 8009728: 429a cmp r2, r3 800972a: db02 blt.n 8009732 <_printf_float+0x222> 800972c: 6823 ldr r3, [r4, #0] 800972e: 07d8 lsls r0, r3, #31 8009730: d50f bpl.n 8009752 <_printf_float+0x242> 8009732: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 8009736: 4631 mov r1, r6 8009738: 4628 mov r0, r5 800973a: 47b8 blx r7 800973c: 3001 adds r0, #1 800973e: f43f af42 beq.w 80095c6 <_printf_float+0xb6> 8009742: f04f 0800 mov.w r8, #0 8009746: f104 091a add.w r9, r4, #26 800974a: 9b0e ldr r3, [sp, #56] ; 0x38 800974c: 3b01 subs r3, #1 800974e: 4543 cmp r3, r8 8009750: dc09 bgt.n 8009766 <_printf_float+0x256> 8009752: 6823 ldr r3, [r4, #0] 8009754: 079b lsls r3, r3, #30 8009756: f100 8102 bmi.w 800995e <_printf_float+0x44e> 800975a: 68e0 ldr r0, [r4, #12] 800975c: 9b0f ldr r3, [sp, #60] ; 0x3c 800975e: 4298 cmp r0, r3 8009760: bfb8 it lt 8009762: 4618 movlt r0, r3 8009764: e731 b.n 80095ca <_printf_float+0xba> 8009766: 2301 movs r3, #1 8009768: 464a mov r2, r9 800976a: 4631 mov r1, r6 800976c: 4628 mov r0, r5 800976e: 47b8 blx r7 8009770: 3001 adds r0, #1 8009772: f43f af28 beq.w 80095c6 <_printf_float+0xb6> 8009776: f108 0801 add.w r8, r8, #1 800977a: e7e6 b.n 800974a <_printf_float+0x23a> 800977c: 9b0d ldr r3, [sp, #52] ; 0x34 800977e: 2b00 cmp r3, #0 8009780: dc38 bgt.n 80097f4 <_printf_float+0x2e4> 8009782: 2301 movs r3, #1 8009784: 4631 mov r1, r6 8009786: 4628 mov r0, r5 8009788: 4a19 ldr r2, [pc, #100] ; (80097f0 <_printf_float+0x2e0>) 800978a: 47b8 blx r7 800978c: 3001 adds r0, #1 800978e: f43f af1a beq.w 80095c6 <_printf_float+0xb6> 8009792: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 8009796: 4313 orrs r3, r2 8009798: d102 bne.n 80097a0 <_printf_float+0x290> 800979a: 6823 ldr r3, [r4, #0] 800979c: 07d9 lsls r1, r3, #31 800979e: d5d8 bpl.n 8009752 <_printf_float+0x242> 80097a0: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 80097a4: 4631 mov r1, r6 80097a6: 4628 mov r0, r5 80097a8: 47b8 blx r7 80097aa: 3001 adds r0, #1 80097ac: f43f af0b beq.w 80095c6 <_printf_float+0xb6> 80097b0: f04f 0900 mov.w r9, #0 80097b4: f104 0a1a add.w sl, r4, #26 80097b8: 9b0d ldr r3, [sp, #52] ; 0x34 80097ba: 425b negs r3, r3 80097bc: 454b cmp r3, r9 80097be: dc01 bgt.n 80097c4 <_printf_float+0x2b4> 80097c0: 9b0e ldr r3, [sp, #56] ; 0x38 80097c2: e794 b.n 80096ee <_printf_float+0x1de> 80097c4: 2301 movs r3, #1 80097c6: 4652 mov r2, sl 80097c8: 4631 mov r1, r6 80097ca: 4628 mov r0, r5 80097cc: 47b8 blx r7 80097ce: 3001 adds r0, #1 80097d0: f43f aef9 beq.w 80095c6 <_printf_float+0xb6> 80097d4: f109 0901 add.w r9, r9, #1 80097d8: e7ee b.n 80097b8 <_printf_float+0x2a8> 80097da: bf00 nop 80097dc: 7fefffff .word 0x7fefffff 80097e0: 0800d3e0 .word 0x0800d3e0 80097e4: 0800d3e4 .word 0x0800d3e4 80097e8: 0800d3ec .word 0x0800d3ec 80097ec: 0800d3e8 .word 0x0800d3e8 80097f0: 0800d7dc .word 0x0800d7dc 80097f4: 9a0e ldr r2, [sp, #56] ; 0x38 80097f6: 6da3 ldr r3, [r4, #88] ; 0x58 80097f8: 429a cmp r2, r3 80097fa: bfa8 it ge 80097fc: 461a movge r2, r3 80097fe: 2a00 cmp r2, #0 8009800: 4691 mov r9, r2 8009802: dc37 bgt.n 8009874 <_printf_float+0x364> 8009804: f04f 0b00 mov.w fp, #0 8009808: ea29 79e9 bic.w r9, r9, r9, asr #31 800980c: f104 021a add.w r2, r4, #26 8009810: f8d4 a058 ldr.w sl, [r4, #88] ; 0x58 8009814: ebaa 0309 sub.w r3, sl, r9 8009818: 455b cmp r3, fp 800981a: dc33 bgt.n 8009884 <_printf_float+0x374> 800981c: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 8009820: 429a cmp r2, r3 8009822: db3b blt.n 800989c <_printf_float+0x38c> 8009824: 6823 ldr r3, [r4, #0] 8009826: 07da lsls r2, r3, #31 8009828: d438 bmi.n 800989c <_printf_float+0x38c> 800982a: 9b0e ldr r3, [sp, #56] ; 0x38 800982c: 990d ldr r1, [sp, #52] ; 0x34 800982e: eba3 020a sub.w r2, r3, sl 8009832: eba3 0901 sub.w r9, r3, r1 8009836: 4591 cmp r9, r2 8009838: bfa8 it ge 800983a: 4691 movge r9, r2 800983c: f1b9 0f00 cmp.w r9, #0 8009840: dc34 bgt.n 80098ac <_printf_float+0x39c> 8009842: f04f 0800 mov.w r8, #0 8009846: ea29 79e9 bic.w r9, r9, r9, asr #31 800984a: f104 0a1a add.w sl, r4, #26 800984e: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 8009852: 1a9b subs r3, r3, r2 8009854: eba3 0309 sub.w r3, r3, r9 8009858: 4543 cmp r3, r8 800985a: f77f af7a ble.w 8009752 <_printf_float+0x242> 800985e: 2301 movs r3, #1 8009860: 4652 mov r2, sl 8009862: 4631 mov r1, r6 8009864: 4628 mov r0, r5 8009866: 47b8 blx r7 8009868: 3001 adds r0, #1 800986a: f43f aeac beq.w 80095c6 <_printf_float+0xb6> 800986e: f108 0801 add.w r8, r8, #1 8009872: e7ec b.n 800984e <_printf_float+0x33e> 8009874: 4613 mov r3, r2 8009876: 4631 mov r1, r6 8009878: 4642 mov r2, r8 800987a: 4628 mov r0, r5 800987c: 47b8 blx r7 800987e: 3001 adds r0, #1 8009880: d1c0 bne.n 8009804 <_printf_float+0x2f4> 8009882: e6a0 b.n 80095c6 <_printf_float+0xb6> 8009884: 2301 movs r3, #1 8009886: 4631 mov r1, r6 8009888: 4628 mov r0, r5 800988a: 920b str r2, [sp, #44] ; 0x2c 800988c: 47b8 blx r7 800988e: 3001 adds r0, #1 8009890: f43f ae99 beq.w 80095c6 <_printf_float+0xb6> 8009894: 9a0b ldr r2, [sp, #44] ; 0x2c 8009896: f10b 0b01 add.w fp, fp, #1 800989a: e7b9 b.n 8009810 <_printf_float+0x300> 800989c: 4631 mov r1, r6 800989e: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 80098a2: 4628 mov r0, r5 80098a4: 47b8 blx r7 80098a6: 3001 adds r0, #1 80098a8: d1bf bne.n 800982a <_printf_float+0x31a> 80098aa: e68c b.n 80095c6 <_printf_float+0xb6> 80098ac: 464b mov r3, r9 80098ae: 4631 mov r1, r6 80098b0: 4628 mov r0, r5 80098b2: eb08 020a add.w r2, r8, sl 80098b6: 47b8 blx r7 80098b8: 3001 adds r0, #1 80098ba: d1c2 bne.n 8009842 <_printf_float+0x332> 80098bc: e683 b.n 80095c6 <_printf_float+0xb6> 80098be: 9a0e ldr r2, [sp, #56] ; 0x38 80098c0: 2a01 cmp r2, #1 80098c2: dc01 bgt.n 80098c8 <_printf_float+0x3b8> 80098c4: 07db lsls r3, r3, #31 80098c6: d537 bpl.n 8009938 <_printf_float+0x428> 80098c8: 2301 movs r3, #1 80098ca: 4642 mov r2, r8 80098cc: 4631 mov r1, r6 80098ce: 4628 mov r0, r5 80098d0: 47b8 blx r7 80098d2: 3001 adds r0, #1 80098d4: f43f ae77 beq.w 80095c6 <_printf_float+0xb6> 80098d8: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 80098dc: 4631 mov r1, r6 80098de: 4628 mov r0, r5 80098e0: 47b8 blx r7 80098e2: 3001 adds r0, #1 80098e4: f43f ae6f beq.w 80095c6 <_printf_float+0xb6> 80098e8: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 80098ec: 2200 movs r2, #0 80098ee: 2300 movs r3, #0 80098f0: f7f7 f8d0 bl 8000a94 <__aeabi_dcmpeq> 80098f4: b9d8 cbnz r0, 800992e <_printf_float+0x41e> 80098f6: 9b0e ldr r3, [sp, #56] ; 0x38 80098f8: f108 0201 add.w r2, r8, #1 80098fc: 3b01 subs r3, #1 80098fe: 4631 mov r1, r6 8009900: 4628 mov r0, r5 8009902: 47b8 blx r7 8009904: 3001 adds r0, #1 8009906: d10e bne.n 8009926 <_printf_float+0x416> 8009908: e65d b.n 80095c6 <_printf_float+0xb6> 800990a: 2301 movs r3, #1 800990c: 464a mov r2, r9 800990e: 4631 mov r1, r6 8009910: 4628 mov r0, r5 8009912: 47b8 blx r7 8009914: 3001 adds r0, #1 8009916: f43f ae56 beq.w 80095c6 <_printf_float+0xb6> 800991a: f108 0801 add.w r8, r8, #1 800991e: 9b0e ldr r3, [sp, #56] ; 0x38 8009920: 3b01 subs r3, #1 8009922: 4543 cmp r3, r8 8009924: dcf1 bgt.n 800990a <_printf_float+0x3fa> 8009926: 4653 mov r3, sl 8009928: f104 0250 add.w r2, r4, #80 ; 0x50 800992c: e6e0 b.n 80096f0 <_printf_float+0x1e0> 800992e: f04f 0800 mov.w r8, #0 8009932: f104 091a add.w r9, r4, #26 8009936: e7f2 b.n 800991e <_printf_float+0x40e> 8009938: 2301 movs r3, #1 800993a: 4642 mov r2, r8 800993c: e7df b.n 80098fe <_printf_float+0x3ee> 800993e: 2301 movs r3, #1 8009940: 464a mov r2, r9 8009942: 4631 mov r1, r6 8009944: 4628 mov r0, r5 8009946: 47b8 blx r7 8009948: 3001 adds r0, #1 800994a: f43f ae3c beq.w 80095c6 <_printf_float+0xb6> 800994e: f108 0801 add.w r8, r8, #1 8009952: 68e3 ldr r3, [r4, #12] 8009954: 990f ldr r1, [sp, #60] ; 0x3c 8009956: 1a5b subs r3, r3, r1 8009958: 4543 cmp r3, r8 800995a: dcf0 bgt.n 800993e <_printf_float+0x42e> 800995c: e6fd b.n 800975a <_printf_float+0x24a> 800995e: f04f 0800 mov.w r8, #0 8009962: f104 0919 add.w r9, r4, #25 8009966: e7f4 b.n 8009952 <_printf_float+0x442> 08009968 <_printf_common>: 8009968: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800996c: 4616 mov r6, r2 800996e: 4699 mov r9, r3 8009970: 688a ldr r2, [r1, #8] 8009972: 690b ldr r3, [r1, #16] 8009974: 4607 mov r7, r0 8009976: 4293 cmp r3, r2 8009978: bfb8 it lt 800997a: 4613 movlt r3, r2 800997c: 6033 str r3, [r6, #0] 800997e: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 8009982: 460c mov r4, r1 8009984: f8dd 8020 ldr.w r8, [sp, #32] 8009988: b10a cbz r2, 800998e <_printf_common+0x26> 800998a: 3301 adds r3, #1 800998c: 6033 str r3, [r6, #0] 800998e: 6823 ldr r3, [r4, #0] 8009990: 0699 lsls r1, r3, #26 8009992: bf42 ittt mi 8009994: 6833 ldrmi r3, [r6, #0] 8009996: 3302 addmi r3, #2 8009998: 6033 strmi r3, [r6, #0] 800999a: 6825 ldr r5, [r4, #0] 800999c: f015 0506 ands.w r5, r5, #6 80099a0: d106 bne.n 80099b0 <_printf_common+0x48> 80099a2: f104 0a19 add.w sl, r4, #25 80099a6: 68e3 ldr r3, [r4, #12] 80099a8: 6832 ldr r2, [r6, #0] 80099aa: 1a9b subs r3, r3, r2 80099ac: 42ab cmp r3, r5 80099ae: dc28 bgt.n 8009a02 <_printf_common+0x9a> 80099b0: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 80099b4: 1e13 subs r3, r2, #0 80099b6: 6822 ldr r2, [r4, #0] 80099b8: bf18 it ne 80099ba: 2301 movne r3, #1 80099bc: 0692 lsls r2, r2, #26 80099be: d42d bmi.n 8009a1c <_printf_common+0xb4> 80099c0: 4649 mov r1, r9 80099c2: 4638 mov r0, r7 80099c4: f104 0243 add.w r2, r4, #67 ; 0x43 80099c8: 47c0 blx r8 80099ca: 3001 adds r0, #1 80099cc: d020 beq.n 8009a10 <_printf_common+0xa8> 80099ce: 6823 ldr r3, [r4, #0] 80099d0: 68e5 ldr r5, [r4, #12] 80099d2: f003 0306 and.w r3, r3, #6 80099d6: 2b04 cmp r3, #4 80099d8: bf18 it ne 80099da: 2500 movne r5, #0 80099dc: 6832 ldr r2, [r6, #0] 80099de: f04f 0600 mov.w r6, #0 80099e2: 68a3 ldr r3, [r4, #8] 80099e4: bf08 it eq 80099e6: 1aad subeq r5, r5, r2 80099e8: 6922 ldr r2, [r4, #16] 80099ea: bf08 it eq 80099ec: ea25 75e5 biceq.w r5, r5, r5, asr #31 80099f0: 4293 cmp r3, r2 80099f2: bfc4 itt gt 80099f4: 1a9b subgt r3, r3, r2 80099f6: 18ed addgt r5, r5, r3 80099f8: 341a adds r4, #26 80099fa: 42b5 cmp r5, r6 80099fc: d11a bne.n 8009a34 <_printf_common+0xcc> 80099fe: 2000 movs r0, #0 8009a00: e008 b.n 8009a14 <_printf_common+0xac> 8009a02: 2301 movs r3, #1 8009a04: 4652 mov r2, sl 8009a06: 4649 mov r1, r9 8009a08: 4638 mov r0, r7 8009a0a: 47c0 blx r8 8009a0c: 3001 adds r0, #1 8009a0e: d103 bne.n 8009a18 <_printf_common+0xb0> 8009a10: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8009a14: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8009a18: 3501 adds r5, #1 8009a1a: e7c4 b.n 80099a6 <_printf_common+0x3e> 8009a1c: 2030 movs r0, #48 ; 0x30 8009a1e: 18e1 adds r1, r4, r3 8009a20: f881 0043 strb.w r0, [r1, #67] ; 0x43 8009a24: 1c5a adds r2, r3, #1 8009a26: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 8009a2a: 4422 add r2, r4 8009a2c: 3302 adds r3, #2 8009a2e: f882 1043 strb.w r1, [r2, #67] ; 0x43 8009a32: e7c5 b.n 80099c0 <_printf_common+0x58> 8009a34: 2301 movs r3, #1 8009a36: 4622 mov r2, r4 8009a38: 4649 mov r1, r9 8009a3a: 4638 mov r0, r7 8009a3c: 47c0 blx r8 8009a3e: 3001 adds r0, #1 8009a40: d0e6 beq.n 8009a10 <_printf_common+0xa8> 8009a42: 3601 adds r6, #1 8009a44: e7d9 b.n 80099fa <_printf_common+0x92> ... 08009a48 <_printf_i>: 8009a48: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8009a4c: 7e0f ldrb r7, [r1, #24] 8009a4e: 4691 mov r9, r2 8009a50: 2f78 cmp r7, #120 ; 0x78 8009a52: 4680 mov r8, r0 8009a54: 460c mov r4, r1 8009a56: 469a mov sl, r3 8009a58: 9d0c ldr r5, [sp, #48] ; 0x30 8009a5a: f101 0243 add.w r2, r1, #67 ; 0x43 8009a5e: d807 bhi.n 8009a70 <_printf_i+0x28> 8009a60: 2f62 cmp r7, #98 ; 0x62 8009a62: d80a bhi.n 8009a7a <_printf_i+0x32> 8009a64: 2f00 cmp r7, #0 8009a66: f000 80d9 beq.w 8009c1c <_printf_i+0x1d4> 8009a6a: 2f58 cmp r7, #88 ; 0x58 8009a6c: f000 80a4 beq.w 8009bb8 <_printf_i+0x170> 8009a70: f104 0542 add.w r5, r4, #66 ; 0x42 8009a74: f884 7042 strb.w r7, [r4, #66] ; 0x42 8009a78: e03a b.n 8009af0 <_printf_i+0xa8> 8009a7a: f1a7 0363 sub.w r3, r7, #99 ; 0x63 8009a7e: 2b15 cmp r3, #21 8009a80: d8f6 bhi.n 8009a70 <_printf_i+0x28> 8009a82: a101 add r1, pc, #4 ; (adr r1, 8009a88 <_printf_i+0x40>) 8009a84: f851 f023 ldr.w pc, [r1, r3, lsl #2] 8009a88: 08009ae1 .word 0x08009ae1 8009a8c: 08009af5 .word 0x08009af5 8009a90: 08009a71 .word 0x08009a71 8009a94: 08009a71 .word 0x08009a71 8009a98: 08009a71 .word 0x08009a71 8009a9c: 08009a71 .word 0x08009a71 8009aa0: 08009af5 .word 0x08009af5 8009aa4: 08009a71 .word 0x08009a71 8009aa8: 08009a71 .word 0x08009a71 8009aac: 08009a71 .word 0x08009a71 8009ab0: 08009a71 .word 0x08009a71 8009ab4: 08009c03 .word 0x08009c03 8009ab8: 08009b25 .word 0x08009b25 8009abc: 08009be5 .word 0x08009be5 8009ac0: 08009a71 .word 0x08009a71 8009ac4: 08009a71 .word 0x08009a71 8009ac8: 08009c25 .word 0x08009c25 8009acc: 08009a71 .word 0x08009a71 8009ad0: 08009b25 .word 0x08009b25 8009ad4: 08009a71 .word 0x08009a71 8009ad8: 08009a71 .word 0x08009a71 8009adc: 08009bed .word 0x08009bed 8009ae0: 682b ldr r3, [r5, #0] 8009ae2: 1d1a adds r2, r3, #4 8009ae4: 681b ldr r3, [r3, #0] 8009ae6: 602a str r2, [r5, #0] 8009ae8: f104 0542 add.w r5, r4, #66 ; 0x42 8009aec: f884 3042 strb.w r3, [r4, #66] ; 0x42 8009af0: 2301 movs r3, #1 8009af2: e0a4 b.n 8009c3e <_printf_i+0x1f6> 8009af4: 6820 ldr r0, [r4, #0] 8009af6: 6829 ldr r1, [r5, #0] 8009af8: 0606 lsls r6, r0, #24 8009afa: f101 0304 add.w r3, r1, #4 8009afe: d50a bpl.n 8009b16 <_printf_i+0xce> 8009b00: 680e ldr r6, [r1, #0] 8009b02: 602b str r3, [r5, #0] 8009b04: 2e00 cmp r6, #0 8009b06: da03 bge.n 8009b10 <_printf_i+0xc8> 8009b08: 232d movs r3, #45 ; 0x2d 8009b0a: 4276 negs r6, r6 8009b0c: f884 3043 strb.w r3, [r4, #67] ; 0x43 8009b10: 230a movs r3, #10 8009b12: 485e ldr r0, [pc, #376] ; (8009c8c <_printf_i+0x244>) 8009b14: e019 b.n 8009b4a <_printf_i+0x102> 8009b16: 680e ldr r6, [r1, #0] 8009b18: f010 0f40 tst.w r0, #64 ; 0x40 8009b1c: 602b str r3, [r5, #0] 8009b1e: bf18 it ne 8009b20: b236 sxthne r6, r6 8009b22: e7ef b.n 8009b04 <_printf_i+0xbc> 8009b24: 682b ldr r3, [r5, #0] 8009b26: 6820 ldr r0, [r4, #0] 8009b28: 1d19 adds r1, r3, #4 8009b2a: 6029 str r1, [r5, #0] 8009b2c: 0601 lsls r1, r0, #24 8009b2e: d501 bpl.n 8009b34 <_printf_i+0xec> 8009b30: 681e ldr r6, [r3, #0] 8009b32: e002 b.n 8009b3a <_printf_i+0xf2> 8009b34: 0646 lsls r6, r0, #25 8009b36: d5fb bpl.n 8009b30 <_printf_i+0xe8> 8009b38: 881e ldrh r6, [r3, #0] 8009b3a: 2f6f cmp r7, #111 ; 0x6f 8009b3c: bf0c ite eq 8009b3e: 2308 moveq r3, #8 8009b40: 230a movne r3, #10 8009b42: 4852 ldr r0, [pc, #328] ; (8009c8c <_printf_i+0x244>) 8009b44: 2100 movs r1, #0 8009b46: f884 1043 strb.w r1, [r4, #67] ; 0x43 8009b4a: 6865 ldr r5, [r4, #4] 8009b4c: 2d00 cmp r5, #0 8009b4e: bfa8 it ge 8009b50: 6821 ldrge r1, [r4, #0] 8009b52: 60a5 str r5, [r4, #8] 8009b54: bfa4 itt ge 8009b56: f021 0104 bicge.w r1, r1, #4 8009b5a: 6021 strge r1, [r4, #0] 8009b5c: b90e cbnz r6, 8009b62 <_printf_i+0x11a> 8009b5e: 2d00 cmp r5, #0 8009b60: d04d beq.n 8009bfe <_printf_i+0x1b6> 8009b62: 4615 mov r5, r2 8009b64: fbb6 f1f3 udiv r1, r6, r3 8009b68: fb03 6711 mls r7, r3, r1, r6 8009b6c: 5dc7 ldrb r7, [r0, r7] 8009b6e: f805 7d01 strb.w r7, [r5, #-1]! 8009b72: 4637 mov r7, r6 8009b74: 42bb cmp r3, r7 8009b76: 460e mov r6, r1 8009b78: d9f4 bls.n 8009b64 <_printf_i+0x11c> 8009b7a: 2b08 cmp r3, #8 8009b7c: d10b bne.n 8009b96 <_printf_i+0x14e> 8009b7e: 6823 ldr r3, [r4, #0] 8009b80: 07de lsls r6, r3, #31 8009b82: d508 bpl.n 8009b96 <_printf_i+0x14e> 8009b84: 6923 ldr r3, [r4, #16] 8009b86: 6861 ldr r1, [r4, #4] 8009b88: 4299 cmp r1, r3 8009b8a: bfde ittt le 8009b8c: 2330 movle r3, #48 ; 0x30 8009b8e: f805 3c01 strble.w r3, [r5, #-1] 8009b92: f105 35ff addle.w r5, r5, #4294967295 ; 0xffffffff 8009b96: 1b52 subs r2, r2, r5 8009b98: 6122 str r2, [r4, #16] 8009b9a: 464b mov r3, r9 8009b9c: 4621 mov r1, r4 8009b9e: 4640 mov r0, r8 8009ba0: f8cd a000 str.w sl, [sp] 8009ba4: aa03 add r2, sp, #12 8009ba6: f7ff fedf bl 8009968 <_printf_common> 8009baa: 3001 adds r0, #1 8009bac: d14c bne.n 8009c48 <_printf_i+0x200> 8009bae: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8009bb2: b004 add sp, #16 8009bb4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8009bb8: 4834 ldr r0, [pc, #208] ; (8009c8c <_printf_i+0x244>) 8009bba: f881 7045 strb.w r7, [r1, #69] ; 0x45 8009bbe: 6829 ldr r1, [r5, #0] 8009bc0: 6823 ldr r3, [r4, #0] 8009bc2: f851 6b04 ldr.w r6, [r1], #4 8009bc6: 6029 str r1, [r5, #0] 8009bc8: 061d lsls r5, r3, #24 8009bca: d514 bpl.n 8009bf6 <_printf_i+0x1ae> 8009bcc: 07df lsls r7, r3, #31 8009bce: bf44 itt mi 8009bd0: f043 0320 orrmi.w r3, r3, #32 8009bd4: 6023 strmi r3, [r4, #0] 8009bd6: b91e cbnz r6, 8009be0 <_printf_i+0x198> 8009bd8: 6823 ldr r3, [r4, #0] 8009bda: f023 0320 bic.w r3, r3, #32 8009bde: 6023 str r3, [r4, #0] 8009be0: 2310 movs r3, #16 8009be2: e7af b.n 8009b44 <_printf_i+0xfc> 8009be4: 6823 ldr r3, [r4, #0] 8009be6: f043 0320 orr.w r3, r3, #32 8009bea: 6023 str r3, [r4, #0] 8009bec: 2378 movs r3, #120 ; 0x78 8009bee: 4828 ldr r0, [pc, #160] ; (8009c90 <_printf_i+0x248>) 8009bf0: f884 3045 strb.w r3, [r4, #69] ; 0x45 8009bf4: e7e3 b.n 8009bbe <_printf_i+0x176> 8009bf6: 0659 lsls r1, r3, #25 8009bf8: bf48 it mi 8009bfa: b2b6 uxthmi r6, r6 8009bfc: e7e6 b.n 8009bcc <_printf_i+0x184> 8009bfe: 4615 mov r5, r2 8009c00: e7bb b.n 8009b7a <_printf_i+0x132> 8009c02: 682b ldr r3, [r5, #0] 8009c04: 6826 ldr r6, [r4, #0] 8009c06: 1d18 adds r0, r3, #4 8009c08: 6961 ldr r1, [r4, #20] 8009c0a: 6028 str r0, [r5, #0] 8009c0c: 0635 lsls r5, r6, #24 8009c0e: 681b ldr r3, [r3, #0] 8009c10: d501 bpl.n 8009c16 <_printf_i+0x1ce> 8009c12: 6019 str r1, [r3, #0] 8009c14: e002 b.n 8009c1c <_printf_i+0x1d4> 8009c16: 0670 lsls r0, r6, #25 8009c18: d5fb bpl.n 8009c12 <_printf_i+0x1ca> 8009c1a: 8019 strh r1, [r3, #0] 8009c1c: 2300 movs r3, #0 8009c1e: 4615 mov r5, r2 8009c20: 6123 str r3, [r4, #16] 8009c22: e7ba b.n 8009b9a <_printf_i+0x152> 8009c24: 682b ldr r3, [r5, #0] 8009c26: 2100 movs r1, #0 8009c28: 1d1a adds r2, r3, #4 8009c2a: 602a str r2, [r5, #0] 8009c2c: 681d ldr r5, [r3, #0] 8009c2e: 6862 ldr r2, [r4, #4] 8009c30: 4628 mov r0, r5 8009c32: f001 fcf3 bl 800b61c 8009c36: b108 cbz r0, 8009c3c <_printf_i+0x1f4> 8009c38: 1b40 subs r0, r0, r5 8009c3a: 6060 str r0, [r4, #4] 8009c3c: 6863 ldr r3, [r4, #4] 8009c3e: 6123 str r3, [r4, #16] 8009c40: 2300 movs r3, #0 8009c42: f884 3043 strb.w r3, [r4, #67] ; 0x43 8009c46: e7a8 b.n 8009b9a <_printf_i+0x152> 8009c48: 462a mov r2, r5 8009c4a: 4649 mov r1, r9 8009c4c: 4640 mov r0, r8 8009c4e: 6923 ldr r3, [r4, #16] 8009c50: 47d0 blx sl 8009c52: 3001 adds r0, #1 8009c54: d0ab beq.n 8009bae <_printf_i+0x166> 8009c56: 6823 ldr r3, [r4, #0] 8009c58: 079b lsls r3, r3, #30 8009c5a: d413 bmi.n 8009c84 <_printf_i+0x23c> 8009c5c: 68e0 ldr r0, [r4, #12] 8009c5e: 9b03 ldr r3, [sp, #12] 8009c60: 4298 cmp r0, r3 8009c62: bfb8 it lt 8009c64: 4618 movlt r0, r3 8009c66: e7a4 b.n 8009bb2 <_printf_i+0x16a> 8009c68: 2301 movs r3, #1 8009c6a: 4632 mov r2, r6 8009c6c: 4649 mov r1, r9 8009c6e: 4640 mov r0, r8 8009c70: 47d0 blx sl 8009c72: 3001 adds r0, #1 8009c74: d09b beq.n 8009bae <_printf_i+0x166> 8009c76: 3501 adds r5, #1 8009c78: 68e3 ldr r3, [r4, #12] 8009c7a: 9903 ldr r1, [sp, #12] 8009c7c: 1a5b subs r3, r3, r1 8009c7e: 42ab cmp r3, r5 8009c80: dcf2 bgt.n 8009c68 <_printf_i+0x220> 8009c82: e7eb b.n 8009c5c <_printf_i+0x214> 8009c84: 2500 movs r5, #0 8009c86: f104 0619 add.w r6, r4, #25 8009c8a: e7f5 b.n 8009c78 <_printf_i+0x230> 8009c8c: 0800d3f0 .word 0x0800d3f0 8009c90: 0800d401 .word 0x0800d401 08009c94 : 8009c94: b40f push {r0, r1, r2, r3} 8009c96: 4b0a ldr r3, [pc, #40] ; (8009cc0 ) 8009c98: b513 push {r0, r1, r4, lr} 8009c9a: 681c ldr r4, [r3, #0] 8009c9c: b124 cbz r4, 8009ca8 8009c9e: 69a3 ldr r3, [r4, #24] 8009ca0: b913 cbnz r3, 8009ca8 8009ca2: 4620 mov r0, r4 8009ca4: f001 fb54 bl 800b350 <__sinit> 8009ca8: ab05 add r3, sp, #20 8009caa: 4620 mov r0, r4 8009cac: 9a04 ldr r2, [sp, #16] 8009cae: 68a1 ldr r1, [r4, #8] 8009cb0: 9301 str r3, [sp, #4] 8009cb2: f002 f88b bl 800bdcc <_vfiprintf_r> 8009cb6: b002 add sp, #8 8009cb8: e8bd 4010 ldmia.w sp!, {r4, lr} 8009cbc: b004 add sp, #16 8009cbe: 4770 bx lr 8009cc0: 20000014 .word 0x20000014 08009cc4 <_puts_r>: 8009cc4: b570 push {r4, r5, r6, lr} 8009cc6: 460e mov r6, r1 8009cc8: 4605 mov r5, r0 8009cca: b118 cbz r0, 8009cd4 <_puts_r+0x10> 8009ccc: 6983 ldr r3, [r0, #24] 8009cce: b90b cbnz r3, 8009cd4 <_puts_r+0x10> 8009cd0: f001 fb3e bl 800b350 <__sinit> 8009cd4: 69ab ldr r3, [r5, #24] 8009cd6: 68ac ldr r4, [r5, #8] 8009cd8: b913 cbnz r3, 8009ce0 <_puts_r+0x1c> 8009cda: 4628 mov r0, r5 8009cdc: f001 fb38 bl 800b350 <__sinit> 8009ce0: 4b2c ldr r3, [pc, #176] ; (8009d94 <_puts_r+0xd0>) 8009ce2: 429c cmp r4, r3 8009ce4: d120 bne.n 8009d28 <_puts_r+0x64> 8009ce6: 686c ldr r4, [r5, #4] 8009ce8: 6e63 ldr r3, [r4, #100] ; 0x64 8009cea: 07db lsls r3, r3, #31 8009cec: d405 bmi.n 8009cfa <_puts_r+0x36> 8009cee: 89a3 ldrh r3, [r4, #12] 8009cf0: 0598 lsls r0, r3, #22 8009cf2: d402 bmi.n 8009cfa <_puts_r+0x36> 8009cf4: 6da0 ldr r0, [r4, #88] ; 0x58 8009cf6: f001 fc29 bl 800b54c <__retarget_lock_acquire_recursive> 8009cfa: 89a3 ldrh r3, [r4, #12] 8009cfc: 0719 lsls r1, r3, #28 8009cfe: d51d bpl.n 8009d3c <_puts_r+0x78> 8009d00: 6923 ldr r3, [r4, #16] 8009d02: b1db cbz r3, 8009d3c <_puts_r+0x78> 8009d04: 3e01 subs r6, #1 8009d06: 68a3 ldr r3, [r4, #8] 8009d08: f816 1f01 ldrb.w r1, [r6, #1]! 8009d0c: 3b01 subs r3, #1 8009d0e: 60a3 str r3, [r4, #8] 8009d10: bb39 cbnz r1, 8009d62 <_puts_r+0x9e> 8009d12: 2b00 cmp r3, #0 8009d14: da38 bge.n 8009d88 <_puts_r+0xc4> 8009d16: 4622 mov r2, r4 8009d18: 210a movs r1, #10 8009d1a: 4628 mov r0, r5 8009d1c: f000 faaa bl 800a274 <__swbuf_r> 8009d20: 3001 adds r0, #1 8009d22: d011 beq.n 8009d48 <_puts_r+0x84> 8009d24: 250a movs r5, #10 8009d26: e011 b.n 8009d4c <_puts_r+0x88> 8009d28: 4b1b ldr r3, [pc, #108] ; (8009d98 <_puts_r+0xd4>) 8009d2a: 429c cmp r4, r3 8009d2c: d101 bne.n 8009d32 <_puts_r+0x6e> 8009d2e: 68ac ldr r4, [r5, #8] 8009d30: e7da b.n 8009ce8 <_puts_r+0x24> 8009d32: 4b1a ldr r3, [pc, #104] ; (8009d9c <_puts_r+0xd8>) 8009d34: 429c cmp r4, r3 8009d36: bf08 it eq 8009d38: 68ec ldreq r4, [r5, #12] 8009d3a: e7d5 b.n 8009ce8 <_puts_r+0x24> 8009d3c: 4621 mov r1, r4 8009d3e: 4628 mov r0, r5 8009d40: f000 faea bl 800a318 <__swsetup_r> 8009d44: 2800 cmp r0, #0 8009d46: d0dd beq.n 8009d04 <_puts_r+0x40> 8009d48: f04f 35ff mov.w r5, #4294967295 ; 0xffffffff 8009d4c: 6e63 ldr r3, [r4, #100] ; 0x64 8009d4e: 07da lsls r2, r3, #31 8009d50: d405 bmi.n 8009d5e <_puts_r+0x9a> 8009d52: 89a3 ldrh r3, [r4, #12] 8009d54: 059b lsls r3, r3, #22 8009d56: d402 bmi.n 8009d5e <_puts_r+0x9a> 8009d58: 6da0 ldr r0, [r4, #88] ; 0x58 8009d5a: f001 fbf9 bl 800b550 <__retarget_lock_release_recursive> 8009d5e: 4628 mov r0, r5 8009d60: bd70 pop {r4, r5, r6, pc} 8009d62: 2b00 cmp r3, #0 8009d64: da04 bge.n 8009d70 <_puts_r+0xac> 8009d66: 69a2 ldr r2, [r4, #24] 8009d68: 429a cmp r2, r3 8009d6a: dc06 bgt.n 8009d7a <_puts_r+0xb6> 8009d6c: 290a cmp r1, #10 8009d6e: d004 beq.n 8009d7a <_puts_r+0xb6> 8009d70: 6823 ldr r3, [r4, #0] 8009d72: 1c5a adds r2, r3, #1 8009d74: 6022 str r2, [r4, #0] 8009d76: 7019 strb r1, [r3, #0] 8009d78: e7c5 b.n 8009d06 <_puts_r+0x42> 8009d7a: 4622 mov r2, r4 8009d7c: 4628 mov r0, r5 8009d7e: f000 fa79 bl 800a274 <__swbuf_r> 8009d82: 3001 adds r0, #1 8009d84: d1bf bne.n 8009d06 <_puts_r+0x42> 8009d86: e7df b.n 8009d48 <_puts_r+0x84> 8009d88: 250a movs r5, #10 8009d8a: 6823 ldr r3, [r4, #0] 8009d8c: 1c5a adds r2, r3, #1 8009d8e: 6022 str r2, [r4, #0] 8009d90: 701d strb r5, [r3, #0] 8009d92: e7db b.n 8009d4c <_puts_r+0x88> 8009d94: 0800d524 .word 0x0800d524 8009d98: 0800d544 .word 0x0800d544 8009d9c: 0800d504 .word 0x0800d504 08009da0 : 8009da0: 4b02 ldr r3, [pc, #8] ; (8009dac ) 8009da2: 4601 mov r1, r0 8009da4: 6818 ldr r0, [r3, #0] 8009da6: f7ff bf8d b.w 8009cc4 <_puts_r> 8009daa: bf00 nop 8009dac: 20000014 .word 0x20000014 08009db0 <_sbrk_r>: 8009db0: b538 push {r3, r4, r5, lr} 8009db2: 2300 movs r3, #0 8009db4: 4d05 ldr r5, [pc, #20] ; (8009dcc <_sbrk_r+0x1c>) 8009db6: 4604 mov r4, r0 8009db8: 4608 mov r0, r1 8009dba: 602b str r3, [r5, #0] 8009dbc: f7fb f8a4 bl 8004f08 <_sbrk> 8009dc0: 1c43 adds r3, r0, #1 8009dc2: d102 bne.n 8009dca <_sbrk_r+0x1a> 8009dc4: 682b ldr r3, [r5, #0] 8009dc6: b103 cbz r3, 8009dca <_sbrk_r+0x1a> 8009dc8: 6023 str r3, [r4, #0] 8009dca: bd38 pop {r3, r4, r5, pc} 8009dcc: 200033cc .word 0x200033cc 08009dd0 : 8009dd0: 4603 mov r3, r0 8009dd2: b510 push {r4, lr} 8009dd4: b172 cbz r2, 8009df4 8009dd6: 3901 subs r1, #1 8009dd8: 1884 adds r4, r0, r2 8009dda: f813 0b01 ldrb.w r0, [r3], #1 8009dde: f811 2f01 ldrb.w r2, [r1, #1]! 8009de2: 4290 cmp r0, r2 8009de4: d101 bne.n 8009dea 8009de6: 42a3 cmp r3, r4 8009de8: d101 bne.n 8009dee 8009dea: 1a80 subs r0, r0, r2 8009dec: bd10 pop {r4, pc} 8009dee: 2800 cmp r0, #0 8009df0: d1f3 bne.n 8009dda 8009df2: e7fa b.n 8009dea 8009df4: 4610 mov r0, r2 8009df6: e7f9 b.n 8009dec 08009df8 <__tzcalc_limits>: 8009df8: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8009dfc: 4605 mov r5, r0 8009dfe: f001 fb9b bl 800b538 <__gettzinfo> 8009e02: f240 73b1 movw r3, #1969 ; 0x7b1 8009e06: 429d cmp r5, r3 8009e08: f340 809a ble.w 8009f40 <__tzcalc_limits+0x148> 8009e0c: f46f 62f6 mvn.w r2, #1968 ; 0x7b0 8009e10: 18ac adds r4, r5, r2 8009e12: f240 126d movw r2, #365 ; 0x16d 8009e16: f2a5 73b2 subw r3, r5, #1970 ; 0x7b2 8009e1a: 10a4 asrs r4, r4, #2 8009e1c: fb02 4403 mla r4, r2, r3, r4 8009e20: f06f 0263 mvn.w r2, #99 ; 0x63 8009e24: f2a5 736d subw r3, r5, #1901 ; 0x76d 8009e28: fb93 f3f2 sdiv r3, r3, r2 8009e2c: f46f 61c8 mvn.w r1, #1600 ; 0x640 8009e30: 441c add r4, r3 8009e32: f44f 73c8 mov.w r3, #400 ; 0x190 8009e36: 186a adds r2, r5, r1 8009e38: fbb2 f2f3 udiv r2, r2, r3 8009e3c: fb95 fcf3 sdiv ip, r5, r3 8009e40: 4414 add r4, r2 8009e42: 2264 movs r2, #100 ; 0x64 8009e44: fb03 5c1c mls ip, r3, ip, r5 8009e48: fb95 f7f2 sdiv r7, r5, r2 8009e4c: fabc f68c clz r6, ip 8009e50: 4601 mov r1, r0 8009e52: fb02 5717 mls r7, r2, r7, r5 8009e56: 6045 str r5, [r0, #4] 8009e58: 0976 lsrs r6, r6, #5 8009e5a: f100 0b50 add.w fp, r0, #80 ; 0x50 8009e5e: f005 0203 and.w r2, r5, #3 8009e62: 7a0d ldrb r5, [r1, #8] 8009e64: 694b ldr r3, [r1, #20] 8009e66: 2d4a cmp r5, #74 ; 0x4a 8009e68: d12d bne.n 8009ec6 <__tzcalc_limits+0xce> 8009e6a: eb04 0e03 add.w lr, r4, r3 8009e6e: b902 cbnz r2, 8009e72 <__tzcalc_limits+0x7a> 8009e70: b917 cbnz r7, 8009e78 <__tzcalc_limits+0x80> 8009e72: f1bc 0f00 cmp.w ip, #0 8009e76: d124 bne.n 8009ec2 <__tzcalc_limits+0xca> 8009e78: 2b3b cmp r3, #59 ; 0x3b 8009e7a: bfd4 ite le 8009e7c: 2300 movle r3, #0 8009e7e: 2301 movgt r3, #1 8009e80: 4473 add r3, lr 8009e82: 3b01 subs r3, #1 8009e84: 698d ldr r5, [r1, #24] 8009e86: f8df 80bc ldr.w r8, [pc, #188] ; 8009f44 <__tzcalc_limits+0x14c> 8009e8a: ea4f 7ee5 mov.w lr, r5, asr #31 8009e8e: fbc3 5e08 smlal r5, lr, r3, r8 8009e92: 6a8b ldr r3, [r1, #40] ; 0x28 8009e94: 18ed adds r5, r5, r3 8009e96: eb4e 73e3 adc.w r3, lr, r3, asr #31 8009e9a: e9c1 5308 strd r5, r3, [r1, #32] 8009e9e: 3128 adds r1, #40 ; 0x28 8009ea0: 458b cmp fp, r1 8009ea2: d1de bne.n 8009e62 <__tzcalc_limits+0x6a> 8009ea4: e9d0 1312 ldrd r1, r3, [r0, #72] ; 0x48 8009ea8: e9d0 4208 ldrd r4, r2, [r0, #32] 8009eac: 428c cmp r4, r1 8009eae: eb72 0303 sbcs.w r3, r2, r3 8009eb2: bfb4 ite lt 8009eb4: 2301 movlt r3, #1 8009eb6: 2300 movge r3, #0 8009eb8: 6003 str r3, [r0, #0] 8009eba: 2001 movs r0, #1 8009ebc: b003 add sp, #12 8009ebe: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8009ec2: 2300 movs r3, #0 8009ec4: e7dc b.n 8009e80 <__tzcalc_limits+0x88> 8009ec6: 2d44 cmp r5, #68 ; 0x44 8009ec8: d101 bne.n 8009ece <__tzcalc_limits+0xd6> 8009eca: 4423 add r3, r4 8009ecc: e7da b.n 8009e84 <__tzcalc_limits+0x8c> 8009ece: bb8a cbnz r2, 8009f34 <__tzcalc_limits+0x13c> 8009ed0: 2f00 cmp r7, #0 8009ed2: bf0c ite eq 8009ed4: 4635 moveq r5, r6 8009ed6: 2501 movne r5, #1 8009ed8: f04f 0a30 mov.w sl, #48 ; 0x30 8009edc: f8d1 e00c ldr.w lr, [r1, #12] 8009ee0: f04f 0800 mov.w r8, #0 8009ee4: f8cd e004 str.w lr, [sp, #4] 8009ee8: 46a6 mov lr, r4 8009eea: f8df 905c ldr.w r9, [pc, #92] ; 8009f48 <__tzcalc_limits+0x150> 8009eee: fb0a 9505 mla r5, sl, r5, r9 8009ef2: 3d04 subs r5, #4 8009ef4: f8dd a004 ldr.w sl, [sp, #4] 8009ef8: f108 0801 add.w r8, r8, #1 8009efc: 45c2 cmp sl, r8 8009efe: f855 9028 ldr.w r9, [r5, r8, lsl #2] 8009f02: dc19 bgt.n 8009f38 <__tzcalc_limits+0x140> 8009f04: f04f 0807 mov.w r8, #7 8009f08: f10e 0504 add.w r5, lr, #4 8009f0c: fb95 f8f8 sdiv r8, r5, r8 8009f10: ebc8 08c8 rsb r8, r8, r8, lsl #3 8009f14: eba5 0808 sub.w r8, r5, r8 8009f18: ebb3 0808 subs.w r8, r3, r8 8009f1c: 690b ldr r3, [r1, #16] 8009f1e: bf48 it mi 8009f20: f108 0807 addmi.w r8, r8, #7 8009f24: 3b01 subs r3, #1 8009f26: ebc3 03c3 rsb r3, r3, r3, lsl #3 8009f2a: 4443 add r3, r8 8009f2c: 454b cmp r3, r9 8009f2e: da05 bge.n 8009f3c <__tzcalc_limits+0x144> 8009f30: 4473 add r3, lr 8009f32: e7a7 b.n 8009e84 <__tzcalc_limits+0x8c> 8009f34: 4635 mov r5, r6 8009f36: e7cf b.n 8009ed8 <__tzcalc_limits+0xe0> 8009f38: 44ce add lr, r9 8009f3a: e7db b.n 8009ef4 <__tzcalc_limits+0xfc> 8009f3c: 3b07 subs r3, #7 8009f3e: e7f5 b.n 8009f2c <__tzcalc_limits+0x134> 8009f40: 2000 movs r0, #0 8009f42: e7bb b.n 8009ebc <__tzcalc_limits+0xc4> 8009f44: 00015180 .word 0x00015180 8009f48: 0800d380 .word 0x0800d380 08009f4c <__tz_lock>: 8009f4c: 4801 ldr r0, [pc, #4] ; (8009f54 <__tz_lock+0x8>) 8009f4e: f001 bafc b.w 800b54a <__retarget_lock_acquire> 8009f52: bf00 nop 8009f54: 200033c8 .word 0x200033c8 08009f58 <__tz_unlock>: 8009f58: 4801 ldr r0, [pc, #4] ; (8009f60 <__tz_unlock+0x8>) 8009f5a: f001 baf8 b.w 800b54e <__retarget_lock_release> 8009f5e: bf00 nop 8009f60: 200033c8 .word 0x200033c8 08009f64 <_tzset_unlocked>: 8009f64: 4b01 ldr r3, [pc, #4] ; (8009f6c <_tzset_unlocked+0x8>) 8009f66: 6818 ldr r0, [r3, #0] 8009f68: f000 b802 b.w 8009f70 <_tzset_unlocked_r> 8009f6c: 20000014 .word 0x20000014 08009f70 <_tzset_unlocked_r>: 8009f70: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8009f74: b08d sub sp, #52 ; 0x34 8009f76: 4607 mov r7, r0 8009f78: f001 fade bl 800b538 <__gettzinfo> 8009f7c: 49b1 ldr r1, [pc, #708] ; (800a244 <_tzset_unlocked_r+0x2d4>) 8009f7e: 4605 mov r5, r0 8009f80: 4638 mov r0, r7 8009f82: f001 fad1 bl 800b528 <_getenv_r> 8009f86: 4eb0 ldr r6, [pc, #704] ; (800a248 <_tzset_unlocked_r+0x2d8>) 8009f88: 4604 mov r4, r0 8009f8a: b970 cbnz r0, 8009faa <_tzset_unlocked_r+0x3a> 8009f8c: 4baf ldr r3, [pc, #700] ; (800a24c <_tzset_unlocked_r+0x2dc>) 8009f8e: 4ab0 ldr r2, [pc, #704] ; (800a250 <_tzset_unlocked_r+0x2e0>) 8009f90: 6018 str r0, [r3, #0] 8009f92: 4bb0 ldr r3, [pc, #704] ; (800a254 <_tzset_unlocked_r+0x2e4>) 8009f94: 6018 str r0, [r3, #0] 8009f96: 4bb0 ldr r3, [pc, #704] ; (800a258 <_tzset_unlocked_r+0x2e8>) 8009f98: 6830 ldr r0, [r6, #0] 8009f9a: e9c3 2200 strd r2, r2, [r3] 8009f9e: f7ff f91f bl 80091e0 8009fa2: 6034 str r4, [r6, #0] 8009fa4: b00d add sp, #52 ; 0x34 8009fa6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8009faa: 6831 ldr r1, [r6, #0] 8009fac: 2900 cmp r1, #0 8009fae: d162 bne.n 800a076 <_tzset_unlocked_r+0x106> 8009fb0: 6830 ldr r0, [r6, #0] 8009fb2: f7ff f915 bl 80091e0 8009fb6: 4620 mov r0, r4 8009fb8: f7f6 f936 bl 8000228 8009fbc: 1c41 adds r1, r0, #1 8009fbe: 4638 mov r0, r7 8009fc0: f7ff f994 bl 80092ec <_malloc_r> 8009fc4: 6030 str r0, [r6, #0] 8009fc6: 2800 cmp r0, #0 8009fc8: d15a bne.n 800a080 <_tzset_unlocked_r+0x110> 8009fca: 7823 ldrb r3, [r4, #0] 8009fcc: ae0a add r6, sp, #40 ; 0x28 8009fce: 2b3a cmp r3, #58 ; 0x3a 8009fd0: bf08 it eq 8009fd2: 3401 addeq r4, #1 8009fd4: 4633 mov r3, r6 8009fd6: 4620 mov r0, r4 8009fd8: 4aa0 ldr r2, [pc, #640] ; (800a25c <_tzset_unlocked_r+0x2ec>) 8009fda: 49a1 ldr r1, [pc, #644] ; (800a260 <_tzset_unlocked_r+0x2f0>) 8009fdc: f002 f826 bl 800c02c 8009fe0: 2800 cmp r0, #0 8009fe2: dddf ble.n 8009fa4 <_tzset_unlocked_r+0x34> 8009fe4: 9b0a ldr r3, [sp, #40] ; 0x28 8009fe6: 18e7 adds r7, r4, r3 8009fe8: 5ce3 ldrb r3, [r4, r3] 8009fea: 2b2d cmp r3, #45 ; 0x2d 8009fec: d14c bne.n 800a088 <_tzset_unlocked_r+0x118> 8009fee: f04f 38ff mov.w r8, #4294967295 ; 0xffffffff 8009ff2: 3701 adds r7, #1 8009ff4: 2400 movs r4, #0 8009ff6: f10d 0a20 add.w sl, sp, #32 8009ffa: f10d 0b1e add.w fp, sp, #30 8009ffe: 4633 mov r3, r6 800a000: 4638 mov r0, r7 800a002: e9cd 6a01 strd r6, sl, [sp, #4] 800a006: 4997 ldr r1, [pc, #604] ; (800a264 <_tzset_unlocked_r+0x2f4>) 800a008: 9603 str r6, [sp, #12] 800a00a: f8cd b000 str.w fp, [sp] 800a00e: aa07 add r2, sp, #28 800a010: f8ad 401e strh.w r4, [sp, #30] 800a014: f8ad 4020 strh.w r4, [sp, #32] 800a018: f002 f808 bl 800c02c 800a01c: 42a0 cmp r0, r4 800a01e: ddc1 ble.n 8009fa4 <_tzset_unlocked_r+0x34> 800a020: 213c movs r1, #60 ; 0x3c 800a022: f8bd 201e ldrh.w r2, [sp, #30] 800a026: f8bd 3020 ldrh.w r3, [sp, #32] 800a02a: f8df 923c ldr.w r9, [pc, #572] ; 800a268 <_tzset_unlocked_r+0x2f8> 800a02e: fb01 3302 mla r3, r1, r2, r3 800a032: f44f 6161 mov.w r1, #3600 ; 0xe10 800a036: f8bd 201c ldrh.w r2, [sp, #28] 800a03a: fb01 3302 mla r3, r1, r2, r3 800a03e: fb08 f303 mul.w r3, r8, r3 800a042: f8df 8214 ldr.w r8, [pc, #532] ; 800a258 <_tzset_unlocked_r+0x2e8> 800a046: 62ab str r3, [r5, #40] ; 0x28 800a048: 4b84 ldr r3, [pc, #528] ; (800a25c <_tzset_unlocked_r+0x2ec>) 800a04a: 464a mov r2, r9 800a04c: f8c8 3000 str.w r3, [r8] 800a050: 9b0a ldr r3, [sp, #40] ; 0x28 800a052: 4983 ldr r1, [pc, #524] ; (800a260 <_tzset_unlocked_r+0x2f0>) 800a054: 441f add r7, r3 800a056: 4638 mov r0, r7 800a058: 4633 mov r3, r6 800a05a: f001 ffe7 bl 800c02c 800a05e: 42a0 cmp r0, r4 800a060: dc18 bgt.n 800a094 <_tzset_unlocked_r+0x124> 800a062: f8d8 3000 ldr.w r3, [r8] 800a066: 6aaa ldr r2, [r5, #40] ; 0x28 800a068: f8c8 3004 str.w r3, [r8, #4] 800a06c: 4b77 ldr r3, [pc, #476] ; (800a24c <_tzset_unlocked_r+0x2dc>) 800a06e: 601a str r2, [r3, #0] 800a070: 4b78 ldr r3, [pc, #480] ; (800a254 <_tzset_unlocked_r+0x2e4>) 800a072: 601c str r4, [r3, #0] 800a074: e796 b.n 8009fa4 <_tzset_unlocked_r+0x34> 800a076: f7f6 f8df bl 8000238 800a07a: 2800 cmp r0, #0 800a07c: d198 bne.n 8009fb0 <_tzset_unlocked_r+0x40> 800a07e: e791 b.n 8009fa4 <_tzset_unlocked_r+0x34> 800a080: 4621 mov r1, r4 800a082: f002 f842 bl 800c10a 800a086: e7a0 b.n 8009fca <_tzset_unlocked_r+0x5a> 800a088: 2b2b cmp r3, #43 ; 0x2b 800a08a: f04f 0801 mov.w r8, #1 800a08e: bf08 it eq 800a090: 3701 addeq r7, #1 800a092: e7af b.n 8009ff4 <_tzset_unlocked_r+0x84> 800a094: 9b0a ldr r3, [sp, #40] ; 0x28 800a096: f8c8 9004 str.w r9, [r8, #4] 800a09a: 18fc adds r4, r7, r3 800a09c: 5cfb ldrb r3, [r7, r3] 800a09e: 2b2d cmp r3, #45 ; 0x2d 800a0a0: f040 808c bne.w 800a1bc <_tzset_unlocked_r+0x24c> 800a0a4: f04f 37ff mov.w r7, #4294967295 ; 0xffffffff 800a0a8: 3401 adds r4, #1 800a0aa: 2300 movs r3, #0 800a0ac: 4620 mov r0, r4 800a0ae: f8ad 301c strh.w r3, [sp, #28] 800a0b2: f8ad 301e strh.w r3, [sp, #30] 800a0b6: f8ad 3020 strh.w r3, [sp, #32] 800a0ba: 930a str r3, [sp, #40] ; 0x28 800a0bc: e9cd a602 strd sl, r6, [sp, #8] 800a0c0: 4633 mov r3, r6 800a0c2: e9cd b600 strd fp, r6, [sp] 800a0c6: 4967 ldr r1, [pc, #412] ; (800a264 <_tzset_unlocked_r+0x2f4>) 800a0c8: aa07 add r2, sp, #28 800a0ca: f001 ffaf bl 800c02c 800a0ce: 2800 cmp r0, #0 800a0d0: dc7a bgt.n 800a1c8 <_tzset_unlocked_r+0x258> 800a0d2: 6aab ldr r3, [r5, #40] ; 0x28 800a0d4: f5a3 6361 sub.w r3, r3, #3600 ; 0xe10 800a0d8: 462f mov r7, r5 800a0da: f04f 0900 mov.w r9, #0 800a0de: 652b str r3, [r5, #80] ; 0x50 800a0e0: 9b0a ldr r3, [sp, #40] ; 0x28 800a0e2: 441c add r4, r3 800a0e4: 7823 ldrb r3, [r4, #0] 800a0e6: 2b2c cmp r3, #44 ; 0x2c 800a0e8: bf08 it eq 800a0ea: 3401 addeq r4, #1 800a0ec: f894 8000 ldrb.w r8, [r4] 800a0f0: f1b8 0f4d cmp.w r8, #77 ; 0x4d 800a0f4: d17a bne.n 800a1ec <_tzset_unlocked_r+0x27c> 800a0f6: f10d 0326 add.w r3, sp, #38 ; 0x26 800a0fa: e9cd 6301 strd r6, r3, [sp, #4] 800a0fe: ab09 add r3, sp, #36 ; 0x24 800a100: 9300 str r3, [sp, #0] 800a102: 4620 mov r0, r4 800a104: 4633 mov r3, r6 800a106: 4959 ldr r1, [pc, #356] ; (800a26c <_tzset_unlocked_r+0x2fc>) 800a108: 9603 str r6, [sp, #12] 800a10a: f10d 0222 add.w r2, sp, #34 ; 0x22 800a10e: f001 ff8d bl 800c02c 800a112: 2803 cmp r0, #3 800a114: f47f af46 bne.w 8009fa4 <_tzset_unlocked_r+0x34> 800a118: f8bd 1022 ldrh.w r1, [sp, #34] ; 0x22 800a11c: 1e4b subs r3, r1, #1 800a11e: 2b0b cmp r3, #11 800a120: f63f af40 bhi.w 8009fa4 <_tzset_unlocked_r+0x34> 800a124: f8bd 2024 ldrh.w r2, [sp, #36] ; 0x24 800a128: 1e53 subs r3, r2, #1 800a12a: 2b04 cmp r3, #4 800a12c: f63f af3a bhi.w 8009fa4 <_tzset_unlocked_r+0x34> 800a130: f8bd 3026 ldrh.w r3, [sp, #38] ; 0x26 800a134: 2b06 cmp r3, #6 800a136: f63f af35 bhi.w 8009fa4 <_tzset_unlocked_r+0x34> 800a13a: e9c7 1203 strd r1, r2, [r7, #12] 800a13e: f887 8008 strb.w r8, [r7, #8] 800a142: 617b str r3, [r7, #20] 800a144: 9b0a ldr r3, [sp, #40] ; 0x28 800a146: eb04 0803 add.w r8, r4, r3 800a14a: 2302 movs r3, #2 800a14c: f8ad 301c strh.w r3, [sp, #28] 800a150: 2300 movs r3, #0 800a152: f8ad 301e strh.w r3, [sp, #30] 800a156: f8ad 3020 strh.w r3, [sp, #32] 800a15a: 930a str r3, [sp, #40] ; 0x28 800a15c: f898 3000 ldrb.w r3, [r8] 800a160: 2b2f cmp r3, #47 ; 0x2f 800a162: d109 bne.n 800a178 <_tzset_unlocked_r+0x208> 800a164: 4633 mov r3, r6 800a166: 4640 mov r0, r8 800a168: e9cd a602 strd sl, r6, [sp, #8] 800a16c: e9cd b600 strd fp, r6, [sp] 800a170: 493f ldr r1, [pc, #252] ; (800a270 <_tzset_unlocked_r+0x300>) 800a172: aa07 add r2, sp, #28 800a174: f001 ff5a bl 800c02c 800a178: 213c movs r1, #60 ; 0x3c 800a17a: f8bd 201e ldrh.w r2, [sp, #30] 800a17e: f8bd 3020 ldrh.w r3, [sp, #32] 800a182: 3728 adds r7, #40 ; 0x28 800a184: fb01 3302 mla r3, r1, r2, r3 800a188: f44f 6161 mov.w r1, #3600 ; 0xe10 800a18c: f8bd 201c ldrh.w r2, [sp, #28] 800a190: fb01 3302 mla r3, r1, r2, r3 800a194: f847 3c10 str.w r3, [r7, #-16] 800a198: 9c0a ldr r4, [sp, #40] ; 0x28 800a19a: 4444 add r4, r8 800a19c: f1b9 0f00 cmp.w r9, #0 800a1a0: d021 beq.n 800a1e6 <_tzset_unlocked_r+0x276> 800a1a2: 6868 ldr r0, [r5, #4] 800a1a4: f7ff fe28 bl 8009df8 <__tzcalc_limits> 800a1a8: 6aaa ldr r2, [r5, #40] ; 0x28 800a1aa: 4b28 ldr r3, [pc, #160] ; (800a24c <_tzset_unlocked_r+0x2dc>) 800a1ac: 601a str r2, [r3, #0] 800a1ae: 6d2b ldr r3, [r5, #80] ; 0x50 800a1b0: 1a9b subs r3, r3, r2 800a1b2: bf18 it ne 800a1b4: 2301 movne r3, #1 800a1b6: 4a27 ldr r2, [pc, #156] ; (800a254 <_tzset_unlocked_r+0x2e4>) 800a1b8: 6013 str r3, [r2, #0] 800a1ba: e6f3 b.n 8009fa4 <_tzset_unlocked_r+0x34> 800a1bc: 2b2b cmp r3, #43 ; 0x2b 800a1be: f04f 0701 mov.w r7, #1 800a1c2: bf08 it eq 800a1c4: 3401 addeq r4, #1 800a1c6: e770 b.n 800a0aa <_tzset_unlocked_r+0x13a> 800a1c8: 213c movs r1, #60 ; 0x3c 800a1ca: f8bd 201e ldrh.w r2, [sp, #30] 800a1ce: f8bd 3020 ldrh.w r3, [sp, #32] 800a1d2: fb01 3302 mla r3, r1, r2, r3 800a1d6: f44f 6161 mov.w r1, #3600 ; 0xe10 800a1da: f8bd 201c ldrh.w r2, [sp, #28] 800a1de: fb01 3302 mla r3, r1, r2, r3 800a1e2: 437b muls r3, r7 800a1e4: e778 b.n 800a0d8 <_tzset_unlocked_r+0x168> 800a1e6: f04f 0901 mov.w r9, #1 800a1ea: e77b b.n 800a0e4 <_tzset_unlocked_r+0x174> 800a1ec: f1b8 0f4a cmp.w r8, #74 ; 0x4a 800a1f0: bf0a itet eq 800a1f2: 4643 moveq r3, r8 800a1f4: 2344 movne r3, #68 ; 0x44 800a1f6: 3401 addeq r4, #1 800a1f8: 220a movs r2, #10 800a1fa: 4620 mov r0, r4 800a1fc: a90b add r1, sp, #44 ; 0x2c 800a1fe: 9305 str r3, [sp, #20] 800a200: f002 f800 bl 800c204 800a204: f8dd 802c ldr.w r8, [sp, #44] ; 0x2c 800a208: 9b05 ldr r3, [sp, #20] 800a20a: 45a0 cmp r8, r4 800a20c: f8ad 0026 strh.w r0, [sp, #38] ; 0x26 800a210: d114 bne.n 800a23c <_tzset_unlocked_r+0x2cc> 800a212: 234d movs r3, #77 ; 0x4d 800a214: f1b9 0f00 cmp.w r9, #0 800a218: d107 bne.n 800a22a <_tzset_unlocked_r+0x2ba> 800a21a: 2103 movs r1, #3 800a21c: 722b strb r3, [r5, #8] 800a21e: 2302 movs r3, #2 800a220: f8c5 9014 str.w r9, [r5, #20] 800a224: e9c5 1303 strd r1, r3, [r5, #12] 800a228: e78f b.n 800a14a <_tzset_unlocked_r+0x1da> 800a22a: 220b movs r2, #11 800a22c: f885 3030 strb.w r3, [r5, #48] ; 0x30 800a230: 2301 movs r3, #1 800a232: e9c5 230d strd r2, r3, [r5, #52] ; 0x34 800a236: 2300 movs r3, #0 800a238: 63eb str r3, [r5, #60] ; 0x3c 800a23a: e786 b.n 800a14a <_tzset_unlocked_r+0x1da> 800a23c: b280 uxth r0, r0 800a23e: 723b strb r3, [r7, #8] 800a240: 6178 str r0, [r7, #20] 800a242: e782 b.n 800a14a <_tzset_unlocked_r+0x1da> 800a244: 0800d412 .word 0x0800d412 800a248: 200033b8 .word 0x200033b8 800a24c: 200033c0 .word 0x200033c0 800a250: 0800d415 .word 0x0800d415 800a254: 200033bc .word 0x200033bc 800a258: 20000078 .word 0x20000078 800a25c: 200033ab .word 0x200033ab 800a260: 0800d419 .word 0x0800d419 800a264: 0800d43c .word 0x0800d43c 800a268: 200033a0 .word 0x200033a0 800a26c: 0800d428 .word 0x0800d428 800a270: 0800d43b .word 0x0800d43b 0800a274 <__swbuf_r>: 800a274: b5f8 push {r3, r4, r5, r6, r7, lr} 800a276: 460e mov r6, r1 800a278: 4614 mov r4, r2 800a27a: 4605 mov r5, r0 800a27c: b118 cbz r0, 800a286 <__swbuf_r+0x12> 800a27e: 6983 ldr r3, [r0, #24] 800a280: b90b cbnz r3, 800a286 <__swbuf_r+0x12> 800a282: f001 f865 bl 800b350 <__sinit> 800a286: 4b21 ldr r3, [pc, #132] ; (800a30c <__swbuf_r+0x98>) 800a288: 429c cmp r4, r3 800a28a: d12b bne.n 800a2e4 <__swbuf_r+0x70> 800a28c: 686c ldr r4, [r5, #4] 800a28e: 69a3 ldr r3, [r4, #24] 800a290: 60a3 str r3, [r4, #8] 800a292: 89a3 ldrh r3, [r4, #12] 800a294: 071a lsls r2, r3, #28 800a296: d52f bpl.n 800a2f8 <__swbuf_r+0x84> 800a298: 6923 ldr r3, [r4, #16] 800a29a: b36b cbz r3, 800a2f8 <__swbuf_r+0x84> 800a29c: 6923 ldr r3, [r4, #16] 800a29e: 6820 ldr r0, [r4, #0] 800a2a0: b2f6 uxtb r6, r6 800a2a2: 1ac0 subs r0, r0, r3 800a2a4: 6963 ldr r3, [r4, #20] 800a2a6: 4637 mov r7, r6 800a2a8: 4283 cmp r3, r0 800a2aa: dc04 bgt.n 800a2b6 <__swbuf_r+0x42> 800a2ac: 4621 mov r1, r4 800a2ae: 4628 mov r0, r5 800a2b0: f000 ffba bl 800b228 <_fflush_r> 800a2b4: bb30 cbnz r0, 800a304 <__swbuf_r+0x90> 800a2b6: 68a3 ldr r3, [r4, #8] 800a2b8: 3001 adds r0, #1 800a2ba: 3b01 subs r3, #1 800a2bc: 60a3 str r3, [r4, #8] 800a2be: 6823 ldr r3, [r4, #0] 800a2c0: 1c5a adds r2, r3, #1 800a2c2: 6022 str r2, [r4, #0] 800a2c4: 701e strb r6, [r3, #0] 800a2c6: 6963 ldr r3, [r4, #20] 800a2c8: 4283 cmp r3, r0 800a2ca: d004 beq.n 800a2d6 <__swbuf_r+0x62> 800a2cc: 89a3 ldrh r3, [r4, #12] 800a2ce: 07db lsls r3, r3, #31 800a2d0: d506 bpl.n 800a2e0 <__swbuf_r+0x6c> 800a2d2: 2e0a cmp r6, #10 800a2d4: d104 bne.n 800a2e0 <__swbuf_r+0x6c> 800a2d6: 4621 mov r1, r4 800a2d8: 4628 mov r0, r5 800a2da: f000 ffa5 bl 800b228 <_fflush_r> 800a2de: b988 cbnz r0, 800a304 <__swbuf_r+0x90> 800a2e0: 4638 mov r0, r7 800a2e2: bdf8 pop {r3, r4, r5, r6, r7, pc} 800a2e4: 4b0a ldr r3, [pc, #40] ; (800a310 <__swbuf_r+0x9c>) 800a2e6: 429c cmp r4, r3 800a2e8: d101 bne.n 800a2ee <__swbuf_r+0x7a> 800a2ea: 68ac ldr r4, [r5, #8] 800a2ec: e7cf b.n 800a28e <__swbuf_r+0x1a> 800a2ee: 4b09 ldr r3, [pc, #36] ; (800a314 <__swbuf_r+0xa0>) 800a2f0: 429c cmp r4, r3 800a2f2: bf08 it eq 800a2f4: 68ec ldreq r4, [r5, #12] 800a2f6: e7ca b.n 800a28e <__swbuf_r+0x1a> 800a2f8: 4621 mov r1, r4 800a2fa: 4628 mov r0, r5 800a2fc: f000 f80c bl 800a318 <__swsetup_r> 800a300: 2800 cmp r0, #0 800a302: d0cb beq.n 800a29c <__swbuf_r+0x28> 800a304: f04f 37ff mov.w r7, #4294967295 ; 0xffffffff 800a308: e7ea b.n 800a2e0 <__swbuf_r+0x6c> 800a30a: bf00 nop 800a30c: 0800d524 .word 0x0800d524 800a310: 0800d544 .word 0x0800d544 800a314: 0800d504 .word 0x0800d504 0800a318 <__swsetup_r>: 800a318: 4b32 ldr r3, [pc, #200] ; (800a3e4 <__swsetup_r+0xcc>) 800a31a: b570 push {r4, r5, r6, lr} 800a31c: 681d ldr r5, [r3, #0] 800a31e: 4606 mov r6, r0 800a320: 460c mov r4, r1 800a322: b125 cbz r5, 800a32e <__swsetup_r+0x16> 800a324: 69ab ldr r3, [r5, #24] 800a326: b913 cbnz r3, 800a32e <__swsetup_r+0x16> 800a328: 4628 mov r0, r5 800a32a: f001 f811 bl 800b350 <__sinit> 800a32e: 4b2e ldr r3, [pc, #184] ; (800a3e8 <__swsetup_r+0xd0>) 800a330: 429c cmp r4, r3 800a332: d10f bne.n 800a354 <__swsetup_r+0x3c> 800a334: 686c ldr r4, [r5, #4] 800a336: 89a3 ldrh r3, [r4, #12] 800a338: f9b4 200c ldrsh.w r2, [r4, #12] 800a33c: 0719 lsls r1, r3, #28 800a33e: d42c bmi.n 800a39a <__swsetup_r+0x82> 800a340: 06dd lsls r5, r3, #27 800a342: d411 bmi.n 800a368 <__swsetup_r+0x50> 800a344: 2309 movs r3, #9 800a346: 6033 str r3, [r6, #0] 800a348: f042 0340 orr.w r3, r2, #64 ; 0x40 800a34c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800a350: 81a3 strh r3, [r4, #12] 800a352: e03e b.n 800a3d2 <__swsetup_r+0xba> 800a354: 4b25 ldr r3, [pc, #148] ; (800a3ec <__swsetup_r+0xd4>) 800a356: 429c cmp r4, r3 800a358: d101 bne.n 800a35e <__swsetup_r+0x46> 800a35a: 68ac ldr r4, [r5, #8] 800a35c: e7eb b.n 800a336 <__swsetup_r+0x1e> 800a35e: 4b24 ldr r3, [pc, #144] ; (800a3f0 <__swsetup_r+0xd8>) 800a360: 429c cmp r4, r3 800a362: bf08 it eq 800a364: 68ec ldreq r4, [r5, #12] 800a366: e7e6 b.n 800a336 <__swsetup_r+0x1e> 800a368: 0758 lsls r0, r3, #29 800a36a: d512 bpl.n 800a392 <__swsetup_r+0x7a> 800a36c: 6b61 ldr r1, [r4, #52] ; 0x34 800a36e: b141 cbz r1, 800a382 <__swsetup_r+0x6a> 800a370: f104 0344 add.w r3, r4, #68 ; 0x44 800a374: 4299 cmp r1, r3 800a376: d002 beq.n 800a37e <__swsetup_r+0x66> 800a378: 4630 mov r0, r6 800a37a: f7fe ff4f bl 800921c <_free_r> 800a37e: 2300 movs r3, #0 800a380: 6363 str r3, [r4, #52] ; 0x34 800a382: 89a3 ldrh r3, [r4, #12] 800a384: f023 0324 bic.w r3, r3, #36 ; 0x24 800a388: 81a3 strh r3, [r4, #12] 800a38a: 2300 movs r3, #0 800a38c: 6063 str r3, [r4, #4] 800a38e: 6923 ldr r3, [r4, #16] 800a390: 6023 str r3, [r4, #0] 800a392: 89a3 ldrh r3, [r4, #12] 800a394: f043 0308 orr.w r3, r3, #8 800a398: 81a3 strh r3, [r4, #12] 800a39a: 6923 ldr r3, [r4, #16] 800a39c: b94b cbnz r3, 800a3b2 <__swsetup_r+0x9a> 800a39e: 89a3 ldrh r3, [r4, #12] 800a3a0: f403 7320 and.w r3, r3, #640 ; 0x280 800a3a4: f5b3 7f00 cmp.w r3, #512 ; 0x200 800a3a8: d003 beq.n 800a3b2 <__swsetup_r+0x9a> 800a3aa: 4621 mov r1, r4 800a3ac: 4630 mov r0, r6 800a3ae: f001 f8f5 bl 800b59c <__smakebuf_r> 800a3b2: 89a0 ldrh r0, [r4, #12] 800a3b4: f9b4 200c ldrsh.w r2, [r4, #12] 800a3b8: f010 0301 ands.w r3, r0, #1 800a3bc: d00a beq.n 800a3d4 <__swsetup_r+0xbc> 800a3be: 2300 movs r3, #0 800a3c0: 60a3 str r3, [r4, #8] 800a3c2: 6963 ldr r3, [r4, #20] 800a3c4: 425b negs r3, r3 800a3c6: 61a3 str r3, [r4, #24] 800a3c8: 6923 ldr r3, [r4, #16] 800a3ca: b943 cbnz r3, 800a3de <__swsetup_r+0xc6> 800a3cc: f010 0080 ands.w r0, r0, #128 ; 0x80 800a3d0: d1ba bne.n 800a348 <__swsetup_r+0x30> 800a3d2: bd70 pop {r4, r5, r6, pc} 800a3d4: 0781 lsls r1, r0, #30 800a3d6: bf58 it pl 800a3d8: 6963 ldrpl r3, [r4, #20] 800a3da: 60a3 str r3, [r4, #8] 800a3dc: e7f4 b.n 800a3c8 <__swsetup_r+0xb0> 800a3de: 2000 movs r0, #0 800a3e0: e7f7 b.n 800a3d2 <__swsetup_r+0xba> 800a3e2: bf00 nop 800a3e4: 20000014 .word 0x20000014 800a3e8: 0800d524 .word 0x0800d524 800a3ec: 0800d544 .word 0x0800d544 800a3f0: 0800d504 .word 0x0800d504 0800a3f4 <__assert_func>: 800a3f4: b51f push {r0, r1, r2, r3, r4, lr} 800a3f6: 4614 mov r4, r2 800a3f8: 461a mov r2, r3 800a3fa: 4b09 ldr r3, [pc, #36] ; (800a420 <__assert_func+0x2c>) 800a3fc: 4605 mov r5, r0 800a3fe: 681b ldr r3, [r3, #0] 800a400: 68d8 ldr r0, [r3, #12] 800a402: b14c cbz r4, 800a418 <__assert_func+0x24> 800a404: 4b07 ldr r3, [pc, #28] ; (800a424 <__assert_func+0x30>) 800a406: e9cd 3401 strd r3, r4, [sp, #4] 800a40a: 9100 str r1, [sp, #0] 800a40c: 462b mov r3, r5 800a40e: 4906 ldr r1, [pc, #24] ; (800a428 <__assert_func+0x34>) 800a410: f001 f81c bl 800b44c 800a414: f001 ff12 bl 800c23c 800a418: 4b04 ldr r3, [pc, #16] ; (800a42c <__assert_func+0x38>) 800a41a: 461c mov r4, r3 800a41c: e7f3 b.n 800a406 <__assert_func+0x12> 800a41e: bf00 nop 800a420: 20000014 .word 0x20000014 800a424: 0800d44e .word 0x0800d44e 800a428: 0800d45b .word 0x0800d45b 800a42c: 0800d489 .word 0x0800d489 0800a430 : 800a430: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 800a434: 6903 ldr r3, [r0, #16] 800a436: 690c ldr r4, [r1, #16] 800a438: 4607 mov r7, r0 800a43a: 42a3 cmp r3, r4 800a43c: f2c0 8082 blt.w 800a544 800a440: 3c01 subs r4, #1 800a442: f100 0514 add.w r5, r0, #20 800a446: f101 0814 add.w r8, r1, #20 800a44a: eb05 0384 add.w r3, r5, r4, lsl #2 800a44e: 9301 str r3, [sp, #4] 800a450: f858 3024 ldr.w r3, [r8, r4, lsl #2] 800a454: f855 2024 ldr.w r2, [r5, r4, lsl #2] 800a458: 3301 adds r3, #1 800a45a: 429a cmp r2, r3 800a45c: fbb2 f6f3 udiv r6, r2, r3 800a460: ea4f 0b84 mov.w fp, r4, lsl #2 800a464: eb08 0984 add.w r9, r8, r4, lsl #2 800a468: d331 bcc.n 800a4ce 800a46a: f04f 0e00 mov.w lr, #0 800a46e: 4640 mov r0, r8 800a470: 46ac mov ip, r5 800a472: 46f2 mov sl, lr 800a474: f850 2b04 ldr.w r2, [r0], #4 800a478: b293 uxth r3, r2 800a47a: fb06 e303 mla r3, r6, r3, lr 800a47e: 0c12 lsrs r2, r2, #16 800a480: ea4f 4e13 mov.w lr, r3, lsr #16 800a484: b29b uxth r3, r3 800a486: fb06 e202 mla r2, r6, r2, lr 800a48a: ebaa 0303 sub.w r3, sl, r3 800a48e: f8dc a000 ldr.w sl, [ip] 800a492: ea4f 4e12 mov.w lr, r2, lsr #16 800a496: fa1f fa8a uxth.w sl, sl 800a49a: 4453 add r3, sl 800a49c: f8dc a000 ldr.w sl, [ip] 800a4a0: b292 uxth r2, r2 800a4a2: ebc2 421a rsb r2, r2, sl, lsr #16 800a4a6: eb02 4223 add.w r2, r2, r3, asr #16 800a4aa: b29b uxth r3, r3 800a4ac: ea43 4302 orr.w r3, r3, r2, lsl #16 800a4b0: 4581 cmp r9, r0 800a4b2: ea4f 4a22 mov.w sl, r2, asr #16 800a4b6: f84c 3b04 str.w r3, [ip], #4 800a4ba: d2db bcs.n 800a474 800a4bc: f855 300b ldr.w r3, [r5, fp] 800a4c0: b92b cbnz r3, 800a4ce 800a4c2: 9b01 ldr r3, [sp, #4] 800a4c4: 3b04 subs r3, #4 800a4c6: 429d cmp r5, r3 800a4c8: 461a mov r2, r3 800a4ca: d32f bcc.n 800a52c 800a4cc: 613c str r4, [r7, #16] 800a4ce: 4638 mov r0, r7 800a4d0: f001 fb3c bl 800bb4c <__mcmp> 800a4d4: 2800 cmp r0, #0 800a4d6: db25 blt.n 800a524 800a4d8: 4628 mov r0, r5 800a4da: f04f 0c00 mov.w ip, #0 800a4de: 3601 adds r6, #1 800a4e0: f858 1b04 ldr.w r1, [r8], #4 800a4e4: f8d0 e000 ldr.w lr, [r0] 800a4e8: b28b uxth r3, r1 800a4ea: ebac 0303 sub.w r3, ip, r3 800a4ee: fa1f f28e uxth.w r2, lr 800a4f2: 4413 add r3, r2 800a4f4: 0c0a lsrs r2, r1, #16 800a4f6: ebc2 421e rsb r2, r2, lr, lsr #16 800a4fa: eb02 4223 add.w r2, r2, r3, asr #16 800a4fe: b29b uxth r3, r3 800a500: ea43 4302 orr.w r3, r3, r2, lsl #16 800a504: 45c1 cmp r9, r8 800a506: ea4f 4c22 mov.w ip, r2, asr #16 800a50a: f840 3b04 str.w r3, [r0], #4 800a50e: d2e7 bcs.n 800a4e0 800a510: f855 2024 ldr.w r2, [r5, r4, lsl #2] 800a514: eb05 0384 add.w r3, r5, r4, lsl #2 800a518: b922 cbnz r2, 800a524 800a51a: 3b04 subs r3, #4 800a51c: 429d cmp r5, r3 800a51e: 461a mov r2, r3 800a520: d30a bcc.n 800a538 800a522: 613c str r4, [r7, #16] 800a524: 4630 mov r0, r6 800a526: b003 add sp, #12 800a528: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800a52c: 6812 ldr r2, [r2, #0] 800a52e: 3b04 subs r3, #4 800a530: 2a00 cmp r2, #0 800a532: d1cb bne.n 800a4cc 800a534: 3c01 subs r4, #1 800a536: e7c6 b.n 800a4c6 800a538: 6812 ldr r2, [r2, #0] 800a53a: 3b04 subs r3, #4 800a53c: 2a00 cmp r2, #0 800a53e: d1f0 bne.n 800a522 800a540: 3c01 subs r4, #1 800a542: e7eb b.n 800a51c 800a544: 2000 movs r0, #0 800a546: e7ee b.n 800a526 0800a548 <_dtoa_r>: 800a548: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800a54c: 4616 mov r6, r2 800a54e: 461f mov r7, r3 800a550: 6a44 ldr r4, [r0, #36] ; 0x24 800a552: b099 sub sp, #100 ; 0x64 800a554: 4605 mov r5, r0 800a556: e9cd 6704 strd r6, r7, [sp, #16] 800a55a: f8dd 8094 ldr.w r8, [sp, #148] ; 0x94 800a55e: b974 cbnz r4, 800a57e <_dtoa_r+0x36> 800a560: 2010 movs r0, #16 800a562: f7fe fe35 bl 80091d0 800a566: 4602 mov r2, r0 800a568: 6268 str r0, [r5, #36] ; 0x24 800a56a: b920 cbnz r0, 800a576 <_dtoa_r+0x2e> 800a56c: 21ea movs r1, #234 ; 0xea 800a56e: 4ba8 ldr r3, [pc, #672] ; (800a810 <_dtoa_r+0x2c8>) 800a570: 48a8 ldr r0, [pc, #672] ; (800a814 <_dtoa_r+0x2cc>) 800a572: f7ff ff3f bl 800a3f4 <__assert_func> 800a576: e9c0 4401 strd r4, r4, [r0, #4] 800a57a: 6004 str r4, [r0, #0] 800a57c: 60c4 str r4, [r0, #12] 800a57e: 6a6b ldr r3, [r5, #36] ; 0x24 800a580: 6819 ldr r1, [r3, #0] 800a582: b151 cbz r1, 800a59a <_dtoa_r+0x52> 800a584: 685a ldr r2, [r3, #4] 800a586: 2301 movs r3, #1 800a588: 4093 lsls r3, r2 800a58a: 604a str r2, [r1, #4] 800a58c: 608b str r3, [r1, #8] 800a58e: 4628 mov r0, r5 800a590: f001 f89e bl 800b6d0 <_Bfree> 800a594: 2200 movs r2, #0 800a596: 6a6b ldr r3, [r5, #36] ; 0x24 800a598: 601a str r2, [r3, #0] 800a59a: 1e3b subs r3, r7, #0 800a59c: bfaf iteee ge 800a59e: 2300 movge r3, #0 800a5a0: 2201 movlt r2, #1 800a5a2: f023 4300 biclt.w r3, r3, #2147483648 ; 0x80000000 800a5a6: 9305 strlt r3, [sp, #20] 800a5a8: bfa8 it ge 800a5aa: f8c8 3000 strge.w r3, [r8] 800a5ae: f8dd 9014 ldr.w r9, [sp, #20] 800a5b2: 4b99 ldr r3, [pc, #612] ; (800a818 <_dtoa_r+0x2d0>) 800a5b4: bfb8 it lt 800a5b6: f8c8 2000 strlt.w r2, [r8] 800a5ba: ea33 0309 bics.w r3, r3, r9 800a5be: d119 bne.n 800a5f4 <_dtoa_r+0xac> 800a5c0: f242 730f movw r3, #9999 ; 0x270f 800a5c4: 9a24 ldr r2, [sp, #144] ; 0x90 800a5c6: 6013 str r3, [r2, #0] 800a5c8: f3c9 0313 ubfx r3, r9, #0, #20 800a5cc: 4333 orrs r3, r6 800a5ce: f000 857f beq.w 800b0d0 <_dtoa_r+0xb88> 800a5d2: 9b26 ldr r3, [sp, #152] ; 0x98 800a5d4: b953 cbnz r3, 800a5ec <_dtoa_r+0xa4> 800a5d6: 4b91 ldr r3, [pc, #580] ; (800a81c <_dtoa_r+0x2d4>) 800a5d8: e022 b.n 800a620 <_dtoa_r+0xd8> 800a5da: 4b91 ldr r3, [pc, #580] ; (800a820 <_dtoa_r+0x2d8>) 800a5dc: 9303 str r3, [sp, #12] 800a5de: 3308 adds r3, #8 800a5e0: 9a26 ldr r2, [sp, #152] ; 0x98 800a5e2: 6013 str r3, [r2, #0] 800a5e4: 9803 ldr r0, [sp, #12] 800a5e6: b019 add sp, #100 ; 0x64 800a5e8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800a5ec: 4b8b ldr r3, [pc, #556] ; (800a81c <_dtoa_r+0x2d4>) 800a5ee: 9303 str r3, [sp, #12] 800a5f0: 3303 adds r3, #3 800a5f2: e7f5 b.n 800a5e0 <_dtoa_r+0x98> 800a5f4: e9dd 3404 ldrd r3, r4, [sp, #16] 800a5f8: e9cd 340c strd r3, r4, [sp, #48] ; 0x30 800a5fc: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 800a600: 2200 movs r2, #0 800a602: 2300 movs r3, #0 800a604: f7f6 fa46 bl 8000a94 <__aeabi_dcmpeq> 800a608: 4680 mov r8, r0 800a60a: b158 cbz r0, 800a624 <_dtoa_r+0xdc> 800a60c: 2301 movs r3, #1 800a60e: 9a24 ldr r2, [sp, #144] ; 0x90 800a610: 6013 str r3, [r2, #0] 800a612: 9b26 ldr r3, [sp, #152] ; 0x98 800a614: 2b00 cmp r3, #0 800a616: f000 8558 beq.w 800b0ca <_dtoa_r+0xb82> 800a61a: 4882 ldr r0, [pc, #520] ; (800a824 <_dtoa_r+0x2dc>) 800a61c: 6018 str r0, [r3, #0] 800a61e: 1e43 subs r3, r0, #1 800a620: 9303 str r3, [sp, #12] 800a622: e7df b.n 800a5e4 <_dtoa_r+0x9c> 800a624: ab16 add r3, sp, #88 ; 0x58 800a626: 9301 str r3, [sp, #4] 800a628: ab17 add r3, sp, #92 ; 0x5c 800a62a: 9300 str r3, [sp, #0] 800a62c: 4628 mov r0, r5 800a62e: e9dd 230c ldrd r2, r3, [sp, #48] ; 0x30 800a632: f001 fb33 bl 800bc9c <__d2b> 800a636: f3c9 540a ubfx r4, r9, #20, #11 800a63a: 4683 mov fp, r0 800a63c: 2c00 cmp r4, #0 800a63e: d07f beq.n 800a740 <_dtoa_r+0x1f8> 800a640: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 800a644: 9b0d ldr r3, [sp, #52] ; 0x34 800a646: f2a4 34ff subw r4, r4, #1023 ; 0x3ff 800a64a: f3c3 0313 ubfx r3, r3, #0, #20 800a64e: f043 517f orr.w r1, r3, #1069547520 ; 0x3fc00000 800a652: f441 1140 orr.w r1, r1, #3145728 ; 0x300000 800a656: f8cd 804c str.w r8, [sp, #76] ; 0x4c 800a65a: 2200 movs r2, #0 800a65c: 4b72 ldr r3, [pc, #456] ; (800a828 <_dtoa_r+0x2e0>) 800a65e: f7f5 fdf9 bl 8000254 <__aeabi_dsub> 800a662: a365 add r3, pc, #404 ; (adr r3, 800a7f8 <_dtoa_r+0x2b0>) 800a664: e9d3 2300 ldrd r2, r3, [r3] 800a668: f7f5 ffac bl 80005c4 <__aeabi_dmul> 800a66c: a364 add r3, pc, #400 ; (adr r3, 800a800 <_dtoa_r+0x2b8>) 800a66e: e9d3 2300 ldrd r2, r3, [r3] 800a672: f7f5 fdf1 bl 8000258 <__adddf3> 800a676: 4606 mov r6, r0 800a678: 4620 mov r0, r4 800a67a: 460f mov r7, r1 800a67c: f7f5 ff38 bl 80004f0 <__aeabi_i2d> 800a680: a361 add r3, pc, #388 ; (adr r3, 800a808 <_dtoa_r+0x2c0>) 800a682: e9d3 2300 ldrd r2, r3, [r3] 800a686: f7f5 ff9d bl 80005c4 <__aeabi_dmul> 800a68a: 4602 mov r2, r0 800a68c: 460b mov r3, r1 800a68e: 4630 mov r0, r6 800a690: 4639 mov r1, r7 800a692: f7f5 fde1 bl 8000258 <__adddf3> 800a696: 4606 mov r6, r0 800a698: 460f mov r7, r1 800a69a: f7f6 fa43 bl 8000b24 <__aeabi_d2iz> 800a69e: 2200 movs r2, #0 800a6a0: 4682 mov sl, r0 800a6a2: 2300 movs r3, #0 800a6a4: 4630 mov r0, r6 800a6a6: 4639 mov r1, r7 800a6a8: f7f6 f9fe bl 8000aa8 <__aeabi_dcmplt> 800a6ac: b148 cbz r0, 800a6c2 <_dtoa_r+0x17a> 800a6ae: 4650 mov r0, sl 800a6b0: f7f5 ff1e bl 80004f0 <__aeabi_i2d> 800a6b4: 4632 mov r2, r6 800a6b6: 463b mov r3, r7 800a6b8: f7f6 f9ec bl 8000a94 <__aeabi_dcmpeq> 800a6bc: b908 cbnz r0, 800a6c2 <_dtoa_r+0x17a> 800a6be: f10a 3aff add.w sl, sl, #4294967295 ; 0xffffffff 800a6c2: f1ba 0f16 cmp.w sl, #22 800a6c6: d858 bhi.n 800a77a <_dtoa_r+0x232> 800a6c8: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 800a6cc: 4b57 ldr r3, [pc, #348] ; (800a82c <_dtoa_r+0x2e4>) 800a6ce: eb03 03ca add.w r3, r3, sl, lsl #3 800a6d2: e9d3 2300 ldrd r2, r3, [r3] 800a6d6: f7f6 f9e7 bl 8000aa8 <__aeabi_dcmplt> 800a6da: 2800 cmp r0, #0 800a6dc: d04f beq.n 800a77e <_dtoa_r+0x236> 800a6de: 2300 movs r3, #0 800a6e0: f10a 3aff add.w sl, sl, #4294967295 ; 0xffffffff 800a6e4: 930f str r3, [sp, #60] ; 0x3c 800a6e6: 9b16 ldr r3, [sp, #88] ; 0x58 800a6e8: 1b1c subs r4, r3, r4 800a6ea: 1e63 subs r3, r4, #1 800a6ec: 9309 str r3, [sp, #36] ; 0x24 800a6ee: bf49 itett mi 800a6f0: f1c4 0301 rsbmi r3, r4, #1 800a6f4: 2300 movpl r3, #0 800a6f6: 9306 strmi r3, [sp, #24] 800a6f8: 2300 movmi r3, #0 800a6fa: bf54 ite pl 800a6fc: 9306 strpl r3, [sp, #24] 800a6fe: 9309 strmi r3, [sp, #36] ; 0x24 800a700: f1ba 0f00 cmp.w sl, #0 800a704: db3d blt.n 800a782 <_dtoa_r+0x23a> 800a706: 9b09 ldr r3, [sp, #36] ; 0x24 800a708: f8cd a038 str.w sl, [sp, #56] ; 0x38 800a70c: 4453 add r3, sl 800a70e: 9309 str r3, [sp, #36] ; 0x24 800a710: 2300 movs r3, #0 800a712: 930a str r3, [sp, #40] ; 0x28 800a714: 9b22 ldr r3, [sp, #136] ; 0x88 800a716: 2b09 cmp r3, #9 800a718: f200 808c bhi.w 800a834 <_dtoa_r+0x2ec> 800a71c: 2b05 cmp r3, #5 800a71e: bfc4 itt gt 800a720: 3b04 subgt r3, #4 800a722: 9322 strgt r3, [sp, #136] ; 0x88 800a724: 9b22 ldr r3, [sp, #136] ; 0x88 800a726: bfc8 it gt 800a728: 2400 movgt r4, #0 800a72a: f1a3 0302 sub.w r3, r3, #2 800a72e: bfd8 it le 800a730: 2401 movle r4, #1 800a732: 2b03 cmp r3, #3 800a734: f200 808a bhi.w 800a84c <_dtoa_r+0x304> 800a738: e8df f003 tbb [pc, r3] 800a73c: 5b4d4f2d .word 0x5b4d4f2d 800a740: e9dd 4316 ldrd r4, r3, [sp, #88] ; 0x58 800a744: 441c add r4, r3 800a746: f204 4332 addw r3, r4, #1074 ; 0x432 800a74a: 2b20 cmp r3, #32 800a74c: bfc3 ittte gt 800a74e: f1c3 0340 rsbgt r3, r3, #64 ; 0x40 800a752: f204 4012 addwgt r0, r4, #1042 ; 0x412 800a756: fa09 f303 lslgt.w r3, r9, r3 800a75a: f1c3 0320 rsble r3, r3, #32 800a75e: bfc6 itte gt 800a760: fa26 f000 lsrgt.w r0, r6, r0 800a764: 4318 orrgt r0, r3 800a766: fa06 f003 lslle.w r0, r6, r3 800a76a: f7f5 feb1 bl 80004d0 <__aeabi_ui2d> 800a76e: 2301 movs r3, #1 800a770: f1a1 71f8 sub.w r1, r1, #32505856 ; 0x1f00000 800a774: 3c01 subs r4, #1 800a776: 9313 str r3, [sp, #76] ; 0x4c 800a778: e76f b.n 800a65a <_dtoa_r+0x112> 800a77a: 2301 movs r3, #1 800a77c: e7b2 b.n 800a6e4 <_dtoa_r+0x19c> 800a77e: 900f str r0, [sp, #60] ; 0x3c 800a780: e7b1 b.n 800a6e6 <_dtoa_r+0x19e> 800a782: 9b06 ldr r3, [sp, #24] 800a784: eba3 030a sub.w r3, r3, sl 800a788: 9306 str r3, [sp, #24] 800a78a: f1ca 0300 rsb r3, sl, #0 800a78e: 930a str r3, [sp, #40] ; 0x28 800a790: 2300 movs r3, #0 800a792: 930e str r3, [sp, #56] ; 0x38 800a794: e7be b.n 800a714 <_dtoa_r+0x1cc> 800a796: 2300 movs r3, #0 800a798: 930b str r3, [sp, #44] ; 0x2c 800a79a: 9b23 ldr r3, [sp, #140] ; 0x8c 800a79c: 2b00 cmp r3, #0 800a79e: dc58 bgt.n 800a852 <_dtoa_r+0x30a> 800a7a0: f04f 0901 mov.w r9, #1 800a7a4: 464b mov r3, r9 800a7a6: f8cd 9020 str.w r9, [sp, #32] 800a7aa: f8cd 908c str.w r9, [sp, #140] ; 0x8c 800a7ae: 2200 movs r2, #0 800a7b0: 6a68 ldr r0, [r5, #36] ; 0x24 800a7b2: 6042 str r2, [r0, #4] 800a7b4: 2204 movs r2, #4 800a7b6: f102 0614 add.w r6, r2, #20 800a7ba: 429e cmp r6, r3 800a7bc: 6841 ldr r1, [r0, #4] 800a7be: d94e bls.n 800a85e <_dtoa_r+0x316> 800a7c0: 4628 mov r0, r5 800a7c2: f000 ff45 bl 800b650 <_Balloc> 800a7c6: 9003 str r0, [sp, #12] 800a7c8: 2800 cmp r0, #0 800a7ca: d14c bne.n 800a866 <_dtoa_r+0x31e> 800a7cc: 4602 mov r2, r0 800a7ce: f44f 71d5 mov.w r1, #426 ; 0x1aa 800a7d2: 4b17 ldr r3, [pc, #92] ; (800a830 <_dtoa_r+0x2e8>) 800a7d4: e6cc b.n 800a570 <_dtoa_r+0x28> 800a7d6: 2301 movs r3, #1 800a7d8: e7de b.n 800a798 <_dtoa_r+0x250> 800a7da: 2300 movs r3, #0 800a7dc: 930b str r3, [sp, #44] ; 0x2c 800a7de: 9b23 ldr r3, [sp, #140] ; 0x8c 800a7e0: eb0a 0903 add.w r9, sl, r3 800a7e4: f109 0301 add.w r3, r9, #1 800a7e8: 2b01 cmp r3, #1 800a7ea: 9308 str r3, [sp, #32] 800a7ec: bfb8 it lt 800a7ee: 2301 movlt r3, #1 800a7f0: e7dd b.n 800a7ae <_dtoa_r+0x266> 800a7f2: 2301 movs r3, #1 800a7f4: e7f2 b.n 800a7dc <_dtoa_r+0x294> 800a7f6: bf00 nop 800a7f8: 636f4361 .word 0x636f4361 800a7fc: 3fd287a7 .word 0x3fd287a7 800a800: 8b60c8b3 .word 0x8b60c8b3 800a804: 3fc68a28 .word 0x3fc68a28 800a808: 509f79fb .word 0x509f79fb 800a80c: 3fd34413 .word 0x3fd34413 800a810: 0800d2ac .word 0x0800d2ac 800a814: 0800d497 .word 0x0800d497 800a818: 7ff00000 .word 0x7ff00000 800a81c: 0800d493 .word 0x0800d493 800a820: 0800d48a .word 0x0800d48a 800a824: 0800d7dd .word 0x0800d7dd 800a828: 3ff80000 .word 0x3ff80000 800a82c: 0800d5e8 .word 0x0800d5e8 800a830: 0800d4f2 .word 0x0800d4f2 800a834: 2401 movs r4, #1 800a836: 2300 movs r3, #0 800a838: 940b str r4, [sp, #44] ; 0x2c 800a83a: 9322 str r3, [sp, #136] ; 0x88 800a83c: f04f 39ff mov.w r9, #4294967295 ; 0xffffffff 800a840: 2200 movs r2, #0 800a842: 2312 movs r3, #18 800a844: f8cd 9020 str.w r9, [sp, #32] 800a848: 9223 str r2, [sp, #140] ; 0x8c 800a84a: e7b0 b.n 800a7ae <_dtoa_r+0x266> 800a84c: 2301 movs r3, #1 800a84e: 930b str r3, [sp, #44] ; 0x2c 800a850: e7f4 b.n 800a83c <_dtoa_r+0x2f4> 800a852: f8dd 908c ldr.w r9, [sp, #140] ; 0x8c 800a856: 464b mov r3, r9 800a858: f8cd 9020 str.w r9, [sp, #32] 800a85c: e7a7 b.n 800a7ae <_dtoa_r+0x266> 800a85e: 3101 adds r1, #1 800a860: 6041 str r1, [r0, #4] 800a862: 0052 lsls r2, r2, #1 800a864: e7a7 b.n 800a7b6 <_dtoa_r+0x26e> 800a866: 6a6b ldr r3, [r5, #36] ; 0x24 800a868: 9a03 ldr r2, [sp, #12] 800a86a: 601a str r2, [r3, #0] 800a86c: 9b08 ldr r3, [sp, #32] 800a86e: 2b0e cmp r3, #14 800a870: f200 80a8 bhi.w 800a9c4 <_dtoa_r+0x47c> 800a874: 2c00 cmp r4, #0 800a876: f000 80a5 beq.w 800a9c4 <_dtoa_r+0x47c> 800a87a: f1ba 0f00 cmp.w sl, #0 800a87e: dd34 ble.n 800a8ea <_dtoa_r+0x3a2> 800a880: 4a9a ldr r2, [pc, #616] ; (800aaec <_dtoa_r+0x5a4>) 800a882: f00a 030f and.w r3, sl, #15 800a886: eb02 03c3 add.w r3, r2, r3, lsl #3 800a88a: f41a 7f80 tst.w sl, #256 ; 0x100 800a88e: e9d3 3400 ldrd r3, r4, [r3] 800a892: e9cd 3410 strd r3, r4, [sp, #64] ; 0x40 800a896: ea4f 142a mov.w r4, sl, asr #4 800a89a: d016 beq.n 800a8ca <_dtoa_r+0x382> 800a89c: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 800a8a0: 4b93 ldr r3, [pc, #588] ; (800aaf0 <_dtoa_r+0x5a8>) 800a8a2: 2703 movs r7, #3 800a8a4: e9d3 2308 ldrd r2, r3, [r3, #32] 800a8a8: f7f5 ffb6 bl 8000818 <__aeabi_ddiv> 800a8ac: e9cd 0104 strd r0, r1, [sp, #16] 800a8b0: f004 040f and.w r4, r4, #15 800a8b4: 4e8e ldr r6, [pc, #568] ; (800aaf0 <_dtoa_r+0x5a8>) 800a8b6: b954 cbnz r4, 800a8ce <_dtoa_r+0x386> 800a8b8: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 800a8bc: e9dd 0104 ldrd r0, r1, [sp, #16] 800a8c0: f7f5 ffaa bl 8000818 <__aeabi_ddiv> 800a8c4: e9cd 0104 strd r0, r1, [sp, #16] 800a8c8: e029 b.n 800a91e <_dtoa_r+0x3d6> 800a8ca: 2702 movs r7, #2 800a8cc: e7f2 b.n 800a8b4 <_dtoa_r+0x36c> 800a8ce: 07e1 lsls r1, r4, #31 800a8d0: d508 bpl.n 800a8e4 <_dtoa_r+0x39c> 800a8d2: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 800a8d6: e9d6 2300 ldrd r2, r3, [r6] 800a8da: f7f5 fe73 bl 80005c4 <__aeabi_dmul> 800a8de: e9cd 0110 strd r0, r1, [sp, #64] ; 0x40 800a8e2: 3701 adds r7, #1 800a8e4: 1064 asrs r4, r4, #1 800a8e6: 3608 adds r6, #8 800a8e8: e7e5 b.n 800a8b6 <_dtoa_r+0x36e> 800a8ea: f000 80a5 beq.w 800aa38 <_dtoa_r+0x4f0> 800a8ee: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 800a8f2: f1ca 0400 rsb r4, sl, #0 800a8f6: 4b7d ldr r3, [pc, #500] ; (800aaec <_dtoa_r+0x5a4>) 800a8f8: f004 020f and.w r2, r4, #15 800a8fc: eb03 03c2 add.w r3, r3, r2, lsl #3 800a900: e9d3 2300 ldrd r2, r3, [r3] 800a904: f7f5 fe5e bl 80005c4 <__aeabi_dmul> 800a908: 2702 movs r7, #2 800a90a: 2300 movs r3, #0 800a90c: e9cd 0104 strd r0, r1, [sp, #16] 800a910: 4e77 ldr r6, [pc, #476] ; (800aaf0 <_dtoa_r+0x5a8>) 800a912: 1124 asrs r4, r4, #4 800a914: 2c00 cmp r4, #0 800a916: f040 8084 bne.w 800aa22 <_dtoa_r+0x4da> 800a91a: 2b00 cmp r3, #0 800a91c: d1d2 bne.n 800a8c4 <_dtoa_r+0x37c> 800a91e: 9b0f ldr r3, [sp, #60] ; 0x3c 800a920: 2b00 cmp r3, #0 800a922: f000 808b beq.w 800aa3c <_dtoa_r+0x4f4> 800a926: e9dd 3404 ldrd r3, r4, [sp, #16] 800a92a: e9cd 3410 strd r3, r4, [sp, #64] ; 0x40 800a92e: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 800a932: 2200 movs r2, #0 800a934: 4b6f ldr r3, [pc, #444] ; (800aaf4 <_dtoa_r+0x5ac>) 800a936: f7f6 f8b7 bl 8000aa8 <__aeabi_dcmplt> 800a93a: 2800 cmp r0, #0 800a93c: d07e beq.n 800aa3c <_dtoa_r+0x4f4> 800a93e: 9b08 ldr r3, [sp, #32] 800a940: 2b00 cmp r3, #0 800a942: d07b beq.n 800aa3c <_dtoa_r+0x4f4> 800a944: f1b9 0f00 cmp.w r9, #0 800a948: dd38 ble.n 800a9bc <_dtoa_r+0x474> 800a94a: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 800a94e: 2200 movs r2, #0 800a950: 4b69 ldr r3, [pc, #420] ; (800aaf8 <_dtoa_r+0x5b0>) 800a952: f7f5 fe37 bl 80005c4 <__aeabi_dmul> 800a956: 464c mov r4, r9 800a958: e9cd 0104 strd r0, r1, [sp, #16] 800a95c: f10a 38ff add.w r8, sl, #4294967295 ; 0xffffffff 800a960: 3701 adds r7, #1 800a962: 4638 mov r0, r7 800a964: f7f5 fdc4 bl 80004f0 <__aeabi_i2d> 800a968: e9dd 2304 ldrd r2, r3, [sp, #16] 800a96c: f7f5 fe2a bl 80005c4 <__aeabi_dmul> 800a970: 2200 movs r2, #0 800a972: 4b62 ldr r3, [pc, #392] ; (800aafc <_dtoa_r+0x5b4>) 800a974: f7f5 fc70 bl 8000258 <__adddf3> 800a978: f1a1 7650 sub.w r6, r1, #54525952 ; 0x3400000 800a97c: e9cd 0110 strd r0, r1, [sp, #64] ; 0x40 800a980: 9611 str r6, [sp, #68] ; 0x44 800a982: 2c00 cmp r4, #0 800a984: d15d bne.n 800aa42 <_dtoa_r+0x4fa> 800a986: e9dd 0104 ldrd r0, r1, [sp, #16] 800a98a: 2200 movs r2, #0 800a98c: 4b5c ldr r3, [pc, #368] ; (800ab00 <_dtoa_r+0x5b8>) 800a98e: f7f5 fc61 bl 8000254 <__aeabi_dsub> 800a992: 4602 mov r2, r0 800a994: 460b mov r3, r1 800a996: e9cd 2304 strd r2, r3, [sp, #16] 800a99a: 4633 mov r3, r6 800a99c: 9a10 ldr r2, [sp, #64] ; 0x40 800a99e: f7f6 f8a1 bl 8000ae4 <__aeabi_dcmpgt> 800a9a2: 2800 cmp r0, #0 800a9a4: f040 829c bne.w 800aee0 <_dtoa_r+0x998> 800a9a8: e9dd 0104 ldrd r0, r1, [sp, #16] 800a9ac: 9a10 ldr r2, [sp, #64] ; 0x40 800a9ae: f106 4300 add.w r3, r6, #2147483648 ; 0x80000000 800a9b2: f7f6 f879 bl 8000aa8 <__aeabi_dcmplt> 800a9b6: 2800 cmp r0, #0 800a9b8: f040 8290 bne.w 800aedc <_dtoa_r+0x994> 800a9bc: e9dd 340c ldrd r3, r4, [sp, #48] ; 0x30 800a9c0: e9cd 3404 strd r3, r4, [sp, #16] 800a9c4: 9b17 ldr r3, [sp, #92] ; 0x5c 800a9c6: 2b00 cmp r3, #0 800a9c8: f2c0 8152 blt.w 800ac70 <_dtoa_r+0x728> 800a9cc: f1ba 0f0e cmp.w sl, #14 800a9d0: f300 814e bgt.w 800ac70 <_dtoa_r+0x728> 800a9d4: 4b45 ldr r3, [pc, #276] ; (800aaec <_dtoa_r+0x5a4>) 800a9d6: eb03 03ca add.w r3, r3, sl, lsl #3 800a9da: e9d3 3400 ldrd r3, r4, [r3] 800a9de: e9cd 3406 strd r3, r4, [sp, #24] 800a9e2: 9b23 ldr r3, [sp, #140] ; 0x8c 800a9e4: 2b00 cmp r3, #0 800a9e6: f280 80db bge.w 800aba0 <_dtoa_r+0x658> 800a9ea: 9b08 ldr r3, [sp, #32] 800a9ec: 2b00 cmp r3, #0 800a9ee: f300 80d7 bgt.w 800aba0 <_dtoa_r+0x658> 800a9f2: f040 8272 bne.w 800aeda <_dtoa_r+0x992> 800a9f6: e9dd 0106 ldrd r0, r1, [sp, #24] 800a9fa: 2200 movs r2, #0 800a9fc: 4b40 ldr r3, [pc, #256] ; (800ab00 <_dtoa_r+0x5b8>) 800a9fe: f7f5 fde1 bl 80005c4 <__aeabi_dmul> 800aa02: e9dd 2304 ldrd r2, r3, [sp, #16] 800aa06: f7f6 f863 bl 8000ad0 <__aeabi_dcmpge> 800aa0a: 9c08 ldr r4, [sp, #32] 800aa0c: 4626 mov r6, r4 800aa0e: 2800 cmp r0, #0 800aa10: f040 8248 bne.w 800aea4 <_dtoa_r+0x95c> 800aa14: 2331 movs r3, #49 ; 0x31 800aa16: 9f03 ldr r7, [sp, #12] 800aa18: f10a 0a01 add.w sl, sl, #1 800aa1c: f807 3b01 strb.w r3, [r7], #1 800aa20: e244 b.n 800aeac <_dtoa_r+0x964> 800aa22: 07e2 lsls r2, r4, #31 800aa24: d505 bpl.n 800aa32 <_dtoa_r+0x4ea> 800aa26: e9d6 2300 ldrd r2, r3, [r6] 800aa2a: f7f5 fdcb bl 80005c4 <__aeabi_dmul> 800aa2e: 2301 movs r3, #1 800aa30: 3701 adds r7, #1 800aa32: 1064 asrs r4, r4, #1 800aa34: 3608 adds r6, #8 800aa36: e76d b.n 800a914 <_dtoa_r+0x3cc> 800aa38: 2702 movs r7, #2 800aa3a: e770 b.n 800a91e <_dtoa_r+0x3d6> 800aa3c: 46d0 mov r8, sl 800aa3e: 9c08 ldr r4, [sp, #32] 800aa40: e78f b.n 800a962 <_dtoa_r+0x41a> 800aa42: 9903 ldr r1, [sp, #12] 800aa44: 4b29 ldr r3, [pc, #164] ; (800aaec <_dtoa_r+0x5a4>) 800aa46: 4421 add r1, r4 800aa48: 9112 str r1, [sp, #72] ; 0x48 800aa4a: 990b ldr r1, [sp, #44] ; 0x2c 800aa4c: eb03 03c4 add.w r3, r3, r4, lsl #3 800aa50: e9dd 6710 ldrd r6, r7, [sp, #64] ; 0x40 800aa54: e953 2302 ldrd r2, r3, [r3, #-8] 800aa58: 2900 cmp r1, #0 800aa5a: d055 beq.n 800ab08 <_dtoa_r+0x5c0> 800aa5c: 2000 movs r0, #0 800aa5e: 4929 ldr r1, [pc, #164] ; (800ab04 <_dtoa_r+0x5bc>) 800aa60: f7f5 feda bl 8000818 <__aeabi_ddiv> 800aa64: 463b mov r3, r7 800aa66: 4632 mov r2, r6 800aa68: f7f5 fbf4 bl 8000254 <__aeabi_dsub> 800aa6c: e9cd 0110 strd r0, r1, [sp, #64] ; 0x40 800aa70: 9f03 ldr r7, [sp, #12] 800aa72: e9dd 0104 ldrd r0, r1, [sp, #16] 800aa76: f7f6 f855 bl 8000b24 <__aeabi_d2iz> 800aa7a: 4604 mov r4, r0 800aa7c: f7f5 fd38 bl 80004f0 <__aeabi_i2d> 800aa80: 4602 mov r2, r0 800aa82: 460b mov r3, r1 800aa84: e9dd 0104 ldrd r0, r1, [sp, #16] 800aa88: f7f5 fbe4 bl 8000254 <__aeabi_dsub> 800aa8c: 4602 mov r2, r0 800aa8e: 460b mov r3, r1 800aa90: 3430 adds r4, #48 ; 0x30 800aa92: e9cd 2304 strd r2, r3, [sp, #16] 800aa96: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 800aa9a: f807 4b01 strb.w r4, [r7], #1 800aa9e: f7f6 f803 bl 8000aa8 <__aeabi_dcmplt> 800aaa2: 2800 cmp r0, #0 800aaa4: d174 bne.n 800ab90 <_dtoa_r+0x648> 800aaa6: e9dd 2304 ldrd r2, r3, [sp, #16] 800aaaa: 2000 movs r0, #0 800aaac: 4911 ldr r1, [pc, #68] ; (800aaf4 <_dtoa_r+0x5ac>) 800aaae: f7f5 fbd1 bl 8000254 <__aeabi_dsub> 800aab2: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 800aab6: f7f5 fff7 bl 8000aa8 <__aeabi_dcmplt> 800aaba: 2800 cmp r0, #0 800aabc: f040 80b7 bne.w 800ac2e <_dtoa_r+0x6e6> 800aac0: 9b12 ldr r3, [sp, #72] ; 0x48 800aac2: 429f cmp r7, r3 800aac4: f43f af7a beq.w 800a9bc <_dtoa_r+0x474> 800aac8: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 800aacc: 2200 movs r2, #0 800aace: 4b0a ldr r3, [pc, #40] ; (800aaf8 <_dtoa_r+0x5b0>) 800aad0: f7f5 fd78 bl 80005c4 <__aeabi_dmul> 800aad4: 2200 movs r2, #0 800aad6: e9cd 0110 strd r0, r1, [sp, #64] ; 0x40 800aada: e9dd 0104 ldrd r0, r1, [sp, #16] 800aade: 4b06 ldr r3, [pc, #24] ; (800aaf8 <_dtoa_r+0x5b0>) 800aae0: f7f5 fd70 bl 80005c4 <__aeabi_dmul> 800aae4: e9cd 0104 strd r0, r1, [sp, #16] 800aae8: e7c3 b.n 800aa72 <_dtoa_r+0x52a> 800aaea: bf00 nop 800aaec: 0800d5e8 .word 0x0800d5e8 800aaf0: 0800d5c0 .word 0x0800d5c0 800aaf4: 3ff00000 .word 0x3ff00000 800aaf8: 40240000 .word 0x40240000 800aafc: 401c0000 .word 0x401c0000 800ab00: 40140000 .word 0x40140000 800ab04: 3fe00000 .word 0x3fe00000 800ab08: 4630 mov r0, r6 800ab0a: 4639 mov r1, r7 800ab0c: f7f5 fd5a bl 80005c4 <__aeabi_dmul> 800ab10: 9b12 ldr r3, [sp, #72] ; 0x48 800ab12: e9cd 0110 strd r0, r1, [sp, #64] ; 0x40 800ab16: 9c03 ldr r4, [sp, #12] 800ab18: 9314 str r3, [sp, #80] ; 0x50 800ab1a: e9dd 0104 ldrd r0, r1, [sp, #16] 800ab1e: f7f6 f801 bl 8000b24 <__aeabi_d2iz> 800ab22: 9015 str r0, [sp, #84] ; 0x54 800ab24: f7f5 fce4 bl 80004f0 <__aeabi_i2d> 800ab28: 4602 mov r2, r0 800ab2a: 460b mov r3, r1 800ab2c: e9dd 0104 ldrd r0, r1, [sp, #16] 800ab30: f7f5 fb90 bl 8000254 <__aeabi_dsub> 800ab34: 9b15 ldr r3, [sp, #84] ; 0x54 800ab36: 4606 mov r6, r0 800ab38: 3330 adds r3, #48 ; 0x30 800ab3a: f804 3b01 strb.w r3, [r4], #1 800ab3e: 9b12 ldr r3, [sp, #72] ; 0x48 800ab40: 460f mov r7, r1 800ab42: 429c cmp r4, r3 800ab44: f04f 0200 mov.w r2, #0 800ab48: d124 bne.n 800ab94 <_dtoa_r+0x64c> 800ab4a: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 800ab4e: 4bb0 ldr r3, [pc, #704] ; (800ae10 <_dtoa_r+0x8c8>) 800ab50: f7f5 fb82 bl 8000258 <__adddf3> 800ab54: 4602 mov r2, r0 800ab56: 460b mov r3, r1 800ab58: 4630 mov r0, r6 800ab5a: 4639 mov r1, r7 800ab5c: f7f5 ffc2 bl 8000ae4 <__aeabi_dcmpgt> 800ab60: 2800 cmp r0, #0 800ab62: d163 bne.n 800ac2c <_dtoa_r+0x6e4> 800ab64: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 800ab68: 2000 movs r0, #0 800ab6a: 49a9 ldr r1, [pc, #676] ; (800ae10 <_dtoa_r+0x8c8>) 800ab6c: f7f5 fb72 bl 8000254 <__aeabi_dsub> 800ab70: 4602 mov r2, r0 800ab72: 460b mov r3, r1 800ab74: 4630 mov r0, r6 800ab76: 4639 mov r1, r7 800ab78: f7f5 ff96 bl 8000aa8 <__aeabi_dcmplt> 800ab7c: 2800 cmp r0, #0 800ab7e: f43f af1d beq.w 800a9bc <_dtoa_r+0x474> 800ab82: 9f14 ldr r7, [sp, #80] ; 0x50 800ab84: 1e7b subs r3, r7, #1 800ab86: 9314 str r3, [sp, #80] ; 0x50 800ab88: f817 3c01 ldrb.w r3, [r7, #-1] 800ab8c: 2b30 cmp r3, #48 ; 0x30 800ab8e: d0f8 beq.n 800ab82 <_dtoa_r+0x63a> 800ab90: 46c2 mov sl, r8 800ab92: e03b b.n 800ac0c <_dtoa_r+0x6c4> 800ab94: 4b9f ldr r3, [pc, #636] ; (800ae14 <_dtoa_r+0x8cc>) 800ab96: f7f5 fd15 bl 80005c4 <__aeabi_dmul> 800ab9a: e9cd 0104 strd r0, r1, [sp, #16] 800ab9e: e7bc b.n 800ab1a <_dtoa_r+0x5d2> 800aba0: 9f03 ldr r7, [sp, #12] 800aba2: e9dd 8904 ldrd r8, r9, [sp, #16] 800aba6: e9dd 2306 ldrd r2, r3, [sp, #24] 800abaa: 4640 mov r0, r8 800abac: 4649 mov r1, r9 800abae: f7f5 fe33 bl 8000818 <__aeabi_ddiv> 800abb2: f7f5 ffb7 bl 8000b24 <__aeabi_d2iz> 800abb6: 4604 mov r4, r0 800abb8: f7f5 fc9a bl 80004f0 <__aeabi_i2d> 800abbc: e9dd 2306 ldrd r2, r3, [sp, #24] 800abc0: f7f5 fd00 bl 80005c4 <__aeabi_dmul> 800abc4: 4602 mov r2, r0 800abc6: 460b mov r3, r1 800abc8: 4640 mov r0, r8 800abca: 4649 mov r1, r9 800abcc: f7f5 fb42 bl 8000254 <__aeabi_dsub> 800abd0: f104 0630 add.w r6, r4, #48 ; 0x30 800abd4: f807 6b01 strb.w r6, [r7], #1 800abd8: 9e03 ldr r6, [sp, #12] 800abda: f8dd c020 ldr.w ip, [sp, #32] 800abde: 1bbe subs r6, r7, r6 800abe0: 45b4 cmp ip, r6 800abe2: 4602 mov r2, r0 800abe4: 460b mov r3, r1 800abe6: d136 bne.n 800ac56 <_dtoa_r+0x70e> 800abe8: f7f5 fb36 bl 8000258 <__adddf3> 800abec: e9dd 2306 ldrd r2, r3, [sp, #24] 800abf0: 4680 mov r8, r0 800abf2: 4689 mov r9, r1 800abf4: f7f5 ff76 bl 8000ae4 <__aeabi_dcmpgt> 800abf8: bb58 cbnz r0, 800ac52 <_dtoa_r+0x70a> 800abfa: e9dd 2306 ldrd r2, r3, [sp, #24] 800abfe: 4640 mov r0, r8 800ac00: 4649 mov r1, r9 800ac02: f7f5 ff47 bl 8000a94 <__aeabi_dcmpeq> 800ac06: b108 cbz r0, 800ac0c <_dtoa_r+0x6c4> 800ac08: 07e1 lsls r1, r4, #31 800ac0a: d422 bmi.n 800ac52 <_dtoa_r+0x70a> 800ac0c: 4628 mov r0, r5 800ac0e: 4659 mov r1, fp 800ac10: f000 fd5e bl 800b6d0 <_Bfree> 800ac14: 2300 movs r3, #0 800ac16: 703b strb r3, [r7, #0] 800ac18: 9b24 ldr r3, [sp, #144] ; 0x90 800ac1a: f10a 0001 add.w r0, sl, #1 800ac1e: 6018 str r0, [r3, #0] 800ac20: 9b26 ldr r3, [sp, #152] ; 0x98 800ac22: 2b00 cmp r3, #0 800ac24: f43f acde beq.w 800a5e4 <_dtoa_r+0x9c> 800ac28: 601f str r7, [r3, #0] 800ac2a: e4db b.n 800a5e4 <_dtoa_r+0x9c> 800ac2c: 4627 mov r7, r4 800ac2e: 463b mov r3, r7 800ac30: 461f mov r7, r3 800ac32: f813 2d01 ldrb.w r2, [r3, #-1]! 800ac36: 2a39 cmp r2, #57 ; 0x39 800ac38: d107 bne.n 800ac4a <_dtoa_r+0x702> 800ac3a: 9a03 ldr r2, [sp, #12] 800ac3c: 429a cmp r2, r3 800ac3e: d1f7 bne.n 800ac30 <_dtoa_r+0x6e8> 800ac40: 2230 movs r2, #48 ; 0x30 800ac42: 9903 ldr r1, [sp, #12] 800ac44: f108 0801 add.w r8, r8, #1 800ac48: 700a strb r2, [r1, #0] 800ac4a: 781a ldrb r2, [r3, #0] 800ac4c: 3201 adds r2, #1 800ac4e: 701a strb r2, [r3, #0] 800ac50: e79e b.n 800ab90 <_dtoa_r+0x648> 800ac52: 46d0 mov r8, sl 800ac54: e7eb b.n 800ac2e <_dtoa_r+0x6e6> 800ac56: 2200 movs r2, #0 800ac58: 4b6e ldr r3, [pc, #440] ; (800ae14 <_dtoa_r+0x8cc>) 800ac5a: f7f5 fcb3 bl 80005c4 <__aeabi_dmul> 800ac5e: 2200 movs r2, #0 800ac60: 2300 movs r3, #0 800ac62: 4680 mov r8, r0 800ac64: 4689 mov r9, r1 800ac66: f7f5 ff15 bl 8000a94 <__aeabi_dcmpeq> 800ac6a: 2800 cmp r0, #0 800ac6c: d09b beq.n 800aba6 <_dtoa_r+0x65e> 800ac6e: e7cd b.n 800ac0c <_dtoa_r+0x6c4> 800ac70: 9a0b ldr r2, [sp, #44] ; 0x2c 800ac72: 2a00 cmp r2, #0 800ac74: f000 80d0 beq.w 800ae18 <_dtoa_r+0x8d0> 800ac78: 9a22 ldr r2, [sp, #136] ; 0x88 800ac7a: 2a01 cmp r2, #1 800ac7c: f300 80ae bgt.w 800addc <_dtoa_r+0x894> 800ac80: 9a13 ldr r2, [sp, #76] ; 0x4c 800ac82: 2a00 cmp r2, #0 800ac84: f000 80a6 beq.w 800add4 <_dtoa_r+0x88c> 800ac88: f203 4333 addw r3, r3, #1075 ; 0x433 800ac8c: 9c0a ldr r4, [sp, #40] ; 0x28 800ac8e: 9f06 ldr r7, [sp, #24] 800ac90: 9a06 ldr r2, [sp, #24] 800ac92: 2101 movs r1, #1 800ac94: 441a add r2, r3 800ac96: 9206 str r2, [sp, #24] 800ac98: 9a09 ldr r2, [sp, #36] ; 0x24 800ac9a: 4628 mov r0, r5 800ac9c: 441a add r2, r3 800ac9e: 9209 str r2, [sp, #36] ; 0x24 800aca0: f000 fdcc bl 800b83c <__i2b> 800aca4: 4606 mov r6, r0 800aca6: 2f00 cmp r7, #0 800aca8: dd0c ble.n 800acc4 <_dtoa_r+0x77c> 800acaa: 9b09 ldr r3, [sp, #36] ; 0x24 800acac: 2b00 cmp r3, #0 800acae: dd09 ble.n 800acc4 <_dtoa_r+0x77c> 800acb0: 42bb cmp r3, r7 800acb2: bfa8 it ge 800acb4: 463b movge r3, r7 800acb6: 9a06 ldr r2, [sp, #24] 800acb8: 1aff subs r7, r7, r3 800acba: 1ad2 subs r2, r2, r3 800acbc: 9206 str r2, [sp, #24] 800acbe: 9a09 ldr r2, [sp, #36] ; 0x24 800acc0: 1ad3 subs r3, r2, r3 800acc2: 9309 str r3, [sp, #36] ; 0x24 800acc4: 9b0a ldr r3, [sp, #40] ; 0x28 800acc6: b1f3 cbz r3, 800ad06 <_dtoa_r+0x7be> 800acc8: 9b0b ldr r3, [sp, #44] ; 0x2c 800acca: 2b00 cmp r3, #0 800accc: f000 80a8 beq.w 800ae20 <_dtoa_r+0x8d8> 800acd0: 2c00 cmp r4, #0 800acd2: dd10 ble.n 800acf6 <_dtoa_r+0x7ae> 800acd4: 4631 mov r1, r6 800acd6: 4622 mov r2, r4 800acd8: 4628 mov r0, r5 800acda: f000 fe6d bl 800b9b8 <__pow5mult> 800acde: 465a mov r2, fp 800ace0: 4601 mov r1, r0 800ace2: 4606 mov r6, r0 800ace4: 4628 mov r0, r5 800ace6: f000 fdbf bl 800b868 <__multiply> 800acea: 4680 mov r8, r0 800acec: 4659 mov r1, fp 800acee: 4628 mov r0, r5 800acf0: f000 fcee bl 800b6d0 <_Bfree> 800acf4: 46c3 mov fp, r8 800acf6: 9b0a ldr r3, [sp, #40] ; 0x28 800acf8: 1b1a subs r2, r3, r4 800acfa: d004 beq.n 800ad06 <_dtoa_r+0x7be> 800acfc: 4659 mov r1, fp 800acfe: 4628 mov r0, r5 800ad00: f000 fe5a bl 800b9b8 <__pow5mult> 800ad04: 4683 mov fp, r0 800ad06: 2101 movs r1, #1 800ad08: 4628 mov r0, r5 800ad0a: f000 fd97 bl 800b83c <__i2b> 800ad0e: 9b0e ldr r3, [sp, #56] ; 0x38 800ad10: 4604 mov r4, r0 800ad12: 2b00 cmp r3, #0 800ad14: f340 8086 ble.w 800ae24 <_dtoa_r+0x8dc> 800ad18: 461a mov r2, r3 800ad1a: 4601 mov r1, r0 800ad1c: 4628 mov r0, r5 800ad1e: f000 fe4b bl 800b9b8 <__pow5mult> 800ad22: 9b22 ldr r3, [sp, #136] ; 0x88 800ad24: 4604 mov r4, r0 800ad26: 2b01 cmp r3, #1 800ad28: dd7f ble.n 800ae2a <_dtoa_r+0x8e2> 800ad2a: f04f 0800 mov.w r8, #0 800ad2e: 6923 ldr r3, [r4, #16] 800ad30: eb04 0383 add.w r3, r4, r3, lsl #2 800ad34: 6918 ldr r0, [r3, #16] 800ad36: f000 fd33 bl 800b7a0 <__hi0bits> 800ad3a: f1c0 0020 rsb r0, r0, #32 800ad3e: 9b09 ldr r3, [sp, #36] ; 0x24 800ad40: 4418 add r0, r3 800ad42: f010 001f ands.w r0, r0, #31 800ad46: f000 8092 beq.w 800ae6e <_dtoa_r+0x926> 800ad4a: f1c0 0320 rsb r3, r0, #32 800ad4e: 2b04 cmp r3, #4 800ad50: f340 808a ble.w 800ae68 <_dtoa_r+0x920> 800ad54: f1c0 001c rsb r0, r0, #28 800ad58: 9b06 ldr r3, [sp, #24] 800ad5a: 4407 add r7, r0 800ad5c: 4403 add r3, r0 800ad5e: 9306 str r3, [sp, #24] 800ad60: 9b09 ldr r3, [sp, #36] ; 0x24 800ad62: 4403 add r3, r0 800ad64: 9309 str r3, [sp, #36] ; 0x24 800ad66: 9b06 ldr r3, [sp, #24] 800ad68: 2b00 cmp r3, #0 800ad6a: dd05 ble.n 800ad78 <_dtoa_r+0x830> 800ad6c: 4659 mov r1, fp 800ad6e: 461a mov r2, r3 800ad70: 4628 mov r0, r5 800ad72: f000 fe7b bl 800ba6c <__lshift> 800ad76: 4683 mov fp, r0 800ad78: 9b09 ldr r3, [sp, #36] ; 0x24 800ad7a: 2b00 cmp r3, #0 800ad7c: dd05 ble.n 800ad8a <_dtoa_r+0x842> 800ad7e: 4621 mov r1, r4 800ad80: 461a mov r2, r3 800ad82: 4628 mov r0, r5 800ad84: f000 fe72 bl 800ba6c <__lshift> 800ad88: 4604 mov r4, r0 800ad8a: 9b0f ldr r3, [sp, #60] ; 0x3c 800ad8c: 2b00 cmp r3, #0 800ad8e: d070 beq.n 800ae72 <_dtoa_r+0x92a> 800ad90: 4621 mov r1, r4 800ad92: 4658 mov r0, fp 800ad94: f000 feda bl 800bb4c <__mcmp> 800ad98: 2800 cmp r0, #0 800ad9a: da6a bge.n 800ae72 <_dtoa_r+0x92a> 800ad9c: 2300 movs r3, #0 800ad9e: 4659 mov r1, fp 800ada0: 220a movs r2, #10 800ada2: 4628 mov r0, r5 800ada4: f000 fcb6 bl 800b714 <__multadd> 800ada8: 9b0b ldr r3, [sp, #44] ; 0x2c 800adaa: 4683 mov fp, r0 800adac: f10a 3aff add.w sl, sl, #4294967295 ; 0xffffffff 800adb0: 2b00 cmp r3, #0 800adb2: f000 8194 beq.w 800b0de <_dtoa_r+0xb96> 800adb6: 4631 mov r1, r6 800adb8: 2300 movs r3, #0 800adba: 220a movs r2, #10 800adbc: 4628 mov r0, r5 800adbe: f000 fca9 bl 800b714 <__multadd> 800adc2: f1b9 0f00 cmp.w r9, #0 800adc6: 4606 mov r6, r0 800adc8: f300 8093 bgt.w 800aef2 <_dtoa_r+0x9aa> 800adcc: 9b22 ldr r3, [sp, #136] ; 0x88 800adce: 2b02 cmp r3, #2 800add0: dc57 bgt.n 800ae82 <_dtoa_r+0x93a> 800add2: e08e b.n 800aef2 <_dtoa_r+0x9aa> 800add4: 9b16 ldr r3, [sp, #88] ; 0x58 800add6: f1c3 0336 rsb r3, r3, #54 ; 0x36 800adda: e757 b.n 800ac8c <_dtoa_r+0x744> 800addc: 9b08 ldr r3, [sp, #32] 800adde: 1e5c subs r4, r3, #1 800ade0: 9b0a ldr r3, [sp, #40] ; 0x28 800ade2: 42a3 cmp r3, r4 800ade4: bfb7 itett lt 800ade6: 9b0a ldrlt r3, [sp, #40] ; 0x28 800ade8: 1b1c subge r4, r3, r4 800adea: 1ae2 sublt r2, r4, r3 800adec: 9b0e ldrlt r3, [sp, #56] ; 0x38 800adee: bfbe ittt lt 800adf0: 940a strlt r4, [sp, #40] ; 0x28 800adf2: 189b addlt r3, r3, r2 800adf4: 930e strlt r3, [sp, #56] ; 0x38 800adf6: 9b08 ldr r3, [sp, #32] 800adf8: bfb8 it lt 800adfa: 2400 movlt r4, #0 800adfc: 2b00 cmp r3, #0 800adfe: bfbb ittet lt 800ae00: 9b06 ldrlt r3, [sp, #24] 800ae02: 9a08 ldrlt r2, [sp, #32] 800ae04: 9f06 ldrge r7, [sp, #24] 800ae06: 1a9f sublt r7, r3, r2 800ae08: bfac ite ge 800ae0a: 9b08 ldrge r3, [sp, #32] 800ae0c: 2300 movlt r3, #0 800ae0e: e73f b.n 800ac90 <_dtoa_r+0x748> 800ae10: 3fe00000 .word 0x3fe00000 800ae14: 40240000 .word 0x40240000 800ae18: 9c0a ldr r4, [sp, #40] ; 0x28 800ae1a: 9f06 ldr r7, [sp, #24] 800ae1c: 9e0b ldr r6, [sp, #44] ; 0x2c 800ae1e: e742 b.n 800aca6 <_dtoa_r+0x75e> 800ae20: 9a0a ldr r2, [sp, #40] ; 0x28 800ae22: e76b b.n 800acfc <_dtoa_r+0x7b4> 800ae24: 9b22 ldr r3, [sp, #136] ; 0x88 800ae26: 2b01 cmp r3, #1 800ae28: dc19 bgt.n 800ae5e <_dtoa_r+0x916> 800ae2a: 9b04 ldr r3, [sp, #16] 800ae2c: b9bb cbnz r3, 800ae5e <_dtoa_r+0x916> 800ae2e: 9b05 ldr r3, [sp, #20] 800ae30: f3c3 0313 ubfx r3, r3, #0, #20 800ae34: b99b cbnz r3, 800ae5e <_dtoa_r+0x916> 800ae36: 9b05 ldr r3, [sp, #20] 800ae38: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 800ae3c: 0d1b lsrs r3, r3, #20 800ae3e: 051b lsls r3, r3, #20 800ae40: b183 cbz r3, 800ae64 <_dtoa_r+0x91c> 800ae42: f04f 0801 mov.w r8, #1 800ae46: 9b06 ldr r3, [sp, #24] 800ae48: 3301 adds r3, #1 800ae4a: 9306 str r3, [sp, #24] 800ae4c: 9b09 ldr r3, [sp, #36] ; 0x24 800ae4e: 3301 adds r3, #1 800ae50: 9309 str r3, [sp, #36] ; 0x24 800ae52: 9b0e ldr r3, [sp, #56] ; 0x38 800ae54: 2b00 cmp r3, #0 800ae56: f47f af6a bne.w 800ad2e <_dtoa_r+0x7e6> 800ae5a: 2001 movs r0, #1 800ae5c: e76f b.n 800ad3e <_dtoa_r+0x7f6> 800ae5e: f04f 0800 mov.w r8, #0 800ae62: e7f6 b.n 800ae52 <_dtoa_r+0x90a> 800ae64: 4698 mov r8, r3 800ae66: e7f4 b.n 800ae52 <_dtoa_r+0x90a> 800ae68: f43f af7d beq.w 800ad66 <_dtoa_r+0x81e> 800ae6c: 4618 mov r0, r3 800ae6e: 301c adds r0, #28 800ae70: e772 b.n 800ad58 <_dtoa_r+0x810> 800ae72: 9b08 ldr r3, [sp, #32] 800ae74: 2b00 cmp r3, #0 800ae76: dc36 bgt.n 800aee6 <_dtoa_r+0x99e> 800ae78: 9b22 ldr r3, [sp, #136] ; 0x88 800ae7a: 2b02 cmp r3, #2 800ae7c: dd33 ble.n 800aee6 <_dtoa_r+0x99e> 800ae7e: f8dd 9020 ldr.w r9, [sp, #32] 800ae82: f1b9 0f00 cmp.w r9, #0 800ae86: d10d bne.n 800aea4 <_dtoa_r+0x95c> 800ae88: 4621 mov r1, r4 800ae8a: 464b mov r3, r9 800ae8c: 2205 movs r2, #5 800ae8e: 4628 mov r0, r5 800ae90: f000 fc40 bl 800b714 <__multadd> 800ae94: 4601 mov r1, r0 800ae96: 4604 mov r4, r0 800ae98: 4658 mov r0, fp 800ae9a: f000 fe57 bl 800bb4c <__mcmp> 800ae9e: 2800 cmp r0, #0 800aea0: f73f adb8 bgt.w 800aa14 <_dtoa_r+0x4cc> 800aea4: 9b23 ldr r3, [sp, #140] ; 0x8c 800aea6: 9f03 ldr r7, [sp, #12] 800aea8: ea6f 0a03 mvn.w sl, r3 800aeac: f04f 0800 mov.w r8, #0 800aeb0: 4621 mov r1, r4 800aeb2: 4628 mov r0, r5 800aeb4: f000 fc0c bl 800b6d0 <_Bfree> 800aeb8: 2e00 cmp r6, #0 800aeba: f43f aea7 beq.w 800ac0c <_dtoa_r+0x6c4> 800aebe: f1b8 0f00 cmp.w r8, #0 800aec2: d005 beq.n 800aed0 <_dtoa_r+0x988> 800aec4: 45b0 cmp r8, r6 800aec6: d003 beq.n 800aed0 <_dtoa_r+0x988> 800aec8: 4641 mov r1, r8 800aeca: 4628 mov r0, r5 800aecc: f000 fc00 bl 800b6d0 <_Bfree> 800aed0: 4631 mov r1, r6 800aed2: 4628 mov r0, r5 800aed4: f000 fbfc bl 800b6d0 <_Bfree> 800aed8: e698 b.n 800ac0c <_dtoa_r+0x6c4> 800aeda: 2400 movs r4, #0 800aedc: 4626 mov r6, r4 800aede: e7e1 b.n 800aea4 <_dtoa_r+0x95c> 800aee0: 46c2 mov sl, r8 800aee2: 4626 mov r6, r4 800aee4: e596 b.n 800aa14 <_dtoa_r+0x4cc> 800aee6: 9b0b ldr r3, [sp, #44] ; 0x2c 800aee8: f8dd 9020 ldr.w r9, [sp, #32] 800aeec: 2b00 cmp r3, #0 800aeee: f000 80fd beq.w 800b0ec <_dtoa_r+0xba4> 800aef2: 2f00 cmp r7, #0 800aef4: dd05 ble.n 800af02 <_dtoa_r+0x9ba> 800aef6: 4631 mov r1, r6 800aef8: 463a mov r2, r7 800aefa: 4628 mov r0, r5 800aefc: f000 fdb6 bl 800ba6c <__lshift> 800af00: 4606 mov r6, r0 800af02: f1b8 0f00 cmp.w r8, #0 800af06: d05c beq.n 800afc2 <_dtoa_r+0xa7a> 800af08: 4628 mov r0, r5 800af0a: 6871 ldr r1, [r6, #4] 800af0c: f000 fba0 bl 800b650 <_Balloc> 800af10: 4607 mov r7, r0 800af12: b928 cbnz r0, 800af20 <_dtoa_r+0x9d8> 800af14: 4602 mov r2, r0 800af16: f240 21ea movw r1, #746 ; 0x2ea 800af1a: 4b7f ldr r3, [pc, #508] ; (800b118 <_dtoa_r+0xbd0>) 800af1c: f7ff bb28 b.w 800a570 <_dtoa_r+0x28> 800af20: 6932 ldr r2, [r6, #16] 800af22: f106 010c add.w r1, r6, #12 800af26: 3202 adds r2, #2 800af28: 0092 lsls r2, r2, #2 800af2a: 300c adds r0, #12 800af2c: f7fe f960 bl 80091f0 800af30: 2201 movs r2, #1 800af32: 4639 mov r1, r7 800af34: 4628 mov r0, r5 800af36: f000 fd99 bl 800ba6c <__lshift> 800af3a: 46b0 mov r8, r6 800af3c: 4606 mov r6, r0 800af3e: 9b03 ldr r3, [sp, #12] 800af40: 3301 adds r3, #1 800af42: 9308 str r3, [sp, #32] 800af44: 9b03 ldr r3, [sp, #12] 800af46: 444b add r3, r9 800af48: 930a str r3, [sp, #40] ; 0x28 800af4a: 9b04 ldr r3, [sp, #16] 800af4c: f003 0301 and.w r3, r3, #1 800af50: 9309 str r3, [sp, #36] ; 0x24 800af52: 9b08 ldr r3, [sp, #32] 800af54: 4621 mov r1, r4 800af56: 3b01 subs r3, #1 800af58: 4658 mov r0, fp 800af5a: 9304 str r3, [sp, #16] 800af5c: f7ff fa68 bl 800a430 800af60: 4603 mov r3, r0 800af62: 4641 mov r1, r8 800af64: 3330 adds r3, #48 ; 0x30 800af66: 9006 str r0, [sp, #24] 800af68: 4658 mov r0, fp 800af6a: 930b str r3, [sp, #44] ; 0x2c 800af6c: f000 fdee bl 800bb4c <__mcmp> 800af70: 4632 mov r2, r6 800af72: 4681 mov r9, r0 800af74: 4621 mov r1, r4 800af76: 4628 mov r0, r5 800af78: f000 fe04 bl 800bb84 <__mdiff> 800af7c: 68c2 ldr r2, [r0, #12] 800af7e: 4607 mov r7, r0 800af80: 9b0b ldr r3, [sp, #44] ; 0x2c 800af82: bb02 cbnz r2, 800afc6 <_dtoa_r+0xa7e> 800af84: 4601 mov r1, r0 800af86: 4658 mov r0, fp 800af88: f000 fde0 bl 800bb4c <__mcmp> 800af8c: 4602 mov r2, r0 800af8e: 9b0b ldr r3, [sp, #44] ; 0x2c 800af90: 4639 mov r1, r7 800af92: 4628 mov r0, r5 800af94: e9cd 320b strd r3, r2, [sp, #44] ; 0x2c 800af98: f000 fb9a bl 800b6d0 <_Bfree> 800af9c: 9b22 ldr r3, [sp, #136] ; 0x88 800af9e: 9a0c ldr r2, [sp, #48] ; 0x30 800afa0: 9f08 ldr r7, [sp, #32] 800afa2: ea43 0102 orr.w r1, r3, r2 800afa6: 9b09 ldr r3, [sp, #36] ; 0x24 800afa8: 430b orrs r3, r1 800afaa: 9b0b ldr r3, [sp, #44] ; 0x2c 800afac: d10d bne.n 800afca <_dtoa_r+0xa82> 800afae: 2b39 cmp r3, #57 ; 0x39 800afb0: d029 beq.n 800b006 <_dtoa_r+0xabe> 800afb2: f1b9 0f00 cmp.w r9, #0 800afb6: dd01 ble.n 800afbc <_dtoa_r+0xa74> 800afb8: 9b06 ldr r3, [sp, #24] 800afba: 3331 adds r3, #49 ; 0x31 800afbc: 9a04 ldr r2, [sp, #16] 800afbe: 7013 strb r3, [r2, #0] 800afc0: e776 b.n 800aeb0 <_dtoa_r+0x968> 800afc2: 4630 mov r0, r6 800afc4: e7b9 b.n 800af3a <_dtoa_r+0x9f2> 800afc6: 2201 movs r2, #1 800afc8: e7e2 b.n 800af90 <_dtoa_r+0xa48> 800afca: f1b9 0f00 cmp.w r9, #0 800afce: db06 blt.n 800afde <_dtoa_r+0xa96> 800afd0: 9922 ldr r1, [sp, #136] ; 0x88 800afd2: ea41 0909 orr.w r9, r1, r9 800afd6: 9909 ldr r1, [sp, #36] ; 0x24 800afd8: ea59 0101 orrs.w r1, r9, r1 800afdc: d120 bne.n 800b020 <_dtoa_r+0xad8> 800afde: 2a00 cmp r2, #0 800afe0: ddec ble.n 800afbc <_dtoa_r+0xa74> 800afe2: 4659 mov r1, fp 800afe4: 2201 movs r2, #1 800afe6: 4628 mov r0, r5 800afe8: 9308 str r3, [sp, #32] 800afea: f000 fd3f bl 800ba6c <__lshift> 800afee: 4621 mov r1, r4 800aff0: 4683 mov fp, r0 800aff2: f000 fdab bl 800bb4c <__mcmp> 800aff6: 2800 cmp r0, #0 800aff8: 9b08 ldr r3, [sp, #32] 800affa: dc02 bgt.n 800b002 <_dtoa_r+0xaba> 800affc: d1de bne.n 800afbc <_dtoa_r+0xa74> 800affe: 07da lsls r2, r3, #31 800b000: d5dc bpl.n 800afbc <_dtoa_r+0xa74> 800b002: 2b39 cmp r3, #57 ; 0x39 800b004: d1d8 bne.n 800afb8 <_dtoa_r+0xa70> 800b006: 2339 movs r3, #57 ; 0x39 800b008: 9a04 ldr r2, [sp, #16] 800b00a: 7013 strb r3, [r2, #0] 800b00c: 463b mov r3, r7 800b00e: 461f mov r7, r3 800b010: f817 2c01 ldrb.w r2, [r7, #-1] 800b014: 3b01 subs r3, #1 800b016: 2a39 cmp r2, #57 ; 0x39 800b018: d050 beq.n 800b0bc <_dtoa_r+0xb74> 800b01a: 3201 adds r2, #1 800b01c: 701a strb r2, [r3, #0] 800b01e: e747 b.n 800aeb0 <_dtoa_r+0x968> 800b020: 2a00 cmp r2, #0 800b022: dd03 ble.n 800b02c <_dtoa_r+0xae4> 800b024: 2b39 cmp r3, #57 ; 0x39 800b026: d0ee beq.n 800b006 <_dtoa_r+0xabe> 800b028: 3301 adds r3, #1 800b02a: e7c7 b.n 800afbc <_dtoa_r+0xa74> 800b02c: 9a08 ldr r2, [sp, #32] 800b02e: 990a ldr r1, [sp, #40] ; 0x28 800b030: f802 3c01 strb.w r3, [r2, #-1] 800b034: 428a cmp r2, r1 800b036: d02a beq.n 800b08e <_dtoa_r+0xb46> 800b038: 4659 mov r1, fp 800b03a: 2300 movs r3, #0 800b03c: 220a movs r2, #10 800b03e: 4628 mov r0, r5 800b040: f000 fb68 bl 800b714 <__multadd> 800b044: 45b0 cmp r8, r6 800b046: 4683 mov fp, r0 800b048: f04f 0300 mov.w r3, #0 800b04c: f04f 020a mov.w r2, #10 800b050: 4641 mov r1, r8 800b052: 4628 mov r0, r5 800b054: d107 bne.n 800b066 <_dtoa_r+0xb1e> 800b056: f000 fb5d bl 800b714 <__multadd> 800b05a: 4680 mov r8, r0 800b05c: 4606 mov r6, r0 800b05e: 9b08 ldr r3, [sp, #32] 800b060: 3301 adds r3, #1 800b062: 9308 str r3, [sp, #32] 800b064: e775 b.n 800af52 <_dtoa_r+0xa0a> 800b066: f000 fb55 bl 800b714 <__multadd> 800b06a: 4631 mov r1, r6 800b06c: 4680 mov r8, r0 800b06e: 2300 movs r3, #0 800b070: 220a movs r2, #10 800b072: 4628 mov r0, r5 800b074: f000 fb4e bl 800b714 <__multadd> 800b078: 4606 mov r6, r0 800b07a: e7f0 b.n 800b05e <_dtoa_r+0xb16> 800b07c: f1b9 0f00 cmp.w r9, #0 800b080: bfcc ite gt 800b082: 464f movgt r7, r9 800b084: 2701 movle r7, #1 800b086: f04f 0800 mov.w r8, #0 800b08a: 9a03 ldr r2, [sp, #12] 800b08c: 4417 add r7, r2 800b08e: 4659 mov r1, fp 800b090: 2201 movs r2, #1 800b092: 4628 mov r0, r5 800b094: 9308 str r3, [sp, #32] 800b096: f000 fce9 bl 800ba6c <__lshift> 800b09a: 4621 mov r1, r4 800b09c: 4683 mov fp, r0 800b09e: f000 fd55 bl 800bb4c <__mcmp> 800b0a2: 2800 cmp r0, #0 800b0a4: dcb2 bgt.n 800b00c <_dtoa_r+0xac4> 800b0a6: d102 bne.n 800b0ae <_dtoa_r+0xb66> 800b0a8: 9b08 ldr r3, [sp, #32] 800b0aa: 07db lsls r3, r3, #31 800b0ac: d4ae bmi.n 800b00c <_dtoa_r+0xac4> 800b0ae: 463b mov r3, r7 800b0b0: 461f mov r7, r3 800b0b2: f813 2d01 ldrb.w r2, [r3, #-1]! 800b0b6: 2a30 cmp r2, #48 ; 0x30 800b0b8: d0fa beq.n 800b0b0 <_dtoa_r+0xb68> 800b0ba: e6f9 b.n 800aeb0 <_dtoa_r+0x968> 800b0bc: 9a03 ldr r2, [sp, #12] 800b0be: 429a cmp r2, r3 800b0c0: d1a5 bne.n 800b00e <_dtoa_r+0xac6> 800b0c2: 2331 movs r3, #49 ; 0x31 800b0c4: f10a 0a01 add.w sl, sl, #1 800b0c8: e779 b.n 800afbe <_dtoa_r+0xa76> 800b0ca: 4b14 ldr r3, [pc, #80] ; (800b11c <_dtoa_r+0xbd4>) 800b0cc: f7ff baa8 b.w 800a620 <_dtoa_r+0xd8> 800b0d0: 9b26 ldr r3, [sp, #152] ; 0x98 800b0d2: 2b00 cmp r3, #0 800b0d4: f47f aa81 bne.w 800a5da <_dtoa_r+0x92> 800b0d8: 4b11 ldr r3, [pc, #68] ; (800b120 <_dtoa_r+0xbd8>) 800b0da: f7ff baa1 b.w 800a620 <_dtoa_r+0xd8> 800b0de: f1b9 0f00 cmp.w r9, #0 800b0e2: dc03 bgt.n 800b0ec <_dtoa_r+0xba4> 800b0e4: 9b22 ldr r3, [sp, #136] ; 0x88 800b0e6: 2b02 cmp r3, #2 800b0e8: f73f aecb bgt.w 800ae82 <_dtoa_r+0x93a> 800b0ec: 9f03 ldr r7, [sp, #12] 800b0ee: 4621 mov r1, r4 800b0f0: 4658 mov r0, fp 800b0f2: f7ff f99d bl 800a430 800b0f6: 9a03 ldr r2, [sp, #12] 800b0f8: f100 0330 add.w r3, r0, #48 ; 0x30 800b0fc: f807 3b01 strb.w r3, [r7], #1 800b100: 1aba subs r2, r7, r2 800b102: 4591 cmp r9, r2 800b104: ddba ble.n 800b07c <_dtoa_r+0xb34> 800b106: 4659 mov r1, fp 800b108: 2300 movs r3, #0 800b10a: 220a movs r2, #10 800b10c: 4628 mov r0, r5 800b10e: f000 fb01 bl 800b714 <__multadd> 800b112: 4683 mov fp, r0 800b114: e7eb b.n 800b0ee <_dtoa_r+0xba6> 800b116: bf00 nop 800b118: 0800d4f2 .word 0x0800d4f2 800b11c: 0800d7dc .word 0x0800d7dc 800b120: 0800d48a .word 0x0800d48a 0800b124 <__sflush_r>: 800b124: 898a ldrh r2, [r1, #12] 800b126: b5f8 push {r3, r4, r5, r6, r7, lr} 800b128: 4605 mov r5, r0 800b12a: 0710 lsls r0, r2, #28 800b12c: 460c mov r4, r1 800b12e: d457 bmi.n 800b1e0 <__sflush_r+0xbc> 800b130: 684b ldr r3, [r1, #4] 800b132: 2b00 cmp r3, #0 800b134: dc04 bgt.n 800b140 <__sflush_r+0x1c> 800b136: 6c0b ldr r3, [r1, #64] ; 0x40 800b138: 2b00 cmp r3, #0 800b13a: dc01 bgt.n 800b140 <__sflush_r+0x1c> 800b13c: 2000 movs r0, #0 800b13e: bdf8 pop {r3, r4, r5, r6, r7, pc} 800b140: 6ae6 ldr r6, [r4, #44] ; 0x2c 800b142: 2e00 cmp r6, #0 800b144: d0fa beq.n 800b13c <__sflush_r+0x18> 800b146: 2300 movs r3, #0 800b148: f412 5280 ands.w r2, r2, #4096 ; 0x1000 800b14c: 682f ldr r7, [r5, #0] 800b14e: 602b str r3, [r5, #0] 800b150: d032 beq.n 800b1b8 <__sflush_r+0x94> 800b152: 6d60 ldr r0, [r4, #84] ; 0x54 800b154: 89a3 ldrh r3, [r4, #12] 800b156: 075a lsls r2, r3, #29 800b158: d505 bpl.n 800b166 <__sflush_r+0x42> 800b15a: 6863 ldr r3, [r4, #4] 800b15c: 1ac0 subs r0, r0, r3 800b15e: 6b63 ldr r3, [r4, #52] ; 0x34 800b160: b10b cbz r3, 800b166 <__sflush_r+0x42> 800b162: 6c23 ldr r3, [r4, #64] ; 0x40 800b164: 1ac0 subs r0, r0, r3 800b166: 2300 movs r3, #0 800b168: 4602 mov r2, r0 800b16a: 6ae6 ldr r6, [r4, #44] ; 0x2c 800b16c: 4628 mov r0, r5 800b16e: 6a21 ldr r1, [r4, #32] 800b170: 47b0 blx r6 800b172: 1c43 adds r3, r0, #1 800b174: 89a3 ldrh r3, [r4, #12] 800b176: d106 bne.n 800b186 <__sflush_r+0x62> 800b178: 6829 ldr r1, [r5, #0] 800b17a: 291d cmp r1, #29 800b17c: d82c bhi.n 800b1d8 <__sflush_r+0xb4> 800b17e: 4a29 ldr r2, [pc, #164] ; (800b224 <__sflush_r+0x100>) 800b180: 40ca lsrs r2, r1 800b182: 07d6 lsls r6, r2, #31 800b184: d528 bpl.n 800b1d8 <__sflush_r+0xb4> 800b186: 2200 movs r2, #0 800b188: 6062 str r2, [r4, #4] 800b18a: 6922 ldr r2, [r4, #16] 800b18c: 04d9 lsls r1, r3, #19 800b18e: 6022 str r2, [r4, #0] 800b190: d504 bpl.n 800b19c <__sflush_r+0x78> 800b192: 1c42 adds r2, r0, #1 800b194: d101 bne.n 800b19a <__sflush_r+0x76> 800b196: 682b ldr r3, [r5, #0] 800b198: b903 cbnz r3, 800b19c <__sflush_r+0x78> 800b19a: 6560 str r0, [r4, #84] ; 0x54 800b19c: 6b61 ldr r1, [r4, #52] ; 0x34 800b19e: 602f str r7, [r5, #0] 800b1a0: 2900 cmp r1, #0 800b1a2: d0cb beq.n 800b13c <__sflush_r+0x18> 800b1a4: f104 0344 add.w r3, r4, #68 ; 0x44 800b1a8: 4299 cmp r1, r3 800b1aa: d002 beq.n 800b1b2 <__sflush_r+0x8e> 800b1ac: 4628 mov r0, r5 800b1ae: f7fe f835 bl 800921c <_free_r> 800b1b2: 2000 movs r0, #0 800b1b4: 6360 str r0, [r4, #52] ; 0x34 800b1b6: e7c2 b.n 800b13e <__sflush_r+0x1a> 800b1b8: 6a21 ldr r1, [r4, #32] 800b1ba: 2301 movs r3, #1 800b1bc: 4628 mov r0, r5 800b1be: 47b0 blx r6 800b1c0: 1c41 adds r1, r0, #1 800b1c2: d1c7 bne.n 800b154 <__sflush_r+0x30> 800b1c4: 682b ldr r3, [r5, #0] 800b1c6: 2b00 cmp r3, #0 800b1c8: d0c4 beq.n 800b154 <__sflush_r+0x30> 800b1ca: 2b1d cmp r3, #29 800b1cc: d001 beq.n 800b1d2 <__sflush_r+0xae> 800b1ce: 2b16 cmp r3, #22 800b1d0: d101 bne.n 800b1d6 <__sflush_r+0xb2> 800b1d2: 602f str r7, [r5, #0] 800b1d4: e7b2 b.n 800b13c <__sflush_r+0x18> 800b1d6: 89a3 ldrh r3, [r4, #12] 800b1d8: f043 0340 orr.w r3, r3, #64 ; 0x40 800b1dc: 81a3 strh r3, [r4, #12] 800b1de: e7ae b.n 800b13e <__sflush_r+0x1a> 800b1e0: 690f ldr r7, [r1, #16] 800b1e2: 2f00 cmp r7, #0 800b1e4: d0aa beq.n 800b13c <__sflush_r+0x18> 800b1e6: 0793 lsls r3, r2, #30 800b1e8: bf18 it ne 800b1ea: 2300 movne r3, #0 800b1ec: 680e ldr r6, [r1, #0] 800b1ee: bf08 it eq 800b1f0: 694b ldreq r3, [r1, #20] 800b1f2: 1bf6 subs r6, r6, r7 800b1f4: 600f str r7, [r1, #0] 800b1f6: 608b str r3, [r1, #8] 800b1f8: 2e00 cmp r6, #0 800b1fa: dd9f ble.n 800b13c <__sflush_r+0x18> 800b1fc: 4633 mov r3, r6 800b1fe: 463a mov r2, r7 800b200: 4628 mov r0, r5 800b202: 6a21 ldr r1, [r4, #32] 800b204: f8d4 c028 ldr.w ip, [r4, #40] ; 0x28 800b208: 47e0 blx ip 800b20a: 2800 cmp r0, #0 800b20c: dc06 bgt.n 800b21c <__sflush_r+0xf8> 800b20e: 89a3 ldrh r3, [r4, #12] 800b210: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800b214: f043 0340 orr.w r3, r3, #64 ; 0x40 800b218: 81a3 strh r3, [r4, #12] 800b21a: e790 b.n 800b13e <__sflush_r+0x1a> 800b21c: 4407 add r7, r0 800b21e: 1a36 subs r6, r6, r0 800b220: e7ea b.n 800b1f8 <__sflush_r+0xd4> 800b222: bf00 nop 800b224: 20400001 .word 0x20400001 0800b228 <_fflush_r>: 800b228: b538 push {r3, r4, r5, lr} 800b22a: 690b ldr r3, [r1, #16] 800b22c: 4605 mov r5, r0 800b22e: 460c mov r4, r1 800b230: b913 cbnz r3, 800b238 <_fflush_r+0x10> 800b232: 2500 movs r5, #0 800b234: 4628 mov r0, r5 800b236: bd38 pop {r3, r4, r5, pc} 800b238: b118 cbz r0, 800b242 <_fflush_r+0x1a> 800b23a: 6983 ldr r3, [r0, #24] 800b23c: b90b cbnz r3, 800b242 <_fflush_r+0x1a> 800b23e: f000 f887 bl 800b350 <__sinit> 800b242: 4b14 ldr r3, [pc, #80] ; (800b294 <_fflush_r+0x6c>) 800b244: 429c cmp r4, r3 800b246: d11b bne.n 800b280 <_fflush_r+0x58> 800b248: 686c ldr r4, [r5, #4] 800b24a: f9b4 300c ldrsh.w r3, [r4, #12] 800b24e: 2b00 cmp r3, #0 800b250: d0ef beq.n 800b232 <_fflush_r+0xa> 800b252: 6e62 ldr r2, [r4, #100] ; 0x64 800b254: 07d0 lsls r0, r2, #31 800b256: d404 bmi.n 800b262 <_fflush_r+0x3a> 800b258: 0599 lsls r1, r3, #22 800b25a: d402 bmi.n 800b262 <_fflush_r+0x3a> 800b25c: 6da0 ldr r0, [r4, #88] ; 0x58 800b25e: f000 f975 bl 800b54c <__retarget_lock_acquire_recursive> 800b262: 4628 mov r0, r5 800b264: 4621 mov r1, r4 800b266: f7ff ff5d bl 800b124 <__sflush_r> 800b26a: 6e63 ldr r3, [r4, #100] ; 0x64 800b26c: 4605 mov r5, r0 800b26e: 07da lsls r2, r3, #31 800b270: d4e0 bmi.n 800b234 <_fflush_r+0xc> 800b272: 89a3 ldrh r3, [r4, #12] 800b274: 059b lsls r3, r3, #22 800b276: d4dd bmi.n 800b234 <_fflush_r+0xc> 800b278: 6da0 ldr r0, [r4, #88] ; 0x58 800b27a: f000 f969 bl 800b550 <__retarget_lock_release_recursive> 800b27e: e7d9 b.n 800b234 <_fflush_r+0xc> 800b280: 4b05 ldr r3, [pc, #20] ; (800b298 <_fflush_r+0x70>) 800b282: 429c cmp r4, r3 800b284: d101 bne.n 800b28a <_fflush_r+0x62> 800b286: 68ac ldr r4, [r5, #8] 800b288: e7df b.n 800b24a <_fflush_r+0x22> 800b28a: 4b04 ldr r3, [pc, #16] ; (800b29c <_fflush_r+0x74>) 800b28c: 429c cmp r4, r3 800b28e: bf08 it eq 800b290: 68ec ldreq r4, [r5, #12] 800b292: e7da b.n 800b24a <_fflush_r+0x22> 800b294: 0800d524 .word 0x0800d524 800b298: 0800d544 .word 0x0800d544 800b29c: 0800d504 .word 0x0800d504 0800b2a0 : 800b2a0: 2300 movs r3, #0 800b2a2: b510 push {r4, lr} 800b2a4: 4604 mov r4, r0 800b2a6: e9c0 3300 strd r3, r3, [r0] 800b2aa: e9c0 3304 strd r3, r3, [r0, #16] 800b2ae: 6083 str r3, [r0, #8] 800b2b0: 8181 strh r1, [r0, #12] 800b2b2: 6643 str r3, [r0, #100] ; 0x64 800b2b4: 81c2 strh r2, [r0, #14] 800b2b6: 6183 str r3, [r0, #24] 800b2b8: 4619 mov r1, r3 800b2ba: 2208 movs r2, #8 800b2bc: 305c adds r0, #92 ; 0x5c 800b2be: f7fd ffa5 bl 800920c 800b2c2: 4b05 ldr r3, [pc, #20] ; (800b2d8 ) 800b2c4: 6224 str r4, [r4, #32] 800b2c6: 6263 str r3, [r4, #36] ; 0x24 800b2c8: 4b04 ldr r3, [pc, #16] ; (800b2dc ) 800b2ca: 62a3 str r3, [r4, #40] ; 0x28 800b2cc: 4b04 ldr r3, [pc, #16] ; (800b2e0 ) 800b2ce: 62e3 str r3, [r4, #44] ; 0x2c 800b2d0: 4b04 ldr r3, [pc, #16] ; (800b2e4 ) 800b2d2: 6323 str r3, [r4, #48] ; 0x30 800b2d4: bd10 pop {r4, pc} 800b2d6: bf00 nop 800b2d8: 0800c081 .word 0x0800c081 800b2dc: 0800c0a7 .word 0x0800c0a7 800b2e0: 0800c0df .word 0x0800c0df 800b2e4: 0800c103 .word 0x0800c103 0800b2e8 <_cleanup_r>: 800b2e8: 4901 ldr r1, [pc, #4] ; (800b2f0 <_cleanup_r+0x8>) 800b2ea: f000 b8c1 b.w 800b470 <_fwalk_reent> 800b2ee: bf00 nop 800b2f0: 0800b229 .word 0x0800b229 0800b2f4 <__sfmoreglue>: 800b2f4: 2268 movs r2, #104 ; 0x68 800b2f6: b570 push {r4, r5, r6, lr} 800b2f8: 1e4d subs r5, r1, #1 800b2fa: 4355 muls r5, r2 800b2fc: 460e mov r6, r1 800b2fe: f105 0174 add.w r1, r5, #116 ; 0x74 800b302: f7fd fff3 bl 80092ec <_malloc_r> 800b306: 4604 mov r4, r0 800b308: b140 cbz r0, 800b31c <__sfmoreglue+0x28> 800b30a: 2100 movs r1, #0 800b30c: e9c0 1600 strd r1, r6, [r0] 800b310: 300c adds r0, #12 800b312: 60a0 str r0, [r4, #8] 800b314: f105 0268 add.w r2, r5, #104 ; 0x68 800b318: f7fd ff78 bl 800920c 800b31c: 4620 mov r0, r4 800b31e: bd70 pop {r4, r5, r6, pc} 0800b320 <__sfp_lock_acquire>: 800b320: 4801 ldr r0, [pc, #4] ; (800b328 <__sfp_lock_acquire+0x8>) 800b322: f000 b913 b.w 800b54c <__retarget_lock_acquire_recursive> 800b326: bf00 nop 800b328: 200033c6 .word 0x200033c6 0800b32c <__sfp_lock_release>: 800b32c: 4801 ldr r0, [pc, #4] ; (800b334 <__sfp_lock_release+0x8>) 800b32e: f000 b90f b.w 800b550 <__retarget_lock_release_recursive> 800b332: bf00 nop 800b334: 200033c6 .word 0x200033c6 0800b338 <__sinit_lock_acquire>: 800b338: 4801 ldr r0, [pc, #4] ; (800b340 <__sinit_lock_acquire+0x8>) 800b33a: f000 b907 b.w 800b54c <__retarget_lock_acquire_recursive> 800b33e: bf00 nop 800b340: 200033c7 .word 0x200033c7 0800b344 <__sinit_lock_release>: 800b344: 4801 ldr r0, [pc, #4] ; (800b34c <__sinit_lock_release+0x8>) 800b346: f000 b903 b.w 800b550 <__retarget_lock_release_recursive> 800b34a: bf00 nop 800b34c: 200033c7 .word 0x200033c7 0800b350 <__sinit>: 800b350: b510 push {r4, lr} 800b352: 4604 mov r4, r0 800b354: f7ff fff0 bl 800b338 <__sinit_lock_acquire> 800b358: 69a3 ldr r3, [r4, #24] 800b35a: b11b cbz r3, 800b364 <__sinit+0x14> 800b35c: e8bd 4010 ldmia.w sp!, {r4, lr} 800b360: f7ff bff0 b.w 800b344 <__sinit_lock_release> 800b364: e9c4 3312 strd r3, r3, [r4, #72] ; 0x48 800b368: 6523 str r3, [r4, #80] ; 0x50 800b36a: 4b13 ldr r3, [pc, #76] ; (800b3b8 <__sinit+0x68>) 800b36c: 4a13 ldr r2, [pc, #76] ; (800b3bc <__sinit+0x6c>) 800b36e: 681b ldr r3, [r3, #0] 800b370: 62a2 str r2, [r4, #40] ; 0x28 800b372: 42a3 cmp r3, r4 800b374: bf08 it eq 800b376: 2301 moveq r3, #1 800b378: 4620 mov r0, r4 800b37a: bf08 it eq 800b37c: 61a3 streq r3, [r4, #24] 800b37e: f000 f81f bl 800b3c0 <__sfp> 800b382: 6060 str r0, [r4, #4] 800b384: 4620 mov r0, r4 800b386: f000 f81b bl 800b3c0 <__sfp> 800b38a: 60a0 str r0, [r4, #8] 800b38c: 4620 mov r0, r4 800b38e: f000 f817 bl 800b3c0 <__sfp> 800b392: 2200 movs r2, #0 800b394: 2104 movs r1, #4 800b396: 60e0 str r0, [r4, #12] 800b398: 6860 ldr r0, [r4, #4] 800b39a: f7ff ff81 bl 800b2a0 800b39e: 2201 movs r2, #1 800b3a0: 2109 movs r1, #9 800b3a2: 68a0 ldr r0, [r4, #8] 800b3a4: f7ff ff7c bl 800b2a0 800b3a8: 2202 movs r2, #2 800b3aa: 2112 movs r1, #18 800b3ac: 68e0 ldr r0, [r4, #12] 800b3ae: f7ff ff77 bl 800b2a0 800b3b2: 2301 movs r3, #1 800b3b4: 61a3 str r3, [r4, #24] 800b3b6: e7d1 b.n 800b35c <__sinit+0xc> 800b3b8: 0800d320 .word 0x0800d320 800b3bc: 0800b2e9 .word 0x0800b2e9 0800b3c0 <__sfp>: 800b3c0: b5f8 push {r3, r4, r5, r6, r7, lr} 800b3c2: 4607 mov r7, r0 800b3c4: f7ff ffac bl 800b320 <__sfp_lock_acquire> 800b3c8: 4b1e ldr r3, [pc, #120] ; (800b444 <__sfp+0x84>) 800b3ca: 681e ldr r6, [r3, #0] 800b3cc: 69b3 ldr r3, [r6, #24] 800b3ce: b913 cbnz r3, 800b3d6 <__sfp+0x16> 800b3d0: 4630 mov r0, r6 800b3d2: f7ff ffbd bl 800b350 <__sinit> 800b3d6: 3648 adds r6, #72 ; 0x48 800b3d8: e9d6 3401 ldrd r3, r4, [r6, #4] 800b3dc: 3b01 subs r3, #1 800b3de: d503 bpl.n 800b3e8 <__sfp+0x28> 800b3e0: 6833 ldr r3, [r6, #0] 800b3e2: b30b cbz r3, 800b428 <__sfp+0x68> 800b3e4: 6836 ldr r6, [r6, #0] 800b3e6: e7f7 b.n 800b3d8 <__sfp+0x18> 800b3e8: f9b4 500c ldrsh.w r5, [r4, #12] 800b3ec: b9d5 cbnz r5, 800b424 <__sfp+0x64> 800b3ee: 4b16 ldr r3, [pc, #88] ; (800b448 <__sfp+0x88>) 800b3f0: f104 0058 add.w r0, r4, #88 ; 0x58 800b3f4: 60e3 str r3, [r4, #12] 800b3f6: 6665 str r5, [r4, #100] ; 0x64 800b3f8: f000 f8a6 bl 800b548 <__retarget_lock_init_recursive> 800b3fc: f7ff ff96 bl 800b32c <__sfp_lock_release> 800b400: 2208 movs r2, #8 800b402: 4629 mov r1, r5 800b404: e9c4 5501 strd r5, r5, [r4, #4] 800b408: e9c4 5504 strd r5, r5, [r4, #16] 800b40c: 6025 str r5, [r4, #0] 800b40e: 61a5 str r5, [r4, #24] 800b410: f104 005c add.w r0, r4, #92 ; 0x5c 800b414: f7fd fefa bl 800920c 800b418: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 800b41c: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 800b420: 4620 mov r0, r4 800b422: bdf8 pop {r3, r4, r5, r6, r7, pc} 800b424: 3468 adds r4, #104 ; 0x68 800b426: e7d9 b.n 800b3dc <__sfp+0x1c> 800b428: 2104 movs r1, #4 800b42a: 4638 mov r0, r7 800b42c: f7ff ff62 bl 800b2f4 <__sfmoreglue> 800b430: 4604 mov r4, r0 800b432: 6030 str r0, [r6, #0] 800b434: 2800 cmp r0, #0 800b436: d1d5 bne.n 800b3e4 <__sfp+0x24> 800b438: f7ff ff78 bl 800b32c <__sfp_lock_release> 800b43c: 230c movs r3, #12 800b43e: 603b str r3, [r7, #0] 800b440: e7ee b.n 800b420 <__sfp+0x60> 800b442: bf00 nop 800b444: 0800d320 .word 0x0800d320 800b448: ffff0001 .word 0xffff0001 0800b44c : 800b44c: b40e push {r1, r2, r3} 800b44e: b503 push {r0, r1, lr} 800b450: 4601 mov r1, r0 800b452: ab03 add r3, sp, #12 800b454: 4805 ldr r0, [pc, #20] ; (800b46c ) 800b456: f853 2b04 ldr.w r2, [r3], #4 800b45a: 6800 ldr r0, [r0, #0] 800b45c: 9301 str r3, [sp, #4] 800b45e: f000 fcb5 bl 800bdcc <_vfiprintf_r> 800b462: b002 add sp, #8 800b464: f85d eb04 ldr.w lr, [sp], #4 800b468: b003 add sp, #12 800b46a: 4770 bx lr 800b46c: 20000014 .word 0x20000014 0800b470 <_fwalk_reent>: 800b470: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 800b474: 4606 mov r6, r0 800b476: 4688 mov r8, r1 800b478: 2700 movs r7, #0 800b47a: f100 0448 add.w r4, r0, #72 ; 0x48 800b47e: e9d4 9501 ldrd r9, r5, [r4, #4] 800b482: f1b9 0901 subs.w r9, r9, #1 800b486: d505 bpl.n 800b494 <_fwalk_reent+0x24> 800b488: 6824 ldr r4, [r4, #0] 800b48a: 2c00 cmp r4, #0 800b48c: d1f7 bne.n 800b47e <_fwalk_reent+0xe> 800b48e: 4638 mov r0, r7 800b490: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 800b494: 89ab ldrh r3, [r5, #12] 800b496: 2b01 cmp r3, #1 800b498: d907 bls.n 800b4aa <_fwalk_reent+0x3a> 800b49a: f9b5 300e ldrsh.w r3, [r5, #14] 800b49e: 3301 adds r3, #1 800b4a0: d003 beq.n 800b4aa <_fwalk_reent+0x3a> 800b4a2: 4629 mov r1, r5 800b4a4: 4630 mov r0, r6 800b4a6: 47c0 blx r8 800b4a8: 4307 orrs r7, r0 800b4aa: 3568 adds r5, #104 ; 0x68 800b4ac: e7e9 b.n 800b482 <_fwalk_reent+0x12> ... 0800b4b0 <_findenv_r>: 800b4b0: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} 800b4b4: f8df a06c ldr.w sl, [pc, #108] ; 800b524 <_findenv_r+0x74> 800b4b8: 4607 mov r7, r0 800b4ba: 4689 mov r9, r1 800b4bc: 4616 mov r6, r2 800b4be: f000 fed5 bl 800c26c <__env_lock> 800b4c2: f8da 4000 ldr.w r4, [sl] 800b4c6: b134 cbz r4, 800b4d6 <_findenv_r+0x26> 800b4c8: 464b mov r3, r9 800b4ca: 4698 mov r8, r3 800b4cc: f813 2b01 ldrb.w r2, [r3], #1 800b4d0: b13a cbz r2, 800b4e2 <_findenv_r+0x32> 800b4d2: 2a3d cmp r2, #61 ; 0x3d 800b4d4: d1f9 bne.n 800b4ca <_findenv_r+0x1a> 800b4d6: 4638 mov r0, r7 800b4d8: f000 fece bl 800c278 <__env_unlock> 800b4dc: 2000 movs r0, #0 800b4de: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} 800b4e2: eba8 0809 sub.w r8, r8, r9 800b4e6: 46a3 mov fp, r4 800b4e8: f854 0b04 ldr.w r0, [r4], #4 800b4ec: 2800 cmp r0, #0 800b4ee: d0f2 beq.n 800b4d6 <_findenv_r+0x26> 800b4f0: 4642 mov r2, r8 800b4f2: 4649 mov r1, r9 800b4f4: f7fe fc6c bl 8009dd0 800b4f8: 2800 cmp r0, #0 800b4fa: d1f4 bne.n 800b4e6 <_findenv_r+0x36> 800b4fc: f854 3c04 ldr.w r3, [r4, #-4] 800b500: eb03 0508 add.w r5, r3, r8 800b504: f813 3008 ldrb.w r3, [r3, r8] 800b508: 2b3d cmp r3, #61 ; 0x3d 800b50a: d1ec bne.n 800b4e6 <_findenv_r+0x36> 800b50c: f8da 3000 ldr.w r3, [sl] 800b510: 4638 mov r0, r7 800b512: ebab 0303 sub.w r3, fp, r3 800b516: 109b asrs r3, r3, #2 800b518: 6033 str r3, [r6, #0] 800b51a: f000 fead bl 800c278 <__env_unlock> 800b51e: 1c68 adds r0, r5, #1 800b520: e7dd b.n 800b4de <_findenv_r+0x2e> 800b522: bf00 nop 800b524: 20000004 .word 0x20000004 0800b528 <_getenv_r>: 800b528: b507 push {r0, r1, r2, lr} 800b52a: aa01 add r2, sp, #4 800b52c: f7ff ffc0 bl 800b4b0 <_findenv_r> 800b530: b003 add sp, #12 800b532: f85d fb04 ldr.w pc, [sp], #4 ... 0800b538 <__gettzinfo>: 800b538: 4800 ldr r0, [pc, #0] ; (800b53c <__gettzinfo+0x4>) 800b53a: 4770 bx lr 800b53c: 20000080 .word 0x20000080 0800b540 <_localeconv_r>: 800b540: 4800 ldr r0, [pc, #0] ; (800b544 <_localeconv_r+0x4>) 800b542: 4770 bx lr 800b544: 200001c8 .word 0x200001c8 0800b548 <__retarget_lock_init_recursive>: 800b548: 4770 bx lr 0800b54a <__retarget_lock_acquire>: 800b54a: 4770 bx lr 0800b54c <__retarget_lock_acquire_recursive>: 800b54c: 4770 bx lr 0800b54e <__retarget_lock_release>: 800b54e: 4770 bx lr 0800b550 <__retarget_lock_release_recursive>: 800b550: 4770 bx lr 0800b552 <__swhatbuf_r>: 800b552: b570 push {r4, r5, r6, lr} 800b554: 460e mov r6, r1 800b556: f9b1 100e ldrsh.w r1, [r1, #14] 800b55a: 4614 mov r4, r2 800b55c: 2900 cmp r1, #0 800b55e: 461d mov r5, r3 800b560: b096 sub sp, #88 ; 0x58 800b562: da08 bge.n 800b576 <__swhatbuf_r+0x24> 800b564: 2200 movs r2, #0 800b566: f9b6 300c ldrsh.w r3, [r6, #12] 800b56a: 602a str r2, [r5, #0] 800b56c: 061a lsls r2, r3, #24 800b56e: d410 bmi.n 800b592 <__swhatbuf_r+0x40> 800b570: f44f 6380 mov.w r3, #1024 ; 0x400 800b574: e00e b.n 800b594 <__swhatbuf_r+0x42> 800b576: 466a mov r2, sp 800b578: f000 fe84 bl 800c284 <_fstat_r> 800b57c: 2800 cmp r0, #0 800b57e: dbf1 blt.n 800b564 <__swhatbuf_r+0x12> 800b580: 9a01 ldr r2, [sp, #4] 800b582: f402 4270 and.w r2, r2, #61440 ; 0xf000 800b586: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 800b58a: 425a negs r2, r3 800b58c: 415a adcs r2, r3 800b58e: 602a str r2, [r5, #0] 800b590: e7ee b.n 800b570 <__swhatbuf_r+0x1e> 800b592: 2340 movs r3, #64 ; 0x40 800b594: 2000 movs r0, #0 800b596: 6023 str r3, [r4, #0] 800b598: b016 add sp, #88 ; 0x58 800b59a: bd70 pop {r4, r5, r6, pc} 0800b59c <__smakebuf_r>: 800b59c: 898b ldrh r3, [r1, #12] 800b59e: b573 push {r0, r1, r4, r5, r6, lr} 800b5a0: 079d lsls r5, r3, #30 800b5a2: 4606 mov r6, r0 800b5a4: 460c mov r4, r1 800b5a6: d507 bpl.n 800b5b8 <__smakebuf_r+0x1c> 800b5a8: f104 0347 add.w r3, r4, #71 ; 0x47 800b5ac: 6023 str r3, [r4, #0] 800b5ae: 6123 str r3, [r4, #16] 800b5b0: 2301 movs r3, #1 800b5b2: 6163 str r3, [r4, #20] 800b5b4: b002 add sp, #8 800b5b6: bd70 pop {r4, r5, r6, pc} 800b5b8: 466a mov r2, sp 800b5ba: ab01 add r3, sp, #4 800b5bc: f7ff ffc9 bl 800b552 <__swhatbuf_r> 800b5c0: 9900 ldr r1, [sp, #0] 800b5c2: 4605 mov r5, r0 800b5c4: 4630 mov r0, r6 800b5c6: f7fd fe91 bl 80092ec <_malloc_r> 800b5ca: b948 cbnz r0, 800b5e0 <__smakebuf_r+0x44> 800b5cc: f9b4 300c ldrsh.w r3, [r4, #12] 800b5d0: 059a lsls r2, r3, #22 800b5d2: d4ef bmi.n 800b5b4 <__smakebuf_r+0x18> 800b5d4: f023 0303 bic.w r3, r3, #3 800b5d8: f043 0302 orr.w r3, r3, #2 800b5dc: 81a3 strh r3, [r4, #12] 800b5de: e7e3 b.n 800b5a8 <__smakebuf_r+0xc> 800b5e0: 4b0d ldr r3, [pc, #52] ; (800b618 <__smakebuf_r+0x7c>) 800b5e2: 62b3 str r3, [r6, #40] ; 0x28 800b5e4: 89a3 ldrh r3, [r4, #12] 800b5e6: 6020 str r0, [r4, #0] 800b5e8: f043 0380 orr.w r3, r3, #128 ; 0x80 800b5ec: 81a3 strh r3, [r4, #12] 800b5ee: 9b00 ldr r3, [sp, #0] 800b5f0: 6120 str r0, [r4, #16] 800b5f2: 6163 str r3, [r4, #20] 800b5f4: 9b01 ldr r3, [sp, #4] 800b5f6: b15b cbz r3, 800b610 <__smakebuf_r+0x74> 800b5f8: 4630 mov r0, r6 800b5fa: f9b4 100e ldrsh.w r1, [r4, #14] 800b5fe: f000 fe53 bl 800c2a8 <_isatty_r> 800b602: b128 cbz r0, 800b610 <__smakebuf_r+0x74> 800b604: 89a3 ldrh r3, [r4, #12] 800b606: f023 0303 bic.w r3, r3, #3 800b60a: f043 0301 orr.w r3, r3, #1 800b60e: 81a3 strh r3, [r4, #12] 800b610: 89a0 ldrh r0, [r4, #12] 800b612: 4305 orrs r5, r0 800b614: 81a5 strh r5, [r4, #12] 800b616: e7cd b.n 800b5b4 <__smakebuf_r+0x18> 800b618: 0800b2e9 .word 0x0800b2e9 0800b61c : 800b61c: 4603 mov r3, r0 800b61e: b510 push {r4, lr} 800b620: b2c9 uxtb r1, r1 800b622: 4402 add r2, r0 800b624: 4293 cmp r3, r2 800b626: 4618 mov r0, r3 800b628: d101 bne.n 800b62e 800b62a: 2000 movs r0, #0 800b62c: e003 b.n 800b636 800b62e: 7804 ldrb r4, [r0, #0] 800b630: 3301 adds r3, #1 800b632: 428c cmp r4, r1 800b634: d1f6 bne.n 800b624 800b636: bd10 pop {r4, pc} 0800b638 <__malloc_lock>: 800b638: 4801 ldr r0, [pc, #4] ; (800b640 <__malloc_lock+0x8>) 800b63a: f7ff bf87 b.w 800b54c <__retarget_lock_acquire_recursive> 800b63e: bf00 nop 800b640: 200033c5 .word 0x200033c5 0800b644 <__malloc_unlock>: 800b644: 4801 ldr r0, [pc, #4] ; (800b64c <__malloc_unlock+0x8>) 800b646: f7ff bf83 b.w 800b550 <__retarget_lock_release_recursive> 800b64a: bf00 nop 800b64c: 200033c5 .word 0x200033c5 0800b650 <_Balloc>: 800b650: b570 push {r4, r5, r6, lr} 800b652: 6a46 ldr r6, [r0, #36] ; 0x24 800b654: 4604 mov r4, r0 800b656: 460d mov r5, r1 800b658: b976 cbnz r6, 800b678 <_Balloc+0x28> 800b65a: 2010 movs r0, #16 800b65c: f7fd fdb8 bl 80091d0 800b660: 4602 mov r2, r0 800b662: 6260 str r0, [r4, #36] ; 0x24 800b664: b920 cbnz r0, 800b670 <_Balloc+0x20> 800b666: 2166 movs r1, #102 ; 0x66 800b668: 4b17 ldr r3, [pc, #92] ; (800b6c8 <_Balloc+0x78>) 800b66a: 4818 ldr r0, [pc, #96] ; (800b6cc <_Balloc+0x7c>) 800b66c: f7fe fec2 bl 800a3f4 <__assert_func> 800b670: e9c0 6601 strd r6, r6, [r0, #4] 800b674: 6006 str r6, [r0, #0] 800b676: 60c6 str r6, [r0, #12] 800b678: 6a66 ldr r6, [r4, #36] ; 0x24 800b67a: 68f3 ldr r3, [r6, #12] 800b67c: b183 cbz r3, 800b6a0 <_Balloc+0x50> 800b67e: 6a63 ldr r3, [r4, #36] ; 0x24 800b680: 68db ldr r3, [r3, #12] 800b682: f853 0025 ldr.w r0, [r3, r5, lsl #2] 800b686: b9b8 cbnz r0, 800b6b8 <_Balloc+0x68> 800b688: 2101 movs r1, #1 800b68a: fa01 f605 lsl.w r6, r1, r5 800b68e: 1d72 adds r2, r6, #5 800b690: 4620 mov r0, r4 800b692: 0092 lsls r2, r2, #2 800b694: f000 fb5e bl 800bd54 <_calloc_r> 800b698: b160 cbz r0, 800b6b4 <_Balloc+0x64> 800b69a: e9c0 5601 strd r5, r6, [r0, #4] 800b69e: e00e b.n 800b6be <_Balloc+0x6e> 800b6a0: 2221 movs r2, #33 ; 0x21 800b6a2: 2104 movs r1, #4 800b6a4: 4620 mov r0, r4 800b6a6: f000 fb55 bl 800bd54 <_calloc_r> 800b6aa: 6a63 ldr r3, [r4, #36] ; 0x24 800b6ac: 60f0 str r0, [r6, #12] 800b6ae: 68db ldr r3, [r3, #12] 800b6b0: 2b00 cmp r3, #0 800b6b2: d1e4 bne.n 800b67e <_Balloc+0x2e> 800b6b4: 2000 movs r0, #0 800b6b6: bd70 pop {r4, r5, r6, pc} 800b6b8: 6802 ldr r2, [r0, #0] 800b6ba: f843 2025 str.w r2, [r3, r5, lsl #2] 800b6be: 2300 movs r3, #0 800b6c0: e9c0 3303 strd r3, r3, [r0, #12] 800b6c4: e7f7 b.n 800b6b6 <_Balloc+0x66> 800b6c6: bf00 nop 800b6c8: 0800d2ac .word 0x0800d2ac 800b6cc: 0800d564 .word 0x0800d564 0800b6d0 <_Bfree>: 800b6d0: b570 push {r4, r5, r6, lr} 800b6d2: 6a46 ldr r6, [r0, #36] ; 0x24 800b6d4: 4605 mov r5, r0 800b6d6: 460c mov r4, r1 800b6d8: b976 cbnz r6, 800b6f8 <_Bfree+0x28> 800b6da: 2010 movs r0, #16 800b6dc: f7fd fd78 bl 80091d0 800b6e0: 4602 mov r2, r0 800b6e2: 6268 str r0, [r5, #36] ; 0x24 800b6e4: b920 cbnz r0, 800b6f0 <_Bfree+0x20> 800b6e6: 218a movs r1, #138 ; 0x8a 800b6e8: 4b08 ldr r3, [pc, #32] ; (800b70c <_Bfree+0x3c>) 800b6ea: 4809 ldr r0, [pc, #36] ; (800b710 <_Bfree+0x40>) 800b6ec: f7fe fe82 bl 800a3f4 <__assert_func> 800b6f0: e9c0 6601 strd r6, r6, [r0, #4] 800b6f4: 6006 str r6, [r0, #0] 800b6f6: 60c6 str r6, [r0, #12] 800b6f8: b13c cbz r4, 800b70a <_Bfree+0x3a> 800b6fa: 6a6b ldr r3, [r5, #36] ; 0x24 800b6fc: 6862 ldr r2, [r4, #4] 800b6fe: 68db ldr r3, [r3, #12] 800b700: f853 1022 ldr.w r1, [r3, r2, lsl #2] 800b704: 6021 str r1, [r4, #0] 800b706: f843 4022 str.w r4, [r3, r2, lsl #2] 800b70a: bd70 pop {r4, r5, r6, pc} 800b70c: 0800d2ac .word 0x0800d2ac 800b710: 0800d564 .word 0x0800d564 0800b714 <__multadd>: 800b714: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800b718: 4607 mov r7, r0 800b71a: 460c mov r4, r1 800b71c: 461e mov r6, r3 800b71e: 2000 movs r0, #0 800b720: 690d ldr r5, [r1, #16] 800b722: f101 0c14 add.w ip, r1, #20 800b726: f8dc 3000 ldr.w r3, [ip] 800b72a: 3001 adds r0, #1 800b72c: b299 uxth r1, r3 800b72e: fb02 6101 mla r1, r2, r1, r6 800b732: 0c1e lsrs r6, r3, #16 800b734: 0c0b lsrs r3, r1, #16 800b736: fb02 3306 mla r3, r2, r6, r3 800b73a: b289 uxth r1, r1 800b73c: eb01 4103 add.w r1, r1, r3, lsl #16 800b740: 4285 cmp r5, r0 800b742: ea4f 4613 mov.w r6, r3, lsr #16 800b746: f84c 1b04 str.w r1, [ip], #4 800b74a: dcec bgt.n 800b726 <__multadd+0x12> 800b74c: b30e cbz r6, 800b792 <__multadd+0x7e> 800b74e: 68a3 ldr r3, [r4, #8] 800b750: 42ab cmp r3, r5 800b752: dc19 bgt.n 800b788 <__multadd+0x74> 800b754: 6861 ldr r1, [r4, #4] 800b756: 4638 mov r0, r7 800b758: 3101 adds r1, #1 800b75a: f7ff ff79 bl 800b650 <_Balloc> 800b75e: 4680 mov r8, r0 800b760: b928 cbnz r0, 800b76e <__multadd+0x5a> 800b762: 4602 mov r2, r0 800b764: 21b5 movs r1, #181 ; 0xb5 800b766: 4b0c ldr r3, [pc, #48] ; (800b798 <__multadd+0x84>) 800b768: 480c ldr r0, [pc, #48] ; (800b79c <__multadd+0x88>) 800b76a: f7fe fe43 bl 800a3f4 <__assert_func> 800b76e: 6922 ldr r2, [r4, #16] 800b770: f104 010c add.w r1, r4, #12 800b774: 3202 adds r2, #2 800b776: 0092 lsls r2, r2, #2 800b778: 300c adds r0, #12 800b77a: f7fd fd39 bl 80091f0 800b77e: 4621 mov r1, r4 800b780: 4638 mov r0, r7 800b782: f7ff ffa5 bl 800b6d0 <_Bfree> 800b786: 4644 mov r4, r8 800b788: eb04 0385 add.w r3, r4, r5, lsl #2 800b78c: 3501 adds r5, #1 800b78e: 615e str r6, [r3, #20] 800b790: 6125 str r5, [r4, #16] 800b792: 4620 mov r0, r4 800b794: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800b798: 0800d4f2 .word 0x0800d4f2 800b79c: 0800d564 .word 0x0800d564 0800b7a0 <__hi0bits>: 800b7a0: 0c02 lsrs r2, r0, #16 800b7a2: 0412 lsls r2, r2, #16 800b7a4: 4603 mov r3, r0 800b7a6: b9ca cbnz r2, 800b7dc <__hi0bits+0x3c> 800b7a8: 0403 lsls r3, r0, #16 800b7aa: 2010 movs r0, #16 800b7ac: f013 4f7f tst.w r3, #4278190080 ; 0xff000000 800b7b0: bf04 itt eq 800b7b2: 021b lsleq r3, r3, #8 800b7b4: 3008 addeq r0, #8 800b7b6: f013 4f70 tst.w r3, #4026531840 ; 0xf0000000 800b7ba: bf04 itt eq 800b7bc: 011b lsleq r3, r3, #4 800b7be: 3004 addeq r0, #4 800b7c0: f013 4f40 tst.w r3, #3221225472 ; 0xc0000000 800b7c4: bf04 itt eq 800b7c6: 009b lsleq r3, r3, #2 800b7c8: 3002 addeq r0, #2 800b7ca: 2b00 cmp r3, #0 800b7cc: db05 blt.n 800b7da <__hi0bits+0x3a> 800b7ce: f013 4f80 tst.w r3, #1073741824 ; 0x40000000 800b7d2: f100 0001 add.w r0, r0, #1 800b7d6: bf08 it eq 800b7d8: 2020 moveq r0, #32 800b7da: 4770 bx lr 800b7dc: 2000 movs r0, #0 800b7de: e7e5 b.n 800b7ac <__hi0bits+0xc> 0800b7e0 <__lo0bits>: 800b7e0: 6803 ldr r3, [r0, #0] 800b7e2: 4602 mov r2, r0 800b7e4: f013 0007 ands.w r0, r3, #7 800b7e8: d00b beq.n 800b802 <__lo0bits+0x22> 800b7ea: 07d9 lsls r1, r3, #31 800b7ec: d421 bmi.n 800b832 <__lo0bits+0x52> 800b7ee: 0798 lsls r0, r3, #30 800b7f0: bf49 itett mi 800b7f2: 085b lsrmi r3, r3, #1 800b7f4: 089b lsrpl r3, r3, #2 800b7f6: 2001 movmi r0, #1 800b7f8: 6013 strmi r3, [r2, #0] 800b7fa: bf5c itt pl 800b7fc: 2002 movpl r0, #2 800b7fe: 6013 strpl r3, [r2, #0] 800b800: 4770 bx lr 800b802: b299 uxth r1, r3 800b804: b909 cbnz r1, 800b80a <__lo0bits+0x2a> 800b806: 2010 movs r0, #16 800b808: 0c1b lsrs r3, r3, #16 800b80a: b2d9 uxtb r1, r3 800b80c: b909 cbnz r1, 800b812 <__lo0bits+0x32> 800b80e: 3008 adds r0, #8 800b810: 0a1b lsrs r3, r3, #8 800b812: 0719 lsls r1, r3, #28 800b814: bf04 itt eq 800b816: 091b lsreq r3, r3, #4 800b818: 3004 addeq r0, #4 800b81a: 0799 lsls r1, r3, #30 800b81c: bf04 itt eq 800b81e: 089b lsreq r3, r3, #2 800b820: 3002 addeq r0, #2 800b822: 07d9 lsls r1, r3, #31 800b824: d403 bmi.n 800b82e <__lo0bits+0x4e> 800b826: 085b lsrs r3, r3, #1 800b828: f100 0001 add.w r0, r0, #1 800b82c: d003 beq.n 800b836 <__lo0bits+0x56> 800b82e: 6013 str r3, [r2, #0] 800b830: 4770 bx lr 800b832: 2000 movs r0, #0 800b834: 4770 bx lr 800b836: 2020 movs r0, #32 800b838: 4770 bx lr ... 0800b83c <__i2b>: 800b83c: b510 push {r4, lr} 800b83e: 460c mov r4, r1 800b840: 2101 movs r1, #1 800b842: f7ff ff05 bl 800b650 <_Balloc> 800b846: 4602 mov r2, r0 800b848: b928 cbnz r0, 800b856 <__i2b+0x1a> 800b84a: f44f 71a0 mov.w r1, #320 ; 0x140 800b84e: 4b04 ldr r3, [pc, #16] ; (800b860 <__i2b+0x24>) 800b850: 4804 ldr r0, [pc, #16] ; (800b864 <__i2b+0x28>) 800b852: f7fe fdcf bl 800a3f4 <__assert_func> 800b856: 2301 movs r3, #1 800b858: 6144 str r4, [r0, #20] 800b85a: 6103 str r3, [r0, #16] 800b85c: bd10 pop {r4, pc} 800b85e: bf00 nop 800b860: 0800d4f2 .word 0x0800d4f2 800b864: 0800d564 .word 0x0800d564 0800b868 <__multiply>: 800b868: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800b86c: 4691 mov r9, r2 800b86e: 690a ldr r2, [r1, #16] 800b870: f8d9 3010 ldr.w r3, [r9, #16] 800b874: 460c mov r4, r1 800b876: 429a cmp r2, r3 800b878: bfbe ittt lt 800b87a: 460b movlt r3, r1 800b87c: 464c movlt r4, r9 800b87e: 4699 movlt r9, r3 800b880: 6927 ldr r7, [r4, #16] 800b882: f8d9 a010 ldr.w sl, [r9, #16] 800b886: 68a3 ldr r3, [r4, #8] 800b888: 6861 ldr r1, [r4, #4] 800b88a: eb07 060a add.w r6, r7, sl 800b88e: 42b3 cmp r3, r6 800b890: b085 sub sp, #20 800b892: bfb8 it lt 800b894: 3101 addlt r1, #1 800b896: f7ff fedb bl 800b650 <_Balloc> 800b89a: b930 cbnz r0, 800b8aa <__multiply+0x42> 800b89c: 4602 mov r2, r0 800b89e: f240 115d movw r1, #349 ; 0x15d 800b8a2: 4b43 ldr r3, [pc, #268] ; (800b9b0 <__multiply+0x148>) 800b8a4: 4843 ldr r0, [pc, #268] ; (800b9b4 <__multiply+0x14c>) 800b8a6: f7fe fda5 bl 800a3f4 <__assert_func> 800b8aa: f100 0514 add.w r5, r0, #20 800b8ae: 462b mov r3, r5 800b8b0: 2200 movs r2, #0 800b8b2: eb05 0886 add.w r8, r5, r6, lsl #2 800b8b6: 4543 cmp r3, r8 800b8b8: d321 bcc.n 800b8fe <__multiply+0x96> 800b8ba: f104 0314 add.w r3, r4, #20 800b8be: eb03 0787 add.w r7, r3, r7, lsl #2 800b8c2: f109 0314 add.w r3, r9, #20 800b8c6: eb03 028a add.w r2, r3, sl, lsl #2 800b8ca: 9202 str r2, [sp, #8] 800b8cc: 1b3a subs r2, r7, r4 800b8ce: 3a15 subs r2, #21 800b8d0: f022 0203 bic.w r2, r2, #3 800b8d4: 3204 adds r2, #4 800b8d6: f104 0115 add.w r1, r4, #21 800b8da: 428f cmp r7, r1 800b8dc: bf38 it cc 800b8de: 2204 movcc r2, #4 800b8e0: 9201 str r2, [sp, #4] 800b8e2: 9a02 ldr r2, [sp, #8] 800b8e4: 9303 str r3, [sp, #12] 800b8e6: 429a cmp r2, r3 800b8e8: d80c bhi.n 800b904 <__multiply+0x9c> 800b8ea: 2e00 cmp r6, #0 800b8ec: dd03 ble.n 800b8f6 <__multiply+0x8e> 800b8ee: f858 3d04 ldr.w r3, [r8, #-4]! 800b8f2: 2b00 cmp r3, #0 800b8f4: d059 beq.n 800b9aa <__multiply+0x142> 800b8f6: 6106 str r6, [r0, #16] 800b8f8: b005 add sp, #20 800b8fa: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800b8fe: f843 2b04 str.w r2, [r3], #4 800b902: e7d8 b.n 800b8b6 <__multiply+0x4e> 800b904: f8b3 a000 ldrh.w sl, [r3] 800b908: f1ba 0f00 cmp.w sl, #0 800b90c: d023 beq.n 800b956 <__multiply+0xee> 800b90e: 46a9 mov r9, r5 800b910: f04f 0c00 mov.w ip, #0 800b914: f104 0e14 add.w lr, r4, #20 800b918: f85e 2b04 ldr.w r2, [lr], #4 800b91c: f8d9 1000 ldr.w r1, [r9] 800b920: fa1f fb82 uxth.w fp, r2 800b924: b289 uxth r1, r1 800b926: fb0a 110b mla r1, sl, fp, r1 800b92a: 4461 add r1, ip 800b92c: f8d9 c000 ldr.w ip, [r9] 800b930: 0c12 lsrs r2, r2, #16 800b932: ea4f 4c1c mov.w ip, ip, lsr #16 800b936: fb0a c202 mla r2, sl, r2, ip 800b93a: eb02 4211 add.w r2, r2, r1, lsr #16 800b93e: b289 uxth r1, r1 800b940: ea41 4102 orr.w r1, r1, r2, lsl #16 800b944: 4577 cmp r7, lr 800b946: ea4f 4c12 mov.w ip, r2, lsr #16 800b94a: f849 1b04 str.w r1, [r9], #4 800b94e: d8e3 bhi.n 800b918 <__multiply+0xb0> 800b950: 9a01 ldr r2, [sp, #4] 800b952: f845 c002 str.w ip, [r5, r2] 800b956: 9a03 ldr r2, [sp, #12] 800b958: 3304 adds r3, #4 800b95a: f8b2 9002 ldrh.w r9, [r2, #2] 800b95e: f1b9 0f00 cmp.w r9, #0 800b962: d020 beq.n 800b9a6 <__multiply+0x13e> 800b964: 46ae mov lr, r5 800b966: f04f 0a00 mov.w sl, #0 800b96a: 6829 ldr r1, [r5, #0] 800b96c: f104 0c14 add.w ip, r4, #20 800b970: f8bc b000 ldrh.w fp, [ip] 800b974: f8be 2002 ldrh.w r2, [lr, #2] 800b978: b289 uxth r1, r1 800b97a: fb09 220b mla r2, r9, fp, r2 800b97e: 4492 add sl, r2 800b980: ea41 410a orr.w r1, r1, sl, lsl #16 800b984: f84e 1b04 str.w r1, [lr], #4 800b988: f85c 2b04 ldr.w r2, [ip], #4 800b98c: f8be 1000 ldrh.w r1, [lr] 800b990: 0c12 lsrs r2, r2, #16 800b992: fb09 1102 mla r1, r9, r2, r1 800b996: 4567 cmp r7, ip 800b998: eb01 411a add.w r1, r1, sl, lsr #16 800b99c: ea4f 4a11 mov.w sl, r1, lsr #16 800b9a0: d8e6 bhi.n 800b970 <__multiply+0x108> 800b9a2: 9a01 ldr r2, [sp, #4] 800b9a4: 50a9 str r1, [r5, r2] 800b9a6: 3504 adds r5, #4 800b9a8: e79b b.n 800b8e2 <__multiply+0x7a> 800b9aa: 3e01 subs r6, #1 800b9ac: e79d b.n 800b8ea <__multiply+0x82> 800b9ae: bf00 nop 800b9b0: 0800d4f2 .word 0x0800d4f2 800b9b4: 0800d564 .word 0x0800d564 0800b9b8 <__pow5mult>: 800b9b8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 800b9bc: 4615 mov r5, r2 800b9be: f012 0203 ands.w r2, r2, #3 800b9c2: 4606 mov r6, r0 800b9c4: 460f mov r7, r1 800b9c6: d007 beq.n 800b9d8 <__pow5mult+0x20> 800b9c8: 4c25 ldr r4, [pc, #148] ; (800ba60 <__pow5mult+0xa8>) 800b9ca: 3a01 subs r2, #1 800b9cc: 2300 movs r3, #0 800b9ce: f854 2022 ldr.w r2, [r4, r2, lsl #2] 800b9d2: f7ff fe9f bl 800b714 <__multadd> 800b9d6: 4607 mov r7, r0 800b9d8: 10ad asrs r5, r5, #2 800b9da: d03d beq.n 800ba58 <__pow5mult+0xa0> 800b9dc: 6a74 ldr r4, [r6, #36] ; 0x24 800b9de: b97c cbnz r4, 800ba00 <__pow5mult+0x48> 800b9e0: 2010 movs r0, #16 800b9e2: f7fd fbf5 bl 80091d0 800b9e6: 4602 mov r2, r0 800b9e8: 6270 str r0, [r6, #36] ; 0x24 800b9ea: b928 cbnz r0, 800b9f8 <__pow5mult+0x40> 800b9ec: f44f 71d7 mov.w r1, #430 ; 0x1ae 800b9f0: 4b1c ldr r3, [pc, #112] ; (800ba64 <__pow5mult+0xac>) 800b9f2: 481d ldr r0, [pc, #116] ; (800ba68 <__pow5mult+0xb0>) 800b9f4: f7fe fcfe bl 800a3f4 <__assert_func> 800b9f8: e9c0 4401 strd r4, r4, [r0, #4] 800b9fc: 6004 str r4, [r0, #0] 800b9fe: 60c4 str r4, [r0, #12] 800ba00: f8d6 8024 ldr.w r8, [r6, #36] ; 0x24 800ba04: f8d8 4008 ldr.w r4, [r8, #8] 800ba08: b94c cbnz r4, 800ba1e <__pow5mult+0x66> 800ba0a: f240 2171 movw r1, #625 ; 0x271 800ba0e: 4630 mov r0, r6 800ba10: f7ff ff14 bl 800b83c <__i2b> 800ba14: 2300 movs r3, #0 800ba16: 4604 mov r4, r0 800ba18: f8c8 0008 str.w r0, [r8, #8] 800ba1c: 6003 str r3, [r0, #0] 800ba1e: f04f 0900 mov.w r9, #0 800ba22: 07eb lsls r3, r5, #31 800ba24: d50a bpl.n 800ba3c <__pow5mult+0x84> 800ba26: 4639 mov r1, r7 800ba28: 4622 mov r2, r4 800ba2a: 4630 mov r0, r6 800ba2c: f7ff ff1c bl 800b868 <__multiply> 800ba30: 4680 mov r8, r0 800ba32: 4639 mov r1, r7 800ba34: 4630 mov r0, r6 800ba36: f7ff fe4b bl 800b6d0 <_Bfree> 800ba3a: 4647 mov r7, r8 800ba3c: 106d asrs r5, r5, #1 800ba3e: d00b beq.n 800ba58 <__pow5mult+0xa0> 800ba40: 6820 ldr r0, [r4, #0] 800ba42: b938 cbnz r0, 800ba54 <__pow5mult+0x9c> 800ba44: 4622 mov r2, r4 800ba46: 4621 mov r1, r4 800ba48: 4630 mov r0, r6 800ba4a: f7ff ff0d bl 800b868 <__multiply> 800ba4e: 6020 str r0, [r4, #0] 800ba50: f8c0 9000 str.w r9, [r0] 800ba54: 4604 mov r4, r0 800ba56: e7e4 b.n 800ba22 <__pow5mult+0x6a> 800ba58: 4638 mov r0, r7 800ba5a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 800ba5e: bf00 nop 800ba60: 0800d6b0 .word 0x0800d6b0 800ba64: 0800d2ac .word 0x0800d2ac 800ba68: 0800d564 .word 0x0800d564 0800ba6c <__lshift>: 800ba6c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800ba70: 460c mov r4, r1 800ba72: 4607 mov r7, r0 800ba74: 4691 mov r9, r2 800ba76: 6923 ldr r3, [r4, #16] 800ba78: 6849 ldr r1, [r1, #4] 800ba7a: eb03 1862 add.w r8, r3, r2, asr #5 800ba7e: 68a3 ldr r3, [r4, #8] 800ba80: ea4f 1a62 mov.w sl, r2, asr #5 800ba84: f108 0601 add.w r6, r8, #1 800ba88: 42b3 cmp r3, r6 800ba8a: db0b blt.n 800baa4 <__lshift+0x38> 800ba8c: 4638 mov r0, r7 800ba8e: f7ff fddf bl 800b650 <_Balloc> 800ba92: 4605 mov r5, r0 800ba94: b948 cbnz r0, 800baaa <__lshift+0x3e> 800ba96: 4602 mov r2, r0 800ba98: f240 11d9 movw r1, #473 ; 0x1d9 800ba9c: 4b29 ldr r3, [pc, #164] ; (800bb44 <__lshift+0xd8>) 800ba9e: 482a ldr r0, [pc, #168] ; (800bb48 <__lshift+0xdc>) 800baa0: f7fe fca8 bl 800a3f4 <__assert_func> 800baa4: 3101 adds r1, #1 800baa6: 005b lsls r3, r3, #1 800baa8: e7ee b.n 800ba88 <__lshift+0x1c> 800baaa: 2300 movs r3, #0 800baac: f100 0114 add.w r1, r0, #20 800bab0: f100 0210 add.w r2, r0, #16 800bab4: 4618 mov r0, r3 800bab6: 4553 cmp r3, sl 800bab8: db37 blt.n 800bb2a <__lshift+0xbe> 800baba: 6920 ldr r0, [r4, #16] 800babc: ea2a 7aea bic.w sl, sl, sl, asr #31 800bac0: f104 0314 add.w r3, r4, #20 800bac4: f019 091f ands.w r9, r9, #31 800bac8: eb01 018a add.w r1, r1, sl, lsl #2 800bacc: eb03 0080 add.w r0, r3, r0, lsl #2 800bad0: d02f beq.n 800bb32 <__lshift+0xc6> 800bad2: 468a mov sl, r1 800bad4: f04f 0c00 mov.w ip, #0 800bad8: f1c9 0e20 rsb lr, r9, #32 800badc: 681a ldr r2, [r3, #0] 800bade: fa02 f209 lsl.w r2, r2, r9 800bae2: ea42 020c orr.w r2, r2, ip 800bae6: f84a 2b04 str.w r2, [sl], #4 800baea: f853 2b04 ldr.w r2, [r3], #4 800baee: 4298 cmp r0, r3 800baf0: fa22 fc0e lsr.w ip, r2, lr 800baf4: d8f2 bhi.n 800badc <__lshift+0x70> 800baf6: 1b03 subs r3, r0, r4 800baf8: 3b15 subs r3, #21 800bafa: f023 0303 bic.w r3, r3, #3 800bafe: 3304 adds r3, #4 800bb00: f104 0215 add.w r2, r4, #21 800bb04: 4290 cmp r0, r2 800bb06: bf38 it cc 800bb08: 2304 movcc r3, #4 800bb0a: f841 c003 str.w ip, [r1, r3] 800bb0e: f1bc 0f00 cmp.w ip, #0 800bb12: d001 beq.n 800bb18 <__lshift+0xac> 800bb14: f108 0602 add.w r6, r8, #2 800bb18: 3e01 subs r6, #1 800bb1a: 4638 mov r0, r7 800bb1c: 4621 mov r1, r4 800bb1e: 612e str r6, [r5, #16] 800bb20: f7ff fdd6 bl 800b6d0 <_Bfree> 800bb24: 4628 mov r0, r5 800bb26: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800bb2a: f842 0f04 str.w r0, [r2, #4]! 800bb2e: 3301 adds r3, #1 800bb30: e7c1 b.n 800bab6 <__lshift+0x4a> 800bb32: 3904 subs r1, #4 800bb34: f853 2b04 ldr.w r2, [r3], #4 800bb38: 4298 cmp r0, r3 800bb3a: f841 2f04 str.w r2, [r1, #4]! 800bb3e: d8f9 bhi.n 800bb34 <__lshift+0xc8> 800bb40: e7ea b.n 800bb18 <__lshift+0xac> 800bb42: bf00 nop 800bb44: 0800d4f2 .word 0x0800d4f2 800bb48: 0800d564 .word 0x0800d564 0800bb4c <__mcmp>: 800bb4c: 4603 mov r3, r0 800bb4e: 690a ldr r2, [r1, #16] 800bb50: 6900 ldr r0, [r0, #16] 800bb52: b530 push {r4, r5, lr} 800bb54: 1a80 subs r0, r0, r2 800bb56: d10d bne.n 800bb74 <__mcmp+0x28> 800bb58: 3314 adds r3, #20 800bb5a: 3114 adds r1, #20 800bb5c: eb03 0482 add.w r4, r3, r2, lsl #2 800bb60: eb01 0182 add.w r1, r1, r2, lsl #2 800bb64: f854 5d04 ldr.w r5, [r4, #-4]! 800bb68: f851 2d04 ldr.w r2, [r1, #-4]! 800bb6c: 4295 cmp r5, r2 800bb6e: d002 beq.n 800bb76 <__mcmp+0x2a> 800bb70: d304 bcc.n 800bb7c <__mcmp+0x30> 800bb72: 2001 movs r0, #1 800bb74: bd30 pop {r4, r5, pc} 800bb76: 42a3 cmp r3, r4 800bb78: d3f4 bcc.n 800bb64 <__mcmp+0x18> 800bb7a: e7fb b.n 800bb74 <__mcmp+0x28> 800bb7c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800bb80: e7f8 b.n 800bb74 <__mcmp+0x28> ... 0800bb84 <__mdiff>: 800bb84: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} 800bb88: 460d mov r5, r1 800bb8a: 4607 mov r7, r0 800bb8c: 4611 mov r1, r2 800bb8e: 4628 mov r0, r5 800bb90: 4614 mov r4, r2 800bb92: f7ff ffdb bl 800bb4c <__mcmp> 800bb96: 1e06 subs r6, r0, #0 800bb98: d111 bne.n 800bbbe <__mdiff+0x3a> 800bb9a: 4631 mov r1, r6 800bb9c: 4638 mov r0, r7 800bb9e: f7ff fd57 bl 800b650 <_Balloc> 800bba2: 4602 mov r2, r0 800bba4: b928 cbnz r0, 800bbb2 <__mdiff+0x2e> 800bba6: f240 2132 movw r1, #562 ; 0x232 800bbaa: 4b3a ldr r3, [pc, #232] ; (800bc94 <__mdiff+0x110>) 800bbac: 483a ldr r0, [pc, #232] ; (800bc98 <__mdiff+0x114>) 800bbae: f7fe fc21 bl 800a3f4 <__assert_func> 800bbb2: 2301 movs r3, #1 800bbb4: e9c0 3604 strd r3, r6, [r0, #16] 800bbb8: 4610 mov r0, r2 800bbba: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} 800bbbe: bfa4 itt ge 800bbc0: 4623 movge r3, r4 800bbc2: 462c movge r4, r5 800bbc4: 4638 mov r0, r7 800bbc6: 6861 ldr r1, [r4, #4] 800bbc8: bfa6 itte ge 800bbca: 461d movge r5, r3 800bbcc: 2600 movge r6, #0 800bbce: 2601 movlt r6, #1 800bbd0: f7ff fd3e bl 800b650 <_Balloc> 800bbd4: 4602 mov r2, r0 800bbd6: b918 cbnz r0, 800bbe0 <__mdiff+0x5c> 800bbd8: f44f 7110 mov.w r1, #576 ; 0x240 800bbdc: 4b2d ldr r3, [pc, #180] ; (800bc94 <__mdiff+0x110>) 800bbde: e7e5 b.n 800bbac <__mdiff+0x28> 800bbe0: f102 0814 add.w r8, r2, #20 800bbe4: 46c2 mov sl, r8 800bbe6: f04f 0c00 mov.w ip, #0 800bbea: 6927 ldr r7, [r4, #16] 800bbec: 60c6 str r6, [r0, #12] 800bbee: 692e ldr r6, [r5, #16] 800bbf0: f104 0014 add.w r0, r4, #20 800bbf4: f105 0914 add.w r9, r5, #20 800bbf8: eb00 0e87 add.w lr, r0, r7, lsl #2 800bbfc: eb09 0686 add.w r6, r9, r6, lsl #2 800bc00: 3410 adds r4, #16 800bc02: f854 bf04 ldr.w fp, [r4, #4]! 800bc06: f859 3b04 ldr.w r3, [r9], #4 800bc0a: fa1f f18b uxth.w r1, fp 800bc0e: 448c add ip, r1 800bc10: b299 uxth r1, r3 800bc12: 0c1b lsrs r3, r3, #16 800bc14: ebac 0101 sub.w r1, ip, r1 800bc18: ebc3 431b rsb r3, r3, fp, lsr #16 800bc1c: eb03 4321 add.w r3, r3, r1, asr #16 800bc20: b289 uxth r1, r1 800bc22: ea4f 4c23 mov.w ip, r3, asr #16 800bc26: 454e cmp r6, r9 800bc28: ea41 4303 orr.w r3, r1, r3, lsl #16 800bc2c: f84a 3b04 str.w r3, [sl], #4 800bc30: d8e7 bhi.n 800bc02 <__mdiff+0x7e> 800bc32: 1b73 subs r3, r6, r5 800bc34: 3b15 subs r3, #21 800bc36: f023 0303 bic.w r3, r3, #3 800bc3a: 3515 adds r5, #21 800bc3c: 3304 adds r3, #4 800bc3e: 42ae cmp r6, r5 800bc40: bf38 it cc 800bc42: 2304 movcc r3, #4 800bc44: 4418 add r0, r3 800bc46: 4443 add r3, r8 800bc48: 461e mov r6, r3 800bc4a: 4605 mov r5, r0 800bc4c: 4575 cmp r5, lr 800bc4e: d30e bcc.n 800bc6e <__mdiff+0xea> 800bc50: f10e 0103 add.w r1, lr, #3 800bc54: 1a09 subs r1, r1, r0 800bc56: f021 0103 bic.w r1, r1, #3 800bc5a: 3803 subs r0, #3 800bc5c: 4586 cmp lr, r0 800bc5e: bf38 it cc 800bc60: 2100 movcc r1, #0 800bc62: 4419 add r1, r3 800bc64: f851 3d04 ldr.w r3, [r1, #-4]! 800bc68: b18b cbz r3, 800bc8e <__mdiff+0x10a> 800bc6a: 6117 str r7, [r2, #16] 800bc6c: e7a4 b.n 800bbb8 <__mdiff+0x34> 800bc6e: f855 8b04 ldr.w r8, [r5], #4 800bc72: fa1f f188 uxth.w r1, r8 800bc76: 4461 add r1, ip 800bc78: 140c asrs r4, r1, #16 800bc7a: eb04 4418 add.w r4, r4, r8, lsr #16 800bc7e: b289 uxth r1, r1 800bc80: ea41 4104 orr.w r1, r1, r4, lsl #16 800bc84: ea4f 4c24 mov.w ip, r4, asr #16 800bc88: f846 1b04 str.w r1, [r6], #4 800bc8c: e7de b.n 800bc4c <__mdiff+0xc8> 800bc8e: 3f01 subs r7, #1 800bc90: e7e8 b.n 800bc64 <__mdiff+0xe0> 800bc92: bf00 nop 800bc94: 0800d4f2 .word 0x0800d4f2 800bc98: 0800d564 .word 0x0800d564 0800bc9c <__d2b>: 800bc9c: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} 800bca0: 2101 movs r1, #1 800bca2: e9dd 7608 ldrd r7, r6, [sp, #32] 800bca6: 4690 mov r8, r2 800bca8: 461d mov r5, r3 800bcaa: f7ff fcd1 bl 800b650 <_Balloc> 800bcae: 4604 mov r4, r0 800bcb0: b930 cbnz r0, 800bcc0 <__d2b+0x24> 800bcb2: 4602 mov r2, r0 800bcb4: f240 310a movw r1, #778 ; 0x30a 800bcb8: 4b24 ldr r3, [pc, #144] ; (800bd4c <__d2b+0xb0>) 800bcba: 4825 ldr r0, [pc, #148] ; (800bd50 <__d2b+0xb4>) 800bcbc: f7fe fb9a bl 800a3f4 <__assert_func> 800bcc0: f3c5 0313 ubfx r3, r5, #0, #20 800bcc4: f3c5 550a ubfx r5, r5, #20, #11 800bcc8: bb2d cbnz r5, 800bd16 <__d2b+0x7a> 800bcca: 9301 str r3, [sp, #4] 800bccc: f1b8 0300 subs.w r3, r8, #0 800bcd0: d026 beq.n 800bd20 <__d2b+0x84> 800bcd2: 4668 mov r0, sp 800bcd4: 9300 str r3, [sp, #0] 800bcd6: f7ff fd83 bl 800b7e0 <__lo0bits> 800bcda: 9900 ldr r1, [sp, #0] 800bcdc: b1f0 cbz r0, 800bd1c <__d2b+0x80> 800bcde: 9a01 ldr r2, [sp, #4] 800bce0: f1c0 0320 rsb r3, r0, #32 800bce4: fa02 f303 lsl.w r3, r2, r3 800bce8: 430b orrs r3, r1 800bcea: 40c2 lsrs r2, r0 800bcec: 6163 str r3, [r4, #20] 800bcee: 9201 str r2, [sp, #4] 800bcf0: 9b01 ldr r3, [sp, #4] 800bcf2: 2b00 cmp r3, #0 800bcf4: bf14 ite ne 800bcf6: 2102 movne r1, #2 800bcf8: 2101 moveq r1, #1 800bcfa: 61a3 str r3, [r4, #24] 800bcfc: 6121 str r1, [r4, #16] 800bcfe: b1c5 cbz r5, 800bd32 <__d2b+0x96> 800bd00: f2a5 4533 subw r5, r5, #1075 ; 0x433 800bd04: 4405 add r5, r0 800bd06: f1c0 0035 rsb r0, r0, #53 ; 0x35 800bd0a: 603d str r5, [r7, #0] 800bd0c: 6030 str r0, [r6, #0] 800bd0e: 4620 mov r0, r4 800bd10: b002 add sp, #8 800bd12: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800bd16: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 800bd1a: e7d6 b.n 800bcca <__d2b+0x2e> 800bd1c: 6161 str r1, [r4, #20] 800bd1e: e7e7 b.n 800bcf0 <__d2b+0x54> 800bd20: a801 add r0, sp, #4 800bd22: f7ff fd5d bl 800b7e0 <__lo0bits> 800bd26: 2101 movs r1, #1 800bd28: 9b01 ldr r3, [sp, #4] 800bd2a: 6121 str r1, [r4, #16] 800bd2c: 6163 str r3, [r4, #20] 800bd2e: 3020 adds r0, #32 800bd30: e7e5 b.n 800bcfe <__d2b+0x62> 800bd32: eb04 0381 add.w r3, r4, r1, lsl #2 800bd36: f2a0 4032 subw r0, r0, #1074 ; 0x432 800bd3a: 6038 str r0, [r7, #0] 800bd3c: 6918 ldr r0, [r3, #16] 800bd3e: f7ff fd2f bl 800b7a0 <__hi0bits> 800bd42: ebc0 1141 rsb r1, r0, r1, lsl #5 800bd46: 6031 str r1, [r6, #0] 800bd48: e7e1 b.n 800bd0e <__d2b+0x72> 800bd4a: bf00 nop 800bd4c: 0800d4f2 .word 0x0800d4f2 800bd50: 0800d564 .word 0x0800d564 0800bd54 <_calloc_r>: 800bd54: b570 push {r4, r5, r6, lr} 800bd56: fba1 5402 umull r5, r4, r1, r2 800bd5a: b934 cbnz r4, 800bd6a <_calloc_r+0x16> 800bd5c: 4629 mov r1, r5 800bd5e: f7fd fac5 bl 80092ec <_malloc_r> 800bd62: 4606 mov r6, r0 800bd64: b928 cbnz r0, 800bd72 <_calloc_r+0x1e> 800bd66: 4630 mov r0, r6 800bd68: bd70 pop {r4, r5, r6, pc} 800bd6a: 220c movs r2, #12 800bd6c: 2600 movs r6, #0 800bd6e: 6002 str r2, [r0, #0] 800bd70: e7f9 b.n 800bd66 <_calloc_r+0x12> 800bd72: 462a mov r2, r5 800bd74: 4621 mov r1, r4 800bd76: f7fd fa49 bl 800920c 800bd7a: e7f4 b.n 800bd66 <_calloc_r+0x12> 0800bd7c <__sfputc_r>: 800bd7c: 6893 ldr r3, [r2, #8] 800bd7e: b410 push {r4} 800bd80: 3b01 subs r3, #1 800bd82: 2b00 cmp r3, #0 800bd84: 6093 str r3, [r2, #8] 800bd86: da07 bge.n 800bd98 <__sfputc_r+0x1c> 800bd88: 6994 ldr r4, [r2, #24] 800bd8a: 42a3 cmp r3, r4 800bd8c: db01 blt.n 800bd92 <__sfputc_r+0x16> 800bd8e: 290a cmp r1, #10 800bd90: d102 bne.n 800bd98 <__sfputc_r+0x1c> 800bd92: bc10 pop {r4} 800bd94: f7fe ba6e b.w 800a274 <__swbuf_r> 800bd98: 6813 ldr r3, [r2, #0] 800bd9a: 1c58 adds r0, r3, #1 800bd9c: 6010 str r0, [r2, #0] 800bd9e: 7019 strb r1, [r3, #0] 800bda0: 4608 mov r0, r1 800bda2: bc10 pop {r4} 800bda4: 4770 bx lr 0800bda6 <__sfputs_r>: 800bda6: b5f8 push {r3, r4, r5, r6, r7, lr} 800bda8: 4606 mov r6, r0 800bdaa: 460f mov r7, r1 800bdac: 4614 mov r4, r2 800bdae: 18d5 adds r5, r2, r3 800bdb0: 42ac cmp r4, r5 800bdb2: d101 bne.n 800bdb8 <__sfputs_r+0x12> 800bdb4: 2000 movs r0, #0 800bdb6: e007 b.n 800bdc8 <__sfputs_r+0x22> 800bdb8: 463a mov r2, r7 800bdba: 4630 mov r0, r6 800bdbc: f814 1b01 ldrb.w r1, [r4], #1 800bdc0: f7ff ffdc bl 800bd7c <__sfputc_r> 800bdc4: 1c43 adds r3, r0, #1 800bdc6: d1f3 bne.n 800bdb0 <__sfputs_r+0xa> 800bdc8: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 0800bdcc <_vfiprintf_r>: 800bdcc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800bdd0: 460d mov r5, r1 800bdd2: 4614 mov r4, r2 800bdd4: 4698 mov r8, r3 800bdd6: 4606 mov r6, r0 800bdd8: b09d sub sp, #116 ; 0x74 800bdda: b118 cbz r0, 800bde4 <_vfiprintf_r+0x18> 800bddc: 6983 ldr r3, [r0, #24] 800bdde: b90b cbnz r3, 800bde4 <_vfiprintf_r+0x18> 800bde0: f7ff fab6 bl 800b350 <__sinit> 800bde4: 4b89 ldr r3, [pc, #548] ; (800c00c <_vfiprintf_r+0x240>) 800bde6: 429d cmp r5, r3 800bde8: d11b bne.n 800be22 <_vfiprintf_r+0x56> 800bdea: 6875 ldr r5, [r6, #4] 800bdec: 6e6b ldr r3, [r5, #100] ; 0x64 800bdee: 07d9 lsls r1, r3, #31 800bdf0: d405 bmi.n 800bdfe <_vfiprintf_r+0x32> 800bdf2: 89ab ldrh r3, [r5, #12] 800bdf4: 059a lsls r2, r3, #22 800bdf6: d402 bmi.n 800bdfe <_vfiprintf_r+0x32> 800bdf8: 6da8 ldr r0, [r5, #88] ; 0x58 800bdfa: f7ff fba7 bl 800b54c <__retarget_lock_acquire_recursive> 800bdfe: 89ab ldrh r3, [r5, #12] 800be00: 071b lsls r3, r3, #28 800be02: d501 bpl.n 800be08 <_vfiprintf_r+0x3c> 800be04: 692b ldr r3, [r5, #16] 800be06: b9eb cbnz r3, 800be44 <_vfiprintf_r+0x78> 800be08: 4629 mov r1, r5 800be0a: 4630 mov r0, r6 800be0c: f7fe fa84 bl 800a318 <__swsetup_r> 800be10: b1c0 cbz r0, 800be44 <_vfiprintf_r+0x78> 800be12: 6e6b ldr r3, [r5, #100] ; 0x64 800be14: 07dc lsls r4, r3, #31 800be16: d50e bpl.n 800be36 <_vfiprintf_r+0x6a> 800be18: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800be1c: b01d add sp, #116 ; 0x74 800be1e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800be22: 4b7b ldr r3, [pc, #492] ; (800c010 <_vfiprintf_r+0x244>) 800be24: 429d cmp r5, r3 800be26: d101 bne.n 800be2c <_vfiprintf_r+0x60> 800be28: 68b5 ldr r5, [r6, #8] 800be2a: e7df b.n 800bdec <_vfiprintf_r+0x20> 800be2c: 4b79 ldr r3, [pc, #484] ; (800c014 <_vfiprintf_r+0x248>) 800be2e: 429d cmp r5, r3 800be30: bf08 it eq 800be32: 68f5 ldreq r5, [r6, #12] 800be34: e7da b.n 800bdec <_vfiprintf_r+0x20> 800be36: 89ab ldrh r3, [r5, #12] 800be38: 0598 lsls r0, r3, #22 800be3a: d4ed bmi.n 800be18 <_vfiprintf_r+0x4c> 800be3c: 6da8 ldr r0, [r5, #88] ; 0x58 800be3e: f7ff fb87 bl 800b550 <__retarget_lock_release_recursive> 800be42: e7e9 b.n 800be18 <_vfiprintf_r+0x4c> 800be44: 2300 movs r3, #0 800be46: 9309 str r3, [sp, #36] ; 0x24 800be48: 2320 movs r3, #32 800be4a: f88d 3029 strb.w r3, [sp, #41] ; 0x29 800be4e: 2330 movs r3, #48 ; 0x30 800be50: f04f 0901 mov.w r9, #1 800be54: f8cd 800c str.w r8, [sp, #12] 800be58: f8df 81bc ldr.w r8, [pc, #444] ; 800c018 <_vfiprintf_r+0x24c> 800be5c: f88d 302a strb.w r3, [sp, #42] ; 0x2a 800be60: 4623 mov r3, r4 800be62: 469a mov sl, r3 800be64: f813 2b01 ldrb.w r2, [r3], #1 800be68: b10a cbz r2, 800be6e <_vfiprintf_r+0xa2> 800be6a: 2a25 cmp r2, #37 ; 0x25 800be6c: d1f9 bne.n 800be62 <_vfiprintf_r+0x96> 800be6e: ebba 0b04 subs.w fp, sl, r4 800be72: d00b beq.n 800be8c <_vfiprintf_r+0xc0> 800be74: 465b mov r3, fp 800be76: 4622 mov r2, r4 800be78: 4629 mov r1, r5 800be7a: 4630 mov r0, r6 800be7c: f7ff ff93 bl 800bda6 <__sfputs_r> 800be80: 3001 adds r0, #1 800be82: f000 80aa beq.w 800bfda <_vfiprintf_r+0x20e> 800be86: 9a09 ldr r2, [sp, #36] ; 0x24 800be88: 445a add r2, fp 800be8a: 9209 str r2, [sp, #36] ; 0x24 800be8c: f89a 3000 ldrb.w r3, [sl] 800be90: 2b00 cmp r3, #0 800be92: f000 80a2 beq.w 800bfda <_vfiprintf_r+0x20e> 800be96: 2300 movs r3, #0 800be98: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 800be9c: e9cd 2305 strd r2, r3, [sp, #20] 800bea0: f10a 0a01 add.w sl, sl, #1 800bea4: 9304 str r3, [sp, #16] 800bea6: 9307 str r3, [sp, #28] 800bea8: f88d 3053 strb.w r3, [sp, #83] ; 0x53 800beac: 931a str r3, [sp, #104] ; 0x68 800beae: 4654 mov r4, sl 800beb0: 2205 movs r2, #5 800beb2: f814 1b01 ldrb.w r1, [r4], #1 800beb6: 4858 ldr r0, [pc, #352] ; (800c018 <_vfiprintf_r+0x24c>) 800beb8: f7ff fbb0 bl 800b61c 800bebc: 9a04 ldr r2, [sp, #16] 800bebe: b9d8 cbnz r0, 800bef8 <_vfiprintf_r+0x12c> 800bec0: 06d1 lsls r1, r2, #27 800bec2: bf44 itt mi 800bec4: 2320 movmi r3, #32 800bec6: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 800beca: 0713 lsls r3, r2, #28 800becc: bf44 itt mi 800bece: 232b movmi r3, #43 ; 0x2b 800bed0: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 800bed4: f89a 3000 ldrb.w r3, [sl] 800bed8: 2b2a cmp r3, #42 ; 0x2a 800beda: d015 beq.n 800bf08 <_vfiprintf_r+0x13c> 800bedc: 4654 mov r4, sl 800bede: 2000 movs r0, #0 800bee0: f04f 0c0a mov.w ip, #10 800bee4: 9a07 ldr r2, [sp, #28] 800bee6: 4621 mov r1, r4 800bee8: f811 3b01 ldrb.w r3, [r1], #1 800beec: 3b30 subs r3, #48 ; 0x30 800beee: 2b09 cmp r3, #9 800bef0: d94e bls.n 800bf90 <_vfiprintf_r+0x1c4> 800bef2: b1b0 cbz r0, 800bf22 <_vfiprintf_r+0x156> 800bef4: 9207 str r2, [sp, #28] 800bef6: e014 b.n 800bf22 <_vfiprintf_r+0x156> 800bef8: eba0 0308 sub.w r3, r0, r8 800befc: fa09 f303 lsl.w r3, r9, r3 800bf00: 4313 orrs r3, r2 800bf02: 46a2 mov sl, r4 800bf04: 9304 str r3, [sp, #16] 800bf06: e7d2 b.n 800beae <_vfiprintf_r+0xe2> 800bf08: 9b03 ldr r3, [sp, #12] 800bf0a: 1d19 adds r1, r3, #4 800bf0c: 681b ldr r3, [r3, #0] 800bf0e: 9103 str r1, [sp, #12] 800bf10: 2b00 cmp r3, #0 800bf12: bfbb ittet lt 800bf14: 425b neglt r3, r3 800bf16: f042 0202 orrlt.w r2, r2, #2 800bf1a: 9307 strge r3, [sp, #28] 800bf1c: 9307 strlt r3, [sp, #28] 800bf1e: bfb8 it lt 800bf20: 9204 strlt r2, [sp, #16] 800bf22: 7823 ldrb r3, [r4, #0] 800bf24: 2b2e cmp r3, #46 ; 0x2e 800bf26: d10c bne.n 800bf42 <_vfiprintf_r+0x176> 800bf28: 7863 ldrb r3, [r4, #1] 800bf2a: 2b2a cmp r3, #42 ; 0x2a 800bf2c: d135 bne.n 800bf9a <_vfiprintf_r+0x1ce> 800bf2e: 9b03 ldr r3, [sp, #12] 800bf30: 3402 adds r4, #2 800bf32: 1d1a adds r2, r3, #4 800bf34: 681b ldr r3, [r3, #0] 800bf36: 9203 str r2, [sp, #12] 800bf38: 2b00 cmp r3, #0 800bf3a: bfb8 it lt 800bf3c: f04f 33ff movlt.w r3, #4294967295 ; 0xffffffff 800bf40: 9305 str r3, [sp, #20] 800bf42: f8df a0d8 ldr.w sl, [pc, #216] ; 800c01c <_vfiprintf_r+0x250> 800bf46: 2203 movs r2, #3 800bf48: 4650 mov r0, sl 800bf4a: 7821 ldrb r1, [r4, #0] 800bf4c: f7ff fb66 bl 800b61c 800bf50: b140 cbz r0, 800bf64 <_vfiprintf_r+0x198> 800bf52: 2340 movs r3, #64 ; 0x40 800bf54: eba0 000a sub.w r0, r0, sl 800bf58: fa03 f000 lsl.w r0, r3, r0 800bf5c: 9b04 ldr r3, [sp, #16] 800bf5e: 3401 adds r4, #1 800bf60: 4303 orrs r3, r0 800bf62: 9304 str r3, [sp, #16] 800bf64: f814 1b01 ldrb.w r1, [r4], #1 800bf68: 2206 movs r2, #6 800bf6a: 482d ldr r0, [pc, #180] ; (800c020 <_vfiprintf_r+0x254>) 800bf6c: f88d 1028 strb.w r1, [sp, #40] ; 0x28 800bf70: f7ff fb54 bl 800b61c 800bf74: 2800 cmp r0, #0 800bf76: d03f beq.n 800bff8 <_vfiprintf_r+0x22c> 800bf78: 4b2a ldr r3, [pc, #168] ; (800c024 <_vfiprintf_r+0x258>) 800bf7a: bb1b cbnz r3, 800bfc4 <_vfiprintf_r+0x1f8> 800bf7c: 9b03 ldr r3, [sp, #12] 800bf7e: 3307 adds r3, #7 800bf80: f023 0307 bic.w r3, r3, #7 800bf84: 3308 adds r3, #8 800bf86: 9303 str r3, [sp, #12] 800bf88: 9b09 ldr r3, [sp, #36] ; 0x24 800bf8a: 443b add r3, r7 800bf8c: 9309 str r3, [sp, #36] ; 0x24 800bf8e: e767 b.n 800be60 <_vfiprintf_r+0x94> 800bf90: 460c mov r4, r1 800bf92: 2001 movs r0, #1 800bf94: fb0c 3202 mla r2, ip, r2, r3 800bf98: e7a5 b.n 800bee6 <_vfiprintf_r+0x11a> 800bf9a: 2300 movs r3, #0 800bf9c: f04f 0c0a mov.w ip, #10 800bfa0: 4619 mov r1, r3 800bfa2: 3401 adds r4, #1 800bfa4: 9305 str r3, [sp, #20] 800bfa6: 4620 mov r0, r4 800bfa8: f810 2b01 ldrb.w r2, [r0], #1 800bfac: 3a30 subs r2, #48 ; 0x30 800bfae: 2a09 cmp r2, #9 800bfb0: d903 bls.n 800bfba <_vfiprintf_r+0x1ee> 800bfb2: 2b00 cmp r3, #0 800bfb4: d0c5 beq.n 800bf42 <_vfiprintf_r+0x176> 800bfb6: 9105 str r1, [sp, #20] 800bfb8: e7c3 b.n 800bf42 <_vfiprintf_r+0x176> 800bfba: 4604 mov r4, r0 800bfbc: 2301 movs r3, #1 800bfbe: fb0c 2101 mla r1, ip, r1, r2 800bfc2: e7f0 b.n 800bfa6 <_vfiprintf_r+0x1da> 800bfc4: ab03 add r3, sp, #12 800bfc6: 9300 str r3, [sp, #0] 800bfc8: 462a mov r2, r5 800bfca: 4630 mov r0, r6 800bfcc: 4b16 ldr r3, [pc, #88] ; (800c028 <_vfiprintf_r+0x25c>) 800bfce: a904 add r1, sp, #16 800bfd0: f7fd fa9e bl 8009510 <_printf_float> 800bfd4: 4607 mov r7, r0 800bfd6: 1c78 adds r0, r7, #1 800bfd8: d1d6 bne.n 800bf88 <_vfiprintf_r+0x1bc> 800bfda: 6e6b ldr r3, [r5, #100] ; 0x64 800bfdc: 07d9 lsls r1, r3, #31 800bfde: d405 bmi.n 800bfec <_vfiprintf_r+0x220> 800bfe0: 89ab ldrh r3, [r5, #12] 800bfe2: 059a lsls r2, r3, #22 800bfe4: d402 bmi.n 800bfec <_vfiprintf_r+0x220> 800bfe6: 6da8 ldr r0, [r5, #88] ; 0x58 800bfe8: f7ff fab2 bl 800b550 <__retarget_lock_release_recursive> 800bfec: 89ab ldrh r3, [r5, #12] 800bfee: 065b lsls r3, r3, #25 800bff0: f53f af12 bmi.w 800be18 <_vfiprintf_r+0x4c> 800bff4: 9809 ldr r0, [sp, #36] ; 0x24 800bff6: e711 b.n 800be1c <_vfiprintf_r+0x50> 800bff8: ab03 add r3, sp, #12 800bffa: 9300 str r3, [sp, #0] 800bffc: 462a mov r2, r5 800bffe: 4630 mov r0, r6 800c000: 4b09 ldr r3, [pc, #36] ; (800c028 <_vfiprintf_r+0x25c>) 800c002: a904 add r1, sp, #16 800c004: f7fd fd20 bl 8009a48 <_printf_i> 800c008: e7e4 b.n 800bfd4 <_vfiprintf_r+0x208> 800c00a: bf00 nop 800c00c: 0800d524 .word 0x0800d524 800c010: 0800d544 .word 0x0800d544 800c014: 0800d504 .word 0x0800d504 800c018: 0800d6bc .word 0x0800d6bc 800c01c: 0800d6c2 .word 0x0800d6c2 800c020: 0800d6c6 .word 0x0800d6c6 800c024: 08009511 .word 0x08009511 800c028: 0800bda7 .word 0x0800bda7 0800c02c : 800c02c: b40e push {r1, r2, r3} 800c02e: f44f 7201 mov.w r2, #516 ; 0x204 800c032: b530 push {r4, r5, lr} 800c034: b09c sub sp, #112 ; 0x70 800c036: ac1f add r4, sp, #124 ; 0x7c 800c038: f854 5b04 ldr.w r5, [r4], #4 800c03c: f8ad 2014 strh.w r2, [sp, #20] 800c040: 9002 str r0, [sp, #8] 800c042: 9006 str r0, [sp, #24] 800c044: f7f4 f8f0 bl 8000228 800c048: 4b0b ldr r3, [pc, #44] ; (800c078 ) 800c04a: 9003 str r0, [sp, #12] 800c04c: 930b str r3, [sp, #44] ; 0x2c 800c04e: 2300 movs r3, #0 800c050: 930f str r3, [sp, #60] ; 0x3c 800c052: 9314 str r3, [sp, #80] ; 0x50 800c054: f64f 73ff movw r3, #65535 ; 0xffff 800c058: 9007 str r0, [sp, #28] 800c05a: 4808 ldr r0, [pc, #32] ; (800c07c ) 800c05c: f8ad 3016 strh.w r3, [sp, #22] 800c060: 462a mov r2, r5 800c062: 4623 mov r3, r4 800c064: a902 add r1, sp, #8 800c066: 6800 ldr r0, [r0, #0] 800c068: 9401 str r4, [sp, #4] 800c06a: f000 f9db bl 800c424 <__ssvfiscanf_r> 800c06e: b01c add sp, #112 ; 0x70 800c070: e8bd 4030 ldmia.w sp!, {r4, r5, lr} 800c074: b003 add sp, #12 800c076: 4770 bx lr 800c078: 0800c0a3 .word 0x0800c0a3 800c07c: 20000014 .word 0x20000014 0800c080 <__sread>: 800c080: b510 push {r4, lr} 800c082: 460c mov r4, r1 800c084: f9b1 100e ldrsh.w r1, [r1, #14] 800c088: f000 fc98 bl 800c9bc <_read_r> 800c08c: 2800 cmp r0, #0 800c08e: bfab itete ge 800c090: 6d63 ldrge r3, [r4, #84] ; 0x54 800c092: 89a3 ldrhlt r3, [r4, #12] 800c094: 181b addge r3, r3, r0 800c096: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 800c09a: bfac ite ge 800c09c: 6563 strge r3, [r4, #84] ; 0x54 800c09e: 81a3 strhlt r3, [r4, #12] 800c0a0: bd10 pop {r4, pc} 0800c0a2 <__seofread>: 800c0a2: 2000 movs r0, #0 800c0a4: 4770 bx lr 0800c0a6 <__swrite>: 800c0a6: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800c0aa: 461f mov r7, r3 800c0ac: 898b ldrh r3, [r1, #12] 800c0ae: 4605 mov r5, r0 800c0b0: 05db lsls r3, r3, #23 800c0b2: 460c mov r4, r1 800c0b4: 4616 mov r6, r2 800c0b6: d505 bpl.n 800c0c4 <__swrite+0x1e> 800c0b8: 2302 movs r3, #2 800c0ba: 2200 movs r2, #0 800c0bc: f9b1 100e ldrsh.w r1, [r1, #14] 800c0c0: f000 f902 bl 800c2c8 <_lseek_r> 800c0c4: 89a3 ldrh r3, [r4, #12] 800c0c6: 4632 mov r2, r6 800c0c8: f423 5380 bic.w r3, r3, #4096 ; 0x1000 800c0cc: 81a3 strh r3, [r4, #12] 800c0ce: 4628 mov r0, r5 800c0d0: 463b mov r3, r7 800c0d2: f9b4 100e ldrsh.w r1, [r4, #14] 800c0d6: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 800c0da: f000 b89d b.w 800c218 <_write_r> 0800c0de <__sseek>: 800c0de: b510 push {r4, lr} 800c0e0: 460c mov r4, r1 800c0e2: f9b1 100e ldrsh.w r1, [r1, #14] 800c0e6: f000 f8ef bl 800c2c8 <_lseek_r> 800c0ea: 1c43 adds r3, r0, #1 800c0ec: 89a3 ldrh r3, [r4, #12] 800c0ee: bf15 itete ne 800c0f0: 6560 strne r0, [r4, #84] ; 0x54 800c0f2: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 800c0f6: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 800c0fa: 81a3 strheq r3, [r4, #12] 800c0fc: bf18 it ne 800c0fe: 81a3 strhne r3, [r4, #12] 800c100: bd10 pop {r4, pc} 0800c102 <__sclose>: 800c102: f9b1 100e ldrsh.w r1, [r1, #14] 800c106: f000 b8a1 b.w 800c24c <_close_r> 0800c10a : 800c10a: 4603 mov r3, r0 800c10c: f811 2b01 ldrb.w r2, [r1], #1 800c110: f803 2b01 strb.w r2, [r3], #1 800c114: 2a00 cmp r2, #0 800c116: d1f9 bne.n 800c10c 800c118: 4770 bx lr ... 0800c11c <_strtoul_l.constprop.0>: 800c11c: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 800c120: 4686 mov lr, r0 800c122: 460d mov r5, r1 800c124: 4f35 ldr r7, [pc, #212] ; (800c1fc <_strtoul_l.constprop.0+0xe0>) 800c126: 4628 mov r0, r5 800c128: f815 4b01 ldrb.w r4, [r5], #1 800c12c: 5de6 ldrb r6, [r4, r7] 800c12e: f016 0608 ands.w r6, r6, #8 800c132: d1f8 bne.n 800c126 <_strtoul_l.constprop.0+0xa> 800c134: 2c2d cmp r4, #45 ; 0x2d 800c136: d12f bne.n 800c198 <_strtoul_l.constprop.0+0x7c> 800c138: 2601 movs r6, #1 800c13a: 782c ldrb r4, [r5, #0] 800c13c: 1c85 adds r5, r0, #2 800c13e: 2b00 cmp r3, #0 800c140: d057 beq.n 800c1f2 <_strtoul_l.constprop.0+0xd6> 800c142: 2b10 cmp r3, #16 800c144: d109 bne.n 800c15a <_strtoul_l.constprop.0+0x3e> 800c146: 2c30 cmp r4, #48 ; 0x30 800c148: d107 bne.n 800c15a <_strtoul_l.constprop.0+0x3e> 800c14a: 7828 ldrb r0, [r5, #0] 800c14c: f000 00df and.w r0, r0, #223 ; 0xdf 800c150: 2858 cmp r0, #88 ; 0x58 800c152: d149 bne.n 800c1e8 <_strtoul_l.constprop.0+0xcc> 800c154: 2310 movs r3, #16 800c156: 786c ldrb r4, [r5, #1] 800c158: 3502 adds r5, #2 800c15a: f04f 38ff mov.w r8, #4294967295 ; 0xffffffff 800c15e: fbb8 f8f3 udiv r8, r8, r3 800c162: 2700 movs r7, #0 800c164: fb03 f908 mul.w r9, r3, r8 800c168: 4638 mov r0, r7 800c16a: ea6f 0909 mvn.w r9, r9 800c16e: f1a4 0c30 sub.w ip, r4, #48 ; 0x30 800c172: f1bc 0f09 cmp.w ip, #9 800c176: d814 bhi.n 800c1a2 <_strtoul_l.constprop.0+0x86> 800c178: 4664 mov r4, ip 800c17a: 42a3 cmp r3, r4 800c17c: dd22 ble.n 800c1c4 <_strtoul_l.constprop.0+0xa8> 800c17e: 2f00 cmp r7, #0 800c180: db1d blt.n 800c1be <_strtoul_l.constprop.0+0xa2> 800c182: 4580 cmp r8, r0 800c184: d31b bcc.n 800c1be <_strtoul_l.constprop.0+0xa2> 800c186: d101 bne.n 800c18c <_strtoul_l.constprop.0+0x70> 800c188: 45a1 cmp r9, r4 800c18a: db18 blt.n 800c1be <_strtoul_l.constprop.0+0xa2> 800c18c: 2701 movs r7, #1 800c18e: fb00 4003 mla r0, r0, r3, r4 800c192: f815 4b01 ldrb.w r4, [r5], #1 800c196: e7ea b.n 800c16e <_strtoul_l.constprop.0+0x52> 800c198: 2c2b cmp r4, #43 ; 0x2b 800c19a: bf04 itt eq 800c19c: 782c ldrbeq r4, [r5, #0] 800c19e: 1c85 addeq r5, r0, #2 800c1a0: e7cd b.n 800c13e <_strtoul_l.constprop.0+0x22> 800c1a2: f1a4 0c41 sub.w ip, r4, #65 ; 0x41 800c1a6: f1bc 0f19 cmp.w ip, #25 800c1aa: d801 bhi.n 800c1b0 <_strtoul_l.constprop.0+0x94> 800c1ac: 3c37 subs r4, #55 ; 0x37 800c1ae: e7e4 b.n 800c17a <_strtoul_l.constprop.0+0x5e> 800c1b0: f1a4 0c61 sub.w ip, r4, #97 ; 0x61 800c1b4: f1bc 0f19 cmp.w ip, #25 800c1b8: d804 bhi.n 800c1c4 <_strtoul_l.constprop.0+0xa8> 800c1ba: 3c57 subs r4, #87 ; 0x57 800c1bc: e7dd b.n 800c17a <_strtoul_l.constprop.0+0x5e> 800c1be: f04f 37ff mov.w r7, #4294967295 ; 0xffffffff 800c1c2: e7e6 b.n 800c192 <_strtoul_l.constprop.0+0x76> 800c1c4: 2f00 cmp r7, #0 800c1c6: da07 bge.n 800c1d8 <_strtoul_l.constprop.0+0xbc> 800c1c8: 2322 movs r3, #34 ; 0x22 800c1ca: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800c1ce: f8ce 3000 str.w r3, [lr] 800c1d2: b932 cbnz r2, 800c1e2 <_strtoul_l.constprop.0+0xc6> 800c1d4: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 800c1d8: b106 cbz r6, 800c1dc <_strtoul_l.constprop.0+0xc0> 800c1da: 4240 negs r0, r0 800c1dc: 2a00 cmp r2, #0 800c1de: d0f9 beq.n 800c1d4 <_strtoul_l.constprop.0+0xb8> 800c1e0: b107 cbz r7, 800c1e4 <_strtoul_l.constprop.0+0xc8> 800c1e2: 1e69 subs r1, r5, #1 800c1e4: 6011 str r1, [r2, #0] 800c1e6: e7f5 b.n 800c1d4 <_strtoul_l.constprop.0+0xb8> 800c1e8: 2430 movs r4, #48 ; 0x30 800c1ea: 2b00 cmp r3, #0 800c1ec: d1b5 bne.n 800c15a <_strtoul_l.constprop.0+0x3e> 800c1ee: 2308 movs r3, #8 800c1f0: e7b3 b.n 800c15a <_strtoul_l.constprop.0+0x3e> 800c1f2: 2c30 cmp r4, #48 ; 0x30 800c1f4: d0a9 beq.n 800c14a <_strtoul_l.constprop.0+0x2e> 800c1f6: 230a movs r3, #10 800c1f8: e7af b.n 800c15a <_strtoul_l.constprop.0+0x3e> 800c1fa: bf00 nop 800c1fc: 0800d6ce .word 0x0800d6ce 0800c200 <_strtoul_r>: 800c200: f7ff bf8c b.w 800c11c <_strtoul_l.constprop.0> 0800c204 : 800c204: 4613 mov r3, r2 800c206: 460a mov r2, r1 800c208: 4601 mov r1, r0 800c20a: 4802 ldr r0, [pc, #8] ; (800c214 ) 800c20c: 6800 ldr r0, [r0, #0] 800c20e: f7ff bf85 b.w 800c11c <_strtoul_l.constprop.0> 800c212: bf00 nop 800c214: 20000014 .word 0x20000014 0800c218 <_write_r>: 800c218: b538 push {r3, r4, r5, lr} 800c21a: 4604 mov r4, r0 800c21c: 4608 mov r0, r1 800c21e: 4611 mov r1, r2 800c220: 2200 movs r2, #0 800c222: 4d05 ldr r5, [pc, #20] ; (800c238 <_write_r+0x20>) 800c224: 602a str r2, [r5, #0] 800c226: 461a mov r2, r3 800c228: f7f6 fb0e bl 8002848 <_write> 800c22c: 1c43 adds r3, r0, #1 800c22e: d102 bne.n 800c236 <_write_r+0x1e> 800c230: 682b ldr r3, [r5, #0] 800c232: b103 cbz r3, 800c236 <_write_r+0x1e> 800c234: 6023 str r3, [r4, #0] 800c236: bd38 pop {r3, r4, r5, pc} 800c238: 200033cc .word 0x200033cc 0800c23c : 800c23c: 2006 movs r0, #6 800c23e: b508 push {r3, lr} 800c240: f000 fc2e bl 800caa0 800c244: 2001 movs r0, #1 800c246: f7f8 fe08 bl 8004e5a <_exit> ... 0800c24c <_close_r>: 800c24c: b538 push {r3, r4, r5, lr} 800c24e: 2300 movs r3, #0 800c250: 4d05 ldr r5, [pc, #20] ; (800c268 <_close_r+0x1c>) 800c252: 4604 mov r4, r0 800c254: 4608 mov r0, r1 800c256: 602b str r3, [r5, #0] 800c258: f7f8 fe26 bl 8004ea8 <_close> 800c25c: 1c43 adds r3, r0, #1 800c25e: d102 bne.n 800c266 <_close_r+0x1a> 800c260: 682b ldr r3, [r5, #0] 800c262: b103 cbz r3, 800c266 <_close_r+0x1a> 800c264: 6023 str r3, [r4, #0] 800c266: bd38 pop {r3, r4, r5, pc} 800c268: 200033cc .word 0x200033cc 0800c26c <__env_lock>: 800c26c: 4801 ldr r0, [pc, #4] ; (800c274 <__env_lock+0x8>) 800c26e: f7ff b96d b.w 800b54c <__retarget_lock_acquire_recursive> 800c272: bf00 nop 800c274: 200033c4 .word 0x200033c4 0800c278 <__env_unlock>: 800c278: 4801 ldr r0, [pc, #4] ; (800c280 <__env_unlock+0x8>) 800c27a: f7ff b969 b.w 800b550 <__retarget_lock_release_recursive> 800c27e: bf00 nop 800c280: 200033c4 .word 0x200033c4 0800c284 <_fstat_r>: 800c284: b538 push {r3, r4, r5, lr} 800c286: 2300 movs r3, #0 800c288: 4d06 ldr r5, [pc, #24] ; (800c2a4 <_fstat_r+0x20>) 800c28a: 4604 mov r4, r0 800c28c: 4608 mov r0, r1 800c28e: 4611 mov r1, r2 800c290: 602b str r3, [r5, #0] 800c292: f7f8 fe14 bl 8004ebe <_fstat> 800c296: 1c43 adds r3, r0, #1 800c298: d102 bne.n 800c2a0 <_fstat_r+0x1c> 800c29a: 682b ldr r3, [r5, #0] 800c29c: b103 cbz r3, 800c2a0 <_fstat_r+0x1c> 800c29e: 6023 str r3, [r4, #0] 800c2a0: bd38 pop {r3, r4, r5, pc} 800c2a2: bf00 nop 800c2a4: 200033cc .word 0x200033cc 0800c2a8 <_isatty_r>: 800c2a8: b538 push {r3, r4, r5, lr} 800c2aa: 2300 movs r3, #0 800c2ac: 4d05 ldr r5, [pc, #20] ; (800c2c4 <_isatty_r+0x1c>) 800c2ae: 4604 mov r4, r0 800c2b0: 4608 mov r0, r1 800c2b2: 602b str r3, [r5, #0] 800c2b4: f7f8 fe12 bl 8004edc <_isatty> 800c2b8: 1c43 adds r3, r0, #1 800c2ba: d102 bne.n 800c2c2 <_isatty_r+0x1a> 800c2bc: 682b ldr r3, [r5, #0] 800c2be: b103 cbz r3, 800c2c2 <_isatty_r+0x1a> 800c2c0: 6023 str r3, [r4, #0] 800c2c2: bd38 pop {r3, r4, r5, pc} 800c2c4: 200033cc .word 0x200033cc 0800c2c8 <_lseek_r>: 800c2c8: b538 push {r3, r4, r5, lr} 800c2ca: 4604 mov r4, r0 800c2cc: 4608 mov r0, r1 800c2ce: 4611 mov r1, r2 800c2d0: 2200 movs r2, #0 800c2d2: 4d05 ldr r5, [pc, #20] ; (800c2e8 <_lseek_r+0x20>) 800c2d4: 602a str r2, [r5, #0] 800c2d6: 461a mov r2, r3 800c2d8: f7f8 fe0a bl 8004ef0 <_lseek> 800c2dc: 1c43 adds r3, r0, #1 800c2de: d102 bne.n 800c2e6 <_lseek_r+0x1e> 800c2e0: 682b ldr r3, [r5, #0] 800c2e2: b103 cbz r3, 800c2e6 <_lseek_r+0x1e> 800c2e4: 6023 str r3, [r4, #0] 800c2e6: bd38 pop {r3, r4, r5, pc} 800c2e8: 200033cc .word 0x200033cc 0800c2ec <__ascii_mbtowc>: 800c2ec: b082 sub sp, #8 800c2ee: b901 cbnz r1, 800c2f2 <__ascii_mbtowc+0x6> 800c2f0: a901 add r1, sp, #4 800c2f2: b142 cbz r2, 800c306 <__ascii_mbtowc+0x1a> 800c2f4: b14b cbz r3, 800c30a <__ascii_mbtowc+0x1e> 800c2f6: 7813 ldrb r3, [r2, #0] 800c2f8: 600b str r3, [r1, #0] 800c2fa: 7812 ldrb r2, [r2, #0] 800c2fc: 1e10 subs r0, r2, #0 800c2fe: bf18 it ne 800c300: 2001 movne r0, #1 800c302: b002 add sp, #8 800c304: 4770 bx lr 800c306: 4610 mov r0, r2 800c308: e7fb b.n 800c302 <__ascii_mbtowc+0x16> 800c30a: f06f 0001 mvn.w r0, #1 800c30e: e7f8 b.n 800c302 <__ascii_mbtowc+0x16> 0800c310 <_realloc_r>: 800c310: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800c314: 4680 mov r8, r0 800c316: 4614 mov r4, r2 800c318: 460e mov r6, r1 800c31a: b921 cbnz r1, 800c326 <_realloc_r+0x16> 800c31c: 4611 mov r1, r2 800c31e: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 800c322: f7fc bfe3 b.w 80092ec <_malloc_r> 800c326: b92a cbnz r2, 800c334 <_realloc_r+0x24> 800c328: f7fc ff78 bl 800921c <_free_r> 800c32c: 4625 mov r5, r4 800c32e: 4628 mov r0, r5 800c330: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800c334: f000 fc93 bl 800cc5e <_malloc_usable_size_r> 800c338: 4284 cmp r4, r0 800c33a: 4607 mov r7, r0 800c33c: d802 bhi.n 800c344 <_realloc_r+0x34> 800c33e: ebb4 0f50 cmp.w r4, r0, lsr #1 800c342: d812 bhi.n 800c36a <_realloc_r+0x5a> 800c344: 4621 mov r1, r4 800c346: 4640 mov r0, r8 800c348: f7fc ffd0 bl 80092ec <_malloc_r> 800c34c: 4605 mov r5, r0 800c34e: 2800 cmp r0, #0 800c350: d0ed beq.n 800c32e <_realloc_r+0x1e> 800c352: 42bc cmp r4, r7 800c354: 4622 mov r2, r4 800c356: 4631 mov r1, r6 800c358: bf28 it cs 800c35a: 463a movcs r2, r7 800c35c: f7fc ff48 bl 80091f0 800c360: 4631 mov r1, r6 800c362: 4640 mov r0, r8 800c364: f7fc ff5a bl 800921c <_free_r> 800c368: e7e1 b.n 800c32e <_realloc_r+0x1e> 800c36a: 4635 mov r5, r6 800c36c: e7df b.n 800c32e <_realloc_r+0x1e> 0800c36e <_sungetc_r>: 800c36e: b538 push {r3, r4, r5, lr} 800c370: 1c4b adds r3, r1, #1 800c372: 4614 mov r4, r2 800c374: d103 bne.n 800c37e <_sungetc_r+0x10> 800c376: f04f 35ff mov.w r5, #4294967295 ; 0xffffffff 800c37a: 4628 mov r0, r5 800c37c: bd38 pop {r3, r4, r5, pc} 800c37e: 8993 ldrh r3, [r2, #12] 800c380: b2cd uxtb r5, r1 800c382: f023 0320 bic.w r3, r3, #32 800c386: 8193 strh r3, [r2, #12] 800c388: 6b63 ldr r3, [r4, #52] ; 0x34 800c38a: 6852 ldr r2, [r2, #4] 800c38c: b18b cbz r3, 800c3b2 <_sungetc_r+0x44> 800c38e: 6ba3 ldr r3, [r4, #56] ; 0x38 800c390: 4293 cmp r3, r2 800c392: dd08 ble.n 800c3a6 <_sungetc_r+0x38> 800c394: 6823 ldr r3, [r4, #0] 800c396: 1e5a subs r2, r3, #1 800c398: 6022 str r2, [r4, #0] 800c39a: f803 5c01 strb.w r5, [r3, #-1] 800c39e: 6863 ldr r3, [r4, #4] 800c3a0: 3301 adds r3, #1 800c3a2: 6063 str r3, [r4, #4] 800c3a4: e7e9 b.n 800c37a <_sungetc_r+0xc> 800c3a6: 4621 mov r1, r4 800c3a8: f000 fc14 bl 800cbd4 <__submore> 800c3ac: 2800 cmp r0, #0 800c3ae: d0f1 beq.n 800c394 <_sungetc_r+0x26> 800c3b0: e7e1 b.n 800c376 <_sungetc_r+0x8> 800c3b2: 6921 ldr r1, [r4, #16] 800c3b4: 6823 ldr r3, [r4, #0] 800c3b6: b151 cbz r1, 800c3ce <_sungetc_r+0x60> 800c3b8: 4299 cmp r1, r3 800c3ba: d208 bcs.n 800c3ce <_sungetc_r+0x60> 800c3bc: f813 1c01 ldrb.w r1, [r3, #-1] 800c3c0: 42a9 cmp r1, r5 800c3c2: d104 bne.n 800c3ce <_sungetc_r+0x60> 800c3c4: 3b01 subs r3, #1 800c3c6: 3201 adds r2, #1 800c3c8: 6023 str r3, [r4, #0] 800c3ca: 6062 str r2, [r4, #4] 800c3cc: e7d5 b.n 800c37a <_sungetc_r+0xc> 800c3ce: e9c4 320f strd r3, r2, [r4, #60] ; 0x3c 800c3d2: f104 0344 add.w r3, r4, #68 ; 0x44 800c3d6: 6363 str r3, [r4, #52] ; 0x34 800c3d8: 2303 movs r3, #3 800c3da: 63a3 str r3, [r4, #56] ; 0x38 800c3dc: 4623 mov r3, r4 800c3de: f803 5f46 strb.w r5, [r3, #70]! 800c3e2: 6023 str r3, [r4, #0] 800c3e4: 2301 movs r3, #1 800c3e6: e7dc b.n 800c3a2 <_sungetc_r+0x34> 0800c3e8 <__ssrefill_r>: 800c3e8: b510 push {r4, lr} 800c3ea: 460c mov r4, r1 800c3ec: 6b49 ldr r1, [r1, #52] ; 0x34 800c3ee: b169 cbz r1, 800c40c <__ssrefill_r+0x24> 800c3f0: f104 0344 add.w r3, r4, #68 ; 0x44 800c3f4: 4299 cmp r1, r3 800c3f6: d001 beq.n 800c3fc <__ssrefill_r+0x14> 800c3f8: f7fc ff10 bl 800921c <_free_r> 800c3fc: 2000 movs r0, #0 800c3fe: 6c23 ldr r3, [r4, #64] ; 0x40 800c400: 6360 str r0, [r4, #52] ; 0x34 800c402: 6063 str r3, [r4, #4] 800c404: b113 cbz r3, 800c40c <__ssrefill_r+0x24> 800c406: 6be3 ldr r3, [r4, #60] ; 0x3c 800c408: 6023 str r3, [r4, #0] 800c40a: bd10 pop {r4, pc} 800c40c: 6923 ldr r3, [r4, #16] 800c40e: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800c412: 6023 str r3, [r4, #0] 800c414: 2300 movs r3, #0 800c416: 6063 str r3, [r4, #4] 800c418: 89a3 ldrh r3, [r4, #12] 800c41a: f043 0320 orr.w r3, r3, #32 800c41e: 81a3 strh r3, [r4, #12] 800c420: e7f3 b.n 800c40a <__ssrefill_r+0x22> ... 0800c424 <__ssvfiscanf_r>: 800c424: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800c428: 460c mov r4, r1 800c42a: 2100 movs r1, #0 800c42c: 4606 mov r6, r0 800c42e: f5ad 7d22 sub.w sp, sp, #648 ; 0x288 800c432: e9cd 1144 strd r1, r1, [sp, #272] ; 0x110 800c436: 49a7 ldr r1, [pc, #668] ; (800c6d4 <__ssvfiscanf_r+0x2b0>) 800c438: f10d 0804 add.w r8, sp, #4 800c43c: 91a0 str r1, [sp, #640] ; 0x280 800c43e: 49a6 ldr r1, [pc, #664] ; (800c6d8 <__ssvfiscanf_r+0x2b4>) 800c440: 4fa6 ldr r7, [pc, #664] ; (800c6dc <__ssvfiscanf_r+0x2b8>) 800c442: f8df 929c ldr.w r9, [pc, #668] ; 800c6e0 <__ssvfiscanf_r+0x2bc> 800c446: f8cd 8118 str.w r8, [sp, #280] ; 0x118 800c44a: 91a1 str r1, [sp, #644] ; 0x284 800c44c: 9300 str r3, [sp, #0] 800c44e: 7813 ldrb r3, [r2, #0] 800c450: 2b00 cmp r3, #0 800c452: f000 815c beq.w 800c70e <__ssvfiscanf_r+0x2ea> 800c456: 5dd9 ldrb r1, [r3, r7] 800c458: 1c55 adds r5, r2, #1 800c45a: f011 0108 ands.w r1, r1, #8 800c45e: d019 beq.n 800c494 <__ssvfiscanf_r+0x70> 800c460: 6863 ldr r3, [r4, #4] 800c462: 2b00 cmp r3, #0 800c464: dd0f ble.n 800c486 <__ssvfiscanf_r+0x62> 800c466: 6823 ldr r3, [r4, #0] 800c468: 781a ldrb r2, [r3, #0] 800c46a: 5cba ldrb r2, [r7, r2] 800c46c: 0712 lsls r2, r2, #28 800c46e: d401 bmi.n 800c474 <__ssvfiscanf_r+0x50> 800c470: 462a mov r2, r5 800c472: e7ec b.n 800c44e <__ssvfiscanf_r+0x2a> 800c474: 9a45 ldr r2, [sp, #276] ; 0x114 800c476: 3301 adds r3, #1 800c478: 3201 adds r2, #1 800c47a: 9245 str r2, [sp, #276] ; 0x114 800c47c: 6862 ldr r2, [r4, #4] 800c47e: 6023 str r3, [r4, #0] 800c480: 3a01 subs r2, #1 800c482: 6062 str r2, [r4, #4] 800c484: e7ec b.n 800c460 <__ssvfiscanf_r+0x3c> 800c486: 4621 mov r1, r4 800c488: 4630 mov r0, r6 800c48a: 9ba1 ldr r3, [sp, #644] ; 0x284 800c48c: 4798 blx r3 800c48e: 2800 cmp r0, #0 800c490: d0e9 beq.n 800c466 <__ssvfiscanf_r+0x42> 800c492: e7ed b.n 800c470 <__ssvfiscanf_r+0x4c> 800c494: 2b25 cmp r3, #37 ; 0x25 800c496: d012 beq.n 800c4be <__ssvfiscanf_r+0x9a> 800c498: 469a mov sl, r3 800c49a: 6863 ldr r3, [r4, #4] 800c49c: 2b00 cmp r3, #0 800c49e: f340 8094 ble.w 800c5ca <__ssvfiscanf_r+0x1a6> 800c4a2: 6822 ldr r2, [r4, #0] 800c4a4: 7813 ldrb r3, [r2, #0] 800c4a6: 4553 cmp r3, sl 800c4a8: f040 8131 bne.w 800c70e <__ssvfiscanf_r+0x2ea> 800c4ac: 6863 ldr r3, [r4, #4] 800c4ae: 3201 adds r2, #1 800c4b0: 3b01 subs r3, #1 800c4b2: 6063 str r3, [r4, #4] 800c4b4: 9b45 ldr r3, [sp, #276] ; 0x114 800c4b6: 6022 str r2, [r4, #0] 800c4b8: 3301 adds r3, #1 800c4ba: 9345 str r3, [sp, #276] ; 0x114 800c4bc: e7d8 b.n 800c470 <__ssvfiscanf_r+0x4c> 800c4be: 9141 str r1, [sp, #260] ; 0x104 800c4c0: 9143 str r1, [sp, #268] ; 0x10c 800c4c2: 7853 ldrb r3, [r2, #1] 800c4c4: 2b2a cmp r3, #42 ; 0x2a 800c4c6: bf04 itt eq 800c4c8: 2310 moveq r3, #16 800c4ca: 1c95 addeq r5, r2, #2 800c4cc: f04f 020a mov.w r2, #10 800c4d0: bf08 it eq 800c4d2: 9341 streq r3, [sp, #260] ; 0x104 800c4d4: 46aa mov sl, r5 800c4d6: f81a 1b01 ldrb.w r1, [sl], #1 800c4da: f1a1 0330 sub.w r3, r1, #48 ; 0x30 800c4de: 2b09 cmp r3, #9 800c4e0: d91d bls.n 800c51e <__ssvfiscanf_r+0xfa> 800c4e2: 2203 movs r2, #3 800c4e4: 487e ldr r0, [pc, #504] ; (800c6e0 <__ssvfiscanf_r+0x2bc>) 800c4e6: f7ff f899 bl 800b61c 800c4ea: b140 cbz r0, 800c4fe <__ssvfiscanf_r+0xda> 800c4ec: 2301 movs r3, #1 800c4ee: 4655 mov r5, sl 800c4f0: eba0 0009 sub.w r0, r0, r9 800c4f4: fa03 f000 lsl.w r0, r3, r0 800c4f8: 9b41 ldr r3, [sp, #260] ; 0x104 800c4fa: 4318 orrs r0, r3 800c4fc: 9041 str r0, [sp, #260] ; 0x104 800c4fe: f815 3b01 ldrb.w r3, [r5], #1 800c502: 2b78 cmp r3, #120 ; 0x78 800c504: d806 bhi.n 800c514 <__ssvfiscanf_r+0xf0> 800c506: 2b57 cmp r3, #87 ; 0x57 800c508: d810 bhi.n 800c52c <__ssvfiscanf_r+0x108> 800c50a: 2b25 cmp r3, #37 ; 0x25 800c50c: d0c4 beq.n 800c498 <__ssvfiscanf_r+0x74> 800c50e: d857 bhi.n 800c5c0 <__ssvfiscanf_r+0x19c> 800c510: 2b00 cmp r3, #0 800c512: d065 beq.n 800c5e0 <__ssvfiscanf_r+0x1bc> 800c514: 2303 movs r3, #3 800c516: 9347 str r3, [sp, #284] ; 0x11c 800c518: 230a movs r3, #10 800c51a: 9342 str r3, [sp, #264] ; 0x108 800c51c: e072 b.n 800c604 <__ssvfiscanf_r+0x1e0> 800c51e: 9b43 ldr r3, [sp, #268] ; 0x10c 800c520: 4655 mov r5, sl 800c522: fb02 1103 mla r1, r2, r3, r1 800c526: 3930 subs r1, #48 ; 0x30 800c528: 9143 str r1, [sp, #268] ; 0x10c 800c52a: e7d3 b.n 800c4d4 <__ssvfiscanf_r+0xb0> 800c52c: f1a3 0258 sub.w r2, r3, #88 ; 0x58 800c530: 2a20 cmp r2, #32 800c532: d8ef bhi.n 800c514 <__ssvfiscanf_r+0xf0> 800c534: a101 add r1, pc, #4 ; (adr r1, 800c53c <__ssvfiscanf_r+0x118>) 800c536: f851 f022 ldr.w pc, [r1, r2, lsl #2] 800c53a: bf00 nop 800c53c: 0800c5ef .word 0x0800c5ef 800c540: 0800c515 .word 0x0800c515 800c544: 0800c515 .word 0x0800c515 800c548: 0800c64d .word 0x0800c64d 800c54c: 0800c515 .word 0x0800c515 800c550: 0800c515 .word 0x0800c515 800c554: 0800c515 .word 0x0800c515 800c558: 0800c515 .word 0x0800c515 800c55c: 0800c515 .word 0x0800c515 800c560: 0800c515 .word 0x0800c515 800c564: 0800c515 .word 0x0800c515 800c568: 0800c663 .word 0x0800c663 800c56c: 0800c639 .word 0x0800c639 800c570: 0800c5c7 .word 0x0800c5c7 800c574: 0800c5c7 .word 0x0800c5c7 800c578: 0800c5c7 .word 0x0800c5c7 800c57c: 0800c515 .word 0x0800c515 800c580: 0800c63d .word 0x0800c63d 800c584: 0800c515 .word 0x0800c515 800c588: 0800c515 .word 0x0800c515 800c58c: 0800c515 .word 0x0800c515 800c590: 0800c515 .word 0x0800c515 800c594: 0800c673 .word 0x0800c673 800c598: 0800c645 .word 0x0800c645 800c59c: 0800c5e7 .word 0x0800c5e7 800c5a0: 0800c515 .word 0x0800c515 800c5a4: 0800c515 .word 0x0800c515 800c5a8: 0800c66f .word 0x0800c66f 800c5ac: 0800c515 .word 0x0800c515 800c5b0: 0800c639 .word 0x0800c639 800c5b4: 0800c515 .word 0x0800c515 800c5b8: 0800c515 .word 0x0800c515 800c5bc: 0800c5ef .word 0x0800c5ef 800c5c0: 3b45 subs r3, #69 ; 0x45 800c5c2: 2b02 cmp r3, #2 800c5c4: d8a6 bhi.n 800c514 <__ssvfiscanf_r+0xf0> 800c5c6: 2305 movs r3, #5 800c5c8: e01b b.n 800c602 <__ssvfiscanf_r+0x1de> 800c5ca: 4621 mov r1, r4 800c5cc: 4630 mov r0, r6 800c5ce: 9ba1 ldr r3, [sp, #644] ; 0x284 800c5d0: 4798 blx r3 800c5d2: 2800 cmp r0, #0 800c5d4: f43f af65 beq.w 800c4a2 <__ssvfiscanf_r+0x7e> 800c5d8: 9844 ldr r0, [sp, #272] ; 0x110 800c5da: 2800 cmp r0, #0 800c5dc: f040 808d bne.w 800c6fa <__ssvfiscanf_r+0x2d6> 800c5e0: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800c5e4: e08f b.n 800c706 <__ssvfiscanf_r+0x2e2> 800c5e6: 9a41 ldr r2, [sp, #260] ; 0x104 800c5e8: f042 0220 orr.w r2, r2, #32 800c5ec: 9241 str r2, [sp, #260] ; 0x104 800c5ee: 9a41 ldr r2, [sp, #260] ; 0x104 800c5f0: f442 7200 orr.w r2, r2, #512 ; 0x200 800c5f4: 9241 str r2, [sp, #260] ; 0x104 800c5f6: 2210 movs r2, #16 800c5f8: 2b6f cmp r3, #111 ; 0x6f 800c5fa: bf34 ite cc 800c5fc: 2303 movcc r3, #3 800c5fe: 2304 movcs r3, #4 800c600: 9242 str r2, [sp, #264] ; 0x108 800c602: 9347 str r3, [sp, #284] ; 0x11c 800c604: 6863 ldr r3, [r4, #4] 800c606: 2b00 cmp r3, #0 800c608: dd42 ble.n 800c690 <__ssvfiscanf_r+0x26c> 800c60a: 9b41 ldr r3, [sp, #260] ; 0x104 800c60c: 0659 lsls r1, r3, #25 800c60e: d404 bmi.n 800c61a <__ssvfiscanf_r+0x1f6> 800c610: 6823 ldr r3, [r4, #0] 800c612: 781a ldrb r2, [r3, #0] 800c614: 5cba ldrb r2, [r7, r2] 800c616: 0712 lsls r2, r2, #28 800c618: d441 bmi.n 800c69e <__ssvfiscanf_r+0x27a> 800c61a: 9b47 ldr r3, [sp, #284] ; 0x11c 800c61c: 2b02 cmp r3, #2 800c61e: dc50 bgt.n 800c6c2 <__ssvfiscanf_r+0x29e> 800c620: 466b mov r3, sp 800c622: 4622 mov r2, r4 800c624: 4630 mov r0, r6 800c626: a941 add r1, sp, #260 ; 0x104 800c628: f000 f876 bl 800c718 <_scanf_chars> 800c62c: 2801 cmp r0, #1 800c62e: d06e beq.n 800c70e <__ssvfiscanf_r+0x2ea> 800c630: 2802 cmp r0, #2 800c632: f47f af1d bne.w 800c470 <__ssvfiscanf_r+0x4c> 800c636: e7cf b.n 800c5d8 <__ssvfiscanf_r+0x1b4> 800c638: 220a movs r2, #10 800c63a: e7dd b.n 800c5f8 <__ssvfiscanf_r+0x1d4> 800c63c: 2300 movs r3, #0 800c63e: 9342 str r3, [sp, #264] ; 0x108 800c640: 2303 movs r3, #3 800c642: e7de b.n 800c602 <__ssvfiscanf_r+0x1de> 800c644: 2308 movs r3, #8 800c646: 9342 str r3, [sp, #264] ; 0x108 800c648: 2304 movs r3, #4 800c64a: e7da b.n 800c602 <__ssvfiscanf_r+0x1de> 800c64c: 4629 mov r1, r5 800c64e: 4640 mov r0, r8 800c650: f000 f9c6 bl 800c9e0 <__sccl> 800c654: 9b41 ldr r3, [sp, #260] ; 0x104 800c656: 4605 mov r5, r0 800c658: f043 0340 orr.w r3, r3, #64 ; 0x40 800c65c: 9341 str r3, [sp, #260] ; 0x104 800c65e: 2301 movs r3, #1 800c660: e7cf b.n 800c602 <__ssvfiscanf_r+0x1de> 800c662: 9b41 ldr r3, [sp, #260] ; 0x104 800c664: f043 0340 orr.w r3, r3, #64 ; 0x40 800c668: 9341 str r3, [sp, #260] ; 0x104 800c66a: 2300 movs r3, #0 800c66c: e7c9 b.n 800c602 <__ssvfiscanf_r+0x1de> 800c66e: 2302 movs r3, #2 800c670: e7c7 b.n 800c602 <__ssvfiscanf_r+0x1de> 800c672: 9841 ldr r0, [sp, #260] ; 0x104 800c674: 06c3 lsls r3, r0, #27 800c676: f53f aefb bmi.w 800c470 <__ssvfiscanf_r+0x4c> 800c67a: 9b00 ldr r3, [sp, #0] 800c67c: 9a45 ldr r2, [sp, #276] ; 0x114 800c67e: 1d19 adds r1, r3, #4 800c680: 9100 str r1, [sp, #0] 800c682: 681b ldr r3, [r3, #0] 800c684: f010 0f01 tst.w r0, #1 800c688: bf14 ite ne 800c68a: 801a strhne r2, [r3, #0] 800c68c: 601a streq r2, [r3, #0] 800c68e: e6ef b.n 800c470 <__ssvfiscanf_r+0x4c> 800c690: 4621 mov r1, r4 800c692: 4630 mov r0, r6 800c694: 9ba1 ldr r3, [sp, #644] ; 0x284 800c696: 4798 blx r3 800c698: 2800 cmp r0, #0 800c69a: d0b6 beq.n 800c60a <__ssvfiscanf_r+0x1e6> 800c69c: e79c b.n 800c5d8 <__ssvfiscanf_r+0x1b4> 800c69e: 9a45 ldr r2, [sp, #276] ; 0x114 800c6a0: 3201 adds r2, #1 800c6a2: 9245 str r2, [sp, #276] ; 0x114 800c6a4: 6862 ldr r2, [r4, #4] 800c6a6: 3a01 subs r2, #1 800c6a8: 2a00 cmp r2, #0 800c6aa: 6062 str r2, [r4, #4] 800c6ac: dd02 ble.n 800c6b4 <__ssvfiscanf_r+0x290> 800c6ae: 3301 adds r3, #1 800c6b0: 6023 str r3, [r4, #0] 800c6b2: e7ad b.n 800c610 <__ssvfiscanf_r+0x1ec> 800c6b4: 4621 mov r1, r4 800c6b6: 4630 mov r0, r6 800c6b8: 9ba1 ldr r3, [sp, #644] ; 0x284 800c6ba: 4798 blx r3 800c6bc: 2800 cmp r0, #0 800c6be: d0a7 beq.n 800c610 <__ssvfiscanf_r+0x1ec> 800c6c0: e78a b.n 800c5d8 <__ssvfiscanf_r+0x1b4> 800c6c2: 2b04 cmp r3, #4 800c6c4: dc0e bgt.n 800c6e4 <__ssvfiscanf_r+0x2c0> 800c6c6: 466b mov r3, sp 800c6c8: 4622 mov r2, r4 800c6ca: 4630 mov r0, r6 800c6cc: a941 add r1, sp, #260 ; 0x104 800c6ce: f000 f87d bl 800c7cc <_scanf_i> 800c6d2: e7ab b.n 800c62c <__ssvfiscanf_r+0x208> 800c6d4: 0800c36f .word 0x0800c36f 800c6d8: 0800c3e9 .word 0x0800c3e9 800c6dc: 0800d6ce .word 0x0800d6ce 800c6e0: 0800d6c2 .word 0x0800d6c2 800c6e4: 4b0b ldr r3, [pc, #44] ; (800c714 <__ssvfiscanf_r+0x2f0>) 800c6e6: 2b00 cmp r3, #0 800c6e8: f43f aec2 beq.w 800c470 <__ssvfiscanf_r+0x4c> 800c6ec: 466b mov r3, sp 800c6ee: 4622 mov r2, r4 800c6f0: 4630 mov r0, r6 800c6f2: a941 add r1, sp, #260 ; 0x104 800c6f4: f3af 8000 nop.w 800c6f8: e798 b.n 800c62c <__ssvfiscanf_r+0x208> 800c6fa: 89a3 ldrh r3, [r4, #12] 800c6fc: f013 0f40 tst.w r3, #64 ; 0x40 800c700: bf18 it ne 800c702: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff 800c706: f50d 7d22 add.w sp, sp, #648 ; 0x288 800c70a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800c70e: 9844 ldr r0, [sp, #272] ; 0x110 800c710: e7f9 b.n 800c706 <__ssvfiscanf_r+0x2e2> 800c712: bf00 nop 800c714: 00000000 .word 0x00000000 0800c718 <_scanf_chars>: 800c718: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 800c71c: 4615 mov r5, r2 800c71e: 688a ldr r2, [r1, #8] 800c720: 4680 mov r8, r0 800c722: 460c mov r4, r1 800c724: b932 cbnz r2, 800c734 <_scanf_chars+0x1c> 800c726: 698a ldr r2, [r1, #24] 800c728: 2a00 cmp r2, #0 800c72a: bf0c ite eq 800c72c: 2201 moveq r2, #1 800c72e: f04f 32ff movne.w r2, #4294967295 ; 0xffffffff 800c732: 608a str r2, [r1, #8] 800c734: 2700 movs r7, #0 800c736: 6822 ldr r2, [r4, #0] 800c738: f8df 908c ldr.w r9, [pc, #140] ; 800c7c8 <_scanf_chars+0xb0> 800c73c: 06d1 lsls r1, r2, #27 800c73e: bf5f itttt pl 800c740: 681a ldrpl r2, [r3, #0] 800c742: 1d11 addpl r1, r2, #4 800c744: 6019 strpl r1, [r3, #0] 800c746: 6816 ldrpl r6, [r2, #0] 800c748: 69a0 ldr r0, [r4, #24] 800c74a: b188 cbz r0, 800c770 <_scanf_chars+0x58> 800c74c: 2801 cmp r0, #1 800c74e: d107 bne.n 800c760 <_scanf_chars+0x48> 800c750: 682b ldr r3, [r5, #0] 800c752: 781a ldrb r2, [r3, #0] 800c754: 6963 ldr r3, [r4, #20] 800c756: 5c9b ldrb r3, [r3, r2] 800c758: b953 cbnz r3, 800c770 <_scanf_chars+0x58> 800c75a: 2f00 cmp r7, #0 800c75c: d031 beq.n 800c7c2 <_scanf_chars+0xaa> 800c75e: e022 b.n 800c7a6 <_scanf_chars+0x8e> 800c760: 2802 cmp r0, #2 800c762: d120 bne.n 800c7a6 <_scanf_chars+0x8e> 800c764: 682b ldr r3, [r5, #0] 800c766: 781b ldrb r3, [r3, #0] 800c768: f813 3009 ldrb.w r3, [r3, r9] 800c76c: 071b lsls r3, r3, #28 800c76e: d41a bmi.n 800c7a6 <_scanf_chars+0x8e> 800c770: 6823 ldr r3, [r4, #0] 800c772: 3701 adds r7, #1 800c774: 06da lsls r2, r3, #27 800c776: bf5e ittt pl 800c778: 682b ldrpl r3, [r5, #0] 800c77a: 781b ldrbpl r3, [r3, #0] 800c77c: f806 3b01 strbpl.w r3, [r6], #1 800c780: 682a ldr r2, [r5, #0] 800c782: 686b ldr r3, [r5, #4] 800c784: 3201 adds r2, #1 800c786: 602a str r2, [r5, #0] 800c788: 68a2 ldr r2, [r4, #8] 800c78a: 3b01 subs r3, #1 800c78c: 3a01 subs r2, #1 800c78e: 606b str r3, [r5, #4] 800c790: 60a2 str r2, [r4, #8] 800c792: b142 cbz r2, 800c7a6 <_scanf_chars+0x8e> 800c794: 2b00 cmp r3, #0 800c796: dcd7 bgt.n 800c748 <_scanf_chars+0x30> 800c798: 4629 mov r1, r5 800c79a: 4640 mov r0, r8 800c79c: f8d4 3180 ldr.w r3, [r4, #384] ; 0x180 800c7a0: 4798 blx r3 800c7a2: 2800 cmp r0, #0 800c7a4: d0d0 beq.n 800c748 <_scanf_chars+0x30> 800c7a6: 6823 ldr r3, [r4, #0] 800c7a8: f013 0310 ands.w r3, r3, #16 800c7ac: d105 bne.n 800c7ba <_scanf_chars+0xa2> 800c7ae: 68e2 ldr r2, [r4, #12] 800c7b0: 3201 adds r2, #1 800c7b2: 60e2 str r2, [r4, #12] 800c7b4: 69a2 ldr r2, [r4, #24] 800c7b6: b102 cbz r2, 800c7ba <_scanf_chars+0xa2> 800c7b8: 7033 strb r3, [r6, #0] 800c7ba: 2000 movs r0, #0 800c7bc: 6923 ldr r3, [r4, #16] 800c7be: 443b add r3, r7 800c7c0: 6123 str r3, [r4, #16] 800c7c2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 800c7c6: bf00 nop 800c7c8: 0800d6ce .word 0x0800d6ce 0800c7cc <_scanf_i>: 800c7cc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800c7d0: 460c mov r4, r1 800c7d2: 4698 mov r8, r3 800c7d4: 4b75 ldr r3, [pc, #468] ; (800c9ac <_scanf_i+0x1e0>) 800c7d6: b087 sub sp, #28 800c7d8: 4682 mov sl, r0 800c7da: 4616 mov r6, r2 800c7dc: e893 0007 ldmia.w r3, {r0, r1, r2} 800c7e0: ab03 add r3, sp, #12 800c7e2: e883 0007 stmia.w r3, {r0, r1, r2} 800c7e6: 4b72 ldr r3, [pc, #456] ; (800c9b0 <_scanf_i+0x1e4>) 800c7e8: 69a1 ldr r1, [r4, #24] 800c7ea: 4a72 ldr r2, [pc, #456] ; (800c9b4 <_scanf_i+0x1e8>) 800c7ec: 4627 mov r7, r4 800c7ee: 2903 cmp r1, #3 800c7f0: bf18 it ne 800c7f2: 461a movne r2, r3 800c7f4: 68a3 ldr r3, [r4, #8] 800c7f6: 9201 str r2, [sp, #4] 800c7f8: 1e5a subs r2, r3, #1 800c7fa: f5b2 7fae cmp.w r2, #348 ; 0x15c 800c7fe: bf81 itttt hi 800c800: f46f 75ae mvnhi.w r5, #348 ; 0x15c 800c804: eb03 0905 addhi.w r9, r3, r5 800c808: f240 135d movwhi r3, #349 ; 0x15d 800c80c: 60a3 strhi r3, [r4, #8] 800c80e: f857 3b1c ldr.w r3, [r7], #28 800c812: bf98 it ls 800c814: f04f 0900 movls.w r9, #0 800c818: 463d mov r5, r7 800c81a: f04f 0b00 mov.w fp, #0 800c81e: f443 6350 orr.w r3, r3, #3328 ; 0xd00 800c822: 6023 str r3, [r4, #0] 800c824: 6831 ldr r1, [r6, #0] 800c826: ab03 add r3, sp, #12 800c828: 2202 movs r2, #2 800c82a: 7809 ldrb r1, [r1, #0] 800c82c: f853 002b ldr.w r0, [r3, fp, lsl #2] 800c830: f7fe fef4 bl 800b61c 800c834: b328 cbz r0, 800c882 <_scanf_i+0xb6> 800c836: f1bb 0f01 cmp.w fp, #1 800c83a: d159 bne.n 800c8f0 <_scanf_i+0x124> 800c83c: 6862 ldr r2, [r4, #4] 800c83e: b92a cbnz r2, 800c84c <_scanf_i+0x80> 800c840: 2308 movs r3, #8 800c842: 6822 ldr r2, [r4, #0] 800c844: 6063 str r3, [r4, #4] 800c846: f442 7200 orr.w r2, r2, #512 ; 0x200 800c84a: 6022 str r2, [r4, #0] 800c84c: 6822 ldr r2, [r4, #0] 800c84e: f422 62a0 bic.w r2, r2, #1280 ; 0x500 800c852: 6022 str r2, [r4, #0] 800c854: 68a2 ldr r2, [r4, #8] 800c856: 1e51 subs r1, r2, #1 800c858: 60a1 str r1, [r4, #8] 800c85a: b192 cbz r2, 800c882 <_scanf_i+0xb6> 800c85c: 6832 ldr r2, [r6, #0] 800c85e: 1c51 adds r1, r2, #1 800c860: 6031 str r1, [r6, #0] 800c862: 7812 ldrb r2, [r2, #0] 800c864: f805 2b01 strb.w r2, [r5], #1 800c868: 6872 ldr r2, [r6, #4] 800c86a: 3a01 subs r2, #1 800c86c: 2a00 cmp r2, #0 800c86e: 6072 str r2, [r6, #4] 800c870: dc07 bgt.n 800c882 <_scanf_i+0xb6> 800c872: 4631 mov r1, r6 800c874: 4650 mov r0, sl 800c876: f8d4 2180 ldr.w r2, [r4, #384] ; 0x180 800c87a: 4790 blx r2 800c87c: 2800 cmp r0, #0 800c87e: f040 8085 bne.w 800c98c <_scanf_i+0x1c0> 800c882: f10b 0b01 add.w fp, fp, #1 800c886: f1bb 0f03 cmp.w fp, #3 800c88a: d1cb bne.n 800c824 <_scanf_i+0x58> 800c88c: 6863 ldr r3, [r4, #4] 800c88e: b90b cbnz r3, 800c894 <_scanf_i+0xc8> 800c890: 230a movs r3, #10 800c892: 6063 str r3, [r4, #4] 800c894: 6863 ldr r3, [r4, #4] 800c896: 4948 ldr r1, [pc, #288] ; (800c9b8 <_scanf_i+0x1ec>) 800c898: 6960 ldr r0, [r4, #20] 800c89a: 1ac9 subs r1, r1, r3 800c89c: f000 f8a0 bl 800c9e0 <__sccl> 800c8a0: f04f 0b00 mov.w fp, #0 800c8a4: 68a3 ldr r3, [r4, #8] 800c8a6: 6822 ldr r2, [r4, #0] 800c8a8: 2b00 cmp r3, #0 800c8aa: d03d beq.n 800c928 <_scanf_i+0x15c> 800c8ac: 6831 ldr r1, [r6, #0] 800c8ae: 6960 ldr r0, [r4, #20] 800c8b0: f891 c000 ldrb.w ip, [r1] 800c8b4: f810 000c ldrb.w r0, [r0, ip] 800c8b8: 2800 cmp r0, #0 800c8ba: d035 beq.n 800c928 <_scanf_i+0x15c> 800c8bc: f1bc 0f30 cmp.w ip, #48 ; 0x30 800c8c0: d124 bne.n 800c90c <_scanf_i+0x140> 800c8c2: 0510 lsls r0, r2, #20 800c8c4: d522 bpl.n 800c90c <_scanf_i+0x140> 800c8c6: f10b 0b01 add.w fp, fp, #1 800c8ca: f1b9 0f00 cmp.w r9, #0 800c8ce: d003 beq.n 800c8d8 <_scanf_i+0x10c> 800c8d0: 3301 adds r3, #1 800c8d2: f109 39ff add.w r9, r9, #4294967295 ; 0xffffffff 800c8d6: 60a3 str r3, [r4, #8] 800c8d8: 6873 ldr r3, [r6, #4] 800c8da: 3b01 subs r3, #1 800c8dc: 2b00 cmp r3, #0 800c8de: 6073 str r3, [r6, #4] 800c8e0: dd1b ble.n 800c91a <_scanf_i+0x14e> 800c8e2: 6833 ldr r3, [r6, #0] 800c8e4: 3301 adds r3, #1 800c8e6: 6033 str r3, [r6, #0] 800c8e8: 68a3 ldr r3, [r4, #8] 800c8ea: 3b01 subs r3, #1 800c8ec: 60a3 str r3, [r4, #8] 800c8ee: e7d9 b.n 800c8a4 <_scanf_i+0xd8> 800c8f0: f1bb 0f02 cmp.w fp, #2 800c8f4: d1ae bne.n 800c854 <_scanf_i+0x88> 800c8f6: 6822 ldr r2, [r4, #0] 800c8f8: f402 61c0 and.w r1, r2, #1536 ; 0x600 800c8fc: f5b1 7f00 cmp.w r1, #512 ; 0x200 800c900: d1bf bne.n 800c882 <_scanf_i+0xb6> 800c902: 2310 movs r3, #16 800c904: f442 7280 orr.w r2, r2, #256 ; 0x100 800c908: 6063 str r3, [r4, #4] 800c90a: e7a2 b.n 800c852 <_scanf_i+0x86> 800c90c: f422 6210 bic.w r2, r2, #2304 ; 0x900 800c910: 6022 str r2, [r4, #0] 800c912: 780b ldrb r3, [r1, #0] 800c914: f805 3b01 strb.w r3, [r5], #1 800c918: e7de b.n 800c8d8 <_scanf_i+0x10c> 800c91a: 4631 mov r1, r6 800c91c: 4650 mov r0, sl 800c91e: f8d4 3180 ldr.w r3, [r4, #384] ; 0x180 800c922: 4798 blx r3 800c924: 2800 cmp r0, #0 800c926: d0df beq.n 800c8e8 <_scanf_i+0x11c> 800c928: 6823 ldr r3, [r4, #0] 800c92a: 05db lsls r3, r3, #23 800c92c: d50d bpl.n 800c94a <_scanf_i+0x17e> 800c92e: 42bd cmp r5, r7 800c930: d909 bls.n 800c946 <_scanf_i+0x17a> 800c932: f815 1c01 ldrb.w r1, [r5, #-1] 800c936: 4632 mov r2, r6 800c938: 4650 mov r0, sl 800c93a: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c 800c93e: f105 39ff add.w r9, r5, #4294967295 ; 0xffffffff 800c942: 4798 blx r3 800c944: 464d mov r5, r9 800c946: 42bd cmp r5, r7 800c948: d02d beq.n 800c9a6 <_scanf_i+0x1da> 800c94a: 6822 ldr r2, [r4, #0] 800c94c: f012 0210 ands.w r2, r2, #16 800c950: d113 bne.n 800c97a <_scanf_i+0x1ae> 800c952: 702a strb r2, [r5, #0] 800c954: 4639 mov r1, r7 800c956: 6863 ldr r3, [r4, #4] 800c958: 4650 mov r0, sl 800c95a: 9e01 ldr r6, [sp, #4] 800c95c: 47b0 blx r6 800c95e: 6821 ldr r1, [r4, #0] 800c960: f8d8 3000 ldr.w r3, [r8] 800c964: f011 0f20 tst.w r1, #32 800c968: d013 beq.n 800c992 <_scanf_i+0x1c6> 800c96a: 1d1a adds r2, r3, #4 800c96c: f8c8 2000 str.w r2, [r8] 800c970: 681b ldr r3, [r3, #0] 800c972: 6018 str r0, [r3, #0] 800c974: 68e3 ldr r3, [r4, #12] 800c976: 3301 adds r3, #1 800c978: 60e3 str r3, [r4, #12] 800c97a: 2000 movs r0, #0 800c97c: 1bed subs r5, r5, r7 800c97e: 44ab add fp, r5 800c980: 6925 ldr r5, [r4, #16] 800c982: 445d add r5, fp 800c984: 6125 str r5, [r4, #16] 800c986: b007 add sp, #28 800c988: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800c98c: f04f 0b00 mov.w fp, #0 800c990: e7ca b.n 800c928 <_scanf_i+0x15c> 800c992: 1d1a adds r2, r3, #4 800c994: f8c8 2000 str.w r2, [r8] 800c998: 681b ldr r3, [r3, #0] 800c99a: f011 0f01 tst.w r1, #1 800c99e: bf14 ite ne 800c9a0: 8018 strhne r0, [r3, #0] 800c9a2: 6018 streq r0, [r3, #0] 800c9a4: e7e6 b.n 800c974 <_scanf_i+0x1a8> 800c9a6: 2001 movs r0, #1 800c9a8: e7ed b.n 800c986 <_scanf_i+0x1ba> 800c9aa: bf00 nop 800c9ac: 0800d288 .word 0x0800d288 800c9b0: 0800c201 .word 0x0800c201 800c9b4: 0800cbd1 .word 0x0800cbd1 800c9b8: 0800d7f1 .word 0x0800d7f1 0800c9bc <_read_r>: 800c9bc: b538 push {r3, r4, r5, lr} 800c9be: 4604 mov r4, r0 800c9c0: 4608 mov r0, r1 800c9c2: 4611 mov r1, r2 800c9c4: 2200 movs r2, #0 800c9c6: 4d05 ldr r5, [pc, #20] ; (800c9dc <_read_r+0x20>) 800c9c8: 602a str r2, [r5, #0] 800c9ca: 461a mov r2, r3 800c9cc: f7f8 fa4f bl 8004e6e <_read> 800c9d0: 1c43 adds r3, r0, #1 800c9d2: d102 bne.n 800c9da <_read_r+0x1e> 800c9d4: 682b ldr r3, [r5, #0] 800c9d6: b103 cbz r3, 800c9da <_read_r+0x1e> 800c9d8: 6023 str r3, [r4, #0] 800c9da: bd38 pop {r3, r4, r5, pc} 800c9dc: 200033cc .word 0x200033cc 0800c9e0 <__sccl>: 800c9e0: b570 push {r4, r5, r6, lr} 800c9e2: 780b ldrb r3, [r1, #0] 800c9e4: 4604 mov r4, r0 800c9e6: 2b5e cmp r3, #94 ; 0x5e 800c9e8: bf13 iteet ne 800c9ea: 2200 movne r2, #0 800c9ec: 2201 moveq r2, #1 800c9ee: 784b ldrbeq r3, [r1, #1] 800c9f0: 1c48 addne r0, r1, #1 800c9f2: bf08 it eq 800c9f4: 1c88 addeq r0, r1, #2 800c9f6: f104 05ff add.w r5, r4, #255 ; 0xff 800c9fa: 1e61 subs r1, r4, #1 800c9fc: f801 2f01 strb.w r2, [r1, #1]! 800ca00: 42a9 cmp r1, r5 800ca02: d1fb bne.n 800c9fc <__sccl+0x1c> 800ca04: b90b cbnz r3, 800ca0a <__sccl+0x2a> 800ca06: 3801 subs r0, #1 800ca08: bd70 pop {r4, r5, r6, pc} 800ca0a: f082 0201 eor.w r2, r2, #1 800ca0e: 4605 mov r5, r0 800ca10: 54e2 strb r2, [r4, r3] 800ca12: 4628 mov r0, r5 800ca14: f810 1b01 ldrb.w r1, [r0], #1 800ca18: 292d cmp r1, #45 ; 0x2d 800ca1a: d006 beq.n 800ca2a <__sccl+0x4a> 800ca1c: 295d cmp r1, #93 ; 0x5d 800ca1e: d0f3 beq.n 800ca08 <__sccl+0x28> 800ca20: b909 cbnz r1, 800ca26 <__sccl+0x46> 800ca22: 4628 mov r0, r5 800ca24: e7f0 b.n 800ca08 <__sccl+0x28> 800ca26: 460b mov r3, r1 800ca28: e7f1 b.n 800ca0e <__sccl+0x2e> 800ca2a: 786e ldrb r6, [r5, #1] 800ca2c: 2e5d cmp r6, #93 ; 0x5d 800ca2e: d0fa beq.n 800ca26 <__sccl+0x46> 800ca30: 42b3 cmp r3, r6 800ca32: dcf8 bgt.n 800ca26 <__sccl+0x46> 800ca34: 4619 mov r1, r3 800ca36: 3502 adds r5, #2 800ca38: 3101 adds r1, #1 800ca3a: 428e cmp r6, r1 800ca3c: 5462 strb r2, [r4, r1] 800ca3e: dcfb bgt.n 800ca38 <__sccl+0x58> 800ca40: 1af1 subs r1, r6, r3 800ca42: 3901 subs r1, #1 800ca44: 42b3 cmp r3, r6 800ca46: bfa8 it ge 800ca48: 2100 movge r1, #0 800ca4a: 1c58 adds r0, r3, #1 800ca4c: 1843 adds r3, r0, r1 800ca4e: e7e0 b.n 800ca12 <__sccl+0x32> 0800ca50 <_raise_r>: 800ca50: 291f cmp r1, #31 800ca52: b538 push {r3, r4, r5, lr} 800ca54: 4604 mov r4, r0 800ca56: 460d mov r5, r1 800ca58: d904 bls.n 800ca64 <_raise_r+0x14> 800ca5a: 2316 movs r3, #22 800ca5c: 6003 str r3, [r0, #0] 800ca5e: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800ca62: bd38 pop {r3, r4, r5, pc} 800ca64: 6c42 ldr r2, [r0, #68] ; 0x44 800ca66: b112 cbz r2, 800ca6e <_raise_r+0x1e> 800ca68: f852 3021 ldr.w r3, [r2, r1, lsl #2] 800ca6c: b94b cbnz r3, 800ca82 <_raise_r+0x32> 800ca6e: 4620 mov r0, r4 800ca70: f000 f830 bl 800cad4 <_getpid_r> 800ca74: 462a mov r2, r5 800ca76: 4601 mov r1, r0 800ca78: 4620 mov r0, r4 800ca7a: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 800ca7e: f000 b817 b.w 800cab0 <_kill_r> 800ca82: 2b01 cmp r3, #1 800ca84: d00a beq.n 800ca9c <_raise_r+0x4c> 800ca86: 1c59 adds r1, r3, #1 800ca88: d103 bne.n 800ca92 <_raise_r+0x42> 800ca8a: 2316 movs r3, #22 800ca8c: 6003 str r3, [r0, #0] 800ca8e: 2001 movs r0, #1 800ca90: e7e7 b.n 800ca62 <_raise_r+0x12> 800ca92: 2400 movs r4, #0 800ca94: 4628 mov r0, r5 800ca96: f842 4025 str.w r4, [r2, r5, lsl #2] 800ca9a: 4798 blx r3 800ca9c: 2000 movs r0, #0 800ca9e: e7e0 b.n 800ca62 <_raise_r+0x12> 0800caa0 : 800caa0: 4b02 ldr r3, [pc, #8] ; (800caac ) 800caa2: 4601 mov r1, r0 800caa4: 6818 ldr r0, [r3, #0] 800caa6: f7ff bfd3 b.w 800ca50 <_raise_r> 800caaa: bf00 nop 800caac: 20000014 .word 0x20000014 0800cab0 <_kill_r>: 800cab0: b538 push {r3, r4, r5, lr} 800cab2: 2300 movs r3, #0 800cab4: 4d06 ldr r5, [pc, #24] ; (800cad0 <_kill_r+0x20>) 800cab6: 4604 mov r4, r0 800cab8: 4608 mov r0, r1 800caba: 4611 mov r1, r2 800cabc: 602b str r3, [r5, #0] 800cabe: f7f8 f9bc bl 8004e3a <_kill> 800cac2: 1c43 adds r3, r0, #1 800cac4: d102 bne.n 800cacc <_kill_r+0x1c> 800cac6: 682b ldr r3, [r5, #0] 800cac8: b103 cbz r3, 800cacc <_kill_r+0x1c> 800caca: 6023 str r3, [r4, #0] 800cacc: bd38 pop {r3, r4, r5, pc} 800cace: bf00 nop 800cad0: 200033cc .word 0x200033cc 0800cad4 <_getpid_r>: 800cad4: f7f8 b9aa b.w 8004e2c <_getpid> 0800cad8 <_strtol_l.constprop.0>: 800cad8: 2b01 cmp r3, #1 800cada: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800cade: 4680 mov r8, r0 800cae0: d001 beq.n 800cae6 <_strtol_l.constprop.0+0xe> 800cae2: 2b24 cmp r3, #36 ; 0x24 800cae4: d906 bls.n 800caf4 <_strtol_l.constprop.0+0x1c> 800cae6: f7fc f96d bl 8008dc4 <__errno> 800caea: 2316 movs r3, #22 800caec: 6003 str r3, [r0, #0] 800caee: 2000 movs r0, #0 800caf0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800caf4: 460d mov r5, r1 800caf6: 4f35 ldr r7, [pc, #212] ; (800cbcc <_strtol_l.constprop.0+0xf4>) 800caf8: 4628 mov r0, r5 800cafa: f815 4b01 ldrb.w r4, [r5], #1 800cafe: 5de6 ldrb r6, [r4, r7] 800cb00: f016 0608 ands.w r6, r6, #8 800cb04: d1f8 bne.n 800caf8 <_strtol_l.constprop.0+0x20> 800cb06: 2c2d cmp r4, #45 ; 0x2d 800cb08: d12f bne.n 800cb6a <_strtol_l.constprop.0+0x92> 800cb0a: 2601 movs r6, #1 800cb0c: 782c ldrb r4, [r5, #0] 800cb0e: 1c85 adds r5, r0, #2 800cb10: 2b00 cmp r3, #0 800cb12: d057 beq.n 800cbc4 <_strtol_l.constprop.0+0xec> 800cb14: 2b10 cmp r3, #16 800cb16: d109 bne.n 800cb2c <_strtol_l.constprop.0+0x54> 800cb18: 2c30 cmp r4, #48 ; 0x30 800cb1a: d107 bne.n 800cb2c <_strtol_l.constprop.0+0x54> 800cb1c: 7828 ldrb r0, [r5, #0] 800cb1e: f000 00df and.w r0, r0, #223 ; 0xdf 800cb22: 2858 cmp r0, #88 ; 0x58 800cb24: d149 bne.n 800cbba <_strtol_l.constprop.0+0xe2> 800cb26: 2310 movs r3, #16 800cb28: 786c ldrb r4, [r5, #1] 800cb2a: 3502 adds r5, #2 800cb2c: 2700 movs r7, #0 800cb2e: f106 4e00 add.w lr, r6, #2147483648 ; 0x80000000 800cb32: f10e 3eff add.w lr, lr, #4294967295 ; 0xffffffff 800cb36: fbbe f9f3 udiv r9, lr, r3 800cb3a: 4638 mov r0, r7 800cb3c: fb03 ea19 mls sl, r3, r9, lr 800cb40: f1a4 0c30 sub.w ip, r4, #48 ; 0x30 800cb44: f1bc 0f09 cmp.w ip, #9 800cb48: d814 bhi.n 800cb74 <_strtol_l.constprop.0+0x9c> 800cb4a: 4664 mov r4, ip 800cb4c: 42a3 cmp r3, r4 800cb4e: dd22 ble.n 800cb96 <_strtol_l.constprop.0+0xbe> 800cb50: 2f00 cmp r7, #0 800cb52: db1d blt.n 800cb90 <_strtol_l.constprop.0+0xb8> 800cb54: 4581 cmp r9, r0 800cb56: d31b bcc.n 800cb90 <_strtol_l.constprop.0+0xb8> 800cb58: d101 bne.n 800cb5e <_strtol_l.constprop.0+0x86> 800cb5a: 45a2 cmp sl, r4 800cb5c: db18 blt.n 800cb90 <_strtol_l.constprop.0+0xb8> 800cb5e: 2701 movs r7, #1 800cb60: fb00 4003 mla r0, r0, r3, r4 800cb64: f815 4b01 ldrb.w r4, [r5], #1 800cb68: e7ea b.n 800cb40 <_strtol_l.constprop.0+0x68> 800cb6a: 2c2b cmp r4, #43 ; 0x2b 800cb6c: bf04 itt eq 800cb6e: 782c ldrbeq r4, [r5, #0] 800cb70: 1c85 addeq r5, r0, #2 800cb72: e7cd b.n 800cb10 <_strtol_l.constprop.0+0x38> 800cb74: f1a4 0c41 sub.w ip, r4, #65 ; 0x41 800cb78: f1bc 0f19 cmp.w ip, #25 800cb7c: d801 bhi.n 800cb82 <_strtol_l.constprop.0+0xaa> 800cb7e: 3c37 subs r4, #55 ; 0x37 800cb80: e7e4 b.n 800cb4c <_strtol_l.constprop.0+0x74> 800cb82: f1a4 0c61 sub.w ip, r4, #97 ; 0x61 800cb86: f1bc 0f19 cmp.w ip, #25 800cb8a: d804 bhi.n 800cb96 <_strtol_l.constprop.0+0xbe> 800cb8c: 3c57 subs r4, #87 ; 0x57 800cb8e: e7dd b.n 800cb4c <_strtol_l.constprop.0+0x74> 800cb90: f04f 37ff mov.w r7, #4294967295 ; 0xffffffff 800cb94: e7e6 b.n 800cb64 <_strtol_l.constprop.0+0x8c> 800cb96: 2f00 cmp r7, #0 800cb98: da07 bge.n 800cbaa <_strtol_l.constprop.0+0xd2> 800cb9a: 2322 movs r3, #34 ; 0x22 800cb9c: 4670 mov r0, lr 800cb9e: f8c8 3000 str.w r3, [r8] 800cba2: 2a00 cmp r2, #0 800cba4: d0a4 beq.n 800caf0 <_strtol_l.constprop.0+0x18> 800cba6: 1e69 subs r1, r5, #1 800cba8: e005 b.n 800cbb6 <_strtol_l.constprop.0+0xde> 800cbaa: b106 cbz r6, 800cbae <_strtol_l.constprop.0+0xd6> 800cbac: 4240 negs r0, r0 800cbae: 2a00 cmp r2, #0 800cbb0: d09e beq.n 800caf0 <_strtol_l.constprop.0+0x18> 800cbb2: 2f00 cmp r7, #0 800cbb4: d1f7 bne.n 800cba6 <_strtol_l.constprop.0+0xce> 800cbb6: 6011 str r1, [r2, #0] 800cbb8: e79a b.n 800caf0 <_strtol_l.constprop.0+0x18> 800cbba: 2430 movs r4, #48 ; 0x30 800cbbc: 2b00 cmp r3, #0 800cbbe: d1b5 bne.n 800cb2c <_strtol_l.constprop.0+0x54> 800cbc0: 2308 movs r3, #8 800cbc2: e7b3 b.n 800cb2c <_strtol_l.constprop.0+0x54> 800cbc4: 2c30 cmp r4, #48 ; 0x30 800cbc6: d0a9 beq.n 800cb1c <_strtol_l.constprop.0+0x44> 800cbc8: 230a movs r3, #10 800cbca: e7af b.n 800cb2c <_strtol_l.constprop.0+0x54> 800cbcc: 0800d6ce .word 0x0800d6ce 0800cbd0 <_strtol_r>: 800cbd0: f7ff bf82 b.w 800cad8 <_strtol_l.constprop.0> 0800cbd4 <__submore>: 800cbd4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800cbd8: 460c mov r4, r1 800cbda: 6b49 ldr r1, [r1, #52] ; 0x34 800cbdc: f104 0344 add.w r3, r4, #68 ; 0x44 800cbe0: 4299 cmp r1, r3 800cbe2: d11b bne.n 800cc1c <__submore+0x48> 800cbe4: f44f 6180 mov.w r1, #1024 ; 0x400 800cbe8: f7fc fb80 bl 80092ec <_malloc_r> 800cbec: b918 cbnz r0, 800cbf6 <__submore+0x22> 800cbee: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800cbf2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800cbf6: f44f 6380 mov.w r3, #1024 ; 0x400 800cbfa: 63a3 str r3, [r4, #56] ; 0x38 800cbfc: f894 3046 ldrb.w r3, [r4, #70] ; 0x46 800cc00: 6360 str r0, [r4, #52] ; 0x34 800cc02: f880 33ff strb.w r3, [r0, #1023] ; 0x3ff 800cc06: f894 3045 ldrb.w r3, [r4, #69] ; 0x45 800cc0a: f200 30fd addw r0, r0, #1021 ; 0x3fd 800cc0e: 7043 strb r3, [r0, #1] 800cc10: f894 3044 ldrb.w r3, [r4, #68] ; 0x44 800cc14: 7003 strb r3, [r0, #0] 800cc16: 6020 str r0, [r4, #0] 800cc18: 2000 movs r0, #0 800cc1a: e7ea b.n 800cbf2 <__submore+0x1e> 800cc1c: 6ba6 ldr r6, [r4, #56] ; 0x38 800cc1e: 0077 lsls r7, r6, #1 800cc20: 463a mov r2, r7 800cc22: f7ff fb75 bl 800c310 <_realloc_r> 800cc26: 4605 mov r5, r0 800cc28: 2800 cmp r0, #0 800cc2a: d0e0 beq.n 800cbee <__submore+0x1a> 800cc2c: eb00 0806 add.w r8, r0, r6 800cc30: 4601 mov r1, r0 800cc32: 4632 mov r2, r6 800cc34: 4640 mov r0, r8 800cc36: f7fc fadb bl 80091f0 800cc3a: e9c4 570d strd r5, r7, [r4, #52] ; 0x34 800cc3e: f8c4 8000 str.w r8, [r4] 800cc42: e7e9 b.n 800cc18 <__submore+0x44> 0800cc44 <__ascii_wctomb>: 800cc44: 4603 mov r3, r0 800cc46: 4608 mov r0, r1 800cc48: b141 cbz r1, 800cc5c <__ascii_wctomb+0x18> 800cc4a: 2aff cmp r2, #255 ; 0xff 800cc4c: d904 bls.n 800cc58 <__ascii_wctomb+0x14> 800cc4e: 228a movs r2, #138 ; 0x8a 800cc50: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800cc54: 601a str r2, [r3, #0] 800cc56: 4770 bx lr 800cc58: 2001 movs r0, #1 800cc5a: 700a strb r2, [r1, #0] 800cc5c: 4770 bx lr 0800cc5e <_malloc_usable_size_r>: 800cc5e: f851 3c04 ldr.w r3, [r1, #-4] 800cc62: 1f18 subs r0, r3, #4 800cc64: 2b00 cmp r3, #0 800cc66: bfbc itt lt 800cc68: 580b ldrlt r3, [r1, r0] 800cc6a: 18c0 addlt r0, r0, r3 800cc6c: 4770 bx lr ... 0800cc70 <_init>: 800cc70: b5f8 push {r3, r4, r5, r6, r7, lr} 800cc72: bf00 nop 800cc74: bcf8 pop {r3, r4, r5, r6, r7} 800cc76: bc08 pop {r3} 800cc78: 469e mov lr, r3 800cc7a: 4770 bx lr 0800cc7c <_fini>: 800cc7c: b5f8 push {r3, r4, r5, r6, r7, lr} 800cc7e: bf00 nop 800cc80: bcf8 pop {r3, r4, r5, r6, r7} 800cc82: bc08 pop {r3} 800cc84: 469e mov lr, r3 800cc86: 4770 bx lr