CCSModuleSW30Web.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001e8 08008000 08008000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000ecac 080081e8 080081e8 000011e8 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000dcc 08016e98 08016e98 0000fe98 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08017c64 08017c64 00011258 2**0 CONTENTS 4 .ARM 00000008 08017c64 08017c64 00010c64 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 08017c6c 08017c6c 00011258 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08017c6c 08017c6c 00010c6c 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08017c70 08017c70 00010c70 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000258 20000000 08017c74 00011000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00001380 20000258 08017ecc 00011258 2**3 ALLOC 10 ._user_heap_stack 00000600 200015d8 08017ecc 000115d8 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 00011258 2**0 CONTENTS, READONLY 12 .debug_info 0001d500 00000000 00000000 00011281 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 000056e8 00000000 00000000 0002e781 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_loclists 00000f96 00000000 00000000 00033e69 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_aranges 00001740 00000000 00000000 00034e00 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_rnglists 00001225 00000000 00000000 00036540 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_macro 000263f8 00000000 00000000 00037765 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_line 0001cb03 00000000 00000000 0005db5d 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_str 000c99aa 00000000 00000000 0007a660 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .comment 00000043 00000000 00000000 0014400a 2**0 CONTENTS, READONLY 21 .debug_frame 00006dd8 00000000 00000000 00144050 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 22 .debug_line_str 0000006e 00000000 00000000 0014ae28 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080081e8 <__do_global_dtors_aux>: 80081e8: b510 push {r4, lr} 80081ea: 4c05 ldr r4, [pc, #20] @ (8008200 <__do_global_dtors_aux+0x18>) 80081ec: 7823 ldrb r3, [r4, #0] 80081ee: b933 cbnz r3, 80081fe <__do_global_dtors_aux+0x16> 80081f0: 4b04 ldr r3, [pc, #16] @ (8008204 <__do_global_dtors_aux+0x1c>) 80081f2: b113 cbz r3, 80081fa <__do_global_dtors_aux+0x12> 80081f4: 4804 ldr r0, [pc, #16] @ (8008208 <__do_global_dtors_aux+0x20>) 80081f6: f3af 8000 nop.w 80081fa: 2301 movs r3, #1 80081fc: 7023 strb r3, [r4, #0] 80081fe: bd10 pop {r4, pc} 8008200: 20000258 .word 0x20000258 8008204: 00000000 .word 0x00000000 8008208: 08016e7c .word 0x08016e7c 0800820c : 800820c: b508 push {r3, lr} 800820e: 4b03 ldr r3, [pc, #12] @ (800821c ) 8008210: b11b cbz r3, 800821a 8008212: 4903 ldr r1, [pc, #12] @ (8008220 ) 8008214: 4803 ldr r0, [pc, #12] @ (8008224 ) 8008216: f3af 8000 nop.w 800821a: bd08 pop {r3, pc} 800821c: 00000000 .word 0x00000000 8008220: 2000025c .word 0x2000025c 8008224: 08016e7c .word 0x08016e7c 08008228 : 8008228: 4603 mov r3, r0 800822a: f813 2b01 ldrb.w r2, [r3], #1 800822e: 2a00 cmp r2, #0 8008230: d1fb bne.n 800822a 8008232: 1a18 subs r0, r3, r0 8008234: 3801 subs r0, #1 8008236: 4770 bx lr 08008238 <__aeabi_drsub>: 8008238: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 800823c: e002 b.n 8008244 <__adddf3> 800823e: bf00 nop 08008240 <__aeabi_dsub>: 8008240: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 08008244 <__adddf3>: 8008244: b530 push {r4, r5, lr} 8008246: ea4f 0441 mov.w r4, r1, lsl #1 800824a: ea4f 0543 mov.w r5, r3, lsl #1 800824e: ea94 0f05 teq r4, r5 8008252: bf08 it eq 8008254: ea90 0f02 teqeq r0, r2 8008258: bf1f itttt ne 800825a: ea54 0c00 orrsne.w ip, r4, r0 800825e: ea55 0c02 orrsne.w ip, r5, r2 8008262: ea7f 5c64 mvnsne.w ip, r4, asr #21 8008266: ea7f 5c65 mvnsne.w ip, r5, asr #21 800826a: f000 80e2 beq.w 8008432 <__adddf3+0x1ee> 800826e: ea4f 5454 mov.w r4, r4, lsr #21 8008272: ebd4 5555 rsbs r5, r4, r5, lsr #21 8008276: bfb8 it lt 8008278: 426d neglt r5, r5 800827a: dd0c ble.n 8008296 <__adddf3+0x52> 800827c: 442c add r4, r5 800827e: ea80 0202 eor.w r2, r0, r2 8008282: ea81 0303 eor.w r3, r1, r3 8008286: ea82 0000 eor.w r0, r2, r0 800828a: ea83 0101 eor.w r1, r3, r1 800828e: ea80 0202 eor.w r2, r0, r2 8008292: ea81 0303 eor.w r3, r1, r3 8008296: 2d36 cmp r5, #54 @ 0x36 8008298: bf88 it hi 800829a: bd30 pophi {r4, r5, pc} 800829c: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 80082a0: ea4f 3101 mov.w r1, r1, lsl #12 80082a4: f44f 1c80 mov.w ip, #1048576 @ 0x100000 80082a8: ea4c 3111 orr.w r1, ip, r1, lsr #12 80082ac: d002 beq.n 80082b4 <__adddf3+0x70> 80082ae: 4240 negs r0, r0 80082b0: eb61 0141 sbc.w r1, r1, r1, lsl #1 80082b4: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 80082b8: ea4f 3303 mov.w r3, r3, lsl #12 80082bc: ea4c 3313 orr.w r3, ip, r3, lsr #12 80082c0: d002 beq.n 80082c8 <__adddf3+0x84> 80082c2: 4252 negs r2, r2 80082c4: eb63 0343 sbc.w r3, r3, r3, lsl #1 80082c8: ea94 0f05 teq r4, r5 80082cc: f000 80a7 beq.w 800841e <__adddf3+0x1da> 80082d0: f1a4 0401 sub.w r4, r4, #1 80082d4: f1d5 0e20 rsbs lr, r5, #32 80082d8: db0d blt.n 80082f6 <__adddf3+0xb2> 80082da: fa02 fc0e lsl.w ip, r2, lr 80082de: fa22 f205 lsr.w r2, r2, r5 80082e2: 1880 adds r0, r0, r2 80082e4: f141 0100 adc.w r1, r1, #0 80082e8: fa03 f20e lsl.w r2, r3, lr 80082ec: 1880 adds r0, r0, r2 80082ee: fa43 f305 asr.w r3, r3, r5 80082f2: 4159 adcs r1, r3 80082f4: e00e b.n 8008314 <__adddf3+0xd0> 80082f6: f1a5 0520 sub.w r5, r5, #32 80082fa: f10e 0e20 add.w lr, lr, #32 80082fe: 2a01 cmp r2, #1 8008300: fa03 fc0e lsl.w ip, r3, lr 8008304: bf28 it cs 8008306: f04c 0c02 orrcs.w ip, ip, #2 800830a: fa43 f305 asr.w r3, r3, r5 800830e: 18c0 adds r0, r0, r3 8008310: eb51 71e3 adcs.w r1, r1, r3, asr #31 8008314: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008318: d507 bpl.n 800832a <__adddf3+0xe6> 800831a: f04f 0e00 mov.w lr, #0 800831e: f1dc 0c00 rsbs ip, ip, #0 8008322: eb7e 0000 sbcs.w r0, lr, r0 8008326: eb6e 0101 sbc.w r1, lr, r1 800832a: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 800832e: d31b bcc.n 8008368 <__adddf3+0x124> 8008330: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 8008334: d30c bcc.n 8008350 <__adddf3+0x10c> 8008336: 0849 lsrs r1, r1, #1 8008338: ea5f 0030 movs.w r0, r0, rrx 800833c: ea4f 0c3c mov.w ip, ip, rrx 8008340: f104 0401 add.w r4, r4, #1 8008344: ea4f 5244 mov.w r2, r4, lsl #21 8008348: f512 0f80 cmn.w r2, #4194304 @ 0x400000 800834c: f080 809a bcs.w 8008484 <__adddf3+0x240> 8008350: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008354: bf08 it eq 8008356: ea5f 0c50 movseq.w ip, r0, lsr #1 800835a: f150 0000 adcs.w r0, r0, #0 800835e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008362: ea41 0105 orr.w r1, r1, r5 8008366: bd30 pop {r4, r5, pc} 8008368: ea5f 0c4c movs.w ip, ip, lsl #1 800836c: 4140 adcs r0, r0 800836e: eb41 0101 adc.w r1, r1, r1 8008372: 3c01 subs r4, #1 8008374: bf28 it cs 8008376: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 800837a: d2e9 bcs.n 8008350 <__adddf3+0x10c> 800837c: f091 0f00 teq r1, #0 8008380: bf04 itt eq 8008382: 4601 moveq r1, r0 8008384: 2000 moveq r0, #0 8008386: fab1 f381 clz r3, r1 800838a: bf08 it eq 800838c: 3320 addeq r3, #32 800838e: f1a3 030b sub.w r3, r3, #11 8008392: f1b3 0220 subs.w r2, r3, #32 8008396: da0c bge.n 80083b2 <__adddf3+0x16e> 8008398: 320c adds r2, #12 800839a: dd08 ble.n 80083ae <__adddf3+0x16a> 800839c: f102 0c14 add.w ip, r2, #20 80083a0: f1c2 020c rsb r2, r2, #12 80083a4: fa01 f00c lsl.w r0, r1, ip 80083a8: fa21 f102 lsr.w r1, r1, r2 80083ac: e00c b.n 80083c8 <__adddf3+0x184> 80083ae: f102 0214 add.w r2, r2, #20 80083b2: bfd8 it le 80083b4: f1c2 0c20 rsble ip, r2, #32 80083b8: fa01 f102 lsl.w r1, r1, r2 80083bc: fa20 fc0c lsr.w ip, r0, ip 80083c0: bfdc itt le 80083c2: ea41 010c orrle.w r1, r1, ip 80083c6: 4090 lslle r0, r2 80083c8: 1ae4 subs r4, r4, r3 80083ca: bfa2 ittt ge 80083cc: eb01 5104 addge.w r1, r1, r4, lsl #20 80083d0: 4329 orrge r1, r5 80083d2: bd30 popge {r4, r5, pc} 80083d4: ea6f 0404 mvn.w r4, r4 80083d8: 3c1f subs r4, #31 80083da: da1c bge.n 8008416 <__adddf3+0x1d2> 80083dc: 340c adds r4, #12 80083de: dc0e bgt.n 80083fe <__adddf3+0x1ba> 80083e0: f104 0414 add.w r4, r4, #20 80083e4: f1c4 0220 rsb r2, r4, #32 80083e8: fa20 f004 lsr.w r0, r0, r4 80083ec: fa01 f302 lsl.w r3, r1, r2 80083f0: ea40 0003 orr.w r0, r0, r3 80083f4: fa21 f304 lsr.w r3, r1, r4 80083f8: ea45 0103 orr.w r1, r5, r3 80083fc: bd30 pop {r4, r5, pc} 80083fe: f1c4 040c rsb r4, r4, #12 8008402: f1c4 0220 rsb r2, r4, #32 8008406: fa20 f002 lsr.w r0, r0, r2 800840a: fa01 f304 lsl.w r3, r1, r4 800840e: ea40 0003 orr.w r0, r0, r3 8008412: 4629 mov r1, r5 8008414: bd30 pop {r4, r5, pc} 8008416: fa21 f004 lsr.w r0, r1, r4 800841a: 4629 mov r1, r5 800841c: bd30 pop {r4, r5, pc} 800841e: f094 0f00 teq r4, #0 8008422: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 8008426: bf06 itte eq 8008428: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 800842c: 3401 addeq r4, #1 800842e: 3d01 subne r5, #1 8008430: e74e b.n 80082d0 <__adddf3+0x8c> 8008432: ea7f 5c64 mvns.w ip, r4, asr #21 8008436: bf18 it ne 8008438: ea7f 5c65 mvnsne.w ip, r5, asr #21 800843c: d029 beq.n 8008492 <__adddf3+0x24e> 800843e: ea94 0f05 teq r4, r5 8008442: bf08 it eq 8008444: ea90 0f02 teqeq r0, r2 8008448: d005 beq.n 8008456 <__adddf3+0x212> 800844a: ea54 0c00 orrs.w ip, r4, r0 800844e: bf04 itt eq 8008450: 4619 moveq r1, r3 8008452: 4610 moveq r0, r2 8008454: bd30 pop {r4, r5, pc} 8008456: ea91 0f03 teq r1, r3 800845a: bf1e ittt ne 800845c: 2100 movne r1, #0 800845e: 2000 movne r0, #0 8008460: bd30 popne {r4, r5, pc} 8008462: ea5f 5c54 movs.w ip, r4, lsr #21 8008466: d105 bne.n 8008474 <__adddf3+0x230> 8008468: 0040 lsls r0, r0, #1 800846a: 4149 adcs r1, r1 800846c: bf28 it cs 800846e: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 8008472: bd30 pop {r4, r5, pc} 8008474: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 8008478: bf3c itt cc 800847a: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 800847e: bd30 popcc {r4, r5, pc} 8008480: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008484: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 8008488: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 800848c: f04f 0000 mov.w r0, #0 8008490: bd30 pop {r4, r5, pc} 8008492: ea7f 5c64 mvns.w ip, r4, asr #21 8008496: bf1a itte ne 8008498: 4619 movne r1, r3 800849a: 4610 movne r0, r2 800849c: ea7f 5c65 mvnseq.w ip, r5, asr #21 80084a0: bf1c itt ne 80084a2: 460b movne r3, r1 80084a4: 4602 movne r2, r0 80084a6: ea50 3401 orrs.w r4, r0, r1, lsl #12 80084aa: bf06 itte eq 80084ac: ea52 3503 orrseq.w r5, r2, r3, lsl #12 80084b0: ea91 0f03 teqeq r1, r3 80084b4: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 80084b8: bd30 pop {r4, r5, pc} 80084ba: bf00 nop 080084bc <__aeabi_ui2d>: 80084bc: f090 0f00 teq r0, #0 80084c0: bf04 itt eq 80084c2: 2100 moveq r1, #0 80084c4: 4770 bxeq lr 80084c6: b530 push {r4, r5, lr} 80084c8: f44f 6480 mov.w r4, #1024 @ 0x400 80084cc: f104 0432 add.w r4, r4, #50 @ 0x32 80084d0: f04f 0500 mov.w r5, #0 80084d4: f04f 0100 mov.w r1, #0 80084d8: e750 b.n 800837c <__adddf3+0x138> 80084da: bf00 nop 080084dc <__aeabi_i2d>: 80084dc: f090 0f00 teq r0, #0 80084e0: bf04 itt eq 80084e2: 2100 moveq r1, #0 80084e4: 4770 bxeq lr 80084e6: b530 push {r4, r5, lr} 80084e8: f44f 6480 mov.w r4, #1024 @ 0x400 80084ec: f104 0432 add.w r4, r4, #50 @ 0x32 80084f0: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 80084f4: bf48 it mi 80084f6: 4240 negmi r0, r0 80084f8: f04f 0100 mov.w r1, #0 80084fc: e73e b.n 800837c <__adddf3+0x138> 80084fe: bf00 nop 08008500 <__aeabi_f2d>: 8008500: 0042 lsls r2, r0, #1 8008502: ea4f 01e2 mov.w r1, r2, asr #3 8008506: ea4f 0131 mov.w r1, r1, rrx 800850a: ea4f 7002 mov.w r0, r2, lsl #28 800850e: bf1f itttt ne 8008510: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 8008514: f093 4f7f teqne r3, #4278190080 @ 0xff000000 8008518: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 800851c: 4770 bxne lr 800851e: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 8008522: bf08 it eq 8008524: 4770 bxeq lr 8008526: f093 4f7f teq r3, #4278190080 @ 0xff000000 800852a: bf04 itt eq 800852c: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 8008530: 4770 bxeq lr 8008532: b530 push {r4, r5, lr} 8008534: f44f 7460 mov.w r4, #896 @ 0x380 8008538: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 800853c: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 8008540: e71c b.n 800837c <__adddf3+0x138> 8008542: bf00 nop 08008544 <__aeabi_ul2d>: 8008544: ea50 0201 orrs.w r2, r0, r1 8008548: bf08 it eq 800854a: 4770 bxeq lr 800854c: b530 push {r4, r5, lr} 800854e: f04f 0500 mov.w r5, #0 8008552: e00a b.n 800856a <__aeabi_l2d+0x16> 08008554 <__aeabi_l2d>: 8008554: ea50 0201 orrs.w r2, r0, r1 8008558: bf08 it eq 800855a: 4770 bxeq lr 800855c: b530 push {r4, r5, lr} 800855e: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 8008562: d502 bpl.n 800856a <__aeabi_l2d+0x16> 8008564: 4240 negs r0, r0 8008566: eb61 0141 sbc.w r1, r1, r1, lsl #1 800856a: f44f 6480 mov.w r4, #1024 @ 0x400 800856e: f104 0432 add.w r4, r4, #50 @ 0x32 8008572: ea5f 5c91 movs.w ip, r1, lsr #22 8008576: f43f aed8 beq.w 800832a <__adddf3+0xe6> 800857a: f04f 0203 mov.w r2, #3 800857e: ea5f 0cdc movs.w ip, ip, lsr #3 8008582: bf18 it ne 8008584: 3203 addne r2, #3 8008586: ea5f 0cdc movs.w ip, ip, lsr #3 800858a: bf18 it ne 800858c: 3203 addne r2, #3 800858e: eb02 02dc add.w r2, r2, ip, lsr #3 8008592: f1c2 0320 rsb r3, r2, #32 8008596: fa00 fc03 lsl.w ip, r0, r3 800859a: fa20 f002 lsr.w r0, r0, r2 800859e: fa01 fe03 lsl.w lr, r1, r3 80085a2: ea40 000e orr.w r0, r0, lr 80085a6: fa21 f102 lsr.w r1, r1, r2 80085aa: 4414 add r4, r2 80085ac: e6bd b.n 800832a <__adddf3+0xe6> 80085ae: bf00 nop 080085b0 <__aeabi_dmul>: 80085b0: b570 push {r4, r5, r6, lr} 80085b2: f04f 0cff mov.w ip, #255 @ 0xff 80085b6: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 80085ba: ea1c 5411 ands.w r4, ip, r1, lsr #20 80085be: bf1d ittte ne 80085c0: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80085c4: ea94 0f0c teqne r4, ip 80085c8: ea95 0f0c teqne r5, ip 80085cc: f000 f8de bleq 800878c <__aeabi_dmul+0x1dc> 80085d0: 442c add r4, r5 80085d2: ea81 0603 eor.w r6, r1, r3 80085d6: ea21 514c bic.w r1, r1, ip, lsl #21 80085da: ea23 534c bic.w r3, r3, ip, lsl #21 80085de: ea50 3501 orrs.w r5, r0, r1, lsl #12 80085e2: bf18 it ne 80085e4: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80085e8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 80085ec: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80085f0: d038 beq.n 8008664 <__aeabi_dmul+0xb4> 80085f2: fba0 ce02 umull ip, lr, r0, r2 80085f6: f04f 0500 mov.w r5, #0 80085fa: fbe1 e502 umlal lr, r5, r1, r2 80085fe: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 8008602: fbe0 e503 umlal lr, r5, r0, r3 8008606: f04f 0600 mov.w r6, #0 800860a: fbe1 5603 umlal r5, r6, r1, r3 800860e: f09c 0f00 teq ip, #0 8008612: bf18 it ne 8008614: f04e 0e01 orrne.w lr, lr, #1 8008618: f1a4 04ff sub.w r4, r4, #255 @ 0xff 800861c: f5b6 7f00 cmp.w r6, #512 @ 0x200 8008620: f564 7440 sbc.w r4, r4, #768 @ 0x300 8008624: d204 bcs.n 8008630 <__aeabi_dmul+0x80> 8008626: ea5f 0e4e movs.w lr, lr, lsl #1 800862a: 416d adcs r5, r5 800862c: eb46 0606 adc.w r6, r6, r6 8008630: ea42 21c6 orr.w r1, r2, r6, lsl #11 8008634: ea41 5155 orr.w r1, r1, r5, lsr #21 8008638: ea4f 20c5 mov.w r0, r5, lsl #11 800863c: ea40 505e orr.w r0, r0, lr, lsr #21 8008640: ea4f 2ece mov.w lr, lr, lsl #11 8008644: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008648: bf88 it hi 800864a: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800864e: d81e bhi.n 800868e <__aeabi_dmul+0xde> 8008650: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 8008654: bf08 it eq 8008656: ea5f 0e50 movseq.w lr, r0, lsr #1 800865a: f150 0000 adcs.w r0, r0, #0 800865e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008662: bd70 pop {r4, r5, r6, pc} 8008664: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 8008668: ea46 0101 orr.w r1, r6, r1 800866c: ea40 0002 orr.w r0, r0, r2 8008670: ea81 0103 eor.w r1, r1, r3 8008674: ebb4 045c subs.w r4, r4, ip, lsr #1 8008678: bfc2 ittt gt 800867a: ebd4 050c rsbsgt r5, r4, ip 800867e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8008682: bd70 popgt {r4, r5, r6, pc} 8008684: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008688: f04f 0e00 mov.w lr, #0 800868c: 3c01 subs r4, #1 800868e: f300 80ab bgt.w 80087e8 <__aeabi_dmul+0x238> 8008692: f114 0f36 cmn.w r4, #54 @ 0x36 8008696: bfde ittt le 8008698: 2000 movle r0, #0 800869a: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 800869e: bd70 pople {r4, r5, r6, pc} 80086a0: f1c4 0400 rsb r4, r4, #0 80086a4: 3c20 subs r4, #32 80086a6: da35 bge.n 8008714 <__aeabi_dmul+0x164> 80086a8: 340c adds r4, #12 80086aa: dc1b bgt.n 80086e4 <__aeabi_dmul+0x134> 80086ac: f104 0414 add.w r4, r4, #20 80086b0: f1c4 0520 rsb r5, r4, #32 80086b4: fa00 f305 lsl.w r3, r0, r5 80086b8: fa20 f004 lsr.w r0, r0, r4 80086bc: fa01 f205 lsl.w r2, r1, r5 80086c0: ea40 0002 orr.w r0, r0, r2 80086c4: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 80086c8: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 80086cc: eb10 70d3 adds.w r0, r0, r3, lsr #31 80086d0: fa21 f604 lsr.w r6, r1, r4 80086d4: eb42 0106 adc.w r1, r2, r6 80086d8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80086dc: bf08 it eq 80086de: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80086e2: bd70 pop {r4, r5, r6, pc} 80086e4: f1c4 040c rsb r4, r4, #12 80086e8: f1c4 0520 rsb r5, r4, #32 80086ec: fa00 f304 lsl.w r3, r0, r4 80086f0: fa20 f005 lsr.w r0, r0, r5 80086f4: fa01 f204 lsl.w r2, r1, r4 80086f8: ea40 0002 orr.w r0, r0, r2 80086fc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008700: eb10 70d3 adds.w r0, r0, r3, lsr #31 8008704: f141 0100 adc.w r1, r1, #0 8008708: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800870c: bf08 it eq 800870e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8008712: bd70 pop {r4, r5, r6, pc} 8008714: f1c4 0520 rsb r5, r4, #32 8008718: fa00 f205 lsl.w r2, r0, r5 800871c: ea4e 0e02 orr.w lr, lr, r2 8008720: fa20 f304 lsr.w r3, r0, r4 8008724: fa01 f205 lsl.w r2, r1, r5 8008728: ea43 0302 orr.w r3, r3, r2 800872c: fa21 f004 lsr.w r0, r1, r4 8008730: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008734: fa21 f204 lsr.w r2, r1, r4 8008738: ea20 0002 bic.w r0, r0, r2 800873c: eb00 70d3 add.w r0, r0, r3, lsr #31 8008740: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8008744: bf08 it eq 8008746: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800874a: bd70 pop {r4, r5, r6, pc} 800874c: f094 0f00 teq r4, #0 8008750: d10f bne.n 8008772 <__aeabi_dmul+0x1c2> 8008752: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 8008756: 0040 lsls r0, r0, #1 8008758: eb41 0101 adc.w r1, r1, r1 800875c: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008760: bf08 it eq 8008762: 3c01 subeq r4, #1 8008764: d0f7 beq.n 8008756 <__aeabi_dmul+0x1a6> 8008766: ea41 0106 orr.w r1, r1, r6 800876a: f095 0f00 teq r5, #0 800876e: bf18 it ne 8008770: 4770 bxne lr 8008772: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 8008776: 0052 lsls r2, r2, #1 8008778: eb43 0303 adc.w r3, r3, r3 800877c: f413 1f80 tst.w r3, #1048576 @ 0x100000 8008780: bf08 it eq 8008782: 3d01 subeq r5, #1 8008784: d0f7 beq.n 8008776 <__aeabi_dmul+0x1c6> 8008786: ea43 0306 orr.w r3, r3, r6 800878a: 4770 bx lr 800878c: ea94 0f0c teq r4, ip 8008790: ea0c 5513 and.w r5, ip, r3, lsr #20 8008794: bf18 it ne 8008796: ea95 0f0c teqne r5, ip 800879a: d00c beq.n 80087b6 <__aeabi_dmul+0x206> 800879c: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087a0: bf18 it ne 80087a2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087a6: d1d1 bne.n 800874c <__aeabi_dmul+0x19c> 80087a8: ea81 0103 eor.w r1, r1, r3 80087ac: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087b0: f04f 0000 mov.w r0, #0 80087b4: bd70 pop {r4, r5, r6, pc} 80087b6: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087ba: bf06 itte eq 80087bc: 4610 moveq r0, r2 80087be: 4619 moveq r1, r3 80087c0: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087c4: d019 beq.n 80087fa <__aeabi_dmul+0x24a> 80087c6: ea94 0f0c teq r4, ip 80087ca: d102 bne.n 80087d2 <__aeabi_dmul+0x222> 80087cc: ea50 3601 orrs.w r6, r0, r1, lsl #12 80087d0: d113 bne.n 80087fa <__aeabi_dmul+0x24a> 80087d2: ea95 0f0c teq r5, ip 80087d6: d105 bne.n 80087e4 <__aeabi_dmul+0x234> 80087d8: ea52 3603 orrs.w r6, r2, r3, lsl #12 80087dc: bf1c itt ne 80087de: 4610 movne r0, r2 80087e0: 4619 movne r1, r3 80087e2: d10a bne.n 80087fa <__aeabi_dmul+0x24a> 80087e4: ea81 0103 eor.w r1, r1, r3 80087e8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087ec: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087f0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 80087f4: f04f 0000 mov.w r0, #0 80087f8: bd70 pop {r4, r5, r6, pc} 80087fa: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087fe: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 8008802: bd70 pop {r4, r5, r6, pc} 08008804 <__aeabi_ddiv>: 8008804: b570 push {r4, r5, r6, lr} 8008806: f04f 0cff mov.w ip, #255 @ 0xff 800880a: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 800880e: ea1c 5411 ands.w r4, ip, r1, lsr #20 8008812: bf1d ittte ne 8008814: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8008818: ea94 0f0c teqne r4, ip 800881c: ea95 0f0c teqne r5, ip 8008820: f000 f8a7 bleq 8008972 <__aeabi_ddiv+0x16e> 8008824: eba4 0405 sub.w r4, r4, r5 8008828: ea81 0e03 eor.w lr, r1, r3 800882c: ea52 3503 orrs.w r5, r2, r3, lsl #12 8008830: ea4f 3101 mov.w r1, r1, lsl #12 8008834: f000 8088 beq.w 8008948 <__aeabi_ddiv+0x144> 8008838: ea4f 3303 mov.w r3, r3, lsl #12 800883c: f04f 5580 mov.w r5, #268435456 @ 0x10000000 8008840: ea45 1313 orr.w r3, r5, r3, lsr #4 8008844: ea43 6312 orr.w r3, r3, r2, lsr #24 8008848: ea4f 2202 mov.w r2, r2, lsl #8 800884c: ea45 1511 orr.w r5, r5, r1, lsr #4 8008850: ea45 6510 orr.w r5, r5, r0, lsr #24 8008854: ea4f 2600 mov.w r6, r0, lsl #8 8008858: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000 800885c: 429d cmp r5, r3 800885e: bf08 it eq 8008860: 4296 cmpeq r6, r2 8008862: f144 04fd adc.w r4, r4, #253 @ 0xfd 8008866: f504 7440 add.w r4, r4, #768 @ 0x300 800886a: d202 bcs.n 8008872 <__aeabi_ddiv+0x6e> 800886c: 085b lsrs r3, r3, #1 800886e: ea4f 0232 mov.w r2, r2, rrx 8008872: 1ab6 subs r6, r6, r2 8008874: eb65 0503 sbc.w r5, r5, r3 8008878: 085b lsrs r3, r3, #1 800887a: ea4f 0232 mov.w r2, r2, rrx 800887e: f44f 1080 mov.w r0, #1048576 @ 0x100000 8008882: f44f 2c00 mov.w ip, #524288 @ 0x80000 8008886: ebb6 0e02 subs.w lr, r6, r2 800888a: eb75 0e03 sbcs.w lr, r5, r3 800888e: bf22 ittt cs 8008890: 1ab6 subcs r6, r6, r2 8008892: 4675 movcs r5, lr 8008894: ea40 000c orrcs.w r0, r0, ip 8008898: 085b lsrs r3, r3, #1 800889a: ea4f 0232 mov.w r2, r2, rrx 800889e: ebb6 0e02 subs.w lr, r6, r2 80088a2: eb75 0e03 sbcs.w lr, r5, r3 80088a6: bf22 ittt cs 80088a8: 1ab6 subcs r6, r6, r2 80088aa: 4675 movcs r5, lr 80088ac: ea40 005c orrcs.w r0, r0, ip, lsr #1 80088b0: 085b lsrs r3, r3, #1 80088b2: ea4f 0232 mov.w r2, r2, rrx 80088b6: ebb6 0e02 subs.w lr, r6, r2 80088ba: eb75 0e03 sbcs.w lr, r5, r3 80088be: bf22 ittt cs 80088c0: 1ab6 subcs r6, r6, r2 80088c2: 4675 movcs r5, lr 80088c4: ea40 009c orrcs.w r0, r0, ip, lsr #2 80088c8: 085b lsrs r3, r3, #1 80088ca: ea4f 0232 mov.w r2, r2, rrx 80088ce: ebb6 0e02 subs.w lr, r6, r2 80088d2: eb75 0e03 sbcs.w lr, r5, r3 80088d6: bf22 ittt cs 80088d8: 1ab6 subcs r6, r6, r2 80088da: 4675 movcs r5, lr 80088dc: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80088e0: ea55 0e06 orrs.w lr, r5, r6 80088e4: d018 beq.n 8008918 <__aeabi_ddiv+0x114> 80088e6: ea4f 1505 mov.w r5, r5, lsl #4 80088ea: ea45 7516 orr.w r5, r5, r6, lsr #28 80088ee: ea4f 1606 mov.w r6, r6, lsl #4 80088f2: ea4f 03c3 mov.w r3, r3, lsl #3 80088f6: ea43 7352 orr.w r3, r3, r2, lsr #29 80088fa: ea4f 02c2 mov.w r2, r2, lsl #3 80088fe: ea5f 1c1c movs.w ip, ip, lsr #4 8008902: d1c0 bne.n 8008886 <__aeabi_ddiv+0x82> 8008904: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008908: d10b bne.n 8008922 <__aeabi_ddiv+0x11e> 800890a: ea41 0100 orr.w r1, r1, r0 800890e: f04f 0000 mov.w r0, #0 8008912: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000 8008916: e7b6 b.n 8008886 <__aeabi_ddiv+0x82> 8008918: f411 1f80 tst.w r1, #1048576 @ 0x100000 800891c: bf04 itt eq 800891e: 4301 orreq r1, r0 8008920: 2000 moveq r0, #0 8008922: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008926: bf88 it hi 8008928: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800892c: f63f aeaf bhi.w 800868e <__aeabi_dmul+0xde> 8008930: ebb5 0c03 subs.w ip, r5, r3 8008934: bf04 itt eq 8008936: ebb6 0c02 subseq.w ip, r6, r2 800893a: ea5f 0c50 movseq.w ip, r0, lsr #1 800893e: f150 0000 adcs.w r0, r0, #0 8008942: eb41 5104 adc.w r1, r1, r4, lsl #20 8008946: bd70 pop {r4, r5, r6, pc} 8008948: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000 800894c: ea4e 3111 orr.w r1, lr, r1, lsr #12 8008950: eb14 045c adds.w r4, r4, ip, lsr #1 8008954: bfc2 ittt gt 8008956: ebd4 050c rsbsgt r5, r4, ip 800895a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800895e: bd70 popgt {r4, r5, r6, pc} 8008960: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008964: f04f 0e00 mov.w lr, #0 8008968: 3c01 subs r4, #1 800896a: e690 b.n 800868e <__aeabi_dmul+0xde> 800896c: ea45 0e06 orr.w lr, r5, r6 8008970: e68d b.n 800868e <__aeabi_dmul+0xde> 8008972: ea0c 5513 and.w r5, ip, r3, lsr #20 8008976: ea94 0f0c teq r4, ip 800897a: bf08 it eq 800897c: ea95 0f0c teqeq r5, ip 8008980: f43f af3b beq.w 80087fa <__aeabi_dmul+0x24a> 8008984: ea94 0f0c teq r4, ip 8008988: d10a bne.n 80089a0 <__aeabi_ddiv+0x19c> 800898a: ea50 3401 orrs.w r4, r0, r1, lsl #12 800898e: f47f af34 bne.w 80087fa <__aeabi_dmul+0x24a> 8008992: ea95 0f0c teq r5, ip 8008996: f47f af25 bne.w 80087e4 <__aeabi_dmul+0x234> 800899a: 4610 mov r0, r2 800899c: 4619 mov r1, r3 800899e: e72c b.n 80087fa <__aeabi_dmul+0x24a> 80089a0: ea95 0f0c teq r5, ip 80089a4: d106 bne.n 80089b4 <__aeabi_ddiv+0x1b0> 80089a6: ea52 3503 orrs.w r5, r2, r3, lsl #12 80089aa: f43f aefd beq.w 80087a8 <__aeabi_dmul+0x1f8> 80089ae: 4610 mov r0, r2 80089b0: 4619 mov r1, r3 80089b2: e722 b.n 80087fa <__aeabi_dmul+0x24a> 80089b4: ea50 0641 orrs.w r6, r0, r1, lsl #1 80089b8: bf18 it ne 80089ba: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80089be: f47f aec5 bne.w 800874c <__aeabi_dmul+0x19c> 80089c2: ea50 0441 orrs.w r4, r0, r1, lsl #1 80089c6: f47f af0d bne.w 80087e4 <__aeabi_dmul+0x234> 80089ca: ea52 0543 orrs.w r5, r2, r3, lsl #1 80089ce: f47f aeeb bne.w 80087a8 <__aeabi_dmul+0x1f8> 80089d2: e712 b.n 80087fa <__aeabi_dmul+0x24a> 080089d4 <__gedf2>: 80089d4: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80089d8: e006 b.n 80089e8 <__cmpdf2+0x4> 80089da: bf00 nop 080089dc <__ledf2>: 80089dc: f04f 0c01 mov.w ip, #1 80089e0: e002 b.n 80089e8 <__cmpdf2+0x4> 80089e2: bf00 nop 080089e4 <__cmpdf2>: 80089e4: f04f 0c01 mov.w ip, #1 80089e8: f84d cd04 str.w ip, [sp, #-4]! 80089ec: ea4f 0c41 mov.w ip, r1, lsl #1 80089f0: ea7f 5c6c mvns.w ip, ip, asr #21 80089f4: ea4f 0c43 mov.w ip, r3, lsl #1 80089f8: bf18 it ne 80089fa: ea7f 5c6c mvnsne.w ip, ip, asr #21 80089fe: d01b beq.n 8008a38 <__cmpdf2+0x54> 8008a00: b001 add sp, #4 8008a02: ea50 0c41 orrs.w ip, r0, r1, lsl #1 8008a06: bf0c ite eq 8008a08: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 8008a0c: ea91 0f03 teqne r1, r3 8008a10: bf02 ittt eq 8008a12: ea90 0f02 teqeq r0, r2 8008a16: 2000 moveq r0, #0 8008a18: 4770 bxeq lr 8008a1a: f110 0f00 cmn.w r0, #0 8008a1e: ea91 0f03 teq r1, r3 8008a22: bf58 it pl 8008a24: 4299 cmppl r1, r3 8008a26: bf08 it eq 8008a28: 4290 cmpeq r0, r2 8008a2a: bf2c ite cs 8008a2c: 17d8 asrcs r0, r3, #31 8008a2e: ea6f 70e3 mvncc.w r0, r3, asr #31 8008a32: f040 0001 orr.w r0, r0, #1 8008a36: 4770 bx lr 8008a38: ea4f 0c41 mov.w ip, r1, lsl #1 8008a3c: ea7f 5c6c mvns.w ip, ip, asr #21 8008a40: d102 bne.n 8008a48 <__cmpdf2+0x64> 8008a42: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8008a46: d107 bne.n 8008a58 <__cmpdf2+0x74> 8008a48: ea4f 0c43 mov.w ip, r3, lsl #1 8008a4c: ea7f 5c6c mvns.w ip, ip, asr #21 8008a50: d1d6 bne.n 8008a00 <__cmpdf2+0x1c> 8008a52: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8008a56: d0d3 beq.n 8008a00 <__cmpdf2+0x1c> 8008a58: f85d 0b04 ldr.w r0, [sp], #4 8008a5c: 4770 bx lr 8008a5e: bf00 nop 08008a60 <__aeabi_cdrcmple>: 8008a60: 4684 mov ip, r0 8008a62: 4610 mov r0, r2 8008a64: 4662 mov r2, ip 8008a66: 468c mov ip, r1 8008a68: 4619 mov r1, r3 8008a6a: 4663 mov r3, ip 8008a6c: e000 b.n 8008a70 <__aeabi_cdcmpeq> 8008a6e: bf00 nop 08008a70 <__aeabi_cdcmpeq>: 8008a70: b501 push {r0, lr} 8008a72: f7ff ffb7 bl 80089e4 <__cmpdf2> 8008a76: 2800 cmp r0, #0 8008a78: bf48 it mi 8008a7a: f110 0f00 cmnmi.w r0, #0 8008a7e: bd01 pop {r0, pc} 08008a80 <__aeabi_dcmpeq>: 8008a80: f84d ed08 str.w lr, [sp, #-8]! 8008a84: f7ff fff4 bl 8008a70 <__aeabi_cdcmpeq> 8008a88: bf0c ite eq 8008a8a: 2001 moveq r0, #1 8008a8c: 2000 movne r0, #0 8008a8e: f85d fb08 ldr.w pc, [sp], #8 8008a92: bf00 nop 08008a94 <__aeabi_dcmplt>: 8008a94: f84d ed08 str.w lr, [sp, #-8]! 8008a98: f7ff ffea bl 8008a70 <__aeabi_cdcmpeq> 8008a9c: bf34 ite cc 8008a9e: 2001 movcc r0, #1 8008aa0: 2000 movcs r0, #0 8008aa2: f85d fb08 ldr.w pc, [sp], #8 8008aa6: bf00 nop 08008aa8 <__aeabi_dcmple>: 8008aa8: f84d ed08 str.w lr, [sp, #-8]! 8008aac: f7ff ffe0 bl 8008a70 <__aeabi_cdcmpeq> 8008ab0: bf94 ite ls 8008ab2: 2001 movls r0, #1 8008ab4: 2000 movhi r0, #0 8008ab6: f85d fb08 ldr.w pc, [sp], #8 8008aba: bf00 nop 08008abc <__aeabi_dcmpge>: 8008abc: f84d ed08 str.w lr, [sp, #-8]! 8008ac0: f7ff ffce bl 8008a60 <__aeabi_cdrcmple> 8008ac4: bf94 ite ls 8008ac6: 2001 movls r0, #1 8008ac8: 2000 movhi r0, #0 8008aca: f85d fb08 ldr.w pc, [sp], #8 8008ace: bf00 nop 08008ad0 <__aeabi_dcmpgt>: 8008ad0: f84d ed08 str.w lr, [sp, #-8]! 8008ad4: f7ff ffc4 bl 8008a60 <__aeabi_cdrcmple> 8008ad8: bf34 ite cc 8008ada: 2001 movcc r0, #1 8008adc: 2000 movcs r0, #0 8008ade: f85d fb08 ldr.w pc, [sp], #8 8008ae2: bf00 nop 08008ae4 <__aeabi_dcmpun>: 8008ae4: ea4f 0c41 mov.w ip, r1, lsl #1 8008ae8: ea7f 5c6c mvns.w ip, ip, asr #21 8008aec: d102 bne.n 8008af4 <__aeabi_dcmpun+0x10> 8008aee: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8008af2: d10a bne.n 8008b0a <__aeabi_dcmpun+0x26> 8008af4: ea4f 0c43 mov.w ip, r3, lsl #1 8008af8: ea7f 5c6c mvns.w ip, ip, asr #21 8008afc: d102 bne.n 8008b04 <__aeabi_dcmpun+0x20> 8008afe: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8008b02: d102 bne.n 8008b0a <__aeabi_dcmpun+0x26> 8008b04: f04f 0000 mov.w r0, #0 8008b08: 4770 bx lr 8008b0a: f04f 0001 mov.w r0, #1 8008b0e: 4770 bx lr 08008b10 <__aeabi_d2iz>: 8008b10: ea4f 0241 mov.w r2, r1, lsl #1 8008b14: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 8008b18: d215 bcs.n 8008b46 <__aeabi_d2iz+0x36> 8008b1a: d511 bpl.n 8008b40 <__aeabi_d2iz+0x30> 8008b1c: f46f 7378 mvn.w r3, #992 @ 0x3e0 8008b20: ebb3 5262 subs.w r2, r3, r2, asr #21 8008b24: d912 bls.n 8008b4c <__aeabi_d2iz+0x3c> 8008b26: ea4f 23c1 mov.w r3, r1, lsl #11 8008b2a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8008b2e: ea43 5350 orr.w r3, r3, r0, lsr #21 8008b32: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008b36: fa23 f002 lsr.w r0, r3, r2 8008b3a: bf18 it ne 8008b3c: 4240 negne r0, r0 8008b3e: 4770 bx lr 8008b40: f04f 0000 mov.w r0, #0 8008b44: 4770 bx lr 8008b46: ea50 3001 orrs.w r0, r0, r1, lsl #12 8008b4a: d105 bne.n 8008b58 <__aeabi_d2iz+0x48> 8008b4c: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000 8008b50: bf08 it eq 8008b52: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 8008b56: 4770 bx lr 8008b58: f04f 0000 mov.w r0, #0 8008b5c: 4770 bx lr 8008b5e: bf00 nop 08008b60 <__aeabi_d2f>: 8008b60: ea4f 0241 mov.w r2, r1, lsl #1 8008b64: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000 8008b68: bf24 itt cs 8008b6a: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000 8008b6e: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000 8008b72: d90d bls.n 8008b90 <__aeabi_d2f+0x30> 8008b74: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008b78: ea4f 02c0 mov.w r2, r0, lsl #3 8008b7c: ea4c 7050 orr.w r0, ip, r0, lsr #29 8008b80: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000 8008b84: eb40 0083 adc.w r0, r0, r3, lsl #2 8008b88: bf08 it eq 8008b8a: f020 0001 biceq.w r0, r0, #1 8008b8e: 4770 bx lr 8008b90: f011 4f80 tst.w r1, #1073741824 @ 0x40000000 8008b94: d121 bne.n 8008bda <__aeabi_d2f+0x7a> 8008b96: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000 8008b9a: bfbc itt lt 8008b9c: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000 8008ba0: 4770 bxlt lr 8008ba2: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008ba6: ea4f 5252 mov.w r2, r2, lsr #21 8008baa: f1c2 0218 rsb r2, r2, #24 8008bae: f1c2 0c20 rsb ip, r2, #32 8008bb2: fa10 f30c lsls.w r3, r0, ip 8008bb6: fa20 f002 lsr.w r0, r0, r2 8008bba: bf18 it ne 8008bbc: f040 0001 orrne.w r0, r0, #1 8008bc0: ea4f 23c1 mov.w r3, r1, lsl #11 8008bc4: ea4f 23d3 mov.w r3, r3, lsr #11 8008bc8: fa03 fc0c lsl.w ip, r3, ip 8008bcc: ea40 000c orr.w r0, r0, ip 8008bd0: fa23 f302 lsr.w r3, r3, r2 8008bd4: ea4f 0343 mov.w r3, r3, lsl #1 8008bd8: e7cc b.n 8008b74 <__aeabi_d2f+0x14> 8008bda: ea7f 5362 mvns.w r3, r2, asr #21 8008bde: d107 bne.n 8008bf0 <__aeabi_d2f+0x90> 8008be0: ea50 3301 orrs.w r3, r0, r1, lsl #12 8008be4: bf1e ittt ne 8008be6: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000 8008bea: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000 8008bee: 4770 bxne lr 8008bf0: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000 8008bf4: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008bf8: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008bfc: 4770 bx lr 8008bfe: bf00 nop 08008c00 <__aeabi_frsub>: 8008c00: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000 8008c04: e002 b.n 8008c0c <__addsf3> 8008c06: bf00 nop 08008c08 <__aeabi_fsub>: 8008c08: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 08008c0c <__addsf3>: 8008c0c: 0042 lsls r2, r0, #1 8008c0e: bf1f itttt ne 8008c10: ea5f 0341 movsne.w r3, r1, lsl #1 8008c14: ea92 0f03 teqne r2, r3 8008c18: ea7f 6c22 mvnsne.w ip, r2, asr #24 8008c1c: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008c20: d06a beq.n 8008cf8 <__addsf3+0xec> 8008c22: ea4f 6212 mov.w r2, r2, lsr #24 8008c26: ebd2 6313 rsbs r3, r2, r3, lsr #24 8008c2a: bfc1 itttt gt 8008c2c: 18d2 addgt r2, r2, r3 8008c2e: 4041 eorgt r1, r0 8008c30: 4048 eorgt r0, r1 8008c32: 4041 eorgt r1, r0 8008c34: bfb8 it lt 8008c36: 425b neglt r3, r3 8008c38: 2b19 cmp r3, #25 8008c3a: bf88 it hi 8008c3c: 4770 bxhi lr 8008c3e: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 8008c42: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008c46: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000 8008c4a: bf18 it ne 8008c4c: 4240 negne r0, r0 8008c4e: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008c52: f441 0100 orr.w r1, r1, #8388608 @ 0x800000 8008c56: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000 8008c5a: bf18 it ne 8008c5c: 4249 negne r1, r1 8008c5e: ea92 0f03 teq r2, r3 8008c62: d03f beq.n 8008ce4 <__addsf3+0xd8> 8008c64: f1a2 0201 sub.w r2, r2, #1 8008c68: fa41 fc03 asr.w ip, r1, r3 8008c6c: eb10 000c adds.w r0, r0, ip 8008c70: f1c3 0320 rsb r3, r3, #32 8008c74: fa01 f103 lsl.w r1, r1, r3 8008c78: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008c7c: d502 bpl.n 8008c84 <__addsf3+0x78> 8008c7e: 4249 negs r1, r1 8008c80: eb60 0040 sbc.w r0, r0, r0, lsl #1 8008c84: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000 8008c88: d313 bcc.n 8008cb2 <__addsf3+0xa6> 8008c8a: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000 8008c8e: d306 bcc.n 8008c9e <__addsf3+0x92> 8008c90: 0840 lsrs r0, r0, #1 8008c92: ea4f 0131 mov.w r1, r1, rrx 8008c96: f102 0201 add.w r2, r2, #1 8008c9a: 2afe cmp r2, #254 @ 0xfe 8008c9c: d251 bcs.n 8008d42 <__addsf3+0x136> 8008c9e: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000 8008ca2: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008ca6: bf08 it eq 8008ca8: f020 0001 biceq.w r0, r0, #1 8008cac: ea40 0003 orr.w r0, r0, r3 8008cb0: 4770 bx lr 8008cb2: 0049 lsls r1, r1, #1 8008cb4: eb40 0000 adc.w r0, r0, r0 8008cb8: 3a01 subs r2, #1 8008cba: bf28 it cs 8008cbc: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000 8008cc0: d2ed bcs.n 8008c9e <__addsf3+0x92> 8008cc2: fab0 fc80 clz ip, r0 8008cc6: f1ac 0c08 sub.w ip, ip, #8 8008cca: ebb2 020c subs.w r2, r2, ip 8008cce: fa00 f00c lsl.w r0, r0, ip 8008cd2: bfaa itet ge 8008cd4: eb00 50c2 addge.w r0, r0, r2, lsl #23 8008cd8: 4252 neglt r2, r2 8008cda: 4318 orrge r0, r3 8008cdc: bfbc itt lt 8008cde: 40d0 lsrlt r0, r2 8008ce0: 4318 orrlt r0, r3 8008ce2: 4770 bx lr 8008ce4: f092 0f00 teq r2, #0 8008ce8: f481 0100 eor.w r1, r1, #8388608 @ 0x800000 8008cec: bf06 itte eq 8008cee: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000 8008cf2: 3201 addeq r2, #1 8008cf4: 3b01 subne r3, #1 8008cf6: e7b5 b.n 8008c64 <__addsf3+0x58> 8008cf8: ea4f 0341 mov.w r3, r1, lsl #1 8008cfc: ea7f 6c22 mvns.w ip, r2, asr #24 8008d00: bf18 it ne 8008d02: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008d06: d021 beq.n 8008d4c <__addsf3+0x140> 8008d08: ea92 0f03 teq r2, r3 8008d0c: d004 beq.n 8008d18 <__addsf3+0x10c> 8008d0e: f092 0f00 teq r2, #0 8008d12: bf08 it eq 8008d14: 4608 moveq r0, r1 8008d16: 4770 bx lr 8008d18: ea90 0f01 teq r0, r1 8008d1c: bf1c itt ne 8008d1e: 2000 movne r0, #0 8008d20: 4770 bxne lr 8008d22: f012 4f7f tst.w r2, #4278190080 @ 0xff000000 8008d26: d104 bne.n 8008d32 <__addsf3+0x126> 8008d28: 0040 lsls r0, r0, #1 8008d2a: bf28 it cs 8008d2c: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000 8008d30: 4770 bx lr 8008d32: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000 8008d36: bf3c itt cc 8008d38: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000 8008d3c: 4770 bxcc lr 8008d3e: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008d42: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000 8008d46: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008d4a: 4770 bx lr 8008d4c: ea7f 6222 mvns.w r2, r2, asr #24 8008d50: bf16 itet ne 8008d52: 4608 movne r0, r1 8008d54: ea7f 6323 mvnseq.w r3, r3, asr #24 8008d58: 4601 movne r1, r0 8008d5a: 0242 lsls r2, r0, #9 8008d5c: bf06 itte eq 8008d5e: ea5f 2341 movseq.w r3, r1, lsl #9 8008d62: ea90 0f01 teqeq r0, r1 8008d66: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000 8008d6a: 4770 bx lr 08008d6c <__aeabi_ui2f>: 8008d6c: f04f 0300 mov.w r3, #0 8008d70: e004 b.n 8008d7c <__aeabi_i2f+0x8> 8008d72: bf00 nop 08008d74 <__aeabi_i2f>: 8008d74: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000 8008d78: bf48 it mi 8008d7a: 4240 negmi r0, r0 8008d7c: ea5f 0c00 movs.w ip, r0 8008d80: bf08 it eq 8008d82: 4770 bxeq lr 8008d84: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000 8008d88: 4601 mov r1, r0 8008d8a: f04f 0000 mov.w r0, #0 8008d8e: e01c b.n 8008dca <__aeabi_l2f+0x2a> 08008d90 <__aeabi_ul2f>: 8008d90: ea50 0201 orrs.w r2, r0, r1 8008d94: bf08 it eq 8008d96: 4770 bxeq lr 8008d98: f04f 0300 mov.w r3, #0 8008d9c: e00a b.n 8008db4 <__aeabi_l2f+0x14> 8008d9e: bf00 nop 08008da0 <__aeabi_l2f>: 8008da0: ea50 0201 orrs.w r2, r0, r1 8008da4: bf08 it eq 8008da6: 4770 bxeq lr 8008da8: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000 8008dac: d502 bpl.n 8008db4 <__aeabi_l2f+0x14> 8008dae: 4240 negs r0, r0 8008db0: eb61 0141 sbc.w r1, r1, r1, lsl #1 8008db4: ea5f 0c01 movs.w ip, r1 8008db8: bf02 ittt eq 8008dba: 4684 moveq ip, r0 8008dbc: 4601 moveq r1, r0 8008dbe: 2000 moveq r0, #0 8008dc0: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000 8008dc4: bf08 it eq 8008dc6: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000 8008dca: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 8008dce: fabc f28c clz r2, ip 8008dd2: 3a08 subs r2, #8 8008dd4: eba3 53c2 sub.w r3, r3, r2, lsl #23 8008dd8: db10 blt.n 8008dfc <__aeabi_l2f+0x5c> 8008dda: fa01 fc02 lsl.w ip, r1, r2 8008dde: 4463 add r3, ip 8008de0: fa00 fc02 lsl.w ip, r0, r2 8008de4: f1c2 0220 rsb r2, r2, #32 8008de8: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008dec: fa20 f202 lsr.w r2, r0, r2 8008df0: eb43 0002 adc.w r0, r3, r2 8008df4: bf08 it eq 8008df6: f020 0001 biceq.w r0, r0, #1 8008dfa: 4770 bx lr 8008dfc: f102 0220 add.w r2, r2, #32 8008e00: fa01 fc02 lsl.w ip, r1, r2 8008e04: f1c2 0220 rsb r2, r2, #32 8008e08: ea50 004c orrs.w r0, r0, ip, lsl #1 8008e0c: fa21 f202 lsr.w r2, r1, r2 8008e10: eb43 0002 adc.w r0, r3, r2 8008e14: bf08 it eq 8008e16: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008e1a: 4770 bx lr 08008e1c <__aeabi_fmul>: 8008e1c: f04f 0cff mov.w ip, #255 @ 0xff 8008e20: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008e24: bf1e ittt ne 8008e26: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008e2a: ea92 0f0c teqne r2, ip 8008e2e: ea93 0f0c teqne r3, ip 8008e32: d06f beq.n 8008f14 <__aeabi_fmul+0xf8> 8008e34: 441a add r2, r3 8008e36: ea80 0c01 eor.w ip, r0, r1 8008e3a: 0240 lsls r0, r0, #9 8008e3c: bf18 it ne 8008e3e: ea5f 2141 movsne.w r1, r1, lsl #9 8008e42: d01e beq.n 8008e82 <__aeabi_fmul+0x66> 8008e44: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8008e48: ea43 1050 orr.w r0, r3, r0, lsr #5 8008e4c: ea43 1151 orr.w r1, r3, r1, lsr #5 8008e50: fba0 3101 umull r3, r1, r0, r1 8008e54: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008e58: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000 8008e5c: bf3e ittt cc 8008e5e: 0049 lslcc r1, r1, #1 8008e60: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 8008e64: 005b lslcc r3, r3, #1 8008e66: ea40 0001 orr.w r0, r0, r1 8008e6a: f162 027f sbc.w r2, r2, #127 @ 0x7f 8008e6e: 2afd cmp r2, #253 @ 0xfd 8008e70: d81d bhi.n 8008eae <__aeabi_fmul+0x92> 8008e72: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008e76: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008e7a: bf08 it eq 8008e7c: f020 0001 biceq.w r0, r0, #1 8008e80: 4770 bx lr 8008e82: f090 0f00 teq r0, #0 8008e86: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8008e8a: bf08 it eq 8008e8c: 0249 lsleq r1, r1, #9 8008e8e: ea4c 2050 orr.w r0, ip, r0, lsr #9 8008e92: ea40 2051 orr.w r0, r0, r1, lsr #9 8008e96: 3a7f subs r2, #127 @ 0x7f 8008e98: bfc2 ittt gt 8008e9a: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 8008e9e: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8008ea2: 4770 bxgt lr 8008ea4: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008ea8: f04f 0300 mov.w r3, #0 8008eac: 3a01 subs r2, #1 8008eae: dc5d bgt.n 8008f6c <__aeabi_fmul+0x150> 8008eb0: f112 0f19 cmn.w r2, #25 8008eb4: bfdc itt le 8008eb6: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000 8008eba: 4770 bxle lr 8008ebc: f1c2 0200 rsb r2, r2, #0 8008ec0: 0041 lsls r1, r0, #1 8008ec2: fa21 f102 lsr.w r1, r1, r2 8008ec6: f1c2 0220 rsb r2, r2, #32 8008eca: fa00 fc02 lsl.w ip, r0, r2 8008ece: ea5f 0031 movs.w r0, r1, rrx 8008ed2: f140 0000 adc.w r0, r0, #0 8008ed6: ea53 034c orrs.w r3, r3, ip, lsl #1 8008eda: bf08 it eq 8008edc: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008ee0: 4770 bx lr 8008ee2: f092 0f00 teq r2, #0 8008ee6: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8008eea: bf02 ittt eq 8008eec: 0040 lsleq r0, r0, #1 8008eee: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 8008ef2: 3a01 subeq r2, #1 8008ef4: d0f9 beq.n 8008eea <__aeabi_fmul+0xce> 8008ef6: ea40 000c orr.w r0, r0, ip 8008efa: f093 0f00 teq r3, #0 8008efe: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008f02: bf02 ittt eq 8008f04: 0049 lsleq r1, r1, #1 8008f06: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8008f0a: 3b01 subeq r3, #1 8008f0c: d0f9 beq.n 8008f02 <__aeabi_fmul+0xe6> 8008f0e: ea41 010c orr.w r1, r1, ip 8008f12: e78f b.n 8008e34 <__aeabi_fmul+0x18> 8008f14: ea0c 53d1 and.w r3, ip, r1, lsr #23 8008f18: ea92 0f0c teq r2, ip 8008f1c: bf18 it ne 8008f1e: ea93 0f0c teqne r3, ip 8008f22: d00a beq.n 8008f3a <__aeabi_fmul+0x11e> 8008f24: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 8008f28: bf18 it ne 8008f2a: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 8008f2e: d1d8 bne.n 8008ee2 <__aeabi_fmul+0xc6> 8008f30: ea80 0001 eor.w r0, r0, r1 8008f34: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008f38: 4770 bx lr 8008f3a: f090 0f00 teq r0, #0 8008f3e: bf17 itett ne 8008f40: f090 4f00 teqne r0, #2147483648 @ 0x80000000 8008f44: 4608 moveq r0, r1 8008f46: f091 0f00 teqne r1, #0 8008f4a: f091 4f00 teqne r1, #2147483648 @ 0x80000000 8008f4e: d014 beq.n 8008f7a <__aeabi_fmul+0x15e> 8008f50: ea92 0f0c teq r2, ip 8008f54: d101 bne.n 8008f5a <__aeabi_fmul+0x13e> 8008f56: 0242 lsls r2, r0, #9 8008f58: d10f bne.n 8008f7a <__aeabi_fmul+0x15e> 8008f5a: ea93 0f0c teq r3, ip 8008f5e: d103 bne.n 8008f68 <__aeabi_fmul+0x14c> 8008f60: 024b lsls r3, r1, #9 8008f62: bf18 it ne 8008f64: 4608 movne r0, r1 8008f66: d108 bne.n 8008f7a <__aeabi_fmul+0x15e> 8008f68: ea80 0001 eor.w r0, r0, r1 8008f6c: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008f70: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008f74: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008f78: 4770 bx lr 8008f7a: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008f7e: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000 8008f82: 4770 bx lr 08008f84 <__aeabi_fdiv>: 8008f84: f04f 0cff mov.w ip, #255 @ 0xff 8008f88: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008f8c: bf1e ittt ne 8008f8e: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008f92: ea92 0f0c teqne r2, ip 8008f96: ea93 0f0c teqne r3, ip 8008f9a: d069 beq.n 8009070 <__aeabi_fdiv+0xec> 8008f9c: eba2 0203 sub.w r2, r2, r3 8008fa0: ea80 0c01 eor.w ip, r0, r1 8008fa4: 0249 lsls r1, r1, #9 8008fa6: ea4f 2040 mov.w r0, r0, lsl #9 8008faa: d037 beq.n 800901c <__aeabi_fdiv+0x98> 8008fac: f04f 5380 mov.w r3, #268435456 @ 0x10000000 8008fb0: ea43 1111 orr.w r1, r3, r1, lsr #4 8008fb4: ea43 1310 orr.w r3, r3, r0, lsr #4 8008fb8: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008fbc: 428b cmp r3, r1 8008fbe: bf38 it cc 8008fc0: 005b lslcc r3, r3, #1 8008fc2: f142 027d adc.w r2, r2, #125 @ 0x7d 8008fc6: f44f 0c00 mov.w ip, #8388608 @ 0x800000 8008fca: 428b cmp r3, r1 8008fcc: bf24 itt cs 8008fce: 1a5b subcs r3, r3, r1 8008fd0: ea40 000c orrcs.w r0, r0, ip 8008fd4: ebb3 0f51 cmp.w r3, r1, lsr #1 8008fd8: bf24 itt cs 8008fda: eba3 0351 subcs.w r3, r3, r1, lsr #1 8008fde: ea40 005c orrcs.w r0, r0, ip, lsr #1 8008fe2: ebb3 0f91 cmp.w r3, r1, lsr #2 8008fe6: bf24 itt cs 8008fe8: eba3 0391 subcs.w r3, r3, r1, lsr #2 8008fec: ea40 009c orrcs.w r0, r0, ip, lsr #2 8008ff0: ebb3 0fd1 cmp.w r3, r1, lsr #3 8008ff4: bf24 itt cs 8008ff6: eba3 03d1 subcs.w r3, r3, r1, lsr #3 8008ffa: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8008ffe: 011b lsls r3, r3, #4 8009000: bf18 it ne 8009002: ea5f 1c1c movsne.w ip, ip, lsr #4 8009006: d1e0 bne.n 8008fca <__aeabi_fdiv+0x46> 8009008: 2afd cmp r2, #253 @ 0xfd 800900a: f63f af50 bhi.w 8008eae <__aeabi_fmul+0x92> 800900e: 428b cmp r3, r1 8009010: eb40 50c2 adc.w r0, r0, r2, lsl #23 8009014: bf08 it eq 8009016: f020 0001 biceq.w r0, r0, #1 800901a: 4770 bx lr 800901c: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8009020: ea4c 2050 orr.w r0, ip, r0, lsr #9 8009024: 327f adds r2, #127 @ 0x7f 8009026: bfc2 ittt gt 8009028: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 800902c: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8009030: 4770 bxgt lr 8009032: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8009036: f04f 0300 mov.w r3, #0 800903a: 3a01 subs r2, #1 800903c: e737 b.n 8008eae <__aeabi_fmul+0x92> 800903e: f092 0f00 teq r2, #0 8009042: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8009046: bf02 ittt eq 8009048: 0040 lsleq r0, r0, #1 800904a: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 800904e: 3a01 subeq r2, #1 8009050: d0f9 beq.n 8009046 <__aeabi_fdiv+0xc2> 8009052: ea40 000c orr.w r0, r0, ip 8009056: f093 0f00 teq r3, #0 800905a: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 800905e: bf02 ittt eq 8009060: 0049 lsleq r1, r1, #1 8009062: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8009066: 3b01 subeq r3, #1 8009068: d0f9 beq.n 800905e <__aeabi_fdiv+0xda> 800906a: ea41 010c orr.w r1, r1, ip 800906e: e795 b.n 8008f9c <__aeabi_fdiv+0x18> 8009070: ea0c 53d1 and.w r3, ip, r1, lsr #23 8009074: ea92 0f0c teq r2, ip 8009078: d108 bne.n 800908c <__aeabi_fdiv+0x108> 800907a: 0242 lsls r2, r0, #9 800907c: f47f af7d bne.w 8008f7a <__aeabi_fmul+0x15e> 8009080: ea93 0f0c teq r3, ip 8009084: f47f af70 bne.w 8008f68 <__aeabi_fmul+0x14c> 8009088: 4608 mov r0, r1 800908a: e776 b.n 8008f7a <__aeabi_fmul+0x15e> 800908c: ea93 0f0c teq r3, ip 8009090: d104 bne.n 800909c <__aeabi_fdiv+0x118> 8009092: 024b lsls r3, r1, #9 8009094: f43f af4c beq.w 8008f30 <__aeabi_fmul+0x114> 8009098: 4608 mov r0, r1 800909a: e76e b.n 8008f7a <__aeabi_fmul+0x15e> 800909c: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 80090a0: bf18 it ne 80090a2: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 80090a6: d1ca bne.n 800903e <__aeabi_fdiv+0xba> 80090a8: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000 80090ac: f47f af5c bne.w 8008f68 <__aeabi_fmul+0x14c> 80090b0: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000 80090b4: f47f af3c bne.w 8008f30 <__aeabi_fmul+0x114> 80090b8: e75f b.n 8008f7a <__aeabi_fmul+0x15e> 80090ba: bf00 nop 080090bc <__gesf2>: 80090bc: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80090c0: e006 b.n 80090d0 <__cmpsf2+0x4> 80090c2: bf00 nop 080090c4 <__lesf2>: 80090c4: f04f 0c01 mov.w ip, #1 80090c8: e002 b.n 80090d0 <__cmpsf2+0x4> 80090ca: bf00 nop 080090cc <__cmpsf2>: 80090cc: f04f 0c01 mov.w ip, #1 80090d0: f84d cd04 str.w ip, [sp, #-4]! 80090d4: ea4f 0240 mov.w r2, r0, lsl #1 80090d8: ea4f 0341 mov.w r3, r1, lsl #1 80090dc: ea7f 6c22 mvns.w ip, r2, asr #24 80090e0: bf18 it ne 80090e2: ea7f 6c23 mvnsne.w ip, r3, asr #24 80090e6: d011 beq.n 800910c <__cmpsf2+0x40> 80090e8: b001 add sp, #4 80090ea: ea52 0c53 orrs.w ip, r2, r3, lsr #1 80090ee: bf18 it ne 80090f0: ea90 0f01 teqne r0, r1 80090f4: bf58 it pl 80090f6: ebb2 0003 subspl.w r0, r2, r3 80090fa: bf88 it hi 80090fc: 17c8 asrhi r0, r1, #31 80090fe: bf38 it cc 8009100: ea6f 70e1 mvncc.w r0, r1, asr #31 8009104: bf18 it ne 8009106: f040 0001 orrne.w r0, r0, #1 800910a: 4770 bx lr 800910c: ea7f 6c22 mvns.w ip, r2, asr #24 8009110: d102 bne.n 8009118 <__cmpsf2+0x4c> 8009112: ea5f 2c40 movs.w ip, r0, lsl #9 8009116: d105 bne.n 8009124 <__cmpsf2+0x58> 8009118: ea7f 6c23 mvns.w ip, r3, asr #24 800911c: d1e4 bne.n 80090e8 <__cmpsf2+0x1c> 800911e: ea5f 2c41 movs.w ip, r1, lsl #9 8009122: d0e1 beq.n 80090e8 <__cmpsf2+0x1c> 8009124: f85d 0b04 ldr.w r0, [sp], #4 8009128: 4770 bx lr 800912a: bf00 nop 0800912c <__aeabi_cfrcmple>: 800912c: 4684 mov ip, r0 800912e: 4608 mov r0, r1 8009130: 4661 mov r1, ip 8009132: e7ff b.n 8009134 <__aeabi_cfcmpeq> 08009134 <__aeabi_cfcmpeq>: 8009134: b50f push {r0, r1, r2, r3, lr} 8009136: f7ff ffc9 bl 80090cc <__cmpsf2> 800913a: 2800 cmp r0, #0 800913c: bf48 it mi 800913e: f110 0f00 cmnmi.w r0, #0 8009142: bd0f pop {r0, r1, r2, r3, pc} 08009144 <__aeabi_fcmpeq>: 8009144: f84d ed08 str.w lr, [sp, #-8]! 8009148: f7ff fff4 bl 8009134 <__aeabi_cfcmpeq> 800914c: bf0c ite eq 800914e: 2001 moveq r0, #1 8009150: 2000 movne r0, #0 8009152: f85d fb08 ldr.w pc, [sp], #8 8009156: bf00 nop 08009158 <__aeabi_fcmplt>: 8009158: f84d ed08 str.w lr, [sp, #-8]! 800915c: f7ff ffea bl 8009134 <__aeabi_cfcmpeq> 8009160: bf34 ite cc 8009162: 2001 movcc r0, #1 8009164: 2000 movcs r0, #0 8009166: f85d fb08 ldr.w pc, [sp], #8 800916a: bf00 nop 0800916c <__aeabi_fcmple>: 800916c: f84d ed08 str.w lr, [sp, #-8]! 8009170: f7ff ffe0 bl 8009134 <__aeabi_cfcmpeq> 8009174: bf94 ite ls 8009176: 2001 movls r0, #1 8009178: 2000 movhi r0, #0 800917a: f85d fb08 ldr.w pc, [sp], #8 800917e: bf00 nop 08009180 <__aeabi_fcmpge>: 8009180: f84d ed08 str.w lr, [sp, #-8]! 8009184: f7ff ffd2 bl 800912c <__aeabi_cfrcmple> 8009188: bf94 ite ls 800918a: 2001 movls r0, #1 800918c: 2000 movhi r0, #0 800918e: f85d fb08 ldr.w pc, [sp], #8 8009192: bf00 nop 08009194 <__aeabi_fcmpgt>: 8009194: f84d ed08 str.w lr, [sp, #-8]! 8009198: f7ff ffc8 bl 800912c <__aeabi_cfrcmple> 800919c: bf34 ite cc 800919e: 2001 movcc r0, #1 80091a0: 2000 movcs r0, #0 80091a2: f85d fb08 ldr.w pc, [sp], #8 80091a6: bf00 nop 080091a8 <__aeabi_f2iz>: 80091a8: ea4f 0240 mov.w r2, r0, lsl #1 80091ac: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000 80091b0: d30f bcc.n 80091d2 <__aeabi_f2iz+0x2a> 80091b2: f04f 039e mov.w r3, #158 @ 0x9e 80091b6: ebb3 6212 subs.w r2, r3, r2, lsr #24 80091ba: d90d bls.n 80091d8 <__aeabi_f2iz+0x30> 80091bc: ea4f 2300 mov.w r3, r0, lsl #8 80091c0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80091c4: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 80091c8: fa23 f002 lsr.w r0, r3, r2 80091cc: bf18 it ne 80091ce: 4240 negne r0, r0 80091d0: 4770 bx lr 80091d2: f04f 0000 mov.w r0, #0 80091d6: 4770 bx lr 80091d8: f112 0f61 cmn.w r2, #97 @ 0x61 80091dc: d101 bne.n 80091e2 <__aeabi_f2iz+0x3a> 80091de: 0242 lsls r2, r0, #9 80091e0: d105 bne.n 80091ee <__aeabi_f2iz+0x46> 80091e2: f010 4000 ands.w r0, r0, #2147483648 @ 0x80000000 80091e6: bf08 it eq 80091e8: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 80091ec: 4770 bx lr 80091ee: f04f 0000 mov.w r0, #0 80091f2: 4770 bx lr 080091f4 <__aeabi_uldivmod>: 80091f4: b953 cbnz r3, 800920c <__aeabi_uldivmod+0x18> 80091f6: b94a cbnz r2, 800920c <__aeabi_uldivmod+0x18> 80091f8: 2900 cmp r1, #0 80091fa: bf08 it eq 80091fc: 2800 cmpeq r0, #0 80091fe: bf1c itt ne 8009200: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8009204: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8009208: f000 b98c b.w 8009524 <__aeabi_idiv0> 800920c: f1ad 0c08 sub.w ip, sp, #8 8009210: e96d ce04 strd ip, lr, [sp, #-16]! 8009214: f000 f806 bl 8009224 <__udivmoddi4> 8009218: f8dd e004 ldr.w lr, [sp, #4] 800921c: e9dd 2302 ldrd r2, r3, [sp, #8] 8009220: b004 add sp, #16 8009222: 4770 bx lr 08009224 <__udivmoddi4>: 8009224: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8009228: 9d08 ldr r5, [sp, #32] 800922a: 468e mov lr, r1 800922c: 4604 mov r4, r0 800922e: 4688 mov r8, r1 8009230: 2b00 cmp r3, #0 8009232: d14a bne.n 80092ca <__udivmoddi4+0xa6> 8009234: 428a cmp r2, r1 8009236: 4617 mov r7, r2 8009238: d962 bls.n 8009300 <__udivmoddi4+0xdc> 800923a: fab2 f682 clz r6, r2 800923e: b14e cbz r6, 8009254 <__udivmoddi4+0x30> 8009240: f1c6 0320 rsb r3, r6, #32 8009244: fa01 f806 lsl.w r8, r1, r6 8009248: fa20 f303 lsr.w r3, r0, r3 800924c: 40b7 lsls r7, r6 800924e: ea43 0808 orr.w r8, r3, r8 8009252: 40b4 lsls r4, r6 8009254: ea4f 4e17 mov.w lr, r7, lsr #16 8009258: fbb8 f1fe udiv r1, r8, lr 800925c: fa1f fc87 uxth.w ip, r7 8009260: fb0e 8811 mls r8, lr, r1, r8 8009264: fb01 f20c mul.w r2, r1, ip 8009268: 0c23 lsrs r3, r4, #16 800926a: ea43 4308 orr.w r3, r3, r8, lsl #16 800926e: 429a cmp r2, r3 8009270: d909 bls.n 8009286 <__udivmoddi4+0x62> 8009272: 18fb adds r3, r7, r3 8009274: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8009278: f080 80eb bcs.w 8009452 <__udivmoddi4+0x22e> 800927c: 429a cmp r2, r3 800927e: f240 80e8 bls.w 8009452 <__udivmoddi4+0x22e> 8009282: 3902 subs r1, #2 8009284: 443b add r3, r7 8009286: 1a9a subs r2, r3, r2 8009288: fbb2 f0fe udiv r0, r2, lr 800928c: fb0e 2210 mls r2, lr, r0, r2 8009290: fb00 fc0c mul.w ip, r0, ip 8009294: b2a3 uxth r3, r4 8009296: ea43 4302 orr.w r3, r3, r2, lsl #16 800929a: 459c cmp ip, r3 800929c: d909 bls.n 80092b2 <__udivmoddi4+0x8e> 800929e: 18fb adds r3, r7, r3 80092a0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80092a4: f080 80d7 bcs.w 8009456 <__udivmoddi4+0x232> 80092a8: 459c cmp ip, r3 80092aa: f240 80d4 bls.w 8009456 <__udivmoddi4+0x232> 80092ae: 443b add r3, r7 80092b0: 3802 subs r0, #2 80092b2: ea40 4001 orr.w r0, r0, r1, lsl #16 80092b6: 2100 movs r1, #0 80092b8: eba3 030c sub.w r3, r3, ip 80092bc: b11d cbz r5, 80092c6 <__udivmoddi4+0xa2> 80092be: 2200 movs r2, #0 80092c0: 40f3 lsrs r3, r6 80092c2: e9c5 3200 strd r3, r2, [r5] 80092c6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80092ca: 428b cmp r3, r1 80092cc: d905 bls.n 80092da <__udivmoddi4+0xb6> 80092ce: b10d cbz r5, 80092d4 <__udivmoddi4+0xb0> 80092d0: e9c5 0100 strd r0, r1, [r5] 80092d4: 2100 movs r1, #0 80092d6: 4608 mov r0, r1 80092d8: e7f5 b.n 80092c6 <__udivmoddi4+0xa2> 80092da: fab3 f183 clz r1, r3 80092de: 2900 cmp r1, #0 80092e0: d146 bne.n 8009370 <__udivmoddi4+0x14c> 80092e2: 4573 cmp r3, lr 80092e4: d302 bcc.n 80092ec <__udivmoddi4+0xc8> 80092e6: 4282 cmp r2, r0 80092e8: f200 8108 bhi.w 80094fc <__udivmoddi4+0x2d8> 80092ec: 1a84 subs r4, r0, r2 80092ee: eb6e 0203 sbc.w r2, lr, r3 80092f2: 2001 movs r0, #1 80092f4: 4690 mov r8, r2 80092f6: 2d00 cmp r5, #0 80092f8: d0e5 beq.n 80092c6 <__udivmoddi4+0xa2> 80092fa: e9c5 4800 strd r4, r8, [r5] 80092fe: e7e2 b.n 80092c6 <__udivmoddi4+0xa2> 8009300: 2a00 cmp r2, #0 8009302: f000 8091 beq.w 8009428 <__udivmoddi4+0x204> 8009306: fab2 f682 clz r6, r2 800930a: 2e00 cmp r6, #0 800930c: f040 80a5 bne.w 800945a <__udivmoddi4+0x236> 8009310: 1a8a subs r2, r1, r2 8009312: 2101 movs r1, #1 8009314: 0c03 lsrs r3, r0, #16 8009316: ea4f 4e17 mov.w lr, r7, lsr #16 800931a: b280 uxth r0, r0 800931c: b2bc uxth r4, r7 800931e: fbb2 fcfe udiv ip, r2, lr 8009322: fb0e 221c mls r2, lr, ip, r2 8009326: ea43 4302 orr.w r3, r3, r2, lsl #16 800932a: fb04 f20c mul.w r2, r4, ip 800932e: 429a cmp r2, r3 8009330: d907 bls.n 8009342 <__udivmoddi4+0x11e> 8009332: 18fb adds r3, r7, r3 8009334: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8009338: d202 bcs.n 8009340 <__udivmoddi4+0x11c> 800933a: 429a cmp r2, r3 800933c: f200 80e3 bhi.w 8009506 <__udivmoddi4+0x2e2> 8009340: 46c4 mov ip, r8 8009342: 1a9b subs r3, r3, r2 8009344: fbb3 f2fe udiv r2, r3, lr 8009348: fb0e 3312 mls r3, lr, r2, r3 800934c: fb02 f404 mul.w r4, r2, r4 8009350: ea40 4303 orr.w r3, r0, r3, lsl #16 8009354: 429c cmp r4, r3 8009356: d907 bls.n 8009368 <__udivmoddi4+0x144> 8009358: 18fb adds r3, r7, r3 800935a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800935e: d202 bcs.n 8009366 <__udivmoddi4+0x142> 8009360: 429c cmp r4, r3 8009362: f200 80cd bhi.w 8009500 <__udivmoddi4+0x2dc> 8009366: 4602 mov r2, r0 8009368: 1b1b subs r3, r3, r4 800936a: ea42 400c orr.w r0, r2, ip, lsl #16 800936e: e7a5 b.n 80092bc <__udivmoddi4+0x98> 8009370: f1c1 0620 rsb r6, r1, #32 8009374: 408b lsls r3, r1 8009376: fa22 f706 lsr.w r7, r2, r6 800937a: 431f orrs r7, r3 800937c: fa2e fa06 lsr.w sl, lr, r6 8009380: ea4f 4917 mov.w r9, r7, lsr #16 8009384: fbba f8f9 udiv r8, sl, r9 8009388: fa0e fe01 lsl.w lr, lr, r1 800938c: fa20 f306 lsr.w r3, r0, r6 8009390: fb09 aa18 mls sl, r9, r8, sl 8009394: fa1f fc87 uxth.w ip, r7 8009398: ea43 030e orr.w r3, r3, lr 800939c: fa00 fe01 lsl.w lr, r0, r1 80093a0: fb08 f00c mul.w r0, r8, ip 80093a4: 0c1c lsrs r4, r3, #16 80093a6: ea44 440a orr.w r4, r4, sl, lsl #16 80093aa: 42a0 cmp r0, r4 80093ac: fa02 f201 lsl.w r2, r2, r1 80093b0: d90a bls.n 80093c8 <__udivmoddi4+0x1a4> 80093b2: 193c adds r4, r7, r4 80093b4: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff 80093b8: f080 809e bcs.w 80094f8 <__udivmoddi4+0x2d4> 80093bc: 42a0 cmp r0, r4 80093be: f240 809b bls.w 80094f8 <__udivmoddi4+0x2d4> 80093c2: f1a8 0802 sub.w r8, r8, #2 80093c6: 443c add r4, r7 80093c8: 1a24 subs r4, r4, r0 80093ca: b298 uxth r0, r3 80093cc: fbb4 f3f9 udiv r3, r4, r9 80093d0: fb09 4413 mls r4, r9, r3, r4 80093d4: fb03 fc0c mul.w ip, r3, ip 80093d8: ea40 4404 orr.w r4, r0, r4, lsl #16 80093dc: 45a4 cmp ip, r4 80093de: d909 bls.n 80093f4 <__udivmoddi4+0x1d0> 80093e0: 193c adds r4, r7, r4 80093e2: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 80093e6: f080 8085 bcs.w 80094f4 <__udivmoddi4+0x2d0> 80093ea: 45a4 cmp ip, r4 80093ec: f240 8082 bls.w 80094f4 <__udivmoddi4+0x2d0> 80093f0: 3b02 subs r3, #2 80093f2: 443c add r4, r7 80093f4: ea43 4008 orr.w r0, r3, r8, lsl #16 80093f8: eba4 040c sub.w r4, r4, ip 80093fc: fba0 8c02 umull r8, ip, r0, r2 8009400: 4564 cmp r4, ip 8009402: 4643 mov r3, r8 8009404: 46e1 mov r9, ip 8009406: d364 bcc.n 80094d2 <__udivmoddi4+0x2ae> 8009408: d061 beq.n 80094ce <__udivmoddi4+0x2aa> 800940a: b15d cbz r5, 8009424 <__udivmoddi4+0x200> 800940c: ebbe 0203 subs.w r2, lr, r3 8009410: eb64 0409 sbc.w r4, r4, r9 8009414: fa04 f606 lsl.w r6, r4, r6 8009418: fa22 f301 lsr.w r3, r2, r1 800941c: 431e orrs r6, r3 800941e: 40cc lsrs r4, r1 8009420: e9c5 6400 strd r6, r4, [r5] 8009424: 2100 movs r1, #0 8009426: e74e b.n 80092c6 <__udivmoddi4+0xa2> 8009428: fbb1 fcf2 udiv ip, r1, r2 800942c: 0c01 lsrs r1, r0, #16 800942e: ea41 410e orr.w r1, r1, lr, lsl #16 8009432: b280 uxth r0, r0 8009434: ea40 4201 orr.w r2, r0, r1, lsl #16 8009438: 463b mov r3, r7 800943a: fbb1 f1f7 udiv r1, r1, r7 800943e: 4638 mov r0, r7 8009440: 463c mov r4, r7 8009442: 46b8 mov r8, r7 8009444: 46be mov lr, r7 8009446: 2620 movs r6, #32 8009448: eba2 0208 sub.w r2, r2, r8 800944c: ea41 410c orr.w r1, r1, ip, lsl #16 8009450: e765 b.n 800931e <__udivmoddi4+0xfa> 8009452: 4601 mov r1, r0 8009454: e717 b.n 8009286 <__udivmoddi4+0x62> 8009456: 4610 mov r0, r2 8009458: e72b b.n 80092b2 <__udivmoddi4+0x8e> 800945a: f1c6 0120 rsb r1, r6, #32 800945e: fa2e fc01 lsr.w ip, lr, r1 8009462: 40b7 lsls r7, r6 8009464: fa0e fe06 lsl.w lr, lr, r6 8009468: fa20 f101 lsr.w r1, r0, r1 800946c: ea41 010e orr.w r1, r1, lr 8009470: ea4f 4e17 mov.w lr, r7, lsr #16 8009474: fbbc f8fe udiv r8, ip, lr 8009478: b2bc uxth r4, r7 800947a: fb0e cc18 mls ip, lr, r8, ip 800947e: fb08 f904 mul.w r9, r8, r4 8009482: 0c0a lsrs r2, r1, #16 8009484: ea42 420c orr.w r2, r2, ip, lsl #16 8009488: 40b0 lsls r0, r6 800948a: 4591 cmp r9, r2 800948c: ea4f 4310 mov.w r3, r0, lsr #16 8009490: b280 uxth r0, r0 8009492: d93e bls.n 8009512 <__udivmoddi4+0x2ee> 8009494: 18ba adds r2, r7, r2 8009496: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 800949a: d201 bcs.n 80094a0 <__udivmoddi4+0x27c> 800949c: 4591 cmp r9, r2 800949e: d81f bhi.n 80094e0 <__udivmoddi4+0x2bc> 80094a0: eba2 0209 sub.w r2, r2, r9 80094a4: fbb2 f9fe udiv r9, r2, lr 80094a8: fb09 f804 mul.w r8, r9, r4 80094ac: fb0e 2a19 mls sl, lr, r9, r2 80094b0: b28a uxth r2, r1 80094b2: ea42 420a orr.w r2, r2, sl, lsl #16 80094b6: 4542 cmp r2, r8 80094b8: d229 bcs.n 800950e <__udivmoddi4+0x2ea> 80094ba: 18ba adds r2, r7, r2 80094bc: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80094c0: d2c2 bcs.n 8009448 <__udivmoddi4+0x224> 80094c2: 4542 cmp r2, r8 80094c4: d2c0 bcs.n 8009448 <__udivmoddi4+0x224> 80094c6: f1a9 0102 sub.w r1, r9, #2 80094ca: 443a add r2, r7 80094cc: e7bc b.n 8009448 <__udivmoddi4+0x224> 80094ce: 45c6 cmp lr, r8 80094d0: d29b bcs.n 800940a <__udivmoddi4+0x1e6> 80094d2: ebb8 0302 subs.w r3, r8, r2 80094d6: eb6c 0c07 sbc.w ip, ip, r7 80094da: 3801 subs r0, #1 80094dc: 46e1 mov r9, ip 80094de: e794 b.n 800940a <__udivmoddi4+0x1e6> 80094e0: eba7 0909 sub.w r9, r7, r9 80094e4: 444a add r2, r9 80094e6: fbb2 f9fe udiv r9, r2, lr 80094ea: f1a8 0c02 sub.w ip, r8, #2 80094ee: fb09 f804 mul.w r8, r9, r4 80094f2: e7db b.n 80094ac <__udivmoddi4+0x288> 80094f4: 4603 mov r3, r0 80094f6: e77d b.n 80093f4 <__udivmoddi4+0x1d0> 80094f8: 46d0 mov r8, sl 80094fa: e765 b.n 80093c8 <__udivmoddi4+0x1a4> 80094fc: 4608 mov r0, r1 80094fe: e6fa b.n 80092f6 <__udivmoddi4+0xd2> 8009500: 443b add r3, r7 8009502: 3a02 subs r2, #2 8009504: e730 b.n 8009368 <__udivmoddi4+0x144> 8009506: f1ac 0c02 sub.w ip, ip, #2 800950a: 443b add r3, r7 800950c: e719 b.n 8009342 <__udivmoddi4+0x11e> 800950e: 4649 mov r1, r9 8009510: e79a b.n 8009448 <__udivmoddi4+0x224> 8009512: eba2 0209 sub.w r2, r2, r9 8009516: fbb2 f9fe udiv r9, r2, lr 800951a: 46c4 mov ip, r8 800951c: fb09 f804 mul.w r8, r9, r4 8009520: e7c4 b.n 80094ac <__udivmoddi4+0x288> 8009522: bf00 nop 08009524 <__aeabi_idiv0>: 8009524: 4770 bx lr 8009526: bf00 nop 08009528 : static volatile uint16_t adc_dma_raw[6]; volatile ADC_ScanData_t adc_data = {0}; static volatile uint8_t adc_scan_data_ready = 0u; void ADC_ScanStart(void) { 8009528: b580 push {r7, lr} 800952a: af00 add r7, sp, #0 if (HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc_dma_raw, 6u) != HAL_OK) 800952c: 2206 movs r2, #6 800952e: 4905 ldr r1, [pc, #20] @ (8009544 ) 8009530: 4805 ldr r0, [pc, #20] @ (8009548 ) 8009532: f004 ffd5 bl 800e4e0 8009536: 4603 mov r3, r0 8009538: 2b00 cmp r3, #0 800953a: d001 beq.n 8009540 { Error_Handler(); 800953c: f001 fb70 bl 800ac20 } } 8009540: bf00 nop 8009542: bd80 pop {r7, pc} 8009544: 20000274 .word 0x20000274 8009548: 20000290 .word 0x20000290 0800954c : ISR_FAST void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { if (hadc->Instance != ADC1) 800954c: 4b0e ldr r3, [pc, #56] @ (8009588 ) 800954e: 6802 ldr r2, [r0, #0] 8009550: 429a cmp r2, r3 8009552: d118 bne.n 8009586 adc_data.cp_raw = adc_dma_raw[1]; adc_data.ntc1_raw = adc_dma_raw[2]; adc_data.ntc2_raw = adc_dma_raw[3]; adc_data.temp_sensor_raw = adc_dma_raw[4]; adc_data.vrefint_raw = adc_dma_raw[5]; adc_scan_data_ready = 1u; 8009554: f04f 0c01 mov.w ip, #1 adc_data.in3_raw = adc_dma_raw[0]; 8009558: 4a0c ldr r2, [pc, #48] @ (800958c ) 800955a: 4b0d ldr r3, [pc, #52] @ (8009590 ) 800955c: 8811 ldrh r1, [r2, #0] adc_scan_data_ready = 1u; 800955e: 480d ldr r0, [pc, #52] @ (8009594 ) adc_data.in3_raw = adc_dma_raw[0]; 8009560: b289 uxth r1, r1 8009562: 8019 strh r1, [r3, #0] adc_data.cp_raw = adc_dma_raw[1]; 8009564: 8851 ldrh r1, [r2, #2] 8009566: b289 uxth r1, r1 8009568: 8059 strh r1, [r3, #2] adc_data.ntc1_raw = adc_dma_raw[2]; 800956a: 8891 ldrh r1, [r2, #4] 800956c: b289 uxth r1, r1 800956e: 8099 strh r1, [r3, #4] adc_data.ntc2_raw = adc_dma_raw[3]; 8009570: 88d1 ldrh r1, [r2, #6] 8009572: b289 uxth r1, r1 8009574: 80d9 strh r1, [r3, #6] adc_data.temp_sensor_raw = adc_dma_raw[4]; 8009576: 8911 ldrh r1, [r2, #8] 8009578: b289 uxth r1, r1 800957a: 8119 strh r1, [r3, #8] adc_data.vrefint_raw = adc_dma_raw[5]; 800957c: 8952 ldrh r2, [r2, #10] 800957e: b292 uxth r2, r2 8009580: 815a strh r2, [r3, #10] adc_scan_data_ready = 1u; 8009582: f880 c000 strb.w ip, [r0] } 8009586: 4770 bx lr 8009588: 40012400 .word 0x40012400 800958c: 20000274 .word 0x20000274 8009590: 20000280 .word 0x20000280 8009594: 2000028c .word 0x2000028c 08009598 : ADC_HandleTypeDef hadc1; DMA_HandleTypeDef hdma_adc1; /* ADC1 init function */ void MX_ADC1_Init(void) { 8009598: b580 push {r7, lr} 800959a: b084 sub sp, #16 800959c: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 800959e: 1d3b adds r3, r7, #4 80095a0: 2200 movs r2, #0 80095a2: 601a str r2, [r3, #0] 80095a4: 605a str r2, [r3, #4] 80095a6: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 80095a8: 4b3c ldr r3, [pc, #240] @ (800969c ) 80095aa: 4a3d ldr r2, [pc, #244] @ (80096a0 ) 80095ac: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 80095ae: 4b3b ldr r3, [pc, #236] @ (800969c ) 80095b0: f44f 7280 mov.w r2, #256 @ 0x100 80095b4: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = DISABLE; 80095b6: 4b39 ldr r3, [pc, #228] @ (800969c ) 80095b8: 2200 movs r2, #0 80095ba: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 80095bc: 4b37 ldr r3, [pc, #220] @ (800969c ) 80095be: 2200 movs r2, #0 80095c0: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T3_TRGO; 80095c2: 4b36 ldr r3, [pc, #216] @ (800969c ) 80095c4: f44f 2200 mov.w r2, #524288 @ 0x80000 80095c8: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80095ca: 4b34 ldr r3, [pc, #208] @ (800969c ) 80095cc: 2200 movs r2, #0 80095ce: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 6; 80095d0: 4b32 ldr r3, [pc, #200] @ (800969c ) 80095d2: 2206 movs r2, #6 80095d4: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 80095d6: 4831 ldr r0, [pc, #196] @ (800969c ) 80095d8: f004 feaa bl 800e330 80095dc: 4603 mov r3, r0 80095de: 2b00 cmp r3, #0 80095e0: d001 beq.n 80095e6 { Error_Handler(); 80095e2: f001 fb1d bl 800ac20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 80095e6: 2303 movs r3, #3 80095e8: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 80095ea: 2301 movs r3, #1 80095ec: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_41CYCLES_5; 80095ee: 2304 movs r3, #4 80095f0: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80095f2: 1d3b adds r3, r7, #4 80095f4: 4619 mov r1, r3 80095f6: 4829 ldr r0, [pc, #164] @ (800969c ) 80095f8: f005 f92a bl 800e850 80095fc: 4603 mov r3, r0 80095fe: 2b00 cmp r3, #0 8009600: d001 beq.n 8009606 { Error_Handler(); 8009602: f001 fb0d bl 800ac20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8009606: 2304 movs r3, #4 8009608: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 800960a: 2302 movs r3, #2 800960c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800960e: 1d3b adds r3, r7, #4 8009610: 4619 mov r1, r3 8009612: 4822 ldr r0, [pc, #136] @ (800969c ) 8009614: f005 f91c bl 800e850 8009618: 4603 mov r3, r0 800961a: 2b00 cmp r3, #0 800961c: d001 beq.n 8009622 { Error_Handler(); 800961e: f001 faff bl 800ac20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8009622: 2308 movs r3, #8 8009624: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8009626: 2303 movs r3, #3 8009628: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800962a: 1d3b adds r3, r7, #4 800962c: 4619 mov r1, r3 800962e: 481b ldr r0, [pc, #108] @ (800969c ) 8009630: f005 f90e bl 800e850 8009634: 4603 mov r3, r0 8009636: 2b00 cmp r3, #0 8009638: d001 beq.n 800963e { Error_Handler(); 800963a: f001 faf1 bl 800ac20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_9; 800963e: 2309 movs r3, #9 8009640: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_4; 8009642: 2304 movs r3, #4 8009644: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8009646: 1d3b adds r3, r7, #4 8009648: 4619 mov r1, r3 800964a: 4814 ldr r0, [pc, #80] @ (800969c ) 800964c: f005 f900 bl 800e850 8009650: 4603 mov r3, r0 8009652: 2b00 cmp r3, #0 8009654: d001 beq.n 800965a { Error_Handler(); 8009656: f001 fae3 bl 800ac20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; 800965a: 2310 movs r3, #16 800965c: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_5; 800965e: 2305 movs r3, #5 8009660: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8009662: 1d3b adds r3, r7, #4 8009664: 4619 mov r1, r3 8009666: 480d ldr r0, [pc, #52] @ (800969c ) 8009668: f005 f8f2 bl 800e850 800966c: 4603 mov r3, r0 800966e: 2b00 cmp r3, #0 8009670: d001 beq.n 8009676 { Error_Handler(); 8009672: f001 fad5 bl 800ac20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; 8009676: 2311 movs r3, #17 8009678: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_6; 800967a: 2306 movs r3, #6 800967c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800967e: 1d3b adds r3, r7, #4 8009680: 4619 mov r1, r3 8009682: 4806 ldr r0, [pc, #24] @ (800969c ) 8009684: f005 f8e4 bl 800e850 8009688: 4603 mov r3, r0 800968a: 2b00 cmp r3, #0 800968c: d001 beq.n 8009692 { Error_Handler(); 800968e: f001 fac7 bl 800ac20 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 8009692: bf00 nop 8009694: 3710 adds r7, #16 8009696: 46bd mov sp, r7 8009698: bd80 pop {r7, pc} 800969a: bf00 nop 800969c: 20000290 .word 0x20000290 80096a0: 40012400 .word 0x40012400 080096a4 : void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 80096a4: b580 push {r7, lr} 80096a6: b08a sub sp, #40 @ 0x28 80096a8: af00 add r7, sp, #0 80096aa: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80096ac: f107 0318 add.w r3, r7, #24 80096b0: 2200 movs r2, #0 80096b2: 601a str r2, [r3, #0] 80096b4: 605a str r2, [r3, #4] 80096b6: 609a str r2, [r3, #8] 80096b8: 60da str r2, [r3, #12] if(adcHandle->Instance==ADC1) 80096ba: 687b ldr r3, [r7, #4] 80096bc: 681b ldr r3, [r3, #0] 80096be: 4a38 ldr r2, [pc, #224] @ (80097a0 ) 80096c0: 4293 cmp r3, r2 80096c2: d168 bne.n 8009796 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 80096c4: 4b37 ldr r3, [pc, #220] @ (80097a4 ) 80096c6: 699b ldr r3, [r3, #24] 80096c8: 4a36 ldr r2, [pc, #216] @ (80097a4 ) 80096ca: f443 7300 orr.w r3, r3, #512 @ 0x200 80096ce: 6193 str r3, [r2, #24] 80096d0: 4b34 ldr r3, [pc, #208] @ (80097a4 ) 80096d2: 699b ldr r3, [r3, #24] 80096d4: f403 7300 and.w r3, r3, #512 @ 0x200 80096d8: 617b str r3, [r7, #20] 80096da: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 80096dc: 4b31 ldr r3, [pc, #196] @ (80097a4 ) 80096de: 699b ldr r3, [r3, #24] 80096e0: 4a30 ldr r2, [pc, #192] @ (80097a4 ) 80096e2: f043 0304 orr.w r3, r3, #4 80096e6: 6193 str r3, [r2, #24] 80096e8: 4b2e ldr r3, [pc, #184] @ (80097a4 ) 80096ea: 699b ldr r3, [r3, #24] 80096ec: f003 0304 and.w r3, r3, #4 80096f0: 613b str r3, [r7, #16] 80096f2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80096f4: 4b2b ldr r3, [pc, #172] @ (80097a4 ) 80096f6: 699b ldr r3, [r3, #24] 80096f8: 4a2a ldr r2, [pc, #168] @ (80097a4 ) 80096fa: f043 0308 orr.w r3, r3, #8 80096fe: 6193 str r3, [r2, #24] 8009700: 4b28 ldr r3, [pc, #160] @ (80097a4 ) 8009702: 699b ldr r3, [r3, #24] 8009704: f003 0308 and.w r3, r3, #8 8009708: 60fb str r3, [r7, #12] 800970a: 68fb ldr r3, [r7, #12] PA3 ------> ADC1_IN3 PA4 ------> ADC1_IN4 PB0 ------> ADC1_IN8 PB1 ------> ADC1_IN9 */ GPIO_InitStruct.Pin = GPIO_PIN_3|CP_ADC_Pin; 800970c: 2318 movs r3, #24 800970e: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009710: 2303 movs r3, #3 8009712: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8009714: f107 0318 add.w r3, r7, #24 8009718: 4619 mov r1, r3 800971a: 4823 ldr r0, [pc, #140] @ (80097a8 ) 800971c: f006 ffd6 bl 80106cc GPIO_InitStruct.Pin = ADC_NTC1_Pin|ADC_NTC2_Pin; 8009720: 2303 movs r3, #3 8009722: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009724: 2303 movs r3, #3 8009726: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009728: f107 0318 add.w r3, r7, #24 800972c: 4619 mov r1, r3 800972e: 481f ldr r0, [pc, #124] @ (80097ac ) 8009730: f006 ffcc bl 80106cc /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; 8009734: 4b1e ldr r3, [pc, #120] @ (80097b0 ) 8009736: 4a1f ldr r2, [pc, #124] @ (80097b4 ) 8009738: 601a str r2, [r3, #0] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 800973a: 4b1d ldr r3, [pc, #116] @ (80097b0 ) 800973c: 2200 movs r2, #0 800973e: 605a str r2, [r3, #4] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8009740: 4b1b ldr r3, [pc, #108] @ (80097b0 ) 8009742: 2200 movs r2, #0 8009744: 609a str r2, [r3, #8] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8009746: 4b1a ldr r3, [pc, #104] @ (80097b0 ) 8009748: 2280 movs r2, #128 @ 0x80 800974a: 60da str r2, [r3, #12] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 800974c: 4b18 ldr r3, [pc, #96] @ (80097b0 ) 800974e: f44f 7280 mov.w r2, #256 @ 0x100 8009752: 611a str r2, [r3, #16] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8009754: 4b16 ldr r3, [pc, #88] @ (80097b0 ) 8009756: f44f 6280 mov.w r2, #1024 @ 0x400 800975a: 615a str r2, [r3, #20] hdma_adc1.Init.Mode = DMA_CIRCULAR; 800975c: 4b14 ldr r3, [pc, #80] @ (80097b0 ) 800975e: 2220 movs r2, #32 8009760: 619a str r2, [r3, #24] hdma_adc1.Init.Priority = DMA_PRIORITY_MEDIUM; 8009762: 4b13 ldr r3, [pc, #76] @ (80097b0 ) 8009764: f44f 5280 mov.w r2, #4096 @ 0x1000 8009768: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 800976a: 4811 ldr r0, [pc, #68] @ (80097b0 ) 800976c: f006 fb20 bl 800fdb0 8009770: 4603 mov r3, r0 8009772: 2b00 cmp r3, #0 8009774: d001 beq.n 800977a { Error_Handler(); 8009776: f001 fa53 bl 800ac20 } __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1); 800977a: 687b ldr r3, [r7, #4] 800977c: 4a0c ldr r2, [pc, #48] @ (80097b0 ) 800977e: 621a str r2, [r3, #32] 8009780: 4a0b ldr r2, [pc, #44] @ (80097b0 ) 8009782: 687b ldr r3, [r7, #4] 8009784: 6253 str r3, [r2, #36] @ 0x24 /* ADC1 interrupt Init */ HAL_NVIC_SetPriority(ADC1_2_IRQn, 7, 0); 8009786: 2200 movs r2, #0 8009788: 2107 movs r1, #7 800978a: 2012 movs r0, #18 800978c: f006 fabd bl 800fd0a HAL_NVIC_EnableIRQ(ADC1_2_IRQn); 8009790: 2012 movs r0, #18 8009792: f006 fad6 bl 800fd42 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8009796: bf00 nop 8009798: 3728 adds r7, #40 @ 0x28 800979a: 46bd mov sp, r7 800979c: bd80 pop {r7, pc} 800979e: bf00 nop 80097a0: 40012400 .word 0x40012400 80097a4: 40021000 .word 0x40021000 80097a8: 40010800 .word 0x40010800 80097ac: 40010c00 .word 0x40010c00 80097b0: 200002c0 .word 0x200002c0 80097b4: 40020008 .word 0x40020008 080097b8 : uint8_t RELAY_State[RELAY_COUNT]; static volatile uint8_t adc_lock = 0; static SMAFilter_t conn_temp_adc_filter[2]; void RELAY_Write(relay_t num, uint8_t state){ 80097b8: b580 push {r7, lr} 80097ba: b082 sub sp, #8 80097bc: af00 add r7, sp, #0 80097be: 4603 mov r3, r0 80097c0: 460a mov r2, r1 80097c2: 71fb strb r3, [r7, #7] 80097c4: 4613 mov r3, r2 80097c6: 71bb strb r3, [r7, #6] switch (num) { 80097c8: 79fb ldrb r3, [r7, #7] 80097ca: 2b07 cmp r3, #7 80097cc: d850 bhi.n 8009870 80097ce: a201 add r2, pc, #4 @ (adr r2, 80097d4 ) 80097d0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80097d4: 080097f5 .word 0x080097f5 80097d8: 08009805 .word 0x08009805 80097dc: 08009815 .word 0x08009815 80097e0: 08009825 .word 0x08009825 80097e4: 08009835 .word 0x08009835 80097e8: 08009845 .word 0x08009845 80097ec: 08009853 .word 0x08009853 80097f0: 08009863 .word 0x08009863 case RELAY_AUX0: HAL_GPIO_WritePin(RELAY1_GPIO_Port, RELAY1_Pin, state); 80097f4: 79bb ldrb r3, [r7, #6] 80097f6: 461a mov r2, r3 80097f8: f44f 7180 mov.w r1, #256 @ 0x100 80097fc: 4821 ldr r0, [pc, #132] @ (8009884 ) 80097fe: f007 f900 bl 8010a02 break; 8009802: e036 b.n 8009872 case RELAY_AUX1: HAL_GPIO_WritePin(RELAY2_GPIO_Port, RELAY2_Pin, state); 8009804: 79bb ldrb r3, [r7, #6] 8009806: 461a mov r2, r3 8009808: f44f 7100 mov.w r1, #512 @ 0x200 800980c: 481d ldr r0, [pc, #116] @ (8009884 ) 800980e: f007 f8f8 bl 8010a02 break; 8009812: e02e b.n 8009872 case RELAY3: HAL_GPIO_WritePin(RELAY3_GPIO_Port, RELAY3_Pin, state); 8009814: 79bb ldrb r3, [r7, #6] 8009816: 461a mov r2, r3 8009818: f44f 6180 mov.w r1, #1024 @ 0x400 800981c: 4819 ldr r0, [pc, #100] @ (8009884 ) 800981e: f007 f8f0 bl 8010a02 break; 8009822: e026 b.n 8009872 case RELAY_DC: HAL_GPIO_WritePin(RELAY4_GPIO_Port, RELAY4_Pin, state); 8009824: 79bb ldrb r3, [r7, #6] 8009826: 461a mov r2, r3 8009828: f44f 6100 mov.w r1, #2048 @ 0x800 800982c: 4815 ldr r0, [pc, #84] @ (8009884 ) 800982e: f007 f8e8 bl 8010a02 break; 8009832: e01e b.n 8009872 case RELAY_AC: HAL_GPIO_WritePin(RELAY5_GPIO_Port, RELAY5_Pin, state); 8009834: 79bb ldrb r3, [r7, #6] 8009836: 461a mov r2, r3 8009838: f44f 5180 mov.w r1, #4096 @ 0x1000 800983c: 4811 ldr r0, [pc, #68] @ (8009884 ) 800983e: f007 f8e0 bl 8010a02 break; 8009842: e016 b.n 8009872 case RELAY_CP: HAL_GPIO_WritePin(RELAY_CP_GPIO_Port, RELAY_CP_Pin, state); 8009844: 79bb ldrb r3, [r7, #6] 8009846: 461a mov r2, r3 8009848: 2108 movs r1, #8 800984a: 480f ldr r0, [pc, #60] @ (8009888 ) 800984c: f007 f8d9 bl 8010a02 break; 8009850: e00f b.n 8009872 case RELAY_CC: HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, state); 8009852: 79bb ldrb r3, [r7, #6] 8009854: 461a mov r2, r3 8009856: f44f 4100 mov.w r1, #32768 @ 0x8000 800985a: 480c ldr r0, [pc, #48] @ (800988c ) 800985c: f007 f8d1 bl 8010a02 break; 8009860: e007 b.n 8009872 case RELAY_DC1: HAL_GPIO_WritePin(RELAY_DC_GPIO_Port, RELAY_DC_Pin, state); 8009862: 79bb ldrb r3, [r7, #6] 8009864: 461a mov r2, r3 8009866: 2108 movs r1, #8 8009868: 4809 ldr r0, [pc, #36] @ (8009890 ) 800986a: f007 f8ca bl 8010a02 break; 800986e: e000 b.n 8009872 default: break; 8009870: bf00 nop } RELAY_State[num] = state; 8009872: 79fb ldrb r3, [r7, #7] 8009874: 4907 ldr r1, [pc, #28] @ (8009894 ) 8009876: 79ba ldrb r2, [r7, #6] 8009878: 54ca strb r2, [r1, r3] } 800987a: bf00 nop 800987c: 3708 adds r7, #8 800987e: 46bd mov sp, r7 8009880: bd80 pop {r7, pc} 8009882: bf00 nop 8009884: 40011800 .word 0x40011800 8009888: 40011000 .word 0x40011000 800988c: 40010800 .word 0x40010800 8009890: 40011400 .word 0x40011400 8009894: 20000304 .word 0x20000304 08009898 : uint8_t RELAY_Read(relay_t num){ 8009898: b480 push {r7} 800989a: b083 sub sp, #12 800989c: af00 add r7, sp, #0 800989e: 4603 mov r3, r0 80098a0: 71fb strb r3, [r7, #7] return RELAY_State[num]; 80098a2: 79fb ldrb r3, [r7, #7] 80098a4: 4a03 ldr r2, [pc, #12] @ (80098b4 ) 80098a6: 5cd3 ldrb r3, [r2, r3] } 80098a8: 4618 mov r0, r3 80098aa: 370c adds r7, #12 80098ac: 46bd mov sp, r7 80098ae: bc80 pop {r7} 80098b0: 4770 bx lr 80098b2: bf00 nop 80098b4: 20000304 .word 0x20000304 080098b8 : uint8_t IN_ReadInput(inputNum_t input_n){ 80098b8: b580 push {r7, lr} 80098ba: b082 sub sp, #8 80098bc: af00 add r7, sp, #0 80098be: 4603 mov r3, r0 80098c0: 71fb strb r3, [r7, #7] switch(input_n){ 80098c2: 79fb ldrb r3, [r7, #7] 80098c4: 2b06 cmp r3, #6 80098c6: d83b bhi.n 8009940 80098c8: a201 add r2, pc, #4 @ (adr r2, 80098d0 ) 80098ca: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80098ce: bf00 nop 80098d0: 080098ed .word 0x080098ed 80098d4: 080098f9 .word 0x080098f9 80098d8: 08009905 .word 0x08009905 80098dc: 08009911 .word 0x08009911 80098e0: 0800991d .word 0x0800991d 80098e4: 08009929 .word 0x08009929 80098e8: 08009935 .word 0x08009935 case IN_SW0: return HAL_GPIO_ReadPin(IN_SW0_GPIO_Port, IN_SW0_Pin); 80098ec: 2102 movs r1, #2 80098ee: 4817 ldr r0, [pc, #92] @ (800994c ) 80098f0: f007 f870 bl 80109d4 80098f4: 4603 mov r3, r0 80098f6: e024 b.n 8009942 case IN_SW1: return HAL_GPIO_ReadPin(IN_SW1_GPIO_Port, IN_SW1_Pin); 80098f8: 2104 movs r1, #4 80098fa: 4814 ldr r0, [pc, #80] @ (800994c ) 80098fc: f007 f86a bl 80109d4 8009900: 4603 mov r3, r0 8009902: e01e b.n 8009942 case IN0: return HAL_GPIO_ReadPin(IN0_GPIO_Port, IN0_Pin); 8009904: 2180 movs r1, #128 @ 0x80 8009906: 4812 ldr r0, [pc, #72] @ (8009950 ) 8009908: f007 f864 bl 80109d4 800990c: 4603 mov r3, r0 800990e: e018 b.n 8009942 case IN_ESTOP: return HAL_GPIO_ReadPin(IN_ESTOP_GPIO_Port, IN_ESTOP_Pin); 8009910: 2180 movs r1, #128 @ 0x80 8009912: 4810 ldr r0, [pc, #64] @ (8009954 ) 8009914: f007 f85e bl 80109d4 8009918: 4603 mov r3, r0 800991a: e012 b.n 8009942 case IN_FB1: return HAL_GPIO_ReadPin(IN_FB1_GPIO_Port, IN_FB1_Pin); 800991c: 2110 movs r1, #16 800991e: 480e ldr r0, [pc, #56] @ (8009958 ) 8009920: f007 f858 bl 80109d4 8009924: 4603 mov r3, r0 8009926: e00c b.n 8009942 case IN_CONT_FB_DC: return HAL_GPIO_ReadPin(IN_FB2_GPIO_Port, IN_FB2_Pin); 8009928: 2108 movs r1, #8 800992a: 480b ldr r0, [pc, #44] @ (8009958 ) 800992c: f007 f852 bl 80109d4 8009930: 4603 mov r3, r0 8009932: e006 b.n 8009942 case ISO_IN: return HAL_GPIO_ReadPin(ISO_IN_GPIO_Port, ISO_IN_Pin); 8009934: 2102 movs r1, #2 8009936: 4806 ldr r0, [pc, #24] @ (8009950 ) 8009938: f007 f84c bl 80109d4 800993c: 4603 mov r3, r0 800993e: e000 b.n 8009942 default: return 0; 8009940: 2300 movs r3, #0 } } 8009942: 4618 mov r0, r3 8009944: 3708 adds r7, #8 8009946: 46bd mov sp, r7 8009948: bd80 pop {r7, pc} 800994a: bf00 nop 800994c: 40010800 .word 0x40010800 8009950: 40011800 .word 0x40011800 8009954: 40011400 .word 0x40011400 8009958: 40010c00 .word 0x40010c00 0800995c : /* Заглушка: температура платы не измеряется (нет реализации АЦП для канала). */ uint8_t GetBoardTemp(void){ return 0; } void Init_Peripheral(){ 800995c: b580 push {r7, lr} 800995e: af00 add r7, sp, #0 HAL_ADCEx_Calibration_Start(&hadc1); 8009960: 4816 ldr r0, [pc, #88] @ (80099bc ) 8009962: f005 f96f bl 800ec44 ADC_ScanStart(); 8009966: f7ff fddf bl 8009528 RELAY_Write(RELAY_AUX0, 0); 800996a: 2100 movs r1, #0 800996c: 2000 movs r0, #0 800996e: f7ff ff23 bl 80097b8 RELAY_Write(RELAY_AUX1, 0); 8009972: 2100 movs r1, #0 8009974: 2001 movs r0, #1 8009976: f7ff ff1f bl 80097b8 RELAY_Write(RELAY3, 0); 800997a: 2100 movs r1, #0 800997c: 2002 movs r0, #2 800997e: f7ff ff1b bl 80097b8 RELAY_Write(RELAY_DC, 0); 8009982: 2100 movs r1, #0 8009984: 2003 movs r0, #3 8009986: f7ff ff17 bl 80097b8 RELAY_Write(RELAY_AC, 0); 800998a: 2100 movs r1, #0 800998c: 2004 movs r0, #4 800998e: f7ff ff13 bl 80097b8 RELAY_Write(RELAY_CP, 0); 8009992: 2100 movs r1, #0 8009994: 2005 movs r0, #5 8009996: f7ff ff0f bl 80097b8 RELAY_Write(RELAY_CC, 0); 800999a: 2100 movs r1, #0 800999c: 2006 movs r0, #6 800999e: f7ff ff0b bl 80097b8 RELAY_Write(RELAY_DC1, 0); 80099a2: 2100 movs r1, #0 80099a4: 2007 movs r0, #7 80099a6: f7ff ff07 bl 80097b8 SMAFilter_Init(&conn_temp_adc_filter[0]); 80099aa: 4805 ldr r0, [pc, #20] @ (80099c0 ) 80099ac: f003 fd48 bl 800d440 SMAFilter_Init(&conn_temp_adc_filter[1]); 80099b0: 4804 ldr r0, [pc, #16] @ (80099c4 ) 80099b2: f003 fd45 bl 800d440 } 80099b6: bf00 nop 80099b8: bd80 pop {r7, pc} 80099ba: bf00 nop 80099bc: 20000290 .word 0x20000290 80099c0: 2000030c .word 0x2000030c 80099c4: 20000334 .word 0x20000334 080099c8 : float pt1000_to_temperature(float resistance) { 80099c8: b590 push {r4, r7, lr} 80099ca: b087 sub sp, #28 80099cc: af00 add r7, sp, #0 80099ce: 6078 str r0, [r7, #4] // Константы для PT1000 const float R0 = 1000.0; // Сопротивление при 0 °C 80099d0: 4b0c ldr r3, [pc, #48] @ (8009a04 ) 80099d2: 617b str r3, [r7, #20] const float C_A = 3.9083E-3f; 80099d4: 4b0c ldr r3, [pc, #48] @ (8009a08 ) 80099d6: 613b str r3, [r7, #16] float temperature = (resistance-R0) / ( R0 * C_A); 80099d8: 6979 ldr r1, [r7, #20] 80099da: 6878 ldr r0, [r7, #4] 80099dc: f7ff f914 bl 8008c08 <__aeabi_fsub> 80099e0: 4603 mov r3, r0 80099e2: 461c mov r4, r3 80099e4: 6939 ldr r1, [r7, #16] 80099e6: 6978 ldr r0, [r7, #20] 80099e8: f7ff fa18 bl 8008e1c <__aeabi_fmul> 80099ec: 4603 mov r3, r0 80099ee: 4619 mov r1, r3 80099f0: 4620 mov r0, r4 80099f2: f7ff fac7 bl 8008f84 <__aeabi_fdiv> 80099f6: 4603 mov r3, r0 80099f8: 60fb str r3, [r7, #12] return temperature; 80099fa: 68fb ldr r3, [r7, #12] } 80099fc: 4618 mov r0, r3 80099fe: 371c adds r7, #28 8009a00: 46bd mov sp, r7 8009a02: bd90 pop {r4, r7, pc} 8009a04: 447a0000 .word 0x447a0000 8009a08: 3b801132 .word 0x3b801132 8009a0c: 00000000 .word 0x00000000 08009a10 : float calculate_NTC_resistance(int adc_value, float Vref, float Vin, float R) { 8009a10: b5b0 push {r4, r5, r7, lr} 8009a12: b086 sub sp, #24 8009a14: af00 add r7, sp, #0 8009a16: 60f8 str r0, [r7, #12] 8009a18: 60b9 str r1, [r7, #8] 8009a1a: 607a str r2, [r7, #4] 8009a1c: 603b str r3, [r7, #0] // Преобразуем значение АЦП в выходное напряжение float Vout = (adc_value / 4095.0) * Vref; 8009a1e: 68f8 ldr r0, [r7, #12] 8009a20: f7fe fd5c bl 80084dc <__aeabi_i2d> 8009a24: a31c add r3, pc, #112 @ (adr r3, 8009a98 ) 8009a26: e9d3 2300 ldrd r2, r3, [r3] 8009a2a: f7fe feeb bl 8008804 <__aeabi_ddiv> 8009a2e: 4602 mov r2, r0 8009a30: 460b mov r3, r1 8009a32: 4614 mov r4, r2 8009a34: 461d mov r5, r3 8009a36: 68b8 ldr r0, [r7, #8] 8009a38: f7fe fd62 bl 8008500 <__aeabi_f2d> 8009a3c: 4602 mov r2, r0 8009a3e: 460b mov r3, r1 8009a40: 4620 mov r0, r4 8009a42: 4629 mov r1, r5 8009a44: f7fe fdb4 bl 80085b0 <__aeabi_dmul> 8009a48: 4602 mov r2, r0 8009a4a: 460b mov r3, r1 8009a4c: 4610 mov r0, r2 8009a4e: 4619 mov r1, r3 8009a50: f7ff f886 bl 8008b60 <__aeabi_d2f> 8009a54: 4603 mov r3, r0 8009a56: 617b str r3, [r7, #20] // Проверяем, чтобы Vout не было равно Vin if (Vout >= Vin) { 8009a58: 6879 ldr r1, [r7, #4] 8009a5a: 6978 ldr r0, [r7, #20] 8009a5c: f7ff fb90 bl 8009180 <__aeabi_fcmpge> 8009a60: 4603 mov r3, r0 8009a62: 2b00 cmp r3, #0 8009a64: d001 beq.n 8009a6a return -1; // Ошибка: Vout не может быть больше или равно Vin 8009a66: 4b0e ldr r3, [pc, #56] @ (8009aa0 ) 8009a68: e010 b.n 8009a8c } // Вычисляем сопротивление термистора float R_NTC = R * (Vout / (Vin - Vout)); 8009a6a: 6979 ldr r1, [r7, #20] 8009a6c: 6878 ldr r0, [r7, #4] 8009a6e: f7ff f8cb bl 8008c08 <__aeabi_fsub> 8009a72: 4603 mov r3, r0 8009a74: 4619 mov r1, r3 8009a76: 6978 ldr r0, [r7, #20] 8009a78: f7ff fa84 bl 8008f84 <__aeabi_fdiv> 8009a7c: 4603 mov r3, r0 8009a7e: 4619 mov r1, r3 8009a80: 6838 ldr r0, [r7, #0] 8009a82: f7ff f9cb bl 8008e1c <__aeabi_fmul> 8009a86: 4603 mov r3, r0 8009a88: 613b str r3, [r7, #16] return R_NTC; 8009a8a: 693b ldr r3, [r7, #16] } 8009a8c: 4618 mov r0, r3 8009a8e: 3718 adds r7, #24 8009a90: 46bd mov sp, r7 8009a92: bdb0 pop {r4, r5, r7, pc} 8009a94: f3af 8000 nop.w 8009a98: 00000000 .word 0x00000000 8009a9c: 40affe00 .word 0x40affe00 8009aa0: bf800000 .word 0xbf800000 08009aa4 : int16_t CONN_ReadTemp(uint8_t ch){ 8009aa4: b580 push {r7, lr} 8009aa6: b088 sub sp, #32 8009aa8: af00 add r7, sp, #0 8009aaa: 4603 mov r3, r0 8009aac: 71fb strb r3, [r7, #7] uint32_t adcValue = 0u; 8009aae: 2300 movs r3, #0 8009ab0: 61fb str r3, [r7, #28] adcValue = ch ? adc_data.ntc2_raw : adc_data.ntc1_raw; 8009ab2: 79fb ldrb r3, [r7, #7] 8009ab4: 2b00 cmp r3, #0 8009ab6: d003 beq.n 8009ac0 8009ab8: 4b1c ldr r3, [pc, #112] @ (8009b2c ) 8009aba: 88db ldrh r3, [r3, #6] 8009abc: b29b uxth r3, r3 8009abe: e002 b.n 8009ac6 8009ac0: 4b1a ldr r3, [pc, #104] @ (8009b2c ) 8009ac2: 889b ldrh r3, [r3, #4] 8009ac4: b29b uxth r3, r3 8009ac6: 61fb str r3, [r7, #28] int32_t adc_filtered = SMAFilter_Update(&conn_temp_adc_filter[ch ? 1u : 0u], (int32_t)adcValue); 8009ac8: 79fb ldrb r3, [r7, #7] 8009aca: 2b00 cmp r3, #0 8009acc: d001 beq.n 8009ad2 8009ace: 2201 movs r2, #1 8009ad0: e000 b.n 8009ad4 8009ad2: 2200 movs r2, #0 8009ad4: 4613 mov r3, r2 8009ad6: 009b lsls r3, r3, #2 8009ad8: 4413 add r3, r2 8009ada: 00db lsls r3, r3, #3 8009adc: 4a14 ldr r2, [pc, #80] @ (8009b30 ) 8009ade: 4413 add r3, r2 8009ae0: 69fa ldr r2, [r7, #28] 8009ae2: 4611 mov r1, r2 8009ae4: 4618 mov r0, r3 8009ae6: f003 fcd0 bl 800d48a 8009aea: 61b8 str r0, [r7, #24] if((uint32_t)adc_filtered > 4000u) { 8009aec: 69bb ldr r3, [r7, #24] 8009aee: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 8009af2: d901 bls.n 8009af8 return 20; //Термодатчик не подключен 8009af4: 2314 movs r3, #20 8009af6: e015 b.n 8009b24 } float Vref = 3.3; // Напряжение опорное 8009af8: 4b0e ldr r3, [pc, #56] @ (8009b34 ) 8009afa: 617b str r3, [r7, #20] float Vin = 5.0; // Входное напряжение 8009afc: 4b0e ldr r3, [pc, #56] @ (8009b38 ) 8009afe: 613b str r3, [r7, #16] float R = 1000; // Сопротивление резистора в Омах 8009b00: 4b0e ldr r3, [pc, #56] @ (8009b3c ) 8009b02: 60fb str r3, [r7, #12] float temp = pt1000_to_temperature(calculate_NTC_resistance((int)adc_filtered, Vref, Vin, R)); 8009b04: 68fb ldr r3, [r7, #12] 8009b06: 693a ldr r2, [r7, #16] 8009b08: 6979 ldr r1, [r7, #20] 8009b0a: 69b8 ldr r0, [r7, #24] 8009b0c: f7ff ff80 bl 8009a10 8009b10: 4603 mov r3, r0 8009b12: 4618 mov r0, r3 8009b14: f7ff ff58 bl 80099c8 8009b18: 60b8 str r0, [r7, #8] return (int16_t)temp; 8009b1a: 68b8 ldr r0, [r7, #8] 8009b1c: f7ff fb44 bl 80091a8 <__aeabi_f2iz> 8009b20: 4603 mov r3, r0 8009b22: b21b sxth r3, r3 } 8009b24: 4618 mov r0, r3 8009b26: 3720 adds r7, #32 8009b28: 46bd mov sp, r7 8009b2a: bd80 pop {r7, pc} 8009b2c: 20000280 .word 0x20000280 8009b30: 2000030c .word 0x2000030c 8009b34: 40533333 .word 0x40533333 8009b38: 40a00000 .word 0x40a00000 8009b3c: 447a0000 .word 0x447a0000 08009b40 : CAN_HandleTypeDef hcan1; CAN_HandleTypeDef hcan2; /* CAN1 init function */ void MX_CAN1_Init(void) { 8009b40: b580 push {r7, lr} 8009b42: af00 add r7, sp, #0 /* USER CODE END CAN1_Init 0 */ /* USER CODE BEGIN CAN1_Init 1 */ /* USER CODE END CAN1_Init 1 */ hcan1.Instance = CAN1; 8009b44: 4b17 ldr r3, [pc, #92] @ (8009ba4 ) 8009b46: 4a18 ldr r2, [pc, #96] @ (8009ba8 ) 8009b48: 601a str r2, [r3, #0] hcan1.Init.Prescaler = 8; 8009b4a: 4b16 ldr r3, [pc, #88] @ (8009ba4 ) 8009b4c: 2208 movs r2, #8 8009b4e: 605a str r2, [r3, #4] hcan1.Init.Mode = CAN_MODE_NORMAL; 8009b50: 4b14 ldr r3, [pc, #80] @ (8009ba4 ) 8009b52: 2200 movs r2, #0 8009b54: 609a str r2, [r3, #8] hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; 8009b56: 4b13 ldr r3, [pc, #76] @ (8009ba4 ) 8009b58: 2200 movs r2, #0 8009b5a: 60da str r2, [r3, #12] hcan1.Init.TimeSeg1 = CAN_BS1_15TQ; 8009b5c: 4b11 ldr r3, [pc, #68] @ (8009ba4 ) 8009b5e: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009b62: 611a str r2, [r3, #16] hcan1.Init.TimeSeg2 = CAN_BS2_2TQ; 8009b64: 4b0f ldr r3, [pc, #60] @ (8009ba4 ) 8009b66: f44f 1280 mov.w r2, #1048576 @ 0x100000 8009b6a: 615a str r2, [r3, #20] hcan1.Init.TimeTriggeredMode = DISABLE; 8009b6c: 4b0d ldr r3, [pc, #52] @ (8009ba4 ) 8009b6e: 2200 movs r2, #0 8009b70: 761a strb r2, [r3, #24] hcan1.Init.AutoBusOff = ENABLE; 8009b72: 4b0c ldr r3, [pc, #48] @ (8009ba4 ) 8009b74: 2201 movs r2, #1 8009b76: 765a strb r2, [r3, #25] hcan1.Init.AutoWakeUp = ENABLE; 8009b78: 4b0a ldr r3, [pc, #40] @ (8009ba4 ) 8009b7a: 2201 movs r2, #1 8009b7c: 769a strb r2, [r3, #26] hcan1.Init.AutoRetransmission = ENABLE; 8009b7e: 4b09 ldr r3, [pc, #36] @ (8009ba4 ) 8009b80: 2201 movs r2, #1 8009b82: 76da strb r2, [r3, #27] hcan1.Init.ReceiveFifoLocked = DISABLE; 8009b84: 4b07 ldr r3, [pc, #28] @ (8009ba4 ) 8009b86: 2200 movs r2, #0 8009b88: 771a strb r2, [r3, #28] hcan1.Init.TransmitFifoPriority = ENABLE; 8009b8a: 4b06 ldr r3, [pc, #24] @ (8009ba4 ) 8009b8c: 2201 movs r2, #1 8009b8e: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan1) != HAL_OK) 8009b90: 4804 ldr r0, [pc, #16] @ (8009ba4 ) 8009b92: f005 f90e bl 800edb2 8009b96: 4603 mov r3, r0 8009b98: 2b00 cmp r3, #0 8009b9a: d001 beq.n 8009ba0 { Error_Handler(); 8009b9c: f001 f840 bl 800ac20 } /* USER CODE BEGIN CAN1_Init 2 */ /* USER CODE END CAN1_Init 2 */ } 8009ba0: bf00 nop 8009ba2: bd80 pop {r7, pc} 8009ba4: 2000035c .word 0x2000035c 8009ba8: 40006400 .word 0x40006400 08009bac : /* CAN2 init function */ void MX_CAN2_Init(void) { 8009bac: b580 push {r7, lr} 8009bae: af00 add r7, sp, #0 /* USER CODE END CAN2_Init 0 */ /* USER CODE BEGIN CAN2_Init 1 */ /* USER CODE END CAN2_Init 1 */ hcan2.Instance = CAN2; 8009bb0: 4b17 ldr r3, [pc, #92] @ (8009c10 ) 8009bb2: 4a18 ldr r2, [pc, #96] @ (8009c14 ) 8009bb4: 601a str r2, [r3, #0] hcan2.Init.Prescaler = 16; 8009bb6: 4b16 ldr r3, [pc, #88] @ (8009c10 ) 8009bb8: 2210 movs r2, #16 8009bba: 605a str r2, [r3, #4] hcan2.Init.Mode = CAN_MODE_NORMAL; 8009bbc: 4b14 ldr r3, [pc, #80] @ (8009c10 ) 8009bbe: 2200 movs r2, #0 8009bc0: 609a str r2, [r3, #8] hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; 8009bc2: 4b13 ldr r3, [pc, #76] @ (8009c10 ) 8009bc4: 2200 movs r2, #0 8009bc6: 60da str r2, [r3, #12] hcan2.Init.TimeSeg1 = CAN_BS1_15TQ; 8009bc8: 4b11 ldr r3, [pc, #68] @ (8009c10 ) 8009bca: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009bce: 611a str r2, [r3, #16] hcan2.Init.TimeSeg2 = CAN_BS2_2TQ; 8009bd0: 4b0f ldr r3, [pc, #60] @ (8009c10 ) 8009bd2: f44f 1280 mov.w r2, #1048576 @ 0x100000 8009bd6: 615a str r2, [r3, #20] hcan2.Init.TimeTriggeredMode = DISABLE; 8009bd8: 4b0d ldr r3, [pc, #52] @ (8009c10 ) 8009bda: 2200 movs r2, #0 8009bdc: 761a strb r2, [r3, #24] hcan2.Init.AutoBusOff = ENABLE; 8009bde: 4b0c ldr r3, [pc, #48] @ (8009c10 ) 8009be0: 2201 movs r2, #1 8009be2: 765a strb r2, [r3, #25] hcan2.Init.AutoWakeUp = ENABLE; 8009be4: 4b0a ldr r3, [pc, #40] @ (8009c10 ) 8009be6: 2201 movs r2, #1 8009be8: 769a strb r2, [r3, #26] hcan2.Init.AutoRetransmission = ENABLE; 8009bea: 4b09 ldr r3, [pc, #36] @ (8009c10 ) 8009bec: 2201 movs r2, #1 8009bee: 76da strb r2, [r3, #27] hcan2.Init.ReceiveFifoLocked = DISABLE; 8009bf0: 4b07 ldr r3, [pc, #28] @ (8009c10 ) 8009bf2: 2200 movs r2, #0 8009bf4: 771a strb r2, [r3, #28] hcan2.Init.TransmitFifoPriority = ENABLE; 8009bf6: 4b06 ldr r3, [pc, #24] @ (8009c10 ) 8009bf8: 2201 movs r2, #1 8009bfa: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan2) != HAL_OK) 8009bfc: 4804 ldr r0, [pc, #16] @ (8009c10 ) 8009bfe: f005 f8d8 bl 800edb2 8009c02: 4603 mov r3, r0 8009c04: 2b00 cmp r3, #0 8009c06: d001 beq.n 8009c0c { Error_Handler(); 8009c08: f001 f80a bl 800ac20 } /* USER CODE BEGIN CAN2_Init 2 */ /* USER CODE END CAN2_Init 2 */ } 8009c0c: bf00 nop 8009c0e: bd80 pop {r7, pc} 8009c10: 20000384 .word 0x20000384 8009c14: 40006800 .word 0x40006800 08009c18 : static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0; void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) { 8009c18: b580 push {r7, lr} 8009c1a: b08e sub sp, #56 @ 0x38 8009c1c: af00 add r7, sp, #0 8009c1e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8009c20: f107 0320 add.w r3, r7, #32 8009c24: 2200 movs r2, #0 8009c26: 601a str r2, [r3, #0] 8009c28: 605a str r2, [r3, #4] 8009c2a: 609a str r2, [r3, #8] 8009c2c: 60da str r2, [r3, #12] if(canHandle->Instance==CAN1) 8009c2e: 687b ldr r3, [r7, #4] 8009c30: 681b ldr r3, [r3, #0] 8009c32: 4a61 ldr r2, [pc, #388] @ (8009db8 ) 8009c34: 4293 cmp r3, r2 8009c36: d153 bne.n 8009ce0 { /* USER CODE BEGIN CAN1_MspInit 0 */ /* USER CODE END CAN1_MspInit 0 */ /* CAN1 clock enable */ HAL_RCC_CAN1_CLK_ENABLED++; 8009c38: 4b60 ldr r3, [pc, #384] @ (8009dbc ) 8009c3a: 681b ldr r3, [r3, #0] 8009c3c: 3301 adds r3, #1 8009c3e: 4a5f ldr r2, [pc, #380] @ (8009dbc ) 8009c40: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009c42: 4b5e ldr r3, [pc, #376] @ (8009dbc ) 8009c44: 681b ldr r3, [r3, #0] 8009c46: 2b01 cmp r3, #1 8009c48: d10b bne.n 8009c62 __HAL_RCC_CAN1_CLK_ENABLE(); 8009c4a: 4b5d ldr r3, [pc, #372] @ (8009dc0 ) 8009c4c: 69db ldr r3, [r3, #28] 8009c4e: 4a5c ldr r2, [pc, #368] @ (8009dc0 ) 8009c50: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009c54: 61d3 str r3, [r2, #28] 8009c56: 4b5a ldr r3, [pc, #360] @ (8009dc0 ) 8009c58: 69db ldr r3, [r3, #28] 8009c5a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009c5e: 61fb str r3, [r7, #28] 8009c60: 69fb ldr r3, [r7, #28] } __HAL_RCC_GPIOD_CLK_ENABLE(); 8009c62: 4b57 ldr r3, [pc, #348] @ (8009dc0 ) 8009c64: 699b ldr r3, [r3, #24] 8009c66: 4a56 ldr r2, [pc, #344] @ (8009dc0 ) 8009c68: f043 0320 orr.w r3, r3, #32 8009c6c: 6193 str r3, [r2, #24] 8009c6e: 4b54 ldr r3, [pc, #336] @ (8009dc0 ) 8009c70: 699b ldr r3, [r3, #24] 8009c72: f003 0320 and.w r3, r3, #32 8009c76: 61bb str r3, [r7, #24] 8009c78: 69bb ldr r3, [r7, #24] /**CAN1 GPIO Configuration PD0 ------> CAN1_RX PD1 ------> CAN1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0; 8009c7a: 2301 movs r3, #1 8009c7c: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009c7e: 2300 movs r3, #0 8009c80: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009c82: 2300 movs r3, #0 8009c84: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009c86: f107 0320 add.w r3, r7, #32 8009c8a: 4619 mov r1, r3 8009c8c: 484d ldr r0, [pc, #308] @ (8009dc4 ) 8009c8e: f006 fd1d bl 80106cc GPIO_InitStruct.Pin = GPIO_PIN_1; 8009c92: 2302 movs r3, #2 8009c94: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009c96: 2302 movs r3, #2 8009c98: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009c9a: 2303 movs r3, #3 8009c9c: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009c9e: f107 0320 add.w r3, r7, #32 8009ca2: 4619 mov r1, r3 8009ca4: 4847 ldr r0, [pc, #284] @ (8009dc4 ) 8009ca6: f006 fd11 bl 80106cc __HAL_AFIO_REMAP_CAN1_3(); 8009caa: 4b47 ldr r3, [pc, #284] @ (8009dc8 ) 8009cac: 685b ldr r3, [r3, #4] 8009cae: 633b str r3, [r7, #48] @ 0x30 8009cb0: 6b3b ldr r3, [r7, #48] @ 0x30 8009cb2: f423 43c0 bic.w r3, r3, #24576 @ 0x6000 8009cb6: 633b str r3, [r7, #48] @ 0x30 8009cb8: 6b3b ldr r3, [r7, #48] @ 0x30 8009cba: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009cbe: 633b str r3, [r7, #48] @ 0x30 8009cc0: 6b3b ldr r3, [r7, #48] @ 0x30 8009cc2: f443 43c0 orr.w r3, r3, #24576 @ 0x6000 8009cc6: 633b str r3, [r7, #48] @ 0x30 8009cc8: 4a3f ldr r2, [pc, #252] @ (8009dc8 ) 8009cca: 6b3b ldr r3, [r7, #48] @ 0x30 8009ccc: 6053 str r3, [r2, #4] /* CAN1 interrupt Init */ HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 3, 0); 8009cce: 2200 movs r2, #0 8009cd0: 2103 movs r1, #3 8009cd2: 2014 movs r0, #20 8009cd4: f006 f819 bl 800fd0a HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn); 8009cd8: 2014 movs r0, #20 8009cda: f006 f832 bl 800fd42 HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); /* USER CODE BEGIN CAN2_MspInit 1 */ /* USER CODE END CAN2_MspInit 1 */ } } 8009cde: e067 b.n 8009db0 else if(canHandle->Instance==CAN2) 8009ce0: 687b ldr r3, [r7, #4] 8009ce2: 681b ldr r3, [r3, #0] 8009ce4: 4a39 ldr r2, [pc, #228] @ (8009dcc ) 8009ce6: 4293 cmp r3, r2 8009ce8: d162 bne.n 8009db0 __HAL_RCC_CAN2_CLK_ENABLE(); 8009cea: 4b35 ldr r3, [pc, #212] @ (8009dc0 ) 8009cec: 69db ldr r3, [r3, #28] 8009cee: 4a34 ldr r2, [pc, #208] @ (8009dc0 ) 8009cf0: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 8009cf4: 61d3 str r3, [r2, #28] 8009cf6: 4b32 ldr r3, [pc, #200] @ (8009dc0 ) 8009cf8: 69db ldr r3, [r3, #28] 8009cfa: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8009cfe: 617b str r3, [r7, #20] 8009d00: 697b ldr r3, [r7, #20] HAL_RCC_CAN1_CLK_ENABLED++; 8009d02: 4b2e ldr r3, [pc, #184] @ (8009dbc ) 8009d04: 681b ldr r3, [r3, #0] 8009d06: 3301 adds r3, #1 8009d08: 4a2c ldr r2, [pc, #176] @ (8009dbc ) 8009d0a: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009d0c: 4b2b ldr r3, [pc, #172] @ (8009dbc ) 8009d0e: 681b ldr r3, [r3, #0] 8009d10: 2b01 cmp r3, #1 8009d12: d10b bne.n 8009d2c __HAL_RCC_CAN1_CLK_ENABLE(); 8009d14: 4b2a ldr r3, [pc, #168] @ (8009dc0 ) 8009d16: 69db ldr r3, [r3, #28] 8009d18: 4a29 ldr r2, [pc, #164] @ (8009dc0 ) 8009d1a: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009d1e: 61d3 str r3, [r2, #28] 8009d20: 4b27 ldr r3, [pc, #156] @ (8009dc0 ) 8009d22: 69db ldr r3, [r3, #28] 8009d24: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009d28: 613b str r3, [r7, #16] 8009d2a: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8009d2c: 4b24 ldr r3, [pc, #144] @ (8009dc0 ) 8009d2e: 699b ldr r3, [r3, #24] 8009d30: 4a23 ldr r2, [pc, #140] @ (8009dc0 ) 8009d32: f043 0308 orr.w r3, r3, #8 8009d36: 6193 str r3, [r2, #24] 8009d38: 4b21 ldr r3, [pc, #132] @ (8009dc0 ) 8009d3a: 699b ldr r3, [r3, #24] 8009d3c: f003 0308 and.w r3, r3, #8 8009d40: 60fb str r3, [r7, #12] 8009d42: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_5; 8009d44: 2320 movs r3, #32 8009d46: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009d48: 2300 movs r3, #0 8009d4a: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009d4c: 2300 movs r3, #0 8009d4e: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009d50: f107 0320 add.w r3, r7, #32 8009d54: 4619 mov r1, r3 8009d56: 481e ldr r0, [pc, #120] @ (8009dd0 ) 8009d58: f006 fcb8 bl 80106cc GPIO_InitStruct.Pin = GPIO_PIN_6; 8009d5c: 2340 movs r3, #64 @ 0x40 8009d5e: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009d60: 2302 movs r3, #2 8009d62: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009d64: 2303 movs r3, #3 8009d66: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009d68: f107 0320 add.w r3, r7, #32 8009d6c: 4619 mov r1, r3 8009d6e: 4818 ldr r0, [pc, #96] @ (8009dd0 ) 8009d70: f006 fcac bl 80106cc __HAL_AFIO_REMAP_CAN2_ENABLE(); 8009d74: 4b14 ldr r3, [pc, #80] @ (8009dc8 ) 8009d76: 685b ldr r3, [r3, #4] 8009d78: 637b str r3, [r7, #52] @ 0x34 8009d7a: 6b7b ldr r3, [r7, #52] @ 0x34 8009d7c: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009d80: 637b str r3, [r7, #52] @ 0x34 8009d82: 6b7b ldr r3, [r7, #52] @ 0x34 8009d84: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8009d88: 637b str r3, [r7, #52] @ 0x34 8009d8a: 4a0f ldr r2, [pc, #60] @ (8009dc8 ) 8009d8c: 6b7b ldr r3, [r7, #52] @ 0x34 8009d8e: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(CAN2_TX_IRQn, 0, 0); 8009d90: 2200 movs r2, #0 8009d92: 2100 movs r1, #0 8009d94: 203f movs r0, #63 @ 0x3f 8009d96: f005 ffb8 bl 800fd0a HAL_NVIC_EnableIRQ(CAN2_TX_IRQn); 8009d9a: 203f movs r0, #63 @ 0x3f 8009d9c: f005 ffd1 bl 800fd42 HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 3, 0); 8009da0: 2200 movs r2, #0 8009da2: 2103 movs r1, #3 8009da4: 2041 movs r0, #65 @ 0x41 8009da6: f005 ffb0 bl 800fd0a HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); 8009daa: 2041 movs r0, #65 @ 0x41 8009dac: f005 ffc9 bl 800fd42 } 8009db0: bf00 nop 8009db2: 3738 adds r7, #56 @ 0x38 8009db4: 46bd mov sp, r7 8009db6: bd80 pop {r7, pc} 8009db8: 40006400 .word 0x40006400 8009dbc: 200003ac .word 0x200003ac 8009dc0: 40021000 .word 0x40021000 8009dc4: 40011400 .word 0x40011400 8009dc8: 40010000 .word 0x40010000 8009dcc: 40006800 .word 0x40006800 8009dd0: 40010c00 .word 0x40010c00 08009dd4 : #include "psu_control.h" ChargingConnector_t CONN; CONN_State_t connectorState; void CONN_Init(){ 8009dd4: b480 push {r7} 8009dd6: af00 add r7, sp, #0 CONN.connControl = CMD_NONE; 8009dd8: 4b08 ldr r3, [pc, #32] @ (8009dfc ) 8009dda: 2200 movs r2, #0 8009ddc: 701a strb r2, [r3, #0] CONN.connState = Unknown; 8009dde: 4b07 ldr r3, [pc, #28] @ (8009dfc ) 8009de0: 2200 movs r2, #0 8009de2: 705a strb r2, [r3, #1] CONN.RequestedVoltage = PSU_MIN_VOLTAGE; 8009de4: 4b05 ldr r3, [pc, #20] @ (8009dfc ) 8009de6: 2200 movs r2, #0 8009de8: f062 0269 orn r2, r2, #105 @ 0x69 8009dec: 73da strb r2, [r3, #15] 8009dee: 2200 movs r2, #0 8009df0: 741a strb r2, [r3, #16] } 8009df2: bf00 nop 8009df4: 46bd mov sp, r7 8009df6: bc80 pop {r7} 8009df8: 4770 bx lr 8009dfa: bf00 nop 8009dfc: 200003b0 .word 0x200003b0 08009e00 : void CONN_Loop(){ 8009e00: b580 push {r7, lr} 8009e02: af00 add r7, sp, #0 static CONN_State_t last_connState = Unknown; if(last_connState != CONN.connState){ 8009e04: 4b1a ldr r3, [pc, #104] @ (8009e70 ) 8009e06: 785a ldrb r2, [r3, #1] 8009e08: 4b1a ldr r3, [pc, #104] @ (8009e74 ) 8009e0a: 781b ldrb r3, [r3, #0] 8009e0c: 429a cmp r2, r3 8009e0e: d006 beq.n 8009e1e last_connState = CONN.connState; 8009e10: 4b17 ldr r3, [pc, #92] @ (8009e70 ) 8009e12: 785a ldrb r2, [r3, #1] 8009e14: 4b17 ldr r3, [pc, #92] @ (8009e74 ) 8009e16: 701a strb r2, [r3, #0] CONN.connControl = CMD_NONE; 8009e18: 4b15 ldr r3, [pc, #84] @ (8009e70 ) 8009e1a: 2200 movs r2, #0 8009e1c: 701a strb r2, [r3, #0] } if(PSU0.cont_fault){ 8009e1e: 4b16 ldr r3, [pc, #88] @ (8009e78 ) 8009e20: 7b1b ldrb r3, [r3, #12] 8009e22: 2b00 cmp r3, #0 8009e24: d003 beq.n 8009e2e CONN.chargingError = CONN_ERR_CONTACTOR; 8009e26: 4b12 ldr r3, [pc, #72] @ (8009e70 ) 8009e28: 2207 movs r2, #7 8009e2a: 775a strb r2, [r3, #29] 8009e2c: e00e b.n 8009e4c } else if(PSU0.psu_fault){ 8009e2e: 4b12 ldr r3, [pc, #72] @ (8009e78 ) 8009e30: 7b5b ldrb r3, [r3, #13] 8009e32: 2b00 cmp r3, #0 8009e34: d003 beq.n 8009e3e CONN.chargingError = CONN_ERR_PSU_FAULT; 8009e36: 4b0e ldr r3, [pc, #56] @ (8009e70 ) 8009e38: 220a movs r2, #10 8009e3a: 775a strb r2, [r3, #29] 8009e3c: e006 b.n 8009e4c }else if (CONN.EvConnected == 0){ 8009e3e: 4b0c ldr r3, [pc, #48] @ (8009e70 ) 8009e40: 7f9b ldrb r3, [r3, #30] 8009e42: 2b00 cmp r3, #0 8009e44: d102 bne.n 8009e4c CONN.chargingError = CONN_NO_ERROR; 8009e46: 4b0a ldr r3, [pc, #40] @ (8009e70 ) 8009e48: 2200 movs r2, #0 8009e4a: 775a strb r2, [r3, #29] } if(ED_TraceWarning(CONN.chargingError, 0)) { 8009e4c: 4b08 ldr r3, [pc, #32] @ (8009e70 ) 8009e4e: 7f5b ldrb r3, [r3, #29] 8009e50: 2100 movs r1, #0 8009e52: 4618 mov r0, r3 8009e54: f000 fd26 bl 800a8a4 8009e58: 4603 mov r3, r0 8009e5a: 2b00 cmp r3, #0 8009e5c: d006 beq.n 8009e6c log_printf(LOG_WARN, "CONN0 Error: %d\n", (int)CONN.chargingError); 8009e5e: 4b04 ldr r3, [pc, #16] @ (8009e70 ) 8009e60: 7f5b ldrb r3, [r3, #29] 8009e62: 461a mov r2, r3 8009e64: 4905 ldr r1, [pc, #20] @ (8009e7c ) 8009e66: 2005 movs r0, #5 8009e68: f000 fb44 bl 800a4f4 } } 8009e6c: bf00 nop 8009e6e: bd80 pop {r7, pc} 8009e70: 200003b0 .word 0x200003b0 8009e74: 200003d0 .word 0x200003d0 8009e78: 20000904 .word 0x20000904 8009e7c: 08016e98 .word 0x08016e98 08009e80 : void CONN_SetState(CONN_State_t state){ 8009e80: b580 push {r7, lr} 8009e82: b082 sub sp, #8 8009e84: af00 add r7, sp, #0 8009e86: 4603 mov r3, r0 8009e88: 71fb strb r3, [r7, #7] if (connectorState == state) { 8009e8a: 4b41 ldr r3, [pc, #260] @ (8009f90 ) 8009e8c: 781b ldrb r3, [r3, #0] 8009e8e: 79fa ldrb r2, [r7, #7] 8009e90: 429a cmp r2, r3 8009e92: d103 bne.n 8009e9c CONN.connState = state; 8009e94: 4a3f ldr r2, [pc, #252] @ (8009f94 ) 8009e96: 79fb ldrb r3, [r7, #7] 8009e98: 7053 strb r3, [r2, #1] return; 8009e9a: e075 b.n 8009f88 } connectorState = state; 8009e9c: 4a3c ldr r2, [pc, #240] @ (8009f90 ) 8009e9e: 79fb ldrb r3, [r7, #7] 8009ea0: 7013 strb r3, [r2, #0] if(connectorState == Unknown) log_printf(LOG_INFO, "Connector: Unknown\n"); 8009ea2: 4b3b ldr r3, [pc, #236] @ (8009f90 ) 8009ea4: 781b ldrb r3, [r3, #0] 8009ea6: 2b00 cmp r3, #0 8009ea8: d103 bne.n 8009eb2 8009eaa: 493b ldr r1, [pc, #236] @ (8009f98 ) 8009eac: 2007 movs r0, #7 8009eae: f000 fb21 bl 800a4f4 if(connectorState == Unplugged) log_printf(LOG_INFO, "Connector: Unplugged\n"); 8009eb2: 4b37 ldr r3, [pc, #220] @ (8009f90 ) 8009eb4: 781b ldrb r3, [r3, #0] 8009eb6: 2b01 cmp r3, #1 8009eb8: d103 bne.n 8009ec2 8009eba: 4938 ldr r1, [pc, #224] @ (8009f9c ) 8009ebc: 2007 movs r0, #7 8009ebe: f000 fb19 bl 800a4f4 if(connectorState == Disabled) log_printf(LOG_INFO, "Connector: Disabled\n"); 8009ec2: 4b33 ldr r3, [pc, #204] @ (8009f90 ) 8009ec4: 781b ldrb r3, [r3, #0] 8009ec6: 2b02 cmp r3, #2 8009ec8: d103 bne.n 8009ed2 8009eca: 4935 ldr r1, [pc, #212] @ (8009fa0 ) 8009ecc: 2007 movs r0, #7 8009ece: f000 fb11 bl 800a4f4 if(connectorState == Preparing) log_printf(LOG_INFO, "Connector: Preparing\n"); 8009ed2: 4b2f ldr r3, [pc, #188] @ (8009f90 ) 8009ed4: 781b ldrb r3, [r3, #0] 8009ed6: 2b03 cmp r3, #3 8009ed8: d103 bne.n 8009ee2 8009eda: 4932 ldr r1, [pc, #200] @ (8009fa4 ) 8009edc: 2007 movs r0, #7 8009ede: f000 fb09 bl 800a4f4 if(connectorState == AuthRequired) log_printf(LOG_INFO, "Connector: AuthRequired\n"); 8009ee2: 4b2b ldr r3, [pc, #172] @ (8009f90 ) 8009ee4: 781b ldrb r3, [r3, #0] 8009ee6: 2b04 cmp r3, #4 8009ee8: d103 bne.n 8009ef2 8009eea: 492f ldr r1, [pc, #188] @ (8009fa8 ) 8009eec: 2007 movs r0, #7 8009eee: f000 fb01 bl 800a4f4 if(connectorState == WaitingForEnergy) log_printf(LOG_INFO, "Connector: WaitingForEnergy\n"); 8009ef2: 4b27 ldr r3, [pc, #156] @ (8009f90 ) 8009ef4: 781b ldrb r3, [r3, #0] 8009ef6: 2b05 cmp r3, #5 8009ef8: d103 bne.n 8009f02 8009efa: 492c ldr r1, [pc, #176] @ (8009fac ) 8009efc: 2007 movs r0, #7 8009efe: f000 faf9 bl 800a4f4 if(connectorState == ChargingPausedEV) log_printf(LOG_INFO, "Connector: ChargingPausedEV\n"); 8009f02: 4b23 ldr r3, [pc, #140] @ (8009f90 ) 8009f04: 781b ldrb r3, [r3, #0] 8009f06: 2b06 cmp r3, #6 8009f08: d103 bne.n 8009f12 8009f0a: 4929 ldr r1, [pc, #164] @ (8009fb0 ) 8009f0c: 2007 movs r0, #7 8009f0e: f000 faf1 bl 800a4f4 if(connectorState == ChargingPausedEVSE) log_printf(LOG_INFO, "Connector: ChargingPausedEVSE\n"); 8009f12: 4b1f ldr r3, [pc, #124] @ (8009f90 ) 8009f14: 781b ldrb r3, [r3, #0] 8009f16: 2b07 cmp r3, #7 8009f18: d103 bne.n 8009f22 8009f1a: 4926 ldr r1, [pc, #152] @ (8009fb4 ) 8009f1c: 2007 movs r0, #7 8009f1e: f000 fae9 bl 800a4f4 if(connectorState == Charging) log_printf(LOG_INFO, "Connector: Charging\n"); 8009f22: 4b1b ldr r3, [pc, #108] @ (8009f90 ) 8009f24: 781b ldrb r3, [r3, #0] 8009f26: 2b08 cmp r3, #8 8009f28: d103 bne.n 8009f32 8009f2a: 4923 ldr r1, [pc, #140] @ (8009fb8 ) 8009f2c: 2007 movs r0, #7 8009f2e: f000 fae1 bl 800a4f4 if(connectorState == AuthTimeout) log_printf(LOG_INFO, "Connector: AuthTimeout\n"); 8009f32: 4b17 ldr r3, [pc, #92] @ (8009f90 ) 8009f34: 781b ldrb r3, [r3, #0] 8009f36: 2b09 cmp r3, #9 8009f38: d103 bne.n 8009f42 8009f3a: 4920 ldr r1, [pc, #128] @ (8009fbc ) 8009f3c: 2007 movs r0, #7 8009f3e: f000 fad9 bl 800a4f4 if(connectorState == Finished) log_printf(LOG_INFO, "Connector: Finished\n"); 8009f42: 4b13 ldr r3, [pc, #76] @ (8009f90 ) 8009f44: 781b ldrb r3, [r3, #0] 8009f46: 2b0a cmp r3, #10 8009f48: d103 bne.n 8009f52 8009f4a: 491d ldr r1, [pc, #116] @ (8009fc0 ) 8009f4c: 2007 movs r0, #7 8009f4e: f000 fad1 bl 800a4f4 if(connectorState == FinishedEVSE) log_printf(LOG_INFO, "Connector: FinishedEVSE\n"); 8009f52: 4b0f ldr r3, [pc, #60] @ (8009f90 ) 8009f54: 781b ldrb r3, [r3, #0] 8009f56: 2b0b cmp r3, #11 8009f58: d103 bne.n 8009f62 8009f5a: 491a ldr r1, [pc, #104] @ (8009fc4 ) 8009f5c: 2007 movs r0, #7 8009f5e: f000 fac9 bl 800a4f4 if(connectorState == FinishedEV) log_printf(LOG_INFO, "Connector: FinishedEV\n"); 8009f62: 4b0b ldr r3, [pc, #44] @ (8009f90 ) 8009f64: 781b ldrb r3, [r3, #0] 8009f66: 2b0c cmp r3, #12 8009f68: d103 bne.n 8009f72 8009f6a: 4917 ldr r1, [pc, #92] @ (8009fc8 ) 8009f6c: 2007 movs r0, #7 8009f6e: f000 fac1 bl 800a4f4 if(connectorState == Replugging) log_printf(LOG_INFO, "Connector: Replugging\n"); 8009f72: 4b07 ldr r3, [pc, #28] @ (8009f90 ) 8009f74: 781b ldrb r3, [r3, #0] 8009f76: 2b0d cmp r3, #13 8009f78: d103 bne.n 8009f82 8009f7a: 4914 ldr r1, [pc, #80] @ (8009fcc ) 8009f7c: 2007 movs r0, #7 8009f7e: f000 fab9 bl 800a4f4 CONN.connState = state; 8009f82: 4a04 ldr r2, [pc, #16] @ (8009f94 ) 8009f84: 79fb ldrb r3, [r7, #7] 8009f86: 7053 strb r3, [r2, #1] } 8009f88: 3708 adds r7, #8 8009f8a: 46bd mov sp, r7 8009f8c: bd80 pop {r7, pc} 8009f8e: bf00 nop 8009f90: 200003cf .word 0x200003cf 8009f94: 200003b0 .word 0x200003b0 8009f98: 08016eac .word 0x08016eac 8009f9c: 08016ec0 .word 0x08016ec0 8009fa0: 08016ed8 .word 0x08016ed8 8009fa4: 08016ef0 .word 0x08016ef0 8009fa8: 08016f08 .word 0x08016f08 8009fac: 08016f24 .word 0x08016f24 8009fb0: 08016f44 .word 0x08016f44 8009fb4: 08016f64 .word 0x08016f64 8009fb8: 08016f84 .word 0x08016f84 8009fbc: 08016f9c .word 0x08016f9c 8009fc0: 08016fb4 .word 0x08016fb4 8009fc4: 08016fcc .word 0x08016fcc 8009fc8: 08016fe8 .word 0x08016fe8 8009fcc: 08017000 .word 0x08017000 08009fd0 : CP_State_t cp_state_buffer = EV_STATE_ACQUIRING; #define VREFINT_CAL_ADDR ((uint16_t*)0x1FFFF7BA) // для STM32F1! static int32_t CP_ReadVoltageMv(void) { 8009fd0: b480 push {r7} 8009fd2: b087 sub sp, #28 8009fd4: af00 add r7, sp, #0 uint32_t adc_cp = adc_data.cp_raw; 8009fd6: 4b13 ldr r3, [pc, #76] @ (800a024 ) 8009fd8: 885b ldrh r3, [r3, #2] 8009fda: b29b uxth r3, r3 8009fdc: 617b str r3, [r7, #20] uint32_t adc_vref = adc_data.vrefint_raw; // нужно измерять! 8009fde: 4b11 ldr r3, [pc, #68] @ (800a024 ) 8009fe0: 895b ldrh r3, [r3, #10] 8009fe2: b29b uxth r3, r3 8009fe4: 613b str r3, [r7, #16] // VREFINT в мВ (берётся из даташита или калибровки MCU) const int32_t VREFINT_MV = 1210; 8009fe6: f240 43ba movw r3, #1210 @ 0x4ba 8009fea: 60fb str r3, [r7, #12] // напряжение на входе АЦП int32_t v_adc_mv = (adc_cp * VREFINT_MV) / adc_vref; 8009fec: 68fb ldr r3, [r7, #12] 8009fee: 697a ldr r2, [r7, #20] 8009ff0: fb03 f202 mul.w r2, r3, r2 8009ff4: 693b ldr r3, [r7, #16] 8009ff6: fbb2 f3f3 udiv r3, r2, r3 8009ffa: 60bb str r3, [r7, #8] // дальше твоя формула int32_t v_out_mv = ((v_adc_mv - 1723) * 7704) / 1000; 8009ffc: 68bb ldr r3, [r7, #8] 8009ffe: f2a3 63bb subw r3, r3, #1723 @ 0x6bb 800a002: f641 6218 movw r2, #7704 @ 0x1e18 800a006: fb02 f303 mul.w r3, r2, r3 800a00a: 4a07 ldr r2, [pc, #28] @ (800a028 ) 800a00c: fb82 1203 smull r1, r2, r2, r3 800a010: 1192 asrs r2, r2, #6 800a012: 17db asrs r3, r3, #31 800a014: 1ad3 subs r3, r2, r3 800a016: 607b str r3, [r7, #4] return v_out_mv; 800a018: 687b ldr r3, [r7, #4] } 800a01a: 4618 mov r0, r3 800a01c: 371c adds r7, #28 800a01e: 46bd mov sp, r7 800a020: bc80 pop {r7} 800a022: 4770 bx lr 800a024: 20000280 .word 0x20000280 800a028: 10624dd3 .word 0x10624dd3 0800a02c : void CP_Init(void) { 800a02c: b580 push {r7, lr} 800a02e: af00 add r7, sp, #0 /* TIM3_CH2 (PA7): set 1kHz PWM like original CCS logic. */ htim3.Instance->PSC = 160 - 1; 800a030: 4b0e ldr r3, [pc, #56] @ (800a06c ) 800a032: 681b ldr r3, [r3, #0] 800a034: 229f movs r2, #159 @ 0x9f 800a036: 629a str r2, [r3, #40] @ 0x28 htim3.Instance->ARR = MAX_DUTY - 1; 800a038: 4b0c ldr r3, [pc, #48] @ (800a06c ) 800a03a: 681b ldr r3, [r3, #0] 800a03c: f240 12c1 movw r2, #449 @ 0x1c1 800a040: 62da str r2, [r3, #44] @ 0x2c #if DUTY_INVERT == 0 htim3.Instance->CCR2 = MAX_DUTY; 800a042: 4b0a ldr r3, [pc, #40] @ (800a06c ) 800a044: 681b ldr r3, [r3, #0] 800a046: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a04a: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = MAX_DUTY + 5; 800a04c: 4b07 ldr r3, [pc, #28] @ (800a06c ) 800a04e: 681b ldr r3, [r3, #0] 800a050: f240 12c7 movw r2, #455 @ 0x1c7 800a054: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = 0; htim3.Instance->CCR1 = 0; #endif HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_2); 800a056: 2104 movs r1, #4 800a058: 4804 ldr r0, [pc, #16] @ (800a06c ) 800a05a: f008 f809 bl 8012070 HAL_TIM_OC_Start(&htim3, TIM_CHANNEL_1); 800a05e: 2100 movs r1, #0 800a060: 4802 ldr r0, [pc, #8] @ (800a06c ) 800a062: f007 ff03 bl 8011e6c } 800a066: bf00 nop 800a068: bd80 pop {r7, pc} 800a06a: bf00 nop 800a06c: 200011c8 .word 0x200011c8 0800a070 : void CP_SetDuty(uint8_t percentage) { 800a070: b480 push {r7} 800a072: b085 sub sp, #20 800a074: af00 add r7, sp, #0 800a076: 4603 mov r3, r0 800a078: 71fb strb r3, [r7, #7] uint32_t pwmduty = MAX_DUTY * percentage / 100; 800a07a: 79fb ldrb r3, [r7, #7] 800a07c: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a080: fb02 f303 mul.w r3, r2, r3 800a084: 4a0b ldr r2, [pc, #44] @ (800a0b4 ) 800a086: fb82 1203 smull r1, r2, r2, r3 800a08a: 1152 asrs r2, r2, #5 800a08c: 17db asrs r3, r3, #31 800a08e: 1ad3 subs r3, r2, r3 800a090: 60fb str r3, [r7, #12] cp_duty = percentage; 800a092: 4a09 ldr r2, [pc, #36] @ (800a0b8 ) 800a094: 79fb ldrb r3, [r7, #7] 800a096: 7013 strb r3, [r2, #0] #if DUTY_INVERT == 0 htim3.Instance->CCR2 = pwmduty; 800a098: 4b08 ldr r3, [pc, #32] @ (800a0bc ) 800a09a: 681b ldr r3, [r3, #0] 800a09c: 68fa ldr r2, [r7, #12] 800a09e: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = 0 + 1; 800a0a0: 4b06 ldr r3, [pc, #24] @ (800a0bc ) 800a0a2: 681b ldr r3, [r3, #0] 800a0a4: 2201 movs r2, #1 800a0a6: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = MAX_DUTY - pwmduty; htim3.Instance->CCR1 = MAX_DUTY - pwmduty + 5; #endif } 800a0a8: bf00 nop 800a0aa: 3714 adds r7, #20 800a0ac: 46bd mov sp, r7 800a0ae: bc80 pop {r7} 800a0b0: 4770 bx lr 800a0b2: bf00 nop 800a0b4: 51eb851f .word 0x51eb851f 800a0b8: 200003d8 .word 0x200003d8 800a0bc: 200011c8 .word 0x200011c8 0800a0c0 : uint8_t CP_GetDuty(void) { 800a0c0: b480 push {r7} 800a0c2: af00 add r7, sp, #0 return cp_duty; 800a0c4: 4b02 ldr r3, [pc, #8] @ (800a0d0 ) 800a0c6: 781b ldrb r3, [r3, #0] } 800a0c8: 4618 mov r0, r3 800a0ca: 46bd mov sp, r7 800a0cc: bc80 pop {r7} 800a0ce: 4770 bx lr 800a0d0: 200003d8 .word 0x200003d8 0800a0d4 : int32_t CP_GetVoltage(void) { 800a0d4: b580 push {r7, lr} 800a0d6: af00 add r7, sp, #0 cp_voltage_mv = CP_ReadVoltageMv(); 800a0d8: f7ff ff7a bl 8009fd0 800a0dc: 4603 mov r3, r0 800a0de: 4a03 ldr r2, [pc, #12] @ (800a0ec ) 800a0e0: 6013 str r3, [r2, #0] return cp_voltage_mv; 800a0e2: 4b02 ldr r3, [pc, #8] @ (800a0ec ) 800a0e4: 681b ldr r3, [r3, #0] } 800a0e6: 4618 mov r0, r3 800a0e8: bd80 pop {r7, pc} 800a0ea: bf00 nop 800a0ec: 200003d4 .word 0x200003d4 0800a0f0 : CP_State_t CP_GetState(void) { 800a0f0: b580 push {r7, lr} 800a0f2: b082 sub sp, #8 800a0f4: af00 add r7, sp, #0 int32_t voltage_real = CP_GetVoltage(); 800a0f6: f7ff ffed bl 800a0d4 800a0fa: 6078 str r0, [r7, #4] if(fake_cp_state != EV_STATE_ACQUIRING) { 800a0fc: 4b21 ldr r3, [pc, #132] @ (800a184 ) 800a0fe: 781b ldrb r3, [r3, #0] 800a100: 2b06 cmp r3, #6 800a102: d002 beq.n 800a10a return fake_cp_state; 800a104: 4b1f ldr r3, [pc, #124] @ (800a184 ) 800a106: 781b ldrb r3, [r3, #0] 800a108: e038 b.n 800a17c } if (voltage_real >= (12000-1000)) { 800a10a: 687b ldr r3, [r7, #4] 800a10c: f642 22f7 movw r2, #10999 @ 0x2af7 800a110: 4293 cmp r3, r2 800a112: dd01 ble.n 800a118 return EV_STATE_A_IDLE; 800a114: 2300 movs r3, #0 800a116: e031 b.n 800a17c } else if (voltage_real >= (9000-1000) && voltage_real <= (9000+1000)) { 800a118: 687b ldr r3, [r7, #4] 800a11a: f5b3 5ffa cmp.w r3, #8000 @ 0x1f40 800a11e: db06 blt.n 800a12e 800a120: 687b ldr r3, [r7, #4] 800a122: f242 7210 movw r2, #10000 @ 0x2710 800a126: 4293 cmp r3, r2 800a128: dc01 bgt.n 800a12e return EV_STATE_B_CONN_PREP; 800a12a: 2301 movs r3, #1 800a12c: e026 b.n 800a17c } else if (voltage_real >= (6000-1000) && voltage_real <= (6000+1000)) { 800a12e: 687b ldr r3, [r7, #4] 800a130: f241 3287 movw r2, #4999 @ 0x1387 800a134: 4293 cmp r3, r2 800a136: dd06 ble.n 800a146 800a138: 687b ldr r3, [r7, #4] 800a13a: f641 3258 movw r2, #7000 @ 0x1b58 800a13e: 4293 cmp r3, r2 800a140: dc01 bgt.n 800a146 return EV_STATE_C_CONN_ACTIVE; 800a142: 2302 movs r3, #2 800a144: e01a b.n 800a17c } else if (voltage_real >= (3000-1000) && voltage_real <= (3000 + 1000)) { 800a146: 687b ldr r3, [r7, #4] 800a148: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800a14c: db05 blt.n 800a15a 800a14e: 687b ldr r3, [r7, #4] 800a150: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800a154: dc01 bgt.n 800a15a return EV_STATE_D_CONN_ACT_VENT; 800a156: 2303 movs r3, #3 800a158: e010 b.n 800a17c } else if (voltage_real >= (0-1000) && voltage_real <= (0+2000)){ 800a15a: 687b ldr r3, [r7, #4] 800a15c: f513 7f7a cmn.w r3, #1000 @ 0x3e8 800a160: db05 blt.n 800a16e 800a162: 687b ldr r3, [r7, #4] 800a164: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800a168: dc01 bgt.n 800a16e return EV_STATE_E_NO_POWER; 800a16a: 2304 movs r3, #4 800a16c: e006 b.n 800a17c } else if (voltage_real <= (-12000+1000)) { 800a16e: 687b ldr r3, [r7, #4] 800a170: 4a05 ldr r2, [pc, #20] @ (800a188 ) 800a172: 4293 cmp r3, r2 800a174: da01 bge.n 800a17a return EV_STATE_F_ERROR; 800a176: 2305 movs r3, #5 800a178: e000 b.n 800a17c } else { return EV_STATE_ACQUIRING; 800a17a: 2306 movs r3, #6 } } 800a17c: 4618 mov r0, r3 800a17e: 3708 adds r7, #8 800a180: 46bd mov sp, r7 800a182: bd80 pop {r7, pc} 800a184: 20000004 .word 0x20000004 800a188: ffffd509 .word 0xffffd509 0800a18c : CP_State_t CP_GetFilteredState(void) { 800a18c: b480 push {r7} 800a18e: af00 add r7, sp, #0 return cp_state_buffer; 800a190: 4b02 ldr r3, [pc, #8] @ (800a19c ) 800a192: 781b ldrb r3, [r3, #0] } 800a194: 4618 mov r0, r3 800a196: 46bd mov sp, r7 800a198: bc80 pop {r7} 800a19a: 4770 bx lr 800a19c: 20000005 .word 0x20000005 0800a1a0 : void CP_FilterState(void) { 800a1a0: b580 push {r7, lr} 800a1a2: b082 sub sp, #8 800a1a4: af00 add r7, sp, #0 static CP_State_t pending_state = EV_STATE_ACQUIRING; static uint8_t stable_count = 0u; CP_State_t current_state = CP_GetState(); 800a1a6: f7ff ffa3 bl 800a0f0 800a1aa: 4603 mov r3, r0 800a1ac: 71fb strb r3, [r7, #7] /* Keep last accepted state while CP is still acquiring. */ if (current_state == EV_STATE_ACQUIRING) { 800a1ae: 79fb ldrb r3, [r7, #7] 800a1b0: 2b06 cmp r3, #6 800a1b2: d106 bne.n 800a1c2 pending_state = EV_STATE_ACQUIRING; 800a1b4: 4b13 ldr r3, [pc, #76] @ (800a204 ) 800a1b6: 2206 movs r2, #6 800a1b8: 701a strb r2, [r3, #0] stable_count = 0u; 800a1ba: 4b13 ldr r3, [pc, #76] @ (800a208 ) 800a1bc: 2200 movs r2, #0 800a1be: 701a strb r2, [r3, #0] return; 800a1c0: e01d b.n 800a1fe } if (current_state != pending_state) { 800a1c2: 4b10 ldr r3, [pc, #64] @ (800a204 ) 800a1c4: 781b ldrb r3, [r3, #0] 800a1c6: 79fa ldrb r2, [r7, #7] 800a1c8: 429a cmp r2, r3 800a1ca: d006 beq.n 800a1da pending_state = current_state; 800a1cc: 4a0d ldr r2, [pc, #52] @ (800a204 ) 800a1ce: 79fb ldrb r3, [r7, #7] 800a1d0: 7013 strb r3, [r2, #0] stable_count = 1u; 800a1d2: 4b0d ldr r3, [pc, #52] @ (800a208 ) 800a1d4: 2201 movs r2, #1 800a1d6: 701a strb r2, [r3, #0] return; 800a1d8: e011 b.n 800a1fe } if (stable_count < FILTER_ORDER) { 800a1da: 4b0b ldr r3, [pc, #44] @ (800a208 ) 800a1dc: 781b ldrb r3, [r3, #0] 800a1de: 2b63 cmp r3, #99 @ 0x63 800a1e0: d805 bhi.n 800a1ee stable_count++; 800a1e2: 4b09 ldr r3, [pc, #36] @ (800a208 ) 800a1e4: 781b ldrb r3, [r3, #0] 800a1e6: 3301 adds r3, #1 800a1e8: b2da uxtb r2, r3 800a1ea: 4b07 ldr r3, [pc, #28] @ (800a208 ) 800a1ec: 701a strb r2, [r3, #0] } if (stable_count >= FILTER_ORDER) { 800a1ee: 4b06 ldr r3, [pc, #24] @ (800a208 ) 800a1f0: 781b ldrb r3, [r3, #0] 800a1f2: 2b63 cmp r3, #99 @ 0x63 800a1f4: d903 bls.n 800a1fe cp_state_buffer = pending_state; 800a1f6: 4b03 ldr r3, [pc, #12] @ (800a204 ) 800a1f8: 781a ldrb r2, [r3, #0] 800a1fa: 4b04 ldr r3, [pc, #16] @ (800a20c ) 800a1fc: 701a strb r2, [r3, #0] } } 800a1fe: 3708 adds r7, #8 800a200: 46bd mov sp, r7 800a202: bd80 pop {r7, pc} 800a204: 20000006 .word 0x20000006 800a208: 200003d9 .word 0x200003d9 800a20c: 20000005 .word 0x20000005 0800a210 : void CP_Loop(void) { 800a210: b580 push {r7, lr} 800a212: b082 sub sp, #8 800a214: af00 add r7, sp, #0 static uint32_t tick; if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800a216: f004 f85d bl 800e2d4 800a21a: 4602 mov r2, r0 800a21c: 4b22 ldr r3, [pc, #136] @ (800a2a8 ) 800a21e: 681b ldr r3, [r3, #0] 800a220: 1ad3 subs r3, r2, r3 800a222: 2b00 cmp r3, #0 800a224: dd3c ble.n 800a2a0 tick = HAL_GetTick(); 800a226: f004 f855 bl 800e2d4 800a22a: 4603 mov r3, r0 800a22c: 4a1e ldr r2, [pc, #120] @ (800a2a8 ) 800a22e: 6013 str r3, [r2, #0] static uint8_t initialized = 0; static CP_State_t prev_state = EV_STATE_ACQUIRING; static uint8_t prev_duty = 0; CP_FilterState(); 800a230: f7ff ffb6 bl 800a1a0 CP_State_t current_state = CP_GetFilteredState(); 800a234: f7ff ffaa bl 800a18c 800a238: 4603 mov r3, r0 800a23a: 71fb strb r3, [r7, #7] uint8_t current_duty = cp_duty; 800a23c: 4b1b ldr r3, [pc, #108] @ (800a2ac ) 800a23e: 781b ldrb r3, [r3, #0] 800a240: 71bb strb r3, [r7, #6] if (!initialized) { 800a242: 4b1b ldr r3, [pc, #108] @ (800a2b0 ) 800a244: 781b ldrb r3, [r3, #0] 800a246: 2b00 cmp r3, #0 800a248: d109 bne.n 800a25e prev_state = current_state; 800a24a: 4a1a ldr r2, [pc, #104] @ (800a2b4 ) 800a24c: 79fb ldrb r3, [r7, #7] 800a24e: 7013 strb r3, [r2, #0] prev_duty = current_duty; 800a250: 4a19 ldr r2, [pc, #100] @ (800a2b8 ) 800a252: 79bb ldrb r3, [r7, #6] 800a254: 7013 strb r3, [r2, #0] initialized = 1; 800a256: 4b16 ldr r3, [pc, #88] @ (800a2b0 ) 800a258: 2201 movs r2, #1 800a25a: 701a strb r2, [r3, #0] return; 800a25c: e021 b.n 800a2a2 } if (current_state != prev_state) { 800a25e: 4b15 ldr r3, [pc, #84] @ (800a2b4 ) 800a260: 781b ldrb r3, [r3, #0] 800a262: 79fa ldrb r2, [r7, #7] 800a264: 429a cmp r2, r3 800a266: d00a beq.n 800a27e log_printf(LOG_INFO, "CP state changed: %d -> %d\n", prev_state, current_state); 800a268: 4b12 ldr r3, [pc, #72] @ (800a2b4 ) 800a26a: 781b ldrb r3, [r3, #0] 800a26c: 461a mov r2, r3 800a26e: 79fb ldrb r3, [r7, #7] 800a270: 4912 ldr r1, [pc, #72] @ (800a2bc ) 800a272: 2007 movs r0, #7 800a274: f000 f93e bl 800a4f4 prev_state = current_state; 800a278: 4a0e ldr r2, [pc, #56] @ (800a2b4 ) 800a27a: 79fb ldrb r3, [r7, #7] 800a27c: 7013 strb r3, [r2, #0] } if (current_duty != prev_duty) { 800a27e: 4b0e ldr r3, [pc, #56] @ (800a2b8 ) 800a280: 781b ldrb r3, [r3, #0] 800a282: 79ba ldrb r2, [r7, #6] 800a284: 429a cmp r2, r3 800a286: d00c beq.n 800a2a2 log_printf(LOG_INFO, "CP duty changed: %u -> %u\n", prev_duty, current_duty); 800a288: 4b0b ldr r3, [pc, #44] @ (800a2b8 ) 800a28a: 781b ldrb r3, [r3, #0] 800a28c: 461a mov r2, r3 800a28e: 79bb ldrb r3, [r7, #6] 800a290: 490b ldr r1, [pc, #44] @ (800a2c0 ) 800a292: 2007 movs r0, #7 800a294: f000 f92e bl 800a4f4 prev_duty = current_duty; 800a298: 4a07 ldr r2, [pc, #28] @ (800a2b8 ) 800a29a: 79bb ldrb r3, [r7, #6] 800a29c: 7013 strb r3, [r2, #0] 800a29e: e000 b.n 800a2a2 if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800a2a0: bf00 nop } } 800a2a2: 3708 adds r7, #8 800a2a4: 46bd mov sp, r7 800a2a6: bd80 pop {r7, pc} 800a2a8: 200003dc .word 0x200003dc 800a2ac: 200003d8 .word 0x200003d8 800a2b0: 200003e0 .word 0x200003e0 800a2b4: 20000007 .word 0x20000007 800a2b8: 200003e1 .word 0x200003e1 800a2bc: 08017018 .word 0x08017018 800a2c0: 08017034 .word 0x08017034 0800a2c4 : CRC_HandleTypeDef hcrc; /* CRC init function */ void MX_CRC_Init(void) { 800a2c4: b580 push {r7, lr} 800a2c6: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 800a2c8: 4b06 ldr r3, [pc, #24] @ (800a2e4 ) 800a2ca: 4a07 ldr r2, [pc, #28] @ (800a2e8 ) 800a2cc: 601a str r2, [r3, #0] if (HAL_CRC_Init(&hcrc) != HAL_OK) 800a2ce: 4805 ldr r0, [pc, #20] @ (800a2e4 ) 800a2d0: f005 fd51 bl 800fd76 800a2d4: 4603 mov r3, r0 800a2d6: 2b00 cmp r3, #0 800a2d8: d001 beq.n 800a2de { Error_Handler(); 800a2da: f000 fca1 bl 800ac20 } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 800a2de: bf00 nop 800a2e0: bd80 pop {r7, pc} 800a2e2: bf00 nop 800a2e4: 200003e4 .word 0x200003e4 800a2e8: 40023000 .word 0x40023000 0800a2ec : void HAL_CRC_MspInit(CRC_HandleTypeDef* crcHandle) { 800a2ec: b480 push {r7} 800a2ee: b085 sub sp, #20 800a2f0: af00 add r7, sp, #0 800a2f2: 6078 str r0, [r7, #4] if(crcHandle->Instance==CRC) 800a2f4: 687b ldr r3, [r7, #4] 800a2f6: 681b ldr r3, [r3, #0] 800a2f8: 4a09 ldr r2, [pc, #36] @ (800a320 ) 800a2fa: 4293 cmp r3, r2 800a2fc: d10b bne.n 800a316 { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* CRC clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 800a2fe: 4b09 ldr r3, [pc, #36] @ (800a324 ) 800a300: 695b ldr r3, [r3, #20] 800a302: 4a08 ldr r2, [pc, #32] @ (800a324 ) 800a304: f043 0340 orr.w r3, r3, #64 @ 0x40 800a308: 6153 str r3, [r2, #20] 800a30a: 4b06 ldr r3, [pc, #24] @ (800a324 ) 800a30c: 695b ldr r3, [r3, #20] 800a30e: f003 0340 and.w r3, r3, #64 @ 0x40 800a312: 60fb str r3, [r7, #12] 800a314: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 800a316: bf00 nop 800a318: 3714 adds r7, #20 800a31a: 46bd mov sp, r7 800a31c: bc80 pop {r7} 800a31e: 4770 bx lr 800a320: 40023000 .word 0x40023000 800a324: 40021000 .word 0x40021000 0800a328 <_write>: #if defined(__GNUC__) int _write(int fd, char * ptr, int len) { 800a328: b580 push {r7, lr} 800a32a: b084 sub sp, #16 800a32c: af00 add r7, sp, #0 800a32e: 60f8 str r0, [r7, #12] 800a330: 60b9 str r1, [r7, #8] 800a332: 607a str r2, [r7, #4] debug_buffer_add((const uint8_t*)ptr, len); 800a334: 687b ldr r3, [r7, #4] 800a336: b29b uxth r3, r3 800a338: 4619 mov r1, r3 800a33a: 68b8 ldr r0, [r7, #8] 800a33c: f000 f806 bl 800a34c return len; 800a340: 687b ldr r3, [r7, #4] } 800a342: 4618 mov r0, r3 800a344: 3710 adds r7, #16 800a346: 46bd mov sp, r7 800a348: bd80 pop {r7, pc} ... 0800a34c : #endif // Добавляет данные в кольцевой буфер void debug_buffer_add(const uint8_t* data, uint16_t len) { 800a34c: b480 push {r7} 800a34e: b085 sub sp, #20 800a350: af00 add r7, sp, #0 800a352: 6078 str r0, [r7, #4] 800a354: 460b mov r3, r1 800a356: 807b strh r3, [r7, #2] \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 800a358: b672 cpsid i } 800a35a: bf00 nop __disable_irq(); for (uint16_t i = 0; i < len; i++) { 800a35c: 2300 movs r3, #0 800a35e: 81fb strh r3, [r7, #14] 800a360: e045 b.n 800a3ee // Если буфер полон, перезаписываем старые данные if (debug_buffer.count >= DEBUG_BUFFER_SIZE) { 800a362: 4b28 ldr r3, [pc, #160] @ (800a404 ) 800a364: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a368: b29b uxth r3, r3 800a36a: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800a36e: d318 bcc.n 800a3a2 debug_buffer.read_index = (debug_buffer.read_index + 1) % DEBUG_BUFFER_SIZE; 800a370: 4b24 ldr r3, [pc, #144] @ (800a404 ) 800a372: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a376: b29b uxth r3, r3 800a378: 3301 adds r3, #1 800a37a: 425a negs r2, r3 800a37c: f3c3 0309 ubfx r3, r3, #0, #10 800a380: f3c2 0209 ubfx r2, r2, #0, #10 800a384: bf58 it pl 800a386: 4253 negpl r3, r2 800a388: b29a uxth r2, r3 800a38a: 4b1e ldr r3, [pc, #120] @ (800a404 ) 800a38c: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count--; 800a390: 4b1c ldr r3, [pc, #112] @ (800a404 ) 800a392: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a396: b29b uxth r3, r3 800a398: 3b01 subs r3, #1 800a39a: b29a uxth r2, r3 800a39c: 4b19 ldr r3, [pc, #100] @ (800a404 ) 800a39e: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 } debug_buffer.buffer[debug_buffer.write_index] = data[i]; 800a3a2: 89fb ldrh r3, [r7, #14] 800a3a4: 687a ldr r2, [r7, #4] 800a3a6: 4413 add r3, r2 800a3a8: 4a16 ldr r2, [pc, #88] @ (800a404 ) 800a3aa: f8b2 2400 ldrh.w r2, [r2, #1024] @ 0x400 800a3ae: b292 uxth r2, r2 800a3b0: 7819 ldrb r1, [r3, #0] 800a3b2: 4b14 ldr r3, [pc, #80] @ (800a404 ) 800a3b4: 5499 strb r1, [r3, r2] debug_buffer.write_index = (debug_buffer.write_index + 1) % DEBUG_BUFFER_SIZE; 800a3b6: 4b13 ldr r3, [pc, #76] @ (800a404 ) 800a3b8: f8b3 3400 ldrh.w r3, [r3, #1024] @ 0x400 800a3bc: b29b uxth r3, r3 800a3be: 3301 adds r3, #1 800a3c0: 425a negs r2, r3 800a3c2: f3c3 0309 ubfx r3, r3, #0, #10 800a3c6: f3c2 0209 ubfx r2, r2, #0, #10 800a3ca: bf58 it pl 800a3cc: 4253 negpl r3, r2 800a3ce: b29a uxth r2, r3 800a3d0: 4b0c ldr r3, [pc, #48] @ (800a404 ) 800a3d2: f8a3 2400 strh.w r2, [r3, #1024] @ 0x400 debug_buffer.count++; 800a3d6: 4b0b ldr r3, [pc, #44] @ (800a404 ) 800a3d8: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a3dc: b29b uxth r3, r3 800a3de: 3301 adds r3, #1 800a3e0: b29a uxth r2, r3 800a3e2: 4b08 ldr r3, [pc, #32] @ (800a404 ) 800a3e4: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 for (uint16_t i = 0; i < len; i++) { 800a3e8: 89fb ldrh r3, [r7, #14] 800a3ea: 3301 adds r3, #1 800a3ec: 81fb strh r3, [r7, #14] 800a3ee: 89fa ldrh r2, [r7, #14] 800a3f0: 887b ldrh r3, [r7, #2] 800a3f2: 429a cmp r2, r3 800a3f4: d3b5 bcc.n 800a362 __ASM volatile ("cpsie i" : : : "memory"); 800a3f6: b662 cpsie i } 800a3f8: bf00 nop } __enable_irq(); } 800a3fa: bf00 nop 800a3fc: 3714 adds r7, #20 800a3fe: 46bd mov sp, r7 800a400: bc80 pop {r7} 800a402: 4770 bx lr 800a404: 200003ec .word 0x200003ec 0800a408 : // Возвращает количество доступных данных в буфере uint16_t debug_buffer_available(void) { 800a408: b480 push {r7} 800a40a: b083 sub sp, #12 800a40c: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a40e: b672 cpsid i } 800a410: bf00 nop __disable_irq(); uint16_t count = debug_buffer.count; 800a412: 4b06 ldr r3, [pc, #24] @ (800a42c ) 800a414: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a418: 80fb strh r3, [r7, #6] __ASM volatile ("cpsie i" : : : "memory"); 800a41a: b662 cpsie i } 800a41c: bf00 nop __enable_irq(); return count; 800a41e: 88fb ldrh r3, [r7, #6] } 800a420: 4618 mov r0, r3 800a422: 370c adds r7, #12 800a424: 46bd mov sp, r7 800a426: bc80 pop {r7} 800a428: 4770 bx lr 800a42a: bf00 nop 800a42c: 200003ec .word 0x200003ec 0800a430 : // Отправляет один пакет данных из буфера через SC_SendPacket (не более 250 байт) void debug_buffer_send(void) { 800a430: b580 push {r7, lr} 800a432: b082 sub sp, #8 800a434: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a436: b672 cpsid i } 800a438: bf00 nop __disable_irq(); // Если буфер пуст, ничего не делаем if (debug_buffer.count == 0) { 800a43a: 4b2d ldr r3, [pc, #180] @ (800a4f0 ) 800a43c: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a440: b29b uxth r3, r3 800a442: 2b00 cmp r3, #0 800a444: d102 bne.n 800a44c __ASM volatile ("cpsie i" : : : "memory"); 800a446: b662 cpsie i } 800a448: bf00 nop __enable_irq(); return; 800a44a: e04e b.n 800a4ea } // Определяем сколько байт можно отправить (не более 250) uint16_t bytes_to_send = debug_buffer.count; 800a44c: 4b28 ldr r3, [pc, #160] @ (800a4f0 ) 800a44e: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a452: 80fb strh r3, [r7, #6] if (bytes_to_send > DEBUG_BUFFER_MAX_COUNT) { 800a454: 88fb ldrh r3, [r7, #6] 800a456: 2b80 cmp r3, #128 @ 0x80 800a458: d901 bls.n 800a45e bytes_to_send = DEBUG_BUFFER_MAX_COUNT; 800a45a: 2380 movs r3, #128 @ 0x80 800a45c: 80fb strh r3, [r7, #6] } // Вычисляем сколько байт до конца буфера uint16_t bytes_to_end = DEBUG_BUFFER_SIZE - debug_buffer.read_index; 800a45e: 4b24 ldr r3, [pc, #144] @ (800a4f0 ) 800a460: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a464: b29b uxth r3, r3 800a466: f5c3 6380 rsb r3, r3, #1024 @ 0x400 800a46a: 80bb strh r3, [r7, #4] // Отправляем только непрерывный блок (до конца буфера или до bytes_to_send) if (bytes_to_send > bytes_to_end) { 800a46c: 88fa ldrh r2, [r7, #6] 800a46e: 88bb ldrh r3, [r7, #4] 800a470: 429a cmp r2, r3 800a472: d901 bls.n 800a478 bytes_to_send = bytes_to_end; 800a474: 88bb ldrh r3, [r7, #4] 800a476: 80fb strh r3, [r7, #6] } // Отправляем данные напрямую из буфера if(bytes_to_send == debug_buffer.count){ 800a478: 4b1d ldr r3, [pc, #116] @ (800a4f0 ) 800a47a: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a47e: b29b uxth r3, r3 800a480: 88fa ldrh r2, [r7, #6] 800a482: 429a cmp r2, r3 800a484: d10c bne.n 800a4a0 SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG); 800a486: 4b1a ldr r3, [pc, #104] @ (800a4f0 ) 800a488: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a48c: b29b uxth r3, r3 800a48e: 461a mov r2, r3 800a490: 4b17 ldr r3, [pc, #92] @ (800a4f0 ) 800a492: 4413 add r3, r2 800a494: 88f9 ldrh r1, [r7, #6] 800a496: 2250 movs r2, #80 @ 0x50 800a498: 4618 mov r0, r3 800a49a: f002 fc37 bl 800cd0c 800a49e: e00b b.n 800a4b8 }else{ SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG_CONTINUE); 800a4a0: 4b13 ldr r3, [pc, #76] @ (800a4f0 ) 800a4a2: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a4a6: b29b uxth r3, r3 800a4a8: 461a mov r2, r3 800a4aa: 4b11 ldr r3, [pc, #68] @ (800a4f0 ) 800a4ac: 4413 add r3, r2 800a4ae: 88f9 ldrh r1, [r7, #6] 800a4b0: 2251 movs r2, #81 @ 0x51 800a4b2: 4618 mov r0, r3 800a4b4: f002 fc2a bl 800cd0c } debug_buffer.read_index = (debug_buffer.read_index + bytes_to_send) % DEBUG_BUFFER_SIZE; 800a4b8: 4b0d ldr r3, [pc, #52] @ (800a4f0 ) 800a4ba: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a4be: b29a uxth r2, r3 800a4c0: 88fb ldrh r3, [r7, #6] 800a4c2: 4413 add r3, r2 800a4c4: b29b uxth r3, r3 800a4c6: f3c3 0309 ubfx r3, r3, #0, #10 800a4ca: b29a uxth r2, r3 800a4cc: 4b08 ldr r3, [pc, #32] @ (800a4f0 ) 800a4ce: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count -= bytes_to_send; 800a4d2: 4b07 ldr r3, [pc, #28] @ (800a4f0 ) 800a4d4: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a4d8: b29a uxth r2, r3 800a4da: 88fb ldrh r3, [r7, #6] 800a4dc: 1ad3 subs r3, r2, r3 800a4de: b29a uxth r2, r3 800a4e0: 4b03 ldr r3, [pc, #12] @ (800a4f0 ) 800a4e2: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 __ASM volatile ("cpsie i" : : : "memory"); 800a4e6: b662 cpsie i } 800a4e8: bf00 nop __enable_irq(); } 800a4ea: 3708 adds r7, #8 800a4ec: 46bd mov sp, r7 800a4ee: bd80 pop {r7, pc} 800a4f0: 200003ec .word 0x200003ec 0800a4f4 : #define LOG_BUFFER_SIZE 128 uint8_t log_buffer[LOG_BUFFER_SIZE]; // Кастомный printf с приоритетом лога int log_printf(LogLevel_t level, const char *format, ...) { 800a4f4: b40e push {r1, r2, r3} 800a4f6: b580 push {r7, lr} 800a4f8: b085 sub sp, #20 800a4fa: af00 add r7, sp, #0 800a4fc: 4603 mov r3, r0 800a4fe: 71fb strb r3, [r7, #7] va_list args; int result; // Добавляем приоритет первым байтом log_buffer[0] = (uint8_t)level; 800a500: 4a15 ldr r2, [pc, #84] @ (800a558 ) 800a502: 79fb ldrb r3, [r7, #7] 800a504: 7013 strb r3, [r2, #0] // Форматируем строку начиная со второго байта va_start(args, format); 800a506: f107 0320 add.w r3, r7, #32 800a50a: 60bb str r3, [r7, #8] result = vsnprintf((char*)&log_buffer[1], LOG_BUFFER_SIZE - 2, format, args); 800a50c: 68bb ldr r3, [r7, #8] 800a50e: 69fa ldr r2, [r7, #28] 800a510: 217e movs r1, #126 @ 0x7e 800a512: 4812 ldr r0, [pc, #72] @ (800a55c ) 800a514: f00a fb6c bl 8014bf0 800a518: 60f8 str r0, [r7, #12] va_end(args); // Проверяем, не переполнился ли буфер if (result < 0) { 800a51a: 68fb ldr r3, [r7, #12] 800a51c: 2b00 cmp r3, #0 800a51e: da01 bge.n 800a524 return result; 800a520: 68fb ldr r3, [r7, #12] 800a522: e012 b.n 800a54a } // Ограничиваем размер, чтобы оставить место для нуль-терминатора if (result >= (LOG_BUFFER_SIZE - 2)) { 800a524: 68fb ldr r3, [r7, #12] 800a526: 2b7d cmp r3, #125 @ 0x7d 800a528: dd01 ble.n 800a52e result = LOG_BUFFER_SIZE - 2; 800a52a: 237e movs r3, #126 @ 0x7e 800a52c: 60fb str r3, [r7, #12] } // Добавляем нуль-терминатор в конец log_buffer[result + 1] = '\0'; 800a52e: 68fb ldr r3, [r7, #12] 800a530: 3301 adds r3, #1 800a532: 4a09 ldr r2, [pc, #36] @ (800a558 ) 800a534: 2100 movs r1, #0 800a536: 54d1 strb r1, [r2, r3] // Отправляем в буфер (приоритет + строка + нуль-терминатор) debug_buffer_add(log_buffer, result + 2); 800a538: 68fb ldr r3, [r7, #12] 800a53a: b29b uxth r3, r3 800a53c: 3302 adds r3, #2 800a53e: b29b uxth r3, r3 800a540: 4619 mov r1, r3 800a542: 4805 ldr r0, [pc, #20] @ (800a558 ) 800a544: f7ff ff02 bl 800a34c return result; 800a548: 68fb ldr r3, [r7, #12] } 800a54a: 4618 mov r0, r3 800a54c: 3714 adds r7, #20 800a54e: 46bd mov sp, r7 800a550: e8bd 4080 ldmia.w sp!, {r7, lr} 800a554: b003 add sp, #12 800a556: 4770 bx lr 800a558: 200007f4 .word 0x200007f4 800a55c: 200007f5 .word 0x200007f5 0800a560 : /** * Enable DMA controller clock */ void MX_DMA_Init(void) { 800a560: b580 push {r7, lr} 800a562: b082 sub sp, #8 800a564: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 800a566: 4b1c ldr r3, [pc, #112] @ (800a5d8 ) 800a568: 695b ldr r3, [r3, #20] 800a56a: 4a1b ldr r2, [pc, #108] @ (800a5d8 ) 800a56c: f043 0301 orr.w r3, r3, #1 800a570: 6153 str r3, [r2, #20] 800a572: 4b19 ldr r3, [pc, #100] @ (800a5d8 ) 800a574: 695b ldr r3, [r3, #20] 800a576: f003 0301 and.w r3, r3, #1 800a57a: 607b str r3, [r7, #4] 800a57c: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 1, 0); 800a57e: 2200 movs r2, #0 800a580: 2101 movs r1, #1 800a582: 200b movs r0, #11 800a584: f005 fbc1 bl 800fd0a HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 800a588: 200b movs r0, #11 800a58a: f005 fbda bl 800fd42 /* DMA1_Channel2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 4, 0); 800a58e: 2200 movs r2, #0 800a590: 2104 movs r1, #4 800a592: 200c movs r0, #12 800a594: f005 fbb9 bl 800fd0a HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); 800a598: 200c movs r0, #12 800a59a: f005 fbd2 bl 800fd42 /* DMA1_Channel3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 1, 0); 800a59e: 2200 movs r2, #0 800a5a0: 2101 movs r1, #1 800a5a2: 200d movs r0, #13 800a5a4: f005 fbb1 bl 800fd0a HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn); 800a5a8: 200d movs r0, #13 800a5aa: f005 fbca bl 800fd42 /* DMA1_Channel6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel6_IRQn, 1, 0); 800a5ae: 2200 movs r2, #0 800a5b0: 2101 movs r1, #1 800a5b2: 2010 movs r0, #16 800a5b4: f005 fba9 bl 800fd0a HAL_NVIC_EnableIRQ(DMA1_Channel6_IRQn); 800a5b8: 2010 movs r0, #16 800a5ba: f005 fbc2 bl 800fd42 /* DMA1_Channel7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 4, 0); 800a5be: 2200 movs r2, #0 800a5c0: 2104 movs r1, #4 800a5c2: 2011 movs r0, #17 800a5c4: f005 fba1 bl 800fd0a HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn); 800a5c8: 2011 movs r0, #17 800a5ca: f005 fbba bl 800fd42 } 800a5ce: bf00 nop 800a5d0: 3708 adds r7, #8 800a5d2: 46bd mov sp, r7 800a5d4: bd80 pop {r7, pc} 800a5d6: bf00 nop 800a5d8: 40021000 .word 0x40021000 0800a5dc : * EXTI PB8 ------> I2C1_SCL PB9 ------> I2C1_SDA */ void MX_GPIO_Init(void) { 800a5dc: b580 push {r7, lr} 800a5de: b08a sub sp, #40 @ 0x28 800a5e0: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800a5e2: f107 0314 add.w r3, r7, #20 800a5e6: 2200 movs r2, #0 800a5e8: 601a str r2, [r3, #0] 800a5ea: 605a str r2, [r3, #4] 800a5ec: 609a str r2, [r3, #8] 800a5ee: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 800a5f0: 4b93 ldr r3, [pc, #588] @ (800a840 ) 800a5f2: 699b ldr r3, [r3, #24] 800a5f4: 4a92 ldr r2, [pc, #584] @ (800a840 ) 800a5f6: f043 0310 orr.w r3, r3, #16 800a5fa: 6193 str r3, [r2, #24] 800a5fc: 4b90 ldr r3, [pc, #576] @ (800a840 ) 800a5fe: 699b ldr r3, [r3, #24] 800a600: f003 0310 and.w r3, r3, #16 800a604: 613b str r3, [r7, #16] 800a606: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800a608: 4b8d ldr r3, [pc, #564] @ (800a840 ) 800a60a: 699b ldr r3, [r3, #24] 800a60c: 4a8c ldr r2, [pc, #560] @ (800a840 ) 800a60e: f043 0304 orr.w r3, r3, #4 800a612: 6193 str r3, [r2, #24] 800a614: 4b8a ldr r3, [pc, #552] @ (800a840 ) 800a616: 699b ldr r3, [r3, #24] 800a618: f003 0304 and.w r3, r3, #4 800a61c: 60fb str r3, [r7, #12] 800a61e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 800a620: 4b87 ldr r3, [pc, #540] @ (800a840 ) 800a622: 699b ldr r3, [r3, #24] 800a624: 4a86 ldr r2, [pc, #536] @ (800a840 ) 800a626: f043 0308 orr.w r3, r3, #8 800a62a: 6193 str r3, [r2, #24] 800a62c: 4b84 ldr r3, [pc, #528] @ (800a840 ) 800a62e: 699b ldr r3, [r3, #24] 800a630: f003 0308 and.w r3, r3, #8 800a634: 60bb str r3, [r7, #8] 800a636: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOE_CLK_ENABLE(); 800a638: 4b81 ldr r3, [pc, #516] @ (800a840 ) 800a63a: 699b ldr r3, [r3, #24] 800a63c: 4a80 ldr r2, [pc, #512] @ (800a840 ) 800a63e: f043 0340 orr.w r3, r3, #64 @ 0x40 800a642: 6193 str r3, [r2, #24] 800a644: 4b7e ldr r3, [pc, #504] @ (800a840 ) 800a646: 699b ldr r3, [r3, #24] 800a648: f003 0340 and.w r3, r3, #64 @ 0x40 800a64c: 607b str r3, [r7, #4] 800a64e: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 800a650: 4b7b ldr r3, [pc, #492] @ (800a840 ) 800a652: 699b ldr r3, [r3, #24] 800a654: 4a7a ldr r2, [pc, #488] @ (800a840 ) 800a656: f043 0320 orr.w r3, r3, #32 800a65a: 6193 str r3, [r2, #24] 800a65c: 4b78 ldr r3, [pc, #480] @ (800a840 ) 800a65e: 699b ldr r3, [r3, #24] 800a660: f003 0320 and.w r3, r3, #32 800a664: 603b str r3, [r7, #0] 800a666: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, DBG1_Pin|RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin, GPIO_PIN_RESET); 800a668: 2200 movs r2, #0 800a66a: 213c movs r1, #60 @ 0x3c 800a66c: 4875 ldr r0, [pc, #468] @ (800a844 ) 800a66e: f006 f9c8 bl 8010a02 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, DBG2_Pin|DBG3_Pin|RELAY_CC_Pin, GPIO_PIN_RESET); 800a672: 2200 movs r2, #0 800a674: f248 0160 movw r1, #32864 @ 0x8060 800a678: 4873 ldr r0, [pc, #460] @ (800a848 ) 800a67a: f006 f9c2 bl 8010a02 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a67e: 2200 movs r2, #0 800a680: f44f 51f8 mov.w r1, #7936 @ 0x1f00 800a684: 4871 ldr r0, [pc, #452] @ (800a84c ) 800a686: f006 f9bc bl 8010a02 |RELAY5_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, DBG5_Pin|DBG4_Pin|EE_WP_Pin, GPIO_PIN_RESET); 800a68a: 2200 movs r2, #0 800a68c: f44f 6148 mov.w r1, #3200 @ 0xc80 800a690: 486f ldr r0, [pc, #444] @ (800a850 ) 800a692: f006 f9b6 bl 8010a02 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, RELAY_DC_Pin|USART2_DIR_Pin, GPIO_PIN_RESET); 800a696: 2200 movs r2, #0 800a698: 2118 movs r1, #24 800a69a: 486e ldr r0, [pc, #440] @ (800a854 ) 800a69c: f006 f9b1 bl 8010a02 /*Configure GPIO pin : DBG1_Pin */ GPIO_InitStruct.Pin = DBG1_Pin; 800a6a0: 2304 movs r3, #4 800a6a2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a6a4: 2301 movs r3, #1 800a6a6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a6a8: 2300 movs r3, #0 800a6aa: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a6ac: 2303 movs r3, #3 800a6ae: 623b str r3, [r7, #32] HAL_GPIO_Init(DBG1_GPIO_Port, &GPIO_InitStruct); 800a6b0: f107 0314 add.w r3, r7, #20 800a6b4: 4619 mov r1, r3 800a6b6: 4863 ldr r0, [pc, #396] @ (800a844 ) 800a6b8: f006 f808 bl 80106cc /*Configure GPIO pins : RELAY_CP_Pin LOCK_A_Pin LOCK_B_Pin */ GPIO_InitStruct.Pin = RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin; 800a6bc: 2338 movs r3, #56 @ 0x38 800a6be: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a6c0: 2301 movs r3, #1 800a6c2: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a6c4: 2300 movs r3, #0 800a6c6: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a6c8: 2302 movs r3, #2 800a6ca: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800a6cc: f107 0314 add.w r3, r7, #20 800a6d0: 4619 mov r1, r3 800a6d2: 485c ldr r0, [pc, #368] @ (800a844 ) 800a6d4: f005 fffa bl 80106cc /*Configure GPIO pin : IN_SW0_Pin */ GPIO_InitStruct.Pin = IN_SW0_Pin; 800a6d8: 2302 movs r3, #2 800a6da: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a6dc: 2300 movs r3, #0 800a6de: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a6e0: 2300 movs r3, #0 800a6e2: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW0_GPIO_Port, &GPIO_InitStruct); 800a6e4: f107 0314 add.w r3, r7, #20 800a6e8: 4619 mov r1, r3 800a6ea: 4857 ldr r0, [pc, #348] @ (800a848 ) 800a6ec: f005 ffee bl 80106cc /*Configure GPIO pin : IN_SW1_Pin */ GPIO_InitStruct.Pin = IN_SW1_Pin; 800a6f0: 2304 movs r3, #4 800a6f2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a6f4: 2300 movs r3, #0 800a6f6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 800a6f8: 2302 movs r3, #2 800a6fa: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW1_GPIO_Port, &GPIO_InitStruct); 800a6fc: f107 0314 add.w r3, r7, #20 800a700: 4619 mov r1, r3 800a702: 4851 ldr r0, [pc, #324] @ (800a848 ) 800a704: f005 ffe2 bl 80106cc /*Configure GPIO pins : DBG2_Pin DBG3_Pin */ GPIO_InitStruct.Pin = DBG2_Pin|DBG3_Pin; 800a708: 2360 movs r3, #96 @ 0x60 800a70a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a70c: 2301 movs r3, #1 800a70e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a710: 2300 movs r3, #0 800a712: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a714: 2303 movs r3, #3 800a716: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800a718: f107 0314 add.w r3, r7, #20 800a71c: 4619 mov r1, r3 800a71e: 484a ldr r0, [pc, #296] @ (800a848 ) 800a720: f005 ffd4 bl 80106cc /*Configure GPIO pins : IN0_Pin AC_OK_Pin ISO_IN_Pin */ GPIO_InitStruct.Pin = IN0_Pin|AC_OK_Pin|ISO_IN_Pin; 800a724: f244 0382 movw r3, #16514 @ 0x4082 800a728: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a72a: 2300 movs r3, #0 800a72c: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a72e: 2300 movs r3, #0 800a730: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a732: f107 0314 add.w r3, r7, #20 800a736: 4619 mov r1, r3 800a738: 4844 ldr r0, [pc, #272] @ (800a84c ) 800a73a: f005 ffc7 bl 80106cc /*Configure GPIO pins : RELAY1_Pin RELAY2_Pin RELAY3_Pin RELAY4_Pin RELAY5_Pin */ GPIO_InitStruct.Pin = RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a73e: f44f 53f8 mov.w r3, #7936 @ 0x1f00 800a742: 617b str r3, [r7, #20] |RELAY5_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a744: 2301 movs r3, #1 800a746: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a748: 2300 movs r3, #0 800a74a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a74c: 2302 movs r3, #2 800a74e: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a750: f107 0314 add.w r3, r7, #20 800a754: 4619 mov r1, r3 800a756: 483d ldr r0, [pc, #244] @ (800a84c ) 800a758: f005 ffb8 bl 80106cc /*Configure GPIO pins : DBG5_Pin DBG4_Pin */ GPIO_InitStruct.Pin = DBG5_Pin|DBG4_Pin; 800a75c: f44f 6340 mov.w r3, #3072 @ 0xc00 800a760: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a762: 2301 movs r3, #1 800a764: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a766: 2300 movs r3, #0 800a768: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a76a: 2303 movs r3, #3 800a76c: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a76e: f107 0314 add.w r3, r7, #20 800a772: 4619 mov r1, r3 800a774: 4836 ldr r0, [pc, #216] @ (800a850 ) 800a776: f005 ffa9 bl 80106cc /*Configure GPIO pin : RELAY_CC_Pin */ GPIO_InitStruct.Pin = RELAY_CC_Pin; 800a77a: f44f 4300 mov.w r3, #32768 @ 0x8000 800a77e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a780: 2301 movs r3, #1 800a782: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a784: 2300 movs r3, #0 800a786: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a788: 2302 movs r3, #2 800a78a: 623b str r3, [r7, #32] HAL_GPIO_Init(RELAY_CC_GPIO_Port, &GPIO_InitStruct); 800a78c: f107 0314 add.w r3, r7, #20 800a790: 4619 mov r1, r3 800a792: 482d ldr r0, [pc, #180] @ (800a848 ) 800a794: f005 ff9a bl 80106cc /*Configure GPIO pins : RELAY_DC_Pin USART2_DIR_Pin */ GPIO_InitStruct.Pin = RELAY_DC_Pin|USART2_DIR_Pin; 800a798: 2318 movs r3, #24 800a79a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a79c: 2301 movs r3, #1 800a79e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a7a0: 2300 movs r3, #0 800a7a2: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a7a4: 2302 movs r3, #2 800a7a6: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800a7a8: f107 0314 add.w r3, r7, #20 800a7ac: 4619 mov r1, r3 800a7ae: 4829 ldr r0, [pc, #164] @ (800a854 ) 800a7b0: f005 ff8c bl 80106cc /*Configure GPIO pin : IN_ESTOP_Pin */ GPIO_InitStruct.Pin = IN_ESTOP_Pin; 800a7b4: 2380 movs r3, #128 @ 0x80 800a7b6: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a7b8: 2300 movs r3, #0 800a7ba: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a7bc: 2300 movs r3, #0 800a7be: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_ESTOP_GPIO_Port, &GPIO_InitStruct); 800a7c0: f107 0314 add.w r3, r7, #20 800a7c4: 4619 mov r1, r3 800a7c6: 4823 ldr r0, [pc, #140] @ (800a854 ) 800a7c8: f005 ff80 bl 80106cc /*Configure GPIO pins : IN_FB2_Pin IN_FB1_Pin */ GPIO_InitStruct.Pin = IN_FB2_Pin|IN_FB1_Pin; 800a7cc: 2318 movs r3, #24 800a7ce: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a7d0: 2300 movs r3, #0 800a7d2: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a7d4: 2300 movs r3, #0 800a7d6: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a7d8: f107 0314 add.w r3, r7, #20 800a7dc: 4619 mov r1, r3 800a7de: 481c ldr r0, [pc, #112] @ (800a850 ) 800a7e0: f005 ff74 bl 80106cc /*Configure GPIO pin : EE_WP_Pin */ GPIO_InitStruct.Pin = EE_WP_Pin; 800a7e4: 2380 movs r3, #128 @ 0x80 800a7e6: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a7e8: 2301 movs r3, #1 800a7ea: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a7ec: 2300 movs r3, #0 800a7ee: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a7f0: 2302 movs r3, #2 800a7f2: 623b str r3, [r7, #32] HAL_GPIO_Init(EE_WP_GPIO_Port, &GPIO_InitStruct); 800a7f4: f107 0314 add.w r3, r7, #20 800a7f8: 4619 mov r1, r3 800a7fa: 4815 ldr r0, [pc, #84] @ (800a850 ) 800a7fc: f005 ff66 bl 80106cc /*Configure GPIO pins : PB8 PB9 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 800a800: f44f 7340 mov.w r3, #768 @ 0x300 800a804: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 800a806: 2312 movs r3, #18 800a808: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a80a: 2303 movs r3, #3 800a80c: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a80e: f107 0314 add.w r3, r7, #20 800a812: 4619 mov r1, r3 800a814: 480e ldr r0, [pc, #56] @ (800a850 ) 800a816: f005 ff59 bl 80106cc /*Configure peripheral I/O remapping */ __HAL_AFIO_REMAP_I2C1_ENABLE(); 800a81a: 4b0f ldr r3, [pc, #60] @ (800a858 ) 800a81c: 685b ldr r3, [r3, #4] 800a81e: 627b str r3, [r7, #36] @ 0x24 800a820: 6a7b ldr r3, [r7, #36] @ 0x24 800a822: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800a826: 627b str r3, [r7, #36] @ 0x24 800a828: 6a7b ldr r3, [r7, #36] @ 0x24 800a82a: f043 0302 orr.w r3, r3, #2 800a82e: 627b str r3, [r7, #36] @ 0x24 800a830: 4a09 ldr r2, [pc, #36] @ (800a858 ) 800a832: 6a7b ldr r3, [r7, #36] @ 0x24 800a834: 6053 str r3, [r2, #4] } 800a836: bf00 nop 800a838: 3728 adds r7, #40 @ 0x28 800a83a: 46bd mov sp, r7 800a83c: bd80 pop {r7, pc} 800a83e: bf00 nop 800a840: 40021000 .word 0x40021000 800a844: 40011000 .word 0x40011000 800a848: 40010800 .word 0x40010800 800a84c: 40011800 .word 0x40011800 800a850: 40010c00 .word 0x40010c00 800a854: 40011400 .word 0x40011400 800a858: 40010000 .word 0x40010000 0800a85c <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 800a85c: b480 push {r7} 800a85e: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 800a860: f3bf 8f4f dsb sy } 800a864: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800a866: 4b06 ldr r3, [pc, #24] @ (800a880 <__NVIC_SystemReset+0x24>) 800a868: 68db ldr r3, [r3, #12] 800a86a: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800a86e: 4904 ldr r1, [pc, #16] @ (800a880 <__NVIC_SystemReset+0x24>) 800a870: 4b04 ldr r3, [pc, #16] @ (800a884 <__NVIC_SystemReset+0x28>) 800a872: 4313 orrs r3, r2 800a874: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800a876: f3bf 8f4f dsb sy } 800a87a: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 800a87c: bf00 nop 800a87e: e7fd b.n 800a87c <__NVIC_SystemReset+0x20> 800a880: e000ed00 .word 0xe000ed00 800a884: 05fa0004 .word 0x05fa0004 0800a888 : * bootloader before starting this program. Unfortunately, function * SystemInit() overwrites this change again. * @return none. */ static void VectorBase_Config(void) { 800a888: b480 push {r7} 800a88a: af00 add r7, sp, #0 * c-startup code. */ extern const unsigned long g_pfnVectors[]; /* Remap the vector table to where the vector table is located for this program. */ SCB->VTOR = (unsigned long)&g_pfnVectors[0]; 800a88c: 4b03 ldr r3, [pc, #12] @ (800a89c ) 800a88e: 4a04 ldr r2, [pc, #16] @ (800a8a0 ) 800a890: 609a str r2, [r3, #8] } 800a892: bf00 nop 800a894: 46bd mov sp, r7 800a896: bc80 pop {r7} 800a898: 4770 bx lr 800a89a: bf00 nop 800a89c: e000ed00 .word 0xe000ed00 800a8a0: 08008000 .word 0x08008000 0800a8a4 : uint8_t ED_TraceWarning(uint8_t flag, uint8_t id){ 800a8a4: b480 push {r7} 800a8a6: b085 sub sp, #20 800a8a8: af00 add r7, sp, #0 800a8aa: 4603 mov r3, r0 800a8ac: 460a mov r2, r1 800a8ae: 71fb strb r3, [r7, #7] 800a8b0: 4613 mov r3, r2 800a8b2: 71bb strb r3, [r7, #6] static uint8_t memory[32]; if(id > 31) return 0; 800a8b4: 79bb ldrb r3, [r7, #6] 800a8b6: 2b1f cmp r3, #31 800a8b8: d901 bls.n 800a8be 800a8ba: 2300 movs r3, #0 800a8bc: e00e b.n 800a8dc uint8_t result = 0; 800a8be: 2300 movs r3, #0 800a8c0: 73fb strb r3, [r7, #15] if(memory[id] != flag){ 800a8c2: 79bb ldrb r3, [r7, #6] 800a8c4: 4a08 ldr r2, [pc, #32] @ (800a8e8 ) 800a8c6: 5cd3 ldrb r3, [r2, r3] 800a8c8: 79fa ldrb r2, [r7, #7] 800a8ca: 429a cmp r2, r3 800a8cc: d001 beq.n 800a8d2 result = 1; 800a8ce: 2301 movs r3, #1 800a8d0: 73fb strb r3, [r7, #15] } memory[id] = flag; 800a8d2: 79bb ldrb r3, [r7, #6] 800a8d4: 4904 ldr r1, [pc, #16] @ (800a8e8 ) 800a8d6: 79fa ldrb r2, [r7, #7] 800a8d8: 54ca strb r2, [r1, r3] return result; 800a8da: 7bfb ldrb r3, [r7, #15] } 800a8dc: 4618 mov r0, r3 800a8de: 3714 adds r7, #20 800a8e0: 46bd mov sp, r7 800a8e2: bc80 pop {r7} 800a8e4: 4770 bx lr 800a8e6: bf00 nop 800a8e8: 20000874 .word 0x20000874 0800a8ec : void ED_Delay(uint32_t Delay) { 800a8ec: b580 push {r7, lr} 800a8ee: b084 sub sp, #16 800a8f0: af00 add r7, sp, #0 800a8f2: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800a8f4: f003 fcee bl 800e2d4 800a8f8: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800a8fa: 687b ldr r3, [r7, #4] 800a8fc: 60fb str r3, [r7, #12] if (wait < HAL_MAX_DELAY) 800a8fe: 68fb ldr r3, [r7, #12] 800a900: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800a904: d010 beq.n 800a928 { wait += (uint32_t)(uwTickFreq); 800a906: 4b0f ldr r3, [pc, #60] @ (800a944 ) 800a908: 781b ldrb r3, [r3, #0] 800a90a: 461a mov r2, r3 800a90c: 68fb ldr r3, [r7, #12] 800a90e: 4413 add r3, r2 800a910: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait){ 800a912: e009 b.n 800a928 CCS_SerialLoop(); 800a914: f001 fa48 bl 800bda8 StopButtonControl(); 800a918: f000 f816 bl 800a948 CP_Loop(); 800a91c: f7ff fc78 bl 800a210 LED_Task(); 800a920: f001 f80a bl 800b938 SC_Task(); 800a924: f002 f898 bl 800ca58 while ((HAL_GetTick() - tickstart) < wait){ 800a928: f003 fcd4 bl 800e2d4 800a92c: 4602 mov r2, r0 800a92e: 68bb ldr r3, [r7, #8] 800a930: 1ad3 subs r3, r2, r3 800a932: 68fa ldr r2, [r7, #12] 800a934: 429a cmp r2, r3 800a936: d8ed bhi.n 800a914 } } 800a938: bf00 nop 800a93a: bf00 nop 800a93c: 3710 adds r7, #16 800a93e: 46bd mov sp, r7 800a940: bd80 pop {r7, pc} 800a942: bf00 nop 800a944: 2000008c .word 0x2000008c 0800a948 : static void StopButtonControl(void){ 800a948: b580 push {r7, lr} 800a94a: b082 sub sp, #8 800a94c: af00 add r7, sp, #0 static uint32_t tick; static uint32_t hold_time; static uint8_t stop_btn_fault = 1; uint32_t now = HAL_GetTick(); 800a94e: f003 fcc1 bl 800e2d4 800a952: 6078 str r0, [r7, #4] /* Run no faster than once per 10 ms. */ if((now - tick) < 10){ 800a954: 4b2a ldr r3, [pc, #168] @ (800aa00 ) 800a956: 681b ldr r3, [r3, #0] 800a958: 687a ldr r2, [r7, #4] 800a95a: 1ad3 subs r3, r2, r3 800a95c: 2b09 cmp r3, #9 800a95e: d949 bls.n 800a9f4 return; } tick = now; 800a960: 4a27 ldr r2, [pc, #156] @ (800aa00 ) 800a962: 687b ldr r3, [r7, #4] 800a964: 6013 str r3, [r2, #0] uint8_t pressed = !IN_ReadInput(IN_ESTOP); 800a966: 2003 movs r0, #3 800a968: f7fe ffa6 bl 80098b8 800a96c: 4603 mov r3, r0 800a96e: 2b00 cmp r3, #0 800a970: bf0c ite eq 800a972: 2301 moveq r3, #1 800a974: 2300 movne r3, #0 800a976: b2db uxtb r3, r3 800a978: 70fb strb r3, [r7, #3] if(!pressed){ 800a97a: 78fb ldrb r3, [r7, #3] 800a97c: 2b00 cmp r3, #0 800a97e: d102 bne.n 800a986 stop_btn_fault = 0; 800a980: 4b20 ldr r3, [pc, #128] @ (800aa04 ) 800a982: 2200 movs r2, #0 800a984: 701a strb r2, [r3, #0] } if(stop_btn_fault){ 800a986: 4b1f ldr r3, [pc, #124] @ (800aa04 ) 800a988: 781b ldrb r3, [r3, #0] 800a98a: 2b00 cmp r3, #0 800a98c: d134 bne.n 800a9f8 return; } if(pressed){ 800a98e: 78fb ldrb r3, [r7, #3] 800a990: 2b00 cmp r3, #0 800a992: d02b beq.n 800a9ec if(hold_time == 0){ 800a994: 4b1c ldr r3, [pc, #112] @ (800aa08 ) 800a996: 681b ldr r3, [r3, #0] 800a998: 2b00 cmp r3, #0 800a99a: d102 bne.n 800a9a2 CONN.connControl = CMD_STOP; 800a99c: 4b1b ldr r3, [pc, #108] @ (800aa0c ) 800a99e: 2201 movs r2, #1 800a9a0: 701a strb r2, [r3, #0] } hold_time += 10; 800a9a2: 4b19 ldr r3, [pc, #100] @ (800aa08 ) 800a9a4: 681b ldr r3, [r3, #0] 800a9a6: 330a adds r3, #10 800a9a8: 4a17 ldr r2, [pc, #92] @ (800aa08 ) 800a9aa: 6013 str r3, [r2, #0] if(hold_time == 5000){ 800a9ac: 4b16 ldr r3, [pc, #88] @ (800aa08 ) 800a9ae: 681b ldr r3, [r3, #0] 800a9b0: f241 3288 movw r2, #5000 @ 0x1388 800a9b4: 4293 cmp r3, r2 800a9b6: d102 bne.n 800a9be CONN.connControl = CMD_FORCE_UNLOCK; 800a9b8: 4b14 ldr r3, [pc, #80] @ (800aa0c ) 800a9ba: 2203 movs r2, #3 800a9bc: 701a strb r2, [r3, #0] } if(hold_time > 40000){ 800a9be: 4b12 ldr r3, [pc, #72] @ (800aa08 ) 800a9c0: 681b ldr r3, [r3, #0] 800a9c2: f649 4240 movw r2, #40000 @ 0x9c40 800a9c6: 4293 cmp r3, r2 800a9c8: d917 bls.n 800a9fa SC_SendPacket(NULL, 0, RESP_SUCCESS); 800a9ca: 2212 movs r2, #18 800a9cc: 2100 movs r1, #0 800a9ce: 2000 movs r0, #0 800a9d0: f002 f99c bl 800cd0c while(huart2.gState == HAL_UART_STATE_BUSY_TX); 800a9d4: bf00 nop 800a9d6: 4b0e ldr r3, [pc, #56] @ (800aa10 ) 800a9d8: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800a9dc: b2db uxtb r3, r3 800a9de: 2b21 cmp r3, #33 @ 0x21 800a9e0: d0f9 beq.n 800a9d6 HAL_Delay(10); 800a9e2: 200a movs r0, #10 800a9e4: f003 fc80 bl 800e2e8 NVIC_SystemReset(); 800a9e8: f7ff ff38 bl 800a85c <__NVIC_SystemReset> } } else{ hold_time = 0; 800a9ec: 4b06 ldr r3, [pc, #24] @ (800aa08 ) 800a9ee: 2200 movs r2, #0 800a9f0: 601a str r2, [r3, #0] 800a9f2: e002 b.n 800a9fa return; 800a9f4: bf00 nop 800a9f6: e000 b.n 800a9fa return; 800a9f8: bf00 nop } } 800a9fa: 3708 adds r7, #8 800a9fc: 46bd mov sp, r7 800a9fe: bd80 pop {r7, pc} 800aa00: 20000894 .word 0x20000894 800aa04: 20000008 .word 0x20000008 800aa08: 20000898 .word 0x20000898 800aa0c: 200003b0 .word 0x200003b0 800aa10: 200012e8 .word 0x200012e8 0800aa14 : static void CAN1_MinimalReInit(void) { 800aa14: b580 push {r7, lr} 800aa16: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan1); 800aa18: 480b ldr r0, [pc, #44] @ (800aa48 ) 800aa1a: f004 fbe9 bl 800f1f0 MX_CAN1_Init(); 800aa1e: f7ff f88f bl 8009b40 if (HAL_CAN_Start(&hcan1) != HAL_OK) { 800aa22: 4809 ldr r0, [pc, #36] @ (800aa48 ) 800aa24: f004 fba0 bl 800f168 800aa28: 4603 mov r3, r0 800aa2a: 2b00 cmp r3, #0 800aa2c: d001 beq.n 800aa32 Error_Handler(); 800aa2e: f000 f8f7 bl 800ac20 } if (HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) { 800aa32: 2102 movs r1, #2 800aa34: 4804 ldr r0, [pc, #16] @ (800aa48 ) 800aa36: f004 fe48 bl 800f6ca 800aa3a: 4603 mov r3, r0 800aa3c: 2b00 cmp r3, #0 800aa3e: d001 beq.n 800aa44 Error_Handler(); 800aa40: f000 f8ee bl 800ac20 } } 800aa44: bf00 nop 800aa46: bd80 pop {r7, pc} 800aa48: 2000035c .word 0x2000035c 0800aa4c
: /** * @brief The application entry point. * @retval int */ int main(void) { 800aa4c: b580 push {r7, lr} 800aa4e: b082 sub sp, #8 800aa50: af02 add r7, sp, #8 /* USER CODE BEGIN 1 */ VectorBase_Config(); 800aa52: f7ff ff19 bl 800a888 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800aa56: f003 fbe5 bl 800e224 /* USER CODE BEGIN Init */ HAL_RCC_DeInit(); 800aa5a: f005 fff7 bl 8010a4c /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800aa5e: f000 f86f bl 800ab40 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800aa62: f7ff fdbb bl 800a5dc MX_DMA_Init(); 800aa66: f7ff fd7b bl 800a560 MX_ADC1_Init(); 800aa6a: f7fe fd95 bl 8009598 MX_CAN1_Init(); 800aa6e: f7ff f867 bl 8009b40 MX_CAN2_Init(); 800aa72: f7ff f89b bl 8009bac MX_RTC_Init(); 800aa76: f000 fffd bl 800ba74 MX_TIM4_Init(); 800aa7a: f002 ffdb bl 800da34 MX_USART2_UART_Init(); 800aa7e: f003 f959 bl 800dd34 MX_CRC_Init(); 800aa82: f7ff fc1f bl 800a2c4 MX_UART5_Init(); 800aa86: f003 f901 bl 800dc8c MX_USART1_UART_Init(); 800aa8a: f003 f929 bl 800dce0 MX_USART3_UART_Init(); 800aa8e: f003 f97b bl 800dd88 MX_TIM3_Init(); 800aa92: f002 ff41 bl 800d918 /* USER CODE BEGIN 2 */ Init_Peripheral(); 800aa96: f7fe ff61 bl 800995c LED_Init(); 800aa9a: f000 ff2d bl 800b8f8 HAL_Delay(300); 800aa9e: f44f 7096 mov.w r0, #300 @ 0x12c 800aaa2: f003 fc21 bl 800e2e8 CCS_Init(); 800aaa6: f001 fc17 bl 800c2d8 SC_Init(); 800aaaa: f001 ffab bl 800ca04 log_printf(LOG_INFO, "CCS module start\n"); 800aaae: 491f ldr r1, [pc, #124] @ (800ab2c ) 800aab0: 2007 movs r0, #7 800aab2: f7ff fd1f bl 800a4f4 ReadVersion(); 800aab6: f001 ff81 bl 800c9bc log_printf(LOG_INFO, "Serial number: %d\n", infoPacket.serialNumber); 800aaba: 4b1d ldr r3, [pc, #116] @ (800ab30 ) 800aabc: 881b ldrh r3, [r3, #0] 800aabe: b29b uxth r3, r3 800aac0: 461a mov r2, r3 800aac2: 491c ldr r1, [pc, #112] @ (800ab34 ) 800aac4: 2007 movs r0, #7 800aac6: f7ff fd15 bl 800a4f4 log_printf(LOG_INFO, "Board revision: %d\n", infoPacket.boardVersion); 800aaca: 4b19 ldr r3, [pc, #100] @ (800ab30 ) 800aacc: 789b ldrb r3, [r3, #2] 800aace: 461a mov r2, r3 800aad0: 4919 ldr r1, [pc, #100] @ (800ab38 ) 800aad2: 2007 movs r0, #7 800aad4: f7ff fd0e bl 800a4f4 log_printf(LOG_INFO, "FW version: %d.%d.%d\n", infoPacket.fw_version_major, infoPacket.fw_version_minor, infoPacket.fw_version_patch); 800aad8: 4b15 ldr r3, [pc, #84] @ (800ab30 ) 800aada: 889b ldrh r3, [r3, #4] 800aadc: b29b uxth r3, r3 800aade: 461a mov r2, r3 800aae0: 4b13 ldr r3, [pc, #76] @ (800ab30 ) 800aae2: 88db ldrh r3, [r3, #6] 800aae4: b29b uxth r3, r3 800aae6: 4619 mov r1, r3 800aae8: 4b11 ldr r3, [pc, #68] @ (800ab30 ) 800aaea: 891b ldrh r3, [r3, #8] 800aaec: b29b uxth r3, r3 800aaee: 9300 str r3, [sp, #0] 800aaf0: 460b mov r3, r1 800aaf2: 4912 ldr r1, [pc, #72] @ (800ab3c ) 800aaf4: 2007 movs r0, #7 800aaf6: f7ff fcfd bl 800a4f4 CAN1_MinimalReInit(); 800aafa: f7ff ff8b bl 800aa14 PSU_Init(); 800aafe: f000 f9e5 bl 800aecc CONN_Init(); 800ab02: f7ff f967 bl 8009dd4 /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ PSU_ReadWrite(); 800ab06: f000 faf3 bl 800b0f0 PSU_Task(); 800ab0a: f000 fbb7 bl 800b27c ED_Delay(10); 800ab0e: 200a movs r0, #10 800ab10: f7ff feec bl 800a8ec METER_CalculateEnergy(); 800ab14: f000 f88a bl 800ac2c CONN_Loop(); 800ab18: f7ff f972 bl 8009e00 LED_Write(); 800ab1c: f000 fd9e bl 800b65c ED_Delay(10); 800ab20: 200a movs r0, #10 800ab22: f7ff fee3 bl 800a8ec PSU_ReadWrite(); 800ab26: bf00 nop 800ab28: e7ed b.n 800ab06 800ab2a: bf00 nop 800ab2c: 08017050 .word 0x08017050 800ab30: 200011b0 .word 0x200011b0 800ab34: 08017064 .word 0x08017064 800ab38: 08017078 .word 0x08017078 800ab3c: 0801708c .word 0x0801708c 0800ab40 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800ab40: b580 push {r7, lr} 800ab42: b09c sub sp, #112 @ 0x70 800ab44: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800ab46: f107 0338 add.w r3, r7, #56 @ 0x38 800ab4a: 2238 movs r2, #56 @ 0x38 800ab4c: 2100 movs r1, #0 800ab4e: 4618 mov r0, r3 800ab50: f00a f87a bl 8014c48 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800ab54: f107 0324 add.w r3, r7, #36 @ 0x24 800ab58: 2200 movs r2, #0 800ab5a: 601a str r2, [r3, #0] 800ab5c: 605a str r2, [r3, #4] 800ab5e: 609a str r2, [r3, #8] 800ab60: 60da str r2, [r3, #12] 800ab62: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 800ab64: 1d3b adds r3, r7, #4 800ab66: 2220 movs r2, #32 800ab68: 2100 movs r1, #0 800ab6a: 4618 mov r0, r3 800ab6c: f00a f86c bl 8014c48 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; 800ab70: 2305 movs r3, #5 800ab72: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800ab74: f44f 3380 mov.w r3, #65536 @ 0x10000 800ab78: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV5; 800ab7a: 2304 movs r3, #4 800ab7c: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 800ab7e: 2301 movs r3, #1 800ab80: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800ab82: 2301 movs r3, #1 800ab84: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.Prediv1Source = RCC_PREDIV1_SOURCE_PLL2; 800ab86: f44f 3380 mov.w r3, #65536 @ 0x10000 800ab8a: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800ab8c: 2302 movs r3, #2 800ab8e: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800ab90: f44f 3380 mov.w r3, #65536 @ 0x10000 800ab94: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 800ab96: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000 800ab9a: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL2.PLL2State = RCC_PLL2_ON; 800ab9c: 2302 movs r3, #2 800ab9e: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL2.PLL2MUL = RCC_PLL2_MUL8; 800aba0: f44f 63c0 mov.w r3, #1536 @ 0x600 800aba4: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL2.HSEPrediv2Value = RCC_HSE_PREDIV2_DIV5; 800aba6: 2340 movs r3, #64 @ 0x40 800aba8: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800abaa: f107 0338 add.w r3, r7, #56 @ 0x38 800abae: 4618 mov r0, r3 800abb0: f006 f81c bl 8010bec 800abb4: 4603 mov r3, r0 800abb6: 2b00 cmp r3, #0 800abb8: d001 beq.n 800abbe { Error_Handler(); 800abba: f000 f831 bl 800ac20 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800abbe: 230f movs r3, #15 800abc0: 627b str r3, [r7, #36] @ 0x24 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800abc2: 2302 movs r3, #2 800abc4: 62bb str r3, [r7, #40] @ 0x28 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800abc6: 2300 movs r3, #0 800abc8: 62fb str r3, [r7, #44] @ 0x2c RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 800abca: f44f 6380 mov.w r3, #1024 @ 0x400 800abce: 633b str r3, [r7, #48] @ 0x30 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 800abd0: 2300 movs r3, #0 800abd2: 637b str r3, [r7, #52] @ 0x34 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800abd4: f107 0324 add.w r3, r7, #36 @ 0x24 800abd8: 2102 movs r1, #2 800abda: 4618 mov r0, r3 800abdc: f006 fb1c bl 8011218 800abe0: 4603 mov r3, r0 800abe2: 2b00 cmp r3, #0 800abe4: d001 beq.n 800abea { Error_Handler(); 800abe6: f000 f81b bl 800ac20 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; 800abea: 2303 movs r3, #3 800abec: 607b str r3, [r7, #4] PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 800abee: f44f 7380 mov.w r3, #256 @ 0x100 800abf2: 60bb str r3, [r7, #8] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 800abf4: f44f 4300 mov.w r3, #32768 @ 0x8000 800abf8: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 800abfa: 1d3b adds r3, r7, #4 800abfc: 4618 mov r0, r3 800abfe: f006 fd01 bl 8011604 800ac02: 4603 mov r3, r0 800ac04: 2b00 cmp r3, #0 800ac06: d001 beq.n 800ac0c { Error_Handler(); 800ac08: f000 f80a bl 800ac20 } /** Configure the Systick interrupt time */ __HAL_RCC_PLLI2S_ENABLE(); 800ac0c: 4b03 ldr r3, [pc, #12] @ (800ac1c ) 800ac0e: 2201 movs r2, #1 800ac10: 601a str r2, [r3, #0] } 800ac12: bf00 nop 800ac14: 3770 adds r7, #112 @ 0x70 800ac16: 46bd mov sp, r7 800ac18: bd80 pop {r7, pc} 800ac1a: bf00 nop 800ac1c: 42420070 .word 0x42420070 0800ac20 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800ac20: b480 push {r7} 800ac22: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800ac24: b672 cpsid i } 800ac26: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 800ac28: bf00 nop 800ac2a: e7fd b.n 800ac28 0800ac2c : METER_t METER; // Функция для расчета и накопления энергии c дробной частью без счетчиков void METER_CalculateEnergy() { 800ac2c: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} 800ac30: b084 sub sp, #16 800ac32: af00 add r7, sp, #0 // Проверяем, что индекс находится в пределах массива METER.online = 0; 800ac34: 4b2c ldr r3, [pc, #176] @ (800ace8 ) 800ac36: 2200 movs r2, #0 800ac38: 701a strb r2, [r3, #0] if(CONN.connState == Charging){ 800ac3a: 4b2c ldr r3, [pc, #176] @ (800acec ) 800ac3c: 785b ldrb r3, [r3, #1] 800ac3e: 2b08 cmp r3, #8 800ac40: d103 bne.n 800ac4a METER.enable = 1; 800ac42: 4b29 ldr r3, [pc, #164] @ (800ace8 ) 800ac44: 2201 movs r2, #1 800ac46: 761a strb r2, [r3, #24] 800ac48: e002 b.n 800ac50 }else{ METER.enable = 0; 800ac4a: 4b27 ldr r3, [pc, #156] @ (800ace8 ) 800ac4c: 2200 movs r2, #0 800ac4e: 761a strb r2, [r3, #24] } uint32_t currentTick = HAL_GetTick(); // Получаем текущее время в миллисекундах 800ac50: f003 fb40 bl 800e2d4 800ac54: 60f8 str r0, [r7, #12] uint32_t elapsedTimeMs = currentTick - METER.lastTick; // Вычисляем время, прошедшее с последнего вызова в секундах 800ac56: 4b24 ldr r3, [pc, #144] @ (800ace8 ) 800ac58: 685b ldr r3, [r3, #4] 800ac5a: 68fa ldr r2, [r7, #12] 800ac5c: 1ad3 subs r3, r2, r3 800ac5e: 60bb str r3, [r7, #8] METER.lastTick = currentTick; // Обновляем время последнего вызова для текущего коннектора 800ac60: 4a21 ldr r2, [pc, #132] @ (800ace8 ) 800ac62: 68fb ldr r3, [r7, #12] 800ac64: 6053 str r3, [r2, #4] uint32_t energyWs = CONN.Power * elapsedTimeMs / 1000; // Рассчитываем энергию в ватт-секундах за прошедший промежуток времени 800ac66: 4b21 ldr r3, [pc, #132] @ (800acec ) 800ac68: f8d3 3003 ldr.w r3, [r3, #3] 800ac6c: 68ba ldr r2, [r7, #8] 800ac6e: fb02 f303 mul.w r3, r2, r3 800ac72: 4a1f ldr r2, [pc, #124] @ (800acf0 ) 800ac74: fba2 2303 umull r2, r3, r2, r3 800ac78: 099b lsrs r3, r3, #6 800ac7a: 607b str r3, [r7, #4] //Расчет энергии теперь идет всегда, смещение берем суммарное METER.EnergyPSU_Ws += energyWs; 800ac7c: 4b1a ldr r3, [pc, #104] @ (800ace8 ) 800ac7e: e9d3 2302 ldrd r2, r3, [r3, #8] 800ac82: 6879 ldr r1, [r7, #4] 800ac84: 2000 movs r0, #0 800ac86: 460c mov r4, r1 800ac88: 4605 mov r5, r0 800ac8a: eb12 0804 adds.w r8, r2, r4 800ac8e: eb43 0905 adc.w r9, r3, r5 800ac92: 4b15 ldr r3, [pc, #84] @ (800ace8 ) 800ac94: e9c3 8902 strd r8, r9, [r3, #8] // Абсолютное значение энергии разъема складывается из накопленной дробной части и значения со счетчиков METER.AbsoluteEnergy = (uint32_t)METER.EnergyPSU_Ws/3600; //переводим в Вт*час 800ac98: 4b13 ldr r3, [pc, #76] @ (800ace8 ) 800ac9a: e9d3 2302 ldrd r2, r3, [r3, #8] 800ac9e: 4b15 ldr r3, [pc, #84] @ (800acf4 ) 800aca0: fba3 2302 umull r2, r3, r3, r2 800aca4: 0adb lsrs r3, r3, #11 800aca6: 4a10 ldr r2, [pc, #64] @ (800ace8 ) 800aca8: 6113 str r3, [r2, #16] if(METER.enable) { 800acaa: 4b0f ldr r3, [pc, #60] @ (800ace8 ) 800acac: 7e1b ldrb r3, [r3, #24] 800acae: 2b00 cmp r3, #0 800acb0: d008 beq.n 800acc4 //enabled state CONN.Energy = METER.AbsoluteEnergy - METER.EnergyOffset;//переводим в Вт*час 800acb2: 4b0d ldr r3, [pc, #52] @ (800ace8 ) 800acb4: 691a ldr r2, [r3, #16] 800acb6: 4b0c ldr r3, [pc, #48] @ (800ace8 ) 800acb8: 695b ldr r3, [r3, #20] 800acba: 1ad3 subs r3, r2, r3 800acbc: 4a0b ldr r2, [pc, #44] @ (800acec ) 800acbe: f8c2 3007 str.w r3, [r2, #7] METER.EnergyOffset = METER.AbsoluteEnergy; } } 800acc2: e00c b.n 800acde CONN.Energy = 0; 800acc4: 4b09 ldr r3, [pc, #36] @ (800acec ) 800acc6: 2200 movs r2, #0 800acc8: 71da strb r2, [r3, #7] 800acca: 2200 movs r2, #0 800accc: 721a strb r2, [r3, #8] 800acce: 2200 movs r2, #0 800acd0: 725a strb r2, [r3, #9] 800acd2: 2200 movs r2, #0 800acd4: 729a strb r2, [r3, #10] METER.EnergyOffset = METER.AbsoluteEnergy; 800acd6: 4b04 ldr r3, [pc, #16] @ (800ace8 ) 800acd8: 691b ldr r3, [r3, #16] 800acda: 4a03 ldr r2, [pc, #12] @ (800ace8 ) 800acdc: 6153 str r3, [r2, #20] } 800acde: bf00 nop 800ace0: 3710 adds r7, #16 800ace2: 46bd mov sp, r7 800ace4: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} 800ace8: 200008a0 .word 0x200008a0 800acec: 200003b0 .word 0x200003b0 800acf0: 10624dd3 .word 0x10624dd3 800acf4: 91a2b3c5 .word 0x91a2b3c5 0800acf8 : extern CAN_HandleTypeDef hcan2; static void PSU_SendCmd(uint8_t source, uint8_t destination, uint8_t cmd, void *data); static void PSU_SwitchState(PSU_State_t state){ 800acf8: b580 push {r7, lr} 800acfa: b082 sub sp, #8 800acfc: af00 add r7, sp, #0 800acfe: 4603 mov r3, r0 800ad00: 71fb strb r3, [r7, #7] PSU0.state = state; 800ad02: 4a06 ldr r2, [pc, #24] @ (800ad1c ) 800ad04: 79fb ldrb r3, [r7, #7] 800ad06: 71d3 strb r3, [r2, #7] PSU0.statetick = HAL_GetTick(); 800ad08: f003 fae4 bl 800e2d4 800ad0c: 4603 mov r3, r0 800ad0e: 4a03 ldr r2, [pc, #12] @ (800ad1c ) 800ad10: 6113 str r3, [r2, #16] } 800ad12: bf00 nop 800ad14: 3708 adds r7, #8 800ad16: 46bd mov sp, r7 800ad18: bd80 pop {r7, pc} 800ad1a: bf00 nop 800ad1c: 20000904 .word 0x20000904 0800ad20 : static uint32_t PSU_StateTime(void){ 800ad20: b580 push {r7, lr} 800ad22: af00 add r7, sp, #0 return HAL_GetTick() - PSU0.statetick; 800ad24: f003 fad6 bl 800e2d4 800ad28: 4602 mov r2, r0 800ad2a: 4b02 ldr r3, [pc, #8] @ (800ad34 ) 800ad2c: 691b ldr r3, [r3, #16] 800ad2e: 1ad3 subs r3, r2, r3 } 800ad30: 4618 mov r0, r3 800ad32: bd80 pop {r7, pc} 800ad34: 20000904 .word 0x20000904 0800ad38 : ISR_FAST void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan){ 800ad38: b538 push {r3, r4, r5, lr} static CAN_RxHeaderTypeDef RxHeader; static uint8_t RxData[8] = {0,}; CanId_t CanId; if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO1, &RxHeader, RxData) == HAL_OK) 800ad3a: 4c42 ldr r4, [pc, #264] @ (800ae44 ) 800ad3c: 4d42 ldr r5, [pc, #264] @ (800ae48 ) 800ad3e: 4623 mov r3, r4 800ad40: 462a mov r2, r5 800ad42: 2101 movs r1, #1 800ad44: f004 fba0 bl 800f488 800ad48: b910 cbnz r0, 800ad50 { memcpy(&CanId, &RxHeader.ExtId, sizeof(CanId_t)); 800ad4a: 686d ldr r5, [r5, #4] /* Для DC30 поддерживается только один силовой модуль (source == 0) */ if(CanId.source != 0) return; 800ad4c: b2eb uxtb r3, r5 800ad4e: b103 cbz r3, 800ad52 CONN.outputEnabled = PSU0.PSU_enabled; } } } } } 800ad50: bd38 pop {r3, r4, r5, pc} can_lastpacket = HAL_GetTick(); 800ad52: f003 fabf bl 800e2d4 if(CanId.command==0x02){ 800ad56: f3c5 4505 ubfx r5, r5, #16, #6 can_lastpacket = HAL_GetTick(); 800ad5a: 4b3c ldr r3, [pc, #240] @ (800ae4c ) if(CanId.command==0x02){ 800ad5c: 2d02 cmp r5, #2 can_lastpacket = HAL_GetTick(); 800ad5e: 6018 str r0, [r3, #0] if(CanId.command==0x02){ 800ad60: d013 beq.n 800ad8a if(CanId.command==0x04){ 800ad62: 2d04 cmp r5, #4 800ad64: d117 bne.n 800ad96 memcpy(&PSU_04, RxData, 8); 800ad66: e894 0003 ldmia.w r4, {r0, r1} 800ad6a: 4b39 ldr r3, [pc, #228] @ (800ae50 ) PSU0.tempAmbient = PSU_04.moduleTemperature; 800ad6c: 4a39 ldr r2, [pc, #228] @ (800ae54 ) memcpy(&PSU_04, RxData, 8); 800ad6e: e883 0003 stmia.w r3, {r0, r1} PSU0.status0.raw = PSU_04.modularForm0; 800ad72: 7a18 ldrb r0, [r3, #8] PSU0.tempAmbient = PSU_04.moduleTemperature; 800ad74: 791c ldrb r4, [r3, #4] PSU0.status1.raw = PSU_04.modularForm1; 800ad76: 79d9 ldrb r1, [r3, #7] PSU0.status2.raw = PSU_04.modularForm2; 800ad78: 799b ldrb r3, [r3, #6] PSU0.tempAmbient = PSU_04.moduleTemperature; 800ad7a: 6214 str r4, [r2, #32] PSU0.status0.raw = PSU_04.modularForm0; 800ad7c: f882 0024 strb.w r0, [r2, #36] @ 0x24 PSU0.status1.raw = PSU_04.modularForm1; 800ad80: f882 1025 strb.w r1, [r2, #37] @ 0x25 PSU0.status2.raw = PSU_04.modularForm2; 800ad84: f882 3026 strb.w r3, [r2, #38] @ 0x26 } 800ad88: bd38 pop {r3, r4, r5, pc} memcpy(&PSU_02, RxData, 8); 800ad8a: 4b33 ldr r3, [pc, #204] @ (800ae58 ) 800ad8c: e894 0003 ldmia.w r4, {r0, r1} 800ad90: e883 0003 stmia.w r3, {r0, r1} } 800ad94: bd38 pop {r3, r4, r5, pc} if(CanId.command==0x06){ 800ad96: 2d06 cmp r5, #6 800ad98: d111 bne.n 800adbe memcpy(&PSU_06, RxData, 8); 800ad9a: e894 0003 ldmia.w r4, {r0, r1} 800ad9e: 4b2f ldr r3, [pc, #188] @ (800ae5c ) 800ada0: e883 0003 stmia.w r3, {r0, r1} PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800ada4: 8818 ldrh r0, [r3, #0] PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ada6: 8859 ldrh r1, [r3, #2] PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ada8: 889a ldrh r2, [r3, #4] PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800adaa: ba40 rev16 r0, r0 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800adac: ba49 rev16 r1, r1 PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800adae: ba52 rev16 r2, r2 PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800adb0: b280 uxth r0, r0 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800adb2: b289 uxth r1, r1 PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800adb4: b292 uxth r2, r2 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800adb6: e9c3 0102 strd r0, r1, [r3, #8] PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800adba: 611a str r2, [r3, #16] } 800adbc: bd38 pop {r3, r4, r5, pc} if(CanId.command==0x08){ 800adbe: 2d08 cmp r5, #8 800adc0: d03a beq.n 800ae38 if(CanId.command==0x09){ 800adc2: 2d09 cmp r5, #9 800adc4: d1c4 bne.n 800ad50 memcpy(&PSU_09, RxData, 8); 800adc6: e894 0003 ldmia.w r4, {r0, r1} PSU0.temperature = PSU_04.moduleTemperature; 800adca: 4b21 ldr r3, [pc, #132] @ (800ae50 ) memcpy(&PSU_09, RxData, 8); 800adcc: 4d24 ldr r5, [pc, #144] @ (800ae60 ) PSU0.outputVoltage = v; 800adce: 4c21 ldr r4, [pc, #132] @ (800ae54 ) PSU0.temperature = PSU_04.moduleTemperature; 800add0: f893 c004 ldrb.w ip, [r3, #4] uint16_t v = PSU_09.moduleNVoltage / 1000; 800add4: 4a23 ldr r2, [pc, #140] @ (800ae64 ) memcpy(&PSU_09, RxData, 8); 800add6: e885 0003 stmia.w r5, {r0, r1} PSU_09.moduleNCurrent = PSU_09.moduleNCurrent_[3]; 800adda: ba00 rev r0, r0 PSU0.temperature = PSU_04.moduleTemperature; 800addc: f884 c006 strb.w ip, [r4, #6] uint16_t v = PSU_09.moduleNVoltage / 1000; 800ade0: fba2 c200 umull ip, r2, r2, r0 800ade4: ba09 rev r1, r1 PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[0]<<24; 800ade6: e9c5 0102 strd r0, r1, [r5, #8] uint16_t v = PSU_09.moduleNVoltage / 1000; 800adea: f3c2 108f ubfx r0, r2, #6, #16 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800adee: 2813 cmp r0, #19 PSU0.online = 1; 800adf0: f04f 0e01 mov.w lr, #1 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800adf4: bf94 ite ls 800adf6: 2500 movls r5, #0 800adf8: 2501 movhi r5, #1 int16_t i = PSU_09.moduleNCurrent / 100; 800adfa: 4b1b ldr r3, [pc, #108] @ (800ae68 ) PSU0.online = 1; 800adfc: f884 e008 strb.w lr, [r4, #8] int16_t i = PSU_09.moduleNCurrent / 100; 800ae00: fba3 c301 umull ip, r3, r3, r1 if(PSU0.state >= PSU_READY){ 800ae04: 79e1 ldrb r1, [r4, #7] int16_t i = PSU_09.moduleNCurrent / 100; 800ae06: 095b lsrs r3, r3, #5 if(PSU0.state >= PSU_READY){ 800ae08: 4571 cmp r1, lr PSU0.outputVoltage = v; 800ae0a: 8060 strh r0, [r4, #2] int16_t i = PSU_09.moduleNCurrent / 100; 800ae0c: 80a3 strh r3, [r4, #4] uint16_t v = PSU_09.moduleNVoltage / 1000; 800ae0e: ea4f 1292 mov.w r2, r2, lsr #6 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800ae12: 72a5 strb r5, [r4, #10] if(PSU0.state >= PSU_READY){ 800ae14: d99c bls.n 800ad50 CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800ae16: b299 uxth r1, r3 800ae18: b292 uxth r2, r2 800ae1a: fb01 f202 mul.w r2, r1, r2 800ae1e: 4c13 ldr r4, [pc, #76] @ (800ae6c ) CONN.MeasuredVoltage = PSU0.outputVoltage; 800ae20: 4913 ldr r1, [pc, #76] @ (800ae70 ) CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800ae22: fba4 4202 umull r4, r2, r4, r2 CONN.MeasuredCurrent = PSU0.outputCurrent; 800ae26: f8a1 3015 strh.w r3, [r1, #21] CONN.outputEnabled = PSU0.PSU_enabled; 800ae2a: 760d strb r5, [r1, #24] CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800ae2c: 08d3 lsrs r3, r2, #3 CONN.MeasuredVoltage = PSU0.outputVoltage; 800ae2e: f8a1 0013 strh.w r0, [r1, #19] CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800ae32: f8c1 3003 str.w r3, [r1, #3] } 800ae36: bd38 pop {r3, r4, r5, pc} memcpy(&PSU_08, RxData, 8); 800ae38: 4b0e ldr r3, [pc, #56] @ (800ae74 ) 800ae3a: e894 0003 ldmia.w r4, {r0, r1} 800ae3e: e883 0003 stmia.w r3, {r0, r1} } 800ae42: bd38 pop {r3, r4, r5, pc} 800ae44: 2000094c .word 0x2000094c 800ae48: 20000930 .word 0x20000930 800ae4c: 2000092c .word 0x2000092c 800ae50: 200008cc .word 0x200008cc 800ae54: 20000904 .word 0x20000904 800ae58: 200008c0 .word 0x200008c0 800ae5c: 200008d8 .word 0x200008d8 800ae60: 200008f4 .word 0x200008f4 800ae64: 10624dd3 .word 0x10624dd3 800ae68: 51eb851f .word 0x51eb851f 800ae6c: cccccccd .word 0xcccccccd 800ae70: 200003b0 .word 0x200003b0 800ae74: 200008ec .word 0x200008ec 0800ae78 : void PSU_CAN_FilterInit(){ 800ae78: b580 push {r7, lr} 800ae7a: b08a sub sp, #40 @ 0x28 800ae7c: af00 add r7, sp, #0 CAN_FilterTypeDef sFilterConfig; sFilterConfig.FilterBank = 14; 800ae7e: 230e movs r3, #14 800ae80: 617b str r3, [r7, #20] sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; 800ae82: 2300 movs r3, #0 800ae84: 61bb str r3, [r7, #24] sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; 800ae86: 2301 movs r3, #1 800ae88: 61fb str r3, [r7, #28] sFilterConfig.FilterIdHigh = 0x0000; 800ae8a: 2300 movs r3, #0 800ae8c: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = 0x0000; 800ae8e: 2300 movs r3, #0 800ae90: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 800ae92: 2300 movs r3, #0 800ae94: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = 0x0000; 800ae96: 2300 movs r3, #0 800ae98: 60fb str r3, [r7, #12] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; 800ae9a: 2300 movs r3, #0 800ae9c: 613b str r3, [r7, #16] sFilterConfig.FilterActivation = ENABLE; 800ae9e: 2301 movs r3, #1 800aea0: 623b str r3, [r7, #32] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 800aea2: 2301 movs r3, #1 800aea4: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 800aea6: 230e movs r3, #14 800aea8: 627b str r3, [r7, #36] @ 0x24 if(HAL_CAN_ConfigFilter(&hcan2, &sFilterConfig) != HAL_OK) 800aeaa: 463b mov r3, r7 800aeac: 4619 mov r1, r3 800aeae: 4806 ldr r0, [pc, #24] @ (800aec8 ) 800aeb0: f004 f87a bl 800efa8 800aeb4: 4603 mov r3, r0 800aeb6: 2b00 cmp r3, #0 800aeb8: d001 beq.n 800aebe { Error_Handler(); 800aeba: f7ff feb1 bl 800ac20 } } 800aebe: bf00 nop 800aec0: 3728 adds r7, #40 @ 0x28 800aec2: 46bd mov sp, r7 800aec4: bd80 pop {r7, pc} 800aec6: bf00 nop 800aec8: 20000384 .word 0x20000384 0800aecc : void PSU_Init(){ 800aecc: b580 push {r7, lr} 800aece: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan2); 800aed0: 4815 ldr r0, [pc, #84] @ (800af28 ) 800aed2: f004 f98d bl 800f1f0 MX_CAN2_Init(); 800aed6: f7fe fe69 bl 8009bac PSU_CAN_FilterInit(); 800aeda: f7ff ffcd bl 800ae78 HAL_CAN_Start(&hcan2); 800aede: 4812 ldr r0, [pc, #72] @ (800af28 ) 800aee0: f004 f942 bl 800f168 HAL_CAN_ActivateNotification(&hcan2, CAN_IT_RX_FIFO1_MSG_PENDING /* | CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | CAN_IT_TX_MAILBOX_EMPTY*/); 800aee4: 2110 movs r1, #16 800aee6: 4810 ldr r0, [pc, #64] @ (800af28 ) 800aee8: f004 fbef bl 800f6ca memset(&PSU0, 0, sizeof(PSU0)); 800aeec: 2228 movs r2, #40 @ 0x28 800aeee: 2100 movs r1, #0 800aef0: 480e ldr r0, [pc, #56] @ (800af2c ) 800aef2: f009 fea9 bl 8014c48 PSU0.state = PSU_UNREADY; 800aef6: 4b0d ldr r3, [pc, #52] @ (800af2c ) 800aef8: 2200 movs r2, #0 800aefa: 71da strb r2, [r3, #7] PSU0.statetick = HAL_GetTick(); 800aefc: f003 f9ea bl 800e2d4 800af00: 4603 mov r3, r0 800af02: 4a0a ldr r2, [pc, #40] @ (800af2c ) 800af04: 6113 str r3, [r2, #16] PSU0.power_limit = PSU_MAX_POWER; // kW 800af06: 4b09 ldr r3, [pc, #36] @ (800af2c ) 800af08: f649 4240 movw r2, #40000 @ 0x9c40 800af0c: 615a str r2, [r3, #20] PSU0.hv_mode = 0; 800af0e: 4b07 ldr r3, [pc, #28] @ (800af2c ) 800af10: 2200 movs r2, #0 800af12: 761a strb r2, [r3, #24] PSU0.hv_tick = 0; 800af14: 4b05 ldr r3, [pc, #20] @ (800af2c ) 800af16: 2200 movs r2, #0 800af18: 61da str r2, [r3, #28] PSU_Enable(0, 0); 800af1a: 2100 movs r1, #0 800af1c: 2000 movs r0, #0 800af1e: f000 f807 bl 800af30 } 800af22: bf00 nop 800af24: bd80 pop {r7, pc} 800af26: bf00 nop 800af28: 20000384 .word 0x20000384 800af2c: 20000904 .word 0x20000904 0800af30 : void PSU_Enable(uint8_t addr, uint8_t enable){ 800af30: b580 push {r7, lr} 800af32: b084 sub sp, #16 800af34: af00 add r7, sp, #0 800af36: 4603 mov r3, r0 800af38: 460a mov r2, r1 800af3a: 71fb strb r3, [r7, #7] 800af3c: 4613 mov r3, r2 800af3e: 71bb strb r3, [r7, #6] PSU_1A_t data; memset(&data, 0, sizeof(data)); 800af40: f107 0308 add.w r3, r7, #8 800af44: 2208 movs r2, #8 800af46: 2100 movs r1, #0 800af48: 4618 mov r0, r3 800af4a: f009 fe7d bl 8014c48 /* Для DC30 поддерживается только один модуль с адресом 0 */ if(addr != 0) return; 800af4e: 79fb ldrb r3, [r7, #7] 800af50: 2b00 cmp r3, #0 800af52: d115 bne.n 800af80 if(PSU0.online == 0) return; 800af54: 4b0d ldr r3, [pc, #52] @ (800af8c ) 800af56: 7a1b ldrb r3, [r3, #8] 800af58: 2b00 cmp r3, #0 800af5a: d013 beq.n 800af84 data.enable = !enable; 800af5c: 79bb ldrb r3, [r7, #6] 800af5e: 2b00 cmp r3, #0 800af60: bf0c ite eq 800af62: 2301 moveq r3, #1 800af64: 2300 movne r3, #0 800af66: b2db uxtb r3, r3 800af68: 723b strb r3, [r7, #8] PSU_SendCmd(0xF0, addr, 0x1A, &data); 800af6a: f107 0308 add.w r3, r7, #8 800af6e: 79f9 ldrb r1, [r7, #7] 800af70: 221a movs r2, #26 800af72: 20f0 movs r0, #240 @ 0xf0 800af74: f000 f866 bl 800b044 ED_Delay(CAN_DELAY); 800af78: 2014 movs r0, #20 800af7a: f7ff fcb7 bl 800a8ec 800af7e: e002 b.n 800af86 if(addr != 0) return; 800af80: bf00 nop 800af82: e000 b.n 800af86 if(PSU0.online == 0) return; 800af84: bf00 nop } 800af86: 3710 adds r7, #16 800af88: 46bd mov sp, r7 800af8a: bd80 pop {r7, pc} 800af8c: 20000904 .word 0x20000904 0800af90 : memset(&data, 0, sizeof(data)); data.enable = !enable; if(addr != 0) return; PSU_SendCmd(0xF0, addr, 0x1D, &data); } void PSU_SetVoltageCurrent(uint8_t addr, uint16_t voltage, uint16_t current){ 800af90: b580 push {r7, lr} 800af92: b086 sub sp, #24 800af94: af00 add r7, sp, #0 800af96: 4603 mov r3, r0 800af98: 71fb strb r3, [r7, #7] 800af9a: 460b mov r3, r1 800af9c: 80bb strh r3, [r7, #4] 800af9e: 4613 mov r3, r2 800afa0: 807b strh r3, [r7, #2] PSU_1C_t data; memset(&data, 0, sizeof(data)); 800afa2: f107 0308 add.w r3, r7, #8 800afa6: 2208 movs r2, #8 800afa8: 2100 movs r1, #0 800afaa: 4618 mov r0, r3 800afac: f009 fe4c bl 8014c48 if(addr != 0) return; 800afb0: 79fb ldrb r3, [r7, #7] 800afb2: 2b00 cmp r3, #0 800afb4: d140 bne.n 800b038 if(voltage 800afbc: 2396 movs r3, #150 @ 0x96 800afbe: 80bb strh r3, [r7, #4] if((PSU0.hv_mode==0) && voltage>499) voltage = 499; 800afc0: 4b1f ldr r3, [pc, #124] @ (800b040 ) 800afc2: 7e1b ldrb r3, [r3, #24] 800afc4: 2b00 cmp r3, #0 800afc6: d106 bne.n 800afd6 800afc8: 88bb ldrh r3, [r7, #4] 800afca: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800afce: d302 bcc.n 800afd6 800afd0: f240 13f3 movw r3, #499 @ 0x1f3 800afd4: 80bb strh r3, [r7, #4] uint32_t current_ma = current * 100; 800afd6: 887b ldrh r3, [r7, #2] 800afd8: 2264 movs r2, #100 @ 0x64 800afda: fb02 f303 mul.w r3, r2, r3 800afde: 617b str r3, [r7, #20] uint32_t voltage_mv = voltage * 1000; 800afe0: 88bb ldrh r3, [r7, #4] 800afe2: f44f 727a mov.w r2, #1000 @ 0x3e8 800afe6: fb02 f303 mul.w r3, r2, r3 800afea: 613b str r3, [r7, #16] data.moduleCurrentTotal[0] = (current_ma >> 24) & 0xFF; 800afec: 697b ldr r3, [r7, #20] 800afee: 0e1b lsrs r3, r3, #24 800aff0: b2db uxtb r3, r3 800aff2: 733b strb r3, [r7, #12] data.moduleCurrentTotal[1] = (current_ma >> 16) & 0xFF; 800aff4: 697b ldr r3, [r7, #20] 800aff6: 0c1b lsrs r3, r3, #16 800aff8: b2db uxtb r3, r3 800affa: 737b strb r3, [r7, #13] data.moduleCurrentTotal[2] = (current_ma >> 8) & 0xFF; 800affc: 697b ldr r3, [r7, #20] 800affe: 0a1b lsrs r3, r3, #8 800b000: b2db uxtb r3, r3 800b002: 73bb strb r3, [r7, #14] data.moduleCurrentTotal[3] = (current_ma >> 0) & 0xFF; 800b004: 697b ldr r3, [r7, #20] 800b006: b2db uxtb r3, r3 800b008: 73fb strb r3, [r7, #15] data.moduleVoltage[0] = (voltage_mv >> 24) & 0xFF; 800b00a: 693b ldr r3, [r7, #16] 800b00c: 0e1b lsrs r3, r3, #24 800b00e: b2db uxtb r3, r3 800b010: 723b strb r3, [r7, #8] data.moduleVoltage[1] = (voltage_mv >> 16) & 0xFF; 800b012: 693b ldr r3, [r7, #16] 800b014: 0c1b lsrs r3, r3, #16 800b016: b2db uxtb r3, r3 800b018: 727b strb r3, [r7, #9] data.moduleVoltage[2] = (voltage_mv >> 8) & 0xFF; 800b01a: 693b ldr r3, [r7, #16] 800b01c: 0a1b lsrs r3, r3, #8 800b01e: b2db uxtb r3, r3 800b020: 72bb strb r3, [r7, #10] data.moduleVoltage[3] = (voltage_mv >> 0) & 0xFF; 800b022: 693b ldr r3, [r7, #16] 800b024: b2db uxtb r3, r3 800b026: 72fb strb r3, [r7, #11] PSU_SendCmd(0xF0, addr, 0x1C, &data); 800b028: f107 0308 add.w r3, r7, #8 800b02c: 79f9 ldrb r1, [r7, #7] 800b02e: 221c movs r2, #28 800b030: 20f0 movs r0, #240 @ 0xf0 800b032: f000 f807 bl 800b044 800b036: e000 b.n 800b03a if(addr != 0) return; 800b038: bf00 nop } 800b03a: 3718 adds r7, #24 800b03c: 46bd mov sp, r7 800b03e: bd80 pop {r7, pc} 800b040: 20000904 .word 0x20000904 0800b044 : void PSU_SendCmd(uint8_t source, uint8_t destination, uint8_t cmd, void *data){ 800b044: b580 push {r7, lr} 800b046: b08c sub sp, #48 @ 0x30 800b048: af00 add r7, sp, #0 800b04a: 603b str r3, [r7, #0] 800b04c: 4603 mov r3, r0 800b04e: 71fb strb r3, [r7, #7] 800b050: 460b mov r3, r1 800b052: 71bb strb r3, [r7, #6] 800b054: 4613 mov r3, r2 800b056: 717b strb r3, [r7, #5] CanId_t CanId; CanId.source = source; 800b058: 79fb ldrb r3, [r7, #7] 800b05a: f887 3028 strb.w r3, [r7, #40] @ 0x28 CanId.destination = destination; 800b05e: 79bb ldrb r3, [r7, #6] 800b060: f887 3029 strb.w r3, [r7, #41] @ 0x29 CanId.command = cmd; 800b064: 797b ldrb r3, [r7, #5] 800b066: f003 033f and.w r3, r3, #63 @ 0x3f 800b06a: b2da uxtb r2, r3 800b06c: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 800b070: f362 0305 bfi r3, r2, #0, #6 800b074: f887 302a strb.w r3, [r7, #42] @ 0x2a CanId.device = 0x0A; 800b078: 8d7b ldrh r3, [r7, #42] @ 0x2a 800b07a: 220a movs r2, #10 800b07c: f362 1389 bfi r3, r2, #6, #4 800b080: 857b strh r3, [r7, #42] @ 0x2a int8_t retry_counter = 10; 800b082: 230a movs r3, #10 800b084: f887 302f strb.w r3, [r7, #47] @ 0x2f CAN_TxHeaderTypeDef tx_header; uint32_t tx_mailbox; HAL_StatusTypeDef CAN_result; memcpy(&tx_header.ExtId, &CanId, sizeof(CanId_t)); 800b088: 6abb ldr r3, [r7, #40] @ 0x28 800b08a: 617b str r3, [r7, #20] tx_header.RTR = CAN_RTR_DATA; 800b08c: 2300 movs r3, #0 800b08e: 61fb str r3, [r7, #28] tx_header.IDE = CAN_ID_EXT; 800b090: 2304 movs r3, #4 800b092: 61bb str r3, [r7, #24] tx_header.DLC = 8; 800b094: 2308 movs r3, #8 800b096: 623b str r3, [r7, #32] while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800b098: e01e b.n 800b0d8 if (HAL_CAN_GetTxMailboxesFreeLevel(&hcan2) > 0){ 800b09a: 4814 ldr r0, [pc, #80] @ (800b0ec ) 800b09c: f004 f9c0 bl 800f420 800b0a0: 4603 mov r3, r0 800b0a2: 2b00 cmp r3, #0 800b0a4: d00e beq.n 800b0c4 /* отправка сообщения */ CAN_result = HAL_CAN_AddTxMessage(&hcan2, &tx_header, (uint8_t*)data, &tx_mailbox); 800b0a6: f107 030c add.w r3, r7, #12 800b0aa: f107 0110 add.w r1, r7, #16 800b0ae: 683a ldr r2, [r7, #0] 800b0b0: 480e ldr r0, [pc, #56] @ (800b0ec ) 800b0b2: f004 f8e6 bl 800f282 800b0b6: 4603 mov r3, r0 800b0b8: f887 302e strb.w r3, [r7, #46] @ 0x2e /* если отправка удалась, выход */ if(CAN_result == HAL_OK) { 800b0bc: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 800b0c0: 2b00 cmp r3, #0 800b0c2: d00e beq.n 800b0e2 return; } } ED_Delay(1); 800b0c4: 2001 movs r0, #1 800b0c6: f7ff fc11 bl 800a8ec retry_counter--; 800b0ca: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800b0ce: b2db uxtb r3, r3 800b0d0: 3b01 subs r3, #1 800b0d2: b2db uxtb r3, r3 800b0d4: f887 302f strb.w r3, [r7, #47] @ 0x2f while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800b0d8: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800b0dc: 2b00 cmp r3, #0 800b0de: dcdc bgt.n 800b09a 800b0e0: e000 b.n 800b0e4 return; 800b0e2: bf00 nop } } 800b0e4: 3730 adds r7, #48 @ 0x30 800b0e6: 46bd mov sp, r7 800b0e8: bd80 pop {r7, pc} 800b0ea: bf00 nop 800b0ec: 20000384 .word 0x20000384 0800b0f0 : void PSU_ReadWrite(){ 800b0f0: b580 push {r7, lr} 800b0f2: b082 sub sp, #8 800b0f4: af00 add r7, sp, #0 uint8_t zero_data[8] = {0,0,0,0,0,0,0,0}; 800b0f6: 463b mov r3, r7 800b0f8: 2200 movs r2, #0 800b0fa: 601a str r2, [r3, #0] 800b0fc: 605a str r2, [r3, #4] PSU_SendCmd(0xF0, 0, 0x04, zero_data);ED_Delay(CAN_DELAY); 800b0fe: 463b mov r3, r7 800b100: 2204 movs r2, #4 800b102: 2100 movs r1, #0 800b104: 20f0 movs r0, #240 @ 0xf0 800b106: f7ff ff9d bl 800b044 800b10a: 2014 movs r0, #20 800b10c: f7ff fbee bl 800a8ec PSU_SendCmd(0xF0, 0, 0x06, zero_data);ED_Delay(CAN_DELAY); 800b110: 463b mov r3, r7 800b112: 2206 movs r2, #6 800b114: 2100 movs r1, #0 800b116: 20f0 movs r0, #240 @ 0xf0 800b118: f7ff ff94 bl 800b044 800b11c: 2014 movs r0, #20 800b11e: f7ff fbe5 bl 800a8ec // PSU_SendCmd(0xF0, 0, 0x08, zero_data);ED_Delay(CAN_DELAY); PSU_SendCmd(0xF0, 0, 0x09, zero_data);ED_Delay(CAN_DELAY); 800b122: 463b mov r3, r7 800b124: 2209 movs r2, #9 800b126: 2100 movs r1, #0 800b128: 20f0 movs r0, #240 @ 0xf0 800b12a: f7ff ff8b bl 800b044 800b12e: 2014 movs r0, #20 800b130: f7ff fbdc bl 800a8ec // Power Limit if ((CONN.WantedCurrent/10) * CONN.MeasuredVoltage > PSU0.power_limit){ 800b134: 4b4d ldr r3, [pc, #308] @ (800b26c ) 800b136: f8b3 301b ldrh.w r3, [r3, #27] 800b13a: b29b uxth r3, r3 800b13c: 4a4c ldr r2, [pc, #304] @ (800b270 ) 800b13e: fba2 2303 umull r2, r3, r2, r3 800b142: 08db lsrs r3, r3, #3 800b144: b29b uxth r3, r3 800b146: 461a mov r2, r3 800b148: 4b48 ldr r3, [pc, #288] @ (800b26c ) 800b14a: f8b3 3013 ldrh.w r3, [r3, #19] 800b14e: b29b uxth r3, r3 800b150: fb02 f303 mul.w r3, r2, r3 800b154: 461a mov r2, r3 800b156: 4b47 ldr r3, [pc, #284] @ (800b274 ) 800b158: 695b ldr r3, [r3, #20] 800b15a: 429a cmp r2, r3 800b15c: d911 bls.n 800b182 CONN.RequestedCurrent = PSU0.power_limit * 10 / CONN.MeasuredVoltage; 800b15e: 4b45 ldr r3, [pc, #276] @ (800b274 ) 800b160: 695a ldr r2, [r3, #20] 800b162: 4613 mov r3, r2 800b164: 009b lsls r3, r3, #2 800b166: 4413 add r3, r2 800b168: 005b lsls r3, r3, #1 800b16a: 461a mov r2, r3 800b16c: 4b3f ldr r3, [pc, #252] @ (800b26c ) 800b16e: f8b3 3013 ldrh.w r3, [r3, #19] 800b172: b29b uxth r3, r3 800b174: fbb2 f3f3 udiv r3, r2, r3 800b178: b29a uxth r2, r3 800b17a: 4b3c ldr r3, [pc, #240] @ (800b26c ) 800b17c: f8a3 2011 strh.w r2, [r3, #17] 800b180: e006 b.n 800b190 }else{ CONN.RequestedCurrent = CONN.WantedCurrent; 800b182: 4b3a ldr r3, [pc, #232] @ (800b26c ) 800b184: f8b3 301b ldrh.w r3, [r3, #27] 800b188: b29a uxth r2, r3 800b18a: 4b38 ldr r3, [pc, #224] @ (800b26c ) 800b18c: f8a3 2011 strh.w r2, [r3, #17] } if(CONN.RequestedCurrent > (PSU_MAX_CURRENT*10)){ 800b190: 4b36 ldr r3, [pc, #216] @ (800b26c ) 800b192: f8b3 3011 ldrh.w r3, [r3, #17] 800b196: b29b uxth r3, r3 800b198: f240 5232 movw r2, #1330 @ 0x532 800b19c: 4293 cmp r3, r2 800b19e: d908 bls.n 800b1b2 CONN.RequestedCurrent = PSU_MAX_CURRENT*10; 800b1a0: 4b32 ldr r3, [pc, #200] @ (800b26c ) 800b1a2: 2200 movs r2, #0 800b1a4: f042 0232 orr.w r2, r2, #50 @ 0x32 800b1a8: 745a strb r2, [r3, #17] 800b1aa: 2200 movs r2, #0 800b1ac: f042 0205 orr.w r2, r2, #5 800b1b0: 749a strb r2, [r3, #18] } CONN.RequestedPower = CONN.RequestedCurrent * CONN.RequestedVoltage / 10; 800b1b2: 4b2e ldr r3, [pc, #184] @ (800b26c ) 800b1b4: f8b3 3011 ldrh.w r3, [r3, #17] 800b1b8: b29b uxth r3, r3 800b1ba: 461a mov r2, r3 800b1bc: 4b2b ldr r3, [pc, #172] @ (800b26c ) 800b1be: f8b3 300f ldrh.w r3, [r3, #15] 800b1c2: b29b uxth r3, r3 800b1c4: fb02 f303 mul.w r3, r2, r3 800b1c8: 4a2b ldr r2, [pc, #172] @ (800b278 ) 800b1ca: fb82 1203 smull r1, r2, r2, r3 800b1ce: 1092 asrs r2, r2, #2 800b1d0: 17db asrs r3, r3, #31 800b1d2: 1ad3 subs r3, r2, r3 800b1d4: 461a mov r2, r3 800b1d6: 4b25 ldr r3, [pc, #148] @ (800b26c ) 800b1d8: f8c3 200b str.w r2, [r3, #11] if(PSU0.ready){ 800b1dc: 4b25 ldr r3, [pc, #148] @ (800b274 ) 800b1de: 7a5b ldrb r3, [r3, #9] 800b1e0: 2b00 cmp r3, #0 800b1e2: d03e beq.n 800b262 if (CONN.RequestedVoltage == FAKE_EVREQ_VOLTAGE_V) { 800b1e4: 4b21 ldr r3, [pc, #132] @ (800b26c ) 800b1e6: f8b3 300f ldrh.w r3, [r3, #15] 800b1ea: b29b uxth r3, r3 800b1ec: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b1f0: d106 bne.n 800b200 PSU_SetVoltageCurrent(0, (uint16_t)FAKE_PSU_VOLTAGE_V, (uint16_t)FAKE_PSU_CURRENT_0P1A); 800b1f2: 220a movs r2, #10 800b1f4: f44f 7196 mov.w r1, #300 @ 0x12c 800b1f8: 2000 movs r0, #0 800b1fa: f7ff fec9 bl 800af90 800b1fe: e00b b.n 800b218 }else{ PSU_SetVoltageCurrent(0, CONN.RequestedVoltage, CONN.RequestedCurrent); // Normal mode 800b200: 4b1a ldr r3, [pc, #104] @ (800b26c ) 800b202: f8b3 300f ldrh.w r3, [r3, #15] 800b206: b29b uxth r3, r3 800b208: 4a18 ldr r2, [pc, #96] @ (800b26c ) 800b20a: f8b2 2011 ldrh.w r2, [r2, #17] 800b20e: b292 uxth r2, r2 800b210: 4619 mov r1, r3 800b212: 2000 movs r0, #0 800b214: f7ff febc bl 800af90 } ED_Delay(CAN_DELAY); 800b218: 2014 movs r0, #20 800b21a: f7ff fb67 bl 800a8ec if(CONN.MeasuredVoltage > 490){ 800b21e: 4b13 ldr r3, [pc, #76] @ (800b26c ) 800b220: f8b3 3013 ldrh.w r3, [r3, #19] 800b224: b29b uxth r3, r3 800b226: f5b3 7ff5 cmp.w r3, #490 @ 0x1ea 800b22a: d917 bls.n 800b25c if(PSU0.hv_tick == 0){ 800b22c: 4b11 ldr r3, [pc, #68] @ (800b274 ) 800b22e: 69db ldr r3, [r3, #28] 800b230: 2b00 cmp r3, #0 800b232: d105 bne.n 800b240 PSU0.hv_tick = HAL_GetTick(); 800b234: f003 f84e bl 800e2d4 800b238: 4603 mov r3, r0 800b23a: 4a0e ldr r2, [pc, #56] @ (800b274 ) 800b23c: 61d3 str r3, [r2, #28] }else{ PSU0.hv_tick = 0; } } } 800b23e: e010 b.n 800b262 }else if((HAL_GetTick() - PSU0.hv_tick) >= 10000){ 800b240: f003 f848 bl 800e2d4 800b244: 4602 mov r2, r0 800b246: 4b0b ldr r3, [pc, #44] @ (800b274 ) 800b248: 69db ldr r3, [r3, #28] 800b24a: 1ad3 subs r3, r2, r3 800b24c: f242 720f movw r2, #9999 @ 0x270f 800b250: 4293 cmp r3, r2 800b252: d906 bls.n 800b262 PSU0.hv_mode = 1; 800b254: 4b07 ldr r3, [pc, #28] @ (800b274 ) 800b256: 2201 movs r2, #1 800b258: 761a strb r2, [r3, #24] } 800b25a: e002 b.n 800b262 PSU0.hv_tick = 0; 800b25c: 4b05 ldr r3, [pc, #20] @ (800b274 ) 800b25e: 2200 movs r2, #0 800b260: 61da str r2, [r3, #28] } 800b262: bf00 nop 800b264: 3708 adds r7, #8 800b266: 46bd mov sp, r7 800b268: bd80 pop {r7, pc} 800b26a: bf00 nop 800b26c: 200003b0 .word 0x200003b0 800b270: cccccccd .word 0xcccccccd 800b274: 20000904 .word 0x20000904 800b278: 66666667 .word 0x66666667 0800b27c : void PSU_Task(void){ 800b27c: b598 push {r3, r4, r7, lr} 800b27e: af00 add r7, sp, #0 static uint32_t psu_on_tick = 0; static uint32_t cont_ok_tick = 0; // Обновляем ONLINE/READY по таймауту if((HAL_GetTick() - can_lastpacket) > PSU_ONLINE_TIMEOUT){ 800b280: f003 f828 bl 800e2d4 800b284: 4602 mov r2, r0 800b286: 4bb3 ldr r3, [pc, #716] @ (800b554 ) 800b288: 681b ldr r3, [r3, #0] 800b28a: 1ad3 subs r3, r2, r3 800b28c: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b290: d920 bls.n 800b2d4 PSU0.online = 0; 800b292: 4bb1 ldr r3, [pc, #708] @ (800b558 ) 800b294: 2200 movs r2, #0 800b296: 721a strb r2, [r3, #8] PSU0.PSU_enabled = 0; 800b298: 4baf ldr r3, [pc, #700] @ (800b558 ) 800b29a: 2200 movs r2, #0 800b29c: 729a strb r2, [r3, #10] PSU_04.moduleTemperature = 0; 800b29e: 4baf ldr r3, [pc, #700] @ (800b55c ) 800b2a0: 2200 movs r2, #0 800b2a2: 711a strb r2, [r3, #4] PSU_04.modularForm0 = 0; 800b2a4: 4bad ldr r3, [pc, #692] @ (800b55c ) 800b2a6: 2200 movs r2, #0 800b2a8: 721a strb r2, [r3, #8] PSU_04.modularForm1 = 0; 800b2aa: 4bac ldr r3, [pc, #688] @ (800b55c ) 800b2ac: 2200 movs r2, #0 800b2ae: 71da strb r2, [r3, #7] PSU_04.modularForm2 = 0; 800b2b0: 4baa ldr r3, [pc, #680] @ (800b55c ) 800b2b2: 2200 movs r2, #0 800b2b4: 719a strb r2, [r3, #6] PSU_06.VAB = 0; 800b2b6: 4baa ldr r3, [pc, #680] @ (800b560 ) 800b2b8: 2200 movs r2, #0 800b2ba: 609a str r2, [r3, #8] PSU_06.VBC = 0; 800b2bc: 4ba8 ldr r3, [pc, #672] @ (800b560 ) 800b2be: 2200 movs r2, #0 800b2c0: 60da str r2, [r3, #12] PSU_06.VCA = 0; 800b2c2: 4ba7 ldr r3, [pc, #668] @ (800b560 ) 800b2c4: 2200 movs r2, #0 800b2c6: 611a str r2, [r3, #16] PSU_09.moduleNCurrent = 0; 800b2c8: 4ba6 ldr r3, [pc, #664] @ (800b564 ) 800b2ca: 2200 movs r2, #0 800b2cc: 60da str r2, [r3, #12] PSU_09.moduleNVoltage = 0; 800b2ce: 4ba5 ldr r3, [pc, #660] @ (800b564 ) 800b2d0: 2200 movs r2, #0 800b2d2: 609a str r2, [r3, #8] } if(!PSU0.online || !PSU0.enableAC){ 800b2d4: 4ba0 ldr r3, [pc, #640] @ (800b558 ) 800b2d6: 7a1b ldrb r3, [r3, #8] 800b2d8: 2b00 cmp r3, #0 800b2da: d003 beq.n 800b2e4 800b2dc: 4b9e ldr r3, [pc, #632] @ (800b558 ) 800b2de: 781b ldrb r3, [r3, #0] 800b2e0: 2b00 cmp r3, #0 800b2e2: d10c bne.n 800b2fe CONN.MeasuredVoltage = 0; 800b2e4: 4ba0 ldr r3, [pc, #640] @ (800b568 ) 800b2e6: 2200 movs r2, #0 800b2e8: 74da strb r2, [r3, #19] 800b2ea: 2200 movs r2, #0 800b2ec: 751a strb r2, [r3, #20] CONN.MeasuredCurrent = 0; 800b2ee: 4b9e ldr r3, [pc, #632] @ (800b568 ) 800b2f0: 2200 movs r2, #0 800b2f2: 755a strb r2, [r3, #21] 800b2f4: 2200 movs r2, #0 800b2f6: 759a strb r2, [r3, #22] CONN.outputEnabled = 0; 800b2f8: 4b9b ldr r3, [pc, #620] @ (800b568 ) 800b2fa: 2200 movs r2, #0 800b2fc: 761a strb r2, [r3, #24] } // Управление AC-контактором с задержкой отключения 1 минута if(CONN.EvConnected){ 800b2fe: 4b9a ldr r3, [pc, #616] @ (800b568 ) 800b300: 7f9b ldrb r3, [r3, #30] 800b302: 2b00 cmp r3, #0 800b304: d00c beq.n 800b320 RELAY_Write(RELAY_AC, 1); 800b306: 2101 movs r1, #1 800b308: 2004 movs r0, #4 800b30a: f7fe fa55 bl 80097b8 psu_on_tick = HAL_GetTick(); 800b30e: f002 ffe1 bl 800e2d4 800b312: 4603 mov r3, r0 800b314: 4a95 ldr r2, [pc, #596] @ (800b56c ) 800b316: 6013 str r3, [r2, #0] PSU0.enableAC = 1; 800b318: 4b8f ldr r3, [pc, #572] @ (800b558 ) 800b31a: 2201 movs r2, #1 800b31c: 701a strb r2, [r3, #0] 800b31e: e010 b.n 800b342 }else{ if((HAL_GetTick() - psu_on_tick) > 1 * 60000){ 800b320: f002 ffd8 bl 800e2d4 800b324: 4602 mov r2, r0 800b326: 4b91 ldr r3, [pc, #580] @ (800b56c ) 800b328: 681b ldr r3, [r3, #0] 800b32a: 1ad3 subs r3, r2, r3 800b32c: f64e 2260 movw r2, #60000 @ 0xea60 800b330: 4293 cmp r3, r2 800b332: d906 bls.n 800b342 RELAY_Write(RELAY_AC, 0); 800b334: 2100 movs r1, #0 800b336: 2004 movs r0, #4 800b338: f7fe fa3e bl 80097b8 PSU0.enableAC = 0; 800b33c: 4b86 ldr r3, [pc, #536] @ (800b558 ) 800b33e: 2200 movs r2, #0 800b340: 701a strb r2, [r3, #0] } } // Текущее состояние DC-контактора по обратной связи PSU0.CONT_enabled = IN_ReadInput(IN_CONT_FB_DC); 800b342: 2005 movs r0, #5 800b344: f7fe fab8 bl 80098b8 800b348: 4603 mov r3, r0 800b34a: 461a mov r2, r3 800b34c: 4b82 ldr r3, [pc, #520] @ (800b558 ) 800b34e: 72da strb r2, [r3, #11] // Обновляем ready с учётом ошибок if(PSU0.online && !PSU0.cont_fault && PSU0.enableAC){ 800b350: 4b81 ldr r3, [pc, #516] @ (800b558 ) 800b352: 7a1b ldrb r3, [r3, #8] 800b354: 2b00 cmp r3, #0 800b356: d007 beq.n 800b368 800b358: 4b7f ldr r3, [pc, #508] @ (800b558 ) 800b35a: 7b1b ldrb r3, [r3, #12] 800b35c: 2b00 cmp r3, #0 800b35e: d103 bne.n 800b368 800b360: 4b7d ldr r3, [pc, #500] @ (800b558 ) 800b362: 781b ldrb r3, [r3, #0] 800b364: 2b00 cmp r3, #0 800b366: d102 bne.n 800b36e // PSU0.ready = 1; }else{ PSU0.ready = 0; 800b368: 4b7b ldr r3, [pc, #492] @ (800b558 ) 800b36a: 2200 movs r2, #0 800b36c: 725a strb r2, [r3, #9] } switch(PSU0.state){ 800b36e: 4b7a ldr r3, [pc, #488] @ (800b558 ) 800b370: 79db ldrb r3, [r3, #7] 800b372: 2b09 cmp r3, #9 800b374: f200 8151 bhi.w 800b61a 800b378: a201 add r2, pc, #4 @ (adr r2, 800b380 ) 800b37a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b37e: bf00 nop 800b380: 0800b3a9 .word 0x0800b3a9 800b384: 0800b3dd .word 0x0800b3dd 800b388: 0800b3f9 .word 0x0800b3f9 800b38c: 0800b437 .word 0x0800b437 800b390: 0800b47b .word 0x0800b47b 800b394: 0800b4bd .word 0x0800b4bd 800b398: 0800b527 .word 0x0800b527 800b39c: 0800b5cd .word 0x0800b5cd 800b3a0: 0800b57d .word 0x0800b57d 800b3a4: 0800b607 .word 0x0800b607 case PSU_UNREADY: PSU0.enableOutput = 0; 800b3a8: 4b6b ldr r3, [pc, #428] @ (800b558 ) 800b3aa: 2200 movs r2, #0 800b3ac: 705a strb r2, [r3, #1] RELAY_Write(RELAY_DC, 0); 800b3ae: 2100 movs r1, #0 800b3b0: 2003 movs r0, #3 800b3b2: f7fe fa01 bl 80097b8 if(PSU0.online && PSU0.enableAC && !PSU0.cont_fault){ 800b3b6: 4b68 ldr r3, [pc, #416] @ (800b558 ) 800b3b8: 7a1b ldrb r3, [r3, #8] 800b3ba: 2b00 cmp r3, #0 800b3bc: f000 8131 beq.w 800b622 800b3c0: 4b65 ldr r3, [pc, #404] @ (800b558 ) 800b3c2: 781b ldrb r3, [r3, #0] 800b3c4: 2b00 cmp r3, #0 800b3c6: f000 812c beq.w 800b622 800b3ca: 4b63 ldr r3, [pc, #396] @ (800b558 ) 800b3cc: 7b1b ldrb r3, [r3, #12] 800b3ce: 2b00 cmp r3, #0 800b3d0: f040 8127 bne.w 800b622 PSU_SwitchState(PSU_INITIALIZING); 800b3d4: 2001 movs r0, #1 800b3d6: f7ff fc8f bl 800acf8 } break; 800b3da: e122 b.n 800b622 case PSU_INITIALIZING: if(PSU_StateTime() > 4000){ // Wait 4s for PSU to initialize 800b3dc: f7ff fca0 bl 800ad20 800b3e0: 4603 mov r3, r0 800b3e2: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b3e6: f240 811e bls.w 800b626 PSU0.ready = 1; 800b3ea: 4b5b ldr r3, [pc, #364] @ (800b558 ) 800b3ec: 2201 movs r2, #1 800b3ee: 725a strb r2, [r3, #9] PSU_SwitchState(PSU_READY); 800b3f0: 2002 movs r0, #2 800b3f2: f7ff fc81 bl 800acf8 } break; 800b3f6: e116 b.n 800b626 case PSU_READY: // модуль готов, но выключен PSU0.hv_mode = 0; 800b3f8: 4b57 ldr r3, [pc, #348] @ (800b558 ) 800b3fa: 2200 movs r2, #0 800b3fc: 761a strb r2, [r3, #24] PSU0.hv_tick = 0; 800b3fe: 4b56 ldr r3, [pc, #344] @ (800b558 ) 800b400: 2200 movs r2, #0 800b402: 61da str r2, [r3, #28] RELAY_Write(RELAY_DC, 0); 800b404: 2100 movs r1, #0 800b406: 2003 movs r0, #3 800b408: f7fe f9d6 bl 80097b8 if(!PSU0.ready){ 800b40c: 4b52 ldr r3, [pc, #328] @ (800b558 ) 800b40e: 7a5b ldrb r3, [r3, #9] 800b410: 2b00 cmp r3, #0 800b412: d103 bne.n 800b41c PSU_SwitchState(PSU_UNREADY); 800b414: 2000 movs r0, #0 800b416: f7ff fc6f bl 800acf8 break; 800b41a: e115 b.n 800b648 } if(CONN.EnableOutput){ 800b41c: 4b52 ldr r3, [pc, #328] @ (800b568 ) 800b41e: 7ddb ldrb r3, [r3, #23] 800b420: 2b00 cmp r3, #0 800b422: f000 8102 beq.w 800b62a PSU_Enable(0, 1); 800b426: 2101 movs r1, #1 800b428: 2000 movs r0, #0 800b42a: f7ff fd81 bl 800af30 PSU_SwitchState(PSU_WAIT_ACK_ON); 800b42e: 2003 movs r0, #3 800b430: f7ff fc62 bl 800acf8 } break; 800b434: e0f9 b.n 800b62a case PSU_WAIT_ACK_ON: if(PSU0.PSU_enabled && PSU0.ready){ 800b436: 4b48 ldr r3, [pc, #288] @ (800b558 ) 800b438: 7a9b ldrb r3, [r3, #10] 800b43a: 2b00 cmp r3, #0 800b43c: d007 beq.n 800b44e 800b43e: 4b46 ldr r3, [pc, #280] @ (800b558 ) 800b440: 7a5b ldrb r3, [r3, #9] 800b442: 2b00 cmp r3, #0 800b444: d003 beq.n 800b44e PSU_SwitchState(PSU_CONT_WAIT_ACK_ON); 800b446: 2004 movs r0, #4 800b448: f7ff fc56 bl 800acf8 PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU on timeout\n"); } break; 800b44c: e0ef b.n 800b62e }else if(PSU_StateTime() > 10000){ 800b44e: f7ff fc67 bl 800ad20 800b452: 4603 mov r3, r0 800b454: f242 7210 movw r2, #10000 @ 0x2710 800b458: 4293 cmp r3, r2 800b45a: f240 80e8 bls.w 800b62e PSU0.psu_fault = 1; 800b45e: 4b3e ldr r3, [pc, #248] @ (800b558 ) 800b460: 2201 movs r2, #1 800b462: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b464: 4b40 ldr r3, [pc, #256] @ (800b568 ) 800b466: 220a movs r2, #10 800b468: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b46a: 2000 movs r0, #0 800b46c: f7ff fc44 bl 800acf8 log_printf(LOG_ERR, "PSU on timeout\n"); 800b470: 493f ldr r1, [pc, #252] @ (800b570 ) 800b472: 2004 movs r0, #4 800b474: f7ff f83e bl 800a4f4 break; 800b478: e0d9 b.n 800b62e case PSU_CONT_WAIT_ACK_ON: // замыкаем DC-контактор и ждём подтверждение RELAY_Write(RELAY_DC, 1); 800b47a: 2101 movs r1, #1 800b47c: 2003 movs r0, #3 800b47e: f7fe f99b bl 80097b8 if(PSU0.CONT_enabled){ 800b482: 4b35 ldr r3, [pc, #212] @ (800b558 ) 800b484: 7adb ldrb r3, [r3, #11] 800b486: 2b00 cmp r3, #0 800b488: d003 beq.n 800b492 PSU_SwitchState(PSU_CONNECTED); 800b48a: 2005 movs r0, #5 800b48c: f7ff fc34 bl 800acf8 PSU0.cont_fault = 1; CONN.chargingError = CONN_ERR_CONTACTOR; PSU_SwitchState(PSU_CURRENT_DROP); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b490: e0cf b.n 800b632 }else if(PSU_StateTime() > 1000){ 800b492: f7ff fc45 bl 800ad20 800b496: 4603 mov r3, r0 800b498: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b49c: f240 80c9 bls.w 800b632 PSU0.cont_fault = 1; 800b4a0: 4b2d ldr r3, [pc, #180] @ (800b558 ) 800b4a2: 2201 movs r2, #1 800b4a4: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b4a6: 4b30 ldr r3, [pc, #192] @ (800b568 ) 800b4a8: 2207 movs r2, #7 800b4aa: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_CURRENT_DROP); 800b4ac: 2006 movs r0, #6 800b4ae: f7ff fc23 bl 800acf8 log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b4b2: 4930 ldr r1, [pc, #192] @ (800b574 ) 800b4b4: 2004 movs r0, #4 800b4b6: f7ff f81d bl 800a4f4 break; 800b4ba: e0ba b.n 800b632 case PSU_CONNECTED: // Основное рабочее состояние if(!CONN.EnableOutput || !PSU0.ready){ 800b4bc: 4b2a ldr r3, [pc, #168] @ (800b568 ) 800b4be: 7ddb ldrb r3, [r3, #23] 800b4c0: 2b00 cmp r3, #0 800b4c2: d003 beq.n 800b4cc 800b4c4: 4b24 ldr r3, [pc, #144] @ (800b558 ) 800b4c6: 7a5b ldrb r3, [r3, #9] 800b4c8: 2b00 cmp r3, #0 800b4ca: d103 bne.n 800b4d4 PSU_SwitchState(PSU_CURRENT_DROP); 800b4cc: 2006 movs r0, #6 800b4ce: f7ff fc13 bl 800acf8 break; 800b4d2: e0b9 b.n 800b648 } // контроль контактора: 1 c таймаут if (IN_ReadInput(IN_CONT_FB_DC) != RELAY_Read(RELAY_DC)){ 800b4d4: 2005 movs r0, #5 800b4d6: f7fe f9ef bl 80098b8 800b4da: 4603 mov r3, r0 800b4dc: 461c mov r4, r3 800b4de: 2003 movs r0, #3 800b4e0: f7fe f9da bl 8009898 800b4e4: 4603 mov r3, r0 800b4e6: 429c cmp r4, r3 800b4e8: d017 beq.n 800b51a if((HAL_GetTick() - cont_ok_tick) > 1000){ 800b4ea: f002 fef3 bl 800e2d4 800b4ee: 4602 mov r2, r0 800b4f0: 4b21 ldr r3, [pc, #132] @ (800b578 ) 800b4f2: 681b ldr r3, [r3, #0] 800b4f4: 1ad3 subs r3, r2, r3 800b4f6: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b4fa: f240 809c bls.w 800b636 CONN.chargingError = CONN_ERR_CONTACTOR; 800b4fe: 4b1a ldr r3, [pc, #104] @ (800b568 ) 800b500: 2207 movs r2, #7 800b502: 775a strb r2, [r3, #29] PSU0.cont_fault = 1; 800b504: 4b14 ldr r3, [pc, #80] @ (800b558 ) 800b506: 2201 movs r2, #1 800b508: 731a strb r2, [r3, #12] PSU_SwitchState(PSU_CURRENT_DROP); 800b50a: 2006 movs r0, #6 800b50c: f7ff fbf4 bl 800acf8 log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b510: 4918 ldr r1, [pc, #96] @ (800b574 ) 800b512: 2004 movs r0, #4 800b514: f7fe ffee bl 800a4f4 } }else{ cont_ok_tick = HAL_GetTick(); } break; 800b518: e08d b.n 800b636 cont_ok_tick = HAL_GetTick(); 800b51a: f002 fedb bl 800e2d4 800b51e: 4603 mov r3, r0 800b520: 4a15 ldr r2, [pc, #84] @ (800b578 ) 800b522: 6013 str r3, [r2, #0] break; 800b524: e087 b.n 800b636 case PSU_CURRENT_DROP: // снижаем ток до нуля перед отключением DC CONN.RequestedCurrent = 0; 800b526: 4b10 ldr r3, [pc, #64] @ (800b568 ) 800b528: 2200 movs r2, #0 800b52a: 745a strb r2, [r3, #17] 800b52c: 2200 movs r2, #0 800b52e: 749a strb r2, [r3, #18] // если ток действительно упал или вышло время, отключаем DC if((CONN.MeasuredCurrent < 30) || (PSU_StateTime() > 5000)){ 800b530: 4b0d ldr r3, [pc, #52] @ (800b568 ) 800b532: f8b3 3015 ldrh.w r3, [r3, #21] 800b536: b29b uxth r3, r3 800b538: 2b1d cmp r3, #29 800b53a: d906 bls.n 800b54a 800b53c: f7ff fbf0 bl 800ad20 800b540: 4603 mov r3, r0 800b542: f241 3288 movw r2, #5000 @ 0x1388 800b546: 4293 cmp r3, r2 800b548: d977 bls.n 800b63a PSU_SwitchState(PSU_CONT_WAIT_ACK_OFF); 800b54a: 2008 movs r0, #8 800b54c: f7ff fbd4 bl 800acf8 } break; 800b550: e073 b.n 800b63a 800b552: bf00 nop 800b554: 2000092c .word 0x2000092c 800b558: 20000904 .word 0x20000904 800b55c: 200008cc .word 0x200008cc 800b560: 200008d8 .word 0x200008d8 800b564: 200008f4 .word 0x200008f4 800b568: 200003b0 .word 0x200003b0 800b56c: 20000954 .word 0x20000954 800b570: 080170a4 .word 0x080170a4 800b574: 080170b4 .word 0x080170b4 800b578: 20000958 .word 0x20000958 case PSU_CONT_WAIT_ACK_OFF: RELAY_Write(RELAY_DC, 0); 800b57c: 2100 movs r1, #0 800b57e: 2003 movs r0, #3 800b580: f7fe f91a bl 80097b8 if(!PSU0.CONT_enabled){ 800b584: 4b31 ldr r3, [pc, #196] @ (800b64c ) 800b586: 7adb ldrb r3, [r3, #11] 800b588: 2b00 cmp r3, #0 800b58a: d107 bne.n 800b59c PSU_Enable(0, 0); 800b58c: 2100 movs r1, #0 800b58e: 2000 movs r0, #0 800b590: f7ff fcce bl 800af30 PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b594: 2007 movs r0, #7 800b596: f7ff fbaf bl 800acf8 CONN.chargingError = CONN_ERR_CONTACTOR; PSU_Enable(0, 0); PSU_SwitchState(PSU_WAIT_ACK_OFF); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b59a: e050 b.n 800b63e }else if(PSU_StateTime() > 1000){ 800b59c: f7ff fbc0 bl 800ad20 800b5a0: 4603 mov r3, r0 800b5a2: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b5a6: d94a bls.n 800b63e PSU0.cont_fault = 1; 800b5a8: 4b28 ldr r3, [pc, #160] @ (800b64c ) 800b5aa: 2201 movs r2, #1 800b5ac: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b5ae: 4b28 ldr r3, [pc, #160] @ (800b650 ) 800b5b0: 2207 movs r2, #7 800b5b2: 775a strb r2, [r3, #29] PSU_Enable(0, 0); 800b5b4: 2100 movs r1, #0 800b5b6: 2000 movs r0, #0 800b5b8: f7ff fcba bl 800af30 PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b5bc: 2007 movs r0, #7 800b5be: f7ff fb9b bl 800acf8 log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b5c2: 4924 ldr r1, [pc, #144] @ (800b654 ) 800b5c4: 2004 movs r0, #4 800b5c6: f7fe ff95 bl 800a4f4 break; 800b5ca: e038 b.n 800b63e case PSU_WAIT_ACK_OFF: if(!PSU0.PSU_enabled){ 800b5cc: 4b1f ldr r3, [pc, #124] @ (800b64c ) 800b5ce: 7a9b ldrb r3, [r3, #10] 800b5d0: 2b00 cmp r3, #0 800b5d2: d103 bne.n 800b5dc PSU_SwitchState(PSU_OFF_PAUSE); 800b5d4: 2009 movs r0, #9 800b5d6: f7ff fb8f bl 800acf8 PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU off timeout\n"); } break; 800b5da: e032 b.n 800b642 }else if(PSU_StateTime() > 10000){ 800b5dc: f7ff fba0 bl 800ad20 800b5e0: 4603 mov r3, r0 800b5e2: f242 7210 movw r2, #10000 @ 0x2710 800b5e6: 4293 cmp r3, r2 800b5e8: d92b bls.n 800b642 PSU0.psu_fault = 1; 800b5ea: 4b18 ldr r3, [pc, #96] @ (800b64c ) 800b5ec: 2201 movs r2, #1 800b5ee: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b5f0: 4b17 ldr r3, [pc, #92] @ (800b650 ) 800b5f2: 220a movs r2, #10 800b5f4: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b5f6: 2000 movs r0, #0 800b5f8: f7ff fb7e bl 800acf8 log_printf(LOG_ERR, "PSU off timeout\n"); 800b5fc: 4916 ldr r1, [pc, #88] @ (800b658 ) 800b5fe: 2004 movs r0, #4 800b600: f7fe ff78 bl 800a4f4 break; 800b604: e01d b.n 800b642 case PSU_OFF_PAUSE: if(PSU_StateTime() > 4000){ 800b606: f7ff fb8b bl 800ad20 800b60a: 4603 mov r3, r0 800b60c: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b610: d919 bls.n 800b646 PSU_SwitchState(PSU_READY); 800b612: 2002 movs r0, #2 800b614: f7ff fb70 bl 800acf8 } break; 800b618: e015 b.n 800b646 default: PSU_SwitchState(PSU_UNREADY); 800b61a: 2000 movs r0, #0 800b61c: f7ff fb6c bl 800acf8 break; 800b620: e012 b.n 800b648 break; 800b622: bf00 nop 800b624: e010 b.n 800b648 break; 800b626: bf00 nop 800b628: e00e b.n 800b648 break; 800b62a: bf00 nop 800b62c: e00c b.n 800b648 break; 800b62e: bf00 nop 800b630: e00a b.n 800b648 break; 800b632: bf00 nop 800b634: e008 b.n 800b648 break; 800b636: bf00 nop 800b638: e006 b.n 800b648 break; 800b63a: bf00 nop 800b63c: e004 b.n 800b648 break; 800b63e: bf00 nop 800b640: e002 b.n 800b648 break; 800b642: bf00 nop 800b644: e000 b.n 800b648 break; 800b646: bf00 nop } } 800b648: bf00 nop 800b64a: bd98 pop {r3, r4, r7, pc} 800b64c: 20000904 .word 0x20000904 800b650: 200003b0 .word 0x200003b0 800b654: 080170b4 .word 0x080170b4 800b658: 080170d4 .word 0x080170d4 0800b65c : .Th = 10, .Tf = 50, .Tl = 0, }; void LED_Write(){ 800b65c: b580 push {r7, lr} 800b65e: af00 add r7, sp, #0 if(CONN.chargingError != CONN_NO_ERROR){ 800b660: 4b3c ldr r3, [pc, #240] @ (800b754 ) 800b662: 7f5b ldrb r3, [r3, #29] 800b664: 2b00 cmp r3, #0 800b666: d003 beq.n 800b670 LED_SetColor(&color_error); 800b668: 483b ldr r0, [pc, #236] @ (800b758 ) 800b66a: f000 f933 bl 800b8d4 return; 800b66e: e06f b.n 800b750 } if(CONN.connControl == CMD_FORCE_UNLOCK){ 800b670: 4b38 ldr r3, [pc, #224] @ (800b754 ) 800b672: 781b ldrb r3, [r3, #0] 800b674: 2b03 cmp r3, #3 800b676: d103 bne.n 800b680 LED_SetColor(&color_unlock); 800b678: 4838 ldr r0, [pc, #224] @ (800b75c ) 800b67a: f000 f92b bl 800b8d4 return; 800b67e: e067 b.n 800b750 } if(CONN.connControl == CMD_STOP){ 800b680: 4b34 ldr r3, [pc, #208] @ (800b754 ) 800b682: 781b ldrb r3, [r3, #0] 800b684: 2b01 cmp r3, #1 800b686: d103 bne.n 800b690 LED_SetColor(&color_estop); 800b688: 4835 ldr r0, [pc, #212] @ (800b760 ) 800b68a: f000 f923 bl 800b8d4 return; 800b68e: e05f b.n 800b750 } switch(CONN.connState){ 800b690: 4b30 ldr r3, [pc, #192] @ (800b754 ) 800b692: 785b ldrb r3, [r3, #1] 800b694: 2b0d cmp r3, #13 800b696: d857 bhi.n 800b748 800b698: a201 add r2, pc, #4 @ (adr r2, 800b6a0 ) 800b69a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b69e: bf00 nop 800b6a0: 0800b6d9 .word 0x0800b6d9 800b6a4: 0800b6e1 .word 0x0800b6e1 800b6a8: 0800b6e9 .word 0x0800b6e9 800b6ac: 0800b6f1 .word 0x0800b6f1 800b6b0: 0800b6f9 .word 0x0800b6f9 800b6b4: 0800b701 .word 0x0800b701 800b6b8: 0800b709 .word 0x0800b709 800b6bc: 0800b711 .word 0x0800b711 800b6c0: 0800b719 .word 0x0800b719 800b6c4: 0800b721 .word 0x0800b721 800b6c8: 0800b729 .word 0x0800b729 800b6cc: 0800b731 .word 0x0800b731 800b6d0: 0800b739 .word 0x0800b739 800b6d4: 0800b741 .word 0x0800b741 case Unknown: LED_SetColor(&color_unknown); 800b6d8: 4822 ldr r0, [pc, #136] @ (800b764 ) 800b6da: f000 f8fb bl 800b8d4 break; 800b6de: e037 b.n 800b750 case Unplugged: LED_SetColor(&color_unplugged); 800b6e0: 4821 ldr r0, [pc, #132] @ (800b768 ) 800b6e2: f000 f8f7 bl 800b8d4 break; 800b6e6: e033 b.n 800b750 case Disabled: LED_SetColor(&color_error); 800b6e8: 481b ldr r0, [pc, #108] @ (800b758 ) 800b6ea: f000 f8f3 bl 800b8d4 break; 800b6ee: e02f b.n 800b750 case Preparing: LED_SetColor(&color_preparing); 800b6f0: 481e ldr r0, [pc, #120] @ (800b76c ) 800b6f2: f000 f8ef bl 800b8d4 break; 800b6f6: e02b b.n 800b750 case AuthRequired: LED_SetColor(&color_preparing); 800b6f8: 481c ldr r0, [pc, #112] @ (800b76c ) 800b6fa: f000 f8eb bl 800b8d4 break; 800b6fe: e027 b.n 800b750 case WaitingForEnergy: LED_SetColor(&color_charging); 800b700: 481b ldr r0, [pc, #108] @ (800b770 ) 800b702: f000 f8e7 bl 800b8d4 break; 800b706: e023 b.n 800b750 case ChargingPausedEV: LED_SetColor(&color_charging); 800b708: 4819 ldr r0, [pc, #100] @ (800b770 ) 800b70a: f000 f8e3 bl 800b8d4 break; 800b70e: e01f b.n 800b750 case ChargingPausedEVSE: LED_SetColor(&color_charging); 800b710: 4817 ldr r0, [pc, #92] @ (800b770 ) 800b712: f000 f8df bl 800b8d4 break; 800b716: e01b b.n 800b750 case Charging: LED_SetColor(&color_charging); 800b718: 4815 ldr r0, [pc, #84] @ (800b770 ) 800b71a: f000 f8db bl 800b8d4 break; 800b71e: e017 b.n 800b750 case AuthTimeout: LED_SetColor(&color_finished); 800b720: 4814 ldr r0, [pc, #80] @ (800b774 ) 800b722: f000 f8d7 bl 800b8d4 break; 800b726: e013 b.n 800b750 case Finished: LED_SetColor(&color_finished); 800b728: 4812 ldr r0, [pc, #72] @ (800b774 ) 800b72a: f000 f8d3 bl 800b8d4 break; 800b72e: e00f b.n 800b750 case FinishedEVSE: LED_SetColor(&color_finished); 800b730: 4810 ldr r0, [pc, #64] @ (800b774 ) 800b732: f000 f8cf bl 800b8d4 break; 800b736: e00b b.n 800b750 case FinishedEV: LED_SetColor(&color_finished); 800b738: 480e ldr r0, [pc, #56] @ (800b774 ) 800b73a: f000 f8cb bl 800b8d4 break; 800b73e: e007 b.n 800b750 case Replugging: LED_SetColor(&color_preparing); 800b740: 480a ldr r0, [pc, #40] @ (800b76c ) 800b742: f000 f8c7 bl 800b8d4 break; 800b746: e003 b.n 800b750 default: LED_SetColor(&color_unknown); 800b748: 4806 ldr r0, [pc, #24] @ (800b764 ) 800b74a: f000 f8c3 bl 800b8d4 break; 800b74e: bf00 nop } } 800b750: bd80 pop {r7, pc} 800b752: bf00 nop 800b754: 200003b0 .word 0x200003b0 800b758: 20000060 .word 0x20000060 800b75c: 20000018 .word 0x20000018 800b760: 2000000c .word 0x2000000c 800b764: 20000024 .word 0x20000024 800b768: 20000030 .word 0x20000030 800b76c: 2000003c .word 0x2000003c 800b770: 20000048 .word 0x20000048 800b774: 20000054 .word 0x20000054 0800b778 : void interpolateColors(RGB_t* color1, RGB_t* color2, uint16_t a, uint16_t b, RGB_t *result) { 800b778: b480 push {r7} 800b77a: b087 sub sp, #28 800b77c: af00 add r7, sp, #0 800b77e: 60f8 str r0, [r7, #12] 800b780: 60b9 str r1, [r7, #8] 800b782: 4611 mov r1, r2 800b784: 461a mov r2, r3 800b786: 460b mov r3, r1 800b788: 80fb strh r3, [r7, #6] 800b78a: 4613 mov r3, r2 800b78c: 80bb strh r3, [r7, #4] // Проверяем, чтобы a не выходила за пределы диапазона if (a > b) a = b; 800b78e: 88fa ldrh r2, [r7, #6] 800b790: 88bb ldrh r3, [r7, #4] 800b792: 429a cmp r2, r3 800b794: d901 bls.n 800b79a 800b796: 88bb ldrh r3, [r7, #4] 800b798: 80fb strh r3, [r7, #6] if(b==0) b = 1; 800b79a: 88bb ldrh r3, [r7, #4] 800b79c: 2b00 cmp r3, #0 800b79e: d101 bne.n 800b7a4 800b7a0: 2301 movs r3, #1 800b7a2: 80bb strh r3, [r7, #4] // Вычисляем коэффициент смешивания в виде целого числа uint16_t t = (a * 255) / b; // t будет от 0 до 255 800b7a4: 88fa ldrh r2, [r7, #6] 800b7a6: 4613 mov r3, r2 800b7a8: 021b lsls r3, r3, #8 800b7aa: 1a9a subs r2, r3, r2 800b7ac: 88bb ldrh r3, [r7, #4] 800b7ae: fb92 f3f3 sdiv r3, r2, r3 800b7b2: 82fb strh r3, [r7, #22] // Линейная интерполяция с использованием целых чисел result->R = (color1->R * (255 - t) + color2->R * t) / 255; 800b7b4: 68fb ldr r3, [r7, #12] 800b7b6: 781b ldrb r3, [r3, #0] 800b7b8: 461a mov r2, r3 800b7ba: 8afb ldrh r3, [r7, #22] 800b7bc: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b7c0: fb03 f202 mul.w r2, r3, r2 800b7c4: 68bb ldr r3, [r7, #8] 800b7c6: 781b ldrb r3, [r3, #0] 800b7c8: 4619 mov r1, r3 800b7ca: 8afb ldrh r3, [r7, #22] 800b7cc: fb01 f303 mul.w r3, r1, r3 800b7d0: 4413 add r3, r2 800b7d2: 4a20 ldr r2, [pc, #128] @ (800b854 ) 800b7d4: fb82 1203 smull r1, r2, r2, r3 800b7d8: 441a add r2, r3 800b7da: 11d2 asrs r2, r2, #7 800b7dc: 17db asrs r3, r3, #31 800b7de: 1ad3 subs r3, r2, r3 800b7e0: b2da uxtb r2, r3 800b7e2: 6a3b ldr r3, [r7, #32] 800b7e4: 701a strb r2, [r3, #0] result->G = (color1->G * (255 - t) + color2->G * t) / 255; 800b7e6: 68fb ldr r3, [r7, #12] 800b7e8: 785b ldrb r3, [r3, #1] 800b7ea: 461a mov r2, r3 800b7ec: 8afb ldrh r3, [r7, #22] 800b7ee: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b7f2: fb03 f202 mul.w r2, r3, r2 800b7f6: 68bb ldr r3, [r7, #8] 800b7f8: 785b ldrb r3, [r3, #1] 800b7fa: 4619 mov r1, r3 800b7fc: 8afb ldrh r3, [r7, #22] 800b7fe: fb01 f303 mul.w r3, r1, r3 800b802: 4413 add r3, r2 800b804: 4a13 ldr r2, [pc, #76] @ (800b854 ) 800b806: fb82 1203 smull r1, r2, r2, r3 800b80a: 441a add r2, r3 800b80c: 11d2 asrs r2, r2, #7 800b80e: 17db asrs r3, r3, #31 800b810: 1ad3 subs r3, r2, r3 800b812: b2da uxtb r2, r3 800b814: 6a3b ldr r3, [r7, #32] 800b816: 705a strb r2, [r3, #1] result->B = (color1->B * (255 - t) + color2->B * t) / 255; 800b818: 68fb ldr r3, [r7, #12] 800b81a: 789b ldrb r3, [r3, #2] 800b81c: 461a mov r2, r3 800b81e: 8afb ldrh r3, [r7, #22] 800b820: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b824: fb03 f202 mul.w r2, r3, r2 800b828: 68bb ldr r3, [r7, #8] 800b82a: 789b ldrb r3, [r3, #2] 800b82c: 4619 mov r1, r3 800b82e: 8afb ldrh r3, [r7, #22] 800b830: fb01 f303 mul.w r3, r1, r3 800b834: 4413 add r3, r2 800b836: 4a07 ldr r2, [pc, #28] @ (800b854 ) 800b838: fb82 1203 smull r1, r2, r2, r3 800b83c: 441a add r2, r3 800b83e: 11d2 asrs r2, r2, #7 800b840: 17db asrs r3, r3, #31 800b842: 1ad3 subs r3, r2, r3 800b844: b2da uxtb r2, r3 800b846: 6a3b ldr r3, [r7, #32] 800b848: 709a strb r2, [r3, #2] } 800b84a: bf00 nop 800b84c: 371c adds r7, #28 800b84e: 46bd mov sp, r7 800b850: bc80 pop {r7} 800b852: 4770 bx lr 800b854: 80808081 .word 0x80808081 0800b858 : void RGB_SetColor(RGB_t *color){ 800b858: b480 push {r7} 800b85a: b083 sub sp, #12 800b85c: af00 add r7, sp, #0 800b85e: 6078 str r0, [r7, #4] htim4.Instance->CCR2 = color->R * 100 / 255; 800b860: 687b ldr r3, [r7, #4] 800b862: 781b ldrb r3, [r3, #0] 800b864: 461a mov r2, r3 800b866: 2364 movs r3, #100 @ 0x64 800b868: fb02 f303 mul.w r3, r2, r3 800b86c: 4a17 ldr r2, [pc, #92] @ (800b8cc ) 800b86e: fb82 1203 smull r1, r2, r2, r3 800b872: 441a add r2, r3 800b874: 11d2 asrs r2, r2, #7 800b876: 17db asrs r3, r3, #31 800b878: 1ad2 subs r2, r2, r3 800b87a: 4b15 ldr r3, [pc, #84] @ (800b8d0 ) 800b87c: 681b ldr r3, [r3, #0] 800b87e: 639a str r2, [r3, #56] @ 0x38 htim4.Instance->CCR3 = color->G * 100 / 255; 800b880: 687b ldr r3, [r7, #4] 800b882: 785b ldrb r3, [r3, #1] 800b884: 461a mov r2, r3 800b886: 2364 movs r3, #100 @ 0x64 800b888: fb02 f303 mul.w r3, r2, r3 800b88c: 4a0f ldr r2, [pc, #60] @ (800b8cc ) 800b88e: fb82 1203 smull r1, r2, r2, r3 800b892: 441a add r2, r3 800b894: 11d2 asrs r2, r2, #7 800b896: 17db asrs r3, r3, #31 800b898: 1ad2 subs r2, r2, r3 800b89a: 4b0d ldr r3, [pc, #52] @ (800b8d0 ) 800b89c: 681b ldr r3, [r3, #0] 800b89e: 63da str r2, [r3, #60] @ 0x3c htim4.Instance->CCR4 = color->B * 100 / 255; 800b8a0: 687b ldr r3, [r7, #4] 800b8a2: 789b ldrb r3, [r3, #2] 800b8a4: 461a mov r2, r3 800b8a6: 2364 movs r3, #100 @ 0x64 800b8a8: fb02 f303 mul.w r3, r2, r3 800b8ac: 4a07 ldr r2, [pc, #28] @ (800b8cc ) 800b8ae: fb82 1203 smull r1, r2, r2, r3 800b8b2: 441a add r2, r3 800b8b4: 11d2 asrs r2, r2, #7 800b8b6: 17db asrs r3, r3, #31 800b8b8: 1ad2 subs r2, r2, r3 800b8ba: 4b05 ldr r3, [pc, #20] @ (800b8d0 ) 800b8bc: 681b ldr r3, [r3, #0] 800b8be: 641a str r2, [r3, #64] @ 0x40 } 800b8c0: bf00 nop 800b8c2: 370c adds r7, #12 800b8c4: 46bd mov sp, r7 800b8c6: bc80 pop {r7} 800b8c8: 4770 bx lr 800b8ca: bf00 nop 800b8cc: 80808081 .word 0x80808081 800b8d0: 20001210 .word 0x20001210 0800b8d4 : void LED_SetColor(RGB_Cycle_t *color){ 800b8d4: b480 push {r7} 800b8d6: b083 sub sp, #12 800b8d8: af00 add r7, sp, #0 800b8da: 6078 str r0, [r7, #4] memcpy(&LED_Cycle, color, sizeof(RGB_Cycle_t)); 800b8dc: 4b05 ldr r3, [pc, #20] @ (800b8f4 ) 800b8de: 687a ldr r2, [r7, #4] 800b8e0: 6810 ldr r0, [r2, #0] 800b8e2: 6851 ldr r1, [r2, #4] 800b8e4: c303 stmia r3!, {r0, r1} 800b8e6: 8912 ldrh r2, [r2, #8] 800b8e8: 801a strh r2, [r3, #0] } 800b8ea: bf00 nop 800b8ec: 370c adds r7, #12 800b8ee: 46bd mov sp, r7 800b8f0: bc80 pop {r7} 800b8f2: 4770 bx lr 800b8f4: 20000964 .word 0x20000964 0800b8f8 : void LED_Init(){ 800b8f8: b580 push {r7, lr} 800b8fa: b082 sub sp, #8 800b8fc: af00 add r7, sp, #0 RGB_t color = {.R=0, .G=0, .B=0}; 800b8fe: 2300 movs r3, #0 800b900: 713b strb r3, [r7, #4] 800b902: 2300 movs r3, #0 800b904: 717b strb r3, [r7, #5] 800b906: 2300 movs r3, #0 800b908: 71bb strb r3, [r7, #6] HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_2); 800b90a: 2104 movs r1, #4 800b90c: 4809 ldr r0, [pc, #36] @ (800b934 ) 800b90e: f006 fbaf bl 8012070 HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); 800b912: 2108 movs r1, #8 800b914: 4807 ldr r0, [pc, #28] @ (800b934 ) 800b916: f006 fbab bl 8012070 HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4); 800b91a: 210c movs r1, #12 800b91c: 4805 ldr r0, [pc, #20] @ (800b934 ) 800b91e: f006 fba7 bl 8012070 RGB_SetColor(&color); 800b922: 1d3b adds r3, r7, #4 800b924: 4618 mov r0, r3 800b926: f7ff ff97 bl 800b858 } 800b92a: bf00 nop 800b92c: 3708 adds r7, #8 800b92e: 46bd mov sp, r7 800b930: bd80 pop {r7, pc} 800b932: bf00 nop 800b934: 20001210 .word 0x20001210 0800b938 : void LED_Task(){ 800b938: b580 push {r7, lr} 800b93a: b082 sub sp, #8 800b93c: af02 add r7, sp, #8 static uint32_t led_tick; if((HAL_GetTick() - led_tick) > 20){ 800b93e: f002 fcc9 bl 800e2d4 800b942: 4602 mov r2, r0 800b944: 4b46 ldr r3, [pc, #280] @ (800ba60 ) 800b946: 681b ldr r3, [r3, #0] 800b948: 1ad3 subs r3, r2, r3 800b94a: 2b14 cmp r3, #20 800b94c: f240 8085 bls.w 800ba5a led_tick = HAL_GetTick(); 800b950: f002 fcc0 bl 800e2d4 800b954: 4603 mov r3, r0 800b956: 4a42 ldr r2, [pc, #264] @ (800ba60 ) 800b958: 6013 str r3, [r2, #0] LED_State.tick++; 800b95a: 4b42 ldr r3, [pc, #264] @ (800ba64 ) 800b95c: 885b ldrh r3, [r3, #2] 800b95e: 3301 adds r3, #1 800b960: b29a uxth r2, r3 800b962: 4b40 ldr r3, [pc, #256] @ (800ba64 ) 800b964: 805a strh r2, [r3, #2] switch(LED_State.state){ 800b966: 4b3f ldr r3, [pc, #252] @ (800ba64 ) 800b968: 781b ldrb r3, [r3, #0] 800b96a: 2b03 cmp r3, #3 800b96c: d867 bhi.n 800ba3e 800b96e: a201 add r2, pc, #4 @ (adr r2, 800b974 ) 800b970: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b974: 0800b985 .word 0x0800b985 800b978: 0800b9b7 .word 0x0800b9b7 800b97c: 0800b9e3 .word 0x0800b9e3 800b980: 0800ba15 .word 0x0800ba15 case LED_RISING: interpolateColors(&LED_Cycle.Color2, &LED_Cycle.Color1, LED_State.tick, LED_Cycle.Tr, &LED_State.color); 800b984: 4b37 ldr r3, [pc, #220] @ (800ba64 ) 800b986: 885a ldrh r2, [r3, #2] 800b988: 4b37 ldr r3, [pc, #220] @ (800ba68 ) 800b98a: 78db ldrb r3, [r3, #3] 800b98c: 4619 mov r1, r3 800b98e: 4b37 ldr r3, [pc, #220] @ (800ba6c ) 800b990: 9300 str r3, [sp, #0] 800b992: 460b mov r3, r1 800b994: 4934 ldr r1, [pc, #208] @ (800ba68 ) 800b996: 4836 ldr r0, [pc, #216] @ (800ba70 ) 800b998: f7ff feee bl 800b778 if(LED_State.tick>LED_Cycle.Tr){ 800b99c: 4b31 ldr r3, [pc, #196] @ (800ba64 ) 800b99e: 885b ldrh r3, [r3, #2] 800b9a0: 4a31 ldr r2, [pc, #196] @ (800ba68 ) 800b9a2: 78d2 ldrb r2, [r2, #3] 800b9a4: 4293 cmp r3, r2 800b9a6: d94e bls.n 800ba46 LED_State.state = LED_HIGH; 800b9a8: 4b2e ldr r3, [pc, #184] @ (800ba64 ) 800b9aa: 2201 movs r2, #1 800b9ac: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b9ae: 4b2d ldr r3, [pc, #180] @ (800ba64 ) 800b9b0: 2200 movs r2, #0 800b9b2: 805a strh r2, [r3, #2] } break; 800b9b4: e047 b.n 800ba46 case LED_HIGH: memcpy(&LED_State.color, &LED_Cycle.Color1, sizeof(RGB_t)); 800b9b6: 4b2b ldr r3, [pc, #172] @ (800ba64 ) 800b9b8: 4a2b ldr r2, [pc, #172] @ (800ba68 ) 800b9ba: 3304 adds r3, #4 800b9bc: 6812 ldr r2, [r2, #0] 800b9be: 4611 mov r1, r2 800b9c0: 8019 strh r1, [r3, #0] 800b9c2: 3302 adds r3, #2 800b9c4: 0c12 lsrs r2, r2, #16 800b9c6: 701a strb r2, [r3, #0] if(LED_State.tick>LED_Cycle.Th){ 800b9c8: 4b26 ldr r3, [pc, #152] @ (800ba64 ) 800b9ca: 885b ldrh r3, [r3, #2] 800b9cc: 4a26 ldr r2, [pc, #152] @ (800ba68 ) 800b9ce: 7912 ldrb r2, [r2, #4] 800b9d0: 4293 cmp r3, r2 800b9d2: d93a bls.n 800ba4a LED_State.state = LED_FALLING; 800b9d4: 4b23 ldr r3, [pc, #140] @ (800ba64 ) 800b9d6: 2202 movs r2, #2 800b9d8: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b9da: 4b22 ldr r3, [pc, #136] @ (800ba64 ) 800b9dc: 2200 movs r2, #0 800b9de: 805a strh r2, [r3, #2] } break; 800b9e0: e033 b.n 800ba4a case LED_FALLING: interpolateColors(&LED_Cycle.Color1, &LED_Cycle.Color2, LED_State.tick, LED_Cycle.Tf, &LED_State.color); 800b9e2: 4b20 ldr r3, [pc, #128] @ (800ba64 ) 800b9e4: 885a ldrh r2, [r3, #2] 800b9e6: 4b20 ldr r3, [pc, #128] @ (800ba68 ) 800b9e8: 795b ldrb r3, [r3, #5] 800b9ea: 4619 mov r1, r3 800b9ec: 4b1f ldr r3, [pc, #124] @ (800ba6c ) 800b9ee: 9300 str r3, [sp, #0] 800b9f0: 460b mov r3, r1 800b9f2: 491f ldr r1, [pc, #124] @ (800ba70 ) 800b9f4: 481c ldr r0, [pc, #112] @ (800ba68 ) 800b9f6: f7ff febf bl 800b778 if(LED_State.tick>LED_Cycle.Tf){ 800b9fa: 4b1a ldr r3, [pc, #104] @ (800ba64 ) 800b9fc: 885b ldrh r3, [r3, #2] 800b9fe: 4a1a ldr r2, [pc, #104] @ (800ba68 ) 800ba00: 7952 ldrb r2, [r2, #5] 800ba02: 4293 cmp r3, r2 800ba04: d923 bls.n 800ba4e LED_State.state = LED_LOW; 800ba06: 4b17 ldr r3, [pc, #92] @ (800ba64 ) 800ba08: 2203 movs r2, #3 800ba0a: 701a strb r2, [r3, #0] LED_State.tick = 0; 800ba0c: 4b15 ldr r3, [pc, #84] @ (800ba64 ) 800ba0e: 2200 movs r2, #0 800ba10: 805a strh r2, [r3, #2] } break; 800ba12: e01c b.n 800ba4e case LED_LOW: memcpy(&LED_State.color, &LED_Cycle.Color2, sizeof(RGB_t)); 800ba14: 4b13 ldr r3, [pc, #76] @ (800ba64 ) 800ba16: 4a14 ldr r2, [pc, #80] @ (800ba68 ) 800ba18: 3304 adds r3, #4 800ba1a: 3207 adds r2, #7 800ba1c: 8811 ldrh r1, [r2, #0] 800ba1e: 7892 ldrb r2, [r2, #2] 800ba20: 8019 strh r1, [r3, #0] 800ba22: 709a strb r2, [r3, #2] if(LED_State.tick>LED_Cycle.Tl){ 800ba24: 4b0f ldr r3, [pc, #60] @ (800ba64 ) 800ba26: 885b ldrh r3, [r3, #2] 800ba28: 4a0f ldr r2, [pc, #60] @ (800ba68 ) 800ba2a: 7992 ldrb r2, [r2, #6] 800ba2c: 4293 cmp r3, r2 800ba2e: d910 bls.n 800ba52 LED_State.state = LED_RISING; 800ba30: 4b0c ldr r3, [pc, #48] @ (800ba64 ) 800ba32: 2200 movs r2, #0 800ba34: 701a strb r2, [r3, #0] LED_State.tick = 0; 800ba36: 4b0b ldr r3, [pc, #44] @ (800ba64 ) 800ba38: 2200 movs r2, #0 800ba3a: 805a strh r2, [r3, #2] } break; 800ba3c: e009 b.n 800ba52 default: LED_State.state = LED_RISING; 800ba3e: 4b09 ldr r3, [pc, #36] @ (800ba64 ) 800ba40: 2200 movs r2, #0 800ba42: 701a strb r2, [r3, #0] 800ba44: e006 b.n 800ba54 break; 800ba46: bf00 nop 800ba48: e004 b.n 800ba54 break; 800ba4a: bf00 nop 800ba4c: e002 b.n 800ba54 break; 800ba4e: bf00 nop 800ba50: e000 b.n 800ba54 break; 800ba52: bf00 nop } RGB_SetColor(&LED_State.color); 800ba54: 4805 ldr r0, [pc, #20] @ (800ba6c ) 800ba56: f7ff feff bl 800b858 } } 800ba5a: bf00 nop 800ba5c: 46bd mov sp, r7 800ba5e: bd80 pop {r7, pc} 800ba60: 20000970 .word 0x20000970 800ba64: 2000095c .word 0x2000095c 800ba68: 20000964 .word 0x20000964 800ba6c: 20000960 .word 0x20000960 800ba70: 2000096b .word 0x2000096b 0800ba74 : RTC_HandleTypeDef hrtc; /* RTC init function */ void MX_RTC_Init(void) { 800ba74: b580 push {r7, lr} 800ba76: af00 add r7, sp, #0 /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 800ba78: 4b0a ldr r3, [pc, #40] @ (800baa4 ) 800ba7a: 4a0b ldr r2, [pc, #44] @ (800baa8 ) 800ba7c: 601a str r2, [r3, #0] hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; 800ba7e: 4b09 ldr r3, [pc, #36] @ (800baa4 ) 800ba80: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800ba84: 605a str r2, [r3, #4] hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; 800ba86: 4b07 ldr r3, [pc, #28] @ (800baa4 ) 800ba88: f44f 7280 mov.w r2, #256 @ 0x100 800ba8c: 609a str r2, [r3, #8] if (HAL_RTC_Init(&hrtc) != HAL_OK) 800ba8e: 4805 ldr r0, [pc, #20] @ (800baa4 ) 800ba90: f006 f83c bl 8011b0c 800ba94: 4603 mov r3, r0 800ba96: 2b00 cmp r3, #0 800ba98: d001 beq.n 800ba9e { Error_Handler(); 800ba9a: f7ff f8c1 bl 800ac20 } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 800ba9e: bf00 nop 800baa0: bd80 pop {r7, pc} 800baa2: bf00 nop 800baa4: 20000974 .word 0x20000974 800baa8: 40002800 .word 0x40002800 0800baac : void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) { 800baac: b580 push {r7, lr} 800baae: b084 sub sp, #16 800bab0: af00 add r7, sp, #0 800bab2: 6078 str r0, [r7, #4] if(rtcHandle->Instance==RTC) 800bab4: 687b ldr r3, [r7, #4] 800bab6: 681b ldr r3, [r3, #0] 800bab8: 4a0b ldr r2, [pc, #44] @ (800bae8 ) 800baba: 4293 cmp r3, r2 800babc: d110 bne.n 800bae0 { /* USER CODE BEGIN RTC_MspInit 0 */ /* USER CODE END RTC_MspInit 0 */ HAL_PWR_EnableBkUpAccess(); 800babe: f004 ffb9 bl 8010a34 /* Enable BKP CLK enable for backup registers */ __HAL_RCC_BKP_CLK_ENABLE(); 800bac2: 4b0a ldr r3, [pc, #40] @ (800baec ) 800bac4: 69db ldr r3, [r3, #28] 800bac6: 4a09 ldr r2, [pc, #36] @ (800baec ) 800bac8: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800bacc: 61d3 str r3, [r2, #28] 800bace: 4b07 ldr r3, [pc, #28] @ (800baec ) 800bad0: 69db ldr r3, [r3, #28] 800bad2: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800bad6: 60fb str r3, [r7, #12] 800bad8: 68fb ldr r3, [r7, #12] /* RTC clock enable */ __HAL_RCC_RTC_ENABLE(); 800bada: 4b05 ldr r3, [pc, #20] @ (800baf0 ) 800badc: 2201 movs r2, #1 800bade: 601a str r2, [r3, #0] /* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE END RTC_MspInit 1 */ } } 800bae0: bf00 nop 800bae2: 3710 adds r7, #16 800bae4: 46bd mov sp, r7 800bae6: bd80 pop {r7, pc} 800bae8: 40002800 .word 0x40002800 800baec: 40021000 .word 0x40021000 800baf0: 4242043c .word 0x4242043c 0800baf4 : ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len); static void CCS_UART3_Watchdog(void); static void CCS_LogUart3Error(const char *tag); ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800baf4: 4602 mov r2, r0 if (err == HAL_UART_ERROR_NONE) { 800baf6: b359 cbz r1, 800bb50 ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800baf8: b570 push {r4, r5, r6, lr} 800bafa: 460c mov r4, r1 log_printf(LOG_ERR, "UART%u HAL error decode: NONE\n", uart_num); return; } log_printf(LOG_ERR, "UART%u HAL error decode: %s%s%s%s%s%s raw=0x%08lx\n", 800bafc: 07cb lsls r3, r1, #31 800bafe: bf58 it pl 800bb00: 4915 ldrpl r1, [pc, #84] @ (800bb58 ) 800bb02: 4d15 ldr r5, [pc, #84] @ (800bb58 ) 800bb04: bf48 it mi 800bb06: 4914 ldrmi r1, [pc, #80] @ (800bb58 ) ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800bb08: b086 sub sp, #24 log_printf(LOG_ERR, "UART%u HAL error decode: %s%s%s%s%s%s raw=0x%08lx\n", 800bb0a: bf54 ite pl 800bb0c: 460b movpl r3, r1 800bb0e: 4b13 ldrmi r3, [pc, #76] @ (800bb5c ) 800bb10: f014 0f02 tst.w r4, #2 800bb14: 9104 str r1, [sp, #16] 800bb16: 4912 ldr r1, [pc, #72] @ (800bb60 ) 800bb18: bf08 it eq 800bb1a: 4629 moveq r1, r5 800bb1c: f014 0f04 tst.w r4, #4 800bb20: 4810 ldr r0, [pc, #64] @ (800bb64 ) 800bb22: bf08 it eq 800bb24: 4628 moveq r0, r5 800bb26: f014 0f08 tst.w r4, #8 800bb2a: 9001 str r0, [sp, #4] 800bb2c: 480e ldr r0, [pc, #56] @ (800bb68 ) 800bb2e: 4e0f ldr r6, [pc, #60] @ (800bb6c ) 800bb30: bf08 it eq 800bb32: 462e moveq r6, r5 800bb34: f014 0f10 tst.w r4, #16 800bb38: bf18 it ne 800bb3a: 4605 movne r5, r0 800bb3c: 9100 str r1, [sp, #0] 800bb3e: e9cd 6502 strd r6, r5, [sp, #8] 800bb42: 490b ldr r1, [pc, #44] @ (800bb70 ) 800bb44: 9405 str r4, [sp, #20] 800bb46: 2004 movs r0, #4 800bb48: f7fe fcd4 bl 800a4f4 (err & HAL_UART_ERROR_INVALID_CALLBACK) ? "INV_CB " : "", #else "", #endif (unsigned long)err); } 800bb4c: b006 add sp, #24 800bb4e: bd70 pop {r4, r5, r6, pc} log_printf(LOG_ERR, "UART%u HAL error decode: NONE\n", uart_num); 800bb50: 2004 movs r0, #4 800bb52: 4908 ldr r1, [pc, #32] @ (800bb74 ) 800bb54: f7fe bcce b.w 800a4f4 800bb58: 080174e0 .word 0x080174e0 800bb5c: 080170e8 .word 0x080170e8 800bb60: 080170ec .word 0x080170ec 800bb64: 080170f0 .word 0x080170f0 800bb68: 080170fc .word 0x080170fc 800bb6c: 080170f4 .word 0x080170f4 800bb70: 08017124 .word 0x08017124 800bb74: 08017104 .word 0x08017104 0800bb78 : ISR_FAST static void uart3_arm_rx_or_log(const char *where) { 800bb78: b530 push {r4, r5, lr} HAL_StatusTypeDef st = HAL_UARTEx_ReceiveToIdle_DMA(&huart3, rx_buffer, sizeof(rx_buffer)); 800bb7a: f44f 7280 mov.w r2, #256 @ 0x100 ISR_FAST static void uart3_arm_rx_or_log(const char *where) { 800bb7e: 4605 mov r5, r0 800bb80: b083 sub sp, #12 HAL_StatusTypeDef st = HAL_UARTEx_ReceiveToIdle_DMA(&huart3, rx_buffer, sizeof(rx_buffer)); 800bb82: 4911 ldr r1, [pc, #68] @ (800bbc8 ) 800bb84: 4811 ldr r0, [pc, #68] @ (800bbcc ) 800bb86: f007 fa6e bl 8013066 if (st == HAL_OK) { 800bb8a: b908 cbnz r0, 800bb90 uart3_log_hal_error(3u, err_after); CCS_LogUart3Error("UART3 RX arm failed details"); if (err_after != HAL_UART_ERROR_NONE) { (void)HAL_UART_AbortReceive(&huart3); } } 800bb8c: b003 add sp, #12 800bb8e: bd30 pop {r4, r5, pc} uint32_t err_after = HAL_UART_GetError(&huart3); 800bb90: 4604 mov r4, r0 800bb92: 480e ldr r0, [pc, #56] @ (800bbcc ) 800bb94: f007 fe79 bl 801388a 800bb98: 4602 mov r2, r0 log_printf(LOG_ERR, 800bb9a: 4623 mov r3, r4 uint32_t err_after = HAL_UART_GetError(&huart3); 800bb9c: 4614 mov r4, r2 log_printf(LOG_ERR, 800bb9e: 490c ldr r1, [pc, #48] @ (800bbd0 ) 800bba0: 462a mov r2, r5 800bba2: 2004 movs r0, #4 800bba4: 9400 str r4, [sp, #0] 800bba6: f7fe fca5 bl 800a4f4 uart3_log_hal_error(3u, err_after); 800bbaa: 2003 movs r0, #3 800bbac: 4621 mov r1, r4 800bbae: f7ff ffa1 bl 800baf4 CCS_LogUart3Error("UART3 RX arm failed details"); 800bbb2: 4808 ldr r0, [pc, #32] @ (800bbd4 ) 800bbb4: f000 fedc bl 800c970 if (err_after != HAL_UART_ERROR_NONE) { 800bbb8: 2c00 cmp r4, #0 800bbba: d0e7 beq.n 800bb8c (void)HAL_UART_AbortReceive(&huart3); 800bbbc: 4803 ldr r0, [pc, #12] @ (800bbcc ) } 800bbbe: b003 add sp, #12 800bbc0: e8bd 4030 ldmia.w sp!, {r4, r5, lr} (void)HAL_UART_AbortReceive(&huart3); 800bbc4: f007 bb10 b.w 80131e8 800bbc8: 200009ac .word 0x200009ac 800bbcc: 20001330 .word 0x20001330 800bbd0: 08017158 .word 0x08017158 800bbd4: 08017194 .word 0x08017194 0800bbd8 : ISR_FAST void CCS_RxEventCallback(UART_HandleTypeDef *huart, uint16_t size) { 800bbd8: b538 push {r3, r4, r5, lr} if (huart != &huart3) { 800bbda: 4b1a ldr r3, [pc, #104] @ (800bc44 ) ISR_FAST void CCS_RxEventCallback(UART_HandleTypeDef *huart, uint16_t size) { 800bbdc: 460c mov r4, r1 if (huart != &huart3) { 800bbde: 4283 cmp r3, r0 800bbe0: d113 bne.n 800bc0a log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", (unsigned)size); return; } if (size == 0u) { 800bbe2: b329 cbz r1, 800bc30 log_printf(LOG_WARN, "UART3 RX drop: RxEvent size=0 (idle, no payload)\n"); uart3_arm_rx_or_log("RxEventCallback"); return; } if (size > sizeof(rx_buffer)) { 800bbe4: f5b1 7f80 cmp.w r1, #256 @ 0x100 800bbe8: d816 bhi.n 800bc18 log_printf(LOG_ERR, "UART3 RX drop: size=%u > rx_buffer %u (overflow, not parsed)\n", (unsigned)size, (unsigned)sizeof(rx_buffer)); uart3_arm_rx_or_log("RxEventCallback"); return; } uart3_last_packet_tick = HAL_GetTick(); 800bbea: f002 fb73 bl 800e2d4 800bbee: 4603 mov r3, r0 800bbf0: 4d15 ldr r5, [pc, #84] @ (800bc48 ) uart3_last_reinit_tick = uart3_last_packet_tick; 800bbf2: 4a16 ldr r2, [pc, #88] @ (800bc4c ) process_received_packet(rx_buffer, size); 800bbf4: 4621 mov r1, r4 800bbf6: 4816 ldr r0, [pc, #88] @ (800bc50 ) uart3_last_packet_tick = HAL_GetTick(); 800bbf8: 602b str r3, [r5, #0] uart3_last_reinit_tick = uart3_last_packet_tick; 800bbfa: 6013 str r3, [r2, #0] process_received_packet(rx_buffer, size); 800bbfc: f000 fe10 bl 800c820 uart3_arm_rx_or_log("RxEventCallback"); } 800bc00: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800bc04: 4813 ldr r0, [pc, #76] @ (800bc54 ) 800bc06: f7ff bfb7 b.w 800bb78 log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", 800bc0a: 460a mov r2, r1 } 800bc0c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", 800bc10: 2005 movs r0, #5 800bc12: 4911 ldr r1, [pc, #68] @ (800bc58 ) 800bc14: f7fe bc6e b.w 800a4f4 log_printf(LOG_ERR, "UART3 RX drop: size=%u > rx_buffer %u (overflow, not parsed)\n", 800bc18: f44f 7380 mov.w r3, #256 @ 0x100 800bc1c: 460a mov r2, r1 800bc1e: 2004 movs r0, #4 800bc20: 490e ldr r1, [pc, #56] @ (800bc5c ) 800bc22: f7fe fc67 bl 800a4f4 } 800bc26: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800bc2a: 480a ldr r0, [pc, #40] @ (800bc54 ) 800bc2c: f7ff bfa4 b.w 800bb78 log_printf(LOG_WARN, "UART3 RX drop: RxEvent size=0 (idle, no payload)\n"); 800bc30: 2005 movs r0, #5 800bc32: 490b ldr r1, [pc, #44] @ (800bc60 ) 800bc34: f7fe fc5e bl 800a4f4 } 800bc38: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800bc3c: 4805 ldr r0, [pc, #20] @ (800bc54 ) 800bc3e: f7ff bf9b b.w 800bb78 800bc42: bf00 nop 800bc44: 20001330 .word 0x20001330 800bc48: 20000cbc .word 0x20000cbc 800bc4c: 20000cc0 .word 0x20000cc0 800bc50: 200009ac .word 0x200009ac 800bc54: 08017220 .word 0x08017220 800bc58: 080171b0 .word 0x080171b0 800bc5c: 08017230 .word 0x08017230 800bc60: 080171ec .word 0x080171ec 0800bc64 : ISR_FAST void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 800bc64: b5f8 push {r3, r4, r5, r6, r7, lr} 800bc66: 4604 mov r4, r0 uint32_t error = HAL_UART_GetError(huart); 800bc68: f007 fe0f bl 801388a uint8_t uart_num = 800bc6c: 4b29 ldr r3, [pc, #164] @ (800bd14 ) uint32_t error = HAL_UART_GetError(huart); 800bc6e: 4605 mov r5, r0 uint8_t uart_num = 800bc70: 429c cmp r4, r3 800bc72: d032 beq.n 800bcda 800bc74: 4e28 ldr r6, [pc, #160] @ (800bd18 ) 800bc76: 42b4 cmp r4, r6 800bc78: d017 beq.n 800bcaa 800bc7a: 4b28 ldr r3, [pc, #160] @ (800bd1c ) 800bc7c: 429c cmp r4, r3 800bc7e: d045 beq.n 800bd0c (huart == &huart2) ? 2 : (huart == &huart3) ? 3 : (huart == &huart5) ? 5 : 0; log_printf(LOG_ERR, 800bc80: 4603 mov r3, r0 800bc82: 2200 movs r2, #0 800bc84: 4926 ldr r1, [pc, #152] @ (800bd20 ) 800bc86: 2004 movs r0, #4 800bc88: f7fe fc34 bl 800a4f4 "UART%u HAL error (ISR): raw=0x%08lx — RX may be corrupted until re-arm\n", uart_num, (unsigned long)error); uart3_log_hal_error(uart_num, error); 800bc8c: 4629 mov r1, r5 800bc8e: 2000 movs r0, #0 800bc90: f7ff ff30 bl 800baf4 (void)HAL_UART_AbortReceive(huart); 800bc94: 4620 mov r0, r4 800bc96: f007 faa7 bl 80131e8 (void)HAL_UART_AbortTransmit(huart); 800bc9a: 4620 mov r0, r4 800bc9c: f007 fa3c bl 8013118 if (huart == &huart3) { uart3_tx_busy = 0; uart3_arm_rx_or_log("ErrorCallback"); } else { SC_RecoverUartDma(huart); 800bca0: 4620 mov r0, r4 } } 800bca2: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} SC_RecoverUartDma(huart); 800bca6: f001 b91f b.w 800cee8 log_printf(LOG_ERR, 800bcaa: 4603 mov r3, r0 800bcac: 2203 movs r2, #3 800bcae: 491c ldr r1, [pc, #112] @ (800bd20 ) 800bcb0: 2004 movs r0, #4 800bcb2: f7fe fc1f bl 800a4f4 uart3_log_hal_error(uart_num, error); 800bcb6: 4629 mov r1, r5 800bcb8: 2003 movs r0, #3 800bcba: f7ff ff1b bl 800baf4 (void)HAL_UART_AbortReceive(huart); 800bcbe: 4620 mov r0, r4 800bcc0: f007 fa92 bl 80131e8 (void)HAL_UART_AbortTransmit(huart); 800bcc4: 4620 mov r0, r4 800bcc6: f007 fa27 bl 8013118 uart3_tx_busy = 0; 800bcca: 2200 movs r2, #0 800bccc: 4b15 ldr r3, [pc, #84] @ (800bd24 ) uart3_arm_rx_or_log("ErrorCallback"); 800bcce: 4816 ldr r0, [pc, #88] @ (800bd28 ) uart3_tx_busy = 0; 800bcd0: 701a strb r2, [r3, #0] } 800bcd2: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} uart3_arm_rx_or_log("ErrorCallback"); 800bcd6: f7ff bf4f b.w 800bb78 800bcda: 2202 movs r2, #2 uint8_t uart_num = 800bcdc: 4617 mov r7, r2 800bcde: 4e0e ldr r6, [pc, #56] @ (800bd18 ) log_printf(LOG_ERR, 800bce0: 462b mov r3, r5 800bce2: 490f ldr r1, [pc, #60] @ (800bd20 ) 800bce4: 2004 movs r0, #4 800bce6: f7fe fc05 bl 800a4f4 uart3_log_hal_error(uart_num, error); 800bcea: 4629 mov r1, r5 800bcec: 4638 mov r0, r7 800bcee: f7ff ff01 bl 800baf4 (void)HAL_UART_AbortReceive(huart); 800bcf2: 4620 mov r0, r4 800bcf4: f007 fa78 bl 80131e8 (void)HAL_UART_AbortTransmit(huart); 800bcf8: 4620 mov r0, r4 800bcfa: f007 fa0d bl 8013118 if (huart == &huart3) { 800bcfe: 42b4 cmp r4, r6 800bd00: d0e3 beq.n 800bcca SC_RecoverUartDma(huart); 800bd02: 4620 mov r0, r4 } 800bd04: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} SC_RecoverUartDma(huart); 800bd08: f001 b8ee b.w 800cee8 800bd0c: 2205 movs r2, #5 uint8_t uart_num = 800bd0e: 4617 mov r7, r2 800bd10: e7e6 b.n 800bce0 800bd12: bf00 nop 800bd14: 200012e8 .word 0x200012e8 800bd18: 20001330 .word 0x20001330 800bd1c: 20001258 .word 0x20001258 800bd20: 08017270 .word 0x08017270 800bd24: 20000cae .word 0x20000cae 800bd28: 080172bc .word 0x080172bc 0800bd2c : void CCS_TxCpltCallback(UART_HandleTypeDef *huart) { 800bd2c: b580 push {r7, lr} 800bd2e: b082 sub sp, #8 800bd30: af00 add r7, sp, #0 800bd32: 6078 str r0, [r7, #4] if (huart != &huart3) { 800bd34: 687b ldr r3, [r7, #4] 800bd36: 4a16 ldr r2, [pc, #88] @ (800bd90 ) 800bd38: 4293 cmp r3, r2 800bd3a: d124 bne.n 800bd86 return; } uart3_tx_busy = 0; 800bd3c: 4b15 ldr r3, [pc, #84] @ (800bd94 ) 800bd3e: 2200 movs r2, #0 800bd40: 701a strb r2, [r3, #0] if (tx_pending_len > 0) { 800bd42: 4b15 ldr r3, [pc, #84] @ (800bd98 ) 800bd44: 881b ldrh r3, [r3, #0] 800bd46: 2b00 cmp r3, #0 800bd48: d01e beq.n 800bd88 memcpy(tx_buffer, tx_pending_buffer, tx_pending_len); 800bd4a: 4b13 ldr r3, [pc, #76] @ (800bd98 ) 800bd4c: 881b ldrh r3, [r3, #0] 800bd4e: 461a mov r2, r3 800bd50: 4912 ldr r1, [pc, #72] @ (800bd9c ) 800bd52: 4813 ldr r0, [pc, #76] @ (800bda0 ) 800bd54: f008 ffc0 bl 8014cd8 uart3_tx_busy = 1; 800bd58: 4b0e ldr r3, [pc, #56] @ (800bd94 ) 800bd5a: 2201 movs r2, #1 800bd5c: 701a strb r2, [r3, #0] if (HAL_UART_Transmit_DMA(&huart3, tx_buffer, tx_pending_len) != HAL_OK) { 800bd5e: 4b0e ldr r3, [pc, #56] @ (800bd98 ) 800bd60: 881b ldrh r3, [r3, #0] 800bd62: 461a mov r2, r3 800bd64: 490e ldr r1, [pc, #56] @ (800bda0 ) 800bd66: 480a ldr r0, [pc, #40] @ (800bd90 ) 800bd68: f007 f8b0 bl 8012ecc 800bd6c: 4603 mov r3, r0 800bd6e: 2b00 cmp r3, #0 800bd70: d005 beq.n 800bd7e uart3_tx_busy = 0; 800bd72: 4b08 ldr r3, [pc, #32] @ (800bd94 ) 800bd74: 2200 movs r2, #0 800bd76: 701a strb r2, [r3, #0] CCS_LogUart3Error("UART3 TX DMA resend failed"); 800bd78: 480a ldr r0, [pc, #40] @ (800bda4 ) 800bd7a: f000 fdf9 bl 800c970 } tx_pending_len = 0; 800bd7e: 4b06 ldr r3, [pc, #24] @ (800bd98 ) 800bd80: 2200 movs r2, #0 800bd82: 801a strh r2, [r3, #0] 800bd84: e000 b.n 800bd88 return; 800bd86: bf00 nop } } 800bd88: 3708 adds r7, #8 800bd8a: 46bd mov sp, r7 800bd8c: bd80 pop {r7, pc} 800bd8e: bf00 nop 800bd90: 20001330 .word 0x20001330 800bd94: 20000cae .word 0x20000cae 800bd98: 20000cac .word 0x20000cac 800bd9c: 20000bac .word 0x20000bac 800bda0: 20000aac .word 0x20000aac 800bda4: 080172cc .word 0x080172cc 0800bda8 : void CCS_SerialLoop(void) { 800bda8: b580 push {r7, lr} 800bdaa: b082 sub sp, #8 800bdac: af00 add r7, sp, #0 static uint32_t tick; if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800bdae: f002 fa91 bl 800e2d4 800bdb2: 4602 mov r2, r0 800bdb4: 4ba5 ldr r3, [pc, #660] @ (800c04c ) 800bdb6: 681b ldr r3, [r3, #0] 800bdb8: 1ad3 subs r3, r2, r3 800bdba: 2b00 cmp r3, #0 800bdbc: f340 826b ble.w 800c296 tick = HAL_GetTick(); 800bdc0: f002 fa88 bl 800e2d4 800bdc4: 4603 mov r3, r0 800bdc6: 4aa1 ldr r2, [pc, #644] @ (800c04c ) 800bdc8: 6013 str r3, [r2, #0] static uint32_t replug_watchdog1_tick = 0; static uint32_t last_state_sent = 0; static uint32_t force_unlock_tick = 0; static uint32_t stop_tick = 0; CCS_UART3_Watchdog(); 800bdca: f000 fd97 bl 800c8fc if (CONN.connControl != CMD_NONE) { 800bdce: 4ba0 ldr r3, [pc, #640] @ (800c050 ) 800bdd0: 781b ldrb r3, [r3, #0] 800bdd2: 2b00 cmp r3, #0 800bdd4: d003 beq.n 800bdde last_cmd = CONN.connControl; 800bdd6: 4b9e ldr r3, [pc, #632] @ (800c050 ) 800bdd8: 781a ldrb r2, [r3, #0] 800bdda: 4b9e ldr r3, [pc, #632] @ (800c054 ) 800bddc: 701a strb r2, [r3, #0] } if (CONN.connControl == CMD_FORCE_UNLOCK) { 800bdde: 4b9c ldr r3, [pc, #624] @ (800c050 ) 800bde0: 781b ldrb r3, [r3, #0] 800bde2: 2b03 cmp r3, #3 800bde4: d11b bne.n 800be1e if (force_unlock_tick == 0) { 800bde6: 4b9c ldr r3, [pc, #624] @ (800c058 ) 800bde8: 681b ldr r3, [r3, #0] 800bdea: 2b00 cmp r3, #0 800bdec: d105 bne.n 800bdfa force_unlock_tick = HAL_GetTick(); 800bdee: f002 fa71 bl 800e2d4 800bdf2: 4603 mov r3, r0 800bdf4: 4a98 ldr r2, [pc, #608] @ (800c058 ) 800bdf6: 6013 str r3, [r2, #0] 800bdf8: e014 b.n 800be24 } else if ((int32_t)(HAL_GetTick() - force_unlock_tick) >= 10000) { 800bdfa: f002 fa6b bl 800e2d4 800bdfe: 4602 mov r2, r0 800be00: 4b95 ldr r3, [pc, #596] @ (800c058 ) 800be02: 681b ldr r3, [r3, #0] 800be04: 1ad3 subs r3, r2, r3 800be06: 461a mov r2, r3 800be08: f242 730f movw r3, #9999 @ 0x270f 800be0c: 429a cmp r2, r3 800be0e: dd09 ble.n 800be24 CONN.connControl = CMD_NONE; 800be10: 4b8f ldr r3, [pc, #572] @ (800c050 ) 800be12: 2200 movs r2, #0 800be14: 701a strb r2, [r3, #0] force_unlock_tick = 0; 800be16: 4b90 ldr r3, [pc, #576] @ (800c058 ) 800be18: 2200 movs r2, #0 800be1a: 601a str r2, [r3, #0] 800be1c: e002 b.n 800be24 } } else { force_unlock_tick = 0; 800be1e: 4b8e ldr r3, [pc, #568] @ (800c058 ) 800be20: 2200 movs r2, #0 800be22: 601a str r2, [r3, #0] } if (CONN.connControl == CMD_STOP) { 800be24: 4b8a ldr r3, [pc, #552] @ (800c050 ) 800be26: 781b ldrb r3, [r3, #0] 800be28: 2b01 cmp r3, #1 800be2a: d119 bne.n 800be60 if (stop_tick == 0) { 800be2c: 4b8b ldr r3, [pc, #556] @ (800c05c ) 800be2e: 681b ldr r3, [r3, #0] 800be30: 2b00 cmp r3, #0 800be32: d105 bne.n 800be40 stop_tick = HAL_GetTick(); 800be34: f002 fa4e bl 800e2d4 800be38: 4603 mov r3, r0 800be3a: 4a88 ldr r2, [pc, #544] @ (800c05c ) 800be3c: 6013 str r3, [r2, #0] 800be3e: e012 b.n 800be66 } else if ((int32_t)(HAL_GetTick() - stop_tick) >= 1000) { 800be40: f002 fa48 bl 800e2d4 800be44: 4602 mov r2, r0 800be46: 4b85 ldr r3, [pc, #532] @ (800c05c ) 800be48: 681b ldr r3, [r3, #0] 800be4a: 1ad3 subs r3, r2, r3 800be4c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800be50: db09 blt.n 800be66 CONN.connControl = CMD_NONE; 800be52: 4b7f ldr r3, [pc, #508] @ (800c050 ) 800be54: 2200 movs r2, #0 800be56: 701a strb r2, [r3, #0] stop_tick = 0; 800be58: 4b80 ldr r3, [pc, #512] @ (800c05c ) 800be5a: 2200 movs r2, #0 800be5c: 601a str r2, [r3, #0] 800be5e: e002 b.n 800be66 } } else { stop_tick = 0; 800be60: 4b7e ldr r3, [pc, #504] @ (800c05c ) 800be62: 2200 movs r2, #0 800be64: 601a str r2, [r3, #0] } if((int32_t)(HAL_GetTick() - last_cmd_sent) > (int32_t)CMD_INTERVAL){ 800be66: f002 fa35 bl 800e2d4 800be6a: 4602 mov r2, r0 800be6c: 4b7c ldr r3, [pc, #496] @ (800c060 ) 800be6e: 681b ldr r3, [r3, #0] 800be70: 1ad3 subs r3, r2, r3 800be72: 2b0a cmp r3, #10 800be74: dd5e ble.n 800bf34 if ((int32_t)(HAL_GetTick() - last_state_sent) >= 200) { 800be76: f002 fa2d bl 800e2d4 800be7a: 4602 mov r2, r0 800be7c: 4b79 ldr r3, [pc, #484] @ (800c064 ) 800be7e: 681b ldr r3, [r3, #0] 800be80: 1ad3 subs r3, r2, r3 800be82: 2bc7 cmp r3, #199 @ 0xc7 800be84: dd06 ble.n 800be94 send_state(); 800be86: f000 fb9b bl 800c5c0 last_state_sent = HAL_GetTick(); 800be8a: f002 fa23 bl 800e2d4 800be8e: 4603 mov r3, r0 800be90: 4a74 ldr r2, [pc, #464] @ (800c064 ) 800be92: 6013 str r3, [r2, #0] } if (ESTOP) { 800be94: 4b74 ldr r3, [pc, #464] @ (800c068 ) 800be96: 781b ldrb r3, [r3, #0] 800be98: 2b00 cmp r3, #0 800be9a: d008 beq.n 800beae log_printf(LOG_ERR, "ESTOP triggered\n"); 800be9c: 4973 ldr r1, [pc, #460] @ (800c06c ) 800be9e: 2004 movs r0, #4 800bea0: f7fe fb28 bl 800a4f4 CCS_SendEmergencyStop(); 800bea4: f000 fb2c bl 800c500 ESTOP = 0; 800bea8: 4b6f ldr r3, [pc, #444] @ (800c068 ) 800beaa: 2200 movs r2, #0 800beac: 701a strb r2, [r3, #0] } if (((CONN.connControl == CMD_STOP) || 800beae: 4b68 ldr r3, [pc, #416] @ (800c050 ) 800beb0: 781b ldrb r3, [r3, #0] 800beb2: 2b01 cmp r3, #1 800beb4: d007 beq.n 800bec6 (CONN.connControl == CMD_FORCE_UNLOCK) || 800beb6: 4b66 ldr r3, [pc, #408] @ (800c050 ) 800beb8: 781b ldrb r3, [r3, #0] if (((CONN.connControl == CMD_STOP) || 800beba: 2b03 cmp r3, #3 800bebc: d003 beq.n 800bec6 (CONN.chargingError != CONN_NO_ERROR)) && 800bebe: 4b64 ldr r3, [pc, #400] @ (800c050 ) 800bec0: 7f5b ldrb r3, [r3, #29] (CONN.connControl == CMD_FORCE_UNLOCK) || 800bec2: 2b00 cmp r3, #0 800bec4: d01a beq.n 800befc ((int32_t)(HAL_GetTick() - last_stop_sent) > 1000)) { 800bec6: f002 fa05 bl 800e2d4 800beca: 4602 mov r2, r0 800becc: 4b68 ldr r3, [pc, #416] @ (800c070 ) 800bece: 681b ldr r3, [r3, #0] 800bed0: 1ad3 subs r3, r2, r3 (CONN.chargingError != CONN_NO_ERROR)) && 800bed2: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bed6: dd11 ble.n 800befc last_stop_sent = HAL_GetTick(); 800bed8: f002 f9fc bl 800e2d4 800bedc: 4603 mov r3, r0 800bede: 4a64 ldr r2, [pc, #400] @ (800c070 ) 800bee0: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "Stopping charging...\n"); 800bee2: 4964 ldr r1, [pc, #400] @ (800c074 ) 800bee4: 2005 movs r0, #5 800bee6: f7fe fb05 bl 800a4f4 if (CONN.connControl == CMD_FORCE_UNLOCK) { 800beea: 4b59 ldr r3, [pc, #356] @ (800c050 ) 800beec: 781b ldrb r3, [r3, #0] 800beee: 2b03 cmp r3, #3 800bef0: d102 bne.n 800bef8 CP_SetDuty(100); 800bef2: 2064 movs r0, #100 @ 0x64 800bef4: f7fe f8bc bl 800a070 } CCS_SendEmergencyStop(); 800bef8: f000 fb02 bl 800c500 } if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800befc: 4b5e ldr r3, [pc, #376] @ (800c078 ) 800befe: 781b ldrb r3, [r3, #0] 800bf00: 2b0c cmp r3, #12 800bf02: d003 beq.n 800bf0c 800bf04: 4b5c ldr r3, [pc, #368] @ (800c078 ) 800bf06: 781b ldrb r3, [r3, #0] 800bf08: 2b0b cmp r3, #11 800bf0a: d113 bne.n 800bf34 ((int32_t)(HAL_GetTick() - last_stop_sent) > 1000)) { 800bf0c: f002 f9e2 bl 800e2d4 800bf10: 4602 mov r2, r0 800bf12: 4b57 ldr r3, [pc, #348] @ (800c070 ) 800bf14: 681b ldr r3, [r3, #0] 800bf16: 1ad3 subs r3, r2, r3 if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800bf18: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bf1c: dd0a ble.n 800bf34 last_stop_sent = HAL_GetTick(); 800bf1e: f002 f9d9 bl 800e2d4 800bf22: 4603 mov r3, r0 800bf24: 4a52 ldr r2, [pc, #328] @ (800c070 ) 800bf26: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "FinishedEV, stopping...\n"); 800bf28: 4954 ldr r1, [pc, #336] @ (800c07c ) 800bf2a: 2005 movs r0, #5 800bf2c: f7fe fae2 bl 800a4f4 CCS_SendEmergencyStop(); 800bf30: f000 fae6 bl 800c500 } (void)replug_watchdog_tick; (void)replug_watchdog1_tick; uint8_t host_timeout_warn = (last_host_seen > 0u) && ((int32_t)(HAL_GetTick() - last_host_seen) > (int32_t)EVEREST_TIMEOUT_WARN_MS); 800bf34: 4b52 ldr r3, [pc, #328] @ (800c080 ) 800bf36: 681b ldr r3, [r3, #0] 800bf38: 2b00 cmp r3, #0 800bf3a: d00c beq.n 800bf56 800bf3c: f002 f9ca bl 800e2d4 800bf40: 4602 mov r2, r0 800bf42: 4b4f ldr r3, [pc, #316] @ (800c080 ) 800bf44: 681b ldr r3, [r3, #0] 800bf46: 1ad3 subs r3, r2, r3 800bf48: 461a mov r2, r3 800bf4a: f241 3388 movw r3, #5000 @ 0x1388 800bf4e: 429a cmp r2, r3 800bf50: dd01 ble.n 800bf56 800bf52: 2301 movs r3, #1 800bf54: e000 b.n 800bf58 800bf56: 2300 movs r3, #0 800bf58: 71fb strb r3, [r7, #7] uint8_t host_timeout_stop = (last_host_seen > 0u) && ((int32_t)(HAL_GetTick() - last_host_seen) > (int32_t)EVEREST_TIMEOUT_STOP_MS); 800bf5a: 4b49 ldr r3, [pc, #292] @ (800c080 ) 800bf5c: 681b ldr r3, [r3, #0] 800bf5e: 2b00 cmp r3, #0 800bf60: d00c beq.n 800bf7c 800bf62: f002 f9b7 bl 800e2d4 800bf66: 4602 mov r2, r0 800bf68: 4b45 ldr r3, [pc, #276] @ (800c080 ) 800bf6a: 681b ldr r3, [r3, #0] 800bf6c: 1ad3 subs r3, r2, r3 800bf6e: 461a mov r2, r3 800bf70: f242 7310 movw r3, #10000 @ 0x2710 800bf74: 429a cmp r2, r3 800bf76: dd01 ble.n 800bf7c 800bf78: 2301 movs r3, #1 800bf7a: e000 b.n 800bf7e 800bf7c: 2300 movs r3, #0 800bf7e: 71bb strb r3, [r7, #6] uint8_t host_timed_out = host_timeout_stop; 800bf80: 79bb ldrb r3, [r7, #6] 800bf82: 717b strb r3, [r7, #5] if (host_timeout_warn && !everest_timeout_warn_latched) { 800bf84: 79fb ldrb r3, [r7, #7] 800bf86: 2b00 cmp r3, #0 800bf88: d00a beq.n 800bfa0 800bf8a: 4b3e ldr r3, [pc, #248] @ (800c084 ) 800bf8c: 781b ldrb r3, [r3, #0] 800bf8e: 2b00 cmp r3, #0 800bf90: d106 bne.n 800bfa0 log_printf(LOG_ERR, "Everest timeout\n"); 800bf92: 493d ldr r1, [pc, #244] @ (800c088 ) 800bf94: 2004 movs r0, #4 800bf96: f7fe faad bl 800a4f4 everest_timeout_warn_latched = 1; 800bf9a: 4b3a ldr r3, [pc, #232] @ (800c084 ) 800bf9c: 2201 movs r2, #1 800bf9e: 701a strb r2, [r3, #0] } if (host_timeout_stop && !everest_timeout_stop_latched) { 800bfa0: 79bb ldrb r3, [r7, #6] 800bfa2: 2b00 cmp r3, #0 800bfa4: d00a beq.n 800bfbc 800bfa6: 4b39 ldr r3, [pc, #228] @ (800c08c ) 800bfa8: 781b ldrb r3, [r3, #0] 800bfaa: 2b00 cmp r3, #0 800bfac: d106 bne.n 800bfbc log_printf(LOG_ERR, "Everest timeout, stopping charging...\n"); 800bfae: 4938 ldr r1, [pc, #224] @ (800c090 ) 800bfb0: 2004 movs r0, #4 800bfb2: f7fe fa9f bl 800a4f4 everest_timeout_stop_latched = 1; 800bfb6: 4b35 ldr r3, [pc, #212] @ (800c08c ) 800bfb8: 2201 movs r2, #1 800bfba: 701a strb r2, [r3, #0] } if (!host_timeout_warn) { 800bfbc: 79fb ldrb r3, [r7, #7] 800bfbe: 2b00 cmp r3, #0 800bfc0: d105 bne.n 800bfce everest_timeout_warn_latched = 0; 800bfc2: 4b30 ldr r3, [pc, #192] @ (800c084 ) 800bfc4: 2200 movs r2, #0 800bfc6: 701a strb r2, [r3, #0] everest_timeout_stop_latched = 0; 800bfc8: 4b30 ldr r3, [pc, #192] @ (800c08c ) 800bfca: 2200 movs r2, #0 800bfcc: 701a strb r2, [r3, #0] } everest_timed_out = host_timeout_stop; 800bfce: 4a31 ldr r2, [pc, #196] @ (800c094 ) 800bfd0: 79bb ldrb r3, [r7, #6] 800bfd2: 7013 strb r3, [r2, #0] switch(CCS_ConnectorState){ 800bfd4: 4b30 ldr r3, [pc, #192] @ (800c098 ) 800bfd6: 781b ldrb r3, [r3, #0] 800bfd8: 2b05 cmp r3, #5 800bfda: f200 8113 bhi.w 800c204 800bfde: a201 add r2, pc, #4 @ (adr r2, 800bfe4 ) 800bfe0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800bfe4: 0800bffd .word 0x0800bffd 800bfe8: 0800c025 .word 0x0800c025 800bfec: 0800c0a1 .word 0x0800c0a1 800bff0: 0800c0e5 .word 0x0800c0e5 800bff4: 0800c121 .word 0x0800c121 800bff8: 0800c179 .word 0x0800c179 case CCS_UNKNOWN: RELAY_Write(RELAY_CP, 0); 800bffc: 2100 movs r1, #0 800bffe: 2005 movs r0, #5 800c000: f7fd fbda bl 80097b8 CONN_SetState(Unknown); 800c004: 2000 movs r0, #0 800c006: f7fd ff3b bl 8009e80 if (config_initialized && !host_timed_out) { 800c00a: 4b24 ldr r3, [pc, #144] @ (800c09c ) 800c00c: 781b ldrb r3, [r3, #0] 800c00e: 2b00 cmp r3, #0 800c010: f000 80ed beq.w 800c1ee 800c014: 797b ldrb r3, [r7, #5] 800c016: 2b00 cmp r3, #0 800c018: f040 80e9 bne.w 800c1ee CCS_ConnectorState = CCS_UNPLUGGED; 800c01c: 4b1e ldr r3, [pc, #120] @ (800c098 ) 800c01e: 2202 movs r2, #2 800c020: 701a strb r2, [r3, #0] } break; 800c022: e0e4 b.n 800c1ee case CCS_DISABLED: RELAY_Write(RELAY_CP, 0); 800c024: 2100 movs r1, #0 800c026: 2005 movs r0, #5 800c028: f7fd fbc6 bl 80097b8 CONN_SetState(Disabled); 800c02c: 2002 movs r0, #2 800c02e: f7fd ff27 bl 8009e80 if ((CONN.chargingError == CONN_NO_ERROR) && !host_timed_out){ 800c032: 4b07 ldr r3, [pc, #28] @ (800c050 ) 800c034: 7f5b ldrb r3, [r3, #29] 800c036: 2b00 cmp r3, #0 800c038: f040 80db bne.w 800c1f2 800c03c: 797b ldrb r3, [r7, #5] 800c03e: 2b00 cmp r3, #0 800c040: f040 80d7 bne.w 800c1f2 CCS_ConnectorState = CCS_UNPLUGGED; 800c044: 4b14 ldr r3, [pc, #80] @ (800c098 ) 800c046: 2202 movs r2, #2 800c048: 701a strb r2, [r3, #0] } break; 800c04a: e0d2 b.n 800c1f2 800c04c: 20000d14 .word 0x20000d14 800c050: 200003b0 .word 0x200003b0 800c054: 200009a8 .word 0x200009a8 800c058: 20000d18 .word 0x20000d18 800c05c: 20000d1c .word 0x20000d1c 800c060: 200009a0 .word 0x200009a0 800c064: 20000d20 .word 0x20000d20 800c068: 20000caf .word 0x20000caf 800c06c: 080172e8 .word 0x080172e8 800c070: 200009a4 .word 0x200009a4 800c074: 080172fc .word 0x080172fc 800c078: 20000d10 .word 0x20000d10 800c07c: 08017314 .word 0x08017314 800c080: 20000cb4 .word 0x20000cb4 800c084: 20000cba .word 0x20000cba 800c088: 08017330 .word 0x08017330 800c08c: 20000cbb .word 0x20000cbb 800c090: 08017344 .word 0x08017344 800c094: 20000cb9 .word 0x20000cb9 800c098: 20000d11 .word 0x20000d11 800c09c: 200011c0 .word 0x200011c0 case CCS_UNPLUGGED: RELAY_Write(RELAY_CP, 1); 800c0a0: 2101 movs r1, #1 800c0a2: 2005 movs r0, #5 800c0a4: f7fd fb88 bl 80097b8 CONN_SetState(Unplugged); 800c0a8: 2001 movs r0, #1 800c0aa: f7fd fee9 bl 8009e80 if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || (cp_state_buffer == EV_STATE_C_CONN_ACTIVE)){ 800c0ae: 4b7c ldr r3, [pc, #496] @ (800c2a0 ) 800c0b0: 781b ldrb r3, [r3, #0] 800c0b2: 2b01 cmp r3, #1 800c0b4: d003 beq.n 800c0be 800c0b6: 4b7a ldr r3, [pc, #488] @ (800c2a0 ) 800c0b8: 781b ldrb r3, [r3, #0] 800c0ba: 2b02 cmp r3, #2 800c0bc: d102 bne.n 800c0c4 CCS_ConnectorState = CCS_AUTH_REQUIRED; 800c0be: 4b79 ldr r3, [pc, #484] @ (800c2a4 ) 800c0c0: 2203 movs r2, #3 800c0c2: 701a strb r2, [r3, #0] } if (CONN.chargingError != CONN_NO_ERROR){ 800c0c4: 4b78 ldr r3, [pc, #480] @ (800c2a8 ) 800c0c6: 7f5b ldrb r3, [r3, #29] 800c0c8: 2b00 cmp r3, #0 800c0ca: f000 8094 beq.w 800c1f6 log_printf(LOG_ERR, "Charging error %d, state -> disabled\n", CONN.chargingError); 800c0ce: 4b76 ldr r3, [pc, #472] @ (800c2a8 ) 800c0d0: 7f5b ldrb r3, [r3, #29] 800c0d2: 461a mov r2, r3 800c0d4: 4975 ldr r1, [pc, #468] @ (800c2ac ) 800c0d6: 2004 movs r0, #4 800c0d8: f7fe fa0c bl 800a4f4 CCS_ConnectorState = CCS_DISABLED; 800c0dc: 4b71 ldr r3, [pc, #452] @ (800c2a4 ) 800c0de: 2201 movs r2, #1 800c0e0: 701a strb r2, [r3, #0] } break; 800c0e2: e088 b.n 800c1f6 case CCS_AUTH_REQUIRED: RELAY_Write(RELAY_CP, 1); 800c0e4: 2101 movs r1, #1 800c0e6: 2005 movs r0, #5 800c0e8: f7fd fb66 bl 80097b8 CONN_SetState(AuthRequired); 800c0ec: 2004 movs r0, #4 800c0ee: f7fd fec7 bl 8009e80 if(CONN.connControl == CMD_START){ 800c0f2: 4b6d ldr r3, [pc, #436] @ (800c2a8 ) 800c0f4: 781b ldrb r3, [r3, #0] 800c0f6: 2b02 cmp r3, #2 800c0f8: d106 bne.n 800c108 log_printf(LOG_INFO, "Charging permitted, start charging\n"); 800c0fa: 496d ldr r1, [pc, #436] @ (800c2b0 ) 800c0fc: 2007 movs r0, #7 800c0fe: f7fe f9f9 bl 800a4f4 CCS_ConnectorState = CCS_CONNECTED; 800c102: 4b68 ldr r3, [pc, #416] @ (800c2a4 ) 800c104: 2204 movs r2, #4 800c106: 701a strb r2, [r3, #0] } if (cp_state_buffer == EV_STATE_A_IDLE){ 800c108: 4b65 ldr r3, [pc, #404] @ (800c2a0 ) 800c10a: 781b ldrb r3, [r3, #0] 800c10c: 2b00 cmp r3, #0 800c10e: d174 bne.n 800c1fa log_printf(LOG_INFO, "Car unplugged\n"); 800c110: 4968 ldr r1, [pc, #416] @ (800c2b4 ) 800c112: 2007 movs r0, #7 800c114: f7fe f9ee bl 800a4f4 CCS_ConnectorState = CCS_UNPLUGGED; 800c118: 4b62 ldr r3, [pc, #392] @ (800c2a4 ) 800c11a: 2202 movs r2, #2 800c11c: 701a strb r2, [r3, #0] } break; 800c11e: e06c b.n 800c1fa case CCS_CONNECTED: RELAY_Write(RELAY_CP, 1); 800c120: 2101 movs r1, #1 800c122: 2005 movs r0, #5 800c124: f7fd fb48 bl 80097b8 if((CCS_EvseState < Preparing) || (CCS_EvseState == AuthRequired)) { 800c128: 4b63 ldr r3, [pc, #396] @ (800c2b8 ) 800c12a: 781b ldrb r3, [r3, #0] 800c12c: 2b02 cmp r3, #2 800c12e: d903 bls.n 800c138 800c130: 4b61 ldr r3, [pc, #388] @ (800c2b8 ) 800c132: 781b ldrb r3, [r3, #0] 800c134: 2b04 cmp r3, #4 800c136: d103 bne.n 800c140 CONN_SetState(Preparing); 800c138: 2003 movs r0, #3 800c13a: f7fd fea1 bl 8009e80 800c13e: e004 b.n 800c14a } else { CONN_SetState(CCS_EvseState); 800c140: 4b5d ldr r3, [pc, #372] @ (800c2b8 ) 800c142: 781b ldrb r3, [r3, #0] 800c144: 4618 mov r0, r3 800c146: f7fd fe9b bl 8009e80 } if (cp_state_buffer == EV_STATE_A_IDLE){ 800c14a: 4b55 ldr r3, [pc, #340] @ (800c2a0 ) 800c14c: 781b ldrb r3, [r3, #0] 800c14e: 2b00 cmp r3, #0 800c150: d106 bne.n 800c160 log_printf(LOG_INFO, "Car unplugged\n"); 800c152: 4958 ldr r1, [pc, #352] @ (800c2b4 ) 800c154: 2007 movs r0, #7 800c156: f7fe f9cd bl 800a4f4 CCS_ConnectorState = CCS_UNPLUGGED; 800c15a: 4b52 ldr r3, [pc, #328] @ (800c2a4 ) 800c15c: 2202 movs r2, #2 800c15e: 701a strb r2, [r3, #0] } if(REPLUG > 0){ 800c160: 4b56 ldr r3, [pc, #344] @ (800c2bc ) 800c162: 781b ldrb r3, [r3, #0] 800c164: 2b00 cmp r3, #0 800c166: d04a beq.n 800c1fe log_printf(LOG_INFO, "Replugging...\n"); 800c168: 4955 ldr r1, [pc, #340] @ (800c2c0 ) 800c16a: 2007 movs r0, #7 800c16c: f7fe f9c2 bl 800a4f4 CCS_ConnectorState = CCS_REPLUGGING; 800c170: 4b4c ldr r3, [pc, #304] @ (800c2a4 ) 800c172: 2205 movs r2, #5 800c174: 701a strb r2, [r3, #0] } break; 800c176: e042 b.n 800c1fe case CCS_REPLUGGING: RELAY_Write(RELAY_CP, 0); 800c178: 2100 movs r1, #0 800c17a: 2005 movs r0, #5 800c17c: f7fd fb1c bl 80097b8 CONN_SetState(Replugging); 800c180: 200d movs r0, #13 800c182: f7fd fe7d bl 8009e80 if((int32_t)(HAL_GetTick() - replug_tick) > 1000){ 800c186: f002 f8a5 bl 800e2d4 800c18a: 4602 mov r2, r0 800c18c: 4b4d ldr r3, [pc, #308] @ (800c2c4 ) 800c18e: 681b ldr r3, [r3, #0] 800c190: 1ad3 subs r3, r2, r3 800c192: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800c196: dd1a ble.n 800c1ce replug_tick = HAL_GetTick(); 800c198: f002 f89c bl 800e2d4 800c19c: 4603 mov r3, r0 800c19e: 4a49 ldr r2, [pc, #292] @ (800c2c4 ) 800c1a0: 6013 str r3, [r2, #0] if(REPLUG > 0){ 800c1a2: 4b46 ldr r3, [pc, #280] @ (800c2bc ) 800c1a4: 781b ldrb r3, [r3, #0] 800c1a6: 2b00 cmp r3, #0 800c1a8: d00a beq.n 800c1c0 if (REPLUG != 0xFF) REPLUG--; 800c1aa: 4b44 ldr r3, [pc, #272] @ (800c2bc ) 800c1ac: 781b ldrb r3, [r3, #0] 800c1ae: 2bff cmp r3, #255 @ 0xff 800c1b0: d00d beq.n 800c1ce 800c1b2: 4b42 ldr r3, [pc, #264] @ (800c2bc ) 800c1b4: 781b ldrb r3, [r3, #0] 800c1b6: 3b01 subs r3, #1 800c1b8: b2da uxtb r2, r3 800c1ba: 4b40 ldr r3, [pc, #256] @ (800c2bc ) 800c1bc: 701a strb r2, [r3, #0] 800c1be: e006 b.n 800c1ce } else { log_printf(LOG_INFO, "Replugging finished, but car unplugged\n"); 800c1c0: 4941 ldr r1, [pc, #260] @ (800c2c8 ) 800c1c2: 2007 movs r0, #7 800c1c4: f7fe f996 bl 800a4f4 CCS_ConnectorState = CCS_UNPLUGGED; 800c1c8: 4b36 ldr r3, [pc, #216] @ (800c2a4 ) 800c1ca: 2202 movs r2, #2 800c1cc: 701a strb r2, [r3, #0] } } if(REPLUG == 0){ 800c1ce: 4b3b ldr r3, [pc, #236] @ (800c2bc ) 800c1d0: 781b ldrb r3, [r3, #0] 800c1d2: 2b00 cmp r3, #0 800c1d4: d115 bne.n 800c202 if(cp_state_buffer == EV_STATE_B_CONN_PREP){ 800c1d6: 4b32 ldr r3, [pc, #200] @ (800c2a0 ) 800c1d8: 781b ldrb r3, [r3, #0] 800c1da: 2b01 cmp r3, #1 800c1dc: d111 bne.n 800c202 log_printf(LOG_INFO, "Replugging finished, car plugged, state -> auth required\n"); 800c1de: 493b ldr r1, [pc, #236] @ (800c2cc ) 800c1e0: 2007 movs r0, #7 800c1e2: f7fe f987 bl 800a4f4 CCS_ConnectorState = CCS_AUTH_REQUIRED; 800c1e6: 4b2f ldr r3, [pc, #188] @ (800c2a4 ) 800c1e8: 2203 movs r2, #3 800c1ea: 701a strb r2, [r3, #0] } } break; 800c1ec: e009 b.n 800c202 break; 800c1ee: bf00 nop 800c1f0: e008 b.n 800c204 break; 800c1f2: bf00 nop 800c1f4: e006 b.n 800c204 break; 800c1f6: bf00 nop 800c1f8: e004 b.n 800c204 break; 800c1fa: bf00 nop 800c1fc: e002 b.n 800c204 break; 800c1fe: bf00 nop 800c200: e000 b.n 800c204 break; 800c202: bf00 nop } // 10s timeout: enforce safe-state until host communication recovers. if (host_timeout_stop) { 800c204: 79bb ldrb r3, [r7, #6] 800c206: 2b00 cmp r3, #0 800c208: d014 beq.n 800c234 CONN.EnableOutput = 0; 800c20a: 4b27 ldr r3, [pc, #156] @ (800c2a8 ) 800c20c: 2200 movs r2, #0 800c20e: 75da strb r2, [r3, #23] CCS_EvseState = Unknown; 800c210: 4b29 ldr r3, [pc, #164] @ (800c2b8 ) 800c212: 2200 movs r2, #0 800c214: 701a strb r2, [r3, #0] CP_SetDuty(100); 800c216: 2064 movs r0, #100 @ 0x64 800c218: f7fd ff2a bl 800a070 if (CCS_ConnectorState != CCS_DISABLED && CCS_ConnectorState != CCS_UNKNOWN) { 800c21c: 4b21 ldr r3, [pc, #132] @ (800c2a4 ) 800c21e: 781b ldrb r3, [r3, #0] 800c220: 2b01 cmp r3, #1 800c222: d024 beq.n 800c26e 800c224: 4b1f ldr r3, [pc, #124] @ (800c2a4 ) 800c226: 781b ldrb r3, [r3, #0] 800c228: 2b00 cmp r3, #0 800c22a: d020 beq.n 800c26e CCS_ConnectorState = CCS_DISABLED; 800c22c: 4b1d ldr r3, [pc, #116] @ (800c2a4 ) 800c22e: 2201 movs r2, #1 800c230: 701a strb r2, [r3, #0] 800c232: e01c b.n 800c26e } } else { if (last_cmd == CMD_STOP) { 800c234: 4b26 ldr r3, [pc, #152] @ (800c2d0 ) 800c236: 781b ldrb r3, [r3, #0] 800c238: 2b01 cmp r3, #1 800c23a: d103 bne.n 800c244 CONN.EnableOutput = 0; 800c23c: 4b1a ldr r3, [pc, #104] @ (800c2a8 ) 800c23e: 2200 movs r2, #0 800c240: 75da strb r2, [r3, #23] 800c242: e014 b.n 800c26e } else { CONN.EnableOutput = ev_enable_output ? 1 : 0; 800c244: 4b23 ldr r3, [pc, #140] @ (800c2d4 ) 800c246: 781b ldrb r3, [r3, #0] 800c248: 2b00 cmp r3, #0 800c24a: bf14 ite ne 800c24c: 2301 movne r3, #1 800c24e: 2300 moveq r3, #0 800c250: b2db uxtb r3, r3 800c252: 461a mov r2, r3 800c254: 4b14 ldr r3, [pc, #80] @ (800c2a8 ) 800c256: 75da strb r2, [r3, #23] if((CONN.EnableOutput == 0) && (CONN.connState == Preparing)){ 800c258: 4b13 ldr r3, [pc, #76] @ (800c2a8 ) 800c25a: 7ddb ldrb r3, [r3, #23] 800c25c: 2b00 cmp r3, #0 800c25e: d106 bne.n 800c26e 800c260: 4b11 ldr r3, [pc, #68] @ (800c2a8 ) 800c262: 785b ldrb r3, [r3, #1] 800c264: 2b03 cmp r3, #3 800c266: d102 bne.n 800c26e CONN.EnableOutput = 0; 800c268: 4b0f ldr r3, [pc, #60] @ (800c2a8 ) 800c26a: 2200 movs r2, #0 800c26c: 75da strb r2, [r3, #23] } } } if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800c26e: 4b0c ldr r3, [pc, #48] @ (800c2a0 ) 800c270: 781b ldrb r3, [r3, #0] 800c272: 2b01 cmp r3, #1 800c274: d007 beq.n 800c286 (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800c276: 4b0a ldr r3, [pc, #40] @ (800c2a0 ) 800c278: 781b ldrb r3, [r3, #0] if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800c27a: 2b02 cmp r3, #2 800c27c: d003 beq.n 800c286 (cp_state_buffer == EV_STATE_D_CONN_ACT_VENT)) { 800c27e: 4b08 ldr r3, [pc, #32] @ (800c2a0 ) 800c280: 781b ldrb r3, [r3, #0] (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800c282: 2b03 cmp r3, #3 800c284: d103 bne.n 800c28e CONN.EvConnected = 1; 800c286: 4b08 ldr r3, [pc, #32] @ (800c2a8 ) 800c288: 2201 movs r2, #1 800c28a: 779a strb r2, [r3, #30] 800c28c: e004 b.n 800c298 } else { CONN.EvConnected = 0; 800c28e: 4b06 ldr r3, [pc, #24] @ (800c2a8 ) 800c290: 2200 movs r2, #0 800c292: 779a strb r2, [r3, #30] 800c294: e000 b.n 800c298 if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800c296: bf00 nop } } 800c298: 3708 adds r7, #8 800c29a: 46bd mov sp, r7 800c29c: bd80 pop {r7, pc} 800c29e: bf00 nop 800c2a0: 20000005 .word 0x20000005 800c2a4: 20000d11 .word 0x20000d11 800c2a8: 200003b0 .word 0x200003b0 800c2ac: 0801736c .word 0x0801736c 800c2b0: 08017394 .word 0x08017394 800c2b4: 080173b8 .word 0x080173b8 800c2b8: 20000d10 .word 0x20000d10 800c2bc: 20000cb0 .word 0x20000cb0 800c2c0: 080173c8 .word 0x080173c8 800c2c4: 20000d24 .word 0x20000d24 800c2c8: 080173d8 .word 0x080173d8 800c2cc: 08017400 .word 0x08017400 800c2d0: 200009a8 .word 0x200009a8 800c2d4: 200009a9 .word 0x200009a9 0800c2d8 : void CCS_Init(void){ 800c2d8: b580 push {r7, lr} 800c2da: af00 add r7, sp, #0 CP_Init(); 800c2dc: f7fd fea6 bl 800a02c CP_SetDuty(100); 800c2e0: 2064 movs r0, #100 @ 0x64 800c2e2: f7fd fec5 bl 800a070 CCS_MaxLoad.maxVoltage = PSU_MAX_VOLTAGE; // 1000V 800c2e6: 4b13 ldr r3, [pc, #76] @ (800c334 ) 800c2e8: f44f 727a mov.w r2, #1000 @ 0x3e8 800c2ec: 801a strh r2, [r3, #0] CCS_MaxLoad.minVoltage = PSU_MIN_VOLTAGE; //150V 800c2ee: 4b11 ldr r3, [pc, #68] @ (800c334 ) 800c2f0: 2296 movs r2, #150 @ 0x96 800c2f2: 805a strh r2, [r3, #2] CCS_MaxLoad.maxCurrent = PSU_MAX_CURRENT*10; //100A 800c2f4: 4b0f ldr r3, [pc, #60] @ (800c334 ) 800c2f6: f240 5232 movw r2, #1330 @ 0x532 800c2fa: 809a strh r2, [r3, #4] CCS_MaxLoad.minCurrent = PSU_MIN_CURRENT*10; //1A 800c2fc: 4b0d ldr r3, [pc, #52] @ (800c334 ) 800c2fe: 220a movs r2, #10 800c300: 80da strh r2, [r3, #6] CCS_MaxLoad.maxPower = PSU_MAX_POWER; //30000W 800c302: 4b0c ldr r3, [pc, #48] @ (800c334 ) 800c304: f649 4240 movw r2, #40000 @ 0x9c40 800c308: 609a str r2, [r3, #8] uart3_last_packet_tick = HAL_GetTick(); 800c30a: f001 ffe3 bl 800e2d4 800c30e: 4603 mov r3, r0 800c310: 4a09 ldr r2, [pc, #36] @ (800c338 ) 800c312: 6013 str r3, [r2, #0] uart3_last_reinit_tick = uart3_last_packet_tick; 800c314: 4b08 ldr r3, [pc, #32] @ (800c338 ) 800c316: 681b ldr r3, [r3, #0] 800c318: 4a08 ldr r2, [pc, #32] @ (800c33c ) 800c31a: 6013 str r3, [r2, #0] uart3_arm_rx_or_log("Init"); 800c31c: 4808 ldr r0, [pc, #32] @ (800c340 ) 800c31e: f7ff fc2b bl 800bb78 CCS_SendResetReason(); 800c322: f000 f8e3 bl 800c4ec log_printf(LOG_INFO, "CCS init\n"); 800c326: 4907 ldr r1, [pc, #28] @ (800c344 ) 800c328: 2007 movs r0, #7 800c32a: f7fe f8e3 bl 800a4f4 } 800c32e: bf00 nop 800c330: bd80 pop {r7, pc} 800c332: bf00 nop 800c334: 20000988 .word 0x20000988 800c338: 20000cbc .word 0x20000cbc 800c33c: 20000cc0 .word 0x20000cc0 800c340: 0801743c .word 0x0801743c 800c344: 08017444 .word 0x08017444 0800c348 : ISR_FAST static uint16_t crc16_ibm(const uint8_t* data, uint16_t length) { uint16_t crc = 0xFFFFu; for (uint16_t i = 0; i < length; i++) { 800c348: b3e9 cbz r1, 800c3c6 800c34a: 4684 mov ip, r0 ISR_FAST static uint16_t crc16_ibm(const uint8_t* data, uint16_t length) { 800c34c: b500 push {lr} 800c34e: 468e mov lr, r1 uint16_t crc = 0xFFFFu; 800c350: f64f 70ff movw r0, #65535 @ 0xffff crc ^= data[i]; for (uint8_t j = 0; j < 8; j++) { if (crc & 1u) { 800c354: 491d ldr r1, [pc, #116] @ (800c3cc ) 800c356: 44e6 add lr, ip crc ^= data[i]; 800c358: f81c 2b01 ldrb.w r2, [ip], #1 800c35c: 4042 eors r2, r0 if (crc & 1u) { 800c35e: f342 0300 sbfx r3, r2, #0, #1 800c362: 400b ands r3, r1 800c364: ea83 0352 eor.w r3, r3, r2, lsr #1 800c368: f343 0200 sbfx r2, r3, #0, #1 800c36c: 400a ands r2, r1 crc = (crc >> 1) ^ 0xA001u; } else { crc >>= 1; 800c36e: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c372: 405a eors r2, r3 800c374: f342 0300 sbfx r3, r2, #0, #1 800c378: 400b ands r3, r1 crc >>= 1; 800c37a: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800c37e: 4053 eors r3, r2 800c380: f343 0200 sbfx r2, r3, #0, #1 800c384: 400a ands r2, r1 crc >>= 1; 800c386: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c38a: 405a eors r2, r3 800c38c: f342 0300 sbfx r3, r2, #0, #1 800c390: 400b ands r3, r1 crc >>= 1; 800c392: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800c396: 4053 eors r3, r2 800c398: f343 0200 sbfx r2, r3, #0, #1 800c39c: 400a ands r2, r1 crc >>= 1; 800c39e: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c3a2: 405a eors r2, r3 800c3a4: f342 0300 sbfx r3, r2, #0, #1 800c3a8: 400b ands r3, r1 crc >>= 1; 800c3aa: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800c3ae: 4053 eors r3, r2 800c3b0: f343 0000 sbfx r0, r3, #0, #1 800c3b4: 4008 ands r0, r1 crc >>= 1; 800c3b6: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c3ba: 4058 eors r0, r3 for (uint16_t i = 0; i < length; i++) { 800c3bc: 45e6 cmp lr, ip if (crc & 1u) { 800c3be: b280 uxth r0, r0 for (uint16_t i = 0; i < length; i++) { 800c3c0: d1ca bne.n 800c358 } } } return crc; } 800c3c2: f85d fb04 ldr.w pc, [sp], #4 uint16_t crc = 0xFFFFu; 800c3c6: f64f 70ff movw r0, #65535 @ 0xffff } 800c3ca: 4770 bx lr 800c3cc: ffffa001 .word 0xffffa001 0800c3d0 : static uint16_t CCS_BuildPacket(uint8_t cmd, const void* payload, uint16_t payload_len, uint8_t* out, uint16_t out_max) { 800c3d0: b580 push {r7, lr} 800c3d2: b086 sub sp, #24 800c3d4: af00 add r7, sp, #0 800c3d6: 60b9 str r1, [r7, #8] 800c3d8: 607b str r3, [r7, #4] 800c3da: 4603 mov r3, r0 800c3dc: 73fb strb r3, [r7, #15] 800c3de: 4613 mov r3, r2 800c3e0: 81bb strh r3, [r7, #12] uint16_t total_len = (uint16_t)(1u + payload_len + 2u); 800c3e2: 89bb ldrh r3, [r7, #12] 800c3e4: 3303 adds r3, #3 800c3e6: 82fb strh r3, [r7, #22] if (total_len > out_max) return 0; 800c3e8: 8afa ldrh r2, [r7, #22] 800c3ea: 8c3b ldrh r3, [r7, #32] 800c3ec: 429a cmp r2, r3 800c3ee: d901 bls.n 800c3f4 800c3f0: 2300 movs r3, #0 800c3f2: e029 b.n 800c448 out[0] = cmd; 800c3f4: 687b ldr r3, [r7, #4] 800c3f6: 7bfa ldrb r2, [r7, #15] 800c3f8: 701a strb r2, [r3, #0] if (payload_len && payload != NULL) { 800c3fa: 89bb ldrh r3, [r7, #12] 800c3fc: 2b00 cmp r3, #0 800c3fe: d009 beq.n 800c414 800c400: 68bb ldr r3, [r7, #8] 800c402: 2b00 cmp r3, #0 800c404: d006 beq.n 800c414 memcpy(&out[1], payload, payload_len); 800c406: 687b ldr r3, [r7, #4] 800c408: 3301 adds r3, #1 800c40a: 89ba ldrh r2, [r7, #12] 800c40c: 68b9 ldr r1, [r7, #8] 800c40e: 4618 mov r0, r3 800c410: f008 fc62 bl 8014cd8 } uint16_t crc = crc16_ibm(out, (uint16_t)(1u + payload_len)); 800c414: 89bb ldrh r3, [r7, #12] 800c416: 3301 adds r3, #1 800c418: b29b uxth r3, r3 800c41a: 4619 mov r1, r3 800c41c: 6878 ldr r0, [r7, #4] 800c41e: f7ff ff93 bl 800c348 800c422: 4603 mov r3, r0 800c424: 82bb strh r3, [r7, #20] out[1u + payload_len] = (uint8_t)(crc & 0xFFu); 800c426: 89bb ldrh r3, [r7, #12] 800c428: 3301 adds r3, #1 800c42a: 687a ldr r2, [r7, #4] 800c42c: 4413 add r3, r2 800c42e: 8aba ldrh r2, [r7, #20] 800c430: b2d2 uxtb r2, r2 800c432: 701a strb r2, [r3, #0] out[1u + payload_len + 1u] = (uint8_t)((crc >> 8) & 0xFFu); 800c434: 8abb ldrh r3, [r7, #20] 800c436: 0a1b lsrs r3, r3, #8 800c438: b299 uxth r1, r3 800c43a: 89bb ldrh r3, [r7, #12] 800c43c: 3302 adds r3, #2 800c43e: 687a ldr r2, [r7, #4] 800c440: 4413 add r3, r2 800c442: b2ca uxtb r2, r1 800c444: 701a strb r2, [r3, #0] return total_len; 800c446: 8afb ldrh r3, [r7, #22] } 800c448: 4618 mov r0, r3 800c44a: 3718 adds r7, #24 800c44c: 46bd mov sp, r7 800c44e: bd80 pop {r7, pc} 0800c450 : static void CCS_SendPacket(uint8_t cmd, const void* payload, uint16_t payload_len) { 800c450: b580 push {r7, lr} 800c452: b086 sub sp, #24 800c454: af02 add r7, sp, #8 800c456: 4603 mov r3, r0 800c458: 6039 str r1, [r7, #0] 800c45a: 71fb strb r3, [r7, #7] 800c45c: 4613 mov r3, r2 800c45e: 80bb strh r3, [r7, #4] uint16_t len = CCS_BuildPacket(cmd, payload, payload_len, tx_buffer, sizeof(tx_buffer)); 800c460: 88ba ldrh r2, [r7, #4] 800c462: 79f8 ldrb r0, [r7, #7] 800c464: f44f 7380 mov.w r3, #256 @ 0x100 800c468: 9300 str r3, [sp, #0] 800c46a: 4b19 ldr r3, [pc, #100] @ (800c4d0 ) 800c46c: 6839 ldr r1, [r7, #0] 800c46e: f7ff ffaf bl 800c3d0 800c472: 4603 mov r3, r0 800c474: 81fb strh r3, [r7, #14] if (len > 0) { 800c476: 89fb ldrh r3, [r7, #14] 800c478: 2b00 cmp r3, #0 800c47a: d01f beq.n 800c4bc if (uart3_tx_busy) { 800c47c: 4b15 ldr r3, [pc, #84] @ (800c4d4 ) 800c47e: 781b ldrb r3, [r3, #0] 800c480: 2b00 cmp r3, #0 800c482: d009 beq.n 800c498 memcpy(tx_pending_buffer, tx_buffer, len); 800c484: 89fb ldrh r3, [r7, #14] 800c486: 461a mov r2, r3 800c488: 4911 ldr r1, [pc, #68] @ (800c4d0 ) 800c48a: 4813 ldr r0, [pc, #76] @ (800c4d8 ) 800c48c: f008 fc24 bl 8014cd8 tx_pending_len = len; 800c490: 4a12 ldr r2, [pc, #72] @ (800c4dc ) 800c492: 89fb ldrh r3, [r7, #14] 800c494: 8013 strh r3, [r2, #0] 800c496: e011 b.n 800c4bc } else { uart3_tx_busy = 1; 800c498: 4b0e ldr r3, [pc, #56] @ (800c4d4 ) 800c49a: 2201 movs r2, #1 800c49c: 701a strb r2, [r3, #0] if (HAL_UART_Transmit_DMA(&huart3, tx_buffer, len) != HAL_OK) { 800c49e: 89fb ldrh r3, [r7, #14] 800c4a0: 461a mov r2, r3 800c4a2: 490b ldr r1, [pc, #44] @ (800c4d0 ) 800c4a4: 480e ldr r0, [pc, #56] @ (800c4e0 ) 800c4a6: f006 fd11 bl 8012ecc 800c4aa: 4603 mov r3, r0 800c4ac: 2b00 cmp r3, #0 800c4ae: d005 beq.n 800c4bc uart3_tx_busy = 0; 800c4b0: 4b08 ldr r3, [pc, #32] @ (800c4d4 ) 800c4b2: 2200 movs r2, #0 800c4b4: 701a strb r2, [r3, #0] CCS_LogUart3Error("UART3 TX DMA start failed"); 800c4b6: 480b ldr r0, [pc, #44] @ (800c4e4 ) 800c4b8: f000 fa5a bl 800c970 } } } last_cmd_sent = HAL_GetTick(); 800c4bc: f001 ff0a bl 800e2d4 800c4c0: 4603 mov r3, r0 800c4c2: 4a09 ldr r2, [pc, #36] @ (800c4e8 ) 800c4c4: 6013 str r3, [r2, #0] } 800c4c6: bf00 nop 800c4c8: 3710 adds r7, #16 800c4ca: 46bd mov sp, r7 800c4cc: bd80 pop {r7, pc} 800c4ce: bf00 nop 800c4d0: 20000aac .word 0x20000aac 800c4d4: 20000cae .word 0x20000cae 800c4d8: 20000bac .word 0x20000bac 800c4dc: 20000cac .word 0x20000cac 800c4e0: 20001330 .word 0x20001330 800c4e4: 08017450 .word 0x08017450 800c4e8: 200009a0 .word 0x200009a0 0800c4ec : static void CCS_SendResetReason(void) { 800c4ec: b580 push {r7, lr} 800c4ee: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_RESET, NULL, 0); 800c4f0: 2200 movs r2, #0 800c4f2: 2100 movs r1, #0 800c4f4: 2052 movs r0, #82 @ 0x52 800c4f6: f7ff ffab bl 800c450 } 800c4fa: bf00 nop 800c4fc: bd80 pop {r7, pc} 800c4fe: bf00 nop 0800c500 : void CCS_SendEmergencyStop(void) { 800c500: b580 push {r7, lr} 800c502: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_ESTOP, NULL, 0); 800c504: 2200 movs r2, #0 800c506: 2100 movs r1, #0 800c508: 2053 movs r0, #83 @ 0x53 800c50a: f7ff ffa1 bl 800c450 } 800c50e: bf00 nop 800c510: bd80 pop {r7, pc} 800c512: bf00 nop 0800c514 : void CCS_SendStart(void) { CCS_SendPacket(CMD_M2E_START, NULL, 0); } static void CCS_CalculateEnergy(void) { 800c514: b580 push {r7, lr} 800c516: b082 sub sp, #8 800c518: af00 add r7, sp, #0 static uint32_t lastTick = 0; uint32_t currentTick = HAL_GetTick(); 800c51a: f001 fedb bl 800e2d4 800c51e: 6078 str r0, [r7, #4] uint32_t elapsedTimeMs = currentTick - lastTick; 800c520: 4b1e ldr r3, [pc, #120] @ (800c59c ) 800c522: 681b ldr r3, [r3, #0] 800c524: 687a ldr r2, [r7, #4] 800c526: 1ad3 subs r3, r2, r3 800c528: 603b str r3, [r7, #0] lastTick = currentTick; 800c52a: 4a1c ldr r2, [pc, #112] @ (800c59c ) 800c52c: 687b ldr r3, [r7, #4] 800c52e: 6013 str r3, [r2, #0] CCS_Power = CONN.MeasuredVoltage * CONN.MeasuredCurrent / 10; 800c530: 4b1b ldr r3, [pc, #108] @ (800c5a0 ) 800c532: f8b3 3013 ldrh.w r3, [r3, #19] 800c536: b29b uxth r3, r3 800c538: 461a mov r2, r3 800c53a: 4b19 ldr r3, [pc, #100] @ (800c5a0 ) 800c53c: f8b3 3015 ldrh.w r3, [r3, #21] 800c540: b29b uxth r3, r3 800c542: fb02 f303 mul.w r3, r2, r3 800c546: 4a17 ldr r2, [pc, #92] @ (800c5a4 ) 800c548: fb82 1203 smull r1, r2, r2, r3 800c54c: 1092 asrs r2, r2, #2 800c54e: 17db asrs r3, r3, #31 800c550: 1ad3 subs r3, r2, r3 800c552: 461a mov r2, r3 800c554: 4b14 ldr r3, [pc, #80] @ (800c5a8 ) 800c556: 601a str r2, [r3, #0] CCS_EnergyWs += (CCS_Power * elapsedTimeMs) / 1000; 800c558: 4b13 ldr r3, [pc, #76] @ (800c5a8 ) 800c55a: 681b ldr r3, [r3, #0] 800c55c: 683a ldr r2, [r7, #0] 800c55e: fb02 f303 mul.w r3, r2, r3 800c562: 4a12 ldr r2, [pc, #72] @ (800c5ac ) 800c564: fba2 2303 umull r2, r3, r2, r3 800c568: 099a lsrs r2, r3, #6 800c56a: 4b11 ldr r3, [pc, #68] @ (800c5b0 ) 800c56c: 681b ldr r3, [r3, #0] 800c56e: 4413 add r3, r2 800c570: 4a0f ldr r2, [pc, #60] @ (800c5b0 ) 800c572: 6013 str r3, [r2, #0] if(CCS_EvseState == Unplugged) { 800c574: 4b0f ldr r3, [pc, #60] @ (800c5b4 ) 800c576: 781b ldrb r3, [r3, #0] 800c578: 2b01 cmp r3, #1 800c57a: d102 bne.n 800c582 CCS_EnergyWs = 0; 800c57c: 4b0c ldr r3, [pc, #48] @ (800c5b0 ) 800c57e: 2200 movs r2, #0 800c580: 601a str r2, [r3, #0] } CCS_Energy = CCS_EnergyWs / 3600; 800c582: 4b0b ldr r3, [pc, #44] @ (800c5b0 ) 800c584: 681b ldr r3, [r3, #0] 800c586: 4a0c ldr r2, [pc, #48] @ (800c5b8 ) 800c588: fba2 2303 umull r2, r3, r2, r3 800c58c: 0adb lsrs r3, r3, #11 800c58e: 4a0b ldr r2, [pc, #44] @ (800c5bc ) 800c590: 6013 str r3, [r2, #0] } 800c592: bf00 nop 800c594: 3708 adds r7, #8 800c596: 46bd mov sp, r7 800c598: bd80 pop {r7, pc} 800c59a: bf00 nop 800c59c: 20000d28 .word 0x20000d28 800c5a0: 200003b0 .word 0x200003b0 800c5a4: 66666667 .word 0x66666667 800c5a8: 20000994 .word 0x20000994 800c5ac: 10624dd3 .word 0x10624dd3 800c5b0: 20000998 .word 0x20000998 800c5b4: 20000d10 .word 0x20000d10 800c5b8: 91a2b3c5 .word 0x91a2b3c5 800c5bc: 2000099c .word 0x2000099c 0800c5c0 : static void send_state(void) { 800c5c0: b580 push {r7, lr} 800c5c2: af00 add r7, sp, #0 CCS_CalculateEnergy(); 800c5c4: f7ff ffa6 bl 800c514 CCS_State.DutyCycle = CP_GetDuty(); 800c5c8: f7fd fd7a bl 800a0c0 800c5cc: 4603 mov r3, r0 800c5ce: 461a mov r2, r3 800c5d0: 4b2e ldr r3, [pc, #184] @ (800c68c ) 800c5d2: 701a strb r2, [r3, #0] CCS_State.OutputEnabled = PSU0.CONT_enabled; 800c5d4: 4b2e ldr r3, [pc, #184] @ (800c690 ) 800c5d6: 7ada ldrb r2, [r3, #11] 800c5d8: 4b2c ldr r3, [pc, #176] @ (800c68c ) 800c5da: 705a strb r2, [r3, #1] CCS_State.MeasuredVoltage = (uint16_t)CONN.MeasuredVoltage; 800c5dc: 4b2d ldr r3, [pc, #180] @ (800c694 ) 800c5de: f8b3 3013 ldrh.w r3, [r3, #19] 800c5e2: b29a uxth r2, r3 800c5e4: 4b29 ldr r3, [pc, #164] @ (800c68c ) 800c5e6: 805a strh r2, [r3, #2] if (fake_500_voltage_mode) { 800c5e8: 4b2b ldr r3, [pc, #172] @ (800c698 ) 800c5ea: 781b ldrb r3, [r3, #0] 800c5ec: 2b00 cmp r3, #0 800c5ee: d003 beq.n 800c5f8 CCS_State.MeasuredVoltage = FAKE_EVREQ_VOLTAGE_V; 800c5f0: 4b26 ldr r3, [pc, #152] @ (800c68c ) 800c5f2: f44f 72fa mov.w r2, #500 @ 0x1f4 800c5f6: 805a strh r2, [r3, #2] } CCS_State.MeasuredCurrent = (uint16_t)CONN.MeasuredCurrent; 800c5f8: 4b26 ldr r3, [pc, #152] @ (800c694 ) 800c5fa: f8b3 3015 ldrh.w r3, [r3, #21] 800c5fe: b29a uxth r2, r3 800c600: 4b22 ldr r3, [pc, #136] @ (800c68c ) 800c602: 809a strh r2, [r3, #4] CCS_State.Power = CCS_Power; 800c604: 4b25 ldr r3, [pc, #148] @ (800c69c ) 800c606: 681b ldr r3, [r3, #0] 800c608: 4a20 ldr r2, [pc, #128] @ (800c68c ) 800c60a: f8c2 3006 str.w r3, [r2, #6] CCS_State.Energy = CCS_Energy; 800c60e: 4b24 ldr r3, [pc, #144] @ (800c6a0 ) 800c610: 681b ldr r3, [r3, #0] 800c612: 4a1e ldr r2, [pc, #120] @ (800c68c ) 800c614: f8c2 300a str.w r3, [r2, #10] if(CCS_ConnectorState == CCS_CONNECTED){ 800c618: 4b22 ldr r3, [pc, #136] @ (800c6a4 ) 800c61a: 781b ldrb r3, [r3, #0] 800c61c: 2b04 cmp r3, #4 800c61e: d104 bne.n 800c62a CCS_State.CpState = cp_state_buffer; 800c620: 4b21 ldr r3, [pc, #132] @ (800c6a8 ) 800c622: 781a ldrb r2, [r3, #0] 800c624: 4b19 ldr r3, [pc, #100] @ (800c68c ) 800c626: 74da strb r2, [r3, #19] 800c628: e002 b.n 800c630 } else { CCS_State.CpState = EV_STATE_A_IDLE; 800c62a: 4b18 ldr r3, [pc, #96] @ (800c68c ) 800c62c: 2200 movs r2, #0 800c62e: 74da strb r2, [r3, #19] } CCS_State.MaxVoltage = CCS_MaxLoad.maxVoltage; 800c630: 4b1e ldr r3, [pc, #120] @ (800c6ac ) 800c632: 881a ldrh r2, [r3, #0] 800c634: 4b15 ldr r3, [pc, #84] @ (800c68c ) 800c636: 829a strh r2, [r3, #20] CCS_State.MinVoltage = CCS_MaxLoad.minVoltage; 800c638: 4b1c ldr r3, [pc, #112] @ (800c6ac ) 800c63a: 885a ldrh r2, [r3, #2] 800c63c: 4b13 ldr r3, [pc, #76] @ (800c68c ) 800c63e: 82da strh r2, [r3, #22] CCS_State.MaxCurrent = CCS_MaxLoad.maxCurrent; 800c640: 4b1a ldr r3, [pc, #104] @ (800c6ac ) 800c642: 889a ldrh r2, [r3, #4] 800c644: 4b11 ldr r3, [pc, #68] @ (800c68c ) 800c646: 831a strh r2, [r3, #24] CCS_State.MinCurrent = CCS_MaxLoad.minCurrent; 800c648: 4b18 ldr r3, [pc, #96] @ (800c6ac ) 800c64a: 88da ldrh r2, [r3, #6] 800c64c: 4b0f ldr r3, [pc, #60] @ (800c68c ) 800c64e: 835a strh r2, [r3, #26] CCS_State.MaxPower = CCS_MaxLoad.maxPower; 800c650: 4b16 ldr r3, [pc, #88] @ (800c6ac ) 800c652: 689b ldr r3, [r3, #8] 800c654: 4a0d ldr r2, [pc, #52] @ (800c68c ) 800c656: 61d3 str r3, [r2, #28] CCS_State.IsolationValid = isolation_enable; 800c658: 4b15 ldr r3, [pc, #84] @ (800c6b0 ) 800c65a: 781a ldrb r2, [r3, #0] 800c65c: 4b0b ldr r3, [pc, #44] @ (800c68c ) 800c65e: 749a strb r2, [r3, #18] CCS_State.IsolationResistance = 900000; 800c660: 4a0a ldr r2, [pc, #40] @ (800c68c ) 800c662: 2300 movs r3, #0 800c664: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800c668: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800c66c: f443 433b orr.w r3, r3, #47872 @ 0xbb00 800c670: f043 03a0 orr.w r3, r3, #160 @ 0xa0 800c674: 81d3 strh r3, [r2, #14] 800c676: 2300 movs r3, #0 800c678: f043 030d orr.w r3, r3, #13 800c67c: 8213 strh r3, [r2, #16] CCS_SendPacket(CMD_M2E_STATE, &CCS_State, sizeof(CCS_State)); 800c67e: 2220 movs r2, #32 800c680: 4902 ldr r1, [pc, #8] @ (800c68c ) 800c682: 2050 movs r0, #80 @ 0x50 800c684: f7ff fee4 bl 800c450 } 800c688: bf00 nop 800c68a: bd80 pop {r7, pc} 800c68c: 20000cc4 .word 0x20000cc4 800c690: 20000904 .word 0x20000904 800c694: 200003b0 .word 0x200003b0 800c698: 20000cb8 .word 0x20000cb8 800c69c: 20000994 .word 0x20000994 800c6a0: 2000099c .word 0x2000099c 800c6a4: 20000d11 .word 0x20000d11 800c6a8: 20000005 .word 0x20000005 800c6ac: 20000988 .word 0x20000988 800c6b0: 20000cb2 .word 0x20000cb2 0800c6b4 : ISR_FAST static uint16_t expected_payload_len(uint8_t cmd) { switch (cmd) { 800c6b4: 3840 subs r0, #64 @ 0x40 800c6b6: b2c0 uxtb r0, r0 800c6b8: 2809 cmp r0, #9 800c6ba: bf9a itte ls 800c6bc: 4b02 ldrls r3, [pc, #8] @ (800c6c8 ) 800c6be: f833 0010 ldrhls.w r0, [r3, r0, lsl #1] ISR_FAST static uint16_t expected_payload_len(uint8_t cmd) { 800c6c2: f64f 70ff movwhi r0, #65535 @ 0xffff case CMD_E2M_EV_INFO: return sizeof(CCS_EvInfo_t); case CMD_E2M_EVSE_STATE: return sizeof(CONN_State_t); case CMD_E2M_KEEP_ALIVE: return 0; default: return 0xFFFFu; } } 800c6c6: 4770 bx lr 800c6c8: 08017880 .word 0x08017880 0800c6cc : ISR_FAST static void apply_command(uint8_t cmd, const uint8_t* payload, uint16_t payload_len) { 800c6cc: b5f8 push {r3, r4, r5, r6, r7, lr} 800c6ce: 4604 mov r4, r0 800c6d0: 460d mov r5, r1 (void)payload_len; last_host_seen = HAL_GetTick(); 800c6d2: f001 fdff bl 800e2d4 everest_timed_out = 0; 800c6d6: 2300 movs r3, #0 800c6d8: 4a42 ldr r2, [pc, #264] @ (800c7e4 ) last_host_seen = HAL_GetTick(); 800c6da: 4e43 ldr r6, [pc, #268] @ (800c7e8 ) everest_timed_out = 0; 800c6dc: 7013 strb r3, [r2, #0] everest_timeout_warn_latched = 0; 800c6de: 4a43 ldr r2, [pc, #268] @ (800c7ec ) last_host_seen = HAL_GetTick(); 800c6e0: 6030 str r0, [r6, #0] everest_timeout_warn_latched = 0; 800c6e2: 7013 strb r3, [r2, #0] everest_timeout_stop_latched = 0; 800c6e4: 4a42 ldr r2, [pc, #264] @ (800c7f0 ) 800c6e6: 7013 strb r3, [r2, #0] switch (cmd) { 800c6e8: f1a4 0340 sub.w r3, r4, #64 @ 0x40 800c6ec: 2b09 cmp r3, #9 800c6ee: d871 bhi.n 800c7d4 800c6f0: e8df f003 tbb [pc, r3] 800c6f4: 4e5b1409 .word 0x4e5b1409 800c6f8: 2e2a1b55 .word 0x2e2a1b55 800c6fc: 054a .short 0x054a (void)payload; CP_SetDuty(pwm_duty_percent); break; } case CMD_E2M_KEEP_ALIVE: { last_host_seen = HAL_GetTick(); 800c6fe: f001 fde9 bl 800e2d4 800c702: 6030 str r0, [r6, #0] log_printf(LOG_WARN, "UART3 RX warn: cmd 0x%02x CRC/len OK but no switch case (expected_payload vs apply_command)\n", cmd); break; } } 800c704: bdf8 pop {r3, r4, r5, r6, r7, pc} if (duty > 100) duty = 100; 800c706: 7828 ldrb r0, [r5, #0] if (CONN.connControl != CMD_FORCE_UNLOCK) { 800c708: 4b3a ldr r3, [pc, #232] @ (800c7f4 ) if (duty > 100) duty = 100; 800c70a: 2864 cmp r0, #100 @ 0x64 800c70c: bf28 it cs 800c70e: 2064 movcs r0, #100 @ 0x64 if (CONN.connControl != CMD_FORCE_UNLOCK) { 800c710: 781b ldrb r3, [r3, #0] pwm_duty_percent = duty; 800c712: 4a39 ldr r2, [pc, #228] @ (800c7f8 ) if (CONN.connControl != CMD_FORCE_UNLOCK) { 800c714: 2b03 cmp r3, #3 pwm_duty_percent = duty; 800c716: 7010 strb r0, [r2, #0] if (CONN.connControl != CMD_FORCE_UNLOCK) { 800c718: d143 bne.n 800c7a2 } 800c71a: bdf8 pop {r3, r4, r5, r6, r7, pc} ev_enable_output = (p->enable_output != 0); 800c71c: 782b ldrb r3, [r5, #0] 800c71e: 4a37 ldr r2, [pc, #220] @ (800c7fc ) 800c720: 3b00 subs r3, #0 800c722: bf18 it ne 800c724: 2301 movne r3, #1 800c726: 7013 strb r3, [r2, #0] } 800c728: bdf8 pop {r3, r4, r5, r6, r7, pc} if (p->voltage_V == FAKE_EVREQ_VOLTAGE_V) { 800c72a: 882b ldrh r3, [r5, #0] 800c72c: b29a uxth r2, r3 800c72e: f5b2 7ffa cmp.w r2, #500 @ 0x1f4 800c732: d043 beq.n 800c7bc fake_500_voltage_mode = 0u; 800c734: 2000 movs r0, #0 CONN.RequestedVoltage = p->voltage_V; 800c736: 4a2f ldr r2, [pc, #188] @ (800c7f4 ) fake_500_voltage_mode = 0u; 800c738: 4931 ldr r1, [pc, #196] @ (800c800 ) CONN.RequestedVoltage = p->voltage_V; 800c73a: f8a2 300f strh.w r3, [r2, #15] fake_500_voltage_mode = 0u; 800c73e: 7008 strb r0, [r1, #0] CONN.WantedCurrent = p->current_0p1A; 800c740: 886b ldrh r3, [r5, #2] 800c742: f8a2 301b strh.w r3, [r2, #27] } 800c746: bdf8 pop {r3, r4, r5, r6, r7, pc} isolation_enable = p->command; 800c748: 782a ldrb r2, [r5, #0] 800c74a: 4b2e ldr r3, [pc, #184] @ (800c804 ) 800c74c: 701a strb r2, [r3, #0] } 800c74e: bdf8 pop {r3, r4, r5, r6, r7, pc} memcpy(&CCS_EvInfo, payload, sizeof(CCS_EvInfo_t)); 800c750: 4f2d ldr r7, [pc, #180] @ (800c808 ) 800c752: 462c mov r4, r5 800c754: 463e mov r6, r7 800c756: f105 0c20 add.w ip, r5, #32 800c75a: 4635 mov r5, r6 800c75c: 6820 ldr r0, [r4, #0] 800c75e: 6861 ldr r1, [r4, #4] 800c760: 68a2 ldr r2, [r4, #8] 800c762: 68e3 ldr r3, [r4, #12] 800c764: 3410 adds r4, #16 800c766: 4564 cmp r4, ip 800c768: c50f stmia r5!, {r0, r1, r2, r3} 800c76a: f106 0610 add.w r6, r6, #16 800c76e: d1f4 bne.n 800c75a 800c770: 6861 ldr r1, [r4, #4] 800c772: 68a2 ldr r2, [r4, #8] 800c774: 6820 ldr r0, [r4, #0] 800c776: c607 stmia r6!, {r0, r1, r2} CONN.SOC = (uint8_t)(CCS_EvInfo.soc / 10); 800c778: 4a24 ldr r2, [pc, #144] @ (800c80c ) 800c77a: 887b ldrh r3, [r7, #2] 800c77c: 491d ldr r1, [pc, #116] @ (800c7f4 ) 800c77e: fba2 2303 umull r2, r3, r2, r3 800c782: 08db lsrs r3, r3, #3 800c784: 708b strb r3, [r1, #2] } 800c786: bdf8 pop {r3, r4, r5, r6, r7, pc} CCS_EvseState = (CONN_State_t)payload[0]; 800c788: 782a ldrb r2, [r5, #0] 800c78a: 4b21 ldr r3, [pc, #132] @ (800c810 ) 800c78c: 701a strb r2, [r3, #0] } 800c78e: bdf8 pop {r3, r4, r5, r6, r7, pc} enabled = (p->enable != 0); 800c790: 782b ldrb r3, [r5, #0] 800c792: 4a20 ldr r2, [pc, #128] @ (800c814 ) 800c794: 3b00 subs r3, #0 800c796: bf18 it ne 800c798: 2301 movne r3, #1 800c79a: 7013 strb r3, [r2, #0] } 800c79c: bdf8 pop {r3, r4, r5, r6, r7, pc} CP_SetDuty(pwm_duty_percent); 800c79e: 4b16 ldr r3, [pc, #88] @ (800c7f8 ) 800c7a0: 7818 ldrb r0, [r3, #0] } 800c7a2: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} CP_SetDuty(pwm_duty_percent); 800c7a6: f7fd bc63 b.w 800a070 if (p->reset) { 800c7aa: 782b ldrb r3, [r5, #0] 800c7ac: 2b00 cmp r3, #0 800c7ae: d0a9 beq.n 800c704 } 800c7b0: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} log_printf(LOG_WARN, "Everest reset command\n"); 800c7b4: 2005 movs r0, #5 800c7b6: 4918 ldr r1, [pc, #96] @ (800c818 ) 800c7b8: f7fd be9c b.w 800a4f4 fake_500_voltage_mode = 1u; 800c7bc: 2201 movs r2, #1 CONN.RequestedVoltage = FAKE_PSU_VOLTAGE_V; 800c7be: 2100 movs r1, #0 800c7c0: 242c movs r4, #44 @ 0x2c CONN.WantedCurrent = FAKE_PSU_CURRENT_0P1A; 800c7c2: 200a movs r0, #10 fake_500_voltage_mode = 1u; 800c7c4: 4d0e ldr r5, [pc, #56] @ (800c800 ) CONN.RequestedVoltage = FAKE_PSU_VOLTAGE_V; 800c7c6: 4b0b ldr r3, [pc, #44] @ (800c7f4 ) fake_500_voltage_mode = 1u; 800c7c8: 702a strb r2, [r5, #0] CONN.RequestedVoltage = FAKE_PSU_VOLTAGE_V; 800c7ca: 741a strb r2, [r3, #16] 800c7cc: 73dc strb r4, [r3, #15] CONN.WantedCurrent = FAKE_PSU_CURRENT_0P1A; 800c7ce: 76d8 strb r0, [r3, #27] 800c7d0: 7719 strb r1, [r3, #28] } 800c7d2: bdf8 pop {r3, r4, r5, r6, r7, pc} log_printf(LOG_WARN, 800c7d4: 4622 mov r2, r4 } 800c7d6: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} log_printf(LOG_WARN, 800c7da: 2005 movs r0, #5 800c7dc: 490f ldr r1, [pc, #60] @ (800c81c ) 800c7de: f7fd be89 b.w 800a4f4 800c7e2: bf00 nop 800c7e4: 20000cb9 .word 0x20000cb9 800c7e8: 20000cb4 .word 0x20000cb4 800c7ec: 20000cba .word 0x20000cba 800c7f0: 20000cbb .word 0x20000cbb 800c7f4: 200003b0 .word 0x200003b0 800c7f8: 2000006a .word 0x2000006a 800c7fc: 200009a9 .word 0x200009a9 800c800: 20000cb8 .word 0x20000cb8 800c804: 20000cb2 .word 0x20000cb2 800c808: 20000ce4 .word 0x20000ce4 800c80c: cccccccd .word 0xcccccccd 800c810: 20000d10 .word 0x20000d10 800c814: 20000cb1 .word 0x20000cb1 800c818: 0801746c .word 0x0801746c 800c81c: 08017484 .word 0x08017484 0800c820 : ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len) { 800c820: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} if (packet_len < 3u) { 800c824: 2902 cmp r1, #2 ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len) { 800c826: 460c mov r4, r1 800c828: 4605 mov r5, r0 800c82a: b084 sub sp, #16 if (packet_len < 3u) { 800c82c: d930 bls.n 800c890 uint8_t cmd = packet[0]; uint16_t payload_len = (uint16_t)(packet_len - 3u); uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | (uint16_t)packet[packet_len - 1u] << 8; 800c82e: 1843 adds r3, r0, r1 uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c830: f813 2c01 ldrb.w r2, [r3, #-1] 800c834: f813 7c02 ldrb.w r7, [r3, #-2] uint16_t payload_len = (uint16_t)(packet_len - 3u); 800c838: 1ece subs r6, r1, #3 uint16_t calculated_crc = crc16_ibm(packet, (uint16_t)(1u + payload_len)); 800c83a: 3902 subs r1, #2 800c83c: b289 uxth r1, r1 uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c83e: ea47 2702 orr.w r7, r7, r2, lsl #8 uint8_t cmd = packet[0]; 800c842: f890 8000 ldrb.w r8, [r0] uint16_t calculated_crc = crc16_ibm(packet, (uint16_t)(1u + payload_len)); 800c846: f7ff fd7f bl 800c348 if (received_crc != calculated_crc) { 800c84a: 4287 cmp r7, r0 uint16_t payload_len = (uint16_t)(packet_len - 3u); 800c84c: b2b6 uxth r6, r6 if (received_crc != calculated_crc) { 800c84e: d112 bne.n 800c876 cmd, (unsigned)packet_len, (unsigned)payload_len, (unsigned)received_crc, (unsigned)calculated_crc); return 0; } uint16_t expected_len = expected_payload_len(cmd); 800c850: 4640 mov r0, r8 800c852: f7ff ff2f bl 800c6b4 if (expected_len == 0xFFFFu) { 800c856: f64f 72ff movw r2, #65535 @ 0xffff 800c85a: 4290 cmp r0, r2 800c85c: d03a beq.n 800c8d4 log_printf(LOG_WARN, "UART3 RX drop: unknown_cmd cmd=0x%02x total_len=%u payload_len=%u\n", cmd, (unsigned)packet_len, (unsigned)payload_len); return 0; } if (expected_len != payload_len) { 800c85e: 4286 cmp r6, r0 800c860: d12a bne.n 800c8b8 cmd, (unsigned)expected_len, (unsigned)payload_len, (unsigned)packet_len); return 0; } if (payload_len > 0) { apply_command(cmd, &packet[1], payload_len); 800c862: 4632 mov r2, r6 if (payload_len > 0) { 800c864: b9fe cbnz r6, 800c8a6 } else { apply_command(cmd, NULL, 0); 800c866: 4631 mov r1, r6 800c868: 4640 mov r0, r8 800c86a: f7ff ff2f bl 800c6cc } return 1; 800c86e: 2001 movs r0, #1 } 800c870: b004 add sp, #16 800c872: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} log_printf(LOG_ERR, 800c876: 9002 str r0, [sp, #8] 800c878: 4623 mov r3, r4 800c87a: 4642 mov r2, r8 800c87c: 2004 movs r0, #4 800c87e: e9cd 6700 strd r6, r7, [sp] 800c882: 4918 ldr r1, [pc, #96] @ (800c8e4 ) 800c884: f7fd fe36 bl 800a4f4 return 0; 800c888: 2000 movs r0, #0 } 800c88a: b004 add sp, #16 800c88c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} if (packet_len == 0u) { 800c890: b1d9 cbz r1, 800c8ca } else if (packet_len == 1u) { 800c892: 2901 cmp r1, #1 log_printf(LOG_WARN, "UART3 RX drop: too_short len=1 b0=0x%02x\n", packet[0]); 800c894: 7802 ldrb r2, [r0, #0] 800c896: f04f 0005 mov.w r0, #5 } else if (packet_len == 1u) { 800c89a: d009 beq.n 800c8b0 log_printf(LOG_WARN, "UART3 RX drop: too_short len=2 b0=0x%02x b1=0x%02x\n", 800c89c: 786b ldrb r3, [r5, #1] 800c89e: 4912 ldr r1, [pc, #72] @ (800c8e8 ) 800c8a0: f7fd fe28 bl 800a4f4 800c8a4: e7f0 b.n 800c888 apply_command(cmd, &packet[1], payload_len); 800c8a6: 4640 mov r0, r8 800c8a8: 1c69 adds r1, r5, #1 800c8aa: f7ff ff0f bl 800c6cc 800c8ae: e7de b.n 800c86e log_printf(LOG_WARN, "UART3 RX drop: too_short len=1 b0=0x%02x\n", packet[0]); 800c8b0: 490e ldr r1, [pc, #56] @ (800c8ec ) 800c8b2: f7fd fe1f bl 800a4f4 800c8b6: e7e7 b.n 800c888 log_printf(LOG_ERR, 800c8b8: 4603 mov r3, r0 800c8ba: 4642 mov r2, r8 800c8bc: e9cd 6400 strd r6, r4, [sp] 800c8c0: 490b ldr r1, [pc, #44] @ (800c8f0 ) 800c8c2: 2004 movs r0, #4 800c8c4: f7fd fe16 bl 800a4f4 return 0; 800c8c8: e7de b.n 800c888 log_printf(LOG_WARN, "UART3 RX drop: too_short len=0 (empty chunk)\n"); 800c8ca: 490a ldr r1, [pc, #40] @ (800c8f4 ) 800c8cc: 2005 movs r0, #5 800c8ce: f7fd fe11 bl 800a4f4 800c8d2: e7d9 b.n 800c888 log_printf(LOG_WARN, 800c8d4: 4623 mov r3, r4 800c8d6: 4642 mov r2, r8 800c8d8: 4907 ldr r1, [pc, #28] @ (800c8f8 ) 800c8da: 9600 str r6, [sp, #0] 800c8dc: 2005 movs r0, #5 800c8de: f7fd fe09 bl 800a4f4 return 0; 800c8e2: e7d1 b.n 800c888 800c8e4: 08017574 .word 0x08017574 800c8e8: 08017540 .word 0x08017540 800c8ec: 08017514 .word 0x08017514 800c8f0: 0801761c .word 0x0801761c 800c8f4: 080174e4 .word 0x080174e4 800c8f8: 080175d8 .word 0x080175d8 0800c8fc : static void CCS_UART3_Watchdog(void) { 800c8fc: b580 push {r7, lr} 800c8fe: b082 sub sp, #8 800c900: af00 add r7, sp, #0 const int32_t since_last_packet = (int32_t)(HAL_GetTick() - uart3_last_packet_tick); 800c902: f001 fce7 bl 800e2d4 800c906: 4602 mov r2, r0 800c908: 4b14 ldr r3, [pc, #80] @ (800c95c ) 800c90a: 681b ldr r3, [r3, #0] 800c90c: 1ad3 subs r3, r2, r3 800c90e: 607b str r3, [r7, #4] const int32_t since_last_reinit = (int32_t)(HAL_GetTick() - uart3_last_reinit_tick); 800c910: f001 fce0 bl 800e2d4 800c914: 4602 mov r2, r0 800c916: 4b12 ldr r3, [pc, #72] @ (800c960 ) 800c918: 681b ldr r3, [r3, #0] 800c91a: 1ad3 subs r3, r2, r3 800c91c: 603b str r3, [r7, #0] if ((since_last_packet >= (int32_t)UART3_REINIT_TIMEOUT_MS) && 800c91e: 687b ldr r3, [r7, #4] 800c920: f240 52db movw r2, #1499 @ 0x5db 800c924: 4293 cmp r3, r2 800c926: dd15 ble.n 800c954 800c928: 683b ldr r3, [r7, #0] 800c92a: f240 52db movw r2, #1499 @ 0x5db 800c92e: 4293 cmp r3, r2 800c930: dd10 ble.n 800c954 (since_last_reinit >= (int32_t)UART3_REINIT_TIMEOUT_MS) && (huart3.RxState == HAL_UART_STATE_READY)) { 800c932: 4b0c ldr r3, [pc, #48] @ (800c964 ) 800c934: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800c938: b2db uxtb r3, r3 (since_last_reinit >= (int32_t)UART3_REINIT_TIMEOUT_MS) && 800c93a: 2b20 cmp r3, #32 800c93c: d10a bne.n 800c954 uart3_arm_rx_or_log("Watchdog"); 800c93e: 480a ldr r0, [pc, #40] @ (800c968 ) 800c940: f7ff f91a bl 800bb78 CCS_LogUart3Error("UART3 watchdog rearm"); 800c944: 4809 ldr r0, [pc, #36] @ (800c96c ) 800c946: f000 f813 bl 800c970 uart3_last_reinit_tick = HAL_GetTick(); 800c94a: f001 fcc3 bl 800e2d4 800c94e: 4603 mov r3, r0 800c950: 4a03 ldr r2, [pc, #12] @ (800c960 ) 800c952: 6013 str r3, [r2, #0] } } 800c954: bf00 nop 800c956: 3708 adds r7, #8 800c958: 46bd mov sp, r7 800c95a: bd80 pop {r7, pc} 800c95c: 20000cbc .word 0x20000cbc 800c960: 20000cc0 .word 0x20000cc0 800c964: 20001330 .word 0x20001330 800c968: 08017674 .word 0x08017674 800c96c: 08017680 .word 0x08017680 0800c970 : static void CCS_LogUart3Error(const char *tag) { 800c970: b580 push {r7, lr} 800c972: b086 sub sp, #24 800c974: af04 add r7, sp, #16 800c976: 6078 str r0, [r7, #4] log_printf(LOG_ERR, "%s: err=0x%08lx g=%lu rx=%lu tx_busy=%u\n", tag, (unsigned long)HAL_UART_GetError(&huart3), 800c978: 480d ldr r0, [pc, #52] @ (800c9b0 ) 800c97a: f006 ff86 bl 801388a 800c97e: 4603 mov r3, r0 (unsigned long)huart3.gState, 800c980: 4a0b ldr r2, [pc, #44] @ (800c9b0 ) 800c982: f892 2041 ldrb.w r2, [r2, #65] @ 0x41 800c986: b2d2 uxtb r2, r2 log_printf(LOG_ERR, "%s: err=0x%08lx g=%lu rx=%lu tx_busy=%u\n", 800c988: 4611 mov r1, r2 (unsigned long)huart3.RxState, 800c98a: 4a09 ldr r2, [pc, #36] @ (800c9b0 ) 800c98c: f892 2042 ldrb.w r2, [r2, #66] @ 0x42 800c990: b2d2 uxtb r2, r2 log_printf(LOG_ERR, "%s: err=0x%08lx g=%lu rx=%lu tx_busy=%u\n", 800c992: 4610 mov r0, r2 800c994: 4a07 ldr r2, [pc, #28] @ (800c9b4 ) 800c996: 7812 ldrb r2, [r2, #0] 800c998: 9202 str r2, [sp, #8] 800c99a: 9001 str r0, [sp, #4] 800c99c: 9100 str r1, [sp, #0] 800c99e: 687a ldr r2, [r7, #4] 800c9a0: 4905 ldr r1, [pc, #20] @ (800c9b8 ) 800c9a2: 2004 movs r0, #4 800c9a4: f7fd fda6 bl 800a4f4 (unsigned)uart3_tx_busy); } 800c9a8: bf00 nop 800c9aa: 3708 adds r7, #8 800c9ac: 46bd mov sp, r7 800c9ae: bd80 pop {r7, pc} 800c9b0: 20001330 .word 0x20001330 800c9b4: 20000cae .word 0x20000cae 800c9b8: 08017698 .word 0x08017698 0800c9bc : .fw_version_major = 0, .fw_version_minor = 0, .fw_version_patch = 0, }; void ReadVersion(){ 800c9bc: b480 push {r7} 800c9be: af00 add r7, sp, #0 infoPacket.serialNumber = InfoBlock->serialNumber; 800c9c0: 4b0e ldr r3, [pc, #56] @ (800c9fc ) 800c9c2: 681b ldr r3, [r3, #0] 800c9c4: 681b ldr r3, [r3, #0] 800c9c6: b29a uxth r2, r3 800c9c8: 4b0d ldr r3, [pc, #52] @ (800ca00 ) 800c9ca: 801a strh r2, [r3, #0] infoPacket.boardVersion = InfoBlock->boardVersion; 800c9cc: 4b0b ldr r3, [pc, #44] @ (800c9fc ) 800c9ce: 681b ldr r3, [r3, #0] 800c9d0: 795a ldrb r2, [r3, #5] 800c9d2: 4b0b ldr r3, [pc, #44] @ (800ca00 ) 800c9d4: 709a strb r2, [r3, #2] infoPacket.stationType = InfoBlock->stationType; 800c9d6: 4b09 ldr r3, [pc, #36] @ (800c9fc ) 800c9d8: 681b ldr r3, [r3, #0] 800c9da: 791a ldrb r2, [r3, #4] 800c9dc: 4b08 ldr r3, [pc, #32] @ (800ca00 ) 800c9de: 70da strb r2, [r3, #3] infoPacket.fw_version_major = FW_VERSION_MAJOR; 800c9e0: 4b07 ldr r3, [pc, #28] @ (800ca00 ) 800c9e2: 2201 movs r2, #1 800c9e4: 809a strh r2, [r3, #4] infoPacket.fw_version_minor = FW_VERSION_MINOR; 800c9e6: 4b06 ldr r3, [pc, #24] @ (800ca00 ) 800c9e8: 2200 movs r2, #0 800c9ea: 80da strh r2, [r3, #6] infoPacket.fw_version_patch = FW_VERSION_PATCH; 800c9ec: 4b04 ldr r3, [pc, #16] @ (800ca00 ) 800c9ee: 2211 movs r2, #17 800c9f0: 811a strh r2, [r3, #8] } 800c9f2: bf00 nop 800c9f4: 46bd mov sp, r7 800c9f6: bc80 pop {r7} 800c9f8: 4770 bx lr 800c9fa: bf00 nop 800c9fc: 20000000 .word 0x20000000 800ca00: 200011b0 .word 0x200011b0 0800ca04 : // Внешняя функция обработки команд (определена в serial_handler.c) extern void SC_CommandHandler(ReceivedCommand_t* cmd); void SC_Init() { 800ca04: b580 push {r7, lr} 800ca06: af00 add r7, sp, #0 // Обнуляем структуру memset(&serial_control, 0, sizeof(SerialControl_t)); 800ca08: f44f 7204 mov.w r2, #528 @ 0x210 800ca0c: 2100 movs r1, #0 800ca0e: 480d ldr r0, [pc, #52] @ (800ca44 ) 800ca10: f008 f91a bl 8014c48 memset(&serial_iso, 0, sizeof(serial_iso)); 800ca14: f44f 7204 mov.w r2, #528 @ 0x210 800ca18: 2100 movs r1, #0 800ca1a: 480b ldr r0, [pc, #44] @ (800ca48 ) 800ca1c: f008 f914 bl 8014c48 sc_uart2_timed_out = 0; 800ca20: 4b0a ldr r3, [pc, #40] @ (800ca4c ) 800ca22: 2200 movs r2, #0 800ca24: 701a strb r2, [r3, #0] sc_uart2_last_packet_tick = HAL_GetTick(); 800ca26: f001 fc55 bl 800e2d4 800ca2a: 4603 mov r3, r0 800ca2c: 4a08 ldr r2, [pc, #32] @ (800ca50 ) 800ca2e: 6013 str r3, [r2, #0] sc_uart2_last_recover_tick = sc_uart2_last_packet_tick; 800ca30: 4b07 ldr r3, [pc, #28] @ (800ca50 ) 800ca32: 681b ldr r3, [r3, #0] 800ca34: 4a07 ldr r2, [pc, #28] @ (800ca54 ) 800ca36: 6013 str r3, [r2, #0] SC_ArmUart2RxDma(); 800ca38: f000 fa14 bl 800ce64 SC_ArmUart5RxDma(); 800ca3c: f000 fa36 bl 800ceac } 800ca40: bf00 nop 800ca42: bd80 pop {r7, pc} 800ca44: 20000d2c .word 0x20000d2c 800ca48: 20000f3c .word 0x20000f3c 800ca4c: 2000114d .word 0x2000114d 800ca50: 20001150 .word 0x20001150 800ca54: 20001154 .word 0x20001154 0800ca58 : void SC_Task() { 800ca58: b580 push {r7, lr} 800ca5a: af00 add r7, sp, #0 static uint32_t tick; if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800ca5c: f001 fc3a bl 800e2d4 800ca60: 4602 mov r2, r0 800ca62: 4b21 ldr r3, [pc, #132] @ (800cae8 ) 800ca64: 681b ldr r3, [r3, #0] 800ca66: 1ad3 subs r3, r2, r3 800ca68: 2b00 cmp r3, #0 800ca6a: dd3b ble.n 800cae4 tick = HAL_GetTick(); 800ca6c: f001 fc32 bl 800e2d4 800ca70: 4603 mov r3, r0 800ca72: 4a1d ldr r2, [pc, #116] @ (800cae8 ) 800ca74: 6013 str r3, [r2, #0] SC_UART2_Watchdog(); 800ca76: f000 f9ad bl 800cdd4 // Запуск приема в режиме DMA + idle SC_ArmUart2RxDma(); 800ca7a: f000 f9f3 bl 800ce64 SC_ArmUart5RxDma(); 800ca7e: f000 fa15 bl 800ceac // Проверка таймаута отправки пакета (больше 100 мс) if (huart2.gState == HAL_UART_STATE_BUSY_TX && serial_control.tx_tick != 0) { 800ca82: 4b1a ldr r3, [pc, #104] @ (800caec ) 800ca84: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800ca88: b2db uxtb r3, r3 800ca8a: 2b21 cmp r3, #33 @ 0x21 800ca8c: d114 bne.n 800cab8 800ca8e: 4b18 ldr r3, [pc, #96] @ (800caf0 ) 800ca90: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800ca94: 2b00 cmp r3, #0 800ca96: d00f beq.n 800cab8 if ((int32_t)(HAL_GetTick() - serial_control.tx_tick) > 100) { 800ca98: f001 fc1c bl 800e2d4 800ca9c: 4602 mov r2, r0 800ca9e: 4b14 ldr r3, [pc, #80] @ (800caf0 ) 800caa0: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800caa4: 1ad3 subs r3, r2, r3 800caa6: 2b64 cmp r3, #100 @ 0x64 800caa8: dd06 ble.n 800cab8 // Таймаут: принудительно сбрасываем передачу (void)HAL_UART_AbortTransmit(&huart2); 800caaa: 4810 ldr r0, [pc, #64] @ (800caec ) 800caac: f006 fb34 bl 8013118 serial_control.tx_tick = 0; // Сбрасываем tick 800cab0: 4b0f ldr r3, [pc, #60] @ (800caf0 ) 800cab2: 2200 movs r2, #0 800cab4: f8c3 220c str.w r2, [r3, #524] @ 0x20c } } // Проверка наличия принятой команды для обработки if (serial_control.command_ready && (huart2.gState != HAL_UART_STATE_BUSY_TX)) { 800cab8: 4b0d ldr r3, [pc, #52] @ (800caf0 ) 800caba: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800cabe: b2db uxtb r3, r3 800cac0: 2b00 cmp r3, #0 800cac2: d010 beq.n 800cae6 800cac4: 4b09 ldr r3, [pc, #36] @ (800caec ) 800cac6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800caca: b2db uxtb r3, r3 800cacc: 2b21 cmp r3, #33 @ 0x21 800cace: d00a beq.n 800cae6 // HAL_Delay(2); SC_CommandHandler((ReceivedCommand_t*)&serial_control.received_command); 800cad0: 4808 ldr r0, [pc, #32] @ (800caf4 ) 800cad2: f000 fa87 bl 800cfe4 serial_control.command_ready = 0; // Сбрасываем флаг 800cad6: 4b06 ldr r3, [pc, #24] @ (800caf0 ) 800cad8: 2200 movs r2, #0 800cada: f883 2208 strb.w r2, [r3, #520] @ 0x208 SC_ArmUart2RxDma(); 800cade: f000 f9c1 bl 800ce64 800cae2: e000 b.n 800cae6 if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800cae4: bf00 nop } } 800cae6: bd80 pop {r7, pc} 800cae8: 200011bc .word 0x200011bc 800caec: 200012e8 .word 0x200012e8 800caf0: 20000d2c .word 0x20000d2c 800caf4: 20000f2c .word 0x20000f2c 0800caf8 : ISR_FAST void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { if (huart->Instance == huart2.Instance) { 800caf8: 4b2e ldr r3, [pc, #184] @ (800cbb4 ) ISR_FAST void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800cafa: b570 push {r4, r5, r6, lr} if (huart->Instance == huart2.Instance) { 800cafc: 681a ldr r2, [r3, #0] 800cafe: 6803 ldr r3, [r0, #0] ISR_FAST void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800cb00: 460c mov r4, r1 if (huart->Instance == huart2.Instance) { 800cb02: 4293 cmp r3, r2 800cb04: d019 beq.n 800cb3a log_printf(LOG_WARN, "UART2 RX invalid packet len=%u\n", (unsigned)Size); SC_SendPacket(NULL, 0, RESP_INVALID); } g_sc_command_source = SC_SOURCE_UART2; SC_ArmUart2RxDma(); } else if (huart->Instance == huart5.Instance) { 800cb06: 4a2c ldr r2, [pc, #176] @ (800cbb8 ) 800cb08: 6812 ldr r2, [r2, #0] 800cb0a: 4293 cmp r3, r2 800cb0c: d004 beq.n 800cb18 SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); } else { log_printf(LOG_WARN, "UART5 RX invalid packet len=%u\n", (unsigned)Size); } SC_ArmUart5RxDma(); } else if (huart->Instance == huart3.Instance) { 800cb0e: 4a2b ldr r2, [pc, #172] @ (800cbbc ) 800cb10: 6812 ldr r2, [r2, #0] 800cb12: 4293 cmp r3, r2 800cb14: d04a beq.n 800cbac CCS_RxEventCallback(huart, Size); } } 800cb16: bd70 pop {r4, r5, r6, pc} if (Size == 0u) { 800cb18: b399 cbz r1, 800cb82 if (process_received_packet(&serial_iso, serial_iso.rx_buffer, Size)) { 800cb1a: 4929 ldr r1, [pc, #164] @ (800cbc0 ) 800cb1c: 4622 mov r2, r4 800cb1e: f5a1 7080 sub.w r0, r1, #256 @ 0x100 800cb22: f000 f949 bl 800cdb8 800cb26: bb10 cbnz r0, 800cb6e log_printf(LOG_WARN, "UART5 RX invalid packet len=%u\n", (unsigned)Size); 800cb28: 4622 mov r2, r4 800cb2a: 2005 movs r0, #5 800cb2c: 4925 ldr r1, [pc, #148] @ (800cbc4 ) 800cb2e: f7fd fce1 bl 800a4f4 } 800cb32: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} SC_ArmUart5RxDma(); 800cb36: f000 b9b9 b.w 800ceac if (Size == 0u) { 800cb3a: b391 cbz r1, 800cba2 sc_uart2_last_packet_tick = HAL_GetTick(); 800cb3c: f001 fbca bl 800e2d4 sc_uart2_timed_out = 0; 800cb40: 2200 movs r2, #0 800cb42: 4b21 ldr r3, [pc, #132] @ (800cbc8 ) if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800cb44: 4921 ldr r1, [pc, #132] @ (800cbcc ) sc_uart2_timed_out = 0; 800cb46: 701a strb r2, [r3, #0] sc_uart2_last_packet_tick = HAL_GetTick(); 800cb48: 4603 mov r3, r0 sc_uart2_last_recover_tick = sc_uart2_last_packet_tick; 800cb4a: 4d21 ldr r5, [pc, #132] @ (800cbd0 ) sc_uart2_last_packet_tick = HAL_GetTick(); 800cb4c: 4e21 ldr r6, [pc, #132] @ (800cbd4 ) if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800cb4e: 4622 mov r2, r4 800cb50: f5a1 7080 sub.w r0, r1, #256 @ 0x100 sc_uart2_last_recover_tick = sc_uart2_last_packet_tick; 800cb54: 602b str r3, [r5, #0] sc_uart2_last_packet_tick = HAL_GetTick(); 800cb56: 6033 str r3, [r6, #0] if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800cb58: f000 f92e bl 800cdb8 800cb5c: 4605 mov r5, r0 800cb5e: b1a8 cbz r0, 800cb8c g_sc_command_source = SC_SOURCE_UART2; 800cb60: 2200 movs r2, #0 800cb62: 4b1d ldr r3, [pc, #116] @ (800cbd8 ) 800cb64: 701a strb r2, [r3, #0] } 800cb66: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} SC_ArmUart2RxDma(); 800cb6a: f000 b97b b.w 800ce64 g_sc_command_source = SC_SOURCE_UART5; 800cb6e: 2201 movs r2, #1 800cb70: 4b19 ldr r3, [pc, #100] @ (800cbd8 ) SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); 800cb72: 481a ldr r0, [pc, #104] @ (800cbdc ) g_sc_command_source = SC_SOURCE_UART5; 800cb74: 701a strb r2, [r3, #0] SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); 800cb76: f000 fa35 bl 800cfe4 } 800cb7a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} SC_ArmUart5RxDma(); 800cb7e: f000 b995 b.w 800ceac log_printf(LOG_WARN, "UART5 RX idle event with zero size\n"); 800cb82: 4917 ldr r1, [pc, #92] @ (800cbe0 ) 800cb84: 2005 movs r0, #5 800cb86: f7fd fcb5 bl 800a4f4 800cb8a: e7c6 b.n 800cb1a log_printf(LOG_WARN, "UART2 RX invalid packet len=%u\n", (unsigned)Size); 800cb8c: 4622 mov r2, r4 800cb8e: 4915 ldr r1, [pc, #84] @ (800cbe4 ) 800cb90: 2005 movs r0, #5 800cb92: f7fd fcaf bl 800a4f4 SC_SendPacket(NULL, 0, RESP_INVALID); 800cb96: 2214 movs r2, #20 800cb98: 4629 mov r1, r5 800cb9a: 4628 mov r0, r5 800cb9c: f000 f8b6 bl 800cd0c 800cba0: e7de b.n 800cb60 log_printf(LOG_WARN, "UART2 RX idle event with zero size\n"); 800cba2: 4911 ldr r1, [pc, #68] @ (800cbe8 ) 800cba4: 2005 movs r0, #5 800cba6: f7fd fca5 bl 800a4f4 800cbaa: e7c7 b.n 800cb3c } 800cbac: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} CCS_RxEventCallback(huart, Size); 800cbb0: f7ff b812 b.w 800bbd8 800cbb4: 200012e8 .word 0x200012e8 800cbb8: 20001258 .word 0x20001258 800cbbc: 20001330 .word 0x20001330 800cbc0: 2000103c .word 0x2000103c 800cbc4: 0801772c .word 0x0801772c 800cbc8: 2000114d .word 0x2000114d 800cbcc: 20000e2c .word 0x20000e2c 800cbd0: 20001154 .word 0x20001154 800cbd4: 20001150 .word 0x20001150 800cbd8: 2000114c .word 0x2000114c 800cbdc: 2000113c .word 0x2000113c 800cbe0: 08017708 .word 0x08017708 800cbe4: 080176e8 .word 0x080176e8 800cbe8: 080176c4 .word 0x080176c4 0800cbec : ISR_FAST void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { if (huart->Instance == huart2.Instance) { 800cbec: 4b08 ldr r3, [pc, #32] @ (800cc10 ) 800cbee: 681a ldr r2, [r3, #0] 800cbf0: 6803 ldr r3, [r0, #0] 800cbf2: 4293 cmp r3, r2 800cbf4: d004 beq.n 800cc00 serial_control.tx_tick = 0; } else if (huart->Instance == huart3.Instance) { 800cbf6: 4a07 ldr r2, [pc, #28] @ (800cc14 ) 800cbf8: 6812 ldr r2, [r2, #0] 800cbfa: 4293 cmp r3, r2 800cbfc: d005 beq.n 800cc0a CCS_TxCpltCallback(huart); } } 800cbfe: 4770 bx lr serial_control.tx_tick = 0; 800cc00: 2200 movs r2, #0 800cc02: 4b05 ldr r3, [pc, #20] @ (800cc18 ) 800cc04: f8c3 220c str.w r2, [r3, #524] @ 0x20c 800cc08: 4770 bx lr CCS_TxCpltCallback(huart); 800cc0a: f7ff b88f b.w 800bd2c 800cc0e: bf00 nop 800cc10: 200012e8 .word 0x200012e8 800cc14: 20001330 .word 0x20001330 800cc18: 20000d2c .word 0x20000d2c 0800cc1c : // Полностью программная реализация CRC-32 (полином CRC32_POLYNOMIAL, порядок little-endian) ISR_FAST static uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { uint32_t crc = 0xFFFFFFFFu; for (uint16_t i = 0; i < length; i++) { 800cc1c: b3c9 cbz r1, 800cc92 uint32_t crc = 0xFFFFFFFFu; 800cc1e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff ISR_FAST static uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { 800cc22: b500 push {lr} crc ^= data[i]; for (uint8_t bit = 0; bit < 8; bit++) { if (crc & 0x1u) { 800cc24: 4a1c ldr r2, [pc, #112] @ (800cc98 ) 800cc26: 4401 add r1, r0 crc ^= data[i]; 800cc28: f810 eb01 ldrb.w lr, [r0], #1 800cc2c: ea8e 0e03 eor.w lr, lr, r3 if (crc & 0x1u) { 800cc30: f34e 0300 sbfx r3, lr, #0, #1 800cc34: f34e 0c40 sbfx ip, lr, #1, #1 800cc38: 4013 ands r3, r2 800cc3a: ea83 035e eor.w r3, r3, lr, lsr #1 800cc3e: ea0c 0c02 and.w ip, ip, r2 800cc42: ea8c 0c53 eor.w ip, ip, r3, lsr #1 800cc46: f343 0340 sbfx r3, r3, #1, #1 800cc4a: f34c 0e40 sbfx lr, ip, #1, #1 800cc4e: 4013 ands r3, r2 800cc50: ea83 035c eor.w r3, r3, ip, lsr #1 800cc54: ea0e 0e02 and.w lr, lr, r2 800cc58: ea8e 0e53 eor.w lr, lr, r3, lsr #1 800cc5c: f343 0340 sbfx r3, r3, #1, #1 800cc60: f34e 0c40 sbfx ip, lr, #1, #1 800cc64: 4013 ands r3, r2 800cc66: ea83 035e eor.w r3, r3, lr, lsr #1 800cc6a: ea0c 0c02 and.w ip, ip, r2 800cc6e: ea8c 0c53 eor.w ip, ip, r3, lsr #1 800cc72: f343 0340 sbfx r3, r3, #1, #1 800cc76: 4013 ands r3, r2 800cc78: f34c 0e40 sbfx lr, ip, #1, #1 800cc7c: ea83 035c eor.w r3, r3, ip, lsr #1 for (uint16_t i = 0; i < length; i++) { 800cc80: 4281 cmp r1, r0 if (crc & 0x1u) { 800cc82: ea0e 0c02 and.w ip, lr, r2 800cc86: ea8c 0353 eor.w r3, ip, r3, lsr #1 for (uint16_t i = 0; i < length; i++) { 800cc8a: d1cd bne.n 800cc28 crc >>= 1; } } } return crc ^ 0xFFFFFFFFu; 800cc8c: 43d8 mvns r0, r3 } 800cc8e: f85d fb04 ldr.w pc, [sp], #4 for (uint16_t i = 0; i < length; i++) { 800cc92: 4608 mov r0, r1 } 800cc94: 4770 bx lr 800cc96: bf00 nop 800cc98: edb88320 .word 0xedb88320 0800cc9c : ISR_FAST static uint16_t encode_packet(const uint8_t* payload, uint16_t payload_len, uint8_t* output, uint8_t response_code) { 800cc9c: b570 push {r4, r5, r6, lr} 800cc9e: 4615 mov r5, r2 uint16_t out_index = 0; output[out_index++] = response_code; 800cca0: 7013 strb r3, [r2, #0] if (payload != NULL) { 800cca2: b360 cbz r0, 800ccfe // Просто копируем полезную нагрузку без какого‑либо экранирования for (uint16_t i = 0; i < payload_len; i++) { 800cca4: b359 cbz r1, 800ccfe output[out_index++] = payload[i]; 800cca6: 4694 mov ip, r2 800cca8: 2302 movs r3, #2 800ccaa: 7802 ldrb r2, [r0, #0] 800ccac: 1e4c subs r4, r1, #1 800ccae: b2a4 uxth r4, r4 800ccb0: 441c add r4, r3 800ccb2: f80c 2f01 strb.w r2, [ip, #1]! // Проверка переполнения if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800ccb6: e005 b.n 800ccc4 output[out_index++] = payload[i]; 800ccb8: f810 1f01 ldrb.w r1, [r0, #1]! if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800ccbc: 2bfb cmp r3, #251 @ 0xfb output[out_index++] = payload[i]; 800ccbe: f80c 1f01 strb.w r1, [ip, #1]! if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800ccc2: d020 beq.n 800cd06 for (uint16_t i = 0; i < payload_len; i++) { 800ccc4: 42a3 cmp r3, r4 if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800ccc6: f103 0301 add.w r3, r3, #1 for (uint16_t i = 0; i < payload_len; i++) { 800ccca: d1f5 bne.n 800ccb8 800cccc: b2a1 uxth r1, r4 output[out_index++] = payload[i]; 800ccce: 1c4e adds r6, r1, #1 800ccd0: b2b6 uxth r6, r6 } } } // Вычисляем CRC для всего содержимого (код ответа + полезная нагрузка) uint32_t crc = calculate_crc32(output, out_index); 800ccd2: 4628 mov r0, r5 800ccd4: f7ff ffa2 bl 800cc1c 800ccd8: 4603 mov r3, r0 uint8_t* crc_bytes = (uint8_t*)&crc; // Добавляем CRC без экранирования for (int i = 0; i < 4; i++) { output[out_index++] = crc_bytes[i]; 800ccda: 1c71 adds r1, r6, #1 800ccdc: 1cb2 adds r2, r6, #2 800ccde: 552b strb r3, [r5, r4] 800cce0: f3c3 2c07 ubfx ip, r3, #8, #8 800cce4: f3c3 4407 ubfx r4, r3, #16, #8 800cce8: b289 uxth r1, r1 800ccea: b292 uxth r2, r2 800ccec: f3c3 6307 ubfx r3, r3, #24, #8 800ccf0: f805 c006 strb.w ip, [r5, r6] 800ccf4: 1cf0 adds r0, r6, #3 800ccf6: 546c strb r4, [r5, r1] 800ccf8: 54ab strb r3, [r5, r2] 800ccfa: b280 uxth r0, r0 return 0; } } return out_index; } 800ccfc: bd70 pop {r4, r5, r6, pc} for (uint16_t i = 0; i < payload_len; i++) { 800ccfe: 2401 movs r4, #1 800cd00: 2602 movs r6, #2 output[out_index++] = response_code; 800cd02: 4621 mov r1, r4 800cd04: e7e5 b.n 800ccd2 return 0; 800cd06: 2000 movs r0, #0 } 800cd08: bd70 pop {r4, r5, r6, pc} 800cd0a: bf00 nop 0800cd0c : ISR_FAST void SC_SendPacket(const uint8_t* payload, uint16_t payload_len, uint8_t response_code) { 800cd0c: b538 push {r3, r4, r5, lr} 800cd0e: 4613 mov r3, r2 uint16_t packet_len = encode_packet(payload, payload_len, serial_control.tx_buffer, response_code); 800cd10: 4a11 ldr r2, [pc, #68] @ (800cd58 ) 800cd12: f7ff ffc3 bl 800cc9c if (packet_len > 0) { 800cd16: b180 cbz r0, 800cd3a if (huart2.gState != HAL_UART_STATE_READY) { 800cd18: 4604 mov r4, r0 800cd1a: 4810 ldr r0, [pc, #64] @ (800cd5c ) 800cd1c: f890 3041 ldrb.w r3, [r0, #65] @ 0x41 800cd20: 2b20 cmp r3, #32 800cd22: d10b bne.n 800cd3c (void)HAL_UART_AbortTransmit(&huart2); log_printf(LOG_WARN, "UART2 TX busy, abort transmit before resend\n"); } if (HAL_UART_Transmit_DMA(&huart2, serial_control.tx_buffer, packet_len) != HAL_OK) { 800cd24: 4d0c ldr r5, [pc, #48] @ (800cd58 ) 800cd26: 4622 mov r2, r4 800cd28: 4629 mov r1, r5 800cd2a: 480c ldr r0, [pc, #48] @ (800cd5c ) 800cd2c: f006 f8ce bl 8012ecc 800cd30: b958 cbnz r0, 800cd4a SC_LogUartError("UART2 TX DMA start failed", &huart2); return; } serial_control.tx_tick = HAL_GetTick(); 800cd32: f001 facf bl 800e2d4 800cd36: f8c5 020c str.w r0, [r5, #524] @ 0x20c } } 800cd3a: bd38 pop {r3, r4, r5, pc} (void)HAL_UART_AbortTransmit(&huart2); 800cd3c: f006 f9ec bl 8013118 log_printf(LOG_WARN, "UART2 TX busy, abort transmit before resend\n"); 800cd40: 4907 ldr r1, [pc, #28] @ (800cd60 ) 800cd42: 2005 movs r0, #5 800cd44: f7fd fbd6 bl 800a4f4 800cd48: e7ec b.n 800cd24 SC_LogUartError("UART2 TX DMA start failed", &huart2); 800cd4a: 4904 ldr r1, [pc, #16] @ (800cd5c ) 800cd4c: 4805 ldr r0, [pc, #20] @ (800cd64 ) } 800cd4e: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} SC_LogUartError("UART2 TX DMA start failed", &huart2); 800cd52: f000 b905 b.w 800cf60 800cd56: bf00 nop 800cd58: 20000d2c .word 0x20000d2c 800cd5c: 200012e8 .word 0x200012e8 800cd60: 0801774c .word 0x0801774c 800cd64: 0801777c .word 0x0801777c 0800cd68 : ISR_FAST static uint8_t parse_packet(const uint8_t* packet_data, uint16_t packet_len, ReceivedCommand_t* out_cmd) { 800cd68: e92d 4178 stmdb sp!, {r3, r4, r5, r6, r8, lr} // }else{ // test_crc_invalid = 5; // } // Минимальный размер: 1 байт команды + 4 байта CRC if (packet_len < 5) return 0; 800cd6c: 1f4b subs r3, r1, #5 800cd6e: 2bfb cmp r3, #251 @ 0xfb 800cd70: d813 bhi.n 800cd9a if (packet_len > MAX_RX_BUFFER_SIZE) return 0; uint16_t payload_length = packet_len - 4; 800cd72: 3904 subs r1, #4 800cd74: b28c uxth r4, r1 // Извлекаем принятую CRC (последние 4 байта, little-endian) uint32_t received_checksum = ((uint32_t)packet_data[payload_length] << 0) | ((uint32_t)packet_data[payload_length + 1] << 8) | 800cd76: 1903 adds r3, r0, r4 ((uint32_t)packet_data[payload_length + 2] << 16) | 800cd78: 789d ldrb r5, [r3, #2] 800cd7a: 4690 mov r8, r2 ((uint32_t)packet_data[payload_length + 1] << 8) | 800cd7c: 785a ldrb r2, [r3, #1] ((uint32_t)packet_data[payload_length + 2] << 16) | 800cd7e: 042d lsls r5, r5, #16 ((uint32_t)packet_data[payload_length + 1] << 8) | 800cd80: ea45 2502 orr.w r5, r5, r2, lsl #8 ((uint32_t)packet_data[payload_length] << 0) | 800cd84: 5d02 ldrb r2, [r0, r4] ((uint32_t)packet_data[payload_length + 3] << 24); 800cd86: 78db ldrb r3, [r3, #3] ((uint32_t)packet_data[payload_length + 1] << 8) | 800cd88: 4315 orrs r5, r2 // Вычисляем CRC для полезной нагрузки uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); 800cd8a: 4621 mov r1, r4 uint32_t received_checksum = 800cd8c: ea45 6503 orr.w r5, r5, r3, lsl #24 uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); 800cd90: 4606 mov r6, r0 800cd92: f7ff ff43 bl 800cc1c if (received_checksum != calculated_checksum) return 0; // CRC не совпадает 800cd96: 4285 cmp r5, r0 800cd98: d002 beq.n 800cda0 if (packet_len < 5) return 0; 800cd9a: 2000 movs r0, #0 out_cmd->argument = (void *)&packet_data[1]; out_cmd->command = packet_data[0]; out_cmd->argument_length = (uint8_t)(payload_length - 1); return 1; } 800cd9c: e8bd 8178 ldmia.w sp!, {r3, r4, r5, r6, r8, pc} out_cmd->argument = (void *)&packet_data[1]; 800cda0: 1c73 adds r3, r6, #1 800cda2: f8c8 3004 str.w r3, [r8, #4] out_cmd->command = packet_data[0]; 800cda6: 7833 ldrb r3, [r6, #0] out_cmd->argument_length = (uint8_t)(payload_length - 1); 800cda8: 3c01 subs r4, #1 out_cmd->command = packet_data[0]; 800cdaa: f888 3000 strb.w r3, [r8] out_cmd->argument_length = (uint8_t)(payload_length - 1); 800cdae: f888 4001 strb.w r4, [r8, #1] return 1; 800cdb2: 2001 movs r0, #1 } 800cdb4: e8bd 8178 ldmia.w sp!, {r3, r4, r5, r6, r8, pc} 0800cdb8 : ISR_FAST static uint8_t process_received_packet(SerialControl_t *ctx, const uint8_t* packet_data, uint16_t packet_len) { 800cdb8: b510 push {r4, lr} 800cdba: 4604 mov r4, r0 if (!parse_packet(packet_data, packet_len, (ReceivedCommand_t *)&ctx->received_command)) { 800cdbc: 4608 mov r0, r1 800cdbe: 4611 mov r1, r2 800cdc0: f504 7200 add.w r2, r4, #512 @ 0x200 800cdc4: f7ff ffd0 bl 800cd68 800cdc8: b118 cbz r0, 800cdd2 return 0; } ctx->command_ready = 1; 800cdca: 2301 movs r3, #1 return 1; 800cdcc: 4618 mov r0, r3 ctx->command_ready = 1; 800cdce: f884 3208 strb.w r3, [r4, #520] @ 0x208 } 800cdd2: bd10 pop {r4, pc} 0800cdd4 : static void SC_UART2_Watchdog(void) { 800cdd4: b580 push {r7, lr} 800cdd6: b082 sub sp, #8 800cdd8: af00 add r7, sp, #0 const uint32_t now = HAL_GetTick(); 800cdda: f001 fa7b bl 800e2d4 800cdde: 6078 str r0, [r7, #4] const int32_t since_last_packet = (int32_t)(now - sc_uart2_last_packet_tick); 800cde0: 4b1a ldr r3, [pc, #104] @ (800ce4c ) 800cde2: 681b ldr r3, [r3, #0] 800cde4: 687a ldr r2, [r7, #4] 800cde6: 1ad3 subs r3, r2, r3 800cde8: 603b str r3, [r7, #0] if (since_last_packet >= (int32_t)SC_UART2_PACKET_TIMEOUT_MS) { 800cdea: 683b ldr r3, [r7, #0] 800cdec: f241 3287 movw r2, #4999 @ 0x1387 800cdf0: 4293 cmp r3, r2 800cdf2: dd12 ble.n 800ce1a if (sc_uart2_timed_out == 0u) { 800cdf4: 4b16 ldr r3, [pc, #88] @ (800ce50 ) 800cdf6: 781b ldrb r3, [r3, #0] 800cdf8: b2db uxtb r3, r3 800cdfa: 2b00 cmp r3, #0 800cdfc: d109 bne.n 800ce12 serial_control.command_ready = 0; 800cdfe: 4b15 ldr r3, [pc, #84] @ (800ce54 ) 800ce00: 2200 movs r2, #0 800ce02: f883 2208 strb.w r2, [r3, #520] @ 0x208 log_printf(LOG_WARN, "UART2 RX packet timeout (%u ms)\n", (unsigned)SC_UART2_PACKET_TIMEOUT_MS); 800ce06: f241 3288 movw r2, #5000 @ 0x1388 800ce0a: 4913 ldr r1, [pc, #76] @ (800ce58 ) 800ce0c: 2005 movs r0, #5 800ce0e: f7fd fb71 bl 800a4f4 } sc_uart2_timed_out = 1; 800ce12: 4b0f ldr r3, [pc, #60] @ (800ce50 ) 800ce14: 2201 movs r2, #1 800ce16: 701a strb r2, [r3, #0] 800ce18: e002 b.n 800ce20 } else { sc_uart2_timed_out = 0; 800ce1a: 4b0d ldr r3, [pc, #52] @ (800ce50 ) 800ce1c: 2200 movs r2, #0 800ce1e: 701a strb r2, [r3, #0] } if ((huart2.RxState == HAL_UART_STATE_READY) && 800ce20: 4b0e ldr r3, [pc, #56] @ (800ce5c ) 800ce22: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800ce26: b2db uxtb r3, r3 800ce28: 2b20 cmp r3, #32 800ce2a: d10a bne.n 800ce42 ((int32_t)(now - sc_uart2_last_recover_tick) >= (int32_t)SC_UART2_RECOVER_GUARD_MS)) { 800ce2c: 4b0c ldr r3, [pc, #48] @ (800ce60 ) 800ce2e: 681b ldr r3, [r3, #0] 800ce30: 687a ldr r2, [r7, #4] 800ce32: 1ad3 subs r3, r2, r3 if ((huart2.RxState == HAL_UART_STATE_READY) && 800ce34: 2bc7 cmp r3, #199 @ 0xc7 800ce36: dd04 ble.n 800ce42 SC_ArmUart2RxDma(); 800ce38: f000 f814 bl 800ce64 sc_uart2_last_recover_tick = now; 800ce3c: 4a08 ldr r2, [pc, #32] @ (800ce60 ) 800ce3e: 687b ldr r3, [r7, #4] 800ce40: 6013 str r3, [r2, #0] } } 800ce42: bf00 nop 800ce44: 3708 adds r7, #8 800ce46: 46bd mov sp, r7 800ce48: bd80 pop {r7, pc} 800ce4a: bf00 nop 800ce4c: 20001150 .word 0x20001150 800ce50: 2000114d .word 0x2000114d 800ce54: 20000d2c .word 0x20000d2c 800ce58: 08017798 .word 0x08017798 800ce5c: 200012e8 .word 0x200012e8 800ce60: 20001154 .word 0x20001154 0800ce64 : static void SC_ArmUart2RxDma(void) { 800ce64: b580 push {r7, lr} 800ce66: af00 add r7, sp, #0 if ((huart2.RxState == HAL_UART_STATE_READY) && (serial_control.command_ready == 0)) { 800ce68: 4b0c ldr r3, [pc, #48] @ (800ce9c ) 800ce6a: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800ce6e: b2db uxtb r3, r3 800ce70: 2b20 cmp r3, #32 800ce72: d111 bne.n 800ce98 800ce74: 4b0a ldr r3, [pc, #40] @ (800cea0 ) 800ce76: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800ce7a: b2db uxtb r3, r3 800ce7c: 2b00 cmp r3, #0 800ce7e: d10b bne.n 800ce98 if (HAL_UARTEx_ReceiveToIdle_DMA(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1) != HAL_OK) { 800ce80: 22ff movs r2, #255 @ 0xff 800ce82: 4908 ldr r1, [pc, #32] @ (800cea4 ) 800ce84: 4805 ldr r0, [pc, #20] @ (800ce9c ) 800ce86: f006 f8ee bl 8013066 800ce8a: 4603 mov r3, r0 800ce8c: 2b00 cmp r3, #0 800ce8e: d003 beq.n 800ce98 SC_LogUartError("UART2 RX DMA arm failed", &huart2); 800ce90: 4902 ldr r1, [pc, #8] @ (800ce9c ) 800ce92: 4805 ldr r0, [pc, #20] @ (800cea8 ) 800ce94: f000 f864 bl 800cf60 } } } 800ce98: bf00 nop 800ce9a: bd80 pop {r7, pc} 800ce9c: 200012e8 .word 0x200012e8 800cea0: 20000d2c .word 0x20000d2c 800cea4: 20000e2c .word 0x20000e2c 800cea8: 080177bc .word 0x080177bc 0800ceac : static void SC_ArmUart5RxDma(void) { 800ceac: b580 push {r7, lr} 800ceae: af00 add r7, sp, #0 if (huart5.RxState == HAL_UART_STATE_READY) { 800ceb0: 4b0a ldr r3, [pc, #40] @ (800cedc ) 800ceb2: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800ceb6: b2db uxtb r3, r3 800ceb8: 2b20 cmp r3, #32 800ceba: d10d bne.n 800ced8 if (HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1) == HAL_OK) { 800cebc: 22ff movs r2, #255 @ 0xff 800cebe: 4908 ldr r1, [pc, #32] @ (800cee0 ) 800cec0: 4806 ldr r0, [pc, #24] @ (800cedc ) 800cec2: f006 f873 bl 8012fac 800cec6: 4603 mov r3, r0 800cec8: 2b00 cmp r3, #0 800ceca: d004 beq.n 800ced6 return; } SC_LogUartError("UART5 RX IT arm failed", &huart5); 800cecc: 4903 ldr r1, [pc, #12] @ (800cedc ) 800cece: 4805 ldr r0, [pc, #20] @ (800cee4 ) 800ced0: f000 f846 bl 800cf60 800ced4: e000 b.n 800ced8 return; 800ced6: bf00 nop } } 800ced8: bd80 pop {r7, pc} 800ceda: bf00 nop 800cedc: 20001258 .word 0x20001258 800cee0: 2000103c .word 0x2000103c 800cee4: 080177d4 .word 0x080177d4 0800cee8 : void SC_RecoverUartDma(UART_HandleTypeDef *huart) { 800cee8: b580 push {r7, lr} 800ceea: b082 sub sp, #8 800ceec: af00 add r7, sp, #0 800ceee: 6078 str r0, [r7, #4] if (huart == &huart2) { 800cef0: 687b ldr r3, [r7, #4] 800cef2: 4a15 ldr r2, [pc, #84] @ (800cf48 ) 800cef4: 4293 cmp r3, r2 800cef6: d115 bne.n 800cf24 SC_LogUartError("UART2 recover start", &huart2); 800cef8: 4913 ldr r1, [pc, #76] @ (800cf48 ) 800cefa: 4814 ldr r0, [pc, #80] @ (800cf4c ) 800cefc: f000 f830 bl 800cf60 (void)HAL_UART_AbortReceive(&huart2); 800cf00: 4811 ldr r0, [pc, #68] @ (800cf48 ) 800cf02: f006 f971 bl 80131e8 (void)HAL_UART_AbortTransmit(&huart2); 800cf06: 4810 ldr r0, [pc, #64] @ (800cf48 ) 800cf08: f006 f906 bl 8013118 serial_control.tx_tick = 0; 800cf0c: 4b10 ldr r3, [pc, #64] @ (800cf50 ) 800cf0e: 2200 movs r2, #0 800cf10: f8c3 220c str.w r2, [r3, #524] @ 0x20c SC_ArmUart2RxDma(); 800cf14: f7ff ffa6 bl 800ce64 sc_uart2_last_recover_tick = HAL_GetTick(); 800cf18: f001 f9dc bl 800e2d4 800cf1c: 4603 mov r3, r0 800cf1e: 4a0d ldr r2, [pc, #52] @ (800cf54 ) 800cf20: 6013 str r3, [r2, #0] } else if (huart == &huart5) { SC_LogUartError("UART5 recover start", &huart5); (void)HAL_UART_AbortReceive(&huart5); SC_ArmUart5RxDma(); } } 800cf22: e00c b.n 800cf3e } else if (huart == &huart5) { 800cf24: 687b ldr r3, [r7, #4] 800cf26: 4a0c ldr r2, [pc, #48] @ (800cf58 ) 800cf28: 4293 cmp r3, r2 800cf2a: d108 bne.n 800cf3e SC_LogUartError("UART5 recover start", &huart5); 800cf2c: 490a ldr r1, [pc, #40] @ (800cf58 ) 800cf2e: 480b ldr r0, [pc, #44] @ (800cf5c ) 800cf30: f000 f816 bl 800cf60 (void)HAL_UART_AbortReceive(&huart5); 800cf34: 4808 ldr r0, [pc, #32] @ (800cf58 ) 800cf36: f006 f957 bl 80131e8 SC_ArmUart5RxDma(); 800cf3a: f7ff ffb7 bl 800ceac } 800cf3e: bf00 nop 800cf40: 3708 adds r7, #8 800cf42: 46bd mov sp, r7 800cf44: bd80 pop {r7, pc} 800cf46: bf00 nop 800cf48: 200012e8 .word 0x200012e8 800cf4c: 080177ec .word 0x080177ec 800cf50: 20000d2c .word 0x20000d2c 800cf54: 20001154 .word 0x20001154 800cf58: 20001258 .word 0x20001258 800cf5c: 08017800 .word 0x08017800 0800cf60 : static void SC_LogUartError(const char *tag, UART_HandleTypeDef *huart) { 800cf60: b590 push {r4, r7, lr} 800cf62: b087 sub sp, #28 800cf64: af04 add r7, sp, #16 800cf66: 6078 str r0, [r7, #4] 800cf68: 6039 str r1, [r7, #0] if (tag == NULL || huart == NULL) { 800cf6a: 687b ldr r3, [r7, #4] 800cf6c: 2b00 cmp r3, #0 800cf6e: d01c beq.n 800cfaa 800cf70: 683b ldr r3, [r7, #0] 800cf72: 2b00 cmp r3, #0 800cf74: d019 beq.n 800cfaa return; } log_printf(LOG_ERR, "%s: instance=0x%08lx err=0x%08lx g=%lu rx=%lu\n", tag, (unsigned long)huart->Instance, 800cf76: 683b ldr r3, [r7, #0] 800cf78: 681b ldr r3, [r3, #0] log_printf(LOG_ERR, "%s: instance=0x%08lx err=0x%08lx g=%lu rx=%lu\n", 800cf7a: 461c mov r4, r3 (unsigned long)HAL_UART_GetError(huart), 800cf7c: 6838 ldr r0, [r7, #0] 800cf7e: f006 fc84 bl 801388a 800cf82: 4602 mov r2, r0 (unsigned long)huart->gState, 800cf84: 683b ldr r3, [r7, #0] 800cf86: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800cf8a: b2db uxtb r3, r3 log_printf(LOG_ERR, "%s: instance=0x%08lx err=0x%08lx g=%lu rx=%lu\n", 800cf8c: 4619 mov r1, r3 (unsigned long)huart->RxState); 800cf8e: 683b ldr r3, [r7, #0] 800cf90: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800cf94: b2db uxtb r3, r3 log_printf(LOG_ERR, "%s: instance=0x%08lx err=0x%08lx g=%lu rx=%lu\n", 800cf96: 9302 str r3, [sp, #8] 800cf98: 9101 str r1, [sp, #4] 800cf9a: 9200 str r2, [sp, #0] 800cf9c: 4623 mov r3, r4 800cf9e: 687a ldr r2, [r7, #4] 800cfa0: 4904 ldr r1, [pc, #16] @ (800cfb4 ) 800cfa2: 2004 movs r0, #4 800cfa4: f7fd faa6 bl 800a4f4 800cfa8: e000 b.n 800cfac return; 800cfaa: bf00 nop } 800cfac: 370c adds r7, #12 800cfae: 46bd mov sp, r7 800cfb0: bd90 pop {r4, r7, pc} 800cfb2: bf00 nop 800cfb4: 08017814 .word 0x08017814 0800cfb8 <__NVIC_SystemReset>: { 800cfb8: b480 push {r7} 800cfba: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 800cfbc: f3bf 8f4f dsb sy } 800cfc0: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800cfc2: 4b06 ldr r3, [pc, #24] @ (800cfdc <__NVIC_SystemReset+0x24>) 800cfc4: 68db ldr r3, [r3, #12] 800cfc6: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800cfca: 4904 ldr r1, [pc, #16] @ (800cfdc <__NVIC_SystemReset+0x24>) 800cfcc: 4b04 ldr r3, [pc, #16] @ (800cfe0 <__NVIC_SystemReset+0x28>) 800cfce: 4313 orrs r3, r2 800cfd0: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800cfd2: f3bf 8f4f dsb sy } 800cfd6: bf00 nop __NOP(); 800cfd8: bf00 nop 800cfda: e7fd b.n 800cfd8 <__NVIC_SystemReset+0x20> 800cfdc: e000ed00 .word 0xe000ed00 800cfe0: 05fa0004 .word 0x05fa0004 0800cfe4 : .chargerNumber = 00001, .unixTime = 1721651966, }; // Единая функция-обработчик всех команд со switch-case void SC_CommandHandler(ReceivedCommand_t* cmd) { 800cfe4: b580 push {r7, lr} 800cfe6: b084 sub sp, #16 800cfe8: af00 add r7, sp, #0 800cfea: 6078 str r0, [r7, #4] uint8_t response_code = RESP_FAILED; 800cfec: 2313 movs r3, #19 800cfee: 73fb strb r3, [r7, #15] switch (cmd->command) { 800cff0: 687b ldr r3, [r7, #4] 800cff2: 781b ldrb r3, [r3, #0] 800cff4: 2bc2 cmp r3, #194 @ 0xc2 800cff6: f300 80cc bgt.w 800d192 800cffa: 2bb0 cmp r3, #176 @ 0xb0 800cffc: da0f bge.n 800d01e 800cffe: 2b60 cmp r3, #96 @ 0x60 800d000: d042 beq.n 800d088 800d002: 2b60 cmp r3, #96 @ 0x60 800d004: f300 80c5 bgt.w 800d192 800d008: 2b50 cmp r3, #80 @ 0x50 800d00a: d043 beq.n 800d094 800d00c: 2b50 cmp r3, #80 @ 0x50 800d00e: f300 80c0 bgt.w 800d192 800d012: 2b01 cmp r3, #1 800d014: f000 80a6 beq.w 800d164 800d018: 2b40 cmp r3, #64 @ 0x40 800d01a: d02d beq.n 800d078 800d01c: e0b9 b.n 800d192 800d01e: 3bb0 subs r3, #176 @ 0xb0 800d020: 2b12 cmp r3, #18 800d022: f200 80b6 bhi.w 800d192 800d026: a201 add r2, pc, #4 @ (adr r2, 800d02c ) 800d028: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d02c: 0800d09b .word 0x0800d09b 800d030: 0800d193 .word 0x0800d193 800d034: 0800d193 .word 0x0800d193 800d038: 0800d193 .word 0x0800d193 800d03c: 0800d193 .word 0x0800d193 800d040: 0800d143 .word 0x0800d143 800d044: 0800d193 .word 0x0800d193 800d048: 0800d193 .word 0x0800d193 800d04c: 0800d193 .word 0x0800d193 800d050: 0800d193 .word 0x0800d193 800d054: 0800d193 .word 0x0800d193 800d058: 0800d193 .word 0x0800d193 800d05c: 0800d193 .word 0x0800d193 800d060: 0800d193 .word 0x0800d193 800d064: 0800d193 .word 0x0800d193 800d068: 0800d193 .word 0x0800d193 800d06c: 0800d0d9 .word 0x0800d0d9 800d070: 0800d13d .word 0x0800d13d 800d074: 0800d111 .word 0x0800d111 // Команды БЕЗ аргументов case CMD_GET_STATUS: // Логика получения информации monitoring_data_callback(); 800d078: f000 f8b2 bl 800d1e0 // Отправляем с нормальным приоритетом SC_SendPacket((uint8_t*)&statusPacket, sizeof(statusPacket), CMD_GET_STATUS); 800d07c: 2240 movs r2, #64 @ 0x40 800d07e: 2158 movs r1, #88 @ 0x58 800d080: 484b ldr r0, [pc, #300] @ (800d1b0 ) 800d082: f7ff fe43 bl 800cd0c return; // Специальный ответ уже отправлен 800d086: e08f b.n 800d1a8 case CMD_GET_INFO: SC_SendPacket((uint8_t*)&infoPacket, sizeof(infoPacket), CMD_GET_INFO); 800d088: 2260 movs r2, #96 @ 0x60 800d08a: 210a movs r1, #10 800d08c: 4849 ldr r0, [pc, #292] @ (800d1b4 ) 800d08e: f7ff fe3d bl 800cd0c return; 800d092: e089 b.n 800d1a8 case CMD_GET_LOG: debug_buffer_send(); 800d094: f7fd f9cc bl 800a430 return; // Ответ формируется внутри debug_buffer_send 800d098: e086 b.n 800d1a8 // Команды С аргументами case CMD_SET_CONFIG: if (cmd->argument_length == sizeof(ConfigBlock_t)) { 800d09a: 687b ldr r3, [r7, #4] 800d09c: 785b ldrb r3, [r3, #1] 800d09e: 2b0b cmp r3, #11 800d0a0: d117 bne.n 800d0d2 memcpy(&config, cmd->argument, sizeof(ConfigBlock_t)); 800d0a2: 687b ldr r3, [r7, #4] 800d0a4: 685a ldr r2, [r3, #4] 800d0a6: 4b44 ldr r3, [pc, #272] @ (800d1b8 ) 800d0a8: 6810 ldr r0, [r2, #0] 800d0aa: 6851 ldr r1, [r2, #4] 800d0ac: c303 stmia r3!, {r0, r1} 800d0ae: 8911 ldrh r1, [r2, #8] 800d0b0: 7a92 ldrb r2, [r2, #10] 800d0b2: 8019 strh r1, [r3, #0] 800d0b4: 709a strb r2, [r3, #2] config_initialized = 1; 800d0b6: 4b41 ldr r3, [pc, #260] @ (800d1bc ) 800d0b8: 2201 movs r2, #1 800d0ba: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Set Config: %s %d\n", config.location, config.chargerNumber); 800d0bc: 4b3e ldr r3, [pc, #248] @ (800d1b8 ) 800d0be: f8d3 3003 ldr.w r3, [r3, #3] 800d0c2: 4a3d ldr r2, [pc, #244] @ (800d1b8 ) 800d0c4: 493e ldr r1, [pc, #248] @ (800d1c0 ) 800d0c6: 2007 movs r0, #7 800d0c8: f7fd fa14 bl 800a4f4 response_code = RESP_SUCCESS; 800d0cc: 2312 movs r3, #18 800d0ce: 73fb strb r3, [r7, #15] break; 800d0d0: e062 b.n 800d198 } response_code = RESP_FAILED; 800d0d2: 2313 movs r3, #19 800d0d4: 73fb strb r3, [r7, #15] break; 800d0d6: e05f b.n 800d198 case CMD_SET_POWER_LIMIT: if (cmd->argument_length == 1) { 800d0d8: 687b ldr r3, [r7, #4] 800d0da: 785b ldrb r3, [r3, #1] 800d0dc: 2b01 cmp r3, #1 800d0de: d114 bne.n 800d10a PSU0.power_limit = ((uint8_t*)cmd->argument)[0] * 1000; 800d0e0: 687b ldr r3, [r7, #4] 800d0e2: 685b ldr r3, [r3, #4] 800d0e4: 781b ldrb r3, [r3, #0] 800d0e6: 461a mov r2, r3 800d0e8: f44f 737a mov.w r3, #1000 @ 0x3e8 800d0ec: fb02 f303 mul.w r3, r2, r3 800d0f0: 461a mov r2, r3 800d0f2: 4b34 ldr r3, [pc, #208] @ (800d1c4 ) 800d0f4: 615a str r2, [r3, #20] log_printf(LOG_INFO, "Power limit: %d\n", PSU0.power_limit); 800d0f6: 4b33 ldr r3, [pc, #204] @ (800d1c4 ) 800d0f8: 695b ldr r3, [r3, #20] 800d0fa: 461a mov r2, r3 800d0fc: 4932 ldr r1, [pc, #200] @ (800d1c8 ) 800d0fe: 2007 movs r0, #7 800d100: f7fd f9f8 bl 800a4f4 //CONN.connState = (((uint8_t*)cmd->argument)[0])/4; response_code = RESP_SUCCESS; 800d104: 2312 movs r3, #18 800d106: 73fb strb r3, [r7, #15] break; 800d108: e046 b.n 800d198 } response_code = RESP_FAILED; 800d10a: 2313 movs r3, #19 800d10c: 73fb strb r3, [r7, #15] break; 800d10e: e043 b.n 800d198 case CMD_CHARGE_PERMIT: if (cmd->argument_length == 1) { 800d110: 687b ldr r3, [r7, #4] 800d112: 785b ldrb r3, [r3, #1] 800d114: 2b01 cmp r3, #1 800d116: d10e bne.n 800d136 CONN.connControl = ((uint8_t*)cmd->argument)[0]; 800d118: 687b ldr r3, [r7, #4] 800d11a: 685b ldr r3, [r3, #4] 800d11c: 781a ldrb r2, [r3, #0] 800d11e: 4b2b ldr r3, [pc, #172] @ (800d1cc ) 800d120: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Charge permit: %d\n", CONN.connControl); 800d122: 4b2a ldr r3, [pc, #168] @ (800d1cc ) 800d124: 781b ldrb r3, [r3, #0] 800d126: 461a mov r2, r3 800d128: 4929 ldr r1, [pc, #164] @ (800d1d0 ) 800d12a: 2007 movs r0, #7 800d12c: f7fd f9e2 bl 800a4f4 response_code = RESP_SUCCESS; 800d130: 2312 movs r3, #18 800d132: 73fb strb r3, [r7, #15] break; 800d134: e030 b.n 800d198 } response_code = RESP_FAILED; 800d136: 2313 movs r3, #19 800d138: 73fb strb r3, [r7, #15] break; 800d13a: e02d b.n 800d198 // memcpy(&PSU_TestMode, cmd->argument, sizeof(PSU_TestMode_t)); // log_printf(LOG_INFO, "Test PSU: %d %d %d\n", PSU_TestMode.enable, PSU_TestMode.voltage, PSU_TestMode.current); // response_code = RESP_SUCCESS; // break; // } response_code = RESP_FAILED; 800d13c: 2313 movs r3, #19 800d13e: 73fb strb r3, [r7, #15] break; 800d140: e02a b.n 800d198 case CMD_DEVICE_RESET: // 2. Отправляем SUCCESS (хост может успеть получить его перед ребутом) SC_SendPacket(NULL, 0, RESP_SUCCESS); 800d142: 2212 movs r2, #18 800d144: 2100 movs r1, #0 800d146: 2000 movs r0, #0 800d148: f7ff fde0 bl 800cd0c while(huart2.gState == HAL_UART_STATE_BUSY_TX); // Ожидание завершения передачи 800d14c: bf00 nop 800d14e: 4b21 ldr r3, [pc, #132] @ (800d1d4 ) 800d150: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800d154: b2db uxtb r3, r3 800d156: 2b21 cmp r3, #33 @ 0x21 800d158: d0f9 beq.n 800d14e HAL_Delay(10); 800d15a: 200a movs r0, #10 800d15c: f001 f8c4 bl 800e2e8 // 3. Выполняем программный сброс NVIC_SystemReset(); 800d160: f7ff ff2a bl 800cfb8 <__NVIC_SystemReset> return; // Сюда код уже не дойдет, но для компилятора нxужно case CMD_ISOLATION_STATUS: if (cmd->argument_length == sizeof(IsolationStatusPacket_t)) { 800d164: 687b ldr r3, [r7, #4] 800d166: 785b ldrb r3, [r3, #1] 800d168: 2b09 cmp r3, #9 800d16a: d10f bne.n 800d18c memcpy(&ISO, cmd->argument, sizeof(IsolationStatusPacket_t)); 800d16c: 687b ldr r3, [r7, #4] 800d16e: 685a ldr r2, [r3, #4] 800d170: 4b19 ldr r3, [pc, #100] @ (800d1d8 ) 800d172: 6810 ldr r0, [r2, #0] 800d174: 6851 ldr r1, [r2, #4] 800d176: c303 stmia r3!, {r0, r1} 800d178: 7a12 ldrb r2, [r2, #8] 800d17a: 701a strb r2, [r3, #0] // Для однонаправленного UART5 ответ не нужен if (g_sc_command_source == SC_SOURCE_UART5) { 800d17c: 4b17 ldr r3, [pc, #92] @ (800d1dc ) 800d17e: 781b ldrb r3, [r3, #0] 800d180: b2db uxtb r3, r3 800d182: 2b01 cmp r3, #1 800d184: d00f beq.n 800d1a6 return; } response_code = RESP_SUCCESS; 800d186: 2312 movs r3, #18 800d188: 73fb strb r3, [r7, #15] break; 800d18a: e005 b.n 800d198 } response_code = RESP_FAILED; 800d18c: 2313 movs r3, #19 800d18e: 73fb strb r3, [r7, #15] break; 800d190: e002 b.n 800d198 default: // Неизвестная команда response_code = RESP_FAILED; 800d192: 2313 movs r3, #19 800d194: 73fb strb r3, [r7, #15] break; 800d196: bf00 nop } // Отправляем финальный ответ (для команд без собственного ответа) SC_SendPacket(NULL, 0, response_code); 800d198: 7bfb ldrb r3, [r7, #15] 800d19a: 461a mov r2, r3 800d19c: 2100 movs r1, #0 800d19e: 2000 movs r0, #0 800d1a0: f7ff fdb4 bl 800cd0c 800d1a4: e000 b.n 800d1a8 return; 800d1a6: bf00 nop } 800d1a8: 3710 adds r7, #16 800d1aa: 46bd mov sp, r7 800d1ac: bd80 pop {r7, pc} 800d1ae: bf00 nop 800d1b0: 20001158 .word 0x20001158 800d1b4: 200011b0 .word 0x200011b0 800d1b8: 20000078 .word 0x20000078 800d1bc: 200011c0 .word 0x200011c0 800d1c0: 08017844 .word 0x08017844 800d1c4: 20000904 .word 0x20000904 800d1c8: 08017858 .word 0x08017858 800d1cc: 200003b0 .word 0x200003b0 800d1d0: 0801786c .word 0x0801786c 800d1d4: 200012e8 .word 0x200012e8 800d1d8: 2000006c .word 0x2000006c 800d1dc: 2000114c .word 0x2000114c 0800d1e0 : // Колбэк для заполнения данных мониторинга static void monitoring_data_callback(void) { 800d1e0: b580 push {r7, lr} 800d1e2: af00 add r7, sp, #0 // Информация о зарядной сессии statusPacket.SOC = CONN.SOC; 800d1e4: 4b8f ldr r3, [pc, #572] @ (800d424 ) 800d1e6: 789a ldrb r2, [r3, #2] 800d1e8: 4b8f ldr r3, [pc, #572] @ (800d428 ) 800d1ea: 709a strb r2, [r3, #2] statusPacket.Energy = CONN.Energy; 800d1ec: 4b8d ldr r3, [pc, #564] @ (800d424 ) 800d1ee: f8d3 3007 ldr.w r3, [r3, #7] 800d1f2: 4a8d ldr r2, [pc, #564] @ (800d428 ) 800d1f4: f8c2 3003 str.w r3, [r2, #3] statusPacket.RequestedVoltage = CONN.RequestedVoltage; 800d1f8: 4b8a ldr r3, [pc, #552] @ (800d424 ) 800d1fa: f8b3 300f ldrh.w r3, [r3, #15] 800d1fe: b29a uxth r2, r3 800d200: 4b89 ldr r3, [pc, #548] @ (800d428 ) 800d202: f8a3 2007 strh.w r2, [r3, #7] statusPacket.RequestedCurrent = CONN.WantedCurrent; 800d206: 4b87 ldr r3, [pc, #540] @ (800d424 ) 800d208: f8b3 301b ldrh.w r3, [r3, #27] 800d20c: b29a uxth r2, r3 800d20e: 4b86 ldr r3, [pc, #536] @ (800d428 ) 800d210: f8a3 2009 strh.w r2, [r3, #9] statusPacket.MeasuredVoltage = CONN.MeasuredVoltage; 800d214: 4b83 ldr r3, [pc, #524] @ (800d424 ) 800d216: f8b3 3013 ldrh.w r3, [r3, #19] 800d21a: b29a uxth r2, r3 800d21c: 4b82 ldr r3, [pc, #520] @ (800d428 ) 800d21e: f8a3 200b strh.w r2, [r3, #11] statusPacket.MeasuredCurrent = CONN.MeasuredCurrent; 800d222: 4b80 ldr r3, [pc, #512] @ (800d424 ) 800d224: f8b3 3015 ldrh.w r3, [r3, #21] 800d228: b29a uxth r2, r3 800d22a: 4b7f ldr r3, [pc, #508] @ (800d428 ) 800d22c: f8a3 200d strh.w r2, [r3, #13] statusPacket.outputEnabled = CONN.outputEnabled; 800d230: 4b7c ldr r3, [pc, #496] @ (800d424 ) 800d232: 7e1a ldrb r2, [r3, #24] 800d234: 4b7c ldr r3, [pc, #496] @ (800d428 ) 800d236: 73da strb r2, [r3, #15] statusPacket.chargingError = CONN.chargingError; 800d238: 4b7a ldr r3, [pc, #488] @ (800d424 ) 800d23a: 7f5a ldrb r2, [r3, #29] 800d23c: 4b7a ldr r3, [pc, #488] @ (800d428 ) 800d23e: 705a strb r2, [r3, #1] statusPacket.connState = CONN.connState; 800d240: 4b78 ldr r3, [pc, #480] @ (800d424 ) 800d242: 785a ldrb r2, [r3, #1] 800d244: 4b78 ldr r3, [pc, #480] @ (800d428 ) 800d246: 701a strb r2, [r3, #0] statusPacket.chargingElapsedTimeMin = 0; 800d248: 4b77 ldr r3, [pc, #476] @ (800d428 ) 800d24a: 2200 movs r2, #0 800d24c: 741a strb r2, [r3, #16] 800d24e: 2200 movs r2, #0 800d250: 745a strb r2, [r3, #17] statusPacket.chargingElapsedTimeSec = 0; 800d252: 4b75 ldr r3, [pc, #468] @ (800d428 ) 800d254: 2200 movs r2, #0 800d256: 749a strb r2, [r3, #18] statusPacket.estimatedRemainingChargingTime = 0; 800d258: 4b73 ldr r3, [pc, #460] @ (800d428 ) 800d25a: 2200 movs r2, #0 800d25c: 74da strb r2, [r3, #19] 800d25e: 2200 movs r2, #0 800d260: 751a strb r2, [r3, #20] // состояние зарядной станции statusPacket.relayAC = RELAY_Read(RELAY_AC); 800d262: 2004 movs r0, #4 800d264: f7fc fb18 bl 8009898 800d268: 4603 mov r3, r0 800d26a: f003 0301 and.w r3, r3, #1 800d26e: b2d9 uxtb r1, r3 800d270: 4a6d ldr r2, [pc, #436] @ (800d428 ) 800d272: 7d53 ldrb r3, [r2, #21] 800d274: f361 0300 bfi r3, r1, #0, #1 800d278: 7553 strb r3, [r2, #21] statusPacket.relayDC = RELAY_Read(RELAY_DC); 800d27a: 2003 movs r0, #3 800d27c: f7fc fb0c bl 8009898 800d280: 4603 mov r3, r0 800d282: f003 0301 and.w r3, r3, #1 800d286: b2d9 uxtb r1, r3 800d288: 4a67 ldr r2, [pc, #412] @ (800d428 ) 800d28a: 7d53 ldrb r3, [r2, #21] 800d28c: f361 0341 bfi r3, r1, #1, #1 800d290: 7553 strb r3, [r2, #21] statusPacket.relayAUX = RELAY_Read(RELAY_AUX0); 800d292: 2000 movs r0, #0 800d294: f7fc fb00 bl 8009898 800d298: 4603 mov r3, r0 800d29a: f003 0301 and.w r3, r3, #1 800d29e: b2d9 uxtb r1, r3 800d2a0: 4a61 ldr r2, [pc, #388] @ (800d428 ) 800d2a2: 7d53 ldrb r3, [r2, #21] 800d2a4: f361 0382 bfi r3, r1, #2, #1 800d2a8: 7553 strb r3, [r2, #21] statusPacket.lockState = 0; 800d2aa: 4a5f ldr r2, [pc, #380] @ (800d428 ) 800d2ac: 7d53 ldrb r3, [r2, #21] 800d2ae: f023 0308 bic.w r3, r3, #8 800d2b2: 7553 strb r3, [r2, #21] statusPacket.stopButton = !IN_ReadInput(IN_ESTOP); 800d2b4: 2003 movs r0, #3 800d2b6: f7fc faff bl 80098b8 800d2ba: 4603 mov r3, r0 800d2bc: 2b00 cmp r3, #0 800d2be: bf0c ite eq 800d2c0: 2301 moveq r3, #1 800d2c2: 2300 movne r3, #0 800d2c4: b2d9 uxtb r1, r3 800d2c6: 4a58 ldr r2, [pc, #352] @ (800d428 ) 800d2c8: 7d53 ldrb r3, [r2, #21] 800d2ca: f361 1304 bfi r3, r1, #4, #1 800d2ce: 7553 strb r3, [r2, #21] statusPacket.logAvailable = (debug_buffer_available()>0)?1:0; 800d2d0: f7fd f89a bl 800a408 800d2d4: 4603 mov r3, r0 800d2d6: 2b00 cmp r3, #0 800d2d8: bf14 ite ne 800d2da: 2301 movne r3, #1 800d2dc: 2300 moveq r3, #0 800d2de: b2d9 uxtb r1, r3 800d2e0: 4a51 ldr r2, [pc, #324] @ (800d428 ) 800d2e2: 7d53 ldrb r3, [r2, #21] 800d2e4: f361 1345 bfi r3, r1, #5, #1 800d2e8: 7553 strb r3, [r2, #21] statusPacket.evInfoAvailable = 0; 800d2ea: 4a4f ldr r2, [pc, #316] @ (800d428 ) 800d2ec: 7d53 ldrb r3, [r2, #21] 800d2ee: f023 0340 bic.w r3, r3, #64 @ 0x40 800d2f2: 7553 strb r3, [r2, #21] statusPacket.psuOnline = PSU0.online; 800d2f4: 4b4d ldr r3, [pc, #308] @ (800d42c ) 800d2f6: 7a1b ldrb r3, [r3, #8] 800d2f8: f003 0301 and.w r3, r3, #1 800d2fc: b2d9 uxtb r1, r3 800d2fe: 4a4a ldr r2, [pc, #296] @ (800d428 ) 800d300: 7d53 ldrb r3, [r2, #21] 800d302: f361 13c7 bfi r3, r1, #7, #1 800d306: 7553 strb r3, [r2, #21] statusPacket.tempConnector0 = CONN_ReadTemp(0); // температура коннектора 800d308: 2000 movs r0, #0 800d30a: f7fc fbcb bl 8009aa4 800d30e: 4603 mov r3, r0 800d310: b25a sxtb r2, r3 800d312: 4b45 ldr r3, [pc, #276] @ (800d428 ) 800d314: 765a strb r2, [r3, #25] statusPacket.tempConnector1 = CONN_ReadTemp(1); 800d316: 2001 movs r0, #1 800d318: f7fc fbc4 bl 8009aa4 800d31c: 4603 mov r3, r0 800d31e: b25a sxtb r2, r3 800d320: 4b41 ldr r3, [pc, #260] @ (800d428 ) 800d322: 769a strb r2, [r3, #26] statusPacket.tempAmbient = PSU0.tempAmbient; // температура окружающего воздуха 800d324: 4b41 ldr r3, [pc, #260] @ (800d42c ) 800d326: 6a1b ldr r3, [r3, #32] 800d328: b25a sxtb r2, r3 800d32a: 4b3f ldr r3, [pc, #252] @ (800d428 ) 800d32c: 76da strb r2, [r3, #27] statusPacket.tempBatteryMax = 0; 800d32e: 4b3e ldr r3, [pc, #248] @ (800d428 ) 800d330: 2200 movs r2, #0 800d332: 771a strb r2, [r3, #28] statusPacket.tempBatteryMin = 0; 800d334: 4b3c ldr r3, [pc, #240] @ (800d428 ) 800d336: 2200 movs r2, #0 800d338: 775a strb r2, [r3, #29] statusPacket.highestVoltageOfBatteryCell = 0; 800d33a: 4b3b ldr r3, [pc, #236] @ (800d428 ) 800d33c: 2200 movs r2, #0 800d33e: 779a strb r2, [r3, #30] 800d340: 2200 movs r2, #0 800d342: 77da strb r2, [r3, #31] statusPacket.batteryStatus = 0; 800d344: 4b38 ldr r3, [pc, #224] @ (800d428 ) 800d346: 2200 movs r2, #0 800d348: f883 2020 strb.w r2, [r3, #32] statusPacket.phaseVoltageAB = PSU_06.VAB; 800d34c: 4b38 ldr r3, [pc, #224] @ (800d430 ) 800d34e: 689b ldr r3, [r3, #8] 800d350: b29a uxth r2, r3 800d352: 4b35 ldr r3, [pc, #212] @ (800d428 ) 800d354: f8a3 2021 strh.w r2, [r3, #33] @ 0x21 statusPacket.phaseVoltageBC = PSU_06.VBC; 800d358: 4b35 ldr r3, [pc, #212] @ (800d430 ) 800d35a: 68db ldr r3, [r3, #12] 800d35c: b29a uxth r2, r3 800d35e: 4b32 ldr r3, [pc, #200] @ (800d428 ) 800d360: f8a3 2023 strh.w r2, [r3, #35] @ 0x23 statusPacket.phaseVoltageCA = PSU_06.VCA; 800d364: 4b32 ldr r3, [pc, #200] @ (800d430 ) 800d366: 691b ldr r3, [r3, #16] 800d368: b29a uxth r2, r3 800d36a: 4b2f ldr r3, [pc, #188] @ (800d428 ) 800d36c: f8a3 2025 strh.w r2, [r3, #37] @ 0x25 // GBT TODO memset(statusPacket.VIN, 0, sizeof(statusPacket.VIN)); 800d370: 2211 movs r2, #17 800d372: 2100 movs r1, #0 800d374: 482f ldr r0, [pc, #188] @ (800d434 ) 800d376: f007 fc67 bl 8014c48 // GBT TODO statusPacket.batteryType = 0; 800d37a: 4b2b ldr r3, [pc, #172] @ (800d428 ) 800d37c: 2200 movs r2, #0 800d37e: f883 2038 strb.w r2, [r3, #56] @ 0x38 statusPacket.batteryCapacity = 0; 800d382: 4b29 ldr r3, [pc, #164] @ (800d428 ) 800d384: 2200 movs r2, #0 800d386: f883 2039 strb.w r2, [r3, #57] @ 0x39 800d38a: 2200 movs r2, #0 800d38c: f883 203a strb.w r2, [r3, #58] @ 0x3a statusPacket.batteryVoltage = 0; 800d390: 4b25 ldr r3, [pc, #148] @ (800d428 ) 800d392: 2200 movs r2, #0 800d394: f883 203b strb.w r2, [r3, #59] @ 0x3b 800d398: 2200 movs r2, #0 800d39a: f883 203c strb.w r2, [r3, #60] @ 0x3c memset(statusPacket.batteryVendor, 0, sizeof(statusPacket.batteryVendor)); 800d39e: 2204 movs r2, #4 800d3a0: 2100 movs r1, #0 800d3a2: 4825 ldr r0, [pc, #148] @ (800d438 ) 800d3a4: f007 fc50 bl 8014c48 statusPacket.batterySN = 0; 800d3a8: 4b1f ldr r3, [pc, #124] @ (800d428 ) 800d3aa: 2200 movs r2, #0 800d3ac: f883 2041 strb.w r2, [r3, #65] @ 0x41 800d3b0: 2200 movs r2, #0 800d3b2: f883 2042 strb.w r2, [r3, #66] @ 0x42 800d3b6: 2200 movs r2, #0 800d3b8: f883 2043 strb.w r2, [r3, #67] @ 0x43 800d3bc: 2200 movs r2, #0 800d3be: f883 2044 strb.w r2, [r3, #68] @ 0x44 statusPacket.batteryManuD = 0; 800d3c2: 4b19 ldr r3, [pc, #100] @ (800d428 ) 800d3c4: 2200 movs r2, #0 800d3c6: f883 2047 strb.w r2, [r3, #71] @ 0x47 statusPacket.batteryManuM = 0; 800d3ca: 4b17 ldr r3, [pc, #92] @ (800d428 ) 800d3cc: 2200 movs r2, #0 800d3ce: f883 2046 strb.w r2, [r3, #70] @ 0x46 statusPacket.batteryManuY = 0; 800d3d2: 4b15 ldr r3, [pc, #84] @ (800d428 ) 800d3d4: 2200 movs r2, #0 800d3d6: f883 2045 strb.w r2, [r3, #69] @ 0x45 statusPacket.batteryCycleCount = 0; 800d3da: 4b13 ldr r3, [pc, #76] @ (800d428 ) 800d3dc: 2200 movs r2, #0 800d3de: f883 2048 strb.w r2, [r3, #72] @ 0x48 800d3e2: 2200 movs r2, #0 800d3e4: f883 2049 strb.w r2, [r3, #73] @ 0x49 statusPacket.ownAuto = 0; 800d3e8: 4b0f ldr r3, [pc, #60] @ (800d428 ) 800d3ea: 2200 movs r2, #0 800d3ec: f883 204a strb.w r2, [r3, #74] @ 0x4a memset(statusPacket.EV_SW_VER, 0, sizeof(statusPacket.EV_SW_VER)); 800d3f0: 2208 movs r2, #8 800d3f2: 2100 movs r1, #0 800d3f4: 4811 ldr r0, [pc, #68] @ (800d43c ) 800d3f6: f007 fc27 bl 8014c48 statusPacket.testMode = 0; 800d3fa: 4b0b ldr r3, [pc, #44] @ (800d428 ) 800d3fc: 2200 movs r2, #0 800d3fe: f883 2053 strb.w r2, [r3, #83] @ 0x53 statusPacket.testVoltage = 0; 800d402: 4b09 ldr r3, [pc, #36] @ (800d428 ) 800d404: 2200 movs r2, #0 800d406: f883 2054 strb.w r2, [r3, #84] @ 0x54 800d40a: 2200 movs r2, #0 800d40c: f883 2055 strb.w r2, [r3, #85] @ 0x55 statusPacket.testCurrent = 0; 800d410: 4b05 ldr r3, [pc, #20] @ (800d428 ) 800d412: 2200 movs r2, #0 800d414: f883 2056 strb.w r2, [r3, #86] @ 0x56 800d418: 2200 movs r2, #0 800d41a: f883 2057 strb.w r2, [r3, #87] @ 0x57 // В debug.c есть CONN_SetState, предполагаем наличие CONN_GetState() // Если такой функции нет, закомментируйте следующую строку: // statusPacket.connState = CONN_GetState(); } 800d41e: bf00 nop 800d420: bd80 pop {r7, pc} 800d422: bf00 nop 800d424: 200003b0 .word 0x200003b0 800d428: 20001158 .word 0x20001158 800d42c: 20000904 .word 0x20000904 800d430: 200008d8 .word 0x200008d8 800d434: 2000117f .word 0x2000117f 800d438: 20001195 .word 0x20001195 800d43c: 200011a3 .word 0x200011a3 0800d440 : #include "sma_filter.h" void SMAFilter_Init(SMAFilter_t* f) { 800d440: b480 push {r7} 800d442: b085 sub sp, #20 800d444: af00 add r7, sp, #0 800d446: 6078 str r0, [r7, #4] if (f == 0) return; 800d448: 687b ldr r3, [r7, #4] 800d44a: 2b00 cmp r3, #0 800d44c: d018 beq.n 800d480 f->sum = 0; 800d44e: 687b ldr r3, [r7, #4] 800d450: 2200 movs r2, #0 800d452: 601a str r2, [r3, #0] f->idx = 0; 800d454: 687b ldr r3, [r7, #4] 800d456: 2200 movs r2, #0 800d458: 809a strh r2, [r3, #4] f->count = 0; 800d45a: 687b ldr r3, [r7, #4] 800d45c: 2200 movs r2, #0 800d45e: 80da strh r2, [r3, #6] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800d460: 2300 movs r3, #0 800d462: 81fb strh r3, [r7, #14] 800d464: e008 b.n 800d478 f->buffer[i] = 0; 800d466: 89fa ldrh r2, [r7, #14] 800d468: 687b ldr r3, [r7, #4] 800d46a: 3202 adds r2, #2 800d46c: 2100 movs r1, #0 800d46e: f843 1022 str.w r1, [r3, r2, lsl #2] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800d472: 89fb ldrh r3, [r7, #14] 800d474: 3301 adds r3, #1 800d476: 81fb strh r3, [r7, #14] 800d478: 89fb ldrh r3, [r7, #14] 800d47a: 2b07 cmp r3, #7 800d47c: d9f3 bls.n 800d466 800d47e: e000 b.n 800d482 if (f == 0) return; 800d480: bf00 nop } } 800d482: 3714 adds r7, #20 800d484: 46bd mov sp, r7 800d486: bc80 pop {r7} 800d488: 4770 bx lr 0800d48a : int32_t SMAFilter_Update(SMAFilter_t* f, int32_t x) { 800d48a: b480 push {r7} 800d48c: b085 sub sp, #20 800d48e: af00 add r7, sp, #0 800d490: 6078 str r0, [r7, #4] 800d492: 6039 str r1, [r7, #0] if (f == 0) return x; 800d494: 687b ldr r3, [r7, #4] 800d496: 2b00 cmp r3, #0 800d498: d101 bne.n 800d49e 800d49a: 683b ldr r3, [r7, #0] 800d49c: e056 b.n 800d54c // Пока окно не заполнено полностью, делим по фактическому count. if (f->count < SMA_FILTER_WINDOW) { 800d49e: 687b ldr r3, [r7, #4] 800d4a0: 88db ldrh r3, [r3, #6] 800d4a2: 2b07 cmp r3, #7 800d4a4: d827 bhi.n 800d4f6 f->buffer[f->idx] = x; 800d4a6: 687b ldr r3, [r7, #4] 800d4a8: 889b ldrh r3, [r3, #4] 800d4aa: 461a mov r2, r3 800d4ac: 687b ldr r3, [r7, #4] 800d4ae: 3202 adds r2, #2 800d4b0: 6839 ldr r1, [r7, #0] 800d4b2: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += x; 800d4b6: 687b ldr r3, [r7, #4] 800d4b8: 681a ldr r2, [r3, #0] 800d4ba: 683b ldr r3, [r7, #0] 800d4bc: 441a add r2, r3 800d4be: 687b ldr r3, [r7, #4] 800d4c0: 601a str r2, [r3, #0] f->idx++; 800d4c2: 687b ldr r3, [r7, #4] 800d4c4: 889b ldrh r3, [r3, #4] 800d4c6: 3301 adds r3, #1 800d4c8: b29a uxth r2, r3 800d4ca: 687b ldr r3, [r7, #4] 800d4cc: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800d4ce: 687b ldr r3, [r7, #4] 800d4d0: 889b ldrh r3, [r3, #4] 800d4d2: 2b07 cmp r3, #7 800d4d4: d902 bls.n 800d4dc 800d4d6: 687b ldr r3, [r7, #4] 800d4d8: 2200 movs r2, #0 800d4da: 809a strh r2, [r3, #4] f->count++; 800d4dc: 687b ldr r3, [r7, #4] 800d4de: 88db ldrh r3, [r3, #6] 800d4e0: 3301 adds r3, #1 800d4e2: b29a uxth r2, r3 800d4e4: 687b ldr r3, [r7, #4] 800d4e6: 80da strh r2, [r3, #6] return (int32_t)(f->sum / (int32_t)f->count); 800d4e8: 687b ldr r3, [r7, #4] 800d4ea: 681b ldr r3, [r3, #0] 800d4ec: 687a ldr r2, [r7, #4] 800d4ee: 88d2 ldrh r2, [r2, #6] 800d4f0: fb93 f3f2 sdiv r3, r3, r2 800d4f4: e02a b.n 800d54c } // Окно заполнено: "вычитаем старое + добавляем новое". int32_t old = f->buffer[f->idx]; 800d4f6: 687b ldr r3, [r7, #4] 800d4f8: 889b ldrh r3, [r3, #4] 800d4fa: 461a mov r2, r3 800d4fc: 687b ldr r3, [r7, #4] 800d4fe: 3202 adds r2, #2 800d500: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800d504: 60fb str r3, [r7, #12] f->buffer[f->idx] = x; 800d506: 687b ldr r3, [r7, #4] 800d508: 889b ldrh r3, [r3, #4] 800d50a: 461a mov r2, r3 800d50c: 687b ldr r3, [r7, #4] 800d50e: 3202 adds r2, #2 800d510: 6839 ldr r1, [r7, #0] 800d512: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += (x - old); 800d516: 687b ldr r3, [r7, #4] 800d518: 681a ldr r2, [r3, #0] 800d51a: 6839 ldr r1, [r7, #0] 800d51c: 68fb ldr r3, [r7, #12] 800d51e: 1acb subs r3, r1, r3 800d520: 441a add r2, r3 800d522: 687b ldr r3, [r7, #4] 800d524: 601a str r2, [r3, #0] f->idx++; 800d526: 687b ldr r3, [r7, #4] 800d528: 889b ldrh r3, [r3, #4] 800d52a: 3301 adds r3, #1 800d52c: b29a uxth r2, r3 800d52e: 687b ldr r3, [r7, #4] 800d530: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800d532: 687b ldr r3, [r7, #4] 800d534: 889b ldrh r3, [r3, #4] 800d536: 2b07 cmp r3, #7 800d538: d902 bls.n 800d540 800d53a: 687b ldr r3, [r7, #4] 800d53c: 2200 movs r2, #0 800d53e: 809a strh r2, [r3, #4] return (int32_t)(f->sum / (int32_t)SMA_FILTER_WINDOW); 800d540: 687b ldr r3, [r7, #4] 800d542: 681b ldr r3, [r3, #0] 800d544: 2b00 cmp r3, #0 800d546: da00 bge.n 800d54a 800d548: 3307 adds r3, #7 800d54a: 10db asrs r3, r3, #3 } 800d54c: 4618 mov r0, r3 800d54e: 3714 adds r7, #20 800d550: 46bd mov sp, r7 800d552: bc80 pop {r7} 800d554: 4770 bx lr ... 0800d558 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800d558: b480 push {r7} 800d55a: b085 sub sp, #20 800d55c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 800d55e: 4b15 ldr r3, [pc, #84] @ (800d5b4 ) 800d560: 699b ldr r3, [r3, #24] 800d562: 4a14 ldr r2, [pc, #80] @ (800d5b4 ) 800d564: f043 0301 orr.w r3, r3, #1 800d568: 6193 str r3, [r2, #24] 800d56a: 4b12 ldr r3, [pc, #72] @ (800d5b4 ) 800d56c: 699b ldr r3, [r3, #24] 800d56e: f003 0301 and.w r3, r3, #1 800d572: 60bb str r3, [r7, #8] 800d574: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800d576: 4b0f ldr r3, [pc, #60] @ (800d5b4 ) 800d578: 69db ldr r3, [r3, #28] 800d57a: 4a0e ldr r2, [pc, #56] @ (800d5b4 ) 800d57c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800d580: 61d3 str r3, [r2, #28] 800d582: 4b0c ldr r3, [pc, #48] @ (800d5b4 ) 800d584: 69db ldr r3, [r3, #28] 800d586: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800d58a: 607b str r3, [r7, #4] 800d58c: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 800d58e: 4b0a ldr r3, [pc, #40] @ (800d5b8 ) 800d590: 685b ldr r3, [r3, #4] 800d592: 60fb str r3, [r7, #12] 800d594: 68fb ldr r3, [r7, #12] 800d596: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 800d59a: 60fb str r3, [r7, #12] 800d59c: 68fb ldr r3, [r7, #12] 800d59e: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 800d5a2: 60fb str r3, [r7, #12] 800d5a4: 4a04 ldr r2, [pc, #16] @ (800d5b8 ) 800d5a6: 68fb ldr r3, [r7, #12] 800d5a8: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800d5aa: bf00 nop 800d5ac: 3714 adds r7, #20 800d5ae: 46bd mov sp, r7 800d5b0: bc80 pop {r7} 800d5b2: 4770 bx lr 800d5b4: 40021000 .word 0x40021000 800d5b8: 40010000 .word 0x40010000 0800d5bc : { /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800d5bc: e7fe b.n 800d5bc 800d5be: bf00 nop 0800d5c0 : void HardFault_Handler(void) { /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800d5c0: e7fe b.n 800d5c0 800d5c2: bf00 nop 0800d5c4 : void MemManage_Handler(void) { /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800d5c4: e7fe b.n 800d5c4 800d5c6: bf00 nop 0800d5c8 : void BusFault_Handler(void) { /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800d5c8: e7fe b.n 800d5c8 800d5ca: bf00 nop 0800d5cc : void UsageFault_Handler(void) { /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 800d5cc: e7fe b.n 800d5cc 800d5ce: bf00 nop 0800d5d0 : /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800d5d0: 4770 bx lr 800d5d2: bf00 nop 0800d5d4 : /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800d5d4: 4770 bx lr 800d5d6: bf00 nop 0800d5d8 : /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800d5d8: 4770 bx lr 800d5da: bf00 nop 0800d5dc : void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800d5dc: f000 be68 b.w 800e2b0 0800d5e0 : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { 800d5e0: b510 push {r4, lr} /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800d5e2: 4c09 ldr r4, [pc, #36] @ (800d608 ) 800d5e4: 2201 movs r2, #1 800d5e6: f44f 6100 mov.w r1, #2048 @ 0x800 800d5ea: 4620 mov r0, r4 800d5ec: f003 fa09 bl 8010a02 /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 800d5f0: 4806 ldr r0, [pc, #24] @ (800d60c ) 800d5f2: f002 fdf7 bl 80101e4 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d5f6: 4620 mov r0, r4 /* USER CODE END DMA1_Channel1_IRQn 1 */ } 800d5f8: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d5fc: 2200 movs r2, #0 800d5fe: f44f 6100 mov.w r1, #2048 @ 0x800 800d602: f003 b9fe b.w 8010a02 800d606: bf00 nop 800d608: 40010c00 .word 0x40010c00 800d60c: 200002c0 .word 0x200002c0 0800d610 : void DMA1_Channel2_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ /* USER CODE END DMA1_Channel2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart3_tx); 800d610: 4801 ldr r0, [pc, #4] @ (800d618 ) 800d612: f002 bde7 b.w 80101e4 800d616: bf00 nop 800d618: 20001444 .word 0x20001444 0800d61c : void DMA1_Channel3_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel3_IRQn 0 */ /* USER CODE END DMA1_Channel3_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart3_rx); 800d61c: 4801 ldr r0, [pc, #4] @ (800d624 ) 800d61e: f002 bde1 b.w 80101e4 800d622: bf00 nop 800d624: 20001400 .word 0x20001400 0800d628 : void DMA1_Channel6_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel6_IRQn 0 */ /* USER CODE END DMA1_Channel6_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_rx); 800d628: 4801 ldr r0, [pc, #4] @ (800d630 ) 800d62a: f002 bddb b.w 80101e4 800d62e: bf00 nop 800d630: 20001378 .word 0x20001378 0800d634 : void DMA1_Channel7_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel7_IRQn 0 */ /* USER CODE END DMA1_Channel7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_tx); 800d634: 4801 ldr r0, [pc, #4] @ (800d63c ) 800d636: f002 bdd5 b.w 80101e4 800d63a: bf00 nop 800d63c: 200013bc .word 0x200013bc 0800d640 : /** * @brief This function handles ADC1 and ADC2 global interrupts. */ void ADC1_2_IRQHandler(void) { 800d640: b510 push {r4, lr} /* USER CODE BEGIN ADC1_2_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800d642: 4c09 ldr r4, [pc, #36] @ (800d668 ) 800d644: 2201 movs r2, #1 800d646: f44f 6100 mov.w r1, #2048 @ 0x800 800d64a: 4620 mov r0, r4 800d64c: f003 f9d9 bl 8010a02 /* USER CODE END ADC1_2_IRQn 0 */ HAL_ADC_IRQHandler(&hadc1); 800d650: 4806 ldr r0, [pc, #24] @ (800d66c ) 800d652: f001 f823 bl 800e69c /* USER CODE BEGIN ADC1_2_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d656: 4620 mov r0, r4 /* USER CODE END ADC1_2_IRQn 1 */ } 800d658: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d65c: 2200 movs r2, #0 800d65e: f44f 6100 mov.w r1, #2048 @ 0x800 800d662: f003 b9ce b.w 8010a02 800d666: bf00 nop 800d668: 40010c00 .word 0x40010c00 800d66c: 20000290 .word 0x20000290 0800d670 : /** * @brief This function handles CAN1 RX0 interrupt. */ void CAN1_RX0_IRQHandler(void) { 800d670: b510 push {r4, lr} /* USER CODE BEGIN CAN1_RX0_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800d672: 4c09 ldr r4, [pc, #36] @ (800d698 ) 800d674: 2201 movs r2, #1 800d676: f44f 6180 mov.w r1, #1024 @ 0x400 800d67a: 4620 mov r0, r4 800d67c: f003 f9c1 bl 8010a02 /* USER CODE END CAN1_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan1); 800d680: 4806 ldr r0, [pc, #24] @ (800d69c ) 800d682: f002 f847 bl 800f714 /* USER CODE BEGIN CAN1_RX0_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d686: 4620 mov r0, r4 /* USER CODE END CAN1_RX0_IRQn 1 */ } 800d688: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d68c: 2200 movs r2, #0 800d68e: f44f 6180 mov.w r1, #1024 @ 0x400 800d692: f003 b9b6 b.w 8010a02 800d696: bf00 nop 800d698: 40010c00 .word 0x40010c00 800d69c: 2000035c .word 0x2000035c 0800d6a0 : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 800d6a0: b510 push {r4, lr} /* USER CODE BEGIN TIM3_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800d6a2: 4c09 ldr r4, [pc, #36] @ (800d6c8 ) 800d6a4: 2201 movs r2, #1 800d6a6: f44f 6100 mov.w r1, #2048 @ 0x800 800d6aa: 4620 mov r0, r4 800d6ac: f003 f9a9 bl 8010a02 /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 800d6b0: 4806 ldr r0, [pc, #24] @ (800d6cc ) 800d6b2: f004 fd87 bl 80121c4 /* USER CODE BEGIN TIM3_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d6b6: 4620 mov r0, r4 /* USER CODE END TIM3_IRQn 1 */ } 800d6b8: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d6bc: 2200 movs r2, #0 800d6be: f44f 6100 mov.w r1, #2048 @ 0x800 800d6c2: f003 b99e b.w 8010a02 800d6c6: bf00 nop 800d6c8: 40010c00 .word 0x40010c00 800d6cc: 200011c8 .word 0x200011c8 0800d6d0 : void USART1_IRQHandler(void) { /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 800d6d0: 4801 ldr r0, [pc, #4] @ (800d6d8 ) 800d6d2: f005 be2d b.w 8013330 800d6d6: bf00 nop 800d6d8: 200012a0 .word 0x200012a0 0800d6dc : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 800d6dc: b510 push {r4, lr} /* USER CODE BEGIN USART2_IRQn 0 */ HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_SET); 800d6de: 4c08 ldr r4, [pc, #32] @ (800d700 ) 800d6e0: 2201 movs r2, #1 800d6e2: 2120 movs r1, #32 800d6e4: 4620 mov r0, r4 800d6e6: f003 f98c bl 8010a02 /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 800d6ea: 4806 ldr r0, [pc, #24] @ (800d704 ) 800d6ec: f005 fe20 bl 8013330 /* USER CODE BEGIN USART2_IRQn 1 */ HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_RESET); 800d6f0: 4620 mov r0, r4 /* USER CODE END USART2_IRQn 1 */ } 800d6f2: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_RESET); 800d6f6: 2200 movs r2, #0 800d6f8: 2120 movs r1, #32 800d6fa: f003 b982 b.w 8010a02 800d6fe: bf00 nop 800d700: 40010800 .word 0x40010800 800d704: 200012e8 .word 0x200012e8 0800d708 : /** * @brief This function handles USART3 global interrupt. */ void USART3_IRQHandler(void) { 800d708: b510 push {r4, lr} /* USER CODE BEGIN USART3_IRQn 0 */ HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_SET); 800d70a: 4c08 ldr r4, [pc, #32] @ (800d72c ) 800d70c: 2201 movs r2, #1 800d70e: 2140 movs r1, #64 @ 0x40 800d710: 4620 mov r0, r4 800d712: f003 f976 bl 8010a02 /* USER CODE END USART3_IRQn 0 */ HAL_UART_IRQHandler(&huart3); 800d716: 4806 ldr r0, [pc, #24] @ (800d730 ) 800d718: f005 fe0a bl 8013330 /* USER CODE BEGIN USART3_IRQn 1 */ HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_RESET); 800d71c: 4620 mov r0, r4 /* USER CODE END USART3_IRQn 1 */ } 800d71e: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_RESET); 800d722: 2200 movs r2, #0 800d724: 2140 movs r1, #64 @ 0x40 800d726: f003 b96c b.w 8010a02 800d72a: bf00 nop 800d72c: 40010800 .word 0x40010800 800d730: 20001330 .word 0x20001330 0800d734 : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 800d734: b510 push {r4, lr} /* USER CODE BEGIN UART5_IRQn 0 */ HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_SET); 800d736: 4c08 ldr r4, [pc, #32] @ (800d758 ) 800d738: 2201 movs r2, #1 800d73a: 2104 movs r1, #4 800d73c: 4620 mov r0, r4 800d73e: f003 f960 bl 8010a02 /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 800d742: 4806 ldr r0, [pc, #24] @ (800d75c ) 800d744: f005 fdf4 bl 8013330 /* USER CODE BEGIN UART5_IRQn 1 */ HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_RESET); 800d748: 4620 mov r0, r4 /* USER CODE END UART5_IRQn 1 */ } 800d74a: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_RESET); 800d74e: 2200 movs r2, #0 800d750: 2104 movs r1, #4 800d752: f003 b956 b.w 8010a02 800d756: bf00 nop 800d758: 40011000 .word 0x40011000 800d75c: 20001258 .word 0x20001258 0800d760 : /** * @brief This function handles CAN2 TX interrupt. */ void CAN2_TX_IRQHandler(void) { 800d760: b510 push {r4, lr} /* USER CODE BEGIN CAN2_TX_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800d762: 4c09 ldr r4, [pc, #36] @ (800d788 ) 800d764: 2201 movs r2, #1 800d766: f44f 6180 mov.w r1, #1024 @ 0x400 800d76a: 4620 mov r0, r4 800d76c: f003 f949 bl 8010a02 /* USER CODE END CAN2_TX_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800d770: 4806 ldr r0, [pc, #24] @ (800d78c ) 800d772: f001 ffcf bl 800f714 /* USER CODE BEGIN CAN2_TX_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d776: 4620 mov r0, r4 /* USER CODE END CAN2_TX_IRQn 1 */ } 800d778: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d77c: 2200 movs r2, #0 800d77e: f44f 6180 mov.w r1, #1024 @ 0x400 800d782: f003 b93e b.w 8010a02 800d786: bf00 nop 800d788: 40010c00 .word 0x40010c00 800d78c: 20000384 .word 0x20000384 0800d790 : /** * @brief This function handles CAN2 RX1 interrupt. */ void CAN2_RX1_IRQHandler(void) { 800d790: b510 push {r4, lr} /* USER CODE BEGIN CAN2_RX1_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800d792: 4c09 ldr r4, [pc, #36] @ (800d7b8 ) 800d794: 2201 movs r2, #1 800d796: f44f 6180 mov.w r1, #1024 @ 0x400 800d79a: 4620 mov r0, r4 800d79c: f003 f931 bl 8010a02 /* USER CODE END CAN2_RX1_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800d7a0: 4806 ldr r0, [pc, #24] @ (800d7bc ) 800d7a2: f001 ffb7 bl 800f714 /* USER CODE BEGIN CAN2_RX1_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d7a6: 4620 mov r0, r4 /* USER CODE END CAN2_RX1_IRQn 1 */ } 800d7a8: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d7ac: 2200 movs r2, #0 800d7ae: f44f 6180 mov.w r1, #1024 @ 0x400 800d7b2: f003 b926 b.w 8010a02 800d7b6: bf00 nop 800d7b8: 40010c00 .word 0x40010c00 800d7bc: 20000384 .word 0x20000384 0800d7c0 <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 800d7c0: b480 push {r7} 800d7c2: af00 add r7, sp, #0 return 1; 800d7c4: 2301 movs r3, #1 } 800d7c6: 4618 mov r0, r3 800d7c8: 46bd mov sp, r7 800d7ca: bc80 pop {r7} 800d7cc: 4770 bx lr 0800d7ce <_kill>: int _kill(int pid, int sig) { 800d7ce: b580 push {r7, lr} 800d7d0: b082 sub sp, #8 800d7d2: af00 add r7, sp, #0 800d7d4: 6078 str r0, [r7, #4] 800d7d6: 6039 str r1, [r7, #0] (void)pid; (void)sig; errno = EINVAL; 800d7d8: f007 fa3e bl 8014c58 <__errno> 800d7dc: 4603 mov r3, r0 800d7de: 2216 movs r2, #22 800d7e0: 601a str r2, [r3, #0] return -1; 800d7e2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800d7e6: 4618 mov r0, r3 800d7e8: 3708 adds r7, #8 800d7ea: 46bd mov sp, r7 800d7ec: bd80 pop {r7, pc} 0800d7ee <_exit>: void _exit (int status) { 800d7ee: b580 push {r7, lr} 800d7f0: b082 sub sp, #8 800d7f2: af00 add r7, sp, #0 800d7f4: 6078 str r0, [r7, #4] _kill(status, -1); 800d7f6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800d7fa: 6878 ldr r0, [r7, #4] 800d7fc: f7ff ffe7 bl 800d7ce <_kill> while (1) {} /* Make sure we hang here */ 800d800: bf00 nop 800d802: e7fd b.n 800d800 <_exit+0x12> 0800d804 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 800d804: b580 push {r7, lr} 800d806: b086 sub sp, #24 800d808: af00 add r7, sp, #0 800d80a: 60f8 str r0, [r7, #12] 800d80c: 60b9 str r1, [r7, #8] 800d80e: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800d810: 2300 movs r3, #0 800d812: 617b str r3, [r7, #20] 800d814: e00a b.n 800d82c <_read+0x28> { *ptr++ = __io_getchar(); 800d816: f3af 8000 nop.w 800d81a: 4601 mov r1, r0 800d81c: 68bb ldr r3, [r7, #8] 800d81e: 1c5a adds r2, r3, #1 800d820: 60ba str r2, [r7, #8] 800d822: b2ca uxtb r2, r1 800d824: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 800d826: 697b ldr r3, [r7, #20] 800d828: 3301 adds r3, #1 800d82a: 617b str r3, [r7, #20] 800d82c: 697a ldr r2, [r7, #20] 800d82e: 687b ldr r3, [r7, #4] 800d830: 429a cmp r2, r3 800d832: dbf0 blt.n 800d816 <_read+0x12> } return len; 800d834: 687b ldr r3, [r7, #4] } 800d836: 4618 mov r0, r3 800d838: 3718 adds r7, #24 800d83a: 46bd mov sp, r7 800d83c: bd80 pop {r7, pc} 0800d83e <_close>: } return len; } int _close(int file) { 800d83e: b480 push {r7} 800d840: b083 sub sp, #12 800d842: af00 add r7, sp, #0 800d844: 6078 str r0, [r7, #4] (void)file; return -1; 800d846: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800d84a: 4618 mov r0, r3 800d84c: 370c adds r7, #12 800d84e: 46bd mov sp, r7 800d850: bc80 pop {r7} 800d852: 4770 bx lr 0800d854 <_fstat>: int _fstat(int file, struct stat *st) { 800d854: b480 push {r7} 800d856: b083 sub sp, #12 800d858: af00 add r7, sp, #0 800d85a: 6078 str r0, [r7, #4] 800d85c: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 800d85e: 683b ldr r3, [r7, #0] 800d860: f44f 5200 mov.w r2, #8192 @ 0x2000 800d864: 605a str r2, [r3, #4] return 0; 800d866: 2300 movs r3, #0 } 800d868: 4618 mov r0, r3 800d86a: 370c adds r7, #12 800d86c: 46bd mov sp, r7 800d86e: bc80 pop {r7} 800d870: 4770 bx lr 0800d872 <_isatty>: int _isatty(int file) { 800d872: b480 push {r7} 800d874: b083 sub sp, #12 800d876: af00 add r7, sp, #0 800d878: 6078 str r0, [r7, #4] (void)file; return 1; 800d87a: 2301 movs r3, #1 } 800d87c: 4618 mov r0, r3 800d87e: 370c adds r7, #12 800d880: 46bd mov sp, r7 800d882: bc80 pop {r7} 800d884: 4770 bx lr 0800d886 <_lseek>: int _lseek(int file, int ptr, int dir) { 800d886: b480 push {r7} 800d888: b085 sub sp, #20 800d88a: af00 add r7, sp, #0 800d88c: 60f8 str r0, [r7, #12] 800d88e: 60b9 str r1, [r7, #8] 800d890: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 800d892: 2300 movs r3, #0 } 800d894: 4618 mov r0, r3 800d896: 3714 adds r7, #20 800d898: 46bd mov sp, r7 800d89a: bc80 pop {r7} 800d89c: 4770 bx lr ... 0800d8a0 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 800d8a0: b580 push {r7, lr} 800d8a2: b086 sub sp, #24 800d8a4: af00 add r7, sp, #0 800d8a6: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 800d8a8: 4a14 ldr r2, [pc, #80] @ (800d8fc <_sbrk+0x5c>) 800d8aa: 4b15 ldr r3, [pc, #84] @ (800d900 <_sbrk+0x60>) 800d8ac: 1ad3 subs r3, r2, r3 800d8ae: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 800d8b0: 697b ldr r3, [r7, #20] 800d8b2: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 800d8b4: 4b13 ldr r3, [pc, #76] @ (800d904 <_sbrk+0x64>) 800d8b6: 681b ldr r3, [r3, #0] 800d8b8: 2b00 cmp r3, #0 800d8ba: d102 bne.n 800d8c2 <_sbrk+0x22> { __sbrk_heap_end = &_end; 800d8bc: 4b11 ldr r3, [pc, #68] @ (800d904 <_sbrk+0x64>) 800d8be: 4a12 ldr r2, [pc, #72] @ (800d908 <_sbrk+0x68>) 800d8c0: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 800d8c2: 4b10 ldr r3, [pc, #64] @ (800d904 <_sbrk+0x64>) 800d8c4: 681a ldr r2, [r3, #0] 800d8c6: 687b ldr r3, [r7, #4] 800d8c8: 4413 add r3, r2 800d8ca: 693a ldr r2, [r7, #16] 800d8cc: 429a cmp r2, r3 800d8ce: d207 bcs.n 800d8e0 <_sbrk+0x40> { errno = ENOMEM; 800d8d0: f007 f9c2 bl 8014c58 <__errno> 800d8d4: 4603 mov r3, r0 800d8d6: 220c movs r2, #12 800d8d8: 601a str r2, [r3, #0] return (void *)-1; 800d8da: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800d8de: e009 b.n 800d8f4 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 800d8e0: 4b08 ldr r3, [pc, #32] @ (800d904 <_sbrk+0x64>) 800d8e2: 681b ldr r3, [r3, #0] 800d8e4: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 800d8e6: 4b07 ldr r3, [pc, #28] @ (800d904 <_sbrk+0x64>) 800d8e8: 681a ldr r2, [r3, #0] 800d8ea: 687b ldr r3, [r7, #4] 800d8ec: 4413 add r3, r2 800d8ee: 4a05 ldr r2, [pc, #20] @ (800d904 <_sbrk+0x64>) 800d8f0: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 800d8f2: 68fb ldr r3, [r7, #12] } 800d8f4: 4618 mov r0, r3 800d8f6: 3718 adds r7, #24 800d8f8: 46bd mov sp, r7 800d8fa: bd80 pop {r7, pc} 800d8fc: 20010000 .word 0x20010000 800d900: 00000400 .word 0x00000400 800d904: 200011c4 .word 0x200011c4 800d908: 200015d8 .word 0x200015d8 0800d90c : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 800d90c: b480 push {r7} 800d90e: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 800d910: bf00 nop 800d912: 46bd mov sp, r7 800d914: bc80 pop {r7} 800d916: 4770 bx lr 0800d918 : TIM_HandleTypeDef htim3; TIM_HandleTypeDef htim4; /* TIM3 init function */ void MX_TIM3_Init(void) { 800d918: b580 push {r7, lr} 800d91a: b08e sub sp, #56 @ 0x38 800d91c: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800d91e: f107 0328 add.w r3, r7, #40 @ 0x28 800d922: 2200 movs r2, #0 800d924: 601a str r2, [r3, #0] 800d926: 605a str r2, [r3, #4] 800d928: 609a str r2, [r3, #8] 800d92a: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800d92c: f107 0320 add.w r3, r7, #32 800d930: 2200 movs r2, #0 800d932: 601a str r2, [r3, #0] 800d934: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800d936: 1d3b adds r3, r7, #4 800d938: 2200 movs r2, #0 800d93a: 601a str r2, [r3, #0] 800d93c: 605a str r2, [r3, #4] 800d93e: 609a str r2, [r3, #8] 800d940: 60da str r2, [r3, #12] 800d942: 611a str r2, [r3, #16] 800d944: 615a str r2, [r3, #20] 800d946: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 800d948: 4b38 ldr r3, [pc, #224] @ (800da2c ) 800d94a: 4a39 ldr r2, [pc, #228] @ (800da30 ) 800d94c: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 800d94e: 4b37 ldr r3, [pc, #220] @ (800da2c ) 800d950: 2200 movs r2, #0 800d952: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 800d954: 4b35 ldr r3, [pc, #212] @ (800da2c ) 800d956: 2200 movs r2, #0 800d958: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 800d95a: 4b34 ldr r3, [pc, #208] @ (800da2c ) 800d95c: f64f 72ff movw r2, #65535 @ 0xffff 800d960: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800d962: 4b32 ldr r3, [pc, #200] @ (800da2c ) 800d964: 2200 movs r2, #0 800d966: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800d968: 4b30 ldr r3, [pc, #192] @ (800da2c ) 800d96a: 2200 movs r2, #0 800d96c: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 800d96e: 482f ldr r0, [pc, #188] @ (800da2c ) 800d970: f004 f9d5 bl 8011d1e 800d974: 4603 mov r3, r0 800d976: 2b00 cmp r3, #0 800d978: d001 beq.n 800d97e { Error_Handler(); 800d97a: f7fd f951 bl 800ac20 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800d97e: f44f 5380 mov.w r3, #4096 @ 0x1000 800d982: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 800d984: f107 0328 add.w r3, r7, #40 @ 0x28 800d988: 4619 mov r1, r3 800d98a: 4828 ldr r0, [pc, #160] @ (800da2c ) 800d98c: f004 fe28 bl 80125e0 800d990: 4603 mov r3, r0 800d992: 2b00 cmp r3, #0 800d994: d001 beq.n 800d99a { Error_Handler(); 800d996: f7fd f943 bl 800ac20 } if (HAL_TIM_OC_Init(&htim3) != HAL_OK) 800d99a: 4824 ldr r0, [pc, #144] @ (800da2c ) 800d99c: f004 fa0e bl 8011dbc 800d9a0: 4603 mov r3, r0 800d9a2: 2b00 cmp r3, #0 800d9a4: d001 beq.n 800d9aa { Error_Handler(); 800d9a6: f7fd f93b bl 800ac20 } if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 800d9aa: 4820 ldr r0, [pc, #128] @ (800da2c ) 800d9ac: f004 fb08 bl 8011fc0 800d9b0: 4603 mov r3, r0 800d9b2: 2b00 cmp r3, #0 800d9b4: d001 beq.n 800d9ba { Error_Handler(); 800d9b6: f7fd f933 bl 800ac20 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_OC1; 800d9ba: 2330 movs r3, #48 @ 0x30 800d9bc: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800d9be: 2300 movs r3, #0 800d9c0: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800d9c2: f107 0320 add.w r3, r7, #32 800d9c6: 4619 mov r1, r3 800d9c8: 4818 ldr r0, [pc, #96] @ (800da2c ) 800d9ca: f005 f9b7 bl 8012d3c 800d9ce: 4603 mov r3, r0 800d9d0: 2b00 cmp r3, #0 800d9d2: d001 beq.n 800d9d8 { Error_Handler(); 800d9d4: f7fd f924 bl 800ac20 } sConfigOC.OCMode = TIM_OCMODE_TIMING; 800d9d8: 2300 movs r3, #0 800d9da: 607b str r3, [r7, #4] sConfigOC.Pulse = 1; 800d9dc: 2301 movs r3, #1 800d9de: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800d9e0: 2300 movs r3, #0 800d9e2: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800d9e4: 2300 movs r3, #0 800d9e6: 617b str r3, [r7, #20] if (HAL_TIM_OC_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 800d9e8: 1d3b adds r3, r7, #4 800d9ea: 2200 movs r2, #0 800d9ec: 4619 mov r1, r3 800d9ee: 480f ldr r0, [pc, #60] @ (800da2c ) 800d9f0: f004 fcd8 bl 80123a4 800d9f4: 4603 mov r3, r0 800d9f6: 2b00 cmp r3, #0 800d9f8: d001 beq.n 800d9fe { Error_Handler(); 800d9fa: f7fd f911 bl 800ac20 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800d9fe: 2360 movs r3, #96 @ 0x60 800da00: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800da02: 2300 movs r3, #0 800da04: 60bb str r3, [r7, #8] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800da06: 1d3b adds r3, r7, #4 800da08: 2204 movs r2, #4 800da0a: 4619 mov r1, r3 800da0c: 4807 ldr r0, [pc, #28] @ (800da2c ) 800da0e: f004 fd25 bl 801245c 800da12: 4603 mov r3, r0 800da14: 2b00 cmp r3, #0 800da16: d001 beq.n 800da1c { Error_Handler(); 800da18: f7fd f902 bl 800ac20 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 800da1c: 4803 ldr r0, [pc, #12] @ (800da2c ) 800da1e: f000 f8cf bl 800dbc0 } 800da22: bf00 nop 800da24: 3738 adds r7, #56 @ 0x38 800da26: 46bd mov sp, r7 800da28: bd80 pop {r7, pc} 800da2a: bf00 nop 800da2c: 200011c8 .word 0x200011c8 800da30: 40000400 .word 0x40000400 0800da34 : /* TIM4 init function */ void MX_TIM4_Init(void) { 800da34: b580 push {r7, lr} 800da36: b08e sub sp, #56 @ 0x38 800da38: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800da3a: f107 0328 add.w r3, r7, #40 @ 0x28 800da3e: 2200 movs r2, #0 800da40: 601a str r2, [r3, #0] 800da42: 605a str r2, [r3, #4] 800da44: 609a str r2, [r3, #8] 800da46: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800da48: f107 0320 add.w r3, r7, #32 800da4c: 2200 movs r2, #0 800da4e: 601a str r2, [r3, #0] 800da50: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800da52: 1d3b adds r3, r7, #4 800da54: 2200 movs r2, #0 800da56: 601a str r2, [r3, #0] 800da58: 605a str r2, [r3, #4] 800da5a: 609a str r2, [r3, #8] 800da5c: 60da str r2, [r3, #12] 800da5e: 611a str r2, [r3, #16] 800da60: 615a str r2, [r3, #20] 800da62: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM4_Init 1 */ /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; 800da64: 4b37 ldr r3, [pc, #220] @ (800db44 ) 800da66: 4a38 ldr r2, [pc, #224] @ (800db48 ) 800da68: 601a str r2, [r3, #0] htim4.Init.Prescaler = 720; 800da6a: 4b36 ldr r3, [pc, #216] @ (800db44 ) 800da6c: f44f 7234 mov.w r2, #720 @ 0x2d0 800da70: 605a str r2, [r3, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 800da72: 4b34 ldr r3, [pc, #208] @ (800db44 ) 800da74: 2200 movs r2, #0 800da76: 609a str r2, [r3, #8] htim4.Init.Period = 100; 800da78: 4b32 ldr r3, [pc, #200] @ (800db44 ) 800da7a: 2264 movs r2, #100 @ 0x64 800da7c: 60da str r2, [r3, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800da7e: 4b31 ldr r3, [pc, #196] @ (800db44 ) 800da80: 2200 movs r2, #0 800da82: 611a str r2, [r3, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800da84: 4b2f ldr r3, [pc, #188] @ (800db44 ) 800da86: 2200 movs r2, #0 800da88: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 800da8a: 482e ldr r0, [pc, #184] @ (800db44 ) 800da8c: f004 f947 bl 8011d1e 800da90: 4603 mov r3, r0 800da92: 2b00 cmp r3, #0 800da94: d001 beq.n 800da9a { Error_Handler(); 800da96: f7fd f8c3 bl 800ac20 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800da9a: f44f 5380 mov.w r3, #4096 @ 0x1000 800da9e: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 800daa0: f107 0328 add.w r3, r7, #40 @ 0x28 800daa4: 4619 mov r1, r3 800daa6: 4827 ldr r0, [pc, #156] @ (800db44 ) 800daa8: f004 fd9a bl 80125e0 800daac: 4603 mov r3, r0 800daae: 2b00 cmp r3, #0 800dab0: d001 beq.n 800dab6 { Error_Handler(); 800dab2: f7fd f8b5 bl 800ac20 } if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) 800dab6: 4823 ldr r0, [pc, #140] @ (800db44 ) 800dab8: f004 fa82 bl 8011fc0 800dabc: 4603 mov r3, r0 800dabe: 2b00 cmp r3, #0 800dac0: d001 beq.n 800dac6 { Error_Handler(); 800dac2: f7fd f8ad bl 800ac20 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800dac6: 2300 movs r3, #0 800dac8: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800daca: 2300 movs r3, #0 800dacc: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 800dace: f107 0320 add.w r3, r7, #32 800dad2: 4619 mov r1, r3 800dad4: 481b ldr r0, [pc, #108] @ (800db44 ) 800dad6: f005 f931 bl 8012d3c 800dada: 4603 mov r3, r0 800dadc: 2b00 cmp r3, #0 800dade: d001 beq.n 800dae4 { Error_Handler(); 800dae0: f7fd f89e bl 800ac20 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800dae4: 2360 movs r3, #96 @ 0x60 800dae6: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800dae8: 2300 movs r3, #0 800daea: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800daec: 2300 movs r3, #0 800daee: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800daf0: 2300 movs r3, #0 800daf2: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800daf4: 1d3b adds r3, r7, #4 800daf6: 2204 movs r2, #4 800daf8: 4619 mov r1, r3 800dafa: 4812 ldr r0, [pc, #72] @ (800db44 ) 800dafc: f004 fcae bl 801245c 800db00: 4603 mov r3, r0 800db02: 2b00 cmp r3, #0 800db04: d001 beq.n 800db0a { Error_Handler(); 800db06: f7fd f88b bl 800ac20 } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 800db0a: 1d3b adds r3, r7, #4 800db0c: 2208 movs r2, #8 800db0e: 4619 mov r1, r3 800db10: 480c ldr r0, [pc, #48] @ (800db44 ) 800db12: f004 fca3 bl 801245c 800db16: 4603 mov r3, r0 800db18: 2b00 cmp r3, #0 800db1a: d001 beq.n 800db20 { Error_Handler(); 800db1c: f7fd f880 bl 800ac20 } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 800db20: 1d3b adds r3, r7, #4 800db22: 220c movs r2, #12 800db24: 4619 mov r1, r3 800db26: 4807 ldr r0, [pc, #28] @ (800db44 ) 800db28: f004 fc98 bl 801245c 800db2c: 4603 mov r3, r0 800db2e: 2b00 cmp r3, #0 800db30: d001 beq.n 800db36 { Error_Handler(); 800db32: f7fd f875 bl 800ac20 } /* USER CODE BEGIN TIM4_Init 2 */ /* USER CODE END TIM4_Init 2 */ HAL_TIM_MspPostInit(&htim4); 800db36: 4803 ldr r0, [pc, #12] @ (800db44 ) 800db38: f000 f842 bl 800dbc0 } 800db3c: bf00 nop 800db3e: 3738 adds r7, #56 @ 0x38 800db40: 46bd mov sp, r7 800db42: bd80 pop {r7, pc} 800db44: 20001210 .word 0x20001210 800db48: 40000800 .word 0x40000800 0800db4c : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 800db4c: b580 push {r7, lr} 800db4e: b084 sub sp, #16 800db50: af00 add r7, sp, #0 800db52: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM3) 800db54: 687b ldr r3, [r7, #4] 800db56: 681b ldr r3, [r3, #0] 800db58: 4a16 ldr r2, [pc, #88] @ (800dbb4 ) 800db5a: 4293 cmp r3, r2 800db5c: d114 bne.n 800db88 { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 800db5e: 4b16 ldr r3, [pc, #88] @ (800dbb8 ) 800db60: 69db ldr r3, [r3, #28] 800db62: 4a15 ldr r2, [pc, #84] @ (800dbb8 ) 800db64: f043 0302 orr.w r3, r3, #2 800db68: 61d3 str r3, [r2, #28] 800db6a: 4b13 ldr r3, [pc, #76] @ (800dbb8 ) 800db6c: 69db ldr r3, [r3, #28] 800db6e: f003 0302 and.w r3, r3, #2 800db72: 60fb str r3, [r7, #12] 800db74: 68fb ldr r3, [r7, #12] /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 6, 0); 800db76: 2200 movs r2, #0 800db78: 2106 movs r1, #6 800db7a: 201d movs r0, #29 800db7c: f002 f8c5 bl 800fd0a HAL_NVIC_EnableIRQ(TIM3_IRQn); 800db80: 201d movs r0, #29 800db82: f002 f8de bl 800fd42 __HAL_RCC_TIM4_CLK_ENABLE(); /* USER CODE BEGIN TIM4_MspInit 1 */ /* USER CODE END TIM4_MspInit 1 */ } } 800db86: e010 b.n 800dbaa else if(tim_baseHandle->Instance==TIM4) 800db88: 687b ldr r3, [r7, #4] 800db8a: 681b ldr r3, [r3, #0] 800db8c: 4a0b ldr r2, [pc, #44] @ (800dbbc ) 800db8e: 4293 cmp r3, r2 800db90: d10b bne.n 800dbaa __HAL_RCC_TIM4_CLK_ENABLE(); 800db92: 4b09 ldr r3, [pc, #36] @ (800dbb8 ) 800db94: 69db ldr r3, [r3, #28] 800db96: 4a08 ldr r2, [pc, #32] @ (800dbb8 ) 800db98: f043 0304 orr.w r3, r3, #4 800db9c: 61d3 str r3, [r2, #28] 800db9e: 4b06 ldr r3, [pc, #24] @ (800dbb8 ) 800dba0: 69db ldr r3, [r3, #28] 800dba2: f003 0304 and.w r3, r3, #4 800dba6: 60bb str r3, [r7, #8] 800dba8: 68bb ldr r3, [r7, #8] } 800dbaa: bf00 nop 800dbac: 3710 adds r7, #16 800dbae: 46bd mov sp, r7 800dbb0: bd80 pop {r7, pc} 800dbb2: bf00 nop 800dbb4: 40000400 .word 0x40000400 800dbb8: 40021000 .word 0x40021000 800dbbc: 40000800 .word 0x40000800 0800dbc0 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 800dbc0: b580 push {r7, lr} 800dbc2: b08a sub sp, #40 @ 0x28 800dbc4: af00 add r7, sp, #0 800dbc6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800dbc8: f107 0314 add.w r3, r7, #20 800dbcc: 2200 movs r2, #0 800dbce: 601a str r2, [r3, #0] 800dbd0: 605a str r2, [r3, #4] 800dbd2: 609a str r2, [r3, #8] 800dbd4: 60da str r2, [r3, #12] if(timHandle->Instance==TIM3) 800dbd6: 687b ldr r3, [r7, #4] 800dbd8: 681b ldr r3, [r3, #0] 800dbda: 4a26 ldr r2, [pc, #152] @ (800dc74 ) 800dbdc: 4293 cmp r3, r2 800dbde: d118 bne.n 800dc12 { /* USER CODE BEGIN TIM3_MspPostInit 0 */ /* USER CODE END TIM3_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800dbe0: 4b25 ldr r3, [pc, #148] @ (800dc78 ) 800dbe2: 699b ldr r3, [r3, #24] 800dbe4: 4a24 ldr r2, [pc, #144] @ (800dc78 ) 800dbe6: f043 0304 orr.w r3, r3, #4 800dbea: 6193 str r3, [r2, #24] 800dbec: 4b22 ldr r3, [pc, #136] @ (800dc78 ) 800dbee: 699b ldr r3, [r3, #24] 800dbf0: f003 0304 and.w r3, r3, #4 800dbf4: 613b str r3, [r7, #16] 800dbf6: 693b ldr r3, [r7, #16] /**TIM3 GPIO Configuration PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = CP_PWM_Pin; 800dbf8: 2380 movs r3, #128 @ 0x80 800dbfa: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800dbfc: 2302 movs r3, #2 800dbfe: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800dc00: 2302 movs r3, #2 800dc02: 623b str r3, [r7, #32] HAL_GPIO_Init(CP_PWM_GPIO_Port, &GPIO_InitStruct); 800dc04: f107 0314 add.w r3, r7, #20 800dc08: 4619 mov r1, r3 800dc0a: 481c ldr r0, [pc, #112] @ (800dc7c ) 800dc0c: f002 fd5e bl 80106cc /* USER CODE BEGIN TIM4_MspPostInit 1 */ /* USER CODE END TIM4_MspPostInit 1 */ } } 800dc10: e02b b.n 800dc6a else if(timHandle->Instance==TIM4) 800dc12: 687b ldr r3, [r7, #4] 800dc14: 681b ldr r3, [r3, #0] 800dc16: 4a1a ldr r2, [pc, #104] @ (800dc80 ) 800dc18: 4293 cmp r3, r2 800dc1a: d126 bne.n 800dc6a __HAL_RCC_GPIOD_CLK_ENABLE(); 800dc1c: 4b16 ldr r3, [pc, #88] @ (800dc78 ) 800dc1e: 699b ldr r3, [r3, #24] 800dc20: 4a15 ldr r2, [pc, #84] @ (800dc78 ) 800dc22: f043 0320 orr.w r3, r3, #32 800dc26: 6193 str r3, [r2, #24] 800dc28: 4b13 ldr r3, [pc, #76] @ (800dc78 ) 800dc2a: 699b ldr r3, [r3, #24] 800dc2c: f003 0320 and.w r3, r3, #32 800dc30: 60fb str r3, [r7, #12] 800dc32: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; 800dc34: f44f 4360 mov.w r3, #57344 @ 0xe000 800dc38: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800dc3a: 2302 movs r3, #2 800dc3c: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800dc3e: 2302 movs r3, #2 800dc40: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800dc42: f107 0314 add.w r3, r7, #20 800dc46: 4619 mov r1, r3 800dc48: 480e ldr r0, [pc, #56] @ (800dc84 ) 800dc4a: f002 fd3f bl 80106cc __HAL_AFIO_REMAP_TIM4_ENABLE(); 800dc4e: 4b0e ldr r3, [pc, #56] @ (800dc88 ) 800dc50: 685b ldr r3, [r3, #4] 800dc52: 627b str r3, [r7, #36] @ 0x24 800dc54: 6a7b ldr r3, [r7, #36] @ 0x24 800dc56: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800dc5a: 627b str r3, [r7, #36] @ 0x24 800dc5c: 6a7b ldr r3, [r7, #36] @ 0x24 800dc5e: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800dc62: 627b str r3, [r7, #36] @ 0x24 800dc64: 4a08 ldr r2, [pc, #32] @ (800dc88 ) 800dc66: 6a7b ldr r3, [r7, #36] @ 0x24 800dc68: 6053 str r3, [r2, #4] } 800dc6a: bf00 nop 800dc6c: 3728 adds r7, #40 @ 0x28 800dc6e: 46bd mov sp, r7 800dc70: bd80 pop {r7, pc} 800dc72: bf00 nop 800dc74: 40000400 .word 0x40000400 800dc78: 40021000 .word 0x40021000 800dc7c: 40010800 .word 0x40010800 800dc80: 40000800 .word 0x40000800 800dc84: 40011400 .word 0x40011400 800dc88: 40010000 .word 0x40010000 0800dc8c : DMA_HandleTypeDef hdma_usart3_rx; DMA_HandleTypeDef hdma_usart3_tx; /* UART5 init function */ void MX_UART5_Init(void) { 800dc8c: b580 push {r7, lr} 800dc8e: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 800dc90: 4b11 ldr r3, [pc, #68] @ (800dcd8 ) 800dc92: 4a12 ldr r2, [pc, #72] @ (800dcdc ) 800dc94: 601a str r2, [r3, #0] huart5.Init.BaudRate = 9600; 800dc96: 4b10 ldr r3, [pc, #64] @ (800dcd8 ) 800dc98: f44f 5216 mov.w r2, #9600 @ 0x2580 800dc9c: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 800dc9e: 4b0e ldr r3, [pc, #56] @ (800dcd8 ) 800dca0: 2200 movs r2, #0 800dca2: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 800dca4: 4b0c ldr r3, [pc, #48] @ (800dcd8 ) 800dca6: 2200 movs r2, #0 800dca8: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 800dcaa: 4b0b ldr r3, [pc, #44] @ (800dcd8 ) 800dcac: 2200 movs r2, #0 800dcae: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 800dcb0: 4b09 ldr r3, [pc, #36] @ (800dcd8 ) 800dcb2: 220c movs r2, #12 800dcb4: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800dcb6: 4b08 ldr r3, [pc, #32] @ (800dcd8 ) 800dcb8: 2200 movs r2, #0 800dcba: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 800dcbc: 4b06 ldr r3, [pc, #24] @ (800dcd8 ) 800dcbe: 2200 movs r2, #0 800dcc0: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 800dcc2: 4805 ldr r0, [pc, #20] @ (800dcd8 ) 800dcc4: f005 f8b2 bl 8012e2c 800dcc8: 4603 mov r3, r0 800dcca: 2b00 cmp r3, #0 800dccc: d001 beq.n 800dcd2 { Error_Handler(); 800dcce: f7fc ffa7 bl 800ac20 } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 800dcd2: bf00 nop 800dcd4: bd80 pop {r7, pc} 800dcd6: bf00 nop 800dcd8: 20001258 .word 0x20001258 800dcdc: 40005000 .word 0x40005000 0800dce0 : /* USART1 init function */ void MX_USART1_UART_Init(void) { 800dce0: b580 push {r7, lr} 800dce2: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 800dce4: 4b11 ldr r3, [pc, #68] @ (800dd2c ) 800dce6: 4a12 ldr r2, [pc, #72] @ (800dd30 ) 800dce8: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800dcea: 4b10 ldr r3, [pc, #64] @ (800dd2c ) 800dcec: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800dcf0: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800dcf2: 4b0e ldr r3, [pc, #56] @ (800dd2c ) 800dcf4: 2200 movs r2, #0 800dcf6: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 800dcf8: 4b0c ldr r3, [pc, #48] @ (800dd2c ) 800dcfa: 2200 movs r2, #0 800dcfc: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800dcfe: 4b0b ldr r3, [pc, #44] @ (800dd2c ) 800dd00: 2200 movs r2, #0 800dd02: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 800dd04: 4b09 ldr r3, [pc, #36] @ (800dd2c ) 800dd06: 220c movs r2, #12 800dd08: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800dd0a: 4b08 ldr r3, [pc, #32] @ (800dd2c ) 800dd0c: 2200 movs r2, #0 800dd0e: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800dd10: 4b06 ldr r3, [pc, #24] @ (800dd2c ) 800dd12: 2200 movs r2, #0 800dd14: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 800dd16: 4805 ldr r0, [pc, #20] @ (800dd2c ) 800dd18: f005 f888 bl 8012e2c 800dd1c: 4603 mov r3, r0 800dd1e: 2b00 cmp r3, #0 800dd20: d001 beq.n 800dd26 { Error_Handler(); 800dd22: f7fc ff7d bl 800ac20 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 800dd26: bf00 nop 800dd28: bd80 pop {r7, pc} 800dd2a: bf00 nop 800dd2c: 200012a0 .word 0x200012a0 800dd30: 40013800 .word 0x40013800 0800dd34 : /* USART2 init function */ void MX_USART2_UART_Init(void) { 800dd34: b580 push {r7, lr} 800dd36: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 800dd38: 4b11 ldr r3, [pc, #68] @ (800dd80 ) 800dd3a: 4a12 ldr r2, [pc, #72] @ (800dd84 ) 800dd3c: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 800dd3e: 4b10 ldr r3, [pc, #64] @ (800dd80 ) 800dd40: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800dd44: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 800dd46: 4b0e ldr r3, [pc, #56] @ (800dd80 ) 800dd48: 2200 movs r2, #0 800dd4a: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 800dd4c: 4b0c ldr r3, [pc, #48] @ (800dd80 ) 800dd4e: 2200 movs r2, #0 800dd50: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800dd52: 4b0b ldr r3, [pc, #44] @ (800dd80 ) 800dd54: 2200 movs r2, #0 800dd56: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 800dd58: 4b09 ldr r3, [pc, #36] @ (800dd80 ) 800dd5a: 220c movs r2, #12 800dd5c: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800dd5e: 4b08 ldr r3, [pc, #32] @ (800dd80 ) 800dd60: 2200 movs r2, #0 800dd62: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 800dd64: 4b06 ldr r3, [pc, #24] @ (800dd80 ) 800dd66: 2200 movs r2, #0 800dd68: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 800dd6a: 4805 ldr r0, [pc, #20] @ (800dd80 ) 800dd6c: f005 f85e bl 8012e2c 800dd70: 4603 mov r3, r0 800dd72: 2b00 cmp r3, #0 800dd74: d001 beq.n 800dd7a { Error_Handler(); 800dd76: f7fc ff53 bl 800ac20 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 800dd7a: bf00 nop 800dd7c: bd80 pop {r7, pc} 800dd7e: bf00 nop 800dd80: 200012e8 .word 0x200012e8 800dd84: 40004400 .word 0x40004400 0800dd88 : /* USART3 init function */ void MX_USART3_UART_Init(void) { 800dd88: b580 push {r7, lr} 800dd8a: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 800dd8c: 4b11 ldr r3, [pc, #68] @ (800ddd4 ) 800dd8e: 4a12 ldr r2, [pc, #72] @ (800ddd8 ) 800dd90: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 800dd92: 4b10 ldr r3, [pc, #64] @ (800ddd4 ) 800dd94: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800dd98: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 800dd9a: 4b0e ldr r3, [pc, #56] @ (800ddd4 ) 800dd9c: 2200 movs r2, #0 800dd9e: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 800dda0: 4b0c ldr r3, [pc, #48] @ (800ddd4 ) 800dda2: 2200 movs r2, #0 800dda4: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 800dda6: 4b0b ldr r3, [pc, #44] @ (800ddd4 ) 800dda8: 2200 movs r2, #0 800ddaa: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 800ddac: 4b09 ldr r3, [pc, #36] @ (800ddd4 ) 800ddae: 220c movs r2, #12 800ddb0: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800ddb2: 4b08 ldr r3, [pc, #32] @ (800ddd4 ) 800ddb4: 2200 movs r2, #0 800ddb6: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 800ddb8: 4b06 ldr r3, [pc, #24] @ (800ddd4 ) 800ddba: 2200 movs r2, #0 800ddbc: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart3) != HAL_OK) 800ddbe: 4805 ldr r0, [pc, #20] @ (800ddd4 ) 800ddc0: f005 f834 bl 8012e2c 800ddc4: 4603 mov r3, r0 800ddc6: 2b00 cmp r3, #0 800ddc8: d001 beq.n 800ddce { Error_Handler(); 800ddca: f7fc ff29 bl 800ac20 } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 800ddce: bf00 nop 800ddd0: bd80 pop {r7, pc} 800ddd2: bf00 nop 800ddd4: 20001330 .word 0x20001330 800ddd8: 40004800 .word 0x40004800 0800dddc : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 800dddc: b580 push {r7, lr} 800ddde: b092 sub sp, #72 @ 0x48 800dde0: af00 add r7, sp, #0 800dde2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800dde4: f107 0330 add.w r3, r7, #48 @ 0x30 800dde8: 2200 movs r2, #0 800ddea: 601a str r2, [r3, #0] 800ddec: 605a str r2, [r3, #4] 800ddee: 609a str r2, [r3, #8] 800ddf0: 60da str r2, [r3, #12] if(uartHandle->Instance==UART5) 800ddf2: 687b ldr r3, [r7, #4] 800ddf4: 681b ldr r3, [r3, #0] 800ddf6: 4a92 ldr r2, [pc, #584] @ (800e040 ) 800ddf8: 4293 cmp r3, r2 800ddfa: d145 bne.n 800de88 { /* USER CODE BEGIN UART5_MspInit 0 */ /* USER CODE END UART5_MspInit 0 */ /* UART5 clock enable */ __HAL_RCC_UART5_CLK_ENABLE(); 800ddfc: 4b91 ldr r3, [pc, #580] @ (800e044 ) 800ddfe: 69db ldr r3, [r3, #28] 800de00: 4a90 ldr r2, [pc, #576] @ (800e044 ) 800de02: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800de06: 61d3 str r3, [r2, #28] 800de08: 4b8e ldr r3, [pc, #568] @ (800e044 ) 800de0a: 69db ldr r3, [r3, #28] 800de0c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800de10: 62fb str r3, [r7, #44] @ 0x2c 800de12: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 800de14: 4b8b ldr r3, [pc, #556] @ (800e044 ) 800de16: 699b ldr r3, [r3, #24] 800de18: 4a8a ldr r2, [pc, #552] @ (800e044 ) 800de1a: f043 0310 orr.w r3, r3, #16 800de1e: 6193 str r3, [r2, #24] 800de20: 4b88 ldr r3, [pc, #544] @ (800e044 ) 800de22: 699b ldr r3, [r3, #24] 800de24: f003 0310 and.w r3, r3, #16 800de28: 62bb str r3, [r7, #40] @ 0x28 800de2a: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOD_CLK_ENABLE(); 800de2c: 4b85 ldr r3, [pc, #532] @ (800e044 ) 800de2e: 699b ldr r3, [r3, #24] 800de30: 4a84 ldr r2, [pc, #528] @ (800e044 ) 800de32: f043 0320 orr.w r3, r3, #32 800de36: 6193 str r3, [r2, #24] 800de38: 4b82 ldr r3, [pc, #520] @ (800e044 ) 800de3a: 699b ldr r3, [r3, #24] 800de3c: f003 0320 and.w r3, r3, #32 800de40: 627b str r3, [r7, #36] @ 0x24 800de42: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART5 GPIO Configuration PC12 ------> UART5_TX PD2 ------> UART5_RX */ GPIO_InitStruct.Pin = GPIO_PIN_12; 800de44: f44f 5380 mov.w r3, #4096 @ 0x1000 800de48: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800de4a: 2302 movs r3, #2 800de4c: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800de4e: 2303 movs r3, #3 800de50: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800de52: f107 0330 add.w r3, r7, #48 @ 0x30 800de56: 4619 mov r1, r3 800de58: 487b ldr r0, [pc, #492] @ (800e048 ) 800de5a: f002 fc37 bl 80106cc GPIO_InitStruct.Pin = GPIO_PIN_2; 800de5e: 2304 movs r3, #4 800de60: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800de62: 2300 movs r3, #0 800de64: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800de66: 2300 movs r3, #0 800de68: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800de6a: f107 0330 add.w r3, r7, #48 @ 0x30 800de6e: 4619 mov r1, r3 800de70: 4876 ldr r0, [pc, #472] @ (800e04c ) 800de72: f002 fc2b bl 80106cc /* UART5 interrupt Init */ HAL_NVIC_SetPriority(UART5_IRQn, 5, 0); 800de76: 2200 movs r2, #0 800de78: 2105 movs r1, #5 800de7a: 2035 movs r0, #53 @ 0x35 800de7c: f001 ff45 bl 800fd0a HAL_NVIC_EnableIRQ(UART5_IRQn); 800de80: 2035 movs r0, #53 @ 0x35 800de82: f001 ff5e bl 800fd42 HAL_NVIC_EnableIRQ(USART3_IRQn); /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 800de86: e193 b.n 800e1b0 else if(uartHandle->Instance==USART1) 800de88: 687b ldr r3, [r7, #4] 800de8a: 681b ldr r3, [r3, #0] 800de8c: 4a70 ldr r2, [pc, #448] @ (800e050 ) 800de8e: 4293 cmp r3, r2 800de90: d13a bne.n 800df08 __HAL_RCC_USART1_CLK_ENABLE(); 800de92: 4b6c ldr r3, [pc, #432] @ (800e044 ) 800de94: 699b ldr r3, [r3, #24] 800de96: 4a6b ldr r2, [pc, #428] @ (800e044 ) 800de98: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800de9c: 6193 str r3, [r2, #24] 800de9e: 4b69 ldr r3, [pc, #420] @ (800e044 ) 800dea0: 699b ldr r3, [r3, #24] 800dea2: f403 4380 and.w r3, r3, #16384 @ 0x4000 800dea6: 623b str r3, [r7, #32] 800dea8: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 800deaa: 4b66 ldr r3, [pc, #408] @ (800e044 ) 800deac: 699b ldr r3, [r3, #24] 800deae: 4a65 ldr r2, [pc, #404] @ (800e044 ) 800deb0: f043 0304 orr.w r3, r3, #4 800deb4: 6193 str r3, [r2, #24] 800deb6: 4b63 ldr r3, [pc, #396] @ (800e044 ) 800deb8: 699b ldr r3, [r3, #24] 800deba: f003 0304 and.w r3, r3, #4 800debe: 61fb str r3, [r7, #28] 800dec0: 69fb ldr r3, [r7, #28] GPIO_InitStruct.Pin = GPIO_PIN_9; 800dec2: f44f 7300 mov.w r3, #512 @ 0x200 800dec6: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800dec8: 2302 movs r3, #2 800deca: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800decc: 2303 movs r3, #3 800dece: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800ded0: f107 0330 add.w r3, r7, #48 @ 0x30 800ded4: 4619 mov r1, r3 800ded6: 485f ldr r0, [pc, #380] @ (800e054 ) 800ded8: f002 fbf8 bl 80106cc GPIO_InitStruct.Pin = GPIO_PIN_10; 800dedc: f44f 6380 mov.w r3, #1024 @ 0x400 800dee0: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800dee2: 2300 movs r3, #0 800dee4: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800dee6: 2300 movs r3, #0 800dee8: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800deea: f107 0330 add.w r3, r7, #48 @ 0x30 800deee: 4619 mov r1, r3 800def0: 4858 ldr r0, [pc, #352] @ (800e054 ) 800def2: f002 fbeb bl 80106cc HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 800def6: 2200 movs r2, #0 800def8: 2105 movs r1, #5 800defa: 2025 movs r0, #37 @ 0x25 800defc: f001 ff05 bl 800fd0a HAL_NVIC_EnableIRQ(USART1_IRQn); 800df00: 2025 movs r0, #37 @ 0x25 800df02: f001 ff1e bl 800fd42 } 800df06: e153 b.n 800e1b0 else if(uartHandle->Instance==USART2) 800df08: 687b ldr r3, [r7, #4] 800df0a: 681b ldr r3, [r3, #0] 800df0c: 4a52 ldr r2, [pc, #328] @ (800e058 ) 800df0e: 4293 cmp r3, r2 800df10: f040 80ae bne.w 800e070 __HAL_RCC_USART2_CLK_ENABLE(); 800df14: 4b4b ldr r3, [pc, #300] @ (800e044 ) 800df16: 69db ldr r3, [r3, #28] 800df18: 4a4a ldr r2, [pc, #296] @ (800e044 ) 800df1a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800df1e: 61d3 str r3, [r2, #28] 800df20: 4b48 ldr r3, [pc, #288] @ (800e044 ) 800df22: 69db ldr r3, [r3, #28] 800df24: f403 3300 and.w r3, r3, #131072 @ 0x20000 800df28: 61bb str r3, [r7, #24] 800df2a: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOD_CLK_ENABLE(); 800df2c: 4b45 ldr r3, [pc, #276] @ (800e044 ) 800df2e: 699b ldr r3, [r3, #24] 800df30: 4a44 ldr r2, [pc, #272] @ (800e044 ) 800df32: f043 0320 orr.w r3, r3, #32 800df36: 6193 str r3, [r2, #24] 800df38: 4b42 ldr r3, [pc, #264] @ (800e044 ) 800df3a: 699b ldr r3, [r3, #24] 800df3c: f003 0320 and.w r3, r3, #32 800df40: 617b str r3, [r7, #20] 800df42: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_5; 800df44: 2320 movs r3, #32 800df46: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800df48: 2302 movs r3, #2 800df4a: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800df4c: 2303 movs r3, #3 800df4e: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800df50: f107 0330 add.w r3, r7, #48 @ 0x30 800df54: 4619 mov r1, r3 800df56: 483d ldr r0, [pc, #244] @ (800e04c ) 800df58: f002 fbb8 bl 80106cc GPIO_InitStruct.Pin = GPIO_PIN_6; 800df5c: 2340 movs r3, #64 @ 0x40 800df5e: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800df60: 2300 movs r3, #0 800df62: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800df64: 2300 movs r3, #0 800df66: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800df68: f107 0330 add.w r3, r7, #48 @ 0x30 800df6c: 4619 mov r1, r3 800df6e: 4837 ldr r0, [pc, #220] @ (800e04c ) 800df70: f002 fbac bl 80106cc __HAL_AFIO_REMAP_USART2_ENABLE(); 800df74: 4b39 ldr r3, [pc, #228] @ (800e05c ) 800df76: 685b ldr r3, [r3, #4] 800df78: 643b str r3, [r7, #64] @ 0x40 800df7a: 6c3b ldr r3, [r7, #64] @ 0x40 800df7c: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800df80: 643b str r3, [r7, #64] @ 0x40 800df82: 6c3b ldr r3, [r7, #64] @ 0x40 800df84: f043 0308 orr.w r3, r3, #8 800df88: 643b str r3, [r7, #64] @ 0x40 800df8a: 4a34 ldr r2, [pc, #208] @ (800e05c ) 800df8c: 6c3b ldr r3, [r7, #64] @ 0x40 800df8e: 6053 str r3, [r2, #4] hdma_usart2_rx.Instance = DMA1_Channel6; 800df90: 4b33 ldr r3, [pc, #204] @ (800e060 ) 800df92: 4a34 ldr r2, [pc, #208] @ (800e064 ) 800df94: 601a str r2, [r3, #0] hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 800df96: 4b32 ldr r3, [pc, #200] @ (800e060 ) 800df98: 2200 movs r2, #0 800df9a: 605a str r2, [r3, #4] hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 800df9c: 4b30 ldr r3, [pc, #192] @ (800e060 ) 800df9e: 2200 movs r2, #0 800dfa0: 609a str r2, [r3, #8] hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; 800dfa2: 4b2f ldr r3, [pc, #188] @ (800e060 ) 800dfa4: 2280 movs r2, #128 @ 0x80 800dfa6: 60da str r2, [r3, #12] hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800dfa8: 4b2d ldr r3, [pc, #180] @ (800e060 ) 800dfaa: 2200 movs r2, #0 800dfac: 611a str r2, [r3, #16] hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800dfae: 4b2c ldr r3, [pc, #176] @ (800e060 ) 800dfb0: 2200 movs r2, #0 800dfb2: 615a str r2, [r3, #20] hdma_usart2_rx.Init.Mode = DMA_NORMAL; 800dfb4: 4b2a ldr r3, [pc, #168] @ (800e060 ) 800dfb6: 2200 movs r2, #0 800dfb8: 619a str r2, [r3, #24] hdma_usart2_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH; 800dfba: 4b29 ldr r3, [pc, #164] @ (800e060 ) 800dfbc: f44f 5240 mov.w r2, #12288 @ 0x3000 800dfc0: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) 800dfc2: 4827 ldr r0, [pc, #156] @ (800e060 ) 800dfc4: f001 fef4 bl 800fdb0 800dfc8: 4603 mov r3, r0 800dfca: 2b00 cmp r3, #0 800dfcc: d001 beq.n 800dfd2 Error_Handler(); 800dfce: f7fc fe27 bl 800ac20 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); 800dfd2: 687b ldr r3, [r7, #4] 800dfd4: 4a22 ldr r2, [pc, #136] @ (800e060 ) 800dfd6: 63da str r2, [r3, #60] @ 0x3c 800dfd8: 4a21 ldr r2, [pc, #132] @ (800e060 ) 800dfda: 687b ldr r3, [r7, #4] 800dfdc: 6253 str r3, [r2, #36] @ 0x24 hdma_usart2_tx.Instance = DMA1_Channel7; 800dfde: 4b22 ldr r3, [pc, #136] @ (800e068 ) 800dfe0: 4a22 ldr r2, [pc, #136] @ (800e06c ) 800dfe2: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 800dfe4: 4b20 ldr r3, [pc, #128] @ (800e068 ) 800dfe6: 2210 movs r2, #16 800dfe8: 605a str r2, [r3, #4] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800dfea: 4b1f ldr r3, [pc, #124] @ (800e068 ) 800dfec: 2200 movs r2, #0 800dfee: 609a str r2, [r3, #8] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; 800dff0: 4b1d ldr r3, [pc, #116] @ (800e068 ) 800dff2: 2280 movs r2, #128 @ 0x80 800dff4: 60da str r2, [r3, #12] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800dff6: 4b1c ldr r3, [pc, #112] @ (800e068 ) 800dff8: 2200 movs r2, #0 800dffa: 611a str r2, [r3, #16] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800dffc: 4b1a ldr r3, [pc, #104] @ (800e068 ) 800dffe: 2200 movs r2, #0 800e000: 615a str r2, [r3, #20] hdma_usart2_tx.Init.Mode = DMA_NORMAL; 800e002: 4b19 ldr r3, [pc, #100] @ (800e068 ) 800e004: 2200 movs r2, #0 800e006: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_HIGH; 800e008: 4b17 ldr r3, [pc, #92] @ (800e068 ) 800e00a: f44f 5200 mov.w r2, #8192 @ 0x2000 800e00e: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 800e010: 4815 ldr r0, [pc, #84] @ (800e068 ) 800e012: f001 fecd bl 800fdb0 800e016: 4603 mov r3, r0 800e018: 2b00 cmp r3, #0 800e01a: d001 beq.n 800e020 Error_Handler(); 800e01c: f7fc fe00 bl 800ac20 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); 800e020: 687b ldr r3, [r7, #4] 800e022: 4a11 ldr r2, [pc, #68] @ (800e068 ) 800e024: 639a str r2, [r3, #56] @ 0x38 800e026: 4a10 ldr r2, [pc, #64] @ (800e068 ) 800e028: 687b ldr r3, [r7, #4] 800e02a: 6253 str r3, [r2, #36] @ 0x24 HAL_NVIC_SetPriority(USART2_IRQn, 2, 0); 800e02c: 2200 movs r2, #0 800e02e: 2102 movs r1, #2 800e030: 2026 movs r0, #38 @ 0x26 800e032: f001 fe6a bl 800fd0a HAL_NVIC_EnableIRQ(USART2_IRQn); 800e036: 2026 movs r0, #38 @ 0x26 800e038: f001 fe83 bl 800fd42 } 800e03c: e0b8 b.n 800e1b0 800e03e: bf00 nop 800e040: 40005000 .word 0x40005000 800e044: 40021000 .word 0x40021000 800e048: 40011000 .word 0x40011000 800e04c: 40011400 .word 0x40011400 800e050: 40013800 .word 0x40013800 800e054: 40010800 .word 0x40010800 800e058: 40004400 .word 0x40004400 800e05c: 40010000 .word 0x40010000 800e060: 20001378 .word 0x20001378 800e064: 4002006c .word 0x4002006c 800e068: 200013bc .word 0x200013bc 800e06c: 40020080 .word 0x40020080 else if(uartHandle->Instance==USART3) 800e070: 687b ldr r3, [r7, #4] 800e072: 681b ldr r3, [r3, #0] 800e074: 4a50 ldr r2, [pc, #320] @ (800e1b8 ) 800e076: 4293 cmp r3, r2 800e078: f040 809a bne.w 800e1b0 __HAL_RCC_USART3_CLK_ENABLE(); 800e07c: 4b4f ldr r3, [pc, #316] @ (800e1bc ) 800e07e: 69db ldr r3, [r3, #28] 800e080: 4a4e ldr r2, [pc, #312] @ (800e1bc ) 800e082: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800e086: 61d3 str r3, [r2, #28] 800e088: 4b4c ldr r3, [pc, #304] @ (800e1bc ) 800e08a: 69db ldr r3, [r3, #28] 800e08c: f403 2380 and.w r3, r3, #262144 @ 0x40000 800e090: 613b str r3, [r7, #16] 800e092: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 800e094: 4b49 ldr r3, [pc, #292] @ (800e1bc ) 800e096: 699b ldr r3, [r3, #24] 800e098: 4a48 ldr r2, [pc, #288] @ (800e1bc ) 800e09a: f043 0310 orr.w r3, r3, #16 800e09e: 6193 str r3, [r2, #24] 800e0a0: 4b46 ldr r3, [pc, #280] @ (800e1bc ) 800e0a2: 699b ldr r3, [r3, #24] 800e0a4: f003 0310 and.w r3, r3, #16 800e0a8: 60fb str r3, [r7, #12] 800e0aa: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_10; 800e0ac: f44f 6380 mov.w r3, #1024 @ 0x400 800e0b0: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800e0b2: 2302 movs r3, #2 800e0b4: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800e0b6: 2303 movs r3, #3 800e0b8: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800e0ba: f107 0330 add.w r3, r7, #48 @ 0x30 800e0be: 4619 mov r1, r3 800e0c0: 483f ldr r0, [pc, #252] @ (800e1c0 ) 800e0c2: f002 fb03 bl 80106cc GPIO_InitStruct.Pin = GPIO_PIN_11; 800e0c6: f44f 6300 mov.w r3, #2048 @ 0x800 800e0ca: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800e0cc: 2300 movs r3, #0 800e0ce: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800e0d0: 2300 movs r3, #0 800e0d2: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800e0d4: f107 0330 add.w r3, r7, #48 @ 0x30 800e0d8: 4619 mov r1, r3 800e0da: 4839 ldr r0, [pc, #228] @ (800e1c0 ) 800e0dc: f002 faf6 bl 80106cc __HAL_AFIO_REMAP_USART3_PARTIAL(); 800e0e0: 4b38 ldr r3, [pc, #224] @ (800e1c4 ) 800e0e2: 685b ldr r3, [r3, #4] 800e0e4: 647b str r3, [r7, #68] @ 0x44 800e0e6: 6c7b ldr r3, [r7, #68] @ 0x44 800e0e8: f023 0330 bic.w r3, r3, #48 @ 0x30 800e0ec: 647b str r3, [r7, #68] @ 0x44 800e0ee: 6c7b ldr r3, [r7, #68] @ 0x44 800e0f0: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800e0f4: 647b str r3, [r7, #68] @ 0x44 800e0f6: 6c7b ldr r3, [r7, #68] @ 0x44 800e0f8: f043 0310 orr.w r3, r3, #16 800e0fc: 647b str r3, [r7, #68] @ 0x44 800e0fe: 4a31 ldr r2, [pc, #196] @ (800e1c4 ) 800e100: 6c7b ldr r3, [r7, #68] @ 0x44 800e102: 6053 str r3, [r2, #4] hdma_usart3_rx.Instance = DMA1_Channel3; 800e104: 4b30 ldr r3, [pc, #192] @ (800e1c8 ) 800e106: 4a31 ldr r2, [pc, #196] @ (800e1cc ) 800e108: 601a str r2, [r3, #0] hdma_usart3_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 800e10a: 4b2f ldr r3, [pc, #188] @ (800e1c8 ) 800e10c: 2200 movs r2, #0 800e10e: 605a str r2, [r3, #4] hdma_usart3_rx.Init.PeriphInc = DMA_PINC_DISABLE; 800e110: 4b2d ldr r3, [pc, #180] @ (800e1c8 ) 800e112: 2200 movs r2, #0 800e114: 609a str r2, [r3, #8] hdma_usart3_rx.Init.MemInc = DMA_MINC_ENABLE; 800e116: 4b2c ldr r3, [pc, #176] @ (800e1c8 ) 800e118: 2280 movs r2, #128 @ 0x80 800e11a: 60da str r2, [r3, #12] hdma_usart3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800e11c: 4b2a ldr r3, [pc, #168] @ (800e1c8 ) 800e11e: 2200 movs r2, #0 800e120: 611a str r2, [r3, #16] hdma_usart3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800e122: 4b29 ldr r3, [pc, #164] @ (800e1c8 ) 800e124: 2200 movs r2, #0 800e126: 615a str r2, [r3, #20] hdma_usart3_rx.Init.Mode = DMA_NORMAL; 800e128: 4b27 ldr r3, [pc, #156] @ (800e1c8 ) 800e12a: 2200 movs r2, #0 800e12c: 619a str r2, [r3, #24] hdma_usart3_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH; 800e12e: 4b26 ldr r3, [pc, #152] @ (800e1c8 ) 800e130: f44f 5240 mov.w r2, #12288 @ 0x3000 800e134: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart3_rx) != HAL_OK) 800e136: 4824 ldr r0, [pc, #144] @ (800e1c8 ) 800e138: f001 fe3a bl 800fdb0 800e13c: 4603 mov r3, r0 800e13e: 2b00 cmp r3, #0 800e140: d001 beq.n 800e146 Error_Handler(); 800e142: f7fc fd6d bl 800ac20 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart3_rx); 800e146: 687b ldr r3, [r7, #4] 800e148: 4a1f ldr r2, [pc, #124] @ (800e1c8 ) 800e14a: 63da str r2, [r3, #60] @ 0x3c 800e14c: 4a1e ldr r2, [pc, #120] @ (800e1c8 ) 800e14e: 687b ldr r3, [r7, #4] 800e150: 6253 str r3, [r2, #36] @ 0x24 hdma_usart3_tx.Instance = DMA1_Channel2; 800e152: 4b1f ldr r3, [pc, #124] @ (800e1d0 ) 800e154: 4a1f ldr r2, [pc, #124] @ (800e1d4 ) 800e156: 601a str r2, [r3, #0] hdma_usart3_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 800e158: 4b1d ldr r3, [pc, #116] @ (800e1d0 ) 800e15a: 2210 movs r2, #16 800e15c: 605a str r2, [r3, #4] hdma_usart3_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800e15e: 4b1c ldr r3, [pc, #112] @ (800e1d0 ) 800e160: 2200 movs r2, #0 800e162: 609a str r2, [r3, #8] hdma_usart3_tx.Init.MemInc = DMA_MINC_ENABLE; 800e164: 4b1a ldr r3, [pc, #104] @ (800e1d0 ) 800e166: 2280 movs r2, #128 @ 0x80 800e168: 60da str r2, [r3, #12] hdma_usart3_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800e16a: 4b19 ldr r3, [pc, #100] @ (800e1d0 ) 800e16c: 2200 movs r2, #0 800e16e: 611a str r2, [r3, #16] hdma_usart3_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800e170: 4b17 ldr r3, [pc, #92] @ (800e1d0 ) 800e172: 2200 movs r2, #0 800e174: 615a str r2, [r3, #20] hdma_usart3_tx.Init.Mode = DMA_NORMAL; 800e176: 4b16 ldr r3, [pc, #88] @ (800e1d0 ) 800e178: 2200 movs r2, #0 800e17a: 619a str r2, [r3, #24] hdma_usart3_tx.Init.Priority = DMA_PRIORITY_HIGH; 800e17c: 4b14 ldr r3, [pc, #80] @ (800e1d0 ) 800e17e: f44f 5200 mov.w r2, #8192 @ 0x2000 800e182: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart3_tx) != HAL_OK) 800e184: 4812 ldr r0, [pc, #72] @ (800e1d0 ) 800e186: f001 fe13 bl 800fdb0 800e18a: 4603 mov r3, r0 800e18c: 2b00 cmp r3, #0 800e18e: d001 beq.n 800e194 Error_Handler(); 800e190: f7fc fd46 bl 800ac20 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart3_tx); 800e194: 687b ldr r3, [r7, #4] 800e196: 4a0e ldr r2, [pc, #56] @ (800e1d0 ) 800e198: 639a str r2, [r3, #56] @ 0x38 800e19a: 4a0d ldr r2, [pc, #52] @ (800e1d0 ) 800e19c: 687b ldr r3, [r7, #4] 800e19e: 6253 str r3, [r2, #36] @ 0x24 HAL_NVIC_SetPriority(USART3_IRQn, 2, 0); 800e1a0: 2200 movs r2, #0 800e1a2: 2102 movs r1, #2 800e1a4: 2027 movs r0, #39 @ 0x27 800e1a6: f001 fdb0 bl 800fd0a HAL_NVIC_EnableIRQ(USART3_IRQn); 800e1aa: 2027 movs r0, #39 @ 0x27 800e1ac: f001 fdc9 bl 800fd42 } 800e1b0: bf00 nop 800e1b2: 3748 adds r7, #72 @ 0x48 800e1b4: 46bd mov sp, r7 800e1b6: bd80 pop {r7, pc} 800e1b8: 40004800 .word 0x40004800 800e1bc: 40021000 .word 0x40021000 800e1c0: 40011000 .word 0x40011000 800e1c4: 40010000 .word 0x40010000 800e1c8: 20001400 .word 0x20001400 800e1cc: 40020030 .word 0x40020030 800e1d0: 20001444 .word 0x20001444 800e1d4: 4002001c .word 0x4002001c 0800e1d8 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 800e1d8: f7ff fb98 bl 800d90c /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 800e1dc: 480b ldr r0, [pc, #44] @ (800e20c ) ldr r1, =_edata 800e1de: 490c ldr r1, [pc, #48] @ (800e210 ) ldr r2, =_sidata 800e1e0: 4a0c ldr r2, [pc, #48] @ (800e214 ) movs r3, #0 800e1e2: 2300 movs r3, #0 b LoopCopyDataInit 800e1e4: e002 b.n 800e1ec 0800e1e6 : CopyDataInit: ldr r4, [r2, r3] 800e1e6: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800e1e8: 50c4 str r4, [r0, r3] adds r3, r3, #4 800e1ea: 3304 adds r3, #4 0800e1ec : LoopCopyDataInit: adds r4, r0, r3 800e1ec: 18c4 adds r4, r0, r3 cmp r4, r1 800e1ee: 428c cmp r4, r1 bcc CopyDataInit 800e1f0: d3f9 bcc.n 800e1e6 /* Zero fill the bss segment. */ ldr r2, =_sbss 800e1f2: 4a09 ldr r2, [pc, #36] @ (800e218 ) ldr r4, =_ebss 800e1f4: 4c09 ldr r4, [pc, #36] @ (800e21c ) movs r3, #0 800e1f6: 2300 movs r3, #0 b LoopFillZerobss 800e1f8: e001 b.n 800e1fe 0800e1fa : FillZerobss: str r3, [r2] 800e1fa: 6013 str r3, [r2, #0] adds r2, r2, #4 800e1fc: 3204 adds r2, #4 0800e1fe : LoopFillZerobss: cmp r2, r4 800e1fe: 42a2 cmp r2, r4 bcc FillZerobss 800e200: d3fb bcc.n 800e1fa /* Call static constructors */ bl __libc_init_array 800e202: f006 fd2f bl 8014c64 <__libc_init_array> /* Call the application's entry point.*/ bl main 800e206: f7fc fc21 bl 800aa4c
bx lr 800e20a: 4770 bx lr ldr r0, =_sdata 800e20c: 20000000 .word 0x20000000 ldr r1, =_edata 800e210: 20000258 .word 0x20000258 ldr r2, =_sidata 800e214: 08017c74 .word 0x08017c74 ldr r2, =_sbss 800e218: 20000258 .word 0x20000258 ldr r4, =_ebss 800e21c: 200015d8 .word 0x200015d8 0800e220 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 800e220: e7fe b.n 800e220 ... 0800e224 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800e224: b580 push {r7, lr} 800e226: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 800e228: 4b08 ldr r3, [pc, #32] @ (800e24c ) 800e22a: 681b ldr r3, [r3, #0] 800e22c: 4a07 ldr r2, [pc, #28] @ (800e24c ) 800e22e: f043 0310 orr.w r3, r3, #16 800e232: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800e234: 2003 movs r0, #3 800e236: f001 fd5d bl 800fcf4 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800e23a: 200f movs r0, #15 800e23c: f000 f808 bl 800e250 /* Init the low level hardware */ HAL_MspInit(); 800e240: f7ff f98a bl 800d558 /* Return function status */ return HAL_OK; 800e244: 2300 movs r3, #0 } 800e246: 4618 mov r0, r3 800e248: bd80 pop {r7, pc} 800e24a: bf00 nop 800e24c: 40022000 .word 0x40022000 0800e250 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800e250: b580 push {r7, lr} 800e252: b082 sub sp, #8 800e254: af00 add r7, sp, #0 800e256: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 800e258: 4b12 ldr r3, [pc, #72] @ (800e2a4 ) 800e25a: 681a ldr r2, [r3, #0] 800e25c: 4b12 ldr r3, [pc, #72] @ (800e2a8 ) 800e25e: 781b ldrb r3, [r3, #0] 800e260: 4619 mov r1, r3 800e262: f44f 737a mov.w r3, #1000 @ 0x3e8 800e266: fbb3 f3f1 udiv r3, r3, r1 800e26a: fbb2 f3f3 udiv r3, r2, r3 800e26e: 4618 mov r0, r3 800e270: f001 fd75 bl 800fd5e 800e274: 4603 mov r3, r0 800e276: 2b00 cmp r3, #0 800e278: d001 beq.n 800e27e { return HAL_ERROR; 800e27a: 2301 movs r3, #1 800e27c: e00e b.n 800e29c } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800e27e: 687b ldr r3, [r7, #4] 800e280: 2b0f cmp r3, #15 800e282: d80a bhi.n 800e29a { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800e284: 2200 movs r2, #0 800e286: 6879 ldr r1, [r7, #4] 800e288: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800e28c: f001 fd3d bl 800fd0a uwTickPrio = TickPriority; 800e290: 4a06 ldr r2, [pc, #24] @ (800e2ac ) 800e292: 687b ldr r3, [r7, #4] 800e294: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800e296: 2300 movs r3, #0 800e298: e000 b.n 800e29c return HAL_ERROR; 800e29a: 2301 movs r3, #1 } 800e29c: 4618 mov r0, r3 800e29e: 3708 adds r7, #8 800e2a0: 46bd mov sp, r7 800e2a2: bd80 pop {r7, pc} 800e2a4: 20000084 .word 0x20000084 800e2a8: 2000008c .word 0x2000008c 800e2ac: 20000088 .word 0x20000088 0800e2b0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800e2b0: b480 push {r7} 800e2b2: af00 add r7, sp, #0 uwTick += uwTickFreq; 800e2b4: 4b05 ldr r3, [pc, #20] @ (800e2cc ) 800e2b6: 781b ldrb r3, [r3, #0] 800e2b8: 461a mov r2, r3 800e2ba: 4b05 ldr r3, [pc, #20] @ (800e2d0 ) 800e2bc: 681b ldr r3, [r3, #0] 800e2be: 4413 add r3, r2 800e2c0: 4a03 ldr r2, [pc, #12] @ (800e2d0 ) 800e2c2: 6013 str r3, [r2, #0] } 800e2c4: bf00 nop 800e2c6: 46bd mov sp, r7 800e2c8: bc80 pop {r7} 800e2ca: 4770 bx lr 800e2cc: 2000008c .word 0x2000008c 800e2d0: 20001488 .word 0x20001488 0800e2d4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 800e2d4: b480 push {r7} 800e2d6: af00 add r7, sp, #0 return uwTick; 800e2d8: 4b02 ldr r3, [pc, #8] @ (800e2e4 ) 800e2da: 681b ldr r3, [r3, #0] } 800e2dc: 4618 mov r0, r3 800e2de: 46bd mov sp, r7 800e2e0: bc80 pop {r7} 800e2e2: 4770 bx lr 800e2e4: 20001488 .word 0x20001488 0800e2e8 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 800e2e8: b580 push {r7, lr} 800e2ea: b084 sub sp, #16 800e2ec: af00 add r7, sp, #0 800e2ee: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800e2f0: f7ff fff0 bl 800e2d4 800e2f4: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800e2f6: 687b ldr r3, [r7, #4] 800e2f8: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800e2fa: 68fb ldr r3, [r7, #12] 800e2fc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800e300: d005 beq.n 800e30e { wait += (uint32_t)(uwTickFreq); 800e302: 4b0a ldr r3, [pc, #40] @ (800e32c ) 800e304: 781b ldrb r3, [r3, #0] 800e306: 461a mov r2, r3 800e308: 68fb ldr r3, [r7, #12] 800e30a: 4413 add r3, r2 800e30c: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 800e30e: bf00 nop 800e310: f7ff ffe0 bl 800e2d4 800e314: 4602 mov r2, r0 800e316: 68bb ldr r3, [r7, #8] 800e318: 1ad3 subs r3, r2, r3 800e31a: 68fa ldr r2, [r7, #12] 800e31c: 429a cmp r2, r3 800e31e: d8f7 bhi.n 800e310 { } } 800e320: bf00 nop 800e322: bf00 nop 800e324: 3710 adds r7, #16 800e326: 46bd mov sp, r7 800e328: bd80 pop {r7, pc} 800e32a: bf00 nop 800e32c: 2000008c .word 0x2000008c 0800e330 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 800e330: b580 push {r7, lr} 800e332: b086 sub sp, #24 800e334: af00 add r7, sp, #0 800e336: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e338: 2300 movs r3, #0 800e33a: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 800e33c: 2300 movs r3, #0 800e33e: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 800e340: 2300 movs r3, #0 800e342: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 800e344: 2300 movs r3, #0 800e346: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 800e348: 687b ldr r3, [r7, #4] 800e34a: 2b00 cmp r3, #0 800e34c: d101 bne.n 800e352 { return HAL_ERROR; 800e34e: 2301 movs r3, #1 800e350: e0be b.n 800e4d0 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 800e352: 687b ldr r3, [r7, #4] 800e354: 689b ldr r3, [r3, #8] 800e356: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 800e358: 687b ldr r3, [r7, #4] 800e35a: 6a9b ldr r3, [r3, #40] @ 0x28 800e35c: 2b00 cmp r3, #0 800e35e: d109 bne.n 800e374 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 800e360: 687b ldr r3, [r7, #4] 800e362: 2200 movs r2, #0 800e364: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 800e366: 687b ldr r3, [r7, #4] 800e368: 2200 movs r2, #0 800e36a: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800e36e: 6878 ldr r0, [r7, #4] 800e370: f7fb f998 bl 80096a4 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800e374: 6878 ldr r0, [r7, #4] 800e376: f000 fbbd bl 800eaf4 800e37a: 4603 mov r3, r0 800e37c: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 800e37e: 687b ldr r3, [r7, #4] 800e380: 6a9b ldr r3, [r3, #40] @ 0x28 800e382: f003 0310 and.w r3, r3, #16 800e386: 2b00 cmp r3, #0 800e388: f040 8099 bne.w 800e4be 800e38c: 7dfb ldrb r3, [r7, #23] 800e38e: 2b00 cmp r3, #0 800e390: f040 8095 bne.w 800e4be (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e394: 687b ldr r3, [r7, #4] 800e396: 6a9b ldr r3, [r3, #40] @ 0x28 800e398: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800e39c: f023 0302 bic.w r3, r3, #2 800e3a0: f043 0202 orr.w r2, r3, #2 800e3a4: 687b ldr r3, [r7, #4] 800e3a6: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 800e3a8: 687b ldr r3, [r7, #4] 800e3aa: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800e3ac: 687b ldr r3, [r7, #4] 800e3ae: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 800e3b0: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 800e3b2: 687b ldr r3, [r7, #4] 800e3b4: 7b1b ldrb r3, [r3, #12] 800e3b6: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800e3b8: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 800e3ba: 68ba ldr r2, [r7, #8] 800e3bc: 4313 orrs r3, r2 800e3be: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 800e3c0: 687b ldr r3, [r7, #4] 800e3c2: 689b ldr r3, [r3, #8] 800e3c4: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e3c8: d003 beq.n 800e3d2 800e3ca: 687b ldr r3, [r7, #4] 800e3cc: 689b ldr r3, [r3, #8] 800e3ce: 2b01 cmp r3, #1 800e3d0: d102 bne.n 800e3d8 800e3d2: f44f 7380 mov.w r3, #256 @ 0x100 800e3d6: e000 b.n 800e3da 800e3d8: 2300 movs r3, #0 800e3da: 693a ldr r2, [r7, #16] 800e3dc: 4313 orrs r3, r2 800e3de: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 800e3e0: 687b ldr r3, [r7, #4] 800e3e2: 7d1b ldrb r3, [r3, #20] 800e3e4: 2b01 cmp r3, #1 800e3e6: d119 bne.n 800e41c { if (hadc->Init.ContinuousConvMode == DISABLE) 800e3e8: 687b ldr r3, [r7, #4] 800e3ea: 7b1b ldrb r3, [r3, #12] 800e3ec: 2b00 cmp r3, #0 800e3ee: d109 bne.n 800e404 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 800e3f0: 687b ldr r3, [r7, #4] 800e3f2: 699b ldr r3, [r3, #24] 800e3f4: 3b01 subs r3, #1 800e3f6: 035a lsls r2, r3, #13 800e3f8: 693b ldr r3, [r7, #16] 800e3fa: 4313 orrs r3, r2 800e3fc: f443 6300 orr.w r3, r3, #2048 @ 0x800 800e400: 613b str r3, [r7, #16] 800e402: e00b b.n 800e41c { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800e404: 687b ldr r3, [r7, #4] 800e406: 6a9b ldr r3, [r3, #40] @ 0x28 800e408: f043 0220 orr.w r2, r3, #32 800e40c: 687b ldr r3, [r7, #4] 800e40e: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e410: 687b ldr r3, [r7, #4] 800e412: 6adb ldr r3, [r3, #44] @ 0x2c 800e414: f043 0201 orr.w r2, r3, #1 800e418: 687b ldr r3, [r7, #4] 800e41a: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 800e41c: 687b ldr r3, [r7, #4] 800e41e: 681b ldr r3, [r3, #0] 800e420: 685b ldr r3, [r3, #4] 800e422: f423 4169 bic.w r1, r3, #59648 @ 0xe900 800e426: 687b ldr r3, [r7, #4] 800e428: 681b ldr r3, [r3, #0] 800e42a: 693a ldr r2, [r7, #16] 800e42c: 430a orrs r2, r1 800e42e: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 800e430: 687b ldr r3, [r7, #4] 800e432: 681b ldr r3, [r3, #0] 800e434: 689a ldr r2, [r3, #8] 800e436: 4b28 ldr r3, [pc, #160] @ (800e4d8 ) 800e438: 4013 ands r3, r2 800e43a: 687a ldr r2, [r7, #4] 800e43c: 6812 ldr r2, [r2, #0] 800e43e: 68b9 ldr r1, [r7, #8] 800e440: 430b orrs r3, r1 800e442: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 800e444: 687b ldr r3, [r7, #4] 800e446: 689b ldr r3, [r3, #8] 800e448: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e44c: d003 beq.n 800e456 800e44e: 687b ldr r3, [r7, #4] 800e450: 689b ldr r3, [r3, #8] 800e452: 2b01 cmp r3, #1 800e454: d104 bne.n 800e460 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 800e456: 687b ldr r3, [r7, #4] 800e458: 691b ldr r3, [r3, #16] 800e45a: 3b01 subs r3, #1 800e45c: 051b lsls r3, r3, #20 800e45e: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 800e460: 687b ldr r3, [r7, #4] 800e462: 681b ldr r3, [r3, #0] 800e464: 6adb ldr r3, [r3, #44] @ 0x2c 800e466: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 800e46a: 687b ldr r3, [r7, #4] 800e46c: 681b ldr r3, [r3, #0] 800e46e: 68fa ldr r2, [r7, #12] 800e470: 430a orrs r2, r1 800e472: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800e474: 687b ldr r3, [r7, #4] 800e476: 681b ldr r3, [r3, #0] 800e478: 689a ldr r2, [r3, #8] 800e47a: 4b18 ldr r3, [pc, #96] @ (800e4dc ) 800e47c: 4013 ands r3, r2 800e47e: 68ba ldr r2, [r7, #8] 800e480: 429a cmp r2, r3 800e482: d10b bne.n 800e49c ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 800e484: 687b ldr r3, [r7, #4] 800e486: 2200 movs r2, #0 800e488: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e48a: 687b ldr r3, [r7, #4] 800e48c: 6a9b ldr r3, [r3, #40] @ 0x28 800e48e: f023 0303 bic.w r3, r3, #3 800e492: f043 0201 orr.w r2, r3, #1 800e496: 687b ldr r3, [r7, #4] 800e498: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800e49a: e018 b.n 800e4ce HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800e49c: 687b ldr r3, [r7, #4] 800e49e: 6a9b ldr r3, [r3, #40] @ 0x28 800e4a0: f023 0312 bic.w r3, r3, #18 800e4a4: f043 0210 orr.w r2, r3, #16 800e4a8: 687b ldr r3, [r7, #4] 800e4aa: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e4ac: 687b ldr r3, [r7, #4] 800e4ae: 6adb ldr r3, [r3, #44] @ 0x2c 800e4b0: f043 0201 orr.w r2, r3, #1 800e4b4: 687b ldr r3, [r7, #4] 800e4b6: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 800e4b8: 2301 movs r3, #1 800e4ba: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800e4bc: e007 b.n 800e4ce } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800e4be: 687b ldr r3, [r7, #4] 800e4c0: 6a9b ldr r3, [r3, #40] @ 0x28 800e4c2: f043 0210 orr.w r2, r3, #16 800e4c6: 687b ldr r3, [r7, #4] 800e4c8: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800e4ca: 2301 movs r3, #1 800e4cc: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800e4ce: 7dfb ldrb r3, [r7, #23] } 800e4d0: 4618 mov r0, r3 800e4d2: 3718 adds r7, #24 800e4d4: 46bd mov sp, r7 800e4d6: bd80 pop {r7, pc} 800e4d8: ffe1f7fd .word 0xffe1f7fd 800e4dc: ff1f0efe .word 0xff1f0efe 0800e4e0 : * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { 800e4e0: b580 push {r7, lr} 800e4e2: b086 sub sp, #24 800e4e4: af00 add r7, sp, #0 800e4e6: 60f8 str r0, [r7, #12] 800e4e8: 60b9 str r1, [r7, #8] 800e4ea: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e4ec: 2300 movs r3, #0 800e4ee: 75fb strb r3, [r7, #23] assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); /* Verification if multimode is disabled (for devices with several ADC) */ /* If multimode is enabled, dedicated function multimode conversion */ /* start DMA must be used. */ if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) 800e4f0: 68fb ldr r3, [r7, #12] 800e4f2: 681b ldr r3, [r3, #0] 800e4f4: 4a64 ldr r2, [pc, #400] @ (800e688 ) 800e4f6: 4293 cmp r3, r2 800e4f8: d004 beq.n 800e504 800e4fa: 68fb ldr r3, [r7, #12] 800e4fc: 681b ldr r3, [r3, #0] 800e4fe: 4a63 ldr r2, [pc, #396] @ (800e68c ) 800e500: 4293 cmp r3, r2 800e502: d106 bne.n 800e512 800e504: 4b60 ldr r3, [pc, #384] @ (800e688 ) 800e506: 685b ldr r3, [r3, #4] 800e508: f403 2370 and.w r3, r3, #983040 @ 0xf0000 800e50c: 2b00 cmp r3, #0 800e50e: f040 80b3 bne.w 800e678 { /* Process locked */ __HAL_LOCK(hadc); 800e512: 68fb ldr r3, [r7, #12] 800e514: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e518: 2b01 cmp r3, #1 800e51a: d101 bne.n 800e520 800e51c: 2302 movs r3, #2 800e51e: e0ae b.n 800e67e 800e520: 68fb ldr r3, [r7, #12] 800e522: 2201 movs r2, #1 800e524: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 800e528: 68f8 ldr r0, [r7, #12] 800e52a: f000 fa89 bl 800ea40 800e52e: 4603 mov r3, r0 800e530: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800e532: 7dfb ldrb r3, [r7, #23] 800e534: 2b00 cmp r3, #0 800e536: f040 809a bne.w 800e66e { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 800e53a: 68fb ldr r3, [r7, #12] 800e53c: 6a9b ldr r3, [r3, #40] @ 0x28 800e53e: f423 6370 bic.w r3, r3, #3840 @ 0xf00 800e542: f023 0301 bic.w r3, r3, #1 800e546: f443 7280 orr.w r2, r3, #256 @ 0x100 800e54a: 68fb ldr r3, [r7, #12] 800e54c: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 800e54e: 68fb ldr r3, [r7, #12] 800e550: 681b ldr r3, [r3, #0] 800e552: 4a4e ldr r2, [pc, #312] @ (800e68c ) 800e554: 4293 cmp r3, r2 800e556: d105 bne.n 800e564 800e558: 4b4b ldr r3, [pc, #300] @ (800e688 ) 800e55a: 685b ldr r3, [r3, #4] 800e55c: f403 2370 and.w r3, r3, #983040 @ 0xf0000 800e560: 2b00 cmp r3, #0 800e562: d115 bne.n 800e590 { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800e564: 68fb ldr r3, [r7, #12] 800e566: 6a9b ldr r3, [r3, #40] @ 0x28 800e568: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 800e56c: 68fb ldr r3, [r7, #12] 800e56e: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800e570: 68fb ldr r3, [r7, #12] 800e572: 681b ldr r3, [r3, #0] 800e574: 685b ldr r3, [r3, #4] 800e576: f403 6380 and.w r3, r3, #1024 @ 0x400 800e57a: 2b00 cmp r3, #0 800e57c: d026 beq.n 800e5cc { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800e57e: 68fb ldr r3, [r7, #12] 800e580: 6a9b ldr r3, [r3, #40] @ 0x28 800e582: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800e586: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800e58a: 68fb ldr r3, [r7, #12] 800e58c: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800e58e: e01d b.n 800e5cc } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800e590: 68fb ldr r3, [r7, #12] 800e592: 6a9b ldr r3, [r3, #40] @ 0x28 800e594: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800e598: 68fb ldr r3, [r7, #12] 800e59a: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 800e59c: 68fb ldr r3, [r7, #12] 800e59e: 681b ldr r3, [r3, #0] 800e5a0: 4a39 ldr r2, [pc, #228] @ (800e688 ) 800e5a2: 4293 cmp r3, r2 800e5a4: d004 beq.n 800e5b0 800e5a6: 68fb ldr r3, [r7, #12] 800e5a8: 681b ldr r3, [r3, #0] 800e5aa: 4a38 ldr r2, [pc, #224] @ (800e68c ) 800e5ac: 4293 cmp r3, r2 800e5ae: d10d bne.n 800e5cc 800e5b0: 4b35 ldr r3, [pc, #212] @ (800e688 ) 800e5b2: 685b ldr r3, [r3, #4] 800e5b4: f403 6380 and.w r3, r3, #1024 @ 0x400 800e5b8: 2b00 cmp r3, #0 800e5ba: d007 beq.n 800e5cc { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800e5bc: 68fb ldr r3, [r7, #12] 800e5be: 6a9b ldr r3, [r3, #40] @ 0x28 800e5c0: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800e5c4: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800e5c8: 68fb ldr r3, [r7, #12] 800e5ca: 629a str r2, [r3, #40] @ 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800e5cc: 68fb ldr r3, [r7, #12] 800e5ce: 6a9b ldr r3, [r3, #40] @ 0x28 800e5d0: f403 5380 and.w r3, r3, #4096 @ 0x1000 800e5d4: 2b00 cmp r3, #0 800e5d6: d006 beq.n 800e5e6 { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 800e5d8: 68fb ldr r3, [r7, #12] 800e5da: 6adb ldr r3, [r3, #44] @ 0x2c 800e5dc: f023 0206 bic.w r2, r3, #6 800e5e0: 68fb ldr r3, [r7, #12] 800e5e2: 62da str r2, [r3, #44] @ 0x2c 800e5e4: e002 b.n 800e5ec } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 800e5e6: 68fb ldr r3, [r7, #12] 800e5e8: 2200 movs r2, #0 800e5ea: 62da str r2, [r3, #44] @ 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 800e5ec: 68fb ldr r3, [r7, #12] 800e5ee: 2200 movs r2, #0 800e5f0: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 800e5f4: 68fb ldr r3, [r7, #12] 800e5f6: 6a1b ldr r3, [r3, #32] 800e5f8: 4a25 ldr r2, [pc, #148] @ (800e690 ) 800e5fa: 629a str r2, [r3, #40] @ 0x28 /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 800e5fc: 68fb ldr r3, [r7, #12] 800e5fe: 6a1b ldr r3, [r3, #32] 800e600: 4a24 ldr r2, [pc, #144] @ (800e694 ) 800e602: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 800e604: 68fb ldr r3, [r7, #12] 800e606: 6a1b ldr r3, [r3, #32] 800e608: 4a23 ldr r2, [pc, #140] @ (800e698 ) 800e60a: 631a str r2, [r3, #48] @ 0x30 /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 800e60c: 68fb ldr r3, [r7, #12] 800e60e: 681b ldr r3, [r3, #0] 800e610: f06f 0202 mvn.w r2, #2 800e614: 601a str r2, [r3, #0] /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); 800e616: 68fb ldr r3, [r7, #12] 800e618: 681b ldr r3, [r3, #0] 800e61a: 689a ldr r2, [r3, #8] 800e61c: 68fb ldr r3, [r7, #12] 800e61e: 681b ldr r3, [r3, #0] 800e620: f442 7280 orr.w r2, r2, #256 @ 0x100 800e624: 609a str r2, [r3, #8] /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 800e626: 68fb ldr r3, [r7, #12] 800e628: 6a18 ldr r0, [r3, #32] 800e62a: 68fb ldr r3, [r7, #12] 800e62c: 681b ldr r3, [r3, #0] 800e62e: 334c adds r3, #76 @ 0x4c 800e630: 4619 mov r1, r3 800e632: 68ba ldr r2, [r7, #8] 800e634: 687b ldr r3, [r7, #4] 800e636: f001 fc31 bl 800fe9c /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) 800e63a: 68fb ldr r3, [r7, #12] 800e63c: 681b ldr r3, [r3, #0] 800e63e: 689b ldr r3, [r3, #8] 800e640: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800e644: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e648: d108 bne.n 800e65c { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 800e64a: 68fb ldr r3, [r7, #12] 800e64c: 681b ldr r3, [r3, #0] 800e64e: 689a ldr r2, [r3, #8] 800e650: 68fb ldr r3, [r7, #12] 800e652: 681b ldr r3, [r3, #0] 800e654: f442 02a0 orr.w r2, r2, #5242880 @ 0x500000 800e658: 609a str r2, [r3, #8] if (tmp_hal_status == HAL_OK) 800e65a: e00f b.n 800e67c } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 800e65c: 68fb ldr r3, [r7, #12] 800e65e: 681b ldr r3, [r3, #0] 800e660: 689a ldr r2, [r3, #8] 800e662: 68fb ldr r3, [r7, #12] 800e664: 681b ldr r3, [r3, #0] 800e666: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 800e66a: 609a str r2, [r3, #8] if (tmp_hal_status == HAL_OK) 800e66c: e006 b.n 800e67c } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 800e66e: 68fb ldr r3, [r7, #12] 800e670: 2200 movs r2, #0 800e672: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (tmp_hal_status == HAL_OK) 800e676: e001 b.n 800e67c } } else { tmp_hal_status = HAL_ERROR; 800e678: 2301 movs r3, #1 800e67a: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800e67c: 7dfb ldrb r3, [r7, #23] } 800e67e: 4618 mov r0, r3 800e680: 3718 adds r7, #24 800e682: 46bd mov sp, r7 800e684: bd80 pop {r7, pc} 800e686: bf00 nop 800e688: 40012400 .word 0x40012400 800e68c: 40012800 .word 0x40012800 800e690: 0800eb77 .word 0x0800eb77 800e694: 0800ebf3 .word 0x0800ebf3 800e698: 0800ec0f .word 0x0800ec0f 0800e69c : * @brief Handles ADC interrupt request * @param hadc: ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { 800e69c: b580 push {r7, lr} 800e69e: b084 sub sp, #16 800e6a0: af00 add r7, sp, #0 800e6a2: 6078 str r0, [r7, #4] uint32_t tmp_sr = hadc->Instance->SR; 800e6a4: 687b ldr r3, [r7, #4] 800e6a6: 681b ldr r3, [r3, #0] 800e6a8: 681b ldr r3, [r3, #0] 800e6aa: 60fb str r3, [r7, #12] uint32_t tmp_cr1 = hadc->Instance->CR1; 800e6ac: 687b ldr r3, [r7, #4] 800e6ae: 681b ldr r3, [r3, #0] 800e6b0: 685b ldr r3, [r3, #4] 800e6b2: 60bb str r3, [r7, #8] assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); /* ========== Check End of Conversion flag for regular group ========== */ if((tmp_cr1 & ADC_IT_EOC) == ADC_IT_EOC) 800e6b4: 68bb ldr r3, [r7, #8] 800e6b6: f003 0320 and.w r3, r3, #32 800e6ba: 2b00 cmp r3, #0 800e6bc: d03e beq.n 800e73c { if((tmp_sr & ADC_FLAG_EOC) == ADC_FLAG_EOC) 800e6be: 68fb ldr r3, [r7, #12] 800e6c0: f003 0302 and.w r3, r3, #2 800e6c4: 2b00 cmp r3, #0 800e6c6: d039 beq.n 800e73c { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 800e6c8: 687b ldr r3, [r7, #4] 800e6ca: 6a9b ldr r3, [r3, #40] @ 0x28 800e6cc: f003 0310 and.w r3, r3, #16 800e6d0: 2b00 cmp r3, #0 800e6d2: d105 bne.n 800e6e0 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800e6d4: 687b ldr r3, [r7, #4] 800e6d6: 6a9b ldr r3, [r3, #40] @ 0x28 800e6d8: f443 7200 orr.w r2, r3, #512 @ 0x200 800e6dc: 687b ldr r3, [r7, #4] 800e6de: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e6e0: 687b ldr r3, [r7, #4] 800e6e2: 681b ldr r3, [r3, #0] 800e6e4: 689b ldr r3, [r3, #8] 800e6e6: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800e6ea: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e6ee: d11d bne.n 800e72c (hadc->Init.ContinuousConvMode == DISABLE) ) 800e6f0: 687b ldr r3, [r7, #4] 800e6f2: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e6f4: 2b00 cmp r3, #0 800e6f6: d119 bne.n 800e72c { /* Disable ADC end of conversion interrupt on group regular */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); 800e6f8: 687b ldr r3, [r7, #4] 800e6fa: 681b ldr r3, [r3, #0] 800e6fc: 685a ldr r2, [r3, #4] 800e6fe: 687b ldr r3, [r7, #4] 800e700: 681b ldr r3, [r3, #0] 800e702: f022 0220 bic.w r2, r2, #32 800e706: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800e708: 687b ldr r3, [r7, #4] 800e70a: 6a9b ldr r3, [r3, #40] @ 0x28 800e70c: f423 7280 bic.w r2, r3, #256 @ 0x100 800e710: 687b ldr r3, [r7, #4] 800e712: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800e714: 687b ldr r3, [r7, #4] 800e716: 6a9b ldr r3, [r3, #40] @ 0x28 800e718: f403 5380 and.w r3, r3, #4096 @ 0x1000 800e71c: 2b00 cmp r3, #0 800e71e: d105 bne.n 800e72c { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800e720: 687b ldr r3, [r7, #4] 800e722: 6a9b ldr r3, [r3, #40] @ 0x28 800e724: f043 0201 orr.w r2, r3, #1 800e728: 687b ldr r3, [r7, #4] 800e72a: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800e72c: 6878 ldr r0, [r7, #4] 800e72e: f7fa ff0d bl 800954c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 800e732: 687b ldr r3, [r7, #4] 800e734: 681b ldr r3, [r3, #0] 800e736: f06f 0212 mvn.w r2, #18 800e73a: 601a str r2, [r3, #0] } } /* ========== Check End of Conversion flag for injected group ========== */ if((tmp_cr1 & ADC_IT_JEOC) == ADC_IT_JEOC) 800e73c: 68bb ldr r3, [r7, #8] 800e73e: f003 0380 and.w r3, r3, #128 @ 0x80 800e742: 2b00 cmp r3, #0 800e744: d04d beq.n 800e7e2 { if((tmp_sr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) 800e746: 68fb ldr r3, [r7, #12] 800e748: f003 0304 and.w r3, r3, #4 800e74c: 2b00 cmp r3, #0 800e74e: d048 beq.n 800e7e2 { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 800e750: 687b ldr r3, [r7, #4] 800e752: 6a9b ldr r3, [r3, #40] @ 0x28 800e754: f003 0310 and.w r3, r3, #16 800e758: 2b00 cmp r3, #0 800e75a: d105 bne.n 800e768 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 800e75c: 687b ldr r3, [r7, #4] 800e75e: 6a9b ldr r3, [r3, #40] @ 0x28 800e760: f443 5200 orr.w r2, r3, #8192 @ 0x2000 800e764: 687b ldr r3, [r7, #4] 800e766: 629a str r2, [r3, #40] @ 0x28 /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 800e768: 687b ldr r3, [r7, #4] 800e76a: 681b ldr r3, [r3, #0] 800e76c: 689b ldr r3, [r3, #8] 800e76e: f403 43e0 and.w r3, r3, #28672 @ 0x7000 800e772: f5b3 4fe0 cmp.w r3, #28672 @ 0x7000 800e776: d012 beq.n 800e79e (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 800e778: 687b ldr r3, [r7, #4] 800e77a: 681b ldr r3, [r3, #0] 800e77c: 685b ldr r3, [r3, #4] 800e77e: f403 6380 and.w r3, r3, #1024 @ 0x400 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 800e782: 2b00 cmp r3, #0 800e784: d125 bne.n 800e7d2 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e786: 687b ldr r3, [r7, #4] 800e788: 681b ldr r3, [r3, #0] 800e78a: 689b ldr r3, [r3, #8] 800e78c: f403 2360 and.w r3, r3, #917504 @ 0xe0000 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 800e790: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e794: d11d bne.n 800e7d2 (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) 800e796: 687b ldr r3, [r7, #4] 800e798: 7b1b ldrb r3, [r3, #12] (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e79a: 2b00 cmp r3, #0 800e79c: d119 bne.n 800e7d2 { /* Disable ADC end of conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 800e79e: 687b ldr r3, [r7, #4] 800e7a0: 681b ldr r3, [r3, #0] 800e7a2: 685a ldr r2, [r3, #4] 800e7a4: 687b ldr r3, [r7, #4] 800e7a6: 681b ldr r3, [r3, #0] 800e7a8: f022 0280 bic.w r2, r2, #128 @ 0x80 800e7ac: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 800e7ae: 687b ldr r3, [r7, #4] 800e7b0: 6a9b ldr r3, [r3, #40] @ 0x28 800e7b2: f423 5280 bic.w r2, r3, #4096 @ 0x1000 800e7b6: 687b ldr r3, [r7, #4] 800e7b8: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 800e7ba: 687b ldr r3, [r7, #4] 800e7bc: 6a9b ldr r3, [r3, #40] @ 0x28 800e7be: f403 7380 and.w r3, r3, #256 @ 0x100 800e7c2: 2b00 cmp r3, #0 800e7c4: d105 bne.n 800e7d2 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800e7c6: 687b ldr r3, [r7, #4] 800e7c8: 6a9b ldr r3, [r3, #40] @ 0x28 800e7ca: f043 0201 orr.w r2, r3, #1 800e7ce: 687b ldr r3, [r7, #4] 800e7d0: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); 800e7d2: 6878 ldr r0, [r7, #4] 800e7d4: f000 fae4 bl 800eda0 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); 800e7d8: 687b ldr r3, [r7, #4] 800e7da: 681b ldr r3, [r3, #0] 800e7dc: f06f 020c mvn.w r2, #12 800e7e0: 601a str r2, [r3, #0] } } /* ========== Check Analog watchdog flags ========== */ if((tmp_cr1 & ADC_IT_AWD) == ADC_IT_AWD) 800e7e2: 68bb ldr r3, [r7, #8] 800e7e4: f003 0340 and.w r3, r3, #64 @ 0x40 800e7e8: 2b00 cmp r3, #0 800e7ea: d012 beq.n 800e812 { if((tmp_sr & ADC_FLAG_AWD) == ADC_FLAG_AWD) 800e7ec: 68fb ldr r3, [r7, #12] 800e7ee: f003 0301 and.w r3, r3, #1 800e7f2: 2b00 cmp r3, #0 800e7f4: d00d beq.n 800e812 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 800e7f6: 687b ldr r3, [r7, #4] 800e7f8: 6a9b ldr r3, [r3, #40] @ 0x28 800e7fa: f443 3280 orr.w r2, r3, #65536 @ 0x10000 800e7fe: 687b ldr r3, [r7, #4] 800e800: 629a str r2, [r3, #40] @ 0x28 /* Level out of window callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); 800e802: 6878 ldr r0, [r7, #4] 800e804: f000 f812 bl 800e82c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear the ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); 800e808: 687b ldr r3, [r7, #4] 800e80a: 681b ldr r3, [r3, #0] 800e80c: f06f 0201 mvn.w r2, #1 800e810: 601a str r2, [r3, #0] } } } 800e812: bf00 nop 800e814: 3710 adds r7, #16 800e816: 46bd mov sp, r7 800e818: bd80 pop {r7, pc} 0800e81a : * @brief Conversion DMA half-transfer callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) { 800e81a: b480 push {r7} 800e81c: b083 sub sp, #12 800e81e: af00 add r7, sp, #0 800e820: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 800e822: bf00 nop 800e824: 370c adds r7, #12 800e826: 46bd mov sp, r7 800e828: bc80 pop {r7} 800e82a: 4770 bx lr 0800e82c : * @brief Analog watchdog callback in non blocking mode. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { 800e82c: b480 push {r7} 800e82e: b083 sub sp, #12 800e830: af00 add r7, sp, #0 800e832: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } 800e834: bf00 nop 800e836: 370c adds r7, #12 800e838: 46bd mov sp, r7 800e83a: bc80 pop {r7} 800e83c: 4770 bx lr 0800e83e : * (ADC conversion with interruption or transfer by DMA) * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 800e83e: b480 push {r7} 800e840: b083 sub sp, #12 800e842: af00 add r7, sp, #0 800e844: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 800e846: bf00 nop 800e848: 370c adds r7, #12 800e84a: 46bd mov sp, r7 800e84c: bc80 pop {r7} 800e84e: 4770 bx lr 0800e850 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 800e850: b480 push {r7} 800e852: b085 sub sp, #20 800e854: af00 add r7, sp, #0 800e856: 6078 str r0, [r7, #4] 800e858: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e85a: 2300 movs r3, #0 800e85c: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 800e85e: 2300 movs r3, #0 800e860: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 800e862: 687b ldr r3, [r7, #4] 800e864: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e868: 2b01 cmp r3, #1 800e86a: d101 bne.n 800e870 800e86c: 2302 movs r3, #2 800e86e: e0dc b.n 800ea2a 800e870: 687b ldr r3, [r7, #4] 800e872: 2201 movs r2, #1 800e874: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 800e878: 683b ldr r3, [r7, #0] 800e87a: 685b ldr r3, [r3, #4] 800e87c: 2b06 cmp r3, #6 800e87e: d81c bhi.n 800e8ba { MODIFY_REG(hadc->Instance->SQR3 , 800e880: 687b ldr r3, [r7, #4] 800e882: 681b ldr r3, [r3, #0] 800e884: 6b59 ldr r1, [r3, #52] @ 0x34 800e886: 683b ldr r3, [r7, #0] 800e888: 685a ldr r2, [r3, #4] 800e88a: 4613 mov r3, r2 800e88c: 009b lsls r3, r3, #2 800e88e: 4413 add r3, r2 800e890: 3b05 subs r3, #5 800e892: 221f movs r2, #31 800e894: fa02 f303 lsl.w r3, r2, r3 800e898: 43db mvns r3, r3 800e89a: 4019 ands r1, r3 800e89c: 683b ldr r3, [r7, #0] 800e89e: 6818 ldr r0, [r3, #0] 800e8a0: 683b ldr r3, [r7, #0] 800e8a2: 685a ldr r2, [r3, #4] 800e8a4: 4613 mov r3, r2 800e8a6: 009b lsls r3, r3, #2 800e8a8: 4413 add r3, r2 800e8aa: 3b05 subs r3, #5 800e8ac: fa00 f203 lsl.w r2, r0, r3 800e8b0: 687b ldr r3, [r7, #4] 800e8b2: 681b ldr r3, [r3, #0] 800e8b4: 430a orrs r2, r1 800e8b6: 635a str r2, [r3, #52] @ 0x34 800e8b8: e03c b.n 800e934 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 800e8ba: 683b ldr r3, [r7, #0] 800e8bc: 685b ldr r3, [r3, #4] 800e8be: 2b0c cmp r3, #12 800e8c0: d81c bhi.n 800e8fc { MODIFY_REG(hadc->Instance->SQR2 , 800e8c2: 687b ldr r3, [r7, #4] 800e8c4: 681b ldr r3, [r3, #0] 800e8c6: 6b19 ldr r1, [r3, #48] @ 0x30 800e8c8: 683b ldr r3, [r7, #0] 800e8ca: 685a ldr r2, [r3, #4] 800e8cc: 4613 mov r3, r2 800e8ce: 009b lsls r3, r3, #2 800e8d0: 4413 add r3, r2 800e8d2: 3b23 subs r3, #35 @ 0x23 800e8d4: 221f movs r2, #31 800e8d6: fa02 f303 lsl.w r3, r2, r3 800e8da: 43db mvns r3, r3 800e8dc: 4019 ands r1, r3 800e8de: 683b ldr r3, [r7, #0] 800e8e0: 6818 ldr r0, [r3, #0] 800e8e2: 683b ldr r3, [r7, #0] 800e8e4: 685a ldr r2, [r3, #4] 800e8e6: 4613 mov r3, r2 800e8e8: 009b lsls r3, r3, #2 800e8ea: 4413 add r3, r2 800e8ec: 3b23 subs r3, #35 @ 0x23 800e8ee: fa00 f203 lsl.w r2, r0, r3 800e8f2: 687b ldr r3, [r7, #4] 800e8f4: 681b ldr r3, [r3, #0] 800e8f6: 430a orrs r2, r1 800e8f8: 631a str r2, [r3, #48] @ 0x30 800e8fa: e01b b.n 800e934 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 800e8fc: 687b ldr r3, [r7, #4] 800e8fe: 681b ldr r3, [r3, #0] 800e900: 6ad9 ldr r1, [r3, #44] @ 0x2c 800e902: 683b ldr r3, [r7, #0] 800e904: 685a ldr r2, [r3, #4] 800e906: 4613 mov r3, r2 800e908: 009b lsls r3, r3, #2 800e90a: 4413 add r3, r2 800e90c: 3b41 subs r3, #65 @ 0x41 800e90e: 221f movs r2, #31 800e910: fa02 f303 lsl.w r3, r2, r3 800e914: 43db mvns r3, r3 800e916: 4019 ands r1, r3 800e918: 683b ldr r3, [r7, #0] 800e91a: 6818 ldr r0, [r3, #0] 800e91c: 683b ldr r3, [r7, #0] 800e91e: 685a ldr r2, [r3, #4] 800e920: 4613 mov r3, r2 800e922: 009b lsls r3, r3, #2 800e924: 4413 add r3, r2 800e926: 3b41 subs r3, #65 @ 0x41 800e928: fa00 f203 lsl.w r2, r0, r3 800e92c: 687b ldr r3, [r7, #4] 800e92e: 681b ldr r3, [r3, #0] 800e930: 430a orrs r2, r1 800e932: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 800e934: 683b ldr r3, [r7, #0] 800e936: 681b ldr r3, [r3, #0] 800e938: 2b09 cmp r3, #9 800e93a: d91c bls.n 800e976 { MODIFY_REG(hadc->Instance->SMPR1 , 800e93c: 687b ldr r3, [r7, #4] 800e93e: 681b ldr r3, [r3, #0] 800e940: 68d9 ldr r1, [r3, #12] 800e942: 683b ldr r3, [r7, #0] 800e944: 681a ldr r2, [r3, #0] 800e946: 4613 mov r3, r2 800e948: 005b lsls r3, r3, #1 800e94a: 4413 add r3, r2 800e94c: 3b1e subs r3, #30 800e94e: 2207 movs r2, #7 800e950: fa02 f303 lsl.w r3, r2, r3 800e954: 43db mvns r3, r3 800e956: 4019 ands r1, r3 800e958: 683b ldr r3, [r7, #0] 800e95a: 6898 ldr r0, [r3, #8] 800e95c: 683b ldr r3, [r7, #0] 800e95e: 681a ldr r2, [r3, #0] 800e960: 4613 mov r3, r2 800e962: 005b lsls r3, r3, #1 800e964: 4413 add r3, r2 800e966: 3b1e subs r3, #30 800e968: fa00 f203 lsl.w r2, r0, r3 800e96c: 687b ldr r3, [r7, #4] 800e96e: 681b ldr r3, [r3, #0] 800e970: 430a orrs r2, r1 800e972: 60da str r2, [r3, #12] 800e974: e019 b.n 800e9aa ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 800e976: 687b ldr r3, [r7, #4] 800e978: 681b ldr r3, [r3, #0] 800e97a: 6919 ldr r1, [r3, #16] 800e97c: 683b ldr r3, [r7, #0] 800e97e: 681a ldr r2, [r3, #0] 800e980: 4613 mov r3, r2 800e982: 005b lsls r3, r3, #1 800e984: 4413 add r3, r2 800e986: 2207 movs r2, #7 800e988: fa02 f303 lsl.w r3, r2, r3 800e98c: 43db mvns r3, r3 800e98e: 4019 ands r1, r3 800e990: 683b ldr r3, [r7, #0] 800e992: 6898 ldr r0, [r3, #8] 800e994: 683b ldr r3, [r7, #0] 800e996: 681a ldr r2, [r3, #0] 800e998: 4613 mov r3, r2 800e99a: 005b lsls r3, r3, #1 800e99c: 4413 add r3, r2 800e99e: fa00 f203 lsl.w r2, r0, r3 800e9a2: 687b ldr r3, [r7, #4] 800e9a4: 681b ldr r3, [r3, #0] 800e9a6: 430a orrs r2, r1 800e9a8: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800e9aa: 683b ldr r3, [r7, #0] 800e9ac: 681b ldr r3, [r3, #0] 800e9ae: 2b10 cmp r3, #16 800e9b0: d003 beq.n 800e9ba (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 800e9b2: 683b ldr r3, [r7, #0] 800e9b4: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800e9b6: 2b11 cmp r3, #17 800e9b8: d132 bne.n 800ea20 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 800e9ba: 687b ldr r3, [r7, #4] 800e9bc: 681b ldr r3, [r3, #0] 800e9be: 4a1d ldr r2, [pc, #116] @ (800ea34 ) 800e9c0: 4293 cmp r3, r2 800e9c2: d125 bne.n 800ea10 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 800e9c4: 687b ldr r3, [r7, #4] 800e9c6: 681b ldr r3, [r3, #0] 800e9c8: 689b ldr r3, [r3, #8] 800e9ca: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800e9ce: 2b00 cmp r3, #0 800e9d0: d126 bne.n 800ea20 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 800e9d2: 687b ldr r3, [r7, #4] 800e9d4: 681b ldr r3, [r3, #0] 800e9d6: 689a ldr r2, [r3, #8] 800e9d8: 687b ldr r3, [r7, #4] 800e9da: 681b ldr r3, [r3, #0] 800e9dc: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 800e9e0: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 800e9e2: 683b ldr r3, [r7, #0] 800e9e4: 681b ldr r3, [r3, #0] 800e9e6: 2b10 cmp r3, #16 800e9e8: d11a bne.n 800ea20 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 800e9ea: 4b13 ldr r3, [pc, #76] @ (800ea38 ) 800e9ec: 681b ldr r3, [r3, #0] 800e9ee: 4a13 ldr r2, [pc, #76] @ (800ea3c ) 800e9f0: fba2 2303 umull r2, r3, r2, r3 800e9f4: 0c9a lsrs r2, r3, #18 800e9f6: 4613 mov r3, r2 800e9f8: 009b lsls r3, r3, #2 800e9fa: 4413 add r3, r2 800e9fc: 005b lsls r3, r3, #1 800e9fe: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800ea00: e002 b.n 800ea08 { wait_loop_index--; 800ea02: 68bb ldr r3, [r7, #8] 800ea04: 3b01 subs r3, #1 800ea06: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800ea08: 68bb ldr r3, [r7, #8] 800ea0a: 2b00 cmp r3, #0 800ea0c: d1f9 bne.n 800ea02 800ea0e: e007 b.n 800ea20 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800ea10: 687b ldr r3, [r7, #4] 800ea12: 6a9b ldr r3, [r3, #40] @ 0x28 800ea14: f043 0220 orr.w r2, r3, #32 800ea18: 687b ldr r3, [r7, #4] 800ea1a: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800ea1c: 2301 movs r3, #1 800ea1e: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 800ea20: 687b ldr r3, [r7, #4] 800ea22: 2200 movs r2, #0 800ea24: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800ea28: 7bfb ldrb r3, [r7, #15] } 800ea2a: 4618 mov r0, r3 800ea2c: 3714 adds r7, #20 800ea2e: 46bd mov sp, r7 800ea30: bc80 pop {r7} 800ea32: 4770 bx lr 800ea34: 40012400 .word 0x40012400 800ea38: 20000084 .word 0x20000084 800ea3c: 431bde83 .word 0x431bde83 0800ea40 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 800ea40: b580 push {r7, lr} 800ea42: b084 sub sp, #16 800ea44: af00 add r7, sp, #0 800ea46: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800ea48: 2300 movs r3, #0 800ea4a: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 800ea4c: 2300 movs r3, #0 800ea4e: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 800ea50: 687b ldr r3, [r7, #4] 800ea52: 681b ldr r3, [r3, #0] 800ea54: 689b ldr r3, [r3, #8] 800ea56: f003 0301 and.w r3, r3, #1 800ea5a: 2b01 cmp r3, #1 800ea5c: d040 beq.n 800eae0 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 800ea5e: 687b ldr r3, [r7, #4] 800ea60: 681b ldr r3, [r3, #0] 800ea62: 689a ldr r2, [r3, #8] 800ea64: 687b ldr r3, [r7, #4] 800ea66: 681b ldr r3, [r3, #0] 800ea68: f042 0201 orr.w r2, r2, #1 800ea6c: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 800ea6e: 4b1f ldr r3, [pc, #124] @ (800eaec ) 800ea70: 681b ldr r3, [r3, #0] 800ea72: 4a1f ldr r2, [pc, #124] @ (800eaf0 ) 800ea74: fba2 2303 umull r2, r3, r2, r3 800ea78: 0c9b lsrs r3, r3, #18 800ea7a: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800ea7c: e002 b.n 800ea84 { wait_loop_index--; 800ea7e: 68bb ldr r3, [r7, #8] 800ea80: 3b01 subs r3, #1 800ea82: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800ea84: 68bb ldr r3, [r7, #8] 800ea86: 2b00 cmp r3, #0 800ea88: d1f9 bne.n 800ea7e } /* Get tick count */ tickstart = HAL_GetTick(); 800ea8a: f7ff fc23 bl 800e2d4 800ea8e: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 800ea90: e01f b.n 800ead2 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 800ea92: f7ff fc1f bl 800e2d4 800ea96: 4602 mov r2, r0 800ea98: 68fb ldr r3, [r7, #12] 800ea9a: 1ad3 subs r3, r2, r3 800ea9c: 2b02 cmp r3, #2 800ea9e: d918 bls.n 800ead2 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 800eaa0: 687b ldr r3, [r7, #4] 800eaa2: 681b ldr r3, [r3, #0] 800eaa4: 689b ldr r3, [r3, #8] 800eaa6: f003 0301 and.w r3, r3, #1 800eaaa: 2b01 cmp r3, #1 800eaac: d011 beq.n 800ead2 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800eaae: 687b ldr r3, [r7, #4] 800eab0: 6a9b ldr r3, [r3, #40] @ 0x28 800eab2: f043 0210 orr.w r2, r3, #16 800eab6: 687b ldr r3, [r7, #4] 800eab8: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800eaba: 687b ldr r3, [r7, #4] 800eabc: 6adb ldr r3, [r3, #44] @ 0x2c 800eabe: f043 0201 orr.w r2, r3, #1 800eac2: 687b ldr r3, [r7, #4] 800eac4: 62da str r2, [r3, #44] @ 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 800eac6: 687b ldr r3, [r7, #4] 800eac8: 2200 movs r2, #0 800eaca: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800eace: 2301 movs r3, #1 800ead0: e007 b.n 800eae2 while(ADC_IS_ENABLE(hadc) == RESET) 800ead2: 687b ldr r3, [r7, #4] 800ead4: 681b ldr r3, [r3, #0] 800ead6: 689b ldr r3, [r3, #8] 800ead8: f003 0301 and.w r3, r3, #1 800eadc: 2b01 cmp r3, #1 800eade: d1d8 bne.n 800ea92 } } } /* Return HAL status */ return HAL_OK; 800eae0: 2300 movs r3, #0 } 800eae2: 4618 mov r0, r3 800eae4: 3710 adds r7, #16 800eae6: 46bd mov sp, r7 800eae8: bd80 pop {r7, pc} 800eaea: bf00 nop 800eaec: 20000084 .word 0x20000084 800eaf0: 431bde83 .word 0x431bde83 0800eaf4 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 800eaf4: b580 push {r7, lr} 800eaf6: b084 sub sp, #16 800eaf8: af00 add r7, sp, #0 800eafa: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800eafc: 2300 movs r3, #0 800eafe: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 800eb00: 687b ldr r3, [r7, #4] 800eb02: 681b ldr r3, [r3, #0] 800eb04: 689b ldr r3, [r3, #8] 800eb06: f003 0301 and.w r3, r3, #1 800eb0a: 2b01 cmp r3, #1 800eb0c: d12e bne.n 800eb6c { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 800eb0e: 687b ldr r3, [r7, #4] 800eb10: 681b ldr r3, [r3, #0] 800eb12: 689a ldr r2, [r3, #8] 800eb14: 687b ldr r3, [r7, #4] 800eb16: 681b ldr r3, [r3, #0] 800eb18: f022 0201 bic.w r2, r2, #1 800eb1c: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 800eb1e: f7ff fbd9 bl 800e2d4 800eb22: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 800eb24: e01b b.n 800eb5e { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800eb26: f7ff fbd5 bl 800e2d4 800eb2a: 4602 mov r2, r0 800eb2c: 68fb ldr r3, [r7, #12] 800eb2e: 1ad3 subs r3, r2, r3 800eb30: 2b02 cmp r3, #2 800eb32: d914 bls.n 800eb5e { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 800eb34: 687b ldr r3, [r7, #4] 800eb36: 681b ldr r3, [r3, #0] 800eb38: 689b ldr r3, [r3, #8] 800eb3a: f003 0301 and.w r3, r3, #1 800eb3e: 2b01 cmp r3, #1 800eb40: d10d bne.n 800eb5e { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800eb42: 687b ldr r3, [r7, #4] 800eb44: 6a9b ldr r3, [r3, #40] @ 0x28 800eb46: f043 0210 orr.w r2, r3, #16 800eb4a: 687b ldr r3, [r7, #4] 800eb4c: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800eb4e: 687b ldr r3, [r7, #4] 800eb50: 6adb ldr r3, [r3, #44] @ 0x2c 800eb52: f043 0201 orr.w r2, r3, #1 800eb56: 687b ldr r3, [r7, #4] 800eb58: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 800eb5a: 2301 movs r3, #1 800eb5c: e007 b.n 800eb6e while(ADC_IS_ENABLE(hadc) != RESET) 800eb5e: 687b ldr r3, [r7, #4] 800eb60: 681b ldr r3, [r3, #0] 800eb62: 689b ldr r3, [r3, #8] 800eb64: f003 0301 and.w r3, r3, #1 800eb68: 2b01 cmp r3, #1 800eb6a: d0dc beq.n 800eb26 } } } /* Return HAL status */ return HAL_OK; 800eb6c: 2300 movs r3, #0 } 800eb6e: 4618 mov r0, r3 800eb70: 3710 adds r7, #16 800eb72: 46bd mov sp, r7 800eb74: bd80 pop {r7, pc} 0800eb76 : * @brief DMA transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 800eb76: b580 push {r7, lr} 800eb78: b084 sub sp, #16 800eb7a: af00 add r7, sp, #0 800eb7c: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800eb7e: 687b ldr r3, [r7, #4] 800eb80: 6a5b ldr r3, [r3, #36] @ 0x24 800eb82: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) 800eb84: 68fb ldr r3, [r7, #12] 800eb86: 6a9b ldr r3, [r3, #40] @ 0x28 800eb88: f003 0350 and.w r3, r3, #80 @ 0x50 800eb8c: 2b00 cmp r3, #0 800eb8e: d127 bne.n 800ebe0 { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800eb90: 68fb ldr r3, [r7, #12] 800eb92: 6a9b ldr r3, [r3, #40] @ 0x28 800eb94: f443 7200 orr.w r2, r3, #512 @ 0x200 800eb98: 68fb ldr r3, [r7, #12] 800eb9a: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800eb9c: 68fb ldr r3, [r7, #12] 800eb9e: 681b ldr r3, [r3, #0] 800eba0: 689b ldr r3, [r3, #8] 800eba2: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800eba6: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800ebaa: d115 bne.n 800ebd8 (hadc->Init.ContinuousConvMode == DISABLE) ) 800ebac: 68fb ldr r3, [r7, #12] 800ebae: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800ebb0: 2b00 cmp r3, #0 800ebb2: d111 bne.n 800ebd8 { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800ebb4: 68fb ldr r3, [r7, #12] 800ebb6: 6a9b ldr r3, [r3, #40] @ 0x28 800ebb8: f423 7280 bic.w r2, r3, #256 @ 0x100 800ebbc: 68fb ldr r3, [r7, #12] 800ebbe: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800ebc0: 68fb ldr r3, [r7, #12] 800ebc2: 6a9b ldr r3, [r3, #40] @ 0x28 800ebc4: f403 5380 and.w r3, r3, #4096 @ 0x1000 800ebc8: 2b00 cmp r3, #0 800ebca: d105 bne.n 800ebd8 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800ebcc: 68fb ldr r3, [r7, #12] 800ebce: 6a9b ldr r3, [r3, #40] @ 0x28 800ebd0: f043 0201 orr.w r2, r3, #1 800ebd4: 68fb ldr r3, [r7, #12] 800ebd6: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800ebd8: 68f8 ldr r0, [r7, #12] 800ebda: f7fa fcb7 bl 800954c else { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } 800ebde: e004 b.n 800ebea hadc->DMA_Handle->XferErrorCallback(hdma); 800ebe0: 68fb ldr r3, [r7, #12] 800ebe2: 6a1b ldr r3, [r3, #32] 800ebe4: 6b1b ldr r3, [r3, #48] @ 0x30 800ebe6: 6878 ldr r0, [r7, #4] 800ebe8: 4798 blx r3 } 800ebea: bf00 nop 800ebec: 3710 adds r7, #16 800ebee: 46bd mov sp, r7 800ebf0: bd80 pop {r7, pc} 0800ebf2 : * @brief DMA half transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 800ebf2: b580 push {r7, lr} 800ebf4: b084 sub sp, #16 800ebf6: af00 add r7, sp, #0 800ebf8: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800ebfa: 687b ldr r3, [r7, #4] 800ebfc: 6a5b ldr r3, [r3, #36] @ 0x24 800ebfe: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 800ec00: 68f8 ldr r0, [r7, #12] 800ec02: f7ff fe0a bl 800e81a #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800ec06: bf00 nop 800ec08: 3710 adds r7, #16 800ec0a: 46bd mov sp, r7 800ec0c: bd80 pop {r7, pc} 0800ec0e : * @brief DMA error callback * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 800ec0e: b580 push {r7, lr} 800ec10: b084 sub sp, #16 800ec12: af00 add r7, sp, #0 800ec14: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800ec16: 687b ldr r3, [r7, #4] 800ec18: 6a5b ldr r3, [r3, #36] @ 0x24 800ec1a: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 800ec1c: 68fb ldr r3, [r7, #12] 800ec1e: 6a9b ldr r3, [r3, #40] @ 0x28 800ec20: f043 0240 orr.w r2, r3, #64 @ 0x40 800ec24: 68fb ldr r3, [r7, #12] 800ec26: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 800ec28: 68fb ldr r3, [r7, #12] 800ec2a: 6adb ldr r3, [r3, #44] @ 0x2c 800ec2c: f043 0204 orr.w r2, r3, #4 800ec30: 68fb ldr r3, [r7, #12] 800ec32: 62da str r2, [r3, #44] @ 0x2c /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 800ec34: 68f8 ldr r0, [r7, #12] 800ec36: f7ff fe02 bl 800e83e #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800ec3a: bf00 nop 800ec3c: 3710 adds r7, #16 800ec3e: 46bd mov sp, r7 800ec40: bd80 pop {r7, pc} ... 0800ec44 : * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { 800ec44: b590 push {r4, r7, lr} 800ec46: b087 sub sp, #28 800ec48: af00 add r7, sp, #0 800ec4a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800ec4c: 2300 movs r3, #0 800ec4e: 75fb strb r3, [r7, #23] uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; 800ec50: 2300 movs r3, #0 800ec52: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800ec54: 687b ldr r3, [r7, #4] 800ec56: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800ec5a: 2b01 cmp r3, #1 800ec5c: d101 bne.n 800ec62 800ec5e: 2302 movs r3, #2 800ec60: e097 b.n 800ed92 800ec62: 687b ldr r3, [r7, #4] 800ec64: 2201 movs r2, #1 800ec66: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* 1. Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800ec6a: 6878 ldr r0, [r7, #4] 800ec6c: f7ff ff42 bl 800eaf4 800ec70: 4603 mov r3, r0 800ec72: 75fb strb r3, [r7, #23] /* 2. Calibration prerequisite delay before starting the calibration. */ /* - ADC must be enabled for at least two ADC clock cycles */ tmp_hal_status = ADC_Enable(hadc); 800ec74: 6878 ldr r0, [r7, #4] 800ec76: f7ff fee3 bl 800ea40 800ec7a: 4603 mov r3, r0 800ec7c: 75fb strb r3, [r7, #23] /* Check if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800ec7e: 7dfb ldrb r3, [r7, #23] 800ec80: 2b00 cmp r3, #0 800ec82: f040 8081 bne.w 800ed88 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800ec86: 687b ldr r3, [r7, #4] 800ec88: 6a9b ldr r3, [r3, #40] @ 0x28 800ec8a: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800ec8e: f023 0302 bic.w r3, r3, #2 800ec92: f043 0202 orr.w r2, r3, #2 800ec96: 687b ldr r3, [r7, #4] 800ec98: 629a str r2, [r3, #40] @ 0x28 /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 800ec9a: 4b40 ldr r3, [pc, #256] @ (800ed9c ) 800ec9c: 681c ldr r4, [r3, #0] 800ec9e: 2002 movs r0, #2 800eca0: f002 fde2 bl 8011868 800eca4: 4603 mov r3, r0 800eca6: fbb4 f3f3 udiv r3, r4, r3 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 800ecaa: 005b lsls r3, r3, #1 wait_loop_index = ((SystemCoreClock 800ecac: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800ecae: e002 b.n 800ecb6 { wait_loop_index--; 800ecb0: 68fb ldr r3, [r7, #12] 800ecb2: 3b01 subs r3, #1 800ecb4: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800ecb6: 68fb ldr r3, [r7, #12] 800ecb8: 2b00 cmp r3, #0 800ecba: d1f9 bne.n 800ecb0 } /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 800ecbc: 687b ldr r3, [r7, #4] 800ecbe: 681b ldr r3, [r3, #0] 800ecc0: 689a ldr r2, [r3, #8] 800ecc2: 687b ldr r3, [r7, #4] 800ecc4: 681b ldr r3, [r3, #0] 800ecc6: f042 0208 orr.w r2, r2, #8 800ecca: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800eccc: f7ff fb02 bl 800e2d4 800ecd0: 6138 str r0, [r7, #16] /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800ecd2: e01b b.n 800ed0c { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800ecd4: f7ff fafe bl 800e2d4 800ecd8: 4602 mov r2, r0 800ecda: 693b ldr r3, [r7, #16] 800ecdc: 1ad3 subs r3, r2, r3 800ecde: 2b0a cmp r3, #10 800ece0: d914 bls.n 800ed0c { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800ece2: 687b ldr r3, [r7, #4] 800ece4: 681b ldr r3, [r3, #0] 800ece6: 689b ldr r3, [r3, #8] 800ece8: f003 0308 and.w r3, r3, #8 800ecec: 2b00 cmp r3, #0 800ecee: d00d beq.n 800ed0c { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800ecf0: 687b ldr r3, [r7, #4] 800ecf2: 6a9b ldr r3, [r3, #40] @ 0x28 800ecf4: f023 0312 bic.w r3, r3, #18 800ecf8: f043 0210 orr.w r2, r3, #16 800ecfc: 687b ldr r3, [r7, #4] 800ecfe: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800ed00: 687b ldr r3, [r7, #4] 800ed02: 2200 movs r2, #0 800ed04: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ed08: 2301 movs r3, #1 800ed0a: e042 b.n 800ed92 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800ed0c: 687b ldr r3, [r7, #4] 800ed0e: 681b ldr r3, [r3, #0] 800ed10: 689b ldr r3, [r3, #8] 800ed12: f003 0308 and.w r3, r3, #8 800ed16: 2b00 cmp r3, #0 800ed18: d1dc bne.n 800ecd4 } } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 800ed1a: 687b ldr r3, [r7, #4] 800ed1c: 681b ldr r3, [r3, #0] 800ed1e: 689a ldr r2, [r3, #8] 800ed20: 687b ldr r3, [r7, #4] 800ed22: 681b ldr r3, [r3, #0] 800ed24: f042 0204 orr.w r2, r2, #4 800ed28: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800ed2a: f7ff fad3 bl 800e2d4 800ed2e: 6138 str r0, [r7, #16] /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800ed30: e01b b.n 800ed6a { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800ed32: f7ff facf bl 800e2d4 800ed36: 4602 mov r2, r0 800ed38: 693b ldr r3, [r7, #16] 800ed3a: 1ad3 subs r3, r2, r3 800ed3c: 2b0a cmp r3, #10 800ed3e: d914 bls.n 800ed6a { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800ed40: 687b ldr r3, [r7, #4] 800ed42: 681b ldr r3, [r3, #0] 800ed44: 689b ldr r3, [r3, #8] 800ed46: f003 0304 and.w r3, r3, #4 800ed4a: 2b00 cmp r3, #0 800ed4c: d00d beq.n 800ed6a { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800ed4e: 687b ldr r3, [r7, #4] 800ed50: 6a9b ldr r3, [r3, #40] @ 0x28 800ed52: f023 0312 bic.w r3, r3, #18 800ed56: f043 0210 orr.w r2, r3, #16 800ed5a: 687b ldr r3, [r7, #4] 800ed5c: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800ed5e: 687b ldr r3, [r7, #4] 800ed60: 2200 movs r2, #0 800ed62: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ed66: 2301 movs r3, #1 800ed68: e013 b.n 800ed92 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800ed6a: 687b ldr r3, [r7, #4] 800ed6c: 681b ldr r3, [r3, #0] 800ed6e: 689b ldr r3, [r3, #8] 800ed70: f003 0304 and.w r3, r3, #4 800ed74: 2b00 cmp r3, #0 800ed76: d1dc bne.n 800ed32 } } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800ed78: 687b ldr r3, [r7, #4] 800ed7a: 6a9b ldr r3, [r3, #40] @ 0x28 800ed7c: f023 0303 bic.w r3, r3, #3 800ed80: f043 0201 orr.w r2, r3, #1 800ed84: 687b ldr r3, [r7, #4] 800ed86: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 800ed88: 687b ldr r3, [r7, #4] 800ed8a: 2200 movs r2, #0 800ed8c: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800ed90: 7dfb ldrb r3, [r7, #23] } 800ed92: 4618 mov r0, r3 800ed94: 371c adds r7, #28 800ed96: 46bd mov sp, r7 800ed98: bd90 pop {r4, r7, pc} 800ed9a: bf00 nop 800ed9c: 20000084 .word 0x20000084 0800eda0 : * @brief Injected conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { 800eda0: b480 push {r7} 800eda2: b083 sub sp, #12 800eda4: af00 add r7, sp, #0 800eda6: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } 800eda8: bf00 nop 800edaa: 370c adds r7, #12 800edac: 46bd mov sp, r7 800edae: bc80 pop {r7} 800edb0: 4770 bx lr 0800edb2 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { 800edb2: b580 push {r7, lr} 800edb4: b084 sub sp, #16 800edb6: af00 add r7, sp, #0 800edb8: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) 800edba: 687b ldr r3, [r7, #4] 800edbc: 2b00 cmp r3, #0 800edbe: d101 bne.n 800edc4 { return HAL_ERROR; 800edc0: 2301 movs r3, #1 800edc2: e0ed b.n 800efa0 /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) 800edc4: 687b ldr r3, [r7, #4] 800edc6: f893 3020 ldrb.w r3, [r3, #32] 800edca: b2db uxtb r3, r3 800edcc: 2b00 cmp r3, #0 800edce: d102 bne.n 800edd6 { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); 800edd0: 6878 ldr r0, [r7, #4] 800edd2: f7fa ff21 bl 8009c18 } #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800edd6: 687b ldr r3, [r7, #4] 800edd8: 681b ldr r3, [r3, #0] 800edda: 681a ldr r2, [r3, #0] 800eddc: 687b ldr r3, [r7, #4] 800edde: 681b ldr r3, [r3, #0] 800ede0: f042 0201 orr.w r2, r2, #1 800ede4: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800ede6: f7ff fa75 bl 800e2d4 800edea: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800edec: e012 b.n 800ee14 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800edee: f7ff fa71 bl 800e2d4 800edf2: 4602 mov r2, r0 800edf4: 68fb ldr r3, [r7, #12] 800edf6: 1ad3 subs r3, r2, r3 800edf8: 2b0a cmp r3, #10 800edfa: d90b bls.n 800ee14 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800edfc: 687b ldr r3, [r7, #4] 800edfe: 6a5b ldr r3, [r3, #36] @ 0x24 800ee00: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800ee04: 687b ldr r3, [r7, #4] 800ee06: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800ee08: 687b ldr r3, [r7, #4] 800ee0a: 2205 movs r2, #5 800ee0c: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800ee10: 2301 movs r3, #1 800ee12: e0c5 b.n 800efa0 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800ee14: 687b ldr r3, [r7, #4] 800ee16: 681b ldr r3, [r3, #0] 800ee18: 685b ldr r3, [r3, #4] 800ee1a: f003 0301 and.w r3, r3, #1 800ee1e: 2b00 cmp r3, #0 800ee20: d0e5 beq.n 800edee } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800ee22: 687b ldr r3, [r7, #4] 800ee24: 681b ldr r3, [r3, #0] 800ee26: 681a ldr r2, [r3, #0] 800ee28: 687b ldr r3, [r7, #4] 800ee2a: 681b ldr r3, [r3, #0] 800ee2c: f022 0202 bic.w r2, r2, #2 800ee30: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800ee32: f7ff fa4f bl 800e2d4 800ee36: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800ee38: e012 b.n 800ee60 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800ee3a: f7ff fa4b bl 800e2d4 800ee3e: 4602 mov r2, r0 800ee40: 68fb ldr r3, [r7, #12] 800ee42: 1ad3 subs r3, r2, r3 800ee44: 2b0a cmp r3, #10 800ee46: d90b bls.n 800ee60 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800ee48: 687b ldr r3, [r7, #4] 800ee4a: 6a5b ldr r3, [r3, #36] @ 0x24 800ee4c: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800ee50: 687b ldr r3, [r7, #4] 800ee52: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800ee54: 687b ldr r3, [r7, #4] 800ee56: 2205 movs r2, #5 800ee58: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800ee5c: 2301 movs r3, #1 800ee5e: e09f b.n 800efa0 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800ee60: 687b ldr r3, [r7, #4] 800ee62: 681b ldr r3, [r3, #0] 800ee64: 685b ldr r3, [r3, #4] 800ee66: f003 0302 and.w r3, r3, #2 800ee6a: 2b00 cmp r3, #0 800ee6c: d1e5 bne.n 800ee3a } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) 800ee6e: 687b ldr r3, [r7, #4] 800ee70: 7e1b ldrb r3, [r3, #24] 800ee72: 2b01 cmp r3, #1 800ee74: d108 bne.n 800ee88 { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800ee76: 687b ldr r3, [r7, #4] 800ee78: 681b ldr r3, [r3, #0] 800ee7a: 681a ldr r2, [r3, #0] 800ee7c: 687b ldr r3, [r7, #4] 800ee7e: 681b ldr r3, [r3, #0] 800ee80: f042 0280 orr.w r2, r2, #128 @ 0x80 800ee84: 601a str r2, [r3, #0] 800ee86: e007 b.n 800ee98 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800ee88: 687b ldr r3, [r7, #4] 800ee8a: 681b ldr r3, [r3, #0] 800ee8c: 681a ldr r2, [r3, #0] 800ee8e: 687b ldr r3, [r7, #4] 800ee90: 681b ldr r3, [r3, #0] 800ee92: f022 0280 bic.w r2, r2, #128 @ 0x80 800ee96: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) 800ee98: 687b ldr r3, [r7, #4] 800ee9a: 7e5b ldrb r3, [r3, #25] 800ee9c: 2b01 cmp r3, #1 800ee9e: d108 bne.n 800eeb2 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800eea0: 687b ldr r3, [r7, #4] 800eea2: 681b ldr r3, [r3, #0] 800eea4: 681a ldr r2, [r3, #0] 800eea6: 687b ldr r3, [r7, #4] 800eea8: 681b ldr r3, [r3, #0] 800eeaa: f042 0240 orr.w r2, r2, #64 @ 0x40 800eeae: 601a str r2, [r3, #0] 800eeb0: e007 b.n 800eec2 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800eeb2: 687b ldr r3, [r7, #4] 800eeb4: 681b ldr r3, [r3, #0] 800eeb6: 681a ldr r2, [r3, #0] 800eeb8: 687b ldr r3, [r7, #4] 800eeba: 681b ldr r3, [r3, #0] 800eebc: f022 0240 bic.w r2, r2, #64 @ 0x40 800eec0: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) 800eec2: 687b ldr r3, [r7, #4] 800eec4: 7e9b ldrb r3, [r3, #26] 800eec6: 2b01 cmp r3, #1 800eec8: d108 bne.n 800eedc { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800eeca: 687b ldr r3, [r7, #4] 800eecc: 681b ldr r3, [r3, #0] 800eece: 681a ldr r2, [r3, #0] 800eed0: 687b ldr r3, [r7, #4] 800eed2: 681b ldr r3, [r3, #0] 800eed4: f042 0220 orr.w r2, r2, #32 800eed8: 601a str r2, [r3, #0] 800eeda: e007 b.n 800eeec } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800eedc: 687b ldr r3, [r7, #4] 800eede: 681b ldr r3, [r3, #0] 800eee0: 681a ldr r2, [r3, #0] 800eee2: 687b ldr r3, [r7, #4] 800eee4: 681b ldr r3, [r3, #0] 800eee6: f022 0220 bic.w r2, r2, #32 800eeea: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) 800eeec: 687b ldr r3, [r7, #4] 800eeee: 7edb ldrb r3, [r3, #27] 800eef0: 2b01 cmp r3, #1 800eef2: d108 bne.n 800ef06 { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800eef4: 687b ldr r3, [r7, #4] 800eef6: 681b ldr r3, [r3, #0] 800eef8: 681a ldr r2, [r3, #0] 800eefa: 687b ldr r3, [r7, #4] 800eefc: 681b ldr r3, [r3, #0] 800eefe: f022 0210 bic.w r2, r2, #16 800ef02: 601a str r2, [r3, #0] 800ef04: e007 b.n 800ef16 } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800ef06: 687b ldr r3, [r7, #4] 800ef08: 681b ldr r3, [r3, #0] 800ef0a: 681a ldr r2, [r3, #0] 800ef0c: 687b ldr r3, [r7, #4] 800ef0e: 681b ldr r3, [r3, #0] 800ef10: f042 0210 orr.w r2, r2, #16 800ef14: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) 800ef16: 687b ldr r3, [r7, #4] 800ef18: 7f1b ldrb r3, [r3, #28] 800ef1a: 2b01 cmp r3, #1 800ef1c: d108 bne.n 800ef30 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800ef1e: 687b ldr r3, [r7, #4] 800ef20: 681b ldr r3, [r3, #0] 800ef22: 681a ldr r2, [r3, #0] 800ef24: 687b ldr r3, [r7, #4] 800ef26: 681b ldr r3, [r3, #0] 800ef28: f042 0208 orr.w r2, r2, #8 800ef2c: 601a str r2, [r3, #0] 800ef2e: e007 b.n 800ef40 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800ef30: 687b ldr r3, [r7, #4] 800ef32: 681b ldr r3, [r3, #0] 800ef34: 681a ldr r2, [r3, #0] 800ef36: 687b ldr r3, [r7, #4] 800ef38: 681b ldr r3, [r3, #0] 800ef3a: f022 0208 bic.w r2, r2, #8 800ef3e: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) 800ef40: 687b ldr r3, [r7, #4] 800ef42: 7f5b ldrb r3, [r3, #29] 800ef44: 2b01 cmp r3, #1 800ef46: d108 bne.n 800ef5a { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800ef48: 687b ldr r3, [r7, #4] 800ef4a: 681b ldr r3, [r3, #0] 800ef4c: 681a ldr r2, [r3, #0] 800ef4e: 687b ldr r3, [r7, #4] 800ef50: 681b ldr r3, [r3, #0] 800ef52: f042 0204 orr.w r2, r2, #4 800ef56: 601a str r2, [r3, #0] 800ef58: e007 b.n 800ef6a } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800ef5a: 687b ldr r3, [r7, #4] 800ef5c: 681b ldr r3, [r3, #0] 800ef5e: 681a ldr r2, [r3, #0] 800ef60: 687b ldr r3, [r7, #4] 800ef62: 681b ldr r3, [r3, #0] 800ef64: f022 0204 bic.w r2, r2, #4 800ef68: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | 800ef6a: 687b ldr r3, [r7, #4] 800ef6c: 689a ldr r2, [r3, #8] 800ef6e: 687b ldr r3, [r7, #4] 800ef70: 68db ldr r3, [r3, #12] 800ef72: 431a orrs r2, r3 800ef74: 687b ldr r3, [r7, #4] 800ef76: 691b ldr r3, [r3, #16] 800ef78: 431a orrs r2, r3 800ef7a: 687b ldr r3, [r7, #4] 800ef7c: 695b ldr r3, [r3, #20] 800ef7e: ea42 0103 orr.w r1, r2, r3 800ef82: 687b ldr r3, [r7, #4] 800ef84: 685b ldr r3, [r3, #4] 800ef86: 1e5a subs r2, r3, #1 800ef88: 687b ldr r3, [r7, #4] 800ef8a: 681b ldr r3, [r3, #0] 800ef8c: 430a orrs r2, r1 800ef8e: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800ef90: 687b ldr r3, [r7, #4] 800ef92: 2200 movs r2, #0 800ef94: 625a str r2, [r3, #36] @ 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; 800ef96: 687b ldr r3, [r7, #4] 800ef98: 2201 movs r2, #1 800ef9a: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800ef9e: 2300 movs r3, #0 } 800efa0: 4618 mov r0, r3 800efa2: 3710 adds r7, #16 800efa4: 46bd mov sp, r7 800efa6: bd80 pop {r7, pc} 0800efa8 : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { 800efa8: b480 push {r7} 800efaa: b087 sub sp, #28 800efac: af00 add r7, sp, #0 800efae: 6078 str r0, [r7, #4] 800efb0: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; 800efb2: 687b ldr r3, [r7, #4] 800efb4: 681b ldr r3, [r3, #0] 800efb6: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; 800efb8: 687b ldr r3, [r7, #4] 800efba: f893 3020 ldrb.w r3, [r3, #32] 800efbe: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || 800efc0: 7cfb ldrb r3, [r7, #19] 800efc2: 2b01 cmp r3, #1 800efc4: d003 beq.n 800efce 800efc6: 7cfb ldrb r3, [r7, #19] 800efc8: 2b02 cmp r3, #2 800efca: f040 80be bne.w 800f14a assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); #if defined(CAN2) /* CAN1 and CAN2 are dual instances with 28 common filters banks */ /* Select master instance to access the filter banks */ can_ip = CAN1; 800efce: 4b65 ldr r3, [pc, #404] @ (800f164 ) 800efd0: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); #endif /* CAN3 */ /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); 800efd2: 697b ldr r3, [r7, #20] 800efd4: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800efd8: f043 0201 orr.w r2, r3, #1 800efdc: 697b ldr r3, [r7, #20] 800efde: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #if defined(CAN2) /* Select the start filter number of CAN2 slave instance */ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); 800efe2: 697b ldr r3, [r7, #20] 800efe4: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800efe8: f423 527c bic.w r2, r3, #16128 @ 0x3f00 800efec: 697b ldr r3, [r7, #20] 800efee: f8c3 2200 str.w r2, [r3, #512] @ 0x200 SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); 800eff2: 697b ldr r3, [r7, #20] 800eff4: f8d3 2200 ldr.w r2, [r3, #512] @ 0x200 800eff8: 683b ldr r3, [r7, #0] 800effa: 6a5b ldr r3, [r3, #36] @ 0x24 800effc: 021b lsls r3, r3, #8 800effe: 431a orrs r2, r3 800f000: 697b ldr r3, [r7, #20] 800f002: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #endif /* CAN3 */ /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); 800f006: 683b ldr r3, [r7, #0] 800f008: 695b ldr r3, [r3, #20] 800f00a: f003 031f and.w r3, r3, #31 800f00e: 2201 movs r2, #1 800f010: fa02 f303 lsl.w r3, r2, r3 800f014: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); 800f016: 697b ldr r3, [r7, #20] 800f018: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800f01c: 68fb ldr r3, [r7, #12] 800f01e: 43db mvns r3, r3 800f020: 401a ands r2, r3 800f022: 697b ldr r3, [r7, #20] 800f024: f8c3 221c str.w r2, [r3, #540] @ 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) 800f028: 683b ldr r3, [r7, #0] 800f02a: 69db ldr r3, [r3, #28] 800f02c: 2b00 cmp r3, #0 800f02e: d123 bne.n 800f078 { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); 800f030: 697b ldr r3, [r7, #20] 800f032: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800f036: 68fb ldr r3, [r7, #12] 800f038: 43db mvns r3, r3 800f03a: 401a ands r2, r3 800f03c: 697b ldr r3, [r7, #20] 800f03e: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800f042: 683b ldr r3, [r7, #0] 800f044: 68db ldr r3, [r3, #12] 800f046: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800f048: 683b ldr r3, [r7, #0] 800f04a: 685b ldr r3, [r3, #4] 800f04c: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800f04e: 683a ldr r2, [r7, #0] 800f050: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800f052: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800f054: 697b ldr r3, [r7, #20] 800f056: 3248 adds r2, #72 @ 0x48 800f058: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800f05c: 683b ldr r3, [r7, #0] 800f05e: 689b ldr r3, [r3, #8] 800f060: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); 800f062: 683b ldr r3, [r7, #0] 800f064: 681b ldr r3, [r3, #0] 800f066: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800f068: 683b ldr r3, [r7, #0] 800f06a: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800f06c: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800f06e: 6979 ldr r1, [r7, #20] 800f070: 3348 adds r3, #72 @ 0x48 800f072: 00db lsls r3, r3, #3 800f074: 440b add r3, r1 800f076: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) 800f078: 683b ldr r3, [r7, #0] 800f07a: 69db ldr r3, [r3, #28] 800f07c: 2b01 cmp r3, #1 800f07e: d122 bne.n 800f0c6 { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); 800f080: 697b ldr r3, [r7, #20] 800f082: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800f086: 68fb ldr r3, [r7, #12] 800f088: 431a orrs r2, r3 800f08a: 697b ldr r3, [r7, #20] 800f08c: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800f090: 683b ldr r3, [r7, #0] 800f092: 681b ldr r3, [r3, #0] 800f094: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800f096: 683b ldr r3, [r7, #0] 800f098: 685b ldr r3, [r3, #4] 800f09a: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800f09c: 683a ldr r2, [r7, #0] 800f09e: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800f0a0: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800f0a2: 697b ldr r3, [r7, #20] 800f0a4: 3248 adds r2, #72 @ 0x48 800f0a6: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800f0aa: 683b ldr r3, [r7, #0] 800f0ac: 689b ldr r3, [r3, #8] 800f0ae: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); 800f0b0: 683b ldr r3, [r7, #0] 800f0b2: 68db ldr r3, [r3, #12] 800f0b4: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800f0b6: 683b ldr r3, [r7, #0] 800f0b8: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800f0ba: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800f0bc: 6979 ldr r1, [r7, #20] 800f0be: 3348 adds r3, #72 @ 0x48 800f0c0: 00db lsls r3, r3, #3 800f0c2: 440b add r3, r1 800f0c4: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) 800f0c6: 683b ldr r3, [r7, #0] 800f0c8: 699b ldr r3, [r3, #24] 800f0ca: 2b00 cmp r3, #0 800f0cc: d109 bne.n 800f0e2 { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); 800f0ce: 697b ldr r3, [r7, #20] 800f0d0: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800f0d4: 68fb ldr r3, [r7, #12] 800f0d6: 43db mvns r3, r3 800f0d8: 401a ands r2, r3 800f0da: 697b ldr r3, [r7, #20] 800f0dc: f8c3 2204 str.w r2, [r3, #516] @ 0x204 800f0e0: e007 b.n 800f0f2 } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); 800f0e2: 697b ldr r3, [r7, #20] 800f0e4: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800f0e8: 68fb ldr r3, [r7, #12] 800f0ea: 431a orrs r2, r3 800f0ec: 697b ldr r3, [r7, #20] 800f0ee: f8c3 2204 str.w r2, [r3, #516] @ 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) 800f0f2: 683b ldr r3, [r7, #0] 800f0f4: 691b ldr r3, [r3, #16] 800f0f6: 2b00 cmp r3, #0 800f0f8: d109 bne.n 800f10e { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); 800f0fa: 697b ldr r3, [r7, #20] 800f0fc: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800f100: 68fb ldr r3, [r7, #12] 800f102: 43db mvns r3, r3 800f104: 401a ands r2, r3 800f106: 697b ldr r3, [r7, #20] 800f108: f8c3 2214 str.w r2, [r3, #532] @ 0x214 800f10c: e007 b.n 800f11e } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); 800f10e: 697b ldr r3, [r7, #20] 800f110: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800f114: 68fb ldr r3, [r7, #12] 800f116: 431a orrs r2, r3 800f118: 697b ldr r3, [r7, #20] 800f11a: f8c3 2214 str.w r2, [r3, #532] @ 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) 800f11e: 683b ldr r3, [r7, #0] 800f120: 6a1b ldr r3, [r3, #32] 800f122: 2b01 cmp r3, #1 800f124: d107 bne.n 800f136 { SET_BIT(can_ip->FA1R, filternbrbitpos); 800f126: 697b ldr r3, [r7, #20] 800f128: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800f12c: 68fb ldr r3, [r7, #12] 800f12e: 431a orrs r2, r3 800f130: 697b ldr r3, [r7, #20] 800f132: f8c3 221c str.w r2, [r3, #540] @ 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); 800f136: 697b ldr r3, [r7, #20] 800f138: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800f13c: f023 0201 bic.w r2, r3, #1 800f140: 697b ldr r3, [r7, #20] 800f142: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Return function status */ return HAL_OK; 800f146: 2300 movs r3, #0 800f148: e006 b.n 800f158 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f14a: 687b ldr r3, [r7, #4] 800f14c: 6a5b ldr r3, [r3, #36] @ 0x24 800f14e: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f152: 687b ldr r3, [r7, #4] 800f154: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f156: 2301 movs r3, #1 } } 800f158: 4618 mov r0, r3 800f15a: 371c adds r7, #28 800f15c: 46bd mov sp, r7 800f15e: bc80 pop {r7} 800f160: 4770 bx lr 800f162: bf00 nop 800f164: 40006400 .word 0x40006400 0800f168 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { 800f168: b580 push {r7, lr} 800f16a: b084 sub sp, #16 800f16c: af00 add r7, sp, #0 800f16e: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) 800f170: 687b ldr r3, [r7, #4] 800f172: f893 3020 ldrb.w r3, [r3, #32] 800f176: b2db uxtb r3, r3 800f178: 2b01 cmp r3, #1 800f17a: d12e bne.n 800f1da { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; 800f17c: 687b ldr r3, [r7, #4] 800f17e: 2202 movs r2, #2 800f180: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800f184: 687b ldr r3, [r7, #4] 800f186: 681b ldr r3, [r3, #0] 800f188: 681a ldr r2, [r3, #0] 800f18a: 687b ldr r3, [r7, #4] 800f18c: 681b ldr r3, [r3, #0] 800f18e: f022 0201 bic.w r2, r2, #1 800f192: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800f194: f7ff f89e bl 800e2d4 800f198: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800f19a: e012 b.n 800f1c2 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800f19c: f7ff f89a bl 800e2d4 800f1a0: 4602 mov r2, r0 800f1a2: 68fb ldr r3, [r7, #12] 800f1a4: 1ad3 subs r3, r2, r3 800f1a6: 2b0a cmp r3, #10 800f1a8: d90b bls.n 800f1c2 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800f1aa: 687b ldr r3, [r7, #4] 800f1ac: 6a5b ldr r3, [r3, #36] @ 0x24 800f1ae: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800f1b2: 687b ldr r3, [r7, #4] 800f1b4: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800f1b6: 687b ldr r3, [r7, #4] 800f1b8: 2205 movs r2, #5 800f1ba: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800f1be: 2301 movs r3, #1 800f1c0: e012 b.n 800f1e8 while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800f1c2: 687b ldr r3, [r7, #4] 800f1c4: 681b ldr r3, [r3, #0] 800f1c6: 685b ldr r3, [r3, #4] 800f1c8: f003 0301 and.w r3, r3, #1 800f1cc: 2b00 cmp r3, #0 800f1ce: d1e5 bne.n 800f19c } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800f1d0: 687b ldr r3, [r7, #4] 800f1d2: 2200 movs r2, #0 800f1d4: 625a str r2, [r3, #36] @ 0x24 /* Return function status */ return HAL_OK; 800f1d6: 2300 movs r3, #0 800f1d8: e006 b.n 800f1e8 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; 800f1da: 687b ldr r3, [r7, #4] 800f1dc: 6a5b ldr r3, [r3, #36] @ 0x24 800f1de: f443 2200 orr.w r2, r3, #524288 @ 0x80000 800f1e2: 687b ldr r3, [r7, #4] 800f1e4: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f1e6: 2301 movs r3, #1 } } 800f1e8: 4618 mov r0, r3 800f1ea: 3710 adds r7, #16 800f1ec: 46bd mov sp, r7 800f1ee: bd80 pop {r7, pc} 0800f1f0 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { 800f1f0: b580 push {r7, lr} 800f1f2: b084 sub sp, #16 800f1f4: af00 add r7, sp, #0 800f1f6: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_LISTENING) 800f1f8: 687b ldr r3, [r7, #4] 800f1fa: f893 3020 ldrb.w r3, [r3, #32] 800f1fe: b2db uxtb r3, r3 800f200: 2b02 cmp r3, #2 800f202: d133 bne.n 800f26c { /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800f204: 687b ldr r3, [r7, #4] 800f206: 681b ldr r3, [r3, #0] 800f208: 681a ldr r2, [r3, #0] 800f20a: 687b ldr r3, [r7, #4] 800f20c: 681b ldr r3, [r3, #0] 800f20e: f042 0201 orr.w r2, r2, #1 800f212: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800f214: f7ff f85e bl 800e2d4 800f218: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800f21a: e012 b.n 800f242 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800f21c: f7ff f85a bl 800e2d4 800f220: 4602 mov r2, r0 800f222: 68fb ldr r3, [r7, #12] 800f224: 1ad3 subs r3, r2, r3 800f226: 2b0a cmp r3, #10 800f228: d90b bls.n 800f242 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800f22a: 687b ldr r3, [r7, #4] 800f22c: 6a5b ldr r3, [r3, #36] @ 0x24 800f22e: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800f232: 687b ldr r3, [r7, #4] 800f234: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800f236: 687b ldr r3, [r7, #4] 800f238: 2205 movs r2, #5 800f23a: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800f23e: 2301 movs r3, #1 800f240: e01b b.n 800f27a while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800f242: 687b ldr r3, [r7, #4] 800f244: 681b ldr r3, [r3, #0] 800f246: 685b ldr r3, [r3, #4] 800f248: f003 0301 and.w r3, r3, #1 800f24c: 2b00 cmp r3, #0 800f24e: d0e5 beq.n 800f21c } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800f250: 687b ldr r3, [r7, #4] 800f252: 681b ldr r3, [r3, #0] 800f254: 681a ldr r2, [r3, #0] 800f256: 687b ldr r3, [r7, #4] 800f258: 681b ldr r3, [r3, #0] 800f25a: f022 0202 bic.w r2, r2, #2 800f25e: 601a str r2, [r3, #0] /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_READY; 800f260: 687b ldr r3, [r7, #4] 800f262: 2201 movs r2, #1 800f264: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800f268: 2300 movs r3, #0 800f26a: e006 b.n 800f27a } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; 800f26c: 687b ldr r3, [r7, #4] 800f26e: 6a5b ldr r3, [r3, #36] @ 0x24 800f270: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800f274: 687b ldr r3, [r7, #4] 800f276: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f278: 2301 movs r3, #1 } } 800f27a: 4618 mov r0, r3 800f27c: 3710 adds r7, #16 800f27e: 46bd mov sp, r7 800f280: bd80 pop {r7, pc} 0800f282 : * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, const uint8_t aData[], uint32_t *pTxMailbox) { 800f282: b480 push {r7} 800f284: b089 sub sp, #36 @ 0x24 800f286: af00 add r7, sp, #0 800f288: 60f8 str r0, [r7, #12] 800f28a: 60b9 str r1, [r7, #8] 800f28c: 607a str r2, [r7, #4] 800f28e: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; 800f290: 68fb ldr r3, [r7, #12] 800f292: f893 3020 ldrb.w r3, [r3, #32] 800f296: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); 800f298: 68fb ldr r3, [r7, #12] 800f29a: 681b ldr r3, [r3, #0] 800f29c: 689b ldr r3, [r3, #8] 800f29e: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || 800f2a0: 7ffb ldrb r3, [r7, #31] 800f2a2: 2b01 cmp r3, #1 800f2a4: d003 beq.n 800f2ae 800f2a6: 7ffb ldrb r3, [r7, #31] 800f2a8: 2b02 cmp r3, #2 800f2aa: f040 80ad bne.w 800f408 (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || 800f2ae: 69bb ldr r3, [r7, #24] 800f2b0: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800f2b4: 2b00 cmp r3, #0 800f2b6: d10a bne.n 800f2ce ((tsr & CAN_TSR_TME1) != 0U) || 800f2b8: 69bb ldr r3, [r7, #24] 800f2ba: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || 800f2be: 2b00 cmp r3, #0 800f2c0: d105 bne.n 800f2ce ((tsr & CAN_TSR_TME2) != 0U)) 800f2c2: 69bb ldr r3, [r7, #24] 800f2c4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || 800f2c8: 2b00 cmp r3, #0 800f2ca: f000 8095 beq.w 800f3f8 { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; 800f2ce: 69bb ldr r3, [r7, #24] 800f2d0: 0e1b lsrs r3, r3, #24 800f2d2: f003 0303 and.w r3, r3, #3 800f2d6: 617b str r3, [r7, #20] /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; 800f2d8: 2201 movs r2, #1 800f2da: 697b ldr r3, [r7, #20] 800f2dc: 409a lsls r2, r3 800f2de: 683b ldr r3, [r7, #0] 800f2e0: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) 800f2e2: 68bb ldr r3, [r7, #8] 800f2e4: 689b ldr r3, [r3, #8] 800f2e6: 2b00 cmp r3, #0 800f2e8: d10d bne.n 800f306 { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800f2ea: 68bb ldr r3, [r7, #8] 800f2ec: 681b ldr r3, [r3, #0] 800f2ee: 055a lsls r2, r3, #21 pHeader->RTR); 800f2f0: 68bb ldr r3, [r7, #8] 800f2f2: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800f2f4: 68f9 ldr r1, [r7, #12] 800f2f6: 6809 ldr r1, [r1, #0] 800f2f8: 431a orrs r2, r3 800f2fa: 697b ldr r3, [r7, #20] 800f2fc: 3318 adds r3, #24 800f2fe: 011b lsls r3, r3, #4 800f300: 440b add r3, r1 800f302: 601a str r2, [r3, #0] 800f304: e00f b.n 800f326 } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f306: 68bb ldr r3, [r7, #8] 800f308: 685b ldr r3, [r3, #4] 800f30a: 00da lsls r2, r3, #3 pHeader->IDE | 800f30c: 68bb ldr r3, [r7, #8] 800f30e: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f310: 431a orrs r2, r3 pHeader->RTR); 800f312: 68bb ldr r3, [r7, #8] 800f314: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f316: 68f9 ldr r1, [r7, #12] 800f318: 6809 ldr r1, [r1, #0] pHeader->IDE | 800f31a: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f31c: 697b ldr r3, [r7, #20] 800f31e: 3318 adds r3, #24 800f320: 011b lsls r3, r3, #4 800f322: 440b add r3, r1 800f324: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); 800f326: 68fb ldr r3, [r7, #12] 800f328: 6819 ldr r1, [r3, #0] 800f32a: 68bb ldr r3, [r7, #8] 800f32c: 691a ldr r2, [r3, #16] 800f32e: 697b ldr r3, [r7, #20] 800f330: 3318 adds r3, #24 800f332: 011b lsls r3, r3, #4 800f334: 440b add r3, r1 800f336: 3304 adds r3, #4 800f338: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) 800f33a: 68bb ldr r3, [r7, #8] 800f33c: 7d1b ldrb r3, [r3, #20] 800f33e: 2b01 cmp r3, #1 800f340: d111 bne.n 800f366 { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); 800f342: 68fb ldr r3, [r7, #12] 800f344: 681a ldr r2, [r3, #0] 800f346: 697b ldr r3, [r7, #20] 800f348: 3318 adds r3, #24 800f34a: 011b lsls r3, r3, #4 800f34c: 4413 add r3, r2 800f34e: 3304 adds r3, #4 800f350: 681b ldr r3, [r3, #0] 800f352: 68fa ldr r2, [r7, #12] 800f354: 6811 ldr r1, [r2, #0] 800f356: f443 7280 orr.w r2, r3, #256 @ 0x100 800f35a: 697b ldr r3, [r7, #20] 800f35c: 3318 adds r3, #24 800f35e: 011b lsls r3, r3, #4 800f360: 440b add r3, r1 800f362: 3304 adds r3, #4 800f364: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, 800f366: 687b ldr r3, [r7, #4] 800f368: 3307 adds r3, #7 800f36a: 781b ldrb r3, [r3, #0] 800f36c: 061a lsls r2, r3, #24 800f36e: 687b ldr r3, [r7, #4] 800f370: 3306 adds r3, #6 800f372: 781b ldrb r3, [r3, #0] 800f374: 041b lsls r3, r3, #16 800f376: 431a orrs r2, r3 800f378: 687b ldr r3, [r7, #4] 800f37a: 3305 adds r3, #5 800f37c: 781b ldrb r3, [r3, #0] 800f37e: 021b lsls r3, r3, #8 800f380: 4313 orrs r3, r2 800f382: 687a ldr r2, [r7, #4] 800f384: 3204 adds r2, #4 800f386: 7812 ldrb r2, [r2, #0] 800f388: 4610 mov r0, r2 800f38a: 68fa ldr r2, [r7, #12] 800f38c: 6811 ldr r1, [r2, #0] 800f38e: ea43 0200 orr.w r2, r3, r0 800f392: 697b ldr r3, [r7, #20] 800f394: 011b lsls r3, r3, #4 800f396: 440b add r3, r1 800f398: f503 73c6 add.w r3, r3, #396 @ 0x18c 800f39c: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, 800f39e: 687b ldr r3, [r7, #4] 800f3a0: 3303 adds r3, #3 800f3a2: 781b ldrb r3, [r3, #0] 800f3a4: 061a lsls r2, r3, #24 800f3a6: 687b ldr r3, [r7, #4] 800f3a8: 3302 adds r3, #2 800f3aa: 781b ldrb r3, [r3, #0] 800f3ac: 041b lsls r3, r3, #16 800f3ae: 431a orrs r2, r3 800f3b0: 687b ldr r3, [r7, #4] 800f3b2: 3301 adds r3, #1 800f3b4: 781b ldrb r3, [r3, #0] 800f3b6: 021b lsls r3, r3, #8 800f3b8: 4313 orrs r3, r2 800f3ba: 687a ldr r2, [r7, #4] 800f3bc: 7812 ldrb r2, [r2, #0] 800f3be: 4610 mov r0, r2 800f3c0: 68fa ldr r2, [r7, #12] 800f3c2: 6811 ldr r1, [r2, #0] 800f3c4: ea43 0200 orr.w r2, r3, r0 800f3c8: 697b ldr r3, [r7, #20] 800f3ca: 011b lsls r3, r3, #4 800f3cc: 440b add r3, r1 800f3ce: f503 73c4 add.w r3, r3, #392 @ 0x188 800f3d2: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); 800f3d4: 68fb ldr r3, [r7, #12] 800f3d6: 681a ldr r2, [r3, #0] 800f3d8: 697b ldr r3, [r7, #20] 800f3da: 3318 adds r3, #24 800f3dc: 011b lsls r3, r3, #4 800f3de: 4413 add r3, r2 800f3e0: 681b ldr r3, [r3, #0] 800f3e2: 68fa ldr r2, [r7, #12] 800f3e4: 6811 ldr r1, [r2, #0] 800f3e6: f043 0201 orr.w r2, r3, #1 800f3ea: 697b ldr r3, [r7, #20] 800f3ec: 3318 adds r3, #24 800f3ee: 011b lsls r3, r3, #4 800f3f0: 440b add r3, r1 800f3f2: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800f3f4: 2300 movs r3, #0 800f3f6: e00e b.n 800f416 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800f3f8: 68fb ldr r3, [r7, #12] 800f3fa: 6a5b ldr r3, [r3, #36] @ 0x24 800f3fc: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800f400: 68fb ldr r3, [r7, #12] 800f402: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f404: 2301 movs r3, #1 800f406: e006 b.n 800f416 } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f408: 68fb ldr r3, [r7, #12] 800f40a: 6a5b ldr r3, [r3, #36] @ 0x24 800f40c: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f410: 68fb ldr r3, [r7, #12] 800f412: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f414: 2301 movs r3, #1 } } 800f416: 4618 mov r0, r3 800f418: 3724 adds r7, #36 @ 0x24 800f41a: 46bd mov sp, r7 800f41c: bc80 pop {r7} 800f41e: 4770 bx lr 0800f420 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval Number of free Tx Mailboxes. */ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) { 800f420: b480 push {r7} 800f422: b085 sub sp, #20 800f424: af00 add r7, sp, #0 800f426: 6078 str r0, [r7, #4] uint32_t freelevel = 0U; 800f428: 2300 movs r3, #0 800f42a: 60fb str r3, [r7, #12] HAL_CAN_StateTypeDef state = hcan->State; 800f42c: 687b ldr r3, [r7, #4] 800f42e: f893 3020 ldrb.w r3, [r3, #32] 800f432: 72fb strb r3, [r7, #11] if ((state == HAL_CAN_STATE_READY) || 800f434: 7afb ldrb r3, [r7, #11] 800f436: 2b01 cmp r3, #1 800f438: d002 beq.n 800f440 800f43a: 7afb ldrb r3, [r7, #11] 800f43c: 2b02 cmp r3, #2 800f43e: d11d bne.n 800f47c (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 status */ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) 800f440: 687b ldr r3, [r7, #4] 800f442: 681b ldr r3, [r3, #0] 800f444: 689b ldr r3, [r3, #8] 800f446: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800f44a: 2b00 cmp r3, #0 800f44c: d002 beq.n 800f454 { freelevel++; 800f44e: 68fb ldr r3, [r7, #12] 800f450: 3301 adds r3, #1 800f452: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 1 status */ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) 800f454: 687b ldr r3, [r7, #4] 800f456: 681b ldr r3, [r3, #0] 800f458: 689b ldr r3, [r3, #8] 800f45a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800f45e: 2b00 cmp r3, #0 800f460: d002 beq.n 800f468 { freelevel++; 800f462: 68fb ldr r3, [r7, #12] 800f464: 3301 adds r3, #1 800f466: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 2 status */ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) 800f468: 687b ldr r3, [r7, #4] 800f46a: 681b ldr r3, [r3, #0] 800f46c: 689b ldr r3, [r3, #8] 800f46e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800f472: 2b00 cmp r3, #0 800f474: d002 beq.n 800f47c { freelevel++; 800f476: 68fb ldr r3, [r7, #12] 800f478: 3301 adds r3, #1 800f47a: 60fb str r3, [r7, #12] } } /* Return Tx Mailboxes free level */ return freelevel; 800f47c: 68fb ldr r3, [r7, #12] } 800f47e: 4618 mov r0, r3 800f480: 3714 adds r7, #20 800f482: 46bd mov sp, r7 800f484: bc80 pop {r7} 800f486: 4770 bx lr 0800f488 : * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { 800f488: b480 push {r7} 800f48a: b087 sub sp, #28 800f48c: af00 add r7, sp, #0 800f48e: 60f8 str r0, [r7, #12] 800f490: 60b9 str r1, [r7, #8] 800f492: 607a str r2, [r7, #4] 800f494: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800f496: 68fb ldr r3, [r7, #12] 800f498: f893 3020 ldrb.w r3, [r3, #32] 800f49c: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || 800f49e: 7dfb ldrb r3, [r7, #23] 800f4a0: 2b01 cmp r3, #1 800f4a2: d003 beq.n 800f4ac 800f4a4: 7dfb ldrb r3, [r7, #23] 800f4a6: 2b02 cmp r3, #2 800f4a8: f040 8103 bne.w 800f6b2 (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800f4ac: 68bb ldr r3, [r7, #8] 800f4ae: 2b00 cmp r3, #0 800f4b0: d10e bne.n 800f4d0 { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) 800f4b2: 68fb ldr r3, [r7, #12] 800f4b4: 681b ldr r3, [r3, #0] 800f4b6: 68db ldr r3, [r3, #12] 800f4b8: f003 0303 and.w r3, r3, #3 800f4bc: 2b00 cmp r3, #0 800f4be: d116 bne.n 800f4ee { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800f4c0: 68fb ldr r3, [r7, #12] 800f4c2: 6a5b ldr r3, [r3, #36] @ 0x24 800f4c4: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800f4c8: 68fb ldr r3, [r7, #12] 800f4ca: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f4cc: 2301 movs r3, #1 800f4ce: e0f7 b.n 800f6c0 } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) 800f4d0: 68fb ldr r3, [r7, #12] 800f4d2: 681b ldr r3, [r3, #0] 800f4d4: 691b ldr r3, [r3, #16] 800f4d6: f003 0303 and.w r3, r3, #3 800f4da: 2b00 cmp r3, #0 800f4dc: d107 bne.n 800f4ee { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800f4de: 68fb ldr r3, [r7, #12] 800f4e0: 6a5b ldr r3, [r3, #36] @ 0x24 800f4e2: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800f4e6: 68fb ldr r3, [r7, #12] 800f4e8: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f4ea: 2301 movs r3, #1 800f4ec: e0e8 b.n 800f6c0 } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; 800f4ee: 68fb ldr r3, [r7, #12] 800f4f0: 681a ldr r2, [r3, #0] 800f4f2: 68bb ldr r3, [r7, #8] 800f4f4: 331b adds r3, #27 800f4f6: 011b lsls r3, r3, #4 800f4f8: 4413 add r3, r2 800f4fa: 681b ldr r3, [r3, #0] 800f4fc: f003 0204 and.w r2, r3, #4 800f500: 687b ldr r3, [r7, #4] 800f502: 609a str r2, [r3, #8] if (pHeader->IDE == CAN_ID_STD) 800f504: 687b ldr r3, [r7, #4] 800f506: 689b ldr r3, [r3, #8] 800f508: 2b00 cmp r3, #0 800f50a: d10c bne.n 800f526 { pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; 800f50c: 68fb ldr r3, [r7, #12] 800f50e: 681a ldr r2, [r3, #0] 800f510: 68bb ldr r3, [r7, #8] 800f512: 331b adds r3, #27 800f514: 011b lsls r3, r3, #4 800f516: 4413 add r3, r2 800f518: 681b ldr r3, [r3, #0] 800f51a: 0d5b lsrs r3, r3, #21 800f51c: f3c3 020a ubfx r2, r3, #0, #11 800f520: 687b ldr r3, [r7, #4] 800f522: 601a str r2, [r3, #0] 800f524: e00b b.n 800f53e } else { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; 800f526: 68fb ldr r3, [r7, #12] 800f528: 681a ldr r2, [r3, #0] 800f52a: 68bb ldr r3, [r7, #8] 800f52c: 331b adds r3, #27 800f52e: 011b lsls r3, r3, #4 800f530: 4413 add r3, r2 800f532: 681b ldr r3, [r3, #0] 800f534: 08db lsrs r3, r3, #3 800f536: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & 800f53a: 687b ldr r3, [r7, #4] 800f53c: 605a str r2, [r3, #4] } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); 800f53e: 68fb ldr r3, [r7, #12] 800f540: 681a ldr r2, [r3, #0] 800f542: 68bb ldr r3, [r7, #8] 800f544: 331b adds r3, #27 800f546: 011b lsls r3, r3, #4 800f548: 4413 add r3, r2 800f54a: 681b ldr r3, [r3, #0] 800f54c: f003 0202 and.w r2, r3, #2 800f550: 687b ldr r3, [r7, #4] 800f552: 60da str r2, [r3, #12] if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) 800f554: 68fb ldr r3, [r7, #12] 800f556: 681a ldr r2, [r3, #0] 800f558: 68bb ldr r3, [r7, #8] 800f55a: 331b adds r3, #27 800f55c: 011b lsls r3, r3, #4 800f55e: 4413 add r3, r2 800f560: 3304 adds r3, #4 800f562: 681b ldr r3, [r3, #0] 800f564: f003 0308 and.w r3, r3, #8 800f568: 2b00 cmp r3, #0 800f56a: d003 beq.n 800f574 { /* Truncate DLC to 8 if received field is over range */ pHeader->DLC = 8U; 800f56c: 687b ldr r3, [r7, #4] 800f56e: 2208 movs r2, #8 800f570: 611a str r2, [r3, #16] 800f572: e00b b.n 800f58c } else { pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; 800f574: 68fb ldr r3, [r7, #12] 800f576: 681a ldr r2, [r3, #0] 800f578: 68bb ldr r3, [r7, #8] 800f57a: 331b adds r3, #27 800f57c: 011b lsls r3, r3, #4 800f57e: 4413 add r3, r2 800f580: 3304 adds r3, #4 800f582: 681b ldr r3, [r3, #0] 800f584: f003 020f and.w r2, r3, #15 800f588: 687b ldr r3, [r7, #4] 800f58a: 611a str r2, [r3, #16] } pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; 800f58c: 68fb ldr r3, [r7, #12] 800f58e: 681a ldr r2, [r3, #0] 800f590: 68bb ldr r3, [r7, #8] 800f592: 331b adds r3, #27 800f594: 011b lsls r3, r3, #4 800f596: 4413 add r3, r2 800f598: 3304 adds r3, #4 800f59a: 681b ldr r3, [r3, #0] 800f59c: 0a1b lsrs r3, r3, #8 800f59e: b2da uxtb r2, r3 800f5a0: 687b ldr r3, [r7, #4] 800f5a2: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; 800f5a4: 68fb ldr r3, [r7, #12] 800f5a6: 681a ldr r2, [r3, #0] 800f5a8: 68bb ldr r3, [r7, #8] 800f5aa: 331b adds r3, #27 800f5ac: 011b lsls r3, r3, #4 800f5ae: 4413 add r3, r2 800f5b0: 3304 adds r3, #4 800f5b2: 681b ldr r3, [r3, #0] 800f5b4: 0c1b lsrs r3, r3, #16 800f5b6: b29a uxth r2, r3 800f5b8: 687b ldr r3, [r7, #4] 800f5ba: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); 800f5bc: 68fb ldr r3, [r7, #12] 800f5be: 681a ldr r2, [r3, #0] 800f5c0: 68bb ldr r3, [r7, #8] 800f5c2: 011b lsls r3, r3, #4 800f5c4: 4413 add r3, r2 800f5c6: f503 73dc add.w r3, r3, #440 @ 0x1b8 800f5ca: 681b ldr r3, [r3, #0] 800f5cc: b2da uxtb r2, r3 800f5ce: 683b ldr r3, [r7, #0] 800f5d0: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); 800f5d2: 68fb ldr r3, [r7, #12] 800f5d4: 681a ldr r2, [r3, #0] 800f5d6: 68bb ldr r3, [r7, #8] 800f5d8: 011b lsls r3, r3, #4 800f5da: 4413 add r3, r2 800f5dc: f503 73dc add.w r3, r3, #440 @ 0x1b8 800f5e0: 681b ldr r3, [r3, #0] 800f5e2: 0a1a lsrs r2, r3, #8 800f5e4: 683b ldr r3, [r7, #0] 800f5e6: 3301 adds r3, #1 800f5e8: b2d2 uxtb r2, r2 800f5ea: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); 800f5ec: 68fb ldr r3, [r7, #12] 800f5ee: 681a ldr r2, [r3, #0] 800f5f0: 68bb ldr r3, [r7, #8] 800f5f2: 011b lsls r3, r3, #4 800f5f4: 4413 add r3, r2 800f5f6: f503 73dc add.w r3, r3, #440 @ 0x1b8 800f5fa: 681b ldr r3, [r3, #0] 800f5fc: 0c1a lsrs r2, r3, #16 800f5fe: 683b ldr r3, [r7, #0] 800f600: 3302 adds r3, #2 800f602: b2d2 uxtb r2, r2 800f604: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); 800f606: 68fb ldr r3, [r7, #12] 800f608: 681a ldr r2, [r3, #0] 800f60a: 68bb ldr r3, [r7, #8] 800f60c: 011b lsls r3, r3, #4 800f60e: 4413 add r3, r2 800f610: f503 73dc add.w r3, r3, #440 @ 0x1b8 800f614: 681b ldr r3, [r3, #0] 800f616: 0e1a lsrs r2, r3, #24 800f618: 683b ldr r3, [r7, #0] 800f61a: 3303 adds r3, #3 800f61c: b2d2 uxtb r2, r2 800f61e: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); 800f620: 68fb ldr r3, [r7, #12] 800f622: 681a ldr r2, [r3, #0] 800f624: 68bb ldr r3, [r7, #8] 800f626: 011b lsls r3, r3, #4 800f628: 4413 add r3, r2 800f62a: f503 73de add.w r3, r3, #444 @ 0x1bc 800f62e: 681a ldr r2, [r3, #0] 800f630: 683b ldr r3, [r7, #0] 800f632: 3304 adds r3, #4 800f634: b2d2 uxtb r2, r2 800f636: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); 800f638: 68fb ldr r3, [r7, #12] 800f63a: 681a ldr r2, [r3, #0] 800f63c: 68bb ldr r3, [r7, #8] 800f63e: 011b lsls r3, r3, #4 800f640: 4413 add r3, r2 800f642: f503 73de add.w r3, r3, #444 @ 0x1bc 800f646: 681b ldr r3, [r3, #0] 800f648: 0a1a lsrs r2, r3, #8 800f64a: 683b ldr r3, [r7, #0] 800f64c: 3305 adds r3, #5 800f64e: b2d2 uxtb r2, r2 800f650: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); 800f652: 68fb ldr r3, [r7, #12] 800f654: 681a ldr r2, [r3, #0] 800f656: 68bb ldr r3, [r7, #8] 800f658: 011b lsls r3, r3, #4 800f65a: 4413 add r3, r2 800f65c: f503 73de add.w r3, r3, #444 @ 0x1bc 800f660: 681b ldr r3, [r3, #0] 800f662: 0c1a lsrs r2, r3, #16 800f664: 683b ldr r3, [r7, #0] 800f666: 3306 adds r3, #6 800f668: b2d2 uxtb r2, r2 800f66a: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); 800f66c: 68fb ldr r3, [r7, #12] 800f66e: 681a ldr r2, [r3, #0] 800f670: 68bb ldr r3, [r7, #8] 800f672: 011b lsls r3, r3, #4 800f674: 4413 add r3, r2 800f676: f503 73de add.w r3, r3, #444 @ 0x1bc 800f67a: 681b ldr r3, [r3, #0] 800f67c: 0e1a lsrs r2, r3, #24 800f67e: 683b ldr r3, [r7, #0] 800f680: 3307 adds r3, #7 800f682: b2d2 uxtb r2, r2 800f684: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800f686: 68bb ldr r3, [r7, #8] 800f688: 2b00 cmp r3, #0 800f68a: d108 bne.n 800f69e { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); 800f68c: 68fb ldr r3, [r7, #12] 800f68e: 681b ldr r3, [r3, #0] 800f690: 68da ldr r2, [r3, #12] 800f692: 68fb ldr r3, [r7, #12] 800f694: 681b ldr r3, [r3, #0] 800f696: f042 0220 orr.w r2, r2, #32 800f69a: 60da str r2, [r3, #12] 800f69c: e007 b.n 800f6ae } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); 800f69e: 68fb ldr r3, [r7, #12] 800f6a0: 681b ldr r3, [r3, #0] 800f6a2: 691a ldr r2, [r3, #16] 800f6a4: 68fb ldr r3, [r7, #12] 800f6a6: 681b ldr r3, [r3, #0] 800f6a8: f042 0220 orr.w r2, r2, #32 800f6ac: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; 800f6ae: 2300 movs r3, #0 800f6b0: e006 b.n 800f6c0 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f6b2: 68fb ldr r3, [r7, #12] 800f6b4: 6a5b ldr r3, [r3, #36] @ 0x24 800f6b6: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f6ba: 68fb ldr r3, [r7, #12] 800f6bc: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f6be: 2301 movs r3, #1 } } 800f6c0: 4618 mov r0, r3 800f6c2: 371c adds r7, #28 800f6c4: 46bd mov sp, r7 800f6c6: bc80 pop {r7} 800f6c8: 4770 bx lr 0800f6ca : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { 800f6ca: b480 push {r7} 800f6cc: b085 sub sp, #20 800f6ce: af00 add r7, sp, #0 800f6d0: 6078 str r0, [r7, #4] 800f6d2: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800f6d4: 687b ldr r3, [r7, #4] 800f6d6: f893 3020 ldrb.w r3, [r3, #32] 800f6da: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || 800f6dc: 7bfb ldrb r3, [r7, #15] 800f6de: 2b01 cmp r3, #1 800f6e0: d002 beq.n 800f6e8 800f6e2: 7bfb ldrb r3, [r7, #15] 800f6e4: 2b02 cmp r3, #2 800f6e6: d109 bne.n 800f6fc (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); 800f6e8: 687b ldr r3, [r7, #4] 800f6ea: 681b ldr r3, [r3, #0] 800f6ec: 6959 ldr r1, [r3, #20] 800f6ee: 687b ldr r3, [r7, #4] 800f6f0: 681b ldr r3, [r3, #0] 800f6f2: 683a ldr r2, [r7, #0] 800f6f4: 430a orrs r2, r1 800f6f6: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; 800f6f8: 2300 movs r3, #0 800f6fa: e006 b.n 800f70a } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f6fc: 687b ldr r3, [r7, #4] 800f6fe: 6a5b ldr r3, [r3, #36] @ 0x24 800f700: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f704: 687b ldr r3, [r7, #4] 800f706: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f708: 2301 movs r3, #1 } } 800f70a: 4618 mov r0, r3 800f70c: 3714 adds r7, #20 800f70e: 46bd mov sp, r7 800f710: bc80 pop {r7} 800f712: 4770 bx lr 0800f714 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { 800f714: b580 push {r7, lr} 800f716: b08a sub sp, #40 @ 0x28 800f718: af00 add r7, sp, #0 800f71a: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; 800f71c: 2300 movs r3, #0 800f71e: 627b str r3, [r7, #36] @ 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); 800f720: 687b ldr r3, [r7, #4] 800f722: 681b ldr r3, [r3, #0] 800f724: 695b ldr r3, [r3, #20] 800f726: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); 800f728: 687b ldr r3, [r7, #4] 800f72a: 681b ldr r3, [r3, #0] 800f72c: 685b ldr r3, [r3, #4] 800f72e: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); 800f730: 687b ldr r3, [r7, #4] 800f732: 681b ldr r3, [r3, #0] 800f734: 689b ldr r3, [r3, #8] 800f736: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); 800f738: 687b ldr r3, [r7, #4] 800f73a: 681b ldr r3, [r3, #0] 800f73c: 68db ldr r3, [r3, #12] 800f73e: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); 800f740: 687b ldr r3, [r7, #4] 800f742: 681b ldr r3, [r3, #0] 800f744: 691b ldr r3, [r3, #16] 800f746: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); 800f748: 687b ldr r3, [r7, #4] 800f74a: 681b ldr r3, [r3, #0] 800f74c: 699b ldr r3, [r3, #24] 800f74e: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) 800f750: 6a3b ldr r3, [r7, #32] 800f752: f003 0301 and.w r3, r3, #1 800f756: 2b00 cmp r3, #0 800f758: d07c beq.n 800f854 { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) 800f75a: 69bb ldr r3, [r7, #24] 800f75c: f003 0301 and.w r3, r3, #1 800f760: 2b00 cmp r3, #0 800f762: d023 beq.n 800f7ac { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); 800f764: 687b ldr r3, [r7, #4] 800f766: 681b ldr r3, [r3, #0] 800f768: 2201 movs r2, #1 800f76a: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) 800f76c: 69bb ldr r3, [r7, #24] 800f76e: f003 0302 and.w r3, r3, #2 800f772: 2b00 cmp r3, #0 800f774: d003 beq.n 800f77e #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); 800f776: 6878 ldr r0, [r7, #4] 800f778: f000 f983 bl 800fa82 800f77c: e016 b.n 800f7ac #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) 800f77e: 69bb ldr r3, [r7, #24] 800f780: f003 0304 and.w r3, r3, #4 800f784: 2b00 cmp r3, #0 800f786: d004 beq.n 800f792 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; 800f788: 6a7b ldr r3, [r7, #36] @ 0x24 800f78a: f443 6300 orr.w r3, r3, #2048 @ 0x800 800f78e: 627b str r3, [r7, #36] @ 0x24 800f790: e00c b.n 800f7ac } else if ((tsrflags & CAN_TSR_TERR0) != 0U) 800f792: 69bb ldr r3, [r7, #24] 800f794: f003 0308 and.w r3, r3, #8 800f798: 2b00 cmp r3, #0 800f79a: d004 beq.n 800f7a6 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; 800f79c: 6a7b ldr r3, [r7, #36] @ 0x24 800f79e: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800f7a2: 627b str r3, [r7, #36] @ 0x24 800f7a4: e002 b.n 800f7ac #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); 800f7a6: 6878 ldr r0, [r7, #4] 800f7a8: f000 f986 bl 800fab8 } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) 800f7ac: 69bb ldr r3, [r7, #24] 800f7ae: f403 7380 and.w r3, r3, #256 @ 0x100 800f7b2: 2b00 cmp r3, #0 800f7b4: d024 beq.n 800f800 { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); 800f7b6: 687b ldr r3, [r7, #4] 800f7b8: 681b ldr r3, [r3, #0] 800f7ba: f44f 7280 mov.w r2, #256 @ 0x100 800f7be: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) 800f7c0: 69bb ldr r3, [r7, #24] 800f7c2: f403 7300 and.w r3, r3, #512 @ 0x200 800f7c6: 2b00 cmp r3, #0 800f7c8: d003 beq.n 800f7d2 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); 800f7ca: 6878 ldr r0, [r7, #4] 800f7cc: f000 f962 bl 800fa94 800f7d0: e016 b.n 800f800 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) 800f7d2: 69bb ldr r3, [r7, #24] 800f7d4: f403 6380 and.w r3, r3, #1024 @ 0x400 800f7d8: 2b00 cmp r3, #0 800f7da: d004 beq.n 800f7e6 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; 800f7dc: 6a7b ldr r3, [r7, #36] @ 0x24 800f7de: f443 5300 orr.w r3, r3, #8192 @ 0x2000 800f7e2: 627b str r3, [r7, #36] @ 0x24 800f7e4: e00c b.n 800f800 } else if ((tsrflags & CAN_TSR_TERR1) != 0U) 800f7e6: 69bb ldr r3, [r7, #24] 800f7e8: f403 6300 and.w r3, r3, #2048 @ 0x800 800f7ec: 2b00 cmp r3, #0 800f7ee: d004 beq.n 800f7fa { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; 800f7f0: 6a7b ldr r3, [r7, #36] @ 0x24 800f7f2: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800f7f6: 627b str r3, [r7, #36] @ 0x24 800f7f8: e002 b.n 800f800 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); 800f7fa: 6878 ldr r0, [r7, #4] 800f7fc: f000 f965 bl 800faca } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) 800f800: 69bb ldr r3, [r7, #24] 800f802: f403 3380 and.w r3, r3, #65536 @ 0x10000 800f806: 2b00 cmp r3, #0 800f808: d024 beq.n 800f854 { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); 800f80a: 687b ldr r3, [r7, #4] 800f80c: 681b ldr r3, [r3, #0] 800f80e: f44f 3280 mov.w r2, #65536 @ 0x10000 800f812: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) 800f814: 69bb ldr r3, [r7, #24] 800f816: f403 3300 and.w r3, r3, #131072 @ 0x20000 800f81a: 2b00 cmp r3, #0 800f81c: d003 beq.n 800f826 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); 800f81e: 6878 ldr r0, [r7, #4] 800f820: f000 f941 bl 800faa6 800f824: e016 b.n 800f854 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) 800f826: 69bb ldr r3, [r7, #24] 800f828: f403 2380 and.w r3, r3, #262144 @ 0x40000 800f82c: 2b00 cmp r3, #0 800f82e: d004 beq.n 800f83a { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; 800f830: 6a7b ldr r3, [r7, #36] @ 0x24 800f832: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f836: 627b str r3, [r7, #36] @ 0x24 800f838: e00c b.n 800f854 } else if ((tsrflags & CAN_TSR_TERR2) != 0U) 800f83a: 69bb ldr r3, [r7, #24] 800f83c: f403 2300 and.w r3, r3, #524288 @ 0x80000 800f840: 2b00 cmp r3, #0 800f842: d004 beq.n 800f84e { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; 800f844: 6a7b ldr r3, [r7, #36] @ 0x24 800f846: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800f84a: 627b str r3, [r7, #36] @ 0x24 800f84c: e002 b.n 800f854 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); 800f84e: 6878 ldr r0, [r7, #4] 800f850: f000 f944 bl 800fadc } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) 800f854: 6a3b ldr r3, [r7, #32] 800f856: f003 0308 and.w r3, r3, #8 800f85a: 2b00 cmp r3, #0 800f85c: d00c beq.n 800f878 { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) 800f85e: 697b ldr r3, [r7, #20] 800f860: f003 0310 and.w r3, r3, #16 800f864: 2b00 cmp r3, #0 800f866: d007 beq.n 800f878 { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; 800f868: 6a7b ldr r3, [r7, #36] @ 0x24 800f86a: f443 7300 orr.w r3, r3, #512 @ 0x200 800f86e: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); 800f870: 687b ldr r3, [r7, #4] 800f872: 681b ldr r3, [r3, #0] 800f874: 2210 movs r2, #16 800f876: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) 800f878: 6a3b ldr r3, [r7, #32] 800f87a: f003 0304 and.w r3, r3, #4 800f87e: 2b00 cmp r3, #0 800f880: d00b beq.n 800f89a { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) 800f882: 697b ldr r3, [r7, #20] 800f884: f003 0308 and.w r3, r3, #8 800f888: 2b00 cmp r3, #0 800f88a: d006 beq.n 800f89a { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); 800f88c: 687b ldr r3, [r7, #4] 800f88e: 681b ldr r3, [r3, #0] 800f890: 2208 movs r2, #8 800f892: 60da str r2, [r3, #12] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); 800f894: 6878 ldr r0, [r7, #4] 800f896: f000 f933 bl 800fb00 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) 800f89a: 6a3b ldr r3, [r7, #32] 800f89c: f003 0302 and.w r3, r3, #2 800f8a0: 2b00 cmp r3, #0 800f8a2: d009 beq.n 800f8b8 { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) 800f8a4: 687b ldr r3, [r7, #4] 800f8a6: 681b ldr r3, [r3, #0] 800f8a8: 68db ldr r3, [r3, #12] 800f8aa: f003 0303 and.w r3, r3, #3 800f8ae: 2b00 cmp r3, #0 800f8b0: d002 beq.n 800f8b8 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); 800f8b2: 6878 ldr r0, [r7, #4] 800f8b4: f000 f91b bl 800faee #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) 800f8b8: 6a3b ldr r3, [r7, #32] 800f8ba: f003 0340 and.w r3, r3, #64 @ 0x40 800f8be: 2b00 cmp r3, #0 800f8c0: d00c beq.n 800f8dc { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) 800f8c2: 693b ldr r3, [r7, #16] 800f8c4: f003 0310 and.w r3, r3, #16 800f8c8: 2b00 cmp r3, #0 800f8ca: d007 beq.n 800f8dc { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; 800f8cc: 6a7b ldr r3, [r7, #36] @ 0x24 800f8ce: f443 6380 orr.w r3, r3, #1024 @ 0x400 800f8d2: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); 800f8d4: 687b ldr r3, [r7, #4] 800f8d6: 681b ldr r3, [r3, #0] 800f8d8: 2210 movs r2, #16 800f8da: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) 800f8dc: 6a3b ldr r3, [r7, #32] 800f8de: f003 0320 and.w r3, r3, #32 800f8e2: 2b00 cmp r3, #0 800f8e4: d00b beq.n 800f8fe { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) 800f8e6: 693b ldr r3, [r7, #16] 800f8e8: f003 0308 and.w r3, r3, #8 800f8ec: 2b00 cmp r3, #0 800f8ee: d006 beq.n 800f8fe { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); 800f8f0: 687b ldr r3, [r7, #4] 800f8f2: 681b ldr r3, [r3, #0] 800f8f4: 2208 movs r2, #8 800f8f6: 611a str r2, [r3, #16] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); 800f8f8: 6878 ldr r0, [r7, #4] 800f8fa: f000 f90a bl 800fb12 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) 800f8fe: 6a3b ldr r3, [r7, #32] 800f900: f003 0310 and.w r3, r3, #16 800f904: 2b00 cmp r3, #0 800f906: d009 beq.n 800f91c { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) 800f908: 687b ldr r3, [r7, #4] 800f90a: 681b ldr r3, [r3, #0] 800f90c: 691b ldr r3, [r3, #16] 800f90e: f003 0303 and.w r3, r3, #3 800f912: 2b00 cmp r3, #0 800f914: d002 beq.n 800f91c #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); 800f916: 6878 ldr r0, [r7, #4] 800f918: f7fb fa0e bl 800ad38 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) 800f91c: 6a3b ldr r3, [r7, #32] 800f91e: f403 3300 and.w r3, r3, #131072 @ 0x20000 800f922: 2b00 cmp r3, #0 800f924: d00b beq.n 800f93e { if ((msrflags & CAN_MSR_SLAKI) != 0U) 800f926: 69fb ldr r3, [r7, #28] 800f928: f003 0310 and.w r3, r3, #16 800f92c: 2b00 cmp r3, #0 800f92e: d006 beq.n 800f93e { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); 800f930: 687b ldr r3, [r7, #4] 800f932: 681b ldr r3, [r3, #0] 800f934: 2210 movs r2, #16 800f936: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->SleepCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); 800f938: 6878 ldr r0, [r7, #4] 800f93a: f000 f8f3 bl 800fb24 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ if ((interrupts & CAN_IT_WAKEUP) != 0U) 800f93e: 6a3b ldr r3, [r7, #32] 800f940: f403 3380 and.w r3, r3, #65536 @ 0x10000 800f944: 2b00 cmp r3, #0 800f946: d00b beq.n 800f960 { if ((msrflags & CAN_MSR_WKUI) != 0U) 800f948: 69fb ldr r3, [r7, #28] 800f94a: f003 0308 and.w r3, r3, #8 800f94e: 2b00 cmp r3, #0 800f950: d006 beq.n 800f960 { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); 800f952: 687b ldr r3, [r7, #4] 800f954: 681b ldr r3, [r3, #0] 800f956: 2208 movs r2, #8 800f958: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->WakeUpFromRxMsgCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); 800f95a: 6878 ldr r0, [r7, #4] 800f95c: f000 f8eb bl 800fb36 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ if ((interrupts & CAN_IT_ERROR) != 0U) 800f960: 6a3b ldr r3, [r7, #32] 800f962: f403 4300 and.w r3, r3, #32768 @ 0x8000 800f966: 2b00 cmp r3, #0 800f968: d07b beq.n 800fa62 { if ((msrflags & CAN_MSR_ERRI) != 0U) 800f96a: 69fb ldr r3, [r7, #28] 800f96c: f003 0304 and.w r3, r3, #4 800f970: 2b00 cmp r3, #0 800f972: d072 beq.n 800fa5a { /* Check Error Warning Flag */ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800f974: 6a3b ldr r3, [r7, #32] 800f976: f403 7380 and.w r3, r3, #256 @ 0x100 800f97a: 2b00 cmp r3, #0 800f97c: d008 beq.n 800f990 ((esrflags & CAN_ESR_EWGF) != 0U)) 800f97e: 68fb ldr r3, [r7, #12] 800f980: f003 0301 and.w r3, r3, #1 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800f984: 2b00 cmp r3, #0 800f986: d003 beq.n 800f990 { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; 800f988: 6a7b ldr r3, [r7, #36] @ 0x24 800f98a: f043 0301 orr.w r3, r3, #1 800f98e: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Warning Flag as read-only */ } /* Check Error Passive Flag */ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800f990: 6a3b ldr r3, [r7, #32] 800f992: f403 7300 and.w r3, r3, #512 @ 0x200 800f996: 2b00 cmp r3, #0 800f998: d008 beq.n 800f9ac ((esrflags & CAN_ESR_EPVF) != 0U)) 800f99a: 68fb ldr r3, [r7, #12] 800f99c: f003 0302 and.w r3, r3, #2 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800f9a0: 2b00 cmp r3, #0 800f9a2: d003 beq.n 800f9ac { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; 800f9a4: 6a7b ldr r3, [r7, #36] @ 0x24 800f9a6: f043 0302 orr.w r3, r3, #2 800f9aa: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-off Flag */ if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800f9ac: 6a3b ldr r3, [r7, #32] 800f9ae: f403 6380 and.w r3, r3, #1024 @ 0x400 800f9b2: 2b00 cmp r3, #0 800f9b4: d008 beq.n 800f9c8 ((esrflags & CAN_ESR_BOFF) != 0U)) 800f9b6: 68fb ldr r3, [r7, #12] 800f9b8: f003 0304 and.w r3, r3, #4 if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800f9bc: 2b00 cmp r3, #0 800f9be: d003 beq.n 800f9c8 { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; 800f9c0: 6a7b ldr r3, [r7, #36] @ 0x24 800f9c2: f043 0304 orr.w r3, r3, #4 800f9c6: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Bus-Off as read-only */ } /* Check Last Error Code Flag */ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800f9c8: 6a3b ldr r3, [r7, #32] 800f9ca: f403 6300 and.w r3, r3, #2048 @ 0x800 800f9ce: 2b00 cmp r3, #0 800f9d0: d043 beq.n 800fa5a ((esrflags & CAN_ESR_LEC) != 0U)) 800f9d2: 68fb ldr r3, [r7, #12] 800f9d4: f003 0370 and.w r3, r3, #112 @ 0x70 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800f9d8: 2b00 cmp r3, #0 800f9da: d03e beq.n 800fa5a { switch (esrflags & CAN_ESR_LEC) 800f9dc: 68fb ldr r3, [r7, #12] 800f9de: f003 0370 and.w r3, r3, #112 @ 0x70 800f9e2: 2b60 cmp r3, #96 @ 0x60 800f9e4: d02b beq.n 800fa3e 800f9e6: 2b60 cmp r3, #96 @ 0x60 800f9e8: d82e bhi.n 800fa48 800f9ea: 2b50 cmp r3, #80 @ 0x50 800f9ec: d022 beq.n 800fa34 800f9ee: 2b50 cmp r3, #80 @ 0x50 800f9f0: d82a bhi.n 800fa48 800f9f2: 2b40 cmp r3, #64 @ 0x40 800f9f4: d019 beq.n 800fa2a 800f9f6: 2b40 cmp r3, #64 @ 0x40 800f9f8: d826 bhi.n 800fa48 800f9fa: 2b30 cmp r3, #48 @ 0x30 800f9fc: d010 beq.n 800fa20 800f9fe: 2b30 cmp r3, #48 @ 0x30 800fa00: d822 bhi.n 800fa48 800fa02: 2b10 cmp r3, #16 800fa04: d002 beq.n 800fa0c 800fa06: 2b20 cmp r3, #32 800fa08: d005 beq.n 800fa16 case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): /* Set CAN error code to CRC error */ errorcode |= HAL_CAN_ERROR_CRC; break; default: break; 800fa0a: e01d b.n 800fa48 errorcode |= HAL_CAN_ERROR_STF; 800fa0c: 6a7b ldr r3, [r7, #36] @ 0x24 800fa0e: f043 0308 orr.w r3, r3, #8 800fa12: 627b str r3, [r7, #36] @ 0x24 break; 800fa14: e019 b.n 800fa4a errorcode |= HAL_CAN_ERROR_FOR; 800fa16: 6a7b ldr r3, [r7, #36] @ 0x24 800fa18: f043 0310 orr.w r3, r3, #16 800fa1c: 627b str r3, [r7, #36] @ 0x24 break; 800fa1e: e014 b.n 800fa4a errorcode |= HAL_CAN_ERROR_ACK; 800fa20: 6a7b ldr r3, [r7, #36] @ 0x24 800fa22: f043 0320 orr.w r3, r3, #32 800fa26: 627b str r3, [r7, #36] @ 0x24 break; 800fa28: e00f b.n 800fa4a errorcode |= HAL_CAN_ERROR_BR; 800fa2a: 6a7b ldr r3, [r7, #36] @ 0x24 800fa2c: f043 0340 orr.w r3, r3, #64 @ 0x40 800fa30: 627b str r3, [r7, #36] @ 0x24 break; 800fa32: e00a b.n 800fa4a errorcode |= HAL_CAN_ERROR_BD; 800fa34: 6a7b ldr r3, [r7, #36] @ 0x24 800fa36: f043 0380 orr.w r3, r3, #128 @ 0x80 800fa3a: 627b str r3, [r7, #36] @ 0x24 break; 800fa3c: e005 b.n 800fa4a errorcode |= HAL_CAN_ERROR_CRC; 800fa3e: 6a7b ldr r3, [r7, #36] @ 0x24 800fa40: f443 7380 orr.w r3, r3, #256 @ 0x100 800fa44: 627b str r3, [r7, #36] @ 0x24 break; 800fa46: e000 b.n 800fa4a break; 800fa48: bf00 nop } /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); 800fa4a: 687b ldr r3, [r7, #4] 800fa4c: 681b ldr r3, [r3, #0] 800fa4e: 699a ldr r2, [r3, #24] 800fa50: 687b ldr r3, [r7, #4] 800fa52: 681b ldr r3, [r3, #0] 800fa54: f022 0270 bic.w r2, r2, #112 @ 0x70 800fa58: 619a str r2, [r3, #24] } } /* Clear ERRI Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); 800fa5a: 687b ldr r3, [r7, #4] 800fa5c: 681b ldr r3, [r3, #0] 800fa5e: 2204 movs r2, #4 800fa60: 605a str r2, [r3, #4] } /* Call the Error call Back in case of Errors */ if (errorcode != HAL_CAN_ERROR_NONE) 800fa62: 6a7b ldr r3, [r7, #36] @ 0x24 800fa64: 2b00 cmp r3, #0 800fa66: d008 beq.n 800fa7a { /* Update error code in handle */ hcan->ErrorCode |= errorcode; 800fa68: 687b ldr r3, [r7, #4] 800fa6a: 6a5a ldr r2, [r3, #36] @ 0x24 800fa6c: 6a7b ldr r3, [r7, #36] @ 0x24 800fa6e: 431a orrs r2, r3 800fa70: 687b ldr r3, [r7, #4] 800fa72: 625a str r2, [r3, #36] @ 0x24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->ErrorCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); 800fa74: 6878 ldr r0, [r7, #4] 800fa76: f000 f867 bl 800fb48 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } 800fa7a: bf00 nop 800fa7c: 3728 adds r7, #40 @ 0x28 800fa7e: 46bd mov sp, r7 800fa80: bd80 pop {r7, pc} 0800fa82 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { 800fa82: b480 push {r7} 800fa84: b083 sub sp, #12 800fa86: af00 add r7, sp, #0 800fa88: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the user file */ } 800fa8a: bf00 nop 800fa8c: 370c adds r7, #12 800fa8e: 46bd mov sp, r7 800fa90: bc80 pop {r7} 800fa92: 4770 bx lr 0800fa94 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { 800fa94: b480 push {r7} 800fa96: b083 sub sp, #12 800fa98: af00 add r7, sp, #0 800fa9a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the user file */ } 800fa9c: bf00 nop 800fa9e: 370c adds r7, #12 800faa0: 46bd mov sp, r7 800faa2: bc80 pop {r7} 800faa4: 4770 bx lr 0800faa6 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) { 800faa6: b480 push {r7} 800faa8: b083 sub sp, #12 800faaa: af00 add r7, sp, #0 800faac: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the user file */ } 800faae: bf00 nop 800fab0: 370c adds r7, #12 800fab2: 46bd mov sp, r7 800fab4: bc80 pop {r7} 800fab6: 4770 bx lr 0800fab8 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { 800fab8: b480 push {r7} 800faba: b083 sub sp, #12 800fabc: af00 add r7, sp, #0 800fabe: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } 800fac0: bf00 nop 800fac2: 370c adds r7, #12 800fac4: 46bd mov sp, r7 800fac6: bc80 pop {r7} 800fac8: 4770 bx lr 0800faca : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { 800faca: b480 push {r7} 800facc: b083 sub sp, #12 800face: af00 add r7, sp, #0 800fad0: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } 800fad2: bf00 nop 800fad4: 370c adds r7, #12 800fad6: 46bd mov sp, r7 800fad8: bc80 pop {r7} 800fada: 4770 bx lr 0800fadc : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { 800fadc: b480 push {r7} 800fade: b083 sub sp, #12 800fae0: af00 add r7, sp, #0 800fae2: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } 800fae4: bf00 nop 800fae6: 370c adds r7, #12 800fae8: 46bd mov sp, r7 800faea: bc80 pop {r7} 800faec: 4770 bx lr 0800faee : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { 800faee: b480 push {r7} 800faf0: b083 sub sp, #12 800faf2: af00 add r7, sp, #0 800faf4: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the user file */ } 800faf6: bf00 nop 800faf8: 370c adds r7, #12 800fafa: 46bd mov sp, r7 800fafc: bc80 pop {r7} 800fafe: 4770 bx lr 0800fb00 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { 800fb00: b480 push {r7} 800fb02: b083 sub sp, #12 800fb04: af00 add r7, sp, #0 800fb06: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } 800fb08: bf00 nop 800fb0a: 370c adds r7, #12 800fb0c: 46bd mov sp, r7 800fb0e: bc80 pop {r7} 800fb10: 4770 bx lr 0800fb12 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { 800fb12: b480 push {r7} 800fb14: b083 sub sp, #12 800fb16: af00 add r7, sp, #0 800fb18: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } 800fb1a: bf00 nop 800fb1c: 370c adds r7, #12 800fb1e: 46bd mov sp, r7 800fb20: bc80 pop {r7} 800fb22: 4770 bx lr 0800fb24 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { 800fb24: b480 push {r7} 800fb26: b083 sub sp, #12 800fb28: af00 add r7, sp, #0 800fb2a: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } 800fb2c: bf00 nop 800fb2e: 370c adds r7, #12 800fb30: 46bd mov sp, r7 800fb32: bc80 pop {r7} 800fb34: 4770 bx lr 0800fb36 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { 800fb36: b480 push {r7} 800fb38: b083 sub sp, #12 800fb3a: af00 add r7, sp, #0 800fb3c: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } 800fb3e: bf00 nop 800fb40: 370c adds r7, #12 800fb42: 46bd mov sp, r7 800fb44: bc80 pop {r7} 800fb46: 4770 bx lr 0800fb48 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { 800fb48: b480 push {r7} 800fb4a: b083 sub sp, #12 800fb4c: af00 add r7, sp, #0 800fb4e: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } 800fb50: bf00 nop 800fb52: 370c adds r7, #12 800fb54: 46bd mov sp, r7 800fb56: bc80 pop {r7} 800fb58: 4770 bx lr ... 0800fb5c <__NVIC_SetPriorityGrouping>: { 800fb5c: b480 push {r7} 800fb5e: b085 sub sp, #20 800fb60: af00 add r7, sp, #0 800fb62: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800fb64: 687b ldr r3, [r7, #4] 800fb66: f003 0307 and.w r3, r3, #7 800fb6a: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 800fb6c: 4b0c ldr r3, [pc, #48] @ (800fba0 <__NVIC_SetPriorityGrouping+0x44>) 800fb6e: 68db ldr r3, [r3, #12] 800fb70: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800fb72: 68ba ldr r2, [r7, #8] 800fb74: f64f 03ff movw r3, #63743 @ 0xf8ff 800fb78: 4013 ands r3, r2 800fb7a: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800fb7c: 68fb ldr r3, [r7, #12] 800fb7e: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800fb80: 68bb ldr r3, [r7, #8] 800fb82: 4313 orrs r3, r2 reg_value = (reg_value | 800fb84: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 800fb88: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800fb8c: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800fb8e: 4a04 ldr r2, [pc, #16] @ (800fba0 <__NVIC_SetPriorityGrouping+0x44>) 800fb90: 68bb ldr r3, [r7, #8] 800fb92: 60d3 str r3, [r2, #12] } 800fb94: bf00 nop 800fb96: 3714 adds r7, #20 800fb98: 46bd mov sp, r7 800fb9a: bc80 pop {r7} 800fb9c: 4770 bx lr 800fb9e: bf00 nop 800fba0: e000ed00 .word 0xe000ed00 0800fba4 <__NVIC_GetPriorityGrouping>: { 800fba4: b480 push {r7} 800fba6: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800fba8: 4b04 ldr r3, [pc, #16] @ (800fbbc <__NVIC_GetPriorityGrouping+0x18>) 800fbaa: 68db ldr r3, [r3, #12] 800fbac: 0a1b lsrs r3, r3, #8 800fbae: f003 0307 and.w r3, r3, #7 } 800fbb2: 4618 mov r0, r3 800fbb4: 46bd mov sp, r7 800fbb6: bc80 pop {r7} 800fbb8: 4770 bx lr 800fbba: bf00 nop 800fbbc: e000ed00 .word 0xe000ed00 0800fbc0 <__NVIC_EnableIRQ>: { 800fbc0: b480 push {r7} 800fbc2: b083 sub sp, #12 800fbc4: af00 add r7, sp, #0 800fbc6: 4603 mov r3, r0 800fbc8: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800fbca: f997 3007 ldrsb.w r3, [r7, #7] 800fbce: 2b00 cmp r3, #0 800fbd0: db0b blt.n 800fbea <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800fbd2: 79fb ldrb r3, [r7, #7] 800fbd4: f003 021f and.w r2, r3, #31 800fbd8: 4906 ldr r1, [pc, #24] @ (800fbf4 <__NVIC_EnableIRQ+0x34>) 800fbda: f997 3007 ldrsb.w r3, [r7, #7] 800fbde: 095b lsrs r3, r3, #5 800fbe0: 2001 movs r0, #1 800fbe2: fa00 f202 lsl.w r2, r0, r2 800fbe6: f841 2023 str.w r2, [r1, r3, lsl #2] } 800fbea: bf00 nop 800fbec: 370c adds r7, #12 800fbee: 46bd mov sp, r7 800fbf0: bc80 pop {r7} 800fbf2: 4770 bx lr 800fbf4: e000e100 .word 0xe000e100 0800fbf8 <__NVIC_SetPriority>: { 800fbf8: b480 push {r7} 800fbfa: b083 sub sp, #12 800fbfc: af00 add r7, sp, #0 800fbfe: 4603 mov r3, r0 800fc00: 6039 str r1, [r7, #0] 800fc02: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800fc04: f997 3007 ldrsb.w r3, [r7, #7] 800fc08: 2b00 cmp r3, #0 800fc0a: db0a blt.n 800fc22 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800fc0c: 683b ldr r3, [r7, #0] 800fc0e: b2da uxtb r2, r3 800fc10: 490c ldr r1, [pc, #48] @ (800fc44 <__NVIC_SetPriority+0x4c>) 800fc12: f997 3007 ldrsb.w r3, [r7, #7] 800fc16: 0112 lsls r2, r2, #4 800fc18: b2d2 uxtb r2, r2 800fc1a: 440b add r3, r1 800fc1c: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 800fc20: e00a b.n 800fc38 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800fc22: 683b ldr r3, [r7, #0] 800fc24: b2da uxtb r2, r3 800fc26: 4908 ldr r1, [pc, #32] @ (800fc48 <__NVIC_SetPriority+0x50>) 800fc28: 79fb ldrb r3, [r7, #7] 800fc2a: f003 030f and.w r3, r3, #15 800fc2e: 3b04 subs r3, #4 800fc30: 0112 lsls r2, r2, #4 800fc32: b2d2 uxtb r2, r2 800fc34: 440b add r3, r1 800fc36: 761a strb r2, [r3, #24] } 800fc38: bf00 nop 800fc3a: 370c adds r7, #12 800fc3c: 46bd mov sp, r7 800fc3e: bc80 pop {r7} 800fc40: 4770 bx lr 800fc42: bf00 nop 800fc44: e000e100 .word 0xe000e100 800fc48: e000ed00 .word 0xe000ed00 0800fc4c : { 800fc4c: b480 push {r7} 800fc4e: b089 sub sp, #36 @ 0x24 800fc50: af00 add r7, sp, #0 800fc52: 60f8 str r0, [r7, #12] 800fc54: 60b9 str r1, [r7, #8] 800fc56: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800fc58: 68fb ldr r3, [r7, #12] 800fc5a: f003 0307 and.w r3, r3, #7 800fc5e: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 800fc60: 69fb ldr r3, [r7, #28] 800fc62: f1c3 0307 rsb r3, r3, #7 800fc66: 2b04 cmp r3, #4 800fc68: bf28 it cs 800fc6a: 2304 movcs r3, #4 800fc6c: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800fc6e: 69fb ldr r3, [r7, #28] 800fc70: 3304 adds r3, #4 800fc72: 2b06 cmp r3, #6 800fc74: d902 bls.n 800fc7c 800fc76: 69fb ldr r3, [r7, #28] 800fc78: 3b03 subs r3, #3 800fc7a: e000 b.n 800fc7e 800fc7c: 2300 movs r3, #0 800fc7e: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800fc80: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800fc84: 69bb ldr r3, [r7, #24] 800fc86: fa02 f303 lsl.w r3, r2, r3 800fc8a: 43da mvns r2, r3 800fc8c: 68bb ldr r3, [r7, #8] 800fc8e: 401a ands r2, r3 800fc90: 697b ldr r3, [r7, #20] 800fc92: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800fc94: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800fc98: 697b ldr r3, [r7, #20] 800fc9a: fa01 f303 lsl.w r3, r1, r3 800fc9e: 43d9 mvns r1, r3 800fca0: 687b ldr r3, [r7, #4] 800fca2: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800fca4: 4313 orrs r3, r2 } 800fca6: 4618 mov r0, r3 800fca8: 3724 adds r7, #36 @ 0x24 800fcaa: 46bd mov sp, r7 800fcac: bc80 pop {r7} 800fcae: 4770 bx lr 0800fcb0 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800fcb0: b580 push {r7, lr} 800fcb2: b082 sub sp, #8 800fcb4: af00 add r7, sp, #0 800fcb6: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 800fcb8: 687b ldr r3, [r7, #4] 800fcba: 3b01 subs r3, #1 800fcbc: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800fcc0: d301 bcc.n 800fcc6 { return (1UL); /* Reload value impossible */ 800fcc2: 2301 movs r3, #1 800fcc4: e00f b.n 800fce6 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800fcc6: 4a0a ldr r2, [pc, #40] @ (800fcf0 ) 800fcc8: 687b ldr r3, [r7, #4] 800fcca: 3b01 subs r3, #1 800fccc: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800fcce: 210f movs r1, #15 800fcd0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800fcd4: f7ff ff90 bl 800fbf8 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800fcd8: 4b05 ldr r3, [pc, #20] @ (800fcf0 ) 800fcda: 2200 movs r2, #0 800fcdc: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800fcde: 4b04 ldr r3, [pc, #16] @ (800fcf0 ) 800fce0: 2207 movs r2, #7 800fce2: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 800fce4: 2300 movs r3, #0 } 800fce6: 4618 mov r0, r3 800fce8: 3708 adds r7, #8 800fcea: 46bd mov sp, r7 800fcec: bd80 pop {r7, pc} 800fcee: bf00 nop 800fcf0: e000e010 .word 0xe000e010 0800fcf4 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 800fcf4: b580 push {r7, lr} 800fcf6: b082 sub sp, #8 800fcf8: af00 add r7, sp, #0 800fcfa: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800fcfc: 6878 ldr r0, [r7, #4] 800fcfe: f7ff ff2d bl 800fb5c <__NVIC_SetPriorityGrouping> } 800fd02: bf00 nop 800fd04: 3708 adds r7, #8 800fd06: 46bd mov sp, r7 800fd08: bd80 pop {r7, pc} 0800fd0a : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800fd0a: b580 push {r7, lr} 800fd0c: b086 sub sp, #24 800fd0e: af00 add r7, sp, #0 800fd10: 4603 mov r3, r0 800fd12: 60b9 str r1, [r7, #8] 800fd14: 607a str r2, [r7, #4] 800fd16: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 800fd18: 2300 movs r3, #0 800fd1a: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800fd1c: f7ff ff42 bl 800fba4 <__NVIC_GetPriorityGrouping> 800fd20: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800fd22: 687a ldr r2, [r7, #4] 800fd24: 68b9 ldr r1, [r7, #8] 800fd26: 6978 ldr r0, [r7, #20] 800fd28: f7ff ff90 bl 800fc4c 800fd2c: 4602 mov r2, r0 800fd2e: f997 300f ldrsb.w r3, [r7, #15] 800fd32: 4611 mov r1, r2 800fd34: 4618 mov r0, r3 800fd36: f7ff ff5f bl 800fbf8 <__NVIC_SetPriority> } 800fd3a: bf00 nop 800fd3c: 3718 adds r7, #24 800fd3e: 46bd mov sp, r7 800fd40: bd80 pop {r7, pc} 0800fd42 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 800fd42: b580 push {r7, lr} 800fd44: b082 sub sp, #8 800fd46: af00 add r7, sp, #0 800fd48: 4603 mov r3, r0 800fd4a: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800fd4c: f997 3007 ldrsb.w r3, [r7, #7] 800fd50: 4618 mov r0, r3 800fd52: f7ff ff35 bl 800fbc0 <__NVIC_EnableIRQ> } 800fd56: bf00 nop 800fd58: 3708 adds r7, #8 800fd5a: 46bd mov sp, r7 800fd5c: bd80 pop {r7, pc} 0800fd5e : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800fd5e: b580 push {r7, lr} 800fd60: b082 sub sp, #8 800fd62: af00 add r7, sp, #0 800fd64: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800fd66: 6878 ldr r0, [r7, #4] 800fd68: f7ff ffa2 bl 800fcb0 800fd6c: 4603 mov r3, r0 } 800fd6e: 4618 mov r0, r3 800fd70: 3708 adds r7, #8 800fd72: 46bd mov sp, r7 800fd74: bd80 pop {r7, pc} 0800fd76 : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 800fd76: b580 push {r7, lr} 800fd78: b082 sub sp, #8 800fd7a: af00 add r7, sp, #0 800fd7c: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 800fd7e: 687b ldr r3, [r7, #4] 800fd80: 2b00 cmp r3, #0 800fd82: d101 bne.n 800fd88 { return HAL_ERROR; 800fd84: 2301 movs r3, #1 800fd86: e00e b.n 800fda6 } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 800fd88: 687b ldr r3, [r7, #4] 800fd8a: 795b ldrb r3, [r3, #5] 800fd8c: b2db uxtb r3, r3 800fd8e: 2b00 cmp r3, #0 800fd90: d105 bne.n 800fd9e { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 800fd92: 687b ldr r3, [r7, #4] 800fd94: 2200 movs r2, #0 800fd96: 711a strb r2, [r3, #4] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 800fd98: 6878 ldr r0, [r7, #4] 800fd9a: f7fa faa7 bl 800a2ec } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 800fd9e: 687b ldr r3, [r7, #4] 800fda0: 2201 movs r2, #1 800fda2: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 800fda4: 2300 movs r3, #0 } 800fda6: 4618 mov r0, r3 800fda8: 3708 adds r7, #8 800fdaa: 46bd mov sp, r7 800fdac: bd80 pop {r7, pc} ... 0800fdb0 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 800fdb0: b480 push {r7} 800fdb2: b085 sub sp, #20 800fdb4: af00 add r7, sp, #0 800fdb6: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 800fdb8: 2300 movs r3, #0 800fdba: 60fb str r3, [r7, #12] /* Check the DMA handle allocation */ if(hdma == NULL) 800fdbc: 687b ldr r3, [r7, #4] 800fdbe: 2b00 cmp r3, #0 800fdc0: d101 bne.n 800fdc6 { return HAL_ERROR; 800fdc2: 2301 movs r3, #1 800fdc4: e059 b.n 800fe7a assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); #if defined (DMA2) /* calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 800fdc6: 687b ldr r3, [r7, #4] 800fdc8: 681b ldr r3, [r3, #0] 800fdca: 461a mov r2, r3 800fdcc: 4b2d ldr r3, [pc, #180] @ (800fe84 ) 800fdce: 429a cmp r2, r3 800fdd0: d80f bhi.n 800fdf2 { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 800fdd2: 687b ldr r3, [r7, #4] 800fdd4: 681b ldr r3, [r3, #0] 800fdd6: 461a mov r2, r3 800fdd8: 4b2b ldr r3, [pc, #172] @ (800fe88 ) 800fdda: 4413 add r3, r2 800fddc: 4a2b ldr r2, [pc, #172] @ (800fe8c ) 800fdde: fba2 2303 umull r2, r3, r2, r3 800fde2: 091b lsrs r3, r3, #4 800fde4: 009a lsls r2, r3, #2 800fde6: 687b ldr r3, [r7, #4] 800fde8: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA1; 800fdea: 687b ldr r3, [r7, #4] 800fdec: 4a28 ldr r2, [pc, #160] @ (800fe90 ) 800fdee: 63da str r2, [r3, #60] @ 0x3c 800fdf0: e00e b.n 800fe10 } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; 800fdf2: 687b ldr r3, [r7, #4] 800fdf4: 681b ldr r3, [r3, #0] 800fdf6: 461a mov r2, r3 800fdf8: 4b26 ldr r3, [pc, #152] @ (800fe94 ) 800fdfa: 4413 add r3, r2 800fdfc: 4a23 ldr r2, [pc, #140] @ (800fe8c ) 800fdfe: fba2 2303 umull r2, r3, r2, r3 800fe02: 091b lsrs r3, r3, #4 800fe04: 009a lsls r2, r3, #2 800fe06: 687b ldr r3, [r7, #4] 800fe08: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA2; 800fe0a: 687b ldr r3, [r7, #4] 800fe0c: 4a22 ldr r2, [pc, #136] @ (800fe98 ) 800fe0e: 63da str r2, [r3, #60] @ 0x3c hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; #endif /* DMA2 */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 800fe10: 687b ldr r3, [r7, #4] 800fe12: 2202 movs r2, #2 800fe14: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Get the CR register value */ tmp = hdma->Instance->CCR; 800fe18: 687b ldr r3, [r7, #4] 800fe1a: 681b ldr r3, [r3, #0] 800fe1c: 681b ldr r3, [r3, #0] 800fe1e: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 800fe20: 68fb ldr r3, [r7, #12] 800fe22: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 800fe26: f023 0330 bic.w r3, r3, #48 @ 0x30 800fe2a: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 800fe2c: 687b ldr r3, [r7, #4] 800fe2e: 685a ldr r2, [r3, #4] hdma->Init.PeriphInc | hdma->Init.MemInc | 800fe30: 687b ldr r3, [r7, #4] 800fe32: 689b ldr r3, [r3, #8] tmp |= hdma->Init.Direction | 800fe34: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 800fe36: 687b ldr r3, [r7, #4] 800fe38: 68db ldr r3, [r3, #12] 800fe3a: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800fe3c: 687b ldr r3, [r7, #4] 800fe3e: 691b ldr r3, [r3, #16] hdma->Init.PeriphInc | hdma->Init.MemInc | 800fe40: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800fe42: 687b ldr r3, [r7, #4] 800fe44: 695b ldr r3, [r3, #20] 800fe46: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800fe48: 687b ldr r3, [r7, #4] 800fe4a: 699b ldr r3, [r3, #24] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800fe4c: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800fe4e: 687b ldr r3, [r7, #4] 800fe50: 69db ldr r3, [r3, #28] 800fe52: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | 800fe54: 68fa ldr r2, [r7, #12] 800fe56: 4313 orrs r3, r2 800fe58: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; 800fe5a: 687b ldr r3, [r7, #4] 800fe5c: 681b ldr r3, [r3, #0] 800fe5e: 68fa ldr r2, [r7, #12] 800fe60: 601a str r2, [r3, #0] /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800fe62: 687b ldr r3, [r7, #4] 800fe64: 2200 movs r2, #0 800fe66: 639a str r2, [r3, #56] @ 0x38 /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 800fe68: 687b ldr r3, [r7, #4] 800fe6a: 2201 movs r2, #1 800fe6c: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; 800fe70: 687b ldr r3, [r7, #4] 800fe72: 2200 movs r2, #0 800fe74: f883 2020 strb.w r2, [r3, #32] return HAL_OK; 800fe78: 2300 movs r3, #0 } 800fe7a: 4618 mov r0, r3 800fe7c: 3714 adds r7, #20 800fe7e: 46bd mov sp, r7 800fe80: bc80 pop {r7} 800fe82: 4770 bx lr 800fe84: 40020407 .word 0x40020407 800fe88: bffdfff8 .word 0xbffdfff8 800fe8c: cccccccd .word 0xcccccccd 800fe90: 40020000 .word 0x40020000 800fe94: bffdfbf8 .word 0xbffdfbf8 800fe98: 40020400 .word 0x40020400 0800fe9c : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 800fe9c: b580 push {r7, lr} 800fe9e: b086 sub sp, #24 800fea0: af00 add r7, sp, #0 800fea2: 60f8 str r0, [r7, #12] 800fea4: 60b9 str r1, [r7, #8] 800fea6: 607a str r2, [r7, #4] 800fea8: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800feaa: 2300 movs r3, #0 800feac: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 800feae: 68fb ldr r3, [r7, #12] 800feb0: f893 3020 ldrb.w r3, [r3, #32] 800feb4: 2b01 cmp r3, #1 800feb6: d101 bne.n 800febc 800feb8: 2302 movs r3, #2 800feba: e04b b.n 800ff54 800febc: 68fb ldr r3, [r7, #12] 800febe: 2201 movs r2, #1 800fec0: f883 2020 strb.w r2, [r3, #32] if(HAL_DMA_STATE_READY == hdma->State) 800fec4: 68fb ldr r3, [r7, #12] 800fec6: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800feca: b2db uxtb r3, r3 800fecc: 2b01 cmp r3, #1 800fece: d13a bne.n 800ff46 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 800fed0: 68fb ldr r3, [r7, #12] 800fed2: 2202 movs r2, #2 800fed4: f883 2021 strb.w r2, [r3, #33] @ 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800fed8: 68fb ldr r3, [r7, #12] 800feda: 2200 movs r2, #0 800fedc: 639a str r2, [r3, #56] @ 0x38 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 800fede: 68fb ldr r3, [r7, #12] 800fee0: 681b ldr r3, [r3, #0] 800fee2: 681a ldr r2, [r3, #0] 800fee4: 68fb ldr r3, [r7, #12] 800fee6: 681b ldr r3, [r3, #0] 800fee8: f022 0201 bic.w r2, r2, #1 800feec: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 800feee: 683b ldr r3, [r7, #0] 800fef0: 687a ldr r2, [r7, #4] 800fef2: 68b9 ldr r1, [r7, #8] 800fef4: 68f8 ldr r0, [r7, #12] 800fef6: f000 fbbc bl 8010672 /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if(NULL != hdma->XferHalfCpltCallback) 800fefa: 68fb ldr r3, [r7, #12] 800fefc: 6adb ldr r3, [r3, #44] @ 0x2c 800fefe: 2b00 cmp r3, #0 800ff00: d008 beq.n 800ff14 { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800ff02: 68fb ldr r3, [r7, #12] 800ff04: 681b ldr r3, [r3, #0] 800ff06: 681a ldr r2, [r3, #0] 800ff08: 68fb ldr r3, [r7, #12] 800ff0a: 681b ldr r3, [r3, #0] 800ff0c: f042 020e orr.w r2, r2, #14 800ff10: 601a str r2, [r3, #0] 800ff12: e00f b.n 800ff34 } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800ff14: 68fb ldr r3, [r7, #12] 800ff16: 681b ldr r3, [r3, #0] 800ff18: 681a ldr r2, [r3, #0] 800ff1a: 68fb ldr r3, [r7, #12] 800ff1c: 681b ldr r3, [r3, #0] 800ff1e: f022 0204 bic.w r2, r2, #4 800ff22: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 800ff24: 68fb ldr r3, [r7, #12] 800ff26: 681b ldr r3, [r3, #0] 800ff28: 681a ldr r2, [r3, #0] 800ff2a: 68fb ldr r3, [r7, #12] 800ff2c: 681b ldr r3, [r3, #0] 800ff2e: f042 020a orr.w r2, r2, #10 800ff32: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 800ff34: 68fb ldr r3, [r7, #12] 800ff36: 681b ldr r3, [r3, #0] 800ff38: 681a ldr r2, [r3, #0] 800ff3a: 68fb ldr r3, [r7, #12] 800ff3c: 681b ldr r3, [r3, #0] 800ff3e: f042 0201 orr.w r2, r2, #1 800ff42: 601a str r2, [r3, #0] 800ff44: e005 b.n 800ff52 } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); 800ff46: 68fb ldr r3, [r7, #12] 800ff48: 2200 movs r2, #0 800ff4a: f883 2020 strb.w r2, [r3, #32] /* Remain BUSY */ status = HAL_BUSY; 800ff4e: 2302 movs r3, #2 800ff50: 75fb strb r3, [r7, #23] } return status; 800ff52: 7dfb ldrb r3, [r7, #23] } 800ff54: 4618 mov r0, r3 800ff56: 3718 adds r7, #24 800ff58: 46bd mov sp, r7 800ff5a: bd80 pop {r7, pc} 0800ff5c : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 800ff5c: b480 push {r7} 800ff5e: b085 sub sp, #20 800ff60: af00 add r7, sp, #0 800ff62: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800ff64: 2300 movs r3, #0 800ff66: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 800ff68: 687b ldr r3, [r7, #4] 800ff6a: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800ff6e: b2db uxtb r3, r3 800ff70: 2b02 cmp r3, #2 800ff72: d008 beq.n 800ff86 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800ff74: 687b ldr r3, [r7, #4] 800ff76: 2204 movs r2, #4 800ff78: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800ff7a: 687b ldr r3, [r7, #4] 800ff7c: 2200 movs r2, #0 800ff7e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800ff82: 2301 movs r3, #1 800ff84: e020 b.n 800ffc8 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800ff86: 687b ldr r3, [r7, #4] 800ff88: 681b ldr r3, [r3, #0] 800ff8a: 681a ldr r2, [r3, #0] 800ff8c: 687b ldr r3, [r7, #4] 800ff8e: 681b ldr r3, [r3, #0] 800ff90: f022 020e bic.w r2, r2, #14 800ff94: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800ff96: 687b ldr r3, [r7, #4] 800ff98: 681b ldr r3, [r3, #0] 800ff9a: 681a ldr r2, [r3, #0] 800ff9c: 687b ldr r3, [r7, #4] 800ff9e: 681b ldr r3, [r3, #0] 800ffa0: f022 0201 bic.w r2, r2, #1 800ffa4: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 800ffa6: 687b ldr r3, [r7, #4] 800ffa8: 6c1a ldr r2, [r3, #64] @ 0x40 800ffaa: 687b ldr r3, [r7, #4] 800ffac: 6bdb ldr r3, [r3, #60] @ 0x3c 800ffae: 2101 movs r1, #1 800ffb0: fa01 f202 lsl.w r2, r1, r2 800ffb4: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800ffb6: 687b ldr r3, [r7, #4] 800ffb8: 2201 movs r2, #1 800ffba: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800ffbe: 687b ldr r3, [r7, #4] 800ffc0: 2200 movs r2, #0 800ffc2: f883 2020 strb.w r2, [r3, #32] return status; 800ffc6: 7bfb ldrb r3, [r7, #15] } 800ffc8: 4618 mov r0, r3 800ffca: 3714 adds r7, #20 800ffcc: 46bd mov sp, r7 800ffce: bc80 pop {r7} 800ffd0: 4770 bx lr ... 0800ffd4 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 800ffd4: b580 push {r7, lr} 800ffd6: b084 sub sp, #16 800ffd8: af00 add r7, sp, #0 800ffda: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800ffdc: 2300 movs r3, #0 800ffde: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 800ffe0: 687b ldr r3, [r7, #4] 800ffe2: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800ffe6: b2db uxtb r3, r3 800ffe8: 2b02 cmp r3, #2 800ffea: d005 beq.n 800fff8 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800ffec: 687b ldr r3, [r7, #4] 800ffee: 2204 movs r2, #4 800fff0: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 800fff2: 2301 movs r3, #1 800fff4: 73fb strb r3, [r7, #15] 800fff6: e0d6 b.n 80101a6 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800fff8: 687b ldr r3, [r7, #4] 800fffa: 681b ldr r3, [r3, #0] 800fffc: 681a ldr r2, [r3, #0] 800fffe: 687b ldr r3, [r7, #4] 8010000: 681b ldr r3, [r3, #0] 8010002: f022 020e bic.w r2, r2, #14 8010006: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8010008: 687b ldr r3, [r7, #4] 801000a: 681b ldr r3, [r3, #0] 801000c: 681a ldr r2, [r3, #0] 801000e: 687b ldr r3, [r7, #4] 8010010: 681b ldr r3, [r3, #0] 8010012: f022 0201 bic.w r2, r2, #1 8010016: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 8010018: 687b ldr r3, [r7, #4] 801001a: 681b ldr r3, [r3, #0] 801001c: 461a mov r2, r3 801001e: 4b64 ldr r3, [pc, #400] @ (80101b0 ) 8010020: 429a cmp r2, r3 8010022: d958 bls.n 80100d6 8010024: 687b ldr r3, [r7, #4] 8010026: 681b ldr r3, [r3, #0] 8010028: 4a62 ldr r2, [pc, #392] @ (80101b4 ) 801002a: 4293 cmp r3, r2 801002c: d04f beq.n 80100ce 801002e: 687b ldr r3, [r7, #4] 8010030: 681b ldr r3, [r3, #0] 8010032: 4a61 ldr r2, [pc, #388] @ (80101b8 ) 8010034: 4293 cmp r3, r2 8010036: d048 beq.n 80100ca 8010038: 687b ldr r3, [r7, #4] 801003a: 681b ldr r3, [r3, #0] 801003c: 4a5f ldr r2, [pc, #380] @ (80101bc ) 801003e: 4293 cmp r3, r2 8010040: d040 beq.n 80100c4 8010042: 687b ldr r3, [r7, #4] 8010044: 681b ldr r3, [r3, #0] 8010046: 4a5e ldr r2, [pc, #376] @ (80101c0 ) 8010048: 4293 cmp r3, r2 801004a: d038 beq.n 80100be 801004c: 687b ldr r3, [r7, #4] 801004e: 681b ldr r3, [r3, #0] 8010050: 4a5c ldr r2, [pc, #368] @ (80101c4 ) 8010052: 4293 cmp r3, r2 8010054: d030 beq.n 80100b8 8010056: 687b ldr r3, [r7, #4] 8010058: 681b ldr r3, [r3, #0] 801005a: 4a5b ldr r2, [pc, #364] @ (80101c8 ) 801005c: 4293 cmp r3, r2 801005e: d028 beq.n 80100b2 8010060: 687b ldr r3, [r7, #4] 8010062: 681b ldr r3, [r3, #0] 8010064: 4a52 ldr r2, [pc, #328] @ (80101b0 ) 8010066: 4293 cmp r3, r2 8010068: d020 beq.n 80100ac 801006a: 687b ldr r3, [r7, #4] 801006c: 681b ldr r3, [r3, #0] 801006e: 4a57 ldr r2, [pc, #348] @ (80101cc ) 8010070: 4293 cmp r3, r2 8010072: d019 beq.n 80100a8 8010074: 687b ldr r3, [r7, #4] 8010076: 681b ldr r3, [r3, #0] 8010078: 4a55 ldr r2, [pc, #340] @ (80101d0 ) 801007a: 4293 cmp r3, r2 801007c: d012 beq.n 80100a4 801007e: 687b ldr r3, [r7, #4] 8010080: 681b ldr r3, [r3, #0] 8010082: 4a54 ldr r2, [pc, #336] @ (80101d4 ) 8010084: 4293 cmp r3, r2 8010086: d00a beq.n 801009e 8010088: 687b ldr r3, [r7, #4] 801008a: 681b ldr r3, [r3, #0] 801008c: 4a52 ldr r2, [pc, #328] @ (80101d8 ) 801008e: 4293 cmp r3, r2 8010090: d102 bne.n 8010098 8010092: f44f 5380 mov.w r3, #4096 @ 0x1000 8010096: e01b b.n 80100d0 8010098: f44f 3380 mov.w r3, #65536 @ 0x10000 801009c: e018 b.n 80100d0 801009e: f44f 7380 mov.w r3, #256 @ 0x100 80100a2: e015 b.n 80100d0 80100a4: 2310 movs r3, #16 80100a6: e013 b.n 80100d0 80100a8: 2301 movs r3, #1 80100aa: e011 b.n 80100d0 80100ac: f04f 7380 mov.w r3, #16777216 @ 0x1000000 80100b0: e00e b.n 80100d0 80100b2: f44f 1380 mov.w r3, #1048576 @ 0x100000 80100b6: e00b b.n 80100d0 80100b8: f44f 3380 mov.w r3, #65536 @ 0x10000 80100bc: e008 b.n 80100d0 80100be: f44f 5380 mov.w r3, #4096 @ 0x1000 80100c2: e005 b.n 80100d0 80100c4: f44f 7380 mov.w r3, #256 @ 0x100 80100c8: e002 b.n 80100d0 80100ca: 2310 movs r3, #16 80100cc: e000 b.n 80100d0 80100ce: 2301 movs r3, #1 80100d0: 4a42 ldr r2, [pc, #264] @ (80101dc ) 80100d2: 6053 str r3, [r2, #4] 80100d4: e057 b.n 8010186 80100d6: 687b ldr r3, [r7, #4] 80100d8: 681b ldr r3, [r3, #0] 80100da: 4a36 ldr r2, [pc, #216] @ (80101b4 ) 80100dc: 4293 cmp r3, r2 80100de: d04f beq.n 8010180 80100e0: 687b ldr r3, [r7, #4] 80100e2: 681b ldr r3, [r3, #0] 80100e4: 4a34 ldr r2, [pc, #208] @ (80101b8 ) 80100e6: 4293 cmp r3, r2 80100e8: d048 beq.n 801017c 80100ea: 687b ldr r3, [r7, #4] 80100ec: 681b ldr r3, [r3, #0] 80100ee: 4a33 ldr r2, [pc, #204] @ (80101bc ) 80100f0: 4293 cmp r3, r2 80100f2: d040 beq.n 8010176 80100f4: 687b ldr r3, [r7, #4] 80100f6: 681b ldr r3, [r3, #0] 80100f8: 4a31 ldr r2, [pc, #196] @ (80101c0 ) 80100fa: 4293 cmp r3, r2 80100fc: d038 beq.n 8010170 80100fe: 687b ldr r3, [r7, #4] 8010100: 681b ldr r3, [r3, #0] 8010102: 4a30 ldr r2, [pc, #192] @ (80101c4 ) 8010104: 4293 cmp r3, r2 8010106: d030 beq.n 801016a 8010108: 687b ldr r3, [r7, #4] 801010a: 681b ldr r3, [r3, #0] 801010c: 4a2e ldr r2, [pc, #184] @ (80101c8 ) 801010e: 4293 cmp r3, r2 8010110: d028 beq.n 8010164 8010112: 687b ldr r3, [r7, #4] 8010114: 681b ldr r3, [r3, #0] 8010116: 4a26 ldr r2, [pc, #152] @ (80101b0 ) 8010118: 4293 cmp r3, r2 801011a: d020 beq.n 801015e 801011c: 687b ldr r3, [r7, #4] 801011e: 681b ldr r3, [r3, #0] 8010120: 4a2a ldr r2, [pc, #168] @ (80101cc ) 8010122: 4293 cmp r3, r2 8010124: d019 beq.n 801015a 8010126: 687b ldr r3, [r7, #4] 8010128: 681b ldr r3, [r3, #0] 801012a: 4a29 ldr r2, [pc, #164] @ (80101d0 ) 801012c: 4293 cmp r3, r2 801012e: d012 beq.n 8010156 8010130: 687b ldr r3, [r7, #4] 8010132: 681b ldr r3, [r3, #0] 8010134: 4a27 ldr r2, [pc, #156] @ (80101d4 ) 8010136: 4293 cmp r3, r2 8010138: d00a beq.n 8010150 801013a: 687b ldr r3, [r7, #4] 801013c: 681b ldr r3, [r3, #0] 801013e: 4a26 ldr r2, [pc, #152] @ (80101d8 ) 8010140: 4293 cmp r3, r2 8010142: d102 bne.n 801014a 8010144: f44f 5380 mov.w r3, #4096 @ 0x1000 8010148: e01b b.n 8010182 801014a: f44f 3380 mov.w r3, #65536 @ 0x10000 801014e: e018 b.n 8010182 8010150: f44f 7380 mov.w r3, #256 @ 0x100 8010154: e015 b.n 8010182 8010156: 2310 movs r3, #16 8010158: e013 b.n 8010182 801015a: 2301 movs r3, #1 801015c: e011 b.n 8010182 801015e: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8010162: e00e b.n 8010182 8010164: f44f 1380 mov.w r3, #1048576 @ 0x100000 8010168: e00b b.n 8010182 801016a: f44f 3380 mov.w r3, #65536 @ 0x10000 801016e: e008 b.n 8010182 8010170: f44f 5380 mov.w r3, #4096 @ 0x1000 8010174: e005 b.n 8010182 8010176: f44f 7380 mov.w r3, #256 @ 0x100 801017a: e002 b.n 8010182 801017c: 2310 movs r3, #16 801017e: e000 b.n 8010182 8010180: 2301 movs r3, #1 8010182: 4a17 ldr r2, [pc, #92] @ (80101e0 ) 8010184: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8010186: 687b ldr r3, [r7, #4] 8010188: 2201 movs r2, #1 801018a: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 801018e: 687b ldr r3, [r7, #4] 8010190: 2200 movs r2, #0 8010192: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8010196: 687b ldr r3, [r7, #4] 8010198: 6b5b ldr r3, [r3, #52] @ 0x34 801019a: 2b00 cmp r3, #0 801019c: d003 beq.n 80101a6 { hdma->XferAbortCallback(hdma); 801019e: 687b ldr r3, [r7, #4] 80101a0: 6b5b ldr r3, [r3, #52] @ 0x34 80101a2: 6878 ldr r0, [r7, #4] 80101a4: 4798 blx r3 } } return status; 80101a6: 7bfb ldrb r3, [r7, #15] } 80101a8: 4618 mov r0, r3 80101aa: 3710 adds r7, #16 80101ac: 46bd mov sp, r7 80101ae: bd80 pop {r7, pc} 80101b0: 40020080 .word 0x40020080 80101b4: 40020008 .word 0x40020008 80101b8: 4002001c .word 0x4002001c 80101bc: 40020030 .word 0x40020030 80101c0: 40020044 .word 0x40020044 80101c4: 40020058 .word 0x40020058 80101c8: 4002006c .word 0x4002006c 80101cc: 40020408 .word 0x40020408 80101d0: 4002041c .word 0x4002041c 80101d4: 40020430 .word 0x40020430 80101d8: 40020444 .word 0x40020444 80101dc: 40020400 .word 0x40020400 80101e0: 40020000 .word 0x40020000 080101e4 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 80101e4: b580 push {r7, lr} 80101e6: b084 sub sp, #16 80101e8: af00 add r7, sp, #0 80101ea: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; 80101ec: 687b ldr r3, [r7, #4] 80101ee: 6bdb ldr r3, [r3, #60] @ 0x3c 80101f0: 681b ldr r3, [r3, #0] 80101f2: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; 80101f4: 687b ldr r3, [r7, #4] 80101f6: 681b ldr r3, [r3, #0] 80101f8: 681b ldr r3, [r3, #0] 80101fa: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 80101fc: 687b ldr r3, [r7, #4] 80101fe: 6c1b ldr r3, [r3, #64] @ 0x40 8010200: 2204 movs r2, #4 8010202: 409a lsls r2, r3 8010204: 68fb ldr r3, [r7, #12] 8010206: 4013 ands r3, r2 8010208: 2b00 cmp r3, #0 801020a: f000 80f1 beq.w 80103f0 801020e: 68bb ldr r3, [r7, #8] 8010210: f003 0304 and.w r3, r3, #4 8010214: 2b00 cmp r3, #0 8010216: f000 80eb beq.w 80103f0 { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 801021a: 687b ldr r3, [r7, #4] 801021c: 681b ldr r3, [r3, #0] 801021e: 681b ldr r3, [r3, #0] 8010220: f003 0320 and.w r3, r3, #32 8010224: 2b00 cmp r3, #0 8010226: d107 bne.n 8010238 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8010228: 687b ldr r3, [r7, #4] 801022a: 681b ldr r3, [r3, #0] 801022c: 681a ldr r2, [r3, #0] 801022e: 687b ldr r3, [r7, #4] 8010230: 681b ldr r3, [r3, #0] 8010232: f022 0204 bic.w r2, r2, #4 8010236: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); 8010238: 687b ldr r3, [r7, #4] 801023a: 681b ldr r3, [r3, #0] 801023c: 461a mov r2, r3 801023e: 4b5f ldr r3, [pc, #380] @ (80103bc ) 8010240: 429a cmp r2, r3 8010242: d958 bls.n 80102f6 8010244: 687b ldr r3, [r7, #4] 8010246: 681b ldr r3, [r3, #0] 8010248: 4a5d ldr r2, [pc, #372] @ (80103c0 ) 801024a: 4293 cmp r3, r2 801024c: d04f beq.n 80102ee 801024e: 687b ldr r3, [r7, #4] 8010250: 681b ldr r3, [r3, #0] 8010252: 4a5c ldr r2, [pc, #368] @ (80103c4 ) 8010254: 4293 cmp r3, r2 8010256: d048 beq.n 80102ea 8010258: 687b ldr r3, [r7, #4] 801025a: 681b ldr r3, [r3, #0] 801025c: 4a5a ldr r2, [pc, #360] @ (80103c8 ) 801025e: 4293 cmp r3, r2 8010260: d040 beq.n 80102e4 8010262: 687b ldr r3, [r7, #4] 8010264: 681b ldr r3, [r3, #0] 8010266: 4a59 ldr r2, [pc, #356] @ (80103cc ) 8010268: 4293 cmp r3, r2 801026a: d038 beq.n 80102de 801026c: 687b ldr r3, [r7, #4] 801026e: 681b ldr r3, [r3, #0] 8010270: 4a57 ldr r2, [pc, #348] @ (80103d0 ) 8010272: 4293 cmp r3, r2 8010274: d030 beq.n 80102d8 8010276: 687b ldr r3, [r7, #4] 8010278: 681b ldr r3, [r3, #0] 801027a: 4a56 ldr r2, [pc, #344] @ (80103d4 ) 801027c: 4293 cmp r3, r2 801027e: d028 beq.n 80102d2 8010280: 687b ldr r3, [r7, #4] 8010282: 681b ldr r3, [r3, #0] 8010284: 4a4d ldr r2, [pc, #308] @ (80103bc ) 8010286: 4293 cmp r3, r2 8010288: d020 beq.n 80102cc 801028a: 687b ldr r3, [r7, #4] 801028c: 681b ldr r3, [r3, #0] 801028e: 4a52 ldr r2, [pc, #328] @ (80103d8 ) 8010290: 4293 cmp r3, r2 8010292: d019 beq.n 80102c8 8010294: 687b ldr r3, [r7, #4] 8010296: 681b ldr r3, [r3, #0] 8010298: 4a50 ldr r2, [pc, #320] @ (80103dc ) 801029a: 4293 cmp r3, r2 801029c: d012 beq.n 80102c4 801029e: 687b ldr r3, [r7, #4] 80102a0: 681b ldr r3, [r3, #0] 80102a2: 4a4f ldr r2, [pc, #316] @ (80103e0 ) 80102a4: 4293 cmp r3, r2 80102a6: d00a beq.n 80102be 80102a8: 687b ldr r3, [r7, #4] 80102aa: 681b ldr r3, [r3, #0] 80102ac: 4a4d ldr r2, [pc, #308] @ (80103e4 ) 80102ae: 4293 cmp r3, r2 80102b0: d102 bne.n 80102b8 80102b2: f44f 4380 mov.w r3, #16384 @ 0x4000 80102b6: e01b b.n 80102f0 80102b8: f44f 2380 mov.w r3, #262144 @ 0x40000 80102bc: e018 b.n 80102f0 80102be: f44f 6380 mov.w r3, #1024 @ 0x400 80102c2: e015 b.n 80102f0 80102c4: 2340 movs r3, #64 @ 0x40 80102c6: e013 b.n 80102f0 80102c8: 2304 movs r3, #4 80102ca: e011 b.n 80102f0 80102cc: f04f 6380 mov.w r3, #67108864 @ 0x4000000 80102d0: e00e b.n 80102f0 80102d2: f44f 0380 mov.w r3, #4194304 @ 0x400000 80102d6: e00b b.n 80102f0 80102d8: f44f 2380 mov.w r3, #262144 @ 0x40000 80102dc: e008 b.n 80102f0 80102de: f44f 4380 mov.w r3, #16384 @ 0x4000 80102e2: e005 b.n 80102f0 80102e4: f44f 6380 mov.w r3, #1024 @ 0x400 80102e8: e002 b.n 80102f0 80102ea: 2340 movs r3, #64 @ 0x40 80102ec: e000 b.n 80102f0 80102ee: 2304 movs r3, #4 80102f0: 4a3d ldr r2, [pc, #244] @ (80103e8 ) 80102f2: 6053 str r3, [r2, #4] 80102f4: e057 b.n 80103a6 80102f6: 687b ldr r3, [r7, #4] 80102f8: 681b ldr r3, [r3, #0] 80102fa: 4a31 ldr r2, [pc, #196] @ (80103c0 ) 80102fc: 4293 cmp r3, r2 80102fe: d04f beq.n 80103a0 8010300: 687b ldr r3, [r7, #4] 8010302: 681b ldr r3, [r3, #0] 8010304: 4a2f ldr r2, [pc, #188] @ (80103c4 ) 8010306: 4293 cmp r3, r2 8010308: d048 beq.n 801039c 801030a: 687b ldr r3, [r7, #4] 801030c: 681b ldr r3, [r3, #0] 801030e: 4a2e ldr r2, [pc, #184] @ (80103c8 ) 8010310: 4293 cmp r3, r2 8010312: d040 beq.n 8010396 8010314: 687b ldr r3, [r7, #4] 8010316: 681b ldr r3, [r3, #0] 8010318: 4a2c ldr r2, [pc, #176] @ (80103cc ) 801031a: 4293 cmp r3, r2 801031c: d038 beq.n 8010390 801031e: 687b ldr r3, [r7, #4] 8010320: 681b ldr r3, [r3, #0] 8010322: 4a2b ldr r2, [pc, #172] @ (80103d0 ) 8010324: 4293 cmp r3, r2 8010326: d030 beq.n 801038a 8010328: 687b ldr r3, [r7, #4] 801032a: 681b ldr r3, [r3, #0] 801032c: 4a29 ldr r2, [pc, #164] @ (80103d4 ) 801032e: 4293 cmp r3, r2 8010330: d028 beq.n 8010384 8010332: 687b ldr r3, [r7, #4] 8010334: 681b ldr r3, [r3, #0] 8010336: 4a21 ldr r2, [pc, #132] @ (80103bc ) 8010338: 4293 cmp r3, r2 801033a: d020 beq.n 801037e 801033c: 687b ldr r3, [r7, #4] 801033e: 681b ldr r3, [r3, #0] 8010340: 4a25 ldr r2, [pc, #148] @ (80103d8 ) 8010342: 4293 cmp r3, r2 8010344: d019 beq.n 801037a 8010346: 687b ldr r3, [r7, #4] 8010348: 681b ldr r3, [r3, #0] 801034a: 4a24 ldr r2, [pc, #144] @ (80103dc ) 801034c: 4293 cmp r3, r2 801034e: d012 beq.n 8010376 8010350: 687b ldr r3, [r7, #4] 8010352: 681b ldr r3, [r3, #0] 8010354: 4a22 ldr r2, [pc, #136] @ (80103e0 ) 8010356: 4293 cmp r3, r2 8010358: d00a beq.n 8010370 801035a: 687b ldr r3, [r7, #4] 801035c: 681b ldr r3, [r3, #0] 801035e: 4a21 ldr r2, [pc, #132] @ (80103e4 ) 8010360: 4293 cmp r3, r2 8010362: d102 bne.n 801036a 8010364: f44f 4380 mov.w r3, #16384 @ 0x4000 8010368: e01b b.n 80103a2 801036a: f44f 2380 mov.w r3, #262144 @ 0x40000 801036e: e018 b.n 80103a2 8010370: f44f 6380 mov.w r3, #1024 @ 0x400 8010374: e015 b.n 80103a2 8010376: 2340 movs r3, #64 @ 0x40 8010378: e013 b.n 80103a2 801037a: 2304 movs r3, #4 801037c: e011 b.n 80103a2 801037e: f04f 6380 mov.w r3, #67108864 @ 0x4000000 8010382: e00e b.n 80103a2 8010384: f44f 0380 mov.w r3, #4194304 @ 0x400000 8010388: e00b b.n 80103a2 801038a: f44f 2380 mov.w r3, #262144 @ 0x40000 801038e: e008 b.n 80103a2 8010390: f44f 4380 mov.w r3, #16384 @ 0x4000 8010394: e005 b.n 80103a2 8010396: f44f 6380 mov.w r3, #1024 @ 0x400 801039a: e002 b.n 80103a2 801039c: 2340 movs r3, #64 @ 0x40 801039e: e000 b.n 80103a2 80103a0: 2304 movs r3, #4 80103a2: 4a12 ldr r2, [pc, #72] @ (80103ec ) 80103a4: 6053 str r3, [r2, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 80103a6: 687b ldr r3, [r7, #4] 80103a8: 6adb ldr r3, [r3, #44] @ 0x2c 80103aa: 2b00 cmp r3, #0 80103ac: f000 8136 beq.w 801061c { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 80103b0: 687b ldr r3, [r7, #4] 80103b2: 6adb ldr r3, [r3, #44] @ 0x2c 80103b4: 6878 ldr r0, [r7, #4] 80103b6: 4798 blx r3 if(hdma->XferHalfCpltCallback != NULL) 80103b8: e130 b.n 801061c 80103ba: bf00 nop 80103bc: 40020080 .word 0x40020080 80103c0: 40020008 .word 0x40020008 80103c4: 4002001c .word 0x4002001c 80103c8: 40020030 .word 0x40020030 80103cc: 40020044 .word 0x40020044 80103d0: 40020058 .word 0x40020058 80103d4: 4002006c .word 0x4002006c 80103d8: 40020408 .word 0x40020408 80103dc: 4002041c .word 0x4002041c 80103e0: 40020430 .word 0x40020430 80103e4: 40020444 .word 0x40020444 80103e8: 40020400 .word 0x40020400 80103ec: 40020000 .word 0x40020000 } } /* Transfer Complete Interrupt management ***********************************/ else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) 80103f0: 687b ldr r3, [r7, #4] 80103f2: 6c1b ldr r3, [r3, #64] @ 0x40 80103f4: 2202 movs r2, #2 80103f6: 409a lsls r2, r3 80103f8: 68fb ldr r3, [r7, #12] 80103fa: 4013 ands r3, r2 80103fc: 2b00 cmp r3, #0 80103fe: f000 80dd beq.w 80105bc 8010402: 68bb ldr r3, [r7, #8] 8010404: f003 0302 and.w r3, r3, #2 8010408: 2b00 cmp r3, #0 801040a: f000 80d7 beq.w 80105bc { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 801040e: 687b ldr r3, [r7, #4] 8010410: 681b ldr r3, [r3, #0] 8010412: 681b ldr r3, [r3, #0] 8010414: f003 0320 and.w r3, r3, #32 8010418: 2b00 cmp r3, #0 801041a: d10b bne.n 8010434 { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 801041c: 687b ldr r3, [r7, #4] 801041e: 681b ldr r3, [r3, #0] 8010420: 681a ldr r2, [r3, #0] 8010422: 687b ldr r3, [r7, #4] 8010424: 681b ldr r3, [r3, #0] 8010426: f022 020a bic.w r2, r2, #10 801042a: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 801042c: 687b ldr r3, [r7, #4] 801042e: 2201 movs r2, #1 8010430: f883 2021 strb.w r2, [r3, #33] @ 0x21 } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 8010434: 687b ldr r3, [r7, #4] 8010436: 681b ldr r3, [r3, #0] 8010438: 461a mov r2, r3 801043a: 4b7b ldr r3, [pc, #492] @ (8010628 ) 801043c: 429a cmp r2, r3 801043e: d958 bls.n 80104f2 8010440: 687b ldr r3, [r7, #4] 8010442: 681b ldr r3, [r3, #0] 8010444: 4a79 ldr r2, [pc, #484] @ (801062c ) 8010446: 4293 cmp r3, r2 8010448: d04f beq.n 80104ea 801044a: 687b ldr r3, [r7, #4] 801044c: 681b ldr r3, [r3, #0] 801044e: 4a78 ldr r2, [pc, #480] @ (8010630 ) 8010450: 4293 cmp r3, r2 8010452: d048 beq.n 80104e6 8010454: 687b ldr r3, [r7, #4] 8010456: 681b ldr r3, [r3, #0] 8010458: 4a76 ldr r2, [pc, #472] @ (8010634 ) 801045a: 4293 cmp r3, r2 801045c: d040 beq.n 80104e0 801045e: 687b ldr r3, [r7, #4] 8010460: 681b ldr r3, [r3, #0] 8010462: 4a75 ldr r2, [pc, #468] @ (8010638 ) 8010464: 4293 cmp r3, r2 8010466: d038 beq.n 80104da 8010468: 687b ldr r3, [r7, #4] 801046a: 681b ldr r3, [r3, #0] 801046c: 4a73 ldr r2, [pc, #460] @ (801063c ) 801046e: 4293 cmp r3, r2 8010470: d030 beq.n 80104d4 8010472: 687b ldr r3, [r7, #4] 8010474: 681b ldr r3, [r3, #0] 8010476: 4a72 ldr r2, [pc, #456] @ (8010640 ) 8010478: 4293 cmp r3, r2 801047a: d028 beq.n 80104ce 801047c: 687b ldr r3, [r7, #4] 801047e: 681b ldr r3, [r3, #0] 8010480: 4a69 ldr r2, [pc, #420] @ (8010628 ) 8010482: 4293 cmp r3, r2 8010484: d020 beq.n 80104c8 8010486: 687b ldr r3, [r7, #4] 8010488: 681b ldr r3, [r3, #0] 801048a: 4a6e ldr r2, [pc, #440] @ (8010644 ) 801048c: 4293 cmp r3, r2 801048e: d019 beq.n 80104c4 8010490: 687b ldr r3, [r7, #4] 8010492: 681b ldr r3, [r3, #0] 8010494: 4a6c ldr r2, [pc, #432] @ (8010648 ) 8010496: 4293 cmp r3, r2 8010498: d012 beq.n 80104c0 801049a: 687b ldr r3, [r7, #4] 801049c: 681b ldr r3, [r3, #0] 801049e: 4a6b ldr r2, [pc, #428] @ (801064c ) 80104a0: 4293 cmp r3, r2 80104a2: d00a beq.n 80104ba 80104a4: 687b ldr r3, [r7, #4] 80104a6: 681b ldr r3, [r3, #0] 80104a8: 4a69 ldr r2, [pc, #420] @ (8010650 ) 80104aa: 4293 cmp r3, r2 80104ac: d102 bne.n 80104b4 80104ae: f44f 5300 mov.w r3, #8192 @ 0x2000 80104b2: e01b b.n 80104ec 80104b4: f44f 3300 mov.w r3, #131072 @ 0x20000 80104b8: e018 b.n 80104ec 80104ba: f44f 7300 mov.w r3, #512 @ 0x200 80104be: e015 b.n 80104ec 80104c0: 2320 movs r3, #32 80104c2: e013 b.n 80104ec 80104c4: 2302 movs r3, #2 80104c6: e011 b.n 80104ec 80104c8: f04f 7300 mov.w r3, #33554432 @ 0x2000000 80104cc: e00e b.n 80104ec 80104ce: f44f 1300 mov.w r3, #2097152 @ 0x200000 80104d2: e00b b.n 80104ec 80104d4: f44f 3300 mov.w r3, #131072 @ 0x20000 80104d8: e008 b.n 80104ec 80104da: f44f 5300 mov.w r3, #8192 @ 0x2000 80104de: e005 b.n 80104ec 80104e0: f44f 7300 mov.w r3, #512 @ 0x200 80104e4: e002 b.n 80104ec 80104e6: 2320 movs r3, #32 80104e8: e000 b.n 80104ec 80104ea: 2302 movs r3, #2 80104ec: 4a59 ldr r2, [pc, #356] @ (8010654 ) 80104ee: 6053 str r3, [r2, #4] 80104f0: e057 b.n 80105a2 80104f2: 687b ldr r3, [r7, #4] 80104f4: 681b ldr r3, [r3, #0] 80104f6: 4a4d ldr r2, [pc, #308] @ (801062c ) 80104f8: 4293 cmp r3, r2 80104fa: d04f beq.n 801059c 80104fc: 687b ldr r3, [r7, #4] 80104fe: 681b ldr r3, [r3, #0] 8010500: 4a4b ldr r2, [pc, #300] @ (8010630 ) 8010502: 4293 cmp r3, r2 8010504: d048 beq.n 8010598 8010506: 687b ldr r3, [r7, #4] 8010508: 681b ldr r3, [r3, #0] 801050a: 4a4a ldr r2, [pc, #296] @ (8010634 ) 801050c: 4293 cmp r3, r2 801050e: d040 beq.n 8010592 8010510: 687b ldr r3, [r7, #4] 8010512: 681b ldr r3, [r3, #0] 8010514: 4a48 ldr r2, [pc, #288] @ (8010638 ) 8010516: 4293 cmp r3, r2 8010518: d038 beq.n 801058c 801051a: 687b ldr r3, [r7, #4] 801051c: 681b ldr r3, [r3, #0] 801051e: 4a47 ldr r2, [pc, #284] @ (801063c ) 8010520: 4293 cmp r3, r2 8010522: d030 beq.n 8010586 8010524: 687b ldr r3, [r7, #4] 8010526: 681b ldr r3, [r3, #0] 8010528: 4a45 ldr r2, [pc, #276] @ (8010640 ) 801052a: 4293 cmp r3, r2 801052c: d028 beq.n 8010580 801052e: 687b ldr r3, [r7, #4] 8010530: 681b ldr r3, [r3, #0] 8010532: 4a3d ldr r2, [pc, #244] @ (8010628 ) 8010534: 4293 cmp r3, r2 8010536: d020 beq.n 801057a 8010538: 687b ldr r3, [r7, #4] 801053a: 681b ldr r3, [r3, #0] 801053c: 4a41 ldr r2, [pc, #260] @ (8010644 ) 801053e: 4293 cmp r3, r2 8010540: d019 beq.n 8010576 8010542: 687b ldr r3, [r7, #4] 8010544: 681b ldr r3, [r3, #0] 8010546: 4a40 ldr r2, [pc, #256] @ (8010648 ) 8010548: 4293 cmp r3, r2 801054a: d012 beq.n 8010572 801054c: 687b ldr r3, [r7, #4] 801054e: 681b ldr r3, [r3, #0] 8010550: 4a3e ldr r2, [pc, #248] @ (801064c ) 8010552: 4293 cmp r3, r2 8010554: d00a beq.n 801056c 8010556: 687b ldr r3, [r7, #4] 8010558: 681b ldr r3, [r3, #0] 801055a: 4a3d ldr r2, [pc, #244] @ (8010650 ) 801055c: 4293 cmp r3, r2 801055e: d102 bne.n 8010566 8010560: f44f 5300 mov.w r3, #8192 @ 0x2000 8010564: e01b b.n 801059e 8010566: f44f 3300 mov.w r3, #131072 @ 0x20000 801056a: e018 b.n 801059e 801056c: f44f 7300 mov.w r3, #512 @ 0x200 8010570: e015 b.n 801059e 8010572: 2320 movs r3, #32 8010574: e013 b.n 801059e 8010576: 2302 movs r3, #2 8010578: e011 b.n 801059e 801057a: f04f 7300 mov.w r3, #33554432 @ 0x2000000 801057e: e00e b.n 801059e 8010580: f44f 1300 mov.w r3, #2097152 @ 0x200000 8010584: e00b b.n 801059e 8010586: f44f 3300 mov.w r3, #131072 @ 0x20000 801058a: e008 b.n 801059e 801058c: f44f 5300 mov.w r3, #8192 @ 0x2000 8010590: e005 b.n 801059e 8010592: f44f 7300 mov.w r3, #512 @ 0x200 8010596: e002 b.n 801059e 8010598: 2320 movs r3, #32 801059a: e000 b.n 801059e 801059c: 2302 movs r3, #2 801059e: 4a2e ldr r2, [pc, #184] @ (8010658 ) 80105a0: 6053 str r3, [r2, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 80105a2: 687b ldr r3, [r7, #4] 80105a4: 2200 movs r2, #0 80105a6: f883 2020 strb.w r2, [r3, #32] if(hdma->XferCpltCallback != NULL) 80105aa: 687b ldr r3, [r7, #4] 80105ac: 6a9b ldr r3, [r3, #40] @ 0x28 80105ae: 2b00 cmp r3, #0 80105b0: d034 beq.n 801061c { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 80105b2: 687b ldr r3, [r7, #4] 80105b4: 6a9b ldr r3, [r3, #40] @ 0x28 80105b6: 6878 ldr r0, [r7, #4] 80105b8: 4798 blx r3 if(hdma->XferCpltCallback != NULL) 80105ba: e02f b.n 801061c } } /* Transfer Error Interrupt management **************************************/ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) 80105bc: 687b ldr r3, [r7, #4] 80105be: 6c1b ldr r3, [r3, #64] @ 0x40 80105c0: 2208 movs r2, #8 80105c2: 409a lsls r2, r3 80105c4: 68fb ldr r3, [r7, #12] 80105c6: 4013 ands r3, r2 80105c8: 2b00 cmp r3, #0 80105ca: d028 beq.n 801061e 80105cc: 68bb ldr r3, [r7, #8] 80105ce: f003 0308 and.w r3, r3, #8 80105d2: 2b00 cmp r3, #0 80105d4: d023 beq.n 801061e { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80105d6: 687b ldr r3, [r7, #4] 80105d8: 681b ldr r3, [r3, #0] 80105da: 681a ldr r2, [r3, #0] 80105dc: 687b ldr r3, [r7, #4] 80105de: 681b ldr r3, [r3, #0] 80105e0: f022 020e bic.w r2, r2, #14 80105e4: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 80105e6: 687b ldr r3, [r7, #4] 80105e8: 6c1a ldr r2, [r3, #64] @ 0x40 80105ea: 687b ldr r3, [r7, #4] 80105ec: 6bdb ldr r3, [r3, #60] @ 0x3c 80105ee: 2101 movs r1, #1 80105f0: fa01 f202 lsl.w r2, r1, r2 80105f4: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 80105f6: 687b ldr r3, [r7, #4] 80105f8: 2201 movs r2, #1 80105fa: 639a str r2, [r3, #56] @ 0x38 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80105fc: 687b ldr r3, [r7, #4] 80105fe: 2201 movs r2, #1 8010600: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8010604: 687b ldr r3, [r7, #4] 8010606: 2200 movs r2, #0 8010608: f883 2020 strb.w r2, [r3, #32] if (hdma->XferErrorCallback != NULL) 801060c: 687b ldr r3, [r7, #4] 801060e: 6b1b ldr r3, [r3, #48] @ 0x30 8010610: 2b00 cmp r3, #0 8010612: d004 beq.n 801061e { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8010614: 687b ldr r3, [r7, #4] 8010616: 6b1b ldr r3, [r3, #48] @ 0x30 8010618: 6878 ldr r0, [r7, #4] 801061a: 4798 blx r3 } } return; 801061c: bf00 nop 801061e: bf00 nop } 8010620: 3710 adds r7, #16 8010622: 46bd mov sp, r7 8010624: bd80 pop {r7, pc} 8010626: bf00 nop 8010628: 40020080 .word 0x40020080 801062c: 40020008 .word 0x40020008 8010630: 4002001c .word 0x4002001c 8010634: 40020030 .word 0x40020030 8010638: 40020044 .word 0x40020044 801063c: 40020058 .word 0x40020058 8010640: 4002006c .word 0x4002006c 8010644: 40020408 .word 0x40020408 8010648: 4002041c .word 0x4002041c 801064c: 40020430 .word 0x40020430 8010650: 40020444 .word 0x40020444 8010654: 40020400 .word 0x40020400 8010658: 40020000 .word 0x40020000 0801065c : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval DMA Error Code */ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { 801065c: b480 push {r7} 801065e: b083 sub sp, #12 8010660: af00 add r7, sp, #0 8010662: 6078 str r0, [r7, #4] return hdma->ErrorCode; 8010664: 687b ldr r3, [r7, #4] 8010666: 6b9b ldr r3, [r3, #56] @ 0x38 } 8010668: 4618 mov r0, r3 801066a: 370c adds r7, #12 801066c: 46bd mov sp, r7 801066e: bc80 pop {r7} 8010670: 4770 bx lr 08010672 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8010672: b480 push {r7} 8010674: b085 sub sp, #20 8010676: af00 add r7, sp, #0 8010678: 60f8 str r0, [r7, #12] 801067a: 60b9 str r1, [r7, #8] 801067c: 607a str r2, [r7, #4] 801067e: 603b str r3, [r7, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8010680: 68fb ldr r3, [r7, #12] 8010682: 6c1a ldr r2, [r3, #64] @ 0x40 8010684: 68fb ldr r3, [r7, #12] 8010686: 6bdb ldr r3, [r3, #60] @ 0x3c 8010688: 2101 movs r1, #1 801068a: fa01 f202 lsl.w r2, r1, r2 801068e: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 8010690: 68fb ldr r3, [r7, #12] 8010692: 681b ldr r3, [r3, #0] 8010694: 683a ldr r2, [r7, #0] 8010696: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8010698: 68fb ldr r3, [r7, #12] 801069a: 685b ldr r3, [r3, #4] 801069c: 2b10 cmp r3, #16 801069e: d108 bne.n 80106b2 { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 80106a0: 68fb ldr r3, [r7, #12] 80106a2: 681b ldr r3, [r3, #0] 80106a4: 687a ldr r2, [r7, #4] 80106a6: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; 80106a8: 68fb ldr r3, [r7, #12] 80106aa: 681b ldr r3, [r3, #0] 80106ac: 68ba ldr r2, [r7, #8] 80106ae: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } 80106b0: e007 b.n 80106c2 hdma->Instance->CPAR = SrcAddress; 80106b2: 68fb ldr r3, [r7, #12] 80106b4: 681b ldr r3, [r3, #0] 80106b6: 68ba ldr r2, [r7, #8] 80106b8: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; 80106ba: 68fb ldr r3, [r7, #12] 80106bc: 681b ldr r3, [r3, #0] 80106be: 687a ldr r2, [r7, #4] 80106c0: 60da str r2, [r3, #12] } 80106c2: bf00 nop 80106c4: 3714 adds r7, #20 80106c6: 46bd mov sp, r7 80106c8: bc80 pop {r7} 80106ca: 4770 bx lr 080106cc : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80106cc: b480 push {r7} 80106ce: b08b sub sp, #44 @ 0x2c 80106d0: af00 add r7, sp, #0 80106d2: 6078 str r0, [r7, #4] 80106d4: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 80106d6: 2300 movs r3, #0 80106d8: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 80106da: 2300 movs r3, #0 80106dc: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 80106de: e169 b.n 80109b4 { /* Get the IO position */ ioposition = (0x01uL << position); 80106e0: 2201 movs r2, #1 80106e2: 6a7b ldr r3, [r7, #36] @ 0x24 80106e4: fa02 f303 lsl.w r3, r2, r3 80106e8: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80106ea: 683b ldr r3, [r7, #0] 80106ec: 681b ldr r3, [r3, #0] 80106ee: 69fa ldr r2, [r7, #28] 80106f0: 4013 ands r3, r2 80106f2: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 80106f4: 69ba ldr r2, [r7, #24] 80106f6: 69fb ldr r3, [r7, #28] 80106f8: 429a cmp r2, r3 80106fa: f040 8158 bne.w 80109ae { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 80106fe: 683b ldr r3, [r7, #0] 8010700: 685b ldr r3, [r3, #4] 8010702: 4a9a ldr r2, [pc, #616] @ (801096c ) 8010704: 4293 cmp r3, r2 8010706: d05e beq.n 80107c6 8010708: 4a98 ldr r2, [pc, #608] @ (801096c ) 801070a: 4293 cmp r3, r2 801070c: d875 bhi.n 80107fa 801070e: 4a98 ldr r2, [pc, #608] @ (8010970 ) 8010710: 4293 cmp r3, r2 8010712: d058 beq.n 80107c6 8010714: 4a96 ldr r2, [pc, #600] @ (8010970 ) 8010716: 4293 cmp r3, r2 8010718: d86f bhi.n 80107fa 801071a: 4a96 ldr r2, [pc, #600] @ (8010974 ) 801071c: 4293 cmp r3, r2 801071e: d052 beq.n 80107c6 8010720: 4a94 ldr r2, [pc, #592] @ (8010974 ) 8010722: 4293 cmp r3, r2 8010724: d869 bhi.n 80107fa 8010726: 4a94 ldr r2, [pc, #592] @ (8010978 ) 8010728: 4293 cmp r3, r2 801072a: d04c beq.n 80107c6 801072c: 4a92 ldr r2, [pc, #584] @ (8010978 ) 801072e: 4293 cmp r3, r2 8010730: d863 bhi.n 80107fa 8010732: 4a92 ldr r2, [pc, #584] @ (801097c ) 8010734: 4293 cmp r3, r2 8010736: d046 beq.n 80107c6 8010738: 4a90 ldr r2, [pc, #576] @ (801097c ) 801073a: 4293 cmp r3, r2 801073c: d85d bhi.n 80107fa 801073e: 2b12 cmp r3, #18 8010740: d82a bhi.n 8010798 8010742: 2b12 cmp r3, #18 8010744: d859 bhi.n 80107fa 8010746: a201 add r2, pc, #4 @ (adr r2, 801074c ) 8010748: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801074c: 080107c7 .word 0x080107c7 8010750: 080107a1 .word 0x080107a1 8010754: 080107b3 .word 0x080107b3 8010758: 080107f5 .word 0x080107f5 801075c: 080107fb .word 0x080107fb 8010760: 080107fb .word 0x080107fb 8010764: 080107fb .word 0x080107fb 8010768: 080107fb .word 0x080107fb 801076c: 080107fb .word 0x080107fb 8010770: 080107fb .word 0x080107fb 8010774: 080107fb .word 0x080107fb 8010778: 080107fb .word 0x080107fb 801077c: 080107fb .word 0x080107fb 8010780: 080107fb .word 0x080107fb 8010784: 080107fb .word 0x080107fb 8010788: 080107fb .word 0x080107fb 801078c: 080107fb .word 0x080107fb 8010790: 080107a9 .word 0x080107a9 8010794: 080107bd .word 0x080107bd 8010798: 4a79 ldr r2, [pc, #484] @ (8010980 ) 801079a: 4293 cmp r3, r2 801079c: d013 beq.n 80107c6 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 801079e: e02c b.n 80107fa config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 80107a0: 683b ldr r3, [r7, #0] 80107a2: 68db ldr r3, [r3, #12] 80107a4: 623b str r3, [r7, #32] break; 80107a6: e029 b.n 80107fc config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 80107a8: 683b ldr r3, [r7, #0] 80107aa: 68db ldr r3, [r3, #12] 80107ac: 3304 adds r3, #4 80107ae: 623b str r3, [r7, #32] break; 80107b0: e024 b.n 80107fc config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 80107b2: 683b ldr r3, [r7, #0] 80107b4: 68db ldr r3, [r3, #12] 80107b6: 3308 adds r3, #8 80107b8: 623b str r3, [r7, #32] break; 80107ba: e01f b.n 80107fc config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 80107bc: 683b ldr r3, [r7, #0] 80107be: 68db ldr r3, [r3, #12] 80107c0: 330c adds r3, #12 80107c2: 623b str r3, [r7, #32] break; 80107c4: e01a b.n 80107fc if (GPIO_Init->Pull == GPIO_NOPULL) 80107c6: 683b ldr r3, [r7, #0] 80107c8: 689b ldr r3, [r3, #8] 80107ca: 2b00 cmp r3, #0 80107cc: d102 bne.n 80107d4 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 80107ce: 2304 movs r3, #4 80107d0: 623b str r3, [r7, #32] break; 80107d2: e013 b.n 80107fc else if (GPIO_Init->Pull == GPIO_PULLUP) 80107d4: 683b ldr r3, [r7, #0] 80107d6: 689b ldr r3, [r3, #8] 80107d8: 2b01 cmp r3, #1 80107da: d105 bne.n 80107e8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80107dc: 2308 movs r3, #8 80107de: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 80107e0: 687b ldr r3, [r7, #4] 80107e2: 69fa ldr r2, [r7, #28] 80107e4: 611a str r2, [r3, #16] break; 80107e6: e009 b.n 80107fc config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80107e8: 2308 movs r3, #8 80107ea: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 80107ec: 687b ldr r3, [r7, #4] 80107ee: 69fa ldr r2, [r7, #28] 80107f0: 615a str r2, [r3, #20] break; 80107f2: e003 b.n 80107fc config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 80107f4: 2300 movs r3, #0 80107f6: 623b str r3, [r7, #32] break; 80107f8: e000 b.n 80107fc break; 80107fa: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 80107fc: 69bb ldr r3, [r7, #24] 80107fe: 2bff cmp r3, #255 @ 0xff 8010800: d801 bhi.n 8010806 8010802: 687b ldr r3, [r7, #4] 8010804: e001 b.n 801080a 8010806: 687b ldr r3, [r7, #4] 8010808: 3304 adds r3, #4 801080a: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 801080c: 69bb ldr r3, [r7, #24] 801080e: 2bff cmp r3, #255 @ 0xff 8010810: d802 bhi.n 8010818 8010812: 6a7b ldr r3, [r7, #36] @ 0x24 8010814: 009b lsls r3, r3, #2 8010816: e002 b.n 801081e 8010818: 6a7b ldr r3, [r7, #36] @ 0x24 801081a: 3b08 subs r3, #8 801081c: 009b lsls r3, r3, #2 801081e: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8010820: 697b ldr r3, [r7, #20] 8010822: 681a ldr r2, [r3, #0] 8010824: 210f movs r1, #15 8010826: 693b ldr r3, [r7, #16] 8010828: fa01 f303 lsl.w r3, r1, r3 801082c: 43db mvns r3, r3 801082e: 401a ands r2, r3 8010830: 6a39 ldr r1, [r7, #32] 8010832: 693b ldr r3, [r7, #16] 8010834: fa01 f303 lsl.w r3, r1, r3 8010838: 431a orrs r2, r3 801083a: 697b ldr r3, [r7, #20] 801083c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 801083e: 683b ldr r3, [r7, #0] 8010840: 685b ldr r3, [r3, #4] 8010842: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010846: 2b00 cmp r3, #0 8010848: f000 80b1 beq.w 80109ae { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 801084c: 4b4d ldr r3, [pc, #308] @ (8010984 ) 801084e: 699b ldr r3, [r3, #24] 8010850: 4a4c ldr r2, [pc, #304] @ (8010984 ) 8010852: f043 0301 orr.w r3, r3, #1 8010856: 6193 str r3, [r2, #24] 8010858: 4b4a ldr r3, [pc, #296] @ (8010984 ) 801085a: 699b ldr r3, [r3, #24] 801085c: f003 0301 and.w r3, r3, #1 8010860: 60bb str r3, [r7, #8] 8010862: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8010864: 4a48 ldr r2, [pc, #288] @ (8010988 ) 8010866: 6a7b ldr r3, [r7, #36] @ 0x24 8010868: 089b lsrs r3, r3, #2 801086a: 3302 adds r3, #2 801086c: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8010870: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8010872: 6a7b ldr r3, [r7, #36] @ 0x24 8010874: f003 0303 and.w r3, r3, #3 8010878: 009b lsls r3, r3, #2 801087a: 220f movs r2, #15 801087c: fa02 f303 lsl.w r3, r2, r3 8010880: 43db mvns r3, r3 8010882: 68fa ldr r2, [r7, #12] 8010884: 4013 ands r3, r2 8010886: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8010888: 687b ldr r3, [r7, #4] 801088a: 4a40 ldr r2, [pc, #256] @ (801098c ) 801088c: 4293 cmp r3, r2 801088e: d013 beq.n 80108b8 8010890: 687b ldr r3, [r7, #4] 8010892: 4a3f ldr r2, [pc, #252] @ (8010990 ) 8010894: 4293 cmp r3, r2 8010896: d00d beq.n 80108b4 8010898: 687b ldr r3, [r7, #4] 801089a: 4a3e ldr r2, [pc, #248] @ (8010994 ) 801089c: 4293 cmp r3, r2 801089e: d007 beq.n 80108b0 80108a0: 687b ldr r3, [r7, #4] 80108a2: 4a3d ldr r2, [pc, #244] @ (8010998 ) 80108a4: 4293 cmp r3, r2 80108a6: d101 bne.n 80108ac 80108a8: 2303 movs r3, #3 80108aa: e006 b.n 80108ba 80108ac: 2304 movs r3, #4 80108ae: e004 b.n 80108ba 80108b0: 2302 movs r3, #2 80108b2: e002 b.n 80108ba 80108b4: 2301 movs r3, #1 80108b6: e000 b.n 80108ba 80108b8: 2300 movs r3, #0 80108ba: 6a7a ldr r2, [r7, #36] @ 0x24 80108bc: f002 0203 and.w r2, r2, #3 80108c0: 0092 lsls r2, r2, #2 80108c2: 4093 lsls r3, r2 80108c4: 68fa ldr r2, [r7, #12] 80108c6: 4313 orrs r3, r2 80108c8: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 80108ca: 492f ldr r1, [pc, #188] @ (8010988 ) 80108cc: 6a7b ldr r3, [r7, #36] @ 0x24 80108ce: 089b lsrs r3, r3, #2 80108d0: 3302 adds r3, #2 80108d2: 68fa ldr r2, [r7, #12] 80108d4: f841 2023 str.w r2, [r1, r3, lsl #2] /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 80108d8: 683b ldr r3, [r7, #0] 80108da: 685b ldr r3, [r3, #4] 80108dc: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80108e0: 2b00 cmp r3, #0 80108e2: d006 beq.n 80108f2 { SET_BIT(EXTI->RTSR, iocurrent); 80108e4: 4b2d ldr r3, [pc, #180] @ (801099c ) 80108e6: 689a ldr r2, [r3, #8] 80108e8: 492c ldr r1, [pc, #176] @ (801099c ) 80108ea: 69bb ldr r3, [r7, #24] 80108ec: 4313 orrs r3, r2 80108ee: 608b str r3, [r1, #8] 80108f0: e006 b.n 8010900 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 80108f2: 4b2a ldr r3, [pc, #168] @ (801099c ) 80108f4: 689a ldr r2, [r3, #8] 80108f6: 69bb ldr r3, [r7, #24] 80108f8: 43db mvns r3, r3 80108fa: 4928 ldr r1, [pc, #160] @ (801099c ) 80108fc: 4013 ands r3, r2 80108fe: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8010900: 683b ldr r3, [r7, #0] 8010902: 685b ldr r3, [r3, #4] 8010904: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8010908: 2b00 cmp r3, #0 801090a: d006 beq.n 801091a { SET_BIT(EXTI->FTSR, iocurrent); 801090c: 4b23 ldr r3, [pc, #140] @ (801099c ) 801090e: 68da ldr r2, [r3, #12] 8010910: 4922 ldr r1, [pc, #136] @ (801099c ) 8010912: 69bb ldr r3, [r7, #24] 8010914: 4313 orrs r3, r2 8010916: 60cb str r3, [r1, #12] 8010918: e006 b.n 8010928 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 801091a: 4b20 ldr r3, [pc, #128] @ (801099c ) 801091c: 68da ldr r2, [r3, #12] 801091e: 69bb ldr r3, [r7, #24] 8010920: 43db mvns r3, r3 8010922: 491e ldr r1, [pc, #120] @ (801099c ) 8010924: 4013 ands r3, r2 8010926: 60cb str r3, [r1, #12] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8010928: 683b ldr r3, [r7, #0] 801092a: 685b ldr r3, [r3, #4] 801092c: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010930: 2b00 cmp r3, #0 8010932: d006 beq.n 8010942 { SET_BIT(EXTI->EMR, iocurrent); 8010934: 4b19 ldr r3, [pc, #100] @ (801099c ) 8010936: 685a ldr r2, [r3, #4] 8010938: 4918 ldr r1, [pc, #96] @ (801099c ) 801093a: 69bb ldr r3, [r7, #24] 801093c: 4313 orrs r3, r2 801093e: 604b str r3, [r1, #4] 8010940: e006 b.n 8010950 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8010942: 4b16 ldr r3, [pc, #88] @ (801099c ) 8010944: 685a ldr r2, [r3, #4] 8010946: 69bb ldr r3, [r7, #24] 8010948: 43db mvns r3, r3 801094a: 4914 ldr r1, [pc, #80] @ (801099c ) 801094c: 4013 ands r3, r2 801094e: 604b str r3, [r1, #4] } /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8010950: 683b ldr r3, [r7, #0] 8010952: 685b ldr r3, [r3, #4] 8010954: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010958: 2b00 cmp r3, #0 801095a: d021 beq.n 80109a0 { SET_BIT(EXTI->IMR, iocurrent); 801095c: 4b0f ldr r3, [pc, #60] @ (801099c ) 801095e: 681a ldr r2, [r3, #0] 8010960: 490e ldr r1, [pc, #56] @ (801099c ) 8010962: 69bb ldr r3, [r7, #24] 8010964: 4313 orrs r3, r2 8010966: 600b str r3, [r1, #0] 8010968: e021 b.n 80109ae 801096a: bf00 nop 801096c: 10320000 .word 0x10320000 8010970: 10310000 .word 0x10310000 8010974: 10220000 .word 0x10220000 8010978: 10210000 .word 0x10210000 801097c: 10120000 .word 0x10120000 8010980: 10110000 .word 0x10110000 8010984: 40021000 .word 0x40021000 8010988: 40010000 .word 0x40010000 801098c: 40010800 .word 0x40010800 8010990: 40010c00 .word 0x40010c00 8010994: 40011000 .word 0x40011000 8010998: 40011400 .word 0x40011400 801099c: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 80109a0: 4b0b ldr r3, [pc, #44] @ (80109d0 ) 80109a2: 681a ldr r2, [r3, #0] 80109a4: 69bb ldr r3, [r7, #24] 80109a6: 43db mvns r3, r3 80109a8: 4909 ldr r1, [pc, #36] @ (80109d0 ) 80109aa: 4013 ands r3, r2 80109ac: 600b str r3, [r1, #0] } } } position++; 80109ae: 6a7b ldr r3, [r7, #36] @ 0x24 80109b0: 3301 adds r3, #1 80109b2: 627b str r3, [r7, #36] @ 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 80109b4: 683b ldr r3, [r7, #0] 80109b6: 681a ldr r2, [r3, #0] 80109b8: 6a7b ldr r3, [r7, #36] @ 0x24 80109ba: fa22 f303 lsr.w r3, r2, r3 80109be: 2b00 cmp r3, #0 80109c0: f47f ae8e bne.w 80106e0 } } 80109c4: bf00 nop 80109c6: bf00 nop 80109c8: 372c adds r7, #44 @ 0x2c 80109ca: 46bd mov sp, r7 80109cc: bc80 pop {r7} 80109ce: 4770 bx lr 80109d0: 40010400 .word 0x40010400 080109d4 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 80109d4: b480 push {r7} 80109d6: b085 sub sp, #20 80109d8: af00 add r7, sp, #0 80109da: 6078 str r0, [r7, #4] 80109dc: 460b mov r3, r1 80109de: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 80109e0: 687b ldr r3, [r7, #4] 80109e2: 689a ldr r2, [r3, #8] 80109e4: 887b ldrh r3, [r7, #2] 80109e6: 4013 ands r3, r2 80109e8: 2b00 cmp r3, #0 80109ea: d002 beq.n 80109f2 { bitstatus = GPIO_PIN_SET; 80109ec: 2301 movs r3, #1 80109ee: 73fb strb r3, [r7, #15] 80109f0: e001 b.n 80109f6 } else { bitstatus = GPIO_PIN_RESET; 80109f2: 2300 movs r3, #0 80109f4: 73fb strb r3, [r7, #15] } return bitstatus; 80109f6: 7bfb ldrb r3, [r7, #15] } 80109f8: 4618 mov r0, r3 80109fa: 3714 adds r7, #20 80109fc: 46bd mov sp, r7 80109fe: bc80 pop {r7} 8010a00: 4770 bx lr 08010a02 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8010a02: b480 push {r7} 8010a04: b083 sub sp, #12 8010a06: af00 add r7, sp, #0 8010a08: 6078 str r0, [r7, #4] 8010a0a: 460b mov r3, r1 8010a0c: 807b strh r3, [r7, #2] 8010a0e: 4613 mov r3, r2 8010a10: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8010a12: 787b ldrb r3, [r7, #1] 8010a14: 2b00 cmp r3, #0 8010a16: d003 beq.n 8010a20 { GPIOx->BSRR = GPIO_Pin; 8010a18: 887a ldrh r2, [r7, #2] 8010a1a: 687b ldr r3, [r7, #4] 8010a1c: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8010a1e: e003 b.n 8010a28 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8010a20: 887b ldrh r3, [r7, #2] 8010a22: 041a lsls r2, r3, #16 8010a24: 687b ldr r3, [r7, #4] 8010a26: 611a str r2, [r3, #16] } 8010a28: bf00 nop 8010a2a: 370c adds r7, #12 8010a2c: 46bd mov sp, r7 8010a2e: bc80 pop {r7} 8010a30: 4770 bx lr ... 08010a34 : * @note If the HSE divided by 128 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 8010a34: b480 push {r7} 8010a36: af00 add r7, sp, #0 /* Enable access to RTC and backup registers */ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 8010a38: 4b03 ldr r3, [pc, #12] @ (8010a48 ) 8010a3a: 2201 movs r2, #1 8010a3c: 601a str r2, [r3, #0] } 8010a3e: bf00 nop 8010a40: 46bd mov sp, r7 8010a42: bc80 pop {r7} 8010a44: 4770 bx lr 8010a46: bf00 nop 8010a48: 420e0020 .word 0x420e0020 08010a4c : * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval HAL_StatusTypeDef */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { 8010a4c: b580 push {r7, lr} 8010a4e: b082 sub sp, #8 8010a50: af00 add r7, sp, #0 uint32_t tickstart; /* Get Start Tick */ tickstart = HAL_GetTick(); 8010a52: f7fd fc3f bl 800e2d4 8010a56: 6078 str r0, [r7, #4] /* Set HSION bit */ SET_BIT(RCC->CR, RCC_CR_HSION); 8010a58: 4b60 ldr r3, [pc, #384] @ (8010bdc ) 8010a5a: 681b ldr r3, [r3, #0] 8010a5c: 4a5f ldr r2, [pc, #380] @ (8010bdc ) 8010a5e: f043 0301 orr.w r3, r3, #1 8010a62: 6013 str r3, [r2, #0] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 8010a64: e008 b.n 8010a78 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8010a66: f7fd fc35 bl 800e2d4 8010a6a: 4602 mov r2, r0 8010a6c: 687b ldr r3, [r7, #4] 8010a6e: 1ad3 subs r3, r2, r3 8010a70: 2b02 cmp r3, #2 8010a72: d901 bls.n 8010a78 { return HAL_TIMEOUT; 8010a74: 2303 movs r3, #3 8010a76: e0ac b.n 8010bd2 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 8010a78: 4b58 ldr r3, [pc, #352] @ (8010bdc ) 8010a7a: 681b ldr r3, [r3, #0] 8010a7c: f003 0302 and.w r3, r3, #2 8010a80: 2b00 cmp r3, #0 8010a82: d0f0 beq.n 8010a66 } } /* Set HSITRIM bits to the reset value */ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); 8010a84: 4b55 ldr r3, [pc, #340] @ (8010bdc ) 8010a86: 681b ldr r3, [r3, #0] 8010a88: f023 03f8 bic.w r3, r3, #248 @ 0xf8 8010a8c: 4a53 ldr r2, [pc, #332] @ (8010bdc ) 8010a8e: f043 0380 orr.w r3, r3, #128 @ 0x80 8010a92: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010a94: f7fd fc1e bl 800e2d4 8010a98: 6078 str r0, [r7, #4] /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); 8010a9a: 4b50 ldr r3, [pc, #320] @ (8010bdc ) 8010a9c: 2200 movs r2, #0 8010a9e: 605a str r2, [r3, #4] /* Wait till clock switch is ready */ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 8010aa0: e00a b.n 8010ab8 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8010aa2: f7fd fc17 bl 800e2d4 8010aa6: 4602 mov r2, r0 8010aa8: 687b ldr r3, [r7, #4] 8010aaa: 1ad3 subs r3, r2, r3 8010aac: f241 3288 movw r2, #5000 @ 0x1388 8010ab0: 4293 cmp r3, r2 8010ab2: d901 bls.n 8010ab8 { return HAL_TIMEOUT; 8010ab4: 2303 movs r3, #3 8010ab6: e08c b.n 8010bd2 while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 8010ab8: 4b48 ldr r3, [pc, #288] @ (8010bdc ) 8010aba: 685b ldr r3, [r3, #4] 8010abc: f003 030c and.w r3, r3, #12 8010ac0: 2b00 cmp r3, #0 8010ac2: d1ee bne.n 8010aa2 } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; 8010ac4: 4b46 ldr r3, [pc, #280] @ (8010be0 ) 8010ac6: 4a47 ldr r2, [pc, #284] @ (8010be4 ) 8010ac8: 601a str r2, [r3, #0] /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 8010aca: 4b47 ldr r3, [pc, #284] @ (8010be8 ) 8010acc: 681b ldr r3, [r3, #0] 8010ace: 4618 mov r0, r3 8010ad0: f7fd fbbe bl 800e250 8010ad4: 4603 mov r3, r0 8010ad6: 2b00 cmp r3, #0 8010ad8: d001 beq.n 8010ade { return HAL_ERROR; 8010ada: 2301 movs r3, #1 8010adc: e079 b.n 8010bd2 } /* Get Start Tick */ tickstart = HAL_GetTick(); 8010ade: f7fd fbf9 bl 800e2d4 8010ae2: 6078 str r0, [r7, #4] /* Second step is to clear PLLON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 8010ae4: 4b3d ldr r3, [pc, #244] @ (8010bdc ) 8010ae6: 681b ldr r3, [r3, #0] 8010ae8: 4a3c ldr r2, [pc, #240] @ (8010bdc ) 8010aea: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 8010aee: 6013 str r3, [r2, #0] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 8010af0: e008 b.n 8010b04 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8010af2: f7fd fbef bl 800e2d4 8010af6: 4602 mov r2, r0 8010af8: 687b ldr r3, [r7, #4] 8010afa: 1ad3 subs r3, r2, r3 8010afc: 2b02 cmp r3, #2 8010afe: d901 bls.n 8010b04 { return HAL_TIMEOUT; 8010b00: 2303 movs r3, #3 8010b02: e066 b.n 8010bd2 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 8010b04: 4b35 ldr r3, [pc, #212] @ (8010bdc ) 8010b06: 681b ldr r3, [r3, #0] 8010b08: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8010b0c: 2b00 cmp r3, #0 8010b0e: d1f0 bne.n 8010af2 } } /* Ensure to reset PLLSRC and PLLMUL bits */ CLEAR_REG(RCC->CFGR); 8010b10: 4b32 ldr r3, [pc, #200] @ (8010bdc ) 8010b12: 2200 movs r2, #0 8010b14: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010b16: f7fd fbdd bl 800e2d4 8010b1a: 6078 str r0, [r7, #4] /* Reset HSEON & CSSON bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON); 8010b1c: 4b2f ldr r3, [pc, #188] @ (8010bdc ) 8010b1e: 681b ldr r3, [r3, #0] 8010b20: 4a2e ldr r2, [pc, #184] @ (8010bdc ) 8010b22: f423 2310 bic.w r3, r3, #589824 @ 0x90000 8010b26: 6013 str r3, [r2, #0] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 8010b28: e008 b.n 8010b3c { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8010b2a: f7fd fbd3 bl 800e2d4 8010b2e: 4602 mov r2, r0 8010b30: 687b ldr r3, [r7, #4] 8010b32: 1ad3 subs r3, r2, r3 8010b34: 2b64 cmp r3, #100 @ 0x64 8010b36: d901 bls.n 8010b3c { return HAL_TIMEOUT; 8010b38: 2303 movs r3, #3 8010b3a: e04a b.n 8010bd2 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 8010b3c: 4b27 ldr r3, [pc, #156] @ (8010bdc ) 8010b3e: 681b ldr r3, [r3, #0] 8010b40: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010b44: 2b00 cmp r3, #0 8010b46: d1f0 bne.n 8010b2a } } /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 8010b48: 4b24 ldr r3, [pc, #144] @ (8010bdc ) 8010b4a: 681b ldr r3, [r3, #0] 8010b4c: 4a23 ldr r2, [pc, #140] @ (8010bdc ) 8010b4e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010b52: 6013 str r3, [r2, #0] #if defined(RCC_PLL2_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 8010b54: f7fd fbbe bl 800e2d4 8010b58: 6078 str r0, [r7, #4] /* Clear PLL2ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); 8010b5a: 4b20 ldr r3, [pc, #128] @ (8010bdc ) 8010b5c: 681b ldr r3, [r3, #0] 8010b5e: 4a1f ldr r2, [pc, #124] @ (8010bdc ) 8010b60: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8010b64: 6013 str r3, [r2, #0] /* Wait till PLL2 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 8010b66: e008 b.n 8010b7a { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8010b68: f7fd fbb4 bl 800e2d4 8010b6c: 4602 mov r2, r0 8010b6e: 687b ldr r3, [r7, #4] 8010b70: 1ad3 subs r3, r2, r3 8010b72: 2b64 cmp r3, #100 @ 0x64 8010b74: d901 bls.n 8010b7a { return HAL_TIMEOUT; 8010b76: 2303 movs r3, #3 8010b78: e02b b.n 8010bd2 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 8010b7a: 4b18 ldr r3, [pc, #96] @ (8010bdc ) 8010b7c: 681b ldr r3, [r3, #0] 8010b7e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8010b82: 2b00 cmp r3, #0 8010b84: d1f0 bne.n 8010b68 } #endif /* RCC_PLL2_SUPPORT */ #if defined(RCC_PLLI2S_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 8010b86: f7fd fba5 bl 800e2d4 8010b8a: 6078 str r0, [r7, #4] /* Clear PLL3ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); 8010b8c: 4b13 ldr r3, [pc, #76] @ (8010bdc ) 8010b8e: 681b ldr r3, [r3, #0] 8010b90: 4a12 ldr r2, [pc, #72] @ (8010bdc ) 8010b92: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8010b96: 6013 str r3, [r2, #0] /* Wait till PLL3 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 8010b98: e008 b.n 8010bac { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8010b9a: f7fd fb9b bl 800e2d4 8010b9e: 4602 mov r2, r0 8010ba0: 687b ldr r3, [r7, #4] 8010ba2: 1ad3 subs r3, r2, r3 8010ba4: 2b64 cmp r3, #100 @ 0x64 8010ba6: d901 bls.n 8010bac { return HAL_TIMEOUT; 8010ba8: 2303 movs r3, #3 8010baa: e012 b.n 8010bd2 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 8010bac: 4b0b ldr r3, [pc, #44] @ (8010bdc ) 8010bae: 681b ldr r3, [r3, #0] 8010bb0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8010bb4: 2b00 cmp r3, #0 8010bb6: d1f0 bne.n 8010b9a } #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_CFGR2_PREDIV1) /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); 8010bb8: 4b08 ldr r3, [pc, #32] @ (8010bdc ) 8010bba: 2200 movs r2, #0 8010bbc: 62da str r2, [r3, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1 */ /* Reset all CSR flags */ SET_BIT(RCC->CSR, RCC_CSR_RMVF); 8010bbe: 4b07 ldr r3, [pc, #28] @ (8010bdc ) 8010bc0: 6a5b ldr r3, [r3, #36] @ 0x24 8010bc2: 4a06 ldr r2, [pc, #24] @ (8010bdc ) 8010bc4: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8010bc8: 6253 str r3, [r2, #36] @ 0x24 /* Disable all interrupts */ CLEAR_REG(RCC->CIR); 8010bca: 4b04 ldr r3, [pc, #16] @ (8010bdc ) 8010bcc: 2200 movs r2, #0 8010bce: 609a str r2, [r3, #8] return HAL_OK; 8010bd0: 2300 movs r3, #0 } 8010bd2: 4618 mov r0, r3 8010bd4: 3708 adds r7, #8 8010bd6: 46bd mov sp, r7 8010bd8: bd80 pop {r7, pc} 8010bda: bf00 nop 8010bdc: 40021000 .word 0x40021000 8010be0: 20000084 .word 0x20000084 8010be4: 007a1200 .word 0x007a1200 8010be8: 20000088 .word 0x20000088 08010bec : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8010bec: b580 push {r7, lr} 8010bee: b086 sub sp, #24 8010bf0: af00 add r7, sp, #0 8010bf2: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8010bf4: 687b ldr r3, [r7, #4] 8010bf6: 2b00 cmp r3, #0 8010bf8: d101 bne.n 8010bfe { return HAL_ERROR; 8010bfa: 2301 movs r3, #1 8010bfc: e304 b.n 8011208 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8010bfe: 687b ldr r3, [r7, #4] 8010c00: 681b ldr r3, [r3, #0] 8010c02: f003 0301 and.w r3, r3, #1 8010c06: 2b00 cmp r3, #0 8010c08: f000 8087 beq.w 8010d1a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8010c0c: 4b92 ldr r3, [pc, #584] @ (8010e58 ) 8010c0e: 685b ldr r3, [r3, #4] 8010c10: f003 030c and.w r3, r3, #12 8010c14: 2b04 cmp r3, #4 8010c16: d00c beq.n 8010c32 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8010c18: 4b8f ldr r3, [pc, #572] @ (8010e58 ) 8010c1a: 685b ldr r3, [r3, #4] 8010c1c: f003 030c and.w r3, r3, #12 8010c20: 2b08 cmp r3, #8 8010c22: d112 bne.n 8010c4a 8010c24: 4b8c ldr r3, [pc, #560] @ (8010e58 ) 8010c26: 685b ldr r3, [r3, #4] 8010c28: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010c2c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010c30: d10b bne.n 8010c4a { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8010c32: 4b89 ldr r3, [pc, #548] @ (8010e58 ) 8010c34: 681b ldr r3, [r3, #0] 8010c36: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010c3a: 2b00 cmp r3, #0 8010c3c: d06c beq.n 8010d18 8010c3e: 687b ldr r3, [r7, #4] 8010c40: 689b ldr r3, [r3, #8] 8010c42: 2b00 cmp r3, #0 8010c44: d168 bne.n 8010d18 { return HAL_ERROR; 8010c46: 2301 movs r3, #1 8010c48: e2de b.n 8011208 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8010c4a: 687b ldr r3, [r7, #4] 8010c4c: 689b ldr r3, [r3, #8] 8010c4e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010c52: d106 bne.n 8010c62 8010c54: 4b80 ldr r3, [pc, #512] @ (8010e58 ) 8010c56: 681b ldr r3, [r3, #0] 8010c58: 4a7f ldr r2, [pc, #508] @ (8010e58 ) 8010c5a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8010c5e: 6013 str r3, [r2, #0] 8010c60: e02e b.n 8010cc0 8010c62: 687b ldr r3, [r7, #4] 8010c64: 689b ldr r3, [r3, #8] 8010c66: 2b00 cmp r3, #0 8010c68: d10c bne.n 8010c84 8010c6a: 4b7b ldr r3, [pc, #492] @ (8010e58 ) 8010c6c: 681b ldr r3, [r3, #0] 8010c6e: 4a7a ldr r2, [pc, #488] @ (8010e58 ) 8010c70: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8010c74: 6013 str r3, [r2, #0] 8010c76: 4b78 ldr r3, [pc, #480] @ (8010e58 ) 8010c78: 681b ldr r3, [r3, #0] 8010c7a: 4a77 ldr r2, [pc, #476] @ (8010e58 ) 8010c7c: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010c80: 6013 str r3, [r2, #0] 8010c82: e01d b.n 8010cc0 8010c84: 687b ldr r3, [r7, #4] 8010c86: 689b ldr r3, [r3, #8] 8010c88: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8010c8c: d10c bne.n 8010ca8 8010c8e: 4b72 ldr r3, [pc, #456] @ (8010e58 ) 8010c90: 681b ldr r3, [r3, #0] 8010c92: 4a71 ldr r2, [pc, #452] @ (8010e58 ) 8010c94: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8010c98: 6013 str r3, [r2, #0] 8010c9a: 4b6f ldr r3, [pc, #444] @ (8010e58 ) 8010c9c: 681b ldr r3, [r3, #0] 8010c9e: 4a6e ldr r2, [pc, #440] @ (8010e58 ) 8010ca0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8010ca4: 6013 str r3, [r2, #0] 8010ca6: e00b b.n 8010cc0 8010ca8: 4b6b ldr r3, [pc, #428] @ (8010e58 ) 8010caa: 681b ldr r3, [r3, #0] 8010cac: 4a6a ldr r2, [pc, #424] @ (8010e58 ) 8010cae: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8010cb2: 6013 str r3, [r2, #0] 8010cb4: 4b68 ldr r3, [pc, #416] @ (8010e58 ) 8010cb6: 681b ldr r3, [r3, #0] 8010cb8: 4a67 ldr r2, [pc, #412] @ (8010e58 ) 8010cba: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010cbe: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8010cc0: 687b ldr r3, [r7, #4] 8010cc2: 689b ldr r3, [r3, #8] 8010cc4: 2b00 cmp r3, #0 8010cc6: d013 beq.n 8010cf0 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010cc8: f7fd fb04 bl 800e2d4 8010ccc: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8010cce: e008 b.n 8010ce2 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8010cd0: f7fd fb00 bl 800e2d4 8010cd4: 4602 mov r2, r0 8010cd6: 693b ldr r3, [r7, #16] 8010cd8: 1ad3 subs r3, r2, r3 8010cda: 2b64 cmp r3, #100 @ 0x64 8010cdc: d901 bls.n 8010ce2 { return HAL_TIMEOUT; 8010cde: 2303 movs r3, #3 8010ce0: e292 b.n 8011208 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8010ce2: 4b5d ldr r3, [pc, #372] @ (8010e58 ) 8010ce4: 681b ldr r3, [r3, #0] 8010ce6: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010cea: 2b00 cmp r3, #0 8010cec: d0f0 beq.n 8010cd0 8010cee: e014 b.n 8010d1a } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010cf0: f7fd faf0 bl 800e2d4 8010cf4: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8010cf6: e008 b.n 8010d0a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8010cf8: f7fd faec bl 800e2d4 8010cfc: 4602 mov r2, r0 8010cfe: 693b ldr r3, [r7, #16] 8010d00: 1ad3 subs r3, r2, r3 8010d02: 2b64 cmp r3, #100 @ 0x64 8010d04: d901 bls.n 8010d0a { return HAL_TIMEOUT; 8010d06: 2303 movs r3, #3 8010d08: e27e b.n 8011208 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8010d0a: 4b53 ldr r3, [pc, #332] @ (8010e58 ) 8010d0c: 681b ldr r3, [r3, #0] 8010d0e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010d12: 2b00 cmp r3, #0 8010d14: d1f0 bne.n 8010cf8 8010d16: e000 b.n 8010d1a if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8010d18: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8010d1a: 687b ldr r3, [r7, #4] 8010d1c: 681b ldr r3, [r3, #0] 8010d1e: f003 0302 and.w r3, r3, #2 8010d22: 2b00 cmp r3, #0 8010d24: d063 beq.n 8010dee /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8010d26: 4b4c ldr r3, [pc, #304] @ (8010e58 ) 8010d28: 685b ldr r3, [r3, #4] 8010d2a: f003 030c and.w r3, r3, #12 8010d2e: 2b00 cmp r3, #0 8010d30: d00b beq.n 8010d4a || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 8010d32: 4b49 ldr r3, [pc, #292] @ (8010e58 ) 8010d34: 685b ldr r3, [r3, #4] 8010d36: f003 030c and.w r3, r3, #12 8010d3a: 2b08 cmp r3, #8 8010d3c: d11c bne.n 8010d78 8010d3e: 4b46 ldr r3, [pc, #280] @ (8010e58 ) 8010d40: 685b ldr r3, [r3, #4] 8010d42: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010d46: 2b00 cmp r3, #0 8010d48: d116 bne.n 8010d78 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8010d4a: 4b43 ldr r3, [pc, #268] @ (8010e58 ) 8010d4c: 681b ldr r3, [r3, #0] 8010d4e: f003 0302 and.w r3, r3, #2 8010d52: 2b00 cmp r3, #0 8010d54: d005 beq.n 8010d62 8010d56: 687b ldr r3, [r7, #4] 8010d58: 695b ldr r3, [r3, #20] 8010d5a: 2b01 cmp r3, #1 8010d5c: d001 beq.n 8010d62 { return HAL_ERROR; 8010d5e: 2301 movs r3, #1 8010d60: e252 b.n 8011208 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8010d62: 4b3d ldr r3, [pc, #244] @ (8010e58 ) 8010d64: 681b ldr r3, [r3, #0] 8010d66: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8010d6a: 687b ldr r3, [r7, #4] 8010d6c: 699b ldr r3, [r3, #24] 8010d6e: 00db lsls r3, r3, #3 8010d70: 4939 ldr r1, [pc, #228] @ (8010e58 ) 8010d72: 4313 orrs r3, r2 8010d74: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8010d76: e03a b.n 8010dee } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8010d78: 687b ldr r3, [r7, #4] 8010d7a: 695b ldr r3, [r3, #20] 8010d7c: 2b00 cmp r3, #0 8010d7e: d020 beq.n 8010dc2 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8010d80: 4b36 ldr r3, [pc, #216] @ (8010e5c ) 8010d82: 2201 movs r2, #1 8010d84: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010d86: f7fd faa5 bl 800e2d4 8010d8a: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8010d8c: e008 b.n 8010da0 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8010d8e: f7fd faa1 bl 800e2d4 8010d92: 4602 mov r2, r0 8010d94: 693b ldr r3, [r7, #16] 8010d96: 1ad3 subs r3, r2, r3 8010d98: 2b02 cmp r3, #2 8010d9a: d901 bls.n 8010da0 { return HAL_TIMEOUT; 8010d9c: 2303 movs r3, #3 8010d9e: e233 b.n 8011208 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8010da0: 4b2d ldr r3, [pc, #180] @ (8010e58 ) 8010da2: 681b ldr r3, [r3, #0] 8010da4: f003 0302 and.w r3, r3, #2 8010da8: 2b00 cmp r3, #0 8010daa: d0f0 beq.n 8010d8e } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8010dac: 4b2a ldr r3, [pc, #168] @ (8010e58 ) 8010dae: 681b ldr r3, [r3, #0] 8010db0: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8010db4: 687b ldr r3, [r7, #4] 8010db6: 699b ldr r3, [r3, #24] 8010db8: 00db lsls r3, r3, #3 8010dba: 4927 ldr r1, [pc, #156] @ (8010e58 ) 8010dbc: 4313 orrs r3, r2 8010dbe: 600b str r3, [r1, #0] 8010dc0: e015 b.n 8010dee } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8010dc2: 4b26 ldr r3, [pc, #152] @ (8010e5c ) 8010dc4: 2200 movs r2, #0 8010dc6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010dc8: f7fd fa84 bl 800e2d4 8010dcc: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8010dce: e008 b.n 8010de2 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8010dd0: f7fd fa80 bl 800e2d4 8010dd4: 4602 mov r2, r0 8010dd6: 693b ldr r3, [r7, #16] 8010dd8: 1ad3 subs r3, r2, r3 8010dda: 2b02 cmp r3, #2 8010ddc: d901 bls.n 8010de2 { return HAL_TIMEOUT; 8010dde: 2303 movs r3, #3 8010de0: e212 b.n 8011208 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8010de2: 4b1d ldr r3, [pc, #116] @ (8010e58 ) 8010de4: 681b ldr r3, [r3, #0] 8010de6: f003 0302 and.w r3, r3, #2 8010dea: 2b00 cmp r3, #0 8010dec: d1f0 bne.n 8010dd0 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8010dee: 687b ldr r3, [r7, #4] 8010df0: 681b ldr r3, [r3, #0] 8010df2: f003 0308 and.w r3, r3, #8 8010df6: 2b00 cmp r3, #0 8010df8: d03a beq.n 8010e70 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8010dfa: 687b ldr r3, [r7, #4] 8010dfc: 69db ldr r3, [r3, #28] 8010dfe: 2b00 cmp r3, #0 8010e00: d019 beq.n 8010e36 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8010e02: 4b17 ldr r3, [pc, #92] @ (8010e60 ) 8010e04: 2201 movs r2, #1 8010e06: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010e08: f7fd fa64 bl 800e2d4 8010e0c: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8010e0e: e008 b.n 8010e22 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8010e10: f7fd fa60 bl 800e2d4 8010e14: 4602 mov r2, r0 8010e16: 693b ldr r3, [r7, #16] 8010e18: 1ad3 subs r3, r2, r3 8010e1a: 2b02 cmp r3, #2 8010e1c: d901 bls.n 8010e22 { return HAL_TIMEOUT; 8010e1e: 2303 movs r3, #3 8010e20: e1f2 b.n 8011208 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8010e22: 4b0d ldr r3, [pc, #52] @ (8010e58 ) 8010e24: 6a5b ldr r3, [r3, #36] @ 0x24 8010e26: f003 0302 and.w r3, r3, #2 8010e2a: 2b00 cmp r3, #0 8010e2c: d0f0 beq.n 8010e10 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 8010e2e: 2001 movs r0, #1 8010e30: f000 fbca bl 80115c8 8010e34: e01c b.n 8010e70 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8010e36: 4b0a ldr r3, [pc, #40] @ (8010e60 ) 8010e38: 2200 movs r2, #0 8010e3a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010e3c: f7fd fa4a bl 800e2d4 8010e40: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8010e42: e00f b.n 8010e64 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8010e44: f7fd fa46 bl 800e2d4 8010e48: 4602 mov r2, r0 8010e4a: 693b ldr r3, [r7, #16] 8010e4c: 1ad3 subs r3, r2, r3 8010e4e: 2b02 cmp r3, #2 8010e50: d908 bls.n 8010e64 { return HAL_TIMEOUT; 8010e52: 2303 movs r3, #3 8010e54: e1d8 b.n 8011208 8010e56: bf00 nop 8010e58: 40021000 .word 0x40021000 8010e5c: 42420000 .word 0x42420000 8010e60: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8010e64: 4b9b ldr r3, [pc, #620] @ (80110d4 ) 8010e66: 6a5b ldr r3, [r3, #36] @ 0x24 8010e68: f003 0302 and.w r3, r3, #2 8010e6c: 2b00 cmp r3, #0 8010e6e: d1e9 bne.n 8010e44 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8010e70: 687b ldr r3, [r7, #4] 8010e72: 681b ldr r3, [r3, #0] 8010e74: f003 0304 and.w r3, r3, #4 8010e78: 2b00 cmp r3, #0 8010e7a: f000 80a6 beq.w 8010fca { FlagStatus pwrclkchanged = RESET; 8010e7e: 2300 movs r3, #0 8010e80: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8010e82: 4b94 ldr r3, [pc, #592] @ (80110d4 ) 8010e84: 69db ldr r3, [r3, #28] 8010e86: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010e8a: 2b00 cmp r3, #0 8010e8c: d10d bne.n 8010eaa { __HAL_RCC_PWR_CLK_ENABLE(); 8010e8e: 4b91 ldr r3, [pc, #580] @ (80110d4 ) 8010e90: 69db ldr r3, [r3, #28] 8010e92: 4a90 ldr r2, [pc, #576] @ (80110d4 ) 8010e94: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8010e98: 61d3 str r3, [r2, #28] 8010e9a: 4b8e ldr r3, [pc, #568] @ (80110d4 ) 8010e9c: 69db ldr r3, [r3, #28] 8010e9e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010ea2: 60bb str r3, [r7, #8] 8010ea4: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8010ea6: 2301 movs r3, #1 8010ea8: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010eaa: 4b8b ldr r3, [pc, #556] @ (80110d8 ) 8010eac: 681b ldr r3, [r3, #0] 8010eae: f403 7380 and.w r3, r3, #256 @ 0x100 8010eb2: 2b00 cmp r3, #0 8010eb4: d118 bne.n 8010ee8 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8010eb6: 4b88 ldr r3, [pc, #544] @ (80110d8 ) 8010eb8: 681b ldr r3, [r3, #0] 8010eba: 4a87 ldr r2, [pc, #540] @ (80110d8 ) 8010ebc: f443 7380 orr.w r3, r3, #256 @ 0x100 8010ec0: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8010ec2: f7fd fa07 bl 800e2d4 8010ec6: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010ec8: e008 b.n 8010edc { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8010eca: f7fd fa03 bl 800e2d4 8010ece: 4602 mov r2, r0 8010ed0: 693b ldr r3, [r7, #16] 8010ed2: 1ad3 subs r3, r2, r3 8010ed4: 2b64 cmp r3, #100 @ 0x64 8010ed6: d901 bls.n 8010edc { return HAL_TIMEOUT; 8010ed8: 2303 movs r3, #3 8010eda: e195 b.n 8011208 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010edc: 4b7e ldr r3, [pc, #504] @ (80110d8 ) 8010ede: 681b ldr r3, [r3, #0] 8010ee0: f403 7380 and.w r3, r3, #256 @ 0x100 8010ee4: 2b00 cmp r3, #0 8010ee6: d0f0 beq.n 8010eca } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8010ee8: 687b ldr r3, [r7, #4] 8010eea: 691b ldr r3, [r3, #16] 8010eec: 2b01 cmp r3, #1 8010eee: d106 bne.n 8010efe 8010ef0: 4b78 ldr r3, [pc, #480] @ (80110d4 ) 8010ef2: 6a1b ldr r3, [r3, #32] 8010ef4: 4a77 ldr r2, [pc, #476] @ (80110d4 ) 8010ef6: f043 0301 orr.w r3, r3, #1 8010efa: 6213 str r3, [r2, #32] 8010efc: e02d b.n 8010f5a 8010efe: 687b ldr r3, [r7, #4] 8010f00: 691b ldr r3, [r3, #16] 8010f02: 2b00 cmp r3, #0 8010f04: d10c bne.n 8010f20 8010f06: 4b73 ldr r3, [pc, #460] @ (80110d4 ) 8010f08: 6a1b ldr r3, [r3, #32] 8010f0a: 4a72 ldr r2, [pc, #456] @ (80110d4 ) 8010f0c: f023 0301 bic.w r3, r3, #1 8010f10: 6213 str r3, [r2, #32] 8010f12: 4b70 ldr r3, [pc, #448] @ (80110d4 ) 8010f14: 6a1b ldr r3, [r3, #32] 8010f16: 4a6f ldr r2, [pc, #444] @ (80110d4 ) 8010f18: f023 0304 bic.w r3, r3, #4 8010f1c: 6213 str r3, [r2, #32] 8010f1e: e01c b.n 8010f5a 8010f20: 687b ldr r3, [r7, #4] 8010f22: 691b ldr r3, [r3, #16] 8010f24: 2b05 cmp r3, #5 8010f26: d10c bne.n 8010f42 8010f28: 4b6a ldr r3, [pc, #424] @ (80110d4 ) 8010f2a: 6a1b ldr r3, [r3, #32] 8010f2c: 4a69 ldr r2, [pc, #420] @ (80110d4 ) 8010f2e: f043 0304 orr.w r3, r3, #4 8010f32: 6213 str r3, [r2, #32] 8010f34: 4b67 ldr r3, [pc, #412] @ (80110d4 ) 8010f36: 6a1b ldr r3, [r3, #32] 8010f38: 4a66 ldr r2, [pc, #408] @ (80110d4 ) 8010f3a: f043 0301 orr.w r3, r3, #1 8010f3e: 6213 str r3, [r2, #32] 8010f40: e00b b.n 8010f5a 8010f42: 4b64 ldr r3, [pc, #400] @ (80110d4 ) 8010f44: 6a1b ldr r3, [r3, #32] 8010f46: 4a63 ldr r2, [pc, #396] @ (80110d4 ) 8010f48: f023 0301 bic.w r3, r3, #1 8010f4c: 6213 str r3, [r2, #32] 8010f4e: 4b61 ldr r3, [pc, #388] @ (80110d4 ) 8010f50: 6a1b ldr r3, [r3, #32] 8010f52: 4a60 ldr r2, [pc, #384] @ (80110d4 ) 8010f54: f023 0304 bic.w r3, r3, #4 8010f58: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8010f5a: 687b ldr r3, [r7, #4] 8010f5c: 691b ldr r3, [r3, #16] 8010f5e: 2b00 cmp r3, #0 8010f60: d015 beq.n 8010f8e { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010f62: f7fd f9b7 bl 800e2d4 8010f66: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8010f68: e00a b.n 8010f80 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8010f6a: f7fd f9b3 bl 800e2d4 8010f6e: 4602 mov r2, r0 8010f70: 693b ldr r3, [r7, #16] 8010f72: 1ad3 subs r3, r2, r3 8010f74: f241 3288 movw r2, #5000 @ 0x1388 8010f78: 4293 cmp r3, r2 8010f7a: d901 bls.n 8010f80 { return HAL_TIMEOUT; 8010f7c: 2303 movs r3, #3 8010f7e: e143 b.n 8011208 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8010f80: 4b54 ldr r3, [pc, #336] @ (80110d4 ) 8010f82: 6a1b ldr r3, [r3, #32] 8010f84: f003 0302 and.w r3, r3, #2 8010f88: 2b00 cmp r3, #0 8010f8a: d0ee beq.n 8010f6a 8010f8c: e014 b.n 8010fb8 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010f8e: f7fd f9a1 bl 800e2d4 8010f92: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8010f94: e00a b.n 8010fac { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8010f96: f7fd f99d bl 800e2d4 8010f9a: 4602 mov r2, r0 8010f9c: 693b ldr r3, [r7, #16] 8010f9e: 1ad3 subs r3, r2, r3 8010fa0: f241 3288 movw r2, #5000 @ 0x1388 8010fa4: 4293 cmp r3, r2 8010fa6: d901 bls.n 8010fac { return HAL_TIMEOUT; 8010fa8: 2303 movs r3, #3 8010faa: e12d b.n 8011208 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8010fac: 4b49 ldr r3, [pc, #292] @ (80110d4 ) 8010fae: 6a1b ldr r3, [r3, #32] 8010fb0: f003 0302 and.w r3, r3, #2 8010fb4: 2b00 cmp r3, #0 8010fb6: d1ee bne.n 8010f96 } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8010fb8: 7dfb ldrb r3, [r7, #23] 8010fba: 2b01 cmp r3, #1 8010fbc: d105 bne.n 8010fca { __HAL_RCC_PWR_CLK_DISABLE(); 8010fbe: 4b45 ldr r3, [pc, #276] @ (80110d4 ) 8010fc0: 69db ldr r3, [r3, #28] 8010fc2: 4a44 ldr r2, [pc, #272] @ (80110d4 ) 8010fc4: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8010fc8: 61d3 str r3, [r2, #28] #if defined(RCC_CR_PLL2ON) /*-------------------------------- PLL2 Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) 8010fca: 687b ldr r3, [r7, #4] 8010fcc: 6adb ldr r3, [r3, #44] @ 0x2c 8010fce: 2b00 cmp r3, #0 8010fd0: f000 808c beq.w 80110ec { /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 8010fd4: 4b3f ldr r3, [pc, #252] @ (80110d4 ) 8010fd6: 685b ldr r3, [r3, #4] 8010fd8: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010fdc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010fe0: d10e bne.n 8011000 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 8010fe2: 4b3c ldr r3, [pc, #240] @ (80110d4 ) 8010fe4: 685b ldr r3, [r3, #4] 8010fe6: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 8010fea: 2b08 cmp r3, #8 8010fec: d108 bne.n 8011000 ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) 8010fee: 4b39 ldr r3, [pc, #228] @ (80110d4 ) 8010ff0: 6adb ldr r3, [r3, #44] @ 0x2c 8010ff2: f403 3380 and.w r3, r3, #65536 @ 0x10000 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 8010ff6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010ffa: d101 bne.n 8011000 { return HAL_ERROR; 8010ffc: 2301 movs r3, #1 8010ffe: e103 b.n 8011208 } else { if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) 8011000: 687b ldr r3, [r7, #4] 8011002: 6adb ldr r3, [r3, #44] @ 0x2c 8011004: 2b02 cmp r3, #2 8011006: d14e bne.n 80110a6 assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); /* Prediv2 can be written only when the PLLI2S is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 8011008: 4b32 ldr r3, [pc, #200] @ (80110d4 ) 801100a: 681b ldr r3, [r3, #0] 801100c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011010: 2b00 cmp r3, #0 8011012: d009 beq.n 8011028 (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) 8011014: 4b2f ldr r3, [pc, #188] @ (80110d4 ) 8011016: 6adb ldr r3, [r3, #44] @ 0x2c 8011018: f003 02f0 and.w r2, r3, #240 @ 0xf0 801101c: 687b ldr r3, [r7, #4] 801101e: 6b5b ldr r3, [r3, #52] @ 0x34 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 8011020: 429a cmp r2, r3 8011022: d001 beq.n 8011028 { return HAL_ERROR; 8011024: 2301 movs r3, #1 8011026: e0ef b.n 8011208 } /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 8011028: 4b2c ldr r3, [pc, #176] @ (80110dc ) 801102a: 2200 movs r2, #0 801102c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 801102e: f7fd f951 bl 800e2d4 8011032: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8011034: e008 b.n 8011048 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8011036: f7fd f94d bl 800e2d4 801103a: 4602 mov r2, r0 801103c: 693b ldr r3, [r7, #16] 801103e: 1ad3 subs r3, r2, r3 8011040: 2b64 cmp r3, #100 @ 0x64 8011042: d901 bls.n 8011048 { return HAL_TIMEOUT; 8011044: 2303 movs r3, #3 8011046: e0df b.n 8011208 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8011048: 4b22 ldr r3, [pc, #136] @ (80110d4 ) 801104a: 681b ldr r3, [r3, #0] 801104c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8011050: 2b00 cmp r3, #0 8011052: d1f0 bne.n 8011036 } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); 8011054: 4b1f ldr r3, [pc, #124] @ (80110d4 ) 8011056: 6adb ldr r3, [r3, #44] @ 0x2c 8011058: f023 02f0 bic.w r2, r3, #240 @ 0xf0 801105c: 687b ldr r3, [r7, #4] 801105e: 6b5b ldr r3, [r3, #52] @ 0x34 8011060: 491c ldr r1, [pc, #112] @ (80110d4 ) 8011062: 4313 orrs r3, r2 8011064: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); 8011066: 4b1b ldr r3, [pc, #108] @ (80110d4 ) 8011068: 6adb ldr r3, [r3, #44] @ 0x2c 801106a: f423 6270 bic.w r2, r3, #3840 @ 0xf00 801106e: 687b ldr r3, [r7, #4] 8011070: 6b1b ldr r3, [r3, #48] @ 0x30 8011072: 4918 ldr r1, [pc, #96] @ (80110d4 ) 8011074: 4313 orrs r3, r2 8011076: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); 8011078: 4b18 ldr r3, [pc, #96] @ (80110dc ) 801107a: 2201 movs r2, #1 801107c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 801107e: f7fd f929 bl 800e2d4 8011082: 6138 str r0, [r7, #16] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8011084: e008 b.n 8011098 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8011086: f7fd f925 bl 800e2d4 801108a: 4602 mov r2, r0 801108c: 693b ldr r3, [r7, #16] 801108e: 1ad3 subs r3, r2, r3 8011090: 2b64 cmp r3, #100 @ 0x64 8011092: d901 bls.n 8011098 { return HAL_TIMEOUT; 8011094: 2303 movs r3, #3 8011096: e0b7 b.n 8011208 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8011098: 4b0e ldr r3, [pc, #56] @ (80110d4 ) 801109a: 681b ldr r3, [r3, #0] 801109c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80110a0: 2b00 cmp r3, #0 80110a2: d0f0 beq.n 8011086 80110a4: e022 b.n 80110ec } } else { /* Set PREDIV1 source to HSE */ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); 80110a6: 4b0b ldr r3, [pc, #44] @ (80110d4 ) 80110a8: 6adb ldr r3, [r3, #44] @ 0x2c 80110aa: 4a0a ldr r2, [pc, #40] @ (80110d4 ) 80110ac: f423 3380 bic.w r3, r3, #65536 @ 0x10000 80110b0: 62d3 str r3, [r2, #44] @ 0x2c /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 80110b2: 4b0a ldr r3, [pc, #40] @ (80110dc ) 80110b4: 2200 movs r2, #0 80110b6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80110b8: f7fd f90c bl 800e2d4 80110bc: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 80110be: e00f b.n 80110e0 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 80110c0: f7fd f908 bl 800e2d4 80110c4: 4602 mov r2, r0 80110c6: 693b ldr r3, [r7, #16] 80110c8: 1ad3 subs r3, r2, r3 80110ca: 2b64 cmp r3, #100 @ 0x64 80110cc: d908 bls.n 80110e0 { return HAL_TIMEOUT; 80110ce: 2303 movs r3, #3 80110d0: e09a b.n 8011208 80110d2: bf00 nop 80110d4: 40021000 .word 0x40021000 80110d8: 40007000 .word 0x40007000 80110dc: 42420068 .word 0x42420068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 80110e0: 4b4b ldr r3, [pc, #300] @ (8011210 ) 80110e2: 681b ldr r3, [r3, #0] 80110e4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80110e8: 2b00 cmp r3, #0 80110ea: d1e9 bne.n 80110c0 #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 80110ec: 687b ldr r3, [r7, #4] 80110ee: 6a1b ldr r3, [r3, #32] 80110f0: 2b00 cmp r3, #0 80110f2: f000 8088 beq.w 8011206 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 80110f6: 4b46 ldr r3, [pc, #280] @ (8011210 ) 80110f8: 685b ldr r3, [r3, #4] 80110fa: f003 030c and.w r3, r3, #12 80110fe: 2b08 cmp r3, #8 8011100: d068 beq.n 80111d4 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8011102: 687b ldr r3, [r7, #4] 8011104: 6a1b ldr r3, [r3, #32] 8011106: 2b02 cmp r3, #2 8011108: d14d bne.n 80111a6 /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 801110a: 4b42 ldr r3, [pc, #264] @ (8011214 ) 801110c: 2200 movs r2, #0 801110e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8011110: f7fd f8e0 bl 800e2d4 8011114: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8011116: e008 b.n 801112a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8011118: f7fd f8dc bl 800e2d4 801111c: 4602 mov r2, r0 801111e: 693b ldr r3, [r7, #16] 8011120: 1ad3 subs r3, r2, r3 8011122: 2b02 cmp r3, #2 8011124: d901 bls.n 801112a { return HAL_TIMEOUT; 8011126: 2303 movs r3, #3 8011128: e06e b.n 8011208 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 801112a: 4b39 ldr r3, [pc, #228] @ (8011210 ) 801112c: 681b ldr r3, [r3, #0] 801112e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8011132: 2b00 cmp r3, #0 8011134: d1f0 bne.n 8011118 } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 8011136: 687b ldr r3, [r7, #4] 8011138: 6a5b ldr r3, [r3, #36] @ 0x24 801113a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 801113e: d10f bne.n 8011160 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); #if defined(RCC_CFGR2_PREDIV1SRC) assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); 8011140: 4b33 ldr r3, [pc, #204] @ (8011210 ) 8011142: 6ada ldr r2, [r3, #44] @ 0x2c 8011144: 687b ldr r3, [r7, #4] 8011146: 685b ldr r3, [r3, #4] 8011148: 4931 ldr r1, [pc, #196] @ (8011210 ) 801114a: 4313 orrs r3, r2 801114c: 62cb str r3, [r1, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 801114e: 4b30 ldr r3, [pc, #192] @ (8011210 ) 8011150: 6adb ldr r3, [r3, #44] @ 0x2c 8011152: f023 020f bic.w r2, r3, #15 8011156: 687b ldr r3, [r7, #4] 8011158: 68db ldr r3, [r3, #12] 801115a: 492d ldr r1, [pc, #180] @ (8011210 ) 801115c: 4313 orrs r3, r2 801115e: 62cb str r3, [r1, #44] @ 0x2c } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8011160: 4b2b ldr r3, [pc, #172] @ (8011210 ) 8011162: 685b ldr r3, [r3, #4] 8011164: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 8011168: 687b ldr r3, [r7, #4] 801116a: 6a59 ldr r1, [r3, #36] @ 0x24 801116c: 687b ldr r3, [r7, #4] 801116e: 6a9b ldr r3, [r3, #40] @ 0x28 8011170: 430b orrs r3, r1 8011172: 4927 ldr r1, [pc, #156] @ (8011210 ) 8011174: 4313 orrs r3, r2 8011176: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8011178: 4b26 ldr r3, [pc, #152] @ (8011214 ) 801117a: 2201 movs r2, #1 801117c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 801117e: f7fd f8a9 bl 800e2d4 8011182: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8011184: e008 b.n 8011198 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8011186: f7fd f8a5 bl 800e2d4 801118a: 4602 mov r2, r0 801118c: 693b ldr r3, [r7, #16] 801118e: 1ad3 subs r3, r2, r3 8011190: 2b02 cmp r3, #2 8011192: d901 bls.n 8011198 { return HAL_TIMEOUT; 8011194: 2303 movs r3, #3 8011196: e037 b.n 8011208 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8011198: 4b1d ldr r3, [pc, #116] @ (8011210 ) 801119a: 681b ldr r3, [r3, #0] 801119c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80111a0: 2b00 cmp r3, #0 80111a2: d0f0 beq.n 8011186 80111a4: e02f b.n 8011206 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80111a6: 4b1b ldr r3, [pc, #108] @ (8011214 ) 80111a8: 2200 movs r2, #0 80111aa: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80111ac: f7fd f892 bl 800e2d4 80111b0: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80111b2: e008 b.n 80111c6 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80111b4: f7fd f88e bl 800e2d4 80111b8: 4602 mov r2, r0 80111ba: 693b ldr r3, [r7, #16] 80111bc: 1ad3 subs r3, r2, r3 80111be: 2b02 cmp r3, #2 80111c0: d901 bls.n 80111c6 { return HAL_TIMEOUT; 80111c2: 2303 movs r3, #3 80111c4: e020 b.n 8011208 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80111c6: 4b12 ldr r3, [pc, #72] @ (8011210 ) 80111c8: 681b ldr r3, [r3, #0] 80111ca: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80111ce: 2b00 cmp r3, #0 80111d0: d1f0 bne.n 80111b4 80111d2: e018 b.n 8011206 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 80111d4: 687b ldr r3, [r7, #4] 80111d6: 6a1b ldr r3, [r3, #32] 80111d8: 2b01 cmp r3, #1 80111da: d101 bne.n 80111e0 { return HAL_ERROR; 80111dc: 2301 movs r3, #1 80111de: e013 b.n 8011208 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 80111e0: 4b0b ldr r3, [pc, #44] @ (8011210 ) 80111e2: 685b ldr r3, [r3, #4] 80111e4: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80111e6: 68fb ldr r3, [r7, #12] 80111e8: f403 3280 and.w r2, r3, #65536 @ 0x10000 80111ec: 687b ldr r3, [r7, #4] 80111ee: 6a5b ldr r3, [r3, #36] @ 0x24 80111f0: 429a cmp r2, r3 80111f2: d106 bne.n 8011202 (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 80111f4: 68fb ldr r3, [r7, #12] 80111f6: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 80111fa: 687b ldr r3, [r7, #4] 80111fc: 6a9b ldr r3, [r3, #40] @ 0x28 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80111fe: 429a cmp r2, r3 8011200: d001 beq.n 8011206 { return HAL_ERROR; 8011202: 2301 movs r3, #1 8011204: e000 b.n 8011208 } } } } return HAL_OK; 8011206: 2300 movs r3, #0 } 8011208: 4618 mov r0, r3 801120a: 3718 adds r7, #24 801120c: 46bd mov sp, r7 801120e: bd80 pop {r7, pc} 8011210: 40021000 .word 0x40021000 8011214: 42420060 .word 0x42420060 08011218 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8011218: b580 push {r7, lr} 801121a: b084 sub sp, #16 801121c: af00 add r7, sp, #0 801121e: 6078 str r0, [r7, #4] 8011220: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8011222: 687b ldr r3, [r7, #4] 8011224: 2b00 cmp r3, #0 8011226: d101 bne.n 801122c { return HAL_ERROR; 8011228: 2301 movs r3, #1 801122a: e0d0 b.n 80113ce must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 801122c: 4b6a ldr r3, [pc, #424] @ (80113d8 ) 801122e: 681b ldr r3, [r3, #0] 8011230: f003 0307 and.w r3, r3, #7 8011234: 683a ldr r2, [r7, #0] 8011236: 429a cmp r2, r3 8011238: d910 bls.n 801125c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 801123a: 4b67 ldr r3, [pc, #412] @ (80113d8 ) 801123c: 681b ldr r3, [r3, #0] 801123e: f023 0207 bic.w r2, r3, #7 8011242: 4965 ldr r1, [pc, #404] @ (80113d8 ) 8011244: 683b ldr r3, [r7, #0] 8011246: 4313 orrs r3, r2 8011248: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 801124a: 4b63 ldr r3, [pc, #396] @ (80113d8 ) 801124c: 681b ldr r3, [r3, #0] 801124e: f003 0307 and.w r3, r3, #7 8011252: 683a ldr r2, [r7, #0] 8011254: 429a cmp r2, r3 8011256: d001 beq.n 801125c { return HAL_ERROR; 8011258: 2301 movs r3, #1 801125a: e0b8 b.n 80113ce } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 801125c: 687b ldr r3, [r7, #4] 801125e: 681b ldr r3, [r3, #0] 8011260: f003 0302 and.w r3, r3, #2 8011264: 2b00 cmp r3, #0 8011266: d020 beq.n 80112aa { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8011268: 687b ldr r3, [r7, #4] 801126a: 681b ldr r3, [r3, #0] 801126c: f003 0304 and.w r3, r3, #4 8011270: 2b00 cmp r3, #0 8011272: d005 beq.n 8011280 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8011274: 4b59 ldr r3, [pc, #356] @ (80113dc ) 8011276: 685b ldr r3, [r3, #4] 8011278: 4a58 ldr r2, [pc, #352] @ (80113dc ) 801127a: f443 63e0 orr.w r3, r3, #1792 @ 0x700 801127e: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8011280: 687b ldr r3, [r7, #4] 8011282: 681b ldr r3, [r3, #0] 8011284: f003 0308 and.w r3, r3, #8 8011288: 2b00 cmp r3, #0 801128a: d005 beq.n 8011298 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 801128c: 4b53 ldr r3, [pc, #332] @ (80113dc ) 801128e: 685b ldr r3, [r3, #4] 8011290: 4a52 ldr r2, [pc, #328] @ (80113dc ) 8011292: f443 5360 orr.w r3, r3, #14336 @ 0x3800 8011296: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8011298: 4b50 ldr r3, [pc, #320] @ (80113dc ) 801129a: 685b ldr r3, [r3, #4] 801129c: f023 02f0 bic.w r2, r3, #240 @ 0xf0 80112a0: 687b ldr r3, [r7, #4] 80112a2: 689b ldr r3, [r3, #8] 80112a4: 494d ldr r1, [pc, #308] @ (80113dc ) 80112a6: 4313 orrs r3, r2 80112a8: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80112aa: 687b ldr r3, [r7, #4] 80112ac: 681b ldr r3, [r3, #0] 80112ae: f003 0301 and.w r3, r3, #1 80112b2: 2b00 cmp r3, #0 80112b4: d040 beq.n 8011338 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80112b6: 687b ldr r3, [r7, #4] 80112b8: 685b ldr r3, [r3, #4] 80112ba: 2b01 cmp r3, #1 80112bc: d107 bne.n 80112ce { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80112be: 4b47 ldr r3, [pc, #284] @ (80113dc ) 80112c0: 681b ldr r3, [r3, #0] 80112c2: f403 3300 and.w r3, r3, #131072 @ 0x20000 80112c6: 2b00 cmp r3, #0 80112c8: d115 bne.n 80112f6 { return HAL_ERROR; 80112ca: 2301 movs r3, #1 80112cc: e07f b.n 80113ce } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 80112ce: 687b ldr r3, [r7, #4] 80112d0: 685b ldr r3, [r3, #4] 80112d2: 2b02 cmp r3, #2 80112d4: d107 bne.n 80112e6 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80112d6: 4b41 ldr r3, [pc, #260] @ (80113dc ) 80112d8: 681b ldr r3, [r3, #0] 80112da: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80112de: 2b00 cmp r3, #0 80112e0: d109 bne.n 80112f6 { return HAL_ERROR; 80112e2: 2301 movs r3, #1 80112e4: e073 b.n 80113ce } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80112e6: 4b3d ldr r3, [pc, #244] @ (80113dc ) 80112e8: 681b ldr r3, [r3, #0] 80112ea: f003 0302 and.w r3, r3, #2 80112ee: 2b00 cmp r3, #0 80112f0: d101 bne.n 80112f6 { return HAL_ERROR; 80112f2: 2301 movs r3, #1 80112f4: e06b b.n 80113ce } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 80112f6: 4b39 ldr r3, [pc, #228] @ (80113dc ) 80112f8: 685b ldr r3, [r3, #4] 80112fa: f023 0203 bic.w r2, r3, #3 80112fe: 687b ldr r3, [r7, #4] 8011300: 685b ldr r3, [r3, #4] 8011302: 4936 ldr r1, [pc, #216] @ (80113dc ) 8011304: 4313 orrs r3, r2 8011306: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8011308: f7fc ffe4 bl 800e2d4 801130c: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 801130e: e00a b.n 8011326 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8011310: f7fc ffe0 bl 800e2d4 8011314: 4602 mov r2, r0 8011316: 68fb ldr r3, [r7, #12] 8011318: 1ad3 subs r3, r2, r3 801131a: f241 3288 movw r2, #5000 @ 0x1388 801131e: 4293 cmp r3, r2 8011320: d901 bls.n 8011326 { return HAL_TIMEOUT; 8011322: 2303 movs r3, #3 8011324: e053 b.n 80113ce while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8011326: 4b2d ldr r3, [pc, #180] @ (80113dc ) 8011328: 685b ldr r3, [r3, #4] 801132a: f003 020c and.w r2, r3, #12 801132e: 687b ldr r3, [r7, #4] 8011330: 685b ldr r3, [r3, #4] 8011332: 009b lsls r3, r3, #2 8011334: 429a cmp r2, r3 8011336: d1eb bne.n 8011310 } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8011338: 4b27 ldr r3, [pc, #156] @ (80113d8 ) 801133a: 681b ldr r3, [r3, #0] 801133c: f003 0307 and.w r3, r3, #7 8011340: 683a ldr r2, [r7, #0] 8011342: 429a cmp r2, r3 8011344: d210 bcs.n 8011368 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8011346: 4b24 ldr r3, [pc, #144] @ (80113d8 ) 8011348: 681b ldr r3, [r3, #0] 801134a: f023 0207 bic.w r2, r3, #7 801134e: 4922 ldr r1, [pc, #136] @ (80113d8 ) 8011350: 683b ldr r3, [r7, #0] 8011352: 4313 orrs r3, r2 8011354: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8011356: 4b20 ldr r3, [pc, #128] @ (80113d8 ) 8011358: 681b ldr r3, [r3, #0] 801135a: f003 0307 and.w r3, r3, #7 801135e: 683a ldr r2, [r7, #0] 8011360: 429a cmp r2, r3 8011362: d001 beq.n 8011368 { return HAL_ERROR; 8011364: 2301 movs r3, #1 8011366: e032 b.n 80113ce } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8011368: 687b ldr r3, [r7, #4] 801136a: 681b ldr r3, [r3, #0] 801136c: f003 0304 and.w r3, r3, #4 8011370: 2b00 cmp r3, #0 8011372: d008 beq.n 8011386 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8011374: 4b19 ldr r3, [pc, #100] @ (80113dc ) 8011376: 685b ldr r3, [r3, #4] 8011378: f423 62e0 bic.w r2, r3, #1792 @ 0x700 801137c: 687b ldr r3, [r7, #4] 801137e: 68db ldr r3, [r3, #12] 8011380: 4916 ldr r1, [pc, #88] @ (80113dc ) 8011382: 4313 orrs r3, r2 8011384: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8011386: 687b ldr r3, [r7, #4] 8011388: 681b ldr r3, [r3, #0] 801138a: f003 0308 and.w r3, r3, #8 801138e: 2b00 cmp r3, #0 8011390: d009 beq.n 80113a6 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 8011392: 4b12 ldr r3, [pc, #72] @ (80113dc ) 8011394: 685b ldr r3, [r3, #4] 8011396: f423 5260 bic.w r2, r3, #14336 @ 0x3800 801139a: 687b ldr r3, [r7, #4] 801139c: 691b ldr r3, [r3, #16] 801139e: 00db lsls r3, r3, #3 80113a0: 490e ldr r1, [pc, #56] @ (80113dc ) 80113a2: 4313 orrs r3, r2 80113a4: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 80113a6: f000 f821 bl 80113ec 80113aa: 4602 mov r2, r0 80113ac: 4b0b ldr r3, [pc, #44] @ (80113dc ) 80113ae: 685b ldr r3, [r3, #4] 80113b0: 091b lsrs r3, r3, #4 80113b2: f003 030f and.w r3, r3, #15 80113b6: 490a ldr r1, [pc, #40] @ (80113e0 ) 80113b8: 5ccb ldrb r3, [r1, r3] 80113ba: fa22 f303 lsr.w r3, r2, r3 80113be: 4a09 ldr r2, [pc, #36] @ (80113e4 ) 80113c0: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 80113c2: 4b09 ldr r3, [pc, #36] @ (80113e8 ) 80113c4: 681b ldr r3, [r3, #0] 80113c6: 4618 mov r0, r3 80113c8: f7fc ff42 bl 800e250 return HAL_OK; 80113cc: 2300 movs r3, #0 } 80113ce: 4618 mov r0, r3 80113d0: 3710 adds r7, #16 80113d2: 46bd mov sp, r7 80113d4: bd80 pop {r7, pc} 80113d6: bf00 nop 80113d8: 40022000 .word 0x40022000 80113dc: 40021000 .word 0x40021000 80113e0: 08017894 .word 0x08017894 80113e4: 20000084 .word 0x20000084 80113e8: 20000088 .word 0x20000088 080113ec : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 80113ec: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 80113f0: b08e sub sp, #56 @ 0x38 80113f2: af00 add r7, sp, #0 #else static const uint8_t aPredivFactorTable[2U] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 80113f4: 2300 movs r3, #0 80113f6: 62fb str r3, [r7, #44] @ 0x2c 80113f8: 2300 movs r3, #0 80113fa: 62bb str r3, [r7, #40] @ 0x28 80113fc: 2300 movs r3, #0 80113fe: 637b str r3, [r7, #52] @ 0x34 8011400: 2300 movs r3, #0 8011402: 627b str r3, [r7, #36] @ 0x24 uint32_t sysclockfreq = 0U; 8011404: 2300 movs r3, #0 8011406: 633b str r3, [r7, #48] @ 0x30 #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; 8011408: 2300 movs r3, #0 801140a: 623b str r3, [r7, #32] 801140c: 2300 movs r3, #0 801140e: 61fb str r3, [r7, #28] #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 8011410: 4b4e ldr r3, [pc, #312] @ (801154c ) 8011412: 685b ldr r3, [r3, #4] 8011414: 62fb str r3, [r7, #44] @ 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8011416: 6afb ldr r3, [r7, #44] @ 0x2c 8011418: f003 030c and.w r3, r3, #12 801141c: 2b04 cmp r3, #4 801141e: d002 beq.n 8011426 8011420: 2b08 cmp r3, #8 8011422: d003 beq.n 801142c 8011424: e089 b.n 801153a { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8011426: 4b4a ldr r3, [pc, #296] @ (8011550 ) 8011428: 633b str r3, [r7, #48] @ 0x30 break; 801142a: e089 b.n 8011540 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 801142c: 6afb ldr r3, [r7, #44] @ 0x2c 801142e: 0c9b lsrs r3, r3, #18 8011430: f003 020f and.w r2, r3, #15 8011434: 4b47 ldr r3, [pc, #284] @ (8011554 ) 8011436: 5c9b ldrb r3, [r3, r2] 8011438: 627b str r3, [r7, #36] @ 0x24 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 801143a: 6afb ldr r3, [r7, #44] @ 0x2c 801143c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8011440: 2b00 cmp r3, #0 8011442: d072 beq.n 801152a { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 8011444: 4b41 ldr r3, [pc, #260] @ (801154c ) 8011446: 6adb ldr r3, [r3, #44] @ 0x2c 8011448: f003 020f and.w r2, r3, #15 801144c: 4b42 ldr r3, [pc, #264] @ (8011558 ) 801144e: 5c9b ldrb r3, [r3, r2] 8011450: 62bb str r3, [r7, #40] @ 0x28 #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /*RCC_CFGR2_PREDIV1*/ #if defined(RCC_CFGR2_PREDIV1SRC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 8011452: 4b3e ldr r3, [pc, #248] @ (801154c ) 8011454: 6adb ldr r3, [r3, #44] @ 0x2c 8011456: f403 3380 and.w r3, r3, #65536 @ 0x10000 801145a: 2b00 cmp r3, #0 801145c: d053 beq.n 8011506 { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 801145e: 4b3b ldr r3, [pc, #236] @ (801154c ) 8011460: 6adb ldr r3, [r3, #44] @ 0x2c 8011462: 091b lsrs r3, r3, #4 8011464: f003 030f and.w r3, r3, #15 8011468: 3301 adds r3, #1 801146a: 623b str r3, [r7, #32] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 801146c: 4b37 ldr r3, [pc, #220] @ (801154c ) 801146e: 6adb ldr r3, [r3, #44] @ 0x2c 8011470: 0a1b lsrs r3, r3, #8 8011472: f003 030f and.w r3, r3, #15 8011476: 3302 adds r3, #2 8011478: 61fb str r3, [r7, #28] pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); 801147a: 69fb ldr r3, [r7, #28] 801147c: 2200 movs r2, #0 801147e: 469a mov sl, r3 8011480: 4693 mov fp, r2 8011482: 6a7b ldr r3, [r7, #36] @ 0x24 8011484: 2200 movs r2, #0 8011486: 613b str r3, [r7, #16] 8011488: 617a str r2, [r7, #20] 801148a: 693b ldr r3, [r7, #16] 801148c: fb03 f20b mul.w r2, r3, fp 8011490: 697b ldr r3, [r7, #20] 8011492: fb0a f303 mul.w r3, sl, r3 8011496: 4413 add r3, r2 8011498: 693a ldr r2, [r7, #16] 801149a: fbaa 0102 umull r0, r1, sl, r2 801149e: 440b add r3, r1 80114a0: 4619 mov r1, r3 80114a2: 4b2b ldr r3, [pc, #172] @ (8011550 ) 80114a4: fb03 f201 mul.w r2, r3, r1 80114a8: 2300 movs r3, #0 80114aa: fb00 f303 mul.w r3, r0, r3 80114ae: 4413 add r3, r2 80114b0: 4a27 ldr r2, [pc, #156] @ (8011550 ) 80114b2: fba0 4502 umull r4, r5, r0, r2 80114b6: 442b add r3, r5 80114b8: 461d mov r5, r3 80114ba: 6a3b ldr r3, [r7, #32] 80114bc: 2200 movs r2, #0 80114be: 60bb str r3, [r7, #8] 80114c0: 60fa str r2, [r7, #12] 80114c2: 6abb ldr r3, [r7, #40] @ 0x28 80114c4: 2200 movs r2, #0 80114c6: 603b str r3, [r7, #0] 80114c8: 607a str r2, [r7, #4] 80114ca: e9d7 0102 ldrd r0, r1, [r7, #8] 80114ce: 460b mov r3, r1 80114d0: e9d7 ab00 ldrd sl, fp, [r7] 80114d4: 4652 mov r2, sl 80114d6: fb02 f203 mul.w r2, r2, r3 80114da: 465b mov r3, fp 80114dc: 4684 mov ip, r0 80114de: fb0c f303 mul.w r3, ip, r3 80114e2: 4413 add r3, r2 80114e4: 4602 mov r2, r0 80114e6: 4651 mov r1, sl 80114e8: fba2 8901 umull r8, r9, r2, r1 80114ec: 444b add r3, r9 80114ee: 4699 mov r9, r3 80114f0: 4642 mov r2, r8 80114f2: 464b mov r3, r9 80114f4: 4620 mov r0, r4 80114f6: 4629 mov r1, r5 80114f8: f7f7 fe7c bl 80091f4 <__aeabi_uldivmod> 80114fc: 4602 mov r2, r0 80114fe: 460b mov r3, r1 8011500: 4613 mov r3, r2 8011502: 637b str r3, [r7, #52] @ 0x34 8011504: e007 b.n 8011516 } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8011506: 6a7b ldr r3, [r7, #36] @ 0x24 8011508: 4a11 ldr r2, [pc, #68] @ (8011550 ) 801150a: fb03 f202 mul.w r2, r3, r2 801150e: 6abb ldr r3, [r7, #40] @ 0x28 8011510: fbb2 f3f3 udiv r3, r2, r3 8011514: 637b str r3, [r7, #52] @ 0x34 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 8011516: 4b0f ldr r3, [pc, #60] @ (8011554 ) 8011518: 7b5b ldrb r3, [r3, #13] 801151a: 461a mov r2, r3 801151c: 6a7b ldr r3, [r7, #36] @ 0x24 801151e: 4293 cmp r3, r2 8011520: d108 bne.n 8011534 { pllclk = pllclk / 2; 8011522: 6b7b ldr r3, [r7, #52] @ 0x34 8011524: 085b lsrs r3, r3, #1 8011526: 637b str r3, [r7, #52] @ 0x34 8011528: e004 b.n 8011534 #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 801152a: 6a7b ldr r3, [r7, #36] @ 0x24 801152c: 4a0b ldr r2, [pc, #44] @ (801155c ) 801152e: fb02 f303 mul.w r3, r2, r3 8011532: 637b str r3, [r7, #52] @ 0x34 } sysclockfreq = pllclk; 8011534: 6b7b ldr r3, [r7, #52] @ 0x34 8011536: 633b str r3, [r7, #48] @ 0x30 break; 8011538: e002 b.n 8011540 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 801153a: 4b09 ldr r3, [pc, #36] @ (8011560 ) 801153c: 633b str r3, [r7, #48] @ 0x30 break; 801153e: bf00 nop } } return sysclockfreq; 8011540: 6b3b ldr r3, [r7, #48] @ 0x30 } 8011542: 4618 mov r0, r3 8011544: 3738 adds r7, #56 @ 0x38 8011546: 46bd mov sp, r7 8011548: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 801154c: 40021000 .word 0x40021000 8011550: 017d7840 .word 0x017d7840 8011554: 080178ac .word 0x080178ac 8011558: 080178bc .word 0x080178bc 801155c: 003d0900 .word 0x003d0900 8011560: 007a1200 .word 0x007a1200 08011564 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8011564: b480 push {r7} 8011566: af00 add r7, sp, #0 return SystemCoreClock; 8011568: 4b02 ldr r3, [pc, #8] @ (8011574 ) 801156a: 681b ldr r3, [r3, #0] } 801156c: 4618 mov r0, r3 801156e: 46bd mov sp, r7 8011570: bc80 pop {r7} 8011572: 4770 bx lr 8011574: 20000084 .word 0x20000084 08011578 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8011578: b580 push {r7, lr} 801157a: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 801157c: f7ff fff2 bl 8011564 8011580: 4602 mov r2, r0 8011582: 4b05 ldr r3, [pc, #20] @ (8011598 ) 8011584: 685b ldr r3, [r3, #4] 8011586: 0a1b lsrs r3, r3, #8 8011588: f003 0307 and.w r3, r3, #7 801158c: 4903 ldr r1, [pc, #12] @ (801159c ) 801158e: 5ccb ldrb r3, [r1, r3] 8011590: fa22 f303 lsr.w r3, r2, r3 } 8011594: 4618 mov r0, r3 8011596: bd80 pop {r7, pc} 8011598: 40021000 .word 0x40021000 801159c: 080178a4 .word 0x080178a4 080115a0 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 80115a0: b580 push {r7, lr} 80115a2: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 80115a4: f7ff ffde bl 8011564 80115a8: 4602 mov r2, r0 80115aa: 4b05 ldr r3, [pc, #20] @ (80115c0 ) 80115ac: 685b ldr r3, [r3, #4] 80115ae: 0adb lsrs r3, r3, #11 80115b0: f003 0307 and.w r3, r3, #7 80115b4: 4903 ldr r1, [pc, #12] @ (80115c4 ) 80115b6: 5ccb ldrb r3, [r1, r3] 80115b8: fa22 f303 lsr.w r3, r2, r3 } 80115bc: 4618 mov r0, r3 80115be: bd80 pop {r7, pc} 80115c0: 40021000 .word 0x40021000 80115c4: 080178a4 .word 0x080178a4 080115c8 : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 80115c8: b480 push {r7} 80115ca: b085 sub sp, #20 80115cc: af00 add r7, sp, #0 80115ce: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 80115d0: 4b0a ldr r3, [pc, #40] @ (80115fc ) 80115d2: 681b ldr r3, [r3, #0] 80115d4: 4a0a ldr r2, [pc, #40] @ (8011600 ) 80115d6: fba2 2303 umull r2, r3, r2, r3 80115da: 0a5b lsrs r3, r3, #9 80115dc: 687a ldr r2, [r7, #4] 80115de: fb02 f303 mul.w r3, r2, r3 80115e2: 60fb str r3, [r7, #12] do { __NOP(); 80115e4: bf00 nop } while (Delay --); 80115e6: 68fb ldr r3, [r7, #12] 80115e8: 1e5a subs r2, r3, #1 80115ea: 60fa str r2, [r7, #12] 80115ec: 2b00 cmp r3, #0 80115ee: d1f9 bne.n 80115e4 } 80115f0: bf00 nop 80115f2: bf00 nop 80115f4: 3714 adds r7, #20 80115f6: 46bd mov sp, r7 80115f8: bc80 pop {r7} 80115fa: 4770 bx lr 80115fc: 20000084 .word 0x20000084 8011600: 10624dd3 .word 0x10624dd3 08011604 : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8011604: b580 push {r7, lr} 8011606: b088 sub sp, #32 8011608: af00 add r7, sp, #0 801160a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 801160c: 2300 movs r3, #0 801160e: 617b str r3, [r7, #20] 8011610: 2300 movs r3, #0 8011612: 613b str r3, [r7, #16] #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t pllactive = 0U; 8011614: 2300 movs r3, #0 8011616: 61fb str r3, [r7, #28] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 8011618: 687b ldr r3, [r7, #4] 801161a: 681b ldr r3, [r3, #0] 801161c: f003 0301 and.w r3, r3, #1 8011620: 2b00 cmp r3, #0 8011622: d07d beq.n 8011720 { FlagStatus pwrclkchanged = RESET; 8011624: 2300 movs r3, #0 8011626: 76fb strb r3, [r7, #27] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8011628: 4b8b ldr r3, [pc, #556] @ (8011858 ) 801162a: 69db ldr r3, [r3, #28] 801162c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011630: 2b00 cmp r3, #0 8011632: d10d bne.n 8011650 { __HAL_RCC_PWR_CLK_ENABLE(); 8011634: 4b88 ldr r3, [pc, #544] @ (8011858 ) 8011636: 69db ldr r3, [r3, #28] 8011638: 4a87 ldr r2, [pc, #540] @ (8011858 ) 801163a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 801163e: 61d3 str r3, [r2, #28] 8011640: 4b85 ldr r3, [pc, #532] @ (8011858 ) 8011642: 69db ldr r3, [r3, #28] 8011644: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011648: 60fb str r3, [r7, #12] 801164a: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 801164c: 2301 movs r3, #1 801164e: 76fb strb r3, [r7, #27] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8011650: 4b82 ldr r3, [pc, #520] @ (801185c ) 8011652: 681b ldr r3, [r3, #0] 8011654: f403 7380 and.w r3, r3, #256 @ 0x100 8011658: 2b00 cmp r3, #0 801165a: d118 bne.n 801168e { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 801165c: 4b7f ldr r3, [pc, #508] @ (801185c ) 801165e: 681b ldr r3, [r3, #0] 8011660: 4a7e ldr r2, [pc, #504] @ (801185c ) 8011662: f443 7380 orr.w r3, r3, #256 @ 0x100 8011666: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8011668: f7fc fe34 bl 800e2d4 801166c: 6178 str r0, [r7, #20] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 801166e: e008 b.n 8011682 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8011670: f7fc fe30 bl 800e2d4 8011674: 4602 mov r2, r0 8011676: 697b ldr r3, [r7, #20] 8011678: 1ad3 subs r3, r2, r3 801167a: 2b64 cmp r3, #100 @ 0x64 801167c: d901 bls.n 8011682 { return HAL_TIMEOUT; 801167e: 2303 movs r3, #3 8011680: e0e5 b.n 801184e while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8011682: 4b76 ldr r3, [pc, #472] @ (801185c ) 8011684: 681b ldr r3, [r3, #0] 8011686: f403 7380 and.w r3, r3, #256 @ 0x100 801168a: 2b00 cmp r3, #0 801168c: d0f0 beq.n 8011670 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 801168e: 4b72 ldr r3, [pc, #456] @ (8011858 ) 8011690: 6a1b ldr r3, [r3, #32] 8011692: f403 7340 and.w r3, r3, #768 @ 0x300 8011696: 613b str r3, [r7, #16] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8011698: 693b ldr r3, [r7, #16] 801169a: 2b00 cmp r3, #0 801169c: d02e beq.n 80116fc 801169e: 687b ldr r3, [r7, #4] 80116a0: 685b ldr r3, [r3, #4] 80116a2: f403 7340 and.w r3, r3, #768 @ 0x300 80116a6: 693a ldr r2, [r7, #16] 80116a8: 429a cmp r2, r3 80116aa: d027 beq.n 80116fc { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 80116ac: 4b6a ldr r3, [pc, #424] @ (8011858 ) 80116ae: 6a1b ldr r3, [r3, #32] 80116b0: f423 7340 bic.w r3, r3, #768 @ 0x300 80116b4: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80116b6: 4b6a ldr r3, [pc, #424] @ (8011860 ) 80116b8: 2201 movs r2, #1 80116ba: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 80116bc: 4b68 ldr r3, [pc, #416] @ (8011860 ) 80116be: 2200 movs r2, #0 80116c0: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 80116c2: 4a65 ldr r2, [pc, #404] @ (8011858 ) 80116c4: 693b ldr r3, [r7, #16] 80116c6: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 80116c8: 693b ldr r3, [r7, #16] 80116ca: f003 0301 and.w r3, r3, #1 80116ce: 2b00 cmp r3, #0 80116d0: d014 beq.n 80116fc { /* Get Start Tick */ tickstart = HAL_GetTick(); 80116d2: f7fc fdff bl 800e2d4 80116d6: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80116d8: e00a b.n 80116f0 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80116da: f7fc fdfb bl 800e2d4 80116de: 4602 mov r2, r0 80116e0: 697b ldr r3, [r7, #20] 80116e2: 1ad3 subs r3, r2, r3 80116e4: f241 3288 movw r2, #5000 @ 0x1388 80116e8: 4293 cmp r3, r2 80116ea: d901 bls.n 80116f0 { return HAL_TIMEOUT; 80116ec: 2303 movs r3, #3 80116ee: e0ae b.n 801184e while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80116f0: 4b59 ldr r3, [pc, #356] @ (8011858 ) 80116f2: 6a1b ldr r3, [r3, #32] 80116f4: f003 0302 and.w r3, r3, #2 80116f8: 2b00 cmp r3, #0 80116fa: d0ee beq.n 80116da } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80116fc: 4b56 ldr r3, [pc, #344] @ (8011858 ) 80116fe: 6a1b ldr r3, [r3, #32] 8011700: f423 7240 bic.w r2, r3, #768 @ 0x300 8011704: 687b ldr r3, [r7, #4] 8011706: 685b ldr r3, [r3, #4] 8011708: 4953 ldr r1, [pc, #332] @ (8011858 ) 801170a: 4313 orrs r3, r2 801170c: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 801170e: 7efb ldrb r3, [r7, #27] 8011710: 2b01 cmp r3, #1 8011712: d105 bne.n 8011720 { __HAL_RCC_PWR_CLK_DISABLE(); 8011714: 4b50 ldr r3, [pc, #320] @ (8011858 ) 8011716: 69db ldr r3, [r3, #28] 8011718: 4a4f ldr r2, [pc, #316] @ (8011858 ) 801171a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 801171e: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8011720: 687b ldr r3, [r7, #4] 8011722: 681b ldr r3, [r3, #0] 8011724: f003 0302 and.w r3, r3, #2 8011728: 2b00 cmp r3, #0 801172a: d008 beq.n 801173e { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 801172c: 4b4a ldr r3, [pc, #296] @ (8011858 ) 801172e: 685b ldr r3, [r3, #4] 8011730: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8011734: 687b ldr r3, [r7, #4] 8011736: 689b ldr r3, [r3, #8] 8011738: 4947 ldr r1, [pc, #284] @ (8011858 ) 801173a: 4313 orrs r3, r2 801173c: 604b str r3, [r1, #4] } #if defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ I2S2 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) 801173e: 687b ldr r3, [r7, #4] 8011740: 681b ldr r3, [r3, #0] 8011742: f003 0304 and.w r3, r3, #4 8011746: 2b00 cmp r3, #0 8011748: d008 beq.n 801175c { /* Check the parameters */ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); /* Configure the I2S2 clock source */ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); 801174a: 4b43 ldr r3, [pc, #268] @ (8011858 ) 801174c: 6adb ldr r3, [r3, #44] @ 0x2c 801174e: f423 3200 bic.w r2, r3, #131072 @ 0x20000 8011752: 687b ldr r3, [r7, #4] 8011754: 68db ldr r3, [r3, #12] 8011756: 4940 ldr r1, [pc, #256] @ (8011858 ) 8011758: 4313 orrs r3, r2 801175a: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ I2S3 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) 801175c: 687b ldr r3, [r7, #4] 801175e: 681b ldr r3, [r3, #0] 8011760: f003 0308 and.w r3, r3, #8 8011764: 2b00 cmp r3, #0 8011766: d008 beq.n 801177a { /* Check the parameters */ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); /* Configure the I2S3 clock source */ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); 8011768: 4b3b ldr r3, [pc, #236] @ (8011858 ) 801176a: 6adb ldr r3, [r3, #44] @ 0x2c 801176c: f423 2280 bic.w r2, r3, #262144 @ 0x40000 8011770: 687b ldr r3, [r7, #4] 8011772: 691b ldr r3, [r3, #16] 8011774: 4938 ldr r1, [pc, #224] @ (8011858 ) 8011776: 4313 orrs r3, r2 8011778: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ PLL I2S Configuration ----------------------*/ /* Check that PLLI2S need to be enabled */ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) 801177a: 4b37 ldr r3, [pc, #220] @ (8011858 ) 801177c: 6adb ldr r3, [r3, #44] @ 0x2c 801177e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8011782: 2b00 cmp r3, #0 8011784: d105 bne.n 8011792 8011786: 4b34 ldr r3, [pc, #208] @ (8011858 ) 8011788: 6adb ldr r3, [r3, #44] @ 0x2c 801178a: f403 2380 and.w r3, r3, #262144 @ 0x40000 801178e: 2b00 cmp r3, #0 8011790: d001 beq.n 8011796 { /* Update flag to indicate that PLL I2S should be active */ pllactive = 1; 8011792: 2301 movs r3, #1 8011794: 61fb str r3, [r7, #28] } /* Check if PLL I2S need to be enabled */ if (pllactive == 1) 8011796: 69fb ldr r3, [r7, #28] 8011798: 2b01 cmp r3, #1 801179a: d148 bne.n 801182e { /* Enable PLL I2S only if not active */ if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) 801179c: 4b2e ldr r3, [pc, #184] @ (8011858 ) 801179e: 681b ldr r3, [r3, #0] 80117a0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80117a4: 2b00 cmp r3, #0 80117a6: d138 bne.n 801181a assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); /* Prediv2 can be written only when the PLL2 is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 80117a8: 4b2b ldr r3, [pc, #172] @ (8011858 ) 80117aa: 681b ldr r3, [r3, #0] 80117ac: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 80117b0: 2b00 cmp r3, #0 80117b2: d009 beq.n 80117c8 (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) 80117b4: 4b28 ldr r3, [pc, #160] @ (8011858 ) 80117b6: 6adb ldr r3, [r3, #44] @ 0x2c 80117b8: f003 02f0 and.w r2, r3, #240 @ 0xf0 80117bc: 687b ldr r3, [r7, #4] 80117be: 699b ldr r3, [r3, #24] if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 80117c0: 429a cmp r2, r3 80117c2: d001 beq.n 80117c8 { return HAL_ERROR; 80117c4: 2301 movs r3, #1 80117c6: e042 b.n 801184e } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); 80117c8: 4b23 ldr r3, [pc, #140] @ (8011858 ) 80117ca: 6adb ldr r3, [r3, #44] @ 0x2c 80117cc: f023 02f0 bic.w r2, r3, #240 @ 0xf0 80117d0: 687b ldr r3, [r7, #4] 80117d2: 699b ldr r3, [r3, #24] 80117d4: 4920 ldr r1, [pc, #128] @ (8011858 ) 80117d6: 4313 orrs r3, r2 80117d8: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); 80117da: 4b1f ldr r3, [pc, #124] @ (8011858 ) 80117dc: 6adb ldr r3, [r3, #44] @ 0x2c 80117de: f423 4270 bic.w r2, r3, #61440 @ 0xf000 80117e2: 687b ldr r3, [r7, #4] 80117e4: 695b ldr r3, [r3, #20] 80117e6: 491c ldr r1, [pc, #112] @ (8011858 ) 80117e8: 4313 orrs r3, r2 80117ea: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); 80117ec: 4b1d ldr r3, [pc, #116] @ (8011864 ) 80117ee: 2201 movs r2, #1 80117f0: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80117f2: f7fc fd6f bl 800e2d4 80117f6: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 80117f8: e008 b.n 801180c { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 80117fa: f7fc fd6b bl 800e2d4 80117fe: 4602 mov r2, r0 8011800: 697b ldr r3, [r7, #20] 8011802: 1ad3 subs r3, r2, r3 8011804: 2b64 cmp r3, #100 @ 0x64 8011806: d901 bls.n 801180c { return HAL_TIMEOUT; 8011808: 2303 movs r3, #3 801180a: e020 b.n 801184e while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 801180c: 4b12 ldr r3, [pc, #72] @ (8011858 ) 801180e: 681b ldr r3, [r3, #0] 8011810: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8011814: 2b00 cmp r3, #0 8011816: d0f0 beq.n 80117fa 8011818: e009 b.n 801182e } } else { /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) 801181a: 4b0f ldr r3, [pc, #60] @ (8011858 ) 801181c: 6adb ldr r3, [r3, #44] @ 0x2c 801181e: f403 4270 and.w r2, r3, #61440 @ 0xf000 8011822: 687b ldr r3, [r7, #4] 8011824: 695b ldr r3, [r3, #20] 8011826: 429a cmp r2, r3 8011828: d001 beq.n 801182e { return HAL_ERROR; 801182a: 2301 movs r3, #1 801182c: e00f b.n 801184e #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 801182e: 687b ldr r3, [r7, #4] 8011830: 681b ldr r3, [r3, #0] 8011832: f003 0310 and.w r3, r3, #16 8011836: 2b00 cmp r3, #0 8011838: d008 beq.n 801184c { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 801183a: 4b07 ldr r3, [pc, #28] @ (8011858 ) 801183c: 685b ldr r3, [r3, #4] 801183e: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 8011842: 687b ldr r3, [r7, #4] 8011844: 69db ldr r3, [r3, #28] 8011846: 4904 ldr r1, [pc, #16] @ (8011858 ) 8011848: 4313 orrs r3, r2 801184a: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 801184c: 2300 movs r3, #0 } 801184e: 4618 mov r0, r3 8011850: 3720 adds r7, #32 8011852: 46bd mov sp, r7 8011854: bd80 pop {r7, pc} 8011856: bf00 nop 8011858: 40021000 .word 0x40021000 801185c: 40007000 .word 0x40007000 8011860: 42420440 .word 0x42420440 8011864: 42420070 .word 0x42420070 08011868 : * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 8011868: b580 push {r7, lr} 801186a: b08a sub sp, #40 @ 0x28 801186c: af00 add r7, sp, #0 801186e: 6078 str r0, [r7, #4] #if defined(STM32F105xC) || defined(STM32F107xC) static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; 8011870: 2300 movs r3, #0 8011872: 61fb str r3, [r7, #28] 8011874: 2300 movs r3, #0 8011876: 627b str r3, [r7, #36] @ 0x24 8011878: 2300 movs r3, #0 801187a: 61bb str r3, [r7, #24] uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; 801187c: 2300 movs r3, #0 801187e: 617b str r3, [r7, #20] 8011880: 2300 movs r3, #0 8011882: 613b str r3, [r7, #16] 8011884: 2300 movs r3, #0 8011886: 60fb str r3, [r7, #12] static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; static const uint8_t aPredivFactorTable[2U] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 8011888: 2300 movs r3, #0 801188a: 60bb str r3, [r7, #8] 801188c: 2300 movs r3, #0 801188e: 623b str r3, [r7, #32] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 8011890: 687b ldr r3, [r7, #4] 8011892: 3b01 subs r3, #1 8011894: 2b0f cmp r3, #15 8011896: f200 811d bhi.w 8011ad4 801189a: a201 add r2, pc, #4 @ (adr r2, 80118a0 ) 801189c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80118a0: 08011a55 .word 0x08011a55 80118a4: 08011ab9 .word 0x08011ab9 80118a8: 08011ad5 .word 0x08011ad5 80118ac: 080119b3 .word 0x080119b3 80118b0: 08011ad5 .word 0x08011ad5 80118b4: 08011ad5 .word 0x08011ad5 80118b8: 08011ad5 .word 0x08011ad5 80118bc: 08011a05 .word 0x08011a05 80118c0: 08011ad5 .word 0x08011ad5 80118c4: 08011ad5 .word 0x08011ad5 80118c8: 08011ad5 .word 0x08011ad5 80118cc: 08011ad5 .word 0x08011ad5 80118d0: 08011ad5 .word 0x08011ad5 80118d4: 08011ad5 .word 0x08011ad5 80118d8: 08011ad5 .word 0x08011ad5 80118dc: 080118e1 .word 0x080118e1 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_USB: { /* Get RCC configuration ------------------------------------------------------*/ temp_reg = RCC->CFGR; 80118e0: 4b83 ldr r3, [pc, #524] @ (8011af0 ) 80118e2: 685b ldr r3, [r3, #4] 80118e4: 60bb str r3, [r7, #8] /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) 80118e6: 4b82 ldr r3, [pc, #520] @ (8011af0 ) 80118e8: 681b ldr r3, [r3, #0] 80118ea: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80118ee: 2b00 cmp r3, #0 80118f0: f000 80f2 beq.w 8011ad8 { pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 80118f4: 68bb ldr r3, [r7, #8] 80118f6: 0c9b lsrs r3, r3, #18 80118f8: f003 030f and.w r3, r3, #15 80118fc: 4a7d ldr r2, [pc, #500] @ (8011af4 ) 80118fe: 5cd3 ldrb r3, [r2, r3] 8011900: 61bb str r3, [r7, #24] if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8011902: 68bb ldr r3, [r7, #8] 8011904: f403 3380 and.w r3, r3, #65536 @ 0x10000 8011908: 2b00 cmp r3, #0 801190a: d03b beq.n 8011984 { #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ || defined(STM32F100xE) prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 801190c: 4b78 ldr r3, [pc, #480] @ (8011af0 ) 801190e: 6adb ldr r3, [r3, #44] @ 0x2c 8011910: f003 030f and.w r3, r3, #15 8011914: 4a78 ldr r2, [pc, #480] @ (8011af8 ) 8011916: 5cd3 ldrb r3, [r2, r3] 8011918: 61fb str r3, [r7, #28] #else prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 801191a: 4b75 ldr r3, [pc, #468] @ (8011af0 ) 801191c: 6adb ldr r3, [r3, #44] @ 0x2c 801191e: f403 3380 and.w r3, r3, #65536 @ 0x10000 8011922: 2b00 cmp r3, #0 8011924: d01c beq.n 8011960 { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8011926: 4b72 ldr r3, [pc, #456] @ (8011af0 ) 8011928: 6adb ldr r3, [r3, #44] @ 0x2c 801192a: 091b lsrs r3, r3, #4 801192c: f003 030f and.w r3, r3, #15 8011930: 3301 adds r3, #1 8011932: 60fb str r3, [r7, #12] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 8011934: 4b6e ldr r3, [pc, #440] @ (8011af0 ) 8011936: 6adb ldr r3, [r3, #44] @ 0x2c 8011938: 0a1b lsrs r3, r3, #8 801193a: f003 030f and.w r3, r3, #15 801193e: 3302 adds r3, #2 8011940: 617b str r3, [r7, #20] pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); 8011942: 4a6e ldr r2, [pc, #440] @ (8011afc ) 8011944: 68fb ldr r3, [r7, #12] 8011946: fbb2 f3f3 udiv r3, r2, r3 801194a: 697a ldr r2, [r7, #20] 801194c: fb03 f202 mul.w r2, r3, r2 8011950: 69fb ldr r3, [r7, #28] 8011952: fbb2 f2f3 udiv r2, r2, r3 8011956: 69bb ldr r3, [r7, #24] 8011958: fb02 f303 mul.w r3, r2, r3 801195c: 627b str r3, [r7, #36] @ 0x24 801195e: e007 b.n 8011970 } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); 8011960: 4a66 ldr r2, [pc, #408] @ (8011afc ) 8011962: 69fb ldr r3, [r7, #28] 8011964: fbb2 f2f3 udiv r2, r2, r3 8011968: 69bb ldr r3, [r7, #24] 801196a: fb02 f303 mul.w r3, r2, r3 801196e: 627b str r3, [r7, #36] @ 0x24 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 8011970: 4b60 ldr r3, [pc, #384] @ (8011af4 ) 8011972: 7b5b ldrb r3, [r3, #13] 8011974: 461a mov r2, r3 8011976: 69bb ldr r3, [r7, #24] 8011978: 4293 cmp r3, r2 801197a: d108 bne.n 801198e { pllclk = pllclk / 2; 801197c: 6a7b ldr r3, [r7, #36] @ 0x24 801197e: 085b lsrs r3, r3, #1 8011980: 627b str r3, [r7, #36] @ 0x24 8011982: e004 b.n 801198e #endif /* STM32F105xC || STM32F107xC */ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8011984: 69bb ldr r3, [r7, #24] 8011986: 4a5e ldr r2, [pc, #376] @ (8011b00 ) 8011988: fb02 f303 mul.w r3, r2, r3 801198c: 627b str r3, [r7, #36] @ 0x24 } /* Calcul of the USB frequency*/ #if defined(STM32F105xC) || defined(STM32F107xC) /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) 801198e: 4b58 ldr r3, [pc, #352] @ (8011af0 ) 8011990: 685b ldr r3, [r3, #4] 8011992: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8011996: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 801199a: d102 bne.n 80119a2 { /* Prescaler of 2 selected for USB */ frequency = pllclk; 801199c: 6a7b ldr r3, [r7, #36] @ 0x24 801199e: 623b str r3, [r7, #32] /* Prescaler of 1.5 selected for USB */ frequency = (pllclk * 2) / 3; } #endif } break; 80119a0: e09a b.n 8011ad8 frequency = (2 * pllclk) / 3; 80119a2: 6a7b ldr r3, [r7, #36] @ 0x24 80119a4: 005b lsls r3, r3, #1 80119a6: 4a57 ldr r2, [pc, #348] @ (8011b04 ) 80119a8: fba2 2303 umull r2, r3, r2, r3 80119ac: 085b lsrs r3, r3, #1 80119ae: 623b str r3, [r7, #32] break; 80119b0: e092 b.n 8011ad8 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) 80119b2: 4b4f ldr r3, [pc, #316] @ (8011af0 ) 80119b4: 6adb ldr r3, [r3, #44] @ 0x2c 80119b6: f403 3300 and.w r3, r3, #131072 @ 0x20000 80119ba: 2b00 cmp r3, #0 80119bc: d103 bne.n 80119c6 { /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); 80119be: f7ff fd15 bl 80113ec 80119c2: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 80119c4: e08a b.n 8011adc if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 80119c6: 4b4a ldr r3, [pc, #296] @ (8011af0 ) 80119c8: 681b ldr r3, [r3, #0] 80119ca: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80119ce: 2b00 cmp r3, #0 80119d0: f000 8084 beq.w 8011adc prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 80119d4: 4b46 ldr r3, [pc, #280] @ (8011af0 ) 80119d6: 6adb ldr r3, [r3, #44] @ 0x2c 80119d8: 091b lsrs r3, r3, #4 80119da: f003 030f and.w r3, r3, #15 80119de: 3301 adds r3, #1 80119e0: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 80119e2: 4b43 ldr r3, [pc, #268] @ (8011af0 ) 80119e4: 6adb ldr r3, [r3, #44] @ 0x2c 80119e6: 0b1b lsrs r3, r3, #12 80119e8: f003 030f and.w r3, r3, #15 80119ec: 3302 adds r3, #2 80119ee: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 80119f0: 4a42 ldr r2, [pc, #264] @ (8011afc ) 80119f2: 68fb ldr r3, [r7, #12] 80119f4: fbb2 f3f3 udiv r3, r2, r3 80119f8: 693a ldr r2, [r7, #16] 80119fa: fb02 f303 mul.w r3, r2, r3 80119fe: 005b lsls r3, r3, #1 8011a00: 623b str r3, [r7, #32] break; 8011a02: e06b b.n 8011adc { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) 8011a04: 4b3a ldr r3, [pc, #232] @ (8011af0 ) 8011a06: 6adb ldr r3, [r3, #44] @ 0x2c 8011a08: f403 2380 and.w r3, r3, #262144 @ 0x40000 8011a0c: 2b00 cmp r3, #0 8011a0e: d103 bne.n 8011a18 { /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); 8011a10: f7ff fcec bl 80113ec 8011a14: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8011a16: e063 b.n 8011ae0 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8011a18: 4b35 ldr r3, [pc, #212] @ (8011af0 ) 8011a1a: 681b ldr r3, [r3, #0] 8011a1c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011a20: 2b00 cmp r3, #0 8011a22: d05d beq.n 8011ae0 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8011a24: 4b32 ldr r3, [pc, #200] @ (8011af0 ) 8011a26: 6adb ldr r3, [r3, #44] @ 0x2c 8011a28: 091b lsrs r3, r3, #4 8011a2a: f003 030f and.w r3, r3, #15 8011a2e: 3301 adds r3, #1 8011a30: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 8011a32: 4b2f ldr r3, [pc, #188] @ (8011af0 ) 8011a34: 6adb ldr r3, [r3, #44] @ 0x2c 8011a36: 0b1b lsrs r3, r3, #12 8011a38: f003 030f and.w r3, r3, #15 8011a3c: 3302 adds r3, #2 8011a3e: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8011a40: 4a2e ldr r2, [pc, #184] @ (8011afc ) 8011a42: 68fb ldr r3, [r7, #12] 8011a44: fbb2 f3f3 udiv r3, r2, r3 8011a48: 693a ldr r2, [r7, #16] 8011a4a: fb02 f303 mul.w r3, r2, r3 8011a4e: 005b lsls r3, r3, #1 8011a50: 623b str r3, [r7, #32] break; 8011a52: e045 b.n 8011ae0 } #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ case RCC_PERIPHCLK_RTC: { /* Get RCC BDCR configuration ------------------------------------------------------*/ temp_reg = RCC->BDCR; 8011a54: 4b26 ldr r3, [pc, #152] @ (8011af0 ) 8011a56: 6a1b ldr r3, [r3, #32] 8011a58: 60bb str r3, [r7, #8] /* Check if LSE is ready if RTC clock selection is LSE */ if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 8011a5a: 68bb ldr r3, [r7, #8] 8011a5c: f403 7340 and.w r3, r3, #768 @ 0x300 8011a60: f5b3 7f80 cmp.w r3, #256 @ 0x100 8011a64: d108 bne.n 8011a78 8011a66: 68bb ldr r3, [r7, #8] 8011a68: f003 0302 and.w r3, r3, #2 8011a6c: 2b00 cmp r3, #0 8011a6e: d003 beq.n 8011a78 { frequency = LSE_VALUE; 8011a70: f44f 4300 mov.w r3, #32768 @ 0x8000 8011a74: 623b str r3, [r7, #32] 8011a76: e01e b.n 8011ab6 } /* Check if LSI is ready if RTC clock selection is LSI */ else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 8011a78: 68bb ldr r3, [r7, #8] 8011a7a: f403 7340 and.w r3, r3, #768 @ 0x300 8011a7e: f5b3 7f00 cmp.w r3, #512 @ 0x200 8011a82: d109 bne.n 8011a98 8011a84: 4b1a ldr r3, [pc, #104] @ (8011af0 ) 8011a86: 6a5b ldr r3, [r3, #36] @ 0x24 8011a88: f003 0302 and.w r3, r3, #2 8011a8c: 2b00 cmp r3, #0 8011a8e: d003 beq.n 8011a98 { frequency = LSI_VALUE; 8011a90: f649 4340 movw r3, #40000 @ 0x9c40 8011a94: 623b str r3, [r7, #32] 8011a96: e00e b.n 8011ab6 } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 8011a98: 68bb ldr r3, [r7, #8] 8011a9a: f403 7340 and.w r3, r3, #768 @ 0x300 8011a9e: f5b3 7f40 cmp.w r3, #768 @ 0x300 8011aa2: d11f bne.n 8011ae4 8011aa4: 4b12 ldr r3, [pc, #72] @ (8011af0 ) 8011aa6: 681b ldr r3, [r3, #0] 8011aa8: f403 3300 and.w r3, r3, #131072 @ 0x20000 8011aac: 2b00 cmp r3, #0 8011aae: d019 beq.n 8011ae4 { frequency = HSE_VALUE / 128U; 8011ab0: 4b15 ldr r3, [pc, #84] @ (8011b08 ) 8011ab2: 623b str r3, [r7, #32] /* Clock not enabled for RTC*/ else { /* nothing to do: frequency already initialized to 0U */ } break; 8011ab4: e016 b.n 8011ae4 8011ab6: e015 b.n 8011ae4 } case RCC_PERIPHCLK_ADC: { frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 8011ab8: f7ff fd72 bl 80115a0 8011abc: 4602 mov r2, r0 8011abe: 4b0c ldr r3, [pc, #48] @ (8011af0 ) 8011ac0: 685b ldr r3, [r3, #4] 8011ac2: 0b9b lsrs r3, r3, #14 8011ac4: f003 0303 and.w r3, r3, #3 8011ac8: 3301 adds r3, #1 8011aca: 005b lsls r3, r3, #1 8011acc: fbb2 f3f3 udiv r3, r2, r3 8011ad0: 623b str r3, [r7, #32] break; 8011ad2: e008 b.n 8011ae6 } default: { break; 8011ad4: bf00 nop 8011ad6: e006 b.n 8011ae6 break; 8011ad8: bf00 nop 8011ada: e004 b.n 8011ae6 break; 8011adc: bf00 nop 8011ade: e002 b.n 8011ae6 break; 8011ae0: bf00 nop 8011ae2: e000 b.n 8011ae6 break; 8011ae4: bf00 nop } } return (frequency); 8011ae6: 6a3b ldr r3, [r7, #32] } 8011ae8: 4618 mov r0, r3 8011aea: 3728 adds r7, #40 @ 0x28 8011aec: 46bd mov sp, r7 8011aee: bd80 pop {r7, pc} 8011af0: 40021000 .word 0x40021000 8011af4: 080178cc .word 0x080178cc 8011af8: 080178dc .word 0x080178dc 8011afc: 017d7840 .word 0x017d7840 8011b00: 003d0900 .word 0x003d0900 8011b04: aaaaaaab .word 0xaaaaaaab 8011b08: 0002faf0 .word 0x0002faf0 08011b0c : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { 8011b0c: b580 push {r7, lr} 8011b0e: b084 sub sp, #16 8011b10: af00 add r7, sp, #0 8011b12: 6078 str r0, [r7, #4] uint32_t prescaler = 0U; 8011b14: 2300 movs r3, #0 8011b16: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8011b18: 687b ldr r3, [r7, #4] 8011b1a: 2b00 cmp r3, #0 8011b1c: d101 bne.n 8011b22 { return HAL_ERROR; 8011b1e: 2301 movs r3, #1 8011b20: e07a b.n 8011c18 { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else if (hrtc->State == HAL_RTC_STATE_RESET) 8011b22: 687b ldr r3, [r7, #4] 8011b24: 7c5b ldrb r3, [r3, #17] 8011b26: b2db uxtb r3, r3 8011b28: 2b00 cmp r3, #0 8011b2a: d105 bne.n 8011b38 { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; 8011b2c: 687b ldr r3, [r7, #4] 8011b2e: 2200 movs r2, #0 8011b30: 741a strb r2, [r3, #16] /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); 8011b32: 6878 ldr r0, [r7, #4] 8011b34: f7f9 ffba bl 800baac } #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; 8011b38: 687b ldr r3, [r7, #4] 8011b3a: 2202 movs r2, #2 8011b3c: 745a strb r2, [r3, #17] /* Waiting for synchro */ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 8011b3e: 6878 ldr r0, [r7, #4] 8011b40: f000 f870 bl 8011c24 8011b44: 4603 mov r3, r0 8011b46: 2b00 cmp r3, #0 8011b48: d004 beq.n 8011b54 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8011b4a: 687b ldr r3, [r7, #4] 8011b4c: 2204 movs r2, #4 8011b4e: 745a strb r2, [r3, #17] return HAL_ERROR; 8011b50: 2301 movs r3, #1 8011b52: e061 b.n 8011c18 } /* Set Initialization mode */ if (RTC_EnterInitMode(hrtc) != HAL_OK) 8011b54: 6878 ldr r0, [r7, #4] 8011b56: f000 f892 bl 8011c7e 8011b5a: 4603 mov r3, r0 8011b5c: 2b00 cmp r3, #0 8011b5e: d004 beq.n 8011b6a { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8011b60: 687b ldr r3, [r7, #4] 8011b62: 2204 movs r2, #4 8011b64: 745a strb r2, [r3, #17] return HAL_ERROR; 8011b66: 2301 movs r3, #1 8011b68: e056 b.n 8011c18 } else { /* Clear Flags Bits */ CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); 8011b6a: 687b ldr r3, [r7, #4] 8011b6c: 681b ldr r3, [r3, #0] 8011b6e: 685a ldr r2, [r3, #4] 8011b70: 687b ldr r3, [r7, #4] 8011b72: 681b ldr r3, [r3, #0] 8011b74: f022 0207 bic.w r2, r2, #7 8011b78: 605a str r2, [r3, #4] if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) 8011b7a: 687b ldr r3, [r7, #4] 8011b7c: 689b ldr r3, [r3, #8] 8011b7e: 2b00 cmp r3, #0 8011b80: d005 beq.n 8011b8e { /* Disable the selected Tamper pin */ CLEAR_BIT(BKP->CR, BKP_CR_TPE); 8011b82: 4b27 ldr r3, [pc, #156] @ (8011c20 ) 8011b84: 6b1b ldr r3, [r3, #48] @ 0x30 8011b86: 4a26 ldr r2, [pc, #152] @ (8011c20 ) 8011b88: f023 0301 bic.w r3, r3, #1 8011b8c: 6313 str r3, [r2, #48] @ 0x30 } /* Set the signal which will be routed to RTC Tamper pin*/ MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); 8011b8e: 4b24 ldr r3, [pc, #144] @ (8011c20 ) 8011b90: 6adb ldr r3, [r3, #44] @ 0x2c 8011b92: f423 7260 bic.w r2, r3, #896 @ 0x380 8011b96: 687b ldr r3, [r7, #4] 8011b98: 689b ldr r3, [r3, #8] 8011b9a: 4921 ldr r1, [pc, #132] @ (8011c20 ) 8011b9c: 4313 orrs r3, r2 8011b9e: 62cb str r3, [r1, #44] @ 0x2c if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) 8011ba0: 687b ldr r3, [r7, #4] 8011ba2: 685b ldr r3, [r3, #4] 8011ba4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8011ba8: d003 beq.n 8011bb2 { /* RTC Prescaler provided directly by end-user*/ prescaler = hrtc->Init.AsynchPrediv; 8011baa: 687b ldr r3, [r7, #4] 8011bac: 685b ldr r3, [r3, #4] 8011bae: 60fb str r3, [r7, #12] 8011bb0: e00e b.n 8011bd0 } else { /* RTC Prescaler will be automatically calculated to get 1 second timebase */ /* Get the RTCCLK frequency */ prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); 8011bb2: 2001 movs r0, #1 8011bb4: f7ff fe58 bl 8011868 8011bb8: 60f8 str r0, [r7, #12] /* Check that RTC clock is enabled*/ if (prescaler == 0U) 8011bba: 68fb ldr r3, [r7, #12] 8011bbc: 2b00 cmp r3, #0 8011bbe: d104 bne.n 8011bca { /* Should not happen. Frequency is not available*/ hrtc->State = HAL_RTC_STATE_ERROR; 8011bc0: 687b ldr r3, [r7, #4] 8011bc2: 2204 movs r2, #4 8011bc4: 745a strb r2, [r3, #17] return HAL_ERROR; 8011bc6: 2301 movs r3, #1 8011bc8: e026 b.n 8011c18 } else { /* RTC period = RTCCLK/(RTC_PR + 1) */ prescaler = prescaler - 1U; 8011bca: 68fb ldr r3, [r7, #12] 8011bcc: 3b01 subs r3, #1 8011bce: 60fb str r3, [r7, #12] } } /* Configure the RTC_PRLH / RTC_PRLL */ WRITE_REG(hrtc->Instance->PRLH, ((prescaler >> 16U) & RTC_PRLH_PRL)); 8011bd0: 68fb ldr r3, [r7, #12] 8011bd2: 0c1a lsrs r2, r3, #16 8011bd4: 687b ldr r3, [r7, #4] 8011bd6: 681b ldr r3, [r3, #0] 8011bd8: f002 020f and.w r2, r2, #15 8011bdc: 609a str r2, [r3, #8] WRITE_REG(hrtc->Instance->PRLL, (prescaler & RTC_PRLL_PRL)); 8011bde: 687b ldr r3, [r7, #4] 8011be0: 681b ldr r3, [r3, #0] 8011be2: 68fa ldr r2, [r7, #12] 8011be4: b292 uxth r2, r2 8011be6: 60da str r2, [r3, #12] /* Wait for synchro */ if (RTC_ExitInitMode(hrtc) != HAL_OK) 8011be8: 6878 ldr r0, [r7, #4] 8011bea: f000 f870 bl 8011cce 8011bee: 4603 mov r3, r0 8011bf0: 2b00 cmp r3, #0 8011bf2: d004 beq.n 8011bfe { hrtc->State = HAL_RTC_STATE_ERROR; 8011bf4: 687b ldr r3, [r7, #4] 8011bf6: 2204 movs r2, #4 8011bf8: 745a strb r2, [r3, #17] return HAL_ERROR; 8011bfa: 2301 movs r3, #1 8011bfc: e00c b.n 8011c18 } /* Initialize date to 1st of January 2000 */ hrtc->DateToUpdate.Year = 0x00U; 8011bfe: 687b ldr r3, [r7, #4] 8011c00: 2200 movs r2, #0 8011c02: 73da strb r2, [r3, #15] hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; 8011c04: 687b ldr r3, [r7, #4] 8011c06: 2201 movs r2, #1 8011c08: 735a strb r2, [r3, #13] hrtc->DateToUpdate.Date = 0x01U; 8011c0a: 687b ldr r3, [r7, #4] 8011c0c: 2201 movs r2, #1 8011c0e: 739a strb r2, [r3, #14] /* Set RTC state */ hrtc->State = HAL_RTC_STATE_READY; 8011c10: 687b ldr r3, [r7, #4] 8011c12: 2201 movs r2, #1 8011c14: 745a strb r2, [r3, #17] return HAL_OK; 8011c16: 2300 movs r3, #0 } } 8011c18: 4618 mov r0, r3 8011c1a: 3710 adds r7, #16 8011c1c: 46bd mov sp, r7 8011c1e: bd80 pop {r7, pc} 8011c20: 40006c00 .word 0x40006c00 08011c24 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { 8011c24: b580 push {r7, lr} 8011c26: b084 sub sp, #16 8011c28: af00 add r7, sp, #0 8011c2a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8011c2c: 2300 movs r3, #0 8011c2e: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8011c30: 687b ldr r3, [r7, #4] 8011c32: 2b00 cmp r3, #0 8011c34: d101 bne.n 8011c3a { return HAL_ERROR; 8011c36: 2301 movs r3, #1 8011c38: e01d b.n 8011c76 } /* Clear RSF flag */ CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); 8011c3a: 687b ldr r3, [r7, #4] 8011c3c: 681b ldr r3, [r3, #0] 8011c3e: 685a ldr r2, [r3, #4] 8011c40: 687b ldr r3, [r7, #4] 8011c42: 681b ldr r3, [r3, #0] 8011c44: f022 0208 bic.w r2, r2, #8 8011c48: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8011c4a: f7fc fb43 bl 800e2d4 8011c4e: 60f8 str r0, [r7, #12] /* Wait the registers to be synchronised */ while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8011c50: e009 b.n 8011c66 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8011c52: f7fc fb3f bl 800e2d4 8011c56: 4602 mov r2, r0 8011c58: 68fb ldr r3, [r7, #12] 8011c5a: 1ad3 subs r3, r2, r3 8011c5c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8011c60: d901 bls.n 8011c66 { return HAL_TIMEOUT; 8011c62: 2303 movs r3, #3 8011c64: e007 b.n 8011c76 while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8011c66: 687b ldr r3, [r7, #4] 8011c68: 681b ldr r3, [r3, #0] 8011c6a: 685b ldr r3, [r3, #4] 8011c6c: f003 0308 and.w r3, r3, #8 8011c70: 2b00 cmp r3, #0 8011c72: d0ee beq.n 8011c52 } } return HAL_OK; 8011c74: 2300 movs r3, #0 } 8011c76: 4618 mov r0, r3 8011c78: 3710 adds r7, #16 8011c7a: 46bd mov sp, r7 8011c7c: bd80 pop {r7, pc} 08011c7e : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { 8011c7e: b580 push {r7, lr} 8011c80: b084 sub sp, #16 8011c82: af00 add r7, sp, #0 8011c84: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8011c86: 2300 movs r3, #0 8011c88: 60fb str r3, [r7, #12] tickstart = HAL_GetTick(); 8011c8a: f7fc fb23 bl 800e2d4 8011c8e: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8011c90: e009 b.n 8011ca6 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8011c92: f7fc fb1f bl 800e2d4 8011c96: 4602 mov r2, r0 8011c98: 68fb ldr r3, [r7, #12] 8011c9a: 1ad3 subs r3, r2, r3 8011c9c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8011ca0: d901 bls.n 8011ca6 { return HAL_TIMEOUT; 8011ca2: 2303 movs r3, #3 8011ca4: e00f b.n 8011cc6 while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8011ca6: 687b ldr r3, [r7, #4] 8011ca8: 681b ldr r3, [r3, #0] 8011caa: 685b ldr r3, [r3, #4] 8011cac: f003 0320 and.w r3, r3, #32 8011cb0: 2b00 cmp r3, #0 8011cb2: d0ee beq.n 8011c92 } } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 8011cb4: 687b ldr r3, [r7, #4] 8011cb6: 681b ldr r3, [r3, #0] 8011cb8: 685a ldr r2, [r3, #4] 8011cba: 687b ldr r3, [r7, #4] 8011cbc: 681b ldr r3, [r3, #0] 8011cbe: f042 0210 orr.w r2, r2, #16 8011cc2: 605a str r2, [r3, #4] return HAL_OK; 8011cc4: 2300 movs r3, #0 } 8011cc6: 4618 mov r0, r3 8011cc8: 3710 adds r7, #16 8011cca: 46bd mov sp, r7 8011ccc: bd80 pop {r7, pc} 08011cce : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) { 8011cce: b580 push {r7, lr} 8011cd0: b084 sub sp, #16 8011cd2: af00 add r7, sp, #0 8011cd4: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8011cd6: 2300 movs r3, #0 8011cd8: 60fb str r3, [r7, #12] /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 8011cda: 687b ldr r3, [r7, #4] 8011cdc: 681b ldr r3, [r3, #0] 8011cde: 685a ldr r2, [r3, #4] 8011ce0: 687b ldr r3, [r7, #4] 8011ce2: 681b ldr r3, [r3, #0] 8011ce4: f022 0210 bic.w r2, r2, #16 8011ce8: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8011cea: f7fc faf3 bl 800e2d4 8011cee: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8011cf0: e009 b.n 8011d06 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8011cf2: f7fc faef bl 800e2d4 8011cf6: 4602 mov r2, r0 8011cf8: 68fb ldr r3, [r7, #12] 8011cfa: 1ad3 subs r3, r2, r3 8011cfc: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8011d00: d901 bls.n 8011d06 { return HAL_TIMEOUT; 8011d02: 2303 movs r3, #3 8011d04: e007 b.n 8011d16 while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8011d06: 687b ldr r3, [r7, #4] 8011d08: 681b ldr r3, [r3, #0] 8011d0a: 685b ldr r3, [r3, #4] 8011d0c: f003 0320 and.w r3, r3, #32 8011d10: 2b00 cmp r3, #0 8011d12: d0ee beq.n 8011cf2 } } return HAL_OK; 8011d14: 2300 movs r3, #0 } 8011d16: 4618 mov r0, r3 8011d18: 3710 adds r7, #16 8011d1a: 46bd mov sp, r7 8011d1c: bd80 pop {r7, pc} 08011d1e : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8011d1e: b580 push {r7, lr} 8011d20: b082 sub sp, #8 8011d22: af00 add r7, sp, #0 8011d24: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8011d26: 687b ldr r3, [r7, #4] 8011d28: 2b00 cmp r3, #0 8011d2a: d101 bne.n 8011d30 { return HAL_ERROR; 8011d2c: 2301 movs r3, #1 8011d2e: e041 b.n 8011db4 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8011d30: 687b ldr r3, [r7, #4] 8011d32: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8011d36: b2db uxtb r3, r3 8011d38: 2b00 cmp r3, #0 8011d3a: d106 bne.n 8011d4a { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8011d3c: 687b ldr r3, [r7, #4] 8011d3e: 2200 movs r2, #0 8011d40: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8011d44: 6878 ldr r0, [r7, #4] 8011d46: f7fb ff01 bl 800db4c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8011d4a: 687b ldr r3, [r7, #4] 8011d4c: 2202 movs r2, #2 8011d4e: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8011d52: 687b ldr r3, [r7, #4] 8011d54: 681a ldr r2, [r3, #0] 8011d56: 687b ldr r3, [r7, #4] 8011d58: 3304 adds r3, #4 8011d5a: 4619 mov r1, r3 8011d5c: 4610 mov r0, r2 8011d5e: f000 fd33 bl 80127c8 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8011d62: 687b ldr r3, [r7, #4] 8011d64: 2201 movs r2, #1 8011d66: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011d6a: 687b ldr r3, [r7, #4] 8011d6c: 2201 movs r2, #1 8011d6e: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011d72: 687b ldr r3, [r7, #4] 8011d74: 2201 movs r2, #1 8011d76: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011d7a: 687b ldr r3, [r7, #4] 8011d7c: 2201 movs r2, #1 8011d7e: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011d82: 687b ldr r3, [r7, #4] 8011d84: 2201 movs r2, #1 8011d86: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011d8a: 687b ldr r3, [r7, #4] 8011d8c: 2201 movs r2, #1 8011d8e: f883 2042 strb.w r2, [r3, #66] @ 0x42 8011d92: 687b ldr r3, [r7, #4] 8011d94: 2201 movs r2, #1 8011d96: f883 2043 strb.w r2, [r3, #67] @ 0x43 8011d9a: 687b ldr r3, [r7, #4] 8011d9c: 2201 movs r2, #1 8011d9e: f883 2044 strb.w r2, [r3, #68] @ 0x44 8011da2: 687b ldr r3, [r7, #4] 8011da4: 2201 movs r2, #1 8011da6: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8011daa: 687b ldr r3, [r7, #4] 8011dac: 2201 movs r2, #1 8011dae: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8011db2: 2300 movs r3, #0 } 8011db4: 4618 mov r0, r3 8011db6: 3708 adds r7, #8 8011db8: 46bd mov sp, r7 8011dba: bd80 pop {r7, pc} 08011dbc : * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { 8011dbc: b580 push {r7, lr} 8011dbe: b082 sub sp, #8 8011dc0: af00 add r7, sp, #0 8011dc2: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8011dc4: 687b ldr r3, [r7, #4] 8011dc6: 2b00 cmp r3, #0 8011dc8: d101 bne.n 8011dce { return HAL_ERROR; 8011dca: 2301 movs r3, #1 8011dcc: e041 b.n 8011e52 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8011dce: 687b ldr r3, [r7, #4] 8011dd0: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8011dd4: b2db uxtb r3, r3 8011dd6: 2b00 cmp r3, #0 8011dd8: d106 bne.n 8011de8 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8011dda: 687b ldr r3, [r7, #4] 8011ddc: 2200 movs r2, #0 8011dde: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); 8011de2: 6878 ldr r0, [r7, #4] 8011de4: f000 f839 bl 8011e5a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8011de8: 687b ldr r3, [r7, #4] 8011dea: 2202 movs r2, #2 8011dec: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8011df0: 687b ldr r3, [r7, #4] 8011df2: 681a ldr r2, [r3, #0] 8011df4: 687b ldr r3, [r7, #4] 8011df6: 3304 adds r3, #4 8011df8: 4619 mov r1, r3 8011dfa: 4610 mov r0, r2 8011dfc: f000 fce4 bl 80127c8 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8011e00: 687b ldr r3, [r7, #4] 8011e02: 2201 movs r2, #1 8011e04: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011e08: 687b ldr r3, [r7, #4] 8011e0a: 2201 movs r2, #1 8011e0c: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011e10: 687b ldr r3, [r7, #4] 8011e12: 2201 movs r2, #1 8011e14: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011e18: 687b ldr r3, [r7, #4] 8011e1a: 2201 movs r2, #1 8011e1c: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011e20: 687b ldr r3, [r7, #4] 8011e22: 2201 movs r2, #1 8011e24: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011e28: 687b ldr r3, [r7, #4] 8011e2a: 2201 movs r2, #1 8011e2c: f883 2042 strb.w r2, [r3, #66] @ 0x42 8011e30: 687b ldr r3, [r7, #4] 8011e32: 2201 movs r2, #1 8011e34: f883 2043 strb.w r2, [r3, #67] @ 0x43 8011e38: 687b ldr r3, [r7, #4] 8011e3a: 2201 movs r2, #1 8011e3c: f883 2044 strb.w r2, [r3, #68] @ 0x44 8011e40: 687b ldr r3, [r7, #4] 8011e42: 2201 movs r2, #1 8011e44: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8011e48: 687b ldr r3, [r7, #4] 8011e4a: 2201 movs r2, #1 8011e4c: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8011e50: 2300 movs r3, #0 } 8011e52: 4618 mov r0, r3 8011e54: 3708 adds r7, #8 8011e56: 46bd mov sp, r7 8011e58: bd80 pop {r7, pc} 08011e5a : * @brief Initializes the TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) { 8011e5a: b480 push {r7} 8011e5c: b083 sub sp, #12 8011e5e: af00 add r7, sp, #0 8011e60: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspInit could be implemented in the user file */ } 8011e62: bf00 nop 8011e64: 370c adds r7, #12 8011e66: 46bd mov sp, r7 8011e68: bc80 pop {r7} 8011e6a: 4770 bx lr 08011e6c : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8011e6c: b580 push {r7, lr} 8011e6e: b084 sub sp, #16 8011e70: af00 add r7, sp, #0 8011e72: 6078 str r0, [r7, #4] 8011e74: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 8011e76: 683b ldr r3, [r7, #0] 8011e78: 2b00 cmp r3, #0 8011e7a: d109 bne.n 8011e90 8011e7c: 687b ldr r3, [r7, #4] 8011e7e: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8011e82: b2db uxtb r3, r3 8011e84: 2b01 cmp r3, #1 8011e86: bf14 ite ne 8011e88: 2301 movne r3, #1 8011e8a: 2300 moveq r3, #0 8011e8c: b2db uxtb r3, r3 8011e8e: e022 b.n 8011ed6 8011e90: 683b ldr r3, [r7, #0] 8011e92: 2b04 cmp r3, #4 8011e94: d109 bne.n 8011eaa 8011e96: 687b ldr r3, [r7, #4] 8011e98: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8011e9c: b2db uxtb r3, r3 8011e9e: 2b01 cmp r3, #1 8011ea0: bf14 ite ne 8011ea2: 2301 movne r3, #1 8011ea4: 2300 moveq r3, #0 8011ea6: b2db uxtb r3, r3 8011ea8: e015 b.n 8011ed6 8011eaa: 683b ldr r3, [r7, #0] 8011eac: 2b08 cmp r3, #8 8011eae: d109 bne.n 8011ec4 8011eb0: 687b ldr r3, [r7, #4] 8011eb2: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8011eb6: b2db uxtb r3, r3 8011eb8: 2b01 cmp r3, #1 8011eba: bf14 ite ne 8011ebc: 2301 movne r3, #1 8011ebe: 2300 moveq r3, #0 8011ec0: b2db uxtb r3, r3 8011ec2: e008 b.n 8011ed6 8011ec4: 687b ldr r3, [r7, #4] 8011ec6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011eca: b2db uxtb r3, r3 8011ecc: 2b01 cmp r3, #1 8011ece: bf14 ite ne 8011ed0: 2301 movne r3, #1 8011ed2: 2300 moveq r3, #0 8011ed4: b2db uxtb r3, r3 8011ed6: 2b00 cmp r3, #0 8011ed8: d001 beq.n 8011ede { return HAL_ERROR; 8011eda: 2301 movs r3, #1 8011edc: e063 b.n 8011fa6 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8011ede: 683b ldr r3, [r7, #0] 8011ee0: 2b00 cmp r3, #0 8011ee2: d104 bne.n 8011eee 8011ee4: 687b ldr r3, [r7, #4] 8011ee6: 2202 movs r2, #2 8011ee8: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011eec: e013 b.n 8011f16 8011eee: 683b ldr r3, [r7, #0] 8011ef0: 2b04 cmp r3, #4 8011ef2: d104 bne.n 8011efe 8011ef4: 687b ldr r3, [r7, #4] 8011ef6: 2202 movs r2, #2 8011ef8: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011efc: e00b b.n 8011f16 8011efe: 683b ldr r3, [r7, #0] 8011f00: 2b08 cmp r3, #8 8011f02: d104 bne.n 8011f0e 8011f04: 687b ldr r3, [r7, #4] 8011f06: 2202 movs r2, #2 8011f08: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011f0c: e003 b.n 8011f16 8011f0e: 687b ldr r3, [r7, #4] 8011f10: 2202 movs r2, #2 8011f12: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 8011f16: 687b ldr r3, [r7, #4] 8011f18: 681b ldr r3, [r3, #0] 8011f1a: 2201 movs r2, #1 8011f1c: 6839 ldr r1, [r7, #0] 8011f1e: 4618 mov r0, r3 8011f20: f000 fee8 bl 8012cf4 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8011f24: 687b ldr r3, [r7, #4] 8011f26: 681b ldr r3, [r3, #0] 8011f28: 4a21 ldr r2, [pc, #132] @ (8011fb0 ) 8011f2a: 4293 cmp r3, r2 8011f2c: d107 bne.n 8011f3e { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8011f2e: 687b ldr r3, [r7, #4] 8011f30: 681b ldr r3, [r3, #0] 8011f32: 6c5a ldr r2, [r3, #68] @ 0x44 8011f34: 687b ldr r3, [r7, #4] 8011f36: 681b ldr r3, [r3, #0] 8011f38: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8011f3c: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8011f3e: 687b ldr r3, [r7, #4] 8011f40: 681b ldr r3, [r3, #0] 8011f42: 4a1b ldr r2, [pc, #108] @ (8011fb0 ) 8011f44: 4293 cmp r3, r2 8011f46: d013 beq.n 8011f70 8011f48: 687b ldr r3, [r7, #4] 8011f4a: 681b ldr r3, [r3, #0] 8011f4c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8011f50: d00e beq.n 8011f70 8011f52: 687b ldr r3, [r7, #4] 8011f54: 681b ldr r3, [r3, #0] 8011f56: 4a17 ldr r2, [pc, #92] @ (8011fb4 ) 8011f58: 4293 cmp r3, r2 8011f5a: d009 beq.n 8011f70 8011f5c: 687b ldr r3, [r7, #4] 8011f5e: 681b ldr r3, [r3, #0] 8011f60: 4a15 ldr r2, [pc, #84] @ (8011fb8 ) 8011f62: 4293 cmp r3, r2 8011f64: d004 beq.n 8011f70 8011f66: 687b ldr r3, [r7, #4] 8011f68: 681b ldr r3, [r3, #0] 8011f6a: 4a14 ldr r2, [pc, #80] @ (8011fbc ) 8011f6c: 4293 cmp r3, r2 8011f6e: d111 bne.n 8011f94 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8011f70: 687b ldr r3, [r7, #4] 8011f72: 681b ldr r3, [r3, #0] 8011f74: 689b ldr r3, [r3, #8] 8011f76: f003 0307 and.w r3, r3, #7 8011f7a: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8011f7c: 68fb ldr r3, [r7, #12] 8011f7e: 2b06 cmp r3, #6 8011f80: d010 beq.n 8011fa4 { __HAL_TIM_ENABLE(htim); 8011f82: 687b ldr r3, [r7, #4] 8011f84: 681b ldr r3, [r3, #0] 8011f86: 681a ldr r2, [r3, #0] 8011f88: 687b ldr r3, [r7, #4] 8011f8a: 681b ldr r3, [r3, #0] 8011f8c: f042 0201 orr.w r2, r2, #1 8011f90: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8011f92: e007 b.n 8011fa4 } } else { __HAL_TIM_ENABLE(htim); 8011f94: 687b ldr r3, [r7, #4] 8011f96: 681b ldr r3, [r3, #0] 8011f98: 681a ldr r2, [r3, #0] 8011f9a: 687b ldr r3, [r7, #4] 8011f9c: 681b ldr r3, [r3, #0] 8011f9e: f042 0201 orr.w r2, r2, #1 8011fa2: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8011fa4: 2300 movs r3, #0 } 8011fa6: 4618 mov r0, r3 8011fa8: 3710 adds r7, #16 8011faa: 46bd mov sp, r7 8011fac: bd80 pop {r7, pc} 8011fae: bf00 nop 8011fb0: 40012c00 .word 0x40012c00 8011fb4: 40000400 .word 0x40000400 8011fb8: 40000800 .word 0x40000800 8011fbc: 40000c00 .word 0x40000c00 08011fc0 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 8011fc0: b580 push {r7, lr} 8011fc2: b082 sub sp, #8 8011fc4: af00 add r7, sp, #0 8011fc6: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8011fc8: 687b ldr r3, [r7, #4] 8011fca: 2b00 cmp r3, #0 8011fcc: d101 bne.n 8011fd2 { return HAL_ERROR; 8011fce: 2301 movs r3, #1 8011fd0: e041 b.n 8012056 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8011fd2: 687b ldr r3, [r7, #4] 8011fd4: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8011fd8: b2db uxtb r3, r3 8011fda: 2b00 cmp r3, #0 8011fdc: d106 bne.n 8011fec { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8011fde: 687b ldr r3, [r7, #4] 8011fe0: 2200 movs r2, #0 8011fe2: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 8011fe6: 6878 ldr r0, [r7, #4] 8011fe8: f000 f839 bl 801205e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8011fec: 687b ldr r3, [r7, #4] 8011fee: 2202 movs r2, #2 8011ff0: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8011ff4: 687b ldr r3, [r7, #4] 8011ff6: 681a ldr r2, [r3, #0] 8011ff8: 687b ldr r3, [r7, #4] 8011ffa: 3304 adds r3, #4 8011ffc: 4619 mov r1, r3 8011ffe: 4610 mov r0, r2 8012000: f000 fbe2 bl 80127c8 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8012004: 687b ldr r3, [r7, #4] 8012006: 2201 movs r2, #1 8012008: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 801200c: 687b ldr r3, [r7, #4] 801200e: 2201 movs r2, #1 8012010: f883 203e strb.w r2, [r3, #62] @ 0x3e 8012014: 687b ldr r3, [r7, #4] 8012016: 2201 movs r2, #1 8012018: f883 203f strb.w r2, [r3, #63] @ 0x3f 801201c: 687b ldr r3, [r7, #4] 801201e: 2201 movs r2, #1 8012020: f883 2040 strb.w r2, [r3, #64] @ 0x40 8012024: 687b ldr r3, [r7, #4] 8012026: 2201 movs r2, #1 8012028: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 801202c: 687b ldr r3, [r7, #4] 801202e: 2201 movs r2, #1 8012030: f883 2042 strb.w r2, [r3, #66] @ 0x42 8012034: 687b ldr r3, [r7, #4] 8012036: 2201 movs r2, #1 8012038: f883 2043 strb.w r2, [r3, #67] @ 0x43 801203c: 687b ldr r3, [r7, #4] 801203e: 2201 movs r2, #1 8012040: f883 2044 strb.w r2, [r3, #68] @ 0x44 8012044: 687b ldr r3, [r7, #4] 8012046: 2201 movs r2, #1 8012048: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 801204c: 687b ldr r3, [r7, #4] 801204e: 2201 movs r2, #1 8012050: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8012054: 2300 movs r3, #0 } 8012056: 4618 mov r0, r3 8012058: 3708 adds r7, #8 801205a: 46bd mov sp, r7 801205c: bd80 pop {r7, pc} 0801205e : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 801205e: b480 push {r7} 8012060: b083 sub sp, #12 8012062: af00 add r7, sp, #0 8012064: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 8012066: bf00 nop 8012068: 370c adds r7, #12 801206a: 46bd mov sp, r7 801206c: bc80 pop {r7} 801206e: 4770 bx lr 08012070 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8012070: b580 push {r7, lr} 8012072: b084 sub sp, #16 8012074: af00 add r7, sp, #0 8012076: 6078 str r0, [r7, #4] 8012078: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 801207a: 683b ldr r3, [r7, #0] 801207c: 2b00 cmp r3, #0 801207e: d109 bne.n 8012094 8012080: 687b ldr r3, [r7, #4] 8012082: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8012086: b2db uxtb r3, r3 8012088: 2b01 cmp r3, #1 801208a: bf14 ite ne 801208c: 2301 movne r3, #1 801208e: 2300 moveq r3, #0 8012090: b2db uxtb r3, r3 8012092: e022 b.n 80120da 8012094: 683b ldr r3, [r7, #0] 8012096: 2b04 cmp r3, #4 8012098: d109 bne.n 80120ae 801209a: 687b ldr r3, [r7, #4] 801209c: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 80120a0: b2db uxtb r3, r3 80120a2: 2b01 cmp r3, #1 80120a4: bf14 ite ne 80120a6: 2301 movne r3, #1 80120a8: 2300 moveq r3, #0 80120aa: b2db uxtb r3, r3 80120ac: e015 b.n 80120da 80120ae: 683b ldr r3, [r7, #0] 80120b0: 2b08 cmp r3, #8 80120b2: d109 bne.n 80120c8 80120b4: 687b ldr r3, [r7, #4] 80120b6: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 80120ba: b2db uxtb r3, r3 80120bc: 2b01 cmp r3, #1 80120be: bf14 ite ne 80120c0: 2301 movne r3, #1 80120c2: 2300 moveq r3, #0 80120c4: b2db uxtb r3, r3 80120c6: e008 b.n 80120da 80120c8: 687b ldr r3, [r7, #4] 80120ca: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80120ce: b2db uxtb r3, r3 80120d0: 2b01 cmp r3, #1 80120d2: bf14 ite ne 80120d4: 2301 movne r3, #1 80120d6: 2300 moveq r3, #0 80120d8: b2db uxtb r3, r3 80120da: 2b00 cmp r3, #0 80120dc: d001 beq.n 80120e2 { return HAL_ERROR; 80120de: 2301 movs r3, #1 80120e0: e063 b.n 80121aa } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 80120e2: 683b ldr r3, [r7, #0] 80120e4: 2b00 cmp r3, #0 80120e6: d104 bne.n 80120f2 80120e8: 687b ldr r3, [r7, #4] 80120ea: 2202 movs r2, #2 80120ec: f883 203e strb.w r2, [r3, #62] @ 0x3e 80120f0: e013 b.n 801211a 80120f2: 683b ldr r3, [r7, #0] 80120f4: 2b04 cmp r3, #4 80120f6: d104 bne.n 8012102 80120f8: 687b ldr r3, [r7, #4] 80120fa: 2202 movs r2, #2 80120fc: f883 203f strb.w r2, [r3, #63] @ 0x3f 8012100: e00b b.n 801211a 8012102: 683b ldr r3, [r7, #0] 8012104: 2b08 cmp r3, #8 8012106: d104 bne.n 8012112 8012108: 687b ldr r3, [r7, #4] 801210a: 2202 movs r2, #2 801210c: f883 2040 strb.w r2, [r3, #64] @ 0x40 8012110: e003 b.n 801211a 8012112: 687b ldr r3, [r7, #4] 8012114: 2202 movs r2, #2 8012116: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 801211a: 687b ldr r3, [r7, #4] 801211c: 681b ldr r3, [r3, #0] 801211e: 2201 movs r2, #1 8012120: 6839 ldr r1, [r7, #0] 8012122: 4618 mov r0, r3 8012124: f000 fde6 bl 8012cf4 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8012128: 687b ldr r3, [r7, #4] 801212a: 681b ldr r3, [r3, #0] 801212c: 4a21 ldr r2, [pc, #132] @ (80121b4 ) 801212e: 4293 cmp r3, r2 8012130: d107 bne.n 8012142 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8012132: 687b ldr r3, [r7, #4] 8012134: 681b ldr r3, [r3, #0] 8012136: 6c5a ldr r2, [r3, #68] @ 0x44 8012138: 687b ldr r3, [r7, #4] 801213a: 681b ldr r3, [r3, #0] 801213c: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8012140: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8012142: 687b ldr r3, [r7, #4] 8012144: 681b ldr r3, [r3, #0] 8012146: 4a1b ldr r2, [pc, #108] @ (80121b4 ) 8012148: 4293 cmp r3, r2 801214a: d013 beq.n 8012174 801214c: 687b ldr r3, [r7, #4] 801214e: 681b ldr r3, [r3, #0] 8012150: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8012154: d00e beq.n 8012174 8012156: 687b ldr r3, [r7, #4] 8012158: 681b ldr r3, [r3, #0] 801215a: 4a17 ldr r2, [pc, #92] @ (80121b8 ) 801215c: 4293 cmp r3, r2 801215e: d009 beq.n 8012174 8012160: 687b ldr r3, [r7, #4] 8012162: 681b ldr r3, [r3, #0] 8012164: 4a15 ldr r2, [pc, #84] @ (80121bc ) 8012166: 4293 cmp r3, r2 8012168: d004 beq.n 8012174 801216a: 687b ldr r3, [r7, #4] 801216c: 681b ldr r3, [r3, #0] 801216e: 4a14 ldr r2, [pc, #80] @ (80121c0 ) 8012170: 4293 cmp r3, r2 8012172: d111 bne.n 8012198 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8012174: 687b ldr r3, [r7, #4] 8012176: 681b ldr r3, [r3, #0] 8012178: 689b ldr r3, [r3, #8] 801217a: f003 0307 and.w r3, r3, #7 801217e: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8012180: 68fb ldr r3, [r7, #12] 8012182: 2b06 cmp r3, #6 8012184: d010 beq.n 80121a8 { __HAL_TIM_ENABLE(htim); 8012186: 687b ldr r3, [r7, #4] 8012188: 681b ldr r3, [r3, #0] 801218a: 681a ldr r2, [r3, #0] 801218c: 687b ldr r3, [r7, #4] 801218e: 681b ldr r3, [r3, #0] 8012190: f042 0201 orr.w r2, r2, #1 8012194: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8012196: e007 b.n 80121a8 } } else { __HAL_TIM_ENABLE(htim); 8012198: 687b ldr r3, [r7, #4] 801219a: 681b ldr r3, [r3, #0] 801219c: 681a ldr r2, [r3, #0] 801219e: 687b ldr r3, [r7, #4] 80121a0: 681b ldr r3, [r3, #0] 80121a2: f042 0201 orr.w r2, r2, #1 80121a6: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 80121a8: 2300 movs r3, #0 } 80121aa: 4618 mov r0, r3 80121ac: 3710 adds r7, #16 80121ae: 46bd mov sp, r7 80121b0: bd80 pop {r7, pc} 80121b2: bf00 nop 80121b4: 40012c00 .word 0x40012c00 80121b8: 40000400 .word 0x40000400 80121bc: 40000800 .word 0x40000800 80121c0: 40000c00 .word 0x40000c00 080121c4 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 80121c4: b580 push {r7, lr} 80121c6: b084 sub sp, #16 80121c8: af00 add r7, sp, #0 80121ca: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 80121cc: 687b ldr r3, [r7, #4] 80121ce: 681b ldr r3, [r3, #0] 80121d0: 68db ldr r3, [r3, #12] 80121d2: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 80121d4: 687b ldr r3, [r7, #4] 80121d6: 681b ldr r3, [r3, #0] 80121d8: 691b ldr r3, [r3, #16] 80121da: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 80121dc: 68bb ldr r3, [r7, #8] 80121de: f003 0302 and.w r3, r3, #2 80121e2: 2b00 cmp r3, #0 80121e4: d020 beq.n 8012228 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 80121e6: 68fb ldr r3, [r7, #12] 80121e8: f003 0302 and.w r3, r3, #2 80121ec: 2b00 cmp r3, #0 80121ee: d01b beq.n 8012228 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 80121f0: 687b ldr r3, [r7, #4] 80121f2: 681b ldr r3, [r3, #0] 80121f4: f06f 0202 mvn.w r2, #2 80121f8: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 80121fa: 687b ldr r3, [r7, #4] 80121fc: 2201 movs r2, #1 80121fe: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8012200: 687b ldr r3, [r7, #4] 8012202: 681b ldr r3, [r3, #0] 8012204: 699b ldr r3, [r3, #24] 8012206: f003 0303 and.w r3, r3, #3 801220a: 2b00 cmp r3, #0 801220c: d003 beq.n 8012216 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 801220e: 6878 ldr r0, [r7, #4] 8012210: f000 fabf bl 8012792 8012214: e005 b.n 8012222 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8012216: 6878 ldr r0, [r7, #4] 8012218: f000 fab2 bl 8012780 HAL_TIM_PWM_PulseFinishedCallback(htim); 801221c: 6878 ldr r0, [r7, #4] 801221e: f000 fac1 bl 80127a4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8012222: 687b ldr r3, [r7, #4] 8012224: 2200 movs r2, #0 8012226: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 8012228: 68bb ldr r3, [r7, #8] 801222a: f003 0304 and.w r3, r3, #4 801222e: 2b00 cmp r3, #0 8012230: d020 beq.n 8012274 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 8012232: 68fb ldr r3, [r7, #12] 8012234: f003 0304 and.w r3, r3, #4 8012238: 2b00 cmp r3, #0 801223a: d01b beq.n 8012274 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 801223c: 687b ldr r3, [r7, #4] 801223e: 681b ldr r3, [r3, #0] 8012240: f06f 0204 mvn.w r2, #4 8012244: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8012246: 687b ldr r3, [r7, #4] 8012248: 2202 movs r2, #2 801224a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 801224c: 687b ldr r3, [r7, #4] 801224e: 681b ldr r3, [r3, #0] 8012250: 699b ldr r3, [r3, #24] 8012252: f403 7340 and.w r3, r3, #768 @ 0x300 8012256: 2b00 cmp r3, #0 8012258: d003 beq.n 8012262 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 801225a: 6878 ldr r0, [r7, #4] 801225c: f000 fa99 bl 8012792 8012260: e005 b.n 801226e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8012262: 6878 ldr r0, [r7, #4] 8012264: f000 fa8c bl 8012780 HAL_TIM_PWM_PulseFinishedCallback(htim); 8012268: 6878 ldr r0, [r7, #4] 801226a: f000 fa9b bl 80127a4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 801226e: 687b ldr r3, [r7, #4] 8012270: 2200 movs r2, #0 8012272: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 8012274: 68bb ldr r3, [r7, #8] 8012276: f003 0308 and.w r3, r3, #8 801227a: 2b00 cmp r3, #0 801227c: d020 beq.n 80122c0 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 801227e: 68fb ldr r3, [r7, #12] 8012280: f003 0308 and.w r3, r3, #8 8012284: 2b00 cmp r3, #0 8012286: d01b beq.n 80122c0 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 8012288: 687b ldr r3, [r7, #4] 801228a: 681b ldr r3, [r3, #0] 801228c: f06f 0208 mvn.w r2, #8 8012290: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8012292: 687b ldr r3, [r7, #4] 8012294: 2204 movs r2, #4 8012296: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8012298: 687b ldr r3, [r7, #4] 801229a: 681b ldr r3, [r3, #0] 801229c: 69db ldr r3, [r3, #28] 801229e: f003 0303 and.w r3, r3, #3 80122a2: 2b00 cmp r3, #0 80122a4: d003 beq.n 80122ae { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80122a6: 6878 ldr r0, [r7, #4] 80122a8: f000 fa73 bl 8012792 80122ac: e005 b.n 80122ba { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80122ae: 6878 ldr r0, [r7, #4] 80122b0: f000 fa66 bl 8012780 HAL_TIM_PWM_PulseFinishedCallback(htim); 80122b4: 6878 ldr r0, [r7, #4] 80122b6: f000 fa75 bl 80127a4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80122ba: 687b ldr r3, [r7, #4] 80122bc: 2200 movs r2, #0 80122be: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 80122c0: 68bb ldr r3, [r7, #8] 80122c2: f003 0310 and.w r3, r3, #16 80122c6: 2b00 cmp r3, #0 80122c8: d020 beq.n 801230c { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 80122ca: 68fb ldr r3, [r7, #12] 80122cc: f003 0310 and.w r3, r3, #16 80122d0: 2b00 cmp r3, #0 80122d2: d01b beq.n 801230c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 80122d4: 687b ldr r3, [r7, #4] 80122d6: 681b ldr r3, [r3, #0] 80122d8: f06f 0210 mvn.w r2, #16 80122dc: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 80122de: 687b ldr r3, [r7, #4] 80122e0: 2208 movs r2, #8 80122e2: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 80122e4: 687b ldr r3, [r7, #4] 80122e6: 681b ldr r3, [r3, #0] 80122e8: 69db ldr r3, [r3, #28] 80122ea: f403 7340 and.w r3, r3, #768 @ 0x300 80122ee: 2b00 cmp r3, #0 80122f0: d003 beq.n 80122fa { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80122f2: 6878 ldr r0, [r7, #4] 80122f4: f000 fa4d bl 8012792 80122f8: e005 b.n 8012306 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80122fa: 6878 ldr r0, [r7, #4] 80122fc: f000 fa40 bl 8012780 HAL_TIM_PWM_PulseFinishedCallback(htim); 8012300: 6878 ldr r0, [r7, #4] 8012302: f000 fa4f bl 80127a4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8012306: 687b ldr r3, [r7, #4] 8012308: 2200 movs r2, #0 801230a: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 801230c: 68bb ldr r3, [r7, #8] 801230e: f003 0301 and.w r3, r3, #1 8012312: 2b00 cmp r3, #0 8012314: d00c beq.n 8012330 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 8012316: 68fb ldr r3, [r7, #12] 8012318: f003 0301 and.w r3, r3, #1 801231c: 2b00 cmp r3, #0 801231e: d007 beq.n 8012330 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 8012320: 687b ldr r3, [r7, #4] 8012322: 681b ldr r3, [r3, #0] 8012324: f06f 0201 mvn.w r2, #1 8012328: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 801232a: 6878 ldr r0, [r7, #4] 801232c: f000 fa1f bl 801276e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) 8012330: 68bb ldr r3, [r7, #8] 8012332: f003 0380 and.w r3, r3, #128 @ 0x80 8012336: 2b00 cmp r3, #0 8012338: d00c beq.n 8012354 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 801233a: 68fb ldr r3, [r7, #12] 801233c: f003 0380 and.w r3, r3, #128 @ 0x80 8012340: 2b00 cmp r3, #0 8012342: d007 beq.n 8012354 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); 8012344: 687b ldr r3, [r7, #4] 8012346: 681b ldr r3, [r3, #0] 8012348: f06f 0280 mvn.w r2, #128 @ 0x80 801234c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 801234e: 6878 ldr r0, [r7, #4] 8012350: f000 fd63 bl 8012e1a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 8012354: 68bb ldr r3, [r7, #8] 8012356: f003 0340 and.w r3, r3, #64 @ 0x40 801235a: 2b00 cmp r3, #0 801235c: d00c beq.n 8012378 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 801235e: 68fb ldr r3, [r7, #12] 8012360: f003 0340 and.w r3, r3, #64 @ 0x40 8012364: 2b00 cmp r3, #0 8012366: d007 beq.n 8012378 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 8012368: 687b ldr r3, [r7, #4] 801236a: 681b ldr r3, [r3, #0] 801236c: f06f 0240 mvn.w r2, #64 @ 0x40 8012370: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 8012372: 6878 ldr r0, [r7, #4] 8012374: f000 fa1f bl 80127b6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 8012378: 68bb ldr r3, [r7, #8] 801237a: f003 0320 and.w r3, r3, #32 801237e: 2b00 cmp r3, #0 8012380: d00c beq.n 801239c { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 8012382: 68fb ldr r3, [r7, #12] 8012384: f003 0320 and.w r3, r3, #32 8012388: 2b00 cmp r3, #0 801238a: d007 beq.n 801239c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 801238c: 687b ldr r3, [r7, #4] 801238e: 681b ldr r3, [r3, #0] 8012390: f06f 0220 mvn.w r2, #32 8012394: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8012396: 6878 ldr r0, [r7, #4] 8012398: f000 fd36 bl 8012e08 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 801239c: bf00 nop 801239e: 3710 adds r7, #16 80123a0: 46bd mov sp, r7 80123a2: bd80 pop {r7, pc} 080123a4 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 80123a4: b580 push {r7, lr} 80123a6: b086 sub sp, #24 80123a8: af00 add r7, sp, #0 80123aa: 60f8 str r0, [r7, #12] 80123ac: 60b9 str r1, [r7, #8] 80123ae: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80123b0: 2300 movs r3, #0 80123b2: 75fb strb r3, [r7, #23] assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); 80123b4: 68fb ldr r3, [r7, #12] 80123b6: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80123ba: 2b01 cmp r3, #1 80123bc: d101 bne.n 80123c2 80123be: 2302 movs r3, #2 80123c0: e048 b.n 8012454 80123c2: 68fb ldr r3, [r7, #12] 80123c4: 2201 movs r2, #1 80123c6: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 80123ca: 687b ldr r3, [r7, #4] 80123cc: 2b0c cmp r3, #12 80123ce: d839 bhi.n 8012444 80123d0: a201 add r2, pc, #4 @ (adr r2, 80123d8 ) 80123d2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80123d6: bf00 nop 80123d8: 0801240d .word 0x0801240d 80123dc: 08012445 .word 0x08012445 80123e0: 08012445 .word 0x08012445 80123e4: 08012445 .word 0x08012445 80123e8: 0801241b .word 0x0801241b 80123ec: 08012445 .word 0x08012445 80123f0: 08012445 .word 0x08012445 80123f4: 08012445 .word 0x08012445 80123f8: 08012429 .word 0x08012429 80123fc: 08012445 .word 0x08012445 8012400: 08012445 .word 0x08012445 8012404: 08012445 .word 0x08012445 8012408: 08012437 .word 0x08012437 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); 801240c: 68fb ldr r3, [r7, #12] 801240e: 681b ldr r3, [r3, #0] 8012410: 68b9 ldr r1, [r7, #8] 8012412: 4618 mov r0, r3 8012414: f000 fa50 bl 80128b8 break; 8012418: e017 b.n 801244a { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); 801241a: 68fb ldr r3, [r7, #12] 801241c: 681b ldr r3, [r3, #0] 801241e: 68b9 ldr r1, [r7, #8] 8012420: 4618 mov r0, r3 8012422: f000 faaf bl 8012984 break; 8012426: e010 b.n 801244a { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8012428: 68fb ldr r3, [r7, #12] 801242a: 681b ldr r3, [r3, #0] 801242c: 68b9 ldr r1, [r7, #8] 801242e: 4618 mov r0, r3 8012430: f000 fb12 bl 8012a58 break; 8012434: e009 b.n 801244a { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8012436: 68fb ldr r3, [r7, #12] 8012438: 681b ldr r3, [r3, #0] 801243a: 68b9 ldr r1, [r7, #8] 801243c: 4618 mov r0, r3 801243e: f000 fb75 bl 8012b2c break; 8012442: e002 b.n 801244a } default: status = HAL_ERROR; 8012444: 2301 movs r3, #1 8012446: 75fb strb r3, [r7, #23] break; 8012448: bf00 nop } __HAL_UNLOCK(htim); 801244a: 68fb ldr r3, [r7, #12] 801244c: 2200 movs r2, #0 801244e: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8012452: 7dfb ldrb r3, [r7, #23] } 8012454: 4618 mov r0, r3 8012456: 3718 adds r7, #24 8012458: 46bd mov sp, r7 801245a: bd80 pop {r7, pc} 0801245c : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 801245c: b580 push {r7, lr} 801245e: b086 sub sp, #24 8012460: af00 add r7, sp, #0 8012462: 60f8 str r0, [r7, #12] 8012464: 60b9 str r1, [r7, #8] 8012466: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8012468: 2300 movs r3, #0 801246a: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 801246c: 68fb ldr r3, [r7, #12] 801246e: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8012472: 2b01 cmp r3, #1 8012474: d101 bne.n 801247a 8012476: 2302 movs r3, #2 8012478: e0ae b.n 80125d8 801247a: 68fb ldr r3, [r7, #12] 801247c: 2201 movs r2, #1 801247e: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 8012482: 687b ldr r3, [r7, #4] 8012484: 2b0c cmp r3, #12 8012486: f200 809f bhi.w 80125c8 801248a: a201 add r2, pc, #4 @ (adr r2, 8012490 ) 801248c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012490: 080124c5 .word 0x080124c5 8012494: 080125c9 .word 0x080125c9 8012498: 080125c9 .word 0x080125c9 801249c: 080125c9 .word 0x080125c9 80124a0: 08012505 .word 0x08012505 80124a4: 080125c9 .word 0x080125c9 80124a8: 080125c9 .word 0x080125c9 80124ac: 080125c9 .word 0x080125c9 80124b0: 08012547 .word 0x08012547 80124b4: 080125c9 .word 0x080125c9 80124b8: 080125c9 .word 0x080125c9 80124bc: 080125c9 .word 0x080125c9 80124c0: 08012587 .word 0x08012587 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 80124c4: 68fb ldr r3, [r7, #12] 80124c6: 681b ldr r3, [r3, #0] 80124c8: 68b9 ldr r1, [r7, #8] 80124ca: 4618 mov r0, r3 80124cc: f000 f9f4 bl 80128b8 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 80124d0: 68fb ldr r3, [r7, #12] 80124d2: 681b ldr r3, [r3, #0] 80124d4: 699a ldr r2, [r3, #24] 80124d6: 68fb ldr r3, [r7, #12] 80124d8: 681b ldr r3, [r3, #0] 80124da: f042 0208 orr.w r2, r2, #8 80124de: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 80124e0: 68fb ldr r3, [r7, #12] 80124e2: 681b ldr r3, [r3, #0] 80124e4: 699a ldr r2, [r3, #24] 80124e6: 68fb ldr r3, [r7, #12] 80124e8: 681b ldr r3, [r3, #0] 80124ea: f022 0204 bic.w r2, r2, #4 80124ee: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 80124f0: 68fb ldr r3, [r7, #12] 80124f2: 681b ldr r3, [r3, #0] 80124f4: 6999 ldr r1, [r3, #24] 80124f6: 68bb ldr r3, [r7, #8] 80124f8: 691a ldr r2, [r3, #16] 80124fa: 68fb ldr r3, [r7, #12] 80124fc: 681b ldr r3, [r3, #0] 80124fe: 430a orrs r2, r1 8012500: 619a str r2, [r3, #24] break; 8012502: e064 b.n 80125ce { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8012504: 68fb ldr r3, [r7, #12] 8012506: 681b ldr r3, [r3, #0] 8012508: 68b9 ldr r1, [r7, #8] 801250a: 4618 mov r0, r3 801250c: f000 fa3a bl 8012984 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8012510: 68fb ldr r3, [r7, #12] 8012512: 681b ldr r3, [r3, #0] 8012514: 699a ldr r2, [r3, #24] 8012516: 68fb ldr r3, [r7, #12] 8012518: 681b ldr r3, [r3, #0] 801251a: f442 6200 orr.w r2, r2, #2048 @ 0x800 801251e: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8012520: 68fb ldr r3, [r7, #12] 8012522: 681b ldr r3, [r3, #0] 8012524: 699a ldr r2, [r3, #24] 8012526: 68fb ldr r3, [r7, #12] 8012528: 681b ldr r3, [r3, #0] 801252a: f422 6280 bic.w r2, r2, #1024 @ 0x400 801252e: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8012530: 68fb ldr r3, [r7, #12] 8012532: 681b ldr r3, [r3, #0] 8012534: 6999 ldr r1, [r3, #24] 8012536: 68bb ldr r3, [r7, #8] 8012538: 691b ldr r3, [r3, #16] 801253a: 021a lsls r2, r3, #8 801253c: 68fb ldr r3, [r7, #12] 801253e: 681b ldr r3, [r3, #0] 8012540: 430a orrs r2, r1 8012542: 619a str r2, [r3, #24] break; 8012544: e043 b.n 80125ce { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8012546: 68fb ldr r3, [r7, #12] 8012548: 681b ldr r3, [r3, #0] 801254a: 68b9 ldr r1, [r7, #8] 801254c: 4618 mov r0, r3 801254e: f000 fa83 bl 8012a58 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 8012552: 68fb ldr r3, [r7, #12] 8012554: 681b ldr r3, [r3, #0] 8012556: 69da ldr r2, [r3, #28] 8012558: 68fb ldr r3, [r7, #12] 801255a: 681b ldr r3, [r3, #0] 801255c: f042 0208 orr.w r2, r2, #8 8012560: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 8012562: 68fb ldr r3, [r7, #12] 8012564: 681b ldr r3, [r3, #0] 8012566: 69da ldr r2, [r3, #28] 8012568: 68fb ldr r3, [r7, #12] 801256a: 681b ldr r3, [r3, #0] 801256c: f022 0204 bic.w r2, r2, #4 8012570: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 8012572: 68fb ldr r3, [r7, #12] 8012574: 681b ldr r3, [r3, #0] 8012576: 69d9 ldr r1, [r3, #28] 8012578: 68bb ldr r3, [r7, #8] 801257a: 691a ldr r2, [r3, #16] 801257c: 68fb ldr r3, [r7, #12] 801257e: 681b ldr r3, [r3, #0] 8012580: 430a orrs r2, r1 8012582: 61da str r2, [r3, #28] break; 8012584: e023 b.n 80125ce { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8012586: 68fb ldr r3, [r7, #12] 8012588: 681b ldr r3, [r3, #0] 801258a: 68b9 ldr r1, [r7, #8] 801258c: 4618 mov r0, r3 801258e: f000 facd bl 8012b2c /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 8012592: 68fb ldr r3, [r7, #12] 8012594: 681b ldr r3, [r3, #0] 8012596: 69da ldr r2, [r3, #28] 8012598: 68fb ldr r3, [r7, #12] 801259a: 681b ldr r3, [r3, #0] 801259c: f442 6200 orr.w r2, r2, #2048 @ 0x800 80125a0: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 80125a2: 68fb ldr r3, [r7, #12] 80125a4: 681b ldr r3, [r3, #0] 80125a6: 69da ldr r2, [r3, #28] 80125a8: 68fb ldr r3, [r7, #12] 80125aa: 681b ldr r3, [r3, #0] 80125ac: f422 6280 bic.w r2, r2, #1024 @ 0x400 80125b0: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 80125b2: 68fb ldr r3, [r7, #12] 80125b4: 681b ldr r3, [r3, #0] 80125b6: 69d9 ldr r1, [r3, #28] 80125b8: 68bb ldr r3, [r7, #8] 80125ba: 691b ldr r3, [r3, #16] 80125bc: 021a lsls r2, r3, #8 80125be: 68fb ldr r3, [r7, #12] 80125c0: 681b ldr r3, [r3, #0] 80125c2: 430a orrs r2, r1 80125c4: 61da str r2, [r3, #28] break; 80125c6: e002 b.n 80125ce } default: status = HAL_ERROR; 80125c8: 2301 movs r3, #1 80125ca: 75fb strb r3, [r7, #23] break; 80125cc: bf00 nop } __HAL_UNLOCK(htim); 80125ce: 68fb ldr r3, [r7, #12] 80125d0: 2200 movs r2, #0 80125d2: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 80125d6: 7dfb ldrb r3, [r7, #23] } 80125d8: 4618 mov r0, r3 80125da: 3718 adds r7, #24 80125dc: 46bd mov sp, r7 80125de: bd80 pop {r7, pc} 080125e0 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 80125e0: b580 push {r7, lr} 80125e2: b084 sub sp, #16 80125e4: af00 add r7, sp, #0 80125e6: 6078 str r0, [r7, #4] 80125e8: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 80125ea: 2300 movs r3, #0 80125ec: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 80125ee: 687b ldr r3, [r7, #4] 80125f0: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80125f4: 2b01 cmp r3, #1 80125f6: d101 bne.n 80125fc 80125f8: 2302 movs r3, #2 80125fa: e0b4 b.n 8012766 80125fc: 687b ldr r3, [r7, #4] 80125fe: 2201 movs r2, #1 8012600: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 8012604: 687b ldr r3, [r7, #4] 8012606: 2202 movs r2, #2 8012608: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 801260c: 687b ldr r3, [r7, #4] 801260e: 681b ldr r3, [r3, #0] 8012610: 689b ldr r3, [r3, #8] 8012612: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 8012614: 68bb ldr r3, [r7, #8] 8012616: f023 0377 bic.w r3, r3, #119 @ 0x77 801261a: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 801261c: 68bb ldr r3, [r7, #8] 801261e: f423 437f bic.w r3, r3, #65280 @ 0xff00 8012622: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 8012624: 687b ldr r3, [r7, #4] 8012626: 681b ldr r3, [r3, #0] 8012628: 68ba ldr r2, [r7, #8] 801262a: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 801262c: 683b ldr r3, [r7, #0] 801262e: 681b ldr r3, [r3, #0] 8012630: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8012634: d03e beq.n 80126b4 8012636: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 801263a: f200 8087 bhi.w 801274c 801263e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012642: f000 8086 beq.w 8012752 8012646: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 801264a: d87f bhi.n 801274c 801264c: 2b70 cmp r3, #112 @ 0x70 801264e: d01a beq.n 8012686 8012650: 2b70 cmp r3, #112 @ 0x70 8012652: d87b bhi.n 801274c 8012654: 2b60 cmp r3, #96 @ 0x60 8012656: d050 beq.n 80126fa 8012658: 2b60 cmp r3, #96 @ 0x60 801265a: d877 bhi.n 801274c 801265c: 2b50 cmp r3, #80 @ 0x50 801265e: d03c beq.n 80126da 8012660: 2b50 cmp r3, #80 @ 0x50 8012662: d873 bhi.n 801274c 8012664: 2b40 cmp r3, #64 @ 0x40 8012666: d058 beq.n 801271a 8012668: 2b40 cmp r3, #64 @ 0x40 801266a: d86f bhi.n 801274c 801266c: 2b30 cmp r3, #48 @ 0x30 801266e: d064 beq.n 801273a 8012670: 2b30 cmp r3, #48 @ 0x30 8012672: d86b bhi.n 801274c 8012674: 2b20 cmp r3, #32 8012676: d060 beq.n 801273a 8012678: 2b20 cmp r3, #32 801267a: d867 bhi.n 801274c 801267c: 2b00 cmp r3, #0 801267e: d05c beq.n 801273a 8012680: 2b10 cmp r3, #16 8012682: d05a beq.n 801273a 8012684: e062 b.n 801274c assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8012686: 687b ldr r3, [r7, #4] 8012688: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 801268a: 683b ldr r3, [r7, #0] 801268c: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 801268e: 683b ldr r3, [r7, #0] 8012690: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8012692: 683b ldr r3, [r7, #0] 8012694: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8012696: f000 fb0e bl 8012cb6 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 801269a: 687b ldr r3, [r7, #4] 801269c: 681b ldr r3, [r3, #0] 801269e: 689b ldr r3, [r3, #8] 80126a0: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 80126a2: 68bb ldr r3, [r7, #8] 80126a4: f043 0377 orr.w r3, r3, #119 @ 0x77 80126a8: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80126aa: 687b ldr r3, [r7, #4] 80126ac: 681b ldr r3, [r3, #0] 80126ae: 68ba ldr r2, [r7, #8] 80126b0: 609a str r2, [r3, #8] break; 80126b2: e04f b.n 8012754 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80126b4: 687b ldr r3, [r7, #4] 80126b6: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 80126b8: 683b ldr r3, [r7, #0] 80126ba: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 80126bc: 683b ldr r3, [r7, #0] 80126be: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 80126c0: 683b ldr r3, [r7, #0] 80126c2: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 80126c4: f000 faf7 bl 8012cb6 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 80126c8: 687b ldr r3, [r7, #4] 80126ca: 681b ldr r3, [r3, #0] 80126cc: 689a ldr r2, [r3, #8] 80126ce: 687b ldr r3, [r7, #4] 80126d0: 681b ldr r3, [r3, #0] 80126d2: f442 4280 orr.w r2, r2, #16384 @ 0x4000 80126d6: 609a str r2, [r3, #8] break; 80126d8: e03c b.n 8012754 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 80126da: 687b ldr r3, [r7, #4] 80126dc: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80126de: 683b ldr r3, [r7, #0] 80126e0: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80126e2: 683b ldr r3, [r7, #0] 80126e4: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 80126e6: 461a mov r2, r3 80126e8: f000 fa6e bl 8012bc8 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 80126ec: 687b ldr r3, [r7, #4] 80126ee: 681b ldr r3, [r3, #0] 80126f0: 2150 movs r1, #80 @ 0x50 80126f2: 4618 mov r0, r3 80126f4: f000 fac5 bl 8012c82 break; 80126f8: e02c b.n 8012754 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 80126fa: 687b ldr r3, [r7, #4] 80126fc: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80126fe: 683b ldr r3, [r7, #0] 8012700: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8012702: 683b ldr r3, [r7, #0] 8012704: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 8012706: 461a mov r2, r3 8012708: f000 fa8c bl 8012c24 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 801270c: 687b ldr r3, [r7, #4] 801270e: 681b ldr r3, [r3, #0] 8012710: 2160 movs r1, #96 @ 0x60 8012712: 4618 mov r0, r3 8012714: f000 fab5 bl 8012c82 break; 8012718: e01c b.n 8012754 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 801271a: 687b ldr r3, [r7, #4] 801271c: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 801271e: 683b ldr r3, [r7, #0] 8012720: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8012722: 683b ldr r3, [r7, #0] 8012724: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 8012726: 461a mov r2, r3 8012728: f000 fa4e bl 8012bc8 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 801272c: 687b ldr r3, [r7, #4] 801272e: 681b ldr r3, [r3, #0] 8012730: 2140 movs r1, #64 @ 0x40 8012732: 4618 mov r0, r3 8012734: f000 faa5 bl 8012c82 break; 8012738: e00c b.n 8012754 case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 801273a: 687b ldr r3, [r7, #4] 801273c: 681a ldr r2, [r3, #0] 801273e: 683b ldr r3, [r7, #0] 8012740: 681b ldr r3, [r3, #0] 8012742: 4619 mov r1, r3 8012744: 4610 mov r0, r2 8012746: f000 fa9c bl 8012c82 break; 801274a: e003 b.n 8012754 } default: status = HAL_ERROR; 801274c: 2301 movs r3, #1 801274e: 73fb strb r3, [r7, #15] break; 8012750: e000 b.n 8012754 break; 8012752: bf00 nop } htim->State = HAL_TIM_STATE_READY; 8012754: 687b ldr r3, [r7, #4] 8012756: 2201 movs r2, #1 8012758: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 801275c: 687b ldr r3, [r7, #4] 801275e: 2200 movs r2, #0 8012760: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8012764: 7bfb ldrb r3, [r7, #15] } 8012766: 4618 mov r0, r3 8012768: 3710 adds r7, #16 801276a: 46bd mov sp, r7 801276c: bd80 pop {r7, pc} 0801276e : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 801276e: b480 push {r7} 8012770: b083 sub sp, #12 8012772: af00 add r7, sp, #0 8012774: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } 8012776: bf00 nop 8012778: 370c adds r7, #12 801277a: 46bd mov sp, r7 801277c: bc80 pop {r7} 801277e: 4770 bx lr 08012780 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 8012780: b480 push {r7} 8012782: b083 sub sp, #12 8012784: af00 add r7, sp, #0 8012786: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 8012788: bf00 nop 801278a: 370c adds r7, #12 801278c: 46bd mov sp, r7 801278e: bc80 pop {r7} 8012790: 4770 bx lr 08012792 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 8012792: b480 push {r7} 8012794: b083 sub sp, #12 8012796: af00 add r7, sp, #0 8012798: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 801279a: bf00 nop 801279c: 370c adds r7, #12 801279e: 46bd mov sp, r7 80127a0: bc80 pop {r7} 80127a2: 4770 bx lr 080127a4 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 80127a4: b480 push {r7} 80127a6: b083 sub sp, #12 80127a8: af00 add r7, sp, #0 80127aa: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 80127ac: bf00 nop 80127ae: 370c adds r7, #12 80127b0: 46bd mov sp, r7 80127b2: bc80 pop {r7} 80127b4: 4770 bx lr 080127b6 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 80127b6: b480 push {r7} 80127b8: b083 sub sp, #12 80127ba: af00 add r7, sp, #0 80127bc: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 80127be: bf00 nop 80127c0: 370c adds r7, #12 80127c2: 46bd mov sp, r7 80127c4: bc80 pop {r7} 80127c6: 4770 bx lr 080127c8 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 80127c8: b480 push {r7} 80127ca: b085 sub sp, #20 80127cc: af00 add r7, sp, #0 80127ce: 6078 str r0, [r7, #4] 80127d0: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 80127d2: 687b ldr r3, [r7, #4] 80127d4: 681b ldr r3, [r3, #0] 80127d6: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80127d8: 687b ldr r3, [r7, #4] 80127da: 4a33 ldr r2, [pc, #204] @ (80128a8 ) 80127dc: 4293 cmp r3, r2 80127de: d00f beq.n 8012800 80127e0: 687b ldr r3, [r7, #4] 80127e2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80127e6: d00b beq.n 8012800 80127e8: 687b ldr r3, [r7, #4] 80127ea: 4a30 ldr r2, [pc, #192] @ (80128ac ) 80127ec: 4293 cmp r3, r2 80127ee: d007 beq.n 8012800 80127f0: 687b ldr r3, [r7, #4] 80127f2: 4a2f ldr r2, [pc, #188] @ (80128b0 ) 80127f4: 4293 cmp r3, r2 80127f6: d003 beq.n 8012800 80127f8: 687b ldr r3, [r7, #4] 80127fa: 4a2e ldr r2, [pc, #184] @ (80128b4 ) 80127fc: 4293 cmp r3, r2 80127fe: d108 bne.n 8012812 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8012800: 68fb ldr r3, [r7, #12] 8012802: f023 0370 bic.w r3, r3, #112 @ 0x70 8012806: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8012808: 683b ldr r3, [r7, #0] 801280a: 685b ldr r3, [r3, #4] 801280c: 68fa ldr r2, [r7, #12] 801280e: 4313 orrs r3, r2 8012810: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8012812: 687b ldr r3, [r7, #4] 8012814: 4a24 ldr r2, [pc, #144] @ (80128a8 ) 8012816: 4293 cmp r3, r2 8012818: d00f beq.n 801283a 801281a: 687b ldr r3, [r7, #4] 801281c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8012820: d00b beq.n 801283a 8012822: 687b ldr r3, [r7, #4] 8012824: 4a21 ldr r2, [pc, #132] @ (80128ac ) 8012826: 4293 cmp r3, r2 8012828: d007 beq.n 801283a 801282a: 687b ldr r3, [r7, #4] 801282c: 4a20 ldr r2, [pc, #128] @ (80128b0 ) 801282e: 4293 cmp r3, r2 8012830: d003 beq.n 801283a 8012832: 687b ldr r3, [r7, #4] 8012834: 4a1f ldr r2, [pc, #124] @ (80128b4 ) 8012836: 4293 cmp r3, r2 8012838: d108 bne.n 801284c { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 801283a: 68fb ldr r3, [r7, #12] 801283c: f423 7340 bic.w r3, r3, #768 @ 0x300 8012840: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8012842: 683b ldr r3, [r7, #0] 8012844: 68db ldr r3, [r3, #12] 8012846: 68fa ldr r2, [r7, #12] 8012848: 4313 orrs r3, r2 801284a: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 801284c: 68fb ldr r3, [r7, #12] 801284e: f023 0280 bic.w r2, r3, #128 @ 0x80 8012852: 683b ldr r3, [r7, #0] 8012854: 695b ldr r3, [r3, #20] 8012856: 4313 orrs r3, r2 8012858: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 801285a: 687b ldr r3, [r7, #4] 801285c: 68fa ldr r2, [r7, #12] 801285e: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8012860: 683b ldr r3, [r7, #0] 8012862: 689a ldr r2, [r3, #8] 8012864: 687b ldr r3, [r7, #4] 8012866: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8012868: 683b ldr r3, [r7, #0] 801286a: 681a ldr r2, [r3, #0] 801286c: 687b ldr r3, [r7, #4] 801286e: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8012870: 687b ldr r3, [r7, #4] 8012872: 4a0d ldr r2, [pc, #52] @ (80128a8 ) 8012874: 4293 cmp r3, r2 8012876: d103 bne.n 8012880 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8012878: 683b ldr r3, [r7, #0] 801287a: 691a ldr r2, [r3, #16] 801287c: 687b ldr r3, [r7, #4] 801287e: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8012880: 687b ldr r3, [r7, #4] 8012882: 2201 movs r2, #1 8012884: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 8012886: 687b ldr r3, [r7, #4] 8012888: 691b ldr r3, [r3, #16] 801288a: f003 0301 and.w r3, r3, #1 801288e: 2b00 cmp r3, #0 8012890: d005 beq.n 801289e { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 8012892: 687b ldr r3, [r7, #4] 8012894: 691b ldr r3, [r3, #16] 8012896: f023 0201 bic.w r2, r3, #1 801289a: 687b ldr r3, [r7, #4] 801289c: 611a str r2, [r3, #16] } } 801289e: bf00 nop 80128a0: 3714 adds r7, #20 80128a2: 46bd mov sp, r7 80128a4: bc80 pop {r7} 80128a6: 4770 bx lr 80128a8: 40012c00 .word 0x40012c00 80128ac: 40000400 .word 0x40000400 80128b0: 40000800 .word 0x40000800 80128b4: 40000c00 .word 0x40000c00 080128b8 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80128b8: b480 push {r7} 80128ba: b087 sub sp, #28 80128bc: af00 add r7, sp, #0 80128be: 6078 str r0, [r7, #4] 80128c0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80128c2: 687b ldr r3, [r7, #4] 80128c4: 6a1b ldr r3, [r3, #32] 80128c6: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 80128c8: 687b ldr r3, [r7, #4] 80128ca: 6a1b ldr r3, [r3, #32] 80128cc: f023 0201 bic.w r2, r3, #1 80128d0: 687b ldr r3, [r7, #4] 80128d2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80128d4: 687b ldr r3, [r7, #4] 80128d6: 685b ldr r3, [r3, #4] 80128d8: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80128da: 687b ldr r3, [r7, #4] 80128dc: 699b ldr r3, [r3, #24] 80128de: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 80128e0: 68fb ldr r3, [r7, #12] 80128e2: f023 0370 bic.w r3, r3, #112 @ 0x70 80128e6: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 80128e8: 68fb ldr r3, [r7, #12] 80128ea: f023 0303 bic.w r3, r3, #3 80128ee: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80128f0: 683b ldr r3, [r7, #0] 80128f2: 681b ldr r3, [r3, #0] 80128f4: 68fa ldr r2, [r7, #12] 80128f6: 4313 orrs r3, r2 80128f8: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 80128fa: 697b ldr r3, [r7, #20] 80128fc: f023 0302 bic.w r3, r3, #2 8012900: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 8012902: 683b ldr r3, [r7, #0] 8012904: 689b ldr r3, [r3, #8] 8012906: 697a ldr r2, [r7, #20] 8012908: 4313 orrs r3, r2 801290a: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 801290c: 687b ldr r3, [r7, #4] 801290e: 4a1c ldr r2, [pc, #112] @ (8012980 ) 8012910: 4293 cmp r3, r2 8012912: d10c bne.n 801292e { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8012914: 697b ldr r3, [r7, #20] 8012916: f023 0308 bic.w r3, r3, #8 801291a: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 801291c: 683b ldr r3, [r7, #0] 801291e: 68db ldr r3, [r3, #12] 8012920: 697a ldr r2, [r7, #20] 8012922: 4313 orrs r3, r2 8012924: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 8012926: 697b ldr r3, [r7, #20] 8012928: f023 0304 bic.w r3, r3, #4 801292c: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 801292e: 687b ldr r3, [r7, #4] 8012930: 4a13 ldr r2, [pc, #76] @ (8012980 ) 8012932: 4293 cmp r3, r2 8012934: d111 bne.n 801295a /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 8012936: 693b ldr r3, [r7, #16] 8012938: f423 7380 bic.w r3, r3, #256 @ 0x100 801293c: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 801293e: 693b ldr r3, [r7, #16] 8012940: f423 7300 bic.w r3, r3, #512 @ 0x200 8012944: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8012946: 683b ldr r3, [r7, #0] 8012948: 695b ldr r3, [r3, #20] 801294a: 693a ldr r2, [r7, #16] 801294c: 4313 orrs r3, r2 801294e: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8012950: 683b ldr r3, [r7, #0] 8012952: 699b ldr r3, [r3, #24] 8012954: 693a ldr r2, [r7, #16] 8012956: 4313 orrs r3, r2 8012958: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 801295a: 687b ldr r3, [r7, #4] 801295c: 693a ldr r2, [r7, #16] 801295e: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8012960: 687b ldr r3, [r7, #4] 8012962: 68fa ldr r2, [r7, #12] 8012964: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 8012966: 683b ldr r3, [r7, #0] 8012968: 685a ldr r2, [r3, #4] 801296a: 687b ldr r3, [r7, #4] 801296c: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 801296e: 687b ldr r3, [r7, #4] 8012970: 697a ldr r2, [r7, #20] 8012972: 621a str r2, [r3, #32] } 8012974: bf00 nop 8012976: 371c adds r7, #28 8012978: 46bd mov sp, r7 801297a: bc80 pop {r7} 801297c: 4770 bx lr 801297e: bf00 nop 8012980: 40012c00 .word 0x40012c00 08012984 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012984: b480 push {r7} 8012986: b087 sub sp, #28 8012988: af00 add r7, sp, #0 801298a: 6078 str r0, [r7, #4] 801298c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 801298e: 687b ldr r3, [r7, #4] 8012990: 6a1b ldr r3, [r3, #32] 8012992: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8012994: 687b ldr r3, [r7, #4] 8012996: 6a1b ldr r3, [r3, #32] 8012998: f023 0210 bic.w r2, r3, #16 801299c: 687b ldr r3, [r7, #4] 801299e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80129a0: 687b ldr r3, [r7, #4] 80129a2: 685b ldr r3, [r3, #4] 80129a4: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80129a6: 687b ldr r3, [r7, #4] 80129a8: 699b ldr r3, [r3, #24] 80129aa: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 80129ac: 68fb ldr r3, [r7, #12] 80129ae: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80129b2: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 80129b4: 68fb ldr r3, [r7, #12] 80129b6: f423 7340 bic.w r3, r3, #768 @ 0x300 80129ba: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80129bc: 683b ldr r3, [r7, #0] 80129be: 681b ldr r3, [r3, #0] 80129c0: 021b lsls r3, r3, #8 80129c2: 68fa ldr r2, [r7, #12] 80129c4: 4313 orrs r3, r2 80129c6: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 80129c8: 697b ldr r3, [r7, #20] 80129ca: f023 0320 bic.w r3, r3, #32 80129ce: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 80129d0: 683b ldr r3, [r7, #0] 80129d2: 689b ldr r3, [r3, #8] 80129d4: 011b lsls r3, r3, #4 80129d6: 697a ldr r2, [r7, #20] 80129d8: 4313 orrs r3, r2 80129da: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 80129dc: 687b ldr r3, [r7, #4] 80129de: 4a1d ldr r2, [pc, #116] @ (8012a54 ) 80129e0: 4293 cmp r3, r2 80129e2: d10d bne.n 8012a00 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 80129e4: 697b ldr r3, [r7, #20] 80129e6: f023 0380 bic.w r3, r3, #128 @ 0x80 80129ea: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 80129ec: 683b ldr r3, [r7, #0] 80129ee: 68db ldr r3, [r3, #12] 80129f0: 011b lsls r3, r3, #4 80129f2: 697a ldr r2, [r7, #20] 80129f4: 4313 orrs r3, r2 80129f6: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 80129f8: 697b ldr r3, [r7, #20] 80129fa: f023 0340 bic.w r3, r3, #64 @ 0x40 80129fe: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8012a00: 687b ldr r3, [r7, #4] 8012a02: 4a14 ldr r2, [pc, #80] @ (8012a54 ) 8012a04: 4293 cmp r3, r2 8012a06: d113 bne.n 8012a30 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8012a08: 693b ldr r3, [r7, #16] 8012a0a: f423 6380 bic.w r3, r3, #1024 @ 0x400 8012a0e: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8012a10: 693b ldr r3, [r7, #16] 8012a12: f423 6300 bic.w r3, r3, #2048 @ 0x800 8012a16: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8012a18: 683b ldr r3, [r7, #0] 8012a1a: 695b ldr r3, [r3, #20] 8012a1c: 009b lsls r3, r3, #2 8012a1e: 693a ldr r2, [r7, #16] 8012a20: 4313 orrs r3, r2 8012a22: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8012a24: 683b ldr r3, [r7, #0] 8012a26: 699b ldr r3, [r3, #24] 8012a28: 009b lsls r3, r3, #2 8012a2a: 693a ldr r2, [r7, #16] 8012a2c: 4313 orrs r3, r2 8012a2e: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012a30: 687b ldr r3, [r7, #4] 8012a32: 693a ldr r2, [r7, #16] 8012a34: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8012a36: 687b ldr r3, [r7, #4] 8012a38: 68fa ldr r2, [r7, #12] 8012a3a: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8012a3c: 683b ldr r3, [r7, #0] 8012a3e: 685a ldr r2, [r3, #4] 8012a40: 687b ldr r3, [r7, #4] 8012a42: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012a44: 687b ldr r3, [r7, #4] 8012a46: 697a ldr r2, [r7, #20] 8012a48: 621a str r2, [r3, #32] } 8012a4a: bf00 nop 8012a4c: 371c adds r7, #28 8012a4e: 46bd mov sp, r7 8012a50: bc80 pop {r7} 8012a52: 4770 bx lr 8012a54: 40012c00 .word 0x40012c00 08012a58 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012a58: b480 push {r7} 8012a5a: b087 sub sp, #28 8012a5c: af00 add r7, sp, #0 8012a5e: 6078 str r0, [r7, #4] 8012a60: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8012a62: 687b ldr r3, [r7, #4] 8012a64: 6a1b ldr r3, [r3, #32] 8012a66: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8012a68: 687b ldr r3, [r7, #4] 8012a6a: 6a1b ldr r3, [r3, #32] 8012a6c: f423 7280 bic.w r2, r3, #256 @ 0x100 8012a70: 687b ldr r3, [r7, #4] 8012a72: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8012a74: 687b ldr r3, [r7, #4] 8012a76: 685b ldr r3, [r3, #4] 8012a78: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8012a7a: 687b ldr r3, [r7, #4] 8012a7c: 69db ldr r3, [r3, #28] 8012a7e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8012a80: 68fb ldr r3, [r7, #12] 8012a82: f023 0370 bic.w r3, r3, #112 @ 0x70 8012a86: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8012a88: 68fb ldr r3, [r7, #12] 8012a8a: f023 0303 bic.w r3, r3, #3 8012a8e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8012a90: 683b ldr r3, [r7, #0] 8012a92: 681b ldr r3, [r3, #0] 8012a94: 68fa ldr r2, [r7, #12] 8012a96: 4313 orrs r3, r2 8012a98: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8012a9a: 697b ldr r3, [r7, #20] 8012a9c: f423 7300 bic.w r3, r3, #512 @ 0x200 8012aa0: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 8012aa2: 683b ldr r3, [r7, #0] 8012aa4: 689b ldr r3, [r3, #8] 8012aa6: 021b lsls r3, r3, #8 8012aa8: 697a ldr r2, [r7, #20] 8012aaa: 4313 orrs r3, r2 8012aac: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8012aae: 687b ldr r3, [r7, #4] 8012ab0: 4a1d ldr r2, [pc, #116] @ (8012b28 ) 8012ab2: 4293 cmp r3, r2 8012ab4: d10d bne.n 8012ad2 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8012ab6: 697b ldr r3, [r7, #20] 8012ab8: f423 6300 bic.w r3, r3, #2048 @ 0x800 8012abc: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 8012abe: 683b ldr r3, [r7, #0] 8012ac0: 68db ldr r3, [r3, #12] 8012ac2: 021b lsls r3, r3, #8 8012ac4: 697a ldr r2, [r7, #20] 8012ac6: 4313 orrs r3, r2 8012ac8: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8012aca: 697b ldr r3, [r7, #20] 8012acc: f423 6380 bic.w r3, r3, #1024 @ 0x400 8012ad0: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8012ad2: 687b ldr r3, [r7, #4] 8012ad4: 4a14 ldr r2, [pc, #80] @ (8012b28 ) 8012ad6: 4293 cmp r3, r2 8012ad8: d113 bne.n 8012b02 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8012ada: 693b ldr r3, [r7, #16] 8012adc: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8012ae0: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8012ae2: 693b ldr r3, [r7, #16] 8012ae4: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8012ae8: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8012aea: 683b ldr r3, [r7, #0] 8012aec: 695b ldr r3, [r3, #20] 8012aee: 011b lsls r3, r3, #4 8012af0: 693a ldr r2, [r7, #16] 8012af2: 4313 orrs r3, r2 8012af4: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 8012af6: 683b ldr r3, [r7, #0] 8012af8: 699b ldr r3, [r3, #24] 8012afa: 011b lsls r3, r3, #4 8012afc: 693a ldr r2, [r7, #16] 8012afe: 4313 orrs r3, r2 8012b00: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012b02: 687b ldr r3, [r7, #4] 8012b04: 693a ldr r2, [r7, #16] 8012b06: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8012b08: 687b ldr r3, [r7, #4] 8012b0a: 68fa ldr r2, [r7, #12] 8012b0c: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8012b0e: 683b ldr r3, [r7, #0] 8012b10: 685a ldr r2, [r3, #4] 8012b12: 687b ldr r3, [r7, #4] 8012b14: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012b16: 687b ldr r3, [r7, #4] 8012b18: 697a ldr r2, [r7, #20] 8012b1a: 621a str r2, [r3, #32] } 8012b1c: bf00 nop 8012b1e: 371c adds r7, #28 8012b20: 46bd mov sp, r7 8012b22: bc80 pop {r7} 8012b24: 4770 bx lr 8012b26: bf00 nop 8012b28: 40012c00 .word 0x40012c00 08012b2c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012b2c: b480 push {r7} 8012b2e: b087 sub sp, #28 8012b30: af00 add r7, sp, #0 8012b32: 6078 str r0, [r7, #4] 8012b34: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8012b36: 687b ldr r3, [r7, #4] 8012b38: 6a1b ldr r3, [r3, #32] 8012b3a: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8012b3c: 687b ldr r3, [r7, #4] 8012b3e: 6a1b ldr r3, [r3, #32] 8012b40: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8012b44: 687b ldr r3, [r7, #4] 8012b46: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8012b48: 687b ldr r3, [r7, #4] 8012b4a: 685b ldr r3, [r3, #4] 8012b4c: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8012b4e: 687b ldr r3, [r7, #4] 8012b50: 69db ldr r3, [r3, #28] 8012b52: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8012b54: 68fb ldr r3, [r7, #12] 8012b56: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8012b5a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8012b5c: 68fb ldr r3, [r7, #12] 8012b5e: f423 7340 bic.w r3, r3, #768 @ 0x300 8012b62: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8012b64: 683b ldr r3, [r7, #0] 8012b66: 681b ldr r3, [r3, #0] 8012b68: 021b lsls r3, r3, #8 8012b6a: 68fa ldr r2, [r7, #12] 8012b6c: 4313 orrs r3, r2 8012b6e: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8012b70: 693b ldr r3, [r7, #16] 8012b72: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8012b76: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8012b78: 683b ldr r3, [r7, #0] 8012b7a: 689b ldr r3, [r3, #8] 8012b7c: 031b lsls r3, r3, #12 8012b7e: 693a ldr r2, [r7, #16] 8012b80: 4313 orrs r3, r2 8012b82: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8012b84: 687b ldr r3, [r7, #4] 8012b86: 4a0f ldr r2, [pc, #60] @ (8012bc4 ) 8012b88: 4293 cmp r3, r2 8012b8a: d109 bne.n 8012ba0 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8012b8c: 697b ldr r3, [r7, #20] 8012b8e: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8012b92: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8012b94: 683b ldr r3, [r7, #0] 8012b96: 695b ldr r3, [r3, #20] 8012b98: 019b lsls r3, r3, #6 8012b9a: 697a ldr r2, [r7, #20] 8012b9c: 4313 orrs r3, r2 8012b9e: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012ba0: 687b ldr r3, [r7, #4] 8012ba2: 697a ldr r2, [r7, #20] 8012ba4: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8012ba6: 687b ldr r3, [r7, #4] 8012ba8: 68fa ldr r2, [r7, #12] 8012baa: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8012bac: 683b ldr r3, [r7, #0] 8012bae: 685a ldr r2, [r3, #4] 8012bb0: 687b ldr r3, [r7, #4] 8012bb2: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012bb4: 687b ldr r3, [r7, #4] 8012bb6: 693a ldr r2, [r7, #16] 8012bb8: 621a str r2, [r3, #32] } 8012bba: bf00 nop 8012bbc: 371c adds r7, #28 8012bbe: 46bd mov sp, r7 8012bc0: bc80 pop {r7} 8012bc2: 4770 bx lr 8012bc4: 40012c00 .word 0x40012c00 08012bc8 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8012bc8: b480 push {r7} 8012bca: b087 sub sp, #28 8012bcc: af00 add r7, sp, #0 8012bce: 60f8 str r0, [r7, #12] 8012bd0: 60b9 str r1, [r7, #8] 8012bd2: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8012bd4: 68fb ldr r3, [r7, #12] 8012bd6: 6a1b ldr r3, [r3, #32] 8012bd8: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8012bda: 68fb ldr r3, [r7, #12] 8012bdc: 6a1b ldr r3, [r3, #32] 8012bde: f023 0201 bic.w r2, r3, #1 8012be2: 68fb ldr r3, [r7, #12] 8012be4: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8012be6: 68fb ldr r3, [r7, #12] 8012be8: 699b ldr r3, [r3, #24] 8012bea: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8012bec: 693b ldr r3, [r7, #16] 8012bee: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8012bf2: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8012bf4: 687b ldr r3, [r7, #4] 8012bf6: 011b lsls r3, r3, #4 8012bf8: 693a ldr r2, [r7, #16] 8012bfa: 4313 orrs r3, r2 8012bfc: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8012bfe: 697b ldr r3, [r7, #20] 8012c00: f023 030a bic.w r3, r3, #10 8012c04: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8012c06: 697a ldr r2, [r7, #20] 8012c08: 68bb ldr r3, [r7, #8] 8012c0a: 4313 orrs r3, r2 8012c0c: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8012c0e: 68fb ldr r3, [r7, #12] 8012c10: 693a ldr r2, [r7, #16] 8012c12: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8012c14: 68fb ldr r3, [r7, #12] 8012c16: 697a ldr r2, [r7, #20] 8012c18: 621a str r2, [r3, #32] } 8012c1a: bf00 nop 8012c1c: 371c adds r7, #28 8012c1e: 46bd mov sp, r7 8012c20: bc80 pop {r7} 8012c22: 4770 bx lr 08012c24 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8012c24: b480 push {r7} 8012c26: b087 sub sp, #28 8012c28: af00 add r7, sp, #0 8012c2a: 60f8 str r0, [r7, #12] 8012c2c: 60b9 str r1, [r7, #8] 8012c2e: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8012c30: 68fb ldr r3, [r7, #12] 8012c32: 6a1b ldr r3, [r3, #32] 8012c34: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8012c36: 68fb ldr r3, [r7, #12] 8012c38: 6a1b ldr r3, [r3, #32] 8012c3a: f023 0210 bic.w r2, r3, #16 8012c3e: 68fb ldr r3, [r7, #12] 8012c40: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8012c42: 68fb ldr r3, [r7, #12] 8012c44: 699b ldr r3, [r3, #24] 8012c46: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8012c48: 693b ldr r3, [r7, #16] 8012c4a: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8012c4e: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8012c50: 687b ldr r3, [r7, #4] 8012c52: 031b lsls r3, r3, #12 8012c54: 693a ldr r2, [r7, #16] 8012c56: 4313 orrs r3, r2 8012c58: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8012c5a: 697b ldr r3, [r7, #20] 8012c5c: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8012c60: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8012c62: 68bb ldr r3, [r7, #8] 8012c64: 011b lsls r3, r3, #4 8012c66: 697a ldr r2, [r7, #20] 8012c68: 4313 orrs r3, r2 8012c6a: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8012c6c: 68fb ldr r3, [r7, #12] 8012c6e: 693a ldr r2, [r7, #16] 8012c70: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8012c72: 68fb ldr r3, [r7, #12] 8012c74: 697a ldr r2, [r7, #20] 8012c76: 621a str r2, [r3, #32] } 8012c78: bf00 nop 8012c7a: 371c adds r7, #28 8012c7c: 46bd mov sp, r7 8012c7e: bc80 pop {r7} 8012c80: 4770 bx lr 08012c82 : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8012c82: b480 push {r7} 8012c84: b085 sub sp, #20 8012c86: af00 add r7, sp, #0 8012c88: 6078 str r0, [r7, #4] 8012c8a: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8012c8c: 687b ldr r3, [r7, #4] 8012c8e: 689b ldr r3, [r3, #8] 8012c90: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8012c92: 68fb ldr r3, [r7, #12] 8012c94: f023 0370 bic.w r3, r3, #112 @ 0x70 8012c98: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8012c9a: 683a ldr r2, [r7, #0] 8012c9c: 68fb ldr r3, [r7, #12] 8012c9e: 4313 orrs r3, r2 8012ca0: f043 0307 orr.w r3, r3, #7 8012ca4: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8012ca6: 687b ldr r3, [r7, #4] 8012ca8: 68fa ldr r2, [r7, #12] 8012caa: 609a str r2, [r3, #8] } 8012cac: bf00 nop 8012cae: 3714 adds r7, #20 8012cb0: 46bd mov sp, r7 8012cb2: bc80 pop {r7} 8012cb4: 4770 bx lr 08012cb6 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8012cb6: b480 push {r7} 8012cb8: b087 sub sp, #28 8012cba: af00 add r7, sp, #0 8012cbc: 60f8 str r0, [r7, #12] 8012cbe: 60b9 str r1, [r7, #8] 8012cc0: 607a str r2, [r7, #4] 8012cc2: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8012cc4: 68fb ldr r3, [r7, #12] 8012cc6: 689b ldr r3, [r3, #8] 8012cc8: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8012cca: 697b ldr r3, [r7, #20] 8012ccc: f423 437f bic.w r3, r3, #65280 @ 0xff00 8012cd0: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8012cd2: 683b ldr r3, [r7, #0] 8012cd4: 021a lsls r2, r3, #8 8012cd6: 687b ldr r3, [r7, #4] 8012cd8: 431a orrs r2, r3 8012cda: 68bb ldr r3, [r7, #8] 8012cdc: 4313 orrs r3, r2 8012cde: 697a ldr r2, [r7, #20] 8012ce0: 4313 orrs r3, r2 8012ce2: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8012ce4: 68fb ldr r3, [r7, #12] 8012ce6: 697a ldr r2, [r7, #20] 8012ce8: 609a str r2, [r3, #8] } 8012cea: bf00 nop 8012cec: 371c adds r7, #28 8012cee: 46bd mov sp, r7 8012cf0: bc80 pop {r7} 8012cf2: 4770 bx lr 08012cf4 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8012cf4: b480 push {r7} 8012cf6: b087 sub sp, #28 8012cf8: af00 add r7, sp, #0 8012cfa: 60f8 str r0, [r7, #12] 8012cfc: 60b9 str r1, [r7, #8] 8012cfe: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8012d00: 68bb ldr r3, [r7, #8] 8012d02: f003 031f and.w r3, r3, #31 8012d06: 2201 movs r2, #1 8012d08: fa02 f303 lsl.w r3, r2, r3 8012d0c: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 8012d0e: 68fb ldr r3, [r7, #12] 8012d10: 6a1a ldr r2, [r3, #32] 8012d12: 697b ldr r3, [r7, #20] 8012d14: 43db mvns r3, r3 8012d16: 401a ands r2, r3 8012d18: 68fb ldr r3, [r7, #12] 8012d1a: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8012d1c: 68fb ldr r3, [r7, #12] 8012d1e: 6a1a ldr r2, [r3, #32] 8012d20: 68bb ldr r3, [r7, #8] 8012d22: f003 031f and.w r3, r3, #31 8012d26: 6879 ldr r1, [r7, #4] 8012d28: fa01 f303 lsl.w r3, r1, r3 8012d2c: 431a orrs r2, r3 8012d2e: 68fb ldr r3, [r7, #12] 8012d30: 621a str r2, [r3, #32] } 8012d32: bf00 nop 8012d34: 371c adds r7, #28 8012d36: 46bd mov sp, r7 8012d38: bc80 pop {r7} 8012d3a: 4770 bx lr 08012d3c : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8012d3c: b480 push {r7} 8012d3e: b085 sub sp, #20 8012d40: af00 add r7, sp, #0 8012d42: 6078 str r0, [r7, #4] 8012d44: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8012d46: 687b ldr r3, [r7, #4] 8012d48: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8012d4c: 2b01 cmp r3, #1 8012d4e: d101 bne.n 8012d54 8012d50: 2302 movs r3, #2 8012d52: e04b b.n 8012dec 8012d54: 687b ldr r3, [r7, #4] 8012d56: 2201 movs r2, #1 8012d58: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8012d5c: 687b ldr r3, [r7, #4] 8012d5e: 2202 movs r2, #2 8012d60: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8012d64: 687b ldr r3, [r7, #4] 8012d66: 681b ldr r3, [r3, #0] 8012d68: 685b ldr r3, [r3, #4] 8012d6a: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8012d6c: 687b ldr r3, [r7, #4] 8012d6e: 681b ldr r3, [r3, #0] 8012d70: 689b ldr r3, [r3, #8] 8012d72: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8012d74: 68fb ldr r3, [r7, #12] 8012d76: f023 0370 bic.w r3, r3, #112 @ 0x70 8012d7a: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8012d7c: 683b ldr r3, [r7, #0] 8012d7e: 681b ldr r3, [r3, #0] 8012d80: 68fa ldr r2, [r7, #12] 8012d82: 4313 orrs r3, r2 8012d84: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8012d86: 687b ldr r3, [r7, #4] 8012d88: 681b ldr r3, [r3, #0] 8012d8a: 68fa ldr r2, [r7, #12] 8012d8c: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8012d8e: 687b ldr r3, [r7, #4] 8012d90: 681b ldr r3, [r3, #0] 8012d92: 4a19 ldr r2, [pc, #100] @ (8012df8 ) 8012d94: 4293 cmp r3, r2 8012d96: d013 beq.n 8012dc0 8012d98: 687b ldr r3, [r7, #4] 8012d9a: 681b ldr r3, [r3, #0] 8012d9c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8012da0: d00e beq.n 8012dc0 8012da2: 687b ldr r3, [r7, #4] 8012da4: 681b ldr r3, [r3, #0] 8012da6: 4a15 ldr r2, [pc, #84] @ (8012dfc ) 8012da8: 4293 cmp r3, r2 8012daa: d009 beq.n 8012dc0 8012dac: 687b ldr r3, [r7, #4] 8012dae: 681b ldr r3, [r3, #0] 8012db0: 4a13 ldr r2, [pc, #76] @ (8012e00 ) 8012db2: 4293 cmp r3, r2 8012db4: d004 beq.n 8012dc0 8012db6: 687b ldr r3, [r7, #4] 8012db8: 681b ldr r3, [r3, #0] 8012dba: 4a12 ldr r2, [pc, #72] @ (8012e04 ) 8012dbc: 4293 cmp r3, r2 8012dbe: d10c bne.n 8012dda { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8012dc0: 68bb ldr r3, [r7, #8] 8012dc2: f023 0380 bic.w r3, r3, #128 @ 0x80 8012dc6: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8012dc8: 683b ldr r3, [r7, #0] 8012dca: 685b ldr r3, [r3, #4] 8012dcc: 68ba ldr r2, [r7, #8] 8012dce: 4313 orrs r3, r2 8012dd0: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8012dd2: 687b ldr r3, [r7, #4] 8012dd4: 681b ldr r3, [r3, #0] 8012dd6: 68ba ldr r2, [r7, #8] 8012dd8: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8012dda: 687b ldr r3, [r7, #4] 8012ddc: 2201 movs r2, #1 8012dde: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8012de2: 687b ldr r3, [r7, #4] 8012de4: 2200 movs r2, #0 8012de6: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8012dea: 2300 movs r3, #0 } 8012dec: 4618 mov r0, r3 8012dee: 3714 adds r7, #20 8012df0: 46bd mov sp, r7 8012df2: bc80 pop {r7} 8012df4: 4770 bx lr 8012df6: bf00 nop 8012df8: 40012c00 .word 0x40012c00 8012dfc: 40000400 .word 0x40000400 8012e00: 40000800 .word 0x40000800 8012e04: 40000c00 .word 0x40000c00 08012e08 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8012e08: b480 push {r7} 8012e0a: b083 sub sp, #12 8012e0c: af00 add r7, sp, #0 8012e0e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8012e10: bf00 nop 8012e12: 370c adds r7, #12 8012e14: 46bd mov sp, r7 8012e16: bc80 pop {r7} 8012e18: 4770 bx lr 08012e1a : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8012e1a: b480 push {r7} 8012e1c: b083 sub sp, #12 8012e1e: af00 add r7, sp, #0 8012e20: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8012e22: bf00 nop 8012e24: 370c adds r7, #12 8012e26: 46bd mov sp, r7 8012e28: bc80 pop {r7} 8012e2a: 4770 bx lr 08012e2c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8012e2c: b580 push {r7, lr} 8012e2e: b082 sub sp, #8 8012e30: af00 add r7, sp, #0 8012e32: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8012e34: 687b ldr r3, [r7, #4] 8012e36: 2b00 cmp r3, #0 8012e38: d101 bne.n 8012e3e { return HAL_ERROR; 8012e3a: 2301 movs r3, #1 8012e3c: e042 b.n 8012ec4 assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 8012e3e: 687b ldr r3, [r7, #4] 8012e40: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8012e44: b2db uxtb r3, r3 8012e46: 2b00 cmp r3, #0 8012e48: d106 bne.n 8012e58 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8012e4a: 687b ldr r3, [r7, #4] 8012e4c: 2200 movs r2, #0 8012e4e: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8012e52: 6878 ldr r0, [r7, #4] 8012e54: f7fa ffc2 bl 800dddc #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8012e58: 687b ldr r3, [r7, #4] 8012e5a: 2224 movs r2, #36 @ 0x24 8012e5c: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8012e60: 687b ldr r3, [r7, #4] 8012e62: 681b ldr r3, [r3, #0] 8012e64: 68da ldr r2, [r3, #12] 8012e66: 687b ldr r3, [r7, #4] 8012e68: 681b ldr r3, [r3, #0] 8012e6a: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8012e6e: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8012e70: 6878 ldr r0, [r7, #4] 8012e72: f001 f903 bl 801407c /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8012e76: 687b ldr r3, [r7, #4] 8012e78: 681b ldr r3, [r3, #0] 8012e7a: 691a ldr r2, [r3, #16] 8012e7c: 687b ldr r3, [r7, #4] 8012e7e: 681b ldr r3, [r3, #0] 8012e80: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8012e84: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8012e86: 687b ldr r3, [r7, #4] 8012e88: 681b ldr r3, [r3, #0] 8012e8a: 695a ldr r2, [r3, #20] 8012e8c: 687b ldr r3, [r7, #4] 8012e8e: 681b ldr r3, [r3, #0] 8012e90: f022 022a bic.w r2, r2, #42 @ 0x2a 8012e94: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8012e96: 687b ldr r3, [r7, #4] 8012e98: 681b ldr r3, [r3, #0] 8012e9a: 68da ldr r2, [r3, #12] 8012e9c: 687b ldr r3, [r7, #4] 8012e9e: 681b ldr r3, [r3, #0] 8012ea0: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8012ea4: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012ea6: 687b ldr r3, [r7, #4] 8012ea8: 2200 movs r2, #0 8012eaa: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8012eac: 687b ldr r3, [r7, #4] 8012eae: 2220 movs r2, #32 8012eb0: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8012eb4: 687b ldr r3, [r7, #4] 8012eb6: 2220 movs r2, #32 8012eb8: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8012ebc: 687b ldr r3, [r7, #4] 8012ebe: 2200 movs r2, #0 8012ec0: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8012ec2: 2300 movs r3, #0 } 8012ec4: 4618 mov r0, r3 8012ec6: 3708 adds r7, #8 8012ec8: 46bd mov sp, r7 8012eca: bd80 pop {r7, pc} 08012ecc : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8012ecc: b580 push {r7, lr} 8012ece: b08c sub sp, #48 @ 0x30 8012ed0: af00 add r7, sp, #0 8012ed2: 60f8 str r0, [r7, #12] 8012ed4: 60b9 str r1, [r7, #8] 8012ed6: 4613 mov r3, r2 8012ed8: 80fb strh r3, [r7, #6] const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8012eda: 68fb ldr r3, [r7, #12] 8012edc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8012ee0: b2db uxtb r3, r3 8012ee2: 2b20 cmp r3, #32 8012ee4: d156 bne.n 8012f94 { if ((pData == NULL) || (Size == 0U)) 8012ee6: 68bb ldr r3, [r7, #8] 8012ee8: 2b00 cmp r3, #0 8012eea: d002 beq.n 8012ef2 8012eec: 88fb ldrh r3, [r7, #6] 8012eee: 2b00 cmp r3, #0 8012ef0: d101 bne.n 8012ef6 { return HAL_ERROR; 8012ef2: 2301 movs r3, #1 8012ef4: e04f b.n 8012f96 } huart->pTxBuffPtr = pData; 8012ef6: 68ba ldr r2, [r7, #8] 8012ef8: 68fb ldr r3, [r7, #12] 8012efa: 621a str r2, [r3, #32] huart->TxXferSize = Size; 8012efc: 68fb ldr r3, [r7, #12] 8012efe: 88fa ldrh r2, [r7, #6] 8012f00: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8012f02: 68fb ldr r3, [r7, #12] 8012f04: 88fa ldrh r2, [r7, #6] 8012f06: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 8012f08: 68fb ldr r3, [r7, #12] 8012f0a: 2200 movs r2, #0 8012f0c: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8012f0e: 68fb ldr r3, [r7, #12] 8012f10: 2221 movs r2, #33 @ 0x21 8012f12: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 8012f16: 68fb ldr r3, [r7, #12] 8012f18: 6b9b ldr r3, [r3, #56] @ 0x38 8012f1a: 4a21 ldr r2, [pc, #132] @ (8012fa0 ) 8012f1c: 629a str r2, [r3, #40] @ 0x28 /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 8012f1e: 68fb ldr r3, [r7, #12] 8012f20: 6b9b ldr r3, [r3, #56] @ 0x38 8012f22: 4a20 ldr r2, [pc, #128] @ (8012fa4 ) 8012f24: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 8012f26: 68fb ldr r3, [r7, #12] 8012f28: 6b9b ldr r3, [r3, #56] @ 0x38 8012f2a: 4a1f ldr r2, [pc, #124] @ (8012fa8 ) 8012f2c: 631a str r2, [r3, #48] @ 0x30 /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 8012f2e: 68fb ldr r3, [r7, #12] 8012f30: 6b9b ldr r3, [r3, #56] @ 0x38 8012f32: 2200 movs r2, #0 8012f34: 635a str r2, [r3, #52] @ 0x34 /* Enable the UART transmit DMA channel */ tmp = (const uint32_t *)&pData; 8012f36: f107 0308 add.w r3, r7, #8 8012f3a: 62fb str r3, [r7, #44] @ 0x2c HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size); 8012f3c: 68fb ldr r3, [r7, #12] 8012f3e: 6b98 ldr r0, [r3, #56] @ 0x38 8012f40: 6afb ldr r3, [r7, #44] @ 0x2c 8012f42: 6819 ldr r1, [r3, #0] 8012f44: 68fb ldr r3, [r7, #12] 8012f46: 681b ldr r3, [r3, #0] 8012f48: 3304 adds r3, #4 8012f4a: 461a mov r2, r3 8012f4c: 88fb ldrh r3, [r7, #6] 8012f4e: f7fc ffa5 bl 800fe9c /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); 8012f52: 68fb ldr r3, [r7, #12] 8012f54: 681b ldr r3, [r3, #0] 8012f56: f06f 0240 mvn.w r2, #64 @ 0x40 8012f5a: 601a str r2, [r3, #0] /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8012f5c: 68fb ldr r3, [r7, #12] 8012f5e: 681b ldr r3, [r3, #0] 8012f60: 3314 adds r3, #20 8012f62: 61bb str r3, [r7, #24] */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012f64: 69bb ldr r3, [r7, #24] 8012f66: e853 3f00 ldrex r3, [r3] 8012f6a: 617b str r3, [r7, #20] return(result); 8012f6c: 697b ldr r3, [r7, #20] 8012f6e: f043 0380 orr.w r3, r3, #128 @ 0x80 8012f72: 62bb str r3, [r7, #40] @ 0x28 8012f74: 68fb ldr r3, [r7, #12] 8012f76: 681b ldr r3, [r3, #0] 8012f78: 3314 adds r3, #20 8012f7a: 6aba ldr r2, [r7, #40] @ 0x28 8012f7c: 627a str r2, [r7, #36] @ 0x24 8012f7e: 623b str r3, [r7, #32] */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012f80: 6a39 ldr r1, [r7, #32] 8012f82: 6a7a ldr r2, [r7, #36] @ 0x24 8012f84: e841 2300 strex r3, r2, [r1] 8012f88: 61fb str r3, [r7, #28] return(result); 8012f8a: 69fb ldr r3, [r7, #28] 8012f8c: 2b00 cmp r3, #0 8012f8e: d1e5 bne.n 8012f5c return HAL_OK; 8012f90: 2300 movs r3, #0 8012f92: e000 b.n 8012f96 } else { return HAL_BUSY; 8012f94: 2302 movs r3, #2 } } 8012f96: 4618 mov r0, r3 8012f98: 3730 adds r7, #48 @ 0x30 8012f9a: 46bd mov sp, r7 8012f9c: bd80 pop {r7, pc} 8012f9e: bf00 nop 8012fa0: 080138a1 .word 0x080138a1 8012fa4: 0801393b .word 0x0801393b 8012fa8: 08013abf .word 0x08013abf 08012fac : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8012fac: b580 push {r7, lr} 8012fae: b08c sub sp, #48 @ 0x30 8012fb0: af00 add r7, sp, #0 8012fb2: 60f8 str r0, [r7, #12] 8012fb4: 60b9 str r1, [r7, #8] 8012fb6: 4613 mov r3, r2 8012fb8: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8012fba: 68fb ldr r3, [r7, #12] 8012fbc: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8012fc0: b2db uxtb r3, r3 8012fc2: 2b20 cmp r3, #32 8012fc4: d14a bne.n 801305c { if ((pData == NULL) || (Size == 0U)) 8012fc6: 68bb ldr r3, [r7, #8] 8012fc8: 2b00 cmp r3, #0 8012fca: d002 beq.n 8012fd2 8012fcc: 88fb ldrh r3, [r7, #6] 8012fce: 2b00 cmp r3, #0 8012fd0: d101 bne.n 8012fd6 { return HAL_ERROR; 8012fd2: 2301 movs r3, #1 8012fd4: e043 b.n 801305e } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8012fd6: 68fb ldr r3, [r7, #12] 8012fd8: 2201 movs r2, #1 8012fda: 631a str r2, [r3, #48] @ 0x30 huart->RxEventType = HAL_UART_RXEVENT_TC; 8012fdc: 68fb ldr r3, [r7, #12] 8012fde: 2200 movs r2, #0 8012fe0: 635a str r2, [r3, #52] @ 0x34 status = UART_Start_Receive_IT(huart, pData, Size); 8012fe2: 88fb ldrh r3, [r7, #6] 8012fe4: 461a mov r2, r3 8012fe6: 68b9 ldr r1, [r7, #8] 8012fe8: 68f8 ldr r0, [r7, #12] 8012fea: f000 fdb2 bl 8013b52 8012fee: 4603 mov r3, r0 8012ff0: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check Rx process has been successfully started */ if (status == HAL_OK) 8012ff4: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8012ff8: 2b00 cmp r3, #0 8012ffa: d12c bne.n 8013056 { if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012ffc: 68fb ldr r3, [r7, #12] 8012ffe: 6b1b ldr r3, [r3, #48] @ 0x30 8013000: 2b01 cmp r3, #1 8013002: d125 bne.n 8013050 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8013004: 2300 movs r3, #0 8013006: 613b str r3, [r7, #16] 8013008: 68fb ldr r3, [r7, #12] 801300a: 681b ldr r3, [r3, #0] 801300c: 681b ldr r3, [r3, #0] 801300e: 613b str r3, [r7, #16] 8013010: 68fb ldr r3, [r7, #12] 8013012: 681b ldr r3, [r3, #0] 8013014: 685b ldr r3, [r3, #4] 8013016: 613b str r3, [r7, #16] 8013018: 693b ldr r3, [r7, #16] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801301a: 68fb ldr r3, [r7, #12] 801301c: 681b ldr r3, [r3, #0] 801301e: 330c adds r3, #12 8013020: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013022: 69bb ldr r3, [r7, #24] 8013024: e853 3f00 ldrex r3, [r3] 8013028: 617b str r3, [r7, #20] return(result); 801302a: 697b ldr r3, [r7, #20] 801302c: f043 0310 orr.w r3, r3, #16 8013030: 62bb str r3, [r7, #40] @ 0x28 8013032: 68fb ldr r3, [r7, #12] 8013034: 681b ldr r3, [r3, #0] 8013036: 330c adds r3, #12 8013038: 6aba ldr r2, [r7, #40] @ 0x28 801303a: 627a str r2, [r7, #36] @ 0x24 801303c: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801303e: 6a39 ldr r1, [r7, #32] 8013040: 6a7a ldr r2, [r7, #36] @ 0x24 8013042: e841 2300 strex r3, r2, [r1] 8013046: 61fb str r3, [r7, #28] return(result); 8013048: 69fb ldr r3, [r7, #28] 801304a: 2b00 cmp r3, #0 801304c: d1e5 bne.n 801301a 801304e: e002 b.n 8013056 { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8013050: 2301 movs r3, #1 8013052: f887 302f strb.w r3, [r7, #47] @ 0x2f } } return status; 8013056: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 801305a: e000 b.n 801305e } else { return HAL_BUSY; 801305c: 2302 movs r3, #2 } } 801305e: 4618 mov r0, r3 8013060: 3730 adds r7, #48 @ 0x30 8013062: 46bd mov sp, r7 8013064: bd80 pop {r7, pc} 08013066 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8013066: b580 push {r7, lr} 8013068: b08c sub sp, #48 @ 0x30 801306a: af00 add r7, sp, #0 801306c: 60f8 str r0, [r7, #12] 801306e: 60b9 str r1, [r7, #8] 8013070: 4613 mov r3, r2 8013072: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8013074: 68fb ldr r3, [r7, #12] 8013076: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 801307a: b2db uxtb r3, r3 801307c: 2b20 cmp r3, #32 801307e: d146 bne.n 801310e { if ((pData == NULL) || (Size == 0U)) 8013080: 68bb ldr r3, [r7, #8] 8013082: 2b00 cmp r3, #0 8013084: d002 beq.n 801308c 8013086: 88fb ldrh r3, [r7, #6] 8013088: 2b00 cmp r3, #0 801308a: d101 bne.n 8013090 { return HAL_ERROR; 801308c: 2301 movs r3, #1 801308e: e03f b.n 8013110 } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8013090: 68fb ldr r3, [r7, #12] 8013092: 2201 movs r2, #1 8013094: 631a str r2, [r3, #48] @ 0x30 huart->RxEventType = HAL_UART_RXEVENT_TC; 8013096: 68fb ldr r3, [r7, #12] 8013098: 2200 movs r2, #0 801309a: 635a str r2, [r3, #52] @ 0x34 status = UART_Start_Receive_DMA(huart, pData, Size); 801309c: 88fb ldrh r3, [r7, #6] 801309e: 461a mov r2, r3 80130a0: 68b9 ldr r1, [r7, #8] 80130a2: 68f8 ldr r0, [r7, #12] 80130a4: f000 fd8e bl 8013bc4 80130a8: 4603 mov r3, r0 80130aa: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check Rx process has been successfully started */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80130ae: 68fb ldr r3, [r7, #12] 80130b0: 6b1b ldr r3, [r3, #48] @ 0x30 80130b2: 2b01 cmp r3, #1 80130b4: d125 bne.n 8013102 { __HAL_UART_CLEAR_IDLEFLAG(huart); 80130b6: 2300 movs r3, #0 80130b8: 613b str r3, [r7, #16] 80130ba: 68fb ldr r3, [r7, #12] 80130bc: 681b ldr r3, [r3, #0] 80130be: 681b ldr r3, [r3, #0] 80130c0: 613b str r3, [r7, #16] 80130c2: 68fb ldr r3, [r7, #12] 80130c4: 681b ldr r3, [r3, #0] 80130c6: 685b ldr r3, [r3, #4] 80130c8: 613b str r3, [r7, #16] 80130ca: 693b ldr r3, [r7, #16] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80130cc: 68fb ldr r3, [r7, #12] 80130ce: 681b ldr r3, [r3, #0] 80130d0: 330c adds r3, #12 80130d2: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80130d4: 69bb ldr r3, [r7, #24] 80130d6: e853 3f00 ldrex r3, [r3] 80130da: 617b str r3, [r7, #20] return(result); 80130dc: 697b ldr r3, [r7, #20] 80130de: f043 0310 orr.w r3, r3, #16 80130e2: 62bb str r3, [r7, #40] @ 0x28 80130e4: 68fb ldr r3, [r7, #12] 80130e6: 681b ldr r3, [r3, #0] 80130e8: 330c adds r3, #12 80130ea: 6aba ldr r2, [r7, #40] @ 0x28 80130ec: 627a str r2, [r7, #36] @ 0x24 80130ee: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80130f0: 6a39 ldr r1, [r7, #32] 80130f2: 6a7a ldr r2, [r7, #36] @ 0x24 80130f4: e841 2300 strex r3, r2, [r1] 80130f8: 61fb str r3, [r7, #28] return(result); 80130fa: 69fb ldr r3, [r7, #28] 80130fc: 2b00 cmp r3, #0 80130fe: d1e5 bne.n 80130cc 8013100: e002 b.n 8013108 { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8013102: 2301 movs r3, #1 8013104: f887 302f strb.w r3, [r7, #47] @ 0x2f } return status; 8013108: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 801310c: e000 b.n 8013110 } else { return HAL_BUSY; 801310e: 2302 movs r3, #2 } } 8013110: 4618 mov r0, r3 8013112: 3730 adds r7, #48 @ 0x30 8013114: 46bd mov sp, r7 8013116: bd80 pop {r7, pc} 08013118 : * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { 8013118: b580 push {r7, lr} 801311a: b08e sub sp, #56 @ 0x38 801311c: af00 add r7, sp, #0 801311e: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 8013120: 687b ldr r3, [r7, #4] 8013122: 681b ldr r3, [r3, #0] 8013124: 330c adds r3, #12 8013126: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013128: 6a3b ldr r3, [r7, #32] 801312a: e853 3f00 ldrex r3, [r3] 801312e: 61fb str r3, [r7, #28] return(result); 8013130: 69fb ldr r3, [r7, #28] 8013132: f023 03c0 bic.w r3, r3, #192 @ 0xc0 8013136: 637b str r3, [r7, #52] @ 0x34 8013138: 687b ldr r3, [r7, #4] 801313a: 681b ldr r3, [r3, #0] 801313c: 330c adds r3, #12 801313e: 6b7a ldr r2, [r7, #52] @ 0x34 8013140: 62fa str r2, [r7, #44] @ 0x2c 8013142: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013144: 6ab9 ldr r1, [r7, #40] @ 0x28 8013146: 6afa ldr r2, [r7, #44] @ 0x2c 8013148: e841 2300 strex r3, r2, [r1] 801314c: 627b str r3, [r7, #36] @ 0x24 return(result); 801314e: 6a7b ldr r3, [r7, #36] @ 0x24 8013150: 2b00 cmp r3, #0 8013152: d1e5 bne.n 8013120 /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) 8013154: 687b ldr r3, [r7, #4] 8013156: 681b ldr r3, [r3, #0] 8013158: 695b ldr r3, [r3, #20] 801315a: f003 0380 and.w r3, r3, #128 @ 0x80 801315e: 2b00 cmp r3, #0 8013160: d036 beq.n 80131d0 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8013162: 687b ldr r3, [r7, #4] 8013164: 681b ldr r3, [r3, #0] 8013166: 3314 adds r3, #20 8013168: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801316a: 68fb ldr r3, [r7, #12] 801316c: e853 3f00 ldrex r3, [r3] 8013170: 60bb str r3, [r7, #8] return(result); 8013172: 68bb ldr r3, [r7, #8] 8013174: f023 0380 bic.w r3, r3, #128 @ 0x80 8013178: 633b str r3, [r7, #48] @ 0x30 801317a: 687b ldr r3, [r7, #4] 801317c: 681b ldr r3, [r3, #0] 801317e: 3314 adds r3, #20 8013180: 6b3a ldr r2, [r7, #48] @ 0x30 8013182: 61ba str r2, [r7, #24] 8013184: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013186: 6979 ldr r1, [r7, #20] 8013188: 69ba ldr r2, [r7, #24] 801318a: e841 2300 strex r3, r2, [r1] 801318e: 613b str r3, [r7, #16] return(result); 8013190: 693b ldr r3, [r7, #16] 8013192: 2b00 cmp r3, #0 8013194: d1e5 bne.n 8013162 /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) 8013196: 687b ldr r3, [r7, #4] 8013198: 6b9b ldr r3, [r3, #56] @ 0x38 801319a: 2b00 cmp r3, #0 801319c: d018 beq.n 80131d0 { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = NULL; 801319e: 687b ldr r3, [r7, #4] 80131a0: 6b9b ldr r3, [r3, #56] @ 0x38 80131a2: 2200 movs r2, #0 80131a4: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) 80131a6: 687b ldr r3, [r7, #4] 80131a8: 6b9b ldr r3, [r3, #56] @ 0x38 80131aa: 4618 mov r0, r3 80131ac: f7fc fed6 bl 800ff5c 80131b0: 4603 mov r3, r0 80131b2: 2b00 cmp r3, #0 80131b4: d00c beq.n 80131d0 { if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) 80131b6: 687b ldr r3, [r7, #4] 80131b8: 6b9b ldr r3, [r3, #56] @ 0x38 80131ba: 4618 mov r0, r3 80131bc: f7fd fa4e bl 801065c 80131c0: 4603 mov r3, r0 80131c2: 2b20 cmp r3, #32 80131c4: d104 bne.n 80131d0 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 80131c6: 687b ldr r3, [r7, #4] 80131c8: 2210 movs r2, #16 80131ca: 645a str r2, [r3, #68] @ 0x44 return HAL_TIMEOUT; 80131cc: 2303 movs r3, #3 80131ce: e007 b.n 80131e0 } } } /* Reset Tx transfer counter */ huart->TxXferCount = 0x00U; 80131d0: 687b ldr r3, [r7, #4] 80131d2: 2200 movs r2, #0 80131d4: 84da strh r2, [r3, #38] @ 0x26 /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80131d6: 687b ldr r3, [r7, #4] 80131d8: 2220 movs r2, #32 80131da: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_OK; 80131de: 2300 movs r3, #0 } 80131e0: 4618 mov r0, r3 80131e2: 3738 adds r7, #56 @ 0x38 80131e4: 46bd mov sp, r7 80131e6: bd80 pop {r7, pc} 080131e8 : * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { 80131e8: b580 push {r7, lr} 80131ea: b09a sub sp, #104 @ 0x68 80131ec: af00 add r7, sp, #0 80131ee: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 80131f0: 687b ldr r3, [r7, #4] 80131f2: 681b ldr r3, [r3, #0] 80131f4: 330c adds r3, #12 80131f6: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80131f8: 6cbb ldr r3, [r7, #72] @ 0x48 80131fa: e853 3f00 ldrex r3, [r3] 80131fe: 647b str r3, [r7, #68] @ 0x44 return(result); 8013200: 6c7b ldr r3, [r7, #68] @ 0x44 8013202: f423 7390 bic.w r3, r3, #288 @ 0x120 8013206: 667b str r3, [r7, #100] @ 0x64 8013208: 687b ldr r3, [r7, #4] 801320a: 681b ldr r3, [r3, #0] 801320c: 330c adds r3, #12 801320e: 6e7a ldr r2, [r7, #100] @ 0x64 8013210: 657a str r2, [r7, #84] @ 0x54 8013212: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013214: 6d39 ldr r1, [r7, #80] @ 0x50 8013216: 6d7a ldr r2, [r7, #84] @ 0x54 8013218: e841 2300 strex r3, r2, [r1] 801321c: 64fb str r3, [r7, #76] @ 0x4c return(result); 801321e: 6cfb ldr r3, [r7, #76] @ 0x4c 8013220: 2b00 cmp r3, #0 8013222: d1e5 bne.n 80131f0 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013224: 687b ldr r3, [r7, #4] 8013226: 681b ldr r3, [r3, #0] 8013228: 3314 adds r3, #20 801322a: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801322c: 6b7b ldr r3, [r7, #52] @ 0x34 801322e: e853 3f00 ldrex r3, [r3] 8013232: 633b str r3, [r7, #48] @ 0x30 return(result); 8013234: 6b3b ldr r3, [r7, #48] @ 0x30 8013236: f023 0301 bic.w r3, r3, #1 801323a: 663b str r3, [r7, #96] @ 0x60 801323c: 687b ldr r3, [r7, #4] 801323e: 681b ldr r3, [r3, #0] 8013240: 3314 adds r3, #20 8013242: 6e3a ldr r2, [r7, #96] @ 0x60 8013244: 643a str r2, [r7, #64] @ 0x40 8013246: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013248: 6bf9 ldr r1, [r7, #60] @ 0x3c 801324a: 6c3a ldr r2, [r7, #64] @ 0x40 801324c: e841 2300 strex r3, r2, [r1] 8013250: 63bb str r3, [r7, #56] @ 0x38 return(result); 8013252: 6bbb ldr r3, [r7, #56] @ 0x38 8013254: 2b00 cmp r3, #0 8013256: d1e5 bne.n 8013224 /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013258: 687b ldr r3, [r7, #4] 801325a: 6b1b ldr r3, [r3, #48] @ 0x30 801325c: 2b01 cmp r3, #1 801325e: d119 bne.n 8013294 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); 8013260: 687b ldr r3, [r7, #4] 8013262: 681b ldr r3, [r3, #0] 8013264: 330c adds r3, #12 8013266: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013268: 6a3b ldr r3, [r7, #32] 801326a: e853 3f00 ldrex r3, [r3] 801326e: 61fb str r3, [r7, #28] return(result); 8013270: 69fb ldr r3, [r7, #28] 8013272: f023 0310 bic.w r3, r3, #16 8013276: 65fb str r3, [r7, #92] @ 0x5c 8013278: 687b ldr r3, [r7, #4] 801327a: 681b ldr r3, [r3, #0] 801327c: 330c adds r3, #12 801327e: 6dfa ldr r2, [r7, #92] @ 0x5c 8013280: 62fa str r2, [r7, #44] @ 0x2c 8013282: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013284: 6ab9 ldr r1, [r7, #40] @ 0x28 8013286: 6afa ldr r2, [r7, #44] @ 0x2c 8013288: e841 2300 strex r3, r2, [r1] 801328c: 627b str r3, [r7, #36] @ 0x24 return(result); 801328e: 6a7b ldr r3, [r7, #36] @ 0x24 8013290: 2b00 cmp r3, #0 8013292: d1e5 bne.n 8013260 } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013294: 687b ldr r3, [r7, #4] 8013296: 681b ldr r3, [r3, #0] 8013298: 695b ldr r3, [r3, #20] 801329a: f003 0340 and.w r3, r3, #64 @ 0x40 801329e: 2b00 cmp r3, #0 80132a0: d036 beq.n 8013310 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80132a2: 687b ldr r3, [r7, #4] 80132a4: 681b ldr r3, [r3, #0] 80132a6: 3314 adds r3, #20 80132a8: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80132aa: 68fb ldr r3, [r7, #12] 80132ac: e853 3f00 ldrex r3, [r3] 80132b0: 60bb str r3, [r7, #8] return(result); 80132b2: 68bb ldr r3, [r7, #8] 80132b4: f023 0340 bic.w r3, r3, #64 @ 0x40 80132b8: 65bb str r3, [r7, #88] @ 0x58 80132ba: 687b ldr r3, [r7, #4] 80132bc: 681b ldr r3, [r3, #0] 80132be: 3314 adds r3, #20 80132c0: 6dba ldr r2, [r7, #88] @ 0x58 80132c2: 61ba str r2, [r7, #24] 80132c4: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80132c6: 6979 ldr r1, [r7, #20] 80132c8: 69ba ldr r2, [r7, #24] 80132ca: e841 2300 strex r3, r2, [r1] 80132ce: 613b str r3, [r7, #16] return(result); 80132d0: 693b ldr r3, [r7, #16] 80132d2: 2b00 cmp r3, #0 80132d4: d1e5 bne.n 80132a2 /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) 80132d6: 687b ldr r3, [r7, #4] 80132d8: 6bdb ldr r3, [r3, #60] @ 0x3c 80132da: 2b00 cmp r3, #0 80132dc: d018 beq.n 8013310 { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = NULL; 80132de: 687b ldr r3, [r7, #4] 80132e0: 6bdb ldr r3, [r3, #60] @ 0x3c 80132e2: 2200 movs r2, #0 80132e4: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) 80132e6: 687b ldr r3, [r7, #4] 80132e8: 6bdb ldr r3, [r3, #60] @ 0x3c 80132ea: 4618 mov r0, r3 80132ec: f7fc fe36 bl 800ff5c 80132f0: 4603 mov r3, r0 80132f2: 2b00 cmp r3, #0 80132f4: d00c beq.n 8013310 { if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) 80132f6: 687b ldr r3, [r7, #4] 80132f8: 6bdb ldr r3, [r3, #60] @ 0x3c 80132fa: 4618 mov r0, r3 80132fc: f7fd f9ae bl 801065c 8013300: 4603 mov r3, r0 8013302: 2b20 cmp r3, #32 8013304: d104 bne.n 8013310 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 8013306: 687b ldr r3, [r7, #4] 8013308: 2210 movs r2, #16 801330a: 645a str r2, [r3, #68] @ 0x44 return HAL_TIMEOUT; 801330c: 2303 movs r3, #3 801330e: e00a b.n 8013326 } } } /* Reset Rx transfer counter */ huart->RxXferCount = 0x00U; 8013310: 687b ldr r3, [r7, #4] 8013312: 2200 movs r2, #0 8013314: 85da strh r2, [r3, #46] @ 0x2e /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013316: 687b ldr r3, [r7, #4] 8013318: 2220 movs r2, #32 801331a: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801331e: 687b ldr r3, [r7, #4] 8013320: 2200 movs r2, #0 8013322: 631a str r2, [r3, #48] @ 0x30 return HAL_OK; 8013324: 2300 movs r3, #0 } 8013326: 4618 mov r0, r3 8013328: 3768 adds r7, #104 @ 0x68 801332a: 46bd mov sp, r7 801332c: bd80 pop {r7, pc} ... 08013330 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8013330: b580 push {r7, lr} 8013332: b0ba sub sp, #232 @ 0xe8 8013334: af00 add r7, sp, #0 8013336: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 8013338: 687b ldr r3, [r7, #4] 801333a: 681b ldr r3, [r3, #0] 801333c: 681b ldr r3, [r3, #0] 801333e: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8013342: 687b ldr r3, [r7, #4] 8013344: 681b ldr r3, [r3, #0] 8013346: 68db ldr r3, [r3, #12] 8013348: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 801334c: 687b ldr r3, [r7, #4] 801334e: 681b ldr r3, [r3, #0] 8013350: 695b ldr r3, [r3, #20] 8013352: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 8013356: 2300 movs r3, #0 8013358: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 801335c: 2300 movs r3, #0 801335e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8013362: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013366: f003 030f and.w r3, r3, #15 801336a: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 801336e: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8013372: 2b00 cmp r3, #0 8013374: d10f bne.n 8013396 { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8013376: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801337a: f003 0320 and.w r3, r3, #32 801337e: 2b00 cmp r3, #0 8013380: d009 beq.n 8013396 8013382: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013386: f003 0320 and.w r3, r3, #32 801338a: 2b00 cmp r3, #0 801338c: d003 beq.n 8013396 { UART_Receive_IT(huart); 801338e: 6878 ldr r0, [r7, #4] 8013390: f000 fdb6 bl 8013f00 return; 8013394: e25b b.n 801384e } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 8013396: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 801339a: 2b00 cmp r3, #0 801339c: f000 80de beq.w 801355c 80133a0: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80133a4: f003 0301 and.w r3, r3, #1 80133a8: 2b00 cmp r3, #0 80133aa: d106 bne.n 80133ba || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 80133ac: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80133b0: f403 7390 and.w r3, r3, #288 @ 0x120 80133b4: 2b00 cmp r3, #0 80133b6: f000 80d1 beq.w 801355c { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 80133ba: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80133be: f003 0301 and.w r3, r3, #1 80133c2: 2b00 cmp r3, #0 80133c4: d00b beq.n 80133de 80133c6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80133ca: f403 7380 and.w r3, r3, #256 @ 0x100 80133ce: 2b00 cmp r3, #0 80133d0: d005 beq.n 80133de { huart->ErrorCode |= HAL_UART_ERROR_PE; 80133d2: 687b ldr r3, [r7, #4] 80133d4: 6c5b ldr r3, [r3, #68] @ 0x44 80133d6: f043 0201 orr.w r2, r3, #1 80133da: 687b ldr r3, [r7, #4] 80133dc: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 80133de: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80133e2: f003 0304 and.w r3, r3, #4 80133e6: 2b00 cmp r3, #0 80133e8: d00b beq.n 8013402 80133ea: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80133ee: f003 0301 and.w r3, r3, #1 80133f2: 2b00 cmp r3, #0 80133f4: d005 beq.n 8013402 { huart->ErrorCode |= HAL_UART_ERROR_NE; 80133f6: 687b ldr r3, [r7, #4] 80133f8: 6c5b ldr r3, [r3, #68] @ 0x44 80133fa: f043 0202 orr.w r2, r3, #2 80133fe: 687b ldr r3, [r7, #4] 8013400: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8013402: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013406: f003 0302 and.w r3, r3, #2 801340a: 2b00 cmp r3, #0 801340c: d00b beq.n 8013426 801340e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8013412: f003 0301 and.w r3, r3, #1 8013416: 2b00 cmp r3, #0 8013418: d005 beq.n 8013426 { huart->ErrorCode |= HAL_UART_ERROR_FE; 801341a: 687b ldr r3, [r7, #4] 801341c: 6c5b ldr r3, [r3, #68] @ 0x44 801341e: f043 0204 orr.w r2, r3, #4 8013422: 687b ldr r3, [r7, #4] 8013424: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 8013426: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801342a: f003 0308 and.w r3, r3, #8 801342e: 2b00 cmp r3, #0 8013430: d011 beq.n 8013456 8013432: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013436: f003 0320 and.w r3, r3, #32 801343a: 2b00 cmp r3, #0 801343c: d105 bne.n 801344a || ((cr3its & USART_CR3_EIE) != RESET))) 801343e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8013442: f003 0301 and.w r3, r3, #1 8013446: 2b00 cmp r3, #0 8013448: d005 beq.n 8013456 { huart->ErrorCode |= HAL_UART_ERROR_ORE; 801344a: 687b ldr r3, [r7, #4] 801344c: 6c5b ldr r3, [r3, #68] @ 0x44 801344e: f043 0208 orr.w r2, r3, #8 8013452: 687b ldr r3, [r7, #4] 8013454: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8013456: 687b ldr r3, [r7, #4] 8013458: 6c5b ldr r3, [r3, #68] @ 0x44 801345a: 2b00 cmp r3, #0 801345c: f000 81f2 beq.w 8013844 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8013460: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013464: f003 0320 and.w r3, r3, #32 8013468: 2b00 cmp r3, #0 801346a: d008 beq.n 801347e 801346c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013470: f003 0320 and.w r3, r3, #32 8013474: 2b00 cmp r3, #0 8013476: d002 beq.n 801347e { UART_Receive_IT(huart); 8013478: 6878 ldr r0, [r7, #4] 801347a: f000 fd41 bl 8013f00 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 801347e: 687b ldr r3, [r7, #4] 8013480: 681b ldr r3, [r3, #0] 8013482: 695b ldr r3, [r3, #20] 8013484: f003 0340 and.w r3, r3, #64 @ 0x40 8013488: 2b00 cmp r3, #0 801348a: bf14 ite ne 801348c: 2301 movne r3, #1 801348e: 2300 moveq r3, #0 8013490: b2db uxtb r3, r3 8013492: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8013496: 687b ldr r3, [r7, #4] 8013498: 6c5b ldr r3, [r3, #68] @ 0x44 801349a: f003 0308 and.w r3, r3, #8 801349e: 2b00 cmp r3, #0 80134a0: d103 bne.n 80134aa 80134a2: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 80134a6: 2b00 cmp r3, #0 80134a8: d04f beq.n 801354a { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 80134aa: 6878 ldr r0, [r7, #4] 80134ac: f000 fc4b bl 8013d46 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80134b0: 687b ldr r3, [r7, #4] 80134b2: 681b ldr r3, [r3, #0] 80134b4: 695b ldr r3, [r3, #20] 80134b6: f003 0340 and.w r3, r3, #64 @ 0x40 80134ba: 2b00 cmp r3, #0 80134bc: d041 beq.n 8013542 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80134be: 687b ldr r3, [r7, #4] 80134c0: 681b ldr r3, [r3, #0] 80134c2: 3314 adds r3, #20 80134c4: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80134c8: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 80134cc: e853 3f00 ldrex r3, [r3] 80134d0: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 80134d4: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 80134d8: f023 0340 bic.w r3, r3, #64 @ 0x40 80134dc: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 80134e0: 687b ldr r3, [r7, #4] 80134e2: 681b ldr r3, [r3, #0] 80134e4: 3314 adds r3, #20 80134e6: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 80134ea: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 80134ee: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80134f2: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 80134f6: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 80134fa: e841 2300 strex r3, r2, [r1] 80134fe: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8013502: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8013506: 2b00 cmp r3, #0 8013508: d1d9 bne.n 80134be /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 801350a: 687b ldr r3, [r7, #4] 801350c: 6bdb ldr r3, [r3, #60] @ 0x3c 801350e: 2b00 cmp r3, #0 8013510: d013 beq.n 801353a { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8013512: 687b ldr r3, [r7, #4] 8013514: 6bdb ldr r3, [r3, #60] @ 0x3c 8013516: 4a7e ldr r2, [pc, #504] @ (8013710 ) 8013518: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 801351a: 687b ldr r3, [r7, #4] 801351c: 6bdb ldr r3, [r3, #60] @ 0x3c 801351e: 4618 mov r0, r3 8013520: f7fc fd58 bl 800ffd4 8013524: 4603 mov r3, r0 8013526: 2b00 cmp r3, #0 8013528: d016 beq.n 8013558 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 801352a: 687b ldr r3, [r7, #4] 801352c: 6bdb ldr r3, [r3, #60] @ 0x3c 801352e: 6b5b ldr r3, [r3, #52] @ 0x34 8013530: 687a ldr r2, [r7, #4] 8013532: 6bd2 ldr r2, [r2, #60] @ 0x3c 8013534: 4610 mov r0, r2 8013536: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013538: e00e b.n 8013558 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 801353a: 6878 ldr r0, [r7, #4] 801353c: f7f8 fb92 bl 800bc64 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013540: e00a b.n 8013558 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013542: 6878 ldr r0, [r7, #4] 8013544: f7f8 fb8e bl 800bc64 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013548: e006 b.n 8013558 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 801354a: 6878 ldr r0, [r7, #4] 801354c: f7f8 fb8a bl 800bc64 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8013550: 687b ldr r3, [r7, #4] 8013552: 2200 movs r2, #0 8013554: 645a str r2, [r3, #68] @ 0x44 } } return; 8013556: e175 b.n 8013844 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013558: bf00 nop return; 801355a: e173 b.n 8013844 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 801355c: 687b ldr r3, [r7, #4] 801355e: 6b1b ldr r3, [r3, #48] @ 0x30 8013560: 2b01 cmp r3, #1 8013562: f040 814f bne.w 8013804 && ((isrflags & USART_SR_IDLE) != 0U) 8013566: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801356a: f003 0310 and.w r3, r3, #16 801356e: 2b00 cmp r3, #0 8013570: f000 8148 beq.w 8013804 && ((cr1its & USART_SR_IDLE) != 0U)) 8013574: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013578: f003 0310 and.w r3, r3, #16 801357c: 2b00 cmp r3, #0 801357e: f000 8141 beq.w 8013804 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8013582: 2300 movs r3, #0 8013584: 60bb str r3, [r7, #8] 8013586: 687b ldr r3, [r7, #4] 8013588: 681b ldr r3, [r3, #0] 801358a: 681b ldr r3, [r3, #0] 801358c: 60bb str r3, [r7, #8] 801358e: 687b ldr r3, [r7, #4] 8013590: 681b ldr r3, [r3, #0] 8013592: 685b ldr r3, [r3, #4] 8013594: 60bb str r3, [r7, #8] 8013596: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013598: 687b ldr r3, [r7, #4] 801359a: 681b ldr r3, [r3, #0] 801359c: 695b ldr r3, [r3, #20] 801359e: f003 0340 and.w r3, r3, #64 @ 0x40 80135a2: 2b00 cmp r3, #0 80135a4: f000 80b6 beq.w 8013714 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 80135a8: 687b ldr r3, [r7, #4] 80135aa: 6bdb ldr r3, [r3, #60] @ 0x3c 80135ac: 681b ldr r3, [r3, #0] 80135ae: 685b ldr r3, [r3, #4] 80135b0: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 80135b4: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 80135b8: 2b00 cmp r3, #0 80135ba: f000 8145 beq.w 8013848 && (nb_remaining_rx_data < huart->RxXferSize)) 80135be: 687b ldr r3, [r7, #4] 80135c0: 8d9b ldrh r3, [r3, #44] @ 0x2c 80135c2: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80135c6: 429a cmp r2, r3 80135c8: f080 813e bcs.w 8013848 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 80135cc: 687b ldr r3, [r7, #4] 80135ce: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80135d2: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 80135d4: 687b ldr r3, [r7, #4] 80135d6: 6bdb ldr r3, [r3, #60] @ 0x3c 80135d8: 699b ldr r3, [r3, #24] 80135da: 2b20 cmp r3, #32 80135dc: f000 8088 beq.w 80136f0 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80135e0: 687b ldr r3, [r7, #4] 80135e2: 681b ldr r3, [r3, #0] 80135e4: 330c adds r3, #12 80135e6: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80135ea: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 80135ee: e853 3f00 ldrex r3, [r3] 80135f2: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 80135f6: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 80135fa: f423 7380 bic.w r3, r3, #256 @ 0x100 80135fe: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8013602: 687b ldr r3, [r7, #4] 8013604: 681b ldr r3, [r3, #0] 8013606: 330c adds r3, #12 8013608: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 801360c: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8013610: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013614: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8013618: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 801361c: e841 2300 strex r3, r2, [r1] 8013620: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8013624: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8013628: 2b00 cmp r3, #0 801362a: d1d9 bne.n 80135e0 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 801362c: 687b ldr r3, [r7, #4] 801362e: 681b ldr r3, [r3, #0] 8013630: 3314 adds r3, #20 8013632: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013634: 6f7b ldr r3, [r7, #116] @ 0x74 8013636: e853 3f00 ldrex r3, [r3] 801363a: 673b str r3, [r7, #112] @ 0x70 return(result); 801363c: 6f3b ldr r3, [r7, #112] @ 0x70 801363e: f023 0301 bic.w r3, r3, #1 8013642: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8013646: 687b ldr r3, [r7, #4] 8013648: 681b ldr r3, [r3, #0] 801364a: 3314 adds r3, #20 801364c: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8013650: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8013654: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013656: 6ff9 ldr r1, [r7, #124] @ 0x7c 8013658: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 801365c: e841 2300 strex r3, r2, [r1] 8013660: 67bb str r3, [r7, #120] @ 0x78 return(result); 8013662: 6fbb ldr r3, [r7, #120] @ 0x78 8013664: 2b00 cmp r3, #0 8013666: d1e1 bne.n 801362c /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8013668: 687b ldr r3, [r7, #4] 801366a: 681b ldr r3, [r3, #0] 801366c: 3314 adds r3, #20 801366e: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013670: 6e3b ldr r3, [r7, #96] @ 0x60 8013672: e853 3f00 ldrex r3, [r3] 8013676: 65fb str r3, [r7, #92] @ 0x5c return(result); 8013678: 6dfb ldr r3, [r7, #92] @ 0x5c 801367a: f023 0340 bic.w r3, r3, #64 @ 0x40 801367e: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8013682: 687b ldr r3, [r7, #4] 8013684: 681b ldr r3, [r3, #0] 8013686: 3314 adds r3, #20 8013688: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 801368c: 66fa str r2, [r7, #108] @ 0x6c 801368e: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013690: 6eb9 ldr r1, [r7, #104] @ 0x68 8013692: 6efa ldr r2, [r7, #108] @ 0x6c 8013694: e841 2300 strex r3, r2, [r1] 8013698: 667b str r3, [r7, #100] @ 0x64 return(result); 801369a: 6e7b ldr r3, [r7, #100] @ 0x64 801369c: 2b00 cmp r3, #0 801369e: d1e3 bne.n 8013668 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80136a0: 687b ldr r3, [r7, #4] 80136a2: 2220 movs r2, #32 80136a4: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80136a8: 687b ldr r3, [r7, #4] 80136aa: 2200 movs r2, #0 80136ac: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80136ae: 687b ldr r3, [r7, #4] 80136b0: 681b ldr r3, [r3, #0] 80136b2: 330c adds r3, #12 80136b4: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80136b6: 6cfb ldr r3, [r7, #76] @ 0x4c 80136b8: e853 3f00 ldrex r3, [r3] 80136bc: 64bb str r3, [r7, #72] @ 0x48 return(result); 80136be: 6cbb ldr r3, [r7, #72] @ 0x48 80136c0: f023 0310 bic.w r3, r3, #16 80136c4: f8c7 30ac str.w r3, [r7, #172] @ 0xac 80136c8: 687b ldr r3, [r7, #4] 80136ca: 681b ldr r3, [r3, #0] 80136cc: 330c adds r3, #12 80136ce: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 80136d2: 65ba str r2, [r7, #88] @ 0x58 80136d4: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80136d6: 6d79 ldr r1, [r7, #84] @ 0x54 80136d8: 6dba ldr r2, [r7, #88] @ 0x58 80136da: e841 2300 strex r3, r2, [r1] 80136de: 653b str r3, [r7, #80] @ 0x50 return(result); 80136e0: 6d3b ldr r3, [r7, #80] @ 0x50 80136e2: 2b00 cmp r3, #0 80136e4: d1e3 bne.n 80136ae /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 80136e6: 687b ldr r3, [r7, #4] 80136e8: 6bdb ldr r3, [r3, #60] @ 0x3c 80136ea: 4618 mov r0, r3 80136ec: f7fc fc36 bl 800ff5c } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 80136f0: 687b ldr r3, [r7, #4] 80136f2: 2202 movs r2, #2 80136f4: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 80136f6: 687b ldr r3, [r7, #4] 80136f8: 8d9a ldrh r2, [r3, #44] @ 0x2c 80136fa: 687b ldr r3, [r7, #4] 80136fc: 8ddb ldrh r3, [r3, #46] @ 0x2e 80136fe: b29b uxth r3, r3 8013700: 1ad3 subs r3, r2, r3 8013702: b29b uxth r3, r3 8013704: 4619 mov r1, r3 8013706: 6878 ldr r0, [r7, #4] 8013708: f7f9 f9f6 bl 800caf8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 801370c: e09c b.n 8013848 801370e: bf00 nop 8013710: 08013e0b .word 0x08013e0b else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8013714: 687b ldr r3, [r7, #4] 8013716: 8d9a ldrh r2, [r3, #44] @ 0x2c 8013718: 687b ldr r3, [r7, #4] 801371a: 8ddb ldrh r3, [r3, #46] @ 0x2e 801371c: b29b uxth r3, r3 801371e: 1ad3 subs r3, r2, r3 8013720: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8013724: 687b ldr r3, [r7, #4] 8013726: 8ddb ldrh r3, [r3, #46] @ 0x2e 8013728: b29b uxth r3, r3 801372a: 2b00 cmp r3, #0 801372c: f000 808e beq.w 801384c && (nb_rx_data > 0U)) 8013730: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8013734: 2b00 cmp r3, #0 8013736: f000 8089 beq.w 801384c { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 801373a: 687b ldr r3, [r7, #4] 801373c: 681b ldr r3, [r3, #0] 801373e: 330c adds r3, #12 8013740: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013742: 6bbb ldr r3, [r7, #56] @ 0x38 8013744: e853 3f00 ldrex r3, [r3] 8013748: 637b str r3, [r7, #52] @ 0x34 return(result); 801374a: 6b7b ldr r3, [r7, #52] @ 0x34 801374c: f423 7390 bic.w r3, r3, #288 @ 0x120 8013750: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8013754: 687b ldr r3, [r7, #4] 8013756: 681b ldr r3, [r3, #0] 8013758: 330c adds r3, #12 801375a: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 801375e: 647a str r2, [r7, #68] @ 0x44 8013760: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013762: 6c39 ldr r1, [r7, #64] @ 0x40 8013764: 6c7a ldr r2, [r7, #68] @ 0x44 8013766: e841 2300 strex r3, r2, [r1] 801376a: 63fb str r3, [r7, #60] @ 0x3c return(result); 801376c: 6bfb ldr r3, [r7, #60] @ 0x3c 801376e: 2b00 cmp r3, #0 8013770: d1e3 bne.n 801373a /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013772: 687b ldr r3, [r7, #4] 8013774: 681b ldr r3, [r3, #0] 8013776: 3314 adds r3, #20 8013778: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801377a: 6a7b ldr r3, [r7, #36] @ 0x24 801377c: e853 3f00 ldrex r3, [r3] 8013780: 623b str r3, [r7, #32] return(result); 8013782: 6a3b ldr r3, [r7, #32] 8013784: f023 0301 bic.w r3, r3, #1 8013788: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 801378c: 687b ldr r3, [r7, #4] 801378e: 681b ldr r3, [r3, #0] 8013790: 3314 adds r3, #20 8013792: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8013796: 633a str r2, [r7, #48] @ 0x30 8013798: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801379a: 6af9 ldr r1, [r7, #44] @ 0x2c 801379c: 6b3a ldr r2, [r7, #48] @ 0x30 801379e: e841 2300 strex r3, r2, [r1] 80137a2: 62bb str r3, [r7, #40] @ 0x28 return(result); 80137a4: 6abb ldr r3, [r7, #40] @ 0x28 80137a6: 2b00 cmp r3, #0 80137a8: d1e3 bne.n 8013772 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80137aa: 687b ldr r3, [r7, #4] 80137ac: 2220 movs r2, #32 80137ae: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80137b2: 687b ldr r3, [r7, #4] 80137b4: 2200 movs r2, #0 80137b6: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80137b8: 687b ldr r3, [r7, #4] 80137ba: 681b ldr r3, [r3, #0] 80137bc: 330c adds r3, #12 80137be: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80137c0: 693b ldr r3, [r7, #16] 80137c2: e853 3f00 ldrex r3, [r3] 80137c6: 60fb str r3, [r7, #12] return(result); 80137c8: 68fb ldr r3, [r7, #12] 80137ca: f023 0310 bic.w r3, r3, #16 80137ce: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 80137d2: 687b ldr r3, [r7, #4] 80137d4: 681b ldr r3, [r3, #0] 80137d6: 330c adds r3, #12 80137d8: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 80137dc: 61fa str r2, [r7, #28] 80137de: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80137e0: 69b9 ldr r1, [r7, #24] 80137e2: 69fa ldr r2, [r7, #28] 80137e4: e841 2300 strex r3, r2, [r1] 80137e8: 617b str r3, [r7, #20] return(result); 80137ea: 697b ldr r3, [r7, #20] 80137ec: 2b00 cmp r3, #0 80137ee: d1e3 bne.n 80137b8 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 80137f0: 687b ldr r3, [r7, #4] 80137f2: 2202 movs r2, #2 80137f4: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 80137f6: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 80137fa: 4619 mov r1, r3 80137fc: 6878 ldr r0, [r7, #4] 80137fe: f7f9 f97b bl 800caf8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8013802: e023 b.n 801384c } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8013804: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013808: f003 0380 and.w r3, r3, #128 @ 0x80 801380c: 2b00 cmp r3, #0 801380e: d009 beq.n 8013824 8013810: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013814: f003 0380 and.w r3, r3, #128 @ 0x80 8013818: 2b00 cmp r3, #0 801381a: d003 beq.n 8013824 { UART_Transmit_IT(huart); 801381c: 6878 ldr r0, [r7, #4] 801381e: f000 fb08 bl 8013e32 return; 8013822: e014 b.n 801384e } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8013824: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013828: f003 0340 and.w r3, r3, #64 @ 0x40 801382c: 2b00 cmp r3, #0 801382e: d00e beq.n 801384e 8013830: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013834: f003 0340 and.w r3, r3, #64 @ 0x40 8013838: 2b00 cmp r3, #0 801383a: d008 beq.n 801384e { UART_EndTransmit_IT(huart); 801383c: 6878 ldr r0, [r7, #4] 801383e: f000 fb47 bl 8013ed0 return; 8013842: e004 b.n 801384e return; 8013844: bf00 nop 8013846: e002 b.n 801384e return; 8013848: bf00 nop 801384a: e000 b.n 801384e return; 801384c: bf00 nop } } 801384e: 37e8 adds r7, #232 @ 0xe8 8013850: 46bd mov sp, r7 8013852: bd80 pop {r7, pc} 08013854 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 8013854: b480 push {r7} 8013856: b083 sub sp, #12 8013858: af00 add r7, sp, #0 801385a: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } 801385c: bf00 nop 801385e: 370c adds r7, #12 8013860: 46bd mov sp, r7 8013862: bc80 pop {r7} 8013864: 4770 bx lr 08013866 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8013866: b480 push {r7} 8013868: b083 sub sp, #12 801386a: af00 add r7, sp, #0 801386c: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback could be implemented in the user file */ } 801386e: bf00 nop 8013870: 370c adds r7, #12 8013872: 46bd mov sp, r7 8013874: bc80 pop {r7} 8013876: 4770 bx lr 08013878 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { 8013878: b480 push {r7} 801387a: b083 sub sp, #12 801387c: af00 add r7, sp, #0 801387e: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback could be implemented in the user file */ } 8013880: bf00 nop 8013882: 370c adds r7, #12 8013884: 46bd mov sp, r7 8013886: bc80 pop {r7} 8013888: 4770 bx lr 0801388a : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. * @retval UART Error Code */ uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) { 801388a: b480 push {r7} 801388c: b083 sub sp, #12 801388e: af00 add r7, sp, #0 8013890: 6078 str r0, [r7, #4] return huart->ErrorCode; 8013892: 687b ldr r3, [r7, #4] 8013894: 6c5b ldr r3, [r3, #68] @ 0x44 } 8013896: 4618 mov r0, r3 8013898: 370c adds r7, #12 801389a: 46bd mov sp, r7 801389c: bc80 pop {r7} 801389e: 4770 bx lr 080138a0 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 80138a0: b580 push {r7, lr} 80138a2: b090 sub sp, #64 @ 0x40 80138a4: af00 add r7, sp, #0 80138a6: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80138a8: 687b ldr r3, [r7, #4] 80138aa: 6a5b ldr r3, [r3, #36] @ 0x24 80138ac: 63fb str r3, [r7, #60] @ 0x3c /* DMA Normal mode*/ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 80138ae: 687b ldr r3, [r7, #4] 80138b0: 681b ldr r3, [r3, #0] 80138b2: 681b ldr r3, [r3, #0] 80138b4: f003 0320 and.w r3, r3, #32 80138b8: 2b00 cmp r3, #0 80138ba: d137 bne.n 801392c { huart->TxXferCount = 0x00U; 80138bc: 6bfb ldr r3, [r7, #60] @ 0x3c 80138be: 2200 movs r2, #0 80138c0: 84da strh r2, [r3, #38] @ 0x26 /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 80138c2: 6bfb ldr r3, [r7, #60] @ 0x3c 80138c4: 681b ldr r3, [r3, #0] 80138c6: 3314 adds r3, #20 80138c8: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80138ca: 6a7b ldr r3, [r7, #36] @ 0x24 80138cc: e853 3f00 ldrex r3, [r3] 80138d0: 623b str r3, [r7, #32] return(result); 80138d2: 6a3b ldr r3, [r7, #32] 80138d4: f023 0380 bic.w r3, r3, #128 @ 0x80 80138d8: 63bb str r3, [r7, #56] @ 0x38 80138da: 6bfb ldr r3, [r7, #60] @ 0x3c 80138dc: 681b ldr r3, [r3, #0] 80138de: 3314 adds r3, #20 80138e0: 6bba ldr r2, [r7, #56] @ 0x38 80138e2: 633a str r2, [r7, #48] @ 0x30 80138e4: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80138e6: 6af9 ldr r1, [r7, #44] @ 0x2c 80138e8: 6b3a ldr r2, [r7, #48] @ 0x30 80138ea: e841 2300 strex r3, r2, [r1] 80138ee: 62bb str r3, [r7, #40] @ 0x28 return(result); 80138f0: 6abb ldr r3, [r7, #40] @ 0x28 80138f2: 2b00 cmp r3, #0 80138f4: d1e5 bne.n 80138c2 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80138f6: 6bfb ldr r3, [r7, #60] @ 0x3c 80138f8: 681b ldr r3, [r3, #0] 80138fa: 330c adds r3, #12 80138fc: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80138fe: 693b ldr r3, [r7, #16] 8013900: e853 3f00 ldrex r3, [r3] 8013904: 60fb str r3, [r7, #12] return(result); 8013906: 68fb ldr r3, [r7, #12] 8013908: f043 0340 orr.w r3, r3, #64 @ 0x40 801390c: 637b str r3, [r7, #52] @ 0x34 801390e: 6bfb ldr r3, [r7, #60] @ 0x3c 8013910: 681b ldr r3, [r3, #0] 8013912: 330c adds r3, #12 8013914: 6b7a ldr r2, [r7, #52] @ 0x34 8013916: 61fa str r2, [r7, #28] 8013918: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801391a: 69b9 ldr r1, [r7, #24] 801391c: 69fa ldr r2, [r7, #28] 801391e: e841 2300 strex r3, r2, [r1] 8013922: 617b str r3, [r7, #20] return(result); 8013924: 697b ldr r3, [r7, #20] 8013926: 2b00 cmp r3, #0 8013928: d1e5 bne.n 80138f6 #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 801392a: e002 b.n 8013932 HAL_UART_TxCpltCallback(huart); 801392c: 6bf8 ldr r0, [r7, #60] @ 0x3c 801392e: f7f9 f95d bl 800cbec } 8013932: bf00 nop 8013934: 3740 adds r7, #64 @ 0x40 8013936: 46bd mov sp, r7 8013938: bd80 pop {r7, pc} 0801393a : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 801393a: b580 push {r7, lr} 801393c: b084 sub sp, #16 801393e: af00 add r7, sp, #0 8013940: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013942: 687b ldr r3, [r7, #4] 8013944: 6a5b ldr r3, [r3, #36] @ 0x24 8013946: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 8013948: 68f8 ldr r0, [r7, #12] 801394a: f7ff ff83 bl 8013854 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 801394e: bf00 nop 8013950: 3710 adds r7, #16 8013952: 46bd mov sp, r7 8013954: bd80 pop {r7, pc} 08013956 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 8013956: b580 push {r7, lr} 8013958: b09c sub sp, #112 @ 0x70 801395a: af00 add r7, sp, #0 801395c: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 801395e: 687b ldr r3, [r7, #4] 8013960: 6a5b ldr r3, [r3, #36] @ 0x24 8013962: 66fb str r3, [r7, #108] @ 0x6c /* DMA Normal mode*/ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8013964: 687b ldr r3, [r7, #4] 8013966: 681b ldr r3, [r3, #0] 8013968: 681b ldr r3, [r3, #0] 801396a: f003 0320 and.w r3, r3, #32 801396e: 2b00 cmp r3, #0 8013970: d172 bne.n 8013a58 { huart->RxXferCount = 0U; 8013972: 6efb ldr r3, [r7, #108] @ 0x6c 8013974: 2200 movs r2, #0 8013976: 85da strh r2, [r3, #46] @ 0x2e /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8013978: 6efb ldr r3, [r7, #108] @ 0x6c 801397a: 681b ldr r3, [r3, #0] 801397c: 330c adds r3, #12 801397e: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013980: 6cfb ldr r3, [r7, #76] @ 0x4c 8013982: e853 3f00 ldrex r3, [r3] 8013986: 64bb str r3, [r7, #72] @ 0x48 return(result); 8013988: 6cbb ldr r3, [r7, #72] @ 0x48 801398a: f423 7380 bic.w r3, r3, #256 @ 0x100 801398e: 66bb str r3, [r7, #104] @ 0x68 8013990: 6efb ldr r3, [r7, #108] @ 0x6c 8013992: 681b ldr r3, [r3, #0] 8013994: 330c adds r3, #12 8013996: 6eba ldr r2, [r7, #104] @ 0x68 8013998: 65ba str r2, [r7, #88] @ 0x58 801399a: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801399c: 6d79 ldr r1, [r7, #84] @ 0x54 801399e: 6dba ldr r2, [r7, #88] @ 0x58 80139a0: e841 2300 strex r3, r2, [r1] 80139a4: 653b str r3, [r7, #80] @ 0x50 return(result); 80139a6: 6d3b ldr r3, [r7, #80] @ 0x50 80139a8: 2b00 cmp r3, #0 80139aa: d1e5 bne.n 8013978 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80139ac: 6efb ldr r3, [r7, #108] @ 0x6c 80139ae: 681b ldr r3, [r3, #0] 80139b0: 3314 adds r3, #20 80139b2: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80139b4: 6bbb ldr r3, [r7, #56] @ 0x38 80139b6: e853 3f00 ldrex r3, [r3] 80139ba: 637b str r3, [r7, #52] @ 0x34 return(result); 80139bc: 6b7b ldr r3, [r7, #52] @ 0x34 80139be: f023 0301 bic.w r3, r3, #1 80139c2: 667b str r3, [r7, #100] @ 0x64 80139c4: 6efb ldr r3, [r7, #108] @ 0x6c 80139c6: 681b ldr r3, [r3, #0] 80139c8: 3314 adds r3, #20 80139ca: 6e7a ldr r2, [r7, #100] @ 0x64 80139cc: 647a str r2, [r7, #68] @ 0x44 80139ce: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80139d0: 6c39 ldr r1, [r7, #64] @ 0x40 80139d2: 6c7a ldr r2, [r7, #68] @ 0x44 80139d4: e841 2300 strex r3, r2, [r1] 80139d8: 63fb str r3, [r7, #60] @ 0x3c return(result); 80139da: 6bfb ldr r3, [r7, #60] @ 0x3c 80139dc: 2b00 cmp r3, #0 80139de: d1e5 bne.n 80139ac /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80139e0: 6efb ldr r3, [r7, #108] @ 0x6c 80139e2: 681b ldr r3, [r3, #0] 80139e4: 3314 adds r3, #20 80139e6: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80139e8: 6a7b ldr r3, [r7, #36] @ 0x24 80139ea: e853 3f00 ldrex r3, [r3] 80139ee: 623b str r3, [r7, #32] return(result); 80139f0: 6a3b ldr r3, [r7, #32] 80139f2: f023 0340 bic.w r3, r3, #64 @ 0x40 80139f6: 663b str r3, [r7, #96] @ 0x60 80139f8: 6efb ldr r3, [r7, #108] @ 0x6c 80139fa: 681b ldr r3, [r3, #0] 80139fc: 3314 adds r3, #20 80139fe: 6e3a ldr r2, [r7, #96] @ 0x60 8013a00: 633a str r2, [r7, #48] @ 0x30 8013a02: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013a04: 6af9 ldr r1, [r7, #44] @ 0x2c 8013a06: 6b3a ldr r2, [r7, #48] @ 0x30 8013a08: e841 2300 strex r3, r2, [r1] 8013a0c: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013a0e: 6abb ldr r3, [r7, #40] @ 0x28 8013a10: 2b00 cmp r3, #0 8013a12: d1e5 bne.n 80139e0 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013a14: 6efb ldr r3, [r7, #108] @ 0x6c 8013a16: 2220 movs r2, #32 8013a18: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013a1c: 6efb ldr r3, [r7, #108] @ 0x6c 8013a1e: 6b1b ldr r3, [r3, #48] @ 0x30 8013a20: 2b01 cmp r3, #1 8013a22: d119 bne.n 8013a58 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013a24: 6efb ldr r3, [r7, #108] @ 0x6c 8013a26: 681b ldr r3, [r3, #0] 8013a28: 330c adds r3, #12 8013a2a: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013a2c: 693b ldr r3, [r7, #16] 8013a2e: e853 3f00 ldrex r3, [r3] 8013a32: 60fb str r3, [r7, #12] return(result); 8013a34: 68fb ldr r3, [r7, #12] 8013a36: f023 0310 bic.w r3, r3, #16 8013a3a: 65fb str r3, [r7, #92] @ 0x5c 8013a3c: 6efb ldr r3, [r7, #108] @ 0x6c 8013a3e: 681b ldr r3, [r3, #0] 8013a40: 330c adds r3, #12 8013a42: 6dfa ldr r2, [r7, #92] @ 0x5c 8013a44: 61fa str r2, [r7, #28] 8013a46: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013a48: 69b9 ldr r1, [r7, #24] 8013a4a: 69fa ldr r2, [r7, #28] 8013a4c: e841 2300 strex r3, r2, [r1] 8013a50: 617b str r3, [r7, #20] return(result); 8013a52: 697b ldr r3, [r7, #20] 8013a54: 2b00 cmp r3, #0 8013a56: d1e5 bne.n 8013a24 } } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8013a58: 6efb ldr r3, [r7, #108] @ 0x6c 8013a5a: 2200 movs r2, #0 8013a5c: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013a5e: 6efb ldr r3, [r7, #108] @ 0x6c 8013a60: 6b1b ldr r3, [r3, #48] @ 0x30 8013a62: 2b01 cmp r3, #1 8013a64: d106 bne.n 8013a74 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8013a66: 6efb ldr r3, [r7, #108] @ 0x6c 8013a68: 8d9b ldrh r3, [r3, #44] @ 0x2c 8013a6a: 4619 mov r1, r3 8013a6c: 6ef8 ldr r0, [r7, #108] @ 0x6c 8013a6e: f7f9 f843 bl 800caf8 #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8013a72: e002 b.n 8013a7a HAL_UART_RxCpltCallback(huart); 8013a74: 6ef8 ldr r0, [r7, #108] @ 0x6c 8013a76: f7ff fef6 bl 8013866 } 8013a7a: bf00 nop 8013a7c: 3770 adds r7, #112 @ 0x70 8013a7e: 46bd mov sp, r7 8013a80: bd80 pop {r7, pc} 08013a82 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { 8013a82: b580 push {r7, lr} 8013a84: b084 sub sp, #16 8013a86: af00 add r7, sp, #0 8013a88: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013a8a: 687b ldr r3, [r7, #4] 8013a8c: 6a5b ldr r3, [r3, #36] @ 0x24 8013a8e: 60fb str r3, [r7, #12] /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Half Transfer */ huart->RxEventType = HAL_UART_RXEVENT_HT; 8013a90: 68fb ldr r3, [r7, #12] 8013a92: 2201 movs r2, #1 8013a94: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013a96: 68fb ldr r3, [r7, #12] 8013a98: 6b1b ldr r3, [r3, #48] @ 0x30 8013a9a: 2b01 cmp r3, #1 8013a9c: d108 bne.n 8013ab0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); 8013a9e: 68fb ldr r3, [r7, #12] 8013aa0: 8d9b ldrh r3, [r3, #44] @ 0x2c 8013aa2: 085b lsrs r3, r3, #1 8013aa4: b29b uxth r3, r3 8013aa6: 4619 mov r1, r3 8013aa8: 68f8 ldr r0, [r7, #12] 8013aaa: f7f9 f825 bl 800caf8 #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8013aae: e002 b.n 8013ab6 HAL_UART_RxHalfCpltCallback(huart); 8013ab0: 68f8 ldr r0, [r7, #12] 8013ab2: f7ff fee1 bl 8013878 } 8013ab6: bf00 nop 8013ab8: 3710 adds r7, #16 8013aba: 46bd mov sp, r7 8013abc: bd80 pop {r7, pc} 08013abe : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 8013abe: b580 push {r7, lr} 8013ac0: b084 sub sp, #16 8013ac2: af00 add r7, sp, #0 8013ac4: 6078 str r0, [r7, #4] uint32_t dmarequest = 0x00U; 8013ac6: 2300 movs r3, #0 8013ac8: 60fb str r3, [r7, #12] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013aca: 687b ldr r3, [r7, #4] 8013acc: 6a5b ldr r3, [r3, #36] @ 0x24 8013ace: 60bb str r3, [r7, #8] /* Stop UART DMA Tx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 8013ad0: 68bb ldr r3, [r7, #8] 8013ad2: 681b ldr r3, [r3, #0] 8013ad4: 695b ldr r3, [r3, #20] 8013ad6: f003 0380 and.w r3, r3, #128 @ 0x80 8013ada: 2b00 cmp r3, #0 8013adc: bf14 ite ne 8013ade: 2301 movne r3, #1 8013ae0: 2300 moveq r3, #0 8013ae2: b2db uxtb r3, r3 8013ae4: 60fb str r3, [r7, #12] if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 8013ae6: 68bb ldr r3, [r7, #8] 8013ae8: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8013aec: b2db uxtb r3, r3 8013aee: 2b21 cmp r3, #33 @ 0x21 8013af0: d108 bne.n 8013b04 8013af2: 68fb ldr r3, [r7, #12] 8013af4: 2b00 cmp r3, #0 8013af6: d005 beq.n 8013b04 { huart->TxXferCount = 0x00U; 8013af8: 68bb ldr r3, [r7, #8] 8013afa: 2200 movs r2, #0 8013afc: 84da strh r2, [r3, #38] @ 0x26 UART_EndTxTransfer(huart); 8013afe: 68b8 ldr r0, [r7, #8] 8013b00: f000 f8fa bl 8013cf8 } /* Stop UART DMA Rx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8013b04: 68bb ldr r3, [r7, #8] 8013b06: 681b ldr r3, [r3, #0] 8013b08: 695b ldr r3, [r3, #20] 8013b0a: f003 0340 and.w r3, r3, #64 @ 0x40 8013b0e: 2b00 cmp r3, #0 8013b10: bf14 ite ne 8013b12: 2301 movne r3, #1 8013b14: 2300 moveq r3, #0 8013b16: b2db uxtb r3, r3 8013b18: 60fb str r3, [r7, #12] if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 8013b1a: 68bb ldr r3, [r7, #8] 8013b1c: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8013b20: b2db uxtb r3, r3 8013b22: 2b22 cmp r3, #34 @ 0x22 8013b24: d108 bne.n 8013b38 8013b26: 68fb ldr r3, [r7, #12] 8013b28: 2b00 cmp r3, #0 8013b2a: d005 beq.n 8013b38 { huart->RxXferCount = 0x00U; 8013b2c: 68bb ldr r3, [r7, #8] 8013b2e: 2200 movs r2, #0 8013b30: 85da strh r2, [r3, #46] @ 0x2e UART_EndRxTransfer(huart); 8013b32: 68b8 ldr r0, [r7, #8] 8013b34: f000 f907 bl 8013d46 } huart->ErrorCode |= HAL_UART_ERROR_DMA; 8013b38: 68bb ldr r3, [r7, #8] 8013b3a: 6c5b ldr r3, [r3, #68] @ 0x44 8013b3c: f043 0210 orr.w r2, r3, #16 8013b40: 68bb ldr r3, [r7, #8] 8013b42: 645a str r2, [r3, #68] @ 0x44 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013b44: 68b8 ldr r0, [r7, #8] 8013b46: f7f8 f88d bl 800bc64 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8013b4a: bf00 nop 8013b4c: 3710 adds r7, #16 8013b4e: 46bd mov sp, r7 8013b50: bd80 pop {r7, pc} 08013b52 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8013b52: b480 push {r7} 8013b54: b085 sub sp, #20 8013b56: af00 add r7, sp, #0 8013b58: 60f8 str r0, [r7, #12] 8013b5a: 60b9 str r1, [r7, #8] 8013b5c: 4613 mov r3, r2 8013b5e: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 8013b60: 68fb ldr r3, [r7, #12] 8013b62: 68ba ldr r2, [r7, #8] 8013b64: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 8013b66: 68fb ldr r3, [r7, #12] 8013b68: 88fa ldrh r2, [r7, #6] 8013b6a: 859a strh r2, [r3, #44] @ 0x2c huart->RxXferCount = Size; 8013b6c: 68fb ldr r3, [r7, #12] 8013b6e: 88fa ldrh r2, [r7, #6] 8013b70: 85da strh r2, [r3, #46] @ 0x2e huart->ErrorCode = HAL_UART_ERROR_NONE; 8013b72: 68fb ldr r3, [r7, #12] 8013b74: 2200 movs r2, #0 8013b76: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 8013b78: 68fb ldr r3, [r7, #12] 8013b7a: 2222 movs r2, #34 @ 0x22 8013b7c: f883 2042 strb.w r2, [r3, #66] @ 0x42 if (huart->Init.Parity != UART_PARITY_NONE) 8013b80: 68fb ldr r3, [r7, #12] 8013b82: 691b ldr r3, [r3, #16] 8013b84: 2b00 cmp r3, #0 8013b86: d007 beq.n 8013b98 { /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); 8013b88: 68fb ldr r3, [r7, #12] 8013b8a: 681b ldr r3, [r3, #0] 8013b8c: 68da ldr r2, [r3, #12] 8013b8e: 68fb ldr r3, [r7, #12] 8013b90: 681b ldr r3, [r3, #0] 8013b92: f442 7280 orr.w r2, r2, #256 @ 0x100 8013b96: 60da str r2, [r3, #12] } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); 8013b98: 68fb ldr r3, [r7, #12] 8013b9a: 681b ldr r3, [r3, #0] 8013b9c: 695a ldr r2, [r3, #20] 8013b9e: 68fb ldr r3, [r7, #12] 8013ba0: 681b ldr r3, [r3, #0] 8013ba2: f042 0201 orr.w r2, r2, #1 8013ba6: 615a str r2, [r3, #20] /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); 8013ba8: 68fb ldr r3, [r7, #12] 8013baa: 681b ldr r3, [r3, #0] 8013bac: 68da ldr r2, [r3, #12] 8013bae: 68fb ldr r3, [r7, #12] 8013bb0: 681b ldr r3, [r3, #0] 8013bb2: f042 0220 orr.w r2, r2, #32 8013bb6: 60da str r2, [r3, #12] return HAL_OK; 8013bb8: 2300 movs r3, #0 } 8013bba: 4618 mov r0, r3 8013bbc: 3714 adds r7, #20 8013bbe: 46bd mov sp, r7 8013bc0: bc80 pop {r7} 8013bc2: 4770 bx lr 08013bc4 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8013bc4: b580 push {r7, lr} 8013bc6: b098 sub sp, #96 @ 0x60 8013bc8: af00 add r7, sp, #0 8013bca: 60f8 str r0, [r7, #12] 8013bcc: 60b9 str r1, [r7, #8] 8013bce: 4613 mov r3, r2 8013bd0: 80fb strh r3, [r7, #6] uint32_t *tmp; huart->pRxBuffPtr = pData; 8013bd2: 68ba ldr r2, [r7, #8] 8013bd4: 68fb ldr r3, [r7, #12] 8013bd6: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 8013bd8: 68fb ldr r3, [r7, #12] 8013bda: 88fa ldrh r2, [r7, #6] 8013bdc: 859a strh r2, [r3, #44] @ 0x2c huart->ErrorCode = HAL_UART_ERROR_NONE; 8013bde: 68fb ldr r3, [r7, #12] 8013be0: 2200 movs r2, #0 8013be2: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 8013be4: 68fb ldr r3, [r7, #12] 8013be6: 2222 movs r2, #34 @ 0x22 8013be8: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 8013bec: 68fb ldr r3, [r7, #12] 8013bee: 6bdb ldr r3, [r3, #60] @ 0x3c 8013bf0: 4a3e ldr r2, [pc, #248] @ (8013cec ) 8013bf2: 629a str r2, [r3, #40] @ 0x28 /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 8013bf4: 68fb ldr r3, [r7, #12] 8013bf6: 6bdb ldr r3, [r3, #60] @ 0x3c 8013bf8: 4a3d ldr r2, [pc, #244] @ (8013cf0 ) 8013bfa: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; 8013bfc: 68fb ldr r3, [r7, #12] 8013bfe: 6bdb ldr r3, [r3, #60] @ 0x3c 8013c00: 4a3c ldr r2, [pc, #240] @ (8013cf4 ) 8013c02: 631a str r2, [r3, #48] @ 0x30 /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; 8013c04: 68fb ldr r3, [r7, #12] 8013c06: 6bdb ldr r3, [r3, #60] @ 0x3c 8013c08: 2200 movs r2, #0 8013c0a: 635a str r2, [r3, #52] @ 0x34 /* Enable the DMA stream */ tmp = (uint32_t *)&pData; 8013c0c: f107 0308 add.w r3, r7, #8 8013c10: 65fb str r3, [r7, #92] @ 0x5c HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size); 8013c12: 68fb ldr r3, [r7, #12] 8013c14: 6bd8 ldr r0, [r3, #60] @ 0x3c 8013c16: 68fb ldr r3, [r7, #12] 8013c18: 681b ldr r3, [r3, #0] 8013c1a: 3304 adds r3, #4 8013c1c: 4619 mov r1, r3 8013c1e: 6dfb ldr r3, [r7, #92] @ 0x5c 8013c20: 681a ldr r2, [r3, #0] 8013c22: 88fb ldrh r3, [r7, #6] 8013c24: f7fc f93a bl 800fe9c /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); 8013c28: 2300 movs r3, #0 8013c2a: 613b str r3, [r7, #16] 8013c2c: 68fb ldr r3, [r7, #12] 8013c2e: 681b ldr r3, [r3, #0] 8013c30: 681b ldr r3, [r3, #0] 8013c32: 613b str r3, [r7, #16] 8013c34: 68fb ldr r3, [r7, #12] 8013c36: 681b ldr r3, [r3, #0] 8013c38: 685b ldr r3, [r3, #4] 8013c3a: 613b str r3, [r7, #16] 8013c3c: 693b ldr r3, [r7, #16] if (huart->Init.Parity != UART_PARITY_NONE) 8013c3e: 68fb ldr r3, [r7, #12] 8013c40: 691b ldr r3, [r3, #16] 8013c42: 2b00 cmp r3, #0 8013c44: d019 beq.n 8013c7a { /* Enable the UART Parity Error Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8013c46: 68fb ldr r3, [r7, #12] 8013c48: 681b ldr r3, [r3, #0] 8013c4a: 330c adds r3, #12 8013c4c: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013c4e: 6c3b ldr r3, [r7, #64] @ 0x40 8013c50: e853 3f00 ldrex r3, [r3] 8013c54: 63fb str r3, [r7, #60] @ 0x3c return(result); 8013c56: 6bfb ldr r3, [r7, #60] @ 0x3c 8013c58: f443 7380 orr.w r3, r3, #256 @ 0x100 8013c5c: 65bb str r3, [r7, #88] @ 0x58 8013c5e: 68fb ldr r3, [r7, #12] 8013c60: 681b ldr r3, [r3, #0] 8013c62: 330c adds r3, #12 8013c64: 6dba ldr r2, [r7, #88] @ 0x58 8013c66: 64fa str r2, [r7, #76] @ 0x4c 8013c68: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013c6a: 6cb9 ldr r1, [r7, #72] @ 0x48 8013c6c: 6cfa ldr r2, [r7, #76] @ 0x4c 8013c6e: e841 2300 strex r3, r2, [r1] 8013c72: 647b str r3, [r7, #68] @ 0x44 return(result); 8013c74: 6c7b ldr r3, [r7, #68] @ 0x44 8013c76: 2b00 cmp r3, #0 8013c78: d1e5 bne.n 8013c46 } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013c7a: 68fb ldr r3, [r7, #12] 8013c7c: 681b ldr r3, [r3, #0] 8013c7e: 3314 adds r3, #20 8013c80: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013c82: 6afb ldr r3, [r7, #44] @ 0x2c 8013c84: e853 3f00 ldrex r3, [r3] 8013c88: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013c8a: 6abb ldr r3, [r7, #40] @ 0x28 8013c8c: f043 0301 orr.w r3, r3, #1 8013c90: 657b str r3, [r7, #84] @ 0x54 8013c92: 68fb ldr r3, [r7, #12] 8013c94: 681b ldr r3, [r3, #0] 8013c96: 3314 adds r3, #20 8013c98: 6d7a ldr r2, [r7, #84] @ 0x54 8013c9a: 63ba str r2, [r7, #56] @ 0x38 8013c9c: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013c9e: 6b79 ldr r1, [r7, #52] @ 0x34 8013ca0: 6bba ldr r2, [r7, #56] @ 0x38 8013ca2: e841 2300 strex r3, r2, [r1] 8013ca6: 633b str r3, [r7, #48] @ 0x30 return(result); 8013ca8: 6b3b ldr r3, [r7, #48] @ 0x30 8013caa: 2b00 cmp r3, #0 8013cac: d1e5 bne.n 8013c7a /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8013cae: 68fb ldr r3, [r7, #12] 8013cb0: 681b ldr r3, [r3, #0] 8013cb2: 3314 adds r3, #20 8013cb4: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013cb6: 69bb ldr r3, [r7, #24] 8013cb8: e853 3f00 ldrex r3, [r3] 8013cbc: 617b str r3, [r7, #20] return(result); 8013cbe: 697b ldr r3, [r7, #20] 8013cc0: f043 0340 orr.w r3, r3, #64 @ 0x40 8013cc4: 653b str r3, [r7, #80] @ 0x50 8013cc6: 68fb ldr r3, [r7, #12] 8013cc8: 681b ldr r3, [r3, #0] 8013cca: 3314 adds r3, #20 8013ccc: 6d3a ldr r2, [r7, #80] @ 0x50 8013cce: 627a str r2, [r7, #36] @ 0x24 8013cd0: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013cd2: 6a39 ldr r1, [r7, #32] 8013cd4: 6a7a ldr r2, [r7, #36] @ 0x24 8013cd6: e841 2300 strex r3, r2, [r1] 8013cda: 61fb str r3, [r7, #28] return(result); 8013cdc: 69fb ldr r3, [r7, #28] 8013cde: 2b00 cmp r3, #0 8013ce0: d1e5 bne.n 8013cae return HAL_OK; 8013ce2: 2300 movs r3, #0 } 8013ce4: 4618 mov r0, r3 8013ce6: 3760 adds r7, #96 @ 0x60 8013ce8: 46bd mov sp, r7 8013cea: bd80 pop {r7, pc} 8013cec: 08013957 .word 0x08013957 8013cf0: 08013a83 .word 0x08013a83 8013cf4: 08013abf .word 0x08013abf 08013cf8 : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 8013cf8: b480 push {r7} 8013cfa: b089 sub sp, #36 @ 0x24 8013cfc: af00 add r7, sp, #0 8013cfe: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 8013d00: 687b ldr r3, [r7, #4] 8013d02: 681b ldr r3, [r3, #0] 8013d04: 330c adds r3, #12 8013d06: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013d08: 68fb ldr r3, [r7, #12] 8013d0a: e853 3f00 ldrex r3, [r3] 8013d0e: 60bb str r3, [r7, #8] return(result); 8013d10: 68bb ldr r3, [r7, #8] 8013d12: f023 03c0 bic.w r3, r3, #192 @ 0xc0 8013d16: 61fb str r3, [r7, #28] 8013d18: 687b ldr r3, [r7, #4] 8013d1a: 681b ldr r3, [r3, #0] 8013d1c: 330c adds r3, #12 8013d1e: 69fa ldr r2, [r7, #28] 8013d20: 61ba str r2, [r7, #24] 8013d22: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013d24: 6979 ldr r1, [r7, #20] 8013d26: 69ba ldr r2, [r7, #24] 8013d28: e841 2300 strex r3, r2, [r1] 8013d2c: 613b str r3, [r7, #16] return(result); 8013d2e: 693b ldr r3, [r7, #16] 8013d30: 2b00 cmp r3, #0 8013d32: d1e5 bne.n 8013d00 /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8013d34: 687b ldr r3, [r7, #4] 8013d36: 2220 movs r2, #32 8013d38: f883 2041 strb.w r2, [r3, #65] @ 0x41 } 8013d3c: bf00 nop 8013d3e: 3724 adds r7, #36 @ 0x24 8013d40: 46bd mov sp, r7 8013d42: bc80 pop {r7} 8013d44: 4770 bx lr 08013d46 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8013d46: b480 push {r7} 8013d48: b095 sub sp, #84 @ 0x54 8013d4a: af00 add r7, sp, #0 8013d4c: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8013d4e: 687b ldr r3, [r7, #4] 8013d50: 681b ldr r3, [r3, #0] 8013d52: 330c adds r3, #12 8013d54: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013d56: 6b7b ldr r3, [r7, #52] @ 0x34 8013d58: e853 3f00 ldrex r3, [r3] 8013d5c: 633b str r3, [r7, #48] @ 0x30 return(result); 8013d5e: 6b3b ldr r3, [r7, #48] @ 0x30 8013d60: f423 7390 bic.w r3, r3, #288 @ 0x120 8013d64: 64fb str r3, [r7, #76] @ 0x4c 8013d66: 687b ldr r3, [r7, #4] 8013d68: 681b ldr r3, [r3, #0] 8013d6a: 330c adds r3, #12 8013d6c: 6cfa ldr r2, [r7, #76] @ 0x4c 8013d6e: 643a str r2, [r7, #64] @ 0x40 8013d70: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013d72: 6bf9 ldr r1, [r7, #60] @ 0x3c 8013d74: 6c3a ldr r2, [r7, #64] @ 0x40 8013d76: e841 2300 strex r3, r2, [r1] 8013d7a: 63bb str r3, [r7, #56] @ 0x38 return(result); 8013d7c: 6bbb ldr r3, [r7, #56] @ 0x38 8013d7e: 2b00 cmp r3, #0 8013d80: d1e5 bne.n 8013d4e ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013d82: 687b ldr r3, [r7, #4] 8013d84: 681b ldr r3, [r3, #0] 8013d86: 3314 adds r3, #20 8013d88: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013d8a: 6a3b ldr r3, [r7, #32] 8013d8c: e853 3f00 ldrex r3, [r3] 8013d90: 61fb str r3, [r7, #28] return(result); 8013d92: 69fb ldr r3, [r7, #28] 8013d94: f023 0301 bic.w r3, r3, #1 8013d98: 64bb str r3, [r7, #72] @ 0x48 8013d9a: 687b ldr r3, [r7, #4] 8013d9c: 681b ldr r3, [r3, #0] 8013d9e: 3314 adds r3, #20 8013da0: 6cba ldr r2, [r7, #72] @ 0x48 8013da2: 62fa str r2, [r7, #44] @ 0x2c 8013da4: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013da6: 6ab9 ldr r1, [r7, #40] @ 0x28 8013da8: 6afa ldr r2, [r7, #44] @ 0x2c 8013daa: e841 2300 strex r3, r2, [r1] 8013dae: 627b str r3, [r7, #36] @ 0x24 return(result); 8013db0: 6a7b ldr r3, [r7, #36] @ 0x24 8013db2: 2b00 cmp r3, #0 8013db4: d1e5 bne.n 8013d82 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013db6: 687b ldr r3, [r7, #4] 8013db8: 6b1b ldr r3, [r3, #48] @ 0x30 8013dba: 2b01 cmp r3, #1 8013dbc: d119 bne.n 8013df2 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013dbe: 687b ldr r3, [r7, #4] 8013dc0: 681b ldr r3, [r3, #0] 8013dc2: 330c adds r3, #12 8013dc4: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013dc6: 68fb ldr r3, [r7, #12] 8013dc8: e853 3f00 ldrex r3, [r3] 8013dcc: 60bb str r3, [r7, #8] return(result); 8013dce: 68bb ldr r3, [r7, #8] 8013dd0: f023 0310 bic.w r3, r3, #16 8013dd4: 647b str r3, [r7, #68] @ 0x44 8013dd6: 687b ldr r3, [r7, #4] 8013dd8: 681b ldr r3, [r3, #0] 8013dda: 330c adds r3, #12 8013ddc: 6c7a ldr r2, [r7, #68] @ 0x44 8013dde: 61ba str r2, [r7, #24] 8013de0: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013de2: 6979 ldr r1, [r7, #20] 8013de4: 69ba ldr r2, [r7, #24] 8013de6: e841 2300 strex r3, r2, [r1] 8013dea: 613b str r3, [r7, #16] return(result); 8013dec: 693b ldr r3, [r7, #16] 8013dee: 2b00 cmp r3, #0 8013df0: d1e5 bne.n 8013dbe } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013df2: 687b ldr r3, [r7, #4] 8013df4: 2220 movs r2, #32 8013df6: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013dfa: 687b ldr r3, [r7, #4] 8013dfc: 2200 movs r2, #0 8013dfe: 631a str r2, [r3, #48] @ 0x30 } 8013e00: bf00 nop 8013e02: 3754 adds r7, #84 @ 0x54 8013e04: 46bd mov sp, r7 8013e06: bc80 pop {r7} 8013e08: 4770 bx lr 08013e0a : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8013e0a: b580 push {r7, lr} 8013e0c: b084 sub sp, #16 8013e0e: af00 add r7, sp, #0 8013e10: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013e12: 687b ldr r3, [r7, #4] 8013e14: 6a5b ldr r3, [r3, #36] @ 0x24 8013e16: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8013e18: 68fb ldr r3, [r7, #12] 8013e1a: 2200 movs r2, #0 8013e1c: 85da strh r2, [r3, #46] @ 0x2e huart->TxXferCount = 0x00U; 8013e1e: 68fb ldr r3, [r7, #12] 8013e20: 2200 movs r2, #0 8013e22: 84da strh r2, [r3, #38] @ 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013e24: 68f8 ldr r0, [r7, #12] 8013e26: f7f7 ff1d bl 800bc64 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8013e2a: bf00 nop 8013e2c: 3710 adds r7, #16 8013e2e: 46bd mov sp, r7 8013e30: bd80 pop {r7, pc} 08013e32 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 8013e32: b480 push {r7} 8013e34: b085 sub sp, #20 8013e36: af00 add r7, sp, #0 8013e38: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8013e3a: 687b ldr r3, [r7, #4] 8013e3c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8013e40: b2db uxtb r3, r3 8013e42: 2b21 cmp r3, #33 @ 0x21 8013e44: d13e bne.n 8013ec4 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8013e46: 687b ldr r3, [r7, #4] 8013e48: 689b ldr r3, [r3, #8] 8013e4a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8013e4e: d114 bne.n 8013e7a 8013e50: 687b ldr r3, [r7, #4] 8013e52: 691b ldr r3, [r3, #16] 8013e54: 2b00 cmp r3, #0 8013e56: d110 bne.n 8013e7a { tmp = (const uint16_t *) huart->pTxBuffPtr; 8013e58: 687b ldr r3, [r7, #4] 8013e5a: 6a1b ldr r3, [r3, #32] 8013e5c: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8013e5e: 68fb ldr r3, [r7, #12] 8013e60: 881b ldrh r3, [r3, #0] 8013e62: 461a mov r2, r3 8013e64: 687b ldr r3, [r7, #4] 8013e66: 681b ldr r3, [r3, #0] 8013e68: f3c2 0208 ubfx r2, r2, #0, #9 8013e6c: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 8013e6e: 687b ldr r3, [r7, #4] 8013e70: 6a1b ldr r3, [r3, #32] 8013e72: 1c9a adds r2, r3, #2 8013e74: 687b ldr r3, [r7, #4] 8013e76: 621a str r2, [r3, #32] 8013e78: e008 b.n 8013e8c } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 8013e7a: 687b ldr r3, [r7, #4] 8013e7c: 6a1b ldr r3, [r3, #32] 8013e7e: 1c59 adds r1, r3, #1 8013e80: 687a ldr r2, [r7, #4] 8013e82: 6211 str r1, [r2, #32] 8013e84: 781a ldrb r2, [r3, #0] 8013e86: 687b ldr r3, [r7, #4] 8013e88: 681b ldr r3, [r3, #0] 8013e8a: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 8013e8c: 687b ldr r3, [r7, #4] 8013e8e: 8cdb ldrh r3, [r3, #38] @ 0x26 8013e90: b29b uxth r3, r3 8013e92: 3b01 subs r3, #1 8013e94: b29b uxth r3, r3 8013e96: 687a ldr r2, [r7, #4] 8013e98: 4619 mov r1, r3 8013e9a: 84d1 strh r1, [r2, #38] @ 0x26 8013e9c: 2b00 cmp r3, #0 8013e9e: d10f bne.n 8013ec0 { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8013ea0: 687b ldr r3, [r7, #4] 8013ea2: 681b ldr r3, [r3, #0] 8013ea4: 68da ldr r2, [r3, #12] 8013ea6: 687b ldr r3, [r7, #4] 8013ea8: 681b ldr r3, [r3, #0] 8013eaa: f022 0280 bic.w r2, r2, #128 @ 0x80 8013eae: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8013eb0: 687b ldr r3, [r7, #4] 8013eb2: 681b ldr r3, [r3, #0] 8013eb4: 68da ldr r2, [r3, #12] 8013eb6: 687b ldr r3, [r7, #4] 8013eb8: 681b ldr r3, [r3, #0] 8013eba: f042 0240 orr.w r2, r2, #64 @ 0x40 8013ebe: 60da str r2, [r3, #12] } return HAL_OK; 8013ec0: 2300 movs r3, #0 8013ec2: e000 b.n 8013ec6 } else { return HAL_BUSY; 8013ec4: 2302 movs r3, #2 } } 8013ec6: 4618 mov r0, r3 8013ec8: 3714 adds r7, #20 8013eca: 46bd mov sp, r7 8013ecc: bc80 pop {r7} 8013ece: 4770 bx lr 08013ed0 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8013ed0: b580 push {r7, lr} 8013ed2: b082 sub sp, #8 8013ed4: af00 add r7, sp, #0 8013ed6: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 8013ed8: 687b ldr r3, [r7, #4] 8013eda: 681b ldr r3, [r3, #0] 8013edc: 68da ldr r2, [r3, #12] 8013ede: 687b ldr r3, [r7, #4] 8013ee0: 681b ldr r3, [r3, #0] 8013ee2: f022 0240 bic.w r2, r2, #64 @ 0x40 8013ee6: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8013ee8: 687b ldr r3, [r7, #4] 8013eea: 2220 movs r2, #32 8013eec: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8013ef0: 6878 ldr r0, [r7, #4] 8013ef2: f7f8 fe7b bl 800cbec #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8013ef6: 2300 movs r3, #0 } 8013ef8: 4618 mov r0, r3 8013efa: 3708 adds r7, #8 8013efc: 46bd mov sp, r7 8013efe: bd80 pop {r7, pc} 08013f00 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 8013f00: b580 push {r7, lr} 8013f02: b08c sub sp, #48 @ 0x30 8013f04: af00 add r7, sp, #0 8013f06: 6078 str r0, [r7, #4] uint8_t *pdata8bits; uint16_t *pdata16bits; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8013f08: 687b ldr r3, [r7, #4] 8013f0a: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8013f0e: b2db uxtb r3, r3 8013f10: 2b22 cmp r3, #34 @ 0x22 8013f12: f040 80ae bne.w 8014072 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8013f16: 687b ldr r3, [r7, #4] 8013f18: 689b ldr r3, [r3, #8] 8013f1a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8013f1e: d117 bne.n 8013f50 8013f20: 687b ldr r3, [r7, #4] 8013f22: 691b ldr r3, [r3, #16] 8013f24: 2b00 cmp r3, #0 8013f26: d113 bne.n 8013f50 { pdata8bits = NULL; 8013f28: 2300 movs r3, #0 8013f2a: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = (uint16_t *) huart->pRxBuffPtr; 8013f2c: 687b ldr r3, [r7, #4] 8013f2e: 6a9b ldr r3, [r3, #40] @ 0x28 8013f30: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8013f32: 687b ldr r3, [r7, #4] 8013f34: 681b ldr r3, [r3, #0] 8013f36: 685b ldr r3, [r3, #4] 8013f38: b29b uxth r3, r3 8013f3a: f3c3 0308 ubfx r3, r3, #0, #9 8013f3e: b29a uxth r2, r3 8013f40: 6abb ldr r3, [r7, #40] @ 0x28 8013f42: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8013f44: 687b ldr r3, [r7, #4] 8013f46: 6a9b ldr r3, [r3, #40] @ 0x28 8013f48: 1c9a adds r2, r3, #2 8013f4a: 687b ldr r3, [r7, #4] 8013f4c: 629a str r2, [r3, #40] @ 0x28 8013f4e: e026 b.n 8013f9e } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8013f50: 687b ldr r3, [r7, #4] 8013f52: 6a9b ldr r3, [r3, #40] @ 0x28 8013f54: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = NULL; 8013f56: 2300 movs r3, #0 8013f58: 62bb str r3, [r7, #40] @ 0x28 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 8013f5a: 687b ldr r3, [r7, #4] 8013f5c: 689b ldr r3, [r3, #8] 8013f5e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8013f62: d007 beq.n 8013f74 8013f64: 687b ldr r3, [r7, #4] 8013f66: 689b ldr r3, [r3, #8] 8013f68: 2b00 cmp r3, #0 8013f6a: d10a bne.n 8013f82 8013f6c: 687b ldr r3, [r7, #4] 8013f6e: 691b ldr r3, [r3, #16] 8013f70: 2b00 cmp r3, #0 8013f72: d106 bne.n 8013f82 { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8013f74: 687b ldr r3, [r7, #4] 8013f76: 681b ldr r3, [r3, #0] 8013f78: 685b ldr r3, [r3, #4] 8013f7a: b2da uxtb r2, r3 8013f7c: 6afb ldr r3, [r7, #44] @ 0x2c 8013f7e: 701a strb r2, [r3, #0] 8013f80: e008 b.n 8013f94 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8013f82: 687b ldr r3, [r7, #4] 8013f84: 681b ldr r3, [r3, #0] 8013f86: 685b ldr r3, [r3, #4] 8013f88: b2db uxtb r3, r3 8013f8a: f003 037f and.w r3, r3, #127 @ 0x7f 8013f8e: b2da uxtb r2, r3 8013f90: 6afb ldr r3, [r7, #44] @ 0x2c 8013f92: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8013f94: 687b ldr r3, [r7, #4] 8013f96: 6a9b ldr r3, [r3, #40] @ 0x28 8013f98: 1c5a adds r2, r3, #1 8013f9a: 687b ldr r3, [r7, #4] 8013f9c: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 8013f9e: 687b ldr r3, [r7, #4] 8013fa0: 8ddb ldrh r3, [r3, #46] @ 0x2e 8013fa2: b29b uxth r3, r3 8013fa4: 3b01 subs r3, #1 8013fa6: b29b uxth r3, r3 8013fa8: 687a ldr r2, [r7, #4] 8013faa: 4619 mov r1, r3 8013fac: 85d1 strh r1, [r2, #46] @ 0x2e 8013fae: 2b00 cmp r3, #0 8013fb0: d15d bne.n 801406e { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8013fb2: 687b ldr r3, [r7, #4] 8013fb4: 681b ldr r3, [r3, #0] 8013fb6: 68da ldr r2, [r3, #12] 8013fb8: 687b ldr r3, [r7, #4] 8013fba: 681b ldr r3, [r3, #0] 8013fbc: f022 0220 bic.w r2, r2, #32 8013fc0: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8013fc2: 687b ldr r3, [r7, #4] 8013fc4: 681b ldr r3, [r3, #0] 8013fc6: 68da ldr r2, [r3, #12] 8013fc8: 687b ldr r3, [r7, #4] 8013fca: 681b ldr r3, [r3, #0] 8013fcc: f422 7280 bic.w r2, r2, #256 @ 0x100 8013fd0: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8013fd2: 687b ldr r3, [r7, #4] 8013fd4: 681b ldr r3, [r3, #0] 8013fd6: 695a ldr r2, [r3, #20] 8013fd8: 687b ldr r3, [r7, #4] 8013fda: 681b ldr r3, [r3, #0] 8013fdc: f022 0201 bic.w r2, r2, #1 8013fe0: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013fe2: 687b ldr r3, [r7, #4] 8013fe4: 2220 movs r2, #32 8013fe6: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8013fea: 687b ldr r3, [r7, #4] 8013fec: 2200 movs r2, #0 8013fee: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013ff0: 687b ldr r3, [r7, #4] 8013ff2: 6b1b ldr r3, [r3, #48] @ 0x30 8013ff4: 2b01 cmp r3, #1 8013ff6: d135 bne.n 8014064 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013ff8: 687b ldr r3, [r7, #4] 8013ffa: 2200 movs r2, #0 8013ffc: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013ffe: 687b ldr r3, [r7, #4] 8014000: 681b ldr r3, [r3, #0] 8014002: 330c adds r3, #12 8014004: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8014006: 697b ldr r3, [r7, #20] 8014008: e853 3f00 ldrex r3, [r3] 801400c: 613b str r3, [r7, #16] return(result); 801400e: 693b ldr r3, [r7, #16] 8014010: f023 0310 bic.w r3, r3, #16 8014014: 627b str r3, [r7, #36] @ 0x24 8014016: 687b ldr r3, [r7, #4] 8014018: 681b ldr r3, [r3, #0] 801401a: 330c adds r3, #12 801401c: 6a7a ldr r2, [r7, #36] @ 0x24 801401e: 623a str r2, [r7, #32] 8014020: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8014022: 69f9 ldr r1, [r7, #28] 8014024: 6a3a ldr r2, [r7, #32] 8014026: e841 2300 strex r3, r2, [r1] 801402a: 61bb str r3, [r7, #24] return(result); 801402c: 69bb ldr r3, [r7, #24] 801402e: 2b00 cmp r3, #0 8014030: d1e5 bne.n 8013ffe /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 8014032: 687b ldr r3, [r7, #4] 8014034: 681b ldr r3, [r3, #0] 8014036: 681b ldr r3, [r3, #0] 8014038: f003 0310 and.w r3, r3, #16 801403c: 2b10 cmp r3, #16 801403e: d10a bne.n 8014056 { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 8014040: 2300 movs r3, #0 8014042: 60fb str r3, [r7, #12] 8014044: 687b ldr r3, [r7, #4] 8014046: 681b ldr r3, [r3, #0] 8014048: 681b ldr r3, [r3, #0] 801404a: 60fb str r3, [r7, #12] 801404c: 687b ldr r3, [r7, #4] 801404e: 681b ldr r3, [r3, #0] 8014050: 685b ldr r3, [r3, #4] 8014052: 60fb str r3, [r7, #12] 8014054: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8014056: 687b ldr r3, [r7, #4] 8014058: 8d9b ldrh r3, [r3, #44] @ 0x2c 801405a: 4619 mov r1, r3 801405c: 6878 ldr r0, [r7, #4] 801405e: f7f8 fd4b bl 800caf8 8014062: e002 b.n 801406a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8014064: 6878 ldr r0, [r7, #4] 8014066: f7ff fbfe bl 8013866 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 801406a: 2300 movs r3, #0 801406c: e002 b.n 8014074 } return HAL_OK; 801406e: 2300 movs r3, #0 8014070: e000 b.n 8014074 } else { return HAL_BUSY; 8014072: 2302 movs r3, #2 } } 8014074: 4618 mov r0, r3 8014076: 3730 adds r7, #48 @ 0x30 8014078: 46bd mov sp, r7 801407a: bd80 pop {r7, pc} 0801407c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 801407c: b580 push {r7, lr} 801407e: b084 sub sp, #16 8014080: af00 add r7, sp, #0 8014082: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8014084: 687b ldr r3, [r7, #4] 8014086: 681b ldr r3, [r3, #0] 8014088: 691b ldr r3, [r3, #16] 801408a: f423 5140 bic.w r1, r3, #12288 @ 0x3000 801408e: 687b ldr r3, [r7, #4] 8014090: 68da ldr r2, [r3, #12] 8014092: 687b ldr r3, [r7, #4] 8014094: 681b ldr r3, [r3, #0] 8014096: 430a orrs r2, r1 8014098: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 801409a: 687b ldr r3, [r7, #4] 801409c: 689a ldr r2, [r3, #8] 801409e: 687b ldr r3, [r7, #4] 80140a0: 691b ldr r3, [r3, #16] 80140a2: 431a orrs r2, r3 80140a4: 687b ldr r3, [r7, #4] 80140a6: 695b ldr r3, [r3, #20] 80140a8: 4313 orrs r3, r2 80140aa: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 80140ac: 687b ldr r3, [r7, #4] 80140ae: 681b ldr r3, [r3, #0] 80140b0: 68db ldr r3, [r3, #12] 80140b2: f423 53b0 bic.w r3, r3, #5632 @ 0x1600 80140b6: f023 030c bic.w r3, r3, #12 80140ba: 687a ldr r2, [r7, #4] 80140bc: 6812 ldr r2, [r2, #0] 80140be: 68b9 ldr r1, [r7, #8] 80140c0: 430b orrs r3, r1 80140c2: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 80140c4: 687b ldr r3, [r7, #4] 80140c6: 681b ldr r3, [r3, #0] 80140c8: 695b ldr r3, [r3, #20] 80140ca: f423 7140 bic.w r1, r3, #768 @ 0x300 80140ce: 687b ldr r3, [r7, #4] 80140d0: 699a ldr r2, [r3, #24] 80140d2: 687b ldr r3, [r7, #4] 80140d4: 681b ldr r3, [r3, #0] 80140d6: 430a orrs r2, r1 80140d8: 615a str r2, [r3, #20] if(huart->Instance == USART1) 80140da: 687b ldr r3, [r7, #4] 80140dc: 681b ldr r3, [r3, #0] 80140de: 4a2c ldr r2, [pc, #176] @ (8014190 ) 80140e0: 4293 cmp r3, r2 80140e2: d103 bne.n 80140ec { pclk = HAL_RCC_GetPCLK2Freq(); 80140e4: f7fd fa5c bl 80115a0 80140e8: 60f8 str r0, [r7, #12] 80140ea: e002 b.n 80140f2 } else { pclk = HAL_RCC_GetPCLK1Freq(); 80140ec: f7fd fa44 bl 8011578 80140f0: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 80140f2: 68fa ldr r2, [r7, #12] 80140f4: 4613 mov r3, r2 80140f6: 009b lsls r3, r3, #2 80140f8: 4413 add r3, r2 80140fa: 009a lsls r2, r3, #2 80140fc: 441a add r2, r3 80140fe: 687b ldr r3, [r7, #4] 8014100: 685b ldr r3, [r3, #4] 8014102: 009b lsls r3, r3, #2 8014104: fbb2 f3f3 udiv r3, r2, r3 8014108: 4a22 ldr r2, [pc, #136] @ (8014194 ) 801410a: fba2 2303 umull r2, r3, r2, r3 801410e: 095b lsrs r3, r3, #5 8014110: 0119 lsls r1, r3, #4 8014112: 68fa ldr r2, [r7, #12] 8014114: 4613 mov r3, r2 8014116: 009b lsls r3, r3, #2 8014118: 4413 add r3, r2 801411a: 009a lsls r2, r3, #2 801411c: 441a add r2, r3 801411e: 687b ldr r3, [r7, #4] 8014120: 685b ldr r3, [r3, #4] 8014122: 009b lsls r3, r3, #2 8014124: fbb2 f2f3 udiv r2, r2, r3 8014128: 4b1a ldr r3, [pc, #104] @ (8014194 ) 801412a: fba3 0302 umull r0, r3, r3, r2 801412e: 095b lsrs r3, r3, #5 8014130: 2064 movs r0, #100 @ 0x64 8014132: fb00 f303 mul.w r3, r0, r3 8014136: 1ad3 subs r3, r2, r3 8014138: 011b lsls r3, r3, #4 801413a: 3332 adds r3, #50 @ 0x32 801413c: 4a15 ldr r2, [pc, #84] @ (8014194 ) 801413e: fba2 2303 umull r2, r3, r2, r3 8014142: 095b lsrs r3, r3, #5 8014144: f003 03f0 and.w r3, r3, #240 @ 0xf0 8014148: 4419 add r1, r3 801414a: 68fa ldr r2, [r7, #12] 801414c: 4613 mov r3, r2 801414e: 009b lsls r3, r3, #2 8014150: 4413 add r3, r2 8014152: 009a lsls r2, r3, #2 8014154: 441a add r2, r3 8014156: 687b ldr r3, [r7, #4] 8014158: 685b ldr r3, [r3, #4] 801415a: 009b lsls r3, r3, #2 801415c: fbb2 f2f3 udiv r2, r2, r3 8014160: 4b0c ldr r3, [pc, #48] @ (8014194 ) 8014162: fba3 0302 umull r0, r3, r3, r2 8014166: 095b lsrs r3, r3, #5 8014168: 2064 movs r0, #100 @ 0x64 801416a: fb00 f303 mul.w r3, r0, r3 801416e: 1ad3 subs r3, r2, r3 8014170: 011b lsls r3, r3, #4 8014172: 3332 adds r3, #50 @ 0x32 8014174: 4a07 ldr r2, [pc, #28] @ (8014194 ) 8014176: fba2 2303 umull r2, r3, r2, r3 801417a: 095b lsrs r3, r3, #5 801417c: f003 020f and.w r2, r3, #15 8014180: 687b ldr r3, [r7, #4] 8014182: 681b ldr r3, [r3, #0] 8014184: 440a add r2, r1 8014186: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 8014188: bf00 nop 801418a: 3710 adds r7, #16 801418c: 46bd mov sp, r7 801418e: bd80 pop {r7, pc} 8014190: 40013800 .word 0x40013800 8014194: 51eb851f .word 0x51eb851f 08014198 <__cvt>: 8014198: 2b00 cmp r3, #0 801419a: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 801419e: 461d mov r5, r3 80141a0: bfbb ittet lt 80141a2: f103 4300 addlt.w r3, r3, #2147483648 @ 0x80000000 80141a6: 461d movlt r5, r3 80141a8: 2300 movge r3, #0 80141aa: 232d movlt r3, #45 @ 0x2d 80141ac: b088 sub sp, #32 80141ae: 4614 mov r4, r2 80141b0: bfb8 it lt 80141b2: 4614 movlt r4, r2 80141b4: 9a12 ldr r2, [sp, #72] @ 0x48 80141b6: 9e10 ldr r6, [sp, #64] @ 0x40 80141b8: 7013 strb r3, [r2, #0] 80141ba: 9b14 ldr r3, [sp, #80] @ 0x50 80141bc: f8dd a04c ldr.w sl, [sp, #76] @ 0x4c 80141c0: f023 0820 bic.w r8, r3, #32 80141c4: f1b8 0f46 cmp.w r8, #70 @ 0x46 80141c8: d005 beq.n 80141d6 <__cvt+0x3e> 80141ca: f1b8 0f45 cmp.w r8, #69 @ 0x45 80141ce: d100 bne.n 80141d2 <__cvt+0x3a> 80141d0: 3601 adds r6, #1 80141d2: 2302 movs r3, #2 80141d4: e000 b.n 80141d8 <__cvt+0x40> 80141d6: 2303 movs r3, #3 80141d8: aa07 add r2, sp, #28 80141da: 9204 str r2, [sp, #16] 80141dc: aa06 add r2, sp, #24 80141de: e9cd a202 strd sl, r2, [sp, #8] 80141e2: e9cd 3600 strd r3, r6, [sp] 80141e6: 4622 mov r2, r4 80141e8: 462b mov r3, r5 80141ea: f000 fe29 bl 8014e40 <_dtoa_r> 80141ee: f1b8 0f47 cmp.w r8, #71 @ 0x47 80141f2: 4607 mov r7, r0 80141f4: d119 bne.n 801422a <__cvt+0x92> 80141f6: 9b11 ldr r3, [sp, #68] @ 0x44 80141f8: 07db lsls r3, r3, #31 80141fa: d50e bpl.n 801421a <__cvt+0x82> 80141fc: eb00 0906 add.w r9, r0, r6 8014200: 2200 movs r2, #0 8014202: 2300 movs r3, #0 8014204: 4620 mov r0, r4 8014206: 4629 mov r1, r5 8014208: f7f4 fc3a bl 8008a80 <__aeabi_dcmpeq> 801420c: b108 cbz r0, 8014212 <__cvt+0x7a> 801420e: f8cd 901c str.w r9, [sp, #28] 8014212: 2230 movs r2, #48 @ 0x30 8014214: 9b07 ldr r3, [sp, #28] 8014216: 454b cmp r3, r9 8014218: d31e bcc.n 8014258 <__cvt+0xc0> 801421a: 4638 mov r0, r7 801421c: 9b07 ldr r3, [sp, #28] 801421e: 9a15 ldr r2, [sp, #84] @ 0x54 8014220: 1bdb subs r3, r3, r7 8014222: 6013 str r3, [r2, #0] 8014224: b008 add sp, #32 8014226: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801422a: f1b8 0f46 cmp.w r8, #70 @ 0x46 801422e: eb00 0906 add.w r9, r0, r6 8014232: d1e5 bne.n 8014200 <__cvt+0x68> 8014234: 7803 ldrb r3, [r0, #0] 8014236: 2b30 cmp r3, #48 @ 0x30 8014238: d10a bne.n 8014250 <__cvt+0xb8> 801423a: 2200 movs r2, #0 801423c: 2300 movs r3, #0 801423e: 4620 mov r0, r4 8014240: 4629 mov r1, r5 8014242: f7f4 fc1d bl 8008a80 <__aeabi_dcmpeq> 8014246: b918 cbnz r0, 8014250 <__cvt+0xb8> 8014248: f1c6 0601 rsb r6, r6, #1 801424c: f8ca 6000 str.w r6, [sl] 8014250: f8da 3000 ldr.w r3, [sl] 8014254: 4499 add r9, r3 8014256: e7d3 b.n 8014200 <__cvt+0x68> 8014258: 1c59 adds r1, r3, #1 801425a: 9107 str r1, [sp, #28] 801425c: 701a strb r2, [r3, #0] 801425e: e7d9 b.n 8014214 <__cvt+0x7c> 08014260 <__exponent>: 8014260: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8014262: 2900 cmp r1, #0 8014264: bfb6 itet lt 8014266: 232d movlt r3, #45 @ 0x2d 8014268: 232b movge r3, #43 @ 0x2b 801426a: 4249 neglt r1, r1 801426c: 2909 cmp r1, #9 801426e: 7002 strb r2, [r0, #0] 8014270: 7043 strb r3, [r0, #1] 8014272: dd29 ble.n 80142c8 <__exponent+0x68> 8014274: f10d 0307 add.w r3, sp, #7 8014278: 461d mov r5, r3 801427a: 270a movs r7, #10 801427c: fbb1 f6f7 udiv r6, r1, r7 8014280: 461a mov r2, r3 8014282: fb07 1416 mls r4, r7, r6, r1 8014286: 3430 adds r4, #48 @ 0x30 8014288: f802 4c01 strb.w r4, [r2, #-1] 801428c: 460c mov r4, r1 801428e: 2c63 cmp r4, #99 @ 0x63 8014290: 4631 mov r1, r6 8014292: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff 8014296: dcf1 bgt.n 801427c <__exponent+0x1c> 8014298: 3130 adds r1, #48 @ 0x30 801429a: 1e94 subs r4, r2, #2 801429c: f803 1c01 strb.w r1, [r3, #-1] 80142a0: 4623 mov r3, r4 80142a2: 1c41 adds r1, r0, #1 80142a4: 42ab cmp r3, r5 80142a6: d30a bcc.n 80142be <__exponent+0x5e> 80142a8: f10d 0309 add.w r3, sp, #9 80142ac: 1a9b subs r3, r3, r2 80142ae: 42ac cmp r4, r5 80142b0: bf88 it hi 80142b2: 2300 movhi r3, #0 80142b4: 3302 adds r3, #2 80142b6: 4403 add r3, r0 80142b8: 1a18 subs r0, r3, r0 80142ba: b003 add sp, #12 80142bc: bdf0 pop {r4, r5, r6, r7, pc} 80142be: f813 6b01 ldrb.w r6, [r3], #1 80142c2: f801 6f01 strb.w r6, [r1, #1]! 80142c6: e7ed b.n 80142a4 <__exponent+0x44> 80142c8: 2330 movs r3, #48 @ 0x30 80142ca: 3130 adds r1, #48 @ 0x30 80142cc: 7083 strb r3, [r0, #2] 80142ce: 70c1 strb r1, [r0, #3] 80142d0: 1d03 adds r3, r0, #4 80142d2: e7f1 b.n 80142b8 <__exponent+0x58> 080142d4 <_printf_float>: 80142d4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80142d8: b091 sub sp, #68 @ 0x44 80142da: 460c mov r4, r1 80142dc: f8dd 8068 ldr.w r8, [sp, #104] @ 0x68 80142e0: 4616 mov r6, r2 80142e2: 461f mov r7, r3 80142e4: 4605 mov r5, r0 80142e6: f000 fce5 bl 8014cb4 <_localeconv_r> 80142ea: 6803 ldr r3, [r0, #0] 80142ec: 4618 mov r0, r3 80142ee: 9308 str r3, [sp, #32] 80142f0: f7f3 ff9a bl 8008228 80142f4: 2300 movs r3, #0 80142f6: 930e str r3, [sp, #56] @ 0x38 80142f8: f8d8 3000 ldr.w r3, [r8] 80142fc: 9009 str r0, [sp, #36] @ 0x24 80142fe: 3307 adds r3, #7 8014300: f023 0307 bic.w r3, r3, #7 8014304: f103 0208 add.w r2, r3, #8 8014308: f894 a018 ldrb.w sl, [r4, #24] 801430c: f8d4 b000 ldr.w fp, [r4] 8014310: f8c8 2000 str.w r2, [r8] 8014314: e9d3 8900 ldrd r8, r9, [r3] 8014318: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000 801431c: 930b str r3, [sp, #44] @ 0x2c 801431e: f8cd 8028 str.w r8, [sp, #40] @ 0x28 8014322: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8014326: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 801432a: e9c4 8912 strd r8, r9, [r4, #72] @ 0x48 801432e: 4b9c ldr r3, [pc, #624] @ (80145a0 <_printf_float+0x2cc>) 8014330: f7f4 fbd8 bl 8008ae4 <__aeabi_dcmpun> 8014334: bb70 cbnz r0, 8014394 <_printf_float+0xc0> 8014336: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 801433a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801433e: 4b98 ldr r3, [pc, #608] @ (80145a0 <_printf_float+0x2cc>) 8014340: f7f4 fbb2 bl 8008aa8 <__aeabi_dcmple> 8014344: bb30 cbnz r0, 8014394 <_printf_float+0xc0> 8014346: 2200 movs r2, #0 8014348: 2300 movs r3, #0 801434a: 4640 mov r0, r8 801434c: 4649 mov r1, r9 801434e: f7f4 fba1 bl 8008a94 <__aeabi_dcmplt> 8014352: b110 cbz r0, 801435a <_printf_float+0x86> 8014354: 232d movs r3, #45 @ 0x2d 8014356: f884 3043 strb.w r3, [r4, #67] @ 0x43 801435a: 4a92 ldr r2, [pc, #584] @ (80145a4 <_printf_float+0x2d0>) 801435c: 4b92 ldr r3, [pc, #584] @ (80145a8 <_printf_float+0x2d4>) 801435e: f1ba 0f47 cmp.w sl, #71 @ 0x47 8014362: bf8c ite hi 8014364: 4690 movhi r8, r2 8014366: 4698 movls r8, r3 8014368: 2303 movs r3, #3 801436a: f04f 0900 mov.w r9, #0 801436e: 6123 str r3, [r4, #16] 8014370: f02b 0304 bic.w r3, fp, #4 8014374: 6023 str r3, [r4, #0] 8014376: 4633 mov r3, r6 8014378: 4621 mov r1, r4 801437a: 4628 mov r0, r5 801437c: 9700 str r7, [sp, #0] 801437e: aa0f add r2, sp, #60 @ 0x3c 8014380: f000 f9d4 bl 801472c <_printf_common> 8014384: 3001 adds r0, #1 8014386: f040 8090 bne.w 80144aa <_printf_float+0x1d6> 801438a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801438e: b011 add sp, #68 @ 0x44 8014390: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8014394: 4642 mov r2, r8 8014396: 464b mov r3, r9 8014398: 4640 mov r0, r8 801439a: 4649 mov r1, r9 801439c: f7f4 fba2 bl 8008ae4 <__aeabi_dcmpun> 80143a0: b148 cbz r0, 80143b6 <_printf_float+0xe2> 80143a2: 464b mov r3, r9 80143a4: 2b00 cmp r3, #0 80143a6: bfb8 it lt 80143a8: 232d movlt r3, #45 @ 0x2d 80143aa: 4a80 ldr r2, [pc, #512] @ (80145ac <_printf_float+0x2d8>) 80143ac: bfb8 it lt 80143ae: f884 3043 strblt.w r3, [r4, #67] @ 0x43 80143b2: 4b7f ldr r3, [pc, #508] @ (80145b0 <_printf_float+0x2dc>) 80143b4: e7d3 b.n 801435e <_printf_float+0x8a> 80143b6: 6863 ldr r3, [r4, #4] 80143b8: f00a 01df and.w r1, sl, #223 @ 0xdf 80143bc: 1c5a adds r2, r3, #1 80143be: d13f bne.n 8014440 <_printf_float+0x16c> 80143c0: 2306 movs r3, #6 80143c2: 6063 str r3, [r4, #4] 80143c4: 2200 movs r2, #0 80143c6: f44b 6380 orr.w r3, fp, #1024 @ 0x400 80143ca: 6023 str r3, [r4, #0] 80143cc: 9206 str r2, [sp, #24] 80143ce: aa0e add r2, sp, #56 @ 0x38 80143d0: e9cd a204 strd sl, r2, [sp, #16] 80143d4: aa0d add r2, sp, #52 @ 0x34 80143d6: 9203 str r2, [sp, #12] 80143d8: f10d 0233 add.w r2, sp, #51 @ 0x33 80143dc: e9cd 3201 strd r3, r2, [sp, #4] 80143e0: 6863 ldr r3, [r4, #4] 80143e2: 4642 mov r2, r8 80143e4: 9300 str r3, [sp, #0] 80143e6: 4628 mov r0, r5 80143e8: 464b mov r3, r9 80143ea: 910a str r1, [sp, #40] @ 0x28 80143ec: f7ff fed4 bl 8014198 <__cvt> 80143f0: 990a ldr r1, [sp, #40] @ 0x28 80143f2: 4680 mov r8, r0 80143f4: 2947 cmp r1, #71 @ 0x47 80143f6: 990d ldr r1, [sp, #52] @ 0x34 80143f8: d128 bne.n 801444c <_printf_float+0x178> 80143fa: 1cc8 adds r0, r1, #3 80143fc: db02 blt.n 8014404 <_printf_float+0x130> 80143fe: 6863 ldr r3, [r4, #4] 8014400: 4299 cmp r1, r3 8014402: dd40 ble.n 8014486 <_printf_float+0x1b2> 8014404: f1aa 0a02 sub.w sl, sl, #2 8014408: fa5f fa8a uxtb.w sl, sl 801440c: 4652 mov r2, sl 801440e: 3901 subs r1, #1 8014410: f104 0050 add.w r0, r4, #80 @ 0x50 8014414: 910d str r1, [sp, #52] @ 0x34 8014416: f7ff ff23 bl 8014260 <__exponent> 801441a: 9a0e ldr r2, [sp, #56] @ 0x38 801441c: 4681 mov r9, r0 801441e: 1813 adds r3, r2, r0 8014420: 2a01 cmp r2, #1 8014422: 6123 str r3, [r4, #16] 8014424: dc02 bgt.n 801442c <_printf_float+0x158> 8014426: 6822 ldr r2, [r4, #0] 8014428: 07d2 lsls r2, r2, #31 801442a: d501 bpl.n 8014430 <_printf_float+0x15c> 801442c: 3301 adds r3, #1 801442e: 6123 str r3, [r4, #16] 8014430: f89d 3033 ldrb.w r3, [sp, #51] @ 0x33 8014434: 2b00 cmp r3, #0 8014436: d09e beq.n 8014376 <_printf_float+0xa2> 8014438: 232d movs r3, #45 @ 0x2d 801443a: f884 3043 strb.w r3, [r4, #67] @ 0x43 801443e: e79a b.n 8014376 <_printf_float+0xa2> 8014440: 2947 cmp r1, #71 @ 0x47 8014442: d1bf bne.n 80143c4 <_printf_float+0xf0> 8014444: 2b00 cmp r3, #0 8014446: d1bd bne.n 80143c4 <_printf_float+0xf0> 8014448: 2301 movs r3, #1 801444a: e7ba b.n 80143c2 <_printf_float+0xee> 801444c: f1ba 0f65 cmp.w sl, #101 @ 0x65 8014450: d9dc bls.n 801440c <_printf_float+0x138> 8014452: f1ba 0f66 cmp.w sl, #102 @ 0x66 8014456: d118 bne.n 801448a <_printf_float+0x1b6> 8014458: 2900 cmp r1, #0 801445a: 6863 ldr r3, [r4, #4] 801445c: dd0b ble.n 8014476 <_printf_float+0x1a2> 801445e: 6121 str r1, [r4, #16] 8014460: b913 cbnz r3, 8014468 <_printf_float+0x194> 8014462: 6822 ldr r2, [r4, #0] 8014464: 07d0 lsls r0, r2, #31 8014466: d502 bpl.n 801446e <_printf_float+0x19a> 8014468: 3301 adds r3, #1 801446a: 440b add r3, r1 801446c: 6123 str r3, [r4, #16] 801446e: f04f 0900 mov.w r9, #0 8014472: 65a1 str r1, [r4, #88] @ 0x58 8014474: e7dc b.n 8014430 <_printf_float+0x15c> 8014476: b913 cbnz r3, 801447e <_printf_float+0x1aa> 8014478: 6822 ldr r2, [r4, #0] 801447a: 07d2 lsls r2, r2, #31 801447c: d501 bpl.n 8014482 <_printf_float+0x1ae> 801447e: 3302 adds r3, #2 8014480: e7f4 b.n 801446c <_printf_float+0x198> 8014482: 2301 movs r3, #1 8014484: e7f2 b.n 801446c <_printf_float+0x198> 8014486: f04f 0a67 mov.w sl, #103 @ 0x67 801448a: 9b0e ldr r3, [sp, #56] @ 0x38 801448c: 4299 cmp r1, r3 801448e: db05 blt.n 801449c <_printf_float+0x1c8> 8014490: 6823 ldr r3, [r4, #0] 8014492: 6121 str r1, [r4, #16] 8014494: 07d8 lsls r0, r3, #31 8014496: d5ea bpl.n 801446e <_printf_float+0x19a> 8014498: 1c4b adds r3, r1, #1 801449a: e7e7 b.n 801446c <_printf_float+0x198> 801449c: 2900 cmp r1, #0 801449e: bfcc ite gt 80144a0: 2201 movgt r2, #1 80144a2: f1c1 0202 rsble r2, r1, #2 80144a6: 4413 add r3, r2 80144a8: e7e0 b.n 801446c <_printf_float+0x198> 80144aa: 6823 ldr r3, [r4, #0] 80144ac: 055a lsls r2, r3, #21 80144ae: d407 bmi.n 80144c0 <_printf_float+0x1ec> 80144b0: 6923 ldr r3, [r4, #16] 80144b2: 4642 mov r2, r8 80144b4: 4631 mov r1, r6 80144b6: 4628 mov r0, r5 80144b8: 47b8 blx r7 80144ba: 3001 adds r0, #1 80144bc: d12b bne.n 8014516 <_printf_float+0x242> 80144be: e764 b.n 801438a <_printf_float+0xb6> 80144c0: f1ba 0f65 cmp.w sl, #101 @ 0x65 80144c4: f240 80dc bls.w 8014680 <_printf_float+0x3ac> 80144c8: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 80144cc: 2200 movs r2, #0 80144ce: 2300 movs r3, #0 80144d0: f7f4 fad6 bl 8008a80 <__aeabi_dcmpeq> 80144d4: 2800 cmp r0, #0 80144d6: d033 beq.n 8014540 <_printf_float+0x26c> 80144d8: 2301 movs r3, #1 80144da: 4631 mov r1, r6 80144dc: 4628 mov r0, r5 80144de: 4a35 ldr r2, [pc, #212] @ (80145b4 <_printf_float+0x2e0>) 80144e0: 47b8 blx r7 80144e2: 3001 adds r0, #1 80144e4: f43f af51 beq.w 801438a <_printf_float+0xb6> 80144e8: e9dd 380d ldrd r3, r8, [sp, #52] @ 0x34 80144ec: 4543 cmp r3, r8 80144ee: db02 blt.n 80144f6 <_printf_float+0x222> 80144f0: 6823 ldr r3, [r4, #0] 80144f2: 07d8 lsls r0, r3, #31 80144f4: d50f bpl.n 8014516 <_printf_float+0x242> 80144f6: e9dd 2308 ldrd r2, r3, [sp, #32] 80144fa: 4631 mov r1, r6 80144fc: 4628 mov r0, r5 80144fe: 47b8 blx r7 8014500: 3001 adds r0, #1 8014502: f43f af42 beq.w 801438a <_printf_float+0xb6> 8014506: f04f 0900 mov.w r9, #0 801450a: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 801450e: f104 0a1a add.w sl, r4, #26 8014512: 45c8 cmp r8, r9 8014514: dc09 bgt.n 801452a <_printf_float+0x256> 8014516: 6823 ldr r3, [r4, #0] 8014518: 079b lsls r3, r3, #30 801451a: f100 8102 bmi.w 8014722 <_printf_float+0x44e> 801451e: 68e0 ldr r0, [r4, #12] 8014520: 9b0f ldr r3, [sp, #60] @ 0x3c 8014522: 4298 cmp r0, r3 8014524: bfb8 it lt 8014526: 4618 movlt r0, r3 8014528: e731 b.n 801438e <_printf_float+0xba> 801452a: 2301 movs r3, #1 801452c: 4652 mov r2, sl 801452e: 4631 mov r1, r6 8014530: 4628 mov r0, r5 8014532: 47b8 blx r7 8014534: 3001 adds r0, #1 8014536: f43f af28 beq.w 801438a <_printf_float+0xb6> 801453a: f109 0901 add.w r9, r9, #1 801453e: e7e8 b.n 8014512 <_printf_float+0x23e> 8014540: 9b0d ldr r3, [sp, #52] @ 0x34 8014542: 2b00 cmp r3, #0 8014544: dc38 bgt.n 80145b8 <_printf_float+0x2e4> 8014546: 2301 movs r3, #1 8014548: 4631 mov r1, r6 801454a: 4628 mov r0, r5 801454c: 4a19 ldr r2, [pc, #100] @ (80145b4 <_printf_float+0x2e0>) 801454e: 47b8 blx r7 8014550: 3001 adds r0, #1 8014552: f43f af1a beq.w 801438a <_printf_float+0xb6> 8014556: e9dd 390d ldrd r3, r9, [sp, #52] @ 0x34 801455a: ea59 0303 orrs.w r3, r9, r3 801455e: d102 bne.n 8014566 <_printf_float+0x292> 8014560: 6823 ldr r3, [r4, #0] 8014562: 07d9 lsls r1, r3, #31 8014564: d5d7 bpl.n 8014516 <_printf_float+0x242> 8014566: e9dd 2308 ldrd r2, r3, [sp, #32] 801456a: 4631 mov r1, r6 801456c: 4628 mov r0, r5 801456e: 47b8 blx r7 8014570: 3001 adds r0, #1 8014572: f43f af0a beq.w 801438a <_printf_float+0xb6> 8014576: f04f 0a00 mov.w sl, #0 801457a: f104 0b1a add.w fp, r4, #26 801457e: 9b0d ldr r3, [sp, #52] @ 0x34 8014580: 425b negs r3, r3 8014582: 4553 cmp r3, sl 8014584: dc01 bgt.n 801458a <_printf_float+0x2b6> 8014586: 464b mov r3, r9 8014588: e793 b.n 80144b2 <_printf_float+0x1de> 801458a: 2301 movs r3, #1 801458c: 465a mov r2, fp 801458e: 4631 mov r1, r6 8014590: 4628 mov r0, r5 8014592: 47b8 blx r7 8014594: 3001 adds r0, #1 8014596: f43f aef8 beq.w 801438a <_printf_float+0xb6> 801459a: f10a 0a01 add.w sl, sl, #1 801459e: e7ee b.n 801457e <_printf_float+0x2aa> 80145a0: 7fefffff .word 0x7fefffff 80145a4: 080178f0 .word 0x080178f0 80145a8: 080178ec .word 0x080178ec 80145ac: 080178f8 .word 0x080178f8 80145b0: 080178f4 .word 0x080178f4 80145b4: 080178fc .word 0x080178fc 80145b8: 6da3 ldr r3, [r4, #88] @ 0x58 80145ba: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 80145be: 4553 cmp r3, sl 80145c0: bfa8 it ge 80145c2: 4653 movge r3, sl 80145c4: 2b00 cmp r3, #0 80145c6: 4699 mov r9, r3 80145c8: dc36 bgt.n 8014638 <_printf_float+0x364> 80145ca: f04f 0b00 mov.w fp, #0 80145ce: ea29 79e9 bic.w r9, r9, r9, asr #31 80145d2: f104 021a add.w r2, r4, #26 80145d6: 6da3 ldr r3, [r4, #88] @ 0x58 80145d8: 930a str r3, [sp, #40] @ 0x28 80145da: eba3 0309 sub.w r3, r3, r9 80145de: 455b cmp r3, fp 80145e0: dc31 bgt.n 8014646 <_printf_float+0x372> 80145e2: 9b0d ldr r3, [sp, #52] @ 0x34 80145e4: 459a cmp sl, r3 80145e6: dc3a bgt.n 801465e <_printf_float+0x38a> 80145e8: 6823 ldr r3, [r4, #0] 80145ea: 07da lsls r2, r3, #31 80145ec: d437 bmi.n 801465e <_printf_float+0x38a> 80145ee: 9b0d ldr r3, [sp, #52] @ 0x34 80145f0: ebaa 0903 sub.w r9, sl, r3 80145f4: 9b0a ldr r3, [sp, #40] @ 0x28 80145f6: ebaa 0303 sub.w r3, sl, r3 80145fa: 4599 cmp r9, r3 80145fc: bfa8 it ge 80145fe: 4699 movge r9, r3 8014600: f1b9 0f00 cmp.w r9, #0 8014604: dc33 bgt.n 801466e <_printf_float+0x39a> 8014606: f04f 0800 mov.w r8, #0 801460a: ea29 79e9 bic.w r9, r9, r9, asr #31 801460e: f104 0b1a add.w fp, r4, #26 8014612: 9b0d ldr r3, [sp, #52] @ 0x34 8014614: ebaa 0303 sub.w r3, sl, r3 8014618: eba3 0309 sub.w r3, r3, r9 801461c: 4543 cmp r3, r8 801461e: f77f af7a ble.w 8014516 <_printf_float+0x242> 8014622: 2301 movs r3, #1 8014624: 465a mov r2, fp 8014626: 4631 mov r1, r6 8014628: 4628 mov r0, r5 801462a: 47b8 blx r7 801462c: 3001 adds r0, #1 801462e: f43f aeac beq.w 801438a <_printf_float+0xb6> 8014632: f108 0801 add.w r8, r8, #1 8014636: e7ec b.n 8014612 <_printf_float+0x33e> 8014638: 4642 mov r2, r8 801463a: 4631 mov r1, r6 801463c: 4628 mov r0, r5 801463e: 47b8 blx r7 8014640: 3001 adds r0, #1 8014642: d1c2 bne.n 80145ca <_printf_float+0x2f6> 8014644: e6a1 b.n 801438a <_printf_float+0xb6> 8014646: 2301 movs r3, #1 8014648: 4631 mov r1, r6 801464a: 4628 mov r0, r5 801464c: 920a str r2, [sp, #40] @ 0x28 801464e: 47b8 blx r7 8014650: 3001 adds r0, #1 8014652: f43f ae9a beq.w 801438a <_printf_float+0xb6> 8014656: 9a0a ldr r2, [sp, #40] @ 0x28 8014658: f10b 0b01 add.w fp, fp, #1 801465c: e7bb b.n 80145d6 <_printf_float+0x302> 801465e: 4631 mov r1, r6 8014660: e9dd 2308 ldrd r2, r3, [sp, #32] 8014664: 4628 mov r0, r5 8014666: 47b8 blx r7 8014668: 3001 adds r0, #1 801466a: d1c0 bne.n 80145ee <_printf_float+0x31a> 801466c: e68d b.n 801438a <_printf_float+0xb6> 801466e: 9a0a ldr r2, [sp, #40] @ 0x28 8014670: 464b mov r3, r9 8014672: 4631 mov r1, r6 8014674: 4628 mov r0, r5 8014676: 4442 add r2, r8 8014678: 47b8 blx r7 801467a: 3001 adds r0, #1 801467c: d1c3 bne.n 8014606 <_printf_float+0x332> 801467e: e684 b.n 801438a <_printf_float+0xb6> 8014680: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 8014684: f1ba 0f01 cmp.w sl, #1 8014688: dc01 bgt.n 801468e <_printf_float+0x3ba> 801468a: 07db lsls r3, r3, #31 801468c: d536 bpl.n 80146fc <_printf_float+0x428> 801468e: 2301 movs r3, #1 8014690: 4642 mov r2, r8 8014692: 4631 mov r1, r6 8014694: 4628 mov r0, r5 8014696: 47b8 blx r7 8014698: 3001 adds r0, #1 801469a: f43f ae76 beq.w 801438a <_printf_float+0xb6> 801469e: e9dd 2308 ldrd r2, r3, [sp, #32] 80146a2: 4631 mov r1, r6 80146a4: 4628 mov r0, r5 80146a6: 47b8 blx r7 80146a8: 3001 adds r0, #1 80146aa: f43f ae6e beq.w 801438a <_printf_float+0xb6> 80146ae: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 80146b2: 2200 movs r2, #0 80146b4: 2300 movs r3, #0 80146b6: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff 80146ba: f7f4 f9e1 bl 8008a80 <__aeabi_dcmpeq> 80146be: b9c0 cbnz r0, 80146f2 <_printf_float+0x41e> 80146c0: 4653 mov r3, sl 80146c2: f108 0201 add.w r2, r8, #1 80146c6: 4631 mov r1, r6 80146c8: 4628 mov r0, r5 80146ca: 47b8 blx r7 80146cc: 3001 adds r0, #1 80146ce: d10c bne.n 80146ea <_printf_float+0x416> 80146d0: e65b b.n 801438a <_printf_float+0xb6> 80146d2: 2301 movs r3, #1 80146d4: 465a mov r2, fp 80146d6: 4631 mov r1, r6 80146d8: 4628 mov r0, r5 80146da: 47b8 blx r7 80146dc: 3001 adds r0, #1 80146de: f43f ae54 beq.w 801438a <_printf_float+0xb6> 80146e2: f108 0801 add.w r8, r8, #1 80146e6: 45d0 cmp r8, sl 80146e8: dbf3 blt.n 80146d2 <_printf_float+0x3fe> 80146ea: 464b mov r3, r9 80146ec: f104 0250 add.w r2, r4, #80 @ 0x50 80146f0: e6e0 b.n 80144b4 <_printf_float+0x1e0> 80146f2: f04f 0800 mov.w r8, #0 80146f6: f104 0b1a add.w fp, r4, #26 80146fa: e7f4 b.n 80146e6 <_printf_float+0x412> 80146fc: 2301 movs r3, #1 80146fe: 4642 mov r2, r8 8014700: e7e1 b.n 80146c6 <_printf_float+0x3f2> 8014702: 2301 movs r3, #1 8014704: 464a mov r2, r9 8014706: 4631 mov r1, r6 8014708: 4628 mov r0, r5 801470a: 47b8 blx r7 801470c: 3001 adds r0, #1 801470e: f43f ae3c beq.w 801438a <_printf_float+0xb6> 8014712: f108 0801 add.w r8, r8, #1 8014716: 68e3 ldr r3, [r4, #12] 8014718: 990f ldr r1, [sp, #60] @ 0x3c 801471a: 1a5b subs r3, r3, r1 801471c: 4543 cmp r3, r8 801471e: dcf0 bgt.n 8014702 <_printf_float+0x42e> 8014720: e6fd b.n 801451e <_printf_float+0x24a> 8014722: f04f 0800 mov.w r8, #0 8014726: f104 0919 add.w r9, r4, #25 801472a: e7f4 b.n 8014716 <_printf_float+0x442> 0801472c <_printf_common>: 801472c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8014730: 4616 mov r6, r2 8014732: 4698 mov r8, r3 8014734: 688a ldr r2, [r1, #8] 8014736: 690b ldr r3, [r1, #16] 8014738: 4607 mov r7, r0 801473a: 4293 cmp r3, r2 801473c: bfb8 it lt 801473e: 4613 movlt r3, r2 8014740: 6033 str r3, [r6, #0] 8014742: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 8014746: 460c mov r4, r1 8014748: f8dd 9020 ldr.w r9, [sp, #32] 801474c: b10a cbz r2, 8014752 <_printf_common+0x26> 801474e: 3301 adds r3, #1 8014750: 6033 str r3, [r6, #0] 8014752: 6823 ldr r3, [r4, #0] 8014754: 0699 lsls r1, r3, #26 8014756: bf42 ittt mi 8014758: 6833 ldrmi r3, [r6, #0] 801475a: 3302 addmi r3, #2 801475c: 6033 strmi r3, [r6, #0] 801475e: 6825 ldr r5, [r4, #0] 8014760: f015 0506 ands.w r5, r5, #6 8014764: d106 bne.n 8014774 <_printf_common+0x48> 8014766: f104 0a19 add.w sl, r4, #25 801476a: 68e3 ldr r3, [r4, #12] 801476c: 6832 ldr r2, [r6, #0] 801476e: 1a9b subs r3, r3, r2 8014770: 42ab cmp r3, r5 8014772: dc2b bgt.n 80147cc <_printf_common+0xa0> 8014774: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 8014778: 6822 ldr r2, [r4, #0] 801477a: 3b00 subs r3, #0 801477c: bf18 it ne 801477e: 2301 movne r3, #1 8014780: 0692 lsls r2, r2, #26 8014782: d430 bmi.n 80147e6 <_printf_common+0xba> 8014784: 4641 mov r1, r8 8014786: 4638 mov r0, r7 8014788: f104 0243 add.w r2, r4, #67 @ 0x43 801478c: 47c8 blx r9 801478e: 3001 adds r0, #1 8014790: d023 beq.n 80147da <_printf_common+0xae> 8014792: 6823 ldr r3, [r4, #0] 8014794: 6922 ldr r2, [r4, #16] 8014796: f003 0306 and.w r3, r3, #6 801479a: 2b04 cmp r3, #4 801479c: bf14 ite ne 801479e: 2500 movne r5, #0 80147a0: 6833 ldreq r3, [r6, #0] 80147a2: f04f 0600 mov.w r6, #0 80147a6: bf08 it eq 80147a8: 68e5 ldreq r5, [r4, #12] 80147aa: f104 041a add.w r4, r4, #26 80147ae: bf08 it eq 80147b0: 1aed subeq r5, r5, r3 80147b2: f854 3c12 ldr.w r3, [r4, #-18] 80147b6: bf08 it eq 80147b8: ea25 75e5 biceq.w r5, r5, r5, asr #31 80147bc: 4293 cmp r3, r2 80147be: bfc4 itt gt 80147c0: 1a9b subgt r3, r3, r2 80147c2: 18ed addgt r5, r5, r3 80147c4: 42b5 cmp r5, r6 80147c6: d11a bne.n 80147fe <_printf_common+0xd2> 80147c8: 2000 movs r0, #0 80147ca: e008 b.n 80147de <_printf_common+0xb2> 80147cc: 2301 movs r3, #1 80147ce: 4652 mov r2, sl 80147d0: 4641 mov r1, r8 80147d2: 4638 mov r0, r7 80147d4: 47c8 blx r9 80147d6: 3001 adds r0, #1 80147d8: d103 bne.n 80147e2 <_printf_common+0xb6> 80147da: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80147de: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80147e2: 3501 adds r5, #1 80147e4: e7c1 b.n 801476a <_printf_common+0x3e> 80147e6: 2030 movs r0, #48 @ 0x30 80147e8: 18e1 adds r1, r4, r3 80147ea: f881 0043 strb.w r0, [r1, #67] @ 0x43 80147ee: 1c5a adds r2, r3, #1 80147f0: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 80147f4: 4422 add r2, r4 80147f6: 3302 adds r3, #2 80147f8: f882 1043 strb.w r1, [r2, #67] @ 0x43 80147fc: e7c2 b.n 8014784 <_printf_common+0x58> 80147fe: 2301 movs r3, #1 8014800: 4622 mov r2, r4 8014802: 4641 mov r1, r8 8014804: 4638 mov r0, r7 8014806: 47c8 blx r9 8014808: 3001 adds r0, #1 801480a: d0e6 beq.n 80147da <_printf_common+0xae> 801480c: 3601 adds r6, #1 801480e: e7d9 b.n 80147c4 <_printf_common+0x98> 08014810 <_printf_i>: 8014810: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8014814: 7e0f ldrb r7, [r1, #24] 8014816: 4691 mov r9, r2 8014818: 2f78 cmp r7, #120 @ 0x78 801481a: 4680 mov r8, r0 801481c: 460c mov r4, r1 801481e: 469a mov sl, r3 8014820: 9e0c ldr r6, [sp, #48] @ 0x30 8014822: f101 0243 add.w r2, r1, #67 @ 0x43 8014826: d807 bhi.n 8014838 <_printf_i+0x28> 8014828: 2f62 cmp r7, #98 @ 0x62 801482a: d80a bhi.n 8014842 <_printf_i+0x32> 801482c: 2f00 cmp r7, #0 801482e: f000 80d1 beq.w 80149d4 <_printf_i+0x1c4> 8014832: 2f58 cmp r7, #88 @ 0x58 8014834: f000 80b8 beq.w 80149a8 <_printf_i+0x198> 8014838: f104 0642 add.w r6, r4, #66 @ 0x42 801483c: f884 7042 strb.w r7, [r4, #66] @ 0x42 8014840: e03a b.n 80148b8 <_printf_i+0xa8> 8014842: f1a7 0363 sub.w r3, r7, #99 @ 0x63 8014846: 2b15 cmp r3, #21 8014848: d8f6 bhi.n 8014838 <_printf_i+0x28> 801484a: a101 add r1, pc, #4 @ (adr r1, 8014850 <_printf_i+0x40>) 801484c: f851 f023 ldr.w pc, [r1, r3, lsl #2] 8014850: 080148a9 .word 0x080148a9 8014854: 080148bd .word 0x080148bd 8014858: 08014839 .word 0x08014839 801485c: 08014839 .word 0x08014839 8014860: 08014839 .word 0x08014839 8014864: 08014839 .word 0x08014839 8014868: 080148bd .word 0x080148bd 801486c: 08014839 .word 0x08014839 8014870: 08014839 .word 0x08014839 8014874: 08014839 .word 0x08014839 8014878: 08014839 .word 0x08014839 801487c: 080149bb .word 0x080149bb 8014880: 080148e7 .word 0x080148e7 8014884: 08014975 .word 0x08014975 8014888: 08014839 .word 0x08014839 801488c: 08014839 .word 0x08014839 8014890: 080149dd .word 0x080149dd 8014894: 08014839 .word 0x08014839 8014898: 080148e7 .word 0x080148e7 801489c: 08014839 .word 0x08014839 80148a0: 08014839 .word 0x08014839 80148a4: 0801497d .word 0x0801497d 80148a8: 6833 ldr r3, [r6, #0] 80148aa: 1d1a adds r2, r3, #4 80148ac: 681b ldr r3, [r3, #0] 80148ae: 6032 str r2, [r6, #0] 80148b0: f104 0642 add.w r6, r4, #66 @ 0x42 80148b4: f884 3042 strb.w r3, [r4, #66] @ 0x42 80148b8: 2301 movs r3, #1 80148ba: e09c b.n 80149f6 <_printf_i+0x1e6> 80148bc: 6833 ldr r3, [r6, #0] 80148be: 6820 ldr r0, [r4, #0] 80148c0: 1d19 adds r1, r3, #4 80148c2: 6031 str r1, [r6, #0] 80148c4: 0606 lsls r6, r0, #24 80148c6: d501 bpl.n 80148cc <_printf_i+0xbc> 80148c8: 681d ldr r5, [r3, #0] 80148ca: e003 b.n 80148d4 <_printf_i+0xc4> 80148cc: 0645 lsls r5, r0, #25 80148ce: d5fb bpl.n 80148c8 <_printf_i+0xb8> 80148d0: f9b3 5000 ldrsh.w r5, [r3] 80148d4: 2d00 cmp r5, #0 80148d6: da03 bge.n 80148e0 <_printf_i+0xd0> 80148d8: 232d movs r3, #45 @ 0x2d 80148da: 426d negs r5, r5 80148dc: f884 3043 strb.w r3, [r4, #67] @ 0x43 80148e0: 230a movs r3, #10 80148e2: 4858 ldr r0, [pc, #352] @ (8014a44 <_printf_i+0x234>) 80148e4: e011 b.n 801490a <_printf_i+0xfa> 80148e6: 6821 ldr r1, [r4, #0] 80148e8: 6833 ldr r3, [r6, #0] 80148ea: 0608 lsls r0, r1, #24 80148ec: f853 5b04 ldr.w r5, [r3], #4 80148f0: d402 bmi.n 80148f8 <_printf_i+0xe8> 80148f2: 0649 lsls r1, r1, #25 80148f4: bf48 it mi 80148f6: b2ad uxthmi r5, r5 80148f8: 2f6f cmp r7, #111 @ 0x6f 80148fa: 6033 str r3, [r6, #0] 80148fc: bf14 ite ne 80148fe: 230a movne r3, #10 8014900: 2308 moveq r3, #8 8014902: 4850 ldr r0, [pc, #320] @ (8014a44 <_printf_i+0x234>) 8014904: 2100 movs r1, #0 8014906: f884 1043 strb.w r1, [r4, #67] @ 0x43 801490a: 6866 ldr r6, [r4, #4] 801490c: 2e00 cmp r6, #0 801490e: 60a6 str r6, [r4, #8] 8014910: db05 blt.n 801491e <_printf_i+0x10e> 8014912: 6821 ldr r1, [r4, #0] 8014914: 432e orrs r6, r5 8014916: f021 0104 bic.w r1, r1, #4 801491a: 6021 str r1, [r4, #0] 801491c: d04b beq.n 80149b6 <_printf_i+0x1a6> 801491e: 4616 mov r6, r2 8014920: fbb5 f1f3 udiv r1, r5, r3 8014924: fb03 5711 mls r7, r3, r1, r5 8014928: 5dc7 ldrb r7, [r0, r7] 801492a: f806 7d01 strb.w r7, [r6, #-1]! 801492e: 462f mov r7, r5 8014930: 42bb cmp r3, r7 8014932: 460d mov r5, r1 8014934: d9f4 bls.n 8014920 <_printf_i+0x110> 8014936: 2b08 cmp r3, #8 8014938: d10b bne.n 8014952 <_printf_i+0x142> 801493a: 6823 ldr r3, [r4, #0] 801493c: 07df lsls r7, r3, #31 801493e: d508 bpl.n 8014952 <_printf_i+0x142> 8014940: 6923 ldr r3, [r4, #16] 8014942: 6861 ldr r1, [r4, #4] 8014944: 4299 cmp r1, r3 8014946: bfde ittt le 8014948: 2330 movle r3, #48 @ 0x30 801494a: f806 3c01 strble.w r3, [r6, #-1] 801494e: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 8014952: 1b92 subs r2, r2, r6 8014954: 6122 str r2, [r4, #16] 8014956: 464b mov r3, r9 8014958: 4621 mov r1, r4 801495a: 4640 mov r0, r8 801495c: f8cd a000 str.w sl, [sp] 8014960: aa03 add r2, sp, #12 8014962: f7ff fee3 bl 801472c <_printf_common> 8014966: 3001 adds r0, #1 8014968: d14a bne.n 8014a00 <_printf_i+0x1f0> 801496a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801496e: b004 add sp, #16 8014970: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8014974: 6823 ldr r3, [r4, #0] 8014976: f043 0320 orr.w r3, r3, #32 801497a: 6023 str r3, [r4, #0] 801497c: 2778 movs r7, #120 @ 0x78 801497e: 4832 ldr r0, [pc, #200] @ (8014a48 <_printf_i+0x238>) 8014980: f884 7045 strb.w r7, [r4, #69] @ 0x45 8014984: 6823 ldr r3, [r4, #0] 8014986: 6831 ldr r1, [r6, #0] 8014988: 061f lsls r7, r3, #24 801498a: f851 5b04 ldr.w r5, [r1], #4 801498e: d402 bmi.n 8014996 <_printf_i+0x186> 8014990: 065f lsls r7, r3, #25 8014992: bf48 it mi 8014994: b2ad uxthmi r5, r5 8014996: 6031 str r1, [r6, #0] 8014998: 07d9 lsls r1, r3, #31 801499a: bf44 itt mi 801499c: f043 0320 orrmi.w r3, r3, #32 80149a0: 6023 strmi r3, [r4, #0] 80149a2: b11d cbz r5, 80149ac <_printf_i+0x19c> 80149a4: 2310 movs r3, #16 80149a6: e7ad b.n 8014904 <_printf_i+0xf4> 80149a8: 4826 ldr r0, [pc, #152] @ (8014a44 <_printf_i+0x234>) 80149aa: e7e9 b.n 8014980 <_printf_i+0x170> 80149ac: 6823 ldr r3, [r4, #0] 80149ae: f023 0320 bic.w r3, r3, #32 80149b2: 6023 str r3, [r4, #0] 80149b4: e7f6 b.n 80149a4 <_printf_i+0x194> 80149b6: 4616 mov r6, r2 80149b8: e7bd b.n 8014936 <_printf_i+0x126> 80149ba: 6833 ldr r3, [r6, #0] 80149bc: 6825 ldr r5, [r4, #0] 80149be: 1d18 adds r0, r3, #4 80149c0: 6961 ldr r1, [r4, #20] 80149c2: 6030 str r0, [r6, #0] 80149c4: 062e lsls r6, r5, #24 80149c6: 681b ldr r3, [r3, #0] 80149c8: d501 bpl.n 80149ce <_printf_i+0x1be> 80149ca: 6019 str r1, [r3, #0] 80149cc: e002 b.n 80149d4 <_printf_i+0x1c4> 80149ce: 0668 lsls r0, r5, #25 80149d0: d5fb bpl.n 80149ca <_printf_i+0x1ba> 80149d2: 8019 strh r1, [r3, #0] 80149d4: 2300 movs r3, #0 80149d6: 4616 mov r6, r2 80149d8: 6123 str r3, [r4, #16] 80149da: e7bc b.n 8014956 <_printf_i+0x146> 80149dc: 6833 ldr r3, [r6, #0] 80149de: 2100 movs r1, #0 80149e0: 1d1a adds r2, r3, #4 80149e2: 6032 str r2, [r6, #0] 80149e4: 681e ldr r6, [r3, #0] 80149e6: 6862 ldr r2, [r4, #4] 80149e8: 4630 mov r0, r6 80149ea: f000 f967 bl 8014cbc 80149ee: b108 cbz r0, 80149f4 <_printf_i+0x1e4> 80149f0: 1b80 subs r0, r0, r6 80149f2: 6060 str r0, [r4, #4] 80149f4: 6863 ldr r3, [r4, #4] 80149f6: 6123 str r3, [r4, #16] 80149f8: 2300 movs r3, #0 80149fa: f884 3043 strb.w r3, [r4, #67] @ 0x43 80149fe: e7aa b.n 8014956 <_printf_i+0x146> 8014a00: 4632 mov r2, r6 8014a02: 4649 mov r1, r9 8014a04: 4640 mov r0, r8 8014a06: 6923 ldr r3, [r4, #16] 8014a08: 47d0 blx sl 8014a0a: 3001 adds r0, #1 8014a0c: d0ad beq.n 801496a <_printf_i+0x15a> 8014a0e: 6823 ldr r3, [r4, #0] 8014a10: 079b lsls r3, r3, #30 8014a12: d413 bmi.n 8014a3c <_printf_i+0x22c> 8014a14: 68e0 ldr r0, [r4, #12] 8014a16: 9b03 ldr r3, [sp, #12] 8014a18: 4298 cmp r0, r3 8014a1a: bfb8 it lt 8014a1c: 4618 movlt r0, r3 8014a1e: e7a6 b.n 801496e <_printf_i+0x15e> 8014a20: 2301 movs r3, #1 8014a22: 4632 mov r2, r6 8014a24: 4649 mov r1, r9 8014a26: 4640 mov r0, r8 8014a28: 47d0 blx sl 8014a2a: 3001 adds r0, #1 8014a2c: d09d beq.n 801496a <_printf_i+0x15a> 8014a2e: 3501 adds r5, #1 8014a30: 68e3 ldr r3, [r4, #12] 8014a32: 9903 ldr r1, [sp, #12] 8014a34: 1a5b subs r3, r3, r1 8014a36: 42ab cmp r3, r5 8014a38: dcf2 bgt.n 8014a20 <_printf_i+0x210> 8014a3a: e7eb b.n 8014a14 <_printf_i+0x204> 8014a3c: 2500 movs r5, #0 8014a3e: f104 0619 add.w r6, r4, #25 8014a42: e7f5 b.n 8014a30 <_printf_i+0x220> 8014a44: 080178fe .word 0x080178fe 8014a48: 0801790f .word 0x0801790f 08014a4c : 8014a4c: 2300 movs r3, #0 8014a4e: b510 push {r4, lr} 8014a50: 4604 mov r4, r0 8014a52: e9c0 3300 strd r3, r3, [r0] 8014a56: e9c0 3304 strd r3, r3, [r0, #16] 8014a5a: 6083 str r3, [r0, #8] 8014a5c: 8181 strh r1, [r0, #12] 8014a5e: 6643 str r3, [r0, #100] @ 0x64 8014a60: 81c2 strh r2, [r0, #14] 8014a62: 6183 str r3, [r0, #24] 8014a64: 4619 mov r1, r3 8014a66: 2208 movs r2, #8 8014a68: 305c adds r0, #92 @ 0x5c 8014a6a: f000 f8ed bl 8014c48 8014a6e: 4b0d ldr r3, [pc, #52] @ (8014aa4 ) 8014a70: 6224 str r4, [r4, #32] 8014a72: 6263 str r3, [r4, #36] @ 0x24 8014a74: 4b0c ldr r3, [pc, #48] @ (8014aa8 ) 8014a76: 62a3 str r3, [r4, #40] @ 0x28 8014a78: 4b0c ldr r3, [pc, #48] @ (8014aac ) 8014a7a: 62e3 str r3, [r4, #44] @ 0x2c 8014a7c: 4b0c ldr r3, [pc, #48] @ (8014ab0 ) 8014a7e: 6323 str r3, [r4, #48] @ 0x30 8014a80: 4b0c ldr r3, [pc, #48] @ (8014ab4 ) 8014a82: 429c cmp r4, r3 8014a84: d006 beq.n 8014a94 8014a86: f103 0268 add.w r2, r3, #104 @ 0x68 8014a8a: 4294 cmp r4, r2 8014a8c: d002 beq.n 8014a94 8014a8e: 33d0 adds r3, #208 @ 0xd0 8014a90: 429c cmp r4, r3 8014a92: d105 bne.n 8014aa0 8014a94: f104 0058 add.w r0, r4, #88 @ 0x58 8014a98: e8bd 4010 ldmia.w sp!, {r4, lr} 8014a9c: f000 b906 b.w 8014cac <__retarget_lock_init_recursive> 8014aa0: bd10 pop {r4, pc} 8014aa2: bf00 nop 8014aa4: 08016649 .word 0x08016649 8014aa8: 0801666b .word 0x0801666b 8014aac: 080166a3 .word 0x080166a3 8014ab0: 080166c7 .word 0x080166c7 8014ab4: 2000148c .word 0x2000148c 08014ab8 : 8014ab8: 4a02 ldr r2, [pc, #8] @ (8014ac4 ) 8014aba: 4903 ldr r1, [pc, #12] @ (8014ac8 ) 8014abc: 4803 ldr r0, [pc, #12] @ (8014acc ) 8014abe: f000 b8a5 b.w 8014c0c <_fwalk_sglue> 8014ac2: bf00 nop 8014ac4: 20000090 .word 0x20000090 8014ac8: 08015eed .word 0x08015eed 8014acc: 200000a0 .word 0x200000a0 08014ad0 : 8014ad0: 6841 ldr r1, [r0, #4] 8014ad2: 4b0c ldr r3, [pc, #48] @ (8014b04 ) 8014ad4: b510 push {r4, lr} 8014ad6: 4299 cmp r1, r3 8014ad8: 4604 mov r4, r0 8014ada: d001 beq.n 8014ae0 8014adc: f001 fa06 bl 8015eec <_fflush_r> 8014ae0: 68a1 ldr r1, [r4, #8] 8014ae2: 4b09 ldr r3, [pc, #36] @ (8014b08 ) 8014ae4: 4299 cmp r1, r3 8014ae6: d002 beq.n 8014aee 8014ae8: 4620 mov r0, r4 8014aea: f001 f9ff bl 8015eec <_fflush_r> 8014aee: 68e1 ldr r1, [r4, #12] 8014af0: 4b06 ldr r3, [pc, #24] @ (8014b0c ) 8014af2: 4299 cmp r1, r3 8014af4: d004 beq.n 8014b00 8014af6: 4620 mov r0, r4 8014af8: e8bd 4010 ldmia.w sp!, {r4, lr} 8014afc: f001 b9f6 b.w 8015eec <_fflush_r> 8014b00: bd10 pop {r4, pc} 8014b02: bf00 nop 8014b04: 2000148c .word 0x2000148c 8014b08: 200014f4 .word 0x200014f4 8014b0c: 2000155c .word 0x2000155c 08014b10 : 8014b10: b510 push {r4, lr} 8014b12: 4b0b ldr r3, [pc, #44] @ (8014b40 ) 8014b14: 4c0b ldr r4, [pc, #44] @ (8014b44 ) 8014b16: 4a0c ldr r2, [pc, #48] @ (8014b48 ) 8014b18: 4620 mov r0, r4 8014b1a: 601a str r2, [r3, #0] 8014b1c: 2104 movs r1, #4 8014b1e: 2200 movs r2, #0 8014b20: f7ff ff94 bl 8014a4c 8014b24: f104 0068 add.w r0, r4, #104 @ 0x68 8014b28: 2201 movs r2, #1 8014b2a: 2109 movs r1, #9 8014b2c: f7ff ff8e bl 8014a4c 8014b30: f104 00d0 add.w r0, r4, #208 @ 0xd0 8014b34: 2202 movs r2, #2 8014b36: e8bd 4010 ldmia.w sp!, {r4, lr} 8014b3a: 2112 movs r1, #18 8014b3c: f7ff bf86 b.w 8014a4c 8014b40: 200015c4 .word 0x200015c4 8014b44: 2000148c .word 0x2000148c 8014b48: 08014ab9 .word 0x08014ab9 08014b4c <__sfp_lock_acquire>: 8014b4c: 4801 ldr r0, [pc, #4] @ (8014b54 <__sfp_lock_acquire+0x8>) 8014b4e: f000 b8ae b.w 8014cae <__retarget_lock_acquire_recursive> 8014b52: bf00 nop 8014b54: 200015c9 .word 0x200015c9 08014b58 <__sfp_lock_release>: 8014b58: 4801 ldr r0, [pc, #4] @ (8014b60 <__sfp_lock_release+0x8>) 8014b5a: f000 b8a9 b.w 8014cb0 <__retarget_lock_release_recursive> 8014b5e: bf00 nop 8014b60: 200015c9 .word 0x200015c9 08014b64 <__sinit>: 8014b64: b510 push {r4, lr} 8014b66: 4604 mov r4, r0 8014b68: f7ff fff0 bl 8014b4c <__sfp_lock_acquire> 8014b6c: 6a23 ldr r3, [r4, #32] 8014b6e: b11b cbz r3, 8014b78 <__sinit+0x14> 8014b70: e8bd 4010 ldmia.w sp!, {r4, lr} 8014b74: f7ff bff0 b.w 8014b58 <__sfp_lock_release> 8014b78: 4b04 ldr r3, [pc, #16] @ (8014b8c <__sinit+0x28>) 8014b7a: 6223 str r3, [r4, #32] 8014b7c: 4b04 ldr r3, [pc, #16] @ (8014b90 <__sinit+0x2c>) 8014b7e: 681b ldr r3, [r3, #0] 8014b80: 2b00 cmp r3, #0 8014b82: d1f5 bne.n 8014b70 <__sinit+0xc> 8014b84: f7ff ffc4 bl 8014b10 8014b88: e7f2 b.n 8014b70 <__sinit+0xc> 8014b8a: bf00 nop 8014b8c: 08014ad1 .word 0x08014ad1 8014b90: 200015c4 .word 0x200015c4 08014b94 <_vsniprintf_r>: 8014b94: b530 push {r4, r5, lr} 8014b96: 4614 mov r4, r2 8014b98: 2c00 cmp r4, #0 8014b9a: 4605 mov r5, r0 8014b9c: 461a mov r2, r3 8014b9e: b09b sub sp, #108 @ 0x6c 8014ba0: da05 bge.n 8014bae <_vsniprintf_r+0x1a> 8014ba2: 238b movs r3, #139 @ 0x8b 8014ba4: 6003 str r3, [r0, #0] 8014ba6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8014baa: b01b add sp, #108 @ 0x6c 8014bac: bd30 pop {r4, r5, pc} 8014bae: f44f 7302 mov.w r3, #520 @ 0x208 8014bb2: f8ad 300c strh.w r3, [sp, #12] 8014bb6: f04f 0300 mov.w r3, #0 8014bba: 9319 str r3, [sp, #100] @ 0x64 8014bbc: bf0c ite eq 8014bbe: 4623 moveq r3, r4 8014bc0: f104 33ff addne.w r3, r4, #4294967295 @ 0xffffffff 8014bc4: 9302 str r3, [sp, #8] 8014bc6: 9305 str r3, [sp, #20] 8014bc8: f64f 73ff movw r3, #65535 @ 0xffff 8014bcc: 9100 str r1, [sp, #0] 8014bce: 9104 str r1, [sp, #16] 8014bd0: f8ad 300e strh.w r3, [sp, #14] 8014bd4: 4669 mov r1, sp 8014bd6: 9b1e ldr r3, [sp, #120] @ 0x78 8014bd8: f000 ff62 bl 8015aa0 <_svfiprintf_r> 8014bdc: 1c43 adds r3, r0, #1 8014bde: bfbc itt lt 8014be0: 238b movlt r3, #139 @ 0x8b 8014be2: 602b strlt r3, [r5, #0] 8014be4: 2c00 cmp r4, #0 8014be6: d0e0 beq.n 8014baa <_vsniprintf_r+0x16> 8014be8: 2200 movs r2, #0 8014bea: 9b00 ldr r3, [sp, #0] 8014bec: 701a strb r2, [r3, #0] 8014bee: e7dc b.n 8014baa <_vsniprintf_r+0x16> 08014bf0 : 8014bf0: b507 push {r0, r1, r2, lr} 8014bf2: 9300 str r3, [sp, #0] 8014bf4: 4613 mov r3, r2 8014bf6: 460a mov r2, r1 8014bf8: 4601 mov r1, r0 8014bfa: 4803 ldr r0, [pc, #12] @ (8014c08 ) 8014bfc: 6800 ldr r0, [r0, #0] 8014bfe: f7ff ffc9 bl 8014b94 <_vsniprintf_r> 8014c02: b003 add sp, #12 8014c04: f85d fb04 ldr.w pc, [sp], #4 8014c08: 2000009c .word 0x2000009c 08014c0c <_fwalk_sglue>: 8014c0c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8014c10: 4607 mov r7, r0 8014c12: 4688 mov r8, r1 8014c14: 4614 mov r4, r2 8014c16: 2600 movs r6, #0 8014c18: e9d4 9501 ldrd r9, r5, [r4, #4] 8014c1c: f1b9 0901 subs.w r9, r9, #1 8014c20: d505 bpl.n 8014c2e <_fwalk_sglue+0x22> 8014c22: 6824 ldr r4, [r4, #0] 8014c24: 2c00 cmp r4, #0 8014c26: d1f7 bne.n 8014c18 <_fwalk_sglue+0xc> 8014c28: 4630 mov r0, r6 8014c2a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8014c2e: 89ab ldrh r3, [r5, #12] 8014c30: 2b01 cmp r3, #1 8014c32: d907 bls.n 8014c44 <_fwalk_sglue+0x38> 8014c34: f9b5 300e ldrsh.w r3, [r5, #14] 8014c38: 3301 adds r3, #1 8014c3a: d003 beq.n 8014c44 <_fwalk_sglue+0x38> 8014c3c: 4629 mov r1, r5 8014c3e: 4638 mov r0, r7 8014c40: 47c0 blx r8 8014c42: 4306 orrs r6, r0 8014c44: 3568 adds r5, #104 @ 0x68 8014c46: e7e9 b.n 8014c1c <_fwalk_sglue+0x10> 08014c48 : 8014c48: 4603 mov r3, r0 8014c4a: 4402 add r2, r0 8014c4c: 4293 cmp r3, r2 8014c4e: d100 bne.n 8014c52 8014c50: 4770 bx lr 8014c52: f803 1b01 strb.w r1, [r3], #1 8014c56: e7f9 b.n 8014c4c 08014c58 <__errno>: 8014c58: 4b01 ldr r3, [pc, #4] @ (8014c60 <__errno+0x8>) 8014c5a: 6818 ldr r0, [r3, #0] 8014c5c: 4770 bx lr 8014c5e: bf00 nop 8014c60: 2000009c .word 0x2000009c 08014c64 <__libc_init_array>: 8014c64: b570 push {r4, r5, r6, lr} 8014c66: 2600 movs r6, #0 8014c68: 4d0c ldr r5, [pc, #48] @ (8014c9c <__libc_init_array+0x38>) 8014c6a: 4c0d ldr r4, [pc, #52] @ (8014ca0 <__libc_init_array+0x3c>) 8014c6c: 1b64 subs r4, r4, r5 8014c6e: 10a4 asrs r4, r4, #2 8014c70: 42a6 cmp r6, r4 8014c72: d109 bne.n 8014c88 <__libc_init_array+0x24> 8014c74: f002 f902 bl 8016e7c <_init> 8014c78: 2600 movs r6, #0 8014c7a: 4d0a ldr r5, [pc, #40] @ (8014ca4 <__libc_init_array+0x40>) 8014c7c: 4c0a ldr r4, [pc, #40] @ (8014ca8 <__libc_init_array+0x44>) 8014c7e: 1b64 subs r4, r4, r5 8014c80: 10a4 asrs r4, r4, #2 8014c82: 42a6 cmp r6, r4 8014c84: d105 bne.n 8014c92 <__libc_init_array+0x2e> 8014c86: bd70 pop {r4, r5, r6, pc} 8014c88: f855 3b04 ldr.w r3, [r5], #4 8014c8c: 4798 blx r3 8014c8e: 3601 adds r6, #1 8014c90: e7ee b.n 8014c70 <__libc_init_array+0xc> 8014c92: f855 3b04 ldr.w r3, [r5], #4 8014c96: 4798 blx r3 8014c98: 3601 adds r6, #1 8014c9a: e7f2 b.n 8014c82 <__libc_init_array+0x1e> 8014c9c: 08017c6c .word 0x08017c6c 8014ca0: 08017c6c .word 0x08017c6c 8014ca4: 08017c6c .word 0x08017c6c 8014ca8: 08017c70 .word 0x08017c70 08014cac <__retarget_lock_init_recursive>: 8014cac: 4770 bx lr 08014cae <__retarget_lock_acquire_recursive>: 8014cae: 4770 bx lr 08014cb0 <__retarget_lock_release_recursive>: 8014cb0: 4770 bx lr ... 08014cb4 <_localeconv_r>: 8014cb4: 4800 ldr r0, [pc, #0] @ (8014cb8 <_localeconv_r+0x4>) 8014cb6: 4770 bx lr 8014cb8: 200001dc .word 0x200001dc 08014cbc : 8014cbc: 4603 mov r3, r0 8014cbe: b510 push {r4, lr} 8014cc0: b2c9 uxtb r1, r1 8014cc2: 4402 add r2, r0 8014cc4: 4293 cmp r3, r2 8014cc6: 4618 mov r0, r3 8014cc8: d101 bne.n 8014cce 8014cca: 2000 movs r0, #0 8014ccc: e003 b.n 8014cd6 8014cce: 7804 ldrb r4, [r0, #0] 8014cd0: 3301 adds r3, #1 8014cd2: 428c cmp r4, r1 8014cd4: d1f6 bne.n 8014cc4 8014cd6: bd10 pop {r4, pc} 08014cd8 : 8014cd8: 440a add r2, r1 8014cda: 4291 cmp r1, r2 8014cdc: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8014ce0: d100 bne.n 8014ce4 8014ce2: 4770 bx lr 8014ce4: b510 push {r4, lr} 8014ce6: f811 4b01 ldrb.w r4, [r1], #1 8014cea: 4291 cmp r1, r2 8014cec: f803 4f01 strb.w r4, [r3, #1]! 8014cf0: d1f9 bne.n 8014ce6 8014cf2: bd10 pop {r4, pc} 08014cf4 <__assert_func>: 8014cf4: b51f push {r0, r1, r2, r3, r4, lr} 8014cf6: 4614 mov r4, r2 8014cf8: 461a mov r2, r3 8014cfa: 4b09 ldr r3, [pc, #36] @ (8014d20 <__assert_func+0x2c>) 8014cfc: 4605 mov r5, r0 8014cfe: 681b ldr r3, [r3, #0] 8014d00: 68d8 ldr r0, [r3, #12] 8014d02: b14c cbz r4, 8014d18 <__assert_func+0x24> 8014d04: 4b07 ldr r3, [pc, #28] @ (8014d24 <__assert_func+0x30>) 8014d06: e9cd 3401 strd r3, r4, [sp, #4] 8014d0a: 9100 str r1, [sp, #0] 8014d0c: 462b mov r3, r5 8014d0e: 4906 ldr r1, [pc, #24] @ (8014d28 <__assert_func+0x34>) 8014d10: f001 fcde bl 80166d0 8014d14: f001 fd8c bl 8016830 8014d18: 4b04 ldr r3, [pc, #16] @ (8014d2c <__assert_func+0x38>) 8014d1a: 461c mov r4, r3 8014d1c: e7f3 b.n 8014d06 <__assert_func+0x12> 8014d1e: bf00 nop 8014d20: 2000009c .word 0x2000009c 8014d24: 08017920 .word 0x08017920 8014d28: 0801792d .word 0x0801792d 8014d2c: 0801795b .word 0x0801795b 08014d30 : 8014d30: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8014d34: 6903 ldr r3, [r0, #16] 8014d36: 690c ldr r4, [r1, #16] 8014d38: 4607 mov r7, r0 8014d3a: 42a3 cmp r3, r4 8014d3c: db7e blt.n 8014e3c 8014d3e: 3c01 subs r4, #1 8014d40: 00a3 lsls r3, r4, #2 8014d42: f100 0514 add.w r5, r0, #20 8014d46: f101 0814 add.w r8, r1, #20 8014d4a: 9300 str r3, [sp, #0] 8014d4c: eb05 0384 add.w r3, r5, r4, lsl #2 8014d50: 9301 str r3, [sp, #4] 8014d52: f858 3024 ldr.w r3, [r8, r4, lsl #2] 8014d56: f855 2024 ldr.w r2, [r5, r4, lsl #2] 8014d5a: 3301 adds r3, #1 8014d5c: 429a cmp r2, r3 8014d5e: fbb2 f6f3 udiv r6, r2, r3 8014d62: eb08 0984 add.w r9, r8, r4, lsl #2 8014d66: d32e bcc.n 8014dc6 8014d68: f04f 0a00 mov.w sl, #0 8014d6c: 46c4 mov ip, r8 8014d6e: 46ae mov lr, r5 8014d70: 46d3 mov fp, sl 8014d72: f85c 3b04 ldr.w r3, [ip], #4 8014d76: b298 uxth r0, r3 8014d78: fb06 a000 mla r0, r6, r0, sl 8014d7c: 0c1b lsrs r3, r3, #16 8014d7e: 0c02 lsrs r2, r0, #16 8014d80: fb06 2303 mla r3, r6, r3, r2 8014d84: f8de 2000 ldr.w r2, [lr] 8014d88: b280 uxth r0, r0 8014d8a: b292 uxth r2, r2 8014d8c: 1a12 subs r2, r2, r0 8014d8e: 445a add r2, fp 8014d90: f8de 0000 ldr.w r0, [lr] 8014d94: ea4f 4a13 mov.w sl, r3, lsr #16 8014d98: b29b uxth r3, r3 8014d9a: ebc3 4322 rsb r3, r3, r2, asr #16 8014d9e: eb03 4310 add.w r3, r3, r0, lsr #16 8014da2: b292 uxth r2, r2 8014da4: ea42 4203 orr.w r2, r2, r3, lsl #16 8014da8: 45e1 cmp r9, ip 8014daa: ea4f 4b23 mov.w fp, r3, asr #16 8014dae: f84e 2b04 str.w r2, [lr], #4 8014db2: d2de bcs.n 8014d72 8014db4: 9b00 ldr r3, [sp, #0] 8014db6: 58eb ldr r3, [r5, r3] 8014db8: b92b cbnz r3, 8014dc6 8014dba: 9b01 ldr r3, [sp, #4] 8014dbc: 3b04 subs r3, #4 8014dbe: 429d cmp r5, r3 8014dc0: 461a mov r2, r3 8014dc2: d32f bcc.n 8014e24 8014dc4: 613c str r4, [r7, #16] 8014dc6: 4638 mov r0, r7 8014dc8: f001 fb36 bl 8016438 <__mcmp> 8014dcc: 2800 cmp r0, #0 8014dce: db25 blt.n 8014e1c 8014dd0: 4629 mov r1, r5 8014dd2: 2000 movs r0, #0 8014dd4: f858 2b04 ldr.w r2, [r8], #4 8014dd8: f8d1 c000 ldr.w ip, [r1] 8014ddc: fa1f fe82 uxth.w lr, r2 8014de0: fa1f f38c uxth.w r3, ip 8014de4: eba3 030e sub.w r3, r3, lr 8014de8: 4403 add r3, r0 8014dea: 0c12 lsrs r2, r2, #16 8014dec: ebc2 4223 rsb r2, r2, r3, asr #16 8014df0: eb02 421c add.w r2, r2, ip, lsr #16 8014df4: b29b uxth r3, r3 8014df6: ea43 4302 orr.w r3, r3, r2, lsl #16 8014dfa: 45c1 cmp r9, r8 8014dfc: ea4f 4022 mov.w r0, r2, asr #16 8014e00: f841 3b04 str.w r3, [r1], #4 8014e04: d2e6 bcs.n 8014dd4 8014e06: f855 2024 ldr.w r2, [r5, r4, lsl #2] 8014e0a: eb05 0384 add.w r3, r5, r4, lsl #2 8014e0e: b922 cbnz r2, 8014e1a 8014e10: 3b04 subs r3, #4 8014e12: 429d cmp r5, r3 8014e14: 461a mov r2, r3 8014e16: d30b bcc.n 8014e30 8014e18: 613c str r4, [r7, #16] 8014e1a: 3601 adds r6, #1 8014e1c: 4630 mov r0, r6 8014e1e: b003 add sp, #12 8014e20: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8014e24: 6812 ldr r2, [r2, #0] 8014e26: 3b04 subs r3, #4 8014e28: 2a00 cmp r2, #0 8014e2a: d1cb bne.n 8014dc4 8014e2c: 3c01 subs r4, #1 8014e2e: e7c6 b.n 8014dbe 8014e30: 6812 ldr r2, [r2, #0] 8014e32: 3b04 subs r3, #4 8014e34: 2a00 cmp r2, #0 8014e36: d1ef bne.n 8014e18 8014e38: 3c01 subs r4, #1 8014e3a: e7ea b.n 8014e12 8014e3c: 2000 movs r0, #0 8014e3e: e7ee b.n 8014e1e 08014e40 <_dtoa_r>: 8014e40: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8014e44: 4614 mov r4, r2 8014e46: 461d mov r5, r3 8014e48: 69c7 ldr r7, [r0, #28] 8014e4a: b097 sub sp, #92 @ 0x5c 8014e4c: 4681 mov r9, r0 8014e4e: e9cd 4506 strd r4, r5, [sp, #24] 8014e52: 9e23 ldr r6, [sp, #140] @ 0x8c 8014e54: b97f cbnz r7, 8014e76 <_dtoa_r+0x36> 8014e56: 2010 movs r0, #16 8014e58: f000 ff1e bl 8015c98 8014e5c: 4602 mov r2, r0 8014e5e: f8c9 001c str.w r0, [r9, #28] 8014e62: b920 cbnz r0, 8014e6e <_dtoa_r+0x2e> 8014e64: 21ef movs r1, #239 @ 0xef 8014e66: 4bac ldr r3, [pc, #688] @ (8015118 <_dtoa_r+0x2d8>) 8014e68: 48ac ldr r0, [pc, #688] @ (801511c <_dtoa_r+0x2dc>) 8014e6a: f7ff ff43 bl 8014cf4 <__assert_func> 8014e6e: e9c0 7701 strd r7, r7, [r0, #4] 8014e72: 6007 str r7, [r0, #0] 8014e74: 60c7 str r7, [r0, #12] 8014e76: f8d9 301c ldr.w r3, [r9, #28] 8014e7a: 6819 ldr r1, [r3, #0] 8014e7c: b159 cbz r1, 8014e96 <_dtoa_r+0x56> 8014e7e: 685a ldr r2, [r3, #4] 8014e80: 2301 movs r3, #1 8014e82: 4093 lsls r3, r2 8014e84: 604a str r2, [r1, #4] 8014e86: 608b str r3, [r1, #8] 8014e88: 4648 mov r0, r9 8014e8a: f001 f8a3 bl 8015fd4 <_Bfree> 8014e8e: 2200 movs r2, #0 8014e90: f8d9 301c ldr.w r3, [r9, #28] 8014e94: 601a str r2, [r3, #0] 8014e96: 1e2b subs r3, r5, #0 8014e98: bfaf iteee ge 8014e9a: 2300 movge r3, #0 8014e9c: 2201 movlt r2, #1 8014e9e: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000 8014ea2: 9307 strlt r3, [sp, #28] 8014ea4: bfa8 it ge 8014ea6: 6033 strge r3, [r6, #0] 8014ea8: f8dd 801c ldr.w r8, [sp, #28] 8014eac: 4b9c ldr r3, [pc, #624] @ (8015120 <_dtoa_r+0x2e0>) 8014eae: bfb8 it lt 8014eb0: 6032 strlt r2, [r6, #0] 8014eb2: ea33 0308 bics.w r3, r3, r8 8014eb6: d112 bne.n 8014ede <_dtoa_r+0x9e> 8014eb8: f242 730f movw r3, #9999 @ 0x270f 8014ebc: 9a22 ldr r2, [sp, #136] @ 0x88 8014ebe: 6013 str r3, [r2, #0] 8014ec0: f3c8 0313 ubfx r3, r8, #0, #20 8014ec4: 4323 orrs r3, r4 8014ec6: f000 855e beq.w 8015986 <_dtoa_r+0xb46> 8014eca: 9b24 ldr r3, [sp, #144] @ 0x90 8014ecc: f8df a254 ldr.w sl, [pc, #596] @ 8015124 <_dtoa_r+0x2e4> 8014ed0: 2b00 cmp r3, #0 8014ed2: f000 8560 beq.w 8015996 <_dtoa_r+0xb56> 8014ed6: f10a 0303 add.w r3, sl, #3 8014eda: f000 bd5a b.w 8015992 <_dtoa_r+0xb52> 8014ede: e9dd 2306 ldrd r2, r3, [sp, #24] 8014ee2: e9cd 230c strd r2, r3, [sp, #48] @ 0x30 8014ee6: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8014eea: 2200 movs r2, #0 8014eec: 2300 movs r3, #0 8014eee: f7f3 fdc7 bl 8008a80 <__aeabi_dcmpeq> 8014ef2: 4607 mov r7, r0 8014ef4: b158 cbz r0, 8014f0e <_dtoa_r+0xce> 8014ef6: 2301 movs r3, #1 8014ef8: 9a22 ldr r2, [sp, #136] @ 0x88 8014efa: 6013 str r3, [r2, #0] 8014efc: 9b24 ldr r3, [sp, #144] @ 0x90 8014efe: b113 cbz r3, 8014f06 <_dtoa_r+0xc6> 8014f00: 4b89 ldr r3, [pc, #548] @ (8015128 <_dtoa_r+0x2e8>) 8014f02: 9a24 ldr r2, [sp, #144] @ 0x90 8014f04: 6013 str r3, [r2, #0] 8014f06: f8df a224 ldr.w sl, [pc, #548] @ 801512c <_dtoa_r+0x2ec> 8014f0a: f000 bd44 b.w 8015996 <_dtoa_r+0xb56> 8014f0e: ab14 add r3, sp, #80 @ 0x50 8014f10: 9301 str r3, [sp, #4] 8014f12: ab15 add r3, sp, #84 @ 0x54 8014f14: 9300 str r3, [sp, #0] 8014f16: 4648 mov r0, r9 8014f18: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30 8014f1c: f001 fb3c bl 8016598 <__d2b> 8014f20: f3c8 560a ubfx r6, r8, #20, #11 8014f24: 9003 str r0, [sp, #12] 8014f26: 2e00 cmp r6, #0 8014f28: d078 beq.n 801501c <_dtoa_r+0x1dc> 8014f2a: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8014f2e: 9b0d ldr r3, [sp, #52] @ 0x34 8014f30: f2a6 36ff subw r6, r6, #1023 @ 0x3ff 8014f34: f3c3 0313 ubfx r3, r3, #0, #20 8014f38: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000 8014f3c: f443 1340 orr.w r3, r3, #3145728 @ 0x300000 8014f40: 9712 str r7, [sp, #72] @ 0x48 8014f42: 4619 mov r1, r3 8014f44: 2200 movs r2, #0 8014f46: 4b7a ldr r3, [pc, #488] @ (8015130 <_dtoa_r+0x2f0>) 8014f48: f7f3 f97a bl 8008240 <__aeabi_dsub> 8014f4c: a36c add r3, pc, #432 @ (adr r3, 8015100 <_dtoa_r+0x2c0>) 8014f4e: e9d3 2300 ldrd r2, r3, [r3] 8014f52: f7f3 fb2d bl 80085b0 <__aeabi_dmul> 8014f56: a36c add r3, pc, #432 @ (adr r3, 8015108 <_dtoa_r+0x2c8>) 8014f58: e9d3 2300 ldrd r2, r3, [r3] 8014f5c: f7f3 f972 bl 8008244 <__adddf3> 8014f60: 4604 mov r4, r0 8014f62: 4630 mov r0, r6 8014f64: 460d mov r5, r1 8014f66: f7f3 fab9 bl 80084dc <__aeabi_i2d> 8014f6a: a369 add r3, pc, #420 @ (adr r3, 8015110 <_dtoa_r+0x2d0>) 8014f6c: e9d3 2300 ldrd r2, r3, [r3] 8014f70: f7f3 fb1e bl 80085b0 <__aeabi_dmul> 8014f74: 4602 mov r2, r0 8014f76: 460b mov r3, r1 8014f78: 4620 mov r0, r4 8014f7a: 4629 mov r1, r5 8014f7c: f7f3 f962 bl 8008244 <__adddf3> 8014f80: 4604 mov r4, r0 8014f82: 460d mov r5, r1 8014f84: f7f3 fdc4 bl 8008b10 <__aeabi_d2iz> 8014f88: 2200 movs r2, #0 8014f8a: 4607 mov r7, r0 8014f8c: 2300 movs r3, #0 8014f8e: 4620 mov r0, r4 8014f90: 4629 mov r1, r5 8014f92: f7f3 fd7f bl 8008a94 <__aeabi_dcmplt> 8014f96: b140 cbz r0, 8014faa <_dtoa_r+0x16a> 8014f98: 4638 mov r0, r7 8014f9a: f7f3 fa9f bl 80084dc <__aeabi_i2d> 8014f9e: 4622 mov r2, r4 8014fa0: 462b mov r3, r5 8014fa2: f7f3 fd6d bl 8008a80 <__aeabi_dcmpeq> 8014fa6: b900 cbnz r0, 8014faa <_dtoa_r+0x16a> 8014fa8: 3f01 subs r7, #1 8014faa: 2f16 cmp r7, #22 8014fac: d854 bhi.n 8015058 <_dtoa_r+0x218> 8014fae: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8014fb2: 4b60 ldr r3, [pc, #384] @ (8015134 <_dtoa_r+0x2f4>) 8014fb4: eb03 03c7 add.w r3, r3, r7, lsl #3 8014fb8: e9d3 2300 ldrd r2, r3, [r3] 8014fbc: f7f3 fd6a bl 8008a94 <__aeabi_dcmplt> 8014fc0: 2800 cmp r0, #0 8014fc2: d04b beq.n 801505c <_dtoa_r+0x21c> 8014fc4: 2300 movs r3, #0 8014fc6: 3f01 subs r7, #1 8014fc8: 930f str r3, [sp, #60] @ 0x3c 8014fca: 9b14 ldr r3, [sp, #80] @ 0x50 8014fcc: 1b9b subs r3, r3, r6 8014fce: 1e5a subs r2, r3, #1 8014fd0: bf49 itett mi 8014fd2: f1c3 0301 rsbmi r3, r3, #1 8014fd6: 2300 movpl r3, #0 8014fd8: 9304 strmi r3, [sp, #16] 8014fda: 2300 movmi r3, #0 8014fdc: 9209 str r2, [sp, #36] @ 0x24 8014fde: bf54 ite pl 8014fe0: 9304 strpl r3, [sp, #16] 8014fe2: 9309 strmi r3, [sp, #36] @ 0x24 8014fe4: 2f00 cmp r7, #0 8014fe6: db3b blt.n 8015060 <_dtoa_r+0x220> 8014fe8: 9b09 ldr r3, [sp, #36] @ 0x24 8014fea: 970e str r7, [sp, #56] @ 0x38 8014fec: 443b add r3, r7 8014fee: 9309 str r3, [sp, #36] @ 0x24 8014ff0: 2300 movs r3, #0 8014ff2: 930a str r3, [sp, #40] @ 0x28 8014ff4: 9b20 ldr r3, [sp, #128] @ 0x80 8014ff6: 2b09 cmp r3, #9 8014ff8: d865 bhi.n 80150c6 <_dtoa_r+0x286> 8014ffa: 2b05 cmp r3, #5 8014ffc: bfc4 itt gt 8014ffe: 3b04 subgt r3, #4 8015000: 9320 strgt r3, [sp, #128] @ 0x80 8015002: 9b20 ldr r3, [sp, #128] @ 0x80 8015004: bfc8 it gt 8015006: 2400 movgt r4, #0 8015008: f1a3 0302 sub.w r3, r3, #2 801500c: bfd8 it le 801500e: 2401 movle r4, #1 8015010: 2b03 cmp r3, #3 8015012: d864 bhi.n 80150de <_dtoa_r+0x29e> 8015014: e8df f003 tbb [pc, r3] 8015018: 2c385553 .word 0x2c385553 801501c: e9dd 6314 ldrd r6, r3, [sp, #80] @ 0x50 8015020: 441e add r6, r3 8015022: f206 4332 addw r3, r6, #1074 @ 0x432 8015026: 2b20 cmp r3, #32 8015028: bfc1 itttt gt 801502a: f1c3 0340 rsbgt r3, r3, #64 @ 0x40 801502e: fa08 f803 lslgt.w r8, r8, r3 8015032: f206 4312 addwgt r3, r6, #1042 @ 0x412 8015036: fa24 f303 lsrgt.w r3, r4, r3 801503a: bfd6 itet le 801503c: f1c3 0320 rsble r3, r3, #32 8015040: ea48 0003 orrgt.w r0, r8, r3 8015044: fa04 f003 lslle.w r0, r4, r3 8015048: f7f3 fa38 bl 80084bc <__aeabi_ui2d> 801504c: 2201 movs r2, #1 801504e: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000 8015052: 3e01 subs r6, #1 8015054: 9212 str r2, [sp, #72] @ 0x48 8015056: e774 b.n 8014f42 <_dtoa_r+0x102> 8015058: 2301 movs r3, #1 801505a: e7b5 b.n 8014fc8 <_dtoa_r+0x188> 801505c: 900f str r0, [sp, #60] @ 0x3c 801505e: e7b4 b.n 8014fca <_dtoa_r+0x18a> 8015060: 9b04 ldr r3, [sp, #16] 8015062: 1bdb subs r3, r3, r7 8015064: 9304 str r3, [sp, #16] 8015066: 427b negs r3, r7 8015068: 930a str r3, [sp, #40] @ 0x28 801506a: 2300 movs r3, #0 801506c: 930e str r3, [sp, #56] @ 0x38 801506e: e7c1 b.n 8014ff4 <_dtoa_r+0x1b4> 8015070: 2301 movs r3, #1 8015072: 930b str r3, [sp, #44] @ 0x2c 8015074: 9b21 ldr r3, [sp, #132] @ 0x84 8015076: eb07 0b03 add.w fp, r7, r3 801507a: f10b 0301 add.w r3, fp, #1 801507e: 2b01 cmp r3, #1 8015080: 9308 str r3, [sp, #32] 8015082: bfb8 it lt 8015084: 2301 movlt r3, #1 8015086: e006 b.n 8015096 <_dtoa_r+0x256> 8015088: 2301 movs r3, #1 801508a: 930b str r3, [sp, #44] @ 0x2c 801508c: 9b21 ldr r3, [sp, #132] @ 0x84 801508e: 2b00 cmp r3, #0 8015090: dd28 ble.n 80150e4 <_dtoa_r+0x2a4> 8015092: 469b mov fp, r3 8015094: 9308 str r3, [sp, #32] 8015096: 2100 movs r1, #0 8015098: 2204 movs r2, #4 801509a: f8d9 001c ldr.w r0, [r9, #28] 801509e: f102 0514 add.w r5, r2, #20 80150a2: 429d cmp r5, r3 80150a4: d926 bls.n 80150f4 <_dtoa_r+0x2b4> 80150a6: 6041 str r1, [r0, #4] 80150a8: 4648 mov r0, r9 80150aa: f000 ff53 bl 8015f54 <_Balloc> 80150ae: 4682 mov sl, r0 80150b0: 2800 cmp r0, #0 80150b2: d143 bne.n 801513c <_dtoa_r+0x2fc> 80150b4: 4602 mov r2, r0 80150b6: f240 11af movw r1, #431 @ 0x1af 80150ba: 4b1f ldr r3, [pc, #124] @ (8015138 <_dtoa_r+0x2f8>) 80150bc: e6d4 b.n 8014e68 <_dtoa_r+0x28> 80150be: 2300 movs r3, #0 80150c0: e7e3 b.n 801508a <_dtoa_r+0x24a> 80150c2: 2300 movs r3, #0 80150c4: e7d5 b.n 8015072 <_dtoa_r+0x232> 80150c6: 2401 movs r4, #1 80150c8: 2300 movs r3, #0 80150ca: 940b str r4, [sp, #44] @ 0x2c 80150cc: 9320 str r3, [sp, #128] @ 0x80 80150ce: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff 80150d2: 2200 movs r2, #0 80150d4: 2312 movs r3, #18 80150d6: f8cd b020 str.w fp, [sp, #32] 80150da: 9221 str r2, [sp, #132] @ 0x84 80150dc: e7db b.n 8015096 <_dtoa_r+0x256> 80150de: 2301 movs r3, #1 80150e0: 930b str r3, [sp, #44] @ 0x2c 80150e2: e7f4 b.n 80150ce <_dtoa_r+0x28e> 80150e4: f04f 0b01 mov.w fp, #1 80150e8: 465b mov r3, fp 80150ea: f8cd b020 str.w fp, [sp, #32] 80150ee: f8cd b084 str.w fp, [sp, #132] @ 0x84 80150f2: e7d0 b.n 8015096 <_dtoa_r+0x256> 80150f4: 3101 adds r1, #1 80150f6: 0052 lsls r2, r2, #1 80150f8: e7d1 b.n 801509e <_dtoa_r+0x25e> 80150fa: bf00 nop 80150fc: f3af 8000 nop.w 8015100: 636f4361 .word 0x636f4361 8015104: 3fd287a7 .word 0x3fd287a7 8015108: 8b60c8b3 .word 0x8b60c8b3 801510c: 3fc68a28 .word 0x3fc68a28 8015110: 509f79fb .word 0x509f79fb 8015114: 3fd34413 .word 0x3fd34413 8015118: 08017969 .word 0x08017969 801511c: 08017980 .word 0x08017980 8015120: 7ff00000 .word 0x7ff00000 8015124: 08017965 .word 0x08017965 8015128: 080178fd .word 0x080178fd 801512c: 080178fc .word 0x080178fc 8015130: 3ff80000 .word 0x3ff80000 8015134: 08017a98 .word 0x08017a98 8015138: 080179d8 .word 0x080179d8 801513c: f8d9 301c ldr.w r3, [r9, #28] 8015140: 6018 str r0, [r3, #0] 8015142: 9b08 ldr r3, [sp, #32] 8015144: 2b0e cmp r3, #14 8015146: f200 80a1 bhi.w 801528c <_dtoa_r+0x44c> 801514a: 2c00 cmp r4, #0 801514c: f000 809e beq.w 801528c <_dtoa_r+0x44c> 8015150: 2f00 cmp r7, #0 8015152: dd33 ble.n 80151bc <_dtoa_r+0x37c> 8015154: 4b9c ldr r3, [pc, #624] @ (80153c8 <_dtoa_r+0x588>) 8015156: f007 020f and.w r2, r7, #15 801515a: eb03 03c2 add.w r3, r3, r2, lsl #3 801515e: 05f8 lsls r0, r7, #23 8015160: e9d3 3400 ldrd r3, r4, [r3] 8015164: e9cd 3410 strd r3, r4, [sp, #64] @ 0x40 8015168: ea4f 1427 mov.w r4, r7, asr #4 801516c: d516 bpl.n 801519c <_dtoa_r+0x35c> 801516e: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8015172: 4b96 ldr r3, [pc, #600] @ (80153cc <_dtoa_r+0x58c>) 8015174: 2603 movs r6, #3 8015176: e9d3 2308 ldrd r2, r3, [r3, #32] 801517a: f7f3 fb43 bl 8008804 <__aeabi_ddiv> 801517e: e9cd 0106 strd r0, r1, [sp, #24] 8015182: f004 040f and.w r4, r4, #15 8015186: 4d91 ldr r5, [pc, #580] @ (80153cc <_dtoa_r+0x58c>) 8015188: b954 cbnz r4, 80151a0 <_dtoa_r+0x360> 801518a: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 801518e: e9dd 0106 ldrd r0, r1, [sp, #24] 8015192: f7f3 fb37 bl 8008804 <__aeabi_ddiv> 8015196: e9cd 0106 strd r0, r1, [sp, #24] 801519a: e028 b.n 80151ee <_dtoa_r+0x3ae> 801519c: 2602 movs r6, #2 801519e: e7f2 b.n 8015186 <_dtoa_r+0x346> 80151a0: 07e1 lsls r1, r4, #31 80151a2: d508 bpl.n 80151b6 <_dtoa_r+0x376> 80151a4: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 80151a8: e9d5 2300 ldrd r2, r3, [r5] 80151ac: f7f3 fa00 bl 80085b0 <__aeabi_dmul> 80151b0: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 80151b4: 3601 adds r6, #1 80151b6: 1064 asrs r4, r4, #1 80151b8: 3508 adds r5, #8 80151ba: e7e5 b.n 8015188 <_dtoa_r+0x348> 80151bc: f000 80af beq.w 801531e <_dtoa_r+0x4de> 80151c0: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 80151c4: 427c negs r4, r7 80151c6: 4b80 ldr r3, [pc, #512] @ (80153c8 <_dtoa_r+0x588>) 80151c8: f004 020f and.w r2, r4, #15 80151cc: eb03 03c2 add.w r3, r3, r2, lsl #3 80151d0: e9d3 2300 ldrd r2, r3, [r3] 80151d4: f7f3 f9ec bl 80085b0 <__aeabi_dmul> 80151d8: 2602 movs r6, #2 80151da: 2300 movs r3, #0 80151dc: e9cd 0106 strd r0, r1, [sp, #24] 80151e0: 4d7a ldr r5, [pc, #488] @ (80153cc <_dtoa_r+0x58c>) 80151e2: 1124 asrs r4, r4, #4 80151e4: 2c00 cmp r4, #0 80151e6: f040 808f bne.w 8015308 <_dtoa_r+0x4c8> 80151ea: 2b00 cmp r3, #0 80151ec: d1d3 bne.n 8015196 <_dtoa_r+0x356> 80151ee: e9dd 4506 ldrd r4, r5, [sp, #24] 80151f2: 9b0f ldr r3, [sp, #60] @ 0x3c 80151f4: 2b00 cmp r3, #0 80151f6: f000 8094 beq.w 8015322 <_dtoa_r+0x4e2> 80151fa: 2200 movs r2, #0 80151fc: 4620 mov r0, r4 80151fe: 4629 mov r1, r5 8015200: 4b73 ldr r3, [pc, #460] @ (80153d0 <_dtoa_r+0x590>) 8015202: f7f3 fc47 bl 8008a94 <__aeabi_dcmplt> 8015206: 2800 cmp r0, #0 8015208: f000 808b beq.w 8015322 <_dtoa_r+0x4e2> 801520c: 9b08 ldr r3, [sp, #32] 801520e: 2b00 cmp r3, #0 8015210: f000 8087 beq.w 8015322 <_dtoa_r+0x4e2> 8015214: f1bb 0f00 cmp.w fp, #0 8015218: dd34 ble.n 8015284 <_dtoa_r+0x444> 801521a: 4620 mov r0, r4 801521c: 2200 movs r2, #0 801521e: 4629 mov r1, r5 8015220: 4b6c ldr r3, [pc, #432] @ (80153d4 <_dtoa_r+0x594>) 8015222: f7f3 f9c5 bl 80085b0 <__aeabi_dmul> 8015226: 465c mov r4, fp 8015228: e9cd 0106 strd r0, r1, [sp, #24] 801522c: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 8015230: 3601 adds r6, #1 8015232: 4630 mov r0, r6 8015234: f7f3 f952 bl 80084dc <__aeabi_i2d> 8015238: e9dd 2306 ldrd r2, r3, [sp, #24] 801523c: f7f3 f9b8 bl 80085b0 <__aeabi_dmul> 8015240: 2200 movs r2, #0 8015242: 4b65 ldr r3, [pc, #404] @ (80153d8 <_dtoa_r+0x598>) 8015244: f7f2 fffe bl 8008244 <__adddf3> 8015248: 4605 mov r5, r0 801524a: f1a1 7650 sub.w r6, r1, #54525952 @ 0x3400000 801524e: 2c00 cmp r4, #0 8015250: d16a bne.n 8015328 <_dtoa_r+0x4e8> 8015252: e9dd 0106 ldrd r0, r1, [sp, #24] 8015256: 2200 movs r2, #0 8015258: 4b60 ldr r3, [pc, #384] @ (80153dc <_dtoa_r+0x59c>) 801525a: f7f2 fff1 bl 8008240 <__aeabi_dsub> 801525e: 4602 mov r2, r0 8015260: 460b mov r3, r1 8015262: e9cd 2306 strd r2, r3, [sp, #24] 8015266: 462a mov r2, r5 8015268: 4633 mov r3, r6 801526a: f7f3 fc31 bl 8008ad0 <__aeabi_dcmpgt> 801526e: 2800 cmp r0, #0 8015270: f040 8298 bne.w 80157a4 <_dtoa_r+0x964> 8015274: e9dd 0106 ldrd r0, r1, [sp, #24] 8015278: 462a mov r2, r5 801527a: f106 4300 add.w r3, r6, #2147483648 @ 0x80000000 801527e: f7f3 fc09 bl 8008a94 <__aeabi_dcmplt> 8015282: bb38 cbnz r0, 80152d4 <_dtoa_r+0x494> 8015284: e9dd 340c ldrd r3, r4, [sp, #48] @ 0x30 8015288: e9cd 3406 strd r3, r4, [sp, #24] 801528c: 9b15 ldr r3, [sp, #84] @ 0x54 801528e: 2b00 cmp r3, #0 8015290: f2c0 8157 blt.w 8015542 <_dtoa_r+0x702> 8015294: 2f0e cmp r7, #14 8015296: f300 8154 bgt.w 8015542 <_dtoa_r+0x702> 801529a: 4b4b ldr r3, [pc, #300] @ (80153c8 <_dtoa_r+0x588>) 801529c: eb03 03c7 add.w r3, r3, r7, lsl #3 80152a0: e9d3 3400 ldrd r3, r4, [r3] 80152a4: e9cd 3404 strd r3, r4, [sp, #16] 80152a8: 9b21 ldr r3, [sp, #132] @ 0x84 80152aa: 2b00 cmp r3, #0 80152ac: f280 80e5 bge.w 801547a <_dtoa_r+0x63a> 80152b0: 9b08 ldr r3, [sp, #32] 80152b2: 2b00 cmp r3, #0 80152b4: f300 80e1 bgt.w 801547a <_dtoa_r+0x63a> 80152b8: d10c bne.n 80152d4 <_dtoa_r+0x494> 80152ba: e9dd 0104 ldrd r0, r1, [sp, #16] 80152be: 2200 movs r2, #0 80152c0: 4b46 ldr r3, [pc, #280] @ (80153dc <_dtoa_r+0x59c>) 80152c2: f7f3 f975 bl 80085b0 <__aeabi_dmul> 80152c6: e9dd 2306 ldrd r2, r3, [sp, #24] 80152ca: f7f3 fbf7 bl 8008abc <__aeabi_dcmpge> 80152ce: 2800 cmp r0, #0 80152d0: f000 8266 beq.w 80157a0 <_dtoa_r+0x960> 80152d4: 2400 movs r4, #0 80152d6: 4625 mov r5, r4 80152d8: 9b21 ldr r3, [sp, #132] @ 0x84 80152da: 4656 mov r6, sl 80152dc: ea6f 0803 mvn.w r8, r3 80152e0: 2700 movs r7, #0 80152e2: 4621 mov r1, r4 80152e4: 4648 mov r0, r9 80152e6: f000 fe75 bl 8015fd4 <_Bfree> 80152ea: 2d00 cmp r5, #0 80152ec: f000 80bd beq.w 801546a <_dtoa_r+0x62a> 80152f0: b12f cbz r7, 80152fe <_dtoa_r+0x4be> 80152f2: 42af cmp r7, r5 80152f4: d003 beq.n 80152fe <_dtoa_r+0x4be> 80152f6: 4639 mov r1, r7 80152f8: 4648 mov r0, r9 80152fa: f000 fe6b bl 8015fd4 <_Bfree> 80152fe: 4629 mov r1, r5 8015300: 4648 mov r0, r9 8015302: f000 fe67 bl 8015fd4 <_Bfree> 8015306: e0b0 b.n 801546a <_dtoa_r+0x62a> 8015308: 07e2 lsls r2, r4, #31 801530a: d505 bpl.n 8015318 <_dtoa_r+0x4d8> 801530c: e9d5 2300 ldrd r2, r3, [r5] 8015310: f7f3 f94e bl 80085b0 <__aeabi_dmul> 8015314: 2301 movs r3, #1 8015316: 3601 adds r6, #1 8015318: 1064 asrs r4, r4, #1 801531a: 3508 adds r5, #8 801531c: e762 b.n 80151e4 <_dtoa_r+0x3a4> 801531e: 2602 movs r6, #2 8015320: e765 b.n 80151ee <_dtoa_r+0x3ae> 8015322: 46b8 mov r8, r7 8015324: 9c08 ldr r4, [sp, #32] 8015326: e784 b.n 8015232 <_dtoa_r+0x3f2> 8015328: 4b27 ldr r3, [pc, #156] @ (80153c8 <_dtoa_r+0x588>) 801532a: 990b ldr r1, [sp, #44] @ 0x2c 801532c: eb03 03c4 add.w r3, r3, r4, lsl #3 8015330: e953 2302 ldrd r2, r3, [r3, #-8] 8015334: 4454 add r4, sl 8015336: 2900 cmp r1, #0 8015338: d054 beq.n 80153e4 <_dtoa_r+0x5a4> 801533a: 2000 movs r0, #0 801533c: 4928 ldr r1, [pc, #160] @ (80153e0 <_dtoa_r+0x5a0>) 801533e: f7f3 fa61 bl 8008804 <__aeabi_ddiv> 8015342: 4633 mov r3, r6 8015344: 462a mov r2, r5 8015346: f7f2 ff7b bl 8008240 <__aeabi_dsub> 801534a: 4656 mov r6, sl 801534c: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 8015350: e9dd 0106 ldrd r0, r1, [sp, #24] 8015354: f7f3 fbdc bl 8008b10 <__aeabi_d2iz> 8015358: 4605 mov r5, r0 801535a: f7f3 f8bf bl 80084dc <__aeabi_i2d> 801535e: 4602 mov r2, r0 8015360: 460b mov r3, r1 8015362: e9dd 0106 ldrd r0, r1, [sp, #24] 8015366: f7f2 ff6b bl 8008240 <__aeabi_dsub> 801536a: 4602 mov r2, r0 801536c: 460b mov r3, r1 801536e: 3530 adds r5, #48 @ 0x30 8015370: e9cd 2306 strd r2, r3, [sp, #24] 8015374: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8015378: f806 5b01 strb.w r5, [r6], #1 801537c: f7f3 fb8a bl 8008a94 <__aeabi_dcmplt> 8015380: 2800 cmp r0, #0 8015382: d172 bne.n 801546a <_dtoa_r+0x62a> 8015384: e9dd 2306 ldrd r2, r3, [sp, #24] 8015388: 2000 movs r0, #0 801538a: 4911 ldr r1, [pc, #68] @ (80153d0 <_dtoa_r+0x590>) 801538c: f7f2 ff58 bl 8008240 <__aeabi_dsub> 8015390: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8015394: f7f3 fb7e bl 8008a94 <__aeabi_dcmplt> 8015398: 2800 cmp r0, #0 801539a: f040 80b4 bne.w 8015506 <_dtoa_r+0x6c6> 801539e: 42a6 cmp r6, r4 80153a0: f43f af70 beq.w 8015284 <_dtoa_r+0x444> 80153a4: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 80153a8: 2200 movs r2, #0 80153aa: 4b0a ldr r3, [pc, #40] @ (80153d4 <_dtoa_r+0x594>) 80153ac: f7f3 f900 bl 80085b0 <__aeabi_dmul> 80153b0: 2200 movs r2, #0 80153b2: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 80153b6: e9dd 0106 ldrd r0, r1, [sp, #24] 80153ba: 4b06 ldr r3, [pc, #24] @ (80153d4 <_dtoa_r+0x594>) 80153bc: f7f3 f8f8 bl 80085b0 <__aeabi_dmul> 80153c0: e9cd 0106 strd r0, r1, [sp, #24] 80153c4: e7c4 b.n 8015350 <_dtoa_r+0x510> 80153c6: bf00 nop 80153c8: 08017a98 .word 0x08017a98 80153cc: 08017a70 .word 0x08017a70 80153d0: 3ff00000 .word 0x3ff00000 80153d4: 40240000 .word 0x40240000 80153d8: 401c0000 .word 0x401c0000 80153dc: 40140000 .word 0x40140000 80153e0: 3fe00000 .word 0x3fe00000 80153e4: 4631 mov r1, r6 80153e6: 4628 mov r0, r5 80153e8: f7f3 f8e2 bl 80085b0 <__aeabi_dmul> 80153ec: 4656 mov r6, sl 80153ee: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 80153f2: 9413 str r4, [sp, #76] @ 0x4c 80153f4: e9dd 0106 ldrd r0, r1, [sp, #24] 80153f8: f7f3 fb8a bl 8008b10 <__aeabi_d2iz> 80153fc: 4605 mov r5, r0 80153fe: f7f3 f86d bl 80084dc <__aeabi_i2d> 8015402: 4602 mov r2, r0 8015404: 460b mov r3, r1 8015406: e9dd 0106 ldrd r0, r1, [sp, #24] 801540a: f7f2 ff19 bl 8008240 <__aeabi_dsub> 801540e: 4602 mov r2, r0 8015410: 460b mov r3, r1 8015412: 3530 adds r5, #48 @ 0x30 8015414: f806 5b01 strb.w r5, [r6], #1 8015418: 42a6 cmp r6, r4 801541a: e9cd 2306 strd r2, r3, [sp, #24] 801541e: f04f 0200 mov.w r2, #0 8015422: d124 bne.n 801546e <_dtoa_r+0x62e> 8015424: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8015428: 4bae ldr r3, [pc, #696] @ (80156e4 <_dtoa_r+0x8a4>) 801542a: f7f2 ff0b bl 8008244 <__adddf3> 801542e: 4602 mov r2, r0 8015430: 460b mov r3, r1 8015432: e9dd 0106 ldrd r0, r1, [sp, #24] 8015436: f7f3 fb4b bl 8008ad0 <__aeabi_dcmpgt> 801543a: 2800 cmp r0, #0 801543c: d163 bne.n 8015506 <_dtoa_r+0x6c6> 801543e: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8015442: 2000 movs r0, #0 8015444: 49a7 ldr r1, [pc, #668] @ (80156e4 <_dtoa_r+0x8a4>) 8015446: f7f2 fefb bl 8008240 <__aeabi_dsub> 801544a: 4602 mov r2, r0 801544c: 460b mov r3, r1 801544e: e9dd 0106 ldrd r0, r1, [sp, #24] 8015452: f7f3 fb1f bl 8008a94 <__aeabi_dcmplt> 8015456: 2800 cmp r0, #0 8015458: f43f af14 beq.w 8015284 <_dtoa_r+0x444> 801545c: 9e13 ldr r6, [sp, #76] @ 0x4c 801545e: 1e73 subs r3, r6, #1 8015460: 9313 str r3, [sp, #76] @ 0x4c 8015462: f816 3c01 ldrb.w r3, [r6, #-1] 8015466: 2b30 cmp r3, #48 @ 0x30 8015468: d0f8 beq.n 801545c <_dtoa_r+0x61c> 801546a: 4647 mov r7, r8 801546c: e03b b.n 80154e6 <_dtoa_r+0x6a6> 801546e: 4b9e ldr r3, [pc, #632] @ (80156e8 <_dtoa_r+0x8a8>) 8015470: f7f3 f89e bl 80085b0 <__aeabi_dmul> 8015474: e9cd 0106 strd r0, r1, [sp, #24] 8015478: e7bc b.n 80153f4 <_dtoa_r+0x5b4> 801547a: 4656 mov r6, sl 801547c: e9dd 4506 ldrd r4, r5, [sp, #24] 8015480: e9dd 2304 ldrd r2, r3, [sp, #16] 8015484: 4620 mov r0, r4 8015486: 4629 mov r1, r5 8015488: f7f3 f9bc bl 8008804 <__aeabi_ddiv> 801548c: f7f3 fb40 bl 8008b10 <__aeabi_d2iz> 8015490: 4680 mov r8, r0 8015492: f7f3 f823 bl 80084dc <__aeabi_i2d> 8015496: e9dd 2304 ldrd r2, r3, [sp, #16] 801549a: f7f3 f889 bl 80085b0 <__aeabi_dmul> 801549e: 4602 mov r2, r0 80154a0: 460b mov r3, r1 80154a2: 4620 mov r0, r4 80154a4: 4629 mov r1, r5 80154a6: f7f2 fecb bl 8008240 <__aeabi_dsub> 80154aa: f108 0430 add.w r4, r8, #48 @ 0x30 80154ae: 9d08 ldr r5, [sp, #32] 80154b0: f806 4b01 strb.w r4, [r6], #1 80154b4: eba6 040a sub.w r4, r6, sl 80154b8: 42a5 cmp r5, r4 80154ba: 4602 mov r2, r0 80154bc: 460b mov r3, r1 80154be: d133 bne.n 8015528 <_dtoa_r+0x6e8> 80154c0: f7f2 fec0 bl 8008244 <__adddf3> 80154c4: e9dd 2304 ldrd r2, r3, [sp, #16] 80154c8: 4604 mov r4, r0 80154ca: 460d mov r5, r1 80154cc: f7f3 fb00 bl 8008ad0 <__aeabi_dcmpgt> 80154d0: b9c0 cbnz r0, 8015504 <_dtoa_r+0x6c4> 80154d2: e9dd 2304 ldrd r2, r3, [sp, #16] 80154d6: 4620 mov r0, r4 80154d8: 4629 mov r1, r5 80154da: f7f3 fad1 bl 8008a80 <__aeabi_dcmpeq> 80154de: b110 cbz r0, 80154e6 <_dtoa_r+0x6a6> 80154e0: f018 0f01 tst.w r8, #1 80154e4: d10e bne.n 8015504 <_dtoa_r+0x6c4> 80154e6: 4648 mov r0, r9 80154e8: 9903 ldr r1, [sp, #12] 80154ea: f000 fd73 bl 8015fd4 <_Bfree> 80154ee: 2300 movs r3, #0 80154f0: 7033 strb r3, [r6, #0] 80154f2: 9b22 ldr r3, [sp, #136] @ 0x88 80154f4: 3701 adds r7, #1 80154f6: 601f str r7, [r3, #0] 80154f8: 9b24 ldr r3, [sp, #144] @ 0x90 80154fa: 2b00 cmp r3, #0 80154fc: f000 824b beq.w 8015996 <_dtoa_r+0xb56> 8015500: 601e str r6, [r3, #0] 8015502: e248 b.n 8015996 <_dtoa_r+0xb56> 8015504: 46b8 mov r8, r7 8015506: 4633 mov r3, r6 8015508: 461e mov r6, r3 801550a: f813 2d01 ldrb.w r2, [r3, #-1]! 801550e: 2a39 cmp r2, #57 @ 0x39 8015510: d106 bne.n 8015520 <_dtoa_r+0x6e0> 8015512: 459a cmp sl, r3 8015514: d1f8 bne.n 8015508 <_dtoa_r+0x6c8> 8015516: 2230 movs r2, #48 @ 0x30 8015518: f108 0801 add.w r8, r8, #1 801551c: f88a 2000 strb.w r2, [sl] 8015520: 781a ldrb r2, [r3, #0] 8015522: 3201 adds r2, #1 8015524: 701a strb r2, [r3, #0] 8015526: e7a0 b.n 801546a <_dtoa_r+0x62a> 8015528: 2200 movs r2, #0 801552a: 4b6f ldr r3, [pc, #444] @ (80156e8 <_dtoa_r+0x8a8>) 801552c: f7f3 f840 bl 80085b0 <__aeabi_dmul> 8015530: 2200 movs r2, #0 8015532: 2300 movs r3, #0 8015534: 4604 mov r4, r0 8015536: 460d mov r5, r1 8015538: f7f3 faa2 bl 8008a80 <__aeabi_dcmpeq> 801553c: 2800 cmp r0, #0 801553e: d09f beq.n 8015480 <_dtoa_r+0x640> 8015540: e7d1 b.n 80154e6 <_dtoa_r+0x6a6> 8015542: 9a0b ldr r2, [sp, #44] @ 0x2c 8015544: 2a00 cmp r2, #0 8015546: f000 80ea beq.w 801571e <_dtoa_r+0x8de> 801554a: 9a20 ldr r2, [sp, #128] @ 0x80 801554c: 2a01 cmp r2, #1 801554e: f300 80cd bgt.w 80156ec <_dtoa_r+0x8ac> 8015552: 9a12 ldr r2, [sp, #72] @ 0x48 8015554: 2a00 cmp r2, #0 8015556: f000 80c1 beq.w 80156dc <_dtoa_r+0x89c> 801555a: f203 4333 addw r3, r3, #1075 @ 0x433 801555e: 9c0a ldr r4, [sp, #40] @ 0x28 8015560: 9e04 ldr r6, [sp, #16] 8015562: 9a04 ldr r2, [sp, #16] 8015564: 2101 movs r1, #1 8015566: 441a add r2, r3 8015568: 9204 str r2, [sp, #16] 801556a: 9a09 ldr r2, [sp, #36] @ 0x24 801556c: 4648 mov r0, r9 801556e: 441a add r2, r3 8015570: 9209 str r2, [sp, #36] @ 0x24 8015572: f000 fde3 bl 801613c <__i2b> 8015576: 4605 mov r5, r0 8015578: b166 cbz r6, 8015594 <_dtoa_r+0x754> 801557a: 9b09 ldr r3, [sp, #36] @ 0x24 801557c: 2b00 cmp r3, #0 801557e: dd09 ble.n 8015594 <_dtoa_r+0x754> 8015580: 42b3 cmp r3, r6 8015582: bfa8 it ge 8015584: 4633 movge r3, r6 8015586: 9a04 ldr r2, [sp, #16] 8015588: 1af6 subs r6, r6, r3 801558a: 1ad2 subs r2, r2, r3 801558c: 9204 str r2, [sp, #16] 801558e: 9a09 ldr r2, [sp, #36] @ 0x24 8015590: 1ad3 subs r3, r2, r3 8015592: 9309 str r3, [sp, #36] @ 0x24 8015594: 9b0a ldr r3, [sp, #40] @ 0x28 8015596: b30b cbz r3, 80155dc <_dtoa_r+0x79c> 8015598: 9b0b ldr r3, [sp, #44] @ 0x2c 801559a: 2b00 cmp r3, #0 801559c: f000 80c6 beq.w 801572c <_dtoa_r+0x8ec> 80155a0: 2c00 cmp r4, #0 80155a2: f000 80c0 beq.w 8015726 <_dtoa_r+0x8e6> 80155a6: 4629 mov r1, r5 80155a8: 4622 mov r2, r4 80155aa: 4648 mov r0, r9 80155ac: f000 fe7e bl 80162ac <__pow5mult> 80155b0: 9a03 ldr r2, [sp, #12] 80155b2: 4601 mov r1, r0 80155b4: 4605 mov r5, r0 80155b6: 4648 mov r0, r9 80155b8: f000 fdd6 bl 8016168 <__multiply> 80155bc: 9903 ldr r1, [sp, #12] 80155be: 4680 mov r8, r0 80155c0: 4648 mov r0, r9 80155c2: f000 fd07 bl 8015fd4 <_Bfree> 80155c6: 9b0a ldr r3, [sp, #40] @ 0x28 80155c8: 1b1b subs r3, r3, r4 80155ca: 930a str r3, [sp, #40] @ 0x28 80155cc: f000 80b1 beq.w 8015732 <_dtoa_r+0x8f2> 80155d0: 4641 mov r1, r8 80155d2: 9a0a ldr r2, [sp, #40] @ 0x28 80155d4: 4648 mov r0, r9 80155d6: f000 fe69 bl 80162ac <__pow5mult> 80155da: 9003 str r0, [sp, #12] 80155dc: 2101 movs r1, #1 80155de: 4648 mov r0, r9 80155e0: f000 fdac bl 801613c <__i2b> 80155e4: 9b0e ldr r3, [sp, #56] @ 0x38 80155e6: 4604 mov r4, r0 80155e8: 2b00 cmp r3, #0 80155ea: f000 81d8 beq.w 801599e <_dtoa_r+0xb5e> 80155ee: 461a mov r2, r3 80155f0: 4601 mov r1, r0 80155f2: 4648 mov r0, r9 80155f4: f000 fe5a bl 80162ac <__pow5mult> 80155f8: 9b20 ldr r3, [sp, #128] @ 0x80 80155fa: 4604 mov r4, r0 80155fc: 2b01 cmp r3, #1 80155fe: f300 809f bgt.w 8015740 <_dtoa_r+0x900> 8015602: 9b06 ldr r3, [sp, #24] 8015604: 2b00 cmp r3, #0 8015606: f040 8097 bne.w 8015738 <_dtoa_r+0x8f8> 801560a: 9b07 ldr r3, [sp, #28] 801560c: f3c3 0313 ubfx r3, r3, #0, #20 8015610: 2b00 cmp r3, #0 8015612: f040 8093 bne.w 801573c <_dtoa_r+0x8fc> 8015616: 9b07 ldr r3, [sp, #28] 8015618: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 801561c: 0d1b lsrs r3, r3, #20 801561e: 051b lsls r3, r3, #20 8015620: b133 cbz r3, 8015630 <_dtoa_r+0x7f0> 8015622: 9b04 ldr r3, [sp, #16] 8015624: 3301 adds r3, #1 8015626: 9304 str r3, [sp, #16] 8015628: 9b09 ldr r3, [sp, #36] @ 0x24 801562a: 3301 adds r3, #1 801562c: 9309 str r3, [sp, #36] @ 0x24 801562e: 2301 movs r3, #1 8015630: 930a str r3, [sp, #40] @ 0x28 8015632: 9b0e ldr r3, [sp, #56] @ 0x38 8015634: 2b00 cmp r3, #0 8015636: f000 81b8 beq.w 80159aa <_dtoa_r+0xb6a> 801563a: 6923 ldr r3, [r4, #16] 801563c: eb04 0383 add.w r3, r4, r3, lsl #2 8015640: 6918 ldr r0, [r3, #16] 8015642: f000 fd2f bl 80160a4 <__hi0bits> 8015646: f1c0 0020 rsb r0, r0, #32 801564a: 9b09 ldr r3, [sp, #36] @ 0x24 801564c: 4418 add r0, r3 801564e: f010 001f ands.w r0, r0, #31 8015652: f000 8082 beq.w 801575a <_dtoa_r+0x91a> 8015656: f1c0 0320 rsb r3, r0, #32 801565a: 2b04 cmp r3, #4 801565c: dd73 ble.n 8015746 <_dtoa_r+0x906> 801565e: 9b04 ldr r3, [sp, #16] 8015660: f1c0 001c rsb r0, r0, #28 8015664: 4403 add r3, r0 8015666: 9304 str r3, [sp, #16] 8015668: 9b09 ldr r3, [sp, #36] @ 0x24 801566a: 4406 add r6, r0 801566c: 4403 add r3, r0 801566e: 9309 str r3, [sp, #36] @ 0x24 8015670: 9b04 ldr r3, [sp, #16] 8015672: 2b00 cmp r3, #0 8015674: dd05 ble.n 8015682 <_dtoa_r+0x842> 8015676: 461a mov r2, r3 8015678: 4648 mov r0, r9 801567a: 9903 ldr r1, [sp, #12] 801567c: f000 fe70 bl 8016360 <__lshift> 8015680: 9003 str r0, [sp, #12] 8015682: 9b09 ldr r3, [sp, #36] @ 0x24 8015684: 2b00 cmp r3, #0 8015686: dd05 ble.n 8015694 <_dtoa_r+0x854> 8015688: 4621 mov r1, r4 801568a: 461a mov r2, r3 801568c: 4648 mov r0, r9 801568e: f000 fe67 bl 8016360 <__lshift> 8015692: 4604 mov r4, r0 8015694: 9b0f ldr r3, [sp, #60] @ 0x3c 8015696: 2b00 cmp r3, #0 8015698: d061 beq.n 801575e <_dtoa_r+0x91e> 801569a: 4621 mov r1, r4 801569c: 9803 ldr r0, [sp, #12] 801569e: f000 fecb bl 8016438 <__mcmp> 80156a2: 2800 cmp r0, #0 80156a4: da5b bge.n 801575e <_dtoa_r+0x91e> 80156a6: 2300 movs r3, #0 80156a8: 220a movs r2, #10 80156aa: 4648 mov r0, r9 80156ac: 9903 ldr r1, [sp, #12] 80156ae: f000 fcb3 bl 8016018 <__multadd> 80156b2: 9b0b ldr r3, [sp, #44] @ 0x2c 80156b4: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 80156b8: 9003 str r0, [sp, #12] 80156ba: 2b00 cmp r3, #0 80156bc: f000 8177 beq.w 80159ae <_dtoa_r+0xb6e> 80156c0: 4629 mov r1, r5 80156c2: 2300 movs r3, #0 80156c4: 220a movs r2, #10 80156c6: 4648 mov r0, r9 80156c8: f000 fca6 bl 8016018 <__multadd> 80156cc: f1bb 0f00 cmp.w fp, #0 80156d0: 4605 mov r5, r0 80156d2: dc6f bgt.n 80157b4 <_dtoa_r+0x974> 80156d4: 9b20 ldr r3, [sp, #128] @ 0x80 80156d6: 2b02 cmp r3, #2 80156d8: dc49 bgt.n 801576e <_dtoa_r+0x92e> 80156da: e06b b.n 80157b4 <_dtoa_r+0x974> 80156dc: 9b14 ldr r3, [sp, #80] @ 0x50 80156de: f1c3 0336 rsb r3, r3, #54 @ 0x36 80156e2: e73c b.n 801555e <_dtoa_r+0x71e> 80156e4: 3fe00000 .word 0x3fe00000 80156e8: 40240000 .word 0x40240000 80156ec: 9b08 ldr r3, [sp, #32] 80156ee: 1e5c subs r4, r3, #1 80156f0: 9b0a ldr r3, [sp, #40] @ 0x28 80156f2: 42a3 cmp r3, r4 80156f4: db09 blt.n 801570a <_dtoa_r+0x8ca> 80156f6: 1b1c subs r4, r3, r4 80156f8: 9b08 ldr r3, [sp, #32] 80156fa: 2b00 cmp r3, #0 80156fc: f6bf af30 bge.w 8015560 <_dtoa_r+0x720> 8015700: 9b04 ldr r3, [sp, #16] 8015702: 9a08 ldr r2, [sp, #32] 8015704: 1a9e subs r6, r3, r2 8015706: 2300 movs r3, #0 8015708: e72b b.n 8015562 <_dtoa_r+0x722> 801570a: 9b0a ldr r3, [sp, #40] @ 0x28 801570c: 9a0e ldr r2, [sp, #56] @ 0x38 801570e: 1ae3 subs r3, r4, r3 8015710: 441a add r2, r3 8015712: 940a str r4, [sp, #40] @ 0x28 8015714: 9e04 ldr r6, [sp, #16] 8015716: 2400 movs r4, #0 8015718: 9b08 ldr r3, [sp, #32] 801571a: 920e str r2, [sp, #56] @ 0x38 801571c: e721 b.n 8015562 <_dtoa_r+0x722> 801571e: 9c0a ldr r4, [sp, #40] @ 0x28 8015720: 9e04 ldr r6, [sp, #16] 8015722: 9d0b ldr r5, [sp, #44] @ 0x2c 8015724: e728 b.n 8015578 <_dtoa_r+0x738> 8015726: f8dd 800c ldr.w r8, [sp, #12] 801572a: e751 b.n 80155d0 <_dtoa_r+0x790> 801572c: 9a0a ldr r2, [sp, #40] @ 0x28 801572e: 9903 ldr r1, [sp, #12] 8015730: e750 b.n 80155d4 <_dtoa_r+0x794> 8015732: f8cd 800c str.w r8, [sp, #12] 8015736: e751 b.n 80155dc <_dtoa_r+0x79c> 8015738: 2300 movs r3, #0 801573a: e779 b.n 8015630 <_dtoa_r+0x7f0> 801573c: 9b06 ldr r3, [sp, #24] 801573e: e777 b.n 8015630 <_dtoa_r+0x7f0> 8015740: 2300 movs r3, #0 8015742: 930a str r3, [sp, #40] @ 0x28 8015744: e779 b.n 801563a <_dtoa_r+0x7fa> 8015746: d093 beq.n 8015670 <_dtoa_r+0x830> 8015748: 9a04 ldr r2, [sp, #16] 801574a: 331c adds r3, #28 801574c: 441a add r2, r3 801574e: 9204 str r2, [sp, #16] 8015750: 9a09 ldr r2, [sp, #36] @ 0x24 8015752: 441e add r6, r3 8015754: 441a add r2, r3 8015756: 9209 str r2, [sp, #36] @ 0x24 8015758: e78a b.n 8015670 <_dtoa_r+0x830> 801575a: 4603 mov r3, r0 801575c: e7f4 b.n 8015748 <_dtoa_r+0x908> 801575e: 9b08 ldr r3, [sp, #32] 8015760: 46b8 mov r8, r7 8015762: 2b00 cmp r3, #0 8015764: dc20 bgt.n 80157a8 <_dtoa_r+0x968> 8015766: 469b mov fp, r3 8015768: 9b20 ldr r3, [sp, #128] @ 0x80 801576a: 2b02 cmp r3, #2 801576c: dd1e ble.n 80157ac <_dtoa_r+0x96c> 801576e: f1bb 0f00 cmp.w fp, #0 8015772: f47f adb1 bne.w 80152d8 <_dtoa_r+0x498> 8015776: 4621 mov r1, r4 8015778: 465b mov r3, fp 801577a: 2205 movs r2, #5 801577c: 4648 mov r0, r9 801577e: f000 fc4b bl 8016018 <__multadd> 8015782: 4601 mov r1, r0 8015784: 4604 mov r4, r0 8015786: 9803 ldr r0, [sp, #12] 8015788: f000 fe56 bl 8016438 <__mcmp> 801578c: 2800 cmp r0, #0 801578e: f77f ada3 ble.w 80152d8 <_dtoa_r+0x498> 8015792: 4656 mov r6, sl 8015794: 2331 movs r3, #49 @ 0x31 8015796: f108 0801 add.w r8, r8, #1 801579a: f806 3b01 strb.w r3, [r6], #1 801579e: e59f b.n 80152e0 <_dtoa_r+0x4a0> 80157a0: 46b8 mov r8, r7 80157a2: 9c08 ldr r4, [sp, #32] 80157a4: 4625 mov r5, r4 80157a6: e7f4 b.n 8015792 <_dtoa_r+0x952> 80157a8: f8dd b020 ldr.w fp, [sp, #32] 80157ac: 9b0b ldr r3, [sp, #44] @ 0x2c 80157ae: 2b00 cmp r3, #0 80157b0: f000 8101 beq.w 80159b6 <_dtoa_r+0xb76> 80157b4: 2e00 cmp r6, #0 80157b6: dd05 ble.n 80157c4 <_dtoa_r+0x984> 80157b8: 4629 mov r1, r5 80157ba: 4632 mov r2, r6 80157bc: 4648 mov r0, r9 80157be: f000 fdcf bl 8016360 <__lshift> 80157c2: 4605 mov r5, r0 80157c4: 9b0a ldr r3, [sp, #40] @ 0x28 80157c6: 2b00 cmp r3, #0 80157c8: d05c beq.n 8015884 <_dtoa_r+0xa44> 80157ca: 4648 mov r0, r9 80157cc: 6869 ldr r1, [r5, #4] 80157ce: f000 fbc1 bl 8015f54 <_Balloc> 80157d2: 4606 mov r6, r0 80157d4: b928 cbnz r0, 80157e2 <_dtoa_r+0x9a2> 80157d6: 4602 mov r2, r0 80157d8: f240 21ef movw r1, #751 @ 0x2ef 80157dc: 4b80 ldr r3, [pc, #512] @ (80159e0 <_dtoa_r+0xba0>) 80157de: f7ff bb43 b.w 8014e68 <_dtoa_r+0x28> 80157e2: 692a ldr r2, [r5, #16] 80157e4: f105 010c add.w r1, r5, #12 80157e8: 3202 adds r2, #2 80157ea: 0092 lsls r2, r2, #2 80157ec: 300c adds r0, #12 80157ee: f7ff fa73 bl 8014cd8 80157f2: 2201 movs r2, #1 80157f4: 4631 mov r1, r6 80157f6: 4648 mov r0, r9 80157f8: f000 fdb2 bl 8016360 <__lshift> 80157fc: 462f mov r7, r5 80157fe: 4605 mov r5, r0 8015800: f10a 0301 add.w r3, sl, #1 8015804: 9304 str r3, [sp, #16] 8015806: eb0a 030b add.w r3, sl, fp 801580a: 930a str r3, [sp, #40] @ 0x28 801580c: 9b06 ldr r3, [sp, #24] 801580e: f003 0301 and.w r3, r3, #1 8015812: 9309 str r3, [sp, #36] @ 0x24 8015814: 9b04 ldr r3, [sp, #16] 8015816: 4621 mov r1, r4 8015818: 9803 ldr r0, [sp, #12] 801581a: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff 801581e: f7ff fa87 bl 8014d30 8015822: 4603 mov r3, r0 8015824: 4639 mov r1, r7 8015826: 3330 adds r3, #48 @ 0x30 8015828: 9006 str r0, [sp, #24] 801582a: 9803 ldr r0, [sp, #12] 801582c: 930b str r3, [sp, #44] @ 0x2c 801582e: f000 fe03 bl 8016438 <__mcmp> 8015832: 462a mov r2, r5 8015834: 9008 str r0, [sp, #32] 8015836: 4621 mov r1, r4 8015838: 4648 mov r0, r9 801583a: f000 fe19 bl 8016470 <__mdiff> 801583e: 68c2 ldr r2, [r0, #12] 8015840: 4606 mov r6, r0 8015842: 9b0b ldr r3, [sp, #44] @ 0x2c 8015844: bb02 cbnz r2, 8015888 <_dtoa_r+0xa48> 8015846: 4601 mov r1, r0 8015848: 9803 ldr r0, [sp, #12] 801584a: f000 fdf5 bl 8016438 <__mcmp> 801584e: 4602 mov r2, r0 8015850: 9b0b ldr r3, [sp, #44] @ 0x2c 8015852: 4631 mov r1, r6 8015854: 4648 mov r0, r9 8015856: e9cd 320b strd r3, r2, [sp, #44] @ 0x2c 801585a: f000 fbbb bl 8015fd4 <_Bfree> 801585e: 9b20 ldr r3, [sp, #128] @ 0x80 8015860: 9a0c ldr r2, [sp, #48] @ 0x30 8015862: 9e04 ldr r6, [sp, #16] 8015864: ea42 0103 orr.w r1, r2, r3 8015868: 9b09 ldr r3, [sp, #36] @ 0x24 801586a: 4319 orrs r1, r3 801586c: 9b0b ldr r3, [sp, #44] @ 0x2c 801586e: d10d bne.n 801588c <_dtoa_r+0xa4c> 8015870: 2b39 cmp r3, #57 @ 0x39 8015872: d027 beq.n 80158c4 <_dtoa_r+0xa84> 8015874: 9a08 ldr r2, [sp, #32] 8015876: 2a00 cmp r2, #0 8015878: dd01 ble.n 801587e <_dtoa_r+0xa3e> 801587a: 9b06 ldr r3, [sp, #24] 801587c: 3331 adds r3, #49 @ 0x31 801587e: f88b 3000 strb.w r3, [fp] 8015882: e52e b.n 80152e2 <_dtoa_r+0x4a2> 8015884: 4628 mov r0, r5 8015886: e7b9 b.n 80157fc <_dtoa_r+0x9bc> 8015888: 2201 movs r2, #1 801588a: e7e2 b.n 8015852 <_dtoa_r+0xa12> 801588c: 9908 ldr r1, [sp, #32] 801588e: 2900 cmp r1, #0 8015890: db04 blt.n 801589c <_dtoa_r+0xa5c> 8015892: 9820 ldr r0, [sp, #128] @ 0x80 8015894: 4301 orrs r1, r0 8015896: 9809 ldr r0, [sp, #36] @ 0x24 8015898: 4301 orrs r1, r0 801589a: d120 bne.n 80158de <_dtoa_r+0xa9e> 801589c: 2a00 cmp r2, #0 801589e: ddee ble.n 801587e <_dtoa_r+0xa3e> 80158a0: 2201 movs r2, #1 80158a2: 9903 ldr r1, [sp, #12] 80158a4: 4648 mov r0, r9 80158a6: 9304 str r3, [sp, #16] 80158a8: f000 fd5a bl 8016360 <__lshift> 80158ac: 4621 mov r1, r4 80158ae: 9003 str r0, [sp, #12] 80158b0: f000 fdc2 bl 8016438 <__mcmp> 80158b4: 2800 cmp r0, #0 80158b6: 9b04 ldr r3, [sp, #16] 80158b8: dc02 bgt.n 80158c0 <_dtoa_r+0xa80> 80158ba: d1e0 bne.n 801587e <_dtoa_r+0xa3e> 80158bc: 07da lsls r2, r3, #31 80158be: d5de bpl.n 801587e <_dtoa_r+0xa3e> 80158c0: 2b39 cmp r3, #57 @ 0x39 80158c2: d1da bne.n 801587a <_dtoa_r+0xa3a> 80158c4: 2339 movs r3, #57 @ 0x39 80158c6: f88b 3000 strb.w r3, [fp] 80158ca: 4633 mov r3, r6 80158cc: 461e mov r6, r3 80158ce: f816 2c01 ldrb.w r2, [r6, #-1] 80158d2: 3b01 subs r3, #1 80158d4: 2a39 cmp r2, #57 @ 0x39 80158d6: d04e beq.n 8015976 <_dtoa_r+0xb36> 80158d8: 3201 adds r2, #1 80158da: 701a strb r2, [r3, #0] 80158dc: e501 b.n 80152e2 <_dtoa_r+0x4a2> 80158de: 2a00 cmp r2, #0 80158e0: dd03 ble.n 80158ea <_dtoa_r+0xaaa> 80158e2: 2b39 cmp r3, #57 @ 0x39 80158e4: d0ee beq.n 80158c4 <_dtoa_r+0xa84> 80158e6: 3301 adds r3, #1 80158e8: e7c9 b.n 801587e <_dtoa_r+0xa3e> 80158ea: 9a04 ldr r2, [sp, #16] 80158ec: 990a ldr r1, [sp, #40] @ 0x28 80158ee: f802 3c01 strb.w r3, [r2, #-1] 80158f2: 428a cmp r2, r1 80158f4: d028 beq.n 8015948 <_dtoa_r+0xb08> 80158f6: 2300 movs r3, #0 80158f8: 220a movs r2, #10 80158fa: 9903 ldr r1, [sp, #12] 80158fc: 4648 mov r0, r9 80158fe: f000 fb8b bl 8016018 <__multadd> 8015902: 42af cmp r7, r5 8015904: 9003 str r0, [sp, #12] 8015906: f04f 0300 mov.w r3, #0 801590a: f04f 020a mov.w r2, #10 801590e: 4639 mov r1, r7 8015910: 4648 mov r0, r9 8015912: d107 bne.n 8015924 <_dtoa_r+0xae4> 8015914: f000 fb80 bl 8016018 <__multadd> 8015918: 4607 mov r7, r0 801591a: 4605 mov r5, r0 801591c: 9b04 ldr r3, [sp, #16] 801591e: 3301 adds r3, #1 8015920: 9304 str r3, [sp, #16] 8015922: e777 b.n 8015814 <_dtoa_r+0x9d4> 8015924: f000 fb78 bl 8016018 <__multadd> 8015928: 4629 mov r1, r5 801592a: 4607 mov r7, r0 801592c: 2300 movs r3, #0 801592e: 220a movs r2, #10 8015930: 4648 mov r0, r9 8015932: f000 fb71 bl 8016018 <__multadd> 8015936: 4605 mov r5, r0 8015938: e7f0 b.n 801591c <_dtoa_r+0xadc> 801593a: f1bb 0f00 cmp.w fp, #0 801593e: bfcc ite gt 8015940: 465e movgt r6, fp 8015942: 2601 movle r6, #1 8015944: 2700 movs r7, #0 8015946: 4456 add r6, sl 8015948: 2201 movs r2, #1 801594a: 9903 ldr r1, [sp, #12] 801594c: 4648 mov r0, r9 801594e: 9304 str r3, [sp, #16] 8015950: f000 fd06 bl 8016360 <__lshift> 8015954: 4621 mov r1, r4 8015956: 9003 str r0, [sp, #12] 8015958: f000 fd6e bl 8016438 <__mcmp> 801595c: 2800 cmp r0, #0 801595e: dcb4 bgt.n 80158ca <_dtoa_r+0xa8a> 8015960: d102 bne.n 8015968 <_dtoa_r+0xb28> 8015962: 9b04 ldr r3, [sp, #16] 8015964: 07db lsls r3, r3, #31 8015966: d4b0 bmi.n 80158ca <_dtoa_r+0xa8a> 8015968: 4633 mov r3, r6 801596a: 461e mov r6, r3 801596c: f813 2d01 ldrb.w r2, [r3, #-1]! 8015970: 2a30 cmp r2, #48 @ 0x30 8015972: d0fa beq.n 801596a <_dtoa_r+0xb2a> 8015974: e4b5 b.n 80152e2 <_dtoa_r+0x4a2> 8015976: 459a cmp sl, r3 8015978: d1a8 bne.n 80158cc <_dtoa_r+0xa8c> 801597a: 2331 movs r3, #49 @ 0x31 801597c: f108 0801 add.w r8, r8, #1 8015980: f88a 3000 strb.w r3, [sl] 8015984: e4ad b.n 80152e2 <_dtoa_r+0x4a2> 8015986: 9b24 ldr r3, [sp, #144] @ 0x90 8015988: f8df a058 ldr.w sl, [pc, #88] @ 80159e4 <_dtoa_r+0xba4> 801598c: b11b cbz r3, 8015996 <_dtoa_r+0xb56> 801598e: f10a 0308 add.w r3, sl, #8 8015992: 9a24 ldr r2, [sp, #144] @ 0x90 8015994: 6013 str r3, [r2, #0] 8015996: 4650 mov r0, sl 8015998: b017 add sp, #92 @ 0x5c 801599a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801599e: 9b20 ldr r3, [sp, #128] @ 0x80 80159a0: 2b01 cmp r3, #1 80159a2: f77f ae2e ble.w 8015602 <_dtoa_r+0x7c2> 80159a6: 9b0e ldr r3, [sp, #56] @ 0x38 80159a8: 930a str r3, [sp, #40] @ 0x28 80159aa: 2001 movs r0, #1 80159ac: e64d b.n 801564a <_dtoa_r+0x80a> 80159ae: f1bb 0f00 cmp.w fp, #0 80159b2: f77f aed9 ble.w 8015768 <_dtoa_r+0x928> 80159b6: 4656 mov r6, sl 80159b8: 4621 mov r1, r4 80159ba: 9803 ldr r0, [sp, #12] 80159bc: f7ff f9b8 bl 8014d30 80159c0: f100 0330 add.w r3, r0, #48 @ 0x30 80159c4: f806 3b01 strb.w r3, [r6], #1 80159c8: eba6 020a sub.w r2, r6, sl 80159cc: 4593 cmp fp, r2 80159ce: ddb4 ble.n 801593a <_dtoa_r+0xafa> 80159d0: 2300 movs r3, #0 80159d2: 220a movs r2, #10 80159d4: 4648 mov r0, r9 80159d6: 9903 ldr r1, [sp, #12] 80159d8: f000 fb1e bl 8016018 <__multadd> 80159dc: 9003 str r0, [sp, #12] 80159de: e7eb b.n 80159b8 <_dtoa_r+0xb78> 80159e0: 080179d8 .word 0x080179d8 80159e4: 0801795c .word 0x0801795c 080159e8 <__ssputs_r>: 80159e8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80159ec: 461f mov r7, r3 80159ee: 688e ldr r6, [r1, #8] 80159f0: 4682 mov sl, r0 80159f2: 42be cmp r6, r7 80159f4: 460c mov r4, r1 80159f6: 4690 mov r8, r2 80159f8: 680b ldr r3, [r1, #0] 80159fa: d82d bhi.n 8015a58 <__ssputs_r+0x70> 80159fc: f9b1 200c ldrsh.w r2, [r1, #12] 8015a00: f412 6f90 tst.w r2, #1152 @ 0x480 8015a04: d026 beq.n 8015a54 <__ssputs_r+0x6c> 8015a06: 6965 ldr r5, [r4, #20] 8015a08: 6909 ldr r1, [r1, #16] 8015a0a: eb05 0545 add.w r5, r5, r5, lsl #1 8015a0e: eba3 0901 sub.w r9, r3, r1 8015a12: eb05 75d5 add.w r5, r5, r5, lsr #31 8015a16: 1c7b adds r3, r7, #1 8015a18: 444b add r3, r9 8015a1a: 106d asrs r5, r5, #1 8015a1c: 429d cmp r5, r3 8015a1e: bf38 it cc 8015a20: 461d movcc r5, r3 8015a22: 0553 lsls r3, r2, #21 8015a24: d527 bpl.n 8015a76 <__ssputs_r+0x8e> 8015a26: 4629 mov r1, r5 8015a28: f000 f960 bl 8015cec <_malloc_r> 8015a2c: 4606 mov r6, r0 8015a2e: b360 cbz r0, 8015a8a <__ssputs_r+0xa2> 8015a30: 464a mov r2, r9 8015a32: 6921 ldr r1, [r4, #16] 8015a34: f7ff f950 bl 8014cd8 8015a38: 89a3 ldrh r3, [r4, #12] 8015a3a: f423 6390 bic.w r3, r3, #1152 @ 0x480 8015a3e: f043 0380 orr.w r3, r3, #128 @ 0x80 8015a42: 81a3 strh r3, [r4, #12] 8015a44: 6126 str r6, [r4, #16] 8015a46: 444e add r6, r9 8015a48: 6026 str r6, [r4, #0] 8015a4a: 463e mov r6, r7 8015a4c: 6165 str r5, [r4, #20] 8015a4e: eba5 0509 sub.w r5, r5, r9 8015a52: 60a5 str r5, [r4, #8] 8015a54: 42be cmp r6, r7 8015a56: d900 bls.n 8015a5a <__ssputs_r+0x72> 8015a58: 463e mov r6, r7 8015a5a: 4632 mov r2, r6 8015a5c: 4641 mov r1, r8 8015a5e: 6820 ldr r0, [r4, #0] 8015a60: f000 fe76 bl 8016750 8015a64: 2000 movs r0, #0 8015a66: 68a3 ldr r3, [r4, #8] 8015a68: 1b9b subs r3, r3, r6 8015a6a: 60a3 str r3, [r4, #8] 8015a6c: 6823 ldr r3, [r4, #0] 8015a6e: 4433 add r3, r6 8015a70: 6023 str r3, [r4, #0] 8015a72: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8015a76: 462a mov r2, r5 8015a78: f000 fe3c bl 80166f4 <_realloc_r> 8015a7c: 4606 mov r6, r0 8015a7e: 2800 cmp r0, #0 8015a80: d1e0 bne.n 8015a44 <__ssputs_r+0x5c> 8015a82: 4650 mov r0, sl 8015a84: 6921 ldr r1, [r4, #16] 8015a86: f000 feef bl 8016868 <_free_r> 8015a8a: 230c movs r3, #12 8015a8c: f8ca 3000 str.w r3, [sl] 8015a90: 89a3 ldrh r3, [r4, #12] 8015a92: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015a96: f043 0340 orr.w r3, r3, #64 @ 0x40 8015a9a: 81a3 strh r3, [r4, #12] 8015a9c: e7e9 b.n 8015a72 <__ssputs_r+0x8a> ... 08015aa0 <_svfiprintf_r>: 8015aa0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8015aa4: 4698 mov r8, r3 8015aa6: 898b ldrh r3, [r1, #12] 8015aa8: 4607 mov r7, r0 8015aaa: 061b lsls r3, r3, #24 8015aac: 460d mov r5, r1 8015aae: 4614 mov r4, r2 8015ab0: b09d sub sp, #116 @ 0x74 8015ab2: d510 bpl.n 8015ad6 <_svfiprintf_r+0x36> 8015ab4: 690b ldr r3, [r1, #16] 8015ab6: b973 cbnz r3, 8015ad6 <_svfiprintf_r+0x36> 8015ab8: 2140 movs r1, #64 @ 0x40 8015aba: f000 f917 bl 8015cec <_malloc_r> 8015abe: 6028 str r0, [r5, #0] 8015ac0: 6128 str r0, [r5, #16] 8015ac2: b930 cbnz r0, 8015ad2 <_svfiprintf_r+0x32> 8015ac4: 230c movs r3, #12 8015ac6: 603b str r3, [r7, #0] 8015ac8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015acc: b01d add sp, #116 @ 0x74 8015ace: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8015ad2: 2340 movs r3, #64 @ 0x40 8015ad4: 616b str r3, [r5, #20] 8015ad6: 2300 movs r3, #0 8015ad8: 9309 str r3, [sp, #36] @ 0x24 8015ada: 2320 movs r3, #32 8015adc: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8015ae0: 2330 movs r3, #48 @ 0x30 8015ae2: f04f 0901 mov.w r9, #1 8015ae6: f8cd 800c str.w r8, [sp, #12] 8015aea: f8df 8198 ldr.w r8, [pc, #408] @ 8015c84 <_svfiprintf_r+0x1e4> 8015aee: f88d 302a strb.w r3, [sp, #42] @ 0x2a 8015af2: 4623 mov r3, r4 8015af4: 469a mov sl, r3 8015af6: f813 2b01 ldrb.w r2, [r3], #1 8015afa: b10a cbz r2, 8015b00 <_svfiprintf_r+0x60> 8015afc: 2a25 cmp r2, #37 @ 0x25 8015afe: d1f9 bne.n 8015af4 <_svfiprintf_r+0x54> 8015b00: ebba 0b04 subs.w fp, sl, r4 8015b04: d00b beq.n 8015b1e <_svfiprintf_r+0x7e> 8015b06: 465b mov r3, fp 8015b08: 4622 mov r2, r4 8015b0a: 4629 mov r1, r5 8015b0c: 4638 mov r0, r7 8015b0e: f7ff ff6b bl 80159e8 <__ssputs_r> 8015b12: 3001 adds r0, #1 8015b14: f000 80a7 beq.w 8015c66 <_svfiprintf_r+0x1c6> 8015b18: 9a09 ldr r2, [sp, #36] @ 0x24 8015b1a: 445a add r2, fp 8015b1c: 9209 str r2, [sp, #36] @ 0x24 8015b1e: f89a 3000 ldrb.w r3, [sl] 8015b22: 2b00 cmp r3, #0 8015b24: f000 809f beq.w 8015c66 <_svfiprintf_r+0x1c6> 8015b28: 2300 movs r3, #0 8015b2a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8015b2e: e9cd 2305 strd r2, r3, [sp, #20] 8015b32: f10a 0a01 add.w sl, sl, #1 8015b36: 9304 str r3, [sp, #16] 8015b38: 9307 str r3, [sp, #28] 8015b3a: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8015b3e: 931a str r3, [sp, #104] @ 0x68 8015b40: 4654 mov r4, sl 8015b42: 2205 movs r2, #5 8015b44: f814 1b01 ldrb.w r1, [r4], #1 8015b48: 484e ldr r0, [pc, #312] @ (8015c84 <_svfiprintf_r+0x1e4>) 8015b4a: f7ff f8b7 bl 8014cbc 8015b4e: 9a04 ldr r2, [sp, #16] 8015b50: b9d8 cbnz r0, 8015b8a <_svfiprintf_r+0xea> 8015b52: 06d0 lsls r0, r2, #27 8015b54: bf44 itt mi 8015b56: 2320 movmi r3, #32 8015b58: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8015b5c: 0711 lsls r1, r2, #28 8015b5e: bf44 itt mi 8015b60: 232b movmi r3, #43 @ 0x2b 8015b62: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8015b66: f89a 3000 ldrb.w r3, [sl] 8015b6a: 2b2a cmp r3, #42 @ 0x2a 8015b6c: d015 beq.n 8015b9a <_svfiprintf_r+0xfa> 8015b6e: 4654 mov r4, sl 8015b70: 2000 movs r0, #0 8015b72: f04f 0c0a mov.w ip, #10 8015b76: 9a07 ldr r2, [sp, #28] 8015b78: 4621 mov r1, r4 8015b7a: f811 3b01 ldrb.w r3, [r1], #1 8015b7e: 3b30 subs r3, #48 @ 0x30 8015b80: 2b09 cmp r3, #9 8015b82: d94b bls.n 8015c1c <_svfiprintf_r+0x17c> 8015b84: b1b0 cbz r0, 8015bb4 <_svfiprintf_r+0x114> 8015b86: 9207 str r2, [sp, #28] 8015b88: e014 b.n 8015bb4 <_svfiprintf_r+0x114> 8015b8a: eba0 0308 sub.w r3, r0, r8 8015b8e: fa09 f303 lsl.w r3, r9, r3 8015b92: 4313 orrs r3, r2 8015b94: 46a2 mov sl, r4 8015b96: 9304 str r3, [sp, #16] 8015b98: e7d2 b.n 8015b40 <_svfiprintf_r+0xa0> 8015b9a: 9b03 ldr r3, [sp, #12] 8015b9c: 1d19 adds r1, r3, #4 8015b9e: 681b ldr r3, [r3, #0] 8015ba0: 9103 str r1, [sp, #12] 8015ba2: 2b00 cmp r3, #0 8015ba4: bfbb ittet lt 8015ba6: 425b neglt r3, r3 8015ba8: f042 0202 orrlt.w r2, r2, #2 8015bac: 9307 strge r3, [sp, #28] 8015bae: 9307 strlt r3, [sp, #28] 8015bb0: bfb8 it lt 8015bb2: 9204 strlt r2, [sp, #16] 8015bb4: 7823 ldrb r3, [r4, #0] 8015bb6: 2b2e cmp r3, #46 @ 0x2e 8015bb8: d10a bne.n 8015bd0 <_svfiprintf_r+0x130> 8015bba: 7863 ldrb r3, [r4, #1] 8015bbc: 2b2a cmp r3, #42 @ 0x2a 8015bbe: d132 bne.n 8015c26 <_svfiprintf_r+0x186> 8015bc0: 9b03 ldr r3, [sp, #12] 8015bc2: 3402 adds r4, #2 8015bc4: 1d1a adds r2, r3, #4 8015bc6: 681b ldr r3, [r3, #0] 8015bc8: 9203 str r2, [sp, #12] 8015bca: ea43 73e3 orr.w r3, r3, r3, asr #31 8015bce: 9305 str r3, [sp, #20] 8015bd0: f8df a0b4 ldr.w sl, [pc, #180] @ 8015c88 <_svfiprintf_r+0x1e8> 8015bd4: 2203 movs r2, #3 8015bd6: 4650 mov r0, sl 8015bd8: 7821 ldrb r1, [r4, #0] 8015bda: f7ff f86f bl 8014cbc 8015bde: b138 cbz r0, 8015bf0 <_svfiprintf_r+0x150> 8015be0: 2240 movs r2, #64 @ 0x40 8015be2: 9b04 ldr r3, [sp, #16] 8015be4: eba0 000a sub.w r0, r0, sl 8015be8: 4082 lsls r2, r0 8015bea: 4313 orrs r3, r2 8015bec: 3401 adds r4, #1 8015bee: 9304 str r3, [sp, #16] 8015bf0: f814 1b01 ldrb.w r1, [r4], #1 8015bf4: 2206 movs r2, #6 8015bf6: 4825 ldr r0, [pc, #148] @ (8015c8c <_svfiprintf_r+0x1ec>) 8015bf8: f88d 1028 strb.w r1, [sp, #40] @ 0x28 8015bfc: f7ff f85e bl 8014cbc 8015c00: 2800 cmp r0, #0 8015c02: d036 beq.n 8015c72 <_svfiprintf_r+0x1d2> 8015c04: 4b22 ldr r3, [pc, #136] @ (8015c90 <_svfiprintf_r+0x1f0>) 8015c06: bb1b cbnz r3, 8015c50 <_svfiprintf_r+0x1b0> 8015c08: 9b03 ldr r3, [sp, #12] 8015c0a: 3307 adds r3, #7 8015c0c: f023 0307 bic.w r3, r3, #7 8015c10: 3308 adds r3, #8 8015c12: 9303 str r3, [sp, #12] 8015c14: 9b09 ldr r3, [sp, #36] @ 0x24 8015c16: 4433 add r3, r6 8015c18: 9309 str r3, [sp, #36] @ 0x24 8015c1a: e76a b.n 8015af2 <_svfiprintf_r+0x52> 8015c1c: 460c mov r4, r1 8015c1e: 2001 movs r0, #1 8015c20: fb0c 3202 mla r2, ip, r2, r3 8015c24: e7a8 b.n 8015b78 <_svfiprintf_r+0xd8> 8015c26: 2300 movs r3, #0 8015c28: f04f 0c0a mov.w ip, #10 8015c2c: 4619 mov r1, r3 8015c2e: 3401 adds r4, #1 8015c30: 9305 str r3, [sp, #20] 8015c32: 4620 mov r0, r4 8015c34: f810 2b01 ldrb.w r2, [r0], #1 8015c38: 3a30 subs r2, #48 @ 0x30 8015c3a: 2a09 cmp r2, #9 8015c3c: d903 bls.n 8015c46 <_svfiprintf_r+0x1a6> 8015c3e: 2b00 cmp r3, #0 8015c40: d0c6 beq.n 8015bd0 <_svfiprintf_r+0x130> 8015c42: 9105 str r1, [sp, #20] 8015c44: e7c4 b.n 8015bd0 <_svfiprintf_r+0x130> 8015c46: 4604 mov r4, r0 8015c48: 2301 movs r3, #1 8015c4a: fb0c 2101 mla r1, ip, r1, r2 8015c4e: e7f0 b.n 8015c32 <_svfiprintf_r+0x192> 8015c50: ab03 add r3, sp, #12 8015c52: 9300 str r3, [sp, #0] 8015c54: 462a mov r2, r5 8015c56: 4638 mov r0, r7 8015c58: 4b0e ldr r3, [pc, #56] @ (8015c94 <_svfiprintf_r+0x1f4>) 8015c5a: a904 add r1, sp, #16 8015c5c: f7fe fb3a bl 80142d4 <_printf_float> 8015c60: 1c42 adds r2, r0, #1 8015c62: 4606 mov r6, r0 8015c64: d1d6 bne.n 8015c14 <_svfiprintf_r+0x174> 8015c66: 89ab ldrh r3, [r5, #12] 8015c68: 065b lsls r3, r3, #25 8015c6a: f53f af2d bmi.w 8015ac8 <_svfiprintf_r+0x28> 8015c6e: 9809 ldr r0, [sp, #36] @ 0x24 8015c70: e72c b.n 8015acc <_svfiprintf_r+0x2c> 8015c72: ab03 add r3, sp, #12 8015c74: 9300 str r3, [sp, #0] 8015c76: 462a mov r2, r5 8015c78: 4638 mov r0, r7 8015c7a: 4b06 ldr r3, [pc, #24] @ (8015c94 <_svfiprintf_r+0x1f4>) 8015c7c: a904 add r1, sp, #16 8015c7e: f7fe fdc7 bl 8014810 <_printf_i> 8015c82: e7ed b.n 8015c60 <_svfiprintf_r+0x1c0> 8015c84: 080179e9 .word 0x080179e9 8015c88: 080179ef .word 0x080179ef 8015c8c: 080179f3 .word 0x080179f3 8015c90: 080142d5 .word 0x080142d5 8015c94: 080159e9 .word 0x080159e9 08015c98 : 8015c98: 4b02 ldr r3, [pc, #8] @ (8015ca4 ) 8015c9a: 4601 mov r1, r0 8015c9c: 6818 ldr r0, [r3, #0] 8015c9e: f000 b825 b.w 8015cec <_malloc_r> 8015ca2: bf00 nop 8015ca4: 2000009c .word 0x2000009c 08015ca8 : 8015ca8: b570 push {r4, r5, r6, lr} 8015caa: 4e0f ldr r6, [pc, #60] @ (8015ce8 ) 8015cac: 460c mov r4, r1 8015cae: 6831 ldr r1, [r6, #0] 8015cb0: 4605 mov r5, r0 8015cb2: b911 cbnz r1, 8015cba 8015cb4: f000 fd8a bl 80167cc <_sbrk_r> 8015cb8: 6030 str r0, [r6, #0] 8015cba: 4621 mov r1, r4 8015cbc: 4628 mov r0, r5 8015cbe: f000 fd85 bl 80167cc <_sbrk_r> 8015cc2: 1c43 adds r3, r0, #1 8015cc4: d103 bne.n 8015cce 8015cc6: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 8015cca: 4620 mov r0, r4 8015ccc: bd70 pop {r4, r5, r6, pc} 8015cce: 1cc4 adds r4, r0, #3 8015cd0: f024 0403 bic.w r4, r4, #3 8015cd4: 42a0 cmp r0, r4 8015cd6: d0f8 beq.n 8015cca 8015cd8: 1a21 subs r1, r4, r0 8015cda: 4628 mov r0, r5 8015cdc: f000 fd76 bl 80167cc <_sbrk_r> 8015ce0: 3001 adds r0, #1 8015ce2: d1f2 bne.n 8015cca 8015ce4: e7ef b.n 8015cc6 8015ce6: bf00 nop 8015ce8: 200015cc .word 0x200015cc 08015cec <_malloc_r>: 8015cec: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8015cf0: 1ccd adds r5, r1, #3 8015cf2: f025 0503 bic.w r5, r5, #3 8015cf6: 3508 adds r5, #8 8015cf8: 2d0c cmp r5, #12 8015cfa: bf38 it cc 8015cfc: 250c movcc r5, #12 8015cfe: 2d00 cmp r5, #0 8015d00: 4606 mov r6, r0 8015d02: db01 blt.n 8015d08 <_malloc_r+0x1c> 8015d04: 42a9 cmp r1, r5 8015d06: d904 bls.n 8015d12 <_malloc_r+0x26> 8015d08: 230c movs r3, #12 8015d0a: 6033 str r3, [r6, #0] 8015d0c: 2000 movs r0, #0 8015d0e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8015d12: f8df 80d4 ldr.w r8, [pc, #212] @ 8015de8 <_malloc_r+0xfc> 8015d16: f000 f911 bl 8015f3c <__malloc_lock> 8015d1a: f8d8 3000 ldr.w r3, [r8] 8015d1e: 461c mov r4, r3 8015d20: bb44 cbnz r4, 8015d74 <_malloc_r+0x88> 8015d22: 4629 mov r1, r5 8015d24: 4630 mov r0, r6 8015d26: f7ff ffbf bl 8015ca8 8015d2a: 1c43 adds r3, r0, #1 8015d2c: 4604 mov r4, r0 8015d2e: d158 bne.n 8015de2 <_malloc_r+0xf6> 8015d30: f8d8 4000 ldr.w r4, [r8] 8015d34: 4627 mov r7, r4 8015d36: 2f00 cmp r7, #0 8015d38: d143 bne.n 8015dc2 <_malloc_r+0xd6> 8015d3a: 2c00 cmp r4, #0 8015d3c: d04b beq.n 8015dd6 <_malloc_r+0xea> 8015d3e: 6823 ldr r3, [r4, #0] 8015d40: 4639 mov r1, r7 8015d42: 4630 mov r0, r6 8015d44: eb04 0903 add.w r9, r4, r3 8015d48: f000 fd40 bl 80167cc <_sbrk_r> 8015d4c: 4581 cmp r9, r0 8015d4e: d142 bne.n 8015dd6 <_malloc_r+0xea> 8015d50: 6821 ldr r1, [r4, #0] 8015d52: 4630 mov r0, r6 8015d54: 1a6d subs r5, r5, r1 8015d56: 4629 mov r1, r5 8015d58: f7ff ffa6 bl 8015ca8 8015d5c: 3001 adds r0, #1 8015d5e: d03a beq.n 8015dd6 <_malloc_r+0xea> 8015d60: 6823 ldr r3, [r4, #0] 8015d62: 442b add r3, r5 8015d64: 6023 str r3, [r4, #0] 8015d66: f8d8 3000 ldr.w r3, [r8] 8015d6a: 685a ldr r2, [r3, #4] 8015d6c: bb62 cbnz r2, 8015dc8 <_malloc_r+0xdc> 8015d6e: f8c8 7000 str.w r7, [r8] 8015d72: e00f b.n 8015d94 <_malloc_r+0xa8> 8015d74: 6822 ldr r2, [r4, #0] 8015d76: 1b52 subs r2, r2, r5 8015d78: d420 bmi.n 8015dbc <_malloc_r+0xd0> 8015d7a: 2a0b cmp r2, #11 8015d7c: d917 bls.n 8015dae <_malloc_r+0xc2> 8015d7e: 1961 adds r1, r4, r5 8015d80: 42a3 cmp r3, r4 8015d82: 6025 str r5, [r4, #0] 8015d84: bf18 it ne 8015d86: 6059 strne r1, [r3, #4] 8015d88: 6863 ldr r3, [r4, #4] 8015d8a: bf08 it eq 8015d8c: f8c8 1000 streq.w r1, [r8] 8015d90: 5162 str r2, [r4, r5] 8015d92: 604b str r3, [r1, #4] 8015d94: 4630 mov r0, r6 8015d96: f000 f8d7 bl 8015f48 <__malloc_unlock> 8015d9a: f104 000b add.w r0, r4, #11 8015d9e: 1d23 adds r3, r4, #4 8015da0: f020 0007 bic.w r0, r0, #7 8015da4: 1ac2 subs r2, r0, r3 8015da6: bf1c itt ne 8015da8: 1a1b subne r3, r3, r0 8015daa: 50a3 strne r3, [r4, r2] 8015dac: e7af b.n 8015d0e <_malloc_r+0x22> 8015dae: 6862 ldr r2, [r4, #4] 8015db0: 42a3 cmp r3, r4 8015db2: bf0c ite eq 8015db4: f8c8 2000 streq.w r2, [r8] 8015db8: 605a strne r2, [r3, #4] 8015dba: e7eb b.n 8015d94 <_malloc_r+0xa8> 8015dbc: 4623 mov r3, r4 8015dbe: 6864 ldr r4, [r4, #4] 8015dc0: e7ae b.n 8015d20 <_malloc_r+0x34> 8015dc2: 463c mov r4, r7 8015dc4: 687f ldr r7, [r7, #4] 8015dc6: e7b6 b.n 8015d36 <_malloc_r+0x4a> 8015dc8: 461a mov r2, r3 8015dca: 685b ldr r3, [r3, #4] 8015dcc: 42a3 cmp r3, r4 8015dce: d1fb bne.n 8015dc8 <_malloc_r+0xdc> 8015dd0: 2300 movs r3, #0 8015dd2: 6053 str r3, [r2, #4] 8015dd4: e7de b.n 8015d94 <_malloc_r+0xa8> 8015dd6: 230c movs r3, #12 8015dd8: 4630 mov r0, r6 8015dda: 6033 str r3, [r6, #0] 8015ddc: f000 f8b4 bl 8015f48 <__malloc_unlock> 8015de0: e794 b.n 8015d0c <_malloc_r+0x20> 8015de2: 6005 str r5, [r0, #0] 8015de4: e7d6 b.n 8015d94 <_malloc_r+0xa8> 8015de6: bf00 nop 8015de8: 200015d0 .word 0x200015d0 08015dec <__sflush_r>: 8015dec: f9b1 200c ldrsh.w r2, [r1, #12] 8015df0: b5f8 push {r3, r4, r5, r6, r7, lr} 8015df2: 0716 lsls r6, r2, #28 8015df4: 4605 mov r5, r0 8015df6: 460c mov r4, r1 8015df8: d454 bmi.n 8015ea4 <__sflush_r+0xb8> 8015dfa: 684b ldr r3, [r1, #4] 8015dfc: 2b00 cmp r3, #0 8015dfe: dc02 bgt.n 8015e06 <__sflush_r+0x1a> 8015e00: 6c0b ldr r3, [r1, #64] @ 0x40 8015e02: 2b00 cmp r3, #0 8015e04: dd48 ble.n 8015e98 <__sflush_r+0xac> 8015e06: 6ae6 ldr r6, [r4, #44] @ 0x2c 8015e08: 2e00 cmp r6, #0 8015e0a: d045 beq.n 8015e98 <__sflush_r+0xac> 8015e0c: 2300 movs r3, #0 8015e0e: f412 5280 ands.w r2, r2, #4096 @ 0x1000 8015e12: 682f ldr r7, [r5, #0] 8015e14: 6a21 ldr r1, [r4, #32] 8015e16: 602b str r3, [r5, #0] 8015e18: d030 beq.n 8015e7c <__sflush_r+0x90> 8015e1a: 6d62 ldr r2, [r4, #84] @ 0x54 8015e1c: 89a3 ldrh r3, [r4, #12] 8015e1e: 0759 lsls r1, r3, #29 8015e20: d505 bpl.n 8015e2e <__sflush_r+0x42> 8015e22: 6863 ldr r3, [r4, #4] 8015e24: 1ad2 subs r2, r2, r3 8015e26: 6b63 ldr r3, [r4, #52] @ 0x34 8015e28: b10b cbz r3, 8015e2e <__sflush_r+0x42> 8015e2a: 6c23 ldr r3, [r4, #64] @ 0x40 8015e2c: 1ad2 subs r2, r2, r3 8015e2e: 2300 movs r3, #0 8015e30: 4628 mov r0, r5 8015e32: 6ae6 ldr r6, [r4, #44] @ 0x2c 8015e34: 6a21 ldr r1, [r4, #32] 8015e36: 47b0 blx r6 8015e38: 1c43 adds r3, r0, #1 8015e3a: 89a3 ldrh r3, [r4, #12] 8015e3c: d106 bne.n 8015e4c <__sflush_r+0x60> 8015e3e: 6829 ldr r1, [r5, #0] 8015e40: 291d cmp r1, #29 8015e42: d82b bhi.n 8015e9c <__sflush_r+0xb0> 8015e44: 4a28 ldr r2, [pc, #160] @ (8015ee8 <__sflush_r+0xfc>) 8015e46: 40ca lsrs r2, r1 8015e48: 07d6 lsls r6, r2, #31 8015e4a: d527 bpl.n 8015e9c <__sflush_r+0xb0> 8015e4c: 2200 movs r2, #0 8015e4e: 6062 str r2, [r4, #4] 8015e50: 6922 ldr r2, [r4, #16] 8015e52: 04d9 lsls r1, r3, #19 8015e54: 6022 str r2, [r4, #0] 8015e56: d504 bpl.n 8015e62 <__sflush_r+0x76> 8015e58: 1c42 adds r2, r0, #1 8015e5a: d101 bne.n 8015e60 <__sflush_r+0x74> 8015e5c: 682b ldr r3, [r5, #0] 8015e5e: b903 cbnz r3, 8015e62 <__sflush_r+0x76> 8015e60: 6560 str r0, [r4, #84] @ 0x54 8015e62: 6b61 ldr r1, [r4, #52] @ 0x34 8015e64: 602f str r7, [r5, #0] 8015e66: b1b9 cbz r1, 8015e98 <__sflush_r+0xac> 8015e68: f104 0344 add.w r3, r4, #68 @ 0x44 8015e6c: 4299 cmp r1, r3 8015e6e: d002 beq.n 8015e76 <__sflush_r+0x8a> 8015e70: 4628 mov r0, r5 8015e72: f000 fcf9 bl 8016868 <_free_r> 8015e76: 2300 movs r3, #0 8015e78: 6363 str r3, [r4, #52] @ 0x34 8015e7a: e00d b.n 8015e98 <__sflush_r+0xac> 8015e7c: 2301 movs r3, #1 8015e7e: 4628 mov r0, r5 8015e80: 47b0 blx r6 8015e82: 4602 mov r2, r0 8015e84: 1c50 adds r0, r2, #1 8015e86: d1c9 bne.n 8015e1c <__sflush_r+0x30> 8015e88: 682b ldr r3, [r5, #0] 8015e8a: 2b00 cmp r3, #0 8015e8c: d0c6 beq.n 8015e1c <__sflush_r+0x30> 8015e8e: 2b1d cmp r3, #29 8015e90: d001 beq.n 8015e96 <__sflush_r+0xaa> 8015e92: 2b16 cmp r3, #22 8015e94: d11d bne.n 8015ed2 <__sflush_r+0xe6> 8015e96: 602f str r7, [r5, #0] 8015e98: 2000 movs r0, #0 8015e9a: e021 b.n 8015ee0 <__sflush_r+0xf4> 8015e9c: f043 0340 orr.w r3, r3, #64 @ 0x40 8015ea0: b21b sxth r3, r3 8015ea2: e01a b.n 8015eda <__sflush_r+0xee> 8015ea4: 690f ldr r7, [r1, #16] 8015ea6: 2f00 cmp r7, #0 8015ea8: d0f6 beq.n 8015e98 <__sflush_r+0xac> 8015eaa: 0793 lsls r3, r2, #30 8015eac: bf18 it ne 8015eae: 2300 movne r3, #0 8015eb0: 680e ldr r6, [r1, #0] 8015eb2: bf08 it eq 8015eb4: 694b ldreq r3, [r1, #20] 8015eb6: 1bf6 subs r6, r6, r7 8015eb8: 600f str r7, [r1, #0] 8015eba: 608b str r3, [r1, #8] 8015ebc: 2e00 cmp r6, #0 8015ebe: ddeb ble.n 8015e98 <__sflush_r+0xac> 8015ec0: 4633 mov r3, r6 8015ec2: 463a mov r2, r7 8015ec4: 4628 mov r0, r5 8015ec6: 6a21 ldr r1, [r4, #32] 8015ec8: f8d4 c028 ldr.w ip, [r4, #40] @ 0x28 8015ecc: 47e0 blx ip 8015ece: 2800 cmp r0, #0 8015ed0: dc07 bgt.n 8015ee2 <__sflush_r+0xf6> 8015ed2: f9b4 300c ldrsh.w r3, [r4, #12] 8015ed6: f043 0340 orr.w r3, r3, #64 @ 0x40 8015eda: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015ede: 81a3 strh r3, [r4, #12] 8015ee0: bdf8 pop {r3, r4, r5, r6, r7, pc} 8015ee2: 4407 add r7, r0 8015ee4: 1a36 subs r6, r6, r0 8015ee6: e7e9 b.n 8015ebc <__sflush_r+0xd0> 8015ee8: 20400001 .word 0x20400001 08015eec <_fflush_r>: 8015eec: b538 push {r3, r4, r5, lr} 8015eee: 690b ldr r3, [r1, #16] 8015ef0: 4605 mov r5, r0 8015ef2: 460c mov r4, r1 8015ef4: b913 cbnz r3, 8015efc <_fflush_r+0x10> 8015ef6: 2500 movs r5, #0 8015ef8: 4628 mov r0, r5 8015efa: bd38 pop {r3, r4, r5, pc} 8015efc: b118 cbz r0, 8015f06 <_fflush_r+0x1a> 8015efe: 6a03 ldr r3, [r0, #32] 8015f00: b90b cbnz r3, 8015f06 <_fflush_r+0x1a> 8015f02: f7fe fe2f bl 8014b64 <__sinit> 8015f06: f9b4 300c ldrsh.w r3, [r4, #12] 8015f0a: 2b00 cmp r3, #0 8015f0c: d0f3 beq.n 8015ef6 <_fflush_r+0xa> 8015f0e: 6e62 ldr r2, [r4, #100] @ 0x64 8015f10: 07d0 lsls r0, r2, #31 8015f12: d404 bmi.n 8015f1e <_fflush_r+0x32> 8015f14: 0599 lsls r1, r3, #22 8015f16: d402 bmi.n 8015f1e <_fflush_r+0x32> 8015f18: 6da0 ldr r0, [r4, #88] @ 0x58 8015f1a: f7fe fec8 bl 8014cae <__retarget_lock_acquire_recursive> 8015f1e: 4628 mov r0, r5 8015f20: 4621 mov r1, r4 8015f22: f7ff ff63 bl 8015dec <__sflush_r> 8015f26: 6e63 ldr r3, [r4, #100] @ 0x64 8015f28: 4605 mov r5, r0 8015f2a: 07da lsls r2, r3, #31 8015f2c: d4e4 bmi.n 8015ef8 <_fflush_r+0xc> 8015f2e: 89a3 ldrh r3, [r4, #12] 8015f30: 059b lsls r3, r3, #22 8015f32: d4e1 bmi.n 8015ef8 <_fflush_r+0xc> 8015f34: 6da0 ldr r0, [r4, #88] @ 0x58 8015f36: f7fe febb bl 8014cb0 <__retarget_lock_release_recursive> 8015f3a: e7dd b.n 8015ef8 <_fflush_r+0xc> 08015f3c <__malloc_lock>: 8015f3c: 4801 ldr r0, [pc, #4] @ (8015f44 <__malloc_lock+0x8>) 8015f3e: f7fe beb6 b.w 8014cae <__retarget_lock_acquire_recursive> 8015f42: bf00 nop 8015f44: 200015c8 .word 0x200015c8 08015f48 <__malloc_unlock>: 8015f48: 4801 ldr r0, [pc, #4] @ (8015f50 <__malloc_unlock+0x8>) 8015f4a: f7fe beb1 b.w 8014cb0 <__retarget_lock_release_recursive> 8015f4e: bf00 nop 8015f50: 200015c8 .word 0x200015c8 08015f54 <_Balloc>: 8015f54: b570 push {r4, r5, r6, lr} 8015f56: 69c6 ldr r6, [r0, #28] 8015f58: 4604 mov r4, r0 8015f5a: 460d mov r5, r1 8015f5c: b976 cbnz r6, 8015f7c <_Balloc+0x28> 8015f5e: 2010 movs r0, #16 8015f60: f7ff fe9a bl 8015c98 8015f64: 4602 mov r2, r0 8015f66: 61e0 str r0, [r4, #28] 8015f68: b920 cbnz r0, 8015f74 <_Balloc+0x20> 8015f6a: 216b movs r1, #107 @ 0x6b 8015f6c: 4b17 ldr r3, [pc, #92] @ (8015fcc <_Balloc+0x78>) 8015f6e: 4818 ldr r0, [pc, #96] @ (8015fd0 <_Balloc+0x7c>) 8015f70: f7fe fec0 bl 8014cf4 <__assert_func> 8015f74: e9c0 6601 strd r6, r6, [r0, #4] 8015f78: 6006 str r6, [r0, #0] 8015f7a: 60c6 str r6, [r0, #12] 8015f7c: 69e6 ldr r6, [r4, #28] 8015f7e: 68f3 ldr r3, [r6, #12] 8015f80: b183 cbz r3, 8015fa4 <_Balloc+0x50> 8015f82: 69e3 ldr r3, [r4, #28] 8015f84: 68db ldr r3, [r3, #12] 8015f86: f853 0025 ldr.w r0, [r3, r5, lsl #2] 8015f8a: b9b8 cbnz r0, 8015fbc <_Balloc+0x68> 8015f8c: 2101 movs r1, #1 8015f8e: fa01 f605 lsl.w r6, r1, r5 8015f92: 1d72 adds r2, r6, #5 8015f94: 4620 mov r0, r4 8015f96: 0092 lsls r2, r2, #2 8015f98: f000 fc51 bl 801683e <_calloc_r> 8015f9c: b160 cbz r0, 8015fb8 <_Balloc+0x64> 8015f9e: e9c0 5601 strd r5, r6, [r0, #4] 8015fa2: e00e b.n 8015fc2 <_Balloc+0x6e> 8015fa4: 2221 movs r2, #33 @ 0x21 8015fa6: 2104 movs r1, #4 8015fa8: 4620 mov r0, r4 8015faa: f000 fc48 bl 801683e <_calloc_r> 8015fae: 69e3 ldr r3, [r4, #28] 8015fb0: 60f0 str r0, [r6, #12] 8015fb2: 68db ldr r3, [r3, #12] 8015fb4: 2b00 cmp r3, #0 8015fb6: d1e4 bne.n 8015f82 <_Balloc+0x2e> 8015fb8: 2000 movs r0, #0 8015fba: bd70 pop {r4, r5, r6, pc} 8015fbc: 6802 ldr r2, [r0, #0] 8015fbe: f843 2025 str.w r2, [r3, r5, lsl #2] 8015fc2: 2300 movs r3, #0 8015fc4: e9c0 3303 strd r3, r3, [r0, #12] 8015fc8: e7f7 b.n 8015fba <_Balloc+0x66> 8015fca: bf00 nop 8015fcc: 08017969 .word 0x08017969 8015fd0: 080179fa .word 0x080179fa 08015fd4 <_Bfree>: 8015fd4: b570 push {r4, r5, r6, lr} 8015fd6: 69c6 ldr r6, [r0, #28] 8015fd8: 4605 mov r5, r0 8015fda: 460c mov r4, r1 8015fdc: b976 cbnz r6, 8015ffc <_Bfree+0x28> 8015fde: 2010 movs r0, #16 8015fe0: f7ff fe5a bl 8015c98 8015fe4: 4602 mov r2, r0 8015fe6: 61e8 str r0, [r5, #28] 8015fe8: b920 cbnz r0, 8015ff4 <_Bfree+0x20> 8015fea: 218f movs r1, #143 @ 0x8f 8015fec: 4b08 ldr r3, [pc, #32] @ (8016010 <_Bfree+0x3c>) 8015fee: 4809 ldr r0, [pc, #36] @ (8016014 <_Bfree+0x40>) 8015ff0: f7fe fe80 bl 8014cf4 <__assert_func> 8015ff4: e9c0 6601 strd r6, r6, [r0, #4] 8015ff8: 6006 str r6, [r0, #0] 8015ffa: 60c6 str r6, [r0, #12] 8015ffc: b13c cbz r4, 801600e <_Bfree+0x3a> 8015ffe: 69eb ldr r3, [r5, #28] 8016000: 6862 ldr r2, [r4, #4] 8016002: 68db ldr r3, [r3, #12] 8016004: f853 1022 ldr.w r1, [r3, r2, lsl #2] 8016008: 6021 str r1, [r4, #0] 801600a: f843 4022 str.w r4, [r3, r2, lsl #2] 801600e: bd70 pop {r4, r5, r6, pc} 8016010: 08017969 .word 0x08017969 8016014: 080179fa .word 0x080179fa 08016018 <__multadd>: 8016018: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 801601c: 4607 mov r7, r0 801601e: 460c mov r4, r1 8016020: 461e mov r6, r3 8016022: 2000 movs r0, #0 8016024: 690d ldr r5, [r1, #16] 8016026: f101 0c14 add.w ip, r1, #20 801602a: f8dc 3000 ldr.w r3, [ip] 801602e: 3001 adds r0, #1 8016030: b299 uxth r1, r3 8016032: fb02 6101 mla r1, r2, r1, r6 8016036: 0c1e lsrs r6, r3, #16 8016038: 0c0b lsrs r3, r1, #16 801603a: fb02 3306 mla r3, r2, r6, r3 801603e: b289 uxth r1, r1 8016040: eb01 4103 add.w r1, r1, r3, lsl #16 8016044: 4285 cmp r5, r0 8016046: ea4f 4613 mov.w r6, r3, lsr #16 801604a: f84c 1b04 str.w r1, [ip], #4 801604e: dcec bgt.n 801602a <__multadd+0x12> 8016050: b30e cbz r6, 8016096 <__multadd+0x7e> 8016052: 68a3 ldr r3, [r4, #8] 8016054: 42ab cmp r3, r5 8016056: dc19 bgt.n 801608c <__multadd+0x74> 8016058: 6861 ldr r1, [r4, #4] 801605a: 4638 mov r0, r7 801605c: 3101 adds r1, #1 801605e: f7ff ff79 bl 8015f54 <_Balloc> 8016062: 4680 mov r8, r0 8016064: b928 cbnz r0, 8016072 <__multadd+0x5a> 8016066: 4602 mov r2, r0 8016068: 21ba movs r1, #186 @ 0xba 801606a: 4b0c ldr r3, [pc, #48] @ (801609c <__multadd+0x84>) 801606c: 480c ldr r0, [pc, #48] @ (80160a0 <__multadd+0x88>) 801606e: f7fe fe41 bl 8014cf4 <__assert_func> 8016072: 6922 ldr r2, [r4, #16] 8016074: f104 010c add.w r1, r4, #12 8016078: 3202 adds r2, #2 801607a: 0092 lsls r2, r2, #2 801607c: 300c adds r0, #12 801607e: f7fe fe2b bl 8014cd8 8016082: 4621 mov r1, r4 8016084: 4638 mov r0, r7 8016086: f7ff ffa5 bl 8015fd4 <_Bfree> 801608a: 4644 mov r4, r8 801608c: eb04 0385 add.w r3, r4, r5, lsl #2 8016090: 3501 adds r5, #1 8016092: 615e str r6, [r3, #20] 8016094: 6125 str r5, [r4, #16] 8016096: 4620 mov r0, r4 8016098: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 801609c: 080179d8 .word 0x080179d8 80160a0: 080179fa .word 0x080179fa 080160a4 <__hi0bits>: 80160a4: 4603 mov r3, r0 80160a6: f5b0 3f80 cmp.w r0, #65536 @ 0x10000 80160aa: bf3a itte cc 80160ac: 0403 lslcc r3, r0, #16 80160ae: 2010 movcc r0, #16 80160b0: 2000 movcs r0, #0 80160b2: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 80160b6: bf3c itt cc 80160b8: 021b lslcc r3, r3, #8 80160ba: 3008 addcc r0, #8 80160bc: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80160c0: bf3c itt cc 80160c2: 011b lslcc r3, r3, #4 80160c4: 3004 addcc r0, #4 80160c6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80160ca: bf3c itt cc 80160cc: 009b lslcc r3, r3, #2 80160ce: 3002 addcc r0, #2 80160d0: 2b00 cmp r3, #0 80160d2: db05 blt.n 80160e0 <__hi0bits+0x3c> 80160d4: f013 4f80 tst.w r3, #1073741824 @ 0x40000000 80160d8: f100 0001 add.w r0, r0, #1 80160dc: bf08 it eq 80160de: 2020 moveq r0, #32 80160e0: 4770 bx lr 080160e2 <__lo0bits>: 80160e2: 6803 ldr r3, [r0, #0] 80160e4: 4602 mov r2, r0 80160e6: f013 0007 ands.w r0, r3, #7 80160ea: d00b beq.n 8016104 <__lo0bits+0x22> 80160ec: 07d9 lsls r1, r3, #31 80160ee: d421 bmi.n 8016134 <__lo0bits+0x52> 80160f0: 0798 lsls r0, r3, #30 80160f2: bf49 itett mi 80160f4: 085b lsrmi r3, r3, #1 80160f6: 089b lsrpl r3, r3, #2 80160f8: 2001 movmi r0, #1 80160fa: 6013 strmi r3, [r2, #0] 80160fc: bf5c itt pl 80160fe: 2002 movpl r0, #2 8016100: 6013 strpl r3, [r2, #0] 8016102: 4770 bx lr 8016104: b299 uxth r1, r3 8016106: b909 cbnz r1, 801610c <__lo0bits+0x2a> 8016108: 2010 movs r0, #16 801610a: 0c1b lsrs r3, r3, #16 801610c: b2d9 uxtb r1, r3 801610e: b909 cbnz r1, 8016114 <__lo0bits+0x32> 8016110: 3008 adds r0, #8 8016112: 0a1b lsrs r3, r3, #8 8016114: 0719 lsls r1, r3, #28 8016116: bf04 itt eq 8016118: 091b lsreq r3, r3, #4 801611a: 3004 addeq r0, #4 801611c: 0799 lsls r1, r3, #30 801611e: bf04 itt eq 8016120: 089b lsreq r3, r3, #2 8016122: 3002 addeq r0, #2 8016124: 07d9 lsls r1, r3, #31 8016126: d403 bmi.n 8016130 <__lo0bits+0x4e> 8016128: 085b lsrs r3, r3, #1 801612a: f100 0001 add.w r0, r0, #1 801612e: d003 beq.n 8016138 <__lo0bits+0x56> 8016130: 6013 str r3, [r2, #0] 8016132: 4770 bx lr 8016134: 2000 movs r0, #0 8016136: 4770 bx lr 8016138: 2020 movs r0, #32 801613a: 4770 bx lr 0801613c <__i2b>: 801613c: b510 push {r4, lr} 801613e: 460c mov r4, r1 8016140: 2101 movs r1, #1 8016142: f7ff ff07 bl 8015f54 <_Balloc> 8016146: 4602 mov r2, r0 8016148: b928 cbnz r0, 8016156 <__i2b+0x1a> 801614a: f240 1145 movw r1, #325 @ 0x145 801614e: 4b04 ldr r3, [pc, #16] @ (8016160 <__i2b+0x24>) 8016150: 4804 ldr r0, [pc, #16] @ (8016164 <__i2b+0x28>) 8016152: f7fe fdcf bl 8014cf4 <__assert_func> 8016156: 2301 movs r3, #1 8016158: 6144 str r4, [r0, #20] 801615a: 6103 str r3, [r0, #16] 801615c: bd10 pop {r4, pc} 801615e: bf00 nop 8016160: 080179d8 .word 0x080179d8 8016164: 080179fa .word 0x080179fa 08016168 <__multiply>: 8016168: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801616c: 4617 mov r7, r2 801616e: 690a ldr r2, [r1, #16] 8016170: 693b ldr r3, [r7, #16] 8016172: 4689 mov r9, r1 8016174: 429a cmp r2, r3 8016176: bfa2 ittt ge 8016178: 463b movge r3, r7 801617a: 460f movge r7, r1 801617c: 4699 movge r9, r3 801617e: 693d ldr r5, [r7, #16] 8016180: f8d9 a010 ldr.w sl, [r9, #16] 8016184: 68bb ldr r3, [r7, #8] 8016186: 6879 ldr r1, [r7, #4] 8016188: eb05 060a add.w r6, r5, sl 801618c: 42b3 cmp r3, r6 801618e: b085 sub sp, #20 8016190: bfb8 it lt 8016192: 3101 addlt r1, #1 8016194: f7ff fede bl 8015f54 <_Balloc> 8016198: b930 cbnz r0, 80161a8 <__multiply+0x40> 801619a: 4602 mov r2, r0 801619c: f44f 71b1 mov.w r1, #354 @ 0x162 80161a0: 4b40 ldr r3, [pc, #256] @ (80162a4 <__multiply+0x13c>) 80161a2: 4841 ldr r0, [pc, #260] @ (80162a8 <__multiply+0x140>) 80161a4: f7fe fda6 bl 8014cf4 <__assert_func> 80161a8: f100 0414 add.w r4, r0, #20 80161ac: 4623 mov r3, r4 80161ae: 2200 movs r2, #0 80161b0: eb04 0e86 add.w lr, r4, r6, lsl #2 80161b4: 4573 cmp r3, lr 80161b6: d320 bcc.n 80161fa <__multiply+0x92> 80161b8: f107 0814 add.w r8, r7, #20 80161bc: f109 0114 add.w r1, r9, #20 80161c0: eb08 0585 add.w r5, r8, r5, lsl #2 80161c4: eb01 038a add.w r3, r1, sl, lsl #2 80161c8: 9302 str r3, [sp, #8] 80161ca: 1beb subs r3, r5, r7 80161cc: 3b15 subs r3, #21 80161ce: f023 0303 bic.w r3, r3, #3 80161d2: 3304 adds r3, #4 80161d4: 3715 adds r7, #21 80161d6: 42bd cmp r5, r7 80161d8: bf38 it cc 80161da: 2304 movcc r3, #4 80161dc: 9301 str r3, [sp, #4] 80161de: 9b02 ldr r3, [sp, #8] 80161e0: 9103 str r1, [sp, #12] 80161e2: 428b cmp r3, r1 80161e4: d80c bhi.n 8016200 <__multiply+0x98> 80161e6: 2e00 cmp r6, #0 80161e8: dd03 ble.n 80161f2 <__multiply+0x8a> 80161ea: f85e 3d04 ldr.w r3, [lr, #-4]! 80161ee: 2b00 cmp r3, #0 80161f0: d055 beq.n 801629e <__multiply+0x136> 80161f2: 6106 str r6, [r0, #16] 80161f4: b005 add sp, #20 80161f6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80161fa: f843 2b04 str.w r2, [r3], #4 80161fe: e7d9 b.n 80161b4 <__multiply+0x4c> 8016200: f8b1 a000 ldrh.w sl, [r1] 8016204: f1ba 0f00 cmp.w sl, #0 8016208: d01f beq.n 801624a <__multiply+0xe2> 801620a: 46c4 mov ip, r8 801620c: 46a1 mov r9, r4 801620e: 2700 movs r7, #0 8016210: f85c 2b04 ldr.w r2, [ip], #4 8016214: f8d9 3000 ldr.w r3, [r9] 8016218: fa1f fb82 uxth.w fp, r2 801621c: b29b uxth r3, r3 801621e: fb0a 330b mla r3, sl, fp, r3 8016222: 443b add r3, r7 8016224: f8d9 7000 ldr.w r7, [r9] 8016228: 0c12 lsrs r2, r2, #16 801622a: 0c3f lsrs r7, r7, #16 801622c: fb0a 7202 mla r2, sl, r2, r7 8016230: eb02 4213 add.w r2, r2, r3, lsr #16 8016234: b29b uxth r3, r3 8016236: ea43 4302 orr.w r3, r3, r2, lsl #16 801623a: 4565 cmp r5, ip 801623c: ea4f 4712 mov.w r7, r2, lsr #16 8016240: f849 3b04 str.w r3, [r9], #4 8016244: d8e4 bhi.n 8016210 <__multiply+0xa8> 8016246: 9b01 ldr r3, [sp, #4] 8016248: 50e7 str r7, [r4, r3] 801624a: 9b03 ldr r3, [sp, #12] 801624c: 3104 adds r1, #4 801624e: f8b3 9002 ldrh.w r9, [r3, #2] 8016252: f1b9 0f00 cmp.w r9, #0 8016256: d020 beq.n 801629a <__multiply+0x132> 8016258: 4647 mov r7, r8 801625a: 46a4 mov ip, r4 801625c: f04f 0a00 mov.w sl, #0 8016260: 6823 ldr r3, [r4, #0] 8016262: f8b7 b000 ldrh.w fp, [r7] 8016266: f8bc 2002 ldrh.w r2, [ip, #2] 801626a: b29b uxth r3, r3 801626c: fb09 220b mla r2, r9, fp, r2 8016270: 4452 add r2, sl 8016272: ea43 4302 orr.w r3, r3, r2, lsl #16 8016276: f84c 3b04 str.w r3, [ip], #4 801627a: f857 3b04 ldr.w r3, [r7], #4 801627e: ea4f 4a13 mov.w sl, r3, lsr #16 8016282: f8bc 3000 ldrh.w r3, [ip] 8016286: 42bd cmp r5, r7 8016288: fb09 330a mla r3, r9, sl, r3 801628c: eb03 4312 add.w r3, r3, r2, lsr #16 8016290: ea4f 4a13 mov.w sl, r3, lsr #16 8016294: d8e5 bhi.n 8016262 <__multiply+0xfa> 8016296: 9a01 ldr r2, [sp, #4] 8016298: 50a3 str r3, [r4, r2] 801629a: 3404 adds r4, #4 801629c: e79f b.n 80161de <__multiply+0x76> 801629e: 3e01 subs r6, #1 80162a0: e7a1 b.n 80161e6 <__multiply+0x7e> 80162a2: bf00 nop 80162a4: 080179d8 .word 0x080179d8 80162a8: 080179fa .word 0x080179fa 080162ac <__pow5mult>: 80162ac: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 80162b0: 4615 mov r5, r2 80162b2: f012 0203 ands.w r2, r2, #3 80162b6: 4607 mov r7, r0 80162b8: 460e mov r6, r1 80162ba: d007 beq.n 80162cc <__pow5mult+0x20> 80162bc: 4c25 ldr r4, [pc, #148] @ (8016354 <__pow5mult+0xa8>) 80162be: 3a01 subs r2, #1 80162c0: 2300 movs r3, #0 80162c2: f854 2022 ldr.w r2, [r4, r2, lsl #2] 80162c6: f7ff fea7 bl 8016018 <__multadd> 80162ca: 4606 mov r6, r0 80162cc: 10ad asrs r5, r5, #2 80162ce: d03d beq.n 801634c <__pow5mult+0xa0> 80162d0: 69fc ldr r4, [r7, #28] 80162d2: b97c cbnz r4, 80162f4 <__pow5mult+0x48> 80162d4: 2010 movs r0, #16 80162d6: f7ff fcdf bl 8015c98 80162da: 4602 mov r2, r0 80162dc: 61f8 str r0, [r7, #28] 80162de: b928 cbnz r0, 80162ec <__pow5mult+0x40> 80162e0: f240 11b3 movw r1, #435 @ 0x1b3 80162e4: 4b1c ldr r3, [pc, #112] @ (8016358 <__pow5mult+0xac>) 80162e6: 481d ldr r0, [pc, #116] @ (801635c <__pow5mult+0xb0>) 80162e8: f7fe fd04 bl 8014cf4 <__assert_func> 80162ec: e9c0 4401 strd r4, r4, [r0, #4] 80162f0: 6004 str r4, [r0, #0] 80162f2: 60c4 str r4, [r0, #12] 80162f4: f8d7 801c ldr.w r8, [r7, #28] 80162f8: f8d8 4008 ldr.w r4, [r8, #8] 80162fc: b94c cbnz r4, 8016312 <__pow5mult+0x66> 80162fe: f240 2171 movw r1, #625 @ 0x271 8016302: 4638 mov r0, r7 8016304: f7ff ff1a bl 801613c <__i2b> 8016308: 2300 movs r3, #0 801630a: 4604 mov r4, r0 801630c: f8c8 0008 str.w r0, [r8, #8] 8016310: 6003 str r3, [r0, #0] 8016312: f04f 0900 mov.w r9, #0 8016316: 07eb lsls r3, r5, #31 8016318: d50a bpl.n 8016330 <__pow5mult+0x84> 801631a: 4631 mov r1, r6 801631c: 4622 mov r2, r4 801631e: 4638 mov r0, r7 8016320: f7ff ff22 bl 8016168 <__multiply> 8016324: 4680 mov r8, r0 8016326: 4631 mov r1, r6 8016328: 4638 mov r0, r7 801632a: f7ff fe53 bl 8015fd4 <_Bfree> 801632e: 4646 mov r6, r8 8016330: 106d asrs r5, r5, #1 8016332: d00b beq.n 801634c <__pow5mult+0xa0> 8016334: 6820 ldr r0, [r4, #0] 8016336: b938 cbnz r0, 8016348 <__pow5mult+0x9c> 8016338: 4622 mov r2, r4 801633a: 4621 mov r1, r4 801633c: 4638 mov r0, r7 801633e: f7ff ff13 bl 8016168 <__multiply> 8016342: 6020 str r0, [r4, #0] 8016344: f8c0 9000 str.w r9, [r0] 8016348: 4604 mov r4, r0 801634a: e7e4 b.n 8016316 <__pow5mult+0x6a> 801634c: 4630 mov r0, r6 801634e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8016352: bf00 nop 8016354: 08017a60 .word 0x08017a60 8016358: 08017969 .word 0x08017969 801635c: 080179fa .word 0x080179fa 08016360 <__lshift>: 8016360: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8016364: 460c mov r4, r1 8016366: 4607 mov r7, r0 8016368: 4691 mov r9, r2 801636a: 6923 ldr r3, [r4, #16] 801636c: 6849 ldr r1, [r1, #4] 801636e: eb03 1862 add.w r8, r3, r2, asr #5 8016372: 68a3 ldr r3, [r4, #8] 8016374: ea4f 1a62 mov.w sl, r2, asr #5 8016378: f108 0601 add.w r6, r8, #1 801637c: 42b3 cmp r3, r6 801637e: db0b blt.n 8016398 <__lshift+0x38> 8016380: 4638 mov r0, r7 8016382: f7ff fde7 bl 8015f54 <_Balloc> 8016386: 4605 mov r5, r0 8016388: b948 cbnz r0, 801639e <__lshift+0x3e> 801638a: 4602 mov r2, r0 801638c: f44f 71ef mov.w r1, #478 @ 0x1de 8016390: 4b27 ldr r3, [pc, #156] @ (8016430 <__lshift+0xd0>) 8016392: 4828 ldr r0, [pc, #160] @ (8016434 <__lshift+0xd4>) 8016394: f7fe fcae bl 8014cf4 <__assert_func> 8016398: 3101 adds r1, #1 801639a: 005b lsls r3, r3, #1 801639c: e7ee b.n 801637c <__lshift+0x1c> 801639e: 2300 movs r3, #0 80163a0: f100 0114 add.w r1, r0, #20 80163a4: f100 0210 add.w r2, r0, #16 80163a8: 4618 mov r0, r3 80163aa: 4553 cmp r3, sl 80163ac: db33 blt.n 8016416 <__lshift+0xb6> 80163ae: 6920 ldr r0, [r4, #16] 80163b0: ea2a 7aea bic.w sl, sl, sl, asr #31 80163b4: f104 0314 add.w r3, r4, #20 80163b8: f019 091f ands.w r9, r9, #31 80163bc: eb01 018a add.w r1, r1, sl, lsl #2 80163c0: eb03 0c80 add.w ip, r3, r0, lsl #2 80163c4: d02b beq.n 801641e <__lshift+0xbe> 80163c6: 468a mov sl, r1 80163c8: 2200 movs r2, #0 80163ca: f1c9 0e20 rsb lr, r9, #32 80163ce: 6818 ldr r0, [r3, #0] 80163d0: fa00 f009 lsl.w r0, r0, r9 80163d4: 4310 orrs r0, r2 80163d6: f84a 0b04 str.w r0, [sl], #4 80163da: f853 2b04 ldr.w r2, [r3], #4 80163de: 459c cmp ip, r3 80163e0: fa22 f20e lsr.w r2, r2, lr 80163e4: d8f3 bhi.n 80163ce <__lshift+0x6e> 80163e6: ebac 0304 sub.w r3, ip, r4 80163ea: 3b15 subs r3, #21 80163ec: f023 0303 bic.w r3, r3, #3 80163f0: 3304 adds r3, #4 80163f2: f104 0015 add.w r0, r4, #21 80163f6: 4560 cmp r0, ip 80163f8: bf88 it hi 80163fa: 2304 movhi r3, #4 80163fc: 50ca str r2, [r1, r3] 80163fe: b10a cbz r2, 8016404 <__lshift+0xa4> 8016400: f108 0602 add.w r6, r8, #2 8016404: 3e01 subs r6, #1 8016406: 4638 mov r0, r7 8016408: 4621 mov r1, r4 801640a: 612e str r6, [r5, #16] 801640c: f7ff fde2 bl 8015fd4 <_Bfree> 8016410: 4628 mov r0, r5 8016412: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8016416: f842 0f04 str.w r0, [r2, #4]! 801641a: 3301 adds r3, #1 801641c: e7c5 b.n 80163aa <__lshift+0x4a> 801641e: 3904 subs r1, #4 8016420: f853 2b04 ldr.w r2, [r3], #4 8016424: 459c cmp ip, r3 8016426: f841 2f04 str.w r2, [r1, #4]! 801642a: d8f9 bhi.n 8016420 <__lshift+0xc0> 801642c: e7ea b.n 8016404 <__lshift+0xa4> 801642e: bf00 nop 8016430: 080179d8 .word 0x080179d8 8016434: 080179fa .word 0x080179fa 08016438 <__mcmp>: 8016438: 4603 mov r3, r0 801643a: 690a ldr r2, [r1, #16] 801643c: 6900 ldr r0, [r0, #16] 801643e: b530 push {r4, r5, lr} 8016440: 1a80 subs r0, r0, r2 8016442: d10e bne.n 8016462 <__mcmp+0x2a> 8016444: 3314 adds r3, #20 8016446: 3114 adds r1, #20 8016448: eb03 0482 add.w r4, r3, r2, lsl #2 801644c: eb01 0182 add.w r1, r1, r2, lsl #2 8016450: f854 5d04 ldr.w r5, [r4, #-4]! 8016454: f851 2d04 ldr.w r2, [r1, #-4]! 8016458: 4295 cmp r5, r2 801645a: d003 beq.n 8016464 <__mcmp+0x2c> 801645c: d205 bcs.n 801646a <__mcmp+0x32> 801645e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016462: bd30 pop {r4, r5, pc} 8016464: 42a3 cmp r3, r4 8016466: d3f3 bcc.n 8016450 <__mcmp+0x18> 8016468: e7fb b.n 8016462 <__mcmp+0x2a> 801646a: 2001 movs r0, #1 801646c: e7f9 b.n 8016462 <__mcmp+0x2a> ... 08016470 <__mdiff>: 8016470: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8016474: 4689 mov r9, r1 8016476: 4606 mov r6, r0 8016478: 4611 mov r1, r2 801647a: 4648 mov r0, r9 801647c: 4614 mov r4, r2 801647e: f7ff ffdb bl 8016438 <__mcmp> 8016482: 1e05 subs r5, r0, #0 8016484: d112 bne.n 80164ac <__mdiff+0x3c> 8016486: 4629 mov r1, r5 8016488: 4630 mov r0, r6 801648a: f7ff fd63 bl 8015f54 <_Balloc> 801648e: 4602 mov r2, r0 8016490: b928 cbnz r0, 801649e <__mdiff+0x2e> 8016492: f240 2137 movw r1, #567 @ 0x237 8016496: 4b3e ldr r3, [pc, #248] @ (8016590 <__mdiff+0x120>) 8016498: 483e ldr r0, [pc, #248] @ (8016594 <__mdiff+0x124>) 801649a: f7fe fc2b bl 8014cf4 <__assert_func> 801649e: 2301 movs r3, #1 80164a0: e9c0 3504 strd r3, r5, [r0, #16] 80164a4: 4610 mov r0, r2 80164a6: b003 add sp, #12 80164a8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80164ac: bfbc itt lt 80164ae: 464b movlt r3, r9 80164b0: 46a1 movlt r9, r4 80164b2: 4630 mov r0, r6 80164b4: f8d9 1004 ldr.w r1, [r9, #4] 80164b8: bfba itte lt 80164ba: 461c movlt r4, r3 80164bc: 2501 movlt r5, #1 80164be: 2500 movge r5, #0 80164c0: f7ff fd48 bl 8015f54 <_Balloc> 80164c4: 4602 mov r2, r0 80164c6: b918 cbnz r0, 80164d0 <__mdiff+0x60> 80164c8: f240 2145 movw r1, #581 @ 0x245 80164cc: 4b30 ldr r3, [pc, #192] @ (8016590 <__mdiff+0x120>) 80164ce: e7e3 b.n 8016498 <__mdiff+0x28> 80164d0: f100 0b14 add.w fp, r0, #20 80164d4: f8d9 7010 ldr.w r7, [r9, #16] 80164d8: f109 0310 add.w r3, r9, #16 80164dc: 60c5 str r5, [r0, #12] 80164de: f04f 0c00 mov.w ip, #0 80164e2: f109 0514 add.w r5, r9, #20 80164e6: 46d9 mov r9, fp 80164e8: 6926 ldr r6, [r4, #16] 80164ea: f104 0e14 add.w lr, r4, #20 80164ee: eb05 0887 add.w r8, r5, r7, lsl #2 80164f2: eb0e 0686 add.w r6, lr, r6, lsl #2 80164f6: 9301 str r3, [sp, #4] 80164f8: 9b01 ldr r3, [sp, #4] 80164fa: f85e 0b04 ldr.w r0, [lr], #4 80164fe: f853 af04 ldr.w sl, [r3, #4]! 8016502: b281 uxth r1, r0 8016504: 9301 str r3, [sp, #4] 8016506: fa1f f38a uxth.w r3, sl 801650a: 1a5b subs r3, r3, r1 801650c: 0c00 lsrs r0, r0, #16 801650e: 4463 add r3, ip 8016510: ebc0 401a rsb r0, r0, sl, lsr #16 8016514: eb00 4023 add.w r0, r0, r3, asr #16 8016518: b29b uxth r3, r3 801651a: ea43 4300 orr.w r3, r3, r0, lsl #16 801651e: 4576 cmp r6, lr 8016520: ea4f 4c20 mov.w ip, r0, asr #16 8016524: f849 3b04 str.w r3, [r9], #4 8016528: d8e6 bhi.n 80164f8 <__mdiff+0x88> 801652a: 1b33 subs r3, r6, r4 801652c: 3b15 subs r3, #21 801652e: f023 0303 bic.w r3, r3, #3 8016532: 3415 adds r4, #21 8016534: 3304 adds r3, #4 8016536: 42a6 cmp r6, r4 8016538: bf38 it cc 801653a: 2304 movcc r3, #4 801653c: 441d add r5, r3 801653e: 445b add r3, fp 8016540: 461e mov r6, r3 8016542: 462c mov r4, r5 8016544: 4544 cmp r4, r8 8016546: d30e bcc.n 8016566 <__mdiff+0xf6> 8016548: f108 0103 add.w r1, r8, #3 801654c: 1b49 subs r1, r1, r5 801654e: f021 0103 bic.w r1, r1, #3 8016552: 3d03 subs r5, #3 8016554: 45a8 cmp r8, r5 8016556: bf38 it cc 8016558: 2100 movcc r1, #0 801655a: 440b add r3, r1 801655c: f853 1d04 ldr.w r1, [r3, #-4]! 8016560: b199 cbz r1, 801658a <__mdiff+0x11a> 8016562: 6117 str r7, [r2, #16] 8016564: e79e b.n 80164a4 <__mdiff+0x34> 8016566: 46e6 mov lr, ip 8016568: f854 1b04 ldr.w r1, [r4], #4 801656c: fa1f fc81 uxth.w ip, r1 8016570: 44f4 add ip, lr 8016572: 0c08 lsrs r0, r1, #16 8016574: 4471 add r1, lr 8016576: eb00 402c add.w r0, r0, ip, asr #16 801657a: b289 uxth r1, r1 801657c: ea41 4100 orr.w r1, r1, r0, lsl #16 8016580: ea4f 4c20 mov.w ip, r0, asr #16 8016584: f846 1b04 str.w r1, [r6], #4 8016588: e7dc b.n 8016544 <__mdiff+0xd4> 801658a: 3f01 subs r7, #1 801658c: e7e6 b.n 801655c <__mdiff+0xec> 801658e: bf00 nop 8016590: 080179d8 .word 0x080179d8 8016594: 080179fa .word 0x080179fa 08016598 <__d2b>: 8016598: e92d 4373 stmdb sp!, {r0, r1, r4, r5, r6, r8, r9, lr} 801659c: 2101 movs r1, #1 801659e: 4690 mov r8, r2 80165a0: 4699 mov r9, r3 80165a2: 9e08 ldr r6, [sp, #32] 80165a4: f7ff fcd6 bl 8015f54 <_Balloc> 80165a8: 4604 mov r4, r0 80165aa: b930 cbnz r0, 80165ba <__d2b+0x22> 80165ac: 4602 mov r2, r0 80165ae: f240 310f movw r1, #783 @ 0x30f 80165b2: 4b23 ldr r3, [pc, #140] @ (8016640 <__d2b+0xa8>) 80165b4: 4823 ldr r0, [pc, #140] @ (8016644 <__d2b+0xac>) 80165b6: f7fe fb9d bl 8014cf4 <__assert_func> 80165ba: f3c9 550a ubfx r5, r9, #20, #11 80165be: f3c9 0313 ubfx r3, r9, #0, #20 80165c2: b10d cbz r5, 80165c8 <__d2b+0x30> 80165c4: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80165c8: 9301 str r3, [sp, #4] 80165ca: f1b8 0300 subs.w r3, r8, #0 80165ce: d024 beq.n 801661a <__d2b+0x82> 80165d0: 4668 mov r0, sp 80165d2: 9300 str r3, [sp, #0] 80165d4: f7ff fd85 bl 80160e2 <__lo0bits> 80165d8: e9dd 1200 ldrd r1, r2, [sp] 80165dc: b1d8 cbz r0, 8016616 <__d2b+0x7e> 80165de: f1c0 0320 rsb r3, r0, #32 80165e2: fa02 f303 lsl.w r3, r2, r3 80165e6: 430b orrs r3, r1 80165e8: 40c2 lsrs r2, r0 80165ea: 6163 str r3, [r4, #20] 80165ec: 9201 str r2, [sp, #4] 80165ee: 9b01 ldr r3, [sp, #4] 80165f0: 2b00 cmp r3, #0 80165f2: bf0c ite eq 80165f4: 2201 moveq r2, #1 80165f6: 2202 movne r2, #2 80165f8: 61a3 str r3, [r4, #24] 80165fa: 6122 str r2, [r4, #16] 80165fc: b1ad cbz r5, 801662a <__d2b+0x92> 80165fe: f2a5 4533 subw r5, r5, #1075 @ 0x433 8016602: 4405 add r5, r0 8016604: 6035 str r5, [r6, #0] 8016606: f1c0 0035 rsb r0, r0, #53 @ 0x35 801660a: 9b09 ldr r3, [sp, #36] @ 0x24 801660c: 6018 str r0, [r3, #0] 801660e: 4620 mov r0, r4 8016610: b002 add sp, #8 8016612: e8bd 8370 ldmia.w sp!, {r4, r5, r6, r8, r9, pc} 8016616: 6161 str r1, [r4, #20] 8016618: e7e9 b.n 80165ee <__d2b+0x56> 801661a: a801 add r0, sp, #4 801661c: f7ff fd61 bl 80160e2 <__lo0bits> 8016620: 9b01 ldr r3, [sp, #4] 8016622: 2201 movs r2, #1 8016624: 6163 str r3, [r4, #20] 8016626: 3020 adds r0, #32 8016628: e7e7 b.n 80165fa <__d2b+0x62> 801662a: f2a0 4032 subw r0, r0, #1074 @ 0x432 801662e: eb04 0382 add.w r3, r4, r2, lsl #2 8016632: 6030 str r0, [r6, #0] 8016634: 6918 ldr r0, [r3, #16] 8016636: f7ff fd35 bl 80160a4 <__hi0bits> 801663a: ebc0 1042 rsb r0, r0, r2, lsl #5 801663e: e7e4 b.n 801660a <__d2b+0x72> 8016640: 080179d8 .word 0x080179d8 8016644: 080179fa .word 0x080179fa 08016648 <__sread>: 8016648: b510 push {r4, lr} 801664a: 460c mov r4, r1 801664c: f9b1 100e ldrsh.w r1, [r1, #14] 8016650: f000 f8aa bl 80167a8 <_read_r> 8016654: 2800 cmp r0, #0 8016656: bfab itete ge 8016658: 6d63 ldrge r3, [r4, #84] @ 0x54 801665a: 89a3 ldrhlt r3, [r4, #12] 801665c: 181b addge r3, r3, r0 801665e: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 8016662: bfac ite ge 8016664: 6563 strge r3, [r4, #84] @ 0x54 8016666: 81a3 strhlt r3, [r4, #12] 8016668: bd10 pop {r4, pc} 0801666a <__swrite>: 801666a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 801666e: 461f mov r7, r3 8016670: 898b ldrh r3, [r1, #12] 8016672: 4605 mov r5, r0 8016674: 05db lsls r3, r3, #23 8016676: 460c mov r4, r1 8016678: 4616 mov r6, r2 801667a: d505 bpl.n 8016688 <__swrite+0x1e> 801667c: 2302 movs r3, #2 801667e: 2200 movs r2, #0 8016680: f9b1 100e ldrsh.w r1, [r1, #14] 8016684: f000 f87e bl 8016784 <_lseek_r> 8016688: 89a3 ldrh r3, [r4, #12] 801668a: 4632 mov r2, r6 801668c: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8016690: 81a3 strh r3, [r4, #12] 8016692: 4628 mov r0, r5 8016694: 463b mov r3, r7 8016696: f9b4 100e ldrsh.w r1, [r4, #14] 801669a: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 801669e: f000 b8a5 b.w 80167ec <_write_r> 080166a2 <__sseek>: 80166a2: b510 push {r4, lr} 80166a4: 460c mov r4, r1 80166a6: f9b1 100e ldrsh.w r1, [r1, #14] 80166aa: f000 f86b bl 8016784 <_lseek_r> 80166ae: 1c43 adds r3, r0, #1 80166b0: 89a3 ldrh r3, [r4, #12] 80166b2: bf15 itete ne 80166b4: 6560 strne r0, [r4, #84] @ 0x54 80166b6: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 80166ba: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 80166be: 81a3 strheq r3, [r4, #12] 80166c0: bf18 it ne 80166c2: 81a3 strhne r3, [r4, #12] 80166c4: bd10 pop {r4, pc} 080166c6 <__sclose>: 80166c6: f9b1 100e ldrsh.w r1, [r1, #14] 80166ca: f000 b8a1 b.w 8016810 <_close_r> ... 080166d0 : 80166d0: b40e push {r1, r2, r3} 80166d2: b503 push {r0, r1, lr} 80166d4: 4601 mov r1, r0 80166d6: ab03 add r3, sp, #12 80166d8: 4805 ldr r0, [pc, #20] @ (80166f0 ) 80166da: f853 2b04 ldr.w r2, [r3], #4 80166de: 6800 ldr r0, [r0, #0] 80166e0: 9301 str r3, [sp, #4] 80166e2: f000 f931 bl 8016948 <_vfiprintf_r> 80166e6: b002 add sp, #8 80166e8: f85d eb04 ldr.w lr, [sp], #4 80166ec: b003 add sp, #12 80166ee: 4770 bx lr 80166f0: 2000009c .word 0x2000009c 080166f4 <_realloc_r>: 80166f4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80166f8: 4607 mov r7, r0 80166fa: 4614 mov r4, r2 80166fc: 460d mov r5, r1 80166fe: b921 cbnz r1, 801670a <_realloc_r+0x16> 8016700: 4611 mov r1, r2 8016702: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8016706: f7ff baf1 b.w 8015cec <_malloc_r> 801670a: b92a cbnz r2, 8016718 <_realloc_r+0x24> 801670c: f000 f8ac bl 8016868 <_free_r> 8016710: 4625 mov r5, r4 8016712: 4628 mov r0, r5 8016714: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8016718: f000 fa40 bl 8016b9c <_malloc_usable_size_r> 801671c: 4284 cmp r4, r0 801671e: 4606 mov r6, r0 8016720: d802 bhi.n 8016728 <_realloc_r+0x34> 8016722: ebb4 0f50 cmp.w r4, r0, lsr #1 8016726: d8f4 bhi.n 8016712 <_realloc_r+0x1e> 8016728: 4621 mov r1, r4 801672a: 4638 mov r0, r7 801672c: f7ff fade bl 8015cec <_malloc_r> 8016730: 4680 mov r8, r0 8016732: b908 cbnz r0, 8016738 <_realloc_r+0x44> 8016734: 4645 mov r5, r8 8016736: e7ec b.n 8016712 <_realloc_r+0x1e> 8016738: 42b4 cmp r4, r6 801673a: 4622 mov r2, r4 801673c: 4629 mov r1, r5 801673e: bf28 it cs 8016740: 4632 movcs r2, r6 8016742: f7fe fac9 bl 8014cd8 8016746: 4629 mov r1, r5 8016748: 4638 mov r0, r7 801674a: f000 f88d bl 8016868 <_free_r> 801674e: e7f1 b.n 8016734 <_realloc_r+0x40> 08016750 : 8016750: 4288 cmp r0, r1 8016752: b510 push {r4, lr} 8016754: eb01 0402 add.w r4, r1, r2 8016758: d902 bls.n 8016760 801675a: 4284 cmp r4, r0 801675c: 4623 mov r3, r4 801675e: d807 bhi.n 8016770 8016760: 1e43 subs r3, r0, #1 8016762: 42a1 cmp r1, r4 8016764: d008 beq.n 8016778 8016766: f811 2b01 ldrb.w r2, [r1], #1 801676a: f803 2f01 strb.w r2, [r3, #1]! 801676e: e7f8 b.n 8016762 8016770: 4601 mov r1, r0 8016772: 4402 add r2, r0 8016774: 428a cmp r2, r1 8016776: d100 bne.n 801677a 8016778: bd10 pop {r4, pc} 801677a: f813 4d01 ldrb.w r4, [r3, #-1]! 801677e: f802 4d01 strb.w r4, [r2, #-1]! 8016782: e7f7 b.n 8016774 08016784 <_lseek_r>: 8016784: b538 push {r3, r4, r5, lr} 8016786: 4604 mov r4, r0 8016788: 4608 mov r0, r1 801678a: 4611 mov r1, r2 801678c: 2200 movs r2, #0 801678e: 4d05 ldr r5, [pc, #20] @ (80167a4 <_lseek_r+0x20>) 8016790: 602a str r2, [r5, #0] 8016792: 461a mov r2, r3 8016794: f7f7 f877 bl 800d886 <_lseek> 8016798: 1c43 adds r3, r0, #1 801679a: d102 bne.n 80167a2 <_lseek_r+0x1e> 801679c: 682b ldr r3, [r5, #0] 801679e: b103 cbz r3, 80167a2 <_lseek_r+0x1e> 80167a0: 6023 str r3, [r4, #0] 80167a2: bd38 pop {r3, r4, r5, pc} 80167a4: 200015d4 .word 0x200015d4 080167a8 <_read_r>: 80167a8: b538 push {r3, r4, r5, lr} 80167aa: 4604 mov r4, r0 80167ac: 4608 mov r0, r1 80167ae: 4611 mov r1, r2 80167b0: 2200 movs r2, #0 80167b2: 4d05 ldr r5, [pc, #20] @ (80167c8 <_read_r+0x20>) 80167b4: 602a str r2, [r5, #0] 80167b6: 461a mov r2, r3 80167b8: f7f7 f824 bl 800d804 <_read> 80167bc: 1c43 adds r3, r0, #1 80167be: d102 bne.n 80167c6 <_read_r+0x1e> 80167c0: 682b ldr r3, [r5, #0] 80167c2: b103 cbz r3, 80167c6 <_read_r+0x1e> 80167c4: 6023 str r3, [r4, #0] 80167c6: bd38 pop {r3, r4, r5, pc} 80167c8: 200015d4 .word 0x200015d4 080167cc <_sbrk_r>: 80167cc: b538 push {r3, r4, r5, lr} 80167ce: 2300 movs r3, #0 80167d0: 4d05 ldr r5, [pc, #20] @ (80167e8 <_sbrk_r+0x1c>) 80167d2: 4604 mov r4, r0 80167d4: 4608 mov r0, r1 80167d6: 602b str r3, [r5, #0] 80167d8: f7f7 f862 bl 800d8a0 <_sbrk> 80167dc: 1c43 adds r3, r0, #1 80167de: d102 bne.n 80167e6 <_sbrk_r+0x1a> 80167e0: 682b ldr r3, [r5, #0] 80167e2: b103 cbz r3, 80167e6 <_sbrk_r+0x1a> 80167e4: 6023 str r3, [r4, #0] 80167e6: bd38 pop {r3, r4, r5, pc} 80167e8: 200015d4 .word 0x200015d4 080167ec <_write_r>: 80167ec: b538 push {r3, r4, r5, lr} 80167ee: 4604 mov r4, r0 80167f0: 4608 mov r0, r1 80167f2: 4611 mov r1, r2 80167f4: 2200 movs r2, #0 80167f6: 4d05 ldr r5, [pc, #20] @ (801680c <_write_r+0x20>) 80167f8: 602a str r2, [r5, #0] 80167fa: 461a mov r2, r3 80167fc: f7f3 fd94 bl 800a328 <_write> 8016800: 1c43 adds r3, r0, #1 8016802: d102 bne.n 801680a <_write_r+0x1e> 8016804: 682b ldr r3, [r5, #0] 8016806: b103 cbz r3, 801680a <_write_r+0x1e> 8016808: 6023 str r3, [r4, #0] 801680a: bd38 pop {r3, r4, r5, pc} 801680c: 200015d4 .word 0x200015d4 08016810 <_close_r>: 8016810: b538 push {r3, r4, r5, lr} 8016812: 2300 movs r3, #0 8016814: 4d05 ldr r5, [pc, #20] @ (801682c <_close_r+0x1c>) 8016816: 4604 mov r4, r0 8016818: 4608 mov r0, r1 801681a: 602b str r3, [r5, #0] 801681c: f7f7 f80f bl 800d83e <_close> 8016820: 1c43 adds r3, r0, #1 8016822: d102 bne.n 801682a <_close_r+0x1a> 8016824: 682b ldr r3, [r5, #0] 8016826: b103 cbz r3, 801682a <_close_r+0x1a> 8016828: 6023 str r3, [r4, #0] 801682a: bd38 pop {r3, r4, r5, pc} 801682c: 200015d4 .word 0x200015d4 08016830 : 8016830: 2006 movs r0, #6 8016832: b508 push {r3, lr} 8016834: f000 fae4 bl 8016e00 8016838: 2001 movs r0, #1 801683a: f7f6 ffd8 bl 800d7ee <_exit> 0801683e <_calloc_r>: 801683e: b570 push {r4, r5, r6, lr} 8016840: fba1 5402 umull r5, r4, r1, r2 8016844: b934 cbnz r4, 8016854 <_calloc_r+0x16> 8016846: 4629 mov r1, r5 8016848: f7ff fa50 bl 8015cec <_malloc_r> 801684c: 4606 mov r6, r0 801684e: b928 cbnz r0, 801685c <_calloc_r+0x1e> 8016850: 4630 mov r0, r6 8016852: bd70 pop {r4, r5, r6, pc} 8016854: 220c movs r2, #12 8016856: 2600 movs r6, #0 8016858: 6002 str r2, [r0, #0] 801685a: e7f9 b.n 8016850 <_calloc_r+0x12> 801685c: 462a mov r2, r5 801685e: 4621 mov r1, r4 8016860: f7fe f9f2 bl 8014c48 8016864: e7f4 b.n 8016850 <_calloc_r+0x12> ... 08016868 <_free_r>: 8016868: b538 push {r3, r4, r5, lr} 801686a: 4605 mov r5, r0 801686c: 2900 cmp r1, #0 801686e: d040 beq.n 80168f2 <_free_r+0x8a> 8016870: f851 3c04 ldr.w r3, [r1, #-4] 8016874: 1f0c subs r4, r1, #4 8016876: 2b00 cmp r3, #0 8016878: bfb8 it lt 801687a: 18e4 addlt r4, r4, r3 801687c: f7ff fb5e bl 8015f3c <__malloc_lock> 8016880: 4a1c ldr r2, [pc, #112] @ (80168f4 <_free_r+0x8c>) 8016882: 6813 ldr r3, [r2, #0] 8016884: b933 cbnz r3, 8016894 <_free_r+0x2c> 8016886: 6063 str r3, [r4, #4] 8016888: 6014 str r4, [r2, #0] 801688a: 4628 mov r0, r5 801688c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8016890: f7ff bb5a b.w 8015f48 <__malloc_unlock> 8016894: 42a3 cmp r3, r4 8016896: d908 bls.n 80168aa <_free_r+0x42> 8016898: 6820 ldr r0, [r4, #0] 801689a: 1821 adds r1, r4, r0 801689c: 428b cmp r3, r1 801689e: bf01 itttt eq 80168a0: 6819 ldreq r1, [r3, #0] 80168a2: 685b ldreq r3, [r3, #4] 80168a4: 1809 addeq r1, r1, r0 80168a6: 6021 streq r1, [r4, #0] 80168a8: e7ed b.n 8016886 <_free_r+0x1e> 80168aa: 461a mov r2, r3 80168ac: 685b ldr r3, [r3, #4] 80168ae: b10b cbz r3, 80168b4 <_free_r+0x4c> 80168b0: 42a3 cmp r3, r4 80168b2: d9fa bls.n 80168aa <_free_r+0x42> 80168b4: 6811 ldr r1, [r2, #0] 80168b6: 1850 adds r0, r2, r1 80168b8: 42a0 cmp r0, r4 80168ba: d10b bne.n 80168d4 <_free_r+0x6c> 80168bc: 6820 ldr r0, [r4, #0] 80168be: 4401 add r1, r0 80168c0: 1850 adds r0, r2, r1 80168c2: 4283 cmp r3, r0 80168c4: 6011 str r1, [r2, #0] 80168c6: d1e0 bne.n 801688a <_free_r+0x22> 80168c8: 6818 ldr r0, [r3, #0] 80168ca: 685b ldr r3, [r3, #4] 80168cc: 4408 add r0, r1 80168ce: 6010 str r0, [r2, #0] 80168d0: 6053 str r3, [r2, #4] 80168d2: e7da b.n 801688a <_free_r+0x22> 80168d4: d902 bls.n 80168dc <_free_r+0x74> 80168d6: 230c movs r3, #12 80168d8: 602b str r3, [r5, #0] 80168da: e7d6 b.n 801688a <_free_r+0x22> 80168dc: 6820 ldr r0, [r4, #0] 80168de: 1821 adds r1, r4, r0 80168e0: 428b cmp r3, r1 80168e2: bf01 itttt eq 80168e4: 6819 ldreq r1, [r3, #0] 80168e6: 685b ldreq r3, [r3, #4] 80168e8: 1809 addeq r1, r1, r0 80168ea: 6021 streq r1, [r4, #0] 80168ec: 6063 str r3, [r4, #4] 80168ee: 6054 str r4, [r2, #4] 80168f0: e7cb b.n 801688a <_free_r+0x22> 80168f2: bd38 pop {r3, r4, r5, pc} 80168f4: 200015d0 .word 0x200015d0 080168f8 <__sfputc_r>: 80168f8: 6893 ldr r3, [r2, #8] 80168fa: b410 push {r4} 80168fc: 3b01 subs r3, #1 80168fe: 2b00 cmp r3, #0 8016900: 6093 str r3, [r2, #8] 8016902: da07 bge.n 8016914 <__sfputc_r+0x1c> 8016904: 6994 ldr r4, [r2, #24] 8016906: 42a3 cmp r3, r4 8016908: db01 blt.n 801690e <__sfputc_r+0x16> 801690a: 290a cmp r1, #10 801690c: d102 bne.n 8016914 <__sfputc_r+0x1c> 801690e: bc10 pop {r4} 8016910: f000 b94c b.w 8016bac <__swbuf_r> 8016914: 6813 ldr r3, [r2, #0] 8016916: 1c58 adds r0, r3, #1 8016918: 6010 str r0, [r2, #0] 801691a: 7019 strb r1, [r3, #0] 801691c: 4608 mov r0, r1 801691e: bc10 pop {r4} 8016920: 4770 bx lr 08016922 <__sfputs_r>: 8016922: b5f8 push {r3, r4, r5, r6, r7, lr} 8016924: 4606 mov r6, r0 8016926: 460f mov r7, r1 8016928: 4614 mov r4, r2 801692a: 18d5 adds r5, r2, r3 801692c: 42ac cmp r4, r5 801692e: d101 bne.n 8016934 <__sfputs_r+0x12> 8016930: 2000 movs r0, #0 8016932: e007 b.n 8016944 <__sfputs_r+0x22> 8016934: 463a mov r2, r7 8016936: 4630 mov r0, r6 8016938: f814 1b01 ldrb.w r1, [r4], #1 801693c: f7ff ffdc bl 80168f8 <__sfputc_r> 8016940: 1c43 adds r3, r0, #1 8016942: d1f3 bne.n 801692c <__sfputs_r+0xa> 8016944: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 08016948 <_vfiprintf_r>: 8016948: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801694c: 460d mov r5, r1 801694e: 4614 mov r4, r2 8016950: 4698 mov r8, r3 8016952: 4606 mov r6, r0 8016954: b09d sub sp, #116 @ 0x74 8016956: b118 cbz r0, 8016960 <_vfiprintf_r+0x18> 8016958: 6a03 ldr r3, [r0, #32] 801695a: b90b cbnz r3, 8016960 <_vfiprintf_r+0x18> 801695c: f7fe f902 bl 8014b64 <__sinit> 8016960: 6e6b ldr r3, [r5, #100] @ 0x64 8016962: 07d9 lsls r1, r3, #31 8016964: d405 bmi.n 8016972 <_vfiprintf_r+0x2a> 8016966: 89ab ldrh r3, [r5, #12] 8016968: 059a lsls r2, r3, #22 801696a: d402 bmi.n 8016972 <_vfiprintf_r+0x2a> 801696c: 6da8 ldr r0, [r5, #88] @ 0x58 801696e: f7fe f99e bl 8014cae <__retarget_lock_acquire_recursive> 8016972: 89ab ldrh r3, [r5, #12] 8016974: 071b lsls r3, r3, #28 8016976: d501 bpl.n 801697c <_vfiprintf_r+0x34> 8016978: 692b ldr r3, [r5, #16] 801697a: b99b cbnz r3, 80169a4 <_vfiprintf_r+0x5c> 801697c: 4629 mov r1, r5 801697e: 4630 mov r0, r6 8016980: f000 f952 bl 8016c28 <__swsetup_r> 8016984: b170 cbz r0, 80169a4 <_vfiprintf_r+0x5c> 8016986: 6e6b ldr r3, [r5, #100] @ 0x64 8016988: 07dc lsls r4, r3, #31 801698a: d504 bpl.n 8016996 <_vfiprintf_r+0x4e> 801698c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016990: b01d add sp, #116 @ 0x74 8016992: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8016996: 89ab ldrh r3, [r5, #12] 8016998: 0598 lsls r0, r3, #22 801699a: d4f7 bmi.n 801698c <_vfiprintf_r+0x44> 801699c: 6da8 ldr r0, [r5, #88] @ 0x58 801699e: f7fe f987 bl 8014cb0 <__retarget_lock_release_recursive> 80169a2: e7f3 b.n 801698c <_vfiprintf_r+0x44> 80169a4: 2300 movs r3, #0 80169a6: 9309 str r3, [sp, #36] @ 0x24 80169a8: 2320 movs r3, #32 80169aa: f88d 3029 strb.w r3, [sp, #41] @ 0x29 80169ae: 2330 movs r3, #48 @ 0x30 80169b0: f04f 0901 mov.w r9, #1 80169b4: f8cd 800c str.w r8, [sp, #12] 80169b8: f8df 81a8 ldr.w r8, [pc, #424] @ 8016b64 <_vfiprintf_r+0x21c> 80169bc: f88d 302a strb.w r3, [sp, #42] @ 0x2a 80169c0: 4623 mov r3, r4 80169c2: 469a mov sl, r3 80169c4: f813 2b01 ldrb.w r2, [r3], #1 80169c8: b10a cbz r2, 80169ce <_vfiprintf_r+0x86> 80169ca: 2a25 cmp r2, #37 @ 0x25 80169cc: d1f9 bne.n 80169c2 <_vfiprintf_r+0x7a> 80169ce: ebba 0b04 subs.w fp, sl, r4 80169d2: d00b beq.n 80169ec <_vfiprintf_r+0xa4> 80169d4: 465b mov r3, fp 80169d6: 4622 mov r2, r4 80169d8: 4629 mov r1, r5 80169da: 4630 mov r0, r6 80169dc: f7ff ffa1 bl 8016922 <__sfputs_r> 80169e0: 3001 adds r0, #1 80169e2: f000 80a7 beq.w 8016b34 <_vfiprintf_r+0x1ec> 80169e6: 9a09 ldr r2, [sp, #36] @ 0x24 80169e8: 445a add r2, fp 80169ea: 9209 str r2, [sp, #36] @ 0x24 80169ec: f89a 3000 ldrb.w r3, [sl] 80169f0: 2b00 cmp r3, #0 80169f2: f000 809f beq.w 8016b34 <_vfiprintf_r+0x1ec> 80169f6: 2300 movs r3, #0 80169f8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80169fc: e9cd 2305 strd r2, r3, [sp, #20] 8016a00: f10a 0a01 add.w sl, sl, #1 8016a04: 9304 str r3, [sp, #16] 8016a06: 9307 str r3, [sp, #28] 8016a08: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8016a0c: 931a str r3, [sp, #104] @ 0x68 8016a0e: 4654 mov r4, sl 8016a10: 2205 movs r2, #5 8016a12: f814 1b01 ldrb.w r1, [r4], #1 8016a16: 4853 ldr r0, [pc, #332] @ (8016b64 <_vfiprintf_r+0x21c>) 8016a18: f7fe f950 bl 8014cbc 8016a1c: 9a04 ldr r2, [sp, #16] 8016a1e: b9d8 cbnz r0, 8016a58 <_vfiprintf_r+0x110> 8016a20: 06d1 lsls r1, r2, #27 8016a22: bf44 itt mi 8016a24: 2320 movmi r3, #32 8016a26: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8016a2a: 0713 lsls r3, r2, #28 8016a2c: bf44 itt mi 8016a2e: 232b movmi r3, #43 @ 0x2b 8016a30: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8016a34: f89a 3000 ldrb.w r3, [sl] 8016a38: 2b2a cmp r3, #42 @ 0x2a 8016a3a: d015 beq.n 8016a68 <_vfiprintf_r+0x120> 8016a3c: 4654 mov r4, sl 8016a3e: 2000 movs r0, #0 8016a40: f04f 0c0a mov.w ip, #10 8016a44: 9a07 ldr r2, [sp, #28] 8016a46: 4621 mov r1, r4 8016a48: f811 3b01 ldrb.w r3, [r1], #1 8016a4c: 3b30 subs r3, #48 @ 0x30 8016a4e: 2b09 cmp r3, #9 8016a50: d94b bls.n 8016aea <_vfiprintf_r+0x1a2> 8016a52: b1b0 cbz r0, 8016a82 <_vfiprintf_r+0x13a> 8016a54: 9207 str r2, [sp, #28] 8016a56: e014 b.n 8016a82 <_vfiprintf_r+0x13a> 8016a58: eba0 0308 sub.w r3, r0, r8 8016a5c: fa09 f303 lsl.w r3, r9, r3 8016a60: 4313 orrs r3, r2 8016a62: 46a2 mov sl, r4 8016a64: 9304 str r3, [sp, #16] 8016a66: e7d2 b.n 8016a0e <_vfiprintf_r+0xc6> 8016a68: 9b03 ldr r3, [sp, #12] 8016a6a: 1d19 adds r1, r3, #4 8016a6c: 681b ldr r3, [r3, #0] 8016a6e: 9103 str r1, [sp, #12] 8016a70: 2b00 cmp r3, #0 8016a72: bfbb ittet lt 8016a74: 425b neglt r3, r3 8016a76: f042 0202 orrlt.w r2, r2, #2 8016a7a: 9307 strge r3, [sp, #28] 8016a7c: 9307 strlt r3, [sp, #28] 8016a7e: bfb8 it lt 8016a80: 9204 strlt r2, [sp, #16] 8016a82: 7823 ldrb r3, [r4, #0] 8016a84: 2b2e cmp r3, #46 @ 0x2e 8016a86: d10a bne.n 8016a9e <_vfiprintf_r+0x156> 8016a88: 7863 ldrb r3, [r4, #1] 8016a8a: 2b2a cmp r3, #42 @ 0x2a 8016a8c: d132 bne.n 8016af4 <_vfiprintf_r+0x1ac> 8016a8e: 9b03 ldr r3, [sp, #12] 8016a90: 3402 adds r4, #2 8016a92: 1d1a adds r2, r3, #4 8016a94: 681b ldr r3, [r3, #0] 8016a96: 9203 str r2, [sp, #12] 8016a98: ea43 73e3 orr.w r3, r3, r3, asr #31 8016a9c: 9305 str r3, [sp, #20] 8016a9e: f8df a0c8 ldr.w sl, [pc, #200] @ 8016b68 <_vfiprintf_r+0x220> 8016aa2: 2203 movs r2, #3 8016aa4: 4650 mov r0, sl 8016aa6: 7821 ldrb r1, [r4, #0] 8016aa8: f7fe f908 bl 8014cbc 8016aac: b138 cbz r0, 8016abe <_vfiprintf_r+0x176> 8016aae: 2240 movs r2, #64 @ 0x40 8016ab0: 9b04 ldr r3, [sp, #16] 8016ab2: eba0 000a sub.w r0, r0, sl 8016ab6: 4082 lsls r2, r0 8016ab8: 4313 orrs r3, r2 8016aba: 3401 adds r4, #1 8016abc: 9304 str r3, [sp, #16] 8016abe: f814 1b01 ldrb.w r1, [r4], #1 8016ac2: 2206 movs r2, #6 8016ac4: 4829 ldr r0, [pc, #164] @ (8016b6c <_vfiprintf_r+0x224>) 8016ac6: f88d 1028 strb.w r1, [sp, #40] @ 0x28 8016aca: f7fe f8f7 bl 8014cbc 8016ace: 2800 cmp r0, #0 8016ad0: d03f beq.n 8016b52 <_vfiprintf_r+0x20a> 8016ad2: 4b27 ldr r3, [pc, #156] @ (8016b70 <_vfiprintf_r+0x228>) 8016ad4: bb1b cbnz r3, 8016b1e <_vfiprintf_r+0x1d6> 8016ad6: 9b03 ldr r3, [sp, #12] 8016ad8: 3307 adds r3, #7 8016ada: f023 0307 bic.w r3, r3, #7 8016ade: 3308 adds r3, #8 8016ae0: 9303 str r3, [sp, #12] 8016ae2: 9b09 ldr r3, [sp, #36] @ 0x24 8016ae4: 443b add r3, r7 8016ae6: 9309 str r3, [sp, #36] @ 0x24 8016ae8: e76a b.n 80169c0 <_vfiprintf_r+0x78> 8016aea: 460c mov r4, r1 8016aec: 2001 movs r0, #1 8016aee: fb0c 3202 mla r2, ip, r2, r3 8016af2: e7a8 b.n 8016a46 <_vfiprintf_r+0xfe> 8016af4: 2300 movs r3, #0 8016af6: f04f 0c0a mov.w ip, #10 8016afa: 4619 mov r1, r3 8016afc: 3401 adds r4, #1 8016afe: 9305 str r3, [sp, #20] 8016b00: 4620 mov r0, r4 8016b02: f810 2b01 ldrb.w r2, [r0], #1 8016b06: 3a30 subs r2, #48 @ 0x30 8016b08: 2a09 cmp r2, #9 8016b0a: d903 bls.n 8016b14 <_vfiprintf_r+0x1cc> 8016b0c: 2b00 cmp r3, #0 8016b0e: d0c6 beq.n 8016a9e <_vfiprintf_r+0x156> 8016b10: 9105 str r1, [sp, #20] 8016b12: e7c4 b.n 8016a9e <_vfiprintf_r+0x156> 8016b14: 4604 mov r4, r0 8016b16: 2301 movs r3, #1 8016b18: fb0c 2101 mla r1, ip, r1, r2 8016b1c: e7f0 b.n 8016b00 <_vfiprintf_r+0x1b8> 8016b1e: ab03 add r3, sp, #12 8016b20: 9300 str r3, [sp, #0] 8016b22: 462a mov r2, r5 8016b24: 4630 mov r0, r6 8016b26: 4b13 ldr r3, [pc, #76] @ (8016b74 <_vfiprintf_r+0x22c>) 8016b28: a904 add r1, sp, #16 8016b2a: f7fd fbd3 bl 80142d4 <_printf_float> 8016b2e: 4607 mov r7, r0 8016b30: 1c78 adds r0, r7, #1 8016b32: d1d6 bne.n 8016ae2 <_vfiprintf_r+0x19a> 8016b34: 6e6b ldr r3, [r5, #100] @ 0x64 8016b36: 07d9 lsls r1, r3, #31 8016b38: d405 bmi.n 8016b46 <_vfiprintf_r+0x1fe> 8016b3a: 89ab ldrh r3, [r5, #12] 8016b3c: 059a lsls r2, r3, #22 8016b3e: d402 bmi.n 8016b46 <_vfiprintf_r+0x1fe> 8016b40: 6da8 ldr r0, [r5, #88] @ 0x58 8016b42: f7fe f8b5 bl 8014cb0 <__retarget_lock_release_recursive> 8016b46: 89ab ldrh r3, [r5, #12] 8016b48: 065b lsls r3, r3, #25 8016b4a: f53f af1f bmi.w 801698c <_vfiprintf_r+0x44> 8016b4e: 9809 ldr r0, [sp, #36] @ 0x24 8016b50: e71e b.n 8016990 <_vfiprintf_r+0x48> 8016b52: ab03 add r3, sp, #12 8016b54: 9300 str r3, [sp, #0] 8016b56: 462a mov r2, r5 8016b58: 4630 mov r0, r6 8016b5a: 4b06 ldr r3, [pc, #24] @ (8016b74 <_vfiprintf_r+0x22c>) 8016b5c: a904 add r1, sp, #16 8016b5e: f7fd fe57 bl 8014810 <_printf_i> 8016b62: e7e4 b.n 8016b2e <_vfiprintf_r+0x1e6> 8016b64: 080179e9 .word 0x080179e9 8016b68: 080179ef .word 0x080179ef 8016b6c: 080179f3 .word 0x080179f3 8016b70: 080142d5 .word 0x080142d5 8016b74: 08016923 .word 0x08016923 08016b78 <__ascii_mbtowc>: 8016b78: b082 sub sp, #8 8016b7a: b901 cbnz r1, 8016b7e <__ascii_mbtowc+0x6> 8016b7c: a901 add r1, sp, #4 8016b7e: b142 cbz r2, 8016b92 <__ascii_mbtowc+0x1a> 8016b80: b14b cbz r3, 8016b96 <__ascii_mbtowc+0x1e> 8016b82: 7813 ldrb r3, [r2, #0] 8016b84: 600b str r3, [r1, #0] 8016b86: 7812 ldrb r2, [r2, #0] 8016b88: 1e10 subs r0, r2, #0 8016b8a: bf18 it ne 8016b8c: 2001 movne r0, #1 8016b8e: b002 add sp, #8 8016b90: 4770 bx lr 8016b92: 4610 mov r0, r2 8016b94: e7fb b.n 8016b8e <__ascii_mbtowc+0x16> 8016b96: f06f 0001 mvn.w r0, #1 8016b9a: e7f8 b.n 8016b8e <__ascii_mbtowc+0x16> 08016b9c <_malloc_usable_size_r>: 8016b9c: f851 3c04 ldr.w r3, [r1, #-4] 8016ba0: 1f18 subs r0, r3, #4 8016ba2: 2b00 cmp r3, #0 8016ba4: bfbc itt lt 8016ba6: 580b ldrlt r3, [r1, r0] 8016ba8: 18c0 addlt r0, r0, r3 8016baa: 4770 bx lr 08016bac <__swbuf_r>: 8016bac: b5f8 push {r3, r4, r5, r6, r7, lr} 8016bae: 460e mov r6, r1 8016bb0: 4614 mov r4, r2 8016bb2: 4605 mov r5, r0 8016bb4: b118 cbz r0, 8016bbe <__swbuf_r+0x12> 8016bb6: 6a03 ldr r3, [r0, #32] 8016bb8: b90b cbnz r3, 8016bbe <__swbuf_r+0x12> 8016bba: f7fd ffd3 bl 8014b64 <__sinit> 8016bbe: 69a3 ldr r3, [r4, #24] 8016bc0: 60a3 str r3, [r4, #8] 8016bc2: 89a3 ldrh r3, [r4, #12] 8016bc4: 071a lsls r2, r3, #28 8016bc6: d501 bpl.n 8016bcc <__swbuf_r+0x20> 8016bc8: 6923 ldr r3, [r4, #16] 8016bca: b943 cbnz r3, 8016bde <__swbuf_r+0x32> 8016bcc: 4621 mov r1, r4 8016bce: 4628 mov r0, r5 8016bd0: f000 f82a bl 8016c28 <__swsetup_r> 8016bd4: b118 cbz r0, 8016bde <__swbuf_r+0x32> 8016bd6: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff 8016bda: 4638 mov r0, r7 8016bdc: bdf8 pop {r3, r4, r5, r6, r7, pc} 8016bde: 6823 ldr r3, [r4, #0] 8016be0: 6922 ldr r2, [r4, #16] 8016be2: b2f6 uxtb r6, r6 8016be4: 1a98 subs r0, r3, r2 8016be6: 6963 ldr r3, [r4, #20] 8016be8: 4637 mov r7, r6 8016bea: 4283 cmp r3, r0 8016bec: dc05 bgt.n 8016bfa <__swbuf_r+0x4e> 8016bee: 4621 mov r1, r4 8016bf0: 4628 mov r0, r5 8016bf2: f7ff f97b bl 8015eec <_fflush_r> 8016bf6: 2800 cmp r0, #0 8016bf8: d1ed bne.n 8016bd6 <__swbuf_r+0x2a> 8016bfa: 68a3 ldr r3, [r4, #8] 8016bfc: 3b01 subs r3, #1 8016bfe: 60a3 str r3, [r4, #8] 8016c00: 6823 ldr r3, [r4, #0] 8016c02: 1c5a adds r2, r3, #1 8016c04: 6022 str r2, [r4, #0] 8016c06: 701e strb r6, [r3, #0] 8016c08: 6962 ldr r2, [r4, #20] 8016c0a: 1c43 adds r3, r0, #1 8016c0c: 429a cmp r2, r3 8016c0e: d004 beq.n 8016c1a <__swbuf_r+0x6e> 8016c10: 89a3 ldrh r3, [r4, #12] 8016c12: 07db lsls r3, r3, #31 8016c14: d5e1 bpl.n 8016bda <__swbuf_r+0x2e> 8016c16: 2e0a cmp r6, #10 8016c18: d1df bne.n 8016bda <__swbuf_r+0x2e> 8016c1a: 4621 mov r1, r4 8016c1c: 4628 mov r0, r5 8016c1e: f7ff f965 bl 8015eec <_fflush_r> 8016c22: 2800 cmp r0, #0 8016c24: d0d9 beq.n 8016bda <__swbuf_r+0x2e> 8016c26: e7d6 b.n 8016bd6 <__swbuf_r+0x2a> 08016c28 <__swsetup_r>: 8016c28: b538 push {r3, r4, r5, lr} 8016c2a: 4b29 ldr r3, [pc, #164] @ (8016cd0 <__swsetup_r+0xa8>) 8016c2c: 4605 mov r5, r0 8016c2e: 6818 ldr r0, [r3, #0] 8016c30: 460c mov r4, r1 8016c32: b118 cbz r0, 8016c3c <__swsetup_r+0x14> 8016c34: 6a03 ldr r3, [r0, #32] 8016c36: b90b cbnz r3, 8016c3c <__swsetup_r+0x14> 8016c38: f7fd ff94 bl 8014b64 <__sinit> 8016c3c: f9b4 300c ldrsh.w r3, [r4, #12] 8016c40: 0719 lsls r1, r3, #28 8016c42: d422 bmi.n 8016c8a <__swsetup_r+0x62> 8016c44: 06da lsls r2, r3, #27 8016c46: d407 bmi.n 8016c58 <__swsetup_r+0x30> 8016c48: 2209 movs r2, #9 8016c4a: 602a str r2, [r5, #0] 8016c4c: f043 0340 orr.w r3, r3, #64 @ 0x40 8016c50: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016c54: 81a3 strh r3, [r4, #12] 8016c56: e033 b.n 8016cc0 <__swsetup_r+0x98> 8016c58: 0758 lsls r0, r3, #29 8016c5a: d512 bpl.n 8016c82 <__swsetup_r+0x5a> 8016c5c: 6b61 ldr r1, [r4, #52] @ 0x34 8016c5e: b141 cbz r1, 8016c72 <__swsetup_r+0x4a> 8016c60: f104 0344 add.w r3, r4, #68 @ 0x44 8016c64: 4299 cmp r1, r3 8016c66: d002 beq.n 8016c6e <__swsetup_r+0x46> 8016c68: 4628 mov r0, r5 8016c6a: f7ff fdfd bl 8016868 <_free_r> 8016c6e: 2300 movs r3, #0 8016c70: 6363 str r3, [r4, #52] @ 0x34 8016c72: 89a3 ldrh r3, [r4, #12] 8016c74: f023 0324 bic.w r3, r3, #36 @ 0x24 8016c78: 81a3 strh r3, [r4, #12] 8016c7a: 2300 movs r3, #0 8016c7c: 6063 str r3, [r4, #4] 8016c7e: 6923 ldr r3, [r4, #16] 8016c80: 6023 str r3, [r4, #0] 8016c82: 89a3 ldrh r3, [r4, #12] 8016c84: f043 0308 orr.w r3, r3, #8 8016c88: 81a3 strh r3, [r4, #12] 8016c8a: 6923 ldr r3, [r4, #16] 8016c8c: b94b cbnz r3, 8016ca2 <__swsetup_r+0x7a> 8016c8e: 89a3 ldrh r3, [r4, #12] 8016c90: f403 7320 and.w r3, r3, #640 @ 0x280 8016c94: f5b3 7f00 cmp.w r3, #512 @ 0x200 8016c98: d003 beq.n 8016ca2 <__swsetup_r+0x7a> 8016c9a: 4621 mov r1, r4 8016c9c: 4628 mov r0, r5 8016c9e: f000 f84b bl 8016d38 <__smakebuf_r> 8016ca2: f9b4 300c ldrsh.w r3, [r4, #12] 8016ca6: f013 0201 ands.w r2, r3, #1 8016caa: d00a beq.n 8016cc2 <__swsetup_r+0x9a> 8016cac: 2200 movs r2, #0 8016cae: 60a2 str r2, [r4, #8] 8016cb0: 6962 ldr r2, [r4, #20] 8016cb2: 4252 negs r2, r2 8016cb4: 61a2 str r2, [r4, #24] 8016cb6: 6922 ldr r2, [r4, #16] 8016cb8: b942 cbnz r2, 8016ccc <__swsetup_r+0xa4> 8016cba: f013 0080 ands.w r0, r3, #128 @ 0x80 8016cbe: d1c5 bne.n 8016c4c <__swsetup_r+0x24> 8016cc0: bd38 pop {r3, r4, r5, pc} 8016cc2: 0799 lsls r1, r3, #30 8016cc4: bf58 it pl 8016cc6: 6962 ldrpl r2, [r4, #20] 8016cc8: 60a2 str r2, [r4, #8] 8016cca: e7f4 b.n 8016cb6 <__swsetup_r+0x8e> 8016ccc: 2000 movs r0, #0 8016cce: e7f7 b.n 8016cc0 <__swsetup_r+0x98> 8016cd0: 2000009c .word 0x2000009c 08016cd4 <__ascii_wctomb>: 8016cd4: 4603 mov r3, r0 8016cd6: 4608 mov r0, r1 8016cd8: b141 cbz r1, 8016cec <__ascii_wctomb+0x18> 8016cda: 2aff cmp r2, #255 @ 0xff 8016cdc: d904 bls.n 8016ce8 <__ascii_wctomb+0x14> 8016cde: 228a movs r2, #138 @ 0x8a 8016ce0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016ce4: 601a str r2, [r3, #0] 8016ce6: 4770 bx lr 8016ce8: 2001 movs r0, #1 8016cea: 700a strb r2, [r1, #0] 8016cec: 4770 bx lr 08016cee <__swhatbuf_r>: 8016cee: b570 push {r4, r5, r6, lr} 8016cf0: 460c mov r4, r1 8016cf2: f9b1 100e ldrsh.w r1, [r1, #14] 8016cf6: 4615 mov r5, r2 8016cf8: 2900 cmp r1, #0 8016cfa: 461e mov r6, r3 8016cfc: b096 sub sp, #88 @ 0x58 8016cfe: da0c bge.n 8016d1a <__swhatbuf_r+0x2c> 8016d00: 89a3 ldrh r3, [r4, #12] 8016d02: 2100 movs r1, #0 8016d04: f013 0f80 tst.w r3, #128 @ 0x80 8016d08: bf14 ite ne 8016d0a: 2340 movne r3, #64 @ 0x40 8016d0c: f44f 6380 moveq.w r3, #1024 @ 0x400 8016d10: 2000 movs r0, #0 8016d12: 6031 str r1, [r6, #0] 8016d14: 602b str r3, [r5, #0] 8016d16: b016 add sp, #88 @ 0x58 8016d18: bd70 pop {r4, r5, r6, pc} 8016d1a: 466a mov r2, sp 8016d1c: f000 f89c bl 8016e58 <_fstat_r> 8016d20: 2800 cmp r0, #0 8016d22: dbed blt.n 8016d00 <__swhatbuf_r+0x12> 8016d24: 9901 ldr r1, [sp, #4] 8016d26: f401 4170 and.w r1, r1, #61440 @ 0xf000 8016d2a: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 8016d2e: 4259 negs r1, r3 8016d30: 4159 adcs r1, r3 8016d32: f44f 6380 mov.w r3, #1024 @ 0x400 8016d36: e7eb b.n 8016d10 <__swhatbuf_r+0x22> 08016d38 <__smakebuf_r>: 8016d38: 898b ldrh r3, [r1, #12] 8016d3a: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8016d3c: 079d lsls r5, r3, #30 8016d3e: 4606 mov r6, r0 8016d40: 460c mov r4, r1 8016d42: d507 bpl.n 8016d54 <__smakebuf_r+0x1c> 8016d44: f104 0347 add.w r3, r4, #71 @ 0x47 8016d48: 6023 str r3, [r4, #0] 8016d4a: 6123 str r3, [r4, #16] 8016d4c: 2301 movs r3, #1 8016d4e: 6163 str r3, [r4, #20] 8016d50: b003 add sp, #12 8016d52: bdf0 pop {r4, r5, r6, r7, pc} 8016d54: 466a mov r2, sp 8016d56: ab01 add r3, sp, #4 8016d58: f7ff ffc9 bl 8016cee <__swhatbuf_r> 8016d5c: 9f00 ldr r7, [sp, #0] 8016d5e: 4605 mov r5, r0 8016d60: 4639 mov r1, r7 8016d62: 4630 mov r0, r6 8016d64: f7fe ffc2 bl 8015cec <_malloc_r> 8016d68: b948 cbnz r0, 8016d7e <__smakebuf_r+0x46> 8016d6a: f9b4 300c ldrsh.w r3, [r4, #12] 8016d6e: 059a lsls r2, r3, #22 8016d70: d4ee bmi.n 8016d50 <__smakebuf_r+0x18> 8016d72: f023 0303 bic.w r3, r3, #3 8016d76: f043 0302 orr.w r3, r3, #2 8016d7a: 81a3 strh r3, [r4, #12] 8016d7c: e7e2 b.n 8016d44 <__smakebuf_r+0xc> 8016d7e: 89a3 ldrh r3, [r4, #12] 8016d80: e9c4 0704 strd r0, r7, [r4, #16] 8016d84: f043 0380 orr.w r3, r3, #128 @ 0x80 8016d88: 81a3 strh r3, [r4, #12] 8016d8a: 9b01 ldr r3, [sp, #4] 8016d8c: 6020 str r0, [r4, #0] 8016d8e: b15b cbz r3, 8016da8 <__smakebuf_r+0x70> 8016d90: 4630 mov r0, r6 8016d92: f9b4 100e ldrsh.w r1, [r4, #14] 8016d96: f000 f83b bl 8016e10 <_isatty_r> 8016d9a: b128 cbz r0, 8016da8 <__smakebuf_r+0x70> 8016d9c: 89a3 ldrh r3, [r4, #12] 8016d9e: f023 0303 bic.w r3, r3, #3 8016da2: f043 0301 orr.w r3, r3, #1 8016da6: 81a3 strh r3, [r4, #12] 8016da8: 89a3 ldrh r3, [r4, #12] 8016daa: 431d orrs r5, r3 8016dac: 81a5 strh r5, [r4, #12] 8016dae: e7cf b.n 8016d50 <__smakebuf_r+0x18> 08016db0 <_raise_r>: 8016db0: 291f cmp r1, #31 8016db2: b538 push {r3, r4, r5, lr} 8016db4: 4605 mov r5, r0 8016db6: 460c mov r4, r1 8016db8: d904 bls.n 8016dc4 <_raise_r+0x14> 8016dba: 2316 movs r3, #22 8016dbc: 6003 str r3, [r0, #0] 8016dbe: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016dc2: bd38 pop {r3, r4, r5, pc} 8016dc4: 6bc2 ldr r2, [r0, #60] @ 0x3c 8016dc6: b112 cbz r2, 8016dce <_raise_r+0x1e> 8016dc8: f852 3021 ldr.w r3, [r2, r1, lsl #2] 8016dcc: b94b cbnz r3, 8016de2 <_raise_r+0x32> 8016dce: 4628 mov r0, r5 8016dd0: f000 f840 bl 8016e54 <_getpid_r> 8016dd4: 4622 mov r2, r4 8016dd6: 4601 mov r1, r0 8016dd8: 4628 mov r0, r5 8016dda: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8016dde: f000 b827 b.w 8016e30 <_kill_r> 8016de2: 2b01 cmp r3, #1 8016de4: d00a beq.n 8016dfc <_raise_r+0x4c> 8016de6: 1c59 adds r1, r3, #1 8016de8: d103 bne.n 8016df2 <_raise_r+0x42> 8016dea: 2316 movs r3, #22 8016dec: 6003 str r3, [r0, #0] 8016dee: 2001 movs r0, #1 8016df0: e7e7 b.n 8016dc2 <_raise_r+0x12> 8016df2: 2100 movs r1, #0 8016df4: 4620 mov r0, r4 8016df6: f842 1024 str.w r1, [r2, r4, lsl #2] 8016dfa: 4798 blx r3 8016dfc: 2000 movs r0, #0 8016dfe: e7e0 b.n 8016dc2 <_raise_r+0x12> 08016e00 : 8016e00: 4b02 ldr r3, [pc, #8] @ (8016e0c ) 8016e02: 4601 mov r1, r0 8016e04: 6818 ldr r0, [r3, #0] 8016e06: f7ff bfd3 b.w 8016db0 <_raise_r> 8016e0a: bf00 nop 8016e0c: 2000009c .word 0x2000009c 08016e10 <_isatty_r>: 8016e10: b538 push {r3, r4, r5, lr} 8016e12: 2300 movs r3, #0 8016e14: 4d05 ldr r5, [pc, #20] @ (8016e2c <_isatty_r+0x1c>) 8016e16: 4604 mov r4, r0 8016e18: 4608 mov r0, r1 8016e1a: 602b str r3, [r5, #0] 8016e1c: f7f6 fd29 bl 800d872 <_isatty> 8016e20: 1c43 adds r3, r0, #1 8016e22: d102 bne.n 8016e2a <_isatty_r+0x1a> 8016e24: 682b ldr r3, [r5, #0] 8016e26: b103 cbz r3, 8016e2a <_isatty_r+0x1a> 8016e28: 6023 str r3, [r4, #0] 8016e2a: bd38 pop {r3, r4, r5, pc} 8016e2c: 200015d4 .word 0x200015d4 08016e30 <_kill_r>: 8016e30: b538 push {r3, r4, r5, lr} 8016e32: 2300 movs r3, #0 8016e34: 4d06 ldr r5, [pc, #24] @ (8016e50 <_kill_r+0x20>) 8016e36: 4604 mov r4, r0 8016e38: 4608 mov r0, r1 8016e3a: 4611 mov r1, r2 8016e3c: 602b str r3, [r5, #0] 8016e3e: f7f6 fcc6 bl 800d7ce <_kill> 8016e42: 1c43 adds r3, r0, #1 8016e44: d102 bne.n 8016e4c <_kill_r+0x1c> 8016e46: 682b ldr r3, [r5, #0] 8016e48: b103 cbz r3, 8016e4c <_kill_r+0x1c> 8016e4a: 6023 str r3, [r4, #0] 8016e4c: bd38 pop {r3, r4, r5, pc} 8016e4e: bf00 nop 8016e50: 200015d4 .word 0x200015d4 08016e54 <_getpid_r>: 8016e54: f7f6 bcb4 b.w 800d7c0 <_getpid> 08016e58 <_fstat_r>: 8016e58: b538 push {r3, r4, r5, lr} 8016e5a: 2300 movs r3, #0 8016e5c: 4d06 ldr r5, [pc, #24] @ (8016e78 <_fstat_r+0x20>) 8016e5e: 4604 mov r4, r0 8016e60: 4608 mov r0, r1 8016e62: 4611 mov r1, r2 8016e64: 602b str r3, [r5, #0] 8016e66: f7f6 fcf5 bl 800d854 <_fstat> 8016e6a: 1c43 adds r3, r0, #1 8016e6c: d102 bne.n 8016e74 <_fstat_r+0x1c> 8016e6e: 682b ldr r3, [r5, #0] 8016e70: b103 cbz r3, 8016e74 <_fstat_r+0x1c> 8016e72: 6023 str r3, [r4, #0] 8016e74: bd38 pop {r3, r4, r5, pc} 8016e76: bf00 nop 8016e78: 200015d4 .word 0x200015d4 08016e7c <_init>: 8016e7c: b5f8 push {r3, r4, r5, r6, r7, lr} 8016e7e: bf00 nop 8016e80: bcf8 pop {r3, r4, r5, r6, r7} 8016e82: bc08 pop {r3} 8016e84: 469e mov lr, r3 8016e86: 4770 bx lr 08016e88 <_fini>: 8016e88: b5f8 push {r3, r4, r5, r6, r7, lr} 8016e8a: bf00 nop 8016e8c: bcf8 pop {r3, r4, r5, r6, r7} 8016e8e: bc08 pop {r3} 8016e90: 469e mov lr, r3 8016e92: 4770 bx lr