CCSModuleSW30Web.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001e4 08008000 08008000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000bd94 080081e8 080081e8 000011e8 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 000004ac 08013f7c 08013f7c 0000cf7c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08014428 08014428 0000e0d4 2**0 CONTENTS 4 .ARM 00000008 08014428 08014428 0000d428 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 08014430 08014430 0000e0d4 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08014430 08014430 0000d430 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08014434 08014434 0000d434 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 000000d4 20000000 08014438 0000e000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000010e8 200000d8 0801450c 0000e0d8 2**3 ALLOC 10 ._user_heap_stack 00000600 200011c0 0801450c 0000e1c0 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 0000e0d4 2**0 CONTENTS, READONLY 12 .debug_info 0001bc59 00000000 00000000 0000e0fd 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 0000546b 00000000 00000000 00029d56 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 000016c0 00000000 00000000 0002f1c8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00001178 00000000 00000000 00030888 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00026207 00000000 00000000 00031a00 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0002117c 00000000 00000000 00057c07 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000c970b 00000000 00000000 00078d83 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 0014248e 2**0 CONTENTS, READONLY 20 .debug_frame 00006588 00000000 00000000 001424d4 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000063 00000000 00000000 00148a5c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080081e8 <__do_global_dtors_aux>: 80081e8: b510 push {r4, lr} 80081ea: 4c05 ldr r4, [pc, #20] @ (8008200 <__do_global_dtors_aux+0x18>) 80081ec: 7823 ldrb r3, [r4, #0] 80081ee: b933 cbnz r3, 80081fe <__do_global_dtors_aux+0x16> 80081f0: 4b04 ldr r3, [pc, #16] @ (8008204 <__do_global_dtors_aux+0x1c>) 80081f2: b113 cbz r3, 80081fa <__do_global_dtors_aux+0x12> 80081f4: 4804 ldr r0, [pc, #16] @ (8008208 <__do_global_dtors_aux+0x20>) 80081f6: f3af 8000 nop.w 80081fa: 2301 movs r3, #1 80081fc: 7023 strb r3, [r4, #0] 80081fe: bd10 pop {r4, pc} 8008200: 200000d8 .word 0x200000d8 8008204: 00000000 .word 0x00000000 8008208: 08013f64 .word 0x08013f64 0800820c : 800820c: b508 push {r3, lr} 800820e: 4b03 ldr r3, [pc, #12] @ (800821c ) 8008210: b11b cbz r3, 800821a 8008212: 4903 ldr r1, [pc, #12] @ (8008220 ) 8008214: 4803 ldr r0, [pc, #12] @ (8008224 ) 8008216: f3af 8000 nop.w 800821a: bd08 pop {r3, pc} 800821c: 00000000 .word 0x00000000 8008220: 200000dc .word 0x200000dc 8008224: 08013f64 .word 0x08013f64 08008228 <__aeabi_drsub>: 8008228: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 800822c: e002 b.n 8008234 <__adddf3> 800822e: bf00 nop 08008230 <__aeabi_dsub>: 8008230: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 08008234 <__adddf3>: 8008234: b530 push {r4, r5, lr} 8008236: ea4f 0441 mov.w r4, r1, lsl #1 800823a: ea4f 0543 mov.w r5, r3, lsl #1 800823e: ea94 0f05 teq r4, r5 8008242: bf08 it eq 8008244: ea90 0f02 teqeq r0, r2 8008248: bf1f itttt ne 800824a: ea54 0c00 orrsne.w ip, r4, r0 800824e: ea55 0c02 orrsne.w ip, r5, r2 8008252: ea7f 5c64 mvnsne.w ip, r4, asr #21 8008256: ea7f 5c65 mvnsne.w ip, r5, asr #21 800825a: f000 80e2 beq.w 8008422 <__adddf3+0x1ee> 800825e: ea4f 5454 mov.w r4, r4, lsr #21 8008262: ebd4 5555 rsbs r5, r4, r5, lsr #21 8008266: bfb8 it lt 8008268: 426d neglt r5, r5 800826a: dd0c ble.n 8008286 <__adddf3+0x52> 800826c: 442c add r4, r5 800826e: ea80 0202 eor.w r2, r0, r2 8008272: ea81 0303 eor.w r3, r1, r3 8008276: ea82 0000 eor.w r0, r2, r0 800827a: ea83 0101 eor.w r1, r3, r1 800827e: ea80 0202 eor.w r2, r0, r2 8008282: ea81 0303 eor.w r3, r1, r3 8008286: 2d36 cmp r5, #54 @ 0x36 8008288: bf88 it hi 800828a: bd30 pophi {r4, r5, pc} 800828c: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008290: ea4f 3101 mov.w r1, r1, lsl #12 8008294: f44f 1c80 mov.w ip, #1048576 @ 0x100000 8008298: ea4c 3111 orr.w r1, ip, r1, lsr #12 800829c: d002 beq.n 80082a4 <__adddf3+0x70> 800829e: 4240 negs r0, r0 80082a0: eb61 0141 sbc.w r1, r1, r1, lsl #1 80082a4: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 80082a8: ea4f 3303 mov.w r3, r3, lsl #12 80082ac: ea4c 3313 orr.w r3, ip, r3, lsr #12 80082b0: d002 beq.n 80082b8 <__adddf3+0x84> 80082b2: 4252 negs r2, r2 80082b4: eb63 0343 sbc.w r3, r3, r3, lsl #1 80082b8: ea94 0f05 teq r4, r5 80082bc: f000 80a7 beq.w 800840e <__adddf3+0x1da> 80082c0: f1a4 0401 sub.w r4, r4, #1 80082c4: f1d5 0e20 rsbs lr, r5, #32 80082c8: db0d blt.n 80082e6 <__adddf3+0xb2> 80082ca: fa02 fc0e lsl.w ip, r2, lr 80082ce: fa22 f205 lsr.w r2, r2, r5 80082d2: 1880 adds r0, r0, r2 80082d4: f141 0100 adc.w r1, r1, #0 80082d8: fa03 f20e lsl.w r2, r3, lr 80082dc: 1880 adds r0, r0, r2 80082de: fa43 f305 asr.w r3, r3, r5 80082e2: 4159 adcs r1, r3 80082e4: e00e b.n 8008304 <__adddf3+0xd0> 80082e6: f1a5 0520 sub.w r5, r5, #32 80082ea: f10e 0e20 add.w lr, lr, #32 80082ee: 2a01 cmp r2, #1 80082f0: fa03 fc0e lsl.w ip, r3, lr 80082f4: bf28 it cs 80082f6: f04c 0c02 orrcs.w ip, ip, #2 80082fa: fa43 f305 asr.w r3, r3, r5 80082fe: 18c0 adds r0, r0, r3 8008300: eb51 71e3 adcs.w r1, r1, r3, asr #31 8008304: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008308: d507 bpl.n 800831a <__adddf3+0xe6> 800830a: f04f 0e00 mov.w lr, #0 800830e: f1dc 0c00 rsbs ip, ip, #0 8008312: eb7e 0000 sbcs.w r0, lr, r0 8008316: eb6e 0101 sbc.w r1, lr, r1 800831a: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 800831e: d31b bcc.n 8008358 <__adddf3+0x124> 8008320: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 8008324: d30c bcc.n 8008340 <__adddf3+0x10c> 8008326: 0849 lsrs r1, r1, #1 8008328: ea5f 0030 movs.w r0, r0, rrx 800832c: ea4f 0c3c mov.w ip, ip, rrx 8008330: f104 0401 add.w r4, r4, #1 8008334: ea4f 5244 mov.w r2, r4, lsl #21 8008338: f512 0f80 cmn.w r2, #4194304 @ 0x400000 800833c: f080 809a bcs.w 8008474 <__adddf3+0x240> 8008340: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008344: bf08 it eq 8008346: ea5f 0c50 movseq.w ip, r0, lsr #1 800834a: f150 0000 adcs.w r0, r0, #0 800834e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008352: ea41 0105 orr.w r1, r1, r5 8008356: bd30 pop {r4, r5, pc} 8008358: ea5f 0c4c movs.w ip, ip, lsl #1 800835c: 4140 adcs r0, r0 800835e: eb41 0101 adc.w r1, r1, r1 8008362: 3c01 subs r4, #1 8008364: bf28 it cs 8008366: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 800836a: d2e9 bcs.n 8008340 <__adddf3+0x10c> 800836c: f091 0f00 teq r1, #0 8008370: bf04 itt eq 8008372: 4601 moveq r1, r0 8008374: 2000 moveq r0, #0 8008376: fab1 f381 clz r3, r1 800837a: bf08 it eq 800837c: 3320 addeq r3, #32 800837e: f1a3 030b sub.w r3, r3, #11 8008382: f1b3 0220 subs.w r2, r3, #32 8008386: da0c bge.n 80083a2 <__adddf3+0x16e> 8008388: 320c adds r2, #12 800838a: dd08 ble.n 800839e <__adddf3+0x16a> 800838c: f102 0c14 add.w ip, r2, #20 8008390: f1c2 020c rsb r2, r2, #12 8008394: fa01 f00c lsl.w r0, r1, ip 8008398: fa21 f102 lsr.w r1, r1, r2 800839c: e00c b.n 80083b8 <__adddf3+0x184> 800839e: f102 0214 add.w r2, r2, #20 80083a2: bfd8 it le 80083a4: f1c2 0c20 rsble ip, r2, #32 80083a8: fa01 f102 lsl.w r1, r1, r2 80083ac: fa20 fc0c lsr.w ip, r0, ip 80083b0: bfdc itt le 80083b2: ea41 010c orrle.w r1, r1, ip 80083b6: 4090 lslle r0, r2 80083b8: 1ae4 subs r4, r4, r3 80083ba: bfa2 ittt ge 80083bc: eb01 5104 addge.w r1, r1, r4, lsl #20 80083c0: 4329 orrge r1, r5 80083c2: bd30 popge {r4, r5, pc} 80083c4: ea6f 0404 mvn.w r4, r4 80083c8: 3c1f subs r4, #31 80083ca: da1c bge.n 8008406 <__adddf3+0x1d2> 80083cc: 340c adds r4, #12 80083ce: dc0e bgt.n 80083ee <__adddf3+0x1ba> 80083d0: f104 0414 add.w r4, r4, #20 80083d4: f1c4 0220 rsb r2, r4, #32 80083d8: fa20 f004 lsr.w r0, r0, r4 80083dc: fa01 f302 lsl.w r3, r1, r2 80083e0: ea40 0003 orr.w r0, r0, r3 80083e4: fa21 f304 lsr.w r3, r1, r4 80083e8: ea45 0103 orr.w r1, r5, r3 80083ec: bd30 pop {r4, r5, pc} 80083ee: f1c4 040c rsb r4, r4, #12 80083f2: f1c4 0220 rsb r2, r4, #32 80083f6: fa20 f002 lsr.w r0, r0, r2 80083fa: fa01 f304 lsl.w r3, r1, r4 80083fe: ea40 0003 orr.w r0, r0, r3 8008402: 4629 mov r1, r5 8008404: bd30 pop {r4, r5, pc} 8008406: fa21 f004 lsr.w r0, r1, r4 800840a: 4629 mov r1, r5 800840c: bd30 pop {r4, r5, pc} 800840e: f094 0f00 teq r4, #0 8008412: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 8008416: bf06 itte eq 8008418: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 800841c: 3401 addeq r4, #1 800841e: 3d01 subne r5, #1 8008420: e74e b.n 80082c0 <__adddf3+0x8c> 8008422: ea7f 5c64 mvns.w ip, r4, asr #21 8008426: bf18 it ne 8008428: ea7f 5c65 mvnsne.w ip, r5, asr #21 800842c: d029 beq.n 8008482 <__adddf3+0x24e> 800842e: ea94 0f05 teq r4, r5 8008432: bf08 it eq 8008434: ea90 0f02 teqeq r0, r2 8008438: d005 beq.n 8008446 <__adddf3+0x212> 800843a: ea54 0c00 orrs.w ip, r4, r0 800843e: bf04 itt eq 8008440: 4619 moveq r1, r3 8008442: 4610 moveq r0, r2 8008444: bd30 pop {r4, r5, pc} 8008446: ea91 0f03 teq r1, r3 800844a: bf1e ittt ne 800844c: 2100 movne r1, #0 800844e: 2000 movne r0, #0 8008450: bd30 popne {r4, r5, pc} 8008452: ea5f 5c54 movs.w ip, r4, lsr #21 8008456: d105 bne.n 8008464 <__adddf3+0x230> 8008458: 0040 lsls r0, r0, #1 800845a: 4149 adcs r1, r1 800845c: bf28 it cs 800845e: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 8008462: bd30 pop {r4, r5, pc} 8008464: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 8008468: bf3c itt cc 800846a: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 800846e: bd30 popcc {r4, r5, pc} 8008470: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008474: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 8008478: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 800847c: f04f 0000 mov.w r0, #0 8008480: bd30 pop {r4, r5, pc} 8008482: ea7f 5c64 mvns.w ip, r4, asr #21 8008486: bf1a itte ne 8008488: 4619 movne r1, r3 800848a: 4610 movne r0, r2 800848c: ea7f 5c65 mvnseq.w ip, r5, asr #21 8008490: bf1c itt ne 8008492: 460b movne r3, r1 8008494: 4602 movne r2, r0 8008496: ea50 3401 orrs.w r4, r0, r1, lsl #12 800849a: bf06 itte eq 800849c: ea52 3503 orrseq.w r5, r2, r3, lsl #12 80084a0: ea91 0f03 teqeq r1, r3 80084a4: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 80084a8: bd30 pop {r4, r5, pc} 80084aa: bf00 nop 080084ac <__aeabi_ui2d>: 80084ac: f090 0f00 teq r0, #0 80084b0: bf04 itt eq 80084b2: 2100 moveq r1, #0 80084b4: 4770 bxeq lr 80084b6: b530 push {r4, r5, lr} 80084b8: f44f 6480 mov.w r4, #1024 @ 0x400 80084bc: f104 0432 add.w r4, r4, #50 @ 0x32 80084c0: f04f 0500 mov.w r5, #0 80084c4: f04f 0100 mov.w r1, #0 80084c8: e750 b.n 800836c <__adddf3+0x138> 80084ca: bf00 nop 080084cc <__aeabi_i2d>: 80084cc: f090 0f00 teq r0, #0 80084d0: bf04 itt eq 80084d2: 2100 moveq r1, #0 80084d4: 4770 bxeq lr 80084d6: b530 push {r4, r5, lr} 80084d8: f44f 6480 mov.w r4, #1024 @ 0x400 80084dc: f104 0432 add.w r4, r4, #50 @ 0x32 80084e0: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 80084e4: bf48 it mi 80084e6: 4240 negmi r0, r0 80084e8: f04f 0100 mov.w r1, #0 80084ec: e73e b.n 800836c <__adddf3+0x138> 80084ee: bf00 nop 080084f0 <__aeabi_f2d>: 80084f0: 0042 lsls r2, r0, #1 80084f2: ea4f 01e2 mov.w r1, r2, asr #3 80084f6: ea4f 0131 mov.w r1, r1, rrx 80084fa: ea4f 7002 mov.w r0, r2, lsl #28 80084fe: bf1f itttt ne 8008500: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 8008504: f093 4f7f teqne r3, #4278190080 @ 0xff000000 8008508: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 800850c: 4770 bxne lr 800850e: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 8008512: bf08 it eq 8008514: 4770 bxeq lr 8008516: f093 4f7f teq r3, #4278190080 @ 0xff000000 800851a: bf04 itt eq 800851c: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 8008520: 4770 bxeq lr 8008522: b530 push {r4, r5, lr} 8008524: f44f 7460 mov.w r4, #896 @ 0x380 8008528: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 800852c: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 8008530: e71c b.n 800836c <__adddf3+0x138> 8008532: bf00 nop 08008534 <__aeabi_ul2d>: 8008534: ea50 0201 orrs.w r2, r0, r1 8008538: bf08 it eq 800853a: 4770 bxeq lr 800853c: b530 push {r4, r5, lr} 800853e: f04f 0500 mov.w r5, #0 8008542: e00a b.n 800855a <__aeabi_l2d+0x16> 08008544 <__aeabi_l2d>: 8008544: ea50 0201 orrs.w r2, r0, r1 8008548: bf08 it eq 800854a: 4770 bxeq lr 800854c: b530 push {r4, r5, lr} 800854e: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 8008552: d502 bpl.n 800855a <__aeabi_l2d+0x16> 8008554: 4240 negs r0, r0 8008556: eb61 0141 sbc.w r1, r1, r1, lsl #1 800855a: f44f 6480 mov.w r4, #1024 @ 0x400 800855e: f104 0432 add.w r4, r4, #50 @ 0x32 8008562: ea5f 5c91 movs.w ip, r1, lsr #22 8008566: f43f aed8 beq.w 800831a <__adddf3+0xe6> 800856a: f04f 0203 mov.w r2, #3 800856e: ea5f 0cdc movs.w ip, ip, lsr #3 8008572: bf18 it ne 8008574: 3203 addne r2, #3 8008576: ea5f 0cdc movs.w ip, ip, lsr #3 800857a: bf18 it ne 800857c: 3203 addne r2, #3 800857e: eb02 02dc add.w r2, r2, ip, lsr #3 8008582: f1c2 0320 rsb r3, r2, #32 8008586: fa00 fc03 lsl.w ip, r0, r3 800858a: fa20 f002 lsr.w r0, r0, r2 800858e: fa01 fe03 lsl.w lr, r1, r3 8008592: ea40 000e orr.w r0, r0, lr 8008596: fa21 f102 lsr.w r1, r1, r2 800859a: 4414 add r4, r2 800859c: e6bd b.n 800831a <__adddf3+0xe6> 800859e: bf00 nop 080085a0 <__aeabi_dmul>: 80085a0: b570 push {r4, r5, r6, lr} 80085a2: f04f 0cff mov.w ip, #255 @ 0xff 80085a6: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 80085aa: ea1c 5411 ands.w r4, ip, r1, lsr #20 80085ae: bf1d ittte ne 80085b0: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80085b4: ea94 0f0c teqne r4, ip 80085b8: ea95 0f0c teqne r5, ip 80085bc: f000 f8de bleq 800877c <__aeabi_dmul+0x1dc> 80085c0: 442c add r4, r5 80085c2: ea81 0603 eor.w r6, r1, r3 80085c6: ea21 514c bic.w r1, r1, ip, lsl #21 80085ca: ea23 534c bic.w r3, r3, ip, lsl #21 80085ce: ea50 3501 orrs.w r5, r0, r1, lsl #12 80085d2: bf18 it ne 80085d4: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80085d8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 80085dc: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80085e0: d038 beq.n 8008654 <__aeabi_dmul+0xb4> 80085e2: fba0 ce02 umull ip, lr, r0, r2 80085e6: f04f 0500 mov.w r5, #0 80085ea: fbe1 e502 umlal lr, r5, r1, r2 80085ee: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 80085f2: fbe0 e503 umlal lr, r5, r0, r3 80085f6: f04f 0600 mov.w r6, #0 80085fa: fbe1 5603 umlal r5, r6, r1, r3 80085fe: f09c 0f00 teq ip, #0 8008602: bf18 it ne 8008604: f04e 0e01 orrne.w lr, lr, #1 8008608: f1a4 04ff sub.w r4, r4, #255 @ 0xff 800860c: f5b6 7f00 cmp.w r6, #512 @ 0x200 8008610: f564 7440 sbc.w r4, r4, #768 @ 0x300 8008614: d204 bcs.n 8008620 <__aeabi_dmul+0x80> 8008616: ea5f 0e4e movs.w lr, lr, lsl #1 800861a: 416d adcs r5, r5 800861c: eb46 0606 adc.w r6, r6, r6 8008620: ea42 21c6 orr.w r1, r2, r6, lsl #11 8008624: ea41 5155 orr.w r1, r1, r5, lsr #21 8008628: ea4f 20c5 mov.w r0, r5, lsl #11 800862c: ea40 505e orr.w r0, r0, lr, lsr #21 8008630: ea4f 2ece mov.w lr, lr, lsl #11 8008634: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008638: bf88 it hi 800863a: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800863e: d81e bhi.n 800867e <__aeabi_dmul+0xde> 8008640: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 8008644: bf08 it eq 8008646: ea5f 0e50 movseq.w lr, r0, lsr #1 800864a: f150 0000 adcs.w r0, r0, #0 800864e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008652: bd70 pop {r4, r5, r6, pc} 8008654: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 8008658: ea46 0101 orr.w r1, r6, r1 800865c: ea40 0002 orr.w r0, r0, r2 8008660: ea81 0103 eor.w r1, r1, r3 8008664: ebb4 045c subs.w r4, r4, ip, lsr #1 8008668: bfc2 ittt gt 800866a: ebd4 050c rsbsgt r5, r4, ip 800866e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8008672: bd70 popgt {r4, r5, r6, pc} 8008674: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008678: f04f 0e00 mov.w lr, #0 800867c: 3c01 subs r4, #1 800867e: f300 80ab bgt.w 80087d8 <__aeabi_dmul+0x238> 8008682: f114 0f36 cmn.w r4, #54 @ 0x36 8008686: bfde ittt le 8008688: 2000 movle r0, #0 800868a: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 800868e: bd70 pople {r4, r5, r6, pc} 8008690: f1c4 0400 rsb r4, r4, #0 8008694: 3c20 subs r4, #32 8008696: da35 bge.n 8008704 <__aeabi_dmul+0x164> 8008698: 340c adds r4, #12 800869a: dc1b bgt.n 80086d4 <__aeabi_dmul+0x134> 800869c: f104 0414 add.w r4, r4, #20 80086a0: f1c4 0520 rsb r5, r4, #32 80086a4: fa00 f305 lsl.w r3, r0, r5 80086a8: fa20 f004 lsr.w r0, r0, r4 80086ac: fa01 f205 lsl.w r2, r1, r5 80086b0: ea40 0002 orr.w r0, r0, r2 80086b4: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 80086b8: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 80086bc: eb10 70d3 adds.w r0, r0, r3, lsr #31 80086c0: fa21 f604 lsr.w r6, r1, r4 80086c4: eb42 0106 adc.w r1, r2, r6 80086c8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80086cc: bf08 it eq 80086ce: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80086d2: bd70 pop {r4, r5, r6, pc} 80086d4: f1c4 040c rsb r4, r4, #12 80086d8: f1c4 0520 rsb r5, r4, #32 80086dc: fa00 f304 lsl.w r3, r0, r4 80086e0: fa20 f005 lsr.w r0, r0, r5 80086e4: fa01 f204 lsl.w r2, r1, r4 80086e8: ea40 0002 orr.w r0, r0, r2 80086ec: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80086f0: eb10 70d3 adds.w r0, r0, r3, lsr #31 80086f4: f141 0100 adc.w r1, r1, #0 80086f8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80086fc: bf08 it eq 80086fe: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8008702: bd70 pop {r4, r5, r6, pc} 8008704: f1c4 0520 rsb r5, r4, #32 8008708: fa00 f205 lsl.w r2, r0, r5 800870c: ea4e 0e02 orr.w lr, lr, r2 8008710: fa20 f304 lsr.w r3, r0, r4 8008714: fa01 f205 lsl.w r2, r1, r5 8008718: ea43 0302 orr.w r3, r3, r2 800871c: fa21 f004 lsr.w r0, r1, r4 8008720: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008724: fa21 f204 lsr.w r2, r1, r4 8008728: ea20 0002 bic.w r0, r0, r2 800872c: eb00 70d3 add.w r0, r0, r3, lsr #31 8008730: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8008734: bf08 it eq 8008736: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800873a: bd70 pop {r4, r5, r6, pc} 800873c: f094 0f00 teq r4, #0 8008740: d10f bne.n 8008762 <__aeabi_dmul+0x1c2> 8008742: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 8008746: 0040 lsls r0, r0, #1 8008748: eb41 0101 adc.w r1, r1, r1 800874c: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008750: bf08 it eq 8008752: 3c01 subeq r4, #1 8008754: d0f7 beq.n 8008746 <__aeabi_dmul+0x1a6> 8008756: ea41 0106 orr.w r1, r1, r6 800875a: f095 0f00 teq r5, #0 800875e: bf18 it ne 8008760: 4770 bxne lr 8008762: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 8008766: 0052 lsls r2, r2, #1 8008768: eb43 0303 adc.w r3, r3, r3 800876c: f413 1f80 tst.w r3, #1048576 @ 0x100000 8008770: bf08 it eq 8008772: 3d01 subeq r5, #1 8008774: d0f7 beq.n 8008766 <__aeabi_dmul+0x1c6> 8008776: ea43 0306 orr.w r3, r3, r6 800877a: 4770 bx lr 800877c: ea94 0f0c teq r4, ip 8008780: ea0c 5513 and.w r5, ip, r3, lsr #20 8008784: bf18 it ne 8008786: ea95 0f0c teqne r5, ip 800878a: d00c beq.n 80087a6 <__aeabi_dmul+0x206> 800878c: ea50 0641 orrs.w r6, r0, r1, lsl #1 8008790: bf18 it ne 8008792: ea52 0643 orrsne.w r6, r2, r3, lsl #1 8008796: d1d1 bne.n 800873c <__aeabi_dmul+0x19c> 8008798: ea81 0103 eor.w r1, r1, r3 800879c: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087a0: f04f 0000 mov.w r0, #0 80087a4: bd70 pop {r4, r5, r6, pc} 80087a6: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087aa: bf06 itte eq 80087ac: 4610 moveq r0, r2 80087ae: 4619 moveq r1, r3 80087b0: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087b4: d019 beq.n 80087ea <__aeabi_dmul+0x24a> 80087b6: ea94 0f0c teq r4, ip 80087ba: d102 bne.n 80087c2 <__aeabi_dmul+0x222> 80087bc: ea50 3601 orrs.w r6, r0, r1, lsl #12 80087c0: d113 bne.n 80087ea <__aeabi_dmul+0x24a> 80087c2: ea95 0f0c teq r5, ip 80087c6: d105 bne.n 80087d4 <__aeabi_dmul+0x234> 80087c8: ea52 3603 orrs.w r6, r2, r3, lsl #12 80087cc: bf1c itt ne 80087ce: 4610 movne r0, r2 80087d0: 4619 movne r1, r3 80087d2: d10a bne.n 80087ea <__aeabi_dmul+0x24a> 80087d4: ea81 0103 eor.w r1, r1, r3 80087d8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087dc: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087e0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 80087e4: f04f 0000 mov.w r0, #0 80087e8: bd70 pop {r4, r5, r6, pc} 80087ea: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087ee: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 80087f2: bd70 pop {r4, r5, r6, pc} 080087f4 <__aeabi_ddiv>: 80087f4: b570 push {r4, r5, r6, lr} 80087f6: f04f 0cff mov.w ip, #255 @ 0xff 80087fa: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 80087fe: ea1c 5411 ands.w r4, ip, r1, lsr #20 8008802: bf1d ittte ne 8008804: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8008808: ea94 0f0c teqne r4, ip 800880c: ea95 0f0c teqne r5, ip 8008810: f000 f8a7 bleq 8008962 <__aeabi_ddiv+0x16e> 8008814: eba4 0405 sub.w r4, r4, r5 8008818: ea81 0e03 eor.w lr, r1, r3 800881c: ea52 3503 orrs.w r5, r2, r3, lsl #12 8008820: ea4f 3101 mov.w r1, r1, lsl #12 8008824: f000 8088 beq.w 8008938 <__aeabi_ddiv+0x144> 8008828: ea4f 3303 mov.w r3, r3, lsl #12 800882c: f04f 5580 mov.w r5, #268435456 @ 0x10000000 8008830: ea45 1313 orr.w r3, r5, r3, lsr #4 8008834: ea43 6312 orr.w r3, r3, r2, lsr #24 8008838: ea4f 2202 mov.w r2, r2, lsl #8 800883c: ea45 1511 orr.w r5, r5, r1, lsr #4 8008840: ea45 6510 orr.w r5, r5, r0, lsr #24 8008844: ea4f 2600 mov.w r6, r0, lsl #8 8008848: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000 800884c: 429d cmp r5, r3 800884e: bf08 it eq 8008850: 4296 cmpeq r6, r2 8008852: f144 04fd adc.w r4, r4, #253 @ 0xfd 8008856: f504 7440 add.w r4, r4, #768 @ 0x300 800885a: d202 bcs.n 8008862 <__aeabi_ddiv+0x6e> 800885c: 085b lsrs r3, r3, #1 800885e: ea4f 0232 mov.w r2, r2, rrx 8008862: 1ab6 subs r6, r6, r2 8008864: eb65 0503 sbc.w r5, r5, r3 8008868: 085b lsrs r3, r3, #1 800886a: ea4f 0232 mov.w r2, r2, rrx 800886e: f44f 1080 mov.w r0, #1048576 @ 0x100000 8008872: f44f 2c00 mov.w ip, #524288 @ 0x80000 8008876: ebb6 0e02 subs.w lr, r6, r2 800887a: eb75 0e03 sbcs.w lr, r5, r3 800887e: bf22 ittt cs 8008880: 1ab6 subcs r6, r6, r2 8008882: 4675 movcs r5, lr 8008884: ea40 000c orrcs.w r0, r0, ip 8008888: 085b lsrs r3, r3, #1 800888a: ea4f 0232 mov.w r2, r2, rrx 800888e: ebb6 0e02 subs.w lr, r6, r2 8008892: eb75 0e03 sbcs.w lr, r5, r3 8008896: bf22 ittt cs 8008898: 1ab6 subcs r6, r6, r2 800889a: 4675 movcs r5, lr 800889c: ea40 005c orrcs.w r0, r0, ip, lsr #1 80088a0: 085b lsrs r3, r3, #1 80088a2: ea4f 0232 mov.w r2, r2, rrx 80088a6: ebb6 0e02 subs.w lr, r6, r2 80088aa: eb75 0e03 sbcs.w lr, r5, r3 80088ae: bf22 ittt cs 80088b0: 1ab6 subcs r6, r6, r2 80088b2: 4675 movcs r5, lr 80088b4: ea40 009c orrcs.w r0, r0, ip, lsr #2 80088b8: 085b lsrs r3, r3, #1 80088ba: ea4f 0232 mov.w r2, r2, rrx 80088be: ebb6 0e02 subs.w lr, r6, r2 80088c2: eb75 0e03 sbcs.w lr, r5, r3 80088c6: bf22 ittt cs 80088c8: 1ab6 subcs r6, r6, r2 80088ca: 4675 movcs r5, lr 80088cc: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80088d0: ea55 0e06 orrs.w lr, r5, r6 80088d4: d018 beq.n 8008908 <__aeabi_ddiv+0x114> 80088d6: ea4f 1505 mov.w r5, r5, lsl #4 80088da: ea45 7516 orr.w r5, r5, r6, lsr #28 80088de: ea4f 1606 mov.w r6, r6, lsl #4 80088e2: ea4f 03c3 mov.w r3, r3, lsl #3 80088e6: ea43 7352 orr.w r3, r3, r2, lsr #29 80088ea: ea4f 02c2 mov.w r2, r2, lsl #3 80088ee: ea5f 1c1c movs.w ip, ip, lsr #4 80088f2: d1c0 bne.n 8008876 <__aeabi_ddiv+0x82> 80088f4: f411 1f80 tst.w r1, #1048576 @ 0x100000 80088f8: d10b bne.n 8008912 <__aeabi_ddiv+0x11e> 80088fa: ea41 0100 orr.w r1, r1, r0 80088fe: f04f 0000 mov.w r0, #0 8008902: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000 8008906: e7b6 b.n 8008876 <__aeabi_ddiv+0x82> 8008908: f411 1f80 tst.w r1, #1048576 @ 0x100000 800890c: bf04 itt eq 800890e: 4301 orreq r1, r0 8008910: 2000 moveq r0, #0 8008912: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008916: bf88 it hi 8008918: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800891c: f63f aeaf bhi.w 800867e <__aeabi_dmul+0xde> 8008920: ebb5 0c03 subs.w ip, r5, r3 8008924: bf04 itt eq 8008926: ebb6 0c02 subseq.w ip, r6, r2 800892a: ea5f 0c50 movseq.w ip, r0, lsr #1 800892e: f150 0000 adcs.w r0, r0, #0 8008932: eb41 5104 adc.w r1, r1, r4, lsl #20 8008936: bd70 pop {r4, r5, r6, pc} 8008938: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000 800893c: ea4e 3111 orr.w r1, lr, r1, lsr #12 8008940: eb14 045c adds.w r4, r4, ip, lsr #1 8008944: bfc2 ittt gt 8008946: ebd4 050c rsbsgt r5, r4, ip 800894a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800894e: bd70 popgt {r4, r5, r6, pc} 8008950: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008954: f04f 0e00 mov.w lr, #0 8008958: 3c01 subs r4, #1 800895a: e690 b.n 800867e <__aeabi_dmul+0xde> 800895c: ea45 0e06 orr.w lr, r5, r6 8008960: e68d b.n 800867e <__aeabi_dmul+0xde> 8008962: ea0c 5513 and.w r5, ip, r3, lsr #20 8008966: ea94 0f0c teq r4, ip 800896a: bf08 it eq 800896c: ea95 0f0c teqeq r5, ip 8008970: f43f af3b beq.w 80087ea <__aeabi_dmul+0x24a> 8008974: ea94 0f0c teq r4, ip 8008978: d10a bne.n 8008990 <__aeabi_ddiv+0x19c> 800897a: ea50 3401 orrs.w r4, r0, r1, lsl #12 800897e: f47f af34 bne.w 80087ea <__aeabi_dmul+0x24a> 8008982: ea95 0f0c teq r5, ip 8008986: f47f af25 bne.w 80087d4 <__aeabi_dmul+0x234> 800898a: 4610 mov r0, r2 800898c: 4619 mov r1, r3 800898e: e72c b.n 80087ea <__aeabi_dmul+0x24a> 8008990: ea95 0f0c teq r5, ip 8008994: d106 bne.n 80089a4 <__aeabi_ddiv+0x1b0> 8008996: ea52 3503 orrs.w r5, r2, r3, lsl #12 800899a: f43f aefd beq.w 8008798 <__aeabi_dmul+0x1f8> 800899e: 4610 mov r0, r2 80089a0: 4619 mov r1, r3 80089a2: e722 b.n 80087ea <__aeabi_dmul+0x24a> 80089a4: ea50 0641 orrs.w r6, r0, r1, lsl #1 80089a8: bf18 it ne 80089aa: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80089ae: f47f aec5 bne.w 800873c <__aeabi_dmul+0x19c> 80089b2: ea50 0441 orrs.w r4, r0, r1, lsl #1 80089b6: f47f af0d bne.w 80087d4 <__aeabi_dmul+0x234> 80089ba: ea52 0543 orrs.w r5, r2, r3, lsl #1 80089be: f47f aeeb bne.w 8008798 <__aeabi_dmul+0x1f8> 80089c2: e712 b.n 80087ea <__aeabi_dmul+0x24a> 080089c4 <__aeabi_d2f>: 80089c4: ea4f 0241 mov.w r2, r1, lsl #1 80089c8: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000 80089cc: bf24 itt cs 80089ce: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000 80089d2: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000 80089d6: d90d bls.n 80089f4 <__aeabi_d2f+0x30> 80089d8: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 80089dc: ea4f 02c0 mov.w r2, r0, lsl #3 80089e0: ea4c 7050 orr.w r0, ip, r0, lsr #29 80089e4: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000 80089e8: eb40 0083 adc.w r0, r0, r3, lsl #2 80089ec: bf08 it eq 80089ee: f020 0001 biceq.w r0, r0, #1 80089f2: 4770 bx lr 80089f4: f011 4f80 tst.w r1, #1073741824 @ 0x40000000 80089f8: d121 bne.n 8008a3e <__aeabi_d2f+0x7a> 80089fa: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000 80089fe: bfbc itt lt 8008a00: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000 8008a04: 4770 bxlt lr 8008a06: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008a0a: ea4f 5252 mov.w r2, r2, lsr #21 8008a0e: f1c2 0218 rsb r2, r2, #24 8008a12: f1c2 0c20 rsb ip, r2, #32 8008a16: fa10 f30c lsls.w r3, r0, ip 8008a1a: fa20 f002 lsr.w r0, r0, r2 8008a1e: bf18 it ne 8008a20: f040 0001 orrne.w r0, r0, #1 8008a24: ea4f 23c1 mov.w r3, r1, lsl #11 8008a28: ea4f 23d3 mov.w r3, r3, lsr #11 8008a2c: fa03 fc0c lsl.w ip, r3, ip 8008a30: ea40 000c orr.w r0, r0, ip 8008a34: fa23 f302 lsr.w r3, r3, r2 8008a38: ea4f 0343 mov.w r3, r3, lsl #1 8008a3c: e7cc b.n 80089d8 <__aeabi_d2f+0x14> 8008a3e: ea7f 5362 mvns.w r3, r2, asr #21 8008a42: d107 bne.n 8008a54 <__aeabi_d2f+0x90> 8008a44: ea50 3301 orrs.w r3, r0, r1, lsl #12 8008a48: bf1e ittt ne 8008a4a: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000 8008a4e: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000 8008a52: 4770 bxne lr 8008a54: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000 8008a58: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008a5c: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008a60: 4770 bx lr 8008a62: bf00 nop 08008a64 <__aeabi_frsub>: 8008a64: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000 8008a68: e002 b.n 8008a70 <__addsf3> 8008a6a: bf00 nop 08008a6c <__aeabi_fsub>: 8008a6c: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 08008a70 <__addsf3>: 8008a70: 0042 lsls r2, r0, #1 8008a72: bf1f itttt ne 8008a74: ea5f 0341 movsne.w r3, r1, lsl #1 8008a78: ea92 0f03 teqne r2, r3 8008a7c: ea7f 6c22 mvnsne.w ip, r2, asr #24 8008a80: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008a84: d06a beq.n 8008b5c <__addsf3+0xec> 8008a86: ea4f 6212 mov.w r2, r2, lsr #24 8008a8a: ebd2 6313 rsbs r3, r2, r3, lsr #24 8008a8e: bfc1 itttt gt 8008a90: 18d2 addgt r2, r2, r3 8008a92: 4041 eorgt r1, r0 8008a94: 4048 eorgt r0, r1 8008a96: 4041 eorgt r1, r0 8008a98: bfb8 it lt 8008a9a: 425b neglt r3, r3 8008a9c: 2b19 cmp r3, #25 8008a9e: bf88 it hi 8008aa0: 4770 bxhi lr 8008aa2: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 8008aa6: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008aaa: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000 8008aae: bf18 it ne 8008ab0: 4240 negne r0, r0 8008ab2: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008ab6: f441 0100 orr.w r1, r1, #8388608 @ 0x800000 8008aba: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000 8008abe: bf18 it ne 8008ac0: 4249 negne r1, r1 8008ac2: ea92 0f03 teq r2, r3 8008ac6: d03f beq.n 8008b48 <__addsf3+0xd8> 8008ac8: f1a2 0201 sub.w r2, r2, #1 8008acc: fa41 fc03 asr.w ip, r1, r3 8008ad0: eb10 000c adds.w r0, r0, ip 8008ad4: f1c3 0320 rsb r3, r3, #32 8008ad8: fa01 f103 lsl.w r1, r1, r3 8008adc: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008ae0: d502 bpl.n 8008ae8 <__addsf3+0x78> 8008ae2: 4249 negs r1, r1 8008ae4: eb60 0040 sbc.w r0, r0, r0, lsl #1 8008ae8: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000 8008aec: d313 bcc.n 8008b16 <__addsf3+0xa6> 8008aee: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000 8008af2: d306 bcc.n 8008b02 <__addsf3+0x92> 8008af4: 0840 lsrs r0, r0, #1 8008af6: ea4f 0131 mov.w r1, r1, rrx 8008afa: f102 0201 add.w r2, r2, #1 8008afe: 2afe cmp r2, #254 @ 0xfe 8008b00: d251 bcs.n 8008ba6 <__addsf3+0x136> 8008b02: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000 8008b06: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008b0a: bf08 it eq 8008b0c: f020 0001 biceq.w r0, r0, #1 8008b10: ea40 0003 orr.w r0, r0, r3 8008b14: 4770 bx lr 8008b16: 0049 lsls r1, r1, #1 8008b18: eb40 0000 adc.w r0, r0, r0 8008b1c: 3a01 subs r2, #1 8008b1e: bf28 it cs 8008b20: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000 8008b24: d2ed bcs.n 8008b02 <__addsf3+0x92> 8008b26: fab0 fc80 clz ip, r0 8008b2a: f1ac 0c08 sub.w ip, ip, #8 8008b2e: ebb2 020c subs.w r2, r2, ip 8008b32: fa00 f00c lsl.w r0, r0, ip 8008b36: bfaa itet ge 8008b38: eb00 50c2 addge.w r0, r0, r2, lsl #23 8008b3c: 4252 neglt r2, r2 8008b3e: 4318 orrge r0, r3 8008b40: bfbc itt lt 8008b42: 40d0 lsrlt r0, r2 8008b44: 4318 orrlt r0, r3 8008b46: 4770 bx lr 8008b48: f092 0f00 teq r2, #0 8008b4c: f481 0100 eor.w r1, r1, #8388608 @ 0x800000 8008b50: bf06 itte eq 8008b52: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000 8008b56: 3201 addeq r2, #1 8008b58: 3b01 subne r3, #1 8008b5a: e7b5 b.n 8008ac8 <__addsf3+0x58> 8008b5c: ea4f 0341 mov.w r3, r1, lsl #1 8008b60: ea7f 6c22 mvns.w ip, r2, asr #24 8008b64: bf18 it ne 8008b66: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008b6a: d021 beq.n 8008bb0 <__addsf3+0x140> 8008b6c: ea92 0f03 teq r2, r3 8008b70: d004 beq.n 8008b7c <__addsf3+0x10c> 8008b72: f092 0f00 teq r2, #0 8008b76: bf08 it eq 8008b78: 4608 moveq r0, r1 8008b7a: 4770 bx lr 8008b7c: ea90 0f01 teq r0, r1 8008b80: bf1c itt ne 8008b82: 2000 movne r0, #0 8008b84: 4770 bxne lr 8008b86: f012 4f7f tst.w r2, #4278190080 @ 0xff000000 8008b8a: d104 bne.n 8008b96 <__addsf3+0x126> 8008b8c: 0040 lsls r0, r0, #1 8008b8e: bf28 it cs 8008b90: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000 8008b94: 4770 bx lr 8008b96: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000 8008b9a: bf3c itt cc 8008b9c: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000 8008ba0: 4770 bxcc lr 8008ba2: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008ba6: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000 8008baa: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008bae: 4770 bx lr 8008bb0: ea7f 6222 mvns.w r2, r2, asr #24 8008bb4: bf16 itet ne 8008bb6: 4608 movne r0, r1 8008bb8: ea7f 6323 mvnseq.w r3, r3, asr #24 8008bbc: 4601 movne r1, r0 8008bbe: 0242 lsls r2, r0, #9 8008bc0: bf06 itte eq 8008bc2: ea5f 2341 movseq.w r3, r1, lsl #9 8008bc6: ea90 0f01 teqeq r0, r1 8008bca: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000 8008bce: 4770 bx lr 08008bd0 <__aeabi_ui2f>: 8008bd0: f04f 0300 mov.w r3, #0 8008bd4: e004 b.n 8008be0 <__aeabi_i2f+0x8> 8008bd6: bf00 nop 08008bd8 <__aeabi_i2f>: 8008bd8: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000 8008bdc: bf48 it mi 8008bde: 4240 negmi r0, r0 8008be0: ea5f 0c00 movs.w ip, r0 8008be4: bf08 it eq 8008be6: 4770 bxeq lr 8008be8: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000 8008bec: 4601 mov r1, r0 8008bee: f04f 0000 mov.w r0, #0 8008bf2: e01c b.n 8008c2e <__aeabi_l2f+0x2a> 08008bf4 <__aeabi_ul2f>: 8008bf4: ea50 0201 orrs.w r2, r0, r1 8008bf8: bf08 it eq 8008bfa: 4770 bxeq lr 8008bfc: f04f 0300 mov.w r3, #0 8008c00: e00a b.n 8008c18 <__aeabi_l2f+0x14> 8008c02: bf00 nop 08008c04 <__aeabi_l2f>: 8008c04: ea50 0201 orrs.w r2, r0, r1 8008c08: bf08 it eq 8008c0a: 4770 bxeq lr 8008c0c: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000 8008c10: d502 bpl.n 8008c18 <__aeabi_l2f+0x14> 8008c12: 4240 negs r0, r0 8008c14: eb61 0141 sbc.w r1, r1, r1, lsl #1 8008c18: ea5f 0c01 movs.w ip, r1 8008c1c: bf02 ittt eq 8008c1e: 4684 moveq ip, r0 8008c20: 4601 moveq r1, r0 8008c22: 2000 moveq r0, #0 8008c24: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000 8008c28: bf08 it eq 8008c2a: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000 8008c2e: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 8008c32: fabc f28c clz r2, ip 8008c36: 3a08 subs r2, #8 8008c38: eba3 53c2 sub.w r3, r3, r2, lsl #23 8008c3c: db10 blt.n 8008c60 <__aeabi_l2f+0x5c> 8008c3e: fa01 fc02 lsl.w ip, r1, r2 8008c42: 4463 add r3, ip 8008c44: fa00 fc02 lsl.w ip, r0, r2 8008c48: f1c2 0220 rsb r2, r2, #32 8008c4c: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008c50: fa20 f202 lsr.w r2, r0, r2 8008c54: eb43 0002 adc.w r0, r3, r2 8008c58: bf08 it eq 8008c5a: f020 0001 biceq.w r0, r0, #1 8008c5e: 4770 bx lr 8008c60: f102 0220 add.w r2, r2, #32 8008c64: fa01 fc02 lsl.w ip, r1, r2 8008c68: f1c2 0220 rsb r2, r2, #32 8008c6c: ea50 004c orrs.w r0, r0, ip, lsl #1 8008c70: fa21 f202 lsr.w r2, r1, r2 8008c74: eb43 0002 adc.w r0, r3, r2 8008c78: bf08 it eq 8008c7a: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008c7e: 4770 bx lr 08008c80 <__aeabi_fmul>: 8008c80: f04f 0cff mov.w ip, #255 @ 0xff 8008c84: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008c88: bf1e ittt ne 8008c8a: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008c8e: ea92 0f0c teqne r2, ip 8008c92: ea93 0f0c teqne r3, ip 8008c96: d06f beq.n 8008d78 <__aeabi_fmul+0xf8> 8008c98: 441a add r2, r3 8008c9a: ea80 0c01 eor.w ip, r0, r1 8008c9e: 0240 lsls r0, r0, #9 8008ca0: bf18 it ne 8008ca2: ea5f 2141 movsne.w r1, r1, lsl #9 8008ca6: d01e beq.n 8008ce6 <__aeabi_fmul+0x66> 8008ca8: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8008cac: ea43 1050 orr.w r0, r3, r0, lsr #5 8008cb0: ea43 1151 orr.w r1, r3, r1, lsr #5 8008cb4: fba0 3101 umull r3, r1, r0, r1 8008cb8: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008cbc: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000 8008cc0: bf3e ittt cc 8008cc2: 0049 lslcc r1, r1, #1 8008cc4: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 8008cc8: 005b lslcc r3, r3, #1 8008cca: ea40 0001 orr.w r0, r0, r1 8008cce: f162 027f sbc.w r2, r2, #127 @ 0x7f 8008cd2: 2afd cmp r2, #253 @ 0xfd 8008cd4: d81d bhi.n 8008d12 <__aeabi_fmul+0x92> 8008cd6: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008cda: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008cde: bf08 it eq 8008ce0: f020 0001 biceq.w r0, r0, #1 8008ce4: 4770 bx lr 8008ce6: f090 0f00 teq r0, #0 8008cea: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8008cee: bf08 it eq 8008cf0: 0249 lsleq r1, r1, #9 8008cf2: ea4c 2050 orr.w r0, ip, r0, lsr #9 8008cf6: ea40 2051 orr.w r0, r0, r1, lsr #9 8008cfa: 3a7f subs r2, #127 @ 0x7f 8008cfc: bfc2 ittt gt 8008cfe: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 8008d02: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8008d06: 4770 bxgt lr 8008d08: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008d0c: f04f 0300 mov.w r3, #0 8008d10: 3a01 subs r2, #1 8008d12: dc5d bgt.n 8008dd0 <__aeabi_fmul+0x150> 8008d14: f112 0f19 cmn.w r2, #25 8008d18: bfdc itt le 8008d1a: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000 8008d1e: 4770 bxle lr 8008d20: f1c2 0200 rsb r2, r2, #0 8008d24: 0041 lsls r1, r0, #1 8008d26: fa21 f102 lsr.w r1, r1, r2 8008d2a: f1c2 0220 rsb r2, r2, #32 8008d2e: fa00 fc02 lsl.w ip, r0, r2 8008d32: ea5f 0031 movs.w r0, r1, rrx 8008d36: f140 0000 adc.w r0, r0, #0 8008d3a: ea53 034c orrs.w r3, r3, ip, lsl #1 8008d3e: bf08 it eq 8008d40: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008d44: 4770 bx lr 8008d46: f092 0f00 teq r2, #0 8008d4a: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8008d4e: bf02 ittt eq 8008d50: 0040 lsleq r0, r0, #1 8008d52: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 8008d56: 3a01 subeq r2, #1 8008d58: d0f9 beq.n 8008d4e <__aeabi_fmul+0xce> 8008d5a: ea40 000c orr.w r0, r0, ip 8008d5e: f093 0f00 teq r3, #0 8008d62: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008d66: bf02 ittt eq 8008d68: 0049 lsleq r1, r1, #1 8008d6a: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8008d6e: 3b01 subeq r3, #1 8008d70: d0f9 beq.n 8008d66 <__aeabi_fmul+0xe6> 8008d72: ea41 010c orr.w r1, r1, ip 8008d76: e78f b.n 8008c98 <__aeabi_fmul+0x18> 8008d78: ea0c 53d1 and.w r3, ip, r1, lsr #23 8008d7c: ea92 0f0c teq r2, ip 8008d80: bf18 it ne 8008d82: ea93 0f0c teqne r3, ip 8008d86: d00a beq.n 8008d9e <__aeabi_fmul+0x11e> 8008d88: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 8008d8c: bf18 it ne 8008d8e: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 8008d92: d1d8 bne.n 8008d46 <__aeabi_fmul+0xc6> 8008d94: ea80 0001 eor.w r0, r0, r1 8008d98: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008d9c: 4770 bx lr 8008d9e: f090 0f00 teq r0, #0 8008da2: bf17 itett ne 8008da4: f090 4f00 teqne r0, #2147483648 @ 0x80000000 8008da8: 4608 moveq r0, r1 8008daa: f091 0f00 teqne r1, #0 8008dae: f091 4f00 teqne r1, #2147483648 @ 0x80000000 8008db2: d014 beq.n 8008dde <__aeabi_fmul+0x15e> 8008db4: ea92 0f0c teq r2, ip 8008db8: d101 bne.n 8008dbe <__aeabi_fmul+0x13e> 8008dba: 0242 lsls r2, r0, #9 8008dbc: d10f bne.n 8008dde <__aeabi_fmul+0x15e> 8008dbe: ea93 0f0c teq r3, ip 8008dc2: d103 bne.n 8008dcc <__aeabi_fmul+0x14c> 8008dc4: 024b lsls r3, r1, #9 8008dc6: bf18 it ne 8008dc8: 4608 movne r0, r1 8008dca: d108 bne.n 8008dde <__aeabi_fmul+0x15e> 8008dcc: ea80 0001 eor.w r0, r0, r1 8008dd0: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008dd4: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008dd8: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008ddc: 4770 bx lr 8008dde: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008de2: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000 8008de6: 4770 bx lr 08008de8 <__aeabi_fdiv>: 8008de8: f04f 0cff mov.w ip, #255 @ 0xff 8008dec: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008df0: bf1e ittt ne 8008df2: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008df6: ea92 0f0c teqne r2, ip 8008dfa: ea93 0f0c teqne r3, ip 8008dfe: d069 beq.n 8008ed4 <__aeabi_fdiv+0xec> 8008e00: eba2 0203 sub.w r2, r2, r3 8008e04: ea80 0c01 eor.w ip, r0, r1 8008e08: 0249 lsls r1, r1, #9 8008e0a: ea4f 2040 mov.w r0, r0, lsl #9 8008e0e: d037 beq.n 8008e80 <__aeabi_fdiv+0x98> 8008e10: f04f 5380 mov.w r3, #268435456 @ 0x10000000 8008e14: ea43 1111 orr.w r1, r3, r1, lsr #4 8008e18: ea43 1310 orr.w r3, r3, r0, lsr #4 8008e1c: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008e20: 428b cmp r3, r1 8008e22: bf38 it cc 8008e24: 005b lslcc r3, r3, #1 8008e26: f142 027d adc.w r2, r2, #125 @ 0x7d 8008e2a: f44f 0c00 mov.w ip, #8388608 @ 0x800000 8008e2e: 428b cmp r3, r1 8008e30: bf24 itt cs 8008e32: 1a5b subcs r3, r3, r1 8008e34: ea40 000c orrcs.w r0, r0, ip 8008e38: ebb3 0f51 cmp.w r3, r1, lsr #1 8008e3c: bf24 itt cs 8008e3e: eba3 0351 subcs.w r3, r3, r1, lsr #1 8008e42: ea40 005c orrcs.w r0, r0, ip, lsr #1 8008e46: ebb3 0f91 cmp.w r3, r1, lsr #2 8008e4a: bf24 itt cs 8008e4c: eba3 0391 subcs.w r3, r3, r1, lsr #2 8008e50: ea40 009c orrcs.w r0, r0, ip, lsr #2 8008e54: ebb3 0fd1 cmp.w r3, r1, lsr #3 8008e58: bf24 itt cs 8008e5a: eba3 03d1 subcs.w r3, r3, r1, lsr #3 8008e5e: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8008e62: 011b lsls r3, r3, #4 8008e64: bf18 it ne 8008e66: ea5f 1c1c movsne.w ip, ip, lsr #4 8008e6a: d1e0 bne.n 8008e2e <__aeabi_fdiv+0x46> 8008e6c: 2afd cmp r2, #253 @ 0xfd 8008e6e: f63f af50 bhi.w 8008d12 <__aeabi_fmul+0x92> 8008e72: 428b cmp r3, r1 8008e74: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008e78: bf08 it eq 8008e7a: f020 0001 biceq.w r0, r0, #1 8008e7e: 4770 bx lr 8008e80: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8008e84: ea4c 2050 orr.w r0, ip, r0, lsr #9 8008e88: 327f adds r2, #127 @ 0x7f 8008e8a: bfc2 ittt gt 8008e8c: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 8008e90: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8008e94: 4770 bxgt lr 8008e96: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008e9a: f04f 0300 mov.w r3, #0 8008e9e: 3a01 subs r2, #1 8008ea0: e737 b.n 8008d12 <__aeabi_fmul+0x92> 8008ea2: f092 0f00 teq r2, #0 8008ea6: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8008eaa: bf02 ittt eq 8008eac: 0040 lsleq r0, r0, #1 8008eae: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 8008eb2: 3a01 subeq r2, #1 8008eb4: d0f9 beq.n 8008eaa <__aeabi_fdiv+0xc2> 8008eb6: ea40 000c orr.w r0, r0, ip 8008eba: f093 0f00 teq r3, #0 8008ebe: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008ec2: bf02 ittt eq 8008ec4: 0049 lsleq r1, r1, #1 8008ec6: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8008eca: 3b01 subeq r3, #1 8008ecc: d0f9 beq.n 8008ec2 <__aeabi_fdiv+0xda> 8008ece: ea41 010c orr.w r1, r1, ip 8008ed2: e795 b.n 8008e00 <__aeabi_fdiv+0x18> 8008ed4: ea0c 53d1 and.w r3, ip, r1, lsr #23 8008ed8: ea92 0f0c teq r2, ip 8008edc: d108 bne.n 8008ef0 <__aeabi_fdiv+0x108> 8008ede: 0242 lsls r2, r0, #9 8008ee0: f47f af7d bne.w 8008dde <__aeabi_fmul+0x15e> 8008ee4: ea93 0f0c teq r3, ip 8008ee8: f47f af70 bne.w 8008dcc <__aeabi_fmul+0x14c> 8008eec: 4608 mov r0, r1 8008eee: e776 b.n 8008dde <__aeabi_fmul+0x15e> 8008ef0: ea93 0f0c teq r3, ip 8008ef4: d104 bne.n 8008f00 <__aeabi_fdiv+0x118> 8008ef6: 024b lsls r3, r1, #9 8008ef8: f43f af4c beq.w 8008d94 <__aeabi_fmul+0x114> 8008efc: 4608 mov r0, r1 8008efe: e76e b.n 8008dde <__aeabi_fmul+0x15e> 8008f00: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 8008f04: bf18 it ne 8008f06: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 8008f0a: d1ca bne.n 8008ea2 <__aeabi_fdiv+0xba> 8008f0c: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000 8008f10: f47f af5c bne.w 8008dcc <__aeabi_fmul+0x14c> 8008f14: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000 8008f18: f47f af3c bne.w 8008d94 <__aeabi_fmul+0x114> 8008f1c: e75f b.n 8008dde <__aeabi_fmul+0x15e> 8008f1e: bf00 nop 08008f20 <__gesf2>: 8008f20: f04f 3cff mov.w ip, #4294967295 8008f24: e006 b.n 8008f34 <__cmpsf2+0x4> 8008f26: bf00 nop 08008f28 <__lesf2>: 8008f28: f04f 0c01 mov.w ip, #1 8008f2c: e002 b.n 8008f34 <__cmpsf2+0x4> 8008f2e: bf00 nop 08008f30 <__cmpsf2>: 8008f30: f04f 0c01 mov.w ip, #1 8008f34: f84d cd04 str.w ip, [sp, #-4]! 8008f38: ea4f 0240 mov.w r2, r0, lsl #1 8008f3c: ea4f 0341 mov.w r3, r1, lsl #1 8008f40: ea7f 6c22 mvns.w ip, r2, asr #24 8008f44: bf18 it ne 8008f46: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008f4a: d011 beq.n 8008f70 <__cmpsf2+0x40> 8008f4c: b001 add sp, #4 8008f4e: ea52 0c53 orrs.w ip, r2, r3, lsr #1 8008f52: bf18 it ne 8008f54: ea90 0f01 teqne r0, r1 8008f58: bf58 it pl 8008f5a: ebb2 0003 subspl.w r0, r2, r3 8008f5e: bf88 it hi 8008f60: 17c8 asrhi r0, r1, #31 8008f62: bf38 it cc 8008f64: ea6f 70e1 mvncc.w r0, r1, asr #31 8008f68: bf18 it ne 8008f6a: f040 0001 orrne.w r0, r0, #1 8008f6e: 4770 bx lr 8008f70: ea7f 6c22 mvns.w ip, r2, asr #24 8008f74: d102 bne.n 8008f7c <__cmpsf2+0x4c> 8008f76: ea5f 2c40 movs.w ip, r0, lsl #9 8008f7a: d105 bne.n 8008f88 <__cmpsf2+0x58> 8008f7c: ea7f 6c23 mvns.w ip, r3, asr #24 8008f80: d1e4 bne.n 8008f4c <__cmpsf2+0x1c> 8008f82: ea5f 2c41 movs.w ip, r1, lsl #9 8008f86: d0e1 beq.n 8008f4c <__cmpsf2+0x1c> 8008f88: f85d 0b04 ldr.w r0, [sp], #4 8008f8c: 4770 bx lr 8008f8e: bf00 nop 08008f90 <__aeabi_cfrcmple>: 8008f90: 4684 mov ip, r0 8008f92: 4608 mov r0, r1 8008f94: 4661 mov r1, ip 8008f96: e7ff b.n 8008f98 <__aeabi_cfcmpeq> 08008f98 <__aeabi_cfcmpeq>: 8008f98: b50f push {r0, r1, r2, r3, lr} 8008f9a: f7ff ffc9 bl 8008f30 <__cmpsf2> 8008f9e: 2800 cmp r0, #0 8008fa0: bf48 it mi 8008fa2: f110 0f00 cmnmi.w r0, #0 8008fa6: bd0f pop {r0, r1, r2, r3, pc} 08008fa8 <__aeabi_fcmpeq>: 8008fa8: f84d ed08 str.w lr, [sp, #-8]! 8008fac: f7ff fff4 bl 8008f98 <__aeabi_cfcmpeq> 8008fb0: bf0c ite eq 8008fb2: 2001 moveq r0, #1 8008fb4: 2000 movne r0, #0 8008fb6: f85d fb08 ldr.w pc, [sp], #8 8008fba: bf00 nop 08008fbc <__aeabi_fcmplt>: 8008fbc: f84d ed08 str.w lr, [sp, #-8]! 8008fc0: f7ff ffea bl 8008f98 <__aeabi_cfcmpeq> 8008fc4: bf34 ite cc 8008fc6: 2001 movcc r0, #1 8008fc8: 2000 movcs r0, #0 8008fca: f85d fb08 ldr.w pc, [sp], #8 8008fce: bf00 nop 08008fd0 <__aeabi_fcmple>: 8008fd0: f84d ed08 str.w lr, [sp, #-8]! 8008fd4: f7ff ffe0 bl 8008f98 <__aeabi_cfcmpeq> 8008fd8: bf94 ite ls 8008fda: 2001 movls r0, #1 8008fdc: 2000 movhi r0, #0 8008fde: f85d fb08 ldr.w pc, [sp], #8 8008fe2: bf00 nop 08008fe4 <__aeabi_fcmpge>: 8008fe4: f84d ed08 str.w lr, [sp, #-8]! 8008fe8: f7ff ffd2 bl 8008f90 <__aeabi_cfrcmple> 8008fec: bf94 ite ls 8008fee: 2001 movls r0, #1 8008ff0: 2000 movhi r0, #0 8008ff2: f85d fb08 ldr.w pc, [sp], #8 8008ff6: bf00 nop 08008ff8 <__aeabi_fcmpgt>: 8008ff8: f84d ed08 str.w lr, [sp, #-8]! 8008ffc: f7ff ffc8 bl 8008f90 <__aeabi_cfrcmple> 8009000: bf34 ite cc 8009002: 2001 movcc r0, #1 8009004: 2000 movcs r0, #0 8009006: f85d fb08 ldr.w pc, [sp], #8 800900a: bf00 nop 0800900c <__aeabi_f2iz>: 800900c: ea4f 0240 mov.w r2, r0, lsl #1 8009010: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000 8009014: d30f bcc.n 8009036 <__aeabi_f2iz+0x2a> 8009016: f04f 039e mov.w r3, #158 @ 0x9e 800901a: ebb3 6212 subs.w r2, r3, r2, lsr #24 800901e: d90d bls.n 800903c <__aeabi_f2iz+0x30> 8009020: ea4f 2300 mov.w r3, r0, lsl #8 8009024: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8009028: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 800902c: fa23 f002 lsr.w r0, r3, r2 8009030: bf18 it ne 8009032: 4240 negne r0, r0 8009034: 4770 bx lr 8009036: f04f 0000 mov.w r0, #0 800903a: 4770 bx lr 800903c: f112 0f61 cmn.w r2, #97 @ 0x61 8009040: d101 bne.n 8009046 <__aeabi_f2iz+0x3a> 8009042: 0242 lsls r2, r0, #9 8009044: d105 bne.n 8009052 <__aeabi_f2iz+0x46> 8009046: f010 4000 ands.w r0, r0, #2147483648 @ 0x80000000 800904a: bf08 it eq 800904c: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 8009050: 4770 bx lr 8009052: f04f 0000 mov.w r0, #0 8009056: 4770 bx lr 08009058 <__aeabi_uldivmod>: 8009058: b953 cbnz r3, 8009070 <__aeabi_uldivmod+0x18> 800905a: b94a cbnz r2, 8009070 <__aeabi_uldivmod+0x18> 800905c: 2900 cmp r1, #0 800905e: bf08 it eq 8009060: 2800 cmpeq r0, #0 8009062: bf1c itt ne 8009064: f04f 31ff movne.w r1, #4294967295 8009068: f04f 30ff movne.w r0, #4294967295 800906c: f000 b98c b.w 8009388 <__aeabi_idiv0> 8009070: f1ad 0c08 sub.w ip, sp, #8 8009074: e96d ce04 strd ip, lr, [sp, #-16]! 8009078: f000 f806 bl 8009088 <__udivmoddi4> 800907c: f8dd e004 ldr.w lr, [sp, #4] 8009080: e9dd 2302 ldrd r2, r3, [sp, #8] 8009084: b004 add sp, #16 8009086: 4770 bx lr 08009088 <__udivmoddi4>: 8009088: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800908c: 9d08 ldr r5, [sp, #32] 800908e: 468e mov lr, r1 8009090: 4604 mov r4, r0 8009092: 4688 mov r8, r1 8009094: 2b00 cmp r3, #0 8009096: d14a bne.n 800912e <__udivmoddi4+0xa6> 8009098: 428a cmp r2, r1 800909a: 4617 mov r7, r2 800909c: d962 bls.n 8009164 <__udivmoddi4+0xdc> 800909e: fab2 f682 clz r6, r2 80090a2: b14e cbz r6, 80090b8 <__udivmoddi4+0x30> 80090a4: f1c6 0320 rsb r3, r6, #32 80090a8: fa01 f806 lsl.w r8, r1, r6 80090ac: fa20 f303 lsr.w r3, r0, r3 80090b0: 40b7 lsls r7, r6 80090b2: ea43 0808 orr.w r8, r3, r8 80090b6: 40b4 lsls r4, r6 80090b8: ea4f 4e17 mov.w lr, r7, lsr #16 80090bc: fbb8 f1fe udiv r1, r8, lr 80090c0: fa1f fc87 uxth.w ip, r7 80090c4: fb0e 8811 mls r8, lr, r1, r8 80090c8: fb01 f20c mul.w r2, r1, ip 80090cc: 0c23 lsrs r3, r4, #16 80090ce: ea43 4308 orr.w r3, r3, r8, lsl #16 80090d2: 429a cmp r2, r3 80090d4: d909 bls.n 80090ea <__udivmoddi4+0x62> 80090d6: 18fb adds r3, r7, r3 80090d8: f101 30ff add.w r0, r1, #4294967295 80090dc: f080 80eb bcs.w 80092b6 <__udivmoddi4+0x22e> 80090e0: 429a cmp r2, r3 80090e2: f240 80e8 bls.w 80092b6 <__udivmoddi4+0x22e> 80090e6: 3902 subs r1, #2 80090e8: 443b add r3, r7 80090ea: 1a9a subs r2, r3, r2 80090ec: fbb2 f0fe udiv r0, r2, lr 80090f0: fb0e 2210 mls r2, lr, r0, r2 80090f4: fb00 fc0c mul.w ip, r0, ip 80090f8: b2a3 uxth r3, r4 80090fa: ea43 4302 orr.w r3, r3, r2, lsl #16 80090fe: 459c cmp ip, r3 8009100: d909 bls.n 8009116 <__udivmoddi4+0x8e> 8009102: 18fb adds r3, r7, r3 8009104: f100 32ff add.w r2, r0, #4294967295 8009108: f080 80d7 bcs.w 80092ba <__udivmoddi4+0x232> 800910c: 459c cmp ip, r3 800910e: f240 80d4 bls.w 80092ba <__udivmoddi4+0x232> 8009112: 443b add r3, r7 8009114: 3802 subs r0, #2 8009116: ea40 4001 orr.w r0, r0, r1, lsl #16 800911a: 2100 movs r1, #0 800911c: eba3 030c sub.w r3, r3, ip 8009120: b11d cbz r5, 800912a <__udivmoddi4+0xa2> 8009122: 2200 movs r2, #0 8009124: 40f3 lsrs r3, r6 8009126: e9c5 3200 strd r3, r2, [r5] 800912a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800912e: 428b cmp r3, r1 8009130: d905 bls.n 800913e <__udivmoddi4+0xb6> 8009132: b10d cbz r5, 8009138 <__udivmoddi4+0xb0> 8009134: e9c5 0100 strd r0, r1, [r5] 8009138: 2100 movs r1, #0 800913a: 4608 mov r0, r1 800913c: e7f5 b.n 800912a <__udivmoddi4+0xa2> 800913e: fab3 f183 clz r1, r3 8009142: 2900 cmp r1, #0 8009144: d146 bne.n 80091d4 <__udivmoddi4+0x14c> 8009146: 4573 cmp r3, lr 8009148: d302 bcc.n 8009150 <__udivmoddi4+0xc8> 800914a: 4282 cmp r2, r0 800914c: f200 8108 bhi.w 8009360 <__udivmoddi4+0x2d8> 8009150: 1a84 subs r4, r0, r2 8009152: eb6e 0203 sbc.w r2, lr, r3 8009156: 2001 movs r0, #1 8009158: 4690 mov r8, r2 800915a: 2d00 cmp r5, #0 800915c: d0e5 beq.n 800912a <__udivmoddi4+0xa2> 800915e: e9c5 4800 strd r4, r8, [r5] 8009162: e7e2 b.n 800912a <__udivmoddi4+0xa2> 8009164: 2a00 cmp r2, #0 8009166: f000 8091 beq.w 800928c <__udivmoddi4+0x204> 800916a: fab2 f682 clz r6, r2 800916e: 2e00 cmp r6, #0 8009170: f040 80a5 bne.w 80092be <__udivmoddi4+0x236> 8009174: 1a8a subs r2, r1, r2 8009176: 2101 movs r1, #1 8009178: 0c03 lsrs r3, r0, #16 800917a: ea4f 4e17 mov.w lr, r7, lsr #16 800917e: b280 uxth r0, r0 8009180: b2bc uxth r4, r7 8009182: fbb2 fcfe udiv ip, r2, lr 8009186: fb0e 221c mls r2, lr, ip, r2 800918a: ea43 4302 orr.w r3, r3, r2, lsl #16 800918e: fb04 f20c mul.w r2, r4, ip 8009192: 429a cmp r2, r3 8009194: d907 bls.n 80091a6 <__udivmoddi4+0x11e> 8009196: 18fb adds r3, r7, r3 8009198: f10c 38ff add.w r8, ip, #4294967295 800919c: d202 bcs.n 80091a4 <__udivmoddi4+0x11c> 800919e: 429a cmp r2, r3 80091a0: f200 80e3 bhi.w 800936a <__udivmoddi4+0x2e2> 80091a4: 46c4 mov ip, r8 80091a6: 1a9b subs r3, r3, r2 80091a8: fbb3 f2fe udiv r2, r3, lr 80091ac: fb0e 3312 mls r3, lr, r2, r3 80091b0: fb02 f404 mul.w r4, r2, r4 80091b4: ea40 4303 orr.w r3, r0, r3, lsl #16 80091b8: 429c cmp r4, r3 80091ba: d907 bls.n 80091cc <__udivmoddi4+0x144> 80091bc: 18fb adds r3, r7, r3 80091be: f102 30ff add.w r0, r2, #4294967295 80091c2: d202 bcs.n 80091ca <__udivmoddi4+0x142> 80091c4: 429c cmp r4, r3 80091c6: f200 80cd bhi.w 8009364 <__udivmoddi4+0x2dc> 80091ca: 4602 mov r2, r0 80091cc: 1b1b subs r3, r3, r4 80091ce: ea42 400c orr.w r0, r2, ip, lsl #16 80091d2: e7a5 b.n 8009120 <__udivmoddi4+0x98> 80091d4: f1c1 0620 rsb r6, r1, #32 80091d8: 408b lsls r3, r1 80091da: fa22 f706 lsr.w r7, r2, r6 80091de: 431f orrs r7, r3 80091e0: fa2e fa06 lsr.w sl, lr, r6 80091e4: ea4f 4917 mov.w r9, r7, lsr #16 80091e8: fbba f8f9 udiv r8, sl, r9 80091ec: fa0e fe01 lsl.w lr, lr, r1 80091f0: fa20 f306 lsr.w r3, r0, r6 80091f4: fb09 aa18 mls sl, r9, r8, sl 80091f8: fa1f fc87 uxth.w ip, r7 80091fc: ea43 030e orr.w r3, r3, lr 8009200: fa00 fe01 lsl.w lr, r0, r1 8009204: fb08 f00c mul.w r0, r8, ip 8009208: 0c1c lsrs r4, r3, #16 800920a: ea44 440a orr.w r4, r4, sl, lsl #16 800920e: 42a0 cmp r0, r4 8009210: fa02 f201 lsl.w r2, r2, r1 8009214: d90a bls.n 800922c <__udivmoddi4+0x1a4> 8009216: 193c adds r4, r7, r4 8009218: f108 3aff add.w sl, r8, #4294967295 800921c: f080 809e bcs.w 800935c <__udivmoddi4+0x2d4> 8009220: 42a0 cmp r0, r4 8009222: f240 809b bls.w 800935c <__udivmoddi4+0x2d4> 8009226: f1a8 0802 sub.w r8, r8, #2 800922a: 443c add r4, r7 800922c: 1a24 subs r4, r4, r0 800922e: b298 uxth r0, r3 8009230: fbb4 f3f9 udiv r3, r4, r9 8009234: fb09 4413 mls r4, r9, r3, r4 8009238: fb03 fc0c mul.w ip, r3, ip 800923c: ea40 4404 orr.w r4, r0, r4, lsl #16 8009240: 45a4 cmp ip, r4 8009242: d909 bls.n 8009258 <__udivmoddi4+0x1d0> 8009244: 193c adds r4, r7, r4 8009246: f103 30ff add.w r0, r3, #4294967295 800924a: f080 8085 bcs.w 8009358 <__udivmoddi4+0x2d0> 800924e: 45a4 cmp ip, r4 8009250: f240 8082 bls.w 8009358 <__udivmoddi4+0x2d0> 8009254: 3b02 subs r3, #2 8009256: 443c add r4, r7 8009258: ea43 4008 orr.w r0, r3, r8, lsl #16 800925c: eba4 040c sub.w r4, r4, ip 8009260: fba0 8c02 umull r8, ip, r0, r2 8009264: 4564 cmp r4, ip 8009266: 4643 mov r3, r8 8009268: 46e1 mov r9, ip 800926a: d364 bcc.n 8009336 <__udivmoddi4+0x2ae> 800926c: d061 beq.n 8009332 <__udivmoddi4+0x2aa> 800926e: b15d cbz r5, 8009288 <__udivmoddi4+0x200> 8009270: ebbe 0203 subs.w r2, lr, r3 8009274: eb64 0409 sbc.w r4, r4, r9 8009278: fa04 f606 lsl.w r6, r4, r6 800927c: fa22 f301 lsr.w r3, r2, r1 8009280: 431e orrs r6, r3 8009282: 40cc lsrs r4, r1 8009284: e9c5 6400 strd r6, r4, [r5] 8009288: 2100 movs r1, #0 800928a: e74e b.n 800912a <__udivmoddi4+0xa2> 800928c: fbb1 fcf2 udiv ip, r1, r2 8009290: 0c01 lsrs r1, r0, #16 8009292: ea41 410e orr.w r1, r1, lr, lsl #16 8009296: b280 uxth r0, r0 8009298: ea40 4201 orr.w r2, r0, r1, lsl #16 800929c: 463b mov r3, r7 800929e: fbb1 f1f7 udiv r1, r1, r7 80092a2: 4638 mov r0, r7 80092a4: 463c mov r4, r7 80092a6: 46b8 mov r8, r7 80092a8: 46be mov lr, r7 80092aa: 2620 movs r6, #32 80092ac: eba2 0208 sub.w r2, r2, r8 80092b0: ea41 410c orr.w r1, r1, ip, lsl #16 80092b4: e765 b.n 8009182 <__udivmoddi4+0xfa> 80092b6: 4601 mov r1, r0 80092b8: e717 b.n 80090ea <__udivmoddi4+0x62> 80092ba: 4610 mov r0, r2 80092bc: e72b b.n 8009116 <__udivmoddi4+0x8e> 80092be: f1c6 0120 rsb r1, r6, #32 80092c2: fa2e fc01 lsr.w ip, lr, r1 80092c6: 40b7 lsls r7, r6 80092c8: fa0e fe06 lsl.w lr, lr, r6 80092cc: fa20 f101 lsr.w r1, r0, r1 80092d0: ea41 010e orr.w r1, r1, lr 80092d4: ea4f 4e17 mov.w lr, r7, lsr #16 80092d8: fbbc f8fe udiv r8, ip, lr 80092dc: b2bc uxth r4, r7 80092de: fb0e cc18 mls ip, lr, r8, ip 80092e2: fb08 f904 mul.w r9, r8, r4 80092e6: 0c0a lsrs r2, r1, #16 80092e8: ea42 420c orr.w r2, r2, ip, lsl #16 80092ec: 40b0 lsls r0, r6 80092ee: 4591 cmp r9, r2 80092f0: ea4f 4310 mov.w r3, r0, lsr #16 80092f4: b280 uxth r0, r0 80092f6: d93e bls.n 8009376 <__udivmoddi4+0x2ee> 80092f8: 18ba adds r2, r7, r2 80092fa: f108 3cff add.w ip, r8, #4294967295 80092fe: d201 bcs.n 8009304 <__udivmoddi4+0x27c> 8009300: 4591 cmp r9, r2 8009302: d81f bhi.n 8009344 <__udivmoddi4+0x2bc> 8009304: eba2 0209 sub.w r2, r2, r9 8009308: fbb2 f9fe udiv r9, r2, lr 800930c: fb09 f804 mul.w r8, r9, r4 8009310: fb0e 2a19 mls sl, lr, r9, r2 8009314: b28a uxth r2, r1 8009316: ea42 420a orr.w r2, r2, sl, lsl #16 800931a: 4542 cmp r2, r8 800931c: d229 bcs.n 8009372 <__udivmoddi4+0x2ea> 800931e: 18ba adds r2, r7, r2 8009320: f109 31ff add.w r1, r9, #4294967295 8009324: d2c2 bcs.n 80092ac <__udivmoddi4+0x224> 8009326: 4542 cmp r2, r8 8009328: d2c0 bcs.n 80092ac <__udivmoddi4+0x224> 800932a: f1a9 0102 sub.w r1, r9, #2 800932e: 443a add r2, r7 8009330: e7bc b.n 80092ac <__udivmoddi4+0x224> 8009332: 45c6 cmp lr, r8 8009334: d29b bcs.n 800926e <__udivmoddi4+0x1e6> 8009336: ebb8 0302 subs.w r3, r8, r2 800933a: eb6c 0c07 sbc.w ip, ip, r7 800933e: 3801 subs r0, #1 8009340: 46e1 mov r9, ip 8009342: e794 b.n 800926e <__udivmoddi4+0x1e6> 8009344: eba7 0909 sub.w r9, r7, r9 8009348: 444a add r2, r9 800934a: fbb2 f9fe udiv r9, r2, lr 800934e: f1a8 0c02 sub.w ip, r8, #2 8009352: fb09 f804 mul.w r8, r9, r4 8009356: e7db b.n 8009310 <__udivmoddi4+0x288> 8009358: 4603 mov r3, r0 800935a: e77d b.n 8009258 <__udivmoddi4+0x1d0> 800935c: 46d0 mov r8, sl 800935e: e765 b.n 800922c <__udivmoddi4+0x1a4> 8009360: 4608 mov r0, r1 8009362: e6fa b.n 800915a <__udivmoddi4+0xd2> 8009364: 443b add r3, r7 8009366: 3a02 subs r2, #2 8009368: e730 b.n 80091cc <__udivmoddi4+0x144> 800936a: f1ac 0c02 sub.w ip, ip, #2 800936e: 443b add r3, r7 8009370: e719 b.n 80091a6 <__udivmoddi4+0x11e> 8009372: 4649 mov r1, r9 8009374: e79a b.n 80092ac <__udivmoddi4+0x224> 8009376: eba2 0209 sub.w r2, r2, r9 800937a: fbb2 f9fe udiv r9, r2, lr 800937e: 46c4 mov ip, r8 8009380: fb09 f804 mul.w r8, r9, r4 8009384: e7c4 b.n 8009310 <__udivmoddi4+0x288> 8009386: bf00 nop 08009388 <__aeabi_idiv0>: 8009388: 4770 bx lr 800938a: bf00 nop 0800938c : ADC_HandleTypeDef hadc1; /* ADC1 init function */ void MX_ADC1_Init(void) { 800938c: b580 push {r7, lr} 800938e: b084 sub sp, #16 8009390: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8009392: 1d3b adds r3, r7, #4 8009394: 2200 movs r2, #0 8009396: 601a str r2, [r3, #0] 8009398: 605a str r2, [r3, #4] 800939a: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 800939c: 4b18 ldr r3, [pc, #96] @ (8009400 ) 800939e: 4a19 ldr r2, [pc, #100] @ (8009404 ) 80093a0: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 80093a2: 4b17 ldr r3, [pc, #92] @ (8009400 ) 80093a4: 2200 movs r2, #0 80093a6: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = DISABLE; 80093a8: 4b15 ldr r3, [pc, #84] @ (8009400 ) 80093aa: 2200 movs r2, #0 80093ac: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 80093ae: 4b14 ldr r3, [pc, #80] @ (8009400 ) 80093b0: 2200 movs r2, #0 80093b2: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 80093b4: 4b12 ldr r3, [pc, #72] @ (8009400 ) 80093b6: f44f 2260 mov.w r2, #917504 @ 0xe0000 80093ba: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80093bc: 4b10 ldr r3, [pc, #64] @ (8009400 ) 80093be: 2200 movs r2, #0 80093c0: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 1; 80093c2: 4b0f ldr r3, [pc, #60] @ (8009400 ) 80093c4: 2201 movs r2, #1 80093c6: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 80093c8: 480d ldr r0, [pc, #52] @ (8009400 ) 80093ca: f004 fab1 bl 800d930 80093ce: 4603 mov r3, r0 80093d0: 2b00 cmp r3, #0 80093d2: d001 beq.n 80093d8 { Error_Handler(); 80093d4: f001 fb0c bl 800a9f0 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 80093d8: 2308 movs r3, #8 80093da: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 80093dc: 2301 movs r3, #1 80093de: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 80093e0: 2300 movs r3, #0 80093e2: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80093e4: 1d3b adds r3, r7, #4 80093e6: 4619 mov r1, r3 80093e8: 4805 ldr r0, [pc, #20] @ (8009400 ) 80093ea: f004 fd65 bl 800deb8 80093ee: 4603 mov r3, r0 80093f0: 2b00 cmp r3, #0 80093f2: d001 beq.n 80093f8 { Error_Handler(); 80093f4: f001 fafc bl 800a9f0 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 80093f8: bf00 nop 80093fa: 3710 adds r7, #16 80093fc: 46bd mov sp, r7 80093fe: bd80 pop {r7, pc} 8009400: 200000f4 .word 0x200000f4 8009404: 40012400 .word 0x40012400 08009408 : void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 8009408: b580 push {r7, lr} 800940a: b08a sub sp, #40 @ 0x28 800940c: af00 add r7, sp, #0 800940e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8009410: f107 0318 add.w r3, r7, #24 8009414: 2200 movs r2, #0 8009416: 601a str r2, [r3, #0] 8009418: 605a str r2, [r3, #4] 800941a: 609a str r2, [r3, #8] 800941c: 60da str r2, [r3, #12] if(adcHandle->Instance==ADC1) 800941e: 687b ldr r3, [r7, #4] 8009420: 681b ldr r3, [r3, #0] 8009422: 4a1f ldr r2, [pc, #124] @ (80094a0 ) 8009424: 4293 cmp r3, r2 8009426: d137 bne.n 8009498 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 8009428: 4b1e ldr r3, [pc, #120] @ (80094a4 ) 800942a: 699b ldr r3, [r3, #24] 800942c: 4a1d ldr r2, [pc, #116] @ (80094a4 ) 800942e: f443 7300 orr.w r3, r3, #512 @ 0x200 8009432: 6193 str r3, [r2, #24] 8009434: 4b1b ldr r3, [pc, #108] @ (80094a4 ) 8009436: 699b ldr r3, [r3, #24] 8009438: f403 7300 and.w r3, r3, #512 @ 0x200 800943c: 617b str r3, [r7, #20] 800943e: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8009440: 4b18 ldr r3, [pc, #96] @ (80094a4 ) 8009442: 699b ldr r3, [r3, #24] 8009444: 4a17 ldr r2, [pc, #92] @ (80094a4 ) 8009446: f043 0304 orr.w r3, r3, #4 800944a: 6193 str r3, [r2, #24] 800944c: 4b15 ldr r3, [pc, #84] @ (80094a4 ) 800944e: 699b ldr r3, [r3, #24] 8009450: f003 0304 and.w r3, r3, #4 8009454: 613b str r3, [r7, #16] 8009456: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8009458: 4b12 ldr r3, [pc, #72] @ (80094a4 ) 800945a: 699b ldr r3, [r3, #24] 800945c: 4a11 ldr r2, [pc, #68] @ (80094a4 ) 800945e: f043 0308 orr.w r3, r3, #8 8009462: 6193 str r3, [r2, #24] 8009464: 4b0f ldr r3, [pc, #60] @ (80094a4 ) 8009466: 699b ldr r3, [r3, #24] 8009468: f003 0308 and.w r3, r3, #8 800946c: 60fb str r3, [r7, #12] 800946e: 68fb ldr r3, [r7, #12] PA3 ------> ADC1_IN3 PA4 ------> ADC1_IN4 PB0 ------> ADC1_IN8 PB1 ------> ADC1_IN9 */ GPIO_InitStruct.Pin = GPIO_PIN_3|CP_ADC_Pin; 8009470: 2318 movs r3, #24 8009472: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009474: 2303 movs r3, #3 8009476: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8009478: f107 0318 add.w r3, r7, #24 800947c: 4619 mov r1, r3 800947e: 480a ldr r0, [pc, #40] @ (80094a8 ) 8009480: f006 f89e bl 800f5c0 GPIO_InitStruct.Pin = ADC_NTC1_Pin|ADC_NTC2_Pin; 8009484: 2303 movs r3, #3 8009486: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009488: 2303 movs r3, #3 800948a: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800948c: f107 0318 add.w r3, r7, #24 8009490: 4619 mov r1, r3 8009492: 4806 ldr r0, [pc, #24] @ (80094ac ) 8009494: f006 f894 bl 800f5c0 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8009498: bf00 nop 800949a: 3728 adds r7, #40 @ 0x28 800949c: 46bd mov sp, r7 800949e: bd80 pop {r7, pc} 80094a0: 40012400 .word 0x40012400 80094a4: 40021000 .word 0x40021000 80094a8: 40010800 .word 0x40010800 80094ac: 40010c00 .word 0x40010c00 080094b0 : uint8_t RELAY_State[RELAY_COUNT]; static volatile uint8_t adc_lock = 0; static SMAFilter_t conn_temp_adc_filter[2]; void RELAY_Write(relay_t num, uint8_t state){ 80094b0: b580 push {r7, lr} 80094b2: b082 sub sp, #8 80094b4: af00 add r7, sp, #0 80094b6: 4603 mov r3, r0 80094b8: 460a mov r2, r1 80094ba: 71fb strb r3, [r7, #7] 80094bc: 4613 mov r3, r2 80094be: 71bb strb r3, [r7, #6] switch (num) { 80094c0: 79fb ldrb r3, [r7, #7] 80094c2: 2b07 cmp r3, #7 80094c4: d850 bhi.n 8009568 80094c6: a201 add r2, pc, #4 @ (adr r2, 80094cc ) 80094c8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80094cc: 080094ed .word 0x080094ed 80094d0: 080094fd .word 0x080094fd 80094d4: 0800950d .word 0x0800950d 80094d8: 0800951d .word 0x0800951d 80094dc: 0800952d .word 0x0800952d 80094e0: 0800953d .word 0x0800953d 80094e4: 0800954b .word 0x0800954b 80094e8: 0800955b .word 0x0800955b case RELAY_AUX0: HAL_GPIO_WritePin(RELAY1_GPIO_Port, RELAY1_Pin, state); 80094ec: 79bb ldrb r3, [r7, #6] 80094ee: 461a mov r2, r3 80094f0: f44f 7180 mov.w r1, #256 @ 0x100 80094f4: 4821 ldr r0, [pc, #132] @ (800957c ) 80094f6: f006 f9fe bl 800f8f6 break; 80094fa: e036 b.n 800956a case RELAY_AUX1: HAL_GPIO_WritePin(RELAY2_GPIO_Port, RELAY2_Pin, state); 80094fc: 79bb ldrb r3, [r7, #6] 80094fe: 461a mov r2, r3 8009500: f44f 7100 mov.w r1, #512 @ 0x200 8009504: 481d ldr r0, [pc, #116] @ (800957c ) 8009506: f006 f9f6 bl 800f8f6 break; 800950a: e02e b.n 800956a case RELAY3: HAL_GPIO_WritePin(RELAY3_GPIO_Port, RELAY3_Pin, state); 800950c: 79bb ldrb r3, [r7, #6] 800950e: 461a mov r2, r3 8009510: f44f 6180 mov.w r1, #1024 @ 0x400 8009514: 4819 ldr r0, [pc, #100] @ (800957c ) 8009516: f006 f9ee bl 800f8f6 break; 800951a: e026 b.n 800956a case RELAY_DC: HAL_GPIO_WritePin(RELAY4_GPIO_Port, RELAY4_Pin, state); 800951c: 79bb ldrb r3, [r7, #6] 800951e: 461a mov r2, r3 8009520: f44f 6100 mov.w r1, #2048 @ 0x800 8009524: 4815 ldr r0, [pc, #84] @ (800957c ) 8009526: f006 f9e6 bl 800f8f6 break; 800952a: e01e b.n 800956a case RELAY_AC: HAL_GPIO_WritePin(RELAY5_GPIO_Port, RELAY5_Pin, state); 800952c: 79bb ldrb r3, [r7, #6] 800952e: 461a mov r2, r3 8009530: f44f 5180 mov.w r1, #4096 @ 0x1000 8009534: 4811 ldr r0, [pc, #68] @ (800957c ) 8009536: f006 f9de bl 800f8f6 break; 800953a: e016 b.n 800956a case RELAY_CP: HAL_GPIO_WritePin(RELAY_CP_GPIO_Port, RELAY_CP_Pin, state); 800953c: 79bb ldrb r3, [r7, #6] 800953e: 461a mov r2, r3 8009540: 2108 movs r1, #8 8009542: 480f ldr r0, [pc, #60] @ (8009580 ) 8009544: f006 f9d7 bl 800f8f6 break; 8009548: e00f b.n 800956a case RELAY_CC: HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, state); 800954a: 79bb ldrb r3, [r7, #6] 800954c: 461a mov r2, r3 800954e: f44f 4100 mov.w r1, #32768 @ 0x8000 8009552: 480c ldr r0, [pc, #48] @ (8009584 ) 8009554: f006 f9cf bl 800f8f6 break; 8009558: e007 b.n 800956a case RELAY_DC1: HAL_GPIO_WritePin(RELAY_DC_GPIO_Port, RELAY_DC_Pin, state); 800955a: 79bb ldrb r3, [r7, #6] 800955c: 461a mov r2, r3 800955e: 2108 movs r1, #8 8009560: 4809 ldr r0, [pc, #36] @ (8009588 ) 8009562: f006 f9c8 bl 800f8f6 break; 8009566: e000 b.n 800956a default: break; 8009568: bf00 nop } RELAY_State[num] = state; 800956a: 79fb ldrb r3, [r7, #7] 800956c: 4907 ldr r1, [pc, #28] @ (800958c ) 800956e: 79ba ldrb r2, [r7, #6] 8009570: 54ca strb r2, [r1, r3] } 8009572: bf00 nop 8009574: 3708 adds r7, #8 8009576: 46bd mov sp, r7 8009578: bd80 pop {r7, pc} 800957a: bf00 nop 800957c: 40011800 .word 0x40011800 8009580: 40011000 .word 0x40011000 8009584: 40010800 .word 0x40010800 8009588: 40011400 .word 0x40011400 800958c: 20000124 .word 0x20000124 08009590 : uint8_t RELAY_Read(relay_t num){ 8009590: b480 push {r7} 8009592: b083 sub sp, #12 8009594: af00 add r7, sp, #0 8009596: 4603 mov r3, r0 8009598: 71fb strb r3, [r7, #7] return RELAY_State[num]; 800959a: 79fb ldrb r3, [r7, #7] 800959c: 4a03 ldr r2, [pc, #12] @ (80095ac ) 800959e: 5cd3 ldrb r3, [r2, r3] } 80095a0: 4618 mov r0, r3 80095a2: 370c adds r7, #12 80095a4: 46bd mov sp, r7 80095a6: bc80 pop {r7} 80095a8: 4770 bx lr 80095aa: bf00 nop 80095ac: 20000124 .word 0x20000124 080095b0 : uint8_t IN_ReadInput(inputNum_t input_n){ 80095b0: b580 push {r7, lr} 80095b2: b082 sub sp, #8 80095b4: af00 add r7, sp, #0 80095b6: 4603 mov r3, r0 80095b8: 71fb strb r3, [r7, #7] switch(input_n){ 80095ba: 79fb ldrb r3, [r7, #7] 80095bc: 2b06 cmp r3, #6 80095be: d83b bhi.n 8009638 80095c0: a201 add r2, pc, #4 @ (adr r2, 80095c8 ) 80095c2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80095c6: bf00 nop 80095c8: 080095e5 .word 0x080095e5 80095cc: 080095f1 .word 0x080095f1 80095d0: 080095fd .word 0x080095fd 80095d4: 08009609 .word 0x08009609 80095d8: 08009615 .word 0x08009615 80095dc: 08009621 .word 0x08009621 80095e0: 0800962d .word 0x0800962d case IN_SW0: return HAL_GPIO_ReadPin(IN_SW0_GPIO_Port, IN_SW0_Pin); 80095e4: 2102 movs r1, #2 80095e6: 4817 ldr r0, [pc, #92] @ (8009644 ) 80095e8: f006 f96e bl 800f8c8 80095ec: 4603 mov r3, r0 80095ee: e024 b.n 800963a case IN_SW1: return HAL_GPIO_ReadPin(IN_SW1_GPIO_Port, IN_SW1_Pin); 80095f0: 2104 movs r1, #4 80095f2: 4814 ldr r0, [pc, #80] @ (8009644 ) 80095f4: f006 f968 bl 800f8c8 80095f8: 4603 mov r3, r0 80095fa: e01e b.n 800963a case IN0: return HAL_GPIO_ReadPin(IN0_GPIO_Port, IN0_Pin); 80095fc: 2180 movs r1, #128 @ 0x80 80095fe: 4812 ldr r0, [pc, #72] @ (8009648 ) 8009600: f006 f962 bl 800f8c8 8009604: 4603 mov r3, r0 8009606: e018 b.n 800963a case IN_ESTOP: return HAL_GPIO_ReadPin(IN_ESTOP_GPIO_Port, IN_ESTOP_Pin); 8009608: 2180 movs r1, #128 @ 0x80 800960a: 4810 ldr r0, [pc, #64] @ (800964c ) 800960c: f006 f95c bl 800f8c8 8009610: 4603 mov r3, r0 8009612: e012 b.n 800963a case IN_FB1: return HAL_GPIO_ReadPin(IN_FB1_GPIO_Port, IN_FB1_Pin); 8009614: 2110 movs r1, #16 8009616: 480e ldr r0, [pc, #56] @ (8009650 ) 8009618: f006 f956 bl 800f8c8 800961c: 4603 mov r3, r0 800961e: e00c b.n 800963a case IN_CONT_FB_DC: return HAL_GPIO_ReadPin(IN_FB2_GPIO_Port, IN_FB2_Pin); 8009620: 2108 movs r1, #8 8009622: 480b ldr r0, [pc, #44] @ (8009650 ) 8009624: f006 f950 bl 800f8c8 8009628: 4603 mov r3, r0 800962a: e006 b.n 800963a case ISO_IN: return HAL_GPIO_ReadPin(ISO_IN_GPIO_Port, ISO_IN_Pin); 800962c: 2102 movs r1, #2 800962e: 4806 ldr r0, [pc, #24] @ (8009648 ) 8009630: f006 f94a bl 800f8c8 8009634: 4603 mov r3, r0 8009636: e000 b.n 800963a default: return 0; 8009638: 2300 movs r3, #0 } } 800963a: 4618 mov r0, r3 800963c: 3708 adds r7, #8 800963e: 46bd mov sp, r7 8009640: bd80 pop {r7, pc} 8009642: bf00 nop 8009644: 40010800 .word 0x40010800 8009648: 40011800 .word 0x40011800 800964c: 40011400 .word 0x40011400 8009650: 40010c00 .word 0x40010c00 08009654 : // // HAL_ADC_Stop(&hadc1); // stop adc return 0; } void Init_Peripheral(){ 8009654: b580 push {r7, lr} 8009656: af00 add r7, sp, #0 HAL_ADCEx_Calibration_Start(&hadc1); 8009658: 4815 ldr r0, [pc, #84] @ (80096b0 ) 800965a: f004 fdc1 bl 800e1e0 RELAY_Write(RELAY_AUX0, 0); 800965e: 2100 movs r1, #0 8009660: 2000 movs r0, #0 8009662: f7ff ff25 bl 80094b0 RELAY_Write(RELAY_AUX1, 0); 8009666: 2100 movs r1, #0 8009668: 2001 movs r0, #1 800966a: f7ff ff21 bl 80094b0 RELAY_Write(RELAY3, 0); 800966e: 2100 movs r1, #0 8009670: 2002 movs r0, #2 8009672: f7ff ff1d bl 80094b0 RELAY_Write(RELAY_DC, 0); 8009676: 2100 movs r1, #0 8009678: 2003 movs r0, #3 800967a: f7ff ff19 bl 80094b0 RELAY_Write(RELAY_AC, 0); 800967e: 2100 movs r1, #0 8009680: 2004 movs r0, #4 8009682: f7ff ff15 bl 80094b0 RELAY_Write(RELAY_CP, 1); 8009686: 2101 movs r1, #1 8009688: 2005 movs r0, #5 800968a: f7ff ff11 bl 80094b0 RELAY_Write(RELAY_CC, 1); 800968e: 2101 movs r1, #1 8009690: 2006 movs r0, #6 8009692: f7ff ff0d bl 80094b0 RELAY_Write(RELAY_DC1, 0); 8009696: 2100 movs r1, #0 8009698: 2007 movs r0, #7 800969a: f7ff ff09 bl 80094b0 SMAFilter_Init(&conn_temp_adc_filter[0]); 800969e: 4805 ldr r0, [pc, #20] @ (80096b4 ) 80096a0: f003 fb42 bl 800cd28 SMAFilter_Init(&conn_temp_adc_filter[1]); 80096a4: 4804 ldr r0, [pc, #16] @ (80096b8 ) 80096a6: f003 fb3f bl 800cd28 } 80096aa: bf00 nop 80096ac: bd80 pop {r7, pc} 80096ae: bf00 nop 80096b0: 200000f4 .word 0x200000f4 80096b4: 20000130 .word 0x20000130 80096b8: 20000158 .word 0x20000158 080096bc : float pt1000_to_temperature(float resistance) { 80096bc: b590 push {r4, r7, lr} 80096be: b087 sub sp, #28 80096c0: af00 add r7, sp, #0 80096c2: 6078 str r0, [r7, #4] // Константы для PT1000 const float R0 = 1000.0; // Сопротивление при 0 °C 80096c4: 4b0c ldr r3, [pc, #48] @ (80096f8 ) 80096c6: 617b str r3, [r7, #20] const float C_A = 3.9083E-3f; 80096c8: 4b0c ldr r3, [pc, #48] @ (80096fc ) 80096ca: 613b str r3, [r7, #16] float temperature = (resistance-R0) / ( R0 * C_A); 80096cc: 6979 ldr r1, [r7, #20] 80096ce: 6878 ldr r0, [r7, #4] 80096d0: f7ff f9cc bl 8008a6c <__aeabi_fsub> 80096d4: 4603 mov r3, r0 80096d6: 461c mov r4, r3 80096d8: 6939 ldr r1, [r7, #16] 80096da: 6978 ldr r0, [r7, #20] 80096dc: f7ff fad0 bl 8008c80 <__aeabi_fmul> 80096e0: 4603 mov r3, r0 80096e2: 4619 mov r1, r3 80096e4: 4620 mov r0, r4 80096e6: f7ff fb7f bl 8008de8 <__aeabi_fdiv> 80096ea: 4603 mov r3, r0 80096ec: 60fb str r3, [r7, #12] return temperature; 80096ee: 68fb ldr r3, [r7, #12] } 80096f0: 4618 mov r0, r3 80096f2: 371c adds r7, #28 80096f4: 46bd mov sp, r7 80096f6: bd90 pop {r4, r7, pc} 80096f8: 447a0000 .word 0x447a0000 80096fc: 3b801132 .word 0x3b801132 08009700 : float calculate_NTC_resistance(int adc_value, float Vref, float Vin, float R) { 8009700: b5b0 push {r4, r5, r7, lr} 8009702: b086 sub sp, #24 8009704: af00 add r7, sp, #0 8009706: 60f8 str r0, [r7, #12] 8009708: 60b9 str r1, [r7, #8] 800970a: 607a str r2, [r7, #4] 800970c: 603b str r3, [r7, #0] // Преобразуем значение АЦП в выходное напряжение float Vout = (adc_value / 4095.0) * Vref; 800970e: 68f8 ldr r0, [r7, #12] 8009710: f7fe fedc bl 80084cc <__aeabi_i2d> 8009714: a31c add r3, pc, #112 @ (adr r3, 8009788 ) 8009716: e9d3 2300 ldrd r2, r3, [r3] 800971a: f7ff f86b bl 80087f4 <__aeabi_ddiv> 800971e: 4602 mov r2, r0 8009720: 460b mov r3, r1 8009722: 4614 mov r4, r2 8009724: 461d mov r5, r3 8009726: 68b8 ldr r0, [r7, #8] 8009728: f7fe fee2 bl 80084f0 <__aeabi_f2d> 800972c: 4602 mov r2, r0 800972e: 460b mov r3, r1 8009730: 4620 mov r0, r4 8009732: 4629 mov r1, r5 8009734: f7fe ff34 bl 80085a0 <__aeabi_dmul> 8009738: 4602 mov r2, r0 800973a: 460b mov r3, r1 800973c: 4610 mov r0, r2 800973e: 4619 mov r1, r3 8009740: f7ff f940 bl 80089c4 <__aeabi_d2f> 8009744: 4603 mov r3, r0 8009746: 617b str r3, [r7, #20] // Проверяем, чтобы Vout не было равно Vin if (Vout >= Vin) { 8009748: 6879 ldr r1, [r7, #4] 800974a: 6978 ldr r0, [r7, #20] 800974c: f7ff fc4a bl 8008fe4 <__aeabi_fcmpge> 8009750: 4603 mov r3, r0 8009752: 2b00 cmp r3, #0 8009754: d001 beq.n 800975a return -1; // Ошибка: Vout не может быть больше или равно Vin 8009756: 4b0e ldr r3, [pc, #56] @ (8009790 ) 8009758: e010 b.n 800977c } // Вычисляем сопротивление термистора float R_NTC = R * (Vout / (Vin - Vout)); 800975a: 6979 ldr r1, [r7, #20] 800975c: 6878 ldr r0, [r7, #4] 800975e: f7ff f985 bl 8008a6c <__aeabi_fsub> 8009762: 4603 mov r3, r0 8009764: 4619 mov r1, r3 8009766: 6978 ldr r0, [r7, #20] 8009768: f7ff fb3e bl 8008de8 <__aeabi_fdiv> 800976c: 4603 mov r3, r0 800976e: 4619 mov r1, r3 8009770: 6838 ldr r0, [r7, #0] 8009772: f7ff fa85 bl 8008c80 <__aeabi_fmul> 8009776: 4603 mov r3, r0 8009778: 613b str r3, [r7, #16] return R_NTC; 800977a: 693b ldr r3, [r7, #16] } 800977c: 4618 mov r0, r3 800977e: 3718 adds r7, #24 8009780: 46bd mov sp, r7 8009782: bdb0 pop {r4, r5, r7, pc} 8009784: f3af 8000 nop.w 8009788: 00000000 .word 0x00000000 800978c: 40affe00 .word 0x40affe00 8009790: bf800000 .word 0xbf800000 08009794 : int16_t CONN_ReadTemp(uint8_t ch){ 8009794: b580 push {r7, lr} 8009796: b088 sub sp, #32 8009798: af00 add r7, sp, #0 800979a: 4603 mov r3, r0 800979c: 71fb strb r3, [r7, #7] ADC_LockBlocking(); 800979e: f000 f89b bl 80098d8 //TODO if(ch)ADC_Select_Channel(ADC_CHANNEL_8); 80097a2: 79fb ldrb r3, [r7, #7] 80097a4: 2b00 cmp r3, #0 80097a6: d003 beq.n 80097b0 80097a8: 2008 movs r0, #8 80097aa: f000 f853 bl 8009854 80097ae: e002 b.n 80097b6 else ADC_Select_Channel(ADC_CHANNEL_9); 80097b0: 2009 movs r0, #9 80097b2: f000 f84f bl 8009854 // Начало конверсии HAL_ADC_Start(&hadc1); 80097b6: 4822 ldr r0, [pc, #136] @ (8009840 ) 80097b8: f004 f992 bl 800dae0 // Ожидание окончания конверсии HAL_ADC_PollForConversion(&hadc1, HAL_MAX_DELAY); 80097bc: f04f 31ff mov.w r1, #4294967295 80097c0: 481f ldr r0, [pc, #124] @ (8009840 ) 80097c2: f004 fa67 bl 800dc94 // Получение значения uint32_t adcValue = HAL_ADC_GetValue(&hadc1); 80097c6: 481e ldr r0, [pc, #120] @ (8009840 ) 80097c8: f004 fb6a bl 800dea0 80097cc: 61f8 str r0, [r7, #28] // Остановка АЦП (по желанию) HAL_ADC_Stop(&hadc1); 80097ce: 481c ldr r0, [pc, #112] @ (8009840 ) 80097d0: f004 fa34 bl 800dc3c int32_t adc_filtered = SMAFilter_Update(&conn_temp_adc_filter[ch ? 1u : 0u], (int32_t)adcValue); 80097d4: 79fb ldrb r3, [r7, #7] 80097d6: 2b00 cmp r3, #0 80097d8: d001 beq.n 80097de 80097da: 2201 movs r2, #1 80097dc: e000 b.n 80097e0 80097de: 2200 movs r2, #0 80097e0: 4613 mov r3, r2 80097e2: 009b lsls r3, r3, #2 80097e4: 4413 add r3, r2 80097e6: 00db lsls r3, r3, #3 80097e8: 4a16 ldr r2, [pc, #88] @ (8009844 ) 80097ea: 4413 add r3, r2 80097ec: 69fa ldr r2, [r7, #28] 80097ee: 4611 mov r1, r2 80097f0: 4618 mov r0, r3 80097f2: f003 fabe bl 800cd72 80097f6: 61b8 str r0, [r7, #24] if((uint32_t)adc_filtered > 4000u) { 80097f8: 69bb ldr r3, [r7, #24] 80097fa: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 80097fe: d903 bls.n 8009808 ADC_Unlock(); 8009800: f000 f876 bl 80098f0 return 20; //Термодатчик не подключен 8009804: 2314 movs r3, #20 8009806: e017 b.n 8009838 } // int adc_value = 2048; // Пример значения АЦП float Vref = 3.3; // Напряжение опорное 8009808: 4b0f ldr r3, [pc, #60] @ (8009848 ) 800980a: 617b str r3, [r7, #20] float Vin = 5.0; // Входное напряжение 800980c: 4b0f ldr r3, [pc, #60] @ (800984c ) 800980e: 613b str r3, [r7, #16] float R = 1000; // Сопротивление резистора в Омах 8009810: 4b0f ldr r3, [pc, #60] @ (8009850 ) 8009812: 60fb str r3, [r7, #12] float temp = pt1000_to_temperature(calculate_NTC_resistance((int)adc_filtered, Vref, Vin, R)); 8009814: 68fb ldr r3, [r7, #12] 8009816: 693a ldr r2, [r7, #16] 8009818: 6979 ldr r1, [r7, #20] 800981a: 69b8 ldr r0, [r7, #24] 800981c: f7ff ff70 bl 8009700 8009820: 4603 mov r3, r0 8009822: 4618 mov r0, r3 8009824: f7ff ff4a bl 80096bc 8009828: 60b8 str r0, [r7, #8] ADC_Unlock(); 800982a: f000 f861 bl 80098f0 return (int16_t)temp; 800982e: 68b8 ldr r0, [r7, #8] 8009830: f7ff fbec bl 800900c <__aeabi_f2iz> 8009834: 4603 mov r3, r0 8009836: b21b sxth r3, r3 } 8009838: 4618 mov r0, r3 800983a: 3720 adds r7, #32 800983c: 46bd mov sp, r7 800983e: bd80 pop {r7, pc} 8009840: 200000f4 .word 0x200000f4 8009844: 20000130 .word 0x20000130 8009848: 40533333 .word 0x40533333 800984c: 40a00000 .word 0x40a00000 8009850: 447a0000 .word 0x447a0000 08009854 : int16_t GBT_ReadTemp(uint8_t ch){ return CONN_ReadTemp(ch); } void ADC_Select_Channel(uint32_t ch) { 8009854: b580 push {r7, lr} 8009856: b086 sub sp, #24 8009858: af00 add r7, sp, #0 800985a: 6078 str r0, [r7, #4] ADC_ChannelConfTypeDef conf = { 800985c: 687b ldr r3, [r7, #4] 800985e: 60fb str r3, [r7, #12] 8009860: 2301 movs r3, #1 8009862: 613b str r3, [r7, #16] 8009864: 2303 movs r3, #3 8009866: 617b str r3, [r7, #20] .Channel = ch, .Rank = 1, .SamplingTime = ADC_SAMPLETIME_28CYCLES_5, }; if (HAL_ADC_ConfigChannel(&hadc1, &conf) != HAL_OK) { 8009868: f107 030c add.w r3, r7, #12 800986c: 4619 mov r1, r3 800986e: 4806 ldr r0, [pc, #24] @ (8009888 ) 8009870: f004 fb22 bl 800deb8 8009874: 4603 mov r3, r0 8009876: 2b00 cmp r3, #0 8009878: d001 beq.n 800987e Error_Handler(); 800987a: f001 f8b9 bl 800a9f0 } } 800987e: bf00 nop 8009880: 3718 adds r7, #24 8009882: 46bd mov sp, r7 8009884: bd80 pop {r7, pc} 8009886: bf00 nop 8009888: 200000f4 .word 0x200000f4 0800988c : uint8_t ADC_TryLock(void) { 800988c: b480 push {r7} 800988e: b083 sub sp, #12 8009890: af00 add r7, sp, #0 */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8009892: f3ef 8310 mrs r3, PRIMASK 8009896: 603b str r3, [r7, #0] return(result); 8009898: 683b ldr r3, [r7, #0] uint32_t primask = __get_PRIMASK(); 800989a: 607b str r3, [r7, #4] __ASM volatile ("cpsid i" : : : "memory"); 800989c: b672 cpsid i } 800989e: bf00 nop __disable_irq(); if (adc_lock != 0u) { 80098a0: 4b0c ldr r3, [pc, #48] @ (80098d4 ) 80098a2: 781b ldrb r3, [r3, #0] 80098a4: b2db uxtb r3, r3 80098a6: 2b00 cmp r3, #0 80098a8: d006 beq.n 80098b8 if (primask == 0u) { 80098aa: 687b ldr r3, [r7, #4] 80098ac: 2b00 cmp r3, #0 80098ae: d101 bne.n 80098b4 __ASM volatile ("cpsie i" : : : "memory"); 80098b0: b662 cpsie i } 80098b2: bf00 nop __enable_irq(); } return 0u; 80098b4: 2300 movs r3, #0 80098b6: e008 b.n 80098ca } adc_lock = 1u; 80098b8: 4b06 ldr r3, [pc, #24] @ (80098d4 ) 80098ba: 2201 movs r2, #1 80098bc: 701a strb r2, [r3, #0] if (primask == 0u) { 80098be: 687b ldr r3, [r7, #4] 80098c0: 2b00 cmp r3, #0 80098c2: d101 bne.n 80098c8 __ASM volatile ("cpsie i" : : : "memory"); 80098c4: b662 cpsie i } 80098c6: bf00 nop __enable_irq(); } return 1u; 80098c8: 2301 movs r3, #1 } 80098ca: 4618 mov r0, r3 80098cc: 370c adds r7, #12 80098ce: 46bd mov sp, r7 80098d0: bc80 pop {r7} 80098d2: 4770 bx lr 80098d4: 2000012c .word 0x2000012c 080098d8 : void ADC_LockBlocking(void) { 80098d8: b580 push {r7, lr} 80098da: af00 add r7, sp, #0 while (ADC_TryLock() == 0u) { 80098dc: bf00 nop 80098de: f7ff ffd5 bl 800988c 80098e2: 4603 mov r3, r0 80098e4: 2b00 cmp r3, #0 80098e6: d0fa beq.n 80098de /* wait in main context until ADC is free */ } } 80098e8: bf00 nop 80098ea: bf00 nop 80098ec: bd80 pop {r7, pc} ... 080098f0 : void ADC_Unlock(void) { 80098f0: b480 push {r7} 80098f2: b083 sub sp, #12 80098f4: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 80098f6: f3ef 8310 mrs r3, PRIMASK 80098fa: 603b str r3, [r7, #0] return(result); 80098fc: 683b ldr r3, [r7, #0] uint32_t primask = __get_PRIMASK(); 80098fe: 607b str r3, [r7, #4] __ASM volatile ("cpsid i" : : : "memory"); 8009900: b672 cpsid i } 8009902: bf00 nop __disable_irq(); adc_lock = 0u; 8009904: 4b06 ldr r3, [pc, #24] @ (8009920 ) 8009906: 2200 movs r2, #0 8009908: 701a strb r2, [r3, #0] if (primask == 0u) { 800990a: 687b ldr r3, [r7, #4] 800990c: 2b00 cmp r3, #0 800990e: d101 bne.n 8009914 __ASM volatile ("cpsie i" : : : "memory"); 8009910: b662 cpsie i } 8009912: bf00 nop __enable_irq(); } } 8009914: bf00 nop 8009916: 370c adds r7, #12 8009918: 46bd mov sp, r7 800991a: bc80 pop {r7} 800991c: 4770 bx lr 800991e: bf00 nop 8009920: 2000012c .word 0x2000012c 08009924 : CAN_HandleTypeDef hcan1; CAN_HandleTypeDef hcan2; /* CAN1 init function */ void MX_CAN1_Init(void) { 8009924: b580 push {r7, lr} 8009926: af00 add r7, sp, #0 /* USER CODE END CAN1_Init 0 */ /* USER CODE BEGIN CAN1_Init 1 */ /* USER CODE END CAN1_Init 1 */ hcan1.Instance = CAN1; 8009928: 4b17 ldr r3, [pc, #92] @ (8009988 ) 800992a: 4a18 ldr r2, [pc, #96] @ (800998c ) 800992c: 601a str r2, [r3, #0] hcan1.Init.Prescaler = 8; 800992e: 4b16 ldr r3, [pc, #88] @ (8009988 ) 8009930: 2208 movs r2, #8 8009932: 605a str r2, [r3, #4] hcan1.Init.Mode = CAN_MODE_NORMAL; 8009934: 4b14 ldr r3, [pc, #80] @ (8009988 ) 8009936: 2200 movs r2, #0 8009938: 609a str r2, [r3, #8] hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; 800993a: 4b13 ldr r3, [pc, #76] @ (8009988 ) 800993c: 2200 movs r2, #0 800993e: 60da str r2, [r3, #12] hcan1.Init.TimeSeg1 = CAN_BS1_15TQ; 8009940: 4b11 ldr r3, [pc, #68] @ (8009988 ) 8009942: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009946: 611a str r2, [r3, #16] hcan1.Init.TimeSeg2 = CAN_BS2_2TQ; 8009948: 4b0f ldr r3, [pc, #60] @ (8009988 ) 800994a: f44f 1280 mov.w r2, #1048576 @ 0x100000 800994e: 615a str r2, [r3, #20] hcan1.Init.TimeTriggeredMode = DISABLE; 8009950: 4b0d ldr r3, [pc, #52] @ (8009988 ) 8009952: 2200 movs r2, #0 8009954: 761a strb r2, [r3, #24] hcan1.Init.AutoBusOff = ENABLE; 8009956: 4b0c ldr r3, [pc, #48] @ (8009988 ) 8009958: 2201 movs r2, #1 800995a: 765a strb r2, [r3, #25] hcan1.Init.AutoWakeUp = ENABLE; 800995c: 4b0a ldr r3, [pc, #40] @ (8009988 ) 800995e: 2201 movs r2, #1 8009960: 769a strb r2, [r3, #26] hcan1.Init.AutoRetransmission = ENABLE; 8009962: 4b09 ldr r3, [pc, #36] @ (8009988 ) 8009964: 2201 movs r2, #1 8009966: 76da strb r2, [r3, #27] hcan1.Init.ReceiveFifoLocked = DISABLE; 8009968: 4b07 ldr r3, [pc, #28] @ (8009988 ) 800996a: 2200 movs r2, #0 800996c: 771a strb r2, [r3, #28] hcan1.Init.TransmitFifoPriority = ENABLE; 800996e: 4b06 ldr r3, [pc, #24] @ (8009988 ) 8009970: 2201 movs r2, #1 8009972: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan1) != HAL_OK) 8009974: 4804 ldr r0, [pc, #16] @ (8009988 ) 8009976: f004 fce1 bl 800e33c 800997a: 4603 mov r3, r0 800997c: 2b00 cmp r3, #0 800997e: d001 beq.n 8009984 { Error_Handler(); 8009980: f001 f836 bl 800a9f0 } /* USER CODE BEGIN CAN1_Init 2 */ /* USER CODE END CAN1_Init 2 */ } 8009984: bf00 nop 8009986: bd80 pop {r7, pc} 8009988: 20000180 .word 0x20000180 800998c: 40006400 .word 0x40006400 08009990 : /* CAN2 init function */ void MX_CAN2_Init(void) { 8009990: b580 push {r7, lr} 8009992: af00 add r7, sp, #0 /* USER CODE END CAN2_Init 0 */ /* USER CODE BEGIN CAN2_Init 1 */ /* USER CODE END CAN2_Init 1 */ hcan2.Instance = CAN2; 8009994: 4b17 ldr r3, [pc, #92] @ (80099f4 ) 8009996: 4a18 ldr r2, [pc, #96] @ (80099f8 ) 8009998: 601a str r2, [r3, #0] hcan2.Init.Prescaler = 16; 800999a: 4b16 ldr r3, [pc, #88] @ (80099f4 ) 800999c: 2210 movs r2, #16 800999e: 605a str r2, [r3, #4] hcan2.Init.Mode = CAN_MODE_NORMAL; 80099a0: 4b14 ldr r3, [pc, #80] @ (80099f4 ) 80099a2: 2200 movs r2, #0 80099a4: 609a str r2, [r3, #8] hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; 80099a6: 4b13 ldr r3, [pc, #76] @ (80099f4 ) 80099a8: 2200 movs r2, #0 80099aa: 60da str r2, [r3, #12] hcan2.Init.TimeSeg1 = CAN_BS1_15TQ; 80099ac: 4b11 ldr r3, [pc, #68] @ (80099f4 ) 80099ae: f44f 2260 mov.w r2, #917504 @ 0xe0000 80099b2: 611a str r2, [r3, #16] hcan2.Init.TimeSeg2 = CAN_BS2_2TQ; 80099b4: 4b0f ldr r3, [pc, #60] @ (80099f4 ) 80099b6: f44f 1280 mov.w r2, #1048576 @ 0x100000 80099ba: 615a str r2, [r3, #20] hcan2.Init.TimeTriggeredMode = DISABLE; 80099bc: 4b0d ldr r3, [pc, #52] @ (80099f4 ) 80099be: 2200 movs r2, #0 80099c0: 761a strb r2, [r3, #24] hcan2.Init.AutoBusOff = ENABLE; 80099c2: 4b0c ldr r3, [pc, #48] @ (80099f4 ) 80099c4: 2201 movs r2, #1 80099c6: 765a strb r2, [r3, #25] hcan2.Init.AutoWakeUp = ENABLE; 80099c8: 4b0a ldr r3, [pc, #40] @ (80099f4 ) 80099ca: 2201 movs r2, #1 80099cc: 769a strb r2, [r3, #26] hcan2.Init.AutoRetransmission = ENABLE; 80099ce: 4b09 ldr r3, [pc, #36] @ (80099f4 ) 80099d0: 2201 movs r2, #1 80099d2: 76da strb r2, [r3, #27] hcan2.Init.ReceiveFifoLocked = DISABLE; 80099d4: 4b07 ldr r3, [pc, #28] @ (80099f4 ) 80099d6: 2200 movs r2, #0 80099d8: 771a strb r2, [r3, #28] hcan2.Init.TransmitFifoPriority = ENABLE; 80099da: 4b06 ldr r3, [pc, #24] @ (80099f4 ) 80099dc: 2201 movs r2, #1 80099de: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan2) != HAL_OK) 80099e0: 4804 ldr r0, [pc, #16] @ (80099f4 ) 80099e2: f004 fcab bl 800e33c 80099e6: 4603 mov r3, r0 80099e8: 2b00 cmp r3, #0 80099ea: d001 beq.n 80099f0 { Error_Handler(); 80099ec: f001 f800 bl 800a9f0 } /* USER CODE BEGIN CAN2_Init 2 */ /* USER CODE END CAN2_Init 2 */ } 80099f0: bf00 nop 80099f2: bd80 pop {r7, pc} 80099f4: 200001a8 .word 0x200001a8 80099f8: 40006800 .word 0x40006800 080099fc : static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0; void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) { 80099fc: b580 push {r7, lr} 80099fe: b08e sub sp, #56 @ 0x38 8009a00: af00 add r7, sp, #0 8009a02: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8009a04: f107 0320 add.w r3, r7, #32 8009a08: 2200 movs r2, #0 8009a0a: 601a str r2, [r3, #0] 8009a0c: 605a str r2, [r3, #4] 8009a0e: 609a str r2, [r3, #8] 8009a10: 60da str r2, [r3, #12] if(canHandle->Instance==CAN1) 8009a12: 687b ldr r3, [r7, #4] 8009a14: 681b ldr r3, [r3, #0] 8009a16: 4a61 ldr r2, [pc, #388] @ (8009b9c ) 8009a18: 4293 cmp r3, r2 8009a1a: d153 bne.n 8009ac4 { /* USER CODE BEGIN CAN1_MspInit 0 */ /* USER CODE END CAN1_MspInit 0 */ /* CAN1 clock enable */ HAL_RCC_CAN1_CLK_ENABLED++; 8009a1c: 4b60 ldr r3, [pc, #384] @ (8009ba0 ) 8009a1e: 681b ldr r3, [r3, #0] 8009a20: 3301 adds r3, #1 8009a22: 4a5f ldr r2, [pc, #380] @ (8009ba0 ) 8009a24: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009a26: 4b5e ldr r3, [pc, #376] @ (8009ba0 ) 8009a28: 681b ldr r3, [r3, #0] 8009a2a: 2b01 cmp r3, #1 8009a2c: d10b bne.n 8009a46 __HAL_RCC_CAN1_CLK_ENABLE(); 8009a2e: 4b5d ldr r3, [pc, #372] @ (8009ba4 ) 8009a30: 69db ldr r3, [r3, #28] 8009a32: 4a5c ldr r2, [pc, #368] @ (8009ba4 ) 8009a34: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009a38: 61d3 str r3, [r2, #28] 8009a3a: 4b5a ldr r3, [pc, #360] @ (8009ba4 ) 8009a3c: 69db ldr r3, [r3, #28] 8009a3e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009a42: 61fb str r3, [r7, #28] 8009a44: 69fb ldr r3, [r7, #28] } __HAL_RCC_GPIOD_CLK_ENABLE(); 8009a46: 4b57 ldr r3, [pc, #348] @ (8009ba4 ) 8009a48: 699b ldr r3, [r3, #24] 8009a4a: 4a56 ldr r2, [pc, #344] @ (8009ba4 ) 8009a4c: f043 0320 orr.w r3, r3, #32 8009a50: 6193 str r3, [r2, #24] 8009a52: 4b54 ldr r3, [pc, #336] @ (8009ba4 ) 8009a54: 699b ldr r3, [r3, #24] 8009a56: f003 0320 and.w r3, r3, #32 8009a5a: 61bb str r3, [r7, #24] 8009a5c: 69bb ldr r3, [r7, #24] /**CAN1 GPIO Configuration PD0 ------> CAN1_RX PD1 ------> CAN1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0; 8009a5e: 2301 movs r3, #1 8009a60: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009a62: 2300 movs r3, #0 8009a64: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009a66: 2300 movs r3, #0 8009a68: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009a6a: f107 0320 add.w r3, r7, #32 8009a6e: 4619 mov r1, r3 8009a70: 484d ldr r0, [pc, #308] @ (8009ba8 ) 8009a72: f005 fda5 bl 800f5c0 GPIO_InitStruct.Pin = GPIO_PIN_1; 8009a76: 2302 movs r3, #2 8009a78: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009a7a: 2302 movs r3, #2 8009a7c: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009a7e: 2303 movs r3, #3 8009a80: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009a82: f107 0320 add.w r3, r7, #32 8009a86: 4619 mov r1, r3 8009a88: 4847 ldr r0, [pc, #284] @ (8009ba8 ) 8009a8a: f005 fd99 bl 800f5c0 __HAL_AFIO_REMAP_CAN1_3(); 8009a8e: 4b47 ldr r3, [pc, #284] @ (8009bac ) 8009a90: 685b ldr r3, [r3, #4] 8009a92: 633b str r3, [r7, #48] @ 0x30 8009a94: 6b3b ldr r3, [r7, #48] @ 0x30 8009a96: f423 43c0 bic.w r3, r3, #24576 @ 0x6000 8009a9a: 633b str r3, [r7, #48] @ 0x30 8009a9c: 6b3b ldr r3, [r7, #48] @ 0x30 8009a9e: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009aa2: 633b str r3, [r7, #48] @ 0x30 8009aa4: 6b3b ldr r3, [r7, #48] @ 0x30 8009aa6: f443 43c0 orr.w r3, r3, #24576 @ 0x6000 8009aaa: 633b str r3, [r7, #48] @ 0x30 8009aac: 4a3f ldr r2, [pc, #252] @ (8009bac ) 8009aae: 6b3b ldr r3, [r7, #48] @ 0x30 8009ab0: 6053 str r3, [r2, #4] /* CAN1 interrupt Init */ HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0); 8009ab2: 2200 movs r2, #0 8009ab4: 2100 movs r1, #0 8009ab6: 2014 movs r0, #20 8009ab8: f005 fbed bl 800f296 HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn); 8009abc: 2014 movs r0, #20 8009abe: f005 fc06 bl 800f2ce HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); /* USER CODE BEGIN CAN2_MspInit 1 */ /* USER CODE END CAN2_MspInit 1 */ } } 8009ac2: e067 b.n 8009b94 else if(canHandle->Instance==CAN2) 8009ac4: 687b ldr r3, [r7, #4] 8009ac6: 681b ldr r3, [r3, #0] 8009ac8: 4a39 ldr r2, [pc, #228] @ (8009bb0 ) 8009aca: 4293 cmp r3, r2 8009acc: d162 bne.n 8009b94 __HAL_RCC_CAN2_CLK_ENABLE(); 8009ace: 4b35 ldr r3, [pc, #212] @ (8009ba4 ) 8009ad0: 69db ldr r3, [r3, #28] 8009ad2: 4a34 ldr r2, [pc, #208] @ (8009ba4 ) 8009ad4: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 8009ad8: 61d3 str r3, [r2, #28] 8009ada: 4b32 ldr r3, [pc, #200] @ (8009ba4 ) 8009adc: 69db ldr r3, [r3, #28] 8009ade: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8009ae2: 617b str r3, [r7, #20] 8009ae4: 697b ldr r3, [r7, #20] HAL_RCC_CAN1_CLK_ENABLED++; 8009ae6: 4b2e ldr r3, [pc, #184] @ (8009ba0 ) 8009ae8: 681b ldr r3, [r3, #0] 8009aea: 3301 adds r3, #1 8009aec: 4a2c ldr r2, [pc, #176] @ (8009ba0 ) 8009aee: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009af0: 4b2b ldr r3, [pc, #172] @ (8009ba0 ) 8009af2: 681b ldr r3, [r3, #0] 8009af4: 2b01 cmp r3, #1 8009af6: d10b bne.n 8009b10 __HAL_RCC_CAN1_CLK_ENABLE(); 8009af8: 4b2a ldr r3, [pc, #168] @ (8009ba4 ) 8009afa: 69db ldr r3, [r3, #28] 8009afc: 4a29 ldr r2, [pc, #164] @ (8009ba4 ) 8009afe: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009b02: 61d3 str r3, [r2, #28] 8009b04: 4b27 ldr r3, [pc, #156] @ (8009ba4 ) 8009b06: 69db ldr r3, [r3, #28] 8009b08: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009b0c: 613b str r3, [r7, #16] 8009b0e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8009b10: 4b24 ldr r3, [pc, #144] @ (8009ba4 ) 8009b12: 699b ldr r3, [r3, #24] 8009b14: 4a23 ldr r2, [pc, #140] @ (8009ba4 ) 8009b16: f043 0308 orr.w r3, r3, #8 8009b1a: 6193 str r3, [r2, #24] 8009b1c: 4b21 ldr r3, [pc, #132] @ (8009ba4 ) 8009b1e: 699b ldr r3, [r3, #24] 8009b20: f003 0308 and.w r3, r3, #8 8009b24: 60fb str r3, [r7, #12] 8009b26: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_5; 8009b28: 2320 movs r3, #32 8009b2a: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009b2c: 2300 movs r3, #0 8009b2e: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009b30: 2300 movs r3, #0 8009b32: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009b34: f107 0320 add.w r3, r7, #32 8009b38: 4619 mov r1, r3 8009b3a: 481e ldr r0, [pc, #120] @ (8009bb4 ) 8009b3c: f005 fd40 bl 800f5c0 GPIO_InitStruct.Pin = GPIO_PIN_6; 8009b40: 2340 movs r3, #64 @ 0x40 8009b42: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009b44: 2302 movs r3, #2 8009b46: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009b48: 2303 movs r3, #3 8009b4a: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009b4c: f107 0320 add.w r3, r7, #32 8009b50: 4619 mov r1, r3 8009b52: 4818 ldr r0, [pc, #96] @ (8009bb4 ) 8009b54: f005 fd34 bl 800f5c0 __HAL_AFIO_REMAP_CAN2_ENABLE(); 8009b58: 4b14 ldr r3, [pc, #80] @ (8009bac ) 8009b5a: 685b ldr r3, [r3, #4] 8009b5c: 637b str r3, [r7, #52] @ 0x34 8009b5e: 6b7b ldr r3, [r7, #52] @ 0x34 8009b60: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009b64: 637b str r3, [r7, #52] @ 0x34 8009b66: 6b7b ldr r3, [r7, #52] @ 0x34 8009b68: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8009b6c: 637b str r3, [r7, #52] @ 0x34 8009b6e: 4a0f ldr r2, [pc, #60] @ (8009bac ) 8009b70: 6b7b ldr r3, [r7, #52] @ 0x34 8009b72: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(CAN2_TX_IRQn, 0, 0); 8009b74: 2200 movs r2, #0 8009b76: 2100 movs r1, #0 8009b78: 203f movs r0, #63 @ 0x3f 8009b7a: f005 fb8c bl 800f296 HAL_NVIC_EnableIRQ(CAN2_TX_IRQn); 8009b7e: 203f movs r0, #63 @ 0x3f 8009b80: f005 fba5 bl 800f2ce HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 0, 0); 8009b84: 2200 movs r2, #0 8009b86: 2100 movs r1, #0 8009b88: 2041 movs r0, #65 @ 0x41 8009b8a: f005 fb84 bl 800f296 HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); 8009b8e: 2041 movs r0, #65 @ 0x41 8009b90: f005 fb9d bl 800f2ce } 8009b94: bf00 nop 8009b96: 3738 adds r7, #56 @ 0x38 8009b98: 46bd mov sp, r7 8009b9a: bd80 pop {r7, pc} 8009b9c: 40006400 .word 0x40006400 8009ba0: 200001d0 .word 0x200001d0 8009ba4: 40021000 .word 0x40021000 8009ba8: 40011400 .word 0x40011400 8009bac: 40010000 .word 0x40010000 8009bb0: 40006800 .word 0x40006800 8009bb4: 40010c00 .word 0x40010c00 08009bb8 : #include "debug.h" ChargingConnector_t CONN; CONN_State_t connectorState; void CONN_Init(){ 8009bb8: b480 push {r7} 8009bba: af00 add r7, sp, #0 CONN.connControl = CMD_NONE; 8009bbc: 4b08 ldr r3, [pc, #32] @ (8009be0 ) 8009bbe: 2200 movs r2, #0 8009bc0: 701a strb r2, [r3, #0] CONN.connState = Unknown; 8009bc2: 4b07 ldr r3, [pc, #28] @ (8009be0 ) 8009bc4: 2200 movs r2, #0 8009bc6: 705a strb r2, [r3, #1] CONN.RequestedVoltage = PSU_MIN_VOLTAGE; 8009bc8: 4b05 ldr r3, [pc, #20] @ (8009be0 ) 8009bca: 2200 movs r2, #0 8009bcc: f062 0269 orn r2, r2, #105 @ 0x69 8009bd0: 73da strb r2, [r3, #15] 8009bd2: 2200 movs r2, #0 8009bd4: 741a strb r2, [r3, #16] } 8009bd6: bf00 nop 8009bd8: 46bd mov sp, r7 8009bda: bc80 pop {r7} 8009bdc: 4770 bx lr 8009bde: bf00 nop 8009be0: 200001d4 .word 0x200001d4 08009be4 : void CONN_Loop(){ 8009be4: b580 push {r7, lr} 8009be6: af00 add r7, sp, #0 static CONN_State_t last_connState = Unknown; if(last_connState != CONN.connState){ 8009be8: 4b1a ldr r3, [pc, #104] @ (8009c54 ) 8009bea: 785a ldrb r2, [r3, #1] 8009bec: 4b1a ldr r3, [pc, #104] @ (8009c58 ) 8009bee: 781b ldrb r3, [r3, #0] 8009bf0: 429a cmp r2, r3 8009bf2: d006 beq.n 8009c02 last_connState = CONN.connState; 8009bf4: 4b17 ldr r3, [pc, #92] @ (8009c54 ) 8009bf6: 785a ldrb r2, [r3, #1] 8009bf8: 4b17 ldr r3, [pc, #92] @ (8009c58 ) 8009bfa: 701a strb r2, [r3, #0] CONN.connControl = CMD_NONE; 8009bfc: 4b15 ldr r3, [pc, #84] @ (8009c54 ) 8009bfe: 2200 movs r2, #0 8009c00: 701a strb r2, [r3, #0] } if(PSU0.cont_fault){ 8009c02: 4b16 ldr r3, [pc, #88] @ (8009c5c ) 8009c04: 7b1b ldrb r3, [r3, #12] 8009c06: 2b00 cmp r3, #0 8009c08: d003 beq.n 8009c12 CONN.chargingError = CONN_ERR_CONTACTOR; 8009c0a: 4b12 ldr r3, [pc, #72] @ (8009c54 ) 8009c0c: 2207 movs r2, #7 8009c0e: 775a strb r2, [r3, #29] 8009c10: e00e b.n 8009c30 } else if(PSU0.psu_fault){ 8009c12: 4b12 ldr r3, [pc, #72] @ (8009c5c ) 8009c14: 7b5b ldrb r3, [r3, #13] 8009c16: 2b00 cmp r3, #0 8009c18: d003 beq.n 8009c22 CONN.chargingError = CONN_ERR_PSU_FAULT; 8009c1a: 4b0e ldr r3, [pc, #56] @ (8009c54 ) 8009c1c: 220a movs r2, #10 8009c1e: 775a strb r2, [r3, #29] 8009c20: e006 b.n 8009c30 // } else if(!CTRL.ac_ok) { // CONN.chargingError = CONN_ERR_AC_FAULT; // } else }else if (CONN.EvConnected == 0){ 8009c22: 4b0c ldr r3, [pc, #48] @ (8009c54 ) 8009c24: 7f9b ldrb r3, [r3, #30] 8009c26: 2b00 cmp r3, #0 8009c28: d102 bne.n 8009c30 CONN.chargingError = CONN_NO_ERROR; 8009c2a: 4b0a ldr r3, [pc, #40] @ (8009c54 ) 8009c2c: 2200 movs r2, #0 8009c2e: 775a strb r2, [r3, #29] } if(ED_TraceWarning(CONN.chargingError, 0)) printf("CONN%d Error: %d\n", 0, CONN.chargingError); 8009c30: 4b08 ldr r3, [pc, #32] @ (8009c54 ) 8009c32: 7f5b ldrb r3, [r3, #29] 8009c34: 2100 movs r1, #0 8009c36: 4618 mov r0, r3 8009c38: f000 fd72 bl 800a720 8009c3c: 4603 mov r3, r0 8009c3e: 2b00 cmp r3, #0 8009c40: d006 beq.n 8009c50 8009c42: 4b04 ldr r3, [pc, #16] @ (8009c54 ) 8009c44: 7f5b ldrb r3, [r3, #29] 8009c46: 461a mov r2, r3 8009c48: 2100 movs r1, #0 8009c4a: 4805 ldr r0, [pc, #20] @ (8009c60 ) 8009c4c: f009 f922 bl 8012e94 } 8009c50: bf00 nop 8009c52: bd80 pop {r7, pc} 8009c54: 200001d4 .word 0x200001d4 8009c58: 200001f4 .word 0x200001f4 8009c5c: 20000724 .word 0x20000724 8009c60: 08013f7c .word 0x08013f7c 08009c64 : void CONN_Task(){ 8009c64: b580 push {r7, lr} 8009c66: af00 add r7, sp, #0 /* CCS state machine is handled in serial.c. * Keep this task lightweight for scheduler compatibility. */ if (CONN.chargingError != CONN_NO_ERROR) { 8009c68: 4b0d ldr r3, [pc, #52] @ (8009ca0 ) 8009c6a: 7f5b ldrb r3, [r3, #29] 8009c6c: 2b00 cmp r3, #0 8009c6e: d003 beq.n 8009c78 CONN_SetState(Disabled); 8009c70: 2002 movs r0, #2 8009c72: f000 f819 bl 8009ca8 return; 8009c76: e012 b.n 8009c9e } if (connectorState == Unknown) { 8009c78: 4b0a ldr r3, [pc, #40] @ (8009ca4 ) 8009c7a: 781b ldrb r3, [r3, #0] 8009c7c: 2b00 cmp r3, #0 8009c7e: d103 bne.n 8009c88 CONN_SetState(Unplugged); 8009c80: 2001 movs r0, #1 8009c82: f000 f811 bl 8009ca8 8009c86: e00a b.n 8009c9e } else if (connectorState == Disabled && CONN.chargingError == CONN_NO_ERROR) { 8009c88: 4b06 ldr r3, [pc, #24] @ (8009ca4 ) 8009c8a: 781b ldrb r3, [r3, #0] 8009c8c: 2b02 cmp r3, #2 8009c8e: d106 bne.n 8009c9e 8009c90: 4b03 ldr r3, [pc, #12] @ (8009ca0 ) 8009c92: 7f5b ldrb r3, [r3, #29] 8009c94: 2b00 cmp r3, #0 8009c96: d102 bne.n 8009c9e CONN_SetState(Unplugged); 8009c98: 2001 movs r0, #1 8009c9a: f000 f805 bl 8009ca8 } } 8009c9e: bd80 pop {r7, pc} 8009ca0: 200001d4 .word 0x200001d4 8009ca4: 200001f3 .word 0x200001f3 08009ca8 : void CONN_SetState(CONN_State_t state){ 8009ca8: b580 push {r7, lr} 8009caa: b082 sub sp, #8 8009cac: af00 add r7, sp, #0 8009cae: 4603 mov r3, r0 8009cb0: 71fb strb r3, [r7, #7] if (connectorState == state) { 8009cb2: 4b41 ldr r3, [pc, #260] @ (8009db8 ) 8009cb4: 781b ldrb r3, [r3, #0] 8009cb6: 79fa ldrb r2, [r7, #7] 8009cb8: 429a cmp r2, r3 8009cba: d103 bne.n 8009cc4 CONN.connState = state; 8009cbc: 4a3f ldr r2, [pc, #252] @ (8009dbc ) 8009cbe: 79fb ldrb r3, [r7, #7] 8009cc0: 7053 strb r3, [r2, #1] return; 8009cc2: e075 b.n 8009db0 } connectorState = state; 8009cc4: 4a3c ldr r2, [pc, #240] @ (8009db8 ) 8009cc6: 79fb ldrb r3, [r7, #7] 8009cc8: 7013 strb r3, [r2, #0] if(connectorState == Unknown) log_printf(LOG_INFO, "Connector: Unknown\n"); 8009cca: 4b3b ldr r3, [pc, #236] @ (8009db8 ) 8009ccc: 781b ldrb r3, [r3, #0] 8009cce: 2b00 cmp r3, #0 8009cd0: d103 bne.n 8009cda 8009cd2: 493b ldr r1, [pc, #236] @ (8009dc0 ) 8009cd4: 2007 movs r0, #7 8009cd6: f000 fbcb bl 800a470 if(connectorState == Unplugged) log_printf(LOG_INFO, "Connector: Unplugged\n"); 8009cda: 4b37 ldr r3, [pc, #220] @ (8009db8 ) 8009cdc: 781b ldrb r3, [r3, #0] 8009cde: 2b01 cmp r3, #1 8009ce0: d103 bne.n 8009cea 8009ce2: 4938 ldr r1, [pc, #224] @ (8009dc4 ) 8009ce4: 2007 movs r0, #7 8009ce6: f000 fbc3 bl 800a470 if(connectorState == Disabled) log_printf(LOG_INFO, "Connector: Disabled\n"); 8009cea: 4b33 ldr r3, [pc, #204] @ (8009db8 ) 8009cec: 781b ldrb r3, [r3, #0] 8009cee: 2b02 cmp r3, #2 8009cf0: d103 bne.n 8009cfa 8009cf2: 4935 ldr r1, [pc, #212] @ (8009dc8 ) 8009cf4: 2007 movs r0, #7 8009cf6: f000 fbbb bl 800a470 if(connectorState == Preparing) log_printf(LOG_INFO, "Connector: Preparing\n"); 8009cfa: 4b2f ldr r3, [pc, #188] @ (8009db8 ) 8009cfc: 781b ldrb r3, [r3, #0] 8009cfe: 2b03 cmp r3, #3 8009d00: d103 bne.n 8009d0a 8009d02: 4932 ldr r1, [pc, #200] @ (8009dcc ) 8009d04: 2007 movs r0, #7 8009d06: f000 fbb3 bl 800a470 if(connectorState == AuthRequired) log_printf(LOG_INFO, "Connector: AuthRequired\n"); 8009d0a: 4b2b ldr r3, [pc, #172] @ (8009db8 ) 8009d0c: 781b ldrb r3, [r3, #0] 8009d0e: 2b04 cmp r3, #4 8009d10: d103 bne.n 8009d1a 8009d12: 492f ldr r1, [pc, #188] @ (8009dd0 ) 8009d14: 2007 movs r0, #7 8009d16: f000 fbab bl 800a470 if(connectorState == WaitingForEnergy) log_printf(LOG_INFO, "Connector: WaitingForEnergy\n"); 8009d1a: 4b27 ldr r3, [pc, #156] @ (8009db8 ) 8009d1c: 781b ldrb r3, [r3, #0] 8009d1e: 2b05 cmp r3, #5 8009d20: d103 bne.n 8009d2a 8009d22: 492c ldr r1, [pc, #176] @ (8009dd4 ) 8009d24: 2007 movs r0, #7 8009d26: f000 fba3 bl 800a470 if(connectorState == ChargingPausedEV) log_printf(LOG_INFO, "Connector: ChargingPausedEV\n"); 8009d2a: 4b23 ldr r3, [pc, #140] @ (8009db8 ) 8009d2c: 781b ldrb r3, [r3, #0] 8009d2e: 2b06 cmp r3, #6 8009d30: d103 bne.n 8009d3a 8009d32: 4929 ldr r1, [pc, #164] @ (8009dd8 ) 8009d34: 2007 movs r0, #7 8009d36: f000 fb9b bl 800a470 if(connectorState == ChargingPausedEVSE) log_printf(LOG_INFO, "Connector: ChargingPausedEVSE\n"); 8009d3a: 4b1f ldr r3, [pc, #124] @ (8009db8 ) 8009d3c: 781b ldrb r3, [r3, #0] 8009d3e: 2b07 cmp r3, #7 8009d40: d103 bne.n 8009d4a 8009d42: 4926 ldr r1, [pc, #152] @ (8009ddc ) 8009d44: 2007 movs r0, #7 8009d46: f000 fb93 bl 800a470 if(connectorState == Charging) log_printf(LOG_INFO, "Connector: Charging\n"); 8009d4a: 4b1b ldr r3, [pc, #108] @ (8009db8 ) 8009d4c: 781b ldrb r3, [r3, #0] 8009d4e: 2b08 cmp r3, #8 8009d50: d103 bne.n 8009d5a 8009d52: 4923 ldr r1, [pc, #140] @ (8009de0 ) 8009d54: 2007 movs r0, #7 8009d56: f000 fb8b bl 800a470 if(connectorState == AuthTimeout) log_printf(LOG_INFO, "Connector: AuthTimeout\n"); 8009d5a: 4b17 ldr r3, [pc, #92] @ (8009db8 ) 8009d5c: 781b ldrb r3, [r3, #0] 8009d5e: 2b09 cmp r3, #9 8009d60: d103 bne.n 8009d6a 8009d62: 4920 ldr r1, [pc, #128] @ (8009de4 ) 8009d64: 2007 movs r0, #7 8009d66: f000 fb83 bl 800a470 if(connectorState == Finished) log_printf(LOG_INFO, "Connector: Finished\n"); 8009d6a: 4b13 ldr r3, [pc, #76] @ (8009db8 ) 8009d6c: 781b ldrb r3, [r3, #0] 8009d6e: 2b0a cmp r3, #10 8009d70: d103 bne.n 8009d7a 8009d72: 491d ldr r1, [pc, #116] @ (8009de8 ) 8009d74: 2007 movs r0, #7 8009d76: f000 fb7b bl 800a470 if(connectorState == FinishedEVSE) log_printf(LOG_INFO, "Connector: FinishedEVSE\n"); 8009d7a: 4b0f ldr r3, [pc, #60] @ (8009db8 ) 8009d7c: 781b ldrb r3, [r3, #0] 8009d7e: 2b0b cmp r3, #11 8009d80: d103 bne.n 8009d8a 8009d82: 491a ldr r1, [pc, #104] @ (8009dec ) 8009d84: 2007 movs r0, #7 8009d86: f000 fb73 bl 800a470 if(connectorState == FinishedEV) log_printf(LOG_INFO, "Connector: FinishedEV\n"); 8009d8a: 4b0b ldr r3, [pc, #44] @ (8009db8 ) 8009d8c: 781b ldrb r3, [r3, #0] 8009d8e: 2b0c cmp r3, #12 8009d90: d103 bne.n 8009d9a 8009d92: 4917 ldr r1, [pc, #92] @ (8009df0 ) 8009d94: 2007 movs r0, #7 8009d96: f000 fb6b bl 800a470 if(connectorState == Replugging) log_printf(LOG_INFO, "Connector: Replugging\n"); 8009d9a: 4b07 ldr r3, [pc, #28] @ (8009db8 ) 8009d9c: 781b ldrb r3, [r3, #0] 8009d9e: 2b0d cmp r3, #13 8009da0: d103 bne.n 8009daa 8009da2: 4914 ldr r1, [pc, #80] @ (8009df4 ) 8009da4: 2007 movs r0, #7 8009da6: f000 fb63 bl 800a470 CONN.connState = state; 8009daa: 4a04 ldr r2, [pc, #16] @ (8009dbc ) 8009dac: 79fb ldrb r3, [r7, #7] 8009dae: 7053 strb r3, [r2, #1] } 8009db0: 3708 adds r7, #8 8009db2: 46bd mov sp, r7 8009db4: bd80 pop {r7, pc} 8009db6: bf00 nop 8009db8: 200001f3 .word 0x200001f3 8009dbc: 200001d4 .word 0x200001d4 8009dc0: 08013f90 .word 0x08013f90 8009dc4: 08013fa4 .word 0x08013fa4 8009dc8: 08013fbc .word 0x08013fbc 8009dcc: 08013fd4 .word 0x08013fd4 8009dd0: 08013fec .word 0x08013fec 8009dd4: 08014008 .word 0x08014008 8009dd8: 08014028 .word 0x08014028 8009ddc: 08014048 .word 0x08014048 8009de0: 08014068 .word 0x08014068 8009de4: 08014080 .word 0x08014080 8009de8: 08014098 .word 0x08014098 8009dec: 080140b0 .word 0x080140b0 8009df0: 080140cc .word 0x080140cc 8009df4: 080140e4 .word 0x080140e4 08009df8 : CP_State_t fake_cp_state = EV_STATE_ACQUIRING; static CP_State_t cp_stable_state = EV_STATE_ACQUIRING; static CP_State_t cp_candidate_state = EV_STATE_ACQUIRING; static uint32_t cp_candidate_since_ms = 0; static uint32_t CP_ReadAdcChannel(uint32_t ch) { 8009df8: b580 push {r7, lr} 8009dfa: b084 sub sp, #16 8009dfc: af00 add r7, sp, #0 8009dfe: 6078 str r0, [r7, #4] uint32_t adc = 0; 8009e00: 2300 movs r3, #0 8009e02: 60fb str r3, [r7, #12] ADC_Select_Channel(ch); 8009e04: 6878 ldr r0, [r7, #4] 8009e06: f7ff fd25 bl 8009854 HAL_ADC_Start(&hadc1); 8009e0a: 4809 ldr r0, [pc, #36] @ (8009e30 ) 8009e0c: f003 fe68 bl 800dae0 HAL_ADC_PollForConversion(&hadc1, 10); 8009e10: 210a movs r1, #10 8009e12: 4807 ldr r0, [pc, #28] @ (8009e30 ) 8009e14: f003 ff3e bl 800dc94 adc = HAL_ADC_GetValue(&hadc1); 8009e18: 4805 ldr r0, [pc, #20] @ (8009e30 ) 8009e1a: f004 f841 bl 800dea0 8009e1e: 60f8 str r0, [r7, #12] HAL_ADC_Stop(&hadc1); 8009e20: 4803 ldr r0, [pc, #12] @ (8009e30 ) 8009e22: f003 ff0b bl 800dc3c return adc; 8009e26: 68fb ldr r3, [r7, #12] } 8009e28: 4618 mov r0, r3 8009e2a: 3710 adds r7, #16 8009e2c: 46bd mov sp, r7 8009e2e: bd80 pop {r7, pc} 8009e30: 200000f4 .word 0x200000f4 08009e34 : #define VREFINT_CAL_ADDR ((uint16_t*)0x1FFFF7BA) // для STM32F1! static uint8_t CP_IsInRange(int32_t v, int32_t lo, int32_t hi) { 8009e34: b480 push {r7} 8009e36: b085 sub sp, #20 8009e38: af00 add r7, sp, #0 8009e3a: 60f8 str r0, [r7, #12] 8009e3c: 60b9 str r1, [r7, #8] 8009e3e: 607a str r2, [r7, #4] return (v >= lo && v <= hi) ? 1u : 0u; 8009e40: 68fa ldr r2, [r7, #12] 8009e42: 68bb ldr r3, [r7, #8] 8009e44: 429a cmp r2, r3 8009e46: db05 blt.n 8009e54 8009e48: 68fa ldr r2, [r7, #12] 8009e4a: 687b ldr r3, [r7, #4] 8009e4c: 429a cmp r2, r3 8009e4e: dc01 bgt.n 8009e54 8009e50: 2301 movs r3, #1 8009e52: e000 b.n 8009e56 8009e54: 2300 movs r3, #0 } 8009e56: 4618 mov r0, r3 8009e58: 3714 adds r7, #20 8009e5a: 46bd mov sp, r7 8009e5c: bc80 pop {r7} 8009e5e: 4770 bx lr 08009e60 : static int32_t CP_ApplyEma(int32_t raw_mv) { 8009e60: b480 push {r7} 8009e62: b083 sub sp, #12 8009e64: af00 add r7, sp, #0 8009e66: 6078 str r0, [r7, #4] if (!cp_filter_initialized) { 8009e68: 4b12 ldr r3, [pc, #72] @ (8009eb4 ) 8009e6a: 781b ldrb r3, [r3, #0] 8009e6c: 2b00 cmp r3, #0 8009e6e: d108 bne.n 8009e82 cp_voltage_filt_mv = raw_mv; 8009e70: 4a11 ldr r2, [pc, #68] @ (8009eb8 ) 8009e72: 687b ldr r3, [r7, #4] 8009e74: 6013 str r3, [r2, #0] cp_filter_initialized = 1; 8009e76: 4b0f ldr r3, [pc, #60] @ (8009eb4 ) 8009e78: 2201 movs r2, #1 8009e7a: 701a strb r2, [r3, #0] return cp_voltage_filt_mv; 8009e7c: 4b0e ldr r3, [pc, #56] @ (8009eb8 ) 8009e7e: 681b ldr r3, [r3, #0] 8009e80: e012 b.n 8009ea8 } cp_voltage_filt_mv += ((raw_mv - cp_voltage_filt_mv) * CP_EMA_ALPHA_Q8) / 256; 8009e82: 4b0d ldr r3, [pc, #52] @ (8009eb8 ) 8009e84: 681b ldr r3, [r3, #0] 8009e86: 687a ldr r2, [r7, #4] 8009e88: 1ad3 subs r3, r2, r3 8009e8a: 2226 movs r2, #38 @ 0x26 8009e8c: fb02 f303 mul.w r3, r2, r3 8009e90: 2b00 cmp r3, #0 8009e92: da00 bge.n 8009e96 8009e94: 33ff adds r3, #255 @ 0xff 8009e96: 121b asrs r3, r3, #8 8009e98: 461a mov r2, r3 8009e9a: 4b07 ldr r3, [pc, #28] @ (8009eb8 ) 8009e9c: 681b ldr r3, [r3, #0] 8009e9e: 4413 add r3, r2 8009ea0: 4a05 ldr r2, [pc, #20] @ (8009eb8 ) 8009ea2: 6013 str r3, [r2, #0] return cp_voltage_filt_mv; 8009ea4: 4b04 ldr r3, [pc, #16] @ (8009eb8 ) 8009ea6: 681b ldr r3, [r3, #0] } 8009ea8: 4618 mov r0, r3 8009eaa: 370c adds r7, #12 8009eac: 46bd mov sp, r7 8009eae: bc80 pop {r7} 8009eb0: 4770 bx lr 8009eb2: bf00 nop 8009eb4: 20000200 .word 0x20000200 8009eb8: 200001fc .word 0x200001fc 08009ebc : static CP_State_t CP_ClassifyWithHysteresis(int32_t v, CP_State_t prev) { 8009ebc: b580 push {r7, lr} 8009ebe: b082 sub sp, #8 8009ec0: af00 add r7, sp, #0 8009ec2: 6078 str r0, [r7, #4] 8009ec4: 460b mov r3, r1 8009ec6: 70fb strb r3, [r7, #3] switch (prev) { 8009ec8: 78fb ldrb r3, [r7, #3] 8009eca: 2b05 cmp r3, #5 8009ecc: d84a bhi.n 8009f64 8009ece: a201 add r2, pc, #4 @ (adr r2, 8009ed4 ) 8009ed0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009ed4: 08009eed .word 0x08009eed 8009ed8: 08009efb .word 0x08009efb 8009edc: 08009f13 .word 0x08009f13 8009ee0: 08009f2b .word 0x08009f2b 8009ee4: 08009f43 .word 0x08009f43 8009ee8: 08009f59 .word 0x08009f59 case EV_STATE_A_IDLE: if (v >= CP_A_EXIT_MV) return EV_STATE_A_IDLE; 8009eec: 687b ldr r3, [r7, #4] 8009eee: f242 720f movw r2, #9999 @ 0x270f 8009ef2: 4293 cmp r3, r2 8009ef4: dd38 ble.n 8009f68 8009ef6: 2300 movs r3, #0 8009ef8: e07e b.n 8009ff8 break; case EV_STATE_B_CONN_PREP: if (CP_IsInRange(v, CP_B_EXIT_LOW_MV, CP_B_EXIT_HIGH_MV)) return EV_STATE_B_CONN_PREP; 8009efa: f642 1204 movw r2, #10500 @ 0x2904 8009efe: f641 514c movw r1, #7500 @ 0x1d4c 8009f02: 6878 ldr r0, [r7, #4] 8009f04: f7ff ff96 bl 8009e34 8009f08: 4603 mov r3, r0 8009f0a: 2b00 cmp r3, #0 8009f0c: d02e beq.n 8009f6c 8009f0e: 2301 movs r3, #1 8009f10: e072 b.n 8009ff8 break; case EV_STATE_C_CONN_ACTIVE: if (CP_IsInRange(v, CP_C_EXIT_LOW_MV, CP_C_EXIT_HIGH_MV)) return EV_STATE_C_CONN_ACTIVE; 8009f12: f641 524c movw r2, #7500 @ 0x1d4c 8009f16: f241 1194 movw r1, #4500 @ 0x1194 8009f1a: 6878 ldr r0, [r7, #4] 8009f1c: f7ff ff8a bl 8009e34 8009f20: 4603 mov r3, r0 8009f22: 2b00 cmp r3, #0 8009f24: d024 beq.n 8009f70 8009f26: 2302 movs r3, #2 8009f28: e066 b.n 8009ff8 break; case EV_STATE_D_CONN_ACT_VENT: if (CP_IsInRange(v, CP_D_EXIT_LOW_MV, CP_D_EXIT_HIGH_MV)) return EV_STATE_D_CONN_ACT_VENT; 8009f2a: f241 1294 movw r2, #4500 @ 0x1194 8009f2e: f240 51dc movw r1, #1500 @ 0x5dc 8009f32: 6878 ldr r0, [r7, #4] 8009f34: f7ff ff7e bl 8009e34 8009f38: 4603 mov r3, r0 8009f3a: 2b00 cmp r3, #0 8009f3c: d01a beq.n 8009f74 8009f3e: 2303 movs r3, #3 8009f40: e05a b.n 8009ff8 break; case EV_STATE_E_NO_POWER: if (CP_IsInRange(v, CP_E_EXIT_LOW_MV, CP_E_EXIT_HIGH_MV)) return EV_STATE_E_NO_POWER; 8009f42: f640 12c4 movw r2, #2500 @ 0x9c4 8009f46: 492e ldr r1, [pc, #184] @ (800a000 ) 8009f48: 6878 ldr r0, [r7, #4] 8009f4a: f7ff ff73 bl 8009e34 8009f4e: 4603 mov r3, r0 8009f50: 2b00 cmp r3, #0 8009f52: d011 beq.n 8009f78 8009f54: 2304 movs r3, #4 8009f56: e04f b.n 8009ff8 break; case EV_STATE_F_ERROR: if (v <= CP_F_EXIT_MV) return EV_STATE_F_ERROR; 8009f58: 687b ldr r3, [r7, #4] 8009f5a: 4a2a ldr r2, [pc, #168] @ (800a004 ) 8009f5c: 4293 cmp r3, r2 8009f5e: da0d bge.n 8009f7c 8009f60: 2305 movs r3, #5 8009f62: e049 b.n 8009ff8 break; default: break; 8009f64: bf00 nop 8009f66: e00a b.n 8009f7e break; 8009f68: bf00 nop 8009f6a: e008 b.n 8009f7e break; 8009f6c: bf00 nop 8009f6e: e006 b.n 8009f7e break; 8009f70: bf00 nop 8009f72: e004 b.n 8009f7e break; 8009f74: bf00 nop 8009f76: e002 b.n 8009f7e break; 8009f78: bf00 nop 8009f7a: e000 b.n 8009f7e break; 8009f7c: bf00 nop } if (v >= CP_A_ENTER_MV) return EV_STATE_A_IDLE; 8009f7e: 687b ldr r3, [r7, #4] 8009f80: f642 22f7 movw r2, #10999 @ 0x2af7 8009f84: 4293 cmp r3, r2 8009f86: dd01 ble.n 8009f8c 8009f88: 2300 movs r3, #0 8009f8a: e035 b.n 8009ff8 if (CP_IsInRange(v, CP_B_ENTER_LOW_MV, CP_B_ENTER_HIGH_MV)) return EV_STATE_B_CONN_PREP; 8009f8c: f242 7210 movw r2, #10000 @ 0x2710 8009f90: f44f 51fa mov.w r1, #8000 @ 0x1f40 8009f94: 6878 ldr r0, [r7, #4] 8009f96: f7ff ff4d bl 8009e34 8009f9a: 4603 mov r3, r0 8009f9c: 2b00 cmp r3, #0 8009f9e: d001 beq.n 8009fa4 8009fa0: 2301 movs r3, #1 8009fa2: e029 b.n 8009ff8 if (CP_IsInRange(v, CP_C_ENTER_LOW_MV, CP_C_ENTER_HIGH_MV)) return EV_STATE_C_CONN_ACTIVE; 8009fa4: f641 3258 movw r2, #7000 @ 0x1b58 8009fa8: f241 3188 movw r1, #5000 @ 0x1388 8009fac: 6878 ldr r0, [r7, #4] 8009fae: f7ff ff41 bl 8009e34 8009fb2: 4603 mov r3, r0 8009fb4: 2b00 cmp r3, #0 8009fb6: d001 beq.n 8009fbc 8009fb8: 2302 movs r3, #2 8009fba: e01d b.n 8009ff8 if (CP_IsInRange(v, CP_D_ENTER_LOW_MV, CP_D_ENTER_HIGH_MV)) return EV_STATE_D_CONN_ACT_VENT; 8009fbc: f44f 627a mov.w r2, #4000 @ 0xfa0 8009fc0: f44f 61fa mov.w r1, #2000 @ 0x7d0 8009fc4: 6878 ldr r0, [r7, #4] 8009fc6: f7ff ff35 bl 8009e34 8009fca: 4603 mov r3, r0 8009fcc: 2b00 cmp r3, #0 8009fce: d001 beq.n 8009fd4 8009fd0: 2303 movs r3, #3 8009fd2: e011 b.n 8009ff8 if (CP_IsInRange(v, CP_E_ENTER_LOW_MV, CP_E_ENTER_HIGH_MV)) return EV_STATE_E_NO_POWER; 8009fd4: f44f 62fa mov.w r2, #2000 @ 0x7d0 8009fd8: 490b ldr r1, [pc, #44] @ (800a008 ) 8009fda: 6878 ldr r0, [r7, #4] 8009fdc: f7ff ff2a bl 8009e34 8009fe0: 4603 mov r3, r0 8009fe2: 2b00 cmp r3, #0 8009fe4: d001 beq.n 8009fea 8009fe6: 2304 movs r3, #4 8009fe8: e006 b.n 8009ff8 if (v <= CP_F_ENTER_MV) return EV_STATE_F_ERROR; 8009fea: 687b ldr r3, [r7, #4] 8009fec: 4a07 ldr r2, [pc, #28] @ (800a00c ) 8009fee: 4293 cmp r3, r2 8009ff0: da01 bge.n 8009ff6 8009ff2: 2305 movs r3, #5 8009ff4: e000 b.n 8009ff8 return EV_STATE_ACQUIRING; 8009ff6: 2306 movs r3, #6 } 8009ff8: 4618 mov r0, r3 8009ffa: 3708 adds r7, #8 8009ffc: 46bd mov sp, r7 8009ffe: bd80 pop {r7, pc} 800a000: fffffa24 .word 0xfffffa24 800a004: ffffd6fd .word 0xffffd6fd 800a008: fffffc18 .word 0xfffffc18 800a00c: ffffd315 .word 0xffffd315 0800a010 : static uint32_t CP_GetDebounceMs(CP_State_t next_state) { 800a010: b480 push {r7} 800a012: b083 sub sp, #12 800a014: af00 add r7, sp, #0 800a016: 4603 mov r3, r0 800a018: 71fb strb r3, [r7, #7] if (next_state == EV_STATE_F_ERROR) { 800a01a: 79fb ldrb r3, [r7, #7] 800a01c: 2b05 cmp r3, #5 800a01e: d107 bne.n 800a030 if (cp_duty <= CP_LOW_DUTY_THRESHOLD_PERCENT) { 800a020: 4b06 ldr r3, [pc, #24] @ (800a03c ) 800a022: 781b ldrb r3, [r3, #0] 800a024: 2b0a cmp r3, #10 800a026: d801 bhi.n 800a02c return CP_DEBOUNCE_MS_F_LOW_DUTY; 800a028: 2364 movs r3, #100 @ 0x64 800a02a: e002 b.n 800a032 } return CP_DEBOUNCE_MS_F; 800a02c: 233c movs r3, #60 @ 0x3c 800a02e: e000 b.n 800a032 } return CP_DEBOUNCE_MS_DEFAULT; 800a030: 230a movs r3, #10 } 800a032: 4618 mov r0, r3 800a034: 370c adds r7, #12 800a036: 46bd mov sp, r7 800a038: bc80 pop {r7} 800a03a: 4770 bx lr 800a03c: 20000201 .word 0x20000201 0800a040 : static int32_t CP_ReadVoltageMv(void) { 800a040: b580 push {r7, lr} 800a042: b084 sub sp, #16 800a044: af00 add r7, sp, #0 uint32_t adc = 0; 800a046: 2300 movs r3, #0 800a048: 60fb str r3, [r7, #12] int32_t v_adc_mv = 0; 800a04a: 2300 movs r3, #0 800a04c: 60bb str r3, [r7, #8] int32_t v_out_mv = 0; 800a04e: 2300 movs r3, #0 800a050: 607b str r3, [r7, #4] adc = CP_ReadAdcChannel((uint32_t)4u); 800a052: 2004 movs r0, #4 800a054: f7ff fed0 bl 8009df8 800a058: 60f8 str r0, [r7, #12] v_adc_mv = (int32_t)((adc * 3300u) / 4095u); 800a05a: 68fb ldr r3, [r7, #12] 800a05c: f640 42e4 movw r2, #3300 @ 0xce4 800a060: fb03 f202 mul.w r2, r3, r2 800a064: 4b0d ldr r3, [pc, #52] @ (800a09c ) 800a066: fba3 1302 umull r1, r3, r3, r2 800a06a: 1ad2 subs r2, r2, r3 800a06c: 0852 lsrs r2, r2, #1 800a06e: 4413 add r3, r2 800a070: 0adb lsrs r3, r3, #11 800a072: 60bb str r3, [r7, #8] v_out_mv = ((v_adc_mv - 1723) * 1000) / 130; 800a074: 68bb ldr r3, [r7, #8] 800a076: f2a3 63bb subw r3, r3, #1723 @ 0x6bb 800a07a: f44f 727a mov.w r2, #1000 @ 0x3e8 800a07e: fb02 f303 mul.w r3, r2, r3 800a082: 4a07 ldr r2, [pc, #28] @ (800a0a0 ) 800a084: fb82 1203 smull r1, r2, r2, r3 800a088: 1192 asrs r2, r2, #6 800a08a: 17db asrs r3, r3, #31 800a08c: 1ad3 subs r3, r2, r3 800a08e: 607b str r3, [r7, #4] return v_out_mv; 800a090: 687b ldr r3, [r7, #4] } 800a092: 4618 mov r0, r3 800a094: 3710 adds r7, #16 800a096: 46bd mov sp, r7 800a098: bd80 pop {r7, pc} 800a09a: bf00 nop 800a09c: 00100101 .word 0x00100101 800a0a0: 7e07e07f .word 0x7e07e07f 0800a0a4 : void CP_Init(void) { 800a0a4: b580 push {r7, lr} 800a0a6: af00 add r7, sp, #0 /* TIM3_CH2 (PA7): set 1kHz PWM like original CCS logic. */ htim3.Instance->PSC = 160 - 1; 800a0a8: 4b0e ldr r3, [pc, #56] @ (800a0e4 ) 800a0aa: 681b ldr r3, [r3, #0] 800a0ac: 229f movs r2, #159 @ 0x9f 800a0ae: 629a str r2, [r3, #40] @ 0x28 htim3.Instance->ARR = MAX_DUTY - 1; 800a0b0: 4b0c ldr r3, [pc, #48] @ (800a0e4 ) 800a0b2: 681b ldr r3, [r3, #0] 800a0b4: f240 12c1 movw r2, #449 @ 0x1c1 800a0b8: 62da str r2, [r3, #44] @ 0x2c #if DUTY_INVERT == 0 htim3.Instance->CCR2 = MAX_DUTY; 800a0ba: 4b0a ldr r3, [pc, #40] @ (800a0e4 ) 800a0bc: 681b ldr r3, [r3, #0] 800a0be: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a0c2: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = MAX_DUTY + 5; 800a0c4: 4b07 ldr r3, [pc, #28] @ (800a0e4 ) 800a0c6: 681b ldr r3, [r3, #0] 800a0c8: f240 12c7 movw r2, #455 @ 0x1c7 800a0cc: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = 0; htim3.Instance->CCR1 = 0; #endif HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_2); 800a0ce: 2104 movs r1, #4 800a0d0: 4804 ldr r0, [pc, #16] @ (800a0e4 ) 800a0d2: f006 ff3b bl 8010f4c HAL_TIM_OC_Start_IT(&htim3, TIM_CHANNEL_1); 800a0d6: 2100 movs r1, #0 800a0d8: 4802 ldr r0, [pc, #8] @ (800a0e4 ) 800a0da: f006 fde9 bl 8010cb0 } 800a0de: bf00 nop 800a0e0: bd80 pop {r7, pc} 800a0e2: bf00 nop 800a0e4: 20000ec0 .word 0x20000ec0 0800a0e8 : void CP_SetDuty(uint8_t percentage) { 800a0e8: b480 push {r7} 800a0ea: b085 sub sp, #20 800a0ec: af00 add r7, sp, #0 800a0ee: 4603 mov r3, r0 800a0f0: 71fb strb r3, [r7, #7] uint32_t pwmduty = MAX_DUTY * percentage / 100; 800a0f2: 79fb ldrb r3, [r7, #7] 800a0f4: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a0f8: fb02 f303 mul.w r3, r2, r3 800a0fc: 4a0b ldr r2, [pc, #44] @ (800a12c ) 800a0fe: fb82 1203 smull r1, r2, r2, r3 800a102: 1152 asrs r2, r2, #5 800a104: 17db asrs r3, r3, #31 800a106: 1ad3 subs r3, r2, r3 800a108: 60fb str r3, [r7, #12] cp_duty = percentage; 800a10a: 4a09 ldr r2, [pc, #36] @ (800a130 ) 800a10c: 79fb ldrb r3, [r7, #7] 800a10e: 7013 strb r3, [r2, #0] #if DUTY_INVERT == 0 htim3.Instance->CCR2 = pwmduty; 800a110: 4b08 ldr r3, [pc, #32] @ (800a134 ) 800a112: 681b ldr r3, [r3, #0] 800a114: 68fa ldr r2, [r7, #12] 800a116: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = 0 + 1; 800a118: 4b06 ldr r3, [pc, #24] @ (800a134 ) 800a11a: 681b ldr r3, [r3, #0] 800a11c: 2201 movs r2, #1 800a11e: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = MAX_DUTY - pwmduty; htim3.Instance->CCR1 = MAX_DUTY - pwmduty + 5; #endif } 800a120: bf00 nop 800a122: 3714 adds r7, #20 800a124: 46bd mov sp, r7 800a126: bc80 pop {r7} 800a128: 4770 bx lr 800a12a: bf00 nop 800a12c: 51eb851f .word 0x51eb851f 800a130: 20000201 .word 0x20000201 800a134: 20000ec0 .word 0x20000ec0 0800a138 : uint8_t CP_GetDuty(void) { 800a138: b480 push {r7} 800a13a: af00 add r7, sp, #0 return cp_duty; 800a13c: 4b02 ldr r3, [pc, #8] @ (800a148 ) 800a13e: 781b ldrb r3, [r3, #0] } 800a140: 4618 mov r0, r3 800a142: 46bd mov sp, r7 800a144: bc80 pop {r7} 800a146: 4770 bx lr 800a148: 20000201 .word 0x20000201 0800a14c : int32_t CP_GetVoltage(void) { return cp_voltage_mv; } CP_State_t CP_GetState(void) { 800a14c: b590 push {r4, r7, lr} 800a14e: b085 sub sp, #20 800a150: af00 add r7, sp, #0 int32_t voltage_real = cp_voltage_filt_mv; 800a152: 4b22 ldr r3, [pc, #136] @ (800a1dc ) 800a154: 681b ldr r3, [r3, #0] 800a156: 60fb str r3, [r7, #12] uint32_t now = HAL_GetTick(); 800a158: f003 fbbc bl 800d8d4 800a15c: 60b8 str r0, [r7, #8] if(fake_cp_state != EV_STATE_ACQUIRING) { 800a15e: 4b20 ldr r3, [pc, #128] @ (800a1e0 ) 800a160: 781b ldrb r3, [r3, #0] 800a162: 2b06 cmp r3, #6 800a164: d002 beq.n 800a16c return fake_cp_state; 800a166: 4b1e ldr r3, [pc, #120] @ (800a1e0 ) 800a168: 781b ldrb r3, [r3, #0] 800a16a: e032 b.n 800a1d2 } CP_State_t instant_state = CP_ClassifyWithHysteresis(voltage_real, cp_stable_state); 800a16c: 4b1d ldr r3, [pc, #116] @ (800a1e4 ) 800a16e: 781b ldrb r3, [r3, #0] 800a170: 4619 mov r1, r3 800a172: 68f8 ldr r0, [r7, #12] 800a174: f7ff fea2 bl 8009ebc 800a178: 4603 mov r3, r0 800a17a: 71fb strb r3, [r7, #7] if (instant_state == cp_stable_state) { 800a17c: 4b19 ldr r3, [pc, #100] @ (800a1e4 ) 800a17e: 781b ldrb r3, [r3, #0] 800a180: 79fa ldrb r2, [r7, #7] 800a182: 429a cmp r2, r3 800a184: d107 bne.n 800a196 cp_candidate_state = cp_stable_state; 800a186: 4b17 ldr r3, [pc, #92] @ (800a1e4 ) 800a188: 781a ldrb r2, [r3, #0] 800a18a: 4b17 ldr r3, [pc, #92] @ (800a1e8 ) 800a18c: 701a strb r2, [r3, #0] cp_candidate_since_ms = now; 800a18e: 4a17 ldr r2, [pc, #92] @ (800a1ec ) 800a190: 68bb ldr r3, [r7, #8] 800a192: 6013 str r3, [r2, #0] 800a194: e01b b.n 800a1ce } else { if (cp_candidate_state != instant_state) { 800a196: 4b14 ldr r3, [pc, #80] @ (800a1e8 ) 800a198: 781b ldrb r3, [r3, #0] 800a19a: 79fa ldrb r2, [r7, #7] 800a19c: 429a cmp r2, r3 800a19e: d006 beq.n 800a1ae cp_candidate_state = instant_state; 800a1a0: 4a11 ldr r2, [pc, #68] @ (800a1e8 ) 800a1a2: 79fb ldrb r3, [r7, #7] 800a1a4: 7013 strb r3, [r2, #0] cp_candidate_since_ms = now; 800a1a6: 4a11 ldr r2, [pc, #68] @ (800a1ec ) 800a1a8: 68bb ldr r3, [r7, #8] 800a1aa: 6013 str r3, [r2, #0] 800a1ac: e00f b.n 800a1ce } else if ((now - cp_candidate_since_ms) >= CP_GetDebounceMs(cp_candidate_state)) { 800a1ae: 4b0f ldr r3, [pc, #60] @ (800a1ec ) 800a1b0: 681b ldr r3, [r3, #0] 800a1b2: 68ba ldr r2, [r7, #8] 800a1b4: 1ad4 subs r4, r2, r3 800a1b6: 4b0c ldr r3, [pc, #48] @ (800a1e8 ) 800a1b8: 781b ldrb r3, [r3, #0] 800a1ba: 4618 mov r0, r3 800a1bc: f7ff ff28 bl 800a010 800a1c0: 4603 mov r3, r0 800a1c2: 429c cmp r4, r3 800a1c4: d303 bcc.n 800a1ce cp_stable_state = cp_candidate_state; 800a1c6: 4b08 ldr r3, [pc, #32] @ (800a1e8 ) 800a1c8: 781a ldrb r2, [r3, #0] 800a1ca: 4b06 ldr r3, [pc, #24] @ (800a1e4 ) 800a1cc: 701a strb r2, [r3, #0] } } return cp_stable_state; 800a1ce: 4b05 ldr r3, [pc, #20] @ (800a1e4 ) 800a1d0: 781b ldrb r3, [r3, #0] } 800a1d2: 4618 mov r0, r3 800a1d4: 3714 adds r7, #20 800a1d6: 46bd mov sp, r7 800a1d8: bd90 pop {r4, r7, pc} 800a1da: bf00 nop 800a1dc: 200001fc .word 0x200001fc 800a1e0: 20000004 .word 0x20000004 800a1e4: 20000005 .word 0x20000005 800a1e8: 20000006 .word 0x20000006 800a1ec: 20000204 .word 0x20000204 0800a1f0 : void CP_Loop(void) { (void)CP_GetState(); } void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 800a1f0: b580 push {r7, lr} 800a1f2: b082 sub sp, #8 800a1f4: af00 add r7, sp, #0 800a1f6: 6078 str r0, [r7, #4] if (htim->Instance == TIM3 && htim->Channel == HAL_TIM_ACTIVE_CHANNEL_1) { 800a1f8: 687b ldr r3, [r7, #4] 800a1fa: 681b ldr r3, [r3, #0] 800a1fc: 4a0e ldr r2, [pc, #56] @ (800a238 ) 800a1fe: 4293 cmp r3, r2 800a200: d116 bne.n 800a230 800a202: 687b ldr r3, [r7, #4] 800a204: 7f1b ldrb r3, [r3, #28] 800a206: 2b01 cmp r3, #1 800a208: d112 bne.n 800a230 if (ADC_TryLock() == 0u) { 800a20a: f7ff fb3f bl 800988c 800a20e: 4603 mov r3, r0 800a210: 2b00 cmp r3, #0 800a212: d00c beq.n 800a22e return; } cp_voltage_mv = CP_ReadVoltageMv(); 800a214: f7ff ff14 bl 800a040 800a218: 4603 mov r3, r0 800a21a: 4a08 ldr r2, [pc, #32] @ (800a23c ) 800a21c: 6013 str r3, [r2, #0] (void)CP_ApplyEma(cp_voltage_mv); 800a21e: 4b07 ldr r3, [pc, #28] @ (800a23c ) 800a220: 681b ldr r3, [r3, #0] 800a222: 4618 mov r0, r3 800a224: f7ff fe1c bl 8009e60 ADC_Unlock(); 800a228: f7ff fb62 bl 80098f0 800a22c: e000 b.n 800a230 return; 800a22e: bf00 nop } } 800a230: 3708 adds r7, #8 800a232: 46bd mov sp, r7 800a234: bd80 pop {r7, pc} 800a236: bf00 nop 800a238: 40000400 .word 0x40000400 800a23c: 200001f8 .word 0x200001f8 0800a240 : CRC_HandleTypeDef hcrc; /* CRC init function */ void MX_CRC_Init(void) { 800a240: b580 push {r7, lr} 800a242: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 800a244: 4b06 ldr r3, [pc, #24] @ (800a260 ) 800a246: 4a07 ldr r2, [pc, #28] @ (800a264 ) 800a248: 601a str r2, [r3, #0] if (HAL_CRC_Init(&hcrc) != HAL_OK) 800a24a: 4805 ldr r0, [pc, #20] @ (800a260 ) 800a24c: f005 f859 bl 800f302 800a250: 4603 mov r3, r0 800a252: 2b00 cmp r3, #0 800a254: d001 beq.n 800a25a { Error_Handler(); 800a256: f000 fbcb bl 800a9f0 } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 800a25a: bf00 nop 800a25c: bd80 pop {r7, pc} 800a25e: bf00 nop 800a260: 20000208 .word 0x20000208 800a264: 40023000 .word 0x40023000 0800a268 : void HAL_CRC_MspInit(CRC_HandleTypeDef* crcHandle) { 800a268: b480 push {r7} 800a26a: b085 sub sp, #20 800a26c: af00 add r7, sp, #0 800a26e: 6078 str r0, [r7, #4] if(crcHandle->Instance==CRC) 800a270: 687b ldr r3, [r7, #4] 800a272: 681b ldr r3, [r3, #0] 800a274: 4a09 ldr r2, [pc, #36] @ (800a29c ) 800a276: 4293 cmp r3, r2 800a278: d10b bne.n 800a292 { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* CRC clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 800a27a: 4b09 ldr r3, [pc, #36] @ (800a2a0 ) 800a27c: 695b ldr r3, [r3, #20] 800a27e: 4a08 ldr r2, [pc, #32] @ (800a2a0 ) 800a280: f043 0340 orr.w r3, r3, #64 @ 0x40 800a284: 6153 str r3, [r2, #20] 800a286: 4b06 ldr r3, [pc, #24] @ (800a2a0 ) 800a288: 695b ldr r3, [r3, #20] 800a28a: f003 0340 and.w r3, r3, #64 @ 0x40 800a28e: 60fb str r3, [r7, #12] 800a290: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 800a292: bf00 nop 800a294: 3714 adds r7, #20 800a296: 46bd mov sp, r7 800a298: bc80 pop {r7} 800a29a: 4770 bx lr 800a29c: 40023000 .word 0x40023000 800a2a0: 40021000 .word 0x40021000 0800a2a4 <_write>: #if defined(__GNUC__) int _write(int fd, char * ptr, int len) { 800a2a4: b580 push {r7, lr} 800a2a6: b084 sub sp, #16 800a2a8: af00 add r7, sp, #0 800a2aa: 60f8 str r0, [r7, #12] 800a2ac: 60b9 str r1, [r7, #8] 800a2ae: 607a str r2, [r7, #4] debug_buffer_add((const uint8_t*)ptr, len); 800a2b0: 687b ldr r3, [r7, #4] 800a2b2: b29b uxth r3, r3 800a2b4: 4619 mov r1, r3 800a2b6: 68b8 ldr r0, [r7, #8] 800a2b8: f000 f806 bl 800a2c8 return len; 800a2bc: 687b ldr r3, [r7, #4] } 800a2be: 4618 mov r0, r3 800a2c0: 3710 adds r7, #16 800a2c2: 46bd mov sp, r7 800a2c4: bd80 pop {r7, pc} ... 0800a2c8 : #endif // Добавляет данные в кольцевой буфер void debug_buffer_add(const uint8_t* data, uint16_t len) { 800a2c8: b480 push {r7} 800a2ca: b085 sub sp, #20 800a2cc: af00 add r7, sp, #0 800a2ce: 6078 str r0, [r7, #4] 800a2d0: 460b mov r3, r1 800a2d2: 807b strh r3, [r7, #2] __ASM volatile ("cpsid i" : : : "memory"); 800a2d4: b672 cpsid i } 800a2d6: bf00 nop __disable_irq(); for (uint16_t i = 0; i < len; i++) { 800a2d8: 2300 movs r3, #0 800a2da: 81fb strh r3, [r7, #14] 800a2dc: e045 b.n 800a36a // Если буфер полон, перезаписываем старые данные if (debug_buffer.count >= DEBUG_BUFFER_SIZE) { 800a2de: 4b28 ldr r3, [pc, #160] @ (800a380 ) 800a2e0: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a2e4: b29b uxth r3, r3 800a2e6: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800a2ea: d318 bcc.n 800a31e debug_buffer.read_index = (debug_buffer.read_index + 1) % DEBUG_BUFFER_SIZE; 800a2ec: 4b24 ldr r3, [pc, #144] @ (800a380 ) 800a2ee: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a2f2: b29b uxth r3, r3 800a2f4: 3301 adds r3, #1 800a2f6: 425a negs r2, r3 800a2f8: f3c3 0309 ubfx r3, r3, #0, #10 800a2fc: f3c2 0209 ubfx r2, r2, #0, #10 800a300: bf58 it pl 800a302: 4253 negpl r3, r2 800a304: b29a uxth r2, r3 800a306: 4b1e ldr r3, [pc, #120] @ (800a380 ) 800a308: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count--; 800a30c: 4b1c ldr r3, [pc, #112] @ (800a380 ) 800a30e: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a312: b29b uxth r3, r3 800a314: 3b01 subs r3, #1 800a316: b29a uxth r2, r3 800a318: 4b19 ldr r3, [pc, #100] @ (800a380 ) 800a31a: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 } debug_buffer.buffer[debug_buffer.write_index] = data[i]; 800a31e: 89fb ldrh r3, [r7, #14] 800a320: 687a ldr r2, [r7, #4] 800a322: 4413 add r3, r2 800a324: 4a16 ldr r2, [pc, #88] @ (800a380 ) 800a326: f8b2 2400 ldrh.w r2, [r2, #1024] @ 0x400 800a32a: b292 uxth r2, r2 800a32c: 7819 ldrb r1, [r3, #0] 800a32e: 4b14 ldr r3, [pc, #80] @ (800a380 ) 800a330: 5499 strb r1, [r3, r2] debug_buffer.write_index = (debug_buffer.write_index + 1) % DEBUG_BUFFER_SIZE; 800a332: 4b13 ldr r3, [pc, #76] @ (800a380 ) 800a334: f8b3 3400 ldrh.w r3, [r3, #1024] @ 0x400 800a338: b29b uxth r3, r3 800a33a: 3301 adds r3, #1 800a33c: 425a negs r2, r3 800a33e: f3c3 0309 ubfx r3, r3, #0, #10 800a342: f3c2 0209 ubfx r2, r2, #0, #10 800a346: bf58 it pl 800a348: 4253 negpl r3, r2 800a34a: b29a uxth r2, r3 800a34c: 4b0c ldr r3, [pc, #48] @ (800a380 ) 800a34e: f8a3 2400 strh.w r2, [r3, #1024] @ 0x400 debug_buffer.count++; 800a352: 4b0b ldr r3, [pc, #44] @ (800a380 ) 800a354: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a358: b29b uxth r3, r3 800a35a: 3301 adds r3, #1 800a35c: b29a uxth r2, r3 800a35e: 4b08 ldr r3, [pc, #32] @ (800a380 ) 800a360: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 for (uint16_t i = 0; i < len; i++) { 800a364: 89fb ldrh r3, [r7, #14] 800a366: 3301 adds r3, #1 800a368: 81fb strh r3, [r7, #14] 800a36a: 89fa ldrh r2, [r7, #14] 800a36c: 887b ldrh r3, [r7, #2] 800a36e: 429a cmp r2, r3 800a370: d3b5 bcc.n 800a2de __ASM volatile ("cpsie i" : : : "memory"); 800a372: b662 cpsie i } 800a374: bf00 nop } __enable_irq(); } 800a376: bf00 nop 800a378: 3714 adds r7, #20 800a37a: 46bd mov sp, r7 800a37c: bc80 pop {r7} 800a37e: 4770 bx lr 800a380: 20000210 .word 0x20000210 0800a384 : // Возвращает количество доступных данных в буфере uint16_t debug_buffer_available(void) { 800a384: b480 push {r7} 800a386: b083 sub sp, #12 800a388: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a38a: b672 cpsid i } 800a38c: bf00 nop __disable_irq(); uint16_t count = debug_buffer.count; 800a38e: 4b06 ldr r3, [pc, #24] @ (800a3a8 ) 800a390: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a394: 80fb strh r3, [r7, #6] __ASM volatile ("cpsie i" : : : "memory"); 800a396: b662 cpsie i } 800a398: bf00 nop __enable_irq(); return count; 800a39a: 88fb ldrh r3, [r7, #6] } 800a39c: 4618 mov r0, r3 800a39e: 370c adds r7, #12 800a3a0: 46bd mov sp, r7 800a3a2: bc80 pop {r7} 800a3a4: 4770 bx lr 800a3a6: bf00 nop 800a3a8: 20000210 .word 0x20000210 0800a3ac : // Отправляет один пакет данных из буфера через SC_SendPacket (не более 250 байт) void debug_buffer_send(void) { 800a3ac: b580 push {r7, lr} 800a3ae: b082 sub sp, #8 800a3b0: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a3b2: b672 cpsid i } 800a3b4: bf00 nop __disable_irq(); // Если буфер пуст, ничего не делаем if (debug_buffer.count == 0) { 800a3b6: 4b2d ldr r3, [pc, #180] @ (800a46c ) 800a3b8: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a3bc: b29b uxth r3, r3 800a3be: 2b00 cmp r3, #0 800a3c0: d102 bne.n 800a3c8 __ASM volatile ("cpsie i" : : : "memory"); 800a3c2: b662 cpsie i } 800a3c4: bf00 nop __enable_irq(); return; 800a3c6: e04e b.n 800a466 } // Определяем сколько байт можно отправить (не более 250) uint16_t bytes_to_send = debug_buffer.count; 800a3c8: 4b28 ldr r3, [pc, #160] @ (800a46c ) 800a3ca: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a3ce: 80fb strh r3, [r7, #6] if (bytes_to_send > DEBUG_BUFFER_MAX_COUNT) { 800a3d0: 88fb ldrh r3, [r7, #6] 800a3d2: 2b80 cmp r3, #128 @ 0x80 800a3d4: d901 bls.n 800a3da bytes_to_send = DEBUG_BUFFER_MAX_COUNT; 800a3d6: 2380 movs r3, #128 @ 0x80 800a3d8: 80fb strh r3, [r7, #6] } // Вычисляем сколько байт до конца буфера uint16_t bytes_to_end = DEBUG_BUFFER_SIZE - debug_buffer.read_index; 800a3da: 4b24 ldr r3, [pc, #144] @ (800a46c ) 800a3dc: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a3e0: b29b uxth r3, r3 800a3e2: f5c3 6380 rsb r3, r3, #1024 @ 0x400 800a3e6: 80bb strh r3, [r7, #4] // Отправляем только непрерывный блок (до конца буфера или до bytes_to_send) if (bytes_to_send > bytes_to_end) { 800a3e8: 88fa ldrh r2, [r7, #6] 800a3ea: 88bb ldrh r3, [r7, #4] 800a3ec: 429a cmp r2, r3 800a3ee: d901 bls.n 800a3f4 bytes_to_send = bytes_to_end; 800a3f0: 88bb ldrh r3, [r7, #4] 800a3f2: 80fb strh r3, [r7, #6] } // Отправляем данные напрямую из буфера if(bytes_to_send == debug_buffer.count){ 800a3f4: 4b1d ldr r3, [pc, #116] @ (800a46c ) 800a3f6: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a3fa: b29b uxth r3, r3 800a3fc: 88fa ldrh r2, [r7, #6] 800a3fe: 429a cmp r2, r3 800a400: d10c bne.n 800a41c SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG); 800a402: 4b1a ldr r3, [pc, #104] @ (800a46c ) 800a404: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a408: b29b uxth r3, r3 800a40a: 461a mov r2, r3 800a40c: 4b17 ldr r3, [pc, #92] @ (800a46c ) 800a40e: 4413 add r3, r2 800a410: 88f9 ldrh r1, [r7, #6] 800a412: 2250 movs r2, #80 @ 0x50 800a414: 4618 mov r0, r3 800a416: f002 f999 bl 800c74c 800a41a: e00b b.n 800a434 }else{ SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG_CONTINUE); 800a41c: 4b13 ldr r3, [pc, #76] @ (800a46c ) 800a41e: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a422: b29b uxth r3, r3 800a424: 461a mov r2, r3 800a426: 4b11 ldr r3, [pc, #68] @ (800a46c ) 800a428: 4413 add r3, r2 800a42a: 88f9 ldrh r1, [r7, #6] 800a42c: 2251 movs r2, #81 @ 0x51 800a42e: 4618 mov r0, r3 800a430: f002 f98c bl 800c74c } debug_buffer.read_index = (debug_buffer.read_index + bytes_to_send) % DEBUG_BUFFER_SIZE; 800a434: 4b0d ldr r3, [pc, #52] @ (800a46c ) 800a436: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a43a: b29a uxth r2, r3 800a43c: 88fb ldrh r3, [r7, #6] 800a43e: 4413 add r3, r2 800a440: b29b uxth r3, r3 800a442: f3c3 0309 ubfx r3, r3, #0, #10 800a446: b29a uxth r2, r3 800a448: 4b08 ldr r3, [pc, #32] @ (800a46c ) 800a44a: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count -= bytes_to_send; 800a44e: 4b07 ldr r3, [pc, #28] @ (800a46c ) 800a450: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a454: b29a uxth r2, r3 800a456: 88fb ldrh r3, [r7, #6] 800a458: 1ad3 subs r3, r2, r3 800a45a: b29a uxth r2, r3 800a45c: 4b03 ldr r3, [pc, #12] @ (800a46c ) 800a45e: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 __ASM volatile ("cpsie i" : : : "memory"); 800a462: b662 cpsie i } 800a464: bf00 nop __enable_irq(); } 800a466: 3708 adds r7, #8 800a468: 46bd mov sp, r7 800a46a: bd80 pop {r7, pc} 800a46c: 20000210 .word 0x20000210 0800a470 : #define LOG_BUFFER_SIZE 128 uint8_t log_buffer[LOG_BUFFER_SIZE]; // Кастомный printf с приоритетом лога int log_printf(LogLevel_t level, const char *format, ...) { 800a470: b40e push {r1, r2, r3} 800a472: b580 push {r7, lr} 800a474: b085 sub sp, #20 800a476: af00 add r7, sp, #0 800a478: 4603 mov r3, r0 800a47a: 71fb strb r3, [r7, #7] va_list args; int result; // Добавляем приоритет первым байтом log_buffer[0] = (uint8_t)level; 800a47c: 4a15 ldr r2, [pc, #84] @ (800a4d4 ) 800a47e: 79fb ldrb r3, [r7, #7] 800a480: 7013 strb r3, [r2, #0] // Форматируем строку начиная со второго байта va_start(args, format); 800a482: f107 0320 add.w r3, r7, #32 800a486: 60bb str r3, [r7, #8] result = vsnprintf((char*)&log_buffer[1], LOG_BUFFER_SIZE - 2, format, args); 800a488: 68bb ldr r3, [r7, #8] 800a48a: 69fa ldr r2, [r7, #28] 800a48c: 217e movs r1, #126 @ 0x7e 800a48e: 4812 ldr r0, [pc, #72] @ (800a4d8 ) 800a490: f008 fd84 bl 8012f9c 800a494: 60f8 str r0, [r7, #12] va_end(args); // Проверяем, не переполнился ли буфер if (result < 0) { 800a496: 68fb ldr r3, [r7, #12] 800a498: 2b00 cmp r3, #0 800a49a: da01 bge.n 800a4a0 return result; 800a49c: 68fb ldr r3, [r7, #12] 800a49e: e012 b.n 800a4c6 } // Ограничиваем размер, чтобы оставить место для нуль-терминатора if (result >= (LOG_BUFFER_SIZE - 2)) { 800a4a0: 68fb ldr r3, [r7, #12] 800a4a2: 2b7d cmp r3, #125 @ 0x7d 800a4a4: dd01 ble.n 800a4aa result = LOG_BUFFER_SIZE - 2; 800a4a6: 237e movs r3, #126 @ 0x7e 800a4a8: 60fb str r3, [r7, #12] } // Добавляем нуль-терминатор в конец log_buffer[result + 1] = '\0'; 800a4aa: 68fb ldr r3, [r7, #12] 800a4ac: 3301 adds r3, #1 800a4ae: 4a09 ldr r2, [pc, #36] @ (800a4d4 ) 800a4b0: 2100 movs r1, #0 800a4b2: 54d1 strb r1, [r2, r3] // Отправляем в буфер (приоритет + строка + нуль-терминатор) debug_buffer_add(log_buffer, result + 2); 800a4b4: 68fb ldr r3, [r7, #12] 800a4b6: b29b uxth r3, r3 800a4b8: 3302 adds r3, #2 800a4ba: b29b uxth r3, r3 800a4bc: 4619 mov r1, r3 800a4be: 4805 ldr r0, [pc, #20] @ (800a4d4 ) 800a4c0: f7ff ff02 bl 800a2c8 return result; 800a4c4: 68fb ldr r3, [r7, #12] } 800a4c6: 4618 mov r0, r3 800a4c8: 3714 adds r7, #20 800a4ca: 46bd mov sp, r7 800a4cc: e8bd 4080 ldmia.w sp!, {r7, lr} 800a4d0: b003 add sp, #12 800a4d2: 4770 bx lr 800a4d4: 20000618 .word 0x20000618 800a4d8: 20000619 .word 0x20000619 0800a4dc : * EXTI PB8 ------> I2C1_SCL PB9 ------> I2C1_SDA */ void MX_GPIO_Init(void) { 800a4dc: b580 push {r7, lr} 800a4de: b08a sub sp, #40 @ 0x28 800a4e0: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800a4e2: f107 0314 add.w r3, r7, #20 800a4e6: 2200 movs r2, #0 800a4e8: 601a str r2, [r3, #0] 800a4ea: 605a str r2, [r3, #4] 800a4ec: 609a str r2, [r3, #8] 800a4ee: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 800a4f0: 4b7d ldr r3, [pc, #500] @ (800a6e8 ) 800a4f2: 699b ldr r3, [r3, #24] 800a4f4: 4a7c ldr r2, [pc, #496] @ (800a6e8 ) 800a4f6: f043 0310 orr.w r3, r3, #16 800a4fa: 6193 str r3, [r2, #24] 800a4fc: 4b7a ldr r3, [pc, #488] @ (800a6e8 ) 800a4fe: 699b ldr r3, [r3, #24] 800a500: f003 0310 and.w r3, r3, #16 800a504: 613b str r3, [r7, #16] 800a506: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800a508: 4b77 ldr r3, [pc, #476] @ (800a6e8 ) 800a50a: 699b ldr r3, [r3, #24] 800a50c: 4a76 ldr r2, [pc, #472] @ (800a6e8 ) 800a50e: f043 0304 orr.w r3, r3, #4 800a512: 6193 str r3, [r2, #24] 800a514: 4b74 ldr r3, [pc, #464] @ (800a6e8 ) 800a516: 699b ldr r3, [r3, #24] 800a518: f003 0304 and.w r3, r3, #4 800a51c: 60fb str r3, [r7, #12] 800a51e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 800a520: 4b71 ldr r3, [pc, #452] @ (800a6e8 ) 800a522: 699b ldr r3, [r3, #24] 800a524: 4a70 ldr r2, [pc, #448] @ (800a6e8 ) 800a526: f043 0308 orr.w r3, r3, #8 800a52a: 6193 str r3, [r2, #24] 800a52c: 4b6e ldr r3, [pc, #440] @ (800a6e8 ) 800a52e: 699b ldr r3, [r3, #24] 800a530: f003 0308 and.w r3, r3, #8 800a534: 60bb str r3, [r7, #8] 800a536: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOE_CLK_ENABLE(); 800a538: 4b6b ldr r3, [pc, #428] @ (800a6e8 ) 800a53a: 699b ldr r3, [r3, #24] 800a53c: 4a6a ldr r2, [pc, #424] @ (800a6e8 ) 800a53e: f043 0340 orr.w r3, r3, #64 @ 0x40 800a542: 6193 str r3, [r2, #24] 800a544: 4b68 ldr r3, [pc, #416] @ (800a6e8 ) 800a546: 699b ldr r3, [r3, #24] 800a548: f003 0340 and.w r3, r3, #64 @ 0x40 800a54c: 607b str r3, [r7, #4] 800a54e: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 800a550: 4b65 ldr r3, [pc, #404] @ (800a6e8 ) 800a552: 699b ldr r3, [r3, #24] 800a554: 4a64 ldr r2, [pc, #400] @ (800a6e8 ) 800a556: f043 0320 orr.w r3, r3, #32 800a55a: 6193 str r3, [r2, #24] 800a55c: 4b62 ldr r3, [pc, #392] @ (800a6e8 ) 800a55e: 699b ldr r3, [r3, #24] 800a560: f003 0320 and.w r3, r3, #32 800a564: 603b str r3, [r7, #0] 800a566: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin, GPIO_PIN_RESET); 800a568: 2200 movs r2, #0 800a56a: 2138 movs r1, #56 @ 0x38 800a56c: 485f ldr r0, [pc, #380] @ (800a6ec ) 800a56e: f005 f9c2 bl 800f8f6 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a572: 2200 movs r2, #0 800a574: f44f 51f8 mov.w r1, #7936 @ 0x1f00 800a578: 485d ldr r0, [pc, #372] @ (800a6f0 ) 800a57a: f005 f9bc bl 800f8f6 |RELAY5_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, GPIO_PIN_RESET); 800a57e: 2200 movs r2, #0 800a580: f44f 4100 mov.w r1, #32768 @ 0x8000 800a584: 485b ldr r0, [pc, #364] @ (800a6f4 ) 800a586: f005 f9b6 bl 800f8f6 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, RELAY_DC_Pin|USART2_DIR_Pin, GPIO_PIN_RESET); 800a58a: 2200 movs r2, #0 800a58c: 2118 movs r1, #24 800a58e: 485a ldr r0, [pc, #360] @ (800a6f8 ) 800a590: f005 f9b1 bl 800f8f6 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(EE_WP_GPIO_Port, EE_WP_Pin, GPIO_PIN_RESET); 800a594: 2200 movs r2, #0 800a596: 2180 movs r1, #128 @ 0x80 800a598: 4858 ldr r0, [pc, #352] @ (800a6fc ) 800a59a: f005 f9ac bl 800f8f6 /*Configure GPIO pins : RELAY_CP_Pin LOCK_A_Pin LOCK_B_Pin */ GPIO_InitStruct.Pin = RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin; 800a59e: 2338 movs r3, #56 @ 0x38 800a5a0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a5a2: 2301 movs r3, #1 800a5a4: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a5a6: 2300 movs r3, #0 800a5a8: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a5aa: 2302 movs r3, #2 800a5ac: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800a5ae: f107 0314 add.w r3, r7, #20 800a5b2: 4619 mov r1, r3 800a5b4: 484d ldr r0, [pc, #308] @ (800a6ec ) 800a5b6: f005 f803 bl 800f5c0 /*Configure GPIO pin : IN_SW0_Pin */ GPIO_InitStruct.Pin = IN_SW0_Pin; 800a5ba: 2302 movs r3, #2 800a5bc: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a5be: 2300 movs r3, #0 800a5c0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a5c2: 2300 movs r3, #0 800a5c4: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW0_GPIO_Port, &GPIO_InitStruct); 800a5c6: f107 0314 add.w r3, r7, #20 800a5ca: 4619 mov r1, r3 800a5cc: 4849 ldr r0, [pc, #292] @ (800a6f4 ) 800a5ce: f004 fff7 bl 800f5c0 /*Configure GPIO pin : IN_SW1_Pin */ GPIO_InitStruct.Pin = IN_SW1_Pin; 800a5d2: 2304 movs r3, #4 800a5d4: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a5d6: 2300 movs r3, #0 800a5d8: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 800a5da: 2302 movs r3, #2 800a5dc: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW1_GPIO_Port, &GPIO_InitStruct); 800a5de: f107 0314 add.w r3, r7, #20 800a5e2: 4619 mov r1, r3 800a5e4: 4843 ldr r0, [pc, #268] @ (800a6f4 ) 800a5e6: f004 ffeb bl 800f5c0 /*Configure GPIO pins : IN0_Pin AC_OK_Pin ISO_IN_Pin */ GPIO_InitStruct.Pin = IN0_Pin|AC_OK_Pin|ISO_IN_Pin; 800a5ea: f244 0382 movw r3, #16514 @ 0x4082 800a5ee: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a5f0: 2300 movs r3, #0 800a5f2: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a5f4: 2300 movs r3, #0 800a5f6: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a5f8: f107 0314 add.w r3, r7, #20 800a5fc: 4619 mov r1, r3 800a5fe: 483c ldr r0, [pc, #240] @ (800a6f0 ) 800a600: f004 ffde bl 800f5c0 /*Configure GPIO pins : RELAY1_Pin RELAY2_Pin RELAY3_Pin RELAY4_Pin RELAY5_Pin */ GPIO_InitStruct.Pin = RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a604: f44f 53f8 mov.w r3, #7936 @ 0x1f00 800a608: 617b str r3, [r7, #20] |RELAY5_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a60a: 2301 movs r3, #1 800a60c: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a60e: 2300 movs r3, #0 800a610: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a612: 2302 movs r3, #2 800a614: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a616: f107 0314 add.w r3, r7, #20 800a61a: 4619 mov r1, r3 800a61c: 4834 ldr r0, [pc, #208] @ (800a6f0 ) 800a61e: f004 ffcf bl 800f5c0 /*Configure GPIO pin : RELAY_CC_Pin */ GPIO_InitStruct.Pin = RELAY_CC_Pin; 800a622: f44f 4300 mov.w r3, #32768 @ 0x8000 800a626: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a628: 2301 movs r3, #1 800a62a: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a62c: 2300 movs r3, #0 800a62e: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a630: 2302 movs r3, #2 800a632: 623b str r3, [r7, #32] HAL_GPIO_Init(RELAY_CC_GPIO_Port, &GPIO_InitStruct); 800a634: f107 0314 add.w r3, r7, #20 800a638: 4619 mov r1, r3 800a63a: 482e ldr r0, [pc, #184] @ (800a6f4 ) 800a63c: f004 ffc0 bl 800f5c0 /*Configure GPIO pins : RELAY_DC_Pin USART2_DIR_Pin */ GPIO_InitStruct.Pin = RELAY_DC_Pin|USART2_DIR_Pin; 800a640: 2318 movs r3, #24 800a642: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a644: 2301 movs r3, #1 800a646: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a648: 2300 movs r3, #0 800a64a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a64c: 2302 movs r3, #2 800a64e: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800a650: f107 0314 add.w r3, r7, #20 800a654: 4619 mov r1, r3 800a656: 4828 ldr r0, [pc, #160] @ (800a6f8 ) 800a658: f004 ffb2 bl 800f5c0 /*Configure GPIO pin : IN_ESTOP_Pin */ GPIO_InitStruct.Pin = IN_ESTOP_Pin; 800a65c: 2380 movs r3, #128 @ 0x80 800a65e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a660: 2300 movs r3, #0 800a662: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a664: 2300 movs r3, #0 800a666: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_ESTOP_GPIO_Port, &GPIO_InitStruct); 800a668: f107 0314 add.w r3, r7, #20 800a66c: 4619 mov r1, r3 800a66e: 4822 ldr r0, [pc, #136] @ (800a6f8 ) 800a670: f004 ffa6 bl 800f5c0 /*Configure GPIO pins : IN_FB2_Pin IN_FB1_Pin */ GPIO_InitStruct.Pin = IN_FB2_Pin|IN_FB1_Pin; 800a674: 2318 movs r3, #24 800a676: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a678: 2300 movs r3, #0 800a67a: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a67c: 2300 movs r3, #0 800a67e: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a680: f107 0314 add.w r3, r7, #20 800a684: 4619 mov r1, r3 800a686: 481d ldr r0, [pc, #116] @ (800a6fc ) 800a688: f004 ff9a bl 800f5c0 /*Configure GPIO pin : EE_WP_Pin */ GPIO_InitStruct.Pin = EE_WP_Pin; 800a68c: 2380 movs r3, #128 @ 0x80 800a68e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a690: 2301 movs r3, #1 800a692: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a694: 2300 movs r3, #0 800a696: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a698: 2302 movs r3, #2 800a69a: 623b str r3, [r7, #32] HAL_GPIO_Init(EE_WP_GPIO_Port, &GPIO_InitStruct); 800a69c: f107 0314 add.w r3, r7, #20 800a6a0: 4619 mov r1, r3 800a6a2: 4816 ldr r0, [pc, #88] @ (800a6fc ) 800a6a4: f004 ff8c bl 800f5c0 /*Configure GPIO pins : PB8 PB9 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 800a6a8: f44f 7340 mov.w r3, #768 @ 0x300 800a6ac: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 800a6ae: 2312 movs r3, #18 800a6b0: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a6b2: 2303 movs r3, #3 800a6b4: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a6b6: f107 0314 add.w r3, r7, #20 800a6ba: 4619 mov r1, r3 800a6bc: 480f ldr r0, [pc, #60] @ (800a6fc ) 800a6be: f004 ff7f bl 800f5c0 /*Configure peripheral I/O remapping */ __HAL_AFIO_REMAP_I2C1_ENABLE(); 800a6c2: 4b0f ldr r3, [pc, #60] @ (800a700 ) 800a6c4: 685b ldr r3, [r3, #4] 800a6c6: 627b str r3, [r7, #36] @ 0x24 800a6c8: 6a7b ldr r3, [r7, #36] @ 0x24 800a6ca: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800a6ce: 627b str r3, [r7, #36] @ 0x24 800a6d0: 6a7b ldr r3, [r7, #36] @ 0x24 800a6d2: f043 0302 orr.w r3, r3, #2 800a6d6: 627b str r3, [r7, #36] @ 0x24 800a6d8: 4a09 ldr r2, [pc, #36] @ (800a700 ) 800a6da: 6a7b ldr r3, [r7, #36] @ 0x24 800a6dc: 6053 str r3, [r2, #4] } 800a6de: bf00 nop 800a6e0: 3728 adds r7, #40 @ 0x28 800a6e2: 46bd mov sp, r7 800a6e4: bd80 pop {r7, pc} 800a6e6: bf00 nop 800a6e8: 40021000 .word 0x40021000 800a6ec: 40011000 .word 0x40011000 800a6f0: 40011800 .word 0x40011800 800a6f4: 40010800 .word 0x40010800 800a6f8: 40011400 .word 0x40011400 800a6fc: 40010c00 .word 0x40010c00 800a700: 40010000 .word 0x40010000 0800a704 : * bootloader before starting this program. Unfortunately, function * SystemInit() overwrites this change again. * @return none. */ static void VectorBase_Config(void) { 800a704: b480 push {r7} 800a706: af00 add r7, sp, #0 * c-startup code. */ extern const unsigned long g_pfnVectors[]; /* Remap the vector table to where the vector table is located for this program. */ SCB->VTOR = (unsigned long)&g_pfnVectors[0]; 800a708: 4b03 ldr r3, [pc, #12] @ (800a718 ) 800a70a: 4a04 ldr r2, [pc, #16] @ (800a71c ) 800a70c: 609a str r2, [r3, #8] } 800a70e: bf00 nop 800a710: 46bd mov sp, r7 800a712: bc80 pop {r7} 800a714: 4770 bx lr 800a716: bf00 nop 800a718: e000ed00 .word 0xe000ed00 800a71c: 08008000 .word 0x08008000 0800a720 : uint8_t ED_TraceWarning(uint8_t flag, uint8_t id){ 800a720: b480 push {r7} 800a722: b085 sub sp, #20 800a724: af00 add r7, sp, #0 800a726: 4603 mov r3, r0 800a728: 460a mov r2, r1 800a72a: 71fb strb r3, [r7, #7] 800a72c: 4613 mov r3, r2 800a72e: 71bb strb r3, [r7, #6] static uint8_t memory[32]; if(id > 31) return 0; 800a730: 79bb ldrb r3, [r7, #6] 800a732: 2b1f cmp r3, #31 800a734: d901 bls.n 800a73a 800a736: 2300 movs r3, #0 800a738: e00e b.n 800a758 uint8_t result = 0; 800a73a: 2300 movs r3, #0 800a73c: 73fb strb r3, [r7, #15] if(memory[id] != flag){ 800a73e: 79bb ldrb r3, [r7, #6] 800a740: 4a08 ldr r2, [pc, #32] @ (800a764 ) 800a742: 5cd3 ldrb r3, [r2, r3] 800a744: 79fa ldrb r2, [r7, #7] 800a746: 429a cmp r2, r3 800a748: d001 beq.n 800a74e result = 1; 800a74a: 2301 movs r3, #1 800a74c: 73fb strb r3, [r7, #15] } memory[id] = flag; 800a74e: 79bb ldrb r3, [r7, #6] 800a750: 4904 ldr r1, [pc, #16] @ (800a764 ) 800a752: 79fa ldrb r2, [r7, #7] 800a754: 54ca strb r2, [r1, r3] return result; 800a756: 7bfb ldrb r3, [r7, #15] } 800a758: 4618 mov r0, r3 800a75a: 3714 adds r7, #20 800a75c: 46bd mov sp, r7 800a75e: bc80 pop {r7} 800a760: 4770 bx lr 800a762: bf00 nop 800a764: 20000698 .word 0x20000698 0800a768 : void ED_Delay(uint32_t Delay) { 800a768: b580 push {r7, lr} 800a76a: b084 sub sp, #16 800a76c: af00 add r7, sp, #0 800a76e: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800a770: f003 f8b0 bl 800d8d4 800a774: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800a776: 687b ldr r3, [r7, #4] 800a778: 60fb str r3, [r7, #12] if (wait < HAL_MAX_DELAY) 800a77a: 68fb ldr r3, [r7, #12] 800a77c: f1b3 3fff cmp.w r3, #4294967295 800a780: d00e beq.n 800a7a0 { wait += (uint32_t)(uwTickFreq); 800a782: 4b0e ldr r3, [pc, #56] @ (800a7bc ) 800a784: 781b ldrb r3, [r3, #0] 800a786: 461a mov r2, r3 800a788: 68fb ldr r3, [r7, #12] 800a78a: 4413 add r3, r2 800a78c: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait){ 800a78e: e007 b.n 800a7a0 CCS_SerialLoop(); 800a790: f001 f92c bl 800b9ec // CP_Loop(); CONN_Task(); 800a794: f7ff fa66 bl 8009c64 LED_Task(); 800a798: f001 f810 bl 800b7bc SC_Task(); 800a79c: f001 fe5c bl 800c458 while ((HAL_GetTick() - tickstart) < wait){ 800a7a0: f003 f898 bl 800d8d4 800a7a4: 4602 mov r2, r0 800a7a6: 68bb ldr r3, [r7, #8] 800a7a8: 1ad3 subs r3, r2, r3 800a7aa: 68fa ldr r2, [r7, #12] 800a7ac: 429a cmp r2, r3 800a7ae: d8ef bhi.n 800a790 } } 800a7b0: bf00 nop 800a7b2: bf00 nop 800a7b4: 3710 adds r7, #16 800a7b6: 46bd mov sp, r7 800a7b8: bd80 pop {r7, pc} 800a7ba: bf00 nop 800a7bc: 20000074 .word 0x20000074 0800a7c0 : void StopButtonControl(){ 800a7c0: b580 push {r7, lr} 800a7c2: af00 add r7, sp, #0 //Charging do nothing if(!IN_ReadInput(IN_ESTOP)){ 800a7c4: 2003 movs r0, #3 800a7c6: f7fe fef3 bl 80095b0 800a7ca: 4603 mov r3, r0 800a7cc: 2b00 cmp r3, #0 800a7ce: d102 bne.n 800a7d6 CONN.connControl = CMD_STOP; 800a7d0: 4b02 ldr r3, [pc, #8] @ (800a7dc ) 800a7d2: 2201 movs r2, #1 800a7d4: 701a strb r2, [r3, #0] } } 800a7d6: bf00 nop 800a7d8: bd80 pop {r7, pc} 800a7da: bf00 nop 800a7dc: 200001d4 .word 0x200001d4 0800a7e0 : uint8_t temp0, temp1; static void CAN1_MinimalReInit(void) { 800a7e0: b580 push {r7, lr} 800a7e2: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan1); 800a7e4: 480b ldr r0, [pc, #44] @ (800a814 ) 800a7e6: f003 ffc9 bl 800e77c MX_CAN1_Init(); 800a7ea: f7ff f89b bl 8009924 if (HAL_CAN_Start(&hcan1) != HAL_OK) { 800a7ee: 4809 ldr r0, [pc, #36] @ (800a814 ) 800a7f0: f003 ff80 bl 800e6f4 800a7f4: 4603 mov r3, r0 800a7f6: 2b00 cmp r3, #0 800a7f8: d001 beq.n 800a7fe Error_Handler(); 800a7fa: f000 f8f9 bl 800a9f0 } if (HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) { 800a7fe: 2102 movs r1, #2 800a800: 4804 ldr r0, [pc, #16] @ (800a814 ) 800a802: f004 fa28 bl 800ec56 800a806: 4603 mov r3, r0 800a808: 2b00 cmp r3, #0 800a80a: d001 beq.n 800a810 Error_Handler(); 800a80c: f000 f8f0 bl 800a9f0 } } 800a810: bf00 nop 800a812: bd80 pop {r7, pc} 800a814: 20000180 .word 0x20000180 0800a818
: /** * @brief The application entry point. * @retval int */ int main(void) { 800a818: b580 push {r7, lr} 800a81a: b082 sub sp, #8 800a81c: af02 add r7, sp, #8 /* USER CODE BEGIN 1 */ VectorBase_Config(); 800a81e: f7ff ff71 bl 800a704 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800a822: f002 ffff bl 800d824 /* USER CODE BEGIN Init */ HAL_RCC_DeInit(); 800a826: f005 f88b bl 800f940 /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800a82a: f000 f871 bl 800a910 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800a82e: f7ff fe55 bl 800a4dc MX_ADC1_Init(); 800a832: f7fe fdab bl 800938c MX_CAN1_Init(); 800a836: f7ff f875 bl 8009924 MX_CAN2_Init(); 800a83a: f7ff f8a9 bl 8009990 MX_RTC_Init(); 800a83e: f001 f85b bl 800b8f8 MX_TIM4_Init(); 800a842: f002 fcab bl 800d19c MX_USART2_UART_Init(); 800a846: f002 fe29 bl 800d49c MX_CRC_Init(); 800a84a: f7ff fcf9 bl 800a240 MX_UART5_Init(); 800a84e: f002 fdd1 bl 800d3f4 MX_USART1_UART_Init(); 800a852: f002 fdf9 bl 800d448 MX_USART3_UART_Init(); 800a856: f002 fe4b bl 800d4f0 MX_TIM3_Init(); 800a85a: f002 fc29 bl 800d0b0 /* USER CODE BEGIN 2 */ Init_Peripheral(); 800a85e: f7fe fef9 bl 8009654 LED_Init(); 800a862: f000 ff8b bl 800b77c HAL_Delay(300); 800a866: f44f 7096 mov.w r0, #300 @ 0x12c 800a86a: f003 f83d bl 800d8e8 CCS_Init(); 800a86e: f001 fa99 bl 800bda4 SC_Init(); 800a872: f001 fddd bl 800c430 log_printf(LOG_INFO, "CCS module start\n"); 800a876: 4921 ldr r1, [pc, #132] @ (800a8fc ) 800a878: 2007 movs r0, #7 800a87a: f7ff fdf9 bl 800a470 ReadVersion(); 800a87e: f001 fdb3 bl 800c3e8 log_printf(LOG_INFO, "Serial number: %d\n", infoPacket.serialNumber); 800a882: 4b1f ldr r3, [pc, #124] @ (800a900 ) 800a884: 881b ldrh r3, [r3, #0] 800a886: b29b uxth r3, r3 800a888: 461a mov r2, r3 800a88a: 491e ldr r1, [pc, #120] @ (800a904 ) 800a88c: 2007 movs r0, #7 800a88e: f7ff fdef bl 800a470 log_printf(LOG_INFO, "Board revision: %d\n", infoPacket.boardVersion); 800a892: 4b1b ldr r3, [pc, #108] @ (800a900 ) 800a894: 789b ldrb r3, [r3, #2] 800a896: 461a mov r2, r3 800a898: 491b ldr r1, [pc, #108] @ (800a908 ) 800a89a: 2007 movs r0, #7 800a89c: f7ff fde8 bl 800a470 log_printf(LOG_INFO, "FW version: %d.%d.%d\n", infoPacket.fw_version_major, infoPacket.fw_version_minor, infoPacket.fw_version_patch); 800a8a0: 4b17 ldr r3, [pc, #92] @ (800a900 ) 800a8a2: 889b ldrh r3, [r3, #4] 800a8a4: b29b uxth r3, r3 800a8a6: 461a mov r2, r3 800a8a8: 4b15 ldr r3, [pc, #84] @ (800a900 ) 800a8aa: 88db ldrh r3, [r3, #6] 800a8ac: b29b uxth r3, r3 800a8ae: 4619 mov r1, r3 800a8b0: 4b13 ldr r3, [pc, #76] @ (800a900 ) 800a8b2: 891b ldrh r3, [r3, #8] 800a8b4: b29b uxth r3, r3 800a8b6: 9300 str r3, [sp, #0] 800a8b8: 460b mov r3, r1 800a8ba: 4914 ldr r1, [pc, #80] @ (800a90c ) 800a8bc: 2007 movs r0, #7 800a8be: f7ff fdd7 bl 800a470 CAN1_MinimalReInit(); 800a8c2: f7ff ff8d bl 800a7e0 PSU_Init(); 800a8c6: f000 fa7d bl 800adc4 CONN_Init(); 800a8ca: f7ff f975 bl 8009bb8 /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ PSU_ReadWrite(); 800a8ce: f000 fb87 bl 800afe0 PSU_Task(); 800a8d2: f000 fc25 bl 800b120 ED_Delay(10); 800a8d6: 200a movs r0, #10 800a8d8: f7ff ff46 bl 800a768 METER_CalculateEnergy(); 800a8dc: f000 f88e bl 800a9fc CONN_Loop(); 800a8e0: f7ff f980 bl 8009be4 LED_Write(); 800a8e4: f000 fe10 bl 800b508 ED_Delay(10); 800a8e8: 200a movs r0, #10 800a8ea: f7ff ff3d bl 800a768 StopButtonControl(); 800a8ee: f7ff ff67 bl 800a7c0 ED_Delay(50); 800a8f2: 2032 movs r0, #50 @ 0x32 800a8f4: f7ff ff38 bl 800a768 { 800a8f8: bf00 nop 800a8fa: e7e8 b.n 800a8ce 800a8fc: 08014130 .word 0x08014130 800a900: 20000eb0 .word 0x20000eb0 800a904: 08014144 .word 0x08014144 800a908: 08014158 .word 0x08014158 800a90c: 0801416c .word 0x0801416c 0800a910 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800a910: b580 push {r7, lr} 800a912: b09c sub sp, #112 @ 0x70 800a914: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800a916: f107 0338 add.w r3, r7, #56 @ 0x38 800a91a: 2238 movs r2, #56 @ 0x38 800a91c: 2100 movs r1, #0 800a91e: 4618 mov r0, r3 800a920: f008 fb4a bl 8012fb8 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800a924: f107 0324 add.w r3, r7, #36 @ 0x24 800a928: 2200 movs r2, #0 800a92a: 601a str r2, [r3, #0] 800a92c: 605a str r2, [r3, #4] 800a92e: 609a str r2, [r3, #8] 800a930: 60da str r2, [r3, #12] 800a932: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 800a934: 1d3b adds r3, r7, #4 800a936: 2220 movs r2, #32 800a938: 2100 movs r1, #0 800a93a: 4618 mov r0, r3 800a93c: f008 fb3c bl 8012fb8 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; 800a940: 2305 movs r3, #5 800a942: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800a944: f44f 3380 mov.w r3, #65536 @ 0x10000 800a948: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV5; 800a94a: 2304 movs r3, #4 800a94c: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 800a94e: 2301 movs r3, #1 800a950: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800a952: 2301 movs r3, #1 800a954: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.Prediv1Source = RCC_PREDIV1_SOURCE_PLL2; 800a956: f44f 3380 mov.w r3, #65536 @ 0x10000 800a95a: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800a95c: 2302 movs r3, #2 800a95e: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800a960: f44f 3380 mov.w r3, #65536 @ 0x10000 800a964: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 800a966: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000 800a96a: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL2.PLL2State = RCC_PLL2_ON; 800a96c: 2302 movs r3, #2 800a96e: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL2.PLL2MUL = RCC_PLL2_MUL8; 800a970: f44f 63c0 mov.w r3, #1536 @ 0x600 800a974: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL2.HSEPrediv2Value = RCC_HSE_PREDIV2_DIV5; 800a976: 2340 movs r3, #64 @ 0x40 800a978: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800a97a: f107 0338 add.w r3, r7, #56 @ 0x38 800a97e: 4618 mov r0, r3 800a980: f005 f8ae bl 800fae0 800a984: 4603 mov r3, r0 800a986: 2b00 cmp r3, #0 800a988: d001 beq.n 800a98e { Error_Handler(); 800a98a: f000 f831 bl 800a9f0 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800a98e: 230f movs r3, #15 800a990: 627b str r3, [r7, #36] @ 0x24 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800a992: 2302 movs r3, #2 800a994: 62bb str r3, [r7, #40] @ 0x28 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800a996: 2300 movs r3, #0 800a998: 62fb str r3, [r7, #44] @ 0x2c RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 800a99a: f44f 6380 mov.w r3, #1024 @ 0x400 800a99e: 633b str r3, [r7, #48] @ 0x30 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 800a9a0: 2300 movs r3, #0 800a9a2: 637b str r3, [r7, #52] @ 0x34 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800a9a4: f107 0324 add.w r3, r7, #36 @ 0x24 800a9a8: 2102 movs r1, #2 800a9aa: 4618 mov r0, r3 800a9ac: f005 fbae bl 801010c 800a9b0: 4603 mov r3, r0 800a9b2: 2b00 cmp r3, #0 800a9b4: d001 beq.n 800a9ba { Error_Handler(); 800a9b6: f000 f81b bl 800a9f0 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; 800a9ba: 2303 movs r3, #3 800a9bc: 607b str r3, [r7, #4] PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 800a9be: f44f 7380 mov.w r3, #256 @ 0x100 800a9c2: 60bb str r3, [r7, #8] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 800a9c4: f44f 4300 mov.w r3, #32768 @ 0x8000 800a9c8: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 800a9ca: 1d3b adds r3, r7, #4 800a9cc: 4618 mov r0, r3 800a9ce: f005 fd93 bl 80104f8 800a9d2: 4603 mov r3, r0 800a9d4: 2b00 cmp r3, #0 800a9d6: d001 beq.n 800a9dc { Error_Handler(); 800a9d8: f000 f80a bl 800a9f0 } /** Configure the Systick interrupt time */ __HAL_RCC_PLLI2S_ENABLE(); 800a9dc: 4b03 ldr r3, [pc, #12] @ (800a9ec ) 800a9de: 2201 movs r2, #1 800a9e0: 601a str r2, [r3, #0] } 800a9e2: bf00 nop 800a9e4: 3770 adds r7, #112 @ 0x70 800a9e6: 46bd mov sp, r7 800a9e8: bd80 pop {r7, pc} 800a9ea: bf00 nop 800a9ec: 42420070 .word 0x42420070 0800a9f0 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800a9f0: b480 push {r7} 800a9f2: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a9f4: b672 cpsid i } 800a9f6: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 800a9f8: bf00 nop 800a9fa: e7fd b.n 800a9f8 0800a9fc : METER_t METER; // Функция для расчета и накопления энергии c дробной частью без счетчиков void METER_CalculateEnergy() { 800a9fc: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} 800aa00: b084 sub sp, #16 800aa02: af00 add r7, sp, #0 // Проверяем, что индекс находится в пределах массива METER.online = 0; 800aa04: 4b2e ldr r3, [pc, #184] @ (800aac0 ) 800aa06: 2200 movs r2, #0 800aa08: 711a strb r2, [r3, #4] if(CONN.connState == Charging){ 800aa0a: 4b2e ldr r3, [pc, #184] @ (800aac4 ) 800aa0c: 785b ldrb r3, [r3, #1] 800aa0e: 2b08 cmp r3, #8 800aa10: d104 bne.n 800aa1c METER.enable = 1; 800aa12: 4b2b ldr r3, [pc, #172] @ (800aac0 ) 800aa14: 2201 movs r2, #1 800aa16: f883 2024 strb.w r2, [r3, #36] @ 0x24 800aa1a: e003 b.n 800aa24 }else{ METER.enable = 0; 800aa1c: 4b28 ldr r3, [pc, #160] @ (800aac0 ) 800aa1e: 2200 movs r2, #0 800aa20: f883 2024 strb.w r2, [r3, #36] @ 0x24 } uint32_t currentTick = HAL_GetTick(); // Получаем текущее время в миллисекундах 800aa24: f002 ff56 bl 800d8d4 800aa28: 60f8 str r0, [r7, #12] uint32_t elapsedTimeMs = currentTick - METER.lastTick; // Вычисляем время, прошедшее с последнего вызова в секундах 800aa2a: 4b25 ldr r3, [pc, #148] @ (800aac0 ) 800aa2c: 689b ldr r3, [r3, #8] 800aa2e: 68fa ldr r2, [r7, #12] 800aa30: 1ad3 subs r3, r2, r3 800aa32: 60bb str r3, [r7, #8] METER.lastTick = currentTick; // Обновляем время последнего вызова для текущего коннектора 800aa34: 4a22 ldr r2, [pc, #136] @ (800aac0 ) 800aa36: 68fb ldr r3, [r7, #12] 800aa38: 6093 str r3, [r2, #8] uint32_t energyWs = CONN.Power * elapsedTimeMs / 1000; // Рассчитываем энергию в ватт-секундах за прошедший промежуток времени 800aa3a: 4b22 ldr r3, [pc, #136] @ (800aac4 ) 800aa3c: f8d3 3003 ldr.w r3, [r3, #3] 800aa40: 68ba ldr r2, [r7, #8] 800aa42: fb02 f303 mul.w r3, r2, r3 800aa46: 4a20 ldr r2, [pc, #128] @ (800aac8 ) 800aa48: fba2 2303 umull r2, r3, r2, r3 800aa4c: 099b lsrs r3, r3, #6 800aa4e: 607b str r3, [r7, #4] //Расчет энергии теперь идет всегда, смещение берем суммарное METER.EnergyPSU_Ws += energyWs; 800aa50: 4b1b ldr r3, [pc, #108] @ (800aac0 ) 800aa52: e9d3 2304 ldrd r2, r3, [r3, #16] 800aa56: 6879 ldr r1, [r7, #4] 800aa58: 2000 movs r0, #0 800aa5a: 460c mov r4, r1 800aa5c: 4605 mov r5, r0 800aa5e: eb12 0804 adds.w r8, r2, r4 800aa62: eb43 0905 adc.w r9, r3, r5 800aa66: 4b16 ldr r3, [pc, #88] @ (800aac0 ) 800aa68: e9c3 8904 strd r8, r9, [r3, #16] // Абсолютное значение энергии разъема складывается из накопленной дробной части и значения со счетчиков METER.AbsoluteEnergy = (uint32_t)METER.EnergyPSU_Ws/3600; //переводим в Вт*час 800aa6c: 4b14 ldr r3, [pc, #80] @ (800aac0 ) 800aa6e: e9d3 2304 ldrd r2, r3, [r3, #16] 800aa72: 4b16 ldr r3, [pc, #88] @ (800aacc ) 800aa74: fba3 2302 umull r2, r3, r3, r2 800aa78: 0adb lsrs r3, r3, #11 800aa7a: 4a11 ldr r2, [pc, #68] @ (800aac0 ) 800aa7c: 6193 str r3, [r2, #24] if(METER.enable) { 800aa7e: 4b10 ldr r3, [pc, #64] @ (800aac0 ) 800aa80: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800aa84: 2b00 cmp r3, #0 800aa86: d008 beq.n 800aa9a //enabled state CONN.Energy = METER.AbsoluteEnergy - METER.EnergyOffset;//переводим в Вт*час 800aa88: 4b0d ldr r3, [pc, #52] @ (800aac0 ) 800aa8a: 699a ldr r2, [r3, #24] 800aa8c: 4b0c ldr r3, [pc, #48] @ (800aac0 ) 800aa8e: 69db ldr r3, [r3, #28] 800aa90: 1ad3 subs r3, r2, r3 800aa92: 4a0c ldr r2, [pc, #48] @ (800aac4 ) 800aa94: f8c2 3007 str.w r3, [r2, #7] METER.EnergyOffset = METER.AbsoluteEnergy; } } 800aa98: e00c b.n 800aab4 CONN.Energy = 0; 800aa9a: 4b0a ldr r3, [pc, #40] @ (800aac4 ) 800aa9c: 2200 movs r2, #0 800aa9e: 71da strb r2, [r3, #7] 800aaa0: 2200 movs r2, #0 800aaa2: 721a strb r2, [r3, #8] 800aaa4: 2200 movs r2, #0 800aaa6: 725a strb r2, [r3, #9] 800aaa8: 2200 movs r2, #0 800aaaa: 729a strb r2, [r3, #10] METER.EnergyOffset = METER.AbsoluteEnergy; 800aaac: 4b04 ldr r3, [pc, #16] @ (800aac0 ) 800aaae: 699b ldr r3, [r3, #24] 800aab0: 4a03 ldr r2, [pc, #12] @ (800aac0 ) 800aab2: 61d3 str r3, [r2, #28] } 800aab4: bf00 nop 800aab6: 3710 adds r7, #16 800aab8: 46bd mov sp, r7 800aaba: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} 800aabe: bf00 nop 800aac0: 200006b8 .word 0x200006b8 800aac4: 200001d4 .word 0x200001d4 800aac8: 10624dd3 .word 0x10624dd3 800aacc: 91a2b3c5 .word 0x91a2b3c5 0800aad0 : uint32_t can_lastpacket; extern CAN_HandleTypeDef hcan2; static void PSU_SwitchState(PSU_State_t state){ 800aad0: b580 push {r7, lr} 800aad2: b082 sub sp, #8 800aad4: af00 add r7, sp, #0 800aad6: 4603 mov r3, r0 800aad8: 71fb strb r3, [r7, #7] PSU0.state = state; 800aada: 4a06 ldr r2, [pc, #24] @ (800aaf4 ) 800aadc: 79fb ldrb r3, [r7, #7] 800aade: 71d3 strb r3, [r2, #7] PSU0.statetick = HAL_GetTick(); 800aae0: f002 fef8 bl 800d8d4 800aae4: 4603 mov r3, r0 800aae6: 4a03 ldr r2, [pc, #12] @ (800aaf4 ) 800aae8: 6113 str r3, [r2, #16] } 800aaea: bf00 nop 800aaec: 3708 adds r7, #8 800aaee: 46bd mov sp, r7 800aaf0: bd80 pop {r7, pc} 800aaf2: bf00 nop 800aaf4: 20000724 .word 0x20000724 0800aaf8 : static uint32_t PSU_StateTime(void){ 800aaf8: b580 push {r7, lr} 800aafa: af00 add r7, sp, #0 return HAL_GetTick() - PSU0.statetick; 800aafc: f002 feea bl 800d8d4 800ab00: 4602 mov r2, r0 800ab02: 4b02 ldr r3, [pc, #8] @ (800ab0c ) 800ab04: 691b ldr r3, [r3, #16] 800ab06: 1ad3 subs r3, r2, r3 } 800ab08: 4618 mov r0, r3 800ab0a: bd80 pop {r7, pc} 800ab0c: 20000724 .word 0x20000724 0800ab10 : void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan){ 800ab10: b580 push {r7, lr} 800ab12: b084 sub sp, #16 800ab14: af00 add r7, sp, #0 800ab16: 6078 str r0, [r7, #4] static CAN_RxHeaderTypeDef RxHeader; static uint8_t RxData[8] = {0,}; CanId_t CanId; if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO1, &RxHeader, RxData) == HAL_OK) 800ab18: 4b88 ldr r3, [pc, #544] @ (800ad3c ) 800ab1a: 4a89 ldr r2, [pc, #548] @ (800ad40 ) 800ab1c: 2101 movs r1, #1 800ab1e: 6878 ldr r0, [r7, #4] 800ab20: f003 ff78 bl 800ea14 800ab24: 4603 mov r3, r0 800ab26: 2b00 cmp r3, #0 800ab28: f040 8104 bne.w 800ad34 { memcpy(&CanId, &RxHeader.ExtId, sizeof(CanId_t)); 800ab2c: 4b84 ldr r3, [pc, #528] @ (800ad40 ) 800ab2e: 685b ldr r3, [r3, #4] 800ab30: 60bb str r3, [r7, #8] /* Для DC30 поддерживается только один силовой модуль (source == 0) */ if(CanId.source != 0) return; 800ab32: 7a3b ldrb r3, [r7, #8] 800ab34: 2b00 cmp r3, #0 800ab36: f040 80fc bne.w 800ad32 can_lastpacket = HAL_GetTick(); 800ab3a: f002 fecb bl 800d8d4 800ab3e: 4603 mov r3, r0 800ab40: 4a80 ldr r2, [pc, #512] @ (800ad44 ) 800ab42: 6013 str r3, [r2, #0] if(CanId.command==0x02){ 800ab44: 7abb ldrb r3, [r7, #10] 800ab46: f003 033f and.w r3, r3, #63 @ 0x3f 800ab4a: b2db uxtb r3, r3 800ab4c: 2b02 cmp r3, #2 800ab4e: d105 bne.n 800ab5c memcpy(&PSU_02, RxData, 8); 800ab50: 4b7d ldr r3, [pc, #500] @ (800ad48 ) 800ab52: 4a7a ldr r2, [pc, #488] @ (800ad3c ) 800ab54: e892 0003 ldmia.w r2, {r0, r1} 800ab58: e883 0003 stmia.w r3, {r0, r1} } if(CanId.command==0x04){ 800ab5c: 7abb ldrb r3, [r7, #10] 800ab5e: f003 033f and.w r3, r3, #63 @ 0x3f 800ab62: b2db uxtb r3, r3 800ab64: 2b04 cmp r3, #4 800ab66: d119 bne.n 800ab9c memcpy(&PSU_04, RxData, 8); 800ab68: 4b78 ldr r3, [pc, #480] @ (800ad4c ) 800ab6a: 4a74 ldr r2, [pc, #464] @ (800ad3c ) 800ab6c: e892 0003 ldmia.w r2, {r0, r1} 800ab70: e883 0003 stmia.w r3, {r0, r1} PSU0.tempAmbient = PSU_04.moduleTemperature; 800ab74: 4b75 ldr r3, [pc, #468] @ (800ad4c ) 800ab76: 791b ldrb r3, [r3, #4] 800ab78: 461a mov r2, r3 800ab7a: 4b75 ldr r3, [pc, #468] @ (800ad50 ) 800ab7c: 61da str r2, [r3, #28] PSU0.status0.raw = PSU_04.modularForm0; 800ab7e: 4b73 ldr r3, [pc, #460] @ (800ad4c ) 800ab80: 7a1a ldrb r2, [r3, #8] 800ab82: 4b73 ldr r3, [pc, #460] @ (800ad50 ) 800ab84: f883 2020 strb.w r2, [r3, #32] PSU0.status1.raw = PSU_04.modularForm1; 800ab88: 4b70 ldr r3, [pc, #448] @ (800ad4c ) 800ab8a: 79da ldrb r2, [r3, #7] 800ab8c: 4b70 ldr r3, [pc, #448] @ (800ad50 ) 800ab8e: f883 2021 strb.w r2, [r3, #33] @ 0x21 PSU0.status2.raw = PSU_04.modularForm2; 800ab92: 4b6e ldr r3, [pc, #440] @ (800ad4c ) 800ab94: 799a ldrb r2, [r3, #6] 800ab96: 4b6e ldr r3, [pc, #440] @ (800ad50 ) 800ab98: f883 2022 strb.w r2, [r3, #34] @ 0x22 } if(CanId.command==0x06){ 800ab9c: 7abb ldrb r3, [r7, #10] 800ab9e: f003 033f and.w r3, r3, #63 @ 0x3f 800aba2: b2db uxtb r3, r3 800aba4: 2b06 cmp r3, #6 800aba6: d123 bne.n 800abf0 memcpy(&PSU_06, RxData, 8); 800aba8: 4b6a ldr r3, [pc, #424] @ (800ad54 ) 800abaa: 4a64 ldr r2, [pc, #400] @ (800ad3c ) 800abac: e892 0003 ldmia.w r2, {r0, r1} 800abb0: e883 0003 stmia.w r3, {r0, r1} PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800abb4: 4b67 ldr r3, [pc, #412] @ (800ad54 ) 800abb6: 785b ldrb r3, [r3, #1] 800abb8: 461a mov r2, r3 800abba: 4b66 ldr r3, [pc, #408] @ (800ad54 ) 800abbc: 781b ldrb r3, [r3, #0] 800abbe: 021b lsls r3, r3, #8 800abc0: 4413 add r3, r2 800abc2: 461a mov r2, r3 800abc4: 4b63 ldr r3, [pc, #396] @ (800ad54 ) 800abc6: 609a str r2, [r3, #8] PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800abc8: 4b62 ldr r3, [pc, #392] @ (800ad54 ) 800abca: 78db ldrb r3, [r3, #3] 800abcc: 461a mov r2, r3 800abce: 4b61 ldr r3, [pc, #388] @ (800ad54 ) 800abd0: 789b ldrb r3, [r3, #2] 800abd2: 021b lsls r3, r3, #8 800abd4: 4413 add r3, r2 800abd6: 461a mov r2, r3 800abd8: 4b5e ldr r3, [pc, #376] @ (800ad54 ) 800abda: 60da str r2, [r3, #12] PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800abdc: 4b5d ldr r3, [pc, #372] @ (800ad54 ) 800abde: 795b ldrb r3, [r3, #5] 800abe0: 461a mov r2, r3 800abe2: 4b5c ldr r3, [pc, #368] @ (800ad54 ) 800abe4: 791b ldrb r3, [r3, #4] 800abe6: 021b lsls r3, r3, #8 800abe8: 4413 add r3, r2 800abea: 461a mov r2, r3 800abec: 4b59 ldr r3, [pc, #356] @ (800ad54 ) 800abee: 611a str r2, [r3, #16] } if(CanId.command==0x08){ 800abf0: 7abb ldrb r3, [r7, #10] 800abf2: f003 033f and.w r3, r3, #63 @ 0x3f 800abf6: b2db uxtb r3, r3 800abf8: 2b08 cmp r3, #8 800abfa: d105 bne.n 800ac08 memcpy(&PSU_08, RxData, 8); 800abfc: 4b56 ldr r3, [pc, #344] @ (800ad58 ) 800abfe: 4a4f ldr r2, [pc, #316] @ (800ad3c ) 800ac00: e892 0003 ldmia.w r2, {r0, r1} 800ac04: e883 0003 stmia.w r3, {r0, r1} } if(CanId.command==0x09){ 800ac08: 7abb ldrb r3, [r7, #10] 800ac0a: f003 033f and.w r3, r3, #63 @ 0x3f 800ac0e: b2db uxtb r3, r3 800ac10: 2b09 cmp r3, #9 800ac12: f040 808f bne.w 800ad34 memcpy(&PSU_09, RxData, 8); 800ac16: 4b51 ldr r3, [pc, #324] @ (800ad5c ) 800ac18: 4a48 ldr r2, [pc, #288] @ (800ad3c ) 800ac1a: e892 0003 ldmia.w r2, {r0, r1} 800ac1e: e883 0003 stmia.w r3, {r0, r1} PSU_09.moduleNCurrent = PSU_09.moduleNCurrent_[3]; 800ac22: 4b4e ldr r3, [pc, #312] @ (800ad5c ) 800ac24: 79db ldrb r3, [r3, #7] 800ac26: 461a mov r2, r3 800ac28: 4b4c ldr r3, [pc, #304] @ (800ad5c ) 800ac2a: 60da str r2, [r3, #12] PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[2]<<8; 800ac2c: 4b4b ldr r3, [pc, #300] @ (800ad5c ) 800ac2e: 68da ldr r2, [r3, #12] 800ac30: 4b4a ldr r3, [pc, #296] @ (800ad5c ) 800ac32: 799b ldrb r3, [r3, #6] 800ac34: 021b lsls r3, r3, #8 800ac36: 4313 orrs r3, r2 800ac38: 4a48 ldr r2, [pc, #288] @ (800ad5c ) 800ac3a: 60d3 str r3, [r2, #12] PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[1]<<16; 800ac3c: 4b47 ldr r3, [pc, #284] @ (800ad5c ) 800ac3e: 68da ldr r2, [r3, #12] 800ac40: 4b46 ldr r3, [pc, #280] @ (800ad5c ) 800ac42: 795b ldrb r3, [r3, #5] 800ac44: 041b lsls r3, r3, #16 800ac46: 4313 orrs r3, r2 800ac48: 4a44 ldr r2, [pc, #272] @ (800ad5c ) 800ac4a: 60d3 str r3, [r2, #12] PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[0]<<24; 800ac4c: 4b43 ldr r3, [pc, #268] @ (800ad5c ) 800ac4e: 68da ldr r2, [r3, #12] 800ac50: 4b42 ldr r3, [pc, #264] @ (800ad5c ) 800ac52: 791b ldrb r3, [r3, #4] 800ac54: 061b lsls r3, r3, #24 800ac56: 4313 orrs r3, r2 800ac58: 4a40 ldr r2, [pc, #256] @ (800ad5c ) 800ac5a: 60d3 str r3, [r2, #12] PSU_09.moduleNVoltage = PSU_09.moduleNVoltage_[3]; 800ac5c: 4b3f ldr r3, [pc, #252] @ (800ad5c ) 800ac5e: 78db ldrb r3, [r3, #3] 800ac60: 461a mov r2, r3 800ac62: 4b3e ldr r3, [pc, #248] @ (800ad5c ) 800ac64: 609a str r2, [r3, #8] PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[2]<<8; 800ac66: 4b3d ldr r3, [pc, #244] @ (800ad5c ) 800ac68: 689a ldr r2, [r3, #8] 800ac6a: 4b3c ldr r3, [pc, #240] @ (800ad5c ) 800ac6c: 789b ldrb r3, [r3, #2] 800ac6e: 021b lsls r3, r3, #8 800ac70: 4313 orrs r3, r2 800ac72: 4a3a ldr r2, [pc, #232] @ (800ad5c ) 800ac74: 6093 str r3, [r2, #8] PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[1]<<16; 800ac76: 4b39 ldr r3, [pc, #228] @ (800ad5c ) 800ac78: 689a ldr r2, [r3, #8] 800ac7a: 4b38 ldr r3, [pc, #224] @ (800ad5c ) 800ac7c: 785b ldrb r3, [r3, #1] 800ac7e: 041b lsls r3, r3, #16 800ac80: 4313 orrs r3, r2 800ac82: 4a36 ldr r2, [pc, #216] @ (800ad5c ) 800ac84: 6093 str r3, [r2, #8] PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[0]<<24; 800ac86: 4b35 ldr r3, [pc, #212] @ (800ad5c ) 800ac88: 689a ldr r2, [r3, #8] 800ac8a: 4b34 ldr r3, [pc, #208] @ (800ad5c ) 800ac8c: 781b ldrb r3, [r3, #0] 800ac8e: 061b lsls r3, r3, #24 800ac90: 4313 orrs r3, r2 800ac92: 4a32 ldr r2, [pc, #200] @ (800ad5c ) 800ac94: 6093 str r3, [r2, #8] // PSU_09 -> PSU -> CONN (один модуль) { uint16_t v = PSU_09.moduleNVoltage / 1000; 800ac96: 4b31 ldr r3, [pc, #196] @ (800ad5c ) 800ac98: 689b ldr r3, [r3, #8] 800ac9a: 4a31 ldr r2, [pc, #196] @ (800ad60 ) 800ac9c: fba2 2303 umull r2, r3, r2, r3 800aca0: 099b lsrs r3, r3, #6 800aca2: 81fb strh r3, [r7, #14] int16_t i = PSU_09.moduleNCurrent / 100; 800aca4: 4b2d ldr r3, [pc, #180] @ (800ad5c ) 800aca6: 68db ldr r3, [r3, #12] 800aca8: 4a2e ldr r2, [pc, #184] @ (800ad64 ) 800acaa: fba2 2303 umull r2, r3, r2, r3 800acae: 095b lsrs r3, r3, #5 800acb0: 81bb strh r3, [r7, #12] // Обновляем модель PSU0 по телеметрии PSU0.outputVoltage = v; 800acb2: 4a27 ldr r2, [pc, #156] @ (800ad50 ) 800acb4: 89fb ldrh r3, [r7, #14] 800acb6: 8053 strh r3, [r2, #2] PSU0.outputCurrent = i; 800acb8: 4a25 ldr r2, [pc, #148] @ (800ad50 ) 800acba: 89bb ldrh r3, [r7, #12] 800acbc: 8093 strh r3, [r2, #4] PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800acbe: 89fb ldrh r3, [r7, #14] 800acc0: 2b13 cmp r3, #19 800acc2: bf8c ite hi 800acc4: 2301 movhi r3, #1 800acc6: 2300 movls r3, #0 800acc8: b2db uxtb r3, r3 800acca: 461a mov r2, r3 800accc: 4b20 ldr r3, [pc, #128] @ (800ad50 ) 800acce: 729a strb r2, [r3, #10] PSU0.online = 1; 800acd0: 4b1f ldr r3, [pc, #124] @ (800ad50 ) 800acd2: 2201 movs r2, #1 800acd4: 721a strb r2, [r3, #8] PSU0.temperature = PSU_04.moduleTemperature; 800acd6: 4b1d ldr r3, [pc, #116] @ (800ad4c ) 800acd8: 791a ldrb r2, [r3, #4] 800acda: 4b1d ldr r3, [pc, #116] @ (800ad50 ) 800acdc: 719a strb r2, [r3, #6] // Экспортируем значения из PSU0 в CONN только, // когда модуль хотя бы в состоянии READY и выше if(PSU0.state >= PSU_READY){ 800acde: 4b1c ldr r3, [pc, #112] @ (800ad50 ) 800ace0: 79db ldrb r3, [r3, #7] 800ace2: 2b01 cmp r3, #1 800ace4: d926 bls.n 800ad34 CONN.MeasuredVoltage = PSU0.outputVoltage; 800ace6: 4b1a ldr r3, [pc, #104] @ (800ad50 ) 800ace8: 885a ldrh r2, [r3, #2] 800acea: 4b1f ldr r3, [pc, #124] @ (800ad68 ) 800acec: f8a3 2013 strh.w r2, [r3, #19] CONN.MeasuredCurrent = PSU0.outputCurrent; 800acf0: 4b17 ldr r3, [pc, #92] @ (800ad50 ) 800acf2: f9b3 3004 ldrsh.w r3, [r3, #4] 800acf6: b29a uxth r2, r3 800acf8: 4b1b ldr r3, [pc, #108] @ (800ad68 ) 800acfa: f8a3 2015 strh.w r2, [r3, #21] CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800acfe: 4b1a ldr r3, [pc, #104] @ (800ad68 ) 800ad00: f8b3 3015 ldrh.w r3, [r3, #21] 800ad04: b29b uxth r3, r3 800ad06: 461a mov r2, r3 800ad08: 4b17 ldr r3, [pc, #92] @ (800ad68 ) 800ad0a: f8b3 3013 ldrh.w r3, [r3, #19] 800ad0e: b29b uxth r3, r3 800ad10: fb02 f303 mul.w r3, r2, r3 800ad14: 4a15 ldr r2, [pc, #84] @ (800ad6c ) 800ad16: fb82 1203 smull r1, r2, r2, r3 800ad1a: 1092 asrs r2, r2, #2 800ad1c: 17db asrs r3, r3, #31 800ad1e: 1ad3 subs r3, r2, r3 800ad20: 461a mov r2, r3 800ad22: 4b11 ldr r3, [pc, #68] @ (800ad68 ) 800ad24: f8c3 2003 str.w r2, [r3, #3] CONN.outputEnabled = PSU0.PSU_enabled; 800ad28: 4b09 ldr r3, [pc, #36] @ (800ad50 ) 800ad2a: 7a9a ldrb r2, [r3, #10] 800ad2c: 4b0e ldr r3, [pc, #56] @ (800ad68 ) 800ad2e: 761a strb r2, [r3, #24] 800ad30: e000 b.n 800ad34 if(CanId.source != 0) return; 800ad32: bf00 nop } } } } } 800ad34: 3710 adds r7, #16 800ad36: 46bd mov sp, r7 800ad38: bd80 pop {r7, pc} 800ad3a: bf00 nop 800ad3c: 20000768 .word 0x20000768 800ad40: 2000074c .word 0x2000074c 800ad44: 20000748 .word 0x20000748 800ad48: 200006e0 .word 0x200006e0 800ad4c: 200006ec .word 0x200006ec 800ad50: 20000724 .word 0x20000724 800ad54: 200006f8 .word 0x200006f8 800ad58: 2000070c .word 0x2000070c 800ad5c: 20000714 .word 0x20000714 800ad60: 10624dd3 .word 0x10624dd3 800ad64: 51eb851f .word 0x51eb851f 800ad68: 200001d4 .word 0x200001d4 800ad6c: 66666667 .word 0x66666667 0800ad70 : void PSU_CAN_FilterInit(){ 800ad70: b580 push {r7, lr} 800ad72: b08a sub sp, #40 @ 0x28 800ad74: af00 add r7, sp, #0 CAN_FilterTypeDef sFilterConfig; sFilterConfig.FilterBank = 14; 800ad76: 230e movs r3, #14 800ad78: 617b str r3, [r7, #20] sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; 800ad7a: 2300 movs r3, #0 800ad7c: 61bb str r3, [r7, #24] sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; 800ad7e: 2301 movs r3, #1 800ad80: 61fb str r3, [r7, #28] sFilterConfig.FilterIdHigh = 0x0000; 800ad82: 2300 movs r3, #0 800ad84: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = 0x0000; 800ad86: 2300 movs r3, #0 800ad88: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 800ad8a: 2300 movs r3, #0 800ad8c: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = 0x0000; 800ad8e: 2300 movs r3, #0 800ad90: 60fb str r3, [r7, #12] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; 800ad92: 2300 movs r3, #0 800ad94: 613b str r3, [r7, #16] sFilterConfig.FilterActivation = ENABLE; 800ad96: 2301 movs r3, #1 800ad98: 623b str r3, [r7, #32] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 800ad9a: 2301 movs r3, #1 800ad9c: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 800ad9e: 230e movs r3, #14 800ada0: 627b str r3, [r7, #36] @ 0x24 if(HAL_CAN_ConfigFilter(&hcan2, &sFilterConfig) != HAL_OK) 800ada2: 463b mov r3, r7 800ada4: 4619 mov r1, r3 800ada6: 4806 ldr r0, [pc, #24] @ (800adc0 ) 800ada8: f003 fbc4 bl 800e534 800adac: 4603 mov r3, r0 800adae: 2b00 cmp r3, #0 800adb0: d001 beq.n 800adb6 { Error_Handler(); 800adb2: f7ff fe1d bl 800a9f0 } } 800adb6: bf00 nop 800adb8: 3728 adds r7, #40 @ 0x28 800adba: 46bd mov sp, r7 800adbc: bd80 pop {r7, pc} 800adbe: bf00 nop 800adc0: 200001a8 .word 0x200001a8 0800adc4 : void PSU_Init(){ 800adc4: b580 push {r7, lr} 800adc6: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan2); 800adc8: 4813 ldr r0, [pc, #76] @ (800ae18 ) 800adca: f003 fcd7 bl 800e77c MX_CAN2_Init(); 800adce: f7fe fddf bl 8009990 PSU_CAN_FilterInit(); 800add2: f7ff ffcd bl 800ad70 HAL_CAN_Start(&hcan2); 800add6: 4810 ldr r0, [pc, #64] @ (800ae18 ) 800add8: f003 fc8c bl 800e6f4 HAL_CAN_ActivateNotification(&hcan2, CAN_IT_RX_FIFO1_MSG_PENDING /* | CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | CAN_IT_TX_MAILBOX_EMPTY*/); 800addc: 2110 movs r1, #16 800adde: 480e ldr r0, [pc, #56] @ (800ae18 ) 800ade0: f003 ff39 bl 800ec56 memset(&PSU0, 0, sizeof(PSU0)); 800ade4: 2224 movs r2, #36 @ 0x24 800ade6: 2100 movs r1, #0 800ade8: 480c ldr r0, [pc, #48] @ (800ae1c ) 800adea: f008 f8e5 bl 8012fb8 PSU0.state = PSU_UNREADY; 800adee: 4b0b ldr r3, [pc, #44] @ (800ae1c ) 800adf0: 2200 movs r2, #0 800adf2: 71da strb r2, [r3, #7] PSU0.statetick = HAL_GetTick(); 800adf4: f002 fd6e bl 800d8d4 800adf8: 4603 mov r3, r0 800adfa: 4a08 ldr r2, [pc, #32] @ (800ae1c ) 800adfc: 6113 str r3, [r2, #16] PSU0.power_limit = PSU_MAX_POWER; // kW 800adfe: 4b07 ldr r3, [pc, #28] @ (800ae1c ) 800ae00: f247 5230 movw r2, #30000 @ 0x7530 800ae04: 615a str r2, [r3, #20] PSU0.hv_mode = 0; 800ae06: 4b05 ldr r3, [pc, #20] @ (800ae1c ) 800ae08: 2200 movs r2, #0 800ae0a: 761a strb r2, [r3, #24] PSU_Enable(0, 0); 800ae0c: 2100 movs r1, #0 800ae0e: 2000 movs r0, #0 800ae10: f000 f806 bl 800ae20 } 800ae14: bf00 nop 800ae16: bd80 pop {r7, pc} 800ae18: 200001a8 .word 0x200001a8 800ae1c: 20000724 .word 0x20000724 0800ae20 : void PSU_Enable(uint8_t addr, uint8_t enable){ 800ae20: b580 push {r7, lr} 800ae22: b084 sub sp, #16 800ae24: af00 add r7, sp, #0 800ae26: 4603 mov r3, r0 800ae28: 460a mov r2, r1 800ae2a: 71fb strb r3, [r7, #7] 800ae2c: 4613 mov r3, r2 800ae2e: 71bb strb r3, [r7, #6] PSU_1A_t data; memset(&data, 0, sizeof(data)); 800ae30: f107 0308 add.w r3, r7, #8 800ae34: 2208 movs r2, #8 800ae36: 2100 movs r1, #0 800ae38: 4618 mov r0, r3 800ae3a: f008 f8bd bl 8012fb8 /* Для DC30 поддерживается только один модуль с адресом 0 */ if(addr != 0) return; 800ae3e: 79fb ldrb r3, [r7, #7] 800ae40: 2b00 cmp r3, #0 800ae42: d115 bne.n 800ae70 if(PSU0.online == 0) return; 800ae44: 4b0d ldr r3, [pc, #52] @ (800ae7c ) 800ae46: 7a1b ldrb r3, [r3, #8] 800ae48: 2b00 cmp r3, #0 800ae4a: d013 beq.n 800ae74 data.enable = !enable; 800ae4c: 79bb ldrb r3, [r7, #6] 800ae4e: 2b00 cmp r3, #0 800ae50: bf0c ite eq 800ae52: 2301 moveq r3, #1 800ae54: 2300 movne r3, #0 800ae56: b2db uxtb r3, r3 800ae58: 723b strb r3, [r7, #8] PSU_SendCmd(0xF0, addr, 0x1A, &data); 800ae5a: 79f9 ldrb r1, [r7, #7] 800ae5c: f107 0308 add.w r3, r7, #8 800ae60: 221a movs r2, #26 800ae62: 20f0 movs r0, #240 @ 0xf0 800ae64: f000 f866 bl 800af34 ED_Delay(CAN_DELAY); 800ae68: 2014 movs r0, #20 800ae6a: f7ff fc7d bl 800a768 800ae6e: e002 b.n 800ae76 if(addr != 0) return; 800ae70: bf00 nop 800ae72: e000 b.n 800ae76 if(PSU0.online == 0) return; 800ae74: bf00 nop } 800ae76: 3710 adds r7, #16 800ae78: 46bd mov sp, r7 800ae7a: bd80 pop {r7, pc} 800ae7c: 20000724 .word 0x20000724 0800ae80 : memset(&data, 0, sizeof(data)); data.enable = !enable; if(addr != 0) return; PSU_SendCmd(0xF0, addr, 0x1D, &data); } void PSU_SetVoltageCurrent(uint8_t addr, uint16_t voltage, uint16_t current){ 800ae80: b580 push {r7, lr} 800ae82: b086 sub sp, #24 800ae84: af00 add r7, sp, #0 800ae86: 4603 mov r3, r0 800ae88: 71fb strb r3, [r7, #7] 800ae8a: 460b mov r3, r1 800ae8c: 80bb strh r3, [r7, #4] 800ae8e: 4613 mov r3, r2 800ae90: 807b strh r3, [r7, #2] PSU_1C_t data; memset(&data, 0, sizeof(data)); 800ae92: f107 0308 add.w r3, r7, #8 800ae96: 2208 movs r2, #8 800ae98: 2100 movs r1, #0 800ae9a: 4618 mov r0, r3 800ae9c: f008 f88c bl 8012fb8 if(addr != 0) return; 800aea0: 79fb ldrb r3, [r7, #7] 800aea2: 2b00 cmp r3, #0 800aea4: d140 bne.n 800af28 if(voltage 800aeac: 2396 movs r3, #150 @ 0x96 800aeae: 80bb strh r3, [r7, #4] if((PSU0.hv_mode==0) && voltage>499) voltage = 499; 800aeb0: 4b1f ldr r3, [pc, #124] @ (800af30 ) 800aeb2: 7e1b ldrb r3, [r3, #24] 800aeb4: 2b00 cmp r3, #0 800aeb6: d106 bne.n 800aec6 800aeb8: 88bb ldrh r3, [r7, #4] 800aeba: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800aebe: d302 bcc.n 800aec6 800aec0: f240 13f3 movw r3, #499 @ 0x1f3 800aec4: 80bb strh r3, [r7, #4] uint32_t current_ma = current * 100; 800aec6: 887b ldrh r3, [r7, #2] 800aec8: 2264 movs r2, #100 @ 0x64 800aeca: fb02 f303 mul.w r3, r2, r3 800aece: 617b str r3, [r7, #20] uint32_t voltage_mv = voltage * 1000; 800aed0: 88bb ldrh r3, [r7, #4] 800aed2: f44f 727a mov.w r2, #1000 @ 0x3e8 800aed6: fb02 f303 mul.w r3, r2, r3 800aeda: 613b str r3, [r7, #16] data.moduleCurrentTotal[0] = (current_ma >> 24) & 0xFF; 800aedc: 697b ldr r3, [r7, #20] 800aede: 0e1b lsrs r3, r3, #24 800aee0: b2db uxtb r3, r3 800aee2: 733b strb r3, [r7, #12] data.moduleCurrentTotal[1] = (current_ma >> 16) & 0xFF; 800aee4: 697b ldr r3, [r7, #20] 800aee6: 0c1b lsrs r3, r3, #16 800aee8: b2db uxtb r3, r3 800aeea: 737b strb r3, [r7, #13] data.moduleCurrentTotal[2] = (current_ma >> 8) & 0xFF; 800aeec: 697b ldr r3, [r7, #20] 800aeee: 0a1b lsrs r3, r3, #8 800aef0: b2db uxtb r3, r3 800aef2: 73bb strb r3, [r7, #14] data.moduleCurrentTotal[3] = (current_ma >> 0) & 0xFF; 800aef4: 697b ldr r3, [r7, #20] 800aef6: b2db uxtb r3, r3 800aef8: 73fb strb r3, [r7, #15] data.moduleVoltage[0] = (voltage_mv >> 24) & 0xFF; 800aefa: 693b ldr r3, [r7, #16] 800aefc: 0e1b lsrs r3, r3, #24 800aefe: b2db uxtb r3, r3 800af00: 723b strb r3, [r7, #8] data.moduleVoltage[1] = (voltage_mv >> 16) & 0xFF; 800af02: 693b ldr r3, [r7, #16] 800af04: 0c1b lsrs r3, r3, #16 800af06: b2db uxtb r3, r3 800af08: 727b strb r3, [r7, #9] data.moduleVoltage[2] = (voltage_mv >> 8) & 0xFF; 800af0a: 693b ldr r3, [r7, #16] 800af0c: 0a1b lsrs r3, r3, #8 800af0e: b2db uxtb r3, r3 800af10: 72bb strb r3, [r7, #10] data.moduleVoltage[3] = (voltage_mv >> 0) & 0xFF; 800af12: 693b ldr r3, [r7, #16] 800af14: b2db uxtb r3, r3 800af16: 72fb strb r3, [r7, #11] PSU_SendCmd(0xF0, addr, 0x1C, &data); 800af18: 79f9 ldrb r1, [r7, #7] 800af1a: f107 0308 add.w r3, r7, #8 800af1e: 221c movs r2, #28 800af20: 20f0 movs r0, #240 @ 0xf0 800af22: f000 f807 bl 800af34 800af26: e000 b.n 800af2a if(addr != 0) return; 800af28: bf00 nop } 800af2a: 3718 adds r7, #24 800af2c: 46bd mov sp, r7 800af2e: bd80 pop {r7, pc} 800af30: 20000724 .word 0x20000724 0800af34 : void PSU_SendCmd(uint8_t source, uint8_t destination, uint8_t cmd, void *data){ 800af34: b580 push {r7, lr} 800af36: b08c sub sp, #48 @ 0x30 800af38: af00 add r7, sp, #0 800af3a: 603b str r3, [r7, #0] 800af3c: 4603 mov r3, r0 800af3e: 71fb strb r3, [r7, #7] 800af40: 460b mov r3, r1 800af42: 71bb strb r3, [r7, #6] 800af44: 4613 mov r3, r2 800af46: 717b strb r3, [r7, #5] CanId_t CanId; CanId.source = source; 800af48: 79fb ldrb r3, [r7, #7] 800af4a: f887 3028 strb.w r3, [r7, #40] @ 0x28 CanId.destination = destination; 800af4e: 79bb ldrb r3, [r7, #6] 800af50: f887 3029 strb.w r3, [r7, #41] @ 0x29 CanId.command = cmd; 800af54: 797b ldrb r3, [r7, #5] 800af56: f003 033f and.w r3, r3, #63 @ 0x3f 800af5a: b2da uxtb r2, r3 800af5c: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 800af60: f362 0305 bfi r3, r2, #0, #6 800af64: f887 302a strb.w r3, [r7, #42] @ 0x2a CanId.device = 0x0A; 800af68: 8d7b ldrh r3, [r7, #42] @ 0x2a 800af6a: 220a movs r2, #10 800af6c: f362 1389 bfi r3, r2, #6, #4 800af70: 857b strh r3, [r7, #42] @ 0x2a int8_t retry_counter = 10; 800af72: 230a movs r3, #10 800af74: f887 302f strb.w r3, [r7, #47] @ 0x2f CAN_TxHeaderTypeDef tx_header; uint32_t tx_mailbox; HAL_StatusTypeDef CAN_result; memcpy(&tx_header.ExtId, &CanId, sizeof(CanId_t)); 800af78: 6abb ldr r3, [r7, #40] @ 0x28 800af7a: 617b str r3, [r7, #20] tx_header.RTR = CAN_RTR_DATA; 800af7c: 2300 movs r3, #0 800af7e: 61fb str r3, [r7, #28] tx_header.IDE = CAN_ID_EXT; 800af80: 2304 movs r3, #4 800af82: 61bb str r3, [r7, #24] tx_header.DLC = 8; 800af84: 2308 movs r3, #8 800af86: 623b str r3, [r7, #32] while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800af88: e01e b.n 800afc8 if (HAL_CAN_GetTxMailboxesFreeLevel(&hcan2) > 0){ 800af8a: 4814 ldr r0, [pc, #80] @ (800afdc ) 800af8c: f003 fd0e bl 800e9ac 800af90: 4603 mov r3, r0 800af92: 2b00 cmp r3, #0 800af94: d00e beq.n 800afb4 /* отправка сообщения */ CAN_result = HAL_CAN_AddTxMessage(&hcan2, &tx_header, (uint8_t*)data, &tx_mailbox); 800af96: f107 030c add.w r3, r7, #12 800af9a: f107 0110 add.w r1, r7, #16 800af9e: 683a ldr r2, [r7, #0] 800afa0: 480e ldr r0, [pc, #56] @ (800afdc ) 800afa2: f003 fc34 bl 800e80e 800afa6: 4603 mov r3, r0 800afa8: f887 302e strb.w r3, [r7, #46] @ 0x2e /* если отправка удалась, выход */ if(CAN_result == HAL_OK) { 800afac: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 800afb0: 2b00 cmp r3, #0 800afb2: d00e beq.n 800afd2 return; retry_counter = 0; } } ED_Delay(1); 800afb4: 2001 movs r0, #1 800afb6: f7ff fbd7 bl 800a768 retry_counter--; 800afba: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800afbe: b2db uxtb r3, r3 800afc0: 3b01 subs r3, #1 800afc2: b2db uxtb r3, r3 800afc4: f887 302f strb.w r3, [r7, #47] @ 0x2f while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800afc8: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800afcc: 2b00 cmp r3, #0 800afce: dcdc bgt.n 800af8a 800afd0: e000 b.n 800afd4 return; 800afd2: bf00 nop } } 800afd4: 3730 adds r7, #48 @ 0x30 800afd6: 46bd mov sp, r7 800afd8: bd80 pop {r7, pc} 800afda: bf00 nop 800afdc: 200001a8 .word 0x200001a8 0800afe0 : uint32_t max(uint32_t a, uint32_t b){ if(a>b) return a; else return b; } void PSU_ReadWrite(){ 800afe0: b580 push {r7, lr} 800afe2: b082 sub sp, #8 800afe4: af00 add r7, sp, #0 uint8_t zero_data[8] = {0,0,0,0,0,0,0,0}; 800afe6: 463b mov r3, r7 800afe8: 2200 movs r2, #0 800afea: 601a str r2, [r3, #0] 800afec: 605a str r2, [r3, #4] PSU_SendCmd(0xF0, 0, 0x04, zero_data);ED_Delay(CAN_DELAY); 800afee: 463b mov r3, r7 800aff0: 2204 movs r2, #4 800aff2: 2100 movs r1, #0 800aff4: 20f0 movs r0, #240 @ 0xf0 800aff6: f7ff ff9d bl 800af34 800affa: 2014 movs r0, #20 800affc: f7ff fbb4 bl 800a768 PSU_SendCmd(0xF0, 0, 0x06, zero_data);ED_Delay(CAN_DELAY); 800b000: 463b mov r3, r7 800b002: 2206 movs r2, #6 800b004: 2100 movs r1, #0 800b006: 20f0 movs r0, #240 @ 0xf0 800b008: f7ff ff94 bl 800af34 800b00c: 2014 movs r0, #20 800b00e: f7ff fbab bl 800a768 // PSU_SendCmd(0xF0, 0, 0x08, zero_data);ED_Delay(CAN_DELAY); PSU_SendCmd(0xF0, 0, 0x09, zero_data);ED_Delay(CAN_DELAY); 800b012: 463b mov r3, r7 800b014: 2209 movs r2, #9 800b016: 2100 movs r1, #0 800b018: 20f0 movs r0, #240 @ 0xf0 800b01a: f7ff ff8b bl 800af34 800b01e: 2014 movs r0, #20 800b020: f7ff fba2 bl 800a768 // Power Limit if ((CONN.WantedCurrent/10) * CONN.MeasuredVoltage > PSU0.power_limit){ 800b024: 4b3a ldr r3, [pc, #232] @ (800b110 ) 800b026: f8b3 301b ldrh.w r3, [r3, #27] 800b02a: b29b uxth r3, r3 800b02c: 4a39 ldr r2, [pc, #228] @ (800b114 ) 800b02e: fba2 2303 umull r2, r3, r2, r3 800b032: 08db lsrs r3, r3, #3 800b034: b29b uxth r3, r3 800b036: 461a mov r2, r3 800b038: 4b35 ldr r3, [pc, #212] @ (800b110 ) 800b03a: f8b3 3013 ldrh.w r3, [r3, #19] 800b03e: b29b uxth r3, r3 800b040: fb02 f303 mul.w r3, r2, r3 800b044: 461a mov r2, r3 800b046: 4b34 ldr r3, [pc, #208] @ (800b118 ) 800b048: 695b ldr r3, [r3, #20] 800b04a: 429a cmp r2, r3 800b04c: d911 bls.n 800b072 CONN.RequestedCurrent = PSU0.power_limit * 10 / CONN.MeasuredVoltage; 800b04e: 4b32 ldr r3, [pc, #200] @ (800b118 ) 800b050: 695a ldr r2, [r3, #20] 800b052: 4613 mov r3, r2 800b054: 009b lsls r3, r3, #2 800b056: 4413 add r3, r2 800b058: 005b lsls r3, r3, #1 800b05a: 461a mov r2, r3 800b05c: 4b2c ldr r3, [pc, #176] @ (800b110 ) 800b05e: f8b3 3013 ldrh.w r3, [r3, #19] 800b062: b29b uxth r3, r3 800b064: fbb2 f3f3 udiv r3, r2, r3 800b068: b29a uxth r2, r3 800b06a: 4b29 ldr r3, [pc, #164] @ (800b110 ) 800b06c: f8a3 2011 strh.w r2, [r3, #17] 800b070: e006 b.n 800b080 }else{ CONN.RequestedCurrent = CONN.WantedCurrent; 800b072: 4b27 ldr r3, [pc, #156] @ (800b110 ) 800b074: f8b3 301b ldrh.w r3, [r3, #27] 800b078: b29a uxth r2, r3 800b07a: 4b25 ldr r3, [pc, #148] @ (800b110 ) 800b07c: f8a3 2011 strh.w r2, [r3, #17] } if(CONN.RequestedCurrent > (PSU_MAX_CURRENT*10)){ 800b080: 4b23 ldr r3, [pc, #140] @ (800b110 ) 800b082: f8b3 3011 ldrh.w r3, [r3, #17] 800b086: b29b uxth r3, r3 800b088: f240 5232 movw r2, #1330 @ 0x532 800b08c: 4293 cmp r3, r2 800b08e: d908 bls.n 800b0a2 CONN.RequestedCurrent = PSU_MAX_CURRENT*10; 800b090: 4b1f ldr r3, [pc, #124] @ (800b110 ) 800b092: 2200 movs r2, #0 800b094: f042 0232 orr.w r2, r2, #50 @ 0x32 800b098: 745a strb r2, [r3, #17] 800b09a: 2200 movs r2, #0 800b09c: f042 0205 orr.w r2, r2, #5 800b0a0: 749a strb r2, [r3, #18] } CONN.RequestedPower = CONN.RequestedCurrent * CONN.RequestedVoltage / 10; 800b0a2: 4b1b ldr r3, [pc, #108] @ (800b110 ) 800b0a4: f8b3 3011 ldrh.w r3, [r3, #17] 800b0a8: b29b uxth r3, r3 800b0aa: 461a mov r2, r3 800b0ac: 4b18 ldr r3, [pc, #96] @ (800b110 ) 800b0ae: f8b3 300f ldrh.w r3, [r3, #15] 800b0b2: b29b uxth r3, r3 800b0b4: fb02 f303 mul.w r3, r2, r3 800b0b8: 4a18 ldr r2, [pc, #96] @ (800b11c ) 800b0ba: fb82 1203 smull r1, r2, r2, r3 800b0be: 1092 asrs r2, r2, #2 800b0c0: 17db asrs r3, r3, #31 800b0c2: 1ad3 subs r3, r2, r3 800b0c4: 461a mov r2, r3 800b0c6: 4b12 ldr r3, [pc, #72] @ (800b110 ) 800b0c8: f8c3 200b str.w r2, [r3, #11] if(PSU0.ready){ 800b0cc: 4b12 ldr r3, [pc, #72] @ (800b118 ) 800b0ce: 7a5b ldrb r3, [r3, #9] 800b0d0: 2b00 cmp r3, #0 800b0d2: d018 beq.n 800b106 PSU_SetVoltageCurrent(0, CONN.RequestedVoltage, CONN.RequestedCurrent); // Normal mode 800b0d4: 4b0e ldr r3, [pc, #56] @ (800b110 ) 800b0d6: f8b3 300f ldrh.w r3, [r3, #15] 800b0da: b29b uxth r3, r3 800b0dc: 4a0c ldr r2, [pc, #48] @ (800b110 ) 800b0de: f8b2 2011 ldrh.w r2, [r2, #17] 800b0e2: b292 uxth r2, r2 800b0e4: 4619 mov r1, r3 800b0e6: 2000 movs r0, #0 800b0e8: f7ff feca bl 800ae80 ED_Delay(CAN_DELAY); 800b0ec: 2014 movs r0, #20 800b0ee: f7ff fb3b bl 800a768 if(CONN.MeasuredVoltage>490) PSU0.hv_mode = 1; 800b0f2: 4b07 ldr r3, [pc, #28] @ (800b110 ) 800b0f4: f8b3 3013 ldrh.w r3, [r3, #19] 800b0f8: b29b uxth r3, r3 800b0fa: f5b3 7ff5 cmp.w r3, #490 @ 0x1ea 800b0fe: d902 bls.n 800b106 800b100: 4b05 ldr r3, [pc, #20] @ (800b118 ) 800b102: 2201 movs r2, #1 800b104: 761a strb r2, [r3, #24] } // PSU_SetHVMode(0, PSU0.hv_mode); // auto set, no need // ED_Delay(CAN_DELAY); } 800b106: bf00 nop 800b108: 3708 adds r7, #8 800b10a: 46bd mov sp, r7 800b10c: bd80 pop {r7, pc} 800b10e: bf00 nop 800b110: 200001d4 .word 0x200001d4 800b114: cccccccd .word 0xcccccccd 800b118: 20000724 .word 0x20000724 800b11c: 66666667 .word 0x66666667 0800b120 : void PSU_Task(void){ 800b120: b598 push {r3, r4, r7, lr} 800b122: af00 add r7, sp, #0 static uint32_t psu_on_tick = 0; static uint32_t dc_on_tick = 0; static uint32_t cont_ok_tick = 0; // Обновляем ONLINE/READY по таймауту if((HAL_GetTick() - can_lastpacket) > PSU_ONLINE_TIMEOUT){ 800b124: f002 fbd6 bl 800d8d4 800b128: 4602 mov r2, r0 800b12a: 4bb4 ldr r3, [pc, #720] @ (800b3fc ) 800b12c: 681b ldr r3, [r3, #0] 800b12e: 1ad3 subs r3, r2, r3 800b130: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b134: d920 bls.n 800b178 PSU0.online = 0; 800b136: 4bb2 ldr r3, [pc, #712] @ (800b400 ) 800b138: 2200 movs r2, #0 800b13a: 721a strb r2, [r3, #8] PSU0.PSU_enabled = 0; 800b13c: 4bb0 ldr r3, [pc, #704] @ (800b400 ) 800b13e: 2200 movs r2, #0 800b140: 729a strb r2, [r3, #10] PSU_04.moduleTemperature = 0; 800b142: 4bb0 ldr r3, [pc, #704] @ (800b404 ) 800b144: 2200 movs r2, #0 800b146: 711a strb r2, [r3, #4] PSU_04.modularForm0 = 0; 800b148: 4bae ldr r3, [pc, #696] @ (800b404 ) 800b14a: 2200 movs r2, #0 800b14c: 721a strb r2, [r3, #8] PSU_04.modularForm1 = 0; 800b14e: 4bad ldr r3, [pc, #692] @ (800b404 ) 800b150: 2200 movs r2, #0 800b152: 71da strb r2, [r3, #7] PSU_04.modularForm2 = 0; 800b154: 4bab ldr r3, [pc, #684] @ (800b404 ) 800b156: 2200 movs r2, #0 800b158: 719a strb r2, [r3, #6] PSU_06.VAB = 0; 800b15a: 4bab ldr r3, [pc, #684] @ (800b408 ) 800b15c: 2200 movs r2, #0 800b15e: 609a str r2, [r3, #8] PSU_06.VBC = 0; 800b160: 4ba9 ldr r3, [pc, #676] @ (800b408 ) 800b162: 2200 movs r2, #0 800b164: 60da str r2, [r3, #12] PSU_06.VCA = 0; 800b166: 4ba8 ldr r3, [pc, #672] @ (800b408 ) 800b168: 2200 movs r2, #0 800b16a: 611a str r2, [r3, #16] PSU_09.moduleNCurrent = 0; 800b16c: 4ba7 ldr r3, [pc, #668] @ (800b40c ) 800b16e: 2200 movs r2, #0 800b170: 60da str r2, [r3, #12] PSU_09.moduleNVoltage = 0; 800b172: 4ba6 ldr r3, [pc, #664] @ (800b40c ) 800b174: 2200 movs r2, #0 800b176: 609a str r2, [r3, #8] } if(!PSU0.online || !PSU0.enableAC){ 800b178: 4ba1 ldr r3, [pc, #644] @ (800b400 ) 800b17a: 7a1b ldrb r3, [r3, #8] 800b17c: 2b00 cmp r3, #0 800b17e: d003 beq.n 800b188 800b180: 4b9f ldr r3, [pc, #636] @ (800b400 ) 800b182: 781b ldrb r3, [r3, #0] 800b184: 2b00 cmp r3, #0 800b186: d10c bne.n 800b1a2 CONN.MeasuredVoltage = 0; 800b188: 4ba1 ldr r3, [pc, #644] @ (800b410 ) 800b18a: 2200 movs r2, #0 800b18c: 74da strb r2, [r3, #19] 800b18e: 2200 movs r2, #0 800b190: 751a strb r2, [r3, #20] CONN.MeasuredCurrent = 0; 800b192: 4b9f ldr r3, [pc, #636] @ (800b410 ) 800b194: 2200 movs r2, #0 800b196: 755a strb r2, [r3, #21] 800b198: 2200 movs r2, #0 800b19a: 759a strb r2, [r3, #22] CONN.outputEnabled = 0; 800b19c: 4b9c ldr r3, [pc, #624] @ (800b410 ) 800b19e: 2200 movs r2, #0 800b1a0: 761a strb r2, [r3, #24] } // Управление AC-контактором с задержкой отключения 1 минута if(CONN.EvConnected){ 800b1a2: 4b9b ldr r3, [pc, #620] @ (800b410 ) 800b1a4: 7f9b ldrb r3, [r3, #30] 800b1a6: 2b00 cmp r3, #0 800b1a8: d00c beq.n 800b1c4 RELAY_Write(RELAY_AC, 1); 800b1aa: 2101 movs r1, #1 800b1ac: 2004 movs r0, #4 800b1ae: f7fe f97f bl 80094b0 psu_on_tick = HAL_GetTick(); 800b1b2: f002 fb8f bl 800d8d4 800b1b6: 4603 mov r3, r0 800b1b8: 4a96 ldr r2, [pc, #600] @ (800b414 ) 800b1ba: 6013 str r3, [r2, #0] PSU0.enableAC = 1; 800b1bc: 4b90 ldr r3, [pc, #576] @ (800b400 ) 800b1be: 2201 movs r2, #1 800b1c0: 701a strb r2, [r3, #0] 800b1c2: e010 b.n 800b1e6 }else{ if((HAL_GetTick() - psu_on_tick) > 1 * 60000){ 800b1c4: f002 fb86 bl 800d8d4 800b1c8: 4602 mov r2, r0 800b1ca: 4b92 ldr r3, [pc, #584] @ (800b414 ) 800b1cc: 681b ldr r3, [r3, #0] 800b1ce: 1ad3 subs r3, r2, r3 800b1d0: f64e 2260 movw r2, #60000 @ 0xea60 800b1d4: 4293 cmp r3, r2 800b1d6: d906 bls.n 800b1e6 RELAY_Write(RELAY_AC, 0); 800b1d8: 2100 movs r1, #0 800b1da: 2004 movs r0, #4 800b1dc: f7fe f968 bl 80094b0 PSU0.enableAC = 0; 800b1e0: 4b87 ldr r3, [pc, #540] @ (800b400 ) 800b1e2: 2200 movs r2, #0 800b1e4: 701a strb r2, [r3, #0] } } // Текущее состояние DC-контактора по обратной связи PSU0.CONT_enabled = IN_ReadInput(IN_CONT_FB_DC); 800b1e6: 2005 movs r0, #5 800b1e8: f7fe f9e2 bl 80095b0 800b1ec: 4603 mov r3, r0 800b1ee: 461a mov r2, r3 800b1f0: 4b83 ldr r3, [pc, #524] @ (800b400 ) 800b1f2: 72da strb r2, [r3, #11] // Обновляем ready с учётом ошибок if(PSU0.online && !PSU0.cont_fault && PSU0.enableAC){ 800b1f4: 4b82 ldr r3, [pc, #520] @ (800b400 ) 800b1f6: 7a1b ldrb r3, [r3, #8] 800b1f8: 2b00 cmp r3, #0 800b1fa: d007 beq.n 800b20c 800b1fc: 4b80 ldr r3, [pc, #512] @ (800b400 ) 800b1fe: 7b1b ldrb r3, [r3, #12] 800b200: 2b00 cmp r3, #0 800b202: d103 bne.n 800b20c 800b204: 4b7e ldr r3, [pc, #504] @ (800b400 ) 800b206: 781b ldrb r3, [r3, #0] 800b208: 2b00 cmp r3, #0 800b20a: d102 bne.n 800b212 // PSU0.ready = 1; }else{ PSU0.ready = 0; 800b20c: 4b7c ldr r3, [pc, #496] @ (800b400 ) 800b20e: 2200 movs r2, #0 800b210: 725a strb r2, [r3, #9] } switch(PSU0.state){ 800b212: 4b7b ldr r3, [pc, #492] @ (800b400 ) 800b214: 79db ldrb r3, [r3, #7] 800b216: 2b09 cmp r3, #9 800b218: f200 8155 bhi.w 800b4c6 800b21c: a201 add r2, pc, #4 @ (adr r2, 800b224 ) 800b21e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b222: bf00 nop 800b224: 0800b24d .word 0x0800b24d 800b228: 0800b281 .word 0x0800b281 800b22c: 0800b29d .word 0x0800b29d 800b230: 0800b2d5 .word 0x0800b2d5 800b234: 0800b323 .word 0x0800b323 800b238: 0800b365 .word 0x0800b365 800b23c: 0800b3cf .word 0x0800b3cf 800b240: 0800b479 .word 0x0800b479 800b244: 0800b429 .word 0x0800b429 800b248: 0800b4b3 .word 0x0800b4b3 case PSU_UNREADY: PSU0.enableOutput = 0; 800b24c: 4b6c ldr r3, [pc, #432] @ (800b400 ) 800b24e: 2200 movs r2, #0 800b250: 705a strb r2, [r3, #1] RELAY_Write(RELAY_DC, 0); 800b252: 2100 movs r1, #0 800b254: 2003 movs r0, #3 800b256: f7fe f92b bl 80094b0 if(PSU0.online && PSU0.enableAC && !PSU0.cont_fault){ 800b25a: 4b69 ldr r3, [pc, #420] @ (800b400 ) 800b25c: 7a1b ldrb r3, [r3, #8] 800b25e: 2b00 cmp r3, #0 800b260: f000 8135 beq.w 800b4ce 800b264: 4b66 ldr r3, [pc, #408] @ (800b400 ) 800b266: 781b ldrb r3, [r3, #0] 800b268: 2b00 cmp r3, #0 800b26a: f000 8130 beq.w 800b4ce 800b26e: 4b64 ldr r3, [pc, #400] @ (800b400 ) 800b270: 7b1b ldrb r3, [r3, #12] 800b272: 2b00 cmp r3, #0 800b274: f040 812b bne.w 800b4ce PSU_SwitchState(PSU_INITIALIZING); 800b278: 2001 movs r0, #1 800b27a: f7ff fc29 bl 800aad0 } break; 800b27e: e126 b.n 800b4ce case PSU_INITIALIZING: if(PSU_StateTime() > 4000){ // Wait 4s for PSU to initialize 800b280: f7ff fc3a bl 800aaf8 800b284: 4603 mov r3, r0 800b286: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b28a: f240 8122 bls.w 800b4d2 PSU0.ready = 1; 800b28e: 4b5c ldr r3, [pc, #368] @ (800b400 ) 800b290: 2201 movs r2, #1 800b292: 725a strb r2, [r3, #9] PSU_SwitchState(PSU_READY); 800b294: 2002 movs r0, #2 800b296: f7ff fc1b bl 800aad0 } break; 800b29a: e11a b.n 800b4d2 case PSU_READY: // модуль готов, но выключен PSU0.hv_mode = 0; 800b29c: 4b58 ldr r3, [pc, #352] @ (800b400 ) 800b29e: 2200 movs r2, #0 800b2a0: 761a strb r2, [r3, #24] RELAY_Write(RELAY_DC, 0); 800b2a2: 2100 movs r1, #0 800b2a4: 2003 movs r0, #3 800b2a6: f7fe f903 bl 80094b0 if(!PSU0.ready){ 800b2aa: 4b55 ldr r3, [pc, #340] @ (800b400 ) 800b2ac: 7a5b ldrb r3, [r3, #9] 800b2ae: 2b00 cmp r3, #0 800b2b0: d103 bne.n 800b2ba PSU_SwitchState(PSU_UNREADY); 800b2b2: 2000 movs r0, #0 800b2b4: f7ff fc0c bl 800aad0 break; 800b2b8: e11c b.n 800b4f4 } if(CONN.EnableOutput){ 800b2ba: 4b55 ldr r3, [pc, #340] @ (800b410 ) 800b2bc: 7ddb ldrb r3, [r3, #23] 800b2be: 2b00 cmp r3, #0 800b2c0: f000 8109 beq.w 800b4d6 PSU_Enable(0, 1); 800b2c4: 2101 movs r1, #1 800b2c6: 2000 movs r0, #0 800b2c8: f7ff fdaa bl 800ae20 PSU_SwitchState(PSU_WAIT_ACK_ON); 800b2cc: 2003 movs r0, #3 800b2ce: f7ff fbff bl 800aad0 } break; 800b2d2: e100 b.n 800b4d6 case PSU_WAIT_ACK_ON: if(PSU0.PSU_enabled && PSU0.ready){ 800b2d4: 4b4a ldr r3, [pc, #296] @ (800b400 ) 800b2d6: 7a9b ldrb r3, [r3, #10] 800b2d8: 2b00 cmp r3, #0 800b2da: d00c beq.n 800b2f6 800b2dc: 4b48 ldr r3, [pc, #288] @ (800b400 ) 800b2de: 7a5b ldrb r3, [r3, #9] 800b2e0: 2b00 cmp r3, #0 800b2e2: d008 beq.n 800b2f6 dc_on_tick = HAL_GetTick(); 800b2e4: f002 faf6 bl 800d8d4 800b2e8: 4603 mov r3, r0 800b2ea: 4a4b ldr r2, [pc, #300] @ (800b418 ) 800b2ec: 6013 str r3, [r2, #0] PSU_SwitchState(PSU_CONT_WAIT_ACK_ON); 800b2ee: 2004 movs r0, #4 800b2f0: f7ff fbee bl 800aad0 PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU on timeout\n"); } break; 800b2f4: e0f1 b.n 800b4da }else if(PSU_StateTime() > 10000){ 800b2f6: f7ff fbff bl 800aaf8 800b2fa: 4603 mov r3, r0 800b2fc: f242 7210 movw r2, #10000 @ 0x2710 800b300: 4293 cmp r3, r2 800b302: f240 80ea bls.w 800b4da PSU0.psu_fault = 1; 800b306: 4b3e ldr r3, [pc, #248] @ (800b400 ) 800b308: 2201 movs r2, #1 800b30a: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b30c: 4b40 ldr r3, [pc, #256] @ (800b410 ) 800b30e: 220a movs r2, #10 800b310: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b312: 2000 movs r0, #0 800b314: f7ff fbdc bl 800aad0 log_printf(LOG_ERR, "PSU on timeout\n"); 800b318: 4940 ldr r1, [pc, #256] @ (800b41c ) 800b31a: 2004 movs r0, #4 800b31c: f7ff f8a8 bl 800a470 break; 800b320: e0db b.n 800b4da case PSU_CONT_WAIT_ACK_ON: // замыкаем DC-контактор и ждём подтверждение RELAY_Write(RELAY_DC, 1); 800b322: 2101 movs r1, #1 800b324: 2003 movs r0, #3 800b326: f7fe f8c3 bl 80094b0 if(PSU0.CONT_enabled){ 800b32a: 4b35 ldr r3, [pc, #212] @ (800b400 ) 800b32c: 7adb ldrb r3, [r3, #11] 800b32e: 2b00 cmp r3, #0 800b330: d003 beq.n 800b33a PSU_SwitchState(PSU_CONNECTED); 800b332: 2005 movs r0, #5 800b334: f7ff fbcc bl 800aad0 PSU0.cont_fault = 1; CONN.chargingError = CONN_ERR_CONTACTOR; PSU_SwitchState(PSU_CURRENT_DROP); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b338: e0d1 b.n 800b4de }else if(PSU_StateTime() > 1000){ 800b33a: f7ff fbdd bl 800aaf8 800b33e: 4603 mov r3, r0 800b340: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b344: f240 80cb bls.w 800b4de PSU0.cont_fault = 1; 800b348: 4b2d ldr r3, [pc, #180] @ (800b400 ) 800b34a: 2201 movs r2, #1 800b34c: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b34e: 4b30 ldr r3, [pc, #192] @ (800b410 ) 800b350: 2207 movs r2, #7 800b352: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_CURRENT_DROP); 800b354: 2006 movs r0, #6 800b356: f7ff fbbb bl 800aad0 log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b35a: 4931 ldr r1, [pc, #196] @ (800b420 ) 800b35c: 2004 movs r0, #4 800b35e: f7ff f887 bl 800a470 break; 800b362: e0bc b.n 800b4de case PSU_CONNECTED: // Основное рабочее состояние if(!CONN.EnableOutput || !PSU0.ready){ 800b364: 4b2a ldr r3, [pc, #168] @ (800b410 ) 800b366: 7ddb ldrb r3, [r3, #23] 800b368: 2b00 cmp r3, #0 800b36a: d003 beq.n 800b374 800b36c: 4b24 ldr r3, [pc, #144] @ (800b400 ) 800b36e: 7a5b ldrb r3, [r3, #9] 800b370: 2b00 cmp r3, #0 800b372: d103 bne.n 800b37c PSU_SwitchState(PSU_CURRENT_DROP); 800b374: 2006 movs r0, #6 800b376: f7ff fbab bl 800aad0 break; 800b37a: e0bb b.n 800b4f4 } // контроль контактора: 1 c таймаут if (IN_ReadInput(IN_CONT_FB_DC) != RELAY_Read(RELAY_DC)){ 800b37c: 2005 movs r0, #5 800b37e: f7fe f917 bl 80095b0 800b382: 4603 mov r3, r0 800b384: 461c mov r4, r3 800b386: 2003 movs r0, #3 800b388: f7fe f902 bl 8009590 800b38c: 4603 mov r3, r0 800b38e: 429c cmp r4, r3 800b390: d017 beq.n 800b3c2 if((HAL_GetTick() - cont_ok_tick) > 1000){ 800b392: f002 fa9f bl 800d8d4 800b396: 4602 mov r2, r0 800b398: 4b22 ldr r3, [pc, #136] @ (800b424 ) 800b39a: 681b ldr r3, [r3, #0] 800b39c: 1ad3 subs r3, r2, r3 800b39e: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b3a2: f240 809e bls.w 800b4e2 CONN.chargingError = CONN_ERR_CONTACTOR; 800b3a6: 4b1a ldr r3, [pc, #104] @ (800b410 ) 800b3a8: 2207 movs r2, #7 800b3aa: 775a strb r2, [r3, #29] PSU0.cont_fault = 1; 800b3ac: 4b14 ldr r3, [pc, #80] @ (800b400 ) 800b3ae: 2201 movs r2, #1 800b3b0: 731a strb r2, [r3, #12] PSU_SwitchState(PSU_CURRENT_DROP); 800b3b2: 2006 movs r0, #6 800b3b4: f7ff fb8c bl 800aad0 log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b3b8: 4919 ldr r1, [pc, #100] @ (800b420 ) 800b3ba: 2004 movs r0, #4 800b3bc: f7ff f858 bl 800a470 } }else{ cont_ok_tick = HAL_GetTick(); } break; 800b3c0: e08f b.n 800b4e2 cont_ok_tick = HAL_GetTick(); 800b3c2: f002 fa87 bl 800d8d4 800b3c6: 4603 mov r3, r0 800b3c8: 4a16 ldr r2, [pc, #88] @ (800b424 ) 800b3ca: 6013 str r3, [r2, #0] break; 800b3cc: e089 b.n 800b4e2 case PSU_CURRENT_DROP: // снижаем ток до нуля перед отключением DC CONN.RequestedCurrent = 0; 800b3ce: 4b10 ldr r3, [pc, #64] @ (800b410 ) 800b3d0: 2200 movs r2, #0 800b3d2: 745a strb r2, [r3, #17] 800b3d4: 2200 movs r2, #0 800b3d6: 749a strb r2, [r3, #18] // если ток действительно упал или вышло время, отключаем DC if((CONN.MeasuredCurrent < 30) || (PSU_StateTime() > 5000)){ 800b3d8: 4b0d ldr r3, [pc, #52] @ (800b410 ) 800b3da: f8b3 3015 ldrh.w r3, [r3, #21] 800b3de: b29b uxth r3, r3 800b3e0: 2b1d cmp r3, #29 800b3e2: d906 bls.n 800b3f2 800b3e4: f7ff fb88 bl 800aaf8 800b3e8: 4603 mov r3, r0 800b3ea: f241 3288 movw r2, #5000 @ 0x1388 800b3ee: 4293 cmp r3, r2 800b3f0: d979 bls.n 800b4e6 PSU_SwitchState(PSU_CONT_WAIT_ACK_OFF); 800b3f2: 2008 movs r0, #8 800b3f4: f7ff fb6c bl 800aad0 } break; 800b3f8: e075 b.n 800b4e6 800b3fa: bf00 nop 800b3fc: 20000748 .word 0x20000748 800b400: 20000724 .word 0x20000724 800b404: 200006ec .word 0x200006ec 800b408: 200006f8 .word 0x200006f8 800b40c: 20000714 .word 0x20000714 800b410: 200001d4 .word 0x200001d4 800b414: 20000770 .word 0x20000770 800b418: 20000774 .word 0x20000774 800b41c: 08014184 .word 0x08014184 800b420: 08014194 .word 0x08014194 800b424: 20000778 .word 0x20000778 case PSU_CONT_WAIT_ACK_OFF: RELAY_Write(RELAY_DC, 0); 800b428: 2100 movs r1, #0 800b42a: 2003 movs r0, #3 800b42c: f7fe f840 bl 80094b0 if(!PSU0.CONT_enabled){ 800b430: 4b31 ldr r3, [pc, #196] @ (800b4f8 ) 800b432: 7adb ldrb r3, [r3, #11] 800b434: 2b00 cmp r3, #0 800b436: d107 bne.n 800b448 PSU_Enable(0, 0); 800b438: 2100 movs r1, #0 800b43a: 2000 movs r0, #0 800b43c: f7ff fcf0 bl 800ae20 PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b440: 2007 movs r0, #7 800b442: f7ff fb45 bl 800aad0 CONN.chargingError = CONN_ERR_CONTACTOR; PSU_Enable(0, 0); PSU_SwitchState(PSU_WAIT_ACK_OFF); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b446: e050 b.n 800b4ea }else if(PSU_StateTime() > 1000){ 800b448: f7ff fb56 bl 800aaf8 800b44c: 4603 mov r3, r0 800b44e: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b452: d94a bls.n 800b4ea PSU0.cont_fault = 1; 800b454: 4b28 ldr r3, [pc, #160] @ (800b4f8 ) 800b456: 2201 movs r2, #1 800b458: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b45a: 4b28 ldr r3, [pc, #160] @ (800b4fc ) 800b45c: 2207 movs r2, #7 800b45e: 775a strb r2, [r3, #29] PSU_Enable(0, 0); 800b460: 2100 movs r1, #0 800b462: 2000 movs r0, #0 800b464: f7ff fcdc bl 800ae20 PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b468: 2007 movs r0, #7 800b46a: f7ff fb31 bl 800aad0 log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b46e: 4924 ldr r1, [pc, #144] @ (800b500 ) 800b470: 2004 movs r0, #4 800b472: f7fe fffd bl 800a470 break; 800b476: e038 b.n 800b4ea case PSU_WAIT_ACK_OFF: if(!PSU0.PSU_enabled){ 800b478: 4b1f ldr r3, [pc, #124] @ (800b4f8 ) 800b47a: 7a9b ldrb r3, [r3, #10] 800b47c: 2b00 cmp r3, #0 800b47e: d103 bne.n 800b488 PSU_SwitchState(PSU_OFF_PAUSE); 800b480: 2009 movs r0, #9 800b482: f7ff fb25 bl 800aad0 PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU off timeout\n"); } break; 800b486: e032 b.n 800b4ee }else if(PSU_StateTime() > 10000){ 800b488: f7ff fb36 bl 800aaf8 800b48c: 4603 mov r3, r0 800b48e: f242 7210 movw r2, #10000 @ 0x2710 800b492: 4293 cmp r3, r2 800b494: d92b bls.n 800b4ee PSU0.psu_fault = 1; 800b496: 4b18 ldr r3, [pc, #96] @ (800b4f8 ) 800b498: 2201 movs r2, #1 800b49a: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b49c: 4b17 ldr r3, [pc, #92] @ (800b4fc ) 800b49e: 220a movs r2, #10 800b4a0: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b4a2: 2000 movs r0, #0 800b4a4: f7ff fb14 bl 800aad0 log_printf(LOG_ERR, "PSU off timeout\n"); 800b4a8: 4916 ldr r1, [pc, #88] @ (800b504 ) 800b4aa: 2004 movs r0, #4 800b4ac: f7fe ffe0 bl 800a470 break; 800b4b0: e01d b.n 800b4ee case PSU_OFF_PAUSE: if(PSU_StateTime() > 4000){ 800b4b2: f7ff fb21 bl 800aaf8 800b4b6: 4603 mov r3, r0 800b4b8: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b4bc: d919 bls.n 800b4f2 PSU_SwitchState(PSU_READY); 800b4be: 2002 movs r0, #2 800b4c0: f7ff fb06 bl 800aad0 } break; 800b4c4: e015 b.n 800b4f2 default: PSU_SwitchState(PSU_UNREADY); 800b4c6: 2000 movs r0, #0 800b4c8: f7ff fb02 bl 800aad0 break; 800b4cc: e012 b.n 800b4f4 break; 800b4ce: bf00 nop 800b4d0: e010 b.n 800b4f4 break; 800b4d2: bf00 nop 800b4d4: e00e b.n 800b4f4 break; 800b4d6: bf00 nop 800b4d8: e00c b.n 800b4f4 break; 800b4da: bf00 nop 800b4dc: e00a b.n 800b4f4 break; 800b4de: bf00 nop 800b4e0: e008 b.n 800b4f4 break; 800b4e2: bf00 nop 800b4e4: e006 b.n 800b4f4 break; 800b4e6: bf00 nop 800b4e8: e004 b.n 800b4f4 break; 800b4ea: bf00 nop 800b4ec: e002 b.n 800b4f4 break; 800b4ee: bf00 nop 800b4f0: e000 b.n 800b4f4 break; 800b4f2: bf00 nop } } 800b4f4: bf00 nop 800b4f6: bd98 pop {r3, r4, r7, pc} 800b4f8: 20000724 .word 0x20000724 800b4fc: 200001d4 .word 0x200001d4 800b500: 08014194 .word 0x08014194 800b504: 080141b4 .word 0x080141b4 0800b508 : .Th = 10, .Tf = 50, .Tl = 0, }; void LED_Write(){ 800b508: b580 push {r7, lr} 800b50a: af00 add r7, sp, #0 if(CONN.chargingError != CONN_NO_ERROR){ 800b50c: 4b34 ldr r3, [pc, #208] @ (800b5e0 ) 800b50e: 7f5b ldrb r3, [r3, #29] 800b510: 2b00 cmp r3, #0 800b512: d003 beq.n 800b51c LED_SetColor(&color_error); 800b514: 4833 ldr r0, [pc, #204] @ (800b5e4 ) 800b516: f000 f91f bl 800b758 return; 800b51a: e05f b.n 800b5dc } switch(CONN.connState){ 800b51c: 4b30 ldr r3, [pc, #192] @ (800b5e0 ) 800b51e: 785b ldrb r3, [r3, #1] 800b520: 2b0d cmp r3, #13 800b522: d857 bhi.n 800b5d4 800b524: a201 add r2, pc, #4 @ (adr r2, 800b52c ) 800b526: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b52a: bf00 nop 800b52c: 0800b565 .word 0x0800b565 800b530: 0800b56d .word 0x0800b56d 800b534: 0800b575 .word 0x0800b575 800b538: 0800b57d .word 0x0800b57d 800b53c: 0800b585 .word 0x0800b585 800b540: 0800b58d .word 0x0800b58d 800b544: 0800b595 .word 0x0800b595 800b548: 0800b59d .word 0x0800b59d 800b54c: 0800b5a5 .word 0x0800b5a5 800b550: 0800b5ad .word 0x0800b5ad 800b554: 0800b5b5 .word 0x0800b5b5 800b558: 0800b5bd .word 0x0800b5bd 800b55c: 0800b5c5 .word 0x0800b5c5 800b560: 0800b5cd .word 0x0800b5cd case Unknown: LED_SetColor(&color_unknown); 800b564: 4820 ldr r0, [pc, #128] @ (800b5e8 ) 800b566: f000 f8f7 bl 800b758 break; 800b56a: e037 b.n 800b5dc case Unplugged: LED_SetColor(&color_unplugged); 800b56c: 481f ldr r0, [pc, #124] @ (800b5ec ) 800b56e: f000 f8f3 bl 800b758 break; 800b572: e033 b.n 800b5dc case Disabled: LED_SetColor(&color_error); 800b574: 481b ldr r0, [pc, #108] @ (800b5e4 ) 800b576: f000 f8ef bl 800b758 break; 800b57a: e02f b.n 800b5dc case Preparing: LED_SetColor(&color_preparing); 800b57c: 481c ldr r0, [pc, #112] @ (800b5f0 ) 800b57e: f000 f8eb bl 800b758 break; 800b582: e02b b.n 800b5dc case AuthRequired: LED_SetColor(&color_preparing); 800b584: 481a ldr r0, [pc, #104] @ (800b5f0 ) 800b586: f000 f8e7 bl 800b758 break; 800b58a: e027 b.n 800b5dc case WaitingForEnergy: LED_SetColor(&color_charging); 800b58c: 4819 ldr r0, [pc, #100] @ (800b5f4 ) 800b58e: f000 f8e3 bl 800b758 break; 800b592: e023 b.n 800b5dc case ChargingPausedEV: LED_SetColor(&color_charging); 800b594: 4817 ldr r0, [pc, #92] @ (800b5f4 ) 800b596: f000 f8df bl 800b758 break; 800b59a: e01f b.n 800b5dc case ChargingPausedEVSE: LED_SetColor(&color_charging); 800b59c: 4815 ldr r0, [pc, #84] @ (800b5f4 ) 800b59e: f000 f8db bl 800b758 break; 800b5a2: e01b b.n 800b5dc case Charging: LED_SetColor(&color_charging); 800b5a4: 4813 ldr r0, [pc, #76] @ (800b5f4 ) 800b5a6: f000 f8d7 bl 800b758 break; 800b5aa: e017 b.n 800b5dc case AuthTimeout: LED_SetColor(&color_finished); 800b5ac: 4812 ldr r0, [pc, #72] @ (800b5f8 ) 800b5ae: f000 f8d3 bl 800b758 break; 800b5b2: e013 b.n 800b5dc case Finished: LED_SetColor(&color_finished); 800b5b4: 4810 ldr r0, [pc, #64] @ (800b5f8 ) 800b5b6: f000 f8cf bl 800b758 break; 800b5ba: e00f b.n 800b5dc case FinishedEVSE: LED_SetColor(&color_finished); 800b5bc: 480e ldr r0, [pc, #56] @ (800b5f8 ) 800b5be: f000 f8cb bl 800b758 break; 800b5c2: e00b b.n 800b5dc case FinishedEV: LED_SetColor(&color_finished); 800b5c4: 480c ldr r0, [pc, #48] @ (800b5f8 ) 800b5c6: f000 f8c7 bl 800b758 break; 800b5ca: e007 b.n 800b5dc case Replugging: LED_SetColor(&color_preparing); 800b5cc: 4808 ldr r0, [pc, #32] @ (800b5f0 ) 800b5ce: f000 f8c3 bl 800b758 break; 800b5d2: e003 b.n 800b5dc default: LED_SetColor(&color_unknown); 800b5d4: 4804 ldr r0, [pc, #16] @ (800b5e8 ) 800b5d6: f000 f8bf bl 800b758 break; 800b5da: bf00 nop } } 800b5dc: bd80 pop {r7, pc} 800b5de: bf00 nop 800b5e0: 200001d4 .word 0x200001d4 800b5e4: 20000044 .word 0x20000044 800b5e8: 20000008 .word 0x20000008 800b5ec: 20000014 .word 0x20000014 800b5f0: 20000020 .word 0x20000020 800b5f4: 2000002c .word 0x2000002c 800b5f8: 20000038 .word 0x20000038 0800b5fc : void interpolateColors(RGB_t* color1, RGB_t* color2, uint16_t a, uint16_t b, RGB_t *result) { 800b5fc: b480 push {r7} 800b5fe: b087 sub sp, #28 800b600: af00 add r7, sp, #0 800b602: 60f8 str r0, [r7, #12] 800b604: 60b9 str r1, [r7, #8] 800b606: 4611 mov r1, r2 800b608: 461a mov r2, r3 800b60a: 460b mov r3, r1 800b60c: 80fb strh r3, [r7, #6] 800b60e: 4613 mov r3, r2 800b610: 80bb strh r3, [r7, #4] // Проверяем, чтобы a не выходила за пределы диапазона if (a > b) a = b; 800b612: 88fa ldrh r2, [r7, #6] 800b614: 88bb ldrh r3, [r7, #4] 800b616: 429a cmp r2, r3 800b618: d901 bls.n 800b61e 800b61a: 88bb ldrh r3, [r7, #4] 800b61c: 80fb strh r3, [r7, #6] if(b==0) b = 1; 800b61e: 88bb ldrh r3, [r7, #4] 800b620: 2b00 cmp r3, #0 800b622: d101 bne.n 800b628 800b624: 2301 movs r3, #1 800b626: 80bb strh r3, [r7, #4] // Вычисляем коэффициент смешивания в виде целого числа uint16_t t = (a * 255) / b; // t будет от 0 до 255 800b628: 88fa ldrh r2, [r7, #6] 800b62a: 4613 mov r3, r2 800b62c: 021b lsls r3, r3, #8 800b62e: 1a9a subs r2, r3, r2 800b630: 88bb ldrh r3, [r7, #4] 800b632: fb92 f3f3 sdiv r3, r2, r3 800b636: 82fb strh r3, [r7, #22] // Линейная интерполяция с использованием целых чисел result->R = (color1->R * (255 - t) + color2->R * t) / 255; 800b638: 68fb ldr r3, [r7, #12] 800b63a: 781b ldrb r3, [r3, #0] 800b63c: 461a mov r2, r3 800b63e: 8afb ldrh r3, [r7, #22] 800b640: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b644: fb03 f202 mul.w r2, r3, r2 800b648: 68bb ldr r3, [r7, #8] 800b64a: 781b ldrb r3, [r3, #0] 800b64c: 4619 mov r1, r3 800b64e: 8afb ldrh r3, [r7, #22] 800b650: fb01 f303 mul.w r3, r1, r3 800b654: 4413 add r3, r2 800b656: 4a20 ldr r2, [pc, #128] @ (800b6d8 ) 800b658: fb82 1203 smull r1, r2, r2, r3 800b65c: 441a add r2, r3 800b65e: 11d2 asrs r2, r2, #7 800b660: 17db asrs r3, r3, #31 800b662: 1ad3 subs r3, r2, r3 800b664: b2da uxtb r2, r3 800b666: 6a3b ldr r3, [r7, #32] 800b668: 701a strb r2, [r3, #0] result->G = (color1->G * (255 - t) + color2->G * t) / 255; 800b66a: 68fb ldr r3, [r7, #12] 800b66c: 785b ldrb r3, [r3, #1] 800b66e: 461a mov r2, r3 800b670: 8afb ldrh r3, [r7, #22] 800b672: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b676: fb03 f202 mul.w r2, r3, r2 800b67a: 68bb ldr r3, [r7, #8] 800b67c: 785b ldrb r3, [r3, #1] 800b67e: 4619 mov r1, r3 800b680: 8afb ldrh r3, [r7, #22] 800b682: fb01 f303 mul.w r3, r1, r3 800b686: 4413 add r3, r2 800b688: 4a13 ldr r2, [pc, #76] @ (800b6d8 ) 800b68a: fb82 1203 smull r1, r2, r2, r3 800b68e: 441a add r2, r3 800b690: 11d2 asrs r2, r2, #7 800b692: 17db asrs r3, r3, #31 800b694: 1ad3 subs r3, r2, r3 800b696: b2da uxtb r2, r3 800b698: 6a3b ldr r3, [r7, #32] 800b69a: 705a strb r2, [r3, #1] result->B = (color1->B * (255 - t) + color2->B * t) / 255; 800b69c: 68fb ldr r3, [r7, #12] 800b69e: 789b ldrb r3, [r3, #2] 800b6a0: 461a mov r2, r3 800b6a2: 8afb ldrh r3, [r7, #22] 800b6a4: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b6a8: fb03 f202 mul.w r2, r3, r2 800b6ac: 68bb ldr r3, [r7, #8] 800b6ae: 789b ldrb r3, [r3, #2] 800b6b0: 4619 mov r1, r3 800b6b2: 8afb ldrh r3, [r7, #22] 800b6b4: fb01 f303 mul.w r3, r1, r3 800b6b8: 4413 add r3, r2 800b6ba: 4a07 ldr r2, [pc, #28] @ (800b6d8 ) 800b6bc: fb82 1203 smull r1, r2, r2, r3 800b6c0: 441a add r2, r3 800b6c2: 11d2 asrs r2, r2, #7 800b6c4: 17db asrs r3, r3, #31 800b6c6: 1ad3 subs r3, r2, r3 800b6c8: b2da uxtb r2, r3 800b6ca: 6a3b ldr r3, [r7, #32] 800b6cc: 709a strb r2, [r3, #2] } 800b6ce: bf00 nop 800b6d0: 371c adds r7, #28 800b6d2: 46bd mov sp, r7 800b6d4: bc80 pop {r7} 800b6d6: 4770 bx lr 800b6d8: 80808081 .word 0x80808081 0800b6dc : void RGB_SetColor(RGB_t *color){ 800b6dc: b480 push {r7} 800b6de: b083 sub sp, #12 800b6e0: af00 add r7, sp, #0 800b6e2: 6078 str r0, [r7, #4] htim4.Instance->CCR2 = color->R * 100 / 255; 800b6e4: 687b ldr r3, [r7, #4] 800b6e6: 781b ldrb r3, [r3, #0] 800b6e8: 461a mov r2, r3 800b6ea: 2364 movs r3, #100 @ 0x64 800b6ec: fb02 f303 mul.w r3, r2, r3 800b6f0: 4a17 ldr r2, [pc, #92] @ (800b750 ) 800b6f2: fb82 1203 smull r1, r2, r2, r3 800b6f6: 441a add r2, r3 800b6f8: 11d2 asrs r2, r2, #7 800b6fa: 17db asrs r3, r3, #31 800b6fc: 1ad2 subs r2, r2, r3 800b6fe: 4b15 ldr r3, [pc, #84] @ (800b754 ) 800b700: 681b ldr r3, [r3, #0] 800b702: 639a str r2, [r3, #56] @ 0x38 htim4.Instance->CCR3 = color->G * 100 / 255; 800b704: 687b ldr r3, [r7, #4] 800b706: 785b ldrb r3, [r3, #1] 800b708: 461a mov r2, r3 800b70a: 2364 movs r3, #100 @ 0x64 800b70c: fb02 f303 mul.w r3, r2, r3 800b710: 4a0f ldr r2, [pc, #60] @ (800b750 ) 800b712: fb82 1203 smull r1, r2, r2, r3 800b716: 441a add r2, r3 800b718: 11d2 asrs r2, r2, #7 800b71a: 17db asrs r3, r3, #31 800b71c: 1ad2 subs r2, r2, r3 800b71e: 4b0d ldr r3, [pc, #52] @ (800b754 ) 800b720: 681b ldr r3, [r3, #0] 800b722: 63da str r2, [r3, #60] @ 0x3c htim4.Instance->CCR4 = color->B * 100 / 255; 800b724: 687b ldr r3, [r7, #4] 800b726: 789b ldrb r3, [r3, #2] 800b728: 461a mov r2, r3 800b72a: 2364 movs r3, #100 @ 0x64 800b72c: fb02 f303 mul.w r3, r2, r3 800b730: 4a07 ldr r2, [pc, #28] @ (800b750 ) 800b732: fb82 1203 smull r1, r2, r2, r3 800b736: 441a add r2, r3 800b738: 11d2 asrs r2, r2, #7 800b73a: 17db asrs r3, r3, #31 800b73c: 1ad2 subs r2, r2, r3 800b73e: 4b05 ldr r3, [pc, #20] @ (800b754 ) 800b740: 681b ldr r3, [r3, #0] 800b742: 641a str r2, [r3, #64] @ 0x40 } 800b744: bf00 nop 800b746: 370c adds r7, #12 800b748: 46bd mov sp, r7 800b74a: bc80 pop {r7} 800b74c: 4770 bx lr 800b74e: bf00 nop 800b750: 80808081 .word 0x80808081 800b754: 20000f08 .word 0x20000f08 0800b758 : void LED_SetColor(RGB_Cycle_t *color){ 800b758: b480 push {r7} 800b75a: b083 sub sp, #12 800b75c: af00 add r7, sp, #0 800b75e: 6078 str r0, [r7, #4] memcpy(&LED_Cycle, color, sizeof(RGB_Cycle_t)); 800b760: 4b05 ldr r3, [pc, #20] @ (800b778 ) 800b762: 687a ldr r2, [r7, #4] 800b764: 6810 ldr r0, [r2, #0] 800b766: 6851 ldr r1, [r2, #4] 800b768: c303 stmia r3!, {r0, r1} 800b76a: 8912 ldrh r2, [r2, #8] 800b76c: 801a strh r2, [r3, #0] } 800b76e: bf00 nop 800b770: 370c adds r7, #12 800b772: 46bd mov sp, r7 800b774: bc80 pop {r7} 800b776: 4770 bx lr 800b778: 20000784 .word 0x20000784 0800b77c : void LED_Init(){ 800b77c: b580 push {r7, lr} 800b77e: b082 sub sp, #8 800b780: af00 add r7, sp, #0 RGB_t color = {.R=0, .G=0, .B=0}; 800b782: 2300 movs r3, #0 800b784: 713b strb r3, [r7, #4] 800b786: 2300 movs r3, #0 800b788: 717b strb r3, [r7, #5] 800b78a: 2300 movs r3, #0 800b78c: 71bb strb r3, [r7, #6] HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_2); 800b78e: 2104 movs r1, #4 800b790: 4809 ldr r0, [pc, #36] @ (800b7b8 ) 800b792: f005 fbdb bl 8010f4c HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); 800b796: 2108 movs r1, #8 800b798: 4807 ldr r0, [pc, #28] @ (800b7b8 ) 800b79a: f005 fbd7 bl 8010f4c HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4); 800b79e: 210c movs r1, #12 800b7a0: 4805 ldr r0, [pc, #20] @ (800b7b8 ) 800b7a2: f005 fbd3 bl 8010f4c RGB_SetColor(&color); 800b7a6: 1d3b adds r3, r7, #4 800b7a8: 4618 mov r0, r3 800b7aa: f7ff ff97 bl 800b6dc } 800b7ae: bf00 nop 800b7b0: 3708 adds r7, #8 800b7b2: 46bd mov sp, r7 800b7b4: bd80 pop {r7, pc} 800b7b6: bf00 nop 800b7b8: 20000f08 .word 0x20000f08 0800b7bc : // } // } // } // } void LED_Task(){ 800b7bc: b580 push {r7, lr} 800b7be: b082 sub sp, #8 800b7c0: af02 add r7, sp, #8 static uint32_t led_tick; if((HAL_GetTick() - led_tick) > 20){ 800b7c2: f002 f887 bl 800d8d4 800b7c6: 4602 mov r2, r0 800b7c8: 4b46 ldr r3, [pc, #280] @ (800b8e4 ) 800b7ca: 681b ldr r3, [r3, #0] 800b7cc: 1ad3 subs r3, r2, r3 800b7ce: 2b14 cmp r3, #20 800b7d0: f240 8085 bls.w 800b8de led_tick = HAL_GetTick(); 800b7d4: f002 f87e bl 800d8d4 800b7d8: 4603 mov r3, r0 800b7da: 4a42 ldr r2, [pc, #264] @ (800b8e4 ) 800b7dc: 6013 str r3, [r2, #0] LED_State.tick++; 800b7de: 4b42 ldr r3, [pc, #264] @ (800b8e8 ) 800b7e0: 885b ldrh r3, [r3, #2] 800b7e2: 3301 adds r3, #1 800b7e4: b29a uxth r2, r3 800b7e6: 4b40 ldr r3, [pc, #256] @ (800b8e8 ) 800b7e8: 805a strh r2, [r3, #2] // LED_PhaseSync(led_n); switch(LED_State.state){ 800b7ea: 4b3f ldr r3, [pc, #252] @ (800b8e8 ) 800b7ec: 781b ldrb r3, [r3, #0] 800b7ee: 2b03 cmp r3, #3 800b7f0: d867 bhi.n 800b8c2 800b7f2: a201 add r2, pc, #4 @ (adr r2, 800b7f8 ) 800b7f4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b7f8: 0800b809 .word 0x0800b809 800b7fc: 0800b83b .word 0x0800b83b 800b800: 0800b867 .word 0x0800b867 800b804: 0800b899 .word 0x0800b899 case LED_RISING: interpolateColors(&LED_Cycle.Color2, &LED_Cycle.Color1, LED_State.tick, LED_Cycle.Tr, &LED_State.color); 800b808: 4b37 ldr r3, [pc, #220] @ (800b8e8 ) 800b80a: 885a ldrh r2, [r3, #2] 800b80c: 4b37 ldr r3, [pc, #220] @ (800b8ec ) 800b80e: 78db ldrb r3, [r3, #3] 800b810: 4619 mov r1, r3 800b812: 4b37 ldr r3, [pc, #220] @ (800b8f0 ) 800b814: 9300 str r3, [sp, #0] 800b816: 460b mov r3, r1 800b818: 4934 ldr r1, [pc, #208] @ (800b8ec ) 800b81a: 4836 ldr r0, [pc, #216] @ (800b8f4 ) 800b81c: f7ff feee bl 800b5fc if(LED_State.tick>LED_Cycle.Tr){ 800b820: 4b31 ldr r3, [pc, #196] @ (800b8e8 ) 800b822: 885b ldrh r3, [r3, #2] 800b824: 4a31 ldr r2, [pc, #196] @ (800b8ec ) 800b826: 78d2 ldrb r2, [r2, #3] 800b828: 4293 cmp r3, r2 800b82a: d94e bls.n 800b8ca LED_State.state = LED_HIGH; 800b82c: 4b2e ldr r3, [pc, #184] @ (800b8e8 ) 800b82e: 2201 movs r2, #1 800b830: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b832: 4b2d ldr r3, [pc, #180] @ (800b8e8 ) 800b834: 2200 movs r2, #0 800b836: 805a strh r2, [r3, #2] } break; 800b838: e047 b.n 800b8ca case LED_HIGH: memcpy(&LED_State.color, &LED_Cycle.Color1, sizeof(RGB_t)); 800b83a: 4b2b ldr r3, [pc, #172] @ (800b8e8 ) 800b83c: 4a2b ldr r2, [pc, #172] @ (800b8ec ) 800b83e: 3304 adds r3, #4 800b840: 6812 ldr r2, [r2, #0] 800b842: 4611 mov r1, r2 800b844: 8019 strh r1, [r3, #0] 800b846: 3302 adds r3, #2 800b848: 0c12 lsrs r2, r2, #16 800b84a: 701a strb r2, [r3, #0] if(LED_State.tick>LED_Cycle.Th){ 800b84c: 4b26 ldr r3, [pc, #152] @ (800b8e8 ) 800b84e: 885b ldrh r3, [r3, #2] 800b850: 4a26 ldr r2, [pc, #152] @ (800b8ec ) 800b852: 7912 ldrb r2, [r2, #4] 800b854: 4293 cmp r3, r2 800b856: d93a bls.n 800b8ce LED_State.state = LED_FALLING; 800b858: 4b23 ldr r3, [pc, #140] @ (800b8e8 ) 800b85a: 2202 movs r2, #2 800b85c: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b85e: 4b22 ldr r3, [pc, #136] @ (800b8e8 ) 800b860: 2200 movs r2, #0 800b862: 805a strh r2, [r3, #2] } break; 800b864: e033 b.n 800b8ce case LED_FALLING: interpolateColors(&LED_Cycle.Color1, &LED_Cycle.Color2, LED_State.tick, LED_Cycle.Tf, &LED_State.color); 800b866: 4b20 ldr r3, [pc, #128] @ (800b8e8 ) 800b868: 885a ldrh r2, [r3, #2] 800b86a: 4b20 ldr r3, [pc, #128] @ (800b8ec ) 800b86c: 795b ldrb r3, [r3, #5] 800b86e: 4619 mov r1, r3 800b870: 4b1f ldr r3, [pc, #124] @ (800b8f0 ) 800b872: 9300 str r3, [sp, #0] 800b874: 460b mov r3, r1 800b876: 491f ldr r1, [pc, #124] @ (800b8f4 ) 800b878: 481c ldr r0, [pc, #112] @ (800b8ec ) 800b87a: f7ff febf bl 800b5fc if(LED_State.tick>LED_Cycle.Tf){ 800b87e: 4b1a ldr r3, [pc, #104] @ (800b8e8 ) 800b880: 885b ldrh r3, [r3, #2] 800b882: 4a1a ldr r2, [pc, #104] @ (800b8ec ) 800b884: 7952 ldrb r2, [r2, #5] 800b886: 4293 cmp r3, r2 800b888: d923 bls.n 800b8d2 LED_State.state = LED_LOW; 800b88a: 4b17 ldr r3, [pc, #92] @ (800b8e8 ) 800b88c: 2203 movs r2, #3 800b88e: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b890: 4b15 ldr r3, [pc, #84] @ (800b8e8 ) 800b892: 2200 movs r2, #0 800b894: 805a strh r2, [r3, #2] } break; 800b896: e01c b.n 800b8d2 case LED_LOW: memcpy(&LED_State.color, &LED_Cycle.Color2, sizeof(RGB_t)); 800b898: 4b13 ldr r3, [pc, #76] @ (800b8e8 ) 800b89a: 4a14 ldr r2, [pc, #80] @ (800b8ec ) 800b89c: 3304 adds r3, #4 800b89e: 3207 adds r2, #7 800b8a0: 8811 ldrh r1, [r2, #0] 800b8a2: 7892 ldrb r2, [r2, #2] 800b8a4: 8019 strh r1, [r3, #0] 800b8a6: 709a strb r2, [r3, #2] if(LED_State.tick>LED_Cycle.Tl){ 800b8a8: 4b0f ldr r3, [pc, #60] @ (800b8e8 ) 800b8aa: 885b ldrh r3, [r3, #2] 800b8ac: 4a0f ldr r2, [pc, #60] @ (800b8ec ) 800b8ae: 7992 ldrb r2, [r2, #6] 800b8b0: 4293 cmp r3, r2 800b8b2: d910 bls.n 800b8d6 LED_State.state = LED_RISING; 800b8b4: 4b0c ldr r3, [pc, #48] @ (800b8e8 ) 800b8b6: 2200 movs r2, #0 800b8b8: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b8ba: 4b0b ldr r3, [pc, #44] @ (800b8e8 ) 800b8bc: 2200 movs r2, #0 800b8be: 805a strh r2, [r3, #2] } break; 800b8c0: e009 b.n 800b8d6 default: LED_State.state = LED_RISING; 800b8c2: 4b09 ldr r3, [pc, #36] @ (800b8e8 ) 800b8c4: 2200 movs r2, #0 800b8c6: 701a strb r2, [r3, #0] 800b8c8: e006 b.n 800b8d8 break; 800b8ca: bf00 nop 800b8cc: e004 b.n 800b8d8 break; 800b8ce: bf00 nop 800b8d0: e002 b.n 800b8d8 break; 800b8d2: bf00 nop 800b8d4: e000 b.n 800b8d8 break; 800b8d6: bf00 nop } RGB_SetColor(&LED_State.color); 800b8d8: 4805 ldr r0, [pc, #20] @ (800b8f0 ) 800b8da: f7ff feff bl 800b6dc } } 800b8de: bf00 nop 800b8e0: 46bd mov sp, r7 800b8e2: bd80 pop {r7, pc} 800b8e4: 20000790 .word 0x20000790 800b8e8: 2000077c .word 0x2000077c 800b8ec: 20000784 .word 0x20000784 800b8f0: 20000780 .word 0x20000780 800b8f4: 2000078b .word 0x2000078b 0800b8f8 : RTC_HandleTypeDef hrtc; /* RTC init function */ void MX_RTC_Init(void) { 800b8f8: b580 push {r7, lr} 800b8fa: af00 add r7, sp, #0 /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 800b8fc: 4b0a ldr r3, [pc, #40] @ (800b928 ) 800b8fe: 4a0b ldr r2, [pc, #44] @ (800b92c ) 800b900: 601a str r2, [r3, #0] hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; 800b902: 4b09 ldr r3, [pc, #36] @ (800b928 ) 800b904: f04f 32ff mov.w r2, #4294967295 800b908: 605a str r2, [r3, #4] hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; 800b90a: 4b07 ldr r3, [pc, #28] @ (800b928 ) 800b90c: f44f 7280 mov.w r2, #256 @ 0x100 800b910: 609a str r2, [r3, #8] if (HAL_RTC_Init(&hrtc) != HAL_OK) 800b912: 4805 ldr r0, [pc, #20] @ (800b928 ) 800b914: f005 f874 bl 8010a00 800b918: 4603 mov r3, r0 800b91a: 2b00 cmp r3, #0 800b91c: d001 beq.n 800b922 { Error_Handler(); 800b91e: f7ff f867 bl 800a9f0 } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 800b922: bf00 nop 800b924: bd80 pop {r7, pc} 800b926: bf00 nop 800b928: 20000794 .word 0x20000794 800b92c: 40002800 .word 0x40002800 0800b930 : void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) { 800b930: b580 push {r7, lr} 800b932: b084 sub sp, #16 800b934: af00 add r7, sp, #0 800b936: 6078 str r0, [r7, #4] if(rtcHandle->Instance==RTC) 800b938: 687b ldr r3, [r7, #4] 800b93a: 681b ldr r3, [r3, #0] 800b93c: 4a0b ldr r2, [pc, #44] @ (800b96c ) 800b93e: 4293 cmp r3, r2 800b940: d110 bne.n 800b964 { /* USER CODE BEGIN RTC_MspInit 0 */ /* USER CODE END RTC_MspInit 0 */ HAL_PWR_EnableBkUpAccess(); 800b942: f003 fff1 bl 800f928 /* Enable BKP CLK enable for backup registers */ __HAL_RCC_BKP_CLK_ENABLE(); 800b946: 4b0a ldr r3, [pc, #40] @ (800b970 ) 800b948: 69db ldr r3, [r3, #28] 800b94a: 4a09 ldr r2, [pc, #36] @ (800b970 ) 800b94c: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800b950: 61d3 str r3, [r2, #28] 800b952: 4b07 ldr r3, [pc, #28] @ (800b970 ) 800b954: 69db ldr r3, [r3, #28] 800b956: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800b95a: 60fb str r3, [r7, #12] 800b95c: 68fb ldr r3, [r7, #12] /* RTC clock enable */ __HAL_RCC_RTC_ENABLE(); 800b95e: 4b05 ldr r3, [pc, #20] @ (800b974 ) 800b960: 2201 movs r2, #1 800b962: 601a str r2, [r3, #0] /* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE END RTC_MspInit 1 */ } } 800b964: bf00 nop 800b966: 3710 adds r7, #16 800b968: 46bd mov sp, r7 800b96a: bd80 pop {r7, pc} 800b96c: 40002800 .word 0x40002800 800b970: 40021000 .word 0x40021000 800b974: 4242043c .word 0x4242043c 0800b978 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 800b978: b480 push {r7} 800b97a: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 800b97c: f3bf 8f4f dsb sy } 800b980: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800b982: 4b06 ldr r3, [pc, #24] @ (800b99c <__NVIC_SystemReset+0x24>) 800b984: 68db ldr r3, [r3, #12] 800b986: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800b98a: 4904 ldr r1, [pc, #16] @ (800b99c <__NVIC_SystemReset+0x24>) 800b98c: 4b04 ldr r3, [pc, #16] @ (800b9a0 <__NVIC_SystemReset+0x28>) 800b98e: 4313 orrs r3, r2 800b990: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800b992: f3bf 8f4f dsb sy } 800b996: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 800b998: bf00 nop 800b99a: e7fd b.n 800b998 <__NVIC_SystemReset+0x20> 800b99c: e000ed00 .word 0xe000ed00 800b9a0: 05fa0004 .word 0x05fa0004 0800b9a4 : CONN_State_t CCS_EvseState; CCS_ConnectorState_t CCS_ConnectorState = CCS_UNPLUGGED; static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len); void CCS_RxEventCallback(UART_HandleTypeDef *huart, uint16_t size) { 800b9a4: b580 push {r7, lr} 800b9a6: b082 sub sp, #8 800b9a8: af00 add r7, sp, #0 800b9aa: 6078 str r0, [r7, #4] 800b9ac: 460b mov r3, r1 800b9ae: 807b strh r3, [r7, #2] if (huart != &huart3) { 800b9b0: 687b ldr r3, [r7, #4] 800b9b2: 4a0b ldr r2, [pc, #44] @ (800b9e0 ) 800b9b4: 4293 cmp r3, r2 800b9b6: d10f bne.n 800b9d8 return; } rx_armed = 0; 800b9b8: 4b0a ldr r3, [pc, #40] @ (800b9e4 ) 800b9ba: 2200 movs r2, #0 800b9bc: 701a strb r2, [r3, #0] if (size > 0 && size <= sizeof(rx_buffer)) { 800b9be: 887b ldrh r3, [r7, #2] 800b9c0: 2b00 cmp r3, #0 800b9c2: d00a beq.n 800b9da 800b9c4: 887b ldrh r3, [r7, #2] 800b9c6: f5b3 7f80 cmp.w r3, #256 @ 0x100 800b9ca: d806 bhi.n 800b9da process_received_packet(rx_buffer, size); 800b9cc: 887b ldrh r3, [r7, #2] 800b9ce: 4619 mov r1, r3 800b9d0: 4805 ldr r0, [pc, #20] @ (800b9e8 ) 800b9d2: f000 fc99 bl 800c308 800b9d6: e000 b.n 800b9da return; 800b9d8: bf00 nop } } 800b9da: 3708 adds r7, #8 800b9dc: 46bd mov sp, r7 800b9de: bd80 pop {r7, pc} 800b9e0: 20001028 .word 0x20001028 800b9e4: 200009cc .word 0x200009cc 800b9e8: 200007cc .word 0x200007cc 0800b9ec : void CCS_SerialLoop(void) { 800b9ec: b580 push {r7, lr} 800b9ee: af00 add r7, sp, #0 static uint32_t replug_tick = 0; static uint32_t replug_watchdog_tick = 0; static uint32_t replug_watchdog1_tick = 0; static uint32_t last_state_sent = 0; if (!rx_armed && HAL_UART_GetState(&huart3) == HAL_UART_STATE_READY) { 800b9f0: 4ba6 ldr r3, [pc, #664] @ (800bc8c ) 800b9f2: 781b ldrb r3, [r3, #0] 800b9f4: 2b00 cmp r3, #0 800b9f6: d111 bne.n 800ba1c 800b9f8: 48a5 ldr r0, [pc, #660] @ (800bc90 ) 800b9fa: f006 fe50 bl 801269e 800b9fe: 4603 mov r3, r0 800ba00: 2b20 cmp r3, #32 800ba02: d10b bne.n 800ba1c if (HAL_UARTEx_ReceiveToIdle_IT(&huart3, rx_buffer, sizeof(rx_buffer)) == HAL_OK) { 800ba04: f44f 7280 mov.w r2, #256 @ 0x100 800ba08: 49a2 ldr r1, [pc, #648] @ (800bc94 ) 800ba0a: 48a1 ldr r0, [pc, #644] @ (800bc90 ) 800ba0c: f006 fa28 bl 8011e60 800ba10: 4603 mov r3, r0 800ba12: 2b00 cmp r3, #0 800ba14: d102 bne.n 800ba1c rx_armed = 1; 800ba16: 4b9d ldr r3, [pc, #628] @ (800bc8c ) 800ba18: 2201 movs r2, #1 800ba1a: 701a strb r2, [r3, #0] } } /* Read CP once per loop and use buffered value below. */ cp_state_buffer = CP_GetState(); 800ba1c: f7fe fb96 bl 800a14c 800ba20: 4603 mov r3, r0 800ba22: 461a mov r2, r3 800ba24: 4b9c ldr r3, [pc, #624] @ (800bc98 ) 800ba26: 701a strb r2, [r3, #0] if (CONN.connControl != CMD_NONE) { 800ba28: 4b9c ldr r3, [pc, #624] @ (800bc9c ) 800ba2a: 781b ldrb r3, [r3, #0] 800ba2c: 2b00 cmp r3, #0 800ba2e: d003 beq.n 800ba38 last_cmd = CONN.connControl; 800ba30: 4b9a ldr r3, [pc, #616] @ (800bc9c ) 800ba32: 781a ldrb r2, [r3, #0] 800ba34: 4b9a ldr r3, [pc, #616] @ (800bca0 ) 800ba36: 701a strb r2, [r3, #0] } if((HAL_GetTick() - last_cmd_sent) > CMD_INTERVAL){ 800ba38: f001 ff4c bl 800d8d4 800ba3c: 4602 mov r2, r0 800ba3e: 4b99 ldr r3, [pc, #612] @ (800bca4 ) 800ba40: 681b ldr r3, [r3, #0] 800ba42: 1ad3 subs r3, r2, r3 800ba44: 2b0a cmp r3, #10 800ba46: d953 bls.n 800baf0 if ((HAL_GetTick() - last_state_sent) >= 200) { 800ba48: f001 ff44 bl 800d8d4 800ba4c: 4602 mov r2, r0 800ba4e: 4b96 ldr r3, [pc, #600] @ (800bca8 ) 800ba50: 681b ldr r3, [r3, #0] 800ba52: 1ad3 subs r3, r2, r3 800ba54: 2bc7 cmp r3, #199 @ 0xc7 800ba56: d906 bls.n 800ba66 send_state(); 800ba58: f000 fada bl 800c010 last_state_sent = HAL_GetTick(); 800ba5c: f001 ff3a bl 800d8d4 800ba60: 4603 mov r3, r0 800ba62: 4a91 ldr r2, [pc, #580] @ (800bca8 ) 800ba64: 6013 str r3, [r2, #0] } if (ESTOP) { 800ba66: 4b91 ldr r3, [pc, #580] @ (800bcac ) 800ba68: 781b ldrb r3, [r3, #0] 800ba6a: 2b00 cmp r3, #0 800ba6c: d008 beq.n 800ba80 log_printf(LOG_ERR, "ESTOP triggered\n"); 800ba6e: 4990 ldr r1, [pc, #576] @ (800bcb0 ) 800ba70: 2004 movs r0, #4 800ba72: f7fe fcfd bl 800a470 CCS_SendEmergencyStop(); 800ba76: f000 fa6c bl 800bf52 ESTOP = 0; 800ba7a: 4b8c ldr r3, [pc, #560] @ (800bcac ) 800ba7c: 2200 movs r2, #0 800ba7e: 701a strb r2, [r3, #0] } if (((CONN.connControl == CMD_STOP) || 800ba80: 4b86 ldr r3, [pc, #536] @ (800bc9c ) 800ba82: 781b ldrb r3, [r3, #0] 800ba84: 2b01 cmp r3, #1 800ba86: d003 beq.n 800ba90 (CONN.chargingError != CONN_NO_ERROR)) && 800ba88: 4b84 ldr r3, [pc, #528] @ (800bc9c ) 800ba8a: 7f5b ldrb r3, [r3, #29] if (((CONN.connControl == CMD_STOP) || 800ba8c: 2b00 cmp r3, #0 800ba8e: d013 beq.n 800bab8 ((HAL_GetTick() - last_stop_sent) > 1000)) { 800ba90: f001 ff20 bl 800d8d4 800ba94: 4602 mov r2, r0 800ba96: 4b87 ldr r3, [pc, #540] @ (800bcb4 ) 800ba98: 681b ldr r3, [r3, #0] 800ba9a: 1ad3 subs r3, r2, r3 (CONN.chargingError != CONN_NO_ERROR)) && 800ba9c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800baa0: d90a bls.n 800bab8 last_stop_sent = HAL_GetTick(); 800baa2: f001 ff17 bl 800d8d4 800baa6: 4603 mov r3, r0 800baa8: 4a82 ldr r2, [pc, #520] @ (800bcb4 ) 800baaa: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "Stopping charging...\n"); 800baac: 4982 ldr r1, [pc, #520] @ (800bcb8 ) 800baae: 2005 movs r0, #5 800bab0: f7fe fcde bl 800a470 CCS_SendEmergencyStop(); 800bab4: f000 fa4d bl 800bf52 } if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800bab8: 4b80 ldr r3, [pc, #512] @ (800bcbc ) 800baba: 781b ldrb r3, [r3, #0] 800babc: 2b0c cmp r3, #12 800babe: d003 beq.n 800bac8 800bac0: 4b7e ldr r3, [pc, #504] @ (800bcbc ) 800bac2: 781b ldrb r3, [r3, #0] 800bac4: 2b0b cmp r3, #11 800bac6: d113 bne.n 800baf0 ((HAL_GetTick() - last_stop_sent) > 1000)) { 800bac8: f001 ff04 bl 800d8d4 800bacc: 4602 mov r2, r0 800bace: 4b79 ldr r3, [pc, #484] @ (800bcb4 ) 800bad0: 681b ldr r3, [r3, #0] 800bad2: 1ad3 subs r3, r2, r3 if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800bad4: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bad8: d90a bls.n 800baf0 last_stop_sent = HAL_GetTick(); 800bada: f001 fefb bl 800d8d4 800bade: 4603 mov r3, r0 800bae0: 4a74 ldr r2, [pc, #464] @ (800bcb4 ) 800bae2: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "FinishedEV, stopping...\n"); 800bae4: 4976 ldr r1, [pc, #472] @ (800bcc0 ) 800bae6: 2005 movs r0, #5 800bae8: f7fe fcc2 bl 800a470 CCS_SendEmergencyStop(); 800baec: f000 fa31 bl 800bf52 } (void)replug_watchdog_tick; (void)replug_watchdog1_tick; switch(CCS_ConnectorState){ 800baf0: 4b74 ldr r3, [pc, #464] @ (800bcc4 ) 800baf2: 781b ldrb r3, [r3, #0] 800baf4: 2b04 cmp r3, #4 800baf6: f200 80f8 bhi.w 800bcea 800bafa: a201 add r2, pc, #4 @ (adr r2, 800bb00 ) 800bafc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800bb00: 0800bb15 .word 0x0800bb15 800bb04: 0800bb35 .word 0x0800bb35 800bb08: 0800bb79 .word 0x0800bb79 800bb0c: 0800bbb5 .word 0x0800bbb5 800bb10: 0800bc05 .word 0x0800bc05 case CCS_DISABLED: RELAY_Write(RELAY_CP, 0); 800bb14: 2100 movs r1, #0 800bb16: 2005 movs r0, #5 800bb18: f7fd fcca bl 80094b0 CONN_SetState(Disabled); 800bb1c: 2002 movs r0, #2 800bb1e: f7fe f8c3 bl 8009ca8 if (CONN.chargingError == CONN_NO_ERROR){ 800bb22: 4b5e ldr r3, [pc, #376] @ (800bc9c ) 800bb24: 7f5b ldrb r3, [r3, #29] 800bb26: 2b00 cmp r3, #0 800bb28: f040 80a7 bne.w 800bc7a CCS_ConnectorState = CCS_UNPLUGGED; 800bb2c: 4b65 ldr r3, [pc, #404] @ (800bcc4 ) 800bb2e: 2201 movs r2, #1 800bb30: 701a strb r2, [r3, #0] } break; 800bb32: e0a2 b.n 800bc7a case CCS_UNPLUGGED: RELAY_Write(RELAY_CP, 1); 800bb34: 2101 movs r1, #1 800bb36: 2005 movs r0, #5 800bb38: f7fd fcba bl 80094b0 CONN_SetState(Unplugged); 800bb3c: 2001 movs r0, #1 800bb3e: f7fe f8b3 bl 8009ca8 if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || (cp_state_buffer == EV_STATE_C_CONN_ACTIVE)){ 800bb42: 4b55 ldr r3, [pc, #340] @ (800bc98 ) 800bb44: 781b ldrb r3, [r3, #0] 800bb46: 2b01 cmp r3, #1 800bb48: d003 beq.n 800bb52 800bb4a: 4b53 ldr r3, [pc, #332] @ (800bc98 ) 800bb4c: 781b ldrb r3, [r3, #0] 800bb4e: 2b02 cmp r3, #2 800bb50: d102 bne.n 800bb58 CCS_ConnectorState = CCS_AUTH_REQUIRED; 800bb52: 4b5c ldr r3, [pc, #368] @ (800bcc4 ) 800bb54: 2202 movs r2, #2 800bb56: 701a strb r2, [r3, #0] } if (CONN.chargingError != CONN_NO_ERROR){ 800bb58: 4b50 ldr r3, [pc, #320] @ (800bc9c ) 800bb5a: 7f5b ldrb r3, [r3, #29] 800bb5c: 2b00 cmp r3, #0 800bb5e: f000 808e beq.w 800bc7e log_printf(LOG_ERR, "Charging error %d, state -> disabled\n", CONN.chargingError); 800bb62: 4b4e ldr r3, [pc, #312] @ (800bc9c ) 800bb64: 7f5b ldrb r3, [r3, #29] 800bb66: 461a mov r2, r3 800bb68: 4957 ldr r1, [pc, #348] @ (800bcc8 ) 800bb6a: 2004 movs r0, #4 800bb6c: f7fe fc80 bl 800a470 CCS_ConnectorState = CCS_DISABLED; 800bb70: 4b54 ldr r3, [pc, #336] @ (800bcc4 ) 800bb72: 2200 movs r2, #0 800bb74: 701a strb r2, [r3, #0] } break; 800bb76: e082 b.n 800bc7e case CCS_AUTH_REQUIRED: RELAY_Write(RELAY_CP, 1); 800bb78: 2101 movs r1, #1 800bb7a: 2005 movs r0, #5 800bb7c: f7fd fc98 bl 80094b0 CONN_SetState(AuthRequired); 800bb80: 2004 movs r0, #4 800bb82: f7fe f891 bl 8009ca8 if(CONN.connControl == CMD_START){ 800bb86: 4b45 ldr r3, [pc, #276] @ (800bc9c ) 800bb88: 781b ldrb r3, [r3, #0] 800bb8a: 2b02 cmp r3, #2 800bb8c: d106 bne.n 800bb9c log_printf(LOG_INFO, "Charging permitted, start charging\n"); 800bb8e: 494f ldr r1, [pc, #316] @ (800bccc ) 800bb90: 2007 movs r0, #7 800bb92: f7fe fc6d bl 800a470 CCS_ConnectorState = CCS_CONNECTED; 800bb96: 4b4b ldr r3, [pc, #300] @ (800bcc4 ) 800bb98: 2203 movs r2, #3 800bb9a: 701a strb r2, [r3, #0] } if (cp_state_buffer == EV_STATE_A_IDLE){ 800bb9c: 4b3e ldr r3, [pc, #248] @ (800bc98 ) 800bb9e: 781b ldrb r3, [r3, #0] 800bba0: 2b00 cmp r3, #0 800bba2: d16e bne.n 800bc82 log_printf(LOG_INFO, "Car unplugged\n"); 800bba4: 494a ldr r1, [pc, #296] @ (800bcd0 ) 800bba6: 2007 movs r0, #7 800bba8: f7fe fc62 bl 800a470 CCS_ConnectorState = CCS_UNPLUGGED; 800bbac: 4b45 ldr r3, [pc, #276] @ (800bcc4 ) 800bbae: 2201 movs r2, #1 800bbb0: 701a strb r2, [r3, #0] } break; 800bbb2: e066 b.n 800bc82 case CCS_CONNECTED: RELAY_Write(RELAY_CP, 1); 800bbb4: 2101 movs r1, #1 800bbb6: 2005 movs r0, #5 800bbb8: f7fd fc7a bl 80094b0 if(CCS_EvseState < Preparing) { 800bbbc: 4b3f ldr r3, [pc, #252] @ (800bcbc ) 800bbbe: 781b ldrb r3, [r3, #0] 800bbc0: 2b02 cmp r3, #2 800bbc2: d803 bhi.n 800bbcc CONN_SetState(Preparing); 800bbc4: 2003 movs r0, #3 800bbc6: f7fe f86f bl 8009ca8 800bbca: e004 b.n 800bbd6 } else { CONN_SetState(CCS_EvseState); 800bbcc: 4b3b ldr r3, [pc, #236] @ (800bcbc ) 800bbce: 781b ldrb r3, [r3, #0] 800bbd0: 4618 mov r0, r3 800bbd2: f7fe f869 bl 8009ca8 } if (cp_state_buffer == EV_STATE_A_IDLE){ 800bbd6: 4b30 ldr r3, [pc, #192] @ (800bc98 ) 800bbd8: 781b ldrb r3, [r3, #0] 800bbda: 2b00 cmp r3, #0 800bbdc: d106 bne.n 800bbec log_printf(LOG_INFO, "Car unplugged\n"); 800bbde: 493c ldr r1, [pc, #240] @ (800bcd0 ) 800bbe0: 2007 movs r0, #7 800bbe2: f7fe fc45 bl 800a470 CCS_ConnectorState = CCS_UNPLUGGED; 800bbe6: 4b37 ldr r3, [pc, #220] @ (800bcc4 ) 800bbe8: 2201 movs r2, #1 800bbea: 701a strb r2, [r3, #0] } if(REPLUG > 0){ 800bbec: 4b39 ldr r3, [pc, #228] @ (800bcd4 ) 800bbee: 781b ldrb r3, [r3, #0] 800bbf0: 2b00 cmp r3, #0 800bbf2: d048 beq.n 800bc86 log_printf(LOG_INFO, "Replugging...\n"); 800bbf4: 4938 ldr r1, [pc, #224] @ (800bcd8 ) 800bbf6: 2007 movs r0, #7 800bbf8: f7fe fc3a bl 800a470 CCS_ConnectorState = CCS_REPLUGGING; 800bbfc: 4b31 ldr r3, [pc, #196] @ (800bcc4 ) 800bbfe: 2204 movs r2, #4 800bc00: 701a strb r2, [r3, #0] } break; 800bc02: e040 b.n 800bc86 case CCS_REPLUGGING: RELAY_Write(RELAY_CP, 0); 800bc04: 2100 movs r1, #0 800bc06: 2005 movs r0, #5 800bc08: f7fd fc52 bl 80094b0 CONN_SetState(Replugging); 800bc0c: 200d movs r0, #13 800bc0e: f7fe f84b bl 8009ca8 if((HAL_GetTick() - replug_tick) > 1000){ 800bc12: f001 fe5f bl 800d8d4 800bc16: 4602 mov r2, r0 800bc18: 4b30 ldr r3, [pc, #192] @ (800bcdc ) 800bc1a: 681b ldr r3, [r3, #0] 800bc1c: 1ad3 subs r3, r2, r3 800bc1e: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bc22: d91a bls.n 800bc5a replug_tick = HAL_GetTick(); 800bc24: f001 fe56 bl 800d8d4 800bc28: 4603 mov r3, r0 800bc2a: 4a2c ldr r2, [pc, #176] @ (800bcdc ) 800bc2c: 6013 str r3, [r2, #0] if(REPLUG > 0){ 800bc2e: 4b29 ldr r3, [pc, #164] @ (800bcd4 ) 800bc30: 781b ldrb r3, [r3, #0] 800bc32: 2b00 cmp r3, #0 800bc34: d00a beq.n 800bc4c if (REPLUG != 0xFF) REPLUG--; 800bc36: 4b27 ldr r3, [pc, #156] @ (800bcd4 ) 800bc38: 781b ldrb r3, [r3, #0] 800bc3a: 2bff cmp r3, #255 @ 0xff 800bc3c: d00d beq.n 800bc5a 800bc3e: 4b25 ldr r3, [pc, #148] @ (800bcd4 ) 800bc40: 781b ldrb r3, [r3, #0] 800bc42: 3b01 subs r3, #1 800bc44: b2da uxtb r2, r3 800bc46: 4b23 ldr r3, [pc, #140] @ (800bcd4 ) 800bc48: 701a strb r2, [r3, #0] 800bc4a: e006 b.n 800bc5a } else { log_printf(LOG_INFO, "Replugging finished, but car unplugged\n"); 800bc4c: 4924 ldr r1, [pc, #144] @ (800bce0 ) 800bc4e: 2007 movs r0, #7 800bc50: f7fe fc0e bl 800a470 CCS_ConnectorState = CCS_UNPLUGGED; 800bc54: 4b1b ldr r3, [pc, #108] @ (800bcc4 ) 800bc56: 2201 movs r2, #1 800bc58: 701a strb r2, [r3, #0] } } if(REPLUG == 0){ 800bc5a: 4b1e ldr r3, [pc, #120] @ (800bcd4 ) 800bc5c: 781b ldrb r3, [r3, #0] 800bc5e: 2b00 cmp r3, #0 800bc60: d142 bne.n 800bce8 if(cp_state_buffer == EV_STATE_B_CONN_PREP){ 800bc62: 4b0d ldr r3, [pc, #52] @ (800bc98 ) 800bc64: 781b ldrb r3, [r3, #0] 800bc66: 2b01 cmp r3, #1 800bc68: d13e bne.n 800bce8 log_printf(LOG_INFO, "Replugging finished, car plugged, state -> auth required\n"); 800bc6a: 491e ldr r1, [pc, #120] @ (800bce4 ) 800bc6c: 2007 movs r0, #7 800bc6e: f7fe fbff bl 800a470 CCS_ConnectorState = CCS_AUTH_REQUIRED; 800bc72: 4b14 ldr r3, [pc, #80] @ (800bcc4 ) 800bc74: 2202 movs r2, #2 800bc76: 701a strb r2, [r3, #0] } } break; 800bc78: e036 b.n 800bce8 break; 800bc7a: bf00 nop 800bc7c: e035 b.n 800bcea break; 800bc7e: bf00 nop 800bc80: e033 b.n 800bcea break; 800bc82: bf00 nop 800bc84: e031 b.n 800bcea break; 800bc86: bf00 nop 800bc88: e02f b.n 800bcea 800bc8a: bf00 nop 800bc8c: 200009cc .word 0x200009cc 800bc90: 20001028 .word 0x20001028 800bc94: 200007cc .word 0x200007cc 800bc98: 2000004f .word 0x2000004f 800bc9c: 200001d4 .word 0x200001d4 800bca0: 200007c8 .word 0x200007c8 800bca4: 200007c0 .word 0x200007c0 800bca8: 20000a28 .word 0x20000a28 800bcac: 200009cd .word 0x200009cd 800bcb0: 080141c8 .word 0x080141c8 800bcb4: 200007c4 .word 0x200007c4 800bcb8: 080141dc .word 0x080141dc 800bcbc: 20000a24 .word 0x20000a24 800bcc0: 080141f4 .word 0x080141f4 800bcc4: 20000050 .word 0x20000050 800bcc8: 08014210 .word 0x08014210 800bccc: 08014238 .word 0x08014238 800bcd0: 0801425c .word 0x0801425c 800bcd4: 200009ce .word 0x200009ce 800bcd8: 0801426c .word 0x0801426c 800bcdc: 20000a2c .word 0x20000a2c 800bce0: 0801427c .word 0x0801427c 800bce4: 080142a4 .word 0x080142a4 break; 800bce8: bf00 nop } if (last_host_seen > 0 && (HAL_GetTick() - last_host_seen) > EVEREST_TIMEOUT_MS) { 800bcea: 4b27 ldr r3, [pc, #156] @ (800bd88 ) 800bcec: 681b ldr r3, [r3, #0] 800bcee: 2b00 cmp r3, #0 800bcf0: d016 beq.n 800bd20 800bcf2: f001 fdef bl 800d8d4 800bcf6: 4602 mov r2, r0 800bcf8: 4b23 ldr r3, [pc, #140] @ (800bd88 ) 800bcfa: 681b ldr r3, [r3, #0] 800bcfc: 1ad3 subs r3, r2, r3 800bcfe: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800bd02: d90d bls.n 800bd20 log_printf(LOG_ERR, "Everest timeout\n"); 800bd04: 4921 ldr r1, [pc, #132] @ (800bd8c ) 800bd06: 2004 movs r0, #4 800bd08: f7fe fbb2 bl 800a470 CONN.EnableOutput = 0; 800bd0c: 4b20 ldr r3, [pc, #128] @ (800bd90 ) 800bd0e: 2200 movs r2, #0 800bd10: 75da strb r2, [r3, #23] CCS_EvseState = Unknown; 800bd12: 4b20 ldr r3, [pc, #128] @ (800bd94 ) 800bd14: 2200 movs r2, #0 800bd16: 701a strb r2, [r3, #0] CP_SetDuty(100); 800bd18: 2064 movs r0, #100 @ 0x64 800bd1a: f7fe f9e5 bl 800a0e8 800bd1e: e01c b.n 800bd5a } else { if (last_cmd == CMD_STOP) { 800bd20: 4b1d ldr r3, [pc, #116] @ (800bd98 ) 800bd22: 781b ldrb r3, [r3, #0] 800bd24: 2b01 cmp r3, #1 800bd26: d103 bne.n 800bd30 CONN.EnableOutput = 0; 800bd28: 4b19 ldr r3, [pc, #100] @ (800bd90 ) 800bd2a: 2200 movs r2, #0 800bd2c: 75da strb r2, [r3, #23] 800bd2e: e014 b.n 800bd5a } else { CONN.EnableOutput = ev_enable_output ? 1 : 0; 800bd30: 4b1a ldr r3, [pc, #104] @ (800bd9c ) 800bd32: 781b ldrb r3, [r3, #0] 800bd34: 2b00 cmp r3, #0 800bd36: bf14 ite ne 800bd38: 2301 movne r3, #1 800bd3a: 2300 moveq r3, #0 800bd3c: b2db uxtb r3, r3 800bd3e: 461a mov r2, r3 800bd40: 4b13 ldr r3, [pc, #76] @ (800bd90 ) 800bd42: 75da strb r2, [r3, #23] if((CONN.EnableOutput == 0) && (CONN.connState == Preparing)){ 800bd44: 4b12 ldr r3, [pc, #72] @ (800bd90 ) 800bd46: 7ddb ldrb r3, [r3, #23] 800bd48: 2b00 cmp r3, #0 800bd4a: d106 bne.n 800bd5a 800bd4c: 4b10 ldr r3, [pc, #64] @ (800bd90 ) 800bd4e: 785b ldrb r3, [r3, #1] 800bd50: 2b03 cmp r3, #3 800bd52: d102 bne.n 800bd5a CONN.EnableOutput = 0; 800bd54: 4b0e ldr r3, [pc, #56] @ (800bd90 ) 800bd56: 2200 movs r2, #0 800bd58: 75da strb r2, [r3, #23] } } } if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800bd5a: 4b11 ldr r3, [pc, #68] @ (800bda0 ) 800bd5c: 781b ldrb r3, [r3, #0] 800bd5e: 2b01 cmp r3, #1 800bd60: d007 beq.n 800bd72 (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800bd62: 4b0f ldr r3, [pc, #60] @ (800bda0 ) 800bd64: 781b ldrb r3, [r3, #0] if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800bd66: 2b02 cmp r3, #2 800bd68: d003 beq.n 800bd72 (cp_state_buffer == EV_STATE_D_CONN_ACT_VENT)) { 800bd6a: 4b0d ldr r3, [pc, #52] @ (800bda0 ) 800bd6c: 781b ldrb r3, [r3, #0] (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800bd6e: 2b03 cmp r3, #3 800bd70: d103 bne.n 800bd7a CONN.EvConnected = 1; 800bd72: 4b07 ldr r3, [pc, #28] @ (800bd90 ) 800bd74: 2201 movs r2, #1 800bd76: 779a strb r2, [r3, #30] 800bd78: e003 b.n 800bd82 } else { CONN.EvConnected = 0; 800bd7a: 4b05 ldr r3, [pc, #20] @ (800bd90 ) 800bd7c: 2200 movs r2, #0 800bd7e: 779a strb r2, [r3, #30] } } 800bd80: bf00 nop 800bd82: bf00 nop 800bd84: bd80 pop {r7, pc} 800bd86: bf00 nop 800bd88: 200009d4 .word 0x200009d4 800bd8c: 080142e0 .word 0x080142e0 800bd90: 200001d4 .word 0x200001d4 800bd94: 20000a24 .word 0x20000a24 800bd98: 200007c8 .word 0x200007c8 800bd9c: 200007c9 .word 0x200007c9 800bda0: 2000004f .word 0x2000004f 0800bda4 : void CCS_Init(void){ 800bda4: b580 push {r7, lr} 800bda6: af00 add r7, sp, #0 CP_Init(); 800bda8: f7fe f97c bl 800a0a4 CP_SetDuty(100); 800bdac: 2064 movs r0, #100 @ 0x64 800bdae: f7fe f99b bl 800a0e8 CCS_MaxLoad.maxVoltage = PSU_MAX_VOLTAGE; // 1000V 800bdb2: 4b0d ldr r3, [pc, #52] @ (800bde8 ) 800bdb4: f44f 727a mov.w r2, #1000 @ 0x3e8 800bdb8: 801a strh r2, [r3, #0] CCS_MaxLoad.minVoltage = PSU_MIN_VOLTAGE; //150V 800bdba: 4b0b ldr r3, [pc, #44] @ (800bde8 ) 800bdbc: 2296 movs r2, #150 @ 0x96 800bdbe: 805a strh r2, [r3, #2] CCS_MaxLoad.maxCurrent = PSU_MAX_CURRENT*10; //100A 800bdc0: 4b09 ldr r3, [pc, #36] @ (800bde8 ) 800bdc2: f240 5232 movw r2, #1330 @ 0x532 800bdc6: 809a strh r2, [r3, #4] CCS_MaxLoad.minCurrent = PSU_MIN_CURRENT*10; //1A 800bdc8: 4b07 ldr r3, [pc, #28] @ (800bde8 ) 800bdca: 220a movs r2, #10 800bdcc: 80da strh r2, [r3, #6] CCS_MaxLoad.maxPower = PSU_MAX_POWER; //30000W 800bdce: 4b06 ldr r3, [pc, #24] @ (800bde8 ) 800bdd0: f247 5230 movw r2, #30000 @ 0x7530 800bdd4: 609a str r2, [r3, #8] CCS_SendResetReason(); 800bdd6: f000 f8b3 bl 800bf40 log_printf(LOG_INFO, "CCS init\n"); 800bdda: 4904 ldr r1, [pc, #16] @ (800bdec ) 800bddc: 2007 movs r0, #7 800bdde: f7fe fb47 bl 800a470 } 800bde2: bf00 nop 800bde4: bd80 pop {r7, pc} 800bde6: bf00 nop 800bde8: 200007a8 .word 0x200007a8 800bdec: 080142f4 .word 0x080142f4 0800bdf0 : static uint16_t crc16_ibm(const uint8_t* data, uint16_t length) { 800bdf0: b480 push {r7} 800bdf2: b085 sub sp, #20 800bdf4: af00 add r7, sp, #0 800bdf6: 6078 str r0, [r7, #4] 800bdf8: 460b mov r3, r1 800bdfa: 807b strh r3, [r7, #2] uint16_t crc = 0xFFFFu; 800bdfc: f64f 73ff movw r3, #65535 @ 0xffff 800be00: 81fb strh r3, [r7, #14] for (uint16_t i = 0; i < length; i++) { 800be02: 2300 movs r3, #0 800be04: 81bb strh r3, [r7, #12] 800be06: e022 b.n 800be4e crc ^= data[i]; 800be08: 89bb ldrh r3, [r7, #12] 800be0a: 687a ldr r2, [r7, #4] 800be0c: 4413 add r3, r2 800be0e: 781b ldrb r3, [r3, #0] 800be10: 461a mov r2, r3 800be12: 89fb ldrh r3, [r7, #14] 800be14: 4053 eors r3, r2 800be16: 81fb strh r3, [r7, #14] for (uint8_t j = 0; j < 8; j++) { 800be18: 2300 movs r3, #0 800be1a: 72fb strb r3, [r7, #11] 800be1c: e011 b.n 800be42 if (crc & 1u) { 800be1e: 89fb ldrh r3, [r7, #14] 800be20: f003 0301 and.w r3, r3, #1 800be24: 2b00 cmp r3, #0 800be26: d006 beq.n 800be36 crc = (crc >> 1) ^ 0xA001u; 800be28: 89fb ldrh r3, [r7, #14] 800be2a: 085b lsrs r3, r3, #1 800be2c: b29a uxth r2, r3 800be2e: 4b0d ldr r3, [pc, #52] @ (800be64 ) 800be30: 4053 eors r3, r2 800be32: 81fb strh r3, [r7, #14] 800be34: e002 b.n 800be3c } else { crc >>= 1; 800be36: 89fb ldrh r3, [r7, #14] 800be38: 085b lsrs r3, r3, #1 800be3a: 81fb strh r3, [r7, #14] for (uint8_t j = 0; j < 8; j++) { 800be3c: 7afb ldrb r3, [r7, #11] 800be3e: 3301 adds r3, #1 800be40: 72fb strb r3, [r7, #11] 800be42: 7afb ldrb r3, [r7, #11] 800be44: 2b07 cmp r3, #7 800be46: d9ea bls.n 800be1e for (uint16_t i = 0; i < length; i++) { 800be48: 89bb ldrh r3, [r7, #12] 800be4a: 3301 adds r3, #1 800be4c: 81bb strh r3, [r7, #12] 800be4e: 89ba ldrh r2, [r7, #12] 800be50: 887b ldrh r3, [r7, #2] 800be52: 429a cmp r2, r3 800be54: d3d8 bcc.n 800be08 } } } return crc; 800be56: 89fb ldrh r3, [r7, #14] } 800be58: 4618 mov r0, r3 800be5a: 3714 adds r7, #20 800be5c: 46bd mov sp, r7 800be5e: bc80 pop {r7} 800be60: 4770 bx lr 800be62: bf00 nop 800be64: ffffa001 .word 0xffffa001 0800be68 : static uint16_t CCS_BuildPacket(uint8_t cmd, const void* payload, uint16_t payload_len, uint8_t* out, uint16_t out_max) { 800be68: b580 push {r7, lr} 800be6a: b086 sub sp, #24 800be6c: af00 add r7, sp, #0 800be6e: 60b9 str r1, [r7, #8] 800be70: 607b str r3, [r7, #4] 800be72: 4603 mov r3, r0 800be74: 73fb strb r3, [r7, #15] 800be76: 4613 mov r3, r2 800be78: 81bb strh r3, [r7, #12] uint16_t total_len = (uint16_t)(1u + payload_len + 2u); 800be7a: 89bb ldrh r3, [r7, #12] 800be7c: 3303 adds r3, #3 800be7e: 82fb strh r3, [r7, #22] if (total_len > out_max) return 0; 800be80: 8afa ldrh r2, [r7, #22] 800be82: 8c3b ldrh r3, [r7, #32] 800be84: 429a cmp r2, r3 800be86: d901 bls.n 800be8c 800be88: 2300 movs r3, #0 800be8a: e029 b.n 800bee0 out[0] = cmd; 800be8c: 687b ldr r3, [r7, #4] 800be8e: 7bfa ldrb r2, [r7, #15] 800be90: 701a strb r2, [r3, #0] if (payload_len && payload != NULL) { 800be92: 89bb ldrh r3, [r7, #12] 800be94: 2b00 cmp r3, #0 800be96: d009 beq.n 800beac 800be98: 68bb ldr r3, [r7, #8] 800be9a: 2b00 cmp r3, #0 800be9c: d006 beq.n 800beac memcpy(&out[1], payload, payload_len); 800be9e: 687b ldr r3, [r7, #4] 800bea0: 3301 adds r3, #1 800bea2: 89ba ldrh r2, [r7, #12] 800bea4: 68b9 ldr r1, [r7, #8] 800bea6: 4618 mov r0, r3 800bea8: f007 f901 bl 80130ae } uint16_t crc = crc16_ibm(out, (uint16_t)(1u + payload_len)); 800beac: 89bb ldrh r3, [r7, #12] 800beae: 3301 adds r3, #1 800beb0: b29b uxth r3, r3 800beb2: 4619 mov r1, r3 800beb4: 6878 ldr r0, [r7, #4] 800beb6: f7ff ff9b bl 800bdf0 800beba: 4603 mov r3, r0 800bebc: 82bb strh r3, [r7, #20] out[1u + payload_len] = (uint8_t)(crc & 0xFFu); 800bebe: 89bb ldrh r3, [r7, #12] 800bec0: 3301 adds r3, #1 800bec2: 687a ldr r2, [r7, #4] 800bec4: 4413 add r3, r2 800bec6: 8aba ldrh r2, [r7, #20] 800bec8: b2d2 uxtb r2, r2 800beca: 701a strb r2, [r3, #0] out[1u + payload_len + 1u] = (uint8_t)((crc >> 8) & 0xFFu); 800becc: 8abb ldrh r3, [r7, #20] 800bece: 0a1b lsrs r3, r3, #8 800bed0: b299 uxth r1, r3 800bed2: 89bb ldrh r3, [r7, #12] 800bed4: 3302 adds r3, #2 800bed6: 687a ldr r2, [r7, #4] 800bed8: 4413 add r3, r2 800beda: b2ca uxtb r2, r1 800bedc: 701a strb r2, [r3, #0] return total_len; 800bede: 8afb ldrh r3, [r7, #22] } 800bee0: 4618 mov r0, r3 800bee2: 3718 adds r7, #24 800bee4: 46bd mov sp, r7 800bee6: bd80 pop {r7, pc} 0800bee8 : static void CCS_SendPacket(uint8_t cmd, const void* payload, uint16_t payload_len) { 800bee8: b580 push {r7, lr} 800beea: b086 sub sp, #24 800beec: af02 add r7, sp, #8 800beee: 4603 mov r3, r0 800bef0: 6039 str r1, [r7, #0] 800bef2: 71fb strb r3, [r7, #7] 800bef4: 4613 mov r3, r2 800bef6: 80bb strh r3, [r7, #4] uint16_t len = CCS_BuildPacket(cmd, payload, payload_len, tx_buffer, sizeof(tx_buffer)); 800bef8: 88ba ldrh r2, [r7, #4] 800befa: 79f8 ldrb r0, [r7, #7] 800befc: f44f 7380 mov.w r3, #256 @ 0x100 800bf00: 9300 str r3, [sp, #0] 800bf02: 4b0c ldr r3, [pc, #48] @ (800bf34 ) 800bf04: 6839 ldr r1, [r7, #0] 800bf06: f7ff ffaf bl 800be68 800bf0a: 4603 mov r3, r0 800bf0c: 81fb strh r3, [r7, #14] if (len > 0) { 800bf0e: 89fb ldrh r3, [r7, #14] 800bf10: 2b00 cmp r3, #0 800bf12: d006 beq.n 800bf22 HAL_UART_Transmit(&huart3, tx_buffer, len, 1000); 800bf14: 89fa ldrh r2, [r7, #14] 800bf16: f44f 737a mov.w r3, #1000 @ 0x3e8 800bf1a: 4906 ldr r1, [pc, #24] @ (800bf34 ) 800bf1c: 4806 ldr r0, [pc, #24] @ (800bf38 ) 800bf1e: f005 fedf bl 8011ce0 } last_cmd_sent = HAL_GetTick(); 800bf22: f001 fcd7 bl 800d8d4 800bf26: 4603 mov r3, r0 800bf28: 4a04 ldr r2, [pc, #16] @ (800bf3c ) 800bf2a: 6013 str r3, [r2, #0] } 800bf2c: bf00 nop 800bf2e: 3710 adds r7, #16 800bf30: 46bd mov sp, r7 800bf32: bd80 pop {r7, pc} 800bf34: 200008cc .word 0x200008cc 800bf38: 20001028 .word 0x20001028 800bf3c: 200007c0 .word 0x200007c0 0800bf40 : static void CCS_SendResetReason(void) { 800bf40: b580 push {r7, lr} 800bf42: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_RESET, NULL, 0); 800bf44: 2200 movs r2, #0 800bf46: 2100 movs r1, #0 800bf48: 2052 movs r0, #82 @ 0x52 800bf4a: f7ff ffcd bl 800bee8 } 800bf4e: bf00 nop 800bf50: bd80 pop {r7, pc} 0800bf52 : void CCS_SendEmergencyStop(void) { 800bf52: b580 push {r7, lr} 800bf54: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_ESTOP, NULL, 0); 800bf56: 2200 movs r2, #0 800bf58: 2100 movs r1, #0 800bf5a: 2053 movs r0, #83 @ 0x53 800bf5c: f7ff ffc4 bl 800bee8 } 800bf60: bf00 nop 800bf62: bd80 pop {r7, pc} 0800bf64 : void CCS_SendStart(void) { CCS_SendPacket(CMD_M2E_START, NULL, 0); } static void CCS_CalculateEnergy(void) { 800bf64: b580 push {r7, lr} 800bf66: b082 sub sp, #8 800bf68: af00 add r7, sp, #0 static uint32_t lastTick = 0; uint32_t currentTick = HAL_GetTick(); 800bf6a: f001 fcb3 bl 800d8d4 800bf6e: 6078 str r0, [r7, #4] uint32_t elapsedTimeMs = currentTick - lastTick; 800bf70: 4b1e ldr r3, [pc, #120] @ (800bfec ) 800bf72: 681b ldr r3, [r3, #0] 800bf74: 687a ldr r2, [r7, #4] 800bf76: 1ad3 subs r3, r2, r3 800bf78: 603b str r3, [r7, #0] lastTick = currentTick; 800bf7a: 4a1c ldr r2, [pc, #112] @ (800bfec ) 800bf7c: 687b ldr r3, [r7, #4] 800bf7e: 6013 str r3, [r2, #0] CCS_Power = CONN.MeasuredVoltage * CONN.MeasuredCurrent / 10; 800bf80: 4b1b ldr r3, [pc, #108] @ (800bff0 ) 800bf82: f8b3 3013 ldrh.w r3, [r3, #19] 800bf86: b29b uxth r3, r3 800bf88: 461a mov r2, r3 800bf8a: 4b19 ldr r3, [pc, #100] @ (800bff0 ) 800bf8c: f8b3 3015 ldrh.w r3, [r3, #21] 800bf90: b29b uxth r3, r3 800bf92: fb02 f303 mul.w r3, r2, r3 800bf96: 4a17 ldr r2, [pc, #92] @ (800bff4 ) 800bf98: fb82 1203 smull r1, r2, r2, r3 800bf9c: 1092 asrs r2, r2, #2 800bf9e: 17db asrs r3, r3, #31 800bfa0: 1ad3 subs r3, r2, r3 800bfa2: 461a mov r2, r3 800bfa4: 4b14 ldr r3, [pc, #80] @ (800bff8 ) 800bfa6: 601a str r2, [r3, #0] CCS_EnergyWs += (CCS_Power * elapsedTimeMs) / 1000; 800bfa8: 4b13 ldr r3, [pc, #76] @ (800bff8 ) 800bfaa: 681b ldr r3, [r3, #0] 800bfac: 683a ldr r2, [r7, #0] 800bfae: fb02 f303 mul.w r3, r2, r3 800bfb2: 4a12 ldr r2, [pc, #72] @ (800bffc ) 800bfb4: fba2 2303 umull r2, r3, r2, r3 800bfb8: 099a lsrs r2, r3, #6 800bfba: 4b11 ldr r3, [pc, #68] @ (800c000 ) 800bfbc: 681b ldr r3, [r3, #0] 800bfbe: 4413 add r3, r2 800bfc0: 4a0f ldr r2, [pc, #60] @ (800c000 ) 800bfc2: 6013 str r3, [r2, #0] if(CCS_EvseState == Unplugged) { 800bfc4: 4b0f ldr r3, [pc, #60] @ (800c004 ) 800bfc6: 781b ldrb r3, [r3, #0] 800bfc8: 2b01 cmp r3, #1 800bfca: d102 bne.n 800bfd2 CCS_EnergyWs = 0; 800bfcc: 4b0c ldr r3, [pc, #48] @ (800c000 ) 800bfce: 2200 movs r2, #0 800bfd0: 601a str r2, [r3, #0] } CCS_Energy = CCS_EnergyWs / 3600; 800bfd2: 4b0b ldr r3, [pc, #44] @ (800c000 ) 800bfd4: 681b ldr r3, [r3, #0] 800bfd6: 4a0c ldr r2, [pc, #48] @ (800c008 ) 800bfd8: fba2 2303 umull r2, r3, r2, r3 800bfdc: 0adb lsrs r3, r3, #11 800bfde: 4a0b ldr r2, [pc, #44] @ (800c00c ) 800bfe0: 6013 str r3, [r2, #0] } 800bfe2: bf00 nop 800bfe4: 3708 adds r7, #8 800bfe6: 46bd mov sp, r7 800bfe8: bd80 pop {r7, pc} 800bfea: bf00 nop 800bfec: 20000a30 .word 0x20000a30 800bff0: 200001d4 .word 0x200001d4 800bff4: 66666667 .word 0x66666667 800bff8: 200007b4 .word 0x200007b4 800bffc: 10624dd3 .word 0x10624dd3 800c000: 200007b8 .word 0x200007b8 800c004: 20000a24 .word 0x20000a24 800c008: 91a2b3c5 .word 0x91a2b3c5 800c00c: 200007bc .word 0x200007bc 0800c010 : static void send_state(void) { 800c010: b580 push {r7, lr} 800c012: af00 add r7, sp, #0 CCS_CalculateEnergy(); 800c014: f7ff ffa6 bl 800bf64 CCS_State.DutyCycle = CP_GetDuty(); 800c018: f7fe f88e bl 800a138 800c01c: 4603 mov r3, r0 800c01e: 461a mov r2, r3 800c020: 4b2a ldr r3, [pc, #168] @ (800c0cc ) 800c022: 701a strb r2, [r3, #0] CCS_State.OutputEnabled = PSU0.CONT_enabled; 800c024: 4b2a ldr r3, [pc, #168] @ (800c0d0 ) 800c026: 7ada ldrb r2, [r3, #11] 800c028: 4b28 ldr r3, [pc, #160] @ (800c0cc ) 800c02a: 705a strb r2, [r3, #1] CCS_State.MeasuredVoltage = (uint16_t)CONN.MeasuredVoltage; 800c02c: 4b29 ldr r3, [pc, #164] @ (800c0d4 ) 800c02e: f8b3 3013 ldrh.w r3, [r3, #19] 800c032: b29a uxth r2, r3 800c034: 4b25 ldr r3, [pc, #148] @ (800c0cc ) 800c036: 805a strh r2, [r3, #2] CCS_State.MeasuredCurrent = (uint16_t)CONN.MeasuredCurrent; 800c038: 4b26 ldr r3, [pc, #152] @ (800c0d4 ) 800c03a: f8b3 3015 ldrh.w r3, [r3, #21] 800c03e: b29a uxth r2, r3 800c040: 4b22 ldr r3, [pc, #136] @ (800c0cc ) 800c042: 809a strh r2, [r3, #4] CCS_State.Power = CCS_Power; 800c044: 4b24 ldr r3, [pc, #144] @ (800c0d8 ) 800c046: 681b ldr r3, [r3, #0] 800c048: 4a20 ldr r2, [pc, #128] @ (800c0cc ) 800c04a: f8c2 3006 str.w r3, [r2, #6] CCS_State.Energy = CCS_Energy; 800c04e: 4b23 ldr r3, [pc, #140] @ (800c0dc ) 800c050: 681b ldr r3, [r3, #0] 800c052: 4a1e ldr r2, [pc, #120] @ (800c0cc ) 800c054: f8c2 300a str.w r3, [r2, #10] if(CCS_ConnectorState == CCS_CONNECTED){ 800c058: 4b21 ldr r3, [pc, #132] @ (800c0e0 ) 800c05a: 781b ldrb r3, [r3, #0] 800c05c: 2b03 cmp r3, #3 800c05e: d104 bne.n 800c06a CCS_State.CpState = cp_state_buffer; 800c060: 4b20 ldr r3, [pc, #128] @ (800c0e4 ) 800c062: 781a ldrb r2, [r3, #0] 800c064: 4b19 ldr r3, [pc, #100] @ (800c0cc ) 800c066: 74da strb r2, [r3, #19] 800c068: e002 b.n 800c070 } else { CCS_State.CpState = EV_STATE_A_IDLE; 800c06a: 4b18 ldr r3, [pc, #96] @ (800c0cc ) 800c06c: 2200 movs r2, #0 800c06e: 74da strb r2, [r3, #19] } CCS_State.MaxVoltage = CCS_MaxLoad.maxVoltage; 800c070: 4b1d ldr r3, [pc, #116] @ (800c0e8 ) 800c072: 881a ldrh r2, [r3, #0] 800c074: 4b15 ldr r3, [pc, #84] @ (800c0cc ) 800c076: 829a strh r2, [r3, #20] CCS_State.MinVoltage = CCS_MaxLoad.minVoltage; 800c078: 4b1b ldr r3, [pc, #108] @ (800c0e8 ) 800c07a: 885a ldrh r2, [r3, #2] 800c07c: 4b13 ldr r3, [pc, #76] @ (800c0cc ) 800c07e: 82da strh r2, [r3, #22] CCS_State.MaxCurrent = CCS_MaxLoad.maxCurrent; 800c080: 4b19 ldr r3, [pc, #100] @ (800c0e8 ) 800c082: 889a ldrh r2, [r3, #4] 800c084: 4b11 ldr r3, [pc, #68] @ (800c0cc ) 800c086: 831a strh r2, [r3, #24] CCS_State.MinCurrent = CCS_MaxLoad.minCurrent; 800c088: 4b17 ldr r3, [pc, #92] @ (800c0e8 ) 800c08a: 88da ldrh r2, [r3, #6] 800c08c: 4b0f ldr r3, [pc, #60] @ (800c0cc ) 800c08e: 835a strh r2, [r3, #26] CCS_State.MaxPower = CCS_MaxLoad.maxPower; 800c090: 4b15 ldr r3, [pc, #84] @ (800c0e8 ) 800c092: 689b ldr r3, [r3, #8] 800c094: 4a0d ldr r2, [pc, #52] @ (800c0cc ) 800c096: 61d3 str r3, [r2, #28] CCS_State.IsolationValid = isolation_enable; 800c098: 4b14 ldr r3, [pc, #80] @ (800c0ec ) 800c09a: 781a ldrb r2, [r3, #0] 800c09c: 4b0b ldr r3, [pc, #44] @ (800c0cc ) 800c09e: 749a strb r2, [r3, #18] CCS_State.IsolationResistance = 900000; 800c0a0: 4a0a ldr r2, [pc, #40] @ (800c0cc ) 800c0a2: 2300 movs r3, #0 800c0a4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800c0a8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800c0ac: f443 433b orr.w r3, r3, #47872 @ 0xbb00 800c0b0: f043 03a0 orr.w r3, r3, #160 @ 0xa0 800c0b4: 81d3 strh r3, [r2, #14] 800c0b6: 2300 movs r3, #0 800c0b8: f043 030d orr.w r3, r3, #13 800c0bc: 8213 strh r3, [r2, #16] CCS_SendPacket(CMD_M2E_STATE, &CCS_State, sizeof(CCS_State)); 800c0be: 2220 movs r2, #32 800c0c0: 4902 ldr r1, [pc, #8] @ (800c0cc ) 800c0c2: 2050 movs r0, #80 @ 0x50 800c0c4: f7ff ff10 bl 800bee8 } 800c0c8: bf00 nop 800c0ca: bd80 pop {r7, pc} 800c0cc: 200009d8 .word 0x200009d8 800c0d0: 20000724 .word 0x20000724 800c0d4: 200001d4 .word 0x200001d4 800c0d8: 200007b4 .word 0x200007b4 800c0dc: 200007bc .word 0x200007bc 800c0e0: 20000050 .word 0x20000050 800c0e4: 2000004f .word 0x2000004f 800c0e8: 200007a8 .word 0x200007a8 800c0ec: 200009d0 .word 0x200009d0 0800c0f0 : static uint16_t expected_payload_len(uint8_t cmd) { 800c0f0: b480 push {r7} 800c0f2: b083 sub sp, #12 800c0f4: af00 add r7, sp, #0 800c0f6: 4603 mov r3, r0 800c0f8: 71fb strb r3, [r7, #7] switch (cmd) { 800c0fa: 79fb ldrb r3, [r7, #7] 800c0fc: 3b40 subs r3, #64 @ 0x40 800c0fe: 2b09 cmp r3, #9 800c100: d82a bhi.n 800c158 800c102: a201 add r2, pc, #4 @ (adr r2, 800c108 ) 800c104: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c108: 0800c131 .word 0x0800c131 800c10c: 0800c135 .word 0x0800c135 800c110: 0800c139 .word 0x0800c139 800c114: 0800c13d .word 0x0800c13d 800c118: 0800c141 .word 0x0800c141 800c11c: 0800c145 .word 0x0800c145 800c120: 0800c149 .word 0x0800c149 800c124: 0800c14d .word 0x0800c14d 800c128: 0800c151 .word 0x0800c151 800c12c: 0800c155 .word 0x0800c155 case CMD_E2M_PWM_DUTY: return sizeof(e2m_pwm_duty_t); 800c130: 2301 movs r3, #1 800c132: e013 b.n 800c15c case CMD_E2M_ENABLE_OUTPUT: return sizeof(e2m_enable_output_t); 800c134: 2301 movs r3, #1 800c136: e011 b.n 800c15c case CMD_E2M_RESET: return sizeof(e2m_reset_t); 800c138: 2301 movs r3, #1 800c13a: e00f b.n 800c15c case CMD_E2M_ENABLE: return sizeof(e2m_enable_t); 800c13c: 2301 movs r3, #1 800c13e: e00d b.n 800c15c case CMD_E2M_REPLUG: return sizeof(e2m_replug_t); 800c140: 2301 movs r3, #1 800c142: e00b b.n 800c15c case CMD_E2M_SET_OUTPUT_VOLTAGE: return sizeof(e2m_set_output_t); 800c144: 2304 movs r3, #4 800c146: e009 b.n 800c15c case CMD_E2M_ISOLATION_CONTROL: return sizeof(e2m_isolation_control_t); 800c148: 2301 movs r3, #1 800c14a: e007 b.n 800c15c case CMD_E2M_EV_INFO: return sizeof(CCS_EvInfo_t); 800c14c: 232c movs r3, #44 @ 0x2c 800c14e: e005 b.n 800c15c case CMD_E2M_EVSE_STATE: return sizeof(CONN_State_t); 800c150: 2301 movs r3, #1 800c152: e003 b.n 800c15c case CMD_E2M_KEEP_ALIVE: return 0; 800c154: 2300 movs r3, #0 800c156: e001 b.n 800c15c default: return 0xFFFFu; 800c158: f64f 73ff movw r3, #65535 @ 0xffff } } 800c15c: 4618 mov r0, r3 800c15e: 370c adds r7, #12 800c160: 46bd mov sp, r7 800c162: bc80 pop {r7} 800c164: 4770 bx lr 800c166: bf00 nop 0800c168 : static void apply_command(uint8_t cmd, const uint8_t* payload, uint16_t payload_len) { 800c168: b5f0 push {r4, r5, r6, r7, lr} 800c16a: b08b sub sp, #44 @ 0x2c 800c16c: af00 add r7, sp, #0 800c16e: 4603 mov r3, r0 800c170: 6039 str r1, [r7, #0] 800c172: 71fb strb r3, [r7, #7] 800c174: 4613 mov r3, r2 800c176: 80bb strh r3, [r7, #4] (void)payload_len; last_host_seen = HAL_GetTick(); 800c178: f001 fbac bl 800d8d4 800c17c: 4603 mov r3, r0 800c17e: 4a58 ldr r2, [pc, #352] @ (800c2e0 ) 800c180: 6013 str r3, [r2, #0] switch (cmd) { 800c182: 79fb ldrb r3, [r7, #7] 800c184: 3b40 subs r3, #64 @ 0x40 800c186: 2b09 cmp r3, #9 800c188: f200 80a3 bhi.w 800c2d2 800c18c: a201 add r2, pc, #4 @ (adr r2, 800c194 ) 800c18e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c192: bf00 nop 800c194: 0800c1bd .word 0x0800c1bd 800c198: 0800c1eb .word 0x0800c1eb 800c19c: 0800c205 .word 0x0800c205 800c1a0: 0800c227 .word 0x0800c227 800c1a4: 0800c2bb .word 0x0800c2bb 800c1a8: 0800c241 .word 0x0800c241 800c1ac: 0800c25f .word 0x0800c25f 800c1b0: 0800c26d .word 0x0800c26d 800c1b4: 0800c2b1 .word 0x0800c2b1 800c1b8: 0800c2c7 .word 0x0800c2c7 case CMD_E2M_PWM_DUTY: { const e2m_pwm_duty_t* p = (const e2m_pwm_duty_t*)payload; 800c1bc: 683b ldr r3, [r7, #0] 800c1be: 60fb str r3, [r7, #12] uint8_t duty = p->pwm_duty_percent; 800c1c0: 68fb ldr r3, [r7, #12] 800c1c2: 781b ldrb r3, [r3, #0] 800c1c4: f887 3027 strb.w r3, [r7, #39] @ 0x27 if (duty > 100) duty = 100; 800c1c8: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 800c1cc: 2b64 cmp r3, #100 @ 0x64 800c1ce: d902 bls.n 800c1d6 800c1d0: 2364 movs r3, #100 @ 0x64 800c1d2: f887 3027 strb.w r3, [r7, #39] @ 0x27 pwm_duty_percent = duty; 800c1d6: 4a43 ldr r2, [pc, #268] @ (800c2e4 ) 800c1d8: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 800c1dc: 7013 strb r3, [r2, #0] CP_SetDuty(duty); 800c1de: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 800c1e2: 4618 mov r0, r3 800c1e4: f7fd ff80 bl 800a0e8 break; 800c1e8: e076 b.n 800c2d8 } case CMD_E2M_ENABLE_OUTPUT: { const e2m_enable_output_t* p = (const e2m_enable_output_t*)payload; 800c1ea: 683b ldr r3, [r7, #0] 800c1ec: 613b str r3, [r7, #16] ev_enable_output = (p->enable_output != 0); 800c1ee: 693b ldr r3, [r7, #16] 800c1f0: 781b ldrb r3, [r3, #0] 800c1f2: 2b00 cmp r3, #0 800c1f4: bf14 ite ne 800c1f6: 2301 movne r3, #1 800c1f8: 2300 moveq r3, #0 800c1fa: b2db uxtb r3, r3 800c1fc: 461a mov r2, r3 800c1fe: 4b3a ldr r3, [pc, #232] @ (800c2e8 ) 800c200: 701a strb r2, [r3, #0] break; 800c202: e069 b.n 800c2d8 } case CMD_E2M_RESET: { const e2m_reset_t* p = (const e2m_reset_t*)payload; 800c204: 683b ldr r3, [r7, #0] 800c206: 617b str r3, [r7, #20] if (p->reset) { 800c208: 697b ldr r3, [r7, #20] 800c20a: 781b ldrb r3, [r3, #0] 800c20c: 2b00 cmp r3, #0 800c20e: d062 beq.n 800c2d6 log_printf(LOG_WARN, "Everest reset command\n"); 800c210: 4936 ldr r1, [pc, #216] @ (800c2ec ) 800c212: 2005 movs r0, #5 800c214: f7fe f92c bl 800a470 CCS_SendResetReason(); 800c218: f7ff fe92 bl 800bf40 HAL_Delay(10); 800c21c: 200a movs r0, #10 800c21e: f001 fb63 bl 800d8e8 NVIC_SystemReset(); 800c222: f7ff fba9 bl 800b978 <__NVIC_SystemReset> } break; } case CMD_E2M_ENABLE: { const e2m_enable_t* p = (const e2m_enable_t*)payload; 800c226: 683b ldr r3, [r7, #0] 800c228: 61bb str r3, [r7, #24] enabled = (p->enable != 0); 800c22a: 69bb ldr r3, [r7, #24] 800c22c: 781b ldrb r3, [r3, #0] 800c22e: 2b00 cmp r3, #0 800c230: bf14 ite ne 800c232: 2301 movne r3, #1 800c234: 2300 moveq r3, #0 800c236: b2db uxtb r3, r3 800c238: 461a mov r2, r3 800c23a: 4b2d ldr r3, [pc, #180] @ (800c2f0 ) 800c23c: 701a strb r2, [r3, #0] (void)enabled; break; 800c23e: e04b b.n 800c2d8 } case CMD_E2M_SET_OUTPUT_VOLTAGE: { const e2m_set_output_t* p = (const e2m_set_output_t*)payload; 800c240: 683b ldr r3, [r7, #0] 800c242: 61fb str r3, [r7, #28] CONN.RequestedVoltage = p->voltage_V; 800c244: 69fb ldr r3, [r7, #28] 800c246: 881b ldrh r3, [r3, #0] 800c248: b29a uxth r2, r3 800c24a: 4b2a ldr r3, [pc, #168] @ (800c2f4 ) 800c24c: f8a3 200f strh.w r2, [r3, #15] CONN.WantedCurrent = p->current_0p1A; 800c250: 69fb ldr r3, [r7, #28] 800c252: 885b ldrh r3, [r3, #2] 800c254: b29a uxth r2, r3 800c256: 4b27 ldr r3, [pc, #156] @ (800c2f4 ) 800c258: f8a3 201b strh.w r2, [r3, #27] break; 800c25c: e03c b.n 800c2d8 } case CMD_E2M_ISOLATION_CONTROL: { const e2m_isolation_control_t* p = (const e2m_isolation_control_t*)payload; 800c25e: 683b ldr r3, [r7, #0] 800c260: 623b str r3, [r7, #32] isolation_enable = p->command; 800c262: 6a3b ldr r3, [r7, #32] 800c264: 781a ldrb r2, [r3, #0] 800c266: 4b24 ldr r3, [pc, #144] @ (800c2f8 ) 800c268: 701a strb r2, [r3, #0] break; 800c26a: e035 b.n 800c2d8 } case CMD_E2M_EV_INFO: { memcpy(&CCS_EvInfo, payload, sizeof(CCS_EvInfo_t)); 800c26c: 4a23 ldr r2, [pc, #140] @ (800c2fc ) 800c26e: 683b ldr r3, [r7, #0] 800c270: 461c mov r4, r3 800c272: 4616 mov r6, r2 800c274: f104 0c20 add.w ip, r4, #32 800c278: 4635 mov r5, r6 800c27a: 4623 mov r3, r4 800c27c: 6818 ldr r0, [r3, #0] 800c27e: 6859 ldr r1, [r3, #4] 800c280: 689a ldr r2, [r3, #8] 800c282: 68db ldr r3, [r3, #12] 800c284: c50f stmia r5!, {r0, r1, r2, r3} 800c286: 3410 adds r4, #16 800c288: 3610 adds r6, #16 800c28a: 4564 cmp r4, ip 800c28c: d1f4 bne.n 800c278 800c28e: 4633 mov r3, r6 800c290: 4622 mov r2, r4 800c292: 6810 ldr r0, [r2, #0] 800c294: 6851 ldr r1, [r2, #4] 800c296: 6892 ldr r2, [r2, #8] 800c298: c307 stmia r3!, {r0, r1, r2} CONN.SOC = (uint8_t)(CCS_EvInfo.soc / 10); 800c29a: 4b18 ldr r3, [pc, #96] @ (800c2fc ) 800c29c: 885b ldrh r3, [r3, #2] 800c29e: 4a18 ldr r2, [pc, #96] @ (800c300 ) 800c2a0: fba2 2303 umull r2, r3, r2, r3 800c2a4: 08db lsrs r3, r3, #3 800c2a6: b29b uxth r3, r3 800c2a8: b2da uxtb r2, r3 800c2aa: 4b12 ldr r3, [pc, #72] @ (800c2f4 ) 800c2ac: 709a strb r2, [r3, #2] break; 800c2ae: e013 b.n 800c2d8 } case CMD_E2M_EVSE_STATE: { CCS_EvseState = (CONN_State_t)payload[0]; 800c2b0: 683b ldr r3, [r7, #0] 800c2b2: 781a ldrb r2, [r3, #0] 800c2b4: 4b13 ldr r3, [pc, #76] @ (800c304 ) 800c2b6: 701a strb r2, [r3, #0] break; 800c2b8: e00e b.n 800c2d8 } case CMD_E2M_REPLUG: { (void)payload; CP_SetDuty(pwm_duty_percent); 800c2ba: 4b0a ldr r3, [pc, #40] @ (800c2e4 ) 800c2bc: 781b ldrb r3, [r3, #0] 800c2be: 4618 mov r0, r3 800c2c0: f7fd ff12 bl 800a0e8 break; 800c2c4: e008 b.n 800c2d8 } case CMD_E2M_KEEP_ALIVE: { last_host_seen = HAL_GetTick(); 800c2c6: f001 fb05 bl 800d8d4 800c2ca: 4603 mov r3, r0 800c2cc: 4a04 ldr r2, [pc, #16] @ (800c2e0 ) 800c2ce: 6013 str r3, [r2, #0] break; 800c2d0: e002 b.n 800c2d8 } default: break; 800c2d2: bf00 nop 800c2d4: e000 b.n 800c2d8 break; 800c2d6: bf00 nop } } 800c2d8: bf00 nop 800c2da: 372c adds r7, #44 @ 0x2c 800c2dc: 46bd mov sp, r7 800c2de: bdf0 pop {r4, r5, r6, r7, pc} 800c2e0: 200009d4 .word 0x200009d4 800c2e4: 2000004e .word 0x2000004e 800c2e8: 200007c9 .word 0x200007c9 800c2ec: 08014300 .word 0x08014300 800c2f0: 200009cf .word 0x200009cf 800c2f4: 200001d4 .word 0x200001d4 800c2f8: 200009d0 .word 0x200009d0 800c2fc: 200009f8 .word 0x200009f8 800c300: cccccccd .word 0xcccccccd 800c304: 20000a24 .word 0x20000a24 0800c308 : static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len) { 800c308: b580 push {r7, lr} 800c30a: b086 sub sp, #24 800c30c: af00 add r7, sp, #0 800c30e: 6078 str r0, [r7, #4] 800c310: 460b mov r3, r1 800c312: 807b strh r3, [r7, #2] if (packet_len < 3) return 0; 800c314: 887b ldrh r3, [r7, #2] 800c316: 2b02 cmp r3, #2 800c318: d801 bhi.n 800c31e 800c31a: 2300 movs r3, #0 800c31c: e05a b.n 800c3d4 uint8_t cmd = packet[0]; 800c31e: 687b ldr r3, [r7, #4] 800c320: 781b ldrb r3, [r3, #0] 800c322: 75fb strb r3, [r7, #23] uint16_t payload_len = (uint16_t)(packet_len - 3); 800c324: 887b ldrh r3, [r7, #2] 800c326: 3b03 subs r3, #3 800c328: 82bb strh r3, [r7, #20] uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c32a: 887b ldrh r3, [r7, #2] 800c32c: 3b02 subs r3, #2 800c32e: 687a ldr r2, [r7, #4] 800c330: 4413 add r3, r2 800c332: 781b ldrb r3, [r3, #0] 800c334: b21a sxth r2, r3 (uint16_t)packet[packet_len - 1u] << 8; 800c336: 887b ldrh r3, [r7, #2] 800c338: 3b01 subs r3, #1 800c33a: 6879 ldr r1, [r7, #4] 800c33c: 440b add r3, r1 800c33e: 781b ldrb r3, [r3, #0] uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c340: b21b sxth r3, r3 800c342: 021b lsls r3, r3, #8 800c344: b21b sxth r3, r3 800c346: 4313 orrs r3, r2 800c348: b21b sxth r3, r3 800c34a: 827b strh r3, [r7, #18] uint16_t calculated_crc = crc16_ibm(packet, (uint16_t)(1 + payload_len)); 800c34c: 8abb ldrh r3, [r7, #20] 800c34e: 3301 adds r3, #1 800c350: b29b uxth r3, r3 800c352: 4619 mov r1, r3 800c354: 6878 ldr r0, [r7, #4] 800c356: f7ff fd4b bl 800bdf0 800c35a: 4603 mov r3, r0 800c35c: 823b strh r3, [r7, #16] if (received_crc != calculated_crc) { 800c35e: 8a7a ldrh r2, [r7, #18] 800c360: 8a3b ldrh r3, [r7, #16] 800c362: 429a cmp r2, r3 800c364: d005 beq.n 800c372 log_printf(LOG_ERR, "Packet CRC error\n"); 800c366: 491d ldr r1, [pc, #116] @ (800c3dc ) 800c368: 2004 movs r0, #4 800c36a: f7fe f881 bl 800a470 return 0; 800c36e: 2300 movs r3, #0 800c370: e030 b.n 800c3d4 } uint16_t expected_len = expected_payload_len(cmd); 800c372: 7dfb ldrb r3, [r7, #23] 800c374: 4618 mov r0, r3 800c376: f7ff febb bl 800c0f0 800c37a: 4603 mov r3, r0 800c37c: 81fb strh r3, [r7, #14] if (expected_len == 0xFFFF) { 800c37e: 89fb ldrh r3, [r7, #14] 800c380: f64f 72ff movw r2, #65535 @ 0xffff 800c384: 4293 cmp r3, r2 800c386: d107 bne.n 800c398 log_printf(LOG_WARN, "Unknown cmd 0x%02x\n", cmd); 800c388: 7dfb ldrb r3, [r7, #23] 800c38a: 461a mov r2, r3 800c38c: 4914 ldr r1, [pc, #80] @ (800c3e0 ) 800c38e: 2005 movs r0, #5 800c390: f7fe f86e bl 800a470 return 0; 800c394: 2300 movs r3, #0 800c396: e01d b.n 800c3d4 } if (expected_len != payload_len) { 800c398: 89fa ldrh r2, [r7, #14] 800c39a: 8abb ldrh r3, [r7, #20] 800c39c: 429a cmp r2, r3 800c39e: d007 beq.n 800c3b0 log_printf(LOG_ERR, "Packet len mismatch cmd=0x%02x\n", cmd); 800c3a0: 7dfb ldrb r3, [r7, #23] 800c3a2: 461a mov r2, r3 800c3a4: 490f ldr r1, [pc, #60] @ (800c3e4 ) 800c3a6: 2004 movs r0, #4 800c3a8: f7fe f862 bl 800a470 return 0; 800c3ac: 2300 movs r3, #0 800c3ae: e011 b.n 800c3d4 } if (payload_len > 0) { 800c3b0: 8abb ldrh r3, [r7, #20] 800c3b2: 2b00 cmp r3, #0 800c3b4: d007 beq.n 800c3c6 apply_command(cmd, &packet[1], payload_len); 800c3b6: 687b ldr r3, [r7, #4] 800c3b8: 1c59 adds r1, r3, #1 800c3ba: 8aba ldrh r2, [r7, #20] 800c3bc: 7dfb ldrb r3, [r7, #23] 800c3be: 4618 mov r0, r3 800c3c0: f7ff fed2 bl 800c168 800c3c4: e005 b.n 800c3d2 } else { apply_command(cmd, NULL, 0); 800c3c6: 7dfb ldrb r3, [r7, #23] 800c3c8: 2200 movs r2, #0 800c3ca: 2100 movs r1, #0 800c3cc: 4618 mov r0, r3 800c3ce: f7ff fecb bl 800c168 } return 1; 800c3d2: 2301 movs r3, #1 } 800c3d4: 4618 mov r0, r3 800c3d6: 3718 adds r7, #24 800c3d8: 46bd mov sp, r7 800c3da: bd80 pop {r7, pc} 800c3dc: 08014318 .word 0x08014318 800c3e0: 0801432c .word 0x0801432c 800c3e4: 08014340 .word 0x08014340 0800c3e8 : .fw_version_major = 0, .fw_version_minor = 0, .fw_version_patch = 0, }; void ReadVersion(){ 800c3e8: b480 push {r7} 800c3ea: af00 add r7, sp, #0 infoPacket.serialNumber = InfoBlock->serialNumber; 800c3ec: 4b0e ldr r3, [pc, #56] @ (800c428 ) 800c3ee: 681b ldr r3, [r3, #0] 800c3f0: 681b ldr r3, [r3, #0] 800c3f2: b29a uxth r2, r3 800c3f4: 4b0d ldr r3, [pc, #52] @ (800c42c ) 800c3f6: 801a strh r2, [r3, #0] infoPacket.boardVersion = InfoBlock->boardVersion; 800c3f8: 4b0b ldr r3, [pc, #44] @ (800c428 ) 800c3fa: 681b ldr r3, [r3, #0] 800c3fc: 795a ldrb r2, [r3, #5] 800c3fe: 4b0b ldr r3, [pc, #44] @ (800c42c ) 800c400: 709a strb r2, [r3, #2] infoPacket.stationType = InfoBlock->stationType; 800c402: 4b09 ldr r3, [pc, #36] @ (800c428 ) 800c404: 681b ldr r3, [r3, #0] 800c406: 791a ldrb r2, [r3, #4] 800c408: 4b08 ldr r3, [pc, #32] @ (800c42c ) 800c40a: 70da strb r2, [r3, #3] infoPacket.fw_version_major = FW_VERSION_MAJOR; 800c40c: 4b07 ldr r3, [pc, #28] @ (800c42c ) 800c40e: 2201 movs r2, #1 800c410: 809a strh r2, [r3, #4] infoPacket.fw_version_minor = FW_VERSION_MINOR; 800c412: 4b06 ldr r3, [pc, #24] @ (800c42c ) 800c414: 2200 movs r2, #0 800c416: 80da strh r2, [r3, #6] infoPacket.fw_version_patch = FW_VERSION_PATCH; 800c418: 4b04 ldr r3, [pc, #16] @ (800c42c ) 800c41a: 2203 movs r2, #3 800c41c: 811a strh r2, [r3, #8] } 800c41e: bf00 nop 800c420: 46bd mov sp, r7 800c422: bc80 pop {r7} 800c424: 4770 bx lr 800c426: bf00 nop 800c428: 20000000 .word 0x20000000 800c42c: 20000eb0 .word 0x20000eb0 0800c430 : // Внешняя функция обработки команд (определена в serial_handler.c) extern void SC_CommandHandler(ReceivedCommand_t* cmd); void SC_Init() { 800c430: b580 push {r7, lr} 800c432: af00 add r7, sp, #0 // Обнуляем структуру memset(&serial_control, 0, sizeof(SerialControl_t)); 800c434: f44f 7204 mov.w r2, #528 @ 0x210 800c438: 2100 movs r1, #0 800c43a: 4805 ldr r0, [pc, #20] @ (800c450 ) 800c43c: f006 fdbc bl 8012fb8 memset(&serial_iso, 0, sizeof(serial_iso)); 800c440: f44f 7204 mov.w r2, #528 @ 0x210 800c444: 2100 movs r1, #0 800c446: 4803 ldr r0, [pc, #12] @ (800c454 ) 800c448: f006 fdb6 bl 8012fb8 } 800c44c: bf00 nop 800c44e: bd80 pop {r7, pc} 800c450: 20000a34 .word 0x20000a34 800c454: 20000c44 .word 0x20000c44 0800c458 : void SC_Task() { 800c458: b580 push {r7, lr} 800c45a: af00 add r7, sp, #0 // Запуск приема в режиме прерывания с ожиданием idle if((huart2.RxState == HAL_UART_STATE_READY) && (serial_control.command_ready == 0)) HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c45c: 4b2a ldr r3, [pc, #168] @ (800c508 ) 800c45e: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800c462: b2db uxtb r3, r3 800c464: 2b20 cmp r3, #32 800c466: d10a bne.n 800c47e 800c468: 4b28 ldr r3, [pc, #160] @ (800c50c ) 800c46a: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800c46e: b2db uxtb r3, r3 800c470: 2b00 cmp r3, #0 800c472: d104 bne.n 800c47e 800c474: 22ff movs r2, #255 @ 0xff 800c476: 4926 ldr r1, [pc, #152] @ (800c510 ) 800c478: 4823 ldr r0, [pc, #140] @ (800c508 ) 800c47a: f005 fcf1 bl 8011e60 if((huart5.RxState == HAL_UART_STATE_READY)) HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c47e: 4b25 ldr r3, [pc, #148] @ (800c514 ) 800c480: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800c484: b2db uxtb r3, r3 800c486: 2b20 cmp r3, #32 800c488: d104 bne.n 800c494 800c48a: 22ff movs r2, #255 @ 0xff 800c48c: 4922 ldr r1, [pc, #136] @ (800c518 ) 800c48e: 4821 ldr r0, [pc, #132] @ (800c514 ) 800c490: f005 fce6 bl 8011e60 // Проверка таймаута отправки пакета (больше 100 мс) if (huart2.gState == HAL_UART_STATE_BUSY_TX && serial_control.tx_tick != 0) { 800c494: 4b1c ldr r3, [pc, #112] @ (800c508 ) 800c496: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800c49a: b2db uxtb r3, r3 800c49c: 2b21 cmp r3, #33 @ 0x21 800c49e: d119 bne.n 800c4d4 800c4a0: 4b1a ldr r3, [pc, #104] @ (800c50c ) 800c4a2: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800c4a6: 2b00 cmp r3, #0 800c4a8: d014 beq.n 800c4d4 if ((HAL_GetTick() - serial_control.tx_tick) > 100) { 800c4aa: f001 fa13 bl 800d8d4 800c4ae: 4602 mov r2, r0 800c4b0: 4b16 ldr r3, [pc, #88] @ (800c50c ) 800c4b2: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800c4b6: 1ad3 subs r3, r2, r3 800c4b8: 2b64 cmp r3, #100 @ 0x64 800c4ba: d90b bls.n 800c4d4 // Таймаут: принудительно сбрасываем передачу HAL_UART_Abort_IT(&huart2); 800c4bc: 4812 ldr r0, [pc, #72] @ (800c508 ) 800c4be: f005 fd2d bl 8011f1c // Выключаем DIR при сбросе передачи HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800c4c2: 2200 movs r2, #0 800c4c4: 2110 movs r1, #16 800c4c6: 4815 ldr r0, [pc, #84] @ (800c51c ) 800c4c8: f003 fa15 bl 800f8f6 serial_control.tx_tick = 0; // Сбрасываем tick 800c4cc: 4b0f ldr r3, [pc, #60] @ (800c50c ) 800c4ce: 2200 movs r2, #0 800c4d0: f8c3 220c str.w r2, [r3, #524] @ 0x20c } } // Проверка наличия принятой команды для обработки if (serial_control.command_ready && (huart2.gState != HAL_UART_STATE_BUSY_TX)) { 800c4d4: 4b0d ldr r3, [pc, #52] @ (800c50c ) 800c4d6: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800c4da: b2db uxtb r3, r3 800c4dc: 2b00 cmp r3, #0 800c4de: d011 beq.n 800c504 800c4e0: 4b09 ldr r3, [pc, #36] @ (800c508 ) 800c4e2: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800c4e6: b2db uxtb r3, r3 800c4e8: 2b21 cmp r3, #33 @ 0x21 800c4ea: d00b beq.n 800c504 // HAL_Delay(2); SC_CommandHandler(&serial_control.received_command); 800c4ec: 480c ldr r0, [pc, #48] @ (800c520 ) 800c4ee: f000 f9ed bl 800c8cc HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c4f2: 22ff movs r2, #255 @ 0xff 800c4f4: 4906 ldr r1, [pc, #24] @ (800c510 ) 800c4f6: 4804 ldr r0, [pc, #16] @ (800c508 ) 800c4f8: f005 fcb2 bl 8011e60 serial_control.command_ready = 0; // Сбрасываем флаг 800c4fc: 4b03 ldr r3, [pc, #12] @ (800c50c ) 800c4fe: 2200 movs r2, #0 800c500: f883 2208 strb.w r2, [r3, #520] @ 0x208 } } 800c504: bf00 nop 800c506: bd80 pop {r7, pc} 800c508: 20000fe0 .word 0x20000fe0 800c50c: 20000a34 .word 0x20000a34 800c510: 20000b34 .word 0x20000b34 800c514: 20000f50 .word 0x20000f50 800c518: 20000d44 .word 0x20000d44 800c51c: 40011400 .word 0x40011400 800c520: 20000c34 .word 0x20000c34 0800c524 : void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800c524: b580 push {r7, lr} 800c526: b082 sub sp, #8 800c528: af00 add r7, sp, #0 800c52a: 6078 str r0, [r7, #4] 800c52c: 460b mov r3, r1 800c52e: 807b strh r3, [r7, #2] if (huart->Instance == huart2.Instance) { 800c530: 687b ldr r3, [r7, #4] 800c532: 681a ldr r2, [r3, #0] 800c534: 4b22 ldr r3, [pc, #136] @ (800c5c0 ) 800c536: 681b ldr r3, [r3, #0] 800c538: 429a cmp r2, r3 800c53a: d116 bne.n 800c56a if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800c53c: 887b ldrh r3, [r7, #2] 800c53e: 461a mov r2, r3 800c540: 4920 ldr r1, [pc, #128] @ (800c5c4 ) 800c542: 4821 ldr r0, [pc, #132] @ (800c5c8 ) 800c544: f000 f98e bl 800c864 800c548: 4603 mov r3, r0 800c54a: 2b00 cmp r3, #0 800c54c: d104 bne.n 800c558 SC_SendPacket(NULL, 0, RESP_INVALID); 800c54e: 2214 movs r2, #20 800c550: 2100 movs r1, #0 800c552: 2000 movs r0, #0 800c554: f000 f8fa bl 800c74c } g_sc_command_source = SC_SOURCE_UART2; 800c558: 4b1c ldr r3, [pc, #112] @ (800c5cc ) 800c55a: 2200 movs r2, #0 800c55c: 701a strb r2, [r3, #0] HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c55e: 22ff movs r2, #255 @ 0xff 800c560: 4918 ldr r1, [pc, #96] @ (800c5c4 ) 800c562: 4817 ldr r0, [pc, #92] @ (800c5c0 ) 800c564: f005 fc7c bl 8011e60 } HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1); } else if (huart->Instance == huart3.Instance) { CCS_RxEventCallback(huart, Size); } } 800c568: e025 b.n 800c5b6 } else if (huart->Instance == huart5.Instance) { 800c56a: 687b ldr r3, [r7, #4] 800c56c: 681a ldr r2, [r3, #0] 800c56e: 4b18 ldr r3, [pc, #96] @ (800c5d0 ) 800c570: 681b ldr r3, [r3, #0] 800c572: 429a cmp r2, r3 800c574: d114 bne.n 800c5a0 if (process_received_packet(&serial_iso, serial_iso.rx_buffer, Size)) { 800c576: 887b ldrh r3, [r7, #2] 800c578: 461a mov r2, r3 800c57a: 4916 ldr r1, [pc, #88] @ (800c5d4 ) 800c57c: 4816 ldr r0, [pc, #88] @ (800c5d8 ) 800c57e: f000 f971 bl 800c864 800c582: 4603 mov r3, r0 800c584: 2b00 cmp r3, #0 800c586: d005 beq.n 800c594 g_sc_command_source = SC_SOURCE_UART5; 800c588: 4b10 ldr r3, [pc, #64] @ (800c5cc ) 800c58a: 2201 movs r2, #1 800c58c: 701a strb r2, [r3, #0] SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); 800c58e: 4813 ldr r0, [pc, #76] @ (800c5dc ) 800c590: f000 f99c bl 800c8cc HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c594: 22ff movs r2, #255 @ 0xff 800c596: 490f ldr r1, [pc, #60] @ (800c5d4 ) 800c598: 480d ldr r0, [pc, #52] @ (800c5d0 ) 800c59a: f005 fc61 bl 8011e60 } 800c59e: e00a b.n 800c5b6 } else if (huart->Instance == huart3.Instance) { 800c5a0: 687b ldr r3, [r7, #4] 800c5a2: 681a ldr r2, [r3, #0] 800c5a4: 4b0e ldr r3, [pc, #56] @ (800c5e0 ) 800c5a6: 681b ldr r3, [r3, #0] 800c5a8: 429a cmp r2, r3 800c5aa: d104 bne.n 800c5b6 CCS_RxEventCallback(huart, Size); 800c5ac: 887b ldrh r3, [r7, #2] 800c5ae: 4619 mov r1, r3 800c5b0: 6878 ldr r0, [r7, #4] 800c5b2: f7ff f9f7 bl 800b9a4 } 800c5b6: bf00 nop 800c5b8: 3708 adds r7, #8 800c5ba: 46bd mov sp, r7 800c5bc: bd80 pop {r7, pc} 800c5be: bf00 nop 800c5c0: 20000fe0 .word 0x20000fe0 800c5c4: 20000b34 .word 0x20000b34 800c5c8: 20000a34 .word 0x20000a34 800c5cc: 20000e54 .word 0x20000e54 800c5d0: 20000f50 .word 0x20000f50 800c5d4: 20000d44 .word 0x20000d44 800c5d8: 20000c44 .word 0x20000c44 800c5dc: 20000e44 .word 0x20000e44 800c5e0: 20001028 .word 0x20001028 0800c5e4 : void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 800c5e4: b580 push {r7, lr} 800c5e6: b082 sub sp, #8 800c5e8: af00 add r7, sp, #0 800c5ea: 6078 str r0, [r7, #4] if (huart->Instance == huart2.Instance) { 800c5ec: 687b ldr r3, [r7, #4] 800c5ee: 681a ldr r2, [r3, #0] 800c5f0: 4b08 ldr r3, [pc, #32] @ (800c614 ) 800c5f2: 681b ldr r3, [r3, #0] 800c5f4: 429a cmp r2, r3 800c5f6: d108 bne.n 800c60a HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800c5f8: 2200 movs r2, #0 800c5fa: 2110 movs r1, #16 800c5fc: 4806 ldr r0, [pc, #24] @ (800c618 ) 800c5fe: f003 f97a bl 800f8f6 serial_control.tx_tick = 0; 800c602: 4b06 ldr r3, [pc, #24] @ (800c61c ) 800c604: 2200 movs r2, #0 800c606: f8c3 220c str.w r2, [r3, #524] @ 0x20c } } 800c60a: bf00 nop 800c60c: 3708 adds r7, #8 800c60e: 46bd mov sp, r7 800c610: bd80 pop {r7, pc} 800c612: bf00 nop 800c614: 20000fe0 .word 0x20000fe0 800c618: 40011400 .word 0x40011400 800c61c: 20000a34 .word 0x20000a34 0800c620 : // Приватные функции реализации // Полностью программная реализация CRC-32 (полином CRC32_POLYNOMIAL, порядок little-endian) static uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { 800c620: b480 push {r7} 800c622: b085 sub sp, #20 800c624: af00 add r7, sp, #0 800c626: 6078 str r0, [r7, #4] 800c628: 460b mov r3, r1 800c62a: 807b strh r3, [r7, #2] uint32_t crc = 0xFFFFFFFFu; 800c62c: f04f 33ff mov.w r3, #4294967295 800c630: 60fb str r3, [r7, #12] for (uint16_t i = 0; i < length; i++) { 800c632: 2300 movs r3, #0 800c634: 817b strh r3, [r7, #10] 800c636: e021 b.n 800c67c crc ^= data[i]; 800c638: 897b ldrh r3, [r7, #10] 800c63a: 687a ldr r2, [r7, #4] 800c63c: 4413 add r3, r2 800c63e: 781b ldrb r3, [r3, #0] 800c640: 461a mov r2, r3 800c642: 68fb ldr r3, [r7, #12] 800c644: 4053 eors r3, r2 800c646: 60fb str r3, [r7, #12] for (uint8_t bit = 0; bit < 8; bit++) { 800c648: 2300 movs r3, #0 800c64a: 727b strb r3, [r7, #9] 800c64c: e010 b.n 800c670 if (crc & 0x1u) { 800c64e: 68fb ldr r3, [r7, #12] 800c650: f003 0301 and.w r3, r3, #1 800c654: 2b00 cmp r3, #0 800c656: d005 beq.n 800c664 crc = (crc >> 1) ^ CRC32_POLYNOMIAL; 800c658: 68fb ldr r3, [r7, #12] 800c65a: 085a lsrs r2, r3, #1 800c65c: 4b0d ldr r3, [pc, #52] @ (800c694 ) 800c65e: 4053 eors r3, r2 800c660: 60fb str r3, [r7, #12] 800c662: e002 b.n 800c66a } else { crc >>= 1; 800c664: 68fb ldr r3, [r7, #12] 800c666: 085b lsrs r3, r3, #1 800c668: 60fb str r3, [r7, #12] for (uint8_t bit = 0; bit < 8; bit++) { 800c66a: 7a7b ldrb r3, [r7, #9] 800c66c: 3301 adds r3, #1 800c66e: 727b strb r3, [r7, #9] 800c670: 7a7b ldrb r3, [r7, #9] 800c672: 2b07 cmp r3, #7 800c674: d9eb bls.n 800c64e for (uint16_t i = 0; i < length; i++) { 800c676: 897b ldrh r3, [r7, #10] 800c678: 3301 adds r3, #1 800c67a: 817b strh r3, [r7, #10] 800c67c: 897a ldrh r2, [r7, #10] 800c67e: 887b ldrh r3, [r7, #2] 800c680: 429a cmp r2, r3 800c682: d3d9 bcc.n 800c638 } } } return crc ^ 0xFFFFFFFFu; 800c684: 68fb ldr r3, [r7, #12] 800c686: 43db mvns r3, r3 } 800c688: 4618 mov r0, r3 800c68a: 3714 adds r7, #20 800c68c: 46bd mov sp, r7 800c68e: bc80 pop {r7} 800c690: 4770 bx lr 800c692: bf00 nop 800c694: edb88320 .word 0xedb88320 0800c698 : static uint16_t encode_packet(const uint8_t* payload, uint16_t payload_len, uint8_t* output, uint8_t response_code) { 800c698: b580 push {r7, lr} 800c69a: b088 sub sp, #32 800c69c: af00 add r7, sp, #0 800c69e: 60f8 str r0, [r7, #12] 800c6a0: 607a str r2, [r7, #4] 800c6a2: 461a mov r2, r3 800c6a4: 460b mov r3, r1 800c6a6: 817b strh r3, [r7, #10] 800c6a8: 4613 mov r3, r2 800c6aa: 727b strb r3, [r7, #9] uint16_t out_index = 0; 800c6ac: 2300 movs r3, #0 800c6ae: 83fb strh r3, [r7, #30] output[out_index++] = response_code; 800c6b0: 8bfb ldrh r3, [r7, #30] 800c6b2: 1c5a adds r2, r3, #1 800c6b4: 83fa strh r2, [r7, #30] 800c6b6: 461a mov r2, r3 800c6b8: 687b ldr r3, [r7, #4] 800c6ba: 4413 add r3, r2 800c6bc: 7a7a ldrb r2, [r7, #9] 800c6be: 701a strb r2, [r3, #0] if (payload != NULL) { 800c6c0: 68fb ldr r3, [r7, #12] 800c6c2: 2b00 cmp r3, #0 800c6c4: d019 beq.n 800c6fa // Просто копируем полезную нагрузку без какого‑либо экранирования for (uint16_t i = 0; i < payload_len; i++) { 800c6c6: 2300 movs r3, #0 800c6c8: 83bb strh r3, [r7, #28] 800c6ca: e012 b.n 800c6f2 output[out_index++] = payload[i]; 800c6cc: 8bbb ldrh r3, [r7, #28] 800c6ce: 68fa ldr r2, [r7, #12] 800c6d0: 441a add r2, r3 800c6d2: 8bfb ldrh r3, [r7, #30] 800c6d4: 1c59 adds r1, r3, #1 800c6d6: 83f9 strh r1, [r7, #30] 800c6d8: 4619 mov r1, r3 800c6da: 687b ldr r3, [r7, #4] 800c6dc: 440b add r3, r1 800c6de: 7812 ldrb r2, [r2, #0] 800c6e0: 701a strb r2, [r3, #0] // Проверка переполнения if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800c6e2: 8bfb ldrh r3, [r7, #30] 800c6e4: 2bfa cmp r3, #250 @ 0xfa 800c6e6: d901 bls.n 800c6ec return 0; 800c6e8: 2300 movs r3, #0 800c6ea: e02a b.n 800c742 for (uint16_t i = 0; i < payload_len; i++) { 800c6ec: 8bbb ldrh r3, [r7, #28] 800c6ee: 3301 adds r3, #1 800c6f0: 83bb strh r3, [r7, #28] 800c6f2: 8bba ldrh r2, [r7, #28] 800c6f4: 897b ldrh r3, [r7, #10] 800c6f6: 429a cmp r2, r3 800c6f8: d3e8 bcc.n 800c6cc } } } // Вычисляем CRC для всего содержимого (код ответа + полезная нагрузка) uint32_t crc = calculate_crc32(output, out_index); 800c6fa: 8bfb ldrh r3, [r7, #30] 800c6fc: 4619 mov r1, r3 800c6fe: 6878 ldr r0, [r7, #4] 800c700: f7ff ff8e bl 800c620 800c704: 4603 mov r3, r0 800c706: 613b str r3, [r7, #16] uint8_t* crc_bytes = (uint8_t*)&crc; 800c708: f107 0310 add.w r3, r7, #16 800c70c: 617b str r3, [r7, #20] // Добавляем CRC без экранирования for (int i = 0; i < 4; i++) { 800c70e: 2300 movs r3, #0 800c710: 61bb str r3, [r7, #24] 800c712: e012 b.n 800c73a output[out_index++] = crc_bytes[i]; 800c714: 69bb ldr r3, [r7, #24] 800c716: 697a ldr r2, [r7, #20] 800c718: 441a add r2, r3 800c71a: 8bfb ldrh r3, [r7, #30] 800c71c: 1c59 adds r1, r3, #1 800c71e: 83f9 strh r1, [r7, #30] 800c720: 4619 mov r1, r3 800c722: 687b ldr r3, [r7, #4] 800c724: 440b add r3, r1 800c726: 7812 ldrb r2, [r2, #0] 800c728: 701a strb r2, [r3, #0] if (out_index >= MAX_TX_BUFFER_SIZE - 1) { // место для END_BYTE 800c72a: 8bfb ldrh r3, [r7, #30] 800c72c: 2bfe cmp r3, #254 @ 0xfe 800c72e: d901 bls.n 800c734 return 0; 800c730: 2300 movs r3, #0 800c732: e006 b.n 800c742 for (int i = 0; i < 4; i++) { 800c734: 69bb ldr r3, [r7, #24] 800c736: 3301 adds r3, #1 800c738: 61bb str r3, [r7, #24] 800c73a: 69bb ldr r3, [r7, #24] 800c73c: 2b03 cmp r3, #3 800c73e: dde9 ble.n 800c714 } } return out_index; 800c740: 8bfb ldrh r3, [r7, #30] } 800c742: 4618 mov r0, r3 800c744: 3720 adds r7, #32 800c746: 46bd mov sp, r7 800c748: bd80 pop {r7, pc} ... 0800c74c : void SC_SendPacket(const uint8_t* payload, uint16_t payload_len, uint8_t response_code) { 800c74c: b580 push {r7, lr} 800c74e: b084 sub sp, #16 800c750: af00 add r7, sp, #0 800c752: 6078 str r0, [r7, #4] 800c754: 460b mov r3, r1 800c756: 807b strh r3, [r7, #2] 800c758: 4613 mov r3, r2 800c75a: 707b strb r3, [r7, #1] uint16_t packet_len = encode_packet(payload, payload_len, serial_control.tx_buffer, response_code); 800c75c: 787b ldrb r3, [r7, #1] 800c75e: 8879 ldrh r1, [r7, #2] 800c760: 4a15 ldr r2, [pc, #84] @ (800c7b8 ) 800c762: 6878 ldr r0, [r7, #4] 800c764: f7ff ff98 bl 800c698 800c768: 4603 mov r3, r0 800c76a: 81fb strh r3, [r7, #14] if (packet_len > 0) { 800c76c: 89fb ldrh r3, [r7, #14] 800c76e: 2b00 cmp r3, #0 800c770: d01e beq.n 800c7b0 if (huart2.gState == HAL_UART_STATE_BUSY_TX) { 800c772: 4b12 ldr r3, [pc, #72] @ (800c7bc ) 800c774: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800c778: b2db uxtb r3, r3 800c77a: 2b21 cmp r3, #33 @ 0x21 800c77c: d107 bne.n 800c78e HAL_UART_Abort_IT(&huart2); 800c77e: 480f ldr r0, [pc, #60] @ (800c7bc ) 800c780: f005 fbcc bl 8011f1c HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800c784: 2200 movs r2, #0 800c786: 2110 movs r1, #16 800c788: 480d ldr r0, [pc, #52] @ (800c7c0 ) 800c78a: f003 f8b4 bl 800f8f6 } HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_SET); 800c78e: 2201 movs r2, #1 800c790: 2110 movs r1, #16 800c792: 480b ldr r0, [pc, #44] @ (800c7c0 ) 800c794: f003 f8af bl 800f8f6 HAL_UART_Transmit_IT(&huart2, serial_control.tx_buffer, packet_len); 800c798: 89fb ldrh r3, [r7, #14] 800c79a: 461a mov r2, r3 800c79c: 4906 ldr r1, [pc, #24] @ (800c7b8 ) 800c79e: 4807 ldr r0, [pc, #28] @ (800c7bc ) 800c7a0: f005 fb29 bl 8011df6 serial_control.tx_tick = HAL_GetTick(); 800c7a4: f001 f896 bl 800d8d4 800c7a8: 4603 mov r3, r0 800c7aa: 4a03 ldr r2, [pc, #12] @ (800c7b8 ) 800c7ac: f8c2 320c str.w r3, [r2, #524] @ 0x20c } } 800c7b0: bf00 nop 800c7b2: 3710 adds r7, #16 800c7b4: 46bd mov sp, r7 800c7b6: bd80 pop {r7, pc} 800c7b8: 20000a34 .word 0x20000a34 800c7bc: 20000fe0 .word 0x20000fe0 800c7c0: 40011400 .word 0x40011400 0800c7c4 : static uint8_t parse_packet(const uint8_t* packet_data, uint16_t packet_len, ReceivedCommand_t* out_cmd) { 800c7c4: b580 push {r7, lr} 800c7c6: b088 sub sp, #32 800c7c8: af00 add r7, sp, #0 800c7ca: 60f8 str r0, [r7, #12] 800c7cc: 460b mov r3, r1 800c7ce: 607a str r2, [r7, #4] 800c7d0: 817b strh r3, [r7, #10] // }else{ // test_crc_invalid = 5; // } // Минимальный размер: 1 байт команды + 4 байта CRC if (packet_len < 5) return 0; 800c7d2: 897b ldrh r3, [r7, #10] 800c7d4: 2b04 cmp r3, #4 800c7d6: d801 bhi.n 800c7dc 800c7d8: 2300 movs r3, #0 800c7da: e03f b.n 800c85c if (packet_len > MAX_RX_BUFFER_SIZE) return 0; 800c7dc: 897b ldrh r3, [r7, #10] 800c7de: f5b3 7f80 cmp.w r3, #256 @ 0x100 800c7e2: d901 bls.n 800c7e8 800c7e4: 2300 movs r3, #0 800c7e6: e039 b.n 800c85c uint16_t payload_length = packet_len - 4; 800c7e8: 897b ldrh r3, [r7, #10] 800c7ea: 3b04 subs r3, #4 800c7ec: 83fb strh r3, [r7, #30] // Извлекаем принятую CRC (последние 4 байта, little-endian) uint32_t received_checksum = ((uint32_t)packet_data[payload_length] << 0) | 800c7ee: 8bfb ldrh r3, [r7, #30] 800c7f0: 68fa ldr r2, [r7, #12] 800c7f2: 4413 add r3, r2 800c7f4: 781b ldrb r3, [r3, #0] 800c7f6: 4619 mov r1, r3 ((uint32_t)packet_data[payload_length + 1] << 8) | 800c7f8: 8bfb ldrh r3, [r7, #30] 800c7fa: 3301 adds r3, #1 800c7fc: 68fa ldr r2, [r7, #12] 800c7fe: 4413 add r3, r2 800c800: 781b ldrb r3, [r3, #0] 800c802: 021b lsls r3, r3, #8 ((uint32_t)packet_data[payload_length] << 0) | 800c804: ea41 0203 orr.w r2, r1, r3 ((uint32_t)packet_data[payload_length + 2] << 16) | 800c808: 8bfb ldrh r3, [r7, #30] 800c80a: 3302 adds r3, #2 800c80c: 68f9 ldr r1, [r7, #12] 800c80e: 440b add r3, r1 800c810: 781b ldrb r3, [r3, #0] 800c812: 041b lsls r3, r3, #16 ((uint32_t)packet_data[payload_length + 1] << 8) | 800c814: 431a orrs r2, r3 ((uint32_t)packet_data[payload_length + 3] << 24); 800c816: 8bfb ldrh r3, [r7, #30] 800c818: 3303 adds r3, #3 800c81a: 68f9 ldr r1, [r7, #12] 800c81c: 440b add r3, r1 800c81e: 781b ldrb r3, [r3, #0] 800c820: 061b lsls r3, r3, #24 uint32_t received_checksum = 800c822: 4313 orrs r3, r2 800c824: 61bb str r3, [r7, #24] // Вычисляем CRC для полезной нагрузки uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); 800c826: 8bfb ldrh r3, [r7, #30] 800c828: 4619 mov r1, r3 800c82a: 68f8 ldr r0, [r7, #12] 800c82c: f7ff fef8 bl 800c620 800c830: 6178 str r0, [r7, #20] if (received_checksum != calculated_checksum) return 0; // CRC не совпадает 800c832: 69ba ldr r2, [r7, #24] 800c834: 697b ldr r3, [r7, #20] 800c836: 429a cmp r2, r3 800c838: d001 beq.n 800c83e 800c83a: 2300 movs r3, #0 800c83c: e00e b.n 800c85c out_cmd->argument = (void *)&packet_data[1]; 800c83e: 68fb ldr r3, [r7, #12] 800c840: 1c5a adds r2, r3, #1 800c842: 687b ldr r3, [r7, #4] 800c844: 605a str r2, [r3, #4] out_cmd->command = packet_data[0]; 800c846: 68fb ldr r3, [r7, #12] 800c848: 781a ldrb r2, [r3, #0] 800c84a: 687b ldr r3, [r7, #4] 800c84c: 701a strb r2, [r3, #0] out_cmd->argument_length = (uint8_t)(payload_length - 1); 800c84e: 8bfb ldrh r3, [r7, #30] 800c850: b2db uxtb r3, r3 800c852: 3b01 subs r3, #1 800c854: b2da uxtb r2, r3 800c856: 687b ldr r3, [r7, #4] 800c858: 705a strb r2, [r3, #1] return 1; 800c85a: 2301 movs r3, #1 } 800c85c: 4618 mov r0, r3 800c85e: 3720 adds r7, #32 800c860: 46bd mov sp, r7 800c862: bd80 pop {r7, pc} 0800c864 : static uint8_t process_received_packet(SerialControl_t *ctx, const uint8_t* packet_data, uint16_t packet_len) { 800c864: b580 push {r7, lr} 800c866: b084 sub sp, #16 800c868: af00 add r7, sp, #0 800c86a: 60f8 str r0, [r7, #12] 800c86c: 60b9 str r1, [r7, #8] 800c86e: 4613 mov r3, r2 800c870: 80fb strh r3, [r7, #6] if (!parse_packet(packet_data, packet_len, (ReceivedCommand_t *)&ctx->received_command)) { 800c872: 68fb ldr r3, [r7, #12] 800c874: f503 7200 add.w r2, r3, #512 @ 0x200 800c878: 88fb ldrh r3, [r7, #6] 800c87a: 4619 mov r1, r3 800c87c: 68b8 ldr r0, [r7, #8] 800c87e: f7ff ffa1 bl 800c7c4 800c882: 4603 mov r3, r0 800c884: 2b00 cmp r3, #0 800c886: d101 bne.n 800c88c return 0; 800c888: 2300 movs r3, #0 800c88a: e004 b.n 800c896 } ctx->command_ready = 1; 800c88c: 68fb ldr r3, [r7, #12] 800c88e: 2201 movs r2, #1 800c890: f883 2208 strb.w r2, [r3, #520] @ 0x208 return 1; 800c894: 2301 movs r3, #1 } 800c896: 4618 mov r0, r3 800c898: 3710 adds r7, #16 800c89a: 46bd mov sp, r7 800c89c: bd80 pop {r7, pc} ... 0800c8a0 <__NVIC_SystemReset>: { 800c8a0: b480 push {r7} 800c8a2: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 800c8a4: f3bf 8f4f dsb sy } 800c8a8: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800c8aa: 4b06 ldr r3, [pc, #24] @ (800c8c4 <__NVIC_SystemReset+0x24>) 800c8ac: 68db ldr r3, [r3, #12] 800c8ae: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800c8b2: 4904 ldr r1, [pc, #16] @ (800c8c4 <__NVIC_SystemReset+0x24>) 800c8b4: 4b04 ldr r3, [pc, #16] @ (800c8c8 <__NVIC_SystemReset+0x28>) 800c8b6: 4313 orrs r3, r2 800c8b8: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800c8ba: f3bf 8f4f dsb sy } 800c8be: bf00 nop __NOP(); 800c8c0: bf00 nop 800c8c2: e7fd b.n 800c8c0 <__NVIC_SystemReset+0x20> 800c8c4: e000ed00 .word 0xe000ed00 800c8c8: 05fa0004 .word 0x05fa0004 0800c8cc : .chargerNumber = 00001, .unixTime = 1721651966, }; // Единая функция-обработчик всех команд со switch-case void SC_CommandHandler(ReceivedCommand_t* cmd) { 800c8cc: b580 push {r7, lr} 800c8ce: b084 sub sp, #16 800c8d0: af00 add r7, sp, #0 800c8d2: 6078 str r0, [r7, #4] uint8_t response_code = RESP_FAILED; 800c8d4: 2313 movs r3, #19 800c8d6: 73fb strb r3, [r7, #15] switch (cmd->command) { 800c8d8: 687b ldr r3, [r7, #4] 800c8da: 781b ldrb r3, [r3, #0] 800c8dc: 2bc2 cmp r3, #194 @ 0xc2 800c8de: f300 80cc bgt.w 800ca7a 800c8e2: 2bb0 cmp r3, #176 @ 0xb0 800c8e4: da0f bge.n 800c906 800c8e6: 2b60 cmp r3, #96 @ 0x60 800c8e8: d042 beq.n 800c970 800c8ea: 2b60 cmp r3, #96 @ 0x60 800c8ec: f300 80c5 bgt.w 800ca7a 800c8f0: 2b50 cmp r3, #80 @ 0x50 800c8f2: d043 beq.n 800c97c 800c8f4: 2b50 cmp r3, #80 @ 0x50 800c8f6: f300 80c0 bgt.w 800ca7a 800c8fa: 2b01 cmp r3, #1 800c8fc: f000 80a6 beq.w 800ca4c 800c900: 2b40 cmp r3, #64 @ 0x40 800c902: d02d beq.n 800c960 800c904: e0b9 b.n 800ca7a 800c906: 3bb0 subs r3, #176 @ 0xb0 800c908: 2b12 cmp r3, #18 800c90a: f200 80b6 bhi.w 800ca7a 800c90e: a201 add r2, pc, #4 @ (adr r2, 800c914 ) 800c910: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c914: 0800c983 .word 0x0800c983 800c918: 0800ca7b .word 0x0800ca7b 800c91c: 0800ca7b .word 0x0800ca7b 800c920: 0800ca7b .word 0x0800ca7b 800c924: 0800ca7b .word 0x0800ca7b 800c928: 0800ca2b .word 0x0800ca2b 800c92c: 0800ca7b .word 0x0800ca7b 800c930: 0800ca7b .word 0x0800ca7b 800c934: 0800ca7b .word 0x0800ca7b 800c938: 0800ca7b .word 0x0800ca7b 800c93c: 0800ca7b .word 0x0800ca7b 800c940: 0800ca7b .word 0x0800ca7b 800c944: 0800ca7b .word 0x0800ca7b 800c948: 0800ca7b .word 0x0800ca7b 800c94c: 0800ca7b .word 0x0800ca7b 800c950: 0800ca7b .word 0x0800ca7b 800c954: 0800c9c1 .word 0x0800c9c1 800c958: 0800ca25 .word 0x0800ca25 800c95c: 0800c9f9 .word 0x0800c9f9 // Команды БЕЗ аргументов case CMD_GET_STATUS: // Логика получения информации monitoring_data_callback(); 800c960: f000 f8b2 bl 800cac8 // Отправляем с нормальным приоритетом SC_SendPacket((uint8_t*)&statusPacket, sizeof(statusPacket), CMD_GET_STATUS); 800c964: 2240 movs r2, #64 @ 0x40 800c966: 2158 movs r1, #88 @ 0x58 800c968: 484b ldr r0, [pc, #300] @ (800ca98 ) 800c96a: f7ff feef bl 800c74c return; // Специальный ответ уже отправлен 800c96e: e08f b.n 800ca90 case CMD_GET_INFO: SC_SendPacket((uint8_t*)&infoPacket, sizeof(infoPacket), CMD_GET_INFO); 800c970: 2260 movs r2, #96 @ 0x60 800c972: 210a movs r1, #10 800c974: 4849 ldr r0, [pc, #292] @ (800ca9c ) 800c976: f7ff fee9 bl 800c74c return; 800c97a: e089 b.n 800ca90 case CMD_GET_LOG: debug_buffer_send(); 800c97c: f7fd fd16 bl 800a3ac return; // Ответ формируется внутри debug_buffer_send 800c980: e086 b.n 800ca90 // Команды С аргументами case CMD_SET_CONFIG: if (cmd->argument_length == sizeof(ConfigBlock_t)) { 800c982: 687b ldr r3, [r7, #4] 800c984: 785b ldrb r3, [r3, #1] 800c986: 2b0b cmp r3, #11 800c988: d117 bne.n 800c9ba memcpy(&config, cmd->argument, sizeof(ConfigBlock_t)); 800c98a: 687b ldr r3, [r7, #4] 800c98c: 685a ldr r2, [r3, #4] 800c98e: 4b44 ldr r3, [pc, #272] @ (800caa0 ) 800c990: 6810 ldr r0, [r2, #0] 800c992: 6851 ldr r1, [r2, #4] 800c994: c303 stmia r3!, {r0, r1} 800c996: 8911 ldrh r1, [r2, #8] 800c998: 7a92 ldrb r2, [r2, #10] 800c99a: 8019 strh r1, [r3, #0] 800c99c: 709a strb r2, [r3, #2] config_initialized = 1; 800c99e: 4b41 ldr r3, [pc, #260] @ (800caa4 ) 800c9a0: 2201 movs r2, #1 800c9a2: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Set Config: %s %d\n", config.location, config.chargerNumber); 800c9a4: 4b3e ldr r3, [pc, #248] @ (800caa0 ) 800c9a6: f8d3 3003 ldr.w r3, [r3, #3] 800c9aa: 4a3d ldr r2, [pc, #244] @ (800caa0 ) 800c9ac: 493e ldr r1, [pc, #248] @ (800caa8 ) 800c9ae: 2007 movs r0, #7 800c9b0: f7fd fd5e bl 800a470 response_code = RESP_SUCCESS; 800c9b4: 2312 movs r3, #18 800c9b6: 73fb strb r3, [r7, #15] break; 800c9b8: e062 b.n 800ca80 } response_code = RESP_FAILED; 800c9ba: 2313 movs r3, #19 800c9bc: 73fb strb r3, [r7, #15] break; 800c9be: e05f b.n 800ca80 case CMD_SET_POWER_LIMIT: if (cmd->argument_length == 1) { 800c9c0: 687b ldr r3, [r7, #4] 800c9c2: 785b ldrb r3, [r3, #1] 800c9c4: 2b01 cmp r3, #1 800c9c6: d114 bne.n 800c9f2 PSU0.power_limit = ((uint8_t*)cmd->argument)[0] * 1000; 800c9c8: 687b ldr r3, [r7, #4] 800c9ca: 685b ldr r3, [r3, #4] 800c9cc: 781b ldrb r3, [r3, #0] 800c9ce: 461a mov r2, r3 800c9d0: f44f 737a mov.w r3, #1000 @ 0x3e8 800c9d4: fb02 f303 mul.w r3, r2, r3 800c9d8: 461a mov r2, r3 800c9da: 4b34 ldr r3, [pc, #208] @ (800caac ) 800c9dc: 615a str r2, [r3, #20] log_printf(LOG_INFO, "Power limit: %d\n", PSU0.power_limit); 800c9de: 4b33 ldr r3, [pc, #204] @ (800caac ) 800c9e0: 695b ldr r3, [r3, #20] 800c9e2: 461a mov r2, r3 800c9e4: 4932 ldr r1, [pc, #200] @ (800cab0 ) 800c9e6: 2007 movs r0, #7 800c9e8: f7fd fd42 bl 800a470 //CONN.connState = (((uint8_t*)cmd->argument)[0])/4; response_code = RESP_SUCCESS; 800c9ec: 2312 movs r3, #18 800c9ee: 73fb strb r3, [r7, #15] break; 800c9f0: e046 b.n 800ca80 } response_code = RESP_FAILED; 800c9f2: 2313 movs r3, #19 800c9f4: 73fb strb r3, [r7, #15] break; 800c9f6: e043 b.n 800ca80 case CMD_CHARGE_PERMIT: if (cmd->argument_length == 1) { 800c9f8: 687b ldr r3, [r7, #4] 800c9fa: 785b ldrb r3, [r3, #1] 800c9fc: 2b01 cmp r3, #1 800c9fe: d10e bne.n 800ca1e CONN.connControl = ((uint8_t*)cmd->argument)[0]; 800ca00: 687b ldr r3, [r7, #4] 800ca02: 685b ldr r3, [r3, #4] 800ca04: 781a ldrb r2, [r3, #0] 800ca06: 4b2b ldr r3, [pc, #172] @ (800cab4 ) 800ca08: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Charge permit: %d\n", CONN.connControl); 800ca0a: 4b2a ldr r3, [pc, #168] @ (800cab4 ) 800ca0c: 781b ldrb r3, [r3, #0] 800ca0e: 461a mov r2, r3 800ca10: 4929 ldr r1, [pc, #164] @ (800cab8 ) 800ca12: 2007 movs r0, #7 800ca14: f7fd fd2c bl 800a470 response_code = RESP_SUCCESS; 800ca18: 2312 movs r3, #18 800ca1a: 73fb strb r3, [r7, #15] break; 800ca1c: e030 b.n 800ca80 } response_code = RESP_FAILED; 800ca1e: 2313 movs r3, #19 800ca20: 73fb strb r3, [r7, #15] break; 800ca22: e02d b.n 800ca80 // memcpy(&PSU_TestMode, cmd->argument, sizeof(PSU_TestMode_t)); // log_printf(LOG_INFO, "Test PSU: %d %d %d\n", PSU_TestMode.enable, PSU_TestMode.voltage, PSU_TestMode.current); // response_code = RESP_SUCCESS; // break; // } response_code = RESP_FAILED; 800ca24: 2313 movs r3, #19 800ca26: 73fb strb r3, [r7, #15] break; 800ca28: e02a b.n 800ca80 case CMD_DEVICE_RESET: // 2. Отправляем SUCCESS (хост может успеть получить его перед ребутом) SC_SendPacket(NULL, 0, RESP_SUCCESS); 800ca2a: 2212 movs r2, #18 800ca2c: 2100 movs r1, #0 800ca2e: 2000 movs r0, #0 800ca30: f7ff fe8c bl 800c74c while(huart2.gState == HAL_UART_STATE_BUSY_TX); // Ожидание завершения передачи 800ca34: bf00 nop 800ca36: 4b21 ldr r3, [pc, #132] @ (800cabc ) 800ca38: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800ca3c: b2db uxtb r3, r3 800ca3e: 2b21 cmp r3, #33 @ 0x21 800ca40: d0f9 beq.n 800ca36 HAL_Delay(10); 800ca42: 200a movs r0, #10 800ca44: f000 ff50 bl 800d8e8 // 3. Выполняем программный сброс NVIC_SystemReset(); 800ca48: f7ff ff2a bl 800c8a0 <__NVIC_SystemReset> return; // Сюда код уже не дойдет, но для компилятора нxужно case CMD_ISOLATION_STATUS: if (cmd->argument_length == sizeof(IsolationStatusPacket_t)) { 800ca4c: 687b ldr r3, [r7, #4] 800ca4e: 785b ldrb r3, [r3, #1] 800ca50: 2b09 cmp r3, #9 800ca52: d10f bne.n 800ca74 memcpy(&ISO, cmd->argument, sizeof(IsolationStatusPacket_t)); 800ca54: 687b ldr r3, [r7, #4] 800ca56: 685a ldr r2, [r3, #4] 800ca58: 4b19 ldr r3, [pc, #100] @ (800cac0 ) 800ca5a: 6810 ldr r0, [r2, #0] 800ca5c: 6851 ldr r1, [r2, #4] 800ca5e: c303 stmia r3!, {r0, r1} 800ca60: 7a12 ldrb r2, [r2, #8] 800ca62: 701a strb r2, [r3, #0] // Для однонаправленного UART5 ответ не нужен if (g_sc_command_source == SC_SOURCE_UART5) { 800ca64: 4b17 ldr r3, [pc, #92] @ (800cac4 ) 800ca66: 781b ldrb r3, [r3, #0] 800ca68: b2db uxtb r3, r3 800ca6a: 2b01 cmp r3, #1 800ca6c: d00f beq.n 800ca8e return; } response_code = RESP_SUCCESS; 800ca6e: 2312 movs r3, #18 800ca70: 73fb strb r3, [r7, #15] break; 800ca72: e005 b.n 800ca80 } response_code = RESP_FAILED; 800ca74: 2313 movs r3, #19 800ca76: 73fb strb r3, [r7, #15] break; 800ca78: e002 b.n 800ca80 default: // Неизвестная команда response_code = RESP_FAILED; 800ca7a: 2313 movs r3, #19 800ca7c: 73fb strb r3, [r7, #15] break; 800ca7e: bf00 nop } // Отправляем финальный ответ (для команд без собственного ответа) SC_SendPacket(NULL, 0, response_code); 800ca80: 7bfb ldrb r3, [r7, #15] 800ca82: 461a mov r2, r3 800ca84: 2100 movs r1, #0 800ca86: 2000 movs r0, #0 800ca88: f7ff fe60 bl 800c74c 800ca8c: e000 b.n 800ca90 return; 800ca8e: bf00 nop } 800ca90: 3710 adds r7, #16 800ca92: 46bd mov sp, r7 800ca94: bd80 pop {r7, pc} 800ca96: bf00 nop 800ca98: 20000e58 .word 0x20000e58 800ca9c: 20000eb0 .word 0x20000eb0 800caa0: 20000060 .word 0x20000060 800caa4: 20000eba .word 0x20000eba 800caa8: 08014360 .word 0x08014360 800caac: 20000724 .word 0x20000724 800cab0: 08014374 .word 0x08014374 800cab4: 200001d4 .word 0x200001d4 800cab8: 08014388 .word 0x08014388 800cabc: 20000fe0 .word 0x20000fe0 800cac0: 20000054 .word 0x20000054 800cac4: 20000e54 .word 0x20000e54 0800cac8 : // Колбэк для заполнения данных мониторинга void monitoring_data_callback() { 800cac8: b580 push {r7, lr} 800caca: af00 add r7, sp, #0 // Информация о зарядной сессии statusPacket.SOC = CONN.SOC; 800cacc: 4b8f ldr r3, [pc, #572] @ (800cd0c ) 800cace: 789a ldrb r2, [r3, #2] 800cad0: 4b8f ldr r3, [pc, #572] @ (800cd10 ) 800cad2: 709a strb r2, [r3, #2] statusPacket.Energy = CONN.Energy; 800cad4: 4b8d ldr r3, [pc, #564] @ (800cd0c ) 800cad6: f8d3 3007 ldr.w r3, [r3, #7] 800cada: 4a8d ldr r2, [pc, #564] @ (800cd10 ) 800cadc: f8c2 3003 str.w r3, [r2, #3] statusPacket.RequestedVoltage = CONN.RequestedVoltage; 800cae0: 4b8a ldr r3, [pc, #552] @ (800cd0c ) 800cae2: f8b3 300f ldrh.w r3, [r3, #15] 800cae6: b29a uxth r2, r3 800cae8: 4b89 ldr r3, [pc, #548] @ (800cd10 ) 800caea: f8a3 2007 strh.w r2, [r3, #7] statusPacket.RequestedCurrent = CONN.WantedCurrent; 800caee: 4b87 ldr r3, [pc, #540] @ (800cd0c ) 800caf0: f8b3 301b ldrh.w r3, [r3, #27] 800caf4: b29a uxth r2, r3 800caf6: 4b86 ldr r3, [pc, #536] @ (800cd10 ) 800caf8: f8a3 2009 strh.w r2, [r3, #9] statusPacket.MeasuredVoltage = CONN.MeasuredVoltage; 800cafc: 4b83 ldr r3, [pc, #524] @ (800cd0c ) 800cafe: f8b3 3013 ldrh.w r3, [r3, #19] 800cb02: b29a uxth r2, r3 800cb04: 4b82 ldr r3, [pc, #520] @ (800cd10 ) 800cb06: f8a3 200b strh.w r2, [r3, #11] statusPacket.MeasuredCurrent = CONN.MeasuredCurrent; 800cb0a: 4b80 ldr r3, [pc, #512] @ (800cd0c ) 800cb0c: f8b3 3015 ldrh.w r3, [r3, #21] 800cb10: b29a uxth r2, r3 800cb12: 4b7f ldr r3, [pc, #508] @ (800cd10 ) 800cb14: f8a3 200d strh.w r2, [r3, #13] statusPacket.outputEnabled = CONN.outputEnabled; 800cb18: 4b7c ldr r3, [pc, #496] @ (800cd0c ) 800cb1a: 7e1a ldrb r2, [r3, #24] 800cb1c: 4b7c ldr r3, [pc, #496] @ (800cd10 ) 800cb1e: 73da strb r2, [r3, #15] statusPacket.chargingError = CONN.chargingError; 800cb20: 4b7a ldr r3, [pc, #488] @ (800cd0c ) 800cb22: 7f5a ldrb r2, [r3, #29] 800cb24: 4b7a ldr r3, [pc, #488] @ (800cd10 ) 800cb26: 705a strb r2, [r3, #1] statusPacket.connState = CONN.connState; 800cb28: 4b78 ldr r3, [pc, #480] @ (800cd0c ) 800cb2a: 785a ldrb r2, [r3, #1] 800cb2c: 4b78 ldr r3, [pc, #480] @ (800cd10 ) 800cb2e: 701a strb r2, [r3, #0] statusPacket.chargingElapsedTimeMin = 0; 800cb30: 4b77 ldr r3, [pc, #476] @ (800cd10 ) 800cb32: 2200 movs r2, #0 800cb34: 741a strb r2, [r3, #16] 800cb36: 2200 movs r2, #0 800cb38: 745a strb r2, [r3, #17] statusPacket.chargingElapsedTimeSec = 0; 800cb3a: 4b75 ldr r3, [pc, #468] @ (800cd10 ) 800cb3c: 2200 movs r2, #0 800cb3e: 749a strb r2, [r3, #18] statusPacket.estimatedRemainingChargingTime = 0; 800cb40: 4b73 ldr r3, [pc, #460] @ (800cd10 ) 800cb42: 2200 movs r2, #0 800cb44: 74da strb r2, [r3, #19] 800cb46: 2200 movs r2, #0 800cb48: 751a strb r2, [r3, #20] // состояние зарядной станции statusPacket.relayAC = RELAY_Read(RELAY_AC); 800cb4a: 2004 movs r0, #4 800cb4c: f7fc fd20 bl 8009590 800cb50: 4603 mov r3, r0 800cb52: f003 0301 and.w r3, r3, #1 800cb56: b2d9 uxtb r1, r3 800cb58: 4a6d ldr r2, [pc, #436] @ (800cd10 ) 800cb5a: 7d53 ldrb r3, [r2, #21] 800cb5c: f361 0300 bfi r3, r1, #0, #1 800cb60: 7553 strb r3, [r2, #21] statusPacket.relayDC = RELAY_Read(RELAY_DC); 800cb62: 2003 movs r0, #3 800cb64: f7fc fd14 bl 8009590 800cb68: 4603 mov r3, r0 800cb6a: f003 0301 and.w r3, r3, #1 800cb6e: b2d9 uxtb r1, r3 800cb70: 4a67 ldr r2, [pc, #412] @ (800cd10 ) 800cb72: 7d53 ldrb r3, [r2, #21] 800cb74: f361 0341 bfi r3, r1, #1, #1 800cb78: 7553 strb r3, [r2, #21] statusPacket.relayAUX = RELAY_Read(RELAY_AUX0); 800cb7a: 2000 movs r0, #0 800cb7c: f7fc fd08 bl 8009590 800cb80: 4603 mov r3, r0 800cb82: f003 0301 and.w r3, r3, #1 800cb86: b2d9 uxtb r1, r3 800cb88: 4a61 ldr r2, [pc, #388] @ (800cd10 ) 800cb8a: 7d53 ldrb r3, [r2, #21] 800cb8c: f361 0382 bfi r3, r1, #2, #1 800cb90: 7553 strb r3, [r2, #21] statusPacket.lockState = 0; 800cb92: 4a5f ldr r2, [pc, #380] @ (800cd10 ) 800cb94: 7d53 ldrb r3, [r2, #21] 800cb96: f023 0308 bic.w r3, r3, #8 800cb9a: 7553 strb r3, [r2, #21] statusPacket.stopButton = !IN_ReadInput(IN_ESTOP); 800cb9c: 2003 movs r0, #3 800cb9e: f7fc fd07 bl 80095b0 800cba2: 4603 mov r3, r0 800cba4: 2b00 cmp r3, #0 800cba6: bf0c ite eq 800cba8: 2301 moveq r3, #1 800cbaa: 2300 movne r3, #0 800cbac: b2d9 uxtb r1, r3 800cbae: 4a58 ldr r2, [pc, #352] @ (800cd10 ) 800cbb0: 7d53 ldrb r3, [r2, #21] 800cbb2: f361 1304 bfi r3, r1, #4, #1 800cbb6: 7553 strb r3, [r2, #21] statusPacket.logAvailable = (debug_buffer_available()>0)?1:0; 800cbb8: f7fd fbe4 bl 800a384 800cbbc: 4603 mov r3, r0 800cbbe: 2b00 cmp r3, #0 800cbc0: bf14 ite ne 800cbc2: 2301 movne r3, #1 800cbc4: 2300 moveq r3, #0 800cbc6: b2d9 uxtb r1, r3 800cbc8: 4a51 ldr r2, [pc, #324] @ (800cd10 ) 800cbca: 7d53 ldrb r3, [r2, #21] 800cbcc: f361 1345 bfi r3, r1, #5, #1 800cbd0: 7553 strb r3, [r2, #21] statusPacket.evInfoAvailable = 0; 800cbd2: 4a4f ldr r2, [pc, #316] @ (800cd10 ) 800cbd4: 7d53 ldrb r3, [r2, #21] 800cbd6: f023 0340 bic.w r3, r3, #64 @ 0x40 800cbda: 7553 strb r3, [r2, #21] statusPacket.psuOnline = PSU0.online; 800cbdc: 4b4d ldr r3, [pc, #308] @ (800cd14 ) 800cbde: 7a1b ldrb r3, [r3, #8] 800cbe0: f003 0301 and.w r3, r3, #1 800cbe4: b2d9 uxtb r1, r3 800cbe6: 4a4a ldr r2, [pc, #296] @ (800cd10 ) 800cbe8: 7d53 ldrb r3, [r2, #21] 800cbea: f361 13c7 bfi r3, r1, #7, #1 800cbee: 7553 strb r3, [r2, #21] statusPacket.tempConnector0 = CONN_ReadTemp(0); // температура коннектора 800cbf0: 2000 movs r0, #0 800cbf2: f7fc fdcf bl 8009794 800cbf6: 4603 mov r3, r0 800cbf8: b25a sxtb r2, r3 800cbfa: 4b45 ldr r3, [pc, #276] @ (800cd10 ) 800cbfc: 765a strb r2, [r3, #25] statusPacket.tempConnector1 = CONN_ReadTemp(1); 800cbfe: 2001 movs r0, #1 800cc00: f7fc fdc8 bl 8009794 800cc04: 4603 mov r3, r0 800cc06: b25a sxtb r2, r3 800cc08: 4b41 ldr r3, [pc, #260] @ (800cd10 ) 800cc0a: 769a strb r2, [r3, #26] statusPacket.tempAmbient = PSU0.tempAmbient; // температура окружающего воздуха 800cc0c: 4b41 ldr r3, [pc, #260] @ (800cd14 ) 800cc0e: 69db ldr r3, [r3, #28] 800cc10: b25a sxtb r2, r3 800cc12: 4b3f ldr r3, [pc, #252] @ (800cd10 ) 800cc14: 76da strb r2, [r3, #27] statusPacket.tempBatteryMax = 0; 800cc16: 4b3e ldr r3, [pc, #248] @ (800cd10 ) 800cc18: 2200 movs r2, #0 800cc1a: 771a strb r2, [r3, #28] statusPacket.tempBatteryMin = 0; 800cc1c: 4b3c ldr r3, [pc, #240] @ (800cd10 ) 800cc1e: 2200 movs r2, #0 800cc20: 775a strb r2, [r3, #29] statusPacket.highestVoltageOfBatteryCell = 0; 800cc22: 4b3b ldr r3, [pc, #236] @ (800cd10 ) 800cc24: 2200 movs r2, #0 800cc26: 779a strb r2, [r3, #30] 800cc28: 2200 movs r2, #0 800cc2a: 77da strb r2, [r3, #31] statusPacket.batteryStatus = 0; 800cc2c: 4b38 ldr r3, [pc, #224] @ (800cd10 ) 800cc2e: 2200 movs r2, #0 800cc30: f883 2020 strb.w r2, [r3, #32] statusPacket.phaseVoltageAB = PSU_06.VAB; 800cc34: 4b38 ldr r3, [pc, #224] @ (800cd18 ) 800cc36: 689b ldr r3, [r3, #8] 800cc38: b29a uxth r2, r3 800cc3a: 4b35 ldr r3, [pc, #212] @ (800cd10 ) 800cc3c: f8a3 2021 strh.w r2, [r3, #33] @ 0x21 statusPacket.phaseVoltageBC = PSU_06.VBC; 800cc40: 4b35 ldr r3, [pc, #212] @ (800cd18 ) 800cc42: 68db ldr r3, [r3, #12] 800cc44: b29a uxth r2, r3 800cc46: 4b32 ldr r3, [pc, #200] @ (800cd10 ) 800cc48: f8a3 2023 strh.w r2, [r3, #35] @ 0x23 statusPacket.phaseVoltageCA = PSU_06.VCA; 800cc4c: 4b32 ldr r3, [pc, #200] @ (800cd18 ) 800cc4e: 691b ldr r3, [r3, #16] 800cc50: b29a uxth r2, r3 800cc52: 4b2f ldr r3, [pc, #188] @ (800cd10 ) 800cc54: f8a3 2025 strh.w r2, [r3, #37] @ 0x25 // GBT TODO memset(statusPacket.VIN, 0, sizeof(statusPacket.VIN)); 800cc58: 2211 movs r2, #17 800cc5a: 2100 movs r1, #0 800cc5c: 482f ldr r0, [pc, #188] @ (800cd1c ) 800cc5e: f006 f9ab bl 8012fb8 // GBT TODO statusPacket.batteryType = 0; 800cc62: 4b2b ldr r3, [pc, #172] @ (800cd10 ) 800cc64: 2200 movs r2, #0 800cc66: f883 2038 strb.w r2, [r3, #56] @ 0x38 statusPacket.batteryCapacity = 0; 800cc6a: 4b29 ldr r3, [pc, #164] @ (800cd10 ) 800cc6c: 2200 movs r2, #0 800cc6e: f883 2039 strb.w r2, [r3, #57] @ 0x39 800cc72: 2200 movs r2, #0 800cc74: f883 203a strb.w r2, [r3, #58] @ 0x3a statusPacket.batteryVoltage = 0; 800cc78: 4b25 ldr r3, [pc, #148] @ (800cd10 ) 800cc7a: 2200 movs r2, #0 800cc7c: f883 203b strb.w r2, [r3, #59] @ 0x3b 800cc80: 2200 movs r2, #0 800cc82: f883 203c strb.w r2, [r3, #60] @ 0x3c memset(statusPacket.batteryVendor, 0, sizeof(statusPacket.batteryVendor)); 800cc86: 2204 movs r2, #4 800cc88: 2100 movs r1, #0 800cc8a: 4825 ldr r0, [pc, #148] @ (800cd20 ) 800cc8c: f006 f994 bl 8012fb8 statusPacket.batterySN = 0; 800cc90: 4b1f ldr r3, [pc, #124] @ (800cd10 ) 800cc92: 2200 movs r2, #0 800cc94: f883 2041 strb.w r2, [r3, #65] @ 0x41 800cc98: 2200 movs r2, #0 800cc9a: f883 2042 strb.w r2, [r3, #66] @ 0x42 800cc9e: 2200 movs r2, #0 800cca0: f883 2043 strb.w r2, [r3, #67] @ 0x43 800cca4: 2200 movs r2, #0 800cca6: f883 2044 strb.w r2, [r3, #68] @ 0x44 statusPacket.batteryManuD = 0; 800ccaa: 4b19 ldr r3, [pc, #100] @ (800cd10 ) 800ccac: 2200 movs r2, #0 800ccae: f883 2047 strb.w r2, [r3, #71] @ 0x47 statusPacket.batteryManuM = 0; 800ccb2: 4b17 ldr r3, [pc, #92] @ (800cd10 ) 800ccb4: 2200 movs r2, #0 800ccb6: f883 2046 strb.w r2, [r3, #70] @ 0x46 statusPacket.batteryManuY = 0; 800ccba: 4b15 ldr r3, [pc, #84] @ (800cd10 ) 800ccbc: 2200 movs r2, #0 800ccbe: f883 2045 strb.w r2, [r3, #69] @ 0x45 statusPacket.batteryCycleCount = 0; 800ccc2: 4b13 ldr r3, [pc, #76] @ (800cd10 ) 800ccc4: 2200 movs r2, #0 800ccc6: f883 2048 strb.w r2, [r3, #72] @ 0x48 800ccca: 2200 movs r2, #0 800cccc: f883 2049 strb.w r2, [r3, #73] @ 0x49 statusPacket.ownAuto = 0; 800ccd0: 4b0f ldr r3, [pc, #60] @ (800cd10 ) 800ccd2: 2200 movs r2, #0 800ccd4: f883 204a strb.w r2, [r3, #74] @ 0x4a memset(statusPacket.EV_SW_VER, 0, sizeof(statusPacket.EV_SW_VER)); 800ccd8: 2208 movs r2, #8 800ccda: 2100 movs r1, #0 800ccdc: 4811 ldr r0, [pc, #68] @ (800cd24 ) 800ccde: f006 f96b bl 8012fb8 statusPacket.testMode = 0; 800cce2: 4b0b ldr r3, [pc, #44] @ (800cd10 ) 800cce4: 2200 movs r2, #0 800cce6: f883 2053 strb.w r2, [r3, #83] @ 0x53 statusPacket.testVoltage = 0; 800ccea: 4b09 ldr r3, [pc, #36] @ (800cd10 ) 800ccec: 2200 movs r2, #0 800ccee: f883 2054 strb.w r2, [r3, #84] @ 0x54 800ccf2: 2200 movs r2, #0 800ccf4: f883 2055 strb.w r2, [r3, #85] @ 0x55 statusPacket.testCurrent = 0; 800ccf8: 4b05 ldr r3, [pc, #20] @ (800cd10 ) 800ccfa: 2200 movs r2, #0 800ccfc: f883 2056 strb.w r2, [r3, #86] @ 0x56 800cd00: 2200 movs r2, #0 800cd02: f883 2057 strb.w r2, [r3, #87] @ 0x57 // В debug.c есть CONN_SetState, предполагаем наличие CONN_GetState() // Если такой функции нет, закомментируйте следующую строку: // statusPacket.connState = CONN_GetState(); } 800cd06: bf00 nop 800cd08: bd80 pop {r7, pc} 800cd0a: bf00 nop 800cd0c: 200001d4 .word 0x200001d4 800cd10: 20000e58 .word 0x20000e58 800cd14: 20000724 .word 0x20000724 800cd18: 200006f8 .word 0x200006f8 800cd1c: 20000e7f .word 0x20000e7f 800cd20: 20000e95 .word 0x20000e95 800cd24: 20000ea3 .word 0x20000ea3 0800cd28 : #include "sma_filter.h" void SMAFilter_Init(SMAFilter_t* f) { 800cd28: b480 push {r7} 800cd2a: b085 sub sp, #20 800cd2c: af00 add r7, sp, #0 800cd2e: 6078 str r0, [r7, #4] if (f == 0) return; 800cd30: 687b ldr r3, [r7, #4] 800cd32: 2b00 cmp r3, #0 800cd34: d018 beq.n 800cd68 f->sum = 0; 800cd36: 687b ldr r3, [r7, #4] 800cd38: 2200 movs r2, #0 800cd3a: 601a str r2, [r3, #0] f->idx = 0; 800cd3c: 687b ldr r3, [r7, #4] 800cd3e: 2200 movs r2, #0 800cd40: 809a strh r2, [r3, #4] f->count = 0; 800cd42: 687b ldr r3, [r7, #4] 800cd44: 2200 movs r2, #0 800cd46: 80da strh r2, [r3, #6] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800cd48: 2300 movs r3, #0 800cd4a: 81fb strh r3, [r7, #14] 800cd4c: e008 b.n 800cd60 f->buffer[i] = 0; 800cd4e: 89fa ldrh r2, [r7, #14] 800cd50: 687b ldr r3, [r7, #4] 800cd52: 3202 adds r2, #2 800cd54: 2100 movs r1, #0 800cd56: f843 1022 str.w r1, [r3, r2, lsl #2] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800cd5a: 89fb ldrh r3, [r7, #14] 800cd5c: 3301 adds r3, #1 800cd5e: 81fb strh r3, [r7, #14] 800cd60: 89fb ldrh r3, [r7, #14] 800cd62: 2b07 cmp r3, #7 800cd64: d9f3 bls.n 800cd4e 800cd66: e000 b.n 800cd6a if (f == 0) return; 800cd68: bf00 nop } } 800cd6a: 3714 adds r7, #20 800cd6c: 46bd mov sp, r7 800cd6e: bc80 pop {r7} 800cd70: 4770 bx lr 0800cd72 : int32_t SMAFilter_Update(SMAFilter_t* f, int32_t x) { 800cd72: b480 push {r7} 800cd74: b085 sub sp, #20 800cd76: af00 add r7, sp, #0 800cd78: 6078 str r0, [r7, #4] 800cd7a: 6039 str r1, [r7, #0] if (f == 0) return x; 800cd7c: 687b ldr r3, [r7, #4] 800cd7e: 2b00 cmp r3, #0 800cd80: d101 bne.n 800cd86 800cd82: 683b ldr r3, [r7, #0] 800cd84: e056 b.n 800ce34 // Пока окно не заполнено полностью, делим по фактическому count. if (f->count < SMA_FILTER_WINDOW) { 800cd86: 687b ldr r3, [r7, #4] 800cd88: 88db ldrh r3, [r3, #6] 800cd8a: 2b07 cmp r3, #7 800cd8c: d827 bhi.n 800cdde f->buffer[f->idx] = x; 800cd8e: 687b ldr r3, [r7, #4] 800cd90: 889b ldrh r3, [r3, #4] 800cd92: 461a mov r2, r3 800cd94: 687b ldr r3, [r7, #4] 800cd96: 3202 adds r2, #2 800cd98: 6839 ldr r1, [r7, #0] 800cd9a: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += x; 800cd9e: 687b ldr r3, [r7, #4] 800cda0: 681a ldr r2, [r3, #0] 800cda2: 683b ldr r3, [r7, #0] 800cda4: 441a add r2, r3 800cda6: 687b ldr r3, [r7, #4] 800cda8: 601a str r2, [r3, #0] f->idx++; 800cdaa: 687b ldr r3, [r7, #4] 800cdac: 889b ldrh r3, [r3, #4] 800cdae: 3301 adds r3, #1 800cdb0: b29a uxth r2, r3 800cdb2: 687b ldr r3, [r7, #4] 800cdb4: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800cdb6: 687b ldr r3, [r7, #4] 800cdb8: 889b ldrh r3, [r3, #4] 800cdba: 2b07 cmp r3, #7 800cdbc: d902 bls.n 800cdc4 800cdbe: 687b ldr r3, [r7, #4] 800cdc0: 2200 movs r2, #0 800cdc2: 809a strh r2, [r3, #4] f->count++; 800cdc4: 687b ldr r3, [r7, #4] 800cdc6: 88db ldrh r3, [r3, #6] 800cdc8: 3301 adds r3, #1 800cdca: b29a uxth r2, r3 800cdcc: 687b ldr r3, [r7, #4] 800cdce: 80da strh r2, [r3, #6] return (int32_t)(f->sum / (int32_t)f->count); 800cdd0: 687b ldr r3, [r7, #4] 800cdd2: 681b ldr r3, [r3, #0] 800cdd4: 687a ldr r2, [r7, #4] 800cdd6: 88d2 ldrh r2, [r2, #6] 800cdd8: fb93 f3f2 sdiv r3, r3, r2 800cddc: e02a b.n 800ce34 } // Окно заполнено: "вычитаем старое + добавляем новое". int32_t old = f->buffer[f->idx]; 800cdde: 687b ldr r3, [r7, #4] 800cde0: 889b ldrh r3, [r3, #4] 800cde2: 461a mov r2, r3 800cde4: 687b ldr r3, [r7, #4] 800cde6: 3202 adds r2, #2 800cde8: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800cdec: 60fb str r3, [r7, #12] f->buffer[f->idx] = x; 800cdee: 687b ldr r3, [r7, #4] 800cdf0: 889b ldrh r3, [r3, #4] 800cdf2: 461a mov r2, r3 800cdf4: 687b ldr r3, [r7, #4] 800cdf6: 3202 adds r2, #2 800cdf8: 6839 ldr r1, [r7, #0] 800cdfa: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += (x - old); 800cdfe: 687b ldr r3, [r7, #4] 800ce00: 681a ldr r2, [r3, #0] 800ce02: 6839 ldr r1, [r7, #0] 800ce04: 68fb ldr r3, [r7, #12] 800ce06: 1acb subs r3, r1, r3 800ce08: 441a add r2, r3 800ce0a: 687b ldr r3, [r7, #4] 800ce0c: 601a str r2, [r3, #0] f->idx++; 800ce0e: 687b ldr r3, [r7, #4] 800ce10: 889b ldrh r3, [r3, #4] 800ce12: 3301 adds r3, #1 800ce14: b29a uxth r2, r3 800ce16: 687b ldr r3, [r7, #4] 800ce18: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800ce1a: 687b ldr r3, [r7, #4] 800ce1c: 889b ldrh r3, [r3, #4] 800ce1e: 2b07 cmp r3, #7 800ce20: d902 bls.n 800ce28 800ce22: 687b ldr r3, [r7, #4] 800ce24: 2200 movs r2, #0 800ce26: 809a strh r2, [r3, #4] return (int32_t)(f->sum / (int32_t)SMA_FILTER_WINDOW); 800ce28: 687b ldr r3, [r7, #4] 800ce2a: 681b ldr r3, [r3, #0] 800ce2c: 2b00 cmp r3, #0 800ce2e: da00 bge.n 800ce32 800ce30: 3307 adds r3, #7 800ce32: 10db asrs r3, r3, #3 } 800ce34: 4618 mov r0, r3 800ce36: 3714 adds r7, #20 800ce38: 46bd mov sp, r7 800ce3a: bc80 pop {r7} 800ce3c: 4770 bx lr ... 0800ce40 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800ce40: b480 push {r7} 800ce42: b085 sub sp, #20 800ce44: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 800ce46: 4b15 ldr r3, [pc, #84] @ (800ce9c ) 800ce48: 699b ldr r3, [r3, #24] 800ce4a: 4a14 ldr r2, [pc, #80] @ (800ce9c ) 800ce4c: f043 0301 orr.w r3, r3, #1 800ce50: 6193 str r3, [r2, #24] 800ce52: 4b12 ldr r3, [pc, #72] @ (800ce9c ) 800ce54: 699b ldr r3, [r3, #24] 800ce56: f003 0301 and.w r3, r3, #1 800ce5a: 60bb str r3, [r7, #8] 800ce5c: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800ce5e: 4b0f ldr r3, [pc, #60] @ (800ce9c ) 800ce60: 69db ldr r3, [r3, #28] 800ce62: 4a0e ldr r2, [pc, #56] @ (800ce9c ) 800ce64: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800ce68: 61d3 str r3, [r2, #28] 800ce6a: 4b0c ldr r3, [pc, #48] @ (800ce9c ) 800ce6c: 69db ldr r3, [r3, #28] 800ce6e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800ce72: 607b str r3, [r7, #4] 800ce74: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 800ce76: 4b0a ldr r3, [pc, #40] @ (800cea0 ) 800ce78: 685b ldr r3, [r3, #4] 800ce7a: 60fb str r3, [r7, #12] 800ce7c: 68fb ldr r3, [r7, #12] 800ce7e: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 800ce82: 60fb str r3, [r7, #12] 800ce84: 68fb ldr r3, [r7, #12] 800ce86: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 800ce8a: 60fb str r3, [r7, #12] 800ce8c: 4a04 ldr r2, [pc, #16] @ (800cea0 ) 800ce8e: 68fb ldr r3, [r7, #12] 800ce90: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800ce92: bf00 nop 800ce94: 3714 adds r7, #20 800ce96: 46bd mov sp, r7 800ce98: bc80 pop {r7} 800ce9a: 4770 bx lr 800ce9c: 40021000 .word 0x40021000 800cea0: 40010000 .word 0x40010000 0800cea4 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 800cea4: b480 push {r7} 800cea6: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800cea8: bf00 nop 800ceaa: e7fd b.n 800cea8 0800ceac : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800ceac: b480 push {r7} 800ceae: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800ceb0: bf00 nop 800ceb2: e7fd b.n 800ceb0 0800ceb4 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 800ceb4: b480 push {r7} 800ceb6: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800ceb8: bf00 nop 800ceba: e7fd b.n 800ceb8 0800cebc : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 800cebc: b480 push {r7} 800cebe: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800cec0: bf00 nop 800cec2: e7fd b.n 800cec0 0800cec4 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 800cec4: b480 push {r7} 800cec6: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 800cec8: bf00 nop 800ceca: e7fd b.n 800cec8 0800cecc : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 800cecc: b480 push {r7} 800cece: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800ced0: bf00 nop 800ced2: 46bd mov sp, r7 800ced4: bc80 pop {r7} 800ced6: 4770 bx lr 0800ced8 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 800ced8: b480 push {r7} 800ceda: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800cedc: bf00 nop 800cede: 46bd mov sp, r7 800cee0: bc80 pop {r7} 800cee2: 4770 bx lr 0800cee4 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800cee4: b480 push {r7} 800cee6: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800cee8: bf00 nop 800ceea: 46bd mov sp, r7 800ceec: bc80 pop {r7} 800ceee: 4770 bx lr 0800cef0 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800cef0: b580 push {r7, lr} 800cef2: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800cef4: f000 fcdc bl 800d8b0 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 800cef8: bf00 nop 800cefa: bd80 pop {r7, pc} 0800cefc : /** * @brief This function handles CAN1 RX0 interrupt. */ void CAN1_RX0_IRQHandler(void) { 800cefc: b580 push {r7, lr} 800cefe: af00 add r7, sp, #0 /* USER CODE BEGIN CAN1_RX0_IRQn 0 */ /* USER CODE END CAN1_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan1); 800cf00: 4802 ldr r0, [pc, #8] @ (800cf0c ) 800cf02: f001 fecd bl 800eca0 /* USER CODE BEGIN CAN1_RX0_IRQn 1 */ /* USER CODE END CAN1_RX0_IRQn 1 */ } 800cf06: bf00 nop 800cf08: bd80 pop {r7, pc} 800cf0a: bf00 nop 800cf0c: 20000180 .word 0x20000180 0800cf10 : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 800cf10: b580 push {r7, lr} 800cf12: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_IRQn 0 */ /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 800cf14: 4802 ldr r0, [pc, #8] @ (800cf20 ) 800cf16: f004 f8c3 bl 80110a0 /* USER CODE BEGIN TIM3_IRQn 1 */ /* USER CODE END TIM3_IRQn 1 */ } 800cf1a: bf00 nop 800cf1c: bd80 pop {r7, pc} 800cf1e: bf00 nop 800cf20: 20000ec0 .word 0x20000ec0 0800cf24 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 800cf24: b580 push {r7, lr} 800cf26: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 800cf28: 4802 ldr r0, [pc, #8] @ (800cf34 ) 800cf2a: f005 f90b bl 8012144 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 800cf2e: bf00 nop 800cf30: bd80 pop {r7, pc} 800cf32: bf00 nop 800cf34: 20000f98 .word 0x20000f98 0800cf38 : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 800cf38: b580 push {r7, lr} 800cf3a: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 800cf3c: 4802 ldr r0, [pc, #8] @ (800cf48 ) 800cf3e: f005 f901 bl 8012144 /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 800cf42: bf00 nop 800cf44: bd80 pop {r7, pc} 800cf46: bf00 nop 800cf48: 20000fe0 .word 0x20000fe0 0800cf4c : /** * @brief This function handles USART3 global interrupt. */ void USART3_IRQHandler(void) { 800cf4c: b580 push {r7, lr} 800cf4e: af00 add r7, sp, #0 /* USER CODE BEGIN USART3_IRQn 0 */ /* USER CODE END USART3_IRQn 0 */ HAL_UART_IRQHandler(&huart3); 800cf50: 4802 ldr r0, [pc, #8] @ (800cf5c ) 800cf52: f005 f8f7 bl 8012144 /* USER CODE BEGIN USART3_IRQn 1 */ /* USER CODE END USART3_IRQn 1 */ } 800cf56: bf00 nop 800cf58: bd80 pop {r7, pc} 800cf5a: bf00 nop 800cf5c: 20001028 .word 0x20001028 0800cf60 : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 800cf60: b580 push {r7, lr} 800cf62: af00 add r7, sp, #0 /* USER CODE BEGIN UART5_IRQn 0 */ /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 800cf64: 4802 ldr r0, [pc, #8] @ (800cf70 ) 800cf66: f005 f8ed bl 8012144 /* USER CODE BEGIN UART5_IRQn 1 */ /* USER CODE END UART5_IRQn 1 */ } 800cf6a: bf00 nop 800cf6c: bd80 pop {r7, pc} 800cf6e: bf00 nop 800cf70: 20000f50 .word 0x20000f50 0800cf74 : /** * @brief This function handles CAN2 TX interrupt. */ void CAN2_TX_IRQHandler(void) { 800cf74: b580 push {r7, lr} 800cf76: af00 add r7, sp, #0 /* USER CODE BEGIN CAN2_TX_IRQn 0 */ /* USER CODE END CAN2_TX_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800cf78: 4802 ldr r0, [pc, #8] @ (800cf84 ) 800cf7a: f001 fe91 bl 800eca0 /* USER CODE BEGIN CAN2_TX_IRQn 1 */ /* USER CODE END CAN2_TX_IRQn 1 */ } 800cf7e: bf00 nop 800cf80: bd80 pop {r7, pc} 800cf82: bf00 nop 800cf84: 200001a8 .word 0x200001a8 0800cf88 : /** * @brief This function handles CAN2 RX1 interrupt. */ void CAN2_RX1_IRQHandler(void) { 800cf88: b580 push {r7, lr} 800cf8a: af00 add r7, sp, #0 /* USER CODE BEGIN CAN2_RX1_IRQn 0 */ /* USER CODE END CAN2_RX1_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800cf8c: 4802 ldr r0, [pc, #8] @ (800cf98 ) 800cf8e: f001 fe87 bl 800eca0 /* USER CODE BEGIN CAN2_RX1_IRQn 1 */ /* USER CODE END CAN2_RX1_IRQn 1 */ } 800cf92: bf00 nop 800cf94: bd80 pop {r7, pc} 800cf96: bf00 nop 800cf98: 200001a8 .word 0x200001a8 0800cf9c <_read>: _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { 800cf9c: b580 push {r7, lr} 800cf9e: b086 sub sp, #24 800cfa0: af00 add r7, sp, #0 800cfa2: 60f8 str r0, [r7, #12] 800cfa4: 60b9 str r1, [r7, #8] 800cfa6: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800cfa8: 2300 movs r3, #0 800cfaa: 617b str r3, [r7, #20] 800cfac: e00a b.n 800cfc4 <_read+0x28> { *ptr++ = __io_getchar(); 800cfae: f3af 8000 nop.w 800cfb2: 4601 mov r1, r0 800cfb4: 68bb ldr r3, [r7, #8] 800cfb6: 1c5a adds r2, r3, #1 800cfb8: 60ba str r2, [r7, #8] 800cfba: b2ca uxtb r2, r1 800cfbc: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 800cfbe: 697b ldr r3, [r7, #20] 800cfc0: 3301 adds r3, #1 800cfc2: 617b str r3, [r7, #20] 800cfc4: 697a ldr r2, [r7, #20] 800cfc6: 687b ldr r3, [r7, #4] 800cfc8: 429a cmp r2, r3 800cfca: dbf0 blt.n 800cfae <_read+0x12> } return len; 800cfcc: 687b ldr r3, [r7, #4] } 800cfce: 4618 mov r0, r3 800cfd0: 3718 adds r7, #24 800cfd2: 46bd mov sp, r7 800cfd4: bd80 pop {r7, pc} 0800cfd6 <_close>: } return len; } int _close(int file) { 800cfd6: b480 push {r7} 800cfd8: b083 sub sp, #12 800cfda: af00 add r7, sp, #0 800cfdc: 6078 str r0, [r7, #4] (void)file; return -1; 800cfde: f04f 33ff mov.w r3, #4294967295 } 800cfe2: 4618 mov r0, r3 800cfe4: 370c adds r7, #12 800cfe6: 46bd mov sp, r7 800cfe8: bc80 pop {r7} 800cfea: 4770 bx lr 0800cfec <_fstat>: int _fstat(int file, struct stat *st) { 800cfec: b480 push {r7} 800cfee: b083 sub sp, #12 800cff0: af00 add r7, sp, #0 800cff2: 6078 str r0, [r7, #4] 800cff4: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 800cff6: 683b ldr r3, [r7, #0] 800cff8: f44f 5200 mov.w r2, #8192 @ 0x2000 800cffc: 605a str r2, [r3, #4] return 0; 800cffe: 2300 movs r3, #0 } 800d000: 4618 mov r0, r3 800d002: 370c adds r7, #12 800d004: 46bd mov sp, r7 800d006: bc80 pop {r7} 800d008: 4770 bx lr 0800d00a <_isatty>: int _isatty(int file) { 800d00a: b480 push {r7} 800d00c: b083 sub sp, #12 800d00e: af00 add r7, sp, #0 800d010: 6078 str r0, [r7, #4] (void)file; return 1; 800d012: 2301 movs r3, #1 } 800d014: 4618 mov r0, r3 800d016: 370c adds r7, #12 800d018: 46bd mov sp, r7 800d01a: bc80 pop {r7} 800d01c: 4770 bx lr 0800d01e <_lseek>: int _lseek(int file, int ptr, int dir) { 800d01e: b480 push {r7} 800d020: b085 sub sp, #20 800d022: af00 add r7, sp, #0 800d024: 60f8 str r0, [r7, #12] 800d026: 60b9 str r1, [r7, #8] 800d028: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 800d02a: 2300 movs r3, #0 } 800d02c: 4618 mov r0, r3 800d02e: 3714 adds r7, #20 800d030: 46bd mov sp, r7 800d032: bc80 pop {r7} 800d034: 4770 bx lr ... 0800d038 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 800d038: b580 push {r7, lr} 800d03a: b086 sub sp, #24 800d03c: af00 add r7, sp, #0 800d03e: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 800d040: 4a14 ldr r2, [pc, #80] @ (800d094 <_sbrk+0x5c>) 800d042: 4b15 ldr r3, [pc, #84] @ (800d098 <_sbrk+0x60>) 800d044: 1ad3 subs r3, r2, r3 800d046: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 800d048: 697b ldr r3, [r7, #20] 800d04a: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 800d04c: 4b13 ldr r3, [pc, #76] @ (800d09c <_sbrk+0x64>) 800d04e: 681b ldr r3, [r3, #0] 800d050: 2b00 cmp r3, #0 800d052: d102 bne.n 800d05a <_sbrk+0x22> { __sbrk_heap_end = &_end; 800d054: 4b11 ldr r3, [pc, #68] @ (800d09c <_sbrk+0x64>) 800d056: 4a12 ldr r2, [pc, #72] @ (800d0a0 <_sbrk+0x68>) 800d058: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 800d05a: 4b10 ldr r3, [pc, #64] @ (800d09c <_sbrk+0x64>) 800d05c: 681a ldr r2, [r3, #0] 800d05e: 687b ldr r3, [r7, #4] 800d060: 4413 add r3, r2 800d062: 693a ldr r2, [r7, #16] 800d064: 429a cmp r2, r3 800d066: d207 bcs.n 800d078 <_sbrk+0x40> { errno = ENOMEM; 800d068: f005 fff4 bl 8013054 <__errno> 800d06c: 4603 mov r3, r0 800d06e: 220c movs r2, #12 800d070: 601a str r2, [r3, #0] return (void *)-1; 800d072: f04f 33ff mov.w r3, #4294967295 800d076: e009 b.n 800d08c <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 800d078: 4b08 ldr r3, [pc, #32] @ (800d09c <_sbrk+0x64>) 800d07a: 681b ldr r3, [r3, #0] 800d07c: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 800d07e: 4b07 ldr r3, [pc, #28] @ (800d09c <_sbrk+0x64>) 800d080: 681a ldr r2, [r3, #0] 800d082: 687b ldr r3, [r7, #4] 800d084: 4413 add r3, r2 800d086: 4a05 ldr r2, [pc, #20] @ (800d09c <_sbrk+0x64>) 800d088: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 800d08a: 68fb ldr r3, [r7, #12] } 800d08c: 4618 mov r0, r3 800d08e: 3718 adds r7, #24 800d090: 46bd mov sp, r7 800d092: bd80 pop {r7, pc} 800d094: 20010000 .word 0x20010000 800d098: 00000400 .word 0x00000400 800d09c: 20000ebc .word 0x20000ebc 800d0a0: 200011c0 .word 0x200011c0 0800d0a4 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 800d0a4: b480 push {r7} 800d0a6: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 800d0a8: bf00 nop 800d0aa: 46bd mov sp, r7 800d0ac: bc80 pop {r7} 800d0ae: 4770 bx lr 0800d0b0 : TIM_HandleTypeDef htim3; TIM_HandleTypeDef htim4; /* TIM3 init function */ void MX_TIM3_Init(void) { 800d0b0: b580 push {r7, lr} 800d0b2: b08e sub sp, #56 @ 0x38 800d0b4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800d0b6: f107 0328 add.w r3, r7, #40 @ 0x28 800d0ba: 2200 movs r2, #0 800d0bc: 601a str r2, [r3, #0] 800d0be: 605a str r2, [r3, #4] 800d0c0: 609a str r2, [r3, #8] 800d0c2: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800d0c4: f107 0320 add.w r3, r7, #32 800d0c8: 2200 movs r2, #0 800d0ca: 601a str r2, [r3, #0] 800d0cc: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800d0ce: 1d3b adds r3, r7, #4 800d0d0: 2200 movs r2, #0 800d0d2: 601a str r2, [r3, #0] 800d0d4: 605a str r2, [r3, #4] 800d0d6: 609a str r2, [r3, #8] 800d0d8: 60da str r2, [r3, #12] 800d0da: 611a str r2, [r3, #16] 800d0dc: 615a str r2, [r3, #20] 800d0de: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 800d0e0: 4b2c ldr r3, [pc, #176] @ (800d194 ) 800d0e2: 4a2d ldr r2, [pc, #180] @ (800d198 ) 800d0e4: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 800d0e6: 4b2b ldr r3, [pc, #172] @ (800d194 ) 800d0e8: 2200 movs r2, #0 800d0ea: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 800d0ec: 4b29 ldr r3, [pc, #164] @ (800d194 ) 800d0ee: 2200 movs r2, #0 800d0f0: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 800d0f2: 4b28 ldr r3, [pc, #160] @ (800d194 ) 800d0f4: f64f 72ff movw r2, #65535 @ 0xffff 800d0f8: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800d0fa: 4b26 ldr r3, [pc, #152] @ (800d194 ) 800d0fc: 2200 movs r2, #0 800d0fe: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800d100: 4b24 ldr r3, [pc, #144] @ (800d194 ) 800d102: 2200 movs r2, #0 800d104: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 800d106: 4823 ldr r0, [pc, #140] @ (800d194 ) 800d108: f003 fd83 bl 8010c12 800d10c: 4603 mov r3, r0 800d10e: 2b00 cmp r3, #0 800d110: d001 beq.n 800d116 { Error_Handler(); 800d112: f7fd fc6d bl 800a9f0 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800d116: f44f 5380 mov.w r3, #4096 @ 0x1000 800d11a: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 800d11c: f107 0328 add.w r3, r7, #40 @ 0x28 800d120: 4619 mov r1, r3 800d122: 481c ldr r0, [pc, #112] @ (800d194 ) 800d124: f004 f96e bl 8011404 800d128: 4603 mov r3, r0 800d12a: 2b00 cmp r3, #0 800d12c: d001 beq.n 800d132 { Error_Handler(); 800d12e: f7fd fc5f bl 800a9f0 } if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 800d132: 4818 ldr r0, [pc, #96] @ (800d194 ) 800d134: f003 feb2 bl 8010e9c 800d138: 4603 mov r3, r0 800d13a: 2b00 cmp r3, #0 800d13c: d001 beq.n 800d142 { Error_Handler(); 800d13e: f7fd fc57 bl 800a9f0 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800d142: 2300 movs r3, #0 800d144: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800d146: 2300 movs r3, #0 800d148: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800d14a: f107 0320 add.w r3, r7, #32 800d14e: 4619 mov r1, r3 800d150: 4810 ldr r0, [pc, #64] @ (800d194 ) 800d152: f004 fcfd bl 8011b50 800d156: 4603 mov r3, r0 800d158: 2b00 cmp r3, #0 800d15a: d001 beq.n 800d160 { Error_Handler(); 800d15c: f7fd fc48 bl 800a9f0 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800d160: 2360 movs r3, #96 @ 0x60 800d162: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800d164: 2300 movs r3, #0 800d166: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800d168: 2300 movs r3, #0 800d16a: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800d16c: 2300 movs r3, #0 800d16e: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800d170: 1d3b adds r3, r7, #4 800d172: 2204 movs r2, #4 800d174: 4619 mov r1, r3 800d176: 4807 ldr r0, [pc, #28] @ (800d194 ) 800d178: f004 f882 bl 8011280 800d17c: 4603 mov r3, r0 800d17e: 2b00 cmp r3, #0 800d180: d001 beq.n 800d186 { Error_Handler(); 800d182: f7fd fc35 bl 800a9f0 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 800d186: 4803 ldr r0, [pc, #12] @ (800d194 ) 800d188: f000 f8ce bl 800d328 } 800d18c: bf00 nop 800d18e: 3738 adds r7, #56 @ 0x38 800d190: 46bd mov sp, r7 800d192: bd80 pop {r7, pc} 800d194: 20000ec0 .word 0x20000ec0 800d198: 40000400 .word 0x40000400 0800d19c : /* TIM4 init function */ void MX_TIM4_Init(void) { 800d19c: b580 push {r7, lr} 800d19e: b08e sub sp, #56 @ 0x38 800d1a0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800d1a2: f107 0328 add.w r3, r7, #40 @ 0x28 800d1a6: 2200 movs r2, #0 800d1a8: 601a str r2, [r3, #0] 800d1aa: 605a str r2, [r3, #4] 800d1ac: 609a str r2, [r3, #8] 800d1ae: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800d1b0: f107 0320 add.w r3, r7, #32 800d1b4: 2200 movs r2, #0 800d1b6: 601a str r2, [r3, #0] 800d1b8: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800d1ba: 1d3b adds r3, r7, #4 800d1bc: 2200 movs r2, #0 800d1be: 601a str r2, [r3, #0] 800d1c0: 605a str r2, [r3, #4] 800d1c2: 609a str r2, [r3, #8] 800d1c4: 60da str r2, [r3, #12] 800d1c6: 611a str r2, [r3, #16] 800d1c8: 615a str r2, [r3, #20] 800d1ca: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM4_Init 1 */ /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; 800d1cc: 4b37 ldr r3, [pc, #220] @ (800d2ac ) 800d1ce: 4a38 ldr r2, [pc, #224] @ (800d2b0 ) 800d1d0: 601a str r2, [r3, #0] htim4.Init.Prescaler = 720; 800d1d2: 4b36 ldr r3, [pc, #216] @ (800d2ac ) 800d1d4: f44f 7234 mov.w r2, #720 @ 0x2d0 800d1d8: 605a str r2, [r3, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 800d1da: 4b34 ldr r3, [pc, #208] @ (800d2ac ) 800d1dc: 2200 movs r2, #0 800d1de: 609a str r2, [r3, #8] htim4.Init.Period = 100; 800d1e0: 4b32 ldr r3, [pc, #200] @ (800d2ac ) 800d1e2: 2264 movs r2, #100 @ 0x64 800d1e4: 60da str r2, [r3, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800d1e6: 4b31 ldr r3, [pc, #196] @ (800d2ac ) 800d1e8: 2200 movs r2, #0 800d1ea: 611a str r2, [r3, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800d1ec: 4b2f ldr r3, [pc, #188] @ (800d2ac ) 800d1ee: 2200 movs r2, #0 800d1f0: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 800d1f2: 482e ldr r0, [pc, #184] @ (800d2ac ) 800d1f4: f003 fd0d bl 8010c12 800d1f8: 4603 mov r3, r0 800d1fa: 2b00 cmp r3, #0 800d1fc: d001 beq.n 800d202 { Error_Handler(); 800d1fe: f7fd fbf7 bl 800a9f0 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800d202: f44f 5380 mov.w r3, #4096 @ 0x1000 800d206: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 800d208: f107 0328 add.w r3, r7, #40 @ 0x28 800d20c: 4619 mov r1, r3 800d20e: 4827 ldr r0, [pc, #156] @ (800d2ac ) 800d210: f004 f8f8 bl 8011404 800d214: 4603 mov r3, r0 800d216: 2b00 cmp r3, #0 800d218: d001 beq.n 800d21e { Error_Handler(); 800d21a: f7fd fbe9 bl 800a9f0 } if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) 800d21e: 4823 ldr r0, [pc, #140] @ (800d2ac ) 800d220: f003 fe3c bl 8010e9c 800d224: 4603 mov r3, r0 800d226: 2b00 cmp r3, #0 800d228: d001 beq.n 800d22e { Error_Handler(); 800d22a: f7fd fbe1 bl 800a9f0 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800d22e: 2300 movs r3, #0 800d230: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800d232: 2300 movs r3, #0 800d234: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 800d236: f107 0320 add.w r3, r7, #32 800d23a: 4619 mov r1, r3 800d23c: 481b ldr r0, [pc, #108] @ (800d2ac ) 800d23e: f004 fc87 bl 8011b50 800d242: 4603 mov r3, r0 800d244: 2b00 cmp r3, #0 800d246: d001 beq.n 800d24c { Error_Handler(); 800d248: f7fd fbd2 bl 800a9f0 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800d24c: 2360 movs r3, #96 @ 0x60 800d24e: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800d250: 2300 movs r3, #0 800d252: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800d254: 2300 movs r3, #0 800d256: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800d258: 2300 movs r3, #0 800d25a: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800d25c: 1d3b adds r3, r7, #4 800d25e: 2204 movs r2, #4 800d260: 4619 mov r1, r3 800d262: 4812 ldr r0, [pc, #72] @ (800d2ac ) 800d264: f004 f80c bl 8011280 800d268: 4603 mov r3, r0 800d26a: 2b00 cmp r3, #0 800d26c: d001 beq.n 800d272 { Error_Handler(); 800d26e: f7fd fbbf bl 800a9f0 } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 800d272: 1d3b adds r3, r7, #4 800d274: 2208 movs r2, #8 800d276: 4619 mov r1, r3 800d278: 480c ldr r0, [pc, #48] @ (800d2ac ) 800d27a: f004 f801 bl 8011280 800d27e: 4603 mov r3, r0 800d280: 2b00 cmp r3, #0 800d282: d001 beq.n 800d288 { Error_Handler(); 800d284: f7fd fbb4 bl 800a9f0 } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 800d288: 1d3b adds r3, r7, #4 800d28a: 220c movs r2, #12 800d28c: 4619 mov r1, r3 800d28e: 4807 ldr r0, [pc, #28] @ (800d2ac ) 800d290: f003 fff6 bl 8011280 800d294: 4603 mov r3, r0 800d296: 2b00 cmp r3, #0 800d298: d001 beq.n 800d29e { Error_Handler(); 800d29a: f7fd fba9 bl 800a9f0 } /* USER CODE BEGIN TIM4_Init 2 */ /* USER CODE END TIM4_Init 2 */ HAL_TIM_MspPostInit(&htim4); 800d29e: 4803 ldr r0, [pc, #12] @ (800d2ac ) 800d2a0: f000 f842 bl 800d328 } 800d2a4: bf00 nop 800d2a6: 3738 adds r7, #56 @ 0x38 800d2a8: 46bd mov sp, r7 800d2aa: bd80 pop {r7, pc} 800d2ac: 20000f08 .word 0x20000f08 800d2b0: 40000800 .word 0x40000800 0800d2b4 : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 800d2b4: b580 push {r7, lr} 800d2b6: b084 sub sp, #16 800d2b8: af00 add r7, sp, #0 800d2ba: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM3) 800d2bc: 687b ldr r3, [r7, #4] 800d2be: 681b ldr r3, [r3, #0] 800d2c0: 4a16 ldr r2, [pc, #88] @ (800d31c ) 800d2c2: 4293 cmp r3, r2 800d2c4: d114 bne.n 800d2f0 { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 800d2c6: 4b16 ldr r3, [pc, #88] @ (800d320 ) 800d2c8: 69db ldr r3, [r3, #28] 800d2ca: 4a15 ldr r2, [pc, #84] @ (800d320 ) 800d2cc: f043 0302 orr.w r3, r3, #2 800d2d0: 61d3 str r3, [r2, #28] 800d2d2: 4b13 ldr r3, [pc, #76] @ (800d320 ) 800d2d4: 69db ldr r3, [r3, #28] 800d2d6: f003 0302 and.w r3, r3, #2 800d2da: 60fb str r3, [r7, #12] 800d2dc: 68fb ldr r3, [r7, #12] /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); 800d2de: 2200 movs r2, #0 800d2e0: 2100 movs r1, #0 800d2e2: 201d movs r0, #29 800d2e4: f001 ffd7 bl 800f296 HAL_NVIC_EnableIRQ(TIM3_IRQn); 800d2e8: 201d movs r0, #29 800d2ea: f001 fff0 bl 800f2ce __HAL_RCC_TIM4_CLK_ENABLE(); /* USER CODE BEGIN TIM4_MspInit 1 */ /* USER CODE END TIM4_MspInit 1 */ } } 800d2ee: e010 b.n 800d312 else if(tim_baseHandle->Instance==TIM4) 800d2f0: 687b ldr r3, [r7, #4] 800d2f2: 681b ldr r3, [r3, #0] 800d2f4: 4a0b ldr r2, [pc, #44] @ (800d324 ) 800d2f6: 4293 cmp r3, r2 800d2f8: d10b bne.n 800d312 __HAL_RCC_TIM4_CLK_ENABLE(); 800d2fa: 4b09 ldr r3, [pc, #36] @ (800d320 ) 800d2fc: 69db ldr r3, [r3, #28] 800d2fe: 4a08 ldr r2, [pc, #32] @ (800d320 ) 800d300: f043 0304 orr.w r3, r3, #4 800d304: 61d3 str r3, [r2, #28] 800d306: 4b06 ldr r3, [pc, #24] @ (800d320 ) 800d308: 69db ldr r3, [r3, #28] 800d30a: f003 0304 and.w r3, r3, #4 800d30e: 60bb str r3, [r7, #8] 800d310: 68bb ldr r3, [r7, #8] } 800d312: bf00 nop 800d314: 3710 adds r7, #16 800d316: 46bd mov sp, r7 800d318: bd80 pop {r7, pc} 800d31a: bf00 nop 800d31c: 40000400 .word 0x40000400 800d320: 40021000 .word 0x40021000 800d324: 40000800 .word 0x40000800 0800d328 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 800d328: b580 push {r7, lr} 800d32a: b08a sub sp, #40 @ 0x28 800d32c: af00 add r7, sp, #0 800d32e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800d330: f107 0314 add.w r3, r7, #20 800d334: 2200 movs r2, #0 800d336: 601a str r2, [r3, #0] 800d338: 605a str r2, [r3, #4] 800d33a: 609a str r2, [r3, #8] 800d33c: 60da str r2, [r3, #12] if(timHandle->Instance==TIM3) 800d33e: 687b ldr r3, [r7, #4] 800d340: 681b ldr r3, [r3, #0] 800d342: 4a26 ldr r2, [pc, #152] @ (800d3dc ) 800d344: 4293 cmp r3, r2 800d346: d118 bne.n 800d37a { /* USER CODE BEGIN TIM3_MspPostInit 0 */ /* USER CODE END TIM3_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800d348: 4b25 ldr r3, [pc, #148] @ (800d3e0 ) 800d34a: 699b ldr r3, [r3, #24] 800d34c: 4a24 ldr r2, [pc, #144] @ (800d3e0 ) 800d34e: f043 0304 orr.w r3, r3, #4 800d352: 6193 str r3, [r2, #24] 800d354: 4b22 ldr r3, [pc, #136] @ (800d3e0 ) 800d356: 699b ldr r3, [r3, #24] 800d358: f003 0304 and.w r3, r3, #4 800d35c: 613b str r3, [r7, #16] 800d35e: 693b ldr r3, [r7, #16] /**TIM3 GPIO Configuration PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = CP_PWM_Pin; 800d360: 2380 movs r3, #128 @ 0x80 800d362: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d364: 2302 movs r3, #2 800d366: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800d368: 2302 movs r3, #2 800d36a: 623b str r3, [r7, #32] HAL_GPIO_Init(CP_PWM_GPIO_Port, &GPIO_InitStruct); 800d36c: f107 0314 add.w r3, r7, #20 800d370: 4619 mov r1, r3 800d372: 481c ldr r0, [pc, #112] @ (800d3e4 ) 800d374: f002 f924 bl 800f5c0 /* USER CODE BEGIN TIM4_MspPostInit 1 */ /* USER CODE END TIM4_MspPostInit 1 */ } } 800d378: e02b b.n 800d3d2 else if(timHandle->Instance==TIM4) 800d37a: 687b ldr r3, [r7, #4] 800d37c: 681b ldr r3, [r3, #0] 800d37e: 4a1a ldr r2, [pc, #104] @ (800d3e8 ) 800d380: 4293 cmp r3, r2 800d382: d126 bne.n 800d3d2 __HAL_RCC_GPIOD_CLK_ENABLE(); 800d384: 4b16 ldr r3, [pc, #88] @ (800d3e0 ) 800d386: 699b ldr r3, [r3, #24] 800d388: 4a15 ldr r2, [pc, #84] @ (800d3e0 ) 800d38a: f043 0320 orr.w r3, r3, #32 800d38e: 6193 str r3, [r2, #24] 800d390: 4b13 ldr r3, [pc, #76] @ (800d3e0 ) 800d392: 699b ldr r3, [r3, #24] 800d394: f003 0320 and.w r3, r3, #32 800d398: 60fb str r3, [r7, #12] 800d39a: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; 800d39c: f44f 4360 mov.w r3, #57344 @ 0xe000 800d3a0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d3a2: 2302 movs r3, #2 800d3a4: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800d3a6: 2302 movs r3, #2 800d3a8: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d3aa: f107 0314 add.w r3, r7, #20 800d3ae: 4619 mov r1, r3 800d3b0: 480e ldr r0, [pc, #56] @ (800d3ec ) 800d3b2: f002 f905 bl 800f5c0 __HAL_AFIO_REMAP_TIM4_ENABLE(); 800d3b6: 4b0e ldr r3, [pc, #56] @ (800d3f0 ) 800d3b8: 685b ldr r3, [r3, #4] 800d3ba: 627b str r3, [r7, #36] @ 0x24 800d3bc: 6a7b ldr r3, [r7, #36] @ 0x24 800d3be: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800d3c2: 627b str r3, [r7, #36] @ 0x24 800d3c4: 6a7b ldr r3, [r7, #36] @ 0x24 800d3c6: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800d3ca: 627b str r3, [r7, #36] @ 0x24 800d3cc: 4a08 ldr r2, [pc, #32] @ (800d3f0 ) 800d3ce: 6a7b ldr r3, [r7, #36] @ 0x24 800d3d0: 6053 str r3, [r2, #4] } 800d3d2: bf00 nop 800d3d4: 3728 adds r7, #40 @ 0x28 800d3d6: 46bd mov sp, r7 800d3d8: bd80 pop {r7, pc} 800d3da: bf00 nop 800d3dc: 40000400 .word 0x40000400 800d3e0: 40021000 .word 0x40021000 800d3e4: 40010800 .word 0x40010800 800d3e8: 40000800 .word 0x40000800 800d3ec: 40011400 .word 0x40011400 800d3f0: 40010000 .word 0x40010000 0800d3f4 : UART_HandleTypeDef huart2; UART_HandleTypeDef huart3; /* UART5 init function */ void MX_UART5_Init(void) { 800d3f4: b580 push {r7, lr} 800d3f6: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 800d3f8: 4b11 ldr r3, [pc, #68] @ (800d440 ) 800d3fa: 4a12 ldr r2, [pc, #72] @ (800d444 ) 800d3fc: 601a str r2, [r3, #0] huart5.Init.BaudRate = 9600; 800d3fe: 4b10 ldr r3, [pc, #64] @ (800d440 ) 800d400: f44f 5216 mov.w r2, #9600 @ 0x2580 800d404: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 800d406: 4b0e ldr r3, [pc, #56] @ (800d440 ) 800d408: 2200 movs r2, #0 800d40a: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 800d40c: 4b0c ldr r3, [pc, #48] @ (800d440 ) 800d40e: 2200 movs r2, #0 800d410: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 800d412: 4b0b ldr r3, [pc, #44] @ (800d440 ) 800d414: 2200 movs r2, #0 800d416: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 800d418: 4b09 ldr r3, [pc, #36] @ (800d440 ) 800d41a: 220c movs r2, #12 800d41c: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d41e: 4b08 ldr r3, [pc, #32] @ (800d440 ) 800d420: 2200 movs r2, #0 800d422: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 800d424: 4b06 ldr r3, [pc, #24] @ (800d440 ) 800d426: 2200 movs r2, #0 800d428: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 800d42a: 4805 ldr r0, [pc, #20] @ (800d440 ) 800d42c: f004 fc08 bl 8011c40 800d430: 4603 mov r3, r0 800d432: 2b00 cmp r3, #0 800d434: d001 beq.n 800d43a { Error_Handler(); 800d436: f7fd fadb bl 800a9f0 } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 800d43a: bf00 nop 800d43c: bd80 pop {r7, pc} 800d43e: bf00 nop 800d440: 20000f50 .word 0x20000f50 800d444: 40005000 .word 0x40005000 0800d448 : /* USART1 init function */ void MX_USART1_UART_Init(void) { 800d448: b580 push {r7, lr} 800d44a: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 800d44c: 4b11 ldr r3, [pc, #68] @ (800d494 ) 800d44e: 4a12 ldr r2, [pc, #72] @ (800d498 ) 800d450: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800d452: 4b10 ldr r3, [pc, #64] @ (800d494 ) 800d454: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800d458: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800d45a: 4b0e ldr r3, [pc, #56] @ (800d494 ) 800d45c: 2200 movs r2, #0 800d45e: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 800d460: 4b0c ldr r3, [pc, #48] @ (800d494 ) 800d462: 2200 movs r2, #0 800d464: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800d466: 4b0b ldr r3, [pc, #44] @ (800d494 ) 800d468: 2200 movs r2, #0 800d46a: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 800d46c: 4b09 ldr r3, [pc, #36] @ (800d494 ) 800d46e: 220c movs r2, #12 800d470: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d472: 4b08 ldr r3, [pc, #32] @ (800d494 ) 800d474: 2200 movs r2, #0 800d476: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800d478: 4b06 ldr r3, [pc, #24] @ (800d494 ) 800d47a: 2200 movs r2, #0 800d47c: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 800d47e: 4805 ldr r0, [pc, #20] @ (800d494 ) 800d480: f004 fbde bl 8011c40 800d484: 4603 mov r3, r0 800d486: 2b00 cmp r3, #0 800d488: d001 beq.n 800d48e { Error_Handler(); 800d48a: f7fd fab1 bl 800a9f0 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 800d48e: bf00 nop 800d490: bd80 pop {r7, pc} 800d492: bf00 nop 800d494: 20000f98 .word 0x20000f98 800d498: 40013800 .word 0x40013800 0800d49c : /* USART2 init function */ void MX_USART2_UART_Init(void) { 800d49c: b580 push {r7, lr} 800d49e: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 800d4a0: 4b11 ldr r3, [pc, #68] @ (800d4e8 ) 800d4a2: 4a12 ldr r2, [pc, #72] @ (800d4ec ) 800d4a4: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 800d4a6: 4b10 ldr r3, [pc, #64] @ (800d4e8 ) 800d4a8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800d4ac: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 800d4ae: 4b0e ldr r3, [pc, #56] @ (800d4e8 ) 800d4b0: 2200 movs r2, #0 800d4b2: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 800d4b4: 4b0c ldr r3, [pc, #48] @ (800d4e8 ) 800d4b6: 2200 movs r2, #0 800d4b8: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800d4ba: 4b0b ldr r3, [pc, #44] @ (800d4e8 ) 800d4bc: 2200 movs r2, #0 800d4be: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 800d4c0: 4b09 ldr r3, [pc, #36] @ (800d4e8 ) 800d4c2: 220c movs r2, #12 800d4c4: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d4c6: 4b08 ldr r3, [pc, #32] @ (800d4e8 ) 800d4c8: 2200 movs r2, #0 800d4ca: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 800d4cc: 4b06 ldr r3, [pc, #24] @ (800d4e8 ) 800d4ce: 2200 movs r2, #0 800d4d0: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 800d4d2: 4805 ldr r0, [pc, #20] @ (800d4e8 ) 800d4d4: f004 fbb4 bl 8011c40 800d4d8: 4603 mov r3, r0 800d4da: 2b00 cmp r3, #0 800d4dc: d001 beq.n 800d4e2 { Error_Handler(); 800d4de: f7fd fa87 bl 800a9f0 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 800d4e2: bf00 nop 800d4e4: bd80 pop {r7, pc} 800d4e6: bf00 nop 800d4e8: 20000fe0 .word 0x20000fe0 800d4ec: 40004400 .word 0x40004400 0800d4f0 : /* USART3 init function */ void MX_USART3_UART_Init(void) { 800d4f0: b580 push {r7, lr} 800d4f2: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 800d4f4: 4b11 ldr r3, [pc, #68] @ (800d53c ) 800d4f6: 4a12 ldr r2, [pc, #72] @ (800d540 ) 800d4f8: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 800d4fa: 4b10 ldr r3, [pc, #64] @ (800d53c ) 800d4fc: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800d500: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 800d502: 4b0e ldr r3, [pc, #56] @ (800d53c ) 800d504: 2200 movs r2, #0 800d506: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 800d508: 4b0c ldr r3, [pc, #48] @ (800d53c ) 800d50a: 2200 movs r2, #0 800d50c: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 800d50e: 4b0b ldr r3, [pc, #44] @ (800d53c ) 800d510: 2200 movs r2, #0 800d512: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 800d514: 4b09 ldr r3, [pc, #36] @ (800d53c ) 800d516: 220c movs r2, #12 800d518: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d51a: 4b08 ldr r3, [pc, #32] @ (800d53c ) 800d51c: 2200 movs r2, #0 800d51e: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 800d520: 4b06 ldr r3, [pc, #24] @ (800d53c ) 800d522: 2200 movs r2, #0 800d524: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart3) != HAL_OK) 800d526: 4805 ldr r0, [pc, #20] @ (800d53c ) 800d528: f004 fb8a bl 8011c40 800d52c: 4603 mov r3, r0 800d52e: 2b00 cmp r3, #0 800d530: d001 beq.n 800d536 { Error_Handler(); 800d532: f7fd fa5d bl 800a9f0 } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 800d536: bf00 nop 800d538: bd80 pop {r7, pc} 800d53a: bf00 nop 800d53c: 20001028 .word 0x20001028 800d540: 40004800 .word 0x40004800 0800d544 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 800d544: b580 push {r7, lr} 800d546: b092 sub sp, #72 @ 0x48 800d548: af00 add r7, sp, #0 800d54a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800d54c: f107 0330 add.w r3, r7, #48 @ 0x30 800d550: 2200 movs r2, #0 800d552: 601a str r2, [r3, #0] 800d554: 605a str r2, [r3, #4] 800d556: 609a str r2, [r3, #8] 800d558: 60da str r2, [r3, #12] if(uartHandle->Instance==UART5) 800d55a: 687b ldr r3, [r7, #4] 800d55c: 681b ldr r3, [r3, #0] 800d55e: 4a95 ldr r2, [pc, #596] @ (800d7b4 ) 800d560: 4293 cmp r3, r2 800d562: d145 bne.n 800d5f0 { /* USER CODE BEGIN UART5_MspInit 0 */ /* USER CODE END UART5_MspInit 0 */ /* UART5 clock enable */ __HAL_RCC_UART5_CLK_ENABLE(); 800d564: 4b94 ldr r3, [pc, #592] @ (800d7b8 ) 800d566: 69db ldr r3, [r3, #28] 800d568: 4a93 ldr r2, [pc, #588] @ (800d7b8 ) 800d56a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800d56e: 61d3 str r3, [r2, #28] 800d570: 4b91 ldr r3, [pc, #580] @ (800d7b8 ) 800d572: 69db ldr r3, [r3, #28] 800d574: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800d578: 62fb str r3, [r7, #44] @ 0x2c 800d57a: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 800d57c: 4b8e ldr r3, [pc, #568] @ (800d7b8 ) 800d57e: 699b ldr r3, [r3, #24] 800d580: 4a8d ldr r2, [pc, #564] @ (800d7b8 ) 800d582: f043 0310 orr.w r3, r3, #16 800d586: 6193 str r3, [r2, #24] 800d588: 4b8b ldr r3, [pc, #556] @ (800d7b8 ) 800d58a: 699b ldr r3, [r3, #24] 800d58c: f003 0310 and.w r3, r3, #16 800d590: 62bb str r3, [r7, #40] @ 0x28 800d592: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOD_CLK_ENABLE(); 800d594: 4b88 ldr r3, [pc, #544] @ (800d7b8 ) 800d596: 699b ldr r3, [r3, #24] 800d598: 4a87 ldr r2, [pc, #540] @ (800d7b8 ) 800d59a: f043 0320 orr.w r3, r3, #32 800d59e: 6193 str r3, [r2, #24] 800d5a0: 4b85 ldr r3, [pc, #532] @ (800d7b8 ) 800d5a2: 699b ldr r3, [r3, #24] 800d5a4: f003 0320 and.w r3, r3, #32 800d5a8: 627b str r3, [r7, #36] @ 0x24 800d5aa: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART5 GPIO Configuration PC12 ------> UART5_TX PD2 ------> UART5_RX */ GPIO_InitStruct.Pin = GPIO_PIN_12; 800d5ac: f44f 5380 mov.w r3, #4096 @ 0x1000 800d5b0: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d5b2: 2302 movs r3, #2 800d5b4: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800d5b6: 2303 movs r3, #3 800d5b8: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800d5ba: f107 0330 add.w r3, r7, #48 @ 0x30 800d5be: 4619 mov r1, r3 800d5c0: 487e ldr r0, [pc, #504] @ (800d7bc ) 800d5c2: f001 fffd bl 800f5c0 GPIO_InitStruct.Pin = GPIO_PIN_2; 800d5c6: 2304 movs r3, #4 800d5c8: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800d5ca: 2300 movs r3, #0 800d5cc: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800d5ce: 2300 movs r3, #0 800d5d0: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d5d2: f107 0330 add.w r3, r7, #48 @ 0x30 800d5d6: 4619 mov r1, r3 800d5d8: 4879 ldr r0, [pc, #484] @ (800d7c0 ) 800d5da: f001 fff1 bl 800f5c0 /* UART5 interrupt Init */ HAL_NVIC_SetPriority(UART5_IRQn, 0, 0); 800d5de: 2200 movs r2, #0 800d5e0: 2100 movs r1, #0 800d5e2: 2035 movs r0, #53 @ 0x35 800d5e4: f001 fe57 bl 800f296 HAL_NVIC_EnableIRQ(UART5_IRQn); 800d5e8: 2035 movs r0, #53 @ 0x35 800d5ea: f001 fe70 bl 800f2ce HAL_NVIC_EnableIRQ(USART3_IRQn); /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 800d5ee: e0dc b.n 800d7aa else if(uartHandle->Instance==USART1) 800d5f0: 687b ldr r3, [r7, #4] 800d5f2: 681b ldr r3, [r3, #0] 800d5f4: 4a73 ldr r2, [pc, #460] @ (800d7c4 ) 800d5f6: 4293 cmp r3, r2 800d5f8: d13a bne.n 800d670 __HAL_RCC_USART1_CLK_ENABLE(); 800d5fa: 4b6f ldr r3, [pc, #444] @ (800d7b8 ) 800d5fc: 699b ldr r3, [r3, #24] 800d5fe: 4a6e ldr r2, [pc, #440] @ (800d7b8 ) 800d600: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800d604: 6193 str r3, [r2, #24] 800d606: 4b6c ldr r3, [pc, #432] @ (800d7b8 ) 800d608: 699b ldr r3, [r3, #24] 800d60a: f403 4380 and.w r3, r3, #16384 @ 0x4000 800d60e: 623b str r3, [r7, #32] 800d610: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 800d612: 4b69 ldr r3, [pc, #420] @ (800d7b8 ) 800d614: 699b ldr r3, [r3, #24] 800d616: 4a68 ldr r2, [pc, #416] @ (800d7b8 ) 800d618: f043 0304 orr.w r3, r3, #4 800d61c: 6193 str r3, [r2, #24] 800d61e: 4b66 ldr r3, [pc, #408] @ (800d7b8 ) 800d620: 699b ldr r3, [r3, #24] 800d622: f003 0304 and.w r3, r3, #4 800d626: 61fb str r3, [r7, #28] 800d628: 69fb ldr r3, [r7, #28] GPIO_InitStruct.Pin = GPIO_PIN_9; 800d62a: f44f 7300 mov.w r3, #512 @ 0x200 800d62e: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d630: 2302 movs r3, #2 800d632: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800d634: 2303 movs r3, #3 800d636: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800d638: f107 0330 add.w r3, r7, #48 @ 0x30 800d63c: 4619 mov r1, r3 800d63e: 4862 ldr r0, [pc, #392] @ (800d7c8 ) 800d640: f001 ffbe bl 800f5c0 GPIO_InitStruct.Pin = GPIO_PIN_10; 800d644: f44f 6380 mov.w r3, #1024 @ 0x400 800d648: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800d64a: 2300 movs r3, #0 800d64c: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800d64e: 2300 movs r3, #0 800d650: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800d652: f107 0330 add.w r3, r7, #48 @ 0x30 800d656: 4619 mov r1, r3 800d658: 485b ldr r0, [pc, #364] @ (800d7c8 ) 800d65a: f001 ffb1 bl 800f5c0 HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 800d65e: 2200 movs r2, #0 800d660: 2100 movs r1, #0 800d662: 2025 movs r0, #37 @ 0x25 800d664: f001 fe17 bl 800f296 HAL_NVIC_EnableIRQ(USART1_IRQn); 800d668: 2025 movs r0, #37 @ 0x25 800d66a: f001 fe30 bl 800f2ce } 800d66e: e09c b.n 800d7aa else if(uartHandle->Instance==USART2) 800d670: 687b ldr r3, [r7, #4] 800d672: 681b ldr r3, [r3, #0] 800d674: 4a55 ldr r2, [pc, #340] @ (800d7cc ) 800d676: 4293 cmp r3, r2 800d678: d146 bne.n 800d708 __HAL_RCC_USART2_CLK_ENABLE(); 800d67a: 4b4f ldr r3, [pc, #316] @ (800d7b8 ) 800d67c: 69db ldr r3, [r3, #28] 800d67e: 4a4e ldr r2, [pc, #312] @ (800d7b8 ) 800d680: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d684: 61d3 str r3, [r2, #28] 800d686: 4b4c ldr r3, [pc, #304] @ (800d7b8 ) 800d688: 69db ldr r3, [r3, #28] 800d68a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800d68e: 61bb str r3, [r7, #24] 800d690: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOD_CLK_ENABLE(); 800d692: 4b49 ldr r3, [pc, #292] @ (800d7b8 ) 800d694: 699b ldr r3, [r3, #24] 800d696: 4a48 ldr r2, [pc, #288] @ (800d7b8 ) 800d698: f043 0320 orr.w r3, r3, #32 800d69c: 6193 str r3, [r2, #24] 800d69e: 4b46 ldr r3, [pc, #280] @ (800d7b8 ) 800d6a0: 699b ldr r3, [r3, #24] 800d6a2: f003 0320 and.w r3, r3, #32 800d6a6: 617b str r3, [r7, #20] 800d6a8: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_5; 800d6aa: 2320 movs r3, #32 800d6ac: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d6ae: 2302 movs r3, #2 800d6b0: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800d6b2: 2303 movs r3, #3 800d6b4: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d6b6: f107 0330 add.w r3, r7, #48 @ 0x30 800d6ba: 4619 mov r1, r3 800d6bc: 4840 ldr r0, [pc, #256] @ (800d7c0 ) 800d6be: f001 ff7f bl 800f5c0 GPIO_InitStruct.Pin = GPIO_PIN_6; 800d6c2: 2340 movs r3, #64 @ 0x40 800d6c4: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800d6c6: 2300 movs r3, #0 800d6c8: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800d6ca: 2300 movs r3, #0 800d6cc: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d6ce: f107 0330 add.w r3, r7, #48 @ 0x30 800d6d2: 4619 mov r1, r3 800d6d4: 483a ldr r0, [pc, #232] @ (800d7c0 ) 800d6d6: f001 ff73 bl 800f5c0 __HAL_AFIO_REMAP_USART2_ENABLE(); 800d6da: 4b3d ldr r3, [pc, #244] @ (800d7d0 ) 800d6dc: 685b ldr r3, [r3, #4] 800d6de: 643b str r3, [r7, #64] @ 0x40 800d6e0: 6c3b ldr r3, [r7, #64] @ 0x40 800d6e2: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800d6e6: 643b str r3, [r7, #64] @ 0x40 800d6e8: 6c3b ldr r3, [r7, #64] @ 0x40 800d6ea: f043 0308 orr.w r3, r3, #8 800d6ee: 643b str r3, [r7, #64] @ 0x40 800d6f0: 4a37 ldr r2, [pc, #220] @ (800d7d0 ) 800d6f2: 6c3b ldr r3, [r7, #64] @ 0x40 800d6f4: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); 800d6f6: 2200 movs r2, #0 800d6f8: 2100 movs r1, #0 800d6fa: 2026 movs r0, #38 @ 0x26 800d6fc: f001 fdcb bl 800f296 HAL_NVIC_EnableIRQ(USART2_IRQn); 800d700: 2026 movs r0, #38 @ 0x26 800d702: f001 fde4 bl 800f2ce } 800d706: e050 b.n 800d7aa else if(uartHandle->Instance==USART3) 800d708: 687b ldr r3, [r7, #4] 800d70a: 681b ldr r3, [r3, #0] 800d70c: 4a31 ldr r2, [pc, #196] @ (800d7d4 ) 800d70e: 4293 cmp r3, r2 800d710: d14b bne.n 800d7aa __HAL_RCC_USART3_CLK_ENABLE(); 800d712: 4b29 ldr r3, [pc, #164] @ (800d7b8 ) 800d714: 69db ldr r3, [r3, #28] 800d716: 4a28 ldr r2, [pc, #160] @ (800d7b8 ) 800d718: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800d71c: 61d3 str r3, [r2, #28] 800d71e: 4b26 ldr r3, [pc, #152] @ (800d7b8 ) 800d720: 69db ldr r3, [r3, #28] 800d722: f403 2380 and.w r3, r3, #262144 @ 0x40000 800d726: 613b str r3, [r7, #16] 800d728: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 800d72a: 4b23 ldr r3, [pc, #140] @ (800d7b8 ) 800d72c: 699b ldr r3, [r3, #24] 800d72e: 4a22 ldr r2, [pc, #136] @ (800d7b8 ) 800d730: f043 0310 orr.w r3, r3, #16 800d734: 6193 str r3, [r2, #24] 800d736: 4b20 ldr r3, [pc, #128] @ (800d7b8 ) 800d738: 699b ldr r3, [r3, #24] 800d73a: f003 0310 and.w r3, r3, #16 800d73e: 60fb str r3, [r7, #12] 800d740: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_10; 800d742: f44f 6380 mov.w r3, #1024 @ 0x400 800d746: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d748: 2302 movs r3, #2 800d74a: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800d74c: 2303 movs r3, #3 800d74e: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800d750: f107 0330 add.w r3, r7, #48 @ 0x30 800d754: 4619 mov r1, r3 800d756: 4819 ldr r0, [pc, #100] @ (800d7bc ) 800d758: f001 ff32 bl 800f5c0 GPIO_InitStruct.Pin = GPIO_PIN_11; 800d75c: f44f 6300 mov.w r3, #2048 @ 0x800 800d760: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800d762: 2300 movs r3, #0 800d764: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800d766: 2300 movs r3, #0 800d768: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800d76a: f107 0330 add.w r3, r7, #48 @ 0x30 800d76e: 4619 mov r1, r3 800d770: 4812 ldr r0, [pc, #72] @ (800d7bc ) 800d772: f001 ff25 bl 800f5c0 __HAL_AFIO_REMAP_USART3_PARTIAL(); 800d776: 4b16 ldr r3, [pc, #88] @ (800d7d0 ) 800d778: 685b ldr r3, [r3, #4] 800d77a: 647b str r3, [r7, #68] @ 0x44 800d77c: 6c7b ldr r3, [r7, #68] @ 0x44 800d77e: f023 0330 bic.w r3, r3, #48 @ 0x30 800d782: 647b str r3, [r7, #68] @ 0x44 800d784: 6c7b ldr r3, [r7, #68] @ 0x44 800d786: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800d78a: 647b str r3, [r7, #68] @ 0x44 800d78c: 6c7b ldr r3, [r7, #68] @ 0x44 800d78e: f043 0310 orr.w r3, r3, #16 800d792: 647b str r3, [r7, #68] @ 0x44 800d794: 4a0e ldr r2, [pc, #56] @ (800d7d0 ) 800d796: 6c7b ldr r3, [r7, #68] @ 0x44 800d798: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); 800d79a: 2200 movs r2, #0 800d79c: 2100 movs r1, #0 800d79e: 2027 movs r0, #39 @ 0x27 800d7a0: f001 fd79 bl 800f296 HAL_NVIC_EnableIRQ(USART3_IRQn); 800d7a4: 2027 movs r0, #39 @ 0x27 800d7a6: f001 fd92 bl 800f2ce } 800d7aa: bf00 nop 800d7ac: 3748 adds r7, #72 @ 0x48 800d7ae: 46bd mov sp, r7 800d7b0: bd80 pop {r7, pc} 800d7b2: bf00 nop 800d7b4: 40005000 .word 0x40005000 800d7b8: 40021000 .word 0x40021000 800d7bc: 40011000 .word 0x40011000 800d7c0: 40011400 .word 0x40011400 800d7c4: 40013800 .word 0x40013800 800d7c8: 40010800 .word 0x40010800 800d7cc: 40004400 .word 0x40004400 800d7d0: 40010000 .word 0x40010000 800d7d4: 40004800 .word 0x40004800 0800d7d8 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 800d7d8: f7ff fc64 bl 800d0a4 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 800d7dc: 480b ldr r0, [pc, #44] @ (800d80c ) ldr r1, =_edata 800d7de: 490c ldr r1, [pc, #48] @ (800d810 ) ldr r2, =_sidata 800d7e0: 4a0c ldr r2, [pc, #48] @ (800d814 ) movs r3, #0 800d7e2: 2300 movs r3, #0 b LoopCopyDataInit 800d7e4: e002 b.n 800d7ec 0800d7e6 : CopyDataInit: ldr r4, [r2, r3] 800d7e6: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800d7e8: 50c4 str r4, [r0, r3] adds r3, r3, #4 800d7ea: 3304 adds r3, #4 0800d7ec : LoopCopyDataInit: adds r4, r0, r3 800d7ec: 18c4 adds r4, r0, r3 cmp r4, r1 800d7ee: 428c cmp r4, r1 bcc CopyDataInit 800d7f0: d3f9 bcc.n 800d7e6 /* Zero fill the bss segment. */ ldr r2, =_sbss 800d7f2: 4a09 ldr r2, [pc, #36] @ (800d818 ) ldr r4, =_ebss 800d7f4: 4c09 ldr r4, [pc, #36] @ (800d81c ) movs r3, #0 800d7f6: 2300 movs r3, #0 b LoopFillZerobss 800d7f8: e001 b.n 800d7fe 0800d7fa : FillZerobss: str r3, [r2] 800d7fa: 6013 str r3, [r2, #0] adds r2, r2, #4 800d7fc: 3204 adds r2, #4 0800d7fe : LoopFillZerobss: cmp r2, r4 800d7fe: 42a2 cmp r2, r4 bcc FillZerobss 800d800: d3fb bcc.n 800d7fa /* Call static constructors */ bl __libc_init_array 800d802: f005 fc2d bl 8013060 <__libc_init_array> /* Call the application's entry point.*/ bl main 800d806: f7fd f807 bl 800a818
bx lr 800d80a: 4770 bx lr ldr r0, =_sdata 800d80c: 20000000 .word 0x20000000 ldr r1, =_edata 800d810: 200000d4 .word 0x200000d4 ldr r2, =_sidata 800d814: 08014438 .word 0x08014438 ldr r2, =_sbss 800d818: 200000d8 .word 0x200000d8 ldr r4, =_ebss 800d81c: 200011c0 .word 0x200011c0 0800d820 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 800d820: e7fe b.n 800d820 ... 0800d824 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800d824: b580 push {r7, lr} 800d826: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 800d828: 4b08 ldr r3, [pc, #32] @ (800d84c ) 800d82a: 681b ldr r3, [r3, #0] 800d82c: 4a07 ldr r2, [pc, #28] @ (800d84c ) 800d82e: f043 0310 orr.w r3, r3, #16 800d832: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800d834: 2003 movs r0, #3 800d836: f001 fd23 bl 800f280 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800d83a: 200f movs r0, #15 800d83c: f000 f808 bl 800d850 /* Init the low level hardware */ HAL_MspInit(); 800d840: f7ff fafe bl 800ce40 /* Return function status */ return HAL_OK; 800d844: 2300 movs r3, #0 } 800d846: 4618 mov r0, r3 800d848: bd80 pop {r7, pc} 800d84a: bf00 nop 800d84c: 40022000 .word 0x40022000 0800d850 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800d850: b580 push {r7, lr} 800d852: b082 sub sp, #8 800d854: af00 add r7, sp, #0 800d856: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 800d858: 4b12 ldr r3, [pc, #72] @ (800d8a4 ) 800d85a: 681a ldr r2, [r3, #0] 800d85c: 4b12 ldr r3, [pc, #72] @ (800d8a8 ) 800d85e: 781b ldrb r3, [r3, #0] 800d860: 4619 mov r1, r3 800d862: f44f 737a mov.w r3, #1000 @ 0x3e8 800d866: fbb3 f3f1 udiv r3, r3, r1 800d86a: fbb2 f3f3 udiv r3, r2, r3 800d86e: 4618 mov r0, r3 800d870: f001 fd3b bl 800f2ea 800d874: 4603 mov r3, r0 800d876: 2b00 cmp r3, #0 800d878: d001 beq.n 800d87e { return HAL_ERROR; 800d87a: 2301 movs r3, #1 800d87c: e00e b.n 800d89c } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800d87e: 687b ldr r3, [r7, #4] 800d880: 2b0f cmp r3, #15 800d882: d80a bhi.n 800d89a { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800d884: 2200 movs r2, #0 800d886: 6879 ldr r1, [r7, #4] 800d888: f04f 30ff mov.w r0, #4294967295 800d88c: f001 fd03 bl 800f296 uwTickPrio = TickPriority; 800d890: 4a06 ldr r2, [pc, #24] @ (800d8ac ) 800d892: 687b ldr r3, [r7, #4] 800d894: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800d896: 2300 movs r3, #0 800d898: e000 b.n 800d89c return HAL_ERROR; 800d89a: 2301 movs r3, #1 } 800d89c: 4618 mov r0, r3 800d89e: 3708 adds r7, #8 800d8a0: 46bd mov sp, r7 800d8a2: bd80 pop {r7, pc} 800d8a4: 2000006c .word 0x2000006c 800d8a8: 20000074 .word 0x20000074 800d8ac: 20000070 .word 0x20000070 0800d8b0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800d8b0: b480 push {r7} 800d8b2: af00 add r7, sp, #0 uwTick += uwTickFreq; 800d8b4: 4b05 ldr r3, [pc, #20] @ (800d8cc ) 800d8b6: 781b ldrb r3, [r3, #0] 800d8b8: 461a mov r2, r3 800d8ba: 4b05 ldr r3, [pc, #20] @ (800d8d0 ) 800d8bc: 681b ldr r3, [r3, #0] 800d8be: 4413 add r3, r2 800d8c0: 4a03 ldr r2, [pc, #12] @ (800d8d0 ) 800d8c2: 6013 str r3, [r2, #0] } 800d8c4: bf00 nop 800d8c6: 46bd mov sp, r7 800d8c8: bc80 pop {r7} 800d8ca: 4770 bx lr 800d8cc: 20000074 .word 0x20000074 800d8d0: 20001070 .word 0x20001070 0800d8d4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 800d8d4: b480 push {r7} 800d8d6: af00 add r7, sp, #0 return uwTick; 800d8d8: 4b02 ldr r3, [pc, #8] @ (800d8e4 ) 800d8da: 681b ldr r3, [r3, #0] } 800d8dc: 4618 mov r0, r3 800d8de: 46bd mov sp, r7 800d8e0: bc80 pop {r7} 800d8e2: 4770 bx lr 800d8e4: 20001070 .word 0x20001070 0800d8e8 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 800d8e8: b580 push {r7, lr} 800d8ea: b084 sub sp, #16 800d8ec: af00 add r7, sp, #0 800d8ee: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800d8f0: f7ff fff0 bl 800d8d4 800d8f4: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800d8f6: 687b ldr r3, [r7, #4] 800d8f8: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800d8fa: 68fb ldr r3, [r7, #12] 800d8fc: f1b3 3fff cmp.w r3, #4294967295 800d900: d005 beq.n 800d90e { wait += (uint32_t)(uwTickFreq); 800d902: 4b0a ldr r3, [pc, #40] @ (800d92c ) 800d904: 781b ldrb r3, [r3, #0] 800d906: 461a mov r2, r3 800d908: 68fb ldr r3, [r7, #12] 800d90a: 4413 add r3, r2 800d90c: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 800d90e: bf00 nop 800d910: f7ff ffe0 bl 800d8d4 800d914: 4602 mov r2, r0 800d916: 68bb ldr r3, [r7, #8] 800d918: 1ad3 subs r3, r2, r3 800d91a: 68fa ldr r2, [r7, #12] 800d91c: 429a cmp r2, r3 800d91e: d8f7 bhi.n 800d910 { } } 800d920: bf00 nop 800d922: bf00 nop 800d924: 3710 adds r7, #16 800d926: 46bd mov sp, r7 800d928: bd80 pop {r7, pc} 800d92a: bf00 nop 800d92c: 20000074 .word 0x20000074 0800d930 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 800d930: b580 push {r7, lr} 800d932: b086 sub sp, #24 800d934: af00 add r7, sp, #0 800d936: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800d938: 2300 movs r3, #0 800d93a: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 800d93c: 2300 movs r3, #0 800d93e: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 800d940: 2300 movs r3, #0 800d942: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 800d944: 2300 movs r3, #0 800d946: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 800d948: 687b ldr r3, [r7, #4] 800d94a: 2b00 cmp r3, #0 800d94c: d101 bne.n 800d952 { return HAL_ERROR; 800d94e: 2301 movs r3, #1 800d950: e0be b.n 800dad0 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 800d952: 687b ldr r3, [r7, #4] 800d954: 689b ldr r3, [r3, #8] 800d956: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 800d958: 687b ldr r3, [r7, #4] 800d95a: 6a9b ldr r3, [r3, #40] @ 0x28 800d95c: 2b00 cmp r3, #0 800d95e: d109 bne.n 800d974 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 800d960: 687b ldr r3, [r7, #4] 800d962: 2200 movs r2, #0 800d964: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 800d966: 687b ldr r3, [r7, #4] 800d968: 2200 movs r2, #0 800d96a: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800d96e: 6878 ldr r0, [r7, #4] 800d970: f7fb fd4a bl 8009408 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800d974: 6878 ldr r0, [r7, #4] 800d976: f000 fbf1 bl 800e15c 800d97a: 4603 mov r3, r0 800d97c: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 800d97e: 687b ldr r3, [r7, #4] 800d980: 6a9b ldr r3, [r3, #40] @ 0x28 800d982: f003 0310 and.w r3, r3, #16 800d986: 2b00 cmp r3, #0 800d988: f040 8099 bne.w 800dabe 800d98c: 7dfb ldrb r3, [r7, #23] 800d98e: 2b00 cmp r3, #0 800d990: f040 8095 bne.w 800dabe (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800d994: 687b ldr r3, [r7, #4] 800d996: 6a9b ldr r3, [r3, #40] @ 0x28 800d998: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800d99c: f023 0302 bic.w r3, r3, #2 800d9a0: f043 0202 orr.w r2, r3, #2 800d9a4: 687b ldr r3, [r7, #4] 800d9a6: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 800d9a8: 687b ldr r3, [r7, #4] 800d9aa: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800d9ac: 687b ldr r3, [r7, #4] 800d9ae: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 800d9b0: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 800d9b2: 687b ldr r3, [r7, #4] 800d9b4: 7b1b ldrb r3, [r3, #12] 800d9b6: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800d9b8: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 800d9ba: 68ba ldr r2, [r7, #8] 800d9bc: 4313 orrs r3, r2 800d9be: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 800d9c0: 687b ldr r3, [r7, #4] 800d9c2: 689b ldr r3, [r3, #8] 800d9c4: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d9c8: d003 beq.n 800d9d2 800d9ca: 687b ldr r3, [r7, #4] 800d9cc: 689b ldr r3, [r3, #8] 800d9ce: 2b01 cmp r3, #1 800d9d0: d102 bne.n 800d9d8 800d9d2: f44f 7380 mov.w r3, #256 @ 0x100 800d9d6: e000 b.n 800d9da 800d9d8: 2300 movs r3, #0 800d9da: 693a ldr r2, [r7, #16] 800d9dc: 4313 orrs r3, r2 800d9de: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 800d9e0: 687b ldr r3, [r7, #4] 800d9e2: 7d1b ldrb r3, [r3, #20] 800d9e4: 2b01 cmp r3, #1 800d9e6: d119 bne.n 800da1c { if (hadc->Init.ContinuousConvMode == DISABLE) 800d9e8: 687b ldr r3, [r7, #4] 800d9ea: 7b1b ldrb r3, [r3, #12] 800d9ec: 2b00 cmp r3, #0 800d9ee: d109 bne.n 800da04 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 800d9f0: 687b ldr r3, [r7, #4] 800d9f2: 699b ldr r3, [r3, #24] 800d9f4: 3b01 subs r3, #1 800d9f6: 035a lsls r2, r3, #13 800d9f8: 693b ldr r3, [r7, #16] 800d9fa: 4313 orrs r3, r2 800d9fc: f443 6300 orr.w r3, r3, #2048 @ 0x800 800da00: 613b str r3, [r7, #16] 800da02: e00b b.n 800da1c { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800da04: 687b ldr r3, [r7, #4] 800da06: 6a9b ldr r3, [r3, #40] @ 0x28 800da08: f043 0220 orr.w r2, r3, #32 800da0c: 687b ldr r3, [r7, #4] 800da0e: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800da10: 687b ldr r3, [r7, #4] 800da12: 6adb ldr r3, [r3, #44] @ 0x2c 800da14: f043 0201 orr.w r2, r3, #1 800da18: 687b ldr r3, [r7, #4] 800da1a: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 800da1c: 687b ldr r3, [r7, #4] 800da1e: 681b ldr r3, [r3, #0] 800da20: 685b ldr r3, [r3, #4] 800da22: f423 4169 bic.w r1, r3, #59648 @ 0xe900 800da26: 687b ldr r3, [r7, #4] 800da28: 681b ldr r3, [r3, #0] 800da2a: 693a ldr r2, [r7, #16] 800da2c: 430a orrs r2, r1 800da2e: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 800da30: 687b ldr r3, [r7, #4] 800da32: 681b ldr r3, [r3, #0] 800da34: 689a ldr r2, [r3, #8] 800da36: 4b28 ldr r3, [pc, #160] @ (800dad8 ) 800da38: 4013 ands r3, r2 800da3a: 687a ldr r2, [r7, #4] 800da3c: 6812 ldr r2, [r2, #0] 800da3e: 68b9 ldr r1, [r7, #8] 800da40: 430b orrs r3, r1 800da42: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 800da44: 687b ldr r3, [r7, #4] 800da46: 689b ldr r3, [r3, #8] 800da48: f5b3 7f80 cmp.w r3, #256 @ 0x100 800da4c: d003 beq.n 800da56 800da4e: 687b ldr r3, [r7, #4] 800da50: 689b ldr r3, [r3, #8] 800da52: 2b01 cmp r3, #1 800da54: d104 bne.n 800da60 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 800da56: 687b ldr r3, [r7, #4] 800da58: 691b ldr r3, [r3, #16] 800da5a: 3b01 subs r3, #1 800da5c: 051b lsls r3, r3, #20 800da5e: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 800da60: 687b ldr r3, [r7, #4] 800da62: 681b ldr r3, [r3, #0] 800da64: 6adb ldr r3, [r3, #44] @ 0x2c 800da66: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 800da6a: 687b ldr r3, [r7, #4] 800da6c: 681b ldr r3, [r3, #0] 800da6e: 68fa ldr r2, [r7, #12] 800da70: 430a orrs r2, r1 800da72: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800da74: 687b ldr r3, [r7, #4] 800da76: 681b ldr r3, [r3, #0] 800da78: 689a ldr r2, [r3, #8] 800da7a: 4b18 ldr r3, [pc, #96] @ (800dadc ) 800da7c: 4013 ands r3, r2 800da7e: 68ba ldr r2, [r7, #8] 800da80: 429a cmp r2, r3 800da82: d10b bne.n 800da9c ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 800da84: 687b ldr r3, [r7, #4] 800da86: 2200 movs r2, #0 800da88: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 800da8a: 687b ldr r3, [r7, #4] 800da8c: 6a9b ldr r3, [r3, #40] @ 0x28 800da8e: f023 0303 bic.w r3, r3, #3 800da92: f043 0201 orr.w r2, r3, #1 800da96: 687b ldr r3, [r7, #4] 800da98: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800da9a: e018 b.n 800dace HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800da9c: 687b ldr r3, [r7, #4] 800da9e: 6a9b ldr r3, [r3, #40] @ 0x28 800daa0: f023 0312 bic.w r3, r3, #18 800daa4: f043 0210 orr.w r2, r3, #16 800daa8: 687b ldr r3, [r7, #4] 800daaa: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800daac: 687b ldr r3, [r7, #4] 800daae: 6adb ldr r3, [r3, #44] @ 0x2c 800dab0: f043 0201 orr.w r2, r3, #1 800dab4: 687b ldr r3, [r7, #4] 800dab6: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 800dab8: 2301 movs r3, #1 800daba: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800dabc: e007 b.n 800dace } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800dabe: 687b ldr r3, [r7, #4] 800dac0: 6a9b ldr r3, [r3, #40] @ 0x28 800dac2: f043 0210 orr.w r2, r3, #16 800dac6: 687b ldr r3, [r7, #4] 800dac8: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800daca: 2301 movs r3, #1 800dacc: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800dace: 7dfb ldrb r3, [r7, #23] } 800dad0: 4618 mov r0, r3 800dad2: 3718 adds r7, #24 800dad4: 46bd mov sp, r7 800dad6: bd80 pop {r7, pc} 800dad8: ffe1f7fd .word 0xffe1f7fd 800dadc: ff1f0efe .word 0xff1f0efe 0800dae0 : * Interruptions enabled in this function: None. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { 800dae0: b580 push {r7, lr} 800dae2: b084 sub sp, #16 800dae4: af00 add r7, sp, #0 800dae6: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800dae8: 2300 movs r3, #0 800daea: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800daec: 687b ldr r3, [r7, #4] 800daee: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800daf2: 2b01 cmp r3, #1 800daf4: d101 bne.n 800dafa 800daf6: 2302 movs r3, #2 800daf8: e098 b.n 800dc2c 800dafa: 687b ldr r3, [r7, #4] 800dafc: 2201 movs r2, #1 800dafe: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 800db02: 6878 ldr r0, [r7, #4] 800db04: f000 fad0 bl 800e0a8 800db08: 4603 mov r3, r0 800db0a: 73fb strb r3, [r7, #15] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800db0c: 7bfb ldrb r3, [r7, #15] 800db0e: 2b00 cmp r3, #0 800db10: f040 8087 bne.w 800dc22 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 800db14: 687b ldr r3, [r7, #4] 800db16: 6a9b ldr r3, [r3, #40] @ 0x28 800db18: f423 7340 bic.w r3, r3, #768 @ 0x300 800db1c: f023 0301 bic.w r3, r3, #1 800db20: f443 7280 orr.w r2, r3, #256 @ 0x100 800db24: 687b ldr r3, [r7, #4] 800db26: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 800db28: 687b ldr r3, [r7, #4] 800db2a: 681b ldr r3, [r3, #0] 800db2c: 4a41 ldr r2, [pc, #260] @ (800dc34 ) 800db2e: 4293 cmp r3, r2 800db30: d105 bne.n 800db3e 800db32: 4b41 ldr r3, [pc, #260] @ (800dc38 ) 800db34: 685b ldr r3, [r3, #4] 800db36: f403 2370 and.w r3, r3, #983040 @ 0xf0000 800db3a: 2b00 cmp r3, #0 800db3c: d115 bne.n 800db6a { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800db3e: 687b ldr r3, [r7, #4] 800db40: 6a9b ldr r3, [r3, #40] @ 0x28 800db42: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 800db46: 687b ldr r3, [r7, #4] 800db48: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800db4a: 687b ldr r3, [r7, #4] 800db4c: 681b ldr r3, [r3, #0] 800db4e: 685b ldr r3, [r3, #4] 800db50: f403 6380 and.w r3, r3, #1024 @ 0x400 800db54: 2b00 cmp r3, #0 800db56: d026 beq.n 800dba6 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800db58: 687b ldr r3, [r7, #4] 800db5a: 6a9b ldr r3, [r3, #40] @ 0x28 800db5c: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800db60: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800db64: 687b ldr r3, [r7, #4] 800db66: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800db68: e01d b.n 800dba6 } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800db6a: 687b ldr r3, [r7, #4] 800db6c: 6a9b ldr r3, [r3, #40] @ 0x28 800db6e: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800db72: 687b ldr r3, [r7, #4] 800db74: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 800db76: 687b ldr r3, [r7, #4] 800db78: 681b ldr r3, [r3, #0] 800db7a: 4a2f ldr r2, [pc, #188] @ (800dc38 ) 800db7c: 4293 cmp r3, r2 800db7e: d004 beq.n 800db8a 800db80: 687b ldr r3, [r7, #4] 800db82: 681b ldr r3, [r3, #0] 800db84: 4a2b ldr r2, [pc, #172] @ (800dc34 ) 800db86: 4293 cmp r3, r2 800db88: d10d bne.n 800dba6 800db8a: 4b2b ldr r3, [pc, #172] @ (800dc38 ) 800db8c: 685b ldr r3, [r3, #4] 800db8e: f403 6380 and.w r3, r3, #1024 @ 0x400 800db92: 2b00 cmp r3, #0 800db94: d007 beq.n 800dba6 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800db96: 687b ldr r3, [r7, #4] 800db98: 6a9b ldr r3, [r3, #40] @ 0x28 800db9a: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800db9e: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800dba2: 687b ldr r3, [r7, #4] 800dba4: 629a str r2, [r3, #40] @ 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800dba6: 687b ldr r3, [r7, #4] 800dba8: 6a9b ldr r3, [r3, #40] @ 0x28 800dbaa: f403 5380 and.w r3, r3, #4096 @ 0x1000 800dbae: 2b00 cmp r3, #0 800dbb0: d006 beq.n 800dbc0 { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 800dbb2: 687b ldr r3, [r7, #4] 800dbb4: 6adb ldr r3, [r3, #44] @ 0x2c 800dbb6: f023 0206 bic.w r2, r3, #6 800dbba: 687b ldr r3, [r7, #4] 800dbbc: 62da str r2, [r3, #44] @ 0x2c 800dbbe: e002 b.n 800dbc6 } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 800dbc0: 687b ldr r3, [r7, #4] 800dbc2: 2200 movs r2, #0 800dbc4: 62da str r2, [r3, #44] @ 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 800dbc6: 687b ldr r3, [r7, #4] 800dbc8: 2200 movs r2, #0 800dbca: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Clear regular group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 800dbce: 687b ldr r3, [r7, #4] 800dbd0: 681b ldr r3, [r3, #0] 800dbd2: f06f 0202 mvn.w r2, #2 800dbd6: 601a str r2, [r3, #0] /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ /* If ADC is master, ADC is enabled and conversion is started. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800dbd8: 687b ldr r3, [r7, #4] 800dbda: 681b ldr r3, [r3, #0] 800dbdc: 689b ldr r3, [r3, #8] 800dbde: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800dbe2: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800dbe6: d113 bne.n 800dc10 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 800dbe8: 687b ldr r3, [r7, #4] 800dbea: 681b ldr r3, [r3, #0] if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800dbec: 4a11 ldr r2, [pc, #68] @ (800dc34 ) 800dbee: 4293 cmp r3, r2 800dbf0: d105 bne.n 800dbfe ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 800dbf2: 4b11 ldr r3, [pc, #68] @ (800dc38 ) 800dbf4: 685b ldr r3, [r3, #4] 800dbf6: f403 2370 and.w r3, r3, #983040 @ 0xf0000 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800dbfa: 2b00 cmp r3, #0 800dbfc: d108 bne.n 800dc10 { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 800dbfe: 687b ldr r3, [r7, #4] 800dc00: 681b ldr r3, [r3, #0] 800dc02: 689a ldr r2, [r3, #8] 800dc04: 687b ldr r3, [r7, #4] 800dc06: 681b ldr r3, [r3, #0] 800dc08: f442 02a0 orr.w r2, r2, #5242880 @ 0x500000 800dc0c: 609a str r2, [r3, #8] 800dc0e: e00c b.n 800dc2a } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 800dc10: 687b ldr r3, [r7, #4] 800dc12: 681b ldr r3, [r3, #0] 800dc14: 689a ldr r2, [r3, #8] 800dc16: 687b ldr r3, [r7, #4] 800dc18: 681b ldr r3, [r3, #0] 800dc1a: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 800dc1e: 609a str r2, [r3, #8] 800dc20: e003 b.n 800dc2a } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 800dc22: 687b ldr r3, [r7, #4] 800dc24: 2200 movs r2, #0 800dc26: f883 2024 strb.w r2, [r3, #36] @ 0x24 } /* Return function status */ return tmp_hal_status; 800dc2a: 7bfb ldrb r3, [r7, #15] } 800dc2c: 4618 mov r0, r3 800dc2e: 3710 adds r7, #16 800dc30: 46bd mov sp, r7 800dc32: bd80 pop {r7, pc} 800dc34: 40012800 .word 0x40012800 800dc38: 40012400 .word 0x40012400 0800dc3c : * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { 800dc3c: b580 push {r7, lr} 800dc3e: b084 sub sp, #16 800dc40: af00 add r7, sp, #0 800dc42: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800dc44: 2300 movs r3, #0 800dc46: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800dc48: 687b ldr r3, [r7, #4] 800dc4a: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800dc4e: 2b01 cmp r3, #1 800dc50: d101 bne.n 800dc56 800dc52: 2302 movs r3, #2 800dc54: e01a b.n 800dc8c 800dc56: 687b ldr r3, [r7, #4] 800dc58: 2201 movs r2, #1 800dc5a: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800dc5e: 6878 ldr r0, [r7, #4] 800dc60: f000 fa7c bl 800e15c 800dc64: 4603 mov r3, r0 800dc66: 73fb strb r3, [r7, #15] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 800dc68: 7bfb ldrb r3, [r7, #15] 800dc6a: 2b00 cmp r3, #0 800dc6c: d109 bne.n 800dc82 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800dc6e: 687b ldr r3, [r7, #4] 800dc70: 6a9b ldr r3, [r3, #40] @ 0x28 800dc72: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800dc76: f023 0301 bic.w r3, r3, #1 800dc7a: f043 0201 orr.w r2, r3, #1 800dc7e: 687b ldr r3, [r7, #4] 800dc80: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 800dc82: 687b ldr r3, [r7, #4] 800dc84: 2200 movs r2, #0 800dc86: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800dc8a: 7bfb ldrb r3, [r7, #15] } 800dc8c: 4618 mov r0, r3 800dc8e: 3710 adds r7, #16 800dc90: 46bd mov sp, r7 800dc92: bd80 pop {r7, pc} 0800dc94 : * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { 800dc94: b590 push {r4, r7, lr} 800dc96: b087 sub sp, #28 800dc98: af00 add r7, sp, #0 800dc9a: 6078 str r0, [r7, #4] 800dc9c: 6039 str r1, [r7, #0] uint32_t tickstart = 0U; 800dc9e: 2300 movs r3, #0 800dca0: 617b str r3, [r7, #20] /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; 800dca2: 2300 movs r3, #0 800dca4: 60fb str r3, [r7, #12] uint32_t Conversion_Timeout_CPU_cycles_max = 0U; 800dca6: 2300 movs r3, #0 800dca8: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Get tick count */ tickstart = HAL_GetTick(); 800dcaa: f7ff fe13 bl 800d8d4 800dcae: 6178 str r0, [r7, #20] /* Verification that ADC configuration is compliant with polling for */ /* each conversion: */ /* Particular case is ADC configured in DMA mode */ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) 800dcb0: 687b ldr r3, [r7, #4] 800dcb2: 681b ldr r3, [r3, #0] 800dcb4: 689b ldr r3, [r3, #8] 800dcb6: f403 7380 and.w r3, r3, #256 @ 0x100 800dcba: 2b00 cmp r3, #0 800dcbc: d00b beq.n 800dcd6 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800dcbe: 687b ldr r3, [r7, #4] 800dcc0: 6a9b ldr r3, [r3, #40] @ 0x28 800dcc2: f043 0220 orr.w r2, r3, #32 800dcc6: 687b ldr r3, [r7, #4] 800dcc8: 629a str r2, [r3, #40] @ 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 800dcca: 687b ldr r3, [r7, #4] 800dccc: 2200 movs r2, #0 800dcce: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800dcd2: 2301 movs r3, #1 800dcd4: e0d3 b.n 800de7e /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ /* As flag EOC is not set after each conversion, no timeout status can */ /* be set. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 800dcd6: 687b ldr r3, [r7, #4] 800dcd8: 681b ldr r3, [r3, #0] 800dcda: 685b ldr r3, [r3, #4] 800dcdc: f403 7380 and.w r3, r3, #256 @ 0x100 800dce0: 2b00 cmp r3, #0 800dce2: d131 bne.n 800dd48 HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ) 800dce4: 687b ldr r3, [r7, #4] 800dce6: 681b ldr r3, [r3, #0] 800dce8: 6adb ldr r3, [r3, #44] @ 0x2c 800dcea: f403 0370 and.w r3, r3, #15728640 @ 0xf00000 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 800dcee: 2b00 cmp r3, #0 800dcf0: d12a bne.n 800dd48 { /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 800dcf2: e021 b.n 800dd38 { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 800dcf4: 683b ldr r3, [r7, #0] 800dcf6: f1b3 3fff cmp.w r3, #4294967295 800dcfa: d01d beq.n 800dd38 { if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) 800dcfc: 683b ldr r3, [r7, #0] 800dcfe: 2b00 cmp r3, #0 800dd00: d007 beq.n 800dd12 800dd02: f7ff fde7 bl 800d8d4 800dd06: 4602 mov r2, r0 800dd08: 697b ldr r3, [r7, #20] 800dd0a: 1ad3 subs r3, r2, r3 800dd0c: 683a ldr r2, [r7, #0] 800dd0e: 429a cmp r2, r3 800dd10: d212 bcs.n 800dd38 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 800dd12: 687b ldr r3, [r7, #4] 800dd14: 681b ldr r3, [r3, #0] 800dd16: 681b ldr r3, [r3, #0] 800dd18: f003 0302 and.w r3, r3, #2 800dd1c: 2b00 cmp r3, #0 800dd1e: d10b bne.n 800dd38 { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 800dd20: 687b ldr r3, [r7, #4] 800dd22: 6a9b ldr r3, [r3, #40] @ 0x28 800dd24: f043 0204 orr.w r2, r3, #4 800dd28: 687b ldr r3, [r7, #4] 800dd2a: 629a str r2, [r3, #40] @ 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 800dd2c: 687b ldr r3, [r7, #4] 800dd2e: 2200 movs r2, #0 800dd30: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_TIMEOUT; 800dd34: 2303 movs r3, #3 800dd36: e0a2 b.n 800de7e while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 800dd38: 687b ldr r3, [r7, #4] 800dd3a: 681b ldr r3, [r3, #0] 800dd3c: 681b ldr r3, [r3, #0] 800dd3e: f003 0302 and.w r3, r3, #2 800dd42: 2b00 cmp r3, #0 800dd44: d0d6 beq.n 800dcf4 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 800dd46: e070 b.n 800de2a /* Replace polling by wait for maximum conversion time */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ /* and ADC maximum conversion cycles on all channels. */ /* - Wait for the expected ADC clock cycles delay */ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 800dd48: 4b4f ldr r3, [pc, #316] @ (800de88 ) 800dd4a: 681c ldr r4, [r3, #0] 800dd4c: 2002 movs r0, #2 800dd4e: f002 fd05 bl 801075c 800dd52: 4603 mov r3, r0 800dd54: fbb4 f2f3 udiv r2, r4, r3 * ADC_CONVCYCLES_MAX_RANGE(hadc) ); 800dd58: 687b ldr r3, [r7, #4] 800dd5a: 681b ldr r3, [r3, #0] 800dd5c: 6919 ldr r1, [r3, #16] 800dd5e: 4b4b ldr r3, [pc, #300] @ (800de8c ) 800dd60: 400b ands r3, r1 800dd62: 2b00 cmp r3, #0 800dd64: d118 bne.n 800dd98 800dd66: 687b ldr r3, [r7, #4] 800dd68: 681b ldr r3, [r3, #0] 800dd6a: 68d9 ldr r1, [r3, #12] 800dd6c: 4b48 ldr r3, [pc, #288] @ (800de90 ) 800dd6e: 400b ands r3, r1 800dd70: 2b00 cmp r3, #0 800dd72: d111 bne.n 800dd98 800dd74: 687b ldr r3, [r7, #4] 800dd76: 681b ldr r3, [r3, #0] 800dd78: 6919 ldr r1, [r3, #16] 800dd7a: 4b46 ldr r3, [pc, #280] @ (800de94 ) 800dd7c: 400b ands r3, r1 800dd7e: 2b00 cmp r3, #0 800dd80: d108 bne.n 800dd94 800dd82: 687b ldr r3, [r7, #4] 800dd84: 681b ldr r3, [r3, #0] 800dd86: 68d9 ldr r1, [r3, #12] 800dd88: 4b43 ldr r3, [pc, #268] @ (800de98 ) 800dd8a: 400b ands r3, r1 800dd8c: 2b00 cmp r3, #0 800dd8e: d101 bne.n 800dd94 800dd90: 2314 movs r3, #20 800dd92: e020 b.n 800ddd6 800dd94: 2329 movs r3, #41 @ 0x29 800dd96: e01e b.n 800ddd6 800dd98: 687b ldr r3, [r7, #4] 800dd9a: 681b ldr r3, [r3, #0] 800dd9c: 6919 ldr r1, [r3, #16] 800dd9e: 4b3d ldr r3, [pc, #244] @ (800de94 ) 800dda0: 400b ands r3, r1 800dda2: 2b00 cmp r3, #0 800dda4: d106 bne.n 800ddb4 800dda6: 687b ldr r3, [r7, #4] 800dda8: 681b ldr r3, [r3, #0] 800ddaa: 68d9 ldr r1, [r3, #12] 800ddac: 4b3a ldr r3, [pc, #232] @ (800de98 ) 800ddae: 400b ands r3, r1 800ddb0: 2b00 cmp r3, #0 800ddb2: d00d beq.n 800ddd0 800ddb4: 687b ldr r3, [r7, #4] 800ddb6: 681b ldr r3, [r3, #0] 800ddb8: 6919 ldr r1, [r3, #16] 800ddba: 4b38 ldr r3, [pc, #224] @ (800de9c ) 800ddbc: 400b ands r3, r1 800ddbe: 2b00 cmp r3, #0 800ddc0: d108 bne.n 800ddd4 800ddc2: 687b ldr r3, [r7, #4] 800ddc4: 681b ldr r3, [r3, #0] 800ddc6: 68d9 ldr r1, [r3, #12] 800ddc8: 4b34 ldr r3, [pc, #208] @ (800de9c ) 800ddca: 400b ands r3, r1 800ddcc: 2b00 cmp r3, #0 800ddce: d101 bne.n 800ddd4 800ddd0: 2354 movs r3, #84 @ 0x54 800ddd2: e000 b.n 800ddd6 800ddd4: 23fc movs r3, #252 @ 0xfc Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock 800ddd6: fb02 f303 mul.w r3, r2, r3 800ddda: 613b str r3, [r7, #16] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 800dddc: e021 b.n 800de22 { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 800ddde: 683b ldr r3, [r7, #0] 800dde0: f1b3 3fff cmp.w r3, #4294967295 800dde4: d01a beq.n 800de1c { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) 800dde6: 683b ldr r3, [r7, #0] 800dde8: 2b00 cmp r3, #0 800ddea: d007 beq.n 800ddfc 800ddec: f7ff fd72 bl 800d8d4 800ddf0: 4602 mov r2, r0 800ddf2: 697b ldr r3, [r7, #20] 800ddf4: 1ad3 subs r3, r2, r3 800ddf6: 683a ldr r2, [r7, #0] 800ddf8: 429a cmp r2, r3 800ddfa: d20f bcs.n 800de1c { /* New check to avoid false timeout detection in case of preemption */ if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 800ddfc: 68fb ldr r3, [r7, #12] 800ddfe: 693a ldr r2, [r7, #16] 800de00: 429a cmp r2, r3 800de02: d90b bls.n 800de1c { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 800de04: 687b ldr r3, [r7, #4] 800de06: 6a9b ldr r3, [r3, #40] @ 0x28 800de08: f043 0204 orr.w r2, r3, #4 800de0c: 687b ldr r3, [r7, #4] 800de0e: 629a str r2, [r3, #40] @ 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 800de10: 687b ldr r3, [r7, #4] 800de12: 2200 movs r2, #0 800de14: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_TIMEOUT; 800de18: 2303 movs r3, #3 800de1a: e030 b.n 800de7e } } } Conversion_Timeout_CPU_cycles ++; 800de1c: 68fb ldr r3, [r7, #12] 800de1e: 3301 adds r3, #1 800de20: 60fb str r3, [r7, #12] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 800de22: 68fb ldr r3, [r7, #12] 800de24: 693a ldr r2, [r7, #16] 800de26: 429a cmp r2, r3 800de28: d8d9 bhi.n 800ddde } } /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 800de2a: 687b ldr r3, [r7, #4] 800de2c: 681b ldr r3, [r3, #0] 800de2e: f06f 0212 mvn.w r2, #18 800de32: 601a str r2, [r3, #0] /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800de34: 687b ldr r3, [r7, #4] 800de36: 6a9b ldr r3, [r3, #40] @ 0x28 800de38: f443 7200 orr.w r2, r3, #512 @ 0x200 800de3c: 687b ldr r3, [r7, #4] 800de3e: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800de40: 687b ldr r3, [r7, #4] 800de42: 681b ldr r3, [r3, #0] 800de44: 689b ldr r3, [r3, #8] 800de46: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800de4a: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800de4e: d115 bne.n 800de7c (hadc->Init.ContinuousConvMode == DISABLE) ) 800de50: 687b ldr r3, [r7, #4] 800de52: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800de54: 2b00 cmp r3, #0 800de56: d111 bne.n 800de7c { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800de58: 687b ldr r3, [r7, #4] 800de5a: 6a9b ldr r3, [r3, #40] @ 0x28 800de5c: f423 7280 bic.w r2, r3, #256 @ 0x100 800de60: 687b ldr r3, [r7, #4] 800de62: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800de64: 687b ldr r3, [r7, #4] 800de66: 6a9b ldr r3, [r3, #40] @ 0x28 800de68: f403 5380 and.w r3, r3, #4096 @ 0x1000 800de6c: 2b00 cmp r3, #0 800de6e: d105 bne.n 800de7c { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800de70: 687b ldr r3, [r7, #4] 800de72: 6a9b ldr r3, [r3, #40] @ 0x28 800de74: f043 0201 orr.w r2, r3, #1 800de78: 687b ldr r3, [r7, #4] 800de7a: 629a str r2, [r3, #40] @ 0x28 } } /* Return ADC state */ return HAL_OK; 800de7c: 2300 movs r3, #0 } 800de7e: 4618 mov r0, r3 800de80: 371c adds r7, #28 800de82: 46bd mov sp, r7 800de84: bd90 pop {r4, r7, pc} 800de86: bf00 nop 800de88: 2000006c .word 0x2000006c 800de8c: 24924924 .word 0x24924924 800de90: 00924924 .word 0x00924924 800de94: 12492492 .word 0x12492492 800de98: 00492492 .word 0x00492492 800de9c: 00249249 .word 0x00249249 0800dea0 : * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc: ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { 800dea0: b480 push {r7} 800dea2: b083 sub sp, #12 800dea4: af00 add r7, sp, #0 800dea6: 6078 str r0, [r7, #4] /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; 800dea8: 687b ldr r3, [r7, #4] 800deaa: 681b ldr r3, [r3, #0] 800deac: 6cdb ldr r3, [r3, #76] @ 0x4c } 800deae: 4618 mov r0, r3 800deb0: 370c adds r7, #12 800deb2: 46bd mov sp, r7 800deb4: bc80 pop {r7} 800deb6: 4770 bx lr 0800deb8 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 800deb8: b480 push {r7} 800deba: b085 sub sp, #20 800debc: af00 add r7, sp, #0 800debe: 6078 str r0, [r7, #4] 800dec0: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800dec2: 2300 movs r3, #0 800dec4: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 800dec6: 2300 movs r3, #0 800dec8: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 800deca: 687b ldr r3, [r7, #4] 800decc: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800ded0: 2b01 cmp r3, #1 800ded2: d101 bne.n 800ded8 800ded4: 2302 movs r3, #2 800ded6: e0dc b.n 800e092 800ded8: 687b ldr r3, [r7, #4] 800deda: 2201 movs r2, #1 800dedc: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 800dee0: 683b ldr r3, [r7, #0] 800dee2: 685b ldr r3, [r3, #4] 800dee4: 2b06 cmp r3, #6 800dee6: d81c bhi.n 800df22 { MODIFY_REG(hadc->Instance->SQR3 , 800dee8: 687b ldr r3, [r7, #4] 800deea: 681b ldr r3, [r3, #0] 800deec: 6b59 ldr r1, [r3, #52] @ 0x34 800deee: 683b ldr r3, [r7, #0] 800def0: 685a ldr r2, [r3, #4] 800def2: 4613 mov r3, r2 800def4: 009b lsls r3, r3, #2 800def6: 4413 add r3, r2 800def8: 3b05 subs r3, #5 800defa: 221f movs r2, #31 800defc: fa02 f303 lsl.w r3, r2, r3 800df00: 43db mvns r3, r3 800df02: 4019 ands r1, r3 800df04: 683b ldr r3, [r7, #0] 800df06: 6818 ldr r0, [r3, #0] 800df08: 683b ldr r3, [r7, #0] 800df0a: 685a ldr r2, [r3, #4] 800df0c: 4613 mov r3, r2 800df0e: 009b lsls r3, r3, #2 800df10: 4413 add r3, r2 800df12: 3b05 subs r3, #5 800df14: fa00 f203 lsl.w r2, r0, r3 800df18: 687b ldr r3, [r7, #4] 800df1a: 681b ldr r3, [r3, #0] 800df1c: 430a orrs r2, r1 800df1e: 635a str r2, [r3, #52] @ 0x34 800df20: e03c b.n 800df9c ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 800df22: 683b ldr r3, [r7, #0] 800df24: 685b ldr r3, [r3, #4] 800df26: 2b0c cmp r3, #12 800df28: d81c bhi.n 800df64 { MODIFY_REG(hadc->Instance->SQR2 , 800df2a: 687b ldr r3, [r7, #4] 800df2c: 681b ldr r3, [r3, #0] 800df2e: 6b19 ldr r1, [r3, #48] @ 0x30 800df30: 683b ldr r3, [r7, #0] 800df32: 685a ldr r2, [r3, #4] 800df34: 4613 mov r3, r2 800df36: 009b lsls r3, r3, #2 800df38: 4413 add r3, r2 800df3a: 3b23 subs r3, #35 @ 0x23 800df3c: 221f movs r2, #31 800df3e: fa02 f303 lsl.w r3, r2, r3 800df42: 43db mvns r3, r3 800df44: 4019 ands r1, r3 800df46: 683b ldr r3, [r7, #0] 800df48: 6818 ldr r0, [r3, #0] 800df4a: 683b ldr r3, [r7, #0] 800df4c: 685a ldr r2, [r3, #4] 800df4e: 4613 mov r3, r2 800df50: 009b lsls r3, r3, #2 800df52: 4413 add r3, r2 800df54: 3b23 subs r3, #35 @ 0x23 800df56: fa00 f203 lsl.w r2, r0, r3 800df5a: 687b ldr r3, [r7, #4] 800df5c: 681b ldr r3, [r3, #0] 800df5e: 430a orrs r2, r1 800df60: 631a str r2, [r3, #48] @ 0x30 800df62: e01b b.n 800df9c ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 800df64: 687b ldr r3, [r7, #4] 800df66: 681b ldr r3, [r3, #0] 800df68: 6ad9 ldr r1, [r3, #44] @ 0x2c 800df6a: 683b ldr r3, [r7, #0] 800df6c: 685a ldr r2, [r3, #4] 800df6e: 4613 mov r3, r2 800df70: 009b lsls r3, r3, #2 800df72: 4413 add r3, r2 800df74: 3b41 subs r3, #65 @ 0x41 800df76: 221f movs r2, #31 800df78: fa02 f303 lsl.w r3, r2, r3 800df7c: 43db mvns r3, r3 800df7e: 4019 ands r1, r3 800df80: 683b ldr r3, [r7, #0] 800df82: 6818 ldr r0, [r3, #0] 800df84: 683b ldr r3, [r7, #0] 800df86: 685a ldr r2, [r3, #4] 800df88: 4613 mov r3, r2 800df8a: 009b lsls r3, r3, #2 800df8c: 4413 add r3, r2 800df8e: 3b41 subs r3, #65 @ 0x41 800df90: fa00 f203 lsl.w r2, r0, r3 800df94: 687b ldr r3, [r7, #4] 800df96: 681b ldr r3, [r3, #0] 800df98: 430a orrs r2, r1 800df9a: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 800df9c: 683b ldr r3, [r7, #0] 800df9e: 681b ldr r3, [r3, #0] 800dfa0: 2b09 cmp r3, #9 800dfa2: d91c bls.n 800dfde { MODIFY_REG(hadc->Instance->SMPR1 , 800dfa4: 687b ldr r3, [r7, #4] 800dfa6: 681b ldr r3, [r3, #0] 800dfa8: 68d9 ldr r1, [r3, #12] 800dfaa: 683b ldr r3, [r7, #0] 800dfac: 681a ldr r2, [r3, #0] 800dfae: 4613 mov r3, r2 800dfb0: 005b lsls r3, r3, #1 800dfb2: 4413 add r3, r2 800dfb4: 3b1e subs r3, #30 800dfb6: 2207 movs r2, #7 800dfb8: fa02 f303 lsl.w r3, r2, r3 800dfbc: 43db mvns r3, r3 800dfbe: 4019 ands r1, r3 800dfc0: 683b ldr r3, [r7, #0] 800dfc2: 6898 ldr r0, [r3, #8] 800dfc4: 683b ldr r3, [r7, #0] 800dfc6: 681a ldr r2, [r3, #0] 800dfc8: 4613 mov r3, r2 800dfca: 005b lsls r3, r3, #1 800dfcc: 4413 add r3, r2 800dfce: 3b1e subs r3, #30 800dfd0: fa00 f203 lsl.w r2, r0, r3 800dfd4: 687b ldr r3, [r7, #4] 800dfd6: 681b ldr r3, [r3, #0] 800dfd8: 430a orrs r2, r1 800dfda: 60da str r2, [r3, #12] 800dfdc: e019 b.n 800e012 ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 800dfde: 687b ldr r3, [r7, #4] 800dfe0: 681b ldr r3, [r3, #0] 800dfe2: 6919 ldr r1, [r3, #16] 800dfe4: 683b ldr r3, [r7, #0] 800dfe6: 681a ldr r2, [r3, #0] 800dfe8: 4613 mov r3, r2 800dfea: 005b lsls r3, r3, #1 800dfec: 4413 add r3, r2 800dfee: 2207 movs r2, #7 800dff0: fa02 f303 lsl.w r3, r2, r3 800dff4: 43db mvns r3, r3 800dff6: 4019 ands r1, r3 800dff8: 683b ldr r3, [r7, #0] 800dffa: 6898 ldr r0, [r3, #8] 800dffc: 683b ldr r3, [r7, #0] 800dffe: 681a ldr r2, [r3, #0] 800e000: 4613 mov r3, r2 800e002: 005b lsls r3, r3, #1 800e004: 4413 add r3, r2 800e006: fa00 f203 lsl.w r2, r0, r3 800e00a: 687b ldr r3, [r7, #4] 800e00c: 681b ldr r3, [r3, #0] 800e00e: 430a orrs r2, r1 800e010: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800e012: 683b ldr r3, [r7, #0] 800e014: 681b ldr r3, [r3, #0] 800e016: 2b10 cmp r3, #16 800e018: d003 beq.n 800e022 (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 800e01a: 683b ldr r3, [r7, #0] 800e01c: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800e01e: 2b11 cmp r3, #17 800e020: d132 bne.n 800e088 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 800e022: 687b ldr r3, [r7, #4] 800e024: 681b ldr r3, [r3, #0] 800e026: 4a1d ldr r2, [pc, #116] @ (800e09c ) 800e028: 4293 cmp r3, r2 800e02a: d125 bne.n 800e078 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 800e02c: 687b ldr r3, [r7, #4] 800e02e: 681b ldr r3, [r3, #0] 800e030: 689b ldr r3, [r3, #8] 800e032: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800e036: 2b00 cmp r3, #0 800e038: d126 bne.n 800e088 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 800e03a: 687b ldr r3, [r7, #4] 800e03c: 681b ldr r3, [r3, #0] 800e03e: 689a ldr r2, [r3, #8] 800e040: 687b ldr r3, [r7, #4] 800e042: 681b ldr r3, [r3, #0] 800e044: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 800e048: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 800e04a: 683b ldr r3, [r7, #0] 800e04c: 681b ldr r3, [r3, #0] 800e04e: 2b10 cmp r3, #16 800e050: d11a bne.n 800e088 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 800e052: 4b13 ldr r3, [pc, #76] @ (800e0a0 ) 800e054: 681b ldr r3, [r3, #0] 800e056: 4a13 ldr r2, [pc, #76] @ (800e0a4 ) 800e058: fba2 2303 umull r2, r3, r2, r3 800e05c: 0c9a lsrs r2, r3, #18 800e05e: 4613 mov r3, r2 800e060: 009b lsls r3, r3, #2 800e062: 4413 add r3, r2 800e064: 005b lsls r3, r3, #1 800e066: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e068: e002 b.n 800e070 { wait_loop_index--; 800e06a: 68bb ldr r3, [r7, #8] 800e06c: 3b01 subs r3, #1 800e06e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e070: 68bb ldr r3, [r7, #8] 800e072: 2b00 cmp r3, #0 800e074: d1f9 bne.n 800e06a 800e076: e007 b.n 800e088 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800e078: 687b ldr r3, [r7, #4] 800e07a: 6a9b ldr r3, [r3, #40] @ 0x28 800e07c: f043 0220 orr.w r2, r3, #32 800e080: 687b ldr r3, [r7, #4] 800e082: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800e084: 2301 movs r3, #1 800e086: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 800e088: 687b ldr r3, [r7, #4] 800e08a: 2200 movs r2, #0 800e08c: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800e090: 7bfb ldrb r3, [r7, #15] } 800e092: 4618 mov r0, r3 800e094: 3714 adds r7, #20 800e096: 46bd mov sp, r7 800e098: bc80 pop {r7} 800e09a: 4770 bx lr 800e09c: 40012400 .word 0x40012400 800e0a0: 2000006c .word 0x2000006c 800e0a4: 431bde83 .word 0x431bde83 0800e0a8 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 800e0a8: b580 push {r7, lr} 800e0aa: b084 sub sp, #16 800e0ac: af00 add r7, sp, #0 800e0ae: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800e0b0: 2300 movs r3, #0 800e0b2: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 800e0b4: 2300 movs r3, #0 800e0b6: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 800e0b8: 687b ldr r3, [r7, #4] 800e0ba: 681b ldr r3, [r3, #0] 800e0bc: 689b ldr r3, [r3, #8] 800e0be: f003 0301 and.w r3, r3, #1 800e0c2: 2b01 cmp r3, #1 800e0c4: d040 beq.n 800e148 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 800e0c6: 687b ldr r3, [r7, #4] 800e0c8: 681b ldr r3, [r3, #0] 800e0ca: 689a ldr r2, [r3, #8] 800e0cc: 687b ldr r3, [r7, #4] 800e0ce: 681b ldr r3, [r3, #0] 800e0d0: f042 0201 orr.w r2, r2, #1 800e0d4: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 800e0d6: 4b1f ldr r3, [pc, #124] @ (800e154 ) 800e0d8: 681b ldr r3, [r3, #0] 800e0da: 4a1f ldr r2, [pc, #124] @ (800e158 ) 800e0dc: fba2 2303 umull r2, r3, r2, r3 800e0e0: 0c9b lsrs r3, r3, #18 800e0e2: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e0e4: e002 b.n 800e0ec { wait_loop_index--; 800e0e6: 68bb ldr r3, [r7, #8] 800e0e8: 3b01 subs r3, #1 800e0ea: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e0ec: 68bb ldr r3, [r7, #8] 800e0ee: 2b00 cmp r3, #0 800e0f0: d1f9 bne.n 800e0e6 } /* Get tick count */ tickstart = HAL_GetTick(); 800e0f2: f7ff fbef bl 800d8d4 800e0f6: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 800e0f8: e01f b.n 800e13a { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 800e0fa: f7ff fbeb bl 800d8d4 800e0fe: 4602 mov r2, r0 800e100: 68fb ldr r3, [r7, #12] 800e102: 1ad3 subs r3, r2, r3 800e104: 2b02 cmp r3, #2 800e106: d918 bls.n 800e13a { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 800e108: 687b ldr r3, [r7, #4] 800e10a: 681b ldr r3, [r3, #0] 800e10c: 689b ldr r3, [r3, #8] 800e10e: f003 0301 and.w r3, r3, #1 800e112: 2b01 cmp r3, #1 800e114: d011 beq.n 800e13a { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800e116: 687b ldr r3, [r7, #4] 800e118: 6a9b ldr r3, [r3, #40] @ 0x28 800e11a: f043 0210 orr.w r2, r3, #16 800e11e: 687b ldr r3, [r7, #4] 800e120: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e122: 687b ldr r3, [r7, #4] 800e124: 6adb ldr r3, [r3, #44] @ 0x2c 800e126: f043 0201 orr.w r2, r3, #1 800e12a: 687b ldr r3, [r7, #4] 800e12c: 62da str r2, [r3, #44] @ 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 800e12e: 687b ldr r3, [r7, #4] 800e130: 2200 movs r2, #0 800e132: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e136: 2301 movs r3, #1 800e138: e007 b.n 800e14a while(ADC_IS_ENABLE(hadc) == RESET) 800e13a: 687b ldr r3, [r7, #4] 800e13c: 681b ldr r3, [r3, #0] 800e13e: 689b ldr r3, [r3, #8] 800e140: f003 0301 and.w r3, r3, #1 800e144: 2b01 cmp r3, #1 800e146: d1d8 bne.n 800e0fa } } } /* Return HAL status */ return HAL_OK; 800e148: 2300 movs r3, #0 } 800e14a: 4618 mov r0, r3 800e14c: 3710 adds r7, #16 800e14e: 46bd mov sp, r7 800e150: bd80 pop {r7, pc} 800e152: bf00 nop 800e154: 2000006c .word 0x2000006c 800e158: 431bde83 .word 0x431bde83 0800e15c : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 800e15c: b580 push {r7, lr} 800e15e: b084 sub sp, #16 800e160: af00 add r7, sp, #0 800e162: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800e164: 2300 movs r3, #0 800e166: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 800e168: 687b ldr r3, [r7, #4] 800e16a: 681b ldr r3, [r3, #0] 800e16c: 689b ldr r3, [r3, #8] 800e16e: f003 0301 and.w r3, r3, #1 800e172: 2b01 cmp r3, #1 800e174: d12e bne.n 800e1d4 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 800e176: 687b ldr r3, [r7, #4] 800e178: 681b ldr r3, [r3, #0] 800e17a: 689a ldr r2, [r3, #8] 800e17c: 687b ldr r3, [r7, #4] 800e17e: 681b ldr r3, [r3, #0] 800e180: f022 0201 bic.w r2, r2, #1 800e184: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 800e186: f7ff fba5 bl 800d8d4 800e18a: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 800e18c: e01b b.n 800e1c6 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800e18e: f7ff fba1 bl 800d8d4 800e192: 4602 mov r2, r0 800e194: 68fb ldr r3, [r7, #12] 800e196: 1ad3 subs r3, r2, r3 800e198: 2b02 cmp r3, #2 800e19a: d914 bls.n 800e1c6 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 800e19c: 687b ldr r3, [r7, #4] 800e19e: 681b ldr r3, [r3, #0] 800e1a0: 689b ldr r3, [r3, #8] 800e1a2: f003 0301 and.w r3, r3, #1 800e1a6: 2b01 cmp r3, #1 800e1a8: d10d bne.n 800e1c6 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800e1aa: 687b ldr r3, [r7, #4] 800e1ac: 6a9b ldr r3, [r3, #40] @ 0x28 800e1ae: f043 0210 orr.w r2, r3, #16 800e1b2: 687b ldr r3, [r7, #4] 800e1b4: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e1b6: 687b ldr r3, [r7, #4] 800e1b8: 6adb ldr r3, [r3, #44] @ 0x2c 800e1ba: f043 0201 orr.w r2, r3, #1 800e1be: 687b ldr r3, [r7, #4] 800e1c0: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 800e1c2: 2301 movs r3, #1 800e1c4: e007 b.n 800e1d6 while(ADC_IS_ENABLE(hadc) != RESET) 800e1c6: 687b ldr r3, [r7, #4] 800e1c8: 681b ldr r3, [r3, #0] 800e1ca: 689b ldr r3, [r3, #8] 800e1cc: f003 0301 and.w r3, r3, #1 800e1d0: 2b01 cmp r3, #1 800e1d2: d0dc beq.n 800e18e } } } /* Return HAL status */ return HAL_OK; 800e1d4: 2300 movs r3, #0 } 800e1d6: 4618 mov r0, r3 800e1d8: 3710 adds r7, #16 800e1da: 46bd mov sp, r7 800e1dc: bd80 pop {r7, pc} ... 0800e1e0 : * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { 800e1e0: b590 push {r4, r7, lr} 800e1e2: b087 sub sp, #28 800e1e4: af00 add r7, sp, #0 800e1e6: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e1e8: 2300 movs r3, #0 800e1ea: 75fb strb r3, [r7, #23] uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; 800e1ec: 2300 movs r3, #0 800e1ee: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800e1f0: 687b ldr r3, [r7, #4] 800e1f2: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e1f6: 2b01 cmp r3, #1 800e1f8: d101 bne.n 800e1fe 800e1fa: 2302 movs r3, #2 800e1fc: e097 b.n 800e32e 800e1fe: 687b ldr r3, [r7, #4] 800e200: 2201 movs r2, #1 800e202: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* 1. Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800e206: 6878 ldr r0, [r7, #4] 800e208: f7ff ffa8 bl 800e15c 800e20c: 4603 mov r3, r0 800e20e: 75fb strb r3, [r7, #23] /* 2. Calibration prerequisite delay before starting the calibration. */ /* - ADC must be enabled for at least two ADC clock cycles */ tmp_hal_status = ADC_Enable(hadc); 800e210: 6878 ldr r0, [r7, #4] 800e212: f7ff ff49 bl 800e0a8 800e216: 4603 mov r3, r0 800e218: 75fb strb r3, [r7, #23] /* Check if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800e21a: 7dfb ldrb r3, [r7, #23] 800e21c: 2b00 cmp r3, #0 800e21e: f040 8081 bne.w 800e324 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e222: 687b ldr r3, [r7, #4] 800e224: 6a9b ldr r3, [r3, #40] @ 0x28 800e226: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800e22a: f023 0302 bic.w r3, r3, #2 800e22e: f043 0202 orr.w r2, r3, #2 800e232: 687b ldr r3, [r7, #4] 800e234: 629a str r2, [r3, #40] @ 0x28 /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 800e236: 4b40 ldr r3, [pc, #256] @ (800e338 ) 800e238: 681c ldr r4, [r3, #0] 800e23a: 2002 movs r0, #2 800e23c: f002 fa8e bl 801075c 800e240: 4603 mov r3, r0 800e242: fbb4 f3f3 udiv r3, r4, r3 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 800e246: 005b lsls r3, r3, #1 wait_loop_index = ((SystemCoreClock 800e248: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800e24a: e002 b.n 800e252 { wait_loop_index--; 800e24c: 68fb ldr r3, [r7, #12] 800e24e: 3b01 subs r3, #1 800e250: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800e252: 68fb ldr r3, [r7, #12] 800e254: 2b00 cmp r3, #0 800e256: d1f9 bne.n 800e24c } /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 800e258: 687b ldr r3, [r7, #4] 800e25a: 681b ldr r3, [r3, #0] 800e25c: 689a ldr r2, [r3, #8] 800e25e: 687b ldr r3, [r7, #4] 800e260: 681b ldr r3, [r3, #0] 800e262: f042 0208 orr.w r2, r2, #8 800e266: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800e268: f7ff fb34 bl 800d8d4 800e26c: 6138 str r0, [r7, #16] /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800e26e: e01b b.n 800e2a8 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800e270: f7ff fb30 bl 800d8d4 800e274: 4602 mov r2, r0 800e276: 693b ldr r3, [r7, #16] 800e278: 1ad3 subs r3, r2, r3 800e27a: 2b0a cmp r3, #10 800e27c: d914 bls.n 800e2a8 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800e27e: 687b ldr r3, [r7, #4] 800e280: 681b ldr r3, [r3, #0] 800e282: 689b ldr r3, [r3, #8] 800e284: f003 0308 and.w r3, r3, #8 800e288: 2b00 cmp r3, #0 800e28a: d00d beq.n 800e2a8 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800e28c: 687b ldr r3, [r7, #4] 800e28e: 6a9b ldr r3, [r3, #40] @ 0x28 800e290: f023 0312 bic.w r3, r3, #18 800e294: f043 0210 orr.w r2, r3, #16 800e298: 687b ldr r3, [r7, #4] 800e29a: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800e29c: 687b ldr r3, [r7, #4] 800e29e: 2200 movs r2, #0 800e2a0: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e2a4: 2301 movs r3, #1 800e2a6: e042 b.n 800e32e while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800e2a8: 687b ldr r3, [r7, #4] 800e2aa: 681b ldr r3, [r3, #0] 800e2ac: 689b ldr r3, [r3, #8] 800e2ae: f003 0308 and.w r3, r3, #8 800e2b2: 2b00 cmp r3, #0 800e2b4: d1dc bne.n 800e270 } } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 800e2b6: 687b ldr r3, [r7, #4] 800e2b8: 681b ldr r3, [r3, #0] 800e2ba: 689a ldr r2, [r3, #8] 800e2bc: 687b ldr r3, [r7, #4] 800e2be: 681b ldr r3, [r3, #0] 800e2c0: f042 0204 orr.w r2, r2, #4 800e2c4: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800e2c6: f7ff fb05 bl 800d8d4 800e2ca: 6138 str r0, [r7, #16] /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800e2cc: e01b b.n 800e306 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800e2ce: f7ff fb01 bl 800d8d4 800e2d2: 4602 mov r2, r0 800e2d4: 693b ldr r3, [r7, #16] 800e2d6: 1ad3 subs r3, r2, r3 800e2d8: 2b0a cmp r3, #10 800e2da: d914 bls.n 800e306 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800e2dc: 687b ldr r3, [r7, #4] 800e2de: 681b ldr r3, [r3, #0] 800e2e0: 689b ldr r3, [r3, #8] 800e2e2: f003 0304 and.w r3, r3, #4 800e2e6: 2b00 cmp r3, #0 800e2e8: d00d beq.n 800e306 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800e2ea: 687b ldr r3, [r7, #4] 800e2ec: 6a9b ldr r3, [r3, #40] @ 0x28 800e2ee: f023 0312 bic.w r3, r3, #18 800e2f2: f043 0210 orr.w r2, r3, #16 800e2f6: 687b ldr r3, [r7, #4] 800e2f8: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800e2fa: 687b ldr r3, [r7, #4] 800e2fc: 2200 movs r2, #0 800e2fe: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e302: 2301 movs r3, #1 800e304: e013 b.n 800e32e while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800e306: 687b ldr r3, [r7, #4] 800e308: 681b ldr r3, [r3, #0] 800e30a: 689b ldr r3, [r3, #8] 800e30c: f003 0304 and.w r3, r3, #4 800e310: 2b00 cmp r3, #0 800e312: d1dc bne.n 800e2ce } } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e314: 687b ldr r3, [r7, #4] 800e316: 6a9b ldr r3, [r3, #40] @ 0x28 800e318: f023 0303 bic.w r3, r3, #3 800e31c: f043 0201 orr.w r2, r3, #1 800e320: 687b ldr r3, [r7, #4] 800e322: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 800e324: 687b ldr r3, [r7, #4] 800e326: 2200 movs r2, #0 800e328: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800e32c: 7dfb ldrb r3, [r7, #23] } 800e32e: 4618 mov r0, r3 800e330: 371c adds r7, #28 800e332: 46bd mov sp, r7 800e334: bd90 pop {r4, r7, pc} 800e336: bf00 nop 800e338: 2000006c .word 0x2000006c 0800e33c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { 800e33c: b580 push {r7, lr} 800e33e: b084 sub sp, #16 800e340: af00 add r7, sp, #0 800e342: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) 800e344: 687b ldr r3, [r7, #4] 800e346: 2b00 cmp r3, #0 800e348: d101 bne.n 800e34e { return HAL_ERROR; 800e34a: 2301 movs r3, #1 800e34c: e0ed b.n 800e52a /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) 800e34e: 687b ldr r3, [r7, #4] 800e350: f893 3020 ldrb.w r3, [r3, #32] 800e354: b2db uxtb r3, r3 800e356: 2b00 cmp r3, #0 800e358: d102 bne.n 800e360 { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); 800e35a: 6878 ldr r0, [r7, #4] 800e35c: f7fb fb4e bl 80099fc } #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800e360: 687b ldr r3, [r7, #4] 800e362: 681b ldr r3, [r3, #0] 800e364: 681a ldr r2, [r3, #0] 800e366: 687b ldr r3, [r7, #4] 800e368: 681b ldr r3, [r3, #0] 800e36a: f042 0201 orr.w r2, r2, #1 800e36e: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800e370: f7ff fab0 bl 800d8d4 800e374: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800e376: e012 b.n 800e39e { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800e378: f7ff faac bl 800d8d4 800e37c: 4602 mov r2, r0 800e37e: 68fb ldr r3, [r7, #12] 800e380: 1ad3 subs r3, r2, r3 800e382: 2b0a cmp r3, #10 800e384: d90b bls.n 800e39e { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800e386: 687b ldr r3, [r7, #4] 800e388: 6a5b ldr r3, [r3, #36] @ 0x24 800e38a: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800e38e: 687b ldr r3, [r7, #4] 800e390: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800e392: 687b ldr r3, [r7, #4] 800e394: 2205 movs r2, #5 800e396: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800e39a: 2301 movs r3, #1 800e39c: e0c5 b.n 800e52a while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800e39e: 687b ldr r3, [r7, #4] 800e3a0: 681b ldr r3, [r3, #0] 800e3a2: 685b ldr r3, [r3, #4] 800e3a4: f003 0301 and.w r3, r3, #1 800e3a8: 2b00 cmp r3, #0 800e3aa: d0e5 beq.n 800e378 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800e3ac: 687b ldr r3, [r7, #4] 800e3ae: 681b ldr r3, [r3, #0] 800e3b0: 681a ldr r2, [r3, #0] 800e3b2: 687b ldr r3, [r7, #4] 800e3b4: 681b ldr r3, [r3, #0] 800e3b6: f022 0202 bic.w r2, r2, #2 800e3ba: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800e3bc: f7ff fa8a bl 800d8d4 800e3c0: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800e3c2: e012 b.n 800e3ea { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800e3c4: f7ff fa86 bl 800d8d4 800e3c8: 4602 mov r2, r0 800e3ca: 68fb ldr r3, [r7, #12] 800e3cc: 1ad3 subs r3, r2, r3 800e3ce: 2b0a cmp r3, #10 800e3d0: d90b bls.n 800e3ea { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800e3d2: 687b ldr r3, [r7, #4] 800e3d4: 6a5b ldr r3, [r3, #36] @ 0x24 800e3d6: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800e3da: 687b ldr r3, [r7, #4] 800e3dc: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800e3de: 687b ldr r3, [r7, #4] 800e3e0: 2205 movs r2, #5 800e3e2: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800e3e6: 2301 movs r3, #1 800e3e8: e09f b.n 800e52a while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800e3ea: 687b ldr r3, [r7, #4] 800e3ec: 681b ldr r3, [r3, #0] 800e3ee: 685b ldr r3, [r3, #4] 800e3f0: f003 0302 and.w r3, r3, #2 800e3f4: 2b00 cmp r3, #0 800e3f6: d1e5 bne.n 800e3c4 } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) 800e3f8: 687b ldr r3, [r7, #4] 800e3fa: 7e1b ldrb r3, [r3, #24] 800e3fc: 2b01 cmp r3, #1 800e3fe: d108 bne.n 800e412 { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800e400: 687b ldr r3, [r7, #4] 800e402: 681b ldr r3, [r3, #0] 800e404: 681a ldr r2, [r3, #0] 800e406: 687b ldr r3, [r7, #4] 800e408: 681b ldr r3, [r3, #0] 800e40a: f042 0280 orr.w r2, r2, #128 @ 0x80 800e40e: 601a str r2, [r3, #0] 800e410: e007 b.n 800e422 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800e412: 687b ldr r3, [r7, #4] 800e414: 681b ldr r3, [r3, #0] 800e416: 681a ldr r2, [r3, #0] 800e418: 687b ldr r3, [r7, #4] 800e41a: 681b ldr r3, [r3, #0] 800e41c: f022 0280 bic.w r2, r2, #128 @ 0x80 800e420: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) 800e422: 687b ldr r3, [r7, #4] 800e424: 7e5b ldrb r3, [r3, #25] 800e426: 2b01 cmp r3, #1 800e428: d108 bne.n 800e43c { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800e42a: 687b ldr r3, [r7, #4] 800e42c: 681b ldr r3, [r3, #0] 800e42e: 681a ldr r2, [r3, #0] 800e430: 687b ldr r3, [r7, #4] 800e432: 681b ldr r3, [r3, #0] 800e434: f042 0240 orr.w r2, r2, #64 @ 0x40 800e438: 601a str r2, [r3, #0] 800e43a: e007 b.n 800e44c } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800e43c: 687b ldr r3, [r7, #4] 800e43e: 681b ldr r3, [r3, #0] 800e440: 681a ldr r2, [r3, #0] 800e442: 687b ldr r3, [r7, #4] 800e444: 681b ldr r3, [r3, #0] 800e446: f022 0240 bic.w r2, r2, #64 @ 0x40 800e44a: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) 800e44c: 687b ldr r3, [r7, #4] 800e44e: 7e9b ldrb r3, [r3, #26] 800e450: 2b01 cmp r3, #1 800e452: d108 bne.n 800e466 { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800e454: 687b ldr r3, [r7, #4] 800e456: 681b ldr r3, [r3, #0] 800e458: 681a ldr r2, [r3, #0] 800e45a: 687b ldr r3, [r7, #4] 800e45c: 681b ldr r3, [r3, #0] 800e45e: f042 0220 orr.w r2, r2, #32 800e462: 601a str r2, [r3, #0] 800e464: e007 b.n 800e476 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800e466: 687b ldr r3, [r7, #4] 800e468: 681b ldr r3, [r3, #0] 800e46a: 681a ldr r2, [r3, #0] 800e46c: 687b ldr r3, [r7, #4] 800e46e: 681b ldr r3, [r3, #0] 800e470: f022 0220 bic.w r2, r2, #32 800e474: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) 800e476: 687b ldr r3, [r7, #4] 800e478: 7edb ldrb r3, [r3, #27] 800e47a: 2b01 cmp r3, #1 800e47c: d108 bne.n 800e490 { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800e47e: 687b ldr r3, [r7, #4] 800e480: 681b ldr r3, [r3, #0] 800e482: 681a ldr r2, [r3, #0] 800e484: 687b ldr r3, [r7, #4] 800e486: 681b ldr r3, [r3, #0] 800e488: f022 0210 bic.w r2, r2, #16 800e48c: 601a str r2, [r3, #0] 800e48e: e007 b.n 800e4a0 } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800e490: 687b ldr r3, [r7, #4] 800e492: 681b ldr r3, [r3, #0] 800e494: 681a ldr r2, [r3, #0] 800e496: 687b ldr r3, [r7, #4] 800e498: 681b ldr r3, [r3, #0] 800e49a: f042 0210 orr.w r2, r2, #16 800e49e: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) 800e4a0: 687b ldr r3, [r7, #4] 800e4a2: 7f1b ldrb r3, [r3, #28] 800e4a4: 2b01 cmp r3, #1 800e4a6: d108 bne.n 800e4ba { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800e4a8: 687b ldr r3, [r7, #4] 800e4aa: 681b ldr r3, [r3, #0] 800e4ac: 681a ldr r2, [r3, #0] 800e4ae: 687b ldr r3, [r7, #4] 800e4b0: 681b ldr r3, [r3, #0] 800e4b2: f042 0208 orr.w r2, r2, #8 800e4b6: 601a str r2, [r3, #0] 800e4b8: e007 b.n 800e4ca } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800e4ba: 687b ldr r3, [r7, #4] 800e4bc: 681b ldr r3, [r3, #0] 800e4be: 681a ldr r2, [r3, #0] 800e4c0: 687b ldr r3, [r7, #4] 800e4c2: 681b ldr r3, [r3, #0] 800e4c4: f022 0208 bic.w r2, r2, #8 800e4c8: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) 800e4ca: 687b ldr r3, [r7, #4] 800e4cc: 7f5b ldrb r3, [r3, #29] 800e4ce: 2b01 cmp r3, #1 800e4d0: d108 bne.n 800e4e4 { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800e4d2: 687b ldr r3, [r7, #4] 800e4d4: 681b ldr r3, [r3, #0] 800e4d6: 681a ldr r2, [r3, #0] 800e4d8: 687b ldr r3, [r7, #4] 800e4da: 681b ldr r3, [r3, #0] 800e4dc: f042 0204 orr.w r2, r2, #4 800e4e0: 601a str r2, [r3, #0] 800e4e2: e007 b.n 800e4f4 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800e4e4: 687b ldr r3, [r7, #4] 800e4e6: 681b ldr r3, [r3, #0] 800e4e8: 681a ldr r2, [r3, #0] 800e4ea: 687b ldr r3, [r7, #4] 800e4ec: 681b ldr r3, [r3, #0] 800e4ee: f022 0204 bic.w r2, r2, #4 800e4f2: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | 800e4f4: 687b ldr r3, [r7, #4] 800e4f6: 689a ldr r2, [r3, #8] 800e4f8: 687b ldr r3, [r7, #4] 800e4fa: 68db ldr r3, [r3, #12] 800e4fc: 431a orrs r2, r3 800e4fe: 687b ldr r3, [r7, #4] 800e500: 691b ldr r3, [r3, #16] 800e502: 431a orrs r2, r3 800e504: 687b ldr r3, [r7, #4] 800e506: 695b ldr r3, [r3, #20] 800e508: ea42 0103 orr.w r1, r2, r3 800e50c: 687b ldr r3, [r7, #4] 800e50e: 685b ldr r3, [r3, #4] 800e510: 1e5a subs r2, r3, #1 800e512: 687b ldr r3, [r7, #4] 800e514: 681b ldr r3, [r3, #0] 800e516: 430a orrs r2, r1 800e518: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800e51a: 687b ldr r3, [r7, #4] 800e51c: 2200 movs r2, #0 800e51e: 625a str r2, [r3, #36] @ 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; 800e520: 687b ldr r3, [r7, #4] 800e522: 2201 movs r2, #1 800e524: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800e528: 2300 movs r3, #0 } 800e52a: 4618 mov r0, r3 800e52c: 3710 adds r7, #16 800e52e: 46bd mov sp, r7 800e530: bd80 pop {r7, pc} ... 0800e534 : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { 800e534: b480 push {r7} 800e536: b087 sub sp, #28 800e538: af00 add r7, sp, #0 800e53a: 6078 str r0, [r7, #4] 800e53c: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; 800e53e: 687b ldr r3, [r7, #4] 800e540: 681b ldr r3, [r3, #0] 800e542: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; 800e544: 687b ldr r3, [r7, #4] 800e546: f893 3020 ldrb.w r3, [r3, #32] 800e54a: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || 800e54c: 7cfb ldrb r3, [r7, #19] 800e54e: 2b01 cmp r3, #1 800e550: d003 beq.n 800e55a 800e552: 7cfb ldrb r3, [r7, #19] 800e554: 2b02 cmp r3, #2 800e556: f040 80be bne.w 800e6d6 assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); #if defined(CAN2) /* CAN1 and CAN2 are dual instances with 28 common filters banks */ /* Select master instance to access the filter banks */ can_ip = CAN1; 800e55a: 4b65 ldr r3, [pc, #404] @ (800e6f0 ) 800e55c: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); #endif /* CAN3 */ /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); 800e55e: 697b ldr r3, [r7, #20] 800e560: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800e564: f043 0201 orr.w r2, r3, #1 800e568: 697b ldr r3, [r7, #20] 800e56a: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #if defined(CAN2) /* Select the start filter number of CAN2 slave instance */ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); 800e56e: 697b ldr r3, [r7, #20] 800e570: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800e574: f423 527c bic.w r2, r3, #16128 @ 0x3f00 800e578: 697b ldr r3, [r7, #20] 800e57a: f8c3 2200 str.w r2, [r3, #512] @ 0x200 SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); 800e57e: 697b ldr r3, [r7, #20] 800e580: f8d3 2200 ldr.w r2, [r3, #512] @ 0x200 800e584: 683b ldr r3, [r7, #0] 800e586: 6a5b ldr r3, [r3, #36] @ 0x24 800e588: 021b lsls r3, r3, #8 800e58a: 431a orrs r2, r3 800e58c: 697b ldr r3, [r7, #20] 800e58e: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #endif /* CAN3 */ /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); 800e592: 683b ldr r3, [r7, #0] 800e594: 695b ldr r3, [r3, #20] 800e596: f003 031f and.w r3, r3, #31 800e59a: 2201 movs r2, #1 800e59c: fa02 f303 lsl.w r3, r2, r3 800e5a0: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); 800e5a2: 697b ldr r3, [r7, #20] 800e5a4: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800e5a8: 68fb ldr r3, [r7, #12] 800e5aa: 43db mvns r3, r3 800e5ac: 401a ands r2, r3 800e5ae: 697b ldr r3, [r7, #20] 800e5b0: f8c3 221c str.w r2, [r3, #540] @ 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) 800e5b4: 683b ldr r3, [r7, #0] 800e5b6: 69db ldr r3, [r3, #28] 800e5b8: 2b00 cmp r3, #0 800e5ba: d123 bne.n 800e604 { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); 800e5bc: 697b ldr r3, [r7, #20] 800e5be: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800e5c2: 68fb ldr r3, [r7, #12] 800e5c4: 43db mvns r3, r3 800e5c6: 401a ands r2, r3 800e5c8: 697b ldr r3, [r7, #20] 800e5ca: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800e5ce: 683b ldr r3, [r7, #0] 800e5d0: 68db ldr r3, [r3, #12] 800e5d2: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800e5d4: 683b ldr r3, [r7, #0] 800e5d6: 685b ldr r3, [r3, #4] 800e5d8: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800e5da: 683a ldr r2, [r7, #0] 800e5dc: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800e5de: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800e5e0: 697b ldr r3, [r7, #20] 800e5e2: 3248 adds r2, #72 @ 0x48 800e5e4: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800e5e8: 683b ldr r3, [r7, #0] 800e5ea: 689b ldr r3, [r3, #8] 800e5ec: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); 800e5ee: 683b ldr r3, [r7, #0] 800e5f0: 681b ldr r3, [r3, #0] 800e5f2: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800e5f4: 683b ldr r3, [r7, #0] 800e5f6: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800e5f8: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800e5fa: 6979 ldr r1, [r7, #20] 800e5fc: 3348 adds r3, #72 @ 0x48 800e5fe: 00db lsls r3, r3, #3 800e600: 440b add r3, r1 800e602: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) 800e604: 683b ldr r3, [r7, #0] 800e606: 69db ldr r3, [r3, #28] 800e608: 2b01 cmp r3, #1 800e60a: d122 bne.n 800e652 { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); 800e60c: 697b ldr r3, [r7, #20] 800e60e: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800e612: 68fb ldr r3, [r7, #12] 800e614: 431a orrs r2, r3 800e616: 697b ldr r3, [r7, #20] 800e618: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800e61c: 683b ldr r3, [r7, #0] 800e61e: 681b ldr r3, [r3, #0] 800e620: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800e622: 683b ldr r3, [r7, #0] 800e624: 685b ldr r3, [r3, #4] 800e626: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800e628: 683a ldr r2, [r7, #0] 800e62a: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800e62c: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800e62e: 697b ldr r3, [r7, #20] 800e630: 3248 adds r2, #72 @ 0x48 800e632: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800e636: 683b ldr r3, [r7, #0] 800e638: 689b ldr r3, [r3, #8] 800e63a: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); 800e63c: 683b ldr r3, [r7, #0] 800e63e: 68db ldr r3, [r3, #12] 800e640: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800e642: 683b ldr r3, [r7, #0] 800e644: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800e646: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800e648: 6979 ldr r1, [r7, #20] 800e64a: 3348 adds r3, #72 @ 0x48 800e64c: 00db lsls r3, r3, #3 800e64e: 440b add r3, r1 800e650: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) 800e652: 683b ldr r3, [r7, #0] 800e654: 699b ldr r3, [r3, #24] 800e656: 2b00 cmp r3, #0 800e658: d109 bne.n 800e66e { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); 800e65a: 697b ldr r3, [r7, #20] 800e65c: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800e660: 68fb ldr r3, [r7, #12] 800e662: 43db mvns r3, r3 800e664: 401a ands r2, r3 800e666: 697b ldr r3, [r7, #20] 800e668: f8c3 2204 str.w r2, [r3, #516] @ 0x204 800e66c: e007 b.n 800e67e } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); 800e66e: 697b ldr r3, [r7, #20] 800e670: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800e674: 68fb ldr r3, [r7, #12] 800e676: 431a orrs r2, r3 800e678: 697b ldr r3, [r7, #20] 800e67a: f8c3 2204 str.w r2, [r3, #516] @ 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) 800e67e: 683b ldr r3, [r7, #0] 800e680: 691b ldr r3, [r3, #16] 800e682: 2b00 cmp r3, #0 800e684: d109 bne.n 800e69a { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); 800e686: 697b ldr r3, [r7, #20] 800e688: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800e68c: 68fb ldr r3, [r7, #12] 800e68e: 43db mvns r3, r3 800e690: 401a ands r2, r3 800e692: 697b ldr r3, [r7, #20] 800e694: f8c3 2214 str.w r2, [r3, #532] @ 0x214 800e698: e007 b.n 800e6aa } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); 800e69a: 697b ldr r3, [r7, #20] 800e69c: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800e6a0: 68fb ldr r3, [r7, #12] 800e6a2: 431a orrs r2, r3 800e6a4: 697b ldr r3, [r7, #20] 800e6a6: f8c3 2214 str.w r2, [r3, #532] @ 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) 800e6aa: 683b ldr r3, [r7, #0] 800e6ac: 6a1b ldr r3, [r3, #32] 800e6ae: 2b01 cmp r3, #1 800e6b0: d107 bne.n 800e6c2 { SET_BIT(can_ip->FA1R, filternbrbitpos); 800e6b2: 697b ldr r3, [r7, #20] 800e6b4: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800e6b8: 68fb ldr r3, [r7, #12] 800e6ba: 431a orrs r2, r3 800e6bc: 697b ldr r3, [r7, #20] 800e6be: f8c3 221c str.w r2, [r3, #540] @ 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); 800e6c2: 697b ldr r3, [r7, #20] 800e6c4: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800e6c8: f023 0201 bic.w r2, r3, #1 800e6cc: 697b ldr r3, [r7, #20] 800e6ce: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Return function status */ return HAL_OK; 800e6d2: 2300 movs r3, #0 800e6d4: e006 b.n 800e6e4 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800e6d6: 687b ldr r3, [r7, #4] 800e6d8: 6a5b ldr r3, [r3, #36] @ 0x24 800e6da: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800e6de: 687b ldr r3, [r7, #4] 800e6e0: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e6e2: 2301 movs r3, #1 } } 800e6e4: 4618 mov r0, r3 800e6e6: 371c adds r7, #28 800e6e8: 46bd mov sp, r7 800e6ea: bc80 pop {r7} 800e6ec: 4770 bx lr 800e6ee: bf00 nop 800e6f0: 40006400 .word 0x40006400 0800e6f4 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { 800e6f4: b580 push {r7, lr} 800e6f6: b084 sub sp, #16 800e6f8: af00 add r7, sp, #0 800e6fa: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) 800e6fc: 687b ldr r3, [r7, #4] 800e6fe: f893 3020 ldrb.w r3, [r3, #32] 800e702: b2db uxtb r3, r3 800e704: 2b01 cmp r3, #1 800e706: d12e bne.n 800e766 { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; 800e708: 687b ldr r3, [r7, #4] 800e70a: 2202 movs r2, #2 800e70c: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800e710: 687b ldr r3, [r7, #4] 800e712: 681b ldr r3, [r3, #0] 800e714: 681a ldr r2, [r3, #0] 800e716: 687b ldr r3, [r7, #4] 800e718: 681b ldr r3, [r3, #0] 800e71a: f022 0201 bic.w r2, r2, #1 800e71e: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800e720: f7ff f8d8 bl 800d8d4 800e724: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800e726: e012 b.n 800e74e { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800e728: f7ff f8d4 bl 800d8d4 800e72c: 4602 mov r2, r0 800e72e: 68fb ldr r3, [r7, #12] 800e730: 1ad3 subs r3, r2, r3 800e732: 2b0a cmp r3, #10 800e734: d90b bls.n 800e74e { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800e736: 687b ldr r3, [r7, #4] 800e738: 6a5b ldr r3, [r3, #36] @ 0x24 800e73a: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800e73e: 687b ldr r3, [r7, #4] 800e740: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800e742: 687b ldr r3, [r7, #4] 800e744: 2205 movs r2, #5 800e746: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800e74a: 2301 movs r3, #1 800e74c: e012 b.n 800e774 while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800e74e: 687b ldr r3, [r7, #4] 800e750: 681b ldr r3, [r3, #0] 800e752: 685b ldr r3, [r3, #4] 800e754: f003 0301 and.w r3, r3, #1 800e758: 2b00 cmp r3, #0 800e75a: d1e5 bne.n 800e728 } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800e75c: 687b ldr r3, [r7, #4] 800e75e: 2200 movs r2, #0 800e760: 625a str r2, [r3, #36] @ 0x24 /* Return function status */ return HAL_OK; 800e762: 2300 movs r3, #0 800e764: e006 b.n 800e774 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; 800e766: 687b ldr r3, [r7, #4] 800e768: 6a5b ldr r3, [r3, #36] @ 0x24 800e76a: f443 2200 orr.w r2, r3, #524288 @ 0x80000 800e76e: 687b ldr r3, [r7, #4] 800e770: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e772: 2301 movs r3, #1 } } 800e774: 4618 mov r0, r3 800e776: 3710 adds r7, #16 800e778: 46bd mov sp, r7 800e77a: bd80 pop {r7, pc} 0800e77c : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { 800e77c: b580 push {r7, lr} 800e77e: b084 sub sp, #16 800e780: af00 add r7, sp, #0 800e782: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_LISTENING) 800e784: 687b ldr r3, [r7, #4] 800e786: f893 3020 ldrb.w r3, [r3, #32] 800e78a: b2db uxtb r3, r3 800e78c: 2b02 cmp r3, #2 800e78e: d133 bne.n 800e7f8 { /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800e790: 687b ldr r3, [r7, #4] 800e792: 681b ldr r3, [r3, #0] 800e794: 681a ldr r2, [r3, #0] 800e796: 687b ldr r3, [r7, #4] 800e798: 681b ldr r3, [r3, #0] 800e79a: f042 0201 orr.w r2, r2, #1 800e79e: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800e7a0: f7ff f898 bl 800d8d4 800e7a4: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800e7a6: e012 b.n 800e7ce { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800e7a8: f7ff f894 bl 800d8d4 800e7ac: 4602 mov r2, r0 800e7ae: 68fb ldr r3, [r7, #12] 800e7b0: 1ad3 subs r3, r2, r3 800e7b2: 2b0a cmp r3, #10 800e7b4: d90b bls.n 800e7ce { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800e7b6: 687b ldr r3, [r7, #4] 800e7b8: 6a5b ldr r3, [r3, #36] @ 0x24 800e7ba: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800e7be: 687b ldr r3, [r7, #4] 800e7c0: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800e7c2: 687b ldr r3, [r7, #4] 800e7c4: 2205 movs r2, #5 800e7c6: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800e7ca: 2301 movs r3, #1 800e7cc: e01b b.n 800e806 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800e7ce: 687b ldr r3, [r7, #4] 800e7d0: 681b ldr r3, [r3, #0] 800e7d2: 685b ldr r3, [r3, #4] 800e7d4: f003 0301 and.w r3, r3, #1 800e7d8: 2b00 cmp r3, #0 800e7da: d0e5 beq.n 800e7a8 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800e7dc: 687b ldr r3, [r7, #4] 800e7de: 681b ldr r3, [r3, #0] 800e7e0: 681a ldr r2, [r3, #0] 800e7e2: 687b ldr r3, [r7, #4] 800e7e4: 681b ldr r3, [r3, #0] 800e7e6: f022 0202 bic.w r2, r2, #2 800e7ea: 601a str r2, [r3, #0] /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_READY; 800e7ec: 687b ldr r3, [r7, #4] 800e7ee: 2201 movs r2, #1 800e7f0: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800e7f4: 2300 movs r3, #0 800e7f6: e006 b.n 800e806 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; 800e7f8: 687b ldr r3, [r7, #4] 800e7fa: 6a5b ldr r3, [r3, #36] @ 0x24 800e7fc: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800e800: 687b ldr r3, [r7, #4] 800e802: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e804: 2301 movs r3, #1 } } 800e806: 4618 mov r0, r3 800e808: 3710 adds r7, #16 800e80a: 46bd mov sp, r7 800e80c: bd80 pop {r7, pc} 0800e80e : * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, const uint8_t aData[], uint32_t *pTxMailbox) { 800e80e: b480 push {r7} 800e810: b089 sub sp, #36 @ 0x24 800e812: af00 add r7, sp, #0 800e814: 60f8 str r0, [r7, #12] 800e816: 60b9 str r1, [r7, #8] 800e818: 607a str r2, [r7, #4] 800e81a: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; 800e81c: 68fb ldr r3, [r7, #12] 800e81e: f893 3020 ldrb.w r3, [r3, #32] 800e822: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); 800e824: 68fb ldr r3, [r7, #12] 800e826: 681b ldr r3, [r3, #0] 800e828: 689b ldr r3, [r3, #8] 800e82a: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || 800e82c: 7ffb ldrb r3, [r7, #31] 800e82e: 2b01 cmp r3, #1 800e830: d003 beq.n 800e83a 800e832: 7ffb ldrb r3, [r7, #31] 800e834: 2b02 cmp r3, #2 800e836: f040 80ad bne.w 800e994 (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || 800e83a: 69bb ldr r3, [r7, #24] 800e83c: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800e840: 2b00 cmp r3, #0 800e842: d10a bne.n 800e85a ((tsr & CAN_TSR_TME1) != 0U) || 800e844: 69bb ldr r3, [r7, #24] 800e846: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || 800e84a: 2b00 cmp r3, #0 800e84c: d105 bne.n 800e85a ((tsr & CAN_TSR_TME2) != 0U)) 800e84e: 69bb ldr r3, [r7, #24] 800e850: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || 800e854: 2b00 cmp r3, #0 800e856: f000 8095 beq.w 800e984 { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; 800e85a: 69bb ldr r3, [r7, #24] 800e85c: 0e1b lsrs r3, r3, #24 800e85e: f003 0303 and.w r3, r3, #3 800e862: 617b str r3, [r7, #20] /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; 800e864: 2201 movs r2, #1 800e866: 697b ldr r3, [r7, #20] 800e868: 409a lsls r2, r3 800e86a: 683b ldr r3, [r7, #0] 800e86c: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) 800e86e: 68bb ldr r3, [r7, #8] 800e870: 689b ldr r3, [r3, #8] 800e872: 2b00 cmp r3, #0 800e874: d10d bne.n 800e892 { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800e876: 68bb ldr r3, [r7, #8] 800e878: 681b ldr r3, [r3, #0] 800e87a: 055a lsls r2, r3, #21 pHeader->RTR); 800e87c: 68bb ldr r3, [r7, #8] 800e87e: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800e880: 68f9 ldr r1, [r7, #12] 800e882: 6809 ldr r1, [r1, #0] 800e884: 431a orrs r2, r3 800e886: 697b ldr r3, [r7, #20] 800e888: 3318 adds r3, #24 800e88a: 011b lsls r3, r3, #4 800e88c: 440b add r3, r1 800e88e: 601a str r2, [r3, #0] 800e890: e00f b.n 800e8b2 } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800e892: 68bb ldr r3, [r7, #8] 800e894: 685b ldr r3, [r3, #4] 800e896: 00da lsls r2, r3, #3 pHeader->IDE | 800e898: 68bb ldr r3, [r7, #8] 800e89a: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800e89c: 431a orrs r2, r3 pHeader->RTR); 800e89e: 68bb ldr r3, [r7, #8] 800e8a0: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800e8a2: 68f9 ldr r1, [r7, #12] 800e8a4: 6809 ldr r1, [r1, #0] pHeader->IDE | 800e8a6: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800e8a8: 697b ldr r3, [r7, #20] 800e8aa: 3318 adds r3, #24 800e8ac: 011b lsls r3, r3, #4 800e8ae: 440b add r3, r1 800e8b0: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); 800e8b2: 68fb ldr r3, [r7, #12] 800e8b4: 6819 ldr r1, [r3, #0] 800e8b6: 68bb ldr r3, [r7, #8] 800e8b8: 691a ldr r2, [r3, #16] 800e8ba: 697b ldr r3, [r7, #20] 800e8bc: 3318 adds r3, #24 800e8be: 011b lsls r3, r3, #4 800e8c0: 440b add r3, r1 800e8c2: 3304 adds r3, #4 800e8c4: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) 800e8c6: 68bb ldr r3, [r7, #8] 800e8c8: 7d1b ldrb r3, [r3, #20] 800e8ca: 2b01 cmp r3, #1 800e8cc: d111 bne.n 800e8f2 { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); 800e8ce: 68fb ldr r3, [r7, #12] 800e8d0: 681a ldr r2, [r3, #0] 800e8d2: 697b ldr r3, [r7, #20] 800e8d4: 3318 adds r3, #24 800e8d6: 011b lsls r3, r3, #4 800e8d8: 4413 add r3, r2 800e8da: 3304 adds r3, #4 800e8dc: 681b ldr r3, [r3, #0] 800e8de: 68fa ldr r2, [r7, #12] 800e8e0: 6811 ldr r1, [r2, #0] 800e8e2: f443 7280 orr.w r2, r3, #256 @ 0x100 800e8e6: 697b ldr r3, [r7, #20] 800e8e8: 3318 adds r3, #24 800e8ea: 011b lsls r3, r3, #4 800e8ec: 440b add r3, r1 800e8ee: 3304 adds r3, #4 800e8f0: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, 800e8f2: 687b ldr r3, [r7, #4] 800e8f4: 3307 adds r3, #7 800e8f6: 781b ldrb r3, [r3, #0] 800e8f8: 061a lsls r2, r3, #24 800e8fa: 687b ldr r3, [r7, #4] 800e8fc: 3306 adds r3, #6 800e8fe: 781b ldrb r3, [r3, #0] 800e900: 041b lsls r3, r3, #16 800e902: 431a orrs r2, r3 800e904: 687b ldr r3, [r7, #4] 800e906: 3305 adds r3, #5 800e908: 781b ldrb r3, [r3, #0] 800e90a: 021b lsls r3, r3, #8 800e90c: 4313 orrs r3, r2 800e90e: 687a ldr r2, [r7, #4] 800e910: 3204 adds r2, #4 800e912: 7812 ldrb r2, [r2, #0] 800e914: 4610 mov r0, r2 800e916: 68fa ldr r2, [r7, #12] 800e918: 6811 ldr r1, [r2, #0] 800e91a: ea43 0200 orr.w r2, r3, r0 800e91e: 697b ldr r3, [r7, #20] 800e920: 011b lsls r3, r3, #4 800e922: 440b add r3, r1 800e924: f503 73c6 add.w r3, r3, #396 @ 0x18c 800e928: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, 800e92a: 687b ldr r3, [r7, #4] 800e92c: 3303 adds r3, #3 800e92e: 781b ldrb r3, [r3, #0] 800e930: 061a lsls r2, r3, #24 800e932: 687b ldr r3, [r7, #4] 800e934: 3302 adds r3, #2 800e936: 781b ldrb r3, [r3, #0] 800e938: 041b lsls r3, r3, #16 800e93a: 431a orrs r2, r3 800e93c: 687b ldr r3, [r7, #4] 800e93e: 3301 adds r3, #1 800e940: 781b ldrb r3, [r3, #0] 800e942: 021b lsls r3, r3, #8 800e944: 4313 orrs r3, r2 800e946: 687a ldr r2, [r7, #4] 800e948: 7812 ldrb r2, [r2, #0] 800e94a: 4610 mov r0, r2 800e94c: 68fa ldr r2, [r7, #12] 800e94e: 6811 ldr r1, [r2, #0] 800e950: ea43 0200 orr.w r2, r3, r0 800e954: 697b ldr r3, [r7, #20] 800e956: 011b lsls r3, r3, #4 800e958: 440b add r3, r1 800e95a: f503 73c4 add.w r3, r3, #392 @ 0x188 800e95e: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); 800e960: 68fb ldr r3, [r7, #12] 800e962: 681a ldr r2, [r3, #0] 800e964: 697b ldr r3, [r7, #20] 800e966: 3318 adds r3, #24 800e968: 011b lsls r3, r3, #4 800e96a: 4413 add r3, r2 800e96c: 681b ldr r3, [r3, #0] 800e96e: 68fa ldr r2, [r7, #12] 800e970: 6811 ldr r1, [r2, #0] 800e972: f043 0201 orr.w r2, r3, #1 800e976: 697b ldr r3, [r7, #20] 800e978: 3318 adds r3, #24 800e97a: 011b lsls r3, r3, #4 800e97c: 440b add r3, r1 800e97e: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800e980: 2300 movs r3, #0 800e982: e00e b.n 800e9a2 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800e984: 68fb ldr r3, [r7, #12] 800e986: 6a5b ldr r3, [r3, #36] @ 0x24 800e988: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800e98c: 68fb ldr r3, [r7, #12] 800e98e: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e990: 2301 movs r3, #1 800e992: e006 b.n 800e9a2 } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800e994: 68fb ldr r3, [r7, #12] 800e996: 6a5b ldr r3, [r3, #36] @ 0x24 800e998: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800e99c: 68fb ldr r3, [r7, #12] 800e99e: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e9a0: 2301 movs r3, #1 } } 800e9a2: 4618 mov r0, r3 800e9a4: 3724 adds r7, #36 @ 0x24 800e9a6: 46bd mov sp, r7 800e9a8: bc80 pop {r7} 800e9aa: 4770 bx lr 0800e9ac : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval Number of free Tx Mailboxes. */ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) { 800e9ac: b480 push {r7} 800e9ae: b085 sub sp, #20 800e9b0: af00 add r7, sp, #0 800e9b2: 6078 str r0, [r7, #4] uint32_t freelevel = 0U; 800e9b4: 2300 movs r3, #0 800e9b6: 60fb str r3, [r7, #12] HAL_CAN_StateTypeDef state = hcan->State; 800e9b8: 687b ldr r3, [r7, #4] 800e9ba: f893 3020 ldrb.w r3, [r3, #32] 800e9be: 72fb strb r3, [r7, #11] if ((state == HAL_CAN_STATE_READY) || 800e9c0: 7afb ldrb r3, [r7, #11] 800e9c2: 2b01 cmp r3, #1 800e9c4: d002 beq.n 800e9cc 800e9c6: 7afb ldrb r3, [r7, #11] 800e9c8: 2b02 cmp r3, #2 800e9ca: d11d bne.n 800ea08 (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 status */ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) 800e9cc: 687b ldr r3, [r7, #4] 800e9ce: 681b ldr r3, [r3, #0] 800e9d0: 689b ldr r3, [r3, #8] 800e9d2: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800e9d6: 2b00 cmp r3, #0 800e9d8: d002 beq.n 800e9e0 { freelevel++; 800e9da: 68fb ldr r3, [r7, #12] 800e9dc: 3301 adds r3, #1 800e9de: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 1 status */ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) 800e9e0: 687b ldr r3, [r7, #4] 800e9e2: 681b ldr r3, [r3, #0] 800e9e4: 689b ldr r3, [r3, #8] 800e9e6: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e9ea: 2b00 cmp r3, #0 800e9ec: d002 beq.n 800e9f4 { freelevel++; 800e9ee: 68fb ldr r3, [r7, #12] 800e9f0: 3301 adds r3, #1 800e9f2: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 2 status */ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) 800e9f4: 687b ldr r3, [r7, #4] 800e9f6: 681b ldr r3, [r3, #0] 800e9f8: 689b ldr r3, [r3, #8] 800e9fa: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800e9fe: 2b00 cmp r3, #0 800ea00: d002 beq.n 800ea08 { freelevel++; 800ea02: 68fb ldr r3, [r7, #12] 800ea04: 3301 adds r3, #1 800ea06: 60fb str r3, [r7, #12] } } /* Return Tx Mailboxes free level */ return freelevel; 800ea08: 68fb ldr r3, [r7, #12] } 800ea0a: 4618 mov r0, r3 800ea0c: 3714 adds r7, #20 800ea0e: 46bd mov sp, r7 800ea10: bc80 pop {r7} 800ea12: 4770 bx lr 0800ea14 : * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { 800ea14: b480 push {r7} 800ea16: b087 sub sp, #28 800ea18: af00 add r7, sp, #0 800ea1a: 60f8 str r0, [r7, #12] 800ea1c: 60b9 str r1, [r7, #8] 800ea1e: 607a str r2, [r7, #4] 800ea20: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800ea22: 68fb ldr r3, [r7, #12] 800ea24: f893 3020 ldrb.w r3, [r3, #32] 800ea28: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || 800ea2a: 7dfb ldrb r3, [r7, #23] 800ea2c: 2b01 cmp r3, #1 800ea2e: d003 beq.n 800ea38 800ea30: 7dfb ldrb r3, [r7, #23] 800ea32: 2b02 cmp r3, #2 800ea34: f040 8103 bne.w 800ec3e (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800ea38: 68bb ldr r3, [r7, #8] 800ea3a: 2b00 cmp r3, #0 800ea3c: d10e bne.n 800ea5c { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) 800ea3e: 68fb ldr r3, [r7, #12] 800ea40: 681b ldr r3, [r3, #0] 800ea42: 68db ldr r3, [r3, #12] 800ea44: f003 0303 and.w r3, r3, #3 800ea48: 2b00 cmp r3, #0 800ea4a: d116 bne.n 800ea7a { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800ea4c: 68fb ldr r3, [r7, #12] 800ea4e: 6a5b ldr r3, [r3, #36] @ 0x24 800ea50: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800ea54: 68fb ldr r3, [r7, #12] 800ea56: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ea58: 2301 movs r3, #1 800ea5a: e0f7 b.n 800ec4c } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) 800ea5c: 68fb ldr r3, [r7, #12] 800ea5e: 681b ldr r3, [r3, #0] 800ea60: 691b ldr r3, [r3, #16] 800ea62: f003 0303 and.w r3, r3, #3 800ea66: 2b00 cmp r3, #0 800ea68: d107 bne.n 800ea7a { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800ea6a: 68fb ldr r3, [r7, #12] 800ea6c: 6a5b ldr r3, [r3, #36] @ 0x24 800ea6e: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800ea72: 68fb ldr r3, [r7, #12] 800ea74: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ea76: 2301 movs r3, #1 800ea78: e0e8 b.n 800ec4c } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; 800ea7a: 68fb ldr r3, [r7, #12] 800ea7c: 681a ldr r2, [r3, #0] 800ea7e: 68bb ldr r3, [r7, #8] 800ea80: 331b adds r3, #27 800ea82: 011b lsls r3, r3, #4 800ea84: 4413 add r3, r2 800ea86: 681b ldr r3, [r3, #0] 800ea88: f003 0204 and.w r2, r3, #4 800ea8c: 687b ldr r3, [r7, #4] 800ea8e: 609a str r2, [r3, #8] if (pHeader->IDE == CAN_ID_STD) 800ea90: 687b ldr r3, [r7, #4] 800ea92: 689b ldr r3, [r3, #8] 800ea94: 2b00 cmp r3, #0 800ea96: d10c bne.n 800eab2 { pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; 800ea98: 68fb ldr r3, [r7, #12] 800ea9a: 681a ldr r2, [r3, #0] 800ea9c: 68bb ldr r3, [r7, #8] 800ea9e: 331b adds r3, #27 800eaa0: 011b lsls r3, r3, #4 800eaa2: 4413 add r3, r2 800eaa4: 681b ldr r3, [r3, #0] 800eaa6: 0d5b lsrs r3, r3, #21 800eaa8: f3c3 020a ubfx r2, r3, #0, #11 800eaac: 687b ldr r3, [r7, #4] 800eaae: 601a str r2, [r3, #0] 800eab0: e00b b.n 800eaca } else { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; 800eab2: 68fb ldr r3, [r7, #12] 800eab4: 681a ldr r2, [r3, #0] 800eab6: 68bb ldr r3, [r7, #8] 800eab8: 331b adds r3, #27 800eaba: 011b lsls r3, r3, #4 800eabc: 4413 add r3, r2 800eabe: 681b ldr r3, [r3, #0] 800eac0: 08db lsrs r3, r3, #3 800eac2: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & 800eac6: 687b ldr r3, [r7, #4] 800eac8: 605a str r2, [r3, #4] } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); 800eaca: 68fb ldr r3, [r7, #12] 800eacc: 681a ldr r2, [r3, #0] 800eace: 68bb ldr r3, [r7, #8] 800ead0: 331b adds r3, #27 800ead2: 011b lsls r3, r3, #4 800ead4: 4413 add r3, r2 800ead6: 681b ldr r3, [r3, #0] 800ead8: f003 0202 and.w r2, r3, #2 800eadc: 687b ldr r3, [r7, #4] 800eade: 60da str r2, [r3, #12] if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) 800eae0: 68fb ldr r3, [r7, #12] 800eae2: 681a ldr r2, [r3, #0] 800eae4: 68bb ldr r3, [r7, #8] 800eae6: 331b adds r3, #27 800eae8: 011b lsls r3, r3, #4 800eaea: 4413 add r3, r2 800eaec: 3304 adds r3, #4 800eaee: 681b ldr r3, [r3, #0] 800eaf0: f003 0308 and.w r3, r3, #8 800eaf4: 2b00 cmp r3, #0 800eaf6: d003 beq.n 800eb00 { /* Truncate DLC to 8 if received field is over range */ pHeader->DLC = 8U; 800eaf8: 687b ldr r3, [r7, #4] 800eafa: 2208 movs r2, #8 800eafc: 611a str r2, [r3, #16] 800eafe: e00b b.n 800eb18 } else { pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; 800eb00: 68fb ldr r3, [r7, #12] 800eb02: 681a ldr r2, [r3, #0] 800eb04: 68bb ldr r3, [r7, #8] 800eb06: 331b adds r3, #27 800eb08: 011b lsls r3, r3, #4 800eb0a: 4413 add r3, r2 800eb0c: 3304 adds r3, #4 800eb0e: 681b ldr r3, [r3, #0] 800eb10: f003 020f and.w r2, r3, #15 800eb14: 687b ldr r3, [r7, #4] 800eb16: 611a str r2, [r3, #16] } pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; 800eb18: 68fb ldr r3, [r7, #12] 800eb1a: 681a ldr r2, [r3, #0] 800eb1c: 68bb ldr r3, [r7, #8] 800eb1e: 331b adds r3, #27 800eb20: 011b lsls r3, r3, #4 800eb22: 4413 add r3, r2 800eb24: 3304 adds r3, #4 800eb26: 681b ldr r3, [r3, #0] 800eb28: 0a1b lsrs r3, r3, #8 800eb2a: b2da uxtb r2, r3 800eb2c: 687b ldr r3, [r7, #4] 800eb2e: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; 800eb30: 68fb ldr r3, [r7, #12] 800eb32: 681a ldr r2, [r3, #0] 800eb34: 68bb ldr r3, [r7, #8] 800eb36: 331b adds r3, #27 800eb38: 011b lsls r3, r3, #4 800eb3a: 4413 add r3, r2 800eb3c: 3304 adds r3, #4 800eb3e: 681b ldr r3, [r3, #0] 800eb40: 0c1b lsrs r3, r3, #16 800eb42: b29a uxth r2, r3 800eb44: 687b ldr r3, [r7, #4] 800eb46: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); 800eb48: 68fb ldr r3, [r7, #12] 800eb4a: 681a ldr r2, [r3, #0] 800eb4c: 68bb ldr r3, [r7, #8] 800eb4e: 011b lsls r3, r3, #4 800eb50: 4413 add r3, r2 800eb52: f503 73dc add.w r3, r3, #440 @ 0x1b8 800eb56: 681b ldr r3, [r3, #0] 800eb58: b2da uxtb r2, r3 800eb5a: 683b ldr r3, [r7, #0] 800eb5c: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); 800eb5e: 68fb ldr r3, [r7, #12] 800eb60: 681a ldr r2, [r3, #0] 800eb62: 68bb ldr r3, [r7, #8] 800eb64: 011b lsls r3, r3, #4 800eb66: 4413 add r3, r2 800eb68: f503 73dc add.w r3, r3, #440 @ 0x1b8 800eb6c: 681b ldr r3, [r3, #0] 800eb6e: 0a1a lsrs r2, r3, #8 800eb70: 683b ldr r3, [r7, #0] 800eb72: 3301 adds r3, #1 800eb74: b2d2 uxtb r2, r2 800eb76: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); 800eb78: 68fb ldr r3, [r7, #12] 800eb7a: 681a ldr r2, [r3, #0] 800eb7c: 68bb ldr r3, [r7, #8] 800eb7e: 011b lsls r3, r3, #4 800eb80: 4413 add r3, r2 800eb82: f503 73dc add.w r3, r3, #440 @ 0x1b8 800eb86: 681b ldr r3, [r3, #0] 800eb88: 0c1a lsrs r2, r3, #16 800eb8a: 683b ldr r3, [r7, #0] 800eb8c: 3302 adds r3, #2 800eb8e: b2d2 uxtb r2, r2 800eb90: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); 800eb92: 68fb ldr r3, [r7, #12] 800eb94: 681a ldr r2, [r3, #0] 800eb96: 68bb ldr r3, [r7, #8] 800eb98: 011b lsls r3, r3, #4 800eb9a: 4413 add r3, r2 800eb9c: f503 73dc add.w r3, r3, #440 @ 0x1b8 800eba0: 681b ldr r3, [r3, #0] 800eba2: 0e1a lsrs r2, r3, #24 800eba4: 683b ldr r3, [r7, #0] 800eba6: 3303 adds r3, #3 800eba8: b2d2 uxtb r2, r2 800ebaa: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); 800ebac: 68fb ldr r3, [r7, #12] 800ebae: 681a ldr r2, [r3, #0] 800ebb0: 68bb ldr r3, [r7, #8] 800ebb2: 011b lsls r3, r3, #4 800ebb4: 4413 add r3, r2 800ebb6: f503 73de add.w r3, r3, #444 @ 0x1bc 800ebba: 681a ldr r2, [r3, #0] 800ebbc: 683b ldr r3, [r7, #0] 800ebbe: 3304 adds r3, #4 800ebc0: b2d2 uxtb r2, r2 800ebc2: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); 800ebc4: 68fb ldr r3, [r7, #12] 800ebc6: 681a ldr r2, [r3, #0] 800ebc8: 68bb ldr r3, [r7, #8] 800ebca: 011b lsls r3, r3, #4 800ebcc: 4413 add r3, r2 800ebce: f503 73de add.w r3, r3, #444 @ 0x1bc 800ebd2: 681b ldr r3, [r3, #0] 800ebd4: 0a1a lsrs r2, r3, #8 800ebd6: 683b ldr r3, [r7, #0] 800ebd8: 3305 adds r3, #5 800ebda: b2d2 uxtb r2, r2 800ebdc: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); 800ebde: 68fb ldr r3, [r7, #12] 800ebe0: 681a ldr r2, [r3, #0] 800ebe2: 68bb ldr r3, [r7, #8] 800ebe4: 011b lsls r3, r3, #4 800ebe6: 4413 add r3, r2 800ebe8: f503 73de add.w r3, r3, #444 @ 0x1bc 800ebec: 681b ldr r3, [r3, #0] 800ebee: 0c1a lsrs r2, r3, #16 800ebf0: 683b ldr r3, [r7, #0] 800ebf2: 3306 adds r3, #6 800ebf4: b2d2 uxtb r2, r2 800ebf6: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); 800ebf8: 68fb ldr r3, [r7, #12] 800ebfa: 681a ldr r2, [r3, #0] 800ebfc: 68bb ldr r3, [r7, #8] 800ebfe: 011b lsls r3, r3, #4 800ec00: 4413 add r3, r2 800ec02: f503 73de add.w r3, r3, #444 @ 0x1bc 800ec06: 681b ldr r3, [r3, #0] 800ec08: 0e1a lsrs r2, r3, #24 800ec0a: 683b ldr r3, [r7, #0] 800ec0c: 3307 adds r3, #7 800ec0e: b2d2 uxtb r2, r2 800ec10: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800ec12: 68bb ldr r3, [r7, #8] 800ec14: 2b00 cmp r3, #0 800ec16: d108 bne.n 800ec2a { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); 800ec18: 68fb ldr r3, [r7, #12] 800ec1a: 681b ldr r3, [r3, #0] 800ec1c: 68da ldr r2, [r3, #12] 800ec1e: 68fb ldr r3, [r7, #12] 800ec20: 681b ldr r3, [r3, #0] 800ec22: f042 0220 orr.w r2, r2, #32 800ec26: 60da str r2, [r3, #12] 800ec28: e007 b.n 800ec3a } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); 800ec2a: 68fb ldr r3, [r7, #12] 800ec2c: 681b ldr r3, [r3, #0] 800ec2e: 691a ldr r2, [r3, #16] 800ec30: 68fb ldr r3, [r7, #12] 800ec32: 681b ldr r3, [r3, #0] 800ec34: f042 0220 orr.w r2, r2, #32 800ec38: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; 800ec3a: 2300 movs r3, #0 800ec3c: e006 b.n 800ec4c } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800ec3e: 68fb ldr r3, [r7, #12] 800ec40: 6a5b ldr r3, [r3, #36] @ 0x24 800ec42: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800ec46: 68fb ldr r3, [r7, #12] 800ec48: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ec4a: 2301 movs r3, #1 } } 800ec4c: 4618 mov r0, r3 800ec4e: 371c adds r7, #28 800ec50: 46bd mov sp, r7 800ec52: bc80 pop {r7} 800ec54: 4770 bx lr 0800ec56 : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { 800ec56: b480 push {r7} 800ec58: b085 sub sp, #20 800ec5a: af00 add r7, sp, #0 800ec5c: 6078 str r0, [r7, #4] 800ec5e: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800ec60: 687b ldr r3, [r7, #4] 800ec62: f893 3020 ldrb.w r3, [r3, #32] 800ec66: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || 800ec68: 7bfb ldrb r3, [r7, #15] 800ec6a: 2b01 cmp r3, #1 800ec6c: d002 beq.n 800ec74 800ec6e: 7bfb ldrb r3, [r7, #15] 800ec70: 2b02 cmp r3, #2 800ec72: d109 bne.n 800ec88 (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); 800ec74: 687b ldr r3, [r7, #4] 800ec76: 681b ldr r3, [r3, #0] 800ec78: 6959 ldr r1, [r3, #20] 800ec7a: 687b ldr r3, [r7, #4] 800ec7c: 681b ldr r3, [r3, #0] 800ec7e: 683a ldr r2, [r7, #0] 800ec80: 430a orrs r2, r1 800ec82: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; 800ec84: 2300 movs r3, #0 800ec86: e006 b.n 800ec96 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800ec88: 687b ldr r3, [r7, #4] 800ec8a: 6a5b ldr r3, [r3, #36] @ 0x24 800ec8c: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800ec90: 687b ldr r3, [r7, #4] 800ec92: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ec94: 2301 movs r3, #1 } } 800ec96: 4618 mov r0, r3 800ec98: 3714 adds r7, #20 800ec9a: 46bd mov sp, r7 800ec9c: bc80 pop {r7} 800ec9e: 4770 bx lr 0800eca0 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { 800eca0: b580 push {r7, lr} 800eca2: b08a sub sp, #40 @ 0x28 800eca4: af00 add r7, sp, #0 800eca6: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; 800eca8: 2300 movs r3, #0 800ecaa: 627b str r3, [r7, #36] @ 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); 800ecac: 687b ldr r3, [r7, #4] 800ecae: 681b ldr r3, [r3, #0] 800ecb0: 695b ldr r3, [r3, #20] 800ecb2: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); 800ecb4: 687b ldr r3, [r7, #4] 800ecb6: 681b ldr r3, [r3, #0] 800ecb8: 685b ldr r3, [r3, #4] 800ecba: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); 800ecbc: 687b ldr r3, [r7, #4] 800ecbe: 681b ldr r3, [r3, #0] 800ecc0: 689b ldr r3, [r3, #8] 800ecc2: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); 800ecc4: 687b ldr r3, [r7, #4] 800ecc6: 681b ldr r3, [r3, #0] 800ecc8: 68db ldr r3, [r3, #12] 800ecca: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); 800eccc: 687b ldr r3, [r7, #4] 800ecce: 681b ldr r3, [r3, #0] 800ecd0: 691b ldr r3, [r3, #16] 800ecd2: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); 800ecd4: 687b ldr r3, [r7, #4] 800ecd6: 681b ldr r3, [r3, #0] 800ecd8: 699b ldr r3, [r3, #24] 800ecda: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) 800ecdc: 6a3b ldr r3, [r7, #32] 800ecde: f003 0301 and.w r3, r3, #1 800ece2: 2b00 cmp r3, #0 800ece4: d07c beq.n 800ede0 { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) 800ece6: 69bb ldr r3, [r7, #24] 800ece8: f003 0301 and.w r3, r3, #1 800ecec: 2b00 cmp r3, #0 800ecee: d023 beq.n 800ed38 { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); 800ecf0: 687b ldr r3, [r7, #4] 800ecf2: 681b ldr r3, [r3, #0] 800ecf4: 2201 movs r2, #1 800ecf6: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) 800ecf8: 69bb ldr r3, [r7, #24] 800ecfa: f003 0302 and.w r3, r3, #2 800ecfe: 2b00 cmp r3, #0 800ed00: d003 beq.n 800ed0a #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); 800ed02: 6878 ldr r0, [r7, #4] 800ed04: f000 f983 bl 800f00e 800ed08: e016 b.n 800ed38 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) 800ed0a: 69bb ldr r3, [r7, #24] 800ed0c: f003 0304 and.w r3, r3, #4 800ed10: 2b00 cmp r3, #0 800ed12: d004 beq.n 800ed1e { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; 800ed14: 6a7b ldr r3, [r7, #36] @ 0x24 800ed16: f443 6300 orr.w r3, r3, #2048 @ 0x800 800ed1a: 627b str r3, [r7, #36] @ 0x24 800ed1c: e00c b.n 800ed38 } else if ((tsrflags & CAN_TSR_TERR0) != 0U) 800ed1e: 69bb ldr r3, [r7, #24] 800ed20: f003 0308 and.w r3, r3, #8 800ed24: 2b00 cmp r3, #0 800ed26: d004 beq.n 800ed32 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; 800ed28: 6a7b ldr r3, [r7, #36] @ 0x24 800ed2a: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800ed2e: 627b str r3, [r7, #36] @ 0x24 800ed30: e002 b.n 800ed38 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); 800ed32: 6878 ldr r0, [r7, #4] 800ed34: f000 f986 bl 800f044 } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) 800ed38: 69bb ldr r3, [r7, #24] 800ed3a: f403 7380 and.w r3, r3, #256 @ 0x100 800ed3e: 2b00 cmp r3, #0 800ed40: d024 beq.n 800ed8c { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); 800ed42: 687b ldr r3, [r7, #4] 800ed44: 681b ldr r3, [r3, #0] 800ed46: f44f 7280 mov.w r2, #256 @ 0x100 800ed4a: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) 800ed4c: 69bb ldr r3, [r7, #24] 800ed4e: f403 7300 and.w r3, r3, #512 @ 0x200 800ed52: 2b00 cmp r3, #0 800ed54: d003 beq.n 800ed5e #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); 800ed56: 6878 ldr r0, [r7, #4] 800ed58: f000 f962 bl 800f020 800ed5c: e016 b.n 800ed8c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) 800ed5e: 69bb ldr r3, [r7, #24] 800ed60: f403 6380 and.w r3, r3, #1024 @ 0x400 800ed64: 2b00 cmp r3, #0 800ed66: d004 beq.n 800ed72 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; 800ed68: 6a7b ldr r3, [r7, #36] @ 0x24 800ed6a: f443 5300 orr.w r3, r3, #8192 @ 0x2000 800ed6e: 627b str r3, [r7, #36] @ 0x24 800ed70: e00c b.n 800ed8c } else if ((tsrflags & CAN_TSR_TERR1) != 0U) 800ed72: 69bb ldr r3, [r7, #24] 800ed74: f403 6300 and.w r3, r3, #2048 @ 0x800 800ed78: 2b00 cmp r3, #0 800ed7a: d004 beq.n 800ed86 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; 800ed7c: 6a7b ldr r3, [r7, #36] @ 0x24 800ed7e: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800ed82: 627b str r3, [r7, #36] @ 0x24 800ed84: e002 b.n 800ed8c #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); 800ed86: 6878 ldr r0, [r7, #4] 800ed88: f000 f965 bl 800f056 } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) 800ed8c: 69bb ldr r3, [r7, #24] 800ed8e: f403 3380 and.w r3, r3, #65536 @ 0x10000 800ed92: 2b00 cmp r3, #0 800ed94: d024 beq.n 800ede0 { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); 800ed96: 687b ldr r3, [r7, #4] 800ed98: 681b ldr r3, [r3, #0] 800ed9a: f44f 3280 mov.w r2, #65536 @ 0x10000 800ed9e: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) 800eda0: 69bb ldr r3, [r7, #24] 800eda2: f403 3300 and.w r3, r3, #131072 @ 0x20000 800eda6: 2b00 cmp r3, #0 800eda8: d003 beq.n 800edb2 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); 800edaa: 6878 ldr r0, [r7, #4] 800edac: f000 f941 bl 800f032 800edb0: e016 b.n 800ede0 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) 800edb2: 69bb ldr r3, [r7, #24] 800edb4: f403 2380 and.w r3, r3, #262144 @ 0x40000 800edb8: 2b00 cmp r3, #0 800edba: d004 beq.n 800edc6 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; 800edbc: 6a7b ldr r3, [r7, #36] @ 0x24 800edbe: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800edc2: 627b str r3, [r7, #36] @ 0x24 800edc4: e00c b.n 800ede0 } else if ((tsrflags & CAN_TSR_TERR2) != 0U) 800edc6: 69bb ldr r3, [r7, #24] 800edc8: f403 2300 and.w r3, r3, #524288 @ 0x80000 800edcc: 2b00 cmp r3, #0 800edce: d004 beq.n 800edda { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; 800edd0: 6a7b ldr r3, [r7, #36] @ 0x24 800edd2: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800edd6: 627b str r3, [r7, #36] @ 0x24 800edd8: e002 b.n 800ede0 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); 800edda: 6878 ldr r0, [r7, #4] 800eddc: f000 f944 bl 800f068 } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) 800ede0: 6a3b ldr r3, [r7, #32] 800ede2: f003 0308 and.w r3, r3, #8 800ede6: 2b00 cmp r3, #0 800ede8: d00c beq.n 800ee04 { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) 800edea: 697b ldr r3, [r7, #20] 800edec: f003 0310 and.w r3, r3, #16 800edf0: 2b00 cmp r3, #0 800edf2: d007 beq.n 800ee04 { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; 800edf4: 6a7b ldr r3, [r7, #36] @ 0x24 800edf6: f443 7300 orr.w r3, r3, #512 @ 0x200 800edfa: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); 800edfc: 687b ldr r3, [r7, #4] 800edfe: 681b ldr r3, [r3, #0] 800ee00: 2210 movs r2, #16 800ee02: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) 800ee04: 6a3b ldr r3, [r7, #32] 800ee06: f003 0304 and.w r3, r3, #4 800ee0a: 2b00 cmp r3, #0 800ee0c: d00b beq.n 800ee26 { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) 800ee0e: 697b ldr r3, [r7, #20] 800ee10: f003 0308 and.w r3, r3, #8 800ee14: 2b00 cmp r3, #0 800ee16: d006 beq.n 800ee26 { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); 800ee18: 687b ldr r3, [r7, #4] 800ee1a: 681b ldr r3, [r3, #0] 800ee1c: 2208 movs r2, #8 800ee1e: 60da str r2, [r3, #12] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); 800ee20: 6878 ldr r0, [r7, #4] 800ee22: f000 f933 bl 800f08c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) 800ee26: 6a3b ldr r3, [r7, #32] 800ee28: f003 0302 and.w r3, r3, #2 800ee2c: 2b00 cmp r3, #0 800ee2e: d009 beq.n 800ee44 { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) 800ee30: 687b ldr r3, [r7, #4] 800ee32: 681b ldr r3, [r3, #0] 800ee34: 68db ldr r3, [r3, #12] 800ee36: f003 0303 and.w r3, r3, #3 800ee3a: 2b00 cmp r3, #0 800ee3c: d002 beq.n 800ee44 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); 800ee3e: 6878 ldr r0, [r7, #4] 800ee40: f000 f91b bl 800f07a #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) 800ee44: 6a3b ldr r3, [r7, #32] 800ee46: f003 0340 and.w r3, r3, #64 @ 0x40 800ee4a: 2b00 cmp r3, #0 800ee4c: d00c beq.n 800ee68 { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) 800ee4e: 693b ldr r3, [r7, #16] 800ee50: f003 0310 and.w r3, r3, #16 800ee54: 2b00 cmp r3, #0 800ee56: d007 beq.n 800ee68 { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; 800ee58: 6a7b ldr r3, [r7, #36] @ 0x24 800ee5a: f443 6380 orr.w r3, r3, #1024 @ 0x400 800ee5e: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); 800ee60: 687b ldr r3, [r7, #4] 800ee62: 681b ldr r3, [r3, #0] 800ee64: 2210 movs r2, #16 800ee66: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) 800ee68: 6a3b ldr r3, [r7, #32] 800ee6a: f003 0320 and.w r3, r3, #32 800ee6e: 2b00 cmp r3, #0 800ee70: d00b beq.n 800ee8a { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) 800ee72: 693b ldr r3, [r7, #16] 800ee74: f003 0308 and.w r3, r3, #8 800ee78: 2b00 cmp r3, #0 800ee7a: d006 beq.n 800ee8a { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); 800ee7c: 687b ldr r3, [r7, #4] 800ee7e: 681b ldr r3, [r3, #0] 800ee80: 2208 movs r2, #8 800ee82: 611a str r2, [r3, #16] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); 800ee84: 6878 ldr r0, [r7, #4] 800ee86: f000 f90a bl 800f09e #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) 800ee8a: 6a3b ldr r3, [r7, #32] 800ee8c: f003 0310 and.w r3, r3, #16 800ee90: 2b00 cmp r3, #0 800ee92: d009 beq.n 800eea8 { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) 800ee94: 687b ldr r3, [r7, #4] 800ee96: 681b ldr r3, [r3, #0] 800ee98: 691b ldr r3, [r3, #16] 800ee9a: f003 0303 and.w r3, r3, #3 800ee9e: 2b00 cmp r3, #0 800eea0: d002 beq.n 800eea8 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); 800eea2: 6878 ldr r0, [r7, #4] 800eea4: f7fb fe34 bl 800ab10 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) 800eea8: 6a3b ldr r3, [r7, #32] 800eeaa: f403 3300 and.w r3, r3, #131072 @ 0x20000 800eeae: 2b00 cmp r3, #0 800eeb0: d00b beq.n 800eeca { if ((msrflags & CAN_MSR_SLAKI) != 0U) 800eeb2: 69fb ldr r3, [r7, #28] 800eeb4: f003 0310 and.w r3, r3, #16 800eeb8: 2b00 cmp r3, #0 800eeba: d006 beq.n 800eeca { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); 800eebc: 687b ldr r3, [r7, #4] 800eebe: 681b ldr r3, [r3, #0] 800eec0: 2210 movs r2, #16 800eec2: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->SleepCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); 800eec4: 6878 ldr r0, [r7, #4] 800eec6: f000 f8f3 bl 800f0b0 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ if ((interrupts & CAN_IT_WAKEUP) != 0U) 800eeca: 6a3b ldr r3, [r7, #32] 800eecc: f403 3380 and.w r3, r3, #65536 @ 0x10000 800eed0: 2b00 cmp r3, #0 800eed2: d00b beq.n 800eeec { if ((msrflags & CAN_MSR_WKUI) != 0U) 800eed4: 69fb ldr r3, [r7, #28] 800eed6: f003 0308 and.w r3, r3, #8 800eeda: 2b00 cmp r3, #0 800eedc: d006 beq.n 800eeec { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); 800eede: 687b ldr r3, [r7, #4] 800eee0: 681b ldr r3, [r3, #0] 800eee2: 2208 movs r2, #8 800eee4: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->WakeUpFromRxMsgCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); 800eee6: 6878 ldr r0, [r7, #4] 800eee8: f000 f8eb bl 800f0c2 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ if ((interrupts & CAN_IT_ERROR) != 0U) 800eeec: 6a3b ldr r3, [r7, #32] 800eeee: f403 4300 and.w r3, r3, #32768 @ 0x8000 800eef2: 2b00 cmp r3, #0 800eef4: d07b beq.n 800efee { if ((msrflags & CAN_MSR_ERRI) != 0U) 800eef6: 69fb ldr r3, [r7, #28] 800eef8: f003 0304 and.w r3, r3, #4 800eefc: 2b00 cmp r3, #0 800eefe: d072 beq.n 800efe6 { /* Check Error Warning Flag */ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800ef00: 6a3b ldr r3, [r7, #32] 800ef02: f403 7380 and.w r3, r3, #256 @ 0x100 800ef06: 2b00 cmp r3, #0 800ef08: d008 beq.n 800ef1c ((esrflags & CAN_ESR_EWGF) != 0U)) 800ef0a: 68fb ldr r3, [r7, #12] 800ef0c: f003 0301 and.w r3, r3, #1 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800ef10: 2b00 cmp r3, #0 800ef12: d003 beq.n 800ef1c { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; 800ef14: 6a7b ldr r3, [r7, #36] @ 0x24 800ef16: f043 0301 orr.w r3, r3, #1 800ef1a: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Warning Flag as read-only */ } /* Check Error Passive Flag */ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800ef1c: 6a3b ldr r3, [r7, #32] 800ef1e: f403 7300 and.w r3, r3, #512 @ 0x200 800ef22: 2b00 cmp r3, #0 800ef24: d008 beq.n 800ef38 ((esrflags & CAN_ESR_EPVF) != 0U)) 800ef26: 68fb ldr r3, [r7, #12] 800ef28: f003 0302 and.w r3, r3, #2 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800ef2c: 2b00 cmp r3, #0 800ef2e: d003 beq.n 800ef38 { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; 800ef30: 6a7b ldr r3, [r7, #36] @ 0x24 800ef32: f043 0302 orr.w r3, r3, #2 800ef36: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-off Flag */ if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800ef38: 6a3b ldr r3, [r7, #32] 800ef3a: f403 6380 and.w r3, r3, #1024 @ 0x400 800ef3e: 2b00 cmp r3, #0 800ef40: d008 beq.n 800ef54 ((esrflags & CAN_ESR_BOFF) != 0U)) 800ef42: 68fb ldr r3, [r7, #12] 800ef44: f003 0304 and.w r3, r3, #4 if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800ef48: 2b00 cmp r3, #0 800ef4a: d003 beq.n 800ef54 { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; 800ef4c: 6a7b ldr r3, [r7, #36] @ 0x24 800ef4e: f043 0304 orr.w r3, r3, #4 800ef52: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Bus-Off as read-only */ } /* Check Last Error Code Flag */ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800ef54: 6a3b ldr r3, [r7, #32] 800ef56: f403 6300 and.w r3, r3, #2048 @ 0x800 800ef5a: 2b00 cmp r3, #0 800ef5c: d043 beq.n 800efe6 ((esrflags & CAN_ESR_LEC) != 0U)) 800ef5e: 68fb ldr r3, [r7, #12] 800ef60: f003 0370 and.w r3, r3, #112 @ 0x70 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800ef64: 2b00 cmp r3, #0 800ef66: d03e beq.n 800efe6 { switch (esrflags & CAN_ESR_LEC) 800ef68: 68fb ldr r3, [r7, #12] 800ef6a: f003 0370 and.w r3, r3, #112 @ 0x70 800ef6e: 2b60 cmp r3, #96 @ 0x60 800ef70: d02b beq.n 800efca 800ef72: 2b60 cmp r3, #96 @ 0x60 800ef74: d82e bhi.n 800efd4 800ef76: 2b50 cmp r3, #80 @ 0x50 800ef78: d022 beq.n 800efc0 800ef7a: 2b50 cmp r3, #80 @ 0x50 800ef7c: d82a bhi.n 800efd4 800ef7e: 2b40 cmp r3, #64 @ 0x40 800ef80: d019 beq.n 800efb6 800ef82: 2b40 cmp r3, #64 @ 0x40 800ef84: d826 bhi.n 800efd4 800ef86: 2b30 cmp r3, #48 @ 0x30 800ef88: d010 beq.n 800efac 800ef8a: 2b30 cmp r3, #48 @ 0x30 800ef8c: d822 bhi.n 800efd4 800ef8e: 2b10 cmp r3, #16 800ef90: d002 beq.n 800ef98 800ef92: 2b20 cmp r3, #32 800ef94: d005 beq.n 800efa2 case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): /* Set CAN error code to CRC error */ errorcode |= HAL_CAN_ERROR_CRC; break; default: break; 800ef96: e01d b.n 800efd4 errorcode |= HAL_CAN_ERROR_STF; 800ef98: 6a7b ldr r3, [r7, #36] @ 0x24 800ef9a: f043 0308 orr.w r3, r3, #8 800ef9e: 627b str r3, [r7, #36] @ 0x24 break; 800efa0: e019 b.n 800efd6 errorcode |= HAL_CAN_ERROR_FOR; 800efa2: 6a7b ldr r3, [r7, #36] @ 0x24 800efa4: f043 0310 orr.w r3, r3, #16 800efa8: 627b str r3, [r7, #36] @ 0x24 break; 800efaa: e014 b.n 800efd6 errorcode |= HAL_CAN_ERROR_ACK; 800efac: 6a7b ldr r3, [r7, #36] @ 0x24 800efae: f043 0320 orr.w r3, r3, #32 800efb2: 627b str r3, [r7, #36] @ 0x24 break; 800efb4: e00f b.n 800efd6 errorcode |= HAL_CAN_ERROR_BR; 800efb6: 6a7b ldr r3, [r7, #36] @ 0x24 800efb8: f043 0340 orr.w r3, r3, #64 @ 0x40 800efbc: 627b str r3, [r7, #36] @ 0x24 break; 800efbe: e00a b.n 800efd6 errorcode |= HAL_CAN_ERROR_BD; 800efc0: 6a7b ldr r3, [r7, #36] @ 0x24 800efc2: f043 0380 orr.w r3, r3, #128 @ 0x80 800efc6: 627b str r3, [r7, #36] @ 0x24 break; 800efc8: e005 b.n 800efd6 errorcode |= HAL_CAN_ERROR_CRC; 800efca: 6a7b ldr r3, [r7, #36] @ 0x24 800efcc: f443 7380 orr.w r3, r3, #256 @ 0x100 800efd0: 627b str r3, [r7, #36] @ 0x24 break; 800efd2: e000 b.n 800efd6 break; 800efd4: bf00 nop } /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); 800efd6: 687b ldr r3, [r7, #4] 800efd8: 681b ldr r3, [r3, #0] 800efda: 699a ldr r2, [r3, #24] 800efdc: 687b ldr r3, [r7, #4] 800efde: 681b ldr r3, [r3, #0] 800efe0: f022 0270 bic.w r2, r2, #112 @ 0x70 800efe4: 619a str r2, [r3, #24] } } /* Clear ERRI Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); 800efe6: 687b ldr r3, [r7, #4] 800efe8: 681b ldr r3, [r3, #0] 800efea: 2204 movs r2, #4 800efec: 605a str r2, [r3, #4] } /* Call the Error call Back in case of Errors */ if (errorcode != HAL_CAN_ERROR_NONE) 800efee: 6a7b ldr r3, [r7, #36] @ 0x24 800eff0: 2b00 cmp r3, #0 800eff2: d008 beq.n 800f006 { /* Update error code in handle */ hcan->ErrorCode |= errorcode; 800eff4: 687b ldr r3, [r7, #4] 800eff6: 6a5a ldr r2, [r3, #36] @ 0x24 800eff8: 6a7b ldr r3, [r7, #36] @ 0x24 800effa: 431a orrs r2, r3 800effc: 687b ldr r3, [r7, #4] 800effe: 625a str r2, [r3, #36] @ 0x24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->ErrorCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); 800f000: 6878 ldr r0, [r7, #4] 800f002: f000 f867 bl 800f0d4 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } 800f006: bf00 nop 800f008: 3728 adds r7, #40 @ 0x28 800f00a: 46bd mov sp, r7 800f00c: bd80 pop {r7, pc} 0800f00e : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { 800f00e: b480 push {r7} 800f010: b083 sub sp, #12 800f012: af00 add r7, sp, #0 800f014: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the user file */ } 800f016: bf00 nop 800f018: 370c adds r7, #12 800f01a: 46bd mov sp, r7 800f01c: bc80 pop {r7} 800f01e: 4770 bx lr 0800f020 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { 800f020: b480 push {r7} 800f022: b083 sub sp, #12 800f024: af00 add r7, sp, #0 800f026: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the user file */ } 800f028: bf00 nop 800f02a: 370c adds r7, #12 800f02c: 46bd mov sp, r7 800f02e: bc80 pop {r7} 800f030: 4770 bx lr 0800f032 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) { 800f032: b480 push {r7} 800f034: b083 sub sp, #12 800f036: af00 add r7, sp, #0 800f038: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the user file */ } 800f03a: bf00 nop 800f03c: 370c adds r7, #12 800f03e: 46bd mov sp, r7 800f040: bc80 pop {r7} 800f042: 4770 bx lr 0800f044 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { 800f044: b480 push {r7} 800f046: b083 sub sp, #12 800f048: af00 add r7, sp, #0 800f04a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } 800f04c: bf00 nop 800f04e: 370c adds r7, #12 800f050: 46bd mov sp, r7 800f052: bc80 pop {r7} 800f054: 4770 bx lr 0800f056 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { 800f056: b480 push {r7} 800f058: b083 sub sp, #12 800f05a: af00 add r7, sp, #0 800f05c: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } 800f05e: bf00 nop 800f060: 370c adds r7, #12 800f062: 46bd mov sp, r7 800f064: bc80 pop {r7} 800f066: 4770 bx lr 0800f068 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { 800f068: b480 push {r7} 800f06a: b083 sub sp, #12 800f06c: af00 add r7, sp, #0 800f06e: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } 800f070: bf00 nop 800f072: 370c adds r7, #12 800f074: 46bd mov sp, r7 800f076: bc80 pop {r7} 800f078: 4770 bx lr 0800f07a : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { 800f07a: b480 push {r7} 800f07c: b083 sub sp, #12 800f07e: af00 add r7, sp, #0 800f080: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the user file */ } 800f082: bf00 nop 800f084: 370c adds r7, #12 800f086: 46bd mov sp, r7 800f088: bc80 pop {r7} 800f08a: 4770 bx lr 0800f08c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { 800f08c: b480 push {r7} 800f08e: b083 sub sp, #12 800f090: af00 add r7, sp, #0 800f092: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } 800f094: bf00 nop 800f096: 370c adds r7, #12 800f098: 46bd mov sp, r7 800f09a: bc80 pop {r7} 800f09c: 4770 bx lr 0800f09e : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { 800f09e: b480 push {r7} 800f0a0: b083 sub sp, #12 800f0a2: af00 add r7, sp, #0 800f0a4: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } 800f0a6: bf00 nop 800f0a8: 370c adds r7, #12 800f0aa: 46bd mov sp, r7 800f0ac: bc80 pop {r7} 800f0ae: 4770 bx lr 0800f0b0 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { 800f0b0: b480 push {r7} 800f0b2: b083 sub sp, #12 800f0b4: af00 add r7, sp, #0 800f0b6: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } 800f0b8: bf00 nop 800f0ba: 370c adds r7, #12 800f0bc: 46bd mov sp, r7 800f0be: bc80 pop {r7} 800f0c0: 4770 bx lr 0800f0c2 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { 800f0c2: b480 push {r7} 800f0c4: b083 sub sp, #12 800f0c6: af00 add r7, sp, #0 800f0c8: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } 800f0ca: bf00 nop 800f0cc: 370c adds r7, #12 800f0ce: 46bd mov sp, r7 800f0d0: bc80 pop {r7} 800f0d2: 4770 bx lr 0800f0d4 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { 800f0d4: b480 push {r7} 800f0d6: b083 sub sp, #12 800f0d8: af00 add r7, sp, #0 800f0da: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } 800f0dc: bf00 nop 800f0de: 370c adds r7, #12 800f0e0: 46bd mov sp, r7 800f0e2: bc80 pop {r7} 800f0e4: 4770 bx lr ... 0800f0e8 <__NVIC_SetPriorityGrouping>: { 800f0e8: b480 push {r7} 800f0ea: b085 sub sp, #20 800f0ec: af00 add r7, sp, #0 800f0ee: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800f0f0: 687b ldr r3, [r7, #4] 800f0f2: f003 0307 and.w r3, r3, #7 800f0f6: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 800f0f8: 4b0c ldr r3, [pc, #48] @ (800f12c <__NVIC_SetPriorityGrouping+0x44>) 800f0fa: 68db ldr r3, [r3, #12] 800f0fc: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800f0fe: 68ba ldr r2, [r7, #8] 800f100: f64f 03ff movw r3, #63743 @ 0xf8ff 800f104: 4013 ands r3, r2 800f106: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800f108: 68fb ldr r3, [r7, #12] 800f10a: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800f10c: 68bb ldr r3, [r7, #8] 800f10e: 4313 orrs r3, r2 reg_value = (reg_value | 800f110: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 800f114: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800f118: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800f11a: 4a04 ldr r2, [pc, #16] @ (800f12c <__NVIC_SetPriorityGrouping+0x44>) 800f11c: 68bb ldr r3, [r7, #8] 800f11e: 60d3 str r3, [r2, #12] } 800f120: bf00 nop 800f122: 3714 adds r7, #20 800f124: 46bd mov sp, r7 800f126: bc80 pop {r7} 800f128: 4770 bx lr 800f12a: bf00 nop 800f12c: e000ed00 .word 0xe000ed00 0800f130 <__NVIC_GetPriorityGrouping>: { 800f130: b480 push {r7} 800f132: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800f134: 4b04 ldr r3, [pc, #16] @ (800f148 <__NVIC_GetPriorityGrouping+0x18>) 800f136: 68db ldr r3, [r3, #12] 800f138: 0a1b lsrs r3, r3, #8 800f13a: f003 0307 and.w r3, r3, #7 } 800f13e: 4618 mov r0, r3 800f140: 46bd mov sp, r7 800f142: bc80 pop {r7} 800f144: 4770 bx lr 800f146: bf00 nop 800f148: e000ed00 .word 0xe000ed00 0800f14c <__NVIC_EnableIRQ>: { 800f14c: b480 push {r7} 800f14e: b083 sub sp, #12 800f150: af00 add r7, sp, #0 800f152: 4603 mov r3, r0 800f154: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800f156: f997 3007 ldrsb.w r3, [r7, #7] 800f15a: 2b00 cmp r3, #0 800f15c: db0b blt.n 800f176 <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800f15e: 79fb ldrb r3, [r7, #7] 800f160: f003 021f and.w r2, r3, #31 800f164: 4906 ldr r1, [pc, #24] @ (800f180 <__NVIC_EnableIRQ+0x34>) 800f166: f997 3007 ldrsb.w r3, [r7, #7] 800f16a: 095b lsrs r3, r3, #5 800f16c: 2001 movs r0, #1 800f16e: fa00 f202 lsl.w r2, r0, r2 800f172: f841 2023 str.w r2, [r1, r3, lsl #2] } 800f176: bf00 nop 800f178: 370c adds r7, #12 800f17a: 46bd mov sp, r7 800f17c: bc80 pop {r7} 800f17e: 4770 bx lr 800f180: e000e100 .word 0xe000e100 0800f184 <__NVIC_SetPriority>: { 800f184: b480 push {r7} 800f186: b083 sub sp, #12 800f188: af00 add r7, sp, #0 800f18a: 4603 mov r3, r0 800f18c: 6039 str r1, [r7, #0] 800f18e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800f190: f997 3007 ldrsb.w r3, [r7, #7] 800f194: 2b00 cmp r3, #0 800f196: db0a blt.n 800f1ae <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800f198: 683b ldr r3, [r7, #0] 800f19a: b2da uxtb r2, r3 800f19c: 490c ldr r1, [pc, #48] @ (800f1d0 <__NVIC_SetPriority+0x4c>) 800f19e: f997 3007 ldrsb.w r3, [r7, #7] 800f1a2: 0112 lsls r2, r2, #4 800f1a4: b2d2 uxtb r2, r2 800f1a6: 440b add r3, r1 800f1a8: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 800f1ac: e00a b.n 800f1c4 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800f1ae: 683b ldr r3, [r7, #0] 800f1b0: b2da uxtb r2, r3 800f1b2: 4908 ldr r1, [pc, #32] @ (800f1d4 <__NVIC_SetPriority+0x50>) 800f1b4: 79fb ldrb r3, [r7, #7] 800f1b6: f003 030f and.w r3, r3, #15 800f1ba: 3b04 subs r3, #4 800f1bc: 0112 lsls r2, r2, #4 800f1be: b2d2 uxtb r2, r2 800f1c0: 440b add r3, r1 800f1c2: 761a strb r2, [r3, #24] } 800f1c4: bf00 nop 800f1c6: 370c adds r7, #12 800f1c8: 46bd mov sp, r7 800f1ca: bc80 pop {r7} 800f1cc: 4770 bx lr 800f1ce: bf00 nop 800f1d0: e000e100 .word 0xe000e100 800f1d4: e000ed00 .word 0xe000ed00 0800f1d8 : { 800f1d8: b480 push {r7} 800f1da: b089 sub sp, #36 @ 0x24 800f1dc: af00 add r7, sp, #0 800f1de: 60f8 str r0, [r7, #12] 800f1e0: 60b9 str r1, [r7, #8] 800f1e2: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800f1e4: 68fb ldr r3, [r7, #12] 800f1e6: f003 0307 and.w r3, r3, #7 800f1ea: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 800f1ec: 69fb ldr r3, [r7, #28] 800f1ee: f1c3 0307 rsb r3, r3, #7 800f1f2: 2b04 cmp r3, #4 800f1f4: bf28 it cs 800f1f6: 2304 movcs r3, #4 800f1f8: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800f1fa: 69fb ldr r3, [r7, #28] 800f1fc: 3304 adds r3, #4 800f1fe: 2b06 cmp r3, #6 800f200: d902 bls.n 800f208 800f202: 69fb ldr r3, [r7, #28] 800f204: 3b03 subs r3, #3 800f206: e000 b.n 800f20a 800f208: 2300 movs r3, #0 800f20a: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800f20c: f04f 32ff mov.w r2, #4294967295 800f210: 69bb ldr r3, [r7, #24] 800f212: fa02 f303 lsl.w r3, r2, r3 800f216: 43da mvns r2, r3 800f218: 68bb ldr r3, [r7, #8] 800f21a: 401a ands r2, r3 800f21c: 697b ldr r3, [r7, #20] 800f21e: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800f220: f04f 31ff mov.w r1, #4294967295 800f224: 697b ldr r3, [r7, #20] 800f226: fa01 f303 lsl.w r3, r1, r3 800f22a: 43d9 mvns r1, r3 800f22c: 687b ldr r3, [r7, #4] 800f22e: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800f230: 4313 orrs r3, r2 } 800f232: 4618 mov r0, r3 800f234: 3724 adds r7, #36 @ 0x24 800f236: 46bd mov sp, r7 800f238: bc80 pop {r7} 800f23a: 4770 bx lr 0800f23c : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800f23c: b580 push {r7, lr} 800f23e: b082 sub sp, #8 800f240: af00 add r7, sp, #0 800f242: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 800f244: 687b ldr r3, [r7, #4] 800f246: 3b01 subs r3, #1 800f248: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800f24c: d301 bcc.n 800f252 { return (1UL); /* Reload value impossible */ 800f24e: 2301 movs r3, #1 800f250: e00f b.n 800f272 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800f252: 4a0a ldr r2, [pc, #40] @ (800f27c ) 800f254: 687b ldr r3, [r7, #4] 800f256: 3b01 subs r3, #1 800f258: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800f25a: 210f movs r1, #15 800f25c: f04f 30ff mov.w r0, #4294967295 800f260: f7ff ff90 bl 800f184 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800f264: 4b05 ldr r3, [pc, #20] @ (800f27c ) 800f266: 2200 movs r2, #0 800f268: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800f26a: 4b04 ldr r3, [pc, #16] @ (800f27c ) 800f26c: 2207 movs r2, #7 800f26e: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 800f270: 2300 movs r3, #0 } 800f272: 4618 mov r0, r3 800f274: 3708 adds r7, #8 800f276: 46bd mov sp, r7 800f278: bd80 pop {r7, pc} 800f27a: bf00 nop 800f27c: e000e010 .word 0xe000e010 0800f280 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 800f280: b580 push {r7, lr} 800f282: b082 sub sp, #8 800f284: af00 add r7, sp, #0 800f286: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800f288: 6878 ldr r0, [r7, #4] 800f28a: f7ff ff2d bl 800f0e8 <__NVIC_SetPriorityGrouping> } 800f28e: bf00 nop 800f290: 3708 adds r7, #8 800f292: 46bd mov sp, r7 800f294: bd80 pop {r7, pc} 0800f296 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800f296: b580 push {r7, lr} 800f298: b086 sub sp, #24 800f29a: af00 add r7, sp, #0 800f29c: 4603 mov r3, r0 800f29e: 60b9 str r1, [r7, #8] 800f2a0: 607a str r2, [r7, #4] 800f2a2: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 800f2a4: 2300 movs r3, #0 800f2a6: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800f2a8: f7ff ff42 bl 800f130 <__NVIC_GetPriorityGrouping> 800f2ac: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800f2ae: 687a ldr r2, [r7, #4] 800f2b0: 68b9 ldr r1, [r7, #8] 800f2b2: 6978 ldr r0, [r7, #20] 800f2b4: f7ff ff90 bl 800f1d8 800f2b8: 4602 mov r2, r0 800f2ba: f997 300f ldrsb.w r3, [r7, #15] 800f2be: 4611 mov r1, r2 800f2c0: 4618 mov r0, r3 800f2c2: f7ff ff5f bl 800f184 <__NVIC_SetPriority> } 800f2c6: bf00 nop 800f2c8: 3718 adds r7, #24 800f2ca: 46bd mov sp, r7 800f2cc: bd80 pop {r7, pc} 0800f2ce : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 800f2ce: b580 push {r7, lr} 800f2d0: b082 sub sp, #8 800f2d2: af00 add r7, sp, #0 800f2d4: 4603 mov r3, r0 800f2d6: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800f2d8: f997 3007 ldrsb.w r3, [r7, #7] 800f2dc: 4618 mov r0, r3 800f2de: f7ff ff35 bl 800f14c <__NVIC_EnableIRQ> } 800f2e2: bf00 nop 800f2e4: 3708 adds r7, #8 800f2e6: 46bd mov sp, r7 800f2e8: bd80 pop {r7, pc} 0800f2ea : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800f2ea: b580 push {r7, lr} 800f2ec: b082 sub sp, #8 800f2ee: af00 add r7, sp, #0 800f2f0: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800f2f2: 6878 ldr r0, [r7, #4] 800f2f4: f7ff ffa2 bl 800f23c 800f2f8: 4603 mov r3, r0 } 800f2fa: 4618 mov r0, r3 800f2fc: 3708 adds r7, #8 800f2fe: 46bd mov sp, r7 800f300: bd80 pop {r7, pc} 0800f302 : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 800f302: b580 push {r7, lr} 800f304: b082 sub sp, #8 800f306: af00 add r7, sp, #0 800f308: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 800f30a: 687b ldr r3, [r7, #4] 800f30c: 2b00 cmp r3, #0 800f30e: d101 bne.n 800f314 { return HAL_ERROR; 800f310: 2301 movs r3, #1 800f312: e00e b.n 800f332 } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 800f314: 687b ldr r3, [r7, #4] 800f316: 795b ldrb r3, [r3, #5] 800f318: b2db uxtb r3, r3 800f31a: 2b00 cmp r3, #0 800f31c: d105 bne.n 800f32a { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 800f31e: 687b ldr r3, [r7, #4] 800f320: 2200 movs r2, #0 800f322: 711a strb r2, [r3, #4] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 800f324: 6878 ldr r0, [r7, #4] 800f326: f7fa ff9f bl 800a268 } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 800f32a: 687b ldr r3, [r7, #4] 800f32c: 2201 movs r2, #1 800f32e: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 800f330: 2300 movs r3, #0 } 800f332: 4618 mov r0, r3 800f334: 3708 adds r7, #8 800f336: 46bd mov sp, r7 800f338: bd80 pop {r7, pc} 0800f33a : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 800f33a: b480 push {r7} 800f33c: b085 sub sp, #20 800f33e: af00 add r7, sp, #0 800f340: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800f342: 2300 movs r3, #0 800f344: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 800f346: 687b ldr r3, [r7, #4] 800f348: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800f34c: b2db uxtb r3, r3 800f34e: 2b02 cmp r3, #2 800f350: d008 beq.n 800f364 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800f352: 687b ldr r3, [r7, #4] 800f354: 2204 movs r2, #4 800f356: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800f358: 687b ldr r3, [r7, #4] 800f35a: 2200 movs r2, #0 800f35c: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800f360: 2301 movs r3, #1 800f362: e020 b.n 800f3a6 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800f364: 687b ldr r3, [r7, #4] 800f366: 681b ldr r3, [r3, #0] 800f368: 681a ldr r2, [r3, #0] 800f36a: 687b ldr r3, [r7, #4] 800f36c: 681b ldr r3, [r3, #0] 800f36e: f022 020e bic.w r2, r2, #14 800f372: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800f374: 687b ldr r3, [r7, #4] 800f376: 681b ldr r3, [r3, #0] 800f378: 681a ldr r2, [r3, #0] 800f37a: 687b ldr r3, [r7, #4] 800f37c: 681b ldr r3, [r3, #0] 800f37e: f022 0201 bic.w r2, r2, #1 800f382: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 800f384: 687b ldr r3, [r7, #4] 800f386: 6c1a ldr r2, [r3, #64] @ 0x40 800f388: 687b ldr r3, [r7, #4] 800f38a: 6bdb ldr r3, [r3, #60] @ 0x3c 800f38c: 2101 movs r1, #1 800f38e: fa01 f202 lsl.w r2, r1, r2 800f392: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800f394: 687b ldr r3, [r7, #4] 800f396: 2201 movs r2, #1 800f398: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800f39c: 687b ldr r3, [r7, #4] 800f39e: 2200 movs r2, #0 800f3a0: f883 2020 strb.w r2, [r3, #32] return status; 800f3a4: 7bfb ldrb r3, [r7, #15] } 800f3a6: 4618 mov r0, r3 800f3a8: 3714 adds r7, #20 800f3aa: 46bd mov sp, r7 800f3ac: bc80 pop {r7} 800f3ae: 4770 bx lr 0800f3b0 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 800f3b0: b580 push {r7, lr} 800f3b2: b084 sub sp, #16 800f3b4: af00 add r7, sp, #0 800f3b6: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800f3b8: 2300 movs r3, #0 800f3ba: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 800f3bc: 687b ldr r3, [r7, #4] 800f3be: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800f3c2: b2db uxtb r3, r3 800f3c4: 2b02 cmp r3, #2 800f3c6: d005 beq.n 800f3d4 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800f3c8: 687b ldr r3, [r7, #4] 800f3ca: 2204 movs r2, #4 800f3cc: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 800f3ce: 2301 movs r3, #1 800f3d0: 73fb strb r3, [r7, #15] 800f3d2: e0d6 b.n 800f582 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800f3d4: 687b ldr r3, [r7, #4] 800f3d6: 681b ldr r3, [r3, #0] 800f3d8: 681a ldr r2, [r3, #0] 800f3da: 687b ldr r3, [r7, #4] 800f3dc: 681b ldr r3, [r3, #0] 800f3de: f022 020e bic.w r2, r2, #14 800f3e2: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800f3e4: 687b ldr r3, [r7, #4] 800f3e6: 681b ldr r3, [r3, #0] 800f3e8: 681a ldr r2, [r3, #0] 800f3ea: 687b ldr r3, [r7, #4] 800f3ec: 681b ldr r3, [r3, #0] 800f3ee: f022 0201 bic.w r2, r2, #1 800f3f2: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 800f3f4: 687b ldr r3, [r7, #4] 800f3f6: 681b ldr r3, [r3, #0] 800f3f8: 461a mov r2, r3 800f3fa: 4b64 ldr r3, [pc, #400] @ (800f58c ) 800f3fc: 429a cmp r2, r3 800f3fe: d958 bls.n 800f4b2 800f400: 687b ldr r3, [r7, #4] 800f402: 681b ldr r3, [r3, #0] 800f404: 4a62 ldr r2, [pc, #392] @ (800f590 ) 800f406: 4293 cmp r3, r2 800f408: d04f beq.n 800f4aa 800f40a: 687b ldr r3, [r7, #4] 800f40c: 681b ldr r3, [r3, #0] 800f40e: 4a61 ldr r2, [pc, #388] @ (800f594 ) 800f410: 4293 cmp r3, r2 800f412: d048 beq.n 800f4a6 800f414: 687b ldr r3, [r7, #4] 800f416: 681b ldr r3, [r3, #0] 800f418: 4a5f ldr r2, [pc, #380] @ (800f598 ) 800f41a: 4293 cmp r3, r2 800f41c: d040 beq.n 800f4a0 800f41e: 687b ldr r3, [r7, #4] 800f420: 681b ldr r3, [r3, #0] 800f422: 4a5e ldr r2, [pc, #376] @ (800f59c ) 800f424: 4293 cmp r3, r2 800f426: d038 beq.n 800f49a 800f428: 687b ldr r3, [r7, #4] 800f42a: 681b ldr r3, [r3, #0] 800f42c: 4a5c ldr r2, [pc, #368] @ (800f5a0 ) 800f42e: 4293 cmp r3, r2 800f430: d030 beq.n 800f494 800f432: 687b ldr r3, [r7, #4] 800f434: 681b ldr r3, [r3, #0] 800f436: 4a5b ldr r2, [pc, #364] @ (800f5a4 ) 800f438: 4293 cmp r3, r2 800f43a: d028 beq.n 800f48e 800f43c: 687b ldr r3, [r7, #4] 800f43e: 681b ldr r3, [r3, #0] 800f440: 4a52 ldr r2, [pc, #328] @ (800f58c ) 800f442: 4293 cmp r3, r2 800f444: d020 beq.n 800f488 800f446: 687b ldr r3, [r7, #4] 800f448: 681b ldr r3, [r3, #0] 800f44a: 4a57 ldr r2, [pc, #348] @ (800f5a8 ) 800f44c: 4293 cmp r3, r2 800f44e: d019 beq.n 800f484 800f450: 687b ldr r3, [r7, #4] 800f452: 681b ldr r3, [r3, #0] 800f454: 4a55 ldr r2, [pc, #340] @ (800f5ac ) 800f456: 4293 cmp r3, r2 800f458: d012 beq.n 800f480 800f45a: 687b ldr r3, [r7, #4] 800f45c: 681b ldr r3, [r3, #0] 800f45e: 4a54 ldr r2, [pc, #336] @ (800f5b0 ) 800f460: 4293 cmp r3, r2 800f462: d00a beq.n 800f47a 800f464: 687b ldr r3, [r7, #4] 800f466: 681b ldr r3, [r3, #0] 800f468: 4a52 ldr r2, [pc, #328] @ (800f5b4 ) 800f46a: 4293 cmp r3, r2 800f46c: d102 bne.n 800f474 800f46e: f44f 5380 mov.w r3, #4096 @ 0x1000 800f472: e01b b.n 800f4ac 800f474: f44f 3380 mov.w r3, #65536 @ 0x10000 800f478: e018 b.n 800f4ac 800f47a: f44f 7380 mov.w r3, #256 @ 0x100 800f47e: e015 b.n 800f4ac 800f480: 2310 movs r3, #16 800f482: e013 b.n 800f4ac 800f484: 2301 movs r3, #1 800f486: e011 b.n 800f4ac 800f488: f04f 7380 mov.w r3, #16777216 @ 0x1000000 800f48c: e00e b.n 800f4ac 800f48e: f44f 1380 mov.w r3, #1048576 @ 0x100000 800f492: e00b b.n 800f4ac 800f494: f44f 3380 mov.w r3, #65536 @ 0x10000 800f498: e008 b.n 800f4ac 800f49a: f44f 5380 mov.w r3, #4096 @ 0x1000 800f49e: e005 b.n 800f4ac 800f4a0: f44f 7380 mov.w r3, #256 @ 0x100 800f4a4: e002 b.n 800f4ac 800f4a6: 2310 movs r3, #16 800f4a8: e000 b.n 800f4ac 800f4aa: 2301 movs r3, #1 800f4ac: 4a42 ldr r2, [pc, #264] @ (800f5b8 ) 800f4ae: 6053 str r3, [r2, #4] 800f4b0: e057 b.n 800f562 800f4b2: 687b ldr r3, [r7, #4] 800f4b4: 681b ldr r3, [r3, #0] 800f4b6: 4a36 ldr r2, [pc, #216] @ (800f590 ) 800f4b8: 4293 cmp r3, r2 800f4ba: d04f beq.n 800f55c 800f4bc: 687b ldr r3, [r7, #4] 800f4be: 681b ldr r3, [r3, #0] 800f4c0: 4a34 ldr r2, [pc, #208] @ (800f594 ) 800f4c2: 4293 cmp r3, r2 800f4c4: d048 beq.n 800f558 800f4c6: 687b ldr r3, [r7, #4] 800f4c8: 681b ldr r3, [r3, #0] 800f4ca: 4a33 ldr r2, [pc, #204] @ (800f598 ) 800f4cc: 4293 cmp r3, r2 800f4ce: d040 beq.n 800f552 800f4d0: 687b ldr r3, [r7, #4] 800f4d2: 681b ldr r3, [r3, #0] 800f4d4: 4a31 ldr r2, [pc, #196] @ (800f59c ) 800f4d6: 4293 cmp r3, r2 800f4d8: d038 beq.n 800f54c 800f4da: 687b ldr r3, [r7, #4] 800f4dc: 681b ldr r3, [r3, #0] 800f4de: 4a30 ldr r2, [pc, #192] @ (800f5a0 ) 800f4e0: 4293 cmp r3, r2 800f4e2: d030 beq.n 800f546 800f4e4: 687b ldr r3, [r7, #4] 800f4e6: 681b ldr r3, [r3, #0] 800f4e8: 4a2e ldr r2, [pc, #184] @ (800f5a4 ) 800f4ea: 4293 cmp r3, r2 800f4ec: d028 beq.n 800f540 800f4ee: 687b ldr r3, [r7, #4] 800f4f0: 681b ldr r3, [r3, #0] 800f4f2: 4a26 ldr r2, [pc, #152] @ (800f58c ) 800f4f4: 4293 cmp r3, r2 800f4f6: d020 beq.n 800f53a 800f4f8: 687b ldr r3, [r7, #4] 800f4fa: 681b ldr r3, [r3, #0] 800f4fc: 4a2a ldr r2, [pc, #168] @ (800f5a8 ) 800f4fe: 4293 cmp r3, r2 800f500: d019 beq.n 800f536 800f502: 687b ldr r3, [r7, #4] 800f504: 681b ldr r3, [r3, #0] 800f506: 4a29 ldr r2, [pc, #164] @ (800f5ac ) 800f508: 4293 cmp r3, r2 800f50a: d012 beq.n 800f532 800f50c: 687b ldr r3, [r7, #4] 800f50e: 681b ldr r3, [r3, #0] 800f510: 4a27 ldr r2, [pc, #156] @ (800f5b0 ) 800f512: 4293 cmp r3, r2 800f514: d00a beq.n 800f52c 800f516: 687b ldr r3, [r7, #4] 800f518: 681b ldr r3, [r3, #0] 800f51a: 4a26 ldr r2, [pc, #152] @ (800f5b4 ) 800f51c: 4293 cmp r3, r2 800f51e: d102 bne.n 800f526 800f520: f44f 5380 mov.w r3, #4096 @ 0x1000 800f524: e01b b.n 800f55e 800f526: f44f 3380 mov.w r3, #65536 @ 0x10000 800f52a: e018 b.n 800f55e 800f52c: f44f 7380 mov.w r3, #256 @ 0x100 800f530: e015 b.n 800f55e 800f532: 2310 movs r3, #16 800f534: e013 b.n 800f55e 800f536: 2301 movs r3, #1 800f538: e011 b.n 800f55e 800f53a: f04f 7380 mov.w r3, #16777216 @ 0x1000000 800f53e: e00e b.n 800f55e 800f540: f44f 1380 mov.w r3, #1048576 @ 0x100000 800f544: e00b b.n 800f55e 800f546: f44f 3380 mov.w r3, #65536 @ 0x10000 800f54a: e008 b.n 800f55e 800f54c: f44f 5380 mov.w r3, #4096 @ 0x1000 800f550: e005 b.n 800f55e 800f552: f44f 7380 mov.w r3, #256 @ 0x100 800f556: e002 b.n 800f55e 800f558: 2310 movs r3, #16 800f55a: e000 b.n 800f55e 800f55c: 2301 movs r3, #1 800f55e: 4a17 ldr r2, [pc, #92] @ (800f5bc ) 800f560: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800f562: 687b ldr r3, [r7, #4] 800f564: 2201 movs r2, #1 800f566: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800f56a: 687b ldr r3, [r7, #4] 800f56c: 2200 movs r2, #0 800f56e: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 800f572: 687b ldr r3, [r7, #4] 800f574: 6b5b ldr r3, [r3, #52] @ 0x34 800f576: 2b00 cmp r3, #0 800f578: d003 beq.n 800f582 { hdma->XferAbortCallback(hdma); 800f57a: 687b ldr r3, [r7, #4] 800f57c: 6b5b ldr r3, [r3, #52] @ 0x34 800f57e: 6878 ldr r0, [r7, #4] 800f580: 4798 blx r3 } } return status; 800f582: 7bfb ldrb r3, [r7, #15] } 800f584: 4618 mov r0, r3 800f586: 3710 adds r7, #16 800f588: 46bd mov sp, r7 800f58a: bd80 pop {r7, pc} 800f58c: 40020080 .word 0x40020080 800f590: 40020008 .word 0x40020008 800f594: 4002001c .word 0x4002001c 800f598: 40020030 .word 0x40020030 800f59c: 40020044 .word 0x40020044 800f5a0: 40020058 .word 0x40020058 800f5a4: 4002006c .word 0x4002006c 800f5a8: 40020408 .word 0x40020408 800f5ac: 4002041c .word 0x4002041c 800f5b0: 40020430 .word 0x40020430 800f5b4: 40020444 .word 0x40020444 800f5b8: 40020400 .word 0x40020400 800f5bc: 40020000 .word 0x40020000 0800f5c0 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800f5c0: b480 push {r7} 800f5c2: b08b sub sp, #44 @ 0x2c 800f5c4: af00 add r7, sp, #0 800f5c6: 6078 str r0, [r7, #4] 800f5c8: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 800f5ca: 2300 movs r3, #0 800f5cc: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 800f5ce: 2300 movs r3, #0 800f5d0: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800f5d2: e169 b.n 800f8a8 { /* Get the IO position */ ioposition = (0x01uL << position); 800f5d4: 2201 movs r2, #1 800f5d6: 6a7b ldr r3, [r7, #36] @ 0x24 800f5d8: fa02 f303 lsl.w r3, r2, r3 800f5dc: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 800f5de: 683b ldr r3, [r7, #0] 800f5e0: 681b ldr r3, [r3, #0] 800f5e2: 69fa ldr r2, [r7, #28] 800f5e4: 4013 ands r3, r2 800f5e6: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 800f5e8: 69ba ldr r2, [r7, #24] 800f5ea: 69fb ldr r3, [r7, #28] 800f5ec: 429a cmp r2, r3 800f5ee: f040 8158 bne.w 800f8a2 { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 800f5f2: 683b ldr r3, [r7, #0] 800f5f4: 685b ldr r3, [r3, #4] 800f5f6: 4a9a ldr r2, [pc, #616] @ (800f860 ) 800f5f8: 4293 cmp r3, r2 800f5fa: d05e beq.n 800f6ba 800f5fc: 4a98 ldr r2, [pc, #608] @ (800f860 ) 800f5fe: 4293 cmp r3, r2 800f600: d875 bhi.n 800f6ee 800f602: 4a98 ldr r2, [pc, #608] @ (800f864 ) 800f604: 4293 cmp r3, r2 800f606: d058 beq.n 800f6ba 800f608: 4a96 ldr r2, [pc, #600] @ (800f864 ) 800f60a: 4293 cmp r3, r2 800f60c: d86f bhi.n 800f6ee 800f60e: 4a96 ldr r2, [pc, #600] @ (800f868 ) 800f610: 4293 cmp r3, r2 800f612: d052 beq.n 800f6ba 800f614: 4a94 ldr r2, [pc, #592] @ (800f868 ) 800f616: 4293 cmp r3, r2 800f618: d869 bhi.n 800f6ee 800f61a: 4a94 ldr r2, [pc, #592] @ (800f86c ) 800f61c: 4293 cmp r3, r2 800f61e: d04c beq.n 800f6ba 800f620: 4a92 ldr r2, [pc, #584] @ (800f86c ) 800f622: 4293 cmp r3, r2 800f624: d863 bhi.n 800f6ee 800f626: 4a92 ldr r2, [pc, #584] @ (800f870 ) 800f628: 4293 cmp r3, r2 800f62a: d046 beq.n 800f6ba 800f62c: 4a90 ldr r2, [pc, #576] @ (800f870 ) 800f62e: 4293 cmp r3, r2 800f630: d85d bhi.n 800f6ee 800f632: 2b12 cmp r3, #18 800f634: d82a bhi.n 800f68c 800f636: 2b12 cmp r3, #18 800f638: d859 bhi.n 800f6ee 800f63a: a201 add r2, pc, #4 @ (adr r2, 800f640 ) 800f63c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800f640: 0800f6bb .word 0x0800f6bb 800f644: 0800f695 .word 0x0800f695 800f648: 0800f6a7 .word 0x0800f6a7 800f64c: 0800f6e9 .word 0x0800f6e9 800f650: 0800f6ef .word 0x0800f6ef 800f654: 0800f6ef .word 0x0800f6ef 800f658: 0800f6ef .word 0x0800f6ef 800f65c: 0800f6ef .word 0x0800f6ef 800f660: 0800f6ef .word 0x0800f6ef 800f664: 0800f6ef .word 0x0800f6ef 800f668: 0800f6ef .word 0x0800f6ef 800f66c: 0800f6ef .word 0x0800f6ef 800f670: 0800f6ef .word 0x0800f6ef 800f674: 0800f6ef .word 0x0800f6ef 800f678: 0800f6ef .word 0x0800f6ef 800f67c: 0800f6ef .word 0x0800f6ef 800f680: 0800f6ef .word 0x0800f6ef 800f684: 0800f69d .word 0x0800f69d 800f688: 0800f6b1 .word 0x0800f6b1 800f68c: 4a79 ldr r2, [pc, #484] @ (800f874 ) 800f68e: 4293 cmp r3, r2 800f690: d013 beq.n 800f6ba config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 800f692: e02c b.n 800f6ee config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 800f694: 683b ldr r3, [r7, #0] 800f696: 68db ldr r3, [r3, #12] 800f698: 623b str r3, [r7, #32] break; 800f69a: e029 b.n 800f6f0 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 800f69c: 683b ldr r3, [r7, #0] 800f69e: 68db ldr r3, [r3, #12] 800f6a0: 3304 adds r3, #4 800f6a2: 623b str r3, [r7, #32] break; 800f6a4: e024 b.n 800f6f0 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 800f6a6: 683b ldr r3, [r7, #0] 800f6a8: 68db ldr r3, [r3, #12] 800f6aa: 3308 adds r3, #8 800f6ac: 623b str r3, [r7, #32] break; 800f6ae: e01f b.n 800f6f0 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 800f6b0: 683b ldr r3, [r7, #0] 800f6b2: 68db ldr r3, [r3, #12] 800f6b4: 330c adds r3, #12 800f6b6: 623b str r3, [r7, #32] break; 800f6b8: e01a b.n 800f6f0 if (GPIO_Init->Pull == GPIO_NOPULL) 800f6ba: 683b ldr r3, [r7, #0] 800f6bc: 689b ldr r3, [r3, #8] 800f6be: 2b00 cmp r3, #0 800f6c0: d102 bne.n 800f6c8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 800f6c2: 2304 movs r3, #4 800f6c4: 623b str r3, [r7, #32] break; 800f6c6: e013 b.n 800f6f0 else if (GPIO_Init->Pull == GPIO_PULLUP) 800f6c8: 683b ldr r3, [r7, #0] 800f6ca: 689b ldr r3, [r3, #8] 800f6cc: 2b01 cmp r3, #1 800f6ce: d105 bne.n 800f6dc config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 800f6d0: 2308 movs r3, #8 800f6d2: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 800f6d4: 687b ldr r3, [r7, #4] 800f6d6: 69fa ldr r2, [r7, #28] 800f6d8: 611a str r2, [r3, #16] break; 800f6da: e009 b.n 800f6f0 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 800f6dc: 2308 movs r3, #8 800f6de: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 800f6e0: 687b ldr r3, [r7, #4] 800f6e2: 69fa ldr r2, [r7, #28] 800f6e4: 615a str r2, [r3, #20] break; 800f6e6: e003 b.n 800f6f0 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 800f6e8: 2300 movs r3, #0 800f6ea: 623b str r3, [r7, #32] break; 800f6ec: e000 b.n 800f6f0 break; 800f6ee: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 800f6f0: 69bb ldr r3, [r7, #24] 800f6f2: 2bff cmp r3, #255 @ 0xff 800f6f4: d801 bhi.n 800f6fa 800f6f6: 687b ldr r3, [r7, #4] 800f6f8: e001 b.n 800f6fe 800f6fa: 687b ldr r3, [r7, #4] 800f6fc: 3304 adds r3, #4 800f6fe: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 800f700: 69bb ldr r3, [r7, #24] 800f702: 2bff cmp r3, #255 @ 0xff 800f704: d802 bhi.n 800f70c 800f706: 6a7b ldr r3, [r7, #36] @ 0x24 800f708: 009b lsls r3, r3, #2 800f70a: e002 b.n 800f712 800f70c: 6a7b ldr r3, [r7, #36] @ 0x24 800f70e: 3b08 subs r3, #8 800f710: 009b lsls r3, r3, #2 800f712: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 800f714: 697b ldr r3, [r7, #20] 800f716: 681a ldr r2, [r3, #0] 800f718: 210f movs r1, #15 800f71a: 693b ldr r3, [r7, #16] 800f71c: fa01 f303 lsl.w r3, r1, r3 800f720: 43db mvns r3, r3 800f722: 401a ands r2, r3 800f724: 6a39 ldr r1, [r7, #32] 800f726: 693b ldr r3, [r7, #16] 800f728: fa01 f303 lsl.w r3, r1, r3 800f72c: 431a orrs r2, r3 800f72e: 697b ldr r3, [r7, #20] 800f730: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 800f732: 683b ldr r3, [r7, #0] 800f734: 685b ldr r3, [r3, #4] 800f736: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800f73a: 2b00 cmp r3, #0 800f73c: f000 80b1 beq.w 800f8a2 { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 800f740: 4b4d ldr r3, [pc, #308] @ (800f878 ) 800f742: 699b ldr r3, [r3, #24] 800f744: 4a4c ldr r2, [pc, #304] @ (800f878 ) 800f746: f043 0301 orr.w r3, r3, #1 800f74a: 6193 str r3, [r2, #24] 800f74c: 4b4a ldr r3, [pc, #296] @ (800f878 ) 800f74e: 699b ldr r3, [r3, #24] 800f750: f003 0301 and.w r3, r3, #1 800f754: 60bb str r3, [r7, #8] 800f756: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 800f758: 4a48 ldr r2, [pc, #288] @ (800f87c ) 800f75a: 6a7b ldr r3, [r7, #36] @ 0x24 800f75c: 089b lsrs r3, r3, #2 800f75e: 3302 adds r3, #2 800f760: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800f764: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 800f766: 6a7b ldr r3, [r7, #36] @ 0x24 800f768: f003 0303 and.w r3, r3, #3 800f76c: 009b lsls r3, r3, #2 800f76e: 220f movs r2, #15 800f770: fa02 f303 lsl.w r3, r2, r3 800f774: 43db mvns r3, r3 800f776: 68fa ldr r2, [r7, #12] 800f778: 4013 ands r3, r2 800f77a: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 800f77c: 687b ldr r3, [r7, #4] 800f77e: 4a40 ldr r2, [pc, #256] @ (800f880 ) 800f780: 4293 cmp r3, r2 800f782: d013 beq.n 800f7ac 800f784: 687b ldr r3, [r7, #4] 800f786: 4a3f ldr r2, [pc, #252] @ (800f884 ) 800f788: 4293 cmp r3, r2 800f78a: d00d beq.n 800f7a8 800f78c: 687b ldr r3, [r7, #4] 800f78e: 4a3e ldr r2, [pc, #248] @ (800f888 ) 800f790: 4293 cmp r3, r2 800f792: d007 beq.n 800f7a4 800f794: 687b ldr r3, [r7, #4] 800f796: 4a3d ldr r2, [pc, #244] @ (800f88c ) 800f798: 4293 cmp r3, r2 800f79a: d101 bne.n 800f7a0 800f79c: 2303 movs r3, #3 800f79e: e006 b.n 800f7ae 800f7a0: 2304 movs r3, #4 800f7a2: e004 b.n 800f7ae 800f7a4: 2302 movs r3, #2 800f7a6: e002 b.n 800f7ae 800f7a8: 2301 movs r3, #1 800f7aa: e000 b.n 800f7ae 800f7ac: 2300 movs r3, #0 800f7ae: 6a7a ldr r2, [r7, #36] @ 0x24 800f7b0: f002 0203 and.w r2, r2, #3 800f7b4: 0092 lsls r2, r2, #2 800f7b6: 4093 lsls r3, r2 800f7b8: 68fa ldr r2, [r7, #12] 800f7ba: 4313 orrs r3, r2 800f7bc: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 800f7be: 492f ldr r1, [pc, #188] @ (800f87c ) 800f7c0: 6a7b ldr r3, [r7, #36] @ 0x24 800f7c2: 089b lsrs r3, r3, #2 800f7c4: 3302 adds r3, #2 800f7c6: 68fa ldr r2, [r7, #12] 800f7c8: f841 2023 str.w r2, [r1, r3, lsl #2] /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 800f7cc: 683b ldr r3, [r7, #0] 800f7ce: 685b ldr r3, [r3, #4] 800f7d0: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800f7d4: 2b00 cmp r3, #0 800f7d6: d006 beq.n 800f7e6 { SET_BIT(EXTI->RTSR, iocurrent); 800f7d8: 4b2d ldr r3, [pc, #180] @ (800f890 ) 800f7da: 689a ldr r2, [r3, #8] 800f7dc: 492c ldr r1, [pc, #176] @ (800f890 ) 800f7de: 69bb ldr r3, [r7, #24] 800f7e0: 4313 orrs r3, r2 800f7e2: 608b str r3, [r1, #8] 800f7e4: e006 b.n 800f7f4 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 800f7e6: 4b2a ldr r3, [pc, #168] @ (800f890 ) 800f7e8: 689a ldr r2, [r3, #8] 800f7ea: 69bb ldr r3, [r7, #24] 800f7ec: 43db mvns r3, r3 800f7ee: 4928 ldr r1, [pc, #160] @ (800f890 ) 800f7f0: 4013 ands r3, r2 800f7f2: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 800f7f4: 683b ldr r3, [r7, #0] 800f7f6: 685b ldr r3, [r3, #4] 800f7f8: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800f7fc: 2b00 cmp r3, #0 800f7fe: d006 beq.n 800f80e { SET_BIT(EXTI->FTSR, iocurrent); 800f800: 4b23 ldr r3, [pc, #140] @ (800f890 ) 800f802: 68da ldr r2, [r3, #12] 800f804: 4922 ldr r1, [pc, #136] @ (800f890 ) 800f806: 69bb ldr r3, [r7, #24] 800f808: 4313 orrs r3, r2 800f80a: 60cb str r3, [r1, #12] 800f80c: e006 b.n 800f81c } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 800f80e: 4b20 ldr r3, [pc, #128] @ (800f890 ) 800f810: 68da ldr r2, [r3, #12] 800f812: 69bb ldr r3, [r7, #24] 800f814: 43db mvns r3, r3 800f816: 491e ldr r1, [pc, #120] @ (800f890 ) 800f818: 4013 ands r3, r2 800f81a: 60cb str r3, [r1, #12] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 800f81c: 683b ldr r3, [r7, #0] 800f81e: 685b ldr r3, [r3, #4] 800f820: f403 3300 and.w r3, r3, #131072 @ 0x20000 800f824: 2b00 cmp r3, #0 800f826: d006 beq.n 800f836 { SET_BIT(EXTI->EMR, iocurrent); 800f828: 4b19 ldr r3, [pc, #100] @ (800f890 ) 800f82a: 685a ldr r2, [r3, #4] 800f82c: 4918 ldr r1, [pc, #96] @ (800f890 ) 800f82e: 69bb ldr r3, [r7, #24] 800f830: 4313 orrs r3, r2 800f832: 604b str r3, [r1, #4] 800f834: e006 b.n 800f844 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 800f836: 4b16 ldr r3, [pc, #88] @ (800f890 ) 800f838: 685a ldr r2, [r3, #4] 800f83a: 69bb ldr r3, [r7, #24] 800f83c: 43db mvns r3, r3 800f83e: 4914 ldr r1, [pc, #80] @ (800f890 ) 800f840: 4013 ands r3, r2 800f842: 604b str r3, [r1, #4] } /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 800f844: 683b ldr r3, [r7, #0] 800f846: 685b ldr r3, [r3, #4] 800f848: f403 3380 and.w r3, r3, #65536 @ 0x10000 800f84c: 2b00 cmp r3, #0 800f84e: d021 beq.n 800f894 { SET_BIT(EXTI->IMR, iocurrent); 800f850: 4b0f ldr r3, [pc, #60] @ (800f890 ) 800f852: 681a ldr r2, [r3, #0] 800f854: 490e ldr r1, [pc, #56] @ (800f890 ) 800f856: 69bb ldr r3, [r7, #24] 800f858: 4313 orrs r3, r2 800f85a: 600b str r3, [r1, #0] 800f85c: e021 b.n 800f8a2 800f85e: bf00 nop 800f860: 10320000 .word 0x10320000 800f864: 10310000 .word 0x10310000 800f868: 10220000 .word 0x10220000 800f86c: 10210000 .word 0x10210000 800f870: 10120000 .word 0x10120000 800f874: 10110000 .word 0x10110000 800f878: 40021000 .word 0x40021000 800f87c: 40010000 .word 0x40010000 800f880: 40010800 .word 0x40010800 800f884: 40010c00 .word 0x40010c00 800f888: 40011000 .word 0x40011000 800f88c: 40011400 .word 0x40011400 800f890: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 800f894: 4b0b ldr r3, [pc, #44] @ (800f8c4 ) 800f896: 681a ldr r2, [r3, #0] 800f898: 69bb ldr r3, [r7, #24] 800f89a: 43db mvns r3, r3 800f89c: 4909 ldr r1, [pc, #36] @ (800f8c4 ) 800f89e: 4013 ands r3, r2 800f8a0: 600b str r3, [r1, #0] } } } position++; 800f8a2: 6a7b ldr r3, [r7, #36] @ 0x24 800f8a4: 3301 adds r3, #1 800f8a6: 627b str r3, [r7, #36] @ 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 800f8a8: 683b ldr r3, [r7, #0] 800f8aa: 681a ldr r2, [r3, #0] 800f8ac: 6a7b ldr r3, [r7, #36] @ 0x24 800f8ae: fa22 f303 lsr.w r3, r2, r3 800f8b2: 2b00 cmp r3, #0 800f8b4: f47f ae8e bne.w 800f5d4 } } 800f8b8: bf00 nop 800f8ba: bf00 nop 800f8bc: 372c adds r7, #44 @ 0x2c 800f8be: 46bd mov sp, r7 800f8c0: bc80 pop {r7} 800f8c2: 4770 bx lr 800f8c4: 40010400 .word 0x40010400 0800f8c8 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800f8c8: b480 push {r7} 800f8ca: b085 sub sp, #20 800f8cc: af00 add r7, sp, #0 800f8ce: 6078 str r0, [r7, #4] 800f8d0: 460b mov r3, r1 800f8d2: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 800f8d4: 687b ldr r3, [r7, #4] 800f8d6: 689a ldr r2, [r3, #8] 800f8d8: 887b ldrh r3, [r7, #2] 800f8da: 4013 ands r3, r2 800f8dc: 2b00 cmp r3, #0 800f8de: d002 beq.n 800f8e6 { bitstatus = GPIO_PIN_SET; 800f8e0: 2301 movs r3, #1 800f8e2: 73fb strb r3, [r7, #15] 800f8e4: e001 b.n 800f8ea } else { bitstatus = GPIO_PIN_RESET; 800f8e6: 2300 movs r3, #0 800f8e8: 73fb strb r3, [r7, #15] } return bitstatus; 800f8ea: 7bfb ldrb r3, [r7, #15] } 800f8ec: 4618 mov r0, r3 800f8ee: 3714 adds r7, #20 800f8f0: 46bd mov sp, r7 800f8f2: bc80 pop {r7} 800f8f4: 4770 bx lr 0800f8f6 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800f8f6: b480 push {r7} 800f8f8: b083 sub sp, #12 800f8fa: af00 add r7, sp, #0 800f8fc: 6078 str r0, [r7, #4] 800f8fe: 460b mov r3, r1 800f900: 807b strh r3, [r7, #2] 800f902: 4613 mov r3, r2 800f904: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800f906: 787b ldrb r3, [r7, #1] 800f908: 2b00 cmp r3, #0 800f90a: d003 beq.n 800f914 { GPIOx->BSRR = GPIO_Pin; 800f90c: 887a ldrh r2, [r7, #2] 800f90e: 687b ldr r3, [r7, #4] 800f910: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 800f912: e003 b.n 800f91c GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 800f914: 887b ldrh r3, [r7, #2] 800f916: 041a lsls r2, r3, #16 800f918: 687b ldr r3, [r7, #4] 800f91a: 611a str r2, [r3, #16] } 800f91c: bf00 nop 800f91e: 370c adds r7, #12 800f920: 46bd mov sp, r7 800f922: bc80 pop {r7} 800f924: 4770 bx lr ... 0800f928 : * @note If the HSE divided by 128 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 800f928: b480 push {r7} 800f92a: af00 add r7, sp, #0 /* Enable access to RTC and backup registers */ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 800f92c: 4b03 ldr r3, [pc, #12] @ (800f93c ) 800f92e: 2201 movs r2, #1 800f930: 601a str r2, [r3, #0] } 800f932: bf00 nop 800f934: 46bd mov sp, r7 800f936: bc80 pop {r7} 800f938: 4770 bx lr 800f93a: bf00 nop 800f93c: 420e0020 .word 0x420e0020 0800f940 : * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval HAL_StatusTypeDef */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { 800f940: b580 push {r7, lr} 800f942: b082 sub sp, #8 800f944: af00 add r7, sp, #0 uint32_t tickstart; /* Get Start Tick */ tickstart = HAL_GetTick(); 800f946: f7fd ffc5 bl 800d8d4 800f94a: 6078 str r0, [r7, #4] /* Set HSION bit */ SET_BIT(RCC->CR, RCC_CR_HSION); 800f94c: 4b60 ldr r3, [pc, #384] @ (800fad0 ) 800f94e: 681b ldr r3, [r3, #0] 800f950: 4a5f ldr r2, [pc, #380] @ (800fad0 ) 800f952: f043 0301 orr.w r3, r3, #1 800f956: 6013 str r3, [r2, #0] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 800f958: e008 b.n 800f96c { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800f95a: f7fd ffbb bl 800d8d4 800f95e: 4602 mov r2, r0 800f960: 687b ldr r3, [r7, #4] 800f962: 1ad3 subs r3, r2, r3 800f964: 2b02 cmp r3, #2 800f966: d901 bls.n 800f96c { return HAL_TIMEOUT; 800f968: 2303 movs r3, #3 800f96a: e0ac b.n 800fac6 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 800f96c: 4b58 ldr r3, [pc, #352] @ (800fad0 ) 800f96e: 681b ldr r3, [r3, #0] 800f970: f003 0302 and.w r3, r3, #2 800f974: 2b00 cmp r3, #0 800f976: d0f0 beq.n 800f95a } } /* Set HSITRIM bits to the reset value */ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); 800f978: 4b55 ldr r3, [pc, #340] @ (800fad0 ) 800f97a: 681b ldr r3, [r3, #0] 800f97c: f023 03f8 bic.w r3, r3, #248 @ 0xf8 800f980: 4a53 ldr r2, [pc, #332] @ (800fad0 ) 800f982: f043 0380 orr.w r3, r3, #128 @ 0x80 800f986: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800f988: f7fd ffa4 bl 800d8d4 800f98c: 6078 str r0, [r7, #4] /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); 800f98e: 4b50 ldr r3, [pc, #320] @ (800fad0 ) 800f990: 2200 movs r2, #0 800f992: 605a str r2, [r3, #4] /* Wait till clock switch is ready */ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 800f994: e00a b.n 800f9ac { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800f996: f7fd ff9d bl 800d8d4 800f99a: 4602 mov r2, r0 800f99c: 687b ldr r3, [r7, #4] 800f99e: 1ad3 subs r3, r2, r3 800f9a0: f241 3288 movw r2, #5000 @ 0x1388 800f9a4: 4293 cmp r3, r2 800f9a6: d901 bls.n 800f9ac { return HAL_TIMEOUT; 800f9a8: 2303 movs r3, #3 800f9aa: e08c b.n 800fac6 while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 800f9ac: 4b48 ldr r3, [pc, #288] @ (800fad0 ) 800f9ae: 685b ldr r3, [r3, #4] 800f9b0: f003 030c and.w r3, r3, #12 800f9b4: 2b00 cmp r3, #0 800f9b6: d1ee bne.n 800f996 } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; 800f9b8: 4b46 ldr r3, [pc, #280] @ (800fad4 ) 800f9ba: 4a47 ldr r2, [pc, #284] @ (800fad8 ) 800f9bc: 601a str r2, [r3, #0] /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 800f9be: 4b47 ldr r3, [pc, #284] @ (800fadc ) 800f9c0: 681b ldr r3, [r3, #0] 800f9c2: 4618 mov r0, r3 800f9c4: f7fd ff44 bl 800d850 800f9c8: 4603 mov r3, r0 800f9ca: 2b00 cmp r3, #0 800f9cc: d001 beq.n 800f9d2 { return HAL_ERROR; 800f9ce: 2301 movs r3, #1 800f9d0: e079 b.n 800fac6 } /* Get Start Tick */ tickstart = HAL_GetTick(); 800f9d2: f7fd ff7f bl 800d8d4 800f9d6: 6078 str r0, [r7, #4] /* Second step is to clear PLLON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 800f9d8: 4b3d ldr r3, [pc, #244] @ (800fad0 ) 800f9da: 681b ldr r3, [r3, #0] 800f9dc: 4a3c ldr r2, [pc, #240] @ (800fad0 ) 800f9de: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800f9e2: 6013 str r3, [r2, #0] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 800f9e4: e008 b.n 800f9f8 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800f9e6: f7fd ff75 bl 800d8d4 800f9ea: 4602 mov r2, r0 800f9ec: 687b ldr r3, [r7, #4] 800f9ee: 1ad3 subs r3, r2, r3 800f9f0: 2b02 cmp r3, #2 800f9f2: d901 bls.n 800f9f8 { return HAL_TIMEOUT; 800f9f4: 2303 movs r3, #3 800f9f6: e066 b.n 800fac6 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 800f9f8: 4b35 ldr r3, [pc, #212] @ (800fad0 ) 800f9fa: 681b ldr r3, [r3, #0] 800f9fc: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800fa00: 2b00 cmp r3, #0 800fa02: d1f0 bne.n 800f9e6 } } /* Ensure to reset PLLSRC and PLLMUL bits */ CLEAR_REG(RCC->CFGR); 800fa04: 4b32 ldr r3, [pc, #200] @ (800fad0 ) 800fa06: 2200 movs r2, #0 800fa08: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 800fa0a: f7fd ff63 bl 800d8d4 800fa0e: 6078 str r0, [r7, #4] /* Reset HSEON & CSSON bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON); 800fa10: 4b2f ldr r3, [pc, #188] @ (800fad0 ) 800fa12: 681b ldr r3, [r3, #0] 800fa14: 4a2e ldr r2, [pc, #184] @ (800fad0 ) 800fa16: f423 2310 bic.w r3, r3, #589824 @ 0x90000 800fa1a: 6013 str r3, [r2, #0] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 800fa1c: e008 b.n 800fa30 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800fa1e: f7fd ff59 bl 800d8d4 800fa22: 4602 mov r2, r0 800fa24: 687b ldr r3, [r7, #4] 800fa26: 1ad3 subs r3, r2, r3 800fa28: 2b64 cmp r3, #100 @ 0x64 800fa2a: d901 bls.n 800fa30 { return HAL_TIMEOUT; 800fa2c: 2303 movs r3, #3 800fa2e: e04a b.n 800fac6 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 800fa30: 4b27 ldr r3, [pc, #156] @ (800fad0 ) 800fa32: 681b ldr r3, [r3, #0] 800fa34: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fa38: 2b00 cmp r3, #0 800fa3a: d1f0 bne.n 800fa1e } } /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 800fa3c: 4b24 ldr r3, [pc, #144] @ (800fad0 ) 800fa3e: 681b ldr r3, [r3, #0] 800fa40: 4a23 ldr r2, [pc, #140] @ (800fad0 ) 800fa42: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800fa46: 6013 str r3, [r2, #0] #if defined(RCC_PLL2_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 800fa48: f7fd ff44 bl 800d8d4 800fa4c: 6078 str r0, [r7, #4] /* Clear PLL2ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); 800fa4e: 4b20 ldr r3, [pc, #128] @ (800fad0 ) 800fa50: 681b ldr r3, [r3, #0] 800fa52: 4a1f ldr r2, [pc, #124] @ (800fad0 ) 800fa54: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800fa58: 6013 str r3, [r2, #0] /* Wait till PLL2 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 800fa5a: e008 b.n 800fa6e { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800fa5c: f7fd ff3a bl 800d8d4 800fa60: 4602 mov r2, r0 800fa62: 687b ldr r3, [r7, #4] 800fa64: 1ad3 subs r3, r2, r3 800fa66: 2b64 cmp r3, #100 @ 0x64 800fa68: d901 bls.n 800fa6e { return HAL_TIMEOUT; 800fa6a: 2303 movs r3, #3 800fa6c: e02b b.n 800fac6 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 800fa6e: 4b18 ldr r3, [pc, #96] @ (800fad0 ) 800fa70: 681b ldr r3, [r3, #0] 800fa72: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800fa76: 2b00 cmp r3, #0 800fa78: d1f0 bne.n 800fa5c } #endif /* RCC_PLL2_SUPPORT */ #if defined(RCC_PLLI2S_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 800fa7a: f7fd ff2b bl 800d8d4 800fa7e: 6078 str r0, [r7, #4] /* Clear PLL3ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); 800fa80: 4b13 ldr r3, [pc, #76] @ (800fad0 ) 800fa82: 681b ldr r3, [r3, #0] 800fa84: 4a12 ldr r2, [pc, #72] @ (800fad0 ) 800fa86: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800fa8a: 6013 str r3, [r2, #0] /* Wait till PLL3 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 800fa8c: e008 b.n 800faa0 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 800fa8e: f7fd ff21 bl 800d8d4 800fa92: 4602 mov r2, r0 800fa94: 687b ldr r3, [r7, #4] 800fa96: 1ad3 subs r3, r2, r3 800fa98: 2b64 cmp r3, #100 @ 0x64 800fa9a: d901 bls.n 800faa0 { return HAL_TIMEOUT; 800fa9c: 2303 movs r3, #3 800fa9e: e012 b.n 800fac6 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 800faa0: 4b0b ldr r3, [pc, #44] @ (800fad0 ) 800faa2: 681b ldr r3, [r3, #0] 800faa4: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800faa8: 2b00 cmp r3, #0 800faaa: d1f0 bne.n 800fa8e } #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_CFGR2_PREDIV1) /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); 800faac: 4b08 ldr r3, [pc, #32] @ (800fad0 ) 800faae: 2200 movs r2, #0 800fab0: 62da str r2, [r3, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1 */ /* Reset all CSR flags */ SET_BIT(RCC->CSR, RCC_CSR_RMVF); 800fab2: 4b07 ldr r3, [pc, #28] @ (800fad0 ) 800fab4: 6a5b ldr r3, [r3, #36] @ 0x24 800fab6: 4a06 ldr r2, [pc, #24] @ (800fad0 ) 800fab8: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800fabc: 6253 str r3, [r2, #36] @ 0x24 /* Disable all interrupts */ CLEAR_REG(RCC->CIR); 800fabe: 4b04 ldr r3, [pc, #16] @ (800fad0 ) 800fac0: 2200 movs r2, #0 800fac2: 609a str r2, [r3, #8] return HAL_OK; 800fac4: 2300 movs r3, #0 } 800fac6: 4618 mov r0, r3 800fac8: 3708 adds r7, #8 800faca: 46bd mov sp, r7 800facc: bd80 pop {r7, pc} 800face: bf00 nop 800fad0: 40021000 .word 0x40021000 800fad4: 2000006c .word 0x2000006c 800fad8: 007a1200 .word 0x007a1200 800fadc: 20000070 .word 0x20000070 0800fae0 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800fae0: b580 push {r7, lr} 800fae2: b086 sub sp, #24 800fae4: af00 add r7, sp, #0 800fae6: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 800fae8: 687b ldr r3, [r7, #4] 800faea: 2b00 cmp r3, #0 800faec: d101 bne.n 800faf2 { return HAL_ERROR; 800faee: 2301 movs r3, #1 800faf0: e304 b.n 80100fc /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800faf2: 687b ldr r3, [r7, #4] 800faf4: 681b ldr r3, [r3, #0] 800faf6: f003 0301 and.w r3, r3, #1 800fafa: 2b00 cmp r3, #0 800fafc: f000 8087 beq.w 800fc0e { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 800fb00: 4b92 ldr r3, [pc, #584] @ (800fd4c ) 800fb02: 685b ldr r3, [r3, #4] 800fb04: f003 030c and.w r3, r3, #12 800fb08: 2b04 cmp r3, #4 800fb0a: d00c beq.n 800fb26 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 800fb0c: 4b8f ldr r3, [pc, #572] @ (800fd4c ) 800fb0e: 685b ldr r3, [r3, #4] 800fb10: f003 030c and.w r3, r3, #12 800fb14: 2b08 cmp r3, #8 800fb16: d112 bne.n 800fb3e 800fb18: 4b8c ldr r3, [pc, #560] @ (800fd4c ) 800fb1a: 685b ldr r3, [r3, #4] 800fb1c: f403 3380 and.w r3, r3, #65536 @ 0x10000 800fb20: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800fb24: d10b bne.n 800fb3e { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800fb26: 4b89 ldr r3, [pc, #548] @ (800fd4c ) 800fb28: 681b ldr r3, [r3, #0] 800fb2a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fb2e: 2b00 cmp r3, #0 800fb30: d06c beq.n 800fc0c 800fb32: 687b ldr r3, [r7, #4] 800fb34: 689b ldr r3, [r3, #8] 800fb36: 2b00 cmp r3, #0 800fb38: d168 bne.n 800fc0c { return HAL_ERROR; 800fb3a: 2301 movs r3, #1 800fb3c: e2de b.n 80100fc } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800fb3e: 687b ldr r3, [r7, #4] 800fb40: 689b ldr r3, [r3, #8] 800fb42: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800fb46: d106 bne.n 800fb56 800fb48: 4b80 ldr r3, [pc, #512] @ (800fd4c ) 800fb4a: 681b ldr r3, [r3, #0] 800fb4c: 4a7f ldr r2, [pc, #508] @ (800fd4c ) 800fb4e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800fb52: 6013 str r3, [r2, #0] 800fb54: e02e b.n 800fbb4 800fb56: 687b ldr r3, [r7, #4] 800fb58: 689b ldr r3, [r3, #8] 800fb5a: 2b00 cmp r3, #0 800fb5c: d10c bne.n 800fb78 800fb5e: 4b7b ldr r3, [pc, #492] @ (800fd4c ) 800fb60: 681b ldr r3, [r3, #0] 800fb62: 4a7a ldr r2, [pc, #488] @ (800fd4c ) 800fb64: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800fb68: 6013 str r3, [r2, #0] 800fb6a: 4b78 ldr r3, [pc, #480] @ (800fd4c ) 800fb6c: 681b ldr r3, [r3, #0] 800fb6e: 4a77 ldr r2, [pc, #476] @ (800fd4c ) 800fb70: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800fb74: 6013 str r3, [r2, #0] 800fb76: e01d b.n 800fbb4 800fb78: 687b ldr r3, [r7, #4] 800fb7a: 689b ldr r3, [r3, #8] 800fb7c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800fb80: d10c bne.n 800fb9c 800fb82: 4b72 ldr r3, [pc, #456] @ (800fd4c ) 800fb84: 681b ldr r3, [r3, #0] 800fb86: 4a71 ldr r2, [pc, #452] @ (800fd4c ) 800fb88: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800fb8c: 6013 str r3, [r2, #0] 800fb8e: 4b6f ldr r3, [pc, #444] @ (800fd4c ) 800fb90: 681b ldr r3, [r3, #0] 800fb92: 4a6e ldr r2, [pc, #440] @ (800fd4c ) 800fb94: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800fb98: 6013 str r3, [r2, #0] 800fb9a: e00b b.n 800fbb4 800fb9c: 4b6b ldr r3, [pc, #428] @ (800fd4c ) 800fb9e: 681b ldr r3, [r3, #0] 800fba0: 4a6a ldr r2, [pc, #424] @ (800fd4c ) 800fba2: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800fba6: 6013 str r3, [r2, #0] 800fba8: 4b68 ldr r3, [pc, #416] @ (800fd4c ) 800fbaa: 681b ldr r3, [r3, #0] 800fbac: 4a67 ldr r2, [pc, #412] @ (800fd4c ) 800fbae: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800fbb2: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 800fbb4: 687b ldr r3, [r7, #4] 800fbb6: 689b ldr r3, [r3, #8] 800fbb8: 2b00 cmp r3, #0 800fbba: d013 beq.n 800fbe4 { /* Get Start Tick */ tickstart = HAL_GetTick(); 800fbbc: f7fd fe8a bl 800d8d4 800fbc0: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800fbc2: e008 b.n 800fbd6 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800fbc4: f7fd fe86 bl 800d8d4 800fbc8: 4602 mov r2, r0 800fbca: 693b ldr r3, [r7, #16] 800fbcc: 1ad3 subs r3, r2, r3 800fbce: 2b64 cmp r3, #100 @ 0x64 800fbd0: d901 bls.n 800fbd6 { return HAL_TIMEOUT; 800fbd2: 2303 movs r3, #3 800fbd4: e292 b.n 80100fc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800fbd6: 4b5d ldr r3, [pc, #372] @ (800fd4c ) 800fbd8: 681b ldr r3, [r3, #0] 800fbda: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fbde: 2b00 cmp r3, #0 800fbe0: d0f0 beq.n 800fbc4 800fbe2: e014 b.n 800fc0e } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 800fbe4: f7fd fe76 bl 800d8d4 800fbe8: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800fbea: e008 b.n 800fbfe { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800fbec: f7fd fe72 bl 800d8d4 800fbf0: 4602 mov r2, r0 800fbf2: 693b ldr r3, [r7, #16] 800fbf4: 1ad3 subs r3, r2, r3 800fbf6: 2b64 cmp r3, #100 @ 0x64 800fbf8: d901 bls.n 800fbfe { return HAL_TIMEOUT; 800fbfa: 2303 movs r3, #3 800fbfc: e27e b.n 80100fc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800fbfe: 4b53 ldr r3, [pc, #332] @ (800fd4c ) 800fc00: 681b ldr r3, [r3, #0] 800fc02: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fc06: 2b00 cmp r3, #0 800fc08: d1f0 bne.n 800fbec 800fc0a: e000 b.n 800fc0e if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800fc0c: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800fc0e: 687b ldr r3, [r7, #4] 800fc10: 681b ldr r3, [r3, #0] 800fc12: f003 0302 and.w r3, r3, #2 800fc16: 2b00 cmp r3, #0 800fc18: d063 beq.n 800fce2 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 800fc1a: 4b4c ldr r3, [pc, #304] @ (800fd4c ) 800fc1c: 685b ldr r3, [r3, #4] 800fc1e: f003 030c and.w r3, r3, #12 800fc22: 2b00 cmp r3, #0 800fc24: d00b beq.n 800fc3e || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 800fc26: 4b49 ldr r3, [pc, #292] @ (800fd4c ) 800fc28: 685b ldr r3, [r3, #4] 800fc2a: f003 030c and.w r3, r3, #12 800fc2e: 2b08 cmp r3, #8 800fc30: d11c bne.n 800fc6c 800fc32: 4b46 ldr r3, [pc, #280] @ (800fd4c ) 800fc34: 685b ldr r3, [r3, #4] 800fc36: f403 3380 and.w r3, r3, #65536 @ 0x10000 800fc3a: 2b00 cmp r3, #0 800fc3c: d116 bne.n 800fc6c { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800fc3e: 4b43 ldr r3, [pc, #268] @ (800fd4c ) 800fc40: 681b ldr r3, [r3, #0] 800fc42: f003 0302 and.w r3, r3, #2 800fc46: 2b00 cmp r3, #0 800fc48: d005 beq.n 800fc56 800fc4a: 687b ldr r3, [r7, #4] 800fc4c: 695b ldr r3, [r3, #20] 800fc4e: 2b01 cmp r3, #1 800fc50: d001 beq.n 800fc56 { return HAL_ERROR; 800fc52: 2301 movs r3, #1 800fc54: e252 b.n 80100fc } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800fc56: 4b3d ldr r3, [pc, #244] @ (800fd4c ) 800fc58: 681b ldr r3, [r3, #0] 800fc5a: f023 02f8 bic.w r2, r3, #248 @ 0xf8 800fc5e: 687b ldr r3, [r7, #4] 800fc60: 699b ldr r3, [r3, #24] 800fc62: 00db lsls r3, r3, #3 800fc64: 4939 ldr r1, [pc, #228] @ (800fd4c ) 800fc66: 4313 orrs r3, r2 800fc68: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800fc6a: e03a b.n 800fce2 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 800fc6c: 687b ldr r3, [r7, #4] 800fc6e: 695b ldr r3, [r3, #20] 800fc70: 2b00 cmp r3, #0 800fc72: d020 beq.n 800fcb6 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 800fc74: 4b36 ldr r3, [pc, #216] @ (800fd50 ) 800fc76: 2201 movs r2, #1 800fc78: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800fc7a: f7fd fe2b bl 800d8d4 800fc7e: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800fc80: e008 b.n 800fc94 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800fc82: f7fd fe27 bl 800d8d4 800fc86: 4602 mov r2, r0 800fc88: 693b ldr r3, [r7, #16] 800fc8a: 1ad3 subs r3, r2, r3 800fc8c: 2b02 cmp r3, #2 800fc8e: d901 bls.n 800fc94 { return HAL_TIMEOUT; 800fc90: 2303 movs r3, #3 800fc92: e233 b.n 80100fc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800fc94: 4b2d ldr r3, [pc, #180] @ (800fd4c ) 800fc96: 681b ldr r3, [r3, #0] 800fc98: f003 0302 and.w r3, r3, #2 800fc9c: 2b00 cmp r3, #0 800fc9e: d0f0 beq.n 800fc82 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800fca0: 4b2a ldr r3, [pc, #168] @ (800fd4c ) 800fca2: 681b ldr r3, [r3, #0] 800fca4: f023 02f8 bic.w r2, r3, #248 @ 0xf8 800fca8: 687b ldr r3, [r7, #4] 800fcaa: 699b ldr r3, [r3, #24] 800fcac: 00db lsls r3, r3, #3 800fcae: 4927 ldr r1, [pc, #156] @ (800fd4c ) 800fcb0: 4313 orrs r3, r2 800fcb2: 600b str r3, [r1, #0] 800fcb4: e015 b.n 800fce2 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800fcb6: 4b26 ldr r3, [pc, #152] @ (800fd50 ) 800fcb8: 2200 movs r2, #0 800fcba: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800fcbc: f7fd fe0a bl 800d8d4 800fcc0: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800fcc2: e008 b.n 800fcd6 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800fcc4: f7fd fe06 bl 800d8d4 800fcc8: 4602 mov r2, r0 800fcca: 693b ldr r3, [r7, #16] 800fccc: 1ad3 subs r3, r2, r3 800fcce: 2b02 cmp r3, #2 800fcd0: d901 bls.n 800fcd6 { return HAL_TIMEOUT; 800fcd2: 2303 movs r3, #3 800fcd4: e212 b.n 80100fc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800fcd6: 4b1d ldr r3, [pc, #116] @ (800fd4c ) 800fcd8: 681b ldr r3, [r3, #0] 800fcda: f003 0302 and.w r3, r3, #2 800fcde: 2b00 cmp r3, #0 800fce0: d1f0 bne.n 800fcc4 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800fce2: 687b ldr r3, [r7, #4] 800fce4: 681b ldr r3, [r3, #0] 800fce6: f003 0308 and.w r3, r3, #8 800fcea: 2b00 cmp r3, #0 800fcec: d03a beq.n 800fd64 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 800fcee: 687b ldr r3, [r7, #4] 800fcf0: 69db ldr r3, [r3, #28] 800fcf2: 2b00 cmp r3, #0 800fcf4: d019 beq.n 800fd2a { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800fcf6: 4b17 ldr r3, [pc, #92] @ (800fd54 ) 800fcf8: 2201 movs r2, #1 800fcfa: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800fcfc: f7fd fdea bl 800d8d4 800fd00: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800fd02: e008 b.n 800fd16 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800fd04: f7fd fde6 bl 800d8d4 800fd08: 4602 mov r2, r0 800fd0a: 693b ldr r3, [r7, #16] 800fd0c: 1ad3 subs r3, r2, r3 800fd0e: 2b02 cmp r3, #2 800fd10: d901 bls.n 800fd16 { return HAL_TIMEOUT; 800fd12: 2303 movs r3, #3 800fd14: e1f2 b.n 80100fc while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800fd16: 4b0d ldr r3, [pc, #52] @ (800fd4c ) 800fd18: 6a5b ldr r3, [r3, #36] @ 0x24 800fd1a: f003 0302 and.w r3, r3, #2 800fd1e: 2b00 cmp r3, #0 800fd20: d0f0 beq.n 800fd04 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 800fd22: 2001 movs r0, #1 800fd24: f000 fbca bl 80104bc 800fd28: e01c b.n 800fd64 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800fd2a: 4b0a ldr r3, [pc, #40] @ (800fd54 ) 800fd2c: 2200 movs r2, #0 800fd2e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800fd30: f7fd fdd0 bl 800d8d4 800fd34: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800fd36: e00f b.n 800fd58 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800fd38: f7fd fdcc bl 800d8d4 800fd3c: 4602 mov r2, r0 800fd3e: 693b ldr r3, [r7, #16] 800fd40: 1ad3 subs r3, r2, r3 800fd42: 2b02 cmp r3, #2 800fd44: d908 bls.n 800fd58 { return HAL_TIMEOUT; 800fd46: 2303 movs r3, #3 800fd48: e1d8 b.n 80100fc 800fd4a: bf00 nop 800fd4c: 40021000 .word 0x40021000 800fd50: 42420000 .word 0x42420000 800fd54: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800fd58: 4b9b ldr r3, [pc, #620] @ (800ffc8 ) 800fd5a: 6a5b ldr r3, [r3, #36] @ 0x24 800fd5c: f003 0302 and.w r3, r3, #2 800fd60: 2b00 cmp r3, #0 800fd62: d1e9 bne.n 800fd38 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800fd64: 687b ldr r3, [r7, #4] 800fd66: 681b ldr r3, [r3, #0] 800fd68: f003 0304 and.w r3, r3, #4 800fd6c: 2b00 cmp r3, #0 800fd6e: f000 80a6 beq.w 800febe { FlagStatus pwrclkchanged = RESET; 800fd72: 2300 movs r3, #0 800fd74: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 800fd76: 4b94 ldr r3, [pc, #592] @ (800ffc8 ) 800fd78: 69db ldr r3, [r3, #28] 800fd7a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800fd7e: 2b00 cmp r3, #0 800fd80: d10d bne.n 800fd9e { __HAL_RCC_PWR_CLK_ENABLE(); 800fd82: 4b91 ldr r3, [pc, #580] @ (800ffc8 ) 800fd84: 69db ldr r3, [r3, #28] 800fd86: 4a90 ldr r2, [pc, #576] @ (800ffc8 ) 800fd88: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800fd8c: 61d3 str r3, [r2, #28] 800fd8e: 4b8e ldr r3, [pc, #568] @ (800ffc8 ) 800fd90: 69db ldr r3, [r3, #28] 800fd92: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800fd96: 60bb str r3, [r7, #8] 800fd98: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 800fd9a: 2301 movs r3, #1 800fd9c: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800fd9e: 4b8b ldr r3, [pc, #556] @ (800ffcc ) 800fda0: 681b ldr r3, [r3, #0] 800fda2: f403 7380 and.w r3, r3, #256 @ 0x100 800fda6: 2b00 cmp r3, #0 800fda8: d118 bne.n 800fddc { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 800fdaa: 4b88 ldr r3, [pc, #544] @ (800ffcc ) 800fdac: 681b ldr r3, [r3, #0] 800fdae: 4a87 ldr r2, [pc, #540] @ (800ffcc ) 800fdb0: f443 7380 orr.w r3, r3, #256 @ 0x100 800fdb4: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800fdb6: f7fd fd8d bl 800d8d4 800fdba: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800fdbc: e008 b.n 800fdd0 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800fdbe: f7fd fd89 bl 800d8d4 800fdc2: 4602 mov r2, r0 800fdc4: 693b ldr r3, [r7, #16] 800fdc6: 1ad3 subs r3, r2, r3 800fdc8: 2b64 cmp r3, #100 @ 0x64 800fdca: d901 bls.n 800fdd0 { return HAL_TIMEOUT; 800fdcc: 2303 movs r3, #3 800fdce: e195 b.n 80100fc while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800fdd0: 4b7e ldr r3, [pc, #504] @ (800ffcc ) 800fdd2: 681b ldr r3, [r3, #0] 800fdd4: f403 7380 and.w r3, r3, #256 @ 0x100 800fdd8: 2b00 cmp r3, #0 800fdda: d0f0 beq.n 800fdbe } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800fddc: 687b ldr r3, [r7, #4] 800fdde: 691b ldr r3, [r3, #16] 800fde0: 2b01 cmp r3, #1 800fde2: d106 bne.n 800fdf2 800fde4: 4b78 ldr r3, [pc, #480] @ (800ffc8 ) 800fde6: 6a1b ldr r3, [r3, #32] 800fde8: 4a77 ldr r2, [pc, #476] @ (800ffc8 ) 800fdea: f043 0301 orr.w r3, r3, #1 800fdee: 6213 str r3, [r2, #32] 800fdf0: e02d b.n 800fe4e 800fdf2: 687b ldr r3, [r7, #4] 800fdf4: 691b ldr r3, [r3, #16] 800fdf6: 2b00 cmp r3, #0 800fdf8: d10c bne.n 800fe14 800fdfa: 4b73 ldr r3, [pc, #460] @ (800ffc8 ) 800fdfc: 6a1b ldr r3, [r3, #32] 800fdfe: 4a72 ldr r2, [pc, #456] @ (800ffc8 ) 800fe00: f023 0301 bic.w r3, r3, #1 800fe04: 6213 str r3, [r2, #32] 800fe06: 4b70 ldr r3, [pc, #448] @ (800ffc8 ) 800fe08: 6a1b ldr r3, [r3, #32] 800fe0a: 4a6f ldr r2, [pc, #444] @ (800ffc8 ) 800fe0c: f023 0304 bic.w r3, r3, #4 800fe10: 6213 str r3, [r2, #32] 800fe12: e01c b.n 800fe4e 800fe14: 687b ldr r3, [r7, #4] 800fe16: 691b ldr r3, [r3, #16] 800fe18: 2b05 cmp r3, #5 800fe1a: d10c bne.n 800fe36 800fe1c: 4b6a ldr r3, [pc, #424] @ (800ffc8 ) 800fe1e: 6a1b ldr r3, [r3, #32] 800fe20: 4a69 ldr r2, [pc, #420] @ (800ffc8 ) 800fe22: f043 0304 orr.w r3, r3, #4 800fe26: 6213 str r3, [r2, #32] 800fe28: 4b67 ldr r3, [pc, #412] @ (800ffc8 ) 800fe2a: 6a1b ldr r3, [r3, #32] 800fe2c: 4a66 ldr r2, [pc, #408] @ (800ffc8 ) 800fe2e: f043 0301 orr.w r3, r3, #1 800fe32: 6213 str r3, [r2, #32] 800fe34: e00b b.n 800fe4e 800fe36: 4b64 ldr r3, [pc, #400] @ (800ffc8 ) 800fe38: 6a1b ldr r3, [r3, #32] 800fe3a: 4a63 ldr r2, [pc, #396] @ (800ffc8 ) 800fe3c: f023 0301 bic.w r3, r3, #1 800fe40: 6213 str r3, [r2, #32] 800fe42: 4b61 ldr r3, [pc, #388] @ (800ffc8 ) 800fe44: 6a1b ldr r3, [r3, #32] 800fe46: 4a60 ldr r2, [pc, #384] @ (800ffc8 ) 800fe48: f023 0304 bic.w r3, r3, #4 800fe4c: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 800fe4e: 687b ldr r3, [r7, #4] 800fe50: 691b ldr r3, [r3, #16] 800fe52: 2b00 cmp r3, #0 800fe54: d015 beq.n 800fe82 { /* Get Start Tick */ tickstart = HAL_GetTick(); 800fe56: f7fd fd3d bl 800d8d4 800fe5a: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800fe5c: e00a b.n 800fe74 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800fe5e: f7fd fd39 bl 800d8d4 800fe62: 4602 mov r2, r0 800fe64: 693b ldr r3, [r7, #16] 800fe66: 1ad3 subs r3, r2, r3 800fe68: f241 3288 movw r2, #5000 @ 0x1388 800fe6c: 4293 cmp r3, r2 800fe6e: d901 bls.n 800fe74 { return HAL_TIMEOUT; 800fe70: 2303 movs r3, #3 800fe72: e143 b.n 80100fc while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800fe74: 4b54 ldr r3, [pc, #336] @ (800ffc8 ) 800fe76: 6a1b ldr r3, [r3, #32] 800fe78: f003 0302 and.w r3, r3, #2 800fe7c: 2b00 cmp r3, #0 800fe7e: d0ee beq.n 800fe5e 800fe80: e014 b.n 800feac } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 800fe82: f7fd fd27 bl 800d8d4 800fe86: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 800fe88: e00a b.n 800fea0 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800fe8a: f7fd fd23 bl 800d8d4 800fe8e: 4602 mov r2, r0 800fe90: 693b ldr r3, [r7, #16] 800fe92: 1ad3 subs r3, r2, r3 800fe94: f241 3288 movw r2, #5000 @ 0x1388 800fe98: 4293 cmp r3, r2 800fe9a: d901 bls.n 800fea0 { return HAL_TIMEOUT; 800fe9c: 2303 movs r3, #3 800fe9e: e12d b.n 80100fc while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 800fea0: 4b49 ldr r3, [pc, #292] @ (800ffc8 ) 800fea2: 6a1b ldr r3, [r3, #32] 800fea4: f003 0302 and.w r3, r3, #2 800fea8: 2b00 cmp r3, #0 800feaa: d1ee bne.n 800fe8a } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 800feac: 7dfb ldrb r3, [r7, #23] 800feae: 2b01 cmp r3, #1 800feb0: d105 bne.n 800febe { __HAL_RCC_PWR_CLK_DISABLE(); 800feb2: 4b45 ldr r3, [pc, #276] @ (800ffc8 ) 800feb4: 69db ldr r3, [r3, #28] 800feb6: 4a44 ldr r2, [pc, #272] @ (800ffc8 ) 800feb8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800febc: 61d3 str r3, [r2, #28] #if defined(RCC_CR_PLL2ON) /*-------------------------------- PLL2 Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) 800febe: 687b ldr r3, [r7, #4] 800fec0: 6adb ldr r3, [r3, #44] @ 0x2c 800fec2: 2b00 cmp r3, #0 800fec4: f000 808c beq.w 800ffe0 { /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 800fec8: 4b3f ldr r3, [pc, #252] @ (800ffc8 ) 800feca: 685b ldr r3, [r3, #4] 800fecc: f403 3380 and.w r3, r3, #65536 @ 0x10000 800fed0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800fed4: d10e bne.n 800fef4 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 800fed6: 4b3c ldr r3, [pc, #240] @ (800ffc8 ) 800fed8: 685b ldr r3, [r3, #4] 800feda: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 800fede: 2b08 cmp r3, #8 800fee0: d108 bne.n 800fef4 ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) 800fee2: 4b39 ldr r3, [pc, #228] @ (800ffc8 ) 800fee4: 6adb ldr r3, [r3, #44] @ 0x2c 800fee6: f403 3380 and.w r3, r3, #65536 @ 0x10000 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 800feea: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800feee: d101 bne.n 800fef4 { return HAL_ERROR; 800fef0: 2301 movs r3, #1 800fef2: e103 b.n 80100fc } else { if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) 800fef4: 687b ldr r3, [r7, #4] 800fef6: 6adb ldr r3, [r3, #44] @ 0x2c 800fef8: 2b02 cmp r3, #2 800fefa: d14e bne.n 800ff9a assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); /* Prediv2 can be written only when the PLLI2S is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 800fefc: 4b32 ldr r3, [pc, #200] @ (800ffc8 ) 800fefe: 681b ldr r3, [r3, #0] 800ff00: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800ff04: 2b00 cmp r3, #0 800ff06: d009 beq.n 800ff1c (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) 800ff08: 4b2f ldr r3, [pc, #188] @ (800ffc8 ) 800ff0a: 6adb ldr r3, [r3, #44] @ 0x2c 800ff0c: f003 02f0 and.w r2, r3, #240 @ 0xf0 800ff10: 687b ldr r3, [r7, #4] 800ff12: 6b5b ldr r3, [r3, #52] @ 0x34 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 800ff14: 429a cmp r2, r3 800ff16: d001 beq.n 800ff1c { return HAL_ERROR; 800ff18: 2301 movs r3, #1 800ff1a: e0ef b.n 80100fc } /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 800ff1c: 4b2c ldr r3, [pc, #176] @ (800ffd0 ) 800ff1e: 2200 movs r2, #0 800ff20: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800ff22: f7fd fcd7 bl 800d8d4 800ff26: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 800ff28: e008 b.n 800ff3c { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800ff2a: f7fd fcd3 bl 800d8d4 800ff2e: 4602 mov r2, r0 800ff30: 693b ldr r3, [r7, #16] 800ff32: 1ad3 subs r3, r2, r3 800ff34: 2b64 cmp r3, #100 @ 0x64 800ff36: d901 bls.n 800ff3c { return HAL_TIMEOUT; 800ff38: 2303 movs r3, #3 800ff3a: e0df b.n 80100fc while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 800ff3c: 4b22 ldr r3, [pc, #136] @ (800ffc8 ) 800ff3e: 681b ldr r3, [r3, #0] 800ff40: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800ff44: 2b00 cmp r3, #0 800ff46: d1f0 bne.n 800ff2a } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); 800ff48: 4b1f ldr r3, [pc, #124] @ (800ffc8 ) 800ff4a: 6adb ldr r3, [r3, #44] @ 0x2c 800ff4c: f023 02f0 bic.w r2, r3, #240 @ 0xf0 800ff50: 687b ldr r3, [r7, #4] 800ff52: 6b5b ldr r3, [r3, #52] @ 0x34 800ff54: 491c ldr r1, [pc, #112] @ (800ffc8 ) 800ff56: 4313 orrs r3, r2 800ff58: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); 800ff5a: 4b1b ldr r3, [pc, #108] @ (800ffc8 ) 800ff5c: 6adb ldr r3, [r3, #44] @ 0x2c 800ff5e: f423 6270 bic.w r2, r3, #3840 @ 0xf00 800ff62: 687b ldr r3, [r7, #4] 800ff64: 6b1b ldr r3, [r3, #48] @ 0x30 800ff66: 4918 ldr r1, [pc, #96] @ (800ffc8 ) 800ff68: 4313 orrs r3, r2 800ff6a: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); 800ff6c: 4b18 ldr r3, [pc, #96] @ (800ffd0 ) 800ff6e: 2201 movs r2, #1 800ff70: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800ff72: f7fd fcaf bl 800d8d4 800ff76: 6138 str r0, [r7, #16] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 800ff78: e008 b.n 800ff8c { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800ff7a: f7fd fcab bl 800d8d4 800ff7e: 4602 mov r2, r0 800ff80: 693b ldr r3, [r7, #16] 800ff82: 1ad3 subs r3, r2, r3 800ff84: 2b64 cmp r3, #100 @ 0x64 800ff86: d901 bls.n 800ff8c { return HAL_TIMEOUT; 800ff88: 2303 movs r3, #3 800ff8a: e0b7 b.n 80100fc while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 800ff8c: 4b0e ldr r3, [pc, #56] @ (800ffc8 ) 800ff8e: 681b ldr r3, [r3, #0] 800ff90: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800ff94: 2b00 cmp r3, #0 800ff96: d0f0 beq.n 800ff7a 800ff98: e022 b.n 800ffe0 } } else { /* Set PREDIV1 source to HSE */ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); 800ff9a: 4b0b ldr r3, [pc, #44] @ (800ffc8 ) 800ff9c: 6adb ldr r3, [r3, #44] @ 0x2c 800ff9e: 4a0a ldr r2, [pc, #40] @ (800ffc8 ) 800ffa0: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ffa4: 62d3 str r3, [r2, #44] @ 0x2c /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 800ffa6: 4b0a ldr r3, [pc, #40] @ (800ffd0 ) 800ffa8: 2200 movs r2, #0 800ffaa: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800ffac: f7fd fc92 bl 800d8d4 800ffb0: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 800ffb2: e00f b.n 800ffd4 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800ffb4: f7fd fc8e bl 800d8d4 800ffb8: 4602 mov r2, r0 800ffba: 693b ldr r3, [r7, #16] 800ffbc: 1ad3 subs r3, r2, r3 800ffbe: 2b64 cmp r3, #100 @ 0x64 800ffc0: d908 bls.n 800ffd4 { return HAL_TIMEOUT; 800ffc2: 2303 movs r3, #3 800ffc4: e09a b.n 80100fc 800ffc6: bf00 nop 800ffc8: 40021000 .word 0x40021000 800ffcc: 40007000 .word 0x40007000 800ffd0: 42420068 .word 0x42420068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 800ffd4: 4b4b ldr r3, [pc, #300] @ (8010104 ) 800ffd6: 681b ldr r3, [r3, #0] 800ffd8: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800ffdc: 2b00 cmp r3, #0 800ffde: d1e9 bne.n 800ffb4 #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800ffe0: 687b ldr r3, [r7, #4] 800ffe2: 6a1b ldr r3, [r3, #32] 800ffe4: 2b00 cmp r3, #0 800ffe6: f000 8088 beq.w 80100fa { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 800ffea: 4b46 ldr r3, [pc, #280] @ (8010104 ) 800ffec: 685b ldr r3, [r3, #4] 800ffee: f003 030c and.w r3, r3, #12 800fff2: 2b08 cmp r3, #8 800fff4: d068 beq.n 80100c8 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 800fff6: 687b ldr r3, [r7, #4] 800fff8: 6a1b ldr r3, [r3, #32] 800fffa: 2b02 cmp r3, #2 800fffc: d14d bne.n 801009a /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800fffe: 4b42 ldr r3, [pc, #264] @ (8010108 ) 8010000: 2200 movs r2, #0 8010002: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010004: f7fd fc66 bl 800d8d4 8010008: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 801000a: e008 b.n 801001e { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 801000c: f7fd fc62 bl 800d8d4 8010010: 4602 mov r2, r0 8010012: 693b ldr r3, [r7, #16] 8010014: 1ad3 subs r3, r2, r3 8010016: 2b02 cmp r3, #2 8010018: d901 bls.n 801001e { return HAL_TIMEOUT; 801001a: 2303 movs r3, #3 801001c: e06e b.n 80100fc while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 801001e: 4b39 ldr r3, [pc, #228] @ (8010104 ) 8010020: 681b ldr r3, [r3, #0] 8010022: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8010026: 2b00 cmp r3, #0 8010028: d1f0 bne.n 801000c } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 801002a: 687b ldr r3, [r7, #4] 801002c: 6a5b ldr r3, [r3, #36] @ 0x24 801002e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010032: d10f bne.n 8010054 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); #if defined(RCC_CFGR2_PREDIV1SRC) assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); 8010034: 4b33 ldr r3, [pc, #204] @ (8010104 ) 8010036: 6ada ldr r2, [r3, #44] @ 0x2c 8010038: 687b ldr r3, [r7, #4] 801003a: 685b ldr r3, [r3, #4] 801003c: 4931 ldr r1, [pc, #196] @ (8010104 ) 801003e: 4313 orrs r3, r2 8010040: 62cb str r3, [r1, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8010042: 4b30 ldr r3, [pc, #192] @ (8010104 ) 8010044: 6adb ldr r3, [r3, #44] @ 0x2c 8010046: f023 020f bic.w r2, r3, #15 801004a: 687b ldr r3, [r7, #4] 801004c: 68db ldr r3, [r3, #12] 801004e: 492d ldr r1, [pc, #180] @ (8010104 ) 8010050: 4313 orrs r3, r2 8010052: 62cb str r3, [r1, #44] @ 0x2c } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8010054: 4b2b ldr r3, [pc, #172] @ (8010104 ) 8010056: 685b ldr r3, [r3, #4] 8010058: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 801005c: 687b ldr r3, [r7, #4] 801005e: 6a59 ldr r1, [r3, #36] @ 0x24 8010060: 687b ldr r3, [r7, #4] 8010062: 6a9b ldr r3, [r3, #40] @ 0x28 8010064: 430b orrs r3, r1 8010066: 4927 ldr r1, [pc, #156] @ (8010104 ) 8010068: 4313 orrs r3, r2 801006a: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 801006c: 4b26 ldr r3, [pc, #152] @ (8010108 ) 801006e: 2201 movs r2, #1 8010070: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010072: f7fd fc2f bl 800d8d4 8010076: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8010078: e008 b.n 801008c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 801007a: f7fd fc2b bl 800d8d4 801007e: 4602 mov r2, r0 8010080: 693b ldr r3, [r7, #16] 8010082: 1ad3 subs r3, r2, r3 8010084: 2b02 cmp r3, #2 8010086: d901 bls.n 801008c { return HAL_TIMEOUT; 8010088: 2303 movs r3, #3 801008a: e037 b.n 80100fc while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 801008c: 4b1d ldr r3, [pc, #116] @ (8010104 ) 801008e: 681b ldr r3, [r3, #0] 8010090: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8010094: 2b00 cmp r3, #0 8010096: d0f0 beq.n 801007a 8010098: e02f b.n 80100fa } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 801009a: 4b1b ldr r3, [pc, #108] @ (8010108 ) 801009c: 2200 movs r2, #0 801009e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80100a0: f7fd fc18 bl 800d8d4 80100a4: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80100a6: e008 b.n 80100ba { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80100a8: f7fd fc14 bl 800d8d4 80100ac: 4602 mov r2, r0 80100ae: 693b ldr r3, [r7, #16] 80100b0: 1ad3 subs r3, r2, r3 80100b2: 2b02 cmp r3, #2 80100b4: d901 bls.n 80100ba { return HAL_TIMEOUT; 80100b6: 2303 movs r3, #3 80100b8: e020 b.n 80100fc while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80100ba: 4b12 ldr r3, [pc, #72] @ (8010104 ) 80100bc: 681b ldr r3, [r3, #0] 80100be: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80100c2: 2b00 cmp r3, #0 80100c4: d1f0 bne.n 80100a8 80100c6: e018 b.n 80100fa } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 80100c8: 687b ldr r3, [r7, #4] 80100ca: 6a1b ldr r3, [r3, #32] 80100cc: 2b01 cmp r3, #1 80100ce: d101 bne.n 80100d4 { return HAL_ERROR; 80100d0: 2301 movs r3, #1 80100d2: e013 b.n 80100fc } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 80100d4: 4b0b ldr r3, [pc, #44] @ (8010104 ) 80100d6: 685b ldr r3, [r3, #4] 80100d8: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80100da: 68fb ldr r3, [r7, #12] 80100dc: f403 3280 and.w r2, r3, #65536 @ 0x10000 80100e0: 687b ldr r3, [r7, #4] 80100e2: 6a5b ldr r3, [r3, #36] @ 0x24 80100e4: 429a cmp r2, r3 80100e6: d106 bne.n 80100f6 (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 80100e8: 68fb ldr r3, [r7, #12] 80100ea: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 80100ee: 687b ldr r3, [r7, #4] 80100f0: 6a9b ldr r3, [r3, #40] @ 0x28 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80100f2: 429a cmp r2, r3 80100f4: d001 beq.n 80100fa { return HAL_ERROR; 80100f6: 2301 movs r3, #1 80100f8: e000 b.n 80100fc } } } } return HAL_OK; 80100fa: 2300 movs r3, #0 } 80100fc: 4618 mov r0, r3 80100fe: 3718 adds r7, #24 8010100: 46bd mov sp, r7 8010102: bd80 pop {r7, pc} 8010104: 40021000 .word 0x40021000 8010108: 42420060 .word 0x42420060 0801010c : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 801010c: b580 push {r7, lr} 801010e: b084 sub sp, #16 8010110: af00 add r7, sp, #0 8010112: 6078 str r0, [r7, #4] 8010114: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8010116: 687b ldr r3, [r7, #4] 8010118: 2b00 cmp r3, #0 801011a: d101 bne.n 8010120 { return HAL_ERROR; 801011c: 2301 movs r3, #1 801011e: e0d0 b.n 80102c2 must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8010120: 4b6a ldr r3, [pc, #424] @ (80102cc ) 8010122: 681b ldr r3, [r3, #0] 8010124: f003 0307 and.w r3, r3, #7 8010128: 683a ldr r2, [r7, #0] 801012a: 429a cmp r2, r3 801012c: d910 bls.n 8010150 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 801012e: 4b67 ldr r3, [pc, #412] @ (80102cc ) 8010130: 681b ldr r3, [r3, #0] 8010132: f023 0207 bic.w r2, r3, #7 8010136: 4965 ldr r1, [pc, #404] @ (80102cc ) 8010138: 683b ldr r3, [r7, #0] 801013a: 4313 orrs r3, r2 801013c: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 801013e: 4b63 ldr r3, [pc, #396] @ (80102cc ) 8010140: 681b ldr r3, [r3, #0] 8010142: f003 0307 and.w r3, r3, #7 8010146: 683a ldr r2, [r7, #0] 8010148: 429a cmp r2, r3 801014a: d001 beq.n 8010150 { return HAL_ERROR; 801014c: 2301 movs r3, #1 801014e: e0b8 b.n 80102c2 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8010150: 687b ldr r3, [r7, #4] 8010152: 681b ldr r3, [r3, #0] 8010154: f003 0302 and.w r3, r3, #2 8010158: 2b00 cmp r3, #0 801015a: d020 beq.n 801019e { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 801015c: 687b ldr r3, [r7, #4] 801015e: 681b ldr r3, [r3, #0] 8010160: f003 0304 and.w r3, r3, #4 8010164: 2b00 cmp r3, #0 8010166: d005 beq.n 8010174 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8010168: 4b59 ldr r3, [pc, #356] @ (80102d0 ) 801016a: 685b ldr r3, [r3, #4] 801016c: 4a58 ldr r2, [pc, #352] @ (80102d0 ) 801016e: f443 63e0 orr.w r3, r3, #1792 @ 0x700 8010172: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8010174: 687b ldr r3, [r7, #4] 8010176: 681b ldr r3, [r3, #0] 8010178: f003 0308 and.w r3, r3, #8 801017c: 2b00 cmp r3, #0 801017e: d005 beq.n 801018c { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8010180: 4b53 ldr r3, [pc, #332] @ (80102d0 ) 8010182: 685b ldr r3, [r3, #4] 8010184: 4a52 ldr r2, [pc, #328] @ (80102d0 ) 8010186: f443 5360 orr.w r3, r3, #14336 @ 0x3800 801018a: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 801018c: 4b50 ldr r3, [pc, #320] @ (80102d0 ) 801018e: 685b ldr r3, [r3, #4] 8010190: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8010194: 687b ldr r3, [r7, #4] 8010196: 689b ldr r3, [r3, #8] 8010198: 494d ldr r1, [pc, #308] @ (80102d0 ) 801019a: 4313 orrs r3, r2 801019c: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 801019e: 687b ldr r3, [r7, #4] 80101a0: 681b ldr r3, [r3, #0] 80101a2: f003 0301 and.w r3, r3, #1 80101a6: 2b00 cmp r3, #0 80101a8: d040 beq.n 801022c { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80101aa: 687b ldr r3, [r7, #4] 80101ac: 685b ldr r3, [r3, #4] 80101ae: 2b01 cmp r3, #1 80101b0: d107 bne.n 80101c2 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80101b2: 4b47 ldr r3, [pc, #284] @ (80102d0 ) 80101b4: 681b ldr r3, [r3, #0] 80101b6: f403 3300 and.w r3, r3, #131072 @ 0x20000 80101ba: 2b00 cmp r3, #0 80101bc: d115 bne.n 80101ea { return HAL_ERROR; 80101be: 2301 movs r3, #1 80101c0: e07f b.n 80102c2 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 80101c2: 687b ldr r3, [r7, #4] 80101c4: 685b ldr r3, [r3, #4] 80101c6: 2b02 cmp r3, #2 80101c8: d107 bne.n 80101da { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80101ca: 4b41 ldr r3, [pc, #260] @ (80102d0 ) 80101cc: 681b ldr r3, [r3, #0] 80101ce: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80101d2: 2b00 cmp r3, #0 80101d4: d109 bne.n 80101ea { return HAL_ERROR; 80101d6: 2301 movs r3, #1 80101d8: e073 b.n 80102c2 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80101da: 4b3d ldr r3, [pc, #244] @ (80102d0 ) 80101dc: 681b ldr r3, [r3, #0] 80101de: f003 0302 and.w r3, r3, #2 80101e2: 2b00 cmp r3, #0 80101e4: d101 bne.n 80101ea { return HAL_ERROR; 80101e6: 2301 movs r3, #1 80101e8: e06b b.n 80102c2 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 80101ea: 4b39 ldr r3, [pc, #228] @ (80102d0 ) 80101ec: 685b ldr r3, [r3, #4] 80101ee: f023 0203 bic.w r2, r3, #3 80101f2: 687b ldr r3, [r7, #4] 80101f4: 685b ldr r3, [r3, #4] 80101f6: 4936 ldr r1, [pc, #216] @ (80102d0 ) 80101f8: 4313 orrs r3, r2 80101fa: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 80101fc: f7fd fb6a bl 800d8d4 8010200: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8010202: e00a b.n 801021a { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8010204: f7fd fb66 bl 800d8d4 8010208: 4602 mov r2, r0 801020a: 68fb ldr r3, [r7, #12] 801020c: 1ad3 subs r3, r2, r3 801020e: f241 3288 movw r2, #5000 @ 0x1388 8010212: 4293 cmp r3, r2 8010214: d901 bls.n 801021a { return HAL_TIMEOUT; 8010216: 2303 movs r3, #3 8010218: e053 b.n 80102c2 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 801021a: 4b2d ldr r3, [pc, #180] @ (80102d0 ) 801021c: 685b ldr r3, [r3, #4] 801021e: f003 020c and.w r2, r3, #12 8010222: 687b ldr r3, [r7, #4] 8010224: 685b ldr r3, [r3, #4] 8010226: 009b lsls r3, r3, #2 8010228: 429a cmp r2, r3 801022a: d1eb bne.n 8010204 } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 801022c: 4b27 ldr r3, [pc, #156] @ (80102cc ) 801022e: 681b ldr r3, [r3, #0] 8010230: f003 0307 and.w r3, r3, #7 8010234: 683a ldr r2, [r7, #0] 8010236: 429a cmp r2, r3 8010238: d210 bcs.n 801025c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 801023a: 4b24 ldr r3, [pc, #144] @ (80102cc ) 801023c: 681b ldr r3, [r3, #0] 801023e: f023 0207 bic.w r2, r3, #7 8010242: 4922 ldr r1, [pc, #136] @ (80102cc ) 8010244: 683b ldr r3, [r7, #0] 8010246: 4313 orrs r3, r2 8010248: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 801024a: 4b20 ldr r3, [pc, #128] @ (80102cc ) 801024c: 681b ldr r3, [r3, #0] 801024e: f003 0307 and.w r3, r3, #7 8010252: 683a ldr r2, [r7, #0] 8010254: 429a cmp r2, r3 8010256: d001 beq.n 801025c { return HAL_ERROR; 8010258: 2301 movs r3, #1 801025a: e032 b.n 80102c2 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 801025c: 687b ldr r3, [r7, #4] 801025e: 681b ldr r3, [r3, #0] 8010260: f003 0304 and.w r3, r3, #4 8010264: 2b00 cmp r3, #0 8010266: d008 beq.n 801027a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8010268: 4b19 ldr r3, [pc, #100] @ (80102d0 ) 801026a: 685b ldr r3, [r3, #4] 801026c: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8010270: 687b ldr r3, [r7, #4] 8010272: 68db ldr r3, [r3, #12] 8010274: 4916 ldr r1, [pc, #88] @ (80102d0 ) 8010276: 4313 orrs r3, r2 8010278: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 801027a: 687b ldr r3, [r7, #4] 801027c: 681b ldr r3, [r3, #0] 801027e: f003 0308 and.w r3, r3, #8 8010282: 2b00 cmp r3, #0 8010284: d009 beq.n 801029a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 8010286: 4b12 ldr r3, [pc, #72] @ (80102d0 ) 8010288: 685b ldr r3, [r3, #4] 801028a: f423 5260 bic.w r2, r3, #14336 @ 0x3800 801028e: 687b ldr r3, [r7, #4] 8010290: 691b ldr r3, [r3, #16] 8010292: 00db lsls r3, r3, #3 8010294: 490e ldr r1, [pc, #56] @ (80102d0 ) 8010296: 4313 orrs r3, r2 8010298: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 801029a: f000 f821 bl 80102e0 801029e: 4602 mov r2, r0 80102a0: 4b0b ldr r3, [pc, #44] @ (80102d0 ) 80102a2: 685b ldr r3, [r3, #4] 80102a4: 091b lsrs r3, r3, #4 80102a6: f003 030f and.w r3, r3, #15 80102aa: 490a ldr r1, [pc, #40] @ (80102d4 ) 80102ac: 5ccb ldrb r3, [r1, r3] 80102ae: fa22 f303 lsr.w r3, r2, r3 80102b2: 4a09 ldr r2, [pc, #36] @ (80102d8 ) 80102b4: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 80102b6: 4b09 ldr r3, [pc, #36] @ (80102dc ) 80102b8: 681b ldr r3, [r3, #0] 80102ba: 4618 mov r0, r3 80102bc: f7fd fac8 bl 800d850 return HAL_OK; 80102c0: 2300 movs r3, #0 } 80102c2: 4618 mov r0, r3 80102c4: 3710 adds r7, #16 80102c6: 46bd mov sp, r7 80102c8: bd80 pop {r7, pc} 80102ca: bf00 nop 80102cc: 40022000 .word 0x40022000 80102d0: 40021000 .word 0x40021000 80102d4: 0801439c .word 0x0801439c 80102d8: 2000006c .word 0x2000006c 80102dc: 20000070 .word 0x20000070 080102e0 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 80102e0: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 80102e4: b08e sub sp, #56 @ 0x38 80102e6: af00 add r7, sp, #0 #else static const uint8_t aPredivFactorTable[2U] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 80102e8: 2300 movs r3, #0 80102ea: 62fb str r3, [r7, #44] @ 0x2c 80102ec: 2300 movs r3, #0 80102ee: 62bb str r3, [r7, #40] @ 0x28 80102f0: 2300 movs r3, #0 80102f2: 637b str r3, [r7, #52] @ 0x34 80102f4: 2300 movs r3, #0 80102f6: 627b str r3, [r7, #36] @ 0x24 uint32_t sysclockfreq = 0U; 80102f8: 2300 movs r3, #0 80102fa: 633b str r3, [r7, #48] @ 0x30 #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; 80102fc: 2300 movs r3, #0 80102fe: 623b str r3, [r7, #32] 8010300: 2300 movs r3, #0 8010302: 61fb str r3, [r7, #28] #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 8010304: 4b4e ldr r3, [pc, #312] @ (8010440 ) 8010306: 685b ldr r3, [r3, #4] 8010308: 62fb str r3, [r7, #44] @ 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 801030a: 6afb ldr r3, [r7, #44] @ 0x2c 801030c: f003 030c and.w r3, r3, #12 8010310: 2b04 cmp r3, #4 8010312: d002 beq.n 801031a 8010314: 2b08 cmp r3, #8 8010316: d003 beq.n 8010320 8010318: e089 b.n 801042e { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 801031a: 4b4a ldr r3, [pc, #296] @ (8010444 ) 801031c: 633b str r3, [r7, #48] @ 0x30 break; 801031e: e089 b.n 8010434 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8010320: 6afb ldr r3, [r7, #44] @ 0x2c 8010322: 0c9b lsrs r3, r3, #18 8010324: f003 020f and.w r2, r3, #15 8010328: 4b47 ldr r3, [pc, #284] @ (8010448 ) 801032a: 5c9b ldrb r3, [r3, r2] 801032c: 627b str r3, [r7, #36] @ 0x24 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 801032e: 6afb ldr r3, [r7, #44] @ 0x2c 8010330: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010334: 2b00 cmp r3, #0 8010336: d072 beq.n 801041e { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 8010338: 4b41 ldr r3, [pc, #260] @ (8010440 ) 801033a: 6adb ldr r3, [r3, #44] @ 0x2c 801033c: f003 020f and.w r2, r3, #15 8010340: 4b42 ldr r3, [pc, #264] @ (801044c ) 8010342: 5c9b ldrb r3, [r3, r2] 8010344: 62bb str r3, [r7, #40] @ 0x28 #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /*RCC_CFGR2_PREDIV1*/ #if defined(RCC_CFGR2_PREDIV1SRC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 8010346: 4b3e ldr r3, [pc, #248] @ (8010440 ) 8010348: 6adb ldr r3, [r3, #44] @ 0x2c 801034a: f403 3380 and.w r3, r3, #65536 @ 0x10000 801034e: 2b00 cmp r3, #0 8010350: d053 beq.n 80103fa { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8010352: 4b3b ldr r3, [pc, #236] @ (8010440 ) 8010354: 6adb ldr r3, [r3, #44] @ 0x2c 8010356: 091b lsrs r3, r3, #4 8010358: f003 030f and.w r3, r3, #15 801035c: 3301 adds r3, #1 801035e: 623b str r3, [r7, #32] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 8010360: 4b37 ldr r3, [pc, #220] @ (8010440 ) 8010362: 6adb ldr r3, [r3, #44] @ 0x2c 8010364: 0a1b lsrs r3, r3, #8 8010366: f003 030f and.w r3, r3, #15 801036a: 3302 adds r3, #2 801036c: 61fb str r3, [r7, #28] pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); 801036e: 69fb ldr r3, [r7, #28] 8010370: 2200 movs r2, #0 8010372: 469a mov sl, r3 8010374: 4693 mov fp, r2 8010376: 6a7b ldr r3, [r7, #36] @ 0x24 8010378: 2200 movs r2, #0 801037a: 613b str r3, [r7, #16] 801037c: 617a str r2, [r7, #20] 801037e: 693b ldr r3, [r7, #16] 8010380: fb03 f20b mul.w r2, r3, fp 8010384: 697b ldr r3, [r7, #20] 8010386: fb0a f303 mul.w r3, sl, r3 801038a: 4413 add r3, r2 801038c: 693a ldr r2, [r7, #16] 801038e: fbaa 0102 umull r0, r1, sl, r2 8010392: 440b add r3, r1 8010394: 4619 mov r1, r3 8010396: 4b2b ldr r3, [pc, #172] @ (8010444 ) 8010398: fb03 f201 mul.w r2, r3, r1 801039c: 2300 movs r3, #0 801039e: fb00 f303 mul.w r3, r0, r3 80103a2: 4413 add r3, r2 80103a4: 4a27 ldr r2, [pc, #156] @ (8010444 ) 80103a6: fba0 4502 umull r4, r5, r0, r2 80103aa: 442b add r3, r5 80103ac: 461d mov r5, r3 80103ae: 6a3b ldr r3, [r7, #32] 80103b0: 2200 movs r2, #0 80103b2: 60bb str r3, [r7, #8] 80103b4: 60fa str r2, [r7, #12] 80103b6: 6abb ldr r3, [r7, #40] @ 0x28 80103b8: 2200 movs r2, #0 80103ba: 603b str r3, [r7, #0] 80103bc: 607a str r2, [r7, #4] 80103be: e9d7 0102 ldrd r0, r1, [r7, #8] 80103c2: 460b mov r3, r1 80103c4: e9d7 ab00 ldrd sl, fp, [r7] 80103c8: 4652 mov r2, sl 80103ca: fb02 f203 mul.w r2, r2, r3 80103ce: 465b mov r3, fp 80103d0: 4684 mov ip, r0 80103d2: fb0c f303 mul.w r3, ip, r3 80103d6: 4413 add r3, r2 80103d8: 4602 mov r2, r0 80103da: 4651 mov r1, sl 80103dc: fba2 8901 umull r8, r9, r2, r1 80103e0: 444b add r3, r9 80103e2: 4699 mov r9, r3 80103e4: 4642 mov r2, r8 80103e6: 464b mov r3, r9 80103e8: 4620 mov r0, r4 80103ea: 4629 mov r1, r5 80103ec: f7f8 fe34 bl 8009058 <__aeabi_uldivmod> 80103f0: 4602 mov r2, r0 80103f2: 460b mov r3, r1 80103f4: 4613 mov r3, r2 80103f6: 637b str r3, [r7, #52] @ 0x34 80103f8: e007 b.n 801040a } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 80103fa: 6a7b ldr r3, [r7, #36] @ 0x24 80103fc: 4a11 ldr r2, [pc, #68] @ (8010444 ) 80103fe: fb03 f202 mul.w r2, r3, r2 8010402: 6abb ldr r3, [r7, #40] @ 0x28 8010404: fbb2 f3f3 udiv r3, r2, r3 8010408: 637b str r3, [r7, #52] @ 0x34 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 801040a: 4b0f ldr r3, [pc, #60] @ (8010448 ) 801040c: 7b5b ldrb r3, [r3, #13] 801040e: 461a mov r2, r3 8010410: 6a7b ldr r3, [r7, #36] @ 0x24 8010412: 4293 cmp r3, r2 8010414: d108 bne.n 8010428 { pllclk = pllclk / 2; 8010416: 6b7b ldr r3, [r7, #52] @ 0x34 8010418: 085b lsrs r3, r3, #1 801041a: 637b str r3, [r7, #52] @ 0x34 801041c: e004 b.n 8010428 #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 801041e: 6a7b ldr r3, [r7, #36] @ 0x24 8010420: 4a0b ldr r2, [pc, #44] @ (8010450 ) 8010422: fb02 f303 mul.w r3, r2, r3 8010426: 637b str r3, [r7, #52] @ 0x34 } sysclockfreq = pllclk; 8010428: 6b7b ldr r3, [r7, #52] @ 0x34 801042a: 633b str r3, [r7, #48] @ 0x30 break; 801042c: e002 b.n 8010434 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 801042e: 4b09 ldr r3, [pc, #36] @ (8010454 ) 8010430: 633b str r3, [r7, #48] @ 0x30 break; 8010432: bf00 nop } } return sysclockfreq; 8010434: 6b3b ldr r3, [r7, #48] @ 0x30 } 8010436: 4618 mov r0, r3 8010438: 3738 adds r7, #56 @ 0x38 801043a: 46bd mov sp, r7 801043c: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8010440: 40021000 .word 0x40021000 8010444: 017d7840 .word 0x017d7840 8010448: 080143b4 .word 0x080143b4 801044c: 080143c4 .word 0x080143c4 8010450: 003d0900 .word 0x003d0900 8010454: 007a1200 .word 0x007a1200 08010458 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8010458: b480 push {r7} 801045a: af00 add r7, sp, #0 return SystemCoreClock; 801045c: 4b02 ldr r3, [pc, #8] @ (8010468 ) 801045e: 681b ldr r3, [r3, #0] } 8010460: 4618 mov r0, r3 8010462: 46bd mov sp, r7 8010464: bc80 pop {r7} 8010466: 4770 bx lr 8010468: 2000006c .word 0x2000006c 0801046c : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 801046c: b580 push {r7, lr} 801046e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8010470: f7ff fff2 bl 8010458 8010474: 4602 mov r2, r0 8010476: 4b05 ldr r3, [pc, #20] @ (801048c ) 8010478: 685b ldr r3, [r3, #4] 801047a: 0a1b lsrs r3, r3, #8 801047c: f003 0307 and.w r3, r3, #7 8010480: 4903 ldr r1, [pc, #12] @ (8010490 ) 8010482: 5ccb ldrb r3, [r1, r3] 8010484: fa22 f303 lsr.w r3, r2, r3 } 8010488: 4618 mov r0, r3 801048a: bd80 pop {r7, pc} 801048c: 40021000 .word 0x40021000 8010490: 080143ac .word 0x080143ac 08010494 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8010494: b580 push {r7, lr} 8010496: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8010498: f7ff ffde bl 8010458 801049c: 4602 mov r2, r0 801049e: 4b05 ldr r3, [pc, #20] @ (80104b4 ) 80104a0: 685b ldr r3, [r3, #4] 80104a2: 0adb lsrs r3, r3, #11 80104a4: f003 0307 and.w r3, r3, #7 80104a8: 4903 ldr r1, [pc, #12] @ (80104b8 ) 80104aa: 5ccb ldrb r3, [r1, r3] 80104ac: fa22 f303 lsr.w r3, r2, r3 } 80104b0: 4618 mov r0, r3 80104b2: bd80 pop {r7, pc} 80104b4: 40021000 .word 0x40021000 80104b8: 080143ac .word 0x080143ac 080104bc : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 80104bc: b480 push {r7} 80104be: b085 sub sp, #20 80104c0: af00 add r7, sp, #0 80104c2: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 80104c4: 4b0a ldr r3, [pc, #40] @ (80104f0 ) 80104c6: 681b ldr r3, [r3, #0] 80104c8: 4a0a ldr r2, [pc, #40] @ (80104f4 ) 80104ca: fba2 2303 umull r2, r3, r2, r3 80104ce: 0a5b lsrs r3, r3, #9 80104d0: 687a ldr r2, [r7, #4] 80104d2: fb02 f303 mul.w r3, r2, r3 80104d6: 60fb str r3, [r7, #12] do { __NOP(); 80104d8: bf00 nop } while (Delay --); 80104da: 68fb ldr r3, [r7, #12] 80104dc: 1e5a subs r2, r3, #1 80104de: 60fa str r2, [r7, #12] 80104e0: 2b00 cmp r3, #0 80104e2: d1f9 bne.n 80104d8 } 80104e4: bf00 nop 80104e6: bf00 nop 80104e8: 3714 adds r7, #20 80104ea: 46bd mov sp, r7 80104ec: bc80 pop {r7} 80104ee: 4770 bx lr 80104f0: 2000006c .word 0x2000006c 80104f4: 10624dd3 .word 0x10624dd3 080104f8 : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 80104f8: b580 push {r7, lr} 80104fa: b088 sub sp, #32 80104fc: af00 add r7, sp, #0 80104fe: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 8010500: 2300 movs r3, #0 8010502: 617b str r3, [r7, #20] 8010504: 2300 movs r3, #0 8010506: 613b str r3, [r7, #16] #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t pllactive = 0U; 8010508: 2300 movs r3, #0 801050a: 61fb str r3, [r7, #28] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 801050c: 687b ldr r3, [r7, #4] 801050e: 681b ldr r3, [r3, #0] 8010510: f003 0301 and.w r3, r3, #1 8010514: 2b00 cmp r3, #0 8010516: d07d beq.n 8010614 { FlagStatus pwrclkchanged = RESET; 8010518: 2300 movs r3, #0 801051a: 76fb strb r3, [r7, #27] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 801051c: 4b8b ldr r3, [pc, #556] @ (801074c ) 801051e: 69db ldr r3, [r3, #28] 8010520: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010524: 2b00 cmp r3, #0 8010526: d10d bne.n 8010544 { __HAL_RCC_PWR_CLK_ENABLE(); 8010528: 4b88 ldr r3, [pc, #544] @ (801074c ) 801052a: 69db ldr r3, [r3, #28] 801052c: 4a87 ldr r2, [pc, #540] @ (801074c ) 801052e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8010532: 61d3 str r3, [r2, #28] 8010534: 4b85 ldr r3, [pc, #532] @ (801074c ) 8010536: 69db ldr r3, [r3, #28] 8010538: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 801053c: 60fb str r3, [r7, #12] 801053e: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8010540: 2301 movs r3, #1 8010542: 76fb strb r3, [r7, #27] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010544: 4b82 ldr r3, [pc, #520] @ (8010750 ) 8010546: 681b ldr r3, [r3, #0] 8010548: f403 7380 and.w r3, r3, #256 @ 0x100 801054c: 2b00 cmp r3, #0 801054e: d118 bne.n 8010582 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8010550: 4b7f ldr r3, [pc, #508] @ (8010750 ) 8010552: 681b ldr r3, [r3, #0] 8010554: 4a7e ldr r2, [pc, #504] @ (8010750 ) 8010556: f443 7380 orr.w r3, r3, #256 @ 0x100 801055a: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 801055c: f7fd f9ba bl 800d8d4 8010560: 6178 str r0, [r7, #20] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010562: e008 b.n 8010576 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8010564: f7fd f9b6 bl 800d8d4 8010568: 4602 mov r2, r0 801056a: 697b ldr r3, [r7, #20] 801056c: 1ad3 subs r3, r2, r3 801056e: 2b64 cmp r3, #100 @ 0x64 8010570: d901 bls.n 8010576 { return HAL_TIMEOUT; 8010572: 2303 movs r3, #3 8010574: e0e5 b.n 8010742 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010576: 4b76 ldr r3, [pc, #472] @ (8010750 ) 8010578: 681b ldr r3, [r3, #0] 801057a: f403 7380 and.w r3, r3, #256 @ 0x100 801057e: 2b00 cmp r3, #0 8010580: d0f0 beq.n 8010564 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 8010582: 4b72 ldr r3, [pc, #456] @ (801074c ) 8010584: 6a1b ldr r3, [r3, #32] 8010586: f403 7340 and.w r3, r3, #768 @ 0x300 801058a: 613b str r3, [r7, #16] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 801058c: 693b ldr r3, [r7, #16] 801058e: 2b00 cmp r3, #0 8010590: d02e beq.n 80105f0 8010592: 687b ldr r3, [r7, #4] 8010594: 685b ldr r3, [r3, #4] 8010596: f403 7340 and.w r3, r3, #768 @ 0x300 801059a: 693a ldr r2, [r7, #16] 801059c: 429a cmp r2, r3 801059e: d027 beq.n 80105f0 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 80105a0: 4b6a ldr r3, [pc, #424] @ (801074c ) 80105a2: 6a1b ldr r3, [r3, #32] 80105a4: f423 7340 bic.w r3, r3, #768 @ 0x300 80105a8: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80105aa: 4b6a ldr r3, [pc, #424] @ (8010754 ) 80105ac: 2201 movs r2, #1 80105ae: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 80105b0: 4b68 ldr r3, [pc, #416] @ (8010754 ) 80105b2: 2200 movs r2, #0 80105b4: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 80105b6: 4a65 ldr r2, [pc, #404] @ (801074c ) 80105b8: 693b ldr r3, [r7, #16] 80105ba: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 80105bc: 693b ldr r3, [r7, #16] 80105be: f003 0301 and.w r3, r3, #1 80105c2: 2b00 cmp r3, #0 80105c4: d014 beq.n 80105f0 { /* Get Start Tick */ tickstart = HAL_GetTick(); 80105c6: f7fd f985 bl 800d8d4 80105ca: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80105cc: e00a b.n 80105e4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80105ce: f7fd f981 bl 800d8d4 80105d2: 4602 mov r2, r0 80105d4: 697b ldr r3, [r7, #20] 80105d6: 1ad3 subs r3, r2, r3 80105d8: f241 3288 movw r2, #5000 @ 0x1388 80105dc: 4293 cmp r3, r2 80105de: d901 bls.n 80105e4 { return HAL_TIMEOUT; 80105e0: 2303 movs r3, #3 80105e2: e0ae b.n 8010742 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80105e4: 4b59 ldr r3, [pc, #356] @ (801074c ) 80105e6: 6a1b ldr r3, [r3, #32] 80105e8: f003 0302 and.w r3, r3, #2 80105ec: 2b00 cmp r3, #0 80105ee: d0ee beq.n 80105ce } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80105f0: 4b56 ldr r3, [pc, #344] @ (801074c ) 80105f2: 6a1b ldr r3, [r3, #32] 80105f4: f423 7240 bic.w r2, r3, #768 @ 0x300 80105f8: 687b ldr r3, [r7, #4] 80105fa: 685b ldr r3, [r3, #4] 80105fc: 4953 ldr r1, [pc, #332] @ (801074c ) 80105fe: 4313 orrs r3, r2 8010600: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8010602: 7efb ldrb r3, [r7, #27] 8010604: 2b01 cmp r3, #1 8010606: d105 bne.n 8010614 { __HAL_RCC_PWR_CLK_DISABLE(); 8010608: 4b50 ldr r3, [pc, #320] @ (801074c ) 801060a: 69db ldr r3, [r3, #28] 801060c: 4a4f ldr r2, [pc, #316] @ (801074c ) 801060e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8010612: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8010614: 687b ldr r3, [r7, #4] 8010616: 681b ldr r3, [r3, #0] 8010618: f003 0302 and.w r3, r3, #2 801061c: 2b00 cmp r3, #0 801061e: d008 beq.n 8010632 { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8010620: 4b4a ldr r3, [pc, #296] @ (801074c ) 8010622: 685b ldr r3, [r3, #4] 8010624: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8010628: 687b ldr r3, [r7, #4] 801062a: 689b ldr r3, [r3, #8] 801062c: 4947 ldr r1, [pc, #284] @ (801074c ) 801062e: 4313 orrs r3, r2 8010630: 604b str r3, [r1, #4] } #if defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ I2S2 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) 8010632: 687b ldr r3, [r7, #4] 8010634: 681b ldr r3, [r3, #0] 8010636: f003 0304 and.w r3, r3, #4 801063a: 2b00 cmp r3, #0 801063c: d008 beq.n 8010650 { /* Check the parameters */ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); /* Configure the I2S2 clock source */ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); 801063e: 4b43 ldr r3, [pc, #268] @ (801074c ) 8010640: 6adb ldr r3, [r3, #44] @ 0x2c 8010642: f423 3200 bic.w r2, r3, #131072 @ 0x20000 8010646: 687b ldr r3, [r7, #4] 8010648: 68db ldr r3, [r3, #12] 801064a: 4940 ldr r1, [pc, #256] @ (801074c ) 801064c: 4313 orrs r3, r2 801064e: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ I2S3 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) 8010650: 687b ldr r3, [r7, #4] 8010652: 681b ldr r3, [r3, #0] 8010654: f003 0308 and.w r3, r3, #8 8010658: 2b00 cmp r3, #0 801065a: d008 beq.n 801066e { /* Check the parameters */ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); /* Configure the I2S3 clock source */ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); 801065c: 4b3b ldr r3, [pc, #236] @ (801074c ) 801065e: 6adb ldr r3, [r3, #44] @ 0x2c 8010660: f423 2280 bic.w r2, r3, #262144 @ 0x40000 8010664: 687b ldr r3, [r7, #4] 8010666: 691b ldr r3, [r3, #16] 8010668: 4938 ldr r1, [pc, #224] @ (801074c ) 801066a: 4313 orrs r3, r2 801066c: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ PLL I2S Configuration ----------------------*/ /* Check that PLLI2S need to be enabled */ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) 801066e: 4b37 ldr r3, [pc, #220] @ (801074c ) 8010670: 6adb ldr r3, [r3, #44] @ 0x2c 8010672: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010676: 2b00 cmp r3, #0 8010678: d105 bne.n 8010686 801067a: 4b34 ldr r3, [pc, #208] @ (801074c ) 801067c: 6adb ldr r3, [r3, #44] @ 0x2c 801067e: f403 2380 and.w r3, r3, #262144 @ 0x40000 8010682: 2b00 cmp r3, #0 8010684: d001 beq.n 801068a { /* Update flag to indicate that PLL I2S should be active */ pllactive = 1; 8010686: 2301 movs r3, #1 8010688: 61fb str r3, [r7, #28] } /* Check if PLL I2S need to be enabled */ if (pllactive == 1) 801068a: 69fb ldr r3, [r7, #28] 801068c: 2b01 cmp r3, #1 801068e: d148 bne.n 8010722 { /* Enable PLL I2S only if not active */ if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) 8010690: 4b2e ldr r3, [pc, #184] @ (801074c ) 8010692: 681b ldr r3, [r3, #0] 8010694: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010698: 2b00 cmp r3, #0 801069a: d138 bne.n 801070e assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); /* Prediv2 can be written only when the PLL2 is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 801069c: 4b2b ldr r3, [pc, #172] @ (801074c ) 801069e: 681b ldr r3, [r3, #0] 80106a0: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 80106a4: 2b00 cmp r3, #0 80106a6: d009 beq.n 80106bc (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) 80106a8: 4b28 ldr r3, [pc, #160] @ (801074c ) 80106aa: 6adb ldr r3, [r3, #44] @ 0x2c 80106ac: f003 02f0 and.w r2, r3, #240 @ 0xf0 80106b0: 687b ldr r3, [r7, #4] 80106b2: 699b ldr r3, [r3, #24] if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 80106b4: 429a cmp r2, r3 80106b6: d001 beq.n 80106bc { return HAL_ERROR; 80106b8: 2301 movs r3, #1 80106ba: e042 b.n 8010742 } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); 80106bc: 4b23 ldr r3, [pc, #140] @ (801074c ) 80106be: 6adb ldr r3, [r3, #44] @ 0x2c 80106c0: f023 02f0 bic.w r2, r3, #240 @ 0xf0 80106c4: 687b ldr r3, [r7, #4] 80106c6: 699b ldr r3, [r3, #24] 80106c8: 4920 ldr r1, [pc, #128] @ (801074c ) 80106ca: 4313 orrs r3, r2 80106cc: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); 80106ce: 4b1f ldr r3, [pc, #124] @ (801074c ) 80106d0: 6adb ldr r3, [r3, #44] @ 0x2c 80106d2: f423 4270 bic.w r2, r3, #61440 @ 0xf000 80106d6: 687b ldr r3, [r7, #4] 80106d8: 695b ldr r3, [r3, #20] 80106da: 491c ldr r1, [pc, #112] @ (801074c ) 80106dc: 4313 orrs r3, r2 80106de: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); 80106e0: 4b1d ldr r3, [pc, #116] @ (8010758 ) 80106e2: 2201 movs r2, #1 80106e4: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80106e6: f7fd f8f5 bl 800d8d4 80106ea: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 80106ec: e008 b.n 8010700 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 80106ee: f7fd f8f1 bl 800d8d4 80106f2: 4602 mov r2, r0 80106f4: 697b ldr r3, [r7, #20] 80106f6: 1ad3 subs r3, r2, r3 80106f8: 2b64 cmp r3, #100 @ 0x64 80106fa: d901 bls.n 8010700 { return HAL_TIMEOUT; 80106fc: 2303 movs r3, #3 80106fe: e020 b.n 8010742 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8010700: 4b12 ldr r3, [pc, #72] @ (801074c ) 8010702: 681b ldr r3, [r3, #0] 8010704: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8010708: 2b00 cmp r3, #0 801070a: d0f0 beq.n 80106ee 801070c: e009 b.n 8010722 } } else { /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) 801070e: 4b0f ldr r3, [pc, #60] @ (801074c ) 8010710: 6adb ldr r3, [r3, #44] @ 0x2c 8010712: f403 4270 and.w r2, r3, #61440 @ 0xf000 8010716: 687b ldr r3, [r7, #4] 8010718: 695b ldr r3, [r3, #20] 801071a: 429a cmp r2, r3 801071c: d001 beq.n 8010722 { return HAL_ERROR; 801071e: 2301 movs r3, #1 8010720: e00f b.n 8010742 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8010722: 687b ldr r3, [r7, #4] 8010724: 681b ldr r3, [r3, #0] 8010726: f003 0310 and.w r3, r3, #16 801072a: 2b00 cmp r3, #0 801072c: d008 beq.n 8010740 { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 801072e: 4b07 ldr r3, [pc, #28] @ (801074c ) 8010730: 685b ldr r3, [r3, #4] 8010732: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 8010736: 687b ldr r3, [r7, #4] 8010738: 69db ldr r3, [r3, #28] 801073a: 4904 ldr r1, [pc, #16] @ (801074c ) 801073c: 4313 orrs r3, r2 801073e: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 8010740: 2300 movs r3, #0 } 8010742: 4618 mov r0, r3 8010744: 3720 adds r7, #32 8010746: 46bd mov sp, r7 8010748: bd80 pop {r7, pc} 801074a: bf00 nop 801074c: 40021000 .word 0x40021000 8010750: 40007000 .word 0x40007000 8010754: 42420440 .word 0x42420440 8010758: 42420070 .word 0x42420070 0801075c : * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 801075c: b580 push {r7, lr} 801075e: b08a sub sp, #40 @ 0x28 8010760: af00 add r7, sp, #0 8010762: 6078 str r0, [r7, #4] #if defined(STM32F105xC) || defined(STM32F107xC) static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; 8010764: 2300 movs r3, #0 8010766: 61fb str r3, [r7, #28] 8010768: 2300 movs r3, #0 801076a: 627b str r3, [r7, #36] @ 0x24 801076c: 2300 movs r3, #0 801076e: 61bb str r3, [r7, #24] uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; 8010770: 2300 movs r3, #0 8010772: 617b str r3, [r7, #20] 8010774: 2300 movs r3, #0 8010776: 613b str r3, [r7, #16] 8010778: 2300 movs r3, #0 801077a: 60fb str r3, [r7, #12] static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; static const uint8_t aPredivFactorTable[2U] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 801077c: 2300 movs r3, #0 801077e: 60bb str r3, [r7, #8] 8010780: 2300 movs r3, #0 8010782: 623b str r3, [r7, #32] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 8010784: 687b ldr r3, [r7, #4] 8010786: 3b01 subs r3, #1 8010788: 2b0f cmp r3, #15 801078a: f200 811d bhi.w 80109c8 801078e: a201 add r2, pc, #4 @ (adr r2, 8010794 ) 8010790: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8010794: 08010949 .word 0x08010949 8010798: 080109ad .word 0x080109ad 801079c: 080109c9 .word 0x080109c9 80107a0: 080108a7 .word 0x080108a7 80107a4: 080109c9 .word 0x080109c9 80107a8: 080109c9 .word 0x080109c9 80107ac: 080109c9 .word 0x080109c9 80107b0: 080108f9 .word 0x080108f9 80107b4: 080109c9 .word 0x080109c9 80107b8: 080109c9 .word 0x080109c9 80107bc: 080109c9 .word 0x080109c9 80107c0: 080109c9 .word 0x080109c9 80107c4: 080109c9 .word 0x080109c9 80107c8: 080109c9 .word 0x080109c9 80107cc: 080109c9 .word 0x080109c9 80107d0: 080107d5 .word 0x080107d5 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_USB: { /* Get RCC configuration ------------------------------------------------------*/ temp_reg = RCC->CFGR; 80107d4: 4b83 ldr r3, [pc, #524] @ (80109e4 ) 80107d6: 685b ldr r3, [r3, #4] 80107d8: 60bb str r3, [r7, #8] /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) 80107da: 4b82 ldr r3, [pc, #520] @ (80109e4 ) 80107dc: 681b ldr r3, [r3, #0] 80107de: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80107e2: 2b00 cmp r3, #0 80107e4: f000 80f2 beq.w 80109cc { pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 80107e8: 68bb ldr r3, [r7, #8] 80107ea: 0c9b lsrs r3, r3, #18 80107ec: f003 030f and.w r3, r3, #15 80107f0: 4a7d ldr r2, [pc, #500] @ (80109e8 ) 80107f2: 5cd3 ldrb r3, [r2, r3] 80107f4: 61bb str r3, [r7, #24] if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 80107f6: 68bb ldr r3, [r7, #8] 80107f8: f403 3380 and.w r3, r3, #65536 @ 0x10000 80107fc: 2b00 cmp r3, #0 80107fe: d03b beq.n 8010878 { #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ || defined(STM32F100xE) prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 8010800: 4b78 ldr r3, [pc, #480] @ (80109e4 ) 8010802: 6adb ldr r3, [r3, #44] @ 0x2c 8010804: f003 030f and.w r3, r3, #15 8010808: 4a78 ldr r2, [pc, #480] @ (80109ec ) 801080a: 5cd3 ldrb r3, [r2, r3] 801080c: 61fb str r3, [r7, #28] #else prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 801080e: 4b75 ldr r3, [pc, #468] @ (80109e4 ) 8010810: 6adb ldr r3, [r3, #44] @ 0x2c 8010812: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010816: 2b00 cmp r3, #0 8010818: d01c beq.n 8010854 { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 801081a: 4b72 ldr r3, [pc, #456] @ (80109e4 ) 801081c: 6adb ldr r3, [r3, #44] @ 0x2c 801081e: 091b lsrs r3, r3, #4 8010820: f003 030f and.w r3, r3, #15 8010824: 3301 adds r3, #1 8010826: 60fb str r3, [r7, #12] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 8010828: 4b6e ldr r3, [pc, #440] @ (80109e4 ) 801082a: 6adb ldr r3, [r3, #44] @ 0x2c 801082c: 0a1b lsrs r3, r3, #8 801082e: f003 030f and.w r3, r3, #15 8010832: 3302 adds r3, #2 8010834: 617b str r3, [r7, #20] pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); 8010836: 4a6e ldr r2, [pc, #440] @ (80109f0 ) 8010838: 68fb ldr r3, [r7, #12] 801083a: fbb2 f3f3 udiv r3, r2, r3 801083e: 697a ldr r2, [r7, #20] 8010840: fb03 f202 mul.w r2, r3, r2 8010844: 69fb ldr r3, [r7, #28] 8010846: fbb2 f2f3 udiv r2, r2, r3 801084a: 69bb ldr r3, [r7, #24] 801084c: fb02 f303 mul.w r3, r2, r3 8010850: 627b str r3, [r7, #36] @ 0x24 8010852: e007 b.n 8010864 } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); 8010854: 4a66 ldr r2, [pc, #408] @ (80109f0 ) 8010856: 69fb ldr r3, [r7, #28] 8010858: fbb2 f2f3 udiv r2, r2, r3 801085c: 69bb ldr r3, [r7, #24] 801085e: fb02 f303 mul.w r3, r2, r3 8010862: 627b str r3, [r7, #36] @ 0x24 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 8010864: 4b60 ldr r3, [pc, #384] @ (80109e8 ) 8010866: 7b5b ldrb r3, [r3, #13] 8010868: 461a mov r2, r3 801086a: 69bb ldr r3, [r7, #24] 801086c: 4293 cmp r3, r2 801086e: d108 bne.n 8010882 { pllclk = pllclk / 2; 8010870: 6a7b ldr r3, [r7, #36] @ 0x24 8010872: 085b lsrs r3, r3, #1 8010874: 627b str r3, [r7, #36] @ 0x24 8010876: e004 b.n 8010882 #endif /* STM32F105xC || STM32F107xC */ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8010878: 69bb ldr r3, [r7, #24] 801087a: 4a5e ldr r2, [pc, #376] @ (80109f4 ) 801087c: fb02 f303 mul.w r3, r2, r3 8010880: 627b str r3, [r7, #36] @ 0x24 } /* Calcul of the USB frequency*/ #if defined(STM32F105xC) || defined(STM32F107xC) /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) 8010882: 4b58 ldr r3, [pc, #352] @ (80109e4 ) 8010884: 685b ldr r3, [r3, #4] 8010886: f403 0380 and.w r3, r3, #4194304 @ 0x400000 801088a: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 801088e: d102 bne.n 8010896 { /* Prescaler of 2 selected for USB */ frequency = pllclk; 8010890: 6a7b ldr r3, [r7, #36] @ 0x24 8010892: 623b str r3, [r7, #32] /* Prescaler of 1.5 selected for USB */ frequency = (pllclk * 2) / 3; } #endif } break; 8010894: e09a b.n 80109cc frequency = (2 * pllclk) / 3; 8010896: 6a7b ldr r3, [r7, #36] @ 0x24 8010898: 005b lsls r3, r3, #1 801089a: 4a57 ldr r2, [pc, #348] @ (80109f8 ) 801089c: fba2 2303 umull r2, r3, r2, r3 80108a0: 085b lsrs r3, r3, #1 80108a2: 623b str r3, [r7, #32] break; 80108a4: e092 b.n 80109cc { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) 80108a6: 4b4f ldr r3, [pc, #316] @ (80109e4 ) 80108a8: 6adb ldr r3, [r3, #44] @ 0x2c 80108aa: f403 3300 and.w r3, r3, #131072 @ 0x20000 80108ae: 2b00 cmp r3, #0 80108b0: d103 bne.n 80108ba { /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); 80108b2: f7ff fd15 bl 80102e0 80108b6: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 80108b8: e08a b.n 80109d0 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 80108ba: 4b4a ldr r3, [pc, #296] @ (80109e4 ) 80108bc: 681b ldr r3, [r3, #0] 80108be: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80108c2: 2b00 cmp r3, #0 80108c4: f000 8084 beq.w 80109d0 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 80108c8: 4b46 ldr r3, [pc, #280] @ (80109e4 ) 80108ca: 6adb ldr r3, [r3, #44] @ 0x2c 80108cc: 091b lsrs r3, r3, #4 80108ce: f003 030f and.w r3, r3, #15 80108d2: 3301 adds r3, #1 80108d4: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 80108d6: 4b43 ldr r3, [pc, #268] @ (80109e4 ) 80108d8: 6adb ldr r3, [r3, #44] @ 0x2c 80108da: 0b1b lsrs r3, r3, #12 80108dc: f003 030f and.w r3, r3, #15 80108e0: 3302 adds r3, #2 80108e2: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 80108e4: 4a42 ldr r2, [pc, #264] @ (80109f0 ) 80108e6: 68fb ldr r3, [r7, #12] 80108e8: fbb2 f3f3 udiv r3, r2, r3 80108ec: 693a ldr r2, [r7, #16] 80108ee: fb02 f303 mul.w r3, r2, r3 80108f2: 005b lsls r3, r3, #1 80108f4: 623b str r3, [r7, #32] break; 80108f6: e06b b.n 80109d0 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) 80108f8: 4b3a ldr r3, [pc, #232] @ (80109e4 ) 80108fa: 6adb ldr r3, [r3, #44] @ 0x2c 80108fc: f403 2380 and.w r3, r3, #262144 @ 0x40000 8010900: 2b00 cmp r3, #0 8010902: d103 bne.n 801090c { /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); 8010904: f7ff fcec bl 80102e0 8010908: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 801090a: e063 b.n 80109d4 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 801090c: 4b35 ldr r3, [pc, #212] @ (80109e4 ) 801090e: 681b ldr r3, [r3, #0] 8010910: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010914: 2b00 cmp r3, #0 8010916: d05d beq.n 80109d4 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8010918: 4b32 ldr r3, [pc, #200] @ (80109e4 ) 801091a: 6adb ldr r3, [r3, #44] @ 0x2c 801091c: 091b lsrs r3, r3, #4 801091e: f003 030f and.w r3, r3, #15 8010922: 3301 adds r3, #1 8010924: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 8010926: 4b2f ldr r3, [pc, #188] @ (80109e4 ) 8010928: 6adb ldr r3, [r3, #44] @ 0x2c 801092a: 0b1b lsrs r3, r3, #12 801092c: f003 030f and.w r3, r3, #15 8010930: 3302 adds r3, #2 8010932: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8010934: 4a2e ldr r2, [pc, #184] @ (80109f0 ) 8010936: 68fb ldr r3, [r7, #12] 8010938: fbb2 f3f3 udiv r3, r2, r3 801093c: 693a ldr r2, [r7, #16] 801093e: fb02 f303 mul.w r3, r2, r3 8010942: 005b lsls r3, r3, #1 8010944: 623b str r3, [r7, #32] break; 8010946: e045 b.n 80109d4 } #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ case RCC_PERIPHCLK_RTC: { /* Get RCC BDCR configuration ------------------------------------------------------*/ temp_reg = RCC->BDCR; 8010948: 4b26 ldr r3, [pc, #152] @ (80109e4 ) 801094a: 6a1b ldr r3, [r3, #32] 801094c: 60bb str r3, [r7, #8] /* Check if LSE is ready if RTC clock selection is LSE */ if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 801094e: 68bb ldr r3, [r7, #8] 8010950: f403 7340 and.w r3, r3, #768 @ 0x300 8010954: f5b3 7f80 cmp.w r3, #256 @ 0x100 8010958: d108 bne.n 801096c 801095a: 68bb ldr r3, [r7, #8] 801095c: f003 0302 and.w r3, r3, #2 8010960: 2b00 cmp r3, #0 8010962: d003 beq.n 801096c { frequency = LSE_VALUE; 8010964: f44f 4300 mov.w r3, #32768 @ 0x8000 8010968: 623b str r3, [r7, #32] 801096a: e01e b.n 80109aa } /* Check if LSI is ready if RTC clock selection is LSI */ else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 801096c: 68bb ldr r3, [r7, #8] 801096e: f403 7340 and.w r3, r3, #768 @ 0x300 8010972: f5b3 7f00 cmp.w r3, #512 @ 0x200 8010976: d109 bne.n 801098c 8010978: 4b1a ldr r3, [pc, #104] @ (80109e4 ) 801097a: 6a5b ldr r3, [r3, #36] @ 0x24 801097c: f003 0302 and.w r3, r3, #2 8010980: 2b00 cmp r3, #0 8010982: d003 beq.n 801098c { frequency = LSI_VALUE; 8010984: f649 4340 movw r3, #40000 @ 0x9c40 8010988: 623b str r3, [r7, #32] 801098a: e00e b.n 80109aa } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 801098c: 68bb ldr r3, [r7, #8] 801098e: f403 7340 and.w r3, r3, #768 @ 0x300 8010992: f5b3 7f40 cmp.w r3, #768 @ 0x300 8010996: d11f bne.n 80109d8 8010998: 4b12 ldr r3, [pc, #72] @ (80109e4 ) 801099a: 681b ldr r3, [r3, #0] 801099c: f403 3300 and.w r3, r3, #131072 @ 0x20000 80109a0: 2b00 cmp r3, #0 80109a2: d019 beq.n 80109d8 { frequency = HSE_VALUE / 128U; 80109a4: 4b15 ldr r3, [pc, #84] @ (80109fc ) 80109a6: 623b str r3, [r7, #32] /* Clock not enabled for RTC*/ else { /* nothing to do: frequency already initialized to 0U */ } break; 80109a8: e016 b.n 80109d8 80109aa: e015 b.n 80109d8 } case RCC_PERIPHCLK_ADC: { frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 80109ac: f7ff fd72 bl 8010494 80109b0: 4602 mov r2, r0 80109b2: 4b0c ldr r3, [pc, #48] @ (80109e4 ) 80109b4: 685b ldr r3, [r3, #4] 80109b6: 0b9b lsrs r3, r3, #14 80109b8: f003 0303 and.w r3, r3, #3 80109bc: 3301 adds r3, #1 80109be: 005b lsls r3, r3, #1 80109c0: fbb2 f3f3 udiv r3, r2, r3 80109c4: 623b str r3, [r7, #32] break; 80109c6: e008 b.n 80109da } default: { break; 80109c8: bf00 nop 80109ca: e006 b.n 80109da break; 80109cc: bf00 nop 80109ce: e004 b.n 80109da break; 80109d0: bf00 nop 80109d2: e002 b.n 80109da break; 80109d4: bf00 nop 80109d6: e000 b.n 80109da break; 80109d8: bf00 nop } } return (frequency); 80109da: 6a3b ldr r3, [r7, #32] } 80109dc: 4618 mov r0, r3 80109de: 3728 adds r7, #40 @ 0x28 80109e0: 46bd mov sp, r7 80109e2: bd80 pop {r7, pc} 80109e4: 40021000 .word 0x40021000 80109e8: 080143d4 .word 0x080143d4 80109ec: 080143e4 .word 0x080143e4 80109f0: 017d7840 .word 0x017d7840 80109f4: 003d0900 .word 0x003d0900 80109f8: aaaaaaab .word 0xaaaaaaab 80109fc: 0002faf0 .word 0x0002faf0 08010a00 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { 8010a00: b580 push {r7, lr} 8010a02: b084 sub sp, #16 8010a04: af00 add r7, sp, #0 8010a06: 6078 str r0, [r7, #4] uint32_t prescaler = 0U; 8010a08: 2300 movs r3, #0 8010a0a: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8010a0c: 687b ldr r3, [r7, #4] 8010a0e: 2b00 cmp r3, #0 8010a10: d101 bne.n 8010a16 { return HAL_ERROR; 8010a12: 2301 movs r3, #1 8010a14: e07a b.n 8010b0c { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else if (hrtc->State == HAL_RTC_STATE_RESET) 8010a16: 687b ldr r3, [r7, #4] 8010a18: 7c5b ldrb r3, [r3, #17] 8010a1a: b2db uxtb r3, r3 8010a1c: 2b00 cmp r3, #0 8010a1e: d105 bne.n 8010a2c { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; 8010a20: 687b ldr r3, [r7, #4] 8010a22: 2200 movs r2, #0 8010a24: 741a strb r2, [r3, #16] /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); 8010a26: 6878 ldr r0, [r7, #4] 8010a28: f7fa ff82 bl 800b930 } #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; 8010a2c: 687b ldr r3, [r7, #4] 8010a2e: 2202 movs r2, #2 8010a30: 745a strb r2, [r3, #17] /* Waiting for synchro */ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 8010a32: 6878 ldr r0, [r7, #4] 8010a34: f000 f870 bl 8010b18 8010a38: 4603 mov r3, r0 8010a3a: 2b00 cmp r3, #0 8010a3c: d004 beq.n 8010a48 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8010a3e: 687b ldr r3, [r7, #4] 8010a40: 2204 movs r2, #4 8010a42: 745a strb r2, [r3, #17] return HAL_ERROR; 8010a44: 2301 movs r3, #1 8010a46: e061 b.n 8010b0c } /* Set Initialization mode */ if (RTC_EnterInitMode(hrtc) != HAL_OK) 8010a48: 6878 ldr r0, [r7, #4] 8010a4a: f000 f892 bl 8010b72 8010a4e: 4603 mov r3, r0 8010a50: 2b00 cmp r3, #0 8010a52: d004 beq.n 8010a5e { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8010a54: 687b ldr r3, [r7, #4] 8010a56: 2204 movs r2, #4 8010a58: 745a strb r2, [r3, #17] return HAL_ERROR; 8010a5a: 2301 movs r3, #1 8010a5c: e056 b.n 8010b0c } else { /* Clear Flags Bits */ CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); 8010a5e: 687b ldr r3, [r7, #4] 8010a60: 681b ldr r3, [r3, #0] 8010a62: 685a ldr r2, [r3, #4] 8010a64: 687b ldr r3, [r7, #4] 8010a66: 681b ldr r3, [r3, #0] 8010a68: f022 0207 bic.w r2, r2, #7 8010a6c: 605a str r2, [r3, #4] if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) 8010a6e: 687b ldr r3, [r7, #4] 8010a70: 689b ldr r3, [r3, #8] 8010a72: 2b00 cmp r3, #0 8010a74: d005 beq.n 8010a82 { /* Disable the selected Tamper pin */ CLEAR_BIT(BKP->CR, BKP_CR_TPE); 8010a76: 4b27 ldr r3, [pc, #156] @ (8010b14 ) 8010a78: 6b1b ldr r3, [r3, #48] @ 0x30 8010a7a: 4a26 ldr r2, [pc, #152] @ (8010b14 ) 8010a7c: f023 0301 bic.w r3, r3, #1 8010a80: 6313 str r3, [r2, #48] @ 0x30 } /* Set the signal which will be routed to RTC Tamper pin*/ MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); 8010a82: 4b24 ldr r3, [pc, #144] @ (8010b14 ) 8010a84: 6adb ldr r3, [r3, #44] @ 0x2c 8010a86: f423 7260 bic.w r2, r3, #896 @ 0x380 8010a8a: 687b ldr r3, [r7, #4] 8010a8c: 689b ldr r3, [r3, #8] 8010a8e: 4921 ldr r1, [pc, #132] @ (8010b14 ) 8010a90: 4313 orrs r3, r2 8010a92: 62cb str r3, [r1, #44] @ 0x2c if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) 8010a94: 687b ldr r3, [r7, #4] 8010a96: 685b ldr r3, [r3, #4] 8010a98: f1b3 3fff cmp.w r3, #4294967295 8010a9c: d003 beq.n 8010aa6 { /* RTC Prescaler provided directly by end-user*/ prescaler = hrtc->Init.AsynchPrediv; 8010a9e: 687b ldr r3, [r7, #4] 8010aa0: 685b ldr r3, [r3, #4] 8010aa2: 60fb str r3, [r7, #12] 8010aa4: e00e b.n 8010ac4 } else { /* RTC Prescaler will be automatically calculated to get 1 second timebase */ /* Get the RTCCLK frequency */ prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); 8010aa6: 2001 movs r0, #1 8010aa8: f7ff fe58 bl 801075c 8010aac: 60f8 str r0, [r7, #12] /* Check that RTC clock is enabled*/ if (prescaler == 0U) 8010aae: 68fb ldr r3, [r7, #12] 8010ab0: 2b00 cmp r3, #0 8010ab2: d104 bne.n 8010abe { /* Should not happen. Frequency is not available*/ hrtc->State = HAL_RTC_STATE_ERROR; 8010ab4: 687b ldr r3, [r7, #4] 8010ab6: 2204 movs r2, #4 8010ab8: 745a strb r2, [r3, #17] return HAL_ERROR; 8010aba: 2301 movs r3, #1 8010abc: e026 b.n 8010b0c } else { /* RTC period = RTCCLK/(RTC_PR + 1) */ prescaler = prescaler - 1U; 8010abe: 68fb ldr r3, [r7, #12] 8010ac0: 3b01 subs r3, #1 8010ac2: 60fb str r3, [r7, #12] } } /* Configure the RTC_PRLH / RTC_PRLL */ WRITE_REG(hrtc->Instance->PRLH, ((prescaler >> 16U) & RTC_PRLH_PRL)); 8010ac4: 68fb ldr r3, [r7, #12] 8010ac6: 0c1a lsrs r2, r3, #16 8010ac8: 687b ldr r3, [r7, #4] 8010aca: 681b ldr r3, [r3, #0] 8010acc: f002 020f and.w r2, r2, #15 8010ad0: 609a str r2, [r3, #8] WRITE_REG(hrtc->Instance->PRLL, (prescaler & RTC_PRLL_PRL)); 8010ad2: 687b ldr r3, [r7, #4] 8010ad4: 681b ldr r3, [r3, #0] 8010ad6: 68fa ldr r2, [r7, #12] 8010ad8: b292 uxth r2, r2 8010ada: 60da str r2, [r3, #12] /* Wait for synchro */ if (RTC_ExitInitMode(hrtc) != HAL_OK) 8010adc: 6878 ldr r0, [r7, #4] 8010ade: f000 f870 bl 8010bc2 8010ae2: 4603 mov r3, r0 8010ae4: 2b00 cmp r3, #0 8010ae6: d004 beq.n 8010af2 { hrtc->State = HAL_RTC_STATE_ERROR; 8010ae8: 687b ldr r3, [r7, #4] 8010aea: 2204 movs r2, #4 8010aec: 745a strb r2, [r3, #17] return HAL_ERROR; 8010aee: 2301 movs r3, #1 8010af0: e00c b.n 8010b0c } /* Initialize date to 1st of January 2000 */ hrtc->DateToUpdate.Year = 0x00U; 8010af2: 687b ldr r3, [r7, #4] 8010af4: 2200 movs r2, #0 8010af6: 73da strb r2, [r3, #15] hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; 8010af8: 687b ldr r3, [r7, #4] 8010afa: 2201 movs r2, #1 8010afc: 735a strb r2, [r3, #13] hrtc->DateToUpdate.Date = 0x01U; 8010afe: 687b ldr r3, [r7, #4] 8010b00: 2201 movs r2, #1 8010b02: 739a strb r2, [r3, #14] /* Set RTC state */ hrtc->State = HAL_RTC_STATE_READY; 8010b04: 687b ldr r3, [r7, #4] 8010b06: 2201 movs r2, #1 8010b08: 745a strb r2, [r3, #17] return HAL_OK; 8010b0a: 2300 movs r3, #0 } } 8010b0c: 4618 mov r0, r3 8010b0e: 3710 adds r7, #16 8010b10: 46bd mov sp, r7 8010b12: bd80 pop {r7, pc} 8010b14: 40006c00 .word 0x40006c00 08010b18 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { 8010b18: b580 push {r7, lr} 8010b1a: b084 sub sp, #16 8010b1c: af00 add r7, sp, #0 8010b1e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8010b20: 2300 movs r3, #0 8010b22: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8010b24: 687b ldr r3, [r7, #4] 8010b26: 2b00 cmp r3, #0 8010b28: d101 bne.n 8010b2e { return HAL_ERROR; 8010b2a: 2301 movs r3, #1 8010b2c: e01d b.n 8010b6a } /* Clear RSF flag */ CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); 8010b2e: 687b ldr r3, [r7, #4] 8010b30: 681b ldr r3, [r3, #0] 8010b32: 685a ldr r2, [r3, #4] 8010b34: 687b ldr r3, [r7, #4] 8010b36: 681b ldr r3, [r3, #0] 8010b38: f022 0208 bic.w r2, r2, #8 8010b3c: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8010b3e: f7fc fec9 bl 800d8d4 8010b42: 60f8 str r0, [r7, #12] /* Wait the registers to be synchronised */ while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8010b44: e009 b.n 8010b5a { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8010b46: f7fc fec5 bl 800d8d4 8010b4a: 4602 mov r2, r0 8010b4c: 68fb ldr r3, [r7, #12] 8010b4e: 1ad3 subs r3, r2, r3 8010b50: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8010b54: d901 bls.n 8010b5a { return HAL_TIMEOUT; 8010b56: 2303 movs r3, #3 8010b58: e007 b.n 8010b6a while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8010b5a: 687b ldr r3, [r7, #4] 8010b5c: 681b ldr r3, [r3, #0] 8010b5e: 685b ldr r3, [r3, #4] 8010b60: f003 0308 and.w r3, r3, #8 8010b64: 2b00 cmp r3, #0 8010b66: d0ee beq.n 8010b46 } } return HAL_OK; 8010b68: 2300 movs r3, #0 } 8010b6a: 4618 mov r0, r3 8010b6c: 3710 adds r7, #16 8010b6e: 46bd mov sp, r7 8010b70: bd80 pop {r7, pc} 08010b72 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { 8010b72: b580 push {r7, lr} 8010b74: b084 sub sp, #16 8010b76: af00 add r7, sp, #0 8010b78: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8010b7a: 2300 movs r3, #0 8010b7c: 60fb str r3, [r7, #12] tickstart = HAL_GetTick(); 8010b7e: f7fc fea9 bl 800d8d4 8010b82: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8010b84: e009 b.n 8010b9a { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8010b86: f7fc fea5 bl 800d8d4 8010b8a: 4602 mov r2, r0 8010b8c: 68fb ldr r3, [r7, #12] 8010b8e: 1ad3 subs r3, r2, r3 8010b90: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8010b94: d901 bls.n 8010b9a { return HAL_TIMEOUT; 8010b96: 2303 movs r3, #3 8010b98: e00f b.n 8010bba while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8010b9a: 687b ldr r3, [r7, #4] 8010b9c: 681b ldr r3, [r3, #0] 8010b9e: 685b ldr r3, [r3, #4] 8010ba0: f003 0320 and.w r3, r3, #32 8010ba4: 2b00 cmp r3, #0 8010ba6: d0ee beq.n 8010b86 } } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 8010ba8: 687b ldr r3, [r7, #4] 8010baa: 681b ldr r3, [r3, #0] 8010bac: 685a ldr r2, [r3, #4] 8010bae: 687b ldr r3, [r7, #4] 8010bb0: 681b ldr r3, [r3, #0] 8010bb2: f042 0210 orr.w r2, r2, #16 8010bb6: 605a str r2, [r3, #4] return HAL_OK; 8010bb8: 2300 movs r3, #0 } 8010bba: 4618 mov r0, r3 8010bbc: 3710 adds r7, #16 8010bbe: 46bd mov sp, r7 8010bc0: bd80 pop {r7, pc} 08010bc2 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) { 8010bc2: b580 push {r7, lr} 8010bc4: b084 sub sp, #16 8010bc6: af00 add r7, sp, #0 8010bc8: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8010bca: 2300 movs r3, #0 8010bcc: 60fb str r3, [r7, #12] /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 8010bce: 687b ldr r3, [r7, #4] 8010bd0: 681b ldr r3, [r3, #0] 8010bd2: 685a ldr r2, [r3, #4] 8010bd4: 687b ldr r3, [r7, #4] 8010bd6: 681b ldr r3, [r3, #0] 8010bd8: f022 0210 bic.w r2, r2, #16 8010bdc: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8010bde: f7fc fe79 bl 800d8d4 8010be2: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8010be4: e009 b.n 8010bfa { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8010be6: f7fc fe75 bl 800d8d4 8010bea: 4602 mov r2, r0 8010bec: 68fb ldr r3, [r7, #12] 8010bee: 1ad3 subs r3, r2, r3 8010bf0: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8010bf4: d901 bls.n 8010bfa { return HAL_TIMEOUT; 8010bf6: 2303 movs r3, #3 8010bf8: e007 b.n 8010c0a while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8010bfa: 687b ldr r3, [r7, #4] 8010bfc: 681b ldr r3, [r3, #0] 8010bfe: 685b ldr r3, [r3, #4] 8010c00: f003 0320 and.w r3, r3, #32 8010c04: 2b00 cmp r3, #0 8010c06: d0ee beq.n 8010be6 } } return HAL_OK; 8010c08: 2300 movs r3, #0 } 8010c0a: 4618 mov r0, r3 8010c0c: 3710 adds r7, #16 8010c0e: 46bd mov sp, r7 8010c10: bd80 pop {r7, pc} 08010c12 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8010c12: b580 push {r7, lr} 8010c14: b082 sub sp, #8 8010c16: af00 add r7, sp, #0 8010c18: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8010c1a: 687b ldr r3, [r7, #4] 8010c1c: 2b00 cmp r3, #0 8010c1e: d101 bne.n 8010c24 { return HAL_ERROR; 8010c20: 2301 movs r3, #1 8010c22: e041 b.n 8010ca8 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8010c24: 687b ldr r3, [r7, #4] 8010c26: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8010c2a: b2db uxtb r3, r3 8010c2c: 2b00 cmp r3, #0 8010c2e: d106 bne.n 8010c3e { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8010c30: 687b ldr r3, [r7, #4] 8010c32: 2200 movs r2, #0 8010c34: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8010c38: 6878 ldr r0, [r7, #4] 8010c3a: f7fc fb3b bl 800d2b4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8010c3e: 687b ldr r3, [r7, #4] 8010c40: 2202 movs r2, #2 8010c42: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8010c46: 687b ldr r3, [r7, #4] 8010c48: 681a ldr r2, [r3, #0] 8010c4a: 687b ldr r3, [r7, #4] 8010c4c: 3304 adds r3, #4 8010c4e: 4619 mov r1, r3 8010c50: 4610 mov r0, r2 8010c52: f000 fcc3 bl 80115dc /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8010c56: 687b ldr r3, [r7, #4] 8010c58: 2201 movs r2, #1 8010c5a: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8010c5e: 687b ldr r3, [r7, #4] 8010c60: 2201 movs r2, #1 8010c62: f883 203e strb.w r2, [r3, #62] @ 0x3e 8010c66: 687b ldr r3, [r7, #4] 8010c68: 2201 movs r2, #1 8010c6a: f883 203f strb.w r2, [r3, #63] @ 0x3f 8010c6e: 687b ldr r3, [r7, #4] 8010c70: 2201 movs r2, #1 8010c72: f883 2040 strb.w r2, [r3, #64] @ 0x40 8010c76: 687b ldr r3, [r7, #4] 8010c78: 2201 movs r2, #1 8010c7a: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8010c7e: 687b ldr r3, [r7, #4] 8010c80: 2201 movs r2, #1 8010c82: f883 2042 strb.w r2, [r3, #66] @ 0x42 8010c86: 687b ldr r3, [r7, #4] 8010c88: 2201 movs r2, #1 8010c8a: f883 2043 strb.w r2, [r3, #67] @ 0x43 8010c8e: 687b ldr r3, [r7, #4] 8010c90: 2201 movs r2, #1 8010c92: f883 2044 strb.w r2, [r3, #68] @ 0x44 8010c96: 687b ldr r3, [r7, #4] 8010c98: 2201 movs r2, #1 8010c9a: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8010c9e: 687b ldr r3, [r7, #4] 8010ca0: 2201 movs r2, #1 8010ca2: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8010ca6: 2300 movs r3, #0 } 8010ca8: 4618 mov r0, r3 8010caa: 3708 adds r7, #8 8010cac: 46bd mov sp, r7 8010cae: bd80 pop {r7, pc} 08010cb0 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { 8010cb0: b580 push {r7, lr} 8010cb2: b084 sub sp, #16 8010cb4: af00 add r7, sp, #0 8010cb6: 6078 str r0, [r7, #4] 8010cb8: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8010cba: 2300 movs r3, #0 8010cbc: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 8010cbe: 683b ldr r3, [r7, #0] 8010cc0: 2b00 cmp r3, #0 8010cc2: d109 bne.n 8010cd8 8010cc4: 687b ldr r3, [r7, #4] 8010cc6: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8010cca: b2db uxtb r3, r3 8010ccc: 2b01 cmp r3, #1 8010cce: bf14 ite ne 8010cd0: 2301 movne r3, #1 8010cd2: 2300 moveq r3, #0 8010cd4: b2db uxtb r3, r3 8010cd6: e022 b.n 8010d1e 8010cd8: 683b ldr r3, [r7, #0] 8010cda: 2b04 cmp r3, #4 8010cdc: d109 bne.n 8010cf2 8010cde: 687b ldr r3, [r7, #4] 8010ce0: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8010ce4: b2db uxtb r3, r3 8010ce6: 2b01 cmp r3, #1 8010ce8: bf14 ite ne 8010cea: 2301 movne r3, #1 8010cec: 2300 moveq r3, #0 8010cee: b2db uxtb r3, r3 8010cf0: e015 b.n 8010d1e 8010cf2: 683b ldr r3, [r7, #0] 8010cf4: 2b08 cmp r3, #8 8010cf6: d109 bne.n 8010d0c 8010cf8: 687b ldr r3, [r7, #4] 8010cfa: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8010cfe: b2db uxtb r3, r3 8010d00: 2b01 cmp r3, #1 8010d02: bf14 ite ne 8010d04: 2301 movne r3, #1 8010d06: 2300 moveq r3, #0 8010d08: b2db uxtb r3, r3 8010d0a: e008 b.n 8010d1e 8010d0c: 687b ldr r3, [r7, #4] 8010d0e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8010d12: b2db uxtb r3, r3 8010d14: 2b01 cmp r3, #1 8010d16: bf14 ite ne 8010d18: 2301 movne r3, #1 8010d1a: 2300 moveq r3, #0 8010d1c: b2db uxtb r3, r3 8010d1e: 2b00 cmp r3, #0 8010d20: d001 beq.n 8010d26 { return HAL_ERROR; 8010d22: 2301 movs r3, #1 8010d24: e0ae b.n 8010e84 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8010d26: 683b ldr r3, [r7, #0] 8010d28: 2b00 cmp r3, #0 8010d2a: d104 bne.n 8010d36 8010d2c: 687b ldr r3, [r7, #4] 8010d2e: 2202 movs r2, #2 8010d30: f883 203e strb.w r2, [r3, #62] @ 0x3e 8010d34: e013 b.n 8010d5e 8010d36: 683b ldr r3, [r7, #0] 8010d38: 2b04 cmp r3, #4 8010d3a: d104 bne.n 8010d46 8010d3c: 687b ldr r3, [r7, #4] 8010d3e: 2202 movs r2, #2 8010d40: f883 203f strb.w r2, [r3, #63] @ 0x3f 8010d44: e00b b.n 8010d5e 8010d46: 683b ldr r3, [r7, #0] 8010d48: 2b08 cmp r3, #8 8010d4a: d104 bne.n 8010d56 8010d4c: 687b ldr r3, [r7, #4] 8010d4e: 2202 movs r2, #2 8010d50: f883 2040 strb.w r2, [r3, #64] @ 0x40 8010d54: e003 b.n 8010d5e 8010d56: 687b ldr r3, [r7, #4] 8010d58: 2202 movs r2, #2 8010d5a: f883 2041 strb.w r2, [r3, #65] @ 0x41 switch (Channel) 8010d5e: 683b ldr r3, [r7, #0] 8010d60: 2b0c cmp r3, #12 8010d62: d841 bhi.n 8010de8 8010d64: a201 add r2, pc, #4 @ (adr r2, 8010d6c ) 8010d66: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8010d6a: bf00 nop 8010d6c: 08010da1 .word 0x08010da1 8010d70: 08010de9 .word 0x08010de9 8010d74: 08010de9 .word 0x08010de9 8010d78: 08010de9 .word 0x08010de9 8010d7c: 08010db3 .word 0x08010db3 8010d80: 08010de9 .word 0x08010de9 8010d84: 08010de9 .word 0x08010de9 8010d88: 08010de9 .word 0x08010de9 8010d8c: 08010dc5 .word 0x08010dc5 8010d90: 08010de9 .word 0x08010de9 8010d94: 08010de9 .word 0x08010de9 8010d98: 08010de9 .word 0x08010de9 8010d9c: 08010dd7 .word 0x08010dd7 { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 8010da0: 687b ldr r3, [r7, #4] 8010da2: 681b ldr r3, [r3, #0] 8010da4: 68da ldr r2, [r3, #12] 8010da6: 687b ldr r3, [r7, #4] 8010da8: 681b ldr r3, [r3, #0] 8010daa: f042 0202 orr.w r2, r2, #2 8010dae: 60da str r2, [r3, #12] break; 8010db0: e01d b.n 8010dee } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 8010db2: 687b ldr r3, [r7, #4] 8010db4: 681b ldr r3, [r3, #0] 8010db6: 68da ldr r2, [r3, #12] 8010db8: 687b ldr r3, [r7, #4] 8010dba: 681b ldr r3, [r3, #0] 8010dbc: f042 0204 orr.w r2, r2, #4 8010dc0: 60da str r2, [r3, #12] break; 8010dc2: e014 b.n 8010dee } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 8010dc4: 687b ldr r3, [r7, #4] 8010dc6: 681b ldr r3, [r3, #0] 8010dc8: 68da ldr r2, [r3, #12] 8010dca: 687b ldr r3, [r7, #4] 8010dcc: 681b ldr r3, [r3, #0] 8010dce: f042 0208 orr.w r2, r2, #8 8010dd2: 60da str r2, [r3, #12] break; 8010dd4: e00b b.n 8010dee } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 8010dd6: 687b ldr r3, [r7, #4] 8010dd8: 681b ldr r3, [r3, #0] 8010dda: 68da ldr r2, [r3, #12] 8010ddc: 687b ldr r3, [r7, #4] 8010dde: 681b ldr r3, [r3, #0] 8010de0: f042 0210 orr.w r2, r2, #16 8010de4: 60da str r2, [r3, #12] break; 8010de6: e002 b.n 8010dee } default: status = HAL_ERROR; 8010de8: 2301 movs r3, #1 8010dea: 73fb strb r3, [r7, #15] break; 8010dec: bf00 nop } if (status == HAL_OK) 8010dee: 7bfb ldrb r3, [r7, #15] 8010df0: 2b00 cmp r3, #0 8010df2: d146 bne.n 8010e82 { /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 8010df4: 687b ldr r3, [r7, #4] 8010df6: 681b ldr r3, [r3, #0] 8010df8: 2201 movs r2, #1 8010dfa: 6839 ldr r1, [r7, #0] 8010dfc: 4618 mov r0, r3 8010dfe: f000 fe83 bl 8011b08 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8010e02: 687b ldr r3, [r7, #4] 8010e04: 681b ldr r3, [r3, #0] 8010e06: 4a21 ldr r2, [pc, #132] @ (8010e8c ) 8010e08: 4293 cmp r3, r2 8010e0a: d107 bne.n 8010e1c { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8010e0c: 687b ldr r3, [r7, #4] 8010e0e: 681b ldr r3, [r3, #0] 8010e10: 6c5a ldr r2, [r3, #68] @ 0x44 8010e12: 687b ldr r3, [r7, #4] 8010e14: 681b ldr r3, [r3, #0] 8010e16: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8010e1a: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8010e1c: 687b ldr r3, [r7, #4] 8010e1e: 681b ldr r3, [r3, #0] 8010e20: 4a1a ldr r2, [pc, #104] @ (8010e8c ) 8010e22: 4293 cmp r3, r2 8010e24: d013 beq.n 8010e4e 8010e26: 687b ldr r3, [r7, #4] 8010e28: 681b ldr r3, [r3, #0] 8010e2a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8010e2e: d00e beq.n 8010e4e 8010e30: 687b ldr r3, [r7, #4] 8010e32: 681b ldr r3, [r3, #0] 8010e34: 4a16 ldr r2, [pc, #88] @ (8010e90 ) 8010e36: 4293 cmp r3, r2 8010e38: d009 beq.n 8010e4e 8010e3a: 687b ldr r3, [r7, #4] 8010e3c: 681b ldr r3, [r3, #0] 8010e3e: 4a15 ldr r2, [pc, #84] @ (8010e94 ) 8010e40: 4293 cmp r3, r2 8010e42: d004 beq.n 8010e4e 8010e44: 687b ldr r3, [r7, #4] 8010e46: 681b ldr r3, [r3, #0] 8010e48: 4a13 ldr r2, [pc, #76] @ (8010e98 ) 8010e4a: 4293 cmp r3, r2 8010e4c: d111 bne.n 8010e72 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8010e4e: 687b ldr r3, [r7, #4] 8010e50: 681b ldr r3, [r3, #0] 8010e52: 689b ldr r3, [r3, #8] 8010e54: f003 0307 and.w r3, r3, #7 8010e58: 60bb str r3, [r7, #8] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8010e5a: 68bb ldr r3, [r7, #8] 8010e5c: 2b06 cmp r3, #6 8010e5e: d010 beq.n 8010e82 { __HAL_TIM_ENABLE(htim); 8010e60: 687b ldr r3, [r7, #4] 8010e62: 681b ldr r3, [r3, #0] 8010e64: 681a ldr r2, [r3, #0] 8010e66: 687b ldr r3, [r7, #4] 8010e68: 681b ldr r3, [r3, #0] 8010e6a: f042 0201 orr.w r2, r2, #1 8010e6e: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8010e70: e007 b.n 8010e82 } } else { __HAL_TIM_ENABLE(htim); 8010e72: 687b ldr r3, [r7, #4] 8010e74: 681b ldr r3, [r3, #0] 8010e76: 681a ldr r2, [r3, #0] 8010e78: 687b ldr r3, [r7, #4] 8010e7a: 681b ldr r3, [r3, #0] 8010e7c: f042 0201 orr.w r2, r2, #1 8010e80: 601a str r2, [r3, #0] } } /* Return function status */ return status; 8010e82: 7bfb ldrb r3, [r7, #15] } 8010e84: 4618 mov r0, r3 8010e86: 3710 adds r7, #16 8010e88: 46bd mov sp, r7 8010e8a: bd80 pop {r7, pc} 8010e8c: 40012c00 .word 0x40012c00 8010e90: 40000400 .word 0x40000400 8010e94: 40000800 .word 0x40000800 8010e98: 40000c00 .word 0x40000c00 08010e9c : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 8010e9c: b580 push {r7, lr} 8010e9e: b082 sub sp, #8 8010ea0: af00 add r7, sp, #0 8010ea2: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8010ea4: 687b ldr r3, [r7, #4] 8010ea6: 2b00 cmp r3, #0 8010ea8: d101 bne.n 8010eae { return HAL_ERROR; 8010eaa: 2301 movs r3, #1 8010eac: e041 b.n 8010f32 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8010eae: 687b ldr r3, [r7, #4] 8010eb0: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8010eb4: b2db uxtb r3, r3 8010eb6: 2b00 cmp r3, #0 8010eb8: d106 bne.n 8010ec8 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8010eba: 687b ldr r3, [r7, #4] 8010ebc: 2200 movs r2, #0 8010ebe: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 8010ec2: 6878 ldr r0, [r7, #4] 8010ec4: f000 f839 bl 8010f3a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8010ec8: 687b ldr r3, [r7, #4] 8010eca: 2202 movs r2, #2 8010ecc: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8010ed0: 687b ldr r3, [r7, #4] 8010ed2: 681a ldr r2, [r3, #0] 8010ed4: 687b ldr r3, [r7, #4] 8010ed6: 3304 adds r3, #4 8010ed8: 4619 mov r1, r3 8010eda: 4610 mov r0, r2 8010edc: f000 fb7e bl 80115dc /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8010ee0: 687b ldr r3, [r7, #4] 8010ee2: 2201 movs r2, #1 8010ee4: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8010ee8: 687b ldr r3, [r7, #4] 8010eea: 2201 movs r2, #1 8010eec: f883 203e strb.w r2, [r3, #62] @ 0x3e 8010ef0: 687b ldr r3, [r7, #4] 8010ef2: 2201 movs r2, #1 8010ef4: f883 203f strb.w r2, [r3, #63] @ 0x3f 8010ef8: 687b ldr r3, [r7, #4] 8010efa: 2201 movs r2, #1 8010efc: f883 2040 strb.w r2, [r3, #64] @ 0x40 8010f00: 687b ldr r3, [r7, #4] 8010f02: 2201 movs r2, #1 8010f04: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8010f08: 687b ldr r3, [r7, #4] 8010f0a: 2201 movs r2, #1 8010f0c: f883 2042 strb.w r2, [r3, #66] @ 0x42 8010f10: 687b ldr r3, [r7, #4] 8010f12: 2201 movs r2, #1 8010f14: f883 2043 strb.w r2, [r3, #67] @ 0x43 8010f18: 687b ldr r3, [r7, #4] 8010f1a: 2201 movs r2, #1 8010f1c: f883 2044 strb.w r2, [r3, #68] @ 0x44 8010f20: 687b ldr r3, [r7, #4] 8010f22: 2201 movs r2, #1 8010f24: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8010f28: 687b ldr r3, [r7, #4] 8010f2a: 2201 movs r2, #1 8010f2c: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8010f30: 2300 movs r3, #0 } 8010f32: 4618 mov r0, r3 8010f34: 3708 adds r7, #8 8010f36: 46bd mov sp, r7 8010f38: bd80 pop {r7, pc} 08010f3a : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 8010f3a: b480 push {r7} 8010f3c: b083 sub sp, #12 8010f3e: af00 add r7, sp, #0 8010f40: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 8010f42: bf00 nop 8010f44: 370c adds r7, #12 8010f46: 46bd mov sp, r7 8010f48: bc80 pop {r7} 8010f4a: 4770 bx lr 08010f4c : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8010f4c: b580 push {r7, lr} 8010f4e: b084 sub sp, #16 8010f50: af00 add r7, sp, #0 8010f52: 6078 str r0, [r7, #4] 8010f54: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 8010f56: 683b ldr r3, [r7, #0] 8010f58: 2b00 cmp r3, #0 8010f5a: d109 bne.n 8010f70 8010f5c: 687b ldr r3, [r7, #4] 8010f5e: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8010f62: b2db uxtb r3, r3 8010f64: 2b01 cmp r3, #1 8010f66: bf14 ite ne 8010f68: 2301 movne r3, #1 8010f6a: 2300 moveq r3, #0 8010f6c: b2db uxtb r3, r3 8010f6e: e022 b.n 8010fb6 8010f70: 683b ldr r3, [r7, #0] 8010f72: 2b04 cmp r3, #4 8010f74: d109 bne.n 8010f8a 8010f76: 687b ldr r3, [r7, #4] 8010f78: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8010f7c: b2db uxtb r3, r3 8010f7e: 2b01 cmp r3, #1 8010f80: bf14 ite ne 8010f82: 2301 movne r3, #1 8010f84: 2300 moveq r3, #0 8010f86: b2db uxtb r3, r3 8010f88: e015 b.n 8010fb6 8010f8a: 683b ldr r3, [r7, #0] 8010f8c: 2b08 cmp r3, #8 8010f8e: d109 bne.n 8010fa4 8010f90: 687b ldr r3, [r7, #4] 8010f92: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8010f96: b2db uxtb r3, r3 8010f98: 2b01 cmp r3, #1 8010f9a: bf14 ite ne 8010f9c: 2301 movne r3, #1 8010f9e: 2300 moveq r3, #0 8010fa0: b2db uxtb r3, r3 8010fa2: e008 b.n 8010fb6 8010fa4: 687b ldr r3, [r7, #4] 8010fa6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8010faa: b2db uxtb r3, r3 8010fac: 2b01 cmp r3, #1 8010fae: bf14 ite ne 8010fb0: 2301 movne r3, #1 8010fb2: 2300 moveq r3, #0 8010fb4: b2db uxtb r3, r3 8010fb6: 2b00 cmp r3, #0 8010fb8: d001 beq.n 8010fbe { return HAL_ERROR; 8010fba: 2301 movs r3, #1 8010fbc: e063 b.n 8011086 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8010fbe: 683b ldr r3, [r7, #0] 8010fc0: 2b00 cmp r3, #0 8010fc2: d104 bne.n 8010fce 8010fc4: 687b ldr r3, [r7, #4] 8010fc6: 2202 movs r2, #2 8010fc8: f883 203e strb.w r2, [r3, #62] @ 0x3e 8010fcc: e013 b.n 8010ff6 8010fce: 683b ldr r3, [r7, #0] 8010fd0: 2b04 cmp r3, #4 8010fd2: d104 bne.n 8010fde 8010fd4: 687b ldr r3, [r7, #4] 8010fd6: 2202 movs r2, #2 8010fd8: f883 203f strb.w r2, [r3, #63] @ 0x3f 8010fdc: e00b b.n 8010ff6 8010fde: 683b ldr r3, [r7, #0] 8010fe0: 2b08 cmp r3, #8 8010fe2: d104 bne.n 8010fee 8010fe4: 687b ldr r3, [r7, #4] 8010fe6: 2202 movs r2, #2 8010fe8: f883 2040 strb.w r2, [r3, #64] @ 0x40 8010fec: e003 b.n 8010ff6 8010fee: 687b ldr r3, [r7, #4] 8010ff0: 2202 movs r2, #2 8010ff2: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 8010ff6: 687b ldr r3, [r7, #4] 8010ff8: 681b ldr r3, [r3, #0] 8010ffa: 2201 movs r2, #1 8010ffc: 6839 ldr r1, [r7, #0] 8010ffe: 4618 mov r0, r3 8011000: f000 fd82 bl 8011b08 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8011004: 687b ldr r3, [r7, #4] 8011006: 681b ldr r3, [r3, #0] 8011008: 4a21 ldr r2, [pc, #132] @ (8011090 ) 801100a: 4293 cmp r3, r2 801100c: d107 bne.n 801101e { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 801100e: 687b ldr r3, [r7, #4] 8011010: 681b ldr r3, [r3, #0] 8011012: 6c5a ldr r2, [r3, #68] @ 0x44 8011014: 687b ldr r3, [r7, #4] 8011016: 681b ldr r3, [r3, #0] 8011018: f442 4200 orr.w r2, r2, #32768 @ 0x8000 801101c: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 801101e: 687b ldr r3, [r7, #4] 8011020: 681b ldr r3, [r3, #0] 8011022: 4a1b ldr r2, [pc, #108] @ (8011090 ) 8011024: 4293 cmp r3, r2 8011026: d013 beq.n 8011050 8011028: 687b ldr r3, [r7, #4] 801102a: 681b ldr r3, [r3, #0] 801102c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8011030: d00e beq.n 8011050 8011032: 687b ldr r3, [r7, #4] 8011034: 681b ldr r3, [r3, #0] 8011036: 4a17 ldr r2, [pc, #92] @ (8011094 ) 8011038: 4293 cmp r3, r2 801103a: d009 beq.n 8011050 801103c: 687b ldr r3, [r7, #4] 801103e: 681b ldr r3, [r3, #0] 8011040: 4a15 ldr r2, [pc, #84] @ (8011098 ) 8011042: 4293 cmp r3, r2 8011044: d004 beq.n 8011050 8011046: 687b ldr r3, [r7, #4] 8011048: 681b ldr r3, [r3, #0] 801104a: 4a14 ldr r2, [pc, #80] @ (801109c ) 801104c: 4293 cmp r3, r2 801104e: d111 bne.n 8011074 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8011050: 687b ldr r3, [r7, #4] 8011052: 681b ldr r3, [r3, #0] 8011054: 689b ldr r3, [r3, #8] 8011056: f003 0307 and.w r3, r3, #7 801105a: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 801105c: 68fb ldr r3, [r7, #12] 801105e: 2b06 cmp r3, #6 8011060: d010 beq.n 8011084 { __HAL_TIM_ENABLE(htim); 8011062: 687b ldr r3, [r7, #4] 8011064: 681b ldr r3, [r3, #0] 8011066: 681a ldr r2, [r3, #0] 8011068: 687b ldr r3, [r7, #4] 801106a: 681b ldr r3, [r3, #0] 801106c: f042 0201 orr.w r2, r2, #1 8011070: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8011072: e007 b.n 8011084 } } else { __HAL_TIM_ENABLE(htim); 8011074: 687b ldr r3, [r7, #4] 8011076: 681b ldr r3, [r3, #0] 8011078: 681a ldr r2, [r3, #0] 801107a: 687b ldr r3, [r7, #4] 801107c: 681b ldr r3, [r3, #0] 801107e: f042 0201 orr.w r2, r2, #1 8011082: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8011084: 2300 movs r3, #0 } 8011086: 4618 mov r0, r3 8011088: 3710 adds r7, #16 801108a: 46bd mov sp, r7 801108c: bd80 pop {r7, pc} 801108e: bf00 nop 8011090: 40012c00 .word 0x40012c00 8011094: 40000400 .word 0x40000400 8011098: 40000800 .word 0x40000800 801109c: 40000c00 .word 0x40000c00 080110a0 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 80110a0: b580 push {r7, lr} 80110a2: b084 sub sp, #16 80110a4: af00 add r7, sp, #0 80110a6: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 80110a8: 687b ldr r3, [r7, #4] 80110aa: 681b ldr r3, [r3, #0] 80110ac: 68db ldr r3, [r3, #12] 80110ae: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 80110b0: 687b ldr r3, [r7, #4] 80110b2: 681b ldr r3, [r3, #0] 80110b4: 691b ldr r3, [r3, #16] 80110b6: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 80110b8: 68bb ldr r3, [r7, #8] 80110ba: f003 0302 and.w r3, r3, #2 80110be: 2b00 cmp r3, #0 80110c0: d020 beq.n 8011104 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 80110c2: 68fb ldr r3, [r7, #12] 80110c4: f003 0302 and.w r3, r3, #2 80110c8: 2b00 cmp r3, #0 80110ca: d01b beq.n 8011104 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 80110cc: 687b ldr r3, [r7, #4] 80110ce: 681b ldr r3, [r3, #0] 80110d0: f06f 0202 mvn.w r2, #2 80110d4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 80110d6: 687b ldr r3, [r7, #4] 80110d8: 2201 movs r2, #1 80110da: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 80110dc: 687b ldr r3, [r7, #4] 80110de: 681b ldr r3, [r3, #0] 80110e0: 699b ldr r3, [r3, #24] 80110e2: f003 0303 and.w r3, r3, #3 80110e6: 2b00 cmp r3, #0 80110e8: d003 beq.n 80110f2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80110ea: 6878 ldr r0, [r7, #4] 80110ec: f000 fa5a bl 80115a4 80110f0: e005 b.n 80110fe { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80110f2: 6878 ldr r0, [r7, #4] 80110f4: f7f9 f87c bl 800a1f0 HAL_TIM_PWM_PulseFinishedCallback(htim); 80110f8: 6878 ldr r0, [r7, #4] 80110fa: f000 fa5c bl 80115b6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80110fe: 687b ldr r3, [r7, #4] 8011100: 2200 movs r2, #0 8011102: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 8011104: 68bb ldr r3, [r7, #8] 8011106: f003 0304 and.w r3, r3, #4 801110a: 2b00 cmp r3, #0 801110c: d020 beq.n 8011150 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 801110e: 68fb ldr r3, [r7, #12] 8011110: f003 0304 and.w r3, r3, #4 8011114: 2b00 cmp r3, #0 8011116: d01b beq.n 8011150 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 8011118: 687b ldr r3, [r7, #4] 801111a: 681b ldr r3, [r3, #0] 801111c: f06f 0204 mvn.w r2, #4 8011120: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8011122: 687b ldr r3, [r7, #4] 8011124: 2202 movs r2, #2 8011126: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8011128: 687b ldr r3, [r7, #4] 801112a: 681b ldr r3, [r3, #0] 801112c: 699b ldr r3, [r3, #24] 801112e: f403 7340 and.w r3, r3, #768 @ 0x300 8011132: 2b00 cmp r3, #0 8011134: d003 beq.n 801113e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8011136: 6878 ldr r0, [r7, #4] 8011138: f000 fa34 bl 80115a4 801113c: e005 b.n 801114a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 801113e: 6878 ldr r0, [r7, #4] 8011140: f7f9 f856 bl 800a1f0 HAL_TIM_PWM_PulseFinishedCallback(htim); 8011144: 6878 ldr r0, [r7, #4] 8011146: f000 fa36 bl 80115b6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 801114a: 687b ldr r3, [r7, #4] 801114c: 2200 movs r2, #0 801114e: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 8011150: 68bb ldr r3, [r7, #8] 8011152: f003 0308 and.w r3, r3, #8 8011156: 2b00 cmp r3, #0 8011158: d020 beq.n 801119c { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 801115a: 68fb ldr r3, [r7, #12] 801115c: f003 0308 and.w r3, r3, #8 8011160: 2b00 cmp r3, #0 8011162: d01b beq.n 801119c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 8011164: 687b ldr r3, [r7, #4] 8011166: 681b ldr r3, [r3, #0] 8011168: f06f 0208 mvn.w r2, #8 801116c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 801116e: 687b ldr r3, [r7, #4] 8011170: 2204 movs r2, #4 8011172: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8011174: 687b ldr r3, [r7, #4] 8011176: 681b ldr r3, [r3, #0] 8011178: 69db ldr r3, [r3, #28] 801117a: f003 0303 and.w r3, r3, #3 801117e: 2b00 cmp r3, #0 8011180: d003 beq.n 801118a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8011182: 6878 ldr r0, [r7, #4] 8011184: f000 fa0e bl 80115a4 8011188: e005 b.n 8011196 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 801118a: 6878 ldr r0, [r7, #4] 801118c: f7f9 f830 bl 800a1f0 HAL_TIM_PWM_PulseFinishedCallback(htim); 8011190: 6878 ldr r0, [r7, #4] 8011192: f000 fa10 bl 80115b6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8011196: 687b ldr r3, [r7, #4] 8011198: 2200 movs r2, #0 801119a: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 801119c: 68bb ldr r3, [r7, #8] 801119e: f003 0310 and.w r3, r3, #16 80111a2: 2b00 cmp r3, #0 80111a4: d020 beq.n 80111e8 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 80111a6: 68fb ldr r3, [r7, #12] 80111a8: f003 0310 and.w r3, r3, #16 80111ac: 2b00 cmp r3, #0 80111ae: d01b beq.n 80111e8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 80111b0: 687b ldr r3, [r7, #4] 80111b2: 681b ldr r3, [r3, #0] 80111b4: f06f 0210 mvn.w r2, #16 80111b8: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 80111ba: 687b ldr r3, [r7, #4] 80111bc: 2208 movs r2, #8 80111be: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 80111c0: 687b ldr r3, [r7, #4] 80111c2: 681b ldr r3, [r3, #0] 80111c4: 69db ldr r3, [r3, #28] 80111c6: f403 7340 and.w r3, r3, #768 @ 0x300 80111ca: 2b00 cmp r3, #0 80111cc: d003 beq.n 80111d6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80111ce: 6878 ldr r0, [r7, #4] 80111d0: f000 f9e8 bl 80115a4 80111d4: e005 b.n 80111e2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80111d6: 6878 ldr r0, [r7, #4] 80111d8: f7f9 f80a bl 800a1f0 HAL_TIM_PWM_PulseFinishedCallback(htim); 80111dc: 6878 ldr r0, [r7, #4] 80111de: f000 f9ea bl 80115b6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80111e2: 687b ldr r3, [r7, #4] 80111e4: 2200 movs r2, #0 80111e6: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 80111e8: 68bb ldr r3, [r7, #8] 80111ea: f003 0301 and.w r3, r3, #1 80111ee: 2b00 cmp r3, #0 80111f0: d00c beq.n 801120c { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 80111f2: 68fb ldr r3, [r7, #12] 80111f4: f003 0301 and.w r3, r3, #1 80111f8: 2b00 cmp r3, #0 80111fa: d007 beq.n 801120c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 80111fc: 687b ldr r3, [r7, #4] 80111fe: 681b ldr r3, [r3, #0] 8011200: f06f 0201 mvn.w r2, #1 8011204: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 8011206: 6878 ldr r0, [r7, #4] 8011208: f000 f9c3 bl 8011592 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) 801120c: 68bb ldr r3, [r7, #8] 801120e: f003 0380 and.w r3, r3, #128 @ 0x80 8011212: 2b00 cmp r3, #0 8011214: d00c beq.n 8011230 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8011216: 68fb ldr r3, [r7, #12] 8011218: f003 0380 and.w r3, r3, #128 @ 0x80 801121c: 2b00 cmp r3, #0 801121e: d007 beq.n 8011230 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); 8011220: 687b ldr r3, [r7, #4] 8011222: 681b ldr r3, [r3, #0] 8011224: f06f 0280 mvn.w r2, #128 @ 0x80 8011228: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 801122a: 6878 ldr r0, [r7, #4] 801122c: f000 fcff bl 8011c2e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 8011230: 68bb ldr r3, [r7, #8] 8011232: f003 0340 and.w r3, r3, #64 @ 0x40 8011236: 2b00 cmp r3, #0 8011238: d00c beq.n 8011254 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 801123a: 68fb ldr r3, [r7, #12] 801123c: f003 0340 and.w r3, r3, #64 @ 0x40 8011240: 2b00 cmp r3, #0 8011242: d007 beq.n 8011254 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 8011244: 687b ldr r3, [r7, #4] 8011246: 681b ldr r3, [r3, #0] 8011248: f06f 0240 mvn.w r2, #64 @ 0x40 801124c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 801124e: 6878 ldr r0, [r7, #4] 8011250: f000 f9ba bl 80115c8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 8011254: 68bb ldr r3, [r7, #8] 8011256: f003 0320 and.w r3, r3, #32 801125a: 2b00 cmp r3, #0 801125c: d00c beq.n 8011278 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 801125e: 68fb ldr r3, [r7, #12] 8011260: f003 0320 and.w r3, r3, #32 8011264: 2b00 cmp r3, #0 8011266: d007 beq.n 8011278 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 8011268: 687b ldr r3, [r7, #4] 801126a: 681b ldr r3, [r3, #0] 801126c: f06f 0220 mvn.w r2, #32 8011270: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8011272: 6878 ldr r0, [r7, #4] 8011274: f000 fcd2 bl 8011c1c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8011278: bf00 nop 801127a: 3710 adds r7, #16 801127c: 46bd mov sp, r7 801127e: bd80 pop {r7, pc} 08011280 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8011280: b580 push {r7, lr} 8011282: b086 sub sp, #24 8011284: af00 add r7, sp, #0 8011286: 60f8 str r0, [r7, #12] 8011288: 60b9 str r1, [r7, #8] 801128a: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 801128c: 2300 movs r3, #0 801128e: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 8011290: 68fb ldr r3, [r7, #12] 8011292: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8011296: 2b01 cmp r3, #1 8011298: d101 bne.n 801129e 801129a: 2302 movs r3, #2 801129c: e0ae b.n 80113fc 801129e: 68fb ldr r3, [r7, #12] 80112a0: 2201 movs r2, #1 80112a2: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 80112a6: 687b ldr r3, [r7, #4] 80112a8: 2b0c cmp r3, #12 80112aa: f200 809f bhi.w 80113ec 80112ae: a201 add r2, pc, #4 @ (adr r2, 80112b4 ) 80112b0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80112b4: 080112e9 .word 0x080112e9 80112b8: 080113ed .word 0x080113ed 80112bc: 080113ed .word 0x080113ed 80112c0: 080113ed .word 0x080113ed 80112c4: 08011329 .word 0x08011329 80112c8: 080113ed .word 0x080113ed 80112cc: 080113ed .word 0x080113ed 80112d0: 080113ed .word 0x080113ed 80112d4: 0801136b .word 0x0801136b 80112d8: 080113ed .word 0x080113ed 80112dc: 080113ed .word 0x080113ed 80112e0: 080113ed .word 0x080113ed 80112e4: 080113ab .word 0x080113ab { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 80112e8: 68fb ldr r3, [r7, #12] 80112ea: 681b ldr r3, [r3, #0] 80112ec: 68b9 ldr r1, [r7, #8] 80112ee: 4618 mov r0, r3 80112f0: f000 f9ec bl 80116cc /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 80112f4: 68fb ldr r3, [r7, #12] 80112f6: 681b ldr r3, [r3, #0] 80112f8: 699a ldr r2, [r3, #24] 80112fa: 68fb ldr r3, [r7, #12] 80112fc: 681b ldr r3, [r3, #0] 80112fe: f042 0208 orr.w r2, r2, #8 8011302: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 8011304: 68fb ldr r3, [r7, #12] 8011306: 681b ldr r3, [r3, #0] 8011308: 699a ldr r2, [r3, #24] 801130a: 68fb ldr r3, [r7, #12] 801130c: 681b ldr r3, [r3, #0] 801130e: f022 0204 bic.w r2, r2, #4 8011312: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 8011314: 68fb ldr r3, [r7, #12] 8011316: 681b ldr r3, [r3, #0] 8011318: 6999 ldr r1, [r3, #24] 801131a: 68bb ldr r3, [r7, #8] 801131c: 691a ldr r2, [r3, #16] 801131e: 68fb ldr r3, [r7, #12] 8011320: 681b ldr r3, [r3, #0] 8011322: 430a orrs r2, r1 8011324: 619a str r2, [r3, #24] break; 8011326: e064 b.n 80113f2 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8011328: 68fb ldr r3, [r7, #12] 801132a: 681b ldr r3, [r3, #0] 801132c: 68b9 ldr r1, [r7, #8] 801132e: 4618 mov r0, r3 8011330: f000 fa32 bl 8011798 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8011334: 68fb ldr r3, [r7, #12] 8011336: 681b ldr r3, [r3, #0] 8011338: 699a ldr r2, [r3, #24] 801133a: 68fb ldr r3, [r7, #12] 801133c: 681b ldr r3, [r3, #0] 801133e: f442 6200 orr.w r2, r2, #2048 @ 0x800 8011342: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8011344: 68fb ldr r3, [r7, #12] 8011346: 681b ldr r3, [r3, #0] 8011348: 699a ldr r2, [r3, #24] 801134a: 68fb ldr r3, [r7, #12] 801134c: 681b ldr r3, [r3, #0] 801134e: f422 6280 bic.w r2, r2, #1024 @ 0x400 8011352: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8011354: 68fb ldr r3, [r7, #12] 8011356: 681b ldr r3, [r3, #0] 8011358: 6999 ldr r1, [r3, #24] 801135a: 68bb ldr r3, [r7, #8] 801135c: 691b ldr r3, [r3, #16] 801135e: 021a lsls r2, r3, #8 8011360: 68fb ldr r3, [r7, #12] 8011362: 681b ldr r3, [r3, #0] 8011364: 430a orrs r2, r1 8011366: 619a str r2, [r3, #24] break; 8011368: e043 b.n 80113f2 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 801136a: 68fb ldr r3, [r7, #12] 801136c: 681b ldr r3, [r3, #0] 801136e: 68b9 ldr r1, [r7, #8] 8011370: 4618 mov r0, r3 8011372: f000 fa7b bl 801186c /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 8011376: 68fb ldr r3, [r7, #12] 8011378: 681b ldr r3, [r3, #0] 801137a: 69da ldr r2, [r3, #28] 801137c: 68fb ldr r3, [r7, #12] 801137e: 681b ldr r3, [r3, #0] 8011380: f042 0208 orr.w r2, r2, #8 8011384: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 8011386: 68fb ldr r3, [r7, #12] 8011388: 681b ldr r3, [r3, #0] 801138a: 69da ldr r2, [r3, #28] 801138c: 68fb ldr r3, [r7, #12] 801138e: 681b ldr r3, [r3, #0] 8011390: f022 0204 bic.w r2, r2, #4 8011394: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 8011396: 68fb ldr r3, [r7, #12] 8011398: 681b ldr r3, [r3, #0] 801139a: 69d9 ldr r1, [r3, #28] 801139c: 68bb ldr r3, [r7, #8] 801139e: 691a ldr r2, [r3, #16] 80113a0: 68fb ldr r3, [r7, #12] 80113a2: 681b ldr r3, [r3, #0] 80113a4: 430a orrs r2, r1 80113a6: 61da str r2, [r3, #28] break; 80113a8: e023 b.n 80113f2 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 80113aa: 68fb ldr r3, [r7, #12] 80113ac: 681b ldr r3, [r3, #0] 80113ae: 68b9 ldr r1, [r7, #8] 80113b0: 4618 mov r0, r3 80113b2: f000 fac5 bl 8011940 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 80113b6: 68fb ldr r3, [r7, #12] 80113b8: 681b ldr r3, [r3, #0] 80113ba: 69da ldr r2, [r3, #28] 80113bc: 68fb ldr r3, [r7, #12] 80113be: 681b ldr r3, [r3, #0] 80113c0: f442 6200 orr.w r2, r2, #2048 @ 0x800 80113c4: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 80113c6: 68fb ldr r3, [r7, #12] 80113c8: 681b ldr r3, [r3, #0] 80113ca: 69da ldr r2, [r3, #28] 80113cc: 68fb ldr r3, [r7, #12] 80113ce: 681b ldr r3, [r3, #0] 80113d0: f422 6280 bic.w r2, r2, #1024 @ 0x400 80113d4: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 80113d6: 68fb ldr r3, [r7, #12] 80113d8: 681b ldr r3, [r3, #0] 80113da: 69d9 ldr r1, [r3, #28] 80113dc: 68bb ldr r3, [r7, #8] 80113de: 691b ldr r3, [r3, #16] 80113e0: 021a lsls r2, r3, #8 80113e2: 68fb ldr r3, [r7, #12] 80113e4: 681b ldr r3, [r3, #0] 80113e6: 430a orrs r2, r1 80113e8: 61da str r2, [r3, #28] break; 80113ea: e002 b.n 80113f2 } default: status = HAL_ERROR; 80113ec: 2301 movs r3, #1 80113ee: 75fb strb r3, [r7, #23] break; 80113f0: bf00 nop } __HAL_UNLOCK(htim); 80113f2: 68fb ldr r3, [r7, #12] 80113f4: 2200 movs r2, #0 80113f6: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 80113fa: 7dfb ldrb r3, [r7, #23] } 80113fc: 4618 mov r0, r3 80113fe: 3718 adds r7, #24 8011400: 46bd mov sp, r7 8011402: bd80 pop {r7, pc} 08011404 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 8011404: b580 push {r7, lr} 8011406: b084 sub sp, #16 8011408: af00 add r7, sp, #0 801140a: 6078 str r0, [r7, #4] 801140c: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 801140e: 2300 movs r3, #0 8011410: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 8011412: 687b ldr r3, [r7, #4] 8011414: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8011418: 2b01 cmp r3, #1 801141a: d101 bne.n 8011420 801141c: 2302 movs r3, #2 801141e: e0b4 b.n 801158a 8011420: 687b ldr r3, [r7, #4] 8011422: 2201 movs r2, #1 8011424: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 8011428: 687b ldr r3, [r7, #4] 801142a: 2202 movs r2, #2 801142c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 8011430: 687b ldr r3, [r7, #4] 8011432: 681b ldr r3, [r3, #0] 8011434: 689b ldr r3, [r3, #8] 8011436: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 8011438: 68bb ldr r3, [r7, #8] 801143a: f023 0377 bic.w r3, r3, #119 @ 0x77 801143e: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8011440: 68bb ldr r3, [r7, #8] 8011442: f423 437f bic.w r3, r3, #65280 @ 0xff00 8011446: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 8011448: 687b ldr r3, [r7, #4] 801144a: 681b ldr r3, [r3, #0] 801144c: 68ba ldr r2, [r7, #8] 801144e: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 8011450: 683b ldr r3, [r7, #0] 8011452: 681b ldr r3, [r3, #0] 8011454: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8011458: d03e beq.n 80114d8 801145a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 801145e: f200 8087 bhi.w 8011570 8011462: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8011466: f000 8086 beq.w 8011576 801146a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 801146e: d87f bhi.n 8011570 8011470: 2b70 cmp r3, #112 @ 0x70 8011472: d01a beq.n 80114aa 8011474: 2b70 cmp r3, #112 @ 0x70 8011476: d87b bhi.n 8011570 8011478: 2b60 cmp r3, #96 @ 0x60 801147a: d050 beq.n 801151e 801147c: 2b60 cmp r3, #96 @ 0x60 801147e: d877 bhi.n 8011570 8011480: 2b50 cmp r3, #80 @ 0x50 8011482: d03c beq.n 80114fe 8011484: 2b50 cmp r3, #80 @ 0x50 8011486: d873 bhi.n 8011570 8011488: 2b40 cmp r3, #64 @ 0x40 801148a: d058 beq.n 801153e 801148c: 2b40 cmp r3, #64 @ 0x40 801148e: d86f bhi.n 8011570 8011490: 2b30 cmp r3, #48 @ 0x30 8011492: d064 beq.n 801155e 8011494: 2b30 cmp r3, #48 @ 0x30 8011496: d86b bhi.n 8011570 8011498: 2b20 cmp r3, #32 801149a: d060 beq.n 801155e 801149c: 2b20 cmp r3, #32 801149e: d867 bhi.n 8011570 80114a0: 2b00 cmp r3, #0 80114a2: d05c beq.n 801155e 80114a4: 2b10 cmp r3, #16 80114a6: d05a beq.n 801155e 80114a8: e062 b.n 8011570 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80114aa: 687b ldr r3, [r7, #4] 80114ac: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 80114ae: 683b ldr r3, [r7, #0] 80114b0: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 80114b2: 683b ldr r3, [r7, #0] 80114b4: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 80114b6: 683b ldr r3, [r7, #0] 80114b8: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 80114ba: f000 fb06 bl 8011aca /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 80114be: 687b ldr r3, [r7, #4] 80114c0: 681b ldr r3, [r3, #0] 80114c2: 689b ldr r3, [r3, #8] 80114c4: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 80114c6: 68bb ldr r3, [r7, #8] 80114c8: f043 0377 orr.w r3, r3, #119 @ 0x77 80114cc: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80114ce: 687b ldr r3, [r7, #4] 80114d0: 681b ldr r3, [r3, #0] 80114d2: 68ba ldr r2, [r7, #8] 80114d4: 609a str r2, [r3, #8] break; 80114d6: e04f b.n 8011578 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80114d8: 687b ldr r3, [r7, #4] 80114da: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 80114dc: 683b ldr r3, [r7, #0] 80114de: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 80114e0: 683b ldr r3, [r7, #0] 80114e2: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 80114e4: 683b ldr r3, [r7, #0] 80114e6: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 80114e8: f000 faef bl 8011aca /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 80114ec: 687b ldr r3, [r7, #4] 80114ee: 681b ldr r3, [r3, #0] 80114f0: 689a ldr r2, [r3, #8] 80114f2: 687b ldr r3, [r7, #4] 80114f4: 681b ldr r3, [r3, #0] 80114f6: f442 4280 orr.w r2, r2, #16384 @ 0x4000 80114fa: 609a str r2, [r3, #8] break; 80114fc: e03c b.n 8011578 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 80114fe: 687b ldr r3, [r7, #4] 8011500: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8011502: 683b ldr r3, [r7, #0] 8011504: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8011506: 683b ldr r3, [r7, #0] 8011508: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 801150a: 461a mov r2, r3 801150c: f000 fa66 bl 80119dc TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 8011510: 687b ldr r3, [r7, #4] 8011512: 681b ldr r3, [r3, #0] 8011514: 2150 movs r1, #80 @ 0x50 8011516: 4618 mov r0, r3 8011518: f000 fabd bl 8011a96 break; 801151c: e02c b.n 8011578 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 801151e: 687b ldr r3, [r7, #4] 8011520: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8011522: 683b ldr r3, [r7, #0] 8011524: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8011526: 683b ldr r3, [r7, #0] 8011528: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 801152a: 461a mov r2, r3 801152c: f000 fa84 bl 8011a38 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 8011530: 687b ldr r3, [r7, #4] 8011532: 681b ldr r3, [r3, #0] 8011534: 2160 movs r1, #96 @ 0x60 8011536: 4618 mov r0, r3 8011538: f000 faad bl 8011a96 break; 801153c: e01c b.n 8011578 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 801153e: 687b ldr r3, [r7, #4] 8011540: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8011542: 683b ldr r3, [r7, #0] 8011544: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8011546: 683b ldr r3, [r7, #0] 8011548: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 801154a: 461a mov r2, r3 801154c: f000 fa46 bl 80119dc TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 8011550: 687b ldr r3, [r7, #4] 8011552: 681b ldr r3, [r3, #0] 8011554: 2140 movs r1, #64 @ 0x40 8011556: 4618 mov r0, r3 8011558: f000 fa9d bl 8011a96 break; 801155c: e00c b.n 8011578 case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 801155e: 687b ldr r3, [r7, #4] 8011560: 681a ldr r2, [r3, #0] 8011562: 683b ldr r3, [r7, #0] 8011564: 681b ldr r3, [r3, #0] 8011566: 4619 mov r1, r3 8011568: 4610 mov r0, r2 801156a: f000 fa94 bl 8011a96 break; 801156e: e003 b.n 8011578 } default: status = HAL_ERROR; 8011570: 2301 movs r3, #1 8011572: 73fb strb r3, [r7, #15] break; 8011574: e000 b.n 8011578 break; 8011576: bf00 nop } htim->State = HAL_TIM_STATE_READY; 8011578: 687b ldr r3, [r7, #4] 801157a: 2201 movs r2, #1 801157c: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8011580: 687b ldr r3, [r7, #4] 8011582: 2200 movs r2, #0 8011584: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8011588: 7bfb ldrb r3, [r7, #15] } 801158a: 4618 mov r0, r3 801158c: 3710 adds r7, #16 801158e: 46bd mov sp, r7 8011590: bd80 pop {r7, pc} 08011592 : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8011592: b480 push {r7} 8011594: b083 sub sp, #12 8011596: af00 add r7, sp, #0 8011598: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } 801159a: bf00 nop 801159c: 370c adds r7, #12 801159e: 46bd mov sp, r7 80115a0: bc80 pop {r7} 80115a2: 4770 bx lr 080115a4 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 80115a4: b480 push {r7} 80115a6: b083 sub sp, #12 80115a8: af00 add r7, sp, #0 80115aa: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 80115ac: bf00 nop 80115ae: 370c adds r7, #12 80115b0: 46bd mov sp, r7 80115b2: bc80 pop {r7} 80115b4: 4770 bx lr 080115b6 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 80115b6: b480 push {r7} 80115b8: b083 sub sp, #12 80115ba: af00 add r7, sp, #0 80115bc: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 80115be: bf00 nop 80115c0: 370c adds r7, #12 80115c2: 46bd mov sp, r7 80115c4: bc80 pop {r7} 80115c6: 4770 bx lr 080115c8 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 80115c8: b480 push {r7} 80115ca: b083 sub sp, #12 80115cc: af00 add r7, sp, #0 80115ce: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 80115d0: bf00 nop 80115d2: 370c adds r7, #12 80115d4: 46bd mov sp, r7 80115d6: bc80 pop {r7} 80115d8: 4770 bx lr ... 080115dc : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 80115dc: b480 push {r7} 80115de: b085 sub sp, #20 80115e0: af00 add r7, sp, #0 80115e2: 6078 str r0, [r7, #4] 80115e4: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 80115e6: 687b ldr r3, [r7, #4] 80115e8: 681b ldr r3, [r3, #0] 80115ea: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80115ec: 687b ldr r3, [r7, #4] 80115ee: 4a33 ldr r2, [pc, #204] @ (80116bc ) 80115f0: 4293 cmp r3, r2 80115f2: d00f beq.n 8011614 80115f4: 687b ldr r3, [r7, #4] 80115f6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80115fa: d00b beq.n 8011614 80115fc: 687b ldr r3, [r7, #4] 80115fe: 4a30 ldr r2, [pc, #192] @ (80116c0 ) 8011600: 4293 cmp r3, r2 8011602: d007 beq.n 8011614 8011604: 687b ldr r3, [r7, #4] 8011606: 4a2f ldr r2, [pc, #188] @ (80116c4 ) 8011608: 4293 cmp r3, r2 801160a: d003 beq.n 8011614 801160c: 687b ldr r3, [r7, #4] 801160e: 4a2e ldr r2, [pc, #184] @ (80116c8 ) 8011610: 4293 cmp r3, r2 8011612: d108 bne.n 8011626 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8011614: 68fb ldr r3, [r7, #12] 8011616: f023 0370 bic.w r3, r3, #112 @ 0x70 801161a: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 801161c: 683b ldr r3, [r7, #0] 801161e: 685b ldr r3, [r3, #4] 8011620: 68fa ldr r2, [r7, #12] 8011622: 4313 orrs r3, r2 8011624: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8011626: 687b ldr r3, [r7, #4] 8011628: 4a24 ldr r2, [pc, #144] @ (80116bc ) 801162a: 4293 cmp r3, r2 801162c: d00f beq.n 801164e 801162e: 687b ldr r3, [r7, #4] 8011630: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8011634: d00b beq.n 801164e 8011636: 687b ldr r3, [r7, #4] 8011638: 4a21 ldr r2, [pc, #132] @ (80116c0 ) 801163a: 4293 cmp r3, r2 801163c: d007 beq.n 801164e 801163e: 687b ldr r3, [r7, #4] 8011640: 4a20 ldr r2, [pc, #128] @ (80116c4 ) 8011642: 4293 cmp r3, r2 8011644: d003 beq.n 801164e 8011646: 687b ldr r3, [r7, #4] 8011648: 4a1f ldr r2, [pc, #124] @ (80116c8 ) 801164a: 4293 cmp r3, r2 801164c: d108 bne.n 8011660 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 801164e: 68fb ldr r3, [r7, #12] 8011650: f423 7340 bic.w r3, r3, #768 @ 0x300 8011654: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8011656: 683b ldr r3, [r7, #0] 8011658: 68db ldr r3, [r3, #12] 801165a: 68fa ldr r2, [r7, #12] 801165c: 4313 orrs r3, r2 801165e: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8011660: 68fb ldr r3, [r7, #12] 8011662: f023 0280 bic.w r2, r3, #128 @ 0x80 8011666: 683b ldr r3, [r7, #0] 8011668: 695b ldr r3, [r3, #20] 801166a: 4313 orrs r3, r2 801166c: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 801166e: 687b ldr r3, [r7, #4] 8011670: 68fa ldr r2, [r7, #12] 8011672: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8011674: 683b ldr r3, [r7, #0] 8011676: 689a ldr r2, [r3, #8] 8011678: 687b ldr r3, [r7, #4] 801167a: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 801167c: 683b ldr r3, [r7, #0] 801167e: 681a ldr r2, [r3, #0] 8011680: 687b ldr r3, [r7, #4] 8011682: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8011684: 687b ldr r3, [r7, #4] 8011686: 4a0d ldr r2, [pc, #52] @ (80116bc ) 8011688: 4293 cmp r3, r2 801168a: d103 bne.n 8011694 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 801168c: 683b ldr r3, [r7, #0] 801168e: 691a ldr r2, [r3, #16] 8011690: 687b ldr r3, [r7, #4] 8011692: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8011694: 687b ldr r3, [r7, #4] 8011696: 2201 movs r2, #1 8011698: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 801169a: 687b ldr r3, [r7, #4] 801169c: 691b ldr r3, [r3, #16] 801169e: f003 0301 and.w r3, r3, #1 80116a2: 2b00 cmp r3, #0 80116a4: d005 beq.n 80116b2 { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 80116a6: 687b ldr r3, [r7, #4] 80116a8: 691b ldr r3, [r3, #16] 80116aa: f023 0201 bic.w r2, r3, #1 80116ae: 687b ldr r3, [r7, #4] 80116b0: 611a str r2, [r3, #16] } } 80116b2: bf00 nop 80116b4: 3714 adds r7, #20 80116b6: 46bd mov sp, r7 80116b8: bc80 pop {r7} 80116ba: 4770 bx lr 80116bc: 40012c00 .word 0x40012c00 80116c0: 40000400 .word 0x40000400 80116c4: 40000800 .word 0x40000800 80116c8: 40000c00 .word 0x40000c00 080116cc : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80116cc: b480 push {r7} 80116ce: b087 sub sp, #28 80116d0: af00 add r7, sp, #0 80116d2: 6078 str r0, [r7, #4] 80116d4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80116d6: 687b ldr r3, [r7, #4] 80116d8: 6a1b ldr r3, [r3, #32] 80116da: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 80116dc: 687b ldr r3, [r7, #4] 80116de: 6a1b ldr r3, [r3, #32] 80116e0: f023 0201 bic.w r2, r3, #1 80116e4: 687b ldr r3, [r7, #4] 80116e6: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80116e8: 687b ldr r3, [r7, #4] 80116ea: 685b ldr r3, [r3, #4] 80116ec: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80116ee: 687b ldr r3, [r7, #4] 80116f0: 699b ldr r3, [r3, #24] 80116f2: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 80116f4: 68fb ldr r3, [r7, #12] 80116f6: f023 0370 bic.w r3, r3, #112 @ 0x70 80116fa: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 80116fc: 68fb ldr r3, [r7, #12] 80116fe: f023 0303 bic.w r3, r3, #3 8011702: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8011704: 683b ldr r3, [r7, #0] 8011706: 681b ldr r3, [r3, #0] 8011708: 68fa ldr r2, [r7, #12] 801170a: 4313 orrs r3, r2 801170c: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 801170e: 697b ldr r3, [r7, #20] 8011710: f023 0302 bic.w r3, r3, #2 8011714: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 8011716: 683b ldr r3, [r7, #0] 8011718: 689b ldr r3, [r3, #8] 801171a: 697a ldr r2, [r7, #20] 801171c: 4313 orrs r3, r2 801171e: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8011720: 687b ldr r3, [r7, #4] 8011722: 4a1c ldr r2, [pc, #112] @ (8011794 ) 8011724: 4293 cmp r3, r2 8011726: d10c bne.n 8011742 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8011728: 697b ldr r3, [r7, #20] 801172a: f023 0308 bic.w r3, r3, #8 801172e: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8011730: 683b ldr r3, [r7, #0] 8011732: 68db ldr r3, [r3, #12] 8011734: 697a ldr r2, [r7, #20] 8011736: 4313 orrs r3, r2 8011738: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 801173a: 697b ldr r3, [r7, #20] 801173c: f023 0304 bic.w r3, r3, #4 8011740: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8011742: 687b ldr r3, [r7, #4] 8011744: 4a13 ldr r2, [pc, #76] @ (8011794 ) 8011746: 4293 cmp r3, r2 8011748: d111 bne.n 801176e /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 801174a: 693b ldr r3, [r7, #16] 801174c: f423 7380 bic.w r3, r3, #256 @ 0x100 8011750: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 8011752: 693b ldr r3, [r7, #16] 8011754: f423 7300 bic.w r3, r3, #512 @ 0x200 8011758: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 801175a: 683b ldr r3, [r7, #0] 801175c: 695b ldr r3, [r3, #20] 801175e: 693a ldr r2, [r7, #16] 8011760: 4313 orrs r3, r2 8011762: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8011764: 683b ldr r3, [r7, #0] 8011766: 699b ldr r3, [r3, #24] 8011768: 693a ldr r2, [r7, #16] 801176a: 4313 orrs r3, r2 801176c: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 801176e: 687b ldr r3, [r7, #4] 8011770: 693a ldr r2, [r7, #16] 8011772: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8011774: 687b ldr r3, [r7, #4] 8011776: 68fa ldr r2, [r7, #12] 8011778: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 801177a: 683b ldr r3, [r7, #0] 801177c: 685a ldr r2, [r3, #4] 801177e: 687b ldr r3, [r7, #4] 8011780: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8011782: 687b ldr r3, [r7, #4] 8011784: 697a ldr r2, [r7, #20] 8011786: 621a str r2, [r3, #32] } 8011788: bf00 nop 801178a: 371c adds r7, #28 801178c: 46bd mov sp, r7 801178e: bc80 pop {r7} 8011790: 4770 bx lr 8011792: bf00 nop 8011794: 40012c00 .word 0x40012c00 08011798 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8011798: b480 push {r7} 801179a: b087 sub sp, #28 801179c: af00 add r7, sp, #0 801179e: 6078 str r0, [r7, #4] 80117a0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80117a2: 687b ldr r3, [r7, #4] 80117a4: 6a1b ldr r3, [r3, #32] 80117a6: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 80117a8: 687b ldr r3, [r7, #4] 80117aa: 6a1b ldr r3, [r3, #32] 80117ac: f023 0210 bic.w r2, r3, #16 80117b0: 687b ldr r3, [r7, #4] 80117b2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80117b4: 687b ldr r3, [r7, #4] 80117b6: 685b ldr r3, [r3, #4] 80117b8: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80117ba: 687b ldr r3, [r7, #4] 80117bc: 699b ldr r3, [r3, #24] 80117be: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 80117c0: 68fb ldr r3, [r7, #12] 80117c2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80117c6: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 80117c8: 68fb ldr r3, [r7, #12] 80117ca: f423 7340 bic.w r3, r3, #768 @ 0x300 80117ce: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80117d0: 683b ldr r3, [r7, #0] 80117d2: 681b ldr r3, [r3, #0] 80117d4: 021b lsls r3, r3, #8 80117d6: 68fa ldr r2, [r7, #12] 80117d8: 4313 orrs r3, r2 80117da: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 80117dc: 697b ldr r3, [r7, #20] 80117de: f023 0320 bic.w r3, r3, #32 80117e2: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 80117e4: 683b ldr r3, [r7, #0] 80117e6: 689b ldr r3, [r3, #8] 80117e8: 011b lsls r3, r3, #4 80117ea: 697a ldr r2, [r7, #20] 80117ec: 4313 orrs r3, r2 80117ee: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 80117f0: 687b ldr r3, [r7, #4] 80117f2: 4a1d ldr r2, [pc, #116] @ (8011868 ) 80117f4: 4293 cmp r3, r2 80117f6: d10d bne.n 8011814 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 80117f8: 697b ldr r3, [r7, #20] 80117fa: f023 0380 bic.w r3, r3, #128 @ 0x80 80117fe: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8011800: 683b ldr r3, [r7, #0] 8011802: 68db ldr r3, [r3, #12] 8011804: 011b lsls r3, r3, #4 8011806: 697a ldr r2, [r7, #20] 8011808: 4313 orrs r3, r2 801180a: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 801180c: 697b ldr r3, [r7, #20] 801180e: f023 0340 bic.w r3, r3, #64 @ 0x40 8011812: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8011814: 687b ldr r3, [r7, #4] 8011816: 4a14 ldr r2, [pc, #80] @ (8011868 ) 8011818: 4293 cmp r3, r2 801181a: d113 bne.n 8011844 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 801181c: 693b ldr r3, [r7, #16] 801181e: f423 6380 bic.w r3, r3, #1024 @ 0x400 8011822: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8011824: 693b ldr r3, [r7, #16] 8011826: f423 6300 bic.w r3, r3, #2048 @ 0x800 801182a: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 801182c: 683b ldr r3, [r7, #0] 801182e: 695b ldr r3, [r3, #20] 8011830: 009b lsls r3, r3, #2 8011832: 693a ldr r2, [r7, #16] 8011834: 4313 orrs r3, r2 8011836: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8011838: 683b ldr r3, [r7, #0] 801183a: 699b ldr r3, [r3, #24] 801183c: 009b lsls r3, r3, #2 801183e: 693a ldr r2, [r7, #16] 8011840: 4313 orrs r3, r2 8011842: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8011844: 687b ldr r3, [r7, #4] 8011846: 693a ldr r2, [r7, #16] 8011848: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 801184a: 687b ldr r3, [r7, #4] 801184c: 68fa ldr r2, [r7, #12] 801184e: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8011850: 683b ldr r3, [r7, #0] 8011852: 685a ldr r2, [r3, #4] 8011854: 687b ldr r3, [r7, #4] 8011856: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8011858: 687b ldr r3, [r7, #4] 801185a: 697a ldr r2, [r7, #20] 801185c: 621a str r2, [r3, #32] } 801185e: bf00 nop 8011860: 371c adds r7, #28 8011862: 46bd mov sp, r7 8011864: bc80 pop {r7} 8011866: 4770 bx lr 8011868: 40012c00 .word 0x40012c00 0801186c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 801186c: b480 push {r7} 801186e: b087 sub sp, #28 8011870: af00 add r7, sp, #0 8011872: 6078 str r0, [r7, #4] 8011874: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8011876: 687b ldr r3, [r7, #4] 8011878: 6a1b ldr r3, [r3, #32] 801187a: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 801187c: 687b ldr r3, [r7, #4] 801187e: 6a1b ldr r3, [r3, #32] 8011880: f423 7280 bic.w r2, r3, #256 @ 0x100 8011884: 687b ldr r3, [r7, #4] 8011886: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8011888: 687b ldr r3, [r7, #4] 801188a: 685b ldr r3, [r3, #4] 801188c: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 801188e: 687b ldr r3, [r7, #4] 8011890: 69db ldr r3, [r3, #28] 8011892: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8011894: 68fb ldr r3, [r7, #12] 8011896: f023 0370 bic.w r3, r3, #112 @ 0x70 801189a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 801189c: 68fb ldr r3, [r7, #12] 801189e: f023 0303 bic.w r3, r3, #3 80118a2: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80118a4: 683b ldr r3, [r7, #0] 80118a6: 681b ldr r3, [r3, #0] 80118a8: 68fa ldr r2, [r7, #12] 80118aa: 4313 orrs r3, r2 80118ac: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 80118ae: 697b ldr r3, [r7, #20] 80118b0: f423 7300 bic.w r3, r3, #512 @ 0x200 80118b4: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 80118b6: 683b ldr r3, [r7, #0] 80118b8: 689b ldr r3, [r3, #8] 80118ba: 021b lsls r3, r3, #8 80118bc: 697a ldr r2, [r7, #20] 80118be: 4313 orrs r3, r2 80118c0: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 80118c2: 687b ldr r3, [r7, #4] 80118c4: 4a1d ldr r2, [pc, #116] @ (801193c ) 80118c6: 4293 cmp r3, r2 80118c8: d10d bne.n 80118e6 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 80118ca: 697b ldr r3, [r7, #20] 80118cc: f423 6300 bic.w r3, r3, #2048 @ 0x800 80118d0: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 80118d2: 683b ldr r3, [r7, #0] 80118d4: 68db ldr r3, [r3, #12] 80118d6: 021b lsls r3, r3, #8 80118d8: 697a ldr r2, [r7, #20] 80118da: 4313 orrs r3, r2 80118dc: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 80118de: 697b ldr r3, [r7, #20] 80118e0: f423 6380 bic.w r3, r3, #1024 @ 0x400 80118e4: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80118e6: 687b ldr r3, [r7, #4] 80118e8: 4a14 ldr r2, [pc, #80] @ (801193c ) 80118ea: 4293 cmp r3, r2 80118ec: d113 bne.n 8011916 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 80118ee: 693b ldr r3, [r7, #16] 80118f0: f423 5380 bic.w r3, r3, #4096 @ 0x1000 80118f4: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 80118f6: 693b ldr r3, [r7, #16] 80118f8: f423 5300 bic.w r3, r3, #8192 @ 0x2000 80118fc: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 80118fe: 683b ldr r3, [r7, #0] 8011900: 695b ldr r3, [r3, #20] 8011902: 011b lsls r3, r3, #4 8011904: 693a ldr r2, [r7, #16] 8011906: 4313 orrs r3, r2 8011908: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 801190a: 683b ldr r3, [r7, #0] 801190c: 699b ldr r3, [r3, #24] 801190e: 011b lsls r3, r3, #4 8011910: 693a ldr r2, [r7, #16] 8011912: 4313 orrs r3, r2 8011914: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8011916: 687b ldr r3, [r7, #4] 8011918: 693a ldr r2, [r7, #16] 801191a: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 801191c: 687b ldr r3, [r7, #4] 801191e: 68fa ldr r2, [r7, #12] 8011920: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8011922: 683b ldr r3, [r7, #0] 8011924: 685a ldr r2, [r3, #4] 8011926: 687b ldr r3, [r7, #4] 8011928: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 801192a: 687b ldr r3, [r7, #4] 801192c: 697a ldr r2, [r7, #20] 801192e: 621a str r2, [r3, #32] } 8011930: bf00 nop 8011932: 371c adds r7, #28 8011934: 46bd mov sp, r7 8011936: bc80 pop {r7} 8011938: 4770 bx lr 801193a: bf00 nop 801193c: 40012c00 .word 0x40012c00 08011940 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8011940: b480 push {r7} 8011942: b087 sub sp, #28 8011944: af00 add r7, sp, #0 8011946: 6078 str r0, [r7, #4] 8011948: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 801194a: 687b ldr r3, [r7, #4] 801194c: 6a1b ldr r3, [r3, #32] 801194e: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8011950: 687b ldr r3, [r7, #4] 8011952: 6a1b ldr r3, [r3, #32] 8011954: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8011958: 687b ldr r3, [r7, #4] 801195a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 801195c: 687b ldr r3, [r7, #4] 801195e: 685b ldr r3, [r3, #4] 8011960: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8011962: 687b ldr r3, [r7, #4] 8011964: 69db ldr r3, [r3, #28] 8011966: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8011968: 68fb ldr r3, [r7, #12] 801196a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 801196e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8011970: 68fb ldr r3, [r7, #12] 8011972: f423 7340 bic.w r3, r3, #768 @ 0x300 8011976: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8011978: 683b ldr r3, [r7, #0] 801197a: 681b ldr r3, [r3, #0] 801197c: 021b lsls r3, r3, #8 801197e: 68fa ldr r2, [r7, #12] 8011980: 4313 orrs r3, r2 8011982: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8011984: 693b ldr r3, [r7, #16] 8011986: f423 5300 bic.w r3, r3, #8192 @ 0x2000 801198a: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 801198c: 683b ldr r3, [r7, #0] 801198e: 689b ldr r3, [r3, #8] 8011990: 031b lsls r3, r3, #12 8011992: 693a ldr r2, [r7, #16] 8011994: 4313 orrs r3, r2 8011996: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8011998: 687b ldr r3, [r7, #4] 801199a: 4a0f ldr r2, [pc, #60] @ (80119d8 ) 801199c: 4293 cmp r3, r2 801199e: d109 bne.n 80119b4 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 80119a0: 697b ldr r3, [r7, #20] 80119a2: f423 4380 bic.w r3, r3, #16384 @ 0x4000 80119a6: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 80119a8: 683b ldr r3, [r7, #0] 80119aa: 695b ldr r3, [r3, #20] 80119ac: 019b lsls r3, r3, #6 80119ae: 697a ldr r2, [r7, #20] 80119b0: 4313 orrs r3, r2 80119b2: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80119b4: 687b ldr r3, [r7, #4] 80119b6: 697a ldr r2, [r7, #20] 80119b8: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 80119ba: 687b ldr r3, [r7, #4] 80119bc: 68fa ldr r2, [r7, #12] 80119be: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 80119c0: 683b ldr r3, [r7, #0] 80119c2: 685a ldr r2, [r3, #4] 80119c4: 687b ldr r3, [r7, #4] 80119c6: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80119c8: 687b ldr r3, [r7, #4] 80119ca: 693a ldr r2, [r7, #16] 80119cc: 621a str r2, [r3, #32] } 80119ce: bf00 nop 80119d0: 371c adds r7, #28 80119d2: 46bd mov sp, r7 80119d4: bc80 pop {r7} 80119d6: 4770 bx lr 80119d8: 40012c00 .word 0x40012c00 080119dc : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 80119dc: b480 push {r7} 80119de: b087 sub sp, #28 80119e0: af00 add r7, sp, #0 80119e2: 60f8 str r0, [r7, #12] 80119e4: 60b9 str r1, [r7, #8] 80119e6: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 80119e8: 68fb ldr r3, [r7, #12] 80119ea: 6a1b ldr r3, [r3, #32] 80119ec: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 80119ee: 68fb ldr r3, [r7, #12] 80119f0: 6a1b ldr r3, [r3, #32] 80119f2: f023 0201 bic.w r2, r3, #1 80119f6: 68fb ldr r3, [r7, #12] 80119f8: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 80119fa: 68fb ldr r3, [r7, #12] 80119fc: 699b ldr r3, [r3, #24] 80119fe: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8011a00: 693b ldr r3, [r7, #16] 8011a02: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8011a06: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8011a08: 687b ldr r3, [r7, #4] 8011a0a: 011b lsls r3, r3, #4 8011a0c: 693a ldr r2, [r7, #16] 8011a0e: 4313 orrs r3, r2 8011a10: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8011a12: 697b ldr r3, [r7, #20] 8011a14: f023 030a bic.w r3, r3, #10 8011a18: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8011a1a: 697a ldr r2, [r7, #20] 8011a1c: 68bb ldr r3, [r7, #8] 8011a1e: 4313 orrs r3, r2 8011a20: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8011a22: 68fb ldr r3, [r7, #12] 8011a24: 693a ldr r2, [r7, #16] 8011a26: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8011a28: 68fb ldr r3, [r7, #12] 8011a2a: 697a ldr r2, [r7, #20] 8011a2c: 621a str r2, [r3, #32] } 8011a2e: bf00 nop 8011a30: 371c adds r7, #28 8011a32: 46bd mov sp, r7 8011a34: bc80 pop {r7} 8011a36: 4770 bx lr 08011a38 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8011a38: b480 push {r7} 8011a3a: b087 sub sp, #28 8011a3c: af00 add r7, sp, #0 8011a3e: 60f8 str r0, [r7, #12] 8011a40: 60b9 str r1, [r7, #8] 8011a42: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8011a44: 68fb ldr r3, [r7, #12] 8011a46: 6a1b ldr r3, [r3, #32] 8011a48: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8011a4a: 68fb ldr r3, [r7, #12] 8011a4c: 6a1b ldr r3, [r3, #32] 8011a4e: f023 0210 bic.w r2, r3, #16 8011a52: 68fb ldr r3, [r7, #12] 8011a54: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8011a56: 68fb ldr r3, [r7, #12] 8011a58: 699b ldr r3, [r3, #24] 8011a5a: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8011a5c: 693b ldr r3, [r7, #16] 8011a5e: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8011a62: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8011a64: 687b ldr r3, [r7, #4] 8011a66: 031b lsls r3, r3, #12 8011a68: 693a ldr r2, [r7, #16] 8011a6a: 4313 orrs r3, r2 8011a6c: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8011a6e: 697b ldr r3, [r7, #20] 8011a70: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8011a74: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8011a76: 68bb ldr r3, [r7, #8] 8011a78: 011b lsls r3, r3, #4 8011a7a: 697a ldr r2, [r7, #20] 8011a7c: 4313 orrs r3, r2 8011a7e: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8011a80: 68fb ldr r3, [r7, #12] 8011a82: 693a ldr r2, [r7, #16] 8011a84: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8011a86: 68fb ldr r3, [r7, #12] 8011a88: 697a ldr r2, [r7, #20] 8011a8a: 621a str r2, [r3, #32] } 8011a8c: bf00 nop 8011a8e: 371c adds r7, #28 8011a90: 46bd mov sp, r7 8011a92: bc80 pop {r7} 8011a94: 4770 bx lr 08011a96 : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8011a96: b480 push {r7} 8011a98: b085 sub sp, #20 8011a9a: af00 add r7, sp, #0 8011a9c: 6078 str r0, [r7, #4] 8011a9e: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8011aa0: 687b ldr r3, [r7, #4] 8011aa2: 689b ldr r3, [r3, #8] 8011aa4: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8011aa6: 68fb ldr r3, [r7, #12] 8011aa8: f023 0370 bic.w r3, r3, #112 @ 0x70 8011aac: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8011aae: 683a ldr r2, [r7, #0] 8011ab0: 68fb ldr r3, [r7, #12] 8011ab2: 4313 orrs r3, r2 8011ab4: f043 0307 orr.w r3, r3, #7 8011ab8: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8011aba: 687b ldr r3, [r7, #4] 8011abc: 68fa ldr r2, [r7, #12] 8011abe: 609a str r2, [r3, #8] } 8011ac0: bf00 nop 8011ac2: 3714 adds r7, #20 8011ac4: 46bd mov sp, r7 8011ac6: bc80 pop {r7} 8011ac8: 4770 bx lr 08011aca : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8011aca: b480 push {r7} 8011acc: b087 sub sp, #28 8011ace: af00 add r7, sp, #0 8011ad0: 60f8 str r0, [r7, #12] 8011ad2: 60b9 str r1, [r7, #8] 8011ad4: 607a str r2, [r7, #4] 8011ad6: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8011ad8: 68fb ldr r3, [r7, #12] 8011ada: 689b ldr r3, [r3, #8] 8011adc: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8011ade: 697b ldr r3, [r7, #20] 8011ae0: f423 437f bic.w r3, r3, #65280 @ 0xff00 8011ae4: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8011ae6: 683b ldr r3, [r7, #0] 8011ae8: 021a lsls r2, r3, #8 8011aea: 687b ldr r3, [r7, #4] 8011aec: 431a orrs r2, r3 8011aee: 68bb ldr r3, [r7, #8] 8011af0: 4313 orrs r3, r2 8011af2: 697a ldr r2, [r7, #20] 8011af4: 4313 orrs r3, r2 8011af6: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8011af8: 68fb ldr r3, [r7, #12] 8011afa: 697a ldr r2, [r7, #20] 8011afc: 609a str r2, [r3, #8] } 8011afe: bf00 nop 8011b00: 371c adds r7, #28 8011b02: 46bd mov sp, r7 8011b04: bc80 pop {r7} 8011b06: 4770 bx lr 08011b08 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8011b08: b480 push {r7} 8011b0a: b087 sub sp, #28 8011b0c: af00 add r7, sp, #0 8011b0e: 60f8 str r0, [r7, #12] 8011b10: 60b9 str r1, [r7, #8] 8011b12: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8011b14: 68bb ldr r3, [r7, #8] 8011b16: f003 031f and.w r3, r3, #31 8011b1a: 2201 movs r2, #1 8011b1c: fa02 f303 lsl.w r3, r2, r3 8011b20: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 8011b22: 68fb ldr r3, [r7, #12] 8011b24: 6a1a ldr r2, [r3, #32] 8011b26: 697b ldr r3, [r7, #20] 8011b28: 43db mvns r3, r3 8011b2a: 401a ands r2, r3 8011b2c: 68fb ldr r3, [r7, #12] 8011b2e: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8011b30: 68fb ldr r3, [r7, #12] 8011b32: 6a1a ldr r2, [r3, #32] 8011b34: 68bb ldr r3, [r7, #8] 8011b36: f003 031f and.w r3, r3, #31 8011b3a: 6879 ldr r1, [r7, #4] 8011b3c: fa01 f303 lsl.w r3, r1, r3 8011b40: 431a orrs r2, r3 8011b42: 68fb ldr r3, [r7, #12] 8011b44: 621a str r2, [r3, #32] } 8011b46: bf00 nop 8011b48: 371c adds r7, #28 8011b4a: 46bd mov sp, r7 8011b4c: bc80 pop {r7} 8011b4e: 4770 bx lr 08011b50 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8011b50: b480 push {r7} 8011b52: b085 sub sp, #20 8011b54: af00 add r7, sp, #0 8011b56: 6078 str r0, [r7, #4] 8011b58: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8011b5a: 687b ldr r3, [r7, #4] 8011b5c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8011b60: 2b01 cmp r3, #1 8011b62: d101 bne.n 8011b68 8011b64: 2302 movs r3, #2 8011b66: e04b b.n 8011c00 8011b68: 687b ldr r3, [r7, #4] 8011b6a: 2201 movs r2, #1 8011b6c: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8011b70: 687b ldr r3, [r7, #4] 8011b72: 2202 movs r2, #2 8011b74: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8011b78: 687b ldr r3, [r7, #4] 8011b7a: 681b ldr r3, [r3, #0] 8011b7c: 685b ldr r3, [r3, #4] 8011b7e: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8011b80: 687b ldr r3, [r7, #4] 8011b82: 681b ldr r3, [r3, #0] 8011b84: 689b ldr r3, [r3, #8] 8011b86: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8011b88: 68fb ldr r3, [r7, #12] 8011b8a: f023 0370 bic.w r3, r3, #112 @ 0x70 8011b8e: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8011b90: 683b ldr r3, [r7, #0] 8011b92: 681b ldr r3, [r3, #0] 8011b94: 68fa ldr r2, [r7, #12] 8011b96: 4313 orrs r3, r2 8011b98: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8011b9a: 687b ldr r3, [r7, #4] 8011b9c: 681b ldr r3, [r3, #0] 8011b9e: 68fa ldr r2, [r7, #12] 8011ba0: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8011ba2: 687b ldr r3, [r7, #4] 8011ba4: 681b ldr r3, [r3, #0] 8011ba6: 4a19 ldr r2, [pc, #100] @ (8011c0c ) 8011ba8: 4293 cmp r3, r2 8011baa: d013 beq.n 8011bd4 8011bac: 687b ldr r3, [r7, #4] 8011bae: 681b ldr r3, [r3, #0] 8011bb0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8011bb4: d00e beq.n 8011bd4 8011bb6: 687b ldr r3, [r7, #4] 8011bb8: 681b ldr r3, [r3, #0] 8011bba: 4a15 ldr r2, [pc, #84] @ (8011c10 ) 8011bbc: 4293 cmp r3, r2 8011bbe: d009 beq.n 8011bd4 8011bc0: 687b ldr r3, [r7, #4] 8011bc2: 681b ldr r3, [r3, #0] 8011bc4: 4a13 ldr r2, [pc, #76] @ (8011c14 ) 8011bc6: 4293 cmp r3, r2 8011bc8: d004 beq.n 8011bd4 8011bca: 687b ldr r3, [r7, #4] 8011bcc: 681b ldr r3, [r3, #0] 8011bce: 4a12 ldr r2, [pc, #72] @ (8011c18 ) 8011bd0: 4293 cmp r3, r2 8011bd2: d10c bne.n 8011bee { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8011bd4: 68bb ldr r3, [r7, #8] 8011bd6: f023 0380 bic.w r3, r3, #128 @ 0x80 8011bda: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8011bdc: 683b ldr r3, [r7, #0] 8011bde: 685b ldr r3, [r3, #4] 8011be0: 68ba ldr r2, [r7, #8] 8011be2: 4313 orrs r3, r2 8011be4: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8011be6: 687b ldr r3, [r7, #4] 8011be8: 681b ldr r3, [r3, #0] 8011bea: 68ba ldr r2, [r7, #8] 8011bec: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8011bee: 687b ldr r3, [r7, #4] 8011bf0: 2201 movs r2, #1 8011bf2: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8011bf6: 687b ldr r3, [r7, #4] 8011bf8: 2200 movs r2, #0 8011bfa: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8011bfe: 2300 movs r3, #0 } 8011c00: 4618 mov r0, r3 8011c02: 3714 adds r7, #20 8011c04: 46bd mov sp, r7 8011c06: bc80 pop {r7} 8011c08: 4770 bx lr 8011c0a: bf00 nop 8011c0c: 40012c00 .word 0x40012c00 8011c10: 40000400 .word 0x40000400 8011c14: 40000800 .word 0x40000800 8011c18: 40000c00 .word 0x40000c00 08011c1c : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8011c1c: b480 push {r7} 8011c1e: b083 sub sp, #12 8011c20: af00 add r7, sp, #0 8011c22: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8011c24: bf00 nop 8011c26: 370c adds r7, #12 8011c28: 46bd mov sp, r7 8011c2a: bc80 pop {r7} 8011c2c: 4770 bx lr 08011c2e : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8011c2e: b480 push {r7} 8011c30: b083 sub sp, #12 8011c32: af00 add r7, sp, #0 8011c34: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8011c36: bf00 nop 8011c38: 370c adds r7, #12 8011c3a: 46bd mov sp, r7 8011c3c: bc80 pop {r7} 8011c3e: 4770 bx lr 08011c40 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8011c40: b580 push {r7, lr} 8011c42: b082 sub sp, #8 8011c44: af00 add r7, sp, #0 8011c46: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8011c48: 687b ldr r3, [r7, #4] 8011c4a: 2b00 cmp r3, #0 8011c4c: d101 bne.n 8011c52 { return HAL_ERROR; 8011c4e: 2301 movs r3, #1 8011c50: e042 b.n 8011cd8 assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 8011c52: 687b ldr r3, [r7, #4] 8011c54: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011c58: b2db uxtb r3, r3 8011c5a: 2b00 cmp r3, #0 8011c5c: d106 bne.n 8011c6c { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8011c5e: 687b ldr r3, [r7, #4] 8011c60: 2200 movs r2, #0 8011c62: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8011c66: 6878 ldr r0, [r7, #4] 8011c68: f7fb fc6c bl 800d544 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8011c6c: 687b ldr r3, [r7, #4] 8011c6e: 2224 movs r2, #36 @ 0x24 8011c70: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8011c74: 687b ldr r3, [r7, #4] 8011c76: 681b ldr r3, [r3, #0] 8011c78: 68da ldr r2, [r3, #12] 8011c7a: 687b ldr r3, [r7, #4] 8011c7c: 681b ldr r3, [r3, #0] 8011c7e: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8011c82: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8011c84: 6878 ldr r0, [r7, #4] 8011c86: f000 ffb5 bl 8012bf4 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8011c8a: 687b ldr r3, [r7, #4] 8011c8c: 681b ldr r3, [r3, #0] 8011c8e: 691a ldr r2, [r3, #16] 8011c90: 687b ldr r3, [r7, #4] 8011c92: 681b ldr r3, [r3, #0] 8011c94: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8011c98: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8011c9a: 687b ldr r3, [r7, #4] 8011c9c: 681b ldr r3, [r3, #0] 8011c9e: 695a ldr r2, [r3, #20] 8011ca0: 687b ldr r3, [r7, #4] 8011ca2: 681b ldr r3, [r3, #0] 8011ca4: f022 022a bic.w r2, r2, #42 @ 0x2a 8011ca8: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8011caa: 687b ldr r3, [r7, #4] 8011cac: 681b ldr r3, [r3, #0] 8011cae: 68da ldr r2, [r3, #12] 8011cb0: 687b ldr r3, [r7, #4] 8011cb2: 681b ldr r3, [r3, #0] 8011cb4: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8011cb8: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8011cba: 687b ldr r3, [r7, #4] 8011cbc: 2200 movs r2, #0 8011cbe: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8011cc0: 687b ldr r3, [r7, #4] 8011cc2: 2220 movs r2, #32 8011cc4: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8011cc8: 687b ldr r3, [r7, #4] 8011cca: 2220 movs r2, #32 8011ccc: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8011cd0: 687b ldr r3, [r7, #4] 8011cd2: 2200 movs r2, #0 8011cd4: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8011cd6: 2300 movs r3, #0 } 8011cd8: 4618 mov r0, r3 8011cda: 3708 adds r7, #8 8011cdc: 46bd mov sp, r7 8011cde: bd80 pop {r7, pc} 08011ce0 : * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8011ce0: b580 push {r7, lr} 8011ce2: b08a sub sp, #40 @ 0x28 8011ce4: af02 add r7, sp, #8 8011ce6: 60f8 str r0, [r7, #12] 8011ce8: 60b9 str r1, [r7, #8] 8011cea: 603b str r3, [r7, #0] 8011cec: 4613 mov r3, r2 8011cee: 80fb strh r3, [r7, #6] const uint8_t *pdata8bits; const uint16_t *pdata16bits; uint32_t tickstart = 0U; 8011cf0: 2300 movs r3, #0 8011cf2: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8011cf4: 68fb ldr r3, [r7, #12] 8011cf6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011cfa: b2db uxtb r3, r3 8011cfc: 2b20 cmp r3, #32 8011cfe: d175 bne.n 8011dec { if ((pData == NULL) || (Size == 0U)) 8011d00: 68bb ldr r3, [r7, #8] 8011d02: 2b00 cmp r3, #0 8011d04: d002 beq.n 8011d0c 8011d06: 88fb ldrh r3, [r7, #6] 8011d08: 2b00 cmp r3, #0 8011d0a: d101 bne.n 8011d10 { return HAL_ERROR; 8011d0c: 2301 movs r3, #1 8011d0e: e06e b.n 8011dee } huart->ErrorCode = HAL_UART_ERROR_NONE; 8011d10: 68fb ldr r3, [r7, #12] 8011d12: 2200 movs r2, #0 8011d14: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8011d16: 68fb ldr r3, [r7, #12] 8011d18: 2221 movs r2, #33 @ 0x21 8011d1a: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8011d1e: f7fb fdd9 bl 800d8d4 8011d22: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 8011d24: 68fb ldr r3, [r7, #12] 8011d26: 88fa ldrh r2, [r7, #6] 8011d28: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8011d2a: 68fb ldr r3, [r7, #12] 8011d2c: 88fa ldrh r2, [r7, #6] 8011d2e: 84da strh r2, [r3, #38] @ 0x26 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8011d30: 68fb ldr r3, [r7, #12] 8011d32: 689b ldr r3, [r3, #8] 8011d34: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8011d38: d108 bne.n 8011d4c 8011d3a: 68fb ldr r3, [r7, #12] 8011d3c: 691b ldr r3, [r3, #16] 8011d3e: 2b00 cmp r3, #0 8011d40: d104 bne.n 8011d4c { pdata8bits = NULL; 8011d42: 2300 movs r3, #0 8011d44: 61fb str r3, [r7, #28] pdata16bits = (const uint16_t *) pData; 8011d46: 68bb ldr r3, [r7, #8] 8011d48: 61bb str r3, [r7, #24] 8011d4a: e003 b.n 8011d54 } else { pdata8bits = pData; 8011d4c: 68bb ldr r3, [r7, #8] 8011d4e: 61fb str r3, [r7, #28] pdata16bits = NULL; 8011d50: 2300 movs r3, #0 8011d52: 61bb str r3, [r7, #24] } while (huart->TxXferCount > 0U) 8011d54: e02e b.n 8011db4 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8011d56: 683b ldr r3, [r7, #0] 8011d58: 9300 str r3, [sp, #0] 8011d5a: 697b ldr r3, [r7, #20] 8011d5c: 2200 movs r2, #0 8011d5e: 2180 movs r1, #128 @ 0x80 8011d60: 68f8 ldr r0, [r7, #12] 8011d62: f000 fcb9 bl 80126d8 8011d66: 4603 mov r3, r0 8011d68: 2b00 cmp r3, #0 8011d6a: d005 beq.n 8011d78 { huart->gState = HAL_UART_STATE_READY; 8011d6c: 68fb ldr r3, [r7, #12] 8011d6e: 2220 movs r2, #32 8011d70: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_TIMEOUT; 8011d74: 2303 movs r3, #3 8011d76: e03a b.n 8011dee } if (pdata8bits == NULL) 8011d78: 69fb ldr r3, [r7, #28] 8011d7a: 2b00 cmp r3, #0 8011d7c: d10b bne.n 8011d96 { huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); 8011d7e: 69bb ldr r3, [r7, #24] 8011d80: 881b ldrh r3, [r3, #0] 8011d82: 461a mov r2, r3 8011d84: 68fb ldr r3, [r7, #12] 8011d86: 681b ldr r3, [r3, #0] 8011d88: f3c2 0208 ubfx r2, r2, #0, #9 8011d8c: 605a str r2, [r3, #4] pdata16bits++; 8011d8e: 69bb ldr r3, [r7, #24] 8011d90: 3302 adds r3, #2 8011d92: 61bb str r3, [r7, #24] 8011d94: e007 b.n 8011da6 } else { huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); 8011d96: 69fb ldr r3, [r7, #28] 8011d98: 781a ldrb r2, [r3, #0] 8011d9a: 68fb ldr r3, [r7, #12] 8011d9c: 681b ldr r3, [r3, #0] 8011d9e: 605a str r2, [r3, #4] pdata8bits++; 8011da0: 69fb ldr r3, [r7, #28] 8011da2: 3301 adds r3, #1 8011da4: 61fb str r3, [r7, #28] } huart->TxXferCount--; 8011da6: 68fb ldr r3, [r7, #12] 8011da8: 8cdb ldrh r3, [r3, #38] @ 0x26 8011daa: b29b uxth r3, r3 8011dac: 3b01 subs r3, #1 8011dae: b29a uxth r2, r3 8011db0: 68fb ldr r3, [r7, #12] 8011db2: 84da strh r2, [r3, #38] @ 0x26 while (huart->TxXferCount > 0U) 8011db4: 68fb ldr r3, [r7, #12] 8011db6: 8cdb ldrh r3, [r3, #38] @ 0x26 8011db8: b29b uxth r3, r3 8011dba: 2b00 cmp r3, #0 8011dbc: d1cb bne.n 8011d56 } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8011dbe: 683b ldr r3, [r7, #0] 8011dc0: 9300 str r3, [sp, #0] 8011dc2: 697b ldr r3, [r7, #20] 8011dc4: 2200 movs r2, #0 8011dc6: 2140 movs r1, #64 @ 0x40 8011dc8: 68f8 ldr r0, [r7, #12] 8011dca: f000 fc85 bl 80126d8 8011dce: 4603 mov r3, r0 8011dd0: 2b00 cmp r3, #0 8011dd2: d005 beq.n 8011de0 { huart->gState = HAL_UART_STATE_READY; 8011dd4: 68fb ldr r3, [r7, #12] 8011dd6: 2220 movs r2, #32 8011dd8: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_TIMEOUT; 8011ddc: 2303 movs r3, #3 8011dde: e006 b.n 8011dee } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8011de0: 68fb ldr r3, [r7, #12] 8011de2: 2220 movs r2, #32 8011de4: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_OK; 8011de8: 2300 movs r3, #0 8011dea: e000 b.n 8011dee } else { return HAL_BUSY; 8011dec: 2302 movs r3, #2 } } 8011dee: 4618 mov r0, r3 8011df0: 3720 adds r7, #32 8011df2: 46bd mov sp, r7 8011df4: bd80 pop {r7, pc} 08011df6 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8011df6: b480 push {r7} 8011df8: b085 sub sp, #20 8011dfa: af00 add r7, sp, #0 8011dfc: 60f8 str r0, [r7, #12] 8011dfe: 60b9 str r1, [r7, #8] 8011e00: 4613 mov r3, r2 8011e02: 80fb strh r3, [r7, #6] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8011e04: 68fb ldr r3, [r7, #12] 8011e06: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011e0a: b2db uxtb r3, r3 8011e0c: 2b20 cmp r3, #32 8011e0e: d121 bne.n 8011e54 { if ((pData == NULL) || (Size == 0U)) 8011e10: 68bb ldr r3, [r7, #8] 8011e12: 2b00 cmp r3, #0 8011e14: d002 beq.n 8011e1c 8011e16: 88fb ldrh r3, [r7, #6] 8011e18: 2b00 cmp r3, #0 8011e1a: d101 bne.n 8011e20 { return HAL_ERROR; 8011e1c: 2301 movs r3, #1 8011e1e: e01a b.n 8011e56 } huart->pTxBuffPtr = pData; 8011e20: 68fb ldr r3, [r7, #12] 8011e22: 68ba ldr r2, [r7, #8] 8011e24: 621a str r2, [r3, #32] huart->TxXferSize = Size; 8011e26: 68fb ldr r3, [r7, #12] 8011e28: 88fa ldrh r2, [r7, #6] 8011e2a: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8011e2c: 68fb ldr r3, [r7, #12] 8011e2e: 88fa ldrh r2, [r7, #6] 8011e30: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 8011e32: 68fb ldr r3, [r7, #12] 8011e34: 2200 movs r2, #0 8011e36: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8011e38: 68fb ldr r3, [r7, #12] 8011e3a: 2221 movs r2, #33 @ 0x21 8011e3c: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the UART Transmit data register empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); 8011e40: 68fb ldr r3, [r7, #12] 8011e42: 681b ldr r3, [r3, #0] 8011e44: 68da ldr r2, [r3, #12] 8011e46: 68fb ldr r3, [r7, #12] 8011e48: 681b ldr r3, [r3, #0] 8011e4a: f042 0280 orr.w r2, r2, #128 @ 0x80 8011e4e: 60da str r2, [r3, #12] return HAL_OK; 8011e50: 2300 movs r3, #0 8011e52: e000 b.n 8011e56 } else { return HAL_BUSY; 8011e54: 2302 movs r3, #2 } } 8011e56: 4618 mov r0, r3 8011e58: 3714 adds r7, #20 8011e5a: 46bd mov sp, r7 8011e5c: bc80 pop {r7} 8011e5e: 4770 bx lr 08011e60 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8011e60: b580 push {r7, lr} 8011e62: b08c sub sp, #48 @ 0x30 8011e64: af00 add r7, sp, #0 8011e66: 60f8 str r0, [r7, #12] 8011e68: 60b9 str r1, [r7, #8] 8011e6a: 4613 mov r3, r2 8011e6c: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8011e6e: 68fb ldr r3, [r7, #12] 8011e70: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8011e74: b2db uxtb r3, r3 8011e76: 2b20 cmp r3, #32 8011e78: d14a bne.n 8011f10 { if ((pData == NULL) || (Size == 0U)) 8011e7a: 68bb ldr r3, [r7, #8] 8011e7c: 2b00 cmp r3, #0 8011e7e: d002 beq.n 8011e86 8011e80: 88fb ldrh r3, [r7, #6] 8011e82: 2b00 cmp r3, #0 8011e84: d101 bne.n 8011e8a { return HAL_ERROR; 8011e86: 2301 movs r3, #1 8011e88: e043 b.n 8011f12 } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8011e8a: 68fb ldr r3, [r7, #12] 8011e8c: 2201 movs r2, #1 8011e8e: 631a str r2, [r3, #48] @ 0x30 huart->RxEventType = HAL_UART_RXEVENT_TC; 8011e90: 68fb ldr r3, [r7, #12] 8011e92: 2200 movs r2, #0 8011e94: 635a str r2, [r3, #52] @ 0x34 status = UART_Start_Receive_IT(huart, pData, Size); 8011e96: 88fb ldrh r3, [r7, #6] 8011e98: 461a mov r2, r3 8011e9a: 68b9 ldr r1, [r7, #8] 8011e9c: 68f8 ldr r0, [r7, #12] 8011e9e: f000 fc74 bl 801278a 8011ea2: 4603 mov r3, r0 8011ea4: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check Rx process has been successfully started */ if (status == HAL_OK) 8011ea8: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8011eac: 2b00 cmp r3, #0 8011eae: d12c bne.n 8011f0a { if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8011eb0: 68fb ldr r3, [r7, #12] 8011eb2: 6b1b ldr r3, [r3, #48] @ 0x30 8011eb4: 2b01 cmp r3, #1 8011eb6: d125 bne.n 8011f04 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8011eb8: 2300 movs r3, #0 8011eba: 613b str r3, [r7, #16] 8011ebc: 68fb ldr r3, [r7, #12] 8011ebe: 681b ldr r3, [r3, #0] 8011ec0: 681b ldr r3, [r3, #0] 8011ec2: 613b str r3, [r7, #16] 8011ec4: 68fb ldr r3, [r7, #12] 8011ec6: 681b ldr r3, [r3, #0] 8011ec8: 685b ldr r3, [r3, #4] 8011eca: 613b str r3, [r7, #16] 8011ecc: 693b ldr r3, [r7, #16] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8011ece: 68fb ldr r3, [r7, #12] 8011ed0: 681b ldr r3, [r3, #0] 8011ed2: 330c adds r3, #12 8011ed4: 61bb str r3, [r7, #24] */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011ed6: 69bb ldr r3, [r7, #24] 8011ed8: e853 3f00 ldrex r3, [r3] 8011edc: 617b str r3, [r7, #20] return(result); 8011ede: 697b ldr r3, [r7, #20] 8011ee0: f043 0310 orr.w r3, r3, #16 8011ee4: 62bb str r3, [r7, #40] @ 0x28 8011ee6: 68fb ldr r3, [r7, #12] 8011ee8: 681b ldr r3, [r3, #0] 8011eea: 330c adds r3, #12 8011eec: 6aba ldr r2, [r7, #40] @ 0x28 8011eee: 627a str r2, [r7, #36] @ 0x24 8011ef0: 623b str r3, [r7, #32] */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011ef2: 6a39 ldr r1, [r7, #32] 8011ef4: 6a7a ldr r2, [r7, #36] @ 0x24 8011ef6: e841 2300 strex r3, r2, [r1] 8011efa: 61fb str r3, [r7, #28] return(result); 8011efc: 69fb ldr r3, [r7, #28] 8011efe: 2b00 cmp r3, #0 8011f00: d1e5 bne.n 8011ece 8011f02: e002 b.n 8011f0a { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8011f04: 2301 movs r3, #1 8011f06: f887 302f strb.w r3, [r7, #47] @ 0x2f } } return status; 8011f0a: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8011f0e: e000 b.n 8011f12 } else { return HAL_BUSY; 8011f10: 2302 movs r3, #2 } } 8011f12: 4618 mov r0, r3 8011f14: 3730 adds r7, #48 @ 0x30 8011f16: 46bd mov sp, r7 8011f18: bd80 pop {r7, pc} ... 08011f1c : * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { 8011f1c: b580 push {r7, lr} 8011f1e: b0a2 sub sp, #136 @ 0x88 8011f20: af00 add r7, sp, #0 8011f22: 6078 str r0, [r7, #4] uint32_t AbortCplt = 0x01U; 8011f24: 2301 movs r3, #1 8011f26: f8c7 3084 str.w r3, [r7, #132] @ 0x84 /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); 8011f2a: 687b ldr r3, [r7, #4] 8011f2c: 681b ldr r3, [r3, #0] 8011f2e: 330c adds r3, #12 8011f30: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011f32: 6e3b ldr r3, [r7, #96] @ 0x60 8011f34: e853 3f00 ldrex r3, [r3] 8011f38: 65fb str r3, [r7, #92] @ 0x5c return(result); 8011f3a: 6dfb ldr r3, [r7, #92] @ 0x5c 8011f3c: f423 73f0 bic.w r3, r3, #480 @ 0x1e0 8011f40: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8011f44: 687b ldr r3, [r7, #4] 8011f46: 681b ldr r3, [r3, #0] 8011f48: 330c adds r3, #12 8011f4a: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8011f4e: 66fa str r2, [r7, #108] @ 0x6c 8011f50: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011f52: 6eb9 ldr r1, [r7, #104] @ 0x68 8011f54: 6efa ldr r2, [r7, #108] @ 0x6c 8011f56: e841 2300 strex r3, r2, [r1] 8011f5a: 667b str r3, [r7, #100] @ 0x64 return(result); 8011f5c: 6e7b ldr r3, [r7, #100] @ 0x64 8011f5e: 2b00 cmp r3, #0 8011f60: d1e3 bne.n 8011f2a ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8011f62: 687b ldr r3, [r7, #4] 8011f64: 681b ldr r3, [r3, #0] 8011f66: 3314 adds r3, #20 8011f68: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011f6a: 6cfb ldr r3, [r7, #76] @ 0x4c 8011f6c: e853 3f00 ldrex r3, [r3] 8011f70: 64bb str r3, [r7, #72] @ 0x48 return(result); 8011f72: 6cbb ldr r3, [r7, #72] @ 0x48 8011f74: f023 0301 bic.w r3, r3, #1 8011f78: 67fb str r3, [r7, #124] @ 0x7c 8011f7a: 687b ldr r3, [r7, #4] 8011f7c: 681b ldr r3, [r3, #0] 8011f7e: 3314 adds r3, #20 8011f80: 6ffa ldr r2, [r7, #124] @ 0x7c 8011f82: 65ba str r2, [r7, #88] @ 0x58 8011f84: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011f86: 6d79 ldr r1, [r7, #84] @ 0x54 8011f88: 6dba ldr r2, [r7, #88] @ 0x58 8011f8a: e841 2300 strex r3, r2, [r1] 8011f8e: 653b str r3, [r7, #80] @ 0x50 return(result); 8011f90: 6d3b ldr r3, [r7, #80] @ 0x50 8011f92: 2b00 cmp r3, #0 8011f94: d1e5 bne.n 8011f62 /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8011f96: 687b ldr r3, [r7, #4] 8011f98: 6b1b ldr r3, [r3, #48] @ 0x30 8011f9a: 2b01 cmp r3, #1 8011f9c: d119 bne.n 8011fd2 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); 8011f9e: 687b ldr r3, [r7, #4] 8011fa0: 681b ldr r3, [r3, #0] 8011fa2: 330c adds r3, #12 8011fa4: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011fa6: 6bbb ldr r3, [r7, #56] @ 0x38 8011fa8: e853 3f00 ldrex r3, [r3] 8011fac: 637b str r3, [r7, #52] @ 0x34 return(result); 8011fae: 6b7b ldr r3, [r7, #52] @ 0x34 8011fb0: f023 0310 bic.w r3, r3, #16 8011fb4: 67bb str r3, [r7, #120] @ 0x78 8011fb6: 687b ldr r3, [r7, #4] 8011fb8: 681b ldr r3, [r3, #0] 8011fba: 330c adds r3, #12 8011fbc: 6fba ldr r2, [r7, #120] @ 0x78 8011fbe: 647a str r2, [r7, #68] @ 0x44 8011fc0: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011fc2: 6c39 ldr r1, [r7, #64] @ 0x40 8011fc4: 6c7a ldr r2, [r7, #68] @ 0x44 8011fc6: e841 2300 strex r3, r2, [r1] 8011fca: 63fb str r3, [r7, #60] @ 0x3c return(result); 8011fcc: 6bfb ldr r3, [r7, #60] @ 0x3c 8011fce: 2b00 cmp r3, #0 8011fd0: d1e5 bne.n 8011f9e } /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ if (huart->hdmatx != NULL) 8011fd2: 687b ldr r3, [r7, #4] 8011fd4: 6b9b ldr r3, [r3, #56] @ 0x38 8011fd6: 2b00 cmp r3, #0 8011fd8: d00f beq.n 8011ffa { /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. Otherwise, set it to NULL */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) 8011fda: 687b ldr r3, [r7, #4] 8011fdc: 681b ldr r3, [r3, #0] 8011fde: 695b ldr r3, [r3, #20] 8011fe0: f003 0380 and.w r3, r3, #128 @ 0x80 8011fe4: 2b00 cmp r3, #0 8011fe6: d004 beq.n 8011ff2 { huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; 8011fe8: 687b ldr r3, [r7, #4] 8011fea: 6b9b ldr r3, [r3, #56] @ 0x38 8011fec: 4a53 ldr r2, [pc, #332] @ (801213c ) 8011fee: 635a str r2, [r3, #52] @ 0x34 8011ff0: e003 b.n 8011ffa } else { huart->hdmatx->XferAbortCallback = NULL; 8011ff2: 687b ldr r3, [r7, #4] 8011ff4: 6b9b ldr r3, [r3, #56] @ 0x38 8011ff6: 2200 movs r2, #0 8011ff8: 635a str r2, [r3, #52] @ 0x34 } } /* DMA Rx Handle is valid */ if (huart->hdmarx != NULL) 8011ffa: 687b ldr r3, [r7, #4] 8011ffc: 6bdb ldr r3, [r3, #60] @ 0x3c 8011ffe: 2b00 cmp r3, #0 8012000: d00f beq.n 8012022 { /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. Otherwise, set it to NULL */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8012002: 687b ldr r3, [r7, #4] 8012004: 681b ldr r3, [r3, #0] 8012006: 695b ldr r3, [r3, #20] 8012008: f003 0340 and.w r3, r3, #64 @ 0x40 801200c: 2b00 cmp r3, #0 801200e: d004 beq.n 801201a { huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; 8012010: 687b ldr r3, [r7, #4] 8012012: 6bdb ldr r3, [r3, #60] @ 0x3c 8012014: 4a4a ldr r2, [pc, #296] @ (8012140 ) 8012016: 635a str r2, [r3, #52] @ 0x34 8012018: e003 b.n 8012022 } else { huart->hdmarx->XferAbortCallback = NULL; 801201a: 687b ldr r3, [r7, #4] 801201c: 6bdb ldr r3, [r3, #60] @ 0x3c 801201e: 2200 movs r2, #0 8012020: 635a str r2, [r3, #52] @ 0x34 } } /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) 8012022: 687b ldr r3, [r7, #4] 8012024: 681b ldr r3, [r3, #0] 8012026: 695b ldr r3, [r3, #20] 8012028: f003 0380 and.w r3, r3, #128 @ 0x80 801202c: 2b00 cmp r3, #0 801202e: d02d beq.n 801208c { /* Disable DMA Tx at UART level */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8012030: 687b ldr r3, [r7, #4] 8012032: 681b ldr r3, [r3, #0] 8012034: 3314 adds r3, #20 8012036: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012038: 6a7b ldr r3, [r7, #36] @ 0x24 801203a: e853 3f00 ldrex r3, [r3] 801203e: 623b str r3, [r7, #32] return(result); 8012040: 6a3b ldr r3, [r7, #32] 8012042: f023 0380 bic.w r3, r3, #128 @ 0x80 8012046: 677b str r3, [r7, #116] @ 0x74 8012048: 687b ldr r3, [r7, #4] 801204a: 681b ldr r3, [r3, #0] 801204c: 3314 adds r3, #20 801204e: 6f7a ldr r2, [r7, #116] @ 0x74 8012050: 633a str r2, [r7, #48] @ 0x30 8012052: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012054: 6af9 ldr r1, [r7, #44] @ 0x2c 8012056: 6b3a ldr r2, [r7, #48] @ 0x30 8012058: e841 2300 strex r3, r2, [r1] 801205c: 62bb str r3, [r7, #40] @ 0x28 return(result); 801205e: 6abb ldr r3, [r7, #40] @ 0x28 8012060: 2b00 cmp r3, #0 8012062: d1e5 bne.n 8012030 /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) 8012064: 687b ldr r3, [r7, #4] 8012066: 6b9b ldr r3, [r3, #56] @ 0x38 8012068: 2b00 cmp r3, #0 801206a: d00f beq.n 801208c { /* UART Tx DMA Abort callback has already been initialised : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA TX */ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) 801206c: 687b ldr r3, [r7, #4] 801206e: 6b9b ldr r3, [r3, #56] @ 0x38 8012070: 4618 mov r0, r3 8012072: f7fd f99d bl 800f3b0 8012076: 4603 mov r3, r0 8012078: 2b00 cmp r3, #0 801207a: d004 beq.n 8012086 { huart->hdmatx->XferAbortCallback = NULL; 801207c: 687b ldr r3, [r7, #4] 801207e: 6b9b ldr r3, [r3, #56] @ 0x38 8012080: 2200 movs r2, #0 8012082: 635a str r2, [r3, #52] @ 0x34 8012084: e002 b.n 801208c } else { AbortCplt = 0x00U; 8012086: 2300 movs r3, #0 8012088: f8c7 3084 str.w r3, [r7, #132] @ 0x84 } } } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801208c: 687b ldr r3, [r7, #4] 801208e: 681b ldr r3, [r3, #0] 8012090: 695b ldr r3, [r3, #20] 8012092: f003 0340 and.w r3, r3, #64 @ 0x40 8012096: 2b00 cmp r3, #0 8012098: d030 beq.n 80120fc { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 801209a: 687b ldr r3, [r7, #4] 801209c: 681b ldr r3, [r3, #0] 801209e: 3314 adds r3, #20 80120a0: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80120a2: 693b ldr r3, [r7, #16] 80120a4: e853 3f00 ldrex r3, [r3] 80120a8: 60fb str r3, [r7, #12] return(result); 80120aa: 68fb ldr r3, [r7, #12] 80120ac: f023 0340 bic.w r3, r3, #64 @ 0x40 80120b0: 673b str r3, [r7, #112] @ 0x70 80120b2: 687b ldr r3, [r7, #4] 80120b4: 681b ldr r3, [r3, #0] 80120b6: 3314 adds r3, #20 80120b8: 6f3a ldr r2, [r7, #112] @ 0x70 80120ba: 61fa str r2, [r7, #28] 80120bc: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80120be: 69b9 ldr r1, [r7, #24] 80120c0: 69fa ldr r2, [r7, #28] 80120c2: e841 2300 strex r3, r2, [r1] 80120c6: 617b str r3, [r7, #20] return(result); 80120c8: 697b ldr r3, [r7, #20] 80120ca: 2b00 cmp r3, #0 80120cc: d1e5 bne.n 801209a /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) 80120ce: 687b ldr r3, [r7, #4] 80120d0: 6bdb ldr r3, [r3, #60] @ 0x3c 80120d2: 2b00 cmp r3, #0 80120d4: d012 beq.n 80120fc { /* UART Rx DMA Abort callback has already been initialised : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 80120d6: 687b ldr r3, [r7, #4] 80120d8: 6bdb ldr r3, [r3, #60] @ 0x3c 80120da: 4618 mov r0, r3 80120dc: f7fd f968 bl 800f3b0 80120e0: 4603 mov r3, r0 80120e2: 2b00 cmp r3, #0 80120e4: d007 beq.n 80120f6 { huart->hdmarx->XferAbortCallback = NULL; 80120e6: 687b ldr r3, [r7, #4] 80120e8: 6bdb ldr r3, [r3, #60] @ 0x3c 80120ea: 2200 movs r2, #0 80120ec: 635a str r2, [r3, #52] @ 0x34 AbortCplt = 0x01U; 80120ee: 2301 movs r3, #1 80120f0: f8c7 3084 str.w r3, [r7, #132] @ 0x84 80120f4: e002 b.n 80120fc } else { AbortCplt = 0x00U; 80120f6: 2300 movs r3, #0 80120f8: f8c7 3084 str.w r3, [r7, #132] @ 0x84 } } } /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (AbortCplt == 0x01U) 80120fc: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8012100: 2b01 cmp r3, #1 8012102: d116 bne.n 8012132 { /* Reset Tx and Rx transfer counters */ huart->TxXferCount = 0x00U; 8012104: 687b ldr r3, [r7, #4] 8012106: 2200 movs r2, #0 8012108: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 801210a: 687b ldr r3, [r7, #4] 801210c: 2200 movs r2, #0 801210e: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012110: 687b ldr r3, [r7, #4] 8012112: 2200 movs r2, #0 8012114: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 8012116: 687b ldr r3, [r7, #4] 8012118: 2220 movs r2, #32 801211a: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 801211e: 687b ldr r3, [r7, #4] 8012120: 2220 movs r2, #32 8012122: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012126: 687b ldr r3, [r7, #4] 8012128: 2200 movs r2, #0 801212a: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 801212c: 6878 ldr r0, [r7, #4] 801212e: f000 faad bl 801268c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8012132: 2300 movs r3, #0 } 8012134: 4618 mov r0, r3 8012136: 3788 adds r7, #136 @ 0x88 8012138: 46bd mov sp, r7 801213a: bd80 pop {r7, pc} 801213c: 080128e9 .word 0x080128e9 8012140: 08012949 .word 0x08012949 08012144 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8012144: b580 push {r7, lr} 8012146: b0ba sub sp, #232 @ 0xe8 8012148: af00 add r7, sp, #0 801214a: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 801214c: 687b ldr r3, [r7, #4] 801214e: 681b ldr r3, [r3, #0] 8012150: 681b ldr r3, [r3, #0] 8012152: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8012156: 687b ldr r3, [r7, #4] 8012158: 681b ldr r3, [r3, #0] 801215a: 68db ldr r3, [r3, #12] 801215c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8012160: 687b ldr r3, [r7, #4] 8012162: 681b ldr r3, [r3, #0] 8012164: 695b ldr r3, [r3, #20] 8012166: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 801216a: 2300 movs r3, #0 801216c: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 8012170: 2300 movs r3, #0 8012172: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8012176: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801217a: f003 030f and.w r3, r3, #15 801217e: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 8012182: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8012186: 2b00 cmp r3, #0 8012188: d10f bne.n 80121aa { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 801218a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801218e: f003 0320 and.w r3, r3, #32 8012192: 2b00 cmp r3, #0 8012194: d009 beq.n 80121aa 8012196: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801219a: f003 0320 and.w r3, r3, #32 801219e: 2b00 cmp r3, #0 80121a0: d003 beq.n 80121aa { UART_Receive_IT(huart); 80121a2: 6878 ldr r0, [r7, #4] 80121a4: f000 fc67 bl 8012a76 return; 80121a8: e25b b.n 8012662 } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 80121aa: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80121ae: 2b00 cmp r3, #0 80121b0: f000 80de beq.w 8012370 80121b4: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80121b8: f003 0301 and.w r3, r3, #1 80121bc: 2b00 cmp r3, #0 80121be: d106 bne.n 80121ce || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 80121c0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80121c4: f403 7390 and.w r3, r3, #288 @ 0x120 80121c8: 2b00 cmp r3, #0 80121ca: f000 80d1 beq.w 8012370 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 80121ce: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80121d2: f003 0301 and.w r3, r3, #1 80121d6: 2b00 cmp r3, #0 80121d8: d00b beq.n 80121f2 80121da: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80121de: f403 7380 and.w r3, r3, #256 @ 0x100 80121e2: 2b00 cmp r3, #0 80121e4: d005 beq.n 80121f2 { huart->ErrorCode |= HAL_UART_ERROR_PE; 80121e6: 687b ldr r3, [r7, #4] 80121e8: 6c5b ldr r3, [r3, #68] @ 0x44 80121ea: f043 0201 orr.w r2, r3, #1 80121ee: 687b ldr r3, [r7, #4] 80121f0: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 80121f2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80121f6: f003 0304 and.w r3, r3, #4 80121fa: 2b00 cmp r3, #0 80121fc: d00b beq.n 8012216 80121fe: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8012202: f003 0301 and.w r3, r3, #1 8012206: 2b00 cmp r3, #0 8012208: d005 beq.n 8012216 { huart->ErrorCode |= HAL_UART_ERROR_NE; 801220a: 687b ldr r3, [r7, #4] 801220c: 6c5b ldr r3, [r3, #68] @ 0x44 801220e: f043 0202 orr.w r2, r3, #2 8012212: 687b ldr r3, [r7, #4] 8012214: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8012216: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801221a: f003 0302 and.w r3, r3, #2 801221e: 2b00 cmp r3, #0 8012220: d00b beq.n 801223a 8012222: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8012226: f003 0301 and.w r3, r3, #1 801222a: 2b00 cmp r3, #0 801222c: d005 beq.n 801223a { huart->ErrorCode |= HAL_UART_ERROR_FE; 801222e: 687b ldr r3, [r7, #4] 8012230: 6c5b ldr r3, [r3, #68] @ 0x44 8012232: f043 0204 orr.w r2, r3, #4 8012236: 687b ldr r3, [r7, #4] 8012238: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 801223a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801223e: f003 0308 and.w r3, r3, #8 8012242: 2b00 cmp r3, #0 8012244: d011 beq.n 801226a 8012246: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801224a: f003 0320 and.w r3, r3, #32 801224e: 2b00 cmp r3, #0 8012250: d105 bne.n 801225e || ((cr3its & USART_CR3_EIE) != RESET))) 8012252: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8012256: f003 0301 and.w r3, r3, #1 801225a: 2b00 cmp r3, #0 801225c: d005 beq.n 801226a { huart->ErrorCode |= HAL_UART_ERROR_ORE; 801225e: 687b ldr r3, [r7, #4] 8012260: 6c5b ldr r3, [r3, #68] @ 0x44 8012262: f043 0208 orr.w r2, r3, #8 8012266: 687b ldr r3, [r7, #4] 8012268: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 801226a: 687b ldr r3, [r7, #4] 801226c: 6c5b ldr r3, [r3, #68] @ 0x44 801226e: 2b00 cmp r3, #0 8012270: f000 81f2 beq.w 8012658 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8012274: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012278: f003 0320 and.w r3, r3, #32 801227c: 2b00 cmp r3, #0 801227e: d008 beq.n 8012292 8012280: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012284: f003 0320 and.w r3, r3, #32 8012288: 2b00 cmp r3, #0 801228a: d002 beq.n 8012292 { UART_Receive_IT(huart); 801228c: 6878 ldr r0, [r7, #4] 801228e: f000 fbf2 bl 8012a76 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8012292: 687b ldr r3, [r7, #4] 8012294: 681b ldr r3, [r3, #0] 8012296: 695b ldr r3, [r3, #20] 8012298: f003 0340 and.w r3, r3, #64 @ 0x40 801229c: 2b00 cmp r3, #0 801229e: bf14 ite ne 80122a0: 2301 movne r3, #1 80122a2: 2300 moveq r3, #0 80122a4: b2db uxtb r3, r3 80122a6: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 80122aa: 687b ldr r3, [r7, #4] 80122ac: 6c5b ldr r3, [r3, #68] @ 0x44 80122ae: f003 0308 and.w r3, r3, #8 80122b2: 2b00 cmp r3, #0 80122b4: d103 bne.n 80122be 80122b6: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 80122ba: 2b00 cmp r3, #0 80122bc: d04f beq.n 801235e { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 80122be: 6878 ldr r0, [r7, #4] 80122c0: f000 fa9c bl 80127fc /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80122c4: 687b ldr r3, [r7, #4] 80122c6: 681b ldr r3, [r3, #0] 80122c8: 695b ldr r3, [r3, #20] 80122ca: f003 0340 and.w r3, r3, #64 @ 0x40 80122ce: 2b00 cmp r3, #0 80122d0: d041 beq.n 8012356 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80122d2: 687b ldr r3, [r7, #4] 80122d4: 681b ldr r3, [r3, #0] 80122d6: 3314 adds r3, #20 80122d8: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80122dc: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 80122e0: e853 3f00 ldrex r3, [r3] 80122e4: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 80122e8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 80122ec: f023 0340 bic.w r3, r3, #64 @ 0x40 80122f0: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 80122f4: 687b ldr r3, [r7, #4] 80122f6: 681b ldr r3, [r3, #0] 80122f8: 3314 adds r3, #20 80122fa: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 80122fe: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8012302: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012306: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 801230a: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 801230e: e841 2300 strex r3, r2, [r1] 8012312: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8012316: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 801231a: 2b00 cmp r3, #0 801231c: d1d9 bne.n 80122d2 /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 801231e: 687b ldr r3, [r7, #4] 8012320: 6bdb ldr r3, [r3, #60] @ 0x3c 8012322: 2b00 cmp r3, #0 8012324: d013 beq.n 801234e { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8012326: 687b ldr r3, [r7, #4] 8012328: 6bdb ldr r3, [r3, #60] @ 0x3c 801232a: 4a7e ldr r2, [pc, #504] @ (8012524 ) 801232c: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 801232e: 687b ldr r3, [r7, #4] 8012330: 6bdb ldr r3, [r3, #60] @ 0x3c 8012332: 4618 mov r0, r3 8012334: f7fd f83c bl 800f3b0 8012338: 4603 mov r3, r0 801233a: 2b00 cmp r3, #0 801233c: d016 beq.n 801236c { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 801233e: 687b ldr r3, [r7, #4] 8012340: 6bdb ldr r3, [r3, #60] @ 0x3c 8012342: 6b5b ldr r3, [r3, #52] @ 0x34 8012344: 687a ldr r2, [r7, #4] 8012346: 6bd2 ldr r2, [r2, #60] @ 0x3c 8012348: 4610 mov r0, r2 801234a: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801234c: e00e b.n 801236c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 801234e: 6878 ldr r0, [r7, #4] 8012350: f000 f993 bl 801267a if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8012354: e00a b.n 801236c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8012356: 6878 ldr r0, [r7, #4] 8012358: f000 f98f bl 801267a if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801235c: e006 b.n 801236c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 801235e: 6878 ldr r0, [r7, #4] 8012360: f000 f98b bl 801267a #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012364: 687b ldr r3, [r7, #4] 8012366: 2200 movs r2, #0 8012368: 645a str r2, [r3, #68] @ 0x44 } } return; 801236a: e175 b.n 8012658 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801236c: bf00 nop return; 801236e: e173 b.n 8012658 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012370: 687b ldr r3, [r7, #4] 8012372: 6b1b ldr r3, [r3, #48] @ 0x30 8012374: 2b01 cmp r3, #1 8012376: f040 814f bne.w 8012618 && ((isrflags & USART_SR_IDLE) != 0U) 801237a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801237e: f003 0310 and.w r3, r3, #16 8012382: 2b00 cmp r3, #0 8012384: f000 8148 beq.w 8012618 && ((cr1its & USART_SR_IDLE) != 0U)) 8012388: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801238c: f003 0310 and.w r3, r3, #16 8012390: 2b00 cmp r3, #0 8012392: f000 8141 beq.w 8012618 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8012396: 2300 movs r3, #0 8012398: 60bb str r3, [r7, #8] 801239a: 687b ldr r3, [r7, #4] 801239c: 681b ldr r3, [r3, #0] 801239e: 681b ldr r3, [r3, #0] 80123a0: 60bb str r3, [r7, #8] 80123a2: 687b ldr r3, [r7, #4] 80123a4: 681b ldr r3, [r3, #0] 80123a6: 685b ldr r3, [r3, #4] 80123a8: 60bb str r3, [r7, #8] 80123aa: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80123ac: 687b ldr r3, [r7, #4] 80123ae: 681b ldr r3, [r3, #0] 80123b0: 695b ldr r3, [r3, #20] 80123b2: f003 0340 and.w r3, r3, #64 @ 0x40 80123b6: 2b00 cmp r3, #0 80123b8: f000 80b6 beq.w 8012528 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 80123bc: 687b ldr r3, [r7, #4] 80123be: 6bdb ldr r3, [r3, #60] @ 0x3c 80123c0: 681b ldr r3, [r3, #0] 80123c2: 685b ldr r3, [r3, #4] 80123c4: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 80123c8: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 80123cc: 2b00 cmp r3, #0 80123ce: f000 8145 beq.w 801265c && (nb_remaining_rx_data < huart->RxXferSize)) 80123d2: 687b ldr r3, [r7, #4] 80123d4: 8d9b ldrh r3, [r3, #44] @ 0x2c 80123d6: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80123da: 429a cmp r2, r3 80123dc: f080 813e bcs.w 801265c { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 80123e0: 687b ldr r3, [r7, #4] 80123e2: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80123e6: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 80123e8: 687b ldr r3, [r7, #4] 80123ea: 6bdb ldr r3, [r3, #60] @ 0x3c 80123ec: 699b ldr r3, [r3, #24] 80123ee: 2b20 cmp r3, #32 80123f0: f000 8088 beq.w 8012504 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80123f4: 687b ldr r3, [r7, #4] 80123f6: 681b ldr r3, [r3, #0] 80123f8: 330c adds r3, #12 80123fa: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80123fe: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8012402: e853 3f00 ldrex r3, [r3] 8012406: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 801240a: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 801240e: f423 7380 bic.w r3, r3, #256 @ 0x100 8012412: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8012416: 687b ldr r3, [r7, #4] 8012418: 681b ldr r3, [r3, #0] 801241a: 330c adds r3, #12 801241c: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 8012420: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8012424: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012428: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 801242c: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8012430: e841 2300 strex r3, r2, [r1] 8012434: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8012438: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 801243c: 2b00 cmp r3, #0 801243e: d1d9 bne.n 80123f4 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012440: 687b ldr r3, [r7, #4] 8012442: 681b ldr r3, [r3, #0] 8012444: 3314 adds r3, #20 8012446: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012448: 6f7b ldr r3, [r7, #116] @ 0x74 801244a: e853 3f00 ldrex r3, [r3] 801244e: 673b str r3, [r7, #112] @ 0x70 return(result); 8012450: 6f3b ldr r3, [r7, #112] @ 0x70 8012452: f023 0301 bic.w r3, r3, #1 8012456: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 801245a: 687b ldr r3, [r7, #4] 801245c: 681b ldr r3, [r3, #0] 801245e: 3314 adds r3, #20 8012460: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8012464: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8012468: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801246a: 6ff9 ldr r1, [r7, #124] @ 0x7c 801246c: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8012470: e841 2300 strex r3, r2, [r1] 8012474: 67bb str r3, [r7, #120] @ 0x78 return(result); 8012476: 6fbb ldr r3, [r7, #120] @ 0x78 8012478: 2b00 cmp r3, #0 801247a: d1e1 bne.n 8012440 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 801247c: 687b ldr r3, [r7, #4] 801247e: 681b ldr r3, [r3, #0] 8012480: 3314 adds r3, #20 8012482: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012484: 6e3b ldr r3, [r7, #96] @ 0x60 8012486: e853 3f00 ldrex r3, [r3] 801248a: 65fb str r3, [r7, #92] @ 0x5c return(result); 801248c: 6dfb ldr r3, [r7, #92] @ 0x5c 801248e: f023 0340 bic.w r3, r3, #64 @ 0x40 8012492: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8012496: 687b ldr r3, [r7, #4] 8012498: 681b ldr r3, [r3, #0] 801249a: 3314 adds r3, #20 801249c: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 80124a0: 66fa str r2, [r7, #108] @ 0x6c 80124a2: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80124a4: 6eb9 ldr r1, [r7, #104] @ 0x68 80124a6: 6efa ldr r2, [r7, #108] @ 0x6c 80124a8: e841 2300 strex r3, r2, [r1] 80124ac: 667b str r3, [r7, #100] @ 0x64 return(result); 80124ae: 6e7b ldr r3, [r7, #100] @ 0x64 80124b0: 2b00 cmp r3, #0 80124b2: d1e3 bne.n 801247c /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80124b4: 687b ldr r3, [r7, #4] 80124b6: 2220 movs r2, #32 80124b8: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80124bc: 687b ldr r3, [r7, #4] 80124be: 2200 movs r2, #0 80124c0: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80124c2: 687b ldr r3, [r7, #4] 80124c4: 681b ldr r3, [r3, #0] 80124c6: 330c adds r3, #12 80124c8: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80124ca: 6cfb ldr r3, [r7, #76] @ 0x4c 80124cc: e853 3f00 ldrex r3, [r3] 80124d0: 64bb str r3, [r7, #72] @ 0x48 return(result); 80124d2: 6cbb ldr r3, [r7, #72] @ 0x48 80124d4: f023 0310 bic.w r3, r3, #16 80124d8: f8c7 30ac str.w r3, [r7, #172] @ 0xac 80124dc: 687b ldr r3, [r7, #4] 80124de: 681b ldr r3, [r3, #0] 80124e0: 330c adds r3, #12 80124e2: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 80124e6: 65ba str r2, [r7, #88] @ 0x58 80124e8: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80124ea: 6d79 ldr r1, [r7, #84] @ 0x54 80124ec: 6dba ldr r2, [r7, #88] @ 0x58 80124ee: e841 2300 strex r3, r2, [r1] 80124f2: 653b str r3, [r7, #80] @ 0x50 return(result); 80124f4: 6d3b ldr r3, [r7, #80] @ 0x50 80124f6: 2b00 cmp r3, #0 80124f8: d1e3 bne.n 80124c2 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 80124fa: 687b ldr r3, [r7, #4] 80124fc: 6bdb ldr r3, [r3, #60] @ 0x3c 80124fe: 4618 mov r0, r3 8012500: f7fc ff1b bl 800f33a } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8012504: 687b ldr r3, [r7, #4] 8012506: 2202 movs r2, #2 8012508: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 801250a: 687b ldr r3, [r7, #4] 801250c: 8d9a ldrh r2, [r3, #44] @ 0x2c 801250e: 687b ldr r3, [r7, #4] 8012510: 8ddb ldrh r3, [r3, #46] @ 0x2e 8012512: b29b uxth r3, r3 8012514: 1ad3 subs r3, r2, r3 8012516: b29b uxth r3, r3 8012518: 4619 mov r1, r3 801251a: 6878 ldr r0, [r7, #4] 801251c: f7fa f802 bl 800c524 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8012520: e09c b.n 801265c 8012522: bf00 nop 8012524: 080128c1 .word 0x080128c1 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8012528: 687b ldr r3, [r7, #4] 801252a: 8d9a ldrh r2, [r3, #44] @ 0x2c 801252c: 687b ldr r3, [r7, #4] 801252e: 8ddb ldrh r3, [r3, #46] @ 0x2e 8012530: b29b uxth r3, r3 8012532: 1ad3 subs r3, r2, r3 8012534: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8012538: 687b ldr r3, [r7, #4] 801253a: 8ddb ldrh r3, [r3, #46] @ 0x2e 801253c: b29b uxth r3, r3 801253e: 2b00 cmp r3, #0 8012540: f000 808e beq.w 8012660 && (nb_rx_data > 0U)) 8012544: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8012548: 2b00 cmp r3, #0 801254a: f000 8089 beq.w 8012660 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 801254e: 687b ldr r3, [r7, #4] 8012550: 681b ldr r3, [r3, #0] 8012552: 330c adds r3, #12 8012554: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012556: 6bbb ldr r3, [r7, #56] @ 0x38 8012558: e853 3f00 ldrex r3, [r3] 801255c: 637b str r3, [r7, #52] @ 0x34 return(result); 801255e: 6b7b ldr r3, [r7, #52] @ 0x34 8012560: f423 7390 bic.w r3, r3, #288 @ 0x120 8012564: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8012568: 687b ldr r3, [r7, #4] 801256a: 681b ldr r3, [r3, #0] 801256c: 330c adds r3, #12 801256e: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 8012572: 647a str r2, [r7, #68] @ 0x44 8012574: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012576: 6c39 ldr r1, [r7, #64] @ 0x40 8012578: 6c7a ldr r2, [r7, #68] @ 0x44 801257a: e841 2300 strex r3, r2, [r1] 801257e: 63fb str r3, [r7, #60] @ 0x3c return(result); 8012580: 6bfb ldr r3, [r7, #60] @ 0x3c 8012582: 2b00 cmp r3, #0 8012584: d1e3 bne.n 801254e /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012586: 687b ldr r3, [r7, #4] 8012588: 681b ldr r3, [r3, #0] 801258a: 3314 adds r3, #20 801258c: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801258e: 6a7b ldr r3, [r7, #36] @ 0x24 8012590: e853 3f00 ldrex r3, [r3] 8012594: 623b str r3, [r7, #32] return(result); 8012596: 6a3b ldr r3, [r7, #32] 8012598: f023 0301 bic.w r3, r3, #1 801259c: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 80125a0: 687b ldr r3, [r7, #4] 80125a2: 681b ldr r3, [r3, #0] 80125a4: 3314 adds r3, #20 80125a6: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 80125aa: 633a str r2, [r7, #48] @ 0x30 80125ac: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80125ae: 6af9 ldr r1, [r7, #44] @ 0x2c 80125b0: 6b3a ldr r2, [r7, #48] @ 0x30 80125b2: e841 2300 strex r3, r2, [r1] 80125b6: 62bb str r3, [r7, #40] @ 0x28 return(result); 80125b8: 6abb ldr r3, [r7, #40] @ 0x28 80125ba: 2b00 cmp r3, #0 80125bc: d1e3 bne.n 8012586 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80125be: 687b ldr r3, [r7, #4] 80125c0: 2220 movs r2, #32 80125c2: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80125c6: 687b ldr r3, [r7, #4] 80125c8: 2200 movs r2, #0 80125ca: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80125cc: 687b ldr r3, [r7, #4] 80125ce: 681b ldr r3, [r3, #0] 80125d0: 330c adds r3, #12 80125d2: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80125d4: 693b ldr r3, [r7, #16] 80125d6: e853 3f00 ldrex r3, [r3] 80125da: 60fb str r3, [r7, #12] return(result); 80125dc: 68fb ldr r3, [r7, #12] 80125de: f023 0310 bic.w r3, r3, #16 80125e2: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 80125e6: 687b ldr r3, [r7, #4] 80125e8: 681b ldr r3, [r3, #0] 80125ea: 330c adds r3, #12 80125ec: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 80125f0: 61fa str r2, [r7, #28] 80125f2: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80125f4: 69b9 ldr r1, [r7, #24] 80125f6: 69fa ldr r2, [r7, #28] 80125f8: e841 2300 strex r3, r2, [r1] 80125fc: 617b str r3, [r7, #20] return(result); 80125fe: 697b ldr r3, [r7, #20] 8012600: 2b00 cmp r3, #0 8012602: d1e3 bne.n 80125cc /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8012604: 687b ldr r3, [r7, #4] 8012606: 2202 movs r2, #2 8012608: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 801260a: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 801260e: 4619 mov r1, r3 8012610: 6878 ldr r0, [r7, #4] 8012612: f7f9 ff87 bl 800c524 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8012616: e023 b.n 8012660 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8012618: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801261c: f003 0380 and.w r3, r3, #128 @ 0x80 8012620: 2b00 cmp r3, #0 8012622: d009 beq.n 8012638 8012624: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012628: f003 0380 and.w r3, r3, #128 @ 0x80 801262c: 2b00 cmp r3, #0 801262e: d003 beq.n 8012638 { UART_Transmit_IT(huart); 8012630: 6878 ldr r0, [r7, #4] 8012632: f000 f9b9 bl 80129a8 return; 8012636: e014 b.n 8012662 } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8012638: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801263c: f003 0340 and.w r3, r3, #64 @ 0x40 8012640: 2b00 cmp r3, #0 8012642: d00e beq.n 8012662 8012644: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012648: f003 0340 and.w r3, r3, #64 @ 0x40 801264c: 2b00 cmp r3, #0 801264e: d008 beq.n 8012662 { UART_EndTransmit_IT(huart); 8012650: 6878 ldr r0, [r7, #4] 8012652: f000 f9f8 bl 8012a46 return; 8012656: e004 b.n 8012662 return; 8012658: bf00 nop 801265a: e002 b.n 8012662 return; 801265c: bf00 nop 801265e: e000 b.n 8012662 return; 8012660: bf00 nop } } 8012662: 37e8 adds r7, #232 @ 0xe8 8012664: 46bd mov sp, r7 8012666: bd80 pop {r7, pc} 08012668 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8012668: b480 push {r7} 801266a: b083 sub sp, #12 801266c: af00 add r7, sp, #0 801266e: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback could be implemented in the user file */ } 8012670: bf00 nop 8012672: 370c adds r7, #12 8012674: 46bd mov sp, r7 8012676: bc80 pop {r7} 8012678: 4770 bx lr 0801267a : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 801267a: b480 push {r7} 801267c: b083 sub sp, #12 801267e: af00 add r7, sp, #0 8012680: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback could be implemented in the user file */ } 8012682: bf00 nop 8012684: 370c adds r7, #12 8012686: 46bd mov sp, r7 8012688: bc80 pop {r7} 801268a: 4770 bx lr 0801268c : * @brief UART Abort Complete callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) { 801268c: b480 push {r7} 801268e: b083 sub sp, #12 8012690: af00 add r7, sp, #0 8012692: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_AbortCpltCallback can be implemented in the user file. */ } 8012694: bf00 nop 8012696: 370c adds r7, #12 8012698: 46bd mov sp, r7 801269a: bc80 pop {r7} 801269c: 4770 bx lr 0801269e : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL state */ HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) { 801269e: b480 push {r7} 80126a0: b085 sub sp, #20 80126a2: af00 add r7, sp, #0 80126a4: 6078 str r0, [r7, #4] uint32_t temp1 = 0x00U, temp2 = 0x00U; 80126a6: 2300 movs r3, #0 80126a8: 60fb str r3, [r7, #12] 80126aa: 2300 movs r3, #0 80126ac: 60bb str r3, [r7, #8] temp1 = huart->gState; 80126ae: 687b ldr r3, [r7, #4] 80126b0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80126b4: b2db uxtb r3, r3 80126b6: 60fb str r3, [r7, #12] temp2 = huart->RxState; 80126b8: 687b ldr r3, [r7, #4] 80126ba: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 80126be: b2db uxtb r3, r3 80126c0: 60bb str r3, [r7, #8] return (HAL_UART_StateTypeDef)(temp1 | temp2); 80126c2: 68fb ldr r3, [r7, #12] 80126c4: b2da uxtb r2, r3 80126c6: 68bb ldr r3, [r7, #8] 80126c8: b2db uxtb r3, r3 80126ca: 4313 orrs r3, r2 80126cc: b2db uxtb r3, r3 } 80126ce: 4618 mov r0, r3 80126d0: 3714 adds r7, #20 80126d2: 46bd mov sp, r7 80126d4: bc80 pop {r7} 80126d6: 4770 bx lr 080126d8 : * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 80126d8: b580 push {r7, lr} 80126da: b086 sub sp, #24 80126dc: af00 add r7, sp, #0 80126de: 60f8 str r0, [r7, #12] 80126e0: 60b9 str r1, [r7, #8] 80126e2: 603b str r3, [r7, #0] 80126e4: 4613 mov r3, r2 80126e6: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 80126e8: e03b b.n 8012762 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 80126ea: 6a3b ldr r3, [r7, #32] 80126ec: f1b3 3fff cmp.w r3, #4294967295 80126f0: d037 beq.n 8012762 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 80126f2: f7fb f8ef bl 800d8d4 80126f6: 4602 mov r2, r0 80126f8: 683b ldr r3, [r7, #0] 80126fa: 1ad3 subs r3, r2, r3 80126fc: 6a3a ldr r2, [r7, #32] 80126fe: 429a cmp r2, r3 8012700: d302 bcc.n 8012708 8012702: 6a3b ldr r3, [r7, #32] 8012704: 2b00 cmp r3, #0 8012706: d101 bne.n 801270c { return HAL_TIMEOUT; 8012708: 2303 movs r3, #3 801270a: e03a b.n 8012782 } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 801270c: 68fb ldr r3, [r7, #12] 801270e: 681b ldr r3, [r3, #0] 8012710: 68db ldr r3, [r3, #12] 8012712: f003 0304 and.w r3, r3, #4 8012716: 2b00 cmp r3, #0 8012718: d023 beq.n 8012762 801271a: 68bb ldr r3, [r7, #8] 801271c: 2b80 cmp r3, #128 @ 0x80 801271e: d020 beq.n 8012762 8012720: 68bb ldr r3, [r7, #8] 8012722: 2b40 cmp r3, #64 @ 0x40 8012724: d01d beq.n 8012762 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8012726: 68fb ldr r3, [r7, #12] 8012728: 681b ldr r3, [r3, #0] 801272a: 681b ldr r3, [r3, #0] 801272c: f003 0308 and.w r3, r3, #8 8012730: 2b08 cmp r3, #8 8012732: d116 bne.n 8012762 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_OREFLAG(huart); 8012734: 2300 movs r3, #0 8012736: 617b str r3, [r7, #20] 8012738: 68fb ldr r3, [r7, #12] 801273a: 681b ldr r3, [r3, #0] 801273c: 681b ldr r3, [r3, #0] 801273e: 617b str r3, [r7, #20] 8012740: 68fb ldr r3, [r7, #12] 8012742: 681b ldr r3, [r3, #0] 8012744: 685b ldr r3, [r3, #4] 8012746: 617b str r3, [r7, #20] 8012748: 697b ldr r3, [r7, #20] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 801274a: 68f8 ldr r0, [r7, #12] 801274c: f000 f856 bl 80127fc huart->ErrorCode = HAL_UART_ERROR_ORE; 8012750: 68fb ldr r3, [r7, #12] 8012752: 2208 movs r2, #8 8012754: 645a str r2, [r3, #68] @ 0x44 /* Process Unlocked */ __HAL_UNLOCK(huart); 8012756: 68fb ldr r3, [r7, #12] 8012758: 2200 movs r2, #0 801275a: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_ERROR; 801275e: 2301 movs r3, #1 8012760: e00f b.n 8012782 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8012762: 68fb ldr r3, [r7, #12] 8012764: 681b ldr r3, [r3, #0] 8012766: 681a ldr r2, [r3, #0] 8012768: 68bb ldr r3, [r7, #8] 801276a: 4013 ands r3, r2 801276c: 68ba ldr r2, [r7, #8] 801276e: 429a cmp r2, r3 8012770: bf0c ite eq 8012772: 2301 moveq r3, #1 8012774: 2300 movne r3, #0 8012776: b2db uxtb r3, r3 8012778: 461a mov r2, r3 801277a: 79fb ldrb r3, [r7, #7] 801277c: 429a cmp r2, r3 801277e: d0b4 beq.n 80126ea } } } } return HAL_OK; 8012780: 2300 movs r3, #0 } 8012782: 4618 mov r0, r3 8012784: 3718 adds r7, #24 8012786: 46bd mov sp, r7 8012788: bd80 pop {r7, pc} 0801278a : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 801278a: b480 push {r7} 801278c: b085 sub sp, #20 801278e: af00 add r7, sp, #0 8012790: 60f8 str r0, [r7, #12] 8012792: 60b9 str r1, [r7, #8] 8012794: 4613 mov r3, r2 8012796: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 8012798: 68fb ldr r3, [r7, #12] 801279a: 68ba ldr r2, [r7, #8] 801279c: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 801279e: 68fb ldr r3, [r7, #12] 80127a0: 88fa ldrh r2, [r7, #6] 80127a2: 859a strh r2, [r3, #44] @ 0x2c huart->RxXferCount = Size; 80127a4: 68fb ldr r3, [r7, #12] 80127a6: 88fa ldrh r2, [r7, #6] 80127a8: 85da strh r2, [r3, #46] @ 0x2e huart->ErrorCode = HAL_UART_ERROR_NONE; 80127aa: 68fb ldr r3, [r7, #12] 80127ac: 2200 movs r2, #0 80127ae: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 80127b0: 68fb ldr r3, [r7, #12] 80127b2: 2222 movs r2, #34 @ 0x22 80127b4: f883 2042 strb.w r2, [r3, #66] @ 0x42 if (huart->Init.Parity != UART_PARITY_NONE) 80127b8: 68fb ldr r3, [r7, #12] 80127ba: 691b ldr r3, [r3, #16] 80127bc: 2b00 cmp r3, #0 80127be: d007 beq.n 80127d0 { /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); 80127c0: 68fb ldr r3, [r7, #12] 80127c2: 681b ldr r3, [r3, #0] 80127c4: 68da ldr r2, [r3, #12] 80127c6: 68fb ldr r3, [r7, #12] 80127c8: 681b ldr r3, [r3, #0] 80127ca: f442 7280 orr.w r2, r2, #256 @ 0x100 80127ce: 60da str r2, [r3, #12] } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); 80127d0: 68fb ldr r3, [r7, #12] 80127d2: 681b ldr r3, [r3, #0] 80127d4: 695a ldr r2, [r3, #20] 80127d6: 68fb ldr r3, [r7, #12] 80127d8: 681b ldr r3, [r3, #0] 80127da: f042 0201 orr.w r2, r2, #1 80127de: 615a str r2, [r3, #20] /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); 80127e0: 68fb ldr r3, [r7, #12] 80127e2: 681b ldr r3, [r3, #0] 80127e4: 68da ldr r2, [r3, #12] 80127e6: 68fb ldr r3, [r7, #12] 80127e8: 681b ldr r3, [r3, #0] 80127ea: f042 0220 orr.w r2, r2, #32 80127ee: 60da str r2, [r3, #12] return HAL_OK; 80127f0: 2300 movs r3, #0 } 80127f2: 4618 mov r0, r3 80127f4: 3714 adds r7, #20 80127f6: 46bd mov sp, r7 80127f8: bc80 pop {r7} 80127fa: 4770 bx lr 080127fc : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 80127fc: b480 push {r7} 80127fe: b095 sub sp, #84 @ 0x54 8012800: af00 add r7, sp, #0 8012802: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8012804: 687b ldr r3, [r7, #4] 8012806: 681b ldr r3, [r3, #0] 8012808: 330c adds r3, #12 801280a: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801280c: 6b7b ldr r3, [r7, #52] @ 0x34 801280e: e853 3f00 ldrex r3, [r3] 8012812: 633b str r3, [r7, #48] @ 0x30 return(result); 8012814: 6b3b ldr r3, [r7, #48] @ 0x30 8012816: f423 7390 bic.w r3, r3, #288 @ 0x120 801281a: 64fb str r3, [r7, #76] @ 0x4c 801281c: 687b ldr r3, [r7, #4] 801281e: 681b ldr r3, [r3, #0] 8012820: 330c adds r3, #12 8012822: 6cfa ldr r2, [r7, #76] @ 0x4c 8012824: 643a str r2, [r7, #64] @ 0x40 8012826: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012828: 6bf9 ldr r1, [r7, #60] @ 0x3c 801282a: 6c3a ldr r2, [r7, #64] @ 0x40 801282c: e841 2300 strex r3, r2, [r1] 8012830: 63bb str r3, [r7, #56] @ 0x38 return(result); 8012832: 6bbb ldr r3, [r7, #56] @ 0x38 8012834: 2b00 cmp r3, #0 8012836: d1e5 bne.n 8012804 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012838: 687b ldr r3, [r7, #4] 801283a: 681b ldr r3, [r3, #0] 801283c: 3314 adds r3, #20 801283e: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012840: 6a3b ldr r3, [r7, #32] 8012842: e853 3f00 ldrex r3, [r3] 8012846: 61fb str r3, [r7, #28] return(result); 8012848: 69fb ldr r3, [r7, #28] 801284a: f023 0301 bic.w r3, r3, #1 801284e: 64bb str r3, [r7, #72] @ 0x48 8012850: 687b ldr r3, [r7, #4] 8012852: 681b ldr r3, [r3, #0] 8012854: 3314 adds r3, #20 8012856: 6cba ldr r2, [r7, #72] @ 0x48 8012858: 62fa str r2, [r7, #44] @ 0x2c 801285a: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801285c: 6ab9 ldr r1, [r7, #40] @ 0x28 801285e: 6afa ldr r2, [r7, #44] @ 0x2c 8012860: e841 2300 strex r3, r2, [r1] 8012864: 627b str r3, [r7, #36] @ 0x24 return(result); 8012866: 6a7b ldr r3, [r7, #36] @ 0x24 8012868: 2b00 cmp r3, #0 801286a: d1e5 bne.n 8012838 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 801286c: 687b ldr r3, [r7, #4] 801286e: 6b1b ldr r3, [r3, #48] @ 0x30 8012870: 2b01 cmp r3, #1 8012872: d119 bne.n 80128a8 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012874: 687b ldr r3, [r7, #4] 8012876: 681b ldr r3, [r3, #0] 8012878: 330c adds r3, #12 801287a: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801287c: 68fb ldr r3, [r7, #12] 801287e: e853 3f00 ldrex r3, [r3] 8012882: 60bb str r3, [r7, #8] return(result); 8012884: 68bb ldr r3, [r7, #8] 8012886: f023 0310 bic.w r3, r3, #16 801288a: 647b str r3, [r7, #68] @ 0x44 801288c: 687b ldr r3, [r7, #4] 801288e: 681b ldr r3, [r3, #0] 8012890: 330c adds r3, #12 8012892: 6c7a ldr r2, [r7, #68] @ 0x44 8012894: 61ba str r2, [r7, #24] 8012896: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012898: 6979 ldr r1, [r7, #20] 801289a: 69ba ldr r2, [r7, #24] 801289c: e841 2300 strex r3, r2, [r1] 80128a0: 613b str r3, [r7, #16] return(result); 80128a2: 693b ldr r3, [r7, #16] 80128a4: 2b00 cmp r3, #0 80128a6: d1e5 bne.n 8012874 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80128a8: 687b ldr r3, [r7, #4] 80128aa: 2220 movs r2, #32 80128ac: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80128b0: 687b ldr r3, [r7, #4] 80128b2: 2200 movs r2, #0 80128b4: 631a str r2, [r3, #48] @ 0x30 } 80128b6: bf00 nop 80128b8: 3754 adds r7, #84 @ 0x54 80128ba: 46bd mov sp, r7 80128bc: bc80 pop {r7} 80128be: 4770 bx lr 080128c0 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 80128c0: b580 push {r7, lr} 80128c2: b084 sub sp, #16 80128c4: af00 add r7, sp, #0 80128c6: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80128c8: 687b ldr r3, [r7, #4] 80128ca: 6a5b ldr r3, [r3, #36] @ 0x24 80128cc: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 80128ce: 68fb ldr r3, [r7, #12] 80128d0: 2200 movs r2, #0 80128d2: 85da strh r2, [r3, #46] @ 0x2e huart->TxXferCount = 0x00U; 80128d4: 68fb ldr r3, [r7, #12] 80128d6: 2200 movs r2, #0 80128d8: 84da strh r2, [r3, #38] @ 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80128da: 68f8 ldr r0, [r7, #12] 80128dc: f7ff fecd bl 801267a #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80128e0: bf00 nop 80128e2: 3710 adds r7, #16 80128e4: 46bd mov sp, r7 80128e6: bd80 pop {r7, pc} 080128e8 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { 80128e8: b580 push {r7, lr} 80128ea: b084 sub sp, #16 80128ec: af00 add r7, sp, #0 80128ee: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80128f0: 687b ldr r3, [r7, #4] 80128f2: 6a5b ldr r3, [r3, #36] @ 0x24 80128f4: 60fb str r3, [r7, #12] huart->hdmatx->XferAbortCallback = NULL; 80128f6: 68fb ldr r3, [r7, #12] 80128f8: 6b9b ldr r3, [r3, #56] @ 0x38 80128fa: 2200 movs r2, #0 80128fc: 635a str r2, [r3, #52] @ 0x34 /* Check if an Abort process is still ongoing */ if (huart->hdmarx != NULL) 80128fe: 68fb ldr r3, [r7, #12] 8012900: 6bdb ldr r3, [r3, #60] @ 0x3c 8012902: 2b00 cmp r3, #0 8012904: d004 beq.n 8012910 { if (huart->hdmarx->XferAbortCallback != NULL) 8012906: 68fb ldr r3, [r7, #12] 8012908: 6bdb ldr r3, [r3, #60] @ 0x3c 801290a: 6b5b ldr r3, [r3, #52] @ 0x34 801290c: 2b00 cmp r3, #0 801290e: d117 bne.n 8012940 return; } } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ huart->TxXferCount = 0x00U; 8012910: 68fb ldr r3, [r7, #12] 8012912: 2200 movs r2, #0 8012914: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 8012916: 68fb ldr r3, [r7, #12] 8012918: 2200 movs r2, #0 801291a: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 801291c: 68fb ldr r3, [r7, #12] 801291e: 2200 movs r2, #0 8012920: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 8012922: 68fb ldr r3, [r7, #12] 8012924: 2220 movs r2, #32 8012926: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 801292a: 68fb ldr r3, [r7, #12] 801292c: 2220 movs r2, #32 801292e: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012932: 68fb ldr r3, [r7, #12] 8012934: 2200 movs r2, #0 8012936: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 8012938: 68f8 ldr r0, [r7, #12] 801293a: f7ff fea7 bl 801268c 801293e: e000 b.n 8012942 return; 8012940: bf00 nop #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8012942: 3710 adds r7, #16 8012944: 46bd mov sp, r7 8012946: bd80 pop {r7, pc} 08012948 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { 8012948: b580 push {r7, lr} 801294a: b084 sub sp, #16 801294c: af00 add r7, sp, #0 801294e: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8012950: 687b ldr r3, [r7, #4] 8012952: 6a5b ldr r3, [r3, #36] @ 0x24 8012954: 60fb str r3, [r7, #12] huart->hdmarx->XferAbortCallback = NULL; 8012956: 68fb ldr r3, [r7, #12] 8012958: 6bdb ldr r3, [r3, #60] @ 0x3c 801295a: 2200 movs r2, #0 801295c: 635a str r2, [r3, #52] @ 0x34 /* Check if an Abort process is still ongoing */ if (huart->hdmatx != NULL) 801295e: 68fb ldr r3, [r7, #12] 8012960: 6b9b ldr r3, [r3, #56] @ 0x38 8012962: 2b00 cmp r3, #0 8012964: d004 beq.n 8012970 { if (huart->hdmatx->XferAbortCallback != NULL) 8012966: 68fb ldr r3, [r7, #12] 8012968: 6b9b ldr r3, [r3, #56] @ 0x38 801296a: 6b5b ldr r3, [r3, #52] @ 0x34 801296c: 2b00 cmp r3, #0 801296e: d117 bne.n 80129a0 return; } } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ huart->TxXferCount = 0x00U; 8012970: 68fb ldr r3, [r7, #12] 8012972: 2200 movs r2, #0 8012974: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 8012976: 68fb ldr r3, [r7, #12] 8012978: 2200 movs r2, #0 801297a: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 801297c: 68fb ldr r3, [r7, #12] 801297e: 2200 movs r2, #0 8012980: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 8012982: 68fb ldr r3, [r7, #12] 8012984: 2220 movs r2, #32 8012986: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 801298a: 68fb ldr r3, [r7, #12] 801298c: 2220 movs r2, #32 801298e: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012992: 68fb ldr r3, [r7, #12] 8012994: 2200 movs r2, #0 8012996: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 8012998: 68f8 ldr r0, [r7, #12] 801299a: f7ff fe77 bl 801268c 801299e: e000 b.n 80129a2 return; 80129a0: bf00 nop #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80129a2: 3710 adds r7, #16 80129a4: 46bd mov sp, r7 80129a6: bd80 pop {r7, pc} 080129a8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 80129a8: b480 push {r7} 80129aa: b085 sub sp, #20 80129ac: af00 add r7, sp, #0 80129ae: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 80129b0: 687b ldr r3, [r7, #4] 80129b2: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80129b6: b2db uxtb r3, r3 80129b8: 2b21 cmp r3, #33 @ 0x21 80129ba: d13e bne.n 8012a3a { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80129bc: 687b ldr r3, [r7, #4] 80129be: 689b ldr r3, [r3, #8] 80129c0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80129c4: d114 bne.n 80129f0 80129c6: 687b ldr r3, [r7, #4] 80129c8: 691b ldr r3, [r3, #16] 80129ca: 2b00 cmp r3, #0 80129cc: d110 bne.n 80129f0 { tmp = (const uint16_t *) huart->pTxBuffPtr; 80129ce: 687b ldr r3, [r7, #4] 80129d0: 6a1b ldr r3, [r3, #32] 80129d2: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 80129d4: 68fb ldr r3, [r7, #12] 80129d6: 881b ldrh r3, [r3, #0] 80129d8: 461a mov r2, r3 80129da: 687b ldr r3, [r7, #4] 80129dc: 681b ldr r3, [r3, #0] 80129de: f3c2 0208 ubfx r2, r2, #0, #9 80129e2: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 80129e4: 687b ldr r3, [r7, #4] 80129e6: 6a1b ldr r3, [r3, #32] 80129e8: 1c9a adds r2, r3, #2 80129ea: 687b ldr r3, [r7, #4] 80129ec: 621a str r2, [r3, #32] 80129ee: e008 b.n 8012a02 } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 80129f0: 687b ldr r3, [r7, #4] 80129f2: 6a1b ldr r3, [r3, #32] 80129f4: 1c59 adds r1, r3, #1 80129f6: 687a ldr r2, [r7, #4] 80129f8: 6211 str r1, [r2, #32] 80129fa: 781a ldrb r2, [r3, #0] 80129fc: 687b ldr r3, [r7, #4] 80129fe: 681b ldr r3, [r3, #0] 8012a00: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 8012a02: 687b ldr r3, [r7, #4] 8012a04: 8cdb ldrh r3, [r3, #38] @ 0x26 8012a06: b29b uxth r3, r3 8012a08: 3b01 subs r3, #1 8012a0a: b29b uxth r3, r3 8012a0c: 687a ldr r2, [r7, #4] 8012a0e: 4619 mov r1, r3 8012a10: 84d1 strh r1, [r2, #38] @ 0x26 8012a12: 2b00 cmp r3, #0 8012a14: d10f bne.n 8012a36 { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8012a16: 687b ldr r3, [r7, #4] 8012a18: 681b ldr r3, [r3, #0] 8012a1a: 68da ldr r2, [r3, #12] 8012a1c: 687b ldr r3, [r7, #4] 8012a1e: 681b ldr r3, [r3, #0] 8012a20: f022 0280 bic.w r2, r2, #128 @ 0x80 8012a24: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8012a26: 687b ldr r3, [r7, #4] 8012a28: 681b ldr r3, [r3, #0] 8012a2a: 68da ldr r2, [r3, #12] 8012a2c: 687b ldr r3, [r7, #4] 8012a2e: 681b ldr r3, [r3, #0] 8012a30: f042 0240 orr.w r2, r2, #64 @ 0x40 8012a34: 60da str r2, [r3, #12] } return HAL_OK; 8012a36: 2300 movs r3, #0 8012a38: e000 b.n 8012a3c } else { return HAL_BUSY; 8012a3a: 2302 movs r3, #2 } } 8012a3c: 4618 mov r0, r3 8012a3e: 3714 adds r7, #20 8012a40: 46bd mov sp, r7 8012a42: bc80 pop {r7} 8012a44: 4770 bx lr 08012a46 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8012a46: b580 push {r7, lr} 8012a48: b082 sub sp, #8 8012a4a: af00 add r7, sp, #0 8012a4c: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 8012a4e: 687b ldr r3, [r7, #4] 8012a50: 681b ldr r3, [r3, #0] 8012a52: 68da ldr r2, [r3, #12] 8012a54: 687b ldr r3, [r7, #4] 8012a56: 681b ldr r3, [r3, #0] 8012a58: f022 0240 bic.w r2, r2, #64 @ 0x40 8012a5c: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8012a5e: 687b ldr r3, [r7, #4] 8012a60: 2220 movs r2, #32 8012a62: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8012a66: 6878 ldr r0, [r7, #4] 8012a68: f7f9 fdbc bl 800c5e4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8012a6c: 2300 movs r3, #0 } 8012a6e: 4618 mov r0, r3 8012a70: 3708 adds r7, #8 8012a72: 46bd mov sp, r7 8012a74: bd80 pop {r7, pc} 08012a76 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 8012a76: b580 push {r7, lr} 8012a78: b08c sub sp, #48 @ 0x30 8012a7a: af00 add r7, sp, #0 8012a7c: 6078 str r0, [r7, #4] uint8_t *pdata8bits; uint16_t *pdata16bits; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8012a7e: 687b ldr r3, [r7, #4] 8012a80: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8012a84: b2db uxtb r3, r3 8012a86: 2b22 cmp r3, #34 @ 0x22 8012a88: f040 80ae bne.w 8012be8 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012a8c: 687b ldr r3, [r7, #4] 8012a8e: 689b ldr r3, [r3, #8] 8012a90: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012a94: d117 bne.n 8012ac6 8012a96: 687b ldr r3, [r7, #4] 8012a98: 691b ldr r3, [r3, #16] 8012a9a: 2b00 cmp r3, #0 8012a9c: d113 bne.n 8012ac6 { pdata8bits = NULL; 8012a9e: 2300 movs r3, #0 8012aa0: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = (uint16_t *) huart->pRxBuffPtr; 8012aa2: 687b ldr r3, [r7, #4] 8012aa4: 6a9b ldr r3, [r3, #40] @ 0x28 8012aa6: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8012aa8: 687b ldr r3, [r7, #4] 8012aaa: 681b ldr r3, [r3, #0] 8012aac: 685b ldr r3, [r3, #4] 8012aae: b29b uxth r3, r3 8012ab0: f3c3 0308 ubfx r3, r3, #0, #9 8012ab4: b29a uxth r2, r3 8012ab6: 6abb ldr r3, [r7, #40] @ 0x28 8012ab8: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8012aba: 687b ldr r3, [r7, #4] 8012abc: 6a9b ldr r3, [r3, #40] @ 0x28 8012abe: 1c9a adds r2, r3, #2 8012ac0: 687b ldr r3, [r7, #4] 8012ac2: 629a str r2, [r3, #40] @ 0x28 8012ac4: e026 b.n 8012b14 } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8012ac6: 687b ldr r3, [r7, #4] 8012ac8: 6a9b ldr r3, [r3, #40] @ 0x28 8012aca: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = NULL; 8012acc: 2300 movs r3, #0 8012ace: 62bb str r3, [r7, #40] @ 0x28 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 8012ad0: 687b ldr r3, [r7, #4] 8012ad2: 689b ldr r3, [r3, #8] 8012ad4: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012ad8: d007 beq.n 8012aea 8012ada: 687b ldr r3, [r7, #4] 8012adc: 689b ldr r3, [r3, #8] 8012ade: 2b00 cmp r3, #0 8012ae0: d10a bne.n 8012af8 8012ae2: 687b ldr r3, [r7, #4] 8012ae4: 691b ldr r3, [r3, #16] 8012ae6: 2b00 cmp r3, #0 8012ae8: d106 bne.n 8012af8 { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8012aea: 687b ldr r3, [r7, #4] 8012aec: 681b ldr r3, [r3, #0] 8012aee: 685b ldr r3, [r3, #4] 8012af0: b2da uxtb r2, r3 8012af2: 6afb ldr r3, [r7, #44] @ 0x2c 8012af4: 701a strb r2, [r3, #0] 8012af6: e008 b.n 8012b0a } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8012af8: 687b ldr r3, [r7, #4] 8012afa: 681b ldr r3, [r3, #0] 8012afc: 685b ldr r3, [r3, #4] 8012afe: b2db uxtb r3, r3 8012b00: f003 037f and.w r3, r3, #127 @ 0x7f 8012b04: b2da uxtb r2, r3 8012b06: 6afb ldr r3, [r7, #44] @ 0x2c 8012b08: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8012b0a: 687b ldr r3, [r7, #4] 8012b0c: 6a9b ldr r3, [r3, #40] @ 0x28 8012b0e: 1c5a adds r2, r3, #1 8012b10: 687b ldr r3, [r7, #4] 8012b12: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 8012b14: 687b ldr r3, [r7, #4] 8012b16: 8ddb ldrh r3, [r3, #46] @ 0x2e 8012b18: b29b uxth r3, r3 8012b1a: 3b01 subs r3, #1 8012b1c: b29b uxth r3, r3 8012b1e: 687a ldr r2, [r7, #4] 8012b20: 4619 mov r1, r3 8012b22: 85d1 strh r1, [r2, #46] @ 0x2e 8012b24: 2b00 cmp r3, #0 8012b26: d15d bne.n 8012be4 { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8012b28: 687b ldr r3, [r7, #4] 8012b2a: 681b ldr r3, [r3, #0] 8012b2c: 68da ldr r2, [r3, #12] 8012b2e: 687b ldr r3, [r7, #4] 8012b30: 681b ldr r3, [r3, #0] 8012b32: f022 0220 bic.w r2, r2, #32 8012b36: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8012b38: 687b ldr r3, [r7, #4] 8012b3a: 681b ldr r3, [r3, #0] 8012b3c: 68da ldr r2, [r3, #12] 8012b3e: 687b ldr r3, [r7, #4] 8012b40: 681b ldr r3, [r3, #0] 8012b42: f422 7280 bic.w r2, r2, #256 @ 0x100 8012b46: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8012b48: 687b ldr r3, [r7, #4] 8012b4a: 681b ldr r3, [r3, #0] 8012b4c: 695a ldr r2, [r3, #20] 8012b4e: 687b ldr r3, [r7, #4] 8012b50: 681b ldr r3, [r3, #0] 8012b52: f022 0201 bic.w r2, r2, #1 8012b56: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012b58: 687b ldr r3, [r7, #4] 8012b5a: 2220 movs r2, #32 8012b5c: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8012b60: 687b ldr r3, [r7, #4] 8012b62: 2200 movs r2, #0 8012b64: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012b66: 687b ldr r3, [r7, #4] 8012b68: 6b1b ldr r3, [r3, #48] @ 0x30 8012b6a: 2b01 cmp r3, #1 8012b6c: d135 bne.n 8012bda { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012b6e: 687b ldr r3, [r7, #4] 8012b70: 2200 movs r2, #0 8012b72: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012b74: 687b ldr r3, [r7, #4] 8012b76: 681b ldr r3, [r3, #0] 8012b78: 330c adds r3, #12 8012b7a: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012b7c: 697b ldr r3, [r7, #20] 8012b7e: e853 3f00 ldrex r3, [r3] 8012b82: 613b str r3, [r7, #16] return(result); 8012b84: 693b ldr r3, [r7, #16] 8012b86: f023 0310 bic.w r3, r3, #16 8012b8a: 627b str r3, [r7, #36] @ 0x24 8012b8c: 687b ldr r3, [r7, #4] 8012b8e: 681b ldr r3, [r3, #0] 8012b90: 330c adds r3, #12 8012b92: 6a7a ldr r2, [r7, #36] @ 0x24 8012b94: 623a str r2, [r7, #32] 8012b96: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012b98: 69f9 ldr r1, [r7, #28] 8012b9a: 6a3a ldr r2, [r7, #32] 8012b9c: e841 2300 strex r3, r2, [r1] 8012ba0: 61bb str r3, [r7, #24] return(result); 8012ba2: 69bb ldr r3, [r7, #24] 8012ba4: 2b00 cmp r3, #0 8012ba6: d1e5 bne.n 8012b74 /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 8012ba8: 687b ldr r3, [r7, #4] 8012baa: 681b ldr r3, [r3, #0] 8012bac: 681b ldr r3, [r3, #0] 8012bae: f003 0310 and.w r3, r3, #16 8012bb2: 2b10 cmp r3, #16 8012bb4: d10a bne.n 8012bcc { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 8012bb6: 2300 movs r3, #0 8012bb8: 60fb str r3, [r7, #12] 8012bba: 687b ldr r3, [r7, #4] 8012bbc: 681b ldr r3, [r3, #0] 8012bbe: 681b ldr r3, [r3, #0] 8012bc0: 60fb str r3, [r7, #12] 8012bc2: 687b ldr r3, [r7, #4] 8012bc4: 681b ldr r3, [r3, #0] 8012bc6: 685b ldr r3, [r3, #4] 8012bc8: 60fb str r3, [r7, #12] 8012bca: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8012bcc: 687b ldr r3, [r7, #4] 8012bce: 8d9b ldrh r3, [r3, #44] @ 0x2c 8012bd0: 4619 mov r1, r3 8012bd2: 6878 ldr r0, [r7, #4] 8012bd4: f7f9 fca6 bl 800c524 8012bd8: e002 b.n 8012be0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8012bda: 6878 ldr r0, [r7, #4] 8012bdc: f7ff fd44 bl 8012668 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8012be0: 2300 movs r3, #0 8012be2: e002 b.n 8012bea } return HAL_OK; 8012be4: 2300 movs r3, #0 8012be6: e000 b.n 8012bea } else { return HAL_BUSY; 8012be8: 2302 movs r3, #2 } } 8012bea: 4618 mov r0, r3 8012bec: 3730 adds r7, #48 @ 0x30 8012bee: 46bd mov sp, r7 8012bf0: bd80 pop {r7, pc} ... 08012bf4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8012bf4: b580 push {r7, lr} 8012bf6: b084 sub sp, #16 8012bf8: af00 add r7, sp, #0 8012bfa: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8012bfc: 687b ldr r3, [r7, #4] 8012bfe: 681b ldr r3, [r3, #0] 8012c00: 691b ldr r3, [r3, #16] 8012c02: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8012c06: 687b ldr r3, [r7, #4] 8012c08: 68da ldr r2, [r3, #12] 8012c0a: 687b ldr r3, [r7, #4] 8012c0c: 681b ldr r3, [r3, #0] 8012c0e: 430a orrs r2, r1 8012c10: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 8012c12: 687b ldr r3, [r7, #4] 8012c14: 689a ldr r2, [r3, #8] 8012c16: 687b ldr r3, [r7, #4] 8012c18: 691b ldr r3, [r3, #16] 8012c1a: 431a orrs r2, r3 8012c1c: 687b ldr r3, [r7, #4] 8012c1e: 695b ldr r3, [r3, #20] 8012c20: 4313 orrs r3, r2 8012c22: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 8012c24: 687b ldr r3, [r7, #4] 8012c26: 681b ldr r3, [r3, #0] 8012c28: 68db ldr r3, [r3, #12] 8012c2a: f423 53b0 bic.w r3, r3, #5632 @ 0x1600 8012c2e: f023 030c bic.w r3, r3, #12 8012c32: 687a ldr r2, [r7, #4] 8012c34: 6812 ldr r2, [r2, #0] 8012c36: 68b9 ldr r1, [r7, #8] 8012c38: 430b orrs r3, r1 8012c3a: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8012c3c: 687b ldr r3, [r7, #4] 8012c3e: 681b ldr r3, [r3, #0] 8012c40: 695b ldr r3, [r3, #20] 8012c42: f423 7140 bic.w r1, r3, #768 @ 0x300 8012c46: 687b ldr r3, [r7, #4] 8012c48: 699a ldr r2, [r3, #24] 8012c4a: 687b ldr r3, [r7, #4] 8012c4c: 681b ldr r3, [r3, #0] 8012c4e: 430a orrs r2, r1 8012c50: 615a str r2, [r3, #20] if(huart->Instance == USART1) 8012c52: 687b ldr r3, [r7, #4] 8012c54: 681b ldr r3, [r3, #0] 8012c56: 4a2c ldr r2, [pc, #176] @ (8012d08 ) 8012c58: 4293 cmp r3, r2 8012c5a: d103 bne.n 8012c64 { pclk = HAL_RCC_GetPCLK2Freq(); 8012c5c: f7fd fc1a bl 8010494 8012c60: 60f8 str r0, [r7, #12] 8012c62: e002 b.n 8012c6a } else { pclk = HAL_RCC_GetPCLK1Freq(); 8012c64: f7fd fc02 bl 801046c 8012c68: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8012c6a: 68fa ldr r2, [r7, #12] 8012c6c: 4613 mov r3, r2 8012c6e: 009b lsls r3, r3, #2 8012c70: 4413 add r3, r2 8012c72: 009a lsls r2, r3, #2 8012c74: 441a add r2, r3 8012c76: 687b ldr r3, [r7, #4] 8012c78: 685b ldr r3, [r3, #4] 8012c7a: 009b lsls r3, r3, #2 8012c7c: fbb2 f3f3 udiv r3, r2, r3 8012c80: 4a22 ldr r2, [pc, #136] @ (8012d0c ) 8012c82: fba2 2303 umull r2, r3, r2, r3 8012c86: 095b lsrs r3, r3, #5 8012c88: 0119 lsls r1, r3, #4 8012c8a: 68fa ldr r2, [r7, #12] 8012c8c: 4613 mov r3, r2 8012c8e: 009b lsls r3, r3, #2 8012c90: 4413 add r3, r2 8012c92: 009a lsls r2, r3, #2 8012c94: 441a add r2, r3 8012c96: 687b ldr r3, [r7, #4] 8012c98: 685b ldr r3, [r3, #4] 8012c9a: 009b lsls r3, r3, #2 8012c9c: fbb2 f2f3 udiv r2, r2, r3 8012ca0: 4b1a ldr r3, [pc, #104] @ (8012d0c ) 8012ca2: fba3 0302 umull r0, r3, r3, r2 8012ca6: 095b lsrs r3, r3, #5 8012ca8: 2064 movs r0, #100 @ 0x64 8012caa: fb00 f303 mul.w r3, r0, r3 8012cae: 1ad3 subs r3, r2, r3 8012cb0: 011b lsls r3, r3, #4 8012cb2: 3332 adds r3, #50 @ 0x32 8012cb4: 4a15 ldr r2, [pc, #84] @ (8012d0c ) 8012cb6: fba2 2303 umull r2, r3, r2, r3 8012cba: 095b lsrs r3, r3, #5 8012cbc: f003 03f0 and.w r3, r3, #240 @ 0xf0 8012cc0: 4419 add r1, r3 8012cc2: 68fa ldr r2, [r7, #12] 8012cc4: 4613 mov r3, r2 8012cc6: 009b lsls r3, r3, #2 8012cc8: 4413 add r3, r2 8012cca: 009a lsls r2, r3, #2 8012ccc: 441a add r2, r3 8012cce: 687b ldr r3, [r7, #4] 8012cd0: 685b ldr r3, [r3, #4] 8012cd2: 009b lsls r3, r3, #2 8012cd4: fbb2 f2f3 udiv r2, r2, r3 8012cd8: 4b0c ldr r3, [pc, #48] @ (8012d0c ) 8012cda: fba3 0302 umull r0, r3, r3, r2 8012cde: 095b lsrs r3, r3, #5 8012ce0: 2064 movs r0, #100 @ 0x64 8012ce2: fb00 f303 mul.w r3, r0, r3 8012ce6: 1ad3 subs r3, r2, r3 8012ce8: 011b lsls r3, r3, #4 8012cea: 3332 adds r3, #50 @ 0x32 8012cec: 4a07 ldr r2, [pc, #28] @ (8012d0c ) 8012cee: fba2 2303 umull r2, r3, r2, r3 8012cf2: 095b lsrs r3, r3, #5 8012cf4: f003 020f and.w r2, r3, #15 8012cf8: 687b ldr r3, [r7, #4] 8012cfa: 681b ldr r3, [r3, #0] 8012cfc: 440a add r2, r1 8012cfe: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 8012d00: bf00 nop 8012d02: 3710 adds r7, #16 8012d04: 46bd mov sp, r7 8012d06: bd80 pop {r7, pc} 8012d08: 40013800 .word 0x40013800 8012d0c: 51eb851f .word 0x51eb851f 08012d10 : 8012d10: 2300 movs r3, #0 8012d12: b510 push {r4, lr} 8012d14: 4604 mov r4, r0 8012d16: e9c0 3300 strd r3, r3, [r0] 8012d1a: e9c0 3304 strd r3, r3, [r0, #16] 8012d1e: 6083 str r3, [r0, #8] 8012d20: 8181 strh r1, [r0, #12] 8012d22: 6643 str r3, [r0, #100] @ 0x64 8012d24: 81c2 strh r2, [r0, #14] 8012d26: 6183 str r3, [r0, #24] 8012d28: 4619 mov r1, r3 8012d2a: 2208 movs r2, #8 8012d2c: 305c adds r0, #92 @ 0x5c 8012d2e: f000 f943 bl 8012fb8 8012d32: 4b0d ldr r3, [pc, #52] @ (8012d68 ) 8012d34: 6224 str r4, [r4, #32] 8012d36: 6263 str r3, [r4, #36] @ 0x24 8012d38: 4b0c ldr r3, [pc, #48] @ (8012d6c ) 8012d3a: 62a3 str r3, [r4, #40] @ 0x28 8012d3c: 4b0c ldr r3, [pc, #48] @ (8012d70 ) 8012d3e: 62e3 str r3, [r4, #44] @ 0x2c 8012d40: 4b0c ldr r3, [pc, #48] @ (8012d74 ) 8012d42: 6323 str r3, [r4, #48] @ 0x30 8012d44: 4b0c ldr r3, [pc, #48] @ (8012d78 ) 8012d46: 429c cmp r4, r3 8012d48: d006 beq.n 8012d58 8012d4a: f103 0268 add.w r2, r3, #104 @ 0x68 8012d4e: 4294 cmp r4, r2 8012d50: d002 beq.n 8012d58 8012d52: 33d0 adds r3, #208 @ 0xd0 8012d54: 429c cmp r4, r3 8012d56: d105 bne.n 8012d64 8012d58: f104 0058 add.w r0, r4, #88 @ 0x58 8012d5c: e8bd 4010 ldmia.w sp!, {r4, lr} 8012d60: f000 b9a2 b.w 80130a8 <__retarget_lock_init_recursive> 8012d64: bd10 pop {r4, pc} 8012d66: bf00 nop 8012d68: 08012eb9 .word 0x08012eb9 8012d6c: 08012edb .word 0x08012edb 8012d70: 08012f13 .word 0x08012f13 8012d74: 08012f37 .word 0x08012f37 8012d78: 20001074 .word 0x20001074 08012d7c : 8012d7c: 4a02 ldr r2, [pc, #8] @ (8012d88 ) 8012d7e: 4903 ldr r1, [pc, #12] @ (8012d8c ) 8012d80: 4803 ldr r0, [pc, #12] @ (8012d90 ) 8012d82: f000 b869 b.w 8012e58 <_fwalk_sglue> 8012d86: bf00 nop 8012d88: 20000078 .word 0x20000078 8012d8c: 08013c09 .word 0x08013c09 8012d90: 20000088 .word 0x20000088 08012d94 : 8012d94: 6841 ldr r1, [r0, #4] 8012d96: 4b0c ldr r3, [pc, #48] @ (8012dc8 ) 8012d98: b510 push {r4, lr} 8012d9a: 4299 cmp r1, r3 8012d9c: 4604 mov r4, r0 8012d9e: d001 beq.n 8012da4 8012da0: f000 ff32 bl 8013c08 <_fflush_r> 8012da4: 68a1 ldr r1, [r4, #8] 8012da6: 4b09 ldr r3, [pc, #36] @ (8012dcc ) 8012da8: 4299 cmp r1, r3 8012daa: d002 beq.n 8012db2 8012dac: 4620 mov r0, r4 8012dae: f000 ff2b bl 8013c08 <_fflush_r> 8012db2: 68e1 ldr r1, [r4, #12] 8012db4: 4b06 ldr r3, [pc, #24] @ (8012dd0 ) 8012db6: 4299 cmp r1, r3 8012db8: d004 beq.n 8012dc4 8012dba: 4620 mov r0, r4 8012dbc: e8bd 4010 ldmia.w sp!, {r4, lr} 8012dc0: f000 bf22 b.w 8013c08 <_fflush_r> 8012dc4: bd10 pop {r4, pc} 8012dc6: bf00 nop 8012dc8: 20001074 .word 0x20001074 8012dcc: 200010dc .word 0x200010dc 8012dd0: 20001144 .word 0x20001144 08012dd4 : 8012dd4: b510 push {r4, lr} 8012dd6: 4b0b ldr r3, [pc, #44] @ (8012e04 ) 8012dd8: 4c0b ldr r4, [pc, #44] @ (8012e08 ) 8012dda: 4a0c ldr r2, [pc, #48] @ (8012e0c ) 8012ddc: 4620 mov r0, r4 8012dde: 601a str r2, [r3, #0] 8012de0: 2104 movs r1, #4 8012de2: 2200 movs r2, #0 8012de4: f7ff ff94 bl 8012d10 8012de8: f104 0068 add.w r0, r4, #104 @ 0x68 8012dec: 2201 movs r2, #1 8012dee: 2109 movs r1, #9 8012df0: f7ff ff8e bl 8012d10 8012df4: f104 00d0 add.w r0, r4, #208 @ 0xd0 8012df8: 2202 movs r2, #2 8012dfa: e8bd 4010 ldmia.w sp!, {r4, lr} 8012dfe: 2112 movs r1, #18 8012e00: f7ff bf86 b.w 8012d10 8012e04: 200011ac .word 0x200011ac 8012e08: 20001074 .word 0x20001074 8012e0c: 08012d7d .word 0x08012d7d 08012e10 <__sfp_lock_acquire>: 8012e10: 4801 ldr r0, [pc, #4] @ (8012e18 <__sfp_lock_acquire+0x8>) 8012e12: f000 b94a b.w 80130aa <__retarget_lock_acquire_recursive> 8012e16: bf00 nop 8012e18: 200011b5 .word 0x200011b5 08012e1c <__sfp_lock_release>: 8012e1c: 4801 ldr r0, [pc, #4] @ (8012e24 <__sfp_lock_release+0x8>) 8012e1e: f000 b945 b.w 80130ac <__retarget_lock_release_recursive> 8012e22: bf00 nop 8012e24: 200011b5 .word 0x200011b5 08012e28 <__sinit>: 8012e28: b510 push {r4, lr} 8012e2a: 4604 mov r4, r0 8012e2c: f7ff fff0 bl 8012e10 <__sfp_lock_acquire> 8012e30: 6a23 ldr r3, [r4, #32] 8012e32: b11b cbz r3, 8012e3c <__sinit+0x14> 8012e34: e8bd 4010 ldmia.w sp!, {r4, lr} 8012e38: f7ff bff0 b.w 8012e1c <__sfp_lock_release> 8012e3c: 4b04 ldr r3, [pc, #16] @ (8012e50 <__sinit+0x28>) 8012e3e: 6223 str r3, [r4, #32] 8012e40: 4b04 ldr r3, [pc, #16] @ (8012e54 <__sinit+0x2c>) 8012e42: 681b ldr r3, [r3, #0] 8012e44: 2b00 cmp r3, #0 8012e46: d1f5 bne.n 8012e34 <__sinit+0xc> 8012e48: f7ff ffc4 bl 8012dd4 8012e4c: e7f2 b.n 8012e34 <__sinit+0xc> 8012e4e: bf00 nop 8012e50: 08012d95 .word 0x08012d95 8012e54: 200011ac .word 0x200011ac 08012e58 <_fwalk_sglue>: 8012e58: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8012e5c: 4607 mov r7, r0 8012e5e: 4688 mov r8, r1 8012e60: 4614 mov r4, r2 8012e62: 2600 movs r6, #0 8012e64: e9d4 9501 ldrd r9, r5, [r4, #4] 8012e68: f1b9 0901 subs.w r9, r9, #1 8012e6c: d505 bpl.n 8012e7a <_fwalk_sglue+0x22> 8012e6e: 6824 ldr r4, [r4, #0] 8012e70: 2c00 cmp r4, #0 8012e72: d1f7 bne.n 8012e64 <_fwalk_sglue+0xc> 8012e74: 4630 mov r0, r6 8012e76: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8012e7a: 89ab ldrh r3, [r5, #12] 8012e7c: 2b01 cmp r3, #1 8012e7e: d907 bls.n 8012e90 <_fwalk_sglue+0x38> 8012e80: f9b5 300e ldrsh.w r3, [r5, #14] 8012e84: 3301 adds r3, #1 8012e86: d003 beq.n 8012e90 <_fwalk_sglue+0x38> 8012e88: 4629 mov r1, r5 8012e8a: 4638 mov r0, r7 8012e8c: 47c0 blx r8 8012e8e: 4306 orrs r6, r0 8012e90: 3568 adds r5, #104 @ 0x68 8012e92: e7e9 b.n 8012e68 <_fwalk_sglue+0x10> 08012e94 : 8012e94: b40f push {r0, r1, r2, r3} 8012e96: b507 push {r0, r1, r2, lr} 8012e98: 4906 ldr r1, [pc, #24] @ (8012eb4 ) 8012e9a: ab04 add r3, sp, #16 8012e9c: 6808 ldr r0, [r1, #0] 8012e9e: f853 2b04 ldr.w r2, [r3], #4 8012ea2: 6881 ldr r1, [r0, #8] 8012ea4: 9301 str r3, [sp, #4] 8012ea6: f000 fb87 bl 80135b8 <_vfiprintf_r> 8012eaa: b003 add sp, #12 8012eac: f85d eb04 ldr.w lr, [sp], #4 8012eb0: b004 add sp, #16 8012eb2: 4770 bx lr 8012eb4: 20000084 .word 0x20000084 08012eb8 <__sread>: 8012eb8: b510 push {r4, lr} 8012eba: 460c mov r4, r1 8012ebc: f9b1 100e ldrsh.w r1, [r1, #14] 8012ec0: f000 f8a4 bl 801300c <_read_r> 8012ec4: 2800 cmp r0, #0 8012ec6: bfab itete ge 8012ec8: 6d63 ldrge r3, [r4, #84] @ 0x54 8012eca: 89a3 ldrhlt r3, [r4, #12] 8012ecc: 181b addge r3, r3, r0 8012ece: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 8012ed2: bfac ite ge 8012ed4: 6563 strge r3, [r4, #84] @ 0x54 8012ed6: 81a3 strhlt r3, [r4, #12] 8012ed8: bd10 pop {r4, pc} 08012eda <__swrite>: 8012eda: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8012ede: 461f mov r7, r3 8012ee0: 898b ldrh r3, [r1, #12] 8012ee2: 4605 mov r5, r0 8012ee4: 05db lsls r3, r3, #23 8012ee6: 460c mov r4, r1 8012ee8: 4616 mov r6, r2 8012eea: d505 bpl.n 8012ef8 <__swrite+0x1e> 8012eec: 2302 movs r3, #2 8012eee: 2200 movs r2, #0 8012ef0: f9b1 100e ldrsh.w r1, [r1, #14] 8012ef4: f000 f878 bl 8012fe8 <_lseek_r> 8012ef8: 89a3 ldrh r3, [r4, #12] 8012efa: 4632 mov r2, r6 8012efc: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8012f00: 81a3 strh r3, [r4, #12] 8012f02: 4628 mov r0, r5 8012f04: 463b mov r3, r7 8012f06: f9b4 100e ldrsh.w r1, [r4, #14] 8012f0a: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8012f0e: f000 b88f b.w 8013030 <_write_r> 08012f12 <__sseek>: 8012f12: b510 push {r4, lr} 8012f14: 460c mov r4, r1 8012f16: f9b1 100e ldrsh.w r1, [r1, #14] 8012f1a: f000 f865 bl 8012fe8 <_lseek_r> 8012f1e: 1c43 adds r3, r0, #1 8012f20: 89a3 ldrh r3, [r4, #12] 8012f22: bf15 itete ne 8012f24: 6560 strne r0, [r4, #84] @ 0x54 8012f26: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 8012f2a: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 8012f2e: 81a3 strheq r3, [r4, #12] 8012f30: bf18 it ne 8012f32: 81a3 strhne r3, [r4, #12] 8012f34: bd10 pop {r4, pc} 08012f36 <__sclose>: 8012f36: f9b1 100e ldrsh.w r1, [r1, #14] 8012f3a: f000 b845 b.w 8012fc8 <_close_r> 08012f3e <_vsniprintf_r>: 8012f3e: b530 push {r4, r5, lr} 8012f40: 4614 mov r4, r2 8012f42: 2c00 cmp r4, #0 8012f44: 4605 mov r5, r0 8012f46: 461a mov r2, r3 8012f48: b09b sub sp, #108 @ 0x6c 8012f4a: da05 bge.n 8012f58 <_vsniprintf_r+0x1a> 8012f4c: 238b movs r3, #139 @ 0x8b 8012f4e: 6003 str r3, [r0, #0] 8012f50: f04f 30ff mov.w r0, #4294967295 8012f54: b01b add sp, #108 @ 0x6c 8012f56: bd30 pop {r4, r5, pc} 8012f58: f44f 7302 mov.w r3, #520 @ 0x208 8012f5c: f8ad 300c strh.w r3, [sp, #12] 8012f60: f04f 0300 mov.w r3, #0 8012f64: 9319 str r3, [sp, #100] @ 0x64 8012f66: bf0c ite eq 8012f68: 4623 moveq r3, r4 8012f6a: f104 33ff addne.w r3, r4, #4294967295 8012f6e: 9302 str r3, [sp, #8] 8012f70: 9305 str r3, [sp, #20] 8012f72: f64f 73ff movw r3, #65535 @ 0xffff 8012f76: 9100 str r1, [sp, #0] 8012f78: 9104 str r1, [sp, #16] 8012f7a: f8ad 300e strh.w r3, [sp, #14] 8012f7e: 4669 mov r1, sp 8012f80: 9b1e ldr r3, [sp, #120] @ 0x78 8012f82: f000 f9f5 bl 8013370 <_svfiprintf_r> 8012f86: 1c43 adds r3, r0, #1 8012f88: bfbc itt lt 8012f8a: 238b movlt r3, #139 @ 0x8b 8012f8c: 602b strlt r3, [r5, #0] 8012f8e: 2c00 cmp r4, #0 8012f90: d0e0 beq.n 8012f54 <_vsniprintf_r+0x16> 8012f92: 2200 movs r2, #0 8012f94: 9b00 ldr r3, [sp, #0] 8012f96: 701a strb r2, [r3, #0] 8012f98: e7dc b.n 8012f54 <_vsniprintf_r+0x16> ... 08012f9c : 8012f9c: b507 push {r0, r1, r2, lr} 8012f9e: 9300 str r3, [sp, #0] 8012fa0: 4613 mov r3, r2 8012fa2: 460a mov r2, r1 8012fa4: 4601 mov r1, r0 8012fa6: 4803 ldr r0, [pc, #12] @ (8012fb4 ) 8012fa8: 6800 ldr r0, [r0, #0] 8012faa: f7ff ffc8 bl 8012f3e <_vsniprintf_r> 8012fae: b003 add sp, #12 8012fb0: f85d fb04 ldr.w pc, [sp], #4 8012fb4: 20000084 .word 0x20000084 08012fb8 : 8012fb8: 4603 mov r3, r0 8012fba: 4402 add r2, r0 8012fbc: 4293 cmp r3, r2 8012fbe: d100 bne.n 8012fc2 8012fc0: 4770 bx lr 8012fc2: f803 1b01 strb.w r1, [r3], #1 8012fc6: e7f9 b.n 8012fbc 08012fc8 <_close_r>: 8012fc8: b538 push {r3, r4, r5, lr} 8012fca: 2300 movs r3, #0 8012fcc: 4d05 ldr r5, [pc, #20] @ (8012fe4 <_close_r+0x1c>) 8012fce: 4604 mov r4, r0 8012fd0: 4608 mov r0, r1 8012fd2: 602b str r3, [r5, #0] 8012fd4: f7f9 ffff bl 800cfd6 <_close> 8012fd8: 1c43 adds r3, r0, #1 8012fda: d102 bne.n 8012fe2 <_close_r+0x1a> 8012fdc: 682b ldr r3, [r5, #0] 8012fde: b103 cbz r3, 8012fe2 <_close_r+0x1a> 8012fe0: 6023 str r3, [r4, #0] 8012fe2: bd38 pop {r3, r4, r5, pc} 8012fe4: 200011b0 .word 0x200011b0 08012fe8 <_lseek_r>: 8012fe8: b538 push {r3, r4, r5, lr} 8012fea: 4604 mov r4, r0 8012fec: 4608 mov r0, r1 8012fee: 4611 mov r1, r2 8012ff0: 2200 movs r2, #0 8012ff2: 4d05 ldr r5, [pc, #20] @ (8013008 <_lseek_r+0x20>) 8012ff4: 602a str r2, [r5, #0] 8012ff6: 461a mov r2, r3 8012ff8: f7fa f811 bl 800d01e <_lseek> 8012ffc: 1c43 adds r3, r0, #1 8012ffe: d102 bne.n 8013006 <_lseek_r+0x1e> 8013000: 682b ldr r3, [r5, #0] 8013002: b103 cbz r3, 8013006 <_lseek_r+0x1e> 8013004: 6023 str r3, [r4, #0] 8013006: bd38 pop {r3, r4, r5, pc} 8013008: 200011b0 .word 0x200011b0 0801300c <_read_r>: 801300c: b538 push {r3, r4, r5, lr} 801300e: 4604 mov r4, r0 8013010: 4608 mov r0, r1 8013012: 4611 mov r1, r2 8013014: 2200 movs r2, #0 8013016: 4d05 ldr r5, [pc, #20] @ (801302c <_read_r+0x20>) 8013018: 602a str r2, [r5, #0] 801301a: 461a mov r2, r3 801301c: f7f9 ffbe bl 800cf9c <_read> 8013020: 1c43 adds r3, r0, #1 8013022: d102 bne.n 801302a <_read_r+0x1e> 8013024: 682b ldr r3, [r5, #0] 8013026: b103 cbz r3, 801302a <_read_r+0x1e> 8013028: 6023 str r3, [r4, #0] 801302a: bd38 pop {r3, r4, r5, pc} 801302c: 200011b0 .word 0x200011b0 08013030 <_write_r>: 8013030: b538 push {r3, r4, r5, lr} 8013032: 4604 mov r4, r0 8013034: 4608 mov r0, r1 8013036: 4611 mov r1, r2 8013038: 2200 movs r2, #0 801303a: 4d05 ldr r5, [pc, #20] @ (8013050 <_write_r+0x20>) 801303c: 602a str r2, [r5, #0] 801303e: 461a mov r2, r3 8013040: f7f7 f930 bl 800a2a4 <_write> 8013044: 1c43 adds r3, r0, #1 8013046: d102 bne.n 801304e <_write_r+0x1e> 8013048: 682b ldr r3, [r5, #0] 801304a: b103 cbz r3, 801304e <_write_r+0x1e> 801304c: 6023 str r3, [r4, #0] 801304e: bd38 pop {r3, r4, r5, pc} 8013050: 200011b0 .word 0x200011b0 08013054 <__errno>: 8013054: 4b01 ldr r3, [pc, #4] @ (801305c <__errno+0x8>) 8013056: 6818 ldr r0, [r3, #0] 8013058: 4770 bx lr 801305a: bf00 nop 801305c: 20000084 .word 0x20000084 08013060 <__libc_init_array>: 8013060: b570 push {r4, r5, r6, lr} 8013062: 2600 movs r6, #0 8013064: 4d0c ldr r5, [pc, #48] @ (8013098 <__libc_init_array+0x38>) 8013066: 4c0d ldr r4, [pc, #52] @ (801309c <__libc_init_array+0x3c>) 8013068: 1b64 subs r4, r4, r5 801306a: 10a4 asrs r4, r4, #2 801306c: 42a6 cmp r6, r4 801306e: d109 bne.n 8013084 <__libc_init_array+0x24> 8013070: f000 ff78 bl 8013f64 <_init> 8013074: 2600 movs r6, #0 8013076: 4d0a ldr r5, [pc, #40] @ (80130a0 <__libc_init_array+0x40>) 8013078: 4c0a ldr r4, [pc, #40] @ (80130a4 <__libc_init_array+0x44>) 801307a: 1b64 subs r4, r4, r5 801307c: 10a4 asrs r4, r4, #2 801307e: 42a6 cmp r6, r4 8013080: d105 bne.n 801308e <__libc_init_array+0x2e> 8013082: bd70 pop {r4, r5, r6, pc} 8013084: f855 3b04 ldr.w r3, [r5], #4 8013088: 4798 blx r3 801308a: 3601 adds r6, #1 801308c: e7ee b.n 801306c <__libc_init_array+0xc> 801308e: f855 3b04 ldr.w r3, [r5], #4 8013092: 4798 blx r3 8013094: 3601 adds r6, #1 8013096: e7f2 b.n 801307e <__libc_init_array+0x1e> 8013098: 08014430 .word 0x08014430 801309c: 08014430 .word 0x08014430 80130a0: 08014430 .word 0x08014430 80130a4: 08014434 .word 0x08014434 080130a8 <__retarget_lock_init_recursive>: 80130a8: 4770 bx lr 080130aa <__retarget_lock_acquire_recursive>: 80130aa: 4770 bx lr 080130ac <__retarget_lock_release_recursive>: 80130ac: 4770 bx lr 080130ae : 80130ae: 440a add r2, r1 80130b0: 4291 cmp r1, r2 80130b2: f100 33ff add.w r3, r0, #4294967295 80130b6: d100 bne.n 80130ba 80130b8: 4770 bx lr 80130ba: b510 push {r4, lr} 80130bc: f811 4b01 ldrb.w r4, [r1], #1 80130c0: 4291 cmp r1, r2 80130c2: f803 4f01 strb.w r4, [r3, #1]! 80130c6: d1f9 bne.n 80130bc 80130c8: bd10 pop {r4, pc} ... 080130cc <_free_r>: 80130cc: b538 push {r3, r4, r5, lr} 80130ce: 4605 mov r5, r0 80130d0: 2900 cmp r1, #0 80130d2: d040 beq.n 8013156 <_free_r+0x8a> 80130d4: f851 3c04 ldr.w r3, [r1, #-4] 80130d8: 1f0c subs r4, r1, #4 80130da: 2b00 cmp r3, #0 80130dc: bfb8 it lt 80130de: 18e4 addlt r4, r4, r3 80130e0: f000 f8de bl 80132a0 <__malloc_lock> 80130e4: 4a1c ldr r2, [pc, #112] @ (8013158 <_free_r+0x8c>) 80130e6: 6813 ldr r3, [r2, #0] 80130e8: b933 cbnz r3, 80130f8 <_free_r+0x2c> 80130ea: 6063 str r3, [r4, #4] 80130ec: 6014 str r4, [r2, #0] 80130ee: 4628 mov r0, r5 80130f0: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 80130f4: f000 b8da b.w 80132ac <__malloc_unlock> 80130f8: 42a3 cmp r3, r4 80130fa: d908 bls.n 801310e <_free_r+0x42> 80130fc: 6820 ldr r0, [r4, #0] 80130fe: 1821 adds r1, r4, r0 8013100: 428b cmp r3, r1 8013102: bf01 itttt eq 8013104: 6819 ldreq r1, [r3, #0] 8013106: 685b ldreq r3, [r3, #4] 8013108: 1809 addeq r1, r1, r0 801310a: 6021 streq r1, [r4, #0] 801310c: e7ed b.n 80130ea <_free_r+0x1e> 801310e: 461a mov r2, r3 8013110: 685b ldr r3, [r3, #4] 8013112: b10b cbz r3, 8013118 <_free_r+0x4c> 8013114: 42a3 cmp r3, r4 8013116: d9fa bls.n 801310e <_free_r+0x42> 8013118: 6811 ldr r1, [r2, #0] 801311a: 1850 adds r0, r2, r1 801311c: 42a0 cmp r0, r4 801311e: d10b bne.n 8013138 <_free_r+0x6c> 8013120: 6820 ldr r0, [r4, #0] 8013122: 4401 add r1, r0 8013124: 1850 adds r0, r2, r1 8013126: 4283 cmp r3, r0 8013128: 6011 str r1, [r2, #0] 801312a: d1e0 bne.n 80130ee <_free_r+0x22> 801312c: 6818 ldr r0, [r3, #0] 801312e: 685b ldr r3, [r3, #4] 8013130: 4408 add r0, r1 8013132: 6010 str r0, [r2, #0] 8013134: 6053 str r3, [r2, #4] 8013136: e7da b.n 80130ee <_free_r+0x22> 8013138: d902 bls.n 8013140 <_free_r+0x74> 801313a: 230c movs r3, #12 801313c: 602b str r3, [r5, #0] 801313e: e7d6 b.n 80130ee <_free_r+0x22> 8013140: 6820 ldr r0, [r4, #0] 8013142: 1821 adds r1, r4, r0 8013144: 428b cmp r3, r1 8013146: bf01 itttt eq 8013148: 6819 ldreq r1, [r3, #0] 801314a: 685b ldreq r3, [r3, #4] 801314c: 1809 addeq r1, r1, r0 801314e: 6021 streq r1, [r4, #0] 8013150: 6063 str r3, [r4, #4] 8013152: 6054 str r4, [r2, #4] 8013154: e7cb b.n 80130ee <_free_r+0x22> 8013156: bd38 pop {r3, r4, r5, pc} 8013158: 200011bc .word 0x200011bc 0801315c : 801315c: b570 push {r4, r5, r6, lr} 801315e: 4e0f ldr r6, [pc, #60] @ (801319c ) 8013160: 460c mov r4, r1 8013162: 6831 ldr r1, [r6, #0] 8013164: 4605 mov r5, r0 8013166: b911 cbnz r1, 801316e 8013168: f000 fe24 bl 8013db4 <_sbrk_r> 801316c: 6030 str r0, [r6, #0] 801316e: 4621 mov r1, r4 8013170: 4628 mov r0, r5 8013172: f000 fe1f bl 8013db4 <_sbrk_r> 8013176: 1c43 adds r3, r0, #1 8013178: d103 bne.n 8013182 801317a: f04f 34ff mov.w r4, #4294967295 801317e: 4620 mov r0, r4 8013180: bd70 pop {r4, r5, r6, pc} 8013182: 1cc4 adds r4, r0, #3 8013184: f024 0403 bic.w r4, r4, #3 8013188: 42a0 cmp r0, r4 801318a: d0f8 beq.n 801317e 801318c: 1a21 subs r1, r4, r0 801318e: 4628 mov r0, r5 8013190: f000 fe10 bl 8013db4 <_sbrk_r> 8013194: 3001 adds r0, #1 8013196: d1f2 bne.n 801317e 8013198: e7ef b.n 801317a 801319a: bf00 nop 801319c: 200011b8 .word 0x200011b8 080131a0 <_malloc_r>: 80131a0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 80131a4: 1ccd adds r5, r1, #3 80131a6: f025 0503 bic.w r5, r5, #3 80131aa: 3508 adds r5, #8 80131ac: 2d0c cmp r5, #12 80131ae: bf38 it cc 80131b0: 250c movcc r5, #12 80131b2: 2d00 cmp r5, #0 80131b4: 4606 mov r6, r0 80131b6: db01 blt.n 80131bc <_malloc_r+0x1c> 80131b8: 42a9 cmp r1, r5 80131ba: d904 bls.n 80131c6 <_malloc_r+0x26> 80131bc: 230c movs r3, #12 80131be: 6033 str r3, [r6, #0] 80131c0: 2000 movs r0, #0 80131c2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 80131c6: f8df 80d4 ldr.w r8, [pc, #212] @ 801329c <_malloc_r+0xfc> 80131ca: f000 f869 bl 80132a0 <__malloc_lock> 80131ce: f8d8 3000 ldr.w r3, [r8] 80131d2: 461c mov r4, r3 80131d4: bb44 cbnz r4, 8013228 <_malloc_r+0x88> 80131d6: 4629 mov r1, r5 80131d8: 4630 mov r0, r6 80131da: f7ff ffbf bl 801315c 80131de: 1c43 adds r3, r0, #1 80131e0: 4604 mov r4, r0 80131e2: d158 bne.n 8013296 <_malloc_r+0xf6> 80131e4: f8d8 4000 ldr.w r4, [r8] 80131e8: 4627 mov r7, r4 80131ea: 2f00 cmp r7, #0 80131ec: d143 bne.n 8013276 <_malloc_r+0xd6> 80131ee: 2c00 cmp r4, #0 80131f0: d04b beq.n 801328a <_malloc_r+0xea> 80131f2: 6823 ldr r3, [r4, #0] 80131f4: 4639 mov r1, r7 80131f6: 4630 mov r0, r6 80131f8: eb04 0903 add.w r9, r4, r3 80131fc: f000 fdda bl 8013db4 <_sbrk_r> 8013200: 4581 cmp r9, r0 8013202: d142 bne.n 801328a <_malloc_r+0xea> 8013204: 6821 ldr r1, [r4, #0] 8013206: 4630 mov r0, r6 8013208: 1a6d subs r5, r5, r1 801320a: 4629 mov r1, r5 801320c: f7ff ffa6 bl 801315c 8013210: 3001 adds r0, #1 8013212: d03a beq.n 801328a <_malloc_r+0xea> 8013214: 6823 ldr r3, [r4, #0] 8013216: 442b add r3, r5 8013218: 6023 str r3, [r4, #0] 801321a: f8d8 3000 ldr.w r3, [r8] 801321e: 685a ldr r2, [r3, #4] 8013220: bb62 cbnz r2, 801327c <_malloc_r+0xdc> 8013222: f8c8 7000 str.w r7, [r8] 8013226: e00f b.n 8013248 <_malloc_r+0xa8> 8013228: 6822 ldr r2, [r4, #0] 801322a: 1b52 subs r2, r2, r5 801322c: d420 bmi.n 8013270 <_malloc_r+0xd0> 801322e: 2a0b cmp r2, #11 8013230: d917 bls.n 8013262 <_malloc_r+0xc2> 8013232: 1961 adds r1, r4, r5 8013234: 42a3 cmp r3, r4 8013236: 6025 str r5, [r4, #0] 8013238: bf18 it ne 801323a: 6059 strne r1, [r3, #4] 801323c: 6863 ldr r3, [r4, #4] 801323e: bf08 it eq 8013240: f8c8 1000 streq.w r1, [r8] 8013244: 5162 str r2, [r4, r5] 8013246: 604b str r3, [r1, #4] 8013248: 4630 mov r0, r6 801324a: f000 f82f bl 80132ac <__malloc_unlock> 801324e: f104 000b add.w r0, r4, #11 8013252: 1d23 adds r3, r4, #4 8013254: f020 0007 bic.w r0, r0, #7 8013258: 1ac2 subs r2, r0, r3 801325a: bf1c itt ne 801325c: 1a1b subne r3, r3, r0 801325e: 50a3 strne r3, [r4, r2] 8013260: e7af b.n 80131c2 <_malloc_r+0x22> 8013262: 6862 ldr r2, [r4, #4] 8013264: 42a3 cmp r3, r4 8013266: bf0c ite eq 8013268: f8c8 2000 streq.w r2, [r8] 801326c: 605a strne r2, [r3, #4] 801326e: e7eb b.n 8013248 <_malloc_r+0xa8> 8013270: 4623 mov r3, r4 8013272: 6864 ldr r4, [r4, #4] 8013274: e7ae b.n 80131d4 <_malloc_r+0x34> 8013276: 463c mov r4, r7 8013278: 687f ldr r7, [r7, #4] 801327a: e7b6 b.n 80131ea <_malloc_r+0x4a> 801327c: 461a mov r2, r3 801327e: 685b ldr r3, [r3, #4] 8013280: 42a3 cmp r3, r4 8013282: d1fb bne.n 801327c <_malloc_r+0xdc> 8013284: 2300 movs r3, #0 8013286: 6053 str r3, [r2, #4] 8013288: e7de b.n 8013248 <_malloc_r+0xa8> 801328a: 230c movs r3, #12 801328c: 4630 mov r0, r6 801328e: 6033 str r3, [r6, #0] 8013290: f000 f80c bl 80132ac <__malloc_unlock> 8013294: e794 b.n 80131c0 <_malloc_r+0x20> 8013296: 6005 str r5, [r0, #0] 8013298: e7d6 b.n 8013248 <_malloc_r+0xa8> 801329a: bf00 nop 801329c: 200011bc .word 0x200011bc 080132a0 <__malloc_lock>: 80132a0: 4801 ldr r0, [pc, #4] @ (80132a8 <__malloc_lock+0x8>) 80132a2: f7ff bf02 b.w 80130aa <__retarget_lock_acquire_recursive> 80132a6: bf00 nop 80132a8: 200011b4 .word 0x200011b4 080132ac <__malloc_unlock>: 80132ac: 4801 ldr r0, [pc, #4] @ (80132b4 <__malloc_unlock+0x8>) 80132ae: f7ff befd b.w 80130ac <__retarget_lock_release_recursive> 80132b2: bf00 nop 80132b4: 200011b4 .word 0x200011b4 080132b8 <__ssputs_r>: 80132b8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80132bc: 461f mov r7, r3 80132be: 688e ldr r6, [r1, #8] 80132c0: 4682 mov sl, r0 80132c2: 42be cmp r6, r7 80132c4: 460c mov r4, r1 80132c6: 4690 mov r8, r2 80132c8: 680b ldr r3, [r1, #0] 80132ca: d82d bhi.n 8013328 <__ssputs_r+0x70> 80132cc: f9b1 200c ldrsh.w r2, [r1, #12] 80132d0: f412 6f90 tst.w r2, #1152 @ 0x480 80132d4: d026 beq.n 8013324 <__ssputs_r+0x6c> 80132d6: 6965 ldr r5, [r4, #20] 80132d8: 6909 ldr r1, [r1, #16] 80132da: eb05 0545 add.w r5, r5, r5, lsl #1 80132de: eba3 0901 sub.w r9, r3, r1 80132e2: eb05 75d5 add.w r5, r5, r5, lsr #31 80132e6: 1c7b adds r3, r7, #1 80132e8: 444b add r3, r9 80132ea: 106d asrs r5, r5, #1 80132ec: 429d cmp r5, r3 80132ee: bf38 it cc 80132f0: 461d movcc r5, r3 80132f2: 0553 lsls r3, r2, #21 80132f4: d527 bpl.n 8013346 <__ssputs_r+0x8e> 80132f6: 4629 mov r1, r5 80132f8: f7ff ff52 bl 80131a0 <_malloc_r> 80132fc: 4606 mov r6, r0 80132fe: b360 cbz r0, 801335a <__ssputs_r+0xa2> 8013300: 464a mov r2, r9 8013302: 6921 ldr r1, [r4, #16] 8013304: f7ff fed3 bl 80130ae 8013308: 89a3 ldrh r3, [r4, #12] 801330a: f423 6390 bic.w r3, r3, #1152 @ 0x480 801330e: f043 0380 orr.w r3, r3, #128 @ 0x80 8013312: 81a3 strh r3, [r4, #12] 8013314: 6126 str r6, [r4, #16] 8013316: 444e add r6, r9 8013318: 6026 str r6, [r4, #0] 801331a: 463e mov r6, r7 801331c: 6165 str r5, [r4, #20] 801331e: eba5 0509 sub.w r5, r5, r9 8013322: 60a5 str r5, [r4, #8] 8013324: 42be cmp r6, r7 8013326: d900 bls.n 801332a <__ssputs_r+0x72> 8013328: 463e mov r6, r7 801332a: 4632 mov r2, r6 801332c: 4641 mov r1, r8 801332e: 6820 ldr r0, [r4, #0] 8013330: f000 fd26 bl 8013d80 8013334: 2000 movs r0, #0 8013336: 68a3 ldr r3, [r4, #8] 8013338: 1b9b subs r3, r3, r6 801333a: 60a3 str r3, [r4, #8] 801333c: 6823 ldr r3, [r4, #0] 801333e: 4433 add r3, r6 8013340: 6023 str r3, [r4, #0] 8013342: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8013346: 462a mov r2, r5 8013348: f000 fd52 bl 8013df0 <_realloc_r> 801334c: 4606 mov r6, r0 801334e: 2800 cmp r0, #0 8013350: d1e0 bne.n 8013314 <__ssputs_r+0x5c> 8013352: 4650 mov r0, sl 8013354: 6921 ldr r1, [r4, #16] 8013356: f7ff feb9 bl 80130cc <_free_r> 801335a: 230c movs r3, #12 801335c: f8ca 3000 str.w r3, [sl] 8013360: 89a3 ldrh r3, [r4, #12] 8013362: f04f 30ff mov.w r0, #4294967295 8013366: f043 0340 orr.w r3, r3, #64 @ 0x40 801336a: 81a3 strh r3, [r4, #12] 801336c: e7e9 b.n 8013342 <__ssputs_r+0x8a> ... 08013370 <_svfiprintf_r>: 8013370: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8013374: 4698 mov r8, r3 8013376: 898b ldrh r3, [r1, #12] 8013378: 4607 mov r7, r0 801337a: 061b lsls r3, r3, #24 801337c: 460d mov r5, r1 801337e: 4614 mov r4, r2 8013380: b09d sub sp, #116 @ 0x74 8013382: d510 bpl.n 80133a6 <_svfiprintf_r+0x36> 8013384: 690b ldr r3, [r1, #16] 8013386: b973 cbnz r3, 80133a6 <_svfiprintf_r+0x36> 8013388: 2140 movs r1, #64 @ 0x40 801338a: f7ff ff09 bl 80131a0 <_malloc_r> 801338e: 6028 str r0, [r5, #0] 8013390: 6128 str r0, [r5, #16] 8013392: b930 cbnz r0, 80133a2 <_svfiprintf_r+0x32> 8013394: 230c movs r3, #12 8013396: 603b str r3, [r7, #0] 8013398: f04f 30ff mov.w r0, #4294967295 801339c: b01d add sp, #116 @ 0x74 801339e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80133a2: 2340 movs r3, #64 @ 0x40 80133a4: 616b str r3, [r5, #20] 80133a6: 2300 movs r3, #0 80133a8: 9309 str r3, [sp, #36] @ 0x24 80133aa: 2320 movs r3, #32 80133ac: f88d 3029 strb.w r3, [sp, #41] @ 0x29 80133b0: 2330 movs r3, #48 @ 0x30 80133b2: f04f 0901 mov.w r9, #1 80133b6: f8cd 800c str.w r8, [sp, #12] 80133ba: f8df 8198 ldr.w r8, [pc, #408] @ 8013554 <_svfiprintf_r+0x1e4> 80133be: f88d 302a strb.w r3, [sp, #42] @ 0x2a 80133c2: 4623 mov r3, r4 80133c4: 469a mov sl, r3 80133c6: f813 2b01 ldrb.w r2, [r3], #1 80133ca: b10a cbz r2, 80133d0 <_svfiprintf_r+0x60> 80133cc: 2a25 cmp r2, #37 @ 0x25 80133ce: d1f9 bne.n 80133c4 <_svfiprintf_r+0x54> 80133d0: ebba 0b04 subs.w fp, sl, r4 80133d4: d00b beq.n 80133ee <_svfiprintf_r+0x7e> 80133d6: 465b mov r3, fp 80133d8: 4622 mov r2, r4 80133da: 4629 mov r1, r5 80133dc: 4638 mov r0, r7 80133de: f7ff ff6b bl 80132b8 <__ssputs_r> 80133e2: 3001 adds r0, #1 80133e4: f000 80a7 beq.w 8013536 <_svfiprintf_r+0x1c6> 80133e8: 9a09 ldr r2, [sp, #36] @ 0x24 80133ea: 445a add r2, fp 80133ec: 9209 str r2, [sp, #36] @ 0x24 80133ee: f89a 3000 ldrb.w r3, [sl] 80133f2: 2b00 cmp r3, #0 80133f4: f000 809f beq.w 8013536 <_svfiprintf_r+0x1c6> 80133f8: 2300 movs r3, #0 80133fa: f04f 32ff mov.w r2, #4294967295 80133fe: e9cd 2305 strd r2, r3, [sp, #20] 8013402: f10a 0a01 add.w sl, sl, #1 8013406: 9304 str r3, [sp, #16] 8013408: 9307 str r3, [sp, #28] 801340a: f88d 3053 strb.w r3, [sp, #83] @ 0x53 801340e: 931a str r3, [sp, #104] @ 0x68 8013410: 4654 mov r4, sl 8013412: 2205 movs r2, #5 8013414: f814 1b01 ldrb.w r1, [r4], #1 8013418: 484e ldr r0, [pc, #312] @ (8013554 <_svfiprintf_r+0x1e4>) 801341a: f000 fcdb bl 8013dd4 801341e: 9a04 ldr r2, [sp, #16] 8013420: b9d8 cbnz r0, 801345a <_svfiprintf_r+0xea> 8013422: 06d0 lsls r0, r2, #27 8013424: bf44 itt mi 8013426: 2320 movmi r3, #32 8013428: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 801342c: 0711 lsls r1, r2, #28 801342e: bf44 itt mi 8013430: 232b movmi r3, #43 @ 0x2b 8013432: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8013436: f89a 3000 ldrb.w r3, [sl] 801343a: 2b2a cmp r3, #42 @ 0x2a 801343c: d015 beq.n 801346a <_svfiprintf_r+0xfa> 801343e: 4654 mov r4, sl 8013440: 2000 movs r0, #0 8013442: f04f 0c0a mov.w ip, #10 8013446: 9a07 ldr r2, [sp, #28] 8013448: 4621 mov r1, r4 801344a: f811 3b01 ldrb.w r3, [r1], #1 801344e: 3b30 subs r3, #48 @ 0x30 8013450: 2b09 cmp r3, #9 8013452: d94b bls.n 80134ec <_svfiprintf_r+0x17c> 8013454: b1b0 cbz r0, 8013484 <_svfiprintf_r+0x114> 8013456: 9207 str r2, [sp, #28] 8013458: e014 b.n 8013484 <_svfiprintf_r+0x114> 801345a: eba0 0308 sub.w r3, r0, r8 801345e: fa09 f303 lsl.w r3, r9, r3 8013462: 4313 orrs r3, r2 8013464: 46a2 mov sl, r4 8013466: 9304 str r3, [sp, #16] 8013468: e7d2 b.n 8013410 <_svfiprintf_r+0xa0> 801346a: 9b03 ldr r3, [sp, #12] 801346c: 1d19 adds r1, r3, #4 801346e: 681b ldr r3, [r3, #0] 8013470: 9103 str r1, [sp, #12] 8013472: 2b00 cmp r3, #0 8013474: bfbb ittet lt 8013476: 425b neglt r3, r3 8013478: f042 0202 orrlt.w r2, r2, #2 801347c: 9307 strge r3, [sp, #28] 801347e: 9307 strlt r3, [sp, #28] 8013480: bfb8 it lt 8013482: 9204 strlt r2, [sp, #16] 8013484: 7823 ldrb r3, [r4, #0] 8013486: 2b2e cmp r3, #46 @ 0x2e 8013488: d10a bne.n 80134a0 <_svfiprintf_r+0x130> 801348a: 7863 ldrb r3, [r4, #1] 801348c: 2b2a cmp r3, #42 @ 0x2a 801348e: d132 bne.n 80134f6 <_svfiprintf_r+0x186> 8013490: 9b03 ldr r3, [sp, #12] 8013492: 3402 adds r4, #2 8013494: 1d1a adds r2, r3, #4 8013496: 681b ldr r3, [r3, #0] 8013498: 9203 str r2, [sp, #12] 801349a: ea43 73e3 orr.w r3, r3, r3, asr #31 801349e: 9305 str r3, [sp, #20] 80134a0: f8df a0b4 ldr.w sl, [pc, #180] @ 8013558 <_svfiprintf_r+0x1e8> 80134a4: 2203 movs r2, #3 80134a6: 4650 mov r0, sl 80134a8: 7821 ldrb r1, [r4, #0] 80134aa: f000 fc93 bl 8013dd4 80134ae: b138 cbz r0, 80134c0 <_svfiprintf_r+0x150> 80134b0: 2240 movs r2, #64 @ 0x40 80134b2: 9b04 ldr r3, [sp, #16] 80134b4: eba0 000a sub.w r0, r0, sl 80134b8: 4082 lsls r2, r0 80134ba: 4313 orrs r3, r2 80134bc: 3401 adds r4, #1 80134be: 9304 str r3, [sp, #16] 80134c0: f814 1b01 ldrb.w r1, [r4], #1 80134c4: 2206 movs r2, #6 80134c6: 4825 ldr r0, [pc, #148] @ (801355c <_svfiprintf_r+0x1ec>) 80134c8: f88d 1028 strb.w r1, [sp, #40] @ 0x28 80134cc: f000 fc82 bl 8013dd4 80134d0: 2800 cmp r0, #0 80134d2: d036 beq.n 8013542 <_svfiprintf_r+0x1d2> 80134d4: 4b22 ldr r3, [pc, #136] @ (8013560 <_svfiprintf_r+0x1f0>) 80134d6: bb1b cbnz r3, 8013520 <_svfiprintf_r+0x1b0> 80134d8: 9b03 ldr r3, [sp, #12] 80134da: 3307 adds r3, #7 80134dc: f023 0307 bic.w r3, r3, #7 80134e0: 3308 adds r3, #8 80134e2: 9303 str r3, [sp, #12] 80134e4: 9b09 ldr r3, [sp, #36] @ 0x24 80134e6: 4433 add r3, r6 80134e8: 9309 str r3, [sp, #36] @ 0x24 80134ea: e76a b.n 80133c2 <_svfiprintf_r+0x52> 80134ec: 460c mov r4, r1 80134ee: 2001 movs r0, #1 80134f0: fb0c 3202 mla r2, ip, r2, r3 80134f4: e7a8 b.n 8013448 <_svfiprintf_r+0xd8> 80134f6: 2300 movs r3, #0 80134f8: f04f 0c0a mov.w ip, #10 80134fc: 4619 mov r1, r3 80134fe: 3401 adds r4, #1 8013500: 9305 str r3, [sp, #20] 8013502: 4620 mov r0, r4 8013504: f810 2b01 ldrb.w r2, [r0], #1 8013508: 3a30 subs r2, #48 @ 0x30 801350a: 2a09 cmp r2, #9 801350c: d903 bls.n 8013516 <_svfiprintf_r+0x1a6> 801350e: 2b00 cmp r3, #0 8013510: d0c6 beq.n 80134a0 <_svfiprintf_r+0x130> 8013512: 9105 str r1, [sp, #20] 8013514: e7c4 b.n 80134a0 <_svfiprintf_r+0x130> 8013516: 4604 mov r4, r0 8013518: 2301 movs r3, #1 801351a: fb0c 2101 mla r1, ip, r1, r2 801351e: e7f0 b.n 8013502 <_svfiprintf_r+0x192> 8013520: ab03 add r3, sp, #12 8013522: 9300 str r3, [sp, #0] 8013524: 462a mov r2, r5 8013526: 4638 mov r0, r7 8013528: 4b0e ldr r3, [pc, #56] @ (8013564 <_svfiprintf_r+0x1f4>) 801352a: a904 add r1, sp, #16 801352c: f3af 8000 nop.w 8013530: 1c42 adds r2, r0, #1 8013532: 4606 mov r6, r0 8013534: d1d6 bne.n 80134e4 <_svfiprintf_r+0x174> 8013536: 89ab ldrh r3, [r5, #12] 8013538: 065b lsls r3, r3, #25 801353a: f53f af2d bmi.w 8013398 <_svfiprintf_r+0x28> 801353e: 9809 ldr r0, [sp, #36] @ 0x24 8013540: e72c b.n 801339c <_svfiprintf_r+0x2c> 8013542: ab03 add r3, sp, #12 8013544: 9300 str r3, [sp, #0] 8013546: 462a mov r2, r5 8013548: 4638 mov r0, r7 801354a: 4b06 ldr r3, [pc, #24] @ (8013564 <_svfiprintf_r+0x1f4>) 801354c: a904 add r1, sp, #16 801354e: f000 f9bd bl 80138cc <_printf_i> 8013552: e7ed b.n 8013530 <_svfiprintf_r+0x1c0> 8013554: 080143f4 .word 0x080143f4 8013558: 080143fa .word 0x080143fa 801355c: 080143fe .word 0x080143fe 8013560: 00000000 .word 0x00000000 8013564: 080132b9 .word 0x080132b9 08013568 <__sfputc_r>: 8013568: 6893 ldr r3, [r2, #8] 801356a: b410 push {r4} 801356c: 3b01 subs r3, #1 801356e: 2b00 cmp r3, #0 8013570: 6093 str r3, [r2, #8] 8013572: da07 bge.n 8013584 <__sfputc_r+0x1c> 8013574: 6994 ldr r4, [r2, #24] 8013576: 42a3 cmp r3, r4 8013578: db01 blt.n 801357e <__sfputc_r+0x16> 801357a: 290a cmp r1, #10 801357c: d102 bne.n 8013584 <__sfputc_r+0x1c> 801357e: bc10 pop {r4} 8013580: f000 bb6a b.w 8013c58 <__swbuf_r> 8013584: 6813 ldr r3, [r2, #0] 8013586: 1c58 adds r0, r3, #1 8013588: 6010 str r0, [r2, #0] 801358a: 7019 strb r1, [r3, #0] 801358c: 4608 mov r0, r1 801358e: bc10 pop {r4} 8013590: 4770 bx lr 08013592 <__sfputs_r>: 8013592: b5f8 push {r3, r4, r5, r6, r7, lr} 8013594: 4606 mov r6, r0 8013596: 460f mov r7, r1 8013598: 4614 mov r4, r2 801359a: 18d5 adds r5, r2, r3 801359c: 42ac cmp r4, r5 801359e: d101 bne.n 80135a4 <__sfputs_r+0x12> 80135a0: 2000 movs r0, #0 80135a2: e007 b.n 80135b4 <__sfputs_r+0x22> 80135a4: 463a mov r2, r7 80135a6: 4630 mov r0, r6 80135a8: f814 1b01 ldrb.w r1, [r4], #1 80135ac: f7ff ffdc bl 8013568 <__sfputc_r> 80135b0: 1c43 adds r3, r0, #1 80135b2: d1f3 bne.n 801359c <__sfputs_r+0xa> 80135b4: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 080135b8 <_vfiprintf_r>: 80135b8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80135bc: 460d mov r5, r1 80135be: 4614 mov r4, r2 80135c0: 4698 mov r8, r3 80135c2: 4606 mov r6, r0 80135c4: b09d sub sp, #116 @ 0x74 80135c6: b118 cbz r0, 80135d0 <_vfiprintf_r+0x18> 80135c8: 6a03 ldr r3, [r0, #32] 80135ca: b90b cbnz r3, 80135d0 <_vfiprintf_r+0x18> 80135cc: f7ff fc2c bl 8012e28 <__sinit> 80135d0: 6e6b ldr r3, [r5, #100] @ 0x64 80135d2: 07d9 lsls r1, r3, #31 80135d4: d405 bmi.n 80135e2 <_vfiprintf_r+0x2a> 80135d6: 89ab ldrh r3, [r5, #12] 80135d8: 059a lsls r2, r3, #22 80135da: d402 bmi.n 80135e2 <_vfiprintf_r+0x2a> 80135dc: 6da8 ldr r0, [r5, #88] @ 0x58 80135de: f7ff fd64 bl 80130aa <__retarget_lock_acquire_recursive> 80135e2: 89ab ldrh r3, [r5, #12] 80135e4: 071b lsls r3, r3, #28 80135e6: d501 bpl.n 80135ec <_vfiprintf_r+0x34> 80135e8: 692b ldr r3, [r5, #16] 80135ea: b99b cbnz r3, 8013614 <_vfiprintf_r+0x5c> 80135ec: 4629 mov r1, r5 80135ee: 4630 mov r0, r6 80135f0: f000 fb70 bl 8013cd4 <__swsetup_r> 80135f4: b170 cbz r0, 8013614 <_vfiprintf_r+0x5c> 80135f6: 6e6b ldr r3, [r5, #100] @ 0x64 80135f8: 07dc lsls r4, r3, #31 80135fa: d504 bpl.n 8013606 <_vfiprintf_r+0x4e> 80135fc: f04f 30ff mov.w r0, #4294967295 8013600: b01d add sp, #116 @ 0x74 8013602: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8013606: 89ab ldrh r3, [r5, #12] 8013608: 0598 lsls r0, r3, #22 801360a: d4f7 bmi.n 80135fc <_vfiprintf_r+0x44> 801360c: 6da8 ldr r0, [r5, #88] @ 0x58 801360e: f7ff fd4d bl 80130ac <__retarget_lock_release_recursive> 8013612: e7f3 b.n 80135fc <_vfiprintf_r+0x44> 8013614: 2300 movs r3, #0 8013616: 9309 str r3, [sp, #36] @ 0x24 8013618: 2320 movs r3, #32 801361a: f88d 3029 strb.w r3, [sp, #41] @ 0x29 801361e: 2330 movs r3, #48 @ 0x30 8013620: f04f 0901 mov.w r9, #1 8013624: f8cd 800c str.w r8, [sp, #12] 8013628: f8df 81a8 ldr.w r8, [pc, #424] @ 80137d4 <_vfiprintf_r+0x21c> 801362c: f88d 302a strb.w r3, [sp, #42] @ 0x2a 8013630: 4623 mov r3, r4 8013632: 469a mov sl, r3 8013634: f813 2b01 ldrb.w r2, [r3], #1 8013638: b10a cbz r2, 801363e <_vfiprintf_r+0x86> 801363a: 2a25 cmp r2, #37 @ 0x25 801363c: d1f9 bne.n 8013632 <_vfiprintf_r+0x7a> 801363e: ebba 0b04 subs.w fp, sl, r4 8013642: d00b beq.n 801365c <_vfiprintf_r+0xa4> 8013644: 465b mov r3, fp 8013646: 4622 mov r2, r4 8013648: 4629 mov r1, r5 801364a: 4630 mov r0, r6 801364c: f7ff ffa1 bl 8013592 <__sfputs_r> 8013650: 3001 adds r0, #1 8013652: f000 80a7 beq.w 80137a4 <_vfiprintf_r+0x1ec> 8013656: 9a09 ldr r2, [sp, #36] @ 0x24 8013658: 445a add r2, fp 801365a: 9209 str r2, [sp, #36] @ 0x24 801365c: f89a 3000 ldrb.w r3, [sl] 8013660: 2b00 cmp r3, #0 8013662: f000 809f beq.w 80137a4 <_vfiprintf_r+0x1ec> 8013666: 2300 movs r3, #0 8013668: f04f 32ff mov.w r2, #4294967295 801366c: e9cd 2305 strd r2, r3, [sp, #20] 8013670: f10a 0a01 add.w sl, sl, #1 8013674: 9304 str r3, [sp, #16] 8013676: 9307 str r3, [sp, #28] 8013678: f88d 3053 strb.w r3, [sp, #83] @ 0x53 801367c: 931a str r3, [sp, #104] @ 0x68 801367e: 4654 mov r4, sl 8013680: 2205 movs r2, #5 8013682: f814 1b01 ldrb.w r1, [r4], #1 8013686: 4853 ldr r0, [pc, #332] @ (80137d4 <_vfiprintf_r+0x21c>) 8013688: f000 fba4 bl 8013dd4 801368c: 9a04 ldr r2, [sp, #16] 801368e: b9d8 cbnz r0, 80136c8 <_vfiprintf_r+0x110> 8013690: 06d1 lsls r1, r2, #27 8013692: bf44 itt mi 8013694: 2320 movmi r3, #32 8013696: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 801369a: 0713 lsls r3, r2, #28 801369c: bf44 itt mi 801369e: 232b movmi r3, #43 @ 0x2b 80136a0: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 80136a4: f89a 3000 ldrb.w r3, [sl] 80136a8: 2b2a cmp r3, #42 @ 0x2a 80136aa: d015 beq.n 80136d8 <_vfiprintf_r+0x120> 80136ac: 4654 mov r4, sl 80136ae: 2000 movs r0, #0 80136b0: f04f 0c0a mov.w ip, #10 80136b4: 9a07 ldr r2, [sp, #28] 80136b6: 4621 mov r1, r4 80136b8: f811 3b01 ldrb.w r3, [r1], #1 80136bc: 3b30 subs r3, #48 @ 0x30 80136be: 2b09 cmp r3, #9 80136c0: d94b bls.n 801375a <_vfiprintf_r+0x1a2> 80136c2: b1b0 cbz r0, 80136f2 <_vfiprintf_r+0x13a> 80136c4: 9207 str r2, [sp, #28] 80136c6: e014 b.n 80136f2 <_vfiprintf_r+0x13a> 80136c8: eba0 0308 sub.w r3, r0, r8 80136cc: fa09 f303 lsl.w r3, r9, r3 80136d0: 4313 orrs r3, r2 80136d2: 46a2 mov sl, r4 80136d4: 9304 str r3, [sp, #16] 80136d6: e7d2 b.n 801367e <_vfiprintf_r+0xc6> 80136d8: 9b03 ldr r3, [sp, #12] 80136da: 1d19 adds r1, r3, #4 80136dc: 681b ldr r3, [r3, #0] 80136de: 9103 str r1, [sp, #12] 80136e0: 2b00 cmp r3, #0 80136e2: bfbb ittet lt 80136e4: 425b neglt r3, r3 80136e6: f042 0202 orrlt.w r2, r2, #2 80136ea: 9307 strge r3, [sp, #28] 80136ec: 9307 strlt r3, [sp, #28] 80136ee: bfb8 it lt 80136f0: 9204 strlt r2, [sp, #16] 80136f2: 7823 ldrb r3, [r4, #0] 80136f4: 2b2e cmp r3, #46 @ 0x2e 80136f6: d10a bne.n 801370e <_vfiprintf_r+0x156> 80136f8: 7863 ldrb r3, [r4, #1] 80136fa: 2b2a cmp r3, #42 @ 0x2a 80136fc: d132 bne.n 8013764 <_vfiprintf_r+0x1ac> 80136fe: 9b03 ldr r3, [sp, #12] 8013700: 3402 adds r4, #2 8013702: 1d1a adds r2, r3, #4 8013704: 681b ldr r3, [r3, #0] 8013706: 9203 str r2, [sp, #12] 8013708: ea43 73e3 orr.w r3, r3, r3, asr #31 801370c: 9305 str r3, [sp, #20] 801370e: f8df a0c8 ldr.w sl, [pc, #200] @ 80137d8 <_vfiprintf_r+0x220> 8013712: 2203 movs r2, #3 8013714: 4650 mov r0, sl 8013716: 7821 ldrb r1, [r4, #0] 8013718: f000 fb5c bl 8013dd4 801371c: b138 cbz r0, 801372e <_vfiprintf_r+0x176> 801371e: 2240 movs r2, #64 @ 0x40 8013720: 9b04 ldr r3, [sp, #16] 8013722: eba0 000a sub.w r0, r0, sl 8013726: 4082 lsls r2, r0 8013728: 4313 orrs r3, r2 801372a: 3401 adds r4, #1 801372c: 9304 str r3, [sp, #16] 801372e: f814 1b01 ldrb.w r1, [r4], #1 8013732: 2206 movs r2, #6 8013734: 4829 ldr r0, [pc, #164] @ (80137dc <_vfiprintf_r+0x224>) 8013736: f88d 1028 strb.w r1, [sp, #40] @ 0x28 801373a: f000 fb4b bl 8013dd4 801373e: 2800 cmp r0, #0 8013740: d03f beq.n 80137c2 <_vfiprintf_r+0x20a> 8013742: 4b27 ldr r3, [pc, #156] @ (80137e0 <_vfiprintf_r+0x228>) 8013744: bb1b cbnz r3, 801378e <_vfiprintf_r+0x1d6> 8013746: 9b03 ldr r3, [sp, #12] 8013748: 3307 adds r3, #7 801374a: f023 0307 bic.w r3, r3, #7 801374e: 3308 adds r3, #8 8013750: 9303 str r3, [sp, #12] 8013752: 9b09 ldr r3, [sp, #36] @ 0x24 8013754: 443b add r3, r7 8013756: 9309 str r3, [sp, #36] @ 0x24 8013758: e76a b.n 8013630 <_vfiprintf_r+0x78> 801375a: 460c mov r4, r1 801375c: 2001 movs r0, #1 801375e: fb0c 3202 mla r2, ip, r2, r3 8013762: e7a8 b.n 80136b6 <_vfiprintf_r+0xfe> 8013764: 2300 movs r3, #0 8013766: f04f 0c0a mov.w ip, #10 801376a: 4619 mov r1, r3 801376c: 3401 adds r4, #1 801376e: 9305 str r3, [sp, #20] 8013770: 4620 mov r0, r4 8013772: f810 2b01 ldrb.w r2, [r0], #1 8013776: 3a30 subs r2, #48 @ 0x30 8013778: 2a09 cmp r2, #9 801377a: d903 bls.n 8013784 <_vfiprintf_r+0x1cc> 801377c: 2b00 cmp r3, #0 801377e: d0c6 beq.n 801370e <_vfiprintf_r+0x156> 8013780: 9105 str r1, [sp, #20] 8013782: e7c4 b.n 801370e <_vfiprintf_r+0x156> 8013784: 4604 mov r4, r0 8013786: 2301 movs r3, #1 8013788: fb0c 2101 mla r1, ip, r1, r2 801378c: e7f0 b.n 8013770 <_vfiprintf_r+0x1b8> 801378e: ab03 add r3, sp, #12 8013790: 9300 str r3, [sp, #0] 8013792: 462a mov r2, r5 8013794: 4630 mov r0, r6 8013796: 4b13 ldr r3, [pc, #76] @ (80137e4 <_vfiprintf_r+0x22c>) 8013798: a904 add r1, sp, #16 801379a: f3af 8000 nop.w 801379e: 4607 mov r7, r0 80137a0: 1c78 adds r0, r7, #1 80137a2: d1d6 bne.n 8013752 <_vfiprintf_r+0x19a> 80137a4: 6e6b ldr r3, [r5, #100] @ 0x64 80137a6: 07d9 lsls r1, r3, #31 80137a8: d405 bmi.n 80137b6 <_vfiprintf_r+0x1fe> 80137aa: 89ab ldrh r3, [r5, #12] 80137ac: 059a lsls r2, r3, #22 80137ae: d402 bmi.n 80137b6 <_vfiprintf_r+0x1fe> 80137b0: 6da8 ldr r0, [r5, #88] @ 0x58 80137b2: f7ff fc7b bl 80130ac <__retarget_lock_release_recursive> 80137b6: 89ab ldrh r3, [r5, #12] 80137b8: 065b lsls r3, r3, #25 80137ba: f53f af1f bmi.w 80135fc <_vfiprintf_r+0x44> 80137be: 9809 ldr r0, [sp, #36] @ 0x24 80137c0: e71e b.n 8013600 <_vfiprintf_r+0x48> 80137c2: ab03 add r3, sp, #12 80137c4: 9300 str r3, [sp, #0] 80137c6: 462a mov r2, r5 80137c8: 4630 mov r0, r6 80137ca: 4b06 ldr r3, [pc, #24] @ (80137e4 <_vfiprintf_r+0x22c>) 80137cc: a904 add r1, sp, #16 80137ce: f000 f87d bl 80138cc <_printf_i> 80137d2: e7e4 b.n 801379e <_vfiprintf_r+0x1e6> 80137d4: 080143f4 .word 0x080143f4 80137d8: 080143fa .word 0x080143fa 80137dc: 080143fe .word 0x080143fe 80137e0: 00000000 .word 0x00000000 80137e4: 08013593 .word 0x08013593 080137e8 <_printf_common>: 80137e8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80137ec: 4616 mov r6, r2 80137ee: 4698 mov r8, r3 80137f0: 688a ldr r2, [r1, #8] 80137f2: 690b ldr r3, [r1, #16] 80137f4: 4607 mov r7, r0 80137f6: 4293 cmp r3, r2 80137f8: bfb8 it lt 80137fa: 4613 movlt r3, r2 80137fc: 6033 str r3, [r6, #0] 80137fe: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 8013802: 460c mov r4, r1 8013804: f8dd 9020 ldr.w r9, [sp, #32] 8013808: b10a cbz r2, 801380e <_printf_common+0x26> 801380a: 3301 adds r3, #1 801380c: 6033 str r3, [r6, #0] 801380e: 6823 ldr r3, [r4, #0] 8013810: 0699 lsls r1, r3, #26 8013812: bf42 ittt mi 8013814: 6833 ldrmi r3, [r6, #0] 8013816: 3302 addmi r3, #2 8013818: 6033 strmi r3, [r6, #0] 801381a: 6825 ldr r5, [r4, #0] 801381c: f015 0506 ands.w r5, r5, #6 8013820: d106 bne.n 8013830 <_printf_common+0x48> 8013822: f104 0a19 add.w sl, r4, #25 8013826: 68e3 ldr r3, [r4, #12] 8013828: 6832 ldr r2, [r6, #0] 801382a: 1a9b subs r3, r3, r2 801382c: 42ab cmp r3, r5 801382e: dc2b bgt.n 8013888 <_printf_common+0xa0> 8013830: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 8013834: 6822 ldr r2, [r4, #0] 8013836: 3b00 subs r3, #0 8013838: bf18 it ne 801383a: 2301 movne r3, #1 801383c: 0692 lsls r2, r2, #26 801383e: d430 bmi.n 80138a2 <_printf_common+0xba> 8013840: 4641 mov r1, r8 8013842: 4638 mov r0, r7 8013844: f104 0243 add.w r2, r4, #67 @ 0x43 8013848: 47c8 blx r9 801384a: 3001 adds r0, #1 801384c: d023 beq.n 8013896 <_printf_common+0xae> 801384e: 6823 ldr r3, [r4, #0] 8013850: 6922 ldr r2, [r4, #16] 8013852: f003 0306 and.w r3, r3, #6 8013856: 2b04 cmp r3, #4 8013858: bf14 ite ne 801385a: 2500 movne r5, #0 801385c: 6833 ldreq r3, [r6, #0] 801385e: f04f 0600 mov.w r6, #0 8013862: bf08 it eq 8013864: 68e5 ldreq r5, [r4, #12] 8013866: f104 041a add.w r4, r4, #26 801386a: bf08 it eq 801386c: 1aed subeq r5, r5, r3 801386e: f854 3c12 ldr.w r3, [r4, #-18] 8013872: bf08 it eq 8013874: ea25 75e5 biceq.w r5, r5, r5, asr #31 8013878: 4293 cmp r3, r2 801387a: bfc4 itt gt 801387c: 1a9b subgt r3, r3, r2 801387e: 18ed addgt r5, r5, r3 8013880: 42b5 cmp r5, r6 8013882: d11a bne.n 80138ba <_printf_common+0xd2> 8013884: 2000 movs r0, #0 8013886: e008 b.n 801389a <_printf_common+0xb2> 8013888: 2301 movs r3, #1 801388a: 4652 mov r2, sl 801388c: 4641 mov r1, r8 801388e: 4638 mov r0, r7 8013890: 47c8 blx r9 8013892: 3001 adds r0, #1 8013894: d103 bne.n 801389e <_printf_common+0xb6> 8013896: f04f 30ff mov.w r0, #4294967295 801389a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801389e: 3501 adds r5, #1 80138a0: e7c1 b.n 8013826 <_printf_common+0x3e> 80138a2: 2030 movs r0, #48 @ 0x30 80138a4: 18e1 adds r1, r4, r3 80138a6: f881 0043 strb.w r0, [r1, #67] @ 0x43 80138aa: 1c5a adds r2, r3, #1 80138ac: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 80138b0: 4422 add r2, r4 80138b2: 3302 adds r3, #2 80138b4: f882 1043 strb.w r1, [r2, #67] @ 0x43 80138b8: e7c2 b.n 8013840 <_printf_common+0x58> 80138ba: 2301 movs r3, #1 80138bc: 4622 mov r2, r4 80138be: 4641 mov r1, r8 80138c0: 4638 mov r0, r7 80138c2: 47c8 blx r9 80138c4: 3001 adds r0, #1 80138c6: d0e6 beq.n 8013896 <_printf_common+0xae> 80138c8: 3601 adds r6, #1 80138ca: e7d9 b.n 8013880 <_printf_common+0x98> 080138cc <_printf_i>: 80138cc: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 80138d0: 7e0f ldrb r7, [r1, #24] 80138d2: 4691 mov r9, r2 80138d4: 2f78 cmp r7, #120 @ 0x78 80138d6: 4680 mov r8, r0 80138d8: 460c mov r4, r1 80138da: 469a mov sl, r3 80138dc: 9e0c ldr r6, [sp, #48] @ 0x30 80138de: f101 0243 add.w r2, r1, #67 @ 0x43 80138e2: d807 bhi.n 80138f4 <_printf_i+0x28> 80138e4: 2f62 cmp r7, #98 @ 0x62 80138e6: d80a bhi.n 80138fe <_printf_i+0x32> 80138e8: 2f00 cmp r7, #0 80138ea: f000 80d1 beq.w 8013a90 <_printf_i+0x1c4> 80138ee: 2f58 cmp r7, #88 @ 0x58 80138f0: f000 80b8 beq.w 8013a64 <_printf_i+0x198> 80138f4: f104 0642 add.w r6, r4, #66 @ 0x42 80138f8: f884 7042 strb.w r7, [r4, #66] @ 0x42 80138fc: e03a b.n 8013974 <_printf_i+0xa8> 80138fe: f1a7 0363 sub.w r3, r7, #99 @ 0x63 8013902: 2b15 cmp r3, #21 8013904: d8f6 bhi.n 80138f4 <_printf_i+0x28> 8013906: a101 add r1, pc, #4 @ (adr r1, 801390c <_printf_i+0x40>) 8013908: f851 f023 ldr.w pc, [r1, r3, lsl #2] 801390c: 08013965 .word 0x08013965 8013910: 08013979 .word 0x08013979 8013914: 080138f5 .word 0x080138f5 8013918: 080138f5 .word 0x080138f5 801391c: 080138f5 .word 0x080138f5 8013920: 080138f5 .word 0x080138f5 8013924: 08013979 .word 0x08013979 8013928: 080138f5 .word 0x080138f5 801392c: 080138f5 .word 0x080138f5 8013930: 080138f5 .word 0x080138f5 8013934: 080138f5 .word 0x080138f5 8013938: 08013a77 .word 0x08013a77 801393c: 080139a3 .word 0x080139a3 8013940: 08013a31 .word 0x08013a31 8013944: 080138f5 .word 0x080138f5 8013948: 080138f5 .word 0x080138f5 801394c: 08013a99 .word 0x08013a99 8013950: 080138f5 .word 0x080138f5 8013954: 080139a3 .word 0x080139a3 8013958: 080138f5 .word 0x080138f5 801395c: 080138f5 .word 0x080138f5 8013960: 08013a39 .word 0x08013a39 8013964: 6833 ldr r3, [r6, #0] 8013966: 1d1a adds r2, r3, #4 8013968: 681b ldr r3, [r3, #0] 801396a: 6032 str r2, [r6, #0] 801396c: f104 0642 add.w r6, r4, #66 @ 0x42 8013970: f884 3042 strb.w r3, [r4, #66] @ 0x42 8013974: 2301 movs r3, #1 8013976: e09c b.n 8013ab2 <_printf_i+0x1e6> 8013978: 6833 ldr r3, [r6, #0] 801397a: 6820 ldr r0, [r4, #0] 801397c: 1d19 adds r1, r3, #4 801397e: 6031 str r1, [r6, #0] 8013980: 0606 lsls r6, r0, #24 8013982: d501 bpl.n 8013988 <_printf_i+0xbc> 8013984: 681d ldr r5, [r3, #0] 8013986: e003 b.n 8013990 <_printf_i+0xc4> 8013988: 0645 lsls r5, r0, #25 801398a: d5fb bpl.n 8013984 <_printf_i+0xb8> 801398c: f9b3 5000 ldrsh.w r5, [r3] 8013990: 2d00 cmp r5, #0 8013992: da03 bge.n 801399c <_printf_i+0xd0> 8013994: 232d movs r3, #45 @ 0x2d 8013996: 426d negs r5, r5 8013998: f884 3043 strb.w r3, [r4, #67] @ 0x43 801399c: 230a movs r3, #10 801399e: 4858 ldr r0, [pc, #352] @ (8013b00 <_printf_i+0x234>) 80139a0: e011 b.n 80139c6 <_printf_i+0xfa> 80139a2: 6821 ldr r1, [r4, #0] 80139a4: 6833 ldr r3, [r6, #0] 80139a6: 0608 lsls r0, r1, #24 80139a8: f853 5b04 ldr.w r5, [r3], #4 80139ac: d402 bmi.n 80139b4 <_printf_i+0xe8> 80139ae: 0649 lsls r1, r1, #25 80139b0: bf48 it mi 80139b2: b2ad uxthmi r5, r5 80139b4: 2f6f cmp r7, #111 @ 0x6f 80139b6: 6033 str r3, [r6, #0] 80139b8: bf14 ite ne 80139ba: 230a movne r3, #10 80139bc: 2308 moveq r3, #8 80139be: 4850 ldr r0, [pc, #320] @ (8013b00 <_printf_i+0x234>) 80139c0: 2100 movs r1, #0 80139c2: f884 1043 strb.w r1, [r4, #67] @ 0x43 80139c6: 6866 ldr r6, [r4, #4] 80139c8: 2e00 cmp r6, #0 80139ca: 60a6 str r6, [r4, #8] 80139cc: db05 blt.n 80139da <_printf_i+0x10e> 80139ce: 6821 ldr r1, [r4, #0] 80139d0: 432e orrs r6, r5 80139d2: f021 0104 bic.w r1, r1, #4 80139d6: 6021 str r1, [r4, #0] 80139d8: d04b beq.n 8013a72 <_printf_i+0x1a6> 80139da: 4616 mov r6, r2 80139dc: fbb5 f1f3 udiv r1, r5, r3 80139e0: fb03 5711 mls r7, r3, r1, r5 80139e4: 5dc7 ldrb r7, [r0, r7] 80139e6: f806 7d01 strb.w r7, [r6, #-1]! 80139ea: 462f mov r7, r5 80139ec: 42bb cmp r3, r7 80139ee: 460d mov r5, r1 80139f0: d9f4 bls.n 80139dc <_printf_i+0x110> 80139f2: 2b08 cmp r3, #8 80139f4: d10b bne.n 8013a0e <_printf_i+0x142> 80139f6: 6823 ldr r3, [r4, #0] 80139f8: 07df lsls r7, r3, #31 80139fa: d508 bpl.n 8013a0e <_printf_i+0x142> 80139fc: 6923 ldr r3, [r4, #16] 80139fe: 6861 ldr r1, [r4, #4] 8013a00: 4299 cmp r1, r3 8013a02: bfde ittt le 8013a04: 2330 movle r3, #48 @ 0x30 8013a06: f806 3c01 strble.w r3, [r6, #-1] 8013a0a: f106 36ff addle.w r6, r6, #4294967295 8013a0e: 1b92 subs r2, r2, r6 8013a10: 6122 str r2, [r4, #16] 8013a12: 464b mov r3, r9 8013a14: 4621 mov r1, r4 8013a16: 4640 mov r0, r8 8013a18: f8cd a000 str.w sl, [sp] 8013a1c: aa03 add r2, sp, #12 8013a1e: f7ff fee3 bl 80137e8 <_printf_common> 8013a22: 3001 adds r0, #1 8013a24: d14a bne.n 8013abc <_printf_i+0x1f0> 8013a26: f04f 30ff mov.w r0, #4294967295 8013a2a: b004 add sp, #16 8013a2c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8013a30: 6823 ldr r3, [r4, #0] 8013a32: f043 0320 orr.w r3, r3, #32 8013a36: 6023 str r3, [r4, #0] 8013a38: 2778 movs r7, #120 @ 0x78 8013a3a: 4832 ldr r0, [pc, #200] @ (8013b04 <_printf_i+0x238>) 8013a3c: f884 7045 strb.w r7, [r4, #69] @ 0x45 8013a40: 6823 ldr r3, [r4, #0] 8013a42: 6831 ldr r1, [r6, #0] 8013a44: 061f lsls r7, r3, #24 8013a46: f851 5b04 ldr.w r5, [r1], #4 8013a4a: d402 bmi.n 8013a52 <_printf_i+0x186> 8013a4c: 065f lsls r7, r3, #25 8013a4e: bf48 it mi 8013a50: b2ad uxthmi r5, r5 8013a52: 6031 str r1, [r6, #0] 8013a54: 07d9 lsls r1, r3, #31 8013a56: bf44 itt mi 8013a58: f043 0320 orrmi.w r3, r3, #32 8013a5c: 6023 strmi r3, [r4, #0] 8013a5e: b11d cbz r5, 8013a68 <_printf_i+0x19c> 8013a60: 2310 movs r3, #16 8013a62: e7ad b.n 80139c0 <_printf_i+0xf4> 8013a64: 4826 ldr r0, [pc, #152] @ (8013b00 <_printf_i+0x234>) 8013a66: e7e9 b.n 8013a3c <_printf_i+0x170> 8013a68: 6823 ldr r3, [r4, #0] 8013a6a: f023 0320 bic.w r3, r3, #32 8013a6e: 6023 str r3, [r4, #0] 8013a70: e7f6 b.n 8013a60 <_printf_i+0x194> 8013a72: 4616 mov r6, r2 8013a74: e7bd b.n 80139f2 <_printf_i+0x126> 8013a76: 6833 ldr r3, [r6, #0] 8013a78: 6825 ldr r5, [r4, #0] 8013a7a: 1d18 adds r0, r3, #4 8013a7c: 6961 ldr r1, [r4, #20] 8013a7e: 6030 str r0, [r6, #0] 8013a80: 062e lsls r6, r5, #24 8013a82: 681b ldr r3, [r3, #0] 8013a84: d501 bpl.n 8013a8a <_printf_i+0x1be> 8013a86: 6019 str r1, [r3, #0] 8013a88: e002 b.n 8013a90 <_printf_i+0x1c4> 8013a8a: 0668 lsls r0, r5, #25 8013a8c: d5fb bpl.n 8013a86 <_printf_i+0x1ba> 8013a8e: 8019 strh r1, [r3, #0] 8013a90: 2300 movs r3, #0 8013a92: 4616 mov r6, r2 8013a94: 6123 str r3, [r4, #16] 8013a96: e7bc b.n 8013a12 <_printf_i+0x146> 8013a98: 6833 ldr r3, [r6, #0] 8013a9a: 2100 movs r1, #0 8013a9c: 1d1a adds r2, r3, #4 8013a9e: 6032 str r2, [r6, #0] 8013aa0: 681e ldr r6, [r3, #0] 8013aa2: 6862 ldr r2, [r4, #4] 8013aa4: 4630 mov r0, r6 8013aa6: f000 f995 bl 8013dd4 8013aaa: b108 cbz r0, 8013ab0 <_printf_i+0x1e4> 8013aac: 1b80 subs r0, r0, r6 8013aae: 6060 str r0, [r4, #4] 8013ab0: 6863 ldr r3, [r4, #4] 8013ab2: 6123 str r3, [r4, #16] 8013ab4: 2300 movs r3, #0 8013ab6: f884 3043 strb.w r3, [r4, #67] @ 0x43 8013aba: e7aa b.n 8013a12 <_printf_i+0x146> 8013abc: 4632 mov r2, r6 8013abe: 4649 mov r1, r9 8013ac0: 4640 mov r0, r8 8013ac2: 6923 ldr r3, [r4, #16] 8013ac4: 47d0 blx sl 8013ac6: 3001 adds r0, #1 8013ac8: d0ad beq.n 8013a26 <_printf_i+0x15a> 8013aca: 6823 ldr r3, [r4, #0] 8013acc: 079b lsls r3, r3, #30 8013ace: d413 bmi.n 8013af8 <_printf_i+0x22c> 8013ad0: 68e0 ldr r0, [r4, #12] 8013ad2: 9b03 ldr r3, [sp, #12] 8013ad4: 4298 cmp r0, r3 8013ad6: bfb8 it lt 8013ad8: 4618 movlt r0, r3 8013ada: e7a6 b.n 8013a2a <_printf_i+0x15e> 8013adc: 2301 movs r3, #1 8013ade: 4632 mov r2, r6 8013ae0: 4649 mov r1, r9 8013ae2: 4640 mov r0, r8 8013ae4: 47d0 blx sl 8013ae6: 3001 adds r0, #1 8013ae8: d09d beq.n 8013a26 <_printf_i+0x15a> 8013aea: 3501 adds r5, #1 8013aec: 68e3 ldr r3, [r4, #12] 8013aee: 9903 ldr r1, [sp, #12] 8013af0: 1a5b subs r3, r3, r1 8013af2: 42ab cmp r3, r5 8013af4: dcf2 bgt.n 8013adc <_printf_i+0x210> 8013af6: e7eb b.n 8013ad0 <_printf_i+0x204> 8013af8: 2500 movs r5, #0 8013afa: f104 0619 add.w r6, r4, #25 8013afe: e7f5 b.n 8013aec <_printf_i+0x220> 8013b00: 08014405 .word 0x08014405 8013b04: 08014416 .word 0x08014416 08013b08 <__sflush_r>: 8013b08: f9b1 200c ldrsh.w r2, [r1, #12] 8013b0c: b5f8 push {r3, r4, r5, r6, r7, lr} 8013b0e: 0716 lsls r6, r2, #28 8013b10: 4605 mov r5, r0 8013b12: 460c mov r4, r1 8013b14: d454 bmi.n 8013bc0 <__sflush_r+0xb8> 8013b16: 684b ldr r3, [r1, #4] 8013b18: 2b00 cmp r3, #0 8013b1a: dc02 bgt.n 8013b22 <__sflush_r+0x1a> 8013b1c: 6c0b ldr r3, [r1, #64] @ 0x40 8013b1e: 2b00 cmp r3, #0 8013b20: dd48 ble.n 8013bb4 <__sflush_r+0xac> 8013b22: 6ae6 ldr r6, [r4, #44] @ 0x2c 8013b24: 2e00 cmp r6, #0 8013b26: d045 beq.n 8013bb4 <__sflush_r+0xac> 8013b28: 2300 movs r3, #0 8013b2a: f412 5280 ands.w r2, r2, #4096 @ 0x1000 8013b2e: 682f ldr r7, [r5, #0] 8013b30: 6a21 ldr r1, [r4, #32] 8013b32: 602b str r3, [r5, #0] 8013b34: d030 beq.n 8013b98 <__sflush_r+0x90> 8013b36: 6d62 ldr r2, [r4, #84] @ 0x54 8013b38: 89a3 ldrh r3, [r4, #12] 8013b3a: 0759 lsls r1, r3, #29 8013b3c: d505 bpl.n 8013b4a <__sflush_r+0x42> 8013b3e: 6863 ldr r3, [r4, #4] 8013b40: 1ad2 subs r2, r2, r3 8013b42: 6b63 ldr r3, [r4, #52] @ 0x34 8013b44: b10b cbz r3, 8013b4a <__sflush_r+0x42> 8013b46: 6c23 ldr r3, [r4, #64] @ 0x40 8013b48: 1ad2 subs r2, r2, r3 8013b4a: 2300 movs r3, #0 8013b4c: 4628 mov r0, r5 8013b4e: 6ae6 ldr r6, [r4, #44] @ 0x2c 8013b50: 6a21 ldr r1, [r4, #32] 8013b52: 47b0 blx r6 8013b54: 1c43 adds r3, r0, #1 8013b56: 89a3 ldrh r3, [r4, #12] 8013b58: d106 bne.n 8013b68 <__sflush_r+0x60> 8013b5a: 6829 ldr r1, [r5, #0] 8013b5c: 291d cmp r1, #29 8013b5e: d82b bhi.n 8013bb8 <__sflush_r+0xb0> 8013b60: 4a28 ldr r2, [pc, #160] @ (8013c04 <__sflush_r+0xfc>) 8013b62: 40ca lsrs r2, r1 8013b64: 07d6 lsls r6, r2, #31 8013b66: d527 bpl.n 8013bb8 <__sflush_r+0xb0> 8013b68: 2200 movs r2, #0 8013b6a: 6062 str r2, [r4, #4] 8013b6c: 6922 ldr r2, [r4, #16] 8013b6e: 04d9 lsls r1, r3, #19 8013b70: 6022 str r2, [r4, #0] 8013b72: d504 bpl.n 8013b7e <__sflush_r+0x76> 8013b74: 1c42 adds r2, r0, #1 8013b76: d101 bne.n 8013b7c <__sflush_r+0x74> 8013b78: 682b ldr r3, [r5, #0] 8013b7a: b903 cbnz r3, 8013b7e <__sflush_r+0x76> 8013b7c: 6560 str r0, [r4, #84] @ 0x54 8013b7e: 6b61 ldr r1, [r4, #52] @ 0x34 8013b80: 602f str r7, [r5, #0] 8013b82: b1b9 cbz r1, 8013bb4 <__sflush_r+0xac> 8013b84: f104 0344 add.w r3, r4, #68 @ 0x44 8013b88: 4299 cmp r1, r3 8013b8a: d002 beq.n 8013b92 <__sflush_r+0x8a> 8013b8c: 4628 mov r0, r5 8013b8e: f7ff fa9d bl 80130cc <_free_r> 8013b92: 2300 movs r3, #0 8013b94: 6363 str r3, [r4, #52] @ 0x34 8013b96: e00d b.n 8013bb4 <__sflush_r+0xac> 8013b98: 2301 movs r3, #1 8013b9a: 4628 mov r0, r5 8013b9c: 47b0 blx r6 8013b9e: 4602 mov r2, r0 8013ba0: 1c50 adds r0, r2, #1 8013ba2: d1c9 bne.n 8013b38 <__sflush_r+0x30> 8013ba4: 682b ldr r3, [r5, #0] 8013ba6: 2b00 cmp r3, #0 8013ba8: d0c6 beq.n 8013b38 <__sflush_r+0x30> 8013baa: 2b1d cmp r3, #29 8013bac: d001 beq.n 8013bb2 <__sflush_r+0xaa> 8013bae: 2b16 cmp r3, #22 8013bb0: d11d bne.n 8013bee <__sflush_r+0xe6> 8013bb2: 602f str r7, [r5, #0] 8013bb4: 2000 movs r0, #0 8013bb6: e021 b.n 8013bfc <__sflush_r+0xf4> 8013bb8: f043 0340 orr.w r3, r3, #64 @ 0x40 8013bbc: b21b sxth r3, r3 8013bbe: e01a b.n 8013bf6 <__sflush_r+0xee> 8013bc0: 690f ldr r7, [r1, #16] 8013bc2: 2f00 cmp r7, #0 8013bc4: d0f6 beq.n 8013bb4 <__sflush_r+0xac> 8013bc6: 0793 lsls r3, r2, #30 8013bc8: bf18 it ne 8013bca: 2300 movne r3, #0 8013bcc: 680e ldr r6, [r1, #0] 8013bce: bf08 it eq 8013bd0: 694b ldreq r3, [r1, #20] 8013bd2: 1bf6 subs r6, r6, r7 8013bd4: 600f str r7, [r1, #0] 8013bd6: 608b str r3, [r1, #8] 8013bd8: 2e00 cmp r6, #0 8013bda: ddeb ble.n 8013bb4 <__sflush_r+0xac> 8013bdc: 4633 mov r3, r6 8013bde: 463a mov r2, r7 8013be0: 4628 mov r0, r5 8013be2: 6a21 ldr r1, [r4, #32] 8013be4: f8d4 c028 ldr.w ip, [r4, #40] @ 0x28 8013be8: 47e0 blx ip 8013bea: 2800 cmp r0, #0 8013bec: dc07 bgt.n 8013bfe <__sflush_r+0xf6> 8013bee: f9b4 300c ldrsh.w r3, [r4, #12] 8013bf2: f043 0340 orr.w r3, r3, #64 @ 0x40 8013bf6: f04f 30ff mov.w r0, #4294967295 8013bfa: 81a3 strh r3, [r4, #12] 8013bfc: bdf8 pop {r3, r4, r5, r6, r7, pc} 8013bfe: 4407 add r7, r0 8013c00: 1a36 subs r6, r6, r0 8013c02: e7e9 b.n 8013bd8 <__sflush_r+0xd0> 8013c04: 20400001 .word 0x20400001 08013c08 <_fflush_r>: 8013c08: b538 push {r3, r4, r5, lr} 8013c0a: 690b ldr r3, [r1, #16] 8013c0c: 4605 mov r5, r0 8013c0e: 460c mov r4, r1 8013c10: b913 cbnz r3, 8013c18 <_fflush_r+0x10> 8013c12: 2500 movs r5, #0 8013c14: 4628 mov r0, r5 8013c16: bd38 pop {r3, r4, r5, pc} 8013c18: b118 cbz r0, 8013c22 <_fflush_r+0x1a> 8013c1a: 6a03 ldr r3, [r0, #32] 8013c1c: b90b cbnz r3, 8013c22 <_fflush_r+0x1a> 8013c1e: f7ff f903 bl 8012e28 <__sinit> 8013c22: f9b4 300c ldrsh.w r3, [r4, #12] 8013c26: 2b00 cmp r3, #0 8013c28: d0f3 beq.n 8013c12 <_fflush_r+0xa> 8013c2a: 6e62 ldr r2, [r4, #100] @ 0x64 8013c2c: 07d0 lsls r0, r2, #31 8013c2e: d404 bmi.n 8013c3a <_fflush_r+0x32> 8013c30: 0599 lsls r1, r3, #22 8013c32: d402 bmi.n 8013c3a <_fflush_r+0x32> 8013c34: 6da0 ldr r0, [r4, #88] @ 0x58 8013c36: f7ff fa38 bl 80130aa <__retarget_lock_acquire_recursive> 8013c3a: 4628 mov r0, r5 8013c3c: 4621 mov r1, r4 8013c3e: f7ff ff63 bl 8013b08 <__sflush_r> 8013c42: 6e63 ldr r3, [r4, #100] @ 0x64 8013c44: 4605 mov r5, r0 8013c46: 07da lsls r2, r3, #31 8013c48: d4e4 bmi.n 8013c14 <_fflush_r+0xc> 8013c4a: 89a3 ldrh r3, [r4, #12] 8013c4c: 059b lsls r3, r3, #22 8013c4e: d4e1 bmi.n 8013c14 <_fflush_r+0xc> 8013c50: 6da0 ldr r0, [r4, #88] @ 0x58 8013c52: f7ff fa2b bl 80130ac <__retarget_lock_release_recursive> 8013c56: e7dd b.n 8013c14 <_fflush_r+0xc> 08013c58 <__swbuf_r>: 8013c58: b5f8 push {r3, r4, r5, r6, r7, lr} 8013c5a: 460e mov r6, r1 8013c5c: 4614 mov r4, r2 8013c5e: 4605 mov r5, r0 8013c60: b118 cbz r0, 8013c6a <__swbuf_r+0x12> 8013c62: 6a03 ldr r3, [r0, #32] 8013c64: b90b cbnz r3, 8013c6a <__swbuf_r+0x12> 8013c66: f7ff f8df bl 8012e28 <__sinit> 8013c6a: 69a3 ldr r3, [r4, #24] 8013c6c: 60a3 str r3, [r4, #8] 8013c6e: 89a3 ldrh r3, [r4, #12] 8013c70: 071a lsls r2, r3, #28 8013c72: d501 bpl.n 8013c78 <__swbuf_r+0x20> 8013c74: 6923 ldr r3, [r4, #16] 8013c76: b943 cbnz r3, 8013c8a <__swbuf_r+0x32> 8013c78: 4621 mov r1, r4 8013c7a: 4628 mov r0, r5 8013c7c: f000 f82a bl 8013cd4 <__swsetup_r> 8013c80: b118 cbz r0, 8013c8a <__swbuf_r+0x32> 8013c82: f04f 37ff mov.w r7, #4294967295 8013c86: 4638 mov r0, r7 8013c88: bdf8 pop {r3, r4, r5, r6, r7, pc} 8013c8a: 6823 ldr r3, [r4, #0] 8013c8c: 6922 ldr r2, [r4, #16] 8013c8e: b2f6 uxtb r6, r6 8013c90: 1a98 subs r0, r3, r2 8013c92: 6963 ldr r3, [r4, #20] 8013c94: 4637 mov r7, r6 8013c96: 4283 cmp r3, r0 8013c98: dc05 bgt.n 8013ca6 <__swbuf_r+0x4e> 8013c9a: 4621 mov r1, r4 8013c9c: 4628 mov r0, r5 8013c9e: f7ff ffb3 bl 8013c08 <_fflush_r> 8013ca2: 2800 cmp r0, #0 8013ca4: d1ed bne.n 8013c82 <__swbuf_r+0x2a> 8013ca6: 68a3 ldr r3, [r4, #8] 8013ca8: 3b01 subs r3, #1 8013caa: 60a3 str r3, [r4, #8] 8013cac: 6823 ldr r3, [r4, #0] 8013cae: 1c5a adds r2, r3, #1 8013cb0: 6022 str r2, [r4, #0] 8013cb2: 701e strb r6, [r3, #0] 8013cb4: 6962 ldr r2, [r4, #20] 8013cb6: 1c43 adds r3, r0, #1 8013cb8: 429a cmp r2, r3 8013cba: d004 beq.n 8013cc6 <__swbuf_r+0x6e> 8013cbc: 89a3 ldrh r3, [r4, #12] 8013cbe: 07db lsls r3, r3, #31 8013cc0: d5e1 bpl.n 8013c86 <__swbuf_r+0x2e> 8013cc2: 2e0a cmp r6, #10 8013cc4: d1df bne.n 8013c86 <__swbuf_r+0x2e> 8013cc6: 4621 mov r1, r4 8013cc8: 4628 mov r0, r5 8013cca: f7ff ff9d bl 8013c08 <_fflush_r> 8013cce: 2800 cmp r0, #0 8013cd0: d0d9 beq.n 8013c86 <__swbuf_r+0x2e> 8013cd2: e7d6 b.n 8013c82 <__swbuf_r+0x2a> 08013cd4 <__swsetup_r>: 8013cd4: b538 push {r3, r4, r5, lr} 8013cd6: 4b29 ldr r3, [pc, #164] @ (8013d7c <__swsetup_r+0xa8>) 8013cd8: 4605 mov r5, r0 8013cda: 6818 ldr r0, [r3, #0] 8013cdc: 460c mov r4, r1 8013cde: b118 cbz r0, 8013ce8 <__swsetup_r+0x14> 8013ce0: 6a03 ldr r3, [r0, #32] 8013ce2: b90b cbnz r3, 8013ce8 <__swsetup_r+0x14> 8013ce4: f7ff f8a0 bl 8012e28 <__sinit> 8013ce8: f9b4 300c ldrsh.w r3, [r4, #12] 8013cec: 0719 lsls r1, r3, #28 8013cee: d422 bmi.n 8013d36 <__swsetup_r+0x62> 8013cf0: 06da lsls r2, r3, #27 8013cf2: d407 bmi.n 8013d04 <__swsetup_r+0x30> 8013cf4: 2209 movs r2, #9 8013cf6: 602a str r2, [r5, #0] 8013cf8: f043 0340 orr.w r3, r3, #64 @ 0x40 8013cfc: f04f 30ff mov.w r0, #4294967295 8013d00: 81a3 strh r3, [r4, #12] 8013d02: e033 b.n 8013d6c <__swsetup_r+0x98> 8013d04: 0758 lsls r0, r3, #29 8013d06: d512 bpl.n 8013d2e <__swsetup_r+0x5a> 8013d08: 6b61 ldr r1, [r4, #52] @ 0x34 8013d0a: b141 cbz r1, 8013d1e <__swsetup_r+0x4a> 8013d0c: f104 0344 add.w r3, r4, #68 @ 0x44 8013d10: 4299 cmp r1, r3 8013d12: d002 beq.n 8013d1a <__swsetup_r+0x46> 8013d14: 4628 mov r0, r5 8013d16: f7ff f9d9 bl 80130cc <_free_r> 8013d1a: 2300 movs r3, #0 8013d1c: 6363 str r3, [r4, #52] @ 0x34 8013d1e: 89a3 ldrh r3, [r4, #12] 8013d20: f023 0324 bic.w r3, r3, #36 @ 0x24 8013d24: 81a3 strh r3, [r4, #12] 8013d26: 2300 movs r3, #0 8013d28: 6063 str r3, [r4, #4] 8013d2a: 6923 ldr r3, [r4, #16] 8013d2c: 6023 str r3, [r4, #0] 8013d2e: 89a3 ldrh r3, [r4, #12] 8013d30: f043 0308 orr.w r3, r3, #8 8013d34: 81a3 strh r3, [r4, #12] 8013d36: 6923 ldr r3, [r4, #16] 8013d38: b94b cbnz r3, 8013d4e <__swsetup_r+0x7a> 8013d3a: 89a3 ldrh r3, [r4, #12] 8013d3c: f403 7320 and.w r3, r3, #640 @ 0x280 8013d40: f5b3 7f00 cmp.w r3, #512 @ 0x200 8013d44: d003 beq.n 8013d4e <__swsetup_r+0x7a> 8013d46: 4621 mov r1, r4 8013d48: 4628 mov r0, r5 8013d4a: f000 f8a4 bl 8013e96 <__smakebuf_r> 8013d4e: f9b4 300c ldrsh.w r3, [r4, #12] 8013d52: f013 0201 ands.w r2, r3, #1 8013d56: d00a beq.n 8013d6e <__swsetup_r+0x9a> 8013d58: 2200 movs r2, #0 8013d5a: 60a2 str r2, [r4, #8] 8013d5c: 6962 ldr r2, [r4, #20] 8013d5e: 4252 negs r2, r2 8013d60: 61a2 str r2, [r4, #24] 8013d62: 6922 ldr r2, [r4, #16] 8013d64: b942 cbnz r2, 8013d78 <__swsetup_r+0xa4> 8013d66: f013 0080 ands.w r0, r3, #128 @ 0x80 8013d6a: d1c5 bne.n 8013cf8 <__swsetup_r+0x24> 8013d6c: bd38 pop {r3, r4, r5, pc} 8013d6e: 0799 lsls r1, r3, #30 8013d70: bf58 it pl 8013d72: 6962 ldrpl r2, [r4, #20] 8013d74: 60a2 str r2, [r4, #8] 8013d76: e7f4 b.n 8013d62 <__swsetup_r+0x8e> 8013d78: 2000 movs r0, #0 8013d7a: e7f7 b.n 8013d6c <__swsetup_r+0x98> 8013d7c: 20000084 .word 0x20000084 08013d80 : 8013d80: 4288 cmp r0, r1 8013d82: b510 push {r4, lr} 8013d84: eb01 0402 add.w r4, r1, r2 8013d88: d902 bls.n 8013d90 8013d8a: 4284 cmp r4, r0 8013d8c: 4623 mov r3, r4 8013d8e: d807 bhi.n 8013da0 8013d90: 1e43 subs r3, r0, #1 8013d92: 42a1 cmp r1, r4 8013d94: d008 beq.n 8013da8 8013d96: f811 2b01 ldrb.w r2, [r1], #1 8013d9a: f803 2f01 strb.w r2, [r3, #1]! 8013d9e: e7f8 b.n 8013d92 8013da0: 4601 mov r1, r0 8013da2: 4402 add r2, r0 8013da4: 428a cmp r2, r1 8013da6: d100 bne.n 8013daa 8013da8: bd10 pop {r4, pc} 8013daa: f813 4d01 ldrb.w r4, [r3, #-1]! 8013dae: f802 4d01 strb.w r4, [r2, #-1]! 8013db2: e7f7 b.n 8013da4 08013db4 <_sbrk_r>: 8013db4: b538 push {r3, r4, r5, lr} 8013db6: 2300 movs r3, #0 8013db8: 4d05 ldr r5, [pc, #20] @ (8013dd0 <_sbrk_r+0x1c>) 8013dba: 4604 mov r4, r0 8013dbc: 4608 mov r0, r1 8013dbe: 602b str r3, [r5, #0] 8013dc0: f7f9 f93a bl 800d038 <_sbrk> 8013dc4: 1c43 adds r3, r0, #1 8013dc6: d102 bne.n 8013dce <_sbrk_r+0x1a> 8013dc8: 682b ldr r3, [r5, #0] 8013dca: b103 cbz r3, 8013dce <_sbrk_r+0x1a> 8013dcc: 6023 str r3, [r4, #0] 8013dce: bd38 pop {r3, r4, r5, pc} 8013dd0: 200011b0 .word 0x200011b0 08013dd4 : 8013dd4: 4603 mov r3, r0 8013dd6: b510 push {r4, lr} 8013dd8: b2c9 uxtb r1, r1 8013dda: 4402 add r2, r0 8013ddc: 4293 cmp r3, r2 8013dde: 4618 mov r0, r3 8013de0: d101 bne.n 8013de6 8013de2: 2000 movs r0, #0 8013de4: e003 b.n 8013dee 8013de6: 7804 ldrb r4, [r0, #0] 8013de8: 3301 adds r3, #1 8013dea: 428c cmp r4, r1 8013dec: d1f6 bne.n 8013ddc 8013dee: bd10 pop {r4, pc} 08013df0 <_realloc_r>: 8013df0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8013df4: 4607 mov r7, r0 8013df6: 4614 mov r4, r2 8013df8: 460d mov r5, r1 8013dfa: b921 cbnz r1, 8013e06 <_realloc_r+0x16> 8013dfc: 4611 mov r1, r2 8013dfe: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8013e02: f7ff b9cd b.w 80131a0 <_malloc_r> 8013e06: b92a cbnz r2, 8013e14 <_realloc_r+0x24> 8013e08: f7ff f960 bl 80130cc <_free_r> 8013e0c: 4625 mov r5, r4 8013e0e: 4628 mov r0, r5 8013e10: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8013e14: f000 f89e bl 8013f54 <_malloc_usable_size_r> 8013e18: 4284 cmp r4, r0 8013e1a: 4606 mov r6, r0 8013e1c: d802 bhi.n 8013e24 <_realloc_r+0x34> 8013e1e: ebb4 0f50 cmp.w r4, r0, lsr #1 8013e22: d8f4 bhi.n 8013e0e <_realloc_r+0x1e> 8013e24: 4621 mov r1, r4 8013e26: 4638 mov r0, r7 8013e28: f7ff f9ba bl 80131a0 <_malloc_r> 8013e2c: 4680 mov r8, r0 8013e2e: b908 cbnz r0, 8013e34 <_realloc_r+0x44> 8013e30: 4645 mov r5, r8 8013e32: e7ec b.n 8013e0e <_realloc_r+0x1e> 8013e34: 42b4 cmp r4, r6 8013e36: 4622 mov r2, r4 8013e38: 4629 mov r1, r5 8013e3a: bf28 it cs 8013e3c: 4632 movcs r2, r6 8013e3e: f7ff f936 bl 80130ae 8013e42: 4629 mov r1, r5 8013e44: 4638 mov r0, r7 8013e46: f7ff f941 bl 80130cc <_free_r> 8013e4a: e7f1 b.n 8013e30 <_realloc_r+0x40> 08013e4c <__swhatbuf_r>: 8013e4c: b570 push {r4, r5, r6, lr} 8013e4e: 460c mov r4, r1 8013e50: f9b1 100e ldrsh.w r1, [r1, #14] 8013e54: 4615 mov r5, r2 8013e56: 2900 cmp r1, #0 8013e58: 461e mov r6, r3 8013e5a: b096 sub sp, #88 @ 0x58 8013e5c: da0c bge.n 8013e78 <__swhatbuf_r+0x2c> 8013e5e: 89a3 ldrh r3, [r4, #12] 8013e60: 2100 movs r1, #0 8013e62: f013 0f80 tst.w r3, #128 @ 0x80 8013e66: bf14 ite ne 8013e68: 2340 movne r3, #64 @ 0x40 8013e6a: f44f 6380 moveq.w r3, #1024 @ 0x400 8013e6e: 2000 movs r0, #0 8013e70: 6031 str r1, [r6, #0] 8013e72: 602b str r3, [r5, #0] 8013e74: b016 add sp, #88 @ 0x58 8013e76: bd70 pop {r4, r5, r6, pc} 8013e78: 466a mov r2, sp 8013e7a: f000 f849 bl 8013f10 <_fstat_r> 8013e7e: 2800 cmp r0, #0 8013e80: dbed blt.n 8013e5e <__swhatbuf_r+0x12> 8013e82: 9901 ldr r1, [sp, #4] 8013e84: f401 4170 and.w r1, r1, #61440 @ 0xf000 8013e88: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 8013e8c: 4259 negs r1, r3 8013e8e: 4159 adcs r1, r3 8013e90: f44f 6380 mov.w r3, #1024 @ 0x400 8013e94: e7eb b.n 8013e6e <__swhatbuf_r+0x22> 08013e96 <__smakebuf_r>: 8013e96: 898b ldrh r3, [r1, #12] 8013e98: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8013e9a: 079d lsls r5, r3, #30 8013e9c: 4606 mov r6, r0 8013e9e: 460c mov r4, r1 8013ea0: d507 bpl.n 8013eb2 <__smakebuf_r+0x1c> 8013ea2: f104 0347 add.w r3, r4, #71 @ 0x47 8013ea6: 6023 str r3, [r4, #0] 8013ea8: 6123 str r3, [r4, #16] 8013eaa: 2301 movs r3, #1 8013eac: 6163 str r3, [r4, #20] 8013eae: b003 add sp, #12 8013eb0: bdf0 pop {r4, r5, r6, r7, pc} 8013eb2: 466a mov r2, sp 8013eb4: ab01 add r3, sp, #4 8013eb6: f7ff ffc9 bl 8013e4c <__swhatbuf_r> 8013eba: 9f00 ldr r7, [sp, #0] 8013ebc: 4605 mov r5, r0 8013ebe: 4639 mov r1, r7 8013ec0: 4630 mov r0, r6 8013ec2: f7ff f96d bl 80131a0 <_malloc_r> 8013ec6: b948 cbnz r0, 8013edc <__smakebuf_r+0x46> 8013ec8: f9b4 300c ldrsh.w r3, [r4, #12] 8013ecc: 059a lsls r2, r3, #22 8013ece: d4ee bmi.n 8013eae <__smakebuf_r+0x18> 8013ed0: f023 0303 bic.w r3, r3, #3 8013ed4: f043 0302 orr.w r3, r3, #2 8013ed8: 81a3 strh r3, [r4, #12] 8013eda: e7e2 b.n 8013ea2 <__smakebuf_r+0xc> 8013edc: 89a3 ldrh r3, [r4, #12] 8013ede: e9c4 0704 strd r0, r7, [r4, #16] 8013ee2: f043 0380 orr.w r3, r3, #128 @ 0x80 8013ee6: 81a3 strh r3, [r4, #12] 8013ee8: 9b01 ldr r3, [sp, #4] 8013eea: 6020 str r0, [r4, #0] 8013eec: b15b cbz r3, 8013f06 <__smakebuf_r+0x70> 8013eee: 4630 mov r0, r6 8013ef0: f9b4 100e ldrsh.w r1, [r4, #14] 8013ef4: f000 f81e bl 8013f34 <_isatty_r> 8013ef8: b128 cbz r0, 8013f06 <__smakebuf_r+0x70> 8013efa: 89a3 ldrh r3, [r4, #12] 8013efc: f023 0303 bic.w r3, r3, #3 8013f00: f043 0301 orr.w r3, r3, #1 8013f04: 81a3 strh r3, [r4, #12] 8013f06: 89a3 ldrh r3, [r4, #12] 8013f08: 431d orrs r5, r3 8013f0a: 81a5 strh r5, [r4, #12] 8013f0c: e7cf b.n 8013eae <__smakebuf_r+0x18> ... 08013f10 <_fstat_r>: 8013f10: b538 push {r3, r4, r5, lr} 8013f12: 2300 movs r3, #0 8013f14: 4d06 ldr r5, [pc, #24] @ (8013f30 <_fstat_r+0x20>) 8013f16: 4604 mov r4, r0 8013f18: 4608 mov r0, r1 8013f1a: 4611 mov r1, r2 8013f1c: 602b str r3, [r5, #0] 8013f1e: f7f9 f865 bl 800cfec <_fstat> 8013f22: 1c43 adds r3, r0, #1 8013f24: d102 bne.n 8013f2c <_fstat_r+0x1c> 8013f26: 682b ldr r3, [r5, #0] 8013f28: b103 cbz r3, 8013f2c <_fstat_r+0x1c> 8013f2a: 6023 str r3, [r4, #0] 8013f2c: bd38 pop {r3, r4, r5, pc} 8013f2e: bf00 nop 8013f30: 200011b0 .word 0x200011b0 08013f34 <_isatty_r>: 8013f34: b538 push {r3, r4, r5, lr} 8013f36: 2300 movs r3, #0 8013f38: 4d05 ldr r5, [pc, #20] @ (8013f50 <_isatty_r+0x1c>) 8013f3a: 4604 mov r4, r0 8013f3c: 4608 mov r0, r1 8013f3e: 602b str r3, [r5, #0] 8013f40: f7f9 f863 bl 800d00a <_isatty> 8013f44: 1c43 adds r3, r0, #1 8013f46: d102 bne.n 8013f4e <_isatty_r+0x1a> 8013f48: 682b ldr r3, [r5, #0] 8013f4a: b103 cbz r3, 8013f4e <_isatty_r+0x1a> 8013f4c: 6023 str r3, [r4, #0] 8013f4e: bd38 pop {r3, r4, r5, pc} 8013f50: 200011b0 .word 0x200011b0 08013f54 <_malloc_usable_size_r>: 8013f54: f851 3c04 ldr.w r3, [r1, #-4] 8013f58: 1f18 subs r0, r3, #4 8013f5a: 2b00 cmp r3, #0 8013f5c: bfbc itt lt 8013f5e: 580b ldrlt r3, [r1, r0] 8013f60: 18c0 addlt r0, r0, r3 8013f62: 4770 bx lr 08013f64 <_init>: 8013f64: b5f8 push {r3, r4, r5, r6, r7, lr} 8013f66: bf00 nop 8013f68: bcf8 pop {r3, r4, r5, r6, r7} 8013f6a: bc08 pop {r3} 8013f6c: 469e mov lr, r3 8013f6e: 4770 bx lr 08013f70 <_fini>: 8013f70: b5f8 push {r3, r4, r5, r6, r7, lr} 8013f72: bf00 nop 8013f74: bcf8 pop {r3, r4, r5, r6, r7} 8013f76: bc08 pop {r3} 8013f78: 469e mov lr, r3 8013f7a: 4770 bx lr