CCSModuleSW30Web.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001e8 08008000 08008000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000ed14 080081e8 080081e8 000011e8 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000dcc 08016f00 08016f00 0000ff00 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08017ccc 08017ccc 00011258 2**0 CONTENTS 4 .ARM 00000008 08017ccc 08017ccc 00010ccc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 08017cd4 08017cd4 00011258 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08017cd4 08017cd4 00010cd4 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08017cd8 08017cd8 00010cd8 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000258 20000000 08017cdc 00011000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00001380 20000258 08017f34 00011258 2**3 ALLOC 10 ._user_heap_stack 00000600 200015d8 08017f34 000115d8 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 00011258 2**0 CONTENTS, READONLY 12 .debug_info 0001d5e5 00000000 00000000 00011281 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 0000570a 00000000 00000000 0002e866 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_loclists 00000f96 00000000 00000000 00033f70 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_aranges 00001748 00000000 00000000 00034f08 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_rnglists 0000122c 00000000 00000000 00036650 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_macro 00026410 00000000 00000000 0003787c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_line 000217ab 00000000 00000000 0005dc8c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_str 000c9a27 00000000 00000000 0007f437 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .comment 00000043 00000000 00000000 00148e5e 2**0 CONTENTS, READONLY 21 .debug_frame 00006e00 00000000 00000000 00148ea4 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 22 .debug_line_str 0000006e 00000000 00000000 0014fca4 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080081e8 <__do_global_dtors_aux>: 80081e8: b510 push {r4, lr} 80081ea: 4c05 ldr r4, [pc, #20] @ (8008200 <__do_global_dtors_aux+0x18>) 80081ec: 7823 ldrb r3, [r4, #0] 80081ee: b933 cbnz r3, 80081fe <__do_global_dtors_aux+0x16> 80081f0: 4b04 ldr r3, [pc, #16] @ (8008204 <__do_global_dtors_aux+0x1c>) 80081f2: b113 cbz r3, 80081fa <__do_global_dtors_aux+0x12> 80081f4: 4804 ldr r0, [pc, #16] @ (8008208 <__do_global_dtors_aux+0x20>) 80081f6: f3af 8000 nop.w 80081fa: 2301 movs r3, #1 80081fc: 7023 strb r3, [r4, #0] 80081fe: bd10 pop {r4, pc} 8008200: 20000258 .word 0x20000258 8008204: 00000000 .word 0x00000000 8008208: 08016ee4 .word 0x08016ee4 0800820c : 800820c: b508 push {r3, lr} 800820e: 4b03 ldr r3, [pc, #12] @ (800821c ) 8008210: b11b cbz r3, 800821a 8008212: 4903 ldr r1, [pc, #12] @ (8008220 ) 8008214: 4803 ldr r0, [pc, #12] @ (8008224 ) 8008216: f3af 8000 nop.w 800821a: bd08 pop {r3, pc} 800821c: 00000000 .word 0x00000000 8008220: 2000025c .word 0x2000025c 8008224: 08016ee4 .word 0x08016ee4 08008228 : 8008228: 4603 mov r3, r0 800822a: f813 2b01 ldrb.w r2, [r3], #1 800822e: 2a00 cmp r2, #0 8008230: d1fb bne.n 800822a 8008232: 1a18 subs r0, r3, r0 8008234: 3801 subs r0, #1 8008236: 4770 bx lr 08008238 <__aeabi_drsub>: 8008238: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 800823c: e002 b.n 8008244 <__adddf3> 800823e: bf00 nop 08008240 <__aeabi_dsub>: 8008240: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 08008244 <__adddf3>: 8008244: b530 push {r4, r5, lr} 8008246: ea4f 0441 mov.w r4, r1, lsl #1 800824a: ea4f 0543 mov.w r5, r3, lsl #1 800824e: ea94 0f05 teq r4, r5 8008252: bf08 it eq 8008254: ea90 0f02 teqeq r0, r2 8008258: bf1f itttt ne 800825a: ea54 0c00 orrsne.w ip, r4, r0 800825e: ea55 0c02 orrsne.w ip, r5, r2 8008262: ea7f 5c64 mvnsne.w ip, r4, asr #21 8008266: ea7f 5c65 mvnsne.w ip, r5, asr #21 800826a: f000 80e2 beq.w 8008432 <__adddf3+0x1ee> 800826e: ea4f 5454 mov.w r4, r4, lsr #21 8008272: ebd4 5555 rsbs r5, r4, r5, lsr #21 8008276: bfb8 it lt 8008278: 426d neglt r5, r5 800827a: dd0c ble.n 8008296 <__adddf3+0x52> 800827c: 442c add r4, r5 800827e: ea80 0202 eor.w r2, r0, r2 8008282: ea81 0303 eor.w r3, r1, r3 8008286: ea82 0000 eor.w r0, r2, r0 800828a: ea83 0101 eor.w r1, r3, r1 800828e: ea80 0202 eor.w r2, r0, r2 8008292: ea81 0303 eor.w r3, r1, r3 8008296: 2d36 cmp r5, #54 @ 0x36 8008298: bf88 it hi 800829a: bd30 pophi {r4, r5, pc} 800829c: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 80082a0: ea4f 3101 mov.w r1, r1, lsl #12 80082a4: f44f 1c80 mov.w ip, #1048576 @ 0x100000 80082a8: ea4c 3111 orr.w r1, ip, r1, lsr #12 80082ac: d002 beq.n 80082b4 <__adddf3+0x70> 80082ae: 4240 negs r0, r0 80082b0: eb61 0141 sbc.w r1, r1, r1, lsl #1 80082b4: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 80082b8: ea4f 3303 mov.w r3, r3, lsl #12 80082bc: ea4c 3313 orr.w r3, ip, r3, lsr #12 80082c0: d002 beq.n 80082c8 <__adddf3+0x84> 80082c2: 4252 negs r2, r2 80082c4: eb63 0343 sbc.w r3, r3, r3, lsl #1 80082c8: ea94 0f05 teq r4, r5 80082cc: f000 80a7 beq.w 800841e <__adddf3+0x1da> 80082d0: f1a4 0401 sub.w r4, r4, #1 80082d4: f1d5 0e20 rsbs lr, r5, #32 80082d8: db0d blt.n 80082f6 <__adddf3+0xb2> 80082da: fa02 fc0e lsl.w ip, r2, lr 80082de: fa22 f205 lsr.w r2, r2, r5 80082e2: 1880 adds r0, r0, r2 80082e4: f141 0100 adc.w r1, r1, #0 80082e8: fa03 f20e lsl.w r2, r3, lr 80082ec: 1880 adds r0, r0, r2 80082ee: fa43 f305 asr.w r3, r3, r5 80082f2: 4159 adcs r1, r3 80082f4: e00e b.n 8008314 <__adddf3+0xd0> 80082f6: f1a5 0520 sub.w r5, r5, #32 80082fa: f10e 0e20 add.w lr, lr, #32 80082fe: 2a01 cmp r2, #1 8008300: fa03 fc0e lsl.w ip, r3, lr 8008304: bf28 it cs 8008306: f04c 0c02 orrcs.w ip, ip, #2 800830a: fa43 f305 asr.w r3, r3, r5 800830e: 18c0 adds r0, r0, r3 8008310: eb51 71e3 adcs.w r1, r1, r3, asr #31 8008314: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008318: d507 bpl.n 800832a <__adddf3+0xe6> 800831a: f04f 0e00 mov.w lr, #0 800831e: f1dc 0c00 rsbs ip, ip, #0 8008322: eb7e 0000 sbcs.w r0, lr, r0 8008326: eb6e 0101 sbc.w r1, lr, r1 800832a: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 800832e: d31b bcc.n 8008368 <__adddf3+0x124> 8008330: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 8008334: d30c bcc.n 8008350 <__adddf3+0x10c> 8008336: 0849 lsrs r1, r1, #1 8008338: ea5f 0030 movs.w r0, r0, rrx 800833c: ea4f 0c3c mov.w ip, ip, rrx 8008340: f104 0401 add.w r4, r4, #1 8008344: ea4f 5244 mov.w r2, r4, lsl #21 8008348: f512 0f80 cmn.w r2, #4194304 @ 0x400000 800834c: f080 809a bcs.w 8008484 <__adddf3+0x240> 8008350: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008354: bf08 it eq 8008356: ea5f 0c50 movseq.w ip, r0, lsr #1 800835a: f150 0000 adcs.w r0, r0, #0 800835e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008362: ea41 0105 orr.w r1, r1, r5 8008366: bd30 pop {r4, r5, pc} 8008368: ea5f 0c4c movs.w ip, ip, lsl #1 800836c: 4140 adcs r0, r0 800836e: eb41 0101 adc.w r1, r1, r1 8008372: 3c01 subs r4, #1 8008374: bf28 it cs 8008376: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 800837a: d2e9 bcs.n 8008350 <__adddf3+0x10c> 800837c: f091 0f00 teq r1, #0 8008380: bf04 itt eq 8008382: 4601 moveq r1, r0 8008384: 2000 moveq r0, #0 8008386: fab1 f381 clz r3, r1 800838a: bf08 it eq 800838c: 3320 addeq r3, #32 800838e: f1a3 030b sub.w r3, r3, #11 8008392: f1b3 0220 subs.w r2, r3, #32 8008396: da0c bge.n 80083b2 <__adddf3+0x16e> 8008398: 320c adds r2, #12 800839a: dd08 ble.n 80083ae <__adddf3+0x16a> 800839c: f102 0c14 add.w ip, r2, #20 80083a0: f1c2 020c rsb r2, r2, #12 80083a4: fa01 f00c lsl.w r0, r1, ip 80083a8: fa21 f102 lsr.w r1, r1, r2 80083ac: e00c b.n 80083c8 <__adddf3+0x184> 80083ae: f102 0214 add.w r2, r2, #20 80083b2: bfd8 it le 80083b4: f1c2 0c20 rsble ip, r2, #32 80083b8: fa01 f102 lsl.w r1, r1, r2 80083bc: fa20 fc0c lsr.w ip, r0, ip 80083c0: bfdc itt le 80083c2: ea41 010c orrle.w r1, r1, ip 80083c6: 4090 lslle r0, r2 80083c8: 1ae4 subs r4, r4, r3 80083ca: bfa2 ittt ge 80083cc: eb01 5104 addge.w r1, r1, r4, lsl #20 80083d0: 4329 orrge r1, r5 80083d2: bd30 popge {r4, r5, pc} 80083d4: ea6f 0404 mvn.w r4, r4 80083d8: 3c1f subs r4, #31 80083da: da1c bge.n 8008416 <__adddf3+0x1d2> 80083dc: 340c adds r4, #12 80083de: dc0e bgt.n 80083fe <__adddf3+0x1ba> 80083e0: f104 0414 add.w r4, r4, #20 80083e4: f1c4 0220 rsb r2, r4, #32 80083e8: fa20 f004 lsr.w r0, r0, r4 80083ec: fa01 f302 lsl.w r3, r1, r2 80083f0: ea40 0003 orr.w r0, r0, r3 80083f4: fa21 f304 lsr.w r3, r1, r4 80083f8: ea45 0103 orr.w r1, r5, r3 80083fc: bd30 pop {r4, r5, pc} 80083fe: f1c4 040c rsb r4, r4, #12 8008402: f1c4 0220 rsb r2, r4, #32 8008406: fa20 f002 lsr.w r0, r0, r2 800840a: fa01 f304 lsl.w r3, r1, r4 800840e: ea40 0003 orr.w r0, r0, r3 8008412: 4629 mov r1, r5 8008414: bd30 pop {r4, r5, pc} 8008416: fa21 f004 lsr.w r0, r1, r4 800841a: 4629 mov r1, r5 800841c: bd30 pop {r4, r5, pc} 800841e: f094 0f00 teq r4, #0 8008422: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 8008426: bf06 itte eq 8008428: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 800842c: 3401 addeq r4, #1 800842e: 3d01 subne r5, #1 8008430: e74e b.n 80082d0 <__adddf3+0x8c> 8008432: ea7f 5c64 mvns.w ip, r4, asr #21 8008436: bf18 it ne 8008438: ea7f 5c65 mvnsne.w ip, r5, asr #21 800843c: d029 beq.n 8008492 <__adddf3+0x24e> 800843e: ea94 0f05 teq r4, r5 8008442: bf08 it eq 8008444: ea90 0f02 teqeq r0, r2 8008448: d005 beq.n 8008456 <__adddf3+0x212> 800844a: ea54 0c00 orrs.w ip, r4, r0 800844e: bf04 itt eq 8008450: 4619 moveq r1, r3 8008452: 4610 moveq r0, r2 8008454: bd30 pop {r4, r5, pc} 8008456: ea91 0f03 teq r1, r3 800845a: bf1e ittt ne 800845c: 2100 movne r1, #0 800845e: 2000 movne r0, #0 8008460: bd30 popne {r4, r5, pc} 8008462: ea5f 5c54 movs.w ip, r4, lsr #21 8008466: d105 bne.n 8008474 <__adddf3+0x230> 8008468: 0040 lsls r0, r0, #1 800846a: 4149 adcs r1, r1 800846c: bf28 it cs 800846e: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 8008472: bd30 pop {r4, r5, pc} 8008474: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 8008478: bf3c itt cc 800847a: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 800847e: bd30 popcc {r4, r5, pc} 8008480: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008484: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 8008488: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 800848c: f04f 0000 mov.w r0, #0 8008490: bd30 pop {r4, r5, pc} 8008492: ea7f 5c64 mvns.w ip, r4, asr #21 8008496: bf1a itte ne 8008498: 4619 movne r1, r3 800849a: 4610 movne r0, r2 800849c: ea7f 5c65 mvnseq.w ip, r5, asr #21 80084a0: bf1c itt ne 80084a2: 460b movne r3, r1 80084a4: 4602 movne r2, r0 80084a6: ea50 3401 orrs.w r4, r0, r1, lsl #12 80084aa: bf06 itte eq 80084ac: ea52 3503 orrseq.w r5, r2, r3, lsl #12 80084b0: ea91 0f03 teqeq r1, r3 80084b4: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 80084b8: bd30 pop {r4, r5, pc} 80084ba: bf00 nop 080084bc <__aeabi_ui2d>: 80084bc: f090 0f00 teq r0, #0 80084c0: bf04 itt eq 80084c2: 2100 moveq r1, #0 80084c4: 4770 bxeq lr 80084c6: b530 push {r4, r5, lr} 80084c8: f44f 6480 mov.w r4, #1024 @ 0x400 80084cc: f104 0432 add.w r4, r4, #50 @ 0x32 80084d0: f04f 0500 mov.w r5, #0 80084d4: f04f 0100 mov.w r1, #0 80084d8: e750 b.n 800837c <__adddf3+0x138> 80084da: bf00 nop 080084dc <__aeabi_i2d>: 80084dc: f090 0f00 teq r0, #0 80084e0: bf04 itt eq 80084e2: 2100 moveq r1, #0 80084e4: 4770 bxeq lr 80084e6: b530 push {r4, r5, lr} 80084e8: f44f 6480 mov.w r4, #1024 @ 0x400 80084ec: f104 0432 add.w r4, r4, #50 @ 0x32 80084f0: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 80084f4: bf48 it mi 80084f6: 4240 negmi r0, r0 80084f8: f04f 0100 mov.w r1, #0 80084fc: e73e b.n 800837c <__adddf3+0x138> 80084fe: bf00 nop 08008500 <__aeabi_f2d>: 8008500: 0042 lsls r2, r0, #1 8008502: ea4f 01e2 mov.w r1, r2, asr #3 8008506: ea4f 0131 mov.w r1, r1, rrx 800850a: ea4f 7002 mov.w r0, r2, lsl #28 800850e: bf1f itttt ne 8008510: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 8008514: f093 4f7f teqne r3, #4278190080 @ 0xff000000 8008518: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 800851c: 4770 bxne lr 800851e: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 8008522: bf08 it eq 8008524: 4770 bxeq lr 8008526: f093 4f7f teq r3, #4278190080 @ 0xff000000 800852a: bf04 itt eq 800852c: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 8008530: 4770 bxeq lr 8008532: b530 push {r4, r5, lr} 8008534: f44f 7460 mov.w r4, #896 @ 0x380 8008538: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 800853c: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 8008540: e71c b.n 800837c <__adddf3+0x138> 8008542: bf00 nop 08008544 <__aeabi_ul2d>: 8008544: ea50 0201 orrs.w r2, r0, r1 8008548: bf08 it eq 800854a: 4770 bxeq lr 800854c: b530 push {r4, r5, lr} 800854e: f04f 0500 mov.w r5, #0 8008552: e00a b.n 800856a <__aeabi_l2d+0x16> 08008554 <__aeabi_l2d>: 8008554: ea50 0201 orrs.w r2, r0, r1 8008558: bf08 it eq 800855a: 4770 bxeq lr 800855c: b530 push {r4, r5, lr} 800855e: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 8008562: d502 bpl.n 800856a <__aeabi_l2d+0x16> 8008564: 4240 negs r0, r0 8008566: eb61 0141 sbc.w r1, r1, r1, lsl #1 800856a: f44f 6480 mov.w r4, #1024 @ 0x400 800856e: f104 0432 add.w r4, r4, #50 @ 0x32 8008572: ea5f 5c91 movs.w ip, r1, lsr #22 8008576: f43f aed8 beq.w 800832a <__adddf3+0xe6> 800857a: f04f 0203 mov.w r2, #3 800857e: ea5f 0cdc movs.w ip, ip, lsr #3 8008582: bf18 it ne 8008584: 3203 addne r2, #3 8008586: ea5f 0cdc movs.w ip, ip, lsr #3 800858a: bf18 it ne 800858c: 3203 addne r2, #3 800858e: eb02 02dc add.w r2, r2, ip, lsr #3 8008592: f1c2 0320 rsb r3, r2, #32 8008596: fa00 fc03 lsl.w ip, r0, r3 800859a: fa20 f002 lsr.w r0, r0, r2 800859e: fa01 fe03 lsl.w lr, r1, r3 80085a2: ea40 000e orr.w r0, r0, lr 80085a6: fa21 f102 lsr.w r1, r1, r2 80085aa: 4414 add r4, r2 80085ac: e6bd b.n 800832a <__adddf3+0xe6> 80085ae: bf00 nop 080085b0 <__aeabi_dmul>: 80085b0: b570 push {r4, r5, r6, lr} 80085b2: f04f 0cff mov.w ip, #255 @ 0xff 80085b6: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 80085ba: ea1c 5411 ands.w r4, ip, r1, lsr #20 80085be: bf1d ittte ne 80085c0: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80085c4: ea94 0f0c teqne r4, ip 80085c8: ea95 0f0c teqne r5, ip 80085cc: f000 f8de bleq 800878c <__aeabi_dmul+0x1dc> 80085d0: 442c add r4, r5 80085d2: ea81 0603 eor.w r6, r1, r3 80085d6: ea21 514c bic.w r1, r1, ip, lsl #21 80085da: ea23 534c bic.w r3, r3, ip, lsl #21 80085de: ea50 3501 orrs.w r5, r0, r1, lsl #12 80085e2: bf18 it ne 80085e4: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80085e8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 80085ec: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80085f0: d038 beq.n 8008664 <__aeabi_dmul+0xb4> 80085f2: fba0 ce02 umull ip, lr, r0, r2 80085f6: f04f 0500 mov.w r5, #0 80085fa: fbe1 e502 umlal lr, r5, r1, r2 80085fe: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 8008602: fbe0 e503 umlal lr, r5, r0, r3 8008606: f04f 0600 mov.w r6, #0 800860a: fbe1 5603 umlal r5, r6, r1, r3 800860e: f09c 0f00 teq ip, #0 8008612: bf18 it ne 8008614: f04e 0e01 orrne.w lr, lr, #1 8008618: f1a4 04ff sub.w r4, r4, #255 @ 0xff 800861c: f5b6 7f00 cmp.w r6, #512 @ 0x200 8008620: f564 7440 sbc.w r4, r4, #768 @ 0x300 8008624: d204 bcs.n 8008630 <__aeabi_dmul+0x80> 8008626: ea5f 0e4e movs.w lr, lr, lsl #1 800862a: 416d adcs r5, r5 800862c: eb46 0606 adc.w r6, r6, r6 8008630: ea42 21c6 orr.w r1, r2, r6, lsl #11 8008634: ea41 5155 orr.w r1, r1, r5, lsr #21 8008638: ea4f 20c5 mov.w r0, r5, lsl #11 800863c: ea40 505e orr.w r0, r0, lr, lsr #21 8008640: ea4f 2ece mov.w lr, lr, lsl #11 8008644: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008648: bf88 it hi 800864a: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800864e: d81e bhi.n 800868e <__aeabi_dmul+0xde> 8008650: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 8008654: bf08 it eq 8008656: ea5f 0e50 movseq.w lr, r0, lsr #1 800865a: f150 0000 adcs.w r0, r0, #0 800865e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008662: bd70 pop {r4, r5, r6, pc} 8008664: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 8008668: ea46 0101 orr.w r1, r6, r1 800866c: ea40 0002 orr.w r0, r0, r2 8008670: ea81 0103 eor.w r1, r1, r3 8008674: ebb4 045c subs.w r4, r4, ip, lsr #1 8008678: bfc2 ittt gt 800867a: ebd4 050c rsbsgt r5, r4, ip 800867e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8008682: bd70 popgt {r4, r5, r6, pc} 8008684: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008688: f04f 0e00 mov.w lr, #0 800868c: 3c01 subs r4, #1 800868e: f300 80ab bgt.w 80087e8 <__aeabi_dmul+0x238> 8008692: f114 0f36 cmn.w r4, #54 @ 0x36 8008696: bfde ittt le 8008698: 2000 movle r0, #0 800869a: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 800869e: bd70 pople {r4, r5, r6, pc} 80086a0: f1c4 0400 rsb r4, r4, #0 80086a4: 3c20 subs r4, #32 80086a6: da35 bge.n 8008714 <__aeabi_dmul+0x164> 80086a8: 340c adds r4, #12 80086aa: dc1b bgt.n 80086e4 <__aeabi_dmul+0x134> 80086ac: f104 0414 add.w r4, r4, #20 80086b0: f1c4 0520 rsb r5, r4, #32 80086b4: fa00 f305 lsl.w r3, r0, r5 80086b8: fa20 f004 lsr.w r0, r0, r4 80086bc: fa01 f205 lsl.w r2, r1, r5 80086c0: ea40 0002 orr.w r0, r0, r2 80086c4: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 80086c8: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 80086cc: eb10 70d3 adds.w r0, r0, r3, lsr #31 80086d0: fa21 f604 lsr.w r6, r1, r4 80086d4: eb42 0106 adc.w r1, r2, r6 80086d8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80086dc: bf08 it eq 80086de: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80086e2: bd70 pop {r4, r5, r6, pc} 80086e4: f1c4 040c rsb r4, r4, #12 80086e8: f1c4 0520 rsb r5, r4, #32 80086ec: fa00 f304 lsl.w r3, r0, r4 80086f0: fa20 f005 lsr.w r0, r0, r5 80086f4: fa01 f204 lsl.w r2, r1, r4 80086f8: ea40 0002 orr.w r0, r0, r2 80086fc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008700: eb10 70d3 adds.w r0, r0, r3, lsr #31 8008704: f141 0100 adc.w r1, r1, #0 8008708: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800870c: bf08 it eq 800870e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8008712: bd70 pop {r4, r5, r6, pc} 8008714: f1c4 0520 rsb r5, r4, #32 8008718: fa00 f205 lsl.w r2, r0, r5 800871c: ea4e 0e02 orr.w lr, lr, r2 8008720: fa20 f304 lsr.w r3, r0, r4 8008724: fa01 f205 lsl.w r2, r1, r5 8008728: ea43 0302 orr.w r3, r3, r2 800872c: fa21 f004 lsr.w r0, r1, r4 8008730: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008734: fa21 f204 lsr.w r2, r1, r4 8008738: ea20 0002 bic.w r0, r0, r2 800873c: eb00 70d3 add.w r0, r0, r3, lsr #31 8008740: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8008744: bf08 it eq 8008746: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800874a: bd70 pop {r4, r5, r6, pc} 800874c: f094 0f00 teq r4, #0 8008750: d10f bne.n 8008772 <__aeabi_dmul+0x1c2> 8008752: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 8008756: 0040 lsls r0, r0, #1 8008758: eb41 0101 adc.w r1, r1, r1 800875c: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008760: bf08 it eq 8008762: 3c01 subeq r4, #1 8008764: d0f7 beq.n 8008756 <__aeabi_dmul+0x1a6> 8008766: ea41 0106 orr.w r1, r1, r6 800876a: f095 0f00 teq r5, #0 800876e: bf18 it ne 8008770: 4770 bxne lr 8008772: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 8008776: 0052 lsls r2, r2, #1 8008778: eb43 0303 adc.w r3, r3, r3 800877c: f413 1f80 tst.w r3, #1048576 @ 0x100000 8008780: bf08 it eq 8008782: 3d01 subeq r5, #1 8008784: d0f7 beq.n 8008776 <__aeabi_dmul+0x1c6> 8008786: ea43 0306 orr.w r3, r3, r6 800878a: 4770 bx lr 800878c: ea94 0f0c teq r4, ip 8008790: ea0c 5513 and.w r5, ip, r3, lsr #20 8008794: bf18 it ne 8008796: ea95 0f0c teqne r5, ip 800879a: d00c beq.n 80087b6 <__aeabi_dmul+0x206> 800879c: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087a0: bf18 it ne 80087a2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087a6: d1d1 bne.n 800874c <__aeabi_dmul+0x19c> 80087a8: ea81 0103 eor.w r1, r1, r3 80087ac: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087b0: f04f 0000 mov.w r0, #0 80087b4: bd70 pop {r4, r5, r6, pc} 80087b6: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087ba: bf06 itte eq 80087bc: 4610 moveq r0, r2 80087be: 4619 moveq r1, r3 80087c0: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087c4: d019 beq.n 80087fa <__aeabi_dmul+0x24a> 80087c6: ea94 0f0c teq r4, ip 80087ca: d102 bne.n 80087d2 <__aeabi_dmul+0x222> 80087cc: ea50 3601 orrs.w r6, r0, r1, lsl #12 80087d0: d113 bne.n 80087fa <__aeabi_dmul+0x24a> 80087d2: ea95 0f0c teq r5, ip 80087d6: d105 bne.n 80087e4 <__aeabi_dmul+0x234> 80087d8: ea52 3603 orrs.w r6, r2, r3, lsl #12 80087dc: bf1c itt ne 80087de: 4610 movne r0, r2 80087e0: 4619 movne r1, r3 80087e2: d10a bne.n 80087fa <__aeabi_dmul+0x24a> 80087e4: ea81 0103 eor.w r1, r1, r3 80087e8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087ec: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087f0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 80087f4: f04f 0000 mov.w r0, #0 80087f8: bd70 pop {r4, r5, r6, pc} 80087fa: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087fe: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 8008802: bd70 pop {r4, r5, r6, pc} 08008804 <__aeabi_ddiv>: 8008804: b570 push {r4, r5, r6, lr} 8008806: f04f 0cff mov.w ip, #255 @ 0xff 800880a: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 800880e: ea1c 5411 ands.w r4, ip, r1, lsr #20 8008812: bf1d ittte ne 8008814: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8008818: ea94 0f0c teqne r4, ip 800881c: ea95 0f0c teqne r5, ip 8008820: f000 f8a7 bleq 8008972 <__aeabi_ddiv+0x16e> 8008824: eba4 0405 sub.w r4, r4, r5 8008828: ea81 0e03 eor.w lr, r1, r3 800882c: ea52 3503 orrs.w r5, r2, r3, lsl #12 8008830: ea4f 3101 mov.w r1, r1, lsl #12 8008834: f000 8088 beq.w 8008948 <__aeabi_ddiv+0x144> 8008838: ea4f 3303 mov.w r3, r3, lsl #12 800883c: f04f 5580 mov.w r5, #268435456 @ 0x10000000 8008840: ea45 1313 orr.w r3, r5, r3, lsr #4 8008844: ea43 6312 orr.w r3, r3, r2, lsr #24 8008848: ea4f 2202 mov.w r2, r2, lsl #8 800884c: ea45 1511 orr.w r5, r5, r1, lsr #4 8008850: ea45 6510 orr.w r5, r5, r0, lsr #24 8008854: ea4f 2600 mov.w r6, r0, lsl #8 8008858: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000 800885c: 429d cmp r5, r3 800885e: bf08 it eq 8008860: 4296 cmpeq r6, r2 8008862: f144 04fd adc.w r4, r4, #253 @ 0xfd 8008866: f504 7440 add.w r4, r4, #768 @ 0x300 800886a: d202 bcs.n 8008872 <__aeabi_ddiv+0x6e> 800886c: 085b lsrs r3, r3, #1 800886e: ea4f 0232 mov.w r2, r2, rrx 8008872: 1ab6 subs r6, r6, r2 8008874: eb65 0503 sbc.w r5, r5, r3 8008878: 085b lsrs r3, r3, #1 800887a: ea4f 0232 mov.w r2, r2, rrx 800887e: f44f 1080 mov.w r0, #1048576 @ 0x100000 8008882: f44f 2c00 mov.w ip, #524288 @ 0x80000 8008886: ebb6 0e02 subs.w lr, r6, r2 800888a: eb75 0e03 sbcs.w lr, r5, r3 800888e: bf22 ittt cs 8008890: 1ab6 subcs r6, r6, r2 8008892: 4675 movcs r5, lr 8008894: ea40 000c orrcs.w r0, r0, ip 8008898: 085b lsrs r3, r3, #1 800889a: ea4f 0232 mov.w r2, r2, rrx 800889e: ebb6 0e02 subs.w lr, r6, r2 80088a2: eb75 0e03 sbcs.w lr, r5, r3 80088a6: bf22 ittt cs 80088a8: 1ab6 subcs r6, r6, r2 80088aa: 4675 movcs r5, lr 80088ac: ea40 005c orrcs.w r0, r0, ip, lsr #1 80088b0: 085b lsrs r3, r3, #1 80088b2: ea4f 0232 mov.w r2, r2, rrx 80088b6: ebb6 0e02 subs.w lr, r6, r2 80088ba: eb75 0e03 sbcs.w lr, r5, r3 80088be: bf22 ittt cs 80088c0: 1ab6 subcs r6, r6, r2 80088c2: 4675 movcs r5, lr 80088c4: ea40 009c orrcs.w r0, r0, ip, lsr #2 80088c8: 085b lsrs r3, r3, #1 80088ca: ea4f 0232 mov.w r2, r2, rrx 80088ce: ebb6 0e02 subs.w lr, r6, r2 80088d2: eb75 0e03 sbcs.w lr, r5, r3 80088d6: bf22 ittt cs 80088d8: 1ab6 subcs r6, r6, r2 80088da: 4675 movcs r5, lr 80088dc: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80088e0: ea55 0e06 orrs.w lr, r5, r6 80088e4: d018 beq.n 8008918 <__aeabi_ddiv+0x114> 80088e6: ea4f 1505 mov.w r5, r5, lsl #4 80088ea: ea45 7516 orr.w r5, r5, r6, lsr #28 80088ee: ea4f 1606 mov.w r6, r6, lsl #4 80088f2: ea4f 03c3 mov.w r3, r3, lsl #3 80088f6: ea43 7352 orr.w r3, r3, r2, lsr #29 80088fa: ea4f 02c2 mov.w r2, r2, lsl #3 80088fe: ea5f 1c1c movs.w ip, ip, lsr #4 8008902: d1c0 bne.n 8008886 <__aeabi_ddiv+0x82> 8008904: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008908: d10b bne.n 8008922 <__aeabi_ddiv+0x11e> 800890a: ea41 0100 orr.w r1, r1, r0 800890e: f04f 0000 mov.w r0, #0 8008912: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000 8008916: e7b6 b.n 8008886 <__aeabi_ddiv+0x82> 8008918: f411 1f80 tst.w r1, #1048576 @ 0x100000 800891c: bf04 itt eq 800891e: 4301 orreq r1, r0 8008920: 2000 moveq r0, #0 8008922: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008926: bf88 it hi 8008928: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800892c: f63f aeaf bhi.w 800868e <__aeabi_dmul+0xde> 8008930: ebb5 0c03 subs.w ip, r5, r3 8008934: bf04 itt eq 8008936: ebb6 0c02 subseq.w ip, r6, r2 800893a: ea5f 0c50 movseq.w ip, r0, lsr #1 800893e: f150 0000 adcs.w r0, r0, #0 8008942: eb41 5104 adc.w r1, r1, r4, lsl #20 8008946: bd70 pop {r4, r5, r6, pc} 8008948: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000 800894c: ea4e 3111 orr.w r1, lr, r1, lsr #12 8008950: eb14 045c adds.w r4, r4, ip, lsr #1 8008954: bfc2 ittt gt 8008956: ebd4 050c rsbsgt r5, r4, ip 800895a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800895e: bd70 popgt {r4, r5, r6, pc} 8008960: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008964: f04f 0e00 mov.w lr, #0 8008968: 3c01 subs r4, #1 800896a: e690 b.n 800868e <__aeabi_dmul+0xde> 800896c: ea45 0e06 orr.w lr, r5, r6 8008970: e68d b.n 800868e <__aeabi_dmul+0xde> 8008972: ea0c 5513 and.w r5, ip, r3, lsr #20 8008976: ea94 0f0c teq r4, ip 800897a: bf08 it eq 800897c: ea95 0f0c teqeq r5, ip 8008980: f43f af3b beq.w 80087fa <__aeabi_dmul+0x24a> 8008984: ea94 0f0c teq r4, ip 8008988: d10a bne.n 80089a0 <__aeabi_ddiv+0x19c> 800898a: ea50 3401 orrs.w r4, r0, r1, lsl #12 800898e: f47f af34 bne.w 80087fa <__aeabi_dmul+0x24a> 8008992: ea95 0f0c teq r5, ip 8008996: f47f af25 bne.w 80087e4 <__aeabi_dmul+0x234> 800899a: 4610 mov r0, r2 800899c: 4619 mov r1, r3 800899e: e72c b.n 80087fa <__aeabi_dmul+0x24a> 80089a0: ea95 0f0c teq r5, ip 80089a4: d106 bne.n 80089b4 <__aeabi_ddiv+0x1b0> 80089a6: ea52 3503 orrs.w r5, r2, r3, lsl #12 80089aa: f43f aefd beq.w 80087a8 <__aeabi_dmul+0x1f8> 80089ae: 4610 mov r0, r2 80089b0: 4619 mov r1, r3 80089b2: e722 b.n 80087fa <__aeabi_dmul+0x24a> 80089b4: ea50 0641 orrs.w r6, r0, r1, lsl #1 80089b8: bf18 it ne 80089ba: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80089be: f47f aec5 bne.w 800874c <__aeabi_dmul+0x19c> 80089c2: ea50 0441 orrs.w r4, r0, r1, lsl #1 80089c6: f47f af0d bne.w 80087e4 <__aeabi_dmul+0x234> 80089ca: ea52 0543 orrs.w r5, r2, r3, lsl #1 80089ce: f47f aeeb bne.w 80087a8 <__aeabi_dmul+0x1f8> 80089d2: e712 b.n 80087fa <__aeabi_dmul+0x24a> 080089d4 <__gedf2>: 80089d4: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80089d8: e006 b.n 80089e8 <__cmpdf2+0x4> 80089da: bf00 nop 080089dc <__ledf2>: 80089dc: f04f 0c01 mov.w ip, #1 80089e0: e002 b.n 80089e8 <__cmpdf2+0x4> 80089e2: bf00 nop 080089e4 <__cmpdf2>: 80089e4: f04f 0c01 mov.w ip, #1 80089e8: f84d cd04 str.w ip, [sp, #-4]! 80089ec: ea4f 0c41 mov.w ip, r1, lsl #1 80089f0: ea7f 5c6c mvns.w ip, ip, asr #21 80089f4: ea4f 0c43 mov.w ip, r3, lsl #1 80089f8: bf18 it ne 80089fa: ea7f 5c6c mvnsne.w ip, ip, asr #21 80089fe: d01b beq.n 8008a38 <__cmpdf2+0x54> 8008a00: b001 add sp, #4 8008a02: ea50 0c41 orrs.w ip, r0, r1, lsl #1 8008a06: bf0c ite eq 8008a08: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 8008a0c: ea91 0f03 teqne r1, r3 8008a10: bf02 ittt eq 8008a12: ea90 0f02 teqeq r0, r2 8008a16: 2000 moveq r0, #0 8008a18: 4770 bxeq lr 8008a1a: f110 0f00 cmn.w r0, #0 8008a1e: ea91 0f03 teq r1, r3 8008a22: bf58 it pl 8008a24: 4299 cmppl r1, r3 8008a26: bf08 it eq 8008a28: 4290 cmpeq r0, r2 8008a2a: bf2c ite cs 8008a2c: 17d8 asrcs r0, r3, #31 8008a2e: ea6f 70e3 mvncc.w r0, r3, asr #31 8008a32: f040 0001 orr.w r0, r0, #1 8008a36: 4770 bx lr 8008a38: ea4f 0c41 mov.w ip, r1, lsl #1 8008a3c: ea7f 5c6c mvns.w ip, ip, asr #21 8008a40: d102 bne.n 8008a48 <__cmpdf2+0x64> 8008a42: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8008a46: d107 bne.n 8008a58 <__cmpdf2+0x74> 8008a48: ea4f 0c43 mov.w ip, r3, lsl #1 8008a4c: ea7f 5c6c mvns.w ip, ip, asr #21 8008a50: d1d6 bne.n 8008a00 <__cmpdf2+0x1c> 8008a52: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8008a56: d0d3 beq.n 8008a00 <__cmpdf2+0x1c> 8008a58: f85d 0b04 ldr.w r0, [sp], #4 8008a5c: 4770 bx lr 8008a5e: bf00 nop 08008a60 <__aeabi_cdrcmple>: 8008a60: 4684 mov ip, r0 8008a62: 4610 mov r0, r2 8008a64: 4662 mov r2, ip 8008a66: 468c mov ip, r1 8008a68: 4619 mov r1, r3 8008a6a: 4663 mov r3, ip 8008a6c: e000 b.n 8008a70 <__aeabi_cdcmpeq> 8008a6e: bf00 nop 08008a70 <__aeabi_cdcmpeq>: 8008a70: b501 push {r0, lr} 8008a72: f7ff ffb7 bl 80089e4 <__cmpdf2> 8008a76: 2800 cmp r0, #0 8008a78: bf48 it mi 8008a7a: f110 0f00 cmnmi.w r0, #0 8008a7e: bd01 pop {r0, pc} 08008a80 <__aeabi_dcmpeq>: 8008a80: f84d ed08 str.w lr, [sp, #-8]! 8008a84: f7ff fff4 bl 8008a70 <__aeabi_cdcmpeq> 8008a88: bf0c ite eq 8008a8a: 2001 moveq r0, #1 8008a8c: 2000 movne r0, #0 8008a8e: f85d fb08 ldr.w pc, [sp], #8 8008a92: bf00 nop 08008a94 <__aeabi_dcmplt>: 8008a94: f84d ed08 str.w lr, [sp, #-8]! 8008a98: f7ff ffea bl 8008a70 <__aeabi_cdcmpeq> 8008a9c: bf34 ite cc 8008a9e: 2001 movcc r0, #1 8008aa0: 2000 movcs r0, #0 8008aa2: f85d fb08 ldr.w pc, [sp], #8 8008aa6: bf00 nop 08008aa8 <__aeabi_dcmple>: 8008aa8: f84d ed08 str.w lr, [sp, #-8]! 8008aac: f7ff ffe0 bl 8008a70 <__aeabi_cdcmpeq> 8008ab0: bf94 ite ls 8008ab2: 2001 movls r0, #1 8008ab4: 2000 movhi r0, #0 8008ab6: f85d fb08 ldr.w pc, [sp], #8 8008aba: bf00 nop 08008abc <__aeabi_dcmpge>: 8008abc: f84d ed08 str.w lr, [sp, #-8]! 8008ac0: f7ff ffce bl 8008a60 <__aeabi_cdrcmple> 8008ac4: bf94 ite ls 8008ac6: 2001 movls r0, #1 8008ac8: 2000 movhi r0, #0 8008aca: f85d fb08 ldr.w pc, [sp], #8 8008ace: bf00 nop 08008ad0 <__aeabi_dcmpgt>: 8008ad0: f84d ed08 str.w lr, [sp, #-8]! 8008ad4: f7ff ffc4 bl 8008a60 <__aeabi_cdrcmple> 8008ad8: bf34 ite cc 8008ada: 2001 movcc r0, #1 8008adc: 2000 movcs r0, #0 8008ade: f85d fb08 ldr.w pc, [sp], #8 8008ae2: bf00 nop 08008ae4 <__aeabi_dcmpun>: 8008ae4: ea4f 0c41 mov.w ip, r1, lsl #1 8008ae8: ea7f 5c6c mvns.w ip, ip, asr #21 8008aec: d102 bne.n 8008af4 <__aeabi_dcmpun+0x10> 8008aee: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8008af2: d10a bne.n 8008b0a <__aeabi_dcmpun+0x26> 8008af4: ea4f 0c43 mov.w ip, r3, lsl #1 8008af8: ea7f 5c6c mvns.w ip, ip, asr #21 8008afc: d102 bne.n 8008b04 <__aeabi_dcmpun+0x20> 8008afe: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8008b02: d102 bne.n 8008b0a <__aeabi_dcmpun+0x26> 8008b04: f04f 0000 mov.w r0, #0 8008b08: 4770 bx lr 8008b0a: f04f 0001 mov.w r0, #1 8008b0e: 4770 bx lr 08008b10 <__aeabi_d2iz>: 8008b10: ea4f 0241 mov.w r2, r1, lsl #1 8008b14: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 8008b18: d215 bcs.n 8008b46 <__aeabi_d2iz+0x36> 8008b1a: d511 bpl.n 8008b40 <__aeabi_d2iz+0x30> 8008b1c: f46f 7378 mvn.w r3, #992 @ 0x3e0 8008b20: ebb3 5262 subs.w r2, r3, r2, asr #21 8008b24: d912 bls.n 8008b4c <__aeabi_d2iz+0x3c> 8008b26: ea4f 23c1 mov.w r3, r1, lsl #11 8008b2a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8008b2e: ea43 5350 orr.w r3, r3, r0, lsr #21 8008b32: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008b36: fa23 f002 lsr.w r0, r3, r2 8008b3a: bf18 it ne 8008b3c: 4240 negne r0, r0 8008b3e: 4770 bx lr 8008b40: f04f 0000 mov.w r0, #0 8008b44: 4770 bx lr 8008b46: ea50 3001 orrs.w r0, r0, r1, lsl #12 8008b4a: d105 bne.n 8008b58 <__aeabi_d2iz+0x48> 8008b4c: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000 8008b50: bf08 it eq 8008b52: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 8008b56: 4770 bx lr 8008b58: f04f 0000 mov.w r0, #0 8008b5c: 4770 bx lr 8008b5e: bf00 nop 08008b60 <__aeabi_d2f>: 8008b60: ea4f 0241 mov.w r2, r1, lsl #1 8008b64: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000 8008b68: bf24 itt cs 8008b6a: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000 8008b6e: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000 8008b72: d90d bls.n 8008b90 <__aeabi_d2f+0x30> 8008b74: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008b78: ea4f 02c0 mov.w r2, r0, lsl #3 8008b7c: ea4c 7050 orr.w r0, ip, r0, lsr #29 8008b80: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000 8008b84: eb40 0083 adc.w r0, r0, r3, lsl #2 8008b88: bf08 it eq 8008b8a: f020 0001 biceq.w r0, r0, #1 8008b8e: 4770 bx lr 8008b90: f011 4f80 tst.w r1, #1073741824 @ 0x40000000 8008b94: d121 bne.n 8008bda <__aeabi_d2f+0x7a> 8008b96: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000 8008b9a: bfbc itt lt 8008b9c: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000 8008ba0: 4770 bxlt lr 8008ba2: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008ba6: ea4f 5252 mov.w r2, r2, lsr #21 8008baa: f1c2 0218 rsb r2, r2, #24 8008bae: f1c2 0c20 rsb ip, r2, #32 8008bb2: fa10 f30c lsls.w r3, r0, ip 8008bb6: fa20 f002 lsr.w r0, r0, r2 8008bba: bf18 it ne 8008bbc: f040 0001 orrne.w r0, r0, #1 8008bc0: ea4f 23c1 mov.w r3, r1, lsl #11 8008bc4: ea4f 23d3 mov.w r3, r3, lsr #11 8008bc8: fa03 fc0c lsl.w ip, r3, ip 8008bcc: ea40 000c orr.w r0, r0, ip 8008bd0: fa23 f302 lsr.w r3, r3, r2 8008bd4: ea4f 0343 mov.w r3, r3, lsl #1 8008bd8: e7cc b.n 8008b74 <__aeabi_d2f+0x14> 8008bda: ea7f 5362 mvns.w r3, r2, asr #21 8008bde: d107 bne.n 8008bf0 <__aeabi_d2f+0x90> 8008be0: ea50 3301 orrs.w r3, r0, r1, lsl #12 8008be4: bf1e ittt ne 8008be6: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000 8008bea: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000 8008bee: 4770 bxne lr 8008bf0: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000 8008bf4: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008bf8: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008bfc: 4770 bx lr 8008bfe: bf00 nop 08008c00 <__aeabi_frsub>: 8008c00: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000 8008c04: e002 b.n 8008c0c <__addsf3> 8008c06: bf00 nop 08008c08 <__aeabi_fsub>: 8008c08: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 08008c0c <__addsf3>: 8008c0c: 0042 lsls r2, r0, #1 8008c0e: bf1f itttt ne 8008c10: ea5f 0341 movsne.w r3, r1, lsl #1 8008c14: ea92 0f03 teqne r2, r3 8008c18: ea7f 6c22 mvnsne.w ip, r2, asr #24 8008c1c: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008c20: d06a beq.n 8008cf8 <__addsf3+0xec> 8008c22: ea4f 6212 mov.w r2, r2, lsr #24 8008c26: ebd2 6313 rsbs r3, r2, r3, lsr #24 8008c2a: bfc1 itttt gt 8008c2c: 18d2 addgt r2, r2, r3 8008c2e: 4041 eorgt r1, r0 8008c30: 4048 eorgt r0, r1 8008c32: 4041 eorgt r1, r0 8008c34: bfb8 it lt 8008c36: 425b neglt r3, r3 8008c38: 2b19 cmp r3, #25 8008c3a: bf88 it hi 8008c3c: 4770 bxhi lr 8008c3e: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 8008c42: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008c46: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000 8008c4a: bf18 it ne 8008c4c: 4240 negne r0, r0 8008c4e: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008c52: f441 0100 orr.w r1, r1, #8388608 @ 0x800000 8008c56: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000 8008c5a: bf18 it ne 8008c5c: 4249 negne r1, r1 8008c5e: ea92 0f03 teq r2, r3 8008c62: d03f beq.n 8008ce4 <__addsf3+0xd8> 8008c64: f1a2 0201 sub.w r2, r2, #1 8008c68: fa41 fc03 asr.w ip, r1, r3 8008c6c: eb10 000c adds.w r0, r0, ip 8008c70: f1c3 0320 rsb r3, r3, #32 8008c74: fa01 f103 lsl.w r1, r1, r3 8008c78: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008c7c: d502 bpl.n 8008c84 <__addsf3+0x78> 8008c7e: 4249 negs r1, r1 8008c80: eb60 0040 sbc.w r0, r0, r0, lsl #1 8008c84: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000 8008c88: d313 bcc.n 8008cb2 <__addsf3+0xa6> 8008c8a: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000 8008c8e: d306 bcc.n 8008c9e <__addsf3+0x92> 8008c90: 0840 lsrs r0, r0, #1 8008c92: ea4f 0131 mov.w r1, r1, rrx 8008c96: f102 0201 add.w r2, r2, #1 8008c9a: 2afe cmp r2, #254 @ 0xfe 8008c9c: d251 bcs.n 8008d42 <__addsf3+0x136> 8008c9e: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000 8008ca2: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008ca6: bf08 it eq 8008ca8: f020 0001 biceq.w r0, r0, #1 8008cac: ea40 0003 orr.w r0, r0, r3 8008cb0: 4770 bx lr 8008cb2: 0049 lsls r1, r1, #1 8008cb4: eb40 0000 adc.w r0, r0, r0 8008cb8: 3a01 subs r2, #1 8008cba: bf28 it cs 8008cbc: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000 8008cc0: d2ed bcs.n 8008c9e <__addsf3+0x92> 8008cc2: fab0 fc80 clz ip, r0 8008cc6: f1ac 0c08 sub.w ip, ip, #8 8008cca: ebb2 020c subs.w r2, r2, ip 8008cce: fa00 f00c lsl.w r0, r0, ip 8008cd2: bfaa itet ge 8008cd4: eb00 50c2 addge.w r0, r0, r2, lsl #23 8008cd8: 4252 neglt r2, r2 8008cda: 4318 orrge r0, r3 8008cdc: bfbc itt lt 8008cde: 40d0 lsrlt r0, r2 8008ce0: 4318 orrlt r0, r3 8008ce2: 4770 bx lr 8008ce4: f092 0f00 teq r2, #0 8008ce8: f481 0100 eor.w r1, r1, #8388608 @ 0x800000 8008cec: bf06 itte eq 8008cee: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000 8008cf2: 3201 addeq r2, #1 8008cf4: 3b01 subne r3, #1 8008cf6: e7b5 b.n 8008c64 <__addsf3+0x58> 8008cf8: ea4f 0341 mov.w r3, r1, lsl #1 8008cfc: ea7f 6c22 mvns.w ip, r2, asr #24 8008d00: bf18 it ne 8008d02: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008d06: d021 beq.n 8008d4c <__addsf3+0x140> 8008d08: ea92 0f03 teq r2, r3 8008d0c: d004 beq.n 8008d18 <__addsf3+0x10c> 8008d0e: f092 0f00 teq r2, #0 8008d12: bf08 it eq 8008d14: 4608 moveq r0, r1 8008d16: 4770 bx lr 8008d18: ea90 0f01 teq r0, r1 8008d1c: bf1c itt ne 8008d1e: 2000 movne r0, #0 8008d20: 4770 bxne lr 8008d22: f012 4f7f tst.w r2, #4278190080 @ 0xff000000 8008d26: d104 bne.n 8008d32 <__addsf3+0x126> 8008d28: 0040 lsls r0, r0, #1 8008d2a: bf28 it cs 8008d2c: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000 8008d30: 4770 bx lr 8008d32: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000 8008d36: bf3c itt cc 8008d38: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000 8008d3c: 4770 bxcc lr 8008d3e: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008d42: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000 8008d46: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008d4a: 4770 bx lr 8008d4c: ea7f 6222 mvns.w r2, r2, asr #24 8008d50: bf16 itet ne 8008d52: 4608 movne r0, r1 8008d54: ea7f 6323 mvnseq.w r3, r3, asr #24 8008d58: 4601 movne r1, r0 8008d5a: 0242 lsls r2, r0, #9 8008d5c: bf06 itte eq 8008d5e: ea5f 2341 movseq.w r3, r1, lsl #9 8008d62: ea90 0f01 teqeq r0, r1 8008d66: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000 8008d6a: 4770 bx lr 08008d6c <__aeabi_ui2f>: 8008d6c: f04f 0300 mov.w r3, #0 8008d70: e004 b.n 8008d7c <__aeabi_i2f+0x8> 8008d72: bf00 nop 08008d74 <__aeabi_i2f>: 8008d74: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000 8008d78: bf48 it mi 8008d7a: 4240 negmi r0, r0 8008d7c: ea5f 0c00 movs.w ip, r0 8008d80: bf08 it eq 8008d82: 4770 bxeq lr 8008d84: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000 8008d88: 4601 mov r1, r0 8008d8a: f04f 0000 mov.w r0, #0 8008d8e: e01c b.n 8008dca <__aeabi_l2f+0x2a> 08008d90 <__aeabi_ul2f>: 8008d90: ea50 0201 orrs.w r2, r0, r1 8008d94: bf08 it eq 8008d96: 4770 bxeq lr 8008d98: f04f 0300 mov.w r3, #0 8008d9c: e00a b.n 8008db4 <__aeabi_l2f+0x14> 8008d9e: bf00 nop 08008da0 <__aeabi_l2f>: 8008da0: ea50 0201 orrs.w r2, r0, r1 8008da4: bf08 it eq 8008da6: 4770 bxeq lr 8008da8: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000 8008dac: d502 bpl.n 8008db4 <__aeabi_l2f+0x14> 8008dae: 4240 negs r0, r0 8008db0: eb61 0141 sbc.w r1, r1, r1, lsl #1 8008db4: ea5f 0c01 movs.w ip, r1 8008db8: bf02 ittt eq 8008dba: 4684 moveq ip, r0 8008dbc: 4601 moveq r1, r0 8008dbe: 2000 moveq r0, #0 8008dc0: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000 8008dc4: bf08 it eq 8008dc6: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000 8008dca: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 8008dce: fabc f28c clz r2, ip 8008dd2: 3a08 subs r2, #8 8008dd4: eba3 53c2 sub.w r3, r3, r2, lsl #23 8008dd8: db10 blt.n 8008dfc <__aeabi_l2f+0x5c> 8008dda: fa01 fc02 lsl.w ip, r1, r2 8008dde: 4463 add r3, ip 8008de0: fa00 fc02 lsl.w ip, r0, r2 8008de4: f1c2 0220 rsb r2, r2, #32 8008de8: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008dec: fa20 f202 lsr.w r2, r0, r2 8008df0: eb43 0002 adc.w r0, r3, r2 8008df4: bf08 it eq 8008df6: f020 0001 biceq.w r0, r0, #1 8008dfa: 4770 bx lr 8008dfc: f102 0220 add.w r2, r2, #32 8008e00: fa01 fc02 lsl.w ip, r1, r2 8008e04: f1c2 0220 rsb r2, r2, #32 8008e08: ea50 004c orrs.w r0, r0, ip, lsl #1 8008e0c: fa21 f202 lsr.w r2, r1, r2 8008e10: eb43 0002 adc.w r0, r3, r2 8008e14: bf08 it eq 8008e16: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008e1a: 4770 bx lr 08008e1c <__aeabi_fmul>: 8008e1c: f04f 0cff mov.w ip, #255 @ 0xff 8008e20: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008e24: bf1e ittt ne 8008e26: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008e2a: ea92 0f0c teqne r2, ip 8008e2e: ea93 0f0c teqne r3, ip 8008e32: d06f beq.n 8008f14 <__aeabi_fmul+0xf8> 8008e34: 441a add r2, r3 8008e36: ea80 0c01 eor.w ip, r0, r1 8008e3a: 0240 lsls r0, r0, #9 8008e3c: bf18 it ne 8008e3e: ea5f 2141 movsne.w r1, r1, lsl #9 8008e42: d01e beq.n 8008e82 <__aeabi_fmul+0x66> 8008e44: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8008e48: ea43 1050 orr.w r0, r3, r0, lsr #5 8008e4c: ea43 1151 orr.w r1, r3, r1, lsr #5 8008e50: fba0 3101 umull r3, r1, r0, r1 8008e54: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008e58: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000 8008e5c: bf3e ittt cc 8008e5e: 0049 lslcc r1, r1, #1 8008e60: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 8008e64: 005b lslcc r3, r3, #1 8008e66: ea40 0001 orr.w r0, r0, r1 8008e6a: f162 027f sbc.w r2, r2, #127 @ 0x7f 8008e6e: 2afd cmp r2, #253 @ 0xfd 8008e70: d81d bhi.n 8008eae <__aeabi_fmul+0x92> 8008e72: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008e76: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008e7a: bf08 it eq 8008e7c: f020 0001 biceq.w r0, r0, #1 8008e80: 4770 bx lr 8008e82: f090 0f00 teq r0, #0 8008e86: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8008e8a: bf08 it eq 8008e8c: 0249 lsleq r1, r1, #9 8008e8e: ea4c 2050 orr.w r0, ip, r0, lsr #9 8008e92: ea40 2051 orr.w r0, r0, r1, lsr #9 8008e96: 3a7f subs r2, #127 @ 0x7f 8008e98: bfc2 ittt gt 8008e9a: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 8008e9e: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8008ea2: 4770 bxgt lr 8008ea4: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008ea8: f04f 0300 mov.w r3, #0 8008eac: 3a01 subs r2, #1 8008eae: dc5d bgt.n 8008f6c <__aeabi_fmul+0x150> 8008eb0: f112 0f19 cmn.w r2, #25 8008eb4: bfdc itt le 8008eb6: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000 8008eba: 4770 bxle lr 8008ebc: f1c2 0200 rsb r2, r2, #0 8008ec0: 0041 lsls r1, r0, #1 8008ec2: fa21 f102 lsr.w r1, r1, r2 8008ec6: f1c2 0220 rsb r2, r2, #32 8008eca: fa00 fc02 lsl.w ip, r0, r2 8008ece: ea5f 0031 movs.w r0, r1, rrx 8008ed2: f140 0000 adc.w r0, r0, #0 8008ed6: ea53 034c orrs.w r3, r3, ip, lsl #1 8008eda: bf08 it eq 8008edc: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008ee0: 4770 bx lr 8008ee2: f092 0f00 teq r2, #0 8008ee6: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8008eea: bf02 ittt eq 8008eec: 0040 lsleq r0, r0, #1 8008eee: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 8008ef2: 3a01 subeq r2, #1 8008ef4: d0f9 beq.n 8008eea <__aeabi_fmul+0xce> 8008ef6: ea40 000c orr.w r0, r0, ip 8008efa: f093 0f00 teq r3, #0 8008efe: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008f02: bf02 ittt eq 8008f04: 0049 lsleq r1, r1, #1 8008f06: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8008f0a: 3b01 subeq r3, #1 8008f0c: d0f9 beq.n 8008f02 <__aeabi_fmul+0xe6> 8008f0e: ea41 010c orr.w r1, r1, ip 8008f12: e78f b.n 8008e34 <__aeabi_fmul+0x18> 8008f14: ea0c 53d1 and.w r3, ip, r1, lsr #23 8008f18: ea92 0f0c teq r2, ip 8008f1c: bf18 it ne 8008f1e: ea93 0f0c teqne r3, ip 8008f22: d00a beq.n 8008f3a <__aeabi_fmul+0x11e> 8008f24: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 8008f28: bf18 it ne 8008f2a: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 8008f2e: d1d8 bne.n 8008ee2 <__aeabi_fmul+0xc6> 8008f30: ea80 0001 eor.w r0, r0, r1 8008f34: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008f38: 4770 bx lr 8008f3a: f090 0f00 teq r0, #0 8008f3e: bf17 itett ne 8008f40: f090 4f00 teqne r0, #2147483648 @ 0x80000000 8008f44: 4608 moveq r0, r1 8008f46: f091 0f00 teqne r1, #0 8008f4a: f091 4f00 teqne r1, #2147483648 @ 0x80000000 8008f4e: d014 beq.n 8008f7a <__aeabi_fmul+0x15e> 8008f50: ea92 0f0c teq r2, ip 8008f54: d101 bne.n 8008f5a <__aeabi_fmul+0x13e> 8008f56: 0242 lsls r2, r0, #9 8008f58: d10f bne.n 8008f7a <__aeabi_fmul+0x15e> 8008f5a: ea93 0f0c teq r3, ip 8008f5e: d103 bne.n 8008f68 <__aeabi_fmul+0x14c> 8008f60: 024b lsls r3, r1, #9 8008f62: bf18 it ne 8008f64: 4608 movne r0, r1 8008f66: d108 bne.n 8008f7a <__aeabi_fmul+0x15e> 8008f68: ea80 0001 eor.w r0, r0, r1 8008f6c: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008f70: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008f74: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008f78: 4770 bx lr 8008f7a: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008f7e: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000 8008f82: 4770 bx lr 08008f84 <__aeabi_fdiv>: 8008f84: f04f 0cff mov.w ip, #255 @ 0xff 8008f88: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008f8c: bf1e ittt ne 8008f8e: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008f92: ea92 0f0c teqne r2, ip 8008f96: ea93 0f0c teqne r3, ip 8008f9a: d069 beq.n 8009070 <__aeabi_fdiv+0xec> 8008f9c: eba2 0203 sub.w r2, r2, r3 8008fa0: ea80 0c01 eor.w ip, r0, r1 8008fa4: 0249 lsls r1, r1, #9 8008fa6: ea4f 2040 mov.w r0, r0, lsl #9 8008faa: d037 beq.n 800901c <__aeabi_fdiv+0x98> 8008fac: f04f 5380 mov.w r3, #268435456 @ 0x10000000 8008fb0: ea43 1111 orr.w r1, r3, r1, lsr #4 8008fb4: ea43 1310 orr.w r3, r3, r0, lsr #4 8008fb8: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008fbc: 428b cmp r3, r1 8008fbe: bf38 it cc 8008fc0: 005b lslcc r3, r3, #1 8008fc2: f142 027d adc.w r2, r2, #125 @ 0x7d 8008fc6: f44f 0c00 mov.w ip, #8388608 @ 0x800000 8008fca: 428b cmp r3, r1 8008fcc: bf24 itt cs 8008fce: 1a5b subcs r3, r3, r1 8008fd0: ea40 000c orrcs.w r0, r0, ip 8008fd4: ebb3 0f51 cmp.w r3, r1, lsr #1 8008fd8: bf24 itt cs 8008fda: eba3 0351 subcs.w r3, r3, r1, lsr #1 8008fde: ea40 005c orrcs.w r0, r0, ip, lsr #1 8008fe2: ebb3 0f91 cmp.w r3, r1, lsr #2 8008fe6: bf24 itt cs 8008fe8: eba3 0391 subcs.w r3, r3, r1, lsr #2 8008fec: ea40 009c orrcs.w r0, r0, ip, lsr #2 8008ff0: ebb3 0fd1 cmp.w r3, r1, lsr #3 8008ff4: bf24 itt cs 8008ff6: eba3 03d1 subcs.w r3, r3, r1, lsr #3 8008ffa: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8008ffe: 011b lsls r3, r3, #4 8009000: bf18 it ne 8009002: ea5f 1c1c movsne.w ip, ip, lsr #4 8009006: d1e0 bne.n 8008fca <__aeabi_fdiv+0x46> 8009008: 2afd cmp r2, #253 @ 0xfd 800900a: f63f af50 bhi.w 8008eae <__aeabi_fmul+0x92> 800900e: 428b cmp r3, r1 8009010: eb40 50c2 adc.w r0, r0, r2, lsl #23 8009014: bf08 it eq 8009016: f020 0001 biceq.w r0, r0, #1 800901a: 4770 bx lr 800901c: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8009020: ea4c 2050 orr.w r0, ip, r0, lsr #9 8009024: 327f adds r2, #127 @ 0x7f 8009026: bfc2 ittt gt 8009028: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 800902c: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8009030: 4770 bxgt lr 8009032: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8009036: f04f 0300 mov.w r3, #0 800903a: 3a01 subs r2, #1 800903c: e737 b.n 8008eae <__aeabi_fmul+0x92> 800903e: f092 0f00 teq r2, #0 8009042: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8009046: bf02 ittt eq 8009048: 0040 lsleq r0, r0, #1 800904a: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 800904e: 3a01 subeq r2, #1 8009050: d0f9 beq.n 8009046 <__aeabi_fdiv+0xc2> 8009052: ea40 000c orr.w r0, r0, ip 8009056: f093 0f00 teq r3, #0 800905a: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 800905e: bf02 ittt eq 8009060: 0049 lsleq r1, r1, #1 8009062: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8009066: 3b01 subeq r3, #1 8009068: d0f9 beq.n 800905e <__aeabi_fdiv+0xda> 800906a: ea41 010c orr.w r1, r1, ip 800906e: e795 b.n 8008f9c <__aeabi_fdiv+0x18> 8009070: ea0c 53d1 and.w r3, ip, r1, lsr #23 8009074: ea92 0f0c teq r2, ip 8009078: d108 bne.n 800908c <__aeabi_fdiv+0x108> 800907a: 0242 lsls r2, r0, #9 800907c: f47f af7d bne.w 8008f7a <__aeabi_fmul+0x15e> 8009080: ea93 0f0c teq r3, ip 8009084: f47f af70 bne.w 8008f68 <__aeabi_fmul+0x14c> 8009088: 4608 mov r0, r1 800908a: e776 b.n 8008f7a <__aeabi_fmul+0x15e> 800908c: ea93 0f0c teq r3, ip 8009090: d104 bne.n 800909c <__aeabi_fdiv+0x118> 8009092: 024b lsls r3, r1, #9 8009094: f43f af4c beq.w 8008f30 <__aeabi_fmul+0x114> 8009098: 4608 mov r0, r1 800909a: e76e b.n 8008f7a <__aeabi_fmul+0x15e> 800909c: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 80090a0: bf18 it ne 80090a2: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 80090a6: d1ca bne.n 800903e <__aeabi_fdiv+0xba> 80090a8: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000 80090ac: f47f af5c bne.w 8008f68 <__aeabi_fmul+0x14c> 80090b0: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000 80090b4: f47f af3c bne.w 8008f30 <__aeabi_fmul+0x114> 80090b8: e75f b.n 8008f7a <__aeabi_fmul+0x15e> 80090ba: bf00 nop 080090bc <__gesf2>: 80090bc: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80090c0: e006 b.n 80090d0 <__cmpsf2+0x4> 80090c2: bf00 nop 080090c4 <__lesf2>: 80090c4: f04f 0c01 mov.w ip, #1 80090c8: e002 b.n 80090d0 <__cmpsf2+0x4> 80090ca: bf00 nop 080090cc <__cmpsf2>: 80090cc: f04f 0c01 mov.w ip, #1 80090d0: f84d cd04 str.w ip, [sp, #-4]! 80090d4: ea4f 0240 mov.w r2, r0, lsl #1 80090d8: ea4f 0341 mov.w r3, r1, lsl #1 80090dc: ea7f 6c22 mvns.w ip, r2, asr #24 80090e0: bf18 it ne 80090e2: ea7f 6c23 mvnsne.w ip, r3, asr #24 80090e6: d011 beq.n 800910c <__cmpsf2+0x40> 80090e8: b001 add sp, #4 80090ea: ea52 0c53 orrs.w ip, r2, r3, lsr #1 80090ee: bf18 it ne 80090f0: ea90 0f01 teqne r0, r1 80090f4: bf58 it pl 80090f6: ebb2 0003 subspl.w r0, r2, r3 80090fa: bf88 it hi 80090fc: 17c8 asrhi r0, r1, #31 80090fe: bf38 it cc 8009100: ea6f 70e1 mvncc.w r0, r1, asr #31 8009104: bf18 it ne 8009106: f040 0001 orrne.w r0, r0, #1 800910a: 4770 bx lr 800910c: ea7f 6c22 mvns.w ip, r2, asr #24 8009110: d102 bne.n 8009118 <__cmpsf2+0x4c> 8009112: ea5f 2c40 movs.w ip, r0, lsl #9 8009116: d105 bne.n 8009124 <__cmpsf2+0x58> 8009118: ea7f 6c23 mvns.w ip, r3, asr #24 800911c: d1e4 bne.n 80090e8 <__cmpsf2+0x1c> 800911e: ea5f 2c41 movs.w ip, r1, lsl #9 8009122: d0e1 beq.n 80090e8 <__cmpsf2+0x1c> 8009124: f85d 0b04 ldr.w r0, [sp], #4 8009128: 4770 bx lr 800912a: bf00 nop 0800912c <__aeabi_cfrcmple>: 800912c: 4684 mov ip, r0 800912e: 4608 mov r0, r1 8009130: 4661 mov r1, ip 8009132: e7ff b.n 8009134 <__aeabi_cfcmpeq> 08009134 <__aeabi_cfcmpeq>: 8009134: b50f push {r0, r1, r2, r3, lr} 8009136: f7ff ffc9 bl 80090cc <__cmpsf2> 800913a: 2800 cmp r0, #0 800913c: bf48 it mi 800913e: f110 0f00 cmnmi.w r0, #0 8009142: bd0f pop {r0, r1, r2, r3, pc} 08009144 <__aeabi_fcmpeq>: 8009144: f84d ed08 str.w lr, [sp, #-8]! 8009148: f7ff fff4 bl 8009134 <__aeabi_cfcmpeq> 800914c: bf0c ite eq 800914e: 2001 moveq r0, #1 8009150: 2000 movne r0, #0 8009152: f85d fb08 ldr.w pc, [sp], #8 8009156: bf00 nop 08009158 <__aeabi_fcmplt>: 8009158: f84d ed08 str.w lr, [sp, #-8]! 800915c: f7ff ffea bl 8009134 <__aeabi_cfcmpeq> 8009160: bf34 ite cc 8009162: 2001 movcc r0, #1 8009164: 2000 movcs r0, #0 8009166: f85d fb08 ldr.w pc, [sp], #8 800916a: bf00 nop 0800916c <__aeabi_fcmple>: 800916c: f84d ed08 str.w lr, [sp, #-8]! 8009170: f7ff ffe0 bl 8009134 <__aeabi_cfcmpeq> 8009174: bf94 ite ls 8009176: 2001 movls r0, #1 8009178: 2000 movhi r0, #0 800917a: f85d fb08 ldr.w pc, [sp], #8 800917e: bf00 nop 08009180 <__aeabi_fcmpge>: 8009180: f84d ed08 str.w lr, [sp, #-8]! 8009184: f7ff ffd2 bl 800912c <__aeabi_cfrcmple> 8009188: bf94 ite ls 800918a: 2001 movls r0, #1 800918c: 2000 movhi r0, #0 800918e: f85d fb08 ldr.w pc, [sp], #8 8009192: bf00 nop 08009194 <__aeabi_fcmpgt>: 8009194: f84d ed08 str.w lr, [sp, #-8]! 8009198: f7ff ffc8 bl 800912c <__aeabi_cfrcmple> 800919c: bf34 ite cc 800919e: 2001 movcc r0, #1 80091a0: 2000 movcs r0, #0 80091a2: f85d fb08 ldr.w pc, [sp], #8 80091a6: bf00 nop 080091a8 <__aeabi_f2iz>: 80091a8: ea4f 0240 mov.w r2, r0, lsl #1 80091ac: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000 80091b0: d30f bcc.n 80091d2 <__aeabi_f2iz+0x2a> 80091b2: f04f 039e mov.w r3, #158 @ 0x9e 80091b6: ebb3 6212 subs.w r2, r3, r2, lsr #24 80091ba: d90d bls.n 80091d8 <__aeabi_f2iz+0x30> 80091bc: ea4f 2300 mov.w r3, r0, lsl #8 80091c0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80091c4: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 80091c8: fa23 f002 lsr.w r0, r3, r2 80091cc: bf18 it ne 80091ce: 4240 negne r0, r0 80091d0: 4770 bx lr 80091d2: f04f 0000 mov.w r0, #0 80091d6: 4770 bx lr 80091d8: f112 0f61 cmn.w r2, #97 @ 0x61 80091dc: d101 bne.n 80091e2 <__aeabi_f2iz+0x3a> 80091de: 0242 lsls r2, r0, #9 80091e0: d105 bne.n 80091ee <__aeabi_f2iz+0x46> 80091e2: f010 4000 ands.w r0, r0, #2147483648 @ 0x80000000 80091e6: bf08 it eq 80091e8: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 80091ec: 4770 bx lr 80091ee: f04f 0000 mov.w r0, #0 80091f2: 4770 bx lr 080091f4 <__aeabi_uldivmod>: 80091f4: b953 cbnz r3, 800920c <__aeabi_uldivmod+0x18> 80091f6: b94a cbnz r2, 800920c <__aeabi_uldivmod+0x18> 80091f8: 2900 cmp r1, #0 80091fa: bf08 it eq 80091fc: 2800 cmpeq r0, #0 80091fe: bf1c itt ne 8009200: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8009204: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8009208: f000 b98c b.w 8009524 <__aeabi_idiv0> 800920c: f1ad 0c08 sub.w ip, sp, #8 8009210: e96d ce04 strd ip, lr, [sp, #-16]! 8009214: f000 f806 bl 8009224 <__udivmoddi4> 8009218: f8dd e004 ldr.w lr, [sp, #4] 800921c: e9dd 2302 ldrd r2, r3, [sp, #8] 8009220: b004 add sp, #16 8009222: 4770 bx lr 08009224 <__udivmoddi4>: 8009224: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8009228: 9d08 ldr r5, [sp, #32] 800922a: 468e mov lr, r1 800922c: 4604 mov r4, r0 800922e: 4688 mov r8, r1 8009230: 2b00 cmp r3, #0 8009232: d14a bne.n 80092ca <__udivmoddi4+0xa6> 8009234: 428a cmp r2, r1 8009236: 4617 mov r7, r2 8009238: d962 bls.n 8009300 <__udivmoddi4+0xdc> 800923a: fab2 f682 clz r6, r2 800923e: b14e cbz r6, 8009254 <__udivmoddi4+0x30> 8009240: f1c6 0320 rsb r3, r6, #32 8009244: fa01 f806 lsl.w r8, r1, r6 8009248: fa20 f303 lsr.w r3, r0, r3 800924c: 40b7 lsls r7, r6 800924e: ea43 0808 orr.w r8, r3, r8 8009252: 40b4 lsls r4, r6 8009254: ea4f 4e17 mov.w lr, r7, lsr #16 8009258: fbb8 f1fe udiv r1, r8, lr 800925c: fa1f fc87 uxth.w ip, r7 8009260: fb0e 8811 mls r8, lr, r1, r8 8009264: fb01 f20c mul.w r2, r1, ip 8009268: 0c23 lsrs r3, r4, #16 800926a: ea43 4308 orr.w r3, r3, r8, lsl #16 800926e: 429a cmp r2, r3 8009270: d909 bls.n 8009286 <__udivmoddi4+0x62> 8009272: 18fb adds r3, r7, r3 8009274: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8009278: f080 80eb bcs.w 8009452 <__udivmoddi4+0x22e> 800927c: 429a cmp r2, r3 800927e: f240 80e8 bls.w 8009452 <__udivmoddi4+0x22e> 8009282: 3902 subs r1, #2 8009284: 443b add r3, r7 8009286: 1a9a subs r2, r3, r2 8009288: fbb2 f0fe udiv r0, r2, lr 800928c: fb0e 2210 mls r2, lr, r0, r2 8009290: fb00 fc0c mul.w ip, r0, ip 8009294: b2a3 uxth r3, r4 8009296: ea43 4302 orr.w r3, r3, r2, lsl #16 800929a: 459c cmp ip, r3 800929c: d909 bls.n 80092b2 <__udivmoddi4+0x8e> 800929e: 18fb adds r3, r7, r3 80092a0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80092a4: f080 80d7 bcs.w 8009456 <__udivmoddi4+0x232> 80092a8: 459c cmp ip, r3 80092aa: f240 80d4 bls.w 8009456 <__udivmoddi4+0x232> 80092ae: 443b add r3, r7 80092b0: 3802 subs r0, #2 80092b2: ea40 4001 orr.w r0, r0, r1, lsl #16 80092b6: 2100 movs r1, #0 80092b8: eba3 030c sub.w r3, r3, ip 80092bc: b11d cbz r5, 80092c6 <__udivmoddi4+0xa2> 80092be: 2200 movs r2, #0 80092c0: 40f3 lsrs r3, r6 80092c2: e9c5 3200 strd r3, r2, [r5] 80092c6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80092ca: 428b cmp r3, r1 80092cc: d905 bls.n 80092da <__udivmoddi4+0xb6> 80092ce: b10d cbz r5, 80092d4 <__udivmoddi4+0xb0> 80092d0: e9c5 0100 strd r0, r1, [r5] 80092d4: 2100 movs r1, #0 80092d6: 4608 mov r0, r1 80092d8: e7f5 b.n 80092c6 <__udivmoddi4+0xa2> 80092da: fab3 f183 clz r1, r3 80092de: 2900 cmp r1, #0 80092e0: d146 bne.n 8009370 <__udivmoddi4+0x14c> 80092e2: 4573 cmp r3, lr 80092e4: d302 bcc.n 80092ec <__udivmoddi4+0xc8> 80092e6: 4282 cmp r2, r0 80092e8: f200 8108 bhi.w 80094fc <__udivmoddi4+0x2d8> 80092ec: 1a84 subs r4, r0, r2 80092ee: eb6e 0203 sbc.w r2, lr, r3 80092f2: 2001 movs r0, #1 80092f4: 4690 mov r8, r2 80092f6: 2d00 cmp r5, #0 80092f8: d0e5 beq.n 80092c6 <__udivmoddi4+0xa2> 80092fa: e9c5 4800 strd r4, r8, [r5] 80092fe: e7e2 b.n 80092c6 <__udivmoddi4+0xa2> 8009300: 2a00 cmp r2, #0 8009302: f000 8091 beq.w 8009428 <__udivmoddi4+0x204> 8009306: fab2 f682 clz r6, r2 800930a: 2e00 cmp r6, #0 800930c: f040 80a5 bne.w 800945a <__udivmoddi4+0x236> 8009310: 1a8a subs r2, r1, r2 8009312: 2101 movs r1, #1 8009314: 0c03 lsrs r3, r0, #16 8009316: ea4f 4e17 mov.w lr, r7, lsr #16 800931a: b280 uxth r0, r0 800931c: b2bc uxth r4, r7 800931e: fbb2 fcfe udiv ip, r2, lr 8009322: fb0e 221c mls r2, lr, ip, r2 8009326: ea43 4302 orr.w r3, r3, r2, lsl #16 800932a: fb04 f20c mul.w r2, r4, ip 800932e: 429a cmp r2, r3 8009330: d907 bls.n 8009342 <__udivmoddi4+0x11e> 8009332: 18fb adds r3, r7, r3 8009334: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8009338: d202 bcs.n 8009340 <__udivmoddi4+0x11c> 800933a: 429a cmp r2, r3 800933c: f200 80e3 bhi.w 8009506 <__udivmoddi4+0x2e2> 8009340: 46c4 mov ip, r8 8009342: 1a9b subs r3, r3, r2 8009344: fbb3 f2fe udiv r2, r3, lr 8009348: fb0e 3312 mls r3, lr, r2, r3 800934c: fb02 f404 mul.w r4, r2, r4 8009350: ea40 4303 orr.w r3, r0, r3, lsl #16 8009354: 429c cmp r4, r3 8009356: d907 bls.n 8009368 <__udivmoddi4+0x144> 8009358: 18fb adds r3, r7, r3 800935a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800935e: d202 bcs.n 8009366 <__udivmoddi4+0x142> 8009360: 429c cmp r4, r3 8009362: f200 80cd bhi.w 8009500 <__udivmoddi4+0x2dc> 8009366: 4602 mov r2, r0 8009368: 1b1b subs r3, r3, r4 800936a: ea42 400c orr.w r0, r2, ip, lsl #16 800936e: e7a5 b.n 80092bc <__udivmoddi4+0x98> 8009370: f1c1 0620 rsb r6, r1, #32 8009374: 408b lsls r3, r1 8009376: fa22 f706 lsr.w r7, r2, r6 800937a: 431f orrs r7, r3 800937c: fa2e fa06 lsr.w sl, lr, r6 8009380: ea4f 4917 mov.w r9, r7, lsr #16 8009384: fbba f8f9 udiv r8, sl, r9 8009388: fa0e fe01 lsl.w lr, lr, r1 800938c: fa20 f306 lsr.w r3, r0, r6 8009390: fb09 aa18 mls sl, r9, r8, sl 8009394: fa1f fc87 uxth.w ip, r7 8009398: ea43 030e orr.w r3, r3, lr 800939c: fa00 fe01 lsl.w lr, r0, r1 80093a0: fb08 f00c mul.w r0, r8, ip 80093a4: 0c1c lsrs r4, r3, #16 80093a6: ea44 440a orr.w r4, r4, sl, lsl #16 80093aa: 42a0 cmp r0, r4 80093ac: fa02 f201 lsl.w r2, r2, r1 80093b0: d90a bls.n 80093c8 <__udivmoddi4+0x1a4> 80093b2: 193c adds r4, r7, r4 80093b4: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff 80093b8: f080 809e bcs.w 80094f8 <__udivmoddi4+0x2d4> 80093bc: 42a0 cmp r0, r4 80093be: f240 809b bls.w 80094f8 <__udivmoddi4+0x2d4> 80093c2: f1a8 0802 sub.w r8, r8, #2 80093c6: 443c add r4, r7 80093c8: 1a24 subs r4, r4, r0 80093ca: b298 uxth r0, r3 80093cc: fbb4 f3f9 udiv r3, r4, r9 80093d0: fb09 4413 mls r4, r9, r3, r4 80093d4: fb03 fc0c mul.w ip, r3, ip 80093d8: ea40 4404 orr.w r4, r0, r4, lsl #16 80093dc: 45a4 cmp ip, r4 80093de: d909 bls.n 80093f4 <__udivmoddi4+0x1d0> 80093e0: 193c adds r4, r7, r4 80093e2: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 80093e6: f080 8085 bcs.w 80094f4 <__udivmoddi4+0x2d0> 80093ea: 45a4 cmp ip, r4 80093ec: f240 8082 bls.w 80094f4 <__udivmoddi4+0x2d0> 80093f0: 3b02 subs r3, #2 80093f2: 443c add r4, r7 80093f4: ea43 4008 orr.w r0, r3, r8, lsl #16 80093f8: eba4 040c sub.w r4, r4, ip 80093fc: fba0 8c02 umull r8, ip, r0, r2 8009400: 4564 cmp r4, ip 8009402: 4643 mov r3, r8 8009404: 46e1 mov r9, ip 8009406: d364 bcc.n 80094d2 <__udivmoddi4+0x2ae> 8009408: d061 beq.n 80094ce <__udivmoddi4+0x2aa> 800940a: b15d cbz r5, 8009424 <__udivmoddi4+0x200> 800940c: ebbe 0203 subs.w r2, lr, r3 8009410: eb64 0409 sbc.w r4, r4, r9 8009414: fa04 f606 lsl.w r6, r4, r6 8009418: fa22 f301 lsr.w r3, r2, r1 800941c: 431e orrs r6, r3 800941e: 40cc lsrs r4, r1 8009420: e9c5 6400 strd r6, r4, [r5] 8009424: 2100 movs r1, #0 8009426: e74e b.n 80092c6 <__udivmoddi4+0xa2> 8009428: fbb1 fcf2 udiv ip, r1, r2 800942c: 0c01 lsrs r1, r0, #16 800942e: ea41 410e orr.w r1, r1, lr, lsl #16 8009432: b280 uxth r0, r0 8009434: ea40 4201 orr.w r2, r0, r1, lsl #16 8009438: 463b mov r3, r7 800943a: fbb1 f1f7 udiv r1, r1, r7 800943e: 4638 mov r0, r7 8009440: 463c mov r4, r7 8009442: 46b8 mov r8, r7 8009444: 46be mov lr, r7 8009446: 2620 movs r6, #32 8009448: eba2 0208 sub.w r2, r2, r8 800944c: ea41 410c orr.w r1, r1, ip, lsl #16 8009450: e765 b.n 800931e <__udivmoddi4+0xfa> 8009452: 4601 mov r1, r0 8009454: e717 b.n 8009286 <__udivmoddi4+0x62> 8009456: 4610 mov r0, r2 8009458: e72b b.n 80092b2 <__udivmoddi4+0x8e> 800945a: f1c6 0120 rsb r1, r6, #32 800945e: fa2e fc01 lsr.w ip, lr, r1 8009462: 40b7 lsls r7, r6 8009464: fa0e fe06 lsl.w lr, lr, r6 8009468: fa20 f101 lsr.w r1, r0, r1 800946c: ea41 010e orr.w r1, r1, lr 8009470: ea4f 4e17 mov.w lr, r7, lsr #16 8009474: fbbc f8fe udiv r8, ip, lr 8009478: b2bc uxth r4, r7 800947a: fb0e cc18 mls ip, lr, r8, ip 800947e: fb08 f904 mul.w r9, r8, r4 8009482: 0c0a lsrs r2, r1, #16 8009484: ea42 420c orr.w r2, r2, ip, lsl #16 8009488: 40b0 lsls r0, r6 800948a: 4591 cmp r9, r2 800948c: ea4f 4310 mov.w r3, r0, lsr #16 8009490: b280 uxth r0, r0 8009492: d93e bls.n 8009512 <__udivmoddi4+0x2ee> 8009494: 18ba adds r2, r7, r2 8009496: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 800949a: d201 bcs.n 80094a0 <__udivmoddi4+0x27c> 800949c: 4591 cmp r9, r2 800949e: d81f bhi.n 80094e0 <__udivmoddi4+0x2bc> 80094a0: eba2 0209 sub.w r2, r2, r9 80094a4: fbb2 f9fe udiv r9, r2, lr 80094a8: fb09 f804 mul.w r8, r9, r4 80094ac: fb0e 2a19 mls sl, lr, r9, r2 80094b0: b28a uxth r2, r1 80094b2: ea42 420a orr.w r2, r2, sl, lsl #16 80094b6: 4542 cmp r2, r8 80094b8: d229 bcs.n 800950e <__udivmoddi4+0x2ea> 80094ba: 18ba adds r2, r7, r2 80094bc: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80094c0: d2c2 bcs.n 8009448 <__udivmoddi4+0x224> 80094c2: 4542 cmp r2, r8 80094c4: d2c0 bcs.n 8009448 <__udivmoddi4+0x224> 80094c6: f1a9 0102 sub.w r1, r9, #2 80094ca: 443a add r2, r7 80094cc: e7bc b.n 8009448 <__udivmoddi4+0x224> 80094ce: 45c6 cmp lr, r8 80094d0: d29b bcs.n 800940a <__udivmoddi4+0x1e6> 80094d2: ebb8 0302 subs.w r3, r8, r2 80094d6: eb6c 0c07 sbc.w ip, ip, r7 80094da: 3801 subs r0, #1 80094dc: 46e1 mov r9, ip 80094de: e794 b.n 800940a <__udivmoddi4+0x1e6> 80094e0: eba7 0909 sub.w r9, r7, r9 80094e4: 444a add r2, r9 80094e6: fbb2 f9fe udiv r9, r2, lr 80094ea: f1a8 0c02 sub.w ip, r8, #2 80094ee: fb09 f804 mul.w r8, r9, r4 80094f2: e7db b.n 80094ac <__udivmoddi4+0x288> 80094f4: 4603 mov r3, r0 80094f6: e77d b.n 80093f4 <__udivmoddi4+0x1d0> 80094f8: 46d0 mov r8, sl 80094fa: e765 b.n 80093c8 <__udivmoddi4+0x1a4> 80094fc: 4608 mov r0, r1 80094fe: e6fa b.n 80092f6 <__udivmoddi4+0xd2> 8009500: 443b add r3, r7 8009502: 3a02 subs r2, #2 8009504: e730 b.n 8009368 <__udivmoddi4+0x144> 8009506: f1ac 0c02 sub.w ip, ip, #2 800950a: 443b add r3, r7 800950c: e719 b.n 8009342 <__udivmoddi4+0x11e> 800950e: 4649 mov r1, r9 8009510: e79a b.n 8009448 <__udivmoddi4+0x224> 8009512: eba2 0209 sub.w r2, r2, r9 8009516: fbb2 f9fe udiv r9, r2, lr 800951a: 46c4 mov ip, r8 800951c: fb09 f804 mul.w r8, r9, r4 8009520: e7c4 b.n 80094ac <__udivmoddi4+0x288> 8009522: bf00 nop 08009524 <__aeabi_idiv0>: 8009524: 4770 bx lr 8009526: bf00 nop 08009528 : static volatile uint16_t adc_dma_raw[6]; volatile ADC_ScanData_t adc_data = {0}; static volatile uint8_t adc_scan_data_ready = 0u; void ADC_ScanStart(void) { 8009528: b580 push {r7, lr} 800952a: af00 add r7, sp, #0 if (HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc_dma_raw, 6u) != HAL_OK) 800952c: 2206 movs r2, #6 800952e: 4905 ldr r1, [pc, #20] @ (8009544 ) 8009530: 4805 ldr r0, [pc, #20] @ (8009548 ) 8009532: f005 f807 bl 800e544 8009536: 4603 mov r3, r0 8009538: 2b00 cmp r3, #0 800953a: d001 beq.n 8009540 { Error_Handler(); 800953c: f001 fba2 bl 800ac84 } } 8009540: bf00 nop 8009542: bd80 pop {r7, pc} 8009544: 20000274 .word 0x20000274 8009548: 20000290 .word 0x20000290 0800954c : ISR_FAST void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { if (hadc->Instance != ADC1) 800954c: 4b0e ldr r3, [pc, #56] @ (8009588 ) 800954e: 6802 ldr r2, [r0, #0] 8009550: 429a cmp r2, r3 8009552: d118 bne.n 8009586 adc_data.cp_raw = adc_dma_raw[1]; adc_data.ntc1_raw = adc_dma_raw[2]; adc_data.ntc2_raw = adc_dma_raw[3]; adc_data.temp_sensor_raw = adc_dma_raw[4]; adc_data.vrefint_raw = adc_dma_raw[5]; adc_scan_data_ready = 1u; 8009554: f04f 0c01 mov.w ip, #1 adc_data.in3_raw = adc_dma_raw[0]; 8009558: 4a0c ldr r2, [pc, #48] @ (800958c ) 800955a: 4b0d ldr r3, [pc, #52] @ (8009590 ) 800955c: 8811 ldrh r1, [r2, #0] adc_scan_data_ready = 1u; 800955e: 480d ldr r0, [pc, #52] @ (8009594 ) adc_data.in3_raw = adc_dma_raw[0]; 8009560: b289 uxth r1, r1 8009562: 8019 strh r1, [r3, #0] adc_data.cp_raw = adc_dma_raw[1]; 8009564: 8851 ldrh r1, [r2, #2] 8009566: b289 uxth r1, r1 8009568: 8059 strh r1, [r3, #2] adc_data.ntc1_raw = adc_dma_raw[2]; 800956a: 8891 ldrh r1, [r2, #4] 800956c: b289 uxth r1, r1 800956e: 8099 strh r1, [r3, #4] adc_data.ntc2_raw = adc_dma_raw[3]; 8009570: 88d1 ldrh r1, [r2, #6] 8009572: b289 uxth r1, r1 8009574: 80d9 strh r1, [r3, #6] adc_data.temp_sensor_raw = adc_dma_raw[4]; 8009576: 8911 ldrh r1, [r2, #8] 8009578: b289 uxth r1, r1 800957a: 8119 strh r1, [r3, #8] adc_data.vrefint_raw = adc_dma_raw[5]; 800957c: 8952 ldrh r2, [r2, #10] 800957e: b292 uxth r2, r2 8009580: 815a strh r2, [r3, #10] adc_scan_data_ready = 1u; 8009582: f880 c000 strb.w ip, [r0] } 8009586: 4770 bx lr 8009588: 40012400 .word 0x40012400 800958c: 20000274 .word 0x20000274 8009590: 20000280 .word 0x20000280 8009594: 2000028c .word 0x2000028c 08009598 : ADC_HandleTypeDef hadc1; DMA_HandleTypeDef hdma_adc1; /* ADC1 init function */ void MX_ADC1_Init(void) { 8009598: b580 push {r7, lr} 800959a: b084 sub sp, #16 800959c: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 800959e: 1d3b adds r3, r7, #4 80095a0: 2200 movs r2, #0 80095a2: 601a str r2, [r3, #0] 80095a4: 605a str r2, [r3, #4] 80095a6: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 80095a8: 4b3c ldr r3, [pc, #240] @ (800969c ) 80095aa: 4a3d ldr r2, [pc, #244] @ (80096a0 ) 80095ac: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 80095ae: 4b3b ldr r3, [pc, #236] @ (800969c ) 80095b0: f44f 7280 mov.w r2, #256 @ 0x100 80095b4: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = DISABLE; 80095b6: 4b39 ldr r3, [pc, #228] @ (800969c ) 80095b8: 2200 movs r2, #0 80095ba: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 80095bc: 4b37 ldr r3, [pc, #220] @ (800969c ) 80095be: 2200 movs r2, #0 80095c0: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T3_TRGO; 80095c2: 4b36 ldr r3, [pc, #216] @ (800969c ) 80095c4: f44f 2200 mov.w r2, #524288 @ 0x80000 80095c8: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80095ca: 4b34 ldr r3, [pc, #208] @ (800969c ) 80095cc: 2200 movs r2, #0 80095ce: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 6; 80095d0: 4b32 ldr r3, [pc, #200] @ (800969c ) 80095d2: 2206 movs r2, #6 80095d4: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 80095d6: 4831 ldr r0, [pc, #196] @ (800969c ) 80095d8: f004 fedc bl 800e394 80095dc: 4603 mov r3, r0 80095de: 2b00 cmp r3, #0 80095e0: d001 beq.n 80095e6 { Error_Handler(); 80095e2: f001 fb4f bl 800ac84 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 80095e6: 2303 movs r3, #3 80095e8: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 80095ea: 2301 movs r3, #1 80095ec: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_41CYCLES_5; 80095ee: 2304 movs r3, #4 80095f0: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80095f2: 1d3b adds r3, r7, #4 80095f4: 4619 mov r1, r3 80095f6: 4829 ldr r0, [pc, #164] @ (800969c ) 80095f8: f005 f95c bl 800e8b4 80095fc: 4603 mov r3, r0 80095fe: 2b00 cmp r3, #0 8009600: d001 beq.n 8009606 { Error_Handler(); 8009602: f001 fb3f bl 800ac84 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8009606: 2304 movs r3, #4 8009608: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 800960a: 2302 movs r3, #2 800960c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800960e: 1d3b adds r3, r7, #4 8009610: 4619 mov r1, r3 8009612: 4822 ldr r0, [pc, #136] @ (800969c ) 8009614: f005 f94e bl 800e8b4 8009618: 4603 mov r3, r0 800961a: 2b00 cmp r3, #0 800961c: d001 beq.n 8009622 { Error_Handler(); 800961e: f001 fb31 bl 800ac84 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8009622: 2308 movs r3, #8 8009624: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8009626: 2303 movs r3, #3 8009628: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800962a: 1d3b adds r3, r7, #4 800962c: 4619 mov r1, r3 800962e: 481b ldr r0, [pc, #108] @ (800969c ) 8009630: f005 f940 bl 800e8b4 8009634: 4603 mov r3, r0 8009636: 2b00 cmp r3, #0 8009638: d001 beq.n 800963e { Error_Handler(); 800963a: f001 fb23 bl 800ac84 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_9; 800963e: 2309 movs r3, #9 8009640: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_4; 8009642: 2304 movs r3, #4 8009644: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8009646: 1d3b adds r3, r7, #4 8009648: 4619 mov r1, r3 800964a: 4814 ldr r0, [pc, #80] @ (800969c ) 800964c: f005 f932 bl 800e8b4 8009650: 4603 mov r3, r0 8009652: 2b00 cmp r3, #0 8009654: d001 beq.n 800965a { Error_Handler(); 8009656: f001 fb15 bl 800ac84 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; 800965a: 2310 movs r3, #16 800965c: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_5; 800965e: 2305 movs r3, #5 8009660: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8009662: 1d3b adds r3, r7, #4 8009664: 4619 mov r1, r3 8009666: 480d ldr r0, [pc, #52] @ (800969c ) 8009668: f005 f924 bl 800e8b4 800966c: 4603 mov r3, r0 800966e: 2b00 cmp r3, #0 8009670: d001 beq.n 8009676 { Error_Handler(); 8009672: f001 fb07 bl 800ac84 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; 8009676: 2311 movs r3, #17 8009678: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_6; 800967a: 2306 movs r3, #6 800967c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800967e: 1d3b adds r3, r7, #4 8009680: 4619 mov r1, r3 8009682: 4806 ldr r0, [pc, #24] @ (800969c ) 8009684: f005 f916 bl 800e8b4 8009688: 4603 mov r3, r0 800968a: 2b00 cmp r3, #0 800968c: d001 beq.n 8009692 { Error_Handler(); 800968e: f001 faf9 bl 800ac84 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 8009692: bf00 nop 8009694: 3710 adds r7, #16 8009696: 46bd mov sp, r7 8009698: bd80 pop {r7, pc} 800969a: bf00 nop 800969c: 20000290 .word 0x20000290 80096a0: 40012400 .word 0x40012400 080096a4 : void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 80096a4: b580 push {r7, lr} 80096a6: b08a sub sp, #40 @ 0x28 80096a8: af00 add r7, sp, #0 80096aa: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80096ac: f107 0318 add.w r3, r7, #24 80096b0: 2200 movs r2, #0 80096b2: 601a str r2, [r3, #0] 80096b4: 605a str r2, [r3, #4] 80096b6: 609a str r2, [r3, #8] 80096b8: 60da str r2, [r3, #12] if(adcHandle->Instance==ADC1) 80096ba: 687b ldr r3, [r7, #4] 80096bc: 681b ldr r3, [r3, #0] 80096be: 4a38 ldr r2, [pc, #224] @ (80097a0 ) 80096c0: 4293 cmp r3, r2 80096c2: d168 bne.n 8009796 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 80096c4: 4b37 ldr r3, [pc, #220] @ (80097a4 ) 80096c6: 699b ldr r3, [r3, #24] 80096c8: 4a36 ldr r2, [pc, #216] @ (80097a4 ) 80096ca: f443 7300 orr.w r3, r3, #512 @ 0x200 80096ce: 6193 str r3, [r2, #24] 80096d0: 4b34 ldr r3, [pc, #208] @ (80097a4 ) 80096d2: 699b ldr r3, [r3, #24] 80096d4: f403 7300 and.w r3, r3, #512 @ 0x200 80096d8: 617b str r3, [r7, #20] 80096da: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 80096dc: 4b31 ldr r3, [pc, #196] @ (80097a4 ) 80096de: 699b ldr r3, [r3, #24] 80096e0: 4a30 ldr r2, [pc, #192] @ (80097a4 ) 80096e2: f043 0304 orr.w r3, r3, #4 80096e6: 6193 str r3, [r2, #24] 80096e8: 4b2e ldr r3, [pc, #184] @ (80097a4 ) 80096ea: 699b ldr r3, [r3, #24] 80096ec: f003 0304 and.w r3, r3, #4 80096f0: 613b str r3, [r7, #16] 80096f2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80096f4: 4b2b ldr r3, [pc, #172] @ (80097a4 ) 80096f6: 699b ldr r3, [r3, #24] 80096f8: 4a2a ldr r2, [pc, #168] @ (80097a4 ) 80096fa: f043 0308 orr.w r3, r3, #8 80096fe: 6193 str r3, [r2, #24] 8009700: 4b28 ldr r3, [pc, #160] @ (80097a4 ) 8009702: 699b ldr r3, [r3, #24] 8009704: f003 0308 and.w r3, r3, #8 8009708: 60fb str r3, [r7, #12] 800970a: 68fb ldr r3, [r7, #12] PA3 ------> ADC1_IN3 PA4 ------> ADC1_IN4 PB0 ------> ADC1_IN8 PB1 ------> ADC1_IN9 */ GPIO_InitStruct.Pin = GPIO_PIN_3|CP_ADC_Pin; 800970c: 2318 movs r3, #24 800970e: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009710: 2303 movs r3, #3 8009712: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8009714: f107 0318 add.w r3, r7, #24 8009718: 4619 mov r1, r3 800971a: 4823 ldr r0, [pc, #140] @ (80097a8 ) 800971c: f007 f808 bl 8010730 GPIO_InitStruct.Pin = ADC_NTC1_Pin|ADC_NTC2_Pin; 8009720: 2303 movs r3, #3 8009722: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009724: 2303 movs r3, #3 8009726: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009728: f107 0318 add.w r3, r7, #24 800972c: 4619 mov r1, r3 800972e: 481f ldr r0, [pc, #124] @ (80097ac ) 8009730: f006 fffe bl 8010730 /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; 8009734: 4b1e ldr r3, [pc, #120] @ (80097b0 ) 8009736: 4a1f ldr r2, [pc, #124] @ (80097b4 ) 8009738: 601a str r2, [r3, #0] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 800973a: 4b1d ldr r3, [pc, #116] @ (80097b0 ) 800973c: 2200 movs r2, #0 800973e: 605a str r2, [r3, #4] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8009740: 4b1b ldr r3, [pc, #108] @ (80097b0 ) 8009742: 2200 movs r2, #0 8009744: 609a str r2, [r3, #8] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8009746: 4b1a ldr r3, [pc, #104] @ (80097b0 ) 8009748: 2280 movs r2, #128 @ 0x80 800974a: 60da str r2, [r3, #12] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 800974c: 4b18 ldr r3, [pc, #96] @ (80097b0 ) 800974e: f44f 7280 mov.w r2, #256 @ 0x100 8009752: 611a str r2, [r3, #16] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8009754: 4b16 ldr r3, [pc, #88] @ (80097b0 ) 8009756: f44f 6280 mov.w r2, #1024 @ 0x400 800975a: 615a str r2, [r3, #20] hdma_adc1.Init.Mode = DMA_CIRCULAR; 800975c: 4b14 ldr r3, [pc, #80] @ (80097b0 ) 800975e: 2220 movs r2, #32 8009760: 619a str r2, [r3, #24] hdma_adc1.Init.Priority = DMA_PRIORITY_MEDIUM; 8009762: 4b13 ldr r3, [pc, #76] @ (80097b0 ) 8009764: f44f 5280 mov.w r2, #4096 @ 0x1000 8009768: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 800976a: 4811 ldr r0, [pc, #68] @ (80097b0 ) 800976c: f006 fb52 bl 800fe14 8009770: 4603 mov r3, r0 8009772: 2b00 cmp r3, #0 8009774: d001 beq.n 800977a { Error_Handler(); 8009776: f001 fa85 bl 800ac84 } __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1); 800977a: 687b ldr r3, [r7, #4] 800977c: 4a0c ldr r2, [pc, #48] @ (80097b0 ) 800977e: 621a str r2, [r3, #32] 8009780: 4a0b ldr r2, [pc, #44] @ (80097b0 ) 8009782: 687b ldr r3, [r7, #4] 8009784: 6253 str r3, [r2, #36] @ 0x24 /* ADC1 interrupt Init */ HAL_NVIC_SetPriority(ADC1_2_IRQn, 7, 0); 8009786: 2200 movs r2, #0 8009788: 2107 movs r1, #7 800978a: 2012 movs r0, #18 800978c: f006 faef bl 800fd6e HAL_NVIC_EnableIRQ(ADC1_2_IRQn); 8009790: 2012 movs r0, #18 8009792: f006 fb08 bl 800fda6 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8009796: bf00 nop 8009798: 3728 adds r7, #40 @ 0x28 800979a: 46bd mov sp, r7 800979c: bd80 pop {r7, pc} 800979e: bf00 nop 80097a0: 40012400 .word 0x40012400 80097a4: 40021000 .word 0x40021000 80097a8: 40010800 .word 0x40010800 80097ac: 40010c00 .word 0x40010c00 80097b0: 200002c0 .word 0x200002c0 80097b4: 40020008 .word 0x40020008 080097b8 : uint8_t RELAY_State[RELAY_COUNT]; static volatile uint8_t adc_lock = 0; static SMAFilter_t conn_temp_adc_filter[2]; void RELAY_Write(relay_t num, uint8_t state){ 80097b8: b580 push {r7, lr} 80097ba: b082 sub sp, #8 80097bc: af00 add r7, sp, #0 80097be: 4603 mov r3, r0 80097c0: 460a mov r2, r1 80097c2: 71fb strb r3, [r7, #7] 80097c4: 4613 mov r3, r2 80097c6: 71bb strb r3, [r7, #6] switch (num) { 80097c8: 79fb ldrb r3, [r7, #7] 80097ca: 2b07 cmp r3, #7 80097cc: d850 bhi.n 8009870 80097ce: a201 add r2, pc, #4 @ (adr r2, 80097d4 ) 80097d0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80097d4: 080097f5 .word 0x080097f5 80097d8: 08009805 .word 0x08009805 80097dc: 08009815 .word 0x08009815 80097e0: 08009825 .word 0x08009825 80097e4: 08009835 .word 0x08009835 80097e8: 08009845 .word 0x08009845 80097ec: 08009853 .word 0x08009853 80097f0: 08009863 .word 0x08009863 case RELAY_AUX0: HAL_GPIO_WritePin(RELAY1_GPIO_Port, RELAY1_Pin, state); 80097f4: 79bb ldrb r3, [r7, #6] 80097f6: 461a mov r2, r3 80097f8: f44f 7180 mov.w r1, #256 @ 0x100 80097fc: 4821 ldr r0, [pc, #132] @ (8009884 ) 80097fe: f007 f932 bl 8010a66 break; 8009802: e036 b.n 8009872 case RELAY_AUX1: HAL_GPIO_WritePin(RELAY2_GPIO_Port, RELAY2_Pin, state); 8009804: 79bb ldrb r3, [r7, #6] 8009806: 461a mov r2, r3 8009808: f44f 7100 mov.w r1, #512 @ 0x200 800980c: 481d ldr r0, [pc, #116] @ (8009884 ) 800980e: f007 f92a bl 8010a66 break; 8009812: e02e b.n 8009872 case RELAY3: HAL_GPIO_WritePin(RELAY3_GPIO_Port, RELAY3_Pin, state); 8009814: 79bb ldrb r3, [r7, #6] 8009816: 461a mov r2, r3 8009818: f44f 6180 mov.w r1, #1024 @ 0x400 800981c: 4819 ldr r0, [pc, #100] @ (8009884 ) 800981e: f007 f922 bl 8010a66 break; 8009822: e026 b.n 8009872 case RELAY_DC: HAL_GPIO_WritePin(RELAY4_GPIO_Port, RELAY4_Pin, state); 8009824: 79bb ldrb r3, [r7, #6] 8009826: 461a mov r2, r3 8009828: f44f 6100 mov.w r1, #2048 @ 0x800 800982c: 4815 ldr r0, [pc, #84] @ (8009884 ) 800982e: f007 f91a bl 8010a66 break; 8009832: e01e b.n 8009872 case RELAY_AC: HAL_GPIO_WritePin(RELAY5_GPIO_Port, RELAY5_Pin, state); 8009834: 79bb ldrb r3, [r7, #6] 8009836: 461a mov r2, r3 8009838: f44f 5180 mov.w r1, #4096 @ 0x1000 800983c: 4811 ldr r0, [pc, #68] @ (8009884 ) 800983e: f007 f912 bl 8010a66 break; 8009842: e016 b.n 8009872 case RELAY_CP: HAL_GPIO_WritePin(RELAY_CP_GPIO_Port, RELAY_CP_Pin, state); 8009844: 79bb ldrb r3, [r7, #6] 8009846: 461a mov r2, r3 8009848: 2108 movs r1, #8 800984a: 480f ldr r0, [pc, #60] @ (8009888 ) 800984c: f007 f90b bl 8010a66 break; 8009850: e00f b.n 8009872 case RELAY_CC: HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, state); 8009852: 79bb ldrb r3, [r7, #6] 8009854: 461a mov r2, r3 8009856: f44f 4100 mov.w r1, #32768 @ 0x8000 800985a: 480c ldr r0, [pc, #48] @ (800988c ) 800985c: f007 f903 bl 8010a66 break; 8009860: e007 b.n 8009872 case RELAY_DC1: HAL_GPIO_WritePin(RELAY_DC_GPIO_Port, RELAY_DC_Pin, state); 8009862: 79bb ldrb r3, [r7, #6] 8009864: 461a mov r2, r3 8009866: 2108 movs r1, #8 8009868: 4809 ldr r0, [pc, #36] @ (8009890 ) 800986a: f007 f8fc bl 8010a66 break; 800986e: e000 b.n 8009872 default: break; 8009870: bf00 nop } RELAY_State[num] = state; 8009872: 79fb ldrb r3, [r7, #7] 8009874: 4907 ldr r1, [pc, #28] @ (8009894 ) 8009876: 79ba ldrb r2, [r7, #6] 8009878: 54ca strb r2, [r1, r3] } 800987a: bf00 nop 800987c: 3708 adds r7, #8 800987e: 46bd mov sp, r7 8009880: bd80 pop {r7, pc} 8009882: bf00 nop 8009884: 40011800 .word 0x40011800 8009888: 40011000 .word 0x40011000 800988c: 40010800 .word 0x40010800 8009890: 40011400 .word 0x40011400 8009894: 20000304 .word 0x20000304 08009898 : uint8_t RELAY_Read(relay_t num){ 8009898: b480 push {r7} 800989a: b083 sub sp, #12 800989c: af00 add r7, sp, #0 800989e: 4603 mov r3, r0 80098a0: 71fb strb r3, [r7, #7] return RELAY_State[num]; 80098a2: 79fb ldrb r3, [r7, #7] 80098a4: 4a03 ldr r2, [pc, #12] @ (80098b4 ) 80098a6: 5cd3 ldrb r3, [r2, r3] } 80098a8: 4618 mov r0, r3 80098aa: 370c adds r7, #12 80098ac: 46bd mov sp, r7 80098ae: bc80 pop {r7} 80098b0: 4770 bx lr 80098b2: bf00 nop 80098b4: 20000304 .word 0x20000304 080098b8 : uint8_t IN_ReadInput(inputNum_t input_n){ 80098b8: b580 push {r7, lr} 80098ba: b082 sub sp, #8 80098bc: af00 add r7, sp, #0 80098be: 4603 mov r3, r0 80098c0: 71fb strb r3, [r7, #7] switch(input_n){ 80098c2: 79fb ldrb r3, [r7, #7] 80098c4: 2b06 cmp r3, #6 80098c6: d83b bhi.n 8009940 80098c8: a201 add r2, pc, #4 @ (adr r2, 80098d0 ) 80098ca: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80098ce: bf00 nop 80098d0: 080098ed .word 0x080098ed 80098d4: 080098f9 .word 0x080098f9 80098d8: 08009905 .word 0x08009905 80098dc: 08009911 .word 0x08009911 80098e0: 0800991d .word 0x0800991d 80098e4: 08009929 .word 0x08009929 80098e8: 08009935 .word 0x08009935 case IN_SW0: return HAL_GPIO_ReadPin(IN_SW0_GPIO_Port, IN_SW0_Pin); 80098ec: 2102 movs r1, #2 80098ee: 4817 ldr r0, [pc, #92] @ (800994c ) 80098f0: f007 f8a2 bl 8010a38 80098f4: 4603 mov r3, r0 80098f6: e024 b.n 8009942 case IN_SW1: return HAL_GPIO_ReadPin(IN_SW1_GPIO_Port, IN_SW1_Pin); 80098f8: 2104 movs r1, #4 80098fa: 4814 ldr r0, [pc, #80] @ (800994c ) 80098fc: f007 f89c bl 8010a38 8009900: 4603 mov r3, r0 8009902: e01e b.n 8009942 case IN0: return HAL_GPIO_ReadPin(IN0_GPIO_Port, IN0_Pin); 8009904: 2180 movs r1, #128 @ 0x80 8009906: 4812 ldr r0, [pc, #72] @ (8009950 ) 8009908: f007 f896 bl 8010a38 800990c: 4603 mov r3, r0 800990e: e018 b.n 8009942 case IN_ESTOP: return HAL_GPIO_ReadPin(IN_ESTOP_GPIO_Port, IN_ESTOP_Pin); 8009910: 2180 movs r1, #128 @ 0x80 8009912: 4810 ldr r0, [pc, #64] @ (8009954 ) 8009914: f007 f890 bl 8010a38 8009918: 4603 mov r3, r0 800991a: e012 b.n 8009942 case IN_FB1: return HAL_GPIO_ReadPin(IN_FB1_GPIO_Port, IN_FB1_Pin); 800991c: 2110 movs r1, #16 800991e: 480e ldr r0, [pc, #56] @ (8009958 ) 8009920: f007 f88a bl 8010a38 8009924: 4603 mov r3, r0 8009926: e00c b.n 8009942 case IN_CONT_FB_DC: return HAL_GPIO_ReadPin(IN_FB2_GPIO_Port, IN_FB2_Pin); 8009928: 2108 movs r1, #8 800992a: 480b ldr r0, [pc, #44] @ (8009958 ) 800992c: f007 f884 bl 8010a38 8009930: 4603 mov r3, r0 8009932: e006 b.n 8009942 case ISO_IN: return HAL_GPIO_ReadPin(ISO_IN_GPIO_Port, ISO_IN_Pin); 8009934: 2102 movs r1, #2 8009936: 4806 ldr r0, [pc, #24] @ (8009950 ) 8009938: f007 f87e bl 8010a38 800993c: 4603 mov r3, r0 800993e: e000 b.n 8009942 default: return 0; 8009940: 2300 movs r3, #0 } } 8009942: 4618 mov r0, r3 8009944: 3708 adds r7, #8 8009946: 46bd mov sp, r7 8009948: bd80 pop {r7, pc} 800994a: bf00 nop 800994c: 40010800 .word 0x40010800 8009950: 40011800 .word 0x40011800 8009954: 40011400 .word 0x40011400 8009958: 40010c00 .word 0x40010c00 0800995c : /** * @brief Force PC12 (HEATER) as GPIO output via CRH/ODR, overriding UART5 MspInit. * CubeMX assigns PC12 to UART5_TX; on the board it drives the heater relay. */ static void Heater_PinForceOutput(void) { 800995c: b480 push {r7} 800995e: b083 sub sp, #12 8009960: af00 add r7, sp, #0 const uint32_t pin_cfg = GPIO_SPEED_FREQ_LOW; /* MODE=10, CNF=00: GP output PP, 2 MHz */ 8009962: 2302 movs r3, #2 8009964: 607b str r3, [r7, #4] __HAL_RCC_GPIOC_CLK_ENABLE(); 8009966: 4b0f ldr r3, [pc, #60] @ (80099a4 ) 8009968: 699b ldr r3, [r3, #24] 800996a: 4a0e ldr r2, [pc, #56] @ (80099a4 ) 800996c: f043 0310 orr.w r3, r3, #16 8009970: 6193 str r3, [r2, #24] 8009972: 4b0c ldr r3, [pc, #48] @ (80099a4 ) 8009974: 699b ldr r3, [r3, #24] 8009976: f003 0310 and.w r3, r3, #16 800997a: 603b str r3, [r7, #0] 800997c: 683b ldr r3, [r7, #0] MODIFY_REG(HEATER_GPIO_Port->CRH, 800997e: 4b0a ldr r3, [pc, #40] @ (80099a8 ) 8009980: 685b ldr r3, [r3, #4] 8009982: f423 2270 bic.w r2, r3, #983040 @ 0xf0000 8009986: 687b ldr r3, [r7, #4] 8009988: 041b lsls r3, r3, #16 800998a: 4907 ldr r1, [pc, #28] @ (80099a8 ) 800998c: 4313 orrs r3, r2 800998e: 604b str r3, [r1, #4] (GPIO_CRH_MODE12 | GPIO_CRH_CNF12), (pin_cfg << GPIO_CRH_MODE12_Pos)); HEATER_GPIO_Port->BSRR = (uint32_t)HEATER_Pin << 16U; 8009990: 4b05 ldr r3, [pc, #20] @ (80099a8 ) 8009992: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8009996: 611a str r2, [r3, #16] } 8009998: bf00 nop 800999a: 370c adds r7, #12 800999c: 46bd mov sp, r7 800999e: bc80 pop {r7} 80099a0: 4770 bx lr 80099a2: bf00 nop 80099a4: 40021000 .word 0x40021000 80099a8: 40011000 .word 0x40011000 080099ac : void Init_Peripheral(){ 80099ac: b580 push {r7, lr} 80099ae: af00 add r7, sp, #0 Heater_PinForceOutput(); 80099b0: f7ff ffd4 bl 800995c HAL_GPIO_WritePin(HEATER_GPIO_Port, HEATER_Pin, GPIO_PIN_RESET); 80099b4: 2200 movs r2, #0 80099b6: f44f 5180 mov.w r1, #4096 @ 0x1000 80099ba: 4818 ldr r0, [pc, #96] @ (8009a1c ) 80099bc: f007 f853 bl 8010a66 HAL_ADCEx_Calibration_Start(&hadc1); 80099c0: 4817 ldr r0, [pc, #92] @ (8009a20 ) 80099c2: f005 f971 bl 800eca8 ADC_ScanStart(); 80099c6: f7ff fdaf bl 8009528 RELAY_Write(RELAY_AUX0, 0); 80099ca: 2100 movs r1, #0 80099cc: 2000 movs r0, #0 80099ce: f7ff fef3 bl 80097b8 RELAY_Write(RELAY_AUX1, 0); 80099d2: 2100 movs r1, #0 80099d4: 2001 movs r0, #1 80099d6: f7ff feef bl 80097b8 RELAY_Write(RELAY3, 0); 80099da: 2100 movs r1, #0 80099dc: 2002 movs r0, #2 80099de: f7ff feeb bl 80097b8 RELAY_Write(RELAY_DC, 0); 80099e2: 2100 movs r1, #0 80099e4: 2003 movs r0, #3 80099e6: f7ff fee7 bl 80097b8 RELAY_Write(RELAY_AC, 0); 80099ea: 2100 movs r1, #0 80099ec: 2004 movs r0, #4 80099ee: f7ff fee3 bl 80097b8 RELAY_Write(RELAY_CP, 0); 80099f2: 2100 movs r1, #0 80099f4: 2005 movs r0, #5 80099f6: f7ff fedf bl 80097b8 RELAY_Write(RELAY_CC, 0); 80099fa: 2100 movs r1, #0 80099fc: 2006 movs r0, #6 80099fe: f7ff fedb bl 80097b8 RELAY_Write(RELAY_DC1, 0); 8009a02: 2100 movs r1, #0 8009a04: 2007 movs r0, #7 8009a06: f7ff fed7 bl 80097b8 SMAFilter_Init(&conn_temp_adc_filter[0]); 8009a0a: 4806 ldr r0, [pc, #24] @ (8009a24 ) 8009a0c: f003 fd4a bl 800d4a4 SMAFilter_Init(&conn_temp_adc_filter[1]); 8009a10: 4805 ldr r0, [pc, #20] @ (8009a28 ) 8009a12: f003 fd47 bl 800d4a4 } 8009a16: bf00 nop 8009a18: bd80 pop {r7, pc} 8009a1a: bf00 nop 8009a1c: 40011000 .word 0x40011000 8009a20: 20000290 .word 0x20000290 8009a24: 2000030c .word 0x2000030c 8009a28: 20000334 .word 0x20000334 08009a2c : float pt1000_to_temperature(float resistance) { 8009a2c: b590 push {r4, r7, lr} 8009a2e: b087 sub sp, #28 8009a30: af00 add r7, sp, #0 8009a32: 6078 str r0, [r7, #4] // Константы для PT1000 const float R0 = 1000.0; // Сопротивление при 0 °C 8009a34: 4b0c ldr r3, [pc, #48] @ (8009a68 ) 8009a36: 617b str r3, [r7, #20] const float C_A = 3.9083E-3f; 8009a38: 4b0c ldr r3, [pc, #48] @ (8009a6c ) 8009a3a: 613b str r3, [r7, #16] float temperature = (resistance-R0) / ( R0 * C_A); 8009a3c: 6979 ldr r1, [r7, #20] 8009a3e: 6878 ldr r0, [r7, #4] 8009a40: f7ff f8e2 bl 8008c08 <__aeabi_fsub> 8009a44: 4603 mov r3, r0 8009a46: 461c mov r4, r3 8009a48: 6939 ldr r1, [r7, #16] 8009a4a: 6978 ldr r0, [r7, #20] 8009a4c: f7ff f9e6 bl 8008e1c <__aeabi_fmul> 8009a50: 4603 mov r3, r0 8009a52: 4619 mov r1, r3 8009a54: 4620 mov r0, r4 8009a56: f7ff fa95 bl 8008f84 <__aeabi_fdiv> 8009a5a: 4603 mov r3, r0 8009a5c: 60fb str r3, [r7, #12] return temperature; 8009a5e: 68fb ldr r3, [r7, #12] } 8009a60: 4618 mov r0, r3 8009a62: 371c adds r7, #28 8009a64: 46bd mov sp, r7 8009a66: bd90 pop {r4, r7, pc} 8009a68: 447a0000 .word 0x447a0000 8009a6c: 3b801132 .word 0x3b801132 08009a70 : float calculate_NTC_resistance(int adc_value, float Vref, float Vin, float R) { 8009a70: b5b0 push {r4, r5, r7, lr} 8009a72: b086 sub sp, #24 8009a74: af00 add r7, sp, #0 8009a76: 60f8 str r0, [r7, #12] 8009a78: 60b9 str r1, [r7, #8] 8009a7a: 607a str r2, [r7, #4] 8009a7c: 603b str r3, [r7, #0] // Преобразуем значение АЦП в выходное напряжение float Vout = (adc_value / 4095.0) * Vref; 8009a7e: 68f8 ldr r0, [r7, #12] 8009a80: f7fe fd2c bl 80084dc <__aeabi_i2d> 8009a84: a31c add r3, pc, #112 @ (adr r3, 8009af8 ) 8009a86: e9d3 2300 ldrd r2, r3, [r3] 8009a8a: f7fe febb bl 8008804 <__aeabi_ddiv> 8009a8e: 4602 mov r2, r0 8009a90: 460b mov r3, r1 8009a92: 4614 mov r4, r2 8009a94: 461d mov r5, r3 8009a96: 68b8 ldr r0, [r7, #8] 8009a98: f7fe fd32 bl 8008500 <__aeabi_f2d> 8009a9c: 4602 mov r2, r0 8009a9e: 460b mov r3, r1 8009aa0: 4620 mov r0, r4 8009aa2: 4629 mov r1, r5 8009aa4: f7fe fd84 bl 80085b0 <__aeabi_dmul> 8009aa8: 4602 mov r2, r0 8009aaa: 460b mov r3, r1 8009aac: 4610 mov r0, r2 8009aae: 4619 mov r1, r3 8009ab0: f7ff f856 bl 8008b60 <__aeabi_d2f> 8009ab4: 4603 mov r3, r0 8009ab6: 617b str r3, [r7, #20] // Проверяем, чтобы Vout не было равно Vin if (Vout >= Vin) { 8009ab8: 6879 ldr r1, [r7, #4] 8009aba: 6978 ldr r0, [r7, #20] 8009abc: f7ff fb60 bl 8009180 <__aeabi_fcmpge> 8009ac0: 4603 mov r3, r0 8009ac2: 2b00 cmp r3, #0 8009ac4: d001 beq.n 8009aca return -1; // Ошибка: Vout не может быть больше или равно Vin 8009ac6: 4b0e ldr r3, [pc, #56] @ (8009b00 ) 8009ac8: e010 b.n 8009aec } // Вычисляем сопротивление термистора float R_NTC = R * (Vout / (Vin - Vout)); 8009aca: 6979 ldr r1, [r7, #20] 8009acc: 6878 ldr r0, [r7, #4] 8009ace: f7ff f89b bl 8008c08 <__aeabi_fsub> 8009ad2: 4603 mov r3, r0 8009ad4: 4619 mov r1, r3 8009ad6: 6978 ldr r0, [r7, #20] 8009ad8: f7ff fa54 bl 8008f84 <__aeabi_fdiv> 8009adc: 4603 mov r3, r0 8009ade: 4619 mov r1, r3 8009ae0: 6838 ldr r0, [r7, #0] 8009ae2: f7ff f99b bl 8008e1c <__aeabi_fmul> 8009ae6: 4603 mov r3, r0 8009ae8: 613b str r3, [r7, #16] return R_NTC; 8009aea: 693b ldr r3, [r7, #16] } 8009aec: 4618 mov r0, r3 8009aee: 3718 adds r7, #24 8009af0: 46bd mov sp, r7 8009af2: bdb0 pop {r4, r5, r7, pc} 8009af4: f3af 8000 nop.w 8009af8: 00000000 .word 0x00000000 8009afc: 40affe00 .word 0x40affe00 8009b00: bf800000 .word 0xbf800000 08009b04 : int16_t CONN_ReadTemp(uint8_t ch){ 8009b04: b580 push {r7, lr} 8009b06: b088 sub sp, #32 8009b08: af00 add r7, sp, #0 8009b0a: 4603 mov r3, r0 8009b0c: 71fb strb r3, [r7, #7] uint32_t adcValue = 0u; 8009b0e: 2300 movs r3, #0 8009b10: 61fb str r3, [r7, #28] adcValue = ch ? adc_data.ntc2_raw : adc_data.ntc1_raw; 8009b12: 79fb ldrb r3, [r7, #7] 8009b14: 2b00 cmp r3, #0 8009b16: d003 beq.n 8009b20 8009b18: 4b1c ldr r3, [pc, #112] @ (8009b8c ) 8009b1a: 88db ldrh r3, [r3, #6] 8009b1c: b29b uxth r3, r3 8009b1e: e002 b.n 8009b26 8009b20: 4b1a ldr r3, [pc, #104] @ (8009b8c ) 8009b22: 889b ldrh r3, [r3, #4] 8009b24: b29b uxth r3, r3 8009b26: 61fb str r3, [r7, #28] int32_t adc_filtered = SMAFilter_Update(&conn_temp_adc_filter[ch ? 1u : 0u], (int32_t)adcValue); 8009b28: 79fb ldrb r3, [r7, #7] 8009b2a: 2b00 cmp r3, #0 8009b2c: d001 beq.n 8009b32 8009b2e: 2201 movs r2, #1 8009b30: e000 b.n 8009b34 8009b32: 2200 movs r2, #0 8009b34: 4613 mov r3, r2 8009b36: 009b lsls r3, r3, #2 8009b38: 4413 add r3, r2 8009b3a: 00db lsls r3, r3, #3 8009b3c: 4a14 ldr r2, [pc, #80] @ (8009b90 ) 8009b3e: 4413 add r3, r2 8009b40: 69fa ldr r2, [r7, #28] 8009b42: 4611 mov r1, r2 8009b44: 4618 mov r0, r3 8009b46: f003 fcd2 bl 800d4ee 8009b4a: 61b8 str r0, [r7, #24] if((uint32_t)adc_filtered > 4000u) { 8009b4c: 69bb ldr r3, [r7, #24] 8009b4e: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 8009b52: d901 bls.n 8009b58 return 20; //Термодатчик не подключен 8009b54: 2314 movs r3, #20 8009b56: e015 b.n 8009b84 } float Vref = 3.3; // Напряжение опорное 8009b58: 4b0e ldr r3, [pc, #56] @ (8009b94 ) 8009b5a: 617b str r3, [r7, #20] float Vin = 5.0; // Входное напряжение 8009b5c: 4b0e ldr r3, [pc, #56] @ (8009b98 ) 8009b5e: 613b str r3, [r7, #16] float R = 1000; // Сопротивление резистора в Омах 8009b60: 4b0e ldr r3, [pc, #56] @ (8009b9c ) 8009b62: 60fb str r3, [r7, #12] float temp = pt1000_to_temperature(calculate_NTC_resistance((int)adc_filtered, Vref, Vin, R)); 8009b64: 68fb ldr r3, [r7, #12] 8009b66: 693a ldr r2, [r7, #16] 8009b68: 6979 ldr r1, [r7, #20] 8009b6a: 69b8 ldr r0, [r7, #24] 8009b6c: f7ff ff80 bl 8009a70 8009b70: 4603 mov r3, r0 8009b72: 4618 mov r0, r3 8009b74: f7ff ff5a bl 8009a2c 8009b78: 60b8 str r0, [r7, #8] return (int16_t)temp; 8009b7a: 68b8 ldr r0, [r7, #8] 8009b7c: f7ff fb14 bl 80091a8 <__aeabi_f2iz> 8009b80: 4603 mov r3, r0 8009b82: b21b sxth r3, r3 } 8009b84: 4618 mov r0, r3 8009b86: 3720 adds r7, #32 8009b88: 46bd mov sp, r7 8009b8a: bd80 pop {r7, pc} 8009b8c: 20000280 .word 0x20000280 8009b90: 2000030c .word 0x2000030c 8009b94: 40533333 .word 0x40533333 8009b98: 40a00000 .word 0x40a00000 8009b9c: 447a0000 .word 0x447a0000 08009ba0 : CAN_HandleTypeDef hcan1; CAN_HandleTypeDef hcan2; /* CAN1 init function */ void MX_CAN1_Init(void) { 8009ba0: b580 push {r7, lr} 8009ba2: af00 add r7, sp, #0 /* USER CODE END CAN1_Init 0 */ /* USER CODE BEGIN CAN1_Init 1 */ /* USER CODE END CAN1_Init 1 */ hcan1.Instance = CAN1; 8009ba4: 4b17 ldr r3, [pc, #92] @ (8009c04 ) 8009ba6: 4a18 ldr r2, [pc, #96] @ (8009c08 ) 8009ba8: 601a str r2, [r3, #0] hcan1.Init.Prescaler = 8; 8009baa: 4b16 ldr r3, [pc, #88] @ (8009c04 ) 8009bac: 2208 movs r2, #8 8009bae: 605a str r2, [r3, #4] hcan1.Init.Mode = CAN_MODE_NORMAL; 8009bb0: 4b14 ldr r3, [pc, #80] @ (8009c04 ) 8009bb2: 2200 movs r2, #0 8009bb4: 609a str r2, [r3, #8] hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; 8009bb6: 4b13 ldr r3, [pc, #76] @ (8009c04 ) 8009bb8: 2200 movs r2, #0 8009bba: 60da str r2, [r3, #12] hcan1.Init.TimeSeg1 = CAN_BS1_15TQ; 8009bbc: 4b11 ldr r3, [pc, #68] @ (8009c04 ) 8009bbe: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009bc2: 611a str r2, [r3, #16] hcan1.Init.TimeSeg2 = CAN_BS2_2TQ; 8009bc4: 4b0f ldr r3, [pc, #60] @ (8009c04 ) 8009bc6: f44f 1280 mov.w r2, #1048576 @ 0x100000 8009bca: 615a str r2, [r3, #20] hcan1.Init.TimeTriggeredMode = DISABLE; 8009bcc: 4b0d ldr r3, [pc, #52] @ (8009c04 ) 8009bce: 2200 movs r2, #0 8009bd0: 761a strb r2, [r3, #24] hcan1.Init.AutoBusOff = ENABLE; 8009bd2: 4b0c ldr r3, [pc, #48] @ (8009c04 ) 8009bd4: 2201 movs r2, #1 8009bd6: 765a strb r2, [r3, #25] hcan1.Init.AutoWakeUp = ENABLE; 8009bd8: 4b0a ldr r3, [pc, #40] @ (8009c04 ) 8009bda: 2201 movs r2, #1 8009bdc: 769a strb r2, [r3, #26] hcan1.Init.AutoRetransmission = ENABLE; 8009bde: 4b09 ldr r3, [pc, #36] @ (8009c04 ) 8009be0: 2201 movs r2, #1 8009be2: 76da strb r2, [r3, #27] hcan1.Init.ReceiveFifoLocked = DISABLE; 8009be4: 4b07 ldr r3, [pc, #28] @ (8009c04 ) 8009be6: 2200 movs r2, #0 8009be8: 771a strb r2, [r3, #28] hcan1.Init.TransmitFifoPriority = ENABLE; 8009bea: 4b06 ldr r3, [pc, #24] @ (8009c04 ) 8009bec: 2201 movs r2, #1 8009bee: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan1) != HAL_OK) 8009bf0: 4804 ldr r0, [pc, #16] @ (8009c04 ) 8009bf2: f005 f910 bl 800ee16 8009bf6: 4603 mov r3, r0 8009bf8: 2b00 cmp r3, #0 8009bfa: d001 beq.n 8009c00 { Error_Handler(); 8009bfc: f001 f842 bl 800ac84 } /* USER CODE BEGIN CAN1_Init 2 */ /* USER CODE END CAN1_Init 2 */ } 8009c00: bf00 nop 8009c02: bd80 pop {r7, pc} 8009c04: 2000035c .word 0x2000035c 8009c08: 40006400 .word 0x40006400 08009c0c : /* CAN2 init function */ void MX_CAN2_Init(void) { 8009c0c: b580 push {r7, lr} 8009c0e: af00 add r7, sp, #0 /* USER CODE END CAN2_Init 0 */ /* USER CODE BEGIN CAN2_Init 1 */ /* USER CODE END CAN2_Init 1 */ hcan2.Instance = CAN2; 8009c10: 4b17 ldr r3, [pc, #92] @ (8009c70 ) 8009c12: 4a18 ldr r2, [pc, #96] @ (8009c74 ) 8009c14: 601a str r2, [r3, #0] hcan2.Init.Prescaler = 16; 8009c16: 4b16 ldr r3, [pc, #88] @ (8009c70 ) 8009c18: 2210 movs r2, #16 8009c1a: 605a str r2, [r3, #4] hcan2.Init.Mode = CAN_MODE_NORMAL; 8009c1c: 4b14 ldr r3, [pc, #80] @ (8009c70 ) 8009c1e: 2200 movs r2, #0 8009c20: 609a str r2, [r3, #8] hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; 8009c22: 4b13 ldr r3, [pc, #76] @ (8009c70 ) 8009c24: 2200 movs r2, #0 8009c26: 60da str r2, [r3, #12] hcan2.Init.TimeSeg1 = CAN_BS1_15TQ; 8009c28: 4b11 ldr r3, [pc, #68] @ (8009c70 ) 8009c2a: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009c2e: 611a str r2, [r3, #16] hcan2.Init.TimeSeg2 = CAN_BS2_2TQ; 8009c30: 4b0f ldr r3, [pc, #60] @ (8009c70 ) 8009c32: f44f 1280 mov.w r2, #1048576 @ 0x100000 8009c36: 615a str r2, [r3, #20] hcan2.Init.TimeTriggeredMode = DISABLE; 8009c38: 4b0d ldr r3, [pc, #52] @ (8009c70 ) 8009c3a: 2200 movs r2, #0 8009c3c: 761a strb r2, [r3, #24] hcan2.Init.AutoBusOff = ENABLE; 8009c3e: 4b0c ldr r3, [pc, #48] @ (8009c70 ) 8009c40: 2201 movs r2, #1 8009c42: 765a strb r2, [r3, #25] hcan2.Init.AutoWakeUp = ENABLE; 8009c44: 4b0a ldr r3, [pc, #40] @ (8009c70 ) 8009c46: 2201 movs r2, #1 8009c48: 769a strb r2, [r3, #26] hcan2.Init.AutoRetransmission = ENABLE; 8009c4a: 4b09 ldr r3, [pc, #36] @ (8009c70 ) 8009c4c: 2201 movs r2, #1 8009c4e: 76da strb r2, [r3, #27] hcan2.Init.ReceiveFifoLocked = DISABLE; 8009c50: 4b07 ldr r3, [pc, #28] @ (8009c70 ) 8009c52: 2200 movs r2, #0 8009c54: 771a strb r2, [r3, #28] hcan2.Init.TransmitFifoPriority = ENABLE; 8009c56: 4b06 ldr r3, [pc, #24] @ (8009c70 ) 8009c58: 2201 movs r2, #1 8009c5a: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan2) != HAL_OK) 8009c5c: 4804 ldr r0, [pc, #16] @ (8009c70 ) 8009c5e: f005 f8da bl 800ee16 8009c62: 4603 mov r3, r0 8009c64: 2b00 cmp r3, #0 8009c66: d001 beq.n 8009c6c { Error_Handler(); 8009c68: f001 f80c bl 800ac84 } /* USER CODE BEGIN CAN2_Init 2 */ /* USER CODE END CAN2_Init 2 */ } 8009c6c: bf00 nop 8009c6e: bd80 pop {r7, pc} 8009c70: 20000384 .word 0x20000384 8009c74: 40006800 .word 0x40006800 08009c78 : static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0; void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) { 8009c78: b580 push {r7, lr} 8009c7a: b08e sub sp, #56 @ 0x38 8009c7c: af00 add r7, sp, #0 8009c7e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8009c80: f107 0320 add.w r3, r7, #32 8009c84: 2200 movs r2, #0 8009c86: 601a str r2, [r3, #0] 8009c88: 605a str r2, [r3, #4] 8009c8a: 609a str r2, [r3, #8] 8009c8c: 60da str r2, [r3, #12] if(canHandle->Instance==CAN1) 8009c8e: 687b ldr r3, [r7, #4] 8009c90: 681b ldr r3, [r3, #0] 8009c92: 4a61 ldr r2, [pc, #388] @ (8009e18 ) 8009c94: 4293 cmp r3, r2 8009c96: d153 bne.n 8009d40 { /* USER CODE BEGIN CAN1_MspInit 0 */ /* USER CODE END CAN1_MspInit 0 */ /* CAN1 clock enable */ HAL_RCC_CAN1_CLK_ENABLED++; 8009c98: 4b60 ldr r3, [pc, #384] @ (8009e1c ) 8009c9a: 681b ldr r3, [r3, #0] 8009c9c: 3301 adds r3, #1 8009c9e: 4a5f ldr r2, [pc, #380] @ (8009e1c ) 8009ca0: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009ca2: 4b5e ldr r3, [pc, #376] @ (8009e1c ) 8009ca4: 681b ldr r3, [r3, #0] 8009ca6: 2b01 cmp r3, #1 8009ca8: d10b bne.n 8009cc2 __HAL_RCC_CAN1_CLK_ENABLE(); 8009caa: 4b5d ldr r3, [pc, #372] @ (8009e20 ) 8009cac: 69db ldr r3, [r3, #28] 8009cae: 4a5c ldr r2, [pc, #368] @ (8009e20 ) 8009cb0: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009cb4: 61d3 str r3, [r2, #28] 8009cb6: 4b5a ldr r3, [pc, #360] @ (8009e20 ) 8009cb8: 69db ldr r3, [r3, #28] 8009cba: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009cbe: 61fb str r3, [r7, #28] 8009cc0: 69fb ldr r3, [r7, #28] } __HAL_RCC_GPIOD_CLK_ENABLE(); 8009cc2: 4b57 ldr r3, [pc, #348] @ (8009e20 ) 8009cc4: 699b ldr r3, [r3, #24] 8009cc6: 4a56 ldr r2, [pc, #344] @ (8009e20 ) 8009cc8: f043 0320 orr.w r3, r3, #32 8009ccc: 6193 str r3, [r2, #24] 8009cce: 4b54 ldr r3, [pc, #336] @ (8009e20 ) 8009cd0: 699b ldr r3, [r3, #24] 8009cd2: f003 0320 and.w r3, r3, #32 8009cd6: 61bb str r3, [r7, #24] 8009cd8: 69bb ldr r3, [r7, #24] /**CAN1 GPIO Configuration PD0 ------> CAN1_RX PD1 ------> CAN1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0; 8009cda: 2301 movs r3, #1 8009cdc: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009cde: 2300 movs r3, #0 8009ce0: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009ce2: 2300 movs r3, #0 8009ce4: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009ce6: f107 0320 add.w r3, r7, #32 8009cea: 4619 mov r1, r3 8009cec: 484d ldr r0, [pc, #308] @ (8009e24 ) 8009cee: f006 fd1f bl 8010730 GPIO_InitStruct.Pin = GPIO_PIN_1; 8009cf2: 2302 movs r3, #2 8009cf4: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009cf6: 2302 movs r3, #2 8009cf8: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009cfa: 2303 movs r3, #3 8009cfc: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009cfe: f107 0320 add.w r3, r7, #32 8009d02: 4619 mov r1, r3 8009d04: 4847 ldr r0, [pc, #284] @ (8009e24 ) 8009d06: f006 fd13 bl 8010730 __HAL_AFIO_REMAP_CAN1_3(); 8009d0a: 4b47 ldr r3, [pc, #284] @ (8009e28 ) 8009d0c: 685b ldr r3, [r3, #4] 8009d0e: 633b str r3, [r7, #48] @ 0x30 8009d10: 6b3b ldr r3, [r7, #48] @ 0x30 8009d12: f423 43c0 bic.w r3, r3, #24576 @ 0x6000 8009d16: 633b str r3, [r7, #48] @ 0x30 8009d18: 6b3b ldr r3, [r7, #48] @ 0x30 8009d1a: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009d1e: 633b str r3, [r7, #48] @ 0x30 8009d20: 6b3b ldr r3, [r7, #48] @ 0x30 8009d22: f443 43c0 orr.w r3, r3, #24576 @ 0x6000 8009d26: 633b str r3, [r7, #48] @ 0x30 8009d28: 4a3f ldr r2, [pc, #252] @ (8009e28 ) 8009d2a: 6b3b ldr r3, [r7, #48] @ 0x30 8009d2c: 6053 str r3, [r2, #4] /* CAN1 interrupt Init */ HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 3, 0); 8009d2e: 2200 movs r2, #0 8009d30: 2103 movs r1, #3 8009d32: 2014 movs r0, #20 8009d34: f006 f81b bl 800fd6e HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn); 8009d38: 2014 movs r0, #20 8009d3a: f006 f834 bl 800fda6 HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); /* USER CODE BEGIN CAN2_MspInit 1 */ /* USER CODE END CAN2_MspInit 1 */ } } 8009d3e: e067 b.n 8009e10 else if(canHandle->Instance==CAN2) 8009d40: 687b ldr r3, [r7, #4] 8009d42: 681b ldr r3, [r3, #0] 8009d44: 4a39 ldr r2, [pc, #228] @ (8009e2c ) 8009d46: 4293 cmp r3, r2 8009d48: d162 bne.n 8009e10 __HAL_RCC_CAN2_CLK_ENABLE(); 8009d4a: 4b35 ldr r3, [pc, #212] @ (8009e20 ) 8009d4c: 69db ldr r3, [r3, #28] 8009d4e: 4a34 ldr r2, [pc, #208] @ (8009e20 ) 8009d50: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 8009d54: 61d3 str r3, [r2, #28] 8009d56: 4b32 ldr r3, [pc, #200] @ (8009e20 ) 8009d58: 69db ldr r3, [r3, #28] 8009d5a: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8009d5e: 617b str r3, [r7, #20] 8009d60: 697b ldr r3, [r7, #20] HAL_RCC_CAN1_CLK_ENABLED++; 8009d62: 4b2e ldr r3, [pc, #184] @ (8009e1c ) 8009d64: 681b ldr r3, [r3, #0] 8009d66: 3301 adds r3, #1 8009d68: 4a2c ldr r2, [pc, #176] @ (8009e1c ) 8009d6a: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009d6c: 4b2b ldr r3, [pc, #172] @ (8009e1c ) 8009d6e: 681b ldr r3, [r3, #0] 8009d70: 2b01 cmp r3, #1 8009d72: d10b bne.n 8009d8c __HAL_RCC_CAN1_CLK_ENABLE(); 8009d74: 4b2a ldr r3, [pc, #168] @ (8009e20 ) 8009d76: 69db ldr r3, [r3, #28] 8009d78: 4a29 ldr r2, [pc, #164] @ (8009e20 ) 8009d7a: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009d7e: 61d3 str r3, [r2, #28] 8009d80: 4b27 ldr r3, [pc, #156] @ (8009e20 ) 8009d82: 69db ldr r3, [r3, #28] 8009d84: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009d88: 613b str r3, [r7, #16] 8009d8a: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8009d8c: 4b24 ldr r3, [pc, #144] @ (8009e20 ) 8009d8e: 699b ldr r3, [r3, #24] 8009d90: 4a23 ldr r2, [pc, #140] @ (8009e20 ) 8009d92: f043 0308 orr.w r3, r3, #8 8009d96: 6193 str r3, [r2, #24] 8009d98: 4b21 ldr r3, [pc, #132] @ (8009e20 ) 8009d9a: 699b ldr r3, [r3, #24] 8009d9c: f003 0308 and.w r3, r3, #8 8009da0: 60fb str r3, [r7, #12] 8009da2: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_5; 8009da4: 2320 movs r3, #32 8009da6: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009da8: 2300 movs r3, #0 8009daa: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009dac: 2300 movs r3, #0 8009dae: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009db0: f107 0320 add.w r3, r7, #32 8009db4: 4619 mov r1, r3 8009db6: 481e ldr r0, [pc, #120] @ (8009e30 ) 8009db8: f006 fcba bl 8010730 GPIO_InitStruct.Pin = GPIO_PIN_6; 8009dbc: 2340 movs r3, #64 @ 0x40 8009dbe: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009dc0: 2302 movs r3, #2 8009dc2: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009dc4: 2303 movs r3, #3 8009dc6: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009dc8: f107 0320 add.w r3, r7, #32 8009dcc: 4619 mov r1, r3 8009dce: 4818 ldr r0, [pc, #96] @ (8009e30 ) 8009dd0: f006 fcae bl 8010730 __HAL_AFIO_REMAP_CAN2_ENABLE(); 8009dd4: 4b14 ldr r3, [pc, #80] @ (8009e28 ) 8009dd6: 685b ldr r3, [r3, #4] 8009dd8: 637b str r3, [r7, #52] @ 0x34 8009dda: 6b7b ldr r3, [r7, #52] @ 0x34 8009ddc: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009de0: 637b str r3, [r7, #52] @ 0x34 8009de2: 6b7b ldr r3, [r7, #52] @ 0x34 8009de4: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8009de8: 637b str r3, [r7, #52] @ 0x34 8009dea: 4a0f ldr r2, [pc, #60] @ (8009e28 ) 8009dec: 6b7b ldr r3, [r7, #52] @ 0x34 8009dee: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(CAN2_TX_IRQn, 0, 0); 8009df0: 2200 movs r2, #0 8009df2: 2100 movs r1, #0 8009df4: 203f movs r0, #63 @ 0x3f 8009df6: f005 ffba bl 800fd6e HAL_NVIC_EnableIRQ(CAN2_TX_IRQn); 8009dfa: 203f movs r0, #63 @ 0x3f 8009dfc: f005 ffd3 bl 800fda6 HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 3, 0); 8009e00: 2200 movs r2, #0 8009e02: 2103 movs r1, #3 8009e04: 2041 movs r0, #65 @ 0x41 8009e06: f005 ffb2 bl 800fd6e HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); 8009e0a: 2041 movs r0, #65 @ 0x41 8009e0c: f005 ffcb bl 800fda6 } 8009e10: bf00 nop 8009e12: 3738 adds r7, #56 @ 0x38 8009e14: 46bd mov sp, r7 8009e16: bd80 pop {r7, pc} 8009e18: 40006400 .word 0x40006400 8009e1c: 200003ac .word 0x200003ac 8009e20: 40021000 .word 0x40021000 8009e24: 40011400 .word 0x40011400 8009e28: 40010000 .word 0x40010000 8009e2c: 40006800 .word 0x40006800 8009e30: 40010c00 .word 0x40010c00 08009e34 : #include "psu_control.h" ChargingConnector_t CONN; CONN_State_t connectorState; void CONN_Init(){ 8009e34: b480 push {r7} 8009e36: af00 add r7, sp, #0 CONN.connControl = CMD_NONE; 8009e38: 4b08 ldr r3, [pc, #32] @ (8009e5c ) 8009e3a: 2200 movs r2, #0 8009e3c: 701a strb r2, [r3, #0] CONN.connState = Unknown; 8009e3e: 4b07 ldr r3, [pc, #28] @ (8009e5c ) 8009e40: 2200 movs r2, #0 8009e42: 705a strb r2, [r3, #1] CONN.RequestedVoltage = PSU_MIN_VOLTAGE; 8009e44: 4b05 ldr r3, [pc, #20] @ (8009e5c ) 8009e46: 2200 movs r2, #0 8009e48: f062 0269 orn r2, r2, #105 @ 0x69 8009e4c: 73da strb r2, [r3, #15] 8009e4e: 2200 movs r2, #0 8009e50: 741a strb r2, [r3, #16] } 8009e52: bf00 nop 8009e54: 46bd mov sp, r7 8009e56: bc80 pop {r7} 8009e58: 4770 bx lr 8009e5a: bf00 nop 8009e5c: 200003b0 .word 0x200003b0 08009e60 : void CONN_Loop(){ 8009e60: b580 push {r7, lr} 8009e62: af00 add r7, sp, #0 static CONN_State_t last_connState = Unknown; if(last_connState != CONN.connState){ 8009e64: 4b1a ldr r3, [pc, #104] @ (8009ed0 ) 8009e66: 785a ldrb r2, [r3, #1] 8009e68: 4b1a ldr r3, [pc, #104] @ (8009ed4 ) 8009e6a: 781b ldrb r3, [r3, #0] 8009e6c: 429a cmp r2, r3 8009e6e: d006 beq.n 8009e7e last_connState = CONN.connState; 8009e70: 4b17 ldr r3, [pc, #92] @ (8009ed0 ) 8009e72: 785a ldrb r2, [r3, #1] 8009e74: 4b17 ldr r3, [pc, #92] @ (8009ed4 ) 8009e76: 701a strb r2, [r3, #0] CONN.connControl = CMD_NONE; 8009e78: 4b15 ldr r3, [pc, #84] @ (8009ed0 ) 8009e7a: 2200 movs r2, #0 8009e7c: 701a strb r2, [r3, #0] } if(PSU0.cont_fault){ 8009e7e: 4b16 ldr r3, [pc, #88] @ (8009ed8 ) 8009e80: 7b1b ldrb r3, [r3, #12] 8009e82: 2b00 cmp r3, #0 8009e84: d003 beq.n 8009e8e CONN.chargingError = CONN_ERR_CONTACTOR; 8009e86: 4b12 ldr r3, [pc, #72] @ (8009ed0 ) 8009e88: 2207 movs r2, #7 8009e8a: 775a strb r2, [r3, #29] 8009e8c: e00e b.n 8009eac } else if(PSU0.psu_fault){ 8009e8e: 4b12 ldr r3, [pc, #72] @ (8009ed8 ) 8009e90: 7b5b ldrb r3, [r3, #13] 8009e92: 2b00 cmp r3, #0 8009e94: d003 beq.n 8009e9e CONN.chargingError = CONN_ERR_PSU_FAULT; 8009e96: 4b0e ldr r3, [pc, #56] @ (8009ed0 ) 8009e98: 220a movs r2, #10 8009e9a: 775a strb r2, [r3, #29] 8009e9c: e006 b.n 8009eac }else if (CONN.EvConnected == 0){ 8009e9e: 4b0c ldr r3, [pc, #48] @ (8009ed0 ) 8009ea0: 7f9b ldrb r3, [r3, #30] 8009ea2: 2b00 cmp r3, #0 8009ea4: d102 bne.n 8009eac CONN.chargingError = CONN_NO_ERROR; 8009ea6: 4b0a ldr r3, [pc, #40] @ (8009ed0 ) 8009ea8: 2200 movs r2, #0 8009eaa: 775a strb r2, [r3, #29] } if(ED_TraceWarning(CONN.chargingError, 0)) { 8009eac: 4b08 ldr r3, [pc, #32] @ (8009ed0 ) 8009eae: 7f5b ldrb r3, [r3, #29] 8009eb0: 2100 movs r1, #0 8009eb2: 4618 mov r0, r3 8009eb4: f000 fd28 bl 800a908 8009eb8: 4603 mov r3, r0 8009eba: 2b00 cmp r3, #0 8009ebc: d006 beq.n 8009ecc log_printf(LOG_WARN, "CONN0 Error: %d\n", (int)CONN.chargingError); 8009ebe: 4b04 ldr r3, [pc, #16] @ (8009ed0 ) 8009ec0: 7f5b ldrb r3, [r3, #29] 8009ec2: 461a mov r2, r3 8009ec4: 4905 ldr r1, [pc, #20] @ (8009edc ) 8009ec6: 2005 movs r0, #5 8009ec8: f000 fb44 bl 800a554 } } 8009ecc: bf00 nop 8009ece: bd80 pop {r7, pc} 8009ed0: 200003b0 .word 0x200003b0 8009ed4: 200003d0 .word 0x200003d0 8009ed8: 20000904 .word 0x20000904 8009edc: 08016f00 .word 0x08016f00 08009ee0 : void CONN_SetState(CONN_State_t state){ 8009ee0: b580 push {r7, lr} 8009ee2: b082 sub sp, #8 8009ee4: af00 add r7, sp, #0 8009ee6: 4603 mov r3, r0 8009ee8: 71fb strb r3, [r7, #7] if (connectorState == state) { 8009eea: 4b41 ldr r3, [pc, #260] @ (8009ff0 ) 8009eec: 781b ldrb r3, [r3, #0] 8009eee: 79fa ldrb r2, [r7, #7] 8009ef0: 429a cmp r2, r3 8009ef2: d103 bne.n 8009efc CONN.connState = state; 8009ef4: 4a3f ldr r2, [pc, #252] @ (8009ff4 ) 8009ef6: 79fb ldrb r3, [r7, #7] 8009ef8: 7053 strb r3, [r2, #1] return; 8009efa: e075 b.n 8009fe8 } connectorState = state; 8009efc: 4a3c ldr r2, [pc, #240] @ (8009ff0 ) 8009efe: 79fb ldrb r3, [r7, #7] 8009f00: 7013 strb r3, [r2, #0] if(connectorState == Unknown) log_printf(LOG_INFO, "Connector: Unknown\n"); 8009f02: 4b3b ldr r3, [pc, #236] @ (8009ff0 ) 8009f04: 781b ldrb r3, [r3, #0] 8009f06: 2b00 cmp r3, #0 8009f08: d103 bne.n 8009f12 8009f0a: 493b ldr r1, [pc, #236] @ (8009ff8 ) 8009f0c: 2007 movs r0, #7 8009f0e: f000 fb21 bl 800a554 if(connectorState == Unplugged) log_printf(LOG_INFO, "Connector: Unplugged\n"); 8009f12: 4b37 ldr r3, [pc, #220] @ (8009ff0 ) 8009f14: 781b ldrb r3, [r3, #0] 8009f16: 2b01 cmp r3, #1 8009f18: d103 bne.n 8009f22 8009f1a: 4938 ldr r1, [pc, #224] @ (8009ffc ) 8009f1c: 2007 movs r0, #7 8009f1e: f000 fb19 bl 800a554 if(connectorState == Disabled) log_printf(LOG_INFO, "Connector: Disabled\n"); 8009f22: 4b33 ldr r3, [pc, #204] @ (8009ff0 ) 8009f24: 781b ldrb r3, [r3, #0] 8009f26: 2b02 cmp r3, #2 8009f28: d103 bne.n 8009f32 8009f2a: 4935 ldr r1, [pc, #212] @ (800a000 ) 8009f2c: 2007 movs r0, #7 8009f2e: f000 fb11 bl 800a554 if(connectorState == Preparing) log_printf(LOG_INFO, "Connector: Preparing\n"); 8009f32: 4b2f ldr r3, [pc, #188] @ (8009ff0 ) 8009f34: 781b ldrb r3, [r3, #0] 8009f36: 2b03 cmp r3, #3 8009f38: d103 bne.n 8009f42 8009f3a: 4932 ldr r1, [pc, #200] @ (800a004 ) 8009f3c: 2007 movs r0, #7 8009f3e: f000 fb09 bl 800a554 if(connectorState == AuthRequired) log_printf(LOG_INFO, "Connector: AuthRequired\n"); 8009f42: 4b2b ldr r3, [pc, #172] @ (8009ff0 ) 8009f44: 781b ldrb r3, [r3, #0] 8009f46: 2b04 cmp r3, #4 8009f48: d103 bne.n 8009f52 8009f4a: 492f ldr r1, [pc, #188] @ (800a008 ) 8009f4c: 2007 movs r0, #7 8009f4e: f000 fb01 bl 800a554 if(connectorState == WaitingForEnergy) log_printf(LOG_INFO, "Connector: WaitingForEnergy\n"); 8009f52: 4b27 ldr r3, [pc, #156] @ (8009ff0 ) 8009f54: 781b ldrb r3, [r3, #0] 8009f56: 2b05 cmp r3, #5 8009f58: d103 bne.n 8009f62 8009f5a: 492c ldr r1, [pc, #176] @ (800a00c ) 8009f5c: 2007 movs r0, #7 8009f5e: f000 faf9 bl 800a554 if(connectorState == ChargingPausedEV) log_printf(LOG_INFO, "Connector: ChargingPausedEV\n"); 8009f62: 4b23 ldr r3, [pc, #140] @ (8009ff0 ) 8009f64: 781b ldrb r3, [r3, #0] 8009f66: 2b06 cmp r3, #6 8009f68: d103 bne.n 8009f72 8009f6a: 4929 ldr r1, [pc, #164] @ (800a010 ) 8009f6c: 2007 movs r0, #7 8009f6e: f000 faf1 bl 800a554 if(connectorState == ChargingPausedEVSE) log_printf(LOG_INFO, "Connector: ChargingPausedEVSE\n"); 8009f72: 4b1f ldr r3, [pc, #124] @ (8009ff0 ) 8009f74: 781b ldrb r3, [r3, #0] 8009f76: 2b07 cmp r3, #7 8009f78: d103 bne.n 8009f82 8009f7a: 4926 ldr r1, [pc, #152] @ (800a014 ) 8009f7c: 2007 movs r0, #7 8009f7e: f000 fae9 bl 800a554 if(connectorState == Charging) log_printf(LOG_INFO, "Connector: Charging\n"); 8009f82: 4b1b ldr r3, [pc, #108] @ (8009ff0 ) 8009f84: 781b ldrb r3, [r3, #0] 8009f86: 2b08 cmp r3, #8 8009f88: d103 bne.n 8009f92 8009f8a: 4923 ldr r1, [pc, #140] @ (800a018 ) 8009f8c: 2007 movs r0, #7 8009f8e: f000 fae1 bl 800a554 if(connectorState == AuthTimeout) log_printf(LOG_INFO, "Connector: AuthTimeout\n"); 8009f92: 4b17 ldr r3, [pc, #92] @ (8009ff0 ) 8009f94: 781b ldrb r3, [r3, #0] 8009f96: 2b09 cmp r3, #9 8009f98: d103 bne.n 8009fa2 8009f9a: 4920 ldr r1, [pc, #128] @ (800a01c ) 8009f9c: 2007 movs r0, #7 8009f9e: f000 fad9 bl 800a554 if(connectorState == Finished) log_printf(LOG_INFO, "Connector: Finished\n"); 8009fa2: 4b13 ldr r3, [pc, #76] @ (8009ff0 ) 8009fa4: 781b ldrb r3, [r3, #0] 8009fa6: 2b0a cmp r3, #10 8009fa8: d103 bne.n 8009fb2 8009faa: 491d ldr r1, [pc, #116] @ (800a020 ) 8009fac: 2007 movs r0, #7 8009fae: f000 fad1 bl 800a554 if(connectorState == FinishedEVSE) log_printf(LOG_INFO, "Connector: FinishedEVSE\n"); 8009fb2: 4b0f ldr r3, [pc, #60] @ (8009ff0 ) 8009fb4: 781b ldrb r3, [r3, #0] 8009fb6: 2b0b cmp r3, #11 8009fb8: d103 bne.n 8009fc2 8009fba: 491a ldr r1, [pc, #104] @ (800a024 ) 8009fbc: 2007 movs r0, #7 8009fbe: f000 fac9 bl 800a554 if(connectorState == FinishedEV) log_printf(LOG_INFO, "Connector: FinishedEV\n"); 8009fc2: 4b0b ldr r3, [pc, #44] @ (8009ff0 ) 8009fc4: 781b ldrb r3, [r3, #0] 8009fc6: 2b0c cmp r3, #12 8009fc8: d103 bne.n 8009fd2 8009fca: 4917 ldr r1, [pc, #92] @ (800a028 ) 8009fcc: 2007 movs r0, #7 8009fce: f000 fac1 bl 800a554 if(connectorState == Replugging) log_printf(LOG_INFO, "Connector: Replugging\n"); 8009fd2: 4b07 ldr r3, [pc, #28] @ (8009ff0 ) 8009fd4: 781b ldrb r3, [r3, #0] 8009fd6: 2b0d cmp r3, #13 8009fd8: d103 bne.n 8009fe2 8009fda: 4914 ldr r1, [pc, #80] @ (800a02c ) 8009fdc: 2007 movs r0, #7 8009fde: f000 fab9 bl 800a554 CONN.connState = state; 8009fe2: 4a04 ldr r2, [pc, #16] @ (8009ff4 ) 8009fe4: 79fb ldrb r3, [r7, #7] 8009fe6: 7053 strb r3, [r2, #1] } 8009fe8: 3708 adds r7, #8 8009fea: 46bd mov sp, r7 8009fec: bd80 pop {r7, pc} 8009fee: bf00 nop 8009ff0: 200003cf .word 0x200003cf 8009ff4: 200003b0 .word 0x200003b0 8009ff8: 08016f14 .word 0x08016f14 8009ffc: 08016f28 .word 0x08016f28 800a000: 08016f40 .word 0x08016f40 800a004: 08016f58 .word 0x08016f58 800a008: 08016f70 .word 0x08016f70 800a00c: 08016f8c .word 0x08016f8c 800a010: 08016fac .word 0x08016fac 800a014: 08016fcc .word 0x08016fcc 800a018: 08016fec .word 0x08016fec 800a01c: 08017004 .word 0x08017004 800a020: 0801701c .word 0x0801701c 800a024: 08017034 .word 0x08017034 800a028: 08017050 .word 0x08017050 800a02c: 08017068 .word 0x08017068 0800a030 : CP_State_t cp_state_buffer = EV_STATE_ACQUIRING; #define VREFINT_CAL_ADDR ((uint16_t*)0x1FFFF7BA) // для STM32F1! static int32_t CP_ReadVoltageMv(void) { 800a030: b480 push {r7} 800a032: b087 sub sp, #28 800a034: af00 add r7, sp, #0 uint32_t adc_cp = adc_data.cp_raw; 800a036: 4b13 ldr r3, [pc, #76] @ (800a084 ) 800a038: 885b ldrh r3, [r3, #2] 800a03a: b29b uxth r3, r3 800a03c: 617b str r3, [r7, #20] uint32_t adc_vref = adc_data.vrefint_raw; // нужно измерять! 800a03e: 4b11 ldr r3, [pc, #68] @ (800a084 ) 800a040: 895b ldrh r3, [r3, #10] 800a042: b29b uxth r3, r3 800a044: 613b str r3, [r7, #16] // VREFINT в мВ (берётся из даташита или калибровки MCU) const int32_t VREFINT_MV = 1210; 800a046: f240 43ba movw r3, #1210 @ 0x4ba 800a04a: 60fb str r3, [r7, #12] // напряжение на входе АЦП int32_t v_adc_mv = (adc_cp * VREFINT_MV) / adc_vref; 800a04c: 68fb ldr r3, [r7, #12] 800a04e: 697a ldr r2, [r7, #20] 800a050: fb03 f202 mul.w r2, r3, r2 800a054: 693b ldr r3, [r7, #16] 800a056: fbb2 f3f3 udiv r3, r2, r3 800a05a: 60bb str r3, [r7, #8] // дальше твоя формула int32_t v_out_mv = ((v_adc_mv - 1723) * 7704) / 1000; 800a05c: 68bb ldr r3, [r7, #8] 800a05e: f2a3 63bb subw r3, r3, #1723 @ 0x6bb 800a062: f641 6218 movw r2, #7704 @ 0x1e18 800a066: fb02 f303 mul.w r3, r2, r3 800a06a: 4a07 ldr r2, [pc, #28] @ (800a088 ) 800a06c: fb82 1203 smull r1, r2, r2, r3 800a070: 1192 asrs r2, r2, #6 800a072: 17db asrs r3, r3, #31 800a074: 1ad3 subs r3, r2, r3 800a076: 607b str r3, [r7, #4] return v_out_mv; 800a078: 687b ldr r3, [r7, #4] } 800a07a: 4618 mov r0, r3 800a07c: 371c adds r7, #28 800a07e: 46bd mov sp, r7 800a080: bc80 pop {r7} 800a082: 4770 bx lr 800a084: 20000280 .word 0x20000280 800a088: 10624dd3 .word 0x10624dd3 0800a08c : void CP_Init(void) { 800a08c: b580 push {r7, lr} 800a08e: af00 add r7, sp, #0 /* TIM3_CH2 (PA7): set 1kHz PWM like original CCS logic. */ htim3.Instance->PSC = 160 - 1; 800a090: 4b0e ldr r3, [pc, #56] @ (800a0cc ) 800a092: 681b ldr r3, [r3, #0] 800a094: 229f movs r2, #159 @ 0x9f 800a096: 629a str r2, [r3, #40] @ 0x28 htim3.Instance->ARR = MAX_DUTY - 1; 800a098: 4b0c ldr r3, [pc, #48] @ (800a0cc ) 800a09a: 681b ldr r3, [r3, #0] 800a09c: f240 12c1 movw r2, #449 @ 0x1c1 800a0a0: 62da str r2, [r3, #44] @ 0x2c #if DUTY_INVERT == 0 htim3.Instance->CCR2 = MAX_DUTY; 800a0a2: 4b0a ldr r3, [pc, #40] @ (800a0cc ) 800a0a4: 681b ldr r3, [r3, #0] 800a0a6: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a0aa: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = MAX_DUTY + 5; 800a0ac: 4b07 ldr r3, [pc, #28] @ (800a0cc ) 800a0ae: 681b ldr r3, [r3, #0] 800a0b0: f240 12c7 movw r2, #455 @ 0x1c7 800a0b4: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = 0; htim3.Instance->CCR1 = 0; #endif HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_2); 800a0b6: 2104 movs r1, #4 800a0b8: 4804 ldr r0, [pc, #16] @ (800a0cc ) 800a0ba: f008 f80b bl 80120d4 HAL_TIM_OC_Start(&htim3, TIM_CHANNEL_1); 800a0be: 2100 movs r1, #0 800a0c0: 4802 ldr r0, [pc, #8] @ (800a0cc ) 800a0c2: f007 ff05 bl 8011ed0 } 800a0c6: bf00 nop 800a0c8: bd80 pop {r7, pc} 800a0ca: bf00 nop 800a0cc: 200011c8 .word 0x200011c8 0800a0d0 : void CP_SetDuty(uint8_t percentage) { 800a0d0: b480 push {r7} 800a0d2: b085 sub sp, #20 800a0d4: af00 add r7, sp, #0 800a0d6: 4603 mov r3, r0 800a0d8: 71fb strb r3, [r7, #7] uint32_t pwmduty = MAX_DUTY * percentage / 100; 800a0da: 79fb ldrb r3, [r7, #7] 800a0dc: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a0e0: fb02 f303 mul.w r3, r2, r3 800a0e4: 4a0b ldr r2, [pc, #44] @ (800a114 ) 800a0e6: fb82 1203 smull r1, r2, r2, r3 800a0ea: 1152 asrs r2, r2, #5 800a0ec: 17db asrs r3, r3, #31 800a0ee: 1ad3 subs r3, r2, r3 800a0f0: 60fb str r3, [r7, #12] cp_duty = percentage; 800a0f2: 4a09 ldr r2, [pc, #36] @ (800a118 ) 800a0f4: 79fb ldrb r3, [r7, #7] 800a0f6: 7013 strb r3, [r2, #0] #if DUTY_INVERT == 0 htim3.Instance->CCR2 = pwmduty; 800a0f8: 4b08 ldr r3, [pc, #32] @ (800a11c ) 800a0fa: 681b ldr r3, [r3, #0] 800a0fc: 68fa ldr r2, [r7, #12] 800a0fe: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = 0 + 1; 800a100: 4b06 ldr r3, [pc, #24] @ (800a11c ) 800a102: 681b ldr r3, [r3, #0] 800a104: 2201 movs r2, #1 800a106: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = MAX_DUTY - pwmduty; htim3.Instance->CCR1 = MAX_DUTY - pwmduty + 5; #endif } 800a108: bf00 nop 800a10a: 3714 adds r7, #20 800a10c: 46bd mov sp, r7 800a10e: bc80 pop {r7} 800a110: 4770 bx lr 800a112: bf00 nop 800a114: 51eb851f .word 0x51eb851f 800a118: 200003d8 .word 0x200003d8 800a11c: 200011c8 .word 0x200011c8 0800a120 : uint8_t CP_GetDuty(void) { 800a120: b480 push {r7} 800a122: af00 add r7, sp, #0 return cp_duty; 800a124: 4b02 ldr r3, [pc, #8] @ (800a130 ) 800a126: 781b ldrb r3, [r3, #0] } 800a128: 4618 mov r0, r3 800a12a: 46bd mov sp, r7 800a12c: bc80 pop {r7} 800a12e: 4770 bx lr 800a130: 200003d8 .word 0x200003d8 0800a134 : int32_t CP_GetVoltage(void) { 800a134: b580 push {r7, lr} 800a136: af00 add r7, sp, #0 cp_voltage_mv = CP_ReadVoltageMv(); 800a138: f7ff ff7a bl 800a030 800a13c: 4603 mov r3, r0 800a13e: 4a03 ldr r2, [pc, #12] @ (800a14c ) 800a140: 6013 str r3, [r2, #0] return cp_voltage_mv; 800a142: 4b02 ldr r3, [pc, #8] @ (800a14c ) 800a144: 681b ldr r3, [r3, #0] } 800a146: 4618 mov r0, r3 800a148: bd80 pop {r7, pc} 800a14a: bf00 nop 800a14c: 200003d4 .word 0x200003d4 0800a150 : CP_State_t CP_GetState(void) { 800a150: b580 push {r7, lr} 800a152: b082 sub sp, #8 800a154: af00 add r7, sp, #0 int32_t voltage_real = CP_GetVoltage(); 800a156: f7ff ffed bl 800a134 800a15a: 6078 str r0, [r7, #4] if(fake_cp_state != EV_STATE_ACQUIRING) { 800a15c: 4b21 ldr r3, [pc, #132] @ (800a1e4 ) 800a15e: 781b ldrb r3, [r3, #0] 800a160: 2b06 cmp r3, #6 800a162: d002 beq.n 800a16a return fake_cp_state; 800a164: 4b1f ldr r3, [pc, #124] @ (800a1e4 ) 800a166: 781b ldrb r3, [r3, #0] 800a168: e038 b.n 800a1dc } if (voltage_real >= (12000-1000)) { 800a16a: 687b ldr r3, [r7, #4] 800a16c: f642 22f7 movw r2, #10999 @ 0x2af7 800a170: 4293 cmp r3, r2 800a172: dd01 ble.n 800a178 return EV_STATE_A_IDLE; 800a174: 2300 movs r3, #0 800a176: e031 b.n 800a1dc } else if (voltage_real >= (9000-1000) && voltage_real <= (9000+1000)) { 800a178: 687b ldr r3, [r7, #4] 800a17a: f5b3 5ffa cmp.w r3, #8000 @ 0x1f40 800a17e: db06 blt.n 800a18e 800a180: 687b ldr r3, [r7, #4] 800a182: f242 7210 movw r2, #10000 @ 0x2710 800a186: 4293 cmp r3, r2 800a188: dc01 bgt.n 800a18e return EV_STATE_B_CONN_PREP; 800a18a: 2301 movs r3, #1 800a18c: e026 b.n 800a1dc } else if (voltage_real >= (6000-1000) && voltage_real <= (6000+1000)) { 800a18e: 687b ldr r3, [r7, #4] 800a190: f241 3287 movw r2, #4999 @ 0x1387 800a194: 4293 cmp r3, r2 800a196: dd06 ble.n 800a1a6 800a198: 687b ldr r3, [r7, #4] 800a19a: f641 3258 movw r2, #7000 @ 0x1b58 800a19e: 4293 cmp r3, r2 800a1a0: dc01 bgt.n 800a1a6 return EV_STATE_C_CONN_ACTIVE; 800a1a2: 2302 movs r3, #2 800a1a4: e01a b.n 800a1dc } else if (voltage_real >= (3000-1000) && voltage_real <= (3000 + 1000)) { 800a1a6: 687b ldr r3, [r7, #4] 800a1a8: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800a1ac: db05 blt.n 800a1ba 800a1ae: 687b ldr r3, [r7, #4] 800a1b0: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800a1b4: dc01 bgt.n 800a1ba return EV_STATE_D_CONN_ACT_VENT; 800a1b6: 2303 movs r3, #3 800a1b8: e010 b.n 800a1dc } else if (voltage_real >= (0-1000) && voltage_real <= (0+2000)){ 800a1ba: 687b ldr r3, [r7, #4] 800a1bc: f513 7f7a cmn.w r3, #1000 @ 0x3e8 800a1c0: db05 blt.n 800a1ce 800a1c2: 687b ldr r3, [r7, #4] 800a1c4: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800a1c8: dc01 bgt.n 800a1ce return EV_STATE_E_NO_POWER; 800a1ca: 2304 movs r3, #4 800a1cc: e006 b.n 800a1dc } else if (voltage_real <= (-12000+1000)) { 800a1ce: 687b ldr r3, [r7, #4] 800a1d0: 4a05 ldr r2, [pc, #20] @ (800a1e8 ) 800a1d2: 4293 cmp r3, r2 800a1d4: da01 bge.n 800a1da return EV_STATE_F_ERROR; 800a1d6: 2305 movs r3, #5 800a1d8: e000 b.n 800a1dc } else { return EV_STATE_ACQUIRING; 800a1da: 2306 movs r3, #6 } } 800a1dc: 4618 mov r0, r3 800a1de: 3708 adds r7, #8 800a1e0: 46bd mov sp, r7 800a1e2: bd80 pop {r7, pc} 800a1e4: 20000004 .word 0x20000004 800a1e8: ffffd509 .word 0xffffd509 0800a1ec : CP_State_t CP_GetFilteredState(void) { 800a1ec: b480 push {r7} 800a1ee: af00 add r7, sp, #0 return cp_state_buffer; 800a1f0: 4b02 ldr r3, [pc, #8] @ (800a1fc ) 800a1f2: 781b ldrb r3, [r3, #0] } 800a1f4: 4618 mov r0, r3 800a1f6: 46bd mov sp, r7 800a1f8: bc80 pop {r7} 800a1fa: 4770 bx lr 800a1fc: 20000005 .word 0x20000005 0800a200 : void CP_FilterState(void) { 800a200: b580 push {r7, lr} 800a202: b082 sub sp, #8 800a204: af00 add r7, sp, #0 static CP_State_t pending_state = EV_STATE_ACQUIRING; static uint8_t stable_count = 0u; CP_State_t current_state = CP_GetState(); 800a206: f7ff ffa3 bl 800a150 800a20a: 4603 mov r3, r0 800a20c: 71fb strb r3, [r7, #7] /* Keep last accepted state while CP is still acquiring. */ if (current_state == EV_STATE_ACQUIRING) { 800a20e: 79fb ldrb r3, [r7, #7] 800a210: 2b06 cmp r3, #6 800a212: d106 bne.n 800a222 pending_state = EV_STATE_ACQUIRING; 800a214: 4b13 ldr r3, [pc, #76] @ (800a264 ) 800a216: 2206 movs r2, #6 800a218: 701a strb r2, [r3, #0] stable_count = 0u; 800a21a: 4b13 ldr r3, [pc, #76] @ (800a268 ) 800a21c: 2200 movs r2, #0 800a21e: 701a strb r2, [r3, #0] return; 800a220: e01d b.n 800a25e } if (current_state != pending_state) { 800a222: 4b10 ldr r3, [pc, #64] @ (800a264 ) 800a224: 781b ldrb r3, [r3, #0] 800a226: 79fa ldrb r2, [r7, #7] 800a228: 429a cmp r2, r3 800a22a: d006 beq.n 800a23a pending_state = current_state; 800a22c: 4a0d ldr r2, [pc, #52] @ (800a264 ) 800a22e: 79fb ldrb r3, [r7, #7] 800a230: 7013 strb r3, [r2, #0] stable_count = 1u; 800a232: 4b0d ldr r3, [pc, #52] @ (800a268 ) 800a234: 2201 movs r2, #1 800a236: 701a strb r2, [r3, #0] return; 800a238: e011 b.n 800a25e } if (stable_count < FILTER_ORDER) { 800a23a: 4b0b ldr r3, [pc, #44] @ (800a268 ) 800a23c: 781b ldrb r3, [r3, #0] 800a23e: 2b63 cmp r3, #99 @ 0x63 800a240: d805 bhi.n 800a24e stable_count++; 800a242: 4b09 ldr r3, [pc, #36] @ (800a268 ) 800a244: 781b ldrb r3, [r3, #0] 800a246: 3301 adds r3, #1 800a248: b2da uxtb r2, r3 800a24a: 4b07 ldr r3, [pc, #28] @ (800a268 ) 800a24c: 701a strb r2, [r3, #0] } if (stable_count >= FILTER_ORDER) { 800a24e: 4b06 ldr r3, [pc, #24] @ (800a268 ) 800a250: 781b ldrb r3, [r3, #0] 800a252: 2b63 cmp r3, #99 @ 0x63 800a254: d903 bls.n 800a25e cp_state_buffer = pending_state; 800a256: 4b03 ldr r3, [pc, #12] @ (800a264 ) 800a258: 781a ldrb r2, [r3, #0] 800a25a: 4b04 ldr r3, [pc, #16] @ (800a26c ) 800a25c: 701a strb r2, [r3, #0] } } 800a25e: 3708 adds r7, #8 800a260: 46bd mov sp, r7 800a262: bd80 pop {r7, pc} 800a264: 20000006 .word 0x20000006 800a268: 200003d9 .word 0x200003d9 800a26c: 20000005 .word 0x20000005 0800a270 : void CP_Loop(void) { 800a270: b580 push {r7, lr} 800a272: b082 sub sp, #8 800a274: af00 add r7, sp, #0 static uint32_t tick; if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800a276: f004 f85f bl 800e338 800a27a: 4602 mov r2, r0 800a27c: 4b22 ldr r3, [pc, #136] @ (800a308 ) 800a27e: 681b ldr r3, [r3, #0] 800a280: 1ad3 subs r3, r2, r3 800a282: 2b00 cmp r3, #0 800a284: dd3c ble.n 800a300 tick = HAL_GetTick(); 800a286: f004 f857 bl 800e338 800a28a: 4603 mov r3, r0 800a28c: 4a1e ldr r2, [pc, #120] @ (800a308 ) 800a28e: 6013 str r3, [r2, #0] static uint8_t initialized = 0; static CP_State_t prev_state = EV_STATE_ACQUIRING; static uint8_t prev_duty = 0; CP_FilterState(); 800a290: f7ff ffb6 bl 800a200 CP_State_t current_state = CP_GetFilteredState(); 800a294: f7ff ffaa bl 800a1ec 800a298: 4603 mov r3, r0 800a29a: 71fb strb r3, [r7, #7] uint8_t current_duty = cp_duty; 800a29c: 4b1b ldr r3, [pc, #108] @ (800a30c ) 800a29e: 781b ldrb r3, [r3, #0] 800a2a0: 71bb strb r3, [r7, #6] if (!initialized) { 800a2a2: 4b1b ldr r3, [pc, #108] @ (800a310 ) 800a2a4: 781b ldrb r3, [r3, #0] 800a2a6: 2b00 cmp r3, #0 800a2a8: d109 bne.n 800a2be prev_state = current_state; 800a2aa: 4a1a ldr r2, [pc, #104] @ (800a314 ) 800a2ac: 79fb ldrb r3, [r7, #7] 800a2ae: 7013 strb r3, [r2, #0] prev_duty = current_duty; 800a2b0: 4a19 ldr r2, [pc, #100] @ (800a318 ) 800a2b2: 79bb ldrb r3, [r7, #6] 800a2b4: 7013 strb r3, [r2, #0] initialized = 1; 800a2b6: 4b16 ldr r3, [pc, #88] @ (800a310 ) 800a2b8: 2201 movs r2, #1 800a2ba: 701a strb r2, [r3, #0] return; 800a2bc: e021 b.n 800a302 } if (current_state != prev_state) { 800a2be: 4b15 ldr r3, [pc, #84] @ (800a314 ) 800a2c0: 781b ldrb r3, [r3, #0] 800a2c2: 79fa ldrb r2, [r7, #7] 800a2c4: 429a cmp r2, r3 800a2c6: d00a beq.n 800a2de log_printf(LOG_INFO, "CP state changed: %d -> %d\n", prev_state, current_state); 800a2c8: 4b12 ldr r3, [pc, #72] @ (800a314 ) 800a2ca: 781b ldrb r3, [r3, #0] 800a2cc: 461a mov r2, r3 800a2ce: 79fb ldrb r3, [r7, #7] 800a2d0: 4912 ldr r1, [pc, #72] @ (800a31c ) 800a2d2: 2007 movs r0, #7 800a2d4: f000 f93e bl 800a554 prev_state = current_state; 800a2d8: 4a0e ldr r2, [pc, #56] @ (800a314 ) 800a2da: 79fb ldrb r3, [r7, #7] 800a2dc: 7013 strb r3, [r2, #0] } if (current_duty != prev_duty) { 800a2de: 4b0e ldr r3, [pc, #56] @ (800a318 ) 800a2e0: 781b ldrb r3, [r3, #0] 800a2e2: 79ba ldrb r2, [r7, #6] 800a2e4: 429a cmp r2, r3 800a2e6: d00c beq.n 800a302 log_printf(LOG_INFO, "CP duty changed: %u -> %u\n", prev_duty, current_duty); 800a2e8: 4b0b ldr r3, [pc, #44] @ (800a318 ) 800a2ea: 781b ldrb r3, [r3, #0] 800a2ec: 461a mov r2, r3 800a2ee: 79bb ldrb r3, [r7, #6] 800a2f0: 490b ldr r1, [pc, #44] @ (800a320 ) 800a2f2: 2007 movs r0, #7 800a2f4: f000 f92e bl 800a554 prev_duty = current_duty; 800a2f8: 4a07 ldr r2, [pc, #28] @ (800a318 ) 800a2fa: 79bb ldrb r3, [r7, #6] 800a2fc: 7013 strb r3, [r2, #0] 800a2fe: e000 b.n 800a302 if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800a300: bf00 nop } } 800a302: 3708 adds r7, #8 800a304: 46bd mov sp, r7 800a306: bd80 pop {r7, pc} 800a308: 200003dc .word 0x200003dc 800a30c: 200003d8 .word 0x200003d8 800a310: 200003e0 .word 0x200003e0 800a314: 20000007 .word 0x20000007 800a318: 200003e1 .word 0x200003e1 800a31c: 08017080 .word 0x08017080 800a320: 0801709c .word 0x0801709c 0800a324 : CRC_HandleTypeDef hcrc; /* CRC init function */ void MX_CRC_Init(void) { 800a324: b580 push {r7, lr} 800a326: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 800a328: 4b06 ldr r3, [pc, #24] @ (800a344 ) 800a32a: 4a07 ldr r2, [pc, #28] @ (800a348 ) 800a32c: 601a str r2, [r3, #0] if (HAL_CRC_Init(&hcrc) != HAL_OK) 800a32e: 4805 ldr r0, [pc, #20] @ (800a344 ) 800a330: f005 fd53 bl 800fdda 800a334: 4603 mov r3, r0 800a336: 2b00 cmp r3, #0 800a338: d001 beq.n 800a33e { Error_Handler(); 800a33a: f000 fca3 bl 800ac84 } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 800a33e: bf00 nop 800a340: bd80 pop {r7, pc} 800a342: bf00 nop 800a344: 200003e4 .word 0x200003e4 800a348: 40023000 .word 0x40023000 0800a34c : void HAL_CRC_MspInit(CRC_HandleTypeDef* crcHandle) { 800a34c: b480 push {r7} 800a34e: b085 sub sp, #20 800a350: af00 add r7, sp, #0 800a352: 6078 str r0, [r7, #4] if(crcHandle->Instance==CRC) 800a354: 687b ldr r3, [r7, #4] 800a356: 681b ldr r3, [r3, #0] 800a358: 4a09 ldr r2, [pc, #36] @ (800a380 ) 800a35a: 4293 cmp r3, r2 800a35c: d10b bne.n 800a376 { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* CRC clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 800a35e: 4b09 ldr r3, [pc, #36] @ (800a384 ) 800a360: 695b ldr r3, [r3, #20] 800a362: 4a08 ldr r2, [pc, #32] @ (800a384 ) 800a364: f043 0340 orr.w r3, r3, #64 @ 0x40 800a368: 6153 str r3, [r2, #20] 800a36a: 4b06 ldr r3, [pc, #24] @ (800a384 ) 800a36c: 695b ldr r3, [r3, #20] 800a36e: f003 0340 and.w r3, r3, #64 @ 0x40 800a372: 60fb str r3, [r7, #12] 800a374: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 800a376: bf00 nop 800a378: 3714 adds r7, #20 800a37a: 46bd mov sp, r7 800a37c: bc80 pop {r7} 800a37e: 4770 bx lr 800a380: 40023000 .word 0x40023000 800a384: 40021000 .word 0x40021000 0800a388 <_write>: #if defined(__GNUC__) int _write(int fd, char * ptr, int len) { 800a388: b580 push {r7, lr} 800a38a: b084 sub sp, #16 800a38c: af00 add r7, sp, #0 800a38e: 60f8 str r0, [r7, #12] 800a390: 60b9 str r1, [r7, #8] 800a392: 607a str r2, [r7, #4] debug_buffer_add((const uint8_t*)ptr, len); 800a394: 687b ldr r3, [r7, #4] 800a396: b29b uxth r3, r3 800a398: 4619 mov r1, r3 800a39a: 68b8 ldr r0, [r7, #8] 800a39c: f000 f806 bl 800a3ac return len; 800a3a0: 687b ldr r3, [r7, #4] } 800a3a2: 4618 mov r0, r3 800a3a4: 3710 adds r7, #16 800a3a6: 46bd mov sp, r7 800a3a8: bd80 pop {r7, pc} ... 0800a3ac : #endif // Добавляет данные в кольцевой буфер void debug_buffer_add(const uint8_t* data, uint16_t len) { 800a3ac: b480 push {r7} 800a3ae: b085 sub sp, #20 800a3b0: af00 add r7, sp, #0 800a3b2: 6078 str r0, [r7, #4] 800a3b4: 460b mov r3, r1 800a3b6: 807b strh r3, [r7, #2] \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 800a3b8: b672 cpsid i } 800a3ba: bf00 nop __disable_irq(); for (uint16_t i = 0; i < len; i++) { 800a3bc: 2300 movs r3, #0 800a3be: 81fb strh r3, [r7, #14] 800a3c0: e045 b.n 800a44e // Если буфер полон, перезаписываем старые данные if (debug_buffer.count >= DEBUG_BUFFER_SIZE) { 800a3c2: 4b28 ldr r3, [pc, #160] @ (800a464 ) 800a3c4: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a3c8: b29b uxth r3, r3 800a3ca: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800a3ce: d318 bcc.n 800a402 debug_buffer.read_index = (debug_buffer.read_index + 1) % DEBUG_BUFFER_SIZE; 800a3d0: 4b24 ldr r3, [pc, #144] @ (800a464 ) 800a3d2: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a3d6: b29b uxth r3, r3 800a3d8: 3301 adds r3, #1 800a3da: 425a negs r2, r3 800a3dc: f3c3 0309 ubfx r3, r3, #0, #10 800a3e0: f3c2 0209 ubfx r2, r2, #0, #10 800a3e4: bf58 it pl 800a3e6: 4253 negpl r3, r2 800a3e8: b29a uxth r2, r3 800a3ea: 4b1e ldr r3, [pc, #120] @ (800a464 ) 800a3ec: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count--; 800a3f0: 4b1c ldr r3, [pc, #112] @ (800a464 ) 800a3f2: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a3f6: b29b uxth r3, r3 800a3f8: 3b01 subs r3, #1 800a3fa: b29a uxth r2, r3 800a3fc: 4b19 ldr r3, [pc, #100] @ (800a464 ) 800a3fe: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 } debug_buffer.buffer[debug_buffer.write_index] = data[i]; 800a402: 89fb ldrh r3, [r7, #14] 800a404: 687a ldr r2, [r7, #4] 800a406: 4413 add r3, r2 800a408: 4a16 ldr r2, [pc, #88] @ (800a464 ) 800a40a: f8b2 2400 ldrh.w r2, [r2, #1024] @ 0x400 800a40e: b292 uxth r2, r2 800a410: 7819 ldrb r1, [r3, #0] 800a412: 4b14 ldr r3, [pc, #80] @ (800a464 ) 800a414: 5499 strb r1, [r3, r2] debug_buffer.write_index = (debug_buffer.write_index + 1) % DEBUG_BUFFER_SIZE; 800a416: 4b13 ldr r3, [pc, #76] @ (800a464 ) 800a418: f8b3 3400 ldrh.w r3, [r3, #1024] @ 0x400 800a41c: b29b uxth r3, r3 800a41e: 3301 adds r3, #1 800a420: 425a negs r2, r3 800a422: f3c3 0309 ubfx r3, r3, #0, #10 800a426: f3c2 0209 ubfx r2, r2, #0, #10 800a42a: bf58 it pl 800a42c: 4253 negpl r3, r2 800a42e: b29a uxth r2, r3 800a430: 4b0c ldr r3, [pc, #48] @ (800a464 ) 800a432: f8a3 2400 strh.w r2, [r3, #1024] @ 0x400 debug_buffer.count++; 800a436: 4b0b ldr r3, [pc, #44] @ (800a464 ) 800a438: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a43c: b29b uxth r3, r3 800a43e: 3301 adds r3, #1 800a440: b29a uxth r2, r3 800a442: 4b08 ldr r3, [pc, #32] @ (800a464 ) 800a444: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 for (uint16_t i = 0; i < len; i++) { 800a448: 89fb ldrh r3, [r7, #14] 800a44a: 3301 adds r3, #1 800a44c: 81fb strh r3, [r7, #14] 800a44e: 89fa ldrh r2, [r7, #14] 800a450: 887b ldrh r3, [r7, #2] 800a452: 429a cmp r2, r3 800a454: d3b5 bcc.n 800a3c2 __ASM volatile ("cpsie i" : : : "memory"); 800a456: b662 cpsie i } 800a458: bf00 nop } __enable_irq(); } 800a45a: bf00 nop 800a45c: 3714 adds r7, #20 800a45e: 46bd mov sp, r7 800a460: bc80 pop {r7} 800a462: 4770 bx lr 800a464: 200003ec .word 0x200003ec 0800a468 : // Возвращает количество доступных данных в буфере uint16_t debug_buffer_available(void) { 800a468: b480 push {r7} 800a46a: b083 sub sp, #12 800a46c: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a46e: b672 cpsid i } 800a470: bf00 nop __disable_irq(); uint16_t count = debug_buffer.count; 800a472: 4b06 ldr r3, [pc, #24] @ (800a48c ) 800a474: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a478: 80fb strh r3, [r7, #6] __ASM volatile ("cpsie i" : : : "memory"); 800a47a: b662 cpsie i } 800a47c: bf00 nop __enable_irq(); return count; 800a47e: 88fb ldrh r3, [r7, #6] } 800a480: 4618 mov r0, r3 800a482: 370c adds r7, #12 800a484: 46bd mov sp, r7 800a486: bc80 pop {r7} 800a488: 4770 bx lr 800a48a: bf00 nop 800a48c: 200003ec .word 0x200003ec 0800a490 : // Отправляет один пакет данных из буфера через SC_SendPacket (не более 250 байт) void debug_buffer_send(void) { 800a490: b580 push {r7, lr} 800a492: b082 sub sp, #8 800a494: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a496: b672 cpsid i } 800a498: bf00 nop __disable_irq(); // Если буфер пуст, ничего не делаем if (debug_buffer.count == 0) { 800a49a: 4b2d ldr r3, [pc, #180] @ (800a550 ) 800a49c: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a4a0: b29b uxth r3, r3 800a4a2: 2b00 cmp r3, #0 800a4a4: d102 bne.n 800a4ac __ASM volatile ("cpsie i" : : : "memory"); 800a4a6: b662 cpsie i } 800a4a8: bf00 nop __enable_irq(); return; 800a4aa: e04e b.n 800a54a } // Определяем сколько байт можно отправить (не более 250) uint16_t bytes_to_send = debug_buffer.count; 800a4ac: 4b28 ldr r3, [pc, #160] @ (800a550 ) 800a4ae: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a4b2: 80fb strh r3, [r7, #6] if (bytes_to_send > DEBUG_BUFFER_MAX_COUNT) { 800a4b4: 88fb ldrh r3, [r7, #6] 800a4b6: 2b80 cmp r3, #128 @ 0x80 800a4b8: d901 bls.n 800a4be bytes_to_send = DEBUG_BUFFER_MAX_COUNT; 800a4ba: 2380 movs r3, #128 @ 0x80 800a4bc: 80fb strh r3, [r7, #6] } // Вычисляем сколько байт до конца буфера uint16_t bytes_to_end = DEBUG_BUFFER_SIZE - debug_buffer.read_index; 800a4be: 4b24 ldr r3, [pc, #144] @ (800a550 ) 800a4c0: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a4c4: b29b uxth r3, r3 800a4c6: f5c3 6380 rsb r3, r3, #1024 @ 0x400 800a4ca: 80bb strh r3, [r7, #4] // Отправляем только непрерывный блок (до конца буфера или до bytes_to_send) if (bytes_to_send > bytes_to_end) { 800a4cc: 88fa ldrh r2, [r7, #6] 800a4ce: 88bb ldrh r3, [r7, #4] 800a4d0: 429a cmp r2, r3 800a4d2: d901 bls.n 800a4d8 bytes_to_send = bytes_to_end; 800a4d4: 88bb ldrh r3, [r7, #4] 800a4d6: 80fb strh r3, [r7, #6] } // Отправляем данные напрямую из буфера if(bytes_to_send == debug_buffer.count){ 800a4d8: 4b1d ldr r3, [pc, #116] @ (800a550 ) 800a4da: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a4de: b29b uxth r3, r3 800a4e0: 88fa ldrh r2, [r7, #6] 800a4e2: 429a cmp r2, r3 800a4e4: d10c bne.n 800a500 SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG); 800a4e6: 4b1a ldr r3, [pc, #104] @ (800a550 ) 800a4e8: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a4ec: b29b uxth r3, r3 800a4ee: 461a mov r2, r3 800a4f0: 4b17 ldr r3, [pc, #92] @ (800a550 ) 800a4f2: 4413 add r3, r2 800a4f4: 88f9 ldrh r1, [r7, #6] 800a4f6: 2250 movs r2, #80 @ 0x50 800a4f8: 4618 mov r0, r3 800a4fa: f002 fc39 bl 800cd70 800a4fe: e00b b.n 800a518 }else{ SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG_CONTINUE); 800a500: 4b13 ldr r3, [pc, #76] @ (800a550 ) 800a502: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a506: b29b uxth r3, r3 800a508: 461a mov r2, r3 800a50a: 4b11 ldr r3, [pc, #68] @ (800a550 ) 800a50c: 4413 add r3, r2 800a50e: 88f9 ldrh r1, [r7, #6] 800a510: 2251 movs r2, #81 @ 0x51 800a512: 4618 mov r0, r3 800a514: f002 fc2c bl 800cd70 } debug_buffer.read_index = (debug_buffer.read_index + bytes_to_send) % DEBUG_BUFFER_SIZE; 800a518: 4b0d ldr r3, [pc, #52] @ (800a550 ) 800a51a: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a51e: b29a uxth r2, r3 800a520: 88fb ldrh r3, [r7, #6] 800a522: 4413 add r3, r2 800a524: b29b uxth r3, r3 800a526: f3c3 0309 ubfx r3, r3, #0, #10 800a52a: b29a uxth r2, r3 800a52c: 4b08 ldr r3, [pc, #32] @ (800a550 ) 800a52e: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count -= bytes_to_send; 800a532: 4b07 ldr r3, [pc, #28] @ (800a550 ) 800a534: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a538: b29a uxth r2, r3 800a53a: 88fb ldrh r3, [r7, #6] 800a53c: 1ad3 subs r3, r2, r3 800a53e: b29a uxth r2, r3 800a540: 4b03 ldr r3, [pc, #12] @ (800a550 ) 800a542: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 __ASM volatile ("cpsie i" : : : "memory"); 800a546: b662 cpsie i } 800a548: bf00 nop __enable_irq(); } 800a54a: 3708 adds r7, #8 800a54c: 46bd mov sp, r7 800a54e: bd80 pop {r7, pc} 800a550: 200003ec .word 0x200003ec 0800a554 : #define LOG_BUFFER_SIZE 128 uint8_t log_buffer[LOG_BUFFER_SIZE]; // Кастомный printf с приоритетом лога int log_printf(LogLevel_t level, const char *format, ...) { 800a554: b40e push {r1, r2, r3} 800a556: b580 push {r7, lr} 800a558: b085 sub sp, #20 800a55a: af00 add r7, sp, #0 800a55c: 4603 mov r3, r0 800a55e: 71fb strb r3, [r7, #7] va_list args; int result; // Добавляем приоритет первым байтом log_buffer[0] = (uint8_t)level; 800a560: 4a15 ldr r2, [pc, #84] @ (800a5b8 ) 800a562: 79fb ldrb r3, [r7, #7] 800a564: 7013 strb r3, [r2, #0] // Форматируем строку начиная со второго байта va_start(args, format); 800a566: f107 0320 add.w r3, r7, #32 800a56a: 60bb str r3, [r7, #8] result = vsnprintf((char*)&log_buffer[1], LOG_BUFFER_SIZE - 2, format, args); 800a56c: 68bb ldr r3, [r7, #8] 800a56e: 69fa ldr r2, [r7, #28] 800a570: 217e movs r1, #126 @ 0x7e 800a572: 4812 ldr r0, [pc, #72] @ (800a5bc ) 800a574: f00a fb6e bl 8014c54 800a578: 60f8 str r0, [r7, #12] va_end(args); // Проверяем, не переполнился ли буфер if (result < 0) { 800a57a: 68fb ldr r3, [r7, #12] 800a57c: 2b00 cmp r3, #0 800a57e: da01 bge.n 800a584 return result; 800a580: 68fb ldr r3, [r7, #12] 800a582: e012 b.n 800a5aa } // Ограничиваем размер, чтобы оставить место для нуль-терминатора if (result >= (LOG_BUFFER_SIZE - 2)) { 800a584: 68fb ldr r3, [r7, #12] 800a586: 2b7d cmp r3, #125 @ 0x7d 800a588: dd01 ble.n 800a58e result = LOG_BUFFER_SIZE - 2; 800a58a: 237e movs r3, #126 @ 0x7e 800a58c: 60fb str r3, [r7, #12] } // Добавляем нуль-терминатор в конец log_buffer[result + 1] = '\0'; 800a58e: 68fb ldr r3, [r7, #12] 800a590: 3301 adds r3, #1 800a592: 4a09 ldr r2, [pc, #36] @ (800a5b8 ) 800a594: 2100 movs r1, #0 800a596: 54d1 strb r1, [r2, r3] // Отправляем в буфер (приоритет + строка + нуль-терминатор) debug_buffer_add(log_buffer, result + 2); 800a598: 68fb ldr r3, [r7, #12] 800a59a: b29b uxth r3, r3 800a59c: 3302 adds r3, #2 800a59e: b29b uxth r3, r3 800a5a0: 4619 mov r1, r3 800a5a2: 4805 ldr r0, [pc, #20] @ (800a5b8 ) 800a5a4: f7ff ff02 bl 800a3ac return result; 800a5a8: 68fb ldr r3, [r7, #12] } 800a5aa: 4618 mov r0, r3 800a5ac: 3714 adds r7, #20 800a5ae: 46bd mov sp, r7 800a5b0: e8bd 4080 ldmia.w sp!, {r7, lr} 800a5b4: b003 add sp, #12 800a5b6: 4770 bx lr 800a5b8: 200007f4 .word 0x200007f4 800a5bc: 200007f5 .word 0x200007f5 0800a5c0 : /** * Enable DMA controller clock */ void MX_DMA_Init(void) { 800a5c0: b580 push {r7, lr} 800a5c2: b082 sub sp, #8 800a5c4: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 800a5c6: 4b1c ldr r3, [pc, #112] @ (800a638 ) 800a5c8: 695b ldr r3, [r3, #20] 800a5ca: 4a1b ldr r2, [pc, #108] @ (800a638 ) 800a5cc: f043 0301 orr.w r3, r3, #1 800a5d0: 6153 str r3, [r2, #20] 800a5d2: 4b19 ldr r3, [pc, #100] @ (800a638 ) 800a5d4: 695b ldr r3, [r3, #20] 800a5d6: f003 0301 and.w r3, r3, #1 800a5da: 607b str r3, [r7, #4] 800a5dc: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 1, 0); 800a5de: 2200 movs r2, #0 800a5e0: 2101 movs r1, #1 800a5e2: 200b movs r0, #11 800a5e4: f005 fbc3 bl 800fd6e HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 800a5e8: 200b movs r0, #11 800a5ea: f005 fbdc bl 800fda6 /* DMA1_Channel2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 4, 0); 800a5ee: 2200 movs r2, #0 800a5f0: 2104 movs r1, #4 800a5f2: 200c movs r0, #12 800a5f4: f005 fbbb bl 800fd6e HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); 800a5f8: 200c movs r0, #12 800a5fa: f005 fbd4 bl 800fda6 /* DMA1_Channel3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 1, 0); 800a5fe: 2200 movs r2, #0 800a600: 2101 movs r1, #1 800a602: 200d movs r0, #13 800a604: f005 fbb3 bl 800fd6e HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn); 800a608: 200d movs r0, #13 800a60a: f005 fbcc bl 800fda6 /* DMA1_Channel6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel6_IRQn, 1, 0); 800a60e: 2200 movs r2, #0 800a610: 2101 movs r1, #1 800a612: 2010 movs r0, #16 800a614: f005 fbab bl 800fd6e HAL_NVIC_EnableIRQ(DMA1_Channel6_IRQn); 800a618: 2010 movs r0, #16 800a61a: f005 fbc4 bl 800fda6 /* DMA1_Channel7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 4, 0); 800a61e: 2200 movs r2, #0 800a620: 2104 movs r1, #4 800a622: 2011 movs r0, #17 800a624: f005 fba3 bl 800fd6e HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn); 800a628: 2011 movs r0, #17 800a62a: f005 fbbc bl 800fda6 } 800a62e: bf00 nop 800a630: 3708 adds r7, #8 800a632: 46bd mov sp, r7 800a634: bd80 pop {r7, pc} 800a636: bf00 nop 800a638: 40021000 .word 0x40021000 0800a63c : * EXTI PB8 ------> I2C1_SCL PB9 ------> I2C1_SDA */ void MX_GPIO_Init(void) { 800a63c: b580 push {r7, lr} 800a63e: b08a sub sp, #40 @ 0x28 800a640: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800a642: f107 0314 add.w r3, r7, #20 800a646: 2200 movs r2, #0 800a648: 601a str r2, [r3, #0] 800a64a: 605a str r2, [r3, #4] 800a64c: 609a str r2, [r3, #8] 800a64e: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 800a650: 4b94 ldr r3, [pc, #592] @ (800a8a4 ) 800a652: 699b ldr r3, [r3, #24] 800a654: 4a93 ldr r2, [pc, #588] @ (800a8a4 ) 800a656: f043 0310 orr.w r3, r3, #16 800a65a: 6193 str r3, [r2, #24] 800a65c: 4b91 ldr r3, [pc, #580] @ (800a8a4 ) 800a65e: 699b ldr r3, [r3, #24] 800a660: f003 0310 and.w r3, r3, #16 800a664: 613b str r3, [r7, #16] 800a666: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800a668: 4b8e ldr r3, [pc, #568] @ (800a8a4 ) 800a66a: 699b ldr r3, [r3, #24] 800a66c: 4a8d ldr r2, [pc, #564] @ (800a8a4 ) 800a66e: f043 0304 orr.w r3, r3, #4 800a672: 6193 str r3, [r2, #24] 800a674: 4b8b ldr r3, [pc, #556] @ (800a8a4 ) 800a676: 699b ldr r3, [r3, #24] 800a678: f003 0304 and.w r3, r3, #4 800a67c: 60fb str r3, [r7, #12] 800a67e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 800a680: 4b88 ldr r3, [pc, #544] @ (800a8a4 ) 800a682: 699b ldr r3, [r3, #24] 800a684: 4a87 ldr r2, [pc, #540] @ (800a8a4 ) 800a686: f043 0308 orr.w r3, r3, #8 800a68a: 6193 str r3, [r2, #24] 800a68c: 4b85 ldr r3, [pc, #532] @ (800a8a4 ) 800a68e: 699b ldr r3, [r3, #24] 800a690: f003 0308 and.w r3, r3, #8 800a694: 60bb str r3, [r7, #8] 800a696: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOE_CLK_ENABLE(); 800a698: 4b82 ldr r3, [pc, #520] @ (800a8a4 ) 800a69a: 699b ldr r3, [r3, #24] 800a69c: 4a81 ldr r2, [pc, #516] @ (800a8a4 ) 800a69e: f043 0340 orr.w r3, r3, #64 @ 0x40 800a6a2: 6193 str r3, [r2, #24] 800a6a4: 4b7f ldr r3, [pc, #508] @ (800a8a4 ) 800a6a6: 699b ldr r3, [r3, #24] 800a6a8: f003 0340 and.w r3, r3, #64 @ 0x40 800a6ac: 607b str r3, [r7, #4] 800a6ae: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 800a6b0: 4b7c ldr r3, [pc, #496] @ (800a8a4 ) 800a6b2: 699b ldr r3, [r3, #24] 800a6b4: 4a7b ldr r2, [pc, #492] @ (800a8a4 ) 800a6b6: f043 0320 orr.w r3, r3, #32 800a6ba: 6193 str r3, [r2, #24] 800a6bc: 4b79 ldr r3, [pc, #484] @ (800a8a4 ) 800a6be: 699b ldr r3, [r3, #24] 800a6c0: f003 0320 and.w r3, r3, #32 800a6c4: 603b str r3, [r7, #0] 800a6c6: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, DBG1_Pin|RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin 800a6c8: 2200 movs r2, #0 800a6ca: f44f 710f mov.w r1, #572 @ 0x23c 800a6ce: 4876 ldr r0, [pc, #472] @ (800a8a8 ) 800a6d0: f006 f9c9 bl 8010a66 |LED_DATA_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, DBG2_Pin|DBG3_Pin|RELAY_CC_Pin, GPIO_PIN_RESET); 800a6d4: 2200 movs r2, #0 800a6d6: f248 0160 movw r1, #32864 @ 0x8060 800a6da: 4874 ldr r0, [pc, #464] @ (800a8ac ) 800a6dc: f006 f9c3 bl 8010a66 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a6e0: 2200 movs r2, #0 800a6e2: f44f 51f8 mov.w r1, #7936 @ 0x1f00 800a6e6: 4872 ldr r0, [pc, #456] @ (800a8b0 ) 800a6e8: f006 f9bd bl 8010a66 |RELAY5_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, DBG5_Pin|DBG4_Pin|EE_WP_Pin, GPIO_PIN_RESET); 800a6ec: 2200 movs r2, #0 800a6ee: f44f 6148 mov.w r1, #3200 @ 0xc80 800a6f2: 4870 ldr r0, [pc, #448] @ (800a8b4 ) 800a6f4: f006 f9b7 bl 8010a66 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, RELAY_DC_Pin|USART2_DIR_Pin, GPIO_PIN_RESET); 800a6f8: 2200 movs r2, #0 800a6fa: 2118 movs r1, #24 800a6fc: 486e ldr r0, [pc, #440] @ (800a8b8 ) 800a6fe: f006 f9b2 bl 8010a66 /*Configure GPIO pin : DBG1_Pin */ GPIO_InitStruct.Pin = DBG1_Pin; 800a702: 2304 movs r3, #4 800a704: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a706: 2301 movs r3, #1 800a708: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a70a: 2300 movs r3, #0 800a70c: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a70e: 2303 movs r3, #3 800a710: 623b str r3, [r7, #32] HAL_GPIO_Init(DBG1_GPIO_Port, &GPIO_InitStruct); 800a712: f107 0314 add.w r3, r7, #20 800a716: 4619 mov r1, r3 800a718: 4863 ldr r0, [pc, #396] @ (800a8a8 ) 800a71a: f006 f809 bl 8010730 /*Configure GPIO pins : RELAY_CP_Pin LOCK_A_Pin LOCK_B_Pin LED_DATA_Pin */ GPIO_InitStruct.Pin = RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin|LED_DATA_Pin; 800a71e: f44f 730e mov.w r3, #568 @ 0x238 800a722: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a724: 2301 movs r3, #1 800a726: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a728: 2300 movs r3, #0 800a72a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a72c: 2302 movs r3, #2 800a72e: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800a730: f107 0314 add.w r3, r7, #20 800a734: 4619 mov r1, r3 800a736: 485c ldr r0, [pc, #368] @ (800a8a8 ) 800a738: f005 fffa bl 8010730 /*Configure GPIO pin : IN_SW0_Pin */ GPIO_InitStruct.Pin = IN_SW0_Pin; 800a73c: 2302 movs r3, #2 800a73e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a740: 2300 movs r3, #0 800a742: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a744: 2300 movs r3, #0 800a746: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW0_GPIO_Port, &GPIO_InitStruct); 800a748: f107 0314 add.w r3, r7, #20 800a74c: 4619 mov r1, r3 800a74e: 4857 ldr r0, [pc, #348] @ (800a8ac ) 800a750: f005 ffee bl 8010730 /*Configure GPIO pin : IN_SW1_Pin */ GPIO_InitStruct.Pin = IN_SW1_Pin; 800a754: 2304 movs r3, #4 800a756: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a758: 2300 movs r3, #0 800a75a: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 800a75c: 2302 movs r3, #2 800a75e: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW1_GPIO_Port, &GPIO_InitStruct); 800a760: f107 0314 add.w r3, r7, #20 800a764: 4619 mov r1, r3 800a766: 4851 ldr r0, [pc, #324] @ (800a8ac ) 800a768: f005 ffe2 bl 8010730 /*Configure GPIO pins : DBG2_Pin DBG3_Pin */ GPIO_InitStruct.Pin = DBG2_Pin|DBG3_Pin; 800a76c: 2360 movs r3, #96 @ 0x60 800a76e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a770: 2301 movs r3, #1 800a772: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a774: 2300 movs r3, #0 800a776: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a778: 2303 movs r3, #3 800a77a: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800a77c: f107 0314 add.w r3, r7, #20 800a780: 4619 mov r1, r3 800a782: 484a ldr r0, [pc, #296] @ (800a8ac ) 800a784: f005 ffd4 bl 8010730 /*Configure GPIO pins : IN0_Pin AC_OK_Pin ISO_IN_Pin */ GPIO_InitStruct.Pin = IN0_Pin|AC_OK_Pin|ISO_IN_Pin; 800a788: f244 0382 movw r3, #16514 @ 0x4082 800a78c: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a78e: 2300 movs r3, #0 800a790: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a792: 2300 movs r3, #0 800a794: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a796: f107 0314 add.w r3, r7, #20 800a79a: 4619 mov r1, r3 800a79c: 4844 ldr r0, [pc, #272] @ (800a8b0 ) 800a79e: f005 ffc7 bl 8010730 /*Configure GPIO pins : RELAY1_Pin RELAY2_Pin RELAY3_Pin RELAY4_Pin RELAY5_Pin */ GPIO_InitStruct.Pin = RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a7a2: f44f 53f8 mov.w r3, #7936 @ 0x1f00 800a7a6: 617b str r3, [r7, #20] |RELAY5_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a7a8: 2301 movs r3, #1 800a7aa: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a7ac: 2300 movs r3, #0 800a7ae: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a7b0: 2302 movs r3, #2 800a7b2: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a7b4: f107 0314 add.w r3, r7, #20 800a7b8: 4619 mov r1, r3 800a7ba: 483d ldr r0, [pc, #244] @ (800a8b0 ) 800a7bc: f005 ffb8 bl 8010730 /*Configure GPIO pins : DBG5_Pin DBG4_Pin */ GPIO_InitStruct.Pin = DBG5_Pin|DBG4_Pin; 800a7c0: f44f 6340 mov.w r3, #3072 @ 0xc00 800a7c4: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a7c6: 2301 movs r3, #1 800a7c8: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a7ca: 2300 movs r3, #0 800a7cc: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a7ce: 2303 movs r3, #3 800a7d0: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a7d2: f107 0314 add.w r3, r7, #20 800a7d6: 4619 mov r1, r3 800a7d8: 4836 ldr r0, [pc, #216] @ (800a8b4 ) 800a7da: f005 ffa9 bl 8010730 /*Configure GPIO pin : RELAY_CC_Pin */ GPIO_InitStruct.Pin = RELAY_CC_Pin; 800a7de: f44f 4300 mov.w r3, #32768 @ 0x8000 800a7e2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a7e4: 2301 movs r3, #1 800a7e6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a7e8: 2300 movs r3, #0 800a7ea: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a7ec: 2302 movs r3, #2 800a7ee: 623b str r3, [r7, #32] HAL_GPIO_Init(RELAY_CC_GPIO_Port, &GPIO_InitStruct); 800a7f0: f107 0314 add.w r3, r7, #20 800a7f4: 4619 mov r1, r3 800a7f6: 482d ldr r0, [pc, #180] @ (800a8ac ) 800a7f8: f005 ff9a bl 8010730 /*Configure GPIO pins : RELAY_DC_Pin USART2_DIR_Pin */ GPIO_InitStruct.Pin = RELAY_DC_Pin|USART2_DIR_Pin; 800a7fc: 2318 movs r3, #24 800a7fe: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a800: 2301 movs r3, #1 800a802: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a804: 2300 movs r3, #0 800a806: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a808: 2302 movs r3, #2 800a80a: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800a80c: f107 0314 add.w r3, r7, #20 800a810: 4619 mov r1, r3 800a812: 4829 ldr r0, [pc, #164] @ (800a8b8 ) 800a814: f005 ff8c bl 8010730 /*Configure GPIO pin : IN_ESTOP_Pin */ GPIO_InitStruct.Pin = IN_ESTOP_Pin; 800a818: 2380 movs r3, #128 @ 0x80 800a81a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a81c: 2300 movs r3, #0 800a81e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a820: 2300 movs r3, #0 800a822: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_ESTOP_GPIO_Port, &GPIO_InitStruct); 800a824: f107 0314 add.w r3, r7, #20 800a828: 4619 mov r1, r3 800a82a: 4823 ldr r0, [pc, #140] @ (800a8b8 ) 800a82c: f005 ff80 bl 8010730 /*Configure GPIO pins : IN_FB2_Pin IN_FB1_Pin */ GPIO_InitStruct.Pin = IN_FB2_Pin|IN_FB1_Pin; 800a830: 2318 movs r3, #24 800a832: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a834: 2300 movs r3, #0 800a836: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a838: 2300 movs r3, #0 800a83a: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a83c: f107 0314 add.w r3, r7, #20 800a840: 4619 mov r1, r3 800a842: 481c ldr r0, [pc, #112] @ (800a8b4 ) 800a844: f005 ff74 bl 8010730 /*Configure GPIO pin : EE_WP_Pin */ GPIO_InitStruct.Pin = EE_WP_Pin; 800a848: 2380 movs r3, #128 @ 0x80 800a84a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a84c: 2301 movs r3, #1 800a84e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a850: 2300 movs r3, #0 800a852: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a854: 2302 movs r3, #2 800a856: 623b str r3, [r7, #32] HAL_GPIO_Init(EE_WP_GPIO_Port, &GPIO_InitStruct); 800a858: f107 0314 add.w r3, r7, #20 800a85c: 4619 mov r1, r3 800a85e: 4815 ldr r0, [pc, #84] @ (800a8b4 ) 800a860: f005 ff66 bl 8010730 /*Configure GPIO pins : PB8 PB9 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 800a864: f44f 7340 mov.w r3, #768 @ 0x300 800a868: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 800a86a: 2312 movs r3, #18 800a86c: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a86e: 2303 movs r3, #3 800a870: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a872: f107 0314 add.w r3, r7, #20 800a876: 4619 mov r1, r3 800a878: 480e ldr r0, [pc, #56] @ (800a8b4 ) 800a87a: f005 ff59 bl 8010730 /*Configure peripheral I/O remapping */ __HAL_AFIO_REMAP_I2C1_ENABLE(); 800a87e: 4b0f ldr r3, [pc, #60] @ (800a8bc ) 800a880: 685b ldr r3, [r3, #4] 800a882: 627b str r3, [r7, #36] @ 0x24 800a884: 6a7b ldr r3, [r7, #36] @ 0x24 800a886: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800a88a: 627b str r3, [r7, #36] @ 0x24 800a88c: 6a7b ldr r3, [r7, #36] @ 0x24 800a88e: f043 0302 orr.w r3, r3, #2 800a892: 627b str r3, [r7, #36] @ 0x24 800a894: 4a09 ldr r2, [pc, #36] @ (800a8bc ) 800a896: 6a7b ldr r3, [r7, #36] @ 0x24 800a898: 6053 str r3, [r2, #4] } 800a89a: bf00 nop 800a89c: 3728 adds r7, #40 @ 0x28 800a89e: 46bd mov sp, r7 800a8a0: bd80 pop {r7, pc} 800a8a2: bf00 nop 800a8a4: 40021000 .word 0x40021000 800a8a8: 40011000 .word 0x40011000 800a8ac: 40010800 .word 0x40010800 800a8b0: 40011800 .word 0x40011800 800a8b4: 40010c00 .word 0x40010c00 800a8b8: 40011400 .word 0x40011400 800a8bc: 40010000 .word 0x40010000 0800a8c0 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 800a8c0: b480 push {r7} 800a8c2: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 800a8c4: f3bf 8f4f dsb sy } 800a8c8: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800a8ca: 4b06 ldr r3, [pc, #24] @ (800a8e4 <__NVIC_SystemReset+0x24>) 800a8cc: 68db ldr r3, [r3, #12] 800a8ce: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800a8d2: 4904 ldr r1, [pc, #16] @ (800a8e4 <__NVIC_SystemReset+0x24>) 800a8d4: 4b04 ldr r3, [pc, #16] @ (800a8e8 <__NVIC_SystemReset+0x28>) 800a8d6: 4313 orrs r3, r2 800a8d8: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800a8da: f3bf 8f4f dsb sy } 800a8de: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 800a8e0: bf00 nop 800a8e2: e7fd b.n 800a8e0 <__NVIC_SystemReset+0x20> 800a8e4: e000ed00 .word 0xe000ed00 800a8e8: 05fa0004 .word 0x05fa0004 0800a8ec : * bootloader before starting this program. Unfortunately, function * SystemInit() overwrites this change again. * @return none. */ static void VectorBase_Config(void) { 800a8ec: b480 push {r7} 800a8ee: af00 add r7, sp, #0 * c-startup code. */ extern const unsigned long g_pfnVectors[]; /* Remap the vector table to where the vector table is located for this program. */ SCB->VTOR = (unsigned long)&g_pfnVectors[0]; 800a8f0: 4b03 ldr r3, [pc, #12] @ (800a900 ) 800a8f2: 4a04 ldr r2, [pc, #16] @ (800a904 ) 800a8f4: 609a str r2, [r3, #8] } 800a8f6: bf00 nop 800a8f8: 46bd mov sp, r7 800a8fa: bc80 pop {r7} 800a8fc: 4770 bx lr 800a8fe: bf00 nop 800a900: e000ed00 .word 0xe000ed00 800a904: 08008000 .word 0x08008000 0800a908 : uint8_t ED_TraceWarning(uint8_t flag, uint8_t id){ 800a908: b480 push {r7} 800a90a: b085 sub sp, #20 800a90c: af00 add r7, sp, #0 800a90e: 4603 mov r3, r0 800a910: 460a mov r2, r1 800a912: 71fb strb r3, [r7, #7] 800a914: 4613 mov r3, r2 800a916: 71bb strb r3, [r7, #6] static uint8_t memory[32]; if(id > 31) return 0; 800a918: 79bb ldrb r3, [r7, #6] 800a91a: 2b1f cmp r3, #31 800a91c: d901 bls.n 800a922 800a91e: 2300 movs r3, #0 800a920: e00e b.n 800a940 uint8_t result = 0; 800a922: 2300 movs r3, #0 800a924: 73fb strb r3, [r7, #15] if(memory[id] != flag){ 800a926: 79bb ldrb r3, [r7, #6] 800a928: 4a08 ldr r2, [pc, #32] @ (800a94c ) 800a92a: 5cd3 ldrb r3, [r2, r3] 800a92c: 79fa ldrb r2, [r7, #7] 800a92e: 429a cmp r2, r3 800a930: d001 beq.n 800a936 result = 1; 800a932: 2301 movs r3, #1 800a934: 73fb strb r3, [r7, #15] } memory[id] = flag; 800a936: 79bb ldrb r3, [r7, #6] 800a938: 4904 ldr r1, [pc, #16] @ (800a94c ) 800a93a: 79fa ldrb r2, [r7, #7] 800a93c: 54ca strb r2, [r1, r3] return result; 800a93e: 7bfb ldrb r3, [r7, #15] } 800a940: 4618 mov r0, r3 800a942: 3714 adds r7, #20 800a944: 46bd mov sp, r7 800a946: bc80 pop {r7} 800a948: 4770 bx lr 800a94a: bf00 nop 800a94c: 20000874 .word 0x20000874 0800a950 : void ED_Delay(uint32_t Delay) { 800a950: b580 push {r7, lr} 800a952: b084 sub sp, #16 800a954: af00 add r7, sp, #0 800a956: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800a958: f003 fcee bl 800e338 800a95c: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800a95e: 687b ldr r3, [r7, #4] 800a960: 60fb str r3, [r7, #12] if (wait < HAL_MAX_DELAY) 800a962: 68fb ldr r3, [r7, #12] 800a964: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800a968: d010 beq.n 800a98c { wait += (uint32_t)(uwTickFreq); 800a96a: 4b0f ldr r3, [pc, #60] @ (800a9a8 ) 800a96c: 781b ldrb r3, [r3, #0] 800a96e: 461a mov r2, r3 800a970: 68fb ldr r3, [r7, #12] 800a972: 4413 add r3, r2 800a974: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait){ 800a976: e009 b.n 800a98c CCS_SerialLoop(); 800a978: f001 fa48 bl 800be0c StopButtonControl(); 800a97c: f000 f816 bl 800a9ac CP_Loop(); 800a980: f7ff fc76 bl 800a270 LED_Task(); 800a984: f001 f80a bl 800b99c SC_Task(); 800a988: f002 f898 bl 800cabc while ((HAL_GetTick() - tickstart) < wait){ 800a98c: f003 fcd4 bl 800e338 800a990: 4602 mov r2, r0 800a992: 68bb ldr r3, [r7, #8] 800a994: 1ad3 subs r3, r2, r3 800a996: 68fa ldr r2, [r7, #12] 800a998: 429a cmp r2, r3 800a99a: d8ed bhi.n 800a978 } } 800a99c: bf00 nop 800a99e: bf00 nop 800a9a0: 3710 adds r7, #16 800a9a2: 46bd mov sp, r7 800a9a4: bd80 pop {r7, pc} 800a9a6: bf00 nop 800a9a8: 2000008c .word 0x2000008c 0800a9ac : static void StopButtonControl(void){ 800a9ac: b580 push {r7, lr} 800a9ae: b082 sub sp, #8 800a9b0: af00 add r7, sp, #0 static uint32_t tick; static uint32_t hold_time; static uint8_t stop_btn_fault = 1; uint32_t now = HAL_GetTick(); 800a9b2: f003 fcc1 bl 800e338 800a9b6: 6078 str r0, [r7, #4] /* Run no faster than once per 10 ms. */ if((now - tick) < 10){ 800a9b8: 4b2a ldr r3, [pc, #168] @ (800aa64 ) 800a9ba: 681b ldr r3, [r3, #0] 800a9bc: 687a ldr r2, [r7, #4] 800a9be: 1ad3 subs r3, r2, r3 800a9c0: 2b09 cmp r3, #9 800a9c2: d949 bls.n 800aa58 return; } tick = now; 800a9c4: 4a27 ldr r2, [pc, #156] @ (800aa64 ) 800a9c6: 687b ldr r3, [r7, #4] 800a9c8: 6013 str r3, [r2, #0] uint8_t pressed = !IN_ReadInput(IN_ESTOP); 800a9ca: 2003 movs r0, #3 800a9cc: f7fe ff74 bl 80098b8 800a9d0: 4603 mov r3, r0 800a9d2: 2b00 cmp r3, #0 800a9d4: bf0c ite eq 800a9d6: 2301 moveq r3, #1 800a9d8: 2300 movne r3, #0 800a9da: b2db uxtb r3, r3 800a9dc: 70fb strb r3, [r7, #3] if(!pressed){ 800a9de: 78fb ldrb r3, [r7, #3] 800a9e0: 2b00 cmp r3, #0 800a9e2: d102 bne.n 800a9ea stop_btn_fault = 0; 800a9e4: 4b20 ldr r3, [pc, #128] @ (800aa68 ) 800a9e6: 2200 movs r2, #0 800a9e8: 701a strb r2, [r3, #0] } if(stop_btn_fault){ 800a9ea: 4b1f ldr r3, [pc, #124] @ (800aa68 ) 800a9ec: 781b ldrb r3, [r3, #0] 800a9ee: 2b00 cmp r3, #0 800a9f0: d134 bne.n 800aa5c return; } if(pressed){ 800a9f2: 78fb ldrb r3, [r7, #3] 800a9f4: 2b00 cmp r3, #0 800a9f6: d02b beq.n 800aa50 if(hold_time == 0){ 800a9f8: 4b1c ldr r3, [pc, #112] @ (800aa6c ) 800a9fa: 681b ldr r3, [r3, #0] 800a9fc: 2b00 cmp r3, #0 800a9fe: d102 bne.n 800aa06 CONN.connControl = CMD_STOP; 800aa00: 4b1b ldr r3, [pc, #108] @ (800aa70 ) 800aa02: 2201 movs r2, #1 800aa04: 701a strb r2, [r3, #0] } hold_time += 10; 800aa06: 4b19 ldr r3, [pc, #100] @ (800aa6c ) 800aa08: 681b ldr r3, [r3, #0] 800aa0a: 330a adds r3, #10 800aa0c: 4a17 ldr r2, [pc, #92] @ (800aa6c ) 800aa0e: 6013 str r3, [r2, #0] if(hold_time == 5000){ 800aa10: 4b16 ldr r3, [pc, #88] @ (800aa6c ) 800aa12: 681b ldr r3, [r3, #0] 800aa14: f241 3288 movw r2, #5000 @ 0x1388 800aa18: 4293 cmp r3, r2 800aa1a: d102 bne.n 800aa22 CONN.connControl = CMD_FORCE_UNLOCK; 800aa1c: 4b14 ldr r3, [pc, #80] @ (800aa70 ) 800aa1e: 2203 movs r2, #3 800aa20: 701a strb r2, [r3, #0] } if(hold_time > 40000){ 800aa22: 4b12 ldr r3, [pc, #72] @ (800aa6c ) 800aa24: 681b ldr r3, [r3, #0] 800aa26: f649 4240 movw r2, #40000 @ 0x9c40 800aa2a: 4293 cmp r3, r2 800aa2c: d917 bls.n 800aa5e SC_SendPacket(NULL, 0, RESP_SUCCESS); 800aa2e: 2212 movs r2, #18 800aa30: 2100 movs r1, #0 800aa32: 2000 movs r0, #0 800aa34: f002 f99c bl 800cd70 while(huart2.gState == HAL_UART_STATE_BUSY_TX); 800aa38: bf00 nop 800aa3a: 4b0e ldr r3, [pc, #56] @ (800aa74 ) 800aa3c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800aa40: b2db uxtb r3, r3 800aa42: 2b21 cmp r3, #33 @ 0x21 800aa44: d0f9 beq.n 800aa3a HAL_Delay(10); 800aa46: 200a movs r0, #10 800aa48: f003 fc80 bl 800e34c NVIC_SystemReset(); 800aa4c: f7ff ff38 bl 800a8c0 <__NVIC_SystemReset> } } else{ hold_time = 0; 800aa50: 4b06 ldr r3, [pc, #24] @ (800aa6c ) 800aa52: 2200 movs r2, #0 800aa54: 601a str r2, [r3, #0] 800aa56: e002 b.n 800aa5e return; 800aa58: bf00 nop 800aa5a: e000 b.n 800aa5e return; 800aa5c: bf00 nop } } 800aa5e: 3708 adds r7, #8 800aa60: 46bd mov sp, r7 800aa62: bd80 pop {r7, pc} 800aa64: 20000894 .word 0x20000894 800aa68: 20000008 .word 0x20000008 800aa6c: 20000898 .word 0x20000898 800aa70: 200003b0 .word 0x200003b0 800aa74: 200012e8 .word 0x200012e8 0800aa78 : static void CAN1_MinimalReInit(void) { 800aa78: b580 push {r7, lr} 800aa7a: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan1); 800aa7c: 480b ldr r0, [pc, #44] @ (800aaac ) 800aa7e: f004 fbe9 bl 800f254 MX_CAN1_Init(); 800aa82: f7ff f88d bl 8009ba0 if (HAL_CAN_Start(&hcan1) != HAL_OK) { 800aa86: 4809 ldr r0, [pc, #36] @ (800aaac ) 800aa88: f004 fba0 bl 800f1cc 800aa8c: 4603 mov r3, r0 800aa8e: 2b00 cmp r3, #0 800aa90: d001 beq.n 800aa96 Error_Handler(); 800aa92: f000 f8f7 bl 800ac84 } if (HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) { 800aa96: 2102 movs r1, #2 800aa98: 4804 ldr r0, [pc, #16] @ (800aaac ) 800aa9a: f004 fe48 bl 800f72e 800aa9e: 4603 mov r3, r0 800aaa0: 2b00 cmp r3, #0 800aaa2: d001 beq.n 800aaa8 Error_Handler(); 800aaa4: f000 f8ee bl 800ac84 } } 800aaa8: bf00 nop 800aaaa: bd80 pop {r7, pc} 800aaac: 2000035c .word 0x2000035c 0800aab0
: /** * @brief The application entry point. * @retval int */ int main(void) { 800aab0: b580 push {r7, lr} 800aab2: b082 sub sp, #8 800aab4: af02 add r7, sp, #8 /* USER CODE BEGIN 1 */ VectorBase_Config(); 800aab6: f7ff ff19 bl 800a8ec /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800aaba: f003 fbe5 bl 800e288 /* USER CODE BEGIN Init */ HAL_RCC_DeInit(); 800aabe: f005 fff7 bl 8010ab0 /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800aac2: f000 f86f bl 800aba4 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800aac6: f7ff fdb9 bl 800a63c MX_DMA_Init(); 800aaca: f7ff fd79 bl 800a5c0 MX_ADC1_Init(); 800aace: f7fe fd63 bl 8009598 MX_CAN1_Init(); 800aad2: f7ff f865 bl 8009ba0 MX_CAN2_Init(); 800aad6: f7ff f899 bl 8009c0c MX_RTC_Init(); 800aada: f000 fffd bl 800bad8 MX_TIM4_Init(); 800aade: f002 ffdb bl 800da98 MX_USART2_UART_Init(); 800aae2: f003 f959 bl 800dd98 MX_CRC_Init(); 800aae6: f7ff fc1d bl 800a324 MX_UART5_Init(); 800aaea: f003 f901 bl 800dcf0 MX_USART1_UART_Init(); 800aaee: f003 f929 bl 800dd44 MX_USART3_UART_Init(); 800aaf2: f003 f97b bl 800ddec MX_TIM3_Init(); 800aaf6: f002 ff41 bl 800d97c /* USER CODE BEGIN 2 */ Init_Peripheral(); 800aafa: f7fe ff57 bl 80099ac LED_Init(); 800aafe: f000 ff2d bl 800b95c HAL_Delay(300); 800ab02: f44f 7096 mov.w r0, #300 @ 0x12c 800ab06: f003 fc21 bl 800e34c CCS_Init(); 800ab0a: f001 fc17 bl 800c33c SC_Init(); 800ab0e: f001 ffab bl 800ca68 log_printf(LOG_INFO, "CCS module start\n"); 800ab12: 491f ldr r1, [pc, #124] @ (800ab90 ) 800ab14: 2007 movs r0, #7 800ab16: f7ff fd1d bl 800a554 ReadVersion(); 800ab1a: f001 ff81 bl 800ca20 log_printf(LOG_INFO, "Serial number: %d\n", infoPacket.serialNumber); 800ab1e: 4b1d ldr r3, [pc, #116] @ (800ab94 ) 800ab20: 881b ldrh r3, [r3, #0] 800ab22: b29b uxth r3, r3 800ab24: 461a mov r2, r3 800ab26: 491c ldr r1, [pc, #112] @ (800ab98 ) 800ab28: 2007 movs r0, #7 800ab2a: f7ff fd13 bl 800a554 log_printf(LOG_INFO, "Board revision: %d\n", infoPacket.boardVersion); 800ab2e: 4b19 ldr r3, [pc, #100] @ (800ab94 ) 800ab30: 789b ldrb r3, [r3, #2] 800ab32: 461a mov r2, r3 800ab34: 4919 ldr r1, [pc, #100] @ (800ab9c ) 800ab36: 2007 movs r0, #7 800ab38: f7ff fd0c bl 800a554 log_printf(LOG_INFO, "FW version: %d.%d.%d\n", infoPacket.fw_version_major, infoPacket.fw_version_minor, infoPacket.fw_version_patch); 800ab3c: 4b15 ldr r3, [pc, #84] @ (800ab94 ) 800ab3e: 889b ldrh r3, [r3, #4] 800ab40: b29b uxth r3, r3 800ab42: 461a mov r2, r3 800ab44: 4b13 ldr r3, [pc, #76] @ (800ab94 ) 800ab46: 88db ldrh r3, [r3, #6] 800ab48: b29b uxth r3, r3 800ab4a: 4619 mov r1, r3 800ab4c: 4b11 ldr r3, [pc, #68] @ (800ab94 ) 800ab4e: 891b ldrh r3, [r3, #8] 800ab50: b29b uxth r3, r3 800ab52: 9300 str r3, [sp, #0] 800ab54: 460b mov r3, r1 800ab56: 4912 ldr r1, [pc, #72] @ (800aba0 ) 800ab58: 2007 movs r0, #7 800ab5a: f7ff fcfb bl 800a554 CAN1_MinimalReInit(); 800ab5e: f7ff ff8b bl 800aa78 PSU_Init(); 800ab62: f000 f9e5 bl 800af30 CONN_Init(); 800ab66: f7ff f965 bl 8009e34 /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ PSU_ReadWrite(); 800ab6a: f000 faf3 bl 800b154 PSU_Task(); 800ab6e: f000 fbb7 bl 800b2e0 ED_Delay(10); 800ab72: 200a movs r0, #10 800ab74: f7ff feec bl 800a950 METER_CalculateEnergy(); 800ab78: f000 f88a bl 800ac90 CONN_Loop(); 800ab7c: f7ff f970 bl 8009e60 LED_Write(); 800ab80: f000 fd9e bl 800b6c0 ED_Delay(10); 800ab84: 200a movs r0, #10 800ab86: f7ff fee3 bl 800a950 PSU_ReadWrite(); 800ab8a: bf00 nop 800ab8c: e7ed b.n 800ab6a 800ab8e: bf00 nop 800ab90: 080170b8 .word 0x080170b8 800ab94: 200011b0 .word 0x200011b0 800ab98: 080170cc .word 0x080170cc 800ab9c: 080170e0 .word 0x080170e0 800aba0: 080170f4 .word 0x080170f4 0800aba4 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800aba4: b580 push {r7, lr} 800aba6: b09c sub sp, #112 @ 0x70 800aba8: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800abaa: f107 0338 add.w r3, r7, #56 @ 0x38 800abae: 2238 movs r2, #56 @ 0x38 800abb0: 2100 movs r1, #0 800abb2: 4618 mov r0, r3 800abb4: f00a f87a bl 8014cac RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800abb8: f107 0324 add.w r3, r7, #36 @ 0x24 800abbc: 2200 movs r2, #0 800abbe: 601a str r2, [r3, #0] 800abc0: 605a str r2, [r3, #4] 800abc2: 609a str r2, [r3, #8] 800abc4: 60da str r2, [r3, #12] 800abc6: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 800abc8: 1d3b adds r3, r7, #4 800abca: 2220 movs r2, #32 800abcc: 2100 movs r1, #0 800abce: 4618 mov r0, r3 800abd0: f00a f86c bl 8014cac /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; 800abd4: 2305 movs r3, #5 800abd6: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800abd8: f44f 3380 mov.w r3, #65536 @ 0x10000 800abdc: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV5; 800abde: 2304 movs r3, #4 800abe0: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 800abe2: 2301 movs r3, #1 800abe4: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800abe6: 2301 movs r3, #1 800abe8: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.Prediv1Source = RCC_PREDIV1_SOURCE_PLL2; 800abea: f44f 3380 mov.w r3, #65536 @ 0x10000 800abee: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800abf0: 2302 movs r3, #2 800abf2: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800abf4: f44f 3380 mov.w r3, #65536 @ 0x10000 800abf8: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 800abfa: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000 800abfe: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL2.PLL2State = RCC_PLL2_ON; 800ac00: 2302 movs r3, #2 800ac02: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL2.PLL2MUL = RCC_PLL2_MUL8; 800ac04: f44f 63c0 mov.w r3, #1536 @ 0x600 800ac08: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL2.HSEPrediv2Value = RCC_HSE_PREDIV2_DIV5; 800ac0a: 2340 movs r3, #64 @ 0x40 800ac0c: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800ac0e: f107 0338 add.w r3, r7, #56 @ 0x38 800ac12: 4618 mov r0, r3 800ac14: f006 f81c bl 8010c50 800ac18: 4603 mov r3, r0 800ac1a: 2b00 cmp r3, #0 800ac1c: d001 beq.n 800ac22 { Error_Handler(); 800ac1e: f000 f831 bl 800ac84 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800ac22: 230f movs r3, #15 800ac24: 627b str r3, [r7, #36] @ 0x24 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800ac26: 2302 movs r3, #2 800ac28: 62bb str r3, [r7, #40] @ 0x28 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800ac2a: 2300 movs r3, #0 800ac2c: 62fb str r3, [r7, #44] @ 0x2c RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 800ac2e: f44f 6380 mov.w r3, #1024 @ 0x400 800ac32: 633b str r3, [r7, #48] @ 0x30 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 800ac34: 2300 movs r3, #0 800ac36: 637b str r3, [r7, #52] @ 0x34 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800ac38: f107 0324 add.w r3, r7, #36 @ 0x24 800ac3c: 2102 movs r1, #2 800ac3e: 4618 mov r0, r3 800ac40: f006 fb1c bl 801127c 800ac44: 4603 mov r3, r0 800ac46: 2b00 cmp r3, #0 800ac48: d001 beq.n 800ac4e { Error_Handler(); 800ac4a: f000 f81b bl 800ac84 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; 800ac4e: 2303 movs r3, #3 800ac50: 607b str r3, [r7, #4] PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 800ac52: f44f 7380 mov.w r3, #256 @ 0x100 800ac56: 60bb str r3, [r7, #8] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 800ac58: f44f 4300 mov.w r3, #32768 @ 0x8000 800ac5c: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 800ac5e: 1d3b adds r3, r7, #4 800ac60: 4618 mov r0, r3 800ac62: f006 fd01 bl 8011668 800ac66: 4603 mov r3, r0 800ac68: 2b00 cmp r3, #0 800ac6a: d001 beq.n 800ac70 { Error_Handler(); 800ac6c: f000 f80a bl 800ac84 } /** Configure the Systick interrupt time */ __HAL_RCC_PLLI2S_ENABLE(); 800ac70: 4b03 ldr r3, [pc, #12] @ (800ac80 ) 800ac72: 2201 movs r2, #1 800ac74: 601a str r2, [r3, #0] } 800ac76: bf00 nop 800ac78: 3770 adds r7, #112 @ 0x70 800ac7a: 46bd mov sp, r7 800ac7c: bd80 pop {r7, pc} 800ac7e: bf00 nop 800ac80: 42420070 .word 0x42420070 0800ac84 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800ac84: b480 push {r7} 800ac86: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800ac88: b672 cpsid i } 800ac8a: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 800ac8c: bf00 nop 800ac8e: e7fd b.n 800ac8c 0800ac90 : METER_t METER; // Функция для расчета и накопления энергии c дробной частью без счетчиков void METER_CalculateEnergy() { 800ac90: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} 800ac94: b084 sub sp, #16 800ac96: af00 add r7, sp, #0 // Проверяем, что индекс находится в пределах массива METER.online = 0; 800ac98: 4b2c ldr r3, [pc, #176] @ (800ad4c ) 800ac9a: 2200 movs r2, #0 800ac9c: 701a strb r2, [r3, #0] if(CONN.connState == Charging){ 800ac9e: 4b2c ldr r3, [pc, #176] @ (800ad50 ) 800aca0: 785b ldrb r3, [r3, #1] 800aca2: 2b08 cmp r3, #8 800aca4: d103 bne.n 800acae METER.enable = 1; 800aca6: 4b29 ldr r3, [pc, #164] @ (800ad4c ) 800aca8: 2201 movs r2, #1 800acaa: 761a strb r2, [r3, #24] 800acac: e002 b.n 800acb4 }else{ METER.enable = 0; 800acae: 4b27 ldr r3, [pc, #156] @ (800ad4c ) 800acb0: 2200 movs r2, #0 800acb2: 761a strb r2, [r3, #24] } uint32_t currentTick = HAL_GetTick(); // Получаем текущее время в миллисекундах 800acb4: f003 fb40 bl 800e338 800acb8: 60f8 str r0, [r7, #12] uint32_t elapsedTimeMs = currentTick - METER.lastTick; // Вычисляем время, прошедшее с последнего вызова в секундах 800acba: 4b24 ldr r3, [pc, #144] @ (800ad4c ) 800acbc: 685b ldr r3, [r3, #4] 800acbe: 68fa ldr r2, [r7, #12] 800acc0: 1ad3 subs r3, r2, r3 800acc2: 60bb str r3, [r7, #8] METER.lastTick = currentTick; // Обновляем время последнего вызова для текущего коннектора 800acc4: 4a21 ldr r2, [pc, #132] @ (800ad4c ) 800acc6: 68fb ldr r3, [r7, #12] 800acc8: 6053 str r3, [r2, #4] uint32_t energyWs = CONN.Power * elapsedTimeMs / 1000; // Рассчитываем энергию в ватт-секундах за прошедший промежуток времени 800acca: 4b21 ldr r3, [pc, #132] @ (800ad50 ) 800accc: f8d3 3003 ldr.w r3, [r3, #3] 800acd0: 68ba ldr r2, [r7, #8] 800acd2: fb02 f303 mul.w r3, r2, r3 800acd6: 4a1f ldr r2, [pc, #124] @ (800ad54 ) 800acd8: fba2 2303 umull r2, r3, r2, r3 800acdc: 099b lsrs r3, r3, #6 800acde: 607b str r3, [r7, #4] //Расчет энергии теперь идет всегда, смещение берем суммарное METER.EnergyPSU_Ws += energyWs; 800ace0: 4b1a ldr r3, [pc, #104] @ (800ad4c ) 800ace2: e9d3 2302 ldrd r2, r3, [r3, #8] 800ace6: 6879 ldr r1, [r7, #4] 800ace8: 2000 movs r0, #0 800acea: 460c mov r4, r1 800acec: 4605 mov r5, r0 800acee: eb12 0804 adds.w r8, r2, r4 800acf2: eb43 0905 adc.w r9, r3, r5 800acf6: 4b15 ldr r3, [pc, #84] @ (800ad4c ) 800acf8: e9c3 8902 strd r8, r9, [r3, #8] // Абсолютное значение энергии разъема складывается из накопленной дробной части и значения со счетчиков METER.AbsoluteEnergy = (uint32_t)METER.EnergyPSU_Ws/3600; //переводим в Вт*час 800acfc: 4b13 ldr r3, [pc, #76] @ (800ad4c ) 800acfe: e9d3 2302 ldrd r2, r3, [r3, #8] 800ad02: 4b15 ldr r3, [pc, #84] @ (800ad58 ) 800ad04: fba3 2302 umull r2, r3, r3, r2 800ad08: 0adb lsrs r3, r3, #11 800ad0a: 4a10 ldr r2, [pc, #64] @ (800ad4c ) 800ad0c: 6113 str r3, [r2, #16] if(METER.enable) { 800ad0e: 4b0f ldr r3, [pc, #60] @ (800ad4c ) 800ad10: 7e1b ldrb r3, [r3, #24] 800ad12: 2b00 cmp r3, #0 800ad14: d008 beq.n 800ad28 //enabled state CONN.Energy = METER.AbsoluteEnergy - METER.EnergyOffset;//переводим в Вт*час 800ad16: 4b0d ldr r3, [pc, #52] @ (800ad4c ) 800ad18: 691a ldr r2, [r3, #16] 800ad1a: 4b0c ldr r3, [pc, #48] @ (800ad4c ) 800ad1c: 695b ldr r3, [r3, #20] 800ad1e: 1ad3 subs r3, r2, r3 800ad20: 4a0b ldr r2, [pc, #44] @ (800ad50 ) 800ad22: f8c2 3007 str.w r3, [r2, #7] METER.EnergyOffset = METER.AbsoluteEnergy; } } 800ad26: e00c b.n 800ad42 CONN.Energy = 0; 800ad28: 4b09 ldr r3, [pc, #36] @ (800ad50 ) 800ad2a: 2200 movs r2, #0 800ad2c: 71da strb r2, [r3, #7] 800ad2e: 2200 movs r2, #0 800ad30: 721a strb r2, [r3, #8] 800ad32: 2200 movs r2, #0 800ad34: 725a strb r2, [r3, #9] 800ad36: 2200 movs r2, #0 800ad38: 729a strb r2, [r3, #10] METER.EnergyOffset = METER.AbsoluteEnergy; 800ad3a: 4b04 ldr r3, [pc, #16] @ (800ad4c ) 800ad3c: 691b ldr r3, [r3, #16] 800ad3e: 4a03 ldr r2, [pc, #12] @ (800ad4c ) 800ad40: 6153 str r3, [r2, #20] } 800ad42: bf00 nop 800ad44: 3710 adds r7, #16 800ad46: 46bd mov sp, r7 800ad48: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} 800ad4c: 200008a0 .word 0x200008a0 800ad50: 200003b0 .word 0x200003b0 800ad54: 10624dd3 .word 0x10624dd3 800ad58: 91a2b3c5 .word 0x91a2b3c5 0800ad5c : extern CAN_HandleTypeDef hcan2; static void PSU_SendCmd(uint8_t source, uint8_t destination, uint8_t cmd, void *data); static void PSU_SwitchState(PSU_State_t state){ 800ad5c: b580 push {r7, lr} 800ad5e: b082 sub sp, #8 800ad60: af00 add r7, sp, #0 800ad62: 4603 mov r3, r0 800ad64: 71fb strb r3, [r7, #7] PSU0.state = state; 800ad66: 4a06 ldr r2, [pc, #24] @ (800ad80 ) 800ad68: 79fb ldrb r3, [r7, #7] 800ad6a: 71d3 strb r3, [r2, #7] PSU0.statetick = HAL_GetTick(); 800ad6c: f003 fae4 bl 800e338 800ad70: 4603 mov r3, r0 800ad72: 4a03 ldr r2, [pc, #12] @ (800ad80 ) 800ad74: 6113 str r3, [r2, #16] } 800ad76: bf00 nop 800ad78: 3708 adds r7, #8 800ad7a: 46bd mov sp, r7 800ad7c: bd80 pop {r7, pc} 800ad7e: bf00 nop 800ad80: 20000904 .word 0x20000904 0800ad84 : static uint32_t PSU_StateTime(void){ 800ad84: b580 push {r7, lr} 800ad86: af00 add r7, sp, #0 return HAL_GetTick() - PSU0.statetick; 800ad88: f003 fad6 bl 800e338 800ad8c: 4602 mov r2, r0 800ad8e: 4b02 ldr r3, [pc, #8] @ (800ad98 ) 800ad90: 691b ldr r3, [r3, #16] 800ad92: 1ad3 subs r3, r2, r3 } 800ad94: 4618 mov r0, r3 800ad96: bd80 pop {r7, pc} 800ad98: 20000904 .word 0x20000904 0800ad9c : ISR_FAST void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan){ 800ad9c: b538 push {r3, r4, r5, lr} static CAN_RxHeaderTypeDef RxHeader; static uint8_t RxData[8] = {0,}; CanId_t CanId; if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO1, &RxHeader, RxData) == HAL_OK) 800ad9e: 4c42 ldr r4, [pc, #264] @ (800aea8 ) 800ada0: 4d42 ldr r5, [pc, #264] @ (800aeac ) 800ada2: 4623 mov r3, r4 800ada4: 462a mov r2, r5 800ada6: 2101 movs r1, #1 800ada8: f004 fba0 bl 800f4ec 800adac: b910 cbnz r0, 800adb4 { memcpy(&CanId, &RxHeader.ExtId, sizeof(CanId_t)); 800adae: 686d ldr r5, [r5, #4] /* Для DC30 поддерживается только один силовой модуль (source == 0) */ if(CanId.source != 0) return; 800adb0: b2eb uxtb r3, r5 800adb2: b103 cbz r3, 800adb6 CONN.outputEnabled = PSU0.PSU_enabled; } } } } } 800adb4: bd38 pop {r3, r4, r5, pc} can_lastpacket = HAL_GetTick(); 800adb6: f003 fabf bl 800e338 if(CanId.command==0x02){ 800adba: f3c5 4505 ubfx r5, r5, #16, #6 can_lastpacket = HAL_GetTick(); 800adbe: 4b3c ldr r3, [pc, #240] @ (800aeb0 ) if(CanId.command==0x02){ 800adc0: 2d02 cmp r5, #2 can_lastpacket = HAL_GetTick(); 800adc2: 6018 str r0, [r3, #0] if(CanId.command==0x02){ 800adc4: d013 beq.n 800adee if(CanId.command==0x04){ 800adc6: 2d04 cmp r5, #4 800adc8: d117 bne.n 800adfa memcpy(&PSU_04, RxData, 8); 800adca: e894 0003 ldmia.w r4, {r0, r1} 800adce: 4b39 ldr r3, [pc, #228] @ (800aeb4 ) PSU0.tempAmbient = PSU_04.moduleTemperature; 800add0: 4a39 ldr r2, [pc, #228] @ (800aeb8 ) memcpy(&PSU_04, RxData, 8); 800add2: e883 0003 stmia.w r3, {r0, r1} PSU0.status0.raw = PSU_04.modularForm0; 800add6: 7a18 ldrb r0, [r3, #8] PSU0.tempAmbient = PSU_04.moduleTemperature; 800add8: 791c ldrb r4, [r3, #4] PSU0.status1.raw = PSU_04.modularForm1; 800adda: 79d9 ldrb r1, [r3, #7] PSU0.status2.raw = PSU_04.modularForm2; 800addc: 799b ldrb r3, [r3, #6] PSU0.tempAmbient = PSU_04.moduleTemperature; 800adde: 6214 str r4, [r2, #32] PSU0.status0.raw = PSU_04.modularForm0; 800ade0: f882 0024 strb.w r0, [r2, #36] @ 0x24 PSU0.status1.raw = PSU_04.modularForm1; 800ade4: f882 1025 strb.w r1, [r2, #37] @ 0x25 PSU0.status2.raw = PSU_04.modularForm2; 800ade8: f882 3026 strb.w r3, [r2, #38] @ 0x26 } 800adec: bd38 pop {r3, r4, r5, pc} memcpy(&PSU_02, RxData, 8); 800adee: 4b33 ldr r3, [pc, #204] @ (800aebc ) 800adf0: e894 0003 ldmia.w r4, {r0, r1} 800adf4: e883 0003 stmia.w r3, {r0, r1} } 800adf8: bd38 pop {r3, r4, r5, pc} if(CanId.command==0x06){ 800adfa: 2d06 cmp r5, #6 800adfc: d111 bne.n 800ae22 memcpy(&PSU_06, RxData, 8); 800adfe: e894 0003 ldmia.w r4, {r0, r1} 800ae02: 4b2f ldr r3, [pc, #188] @ (800aec0 ) 800ae04: e883 0003 stmia.w r3, {r0, r1} PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800ae08: 8818 ldrh r0, [r3, #0] PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ae0a: 8859 ldrh r1, [r3, #2] PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ae0c: 889a ldrh r2, [r3, #4] PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800ae0e: ba40 rev16 r0, r0 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ae10: ba49 rev16 r1, r1 PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ae12: ba52 rev16 r2, r2 PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800ae14: b280 uxth r0, r0 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ae16: b289 uxth r1, r1 PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ae18: b292 uxth r2, r2 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ae1a: e9c3 0102 strd r0, r1, [r3, #8] PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ae1e: 611a str r2, [r3, #16] } 800ae20: bd38 pop {r3, r4, r5, pc} if(CanId.command==0x08){ 800ae22: 2d08 cmp r5, #8 800ae24: d03a beq.n 800ae9c if(CanId.command==0x09){ 800ae26: 2d09 cmp r5, #9 800ae28: d1c4 bne.n 800adb4 memcpy(&PSU_09, RxData, 8); 800ae2a: e894 0003 ldmia.w r4, {r0, r1} PSU0.temperature = PSU_04.moduleTemperature; 800ae2e: 4b21 ldr r3, [pc, #132] @ (800aeb4 ) memcpy(&PSU_09, RxData, 8); 800ae30: 4d24 ldr r5, [pc, #144] @ (800aec4 ) PSU0.outputVoltage = v; 800ae32: 4c21 ldr r4, [pc, #132] @ (800aeb8 ) PSU0.temperature = PSU_04.moduleTemperature; 800ae34: f893 c004 ldrb.w ip, [r3, #4] uint16_t v = PSU_09.moduleNVoltage / 1000; 800ae38: 4a23 ldr r2, [pc, #140] @ (800aec8 ) memcpy(&PSU_09, RxData, 8); 800ae3a: e885 0003 stmia.w r5, {r0, r1} PSU_09.moduleNCurrent = PSU_09.moduleNCurrent_[3]; 800ae3e: ba00 rev r0, r0 PSU0.temperature = PSU_04.moduleTemperature; 800ae40: f884 c006 strb.w ip, [r4, #6] uint16_t v = PSU_09.moduleNVoltage / 1000; 800ae44: fba2 c200 umull ip, r2, r2, r0 800ae48: ba09 rev r1, r1 PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[0]<<24; 800ae4a: e9c5 0102 strd r0, r1, [r5, #8] uint16_t v = PSU_09.moduleNVoltage / 1000; 800ae4e: f3c2 108f ubfx r0, r2, #6, #16 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800ae52: 2813 cmp r0, #19 PSU0.online = 1; 800ae54: f04f 0e01 mov.w lr, #1 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800ae58: bf94 ite ls 800ae5a: 2500 movls r5, #0 800ae5c: 2501 movhi r5, #1 int16_t i = PSU_09.moduleNCurrent / 100; 800ae5e: 4b1b ldr r3, [pc, #108] @ (800aecc ) PSU0.online = 1; 800ae60: f884 e008 strb.w lr, [r4, #8] int16_t i = PSU_09.moduleNCurrent / 100; 800ae64: fba3 c301 umull ip, r3, r3, r1 if(PSU0.state >= PSU_READY){ 800ae68: 79e1 ldrb r1, [r4, #7] int16_t i = PSU_09.moduleNCurrent / 100; 800ae6a: 095b lsrs r3, r3, #5 if(PSU0.state >= PSU_READY){ 800ae6c: 4571 cmp r1, lr PSU0.outputVoltage = v; 800ae6e: 8060 strh r0, [r4, #2] int16_t i = PSU_09.moduleNCurrent / 100; 800ae70: 80a3 strh r3, [r4, #4] uint16_t v = PSU_09.moduleNVoltage / 1000; 800ae72: ea4f 1292 mov.w r2, r2, lsr #6 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800ae76: 72a5 strb r5, [r4, #10] if(PSU0.state >= PSU_READY){ 800ae78: d99c bls.n 800adb4 CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800ae7a: b299 uxth r1, r3 800ae7c: b292 uxth r2, r2 800ae7e: fb01 f202 mul.w r2, r1, r2 800ae82: 4c13 ldr r4, [pc, #76] @ (800aed0 ) CONN.MeasuredVoltage = PSU0.outputVoltage; 800ae84: 4913 ldr r1, [pc, #76] @ (800aed4 ) CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800ae86: fba4 4202 umull r4, r2, r4, r2 CONN.MeasuredCurrent = PSU0.outputCurrent; 800ae8a: f8a1 3015 strh.w r3, [r1, #21] CONN.outputEnabled = PSU0.PSU_enabled; 800ae8e: 760d strb r5, [r1, #24] CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800ae90: 08d3 lsrs r3, r2, #3 CONN.MeasuredVoltage = PSU0.outputVoltage; 800ae92: f8a1 0013 strh.w r0, [r1, #19] CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800ae96: f8c1 3003 str.w r3, [r1, #3] } 800ae9a: bd38 pop {r3, r4, r5, pc} memcpy(&PSU_08, RxData, 8); 800ae9c: 4b0e ldr r3, [pc, #56] @ (800aed8 ) 800ae9e: e894 0003 ldmia.w r4, {r0, r1} 800aea2: e883 0003 stmia.w r3, {r0, r1} } 800aea6: bd38 pop {r3, r4, r5, pc} 800aea8: 2000094c .word 0x2000094c 800aeac: 20000930 .word 0x20000930 800aeb0: 2000092c .word 0x2000092c 800aeb4: 200008cc .word 0x200008cc 800aeb8: 20000904 .word 0x20000904 800aebc: 200008c0 .word 0x200008c0 800aec0: 200008d8 .word 0x200008d8 800aec4: 200008f4 .word 0x200008f4 800aec8: 10624dd3 .word 0x10624dd3 800aecc: 51eb851f .word 0x51eb851f 800aed0: cccccccd .word 0xcccccccd 800aed4: 200003b0 .word 0x200003b0 800aed8: 200008ec .word 0x200008ec 0800aedc : void PSU_CAN_FilterInit(){ 800aedc: b580 push {r7, lr} 800aede: b08a sub sp, #40 @ 0x28 800aee0: af00 add r7, sp, #0 CAN_FilterTypeDef sFilterConfig; sFilterConfig.FilterBank = 14; 800aee2: 230e movs r3, #14 800aee4: 617b str r3, [r7, #20] sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; 800aee6: 2300 movs r3, #0 800aee8: 61bb str r3, [r7, #24] sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; 800aeea: 2301 movs r3, #1 800aeec: 61fb str r3, [r7, #28] sFilterConfig.FilterIdHigh = 0x0000; 800aeee: 2300 movs r3, #0 800aef0: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = 0x0000; 800aef2: 2300 movs r3, #0 800aef4: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 800aef6: 2300 movs r3, #0 800aef8: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = 0x0000; 800aefa: 2300 movs r3, #0 800aefc: 60fb str r3, [r7, #12] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; 800aefe: 2300 movs r3, #0 800af00: 613b str r3, [r7, #16] sFilterConfig.FilterActivation = ENABLE; 800af02: 2301 movs r3, #1 800af04: 623b str r3, [r7, #32] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 800af06: 2301 movs r3, #1 800af08: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 800af0a: 230e movs r3, #14 800af0c: 627b str r3, [r7, #36] @ 0x24 if(HAL_CAN_ConfigFilter(&hcan2, &sFilterConfig) != HAL_OK) 800af0e: 463b mov r3, r7 800af10: 4619 mov r1, r3 800af12: 4806 ldr r0, [pc, #24] @ (800af2c ) 800af14: f004 f87a bl 800f00c 800af18: 4603 mov r3, r0 800af1a: 2b00 cmp r3, #0 800af1c: d001 beq.n 800af22 { Error_Handler(); 800af1e: f7ff feb1 bl 800ac84 } } 800af22: bf00 nop 800af24: 3728 adds r7, #40 @ 0x28 800af26: 46bd mov sp, r7 800af28: bd80 pop {r7, pc} 800af2a: bf00 nop 800af2c: 20000384 .word 0x20000384 0800af30 : void PSU_Init(){ 800af30: b580 push {r7, lr} 800af32: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan2); 800af34: 4815 ldr r0, [pc, #84] @ (800af8c ) 800af36: f004 f98d bl 800f254 MX_CAN2_Init(); 800af3a: f7fe fe67 bl 8009c0c PSU_CAN_FilterInit(); 800af3e: f7ff ffcd bl 800aedc HAL_CAN_Start(&hcan2); 800af42: 4812 ldr r0, [pc, #72] @ (800af8c ) 800af44: f004 f942 bl 800f1cc HAL_CAN_ActivateNotification(&hcan2, CAN_IT_RX_FIFO1_MSG_PENDING /* | CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | CAN_IT_TX_MAILBOX_EMPTY*/); 800af48: 2110 movs r1, #16 800af4a: 4810 ldr r0, [pc, #64] @ (800af8c ) 800af4c: f004 fbef bl 800f72e memset(&PSU0, 0, sizeof(PSU0)); 800af50: 2228 movs r2, #40 @ 0x28 800af52: 2100 movs r1, #0 800af54: 480e ldr r0, [pc, #56] @ (800af90 ) 800af56: f009 fea9 bl 8014cac PSU0.state = PSU_UNREADY; 800af5a: 4b0d ldr r3, [pc, #52] @ (800af90 ) 800af5c: 2200 movs r2, #0 800af5e: 71da strb r2, [r3, #7] PSU0.statetick = HAL_GetTick(); 800af60: f003 f9ea bl 800e338 800af64: 4603 mov r3, r0 800af66: 4a0a ldr r2, [pc, #40] @ (800af90 ) 800af68: 6113 str r3, [r2, #16] PSU0.power_limit = PSU_MAX_POWER; // kW 800af6a: 4b09 ldr r3, [pc, #36] @ (800af90 ) 800af6c: f649 4240 movw r2, #40000 @ 0x9c40 800af70: 615a str r2, [r3, #20] PSU0.hv_mode = 0; 800af72: 4b07 ldr r3, [pc, #28] @ (800af90 ) 800af74: 2200 movs r2, #0 800af76: 761a strb r2, [r3, #24] PSU0.hv_tick = 0; 800af78: 4b05 ldr r3, [pc, #20] @ (800af90 ) 800af7a: 2200 movs r2, #0 800af7c: 61da str r2, [r3, #28] PSU_Enable(0, 0); 800af7e: 2100 movs r1, #0 800af80: 2000 movs r0, #0 800af82: f000 f807 bl 800af94 } 800af86: bf00 nop 800af88: bd80 pop {r7, pc} 800af8a: bf00 nop 800af8c: 20000384 .word 0x20000384 800af90: 20000904 .word 0x20000904 0800af94 : void PSU_Enable(uint8_t addr, uint8_t enable){ 800af94: b580 push {r7, lr} 800af96: b084 sub sp, #16 800af98: af00 add r7, sp, #0 800af9a: 4603 mov r3, r0 800af9c: 460a mov r2, r1 800af9e: 71fb strb r3, [r7, #7] 800afa0: 4613 mov r3, r2 800afa2: 71bb strb r3, [r7, #6] PSU_1A_t data; memset(&data, 0, sizeof(data)); 800afa4: f107 0308 add.w r3, r7, #8 800afa8: 2208 movs r2, #8 800afaa: 2100 movs r1, #0 800afac: 4618 mov r0, r3 800afae: f009 fe7d bl 8014cac /* Для DC30 поддерживается только один модуль с адресом 0 */ if(addr != 0) return; 800afb2: 79fb ldrb r3, [r7, #7] 800afb4: 2b00 cmp r3, #0 800afb6: d115 bne.n 800afe4 if(PSU0.online == 0) return; 800afb8: 4b0d ldr r3, [pc, #52] @ (800aff0 ) 800afba: 7a1b ldrb r3, [r3, #8] 800afbc: 2b00 cmp r3, #0 800afbe: d013 beq.n 800afe8 data.enable = !enable; 800afc0: 79bb ldrb r3, [r7, #6] 800afc2: 2b00 cmp r3, #0 800afc4: bf0c ite eq 800afc6: 2301 moveq r3, #1 800afc8: 2300 movne r3, #0 800afca: b2db uxtb r3, r3 800afcc: 723b strb r3, [r7, #8] PSU_SendCmd(0xF0, addr, 0x1A, &data); 800afce: f107 0308 add.w r3, r7, #8 800afd2: 79f9 ldrb r1, [r7, #7] 800afd4: 221a movs r2, #26 800afd6: 20f0 movs r0, #240 @ 0xf0 800afd8: f000 f866 bl 800b0a8 ED_Delay(CAN_DELAY); 800afdc: 2014 movs r0, #20 800afde: f7ff fcb7 bl 800a950 800afe2: e002 b.n 800afea if(addr != 0) return; 800afe4: bf00 nop 800afe6: e000 b.n 800afea if(PSU0.online == 0) return; 800afe8: bf00 nop } 800afea: 3710 adds r7, #16 800afec: 46bd mov sp, r7 800afee: bd80 pop {r7, pc} 800aff0: 20000904 .word 0x20000904 0800aff4 : memset(&data, 0, sizeof(data)); data.enable = !enable; if(addr != 0) return; PSU_SendCmd(0xF0, addr, 0x1D, &data); } void PSU_SetVoltageCurrent(uint8_t addr, uint16_t voltage, uint16_t current){ 800aff4: b580 push {r7, lr} 800aff6: b086 sub sp, #24 800aff8: af00 add r7, sp, #0 800affa: 4603 mov r3, r0 800affc: 71fb strb r3, [r7, #7] 800affe: 460b mov r3, r1 800b000: 80bb strh r3, [r7, #4] 800b002: 4613 mov r3, r2 800b004: 807b strh r3, [r7, #2] PSU_1C_t data; memset(&data, 0, sizeof(data)); 800b006: f107 0308 add.w r3, r7, #8 800b00a: 2208 movs r2, #8 800b00c: 2100 movs r1, #0 800b00e: 4618 mov r0, r3 800b010: f009 fe4c bl 8014cac if(addr != 0) return; 800b014: 79fb ldrb r3, [r7, #7] 800b016: 2b00 cmp r3, #0 800b018: d140 bne.n 800b09c if(voltage 800b020: 2396 movs r3, #150 @ 0x96 800b022: 80bb strh r3, [r7, #4] if((PSU0.hv_mode==0) && voltage>499) voltage = 499; 800b024: 4b1f ldr r3, [pc, #124] @ (800b0a4 ) 800b026: 7e1b ldrb r3, [r3, #24] 800b028: 2b00 cmp r3, #0 800b02a: d106 bne.n 800b03a 800b02c: 88bb ldrh r3, [r7, #4] 800b02e: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b032: d302 bcc.n 800b03a 800b034: f240 13f3 movw r3, #499 @ 0x1f3 800b038: 80bb strh r3, [r7, #4] uint32_t current_ma = current * 100; 800b03a: 887b ldrh r3, [r7, #2] 800b03c: 2264 movs r2, #100 @ 0x64 800b03e: fb02 f303 mul.w r3, r2, r3 800b042: 617b str r3, [r7, #20] uint32_t voltage_mv = voltage * 1000; 800b044: 88bb ldrh r3, [r7, #4] 800b046: f44f 727a mov.w r2, #1000 @ 0x3e8 800b04a: fb02 f303 mul.w r3, r2, r3 800b04e: 613b str r3, [r7, #16] data.moduleCurrentTotal[0] = (current_ma >> 24) & 0xFF; 800b050: 697b ldr r3, [r7, #20] 800b052: 0e1b lsrs r3, r3, #24 800b054: b2db uxtb r3, r3 800b056: 733b strb r3, [r7, #12] data.moduleCurrentTotal[1] = (current_ma >> 16) & 0xFF; 800b058: 697b ldr r3, [r7, #20] 800b05a: 0c1b lsrs r3, r3, #16 800b05c: b2db uxtb r3, r3 800b05e: 737b strb r3, [r7, #13] data.moduleCurrentTotal[2] = (current_ma >> 8) & 0xFF; 800b060: 697b ldr r3, [r7, #20] 800b062: 0a1b lsrs r3, r3, #8 800b064: b2db uxtb r3, r3 800b066: 73bb strb r3, [r7, #14] data.moduleCurrentTotal[3] = (current_ma >> 0) & 0xFF; 800b068: 697b ldr r3, [r7, #20] 800b06a: b2db uxtb r3, r3 800b06c: 73fb strb r3, [r7, #15] data.moduleVoltage[0] = (voltage_mv >> 24) & 0xFF; 800b06e: 693b ldr r3, [r7, #16] 800b070: 0e1b lsrs r3, r3, #24 800b072: b2db uxtb r3, r3 800b074: 723b strb r3, [r7, #8] data.moduleVoltage[1] = (voltage_mv >> 16) & 0xFF; 800b076: 693b ldr r3, [r7, #16] 800b078: 0c1b lsrs r3, r3, #16 800b07a: b2db uxtb r3, r3 800b07c: 727b strb r3, [r7, #9] data.moduleVoltage[2] = (voltage_mv >> 8) & 0xFF; 800b07e: 693b ldr r3, [r7, #16] 800b080: 0a1b lsrs r3, r3, #8 800b082: b2db uxtb r3, r3 800b084: 72bb strb r3, [r7, #10] data.moduleVoltage[3] = (voltage_mv >> 0) & 0xFF; 800b086: 693b ldr r3, [r7, #16] 800b088: b2db uxtb r3, r3 800b08a: 72fb strb r3, [r7, #11] PSU_SendCmd(0xF0, addr, 0x1C, &data); 800b08c: f107 0308 add.w r3, r7, #8 800b090: 79f9 ldrb r1, [r7, #7] 800b092: 221c movs r2, #28 800b094: 20f0 movs r0, #240 @ 0xf0 800b096: f000 f807 bl 800b0a8 800b09a: e000 b.n 800b09e if(addr != 0) return; 800b09c: bf00 nop } 800b09e: 3718 adds r7, #24 800b0a0: 46bd mov sp, r7 800b0a2: bd80 pop {r7, pc} 800b0a4: 20000904 .word 0x20000904 0800b0a8 : void PSU_SendCmd(uint8_t source, uint8_t destination, uint8_t cmd, void *data){ 800b0a8: b580 push {r7, lr} 800b0aa: b08c sub sp, #48 @ 0x30 800b0ac: af00 add r7, sp, #0 800b0ae: 603b str r3, [r7, #0] 800b0b0: 4603 mov r3, r0 800b0b2: 71fb strb r3, [r7, #7] 800b0b4: 460b mov r3, r1 800b0b6: 71bb strb r3, [r7, #6] 800b0b8: 4613 mov r3, r2 800b0ba: 717b strb r3, [r7, #5] CanId_t CanId; CanId.source = source; 800b0bc: 79fb ldrb r3, [r7, #7] 800b0be: f887 3028 strb.w r3, [r7, #40] @ 0x28 CanId.destination = destination; 800b0c2: 79bb ldrb r3, [r7, #6] 800b0c4: f887 3029 strb.w r3, [r7, #41] @ 0x29 CanId.command = cmd; 800b0c8: 797b ldrb r3, [r7, #5] 800b0ca: f003 033f and.w r3, r3, #63 @ 0x3f 800b0ce: b2da uxtb r2, r3 800b0d0: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 800b0d4: f362 0305 bfi r3, r2, #0, #6 800b0d8: f887 302a strb.w r3, [r7, #42] @ 0x2a CanId.device = 0x0A; 800b0dc: 8d7b ldrh r3, [r7, #42] @ 0x2a 800b0de: 220a movs r2, #10 800b0e0: f362 1389 bfi r3, r2, #6, #4 800b0e4: 857b strh r3, [r7, #42] @ 0x2a int8_t retry_counter = 10; 800b0e6: 230a movs r3, #10 800b0e8: f887 302f strb.w r3, [r7, #47] @ 0x2f CAN_TxHeaderTypeDef tx_header; uint32_t tx_mailbox; HAL_StatusTypeDef CAN_result; memcpy(&tx_header.ExtId, &CanId, sizeof(CanId_t)); 800b0ec: 6abb ldr r3, [r7, #40] @ 0x28 800b0ee: 617b str r3, [r7, #20] tx_header.RTR = CAN_RTR_DATA; 800b0f0: 2300 movs r3, #0 800b0f2: 61fb str r3, [r7, #28] tx_header.IDE = CAN_ID_EXT; 800b0f4: 2304 movs r3, #4 800b0f6: 61bb str r3, [r7, #24] tx_header.DLC = 8; 800b0f8: 2308 movs r3, #8 800b0fa: 623b str r3, [r7, #32] while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800b0fc: e01e b.n 800b13c if (HAL_CAN_GetTxMailboxesFreeLevel(&hcan2) > 0){ 800b0fe: 4814 ldr r0, [pc, #80] @ (800b150 ) 800b100: f004 f9c0 bl 800f484 800b104: 4603 mov r3, r0 800b106: 2b00 cmp r3, #0 800b108: d00e beq.n 800b128 /* отправка сообщения */ CAN_result = HAL_CAN_AddTxMessage(&hcan2, &tx_header, (uint8_t*)data, &tx_mailbox); 800b10a: f107 030c add.w r3, r7, #12 800b10e: f107 0110 add.w r1, r7, #16 800b112: 683a ldr r2, [r7, #0] 800b114: 480e ldr r0, [pc, #56] @ (800b150 ) 800b116: f004 f8e6 bl 800f2e6 800b11a: 4603 mov r3, r0 800b11c: f887 302e strb.w r3, [r7, #46] @ 0x2e /* если отправка удалась, выход */ if(CAN_result == HAL_OK) { 800b120: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 800b124: 2b00 cmp r3, #0 800b126: d00e beq.n 800b146 return; } } ED_Delay(1); 800b128: 2001 movs r0, #1 800b12a: f7ff fc11 bl 800a950 retry_counter--; 800b12e: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800b132: b2db uxtb r3, r3 800b134: 3b01 subs r3, #1 800b136: b2db uxtb r3, r3 800b138: f887 302f strb.w r3, [r7, #47] @ 0x2f while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800b13c: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800b140: 2b00 cmp r3, #0 800b142: dcdc bgt.n 800b0fe 800b144: e000 b.n 800b148 return; 800b146: bf00 nop } } 800b148: 3730 adds r7, #48 @ 0x30 800b14a: 46bd mov sp, r7 800b14c: bd80 pop {r7, pc} 800b14e: bf00 nop 800b150: 20000384 .word 0x20000384 0800b154 : void PSU_ReadWrite(){ 800b154: b580 push {r7, lr} 800b156: b082 sub sp, #8 800b158: af00 add r7, sp, #0 uint8_t zero_data[8] = {0,0,0,0,0,0,0,0}; 800b15a: 463b mov r3, r7 800b15c: 2200 movs r2, #0 800b15e: 601a str r2, [r3, #0] 800b160: 605a str r2, [r3, #4] PSU_SendCmd(0xF0, 0, 0x04, zero_data);ED_Delay(CAN_DELAY); 800b162: 463b mov r3, r7 800b164: 2204 movs r2, #4 800b166: 2100 movs r1, #0 800b168: 20f0 movs r0, #240 @ 0xf0 800b16a: f7ff ff9d bl 800b0a8 800b16e: 2014 movs r0, #20 800b170: f7ff fbee bl 800a950 PSU_SendCmd(0xF0, 0, 0x06, zero_data);ED_Delay(CAN_DELAY); 800b174: 463b mov r3, r7 800b176: 2206 movs r2, #6 800b178: 2100 movs r1, #0 800b17a: 20f0 movs r0, #240 @ 0xf0 800b17c: f7ff ff94 bl 800b0a8 800b180: 2014 movs r0, #20 800b182: f7ff fbe5 bl 800a950 // PSU_SendCmd(0xF0, 0, 0x08, zero_data);ED_Delay(CAN_DELAY); PSU_SendCmd(0xF0, 0, 0x09, zero_data);ED_Delay(CAN_DELAY); 800b186: 463b mov r3, r7 800b188: 2209 movs r2, #9 800b18a: 2100 movs r1, #0 800b18c: 20f0 movs r0, #240 @ 0xf0 800b18e: f7ff ff8b bl 800b0a8 800b192: 2014 movs r0, #20 800b194: f7ff fbdc bl 800a950 // Power Limit if ((CONN.WantedCurrent/10) * CONN.MeasuredVoltage > PSU0.power_limit){ 800b198: 4b4d ldr r3, [pc, #308] @ (800b2d0 ) 800b19a: f8b3 301b ldrh.w r3, [r3, #27] 800b19e: b29b uxth r3, r3 800b1a0: 4a4c ldr r2, [pc, #304] @ (800b2d4 ) 800b1a2: fba2 2303 umull r2, r3, r2, r3 800b1a6: 08db lsrs r3, r3, #3 800b1a8: b29b uxth r3, r3 800b1aa: 461a mov r2, r3 800b1ac: 4b48 ldr r3, [pc, #288] @ (800b2d0 ) 800b1ae: f8b3 3013 ldrh.w r3, [r3, #19] 800b1b2: b29b uxth r3, r3 800b1b4: fb02 f303 mul.w r3, r2, r3 800b1b8: 461a mov r2, r3 800b1ba: 4b47 ldr r3, [pc, #284] @ (800b2d8 ) 800b1bc: 695b ldr r3, [r3, #20] 800b1be: 429a cmp r2, r3 800b1c0: d911 bls.n 800b1e6 CONN.RequestedCurrent = PSU0.power_limit * 10 / CONN.MeasuredVoltage; 800b1c2: 4b45 ldr r3, [pc, #276] @ (800b2d8 ) 800b1c4: 695a ldr r2, [r3, #20] 800b1c6: 4613 mov r3, r2 800b1c8: 009b lsls r3, r3, #2 800b1ca: 4413 add r3, r2 800b1cc: 005b lsls r3, r3, #1 800b1ce: 461a mov r2, r3 800b1d0: 4b3f ldr r3, [pc, #252] @ (800b2d0 ) 800b1d2: f8b3 3013 ldrh.w r3, [r3, #19] 800b1d6: b29b uxth r3, r3 800b1d8: fbb2 f3f3 udiv r3, r2, r3 800b1dc: b29a uxth r2, r3 800b1de: 4b3c ldr r3, [pc, #240] @ (800b2d0 ) 800b1e0: f8a3 2011 strh.w r2, [r3, #17] 800b1e4: e006 b.n 800b1f4 }else{ CONN.RequestedCurrent = CONN.WantedCurrent; 800b1e6: 4b3a ldr r3, [pc, #232] @ (800b2d0 ) 800b1e8: f8b3 301b ldrh.w r3, [r3, #27] 800b1ec: b29a uxth r2, r3 800b1ee: 4b38 ldr r3, [pc, #224] @ (800b2d0 ) 800b1f0: f8a3 2011 strh.w r2, [r3, #17] } if(CONN.RequestedCurrent > (PSU_MAX_CURRENT*10)){ 800b1f4: 4b36 ldr r3, [pc, #216] @ (800b2d0 ) 800b1f6: f8b3 3011 ldrh.w r3, [r3, #17] 800b1fa: b29b uxth r3, r3 800b1fc: f240 5232 movw r2, #1330 @ 0x532 800b200: 4293 cmp r3, r2 800b202: d908 bls.n 800b216 CONN.RequestedCurrent = PSU_MAX_CURRENT*10; 800b204: 4b32 ldr r3, [pc, #200] @ (800b2d0 ) 800b206: 2200 movs r2, #0 800b208: f042 0232 orr.w r2, r2, #50 @ 0x32 800b20c: 745a strb r2, [r3, #17] 800b20e: 2200 movs r2, #0 800b210: f042 0205 orr.w r2, r2, #5 800b214: 749a strb r2, [r3, #18] } CONN.RequestedPower = CONN.RequestedCurrent * CONN.RequestedVoltage / 10; 800b216: 4b2e ldr r3, [pc, #184] @ (800b2d0 ) 800b218: f8b3 3011 ldrh.w r3, [r3, #17] 800b21c: b29b uxth r3, r3 800b21e: 461a mov r2, r3 800b220: 4b2b ldr r3, [pc, #172] @ (800b2d0 ) 800b222: f8b3 300f ldrh.w r3, [r3, #15] 800b226: b29b uxth r3, r3 800b228: fb02 f303 mul.w r3, r2, r3 800b22c: 4a2b ldr r2, [pc, #172] @ (800b2dc ) 800b22e: fb82 1203 smull r1, r2, r2, r3 800b232: 1092 asrs r2, r2, #2 800b234: 17db asrs r3, r3, #31 800b236: 1ad3 subs r3, r2, r3 800b238: 461a mov r2, r3 800b23a: 4b25 ldr r3, [pc, #148] @ (800b2d0 ) 800b23c: f8c3 200b str.w r2, [r3, #11] if(PSU0.ready){ 800b240: 4b25 ldr r3, [pc, #148] @ (800b2d8 ) 800b242: 7a5b ldrb r3, [r3, #9] 800b244: 2b00 cmp r3, #0 800b246: d03e beq.n 800b2c6 if (CONN.RequestedVoltage == FAKE_EVREQ_VOLTAGE_V) { 800b248: 4b21 ldr r3, [pc, #132] @ (800b2d0 ) 800b24a: f8b3 300f ldrh.w r3, [r3, #15] 800b24e: b29b uxth r3, r3 800b250: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b254: d106 bne.n 800b264 PSU_SetVoltageCurrent(0, (uint16_t)FAKE_PSU_VOLTAGE_V, (uint16_t)FAKE_PSU_CURRENT_0P1A); 800b256: 220a movs r2, #10 800b258: f44f 7196 mov.w r1, #300 @ 0x12c 800b25c: 2000 movs r0, #0 800b25e: f7ff fec9 bl 800aff4 800b262: e00b b.n 800b27c }else{ PSU_SetVoltageCurrent(0, CONN.RequestedVoltage, CONN.RequestedCurrent); // Normal mode 800b264: 4b1a ldr r3, [pc, #104] @ (800b2d0 ) 800b266: f8b3 300f ldrh.w r3, [r3, #15] 800b26a: b29b uxth r3, r3 800b26c: 4a18 ldr r2, [pc, #96] @ (800b2d0 ) 800b26e: f8b2 2011 ldrh.w r2, [r2, #17] 800b272: b292 uxth r2, r2 800b274: 4619 mov r1, r3 800b276: 2000 movs r0, #0 800b278: f7ff febc bl 800aff4 } ED_Delay(CAN_DELAY); 800b27c: 2014 movs r0, #20 800b27e: f7ff fb67 bl 800a950 if(CONN.MeasuredVoltage > 490){ 800b282: 4b13 ldr r3, [pc, #76] @ (800b2d0 ) 800b284: f8b3 3013 ldrh.w r3, [r3, #19] 800b288: b29b uxth r3, r3 800b28a: f5b3 7ff5 cmp.w r3, #490 @ 0x1ea 800b28e: d917 bls.n 800b2c0 if(PSU0.hv_tick == 0){ 800b290: 4b11 ldr r3, [pc, #68] @ (800b2d8 ) 800b292: 69db ldr r3, [r3, #28] 800b294: 2b00 cmp r3, #0 800b296: d105 bne.n 800b2a4 PSU0.hv_tick = HAL_GetTick(); 800b298: f003 f84e bl 800e338 800b29c: 4603 mov r3, r0 800b29e: 4a0e ldr r2, [pc, #56] @ (800b2d8 ) 800b2a0: 61d3 str r3, [r2, #28] } // PSU_SetHVMode(0, PSU0.hv_mode); // auto set, no need // ED_Delay(CAN_DELAY); } 800b2a2: e010 b.n 800b2c6 }else if((HAL_GetTick() - PSU0.hv_tick) >= 10000){ 800b2a4: f003 f848 bl 800e338 800b2a8: 4602 mov r2, r0 800b2aa: 4b0b ldr r3, [pc, #44] @ (800b2d8 ) 800b2ac: 69db ldr r3, [r3, #28] 800b2ae: 1ad3 subs r3, r2, r3 800b2b0: f242 720f movw r2, #9999 @ 0x270f 800b2b4: 4293 cmp r3, r2 800b2b6: d906 bls.n 800b2c6 PSU0.hv_mode = 1; 800b2b8: 4b07 ldr r3, [pc, #28] @ (800b2d8 ) 800b2ba: 2201 movs r2, #1 800b2bc: 761a strb r2, [r3, #24] } 800b2be: e002 b.n 800b2c6 PSU0.hv_tick = 0; 800b2c0: 4b05 ldr r3, [pc, #20] @ (800b2d8 ) 800b2c2: 2200 movs r2, #0 800b2c4: 61da str r2, [r3, #28] } 800b2c6: bf00 nop 800b2c8: 3708 adds r7, #8 800b2ca: 46bd mov sp, r7 800b2cc: bd80 pop {r7, pc} 800b2ce: bf00 nop 800b2d0: 200003b0 .word 0x200003b0 800b2d4: cccccccd .word 0xcccccccd 800b2d8: 20000904 .word 0x20000904 800b2dc: 66666667 .word 0x66666667 0800b2e0 : void PSU_Task(void){ 800b2e0: b598 push {r3, r4, r7, lr} 800b2e2: af00 add r7, sp, #0 static uint32_t psu_on_tick = 0; static uint32_t cont_ok_tick = 0; // Обновляем ONLINE/READY по таймауту if((HAL_GetTick() - can_lastpacket) > PSU_ONLINE_TIMEOUT){ 800b2e4: f003 f828 bl 800e338 800b2e8: 4602 mov r2, r0 800b2ea: 4bb3 ldr r3, [pc, #716] @ (800b5b8 ) 800b2ec: 681b ldr r3, [r3, #0] 800b2ee: 1ad3 subs r3, r2, r3 800b2f0: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b2f4: d920 bls.n 800b338 PSU0.online = 0; 800b2f6: 4bb1 ldr r3, [pc, #708] @ (800b5bc ) 800b2f8: 2200 movs r2, #0 800b2fa: 721a strb r2, [r3, #8] PSU0.PSU_enabled = 0; 800b2fc: 4baf ldr r3, [pc, #700] @ (800b5bc ) 800b2fe: 2200 movs r2, #0 800b300: 729a strb r2, [r3, #10] PSU_04.moduleTemperature = 0; 800b302: 4baf ldr r3, [pc, #700] @ (800b5c0 ) 800b304: 2200 movs r2, #0 800b306: 711a strb r2, [r3, #4] PSU_04.modularForm0 = 0; 800b308: 4bad ldr r3, [pc, #692] @ (800b5c0 ) 800b30a: 2200 movs r2, #0 800b30c: 721a strb r2, [r3, #8] PSU_04.modularForm1 = 0; 800b30e: 4bac ldr r3, [pc, #688] @ (800b5c0 ) 800b310: 2200 movs r2, #0 800b312: 71da strb r2, [r3, #7] PSU_04.modularForm2 = 0; 800b314: 4baa ldr r3, [pc, #680] @ (800b5c0 ) 800b316: 2200 movs r2, #0 800b318: 719a strb r2, [r3, #6] PSU_06.VAB = 0; 800b31a: 4baa ldr r3, [pc, #680] @ (800b5c4 ) 800b31c: 2200 movs r2, #0 800b31e: 609a str r2, [r3, #8] PSU_06.VBC = 0; 800b320: 4ba8 ldr r3, [pc, #672] @ (800b5c4 ) 800b322: 2200 movs r2, #0 800b324: 60da str r2, [r3, #12] PSU_06.VCA = 0; 800b326: 4ba7 ldr r3, [pc, #668] @ (800b5c4 ) 800b328: 2200 movs r2, #0 800b32a: 611a str r2, [r3, #16] PSU_09.moduleNCurrent = 0; 800b32c: 4ba6 ldr r3, [pc, #664] @ (800b5c8 ) 800b32e: 2200 movs r2, #0 800b330: 60da str r2, [r3, #12] PSU_09.moduleNVoltage = 0; 800b332: 4ba5 ldr r3, [pc, #660] @ (800b5c8 ) 800b334: 2200 movs r2, #0 800b336: 609a str r2, [r3, #8] } if(!PSU0.online || !PSU0.enableAC){ 800b338: 4ba0 ldr r3, [pc, #640] @ (800b5bc ) 800b33a: 7a1b ldrb r3, [r3, #8] 800b33c: 2b00 cmp r3, #0 800b33e: d003 beq.n 800b348 800b340: 4b9e ldr r3, [pc, #632] @ (800b5bc ) 800b342: 781b ldrb r3, [r3, #0] 800b344: 2b00 cmp r3, #0 800b346: d10c bne.n 800b362 CONN.MeasuredVoltage = 0; 800b348: 4ba0 ldr r3, [pc, #640] @ (800b5cc ) 800b34a: 2200 movs r2, #0 800b34c: 74da strb r2, [r3, #19] 800b34e: 2200 movs r2, #0 800b350: 751a strb r2, [r3, #20] CONN.MeasuredCurrent = 0; 800b352: 4b9e ldr r3, [pc, #632] @ (800b5cc ) 800b354: 2200 movs r2, #0 800b356: 755a strb r2, [r3, #21] 800b358: 2200 movs r2, #0 800b35a: 759a strb r2, [r3, #22] CONN.outputEnabled = 0; 800b35c: 4b9b ldr r3, [pc, #620] @ (800b5cc ) 800b35e: 2200 movs r2, #0 800b360: 761a strb r2, [r3, #24] } // Управление AC-контактором с задержкой отключения 1 минута if(CONN.EvConnected){ 800b362: 4b9a ldr r3, [pc, #616] @ (800b5cc ) 800b364: 7f9b ldrb r3, [r3, #30] 800b366: 2b00 cmp r3, #0 800b368: d00c beq.n 800b384 RELAY_Write(RELAY_AC, 1); 800b36a: 2101 movs r1, #1 800b36c: 2004 movs r0, #4 800b36e: f7fe fa23 bl 80097b8 psu_on_tick = HAL_GetTick(); 800b372: f002 ffe1 bl 800e338 800b376: 4603 mov r3, r0 800b378: 4a95 ldr r2, [pc, #596] @ (800b5d0 ) 800b37a: 6013 str r3, [r2, #0] PSU0.enableAC = 1; 800b37c: 4b8f ldr r3, [pc, #572] @ (800b5bc ) 800b37e: 2201 movs r2, #1 800b380: 701a strb r2, [r3, #0] 800b382: e010 b.n 800b3a6 }else{ if((HAL_GetTick() - psu_on_tick) > 1 * 60000){ 800b384: f002 ffd8 bl 800e338 800b388: 4602 mov r2, r0 800b38a: 4b91 ldr r3, [pc, #580] @ (800b5d0 ) 800b38c: 681b ldr r3, [r3, #0] 800b38e: 1ad3 subs r3, r2, r3 800b390: f64e 2260 movw r2, #60000 @ 0xea60 800b394: 4293 cmp r3, r2 800b396: d906 bls.n 800b3a6 RELAY_Write(RELAY_AC, 0); 800b398: 2100 movs r1, #0 800b39a: 2004 movs r0, #4 800b39c: f7fe fa0c bl 80097b8 PSU0.enableAC = 0; 800b3a0: 4b86 ldr r3, [pc, #536] @ (800b5bc ) 800b3a2: 2200 movs r2, #0 800b3a4: 701a strb r2, [r3, #0] } } // Текущее состояние DC-контактора по обратной связи PSU0.CONT_enabled = IN_ReadInput(IN_CONT_FB_DC); 800b3a6: 2005 movs r0, #5 800b3a8: f7fe fa86 bl 80098b8 800b3ac: 4603 mov r3, r0 800b3ae: 461a mov r2, r3 800b3b0: 4b82 ldr r3, [pc, #520] @ (800b5bc ) 800b3b2: 72da strb r2, [r3, #11] // Обновляем ready с учётом ошибок if(PSU0.online && !PSU0.cont_fault && PSU0.enableAC){ 800b3b4: 4b81 ldr r3, [pc, #516] @ (800b5bc ) 800b3b6: 7a1b ldrb r3, [r3, #8] 800b3b8: 2b00 cmp r3, #0 800b3ba: d007 beq.n 800b3cc 800b3bc: 4b7f ldr r3, [pc, #508] @ (800b5bc ) 800b3be: 7b1b ldrb r3, [r3, #12] 800b3c0: 2b00 cmp r3, #0 800b3c2: d103 bne.n 800b3cc 800b3c4: 4b7d ldr r3, [pc, #500] @ (800b5bc ) 800b3c6: 781b ldrb r3, [r3, #0] 800b3c8: 2b00 cmp r3, #0 800b3ca: d102 bne.n 800b3d2 // PSU0.ready = 1; }else{ PSU0.ready = 0; 800b3cc: 4b7b ldr r3, [pc, #492] @ (800b5bc ) 800b3ce: 2200 movs r2, #0 800b3d0: 725a strb r2, [r3, #9] } switch(PSU0.state){ 800b3d2: 4b7a ldr r3, [pc, #488] @ (800b5bc ) 800b3d4: 79db ldrb r3, [r3, #7] 800b3d6: 2b09 cmp r3, #9 800b3d8: f200 8151 bhi.w 800b67e 800b3dc: a201 add r2, pc, #4 @ (adr r2, 800b3e4 ) 800b3de: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b3e2: bf00 nop 800b3e4: 0800b40d .word 0x0800b40d 800b3e8: 0800b441 .word 0x0800b441 800b3ec: 0800b45d .word 0x0800b45d 800b3f0: 0800b49b .word 0x0800b49b 800b3f4: 0800b4df .word 0x0800b4df 800b3f8: 0800b521 .word 0x0800b521 800b3fc: 0800b58b .word 0x0800b58b 800b400: 0800b631 .word 0x0800b631 800b404: 0800b5e1 .word 0x0800b5e1 800b408: 0800b66b .word 0x0800b66b case PSU_UNREADY: PSU0.enableOutput = 0; 800b40c: 4b6b ldr r3, [pc, #428] @ (800b5bc ) 800b40e: 2200 movs r2, #0 800b410: 705a strb r2, [r3, #1] RELAY_Write(RELAY_DC, 0); 800b412: 2100 movs r1, #0 800b414: 2003 movs r0, #3 800b416: f7fe f9cf bl 80097b8 if(PSU0.online && PSU0.enableAC && !PSU0.cont_fault){ 800b41a: 4b68 ldr r3, [pc, #416] @ (800b5bc ) 800b41c: 7a1b ldrb r3, [r3, #8] 800b41e: 2b00 cmp r3, #0 800b420: f000 8131 beq.w 800b686 800b424: 4b65 ldr r3, [pc, #404] @ (800b5bc ) 800b426: 781b ldrb r3, [r3, #0] 800b428: 2b00 cmp r3, #0 800b42a: f000 812c beq.w 800b686 800b42e: 4b63 ldr r3, [pc, #396] @ (800b5bc ) 800b430: 7b1b ldrb r3, [r3, #12] 800b432: 2b00 cmp r3, #0 800b434: f040 8127 bne.w 800b686 PSU_SwitchState(PSU_INITIALIZING); 800b438: 2001 movs r0, #1 800b43a: f7ff fc8f bl 800ad5c } break; 800b43e: e122 b.n 800b686 case PSU_INITIALIZING: if(PSU_StateTime() > 4000){ // Wait 4s for PSU to initialize 800b440: f7ff fca0 bl 800ad84 800b444: 4603 mov r3, r0 800b446: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b44a: f240 811e bls.w 800b68a PSU0.ready = 1; 800b44e: 4b5b ldr r3, [pc, #364] @ (800b5bc ) 800b450: 2201 movs r2, #1 800b452: 725a strb r2, [r3, #9] PSU_SwitchState(PSU_READY); 800b454: 2002 movs r0, #2 800b456: f7ff fc81 bl 800ad5c } break; 800b45a: e116 b.n 800b68a case PSU_READY: // модуль готов, но выключен PSU0.hv_mode = 0; 800b45c: 4b57 ldr r3, [pc, #348] @ (800b5bc ) 800b45e: 2200 movs r2, #0 800b460: 761a strb r2, [r3, #24] PSU0.hv_tick = 0; 800b462: 4b56 ldr r3, [pc, #344] @ (800b5bc ) 800b464: 2200 movs r2, #0 800b466: 61da str r2, [r3, #28] RELAY_Write(RELAY_DC, 0); 800b468: 2100 movs r1, #0 800b46a: 2003 movs r0, #3 800b46c: f7fe f9a4 bl 80097b8 if(!PSU0.ready){ 800b470: 4b52 ldr r3, [pc, #328] @ (800b5bc ) 800b472: 7a5b ldrb r3, [r3, #9] 800b474: 2b00 cmp r3, #0 800b476: d103 bne.n 800b480 PSU_SwitchState(PSU_UNREADY); 800b478: 2000 movs r0, #0 800b47a: f7ff fc6f bl 800ad5c break; 800b47e: e115 b.n 800b6ac } if(CONN.EnableOutput){ 800b480: 4b52 ldr r3, [pc, #328] @ (800b5cc ) 800b482: 7ddb ldrb r3, [r3, #23] 800b484: 2b00 cmp r3, #0 800b486: f000 8102 beq.w 800b68e PSU_Enable(0, 1); 800b48a: 2101 movs r1, #1 800b48c: 2000 movs r0, #0 800b48e: f7ff fd81 bl 800af94 PSU_SwitchState(PSU_WAIT_ACK_ON); 800b492: 2003 movs r0, #3 800b494: f7ff fc62 bl 800ad5c } break; 800b498: e0f9 b.n 800b68e case PSU_WAIT_ACK_ON: if(PSU0.PSU_enabled && PSU0.ready){ 800b49a: 4b48 ldr r3, [pc, #288] @ (800b5bc ) 800b49c: 7a9b ldrb r3, [r3, #10] 800b49e: 2b00 cmp r3, #0 800b4a0: d007 beq.n 800b4b2 800b4a2: 4b46 ldr r3, [pc, #280] @ (800b5bc ) 800b4a4: 7a5b ldrb r3, [r3, #9] 800b4a6: 2b00 cmp r3, #0 800b4a8: d003 beq.n 800b4b2 PSU_SwitchState(PSU_CONT_WAIT_ACK_ON); 800b4aa: 2004 movs r0, #4 800b4ac: f7ff fc56 bl 800ad5c PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU on timeout\n"); } break; 800b4b0: e0ef b.n 800b692 }else if(PSU_StateTime() > 10000){ 800b4b2: f7ff fc67 bl 800ad84 800b4b6: 4603 mov r3, r0 800b4b8: f242 7210 movw r2, #10000 @ 0x2710 800b4bc: 4293 cmp r3, r2 800b4be: f240 80e8 bls.w 800b692 PSU0.psu_fault = 1; 800b4c2: 4b3e ldr r3, [pc, #248] @ (800b5bc ) 800b4c4: 2201 movs r2, #1 800b4c6: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b4c8: 4b40 ldr r3, [pc, #256] @ (800b5cc ) 800b4ca: 220a movs r2, #10 800b4cc: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b4ce: 2000 movs r0, #0 800b4d0: f7ff fc44 bl 800ad5c log_printf(LOG_ERR, "PSU on timeout\n"); 800b4d4: 493f ldr r1, [pc, #252] @ (800b5d4 ) 800b4d6: 2004 movs r0, #4 800b4d8: f7ff f83c bl 800a554 break; 800b4dc: e0d9 b.n 800b692 case PSU_CONT_WAIT_ACK_ON: // замыкаем DC-контактор и ждём подтверждение RELAY_Write(RELAY_DC, 1); 800b4de: 2101 movs r1, #1 800b4e0: 2003 movs r0, #3 800b4e2: f7fe f969 bl 80097b8 if(PSU0.CONT_enabled){ 800b4e6: 4b35 ldr r3, [pc, #212] @ (800b5bc ) 800b4e8: 7adb ldrb r3, [r3, #11] 800b4ea: 2b00 cmp r3, #0 800b4ec: d003 beq.n 800b4f6 PSU_SwitchState(PSU_CONNECTED); 800b4ee: 2005 movs r0, #5 800b4f0: f7ff fc34 bl 800ad5c PSU0.cont_fault = 1; CONN.chargingError = CONN_ERR_CONTACTOR; PSU_SwitchState(PSU_CURRENT_DROP); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b4f4: e0cf b.n 800b696 }else if(PSU_StateTime() > 1000){ 800b4f6: f7ff fc45 bl 800ad84 800b4fa: 4603 mov r3, r0 800b4fc: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b500: f240 80c9 bls.w 800b696 PSU0.cont_fault = 1; 800b504: 4b2d ldr r3, [pc, #180] @ (800b5bc ) 800b506: 2201 movs r2, #1 800b508: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b50a: 4b30 ldr r3, [pc, #192] @ (800b5cc ) 800b50c: 2207 movs r2, #7 800b50e: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_CURRENT_DROP); 800b510: 2006 movs r0, #6 800b512: f7ff fc23 bl 800ad5c log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b516: 4930 ldr r1, [pc, #192] @ (800b5d8 ) 800b518: 2004 movs r0, #4 800b51a: f7ff f81b bl 800a554 break; 800b51e: e0ba b.n 800b696 case PSU_CONNECTED: // Основное рабочее состояние if(!CONN.EnableOutput || !PSU0.ready){ 800b520: 4b2a ldr r3, [pc, #168] @ (800b5cc ) 800b522: 7ddb ldrb r3, [r3, #23] 800b524: 2b00 cmp r3, #0 800b526: d003 beq.n 800b530 800b528: 4b24 ldr r3, [pc, #144] @ (800b5bc ) 800b52a: 7a5b ldrb r3, [r3, #9] 800b52c: 2b00 cmp r3, #0 800b52e: d103 bne.n 800b538 PSU_SwitchState(PSU_CURRENT_DROP); 800b530: 2006 movs r0, #6 800b532: f7ff fc13 bl 800ad5c break; 800b536: e0b9 b.n 800b6ac } // контроль контактора: 1 c таймаут if (IN_ReadInput(IN_CONT_FB_DC) != RELAY_Read(RELAY_DC)){ 800b538: 2005 movs r0, #5 800b53a: f7fe f9bd bl 80098b8 800b53e: 4603 mov r3, r0 800b540: 461c mov r4, r3 800b542: 2003 movs r0, #3 800b544: f7fe f9a8 bl 8009898 800b548: 4603 mov r3, r0 800b54a: 429c cmp r4, r3 800b54c: d017 beq.n 800b57e if((HAL_GetTick() - cont_ok_tick) > 1000){ 800b54e: f002 fef3 bl 800e338 800b552: 4602 mov r2, r0 800b554: 4b21 ldr r3, [pc, #132] @ (800b5dc ) 800b556: 681b ldr r3, [r3, #0] 800b558: 1ad3 subs r3, r2, r3 800b55a: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b55e: f240 809c bls.w 800b69a CONN.chargingError = CONN_ERR_CONTACTOR; 800b562: 4b1a ldr r3, [pc, #104] @ (800b5cc ) 800b564: 2207 movs r2, #7 800b566: 775a strb r2, [r3, #29] PSU0.cont_fault = 1; 800b568: 4b14 ldr r3, [pc, #80] @ (800b5bc ) 800b56a: 2201 movs r2, #1 800b56c: 731a strb r2, [r3, #12] PSU_SwitchState(PSU_CURRENT_DROP); 800b56e: 2006 movs r0, #6 800b570: f7ff fbf4 bl 800ad5c log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b574: 4918 ldr r1, [pc, #96] @ (800b5d8 ) 800b576: 2004 movs r0, #4 800b578: f7fe ffec bl 800a554 } }else{ cont_ok_tick = HAL_GetTick(); } break; 800b57c: e08d b.n 800b69a cont_ok_tick = HAL_GetTick(); 800b57e: f002 fedb bl 800e338 800b582: 4603 mov r3, r0 800b584: 4a15 ldr r2, [pc, #84] @ (800b5dc ) 800b586: 6013 str r3, [r2, #0] break; 800b588: e087 b.n 800b69a case PSU_CURRENT_DROP: // снижаем ток до нуля перед отключением DC CONN.RequestedCurrent = 0; 800b58a: 4b10 ldr r3, [pc, #64] @ (800b5cc ) 800b58c: 2200 movs r2, #0 800b58e: 745a strb r2, [r3, #17] 800b590: 2200 movs r2, #0 800b592: 749a strb r2, [r3, #18] // если ток действительно упал или вышло время, отключаем DC if((CONN.MeasuredCurrent < 30) || (PSU_StateTime() > 5000)){ 800b594: 4b0d ldr r3, [pc, #52] @ (800b5cc ) 800b596: f8b3 3015 ldrh.w r3, [r3, #21] 800b59a: b29b uxth r3, r3 800b59c: 2b1d cmp r3, #29 800b59e: d906 bls.n 800b5ae 800b5a0: f7ff fbf0 bl 800ad84 800b5a4: 4603 mov r3, r0 800b5a6: f241 3288 movw r2, #5000 @ 0x1388 800b5aa: 4293 cmp r3, r2 800b5ac: d977 bls.n 800b69e PSU_SwitchState(PSU_CONT_WAIT_ACK_OFF); 800b5ae: 2008 movs r0, #8 800b5b0: f7ff fbd4 bl 800ad5c } break; 800b5b4: e073 b.n 800b69e 800b5b6: bf00 nop 800b5b8: 2000092c .word 0x2000092c 800b5bc: 20000904 .word 0x20000904 800b5c0: 200008cc .word 0x200008cc 800b5c4: 200008d8 .word 0x200008d8 800b5c8: 200008f4 .word 0x200008f4 800b5cc: 200003b0 .word 0x200003b0 800b5d0: 20000954 .word 0x20000954 800b5d4: 0801710c .word 0x0801710c 800b5d8: 0801711c .word 0x0801711c 800b5dc: 20000958 .word 0x20000958 case PSU_CONT_WAIT_ACK_OFF: RELAY_Write(RELAY_DC, 0); 800b5e0: 2100 movs r1, #0 800b5e2: 2003 movs r0, #3 800b5e4: f7fe f8e8 bl 80097b8 if(!PSU0.CONT_enabled){ 800b5e8: 4b31 ldr r3, [pc, #196] @ (800b6b0 ) 800b5ea: 7adb ldrb r3, [r3, #11] 800b5ec: 2b00 cmp r3, #0 800b5ee: d107 bne.n 800b600 PSU_Enable(0, 0); 800b5f0: 2100 movs r1, #0 800b5f2: 2000 movs r0, #0 800b5f4: f7ff fcce bl 800af94 PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b5f8: 2007 movs r0, #7 800b5fa: f7ff fbaf bl 800ad5c CONN.chargingError = CONN_ERR_CONTACTOR; PSU_Enable(0, 0); PSU_SwitchState(PSU_WAIT_ACK_OFF); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b5fe: e050 b.n 800b6a2 }else if(PSU_StateTime() > 1000){ 800b600: f7ff fbc0 bl 800ad84 800b604: 4603 mov r3, r0 800b606: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b60a: d94a bls.n 800b6a2 PSU0.cont_fault = 1; 800b60c: 4b28 ldr r3, [pc, #160] @ (800b6b0 ) 800b60e: 2201 movs r2, #1 800b610: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b612: 4b28 ldr r3, [pc, #160] @ (800b6b4 ) 800b614: 2207 movs r2, #7 800b616: 775a strb r2, [r3, #29] PSU_Enable(0, 0); 800b618: 2100 movs r1, #0 800b61a: 2000 movs r0, #0 800b61c: f7ff fcba bl 800af94 PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b620: 2007 movs r0, #7 800b622: f7ff fb9b bl 800ad5c log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b626: 4924 ldr r1, [pc, #144] @ (800b6b8 ) 800b628: 2004 movs r0, #4 800b62a: f7fe ff93 bl 800a554 break; 800b62e: e038 b.n 800b6a2 case PSU_WAIT_ACK_OFF: if(!PSU0.PSU_enabled){ 800b630: 4b1f ldr r3, [pc, #124] @ (800b6b0 ) 800b632: 7a9b ldrb r3, [r3, #10] 800b634: 2b00 cmp r3, #0 800b636: d103 bne.n 800b640 PSU_SwitchState(PSU_OFF_PAUSE); 800b638: 2009 movs r0, #9 800b63a: f7ff fb8f bl 800ad5c PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU off timeout\n"); } break; 800b63e: e032 b.n 800b6a6 }else if(PSU_StateTime() > 10000){ 800b640: f7ff fba0 bl 800ad84 800b644: 4603 mov r3, r0 800b646: f242 7210 movw r2, #10000 @ 0x2710 800b64a: 4293 cmp r3, r2 800b64c: d92b bls.n 800b6a6 PSU0.psu_fault = 1; 800b64e: 4b18 ldr r3, [pc, #96] @ (800b6b0 ) 800b650: 2201 movs r2, #1 800b652: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b654: 4b17 ldr r3, [pc, #92] @ (800b6b4 ) 800b656: 220a movs r2, #10 800b658: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b65a: 2000 movs r0, #0 800b65c: f7ff fb7e bl 800ad5c log_printf(LOG_ERR, "PSU off timeout\n"); 800b660: 4916 ldr r1, [pc, #88] @ (800b6bc ) 800b662: 2004 movs r0, #4 800b664: f7fe ff76 bl 800a554 break; 800b668: e01d b.n 800b6a6 case PSU_OFF_PAUSE: if(PSU_StateTime() > 4000){ 800b66a: f7ff fb8b bl 800ad84 800b66e: 4603 mov r3, r0 800b670: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b674: d919 bls.n 800b6aa PSU_SwitchState(PSU_READY); 800b676: 2002 movs r0, #2 800b678: f7ff fb70 bl 800ad5c } break; 800b67c: e015 b.n 800b6aa default: PSU_SwitchState(PSU_UNREADY); 800b67e: 2000 movs r0, #0 800b680: f7ff fb6c bl 800ad5c break; 800b684: e012 b.n 800b6ac break; 800b686: bf00 nop 800b688: e010 b.n 800b6ac break; 800b68a: bf00 nop 800b68c: e00e b.n 800b6ac break; 800b68e: bf00 nop 800b690: e00c b.n 800b6ac break; 800b692: bf00 nop 800b694: e00a b.n 800b6ac break; 800b696: bf00 nop 800b698: e008 b.n 800b6ac break; 800b69a: bf00 nop 800b69c: e006 b.n 800b6ac break; 800b69e: bf00 nop 800b6a0: e004 b.n 800b6ac break; 800b6a2: bf00 nop 800b6a4: e002 b.n 800b6ac break; 800b6a6: bf00 nop 800b6a8: e000 b.n 800b6ac break; 800b6aa: bf00 nop } } 800b6ac: bf00 nop 800b6ae: bd98 pop {r3, r4, r7, pc} 800b6b0: 20000904 .word 0x20000904 800b6b4: 200003b0 .word 0x200003b0 800b6b8: 0801711c .word 0x0801711c 800b6bc: 0801713c .word 0x0801713c 0800b6c0 : .Th = 10, .Tf = 50, .Tl = 0, }; void LED_Write(){ 800b6c0: b580 push {r7, lr} 800b6c2: af00 add r7, sp, #0 if(CONN.chargingError != CONN_NO_ERROR){ 800b6c4: 4b3c ldr r3, [pc, #240] @ (800b7b8 ) 800b6c6: 7f5b ldrb r3, [r3, #29] 800b6c8: 2b00 cmp r3, #0 800b6ca: d003 beq.n 800b6d4 LED_SetColor(&color_error); 800b6cc: 483b ldr r0, [pc, #236] @ (800b7bc ) 800b6ce: f000 f933 bl 800b938 return; 800b6d2: e06f b.n 800b7b4 } if(CONN.connControl == CMD_FORCE_UNLOCK){ 800b6d4: 4b38 ldr r3, [pc, #224] @ (800b7b8 ) 800b6d6: 781b ldrb r3, [r3, #0] 800b6d8: 2b03 cmp r3, #3 800b6da: d103 bne.n 800b6e4 LED_SetColor(&color_unlock); 800b6dc: 4838 ldr r0, [pc, #224] @ (800b7c0 ) 800b6de: f000 f92b bl 800b938 return; 800b6e2: e067 b.n 800b7b4 } if(CONN.connControl == CMD_STOP){ 800b6e4: 4b34 ldr r3, [pc, #208] @ (800b7b8 ) 800b6e6: 781b ldrb r3, [r3, #0] 800b6e8: 2b01 cmp r3, #1 800b6ea: d103 bne.n 800b6f4 LED_SetColor(&color_estop); 800b6ec: 4835 ldr r0, [pc, #212] @ (800b7c4 ) 800b6ee: f000 f923 bl 800b938 return; 800b6f2: e05f b.n 800b7b4 } switch(CONN.connState){ 800b6f4: 4b30 ldr r3, [pc, #192] @ (800b7b8 ) 800b6f6: 785b ldrb r3, [r3, #1] 800b6f8: 2b0d cmp r3, #13 800b6fa: d857 bhi.n 800b7ac 800b6fc: a201 add r2, pc, #4 @ (adr r2, 800b704 ) 800b6fe: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b702: bf00 nop 800b704: 0800b73d .word 0x0800b73d 800b708: 0800b745 .word 0x0800b745 800b70c: 0800b74d .word 0x0800b74d 800b710: 0800b755 .word 0x0800b755 800b714: 0800b75d .word 0x0800b75d 800b718: 0800b765 .word 0x0800b765 800b71c: 0800b76d .word 0x0800b76d 800b720: 0800b775 .word 0x0800b775 800b724: 0800b77d .word 0x0800b77d 800b728: 0800b785 .word 0x0800b785 800b72c: 0800b78d .word 0x0800b78d 800b730: 0800b795 .word 0x0800b795 800b734: 0800b79d .word 0x0800b79d 800b738: 0800b7a5 .word 0x0800b7a5 case Unknown: LED_SetColor(&color_unknown); 800b73c: 4822 ldr r0, [pc, #136] @ (800b7c8 ) 800b73e: f000 f8fb bl 800b938 break; 800b742: e037 b.n 800b7b4 case Unplugged: LED_SetColor(&color_unplugged); 800b744: 4821 ldr r0, [pc, #132] @ (800b7cc ) 800b746: f000 f8f7 bl 800b938 break; 800b74a: e033 b.n 800b7b4 case Disabled: LED_SetColor(&color_error); 800b74c: 481b ldr r0, [pc, #108] @ (800b7bc ) 800b74e: f000 f8f3 bl 800b938 break; 800b752: e02f b.n 800b7b4 case Preparing: LED_SetColor(&color_preparing); 800b754: 481e ldr r0, [pc, #120] @ (800b7d0 ) 800b756: f000 f8ef bl 800b938 break; 800b75a: e02b b.n 800b7b4 case AuthRequired: LED_SetColor(&color_preparing); 800b75c: 481c ldr r0, [pc, #112] @ (800b7d0 ) 800b75e: f000 f8eb bl 800b938 break; 800b762: e027 b.n 800b7b4 case WaitingForEnergy: LED_SetColor(&color_charging); 800b764: 481b ldr r0, [pc, #108] @ (800b7d4 ) 800b766: f000 f8e7 bl 800b938 break; 800b76a: e023 b.n 800b7b4 case ChargingPausedEV: LED_SetColor(&color_charging); 800b76c: 4819 ldr r0, [pc, #100] @ (800b7d4 ) 800b76e: f000 f8e3 bl 800b938 break; 800b772: e01f b.n 800b7b4 case ChargingPausedEVSE: LED_SetColor(&color_charging); 800b774: 4817 ldr r0, [pc, #92] @ (800b7d4 ) 800b776: f000 f8df bl 800b938 break; 800b77a: e01b b.n 800b7b4 case Charging: LED_SetColor(&color_charging); 800b77c: 4815 ldr r0, [pc, #84] @ (800b7d4 ) 800b77e: f000 f8db bl 800b938 break; 800b782: e017 b.n 800b7b4 case AuthTimeout: LED_SetColor(&color_finished); 800b784: 4814 ldr r0, [pc, #80] @ (800b7d8 ) 800b786: f000 f8d7 bl 800b938 break; 800b78a: e013 b.n 800b7b4 case Finished: LED_SetColor(&color_finished); 800b78c: 4812 ldr r0, [pc, #72] @ (800b7d8 ) 800b78e: f000 f8d3 bl 800b938 break; 800b792: e00f b.n 800b7b4 case FinishedEVSE: LED_SetColor(&color_finished); 800b794: 4810 ldr r0, [pc, #64] @ (800b7d8 ) 800b796: f000 f8cf bl 800b938 break; 800b79a: e00b b.n 800b7b4 case FinishedEV: LED_SetColor(&color_finished); 800b79c: 480e ldr r0, [pc, #56] @ (800b7d8 ) 800b79e: f000 f8cb bl 800b938 break; 800b7a2: e007 b.n 800b7b4 case Replugging: LED_SetColor(&color_preparing); 800b7a4: 480a ldr r0, [pc, #40] @ (800b7d0 ) 800b7a6: f000 f8c7 bl 800b938 break; 800b7aa: e003 b.n 800b7b4 default: LED_SetColor(&color_unknown); 800b7ac: 4806 ldr r0, [pc, #24] @ (800b7c8 ) 800b7ae: f000 f8c3 bl 800b938 break; 800b7b2: bf00 nop } } 800b7b4: bd80 pop {r7, pc} 800b7b6: bf00 nop 800b7b8: 200003b0 .word 0x200003b0 800b7bc: 20000060 .word 0x20000060 800b7c0: 20000018 .word 0x20000018 800b7c4: 2000000c .word 0x2000000c 800b7c8: 20000024 .word 0x20000024 800b7cc: 20000030 .word 0x20000030 800b7d0: 2000003c .word 0x2000003c 800b7d4: 20000048 .word 0x20000048 800b7d8: 20000054 .word 0x20000054 0800b7dc : void interpolateColors(RGB_t* color1, RGB_t* color2, uint16_t a, uint16_t b, RGB_t *result) { 800b7dc: b480 push {r7} 800b7de: b087 sub sp, #28 800b7e0: af00 add r7, sp, #0 800b7e2: 60f8 str r0, [r7, #12] 800b7e4: 60b9 str r1, [r7, #8] 800b7e6: 4611 mov r1, r2 800b7e8: 461a mov r2, r3 800b7ea: 460b mov r3, r1 800b7ec: 80fb strh r3, [r7, #6] 800b7ee: 4613 mov r3, r2 800b7f0: 80bb strh r3, [r7, #4] // Проверяем, чтобы a не выходила за пределы диапазона if (a > b) a = b; 800b7f2: 88fa ldrh r2, [r7, #6] 800b7f4: 88bb ldrh r3, [r7, #4] 800b7f6: 429a cmp r2, r3 800b7f8: d901 bls.n 800b7fe 800b7fa: 88bb ldrh r3, [r7, #4] 800b7fc: 80fb strh r3, [r7, #6] if(b==0) b = 1; 800b7fe: 88bb ldrh r3, [r7, #4] 800b800: 2b00 cmp r3, #0 800b802: d101 bne.n 800b808 800b804: 2301 movs r3, #1 800b806: 80bb strh r3, [r7, #4] // Вычисляем коэффициент смешивания в виде целого числа uint16_t t = (a * 255) / b; // t будет от 0 до 255 800b808: 88fa ldrh r2, [r7, #6] 800b80a: 4613 mov r3, r2 800b80c: 021b lsls r3, r3, #8 800b80e: 1a9a subs r2, r3, r2 800b810: 88bb ldrh r3, [r7, #4] 800b812: fb92 f3f3 sdiv r3, r2, r3 800b816: 82fb strh r3, [r7, #22] // Линейная интерполяция с использованием целых чисел result->R = (color1->R * (255 - t) + color2->R * t) / 255; 800b818: 68fb ldr r3, [r7, #12] 800b81a: 781b ldrb r3, [r3, #0] 800b81c: 461a mov r2, r3 800b81e: 8afb ldrh r3, [r7, #22] 800b820: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b824: fb03 f202 mul.w r2, r3, r2 800b828: 68bb ldr r3, [r7, #8] 800b82a: 781b ldrb r3, [r3, #0] 800b82c: 4619 mov r1, r3 800b82e: 8afb ldrh r3, [r7, #22] 800b830: fb01 f303 mul.w r3, r1, r3 800b834: 4413 add r3, r2 800b836: 4a20 ldr r2, [pc, #128] @ (800b8b8 ) 800b838: fb82 1203 smull r1, r2, r2, r3 800b83c: 441a add r2, r3 800b83e: 11d2 asrs r2, r2, #7 800b840: 17db asrs r3, r3, #31 800b842: 1ad3 subs r3, r2, r3 800b844: b2da uxtb r2, r3 800b846: 6a3b ldr r3, [r7, #32] 800b848: 701a strb r2, [r3, #0] result->G = (color1->G * (255 - t) + color2->G * t) / 255; 800b84a: 68fb ldr r3, [r7, #12] 800b84c: 785b ldrb r3, [r3, #1] 800b84e: 461a mov r2, r3 800b850: 8afb ldrh r3, [r7, #22] 800b852: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b856: fb03 f202 mul.w r2, r3, r2 800b85a: 68bb ldr r3, [r7, #8] 800b85c: 785b ldrb r3, [r3, #1] 800b85e: 4619 mov r1, r3 800b860: 8afb ldrh r3, [r7, #22] 800b862: fb01 f303 mul.w r3, r1, r3 800b866: 4413 add r3, r2 800b868: 4a13 ldr r2, [pc, #76] @ (800b8b8 ) 800b86a: fb82 1203 smull r1, r2, r2, r3 800b86e: 441a add r2, r3 800b870: 11d2 asrs r2, r2, #7 800b872: 17db asrs r3, r3, #31 800b874: 1ad3 subs r3, r2, r3 800b876: b2da uxtb r2, r3 800b878: 6a3b ldr r3, [r7, #32] 800b87a: 705a strb r2, [r3, #1] result->B = (color1->B * (255 - t) + color2->B * t) / 255; 800b87c: 68fb ldr r3, [r7, #12] 800b87e: 789b ldrb r3, [r3, #2] 800b880: 461a mov r2, r3 800b882: 8afb ldrh r3, [r7, #22] 800b884: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b888: fb03 f202 mul.w r2, r3, r2 800b88c: 68bb ldr r3, [r7, #8] 800b88e: 789b ldrb r3, [r3, #2] 800b890: 4619 mov r1, r3 800b892: 8afb ldrh r3, [r7, #22] 800b894: fb01 f303 mul.w r3, r1, r3 800b898: 4413 add r3, r2 800b89a: 4a07 ldr r2, [pc, #28] @ (800b8b8 ) 800b89c: fb82 1203 smull r1, r2, r2, r3 800b8a0: 441a add r2, r3 800b8a2: 11d2 asrs r2, r2, #7 800b8a4: 17db asrs r3, r3, #31 800b8a6: 1ad3 subs r3, r2, r3 800b8a8: b2da uxtb r2, r3 800b8aa: 6a3b ldr r3, [r7, #32] 800b8ac: 709a strb r2, [r3, #2] } 800b8ae: bf00 nop 800b8b0: 371c adds r7, #28 800b8b2: 46bd mov sp, r7 800b8b4: bc80 pop {r7} 800b8b6: 4770 bx lr 800b8b8: 80808081 .word 0x80808081 0800b8bc : void RGB_SetColor(RGB_t *color){ 800b8bc: b480 push {r7} 800b8be: b083 sub sp, #12 800b8c0: af00 add r7, sp, #0 800b8c2: 6078 str r0, [r7, #4] htim4.Instance->CCR2 = color->R * 100 / 255; 800b8c4: 687b ldr r3, [r7, #4] 800b8c6: 781b ldrb r3, [r3, #0] 800b8c8: 461a mov r2, r3 800b8ca: 2364 movs r3, #100 @ 0x64 800b8cc: fb02 f303 mul.w r3, r2, r3 800b8d0: 4a17 ldr r2, [pc, #92] @ (800b930 ) 800b8d2: fb82 1203 smull r1, r2, r2, r3 800b8d6: 441a add r2, r3 800b8d8: 11d2 asrs r2, r2, #7 800b8da: 17db asrs r3, r3, #31 800b8dc: 1ad2 subs r2, r2, r3 800b8de: 4b15 ldr r3, [pc, #84] @ (800b934 ) 800b8e0: 681b ldr r3, [r3, #0] 800b8e2: 639a str r2, [r3, #56] @ 0x38 htim4.Instance->CCR3 = color->G * 100 / 255; 800b8e4: 687b ldr r3, [r7, #4] 800b8e6: 785b ldrb r3, [r3, #1] 800b8e8: 461a mov r2, r3 800b8ea: 2364 movs r3, #100 @ 0x64 800b8ec: fb02 f303 mul.w r3, r2, r3 800b8f0: 4a0f ldr r2, [pc, #60] @ (800b930 ) 800b8f2: fb82 1203 smull r1, r2, r2, r3 800b8f6: 441a add r2, r3 800b8f8: 11d2 asrs r2, r2, #7 800b8fa: 17db asrs r3, r3, #31 800b8fc: 1ad2 subs r2, r2, r3 800b8fe: 4b0d ldr r3, [pc, #52] @ (800b934 ) 800b900: 681b ldr r3, [r3, #0] 800b902: 63da str r2, [r3, #60] @ 0x3c htim4.Instance->CCR4 = color->B * 100 / 255; 800b904: 687b ldr r3, [r7, #4] 800b906: 789b ldrb r3, [r3, #2] 800b908: 461a mov r2, r3 800b90a: 2364 movs r3, #100 @ 0x64 800b90c: fb02 f303 mul.w r3, r2, r3 800b910: 4a07 ldr r2, [pc, #28] @ (800b930 ) 800b912: fb82 1203 smull r1, r2, r2, r3 800b916: 441a add r2, r3 800b918: 11d2 asrs r2, r2, #7 800b91a: 17db asrs r3, r3, #31 800b91c: 1ad2 subs r2, r2, r3 800b91e: 4b05 ldr r3, [pc, #20] @ (800b934 ) 800b920: 681b ldr r3, [r3, #0] 800b922: 641a str r2, [r3, #64] @ 0x40 } 800b924: bf00 nop 800b926: 370c adds r7, #12 800b928: 46bd mov sp, r7 800b92a: bc80 pop {r7} 800b92c: 4770 bx lr 800b92e: bf00 nop 800b930: 80808081 .word 0x80808081 800b934: 20001210 .word 0x20001210 0800b938 : void LED_SetColor(RGB_Cycle_t *color){ 800b938: b480 push {r7} 800b93a: b083 sub sp, #12 800b93c: af00 add r7, sp, #0 800b93e: 6078 str r0, [r7, #4] memcpy(&LED_Cycle, color, sizeof(RGB_Cycle_t)); 800b940: 4b05 ldr r3, [pc, #20] @ (800b958 ) 800b942: 687a ldr r2, [r7, #4] 800b944: 6810 ldr r0, [r2, #0] 800b946: 6851 ldr r1, [r2, #4] 800b948: c303 stmia r3!, {r0, r1} 800b94a: 8912 ldrh r2, [r2, #8] 800b94c: 801a strh r2, [r3, #0] } 800b94e: bf00 nop 800b950: 370c adds r7, #12 800b952: 46bd mov sp, r7 800b954: bc80 pop {r7} 800b956: 4770 bx lr 800b958: 20000964 .word 0x20000964 0800b95c : void LED_Init(){ 800b95c: b580 push {r7, lr} 800b95e: b082 sub sp, #8 800b960: af00 add r7, sp, #0 RGB_t color = {.R=0, .G=0, .B=0}; 800b962: 2300 movs r3, #0 800b964: 713b strb r3, [r7, #4] 800b966: 2300 movs r3, #0 800b968: 717b strb r3, [r7, #5] 800b96a: 2300 movs r3, #0 800b96c: 71bb strb r3, [r7, #6] HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_2); 800b96e: 2104 movs r1, #4 800b970: 4809 ldr r0, [pc, #36] @ (800b998 ) 800b972: f006 fbaf bl 80120d4 HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); 800b976: 2108 movs r1, #8 800b978: 4807 ldr r0, [pc, #28] @ (800b998 ) 800b97a: f006 fbab bl 80120d4 HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4); 800b97e: 210c movs r1, #12 800b980: 4805 ldr r0, [pc, #20] @ (800b998 ) 800b982: f006 fba7 bl 80120d4 RGB_SetColor(&color); 800b986: 1d3b adds r3, r7, #4 800b988: 4618 mov r0, r3 800b98a: f7ff ff97 bl 800b8bc } 800b98e: bf00 nop 800b990: 3708 adds r7, #8 800b992: 46bd mov sp, r7 800b994: bd80 pop {r7, pc} 800b996: bf00 nop 800b998: 20001210 .word 0x20001210 0800b99c : void LED_Task(){ 800b99c: b580 push {r7, lr} 800b99e: b082 sub sp, #8 800b9a0: af02 add r7, sp, #8 static uint32_t led_tick; if((HAL_GetTick() - led_tick) > 20){ 800b9a2: f002 fcc9 bl 800e338 800b9a6: 4602 mov r2, r0 800b9a8: 4b46 ldr r3, [pc, #280] @ (800bac4 ) 800b9aa: 681b ldr r3, [r3, #0] 800b9ac: 1ad3 subs r3, r2, r3 800b9ae: 2b14 cmp r3, #20 800b9b0: f240 8085 bls.w 800babe led_tick = HAL_GetTick(); 800b9b4: f002 fcc0 bl 800e338 800b9b8: 4603 mov r3, r0 800b9ba: 4a42 ldr r2, [pc, #264] @ (800bac4 ) 800b9bc: 6013 str r3, [r2, #0] LED_State.tick++; 800b9be: 4b42 ldr r3, [pc, #264] @ (800bac8 ) 800b9c0: 885b ldrh r3, [r3, #2] 800b9c2: 3301 adds r3, #1 800b9c4: b29a uxth r2, r3 800b9c6: 4b40 ldr r3, [pc, #256] @ (800bac8 ) 800b9c8: 805a strh r2, [r3, #2] switch(LED_State.state){ 800b9ca: 4b3f ldr r3, [pc, #252] @ (800bac8 ) 800b9cc: 781b ldrb r3, [r3, #0] 800b9ce: 2b03 cmp r3, #3 800b9d0: d867 bhi.n 800baa2 800b9d2: a201 add r2, pc, #4 @ (adr r2, 800b9d8 ) 800b9d4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b9d8: 0800b9e9 .word 0x0800b9e9 800b9dc: 0800ba1b .word 0x0800ba1b 800b9e0: 0800ba47 .word 0x0800ba47 800b9e4: 0800ba79 .word 0x0800ba79 case LED_RISING: interpolateColors(&LED_Cycle.Color2, &LED_Cycle.Color1, LED_State.tick, LED_Cycle.Tr, &LED_State.color); 800b9e8: 4b37 ldr r3, [pc, #220] @ (800bac8 ) 800b9ea: 885a ldrh r2, [r3, #2] 800b9ec: 4b37 ldr r3, [pc, #220] @ (800bacc ) 800b9ee: 78db ldrb r3, [r3, #3] 800b9f0: 4619 mov r1, r3 800b9f2: 4b37 ldr r3, [pc, #220] @ (800bad0 ) 800b9f4: 9300 str r3, [sp, #0] 800b9f6: 460b mov r3, r1 800b9f8: 4934 ldr r1, [pc, #208] @ (800bacc ) 800b9fa: 4836 ldr r0, [pc, #216] @ (800bad4 ) 800b9fc: f7ff feee bl 800b7dc if(LED_State.tick>LED_Cycle.Tr){ 800ba00: 4b31 ldr r3, [pc, #196] @ (800bac8 ) 800ba02: 885b ldrh r3, [r3, #2] 800ba04: 4a31 ldr r2, [pc, #196] @ (800bacc ) 800ba06: 78d2 ldrb r2, [r2, #3] 800ba08: 4293 cmp r3, r2 800ba0a: d94e bls.n 800baaa LED_State.state = LED_HIGH; 800ba0c: 4b2e ldr r3, [pc, #184] @ (800bac8 ) 800ba0e: 2201 movs r2, #1 800ba10: 701a strb r2, [r3, #0] LED_State.tick = 0; 800ba12: 4b2d ldr r3, [pc, #180] @ (800bac8 ) 800ba14: 2200 movs r2, #0 800ba16: 805a strh r2, [r3, #2] } break; 800ba18: e047 b.n 800baaa case LED_HIGH: memcpy(&LED_State.color, &LED_Cycle.Color1, sizeof(RGB_t)); 800ba1a: 4b2b ldr r3, [pc, #172] @ (800bac8 ) 800ba1c: 4a2b ldr r2, [pc, #172] @ (800bacc ) 800ba1e: 3304 adds r3, #4 800ba20: 6812 ldr r2, [r2, #0] 800ba22: 4611 mov r1, r2 800ba24: 8019 strh r1, [r3, #0] 800ba26: 3302 adds r3, #2 800ba28: 0c12 lsrs r2, r2, #16 800ba2a: 701a strb r2, [r3, #0] if(LED_State.tick>LED_Cycle.Th){ 800ba2c: 4b26 ldr r3, [pc, #152] @ (800bac8 ) 800ba2e: 885b ldrh r3, [r3, #2] 800ba30: 4a26 ldr r2, [pc, #152] @ (800bacc ) 800ba32: 7912 ldrb r2, [r2, #4] 800ba34: 4293 cmp r3, r2 800ba36: d93a bls.n 800baae LED_State.state = LED_FALLING; 800ba38: 4b23 ldr r3, [pc, #140] @ (800bac8 ) 800ba3a: 2202 movs r2, #2 800ba3c: 701a strb r2, [r3, #0] LED_State.tick = 0; 800ba3e: 4b22 ldr r3, [pc, #136] @ (800bac8 ) 800ba40: 2200 movs r2, #0 800ba42: 805a strh r2, [r3, #2] } break; 800ba44: e033 b.n 800baae case LED_FALLING: interpolateColors(&LED_Cycle.Color1, &LED_Cycle.Color2, LED_State.tick, LED_Cycle.Tf, &LED_State.color); 800ba46: 4b20 ldr r3, [pc, #128] @ (800bac8 ) 800ba48: 885a ldrh r2, [r3, #2] 800ba4a: 4b20 ldr r3, [pc, #128] @ (800bacc ) 800ba4c: 795b ldrb r3, [r3, #5] 800ba4e: 4619 mov r1, r3 800ba50: 4b1f ldr r3, [pc, #124] @ (800bad0 ) 800ba52: 9300 str r3, [sp, #0] 800ba54: 460b mov r3, r1 800ba56: 491f ldr r1, [pc, #124] @ (800bad4 ) 800ba58: 481c ldr r0, [pc, #112] @ (800bacc ) 800ba5a: f7ff febf bl 800b7dc if(LED_State.tick>LED_Cycle.Tf){ 800ba5e: 4b1a ldr r3, [pc, #104] @ (800bac8 ) 800ba60: 885b ldrh r3, [r3, #2] 800ba62: 4a1a ldr r2, [pc, #104] @ (800bacc ) 800ba64: 7952 ldrb r2, [r2, #5] 800ba66: 4293 cmp r3, r2 800ba68: d923 bls.n 800bab2 LED_State.state = LED_LOW; 800ba6a: 4b17 ldr r3, [pc, #92] @ (800bac8 ) 800ba6c: 2203 movs r2, #3 800ba6e: 701a strb r2, [r3, #0] LED_State.tick = 0; 800ba70: 4b15 ldr r3, [pc, #84] @ (800bac8 ) 800ba72: 2200 movs r2, #0 800ba74: 805a strh r2, [r3, #2] } break; 800ba76: e01c b.n 800bab2 case LED_LOW: memcpy(&LED_State.color, &LED_Cycle.Color2, sizeof(RGB_t)); 800ba78: 4b13 ldr r3, [pc, #76] @ (800bac8 ) 800ba7a: 4a14 ldr r2, [pc, #80] @ (800bacc ) 800ba7c: 3304 adds r3, #4 800ba7e: 3207 adds r2, #7 800ba80: 8811 ldrh r1, [r2, #0] 800ba82: 7892 ldrb r2, [r2, #2] 800ba84: 8019 strh r1, [r3, #0] 800ba86: 709a strb r2, [r3, #2] if(LED_State.tick>LED_Cycle.Tl){ 800ba88: 4b0f ldr r3, [pc, #60] @ (800bac8 ) 800ba8a: 885b ldrh r3, [r3, #2] 800ba8c: 4a0f ldr r2, [pc, #60] @ (800bacc ) 800ba8e: 7992 ldrb r2, [r2, #6] 800ba90: 4293 cmp r3, r2 800ba92: d910 bls.n 800bab6 LED_State.state = LED_RISING; 800ba94: 4b0c ldr r3, [pc, #48] @ (800bac8 ) 800ba96: 2200 movs r2, #0 800ba98: 701a strb r2, [r3, #0] LED_State.tick = 0; 800ba9a: 4b0b ldr r3, [pc, #44] @ (800bac8 ) 800ba9c: 2200 movs r2, #0 800ba9e: 805a strh r2, [r3, #2] } break; 800baa0: e009 b.n 800bab6 default: LED_State.state = LED_RISING; 800baa2: 4b09 ldr r3, [pc, #36] @ (800bac8 ) 800baa4: 2200 movs r2, #0 800baa6: 701a strb r2, [r3, #0] 800baa8: e006 b.n 800bab8 break; 800baaa: bf00 nop 800baac: e004 b.n 800bab8 break; 800baae: bf00 nop 800bab0: e002 b.n 800bab8 break; 800bab2: bf00 nop 800bab4: e000 b.n 800bab8 break; 800bab6: bf00 nop } RGB_SetColor(&LED_State.color); 800bab8: 4805 ldr r0, [pc, #20] @ (800bad0 ) 800baba: f7ff feff bl 800b8bc } } 800babe: bf00 nop 800bac0: 46bd mov sp, r7 800bac2: bd80 pop {r7, pc} 800bac4: 20000970 .word 0x20000970 800bac8: 2000095c .word 0x2000095c 800bacc: 20000964 .word 0x20000964 800bad0: 20000960 .word 0x20000960 800bad4: 2000096b .word 0x2000096b 0800bad8 : RTC_HandleTypeDef hrtc; /* RTC init function */ void MX_RTC_Init(void) { 800bad8: b580 push {r7, lr} 800bada: af00 add r7, sp, #0 /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 800badc: 4b0a ldr r3, [pc, #40] @ (800bb08 ) 800bade: 4a0b ldr r2, [pc, #44] @ (800bb0c ) 800bae0: 601a str r2, [r3, #0] hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; 800bae2: 4b09 ldr r3, [pc, #36] @ (800bb08 ) 800bae4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800bae8: 605a str r2, [r3, #4] hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; 800baea: 4b07 ldr r3, [pc, #28] @ (800bb08 ) 800baec: f44f 7280 mov.w r2, #256 @ 0x100 800baf0: 609a str r2, [r3, #8] if (HAL_RTC_Init(&hrtc) != HAL_OK) 800baf2: 4805 ldr r0, [pc, #20] @ (800bb08 ) 800baf4: f006 f83c bl 8011b70 800baf8: 4603 mov r3, r0 800bafa: 2b00 cmp r3, #0 800bafc: d001 beq.n 800bb02 { Error_Handler(); 800bafe: f7ff f8c1 bl 800ac84 } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 800bb02: bf00 nop 800bb04: bd80 pop {r7, pc} 800bb06: bf00 nop 800bb08: 20000974 .word 0x20000974 800bb0c: 40002800 .word 0x40002800 0800bb10 : void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) { 800bb10: b580 push {r7, lr} 800bb12: b084 sub sp, #16 800bb14: af00 add r7, sp, #0 800bb16: 6078 str r0, [r7, #4] if(rtcHandle->Instance==RTC) 800bb18: 687b ldr r3, [r7, #4] 800bb1a: 681b ldr r3, [r3, #0] 800bb1c: 4a0b ldr r2, [pc, #44] @ (800bb4c ) 800bb1e: 4293 cmp r3, r2 800bb20: d110 bne.n 800bb44 { /* USER CODE BEGIN RTC_MspInit 0 */ /* USER CODE END RTC_MspInit 0 */ HAL_PWR_EnableBkUpAccess(); 800bb22: f004 ffb9 bl 8010a98 /* Enable BKP CLK enable for backup registers */ __HAL_RCC_BKP_CLK_ENABLE(); 800bb26: 4b0a ldr r3, [pc, #40] @ (800bb50 ) 800bb28: 69db ldr r3, [r3, #28] 800bb2a: 4a09 ldr r2, [pc, #36] @ (800bb50 ) 800bb2c: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800bb30: 61d3 str r3, [r2, #28] 800bb32: 4b07 ldr r3, [pc, #28] @ (800bb50 ) 800bb34: 69db ldr r3, [r3, #28] 800bb36: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800bb3a: 60fb str r3, [r7, #12] 800bb3c: 68fb ldr r3, [r7, #12] /* RTC clock enable */ __HAL_RCC_RTC_ENABLE(); 800bb3e: 4b05 ldr r3, [pc, #20] @ (800bb54 ) 800bb40: 2201 movs r2, #1 800bb42: 601a str r2, [r3, #0] /* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE END RTC_MspInit 1 */ } } 800bb44: bf00 nop 800bb46: 3710 adds r7, #16 800bb48: 46bd mov sp, r7 800bb4a: bd80 pop {r7, pc} 800bb4c: 40002800 .word 0x40002800 800bb50: 40021000 .word 0x40021000 800bb54: 4242043c .word 0x4242043c 0800bb58 : ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len); static void CCS_UART3_Watchdog(void); static void CCS_LogUart3Error(const char *tag); ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800bb58: 4602 mov r2, r0 if (err == HAL_UART_ERROR_NONE) { 800bb5a: b359 cbz r1, 800bbb4 ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800bb5c: b570 push {r4, r5, r6, lr} 800bb5e: 460c mov r4, r1 log_printf(LOG_ERR, "UART%u HAL error decode: NONE\n", uart_num); return; } log_printf(LOG_ERR, "UART%u HAL error decode: %s%s%s%s%s%s raw=0x%08lx\n", 800bb60: 07cb lsls r3, r1, #31 800bb62: bf58 it pl 800bb64: 4915 ldrpl r1, [pc, #84] @ (800bbbc ) 800bb66: 4d15 ldr r5, [pc, #84] @ (800bbbc ) 800bb68: bf48 it mi 800bb6a: 4914 ldrmi r1, [pc, #80] @ (800bbbc ) ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800bb6c: b086 sub sp, #24 log_printf(LOG_ERR, "UART%u HAL error decode: %s%s%s%s%s%s raw=0x%08lx\n", 800bb6e: bf54 ite pl 800bb70: 460b movpl r3, r1 800bb72: 4b13 ldrmi r3, [pc, #76] @ (800bbc0 ) 800bb74: f014 0f02 tst.w r4, #2 800bb78: 9104 str r1, [sp, #16] 800bb7a: 4912 ldr r1, [pc, #72] @ (800bbc4 ) 800bb7c: bf08 it eq 800bb7e: 4629 moveq r1, r5 800bb80: f014 0f04 tst.w r4, #4 800bb84: 4810 ldr r0, [pc, #64] @ (800bbc8 ) 800bb86: bf08 it eq 800bb88: 4628 moveq r0, r5 800bb8a: f014 0f08 tst.w r4, #8 800bb8e: 9001 str r0, [sp, #4] 800bb90: 480e ldr r0, [pc, #56] @ (800bbcc ) 800bb92: 4e0f ldr r6, [pc, #60] @ (800bbd0 ) 800bb94: bf08 it eq 800bb96: 462e moveq r6, r5 800bb98: f014 0f10 tst.w r4, #16 800bb9c: bf18 it ne 800bb9e: 4605 movne r5, r0 800bba0: 9100 str r1, [sp, #0] 800bba2: e9cd 6502 strd r6, r5, [sp, #8] 800bba6: 490b ldr r1, [pc, #44] @ (800bbd4 ) 800bba8: 9405 str r4, [sp, #20] 800bbaa: 2004 movs r0, #4 800bbac: f7fe fcd2 bl 800a554 (err & HAL_UART_ERROR_INVALID_CALLBACK) ? "INV_CB " : "", #else "", #endif (unsigned long)err); } 800bbb0: b006 add sp, #24 800bbb2: bd70 pop {r4, r5, r6, pc} log_printf(LOG_ERR, "UART%u HAL error decode: NONE\n", uart_num); 800bbb4: 2004 movs r0, #4 800bbb6: 4908 ldr r1, [pc, #32] @ (800bbd8 ) 800bbb8: f7fe bccc b.w 800a554 800bbbc: 08017548 .word 0x08017548 800bbc0: 08017150 .word 0x08017150 800bbc4: 08017154 .word 0x08017154 800bbc8: 08017158 .word 0x08017158 800bbcc: 08017164 .word 0x08017164 800bbd0: 0801715c .word 0x0801715c 800bbd4: 0801718c .word 0x0801718c 800bbd8: 0801716c .word 0x0801716c 0800bbdc : ISR_FAST static void uart3_arm_rx_or_log(const char *where) { 800bbdc: b530 push {r4, r5, lr} HAL_StatusTypeDef st = HAL_UARTEx_ReceiveToIdle_DMA(&huart3, rx_buffer, sizeof(rx_buffer)); 800bbde: f44f 7280 mov.w r2, #256 @ 0x100 ISR_FAST static void uart3_arm_rx_or_log(const char *where) { 800bbe2: 4605 mov r5, r0 800bbe4: b083 sub sp, #12 HAL_StatusTypeDef st = HAL_UARTEx_ReceiveToIdle_DMA(&huart3, rx_buffer, sizeof(rx_buffer)); 800bbe6: 4911 ldr r1, [pc, #68] @ (800bc2c ) 800bbe8: 4811 ldr r0, [pc, #68] @ (800bc30 ) 800bbea: f007 fa6e bl 80130ca if (st == HAL_OK) { 800bbee: b908 cbnz r0, 800bbf4 uart3_log_hal_error(3u, err_after); CCS_LogUart3Error("UART3 RX arm failed details"); if (err_after != HAL_UART_ERROR_NONE) { (void)HAL_UART_AbortReceive(&huart3); } } 800bbf0: b003 add sp, #12 800bbf2: bd30 pop {r4, r5, pc} uint32_t err_after = HAL_UART_GetError(&huart3); 800bbf4: 4604 mov r4, r0 800bbf6: 480e ldr r0, [pc, #56] @ (800bc30 ) 800bbf8: f007 fe79 bl 80138ee 800bbfc: 4602 mov r2, r0 log_printf(LOG_ERR, 800bbfe: 4623 mov r3, r4 uint32_t err_after = HAL_UART_GetError(&huart3); 800bc00: 4614 mov r4, r2 log_printf(LOG_ERR, 800bc02: 490c ldr r1, [pc, #48] @ (800bc34 ) 800bc04: 462a mov r2, r5 800bc06: 2004 movs r0, #4 800bc08: 9400 str r4, [sp, #0] 800bc0a: f7fe fca3 bl 800a554 uart3_log_hal_error(3u, err_after); 800bc0e: 2003 movs r0, #3 800bc10: 4621 mov r1, r4 800bc12: f7ff ffa1 bl 800bb58 CCS_LogUart3Error("UART3 RX arm failed details"); 800bc16: 4808 ldr r0, [pc, #32] @ (800bc38 ) 800bc18: f000 fedc bl 800c9d4 if (err_after != HAL_UART_ERROR_NONE) { 800bc1c: 2c00 cmp r4, #0 800bc1e: d0e7 beq.n 800bbf0 (void)HAL_UART_AbortReceive(&huart3); 800bc20: 4803 ldr r0, [pc, #12] @ (800bc30 ) } 800bc22: b003 add sp, #12 800bc24: e8bd 4030 ldmia.w sp!, {r4, r5, lr} (void)HAL_UART_AbortReceive(&huart3); 800bc28: f007 bb10 b.w 801324c 800bc2c: 200009ac .word 0x200009ac 800bc30: 20001330 .word 0x20001330 800bc34: 080171c0 .word 0x080171c0 800bc38: 080171fc .word 0x080171fc 0800bc3c : ISR_FAST void CCS_RxEventCallback(UART_HandleTypeDef *huart, uint16_t size) { 800bc3c: b538 push {r3, r4, r5, lr} if (huart != &huart3) { 800bc3e: 4b1a ldr r3, [pc, #104] @ (800bca8 ) ISR_FAST void CCS_RxEventCallback(UART_HandleTypeDef *huart, uint16_t size) { 800bc40: 460c mov r4, r1 if (huart != &huart3) { 800bc42: 4283 cmp r3, r0 800bc44: d113 bne.n 800bc6e log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", (unsigned)size); return; } if (size == 0u) { 800bc46: b329 cbz r1, 800bc94 log_printf(LOG_WARN, "UART3 RX drop: RxEvent size=0 (idle, no payload)\n"); uart3_arm_rx_or_log("RxEventCallback"); return; } if (size > sizeof(rx_buffer)) { 800bc48: f5b1 7f80 cmp.w r1, #256 @ 0x100 800bc4c: d816 bhi.n 800bc7c log_printf(LOG_ERR, "UART3 RX drop: size=%u > rx_buffer %u (overflow, not parsed)\n", (unsigned)size, (unsigned)sizeof(rx_buffer)); uart3_arm_rx_or_log("RxEventCallback"); return; } uart3_last_packet_tick = HAL_GetTick(); 800bc4e: f002 fb73 bl 800e338 800bc52: 4603 mov r3, r0 800bc54: 4d15 ldr r5, [pc, #84] @ (800bcac ) uart3_last_reinit_tick = uart3_last_packet_tick; 800bc56: 4a16 ldr r2, [pc, #88] @ (800bcb0 ) process_received_packet(rx_buffer, size); 800bc58: 4621 mov r1, r4 800bc5a: 4816 ldr r0, [pc, #88] @ (800bcb4 ) uart3_last_packet_tick = HAL_GetTick(); 800bc5c: 602b str r3, [r5, #0] uart3_last_reinit_tick = uart3_last_packet_tick; 800bc5e: 6013 str r3, [r2, #0] process_received_packet(rx_buffer, size); 800bc60: f000 fe10 bl 800c884 uart3_arm_rx_or_log("RxEventCallback"); } 800bc64: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800bc68: 4813 ldr r0, [pc, #76] @ (800bcb8 ) 800bc6a: f7ff bfb7 b.w 800bbdc log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", 800bc6e: 460a mov r2, r1 } 800bc70: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", 800bc74: 2005 movs r0, #5 800bc76: 4911 ldr r1, [pc, #68] @ (800bcbc ) 800bc78: f7fe bc6c b.w 800a554 log_printf(LOG_ERR, "UART3 RX drop: size=%u > rx_buffer %u (overflow, not parsed)\n", 800bc7c: f44f 7380 mov.w r3, #256 @ 0x100 800bc80: 460a mov r2, r1 800bc82: 2004 movs r0, #4 800bc84: 490e ldr r1, [pc, #56] @ (800bcc0 ) 800bc86: f7fe fc65 bl 800a554 } 800bc8a: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800bc8e: 480a ldr r0, [pc, #40] @ (800bcb8 ) 800bc90: f7ff bfa4 b.w 800bbdc log_printf(LOG_WARN, "UART3 RX drop: RxEvent size=0 (idle, no payload)\n"); 800bc94: 2005 movs r0, #5 800bc96: 490b ldr r1, [pc, #44] @ (800bcc4 ) 800bc98: f7fe fc5c bl 800a554 } 800bc9c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800bca0: 4805 ldr r0, [pc, #20] @ (800bcb8 ) 800bca2: f7ff bf9b b.w 800bbdc 800bca6: bf00 nop 800bca8: 20001330 .word 0x20001330 800bcac: 20000cbc .word 0x20000cbc 800bcb0: 20000cc0 .word 0x20000cc0 800bcb4: 200009ac .word 0x200009ac 800bcb8: 08017288 .word 0x08017288 800bcbc: 08017218 .word 0x08017218 800bcc0: 08017298 .word 0x08017298 800bcc4: 08017254 .word 0x08017254 0800bcc8 : ISR_FAST void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 800bcc8: b5f8 push {r3, r4, r5, r6, r7, lr} 800bcca: 4604 mov r4, r0 uint32_t error = HAL_UART_GetError(huart); 800bccc: f007 fe0f bl 80138ee uint8_t uart_num = 800bcd0: 4b29 ldr r3, [pc, #164] @ (800bd78 ) uint32_t error = HAL_UART_GetError(huart); 800bcd2: 4605 mov r5, r0 uint8_t uart_num = 800bcd4: 429c cmp r4, r3 800bcd6: d032 beq.n 800bd3e 800bcd8: 4e28 ldr r6, [pc, #160] @ (800bd7c ) 800bcda: 42b4 cmp r4, r6 800bcdc: d017 beq.n 800bd0e 800bcde: 4b28 ldr r3, [pc, #160] @ (800bd80 ) 800bce0: 429c cmp r4, r3 800bce2: d045 beq.n 800bd70 (huart == &huart2) ? 2 : (huart == &huart3) ? 3 : (huart == &huart5) ? 5 : 0; log_printf(LOG_ERR, 800bce4: 4603 mov r3, r0 800bce6: 2200 movs r2, #0 800bce8: 4926 ldr r1, [pc, #152] @ (800bd84 ) 800bcea: 2004 movs r0, #4 800bcec: f7fe fc32 bl 800a554 "UART%u HAL error (ISR): raw=0x%08lx — RX may be corrupted until re-arm\n", uart_num, (unsigned long)error); uart3_log_hal_error(uart_num, error); 800bcf0: 4629 mov r1, r5 800bcf2: 2000 movs r0, #0 800bcf4: f7ff ff30 bl 800bb58 (void)HAL_UART_AbortReceive(huart); 800bcf8: 4620 mov r0, r4 800bcfa: f007 faa7 bl 801324c (void)HAL_UART_AbortTransmit(huart); 800bcfe: 4620 mov r0, r4 800bd00: f007 fa3c bl 801317c if (huart == &huart3) { uart3_tx_busy = 0; uart3_arm_rx_or_log("ErrorCallback"); } else { SC_RecoverUartDma(huart); 800bd04: 4620 mov r0, r4 } } 800bd06: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} SC_RecoverUartDma(huart); 800bd0a: f001 b91f b.w 800cf4c log_printf(LOG_ERR, 800bd0e: 4603 mov r3, r0 800bd10: 2203 movs r2, #3 800bd12: 491c ldr r1, [pc, #112] @ (800bd84 ) 800bd14: 2004 movs r0, #4 800bd16: f7fe fc1d bl 800a554 uart3_log_hal_error(uart_num, error); 800bd1a: 4629 mov r1, r5 800bd1c: 2003 movs r0, #3 800bd1e: f7ff ff1b bl 800bb58 (void)HAL_UART_AbortReceive(huart); 800bd22: 4620 mov r0, r4 800bd24: f007 fa92 bl 801324c (void)HAL_UART_AbortTransmit(huart); 800bd28: 4620 mov r0, r4 800bd2a: f007 fa27 bl 801317c uart3_tx_busy = 0; 800bd2e: 2200 movs r2, #0 800bd30: 4b15 ldr r3, [pc, #84] @ (800bd88 ) uart3_arm_rx_or_log("ErrorCallback"); 800bd32: 4816 ldr r0, [pc, #88] @ (800bd8c ) uart3_tx_busy = 0; 800bd34: 701a strb r2, [r3, #0] } 800bd36: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} uart3_arm_rx_or_log("ErrorCallback"); 800bd3a: f7ff bf4f b.w 800bbdc 800bd3e: 2202 movs r2, #2 uint8_t uart_num = 800bd40: 4617 mov r7, r2 800bd42: 4e0e ldr r6, [pc, #56] @ (800bd7c ) log_printf(LOG_ERR, 800bd44: 462b mov r3, r5 800bd46: 490f ldr r1, [pc, #60] @ (800bd84 ) 800bd48: 2004 movs r0, #4 800bd4a: f7fe fc03 bl 800a554 uart3_log_hal_error(uart_num, error); 800bd4e: 4629 mov r1, r5 800bd50: 4638 mov r0, r7 800bd52: f7ff ff01 bl 800bb58 (void)HAL_UART_AbortReceive(huart); 800bd56: 4620 mov r0, r4 800bd58: f007 fa78 bl 801324c (void)HAL_UART_AbortTransmit(huart); 800bd5c: 4620 mov r0, r4 800bd5e: f007 fa0d bl 801317c if (huart == &huart3) { 800bd62: 42b4 cmp r4, r6 800bd64: d0e3 beq.n 800bd2e SC_RecoverUartDma(huart); 800bd66: 4620 mov r0, r4 } 800bd68: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} SC_RecoverUartDma(huart); 800bd6c: f001 b8ee b.w 800cf4c 800bd70: 2205 movs r2, #5 uint8_t uart_num = 800bd72: 4617 mov r7, r2 800bd74: e7e6 b.n 800bd44 800bd76: bf00 nop 800bd78: 200012e8 .word 0x200012e8 800bd7c: 20001330 .word 0x20001330 800bd80: 20001258 .word 0x20001258 800bd84: 080172d8 .word 0x080172d8 800bd88: 20000cae .word 0x20000cae 800bd8c: 08017324 .word 0x08017324 0800bd90 : void CCS_TxCpltCallback(UART_HandleTypeDef *huart) { 800bd90: b580 push {r7, lr} 800bd92: b082 sub sp, #8 800bd94: af00 add r7, sp, #0 800bd96: 6078 str r0, [r7, #4] if (huart != &huart3) { 800bd98: 687b ldr r3, [r7, #4] 800bd9a: 4a16 ldr r2, [pc, #88] @ (800bdf4 ) 800bd9c: 4293 cmp r3, r2 800bd9e: d124 bne.n 800bdea return; } uart3_tx_busy = 0; 800bda0: 4b15 ldr r3, [pc, #84] @ (800bdf8 ) 800bda2: 2200 movs r2, #0 800bda4: 701a strb r2, [r3, #0] if (tx_pending_len > 0) { 800bda6: 4b15 ldr r3, [pc, #84] @ (800bdfc ) 800bda8: 881b ldrh r3, [r3, #0] 800bdaa: 2b00 cmp r3, #0 800bdac: d01e beq.n 800bdec memcpy(tx_buffer, tx_pending_buffer, tx_pending_len); 800bdae: 4b13 ldr r3, [pc, #76] @ (800bdfc ) 800bdb0: 881b ldrh r3, [r3, #0] 800bdb2: 461a mov r2, r3 800bdb4: 4912 ldr r1, [pc, #72] @ (800be00 ) 800bdb6: 4813 ldr r0, [pc, #76] @ (800be04 ) 800bdb8: f008 ffc0 bl 8014d3c uart3_tx_busy = 1; 800bdbc: 4b0e ldr r3, [pc, #56] @ (800bdf8 ) 800bdbe: 2201 movs r2, #1 800bdc0: 701a strb r2, [r3, #0] if (HAL_UART_Transmit_DMA(&huart3, tx_buffer, tx_pending_len) != HAL_OK) { 800bdc2: 4b0e ldr r3, [pc, #56] @ (800bdfc ) 800bdc4: 881b ldrh r3, [r3, #0] 800bdc6: 461a mov r2, r3 800bdc8: 490e ldr r1, [pc, #56] @ (800be04 ) 800bdca: 480a ldr r0, [pc, #40] @ (800bdf4 ) 800bdcc: f007 f8b0 bl 8012f30 800bdd0: 4603 mov r3, r0 800bdd2: 2b00 cmp r3, #0 800bdd4: d005 beq.n 800bde2 uart3_tx_busy = 0; 800bdd6: 4b08 ldr r3, [pc, #32] @ (800bdf8 ) 800bdd8: 2200 movs r2, #0 800bdda: 701a strb r2, [r3, #0] CCS_LogUart3Error("UART3 TX DMA resend failed"); 800bddc: 480a ldr r0, [pc, #40] @ (800be08 ) 800bdde: f000 fdf9 bl 800c9d4 } tx_pending_len = 0; 800bde2: 4b06 ldr r3, [pc, #24] @ (800bdfc ) 800bde4: 2200 movs r2, #0 800bde6: 801a strh r2, [r3, #0] 800bde8: e000 b.n 800bdec return; 800bdea: bf00 nop } } 800bdec: 3708 adds r7, #8 800bdee: 46bd mov sp, r7 800bdf0: bd80 pop {r7, pc} 800bdf2: bf00 nop 800bdf4: 20001330 .word 0x20001330 800bdf8: 20000cae .word 0x20000cae 800bdfc: 20000cac .word 0x20000cac 800be00: 20000bac .word 0x20000bac 800be04: 20000aac .word 0x20000aac 800be08: 08017334 .word 0x08017334 0800be0c : void CCS_SerialLoop(void) { 800be0c: b580 push {r7, lr} 800be0e: b082 sub sp, #8 800be10: af00 add r7, sp, #0 static uint32_t tick; if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800be12: f002 fa91 bl 800e338 800be16: 4602 mov r2, r0 800be18: 4ba5 ldr r3, [pc, #660] @ (800c0b0 ) 800be1a: 681b ldr r3, [r3, #0] 800be1c: 1ad3 subs r3, r2, r3 800be1e: 2b00 cmp r3, #0 800be20: f340 826b ble.w 800c2fa tick = HAL_GetTick(); 800be24: f002 fa88 bl 800e338 800be28: 4603 mov r3, r0 800be2a: 4aa1 ldr r2, [pc, #644] @ (800c0b0 ) 800be2c: 6013 str r3, [r2, #0] static uint32_t replug_watchdog1_tick = 0; static uint32_t last_state_sent = 0; static uint32_t force_unlock_tick = 0; static uint32_t stop_tick = 0; CCS_UART3_Watchdog(); 800be2e: f000 fd97 bl 800c960 if (CONN.connControl != CMD_NONE) { 800be32: 4ba0 ldr r3, [pc, #640] @ (800c0b4 ) 800be34: 781b ldrb r3, [r3, #0] 800be36: 2b00 cmp r3, #0 800be38: d003 beq.n 800be42 last_cmd = CONN.connControl; 800be3a: 4b9e ldr r3, [pc, #632] @ (800c0b4 ) 800be3c: 781a ldrb r2, [r3, #0] 800be3e: 4b9e ldr r3, [pc, #632] @ (800c0b8 ) 800be40: 701a strb r2, [r3, #0] } if (CONN.connControl == CMD_FORCE_UNLOCK) { 800be42: 4b9c ldr r3, [pc, #624] @ (800c0b4 ) 800be44: 781b ldrb r3, [r3, #0] 800be46: 2b03 cmp r3, #3 800be48: d11b bne.n 800be82 if (force_unlock_tick == 0) { 800be4a: 4b9c ldr r3, [pc, #624] @ (800c0bc ) 800be4c: 681b ldr r3, [r3, #0] 800be4e: 2b00 cmp r3, #0 800be50: d105 bne.n 800be5e force_unlock_tick = HAL_GetTick(); 800be52: f002 fa71 bl 800e338 800be56: 4603 mov r3, r0 800be58: 4a98 ldr r2, [pc, #608] @ (800c0bc ) 800be5a: 6013 str r3, [r2, #0] 800be5c: e014 b.n 800be88 } else if ((int32_t)(HAL_GetTick() - force_unlock_tick) >= 10000) { 800be5e: f002 fa6b bl 800e338 800be62: 4602 mov r2, r0 800be64: 4b95 ldr r3, [pc, #596] @ (800c0bc ) 800be66: 681b ldr r3, [r3, #0] 800be68: 1ad3 subs r3, r2, r3 800be6a: 461a mov r2, r3 800be6c: f242 730f movw r3, #9999 @ 0x270f 800be70: 429a cmp r2, r3 800be72: dd09 ble.n 800be88 CONN.connControl = CMD_NONE; 800be74: 4b8f ldr r3, [pc, #572] @ (800c0b4 ) 800be76: 2200 movs r2, #0 800be78: 701a strb r2, [r3, #0] force_unlock_tick = 0; 800be7a: 4b90 ldr r3, [pc, #576] @ (800c0bc ) 800be7c: 2200 movs r2, #0 800be7e: 601a str r2, [r3, #0] 800be80: e002 b.n 800be88 } } else { force_unlock_tick = 0; 800be82: 4b8e ldr r3, [pc, #568] @ (800c0bc ) 800be84: 2200 movs r2, #0 800be86: 601a str r2, [r3, #0] } if (CONN.connControl == CMD_STOP) { 800be88: 4b8a ldr r3, [pc, #552] @ (800c0b4 ) 800be8a: 781b ldrb r3, [r3, #0] 800be8c: 2b01 cmp r3, #1 800be8e: d119 bne.n 800bec4 if (stop_tick == 0) { 800be90: 4b8b ldr r3, [pc, #556] @ (800c0c0 ) 800be92: 681b ldr r3, [r3, #0] 800be94: 2b00 cmp r3, #0 800be96: d105 bne.n 800bea4 stop_tick = HAL_GetTick(); 800be98: f002 fa4e bl 800e338 800be9c: 4603 mov r3, r0 800be9e: 4a88 ldr r2, [pc, #544] @ (800c0c0 ) 800bea0: 6013 str r3, [r2, #0] 800bea2: e012 b.n 800beca } else if ((int32_t)(HAL_GetTick() - stop_tick) >= 1000) { 800bea4: f002 fa48 bl 800e338 800bea8: 4602 mov r2, r0 800beaa: 4b85 ldr r3, [pc, #532] @ (800c0c0 ) 800beac: 681b ldr r3, [r3, #0] 800beae: 1ad3 subs r3, r2, r3 800beb0: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800beb4: db09 blt.n 800beca CONN.connControl = CMD_NONE; 800beb6: 4b7f ldr r3, [pc, #508] @ (800c0b4 ) 800beb8: 2200 movs r2, #0 800beba: 701a strb r2, [r3, #0] stop_tick = 0; 800bebc: 4b80 ldr r3, [pc, #512] @ (800c0c0 ) 800bebe: 2200 movs r2, #0 800bec0: 601a str r2, [r3, #0] 800bec2: e002 b.n 800beca } } else { stop_tick = 0; 800bec4: 4b7e ldr r3, [pc, #504] @ (800c0c0 ) 800bec6: 2200 movs r2, #0 800bec8: 601a str r2, [r3, #0] } if((int32_t)(HAL_GetTick() - last_cmd_sent) > (int32_t)CMD_INTERVAL){ 800beca: f002 fa35 bl 800e338 800bece: 4602 mov r2, r0 800bed0: 4b7c ldr r3, [pc, #496] @ (800c0c4 ) 800bed2: 681b ldr r3, [r3, #0] 800bed4: 1ad3 subs r3, r2, r3 800bed6: 2b0a cmp r3, #10 800bed8: dd5e ble.n 800bf98 if ((int32_t)(HAL_GetTick() - last_state_sent) >= 200) { 800beda: f002 fa2d bl 800e338 800bede: 4602 mov r2, r0 800bee0: 4b79 ldr r3, [pc, #484] @ (800c0c8 ) 800bee2: 681b ldr r3, [r3, #0] 800bee4: 1ad3 subs r3, r2, r3 800bee6: 2bc7 cmp r3, #199 @ 0xc7 800bee8: dd06 ble.n 800bef8 send_state(); 800beea: f000 fb9b bl 800c624 last_state_sent = HAL_GetTick(); 800beee: f002 fa23 bl 800e338 800bef2: 4603 mov r3, r0 800bef4: 4a74 ldr r2, [pc, #464] @ (800c0c8 ) 800bef6: 6013 str r3, [r2, #0] } if (ESTOP) { 800bef8: 4b74 ldr r3, [pc, #464] @ (800c0cc ) 800befa: 781b ldrb r3, [r3, #0] 800befc: 2b00 cmp r3, #0 800befe: d008 beq.n 800bf12 log_printf(LOG_ERR, "ESTOP triggered\n"); 800bf00: 4973 ldr r1, [pc, #460] @ (800c0d0 ) 800bf02: 2004 movs r0, #4 800bf04: f7fe fb26 bl 800a554 CCS_SendEmergencyStop(); 800bf08: f000 fb2c bl 800c564 ESTOP = 0; 800bf0c: 4b6f ldr r3, [pc, #444] @ (800c0cc ) 800bf0e: 2200 movs r2, #0 800bf10: 701a strb r2, [r3, #0] } if (((CONN.connControl == CMD_STOP) || 800bf12: 4b68 ldr r3, [pc, #416] @ (800c0b4 ) 800bf14: 781b ldrb r3, [r3, #0] 800bf16: 2b01 cmp r3, #1 800bf18: d007 beq.n 800bf2a (CONN.connControl == CMD_FORCE_UNLOCK) || 800bf1a: 4b66 ldr r3, [pc, #408] @ (800c0b4 ) 800bf1c: 781b ldrb r3, [r3, #0] if (((CONN.connControl == CMD_STOP) || 800bf1e: 2b03 cmp r3, #3 800bf20: d003 beq.n 800bf2a (CONN.chargingError != CONN_NO_ERROR)) && 800bf22: 4b64 ldr r3, [pc, #400] @ (800c0b4 ) 800bf24: 7f5b ldrb r3, [r3, #29] (CONN.connControl == CMD_FORCE_UNLOCK) || 800bf26: 2b00 cmp r3, #0 800bf28: d01a beq.n 800bf60 ((int32_t)(HAL_GetTick() - last_stop_sent) > 1000)) { 800bf2a: f002 fa05 bl 800e338 800bf2e: 4602 mov r2, r0 800bf30: 4b68 ldr r3, [pc, #416] @ (800c0d4 ) 800bf32: 681b ldr r3, [r3, #0] 800bf34: 1ad3 subs r3, r2, r3 (CONN.chargingError != CONN_NO_ERROR)) && 800bf36: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bf3a: dd11 ble.n 800bf60 last_stop_sent = HAL_GetTick(); 800bf3c: f002 f9fc bl 800e338 800bf40: 4603 mov r3, r0 800bf42: 4a64 ldr r2, [pc, #400] @ (800c0d4 ) 800bf44: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "Stopping charging...\n"); 800bf46: 4964 ldr r1, [pc, #400] @ (800c0d8 ) 800bf48: 2005 movs r0, #5 800bf4a: f7fe fb03 bl 800a554 if (CONN.connControl == CMD_FORCE_UNLOCK) { 800bf4e: 4b59 ldr r3, [pc, #356] @ (800c0b4 ) 800bf50: 781b ldrb r3, [r3, #0] 800bf52: 2b03 cmp r3, #3 800bf54: d102 bne.n 800bf5c CP_SetDuty(100); 800bf56: 2064 movs r0, #100 @ 0x64 800bf58: f7fe f8ba bl 800a0d0 } CCS_SendEmergencyStop(); 800bf5c: f000 fb02 bl 800c564 } if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800bf60: 4b5e ldr r3, [pc, #376] @ (800c0dc ) 800bf62: 781b ldrb r3, [r3, #0] 800bf64: 2b0c cmp r3, #12 800bf66: d003 beq.n 800bf70 800bf68: 4b5c ldr r3, [pc, #368] @ (800c0dc ) 800bf6a: 781b ldrb r3, [r3, #0] 800bf6c: 2b0b cmp r3, #11 800bf6e: d113 bne.n 800bf98 ((int32_t)(HAL_GetTick() - last_stop_sent) > 1000)) { 800bf70: f002 f9e2 bl 800e338 800bf74: 4602 mov r2, r0 800bf76: 4b57 ldr r3, [pc, #348] @ (800c0d4 ) 800bf78: 681b ldr r3, [r3, #0] 800bf7a: 1ad3 subs r3, r2, r3 if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800bf7c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bf80: dd0a ble.n 800bf98 last_stop_sent = HAL_GetTick(); 800bf82: f002 f9d9 bl 800e338 800bf86: 4603 mov r3, r0 800bf88: 4a52 ldr r2, [pc, #328] @ (800c0d4 ) 800bf8a: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "FinishedEV, stopping...\n"); 800bf8c: 4954 ldr r1, [pc, #336] @ (800c0e0 ) 800bf8e: 2005 movs r0, #5 800bf90: f7fe fae0 bl 800a554 CCS_SendEmergencyStop(); 800bf94: f000 fae6 bl 800c564 } (void)replug_watchdog_tick; (void)replug_watchdog1_tick; uint8_t host_timeout_warn = (last_host_seen > 0u) && ((int32_t)(HAL_GetTick() - last_host_seen) > (int32_t)EVEREST_TIMEOUT_WARN_MS); 800bf98: 4b52 ldr r3, [pc, #328] @ (800c0e4 ) 800bf9a: 681b ldr r3, [r3, #0] 800bf9c: 2b00 cmp r3, #0 800bf9e: d00c beq.n 800bfba 800bfa0: f002 f9ca bl 800e338 800bfa4: 4602 mov r2, r0 800bfa6: 4b4f ldr r3, [pc, #316] @ (800c0e4 ) 800bfa8: 681b ldr r3, [r3, #0] 800bfaa: 1ad3 subs r3, r2, r3 800bfac: 461a mov r2, r3 800bfae: f241 3388 movw r3, #5000 @ 0x1388 800bfb2: 429a cmp r2, r3 800bfb4: dd01 ble.n 800bfba 800bfb6: 2301 movs r3, #1 800bfb8: e000 b.n 800bfbc 800bfba: 2300 movs r3, #0 800bfbc: 71fb strb r3, [r7, #7] uint8_t host_timeout_stop = (last_host_seen > 0u) && ((int32_t)(HAL_GetTick() - last_host_seen) > (int32_t)EVEREST_TIMEOUT_STOP_MS); 800bfbe: 4b49 ldr r3, [pc, #292] @ (800c0e4 ) 800bfc0: 681b ldr r3, [r3, #0] 800bfc2: 2b00 cmp r3, #0 800bfc4: d00c beq.n 800bfe0 800bfc6: f002 f9b7 bl 800e338 800bfca: 4602 mov r2, r0 800bfcc: 4b45 ldr r3, [pc, #276] @ (800c0e4 ) 800bfce: 681b ldr r3, [r3, #0] 800bfd0: 1ad3 subs r3, r2, r3 800bfd2: 461a mov r2, r3 800bfd4: f242 7310 movw r3, #10000 @ 0x2710 800bfd8: 429a cmp r2, r3 800bfda: dd01 ble.n 800bfe0 800bfdc: 2301 movs r3, #1 800bfde: e000 b.n 800bfe2 800bfe0: 2300 movs r3, #0 800bfe2: 71bb strb r3, [r7, #6] uint8_t host_timed_out = host_timeout_stop; 800bfe4: 79bb ldrb r3, [r7, #6] 800bfe6: 717b strb r3, [r7, #5] if (host_timeout_warn && !everest_timeout_warn_latched) { 800bfe8: 79fb ldrb r3, [r7, #7] 800bfea: 2b00 cmp r3, #0 800bfec: d00a beq.n 800c004 800bfee: 4b3e ldr r3, [pc, #248] @ (800c0e8 ) 800bff0: 781b ldrb r3, [r3, #0] 800bff2: 2b00 cmp r3, #0 800bff4: d106 bne.n 800c004 log_printf(LOG_ERR, "Everest timeout\n"); 800bff6: 493d ldr r1, [pc, #244] @ (800c0ec ) 800bff8: 2004 movs r0, #4 800bffa: f7fe faab bl 800a554 everest_timeout_warn_latched = 1; 800bffe: 4b3a ldr r3, [pc, #232] @ (800c0e8 ) 800c000: 2201 movs r2, #1 800c002: 701a strb r2, [r3, #0] } if (host_timeout_stop && !everest_timeout_stop_latched) { 800c004: 79bb ldrb r3, [r7, #6] 800c006: 2b00 cmp r3, #0 800c008: d00a beq.n 800c020 800c00a: 4b39 ldr r3, [pc, #228] @ (800c0f0 ) 800c00c: 781b ldrb r3, [r3, #0] 800c00e: 2b00 cmp r3, #0 800c010: d106 bne.n 800c020 log_printf(LOG_ERR, "Everest timeout, stopping charging...\n"); 800c012: 4938 ldr r1, [pc, #224] @ (800c0f4 ) 800c014: 2004 movs r0, #4 800c016: f7fe fa9d bl 800a554 everest_timeout_stop_latched = 1; 800c01a: 4b35 ldr r3, [pc, #212] @ (800c0f0 ) 800c01c: 2201 movs r2, #1 800c01e: 701a strb r2, [r3, #0] } if (!host_timeout_warn) { 800c020: 79fb ldrb r3, [r7, #7] 800c022: 2b00 cmp r3, #0 800c024: d105 bne.n 800c032 everest_timeout_warn_latched = 0; 800c026: 4b30 ldr r3, [pc, #192] @ (800c0e8 ) 800c028: 2200 movs r2, #0 800c02a: 701a strb r2, [r3, #0] everest_timeout_stop_latched = 0; 800c02c: 4b30 ldr r3, [pc, #192] @ (800c0f0 ) 800c02e: 2200 movs r2, #0 800c030: 701a strb r2, [r3, #0] } everest_timed_out = host_timeout_stop; 800c032: 4a31 ldr r2, [pc, #196] @ (800c0f8 ) 800c034: 79bb ldrb r3, [r7, #6] 800c036: 7013 strb r3, [r2, #0] switch(CCS_ConnectorState){ 800c038: 4b30 ldr r3, [pc, #192] @ (800c0fc ) 800c03a: 781b ldrb r3, [r3, #0] 800c03c: 2b05 cmp r3, #5 800c03e: f200 8113 bhi.w 800c268 800c042: a201 add r2, pc, #4 @ (adr r2, 800c048 ) 800c044: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c048: 0800c061 .word 0x0800c061 800c04c: 0800c089 .word 0x0800c089 800c050: 0800c105 .word 0x0800c105 800c054: 0800c149 .word 0x0800c149 800c058: 0800c185 .word 0x0800c185 800c05c: 0800c1dd .word 0x0800c1dd case CCS_UNKNOWN: RELAY_Write(RELAY_CP, 0); 800c060: 2100 movs r1, #0 800c062: 2005 movs r0, #5 800c064: f7fd fba8 bl 80097b8 CONN_SetState(Unknown); 800c068: 2000 movs r0, #0 800c06a: f7fd ff39 bl 8009ee0 if (config_initialized && !host_timed_out) { 800c06e: 4b24 ldr r3, [pc, #144] @ (800c100 ) 800c070: 781b ldrb r3, [r3, #0] 800c072: 2b00 cmp r3, #0 800c074: f000 80ed beq.w 800c252 800c078: 797b ldrb r3, [r7, #5] 800c07a: 2b00 cmp r3, #0 800c07c: f040 80e9 bne.w 800c252 CCS_ConnectorState = CCS_UNPLUGGED; 800c080: 4b1e ldr r3, [pc, #120] @ (800c0fc ) 800c082: 2202 movs r2, #2 800c084: 701a strb r2, [r3, #0] } break; 800c086: e0e4 b.n 800c252 case CCS_DISABLED: RELAY_Write(RELAY_CP, 0); 800c088: 2100 movs r1, #0 800c08a: 2005 movs r0, #5 800c08c: f7fd fb94 bl 80097b8 CONN_SetState(Disabled); 800c090: 2002 movs r0, #2 800c092: f7fd ff25 bl 8009ee0 if ((CONN.chargingError == CONN_NO_ERROR) && !host_timed_out){ 800c096: 4b07 ldr r3, [pc, #28] @ (800c0b4 ) 800c098: 7f5b ldrb r3, [r3, #29] 800c09a: 2b00 cmp r3, #0 800c09c: f040 80db bne.w 800c256 800c0a0: 797b ldrb r3, [r7, #5] 800c0a2: 2b00 cmp r3, #0 800c0a4: f040 80d7 bne.w 800c256 CCS_ConnectorState = CCS_UNPLUGGED; 800c0a8: 4b14 ldr r3, [pc, #80] @ (800c0fc ) 800c0aa: 2202 movs r2, #2 800c0ac: 701a strb r2, [r3, #0] } break; 800c0ae: e0d2 b.n 800c256 800c0b0: 20000d14 .word 0x20000d14 800c0b4: 200003b0 .word 0x200003b0 800c0b8: 200009a8 .word 0x200009a8 800c0bc: 20000d18 .word 0x20000d18 800c0c0: 20000d1c .word 0x20000d1c 800c0c4: 200009a0 .word 0x200009a0 800c0c8: 20000d20 .word 0x20000d20 800c0cc: 20000caf .word 0x20000caf 800c0d0: 08017350 .word 0x08017350 800c0d4: 200009a4 .word 0x200009a4 800c0d8: 08017364 .word 0x08017364 800c0dc: 20000d10 .word 0x20000d10 800c0e0: 0801737c .word 0x0801737c 800c0e4: 20000cb4 .word 0x20000cb4 800c0e8: 20000cba .word 0x20000cba 800c0ec: 08017398 .word 0x08017398 800c0f0: 20000cbb .word 0x20000cbb 800c0f4: 080173ac .word 0x080173ac 800c0f8: 20000cb9 .word 0x20000cb9 800c0fc: 20000d11 .word 0x20000d11 800c100: 200011c0 .word 0x200011c0 case CCS_UNPLUGGED: RELAY_Write(RELAY_CP, 1); 800c104: 2101 movs r1, #1 800c106: 2005 movs r0, #5 800c108: f7fd fb56 bl 80097b8 CONN_SetState(Unplugged); 800c10c: 2001 movs r0, #1 800c10e: f7fd fee7 bl 8009ee0 if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || (cp_state_buffer == EV_STATE_C_CONN_ACTIVE)){ 800c112: 4b7c ldr r3, [pc, #496] @ (800c304 ) 800c114: 781b ldrb r3, [r3, #0] 800c116: 2b01 cmp r3, #1 800c118: d003 beq.n 800c122 800c11a: 4b7a ldr r3, [pc, #488] @ (800c304 ) 800c11c: 781b ldrb r3, [r3, #0] 800c11e: 2b02 cmp r3, #2 800c120: d102 bne.n 800c128 CCS_ConnectorState = CCS_AUTH_REQUIRED; 800c122: 4b79 ldr r3, [pc, #484] @ (800c308 ) 800c124: 2203 movs r2, #3 800c126: 701a strb r2, [r3, #0] } if (CONN.chargingError != CONN_NO_ERROR){ 800c128: 4b78 ldr r3, [pc, #480] @ (800c30c ) 800c12a: 7f5b ldrb r3, [r3, #29] 800c12c: 2b00 cmp r3, #0 800c12e: f000 8094 beq.w 800c25a log_printf(LOG_ERR, "Charging error %d, state -> disabled\n", CONN.chargingError); 800c132: 4b76 ldr r3, [pc, #472] @ (800c30c ) 800c134: 7f5b ldrb r3, [r3, #29] 800c136: 461a mov r2, r3 800c138: 4975 ldr r1, [pc, #468] @ (800c310 ) 800c13a: 2004 movs r0, #4 800c13c: f7fe fa0a bl 800a554 CCS_ConnectorState = CCS_DISABLED; 800c140: 4b71 ldr r3, [pc, #452] @ (800c308 ) 800c142: 2201 movs r2, #1 800c144: 701a strb r2, [r3, #0] } break; 800c146: e088 b.n 800c25a case CCS_AUTH_REQUIRED: RELAY_Write(RELAY_CP, 1); 800c148: 2101 movs r1, #1 800c14a: 2005 movs r0, #5 800c14c: f7fd fb34 bl 80097b8 CONN_SetState(AuthRequired); 800c150: 2004 movs r0, #4 800c152: f7fd fec5 bl 8009ee0 if(CONN.connControl == CMD_START){ 800c156: 4b6d ldr r3, [pc, #436] @ (800c30c ) 800c158: 781b ldrb r3, [r3, #0] 800c15a: 2b02 cmp r3, #2 800c15c: d106 bne.n 800c16c log_printf(LOG_INFO, "Charging permitted, start charging\n"); 800c15e: 496d ldr r1, [pc, #436] @ (800c314 ) 800c160: 2007 movs r0, #7 800c162: f7fe f9f7 bl 800a554 CCS_ConnectorState = CCS_CONNECTED; 800c166: 4b68 ldr r3, [pc, #416] @ (800c308 ) 800c168: 2204 movs r2, #4 800c16a: 701a strb r2, [r3, #0] } if (cp_state_buffer == EV_STATE_A_IDLE){ 800c16c: 4b65 ldr r3, [pc, #404] @ (800c304 ) 800c16e: 781b ldrb r3, [r3, #0] 800c170: 2b00 cmp r3, #0 800c172: d174 bne.n 800c25e log_printf(LOG_INFO, "Car unplugged\n"); 800c174: 4968 ldr r1, [pc, #416] @ (800c318 ) 800c176: 2007 movs r0, #7 800c178: f7fe f9ec bl 800a554 CCS_ConnectorState = CCS_UNPLUGGED; 800c17c: 4b62 ldr r3, [pc, #392] @ (800c308 ) 800c17e: 2202 movs r2, #2 800c180: 701a strb r2, [r3, #0] } break; 800c182: e06c b.n 800c25e case CCS_CONNECTED: RELAY_Write(RELAY_CP, 1); 800c184: 2101 movs r1, #1 800c186: 2005 movs r0, #5 800c188: f7fd fb16 bl 80097b8 if((CCS_EvseState < Preparing) || (CCS_EvseState == AuthRequired)) { 800c18c: 4b63 ldr r3, [pc, #396] @ (800c31c ) 800c18e: 781b ldrb r3, [r3, #0] 800c190: 2b02 cmp r3, #2 800c192: d903 bls.n 800c19c 800c194: 4b61 ldr r3, [pc, #388] @ (800c31c ) 800c196: 781b ldrb r3, [r3, #0] 800c198: 2b04 cmp r3, #4 800c19a: d103 bne.n 800c1a4 CONN_SetState(Preparing); 800c19c: 2003 movs r0, #3 800c19e: f7fd fe9f bl 8009ee0 800c1a2: e004 b.n 800c1ae } else { CONN_SetState(CCS_EvseState); 800c1a4: 4b5d ldr r3, [pc, #372] @ (800c31c ) 800c1a6: 781b ldrb r3, [r3, #0] 800c1a8: 4618 mov r0, r3 800c1aa: f7fd fe99 bl 8009ee0 } if (cp_state_buffer == EV_STATE_A_IDLE){ 800c1ae: 4b55 ldr r3, [pc, #340] @ (800c304 ) 800c1b0: 781b ldrb r3, [r3, #0] 800c1b2: 2b00 cmp r3, #0 800c1b4: d106 bne.n 800c1c4 log_printf(LOG_INFO, "Car unplugged\n"); 800c1b6: 4958 ldr r1, [pc, #352] @ (800c318 ) 800c1b8: 2007 movs r0, #7 800c1ba: f7fe f9cb bl 800a554 CCS_ConnectorState = CCS_UNPLUGGED; 800c1be: 4b52 ldr r3, [pc, #328] @ (800c308 ) 800c1c0: 2202 movs r2, #2 800c1c2: 701a strb r2, [r3, #0] } if(REPLUG > 0){ 800c1c4: 4b56 ldr r3, [pc, #344] @ (800c320 ) 800c1c6: 781b ldrb r3, [r3, #0] 800c1c8: 2b00 cmp r3, #0 800c1ca: d04a beq.n 800c262 log_printf(LOG_INFO, "Replugging...\n"); 800c1cc: 4955 ldr r1, [pc, #340] @ (800c324 ) 800c1ce: 2007 movs r0, #7 800c1d0: f7fe f9c0 bl 800a554 CCS_ConnectorState = CCS_REPLUGGING; 800c1d4: 4b4c ldr r3, [pc, #304] @ (800c308 ) 800c1d6: 2205 movs r2, #5 800c1d8: 701a strb r2, [r3, #0] } break; 800c1da: e042 b.n 800c262 case CCS_REPLUGGING: RELAY_Write(RELAY_CP, 0); 800c1dc: 2100 movs r1, #0 800c1de: 2005 movs r0, #5 800c1e0: f7fd faea bl 80097b8 CONN_SetState(Replugging); 800c1e4: 200d movs r0, #13 800c1e6: f7fd fe7b bl 8009ee0 if((int32_t)(HAL_GetTick() - replug_tick) > 1000){ 800c1ea: f002 f8a5 bl 800e338 800c1ee: 4602 mov r2, r0 800c1f0: 4b4d ldr r3, [pc, #308] @ (800c328 ) 800c1f2: 681b ldr r3, [r3, #0] 800c1f4: 1ad3 subs r3, r2, r3 800c1f6: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800c1fa: dd1a ble.n 800c232 replug_tick = HAL_GetTick(); 800c1fc: f002 f89c bl 800e338 800c200: 4603 mov r3, r0 800c202: 4a49 ldr r2, [pc, #292] @ (800c328 ) 800c204: 6013 str r3, [r2, #0] if(REPLUG > 0){ 800c206: 4b46 ldr r3, [pc, #280] @ (800c320 ) 800c208: 781b ldrb r3, [r3, #0] 800c20a: 2b00 cmp r3, #0 800c20c: d00a beq.n 800c224 if (REPLUG != 0xFF) REPLUG--; 800c20e: 4b44 ldr r3, [pc, #272] @ (800c320 ) 800c210: 781b ldrb r3, [r3, #0] 800c212: 2bff cmp r3, #255 @ 0xff 800c214: d00d beq.n 800c232 800c216: 4b42 ldr r3, [pc, #264] @ (800c320 ) 800c218: 781b ldrb r3, [r3, #0] 800c21a: 3b01 subs r3, #1 800c21c: b2da uxtb r2, r3 800c21e: 4b40 ldr r3, [pc, #256] @ (800c320 ) 800c220: 701a strb r2, [r3, #0] 800c222: e006 b.n 800c232 } else { log_printf(LOG_INFO, "Replugging finished, but car unplugged\n"); 800c224: 4941 ldr r1, [pc, #260] @ (800c32c ) 800c226: 2007 movs r0, #7 800c228: f7fe f994 bl 800a554 CCS_ConnectorState = CCS_UNPLUGGED; 800c22c: 4b36 ldr r3, [pc, #216] @ (800c308 ) 800c22e: 2202 movs r2, #2 800c230: 701a strb r2, [r3, #0] } } if(REPLUG == 0){ 800c232: 4b3b ldr r3, [pc, #236] @ (800c320 ) 800c234: 781b ldrb r3, [r3, #0] 800c236: 2b00 cmp r3, #0 800c238: d115 bne.n 800c266 if(cp_state_buffer == EV_STATE_B_CONN_PREP){ 800c23a: 4b32 ldr r3, [pc, #200] @ (800c304 ) 800c23c: 781b ldrb r3, [r3, #0] 800c23e: 2b01 cmp r3, #1 800c240: d111 bne.n 800c266 log_printf(LOG_INFO, "Replugging finished, car plugged, state -> auth required\n"); 800c242: 493b ldr r1, [pc, #236] @ (800c330 ) 800c244: 2007 movs r0, #7 800c246: f7fe f985 bl 800a554 CCS_ConnectorState = CCS_AUTH_REQUIRED; 800c24a: 4b2f ldr r3, [pc, #188] @ (800c308 ) 800c24c: 2203 movs r2, #3 800c24e: 701a strb r2, [r3, #0] } } break; 800c250: e009 b.n 800c266 break; 800c252: bf00 nop 800c254: e008 b.n 800c268 break; 800c256: bf00 nop 800c258: e006 b.n 800c268 break; 800c25a: bf00 nop 800c25c: e004 b.n 800c268 break; 800c25e: bf00 nop 800c260: e002 b.n 800c268 break; 800c262: bf00 nop 800c264: e000 b.n 800c268 break; 800c266: bf00 nop } // 10s timeout: enforce safe-state until host communication recovers. if (host_timeout_stop) { 800c268: 79bb ldrb r3, [r7, #6] 800c26a: 2b00 cmp r3, #0 800c26c: d014 beq.n 800c298 CONN.EnableOutput = 0; 800c26e: 4b27 ldr r3, [pc, #156] @ (800c30c ) 800c270: 2200 movs r2, #0 800c272: 75da strb r2, [r3, #23] CCS_EvseState = Unknown; 800c274: 4b29 ldr r3, [pc, #164] @ (800c31c ) 800c276: 2200 movs r2, #0 800c278: 701a strb r2, [r3, #0] CP_SetDuty(100); 800c27a: 2064 movs r0, #100 @ 0x64 800c27c: f7fd ff28 bl 800a0d0 if (CCS_ConnectorState != CCS_DISABLED && CCS_ConnectorState != CCS_UNKNOWN) { 800c280: 4b21 ldr r3, [pc, #132] @ (800c308 ) 800c282: 781b ldrb r3, [r3, #0] 800c284: 2b01 cmp r3, #1 800c286: d024 beq.n 800c2d2 800c288: 4b1f ldr r3, [pc, #124] @ (800c308 ) 800c28a: 781b ldrb r3, [r3, #0] 800c28c: 2b00 cmp r3, #0 800c28e: d020 beq.n 800c2d2 CCS_ConnectorState = CCS_DISABLED; 800c290: 4b1d ldr r3, [pc, #116] @ (800c308 ) 800c292: 2201 movs r2, #1 800c294: 701a strb r2, [r3, #0] 800c296: e01c b.n 800c2d2 } } else { if (last_cmd == CMD_STOP) { 800c298: 4b26 ldr r3, [pc, #152] @ (800c334 ) 800c29a: 781b ldrb r3, [r3, #0] 800c29c: 2b01 cmp r3, #1 800c29e: d103 bne.n 800c2a8 CONN.EnableOutput = 0; 800c2a0: 4b1a ldr r3, [pc, #104] @ (800c30c ) 800c2a2: 2200 movs r2, #0 800c2a4: 75da strb r2, [r3, #23] 800c2a6: e014 b.n 800c2d2 } else { CONN.EnableOutput = ev_enable_output ? 1 : 0; 800c2a8: 4b23 ldr r3, [pc, #140] @ (800c338 ) 800c2aa: 781b ldrb r3, [r3, #0] 800c2ac: 2b00 cmp r3, #0 800c2ae: bf14 ite ne 800c2b0: 2301 movne r3, #1 800c2b2: 2300 moveq r3, #0 800c2b4: b2db uxtb r3, r3 800c2b6: 461a mov r2, r3 800c2b8: 4b14 ldr r3, [pc, #80] @ (800c30c ) 800c2ba: 75da strb r2, [r3, #23] if((CONN.EnableOutput == 0) && (CONN.connState == Preparing)){ 800c2bc: 4b13 ldr r3, [pc, #76] @ (800c30c ) 800c2be: 7ddb ldrb r3, [r3, #23] 800c2c0: 2b00 cmp r3, #0 800c2c2: d106 bne.n 800c2d2 800c2c4: 4b11 ldr r3, [pc, #68] @ (800c30c ) 800c2c6: 785b ldrb r3, [r3, #1] 800c2c8: 2b03 cmp r3, #3 800c2ca: d102 bne.n 800c2d2 CONN.EnableOutput = 0; 800c2cc: 4b0f ldr r3, [pc, #60] @ (800c30c ) 800c2ce: 2200 movs r2, #0 800c2d0: 75da strb r2, [r3, #23] } } } if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800c2d2: 4b0c ldr r3, [pc, #48] @ (800c304 ) 800c2d4: 781b ldrb r3, [r3, #0] 800c2d6: 2b01 cmp r3, #1 800c2d8: d007 beq.n 800c2ea (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800c2da: 4b0a ldr r3, [pc, #40] @ (800c304 ) 800c2dc: 781b ldrb r3, [r3, #0] if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800c2de: 2b02 cmp r3, #2 800c2e0: d003 beq.n 800c2ea (cp_state_buffer == EV_STATE_D_CONN_ACT_VENT)) { 800c2e2: 4b08 ldr r3, [pc, #32] @ (800c304 ) 800c2e4: 781b ldrb r3, [r3, #0] (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800c2e6: 2b03 cmp r3, #3 800c2e8: d103 bne.n 800c2f2 CONN.EvConnected = 1; 800c2ea: 4b08 ldr r3, [pc, #32] @ (800c30c ) 800c2ec: 2201 movs r2, #1 800c2ee: 779a strb r2, [r3, #30] 800c2f0: e004 b.n 800c2fc } else { CONN.EvConnected = 0; 800c2f2: 4b06 ldr r3, [pc, #24] @ (800c30c ) 800c2f4: 2200 movs r2, #0 800c2f6: 779a strb r2, [r3, #30] 800c2f8: e000 b.n 800c2fc if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800c2fa: bf00 nop } } 800c2fc: 3708 adds r7, #8 800c2fe: 46bd mov sp, r7 800c300: bd80 pop {r7, pc} 800c302: bf00 nop 800c304: 20000005 .word 0x20000005 800c308: 20000d11 .word 0x20000d11 800c30c: 200003b0 .word 0x200003b0 800c310: 080173d4 .word 0x080173d4 800c314: 080173fc .word 0x080173fc 800c318: 08017420 .word 0x08017420 800c31c: 20000d10 .word 0x20000d10 800c320: 20000cb0 .word 0x20000cb0 800c324: 08017430 .word 0x08017430 800c328: 20000d24 .word 0x20000d24 800c32c: 08017440 .word 0x08017440 800c330: 08017468 .word 0x08017468 800c334: 200009a8 .word 0x200009a8 800c338: 200009a9 .word 0x200009a9 0800c33c : void CCS_Init(void){ 800c33c: b580 push {r7, lr} 800c33e: af00 add r7, sp, #0 CP_Init(); 800c340: f7fd fea4 bl 800a08c CP_SetDuty(100); 800c344: 2064 movs r0, #100 @ 0x64 800c346: f7fd fec3 bl 800a0d0 CCS_MaxLoad.maxVoltage = PSU_MAX_VOLTAGE; // 1000V 800c34a: 4b13 ldr r3, [pc, #76] @ (800c398 ) 800c34c: f44f 727a mov.w r2, #1000 @ 0x3e8 800c350: 801a strh r2, [r3, #0] CCS_MaxLoad.minVoltage = PSU_MIN_VOLTAGE; //150V 800c352: 4b11 ldr r3, [pc, #68] @ (800c398 ) 800c354: 2296 movs r2, #150 @ 0x96 800c356: 805a strh r2, [r3, #2] CCS_MaxLoad.maxCurrent = PSU_MAX_CURRENT*10; //100A 800c358: 4b0f ldr r3, [pc, #60] @ (800c398 ) 800c35a: f240 5232 movw r2, #1330 @ 0x532 800c35e: 809a strh r2, [r3, #4] CCS_MaxLoad.minCurrent = PSU_MIN_CURRENT*10; //1A 800c360: 4b0d ldr r3, [pc, #52] @ (800c398 ) 800c362: 220a movs r2, #10 800c364: 80da strh r2, [r3, #6] CCS_MaxLoad.maxPower = PSU_MAX_POWER; //30000W 800c366: 4b0c ldr r3, [pc, #48] @ (800c398 ) 800c368: f649 4240 movw r2, #40000 @ 0x9c40 800c36c: 609a str r2, [r3, #8] uart3_last_packet_tick = HAL_GetTick(); 800c36e: f001 ffe3 bl 800e338 800c372: 4603 mov r3, r0 800c374: 4a09 ldr r2, [pc, #36] @ (800c39c ) 800c376: 6013 str r3, [r2, #0] uart3_last_reinit_tick = uart3_last_packet_tick; 800c378: 4b08 ldr r3, [pc, #32] @ (800c39c ) 800c37a: 681b ldr r3, [r3, #0] 800c37c: 4a08 ldr r2, [pc, #32] @ (800c3a0 ) 800c37e: 6013 str r3, [r2, #0] uart3_arm_rx_or_log("Init"); 800c380: 4808 ldr r0, [pc, #32] @ (800c3a4 ) 800c382: f7ff fc2b bl 800bbdc CCS_SendResetReason(); 800c386: f000 f8e3 bl 800c550 log_printf(LOG_INFO, "CCS init\n"); 800c38a: 4907 ldr r1, [pc, #28] @ (800c3a8 ) 800c38c: 2007 movs r0, #7 800c38e: f7fe f8e1 bl 800a554 } 800c392: bf00 nop 800c394: bd80 pop {r7, pc} 800c396: bf00 nop 800c398: 20000988 .word 0x20000988 800c39c: 20000cbc .word 0x20000cbc 800c3a0: 20000cc0 .word 0x20000cc0 800c3a4: 080174a4 .word 0x080174a4 800c3a8: 080174ac .word 0x080174ac 0800c3ac : ISR_FAST static uint16_t crc16_ibm(const uint8_t* data, uint16_t length) { uint16_t crc = 0xFFFFu; for (uint16_t i = 0; i < length; i++) { 800c3ac: b3e9 cbz r1, 800c42a 800c3ae: 4684 mov ip, r0 ISR_FAST static uint16_t crc16_ibm(const uint8_t* data, uint16_t length) { 800c3b0: b500 push {lr} 800c3b2: 468e mov lr, r1 uint16_t crc = 0xFFFFu; 800c3b4: f64f 70ff movw r0, #65535 @ 0xffff crc ^= data[i]; for (uint8_t j = 0; j < 8; j++) { if (crc & 1u) { 800c3b8: 491d ldr r1, [pc, #116] @ (800c430 ) 800c3ba: 44e6 add lr, ip crc ^= data[i]; 800c3bc: f81c 2b01 ldrb.w r2, [ip], #1 800c3c0: 4042 eors r2, r0 if (crc & 1u) { 800c3c2: f342 0300 sbfx r3, r2, #0, #1 800c3c6: 400b ands r3, r1 800c3c8: ea83 0352 eor.w r3, r3, r2, lsr #1 800c3cc: f343 0200 sbfx r2, r3, #0, #1 800c3d0: 400a ands r2, r1 crc = (crc >> 1) ^ 0xA001u; } else { crc >>= 1; 800c3d2: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c3d6: 405a eors r2, r3 800c3d8: f342 0300 sbfx r3, r2, #0, #1 800c3dc: 400b ands r3, r1 crc >>= 1; 800c3de: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800c3e2: 4053 eors r3, r2 800c3e4: f343 0200 sbfx r2, r3, #0, #1 800c3e8: 400a ands r2, r1 crc >>= 1; 800c3ea: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c3ee: 405a eors r2, r3 800c3f0: f342 0300 sbfx r3, r2, #0, #1 800c3f4: 400b ands r3, r1 crc >>= 1; 800c3f6: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800c3fa: 4053 eors r3, r2 800c3fc: f343 0200 sbfx r2, r3, #0, #1 800c400: 400a ands r2, r1 crc >>= 1; 800c402: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c406: 405a eors r2, r3 800c408: f342 0300 sbfx r3, r2, #0, #1 800c40c: 400b ands r3, r1 crc >>= 1; 800c40e: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800c412: 4053 eors r3, r2 800c414: f343 0000 sbfx r0, r3, #0, #1 800c418: 4008 ands r0, r1 crc >>= 1; 800c41a: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c41e: 4058 eors r0, r3 for (uint16_t i = 0; i < length; i++) { 800c420: 45e6 cmp lr, ip if (crc & 1u) { 800c422: b280 uxth r0, r0 for (uint16_t i = 0; i < length; i++) { 800c424: d1ca bne.n 800c3bc } } } return crc; } 800c426: f85d fb04 ldr.w pc, [sp], #4 uint16_t crc = 0xFFFFu; 800c42a: f64f 70ff movw r0, #65535 @ 0xffff } 800c42e: 4770 bx lr 800c430: ffffa001 .word 0xffffa001 0800c434 : static uint16_t CCS_BuildPacket(uint8_t cmd, const void* payload, uint16_t payload_len, uint8_t* out, uint16_t out_max) { 800c434: b580 push {r7, lr} 800c436: b086 sub sp, #24 800c438: af00 add r7, sp, #0 800c43a: 60b9 str r1, [r7, #8] 800c43c: 607b str r3, [r7, #4] 800c43e: 4603 mov r3, r0 800c440: 73fb strb r3, [r7, #15] 800c442: 4613 mov r3, r2 800c444: 81bb strh r3, [r7, #12] uint16_t total_len = (uint16_t)(1u + payload_len + 2u); 800c446: 89bb ldrh r3, [r7, #12] 800c448: 3303 adds r3, #3 800c44a: 82fb strh r3, [r7, #22] if (total_len > out_max) return 0; 800c44c: 8afa ldrh r2, [r7, #22] 800c44e: 8c3b ldrh r3, [r7, #32] 800c450: 429a cmp r2, r3 800c452: d901 bls.n 800c458 800c454: 2300 movs r3, #0 800c456: e029 b.n 800c4ac out[0] = cmd; 800c458: 687b ldr r3, [r7, #4] 800c45a: 7bfa ldrb r2, [r7, #15] 800c45c: 701a strb r2, [r3, #0] if (payload_len && payload != NULL) { 800c45e: 89bb ldrh r3, [r7, #12] 800c460: 2b00 cmp r3, #0 800c462: d009 beq.n 800c478 800c464: 68bb ldr r3, [r7, #8] 800c466: 2b00 cmp r3, #0 800c468: d006 beq.n 800c478 memcpy(&out[1], payload, payload_len); 800c46a: 687b ldr r3, [r7, #4] 800c46c: 3301 adds r3, #1 800c46e: 89ba ldrh r2, [r7, #12] 800c470: 68b9 ldr r1, [r7, #8] 800c472: 4618 mov r0, r3 800c474: f008 fc62 bl 8014d3c } uint16_t crc = crc16_ibm(out, (uint16_t)(1u + payload_len)); 800c478: 89bb ldrh r3, [r7, #12] 800c47a: 3301 adds r3, #1 800c47c: b29b uxth r3, r3 800c47e: 4619 mov r1, r3 800c480: 6878 ldr r0, [r7, #4] 800c482: f7ff ff93 bl 800c3ac 800c486: 4603 mov r3, r0 800c488: 82bb strh r3, [r7, #20] out[1u + payload_len] = (uint8_t)(crc & 0xFFu); 800c48a: 89bb ldrh r3, [r7, #12] 800c48c: 3301 adds r3, #1 800c48e: 687a ldr r2, [r7, #4] 800c490: 4413 add r3, r2 800c492: 8aba ldrh r2, [r7, #20] 800c494: b2d2 uxtb r2, r2 800c496: 701a strb r2, [r3, #0] out[1u + payload_len + 1u] = (uint8_t)((crc >> 8) & 0xFFu); 800c498: 8abb ldrh r3, [r7, #20] 800c49a: 0a1b lsrs r3, r3, #8 800c49c: b299 uxth r1, r3 800c49e: 89bb ldrh r3, [r7, #12] 800c4a0: 3302 adds r3, #2 800c4a2: 687a ldr r2, [r7, #4] 800c4a4: 4413 add r3, r2 800c4a6: b2ca uxtb r2, r1 800c4a8: 701a strb r2, [r3, #0] return total_len; 800c4aa: 8afb ldrh r3, [r7, #22] } 800c4ac: 4618 mov r0, r3 800c4ae: 3718 adds r7, #24 800c4b0: 46bd mov sp, r7 800c4b2: bd80 pop {r7, pc} 0800c4b4 : static void CCS_SendPacket(uint8_t cmd, const void* payload, uint16_t payload_len) { 800c4b4: b580 push {r7, lr} 800c4b6: b086 sub sp, #24 800c4b8: af02 add r7, sp, #8 800c4ba: 4603 mov r3, r0 800c4bc: 6039 str r1, [r7, #0] 800c4be: 71fb strb r3, [r7, #7] 800c4c0: 4613 mov r3, r2 800c4c2: 80bb strh r3, [r7, #4] uint16_t len = CCS_BuildPacket(cmd, payload, payload_len, tx_buffer, sizeof(tx_buffer)); 800c4c4: 88ba ldrh r2, [r7, #4] 800c4c6: 79f8 ldrb r0, [r7, #7] 800c4c8: f44f 7380 mov.w r3, #256 @ 0x100 800c4cc: 9300 str r3, [sp, #0] 800c4ce: 4b19 ldr r3, [pc, #100] @ (800c534 ) 800c4d0: 6839 ldr r1, [r7, #0] 800c4d2: f7ff ffaf bl 800c434 800c4d6: 4603 mov r3, r0 800c4d8: 81fb strh r3, [r7, #14] if (len > 0) { 800c4da: 89fb ldrh r3, [r7, #14] 800c4dc: 2b00 cmp r3, #0 800c4de: d01f beq.n 800c520 if (uart3_tx_busy) { 800c4e0: 4b15 ldr r3, [pc, #84] @ (800c538 ) 800c4e2: 781b ldrb r3, [r3, #0] 800c4e4: 2b00 cmp r3, #0 800c4e6: d009 beq.n 800c4fc memcpy(tx_pending_buffer, tx_buffer, len); 800c4e8: 89fb ldrh r3, [r7, #14] 800c4ea: 461a mov r2, r3 800c4ec: 4911 ldr r1, [pc, #68] @ (800c534 ) 800c4ee: 4813 ldr r0, [pc, #76] @ (800c53c ) 800c4f0: f008 fc24 bl 8014d3c tx_pending_len = len; 800c4f4: 4a12 ldr r2, [pc, #72] @ (800c540 ) 800c4f6: 89fb ldrh r3, [r7, #14] 800c4f8: 8013 strh r3, [r2, #0] 800c4fa: e011 b.n 800c520 } else { uart3_tx_busy = 1; 800c4fc: 4b0e ldr r3, [pc, #56] @ (800c538 ) 800c4fe: 2201 movs r2, #1 800c500: 701a strb r2, [r3, #0] if (HAL_UART_Transmit_DMA(&huart3, tx_buffer, len) != HAL_OK) { 800c502: 89fb ldrh r3, [r7, #14] 800c504: 461a mov r2, r3 800c506: 490b ldr r1, [pc, #44] @ (800c534 ) 800c508: 480e ldr r0, [pc, #56] @ (800c544 ) 800c50a: f006 fd11 bl 8012f30 800c50e: 4603 mov r3, r0 800c510: 2b00 cmp r3, #0 800c512: d005 beq.n 800c520 uart3_tx_busy = 0; 800c514: 4b08 ldr r3, [pc, #32] @ (800c538 ) 800c516: 2200 movs r2, #0 800c518: 701a strb r2, [r3, #0] CCS_LogUart3Error("UART3 TX DMA start failed"); 800c51a: 480b ldr r0, [pc, #44] @ (800c548 ) 800c51c: f000 fa5a bl 800c9d4 } } } last_cmd_sent = HAL_GetTick(); 800c520: f001 ff0a bl 800e338 800c524: 4603 mov r3, r0 800c526: 4a09 ldr r2, [pc, #36] @ (800c54c ) 800c528: 6013 str r3, [r2, #0] } 800c52a: bf00 nop 800c52c: 3710 adds r7, #16 800c52e: 46bd mov sp, r7 800c530: bd80 pop {r7, pc} 800c532: bf00 nop 800c534: 20000aac .word 0x20000aac 800c538: 20000cae .word 0x20000cae 800c53c: 20000bac .word 0x20000bac 800c540: 20000cac .word 0x20000cac 800c544: 20001330 .word 0x20001330 800c548: 080174b8 .word 0x080174b8 800c54c: 200009a0 .word 0x200009a0 0800c550 : static void CCS_SendResetReason(void) { 800c550: b580 push {r7, lr} 800c552: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_RESET, NULL, 0); 800c554: 2200 movs r2, #0 800c556: 2100 movs r1, #0 800c558: 2052 movs r0, #82 @ 0x52 800c55a: f7ff ffab bl 800c4b4 } 800c55e: bf00 nop 800c560: bd80 pop {r7, pc} 800c562: bf00 nop 0800c564 : void CCS_SendEmergencyStop(void) { 800c564: b580 push {r7, lr} 800c566: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_ESTOP, NULL, 0); 800c568: 2200 movs r2, #0 800c56a: 2100 movs r1, #0 800c56c: 2053 movs r0, #83 @ 0x53 800c56e: f7ff ffa1 bl 800c4b4 } 800c572: bf00 nop 800c574: bd80 pop {r7, pc} 800c576: bf00 nop 0800c578 : void CCS_SendStart(void) { CCS_SendPacket(CMD_M2E_START, NULL, 0); } static void CCS_CalculateEnergy(void) { 800c578: b580 push {r7, lr} 800c57a: b082 sub sp, #8 800c57c: af00 add r7, sp, #0 static uint32_t lastTick = 0; uint32_t currentTick = HAL_GetTick(); 800c57e: f001 fedb bl 800e338 800c582: 6078 str r0, [r7, #4] uint32_t elapsedTimeMs = currentTick - lastTick; 800c584: 4b1e ldr r3, [pc, #120] @ (800c600 ) 800c586: 681b ldr r3, [r3, #0] 800c588: 687a ldr r2, [r7, #4] 800c58a: 1ad3 subs r3, r2, r3 800c58c: 603b str r3, [r7, #0] lastTick = currentTick; 800c58e: 4a1c ldr r2, [pc, #112] @ (800c600 ) 800c590: 687b ldr r3, [r7, #4] 800c592: 6013 str r3, [r2, #0] CCS_Power = CONN.MeasuredVoltage * CONN.MeasuredCurrent / 10; 800c594: 4b1b ldr r3, [pc, #108] @ (800c604 ) 800c596: f8b3 3013 ldrh.w r3, [r3, #19] 800c59a: b29b uxth r3, r3 800c59c: 461a mov r2, r3 800c59e: 4b19 ldr r3, [pc, #100] @ (800c604 ) 800c5a0: f8b3 3015 ldrh.w r3, [r3, #21] 800c5a4: b29b uxth r3, r3 800c5a6: fb02 f303 mul.w r3, r2, r3 800c5aa: 4a17 ldr r2, [pc, #92] @ (800c608 ) 800c5ac: fb82 1203 smull r1, r2, r2, r3 800c5b0: 1092 asrs r2, r2, #2 800c5b2: 17db asrs r3, r3, #31 800c5b4: 1ad3 subs r3, r2, r3 800c5b6: 461a mov r2, r3 800c5b8: 4b14 ldr r3, [pc, #80] @ (800c60c ) 800c5ba: 601a str r2, [r3, #0] CCS_EnergyWs += (CCS_Power * elapsedTimeMs) / 1000; 800c5bc: 4b13 ldr r3, [pc, #76] @ (800c60c ) 800c5be: 681b ldr r3, [r3, #0] 800c5c0: 683a ldr r2, [r7, #0] 800c5c2: fb02 f303 mul.w r3, r2, r3 800c5c6: 4a12 ldr r2, [pc, #72] @ (800c610 ) 800c5c8: fba2 2303 umull r2, r3, r2, r3 800c5cc: 099a lsrs r2, r3, #6 800c5ce: 4b11 ldr r3, [pc, #68] @ (800c614 ) 800c5d0: 681b ldr r3, [r3, #0] 800c5d2: 4413 add r3, r2 800c5d4: 4a0f ldr r2, [pc, #60] @ (800c614 ) 800c5d6: 6013 str r3, [r2, #0] if(CCS_EvseState == Unplugged) { 800c5d8: 4b0f ldr r3, [pc, #60] @ (800c618 ) 800c5da: 781b ldrb r3, [r3, #0] 800c5dc: 2b01 cmp r3, #1 800c5de: d102 bne.n 800c5e6 CCS_EnergyWs = 0; 800c5e0: 4b0c ldr r3, [pc, #48] @ (800c614 ) 800c5e2: 2200 movs r2, #0 800c5e4: 601a str r2, [r3, #0] } CCS_Energy = CCS_EnergyWs / 3600; 800c5e6: 4b0b ldr r3, [pc, #44] @ (800c614 ) 800c5e8: 681b ldr r3, [r3, #0] 800c5ea: 4a0c ldr r2, [pc, #48] @ (800c61c ) 800c5ec: fba2 2303 umull r2, r3, r2, r3 800c5f0: 0adb lsrs r3, r3, #11 800c5f2: 4a0b ldr r2, [pc, #44] @ (800c620 ) 800c5f4: 6013 str r3, [r2, #0] } 800c5f6: bf00 nop 800c5f8: 3708 adds r7, #8 800c5fa: 46bd mov sp, r7 800c5fc: bd80 pop {r7, pc} 800c5fe: bf00 nop 800c600: 20000d28 .word 0x20000d28 800c604: 200003b0 .word 0x200003b0 800c608: 66666667 .word 0x66666667 800c60c: 20000994 .word 0x20000994 800c610: 10624dd3 .word 0x10624dd3 800c614: 20000998 .word 0x20000998 800c618: 20000d10 .word 0x20000d10 800c61c: 91a2b3c5 .word 0x91a2b3c5 800c620: 2000099c .word 0x2000099c 0800c624 : static void send_state(void) { 800c624: b580 push {r7, lr} 800c626: af00 add r7, sp, #0 CCS_CalculateEnergy(); 800c628: f7ff ffa6 bl 800c578 CCS_State.DutyCycle = CP_GetDuty(); 800c62c: f7fd fd78 bl 800a120 800c630: 4603 mov r3, r0 800c632: 461a mov r2, r3 800c634: 4b2e ldr r3, [pc, #184] @ (800c6f0 ) 800c636: 701a strb r2, [r3, #0] CCS_State.OutputEnabled = PSU0.CONT_enabled; 800c638: 4b2e ldr r3, [pc, #184] @ (800c6f4 ) 800c63a: 7ada ldrb r2, [r3, #11] 800c63c: 4b2c ldr r3, [pc, #176] @ (800c6f0 ) 800c63e: 705a strb r2, [r3, #1] CCS_State.MeasuredVoltage = (uint16_t)CONN.MeasuredVoltage; 800c640: 4b2d ldr r3, [pc, #180] @ (800c6f8 ) 800c642: f8b3 3013 ldrh.w r3, [r3, #19] 800c646: b29a uxth r2, r3 800c648: 4b29 ldr r3, [pc, #164] @ (800c6f0 ) 800c64a: 805a strh r2, [r3, #2] if (fake_500_voltage_mode) { 800c64c: 4b2b ldr r3, [pc, #172] @ (800c6fc ) 800c64e: 781b ldrb r3, [r3, #0] 800c650: 2b00 cmp r3, #0 800c652: d003 beq.n 800c65c CCS_State.MeasuredVoltage = FAKE_EVREQ_VOLTAGE_V; 800c654: 4b26 ldr r3, [pc, #152] @ (800c6f0 ) 800c656: f44f 72fa mov.w r2, #500 @ 0x1f4 800c65a: 805a strh r2, [r3, #2] } CCS_State.MeasuredCurrent = (uint16_t)CONN.MeasuredCurrent; 800c65c: 4b26 ldr r3, [pc, #152] @ (800c6f8 ) 800c65e: f8b3 3015 ldrh.w r3, [r3, #21] 800c662: b29a uxth r2, r3 800c664: 4b22 ldr r3, [pc, #136] @ (800c6f0 ) 800c666: 809a strh r2, [r3, #4] CCS_State.Power = CCS_Power; 800c668: 4b25 ldr r3, [pc, #148] @ (800c700 ) 800c66a: 681b ldr r3, [r3, #0] 800c66c: 4a20 ldr r2, [pc, #128] @ (800c6f0 ) 800c66e: f8c2 3006 str.w r3, [r2, #6] CCS_State.Energy = CCS_Energy; 800c672: 4b24 ldr r3, [pc, #144] @ (800c704 ) 800c674: 681b ldr r3, [r3, #0] 800c676: 4a1e ldr r2, [pc, #120] @ (800c6f0 ) 800c678: f8c2 300a str.w r3, [r2, #10] if(CCS_ConnectorState == CCS_CONNECTED){ 800c67c: 4b22 ldr r3, [pc, #136] @ (800c708 ) 800c67e: 781b ldrb r3, [r3, #0] 800c680: 2b04 cmp r3, #4 800c682: d104 bne.n 800c68e CCS_State.CpState = cp_state_buffer; 800c684: 4b21 ldr r3, [pc, #132] @ (800c70c ) 800c686: 781a ldrb r2, [r3, #0] 800c688: 4b19 ldr r3, [pc, #100] @ (800c6f0 ) 800c68a: 74da strb r2, [r3, #19] 800c68c: e002 b.n 800c694 } else { CCS_State.CpState = EV_STATE_A_IDLE; 800c68e: 4b18 ldr r3, [pc, #96] @ (800c6f0 ) 800c690: 2200 movs r2, #0 800c692: 74da strb r2, [r3, #19] } CCS_State.MaxVoltage = CCS_MaxLoad.maxVoltage; 800c694: 4b1e ldr r3, [pc, #120] @ (800c710 ) 800c696: 881a ldrh r2, [r3, #0] 800c698: 4b15 ldr r3, [pc, #84] @ (800c6f0 ) 800c69a: 829a strh r2, [r3, #20] CCS_State.MinVoltage = CCS_MaxLoad.minVoltage; 800c69c: 4b1c ldr r3, [pc, #112] @ (800c710 ) 800c69e: 885a ldrh r2, [r3, #2] 800c6a0: 4b13 ldr r3, [pc, #76] @ (800c6f0 ) 800c6a2: 82da strh r2, [r3, #22] CCS_State.MaxCurrent = CCS_MaxLoad.maxCurrent; 800c6a4: 4b1a ldr r3, [pc, #104] @ (800c710 ) 800c6a6: 889a ldrh r2, [r3, #4] 800c6a8: 4b11 ldr r3, [pc, #68] @ (800c6f0 ) 800c6aa: 831a strh r2, [r3, #24] CCS_State.MinCurrent = CCS_MaxLoad.minCurrent; 800c6ac: 4b18 ldr r3, [pc, #96] @ (800c710 ) 800c6ae: 88da ldrh r2, [r3, #6] 800c6b0: 4b0f ldr r3, [pc, #60] @ (800c6f0 ) 800c6b2: 835a strh r2, [r3, #26] CCS_State.MaxPower = CCS_MaxLoad.maxPower; 800c6b4: 4b16 ldr r3, [pc, #88] @ (800c710 ) 800c6b6: 689b ldr r3, [r3, #8] 800c6b8: 4a0d ldr r2, [pc, #52] @ (800c6f0 ) 800c6ba: 61d3 str r3, [r2, #28] CCS_State.IsolationValid = isolation_enable; 800c6bc: 4b15 ldr r3, [pc, #84] @ (800c714 ) 800c6be: 781a ldrb r2, [r3, #0] 800c6c0: 4b0b ldr r3, [pc, #44] @ (800c6f0 ) 800c6c2: 749a strb r2, [r3, #18] CCS_State.IsolationResistance = 900000; 800c6c4: 4a0a ldr r2, [pc, #40] @ (800c6f0 ) 800c6c6: 2300 movs r3, #0 800c6c8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800c6cc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800c6d0: f443 433b orr.w r3, r3, #47872 @ 0xbb00 800c6d4: f043 03a0 orr.w r3, r3, #160 @ 0xa0 800c6d8: 81d3 strh r3, [r2, #14] 800c6da: 2300 movs r3, #0 800c6dc: f043 030d orr.w r3, r3, #13 800c6e0: 8213 strh r3, [r2, #16] CCS_SendPacket(CMD_M2E_STATE, &CCS_State, sizeof(CCS_State)); 800c6e2: 2220 movs r2, #32 800c6e4: 4902 ldr r1, [pc, #8] @ (800c6f0 ) 800c6e6: 2050 movs r0, #80 @ 0x50 800c6e8: f7ff fee4 bl 800c4b4 } 800c6ec: bf00 nop 800c6ee: bd80 pop {r7, pc} 800c6f0: 20000cc4 .word 0x20000cc4 800c6f4: 20000904 .word 0x20000904 800c6f8: 200003b0 .word 0x200003b0 800c6fc: 20000cb8 .word 0x20000cb8 800c700: 20000994 .word 0x20000994 800c704: 2000099c .word 0x2000099c 800c708: 20000d11 .word 0x20000d11 800c70c: 20000005 .word 0x20000005 800c710: 20000988 .word 0x20000988 800c714: 20000cb2 .word 0x20000cb2 0800c718 : ISR_FAST static uint16_t expected_payload_len(uint8_t cmd) { switch (cmd) { 800c718: 3840 subs r0, #64 @ 0x40 800c71a: b2c0 uxtb r0, r0 800c71c: 2809 cmp r0, #9 800c71e: bf9a itte ls 800c720: 4b02 ldrls r3, [pc, #8] @ (800c72c ) 800c722: f833 0010 ldrhls.w r0, [r3, r0, lsl #1] ISR_FAST static uint16_t expected_payload_len(uint8_t cmd) { 800c726: f64f 70ff movwhi r0, #65535 @ 0xffff case CMD_E2M_EV_INFO: return sizeof(CCS_EvInfo_t); case CMD_E2M_EVSE_STATE: return sizeof(CONN_State_t); case CMD_E2M_KEEP_ALIVE: return 0; default: return 0xFFFFu; } } 800c72a: 4770 bx lr 800c72c: 080178e8 .word 0x080178e8 0800c730 : ISR_FAST static void apply_command(uint8_t cmd, const uint8_t* payload, uint16_t payload_len) { 800c730: b5f8 push {r3, r4, r5, r6, r7, lr} 800c732: 4604 mov r4, r0 800c734: 460d mov r5, r1 (void)payload_len; last_host_seen = HAL_GetTick(); 800c736: f001 fdff bl 800e338 everest_timed_out = 0; 800c73a: 2300 movs r3, #0 800c73c: 4a42 ldr r2, [pc, #264] @ (800c848 ) last_host_seen = HAL_GetTick(); 800c73e: 4e43 ldr r6, [pc, #268] @ (800c84c ) everest_timed_out = 0; 800c740: 7013 strb r3, [r2, #0] everest_timeout_warn_latched = 0; 800c742: 4a43 ldr r2, [pc, #268] @ (800c850 ) last_host_seen = HAL_GetTick(); 800c744: 6030 str r0, [r6, #0] everest_timeout_warn_latched = 0; 800c746: 7013 strb r3, [r2, #0] everest_timeout_stop_latched = 0; 800c748: 4a42 ldr r2, [pc, #264] @ (800c854 ) 800c74a: 7013 strb r3, [r2, #0] switch (cmd) { 800c74c: f1a4 0340 sub.w r3, r4, #64 @ 0x40 800c750: 2b09 cmp r3, #9 800c752: d871 bhi.n 800c838 800c754: e8df f003 tbb [pc, r3] 800c758: 4e5b1409 .word 0x4e5b1409 800c75c: 2e2a1b55 .word 0x2e2a1b55 800c760: 054a .short 0x054a (void)payload; CP_SetDuty(pwm_duty_percent); break; } case CMD_E2M_KEEP_ALIVE: { last_host_seen = HAL_GetTick(); 800c762: f001 fde9 bl 800e338 800c766: 6030 str r0, [r6, #0] log_printf(LOG_WARN, "UART3 RX warn: cmd 0x%02x CRC/len OK but no switch case (expected_payload vs apply_command)\n", cmd); break; } } 800c768: bdf8 pop {r3, r4, r5, r6, r7, pc} if (duty > 100) duty = 100; 800c76a: 7828 ldrb r0, [r5, #0] if (CONN.connControl != CMD_FORCE_UNLOCK) { 800c76c: 4b3a ldr r3, [pc, #232] @ (800c858 ) if (duty > 100) duty = 100; 800c76e: 2864 cmp r0, #100 @ 0x64 800c770: bf28 it cs 800c772: 2064 movcs r0, #100 @ 0x64 if (CONN.connControl != CMD_FORCE_UNLOCK) { 800c774: 781b ldrb r3, [r3, #0] pwm_duty_percent = duty; 800c776: 4a39 ldr r2, [pc, #228] @ (800c85c ) if (CONN.connControl != CMD_FORCE_UNLOCK) { 800c778: 2b03 cmp r3, #3 pwm_duty_percent = duty; 800c77a: 7010 strb r0, [r2, #0] if (CONN.connControl != CMD_FORCE_UNLOCK) { 800c77c: d143 bne.n 800c806 } 800c77e: bdf8 pop {r3, r4, r5, r6, r7, pc} ev_enable_output = (p->enable_output != 0); 800c780: 782b ldrb r3, [r5, #0] 800c782: 4a37 ldr r2, [pc, #220] @ (800c860 ) 800c784: 3b00 subs r3, #0 800c786: bf18 it ne 800c788: 2301 movne r3, #1 800c78a: 7013 strb r3, [r2, #0] } 800c78c: bdf8 pop {r3, r4, r5, r6, r7, pc} if (p->voltage_V == FAKE_EVREQ_VOLTAGE_V) { 800c78e: 882b ldrh r3, [r5, #0] 800c790: b29a uxth r2, r3 800c792: f5b2 7ffa cmp.w r2, #500 @ 0x1f4 800c796: d043 beq.n 800c820 fake_500_voltage_mode = 0u; 800c798: 2000 movs r0, #0 CONN.RequestedVoltage = p->voltage_V; 800c79a: 4a2f ldr r2, [pc, #188] @ (800c858 ) fake_500_voltage_mode = 0u; 800c79c: 4931 ldr r1, [pc, #196] @ (800c864 ) CONN.RequestedVoltage = p->voltage_V; 800c79e: f8a2 300f strh.w r3, [r2, #15] fake_500_voltage_mode = 0u; 800c7a2: 7008 strb r0, [r1, #0] CONN.WantedCurrent = p->current_0p1A; 800c7a4: 886b ldrh r3, [r5, #2] 800c7a6: f8a2 301b strh.w r3, [r2, #27] } 800c7aa: bdf8 pop {r3, r4, r5, r6, r7, pc} isolation_enable = p->command; 800c7ac: 782a ldrb r2, [r5, #0] 800c7ae: 4b2e ldr r3, [pc, #184] @ (800c868 ) 800c7b0: 701a strb r2, [r3, #0] } 800c7b2: bdf8 pop {r3, r4, r5, r6, r7, pc} memcpy(&CCS_EvInfo, payload, sizeof(CCS_EvInfo_t)); 800c7b4: 4f2d ldr r7, [pc, #180] @ (800c86c ) 800c7b6: 462c mov r4, r5 800c7b8: 463e mov r6, r7 800c7ba: f105 0c20 add.w ip, r5, #32 800c7be: 4635 mov r5, r6 800c7c0: 6820 ldr r0, [r4, #0] 800c7c2: 6861 ldr r1, [r4, #4] 800c7c4: 68a2 ldr r2, [r4, #8] 800c7c6: 68e3 ldr r3, [r4, #12] 800c7c8: 3410 adds r4, #16 800c7ca: 4564 cmp r4, ip 800c7cc: c50f stmia r5!, {r0, r1, r2, r3} 800c7ce: f106 0610 add.w r6, r6, #16 800c7d2: d1f4 bne.n 800c7be 800c7d4: 6861 ldr r1, [r4, #4] 800c7d6: 68a2 ldr r2, [r4, #8] 800c7d8: 6820 ldr r0, [r4, #0] 800c7da: c607 stmia r6!, {r0, r1, r2} CONN.SOC = (uint8_t)(CCS_EvInfo.soc / 10); 800c7dc: 4a24 ldr r2, [pc, #144] @ (800c870 ) 800c7de: 887b ldrh r3, [r7, #2] 800c7e0: 491d ldr r1, [pc, #116] @ (800c858 ) 800c7e2: fba2 2303 umull r2, r3, r2, r3 800c7e6: 08db lsrs r3, r3, #3 800c7e8: 708b strb r3, [r1, #2] } 800c7ea: bdf8 pop {r3, r4, r5, r6, r7, pc} CCS_EvseState = (CONN_State_t)payload[0]; 800c7ec: 782a ldrb r2, [r5, #0] 800c7ee: 4b21 ldr r3, [pc, #132] @ (800c874 ) 800c7f0: 701a strb r2, [r3, #0] } 800c7f2: bdf8 pop {r3, r4, r5, r6, r7, pc} enabled = (p->enable != 0); 800c7f4: 782b ldrb r3, [r5, #0] 800c7f6: 4a20 ldr r2, [pc, #128] @ (800c878 ) 800c7f8: 3b00 subs r3, #0 800c7fa: bf18 it ne 800c7fc: 2301 movne r3, #1 800c7fe: 7013 strb r3, [r2, #0] } 800c800: bdf8 pop {r3, r4, r5, r6, r7, pc} CP_SetDuty(pwm_duty_percent); 800c802: 4b16 ldr r3, [pc, #88] @ (800c85c ) 800c804: 7818 ldrb r0, [r3, #0] } 800c806: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} CP_SetDuty(pwm_duty_percent); 800c80a: f7fd bc61 b.w 800a0d0 if (p->reset) { 800c80e: 782b ldrb r3, [r5, #0] 800c810: 2b00 cmp r3, #0 800c812: d0a9 beq.n 800c768 } 800c814: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} log_printf(LOG_WARN, "Everest reset command\n"); 800c818: 2005 movs r0, #5 800c81a: 4918 ldr r1, [pc, #96] @ (800c87c ) 800c81c: f7fd be9a b.w 800a554 fake_500_voltage_mode = 1u; 800c820: 2201 movs r2, #1 CONN.RequestedVoltage = FAKE_PSU_VOLTAGE_V; 800c822: 2100 movs r1, #0 800c824: 242c movs r4, #44 @ 0x2c CONN.WantedCurrent = FAKE_PSU_CURRENT_0P1A; 800c826: 200a movs r0, #10 fake_500_voltage_mode = 1u; 800c828: 4d0e ldr r5, [pc, #56] @ (800c864 ) CONN.RequestedVoltage = FAKE_PSU_VOLTAGE_V; 800c82a: 4b0b ldr r3, [pc, #44] @ (800c858 ) fake_500_voltage_mode = 1u; 800c82c: 702a strb r2, [r5, #0] CONN.RequestedVoltage = FAKE_PSU_VOLTAGE_V; 800c82e: 741a strb r2, [r3, #16] 800c830: 73dc strb r4, [r3, #15] CONN.WantedCurrent = FAKE_PSU_CURRENT_0P1A; 800c832: 76d8 strb r0, [r3, #27] 800c834: 7719 strb r1, [r3, #28] } 800c836: bdf8 pop {r3, r4, r5, r6, r7, pc} log_printf(LOG_WARN, 800c838: 4622 mov r2, r4 } 800c83a: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} log_printf(LOG_WARN, 800c83e: 2005 movs r0, #5 800c840: 490f ldr r1, [pc, #60] @ (800c880 ) 800c842: f7fd be87 b.w 800a554 800c846: bf00 nop 800c848: 20000cb9 .word 0x20000cb9 800c84c: 20000cb4 .word 0x20000cb4 800c850: 20000cba .word 0x20000cba 800c854: 20000cbb .word 0x20000cbb 800c858: 200003b0 .word 0x200003b0 800c85c: 2000006a .word 0x2000006a 800c860: 200009a9 .word 0x200009a9 800c864: 20000cb8 .word 0x20000cb8 800c868: 20000cb2 .word 0x20000cb2 800c86c: 20000ce4 .word 0x20000ce4 800c870: cccccccd .word 0xcccccccd 800c874: 20000d10 .word 0x20000d10 800c878: 20000cb1 .word 0x20000cb1 800c87c: 080174d4 .word 0x080174d4 800c880: 080174ec .word 0x080174ec 0800c884 : ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len) { 800c884: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} if (packet_len < 3u) { 800c888: 2902 cmp r1, #2 ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len) { 800c88a: 460c mov r4, r1 800c88c: 4605 mov r5, r0 800c88e: b084 sub sp, #16 if (packet_len < 3u) { 800c890: d930 bls.n 800c8f4 uint8_t cmd = packet[0]; uint16_t payload_len = (uint16_t)(packet_len - 3u); uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | (uint16_t)packet[packet_len - 1u] << 8; 800c892: 1843 adds r3, r0, r1 uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c894: f813 2c01 ldrb.w r2, [r3, #-1] 800c898: f813 7c02 ldrb.w r7, [r3, #-2] uint16_t payload_len = (uint16_t)(packet_len - 3u); 800c89c: 1ece subs r6, r1, #3 uint16_t calculated_crc = crc16_ibm(packet, (uint16_t)(1u + payload_len)); 800c89e: 3902 subs r1, #2 800c8a0: b289 uxth r1, r1 uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c8a2: ea47 2702 orr.w r7, r7, r2, lsl #8 uint8_t cmd = packet[0]; 800c8a6: f890 8000 ldrb.w r8, [r0] uint16_t calculated_crc = crc16_ibm(packet, (uint16_t)(1u + payload_len)); 800c8aa: f7ff fd7f bl 800c3ac if (received_crc != calculated_crc) { 800c8ae: 4287 cmp r7, r0 uint16_t payload_len = (uint16_t)(packet_len - 3u); 800c8b0: b2b6 uxth r6, r6 if (received_crc != calculated_crc) { 800c8b2: d112 bne.n 800c8da cmd, (unsigned)packet_len, (unsigned)payload_len, (unsigned)received_crc, (unsigned)calculated_crc); return 0; } uint16_t expected_len = expected_payload_len(cmd); 800c8b4: 4640 mov r0, r8 800c8b6: f7ff ff2f bl 800c718 if (expected_len == 0xFFFFu) { 800c8ba: f64f 72ff movw r2, #65535 @ 0xffff 800c8be: 4290 cmp r0, r2 800c8c0: d03a beq.n 800c938 log_printf(LOG_WARN, "UART3 RX drop: unknown_cmd cmd=0x%02x total_len=%u payload_len=%u\n", cmd, (unsigned)packet_len, (unsigned)payload_len); return 0; } if (expected_len != payload_len) { 800c8c2: 4286 cmp r6, r0 800c8c4: d12a bne.n 800c91c cmd, (unsigned)expected_len, (unsigned)payload_len, (unsigned)packet_len); return 0; } if (payload_len > 0) { apply_command(cmd, &packet[1], payload_len); 800c8c6: 4632 mov r2, r6 if (payload_len > 0) { 800c8c8: b9fe cbnz r6, 800c90a } else { apply_command(cmd, NULL, 0); 800c8ca: 4631 mov r1, r6 800c8cc: 4640 mov r0, r8 800c8ce: f7ff ff2f bl 800c730 } return 1; 800c8d2: 2001 movs r0, #1 } 800c8d4: b004 add sp, #16 800c8d6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} log_printf(LOG_ERR, 800c8da: 9002 str r0, [sp, #8] 800c8dc: 4623 mov r3, r4 800c8de: 4642 mov r2, r8 800c8e0: 2004 movs r0, #4 800c8e2: e9cd 6700 strd r6, r7, [sp] 800c8e6: 4918 ldr r1, [pc, #96] @ (800c948 ) 800c8e8: f7fd fe34 bl 800a554 return 0; 800c8ec: 2000 movs r0, #0 } 800c8ee: b004 add sp, #16 800c8f0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} if (packet_len == 0u) { 800c8f4: b1d9 cbz r1, 800c92e } else if (packet_len == 1u) { 800c8f6: 2901 cmp r1, #1 log_printf(LOG_WARN, "UART3 RX drop: too_short len=1 b0=0x%02x\n", packet[0]); 800c8f8: 7802 ldrb r2, [r0, #0] 800c8fa: f04f 0005 mov.w r0, #5 } else if (packet_len == 1u) { 800c8fe: d009 beq.n 800c914 log_printf(LOG_WARN, "UART3 RX drop: too_short len=2 b0=0x%02x b1=0x%02x\n", 800c900: 786b ldrb r3, [r5, #1] 800c902: 4912 ldr r1, [pc, #72] @ (800c94c ) 800c904: f7fd fe26 bl 800a554 800c908: e7f0 b.n 800c8ec apply_command(cmd, &packet[1], payload_len); 800c90a: 4640 mov r0, r8 800c90c: 1c69 adds r1, r5, #1 800c90e: f7ff ff0f bl 800c730 800c912: e7de b.n 800c8d2 log_printf(LOG_WARN, "UART3 RX drop: too_short len=1 b0=0x%02x\n", packet[0]); 800c914: 490e ldr r1, [pc, #56] @ (800c950 ) 800c916: f7fd fe1d bl 800a554 800c91a: e7e7 b.n 800c8ec log_printf(LOG_ERR, 800c91c: 4603 mov r3, r0 800c91e: 4642 mov r2, r8 800c920: e9cd 6400 strd r6, r4, [sp] 800c924: 490b ldr r1, [pc, #44] @ (800c954 ) 800c926: 2004 movs r0, #4 800c928: f7fd fe14 bl 800a554 return 0; 800c92c: e7de b.n 800c8ec log_printf(LOG_WARN, "UART3 RX drop: too_short len=0 (empty chunk)\n"); 800c92e: 490a ldr r1, [pc, #40] @ (800c958 ) 800c930: 2005 movs r0, #5 800c932: f7fd fe0f bl 800a554 800c936: e7d9 b.n 800c8ec log_printf(LOG_WARN, 800c938: 4623 mov r3, r4 800c93a: 4642 mov r2, r8 800c93c: 4907 ldr r1, [pc, #28] @ (800c95c ) 800c93e: 9600 str r6, [sp, #0] 800c940: 2005 movs r0, #5 800c942: f7fd fe07 bl 800a554 return 0; 800c946: e7d1 b.n 800c8ec 800c948: 080175dc .word 0x080175dc 800c94c: 080175a8 .word 0x080175a8 800c950: 0801757c .word 0x0801757c 800c954: 08017684 .word 0x08017684 800c958: 0801754c .word 0x0801754c 800c95c: 08017640 .word 0x08017640 0800c960 : static void CCS_UART3_Watchdog(void) { 800c960: b580 push {r7, lr} 800c962: b082 sub sp, #8 800c964: af00 add r7, sp, #0 const int32_t since_last_packet = (int32_t)(HAL_GetTick() - uart3_last_packet_tick); 800c966: f001 fce7 bl 800e338 800c96a: 4602 mov r2, r0 800c96c: 4b14 ldr r3, [pc, #80] @ (800c9c0 ) 800c96e: 681b ldr r3, [r3, #0] 800c970: 1ad3 subs r3, r2, r3 800c972: 607b str r3, [r7, #4] const int32_t since_last_reinit = (int32_t)(HAL_GetTick() - uart3_last_reinit_tick); 800c974: f001 fce0 bl 800e338 800c978: 4602 mov r2, r0 800c97a: 4b12 ldr r3, [pc, #72] @ (800c9c4 ) 800c97c: 681b ldr r3, [r3, #0] 800c97e: 1ad3 subs r3, r2, r3 800c980: 603b str r3, [r7, #0] if ((since_last_packet >= (int32_t)UART3_REINIT_TIMEOUT_MS) && 800c982: 687b ldr r3, [r7, #4] 800c984: f240 52db movw r2, #1499 @ 0x5db 800c988: 4293 cmp r3, r2 800c98a: dd15 ble.n 800c9b8 800c98c: 683b ldr r3, [r7, #0] 800c98e: f240 52db movw r2, #1499 @ 0x5db 800c992: 4293 cmp r3, r2 800c994: dd10 ble.n 800c9b8 (since_last_reinit >= (int32_t)UART3_REINIT_TIMEOUT_MS) && (huart3.RxState == HAL_UART_STATE_READY)) { 800c996: 4b0c ldr r3, [pc, #48] @ (800c9c8 ) 800c998: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800c99c: b2db uxtb r3, r3 (since_last_reinit >= (int32_t)UART3_REINIT_TIMEOUT_MS) && 800c99e: 2b20 cmp r3, #32 800c9a0: d10a bne.n 800c9b8 uart3_arm_rx_or_log("Watchdog"); 800c9a2: 480a ldr r0, [pc, #40] @ (800c9cc ) 800c9a4: f7ff f91a bl 800bbdc CCS_LogUart3Error("UART3 watchdog rearm"); 800c9a8: 4809 ldr r0, [pc, #36] @ (800c9d0 ) 800c9aa: f000 f813 bl 800c9d4 uart3_last_reinit_tick = HAL_GetTick(); 800c9ae: f001 fcc3 bl 800e338 800c9b2: 4603 mov r3, r0 800c9b4: 4a03 ldr r2, [pc, #12] @ (800c9c4 ) 800c9b6: 6013 str r3, [r2, #0] } } 800c9b8: bf00 nop 800c9ba: 3708 adds r7, #8 800c9bc: 46bd mov sp, r7 800c9be: bd80 pop {r7, pc} 800c9c0: 20000cbc .word 0x20000cbc 800c9c4: 20000cc0 .word 0x20000cc0 800c9c8: 20001330 .word 0x20001330 800c9cc: 080176dc .word 0x080176dc 800c9d0: 080176e8 .word 0x080176e8 0800c9d4 : static void CCS_LogUart3Error(const char *tag) { 800c9d4: b580 push {r7, lr} 800c9d6: b086 sub sp, #24 800c9d8: af04 add r7, sp, #16 800c9da: 6078 str r0, [r7, #4] log_printf(LOG_ERR, "%s: err=0x%08lx g=%lu rx=%lu tx_busy=%u\n", tag, (unsigned long)HAL_UART_GetError(&huart3), 800c9dc: 480d ldr r0, [pc, #52] @ (800ca14 ) 800c9de: f006 ff86 bl 80138ee 800c9e2: 4603 mov r3, r0 (unsigned long)huart3.gState, 800c9e4: 4a0b ldr r2, [pc, #44] @ (800ca14 ) 800c9e6: f892 2041 ldrb.w r2, [r2, #65] @ 0x41 800c9ea: b2d2 uxtb r2, r2 log_printf(LOG_ERR, "%s: err=0x%08lx g=%lu rx=%lu tx_busy=%u\n", 800c9ec: 4611 mov r1, r2 (unsigned long)huart3.RxState, 800c9ee: 4a09 ldr r2, [pc, #36] @ (800ca14 ) 800c9f0: f892 2042 ldrb.w r2, [r2, #66] @ 0x42 800c9f4: b2d2 uxtb r2, r2 log_printf(LOG_ERR, "%s: err=0x%08lx g=%lu rx=%lu tx_busy=%u\n", 800c9f6: 4610 mov r0, r2 800c9f8: 4a07 ldr r2, [pc, #28] @ (800ca18 ) 800c9fa: 7812 ldrb r2, [r2, #0] 800c9fc: 9202 str r2, [sp, #8] 800c9fe: 9001 str r0, [sp, #4] 800ca00: 9100 str r1, [sp, #0] 800ca02: 687a ldr r2, [r7, #4] 800ca04: 4905 ldr r1, [pc, #20] @ (800ca1c ) 800ca06: 2004 movs r0, #4 800ca08: f7fd fda4 bl 800a554 (unsigned)uart3_tx_busy); } 800ca0c: bf00 nop 800ca0e: 3708 adds r7, #8 800ca10: 46bd mov sp, r7 800ca12: bd80 pop {r7, pc} 800ca14: 20001330 .word 0x20001330 800ca18: 20000cae .word 0x20000cae 800ca1c: 08017700 .word 0x08017700 0800ca20 : .fw_version_major = 0, .fw_version_minor = 0, .fw_version_patch = 0, }; void ReadVersion(){ 800ca20: b480 push {r7} 800ca22: af00 add r7, sp, #0 infoPacket.serialNumber = InfoBlock->serialNumber; 800ca24: 4b0e ldr r3, [pc, #56] @ (800ca60 ) 800ca26: 681b ldr r3, [r3, #0] 800ca28: 681b ldr r3, [r3, #0] 800ca2a: b29a uxth r2, r3 800ca2c: 4b0d ldr r3, [pc, #52] @ (800ca64 ) 800ca2e: 801a strh r2, [r3, #0] infoPacket.boardVersion = InfoBlock->boardVersion; 800ca30: 4b0b ldr r3, [pc, #44] @ (800ca60 ) 800ca32: 681b ldr r3, [r3, #0] 800ca34: 795a ldrb r2, [r3, #5] 800ca36: 4b0b ldr r3, [pc, #44] @ (800ca64 ) 800ca38: 709a strb r2, [r3, #2] infoPacket.stationType = InfoBlock->stationType; 800ca3a: 4b09 ldr r3, [pc, #36] @ (800ca60 ) 800ca3c: 681b ldr r3, [r3, #0] 800ca3e: 791a ldrb r2, [r3, #4] 800ca40: 4b08 ldr r3, [pc, #32] @ (800ca64 ) 800ca42: 70da strb r2, [r3, #3] infoPacket.fw_version_major = FW_VERSION_MAJOR; 800ca44: 4b07 ldr r3, [pc, #28] @ (800ca64 ) 800ca46: 2201 movs r2, #1 800ca48: 809a strh r2, [r3, #4] infoPacket.fw_version_minor = FW_VERSION_MINOR; 800ca4a: 4b06 ldr r3, [pc, #24] @ (800ca64 ) 800ca4c: 2200 movs r2, #0 800ca4e: 80da strh r2, [r3, #6] infoPacket.fw_version_patch = FW_VERSION_PATCH; 800ca50: 4b04 ldr r3, [pc, #16] @ (800ca64 ) 800ca52: 2211 movs r2, #17 800ca54: 811a strh r2, [r3, #8] } 800ca56: bf00 nop 800ca58: 46bd mov sp, r7 800ca5a: bc80 pop {r7} 800ca5c: 4770 bx lr 800ca5e: bf00 nop 800ca60: 20000000 .word 0x20000000 800ca64: 200011b0 .word 0x200011b0 0800ca68 : // Внешняя функция обработки команд (определена в serial_handler.c) extern void SC_CommandHandler(ReceivedCommand_t* cmd); void SC_Init() { 800ca68: b580 push {r7, lr} 800ca6a: af00 add r7, sp, #0 // Обнуляем структуру memset(&serial_control, 0, sizeof(SerialControl_t)); 800ca6c: f44f 7204 mov.w r2, #528 @ 0x210 800ca70: 2100 movs r1, #0 800ca72: 480d ldr r0, [pc, #52] @ (800caa8 ) 800ca74: f008 f91a bl 8014cac memset(&serial_iso, 0, sizeof(serial_iso)); 800ca78: f44f 7204 mov.w r2, #528 @ 0x210 800ca7c: 2100 movs r1, #0 800ca7e: 480b ldr r0, [pc, #44] @ (800caac ) 800ca80: f008 f914 bl 8014cac sc_uart2_timed_out = 0; 800ca84: 4b0a ldr r3, [pc, #40] @ (800cab0 ) 800ca86: 2200 movs r2, #0 800ca88: 701a strb r2, [r3, #0] sc_uart2_last_packet_tick = HAL_GetTick(); 800ca8a: f001 fc55 bl 800e338 800ca8e: 4603 mov r3, r0 800ca90: 4a08 ldr r2, [pc, #32] @ (800cab4 ) 800ca92: 6013 str r3, [r2, #0] sc_uart2_last_recover_tick = sc_uart2_last_packet_tick; 800ca94: 4b07 ldr r3, [pc, #28] @ (800cab4 ) 800ca96: 681b ldr r3, [r3, #0] 800ca98: 4a07 ldr r2, [pc, #28] @ (800cab8 ) 800ca9a: 6013 str r3, [r2, #0] SC_ArmUart2RxDma(); 800ca9c: f000 fa14 bl 800cec8 SC_ArmUart5RxDma(); 800caa0: f000 fa36 bl 800cf10 } 800caa4: bf00 nop 800caa6: bd80 pop {r7, pc} 800caa8: 20000d2c .word 0x20000d2c 800caac: 20000f3c .word 0x20000f3c 800cab0: 2000114d .word 0x2000114d 800cab4: 20001150 .word 0x20001150 800cab8: 20001154 .word 0x20001154 0800cabc : void SC_Task() { 800cabc: b580 push {r7, lr} 800cabe: af00 add r7, sp, #0 static uint32_t tick; if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800cac0: f001 fc3a bl 800e338 800cac4: 4602 mov r2, r0 800cac6: 4b21 ldr r3, [pc, #132] @ (800cb4c ) 800cac8: 681b ldr r3, [r3, #0] 800caca: 1ad3 subs r3, r2, r3 800cacc: 2b00 cmp r3, #0 800cace: dd3b ble.n 800cb48 tick = HAL_GetTick(); 800cad0: f001 fc32 bl 800e338 800cad4: 4603 mov r3, r0 800cad6: 4a1d ldr r2, [pc, #116] @ (800cb4c ) 800cad8: 6013 str r3, [r2, #0] SC_UART2_Watchdog(); 800cada: f000 f9ad bl 800ce38 // Запуск приема в режиме DMA + idle SC_ArmUart2RxDma(); 800cade: f000 f9f3 bl 800cec8 SC_ArmUart5RxDma(); 800cae2: f000 fa15 bl 800cf10 // Проверка таймаута отправки пакета (больше 100 мс) if (huart2.gState == HAL_UART_STATE_BUSY_TX && serial_control.tx_tick != 0) { 800cae6: 4b1a ldr r3, [pc, #104] @ (800cb50 ) 800cae8: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800caec: b2db uxtb r3, r3 800caee: 2b21 cmp r3, #33 @ 0x21 800caf0: d114 bne.n 800cb1c 800caf2: 4b18 ldr r3, [pc, #96] @ (800cb54 ) 800caf4: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800caf8: 2b00 cmp r3, #0 800cafa: d00f beq.n 800cb1c if ((int32_t)(HAL_GetTick() - serial_control.tx_tick) > 100) { 800cafc: f001 fc1c bl 800e338 800cb00: 4602 mov r2, r0 800cb02: 4b14 ldr r3, [pc, #80] @ (800cb54 ) 800cb04: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800cb08: 1ad3 subs r3, r2, r3 800cb0a: 2b64 cmp r3, #100 @ 0x64 800cb0c: dd06 ble.n 800cb1c // Таймаут: принудительно сбрасываем передачу (void)HAL_UART_AbortTransmit(&huart2); 800cb0e: 4810 ldr r0, [pc, #64] @ (800cb50 ) 800cb10: f006 fb34 bl 801317c serial_control.tx_tick = 0; // Сбрасываем tick 800cb14: 4b0f ldr r3, [pc, #60] @ (800cb54 ) 800cb16: 2200 movs r2, #0 800cb18: f8c3 220c str.w r2, [r3, #524] @ 0x20c } } // Проверка наличия принятой команды для обработки if (serial_control.command_ready && (huart2.gState != HAL_UART_STATE_BUSY_TX)) { 800cb1c: 4b0d ldr r3, [pc, #52] @ (800cb54 ) 800cb1e: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800cb22: b2db uxtb r3, r3 800cb24: 2b00 cmp r3, #0 800cb26: d010 beq.n 800cb4a 800cb28: 4b09 ldr r3, [pc, #36] @ (800cb50 ) 800cb2a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800cb2e: b2db uxtb r3, r3 800cb30: 2b21 cmp r3, #33 @ 0x21 800cb32: d00a beq.n 800cb4a // HAL_Delay(2); SC_CommandHandler((ReceivedCommand_t*)&serial_control.received_command); 800cb34: 4808 ldr r0, [pc, #32] @ (800cb58 ) 800cb36: f000 fa87 bl 800d048 serial_control.command_ready = 0; // Сбрасываем флаг 800cb3a: 4b06 ldr r3, [pc, #24] @ (800cb54 ) 800cb3c: 2200 movs r2, #0 800cb3e: f883 2208 strb.w r2, [r3, #520] @ 0x208 SC_ArmUart2RxDma(); 800cb42: f000 f9c1 bl 800cec8 800cb46: e000 b.n 800cb4a if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800cb48: bf00 nop } } 800cb4a: bd80 pop {r7, pc} 800cb4c: 200011bc .word 0x200011bc 800cb50: 200012e8 .word 0x200012e8 800cb54: 20000d2c .word 0x20000d2c 800cb58: 20000f2c .word 0x20000f2c 0800cb5c : ISR_FAST void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { if (huart->Instance == huart2.Instance) { 800cb5c: 4b2e ldr r3, [pc, #184] @ (800cc18 ) ISR_FAST void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800cb5e: b570 push {r4, r5, r6, lr} if (huart->Instance == huart2.Instance) { 800cb60: 681a ldr r2, [r3, #0] 800cb62: 6803 ldr r3, [r0, #0] ISR_FAST void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800cb64: 460c mov r4, r1 if (huart->Instance == huart2.Instance) { 800cb66: 4293 cmp r3, r2 800cb68: d019 beq.n 800cb9e log_printf(LOG_WARN, "UART2 RX invalid packet len=%u\n", (unsigned)Size); SC_SendPacket(NULL, 0, RESP_INVALID); } g_sc_command_source = SC_SOURCE_UART2; SC_ArmUart2RxDma(); } else if (huart->Instance == huart5.Instance) { 800cb6a: 4a2c ldr r2, [pc, #176] @ (800cc1c ) 800cb6c: 6812 ldr r2, [r2, #0] 800cb6e: 4293 cmp r3, r2 800cb70: d004 beq.n 800cb7c SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); } else { log_printf(LOG_WARN, "UART5 RX invalid packet len=%u\n", (unsigned)Size); } SC_ArmUart5RxDma(); } else if (huart->Instance == huart3.Instance) { 800cb72: 4a2b ldr r2, [pc, #172] @ (800cc20 ) 800cb74: 6812 ldr r2, [r2, #0] 800cb76: 4293 cmp r3, r2 800cb78: d04a beq.n 800cc10 CCS_RxEventCallback(huart, Size); } } 800cb7a: bd70 pop {r4, r5, r6, pc} if (Size == 0u) { 800cb7c: b399 cbz r1, 800cbe6 if (process_received_packet(&serial_iso, serial_iso.rx_buffer, Size)) { 800cb7e: 4929 ldr r1, [pc, #164] @ (800cc24 ) 800cb80: 4622 mov r2, r4 800cb82: f5a1 7080 sub.w r0, r1, #256 @ 0x100 800cb86: f000 f949 bl 800ce1c 800cb8a: bb10 cbnz r0, 800cbd2 log_printf(LOG_WARN, "UART5 RX invalid packet len=%u\n", (unsigned)Size); 800cb8c: 4622 mov r2, r4 800cb8e: 2005 movs r0, #5 800cb90: 4925 ldr r1, [pc, #148] @ (800cc28 ) 800cb92: f7fd fcdf bl 800a554 } 800cb96: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} SC_ArmUart5RxDma(); 800cb9a: f000 b9b9 b.w 800cf10 if (Size == 0u) { 800cb9e: b391 cbz r1, 800cc06 sc_uart2_last_packet_tick = HAL_GetTick(); 800cba0: f001 fbca bl 800e338 sc_uart2_timed_out = 0; 800cba4: 2200 movs r2, #0 800cba6: 4b21 ldr r3, [pc, #132] @ (800cc2c ) if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800cba8: 4921 ldr r1, [pc, #132] @ (800cc30 ) sc_uart2_timed_out = 0; 800cbaa: 701a strb r2, [r3, #0] sc_uart2_last_packet_tick = HAL_GetTick(); 800cbac: 4603 mov r3, r0 sc_uart2_last_recover_tick = sc_uart2_last_packet_tick; 800cbae: 4d21 ldr r5, [pc, #132] @ (800cc34 ) sc_uart2_last_packet_tick = HAL_GetTick(); 800cbb0: 4e21 ldr r6, [pc, #132] @ (800cc38 ) if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800cbb2: 4622 mov r2, r4 800cbb4: f5a1 7080 sub.w r0, r1, #256 @ 0x100 sc_uart2_last_recover_tick = sc_uart2_last_packet_tick; 800cbb8: 602b str r3, [r5, #0] sc_uart2_last_packet_tick = HAL_GetTick(); 800cbba: 6033 str r3, [r6, #0] if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800cbbc: f000 f92e bl 800ce1c 800cbc0: 4605 mov r5, r0 800cbc2: b1a8 cbz r0, 800cbf0 g_sc_command_source = SC_SOURCE_UART2; 800cbc4: 2200 movs r2, #0 800cbc6: 4b1d ldr r3, [pc, #116] @ (800cc3c ) 800cbc8: 701a strb r2, [r3, #0] } 800cbca: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} SC_ArmUart2RxDma(); 800cbce: f000 b97b b.w 800cec8 g_sc_command_source = SC_SOURCE_UART5; 800cbd2: 2201 movs r2, #1 800cbd4: 4b19 ldr r3, [pc, #100] @ (800cc3c ) SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); 800cbd6: 481a ldr r0, [pc, #104] @ (800cc40 ) g_sc_command_source = SC_SOURCE_UART5; 800cbd8: 701a strb r2, [r3, #0] SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); 800cbda: f000 fa35 bl 800d048 } 800cbde: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} SC_ArmUart5RxDma(); 800cbe2: f000 b995 b.w 800cf10 log_printf(LOG_WARN, "UART5 RX idle event with zero size\n"); 800cbe6: 4917 ldr r1, [pc, #92] @ (800cc44 ) 800cbe8: 2005 movs r0, #5 800cbea: f7fd fcb3 bl 800a554 800cbee: e7c6 b.n 800cb7e log_printf(LOG_WARN, "UART2 RX invalid packet len=%u\n", (unsigned)Size); 800cbf0: 4622 mov r2, r4 800cbf2: 4915 ldr r1, [pc, #84] @ (800cc48 ) 800cbf4: 2005 movs r0, #5 800cbf6: f7fd fcad bl 800a554 SC_SendPacket(NULL, 0, RESP_INVALID); 800cbfa: 2214 movs r2, #20 800cbfc: 4629 mov r1, r5 800cbfe: 4628 mov r0, r5 800cc00: f000 f8b6 bl 800cd70 800cc04: e7de b.n 800cbc4 log_printf(LOG_WARN, "UART2 RX idle event with zero size\n"); 800cc06: 4911 ldr r1, [pc, #68] @ (800cc4c ) 800cc08: 2005 movs r0, #5 800cc0a: f7fd fca3 bl 800a554 800cc0e: e7c7 b.n 800cba0 } 800cc10: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} CCS_RxEventCallback(huart, Size); 800cc14: f7ff b812 b.w 800bc3c 800cc18: 200012e8 .word 0x200012e8 800cc1c: 20001258 .word 0x20001258 800cc20: 20001330 .word 0x20001330 800cc24: 2000103c .word 0x2000103c 800cc28: 08017794 .word 0x08017794 800cc2c: 2000114d .word 0x2000114d 800cc30: 20000e2c .word 0x20000e2c 800cc34: 20001154 .word 0x20001154 800cc38: 20001150 .word 0x20001150 800cc3c: 2000114c .word 0x2000114c 800cc40: 2000113c .word 0x2000113c 800cc44: 08017770 .word 0x08017770 800cc48: 08017750 .word 0x08017750 800cc4c: 0801772c .word 0x0801772c 0800cc50 : ISR_FAST void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { if (huart->Instance == huart2.Instance) { 800cc50: 4b08 ldr r3, [pc, #32] @ (800cc74 ) 800cc52: 681a ldr r2, [r3, #0] 800cc54: 6803 ldr r3, [r0, #0] 800cc56: 4293 cmp r3, r2 800cc58: d004 beq.n 800cc64 serial_control.tx_tick = 0; } else if (huart->Instance == huart3.Instance) { 800cc5a: 4a07 ldr r2, [pc, #28] @ (800cc78 ) 800cc5c: 6812 ldr r2, [r2, #0] 800cc5e: 4293 cmp r3, r2 800cc60: d005 beq.n 800cc6e CCS_TxCpltCallback(huart); } } 800cc62: 4770 bx lr serial_control.tx_tick = 0; 800cc64: 2200 movs r2, #0 800cc66: 4b05 ldr r3, [pc, #20] @ (800cc7c ) 800cc68: f8c3 220c str.w r2, [r3, #524] @ 0x20c 800cc6c: 4770 bx lr CCS_TxCpltCallback(huart); 800cc6e: f7ff b88f b.w 800bd90 800cc72: bf00 nop 800cc74: 200012e8 .word 0x200012e8 800cc78: 20001330 .word 0x20001330 800cc7c: 20000d2c .word 0x20000d2c 0800cc80 : // Полностью программная реализация CRC-32 (полином CRC32_POLYNOMIAL, порядок little-endian) ISR_FAST static uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { uint32_t crc = 0xFFFFFFFFu; for (uint16_t i = 0; i < length; i++) { 800cc80: b3c9 cbz r1, 800ccf6 uint32_t crc = 0xFFFFFFFFu; 800cc82: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff ISR_FAST static uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { 800cc86: b500 push {lr} crc ^= data[i]; for (uint8_t bit = 0; bit < 8; bit++) { if (crc & 0x1u) { 800cc88: 4a1c ldr r2, [pc, #112] @ (800ccfc ) 800cc8a: 4401 add r1, r0 crc ^= data[i]; 800cc8c: f810 eb01 ldrb.w lr, [r0], #1 800cc90: ea8e 0e03 eor.w lr, lr, r3 if (crc & 0x1u) { 800cc94: f34e 0300 sbfx r3, lr, #0, #1 800cc98: f34e 0c40 sbfx ip, lr, #1, #1 800cc9c: 4013 ands r3, r2 800cc9e: ea83 035e eor.w r3, r3, lr, lsr #1 800cca2: ea0c 0c02 and.w ip, ip, r2 800cca6: ea8c 0c53 eor.w ip, ip, r3, lsr #1 800ccaa: f343 0340 sbfx r3, r3, #1, #1 800ccae: f34c 0e40 sbfx lr, ip, #1, #1 800ccb2: 4013 ands r3, r2 800ccb4: ea83 035c eor.w r3, r3, ip, lsr #1 800ccb8: ea0e 0e02 and.w lr, lr, r2 800ccbc: ea8e 0e53 eor.w lr, lr, r3, lsr #1 800ccc0: f343 0340 sbfx r3, r3, #1, #1 800ccc4: f34e 0c40 sbfx ip, lr, #1, #1 800ccc8: 4013 ands r3, r2 800ccca: ea83 035e eor.w r3, r3, lr, lsr #1 800ccce: ea0c 0c02 and.w ip, ip, r2 800ccd2: ea8c 0c53 eor.w ip, ip, r3, lsr #1 800ccd6: f343 0340 sbfx r3, r3, #1, #1 800ccda: 4013 ands r3, r2 800ccdc: f34c 0e40 sbfx lr, ip, #1, #1 800cce0: ea83 035c eor.w r3, r3, ip, lsr #1 for (uint16_t i = 0; i < length; i++) { 800cce4: 4281 cmp r1, r0 if (crc & 0x1u) { 800cce6: ea0e 0c02 and.w ip, lr, r2 800ccea: ea8c 0353 eor.w r3, ip, r3, lsr #1 for (uint16_t i = 0; i < length; i++) { 800ccee: d1cd bne.n 800cc8c crc >>= 1; } } } return crc ^ 0xFFFFFFFFu; 800ccf0: 43d8 mvns r0, r3 } 800ccf2: f85d fb04 ldr.w pc, [sp], #4 for (uint16_t i = 0; i < length; i++) { 800ccf6: 4608 mov r0, r1 } 800ccf8: 4770 bx lr 800ccfa: bf00 nop 800ccfc: edb88320 .word 0xedb88320 0800cd00 : ISR_FAST static uint16_t encode_packet(const uint8_t* payload, uint16_t payload_len, uint8_t* output, uint8_t response_code) { 800cd00: b570 push {r4, r5, r6, lr} 800cd02: 4615 mov r5, r2 uint16_t out_index = 0; output[out_index++] = response_code; 800cd04: 7013 strb r3, [r2, #0] if (payload != NULL) { 800cd06: b360 cbz r0, 800cd62 // Просто копируем полезную нагрузку без какого‑либо экранирования for (uint16_t i = 0; i < payload_len; i++) { 800cd08: b359 cbz r1, 800cd62 output[out_index++] = payload[i]; 800cd0a: 4694 mov ip, r2 800cd0c: 2302 movs r3, #2 800cd0e: 7802 ldrb r2, [r0, #0] 800cd10: 1e4c subs r4, r1, #1 800cd12: b2a4 uxth r4, r4 800cd14: 441c add r4, r3 800cd16: f80c 2f01 strb.w r2, [ip, #1]! // Проверка переполнения if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800cd1a: e005 b.n 800cd28 output[out_index++] = payload[i]; 800cd1c: f810 1f01 ldrb.w r1, [r0, #1]! if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800cd20: 2bfb cmp r3, #251 @ 0xfb output[out_index++] = payload[i]; 800cd22: f80c 1f01 strb.w r1, [ip, #1]! if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800cd26: d020 beq.n 800cd6a for (uint16_t i = 0; i < payload_len; i++) { 800cd28: 42a3 cmp r3, r4 if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800cd2a: f103 0301 add.w r3, r3, #1 for (uint16_t i = 0; i < payload_len; i++) { 800cd2e: d1f5 bne.n 800cd1c 800cd30: b2a1 uxth r1, r4 output[out_index++] = payload[i]; 800cd32: 1c4e adds r6, r1, #1 800cd34: b2b6 uxth r6, r6 } } } // Вычисляем CRC для всего содержимого (код ответа + полезная нагрузка) uint32_t crc = calculate_crc32(output, out_index); 800cd36: 4628 mov r0, r5 800cd38: f7ff ffa2 bl 800cc80 800cd3c: 4603 mov r3, r0 uint8_t* crc_bytes = (uint8_t*)&crc; // Добавляем CRC без экранирования for (int i = 0; i < 4; i++) { output[out_index++] = crc_bytes[i]; 800cd3e: 1c71 adds r1, r6, #1 800cd40: 1cb2 adds r2, r6, #2 800cd42: 552b strb r3, [r5, r4] 800cd44: f3c3 2c07 ubfx ip, r3, #8, #8 800cd48: f3c3 4407 ubfx r4, r3, #16, #8 800cd4c: b289 uxth r1, r1 800cd4e: b292 uxth r2, r2 800cd50: f3c3 6307 ubfx r3, r3, #24, #8 800cd54: f805 c006 strb.w ip, [r5, r6] 800cd58: 1cf0 adds r0, r6, #3 800cd5a: 546c strb r4, [r5, r1] 800cd5c: 54ab strb r3, [r5, r2] 800cd5e: b280 uxth r0, r0 return 0; } } return out_index; } 800cd60: bd70 pop {r4, r5, r6, pc} for (uint16_t i = 0; i < payload_len; i++) { 800cd62: 2401 movs r4, #1 800cd64: 2602 movs r6, #2 output[out_index++] = response_code; 800cd66: 4621 mov r1, r4 800cd68: e7e5 b.n 800cd36 return 0; 800cd6a: 2000 movs r0, #0 } 800cd6c: bd70 pop {r4, r5, r6, pc} 800cd6e: bf00 nop 0800cd70 : ISR_FAST void SC_SendPacket(const uint8_t* payload, uint16_t payload_len, uint8_t response_code) { 800cd70: b538 push {r3, r4, r5, lr} 800cd72: 4613 mov r3, r2 uint16_t packet_len = encode_packet(payload, payload_len, serial_control.tx_buffer, response_code); 800cd74: 4a11 ldr r2, [pc, #68] @ (800cdbc ) 800cd76: f7ff ffc3 bl 800cd00 if (packet_len > 0) { 800cd7a: b180 cbz r0, 800cd9e if (huart2.gState != HAL_UART_STATE_READY) { 800cd7c: 4604 mov r4, r0 800cd7e: 4810 ldr r0, [pc, #64] @ (800cdc0 ) 800cd80: f890 3041 ldrb.w r3, [r0, #65] @ 0x41 800cd84: 2b20 cmp r3, #32 800cd86: d10b bne.n 800cda0 (void)HAL_UART_AbortTransmit(&huart2); log_printf(LOG_WARN, "UART2 TX busy, abort transmit before resend\n"); } if (HAL_UART_Transmit_DMA(&huart2, serial_control.tx_buffer, packet_len) != HAL_OK) { 800cd88: 4d0c ldr r5, [pc, #48] @ (800cdbc ) 800cd8a: 4622 mov r2, r4 800cd8c: 4629 mov r1, r5 800cd8e: 480c ldr r0, [pc, #48] @ (800cdc0 ) 800cd90: f006 f8ce bl 8012f30 800cd94: b958 cbnz r0, 800cdae SC_LogUartError("UART2 TX DMA start failed", &huart2); return; } serial_control.tx_tick = HAL_GetTick(); 800cd96: f001 facf bl 800e338 800cd9a: f8c5 020c str.w r0, [r5, #524] @ 0x20c } } 800cd9e: bd38 pop {r3, r4, r5, pc} (void)HAL_UART_AbortTransmit(&huart2); 800cda0: f006 f9ec bl 801317c log_printf(LOG_WARN, "UART2 TX busy, abort transmit before resend\n"); 800cda4: 4907 ldr r1, [pc, #28] @ (800cdc4 ) 800cda6: 2005 movs r0, #5 800cda8: f7fd fbd4 bl 800a554 800cdac: e7ec b.n 800cd88 SC_LogUartError("UART2 TX DMA start failed", &huart2); 800cdae: 4904 ldr r1, [pc, #16] @ (800cdc0 ) 800cdb0: 4805 ldr r0, [pc, #20] @ (800cdc8 ) } 800cdb2: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} SC_LogUartError("UART2 TX DMA start failed", &huart2); 800cdb6: f000 b905 b.w 800cfc4 800cdba: bf00 nop 800cdbc: 20000d2c .word 0x20000d2c 800cdc0: 200012e8 .word 0x200012e8 800cdc4: 080177b4 .word 0x080177b4 800cdc8: 080177e4 .word 0x080177e4 0800cdcc : ISR_FAST static uint8_t parse_packet(const uint8_t* packet_data, uint16_t packet_len, ReceivedCommand_t* out_cmd) { 800cdcc: e92d 4178 stmdb sp!, {r3, r4, r5, r6, r8, lr} // }else{ // test_crc_invalid = 5; // } // Минимальный размер: 1 байт команды + 4 байта CRC if (packet_len < 5) return 0; 800cdd0: 1f4b subs r3, r1, #5 800cdd2: 2bfb cmp r3, #251 @ 0xfb 800cdd4: d813 bhi.n 800cdfe if (packet_len > MAX_RX_BUFFER_SIZE) return 0; uint16_t payload_length = packet_len - 4; 800cdd6: 3904 subs r1, #4 800cdd8: b28c uxth r4, r1 // Извлекаем принятую CRC (последние 4 байта, little-endian) uint32_t received_checksum = ((uint32_t)packet_data[payload_length] << 0) | ((uint32_t)packet_data[payload_length + 1] << 8) | 800cdda: 1903 adds r3, r0, r4 ((uint32_t)packet_data[payload_length + 2] << 16) | 800cddc: 789d ldrb r5, [r3, #2] 800cdde: 4690 mov r8, r2 ((uint32_t)packet_data[payload_length + 1] << 8) | 800cde0: 785a ldrb r2, [r3, #1] ((uint32_t)packet_data[payload_length + 2] << 16) | 800cde2: 042d lsls r5, r5, #16 ((uint32_t)packet_data[payload_length + 1] << 8) | 800cde4: ea45 2502 orr.w r5, r5, r2, lsl #8 ((uint32_t)packet_data[payload_length] << 0) | 800cde8: 5d02 ldrb r2, [r0, r4] ((uint32_t)packet_data[payload_length + 3] << 24); 800cdea: 78db ldrb r3, [r3, #3] ((uint32_t)packet_data[payload_length + 1] << 8) | 800cdec: 4315 orrs r5, r2 // Вычисляем CRC для полезной нагрузки uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); 800cdee: 4621 mov r1, r4 uint32_t received_checksum = 800cdf0: ea45 6503 orr.w r5, r5, r3, lsl #24 uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); 800cdf4: 4606 mov r6, r0 800cdf6: f7ff ff43 bl 800cc80 if (received_checksum != calculated_checksum) return 0; // CRC не совпадает 800cdfa: 4285 cmp r5, r0 800cdfc: d002 beq.n 800ce04 if (packet_len < 5) return 0; 800cdfe: 2000 movs r0, #0 out_cmd->argument = (void *)&packet_data[1]; out_cmd->command = packet_data[0]; out_cmd->argument_length = (uint8_t)(payload_length - 1); return 1; } 800ce00: e8bd 8178 ldmia.w sp!, {r3, r4, r5, r6, r8, pc} out_cmd->argument = (void *)&packet_data[1]; 800ce04: 1c73 adds r3, r6, #1 800ce06: f8c8 3004 str.w r3, [r8, #4] out_cmd->command = packet_data[0]; 800ce0a: 7833 ldrb r3, [r6, #0] out_cmd->argument_length = (uint8_t)(payload_length - 1); 800ce0c: 3c01 subs r4, #1 out_cmd->command = packet_data[0]; 800ce0e: f888 3000 strb.w r3, [r8] out_cmd->argument_length = (uint8_t)(payload_length - 1); 800ce12: f888 4001 strb.w r4, [r8, #1] return 1; 800ce16: 2001 movs r0, #1 } 800ce18: e8bd 8178 ldmia.w sp!, {r3, r4, r5, r6, r8, pc} 0800ce1c : ISR_FAST static uint8_t process_received_packet(SerialControl_t *ctx, const uint8_t* packet_data, uint16_t packet_len) { 800ce1c: b510 push {r4, lr} 800ce1e: 4604 mov r4, r0 if (!parse_packet(packet_data, packet_len, (ReceivedCommand_t *)&ctx->received_command)) { 800ce20: 4608 mov r0, r1 800ce22: 4611 mov r1, r2 800ce24: f504 7200 add.w r2, r4, #512 @ 0x200 800ce28: f7ff ffd0 bl 800cdcc 800ce2c: b118 cbz r0, 800ce36 return 0; } ctx->command_ready = 1; 800ce2e: 2301 movs r3, #1 return 1; 800ce30: 4618 mov r0, r3 ctx->command_ready = 1; 800ce32: f884 3208 strb.w r3, [r4, #520] @ 0x208 } 800ce36: bd10 pop {r4, pc} 0800ce38 : static void SC_UART2_Watchdog(void) { 800ce38: b580 push {r7, lr} 800ce3a: b082 sub sp, #8 800ce3c: af00 add r7, sp, #0 const uint32_t now = HAL_GetTick(); 800ce3e: f001 fa7b bl 800e338 800ce42: 6078 str r0, [r7, #4] const int32_t since_last_packet = (int32_t)(now - sc_uart2_last_packet_tick); 800ce44: 4b1a ldr r3, [pc, #104] @ (800ceb0 ) 800ce46: 681b ldr r3, [r3, #0] 800ce48: 687a ldr r2, [r7, #4] 800ce4a: 1ad3 subs r3, r2, r3 800ce4c: 603b str r3, [r7, #0] if (since_last_packet >= (int32_t)SC_UART2_PACKET_TIMEOUT_MS) { 800ce4e: 683b ldr r3, [r7, #0] 800ce50: f241 3287 movw r2, #4999 @ 0x1387 800ce54: 4293 cmp r3, r2 800ce56: dd12 ble.n 800ce7e if (sc_uart2_timed_out == 0u) { 800ce58: 4b16 ldr r3, [pc, #88] @ (800ceb4 ) 800ce5a: 781b ldrb r3, [r3, #0] 800ce5c: b2db uxtb r3, r3 800ce5e: 2b00 cmp r3, #0 800ce60: d109 bne.n 800ce76 serial_control.command_ready = 0; 800ce62: 4b15 ldr r3, [pc, #84] @ (800ceb8 ) 800ce64: 2200 movs r2, #0 800ce66: f883 2208 strb.w r2, [r3, #520] @ 0x208 log_printf(LOG_WARN, "UART2 RX packet timeout (%u ms)\n", (unsigned)SC_UART2_PACKET_TIMEOUT_MS); 800ce6a: f241 3288 movw r2, #5000 @ 0x1388 800ce6e: 4913 ldr r1, [pc, #76] @ (800cebc ) 800ce70: 2005 movs r0, #5 800ce72: f7fd fb6f bl 800a554 } sc_uart2_timed_out = 1; 800ce76: 4b0f ldr r3, [pc, #60] @ (800ceb4 ) 800ce78: 2201 movs r2, #1 800ce7a: 701a strb r2, [r3, #0] 800ce7c: e002 b.n 800ce84 } else { sc_uart2_timed_out = 0; 800ce7e: 4b0d ldr r3, [pc, #52] @ (800ceb4 ) 800ce80: 2200 movs r2, #0 800ce82: 701a strb r2, [r3, #0] } if ((huart2.RxState == HAL_UART_STATE_READY) && 800ce84: 4b0e ldr r3, [pc, #56] @ (800cec0 ) 800ce86: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800ce8a: b2db uxtb r3, r3 800ce8c: 2b20 cmp r3, #32 800ce8e: d10a bne.n 800cea6 ((int32_t)(now - sc_uart2_last_recover_tick) >= (int32_t)SC_UART2_RECOVER_GUARD_MS)) { 800ce90: 4b0c ldr r3, [pc, #48] @ (800cec4 ) 800ce92: 681b ldr r3, [r3, #0] 800ce94: 687a ldr r2, [r7, #4] 800ce96: 1ad3 subs r3, r2, r3 if ((huart2.RxState == HAL_UART_STATE_READY) && 800ce98: 2bc7 cmp r3, #199 @ 0xc7 800ce9a: dd04 ble.n 800cea6 SC_ArmUart2RxDma(); 800ce9c: f000 f814 bl 800cec8 sc_uart2_last_recover_tick = now; 800cea0: 4a08 ldr r2, [pc, #32] @ (800cec4 ) 800cea2: 687b ldr r3, [r7, #4] 800cea4: 6013 str r3, [r2, #0] } } 800cea6: bf00 nop 800cea8: 3708 adds r7, #8 800ceaa: 46bd mov sp, r7 800ceac: bd80 pop {r7, pc} 800ceae: bf00 nop 800ceb0: 20001150 .word 0x20001150 800ceb4: 2000114d .word 0x2000114d 800ceb8: 20000d2c .word 0x20000d2c 800cebc: 08017800 .word 0x08017800 800cec0: 200012e8 .word 0x200012e8 800cec4: 20001154 .word 0x20001154 0800cec8 : static void SC_ArmUart2RxDma(void) { 800cec8: b580 push {r7, lr} 800ceca: af00 add r7, sp, #0 if ((huart2.RxState == HAL_UART_STATE_READY) && (serial_control.command_ready == 0)) { 800cecc: 4b0c ldr r3, [pc, #48] @ (800cf00 ) 800cece: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800ced2: b2db uxtb r3, r3 800ced4: 2b20 cmp r3, #32 800ced6: d111 bne.n 800cefc 800ced8: 4b0a ldr r3, [pc, #40] @ (800cf04 ) 800ceda: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800cede: b2db uxtb r3, r3 800cee0: 2b00 cmp r3, #0 800cee2: d10b bne.n 800cefc if (HAL_UARTEx_ReceiveToIdle_DMA(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1) != HAL_OK) { 800cee4: 22ff movs r2, #255 @ 0xff 800cee6: 4908 ldr r1, [pc, #32] @ (800cf08 ) 800cee8: 4805 ldr r0, [pc, #20] @ (800cf00 ) 800ceea: f006 f8ee bl 80130ca 800ceee: 4603 mov r3, r0 800cef0: 2b00 cmp r3, #0 800cef2: d003 beq.n 800cefc SC_LogUartError("UART2 RX DMA arm failed", &huart2); 800cef4: 4902 ldr r1, [pc, #8] @ (800cf00 ) 800cef6: 4805 ldr r0, [pc, #20] @ (800cf0c ) 800cef8: f000 f864 bl 800cfc4 } } } 800cefc: bf00 nop 800cefe: bd80 pop {r7, pc} 800cf00: 200012e8 .word 0x200012e8 800cf04: 20000d2c .word 0x20000d2c 800cf08: 20000e2c .word 0x20000e2c 800cf0c: 08017824 .word 0x08017824 0800cf10 : static void SC_ArmUart5RxDma(void) { 800cf10: b580 push {r7, lr} 800cf12: af00 add r7, sp, #0 if (huart5.RxState == HAL_UART_STATE_READY) { 800cf14: 4b0a ldr r3, [pc, #40] @ (800cf40 ) 800cf16: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800cf1a: b2db uxtb r3, r3 800cf1c: 2b20 cmp r3, #32 800cf1e: d10d bne.n 800cf3c if (HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1) == HAL_OK) { 800cf20: 22ff movs r2, #255 @ 0xff 800cf22: 4908 ldr r1, [pc, #32] @ (800cf44 ) 800cf24: 4806 ldr r0, [pc, #24] @ (800cf40 ) 800cf26: f006 f873 bl 8013010 800cf2a: 4603 mov r3, r0 800cf2c: 2b00 cmp r3, #0 800cf2e: d004 beq.n 800cf3a return; } SC_LogUartError("UART5 RX IT arm failed", &huart5); 800cf30: 4903 ldr r1, [pc, #12] @ (800cf40 ) 800cf32: 4805 ldr r0, [pc, #20] @ (800cf48 ) 800cf34: f000 f846 bl 800cfc4 800cf38: e000 b.n 800cf3c return; 800cf3a: bf00 nop } } 800cf3c: bd80 pop {r7, pc} 800cf3e: bf00 nop 800cf40: 20001258 .word 0x20001258 800cf44: 2000103c .word 0x2000103c 800cf48: 0801783c .word 0x0801783c 0800cf4c : void SC_RecoverUartDma(UART_HandleTypeDef *huart) { 800cf4c: b580 push {r7, lr} 800cf4e: b082 sub sp, #8 800cf50: af00 add r7, sp, #0 800cf52: 6078 str r0, [r7, #4] if (huart == &huart2) { 800cf54: 687b ldr r3, [r7, #4] 800cf56: 4a15 ldr r2, [pc, #84] @ (800cfac ) 800cf58: 4293 cmp r3, r2 800cf5a: d115 bne.n 800cf88 SC_LogUartError("UART2 recover start", &huart2); 800cf5c: 4913 ldr r1, [pc, #76] @ (800cfac ) 800cf5e: 4814 ldr r0, [pc, #80] @ (800cfb0 ) 800cf60: f000 f830 bl 800cfc4 (void)HAL_UART_AbortReceive(&huart2); 800cf64: 4811 ldr r0, [pc, #68] @ (800cfac ) 800cf66: f006 f971 bl 801324c (void)HAL_UART_AbortTransmit(&huart2); 800cf6a: 4810 ldr r0, [pc, #64] @ (800cfac ) 800cf6c: f006 f906 bl 801317c serial_control.tx_tick = 0; 800cf70: 4b10 ldr r3, [pc, #64] @ (800cfb4 ) 800cf72: 2200 movs r2, #0 800cf74: f8c3 220c str.w r2, [r3, #524] @ 0x20c SC_ArmUart2RxDma(); 800cf78: f7ff ffa6 bl 800cec8 sc_uart2_last_recover_tick = HAL_GetTick(); 800cf7c: f001 f9dc bl 800e338 800cf80: 4603 mov r3, r0 800cf82: 4a0d ldr r2, [pc, #52] @ (800cfb8 ) 800cf84: 6013 str r3, [r2, #0] } else if (huart == &huart5) { SC_LogUartError("UART5 recover start", &huart5); (void)HAL_UART_AbortReceive(&huart5); SC_ArmUart5RxDma(); } } 800cf86: e00c b.n 800cfa2 } else if (huart == &huart5) { 800cf88: 687b ldr r3, [r7, #4] 800cf8a: 4a0c ldr r2, [pc, #48] @ (800cfbc ) 800cf8c: 4293 cmp r3, r2 800cf8e: d108 bne.n 800cfa2 SC_LogUartError("UART5 recover start", &huart5); 800cf90: 490a ldr r1, [pc, #40] @ (800cfbc ) 800cf92: 480b ldr r0, [pc, #44] @ (800cfc0 ) 800cf94: f000 f816 bl 800cfc4 (void)HAL_UART_AbortReceive(&huart5); 800cf98: 4808 ldr r0, [pc, #32] @ (800cfbc ) 800cf9a: f006 f957 bl 801324c SC_ArmUart5RxDma(); 800cf9e: f7ff ffb7 bl 800cf10 } 800cfa2: bf00 nop 800cfa4: 3708 adds r7, #8 800cfa6: 46bd mov sp, r7 800cfa8: bd80 pop {r7, pc} 800cfaa: bf00 nop 800cfac: 200012e8 .word 0x200012e8 800cfb0: 08017854 .word 0x08017854 800cfb4: 20000d2c .word 0x20000d2c 800cfb8: 20001154 .word 0x20001154 800cfbc: 20001258 .word 0x20001258 800cfc0: 08017868 .word 0x08017868 0800cfc4 : static void SC_LogUartError(const char *tag, UART_HandleTypeDef *huart) { 800cfc4: b590 push {r4, r7, lr} 800cfc6: b087 sub sp, #28 800cfc8: af04 add r7, sp, #16 800cfca: 6078 str r0, [r7, #4] 800cfcc: 6039 str r1, [r7, #0] if (tag == NULL || huart == NULL) { 800cfce: 687b ldr r3, [r7, #4] 800cfd0: 2b00 cmp r3, #0 800cfd2: d01c beq.n 800d00e 800cfd4: 683b ldr r3, [r7, #0] 800cfd6: 2b00 cmp r3, #0 800cfd8: d019 beq.n 800d00e return; } log_printf(LOG_ERR, "%s: instance=0x%08lx err=0x%08lx g=%lu rx=%lu\n", tag, (unsigned long)huart->Instance, 800cfda: 683b ldr r3, [r7, #0] 800cfdc: 681b ldr r3, [r3, #0] log_printf(LOG_ERR, "%s: instance=0x%08lx err=0x%08lx g=%lu rx=%lu\n", 800cfde: 461c mov r4, r3 (unsigned long)HAL_UART_GetError(huart), 800cfe0: 6838 ldr r0, [r7, #0] 800cfe2: f006 fc84 bl 80138ee 800cfe6: 4602 mov r2, r0 (unsigned long)huart->gState, 800cfe8: 683b ldr r3, [r7, #0] 800cfea: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800cfee: b2db uxtb r3, r3 log_printf(LOG_ERR, "%s: instance=0x%08lx err=0x%08lx g=%lu rx=%lu\n", 800cff0: 4619 mov r1, r3 (unsigned long)huart->RxState); 800cff2: 683b ldr r3, [r7, #0] 800cff4: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800cff8: b2db uxtb r3, r3 log_printf(LOG_ERR, "%s: instance=0x%08lx err=0x%08lx g=%lu rx=%lu\n", 800cffa: 9302 str r3, [sp, #8] 800cffc: 9101 str r1, [sp, #4] 800cffe: 9200 str r2, [sp, #0] 800d000: 4623 mov r3, r4 800d002: 687a ldr r2, [r7, #4] 800d004: 4904 ldr r1, [pc, #16] @ (800d018 ) 800d006: 2004 movs r0, #4 800d008: f7fd faa4 bl 800a554 800d00c: e000 b.n 800d010 return; 800d00e: bf00 nop } 800d010: 370c adds r7, #12 800d012: 46bd mov sp, r7 800d014: bd90 pop {r4, r7, pc} 800d016: bf00 nop 800d018: 0801787c .word 0x0801787c 0800d01c <__NVIC_SystemReset>: { 800d01c: b480 push {r7} 800d01e: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 800d020: f3bf 8f4f dsb sy } 800d024: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800d026: 4b06 ldr r3, [pc, #24] @ (800d040 <__NVIC_SystemReset+0x24>) 800d028: 68db ldr r3, [r3, #12] 800d02a: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800d02e: 4904 ldr r1, [pc, #16] @ (800d040 <__NVIC_SystemReset+0x24>) 800d030: 4b04 ldr r3, [pc, #16] @ (800d044 <__NVIC_SystemReset+0x28>) 800d032: 4313 orrs r3, r2 800d034: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800d036: f3bf 8f4f dsb sy } 800d03a: bf00 nop __NOP(); 800d03c: bf00 nop 800d03e: e7fd b.n 800d03c <__NVIC_SystemReset+0x20> 800d040: e000ed00 .word 0xe000ed00 800d044: 05fa0004 .word 0x05fa0004 0800d048 : .chargerNumber = 00001, .unixTime = 1721651966, }; // Единая функция-обработчик всех команд со switch-case void SC_CommandHandler(ReceivedCommand_t* cmd) { 800d048: b580 push {r7, lr} 800d04a: b084 sub sp, #16 800d04c: af00 add r7, sp, #0 800d04e: 6078 str r0, [r7, #4] uint8_t response_code = RESP_FAILED; 800d050: 2313 movs r3, #19 800d052: 73fb strb r3, [r7, #15] switch (cmd->command) { 800d054: 687b ldr r3, [r7, #4] 800d056: 781b ldrb r3, [r3, #0] 800d058: 2bc2 cmp r3, #194 @ 0xc2 800d05a: f300 80cc bgt.w 800d1f6 800d05e: 2bb0 cmp r3, #176 @ 0xb0 800d060: da0f bge.n 800d082 800d062: 2b60 cmp r3, #96 @ 0x60 800d064: d042 beq.n 800d0ec 800d066: 2b60 cmp r3, #96 @ 0x60 800d068: f300 80c5 bgt.w 800d1f6 800d06c: 2b50 cmp r3, #80 @ 0x50 800d06e: d043 beq.n 800d0f8 800d070: 2b50 cmp r3, #80 @ 0x50 800d072: f300 80c0 bgt.w 800d1f6 800d076: 2b01 cmp r3, #1 800d078: f000 80a6 beq.w 800d1c8 800d07c: 2b40 cmp r3, #64 @ 0x40 800d07e: d02d beq.n 800d0dc 800d080: e0b9 b.n 800d1f6 800d082: 3bb0 subs r3, #176 @ 0xb0 800d084: 2b12 cmp r3, #18 800d086: f200 80b6 bhi.w 800d1f6 800d08a: a201 add r2, pc, #4 @ (adr r2, 800d090 ) 800d08c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d090: 0800d0ff .word 0x0800d0ff 800d094: 0800d1f7 .word 0x0800d1f7 800d098: 0800d1f7 .word 0x0800d1f7 800d09c: 0800d1f7 .word 0x0800d1f7 800d0a0: 0800d1f7 .word 0x0800d1f7 800d0a4: 0800d1a7 .word 0x0800d1a7 800d0a8: 0800d1f7 .word 0x0800d1f7 800d0ac: 0800d1f7 .word 0x0800d1f7 800d0b0: 0800d1f7 .word 0x0800d1f7 800d0b4: 0800d1f7 .word 0x0800d1f7 800d0b8: 0800d1f7 .word 0x0800d1f7 800d0bc: 0800d1f7 .word 0x0800d1f7 800d0c0: 0800d1f7 .word 0x0800d1f7 800d0c4: 0800d1f7 .word 0x0800d1f7 800d0c8: 0800d1f7 .word 0x0800d1f7 800d0cc: 0800d1f7 .word 0x0800d1f7 800d0d0: 0800d13d .word 0x0800d13d 800d0d4: 0800d1a1 .word 0x0800d1a1 800d0d8: 0800d175 .word 0x0800d175 // Команды БЕЗ аргументов case CMD_GET_STATUS: // Логика получения информации monitoring_data_callback(); 800d0dc: f000 f8b2 bl 800d244 // Отправляем с нормальным приоритетом SC_SendPacket((uint8_t*)&statusPacket, sizeof(statusPacket), CMD_GET_STATUS); 800d0e0: 2240 movs r2, #64 @ 0x40 800d0e2: 2158 movs r1, #88 @ 0x58 800d0e4: 484b ldr r0, [pc, #300] @ (800d214 ) 800d0e6: f7ff fe43 bl 800cd70 return; // Специальный ответ уже отправлен 800d0ea: e08f b.n 800d20c case CMD_GET_INFO: SC_SendPacket((uint8_t*)&infoPacket, sizeof(infoPacket), CMD_GET_INFO); 800d0ec: 2260 movs r2, #96 @ 0x60 800d0ee: 210a movs r1, #10 800d0f0: 4849 ldr r0, [pc, #292] @ (800d218 ) 800d0f2: f7ff fe3d bl 800cd70 return; 800d0f6: e089 b.n 800d20c case CMD_GET_LOG: debug_buffer_send(); 800d0f8: f7fd f9ca bl 800a490 return; // Ответ формируется внутри debug_buffer_send 800d0fc: e086 b.n 800d20c // Команды С аргументами case CMD_SET_CONFIG: if (cmd->argument_length == sizeof(ConfigBlock_t)) { 800d0fe: 687b ldr r3, [r7, #4] 800d100: 785b ldrb r3, [r3, #1] 800d102: 2b0b cmp r3, #11 800d104: d117 bne.n 800d136 memcpy(&config, cmd->argument, sizeof(ConfigBlock_t)); 800d106: 687b ldr r3, [r7, #4] 800d108: 685a ldr r2, [r3, #4] 800d10a: 4b44 ldr r3, [pc, #272] @ (800d21c ) 800d10c: 6810 ldr r0, [r2, #0] 800d10e: 6851 ldr r1, [r2, #4] 800d110: c303 stmia r3!, {r0, r1} 800d112: 8911 ldrh r1, [r2, #8] 800d114: 7a92 ldrb r2, [r2, #10] 800d116: 8019 strh r1, [r3, #0] 800d118: 709a strb r2, [r3, #2] config_initialized = 1; 800d11a: 4b41 ldr r3, [pc, #260] @ (800d220 ) 800d11c: 2201 movs r2, #1 800d11e: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Set Config: %s %d\n", config.location, config.chargerNumber); 800d120: 4b3e ldr r3, [pc, #248] @ (800d21c ) 800d122: f8d3 3003 ldr.w r3, [r3, #3] 800d126: 4a3d ldr r2, [pc, #244] @ (800d21c ) 800d128: 493e ldr r1, [pc, #248] @ (800d224 ) 800d12a: 2007 movs r0, #7 800d12c: f7fd fa12 bl 800a554 response_code = RESP_SUCCESS; 800d130: 2312 movs r3, #18 800d132: 73fb strb r3, [r7, #15] break; 800d134: e062 b.n 800d1fc } response_code = RESP_FAILED; 800d136: 2313 movs r3, #19 800d138: 73fb strb r3, [r7, #15] break; 800d13a: e05f b.n 800d1fc case CMD_SET_POWER_LIMIT: if (cmd->argument_length == 1) { 800d13c: 687b ldr r3, [r7, #4] 800d13e: 785b ldrb r3, [r3, #1] 800d140: 2b01 cmp r3, #1 800d142: d114 bne.n 800d16e PSU0.power_limit = ((uint8_t*)cmd->argument)[0] * 1000; 800d144: 687b ldr r3, [r7, #4] 800d146: 685b ldr r3, [r3, #4] 800d148: 781b ldrb r3, [r3, #0] 800d14a: 461a mov r2, r3 800d14c: f44f 737a mov.w r3, #1000 @ 0x3e8 800d150: fb02 f303 mul.w r3, r2, r3 800d154: 461a mov r2, r3 800d156: 4b34 ldr r3, [pc, #208] @ (800d228 ) 800d158: 615a str r2, [r3, #20] log_printf(LOG_INFO, "Power limit: %d\n", PSU0.power_limit); 800d15a: 4b33 ldr r3, [pc, #204] @ (800d228 ) 800d15c: 695b ldr r3, [r3, #20] 800d15e: 461a mov r2, r3 800d160: 4932 ldr r1, [pc, #200] @ (800d22c ) 800d162: 2007 movs r0, #7 800d164: f7fd f9f6 bl 800a554 //CONN.connState = (((uint8_t*)cmd->argument)[0])/4; response_code = RESP_SUCCESS; 800d168: 2312 movs r3, #18 800d16a: 73fb strb r3, [r7, #15] break; 800d16c: e046 b.n 800d1fc } response_code = RESP_FAILED; 800d16e: 2313 movs r3, #19 800d170: 73fb strb r3, [r7, #15] break; 800d172: e043 b.n 800d1fc case CMD_CHARGE_PERMIT: if (cmd->argument_length == 1) { 800d174: 687b ldr r3, [r7, #4] 800d176: 785b ldrb r3, [r3, #1] 800d178: 2b01 cmp r3, #1 800d17a: d10e bne.n 800d19a CONN.connControl = ((uint8_t*)cmd->argument)[0]; 800d17c: 687b ldr r3, [r7, #4] 800d17e: 685b ldr r3, [r3, #4] 800d180: 781a ldrb r2, [r3, #0] 800d182: 4b2b ldr r3, [pc, #172] @ (800d230 ) 800d184: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Charge permit: %d\n", CONN.connControl); 800d186: 4b2a ldr r3, [pc, #168] @ (800d230 ) 800d188: 781b ldrb r3, [r3, #0] 800d18a: 461a mov r2, r3 800d18c: 4929 ldr r1, [pc, #164] @ (800d234 ) 800d18e: 2007 movs r0, #7 800d190: f7fd f9e0 bl 800a554 response_code = RESP_SUCCESS; 800d194: 2312 movs r3, #18 800d196: 73fb strb r3, [r7, #15] break; 800d198: e030 b.n 800d1fc } response_code = RESP_FAILED; 800d19a: 2313 movs r3, #19 800d19c: 73fb strb r3, [r7, #15] break; 800d19e: e02d b.n 800d1fc // memcpy(&PSU_TestMode, cmd->argument, sizeof(PSU_TestMode_t)); // log_printf(LOG_INFO, "Test PSU: %d %d %d\n", PSU_TestMode.enable, PSU_TestMode.voltage, PSU_TestMode.current); // response_code = RESP_SUCCESS; // break; // } response_code = RESP_FAILED; 800d1a0: 2313 movs r3, #19 800d1a2: 73fb strb r3, [r7, #15] break; 800d1a4: e02a b.n 800d1fc case CMD_DEVICE_RESET: // 2. Отправляем SUCCESS (хост может успеть получить его перед ребутом) SC_SendPacket(NULL, 0, RESP_SUCCESS); 800d1a6: 2212 movs r2, #18 800d1a8: 2100 movs r1, #0 800d1aa: 2000 movs r0, #0 800d1ac: f7ff fde0 bl 800cd70 while(huart2.gState == HAL_UART_STATE_BUSY_TX); // Ожидание завершения передачи 800d1b0: bf00 nop 800d1b2: 4b21 ldr r3, [pc, #132] @ (800d238 ) 800d1b4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800d1b8: b2db uxtb r3, r3 800d1ba: 2b21 cmp r3, #33 @ 0x21 800d1bc: d0f9 beq.n 800d1b2 HAL_Delay(10); 800d1be: 200a movs r0, #10 800d1c0: f001 f8c4 bl 800e34c // 3. Выполняем программный сброс NVIC_SystemReset(); 800d1c4: f7ff ff2a bl 800d01c <__NVIC_SystemReset> return; // Сюда код уже не дойдет, но для компилятора нxужно case CMD_ISOLATION_STATUS: if (cmd->argument_length == sizeof(IsolationStatusPacket_t)) { 800d1c8: 687b ldr r3, [r7, #4] 800d1ca: 785b ldrb r3, [r3, #1] 800d1cc: 2b09 cmp r3, #9 800d1ce: d10f bne.n 800d1f0 memcpy(&ISO, cmd->argument, sizeof(IsolationStatusPacket_t)); 800d1d0: 687b ldr r3, [r7, #4] 800d1d2: 685a ldr r2, [r3, #4] 800d1d4: 4b19 ldr r3, [pc, #100] @ (800d23c ) 800d1d6: 6810 ldr r0, [r2, #0] 800d1d8: 6851 ldr r1, [r2, #4] 800d1da: c303 stmia r3!, {r0, r1} 800d1dc: 7a12 ldrb r2, [r2, #8] 800d1de: 701a strb r2, [r3, #0] // Для однонаправленного UART5 ответ не нужен if (g_sc_command_source == SC_SOURCE_UART5) { 800d1e0: 4b17 ldr r3, [pc, #92] @ (800d240 ) 800d1e2: 781b ldrb r3, [r3, #0] 800d1e4: b2db uxtb r3, r3 800d1e6: 2b01 cmp r3, #1 800d1e8: d00f beq.n 800d20a return; } response_code = RESP_SUCCESS; 800d1ea: 2312 movs r3, #18 800d1ec: 73fb strb r3, [r7, #15] break; 800d1ee: e005 b.n 800d1fc } response_code = RESP_FAILED; 800d1f0: 2313 movs r3, #19 800d1f2: 73fb strb r3, [r7, #15] break; 800d1f4: e002 b.n 800d1fc default: // Неизвестная команда response_code = RESP_FAILED; 800d1f6: 2313 movs r3, #19 800d1f8: 73fb strb r3, [r7, #15] break; 800d1fa: bf00 nop } // Отправляем финальный ответ (для команд без собственного ответа) SC_SendPacket(NULL, 0, response_code); 800d1fc: 7bfb ldrb r3, [r7, #15] 800d1fe: 461a mov r2, r3 800d200: 2100 movs r1, #0 800d202: 2000 movs r0, #0 800d204: f7ff fdb4 bl 800cd70 800d208: e000 b.n 800d20c return; 800d20a: bf00 nop } 800d20c: 3710 adds r7, #16 800d20e: 46bd mov sp, r7 800d210: bd80 pop {r7, pc} 800d212: bf00 nop 800d214: 20001158 .word 0x20001158 800d218: 200011b0 .word 0x200011b0 800d21c: 20000078 .word 0x20000078 800d220: 200011c0 .word 0x200011c0 800d224: 080178ac .word 0x080178ac 800d228: 20000904 .word 0x20000904 800d22c: 080178c0 .word 0x080178c0 800d230: 200003b0 .word 0x200003b0 800d234: 080178d4 .word 0x080178d4 800d238: 200012e8 .word 0x200012e8 800d23c: 2000006c .word 0x2000006c 800d240: 2000114c .word 0x2000114c 0800d244 : // Колбэк для заполнения данных мониторинга static void monitoring_data_callback(void) { 800d244: b580 push {r7, lr} 800d246: af00 add r7, sp, #0 // Информация о зарядной сессии statusPacket.SOC = CONN.SOC; 800d248: 4b8f ldr r3, [pc, #572] @ (800d488 ) 800d24a: 789a ldrb r2, [r3, #2] 800d24c: 4b8f ldr r3, [pc, #572] @ (800d48c ) 800d24e: 709a strb r2, [r3, #2] statusPacket.Energy = CONN.Energy; 800d250: 4b8d ldr r3, [pc, #564] @ (800d488 ) 800d252: f8d3 3007 ldr.w r3, [r3, #7] 800d256: 4a8d ldr r2, [pc, #564] @ (800d48c ) 800d258: f8c2 3003 str.w r3, [r2, #3] statusPacket.RequestedVoltage = CONN.RequestedVoltage; 800d25c: 4b8a ldr r3, [pc, #552] @ (800d488 ) 800d25e: f8b3 300f ldrh.w r3, [r3, #15] 800d262: b29a uxth r2, r3 800d264: 4b89 ldr r3, [pc, #548] @ (800d48c ) 800d266: f8a3 2007 strh.w r2, [r3, #7] statusPacket.RequestedCurrent = CONN.WantedCurrent; 800d26a: 4b87 ldr r3, [pc, #540] @ (800d488 ) 800d26c: f8b3 301b ldrh.w r3, [r3, #27] 800d270: b29a uxth r2, r3 800d272: 4b86 ldr r3, [pc, #536] @ (800d48c ) 800d274: f8a3 2009 strh.w r2, [r3, #9] statusPacket.MeasuredVoltage = CONN.MeasuredVoltage; 800d278: 4b83 ldr r3, [pc, #524] @ (800d488 ) 800d27a: f8b3 3013 ldrh.w r3, [r3, #19] 800d27e: b29a uxth r2, r3 800d280: 4b82 ldr r3, [pc, #520] @ (800d48c ) 800d282: f8a3 200b strh.w r2, [r3, #11] statusPacket.MeasuredCurrent = CONN.MeasuredCurrent; 800d286: 4b80 ldr r3, [pc, #512] @ (800d488 ) 800d288: f8b3 3015 ldrh.w r3, [r3, #21] 800d28c: b29a uxth r2, r3 800d28e: 4b7f ldr r3, [pc, #508] @ (800d48c ) 800d290: f8a3 200d strh.w r2, [r3, #13] statusPacket.outputEnabled = CONN.outputEnabled; 800d294: 4b7c ldr r3, [pc, #496] @ (800d488 ) 800d296: 7e1a ldrb r2, [r3, #24] 800d298: 4b7c ldr r3, [pc, #496] @ (800d48c ) 800d29a: 73da strb r2, [r3, #15] statusPacket.chargingError = CONN.chargingError; 800d29c: 4b7a ldr r3, [pc, #488] @ (800d488 ) 800d29e: 7f5a ldrb r2, [r3, #29] 800d2a0: 4b7a ldr r3, [pc, #488] @ (800d48c ) 800d2a2: 705a strb r2, [r3, #1] statusPacket.connState = CONN.connState; 800d2a4: 4b78 ldr r3, [pc, #480] @ (800d488 ) 800d2a6: 785a ldrb r2, [r3, #1] 800d2a8: 4b78 ldr r3, [pc, #480] @ (800d48c ) 800d2aa: 701a strb r2, [r3, #0] statusPacket.chargingElapsedTimeMin = 0; 800d2ac: 4b77 ldr r3, [pc, #476] @ (800d48c ) 800d2ae: 2200 movs r2, #0 800d2b0: 741a strb r2, [r3, #16] 800d2b2: 2200 movs r2, #0 800d2b4: 745a strb r2, [r3, #17] statusPacket.chargingElapsedTimeSec = 0; 800d2b6: 4b75 ldr r3, [pc, #468] @ (800d48c ) 800d2b8: 2200 movs r2, #0 800d2ba: 749a strb r2, [r3, #18] statusPacket.estimatedRemainingChargingTime = 0; 800d2bc: 4b73 ldr r3, [pc, #460] @ (800d48c ) 800d2be: 2200 movs r2, #0 800d2c0: 74da strb r2, [r3, #19] 800d2c2: 2200 movs r2, #0 800d2c4: 751a strb r2, [r3, #20] // состояние зарядной станции statusPacket.relayAC = RELAY_Read(RELAY_AC); 800d2c6: 2004 movs r0, #4 800d2c8: f7fc fae6 bl 8009898 800d2cc: 4603 mov r3, r0 800d2ce: f003 0301 and.w r3, r3, #1 800d2d2: b2d9 uxtb r1, r3 800d2d4: 4a6d ldr r2, [pc, #436] @ (800d48c ) 800d2d6: 7d53 ldrb r3, [r2, #21] 800d2d8: f361 0300 bfi r3, r1, #0, #1 800d2dc: 7553 strb r3, [r2, #21] statusPacket.relayDC = RELAY_Read(RELAY_DC); 800d2de: 2003 movs r0, #3 800d2e0: f7fc fada bl 8009898 800d2e4: 4603 mov r3, r0 800d2e6: f003 0301 and.w r3, r3, #1 800d2ea: b2d9 uxtb r1, r3 800d2ec: 4a67 ldr r2, [pc, #412] @ (800d48c ) 800d2ee: 7d53 ldrb r3, [r2, #21] 800d2f0: f361 0341 bfi r3, r1, #1, #1 800d2f4: 7553 strb r3, [r2, #21] statusPacket.relayAUX = RELAY_Read(RELAY_AUX0); 800d2f6: 2000 movs r0, #0 800d2f8: f7fc face bl 8009898 800d2fc: 4603 mov r3, r0 800d2fe: f003 0301 and.w r3, r3, #1 800d302: b2d9 uxtb r1, r3 800d304: 4a61 ldr r2, [pc, #388] @ (800d48c ) 800d306: 7d53 ldrb r3, [r2, #21] 800d308: f361 0382 bfi r3, r1, #2, #1 800d30c: 7553 strb r3, [r2, #21] statusPacket.lockState = 0; 800d30e: 4a5f ldr r2, [pc, #380] @ (800d48c ) 800d310: 7d53 ldrb r3, [r2, #21] 800d312: f023 0308 bic.w r3, r3, #8 800d316: 7553 strb r3, [r2, #21] statusPacket.stopButton = !IN_ReadInput(IN_ESTOP); 800d318: 2003 movs r0, #3 800d31a: f7fc facd bl 80098b8 800d31e: 4603 mov r3, r0 800d320: 2b00 cmp r3, #0 800d322: bf0c ite eq 800d324: 2301 moveq r3, #1 800d326: 2300 movne r3, #0 800d328: b2d9 uxtb r1, r3 800d32a: 4a58 ldr r2, [pc, #352] @ (800d48c ) 800d32c: 7d53 ldrb r3, [r2, #21] 800d32e: f361 1304 bfi r3, r1, #4, #1 800d332: 7553 strb r3, [r2, #21] statusPacket.logAvailable = (debug_buffer_available()>0)?1:0; 800d334: f7fd f898 bl 800a468 800d338: 4603 mov r3, r0 800d33a: 2b00 cmp r3, #0 800d33c: bf14 ite ne 800d33e: 2301 movne r3, #1 800d340: 2300 moveq r3, #0 800d342: b2d9 uxtb r1, r3 800d344: 4a51 ldr r2, [pc, #324] @ (800d48c ) 800d346: 7d53 ldrb r3, [r2, #21] 800d348: f361 1345 bfi r3, r1, #5, #1 800d34c: 7553 strb r3, [r2, #21] statusPacket.evInfoAvailable = 0; 800d34e: 4a4f ldr r2, [pc, #316] @ (800d48c ) 800d350: 7d53 ldrb r3, [r2, #21] 800d352: f023 0340 bic.w r3, r3, #64 @ 0x40 800d356: 7553 strb r3, [r2, #21] statusPacket.psuOnline = PSU0.online; 800d358: 4b4d ldr r3, [pc, #308] @ (800d490 ) 800d35a: 7a1b ldrb r3, [r3, #8] 800d35c: f003 0301 and.w r3, r3, #1 800d360: b2d9 uxtb r1, r3 800d362: 4a4a ldr r2, [pc, #296] @ (800d48c ) 800d364: 7d53 ldrb r3, [r2, #21] 800d366: f361 13c7 bfi r3, r1, #7, #1 800d36a: 7553 strb r3, [r2, #21] statusPacket.tempConnector0 = CONN_ReadTemp(0); // температура коннектора 800d36c: 2000 movs r0, #0 800d36e: f7fc fbc9 bl 8009b04 800d372: 4603 mov r3, r0 800d374: b25a sxtb r2, r3 800d376: 4b45 ldr r3, [pc, #276] @ (800d48c ) 800d378: 765a strb r2, [r3, #25] statusPacket.tempConnector1 = CONN_ReadTemp(1); 800d37a: 2001 movs r0, #1 800d37c: f7fc fbc2 bl 8009b04 800d380: 4603 mov r3, r0 800d382: b25a sxtb r2, r3 800d384: 4b41 ldr r3, [pc, #260] @ (800d48c ) 800d386: 769a strb r2, [r3, #26] statusPacket.tempAmbient = PSU0.tempAmbient; // температура окружающего воздуха 800d388: 4b41 ldr r3, [pc, #260] @ (800d490 ) 800d38a: 6a1b ldr r3, [r3, #32] 800d38c: b25a sxtb r2, r3 800d38e: 4b3f ldr r3, [pc, #252] @ (800d48c ) 800d390: 76da strb r2, [r3, #27] statusPacket.tempBatteryMax = 0; 800d392: 4b3e ldr r3, [pc, #248] @ (800d48c ) 800d394: 2200 movs r2, #0 800d396: 771a strb r2, [r3, #28] statusPacket.tempBatteryMin = 0; 800d398: 4b3c ldr r3, [pc, #240] @ (800d48c ) 800d39a: 2200 movs r2, #0 800d39c: 775a strb r2, [r3, #29] statusPacket.highestVoltageOfBatteryCell = 0; 800d39e: 4b3b ldr r3, [pc, #236] @ (800d48c ) 800d3a0: 2200 movs r2, #0 800d3a2: 779a strb r2, [r3, #30] 800d3a4: 2200 movs r2, #0 800d3a6: 77da strb r2, [r3, #31] statusPacket.batteryStatus = 0; 800d3a8: 4b38 ldr r3, [pc, #224] @ (800d48c ) 800d3aa: 2200 movs r2, #0 800d3ac: f883 2020 strb.w r2, [r3, #32] statusPacket.phaseVoltageAB = PSU_06.VAB; 800d3b0: 4b38 ldr r3, [pc, #224] @ (800d494 ) 800d3b2: 689b ldr r3, [r3, #8] 800d3b4: b29a uxth r2, r3 800d3b6: 4b35 ldr r3, [pc, #212] @ (800d48c ) 800d3b8: f8a3 2021 strh.w r2, [r3, #33] @ 0x21 statusPacket.phaseVoltageBC = PSU_06.VBC; 800d3bc: 4b35 ldr r3, [pc, #212] @ (800d494 ) 800d3be: 68db ldr r3, [r3, #12] 800d3c0: b29a uxth r2, r3 800d3c2: 4b32 ldr r3, [pc, #200] @ (800d48c ) 800d3c4: f8a3 2023 strh.w r2, [r3, #35] @ 0x23 statusPacket.phaseVoltageCA = PSU_06.VCA; 800d3c8: 4b32 ldr r3, [pc, #200] @ (800d494 ) 800d3ca: 691b ldr r3, [r3, #16] 800d3cc: b29a uxth r2, r3 800d3ce: 4b2f ldr r3, [pc, #188] @ (800d48c ) 800d3d0: f8a3 2025 strh.w r2, [r3, #37] @ 0x25 // GBT TODO memset(statusPacket.VIN, 0, sizeof(statusPacket.VIN)); 800d3d4: 2211 movs r2, #17 800d3d6: 2100 movs r1, #0 800d3d8: 482f ldr r0, [pc, #188] @ (800d498 ) 800d3da: f007 fc67 bl 8014cac // GBT TODO statusPacket.batteryType = 0; 800d3de: 4b2b ldr r3, [pc, #172] @ (800d48c ) 800d3e0: 2200 movs r2, #0 800d3e2: f883 2038 strb.w r2, [r3, #56] @ 0x38 statusPacket.batteryCapacity = 0; 800d3e6: 4b29 ldr r3, [pc, #164] @ (800d48c ) 800d3e8: 2200 movs r2, #0 800d3ea: f883 2039 strb.w r2, [r3, #57] @ 0x39 800d3ee: 2200 movs r2, #0 800d3f0: f883 203a strb.w r2, [r3, #58] @ 0x3a statusPacket.batteryVoltage = 0; 800d3f4: 4b25 ldr r3, [pc, #148] @ (800d48c ) 800d3f6: 2200 movs r2, #0 800d3f8: f883 203b strb.w r2, [r3, #59] @ 0x3b 800d3fc: 2200 movs r2, #0 800d3fe: f883 203c strb.w r2, [r3, #60] @ 0x3c memset(statusPacket.batteryVendor, 0, sizeof(statusPacket.batteryVendor)); 800d402: 2204 movs r2, #4 800d404: 2100 movs r1, #0 800d406: 4825 ldr r0, [pc, #148] @ (800d49c ) 800d408: f007 fc50 bl 8014cac statusPacket.batterySN = 0; 800d40c: 4b1f ldr r3, [pc, #124] @ (800d48c ) 800d40e: 2200 movs r2, #0 800d410: f883 2041 strb.w r2, [r3, #65] @ 0x41 800d414: 2200 movs r2, #0 800d416: f883 2042 strb.w r2, [r3, #66] @ 0x42 800d41a: 2200 movs r2, #0 800d41c: f883 2043 strb.w r2, [r3, #67] @ 0x43 800d420: 2200 movs r2, #0 800d422: f883 2044 strb.w r2, [r3, #68] @ 0x44 statusPacket.batteryManuD = 0; 800d426: 4b19 ldr r3, [pc, #100] @ (800d48c ) 800d428: 2200 movs r2, #0 800d42a: f883 2047 strb.w r2, [r3, #71] @ 0x47 statusPacket.batteryManuM = 0; 800d42e: 4b17 ldr r3, [pc, #92] @ (800d48c ) 800d430: 2200 movs r2, #0 800d432: f883 2046 strb.w r2, [r3, #70] @ 0x46 statusPacket.batteryManuY = 0; 800d436: 4b15 ldr r3, [pc, #84] @ (800d48c ) 800d438: 2200 movs r2, #0 800d43a: f883 2045 strb.w r2, [r3, #69] @ 0x45 statusPacket.batteryCycleCount = 0; 800d43e: 4b13 ldr r3, [pc, #76] @ (800d48c ) 800d440: 2200 movs r2, #0 800d442: f883 2048 strb.w r2, [r3, #72] @ 0x48 800d446: 2200 movs r2, #0 800d448: f883 2049 strb.w r2, [r3, #73] @ 0x49 statusPacket.ownAuto = 0; 800d44c: 4b0f ldr r3, [pc, #60] @ (800d48c ) 800d44e: 2200 movs r2, #0 800d450: f883 204a strb.w r2, [r3, #74] @ 0x4a memset(statusPacket.EV_SW_VER, 0, sizeof(statusPacket.EV_SW_VER)); 800d454: 2208 movs r2, #8 800d456: 2100 movs r1, #0 800d458: 4811 ldr r0, [pc, #68] @ (800d4a0 ) 800d45a: f007 fc27 bl 8014cac statusPacket.testMode = 0; 800d45e: 4b0b ldr r3, [pc, #44] @ (800d48c ) 800d460: 2200 movs r2, #0 800d462: f883 2053 strb.w r2, [r3, #83] @ 0x53 statusPacket.testVoltage = 0; 800d466: 4b09 ldr r3, [pc, #36] @ (800d48c ) 800d468: 2200 movs r2, #0 800d46a: f883 2054 strb.w r2, [r3, #84] @ 0x54 800d46e: 2200 movs r2, #0 800d470: f883 2055 strb.w r2, [r3, #85] @ 0x55 statusPacket.testCurrent = 0; 800d474: 4b05 ldr r3, [pc, #20] @ (800d48c ) 800d476: 2200 movs r2, #0 800d478: f883 2056 strb.w r2, [r3, #86] @ 0x56 800d47c: 2200 movs r2, #0 800d47e: f883 2057 strb.w r2, [r3, #87] @ 0x57 // В debug.c есть CONN_SetState, предполагаем наличие CONN_GetState() // Если такой функции нет, закомментируйте следующую строку: // statusPacket.connState = CONN_GetState(); } 800d482: bf00 nop 800d484: bd80 pop {r7, pc} 800d486: bf00 nop 800d488: 200003b0 .word 0x200003b0 800d48c: 20001158 .word 0x20001158 800d490: 20000904 .word 0x20000904 800d494: 200008d8 .word 0x200008d8 800d498: 2000117f .word 0x2000117f 800d49c: 20001195 .word 0x20001195 800d4a0: 200011a3 .word 0x200011a3 0800d4a4 : #include "sma_filter.h" void SMAFilter_Init(SMAFilter_t* f) { 800d4a4: b480 push {r7} 800d4a6: b085 sub sp, #20 800d4a8: af00 add r7, sp, #0 800d4aa: 6078 str r0, [r7, #4] if (f == 0) return; 800d4ac: 687b ldr r3, [r7, #4] 800d4ae: 2b00 cmp r3, #0 800d4b0: d018 beq.n 800d4e4 f->sum = 0; 800d4b2: 687b ldr r3, [r7, #4] 800d4b4: 2200 movs r2, #0 800d4b6: 601a str r2, [r3, #0] f->idx = 0; 800d4b8: 687b ldr r3, [r7, #4] 800d4ba: 2200 movs r2, #0 800d4bc: 809a strh r2, [r3, #4] f->count = 0; 800d4be: 687b ldr r3, [r7, #4] 800d4c0: 2200 movs r2, #0 800d4c2: 80da strh r2, [r3, #6] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800d4c4: 2300 movs r3, #0 800d4c6: 81fb strh r3, [r7, #14] 800d4c8: e008 b.n 800d4dc f->buffer[i] = 0; 800d4ca: 89fa ldrh r2, [r7, #14] 800d4cc: 687b ldr r3, [r7, #4] 800d4ce: 3202 adds r2, #2 800d4d0: 2100 movs r1, #0 800d4d2: f843 1022 str.w r1, [r3, r2, lsl #2] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800d4d6: 89fb ldrh r3, [r7, #14] 800d4d8: 3301 adds r3, #1 800d4da: 81fb strh r3, [r7, #14] 800d4dc: 89fb ldrh r3, [r7, #14] 800d4de: 2b07 cmp r3, #7 800d4e0: d9f3 bls.n 800d4ca 800d4e2: e000 b.n 800d4e6 if (f == 0) return; 800d4e4: bf00 nop } } 800d4e6: 3714 adds r7, #20 800d4e8: 46bd mov sp, r7 800d4ea: bc80 pop {r7} 800d4ec: 4770 bx lr 0800d4ee : int32_t SMAFilter_Update(SMAFilter_t* f, int32_t x) { 800d4ee: b480 push {r7} 800d4f0: b085 sub sp, #20 800d4f2: af00 add r7, sp, #0 800d4f4: 6078 str r0, [r7, #4] 800d4f6: 6039 str r1, [r7, #0] if (f == 0) return x; 800d4f8: 687b ldr r3, [r7, #4] 800d4fa: 2b00 cmp r3, #0 800d4fc: d101 bne.n 800d502 800d4fe: 683b ldr r3, [r7, #0] 800d500: e056 b.n 800d5b0 // Пока окно не заполнено полностью, делим по фактическому count. if (f->count < SMA_FILTER_WINDOW) { 800d502: 687b ldr r3, [r7, #4] 800d504: 88db ldrh r3, [r3, #6] 800d506: 2b07 cmp r3, #7 800d508: d827 bhi.n 800d55a f->buffer[f->idx] = x; 800d50a: 687b ldr r3, [r7, #4] 800d50c: 889b ldrh r3, [r3, #4] 800d50e: 461a mov r2, r3 800d510: 687b ldr r3, [r7, #4] 800d512: 3202 adds r2, #2 800d514: 6839 ldr r1, [r7, #0] 800d516: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += x; 800d51a: 687b ldr r3, [r7, #4] 800d51c: 681a ldr r2, [r3, #0] 800d51e: 683b ldr r3, [r7, #0] 800d520: 441a add r2, r3 800d522: 687b ldr r3, [r7, #4] 800d524: 601a str r2, [r3, #0] f->idx++; 800d526: 687b ldr r3, [r7, #4] 800d528: 889b ldrh r3, [r3, #4] 800d52a: 3301 adds r3, #1 800d52c: b29a uxth r2, r3 800d52e: 687b ldr r3, [r7, #4] 800d530: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800d532: 687b ldr r3, [r7, #4] 800d534: 889b ldrh r3, [r3, #4] 800d536: 2b07 cmp r3, #7 800d538: d902 bls.n 800d540 800d53a: 687b ldr r3, [r7, #4] 800d53c: 2200 movs r2, #0 800d53e: 809a strh r2, [r3, #4] f->count++; 800d540: 687b ldr r3, [r7, #4] 800d542: 88db ldrh r3, [r3, #6] 800d544: 3301 adds r3, #1 800d546: b29a uxth r2, r3 800d548: 687b ldr r3, [r7, #4] 800d54a: 80da strh r2, [r3, #6] return (int32_t)(f->sum / (int32_t)f->count); 800d54c: 687b ldr r3, [r7, #4] 800d54e: 681b ldr r3, [r3, #0] 800d550: 687a ldr r2, [r7, #4] 800d552: 88d2 ldrh r2, [r2, #6] 800d554: fb93 f3f2 sdiv r3, r3, r2 800d558: e02a b.n 800d5b0 } // Окно заполнено: "вычитаем старое + добавляем новое". int32_t old = f->buffer[f->idx]; 800d55a: 687b ldr r3, [r7, #4] 800d55c: 889b ldrh r3, [r3, #4] 800d55e: 461a mov r2, r3 800d560: 687b ldr r3, [r7, #4] 800d562: 3202 adds r2, #2 800d564: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800d568: 60fb str r3, [r7, #12] f->buffer[f->idx] = x; 800d56a: 687b ldr r3, [r7, #4] 800d56c: 889b ldrh r3, [r3, #4] 800d56e: 461a mov r2, r3 800d570: 687b ldr r3, [r7, #4] 800d572: 3202 adds r2, #2 800d574: 6839 ldr r1, [r7, #0] 800d576: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += (x - old); 800d57a: 687b ldr r3, [r7, #4] 800d57c: 681a ldr r2, [r3, #0] 800d57e: 6839 ldr r1, [r7, #0] 800d580: 68fb ldr r3, [r7, #12] 800d582: 1acb subs r3, r1, r3 800d584: 441a add r2, r3 800d586: 687b ldr r3, [r7, #4] 800d588: 601a str r2, [r3, #0] f->idx++; 800d58a: 687b ldr r3, [r7, #4] 800d58c: 889b ldrh r3, [r3, #4] 800d58e: 3301 adds r3, #1 800d590: b29a uxth r2, r3 800d592: 687b ldr r3, [r7, #4] 800d594: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800d596: 687b ldr r3, [r7, #4] 800d598: 889b ldrh r3, [r3, #4] 800d59a: 2b07 cmp r3, #7 800d59c: d902 bls.n 800d5a4 800d59e: 687b ldr r3, [r7, #4] 800d5a0: 2200 movs r2, #0 800d5a2: 809a strh r2, [r3, #4] return (int32_t)(f->sum / (int32_t)SMA_FILTER_WINDOW); 800d5a4: 687b ldr r3, [r7, #4] 800d5a6: 681b ldr r3, [r3, #0] 800d5a8: 2b00 cmp r3, #0 800d5aa: da00 bge.n 800d5ae 800d5ac: 3307 adds r3, #7 800d5ae: 10db asrs r3, r3, #3 } 800d5b0: 4618 mov r0, r3 800d5b2: 3714 adds r7, #20 800d5b4: 46bd mov sp, r7 800d5b6: bc80 pop {r7} 800d5b8: 4770 bx lr ... 0800d5bc : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800d5bc: b480 push {r7} 800d5be: b085 sub sp, #20 800d5c0: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 800d5c2: 4b15 ldr r3, [pc, #84] @ (800d618 ) 800d5c4: 699b ldr r3, [r3, #24] 800d5c6: 4a14 ldr r2, [pc, #80] @ (800d618 ) 800d5c8: f043 0301 orr.w r3, r3, #1 800d5cc: 6193 str r3, [r2, #24] 800d5ce: 4b12 ldr r3, [pc, #72] @ (800d618 ) 800d5d0: 699b ldr r3, [r3, #24] 800d5d2: f003 0301 and.w r3, r3, #1 800d5d6: 60bb str r3, [r7, #8] 800d5d8: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800d5da: 4b0f ldr r3, [pc, #60] @ (800d618 ) 800d5dc: 69db ldr r3, [r3, #28] 800d5de: 4a0e ldr r2, [pc, #56] @ (800d618 ) 800d5e0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800d5e4: 61d3 str r3, [r2, #28] 800d5e6: 4b0c ldr r3, [pc, #48] @ (800d618 ) 800d5e8: 69db ldr r3, [r3, #28] 800d5ea: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800d5ee: 607b str r3, [r7, #4] 800d5f0: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 800d5f2: 4b0a ldr r3, [pc, #40] @ (800d61c ) 800d5f4: 685b ldr r3, [r3, #4] 800d5f6: 60fb str r3, [r7, #12] 800d5f8: 68fb ldr r3, [r7, #12] 800d5fa: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 800d5fe: 60fb str r3, [r7, #12] 800d600: 68fb ldr r3, [r7, #12] 800d602: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 800d606: 60fb str r3, [r7, #12] 800d608: 4a04 ldr r2, [pc, #16] @ (800d61c ) 800d60a: 68fb ldr r3, [r7, #12] 800d60c: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800d60e: bf00 nop 800d610: 3714 adds r7, #20 800d612: 46bd mov sp, r7 800d614: bc80 pop {r7} 800d616: 4770 bx lr 800d618: 40021000 .word 0x40021000 800d61c: 40010000 .word 0x40010000 0800d620 : { /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800d620: e7fe b.n 800d620 800d622: bf00 nop 0800d624 : void HardFault_Handler(void) { /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800d624: e7fe b.n 800d624 800d626: bf00 nop 0800d628 : void MemManage_Handler(void) { /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800d628: e7fe b.n 800d628 800d62a: bf00 nop 0800d62c : void BusFault_Handler(void) { /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800d62c: e7fe b.n 800d62c 800d62e: bf00 nop 0800d630 : void UsageFault_Handler(void) { /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 800d630: e7fe b.n 800d630 800d632: bf00 nop 0800d634 : /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800d634: 4770 bx lr 800d636: bf00 nop 0800d638 : /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800d638: 4770 bx lr 800d63a: bf00 nop 0800d63c : /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800d63c: 4770 bx lr 800d63e: bf00 nop 0800d640 : void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800d640: f000 be68 b.w 800e314 0800d644 : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { 800d644: b510 push {r4, lr} /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800d646: 4c09 ldr r4, [pc, #36] @ (800d66c ) 800d648: 2201 movs r2, #1 800d64a: f44f 6100 mov.w r1, #2048 @ 0x800 800d64e: 4620 mov r0, r4 800d650: f003 fa09 bl 8010a66 /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 800d654: 4806 ldr r0, [pc, #24] @ (800d670 ) 800d656: f002 fdf7 bl 8010248 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d65a: 4620 mov r0, r4 /* USER CODE END DMA1_Channel1_IRQn 1 */ } 800d65c: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d660: 2200 movs r2, #0 800d662: f44f 6100 mov.w r1, #2048 @ 0x800 800d666: f003 b9fe b.w 8010a66 800d66a: bf00 nop 800d66c: 40010c00 .word 0x40010c00 800d670: 200002c0 .word 0x200002c0 0800d674 : void DMA1_Channel2_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ /* USER CODE END DMA1_Channel2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart3_tx); 800d674: 4801 ldr r0, [pc, #4] @ (800d67c ) 800d676: f002 bde7 b.w 8010248 800d67a: bf00 nop 800d67c: 20001444 .word 0x20001444 0800d680 : void DMA1_Channel3_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel3_IRQn 0 */ /* USER CODE END DMA1_Channel3_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart3_rx); 800d680: 4801 ldr r0, [pc, #4] @ (800d688 ) 800d682: f002 bde1 b.w 8010248 800d686: bf00 nop 800d688: 20001400 .word 0x20001400 0800d68c : void DMA1_Channel6_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel6_IRQn 0 */ /* USER CODE END DMA1_Channel6_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_rx); 800d68c: 4801 ldr r0, [pc, #4] @ (800d694 ) 800d68e: f002 bddb b.w 8010248 800d692: bf00 nop 800d694: 20001378 .word 0x20001378 0800d698 : void DMA1_Channel7_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel7_IRQn 0 */ /* USER CODE END DMA1_Channel7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_tx); 800d698: 4801 ldr r0, [pc, #4] @ (800d6a0 ) 800d69a: f002 bdd5 b.w 8010248 800d69e: bf00 nop 800d6a0: 200013bc .word 0x200013bc 0800d6a4 : /** * @brief This function handles ADC1 and ADC2 global interrupts. */ void ADC1_2_IRQHandler(void) { 800d6a4: b510 push {r4, lr} /* USER CODE BEGIN ADC1_2_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800d6a6: 4c09 ldr r4, [pc, #36] @ (800d6cc ) 800d6a8: 2201 movs r2, #1 800d6aa: f44f 6100 mov.w r1, #2048 @ 0x800 800d6ae: 4620 mov r0, r4 800d6b0: f003 f9d9 bl 8010a66 /* USER CODE END ADC1_2_IRQn 0 */ HAL_ADC_IRQHandler(&hadc1); 800d6b4: 4806 ldr r0, [pc, #24] @ (800d6d0 ) 800d6b6: f001 f823 bl 800e700 /* USER CODE BEGIN ADC1_2_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d6ba: 4620 mov r0, r4 /* USER CODE END ADC1_2_IRQn 1 */ } 800d6bc: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d6c0: 2200 movs r2, #0 800d6c2: f44f 6100 mov.w r1, #2048 @ 0x800 800d6c6: f003 b9ce b.w 8010a66 800d6ca: bf00 nop 800d6cc: 40010c00 .word 0x40010c00 800d6d0: 20000290 .word 0x20000290 0800d6d4 : /** * @brief This function handles CAN1 RX0 interrupt. */ void CAN1_RX0_IRQHandler(void) { 800d6d4: b510 push {r4, lr} /* USER CODE BEGIN CAN1_RX0_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800d6d6: 4c09 ldr r4, [pc, #36] @ (800d6fc ) 800d6d8: 2201 movs r2, #1 800d6da: f44f 6180 mov.w r1, #1024 @ 0x400 800d6de: 4620 mov r0, r4 800d6e0: f003 f9c1 bl 8010a66 /* USER CODE END CAN1_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan1); 800d6e4: 4806 ldr r0, [pc, #24] @ (800d700 ) 800d6e6: f002 f847 bl 800f778 /* USER CODE BEGIN CAN1_RX0_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d6ea: 4620 mov r0, r4 /* USER CODE END CAN1_RX0_IRQn 1 */ } 800d6ec: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d6f0: 2200 movs r2, #0 800d6f2: f44f 6180 mov.w r1, #1024 @ 0x400 800d6f6: f003 b9b6 b.w 8010a66 800d6fa: bf00 nop 800d6fc: 40010c00 .word 0x40010c00 800d700: 2000035c .word 0x2000035c 0800d704 : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 800d704: b510 push {r4, lr} /* USER CODE BEGIN TIM3_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800d706: 4c09 ldr r4, [pc, #36] @ (800d72c ) 800d708: 2201 movs r2, #1 800d70a: f44f 6100 mov.w r1, #2048 @ 0x800 800d70e: 4620 mov r0, r4 800d710: f003 f9a9 bl 8010a66 /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 800d714: 4806 ldr r0, [pc, #24] @ (800d730 ) 800d716: f004 fd87 bl 8012228 /* USER CODE BEGIN TIM3_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d71a: 4620 mov r0, r4 /* USER CODE END TIM3_IRQn 1 */ } 800d71c: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d720: 2200 movs r2, #0 800d722: f44f 6100 mov.w r1, #2048 @ 0x800 800d726: f003 b99e b.w 8010a66 800d72a: bf00 nop 800d72c: 40010c00 .word 0x40010c00 800d730: 200011c8 .word 0x200011c8 0800d734 : void USART1_IRQHandler(void) { /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 800d734: 4801 ldr r0, [pc, #4] @ (800d73c ) 800d736: f005 be2d b.w 8013394 800d73a: bf00 nop 800d73c: 200012a0 .word 0x200012a0 0800d740 : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 800d740: b510 push {r4, lr} /* USER CODE BEGIN USART2_IRQn 0 */ HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_SET); 800d742: 4c08 ldr r4, [pc, #32] @ (800d764 ) 800d744: 2201 movs r2, #1 800d746: 2120 movs r1, #32 800d748: 4620 mov r0, r4 800d74a: f003 f98c bl 8010a66 /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 800d74e: 4806 ldr r0, [pc, #24] @ (800d768 ) 800d750: f005 fe20 bl 8013394 /* USER CODE BEGIN USART2_IRQn 1 */ HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_RESET); 800d754: 4620 mov r0, r4 /* USER CODE END USART2_IRQn 1 */ } 800d756: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_RESET); 800d75a: 2200 movs r2, #0 800d75c: 2120 movs r1, #32 800d75e: f003 b982 b.w 8010a66 800d762: bf00 nop 800d764: 40010800 .word 0x40010800 800d768: 200012e8 .word 0x200012e8 0800d76c : /** * @brief This function handles USART3 global interrupt. */ void USART3_IRQHandler(void) { 800d76c: b510 push {r4, lr} /* USER CODE BEGIN USART3_IRQn 0 */ HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_SET); 800d76e: 4c08 ldr r4, [pc, #32] @ (800d790 ) 800d770: 2201 movs r2, #1 800d772: 2140 movs r1, #64 @ 0x40 800d774: 4620 mov r0, r4 800d776: f003 f976 bl 8010a66 /* USER CODE END USART3_IRQn 0 */ HAL_UART_IRQHandler(&huart3); 800d77a: 4806 ldr r0, [pc, #24] @ (800d794 ) 800d77c: f005 fe0a bl 8013394 /* USER CODE BEGIN USART3_IRQn 1 */ HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_RESET); 800d780: 4620 mov r0, r4 /* USER CODE END USART3_IRQn 1 */ } 800d782: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_RESET); 800d786: 2200 movs r2, #0 800d788: 2140 movs r1, #64 @ 0x40 800d78a: f003 b96c b.w 8010a66 800d78e: bf00 nop 800d790: 40010800 .word 0x40010800 800d794: 20001330 .word 0x20001330 0800d798 : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 800d798: b510 push {r4, lr} /* USER CODE BEGIN UART5_IRQn 0 */ HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_SET); 800d79a: 4c08 ldr r4, [pc, #32] @ (800d7bc ) 800d79c: 2201 movs r2, #1 800d79e: 2104 movs r1, #4 800d7a0: 4620 mov r0, r4 800d7a2: f003 f960 bl 8010a66 /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 800d7a6: 4806 ldr r0, [pc, #24] @ (800d7c0 ) 800d7a8: f005 fdf4 bl 8013394 /* USER CODE BEGIN UART5_IRQn 1 */ HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_RESET); 800d7ac: 4620 mov r0, r4 /* USER CODE END UART5_IRQn 1 */ } 800d7ae: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_RESET); 800d7b2: 2200 movs r2, #0 800d7b4: 2104 movs r1, #4 800d7b6: f003 b956 b.w 8010a66 800d7ba: bf00 nop 800d7bc: 40011000 .word 0x40011000 800d7c0: 20001258 .word 0x20001258 0800d7c4 : /** * @brief This function handles CAN2 TX interrupt. */ void CAN2_TX_IRQHandler(void) { 800d7c4: b510 push {r4, lr} /* USER CODE BEGIN CAN2_TX_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800d7c6: 4c09 ldr r4, [pc, #36] @ (800d7ec ) 800d7c8: 2201 movs r2, #1 800d7ca: f44f 6180 mov.w r1, #1024 @ 0x400 800d7ce: 4620 mov r0, r4 800d7d0: f003 f949 bl 8010a66 /* USER CODE END CAN2_TX_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800d7d4: 4806 ldr r0, [pc, #24] @ (800d7f0 ) 800d7d6: f001 ffcf bl 800f778 /* USER CODE BEGIN CAN2_TX_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d7da: 4620 mov r0, r4 /* USER CODE END CAN2_TX_IRQn 1 */ } 800d7dc: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d7e0: 2200 movs r2, #0 800d7e2: f44f 6180 mov.w r1, #1024 @ 0x400 800d7e6: f003 b93e b.w 8010a66 800d7ea: bf00 nop 800d7ec: 40010c00 .word 0x40010c00 800d7f0: 20000384 .word 0x20000384 0800d7f4 : /** * @brief This function handles CAN2 RX1 interrupt. */ void CAN2_RX1_IRQHandler(void) { 800d7f4: b510 push {r4, lr} /* USER CODE BEGIN CAN2_RX1_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800d7f6: 4c09 ldr r4, [pc, #36] @ (800d81c ) 800d7f8: 2201 movs r2, #1 800d7fa: f44f 6180 mov.w r1, #1024 @ 0x400 800d7fe: 4620 mov r0, r4 800d800: f003 f931 bl 8010a66 /* USER CODE END CAN2_RX1_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800d804: 4806 ldr r0, [pc, #24] @ (800d820 ) 800d806: f001 ffb7 bl 800f778 /* USER CODE BEGIN CAN2_RX1_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d80a: 4620 mov r0, r4 /* USER CODE END CAN2_RX1_IRQn 1 */ } 800d80c: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d810: 2200 movs r2, #0 800d812: f44f 6180 mov.w r1, #1024 @ 0x400 800d816: f003 b926 b.w 8010a66 800d81a: bf00 nop 800d81c: 40010c00 .word 0x40010c00 800d820: 20000384 .word 0x20000384 0800d824 <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 800d824: b480 push {r7} 800d826: af00 add r7, sp, #0 return 1; 800d828: 2301 movs r3, #1 } 800d82a: 4618 mov r0, r3 800d82c: 46bd mov sp, r7 800d82e: bc80 pop {r7} 800d830: 4770 bx lr 0800d832 <_kill>: int _kill(int pid, int sig) { 800d832: b580 push {r7, lr} 800d834: b082 sub sp, #8 800d836: af00 add r7, sp, #0 800d838: 6078 str r0, [r7, #4] 800d83a: 6039 str r1, [r7, #0] (void)pid; (void)sig; errno = EINVAL; 800d83c: f007 fa3e bl 8014cbc <__errno> 800d840: 4603 mov r3, r0 800d842: 2216 movs r2, #22 800d844: 601a str r2, [r3, #0] return -1; 800d846: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800d84a: 4618 mov r0, r3 800d84c: 3708 adds r7, #8 800d84e: 46bd mov sp, r7 800d850: bd80 pop {r7, pc} 0800d852 <_exit>: void _exit (int status) { 800d852: b580 push {r7, lr} 800d854: b082 sub sp, #8 800d856: af00 add r7, sp, #0 800d858: 6078 str r0, [r7, #4] _kill(status, -1); 800d85a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800d85e: 6878 ldr r0, [r7, #4] 800d860: f7ff ffe7 bl 800d832 <_kill> while (1) {} /* Make sure we hang here */ 800d864: bf00 nop 800d866: e7fd b.n 800d864 <_exit+0x12> 0800d868 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 800d868: b580 push {r7, lr} 800d86a: b086 sub sp, #24 800d86c: af00 add r7, sp, #0 800d86e: 60f8 str r0, [r7, #12] 800d870: 60b9 str r1, [r7, #8] 800d872: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800d874: 2300 movs r3, #0 800d876: 617b str r3, [r7, #20] 800d878: e00a b.n 800d890 <_read+0x28> { *ptr++ = __io_getchar(); 800d87a: f3af 8000 nop.w 800d87e: 4601 mov r1, r0 800d880: 68bb ldr r3, [r7, #8] 800d882: 1c5a adds r2, r3, #1 800d884: 60ba str r2, [r7, #8] 800d886: b2ca uxtb r2, r1 800d888: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 800d88a: 697b ldr r3, [r7, #20] 800d88c: 3301 adds r3, #1 800d88e: 617b str r3, [r7, #20] 800d890: 697a ldr r2, [r7, #20] 800d892: 687b ldr r3, [r7, #4] 800d894: 429a cmp r2, r3 800d896: dbf0 blt.n 800d87a <_read+0x12> } return len; 800d898: 687b ldr r3, [r7, #4] } 800d89a: 4618 mov r0, r3 800d89c: 3718 adds r7, #24 800d89e: 46bd mov sp, r7 800d8a0: bd80 pop {r7, pc} 0800d8a2 <_close>: } return len; } int _close(int file) { 800d8a2: b480 push {r7} 800d8a4: b083 sub sp, #12 800d8a6: af00 add r7, sp, #0 800d8a8: 6078 str r0, [r7, #4] (void)file; return -1; 800d8aa: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800d8ae: 4618 mov r0, r3 800d8b0: 370c adds r7, #12 800d8b2: 46bd mov sp, r7 800d8b4: bc80 pop {r7} 800d8b6: 4770 bx lr 0800d8b8 <_fstat>: int _fstat(int file, struct stat *st) { 800d8b8: b480 push {r7} 800d8ba: b083 sub sp, #12 800d8bc: af00 add r7, sp, #0 800d8be: 6078 str r0, [r7, #4] 800d8c0: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 800d8c2: 683b ldr r3, [r7, #0] 800d8c4: f44f 5200 mov.w r2, #8192 @ 0x2000 800d8c8: 605a str r2, [r3, #4] return 0; 800d8ca: 2300 movs r3, #0 } 800d8cc: 4618 mov r0, r3 800d8ce: 370c adds r7, #12 800d8d0: 46bd mov sp, r7 800d8d2: bc80 pop {r7} 800d8d4: 4770 bx lr 0800d8d6 <_isatty>: int _isatty(int file) { 800d8d6: b480 push {r7} 800d8d8: b083 sub sp, #12 800d8da: af00 add r7, sp, #0 800d8dc: 6078 str r0, [r7, #4] (void)file; return 1; 800d8de: 2301 movs r3, #1 } 800d8e0: 4618 mov r0, r3 800d8e2: 370c adds r7, #12 800d8e4: 46bd mov sp, r7 800d8e6: bc80 pop {r7} 800d8e8: 4770 bx lr 0800d8ea <_lseek>: int _lseek(int file, int ptr, int dir) { 800d8ea: b480 push {r7} 800d8ec: b085 sub sp, #20 800d8ee: af00 add r7, sp, #0 800d8f0: 60f8 str r0, [r7, #12] 800d8f2: 60b9 str r1, [r7, #8] 800d8f4: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 800d8f6: 2300 movs r3, #0 } 800d8f8: 4618 mov r0, r3 800d8fa: 3714 adds r7, #20 800d8fc: 46bd mov sp, r7 800d8fe: bc80 pop {r7} 800d900: 4770 bx lr ... 0800d904 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 800d904: b580 push {r7, lr} 800d906: b086 sub sp, #24 800d908: af00 add r7, sp, #0 800d90a: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 800d90c: 4a14 ldr r2, [pc, #80] @ (800d960 <_sbrk+0x5c>) 800d90e: 4b15 ldr r3, [pc, #84] @ (800d964 <_sbrk+0x60>) 800d910: 1ad3 subs r3, r2, r3 800d912: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 800d914: 697b ldr r3, [r7, #20] 800d916: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 800d918: 4b13 ldr r3, [pc, #76] @ (800d968 <_sbrk+0x64>) 800d91a: 681b ldr r3, [r3, #0] 800d91c: 2b00 cmp r3, #0 800d91e: d102 bne.n 800d926 <_sbrk+0x22> { __sbrk_heap_end = &_end; 800d920: 4b11 ldr r3, [pc, #68] @ (800d968 <_sbrk+0x64>) 800d922: 4a12 ldr r2, [pc, #72] @ (800d96c <_sbrk+0x68>) 800d924: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 800d926: 4b10 ldr r3, [pc, #64] @ (800d968 <_sbrk+0x64>) 800d928: 681a ldr r2, [r3, #0] 800d92a: 687b ldr r3, [r7, #4] 800d92c: 4413 add r3, r2 800d92e: 693a ldr r2, [r7, #16] 800d930: 429a cmp r2, r3 800d932: d207 bcs.n 800d944 <_sbrk+0x40> { errno = ENOMEM; 800d934: f007 f9c2 bl 8014cbc <__errno> 800d938: 4603 mov r3, r0 800d93a: 220c movs r2, #12 800d93c: 601a str r2, [r3, #0] return (void *)-1; 800d93e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800d942: e009 b.n 800d958 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 800d944: 4b08 ldr r3, [pc, #32] @ (800d968 <_sbrk+0x64>) 800d946: 681b ldr r3, [r3, #0] 800d948: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 800d94a: 4b07 ldr r3, [pc, #28] @ (800d968 <_sbrk+0x64>) 800d94c: 681a ldr r2, [r3, #0] 800d94e: 687b ldr r3, [r7, #4] 800d950: 4413 add r3, r2 800d952: 4a05 ldr r2, [pc, #20] @ (800d968 <_sbrk+0x64>) 800d954: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 800d956: 68fb ldr r3, [r7, #12] } 800d958: 4618 mov r0, r3 800d95a: 3718 adds r7, #24 800d95c: 46bd mov sp, r7 800d95e: bd80 pop {r7, pc} 800d960: 20010000 .word 0x20010000 800d964: 00000400 .word 0x00000400 800d968: 200011c4 .word 0x200011c4 800d96c: 200015d8 .word 0x200015d8 0800d970 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 800d970: b480 push {r7} 800d972: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 800d974: bf00 nop 800d976: 46bd mov sp, r7 800d978: bc80 pop {r7} 800d97a: 4770 bx lr 0800d97c : TIM_HandleTypeDef htim3; TIM_HandleTypeDef htim4; /* TIM3 init function */ void MX_TIM3_Init(void) { 800d97c: b580 push {r7, lr} 800d97e: b08e sub sp, #56 @ 0x38 800d980: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800d982: f107 0328 add.w r3, r7, #40 @ 0x28 800d986: 2200 movs r2, #0 800d988: 601a str r2, [r3, #0] 800d98a: 605a str r2, [r3, #4] 800d98c: 609a str r2, [r3, #8] 800d98e: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800d990: f107 0320 add.w r3, r7, #32 800d994: 2200 movs r2, #0 800d996: 601a str r2, [r3, #0] 800d998: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800d99a: 1d3b adds r3, r7, #4 800d99c: 2200 movs r2, #0 800d99e: 601a str r2, [r3, #0] 800d9a0: 605a str r2, [r3, #4] 800d9a2: 609a str r2, [r3, #8] 800d9a4: 60da str r2, [r3, #12] 800d9a6: 611a str r2, [r3, #16] 800d9a8: 615a str r2, [r3, #20] 800d9aa: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 800d9ac: 4b38 ldr r3, [pc, #224] @ (800da90 ) 800d9ae: 4a39 ldr r2, [pc, #228] @ (800da94 ) 800d9b0: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 800d9b2: 4b37 ldr r3, [pc, #220] @ (800da90 ) 800d9b4: 2200 movs r2, #0 800d9b6: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 800d9b8: 4b35 ldr r3, [pc, #212] @ (800da90 ) 800d9ba: 2200 movs r2, #0 800d9bc: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 800d9be: 4b34 ldr r3, [pc, #208] @ (800da90 ) 800d9c0: f64f 72ff movw r2, #65535 @ 0xffff 800d9c4: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800d9c6: 4b32 ldr r3, [pc, #200] @ (800da90 ) 800d9c8: 2200 movs r2, #0 800d9ca: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800d9cc: 4b30 ldr r3, [pc, #192] @ (800da90 ) 800d9ce: 2200 movs r2, #0 800d9d0: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 800d9d2: 482f ldr r0, [pc, #188] @ (800da90 ) 800d9d4: f004 f9d5 bl 8011d82 800d9d8: 4603 mov r3, r0 800d9da: 2b00 cmp r3, #0 800d9dc: d001 beq.n 800d9e2 { Error_Handler(); 800d9de: f7fd f951 bl 800ac84 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800d9e2: f44f 5380 mov.w r3, #4096 @ 0x1000 800d9e6: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 800d9e8: f107 0328 add.w r3, r7, #40 @ 0x28 800d9ec: 4619 mov r1, r3 800d9ee: 4828 ldr r0, [pc, #160] @ (800da90 ) 800d9f0: f004 fe28 bl 8012644 800d9f4: 4603 mov r3, r0 800d9f6: 2b00 cmp r3, #0 800d9f8: d001 beq.n 800d9fe { Error_Handler(); 800d9fa: f7fd f943 bl 800ac84 } if (HAL_TIM_OC_Init(&htim3) != HAL_OK) 800d9fe: 4824 ldr r0, [pc, #144] @ (800da90 ) 800da00: f004 fa0e bl 8011e20 800da04: 4603 mov r3, r0 800da06: 2b00 cmp r3, #0 800da08: d001 beq.n 800da0e { Error_Handler(); 800da0a: f7fd f93b bl 800ac84 } if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 800da0e: 4820 ldr r0, [pc, #128] @ (800da90 ) 800da10: f004 fb08 bl 8012024 800da14: 4603 mov r3, r0 800da16: 2b00 cmp r3, #0 800da18: d001 beq.n 800da1e { Error_Handler(); 800da1a: f7fd f933 bl 800ac84 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_OC1; 800da1e: 2330 movs r3, #48 @ 0x30 800da20: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800da22: 2300 movs r3, #0 800da24: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800da26: f107 0320 add.w r3, r7, #32 800da2a: 4619 mov r1, r3 800da2c: 4818 ldr r0, [pc, #96] @ (800da90 ) 800da2e: f005 f9b7 bl 8012da0 800da32: 4603 mov r3, r0 800da34: 2b00 cmp r3, #0 800da36: d001 beq.n 800da3c { Error_Handler(); 800da38: f7fd f924 bl 800ac84 } sConfigOC.OCMode = TIM_OCMODE_TIMING; 800da3c: 2300 movs r3, #0 800da3e: 607b str r3, [r7, #4] sConfigOC.Pulse = 1; 800da40: 2301 movs r3, #1 800da42: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800da44: 2300 movs r3, #0 800da46: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800da48: 2300 movs r3, #0 800da4a: 617b str r3, [r7, #20] if (HAL_TIM_OC_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 800da4c: 1d3b adds r3, r7, #4 800da4e: 2200 movs r2, #0 800da50: 4619 mov r1, r3 800da52: 480f ldr r0, [pc, #60] @ (800da90 ) 800da54: f004 fcd8 bl 8012408 800da58: 4603 mov r3, r0 800da5a: 2b00 cmp r3, #0 800da5c: d001 beq.n 800da62 { Error_Handler(); 800da5e: f7fd f911 bl 800ac84 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800da62: 2360 movs r3, #96 @ 0x60 800da64: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800da66: 2300 movs r3, #0 800da68: 60bb str r3, [r7, #8] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800da6a: 1d3b adds r3, r7, #4 800da6c: 2204 movs r2, #4 800da6e: 4619 mov r1, r3 800da70: 4807 ldr r0, [pc, #28] @ (800da90 ) 800da72: f004 fd25 bl 80124c0 800da76: 4603 mov r3, r0 800da78: 2b00 cmp r3, #0 800da7a: d001 beq.n 800da80 { Error_Handler(); 800da7c: f7fd f902 bl 800ac84 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 800da80: 4803 ldr r0, [pc, #12] @ (800da90 ) 800da82: f000 f8cf bl 800dc24 } 800da86: bf00 nop 800da88: 3738 adds r7, #56 @ 0x38 800da8a: 46bd mov sp, r7 800da8c: bd80 pop {r7, pc} 800da8e: bf00 nop 800da90: 200011c8 .word 0x200011c8 800da94: 40000400 .word 0x40000400 0800da98 : /* TIM4 init function */ void MX_TIM4_Init(void) { 800da98: b580 push {r7, lr} 800da9a: b08e sub sp, #56 @ 0x38 800da9c: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800da9e: f107 0328 add.w r3, r7, #40 @ 0x28 800daa2: 2200 movs r2, #0 800daa4: 601a str r2, [r3, #0] 800daa6: 605a str r2, [r3, #4] 800daa8: 609a str r2, [r3, #8] 800daaa: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800daac: f107 0320 add.w r3, r7, #32 800dab0: 2200 movs r2, #0 800dab2: 601a str r2, [r3, #0] 800dab4: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800dab6: 1d3b adds r3, r7, #4 800dab8: 2200 movs r2, #0 800daba: 601a str r2, [r3, #0] 800dabc: 605a str r2, [r3, #4] 800dabe: 609a str r2, [r3, #8] 800dac0: 60da str r2, [r3, #12] 800dac2: 611a str r2, [r3, #16] 800dac4: 615a str r2, [r3, #20] 800dac6: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM4_Init 1 */ /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; 800dac8: 4b37 ldr r3, [pc, #220] @ (800dba8 ) 800daca: 4a38 ldr r2, [pc, #224] @ (800dbac ) 800dacc: 601a str r2, [r3, #0] htim4.Init.Prescaler = 720; 800dace: 4b36 ldr r3, [pc, #216] @ (800dba8 ) 800dad0: f44f 7234 mov.w r2, #720 @ 0x2d0 800dad4: 605a str r2, [r3, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 800dad6: 4b34 ldr r3, [pc, #208] @ (800dba8 ) 800dad8: 2200 movs r2, #0 800dada: 609a str r2, [r3, #8] htim4.Init.Period = 100; 800dadc: 4b32 ldr r3, [pc, #200] @ (800dba8 ) 800dade: 2264 movs r2, #100 @ 0x64 800dae0: 60da str r2, [r3, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800dae2: 4b31 ldr r3, [pc, #196] @ (800dba8 ) 800dae4: 2200 movs r2, #0 800dae6: 611a str r2, [r3, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800dae8: 4b2f ldr r3, [pc, #188] @ (800dba8 ) 800daea: 2200 movs r2, #0 800daec: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 800daee: 482e ldr r0, [pc, #184] @ (800dba8 ) 800daf0: f004 f947 bl 8011d82 800daf4: 4603 mov r3, r0 800daf6: 2b00 cmp r3, #0 800daf8: d001 beq.n 800dafe { Error_Handler(); 800dafa: f7fd f8c3 bl 800ac84 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800dafe: f44f 5380 mov.w r3, #4096 @ 0x1000 800db02: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 800db04: f107 0328 add.w r3, r7, #40 @ 0x28 800db08: 4619 mov r1, r3 800db0a: 4827 ldr r0, [pc, #156] @ (800dba8 ) 800db0c: f004 fd9a bl 8012644 800db10: 4603 mov r3, r0 800db12: 2b00 cmp r3, #0 800db14: d001 beq.n 800db1a { Error_Handler(); 800db16: f7fd f8b5 bl 800ac84 } if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) 800db1a: 4823 ldr r0, [pc, #140] @ (800dba8 ) 800db1c: f004 fa82 bl 8012024 800db20: 4603 mov r3, r0 800db22: 2b00 cmp r3, #0 800db24: d001 beq.n 800db2a { Error_Handler(); 800db26: f7fd f8ad bl 800ac84 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800db2a: 2300 movs r3, #0 800db2c: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800db2e: 2300 movs r3, #0 800db30: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 800db32: f107 0320 add.w r3, r7, #32 800db36: 4619 mov r1, r3 800db38: 481b ldr r0, [pc, #108] @ (800dba8 ) 800db3a: f005 f931 bl 8012da0 800db3e: 4603 mov r3, r0 800db40: 2b00 cmp r3, #0 800db42: d001 beq.n 800db48 { Error_Handler(); 800db44: f7fd f89e bl 800ac84 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800db48: 2360 movs r3, #96 @ 0x60 800db4a: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800db4c: 2300 movs r3, #0 800db4e: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800db50: 2300 movs r3, #0 800db52: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800db54: 2300 movs r3, #0 800db56: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800db58: 1d3b adds r3, r7, #4 800db5a: 2204 movs r2, #4 800db5c: 4619 mov r1, r3 800db5e: 4812 ldr r0, [pc, #72] @ (800dba8 ) 800db60: f004 fcae bl 80124c0 800db64: 4603 mov r3, r0 800db66: 2b00 cmp r3, #0 800db68: d001 beq.n 800db6e { Error_Handler(); 800db6a: f7fd f88b bl 800ac84 } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 800db6e: 1d3b adds r3, r7, #4 800db70: 2208 movs r2, #8 800db72: 4619 mov r1, r3 800db74: 480c ldr r0, [pc, #48] @ (800dba8 ) 800db76: f004 fca3 bl 80124c0 800db7a: 4603 mov r3, r0 800db7c: 2b00 cmp r3, #0 800db7e: d001 beq.n 800db84 { Error_Handler(); 800db80: f7fd f880 bl 800ac84 } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 800db84: 1d3b adds r3, r7, #4 800db86: 220c movs r2, #12 800db88: 4619 mov r1, r3 800db8a: 4807 ldr r0, [pc, #28] @ (800dba8 ) 800db8c: f004 fc98 bl 80124c0 800db90: 4603 mov r3, r0 800db92: 2b00 cmp r3, #0 800db94: d001 beq.n 800db9a { Error_Handler(); 800db96: f7fd f875 bl 800ac84 } /* USER CODE BEGIN TIM4_Init 2 */ /* USER CODE END TIM4_Init 2 */ HAL_TIM_MspPostInit(&htim4); 800db9a: 4803 ldr r0, [pc, #12] @ (800dba8 ) 800db9c: f000 f842 bl 800dc24 } 800dba0: bf00 nop 800dba2: 3738 adds r7, #56 @ 0x38 800dba4: 46bd mov sp, r7 800dba6: bd80 pop {r7, pc} 800dba8: 20001210 .word 0x20001210 800dbac: 40000800 .word 0x40000800 0800dbb0 : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 800dbb0: b580 push {r7, lr} 800dbb2: b084 sub sp, #16 800dbb4: af00 add r7, sp, #0 800dbb6: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM3) 800dbb8: 687b ldr r3, [r7, #4] 800dbba: 681b ldr r3, [r3, #0] 800dbbc: 4a16 ldr r2, [pc, #88] @ (800dc18 ) 800dbbe: 4293 cmp r3, r2 800dbc0: d114 bne.n 800dbec { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 800dbc2: 4b16 ldr r3, [pc, #88] @ (800dc1c ) 800dbc4: 69db ldr r3, [r3, #28] 800dbc6: 4a15 ldr r2, [pc, #84] @ (800dc1c ) 800dbc8: f043 0302 orr.w r3, r3, #2 800dbcc: 61d3 str r3, [r2, #28] 800dbce: 4b13 ldr r3, [pc, #76] @ (800dc1c ) 800dbd0: 69db ldr r3, [r3, #28] 800dbd2: f003 0302 and.w r3, r3, #2 800dbd6: 60fb str r3, [r7, #12] 800dbd8: 68fb ldr r3, [r7, #12] /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 6, 0); 800dbda: 2200 movs r2, #0 800dbdc: 2106 movs r1, #6 800dbde: 201d movs r0, #29 800dbe0: f002 f8c5 bl 800fd6e HAL_NVIC_EnableIRQ(TIM3_IRQn); 800dbe4: 201d movs r0, #29 800dbe6: f002 f8de bl 800fda6 __HAL_RCC_TIM4_CLK_ENABLE(); /* USER CODE BEGIN TIM4_MspInit 1 */ /* USER CODE END TIM4_MspInit 1 */ } } 800dbea: e010 b.n 800dc0e else if(tim_baseHandle->Instance==TIM4) 800dbec: 687b ldr r3, [r7, #4] 800dbee: 681b ldr r3, [r3, #0] 800dbf0: 4a0b ldr r2, [pc, #44] @ (800dc20 ) 800dbf2: 4293 cmp r3, r2 800dbf4: d10b bne.n 800dc0e __HAL_RCC_TIM4_CLK_ENABLE(); 800dbf6: 4b09 ldr r3, [pc, #36] @ (800dc1c ) 800dbf8: 69db ldr r3, [r3, #28] 800dbfa: 4a08 ldr r2, [pc, #32] @ (800dc1c ) 800dbfc: f043 0304 orr.w r3, r3, #4 800dc00: 61d3 str r3, [r2, #28] 800dc02: 4b06 ldr r3, [pc, #24] @ (800dc1c ) 800dc04: 69db ldr r3, [r3, #28] 800dc06: f003 0304 and.w r3, r3, #4 800dc0a: 60bb str r3, [r7, #8] 800dc0c: 68bb ldr r3, [r7, #8] } 800dc0e: bf00 nop 800dc10: 3710 adds r7, #16 800dc12: 46bd mov sp, r7 800dc14: bd80 pop {r7, pc} 800dc16: bf00 nop 800dc18: 40000400 .word 0x40000400 800dc1c: 40021000 .word 0x40021000 800dc20: 40000800 .word 0x40000800 0800dc24 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 800dc24: b580 push {r7, lr} 800dc26: b08a sub sp, #40 @ 0x28 800dc28: af00 add r7, sp, #0 800dc2a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800dc2c: f107 0314 add.w r3, r7, #20 800dc30: 2200 movs r2, #0 800dc32: 601a str r2, [r3, #0] 800dc34: 605a str r2, [r3, #4] 800dc36: 609a str r2, [r3, #8] 800dc38: 60da str r2, [r3, #12] if(timHandle->Instance==TIM3) 800dc3a: 687b ldr r3, [r7, #4] 800dc3c: 681b ldr r3, [r3, #0] 800dc3e: 4a26 ldr r2, [pc, #152] @ (800dcd8 ) 800dc40: 4293 cmp r3, r2 800dc42: d118 bne.n 800dc76 { /* USER CODE BEGIN TIM3_MspPostInit 0 */ /* USER CODE END TIM3_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800dc44: 4b25 ldr r3, [pc, #148] @ (800dcdc ) 800dc46: 699b ldr r3, [r3, #24] 800dc48: 4a24 ldr r2, [pc, #144] @ (800dcdc ) 800dc4a: f043 0304 orr.w r3, r3, #4 800dc4e: 6193 str r3, [r2, #24] 800dc50: 4b22 ldr r3, [pc, #136] @ (800dcdc ) 800dc52: 699b ldr r3, [r3, #24] 800dc54: f003 0304 and.w r3, r3, #4 800dc58: 613b str r3, [r7, #16] 800dc5a: 693b ldr r3, [r7, #16] /**TIM3 GPIO Configuration PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = CP_PWM_Pin; 800dc5c: 2380 movs r3, #128 @ 0x80 800dc5e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800dc60: 2302 movs r3, #2 800dc62: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800dc64: 2302 movs r3, #2 800dc66: 623b str r3, [r7, #32] HAL_GPIO_Init(CP_PWM_GPIO_Port, &GPIO_InitStruct); 800dc68: f107 0314 add.w r3, r7, #20 800dc6c: 4619 mov r1, r3 800dc6e: 481c ldr r0, [pc, #112] @ (800dce0 ) 800dc70: f002 fd5e bl 8010730 /* USER CODE BEGIN TIM4_MspPostInit 1 */ /* USER CODE END TIM4_MspPostInit 1 */ } } 800dc74: e02b b.n 800dcce else if(timHandle->Instance==TIM4) 800dc76: 687b ldr r3, [r7, #4] 800dc78: 681b ldr r3, [r3, #0] 800dc7a: 4a1a ldr r2, [pc, #104] @ (800dce4 ) 800dc7c: 4293 cmp r3, r2 800dc7e: d126 bne.n 800dcce __HAL_RCC_GPIOD_CLK_ENABLE(); 800dc80: 4b16 ldr r3, [pc, #88] @ (800dcdc ) 800dc82: 699b ldr r3, [r3, #24] 800dc84: 4a15 ldr r2, [pc, #84] @ (800dcdc ) 800dc86: f043 0320 orr.w r3, r3, #32 800dc8a: 6193 str r3, [r2, #24] 800dc8c: 4b13 ldr r3, [pc, #76] @ (800dcdc ) 800dc8e: 699b ldr r3, [r3, #24] 800dc90: f003 0320 and.w r3, r3, #32 800dc94: 60fb str r3, [r7, #12] 800dc96: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; 800dc98: f44f 4360 mov.w r3, #57344 @ 0xe000 800dc9c: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800dc9e: 2302 movs r3, #2 800dca0: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800dca2: 2302 movs r3, #2 800dca4: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800dca6: f107 0314 add.w r3, r7, #20 800dcaa: 4619 mov r1, r3 800dcac: 480e ldr r0, [pc, #56] @ (800dce8 ) 800dcae: f002 fd3f bl 8010730 __HAL_AFIO_REMAP_TIM4_ENABLE(); 800dcb2: 4b0e ldr r3, [pc, #56] @ (800dcec ) 800dcb4: 685b ldr r3, [r3, #4] 800dcb6: 627b str r3, [r7, #36] @ 0x24 800dcb8: 6a7b ldr r3, [r7, #36] @ 0x24 800dcba: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800dcbe: 627b str r3, [r7, #36] @ 0x24 800dcc0: 6a7b ldr r3, [r7, #36] @ 0x24 800dcc2: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800dcc6: 627b str r3, [r7, #36] @ 0x24 800dcc8: 4a08 ldr r2, [pc, #32] @ (800dcec ) 800dcca: 6a7b ldr r3, [r7, #36] @ 0x24 800dccc: 6053 str r3, [r2, #4] } 800dcce: bf00 nop 800dcd0: 3728 adds r7, #40 @ 0x28 800dcd2: 46bd mov sp, r7 800dcd4: bd80 pop {r7, pc} 800dcd6: bf00 nop 800dcd8: 40000400 .word 0x40000400 800dcdc: 40021000 .word 0x40021000 800dce0: 40010800 .word 0x40010800 800dce4: 40000800 .word 0x40000800 800dce8: 40011400 .word 0x40011400 800dcec: 40010000 .word 0x40010000 0800dcf0 : DMA_HandleTypeDef hdma_usart3_rx; DMA_HandleTypeDef hdma_usart3_tx; /* UART5 init function */ void MX_UART5_Init(void) { 800dcf0: b580 push {r7, lr} 800dcf2: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 800dcf4: 4b11 ldr r3, [pc, #68] @ (800dd3c ) 800dcf6: 4a12 ldr r2, [pc, #72] @ (800dd40 ) 800dcf8: 601a str r2, [r3, #0] huart5.Init.BaudRate = 9600; 800dcfa: 4b10 ldr r3, [pc, #64] @ (800dd3c ) 800dcfc: f44f 5216 mov.w r2, #9600 @ 0x2580 800dd00: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 800dd02: 4b0e ldr r3, [pc, #56] @ (800dd3c ) 800dd04: 2200 movs r2, #0 800dd06: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 800dd08: 4b0c ldr r3, [pc, #48] @ (800dd3c ) 800dd0a: 2200 movs r2, #0 800dd0c: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 800dd0e: 4b0b ldr r3, [pc, #44] @ (800dd3c ) 800dd10: 2200 movs r2, #0 800dd12: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 800dd14: 4b09 ldr r3, [pc, #36] @ (800dd3c ) 800dd16: 220c movs r2, #12 800dd18: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800dd1a: 4b08 ldr r3, [pc, #32] @ (800dd3c ) 800dd1c: 2200 movs r2, #0 800dd1e: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 800dd20: 4b06 ldr r3, [pc, #24] @ (800dd3c ) 800dd22: 2200 movs r2, #0 800dd24: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 800dd26: 4805 ldr r0, [pc, #20] @ (800dd3c ) 800dd28: f005 f8b2 bl 8012e90 800dd2c: 4603 mov r3, r0 800dd2e: 2b00 cmp r3, #0 800dd30: d001 beq.n 800dd36 { Error_Handler(); 800dd32: f7fc ffa7 bl 800ac84 } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 800dd36: bf00 nop 800dd38: bd80 pop {r7, pc} 800dd3a: bf00 nop 800dd3c: 20001258 .word 0x20001258 800dd40: 40005000 .word 0x40005000 0800dd44 : /* USART1 init function */ void MX_USART1_UART_Init(void) { 800dd44: b580 push {r7, lr} 800dd46: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 800dd48: 4b11 ldr r3, [pc, #68] @ (800dd90 ) 800dd4a: 4a12 ldr r2, [pc, #72] @ (800dd94 ) 800dd4c: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800dd4e: 4b10 ldr r3, [pc, #64] @ (800dd90 ) 800dd50: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800dd54: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800dd56: 4b0e ldr r3, [pc, #56] @ (800dd90 ) 800dd58: 2200 movs r2, #0 800dd5a: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 800dd5c: 4b0c ldr r3, [pc, #48] @ (800dd90 ) 800dd5e: 2200 movs r2, #0 800dd60: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800dd62: 4b0b ldr r3, [pc, #44] @ (800dd90 ) 800dd64: 2200 movs r2, #0 800dd66: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 800dd68: 4b09 ldr r3, [pc, #36] @ (800dd90 ) 800dd6a: 220c movs r2, #12 800dd6c: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800dd6e: 4b08 ldr r3, [pc, #32] @ (800dd90 ) 800dd70: 2200 movs r2, #0 800dd72: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800dd74: 4b06 ldr r3, [pc, #24] @ (800dd90 ) 800dd76: 2200 movs r2, #0 800dd78: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 800dd7a: 4805 ldr r0, [pc, #20] @ (800dd90 ) 800dd7c: f005 f888 bl 8012e90 800dd80: 4603 mov r3, r0 800dd82: 2b00 cmp r3, #0 800dd84: d001 beq.n 800dd8a { Error_Handler(); 800dd86: f7fc ff7d bl 800ac84 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 800dd8a: bf00 nop 800dd8c: bd80 pop {r7, pc} 800dd8e: bf00 nop 800dd90: 200012a0 .word 0x200012a0 800dd94: 40013800 .word 0x40013800 0800dd98 : /* USART2 init function */ void MX_USART2_UART_Init(void) { 800dd98: b580 push {r7, lr} 800dd9a: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 800dd9c: 4b11 ldr r3, [pc, #68] @ (800dde4 ) 800dd9e: 4a12 ldr r2, [pc, #72] @ (800dde8 ) 800dda0: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 800dda2: 4b10 ldr r3, [pc, #64] @ (800dde4 ) 800dda4: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800dda8: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 800ddaa: 4b0e ldr r3, [pc, #56] @ (800dde4 ) 800ddac: 2200 movs r2, #0 800ddae: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 800ddb0: 4b0c ldr r3, [pc, #48] @ (800dde4 ) 800ddb2: 2200 movs r2, #0 800ddb4: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800ddb6: 4b0b ldr r3, [pc, #44] @ (800dde4 ) 800ddb8: 2200 movs r2, #0 800ddba: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 800ddbc: 4b09 ldr r3, [pc, #36] @ (800dde4 ) 800ddbe: 220c movs r2, #12 800ddc0: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800ddc2: 4b08 ldr r3, [pc, #32] @ (800dde4 ) 800ddc4: 2200 movs r2, #0 800ddc6: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 800ddc8: 4b06 ldr r3, [pc, #24] @ (800dde4 ) 800ddca: 2200 movs r2, #0 800ddcc: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 800ddce: 4805 ldr r0, [pc, #20] @ (800dde4 ) 800ddd0: f005 f85e bl 8012e90 800ddd4: 4603 mov r3, r0 800ddd6: 2b00 cmp r3, #0 800ddd8: d001 beq.n 800ddde { Error_Handler(); 800ddda: f7fc ff53 bl 800ac84 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 800ddde: bf00 nop 800dde0: bd80 pop {r7, pc} 800dde2: bf00 nop 800dde4: 200012e8 .word 0x200012e8 800dde8: 40004400 .word 0x40004400 0800ddec : /* USART3 init function */ void MX_USART3_UART_Init(void) { 800ddec: b580 push {r7, lr} 800ddee: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 800ddf0: 4b11 ldr r3, [pc, #68] @ (800de38 ) 800ddf2: 4a12 ldr r2, [pc, #72] @ (800de3c ) 800ddf4: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 800ddf6: 4b10 ldr r3, [pc, #64] @ (800de38 ) 800ddf8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800ddfc: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 800ddfe: 4b0e ldr r3, [pc, #56] @ (800de38 ) 800de00: 2200 movs r2, #0 800de02: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 800de04: 4b0c ldr r3, [pc, #48] @ (800de38 ) 800de06: 2200 movs r2, #0 800de08: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 800de0a: 4b0b ldr r3, [pc, #44] @ (800de38 ) 800de0c: 2200 movs r2, #0 800de0e: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 800de10: 4b09 ldr r3, [pc, #36] @ (800de38 ) 800de12: 220c movs r2, #12 800de14: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800de16: 4b08 ldr r3, [pc, #32] @ (800de38 ) 800de18: 2200 movs r2, #0 800de1a: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 800de1c: 4b06 ldr r3, [pc, #24] @ (800de38 ) 800de1e: 2200 movs r2, #0 800de20: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart3) != HAL_OK) 800de22: 4805 ldr r0, [pc, #20] @ (800de38 ) 800de24: f005 f834 bl 8012e90 800de28: 4603 mov r3, r0 800de2a: 2b00 cmp r3, #0 800de2c: d001 beq.n 800de32 { Error_Handler(); 800de2e: f7fc ff29 bl 800ac84 } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 800de32: bf00 nop 800de34: bd80 pop {r7, pc} 800de36: bf00 nop 800de38: 20001330 .word 0x20001330 800de3c: 40004800 .word 0x40004800 0800de40 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 800de40: b580 push {r7, lr} 800de42: b092 sub sp, #72 @ 0x48 800de44: af00 add r7, sp, #0 800de46: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800de48: f107 0330 add.w r3, r7, #48 @ 0x30 800de4c: 2200 movs r2, #0 800de4e: 601a str r2, [r3, #0] 800de50: 605a str r2, [r3, #4] 800de52: 609a str r2, [r3, #8] 800de54: 60da str r2, [r3, #12] if(uartHandle->Instance==UART5) 800de56: 687b ldr r3, [r7, #4] 800de58: 681b ldr r3, [r3, #0] 800de5a: 4a92 ldr r2, [pc, #584] @ (800e0a4 ) 800de5c: 4293 cmp r3, r2 800de5e: d145 bne.n 800deec { /* USER CODE BEGIN UART5_MspInit 0 */ /* USER CODE END UART5_MspInit 0 */ /* UART5 clock enable */ __HAL_RCC_UART5_CLK_ENABLE(); 800de60: 4b91 ldr r3, [pc, #580] @ (800e0a8 ) 800de62: 69db ldr r3, [r3, #28] 800de64: 4a90 ldr r2, [pc, #576] @ (800e0a8 ) 800de66: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800de6a: 61d3 str r3, [r2, #28] 800de6c: 4b8e ldr r3, [pc, #568] @ (800e0a8 ) 800de6e: 69db ldr r3, [r3, #28] 800de70: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800de74: 62fb str r3, [r7, #44] @ 0x2c 800de76: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 800de78: 4b8b ldr r3, [pc, #556] @ (800e0a8 ) 800de7a: 699b ldr r3, [r3, #24] 800de7c: 4a8a ldr r2, [pc, #552] @ (800e0a8 ) 800de7e: f043 0310 orr.w r3, r3, #16 800de82: 6193 str r3, [r2, #24] 800de84: 4b88 ldr r3, [pc, #544] @ (800e0a8 ) 800de86: 699b ldr r3, [r3, #24] 800de88: f003 0310 and.w r3, r3, #16 800de8c: 62bb str r3, [r7, #40] @ 0x28 800de8e: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOD_CLK_ENABLE(); 800de90: 4b85 ldr r3, [pc, #532] @ (800e0a8 ) 800de92: 699b ldr r3, [r3, #24] 800de94: 4a84 ldr r2, [pc, #528] @ (800e0a8 ) 800de96: f043 0320 orr.w r3, r3, #32 800de9a: 6193 str r3, [r2, #24] 800de9c: 4b82 ldr r3, [pc, #520] @ (800e0a8 ) 800de9e: 699b ldr r3, [r3, #24] 800dea0: f003 0320 and.w r3, r3, #32 800dea4: 627b str r3, [r7, #36] @ 0x24 800dea6: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART5 GPIO Configuration PC12 ------> UART5_TX PD2 ------> UART5_RX */ GPIO_InitStruct.Pin = HEATER_Pin; 800dea8: f44f 5380 mov.w r3, #4096 @ 0x1000 800deac: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800deae: 2302 movs r3, #2 800deb0: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800deb2: 2303 movs r3, #3 800deb4: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(HEATER_GPIO_Port, &GPIO_InitStruct); 800deb6: f107 0330 add.w r3, r7, #48 @ 0x30 800deba: 4619 mov r1, r3 800debc: 487b ldr r0, [pc, #492] @ (800e0ac ) 800debe: f002 fc37 bl 8010730 GPIO_InitStruct.Pin = GPIO_PIN_2; 800dec2: 2304 movs r3, #4 800dec4: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800dec6: 2300 movs r3, #0 800dec8: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800deca: 2300 movs r3, #0 800decc: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800dece: f107 0330 add.w r3, r7, #48 @ 0x30 800ded2: 4619 mov r1, r3 800ded4: 4876 ldr r0, [pc, #472] @ (800e0b0 ) 800ded6: f002 fc2b bl 8010730 /* UART5 interrupt Init */ HAL_NVIC_SetPriority(UART5_IRQn, 5, 0); 800deda: 2200 movs r2, #0 800dedc: 2105 movs r1, #5 800dede: 2035 movs r0, #53 @ 0x35 800dee0: f001 ff45 bl 800fd6e HAL_NVIC_EnableIRQ(UART5_IRQn); 800dee4: 2035 movs r0, #53 @ 0x35 800dee6: f001 ff5e bl 800fda6 HAL_NVIC_EnableIRQ(USART3_IRQn); /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 800deea: e193 b.n 800e214 else if(uartHandle->Instance==USART1) 800deec: 687b ldr r3, [r7, #4] 800deee: 681b ldr r3, [r3, #0] 800def0: 4a70 ldr r2, [pc, #448] @ (800e0b4 ) 800def2: 4293 cmp r3, r2 800def4: d13a bne.n 800df6c __HAL_RCC_USART1_CLK_ENABLE(); 800def6: 4b6c ldr r3, [pc, #432] @ (800e0a8 ) 800def8: 699b ldr r3, [r3, #24] 800defa: 4a6b ldr r2, [pc, #428] @ (800e0a8 ) 800defc: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800df00: 6193 str r3, [r2, #24] 800df02: 4b69 ldr r3, [pc, #420] @ (800e0a8 ) 800df04: 699b ldr r3, [r3, #24] 800df06: f403 4380 and.w r3, r3, #16384 @ 0x4000 800df0a: 623b str r3, [r7, #32] 800df0c: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 800df0e: 4b66 ldr r3, [pc, #408] @ (800e0a8 ) 800df10: 699b ldr r3, [r3, #24] 800df12: 4a65 ldr r2, [pc, #404] @ (800e0a8 ) 800df14: f043 0304 orr.w r3, r3, #4 800df18: 6193 str r3, [r2, #24] 800df1a: 4b63 ldr r3, [pc, #396] @ (800e0a8 ) 800df1c: 699b ldr r3, [r3, #24] 800df1e: f003 0304 and.w r3, r3, #4 800df22: 61fb str r3, [r7, #28] 800df24: 69fb ldr r3, [r7, #28] GPIO_InitStruct.Pin = GPIO_PIN_9; 800df26: f44f 7300 mov.w r3, #512 @ 0x200 800df2a: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800df2c: 2302 movs r3, #2 800df2e: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800df30: 2303 movs r3, #3 800df32: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800df34: f107 0330 add.w r3, r7, #48 @ 0x30 800df38: 4619 mov r1, r3 800df3a: 485f ldr r0, [pc, #380] @ (800e0b8 ) 800df3c: f002 fbf8 bl 8010730 GPIO_InitStruct.Pin = GPIO_PIN_10; 800df40: f44f 6380 mov.w r3, #1024 @ 0x400 800df44: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800df46: 2300 movs r3, #0 800df48: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800df4a: 2300 movs r3, #0 800df4c: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800df4e: f107 0330 add.w r3, r7, #48 @ 0x30 800df52: 4619 mov r1, r3 800df54: 4858 ldr r0, [pc, #352] @ (800e0b8 ) 800df56: f002 fbeb bl 8010730 HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 800df5a: 2200 movs r2, #0 800df5c: 2105 movs r1, #5 800df5e: 2025 movs r0, #37 @ 0x25 800df60: f001 ff05 bl 800fd6e HAL_NVIC_EnableIRQ(USART1_IRQn); 800df64: 2025 movs r0, #37 @ 0x25 800df66: f001 ff1e bl 800fda6 } 800df6a: e153 b.n 800e214 else if(uartHandle->Instance==USART2) 800df6c: 687b ldr r3, [r7, #4] 800df6e: 681b ldr r3, [r3, #0] 800df70: 4a52 ldr r2, [pc, #328] @ (800e0bc ) 800df72: 4293 cmp r3, r2 800df74: f040 80ae bne.w 800e0d4 __HAL_RCC_USART2_CLK_ENABLE(); 800df78: 4b4b ldr r3, [pc, #300] @ (800e0a8 ) 800df7a: 69db ldr r3, [r3, #28] 800df7c: 4a4a ldr r2, [pc, #296] @ (800e0a8 ) 800df7e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800df82: 61d3 str r3, [r2, #28] 800df84: 4b48 ldr r3, [pc, #288] @ (800e0a8 ) 800df86: 69db ldr r3, [r3, #28] 800df88: f403 3300 and.w r3, r3, #131072 @ 0x20000 800df8c: 61bb str r3, [r7, #24] 800df8e: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOD_CLK_ENABLE(); 800df90: 4b45 ldr r3, [pc, #276] @ (800e0a8 ) 800df92: 699b ldr r3, [r3, #24] 800df94: 4a44 ldr r2, [pc, #272] @ (800e0a8 ) 800df96: f043 0320 orr.w r3, r3, #32 800df9a: 6193 str r3, [r2, #24] 800df9c: 4b42 ldr r3, [pc, #264] @ (800e0a8 ) 800df9e: 699b ldr r3, [r3, #24] 800dfa0: f003 0320 and.w r3, r3, #32 800dfa4: 617b str r3, [r7, #20] 800dfa6: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_5; 800dfa8: 2320 movs r3, #32 800dfaa: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800dfac: 2302 movs r3, #2 800dfae: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800dfb0: 2303 movs r3, #3 800dfb2: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800dfb4: f107 0330 add.w r3, r7, #48 @ 0x30 800dfb8: 4619 mov r1, r3 800dfba: 483d ldr r0, [pc, #244] @ (800e0b0 ) 800dfbc: f002 fbb8 bl 8010730 GPIO_InitStruct.Pin = GPIO_PIN_6; 800dfc0: 2340 movs r3, #64 @ 0x40 800dfc2: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800dfc4: 2300 movs r3, #0 800dfc6: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800dfc8: 2300 movs r3, #0 800dfca: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800dfcc: f107 0330 add.w r3, r7, #48 @ 0x30 800dfd0: 4619 mov r1, r3 800dfd2: 4837 ldr r0, [pc, #220] @ (800e0b0 ) 800dfd4: f002 fbac bl 8010730 __HAL_AFIO_REMAP_USART2_ENABLE(); 800dfd8: 4b39 ldr r3, [pc, #228] @ (800e0c0 ) 800dfda: 685b ldr r3, [r3, #4] 800dfdc: 643b str r3, [r7, #64] @ 0x40 800dfde: 6c3b ldr r3, [r7, #64] @ 0x40 800dfe0: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800dfe4: 643b str r3, [r7, #64] @ 0x40 800dfe6: 6c3b ldr r3, [r7, #64] @ 0x40 800dfe8: f043 0308 orr.w r3, r3, #8 800dfec: 643b str r3, [r7, #64] @ 0x40 800dfee: 4a34 ldr r2, [pc, #208] @ (800e0c0 ) 800dff0: 6c3b ldr r3, [r7, #64] @ 0x40 800dff2: 6053 str r3, [r2, #4] hdma_usart2_rx.Instance = DMA1_Channel6; 800dff4: 4b33 ldr r3, [pc, #204] @ (800e0c4 ) 800dff6: 4a34 ldr r2, [pc, #208] @ (800e0c8 ) 800dff8: 601a str r2, [r3, #0] hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 800dffa: 4b32 ldr r3, [pc, #200] @ (800e0c4 ) 800dffc: 2200 movs r2, #0 800dffe: 605a str r2, [r3, #4] hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 800e000: 4b30 ldr r3, [pc, #192] @ (800e0c4 ) 800e002: 2200 movs r2, #0 800e004: 609a str r2, [r3, #8] hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; 800e006: 4b2f ldr r3, [pc, #188] @ (800e0c4 ) 800e008: 2280 movs r2, #128 @ 0x80 800e00a: 60da str r2, [r3, #12] hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800e00c: 4b2d ldr r3, [pc, #180] @ (800e0c4 ) 800e00e: 2200 movs r2, #0 800e010: 611a str r2, [r3, #16] hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800e012: 4b2c ldr r3, [pc, #176] @ (800e0c4 ) 800e014: 2200 movs r2, #0 800e016: 615a str r2, [r3, #20] hdma_usart2_rx.Init.Mode = DMA_NORMAL; 800e018: 4b2a ldr r3, [pc, #168] @ (800e0c4 ) 800e01a: 2200 movs r2, #0 800e01c: 619a str r2, [r3, #24] hdma_usart2_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH; 800e01e: 4b29 ldr r3, [pc, #164] @ (800e0c4 ) 800e020: f44f 5240 mov.w r2, #12288 @ 0x3000 800e024: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) 800e026: 4827 ldr r0, [pc, #156] @ (800e0c4 ) 800e028: f001 fef4 bl 800fe14 800e02c: 4603 mov r3, r0 800e02e: 2b00 cmp r3, #0 800e030: d001 beq.n 800e036 Error_Handler(); 800e032: f7fc fe27 bl 800ac84 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); 800e036: 687b ldr r3, [r7, #4] 800e038: 4a22 ldr r2, [pc, #136] @ (800e0c4 ) 800e03a: 63da str r2, [r3, #60] @ 0x3c 800e03c: 4a21 ldr r2, [pc, #132] @ (800e0c4 ) 800e03e: 687b ldr r3, [r7, #4] 800e040: 6253 str r3, [r2, #36] @ 0x24 hdma_usart2_tx.Instance = DMA1_Channel7; 800e042: 4b22 ldr r3, [pc, #136] @ (800e0cc ) 800e044: 4a22 ldr r2, [pc, #136] @ (800e0d0 ) 800e046: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 800e048: 4b20 ldr r3, [pc, #128] @ (800e0cc ) 800e04a: 2210 movs r2, #16 800e04c: 605a str r2, [r3, #4] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800e04e: 4b1f ldr r3, [pc, #124] @ (800e0cc ) 800e050: 2200 movs r2, #0 800e052: 609a str r2, [r3, #8] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; 800e054: 4b1d ldr r3, [pc, #116] @ (800e0cc ) 800e056: 2280 movs r2, #128 @ 0x80 800e058: 60da str r2, [r3, #12] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800e05a: 4b1c ldr r3, [pc, #112] @ (800e0cc ) 800e05c: 2200 movs r2, #0 800e05e: 611a str r2, [r3, #16] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800e060: 4b1a ldr r3, [pc, #104] @ (800e0cc ) 800e062: 2200 movs r2, #0 800e064: 615a str r2, [r3, #20] hdma_usart2_tx.Init.Mode = DMA_NORMAL; 800e066: 4b19 ldr r3, [pc, #100] @ (800e0cc ) 800e068: 2200 movs r2, #0 800e06a: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_HIGH; 800e06c: 4b17 ldr r3, [pc, #92] @ (800e0cc ) 800e06e: f44f 5200 mov.w r2, #8192 @ 0x2000 800e072: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 800e074: 4815 ldr r0, [pc, #84] @ (800e0cc ) 800e076: f001 fecd bl 800fe14 800e07a: 4603 mov r3, r0 800e07c: 2b00 cmp r3, #0 800e07e: d001 beq.n 800e084 Error_Handler(); 800e080: f7fc fe00 bl 800ac84 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); 800e084: 687b ldr r3, [r7, #4] 800e086: 4a11 ldr r2, [pc, #68] @ (800e0cc ) 800e088: 639a str r2, [r3, #56] @ 0x38 800e08a: 4a10 ldr r2, [pc, #64] @ (800e0cc ) 800e08c: 687b ldr r3, [r7, #4] 800e08e: 6253 str r3, [r2, #36] @ 0x24 HAL_NVIC_SetPriority(USART2_IRQn, 2, 0); 800e090: 2200 movs r2, #0 800e092: 2102 movs r1, #2 800e094: 2026 movs r0, #38 @ 0x26 800e096: f001 fe6a bl 800fd6e HAL_NVIC_EnableIRQ(USART2_IRQn); 800e09a: 2026 movs r0, #38 @ 0x26 800e09c: f001 fe83 bl 800fda6 } 800e0a0: e0b8 b.n 800e214 800e0a2: bf00 nop 800e0a4: 40005000 .word 0x40005000 800e0a8: 40021000 .word 0x40021000 800e0ac: 40011000 .word 0x40011000 800e0b0: 40011400 .word 0x40011400 800e0b4: 40013800 .word 0x40013800 800e0b8: 40010800 .word 0x40010800 800e0bc: 40004400 .word 0x40004400 800e0c0: 40010000 .word 0x40010000 800e0c4: 20001378 .word 0x20001378 800e0c8: 4002006c .word 0x4002006c 800e0cc: 200013bc .word 0x200013bc 800e0d0: 40020080 .word 0x40020080 else if(uartHandle->Instance==USART3) 800e0d4: 687b ldr r3, [r7, #4] 800e0d6: 681b ldr r3, [r3, #0] 800e0d8: 4a50 ldr r2, [pc, #320] @ (800e21c ) 800e0da: 4293 cmp r3, r2 800e0dc: f040 809a bne.w 800e214 __HAL_RCC_USART3_CLK_ENABLE(); 800e0e0: 4b4f ldr r3, [pc, #316] @ (800e220 ) 800e0e2: 69db ldr r3, [r3, #28] 800e0e4: 4a4e ldr r2, [pc, #312] @ (800e220 ) 800e0e6: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800e0ea: 61d3 str r3, [r2, #28] 800e0ec: 4b4c ldr r3, [pc, #304] @ (800e220 ) 800e0ee: 69db ldr r3, [r3, #28] 800e0f0: f403 2380 and.w r3, r3, #262144 @ 0x40000 800e0f4: 613b str r3, [r7, #16] 800e0f6: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 800e0f8: 4b49 ldr r3, [pc, #292] @ (800e220 ) 800e0fa: 699b ldr r3, [r3, #24] 800e0fc: 4a48 ldr r2, [pc, #288] @ (800e220 ) 800e0fe: f043 0310 orr.w r3, r3, #16 800e102: 6193 str r3, [r2, #24] 800e104: 4b46 ldr r3, [pc, #280] @ (800e220 ) 800e106: 699b ldr r3, [r3, #24] 800e108: f003 0310 and.w r3, r3, #16 800e10c: 60fb str r3, [r7, #12] 800e10e: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_10; 800e110: f44f 6380 mov.w r3, #1024 @ 0x400 800e114: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800e116: 2302 movs r3, #2 800e118: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800e11a: 2303 movs r3, #3 800e11c: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800e11e: f107 0330 add.w r3, r7, #48 @ 0x30 800e122: 4619 mov r1, r3 800e124: 483f ldr r0, [pc, #252] @ (800e224 ) 800e126: f002 fb03 bl 8010730 GPIO_InitStruct.Pin = GPIO_PIN_11; 800e12a: f44f 6300 mov.w r3, #2048 @ 0x800 800e12e: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800e130: 2300 movs r3, #0 800e132: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800e134: 2300 movs r3, #0 800e136: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800e138: f107 0330 add.w r3, r7, #48 @ 0x30 800e13c: 4619 mov r1, r3 800e13e: 4839 ldr r0, [pc, #228] @ (800e224 ) 800e140: f002 faf6 bl 8010730 __HAL_AFIO_REMAP_USART3_PARTIAL(); 800e144: 4b38 ldr r3, [pc, #224] @ (800e228 ) 800e146: 685b ldr r3, [r3, #4] 800e148: 647b str r3, [r7, #68] @ 0x44 800e14a: 6c7b ldr r3, [r7, #68] @ 0x44 800e14c: f023 0330 bic.w r3, r3, #48 @ 0x30 800e150: 647b str r3, [r7, #68] @ 0x44 800e152: 6c7b ldr r3, [r7, #68] @ 0x44 800e154: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800e158: 647b str r3, [r7, #68] @ 0x44 800e15a: 6c7b ldr r3, [r7, #68] @ 0x44 800e15c: f043 0310 orr.w r3, r3, #16 800e160: 647b str r3, [r7, #68] @ 0x44 800e162: 4a31 ldr r2, [pc, #196] @ (800e228 ) 800e164: 6c7b ldr r3, [r7, #68] @ 0x44 800e166: 6053 str r3, [r2, #4] hdma_usart3_rx.Instance = DMA1_Channel3; 800e168: 4b30 ldr r3, [pc, #192] @ (800e22c ) 800e16a: 4a31 ldr r2, [pc, #196] @ (800e230 ) 800e16c: 601a str r2, [r3, #0] hdma_usart3_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 800e16e: 4b2f ldr r3, [pc, #188] @ (800e22c ) 800e170: 2200 movs r2, #0 800e172: 605a str r2, [r3, #4] hdma_usart3_rx.Init.PeriphInc = DMA_PINC_DISABLE; 800e174: 4b2d ldr r3, [pc, #180] @ (800e22c ) 800e176: 2200 movs r2, #0 800e178: 609a str r2, [r3, #8] hdma_usart3_rx.Init.MemInc = DMA_MINC_ENABLE; 800e17a: 4b2c ldr r3, [pc, #176] @ (800e22c ) 800e17c: 2280 movs r2, #128 @ 0x80 800e17e: 60da str r2, [r3, #12] hdma_usart3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800e180: 4b2a ldr r3, [pc, #168] @ (800e22c ) 800e182: 2200 movs r2, #0 800e184: 611a str r2, [r3, #16] hdma_usart3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800e186: 4b29 ldr r3, [pc, #164] @ (800e22c ) 800e188: 2200 movs r2, #0 800e18a: 615a str r2, [r3, #20] hdma_usart3_rx.Init.Mode = DMA_NORMAL; 800e18c: 4b27 ldr r3, [pc, #156] @ (800e22c ) 800e18e: 2200 movs r2, #0 800e190: 619a str r2, [r3, #24] hdma_usart3_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH; 800e192: 4b26 ldr r3, [pc, #152] @ (800e22c ) 800e194: f44f 5240 mov.w r2, #12288 @ 0x3000 800e198: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart3_rx) != HAL_OK) 800e19a: 4824 ldr r0, [pc, #144] @ (800e22c ) 800e19c: f001 fe3a bl 800fe14 800e1a0: 4603 mov r3, r0 800e1a2: 2b00 cmp r3, #0 800e1a4: d001 beq.n 800e1aa Error_Handler(); 800e1a6: f7fc fd6d bl 800ac84 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart3_rx); 800e1aa: 687b ldr r3, [r7, #4] 800e1ac: 4a1f ldr r2, [pc, #124] @ (800e22c ) 800e1ae: 63da str r2, [r3, #60] @ 0x3c 800e1b0: 4a1e ldr r2, [pc, #120] @ (800e22c ) 800e1b2: 687b ldr r3, [r7, #4] 800e1b4: 6253 str r3, [r2, #36] @ 0x24 hdma_usart3_tx.Instance = DMA1_Channel2; 800e1b6: 4b1f ldr r3, [pc, #124] @ (800e234 ) 800e1b8: 4a1f ldr r2, [pc, #124] @ (800e238 ) 800e1ba: 601a str r2, [r3, #0] hdma_usart3_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 800e1bc: 4b1d ldr r3, [pc, #116] @ (800e234 ) 800e1be: 2210 movs r2, #16 800e1c0: 605a str r2, [r3, #4] hdma_usart3_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800e1c2: 4b1c ldr r3, [pc, #112] @ (800e234 ) 800e1c4: 2200 movs r2, #0 800e1c6: 609a str r2, [r3, #8] hdma_usart3_tx.Init.MemInc = DMA_MINC_ENABLE; 800e1c8: 4b1a ldr r3, [pc, #104] @ (800e234 ) 800e1ca: 2280 movs r2, #128 @ 0x80 800e1cc: 60da str r2, [r3, #12] hdma_usart3_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800e1ce: 4b19 ldr r3, [pc, #100] @ (800e234 ) 800e1d0: 2200 movs r2, #0 800e1d2: 611a str r2, [r3, #16] hdma_usart3_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800e1d4: 4b17 ldr r3, [pc, #92] @ (800e234 ) 800e1d6: 2200 movs r2, #0 800e1d8: 615a str r2, [r3, #20] hdma_usart3_tx.Init.Mode = DMA_NORMAL; 800e1da: 4b16 ldr r3, [pc, #88] @ (800e234 ) 800e1dc: 2200 movs r2, #0 800e1de: 619a str r2, [r3, #24] hdma_usart3_tx.Init.Priority = DMA_PRIORITY_HIGH; 800e1e0: 4b14 ldr r3, [pc, #80] @ (800e234 ) 800e1e2: f44f 5200 mov.w r2, #8192 @ 0x2000 800e1e6: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart3_tx) != HAL_OK) 800e1e8: 4812 ldr r0, [pc, #72] @ (800e234 ) 800e1ea: f001 fe13 bl 800fe14 800e1ee: 4603 mov r3, r0 800e1f0: 2b00 cmp r3, #0 800e1f2: d001 beq.n 800e1f8 Error_Handler(); 800e1f4: f7fc fd46 bl 800ac84 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart3_tx); 800e1f8: 687b ldr r3, [r7, #4] 800e1fa: 4a0e ldr r2, [pc, #56] @ (800e234 ) 800e1fc: 639a str r2, [r3, #56] @ 0x38 800e1fe: 4a0d ldr r2, [pc, #52] @ (800e234 ) 800e200: 687b ldr r3, [r7, #4] 800e202: 6253 str r3, [r2, #36] @ 0x24 HAL_NVIC_SetPriority(USART3_IRQn, 2, 0); 800e204: 2200 movs r2, #0 800e206: 2102 movs r1, #2 800e208: 2027 movs r0, #39 @ 0x27 800e20a: f001 fdb0 bl 800fd6e HAL_NVIC_EnableIRQ(USART3_IRQn); 800e20e: 2027 movs r0, #39 @ 0x27 800e210: f001 fdc9 bl 800fda6 } 800e214: bf00 nop 800e216: 3748 adds r7, #72 @ 0x48 800e218: 46bd mov sp, r7 800e21a: bd80 pop {r7, pc} 800e21c: 40004800 .word 0x40004800 800e220: 40021000 .word 0x40021000 800e224: 40011000 .word 0x40011000 800e228: 40010000 .word 0x40010000 800e22c: 20001400 .word 0x20001400 800e230: 40020030 .word 0x40020030 800e234: 20001444 .word 0x20001444 800e238: 4002001c .word 0x4002001c 0800e23c : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 800e23c: f7ff fb98 bl 800d970 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 800e240: 480b ldr r0, [pc, #44] @ (800e270 ) ldr r1, =_edata 800e242: 490c ldr r1, [pc, #48] @ (800e274 ) ldr r2, =_sidata 800e244: 4a0c ldr r2, [pc, #48] @ (800e278 ) movs r3, #0 800e246: 2300 movs r3, #0 b LoopCopyDataInit 800e248: e002 b.n 800e250 0800e24a : CopyDataInit: ldr r4, [r2, r3] 800e24a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800e24c: 50c4 str r4, [r0, r3] adds r3, r3, #4 800e24e: 3304 adds r3, #4 0800e250 : LoopCopyDataInit: adds r4, r0, r3 800e250: 18c4 adds r4, r0, r3 cmp r4, r1 800e252: 428c cmp r4, r1 bcc CopyDataInit 800e254: d3f9 bcc.n 800e24a /* Zero fill the bss segment. */ ldr r2, =_sbss 800e256: 4a09 ldr r2, [pc, #36] @ (800e27c ) ldr r4, =_ebss 800e258: 4c09 ldr r4, [pc, #36] @ (800e280 ) movs r3, #0 800e25a: 2300 movs r3, #0 b LoopFillZerobss 800e25c: e001 b.n 800e262 0800e25e : FillZerobss: str r3, [r2] 800e25e: 6013 str r3, [r2, #0] adds r2, r2, #4 800e260: 3204 adds r2, #4 0800e262 : LoopFillZerobss: cmp r2, r4 800e262: 42a2 cmp r2, r4 bcc FillZerobss 800e264: d3fb bcc.n 800e25e /* Call static constructors */ bl __libc_init_array 800e266: f006 fd2f bl 8014cc8 <__libc_init_array> /* Call the application's entry point.*/ bl main 800e26a: f7fc fc21 bl 800aab0
bx lr 800e26e: 4770 bx lr ldr r0, =_sdata 800e270: 20000000 .word 0x20000000 ldr r1, =_edata 800e274: 20000258 .word 0x20000258 ldr r2, =_sidata 800e278: 08017cdc .word 0x08017cdc ldr r2, =_sbss 800e27c: 20000258 .word 0x20000258 ldr r4, =_ebss 800e280: 200015d8 .word 0x200015d8 0800e284 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 800e284: e7fe b.n 800e284 ... 0800e288 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800e288: b580 push {r7, lr} 800e28a: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 800e28c: 4b08 ldr r3, [pc, #32] @ (800e2b0 ) 800e28e: 681b ldr r3, [r3, #0] 800e290: 4a07 ldr r2, [pc, #28] @ (800e2b0 ) 800e292: f043 0310 orr.w r3, r3, #16 800e296: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800e298: 2003 movs r0, #3 800e29a: f001 fd5d bl 800fd58 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800e29e: 200f movs r0, #15 800e2a0: f000 f808 bl 800e2b4 /* Init the low level hardware */ HAL_MspInit(); 800e2a4: f7ff f98a bl 800d5bc /* Return function status */ return HAL_OK; 800e2a8: 2300 movs r3, #0 } 800e2aa: 4618 mov r0, r3 800e2ac: bd80 pop {r7, pc} 800e2ae: bf00 nop 800e2b0: 40022000 .word 0x40022000 0800e2b4 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800e2b4: b580 push {r7, lr} 800e2b6: b082 sub sp, #8 800e2b8: af00 add r7, sp, #0 800e2ba: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 800e2bc: 4b12 ldr r3, [pc, #72] @ (800e308 ) 800e2be: 681a ldr r2, [r3, #0] 800e2c0: 4b12 ldr r3, [pc, #72] @ (800e30c ) 800e2c2: 781b ldrb r3, [r3, #0] 800e2c4: 4619 mov r1, r3 800e2c6: f44f 737a mov.w r3, #1000 @ 0x3e8 800e2ca: fbb3 f3f1 udiv r3, r3, r1 800e2ce: fbb2 f3f3 udiv r3, r2, r3 800e2d2: 4618 mov r0, r3 800e2d4: f001 fd75 bl 800fdc2 800e2d8: 4603 mov r3, r0 800e2da: 2b00 cmp r3, #0 800e2dc: d001 beq.n 800e2e2 { return HAL_ERROR; 800e2de: 2301 movs r3, #1 800e2e0: e00e b.n 800e300 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800e2e2: 687b ldr r3, [r7, #4] 800e2e4: 2b0f cmp r3, #15 800e2e6: d80a bhi.n 800e2fe { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800e2e8: 2200 movs r2, #0 800e2ea: 6879 ldr r1, [r7, #4] 800e2ec: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800e2f0: f001 fd3d bl 800fd6e uwTickPrio = TickPriority; 800e2f4: 4a06 ldr r2, [pc, #24] @ (800e310 ) 800e2f6: 687b ldr r3, [r7, #4] 800e2f8: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800e2fa: 2300 movs r3, #0 800e2fc: e000 b.n 800e300 return HAL_ERROR; 800e2fe: 2301 movs r3, #1 } 800e300: 4618 mov r0, r3 800e302: 3708 adds r7, #8 800e304: 46bd mov sp, r7 800e306: bd80 pop {r7, pc} 800e308: 20000084 .word 0x20000084 800e30c: 2000008c .word 0x2000008c 800e310: 20000088 .word 0x20000088 0800e314 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800e314: b480 push {r7} 800e316: af00 add r7, sp, #0 uwTick += uwTickFreq; 800e318: 4b05 ldr r3, [pc, #20] @ (800e330 ) 800e31a: 781b ldrb r3, [r3, #0] 800e31c: 461a mov r2, r3 800e31e: 4b05 ldr r3, [pc, #20] @ (800e334 ) 800e320: 681b ldr r3, [r3, #0] 800e322: 4413 add r3, r2 800e324: 4a03 ldr r2, [pc, #12] @ (800e334 ) 800e326: 6013 str r3, [r2, #0] } 800e328: bf00 nop 800e32a: 46bd mov sp, r7 800e32c: bc80 pop {r7} 800e32e: 4770 bx lr 800e330: 2000008c .word 0x2000008c 800e334: 20001488 .word 0x20001488 0800e338 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 800e338: b480 push {r7} 800e33a: af00 add r7, sp, #0 return uwTick; 800e33c: 4b02 ldr r3, [pc, #8] @ (800e348 ) 800e33e: 681b ldr r3, [r3, #0] } 800e340: 4618 mov r0, r3 800e342: 46bd mov sp, r7 800e344: bc80 pop {r7} 800e346: 4770 bx lr 800e348: 20001488 .word 0x20001488 0800e34c : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 800e34c: b580 push {r7, lr} 800e34e: b084 sub sp, #16 800e350: af00 add r7, sp, #0 800e352: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800e354: f7ff fff0 bl 800e338 800e358: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800e35a: 687b ldr r3, [r7, #4] 800e35c: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800e35e: 68fb ldr r3, [r7, #12] 800e360: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800e364: d005 beq.n 800e372 { wait += (uint32_t)(uwTickFreq); 800e366: 4b0a ldr r3, [pc, #40] @ (800e390 ) 800e368: 781b ldrb r3, [r3, #0] 800e36a: 461a mov r2, r3 800e36c: 68fb ldr r3, [r7, #12] 800e36e: 4413 add r3, r2 800e370: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 800e372: bf00 nop 800e374: f7ff ffe0 bl 800e338 800e378: 4602 mov r2, r0 800e37a: 68bb ldr r3, [r7, #8] 800e37c: 1ad3 subs r3, r2, r3 800e37e: 68fa ldr r2, [r7, #12] 800e380: 429a cmp r2, r3 800e382: d8f7 bhi.n 800e374 { } } 800e384: bf00 nop 800e386: bf00 nop 800e388: 3710 adds r7, #16 800e38a: 46bd mov sp, r7 800e38c: bd80 pop {r7, pc} 800e38e: bf00 nop 800e390: 2000008c .word 0x2000008c 0800e394 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 800e394: b580 push {r7, lr} 800e396: b086 sub sp, #24 800e398: af00 add r7, sp, #0 800e39a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e39c: 2300 movs r3, #0 800e39e: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 800e3a0: 2300 movs r3, #0 800e3a2: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 800e3a4: 2300 movs r3, #0 800e3a6: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 800e3a8: 2300 movs r3, #0 800e3aa: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 800e3ac: 687b ldr r3, [r7, #4] 800e3ae: 2b00 cmp r3, #0 800e3b0: d101 bne.n 800e3b6 { return HAL_ERROR; 800e3b2: 2301 movs r3, #1 800e3b4: e0be b.n 800e534 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 800e3b6: 687b ldr r3, [r7, #4] 800e3b8: 689b ldr r3, [r3, #8] 800e3ba: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 800e3bc: 687b ldr r3, [r7, #4] 800e3be: 6a9b ldr r3, [r3, #40] @ 0x28 800e3c0: 2b00 cmp r3, #0 800e3c2: d109 bne.n 800e3d8 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 800e3c4: 687b ldr r3, [r7, #4] 800e3c6: 2200 movs r2, #0 800e3c8: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 800e3ca: 687b ldr r3, [r7, #4] 800e3cc: 2200 movs r2, #0 800e3ce: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800e3d2: 6878 ldr r0, [r7, #4] 800e3d4: f7fb f966 bl 80096a4 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800e3d8: 6878 ldr r0, [r7, #4] 800e3da: f000 fbbd bl 800eb58 800e3de: 4603 mov r3, r0 800e3e0: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 800e3e2: 687b ldr r3, [r7, #4] 800e3e4: 6a9b ldr r3, [r3, #40] @ 0x28 800e3e6: f003 0310 and.w r3, r3, #16 800e3ea: 2b00 cmp r3, #0 800e3ec: f040 8099 bne.w 800e522 800e3f0: 7dfb ldrb r3, [r7, #23] 800e3f2: 2b00 cmp r3, #0 800e3f4: f040 8095 bne.w 800e522 (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e3f8: 687b ldr r3, [r7, #4] 800e3fa: 6a9b ldr r3, [r3, #40] @ 0x28 800e3fc: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800e400: f023 0302 bic.w r3, r3, #2 800e404: f043 0202 orr.w r2, r3, #2 800e408: 687b ldr r3, [r7, #4] 800e40a: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 800e40c: 687b ldr r3, [r7, #4] 800e40e: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800e410: 687b ldr r3, [r7, #4] 800e412: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 800e414: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 800e416: 687b ldr r3, [r7, #4] 800e418: 7b1b ldrb r3, [r3, #12] 800e41a: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800e41c: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 800e41e: 68ba ldr r2, [r7, #8] 800e420: 4313 orrs r3, r2 800e422: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 800e424: 687b ldr r3, [r7, #4] 800e426: 689b ldr r3, [r3, #8] 800e428: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e42c: d003 beq.n 800e436 800e42e: 687b ldr r3, [r7, #4] 800e430: 689b ldr r3, [r3, #8] 800e432: 2b01 cmp r3, #1 800e434: d102 bne.n 800e43c 800e436: f44f 7380 mov.w r3, #256 @ 0x100 800e43a: e000 b.n 800e43e 800e43c: 2300 movs r3, #0 800e43e: 693a ldr r2, [r7, #16] 800e440: 4313 orrs r3, r2 800e442: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 800e444: 687b ldr r3, [r7, #4] 800e446: 7d1b ldrb r3, [r3, #20] 800e448: 2b01 cmp r3, #1 800e44a: d119 bne.n 800e480 { if (hadc->Init.ContinuousConvMode == DISABLE) 800e44c: 687b ldr r3, [r7, #4] 800e44e: 7b1b ldrb r3, [r3, #12] 800e450: 2b00 cmp r3, #0 800e452: d109 bne.n 800e468 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 800e454: 687b ldr r3, [r7, #4] 800e456: 699b ldr r3, [r3, #24] 800e458: 3b01 subs r3, #1 800e45a: 035a lsls r2, r3, #13 800e45c: 693b ldr r3, [r7, #16] 800e45e: 4313 orrs r3, r2 800e460: f443 6300 orr.w r3, r3, #2048 @ 0x800 800e464: 613b str r3, [r7, #16] 800e466: e00b b.n 800e480 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800e468: 687b ldr r3, [r7, #4] 800e46a: 6a9b ldr r3, [r3, #40] @ 0x28 800e46c: f043 0220 orr.w r2, r3, #32 800e470: 687b ldr r3, [r7, #4] 800e472: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e474: 687b ldr r3, [r7, #4] 800e476: 6adb ldr r3, [r3, #44] @ 0x2c 800e478: f043 0201 orr.w r2, r3, #1 800e47c: 687b ldr r3, [r7, #4] 800e47e: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 800e480: 687b ldr r3, [r7, #4] 800e482: 681b ldr r3, [r3, #0] 800e484: 685b ldr r3, [r3, #4] 800e486: f423 4169 bic.w r1, r3, #59648 @ 0xe900 800e48a: 687b ldr r3, [r7, #4] 800e48c: 681b ldr r3, [r3, #0] 800e48e: 693a ldr r2, [r7, #16] 800e490: 430a orrs r2, r1 800e492: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 800e494: 687b ldr r3, [r7, #4] 800e496: 681b ldr r3, [r3, #0] 800e498: 689a ldr r2, [r3, #8] 800e49a: 4b28 ldr r3, [pc, #160] @ (800e53c ) 800e49c: 4013 ands r3, r2 800e49e: 687a ldr r2, [r7, #4] 800e4a0: 6812 ldr r2, [r2, #0] 800e4a2: 68b9 ldr r1, [r7, #8] 800e4a4: 430b orrs r3, r1 800e4a6: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 800e4a8: 687b ldr r3, [r7, #4] 800e4aa: 689b ldr r3, [r3, #8] 800e4ac: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e4b0: d003 beq.n 800e4ba 800e4b2: 687b ldr r3, [r7, #4] 800e4b4: 689b ldr r3, [r3, #8] 800e4b6: 2b01 cmp r3, #1 800e4b8: d104 bne.n 800e4c4 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 800e4ba: 687b ldr r3, [r7, #4] 800e4bc: 691b ldr r3, [r3, #16] 800e4be: 3b01 subs r3, #1 800e4c0: 051b lsls r3, r3, #20 800e4c2: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 800e4c4: 687b ldr r3, [r7, #4] 800e4c6: 681b ldr r3, [r3, #0] 800e4c8: 6adb ldr r3, [r3, #44] @ 0x2c 800e4ca: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 800e4ce: 687b ldr r3, [r7, #4] 800e4d0: 681b ldr r3, [r3, #0] 800e4d2: 68fa ldr r2, [r7, #12] 800e4d4: 430a orrs r2, r1 800e4d6: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800e4d8: 687b ldr r3, [r7, #4] 800e4da: 681b ldr r3, [r3, #0] 800e4dc: 689a ldr r2, [r3, #8] 800e4de: 4b18 ldr r3, [pc, #96] @ (800e540 ) 800e4e0: 4013 ands r3, r2 800e4e2: 68ba ldr r2, [r7, #8] 800e4e4: 429a cmp r2, r3 800e4e6: d10b bne.n 800e500 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 800e4e8: 687b ldr r3, [r7, #4] 800e4ea: 2200 movs r2, #0 800e4ec: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e4ee: 687b ldr r3, [r7, #4] 800e4f0: 6a9b ldr r3, [r3, #40] @ 0x28 800e4f2: f023 0303 bic.w r3, r3, #3 800e4f6: f043 0201 orr.w r2, r3, #1 800e4fa: 687b ldr r3, [r7, #4] 800e4fc: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800e4fe: e018 b.n 800e532 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800e500: 687b ldr r3, [r7, #4] 800e502: 6a9b ldr r3, [r3, #40] @ 0x28 800e504: f023 0312 bic.w r3, r3, #18 800e508: f043 0210 orr.w r2, r3, #16 800e50c: 687b ldr r3, [r7, #4] 800e50e: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e510: 687b ldr r3, [r7, #4] 800e512: 6adb ldr r3, [r3, #44] @ 0x2c 800e514: f043 0201 orr.w r2, r3, #1 800e518: 687b ldr r3, [r7, #4] 800e51a: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 800e51c: 2301 movs r3, #1 800e51e: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800e520: e007 b.n 800e532 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800e522: 687b ldr r3, [r7, #4] 800e524: 6a9b ldr r3, [r3, #40] @ 0x28 800e526: f043 0210 orr.w r2, r3, #16 800e52a: 687b ldr r3, [r7, #4] 800e52c: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800e52e: 2301 movs r3, #1 800e530: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800e532: 7dfb ldrb r3, [r7, #23] } 800e534: 4618 mov r0, r3 800e536: 3718 adds r7, #24 800e538: 46bd mov sp, r7 800e53a: bd80 pop {r7, pc} 800e53c: ffe1f7fd .word 0xffe1f7fd 800e540: ff1f0efe .word 0xff1f0efe 0800e544 : * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { 800e544: b580 push {r7, lr} 800e546: b086 sub sp, #24 800e548: af00 add r7, sp, #0 800e54a: 60f8 str r0, [r7, #12] 800e54c: 60b9 str r1, [r7, #8] 800e54e: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e550: 2300 movs r3, #0 800e552: 75fb strb r3, [r7, #23] assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); /* Verification if multimode is disabled (for devices with several ADC) */ /* If multimode is enabled, dedicated function multimode conversion */ /* start DMA must be used. */ if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) 800e554: 68fb ldr r3, [r7, #12] 800e556: 681b ldr r3, [r3, #0] 800e558: 4a64 ldr r2, [pc, #400] @ (800e6ec ) 800e55a: 4293 cmp r3, r2 800e55c: d004 beq.n 800e568 800e55e: 68fb ldr r3, [r7, #12] 800e560: 681b ldr r3, [r3, #0] 800e562: 4a63 ldr r2, [pc, #396] @ (800e6f0 ) 800e564: 4293 cmp r3, r2 800e566: d106 bne.n 800e576 800e568: 4b60 ldr r3, [pc, #384] @ (800e6ec ) 800e56a: 685b ldr r3, [r3, #4] 800e56c: f403 2370 and.w r3, r3, #983040 @ 0xf0000 800e570: 2b00 cmp r3, #0 800e572: f040 80b3 bne.w 800e6dc { /* Process locked */ __HAL_LOCK(hadc); 800e576: 68fb ldr r3, [r7, #12] 800e578: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e57c: 2b01 cmp r3, #1 800e57e: d101 bne.n 800e584 800e580: 2302 movs r3, #2 800e582: e0ae b.n 800e6e2 800e584: 68fb ldr r3, [r7, #12] 800e586: 2201 movs r2, #1 800e588: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 800e58c: 68f8 ldr r0, [r7, #12] 800e58e: f000 fa89 bl 800eaa4 800e592: 4603 mov r3, r0 800e594: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800e596: 7dfb ldrb r3, [r7, #23] 800e598: 2b00 cmp r3, #0 800e59a: f040 809a bne.w 800e6d2 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 800e59e: 68fb ldr r3, [r7, #12] 800e5a0: 6a9b ldr r3, [r3, #40] @ 0x28 800e5a2: f423 6370 bic.w r3, r3, #3840 @ 0xf00 800e5a6: f023 0301 bic.w r3, r3, #1 800e5aa: f443 7280 orr.w r2, r3, #256 @ 0x100 800e5ae: 68fb ldr r3, [r7, #12] 800e5b0: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 800e5b2: 68fb ldr r3, [r7, #12] 800e5b4: 681b ldr r3, [r3, #0] 800e5b6: 4a4e ldr r2, [pc, #312] @ (800e6f0 ) 800e5b8: 4293 cmp r3, r2 800e5ba: d105 bne.n 800e5c8 800e5bc: 4b4b ldr r3, [pc, #300] @ (800e6ec ) 800e5be: 685b ldr r3, [r3, #4] 800e5c0: f403 2370 and.w r3, r3, #983040 @ 0xf0000 800e5c4: 2b00 cmp r3, #0 800e5c6: d115 bne.n 800e5f4 { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800e5c8: 68fb ldr r3, [r7, #12] 800e5ca: 6a9b ldr r3, [r3, #40] @ 0x28 800e5cc: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 800e5d0: 68fb ldr r3, [r7, #12] 800e5d2: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800e5d4: 68fb ldr r3, [r7, #12] 800e5d6: 681b ldr r3, [r3, #0] 800e5d8: 685b ldr r3, [r3, #4] 800e5da: f403 6380 and.w r3, r3, #1024 @ 0x400 800e5de: 2b00 cmp r3, #0 800e5e0: d026 beq.n 800e630 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800e5e2: 68fb ldr r3, [r7, #12] 800e5e4: 6a9b ldr r3, [r3, #40] @ 0x28 800e5e6: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800e5ea: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800e5ee: 68fb ldr r3, [r7, #12] 800e5f0: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800e5f2: e01d b.n 800e630 } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800e5f4: 68fb ldr r3, [r7, #12] 800e5f6: 6a9b ldr r3, [r3, #40] @ 0x28 800e5f8: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800e5fc: 68fb ldr r3, [r7, #12] 800e5fe: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 800e600: 68fb ldr r3, [r7, #12] 800e602: 681b ldr r3, [r3, #0] 800e604: 4a39 ldr r2, [pc, #228] @ (800e6ec ) 800e606: 4293 cmp r3, r2 800e608: d004 beq.n 800e614 800e60a: 68fb ldr r3, [r7, #12] 800e60c: 681b ldr r3, [r3, #0] 800e60e: 4a38 ldr r2, [pc, #224] @ (800e6f0 ) 800e610: 4293 cmp r3, r2 800e612: d10d bne.n 800e630 800e614: 4b35 ldr r3, [pc, #212] @ (800e6ec ) 800e616: 685b ldr r3, [r3, #4] 800e618: f403 6380 and.w r3, r3, #1024 @ 0x400 800e61c: 2b00 cmp r3, #0 800e61e: d007 beq.n 800e630 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800e620: 68fb ldr r3, [r7, #12] 800e622: 6a9b ldr r3, [r3, #40] @ 0x28 800e624: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800e628: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800e62c: 68fb ldr r3, [r7, #12] 800e62e: 629a str r2, [r3, #40] @ 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800e630: 68fb ldr r3, [r7, #12] 800e632: 6a9b ldr r3, [r3, #40] @ 0x28 800e634: f403 5380 and.w r3, r3, #4096 @ 0x1000 800e638: 2b00 cmp r3, #0 800e63a: d006 beq.n 800e64a { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 800e63c: 68fb ldr r3, [r7, #12] 800e63e: 6adb ldr r3, [r3, #44] @ 0x2c 800e640: f023 0206 bic.w r2, r3, #6 800e644: 68fb ldr r3, [r7, #12] 800e646: 62da str r2, [r3, #44] @ 0x2c 800e648: e002 b.n 800e650 } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 800e64a: 68fb ldr r3, [r7, #12] 800e64c: 2200 movs r2, #0 800e64e: 62da str r2, [r3, #44] @ 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 800e650: 68fb ldr r3, [r7, #12] 800e652: 2200 movs r2, #0 800e654: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 800e658: 68fb ldr r3, [r7, #12] 800e65a: 6a1b ldr r3, [r3, #32] 800e65c: 4a25 ldr r2, [pc, #148] @ (800e6f4 ) 800e65e: 629a str r2, [r3, #40] @ 0x28 /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 800e660: 68fb ldr r3, [r7, #12] 800e662: 6a1b ldr r3, [r3, #32] 800e664: 4a24 ldr r2, [pc, #144] @ (800e6f8 ) 800e666: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 800e668: 68fb ldr r3, [r7, #12] 800e66a: 6a1b ldr r3, [r3, #32] 800e66c: 4a23 ldr r2, [pc, #140] @ (800e6fc ) 800e66e: 631a str r2, [r3, #48] @ 0x30 /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 800e670: 68fb ldr r3, [r7, #12] 800e672: 681b ldr r3, [r3, #0] 800e674: f06f 0202 mvn.w r2, #2 800e678: 601a str r2, [r3, #0] /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); 800e67a: 68fb ldr r3, [r7, #12] 800e67c: 681b ldr r3, [r3, #0] 800e67e: 689a ldr r2, [r3, #8] 800e680: 68fb ldr r3, [r7, #12] 800e682: 681b ldr r3, [r3, #0] 800e684: f442 7280 orr.w r2, r2, #256 @ 0x100 800e688: 609a str r2, [r3, #8] /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 800e68a: 68fb ldr r3, [r7, #12] 800e68c: 6a18 ldr r0, [r3, #32] 800e68e: 68fb ldr r3, [r7, #12] 800e690: 681b ldr r3, [r3, #0] 800e692: 334c adds r3, #76 @ 0x4c 800e694: 4619 mov r1, r3 800e696: 68ba ldr r2, [r7, #8] 800e698: 687b ldr r3, [r7, #4] 800e69a: f001 fc31 bl 800ff00 /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) 800e69e: 68fb ldr r3, [r7, #12] 800e6a0: 681b ldr r3, [r3, #0] 800e6a2: 689b ldr r3, [r3, #8] 800e6a4: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800e6a8: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e6ac: d108 bne.n 800e6c0 { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 800e6ae: 68fb ldr r3, [r7, #12] 800e6b0: 681b ldr r3, [r3, #0] 800e6b2: 689a ldr r2, [r3, #8] 800e6b4: 68fb ldr r3, [r7, #12] 800e6b6: 681b ldr r3, [r3, #0] 800e6b8: f442 02a0 orr.w r2, r2, #5242880 @ 0x500000 800e6bc: 609a str r2, [r3, #8] if (tmp_hal_status == HAL_OK) 800e6be: e00f b.n 800e6e0 } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 800e6c0: 68fb ldr r3, [r7, #12] 800e6c2: 681b ldr r3, [r3, #0] 800e6c4: 689a ldr r2, [r3, #8] 800e6c6: 68fb ldr r3, [r7, #12] 800e6c8: 681b ldr r3, [r3, #0] 800e6ca: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 800e6ce: 609a str r2, [r3, #8] if (tmp_hal_status == HAL_OK) 800e6d0: e006 b.n 800e6e0 } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 800e6d2: 68fb ldr r3, [r7, #12] 800e6d4: 2200 movs r2, #0 800e6d6: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (tmp_hal_status == HAL_OK) 800e6da: e001 b.n 800e6e0 } } else { tmp_hal_status = HAL_ERROR; 800e6dc: 2301 movs r3, #1 800e6de: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800e6e0: 7dfb ldrb r3, [r7, #23] } 800e6e2: 4618 mov r0, r3 800e6e4: 3718 adds r7, #24 800e6e6: 46bd mov sp, r7 800e6e8: bd80 pop {r7, pc} 800e6ea: bf00 nop 800e6ec: 40012400 .word 0x40012400 800e6f0: 40012800 .word 0x40012800 800e6f4: 0800ebdb .word 0x0800ebdb 800e6f8: 0800ec57 .word 0x0800ec57 800e6fc: 0800ec73 .word 0x0800ec73 0800e700 : * @brief Handles ADC interrupt request * @param hadc: ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { 800e700: b580 push {r7, lr} 800e702: b084 sub sp, #16 800e704: af00 add r7, sp, #0 800e706: 6078 str r0, [r7, #4] uint32_t tmp_sr = hadc->Instance->SR; 800e708: 687b ldr r3, [r7, #4] 800e70a: 681b ldr r3, [r3, #0] 800e70c: 681b ldr r3, [r3, #0] 800e70e: 60fb str r3, [r7, #12] uint32_t tmp_cr1 = hadc->Instance->CR1; 800e710: 687b ldr r3, [r7, #4] 800e712: 681b ldr r3, [r3, #0] 800e714: 685b ldr r3, [r3, #4] 800e716: 60bb str r3, [r7, #8] assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); /* ========== Check End of Conversion flag for regular group ========== */ if((tmp_cr1 & ADC_IT_EOC) == ADC_IT_EOC) 800e718: 68bb ldr r3, [r7, #8] 800e71a: f003 0320 and.w r3, r3, #32 800e71e: 2b00 cmp r3, #0 800e720: d03e beq.n 800e7a0 { if((tmp_sr & ADC_FLAG_EOC) == ADC_FLAG_EOC) 800e722: 68fb ldr r3, [r7, #12] 800e724: f003 0302 and.w r3, r3, #2 800e728: 2b00 cmp r3, #0 800e72a: d039 beq.n 800e7a0 { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 800e72c: 687b ldr r3, [r7, #4] 800e72e: 6a9b ldr r3, [r3, #40] @ 0x28 800e730: f003 0310 and.w r3, r3, #16 800e734: 2b00 cmp r3, #0 800e736: d105 bne.n 800e744 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800e738: 687b ldr r3, [r7, #4] 800e73a: 6a9b ldr r3, [r3, #40] @ 0x28 800e73c: f443 7200 orr.w r2, r3, #512 @ 0x200 800e740: 687b ldr r3, [r7, #4] 800e742: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e744: 687b ldr r3, [r7, #4] 800e746: 681b ldr r3, [r3, #0] 800e748: 689b ldr r3, [r3, #8] 800e74a: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800e74e: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e752: d11d bne.n 800e790 (hadc->Init.ContinuousConvMode == DISABLE) ) 800e754: 687b ldr r3, [r7, #4] 800e756: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e758: 2b00 cmp r3, #0 800e75a: d119 bne.n 800e790 { /* Disable ADC end of conversion interrupt on group regular */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); 800e75c: 687b ldr r3, [r7, #4] 800e75e: 681b ldr r3, [r3, #0] 800e760: 685a ldr r2, [r3, #4] 800e762: 687b ldr r3, [r7, #4] 800e764: 681b ldr r3, [r3, #0] 800e766: f022 0220 bic.w r2, r2, #32 800e76a: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800e76c: 687b ldr r3, [r7, #4] 800e76e: 6a9b ldr r3, [r3, #40] @ 0x28 800e770: f423 7280 bic.w r2, r3, #256 @ 0x100 800e774: 687b ldr r3, [r7, #4] 800e776: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800e778: 687b ldr r3, [r7, #4] 800e77a: 6a9b ldr r3, [r3, #40] @ 0x28 800e77c: f403 5380 and.w r3, r3, #4096 @ 0x1000 800e780: 2b00 cmp r3, #0 800e782: d105 bne.n 800e790 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800e784: 687b ldr r3, [r7, #4] 800e786: 6a9b ldr r3, [r3, #40] @ 0x28 800e788: f043 0201 orr.w r2, r3, #1 800e78c: 687b ldr r3, [r7, #4] 800e78e: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800e790: 6878 ldr r0, [r7, #4] 800e792: f7fa fedb bl 800954c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 800e796: 687b ldr r3, [r7, #4] 800e798: 681b ldr r3, [r3, #0] 800e79a: f06f 0212 mvn.w r2, #18 800e79e: 601a str r2, [r3, #0] } } /* ========== Check End of Conversion flag for injected group ========== */ if((tmp_cr1 & ADC_IT_JEOC) == ADC_IT_JEOC) 800e7a0: 68bb ldr r3, [r7, #8] 800e7a2: f003 0380 and.w r3, r3, #128 @ 0x80 800e7a6: 2b00 cmp r3, #0 800e7a8: d04d beq.n 800e846 { if((tmp_sr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) 800e7aa: 68fb ldr r3, [r7, #12] 800e7ac: f003 0304 and.w r3, r3, #4 800e7b0: 2b00 cmp r3, #0 800e7b2: d048 beq.n 800e846 { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 800e7b4: 687b ldr r3, [r7, #4] 800e7b6: 6a9b ldr r3, [r3, #40] @ 0x28 800e7b8: f003 0310 and.w r3, r3, #16 800e7bc: 2b00 cmp r3, #0 800e7be: d105 bne.n 800e7cc { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 800e7c0: 687b ldr r3, [r7, #4] 800e7c2: 6a9b ldr r3, [r3, #40] @ 0x28 800e7c4: f443 5200 orr.w r2, r3, #8192 @ 0x2000 800e7c8: 687b ldr r3, [r7, #4] 800e7ca: 629a str r2, [r3, #40] @ 0x28 /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 800e7cc: 687b ldr r3, [r7, #4] 800e7ce: 681b ldr r3, [r3, #0] 800e7d0: 689b ldr r3, [r3, #8] 800e7d2: f403 43e0 and.w r3, r3, #28672 @ 0x7000 800e7d6: f5b3 4fe0 cmp.w r3, #28672 @ 0x7000 800e7da: d012 beq.n 800e802 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 800e7dc: 687b ldr r3, [r7, #4] 800e7de: 681b ldr r3, [r3, #0] 800e7e0: 685b ldr r3, [r3, #4] 800e7e2: f403 6380 and.w r3, r3, #1024 @ 0x400 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 800e7e6: 2b00 cmp r3, #0 800e7e8: d125 bne.n 800e836 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e7ea: 687b ldr r3, [r7, #4] 800e7ec: 681b ldr r3, [r3, #0] 800e7ee: 689b ldr r3, [r3, #8] 800e7f0: f403 2360 and.w r3, r3, #917504 @ 0xe0000 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 800e7f4: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e7f8: d11d bne.n 800e836 (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) 800e7fa: 687b ldr r3, [r7, #4] 800e7fc: 7b1b ldrb r3, [r3, #12] (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e7fe: 2b00 cmp r3, #0 800e800: d119 bne.n 800e836 { /* Disable ADC end of conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 800e802: 687b ldr r3, [r7, #4] 800e804: 681b ldr r3, [r3, #0] 800e806: 685a ldr r2, [r3, #4] 800e808: 687b ldr r3, [r7, #4] 800e80a: 681b ldr r3, [r3, #0] 800e80c: f022 0280 bic.w r2, r2, #128 @ 0x80 800e810: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 800e812: 687b ldr r3, [r7, #4] 800e814: 6a9b ldr r3, [r3, #40] @ 0x28 800e816: f423 5280 bic.w r2, r3, #4096 @ 0x1000 800e81a: 687b ldr r3, [r7, #4] 800e81c: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 800e81e: 687b ldr r3, [r7, #4] 800e820: 6a9b ldr r3, [r3, #40] @ 0x28 800e822: f403 7380 and.w r3, r3, #256 @ 0x100 800e826: 2b00 cmp r3, #0 800e828: d105 bne.n 800e836 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800e82a: 687b ldr r3, [r7, #4] 800e82c: 6a9b ldr r3, [r3, #40] @ 0x28 800e82e: f043 0201 orr.w r2, r3, #1 800e832: 687b ldr r3, [r7, #4] 800e834: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); 800e836: 6878 ldr r0, [r7, #4] 800e838: f000 fae4 bl 800ee04 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); 800e83c: 687b ldr r3, [r7, #4] 800e83e: 681b ldr r3, [r3, #0] 800e840: f06f 020c mvn.w r2, #12 800e844: 601a str r2, [r3, #0] } } /* ========== Check Analog watchdog flags ========== */ if((tmp_cr1 & ADC_IT_AWD) == ADC_IT_AWD) 800e846: 68bb ldr r3, [r7, #8] 800e848: f003 0340 and.w r3, r3, #64 @ 0x40 800e84c: 2b00 cmp r3, #0 800e84e: d012 beq.n 800e876 { if((tmp_sr & ADC_FLAG_AWD) == ADC_FLAG_AWD) 800e850: 68fb ldr r3, [r7, #12] 800e852: f003 0301 and.w r3, r3, #1 800e856: 2b00 cmp r3, #0 800e858: d00d beq.n 800e876 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 800e85a: 687b ldr r3, [r7, #4] 800e85c: 6a9b ldr r3, [r3, #40] @ 0x28 800e85e: f443 3280 orr.w r2, r3, #65536 @ 0x10000 800e862: 687b ldr r3, [r7, #4] 800e864: 629a str r2, [r3, #40] @ 0x28 /* Level out of window callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); 800e866: 6878 ldr r0, [r7, #4] 800e868: f000 f812 bl 800e890 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear the ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); 800e86c: 687b ldr r3, [r7, #4] 800e86e: 681b ldr r3, [r3, #0] 800e870: f06f 0201 mvn.w r2, #1 800e874: 601a str r2, [r3, #0] } } } 800e876: bf00 nop 800e878: 3710 adds r7, #16 800e87a: 46bd mov sp, r7 800e87c: bd80 pop {r7, pc} 0800e87e : * @brief Conversion DMA half-transfer callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) { 800e87e: b480 push {r7} 800e880: b083 sub sp, #12 800e882: af00 add r7, sp, #0 800e884: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 800e886: bf00 nop 800e888: 370c adds r7, #12 800e88a: 46bd mov sp, r7 800e88c: bc80 pop {r7} 800e88e: 4770 bx lr 0800e890 : * @brief Analog watchdog callback in non blocking mode. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { 800e890: b480 push {r7} 800e892: b083 sub sp, #12 800e894: af00 add r7, sp, #0 800e896: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } 800e898: bf00 nop 800e89a: 370c adds r7, #12 800e89c: 46bd mov sp, r7 800e89e: bc80 pop {r7} 800e8a0: 4770 bx lr 0800e8a2 : * (ADC conversion with interruption or transfer by DMA) * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 800e8a2: b480 push {r7} 800e8a4: b083 sub sp, #12 800e8a6: af00 add r7, sp, #0 800e8a8: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 800e8aa: bf00 nop 800e8ac: 370c adds r7, #12 800e8ae: 46bd mov sp, r7 800e8b0: bc80 pop {r7} 800e8b2: 4770 bx lr 0800e8b4 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 800e8b4: b480 push {r7} 800e8b6: b085 sub sp, #20 800e8b8: af00 add r7, sp, #0 800e8ba: 6078 str r0, [r7, #4] 800e8bc: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e8be: 2300 movs r3, #0 800e8c0: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 800e8c2: 2300 movs r3, #0 800e8c4: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 800e8c6: 687b ldr r3, [r7, #4] 800e8c8: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e8cc: 2b01 cmp r3, #1 800e8ce: d101 bne.n 800e8d4 800e8d0: 2302 movs r3, #2 800e8d2: e0dc b.n 800ea8e 800e8d4: 687b ldr r3, [r7, #4] 800e8d6: 2201 movs r2, #1 800e8d8: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 800e8dc: 683b ldr r3, [r7, #0] 800e8de: 685b ldr r3, [r3, #4] 800e8e0: 2b06 cmp r3, #6 800e8e2: d81c bhi.n 800e91e { MODIFY_REG(hadc->Instance->SQR3 , 800e8e4: 687b ldr r3, [r7, #4] 800e8e6: 681b ldr r3, [r3, #0] 800e8e8: 6b59 ldr r1, [r3, #52] @ 0x34 800e8ea: 683b ldr r3, [r7, #0] 800e8ec: 685a ldr r2, [r3, #4] 800e8ee: 4613 mov r3, r2 800e8f0: 009b lsls r3, r3, #2 800e8f2: 4413 add r3, r2 800e8f4: 3b05 subs r3, #5 800e8f6: 221f movs r2, #31 800e8f8: fa02 f303 lsl.w r3, r2, r3 800e8fc: 43db mvns r3, r3 800e8fe: 4019 ands r1, r3 800e900: 683b ldr r3, [r7, #0] 800e902: 6818 ldr r0, [r3, #0] 800e904: 683b ldr r3, [r7, #0] 800e906: 685a ldr r2, [r3, #4] 800e908: 4613 mov r3, r2 800e90a: 009b lsls r3, r3, #2 800e90c: 4413 add r3, r2 800e90e: 3b05 subs r3, #5 800e910: fa00 f203 lsl.w r2, r0, r3 800e914: 687b ldr r3, [r7, #4] 800e916: 681b ldr r3, [r3, #0] 800e918: 430a orrs r2, r1 800e91a: 635a str r2, [r3, #52] @ 0x34 800e91c: e03c b.n 800e998 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 800e91e: 683b ldr r3, [r7, #0] 800e920: 685b ldr r3, [r3, #4] 800e922: 2b0c cmp r3, #12 800e924: d81c bhi.n 800e960 { MODIFY_REG(hadc->Instance->SQR2 , 800e926: 687b ldr r3, [r7, #4] 800e928: 681b ldr r3, [r3, #0] 800e92a: 6b19 ldr r1, [r3, #48] @ 0x30 800e92c: 683b ldr r3, [r7, #0] 800e92e: 685a ldr r2, [r3, #4] 800e930: 4613 mov r3, r2 800e932: 009b lsls r3, r3, #2 800e934: 4413 add r3, r2 800e936: 3b23 subs r3, #35 @ 0x23 800e938: 221f movs r2, #31 800e93a: fa02 f303 lsl.w r3, r2, r3 800e93e: 43db mvns r3, r3 800e940: 4019 ands r1, r3 800e942: 683b ldr r3, [r7, #0] 800e944: 6818 ldr r0, [r3, #0] 800e946: 683b ldr r3, [r7, #0] 800e948: 685a ldr r2, [r3, #4] 800e94a: 4613 mov r3, r2 800e94c: 009b lsls r3, r3, #2 800e94e: 4413 add r3, r2 800e950: 3b23 subs r3, #35 @ 0x23 800e952: fa00 f203 lsl.w r2, r0, r3 800e956: 687b ldr r3, [r7, #4] 800e958: 681b ldr r3, [r3, #0] 800e95a: 430a orrs r2, r1 800e95c: 631a str r2, [r3, #48] @ 0x30 800e95e: e01b b.n 800e998 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 800e960: 687b ldr r3, [r7, #4] 800e962: 681b ldr r3, [r3, #0] 800e964: 6ad9 ldr r1, [r3, #44] @ 0x2c 800e966: 683b ldr r3, [r7, #0] 800e968: 685a ldr r2, [r3, #4] 800e96a: 4613 mov r3, r2 800e96c: 009b lsls r3, r3, #2 800e96e: 4413 add r3, r2 800e970: 3b41 subs r3, #65 @ 0x41 800e972: 221f movs r2, #31 800e974: fa02 f303 lsl.w r3, r2, r3 800e978: 43db mvns r3, r3 800e97a: 4019 ands r1, r3 800e97c: 683b ldr r3, [r7, #0] 800e97e: 6818 ldr r0, [r3, #0] 800e980: 683b ldr r3, [r7, #0] 800e982: 685a ldr r2, [r3, #4] 800e984: 4613 mov r3, r2 800e986: 009b lsls r3, r3, #2 800e988: 4413 add r3, r2 800e98a: 3b41 subs r3, #65 @ 0x41 800e98c: fa00 f203 lsl.w r2, r0, r3 800e990: 687b ldr r3, [r7, #4] 800e992: 681b ldr r3, [r3, #0] 800e994: 430a orrs r2, r1 800e996: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 800e998: 683b ldr r3, [r7, #0] 800e99a: 681b ldr r3, [r3, #0] 800e99c: 2b09 cmp r3, #9 800e99e: d91c bls.n 800e9da { MODIFY_REG(hadc->Instance->SMPR1 , 800e9a0: 687b ldr r3, [r7, #4] 800e9a2: 681b ldr r3, [r3, #0] 800e9a4: 68d9 ldr r1, [r3, #12] 800e9a6: 683b ldr r3, [r7, #0] 800e9a8: 681a ldr r2, [r3, #0] 800e9aa: 4613 mov r3, r2 800e9ac: 005b lsls r3, r3, #1 800e9ae: 4413 add r3, r2 800e9b0: 3b1e subs r3, #30 800e9b2: 2207 movs r2, #7 800e9b4: fa02 f303 lsl.w r3, r2, r3 800e9b8: 43db mvns r3, r3 800e9ba: 4019 ands r1, r3 800e9bc: 683b ldr r3, [r7, #0] 800e9be: 6898 ldr r0, [r3, #8] 800e9c0: 683b ldr r3, [r7, #0] 800e9c2: 681a ldr r2, [r3, #0] 800e9c4: 4613 mov r3, r2 800e9c6: 005b lsls r3, r3, #1 800e9c8: 4413 add r3, r2 800e9ca: 3b1e subs r3, #30 800e9cc: fa00 f203 lsl.w r2, r0, r3 800e9d0: 687b ldr r3, [r7, #4] 800e9d2: 681b ldr r3, [r3, #0] 800e9d4: 430a orrs r2, r1 800e9d6: 60da str r2, [r3, #12] 800e9d8: e019 b.n 800ea0e ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 800e9da: 687b ldr r3, [r7, #4] 800e9dc: 681b ldr r3, [r3, #0] 800e9de: 6919 ldr r1, [r3, #16] 800e9e0: 683b ldr r3, [r7, #0] 800e9e2: 681a ldr r2, [r3, #0] 800e9e4: 4613 mov r3, r2 800e9e6: 005b lsls r3, r3, #1 800e9e8: 4413 add r3, r2 800e9ea: 2207 movs r2, #7 800e9ec: fa02 f303 lsl.w r3, r2, r3 800e9f0: 43db mvns r3, r3 800e9f2: 4019 ands r1, r3 800e9f4: 683b ldr r3, [r7, #0] 800e9f6: 6898 ldr r0, [r3, #8] 800e9f8: 683b ldr r3, [r7, #0] 800e9fa: 681a ldr r2, [r3, #0] 800e9fc: 4613 mov r3, r2 800e9fe: 005b lsls r3, r3, #1 800ea00: 4413 add r3, r2 800ea02: fa00 f203 lsl.w r2, r0, r3 800ea06: 687b ldr r3, [r7, #4] 800ea08: 681b ldr r3, [r3, #0] 800ea0a: 430a orrs r2, r1 800ea0c: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800ea0e: 683b ldr r3, [r7, #0] 800ea10: 681b ldr r3, [r3, #0] 800ea12: 2b10 cmp r3, #16 800ea14: d003 beq.n 800ea1e (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 800ea16: 683b ldr r3, [r7, #0] 800ea18: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800ea1a: 2b11 cmp r3, #17 800ea1c: d132 bne.n 800ea84 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 800ea1e: 687b ldr r3, [r7, #4] 800ea20: 681b ldr r3, [r3, #0] 800ea22: 4a1d ldr r2, [pc, #116] @ (800ea98 ) 800ea24: 4293 cmp r3, r2 800ea26: d125 bne.n 800ea74 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 800ea28: 687b ldr r3, [r7, #4] 800ea2a: 681b ldr r3, [r3, #0] 800ea2c: 689b ldr r3, [r3, #8] 800ea2e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800ea32: 2b00 cmp r3, #0 800ea34: d126 bne.n 800ea84 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 800ea36: 687b ldr r3, [r7, #4] 800ea38: 681b ldr r3, [r3, #0] 800ea3a: 689a ldr r2, [r3, #8] 800ea3c: 687b ldr r3, [r7, #4] 800ea3e: 681b ldr r3, [r3, #0] 800ea40: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 800ea44: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 800ea46: 683b ldr r3, [r7, #0] 800ea48: 681b ldr r3, [r3, #0] 800ea4a: 2b10 cmp r3, #16 800ea4c: d11a bne.n 800ea84 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 800ea4e: 4b13 ldr r3, [pc, #76] @ (800ea9c ) 800ea50: 681b ldr r3, [r3, #0] 800ea52: 4a13 ldr r2, [pc, #76] @ (800eaa0 ) 800ea54: fba2 2303 umull r2, r3, r2, r3 800ea58: 0c9a lsrs r2, r3, #18 800ea5a: 4613 mov r3, r2 800ea5c: 009b lsls r3, r3, #2 800ea5e: 4413 add r3, r2 800ea60: 005b lsls r3, r3, #1 800ea62: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800ea64: e002 b.n 800ea6c { wait_loop_index--; 800ea66: 68bb ldr r3, [r7, #8] 800ea68: 3b01 subs r3, #1 800ea6a: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800ea6c: 68bb ldr r3, [r7, #8] 800ea6e: 2b00 cmp r3, #0 800ea70: d1f9 bne.n 800ea66 800ea72: e007 b.n 800ea84 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800ea74: 687b ldr r3, [r7, #4] 800ea76: 6a9b ldr r3, [r3, #40] @ 0x28 800ea78: f043 0220 orr.w r2, r3, #32 800ea7c: 687b ldr r3, [r7, #4] 800ea7e: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800ea80: 2301 movs r3, #1 800ea82: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 800ea84: 687b ldr r3, [r7, #4] 800ea86: 2200 movs r2, #0 800ea88: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800ea8c: 7bfb ldrb r3, [r7, #15] } 800ea8e: 4618 mov r0, r3 800ea90: 3714 adds r7, #20 800ea92: 46bd mov sp, r7 800ea94: bc80 pop {r7} 800ea96: 4770 bx lr 800ea98: 40012400 .word 0x40012400 800ea9c: 20000084 .word 0x20000084 800eaa0: 431bde83 .word 0x431bde83 0800eaa4 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 800eaa4: b580 push {r7, lr} 800eaa6: b084 sub sp, #16 800eaa8: af00 add r7, sp, #0 800eaaa: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800eaac: 2300 movs r3, #0 800eaae: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 800eab0: 2300 movs r3, #0 800eab2: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 800eab4: 687b ldr r3, [r7, #4] 800eab6: 681b ldr r3, [r3, #0] 800eab8: 689b ldr r3, [r3, #8] 800eaba: f003 0301 and.w r3, r3, #1 800eabe: 2b01 cmp r3, #1 800eac0: d040 beq.n 800eb44 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 800eac2: 687b ldr r3, [r7, #4] 800eac4: 681b ldr r3, [r3, #0] 800eac6: 689a ldr r2, [r3, #8] 800eac8: 687b ldr r3, [r7, #4] 800eaca: 681b ldr r3, [r3, #0] 800eacc: f042 0201 orr.w r2, r2, #1 800ead0: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 800ead2: 4b1f ldr r3, [pc, #124] @ (800eb50 ) 800ead4: 681b ldr r3, [r3, #0] 800ead6: 4a1f ldr r2, [pc, #124] @ (800eb54 ) 800ead8: fba2 2303 umull r2, r3, r2, r3 800eadc: 0c9b lsrs r3, r3, #18 800eade: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800eae0: e002 b.n 800eae8 { wait_loop_index--; 800eae2: 68bb ldr r3, [r7, #8] 800eae4: 3b01 subs r3, #1 800eae6: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800eae8: 68bb ldr r3, [r7, #8] 800eaea: 2b00 cmp r3, #0 800eaec: d1f9 bne.n 800eae2 } /* Get tick count */ tickstart = HAL_GetTick(); 800eaee: f7ff fc23 bl 800e338 800eaf2: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 800eaf4: e01f b.n 800eb36 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 800eaf6: f7ff fc1f bl 800e338 800eafa: 4602 mov r2, r0 800eafc: 68fb ldr r3, [r7, #12] 800eafe: 1ad3 subs r3, r2, r3 800eb00: 2b02 cmp r3, #2 800eb02: d918 bls.n 800eb36 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 800eb04: 687b ldr r3, [r7, #4] 800eb06: 681b ldr r3, [r3, #0] 800eb08: 689b ldr r3, [r3, #8] 800eb0a: f003 0301 and.w r3, r3, #1 800eb0e: 2b01 cmp r3, #1 800eb10: d011 beq.n 800eb36 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800eb12: 687b ldr r3, [r7, #4] 800eb14: 6a9b ldr r3, [r3, #40] @ 0x28 800eb16: f043 0210 orr.w r2, r3, #16 800eb1a: 687b ldr r3, [r7, #4] 800eb1c: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800eb1e: 687b ldr r3, [r7, #4] 800eb20: 6adb ldr r3, [r3, #44] @ 0x2c 800eb22: f043 0201 orr.w r2, r3, #1 800eb26: 687b ldr r3, [r7, #4] 800eb28: 62da str r2, [r3, #44] @ 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 800eb2a: 687b ldr r3, [r7, #4] 800eb2c: 2200 movs r2, #0 800eb2e: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800eb32: 2301 movs r3, #1 800eb34: e007 b.n 800eb46 while(ADC_IS_ENABLE(hadc) == RESET) 800eb36: 687b ldr r3, [r7, #4] 800eb38: 681b ldr r3, [r3, #0] 800eb3a: 689b ldr r3, [r3, #8] 800eb3c: f003 0301 and.w r3, r3, #1 800eb40: 2b01 cmp r3, #1 800eb42: d1d8 bne.n 800eaf6 } } } /* Return HAL status */ return HAL_OK; 800eb44: 2300 movs r3, #0 } 800eb46: 4618 mov r0, r3 800eb48: 3710 adds r7, #16 800eb4a: 46bd mov sp, r7 800eb4c: bd80 pop {r7, pc} 800eb4e: bf00 nop 800eb50: 20000084 .word 0x20000084 800eb54: 431bde83 .word 0x431bde83 0800eb58 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 800eb58: b580 push {r7, lr} 800eb5a: b084 sub sp, #16 800eb5c: af00 add r7, sp, #0 800eb5e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800eb60: 2300 movs r3, #0 800eb62: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 800eb64: 687b ldr r3, [r7, #4] 800eb66: 681b ldr r3, [r3, #0] 800eb68: 689b ldr r3, [r3, #8] 800eb6a: f003 0301 and.w r3, r3, #1 800eb6e: 2b01 cmp r3, #1 800eb70: d12e bne.n 800ebd0 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 800eb72: 687b ldr r3, [r7, #4] 800eb74: 681b ldr r3, [r3, #0] 800eb76: 689a ldr r2, [r3, #8] 800eb78: 687b ldr r3, [r7, #4] 800eb7a: 681b ldr r3, [r3, #0] 800eb7c: f022 0201 bic.w r2, r2, #1 800eb80: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 800eb82: f7ff fbd9 bl 800e338 800eb86: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 800eb88: e01b b.n 800ebc2 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800eb8a: f7ff fbd5 bl 800e338 800eb8e: 4602 mov r2, r0 800eb90: 68fb ldr r3, [r7, #12] 800eb92: 1ad3 subs r3, r2, r3 800eb94: 2b02 cmp r3, #2 800eb96: d914 bls.n 800ebc2 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 800eb98: 687b ldr r3, [r7, #4] 800eb9a: 681b ldr r3, [r3, #0] 800eb9c: 689b ldr r3, [r3, #8] 800eb9e: f003 0301 and.w r3, r3, #1 800eba2: 2b01 cmp r3, #1 800eba4: d10d bne.n 800ebc2 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800eba6: 687b ldr r3, [r7, #4] 800eba8: 6a9b ldr r3, [r3, #40] @ 0x28 800ebaa: f043 0210 orr.w r2, r3, #16 800ebae: 687b ldr r3, [r7, #4] 800ebb0: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800ebb2: 687b ldr r3, [r7, #4] 800ebb4: 6adb ldr r3, [r3, #44] @ 0x2c 800ebb6: f043 0201 orr.w r2, r3, #1 800ebba: 687b ldr r3, [r7, #4] 800ebbc: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 800ebbe: 2301 movs r3, #1 800ebc0: e007 b.n 800ebd2 while(ADC_IS_ENABLE(hadc) != RESET) 800ebc2: 687b ldr r3, [r7, #4] 800ebc4: 681b ldr r3, [r3, #0] 800ebc6: 689b ldr r3, [r3, #8] 800ebc8: f003 0301 and.w r3, r3, #1 800ebcc: 2b01 cmp r3, #1 800ebce: d0dc beq.n 800eb8a } } } /* Return HAL status */ return HAL_OK; 800ebd0: 2300 movs r3, #0 } 800ebd2: 4618 mov r0, r3 800ebd4: 3710 adds r7, #16 800ebd6: 46bd mov sp, r7 800ebd8: bd80 pop {r7, pc} 0800ebda : * @brief DMA transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 800ebda: b580 push {r7, lr} 800ebdc: b084 sub sp, #16 800ebde: af00 add r7, sp, #0 800ebe0: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800ebe2: 687b ldr r3, [r7, #4] 800ebe4: 6a5b ldr r3, [r3, #36] @ 0x24 800ebe6: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) 800ebe8: 68fb ldr r3, [r7, #12] 800ebea: 6a9b ldr r3, [r3, #40] @ 0x28 800ebec: f003 0350 and.w r3, r3, #80 @ 0x50 800ebf0: 2b00 cmp r3, #0 800ebf2: d127 bne.n 800ec44 { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800ebf4: 68fb ldr r3, [r7, #12] 800ebf6: 6a9b ldr r3, [r3, #40] @ 0x28 800ebf8: f443 7200 orr.w r2, r3, #512 @ 0x200 800ebfc: 68fb ldr r3, [r7, #12] 800ebfe: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800ec00: 68fb ldr r3, [r7, #12] 800ec02: 681b ldr r3, [r3, #0] 800ec04: 689b ldr r3, [r3, #8] 800ec06: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800ec0a: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800ec0e: d115 bne.n 800ec3c (hadc->Init.ContinuousConvMode == DISABLE) ) 800ec10: 68fb ldr r3, [r7, #12] 800ec12: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800ec14: 2b00 cmp r3, #0 800ec16: d111 bne.n 800ec3c { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800ec18: 68fb ldr r3, [r7, #12] 800ec1a: 6a9b ldr r3, [r3, #40] @ 0x28 800ec1c: f423 7280 bic.w r2, r3, #256 @ 0x100 800ec20: 68fb ldr r3, [r7, #12] 800ec22: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800ec24: 68fb ldr r3, [r7, #12] 800ec26: 6a9b ldr r3, [r3, #40] @ 0x28 800ec28: f403 5380 and.w r3, r3, #4096 @ 0x1000 800ec2c: 2b00 cmp r3, #0 800ec2e: d105 bne.n 800ec3c { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800ec30: 68fb ldr r3, [r7, #12] 800ec32: 6a9b ldr r3, [r3, #40] @ 0x28 800ec34: f043 0201 orr.w r2, r3, #1 800ec38: 68fb ldr r3, [r7, #12] 800ec3a: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800ec3c: 68f8 ldr r0, [r7, #12] 800ec3e: f7fa fc85 bl 800954c else { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } 800ec42: e004 b.n 800ec4e hadc->DMA_Handle->XferErrorCallback(hdma); 800ec44: 68fb ldr r3, [r7, #12] 800ec46: 6a1b ldr r3, [r3, #32] 800ec48: 6b1b ldr r3, [r3, #48] @ 0x30 800ec4a: 6878 ldr r0, [r7, #4] 800ec4c: 4798 blx r3 } 800ec4e: bf00 nop 800ec50: 3710 adds r7, #16 800ec52: 46bd mov sp, r7 800ec54: bd80 pop {r7, pc} 0800ec56 : * @brief DMA half transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 800ec56: b580 push {r7, lr} 800ec58: b084 sub sp, #16 800ec5a: af00 add r7, sp, #0 800ec5c: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800ec5e: 687b ldr r3, [r7, #4] 800ec60: 6a5b ldr r3, [r3, #36] @ 0x24 800ec62: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 800ec64: 68f8 ldr r0, [r7, #12] 800ec66: f7ff fe0a bl 800e87e #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800ec6a: bf00 nop 800ec6c: 3710 adds r7, #16 800ec6e: 46bd mov sp, r7 800ec70: bd80 pop {r7, pc} 0800ec72 : * @brief DMA error callback * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 800ec72: b580 push {r7, lr} 800ec74: b084 sub sp, #16 800ec76: af00 add r7, sp, #0 800ec78: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800ec7a: 687b ldr r3, [r7, #4] 800ec7c: 6a5b ldr r3, [r3, #36] @ 0x24 800ec7e: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 800ec80: 68fb ldr r3, [r7, #12] 800ec82: 6a9b ldr r3, [r3, #40] @ 0x28 800ec84: f043 0240 orr.w r2, r3, #64 @ 0x40 800ec88: 68fb ldr r3, [r7, #12] 800ec8a: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 800ec8c: 68fb ldr r3, [r7, #12] 800ec8e: 6adb ldr r3, [r3, #44] @ 0x2c 800ec90: f043 0204 orr.w r2, r3, #4 800ec94: 68fb ldr r3, [r7, #12] 800ec96: 62da str r2, [r3, #44] @ 0x2c /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 800ec98: 68f8 ldr r0, [r7, #12] 800ec9a: f7ff fe02 bl 800e8a2 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800ec9e: bf00 nop 800eca0: 3710 adds r7, #16 800eca2: 46bd mov sp, r7 800eca4: bd80 pop {r7, pc} ... 0800eca8 : * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { 800eca8: b590 push {r4, r7, lr} 800ecaa: b087 sub sp, #28 800ecac: af00 add r7, sp, #0 800ecae: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800ecb0: 2300 movs r3, #0 800ecb2: 75fb strb r3, [r7, #23] uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; 800ecb4: 2300 movs r3, #0 800ecb6: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800ecb8: 687b ldr r3, [r7, #4] 800ecba: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800ecbe: 2b01 cmp r3, #1 800ecc0: d101 bne.n 800ecc6 800ecc2: 2302 movs r3, #2 800ecc4: e097 b.n 800edf6 800ecc6: 687b ldr r3, [r7, #4] 800ecc8: 2201 movs r2, #1 800ecca: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* 1. Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800ecce: 6878 ldr r0, [r7, #4] 800ecd0: f7ff ff42 bl 800eb58 800ecd4: 4603 mov r3, r0 800ecd6: 75fb strb r3, [r7, #23] /* 2. Calibration prerequisite delay before starting the calibration. */ /* - ADC must be enabled for at least two ADC clock cycles */ tmp_hal_status = ADC_Enable(hadc); 800ecd8: 6878 ldr r0, [r7, #4] 800ecda: f7ff fee3 bl 800eaa4 800ecde: 4603 mov r3, r0 800ece0: 75fb strb r3, [r7, #23] /* Check if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800ece2: 7dfb ldrb r3, [r7, #23] 800ece4: 2b00 cmp r3, #0 800ece6: f040 8081 bne.w 800edec { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800ecea: 687b ldr r3, [r7, #4] 800ecec: 6a9b ldr r3, [r3, #40] @ 0x28 800ecee: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800ecf2: f023 0302 bic.w r3, r3, #2 800ecf6: f043 0202 orr.w r2, r3, #2 800ecfa: 687b ldr r3, [r7, #4] 800ecfc: 629a str r2, [r3, #40] @ 0x28 /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 800ecfe: 4b40 ldr r3, [pc, #256] @ (800ee00 ) 800ed00: 681c ldr r4, [r3, #0] 800ed02: 2002 movs r0, #2 800ed04: f002 fde2 bl 80118cc 800ed08: 4603 mov r3, r0 800ed0a: fbb4 f3f3 udiv r3, r4, r3 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 800ed0e: 005b lsls r3, r3, #1 wait_loop_index = ((SystemCoreClock 800ed10: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800ed12: e002 b.n 800ed1a { wait_loop_index--; 800ed14: 68fb ldr r3, [r7, #12] 800ed16: 3b01 subs r3, #1 800ed18: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800ed1a: 68fb ldr r3, [r7, #12] 800ed1c: 2b00 cmp r3, #0 800ed1e: d1f9 bne.n 800ed14 } /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 800ed20: 687b ldr r3, [r7, #4] 800ed22: 681b ldr r3, [r3, #0] 800ed24: 689a ldr r2, [r3, #8] 800ed26: 687b ldr r3, [r7, #4] 800ed28: 681b ldr r3, [r3, #0] 800ed2a: f042 0208 orr.w r2, r2, #8 800ed2e: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800ed30: f7ff fb02 bl 800e338 800ed34: 6138 str r0, [r7, #16] /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800ed36: e01b b.n 800ed70 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800ed38: f7ff fafe bl 800e338 800ed3c: 4602 mov r2, r0 800ed3e: 693b ldr r3, [r7, #16] 800ed40: 1ad3 subs r3, r2, r3 800ed42: 2b0a cmp r3, #10 800ed44: d914 bls.n 800ed70 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800ed46: 687b ldr r3, [r7, #4] 800ed48: 681b ldr r3, [r3, #0] 800ed4a: 689b ldr r3, [r3, #8] 800ed4c: f003 0308 and.w r3, r3, #8 800ed50: 2b00 cmp r3, #0 800ed52: d00d beq.n 800ed70 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800ed54: 687b ldr r3, [r7, #4] 800ed56: 6a9b ldr r3, [r3, #40] @ 0x28 800ed58: f023 0312 bic.w r3, r3, #18 800ed5c: f043 0210 orr.w r2, r3, #16 800ed60: 687b ldr r3, [r7, #4] 800ed62: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800ed64: 687b ldr r3, [r7, #4] 800ed66: 2200 movs r2, #0 800ed68: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ed6c: 2301 movs r3, #1 800ed6e: e042 b.n 800edf6 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800ed70: 687b ldr r3, [r7, #4] 800ed72: 681b ldr r3, [r3, #0] 800ed74: 689b ldr r3, [r3, #8] 800ed76: f003 0308 and.w r3, r3, #8 800ed7a: 2b00 cmp r3, #0 800ed7c: d1dc bne.n 800ed38 } } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 800ed7e: 687b ldr r3, [r7, #4] 800ed80: 681b ldr r3, [r3, #0] 800ed82: 689a ldr r2, [r3, #8] 800ed84: 687b ldr r3, [r7, #4] 800ed86: 681b ldr r3, [r3, #0] 800ed88: f042 0204 orr.w r2, r2, #4 800ed8c: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800ed8e: f7ff fad3 bl 800e338 800ed92: 6138 str r0, [r7, #16] /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800ed94: e01b b.n 800edce { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800ed96: f7ff facf bl 800e338 800ed9a: 4602 mov r2, r0 800ed9c: 693b ldr r3, [r7, #16] 800ed9e: 1ad3 subs r3, r2, r3 800eda0: 2b0a cmp r3, #10 800eda2: d914 bls.n 800edce { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800eda4: 687b ldr r3, [r7, #4] 800eda6: 681b ldr r3, [r3, #0] 800eda8: 689b ldr r3, [r3, #8] 800edaa: f003 0304 and.w r3, r3, #4 800edae: 2b00 cmp r3, #0 800edb0: d00d beq.n 800edce { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800edb2: 687b ldr r3, [r7, #4] 800edb4: 6a9b ldr r3, [r3, #40] @ 0x28 800edb6: f023 0312 bic.w r3, r3, #18 800edba: f043 0210 orr.w r2, r3, #16 800edbe: 687b ldr r3, [r7, #4] 800edc0: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800edc2: 687b ldr r3, [r7, #4] 800edc4: 2200 movs r2, #0 800edc6: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800edca: 2301 movs r3, #1 800edcc: e013 b.n 800edf6 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800edce: 687b ldr r3, [r7, #4] 800edd0: 681b ldr r3, [r3, #0] 800edd2: 689b ldr r3, [r3, #8] 800edd4: f003 0304 and.w r3, r3, #4 800edd8: 2b00 cmp r3, #0 800edda: d1dc bne.n 800ed96 } } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800eddc: 687b ldr r3, [r7, #4] 800edde: 6a9b ldr r3, [r3, #40] @ 0x28 800ede0: f023 0303 bic.w r3, r3, #3 800ede4: f043 0201 orr.w r2, r3, #1 800ede8: 687b ldr r3, [r7, #4] 800edea: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 800edec: 687b ldr r3, [r7, #4] 800edee: 2200 movs r2, #0 800edf0: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800edf4: 7dfb ldrb r3, [r7, #23] } 800edf6: 4618 mov r0, r3 800edf8: 371c adds r7, #28 800edfa: 46bd mov sp, r7 800edfc: bd90 pop {r4, r7, pc} 800edfe: bf00 nop 800ee00: 20000084 .word 0x20000084 0800ee04 : * @brief Injected conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { 800ee04: b480 push {r7} 800ee06: b083 sub sp, #12 800ee08: af00 add r7, sp, #0 800ee0a: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } 800ee0c: bf00 nop 800ee0e: 370c adds r7, #12 800ee10: 46bd mov sp, r7 800ee12: bc80 pop {r7} 800ee14: 4770 bx lr 0800ee16 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { 800ee16: b580 push {r7, lr} 800ee18: b084 sub sp, #16 800ee1a: af00 add r7, sp, #0 800ee1c: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) 800ee1e: 687b ldr r3, [r7, #4] 800ee20: 2b00 cmp r3, #0 800ee22: d101 bne.n 800ee28 { return HAL_ERROR; 800ee24: 2301 movs r3, #1 800ee26: e0ed b.n 800f004 /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) 800ee28: 687b ldr r3, [r7, #4] 800ee2a: f893 3020 ldrb.w r3, [r3, #32] 800ee2e: b2db uxtb r3, r3 800ee30: 2b00 cmp r3, #0 800ee32: d102 bne.n 800ee3a { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); 800ee34: 6878 ldr r0, [r7, #4] 800ee36: f7fa ff1f bl 8009c78 } #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800ee3a: 687b ldr r3, [r7, #4] 800ee3c: 681b ldr r3, [r3, #0] 800ee3e: 681a ldr r2, [r3, #0] 800ee40: 687b ldr r3, [r7, #4] 800ee42: 681b ldr r3, [r3, #0] 800ee44: f042 0201 orr.w r2, r2, #1 800ee48: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800ee4a: f7ff fa75 bl 800e338 800ee4e: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800ee50: e012 b.n 800ee78 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800ee52: f7ff fa71 bl 800e338 800ee56: 4602 mov r2, r0 800ee58: 68fb ldr r3, [r7, #12] 800ee5a: 1ad3 subs r3, r2, r3 800ee5c: 2b0a cmp r3, #10 800ee5e: d90b bls.n 800ee78 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800ee60: 687b ldr r3, [r7, #4] 800ee62: 6a5b ldr r3, [r3, #36] @ 0x24 800ee64: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800ee68: 687b ldr r3, [r7, #4] 800ee6a: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800ee6c: 687b ldr r3, [r7, #4] 800ee6e: 2205 movs r2, #5 800ee70: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800ee74: 2301 movs r3, #1 800ee76: e0c5 b.n 800f004 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800ee78: 687b ldr r3, [r7, #4] 800ee7a: 681b ldr r3, [r3, #0] 800ee7c: 685b ldr r3, [r3, #4] 800ee7e: f003 0301 and.w r3, r3, #1 800ee82: 2b00 cmp r3, #0 800ee84: d0e5 beq.n 800ee52 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800ee86: 687b ldr r3, [r7, #4] 800ee88: 681b ldr r3, [r3, #0] 800ee8a: 681a ldr r2, [r3, #0] 800ee8c: 687b ldr r3, [r7, #4] 800ee8e: 681b ldr r3, [r3, #0] 800ee90: f022 0202 bic.w r2, r2, #2 800ee94: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800ee96: f7ff fa4f bl 800e338 800ee9a: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800ee9c: e012 b.n 800eec4 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800ee9e: f7ff fa4b bl 800e338 800eea2: 4602 mov r2, r0 800eea4: 68fb ldr r3, [r7, #12] 800eea6: 1ad3 subs r3, r2, r3 800eea8: 2b0a cmp r3, #10 800eeaa: d90b bls.n 800eec4 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800eeac: 687b ldr r3, [r7, #4] 800eeae: 6a5b ldr r3, [r3, #36] @ 0x24 800eeb0: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800eeb4: 687b ldr r3, [r7, #4] 800eeb6: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800eeb8: 687b ldr r3, [r7, #4] 800eeba: 2205 movs r2, #5 800eebc: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800eec0: 2301 movs r3, #1 800eec2: e09f b.n 800f004 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800eec4: 687b ldr r3, [r7, #4] 800eec6: 681b ldr r3, [r3, #0] 800eec8: 685b ldr r3, [r3, #4] 800eeca: f003 0302 and.w r3, r3, #2 800eece: 2b00 cmp r3, #0 800eed0: d1e5 bne.n 800ee9e } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) 800eed2: 687b ldr r3, [r7, #4] 800eed4: 7e1b ldrb r3, [r3, #24] 800eed6: 2b01 cmp r3, #1 800eed8: d108 bne.n 800eeec { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800eeda: 687b ldr r3, [r7, #4] 800eedc: 681b ldr r3, [r3, #0] 800eede: 681a ldr r2, [r3, #0] 800eee0: 687b ldr r3, [r7, #4] 800eee2: 681b ldr r3, [r3, #0] 800eee4: f042 0280 orr.w r2, r2, #128 @ 0x80 800eee8: 601a str r2, [r3, #0] 800eeea: e007 b.n 800eefc } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800eeec: 687b ldr r3, [r7, #4] 800eeee: 681b ldr r3, [r3, #0] 800eef0: 681a ldr r2, [r3, #0] 800eef2: 687b ldr r3, [r7, #4] 800eef4: 681b ldr r3, [r3, #0] 800eef6: f022 0280 bic.w r2, r2, #128 @ 0x80 800eefa: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) 800eefc: 687b ldr r3, [r7, #4] 800eefe: 7e5b ldrb r3, [r3, #25] 800ef00: 2b01 cmp r3, #1 800ef02: d108 bne.n 800ef16 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800ef04: 687b ldr r3, [r7, #4] 800ef06: 681b ldr r3, [r3, #0] 800ef08: 681a ldr r2, [r3, #0] 800ef0a: 687b ldr r3, [r7, #4] 800ef0c: 681b ldr r3, [r3, #0] 800ef0e: f042 0240 orr.w r2, r2, #64 @ 0x40 800ef12: 601a str r2, [r3, #0] 800ef14: e007 b.n 800ef26 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800ef16: 687b ldr r3, [r7, #4] 800ef18: 681b ldr r3, [r3, #0] 800ef1a: 681a ldr r2, [r3, #0] 800ef1c: 687b ldr r3, [r7, #4] 800ef1e: 681b ldr r3, [r3, #0] 800ef20: f022 0240 bic.w r2, r2, #64 @ 0x40 800ef24: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) 800ef26: 687b ldr r3, [r7, #4] 800ef28: 7e9b ldrb r3, [r3, #26] 800ef2a: 2b01 cmp r3, #1 800ef2c: d108 bne.n 800ef40 { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800ef2e: 687b ldr r3, [r7, #4] 800ef30: 681b ldr r3, [r3, #0] 800ef32: 681a ldr r2, [r3, #0] 800ef34: 687b ldr r3, [r7, #4] 800ef36: 681b ldr r3, [r3, #0] 800ef38: f042 0220 orr.w r2, r2, #32 800ef3c: 601a str r2, [r3, #0] 800ef3e: e007 b.n 800ef50 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800ef40: 687b ldr r3, [r7, #4] 800ef42: 681b ldr r3, [r3, #0] 800ef44: 681a ldr r2, [r3, #0] 800ef46: 687b ldr r3, [r7, #4] 800ef48: 681b ldr r3, [r3, #0] 800ef4a: f022 0220 bic.w r2, r2, #32 800ef4e: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) 800ef50: 687b ldr r3, [r7, #4] 800ef52: 7edb ldrb r3, [r3, #27] 800ef54: 2b01 cmp r3, #1 800ef56: d108 bne.n 800ef6a { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800ef58: 687b ldr r3, [r7, #4] 800ef5a: 681b ldr r3, [r3, #0] 800ef5c: 681a ldr r2, [r3, #0] 800ef5e: 687b ldr r3, [r7, #4] 800ef60: 681b ldr r3, [r3, #0] 800ef62: f022 0210 bic.w r2, r2, #16 800ef66: 601a str r2, [r3, #0] 800ef68: e007 b.n 800ef7a } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800ef6a: 687b ldr r3, [r7, #4] 800ef6c: 681b ldr r3, [r3, #0] 800ef6e: 681a ldr r2, [r3, #0] 800ef70: 687b ldr r3, [r7, #4] 800ef72: 681b ldr r3, [r3, #0] 800ef74: f042 0210 orr.w r2, r2, #16 800ef78: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) 800ef7a: 687b ldr r3, [r7, #4] 800ef7c: 7f1b ldrb r3, [r3, #28] 800ef7e: 2b01 cmp r3, #1 800ef80: d108 bne.n 800ef94 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800ef82: 687b ldr r3, [r7, #4] 800ef84: 681b ldr r3, [r3, #0] 800ef86: 681a ldr r2, [r3, #0] 800ef88: 687b ldr r3, [r7, #4] 800ef8a: 681b ldr r3, [r3, #0] 800ef8c: f042 0208 orr.w r2, r2, #8 800ef90: 601a str r2, [r3, #0] 800ef92: e007 b.n 800efa4 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800ef94: 687b ldr r3, [r7, #4] 800ef96: 681b ldr r3, [r3, #0] 800ef98: 681a ldr r2, [r3, #0] 800ef9a: 687b ldr r3, [r7, #4] 800ef9c: 681b ldr r3, [r3, #0] 800ef9e: f022 0208 bic.w r2, r2, #8 800efa2: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) 800efa4: 687b ldr r3, [r7, #4] 800efa6: 7f5b ldrb r3, [r3, #29] 800efa8: 2b01 cmp r3, #1 800efaa: d108 bne.n 800efbe { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800efac: 687b ldr r3, [r7, #4] 800efae: 681b ldr r3, [r3, #0] 800efb0: 681a ldr r2, [r3, #0] 800efb2: 687b ldr r3, [r7, #4] 800efb4: 681b ldr r3, [r3, #0] 800efb6: f042 0204 orr.w r2, r2, #4 800efba: 601a str r2, [r3, #0] 800efbc: e007 b.n 800efce } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800efbe: 687b ldr r3, [r7, #4] 800efc0: 681b ldr r3, [r3, #0] 800efc2: 681a ldr r2, [r3, #0] 800efc4: 687b ldr r3, [r7, #4] 800efc6: 681b ldr r3, [r3, #0] 800efc8: f022 0204 bic.w r2, r2, #4 800efcc: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | 800efce: 687b ldr r3, [r7, #4] 800efd0: 689a ldr r2, [r3, #8] 800efd2: 687b ldr r3, [r7, #4] 800efd4: 68db ldr r3, [r3, #12] 800efd6: 431a orrs r2, r3 800efd8: 687b ldr r3, [r7, #4] 800efda: 691b ldr r3, [r3, #16] 800efdc: 431a orrs r2, r3 800efde: 687b ldr r3, [r7, #4] 800efe0: 695b ldr r3, [r3, #20] 800efe2: ea42 0103 orr.w r1, r2, r3 800efe6: 687b ldr r3, [r7, #4] 800efe8: 685b ldr r3, [r3, #4] 800efea: 1e5a subs r2, r3, #1 800efec: 687b ldr r3, [r7, #4] 800efee: 681b ldr r3, [r3, #0] 800eff0: 430a orrs r2, r1 800eff2: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800eff4: 687b ldr r3, [r7, #4] 800eff6: 2200 movs r2, #0 800eff8: 625a str r2, [r3, #36] @ 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; 800effa: 687b ldr r3, [r7, #4] 800effc: 2201 movs r2, #1 800effe: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800f002: 2300 movs r3, #0 } 800f004: 4618 mov r0, r3 800f006: 3710 adds r7, #16 800f008: 46bd mov sp, r7 800f00a: bd80 pop {r7, pc} 0800f00c : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { 800f00c: b480 push {r7} 800f00e: b087 sub sp, #28 800f010: af00 add r7, sp, #0 800f012: 6078 str r0, [r7, #4] 800f014: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; 800f016: 687b ldr r3, [r7, #4] 800f018: 681b ldr r3, [r3, #0] 800f01a: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; 800f01c: 687b ldr r3, [r7, #4] 800f01e: f893 3020 ldrb.w r3, [r3, #32] 800f022: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || 800f024: 7cfb ldrb r3, [r7, #19] 800f026: 2b01 cmp r3, #1 800f028: d003 beq.n 800f032 800f02a: 7cfb ldrb r3, [r7, #19] 800f02c: 2b02 cmp r3, #2 800f02e: f040 80be bne.w 800f1ae assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); #if defined(CAN2) /* CAN1 and CAN2 are dual instances with 28 common filters banks */ /* Select master instance to access the filter banks */ can_ip = CAN1; 800f032: 4b65 ldr r3, [pc, #404] @ (800f1c8 ) 800f034: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); #endif /* CAN3 */ /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); 800f036: 697b ldr r3, [r7, #20] 800f038: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800f03c: f043 0201 orr.w r2, r3, #1 800f040: 697b ldr r3, [r7, #20] 800f042: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #if defined(CAN2) /* Select the start filter number of CAN2 slave instance */ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); 800f046: 697b ldr r3, [r7, #20] 800f048: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800f04c: f423 527c bic.w r2, r3, #16128 @ 0x3f00 800f050: 697b ldr r3, [r7, #20] 800f052: f8c3 2200 str.w r2, [r3, #512] @ 0x200 SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); 800f056: 697b ldr r3, [r7, #20] 800f058: f8d3 2200 ldr.w r2, [r3, #512] @ 0x200 800f05c: 683b ldr r3, [r7, #0] 800f05e: 6a5b ldr r3, [r3, #36] @ 0x24 800f060: 021b lsls r3, r3, #8 800f062: 431a orrs r2, r3 800f064: 697b ldr r3, [r7, #20] 800f066: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #endif /* CAN3 */ /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); 800f06a: 683b ldr r3, [r7, #0] 800f06c: 695b ldr r3, [r3, #20] 800f06e: f003 031f and.w r3, r3, #31 800f072: 2201 movs r2, #1 800f074: fa02 f303 lsl.w r3, r2, r3 800f078: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); 800f07a: 697b ldr r3, [r7, #20] 800f07c: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800f080: 68fb ldr r3, [r7, #12] 800f082: 43db mvns r3, r3 800f084: 401a ands r2, r3 800f086: 697b ldr r3, [r7, #20] 800f088: f8c3 221c str.w r2, [r3, #540] @ 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) 800f08c: 683b ldr r3, [r7, #0] 800f08e: 69db ldr r3, [r3, #28] 800f090: 2b00 cmp r3, #0 800f092: d123 bne.n 800f0dc { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); 800f094: 697b ldr r3, [r7, #20] 800f096: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800f09a: 68fb ldr r3, [r7, #12] 800f09c: 43db mvns r3, r3 800f09e: 401a ands r2, r3 800f0a0: 697b ldr r3, [r7, #20] 800f0a2: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800f0a6: 683b ldr r3, [r7, #0] 800f0a8: 68db ldr r3, [r3, #12] 800f0aa: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800f0ac: 683b ldr r3, [r7, #0] 800f0ae: 685b ldr r3, [r3, #4] 800f0b0: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800f0b2: 683a ldr r2, [r7, #0] 800f0b4: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800f0b6: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800f0b8: 697b ldr r3, [r7, #20] 800f0ba: 3248 adds r2, #72 @ 0x48 800f0bc: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800f0c0: 683b ldr r3, [r7, #0] 800f0c2: 689b ldr r3, [r3, #8] 800f0c4: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); 800f0c6: 683b ldr r3, [r7, #0] 800f0c8: 681b ldr r3, [r3, #0] 800f0ca: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800f0cc: 683b ldr r3, [r7, #0] 800f0ce: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800f0d0: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800f0d2: 6979 ldr r1, [r7, #20] 800f0d4: 3348 adds r3, #72 @ 0x48 800f0d6: 00db lsls r3, r3, #3 800f0d8: 440b add r3, r1 800f0da: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) 800f0dc: 683b ldr r3, [r7, #0] 800f0de: 69db ldr r3, [r3, #28] 800f0e0: 2b01 cmp r3, #1 800f0e2: d122 bne.n 800f12a { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); 800f0e4: 697b ldr r3, [r7, #20] 800f0e6: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800f0ea: 68fb ldr r3, [r7, #12] 800f0ec: 431a orrs r2, r3 800f0ee: 697b ldr r3, [r7, #20] 800f0f0: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800f0f4: 683b ldr r3, [r7, #0] 800f0f6: 681b ldr r3, [r3, #0] 800f0f8: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800f0fa: 683b ldr r3, [r7, #0] 800f0fc: 685b ldr r3, [r3, #4] 800f0fe: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800f100: 683a ldr r2, [r7, #0] 800f102: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800f104: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800f106: 697b ldr r3, [r7, #20] 800f108: 3248 adds r2, #72 @ 0x48 800f10a: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800f10e: 683b ldr r3, [r7, #0] 800f110: 689b ldr r3, [r3, #8] 800f112: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); 800f114: 683b ldr r3, [r7, #0] 800f116: 68db ldr r3, [r3, #12] 800f118: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800f11a: 683b ldr r3, [r7, #0] 800f11c: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800f11e: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800f120: 6979 ldr r1, [r7, #20] 800f122: 3348 adds r3, #72 @ 0x48 800f124: 00db lsls r3, r3, #3 800f126: 440b add r3, r1 800f128: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) 800f12a: 683b ldr r3, [r7, #0] 800f12c: 699b ldr r3, [r3, #24] 800f12e: 2b00 cmp r3, #0 800f130: d109 bne.n 800f146 { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); 800f132: 697b ldr r3, [r7, #20] 800f134: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800f138: 68fb ldr r3, [r7, #12] 800f13a: 43db mvns r3, r3 800f13c: 401a ands r2, r3 800f13e: 697b ldr r3, [r7, #20] 800f140: f8c3 2204 str.w r2, [r3, #516] @ 0x204 800f144: e007 b.n 800f156 } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); 800f146: 697b ldr r3, [r7, #20] 800f148: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800f14c: 68fb ldr r3, [r7, #12] 800f14e: 431a orrs r2, r3 800f150: 697b ldr r3, [r7, #20] 800f152: f8c3 2204 str.w r2, [r3, #516] @ 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) 800f156: 683b ldr r3, [r7, #0] 800f158: 691b ldr r3, [r3, #16] 800f15a: 2b00 cmp r3, #0 800f15c: d109 bne.n 800f172 { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); 800f15e: 697b ldr r3, [r7, #20] 800f160: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800f164: 68fb ldr r3, [r7, #12] 800f166: 43db mvns r3, r3 800f168: 401a ands r2, r3 800f16a: 697b ldr r3, [r7, #20] 800f16c: f8c3 2214 str.w r2, [r3, #532] @ 0x214 800f170: e007 b.n 800f182 } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); 800f172: 697b ldr r3, [r7, #20] 800f174: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800f178: 68fb ldr r3, [r7, #12] 800f17a: 431a orrs r2, r3 800f17c: 697b ldr r3, [r7, #20] 800f17e: f8c3 2214 str.w r2, [r3, #532] @ 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) 800f182: 683b ldr r3, [r7, #0] 800f184: 6a1b ldr r3, [r3, #32] 800f186: 2b01 cmp r3, #1 800f188: d107 bne.n 800f19a { SET_BIT(can_ip->FA1R, filternbrbitpos); 800f18a: 697b ldr r3, [r7, #20] 800f18c: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800f190: 68fb ldr r3, [r7, #12] 800f192: 431a orrs r2, r3 800f194: 697b ldr r3, [r7, #20] 800f196: f8c3 221c str.w r2, [r3, #540] @ 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); 800f19a: 697b ldr r3, [r7, #20] 800f19c: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800f1a0: f023 0201 bic.w r2, r3, #1 800f1a4: 697b ldr r3, [r7, #20] 800f1a6: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Return function status */ return HAL_OK; 800f1aa: 2300 movs r3, #0 800f1ac: e006 b.n 800f1bc } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f1ae: 687b ldr r3, [r7, #4] 800f1b0: 6a5b ldr r3, [r3, #36] @ 0x24 800f1b2: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f1b6: 687b ldr r3, [r7, #4] 800f1b8: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f1ba: 2301 movs r3, #1 } } 800f1bc: 4618 mov r0, r3 800f1be: 371c adds r7, #28 800f1c0: 46bd mov sp, r7 800f1c2: bc80 pop {r7} 800f1c4: 4770 bx lr 800f1c6: bf00 nop 800f1c8: 40006400 .word 0x40006400 0800f1cc : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { 800f1cc: b580 push {r7, lr} 800f1ce: b084 sub sp, #16 800f1d0: af00 add r7, sp, #0 800f1d2: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) 800f1d4: 687b ldr r3, [r7, #4] 800f1d6: f893 3020 ldrb.w r3, [r3, #32] 800f1da: b2db uxtb r3, r3 800f1dc: 2b01 cmp r3, #1 800f1de: d12e bne.n 800f23e { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; 800f1e0: 687b ldr r3, [r7, #4] 800f1e2: 2202 movs r2, #2 800f1e4: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800f1e8: 687b ldr r3, [r7, #4] 800f1ea: 681b ldr r3, [r3, #0] 800f1ec: 681a ldr r2, [r3, #0] 800f1ee: 687b ldr r3, [r7, #4] 800f1f0: 681b ldr r3, [r3, #0] 800f1f2: f022 0201 bic.w r2, r2, #1 800f1f6: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800f1f8: f7ff f89e bl 800e338 800f1fc: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800f1fe: e012 b.n 800f226 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800f200: f7ff f89a bl 800e338 800f204: 4602 mov r2, r0 800f206: 68fb ldr r3, [r7, #12] 800f208: 1ad3 subs r3, r2, r3 800f20a: 2b0a cmp r3, #10 800f20c: d90b bls.n 800f226 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800f20e: 687b ldr r3, [r7, #4] 800f210: 6a5b ldr r3, [r3, #36] @ 0x24 800f212: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800f216: 687b ldr r3, [r7, #4] 800f218: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800f21a: 687b ldr r3, [r7, #4] 800f21c: 2205 movs r2, #5 800f21e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800f222: 2301 movs r3, #1 800f224: e012 b.n 800f24c while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800f226: 687b ldr r3, [r7, #4] 800f228: 681b ldr r3, [r3, #0] 800f22a: 685b ldr r3, [r3, #4] 800f22c: f003 0301 and.w r3, r3, #1 800f230: 2b00 cmp r3, #0 800f232: d1e5 bne.n 800f200 } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800f234: 687b ldr r3, [r7, #4] 800f236: 2200 movs r2, #0 800f238: 625a str r2, [r3, #36] @ 0x24 /* Return function status */ return HAL_OK; 800f23a: 2300 movs r3, #0 800f23c: e006 b.n 800f24c } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; 800f23e: 687b ldr r3, [r7, #4] 800f240: 6a5b ldr r3, [r3, #36] @ 0x24 800f242: f443 2200 orr.w r2, r3, #524288 @ 0x80000 800f246: 687b ldr r3, [r7, #4] 800f248: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f24a: 2301 movs r3, #1 } } 800f24c: 4618 mov r0, r3 800f24e: 3710 adds r7, #16 800f250: 46bd mov sp, r7 800f252: bd80 pop {r7, pc} 0800f254 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { 800f254: b580 push {r7, lr} 800f256: b084 sub sp, #16 800f258: af00 add r7, sp, #0 800f25a: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_LISTENING) 800f25c: 687b ldr r3, [r7, #4] 800f25e: f893 3020 ldrb.w r3, [r3, #32] 800f262: b2db uxtb r3, r3 800f264: 2b02 cmp r3, #2 800f266: d133 bne.n 800f2d0 { /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800f268: 687b ldr r3, [r7, #4] 800f26a: 681b ldr r3, [r3, #0] 800f26c: 681a ldr r2, [r3, #0] 800f26e: 687b ldr r3, [r7, #4] 800f270: 681b ldr r3, [r3, #0] 800f272: f042 0201 orr.w r2, r2, #1 800f276: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800f278: f7ff f85e bl 800e338 800f27c: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800f27e: e012 b.n 800f2a6 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800f280: f7ff f85a bl 800e338 800f284: 4602 mov r2, r0 800f286: 68fb ldr r3, [r7, #12] 800f288: 1ad3 subs r3, r2, r3 800f28a: 2b0a cmp r3, #10 800f28c: d90b bls.n 800f2a6 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800f28e: 687b ldr r3, [r7, #4] 800f290: 6a5b ldr r3, [r3, #36] @ 0x24 800f292: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800f296: 687b ldr r3, [r7, #4] 800f298: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800f29a: 687b ldr r3, [r7, #4] 800f29c: 2205 movs r2, #5 800f29e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800f2a2: 2301 movs r3, #1 800f2a4: e01b b.n 800f2de while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800f2a6: 687b ldr r3, [r7, #4] 800f2a8: 681b ldr r3, [r3, #0] 800f2aa: 685b ldr r3, [r3, #4] 800f2ac: f003 0301 and.w r3, r3, #1 800f2b0: 2b00 cmp r3, #0 800f2b2: d0e5 beq.n 800f280 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800f2b4: 687b ldr r3, [r7, #4] 800f2b6: 681b ldr r3, [r3, #0] 800f2b8: 681a ldr r2, [r3, #0] 800f2ba: 687b ldr r3, [r7, #4] 800f2bc: 681b ldr r3, [r3, #0] 800f2be: f022 0202 bic.w r2, r2, #2 800f2c2: 601a str r2, [r3, #0] /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_READY; 800f2c4: 687b ldr r3, [r7, #4] 800f2c6: 2201 movs r2, #1 800f2c8: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800f2cc: 2300 movs r3, #0 800f2ce: e006 b.n 800f2de } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; 800f2d0: 687b ldr r3, [r7, #4] 800f2d2: 6a5b ldr r3, [r3, #36] @ 0x24 800f2d4: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800f2d8: 687b ldr r3, [r7, #4] 800f2da: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f2dc: 2301 movs r3, #1 } } 800f2de: 4618 mov r0, r3 800f2e0: 3710 adds r7, #16 800f2e2: 46bd mov sp, r7 800f2e4: bd80 pop {r7, pc} 0800f2e6 : * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, const uint8_t aData[], uint32_t *pTxMailbox) { 800f2e6: b480 push {r7} 800f2e8: b089 sub sp, #36 @ 0x24 800f2ea: af00 add r7, sp, #0 800f2ec: 60f8 str r0, [r7, #12] 800f2ee: 60b9 str r1, [r7, #8] 800f2f0: 607a str r2, [r7, #4] 800f2f2: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; 800f2f4: 68fb ldr r3, [r7, #12] 800f2f6: f893 3020 ldrb.w r3, [r3, #32] 800f2fa: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); 800f2fc: 68fb ldr r3, [r7, #12] 800f2fe: 681b ldr r3, [r3, #0] 800f300: 689b ldr r3, [r3, #8] 800f302: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || 800f304: 7ffb ldrb r3, [r7, #31] 800f306: 2b01 cmp r3, #1 800f308: d003 beq.n 800f312 800f30a: 7ffb ldrb r3, [r7, #31] 800f30c: 2b02 cmp r3, #2 800f30e: f040 80ad bne.w 800f46c (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || 800f312: 69bb ldr r3, [r7, #24] 800f314: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800f318: 2b00 cmp r3, #0 800f31a: d10a bne.n 800f332 ((tsr & CAN_TSR_TME1) != 0U) || 800f31c: 69bb ldr r3, [r7, #24] 800f31e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || 800f322: 2b00 cmp r3, #0 800f324: d105 bne.n 800f332 ((tsr & CAN_TSR_TME2) != 0U)) 800f326: 69bb ldr r3, [r7, #24] 800f328: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || 800f32c: 2b00 cmp r3, #0 800f32e: f000 8095 beq.w 800f45c { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; 800f332: 69bb ldr r3, [r7, #24] 800f334: 0e1b lsrs r3, r3, #24 800f336: f003 0303 and.w r3, r3, #3 800f33a: 617b str r3, [r7, #20] /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; 800f33c: 2201 movs r2, #1 800f33e: 697b ldr r3, [r7, #20] 800f340: 409a lsls r2, r3 800f342: 683b ldr r3, [r7, #0] 800f344: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) 800f346: 68bb ldr r3, [r7, #8] 800f348: 689b ldr r3, [r3, #8] 800f34a: 2b00 cmp r3, #0 800f34c: d10d bne.n 800f36a { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800f34e: 68bb ldr r3, [r7, #8] 800f350: 681b ldr r3, [r3, #0] 800f352: 055a lsls r2, r3, #21 pHeader->RTR); 800f354: 68bb ldr r3, [r7, #8] 800f356: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800f358: 68f9 ldr r1, [r7, #12] 800f35a: 6809 ldr r1, [r1, #0] 800f35c: 431a orrs r2, r3 800f35e: 697b ldr r3, [r7, #20] 800f360: 3318 adds r3, #24 800f362: 011b lsls r3, r3, #4 800f364: 440b add r3, r1 800f366: 601a str r2, [r3, #0] 800f368: e00f b.n 800f38a } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f36a: 68bb ldr r3, [r7, #8] 800f36c: 685b ldr r3, [r3, #4] 800f36e: 00da lsls r2, r3, #3 pHeader->IDE | 800f370: 68bb ldr r3, [r7, #8] 800f372: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f374: 431a orrs r2, r3 pHeader->RTR); 800f376: 68bb ldr r3, [r7, #8] 800f378: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f37a: 68f9 ldr r1, [r7, #12] 800f37c: 6809 ldr r1, [r1, #0] pHeader->IDE | 800f37e: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f380: 697b ldr r3, [r7, #20] 800f382: 3318 adds r3, #24 800f384: 011b lsls r3, r3, #4 800f386: 440b add r3, r1 800f388: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); 800f38a: 68fb ldr r3, [r7, #12] 800f38c: 6819 ldr r1, [r3, #0] 800f38e: 68bb ldr r3, [r7, #8] 800f390: 691a ldr r2, [r3, #16] 800f392: 697b ldr r3, [r7, #20] 800f394: 3318 adds r3, #24 800f396: 011b lsls r3, r3, #4 800f398: 440b add r3, r1 800f39a: 3304 adds r3, #4 800f39c: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) 800f39e: 68bb ldr r3, [r7, #8] 800f3a0: 7d1b ldrb r3, [r3, #20] 800f3a2: 2b01 cmp r3, #1 800f3a4: d111 bne.n 800f3ca { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); 800f3a6: 68fb ldr r3, [r7, #12] 800f3a8: 681a ldr r2, [r3, #0] 800f3aa: 697b ldr r3, [r7, #20] 800f3ac: 3318 adds r3, #24 800f3ae: 011b lsls r3, r3, #4 800f3b0: 4413 add r3, r2 800f3b2: 3304 adds r3, #4 800f3b4: 681b ldr r3, [r3, #0] 800f3b6: 68fa ldr r2, [r7, #12] 800f3b8: 6811 ldr r1, [r2, #0] 800f3ba: f443 7280 orr.w r2, r3, #256 @ 0x100 800f3be: 697b ldr r3, [r7, #20] 800f3c0: 3318 adds r3, #24 800f3c2: 011b lsls r3, r3, #4 800f3c4: 440b add r3, r1 800f3c6: 3304 adds r3, #4 800f3c8: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, 800f3ca: 687b ldr r3, [r7, #4] 800f3cc: 3307 adds r3, #7 800f3ce: 781b ldrb r3, [r3, #0] 800f3d0: 061a lsls r2, r3, #24 800f3d2: 687b ldr r3, [r7, #4] 800f3d4: 3306 adds r3, #6 800f3d6: 781b ldrb r3, [r3, #0] 800f3d8: 041b lsls r3, r3, #16 800f3da: 431a orrs r2, r3 800f3dc: 687b ldr r3, [r7, #4] 800f3de: 3305 adds r3, #5 800f3e0: 781b ldrb r3, [r3, #0] 800f3e2: 021b lsls r3, r3, #8 800f3e4: 4313 orrs r3, r2 800f3e6: 687a ldr r2, [r7, #4] 800f3e8: 3204 adds r2, #4 800f3ea: 7812 ldrb r2, [r2, #0] 800f3ec: 4610 mov r0, r2 800f3ee: 68fa ldr r2, [r7, #12] 800f3f0: 6811 ldr r1, [r2, #0] 800f3f2: ea43 0200 orr.w r2, r3, r0 800f3f6: 697b ldr r3, [r7, #20] 800f3f8: 011b lsls r3, r3, #4 800f3fa: 440b add r3, r1 800f3fc: f503 73c6 add.w r3, r3, #396 @ 0x18c 800f400: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, 800f402: 687b ldr r3, [r7, #4] 800f404: 3303 adds r3, #3 800f406: 781b ldrb r3, [r3, #0] 800f408: 061a lsls r2, r3, #24 800f40a: 687b ldr r3, [r7, #4] 800f40c: 3302 adds r3, #2 800f40e: 781b ldrb r3, [r3, #0] 800f410: 041b lsls r3, r3, #16 800f412: 431a orrs r2, r3 800f414: 687b ldr r3, [r7, #4] 800f416: 3301 adds r3, #1 800f418: 781b ldrb r3, [r3, #0] 800f41a: 021b lsls r3, r3, #8 800f41c: 4313 orrs r3, r2 800f41e: 687a ldr r2, [r7, #4] 800f420: 7812 ldrb r2, [r2, #0] 800f422: 4610 mov r0, r2 800f424: 68fa ldr r2, [r7, #12] 800f426: 6811 ldr r1, [r2, #0] 800f428: ea43 0200 orr.w r2, r3, r0 800f42c: 697b ldr r3, [r7, #20] 800f42e: 011b lsls r3, r3, #4 800f430: 440b add r3, r1 800f432: f503 73c4 add.w r3, r3, #392 @ 0x188 800f436: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); 800f438: 68fb ldr r3, [r7, #12] 800f43a: 681a ldr r2, [r3, #0] 800f43c: 697b ldr r3, [r7, #20] 800f43e: 3318 adds r3, #24 800f440: 011b lsls r3, r3, #4 800f442: 4413 add r3, r2 800f444: 681b ldr r3, [r3, #0] 800f446: 68fa ldr r2, [r7, #12] 800f448: 6811 ldr r1, [r2, #0] 800f44a: f043 0201 orr.w r2, r3, #1 800f44e: 697b ldr r3, [r7, #20] 800f450: 3318 adds r3, #24 800f452: 011b lsls r3, r3, #4 800f454: 440b add r3, r1 800f456: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800f458: 2300 movs r3, #0 800f45a: e00e b.n 800f47a } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800f45c: 68fb ldr r3, [r7, #12] 800f45e: 6a5b ldr r3, [r3, #36] @ 0x24 800f460: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800f464: 68fb ldr r3, [r7, #12] 800f466: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f468: 2301 movs r3, #1 800f46a: e006 b.n 800f47a } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f46c: 68fb ldr r3, [r7, #12] 800f46e: 6a5b ldr r3, [r3, #36] @ 0x24 800f470: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f474: 68fb ldr r3, [r7, #12] 800f476: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f478: 2301 movs r3, #1 } } 800f47a: 4618 mov r0, r3 800f47c: 3724 adds r7, #36 @ 0x24 800f47e: 46bd mov sp, r7 800f480: bc80 pop {r7} 800f482: 4770 bx lr 0800f484 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval Number of free Tx Mailboxes. */ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) { 800f484: b480 push {r7} 800f486: b085 sub sp, #20 800f488: af00 add r7, sp, #0 800f48a: 6078 str r0, [r7, #4] uint32_t freelevel = 0U; 800f48c: 2300 movs r3, #0 800f48e: 60fb str r3, [r7, #12] HAL_CAN_StateTypeDef state = hcan->State; 800f490: 687b ldr r3, [r7, #4] 800f492: f893 3020 ldrb.w r3, [r3, #32] 800f496: 72fb strb r3, [r7, #11] if ((state == HAL_CAN_STATE_READY) || 800f498: 7afb ldrb r3, [r7, #11] 800f49a: 2b01 cmp r3, #1 800f49c: d002 beq.n 800f4a4 800f49e: 7afb ldrb r3, [r7, #11] 800f4a0: 2b02 cmp r3, #2 800f4a2: d11d bne.n 800f4e0 (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 status */ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) 800f4a4: 687b ldr r3, [r7, #4] 800f4a6: 681b ldr r3, [r3, #0] 800f4a8: 689b ldr r3, [r3, #8] 800f4aa: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800f4ae: 2b00 cmp r3, #0 800f4b0: d002 beq.n 800f4b8 { freelevel++; 800f4b2: 68fb ldr r3, [r7, #12] 800f4b4: 3301 adds r3, #1 800f4b6: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 1 status */ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) 800f4b8: 687b ldr r3, [r7, #4] 800f4ba: 681b ldr r3, [r3, #0] 800f4bc: 689b ldr r3, [r3, #8] 800f4be: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800f4c2: 2b00 cmp r3, #0 800f4c4: d002 beq.n 800f4cc { freelevel++; 800f4c6: 68fb ldr r3, [r7, #12] 800f4c8: 3301 adds r3, #1 800f4ca: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 2 status */ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) 800f4cc: 687b ldr r3, [r7, #4] 800f4ce: 681b ldr r3, [r3, #0] 800f4d0: 689b ldr r3, [r3, #8] 800f4d2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800f4d6: 2b00 cmp r3, #0 800f4d8: d002 beq.n 800f4e0 { freelevel++; 800f4da: 68fb ldr r3, [r7, #12] 800f4dc: 3301 adds r3, #1 800f4de: 60fb str r3, [r7, #12] } } /* Return Tx Mailboxes free level */ return freelevel; 800f4e0: 68fb ldr r3, [r7, #12] } 800f4e2: 4618 mov r0, r3 800f4e4: 3714 adds r7, #20 800f4e6: 46bd mov sp, r7 800f4e8: bc80 pop {r7} 800f4ea: 4770 bx lr 0800f4ec : * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { 800f4ec: b480 push {r7} 800f4ee: b087 sub sp, #28 800f4f0: af00 add r7, sp, #0 800f4f2: 60f8 str r0, [r7, #12] 800f4f4: 60b9 str r1, [r7, #8] 800f4f6: 607a str r2, [r7, #4] 800f4f8: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800f4fa: 68fb ldr r3, [r7, #12] 800f4fc: f893 3020 ldrb.w r3, [r3, #32] 800f500: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || 800f502: 7dfb ldrb r3, [r7, #23] 800f504: 2b01 cmp r3, #1 800f506: d003 beq.n 800f510 800f508: 7dfb ldrb r3, [r7, #23] 800f50a: 2b02 cmp r3, #2 800f50c: f040 8103 bne.w 800f716 (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800f510: 68bb ldr r3, [r7, #8] 800f512: 2b00 cmp r3, #0 800f514: d10e bne.n 800f534 { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) 800f516: 68fb ldr r3, [r7, #12] 800f518: 681b ldr r3, [r3, #0] 800f51a: 68db ldr r3, [r3, #12] 800f51c: f003 0303 and.w r3, r3, #3 800f520: 2b00 cmp r3, #0 800f522: d116 bne.n 800f552 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800f524: 68fb ldr r3, [r7, #12] 800f526: 6a5b ldr r3, [r3, #36] @ 0x24 800f528: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800f52c: 68fb ldr r3, [r7, #12] 800f52e: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f530: 2301 movs r3, #1 800f532: e0f7 b.n 800f724 } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) 800f534: 68fb ldr r3, [r7, #12] 800f536: 681b ldr r3, [r3, #0] 800f538: 691b ldr r3, [r3, #16] 800f53a: f003 0303 and.w r3, r3, #3 800f53e: 2b00 cmp r3, #0 800f540: d107 bne.n 800f552 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800f542: 68fb ldr r3, [r7, #12] 800f544: 6a5b ldr r3, [r3, #36] @ 0x24 800f546: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800f54a: 68fb ldr r3, [r7, #12] 800f54c: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f54e: 2301 movs r3, #1 800f550: e0e8 b.n 800f724 } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; 800f552: 68fb ldr r3, [r7, #12] 800f554: 681a ldr r2, [r3, #0] 800f556: 68bb ldr r3, [r7, #8] 800f558: 331b adds r3, #27 800f55a: 011b lsls r3, r3, #4 800f55c: 4413 add r3, r2 800f55e: 681b ldr r3, [r3, #0] 800f560: f003 0204 and.w r2, r3, #4 800f564: 687b ldr r3, [r7, #4] 800f566: 609a str r2, [r3, #8] if (pHeader->IDE == CAN_ID_STD) 800f568: 687b ldr r3, [r7, #4] 800f56a: 689b ldr r3, [r3, #8] 800f56c: 2b00 cmp r3, #0 800f56e: d10c bne.n 800f58a { pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; 800f570: 68fb ldr r3, [r7, #12] 800f572: 681a ldr r2, [r3, #0] 800f574: 68bb ldr r3, [r7, #8] 800f576: 331b adds r3, #27 800f578: 011b lsls r3, r3, #4 800f57a: 4413 add r3, r2 800f57c: 681b ldr r3, [r3, #0] 800f57e: 0d5b lsrs r3, r3, #21 800f580: f3c3 020a ubfx r2, r3, #0, #11 800f584: 687b ldr r3, [r7, #4] 800f586: 601a str r2, [r3, #0] 800f588: e00b b.n 800f5a2 } else { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; 800f58a: 68fb ldr r3, [r7, #12] 800f58c: 681a ldr r2, [r3, #0] 800f58e: 68bb ldr r3, [r7, #8] 800f590: 331b adds r3, #27 800f592: 011b lsls r3, r3, #4 800f594: 4413 add r3, r2 800f596: 681b ldr r3, [r3, #0] 800f598: 08db lsrs r3, r3, #3 800f59a: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & 800f59e: 687b ldr r3, [r7, #4] 800f5a0: 605a str r2, [r3, #4] } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); 800f5a2: 68fb ldr r3, [r7, #12] 800f5a4: 681a ldr r2, [r3, #0] 800f5a6: 68bb ldr r3, [r7, #8] 800f5a8: 331b adds r3, #27 800f5aa: 011b lsls r3, r3, #4 800f5ac: 4413 add r3, r2 800f5ae: 681b ldr r3, [r3, #0] 800f5b0: f003 0202 and.w r2, r3, #2 800f5b4: 687b ldr r3, [r7, #4] 800f5b6: 60da str r2, [r3, #12] if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) 800f5b8: 68fb ldr r3, [r7, #12] 800f5ba: 681a ldr r2, [r3, #0] 800f5bc: 68bb ldr r3, [r7, #8] 800f5be: 331b adds r3, #27 800f5c0: 011b lsls r3, r3, #4 800f5c2: 4413 add r3, r2 800f5c4: 3304 adds r3, #4 800f5c6: 681b ldr r3, [r3, #0] 800f5c8: f003 0308 and.w r3, r3, #8 800f5cc: 2b00 cmp r3, #0 800f5ce: d003 beq.n 800f5d8 { /* Truncate DLC to 8 if received field is over range */ pHeader->DLC = 8U; 800f5d0: 687b ldr r3, [r7, #4] 800f5d2: 2208 movs r2, #8 800f5d4: 611a str r2, [r3, #16] 800f5d6: e00b b.n 800f5f0 } else { pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; 800f5d8: 68fb ldr r3, [r7, #12] 800f5da: 681a ldr r2, [r3, #0] 800f5dc: 68bb ldr r3, [r7, #8] 800f5de: 331b adds r3, #27 800f5e0: 011b lsls r3, r3, #4 800f5e2: 4413 add r3, r2 800f5e4: 3304 adds r3, #4 800f5e6: 681b ldr r3, [r3, #0] 800f5e8: f003 020f and.w r2, r3, #15 800f5ec: 687b ldr r3, [r7, #4] 800f5ee: 611a str r2, [r3, #16] } pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; 800f5f0: 68fb ldr r3, [r7, #12] 800f5f2: 681a ldr r2, [r3, #0] 800f5f4: 68bb ldr r3, [r7, #8] 800f5f6: 331b adds r3, #27 800f5f8: 011b lsls r3, r3, #4 800f5fa: 4413 add r3, r2 800f5fc: 3304 adds r3, #4 800f5fe: 681b ldr r3, [r3, #0] 800f600: 0a1b lsrs r3, r3, #8 800f602: b2da uxtb r2, r3 800f604: 687b ldr r3, [r7, #4] 800f606: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; 800f608: 68fb ldr r3, [r7, #12] 800f60a: 681a ldr r2, [r3, #0] 800f60c: 68bb ldr r3, [r7, #8] 800f60e: 331b adds r3, #27 800f610: 011b lsls r3, r3, #4 800f612: 4413 add r3, r2 800f614: 3304 adds r3, #4 800f616: 681b ldr r3, [r3, #0] 800f618: 0c1b lsrs r3, r3, #16 800f61a: b29a uxth r2, r3 800f61c: 687b ldr r3, [r7, #4] 800f61e: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); 800f620: 68fb ldr r3, [r7, #12] 800f622: 681a ldr r2, [r3, #0] 800f624: 68bb ldr r3, [r7, #8] 800f626: 011b lsls r3, r3, #4 800f628: 4413 add r3, r2 800f62a: f503 73dc add.w r3, r3, #440 @ 0x1b8 800f62e: 681b ldr r3, [r3, #0] 800f630: b2da uxtb r2, r3 800f632: 683b ldr r3, [r7, #0] 800f634: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); 800f636: 68fb ldr r3, [r7, #12] 800f638: 681a ldr r2, [r3, #0] 800f63a: 68bb ldr r3, [r7, #8] 800f63c: 011b lsls r3, r3, #4 800f63e: 4413 add r3, r2 800f640: f503 73dc add.w r3, r3, #440 @ 0x1b8 800f644: 681b ldr r3, [r3, #0] 800f646: 0a1a lsrs r2, r3, #8 800f648: 683b ldr r3, [r7, #0] 800f64a: 3301 adds r3, #1 800f64c: b2d2 uxtb r2, r2 800f64e: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); 800f650: 68fb ldr r3, [r7, #12] 800f652: 681a ldr r2, [r3, #0] 800f654: 68bb ldr r3, [r7, #8] 800f656: 011b lsls r3, r3, #4 800f658: 4413 add r3, r2 800f65a: f503 73dc add.w r3, r3, #440 @ 0x1b8 800f65e: 681b ldr r3, [r3, #0] 800f660: 0c1a lsrs r2, r3, #16 800f662: 683b ldr r3, [r7, #0] 800f664: 3302 adds r3, #2 800f666: b2d2 uxtb r2, r2 800f668: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); 800f66a: 68fb ldr r3, [r7, #12] 800f66c: 681a ldr r2, [r3, #0] 800f66e: 68bb ldr r3, [r7, #8] 800f670: 011b lsls r3, r3, #4 800f672: 4413 add r3, r2 800f674: f503 73dc add.w r3, r3, #440 @ 0x1b8 800f678: 681b ldr r3, [r3, #0] 800f67a: 0e1a lsrs r2, r3, #24 800f67c: 683b ldr r3, [r7, #0] 800f67e: 3303 adds r3, #3 800f680: b2d2 uxtb r2, r2 800f682: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); 800f684: 68fb ldr r3, [r7, #12] 800f686: 681a ldr r2, [r3, #0] 800f688: 68bb ldr r3, [r7, #8] 800f68a: 011b lsls r3, r3, #4 800f68c: 4413 add r3, r2 800f68e: f503 73de add.w r3, r3, #444 @ 0x1bc 800f692: 681a ldr r2, [r3, #0] 800f694: 683b ldr r3, [r7, #0] 800f696: 3304 adds r3, #4 800f698: b2d2 uxtb r2, r2 800f69a: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); 800f69c: 68fb ldr r3, [r7, #12] 800f69e: 681a ldr r2, [r3, #0] 800f6a0: 68bb ldr r3, [r7, #8] 800f6a2: 011b lsls r3, r3, #4 800f6a4: 4413 add r3, r2 800f6a6: f503 73de add.w r3, r3, #444 @ 0x1bc 800f6aa: 681b ldr r3, [r3, #0] 800f6ac: 0a1a lsrs r2, r3, #8 800f6ae: 683b ldr r3, [r7, #0] 800f6b0: 3305 adds r3, #5 800f6b2: b2d2 uxtb r2, r2 800f6b4: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); 800f6b6: 68fb ldr r3, [r7, #12] 800f6b8: 681a ldr r2, [r3, #0] 800f6ba: 68bb ldr r3, [r7, #8] 800f6bc: 011b lsls r3, r3, #4 800f6be: 4413 add r3, r2 800f6c0: f503 73de add.w r3, r3, #444 @ 0x1bc 800f6c4: 681b ldr r3, [r3, #0] 800f6c6: 0c1a lsrs r2, r3, #16 800f6c8: 683b ldr r3, [r7, #0] 800f6ca: 3306 adds r3, #6 800f6cc: b2d2 uxtb r2, r2 800f6ce: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); 800f6d0: 68fb ldr r3, [r7, #12] 800f6d2: 681a ldr r2, [r3, #0] 800f6d4: 68bb ldr r3, [r7, #8] 800f6d6: 011b lsls r3, r3, #4 800f6d8: 4413 add r3, r2 800f6da: f503 73de add.w r3, r3, #444 @ 0x1bc 800f6de: 681b ldr r3, [r3, #0] 800f6e0: 0e1a lsrs r2, r3, #24 800f6e2: 683b ldr r3, [r7, #0] 800f6e4: 3307 adds r3, #7 800f6e6: b2d2 uxtb r2, r2 800f6e8: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800f6ea: 68bb ldr r3, [r7, #8] 800f6ec: 2b00 cmp r3, #0 800f6ee: d108 bne.n 800f702 { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); 800f6f0: 68fb ldr r3, [r7, #12] 800f6f2: 681b ldr r3, [r3, #0] 800f6f4: 68da ldr r2, [r3, #12] 800f6f6: 68fb ldr r3, [r7, #12] 800f6f8: 681b ldr r3, [r3, #0] 800f6fa: f042 0220 orr.w r2, r2, #32 800f6fe: 60da str r2, [r3, #12] 800f700: e007 b.n 800f712 } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); 800f702: 68fb ldr r3, [r7, #12] 800f704: 681b ldr r3, [r3, #0] 800f706: 691a ldr r2, [r3, #16] 800f708: 68fb ldr r3, [r7, #12] 800f70a: 681b ldr r3, [r3, #0] 800f70c: f042 0220 orr.w r2, r2, #32 800f710: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; 800f712: 2300 movs r3, #0 800f714: e006 b.n 800f724 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f716: 68fb ldr r3, [r7, #12] 800f718: 6a5b ldr r3, [r3, #36] @ 0x24 800f71a: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f71e: 68fb ldr r3, [r7, #12] 800f720: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f722: 2301 movs r3, #1 } } 800f724: 4618 mov r0, r3 800f726: 371c adds r7, #28 800f728: 46bd mov sp, r7 800f72a: bc80 pop {r7} 800f72c: 4770 bx lr 0800f72e : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { 800f72e: b480 push {r7} 800f730: b085 sub sp, #20 800f732: af00 add r7, sp, #0 800f734: 6078 str r0, [r7, #4] 800f736: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800f738: 687b ldr r3, [r7, #4] 800f73a: f893 3020 ldrb.w r3, [r3, #32] 800f73e: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || 800f740: 7bfb ldrb r3, [r7, #15] 800f742: 2b01 cmp r3, #1 800f744: d002 beq.n 800f74c 800f746: 7bfb ldrb r3, [r7, #15] 800f748: 2b02 cmp r3, #2 800f74a: d109 bne.n 800f760 (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); 800f74c: 687b ldr r3, [r7, #4] 800f74e: 681b ldr r3, [r3, #0] 800f750: 6959 ldr r1, [r3, #20] 800f752: 687b ldr r3, [r7, #4] 800f754: 681b ldr r3, [r3, #0] 800f756: 683a ldr r2, [r7, #0] 800f758: 430a orrs r2, r1 800f75a: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; 800f75c: 2300 movs r3, #0 800f75e: e006 b.n 800f76e } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f760: 687b ldr r3, [r7, #4] 800f762: 6a5b ldr r3, [r3, #36] @ 0x24 800f764: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f768: 687b ldr r3, [r7, #4] 800f76a: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f76c: 2301 movs r3, #1 } } 800f76e: 4618 mov r0, r3 800f770: 3714 adds r7, #20 800f772: 46bd mov sp, r7 800f774: bc80 pop {r7} 800f776: 4770 bx lr 0800f778 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { 800f778: b580 push {r7, lr} 800f77a: b08a sub sp, #40 @ 0x28 800f77c: af00 add r7, sp, #0 800f77e: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; 800f780: 2300 movs r3, #0 800f782: 627b str r3, [r7, #36] @ 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); 800f784: 687b ldr r3, [r7, #4] 800f786: 681b ldr r3, [r3, #0] 800f788: 695b ldr r3, [r3, #20] 800f78a: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); 800f78c: 687b ldr r3, [r7, #4] 800f78e: 681b ldr r3, [r3, #0] 800f790: 685b ldr r3, [r3, #4] 800f792: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); 800f794: 687b ldr r3, [r7, #4] 800f796: 681b ldr r3, [r3, #0] 800f798: 689b ldr r3, [r3, #8] 800f79a: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); 800f79c: 687b ldr r3, [r7, #4] 800f79e: 681b ldr r3, [r3, #0] 800f7a0: 68db ldr r3, [r3, #12] 800f7a2: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); 800f7a4: 687b ldr r3, [r7, #4] 800f7a6: 681b ldr r3, [r3, #0] 800f7a8: 691b ldr r3, [r3, #16] 800f7aa: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); 800f7ac: 687b ldr r3, [r7, #4] 800f7ae: 681b ldr r3, [r3, #0] 800f7b0: 699b ldr r3, [r3, #24] 800f7b2: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) 800f7b4: 6a3b ldr r3, [r7, #32] 800f7b6: f003 0301 and.w r3, r3, #1 800f7ba: 2b00 cmp r3, #0 800f7bc: d07c beq.n 800f8b8 { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) 800f7be: 69bb ldr r3, [r7, #24] 800f7c0: f003 0301 and.w r3, r3, #1 800f7c4: 2b00 cmp r3, #0 800f7c6: d023 beq.n 800f810 { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); 800f7c8: 687b ldr r3, [r7, #4] 800f7ca: 681b ldr r3, [r3, #0] 800f7cc: 2201 movs r2, #1 800f7ce: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) 800f7d0: 69bb ldr r3, [r7, #24] 800f7d2: f003 0302 and.w r3, r3, #2 800f7d6: 2b00 cmp r3, #0 800f7d8: d003 beq.n 800f7e2 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); 800f7da: 6878 ldr r0, [r7, #4] 800f7dc: f000 f983 bl 800fae6 800f7e0: e016 b.n 800f810 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) 800f7e2: 69bb ldr r3, [r7, #24] 800f7e4: f003 0304 and.w r3, r3, #4 800f7e8: 2b00 cmp r3, #0 800f7ea: d004 beq.n 800f7f6 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; 800f7ec: 6a7b ldr r3, [r7, #36] @ 0x24 800f7ee: f443 6300 orr.w r3, r3, #2048 @ 0x800 800f7f2: 627b str r3, [r7, #36] @ 0x24 800f7f4: e00c b.n 800f810 } else if ((tsrflags & CAN_TSR_TERR0) != 0U) 800f7f6: 69bb ldr r3, [r7, #24] 800f7f8: f003 0308 and.w r3, r3, #8 800f7fc: 2b00 cmp r3, #0 800f7fe: d004 beq.n 800f80a { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; 800f800: 6a7b ldr r3, [r7, #36] @ 0x24 800f802: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800f806: 627b str r3, [r7, #36] @ 0x24 800f808: e002 b.n 800f810 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); 800f80a: 6878 ldr r0, [r7, #4] 800f80c: f000 f986 bl 800fb1c } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) 800f810: 69bb ldr r3, [r7, #24] 800f812: f403 7380 and.w r3, r3, #256 @ 0x100 800f816: 2b00 cmp r3, #0 800f818: d024 beq.n 800f864 { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); 800f81a: 687b ldr r3, [r7, #4] 800f81c: 681b ldr r3, [r3, #0] 800f81e: f44f 7280 mov.w r2, #256 @ 0x100 800f822: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) 800f824: 69bb ldr r3, [r7, #24] 800f826: f403 7300 and.w r3, r3, #512 @ 0x200 800f82a: 2b00 cmp r3, #0 800f82c: d003 beq.n 800f836 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); 800f82e: 6878 ldr r0, [r7, #4] 800f830: f000 f962 bl 800faf8 800f834: e016 b.n 800f864 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) 800f836: 69bb ldr r3, [r7, #24] 800f838: f403 6380 and.w r3, r3, #1024 @ 0x400 800f83c: 2b00 cmp r3, #0 800f83e: d004 beq.n 800f84a { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; 800f840: 6a7b ldr r3, [r7, #36] @ 0x24 800f842: f443 5300 orr.w r3, r3, #8192 @ 0x2000 800f846: 627b str r3, [r7, #36] @ 0x24 800f848: e00c b.n 800f864 } else if ((tsrflags & CAN_TSR_TERR1) != 0U) 800f84a: 69bb ldr r3, [r7, #24] 800f84c: f403 6300 and.w r3, r3, #2048 @ 0x800 800f850: 2b00 cmp r3, #0 800f852: d004 beq.n 800f85e { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; 800f854: 6a7b ldr r3, [r7, #36] @ 0x24 800f856: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800f85a: 627b str r3, [r7, #36] @ 0x24 800f85c: e002 b.n 800f864 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); 800f85e: 6878 ldr r0, [r7, #4] 800f860: f000 f965 bl 800fb2e } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) 800f864: 69bb ldr r3, [r7, #24] 800f866: f403 3380 and.w r3, r3, #65536 @ 0x10000 800f86a: 2b00 cmp r3, #0 800f86c: d024 beq.n 800f8b8 { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); 800f86e: 687b ldr r3, [r7, #4] 800f870: 681b ldr r3, [r3, #0] 800f872: f44f 3280 mov.w r2, #65536 @ 0x10000 800f876: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) 800f878: 69bb ldr r3, [r7, #24] 800f87a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800f87e: 2b00 cmp r3, #0 800f880: d003 beq.n 800f88a #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); 800f882: 6878 ldr r0, [r7, #4] 800f884: f000 f941 bl 800fb0a 800f888: e016 b.n 800f8b8 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) 800f88a: 69bb ldr r3, [r7, #24] 800f88c: f403 2380 and.w r3, r3, #262144 @ 0x40000 800f890: 2b00 cmp r3, #0 800f892: d004 beq.n 800f89e { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; 800f894: 6a7b ldr r3, [r7, #36] @ 0x24 800f896: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f89a: 627b str r3, [r7, #36] @ 0x24 800f89c: e00c b.n 800f8b8 } else if ((tsrflags & CAN_TSR_TERR2) != 0U) 800f89e: 69bb ldr r3, [r7, #24] 800f8a0: f403 2300 and.w r3, r3, #524288 @ 0x80000 800f8a4: 2b00 cmp r3, #0 800f8a6: d004 beq.n 800f8b2 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; 800f8a8: 6a7b ldr r3, [r7, #36] @ 0x24 800f8aa: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800f8ae: 627b str r3, [r7, #36] @ 0x24 800f8b0: e002 b.n 800f8b8 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); 800f8b2: 6878 ldr r0, [r7, #4] 800f8b4: f000 f944 bl 800fb40 } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) 800f8b8: 6a3b ldr r3, [r7, #32] 800f8ba: f003 0308 and.w r3, r3, #8 800f8be: 2b00 cmp r3, #0 800f8c0: d00c beq.n 800f8dc { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) 800f8c2: 697b ldr r3, [r7, #20] 800f8c4: f003 0310 and.w r3, r3, #16 800f8c8: 2b00 cmp r3, #0 800f8ca: d007 beq.n 800f8dc { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; 800f8cc: 6a7b ldr r3, [r7, #36] @ 0x24 800f8ce: f443 7300 orr.w r3, r3, #512 @ 0x200 800f8d2: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); 800f8d4: 687b ldr r3, [r7, #4] 800f8d6: 681b ldr r3, [r3, #0] 800f8d8: 2210 movs r2, #16 800f8da: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) 800f8dc: 6a3b ldr r3, [r7, #32] 800f8de: f003 0304 and.w r3, r3, #4 800f8e2: 2b00 cmp r3, #0 800f8e4: d00b beq.n 800f8fe { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) 800f8e6: 697b ldr r3, [r7, #20] 800f8e8: f003 0308 and.w r3, r3, #8 800f8ec: 2b00 cmp r3, #0 800f8ee: d006 beq.n 800f8fe { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); 800f8f0: 687b ldr r3, [r7, #4] 800f8f2: 681b ldr r3, [r3, #0] 800f8f4: 2208 movs r2, #8 800f8f6: 60da str r2, [r3, #12] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); 800f8f8: 6878 ldr r0, [r7, #4] 800f8fa: f000 f933 bl 800fb64 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) 800f8fe: 6a3b ldr r3, [r7, #32] 800f900: f003 0302 and.w r3, r3, #2 800f904: 2b00 cmp r3, #0 800f906: d009 beq.n 800f91c { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) 800f908: 687b ldr r3, [r7, #4] 800f90a: 681b ldr r3, [r3, #0] 800f90c: 68db ldr r3, [r3, #12] 800f90e: f003 0303 and.w r3, r3, #3 800f912: 2b00 cmp r3, #0 800f914: d002 beq.n 800f91c #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); 800f916: 6878 ldr r0, [r7, #4] 800f918: f000 f91b bl 800fb52 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) 800f91c: 6a3b ldr r3, [r7, #32] 800f91e: f003 0340 and.w r3, r3, #64 @ 0x40 800f922: 2b00 cmp r3, #0 800f924: d00c beq.n 800f940 { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) 800f926: 693b ldr r3, [r7, #16] 800f928: f003 0310 and.w r3, r3, #16 800f92c: 2b00 cmp r3, #0 800f92e: d007 beq.n 800f940 { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; 800f930: 6a7b ldr r3, [r7, #36] @ 0x24 800f932: f443 6380 orr.w r3, r3, #1024 @ 0x400 800f936: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); 800f938: 687b ldr r3, [r7, #4] 800f93a: 681b ldr r3, [r3, #0] 800f93c: 2210 movs r2, #16 800f93e: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) 800f940: 6a3b ldr r3, [r7, #32] 800f942: f003 0320 and.w r3, r3, #32 800f946: 2b00 cmp r3, #0 800f948: d00b beq.n 800f962 { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) 800f94a: 693b ldr r3, [r7, #16] 800f94c: f003 0308 and.w r3, r3, #8 800f950: 2b00 cmp r3, #0 800f952: d006 beq.n 800f962 { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); 800f954: 687b ldr r3, [r7, #4] 800f956: 681b ldr r3, [r3, #0] 800f958: 2208 movs r2, #8 800f95a: 611a str r2, [r3, #16] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); 800f95c: 6878 ldr r0, [r7, #4] 800f95e: f000 f90a bl 800fb76 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) 800f962: 6a3b ldr r3, [r7, #32] 800f964: f003 0310 and.w r3, r3, #16 800f968: 2b00 cmp r3, #0 800f96a: d009 beq.n 800f980 { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) 800f96c: 687b ldr r3, [r7, #4] 800f96e: 681b ldr r3, [r3, #0] 800f970: 691b ldr r3, [r3, #16] 800f972: f003 0303 and.w r3, r3, #3 800f976: 2b00 cmp r3, #0 800f978: d002 beq.n 800f980 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); 800f97a: 6878 ldr r0, [r7, #4] 800f97c: f7fb fa0e bl 800ad9c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) 800f980: 6a3b ldr r3, [r7, #32] 800f982: f403 3300 and.w r3, r3, #131072 @ 0x20000 800f986: 2b00 cmp r3, #0 800f988: d00b beq.n 800f9a2 { if ((msrflags & CAN_MSR_SLAKI) != 0U) 800f98a: 69fb ldr r3, [r7, #28] 800f98c: f003 0310 and.w r3, r3, #16 800f990: 2b00 cmp r3, #0 800f992: d006 beq.n 800f9a2 { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); 800f994: 687b ldr r3, [r7, #4] 800f996: 681b ldr r3, [r3, #0] 800f998: 2210 movs r2, #16 800f99a: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->SleepCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); 800f99c: 6878 ldr r0, [r7, #4] 800f99e: f000 f8f3 bl 800fb88 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ if ((interrupts & CAN_IT_WAKEUP) != 0U) 800f9a2: 6a3b ldr r3, [r7, #32] 800f9a4: f403 3380 and.w r3, r3, #65536 @ 0x10000 800f9a8: 2b00 cmp r3, #0 800f9aa: d00b beq.n 800f9c4 { if ((msrflags & CAN_MSR_WKUI) != 0U) 800f9ac: 69fb ldr r3, [r7, #28] 800f9ae: f003 0308 and.w r3, r3, #8 800f9b2: 2b00 cmp r3, #0 800f9b4: d006 beq.n 800f9c4 { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); 800f9b6: 687b ldr r3, [r7, #4] 800f9b8: 681b ldr r3, [r3, #0] 800f9ba: 2208 movs r2, #8 800f9bc: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->WakeUpFromRxMsgCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); 800f9be: 6878 ldr r0, [r7, #4] 800f9c0: f000 f8eb bl 800fb9a #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ if ((interrupts & CAN_IT_ERROR) != 0U) 800f9c4: 6a3b ldr r3, [r7, #32] 800f9c6: f403 4300 and.w r3, r3, #32768 @ 0x8000 800f9ca: 2b00 cmp r3, #0 800f9cc: d07b beq.n 800fac6 { if ((msrflags & CAN_MSR_ERRI) != 0U) 800f9ce: 69fb ldr r3, [r7, #28] 800f9d0: f003 0304 and.w r3, r3, #4 800f9d4: 2b00 cmp r3, #0 800f9d6: d072 beq.n 800fabe { /* Check Error Warning Flag */ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800f9d8: 6a3b ldr r3, [r7, #32] 800f9da: f403 7380 and.w r3, r3, #256 @ 0x100 800f9de: 2b00 cmp r3, #0 800f9e0: d008 beq.n 800f9f4 ((esrflags & CAN_ESR_EWGF) != 0U)) 800f9e2: 68fb ldr r3, [r7, #12] 800f9e4: f003 0301 and.w r3, r3, #1 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800f9e8: 2b00 cmp r3, #0 800f9ea: d003 beq.n 800f9f4 { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; 800f9ec: 6a7b ldr r3, [r7, #36] @ 0x24 800f9ee: f043 0301 orr.w r3, r3, #1 800f9f2: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Warning Flag as read-only */ } /* Check Error Passive Flag */ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800f9f4: 6a3b ldr r3, [r7, #32] 800f9f6: f403 7300 and.w r3, r3, #512 @ 0x200 800f9fa: 2b00 cmp r3, #0 800f9fc: d008 beq.n 800fa10 ((esrflags & CAN_ESR_EPVF) != 0U)) 800f9fe: 68fb ldr r3, [r7, #12] 800fa00: f003 0302 and.w r3, r3, #2 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800fa04: 2b00 cmp r3, #0 800fa06: d003 beq.n 800fa10 { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; 800fa08: 6a7b ldr r3, [r7, #36] @ 0x24 800fa0a: f043 0302 orr.w r3, r3, #2 800fa0e: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-off Flag */ if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800fa10: 6a3b ldr r3, [r7, #32] 800fa12: f403 6380 and.w r3, r3, #1024 @ 0x400 800fa16: 2b00 cmp r3, #0 800fa18: d008 beq.n 800fa2c ((esrflags & CAN_ESR_BOFF) != 0U)) 800fa1a: 68fb ldr r3, [r7, #12] 800fa1c: f003 0304 and.w r3, r3, #4 if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800fa20: 2b00 cmp r3, #0 800fa22: d003 beq.n 800fa2c { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; 800fa24: 6a7b ldr r3, [r7, #36] @ 0x24 800fa26: f043 0304 orr.w r3, r3, #4 800fa2a: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Bus-Off as read-only */ } /* Check Last Error Code Flag */ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800fa2c: 6a3b ldr r3, [r7, #32] 800fa2e: f403 6300 and.w r3, r3, #2048 @ 0x800 800fa32: 2b00 cmp r3, #0 800fa34: d043 beq.n 800fabe ((esrflags & CAN_ESR_LEC) != 0U)) 800fa36: 68fb ldr r3, [r7, #12] 800fa38: f003 0370 and.w r3, r3, #112 @ 0x70 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800fa3c: 2b00 cmp r3, #0 800fa3e: d03e beq.n 800fabe { switch (esrflags & CAN_ESR_LEC) 800fa40: 68fb ldr r3, [r7, #12] 800fa42: f003 0370 and.w r3, r3, #112 @ 0x70 800fa46: 2b60 cmp r3, #96 @ 0x60 800fa48: d02b beq.n 800faa2 800fa4a: 2b60 cmp r3, #96 @ 0x60 800fa4c: d82e bhi.n 800faac 800fa4e: 2b50 cmp r3, #80 @ 0x50 800fa50: d022 beq.n 800fa98 800fa52: 2b50 cmp r3, #80 @ 0x50 800fa54: d82a bhi.n 800faac 800fa56: 2b40 cmp r3, #64 @ 0x40 800fa58: d019 beq.n 800fa8e 800fa5a: 2b40 cmp r3, #64 @ 0x40 800fa5c: d826 bhi.n 800faac 800fa5e: 2b30 cmp r3, #48 @ 0x30 800fa60: d010 beq.n 800fa84 800fa62: 2b30 cmp r3, #48 @ 0x30 800fa64: d822 bhi.n 800faac 800fa66: 2b10 cmp r3, #16 800fa68: d002 beq.n 800fa70 800fa6a: 2b20 cmp r3, #32 800fa6c: d005 beq.n 800fa7a case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): /* Set CAN error code to CRC error */ errorcode |= HAL_CAN_ERROR_CRC; break; default: break; 800fa6e: e01d b.n 800faac errorcode |= HAL_CAN_ERROR_STF; 800fa70: 6a7b ldr r3, [r7, #36] @ 0x24 800fa72: f043 0308 orr.w r3, r3, #8 800fa76: 627b str r3, [r7, #36] @ 0x24 break; 800fa78: e019 b.n 800faae errorcode |= HAL_CAN_ERROR_FOR; 800fa7a: 6a7b ldr r3, [r7, #36] @ 0x24 800fa7c: f043 0310 orr.w r3, r3, #16 800fa80: 627b str r3, [r7, #36] @ 0x24 break; 800fa82: e014 b.n 800faae errorcode |= HAL_CAN_ERROR_ACK; 800fa84: 6a7b ldr r3, [r7, #36] @ 0x24 800fa86: f043 0320 orr.w r3, r3, #32 800fa8a: 627b str r3, [r7, #36] @ 0x24 break; 800fa8c: e00f b.n 800faae errorcode |= HAL_CAN_ERROR_BR; 800fa8e: 6a7b ldr r3, [r7, #36] @ 0x24 800fa90: f043 0340 orr.w r3, r3, #64 @ 0x40 800fa94: 627b str r3, [r7, #36] @ 0x24 break; 800fa96: e00a b.n 800faae errorcode |= HAL_CAN_ERROR_BD; 800fa98: 6a7b ldr r3, [r7, #36] @ 0x24 800fa9a: f043 0380 orr.w r3, r3, #128 @ 0x80 800fa9e: 627b str r3, [r7, #36] @ 0x24 break; 800faa0: e005 b.n 800faae errorcode |= HAL_CAN_ERROR_CRC; 800faa2: 6a7b ldr r3, [r7, #36] @ 0x24 800faa4: f443 7380 orr.w r3, r3, #256 @ 0x100 800faa8: 627b str r3, [r7, #36] @ 0x24 break; 800faaa: e000 b.n 800faae break; 800faac: bf00 nop } /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); 800faae: 687b ldr r3, [r7, #4] 800fab0: 681b ldr r3, [r3, #0] 800fab2: 699a ldr r2, [r3, #24] 800fab4: 687b ldr r3, [r7, #4] 800fab6: 681b ldr r3, [r3, #0] 800fab8: f022 0270 bic.w r2, r2, #112 @ 0x70 800fabc: 619a str r2, [r3, #24] } } /* Clear ERRI Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); 800fabe: 687b ldr r3, [r7, #4] 800fac0: 681b ldr r3, [r3, #0] 800fac2: 2204 movs r2, #4 800fac4: 605a str r2, [r3, #4] } /* Call the Error call Back in case of Errors */ if (errorcode != HAL_CAN_ERROR_NONE) 800fac6: 6a7b ldr r3, [r7, #36] @ 0x24 800fac8: 2b00 cmp r3, #0 800faca: d008 beq.n 800fade { /* Update error code in handle */ hcan->ErrorCode |= errorcode; 800facc: 687b ldr r3, [r7, #4] 800face: 6a5a ldr r2, [r3, #36] @ 0x24 800fad0: 6a7b ldr r3, [r7, #36] @ 0x24 800fad2: 431a orrs r2, r3 800fad4: 687b ldr r3, [r7, #4] 800fad6: 625a str r2, [r3, #36] @ 0x24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->ErrorCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); 800fad8: 6878 ldr r0, [r7, #4] 800fada: f000 f867 bl 800fbac #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } 800fade: bf00 nop 800fae0: 3728 adds r7, #40 @ 0x28 800fae2: 46bd mov sp, r7 800fae4: bd80 pop {r7, pc} 0800fae6 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { 800fae6: b480 push {r7} 800fae8: b083 sub sp, #12 800faea: af00 add r7, sp, #0 800faec: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the user file */ } 800faee: bf00 nop 800faf0: 370c adds r7, #12 800faf2: 46bd mov sp, r7 800faf4: bc80 pop {r7} 800faf6: 4770 bx lr 0800faf8 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { 800faf8: b480 push {r7} 800fafa: b083 sub sp, #12 800fafc: af00 add r7, sp, #0 800fafe: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the user file */ } 800fb00: bf00 nop 800fb02: 370c adds r7, #12 800fb04: 46bd mov sp, r7 800fb06: bc80 pop {r7} 800fb08: 4770 bx lr 0800fb0a : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) { 800fb0a: b480 push {r7} 800fb0c: b083 sub sp, #12 800fb0e: af00 add r7, sp, #0 800fb10: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the user file */ } 800fb12: bf00 nop 800fb14: 370c adds r7, #12 800fb16: 46bd mov sp, r7 800fb18: bc80 pop {r7} 800fb1a: 4770 bx lr 0800fb1c : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { 800fb1c: b480 push {r7} 800fb1e: b083 sub sp, #12 800fb20: af00 add r7, sp, #0 800fb22: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } 800fb24: bf00 nop 800fb26: 370c adds r7, #12 800fb28: 46bd mov sp, r7 800fb2a: bc80 pop {r7} 800fb2c: 4770 bx lr 0800fb2e : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { 800fb2e: b480 push {r7} 800fb30: b083 sub sp, #12 800fb32: af00 add r7, sp, #0 800fb34: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } 800fb36: bf00 nop 800fb38: 370c adds r7, #12 800fb3a: 46bd mov sp, r7 800fb3c: bc80 pop {r7} 800fb3e: 4770 bx lr 0800fb40 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { 800fb40: b480 push {r7} 800fb42: b083 sub sp, #12 800fb44: af00 add r7, sp, #0 800fb46: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } 800fb48: bf00 nop 800fb4a: 370c adds r7, #12 800fb4c: 46bd mov sp, r7 800fb4e: bc80 pop {r7} 800fb50: 4770 bx lr 0800fb52 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { 800fb52: b480 push {r7} 800fb54: b083 sub sp, #12 800fb56: af00 add r7, sp, #0 800fb58: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the user file */ } 800fb5a: bf00 nop 800fb5c: 370c adds r7, #12 800fb5e: 46bd mov sp, r7 800fb60: bc80 pop {r7} 800fb62: 4770 bx lr 0800fb64 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { 800fb64: b480 push {r7} 800fb66: b083 sub sp, #12 800fb68: af00 add r7, sp, #0 800fb6a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } 800fb6c: bf00 nop 800fb6e: 370c adds r7, #12 800fb70: 46bd mov sp, r7 800fb72: bc80 pop {r7} 800fb74: 4770 bx lr 0800fb76 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { 800fb76: b480 push {r7} 800fb78: b083 sub sp, #12 800fb7a: af00 add r7, sp, #0 800fb7c: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } 800fb7e: bf00 nop 800fb80: 370c adds r7, #12 800fb82: 46bd mov sp, r7 800fb84: bc80 pop {r7} 800fb86: 4770 bx lr 0800fb88 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { 800fb88: b480 push {r7} 800fb8a: b083 sub sp, #12 800fb8c: af00 add r7, sp, #0 800fb8e: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } 800fb90: bf00 nop 800fb92: 370c adds r7, #12 800fb94: 46bd mov sp, r7 800fb96: bc80 pop {r7} 800fb98: 4770 bx lr 0800fb9a : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { 800fb9a: b480 push {r7} 800fb9c: b083 sub sp, #12 800fb9e: af00 add r7, sp, #0 800fba0: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } 800fba2: bf00 nop 800fba4: 370c adds r7, #12 800fba6: 46bd mov sp, r7 800fba8: bc80 pop {r7} 800fbaa: 4770 bx lr 0800fbac : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { 800fbac: b480 push {r7} 800fbae: b083 sub sp, #12 800fbb0: af00 add r7, sp, #0 800fbb2: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } 800fbb4: bf00 nop 800fbb6: 370c adds r7, #12 800fbb8: 46bd mov sp, r7 800fbba: bc80 pop {r7} 800fbbc: 4770 bx lr ... 0800fbc0 <__NVIC_SetPriorityGrouping>: { 800fbc0: b480 push {r7} 800fbc2: b085 sub sp, #20 800fbc4: af00 add r7, sp, #0 800fbc6: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800fbc8: 687b ldr r3, [r7, #4] 800fbca: f003 0307 and.w r3, r3, #7 800fbce: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 800fbd0: 4b0c ldr r3, [pc, #48] @ (800fc04 <__NVIC_SetPriorityGrouping+0x44>) 800fbd2: 68db ldr r3, [r3, #12] 800fbd4: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800fbd6: 68ba ldr r2, [r7, #8] 800fbd8: f64f 03ff movw r3, #63743 @ 0xf8ff 800fbdc: 4013 ands r3, r2 800fbde: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800fbe0: 68fb ldr r3, [r7, #12] 800fbe2: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800fbe4: 68bb ldr r3, [r7, #8] 800fbe6: 4313 orrs r3, r2 reg_value = (reg_value | 800fbe8: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 800fbec: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800fbf0: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800fbf2: 4a04 ldr r2, [pc, #16] @ (800fc04 <__NVIC_SetPriorityGrouping+0x44>) 800fbf4: 68bb ldr r3, [r7, #8] 800fbf6: 60d3 str r3, [r2, #12] } 800fbf8: bf00 nop 800fbfa: 3714 adds r7, #20 800fbfc: 46bd mov sp, r7 800fbfe: bc80 pop {r7} 800fc00: 4770 bx lr 800fc02: bf00 nop 800fc04: e000ed00 .word 0xe000ed00 0800fc08 <__NVIC_GetPriorityGrouping>: { 800fc08: b480 push {r7} 800fc0a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800fc0c: 4b04 ldr r3, [pc, #16] @ (800fc20 <__NVIC_GetPriorityGrouping+0x18>) 800fc0e: 68db ldr r3, [r3, #12] 800fc10: 0a1b lsrs r3, r3, #8 800fc12: f003 0307 and.w r3, r3, #7 } 800fc16: 4618 mov r0, r3 800fc18: 46bd mov sp, r7 800fc1a: bc80 pop {r7} 800fc1c: 4770 bx lr 800fc1e: bf00 nop 800fc20: e000ed00 .word 0xe000ed00 0800fc24 <__NVIC_EnableIRQ>: { 800fc24: b480 push {r7} 800fc26: b083 sub sp, #12 800fc28: af00 add r7, sp, #0 800fc2a: 4603 mov r3, r0 800fc2c: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800fc2e: f997 3007 ldrsb.w r3, [r7, #7] 800fc32: 2b00 cmp r3, #0 800fc34: db0b blt.n 800fc4e <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800fc36: 79fb ldrb r3, [r7, #7] 800fc38: f003 021f and.w r2, r3, #31 800fc3c: 4906 ldr r1, [pc, #24] @ (800fc58 <__NVIC_EnableIRQ+0x34>) 800fc3e: f997 3007 ldrsb.w r3, [r7, #7] 800fc42: 095b lsrs r3, r3, #5 800fc44: 2001 movs r0, #1 800fc46: fa00 f202 lsl.w r2, r0, r2 800fc4a: f841 2023 str.w r2, [r1, r3, lsl #2] } 800fc4e: bf00 nop 800fc50: 370c adds r7, #12 800fc52: 46bd mov sp, r7 800fc54: bc80 pop {r7} 800fc56: 4770 bx lr 800fc58: e000e100 .word 0xe000e100 0800fc5c <__NVIC_SetPriority>: { 800fc5c: b480 push {r7} 800fc5e: b083 sub sp, #12 800fc60: af00 add r7, sp, #0 800fc62: 4603 mov r3, r0 800fc64: 6039 str r1, [r7, #0] 800fc66: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800fc68: f997 3007 ldrsb.w r3, [r7, #7] 800fc6c: 2b00 cmp r3, #0 800fc6e: db0a blt.n 800fc86 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800fc70: 683b ldr r3, [r7, #0] 800fc72: b2da uxtb r2, r3 800fc74: 490c ldr r1, [pc, #48] @ (800fca8 <__NVIC_SetPriority+0x4c>) 800fc76: f997 3007 ldrsb.w r3, [r7, #7] 800fc7a: 0112 lsls r2, r2, #4 800fc7c: b2d2 uxtb r2, r2 800fc7e: 440b add r3, r1 800fc80: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 800fc84: e00a b.n 800fc9c <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800fc86: 683b ldr r3, [r7, #0] 800fc88: b2da uxtb r2, r3 800fc8a: 4908 ldr r1, [pc, #32] @ (800fcac <__NVIC_SetPriority+0x50>) 800fc8c: 79fb ldrb r3, [r7, #7] 800fc8e: f003 030f and.w r3, r3, #15 800fc92: 3b04 subs r3, #4 800fc94: 0112 lsls r2, r2, #4 800fc96: b2d2 uxtb r2, r2 800fc98: 440b add r3, r1 800fc9a: 761a strb r2, [r3, #24] } 800fc9c: bf00 nop 800fc9e: 370c adds r7, #12 800fca0: 46bd mov sp, r7 800fca2: bc80 pop {r7} 800fca4: 4770 bx lr 800fca6: bf00 nop 800fca8: e000e100 .word 0xe000e100 800fcac: e000ed00 .word 0xe000ed00 0800fcb0 : { 800fcb0: b480 push {r7} 800fcb2: b089 sub sp, #36 @ 0x24 800fcb4: af00 add r7, sp, #0 800fcb6: 60f8 str r0, [r7, #12] 800fcb8: 60b9 str r1, [r7, #8] 800fcba: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800fcbc: 68fb ldr r3, [r7, #12] 800fcbe: f003 0307 and.w r3, r3, #7 800fcc2: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 800fcc4: 69fb ldr r3, [r7, #28] 800fcc6: f1c3 0307 rsb r3, r3, #7 800fcca: 2b04 cmp r3, #4 800fccc: bf28 it cs 800fcce: 2304 movcs r3, #4 800fcd0: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800fcd2: 69fb ldr r3, [r7, #28] 800fcd4: 3304 adds r3, #4 800fcd6: 2b06 cmp r3, #6 800fcd8: d902 bls.n 800fce0 800fcda: 69fb ldr r3, [r7, #28] 800fcdc: 3b03 subs r3, #3 800fcde: e000 b.n 800fce2 800fce0: 2300 movs r3, #0 800fce2: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800fce4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800fce8: 69bb ldr r3, [r7, #24] 800fcea: fa02 f303 lsl.w r3, r2, r3 800fcee: 43da mvns r2, r3 800fcf0: 68bb ldr r3, [r7, #8] 800fcf2: 401a ands r2, r3 800fcf4: 697b ldr r3, [r7, #20] 800fcf6: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800fcf8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800fcfc: 697b ldr r3, [r7, #20] 800fcfe: fa01 f303 lsl.w r3, r1, r3 800fd02: 43d9 mvns r1, r3 800fd04: 687b ldr r3, [r7, #4] 800fd06: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800fd08: 4313 orrs r3, r2 } 800fd0a: 4618 mov r0, r3 800fd0c: 3724 adds r7, #36 @ 0x24 800fd0e: 46bd mov sp, r7 800fd10: bc80 pop {r7} 800fd12: 4770 bx lr 0800fd14 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800fd14: b580 push {r7, lr} 800fd16: b082 sub sp, #8 800fd18: af00 add r7, sp, #0 800fd1a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 800fd1c: 687b ldr r3, [r7, #4] 800fd1e: 3b01 subs r3, #1 800fd20: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800fd24: d301 bcc.n 800fd2a { return (1UL); /* Reload value impossible */ 800fd26: 2301 movs r3, #1 800fd28: e00f b.n 800fd4a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800fd2a: 4a0a ldr r2, [pc, #40] @ (800fd54 ) 800fd2c: 687b ldr r3, [r7, #4] 800fd2e: 3b01 subs r3, #1 800fd30: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800fd32: 210f movs r1, #15 800fd34: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800fd38: f7ff ff90 bl 800fc5c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800fd3c: 4b05 ldr r3, [pc, #20] @ (800fd54 ) 800fd3e: 2200 movs r2, #0 800fd40: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800fd42: 4b04 ldr r3, [pc, #16] @ (800fd54 ) 800fd44: 2207 movs r2, #7 800fd46: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 800fd48: 2300 movs r3, #0 } 800fd4a: 4618 mov r0, r3 800fd4c: 3708 adds r7, #8 800fd4e: 46bd mov sp, r7 800fd50: bd80 pop {r7, pc} 800fd52: bf00 nop 800fd54: e000e010 .word 0xe000e010 0800fd58 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 800fd58: b580 push {r7, lr} 800fd5a: b082 sub sp, #8 800fd5c: af00 add r7, sp, #0 800fd5e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800fd60: 6878 ldr r0, [r7, #4] 800fd62: f7ff ff2d bl 800fbc0 <__NVIC_SetPriorityGrouping> } 800fd66: bf00 nop 800fd68: 3708 adds r7, #8 800fd6a: 46bd mov sp, r7 800fd6c: bd80 pop {r7, pc} 0800fd6e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800fd6e: b580 push {r7, lr} 800fd70: b086 sub sp, #24 800fd72: af00 add r7, sp, #0 800fd74: 4603 mov r3, r0 800fd76: 60b9 str r1, [r7, #8] 800fd78: 607a str r2, [r7, #4] 800fd7a: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 800fd7c: 2300 movs r3, #0 800fd7e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800fd80: f7ff ff42 bl 800fc08 <__NVIC_GetPriorityGrouping> 800fd84: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800fd86: 687a ldr r2, [r7, #4] 800fd88: 68b9 ldr r1, [r7, #8] 800fd8a: 6978 ldr r0, [r7, #20] 800fd8c: f7ff ff90 bl 800fcb0 800fd90: 4602 mov r2, r0 800fd92: f997 300f ldrsb.w r3, [r7, #15] 800fd96: 4611 mov r1, r2 800fd98: 4618 mov r0, r3 800fd9a: f7ff ff5f bl 800fc5c <__NVIC_SetPriority> } 800fd9e: bf00 nop 800fda0: 3718 adds r7, #24 800fda2: 46bd mov sp, r7 800fda4: bd80 pop {r7, pc} 0800fda6 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 800fda6: b580 push {r7, lr} 800fda8: b082 sub sp, #8 800fdaa: af00 add r7, sp, #0 800fdac: 4603 mov r3, r0 800fdae: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800fdb0: f997 3007 ldrsb.w r3, [r7, #7] 800fdb4: 4618 mov r0, r3 800fdb6: f7ff ff35 bl 800fc24 <__NVIC_EnableIRQ> } 800fdba: bf00 nop 800fdbc: 3708 adds r7, #8 800fdbe: 46bd mov sp, r7 800fdc0: bd80 pop {r7, pc} 0800fdc2 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800fdc2: b580 push {r7, lr} 800fdc4: b082 sub sp, #8 800fdc6: af00 add r7, sp, #0 800fdc8: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800fdca: 6878 ldr r0, [r7, #4] 800fdcc: f7ff ffa2 bl 800fd14 800fdd0: 4603 mov r3, r0 } 800fdd2: 4618 mov r0, r3 800fdd4: 3708 adds r7, #8 800fdd6: 46bd mov sp, r7 800fdd8: bd80 pop {r7, pc} 0800fdda : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 800fdda: b580 push {r7, lr} 800fddc: b082 sub sp, #8 800fdde: af00 add r7, sp, #0 800fde0: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 800fde2: 687b ldr r3, [r7, #4] 800fde4: 2b00 cmp r3, #0 800fde6: d101 bne.n 800fdec { return HAL_ERROR; 800fde8: 2301 movs r3, #1 800fdea: e00e b.n 800fe0a } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 800fdec: 687b ldr r3, [r7, #4] 800fdee: 795b ldrb r3, [r3, #5] 800fdf0: b2db uxtb r3, r3 800fdf2: 2b00 cmp r3, #0 800fdf4: d105 bne.n 800fe02 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 800fdf6: 687b ldr r3, [r7, #4] 800fdf8: 2200 movs r2, #0 800fdfa: 711a strb r2, [r3, #4] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 800fdfc: 6878 ldr r0, [r7, #4] 800fdfe: f7fa faa5 bl 800a34c } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 800fe02: 687b ldr r3, [r7, #4] 800fe04: 2201 movs r2, #1 800fe06: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 800fe08: 2300 movs r3, #0 } 800fe0a: 4618 mov r0, r3 800fe0c: 3708 adds r7, #8 800fe0e: 46bd mov sp, r7 800fe10: bd80 pop {r7, pc} ... 0800fe14 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 800fe14: b480 push {r7} 800fe16: b085 sub sp, #20 800fe18: af00 add r7, sp, #0 800fe1a: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 800fe1c: 2300 movs r3, #0 800fe1e: 60fb str r3, [r7, #12] /* Check the DMA handle allocation */ if(hdma == NULL) 800fe20: 687b ldr r3, [r7, #4] 800fe22: 2b00 cmp r3, #0 800fe24: d101 bne.n 800fe2a { return HAL_ERROR; 800fe26: 2301 movs r3, #1 800fe28: e059 b.n 800fede assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); #if defined (DMA2) /* calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 800fe2a: 687b ldr r3, [r7, #4] 800fe2c: 681b ldr r3, [r3, #0] 800fe2e: 461a mov r2, r3 800fe30: 4b2d ldr r3, [pc, #180] @ (800fee8 ) 800fe32: 429a cmp r2, r3 800fe34: d80f bhi.n 800fe56 { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 800fe36: 687b ldr r3, [r7, #4] 800fe38: 681b ldr r3, [r3, #0] 800fe3a: 461a mov r2, r3 800fe3c: 4b2b ldr r3, [pc, #172] @ (800feec ) 800fe3e: 4413 add r3, r2 800fe40: 4a2b ldr r2, [pc, #172] @ (800fef0 ) 800fe42: fba2 2303 umull r2, r3, r2, r3 800fe46: 091b lsrs r3, r3, #4 800fe48: 009a lsls r2, r3, #2 800fe4a: 687b ldr r3, [r7, #4] 800fe4c: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA1; 800fe4e: 687b ldr r3, [r7, #4] 800fe50: 4a28 ldr r2, [pc, #160] @ (800fef4 ) 800fe52: 63da str r2, [r3, #60] @ 0x3c 800fe54: e00e b.n 800fe74 } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; 800fe56: 687b ldr r3, [r7, #4] 800fe58: 681b ldr r3, [r3, #0] 800fe5a: 461a mov r2, r3 800fe5c: 4b26 ldr r3, [pc, #152] @ (800fef8 ) 800fe5e: 4413 add r3, r2 800fe60: 4a23 ldr r2, [pc, #140] @ (800fef0 ) 800fe62: fba2 2303 umull r2, r3, r2, r3 800fe66: 091b lsrs r3, r3, #4 800fe68: 009a lsls r2, r3, #2 800fe6a: 687b ldr r3, [r7, #4] 800fe6c: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA2; 800fe6e: 687b ldr r3, [r7, #4] 800fe70: 4a22 ldr r2, [pc, #136] @ (800fefc ) 800fe72: 63da str r2, [r3, #60] @ 0x3c hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; #endif /* DMA2 */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 800fe74: 687b ldr r3, [r7, #4] 800fe76: 2202 movs r2, #2 800fe78: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Get the CR register value */ tmp = hdma->Instance->CCR; 800fe7c: 687b ldr r3, [r7, #4] 800fe7e: 681b ldr r3, [r3, #0] 800fe80: 681b ldr r3, [r3, #0] 800fe82: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 800fe84: 68fb ldr r3, [r7, #12] 800fe86: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 800fe8a: f023 0330 bic.w r3, r3, #48 @ 0x30 800fe8e: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 800fe90: 687b ldr r3, [r7, #4] 800fe92: 685a ldr r2, [r3, #4] hdma->Init.PeriphInc | hdma->Init.MemInc | 800fe94: 687b ldr r3, [r7, #4] 800fe96: 689b ldr r3, [r3, #8] tmp |= hdma->Init.Direction | 800fe98: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 800fe9a: 687b ldr r3, [r7, #4] 800fe9c: 68db ldr r3, [r3, #12] 800fe9e: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800fea0: 687b ldr r3, [r7, #4] 800fea2: 691b ldr r3, [r3, #16] hdma->Init.PeriphInc | hdma->Init.MemInc | 800fea4: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800fea6: 687b ldr r3, [r7, #4] 800fea8: 695b ldr r3, [r3, #20] 800feaa: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800feac: 687b ldr r3, [r7, #4] 800feae: 699b ldr r3, [r3, #24] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800feb0: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800feb2: 687b ldr r3, [r7, #4] 800feb4: 69db ldr r3, [r3, #28] 800feb6: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | 800feb8: 68fa ldr r2, [r7, #12] 800feba: 4313 orrs r3, r2 800febc: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; 800febe: 687b ldr r3, [r7, #4] 800fec0: 681b ldr r3, [r3, #0] 800fec2: 68fa ldr r2, [r7, #12] 800fec4: 601a str r2, [r3, #0] /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800fec6: 687b ldr r3, [r7, #4] 800fec8: 2200 movs r2, #0 800feca: 639a str r2, [r3, #56] @ 0x38 /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 800fecc: 687b ldr r3, [r7, #4] 800fece: 2201 movs r2, #1 800fed0: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; 800fed4: 687b ldr r3, [r7, #4] 800fed6: 2200 movs r2, #0 800fed8: f883 2020 strb.w r2, [r3, #32] return HAL_OK; 800fedc: 2300 movs r3, #0 } 800fede: 4618 mov r0, r3 800fee0: 3714 adds r7, #20 800fee2: 46bd mov sp, r7 800fee4: bc80 pop {r7} 800fee6: 4770 bx lr 800fee8: 40020407 .word 0x40020407 800feec: bffdfff8 .word 0xbffdfff8 800fef0: cccccccd .word 0xcccccccd 800fef4: 40020000 .word 0x40020000 800fef8: bffdfbf8 .word 0xbffdfbf8 800fefc: 40020400 .word 0x40020400 0800ff00 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 800ff00: b580 push {r7, lr} 800ff02: b086 sub sp, #24 800ff04: af00 add r7, sp, #0 800ff06: 60f8 str r0, [r7, #12] 800ff08: 60b9 str r1, [r7, #8] 800ff0a: 607a str r2, [r7, #4] 800ff0c: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800ff0e: 2300 movs r3, #0 800ff10: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 800ff12: 68fb ldr r3, [r7, #12] 800ff14: f893 3020 ldrb.w r3, [r3, #32] 800ff18: 2b01 cmp r3, #1 800ff1a: d101 bne.n 800ff20 800ff1c: 2302 movs r3, #2 800ff1e: e04b b.n 800ffb8 800ff20: 68fb ldr r3, [r7, #12] 800ff22: 2201 movs r2, #1 800ff24: f883 2020 strb.w r2, [r3, #32] if(HAL_DMA_STATE_READY == hdma->State) 800ff28: 68fb ldr r3, [r7, #12] 800ff2a: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800ff2e: b2db uxtb r3, r3 800ff30: 2b01 cmp r3, #1 800ff32: d13a bne.n 800ffaa { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 800ff34: 68fb ldr r3, [r7, #12] 800ff36: 2202 movs r2, #2 800ff38: f883 2021 strb.w r2, [r3, #33] @ 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800ff3c: 68fb ldr r3, [r7, #12] 800ff3e: 2200 movs r2, #0 800ff40: 639a str r2, [r3, #56] @ 0x38 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 800ff42: 68fb ldr r3, [r7, #12] 800ff44: 681b ldr r3, [r3, #0] 800ff46: 681a ldr r2, [r3, #0] 800ff48: 68fb ldr r3, [r7, #12] 800ff4a: 681b ldr r3, [r3, #0] 800ff4c: f022 0201 bic.w r2, r2, #1 800ff50: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 800ff52: 683b ldr r3, [r7, #0] 800ff54: 687a ldr r2, [r7, #4] 800ff56: 68b9 ldr r1, [r7, #8] 800ff58: 68f8 ldr r0, [r7, #12] 800ff5a: f000 fbbc bl 80106d6 /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if(NULL != hdma->XferHalfCpltCallback) 800ff5e: 68fb ldr r3, [r7, #12] 800ff60: 6adb ldr r3, [r3, #44] @ 0x2c 800ff62: 2b00 cmp r3, #0 800ff64: d008 beq.n 800ff78 { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800ff66: 68fb ldr r3, [r7, #12] 800ff68: 681b ldr r3, [r3, #0] 800ff6a: 681a ldr r2, [r3, #0] 800ff6c: 68fb ldr r3, [r7, #12] 800ff6e: 681b ldr r3, [r3, #0] 800ff70: f042 020e orr.w r2, r2, #14 800ff74: 601a str r2, [r3, #0] 800ff76: e00f b.n 800ff98 } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800ff78: 68fb ldr r3, [r7, #12] 800ff7a: 681b ldr r3, [r3, #0] 800ff7c: 681a ldr r2, [r3, #0] 800ff7e: 68fb ldr r3, [r7, #12] 800ff80: 681b ldr r3, [r3, #0] 800ff82: f022 0204 bic.w r2, r2, #4 800ff86: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 800ff88: 68fb ldr r3, [r7, #12] 800ff8a: 681b ldr r3, [r3, #0] 800ff8c: 681a ldr r2, [r3, #0] 800ff8e: 68fb ldr r3, [r7, #12] 800ff90: 681b ldr r3, [r3, #0] 800ff92: f042 020a orr.w r2, r2, #10 800ff96: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 800ff98: 68fb ldr r3, [r7, #12] 800ff9a: 681b ldr r3, [r3, #0] 800ff9c: 681a ldr r2, [r3, #0] 800ff9e: 68fb ldr r3, [r7, #12] 800ffa0: 681b ldr r3, [r3, #0] 800ffa2: f042 0201 orr.w r2, r2, #1 800ffa6: 601a str r2, [r3, #0] 800ffa8: e005 b.n 800ffb6 } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); 800ffaa: 68fb ldr r3, [r7, #12] 800ffac: 2200 movs r2, #0 800ffae: f883 2020 strb.w r2, [r3, #32] /* Remain BUSY */ status = HAL_BUSY; 800ffb2: 2302 movs r3, #2 800ffb4: 75fb strb r3, [r7, #23] } return status; 800ffb6: 7dfb ldrb r3, [r7, #23] } 800ffb8: 4618 mov r0, r3 800ffba: 3718 adds r7, #24 800ffbc: 46bd mov sp, r7 800ffbe: bd80 pop {r7, pc} 0800ffc0 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 800ffc0: b480 push {r7} 800ffc2: b085 sub sp, #20 800ffc4: af00 add r7, sp, #0 800ffc6: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800ffc8: 2300 movs r3, #0 800ffca: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 800ffcc: 687b ldr r3, [r7, #4] 800ffce: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800ffd2: b2db uxtb r3, r3 800ffd4: 2b02 cmp r3, #2 800ffd6: d008 beq.n 800ffea { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800ffd8: 687b ldr r3, [r7, #4] 800ffda: 2204 movs r2, #4 800ffdc: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800ffde: 687b ldr r3, [r7, #4] 800ffe0: 2200 movs r2, #0 800ffe2: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800ffe6: 2301 movs r3, #1 800ffe8: e020 b.n 801002c } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800ffea: 687b ldr r3, [r7, #4] 800ffec: 681b ldr r3, [r3, #0] 800ffee: 681a ldr r2, [r3, #0] 800fff0: 687b ldr r3, [r7, #4] 800fff2: 681b ldr r3, [r3, #0] 800fff4: f022 020e bic.w r2, r2, #14 800fff8: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800fffa: 687b ldr r3, [r7, #4] 800fffc: 681b ldr r3, [r3, #0] 800fffe: 681a ldr r2, [r3, #0] 8010000: 687b ldr r3, [r7, #4] 8010002: 681b ldr r3, [r3, #0] 8010004: f022 0201 bic.w r2, r2, #1 8010008: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 801000a: 687b ldr r3, [r7, #4] 801000c: 6c1a ldr r2, [r3, #64] @ 0x40 801000e: 687b ldr r3, [r7, #4] 8010010: 6bdb ldr r3, [r3, #60] @ 0x3c 8010012: 2101 movs r1, #1 8010014: fa01 f202 lsl.w r2, r1, r2 8010018: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 801001a: 687b ldr r3, [r7, #4] 801001c: 2201 movs r2, #1 801001e: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8010022: 687b ldr r3, [r7, #4] 8010024: 2200 movs r2, #0 8010026: f883 2020 strb.w r2, [r3, #32] return status; 801002a: 7bfb ldrb r3, [r7, #15] } 801002c: 4618 mov r0, r3 801002e: 3714 adds r7, #20 8010030: 46bd mov sp, r7 8010032: bc80 pop {r7} 8010034: 4770 bx lr ... 08010038 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8010038: b580 push {r7, lr} 801003a: b084 sub sp, #16 801003c: af00 add r7, sp, #0 801003e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8010040: 2300 movs r3, #0 8010042: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 8010044: 687b ldr r3, [r7, #4] 8010046: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 801004a: b2db uxtb r3, r3 801004c: 2b02 cmp r3, #2 801004e: d005 beq.n 801005c { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8010050: 687b ldr r3, [r7, #4] 8010052: 2204 movs r2, #4 8010054: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 8010056: 2301 movs r3, #1 8010058: 73fb strb r3, [r7, #15] 801005a: e0d6 b.n 801020a } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 801005c: 687b ldr r3, [r7, #4] 801005e: 681b ldr r3, [r3, #0] 8010060: 681a ldr r2, [r3, #0] 8010062: 687b ldr r3, [r7, #4] 8010064: 681b ldr r3, [r3, #0] 8010066: f022 020e bic.w r2, r2, #14 801006a: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 801006c: 687b ldr r3, [r7, #4] 801006e: 681b ldr r3, [r3, #0] 8010070: 681a ldr r2, [r3, #0] 8010072: 687b ldr r3, [r7, #4] 8010074: 681b ldr r3, [r3, #0] 8010076: f022 0201 bic.w r2, r2, #1 801007a: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 801007c: 687b ldr r3, [r7, #4] 801007e: 681b ldr r3, [r3, #0] 8010080: 461a mov r2, r3 8010082: 4b64 ldr r3, [pc, #400] @ (8010214 ) 8010084: 429a cmp r2, r3 8010086: d958 bls.n 801013a 8010088: 687b ldr r3, [r7, #4] 801008a: 681b ldr r3, [r3, #0] 801008c: 4a62 ldr r2, [pc, #392] @ (8010218 ) 801008e: 4293 cmp r3, r2 8010090: d04f beq.n 8010132 8010092: 687b ldr r3, [r7, #4] 8010094: 681b ldr r3, [r3, #0] 8010096: 4a61 ldr r2, [pc, #388] @ (801021c ) 8010098: 4293 cmp r3, r2 801009a: d048 beq.n 801012e 801009c: 687b ldr r3, [r7, #4] 801009e: 681b ldr r3, [r3, #0] 80100a0: 4a5f ldr r2, [pc, #380] @ (8010220 ) 80100a2: 4293 cmp r3, r2 80100a4: d040 beq.n 8010128 80100a6: 687b ldr r3, [r7, #4] 80100a8: 681b ldr r3, [r3, #0] 80100aa: 4a5e ldr r2, [pc, #376] @ (8010224 ) 80100ac: 4293 cmp r3, r2 80100ae: d038 beq.n 8010122 80100b0: 687b ldr r3, [r7, #4] 80100b2: 681b ldr r3, [r3, #0] 80100b4: 4a5c ldr r2, [pc, #368] @ (8010228 ) 80100b6: 4293 cmp r3, r2 80100b8: d030 beq.n 801011c 80100ba: 687b ldr r3, [r7, #4] 80100bc: 681b ldr r3, [r3, #0] 80100be: 4a5b ldr r2, [pc, #364] @ (801022c ) 80100c0: 4293 cmp r3, r2 80100c2: d028 beq.n 8010116 80100c4: 687b ldr r3, [r7, #4] 80100c6: 681b ldr r3, [r3, #0] 80100c8: 4a52 ldr r2, [pc, #328] @ (8010214 ) 80100ca: 4293 cmp r3, r2 80100cc: d020 beq.n 8010110 80100ce: 687b ldr r3, [r7, #4] 80100d0: 681b ldr r3, [r3, #0] 80100d2: 4a57 ldr r2, [pc, #348] @ (8010230 ) 80100d4: 4293 cmp r3, r2 80100d6: d019 beq.n 801010c 80100d8: 687b ldr r3, [r7, #4] 80100da: 681b ldr r3, [r3, #0] 80100dc: 4a55 ldr r2, [pc, #340] @ (8010234 ) 80100de: 4293 cmp r3, r2 80100e0: d012 beq.n 8010108 80100e2: 687b ldr r3, [r7, #4] 80100e4: 681b ldr r3, [r3, #0] 80100e6: 4a54 ldr r2, [pc, #336] @ (8010238 ) 80100e8: 4293 cmp r3, r2 80100ea: d00a beq.n 8010102 80100ec: 687b ldr r3, [r7, #4] 80100ee: 681b ldr r3, [r3, #0] 80100f0: 4a52 ldr r2, [pc, #328] @ (801023c ) 80100f2: 4293 cmp r3, r2 80100f4: d102 bne.n 80100fc 80100f6: f44f 5380 mov.w r3, #4096 @ 0x1000 80100fa: e01b b.n 8010134 80100fc: f44f 3380 mov.w r3, #65536 @ 0x10000 8010100: e018 b.n 8010134 8010102: f44f 7380 mov.w r3, #256 @ 0x100 8010106: e015 b.n 8010134 8010108: 2310 movs r3, #16 801010a: e013 b.n 8010134 801010c: 2301 movs r3, #1 801010e: e011 b.n 8010134 8010110: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8010114: e00e b.n 8010134 8010116: f44f 1380 mov.w r3, #1048576 @ 0x100000 801011a: e00b b.n 8010134 801011c: f44f 3380 mov.w r3, #65536 @ 0x10000 8010120: e008 b.n 8010134 8010122: f44f 5380 mov.w r3, #4096 @ 0x1000 8010126: e005 b.n 8010134 8010128: f44f 7380 mov.w r3, #256 @ 0x100 801012c: e002 b.n 8010134 801012e: 2310 movs r3, #16 8010130: e000 b.n 8010134 8010132: 2301 movs r3, #1 8010134: 4a42 ldr r2, [pc, #264] @ (8010240 ) 8010136: 6053 str r3, [r2, #4] 8010138: e057 b.n 80101ea 801013a: 687b ldr r3, [r7, #4] 801013c: 681b ldr r3, [r3, #0] 801013e: 4a36 ldr r2, [pc, #216] @ (8010218 ) 8010140: 4293 cmp r3, r2 8010142: d04f beq.n 80101e4 8010144: 687b ldr r3, [r7, #4] 8010146: 681b ldr r3, [r3, #0] 8010148: 4a34 ldr r2, [pc, #208] @ (801021c ) 801014a: 4293 cmp r3, r2 801014c: d048 beq.n 80101e0 801014e: 687b ldr r3, [r7, #4] 8010150: 681b ldr r3, [r3, #0] 8010152: 4a33 ldr r2, [pc, #204] @ (8010220 ) 8010154: 4293 cmp r3, r2 8010156: d040 beq.n 80101da 8010158: 687b ldr r3, [r7, #4] 801015a: 681b ldr r3, [r3, #0] 801015c: 4a31 ldr r2, [pc, #196] @ (8010224 ) 801015e: 4293 cmp r3, r2 8010160: d038 beq.n 80101d4 8010162: 687b ldr r3, [r7, #4] 8010164: 681b ldr r3, [r3, #0] 8010166: 4a30 ldr r2, [pc, #192] @ (8010228 ) 8010168: 4293 cmp r3, r2 801016a: d030 beq.n 80101ce 801016c: 687b ldr r3, [r7, #4] 801016e: 681b ldr r3, [r3, #0] 8010170: 4a2e ldr r2, [pc, #184] @ (801022c ) 8010172: 4293 cmp r3, r2 8010174: d028 beq.n 80101c8 8010176: 687b ldr r3, [r7, #4] 8010178: 681b ldr r3, [r3, #0] 801017a: 4a26 ldr r2, [pc, #152] @ (8010214 ) 801017c: 4293 cmp r3, r2 801017e: d020 beq.n 80101c2 8010180: 687b ldr r3, [r7, #4] 8010182: 681b ldr r3, [r3, #0] 8010184: 4a2a ldr r2, [pc, #168] @ (8010230 ) 8010186: 4293 cmp r3, r2 8010188: d019 beq.n 80101be 801018a: 687b ldr r3, [r7, #4] 801018c: 681b ldr r3, [r3, #0] 801018e: 4a29 ldr r2, [pc, #164] @ (8010234 ) 8010190: 4293 cmp r3, r2 8010192: d012 beq.n 80101ba 8010194: 687b ldr r3, [r7, #4] 8010196: 681b ldr r3, [r3, #0] 8010198: 4a27 ldr r2, [pc, #156] @ (8010238 ) 801019a: 4293 cmp r3, r2 801019c: d00a beq.n 80101b4 801019e: 687b ldr r3, [r7, #4] 80101a0: 681b ldr r3, [r3, #0] 80101a2: 4a26 ldr r2, [pc, #152] @ (801023c ) 80101a4: 4293 cmp r3, r2 80101a6: d102 bne.n 80101ae 80101a8: f44f 5380 mov.w r3, #4096 @ 0x1000 80101ac: e01b b.n 80101e6 80101ae: f44f 3380 mov.w r3, #65536 @ 0x10000 80101b2: e018 b.n 80101e6 80101b4: f44f 7380 mov.w r3, #256 @ 0x100 80101b8: e015 b.n 80101e6 80101ba: 2310 movs r3, #16 80101bc: e013 b.n 80101e6 80101be: 2301 movs r3, #1 80101c0: e011 b.n 80101e6 80101c2: f04f 7380 mov.w r3, #16777216 @ 0x1000000 80101c6: e00e b.n 80101e6 80101c8: f44f 1380 mov.w r3, #1048576 @ 0x100000 80101cc: e00b b.n 80101e6 80101ce: f44f 3380 mov.w r3, #65536 @ 0x10000 80101d2: e008 b.n 80101e6 80101d4: f44f 5380 mov.w r3, #4096 @ 0x1000 80101d8: e005 b.n 80101e6 80101da: f44f 7380 mov.w r3, #256 @ 0x100 80101de: e002 b.n 80101e6 80101e0: 2310 movs r3, #16 80101e2: e000 b.n 80101e6 80101e4: 2301 movs r3, #1 80101e6: 4a17 ldr r2, [pc, #92] @ (8010244 ) 80101e8: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80101ea: 687b ldr r3, [r7, #4] 80101ec: 2201 movs r2, #1 80101ee: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80101f2: 687b ldr r3, [r7, #4] 80101f4: 2200 movs r2, #0 80101f6: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 80101fa: 687b ldr r3, [r7, #4] 80101fc: 6b5b ldr r3, [r3, #52] @ 0x34 80101fe: 2b00 cmp r3, #0 8010200: d003 beq.n 801020a { hdma->XferAbortCallback(hdma); 8010202: 687b ldr r3, [r7, #4] 8010204: 6b5b ldr r3, [r3, #52] @ 0x34 8010206: 6878 ldr r0, [r7, #4] 8010208: 4798 blx r3 } } return status; 801020a: 7bfb ldrb r3, [r7, #15] } 801020c: 4618 mov r0, r3 801020e: 3710 adds r7, #16 8010210: 46bd mov sp, r7 8010212: bd80 pop {r7, pc} 8010214: 40020080 .word 0x40020080 8010218: 40020008 .word 0x40020008 801021c: 4002001c .word 0x4002001c 8010220: 40020030 .word 0x40020030 8010224: 40020044 .word 0x40020044 8010228: 40020058 .word 0x40020058 801022c: 4002006c .word 0x4002006c 8010230: 40020408 .word 0x40020408 8010234: 4002041c .word 0x4002041c 8010238: 40020430 .word 0x40020430 801023c: 40020444 .word 0x40020444 8010240: 40020400 .word 0x40020400 8010244: 40020000 .word 0x40020000 08010248 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8010248: b580 push {r7, lr} 801024a: b084 sub sp, #16 801024c: af00 add r7, sp, #0 801024e: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; 8010250: 687b ldr r3, [r7, #4] 8010252: 6bdb ldr r3, [r3, #60] @ 0x3c 8010254: 681b ldr r3, [r3, #0] 8010256: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; 8010258: 687b ldr r3, [r7, #4] 801025a: 681b ldr r3, [r3, #0] 801025c: 681b ldr r3, [r3, #0] 801025e: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 8010260: 687b ldr r3, [r7, #4] 8010262: 6c1b ldr r3, [r3, #64] @ 0x40 8010264: 2204 movs r2, #4 8010266: 409a lsls r2, r3 8010268: 68fb ldr r3, [r7, #12] 801026a: 4013 ands r3, r2 801026c: 2b00 cmp r3, #0 801026e: f000 80f1 beq.w 8010454 8010272: 68bb ldr r3, [r7, #8] 8010274: f003 0304 and.w r3, r3, #4 8010278: 2b00 cmp r3, #0 801027a: f000 80eb beq.w 8010454 { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 801027e: 687b ldr r3, [r7, #4] 8010280: 681b ldr r3, [r3, #0] 8010282: 681b ldr r3, [r3, #0] 8010284: f003 0320 and.w r3, r3, #32 8010288: 2b00 cmp r3, #0 801028a: d107 bne.n 801029c { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 801028c: 687b ldr r3, [r7, #4] 801028e: 681b ldr r3, [r3, #0] 8010290: 681a ldr r2, [r3, #0] 8010292: 687b ldr r3, [r7, #4] 8010294: 681b ldr r3, [r3, #0] 8010296: f022 0204 bic.w r2, r2, #4 801029a: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); 801029c: 687b ldr r3, [r7, #4] 801029e: 681b ldr r3, [r3, #0] 80102a0: 461a mov r2, r3 80102a2: 4b5f ldr r3, [pc, #380] @ (8010420 ) 80102a4: 429a cmp r2, r3 80102a6: d958 bls.n 801035a 80102a8: 687b ldr r3, [r7, #4] 80102aa: 681b ldr r3, [r3, #0] 80102ac: 4a5d ldr r2, [pc, #372] @ (8010424 ) 80102ae: 4293 cmp r3, r2 80102b0: d04f beq.n 8010352 80102b2: 687b ldr r3, [r7, #4] 80102b4: 681b ldr r3, [r3, #0] 80102b6: 4a5c ldr r2, [pc, #368] @ (8010428 ) 80102b8: 4293 cmp r3, r2 80102ba: d048 beq.n 801034e 80102bc: 687b ldr r3, [r7, #4] 80102be: 681b ldr r3, [r3, #0] 80102c0: 4a5a ldr r2, [pc, #360] @ (801042c ) 80102c2: 4293 cmp r3, r2 80102c4: d040 beq.n 8010348 80102c6: 687b ldr r3, [r7, #4] 80102c8: 681b ldr r3, [r3, #0] 80102ca: 4a59 ldr r2, [pc, #356] @ (8010430 ) 80102cc: 4293 cmp r3, r2 80102ce: d038 beq.n 8010342 80102d0: 687b ldr r3, [r7, #4] 80102d2: 681b ldr r3, [r3, #0] 80102d4: 4a57 ldr r2, [pc, #348] @ (8010434 ) 80102d6: 4293 cmp r3, r2 80102d8: d030 beq.n 801033c 80102da: 687b ldr r3, [r7, #4] 80102dc: 681b ldr r3, [r3, #0] 80102de: 4a56 ldr r2, [pc, #344] @ (8010438 ) 80102e0: 4293 cmp r3, r2 80102e2: d028 beq.n 8010336 80102e4: 687b ldr r3, [r7, #4] 80102e6: 681b ldr r3, [r3, #0] 80102e8: 4a4d ldr r2, [pc, #308] @ (8010420 ) 80102ea: 4293 cmp r3, r2 80102ec: d020 beq.n 8010330 80102ee: 687b ldr r3, [r7, #4] 80102f0: 681b ldr r3, [r3, #0] 80102f2: 4a52 ldr r2, [pc, #328] @ (801043c ) 80102f4: 4293 cmp r3, r2 80102f6: d019 beq.n 801032c 80102f8: 687b ldr r3, [r7, #4] 80102fa: 681b ldr r3, [r3, #0] 80102fc: 4a50 ldr r2, [pc, #320] @ (8010440 ) 80102fe: 4293 cmp r3, r2 8010300: d012 beq.n 8010328 8010302: 687b ldr r3, [r7, #4] 8010304: 681b ldr r3, [r3, #0] 8010306: 4a4f ldr r2, [pc, #316] @ (8010444 ) 8010308: 4293 cmp r3, r2 801030a: d00a beq.n 8010322 801030c: 687b ldr r3, [r7, #4] 801030e: 681b ldr r3, [r3, #0] 8010310: 4a4d ldr r2, [pc, #308] @ (8010448 ) 8010312: 4293 cmp r3, r2 8010314: d102 bne.n 801031c 8010316: f44f 4380 mov.w r3, #16384 @ 0x4000 801031a: e01b b.n 8010354 801031c: f44f 2380 mov.w r3, #262144 @ 0x40000 8010320: e018 b.n 8010354 8010322: f44f 6380 mov.w r3, #1024 @ 0x400 8010326: e015 b.n 8010354 8010328: 2340 movs r3, #64 @ 0x40 801032a: e013 b.n 8010354 801032c: 2304 movs r3, #4 801032e: e011 b.n 8010354 8010330: f04f 6380 mov.w r3, #67108864 @ 0x4000000 8010334: e00e b.n 8010354 8010336: f44f 0380 mov.w r3, #4194304 @ 0x400000 801033a: e00b b.n 8010354 801033c: f44f 2380 mov.w r3, #262144 @ 0x40000 8010340: e008 b.n 8010354 8010342: f44f 4380 mov.w r3, #16384 @ 0x4000 8010346: e005 b.n 8010354 8010348: f44f 6380 mov.w r3, #1024 @ 0x400 801034c: e002 b.n 8010354 801034e: 2340 movs r3, #64 @ 0x40 8010350: e000 b.n 8010354 8010352: 2304 movs r3, #4 8010354: 4a3d ldr r2, [pc, #244] @ (801044c ) 8010356: 6053 str r3, [r2, #4] 8010358: e057 b.n 801040a 801035a: 687b ldr r3, [r7, #4] 801035c: 681b ldr r3, [r3, #0] 801035e: 4a31 ldr r2, [pc, #196] @ (8010424 ) 8010360: 4293 cmp r3, r2 8010362: d04f beq.n 8010404 8010364: 687b ldr r3, [r7, #4] 8010366: 681b ldr r3, [r3, #0] 8010368: 4a2f ldr r2, [pc, #188] @ (8010428 ) 801036a: 4293 cmp r3, r2 801036c: d048 beq.n 8010400 801036e: 687b ldr r3, [r7, #4] 8010370: 681b ldr r3, [r3, #0] 8010372: 4a2e ldr r2, [pc, #184] @ (801042c ) 8010374: 4293 cmp r3, r2 8010376: d040 beq.n 80103fa 8010378: 687b ldr r3, [r7, #4] 801037a: 681b ldr r3, [r3, #0] 801037c: 4a2c ldr r2, [pc, #176] @ (8010430 ) 801037e: 4293 cmp r3, r2 8010380: d038 beq.n 80103f4 8010382: 687b ldr r3, [r7, #4] 8010384: 681b ldr r3, [r3, #0] 8010386: 4a2b ldr r2, [pc, #172] @ (8010434 ) 8010388: 4293 cmp r3, r2 801038a: d030 beq.n 80103ee 801038c: 687b ldr r3, [r7, #4] 801038e: 681b ldr r3, [r3, #0] 8010390: 4a29 ldr r2, [pc, #164] @ (8010438 ) 8010392: 4293 cmp r3, r2 8010394: d028 beq.n 80103e8 8010396: 687b ldr r3, [r7, #4] 8010398: 681b ldr r3, [r3, #0] 801039a: 4a21 ldr r2, [pc, #132] @ (8010420 ) 801039c: 4293 cmp r3, r2 801039e: d020 beq.n 80103e2 80103a0: 687b ldr r3, [r7, #4] 80103a2: 681b ldr r3, [r3, #0] 80103a4: 4a25 ldr r2, [pc, #148] @ (801043c ) 80103a6: 4293 cmp r3, r2 80103a8: d019 beq.n 80103de 80103aa: 687b ldr r3, [r7, #4] 80103ac: 681b ldr r3, [r3, #0] 80103ae: 4a24 ldr r2, [pc, #144] @ (8010440 ) 80103b0: 4293 cmp r3, r2 80103b2: d012 beq.n 80103da 80103b4: 687b ldr r3, [r7, #4] 80103b6: 681b ldr r3, [r3, #0] 80103b8: 4a22 ldr r2, [pc, #136] @ (8010444 ) 80103ba: 4293 cmp r3, r2 80103bc: d00a beq.n 80103d4 80103be: 687b ldr r3, [r7, #4] 80103c0: 681b ldr r3, [r3, #0] 80103c2: 4a21 ldr r2, [pc, #132] @ (8010448 ) 80103c4: 4293 cmp r3, r2 80103c6: d102 bne.n 80103ce 80103c8: f44f 4380 mov.w r3, #16384 @ 0x4000 80103cc: e01b b.n 8010406 80103ce: f44f 2380 mov.w r3, #262144 @ 0x40000 80103d2: e018 b.n 8010406 80103d4: f44f 6380 mov.w r3, #1024 @ 0x400 80103d8: e015 b.n 8010406 80103da: 2340 movs r3, #64 @ 0x40 80103dc: e013 b.n 8010406 80103de: 2304 movs r3, #4 80103e0: e011 b.n 8010406 80103e2: f04f 6380 mov.w r3, #67108864 @ 0x4000000 80103e6: e00e b.n 8010406 80103e8: f44f 0380 mov.w r3, #4194304 @ 0x400000 80103ec: e00b b.n 8010406 80103ee: f44f 2380 mov.w r3, #262144 @ 0x40000 80103f2: e008 b.n 8010406 80103f4: f44f 4380 mov.w r3, #16384 @ 0x4000 80103f8: e005 b.n 8010406 80103fa: f44f 6380 mov.w r3, #1024 @ 0x400 80103fe: e002 b.n 8010406 8010400: 2340 movs r3, #64 @ 0x40 8010402: e000 b.n 8010406 8010404: 2304 movs r3, #4 8010406: 4a12 ldr r2, [pc, #72] @ (8010450 ) 8010408: 6053 str r3, [r2, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 801040a: 687b ldr r3, [r7, #4] 801040c: 6adb ldr r3, [r3, #44] @ 0x2c 801040e: 2b00 cmp r3, #0 8010410: f000 8136 beq.w 8010680 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8010414: 687b ldr r3, [r7, #4] 8010416: 6adb ldr r3, [r3, #44] @ 0x2c 8010418: 6878 ldr r0, [r7, #4] 801041a: 4798 blx r3 if(hdma->XferHalfCpltCallback != NULL) 801041c: e130 b.n 8010680 801041e: bf00 nop 8010420: 40020080 .word 0x40020080 8010424: 40020008 .word 0x40020008 8010428: 4002001c .word 0x4002001c 801042c: 40020030 .word 0x40020030 8010430: 40020044 .word 0x40020044 8010434: 40020058 .word 0x40020058 8010438: 4002006c .word 0x4002006c 801043c: 40020408 .word 0x40020408 8010440: 4002041c .word 0x4002041c 8010444: 40020430 .word 0x40020430 8010448: 40020444 .word 0x40020444 801044c: 40020400 .word 0x40020400 8010450: 40020000 .word 0x40020000 } } /* Transfer Complete Interrupt management ***********************************/ else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) 8010454: 687b ldr r3, [r7, #4] 8010456: 6c1b ldr r3, [r3, #64] @ 0x40 8010458: 2202 movs r2, #2 801045a: 409a lsls r2, r3 801045c: 68fb ldr r3, [r7, #12] 801045e: 4013 ands r3, r2 8010460: 2b00 cmp r3, #0 8010462: f000 80dd beq.w 8010620 8010466: 68bb ldr r3, [r7, #8] 8010468: f003 0302 and.w r3, r3, #2 801046c: 2b00 cmp r3, #0 801046e: f000 80d7 beq.w 8010620 { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8010472: 687b ldr r3, [r7, #4] 8010474: 681b ldr r3, [r3, #0] 8010476: 681b ldr r3, [r3, #0] 8010478: f003 0320 and.w r3, r3, #32 801047c: 2b00 cmp r3, #0 801047e: d10b bne.n 8010498 { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 8010480: 687b ldr r3, [r7, #4] 8010482: 681b ldr r3, [r3, #0] 8010484: 681a ldr r2, [r3, #0] 8010486: 687b ldr r3, [r7, #4] 8010488: 681b ldr r3, [r3, #0] 801048a: f022 020a bic.w r2, r2, #10 801048e: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8010490: 687b ldr r3, [r7, #4] 8010492: 2201 movs r2, #1 8010494: f883 2021 strb.w r2, [r3, #33] @ 0x21 } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 8010498: 687b ldr r3, [r7, #4] 801049a: 681b ldr r3, [r3, #0] 801049c: 461a mov r2, r3 801049e: 4b7b ldr r3, [pc, #492] @ (801068c ) 80104a0: 429a cmp r2, r3 80104a2: d958 bls.n 8010556 80104a4: 687b ldr r3, [r7, #4] 80104a6: 681b ldr r3, [r3, #0] 80104a8: 4a79 ldr r2, [pc, #484] @ (8010690 ) 80104aa: 4293 cmp r3, r2 80104ac: d04f beq.n 801054e 80104ae: 687b ldr r3, [r7, #4] 80104b0: 681b ldr r3, [r3, #0] 80104b2: 4a78 ldr r2, [pc, #480] @ (8010694 ) 80104b4: 4293 cmp r3, r2 80104b6: d048 beq.n 801054a 80104b8: 687b ldr r3, [r7, #4] 80104ba: 681b ldr r3, [r3, #0] 80104bc: 4a76 ldr r2, [pc, #472] @ (8010698 ) 80104be: 4293 cmp r3, r2 80104c0: d040 beq.n 8010544 80104c2: 687b ldr r3, [r7, #4] 80104c4: 681b ldr r3, [r3, #0] 80104c6: 4a75 ldr r2, [pc, #468] @ (801069c ) 80104c8: 4293 cmp r3, r2 80104ca: d038 beq.n 801053e 80104cc: 687b ldr r3, [r7, #4] 80104ce: 681b ldr r3, [r3, #0] 80104d0: 4a73 ldr r2, [pc, #460] @ (80106a0 ) 80104d2: 4293 cmp r3, r2 80104d4: d030 beq.n 8010538 80104d6: 687b ldr r3, [r7, #4] 80104d8: 681b ldr r3, [r3, #0] 80104da: 4a72 ldr r2, [pc, #456] @ (80106a4 ) 80104dc: 4293 cmp r3, r2 80104de: d028 beq.n 8010532 80104e0: 687b ldr r3, [r7, #4] 80104e2: 681b ldr r3, [r3, #0] 80104e4: 4a69 ldr r2, [pc, #420] @ (801068c ) 80104e6: 4293 cmp r3, r2 80104e8: d020 beq.n 801052c 80104ea: 687b ldr r3, [r7, #4] 80104ec: 681b ldr r3, [r3, #0] 80104ee: 4a6e ldr r2, [pc, #440] @ (80106a8 ) 80104f0: 4293 cmp r3, r2 80104f2: d019 beq.n 8010528 80104f4: 687b ldr r3, [r7, #4] 80104f6: 681b ldr r3, [r3, #0] 80104f8: 4a6c ldr r2, [pc, #432] @ (80106ac ) 80104fa: 4293 cmp r3, r2 80104fc: d012 beq.n 8010524 80104fe: 687b ldr r3, [r7, #4] 8010500: 681b ldr r3, [r3, #0] 8010502: 4a6b ldr r2, [pc, #428] @ (80106b0 ) 8010504: 4293 cmp r3, r2 8010506: d00a beq.n 801051e 8010508: 687b ldr r3, [r7, #4] 801050a: 681b ldr r3, [r3, #0] 801050c: 4a69 ldr r2, [pc, #420] @ (80106b4 ) 801050e: 4293 cmp r3, r2 8010510: d102 bne.n 8010518 8010512: f44f 5300 mov.w r3, #8192 @ 0x2000 8010516: e01b b.n 8010550 8010518: f44f 3300 mov.w r3, #131072 @ 0x20000 801051c: e018 b.n 8010550 801051e: f44f 7300 mov.w r3, #512 @ 0x200 8010522: e015 b.n 8010550 8010524: 2320 movs r3, #32 8010526: e013 b.n 8010550 8010528: 2302 movs r3, #2 801052a: e011 b.n 8010550 801052c: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8010530: e00e b.n 8010550 8010532: f44f 1300 mov.w r3, #2097152 @ 0x200000 8010536: e00b b.n 8010550 8010538: f44f 3300 mov.w r3, #131072 @ 0x20000 801053c: e008 b.n 8010550 801053e: f44f 5300 mov.w r3, #8192 @ 0x2000 8010542: e005 b.n 8010550 8010544: f44f 7300 mov.w r3, #512 @ 0x200 8010548: e002 b.n 8010550 801054a: 2320 movs r3, #32 801054c: e000 b.n 8010550 801054e: 2302 movs r3, #2 8010550: 4a59 ldr r2, [pc, #356] @ (80106b8 ) 8010552: 6053 str r3, [r2, #4] 8010554: e057 b.n 8010606 8010556: 687b ldr r3, [r7, #4] 8010558: 681b ldr r3, [r3, #0] 801055a: 4a4d ldr r2, [pc, #308] @ (8010690 ) 801055c: 4293 cmp r3, r2 801055e: d04f beq.n 8010600 8010560: 687b ldr r3, [r7, #4] 8010562: 681b ldr r3, [r3, #0] 8010564: 4a4b ldr r2, [pc, #300] @ (8010694 ) 8010566: 4293 cmp r3, r2 8010568: d048 beq.n 80105fc 801056a: 687b ldr r3, [r7, #4] 801056c: 681b ldr r3, [r3, #0] 801056e: 4a4a ldr r2, [pc, #296] @ (8010698 ) 8010570: 4293 cmp r3, r2 8010572: d040 beq.n 80105f6 8010574: 687b ldr r3, [r7, #4] 8010576: 681b ldr r3, [r3, #0] 8010578: 4a48 ldr r2, [pc, #288] @ (801069c ) 801057a: 4293 cmp r3, r2 801057c: d038 beq.n 80105f0 801057e: 687b ldr r3, [r7, #4] 8010580: 681b ldr r3, [r3, #0] 8010582: 4a47 ldr r2, [pc, #284] @ (80106a0 ) 8010584: 4293 cmp r3, r2 8010586: d030 beq.n 80105ea 8010588: 687b ldr r3, [r7, #4] 801058a: 681b ldr r3, [r3, #0] 801058c: 4a45 ldr r2, [pc, #276] @ (80106a4 ) 801058e: 4293 cmp r3, r2 8010590: d028 beq.n 80105e4 8010592: 687b ldr r3, [r7, #4] 8010594: 681b ldr r3, [r3, #0] 8010596: 4a3d ldr r2, [pc, #244] @ (801068c ) 8010598: 4293 cmp r3, r2 801059a: d020 beq.n 80105de 801059c: 687b ldr r3, [r7, #4] 801059e: 681b ldr r3, [r3, #0] 80105a0: 4a41 ldr r2, [pc, #260] @ (80106a8 ) 80105a2: 4293 cmp r3, r2 80105a4: d019 beq.n 80105da 80105a6: 687b ldr r3, [r7, #4] 80105a8: 681b ldr r3, [r3, #0] 80105aa: 4a40 ldr r2, [pc, #256] @ (80106ac ) 80105ac: 4293 cmp r3, r2 80105ae: d012 beq.n 80105d6 80105b0: 687b ldr r3, [r7, #4] 80105b2: 681b ldr r3, [r3, #0] 80105b4: 4a3e ldr r2, [pc, #248] @ (80106b0 ) 80105b6: 4293 cmp r3, r2 80105b8: d00a beq.n 80105d0 80105ba: 687b ldr r3, [r7, #4] 80105bc: 681b ldr r3, [r3, #0] 80105be: 4a3d ldr r2, [pc, #244] @ (80106b4 ) 80105c0: 4293 cmp r3, r2 80105c2: d102 bne.n 80105ca 80105c4: f44f 5300 mov.w r3, #8192 @ 0x2000 80105c8: e01b b.n 8010602 80105ca: f44f 3300 mov.w r3, #131072 @ 0x20000 80105ce: e018 b.n 8010602 80105d0: f44f 7300 mov.w r3, #512 @ 0x200 80105d4: e015 b.n 8010602 80105d6: 2320 movs r3, #32 80105d8: e013 b.n 8010602 80105da: 2302 movs r3, #2 80105dc: e011 b.n 8010602 80105de: f04f 7300 mov.w r3, #33554432 @ 0x2000000 80105e2: e00e b.n 8010602 80105e4: f44f 1300 mov.w r3, #2097152 @ 0x200000 80105e8: e00b b.n 8010602 80105ea: f44f 3300 mov.w r3, #131072 @ 0x20000 80105ee: e008 b.n 8010602 80105f0: f44f 5300 mov.w r3, #8192 @ 0x2000 80105f4: e005 b.n 8010602 80105f6: f44f 7300 mov.w r3, #512 @ 0x200 80105fa: e002 b.n 8010602 80105fc: 2320 movs r3, #32 80105fe: e000 b.n 8010602 8010600: 2302 movs r3, #2 8010602: 4a2e ldr r2, [pc, #184] @ (80106bc ) 8010604: 6053 str r3, [r2, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 8010606: 687b ldr r3, [r7, #4] 8010608: 2200 movs r2, #0 801060a: f883 2020 strb.w r2, [r3, #32] if(hdma->XferCpltCallback != NULL) 801060e: 687b ldr r3, [r7, #4] 8010610: 6a9b ldr r3, [r3, #40] @ 0x28 8010612: 2b00 cmp r3, #0 8010614: d034 beq.n 8010680 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8010616: 687b ldr r3, [r7, #4] 8010618: 6a9b ldr r3, [r3, #40] @ 0x28 801061a: 6878 ldr r0, [r7, #4] 801061c: 4798 blx r3 if(hdma->XferCpltCallback != NULL) 801061e: e02f b.n 8010680 } } /* Transfer Error Interrupt management **************************************/ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) 8010620: 687b ldr r3, [r7, #4] 8010622: 6c1b ldr r3, [r3, #64] @ 0x40 8010624: 2208 movs r2, #8 8010626: 409a lsls r2, r3 8010628: 68fb ldr r3, [r7, #12] 801062a: 4013 ands r3, r2 801062c: 2b00 cmp r3, #0 801062e: d028 beq.n 8010682 8010630: 68bb ldr r3, [r7, #8] 8010632: f003 0308 and.w r3, r3, #8 8010636: 2b00 cmp r3, #0 8010638: d023 beq.n 8010682 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 801063a: 687b ldr r3, [r7, #4] 801063c: 681b ldr r3, [r3, #0] 801063e: 681a ldr r2, [r3, #0] 8010640: 687b ldr r3, [r7, #4] 8010642: 681b ldr r3, [r3, #0] 8010644: f022 020e bic.w r2, r2, #14 8010648: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 801064a: 687b ldr r3, [r7, #4] 801064c: 6c1a ldr r2, [r3, #64] @ 0x40 801064e: 687b ldr r3, [r7, #4] 8010650: 6bdb ldr r3, [r3, #60] @ 0x3c 8010652: 2101 movs r1, #1 8010654: fa01 f202 lsl.w r2, r1, r2 8010658: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 801065a: 687b ldr r3, [r7, #4] 801065c: 2201 movs r2, #1 801065e: 639a str r2, [r3, #56] @ 0x38 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8010660: 687b ldr r3, [r7, #4] 8010662: 2201 movs r2, #1 8010664: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8010668: 687b ldr r3, [r7, #4] 801066a: 2200 movs r2, #0 801066c: f883 2020 strb.w r2, [r3, #32] if (hdma->XferErrorCallback != NULL) 8010670: 687b ldr r3, [r7, #4] 8010672: 6b1b ldr r3, [r3, #48] @ 0x30 8010674: 2b00 cmp r3, #0 8010676: d004 beq.n 8010682 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8010678: 687b ldr r3, [r7, #4] 801067a: 6b1b ldr r3, [r3, #48] @ 0x30 801067c: 6878 ldr r0, [r7, #4] 801067e: 4798 blx r3 } } return; 8010680: bf00 nop 8010682: bf00 nop } 8010684: 3710 adds r7, #16 8010686: 46bd mov sp, r7 8010688: bd80 pop {r7, pc} 801068a: bf00 nop 801068c: 40020080 .word 0x40020080 8010690: 40020008 .word 0x40020008 8010694: 4002001c .word 0x4002001c 8010698: 40020030 .word 0x40020030 801069c: 40020044 .word 0x40020044 80106a0: 40020058 .word 0x40020058 80106a4: 4002006c .word 0x4002006c 80106a8: 40020408 .word 0x40020408 80106ac: 4002041c .word 0x4002041c 80106b0: 40020430 .word 0x40020430 80106b4: 40020444 .word 0x40020444 80106b8: 40020400 .word 0x40020400 80106bc: 40020000 .word 0x40020000 080106c0 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval DMA Error Code */ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { 80106c0: b480 push {r7} 80106c2: b083 sub sp, #12 80106c4: af00 add r7, sp, #0 80106c6: 6078 str r0, [r7, #4] return hdma->ErrorCode; 80106c8: 687b ldr r3, [r7, #4] 80106ca: 6b9b ldr r3, [r3, #56] @ 0x38 } 80106cc: 4618 mov r0, r3 80106ce: 370c adds r7, #12 80106d0: 46bd mov sp, r7 80106d2: bc80 pop {r7} 80106d4: 4770 bx lr 080106d6 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 80106d6: b480 push {r7} 80106d8: b085 sub sp, #20 80106da: af00 add r7, sp, #0 80106dc: 60f8 str r0, [r7, #12] 80106de: 60b9 str r1, [r7, #8] 80106e0: 607a str r2, [r7, #4] 80106e2: 603b str r3, [r7, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 80106e4: 68fb ldr r3, [r7, #12] 80106e6: 6c1a ldr r2, [r3, #64] @ 0x40 80106e8: 68fb ldr r3, [r7, #12] 80106ea: 6bdb ldr r3, [r3, #60] @ 0x3c 80106ec: 2101 movs r1, #1 80106ee: fa01 f202 lsl.w r2, r1, r2 80106f2: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 80106f4: 68fb ldr r3, [r7, #12] 80106f6: 681b ldr r3, [r3, #0] 80106f8: 683a ldr r2, [r7, #0] 80106fa: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 80106fc: 68fb ldr r3, [r7, #12] 80106fe: 685b ldr r3, [r3, #4] 8010700: 2b10 cmp r3, #16 8010702: d108 bne.n 8010716 { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 8010704: 68fb ldr r3, [r7, #12] 8010706: 681b ldr r3, [r3, #0] 8010708: 687a ldr r2, [r7, #4] 801070a: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; 801070c: 68fb ldr r3, [r7, #12] 801070e: 681b ldr r3, [r3, #0] 8010710: 68ba ldr r2, [r7, #8] 8010712: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } 8010714: e007 b.n 8010726 hdma->Instance->CPAR = SrcAddress; 8010716: 68fb ldr r3, [r7, #12] 8010718: 681b ldr r3, [r3, #0] 801071a: 68ba ldr r2, [r7, #8] 801071c: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; 801071e: 68fb ldr r3, [r7, #12] 8010720: 681b ldr r3, [r3, #0] 8010722: 687a ldr r2, [r7, #4] 8010724: 60da str r2, [r3, #12] } 8010726: bf00 nop 8010728: 3714 adds r7, #20 801072a: 46bd mov sp, r7 801072c: bc80 pop {r7} 801072e: 4770 bx lr 08010730 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8010730: b480 push {r7} 8010732: b08b sub sp, #44 @ 0x2c 8010734: af00 add r7, sp, #0 8010736: 6078 str r0, [r7, #4] 8010738: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 801073a: 2300 movs r3, #0 801073c: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 801073e: 2300 movs r3, #0 8010740: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8010742: e169 b.n 8010a18 { /* Get the IO position */ ioposition = (0x01uL << position); 8010744: 2201 movs r2, #1 8010746: 6a7b ldr r3, [r7, #36] @ 0x24 8010748: fa02 f303 lsl.w r3, r2, r3 801074c: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 801074e: 683b ldr r3, [r7, #0] 8010750: 681b ldr r3, [r3, #0] 8010752: 69fa ldr r2, [r7, #28] 8010754: 4013 ands r3, r2 8010756: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8010758: 69ba ldr r2, [r7, #24] 801075a: 69fb ldr r3, [r7, #28] 801075c: 429a cmp r2, r3 801075e: f040 8158 bne.w 8010a12 { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 8010762: 683b ldr r3, [r7, #0] 8010764: 685b ldr r3, [r3, #4] 8010766: 4a9a ldr r2, [pc, #616] @ (80109d0 ) 8010768: 4293 cmp r3, r2 801076a: d05e beq.n 801082a 801076c: 4a98 ldr r2, [pc, #608] @ (80109d0 ) 801076e: 4293 cmp r3, r2 8010770: d875 bhi.n 801085e 8010772: 4a98 ldr r2, [pc, #608] @ (80109d4 ) 8010774: 4293 cmp r3, r2 8010776: d058 beq.n 801082a 8010778: 4a96 ldr r2, [pc, #600] @ (80109d4 ) 801077a: 4293 cmp r3, r2 801077c: d86f bhi.n 801085e 801077e: 4a96 ldr r2, [pc, #600] @ (80109d8 ) 8010780: 4293 cmp r3, r2 8010782: d052 beq.n 801082a 8010784: 4a94 ldr r2, [pc, #592] @ (80109d8 ) 8010786: 4293 cmp r3, r2 8010788: d869 bhi.n 801085e 801078a: 4a94 ldr r2, [pc, #592] @ (80109dc ) 801078c: 4293 cmp r3, r2 801078e: d04c beq.n 801082a 8010790: 4a92 ldr r2, [pc, #584] @ (80109dc ) 8010792: 4293 cmp r3, r2 8010794: d863 bhi.n 801085e 8010796: 4a92 ldr r2, [pc, #584] @ (80109e0 ) 8010798: 4293 cmp r3, r2 801079a: d046 beq.n 801082a 801079c: 4a90 ldr r2, [pc, #576] @ (80109e0 ) 801079e: 4293 cmp r3, r2 80107a0: d85d bhi.n 801085e 80107a2: 2b12 cmp r3, #18 80107a4: d82a bhi.n 80107fc 80107a6: 2b12 cmp r3, #18 80107a8: d859 bhi.n 801085e 80107aa: a201 add r2, pc, #4 @ (adr r2, 80107b0 ) 80107ac: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80107b0: 0801082b .word 0x0801082b 80107b4: 08010805 .word 0x08010805 80107b8: 08010817 .word 0x08010817 80107bc: 08010859 .word 0x08010859 80107c0: 0801085f .word 0x0801085f 80107c4: 0801085f .word 0x0801085f 80107c8: 0801085f .word 0x0801085f 80107cc: 0801085f .word 0x0801085f 80107d0: 0801085f .word 0x0801085f 80107d4: 0801085f .word 0x0801085f 80107d8: 0801085f .word 0x0801085f 80107dc: 0801085f .word 0x0801085f 80107e0: 0801085f .word 0x0801085f 80107e4: 0801085f .word 0x0801085f 80107e8: 0801085f .word 0x0801085f 80107ec: 0801085f .word 0x0801085f 80107f0: 0801085f .word 0x0801085f 80107f4: 0801080d .word 0x0801080d 80107f8: 08010821 .word 0x08010821 80107fc: 4a79 ldr r2, [pc, #484] @ (80109e4 ) 80107fe: 4293 cmp r3, r2 8010800: d013 beq.n 801082a config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8010802: e02c b.n 801085e config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8010804: 683b ldr r3, [r7, #0] 8010806: 68db ldr r3, [r3, #12] 8010808: 623b str r3, [r7, #32] break; 801080a: e029 b.n 8010860 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 801080c: 683b ldr r3, [r7, #0] 801080e: 68db ldr r3, [r3, #12] 8010810: 3304 adds r3, #4 8010812: 623b str r3, [r7, #32] break; 8010814: e024 b.n 8010860 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8010816: 683b ldr r3, [r7, #0] 8010818: 68db ldr r3, [r3, #12] 801081a: 3308 adds r3, #8 801081c: 623b str r3, [r7, #32] break; 801081e: e01f b.n 8010860 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8010820: 683b ldr r3, [r7, #0] 8010822: 68db ldr r3, [r3, #12] 8010824: 330c adds r3, #12 8010826: 623b str r3, [r7, #32] break; 8010828: e01a b.n 8010860 if (GPIO_Init->Pull == GPIO_NOPULL) 801082a: 683b ldr r3, [r7, #0] 801082c: 689b ldr r3, [r3, #8] 801082e: 2b00 cmp r3, #0 8010830: d102 bne.n 8010838 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8010832: 2304 movs r3, #4 8010834: 623b str r3, [r7, #32] break; 8010836: e013 b.n 8010860 else if (GPIO_Init->Pull == GPIO_PULLUP) 8010838: 683b ldr r3, [r7, #0] 801083a: 689b ldr r3, [r3, #8] 801083c: 2b01 cmp r3, #1 801083e: d105 bne.n 801084c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8010840: 2308 movs r3, #8 8010842: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8010844: 687b ldr r3, [r7, #4] 8010846: 69fa ldr r2, [r7, #28] 8010848: 611a str r2, [r3, #16] break; 801084a: e009 b.n 8010860 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 801084c: 2308 movs r3, #8 801084e: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 8010850: 687b ldr r3, [r7, #4] 8010852: 69fa ldr r2, [r7, #28] 8010854: 615a str r2, [r3, #20] break; 8010856: e003 b.n 8010860 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8010858: 2300 movs r3, #0 801085a: 623b str r3, [r7, #32] break; 801085c: e000 b.n 8010860 break; 801085e: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8010860: 69bb ldr r3, [r7, #24] 8010862: 2bff cmp r3, #255 @ 0xff 8010864: d801 bhi.n 801086a 8010866: 687b ldr r3, [r7, #4] 8010868: e001 b.n 801086e 801086a: 687b ldr r3, [r7, #4] 801086c: 3304 adds r3, #4 801086e: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8010870: 69bb ldr r3, [r7, #24] 8010872: 2bff cmp r3, #255 @ 0xff 8010874: d802 bhi.n 801087c 8010876: 6a7b ldr r3, [r7, #36] @ 0x24 8010878: 009b lsls r3, r3, #2 801087a: e002 b.n 8010882 801087c: 6a7b ldr r3, [r7, #36] @ 0x24 801087e: 3b08 subs r3, #8 8010880: 009b lsls r3, r3, #2 8010882: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8010884: 697b ldr r3, [r7, #20] 8010886: 681a ldr r2, [r3, #0] 8010888: 210f movs r1, #15 801088a: 693b ldr r3, [r7, #16] 801088c: fa01 f303 lsl.w r3, r1, r3 8010890: 43db mvns r3, r3 8010892: 401a ands r2, r3 8010894: 6a39 ldr r1, [r7, #32] 8010896: 693b ldr r3, [r7, #16] 8010898: fa01 f303 lsl.w r3, r1, r3 801089c: 431a orrs r2, r3 801089e: 697b ldr r3, [r7, #20] 80108a0: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 80108a2: 683b ldr r3, [r7, #0] 80108a4: 685b ldr r3, [r3, #4] 80108a6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80108aa: 2b00 cmp r3, #0 80108ac: f000 80b1 beq.w 8010a12 { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 80108b0: 4b4d ldr r3, [pc, #308] @ (80109e8 ) 80108b2: 699b ldr r3, [r3, #24] 80108b4: 4a4c ldr r2, [pc, #304] @ (80109e8 ) 80108b6: f043 0301 orr.w r3, r3, #1 80108ba: 6193 str r3, [r2, #24] 80108bc: 4b4a ldr r3, [pc, #296] @ (80109e8 ) 80108be: 699b ldr r3, [r3, #24] 80108c0: f003 0301 and.w r3, r3, #1 80108c4: 60bb str r3, [r7, #8] 80108c6: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 80108c8: 4a48 ldr r2, [pc, #288] @ (80109ec ) 80108ca: 6a7b ldr r3, [r7, #36] @ 0x24 80108cc: 089b lsrs r3, r3, #2 80108ce: 3302 adds r3, #2 80108d0: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80108d4: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 80108d6: 6a7b ldr r3, [r7, #36] @ 0x24 80108d8: f003 0303 and.w r3, r3, #3 80108dc: 009b lsls r3, r3, #2 80108de: 220f movs r2, #15 80108e0: fa02 f303 lsl.w r3, r2, r3 80108e4: 43db mvns r3, r3 80108e6: 68fa ldr r2, [r7, #12] 80108e8: 4013 ands r3, r2 80108ea: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 80108ec: 687b ldr r3, [r7, #4] 80108ee: 4a40 ldr r2, [pc, #256] @ (80109f0 ) 80108f0: 4293 cmp r3, r2 80108f2: d013 beq.n 801091c 80108f4: 687b ldr r3, [r7, #4] 80108f6: 4a3f ldr r2, [pc, #252] @ (80109f4 ) 80108f8: 4293 cmp r3, r2 80108fa: d00d beq.n 8010918 80108fc: 687b ldr r3, [r7, #4] 80108fe: 4a3e ldr r2, [pc, #248] @ (80109f8 ) 8010900: 4293 cmp r3, r2 8010902: d007 beq.n 8010914 8010904: 687b ldr r3, [r7, #4] 8010906: 4a3d ldr r2, [pc, #244] @ (80109fc ) 8010908: 4293 cmp r3, r2 801090a: d101 bne.n 8010910 801090c: 2303 movs r3, #3 801090e: e006 b.n 801091e 8010910: 2304 movs r3, #4 8010912: e004 b.n 801091e 8010914: 2302 movs r3, #2 8010916: e002 b.n 801091e 8010918: 2301 movs r3, #1 801091a: e000 b.n 801091e 801091c: 2300 movs r3, #0 801091e: 6a7a ldr r2, [r7, #36] @ 0x24 8010920: f002 0203 and.w r2, r2, #3 8010924: 0092 lsls r2, r2, #2 8010926: 4093 lsls r3, r2 8010928: 68fa ldr r2, [r7, #12] 801092a: 4313 orrs r3, r2 801092c: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 801092e: 492f ldr r1, [pc, #188] @ (80109ec ) 8010930: 6a7b ldr r3, [r7, #36] @ 0x24 8010932: 089b lsrs r3, r3, #2 8010934: 3302 adds r3, #2 8010936: 68fa ldr r2, [r7, #12] 8010938: f841 2023 str.w r2, [r1, r3, lsl #2] /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 801093c: 683b ldr r3, [r7, #0] 801093e: 685b ldr r3, [r3, #4] 8010940: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8010944: 2b00 cmp r3, #0 8010946: d006 beq.n 8010956 { SET_BIT(EXTI->RTSR, iocurrent); 8010948: 4b2d ldr r3, [pc, #180] @ (8010a00 ) 801094a: 689a ldr r2, [r3, #8] 801094c: 492c ldr r1, [pc, #176] @ (8010a00 ) 801094e: 69bb ldr r3, [r7, #24] 8010950: 4313 orrs r3, r2 8010952: 608b str r3, [r1, #8] 8010954: e006 b.n 8010964 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8010956: 4b2a ldr r3, [pc, #168] @ (8010a00 ) 8010958: 689a ldr r2, [r3, #8] 801095a: 69bb ldr r3, [r7, #24] 801095c: 43db mvns r3, r3 801095e: 4928 ldr r1, [pc, #160] @ (8010a00 ) 8010960: 4013 ands r3, r2 8010962: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8010964: 683b ldr r3, [r7, #0] 8010966: 685b ldr r3, [r3, #4] 8010968: f403 1300 and.w r3, r3, #2097152 @ 0x200000 801096c: 2b00 cmp r3, #0 801096e: d006 beq.n 801097e { SET_BIT(EXTI->FTSR, iocurrent); 8010970: 4b23 ldr r3, [pc, #140] @ (8010a00 ) 8010972: 68da ldr r2, [r3, #12] 8010974: 4922 ldr r1, [pc, #136] @ (8010a00 ) 8010976: 69bb ldr r3, [r7, #24] 8010978: 4313 orrs r3, r2 801097a: 60cb str r3, [r1, #12] 801097c: e006 b.n 801098c } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 801097e: 4b20 ldr r3, [pc, #128] @ (8010a00 ) 8010980: 68da ldr r2, [r3, #12] 8010982: 69bb ldr r3, [r7, #24] 8010984: 43db mvns r3, r3 8010986: 491e ldr r1, [pc, #120] @ (8010a00 ) 8010988: 4013 ands r3, r2 801098a: 60cb str r3, [r1, #12] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 801098c: 683b ldr r3, [r7, #0] 801098e: 685b ldr r3, [r3, #4] 8010990: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010994: 2b00 cmp r3, #0 8010996: d006 beq.n 80109a6 { SET_BIT(EXTI->EMR, iocurrent); 8010998: 4b19 ldr r3, [pc, #100] @ (8010a00 ) 801099a: 685a ldr r2, [r3, #4] 801099c: 4918 ldr r1, [pc, #96] @ (8010a00 ) 801099e: 69bb ldr r3, [r7, #24] 80109a0: 4313 orrs r3, r2 80109a2: 604b str r3, [r1, #4] 80109a4: e006 b.n 80109b4 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 80109a6: 4b16 ldr r3, [pc, #88] @ (8010a00 ) 80109a8: 685a ldr r2, [r3, #4] 80109aa: 69bb ldr r3, [r7, #24] 80109ac: 43db mvns r3, r3 80109ae: 4914 ldr r1, [pc, #80] @ (8010a00 ) 80109b0: 4013 ands r3, r2 80109b2: 604b str r3, [r1, #4] } /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 80109b4: 683b ldr r3, [r7, #0] 80109b6: 685b ldr r3, [r3, #4] 80109b8: f403 3380 and.w r3, r3, #65536 @ 0x10000 80109bc: 2b00 cmp r3, #0 80109be: d021 beq.n 8010a04 { SET_BIT(EXTI->IMR, iocurrent); 80109c0: 4b0f ldr r3, [pc, #60] @ (8010a00 ) 80109c2: 681a ldr r2, [r3, #0] 80109c4: 490e ldr r1, [pc, #56] @ (8010a00 ) 80109c6: 69bb ldr r3, [r7, #24] 80109c8: 4313 orrs r3, r2 80109ca: 600b str r3, [r1, #0] 80109cc: e021 b.n 8010a12 80109ce: bf00 nop 80109d0: 10320000 .word 0x10320000 80109d4: 10310000 .word 0x10310000 80109d8: 10220000 .word 0x10220000 80109dc: 10210000 .word 0x10210000 80109e0: 10120000 .word 0x10120000 80109e4: 10110000 .word 0x10110000 80109e8: 40021000 .word 0x40021000 80109ec: 40010000 .word 0x40010000 80109f0: 40010800 .word 0x40010800 80109f4: 40010c00 .word 0x40010c00 80109f8: 40011000 .word 0x40011000 80109fc: 40011400 .word 0x40011400 8010a00: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8010a04: 4b0b ldr r3, [pc, #44] @ (8010a34 ) 8010a06: 681a ldr r2, [r3, #0] 8010a08: 69bb ldr r3, [r7, #24] 8010a0a: 43db mvns r3, r3 8010a0c: 4909 ldr r1, [pc, #36] @ (8010a34 ) 8010a0e: 4013 ands r3, r2 8010a10: 600b str r3, [r1, #0] } } } position++; 8010a12: 6a7b ldr r3, [r7, #36] @ 0x24 8010a14: 3301 adds r3, #1 8010a16: 627b str r3, [r7, #36] @ 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8010a18: 683b ldr r3, [r7, #0] 8010a1a: 681a ldr r2, [r3, #0] 8010a1c: 6a7b ldr r3, [r7, #36] @ 0x24 8010a1e: fa22 f303 lsr.w r3, r2, r3 8010a22: 2b00 cmp r3, #0 8010a24: f47f ae8e bne.w 8010744 } } 8010a28: bf00 nop 8010a2a: bf00 nop 8010a2c: 372c adds r7, #44 @ 0x2c 8010a2e: 46bd mov sp, r7 8010a30: bc80 pop {r7} 8010a32: 4770 bx lr 8010a34: 40010400 .word 0x40010400 08010a38 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8010a38: b480 push {r7} 8010a3a: b085 sub sp, #20 8010a3c: af00 add r7, sp, #0 8010a3e: 6078 str r0, [r7, #4] 8010a40: 460b mov r3, r1 8010a42: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8010a44: 687b ldr r3, [r7, #4] 8010a46: 689a ldr r2, [r3, #8] 8010a48: 887b ldrh r3, [r7, #2] 8010a4a: 4013 ands r3, r2 8010a4c: 2b00 cmp r3, #0 8010a4e: d002 beq.n 8010a56 { bitstatus = GPIO_PIN_SET; 8010a50: 2301 movs r3, #1 8010a52: 73fb strb r3, [r7, #15] 8010a54: e001 b.n 8010a5a } else { bitstatus = GPIO_PIN_RESET; 8010a56: 2300 movs r3, #0 8010a58: 73fb strb r3, [r7, #15] } return bitstatus; 8010a5a: 7bfb ldrb r3, [r7, #15] } 8010a5c: 4618 mov r0, r3 8010a5e: 3714 adds r7, #20 8010a60: 46bd mov sp, r7 8010a62: bc80 pop {r7} 8010a64: 4770 bx lr 08010a66 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8010a66: b480 push {r7} 8010a68: b083 sub sp, #12 8010a6a: af00 add r7, sp, #0 8010a6c: 6078 str r0, [r7, #4] 8010a6e: 460b mov r3, r1 8010a70: 807b strh r3, [r7, #2] 8010a72: 4613 mov r3, r2 8010a74: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8010a76: 787b ldrb r3, [r7, #1] 8010a78: 2b00 cmp r3, #0 8010a7a: d003 beq.n 8010a84 { GPIOx->BSRR = GPIO_Pin; 8010a7c: 887a ldrh r2, [r7, #2] 8010a7e: 687b ldr r3, [r7, #4] 8010a80: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8010a82: e003 b.n 8010a8c GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8010a84: 887b ldrh r3, [r7, #2] 8010a86: 041a lsls r2, r3, #16 8010a88: 687b ldr r3, [r7, #4] 8010a8a: 611a str r2, [r3, #16] } 8010a8c: bf00 nop 8010a8e: 370c adds r7, #12 8010a90: 46bd mov sp, r7 8010a92: bc80 pop {r7} 8010a94: 4770 bx lr ... 08010a98 : * @note If the HSE divided by 128 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 8010a98: b480 push {r7} 8010a9a: af00 add r7, sp, #0 /* Enable access to RTC and backup registers */ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 8010a9c: 4b03 ldr r3, [pc, #12] @ (8010aac ) 8010a9e: 2201 movs r2, #1 8010aa0: 601a str r2, [r3, #0] } 8010aa2: bf00 nop 8010aa4: 46bd mov sp, r7 8010aa6: bc80 pop {r7} 8010aa8: 4770 bx lr 8010aaa: bf00 nop 8010aac: 420e0020 .word 0x420e0020 08010ab0 : * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval HAL_StatusTypeDef */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { 8010ab0: b580 push {r7, lr} 8010ab2: b082 sub sp, #8 8010ab4: af00 add r7, sp, #0 uint32_t tickstart; /* Get Start Tick */ tickstart = HAL_GetTick(); 8010ab6: f7fd fc3f bl 800e338 8010aba: 6078 str r0, [r7, #4] /* Set HSION bit */ SET_BIT(RCC->CR, RCC_CR_HSION); 8010abc: 4b60 ldr r3, [pc, #384] @ (8010c40 ) 8010abe: 681b ldr r3, [r3, #0] 8010ac0: 4a5f ldr r2, [pc, #380] @ (8010c40 ) 8010ac2: f043 0301 orr.w r3, r3, #1 8010ac6: 6013 str r3, [r2, #0] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 8010ac8: e008 b.n 8010adc { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8010aca: f7fd fc35 bl 800e338 8010ace: 4602 mov r2, r0 8010ad0: 687b ldr r3, [r7, #4] 8010ad2: 1ad3 subs r3, r2, r3 8010ad4: 2b02 cmp r3, #2 8010ad6: d901 bls.n 8010adc { return HAL_TIMEOUT; 8010ad8: 2303 movs r3, #3 8010ada: e0ac b.n 8010c36 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 8010adc: 4b58 ldr r3, [pc, #352] @ (8010c40 ) 8010ade: 681b ldr r3, [r3, #0] 8010ae0: f003 0302 and.w r3, r3, #2 8010ae4: 2b00 cmp r3, #0 8010ae6: d0f0 beq.n 8010aca } } /* Set HSITRIM bits to the reset value */ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); 8010ae8: 4b55 ldr r3, [pc, #340] @ (8010c40 ) 8010aea: 681b ldr r3, [r3, #0] 8010aec: f023 03f8 bic.w r3, r3, #248 @ 0xf8 8010af0: 4a53 ldr r2, [pc, #332] @ (8010c40 ) 8010af2: f043 0380 orr.w r3, r3, #128 @ 0x80 8010af6: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010af8: f7fd fc1e bl 800e338 8010afc: 6078 str r0, [r7, #4] /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); 8010afe: 4b50 ldr r3, [pc, #320] @ (8010c40 ) 8010b00: 2200 movs r2, #0 8010b02: 605a str r2, [r3, #4] /* Wait till clock switch is ready */ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 8010b04: e00a b.n 8010b1c { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8010b06: f7fd fc17 bl 800e338 8010b0a: 4602 mov r2, r0 8010b0c: 687b ldr r3, [r7, #4] 8010b0e: 1ad3 subs r3, r2, r3 8010b10: f241 3288 movw r2, #5000 @ 0x1388 8010b14: 4293 cmp r3, r2 8010b16: d901 bls.n 8010b1c { return HAL_TIMEOUT; 8010b18: 2303 movs r3, #3 8010b1a: e08c b.n 8010c36 while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 8010b1c: 4b48 ldr r3, [pc, #288] @ (8010c40 ) 8010b1e: 685b ldr r3, [r3, #4] 8010b20: f003 030c and.w r3, r3, #12 8010b24: 2b00 cmp r3, #0 8010b26: d1ee bne.n 8010b06 } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; 8010b28: 4b46 ldr r3, [pc, #280] @ (8010c44 ) 8010b2a: 4a47 ldr r2, [pc, #284] @ (8010c48 ) 8010b2c: 601a str r2, [r3, #0] /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 8010b2e: 4b47 ldr r3, [pc, #284] @ (8010c4c ) 8010b30: 681b ldr r3, [r3, #0] 8010b32: 4618 mov r0, r3 8010b34: f7fd fbbe bl 800e2b4 8010b38: 4603 mov r3, r0 8010b3a: 2b00 cmp r3, #0 8010b3c: d001 beq.n 8010b42 { return HAL_ERROR; 8010b3e: 2301 movs r3, #1 8010b40: e079 b.n 8010c36 } /* Get Start Tick */ tickstart = HAL_GetTick(); 8010b42: f7fd fbf9 bl 800e338 8010b46: 6078 str r0, [r7, #4] /* Second step is to clear PLLON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 8010b48: 4b3d ldr r3, [pc, #244] @ (8010c40 ) 8010b4a: 681b ldr r3, [r3, #0] 8010b4c: 4a3c ldr r2, [pc, #240] @ (8010c40 ) 8010b4e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 8010b52: 6013 str r3, [r2, #0] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 8010b54: e008 b.n 8010b68 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8010b56: f7fd fbef bl 800e338 8010b5a: 4602 mov r2, r0 8010b5c: 687b ldr r3, [r7, #4] 8010b5e: 1ad3 subs r3, r2, r3 8010b60: 2b02 cmp r3, #2 8010b62: d901 bls.n 8010b68 { return HAL_TIMEOUT; 8010b64: 2303 movs r3, #3 8010b66: e066 b.n 8010c36 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 8010b68: 4b35 ldr r3, [pc, #212] @ (8010c40 ) 8010b6a: 681b ldr r3, [r3, #0] 8010b6c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8010b70: 2b00 cmp r3, #0 8010b72: d1f0 bne.n 8010b56 } } /* Ensure to reset PLLSRC and PLLMUL bits */ CLEAR_REG(RCC->CFGR); 8010b74: 4b32 ldr r3, [pc, #200] @ (8010c40 ) 8010b76: 2200 movs r2, #0 8010b78: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010b7a: f7fd fbdd bl 800e338 8010b7e: 6078 str r0, [r7, #4] /* Reset HSEON & CSSON bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON); 8010b80: 4b2f ldr r3, [pc, #188] @ (8010c40 ) 8010b82: 681b ldr r3, [r3, #0] 8010b84: 4a2e ldr r2, [pc, #184] @ (8010c40 ) 8010b86: f423 2310 bic.w r3, r3, #589824 @ 0x90000 8010b8a: 6013 str r3, [r2, #0] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 8010b8c: e008 b.n 8010ba0 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8010b8e: f7fd fbd3 bl 800e338 8010b92: 4602 mov r2, r0 8010b94: 687b ldr r3, [r7, #4] 8010b96: 1ad3 subs r3, r2, r3 8010b98: 2b64 cmp r3, #100 @ 0x64 8010b9a: d901 bls.n 8010ba0 { return HAL_TIMEOUT; 8010b9c: 2303 movs r3, #3 8010b9e: e04a b.n 8010c36 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 8010ba0: 4b27 ldr r3, [pc, #156] @ (8010c40 ) 8010ba2: 681b ldr r3, [r3, #0] 8010ba4: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010ba8: 2b00 cmp r3, #0 8010baa: d1f0 bne.n 8010b8e } } /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 8010bac: 4b24 ldr r3, [pc, #144] @ (8010c40 ) 8010bae: 681b ldr r3, [r3, #0] 8010bb0: 4a23 ldr r2, [pc, #140] @ (8010c40 ) 8010bb2: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010bb6: 6013 str r3, [r2, #0] #if defined(RCC_PLL2_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 8010bb8: f7fd fbbe bl 800e338 8010bbc: 6078 str r0, [r7, #4] /* Clear PLL2ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); 8010bbe: 4b20 ldr r3, [pc, #128] @ (8010c40 ) 8010bc0: 681b ldr r3, [r3, #0] 8010bc2: 4a1f ldr r2, [pc, #124] @ (8010c40 ) 8010bc4: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8010bc8: 6013 str r3, [r2, #0] /* Wait till PLL2 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 8010bca: e008 b.n 8010bde { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8010bcc: f7fd fbb4 bl 800e338 8010bd0: 4602 mov r2, r0 8010bd2: 687b ldr r3, [r7, #4] 8010bd4: 1ad3 subs r3, r2, r3 8010bd6: 2b64 cmp r3, #100 @ 0x64 8010bd8: d901 bls.n 8010bde { return HAL_TIMEOUT; 8010bda: 2303 movs r3, #3 8010bdc: e02b b.n 8010c36 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 8010bde: 4b18 ldr r3, [pc, #96] @ (8010c40 ) 8010be0: 681b ldr r3, [r3, #0] 8010be2: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8010be6: 2b00 cmp r3, #0 8010be8: d1f0 bne.n 8010bcc } #endif /* RCC_PLL2_SUPPORT */ #if defined(RCC_PLLI2S_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 8010bea: f7fd fba5 bl 800e338 8010bee: 6078 str r0, [r7, #4] /* Clear PLL3ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); 8010bf0: 4b13 ldr r3, [pc, #76] @ (8010c40 ) 8010bf2: 681b ldr r3, [r3, #0] 8010bf4: 4a12 ldr r2, [pc, #72] @ (8010c40 ) 8010bf6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8010bfa: 6013 str r3, [r2, #0] /* Wait till PLL3 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 8010bfc: e008 b.n 8010c10 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8010bfe: f7fd fb9b bl 800e338 8010c02: 4602 mov r2, r0 8010c04: 687b ldr r3, [r7, #4] 8010c06: 1ad3 subs r3, r2, r3 8010c08: 2b64 cmp r3, #100 @ 0x64 8010c0a: d901 bls.n 8010c10 { return HAL_TIMEOUT; 8010c0c: 2303 movs r3, #3 8010c0e: e012 b.n 8010c36 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 8010c10: 4b0b ldr r3, [pc, #44] @ (8010c40 ) 8010c12: 681b ldr r3, [r3, #0] 8010c14: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8010c18: 2b00 cmp r3, #0 8010c1a: d1f0 bne.n 8010bfe } #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_CFGR2_PREDIV1) /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); 8010c1c: 4b08 ldr r3, [pc, #32] @ (8010c40 ) 8010c1e: 2200 movs r2, #0 8010c20: 62da str r2, [r3, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1 */ /* Reset all CSR flags */ SET_BIT(RCC->CSR, RCC_CSR_RMVF); 8010c22: 4b07 ldr r3, [pc, #28] @ (8010c40 ) 8010c24: 6a5b ldr r3, [r3, #36] @ 0x24 8010c26: 4a06 ldr r2, [pc, #24] @ (8010c40 ) 8010c28: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8010c2c: 6253 str r3, [r2, #36] @ 0x24 /* Disable all interrupts */ CLEAR_REG(RCC->CIR); 8010c2e: 4b04 ldr r3, [pc, #16] @ (8010c40 ) 8010c30: 2200 movs r2, #0 8010c32: 609a str r2, [r3, #8] return HAL_OK; 8010c34: 2300 movs r3, #0 } 8010c36: 4618 mov r0, r3 8010c38: 3708 adds r7, #8 8010c3a: 46bd mov sp, r7 8010c3c: bd80 pop {r7, pc} 8010c3e: bf00 nop 8010c40: 40021000 .word 0x40021000 8010c44: 20000084 .word 0x20000084 8010c48: 007a1200 .word 0x007a1200 8010c4c: 20000088 .word 0x20000088 08010c50 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8010c50: b580 push {r7, lr} 8010c52: b086 sub sp, #24 8010c54: af00 add r7, sp, #0 8010c56: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8010c58: 687b ldr r3, [r7, #4] 8010c5a: 2b00 cmp r3, #0 8010c5c: d101 bne.n 8010c62 { return HAL_ERROR; 8010c5e: 2301 movs r3, #1 8010c60: e304 b.n 801126c /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8010c62: 687b ldr r3, [r7, #4] 8010c64: 681b ldr r3, [r3, #0] 8010c66: f003 0301 and.w r3, r3, #1 8010c6a: 2b00 cmp r3, #0 8010c6c: f000 8087 beq.w 8010d7e { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8010c70: 4b92 ldr r3, [pc, #584] @ (8010ebc ) 8010c72: 685b ldr r3, [r3, #4] 8010c74: f003 030c and.w r3, r3, #12 8010c78: 2b04 cmp r3, #4 8010c7a: d00c beq.n 8010c96 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8010c7c: 4b8f ldr r3, [pc, #572] @ (8010ebc ) 8010c7e: 685b ldr r3, [r3, #4] 8010c80: f003 030c and.w r3, r3, #12 8010c84: 2b08 cmp r3, #8 8010c86: d112 bne.n 8010cae 8010c88: 4b8c ldr r3, [pc, #560] @ (8010ebc ) 8010c8a: 685b ldr r3, [r3, #4] 8010c8c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010c90: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010c94: d10b bne.n 8010cae { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8010c96: 4b89 ldr r3, [pc, #548] @ (8010ebc ) 8010c98: 681b ldr r3, [r3, #0] 8010c9a: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010c9e: 2b00 cmp r3, #0 8010ca0: d06c beq.n 8010d7c 8010ca2: 687b ldr r3, [r7, #4] 8010ca4: 689b ldr r3, [r3, #8] 8010ca6: 2b00 cmp r3, #0 8010ca8: d168 bne.n 8010d7c { return HAL_ERROR; 8010caa: 2301 movs r3, #1 8010cac: e2de b.n 801126c } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8010cae: 687b ldr r3, [r7, #4] 8010cb0: 689b ldr r3, [r3, #8] 8010cb2: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010cb6: d106 bne.n 8010cc6 8010cb8: 4b80 ldr r3, [pc, #512] @ (8010ebc ) 8010cba: 681b ldr r3, [r3, #0] 8010cbc: 4a7f ldr r2, [pc, #508] @ (8010ebc ) 8010cbe: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8010cc2: 6013 str r3, [r2, #0] 8010cc4: e02e b.n 8010d24 8010cc6: 687b ldr r3, [r7, #4] 8010cc8: 689b ldr r3, [r3, #8] 8010cca: 2b00 cmp r3, #0 8010ccc: d10c bne.n 8010ce8 8010cce: 4b7b ldr r3, [pc, #492] @ (8010ebc ) 8010cd0: 681b ldr r3, [r3, #0] 8010cd2: 4a7a ldr r2, [pc, #488] @ (8010ebc ) 8010cd4: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8010cd8: 6013 str r3, [r2, #0] 8010cda: 4b78 ldr r3, [pc, #480] @ (8010ebc ) 8010cdc: 681b ldr r3, [r3, #0] 8010cde: 4a77 ldr r2, [pc, #476] @ (8010ebc ) 8010ce0: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010ce4: 6013 str r3, [r2, #0] 8010ce6: e01d b.n 8010d24 8010ce8: 687b ldr r3, [r7, #4] 8010cea: 689b ldr r3, [r3, #8] 8010cec: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8010cf0: d10c bne.n 8010d0c 8010cf2: 4b72 ldr r3, [pc, #456] @ (8010ebc ) 8010cf4: 681b ldr r3, [r3, #0] 8010cf6: 4a71 ldr r2, [pc, #452] @ (8010ebc ) 8010cf8: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8010cfc: 6013 str r3, [r2, #0] 8010cfe: 4b6f ldr r3, [pc, #444] @ (8010ebc ) 8010d00: 681b ldr r3, [r3, #0] 8010d02: 4a6e ldr r2, [pc, #440] @ (8010ebc ) 8010d04: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8010d08: 6013 str r3, [r2, #0] 8010d0a: e00b b.n 8010d24 8010d0c: 4b6b ldr r3, [pc, #428] @ (8010ebc ) 8010d0e: 681b ldr r3, [r3, #0] 8010d10: 4a6a ldr r2, [pc, #424] @ (8010ebc ) 8010d12: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8010d16: 6013 str r3, [r2, #0] 8010d18: 4b68 ldr r3, [pc, #416] @ (8010ebc ) 8010d1a: 681b ldr r3, [r3, #0] 8010d1c: 4a67 ldr r2, [pc, #412] @ (8010ebc ) 8010d1e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010d22: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8010d24: 687b ldr r3, [r7, #4] 8010d26: 689b ldr r3, [r3, #8] 8010d28: 2b00 cmp r3, #0 8010d2a: d013 beq.n 8010d54 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010d2c: f7fd fb04 bl 800e338 8010d30: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8010d32: e008 b.n 8010d46 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8010d34: f7fd fb00 bl 800e338 8010d38: 4602 mov r2, r0 8010d3a: 693b ldr r3, [r7, #16] 8010d3c: 1ad3 subs r3, r2, r3 8010d3e: 2b64 cmp r3, #100 @ 0x64 8010d40: d901 bls.n 8010d46 { return HAL_TIMEOUT; 8010d42: 2303 movs r3, #3 8010d44: e292 b.n 801126c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8010d46: 4b5d ldr r3, [pc, #372] @ (8010ebc ) 8010d48: 681b ldr r3, [r3, #0] 8010d4a: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010d4e: 2b00 cmp r3, #0 8010d50: d0f0 beq.n 8010d34 8010d52: e014 b.n 8010d7e } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010d54: f7fd faf0 bl 800e338 8010d58: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8010d5a: e008 b.n 8010d6e { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8010d5c: f7fd faec bl 800e338 8010d60: 4602 mov r2, r0 8010d62: 693b ldr r3, [r7, #16] 8010d64: 1ad3 subs r3, r2, r3 8010d66: 2b64 cmp r3, #100 @ 0x64 8010d68: d901 bls.n 8010d6e { return HAL_TIMEOUT; 8010d6a: 2303 movs r3, #3 8010d6c: e27e b.n 801126c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8010d6e: 4b53 ldr r3, [pc, #332] @ (8010ebc ) 8010d70: 681b ldr r3, [r3, #0] 8010d72: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010d76: 2b00 cmp r3, #0 8010d78: d1f0 bne.n 8010d5c 8010d7a: e000 b.n 8010d7e if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8010d7c: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8010d7e: 687b ldr r3, [r7, #4] 8010d80: 681b ldr r3, [r3, #0] 8010d82: f003 0302 and.w r3, r3, #2 8010d86: 2b00 cmp r3, #0 8010d88: d063 beq.n 8010e52 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8010d8a: 4b4c ldr r3, [pc, #304] @ (8010ebc ) 8010d8c: 685b ldr r3, [r3, #4] 8010d8e: f003 030c and.w r3, r3, #12 8010d92: 2b00 cmp r3, #0 8010d94: d00b beq.n 8010dae || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 8010d96: 4b49 ldr r3, [pc, #292] @ (8010ebc ) 8010d98: 685b ldr r3, [r3, #4] 8010d9a: f003 030c and.w r3, r3, #12 8010d9e: 2b08 cmp r3, #8 8010da0: d11c bne.n 8010ddc 8010da2: 4b46 ldr r3, [pc, #280] @ (8010ebc ) 8010da4: 685b ldr r3, [r3, #4] 8010da6: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010daa: 2b00 cmp r3, #0 8010dac: d116 bne.n 8010ddc { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8010dae: 4b43 ldr r3, [pc, #268] @ (8010ebc ) 8010db0: 681b ldr r3, [r3, #0] 8010db2: f003 0302 and.w r3, r3, #2 8010db6: 2b00 cmp r3, #0 8010db8: d005 beq.n 8010dc6 8010dba: 687b ldr r3, [r7, #4] 8010dbc: 695b ldr r3, [r3, #20] 8010dbe: 2b01 cmp r3, #1 8010dc0: d001 beq.n 8010dc6 { return HAL_ERROR; 8010dc2: 2301 movs r3, #1 8010dc4: e252 b.n 801126c } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8010dc6: 4b3d ldr r3, [pc, #244] @ (8010ebc ) 8010dc8: 681b ldr r3, [r3, #0] 8010dca: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8010dce: 687b ldr r3, [r7, #4] 8010dd0: 699b ldr r3, [r3, #24] 8010dd2: 00db lsls r3, r3, #3 8010dd4: 4939 ldr r1, [pc, #228] @ (8010ebc ) 8010dd6: 4313 orrs r3, r2 8010dd8: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8010dda: e03a b.n 8010e52 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8010ddc: 687b ldr r3, [r7, #4] 8010dde: 695b ldr r3, [r3, #20] 8010de0: 2b00 cmp r3, #0 8010de2: d020 beq.n 8010e26 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8010de4: 4b36 ldr r3, [pc, #216] @ (8010ec0 ) 8010de6: 2201 movs r2, #1 8010de8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010dea: f7fd faa5 bl 800e338 8010dee: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8010df0: e008 b.n 8010e04 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8010df2: f7fd faa1 bl 800e338 8010df6: 4602 mov r2, r0 8010df8: 693b ldr r3, [r7, #16] 8010dfa: 1ad3 subs r3, r2, r3 8010dfc: 2b02 cmp r3, #2 8010dfe: d901 bls.n 8010e04 { return HAL_TIMEOUT; 8010e00: 2303 movs r3, #3 8010e02: e233 b.n 801126c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8010e04: 4b2d ldr r3, [pc, #180] @ (8010ebc ) 8010e06: 681b ldr r3, [r3, #0] 8010e08: f003 0302 and.w r3, r3, #2 8010e0c: 2b00 cmp r3, #0 8010e0e: d0f0 beq.n 8010df2 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8010e10: 4b2a ldr r3, [pc, #168] @ (8010ebc ) 8010e12: 681b ldr r3, [r3, #0] 8010e14: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8010e18: 687b ldr r3, [r7, #4] 8010e1a: 699b ldr r3, [r3, #24] 8010e1c: 00db lsls r3, r3, #3 8010e1e: 4927 ldr r1, [pc, #156] @ (8010ebc ) 8010e20: 4313 orrs r3, r2 8010e22: 600b str r3, [r1, #0] 8010e24: e015 b.n 8010e52 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8010e26: 4b26 ldr r3, [pc, #152] @ (8010ec0 ) 8010e28: 2200 movs r2, #0 8010e2a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010e2c: f7fd fa84 bl 800e338 8010e30: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8010e32: e008 b.n 8010e46 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8010e34: f7fd fa80 bl 800e338 8010e38: 4602 mov r2, r0 8010e3a: 693b ldr r3, [r7, #16] 8010e3c: 1ad3 subs r3, r2, r3 8010e3e: 2b02 cmp r3, #2 8010e40: d901 bls.n 8010e46 { return HAL_TIMEOUT; 8010e42: 2303 movs r3, #3 8010e44: e212 b.n 801126c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8010e46: 4b1d ldr r3, [pc, #116] @ (8010ebc ) 8010e48: 681b ldr r3, [r3, #0] 8010e4a: f003 0302 and.w r3, r3, #2 8010e4e: 2b00 cmp r3, #0 8010e50: d1f0 bne.n 8010e34 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8010e52: 687b ldr r3, [r7, #4] 8010e54: 681b ldr r3, [r3, #0] 8010e56: f003 0308 and.w r3, r3, #8 8010e5a: 2b00 cmp r3, #0 8010e5c: d03a beq.n 8010ed4 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8010e5e: 687b ldr r3, [r7, #4] 8010e60: 69db ldr r3, [r3, #28] 8010e62: 2b00 cmp r3, #0 8010e64: d019 beq.n 8010e9a { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8010e66: 4b17 ldr r3, [pc, #92] @ (8010ec4 ) 8010e68: 2201 movs r2, #1 8010e6a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010e6c: f7fd fa64 bl 800e338 8010e70: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8010e72: e008 b.n 8010e86 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8010e74: f7fd fa60 bl 800e338 8010e78: 4602 mov r2, r0 8010e7a: 693b ldr r3, [r7, #16] 8010e7c: 1ad3 subs r3, r2, r3 8010e7e: 2b02 cmp r3, #2 8010e80: d901 bls.n 8010e86 { return HAL_TIMEOUT; 8010e82: 2303 movs r3, #3 8010e84: e1f2 b.n 801126c while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8010e86: 4b0d ldr r3, [pc, #52] @ (8010ebc ) 8010e88: 6a5b ldr r3, [r3, #36] @ 0x24 8010e8a: f003 0302 and.w r3, r3, #2 8010e8e: 2b00 cmp r3, #0 8010e90: d0f0 beq.n 8010e74 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 8010e92: 2001 movs r0, #1 8010e94: f000 fbca bl 801162c 8010e98: e01c b.n 8010ed4 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8010e9a: 4b0a ldr r3, [pc, #40] @ (8010ec4 ) 8010e9c: 2200 movs r2, #0 8010e9e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010ea0: f7fd fa4a bl 800e338 8010ea4: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8010ea6: e00f b.n 8010ec8 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8010ea8: f7fd fa46 bl 800e338 8010eac: 4602 mov r2, r0 8010eae: 693b ldr r3, [r7, #16] 8010eb0: 1ad3 subs r3, r2, r3 8010eb2: 2b02 cmp r3, #2 8010eb4: d908 bls.n 8010ec8 { return HAL_TIMEOUT; 8010eb6: 2303 movs r3, #3 8010eb8: e1d8 b.n 801126c 8010eba: bf00 nop 8010ebc: 40021000 .word 0x40021000 8010ec0: 42420000 .word 0x42420000 8010ec4: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8010ec8: 4b9b ldr r3, [pc, #620] @ (8011138 ) 8010eca: 6a5b ldr r3, [r3, #36] @ 0x24 8010ecc: f003 0302 and.w r3, r3, #2 8010ed0: 2b00 cmp r3, #0 8010ed2: d1e9 bne.n 8010ea8 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8010ed4: 687b ldr r3, [r7, #4] 8010ed6: 681b ldr r3, [r3, #0] 8010ed8: f003 0304 and.w r3, r3, #4 8010edc: 2b00 cmp r3, #0 8010ede: f000 80a6 beq.w 801102e { FlagStatus pwrclkchanged = RESET; 8010ee2: 2300 movs r3, #0 8010ee4: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8010ee6: 4b94 ldr r3, [pc, #592] @ (8011138 ) 8010ee8: 69db ldr r3, [r3, #28] 8010eea: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010eee: 2b00 cmp r3, #0 8010ef0: d10d bne.n 8010f0e { __HAL_RCC_PWR_CLK_ENABLE(); 8010ef2: 4b91 ldr r3, [pc, #580] @ (8011138 ) 8010ef4: 69db ldr r3, [r3, #28] 8010ef6: 4a90 ldr r2, [pc, #576] @ (8011138 ) 8010ef8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8010efc: 61d3 str r3, [r2, #28] 8010efe: 4b8e ldr r3, [pc, #568] @ (8011138 ) 8010f00: 69db ldr r3, [r3, #28] 8010f02: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010f06: 60bb str r3, [r7, #8] 8010f08: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8010f0a: 2301 movs r3, #1 8010f0c: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010f0e: 4b8b ldr r3, [pc, #556] @ (801113c ) 8010f10: 681b ldr r3, [r3, #0] 8010f12: f403 7380 and.w r3, r3, #256 @ 0x100 8010f16: 2b00 cmp r3, #0 8010f18: d118 bne.n 8010f4c { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8010f1a: 4b88 ldr r3, [pc, #544] @ (801113c ) 8010f1c: 681b ldr r3, [r3, #0] 8010f1e: 4a87 ldr r2, [pc, #540] @ (801113c ) 8010f20: f443 7380 orr.w r3, r3, #256 @ 0x100 8010f24: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8010f26: f7fd fa07 bl 800e338 8010f2a: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010f2c: e008 b.n 8010f40 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8010f2e: f7fd fa03 bl 800e338 8010f32: 4602 mov r2, r0 8010f34: 693b ldr r3, [r7, #16] 8010f36: 1ad3 subs r3, r2, r3 8010f38: 2b64 cmp r3, #100 @ 0x64 8010f3a: d901 bls.n 8010f40 { return HAL_TIMEOUT; 8010f3c: 2303 movs r3, #3 8010f3e: e195 b.n 801126c while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010f40: 4b7e ldr r3, [pc, #504] @ (801113c ) 8010f42: 681b ldr r3, [r3, #0] 8010f44: f403 7380 and.w r3, r3, #256 @ 0x100 8010f48: 2b00 cmp r3, #0 8010f4a: d0f0 beq.n 8010f2e } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8010f4c: 687b ldr r3, [r7, #4] 8010f4e: 691b ldr r3, [r3, #16] 8010f50: 2b01 cmp r3, #1 8010f52: d106 bne.n 8010f62 8010f54: 4b78 ldr r3, [pc, #480] @ (8011138 ) 8010f56: 6a1b ldr r3, [r3, #32] 8010f58: 4a77 ldr r2, [pc, #476] @ (8011138 ) 8010f5a: f043 0301 orr.w r3, r3, #1 8010f5e: 6213 str r3, [r2, #32] 8010f60: e02d b.n 8010fbe 8010f62: 687b ldr r3, [r7, #4] 8010f64: 691b ldr r3, [r3, #16] 8010f66: 2b00 cmp r3, #0 8010f68: d10c bne.n 8010f84 8010f6a: 4b73 ldr r3, [pc, #460] @ (8011138 ) 8010f6c: 6a1b ldr r3, [r3, #32] 8010f6e: 4a72 ldr r2, [pc, #456] @ (8011138 ) 8010f70: f023 0301 bic.w r3, r3, #1 8010f74: 6213 str r3, [r2, #32] 8010f76: 4b70 ldr r3, [pc, #448] @ (8011138 ) 8010f78: 6a1b ldr r3, [r3, #32] 8010f7a: 4a6f ldr r2, [pc, #444] @ (8011138 ) 8010f7c: f023 0304 bic.w r3, r3, #4 8010f80: 6213 str r3, [r2, #32] 8010f82: e01c b.n 8010fbe 8010f84: 687b ldr r3, [r7, #4] 8010f86: 691b ldr r3, [r3, #16] 8010f88: 2b05 cmp r3, #5 8010f8a: d10c bne.n 8010fa6 8010f8c: 4b6a ldr r3, [pc, #424] @ (8011138 ) 8010f8e: 6a1b ldr r3, [r3, #32] 8010f90: 4a69 ldr r2, [pc, #420] @ (8011138 ) 8010f92: f043 0304 orr.w r3, r3, #4 8010f96: 6213 str r3, [r2, #32] 8010f98: 4b67 ldr r3, [pc, #412] @ (8011138 ) 8010f9a: 6a1b ldr r3, [r3, #32] 8010f9c: 4a66 ldr r2, [pc, #408] @ (8011138 ) 8010f9e: f043 0301 orr.w r3, r3, #1 8010fa2: 6213 str r3, [r2, #32] 8010fa4: e00b b.n 8010fbe 8010fa6: 4b64 ldr r3, [pc, #400] @ (8011138 ) 8010fa8: 6a1b ldr r3, [r3, #32] 8010faa: 4a63 ldr r2, [pc, #396] @ (8011138 ) 8010fac: f023 0301 bic.w r3, r3, #1 8010fb0: 6213 str r3, [r2, #32] 8010fb2: 4b61 ldr r3, [pc, #388] @ (8011138 ) 8010fb4: 6a1b ldr r3, [r3, #32] 8010fb6: 4a60 ldr r2, [pc, #384] @ (8011138 ) 8010fb8: f023 0304 bic.w r3, r3, #4 8010fbc: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8010fbe: 687b ldr r3, [r7, #4] 8010fc0: 691b ldr r3, [r3, #16] 8010fc2: 2b00 cmp r3, #0 8010fc4: d015 beq.n 8010ff2 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010fc6: f7fd f9b7 bl 800e338 8010fca: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8010fcc: e00a b.n 8010fe4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8010fce: f7fd f9b3 bl 800e338 8010fd2: 4602 mov r2, r0 8010fd4: 693b ldr r3, [r7, #16] 8010fd6: 1ad3 subs r3, r2, r3 8010fd8: f241 3288 movw r2, #5000 @ 0x1388 8010fdc: 4293 cmp r3, r2 8010fde: d901 bls.n 8010fe4 { return HAL_TIMEOUT; 8010fe0: 2303 movs r3, #3 8010fe2: e143 b.n 801126c while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8010fe4: 4b54 ldr r3, [pc, #336] @ (8011138 ) 8010fe6: 6a1b ldr r3, [r3, #32] 8010fe8: f003 0302 and.w r3, r3, #2 8010fec: 2b00 cmp r3, #0 8010fee: d0ee beq.n 8010fce 8010ff0: e014 b.n 801101c } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010ff2: f7fd f9a1 bl 800e338 8010ff6: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8010ff8: e00a b.n 8011010 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8010ffa: f7fd f99d bl 800e338 8010ffe: 4602 mov r2, r0 8011000: 693b ldr r3, [r7, #16] 8011002: 1ad3 subs r3, r2, r3 8011004: f241 3288 movw r2, #5000 @ 0x1388 8011008: 4293 cmp r3, r2 801100a: d901 bls.n 8011010 { return HAL_TIMEOUT; 801100c: 2303 movs r3, #3 801100e: e12d b.n 801126c while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8011010: 4b49 ldr r3, [pc, #292] @ (8011138 ) 8011012: 6a1b ldr r3, [r3, #32] 8011014: f003 0302 and.w r3, r3, #2 8011018: 2b00 cmp r3, #0 801101a: d1ee bne.n 8010ffa } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 801101c: 7dfb ldrb r3, [r7, #23] 801101e: 2b01 cmp r3, #1 8011020: d105 bne.n 801102e { __HAL_RCC_PWR_CLK_DISABLE(); 8011022: 4b45 ldr r3, [pc, #276] @ (8011138 ) 8011024: 69db ldr r3, [r3, #28] 8011026: 4a44 ldr r2, [pc, #272] @ (8011138 ) 8011028: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 801102c: 61d3 str r3, [r2, #28] #if defined(RCC_CR_PLL2ON) /*-------------------------------- PLL2 Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) 801102e: 687b ldr r3, [r7, #4] 8011030: 6adb ldr r3, [r3, #44] @ 0x2c 8011032: 2b00 cmp r3, #0 8011034: f000 808c beq.w 8011150 { /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 8011038: 4b3f ldr r3, [pc, #252] @ (8011138 ) 801103a: 685b ldr r3, [r3, #4] 801103c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8011040: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8011044: d10e bne.n 8011064 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 8011046: 4b3c ldr r3, [pc, #240] @ (8011138 ) 8011048: 685b ldr r3, [r3, #4] 801104a: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 801104e: 2b08 cmp r3, #8 8011050: d108 bne.n 8011064 ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) 8011052: 4b39 ldr r3, [pc, #228] @ (8011138 ) 8011054: 6adb ldr r3, [r3, #44] @ 0x2c 8011056: f403 3380 and.w r3, r3, #65536 @ 0x10000 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 801105a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 801105e: d101 bne.n 8011064 { return HAL_ERROR; 8011060: 2301 movs r3, #1 8011062: e103 b.n 801126c } else { if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) 8011064: 687b ldr r3, [r7, #4] 8011066: 6adb ldr r3, [r3, #44] @ 0x2c 8011068: 2b02 cmp r3, #2 801106a: d14e bne.n 801110a assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); /* Prediv2 can be written only when the PLLI2S is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 801106c: 4b32 ldr r3, [pc, #200] @ (8011138 ) 801106e: 681b ldr r3, [r3, #0] 8011070: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011074: 2b00 cmp r3, #0 8011076: d009 beq.n 801108c (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) 8011078: 4b2f ldr r3, [pc, #188] @ (8011138 ) 801107a: 6adb ldr r3, [r3, #44] @ 0x2c 801107c: f003 02f0 and.w r2, r3, #240 @ 0xf0 8011080: 687b ldr r3, [r7, #4] 8011082: 6b5b ldr r3, [r3, #52] @ 0x34 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 8011084: 429a cmp r2, r3 8011086: d001 beq.n 801108c { return HAL_ERROR; 8011088: 2301 movs r3, #1 801108a: e0ef b.n 801126c } /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 801108c: 4b2c ldr r3, [pc, #176] @ (8011140 ) 801108e: 2200 movs r2, #0 8011090: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8011092: f7fd f951 bl 800e338 8011096: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8011098: e008 b.n 80110ac { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 801109a: f7fd f94d bl 800e338 801109e: 4602 mov r2, r0 80110a0: 693b ldr r3, [r7, #16] 80110a2: 1ad3 subs r3, r2, r3 80110a4: 2b64 cmp r3, #100 @ 0x64 80110a6: d901 bls.n 80110ac { return HAL_TIMEOUT; 80110a8: 2303 movs r3, #3 80110aa: e0df b.n 801126c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 80110ac: 4b22 ldr r3, [pc, #136] @ (8011138 ) 80110ae: 681b ldr r3, [r3, #0] 80110b0: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80110b4: 2b00 cmp r3, #0 80110b6: d1f0 bne.n 801109a } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); 80110b8: 4b1f ldr r3, [pc, #124] @ (8011138 ) 80110ba: 6adb ldr r3, [r3, #44] @ 0x2c 80110bc: f023 02f0 bic.w r2, r3, #240 @ 0xf0 80110c0: 687b ldr r3, [r7, #4] 80110c2: 6b5b ldr r3, [r3, #52] @ 0x34 80110c4: 491c ldr r1, [pc, #112] @ (8011138 ) 80110c6: 4313 orrs r3, r2 80110c8: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); 80110ca: 4b1b ldr r3, [pc, #108] @ (8011138 ) 80110cc: 6adb ldr r3, [r3, #44] @ 0x2c 80110ce: f423 6270 bic.w r2, r3, #3840 @ 0xf00 80110d2: 687b ldr r3, [r7, #4] 80110d4: 6b1b ldr r3, [r3, #48] @ 0x30 80110d6: 4918 ldr r1, [pc, #96] @ (8011138 ) 80110d8: 4313 orrs r3, r2 80110da: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); 80110dc: 4b18 ldr r3, [pc, #96] @ (8011140 ) 80110de: 2201 movs r2, #1 80110e0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80110e2: f7fd f929 bl 800e338 80110e6: 6138 str r0, [r7, #16] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 80110e8: e008 b.n 80110fc { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 80110ea: f7fd f925 bl 800e338 80110ee: 4602 mov r2, r0 80110f0: 693b ldr r3, [r7, #16] 80110f2: 1ad3 subs r3, r2, r3 80110f4: 2b64 cmp r3, #100 @ 0x64 80110f6: d901 bls.n 80110fc { return HAL_TIMEOUT; 80110f8: 2303 movs r3, #3 80110fa: e0b7 b.n 801126c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 80110fc: 4b0e ldr r3, [pc, #56] @ (8011138 ) 80110fe: 681b ldr r3, [r3, #0] 8011100: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8011104: 2b00 cmp r3, #0 8011106: d0f0 beq.n 80110ea 8011108: e022 b.n 8011150 } } else { /* Set PREDIV1 source to HSE */ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); 801110a: 4b0b ldr r3, [pc, #44] @ (8011138 ) 801110c: 6adb ldr r3, [r3, #44] @ 0x2c 801110e: 4a0a ldr r2, [pc, #40] @ (8011138 ) 8011110: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8011114: 62d3 str r3, [r2, #44] @ 0x2c /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 8011116: 4b0a ldr r3, [pc, #40] @ (8011140 ) 8011118: 2200 movs r2, #0 801111a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 801111c: f7fd f90c bl 800e338 8011120: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8011122: e00f b.n 8011144 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8011124: f7fd f908 bl 800e338 8011128: 4602 mov r2, r0 801112a: 693b ldr r3, [r7, #16] 801112c: 1ad3 subs r3, r2, r3 801112e: 2b64 cmp r3, #100 @ 0x64 8011130: d908 bls.n 8011144 { return HAL_TIMEOUT; 8011132: 2303 movs r3, #3 8011134: e09a b.n 801126c 8011136: bf00 nop 8011138: 40021000 .word 0x40021000 801113c: 40007000 .word 0x40007000 8011140: 42420068 .word 0x42420068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8011144: 4b4b ldr r3, [pc, #300] @ (8011274 ) 8011146: 681b ldr r3, [r3, #0] 8011148: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 801114c: 2b00 cmp r3, #0 801114e: d1e9 bne.n 8011124 #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8011150: 687b ldr r3, [r7, #4] 8011152: 6a1b ldr r3, [r3, #32] 8011154: 2b00 cmp r3, #0 8011156: f000 8088 beq.w 801126a { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 801115a: 4b46 ldr r3, [pc, #280] @ (8011274 ) 801115c: 685b ldr r3, [r3, #4] 801115e: f003 030c and.w r3, r3, #12 8011162: 2b08 cmp r3, #8 8011164: d068 beq.n 8011238 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8011166: 687b ldr r3, [r7, #4] 8011168: 6a1b ldr r3, [r3, #32] 801116a: 2b02 cmp r3, #2 801116c: d14d bne.n 801120a /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 801116e: 4b42 ldr r3, [pc, #264] @ (8011278 ) 8011170: 2200 movs r2, #0 8011172: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8011174: f7fd f8e0 bl 800e338 8011178: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 801117a: e008 b.n 801118e { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 801117c: f7fd f8dc bl 800e338 8011180: 4602 mov r2, r0 8011182: 693b ldr r3, [r7, #16] 8011184: 1ad3 subs r3, r2, r3 8011186: 2b02 cmp r3, #2 8011188: d901 bls.n 801118e { return HAL_TIMEOUT; 801118a: 2303 movs r3, #3 801118c: e06e b.n 801126c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 801118e: 4b39 ldr r3, [pc, #228] @ (8011274 ) 8011190: 681b ldr r3, [r3, #0] 8011192: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8011196: 2b00 cmp r3, #0 8011198: d1f0 bne.n 801117c } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 801119a: 687b ldr r3, [r7, #4] 801119c: 6a5b ldr r3, [r3, #36] @ 0x24 801119e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80111a2: d10f bne.n 80111c4 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); #if defined(RCC_CFGR2_PREDIV1SRC) assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); 80111a4: 4b33 ldr r3, [pc, #204] @ (8011274 ) 80111a6: 6ada ldr r2, [r3, #44] @ 0x2c 80111a8: 687b ldr r3, [r7, #4] 80111aa: 685b ldr r3, [r3, #4] 80111ac: 4931 ldr r1, [pc, #196] @ (8011274 ) 80111ae: 4313 orrs r3, r2 80111b0: 62cb str r3, [r1, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 80111b2: 4b30 ldr r3, [pc, #192] @ (8011274 ) 80111b4: 6adb ldr r3, [r3, #44] @ 0x2c 80111b6: f023 020f bic.w r2, r3, #15 80111ba: 687b ldr r3, [r7, #4] 80111bc: 68db ldr r3, [r3, #12] 80111be: 492d ldr r1, [pc, #180] @ (8011274 ) 80111c0: 4313 orrs r3, r2 80111c2: 62cb str r3, [r1, #44] @ 0x2c } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80111c4: 4b2b ldr r3, [pc, #172] @ (8011274 ) 80111c6: 685b ldr r3, [r3, #4] 80111c8: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 80111cc: 687b ldr r3, [r7, #4] 80111ce: 6a59 ldr r1, [r3, #36] @ 0x24 80111d0: 687b ldr r3, [r7, #4] 80111d2: 6a9b ldr r3, [r3, #40] @ 0x28 80111d4: 430b orrs r3, r1 80111d6: 4927 ldr r1, [pc, #156] @ (8011274 ) 80111d8: 4313 orrs r3, r2 80111da: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 80111dc: 4b26 ldr r3, [pc, #152] @ (8011278 ) 80111de: 2201 movs r2, #1 80111e0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80111e2: f7fd f8a9 bl 800e338 80111e6: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80111e8: e008 b.n 80111fc { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80111ea: f7fd f8a5 bl 800e338 80111ee: 4602 mov r2, r0 80111f0: 693b ldr r3, [r7, #16] 80111f2: 1ad3 subs r3, r2, r3 80111f4: 2b02 cmp r3, #2 80111f6: d901 bls.n 80111fc { return HAL_TIMEOUT; 80111f8: 2303 movs r3, #3 80111fa: e037 b.n 801126c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80111fc: 4b1d ldr r3, [pc, #116] @ (8011274 ) 80111fe: 681b ldr r3, [r3, #0] 8011200: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8011204: 2b00 cmp r3, #0 8011206: d0f0 beq.n 80111ea 8011208: e02f b.n 801126a } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 801120a: 4b1b ldr r3, [pc, #108] @ (8011278 ) 801120c: 2200 movs r2, #0 801120e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8011210: f7fd f892 bl 800e338 8011214: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8011216: e008 b.n 801122a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8011218: f7fd f88e bl 800e338 801121c: 4602 mov r2, r0 801121e: 693b ldr r3, [r7, #16] 8011220: 1ad3 subs r3, r2, r3 8011222: 2b02 cmp r3, #2 8011224: d901 bls.n 801122a { return HAL_TIMEOUT; 8011226: 2303 movs r3, #3 8011228: e020 b.n 801126c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 801122a: 4b12 ldr r3, [pc, #72] @ (8011274 ) 801122c: 681b ldr r3, [r3, #0] 801122e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8011232: 2b00 cmp r3, #0 8011234: d1f0 bne.n 8011218 8011236: e018 b.n 801126a } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8011238: 687b ldr r3, [r7, #4] 801123a: 6a1b ldr r3, [r3, #32] 801123c: 2b01 cmp r3, #1 801123e: d101 bne.n 8011244 { return HAL_ERROR; 8011240: 2301 movs r3, #1 8011242: e013 b.n 801126c } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8011244: 4b0b ldr r3, [pc, #44] @ (8011274 ) 8011246: 685b ldr r3, [r3, #4] 8011248: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 801124a: 68fb ldr r3, [r7, #12] 801124c: f403 3280 and.w r2, r3, #65536 @ 0x10000 8011250: 687b ldr r3, [r7, #4] 8011252: 6a5b ldr r3, [r3, #36] @ 0x24 8011254: 429a cmp r2, r3 8011256: d106 bne.n 8011266 (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8011258: 68fb ldr r3, [r7, #12] 801125a: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 801125e: 687b ldr r3, [r7, #4] 8011260: 6a9b ldr r3, [r3, #40] @ 0x28 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8011262: 429a cmp r2, r3 8011264: d001 beq.n 801126a { return HAL_ERROR; 8011266: 2301 movs r3, #1 8011268: e000 b.n 801126c } } } } return HAL_OK; 801126a: 2300 movs r3, #0 } 801126c: 4618 mov r0, r3 801126e: 3718 adds r7, #24 8011270: 46bd mov sp, r7 8011272: bd80 pop {r7, pc} 8011274: 40021000 .word 0x40021000 8011278: 42420060 .word 0x42420060 0801127c : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 801127c: b580 push {r7, lr} 801127e: b084 sub sp, #16 8011280: af00 add r7, sp, #0 8011282: 6078 str r0, [r7, #4] 8011284: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8011286: 687b ldr r3, [r7, #4] 8011288: 2b00 cmp r3, #0 801128a: d101 bne.n 8011290 { return HAL_ERROR; 801128c: 2301 movs r3, #1 801128e: e0d0 b.n 8011432 must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8011290: 4b6a ldr r3, [pc, #424] @ (801143c ) 8011292: 681b ldr r3, [r3, #0] 8011294: f003 0307 and.w r3, r3, #7 8011298: 683a ldr r2, [r7, #0] 801129a: 429a cmp r2, r3 801129c: d910 bls.n 80112c0 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 801129e: 4b67 ldr r3, [pc, #412] @ (801143c ) 80112a0: 681b ldr r3, [r3, #0] 80112a2: f023 0207 bic.w r2, r3, #7 80112a6: 4965 ldr r1, [pc, #404] @ (801143c ) 80112a8: 683b ldr r3, [r7, #0] 80112aa: 4313 orrs r3, r2 80112ac: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80112ae: 4b63 ldr r3, [pc, #396] @ (801143c ) 80112b0: 681b ldr r3, [r3, #0] 80112b2: f003 0307 and.w r3, r3, #7 80112b6: 683a ldr r2, [r7, #0] 80112b8: 429a cmp r2, r3 80112ba: d001 beq.n 80112c0 { return HAL_ERROR; 80112bc: 2301 movs r3, #1 80112be: e0b8 b.n 8011432 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 80112c0: 687b ldr r3, [r7, #4] 80112c2: 681b ldr r3, [r3, #0] 80112c4: f003 0302 and.w r3, r3, #2 80112c8: 2b00 cmp r3, #0 80112ca: d020 beq.n 801130e { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80112cc: 687b ldr r3, [r7, #4] 80112ce: 681b ldr r3, [r3, #0] 80112d0: f003 0304 and.w r3, r3, #4 80112d4: 2b00 cmp r3, #0 80112d6: d005 beq.n 80112e4 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 80112d8: 4b59 ldr r3, [pc, #356] @ (8011440 ) 80112da: 685b ldr r3, [r3, #4] 80112dc: 4a58 ldr r2, [pc, #352] @ (8011440 ) 80112de: f443 63e0 orr.w r3, r3, #1792 @ 0x700 80112e2: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80112e4: 687b ldr r3, [r7, #4] 80112e6: 681b ldr r3, [r3, #0] 80112e8: f003 0308 and.w r3, r3, #8 80112ec: 2b00 cmp r3, #0 80112ee: d005 beq.n 80112fc { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 80112f0: 4b53 ldr r3, [pc, #332] @ (8011440 ) 80112f2: 685b ldr r3, [r3, #4] 80112f4: 4a52 ldr r2, [pc, #328] @ (8011440 ) 80112f6: f443 5360 orr.w r3, r3, #14336 @ 0x3800 80112fa: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80112fc: 4b50 ldr r3, [pc, #320] @ (8011440 ) 80112fe: 685b ldr r3, [r3, #4] 8011300: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8011304: 687b ldr r3, [r7, #4] 8011306: 689b ldr r3, [r3, #8] 8011308: 494d ldr r1, [pc, #308] @ (8011440 ) 801130a: 4313 orrs r3, r2 801130c: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 801130e: 687b ldr r3, [r7, #4] 8011310: 681b ldr r3, [r3, #0] 8011312: f003 0301 and.w r3, r3, #1 8011316: 2b00 cmp r3, #0 8011318: d040 beq.n 801139c { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 801131a: 687b ldr r3, [r7, #4] 801131c: 685b ldr r3, [r3, #4] 801131e: 2b01 cmp r3, #1 8011320: d107 bne.n 8011332 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8011322: 4b47 ldr r3, [pc, #284] @ (8011440 ) 8011324: 681b ldr r3, [r3, #0] 8011326: f403 3300 and.w r3, r3, #131072 @ 0x20000 801132a: 2b00 cmp r3, #0 801132c: d115 bne.n 801135a { return HAL_ERROR; 801132e: 2301 movs r3, #1 8011330: e07f b.n 8011432 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8011332: 687b ldr r3, [r7, #4] 8011334: 685b ldr r3, [r3, #4] 8011336: 2b02 cmp r3, #2 8011338: d107 bne.n 801134a { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 801133a: 4b41 ldr r3, [pc, #260] @ (8011440 ) 801133c: 681b ldr r3, [r3, #0] 801133e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8011342: 2b00 cmp r3, #0 8011344: d109 bne.n 801135a { return HAL_ERROR; 8011346: 2301 movs r3, #1 8011348: e073 b.n 8011432 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 801134a: 4b3d ldr r3, [pc, #244] @ (8011440 ) 801134c: 681b ldr r3, [r3, #0] 801134e: f003 0302 and.w r3, r3, #2 8011352: 2b00 cmp r3, #0 8011354: d101 bne.n 801135a { return HAL_ERROR; 8011356: 2301 movs r3, #1 8011358: e06b b.n 8011432 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 801135a: 4b39 ldr r3, [pc, #228] @ (8011440 ) 801135c: 685b ldr r3, [r3, #4] 801135e: f023 0203 bic.w r2, r3, #3 8011362: 687b ldr r3, [r7, #4] 8011364: 685b ldr r3, [r3, #4] 8011366: 4936 ldr r1, [pc, #216] @ (8011440 ) 8011368: 4313 orrs r3, r2 801136a: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 801136c: f7fc ffe4 bl 800e338 8011370: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8011372: e00a b.n 801138a { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8011374: f7fc ffe0 bl 800e338 8011378: 4602 mov r2, r0 801137a: 68fb ldr r3, [r7, #12] 801137c: 1ad3 subs r3, r2, r3 801137e: f241 3288 movw r2, #5000 @ 0x1388 8011382: 4293 cmp r3, r2 8011384: d901 bls.n 801138a { return HAL_TIMEOUT; 8011386: 2303 movs r3, #3 8011388: e053 b.n 8011432 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 801138a: 4b2d ldr r3, [pc, #180] @ (8011440 ) 801138c: 685b ldr r3, [r3, #4] 801138e: f003 020c and.w r2, r3, #12 8011392: 687b ldr r3, [r7, #4] 8011394: 685b ldr r3, [r3, #4] 8011396: 009b lsls r3, r3, #2 8011398: 429a cmp r2, r3 801139a: d1eb bne.n 8011374 } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 801139c: 4b27 ldr r3, [pc, #156] @ (801143c ) 801139e: 681b ldr r3, [r3, #0] 80113a0: f003 0307 and.w r3, r3, #7 80113a4: 683a ldr r2, [r7, #0] 80113a6: 429a cmp r2, r3 80113a8: d210 bcs.n 80113cc { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80113aa: 4b24 ldr r3, [pc, #144] @ (801143c ) 80113ac: 681b ldr r3, [r3, #0] 80113ae: f023 0207 bic.w r2, r3, #7 80113b2: 4922 ldr r1, [pc, #136] @ (801143c ) 80113b4: 683b ldr r3, [r7, #0] 80113b6: 4313 orrs r3, r2 80113b8: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80113ba: 4b20 ldr r3, [pc, #128] @ (801143c ) 80113bc: 681b ldr r3, [r3, #0] 80113be: f003 0307 and.w r3, r3, #7 80113c2: 683a ldr r2, [r7, #0] 80113c4: 429a cmp r2, r3 80113c6: d001 beq.n 80113cc { return HAL_ERROR; 80113c8: 2301 movs r3, #1 80113ca: e032 b.n 8011432 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80113cc: 687b ldr r3, [r7, #4] 80113ce: 681b ldr r3, [r3, #0] 80113d0: f003 0304 and.w r3, r3, #4 80113d4: 2b00 cmp r3, #0 80113d6: d008 beq.n 80113ea { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 80113d8: 4b19 ldr r3, [pc, #100] @ (8011440 ) 80113da: 685b ldr r3, [r3, #4] 80113dc: f423 62e0 bic.w r2, r3, #1792 @ 0x700 80113e0: 687b ldr r3, [r7, #4] 80113e2: 68db ldr r3, [r3, #12] 80113e4: 4916 ldr r1, [pc, #88] @ (8011440 ) 80113e6: 4313 orrs r3, r2 80113e8: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80113ea: 687b ldr r3, [r7, #4] 80113ec: 681b ldr r3, [r3, #0] 80113ee: f003 0308 and.w r3, r3, #8 80113f2: 2b00 cmp r3, #0 80113f4: d009 beq.n 801140a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 80113f6: 4b12 ldr r3, [pc, #72] @ (8011440 ) 80113f8: 685b ldr r3, [r3, #4] 80113fa: f423 5260 bic.w r2, r3, #14336 @ 0x3800 80113fe: 687b ldr r3, [r7, #4] 8011400: 691b ldr r3, [r3, #16] 8011402: 00db lsls r3, r3, #3 8011404: 490e ldr r1, [pc, #56] @ (8011440 ) 8011406: 4313 orrs r3, r2 8011408: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 801140a: f000 f821 bl 8011450 801140e: 4602 mov r2, r0 8011410: 4b0b ldr r3, [pc, #44] @ (8011440 ) 8011412: 685b ldr r3, [r3, #4] 8011414: 091b lsrs r3, r3, #4 8011416: f003 030f and.w r3, r3, #15 801141a: 490a ldr r1, [pc, #40] @ (8011444 ) 801141c: 5ccb ldrb r3, [r1, r3] 801141e: fa22 f303 lsr.w r3, r2, r3 8011422: 4a09 ldr r2, [pc, #36] @ (8011448 ) 8011424: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 8011426: 4b09 ldr r3, [pc, #36] @ (801144c ) 8011428: 681b ldr r3, [r3, #0] 801142a: 4618 mov r0, r3 801142c: f7fc ff42 bl 800e2b4 return HAL_OK; 8011430: 2300 movs r3, #0 } 8011432: 4618 mov r0, r3 8011434: 3710 adds r7, #16 8011436: 46bd mov sp, r7 8011438: bd80 pop {r7, pc} 801143a: bf00 nop 801143c: 40022000 .word 0x40022000 8011440: 40021000 .word 0x40021000 8011444: 080178fc .word 0x080178fc 8011448: 20000084 .word 0x20000084 801144c: 20000088 .word 0x20000088 08011450 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8011450: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8011454: b08e sub sp, #56 @ 0x38 8011456: af00 add r7, sp, #0 #else static const uint8_t aPredivFactorTable[2U] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8011458: 2300 movs r3, #0 801145a: 62fb str r3, [r7, #44] @ 0x2c 801145c: 2300 movs r3, #0 801145e: 62bb str r3, [r7, #40] @ 0x28 8011460: 2300 movs r3, #0 8011462: 637b str r3, [r7, #52] @ 0x34 8011464: 2300 movs r3, #0 8011466: 627b str r3, [r7, #36] @ 0x24 uint32_t sysclockfreq = 0U; 8011468: 2300 movs r3, #0 801146a: 633b str r3, [r7, #48] @ 0x30 #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; 801146c: 2300 movs r3, #0 801146e: 623b str r3, [r7, #32] 8011470: 2300 movs r3, #0 8011472: 61fb str r3, [r7, #28] #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 8011474: 4b4e ldr r3, [pc, #312] @ (80115b0 ) 8011476: 685b ldr r3, [r3, #4] 8011478: 62fb str r3, [r7, #44] @ 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 801147a: 6afb ldr r3, [r7, #44] @ 0x2c 801147c: f003 030c and.w r3, r3, #12 8011480: 2b04 cmp r3, #4 8011482: d002 beq.n 801148a 8011484: 2b08 cmp r3, #8 8011486: d003 beq.n 8011490 8011488: e089 b.n 801159e { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 801148a: 4b4a ldr r3, [pc, #296] @ (80115b4 ) 801148c: 633b str r3, [r7, #48] @ 0x30 break; 801148e: e089 b.n 80115a4 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8011490: 6afb ldr r3, [r7, #44] @ 0x2c 8011492: 0c9b lsrs r3, r3, #18 8011494: f003 020f and.w r2, r3, #15 8011498: 4b47 ldr r3, [pc, #284] @ (80115b8 ) 801149a: 5c9b ldrb r3, [r3, r2] 801149c: 627b str r3, [r7, #36] @ 0x24 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 801149e: 6afb ldr r3, [r7, #44] @ 0x2c 80114a0: f403 3380 and.w r3, r3, #65536 @ 0x10000 80114a4: 2b00 cmp r3, #0 80114a6: d072 beq.n 801158e { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 80114a8: 4b41 ldr r3, [pc, #260] @ (80115b0 ) 80114aa: 6adb ldr r3, [r3, #44] @ 0x2c 80114ac: f003 020f and.w r2, r3, #15 80114b0: 4b42 ldr r3, [pc, #264] @ (80115bc ) 80114b2: 5c9b ldrb r3, [r3, r2] 80114b4: 62bb str r3, [r7, #40] @ 0x28 #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /*RCC_CFGR2_PREDIV1*/ #if defined(RCC_CFGR2_PREDIV1SRC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 80114b6: 4b3e ldr r3, [pc, #248] @ (80115b0 ) 80114b8: 6adb ldr r3, [r3, #44] @ 0x2c 80114ba: f403 3380 and.w r3, r3, #65536 @ 0x10000 80114be: 2b00 cmp r3, #0 80114c0: d053 beq.n 801156a { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 80114c2: 4b3b ldr r3, [pc, #236] @ (80115b0 ) 80114c4: 6adb ldr r3, [r3, #44] @ 0x2c 80114c6: 091b lsrs r3, r3, #4 80114c8: f003 030f and.w r3, r3, #15 80114cc: 3301 adds r3, #1 80114ce: 623b str r3, [r7, #32] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 80114d0: 4b37 ldr r3, [pc, #220] @ (80115b0 ) 80114d2: 6adb ldr r3, [r3, #44] @ 0x2c 80114d4: 0a1b lsrs r3, r3, #8 80114d6: f003 030f and.w r3, r3, #15 80114da: 3302 adds r3, #2 80114dc: 61fb str r3, [r7, #28] pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); 80114de: 69fb ldr r3, [r7, #28] 80114e0: 2200 movs r2, #0 80114e2: 469a mov sl, r3 80114e4: 4693 mov fp, r2 80114e6: 6a7b ldr r3, [r7, #36] @ 0x24 80114e8: 2200 movs r2, #0 80114ea: 613b str r3, [r7, #16] 80114ec: 617a str r2, [r7, #20] 80114ee: 693b ldr r3, [r7, #16] 80114f0: fb03 f20b mul.w r2, r3, fp 80114f4: 697b ldr r3, [r7, #20] 80114f6: fb0a f303 mul.w r3, sl, r3 80114fa: 4413 add r3, r2 80114fc: 693a ldr r2, [r7, #16] 80114fe: fbaa 0102 umull r0, r1, sl, r2 8011502: 440b add r3, r1 8011504: 4619 mov r1, r3 8011506: 4b2b ldr r3, [pc, #172] @ (80115b4 ) 8011508: fb03 f201 mul.w r2, r3, r1 801150c: 2300 movs r3, #0 801150e: fb00 f303 mul.w r3, r0, r3 8011512: 4413 add r3, r2 8011514: 4a27 ldr r2, [pc, #156] @ (80115b4 ) 8011516: fba0 4502 umull r4, r5, r0, r2 801151a: 442b add r3, r5 801151c: 461d mov r5, r3 801151e: 6a3b ldr r3, [r7, #32] 8011520: 2200 movs r2, #0 8011522: 60bb str r3, [r7, #8] 8011524: 60fa str r2, [r7, #12] 8011526: 6abb ldr r3, [r7, #40] @ 0x28 8011528: 2200 movs r2, #0 801152a: 603b str r3, [r7, #0] 801152c: 607a str r2, [r7, #4] 801152e: e9d7 0102 ldrd r0, r1, [r7, #8] 8011532: 460b mov r3, r1 8011534: e9d7 ab00 ldrd sl, fp, [r7] 8011538: 4652 mov r2, sl 801153a: fb02 f203 mul.w r2, r2, r3 801153e: 465b mov r3, fp 8011540: 4684 mov ip, r0 8011542: fb0c f303 mul.w r3, ip, r3 8011546: 4413 add r3, r2 8011548: 4602 mov r2, r0 801154a: 4651 mov r1, sl 801154c: fba2 8901 umull r8, r9, r2, r1 8011550: 444b add r3, r9 8011552: 4699 mov r9, r3 8011554: 4642 mov r2, r8 8011556: 464b mov r3, r9 8011558: 4620 mov r0, r4 801155a: 4629 mov r1, r5 801155c: f7f7 fe4a bl 80091f4 <__aeabi_uldivmod> 8011560: 4602 mov r2, r0 8011562: 460b mov r3, r1 8011564: 4613 mov r3, r2 8011566: 637b str r3, [r7, #52] @ 0x34 8011568: e007 b.n 801157a } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 801156a: 6a7b ldr r3, [r7, #36] @ 0x24 801156c: 4a11 ldr r2, [pc, #68] @ (80115b4 ) 801156e: fb03 f202 mul.w r2, r3, r2 8011572: 6abb ldr r3, [r7, #40] @ 0x28 8011574: fbb2 f3f3 udiv r3, r2, r3 8011578: 637b str r3, [r7, #52] @ 0x34 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 801157a: 4b0f ldr r3, [pc, #60] @ (80115b8 ) 801157c: 7b5b ldrb r3, [r3, #13] 801157e: 461a mov r2, r3 8011580: 6a7b ldr r3, [r7, #36] @ 0x24 8011582: 4293 cmp r3, r2 8011584: d108 bne.n 8011598 { pllclk = pllclk / 2; 8011586: 6b7b ldr r3, [r7, #52] @ 0x34 8011588: 085b lsrs r3, r3, #1 801158a: 637b str r3, [r7, #52] @ 0x34 801158c: e004 b.n 8011598 #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 801158e: 6a7b ldr r3, [r7, #36] @ 0x24 8011590: 4a0b ldr r2, [pc, #44] @ (80115c0 ) 8011592: fb02 f303 mul.w r3, r2, r3 8011596: 637b str r3, [r7, #52] @ 0x34 } sysclockfreq = pllclk; 8011598: 6b7b ldr r3, [r7, #52] @ 0x34 801159a: 633b str r3, [r7, #48] @ 0x30 break; 801159c: e002 b.n 80115a4 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 801159e: 4b09 ldr r3, [pc, #36] @ (80115c4 ) 80115a0: 633b str r3, [r7, #48] @ 0x30 break; 80115a2: bf00 nop } } return sysclockfreq; 80115a4: 6b3b ldr r3, [r7, #48] @ 0x30 } 80115a6: 4618 mov r0, r3 80115a8: 3738 adds r7, #56 @ 0x38 80115aa: 46bd mov sp, r7 80115ac: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 80115b0: 40021000 .word 0x40021000 80115b4: 017d7840 .word 0x017d7840 80115b8: 08017914 .word 0x08017914 80115bc: 08017924 .word 0x08017924 80115c0: 003d0900 .word 0x003d0900 80115c4: 007a1200 .word 0x007a1200 080115c8 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 80115c8: b480 push {r7} 80115ca: af00 add r7, sp, #0 return SystemCoreClock; 80115cc: 4b02 ldr r3, [pc, #8] @ (80115d8 ) 80115ce: 681b ldr r3, [r3, #0] } 80115d0: 4618 mov r0, r3 80115d2: 46bd mov sp, r7 80115d4: bc80 pop {r7} 80115d6: 4770 bx lr 80115d8: 20000084 .word 0x20000084 080115dc : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 80115dc: b580 push {r7, lr} 80115de: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 80115e0: f7ff fff2 bl 80115c8 80115e4: 4602 mov r2, r0 80115e6: 4b05 ldr r3, [pc, #20] @ (80115fc ) 80115e8: 685b ldr r3, [r3, #4] 80115ea: 0a1b lsrs r3, r3, #8 80115ec: f003 0307 and.w r3, r3, #7 80115f0: 4903 ldr r1, [pc, #12] @ (8011600 ) 80115f2: 5ccb ldrb r3, [r1, r3] 80115f4: fa22 f303 lsr.w r3, r2, r3 } 80115f8: 4618 mov r0, r3 80115fa: bd80 pop {r7, pc} 80115fc: 40021000 .word 0x40021000 8011600: 0801790c .word 0x0801790c 08011604 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8011604: b580 push {r7, lr} 8011606: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8011608: f7ff ffde bl 80115c8 801160c: 4602 mov r2, r0 801160e: 4b05 ldr r3, [pc, #20] @ (8011624 ) 8011610: 685b ldr r3, [r3, #4] 8011612: 0adb lsrs r3, r3, #11 8011614: f003 0307 and.w r3, r3, #7 8011618: 4903 ldr r1, [pc, #12] @ (8011628 ) 801161a: 5ccb ldrb r3, [r1, r3] 801161c: fa22 f303 lsr.w r3, r2, r3 } 8011620: 4618 mov r0, r3 8011622: bd80 pop {r7, pc} 8011624: 40021000 .word 0x40021000 8011628: 0801790c .word 0x0801790c 0801162c : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 801162c: b480 push {r7} 801162e: b085 sub sp, #20 8011630: af00 add r7, sp, #0 8011632: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8011634: 4b0a ldr r3, [pc, #40] @ (8011660 ) 8011636: 681b ldr r3, [r3, #0] 8011638: 4a0a ldr r2, [pc, #40] @ (8011664 ) 801163a: fba2 2303 umull r2, r3, r2, r3 801163e: 0a5b lsrs r3, r3, #9 8011640: 687a ldr r2, [r7, #4] 8011642: fb02 f303 mul.w r3, r2, r3 8011646: 60fb str r3, [r7, #12] do { __NOP(); 8011648: bf00 nop } while (Delay --); 801164a: 68fb ldr r3, [r7, #12] 801164c: 1e5a subs r2, r3, #1 801164e: 60fa str r2, [r7, #12] 8011650: 2b00 cmp r3, #0 8011652: d1f9 bne.n 8011648 } 8011654: bf00 nop 8011656: bf00 nop 8011658: 3714 adds r7, #20 801165a: 46bd mov sp, r7 801165c: bc80 pop {r7} 801165e: 4770 bx lr 8011660: 20000084 .word 0x20000084 8011664: 10624dd3 .word 0x10624dd3 08011668 : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8011668: b580 push {r7, lr} 801166a: b088 sub sp, #32 801166c: af00 add r7, sp, #0 801166e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 8011670: 2300 movs r3, #0 8011672: 617b str r3, [r7, #20] 8011674: 2300 movs r3, #0 8011676: 613b str r3, [r7, #16] #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t pllactive = 0U; 8011678: 2300 movs r3, #0 801167a: 61fb str r3, [r7, #28] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 801167c: 687b ldr r3, [r7, #4] 801167e: 681b ldr r3, [r3, #0] 8011680: f003 0301 and.w r3, r3, #1 8011684: 2b00 cmp r3, #0 8011686: d07d beq.n 8011784 { FlagStatus pwrclkchanged = RESET; 8011688: 2300 movs r3, #0 801168a: 76fb strb r3, [r7, #27] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 801168c: 4b8b ldr r3, [pc, #556] @ (80118bc ) 801168e: 69db ldr r3, [r3, #28] 8011690: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011694: 2b00 cmp r3, #0 8011696: d10d bne.n 80116b4 { __HAL_RCC_PWR_CLK_ENABLE(); 8011698: 4b88 ldr r3, [pc, #544] @ (80118bc ) 801169a: 69db ldr r3, [r3, #28] 801169c: 4a87 ldr r2, [pc, #540] @ (80118bc ) 801169e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80116a2: 61d3 str r3, [r2, #28] 80116a4: 4b85 ldr r3, [pc, #532] @ (80118bc ) 80116a6: 69db ldr r3, [r3, #28] 80116a8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80116ac: 60fb str r3, [r7, #12] 80116ae: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 80116b0: 2301 movs r3, #1 80116b2: 76fb strb r3, [r7, #27] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80116b4: 4b82 ldr r3, [pc, #520] @ (80118c0 ) 80116b6: 681b ldr r3, [r3, #0] 80116b8: f403 7380 and.w r3, r3, #256 @ 0x100 80116bc: 2b00 cmp r3, #0 80116be: d118 bne.n 80116f2 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80116c0: 4b7f ldr r3, [pc, #508] @ (80118c0 ) 80116c2: 681b ldr r3, [r3, #0] 80116c4: 4a7e ldr r2, [pc, #504] @ (80118c0 ) 80116c6: f443 7380 orr.w r3, r3, #256 @ 0x100 80116ca: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80116cc: f7fc fe34 bl 800e338 80116d0: 6178 str r0, [r7, #20] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80116d2: e008 b.n 80116e6 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80116d4: f7fc fe30 bl 800e338 80116d8: 4602 mov r2, r0 80116da: 697b ldr r3, [r7, #20] 80116dc: 1ad3 subs r3, r2, r3 80116de: 2b64 cmp r3, #100 @ 0x64 80116e0: d901 bls.n 80116e6 { return HAL_TIMEOUT; 80116e2: 2303 movs r3, #3 80116e4: e0e5 b.n 80118b2 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80116e6: 4b76 ldr r3, [pc, #472] @ (80118c0 ) 80116e8: 681b ldr r3, [r3, #0] 80116ea: f403 7380 and.w r3, r3, #256 @ 0x100 80116ee: 2b00 cmp r3, #0 80116f0: d0f0 beq.n 80116d4 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 80116f2: 4b72 ldr r3, [pc, #456] @ (80118bc ) 80116f4: 6a1b ldr r3, [r3, #32] 80116f6: f403 7340 and.w r3, r3, #768 @ 0x300 80116fa: 613b str r3, [r7, #16] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 80116fc: 693b ldr r3, [r7, #16] 80116fe: 2b00 cmp r3, #0 8011700: d02e beq.n 8011760 8011702: 687b ldr r3, [r7, #4] 8011704: 685b ldr r3, [r3, #4] 8011706: f403 7340 and.w r3, r3, #768 @ 0x300 801170a: 693a ldr r2, [r7, #16] 801170c: 429a cmp r2, r3 801170e: d027 beq.n 8011760 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8011710: 4b6a ldr r3, [pc, #424] @ (80118bc ) 8011712: 6a1b ldr r3, [r3, #32] 8011714: f423 7340 bic.w r3, r3, #768 @ 0x300 8011718: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 801171a: 4b6a ldr r3, [pc, #424] @ (80118c4 ) 801171c: 2201 movs r2, #1 801171e: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8011720: 4b68 ldr r3, [pc, #416] @ (80118c4 ) 8011722: 2200 movs r2, #0 8011724: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 8011726: 4a65 ldr r2, [pc, #404] @ (80118bc ) 8011728: 693b ldr r3, [r7, #16] 801172a: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 801172c: 693b ldr r3, [r7, #16] 801172e: f003 0301 and.w r3, r3, #1 8011732: 2b00 cmp r3, #0 8011734: d014 beq.n 8011760 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8011736: f7fc fdff bl 800e338 801173a: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 801173c: e00a b.n 8011754 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 801173e: f7fc fdfb bl 800e338 8011742: 4602 mov r2, r0 8011744: 697b ldr r3, [r7, #20] 8011746: 1ad3 subs r3, r2, r3 8011748: f241 3288 movw r2, #5000 @ 0x1388 801174c: 4293 cmp r3, r2 801174e: d901 bls.n 8011754 { return HAL_TIMEOUT; 8011750: 2303 movs r3, #3 8011752: e0ae b.n 80118b2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8011754: 4b59 ldr r3, [pc, #356] @ (80118bc ) 8011756: 6a1b ldr r3, [r3, #32] 8011758: f003 0302 and.w r3, r3, #2 801175c: 2b00 cmp r3, #0 801175e: d0ee beq.n 801173e } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8011760: 4b56 ldr r3, [pc, #344] @ (80118bc ) 8011762: 6a1b ldr r3, [r3, #32] 8011764: f423 7240 bic.w r2, r3, #768 @ 0x300 8011768: 687b ldr r3, [r7, #4] 801176a: 685b ldr r3, [r3, #4] 801176c: 4953 ldr r1, [pc, #332] @ (80118bc ) 801176e: 4313 orrs r3, r2 8011770: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8011772: 7efb ldrb r3, [r7, #27] 8011774: 2b01 cmp r3, #1 8011776: d105 bne.n 8011784 { __HAL_RCC_PWR_CLK_DISABLE(); 8011778: 4b50 ldr r3, [pc, #320] @ (80118bc ) 801177a: 69db ldr r3, [r3, #28] 801177c: 4a4f ldr r2, [pc, #316] @ (80118bc ) 801177e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8011782: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8011784: 687b ldr r3, [r7, #4] 8011786: 681b ldr r3, [r3, #0] 8011788: f003 0302 and.w r3, r3, #2 801178c: 2b00 cmp r3, #0 801178e: d008 beq.n 80117a2 { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8011790: 4b4a ldr r3, [pc, #296] @ (80118bc ) 8011792: 685b ldr r3, [r3, #4] 8011794: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8011798: 687b ldr r3, [r7, #4] 801179a: 689b ldr r3, [r3, #8] 801179c: 4947 ldr r1, [pc, #284] @ (80118bc ) 801179e: 4313 orrs r3, r2 80117a0: 604b str r3, [r1, #4] } #if defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ I2S2 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) 80117a2: 687b ldr r3, [r7, #4] 80117a4: 681b ldr r3, [r3, #0] 80117a6: f003 0304 and.w r3, r3, #4 80117aa: 2b00 cmp r3, #0 80117ac: d008 beq.n 80117c0 { /* Check the parameters */ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); /* Configure the I2S2 clock source */ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); 80117ae: 4b43 ldr r3, [pc, #268] @ (80118bc ) 80117b0: 6adb ldr r3, [r3, #44] @ 0x2c 80117b2: f423 3200 bic.w r2, r3, #131072 @ 0x20000 80117b6: 687b ldr r3, [r7, #4] 80117b8: 68db ldr r3, [r3, #12] 80117ba: 4940 ldr r1, [pc, #256] @ (80118bc ) 80117bc: 4313 orrs r3, r2 80117be: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ I2S3 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) 80117c0: 687b ldr r3, [r7, #4] 80117c2: 681b ldr r3, [r3, #0] 80117c4: f003 0308 and.w r3, r3, #8 80117c8: 2b00 cmp r3, #0 80117ca: d008 beq.n 80117de { /* Check the parameters */ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); /* Configure the I2S3 clock source */ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); 80117cc: 4b3b ldr r3, [pc, #236] @ (80118bc ) 80117ce: 6adb ldr r3, [r3, #44] @ 0x2c 80117d0: f423 2280 bic.w r2, r3, #262144 @ 0x40000 80117d4: 687b ldr r3, [r7, #4] 80117d6: 691b ldr r3, [r3, #16] 80117d8: 4938 ldr r1, [pc, #224] @ (80118bc ) 80117da: 4313 orrs r3, r2 80117dc: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ PLL I2S Configuration ----------------------*/ /* Check that PLLI2S need to be enabled */ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) 80117de: 4b37 ldr r3, [pc, #220] @ (80118bc ) 80117e0: 6adb ldr r3, [r3, #44] @ 0x2c 80117e2: f403 3300 and.w r3, r3, #131072 @ 0x20000 80117e6: 2b00 cmp r3, #0 80117e8: d105 bne.n 80117f6 80117ea: 4b34 ldr r3, [pc, #208] @ (80118bc ) 80117ec: 6adb ldr r3, [r3, #44] @ 0x2c 80117ee: f403 2380 and.w r3, r3, #262144 @ 0x40000 80117f2: 2b00 cmp r3, #0 80117f4: d001 beq.n 80117fa { /* Update flag to indicate that PLL I2S should be active */ pllactive = 1; 80117f6: 2301 movs r3, #1 80117f8: 61fb str r3, [r7, #28] } /* Check if PLL I2S need to be enabled */ if (pllactive == 1) 80117fa: 69fb ldr r3, [r7, #28] 80117fc: 2b01 cmp r3, #1 80117fe: d148 bne.n 8011892 { /* Enable PLL I2S only if not active */ if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) 8011800: 4b2e ldr r3, [pc, #184] @ (80118bc ) 8011802: 681b ldr r3, [r3, #0] 8011804: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011808: 2b00 cmp r3, #0 801180a: d138 bne.n 801187e assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); /* Prediv2 can be written only when the PLL2 is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 801180c: 4b2b ldr r3, [pc, #172] @ (80118bc ) 801180e: 681b ldr r3, [r3, #0] 8011810: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8011814: 2b00 cmp r3, #0 8011816: d009 beq.n 801182c (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) 8011818: 4b28 ldr r3, [pc, #160] @ (80118bc ) 801181a: 6adb ldr r3, [r3, #44] @ 0x2c 801181c: f003 02f0 and.w r2, r3, #240 @ 0xf0 8011820: 687b ldr r3, [r7, #4] 8011822: 699b ldr r3, [r3, #24] if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 8011824: 429a cmp r2, r3 8011826: d001 beq.n 801182c { return HAL_ERROR; 8011828: 2301 movs r3, #1 801182a: e042 b.n 80118b2 } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); 801182c: 4b23 ldr r3, [pc, #140] @ (80118bc ) 801182e: 6adb ldr r3, [r3, #44] @ 0x2c 8011830: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8011834: 687b ldr r3, [r7, #4] 8011836: 699b ldr r3, [r3, #24] 8011838: 4920 ldr r1, [pc, #128] @ (80118bc ) 801183a: 4313 orrs r3, r2 801183c: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); 801183e: 4b1f ldr r3, [pc, #124] @ (80118bc ) 8011840: 6adb ldr r3, [r3, #44] @ 0x2c 8011842: f423 4270 bic.w r2, r3, #61440 @ 0xf000 8011846: 687b ldr r3, [r7, #4] 8011848: 695b ldr r3, [r3, #20] 801184a: 491c ldr r1, [pc, #112] @ (80118bc ) 801184c: 4313 orrs r3, r2 801184e: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); 8011850: 4b1d ldr r3, [pc, #116] @ (80118c8 ) 8011852: 2201 movs r2, #1 8011854: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8011856: f7fc fd6f bl 800e338 801185a: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 801185c: e008 b.n 8011870 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 801185e: f7fc fd6b bl 800e338 8011862: 4602 mov r2, r0 8011864: 697b ldr r3, [r7, #20] 8011866: 1ad3 subs r3, r2, r3 8011868: 2b64 cmp r3, #100 @ 0x64 801186a: d901 bls.n 8011870 { return HAL_TIMEOUT; 801186c: 2303 movs r3, #3 801186e: e020 b.n 80118b2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8011870: 4b12 ldr r3, [pc, #72] @ (80118bc ) 8011872: 681b ldr r3, [r3, #0] 8011874: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8011878: 2b00 cmp r3, #0 801187a: d0f0 beq.n 801185e 801187c: e009 b.n 8011892 } } else { /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) 801187e: 4b0f ldr r3, [pc, #60] @ (80118bc ) 8011880: 6adb ldr r3, [r3, #44] @ 0x2c 8011882: f403 4270 and.w r2, r3, #61440 @ 0xf000 8011886: 687b ldr r3, [r7, #4] 8011888: 695b ldr r3, [r3, #20] 801188a: 429a cmp r2, r3 801188c: d001 beq.n 8011892 { return HAL_ERROR; 801188e: 2301 movs r3, #1 8011890: e00f b.n 80118b2 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8011892: 687b ldr r3, [r7, #4] 8011894: 681b ldr r3, [r3, #0] 8011896: f003 0310 and.w r3, r3, #16 801189a: 2b00 cmp r3, #0 801189c: d008 beq.n 80118b0 { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 801189e: 4b07 ldr r3, [pc, #28] @ (80118bc ) 80118a0: 685b ldr r3, [r3, #4] 80118a2: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 80118a6: 687b ldr r3, [r7, #4] 80118a8: 69db ldr r3, [r3, #28] 80118aa: 4904 ldr r1, [pc, #16] @ (80118bc ) 80118ac: 4313 orrs r3, r2 80118ae: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 80118b0: 2300 movs r3, #0 } 80118b2: 4618 mov r0, r3 80118b4: 3720 adds r7, #32 80118b6: 46bd mov sp, r7 80118b8: bd80 pop {r7, pc} 80118ba: bf00 nop 80118bc: 40021000 .word 0x40021000 80118c0: 40007000 .word 0x40007000 80118c4: 42420440 .word 0x42420440 80118c8: 42420070 .word 0x42420070 080118cc : * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 80118cc: b580 push {r7, lr} 80118ce: b08a sub sp, #40 @ 0x28 80118d0: af00 add r7, sp, #0 80118d2: 6078 str r0, [r7, #4] #if defined(STM32F105xC) || defined(STM32F107xC) static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; 80118d4: 2300 movs r3, #0 80118d6: 61fb str r3, [r7, #28] 80118d8: 2300 movs r3, #0 80118da: 627b str r3, [r7, #36] @ 0x24 80118dc: 2300 movs r3, #0 80118de: 61bb str r3, [r7, #24] uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; 80118e0: 2300 movs r3, #0 80118e2: 617b str r3, [r7, #20] 80118e4: 2300 movs r3, #0 80118e6: 613b str r3, [r7, #16] 80118e8: 2300 movs r3, #0 80118ea: 60fb str r3, [r7, #12] static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; static const uint8_t aPredivFactorTable[2U] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 80118ec: 2300 movs r3, #0 80118ee: 60bb str r3, [r7, #8] 80118f0: 2300 movs r3, #0 80118f2: 623b str r3, [r7, #32] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 80118f4: 687b ldr r3, [r7, #4] 80118f6: 3b01 subs r3, #1 80118f8: 2b0f cmp r3, #15 80118fa: f200 811d bhi.w 8011b38 80118fe: a201 add r2, pc, #4 @ (adr r2, 8011904 ) 8011900: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011904: 08011ab9 .word 0x08011ab9 8011908: 08011b1d .word 0x08011b1d 801190c: 08011b39 .word 0x08011b39 8011910: 08011a17 .word 0x08011a17 8011914: 08011b39 .word 0x08011b39 8011918: 08011b39 .word 0x08011b39 801191c: 08011b39 .word 0x08011b39 8011920: 08011a69 .word 0x08011a69 8011924: 08011b39 .word 0x08011b39 8011928: 08011b39 .word 0x08011b39 801192c: 08011b39 .word 0x08011b39 8011930: 08011b39 .word 0x08011b39 8011934: 08011b39 .word 0x08011b39 8011938: 08011b39 .word 0x08011b39 801193c: 08011b39 .word 0x08011b39 8011940: 08011945 .word 0x08011945 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_USB: { /* Get RCC configuration ------------------------------------------------------*/ temp_reg = RCC->CFGR; 8011944: 4b83 ldr r3, [pc, #524] @ (8011b54 ) 8011946: 685b ldr r3, [r3, #4] 8011948: 60bb str r3, [r7, #8] /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) 801194a: 4b82 ldr r3, [pc, #520] @ (8011b54 ) 801194c: 681b ldr r3, [r3, #0] 801194e: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8011952: 2b00 cmp r3, #0 8011954: f000 80f2 beq.w 8011b3c { pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8011958: 68bb ldr r3, [r7, #8] 801195a: 0c9b lsrs r3, r3, #18 801195c: f003 030f and.w r3, r3, #15 8011960: 4a7d ldr r2, [pc, #500] @ (8011b58 ) 8011962: 5cd3 ldrb r3, [r2, r3] 8011964: 61bb str r3, [r7, #24] if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8011966: 68bb ldr r3, [r7, #8] 8011968: f403 3380 and.w r3, r3, #65536 @ 0x10000 801196c: 2b00 cmp r3, #0 801196e: d03b beq.n 80119e8 { #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ || defined(STM32F100xE) prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 8011970: 4b78 ldr r3, [pc, #480] @ (8011b54 ) 8011972: 6adb ldr r3, [r3, #44] @ 0x2c 8011974: f003 030f and.w r3, r3, #15 8011978: 4a78 ldr r2, [pc, #480] @ (8011b5c ) 801197a: 5cd3 ldrb r3, [r2, r3] 801197c: 61fb str r3, [r7, #28] #else prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 801197e: 4b75 ldr r3, [pc, #468] @ (8011b54 ) 8011980: 6adb ldr r3, [r3, #44] @ 0x2c 8011982: f403 3380 and.w r3, r3, #65536 @ 0x10000 8011986: 2b00 cmp r3, #0 8011988: d01c beq.n 80119c4 { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 801198a: 4b72 ldr r3, [pc, #456] @ (8011b54 ) 801198c: 6adb ldr r3, [r3, #44] @ 0x2c 801198e: 091b lsrs r3, r3, #4 8011990: f003 030f and.w r3, r3, #15 8011994: 3301 adds r3, #1 8011996: 60fb str r3, [r7, #12] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 8011998: 4b6e ldr r3, [pc, #440] @ (8011b54 ) 801199a: 6adb ldr r3, [r3, #44] @ 0x2c 801199c: 0a1b lsrs r3, r3, #8 801199e: f003 030f and.w r3, r3, #15 80119a2: 3302 adds r3, #2 80119a4: 617b str r3, [r7, #20] pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); 80119a6: 4a6e ldr r2, [pc, #440] @ (8011b60 ) 80119a8: 68fb ldr r3, [r7, #12] 80119aa: fbb2 f3f3 udiv r3, r2, r3 80119ae: 697a ldr r2, [r7, #20] 80119b0: fb03 f202 mul.w r2, r3, r2 80119b4: 69fb ldr r3, [r7, #28] 80119b6: fbb2 f2f3 udiv r2, r2, r3 80119ba: 69bb ldr r3, [r7, #24] 80119bc: fb02 f303 mul.w r3, r2, r3 80119c0: 627b str r3, [r7, #36] @ 0x24 80119c2: e007 b.n 80119d4 } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); 80119c4: 4a66 ldr r2, [pc, #408] @ (8011b60 ) 80119c6: 69fb ldr r3, [r7, #28] 80119c8: fbb2 f2f3 udiv r2, r2, r3 80119cc: 69bb ldr r3, [r7, #24] 80119ce: fb02 f303 mul.w r3, r2, r3 80119d2: 627b str r3, [r7, #36] @ 0x24 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 80119d4: 4b60 ldr r3, [pc, #384] @ (8011b58 ) 80119d6: 7b5b ldrb r3, [r3, #13] 80119d8: 461a mov r2, r3 80119da: 69bb ldr r3, [r7, #24] 80119dc: 4293 cmp r3, r2 80119de: d108 bne.n 80119f2 { pllclk = pllclk / 2; 80119e0: 6a7b ldr r3, [r7, #36] @ 0x24 80119e2: 085b lsrs r3, r3, #1 80119e4: 627b str r3, [r7, #36] @ 0x24 80119e6: e004 b.n 80119f2 #endif /* STM32F105xC || STM32F107xC */ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 80119e8: 69bb ldr r3, [r7, #24] 80119ea: 4a5e ldr r2, [pc, #376] @ (8011b64 ) 80119ec: fb02 f303 mul.w r3, r2, r3 80119f0: 627b str r3, [r7, #36] @ 0x24 } /* Calcul of the USB frequency*/ #if defined(STM32F105xC) || defined(STM32F107xC) /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) 80119f2: 4b58 ldr r3, [pc, #352] @ (8011b54 ) 80119f4: 685b ldr r3, [r3, #4] 80119f6: f403 0380 and.w r3, r3, #4194304 @ 0x400000 80119fa: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 80119fe: d102 bne.n 8011a06 { /* Prescaler of 2 selected for USB */ frequency = pllclk; 8011a00: 6a7b ldr r3, [r7, #36] @ 0x24 8011a02: 623b str r3, [r7, #32] /* Prescaler of 1.5 selected for USB */ frequency = (pllclk * 2) / 3; } #endif } break; 8011a04: e09a b.n 8011b3c frequency = (2 * pllclk) / 3; 8011a06: 6a7b ldr r3, [r7, #36] @ 0x24 8011a08: 005b lsls r3, r3, #1 8011a0a: 4a57 ldr r2, [pc, #348] @ (8011b68 ) 8011a0c: fba2 2303 umull r2, r3, r2, r3 8011a10: 085b lsrs r3, r3, #1 8011a12: 623b str r3, [r7, #32] break; 8011a14: e092 b.n 8011b3c { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) 8011a16: 4b4f ldr r3, [pc, #316] @ (8011b54 ) 8011a18: 6adb ldr r3, [r3, #44] @ 0x2c 8011a1a: f403 3300 and.w r3, r3, #131072 @ 0x20000 8011a1e: 2b00 cmp r3, #0 8011a20: d103 bne.n 8011a2a { /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); 8011a22: f7ff fd15 bl 8011450 8011a26: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8011a28: e08a b.n 8011b40 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8011a2a: 4b4a ldr r3, [pc, #296] @ (8011b54 ) 8011a2c: 681b ldr r3, [r3, #0] 8011a2e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011a32: 2b00 cmp r3, #0 8011a34: f000 8084 beq.w 8011b40 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8011a38: 4b46 ldr r3, [pc, #280] @ (8011b54 ) 8011a3a: 6adb ldr r3, [r3, #44] @ 0x2c 8011a3c: 091b lsrs r3, r3, #4 8011a3e: f003 030f and.w r3, r3, #15 8011a42: 3301 adds r3, #1 8011a44: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 8011a46: 4b43 ldr r3, [pc, #268] @ (8011b54 ) 8011a48: 6adb ldr r3, [r3, #44] @ 0x2c 8011a4a: 0b1b lsrs r3, r3, #12 8011a4c: f003 030f and.w r3, r3, #15 8011a50: 3302 adds r3, #2 8011a52: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8011a54: 4a42 ldr r2, [pc, #264] @ (8011b60 ) 8011a56: 68fb ldr r3, [r7, #12] 8011a58: fbb2 f3f3 udiv r3, r2, r3 8011a5c: 693a ldr r2, [r7, #16] 8011a5e: fb02 f303 mul.w r3, r2, r3 8011a62: 005b lsls r3, r3, #1 8011a64: 623b str r3, [r7, #32] break; 8011a66: e06b b.n 8011b40 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) 8011a68: 4b3a ldr r3, [pc, #232] @ (8011b54 ) 8011a6a: 6adb ldr r3, [r3, #44] @ 0x2c 8011a6c: f403 2380 and.w r3, r3, #262144 @ 0x40000 8011a70: 2b00 cmp r3, #0 8011a72: d103 bne.n 8011a7c { /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); 8011a74: f7ff fcec bl 8011450 8011a78: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8011a7a: e063 b.n 8011b44 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8011a7c: 4b35 ldr r3, [pc, #212] @ (8011b54 ) 8011a7e: 681b ldr r3, [r3, #0] 8011a80: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011a84: 2b00 cmp r3, #0 8011a86: d05d beq.n 8011b44 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8011a88: 4b32 ldr r3, [pc, #200] @ (8011b54 ) 8011a8a: 6adb ldr r3, [r3, #44] @ 0x2c 8011a8c: 091b lsrs r3, r3, #4 8011a8e: f003 030f and.w r3, r3, #15 8011a92: 3301 adds r3, #1 8011a94: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 8011a96: 4b2f ldr r3, [pc, #188] @ (8011b54 ) 8011a98: 6adb ldr r3, [r3, #44] @ 0x2c 8011a9a: 0b1b lsrs r3, r3, #12 8011a9c: f003 030f and.w r3, r3, #15 8011aa0: 3302 adds r3, #2 8011aa2: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8011aa4: 4a2e ldr r2, [pc, #184] @ (8011b60 ) 8011aa6: 68fb ldr r3, [r7, #12] 8011aa8: fbb2 f3f3 udiv r3, r2, r3 8011aac: 693a ldr r2, [r7, #16] 8011aae: fb02 f303 mul.w r3, r2, r3 8011ab2: 005b lsls r3, r3, #1 8011ab4: 623b str r3, [r7, #32] break; 8011ab6: e045 b.n 8011b44 } #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ case RCC_PERIPHCLK_RTC: { /* Get RCC BDCR configuration ------------------------------------------------------*/ temp_reg = RCC->BDCR; 8011ab8: 4b26 ldr r3, [pc, #152] @ (8011b54 ) 8011aba: 6a1b ldr r3, [r3, #32] 8011abc: 60bb str r3, [r7, #8] /* Check if LSE is ready if RTC clock selection is LSE */ if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 8011abe: 68bb ldr r3, [r7, #8] 8011ac0: f403 7340 and.w r3, r3, #768 @ 0x300 8011ac4: f5b3 7f80 cmp.w r3, #256 @ 0x100 8011ac8: d108 bne.n 8011adc 8011aca: 68bb ldr r3, [r7, #8] 8011acc: f003 0302 and.w r3, r3, #2 8011ad0: 2b00 cmp r3, #0 8011ad2: d003 beq.n 8011adc { frequency = LSE_VALUE; 8011ad4: f44f 4300 mov.w r3, #32768 @ 0x8000 8011ad8: 623b str r3, [r7, #32] 8011ada: e01e b.n 8011b1a } /* Check if LSI is ready if RTC clock selection is LSI */ else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 8011adc: 68bb ldr r3, [r7, #8] 8011ade: f403 7340 and.w r3, r3, #768 @ 0x300 8011ae2: f5b3 7f00 cmp.w r3, #512 @ 0x200 8011ae6: d109 bne.n 8011afc 8011ae8: 4b1a ldr r3, [pc, #104] @ (8011b54 ) 8011aea: 6a5b ldr r3, [r3, #36] @ 0x24 8011aec: f003 0302 and.w r3, r3, #2 8011af0: 2b00 cmp r3, #0 8011af2: d003 beq.n 8011afc { frequency = LSI_VALUE; 8011af4: f649 4340 movw r3, #40000 @ 0x9c40 8011af8: 623b str r3, [r7, #32] 8011afa: e00e b.n 8011b1a } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 8011afc: 68bb ldr r3, [r7, #8] 8011afe: f403 7340 and.w r3, r3, #768 @ 0x300 8011b02: f5b3 7f40 cmp.w r3, #768 @ 0x300 8011b06: d11f bne.n 8011b48 8011b08: 4b12 ldr r3, [pc, #72] @ (8011b54 ) 8011b0a: 681b ldr r3, [r3, #0] 8011b0c: f403 3300 and.w r3, r3, #131072 @ 0x20000 8011b10: 2b00 cmp r3, #0 8011b12: d019 beq.n 8011b48 { frequency = HSE_VALUE / 128U; 8011b14: 4b15 ldr r3, [pc, #84] @ (8011b6c ) 8011b16: 623b str r3, [r7, #32] /* Clock not enabled for RTC*/ else { /* nothing to do: frequency already initialized to 0U */ } break; 8011b18: e016 b.n 8011b48 8011b1a: e015 b.n 8011b48 } case RCC_PERIPHCLK_ADC: { frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 8011b1c: f7ff fd72 bl 8011604 8011b20: 4602 mov r2, r0 8011b22: 4b0c ldr r3, [pc, #48] @ (8011b54 ) 8011b24: 685b ldr r3, [r3, #4] 8011b26: 0b9b lsrs r3, r3, #14 8011b28: f003 0303 and.w r3, r3, #3 8011b2c: 3301 adds r3, #1 8011b2e: 005b lsls r3, r3, #1 8011b30: fbb2 f3f3 udiv r3, r2, r3 8011b34: 623b str r3, [r7, #32] break; 8011b36: e008 b.n 8011b4a } default: { break; 8011b38: bf00 nop 8011b3a: e006 b.n 8011b4a break; 8011b3c: bf00 nop 8011b3e: e004 b.n 8011b4a break; 8011b40: bf00 nop 8011b42: e002 b.n 8011b4a break; 8011b44: bf00 nop 8011b46: e000 b.n 8011b4a break; 8011b48: bf00 nop } } return (frequency); 8011b4a: 6a3b ldr r3, [r7, #32] } 8011b4c: 4618 mov r0, r3 8011b4e: 3728 adds r7, #40 @ 0x28 8011b50: 46bd mov sp, r7 8011b52: bd80 pop {r7, pc} 8011b54: 40021000 .word 0x40021000 8011b58: 08017934 .word 0x08017934 8011b5c: 08017944 .word 0x08017944 8011b60: 017d7840 .word 0x017d7840 8011b64: 003d0900 .word 0x003d0900 8011b68: aaaaaaab .word 0xaaaaaaab 8011b6c: 0002faf0 .word 0x0002faf0 08011b70 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { 8011b70: b580 push {r7, lr} 8011b72: b084 sub sp, #16 8011b74: af00 add r7, sp, #0 8011b76: 6078 str r0, [r7, #4] uint32_t prescaler = 0U; 8011b78: 2300 movs r3, #0 8011b7a: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8011b7c: 687b ldr r3, [r7, #4] 8011b7e: 2b00 cmp r3, #0 8011b80: d101 bne.n 8011b86 { return HAL_ERROR; 8011b82: 2301 movs r3, #1 8011b84: e07a b.n 8011c7c { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else if (hrtc->State == HAL_RTC_STATE_RESET) 8011b86: 687b ldr r3, [r7, #4] 8011b88: 7c5b ldrb r3, [r3, #17] 8011b8a: b2db uxtb r3, r3 8011b8c: 2b00 cmp r3, #0 8011b8e: d105 bne.n 8011b9c { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; 8011b90: 687b ldr r3, [r7, #4] 8011b92: 2200 movs r2, #0 8011b94: 741a strb r2, [r3, #16] /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); 8011b96: 6878 ldr r0, [r7, #4] 8011b98: f7f9 ffba bl 800bb10 } #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; 8011b9c: 687b ldr r3, [r7, #4] 8011b9e: 2202 movs r2, #2 8011ba0: 745a strb r2, [r3, #17] /* Waiting for synchro */ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 8011ba2: 6878 ldr r0, [r7, #4] 8011ba4: f000 f870 bl 8011c88 8011ba8: 4603 mov r3, r0 8011baa: 2b00 cmp r3, #0 8011bac: d004 beq.n 8011bb8 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8011bae: 687b ldr r3, [r7, #4] 8011bb0: 2204 movs r2, #4 8011bb2: 745a strb r2, [r3, #17] return HAL_ERROR; 8011bb4: 2301 movs r3, #1 8011bb6: e061 b.n 8011c7c } /* Set Initialization mode */ if (RTC_EnterInitMode(hrtc) != HAL_OK) 8011bb8: 6878 ldr r0, [r7, #4] 8011bba: f000 f892 bl 8011ce2 8011bbe: 4603 mov r3, r0 8011bc0: 2b00 cmp r3, #0 8011bc2: d004 beq.n 8011bce { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8011bc4: 687b ldr r3, [r7, #4] 8011bc6: 2204 movs r2, #4 8011bc8: 745a strb r2, [r3, #17] return HAL_ERROR; 8011bca: 2301 movs r3, #1 8011bcc: e056 b.n 8011c7c } else { /* Clear Flags Bits */ CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); 8011bce: 687b ldr r3, [r7, #4] 8011bd0: 681b ldr r3, [r3, #0] 8011bd2: 685a ldr r2, [r3, #4] 8011bd4: 687b ldr r3, [r7, #4] 8011bd6: 681b ldr r3, [r3, #0] 8011bd8: f022 0207 bic.w r2, r2, #7 8011bdc: 605a str r2, [r3, #4] if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) 8011bde: 687b ldr r3, [r7, #4] 8011be0: 689b ldr r3, [r3, #8] 8011be2: 2b00 cmp r3, #0 8011be4: d005 beq.n 8011bf2 { /* Disable the selected Tamper pin */ CLEAR_BIT(BKP->CR, BKP_CR_TPE); 8011be6: 4b27 ldr r3, [pc, #156] @ (8011c84 ) 8011be8: 6b1b ldr r3, [r3, #48] @ 0x30 8011bea: 4a26 ldr r2, [pc, #152] @ (8011c84 ) 8011bec: f023 0301 bic.w r3, r3, #1 8011bf0: 6313 str r3, [r2, #48] @ 0x30 } /* Set the signal which will be routed to RTC Tamper pin*/ MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); 8011bf2: 4b24 ldr r3, [pc, #144] @ (8011c84 ) 8011bf4: 6adb ldr r3, [r3, #44] @ 0x2c 8011bf6: f423 7260 bic.w r2, r3, #896 @ 0x380 8011bfa: 687b ldr r3, [r7, #4] 8011bfc: 689b ldr r3, [r3, #8] 8011bfe: 4921 ldr r1, [pc, #132] @ (8011c84 ) 8011c00: 4313 orrs r3, r2 8011c02: 62cb str r3, [r1, #44] @ 0x2c if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) 8011c04: 687b ldr r3, [r7, #4] 8011c06: 685b ldr r3, [r3, #4] 8011c08: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8011c0c: d003 beq.n 8011c16 { /* RTC Prescaler provided directly by end-user*/ prescaler = hrtc->Init.AsynchPrediv; 8011c0e: 687b ldr r3, [r7, #4] 8011c10: 685b ldr r3, [r3, #4] 8011c12: 60fb str r3, [r7, #12] 8011c14: e00e b.n 8011c34 } else { /* RTC Prescaler will be automatically calculated to get 1 second timebase */ /* Get the RTCCLK frequency */ prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); 8011c16: 2001 movs r0, #1 8011c18: f7ff fe58 bl 80118cc 8011c1c: 60f8 str r0, [r7, #12] /* Check that RTC clock is enabled*/ if (prescaler == 0U) 8011c1e: 68fb ldr r3, [r7, #12] 8011c20: 2b00 cmp r3, #0 8011c22: d104 bne.n 8011c2e { /* Should not happen. Frequency is not available*/ hrtc->State = HAL_RTC_STATE_ERROR; 8011c24: 687b ldr r3, [r7, #4] 8011c26: 2204 movs r2, #4 8011c28: 745a strb r2, [r3, #17] return HAL_ERROR; 8011c2a: 2301 movs r3, #1 8011c2c: e026 b.n 8011c7c } else { /* RTC period = RTCCLK/(RTC_PR + 1) */ prescaler = prescaler - 1U; 8011c2e: 68fb ldr r3, [r7, #12] 8011c30: 3b01 subs r3, #1 8011c32: 60fb str r3, [r7, #12] } } /* Configure the RTC_PRLH / RTC_PRLL */ WRITE_REG(hrtc->Instance->PRLH, ((prescaler >> 16U) & RTC_PRLH_PRL)); 8011c34: 68fb ldr r3, [r7, #12] 8011c36: 0c1a lsrs r2, r3, #16 8011c38: 687b ldr r3, [r7, #4] 8011c3a: 681b ldr r3, [r3, #0] 8011c3c: f002 020f and.w r2, r2, #15 8011c40: 609a str r2, [r3, #8] WRITE_REG(hrtc->Instance->PRLL, (prescaler & RTC_PRLL_PRL)); 8011c42: 687b ldr r3, [r7, #4] 8011c44: 681b ldr r3, [r3, #0] 8011c46: 68fa ldr r2, [r7, #12] 8011c48: b292 uxth r2, r2 8011c4a: 60da str r2, [r3, #12] /* Wait for synchro */ if (RTC_ExitInitMode(hrtc) != HAL_OK) 8011c4c: 6878 ldr r0, [r7, #4] 8011c4e: f000 f870 bl 8011d32 8011c52: 4603 mov r3, r0 8011c54: 2b00 cmp r3, #0 8011c56: d004 beq.n 8011c62 { hrtc->State = HAL_RTC_STATE_ERROR; 8011c58: 687b ldr r3, [r7, #4] 8011c5a: 2204 movs r2, #4 8011c5c: 745a strb r2, [r3, #17] return HAL_ERROR; 8011c5e: 2301 movs r3, #1 8011c60: e00c b.n 8011c7c } /* Initialize date to 1st of January 2000 */ hrtc->DateToUpdate.Year = 0x00U; 8011c62: 687b ldr r3, [r7, #4] 8011c64: 2200 movs r2, #0 8011c66: 73da strb r2, [r3, #15] hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; 8011c68: 687b ldr r3, [r7, #4] 8011c6a: 2201 movs r2, #1 8011c6c: 735a strb r2, [r3, #13] hrtc->DateToUpdate.Date = 0x01U; 8011c6e: 687b ldr r3, [r7, #4] 8011c70: 2201 movs r2, #1 8011c72: 739a strb r2, [r3, #14] /* Set RTC state */ hrtc->State = HAL_RTC_STATE_READY; 8011c74: 687b ldr r3, [r7, #4] 8011c76: 2201 movs r2, #1 8011c78: 745a strb r2, [r3, #17] return HAL_OK; 8011c7a: 2300 movs r3, #0 } } 8011c7c: 4618 mov r0, r3 8011c7e: 3710 adds r7, #16 8011c80: 46bd mov sp, r7 8011c82: bd80 pop {r7, pc} 8011c84: 40006c00 .word 0x40006c00 08011c88 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { 8011c88: b580 push {r7, lr} 8011c8a: b084 sub sp, #16 8011c8c: af00 add r7, sp, #0 8011c8e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8011c90: 2300 movs r3, #0 8011c92: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8011c94: 687b ldr r3, [r7, #4] 8011c96: 2b00 cmp r3, #0 8011c98: d101 bne.n 8011c9e { return HAL_ERROR; 8011c9a: 2301 movs r3, #1 8011c9c: e01d b.n 8011cda } /* Clear RSF flag */ CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); 8011c9e: 687b ldr r3, [r7, #4] 8011ca0: 681b ldr r3, [r3, #0] 8011ca2: 685a ldr r2, [r3, #4] 8011ca4: 687b ldr r3, [r7, #4] 8011ca6: 681b ldr r3, [r3, #0] 8011ca8: f022 0208 bic.w r2, r2, #8 8011cac: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8011cae: f7fc fb43 bl 800e338 8011cb2: 60f8 str r0, [r7, #12] /* Wait the registers to be synchronised */ while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8011cb4: e009 b.n 8011cca { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8011cb6: f7fc fb3f bl 800e338 8011cba: 4602 mov r2, r0 8011cbc: 68fb ldr r3, [r7, #12] 8011cbe: 1ad3 subs r3, r2, r3 8011cc0: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8011cc4: d901 bls.n 8011cca { return HAL_TIMEOUT; 8011cc6: 2303 movs r3, #3 8011cc8: e007 b.n 8011cda while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8011cca: 687b ldr r3, [r7, #4] 8011ccc: 681b ldr r3, [r3, #0] 8011cce: 685b ldr r3, [r3, #4] 8011cd0: f003 0308 and.w r3, r3, #8 8011cd4: 2b00 cmp r3, #0 8011cd6: d0ee beq.n 8011cb6 } } return HAL_OK; 8011cd8: 2300 movs r3, #0 } 8011cda: 4618 mov r0, r3 8011cdc: 3710 adds r7, #16 8011cde: 46bd mov sp, r7 8011ce0: bd80 pop {r7, pc} 08011ce2 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { 8011ce2: b580 push {r7, lr} 8011ce4: b084 sub sp, #16 8011ce6: af00 add r7, sp, #0 8011ce8: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8011cea: 2300 movs r3, #0 8011cec: 60fb str r3, [r7, #12] tickstart = HAL_GetTick(); 8011cee: f7fc fb23 bl 800e338 8011cf2: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8011cf4: e009 b.n 8011d0a { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8011cf6: f7fc fb1f bl 800e338 8011cfa: 4602 mov r2, r0 8011cfc: 68fb ldr r3, [r7, #12] 8011cfe: 1ad3 subs r3, r2, r3 8011d00: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8011d04: d901 bls.n 8011d0a { return HAL_TIMEOUT; 8011d06: 2303 movs r3, #3 8011d08: e00f b.n 8011d2a while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8011d0a: 687b ldr r3, [r7, #4] 8011d0c: 681b ldr r3, [r3, #0] 8011d0e: 685b ldr r3, [r3, #4] 8011d10: f003 0320 and.w r3, r3, #32 8011d14: 2b00 cmp r3, #0 8011d16: d0ee beq.n 8011cf6 } } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 8011d18: 687b ldr r3, [r7, #4] 8011d1a: 681b ldr r3, [r3, #0] 8011d1c: 685a ldr r2, [r3, #4] 8011d1e: 687b ldr r3, [r7, #4] 8011d20: 681b ldr r3, [r3, #0] 8011d22: f042 0210 orr.w r2, r2, #16 8011d26: 605a str r2, [r3, #4] return HAL_OK; 8011d28: 2300 movs r3, #0 } 8011d2a: 4618 mov r0, r3 8011d2c: 3710 adds r7, #16 8011d2e: 46bd mov sp, r7 8011d30: bd80 pop {r7, pc} 08011d32 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) { 8011d32: b580 push {r7, lr} 8011d34: b084 sub sp, #16 8011d36: af00 add r7, sp, #0 8011d38: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8011d3a: 2300 movs r3, #0 8011d3c: 60fb str r3, [r7, #12] /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 8011d3e: 687b ldr r3, [r7, #4] 8011d40: 681b ldr r3, [r3, #0] 8011d42: 685a ldr r2, [r3, #4] 8011d44: 687b ldr r3, [r7, #4] 8011d46: 681b ldr r3, [r3, #0] 8011d48: f022 0210 bic.w r2, r2, #16 8011d4c: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8011d4e: f7fc faf3 bl 800e338 8011d52: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8011d54: e009 b.n 8011d6a { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8011d56: f7fc faef bl 800e338 8011d5a: 4602 mov r2, r0 8011d5c: 68fb ldr r3, [r7, #12] 8011d5e: 1ad3 subs r3, r2, r3 8011d60: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8011d64: d901 bls.n 8011d6a { return HAL_TIMEOUT; 8011d66: 2303 movs r3, #3 8011d68: e007 b.n 8011d7a while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8011d6a: 687b ldr r3, [r7, #4] 8011d6c: 681b ldr r3, [r3, #0] 8011d6e: 685b ldr r3, [r3, #4] 8011d70: f003 0320 and.w r3, r3, #32 8011d74: 2b00 cmp r3, #0 8011d76: d0ee beq.n 8011d56 } } return HAL_OK; 8011d78: 2300 movs r3, #0 } 8011d7a: 4618 mov r0, r3 8011d7c: 3710 adds r7, #16 8011d7e: 46bd mov sp, r7 8011d80: bd80 pop {r7, pc} 08011d82 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8011d82: b580 push {r7, lr} 8011d84: b082 sub sp, #8 8011d86: af00 add r7, sp, #0 8011d88: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8011d8a: 687b ldr r3, [r7, #4] 8011d8c: 2b00 cmp r3, #0 8011d8e: d101 bne.n 8011d94 { return HAL_ERROR; 8011d90: 2301 movs r3, #1 8011d92: e041 b.n 8011e18 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8011d94: 687b ldr r3, [r7, #4] 8011d96: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8011d9a: b2db uxtb r3, r3 8011d9c: 2b00 cmp r3, #0 8011d9e: d106 bne.n 8011dae { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8011da0: 687b ldr r3, [r7, #4] 8011da2: 2200 movs r2, #0 8011da4: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8011da8: 6878 ldr r0, [r7, #4] 8011daa: f7fb ff01 bl 800dbb0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8011dae: 687b ldr r3, [r7, #4] 8011db0: 2202 movs r2, #2 8011db2: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8011db6: 687b ldr r3, [r7, #4] 8011db8: 681a ldr r2, [r3, #0] 8011dba: 687b ldr r3, [r7, #4] 8011dbc: 3304 adds r3, #4 8011dbe: 4619 mov r1, r3 8011dc0: 4610 mov r0, r2 8011dc2: f000 fd33 bl 801282c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8011dc6: 687b ldr r3, [r7, #4] 8011dc8: 2201 movs r2, #1 8011dca: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011dce: 687b ldr r3, [r7, #4] 8011dd0: 2201 movs r2, #1 8011dd2: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011dd6: 687b ldr r3, [r7, #4] 8011dd8: 2201 movs r2, #1 8011dda: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011dde: 687b ldr r3, [r7, #4] 8011de0: 2201 movs r2, #1 8011de2: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011de6: 687b ldr r3, [r7, #4] 8011de8: 2201 movs r2, #1 8011dea: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011dee: 687b ldr r3, [r7, #4] 8011df0: 2201 movs r2, #1 8011df2: f883 2042 strb.w r2, [r3, #66] @ 0x42 8011df6: 687b ldr r3, [r7, #4] 8011df8: 2201 movs r2, #1 8011dfa: f883 2043 strb.w r2, [r3, #67] @ 0x43 8011dfe: 687b ldr r3, [r7, #4] 8011e00: 2201 movs r2, #1 8011e02: f883 2044 strb.w r2, [r3, #68] @ 0x44 8011e06: 687b ldr r3, [r7, #4] 8011e08: 2201 movs r2, #1 8011e0a: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8011e0e: 687b ldr r3, [r7, #4] 8011e10: 2201 movs r2, #1 8011e12: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8011e16: 2300 movs r3, #0 } 8011e18: 4618 mov r0, r3 8011e1a: 3708 adds r7, #8 8011e1c: 46bd mov sp, r7 8011e1e: bd80 pop {r7, pc} 08011e20 : * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { 8011e20: b580 push {r7, lr} 8011e22: b082 sub sp, #8 8011e24: af00 add r7, sp, #0 8011e26: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8011e28: 687b ldr r3, [r7, #4] 8011e2a: 2b00 cmp r3, #0 8011e2c: d101 bne.n 8011e32 { return HAL_ERROR; 8011e2e: 2301 movs r3, #1 8011e30: e041 b.n 8011eb6 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8011e32: 687b ldr r3, [r7, #4] 8011e34: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8011e38: b2db uxtb r3, r3 8011e3a: 2b00 cmp r3, #0 8011e3c: d106 bne.n 8011e4c { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8011e3e: 687b ldr r3, [r7, #4] 8011e40: 2200 movs r2, #0 8011e42: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); 8011e46: 6878 ldr r0, [r7, #4] 8011e48: f000 f839 bl 8011ebe #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8011e4c: 687b ldr r3, [r7, #4] 8011e4e: 2202 movs r2, #2 8011e50: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8011e54: 687b ldr r3, [r7, #4] 8011e56: 681a ldr r2, [r3, #0] 8011e58: 687b ldr r3, [r7, #4] 8011e5a: 3304 adds r3, #4 8011e5c: 4619 mov r1, r3 8011e5e: 4610 mov r0, r2 8011e60: f000 fce4 bl 801282c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8011e64: 687b ldr r3, [r7, #4] 8011e66: 2201 movs r2, #1 8011e68: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011e6c: 687b ldr r3, [r7, #4] 8011e6e: 2201 movs r2, #1 8011e70: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011e74: 687b ldr r3, [r7, #4] 8011e76: 2201 movs r2, #1 8011e78: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011e7c: 687b ldr r3, [r7, #4] 8011e7e: 2201 movs r2, #1 8011e80: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011e84: 687b ldr r3, [r7, #4] 8011e86: 2201 movs r2, #1 8011e88: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011e8c: 687b ldr r3, [r7, #4] 8011e8e: 2201 movs r2, #1 8011e90: f883 2042 strb.w r2, [r3, #66] @ 0x42 8011e94: 687b ldr r3, [r7, #4] 8011e96: 2201 movs r2, #1 8011e98: f883 2043 strb.w r2, [r3, #67] @ 0x43 8011e9c: 687b ldr r3, [r7, #4] 8011e9e: 2201 movs r2, #1 8011ea0: f883 2044 strb.w r2, [r3, #68] @ 0x44 8011ea4: 687b ldr r3, [r7, #4] 8011ea6: 2201 movs r2, #1 8011ea8: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8011eac: 687b ldr r3, [r7, #4] 8011eae: 2201 movs r2, #1 8011eb0: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8011eb4: 2300 movs r3, #0 } 8011eb6: 4618 mov r0, r3 8011eb8: 3708 adds r7, #8 8011eba: 46bd mov sp, r7 8011ebc: bd80 pop {r7, pc} 08011ebe : * @brief Initializes the TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) { 8011ebe: b480 push {r7} 8011ec0: b083 sub sp, #12 8011ec2: af00 add r7, sp, #0 8011ec4: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspInit could be implemented in the user file */ } 8011ec6: bf00 nop 8011ec8: 370c adds r7, #12 8011eca: 46bd mov sp, r7 8011ecc: bc80 pop {r7} 8011ece: 4770 bx lr 08011ed0 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8011ed0: b580 push {r7, lr} 8011ed2: b084 sub sp, #16 8011ed4: af00 add r7, sp, #0 8011ed6: 6078 str r0, [r7, #4] 8011ed8: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 8011eda: 683b ldr r3, [r7, #0] 8011edc: 2b00 cmp r3, #0 8011ede: d109 bne.n 8011ef4 8011ee0: 687b ldr r3, [r7, #4] 8011ee2: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8011ee6: b2db uxtb r3, r3 8011ee8: 2b01 cmp r3, #1 8011eea: bf14 ite ne 8011eec: 2301 movne r3, #1 8011eee: 2300 moveq r3, #0 8011ef0: b2db uxtb r3, r3 8011ef2: e022 b.n 8011f3a 8011ef4: 683b ldr r3, [r7, #0] 8011ef6: 2b04 cmp r3, #4 8011ef8: d109 bne.n 8011f0e 8011efa: 687b ldr r3, [r7, #4] 8011efc: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8011f00: b2db uxtb r3, r3 8011f02: 2b01 cmp r3, #1 8011f04: bf14 ite ne 8011f06: 2301 movne r3, #1 8011f08: 2300 moveq r3, #0 8011f0a: b2db uxtb r3, r3 8011f0c: e015 b.n 8011f3a 8011f0e: 683b ldr r3, [r7, #0] 8011f10: 2b08 cmp r3, #8 8011f12: d109 bne.n 8011f28 8011f14: 687b ldr r3, [r7, #4] 8011f16: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8011f1a: b2db uxtb r3, r3 8011f1c: 2b01 cmp r3, #1 8011f1e: bf14 ite ne 8011f20: 2301 movne r3, #1 8011f22: 2300 moveq r3, #0 8011f24: b2db uxtb r3, r3 8011f26: e008 b.n 8011f3a 8011f28: 687b ldr r3, [r7, #4] 8011f2a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011f2e: b2db uxtb r3, r3 8011f30: 2b01 cmp r3, #1 8011f32: bf14 ite ne 8011f34: 2301 movne r3, #1 8011f36: 2300 moveq r3, #0 8011f38: b2db uxtb r3, r3 8011f3a: 2b00 cmp r3, #0 8011f3c: d001 beq.n 8011f42 { return HAL_ERROR; 8011f3e: 2301 movs r3, #1 8011f40: e063 b.n 801200a } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8011f42: 683b ldr r3, [r7, #0] 8011f44: 2b00 cmp r3, #0 8011f46: d104 bne.n 8011f52 8011f48: 687b ldr r3, [r7, #4] 8011f4a: 2202 movs r2, #2 8011f4c: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011f50: e013 b.n 8011f7a 8011f52: 683b ldr r3, [r7, #0] 8011f54: 2b04 cmp r3, #4 8011f56: d104 bne.n 8011f62 8011f58: 687b ldr r3, [r7, #4] 8011f5a: 2202 movs r2, #2 8011f5c: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011f60: e00b b.n 8011f7a 8011f62: 683b ldr r3, [r7, #0] 8011f64: 2b08 cmp r3, #8 8011f66: d104 bne.n 8011f72 8011f68: 687b ldr r3, [r7, #4] 8011f6a: 2202 movs r2, #2 8011f6c: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011f70: e003 b.n 8011f7a 8011f72: 687b ldr r3, [r7, #4] 8011f74: 2202 movs r2, #2 8011f76: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 8011f7a: 687b ldr r3, [r7, #4] 8011f7c: 681b ldr r3, [r3, #0] 8011f7e: 2201 movs r2, #1 8011f80: 6839 ldr r1, [r7, #0] 8011f82: 4618 mov r0, r3 8011f84: f000 fee8 bl 8012d58 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8011f88: 687b ldr r3, [r7, #4] 8011f8a: 681b ldr r3, [r3, #0] 8011f8c: 4a21 ldr r2, [pc, #132] @ (8012014 ) 8011f8e: 4293 cmp r3, r2 8011f90: d107 bne.n 8011fa2 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8011f92: 687b ldr r3, [r7, #4] 8011f94: 681b ldr r3, [r3, #0] 8011f96: 6c5a ldr r2, [r3, #68] @ 0x44 8011f98: 687b ldr r3, [r7, #4] 8011f9a: 681b ldr r3, [r3, #0] 8011f9c: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8011fa0: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8011fa2: 687b ldr r3, [r7, #4] 8011fa4: 681b ldr r3, [r3, #0] 8011fa6: 4a1b ldr r2, [pc, #108] @ (8012014 ) 8011fa8: 4293 cmp r3, r2 8011faa: d013 beq.n 8011fd4 8011fac: 687b ldr r3, [r7, #4] 8011fae: 681b ldr r3, [r3, #0] 8011fb0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8011fb4: d00e beq.n 8011fd4 8011fb6: 687b ldr r3, [r7, #4] 8011fb8: 681b ldr r3, [r3, #0] 8011fba: 4a17 ldr r2, [pc, #92] @ (8012018 ) 8011fbc: 4293 cmp r3, r2 8011fbe: d009 beq.n 8011fd4 8011fc0: 687b ldr r3, [r7, #4] 8011fc2: 681b ldr r3, [r3, #0] 8011fc4: 4a15 ldr r2, [pc, #84] @ (801201c ) 8011fc6: 4293 cmp r3, r2 8011fc8: d004 beq.n 8011fd4 8011fca: 687b ldr r3, [r7, #4] 8011fcc: 681b ldr r3, [r3, #0] 8011fce: 4a14 ldr r2, [pc, #80] @ (8012020 ) 8011fd0: 4293 cmp r3, r2 8011fd2: d111 bne.n 8011ff8 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8011fd4: 687b ldr r3, [r7, #4] 8011fd6: 681b ldr r3, [r3, #0] 8011fd8: 689b ldr r3, [r3, #8] 8011fda: f003 0307 and.w r3, r3, #7 8011fde: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8011fe0: 68fb ldr r3, [r7, #12] 8011fe2: 2b06 cmp r3, #6 8011fe4: d010 beq.n 8012008 { __HAL_TIM_ENABLE(htim); 8011fe6: 687b ldr r3, [r7, #4] 8011fe8: 681b ldr r3, [r3, #0] 8011fea: 681a ldr r2, [r3, #0] 8011fec: 687b ldr r3, [r7, #4] 8011fee: 681b ldr r3, [r3, #0] 8011ff0: f042 0201 orr.w r2, r2, #1 8011ff4: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8011ff6: e007 b.n 8012008 } } else { __HAL_TIM_ENABLE(htim); 8011ff8: 687b ldr r3, [r7, #4] 8011ffa: 681b ldr r3, [r3, #0] 8011ffc: 681a ldr r2, [r3, #0] 8011ffe: 687b ldr r3, [r7, #4] 8012000: 681b ldr r3, [r3, #0] 8012002: f042 0201 orr.w r2, r2, #1 8012006: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8012008: 2300 movs r3, #0 } 801200a: 4618 mov r0, r3 801200c: 3710 adds r7, #16 801200e: 46bd mov sp, r7 8012010: bd80 pop {r7, pc} 8012012: bf00 nop 8012014: 40012c00 .word 0x40012c00 8012018: 40000400 .word 0x40000400 801201c: 40000800 .word 0x40000800 8012020: 40000c00 .word 0x40000c00 08012024 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 8012024: b580 push {r7, lr} 8012026: b082 sub sp, #8 8012028: af00 add r7, sp, #0 801202a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 801202c: 687b ldr r3, [r7, #4] 801202e: 2b00 cmp r3, #0 8012030: d101 bne.n 8012036 { return HAL_ERROR; 8012032: 2301 movs r3, #1 8012034: e041 b.n 80120ba assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8012036: 687b ldr r3, [r7, #4] 8012038: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 801203c: b2db uxtb r3, r3 801203e: 2b00 cmp r3, #0 8012040: d106 bne.n 8012050 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8012042: 687b ldr r3, [r7, #4] 8012044: 2200 movs r2, #0 8012046: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 801204a: 6878 ldr r0, [r7, #4] 801204c: f000 f839 bl 80120c2 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8012050: 687b ldr r3, [r7, #4] 8012052: 2202 movs r2, #2 8012054: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8012058: 687b ldr r3, [r7, #4] 801205a: 681a ldr r2, [r3, #0] 801205c: 687b ldr r3, [r7, #4] 801205e: 3304 adds r3, #4 8012060: 4619 mov r1, r3 8012062: 4610 mov r0, r2 8012064: f000 fbe2 bl 801282c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8012068: 687b ldr r3, [r7, #4] 801206a: 2201 movs r2, #1 801206c: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8012070: 687b ldr r3, [r7, #4] 8012072: 2201 movs r2, #1 8012074: f883 203e strb.w r2, [r3, #62] @ 0x3e 8012078: 687b ldr r3, [r7, #4] 801207a: 2201 movs r2, #1 801207c: f883 203f strb.w r2, [r3, #63] @ 0x3f 8012080: 687b ldr r3, [r7, #4] 8012082: 2201 movs r2, #1 8012084: f883 2040 strb.w r2, [r3, #64] @ 0x40 8012088: 687b ldr r3, [r7, #4] 801208a: 2201 movs r2, #1 801208c: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8012090: 687b ldr r3, [r7, #4] 8012092: 2201 movs r2, #1 8012094: f883 2042 strb.w r2, [r3, #66] @ 0x42 8012098: 687b ldr r3, [r7, #4] 801209a: 2201 movs r2, #1 801209c: f883 2043 strb.w r2, [r3, #67] @ 0x43 80120a0: 687b ldr r3, [r7, #4] 80120a2: 2201 movs r2, #1 80120a4: f883 2044 strb.w r2, [r3, #68] @ 0x44 80120a8: 687b ldr r3, [r7, #4] 80120aa: 2201 movs r2, #1 80120ac: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80120b0: 687b ldr r3, [r7, #4] 80120b2: 2201 movs r2, #1 80120b4: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 80120b8: 2300 movs r3, #0 } 80120ba: 4618 mov r0, r3 80120bc: 3708 adds r7, #8 80120be: 46bd mov sp, r7 80120c0: bd80 pop {r7, pc} 080120c2 : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 80120c2: b480 push {r7} 80120c4: b083 sub sp, #12 80120c6: af00 add r7, sp, #0 80120c8: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 80120ca: bf00 nop 80120cc: 370c adds r7, #12 80120ce: 46bd mov sp, r7 80120d0: bc80 pop {r7} 80120d2: 4770 bx lr 080120d4 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 80120d4: b580 push {r7, lr} 80120d6: b084 sub sp, #16 80120d8: af00 add r7, sp, #0 80120da: 6078 str r0, [r7, #4] 80120dc: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 80120de: 683b ldr r3, [r7, #0] 80120e0: 2b00 cmp r3, #0 80120e2: d109 bne.n 80120f8 80120e4: 687b ldr r3, [r7, #4] 80120e6: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 80120ea: b2db uxtb r3, r3 80120ec: 2b01 cmp r3, #1 80120ee: bf14 ite ne 80120f0: 2301 movne r3, #1 80120f2: 2300 moveq r3, #0 80120f4: b2db uxtb r3, r3 80120f6: e022 b.n 801213e 80120f8: 683b ldr r3, [r7, #0] 80120fa: 2b04 cmp r3, #4 80120fc: d109 bne.n 8012112 80120fe: 687b ldr r3, [r7, #4] 8012100: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8012104: b2db uxtb r3, r3 8012106: 2b01 cmp r3, #1 8012108: bf14 ite ne 801210a: 2301 movne r3, #1 801210c: 2300 moveq r3, #0 801210e: b2db uxtb r3, r3 8012110: e015 b.n 801213e 8012112: 683b ldr r3, [r7, #0] 8012114: 2b08 cmp r3, #8 8012116: d109 bne.n 801212c 8012118: 687b ldr r3, [r7, #4] 801211a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 801211e: b2db uxtb r3, r3 8012120: 2b01 cmp r3, #1 8012122: bf14 ite ne 8012124: 2301 movne r3, #1 8012126: 2300 moveq r3, #0 8012128: b2db uxtb r3, r3 801212a: e008 b.n 801213e 801212c: 687b ldr r3, [r7, #4] 801212e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8012132: b2db uxtb r3, r3 8012134: 2b01 cmp r3, #1 8012136: bf14 ite ne 8012138: 2301 movne r3, #1 801213a: 2300 moveq r3, #0 801213c: b2db uxtb r3, r3 801213e: 2b00 cmp r3, #0 8012140: d001 beq.n 8012146 { return HAL_ERROR; 8012142: 2301 movs r3, #1 8012144: e063 b.n 801220e } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8012146: 683b ldr r3, [r7, #0] 8012148: 2b00 cmp r3, #0 801214a: d104 bne.n 8012156 801214c: 687b ldr r3, [r7, #4] 801214e: 2202 movs r2, #2 8012150: f883 203e strb.w r2, [r3, #62] @ 0x3e 8012154: e013 b.n 801217e 8012156: 683b ldr r3, [r7, #0] 8012158: 2b04 cmp r3, #4 801215a: d104 bne.n 8012166 801215c: 687b ldr r3, [r7, #4] 801215e: 2202 movs r2, #2 8012160: f883 203f strb.w r2, [r3, #63] @ 0x3f 8012164: e00b b.n 801217e 8012166: 683b ldr r3, [r7, #0] 8012168: 2b08 cmp r3, #8 801216a: d104 bne.n 8012176 801216c: 687b ldr r3, [r7, #4] 801216e: 2202 movs r2, #2 8012170: f883 2040 strb.w r2, [r3, #64] @ 0x40 8012174: e003 b.n 801217e 8012176: 687b ldr r3, [r7, #4] 8012178: 2202 movs r2, #2 801217a: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 801217e: 687b ldr r3, [r7, #4] 8012180: 681b ldr r3, [r3, #0] 8012182: 2201 movs r2, #1 8012184: 6839 ldr r1, [r7, #0] 8012186: 4618 mov r0, r3 8012188: f000 fde6 bl 8012d58 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 801218c: 687b ldr r3, [r7, #4] 801218e: 681b ldr r3, [r3, #0] 8012190: 4a21 ldr r2, [pc, #132] @ (8012218 ) 8012192: 4293 cmp r3, r2 8012194: d107 bne.n 80121a6 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8012196: 687b ldr r3, [r7, #4] 8012198: 681b ldr r3, [r3, #0] 801219a: 6c5a ldr r2, [r3, #68] @ 0x44 801219c: 687b ldr r3, [r7, #4] 801219e: 681b ldr r3, [r3, #0] 80121a0: f442 4200 orr.w r2, r2, #32768 @ 0x8000 80121a4: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80121a6: 687b ldr r3, [r7, #4] 80121a8: 681b ldr r3, [r3, #0] 80121aa: 4a1b ldr r2, [pc, #108] @ (8012218 ) 80121ac: 4293 cmp r3, r2 80121ae: d013 beq.n 80121d8 80121b0: 687b ldr r3, [r7, #4] 80121b2: 681b ldr r3, [r3, #0] 80121b4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80121b8: d00e beq.n 80121d8 80121ba: 687b ldr r3, [r7, #4] 80121bc: 681b ldr r3, [r3, #0] 80121be: 4a17 ldr r2, [pc, #92] @ (801221c ) 80121c0: 4293 cmp r3, r2 80121c2: d009 beq.n 80121d8 80121c4: 687b ldr r3, [r7, #4] 80121c6: 681b ldr r3, [r3, #0] 80121c8: 4a15 ldr r2, [pc, #84] @ (8012220 ) 80121ca: 4293 cmp r3, r2 80121cc: d004 beq.n 80121d8 80121ce: 687b ldr r3, [r7, #4] 80121d0: 681b ldr r3, [r3, #0] 80121d2: 4a14 ldr r2, [pc, #80] @ (8012224 ) 80121d4: 4293 cmp r3, r2 80121d6: d111 bne.n 80121fc { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 80121d8: 687b ldr r3, [r7, #4] 80121da: 681b ldr r3, [r3, #0] 80121dc: 689b ldr r3, [r3, #8] 80121de: f003 0307 and.w r3, r3, #7 80121e2: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80121e4: 68fb ldr r3, [r7, #12] 80121e6: 2b06 cmp r3, #6 80121e8: d010 beq.n 801220c { __HAL_TIM_ENABLE(htim); 80121ea: 687b ldr r3, [r7, #4] 80121ec: 681b ldr r3, [r3, #0] 80121ee: 681a ldr r2, [r3, #0] 80121f0: 687b ldr r3, [r7, #4] 80121f2: 681b ldr r3, [r3, #0] 80121f4: f042 0201 orr.w r2, r2, #1 80121f8: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80121fa: e007 b.n 801220c } } else { __HAL_TIM_ENABLE(htim); 80121fc: 687b ldr r3, [r7, #4] 80121fe: 681b ldr r3, [r3, #0] 8012200: 681a ldr r2, [r3, #0] 8012202: 687b ldr r3, [r7, #4] 8012204: 681b ldr r3, [r3, #0] 8012206: f042 0201 orr.w r2, r2, #1 801220a: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 801220c: 2300 movs r3, #0 } 801220e: 4618 mov r0, r3 8012210: 3710 adds r7, #16 8012212: 46bd mov sp, r7 8012214: bd80 pop {r7, pc} 8012216: bf00 nop 8012218: 40012c00 .word 0x40012c00 801221c: 40000400 .word 0x40000400 8012220: 40000800 .word 0x40000800 8012224: 40000c00 .word 0x40000c00 08012228 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8012228: b580 push {r7, lr} 801222a: b084 sub sp, #16 801222c: af00 add r7, sp, #0 801222e: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 8012230: 687b ldr r3, [r7, #4] 8012232: 681b ldr r3, [r3, #0] 8012234: 68db ldr r3, [r3, #12] 8012236: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 8012238: 687b ldr r3, [r7, #4] 801223a: 681b ldr r3, [r3, #0] 801223c: 691b ldr r3, [r3, #16] 801223e: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 8012240: 68bb ldr r3, [r7, #8] 8012242: f003 0302 and.w r3, r3, #2 8012246: 2b00 cmp r3, #0 8012248: d020 beq.n 801228c { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 801224a: 68fb ldr r3, [r7, #12] 801224c: f003 0302 and.w r3, r3, #2 8012250: 2b00 cmp r3, #0 8012252: d01b beq.n 801228c { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 8012254: 687b ldr r3, [r7, #4] 8012256: 681b ldr r3, [r3, #0] 8012258: f06f 0202 mvn.w r2, #2 801225c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 801225e: 687b ldr r3, [r7, #4] 8012260: 2201 movs r2, #1 8012262: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8012264: 687b ldr r3, [r7, #4] 8012266: 681b ldr r3, [r3, #0] 8012268: 699b ldr r3, [r3, #24] 801226a: f003 0303 and.w r3, r3, #3 801226e: 2b00 cmp r3, #0 8012270: d003 beq.n 801227a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8012272: 6878 ldr r0, [r7, #4] 8012274: f000 fabf bl 80127f6 8012278: e005 b.n 8012286 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 801227a: 6878 ldr r0, [r7, #4] 801227c: f000 fab2 bl 80127e4 HAL_TIM_PWM_PulseFinishedCallback(htim); 8012280: 6878 ldr r0, [r7, #4] 8012282: f000 fac1 bl 8012808 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8012286: 687b ldr r3, [r7, #4] 8012288: 2200 movs r2, #0 801228a: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 801228c: 68bb ldr r3, [r7, #8] 801228e: f003 0304 and.w r3, r3, #4 8012292: 2b00 cmp r3, #0 8012294: d020 beq.n 80122d8 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 8012296: 68fb ldr r3, [r7, #12] 8012298: f003 0304 and.w r3, r3, #4 801229c: 2b00 cmp r3, #0 801229e: d01b beq.n 80122d8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 80122a0: 687b ldr r3, [r7, #4] 80122a2: 681b ldr r3, [r3, #0] 80122a4: f06f 0204 mvn.w r2, #4 80122a8: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 80122aa: 687b ldr r3, [r7, #4] 80122ac: 2202 movs r2, #2 80122ae: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 80122b0: 687b ldr r3, [r7, #4] 80122b2: 681b ldr r3, [r3, #0] 80122b4: 699b ldr r3, [r3, #24] 80122b6: f403 7340 and.w r3, r3, #768 @ 0x300 80122ba: 2b00 cmp r3, #0 80122bc: d003 beq.n 80122c6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80122be: 6878 ldr r0, [r7, #4] 80122c0: f000 fa99 bl 80127f6 80122c4: e005 b.n 80122d2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80122c6: 6878 ldr r0, [r7, #4] 80122c8: f000 fa8c bl 80127e4 HAL_TIM_PWM_PulseFinishedCallback(htim); 80122cc: 6878 ldr r0, [r7, #4] 80122ce: f000 fa9b bl 8012808 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80122d2: 687b ldr r3, [r7, #4] 80122d4: 2200 movs r2, #0 80122d6: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 80122d8: 68bb ldr r3, [r7, #8] 80122da: f003 0308 and.w r3, r3, #8 80122de: 2b00 cmp r3, #0 80122e0: d020 beq.n 8012324 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 80122e2: 68fb ldr r3, [r7, #12] 80122e4: f003 0308 and.w r3, r3, #8 80122e8: 2b00 cmp r3, #0 80122ea: d01b beq.n 8012324 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 80122ec: 687b ldr r3, [r7, #4] 80122ee: 681b ldr r3, [r3, #0] 80122f0: f06f 0208 mvn.w r2, #8 80122f4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 80122f6: 687b ldr r3, [r7, #4] 80122f8: 2204 movs r2, #4 80122fa: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 80122fc: 687b ldr r3, [r7, #4] 80122fe: 681b ldr r3, [r3, #0] 8012300: 69db ldr r3, [r3, #28] 8012302: f003 0303 and.w r3, r3, #3 8012306: 2b00 cmp r3, #0 8012308: d003 beq.n 8012312 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 801230a: 6878 ldr r0, [r7, #4] 801230c: f000 fa73 bl 80127f6 8012310: e005 b.n 801231e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8012312: 6878 ldr r0, [r7, #4] 8012314: f000 fa66 bl 80127e4 HAL_TIM_PWM_PulseFinishedCallback(htim); 8012318: 6878 ldr r0, [r7, #4] 801231a: f000 fa75 bl 8012808 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 801231e: 687b ldr r3, [r7, #4] 8012320: 2200 movs r2, #0 8012322: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 8012324: 68bb ldr r3, [r7, #8] 8012326: f003 0310 and.w r3, r3, #16 801232a: 2b00 cmp r3, #0 801232c: d020 beq.n 8012370 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 801232e: 68fb ldr r3, [r7, #12] 8012330: f003 0310 and.w r3, r3, #16 8012334: 2b00 cmp r3, #0 8012336: d01b beq.n 8012370 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 8012338: 687b ldr r3, [r7, #4] 801233a: 681b ldr r3, [r3, #0] 801233c: f06f 0210 mvn.w r2, #16 8012340: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8012342: 687b ldr r3, [r7, #4] 8012344: 2208 movs r2, #8 8012346: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8012348: 687b ldr r3, [r7, #4] 801234a: 681b ldr r3, [r3, #0] 801234c: 69db ldr r3, [r3, #28] 801234e: f403 7340 and.w r3, r3, #768 @ 0x300 8012352: 2b00 cmp r3, #0 8012354: d003 beq.n 801235e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8012356: 6878 ldr r0, [r7, #4] 8012358: f000 fa4d bl 80127f6 801235c: e005 b.n 801236a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 801235e: 6878 ldr r0, [r7, #4] 8012360: f000 fa40 bl 80127e4 HAL_TIM_PWM_PulseFinishedCallback(htim); 8012364: 6878 ldr r0, [r7, #4] 8012366: f000 fa4f bl 8012808 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 801236a: 687b ldr r3, [r7, #4] 801236c: 2200 movs r2, #0 801236e: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 8012370: 68bb ldr r3, [r7, #8] 8012372: f003 0301 and.w r3, r3, #1 8012376: 2b00 cmp r3, #0 8012378: d00c beq.n 8012394 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 801237a: 68fb ldr r3, [r7, #12] 801237c: f003 0301 and.w r3, r3, #1 8012380: 2b00 cmp r3, #0 8012382: d007 beq.n 8012394 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 8012384: 687b ldr r3, [r7, #4] 8012386: 681b ldr r3, [r3, #0] 8012388: f06f 0201 mvn.w r2, #1 801238c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 801238e: 6878 ldr r0, [r7, #4] 8012390: f000 fa1f bl 80127d2 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) 8012394: 68bb ldr r3, [r7, #8] 8012396: f003 0380 and.w r3, r3, #128 @ 0x80 801239a: 2b00 cmp r3, #0 801239c: d00c beq.n 80123b8 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 801239e: 68fb ldr r3, [r7, #12] 80123a0: f003 0380 and.w r3, r3, #128 @ 0x80 80123a4: 2b00 cmp r3, #0 80123a6: d007 beq.n 80123b8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); 80123a8: 687b ldr r3, [r7, #4] 80123aa: 681b ldr r3, [r3, #0] 80123ac: f06f 0280 mvn.w r2, #128 @ 0x80 80123b0: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 80123b2: 6878 ldr r0, [r7, #4] 80123b4: f000 fd63 bl 8012e7e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 80123b8: 68bb ldr r3, [r7, #8] 80123ba: f003 0340 and.w r3, r3, #64 @ 0x40 80123be: 2b00 cmp r3, #0 80123c0: d00c beq.n 80123dc { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 80123c2: 68fb ldr r3, [r7, #12] 80123c4: f003 0340 and.w r3, r3, #64 @ 0x40 80123c8: 2b00 cmp r3, #0 80123ca: d007 beq.n 80123dc { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 80123cc: 687b ldr r3, [r7, #4] 80123ce: 681b ldr r3, [r3, #0] 80123d0: f06f 0240 mvn.w r2, #64 @ 0x40 80123d4: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 80123d6: 6878 ldr r0, [r7, #4] 80123d8: f000 fa1f bl 801281a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 80123dc: 68bb ldr r3, [r7, #8] 80123de: f003 0320 and.w r3, r3, #32 80123e2: 2b00 cmp r3, #0 80123e4: d00c beq.n 8012400 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 80123e6: 68fb ldr r3, [r7, #12] 80123e8: f003 0320 and.w r3, r3, #32 80123ec: 2b00 cmp r3, #0 80123ee: d007 beq.n 8012400 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 80123f0: 687b ldr r3, [r7, #4] 80123f2: 681b ldr r3, [r3, #0] 80123f4: f06f 0220 mvn.w r2, #32 80123f8: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 80123fa: 6878 ldr r0, [r7, #4] 80123fc: f000 fd36 bl 8012e6c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8012400: bf00 nop 8012402: 3710 adds r7, #16 8012404: 46bd mov sp, r7 8012406: bd80 pop {r7, pc} 08012408 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8012408: b580 push {r7, lr} 801240a: b086 sub sp, #24 801240c: af00 add r7, sp, #0 801240e: 60f8 str r0, [r7, #12] 8012410: 60b9 str r1, [r7, #8] 8012412: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8012414: 2300 movs r3, #0 8012416: 75fb strb r3, [r7, #23] assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); 8012418: 68fb ldr r3, [r7, #12] 801241a: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 801241e: 2b01 cmp r3, #1 8012420: d101 bne.n 8012426 8012422: 2302 movs r3, #2 8012424: e048 b.n 80124b8 8012426: 68fb ldr r3, [r7, #12] 8012428: 2201 movs r2, #1 801242a: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 801242e: 687b ldr r3, [r7, #4] 8012430: 2b0c cmp r3, #12 8012432: d839 bhi.n 80124a8 8012434: a201 add r2, pc, #4 @ (adr r2, 801243c ) 8012436: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801243a: bf00 nop 801243c: 08012471 .word 0x08012471 8012440: 080124a9 .word 0x080124a9 8012444: 080124a9 .word 0x080124a9 8012448: 080124a9 .word 0x080124a9 801244c: 0801247f .word 0x0801247f 8012450: 080124a9 .word 0x080124a9 8012454: 080124a9 .word 0x080124a9 8012458: 080124a9 .word 0x080124a9 801245c: 0801248d .word 0x0801248d 8012460: 080124a9 .word 0x080124a9 8012464: 080124a9 .word 0x080124a9 8012468: 080124a9 .word 0x080124a9 801246c: 0801249b .word 0x0801249b { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8012470: 68fb ldr r3, [r7, #12] 8012472: 681b ldr r3, [r3, #0] 8012474: 68b9 ldr r1, [r7, #8] 8012476: 4618 mov r0, r3 8012478: f000 fa50 bl 801291c break; 801247c: e017 b.n 80124ae { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); 801247e: 68fb ldr r3, [r7, #12] 8012480: 681b ldr r3, [r3, #0] 8012482: 68b9 ldr r1, [r7, #8] 8012484: 4618 mov r0, r3 8012486: f000 faaf bl 80129e8 break; 801248a: e010 b.n 80124ae { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); 801248c: 68fb ldr r3, [r7, #12] 801248e: 681b ldr r3, [r3, #0] 8012490: 68b9 ldr r1, [r7, #8] 8012492: 4618 mov r0, r3 8012494: f000 fb12 bl 8012abc break; 8012498: e009 b.n 80124ae { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); 801249a: 68fb ldr r3, [r7, #12] 801249c: 681b ldr r3, [r3, #0] 801249e: 68b9 ldr r1, [r7, #8] 80124a0: 4618 mov r0, r3 80124a2: f000 fb75 bl 8012b90 break; 80124a6: e002 b.n 80124ae } default: status = HAL_ERROR; 80124a8: 2301 movs r3, #1 80124aa: 75fb strb r3, [r7, #23] break; 80124ac: bf00 nop } __HAL_UNLOCK(htim); 80124ae: 68fb ldr r3, [r7, #12] 80124b0: 2200 movs r2, #0 80124b2: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 80124b6: 7dfb ldrb r3, [r7, #23] } 80124b8: 4618 mov r0, r3 80124ba: 3718 adds r7, #24 80124bc: 46bd mov sp, r7 80124be: bd80 pop {r7, pc} 080124c0 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 80124c0: b580 push {r7, lr} 80124c2: b086 sub sp, #24 80124c4: af00 add r7, sp, #0 80124c6: 60f8 str r0, [r7, #12] 80124c8: 60b9 str r1, [r7, #8] 80124ca: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80124cc: 2300 movs r3, #0 80124ce: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 80124d0: 68fb ldr r3, [r7, #12] 80124d2: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80124d6: 2b01 cmp r3, #1 80124d8: d101 bne.n 80124de 80124da: 2302 movs r3, #2 80124dc: e0ae b.n 801263c 80124de: 68fb ldr r3, [r7, #12] 80124e0: 2201 movs r2, #1 80124e2: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 80124e6: 687b ldr r3, [r7, #4] 80124e8: 2b0c cmp r3, #12 80124ea: f200 809f bhi.w 801262c 80124ee: a201 add r2, pc, #4 @ (adr r2, 80124f4 ) 80124f0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80124f4: 08012529 .word 0x08012529 80124f8: 0801262d .word 0x0801262d 80124fc: 0801262d .word 0x0801262d 8012500: 0801262d .word 0x0801262d 8012504: 08012569 .word 0x08012569 8012508: 0801262d .word 0x0801262d 801250c: 0801262d .word 0x0801262d 8012510: 0801262d .word 0x0801262d 8012514: 080125ab .word 0x080125ab 8012518: 0801262d .word 0x0801262d 801251c: 0801262d .word 0x0801262d 8012520: 0801262d .word 0x0801262d 8012524: 080125eb .word 0x080125eb { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8012528: 68fb ldr r3, [r7, #12] 801252a: 681b ldr r3, [r3, #0] 801252c: 68b9 ldr r1, [r7, #8] 801252e: 4618 mov r0, r3 8012530: f000 f9f4 bl 801291c /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 8012534: 68fb ldr r3, [r7, #12] 8012536: 681b ldr r3, [r3, #0] 8012538: 699a ldr r2, [r3, #24] 801253a: 68fb ldr r3, [r7, #12] 801253c: 681b ldr r3, [r3, #0] 801253e: f042 0208 orr.w r2, r2, #8 8012542: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 8012544: 68fb ldr r3, [r7, #12] 8012546: 681b ldr r3, [r3, #0] 8012548: 699a ldr r2, [r3, #24] 801254a: 68fb ldr r3, [r7, #12] 801254c: 681b ldr r3, [r3, #0] 801254e: f022 0204 bic.w r2, r2, #4 8012552: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 8012554: 68fb ldr r3, [r7, #12] 8012556: 681b ldr r3, [r3, #0] 8012558: 6999 ldr r1, [r3, #24] 801255a: 68bb ldr r3, [r7, #8] 801255c: 691a ldr r2, [r3, #16] 801255e: 68fb ldr r3, [r7, #12] 8012560: 681b ldr r3, [r3, #0] 8012562: 430a orrs r2, r1 8012564: 619a str r2, [r3, #24] break; 8012566: e064 b.n 8012632 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8012568: 68fb ldr r3, [r7, #12] 801256a: 681b ldr r3, [r3, #0] 801256c: 68b9 ldr r1, [r7, #8] 801256e: 4618 mov r0, r3 8012570: f000 fa3a bl 80129e8 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8012574: 68fb ldr r3, [r7, #12] 8012576: 681b ldr r3, [r3, #0] 8012578: 699a ldr r2, [r3, #24] 801257a: 68fb ldr r3, [r7, #12] 801257c: 681b ldr r3, [r3, #0] 801257e: f442 6200 orr.w r2, r2, #2048 @ 0x800 8012582: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8012584: 68fb ldr r3, [r7, #12] 8012586: 681b ldr r3, [r3, #0] 8012588: 699a ldr r2, [r3, #24] 801258a: 68fb ldr r3, [r7, #12] 801258c: 681b ldr r3, [r3, #0] 801258e: f422 6280 bic.w r2, r2, #1024 @ 0x400 8012592: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8012594: 68fb ldr r3, [r7, #12] 8012596: 681b ldr r3, [r3, #0] 8012598: 6999 ldr r1, [r3, #24] 801259a: 68bb ldr r3, [r7, #8] 801259c: 691b ldr r3, [r3, #16] 801259e: 021a lsls r2, r3, #8 80125a0: 68fb ldr r3, [r7, #12] 80125a2: 681b ldr r3, [r3, #0] 80125a4: 430a orrs r2, r1 80125a6: 619a str r2, [r3, #24] break; 80125a8: e043 b.n 8012632 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 80125aa: 68fb ldr r3, [r7, #12] 80125ac: 681b ldr r3, [r3, #0] 80125ae: 68b9 ldr r1, [r7, #8] 80125b0: 4618 mov r0, r3 80125b2: f000 fa83 bl 8012abc /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 80125b6: 68fb ldr r3, [r7, #12] 80125b8: 681b ldr r3, [r3, #0] 80125ba: 69da ldr r2, [r3, #28] 80125bc: 68fb ldr r3, [r7, #12] 80125be: 681b ldr r3, [r3, #0] 80125c0: f042 0208 orr.w r2, r2, #8 80125c4: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 80125c6: 68fb ldr r3, [r7, #12] 80125c8: 681b ldr r3, [r3, #0] 80125ca: 69da ldr r2, [r3, #28] 80125cc: 68fb ldr r3, [r7, #12] 80125ce: 681b ldr r3, [r3, #0] 80125d0: f022 0204 bic.w r2, r2, #4 80125d4: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 80125d6: 68fb ldr r3, [r7, #12] 80125d8: 681b ldr r3, [r3, #0] 80125da: 69d9 ldr r1, [r3, #28] 80125dc: 68bb ldr r3, [r7, #8] 80125de: 691a ldr r2, [r3, #16] 80125e0: 68fb ldr r3, [r7, #12] 80125e2: 681b ldr r3, [r3, #0] 80125e4: 430a orrs r2, r1 80125e6: 61da str r2, [r3, #28] break; 80125e8: e023 b.n 8012632 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 80125ea: 68fb ldr r3, [r7, #12] 80125ec: 681b ldr r3, [r3, #0] 80125ee: 68b9 ldr r1, [r7, #8] 80125f0: 4618 mov r0, r3 80125f2: f000 facd bl 8012b90 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 80125f6: 68fb ldr r3, [r7, #12] 80125f8: 681b ldr r3, [r3, #0] 80125fa: 69da ldr r2, [r3, #28] 80125fc: 68fb ldr r3, [r7, #12] 80125fe: 681b ldr r3, [r3, #0] 8012600: f442 6200 orr.w r2, r2, #2048 @ 0x800 8012604: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 8012606: 68fb ldr r3, [r7, #12] 8012608: 681b ldr r3, [r3, #0] 801260a: 69da ldr r2, [r3, #28] 801260c: 68fb ldr r3, [r7, #12] 801260e: 681b ldr r3, [r3, #0] 8012610: f422 6280 bic.w r2, r2, #1024 @ 0x400 8012614: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 8012616: 68fb ldr r3, [r7, #12] 8012618: 681b ldr r3, [r3, #0] 801261a: 69d9 ldr r1, [r3, #28] 801261c: 68bb ldr r3, [r7, #8] 801261e: 691b ldr r3, [r3, #16] 8012620: 021a lsls r2, r3, #8 8012622: 68fb ldr r3, [r7, #12] 8012624: 681b ldr r3, [r3, #0] 8012626: 430a orrs r2, r1 8012628: 61da str r2, [r3, #28] break; 801262a: e002 b.n 8012632 } default: status = HAL_ERROR; 801262c: 2301 movs r3, #1 801262e: 75fb strb r3, [r7, #23] break; 8012630: bf00 nop } __HAL_UNLOCK(htim); 8012632: 68fb ldr r3, [r7, #12] 8012634: 2200 movs r2, #0 8012636: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 801263a: 7dfb ldrb r3, [r7, #23] } 801263c: 4618 mov r0, r3 801263e: 3718 adds r7, #24 8012640: 46bd mov sp, r7 8012642: bd80 pop {r7, pc} 08012644 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 8012644: b580 push {r7, lr} 8012646: b084 sub sp, #16 8012648: af00 add r7, sp, #0 801264a: 6078 str r0, [r7, #4] 801264c: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 801264e: 2300 movs r3, #0 8012650: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 8012652: 687b ldr r3, [r7, #4] 8012654: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8012658: 2b01 cmp r3, #1 801265a: d101 bne.n 8012660 801265c: 2302 movs r3, #2 801265e: e0b4 b.n 80127ca 8012660: 687b ldr r3, [r7, #4] 8012662: 2201 movs r2, #1 8012664: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 8012668: 687b ldr r3, [r7, #4] 801266a: 2202 movs r2, #2 801266c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 8012670: 687b ldr r3, [r7, #4] 8012672: 681b ldr r3, [r3, #0] 8012674: 689b ldr r3, [r3, #8] 8012676: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 8012678: 68bb ldr r3, [r7, #8] 801267a: f023 0377 bic.w r3, r3, #119 @ 0x77 801267e: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8012680: 68bb ldr r3, [r7, #8] 8012682: f423 437f bic.w r3, r3, #65280 @ 0xff00 8012686: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 8012688: 687b ldr r3, [r7, #4] 801268a: 681b ldr r3, [r3, #0] 801268c: 68ba ldr r2, [r7, #8] 801268e: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 8012690: 683b ldr r3, [r7, #0] 8012692: 681b ldr r3, [r3, #0] 8012694: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8012698: d03e beq.n 8012718 801269a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 801269e: f200 8087 bhi.w 80127b0 80126a2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80126a6: f000 8086 beq.w 80127b6 80126aa: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80126ae: d87f bhi.n 80127b0 80126b0: 2b70 cmp r3, #112 @ 0x70 80126b2: d01a beq.n 80126ea 80126b4: 2b70 cmp r3, #112 @ 0x70 80126b6: d87b bhi.n 80127b0 80126b8: 2b60 cmp r3, #96 @ 0x60 80126ba: d050 beq.n 801275e 80126bc: 2b60 cmp r3, #96 @ 0x60 80126be: d877 bhi.n 80127b0 80126c0: 2b50 cmp r3, #80 @ 0x50 80126c2: d03c beq.n 801273e 80126c4: 2b50 cmp r3, #80 @ 0x50 80126c6: d873 bhi.n 80127b0 80126c8: 2b40 cmp r3, #64 @ 0x40 80126ca: d058 beq.n 801277e 80126cc: 2b40 cmp r3, #64 @ 0x40 80126ce: d86f bhi.n 80127b0 80126d0: 2b30 cmp r3, #48 @ 0x30 80126d2: d064 beq.n 801279e 80126d4: 2b30 cmp r3, #48 @ 0x30 80126d6: d86b bhi.n 80127b0 80126d8: 2b20 cmp r3, #32 80126da: d060 beq.n 801279e 80126dc: 2b20 cmp r3, #32 80126de: d867 bhi.n 80127b0 80126e0: 2b00 cmp r3, #0 80126e2: d05c beq.n 801279e 80126e4: 2b10 cmp r3, #16 80126e6: d05a beq.n 801279e 80126e8: e062 b.n 80127b0 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80126ea: 687b ldr r3, [r7, #4] 80126ec: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 80126ee: 683b ldr r3, [r7, #0] 80126f0: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 80126f2: 683b ldr r3, [r7, #0] 80126f4: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 80126f6: 683b ldr r3, [r7, #0] 80126f8: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 80126fa: f000 fb0e bl 8012d1a /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 80126fe: 687b ldr r3, [r7, #4] 8012700: 681b ldr r3, [r3, #0] 8012702: 689b ldr r3, [r3, #8] 8012704: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 8012706: 68bb ldr r3, [r7, #8] 8012708: f043 0377 orr.w r3, r3, #119 @ 0x77 801270c: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 801270e: 687b ldr r3, [r7, #4] 8012710: 681b ldr r3, [r3, #0] 8012712: 68ba ldr r2, [r7, #8] 8012714: 609a str r2, [r3, #8] break; 8012716: e04f b.n 80127b8 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8012718: 687b ldr r3, [r7, #4] 801271a: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 801271c: 683b ldr r3, [r7, #0] 801271e: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 8012720: 683b ldr r3, [r7, #0] 8012722: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8012724: 683b ldr r3, [r7, #0] 8012726: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8012728: f000 faf7 bl 8012d1a /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 801272c: 687b ldr r3, [r7, #4] 801272e: 681b ldr r3, [r3, #0] 8012730: 689a ldr r2, [r3, #8] 8012732: 687b ldr r3, [r7, #4] 8012734: 681b ldr r3, [r3, #0] 8012736: f442 4280 orr.w r2, r2, #16384 @ 0x4000 801273a: 609a str r2, [r3, #8] break; 801273c: e03c b.n 80127b8 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 801273e: 687b ldr r3, [r7, #4] 8012740: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8012742: 683b ldr r3, [r7, #0] 8012744: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8012746: 683b ldr r3, [r7, #0] 8012748: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 801274a: 461a mov r2, r3 801274c: f000 fa6e bl 8012c2c TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 8012750: 687b ldr r3, [r7, #4] 8012752: 681b ldr r3, [r3, #0] 8012754: 2150 movs r1, #80 @ 0x50 8012756: 4618 mov r0, r3 8012758: f000 fac5 bl 8012ce6 break; 801275c: e02c b.n 80127b8 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 801275e: 687b ldr r3, [r7, #4] 8012760: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8012762: 683b ldr r3, [r7, #0] 8012764: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8012766: 683b ldr r3, [r7, #0] 8012768: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 801276a: 461a mov r2, r3 801276c: f000 fa8c bl 8012c88 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 8012770: 687b ldr r3, [r7, #4] 8012772: 681b ldr r3, [r3, #0] 8012774: 2160 movs r1, #96 @ 0x60 8012776: 4618 mov r0, r3 8012778: f000 fab5 bl 8012ce6 break; 801277c: e01c b.n 80127b8 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 801277e: 687b ldr r3, [r7, #4] 8012780: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8012782: 683b ldr r3, [r7, #0] 8012784: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8012786: 683b ldr r3, [r7, #0] 8012788: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 801278a: 461a mov r2, r3 801278c: f000 fa4e bl 8012c2c TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 8012790: 687b ldr r3, [r7, #4] 8012792: 681b ldr r3, [r3, #0] 8012794: 2140 movs r1, #64 @ 0x40 8012796: 4618 mov r0, r3 8012798: f000 faa5 bl 8012ce6 break; 801279c: e00c b.n 80127b8 case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 801279e: 687b ldr r3, [r7, #4] 80127a0: 681a ldr r2, [r3, #0] 80127a2: 683b ldr r3, [r7, #0] 80127a4: 681b ldr r3, [r3, #0] 80127a6: 4619 mov r1, r3 80127a8: 4610 mov r0, r2 80127aa: f000 fa9c bl 8012ce6 break; 80127ae: e003 b.n 80127b8 } default: status = HAL_ERROR; 80127b0: 2301 movs r3, #1 80127b2: 73fb strb r3, [r7, #15] break; 80127b4: e000 b.n 80127b8 break; 80127b6: bf00 nop } htim->State = HAL_TIM_STATE_READY; 80127b8: 687b ldr r3, [r7, #4] 80127ba: 2201 movs r2, #1 80127bc: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 80127c0: 687b ldr r3, [r7, #4] 80127c2: 2200 movs r2, #0 80127c4: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 80127c8: 7bfb ldrb r3, [r7, #15] } 80127ca: 4618 mov r0, r3 80127cc: 3710 adds r7, #16 80127ce: 46bd mov sp, r7 80127d0: bd80 pop {r7, pc} 080127d2 : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 80127d2: b480 push {r7} 80127d4: b083 sub sp, #12 80127d6: af00 add r7, sp, #0 80127d8: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } 80127da: bf00 nop 80127dc: 370c adds r7, #12 80127de: 46bd mov sp, r7 80127e0: bc80 pop {r7} 80127e2: 4770 bx lr 080127e4 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 80127e4: b480 push {r7} 80127e6: b083 sub sp, #12 80127e8: af00 add r7, sp, #0 80127ea: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 80127ec: bf00 nop 80127ee: 370c adds r7, #12 80127f0: 46bd mov sp, r7 80127f2: bc80 pop {r7} 80127f4: 4770 bx lr 080127f6 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 80127f6: b480 push {r7} 80127f8: b083 sub sp, #12 80127fa: af00 add r7, sp, #0 80127fc: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 80127fe: bf00 nop 8012800: 370c adds r7, #12 8012802: 46bd mov sp, r7 8012804: bc80 pop {r7} 8012806: 4770 bx lr 08012808 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8012808: b480 push {r7} 801280a: b083 sub sp, #12 801280c: af00 add r7, sp, #0 801280e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8012810: bf00 nop 8012812: 370c adds r7, #12 8012814: 46bd mov sp, r7 8012816: bc80 pop {r7} 8012818: 4770 bx lr 0801281a : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 801281a: b480 push {r7} 801281c: b083 sub sp, #12 801281e: af00 add r7, sp, #0 8012820: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 8012822: bf00 nop 8012824: 370c adds r7, #12 8012826: 46bd mov sp, r7 8012828: bc80 pop {r7} 801282a: 4770 bx lr 0801282c : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 801282c: b480 push {r7} 801282e: b085 sub sp, #20 8012830: af00 add r7, sp, #0 8012832: 6078 str r0, [r7, #4] 8012834: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8012836: 687b ldr r3, [r7, #4] 8012838: 681b ldr r3, [r3, #0] 801283a: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 801283c: 687b ldr r3, [r7, #4] 801283e: 4a33 ldr r2, [pc, #204] @ (801290c ) 8012840: 4293 cmp r3, r2 8012842: d00f beq.n 8012864 8012844: 687b ldr r3, [r7, #4] 8012846: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 801284a: d00b beq.n 8012864 801284c: 687b ldr r3, [r7, #4] 801284e: 4a30 ldr r2, [pc, #192] @ (8012910 ) 8012850: 4293 cmp r3, r2 8012852: d007 beq.n 8012864 8012854: 687b ldr r3, [r7, #4] 8012856: 4a2f ldr r2, [pc, #188] @ (8012914 ) 8012858: 4293 cmp r3, r2 801285a: d003 beq.n 8012864 801285c: 687b ldr r3, [r7, #4] 801285e: 4a2e ldr r2, [pc, #184] @ (8012918 ) 8012860: 4293 cmp r3, r2 8012862: d108 bne.n 8012876 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8012864: 68fb ldr r3, [r7, #12] 8012866: f023 0370 bic.w r3, r3, #112 @ 0x70 801286a: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 801286c: 683b ldr r3, [r7, #0] 801286e: 685b ldr r3, [r3, #4] 8012870: 68fa ldr r2, [r7, #12] 8012872: 4313 orrs r3, r2 8012874: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8012876: 687b ldr r3, [r7, #4] 8012878: 4a24 ldr r2, [pc, #144] @ (801290c ) 801287a: 4293 cmp r3, r2 801287c: d00f beq.n 801289e 801287e: 687b ldr r3, [r7, #4] 8012880: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8012884: d00b beq.n 801289e 8012886: 687b ldr r3, [r7, #4] 8012888: 4a21 ldr r2, [pc, #132] @ (8012910 ) 801288a: 4293 cmp r3, r2 801288c: d007 beq.n 801289e 801288e: 687b ldr r3, [r7, #4] 8012890: 4a20 ldr r2, [pc, #128] @ (8012914 ) 8012892: 4293 cmp r3, r2 8012894: d003 beq.n 801289e 8012896: 687b ldr r3, [r7, #4] 8012898: 4a1f ldr r2, [pc, #124] @ (8012918 ) 801289a: 4293 cmp r3, r2 801289c: d108 bne.n 80128b0 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 801289e: 68fb ldr r3, [r7, #12] 80128a0: f423 7340 bic.w r3, r3, #768 @ 0x300 80128a4: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80128a6: 683b ldr r3, [r7, #0] 80128a8: 68db ldr r3, [r3, #12] 80128aa: 68fa ldr r2, [r7, #12] 80128ac: 4313 orrs r3, r2 80128ae: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80128b0: 68fb ldr r3, [r7, #12] 80128b2: f023 0280 bic.w r2, r3, #128 @ 0x80 80128b6: 683b ldr r3, [r7, #0] 80128b8: 695b ldr r3, [r3, #20] 80128ba: 4313 orrs r3, r2 80128bc: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 80128be: 687b ldr r3, [r7, #4] 80128c0: 68fa ldr r2, [r7, #12] 80128c2: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 80128c4: 683b ldr r3, [r7, #0] 80128c6: 689a ldr r2, [r3, #8] 80128c8: 687b ldr r3, [r7, #4] 80128ca: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 80128cc: 683b ldr r3, [r7, #0] 80128ce: 681a ldr r2, [r3, #0] 80128d0: 687b ldr r3, [r7, #4] 80128d2: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80128d4: 687b ldr r3, [r7, #4] 80128d6: 4a0d ldr r2, [pc, #52] @ (801290c ) 80128d8: 4293 cmp r3, r2 80128da: d103 bne.n 80128e4 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 80128dc: 683b ldr r3, [r7, #0] 80128de: 691a ldr r2, [r3, #16] 80128e0: 687b ldr r3, [r7, #4] 80128e2: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 80128e4: 687b ldr r3, [r7, #4] 80128e6: 2201 movs r2, #1 80128e8: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 80128ea: 687b ldr r3, [r7, #4] 80128ec: 691b ldr r3, [r3, #16] 80128ee: f003 0301 and.w r3, r3, #1 80128f2: 2b00 cmp r3, #0 80128f4: d005 beq.n 8012902 { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 80128f6: 687b ldr r3, [r7, #4] 80128f8: 691b ldr r3, [r3, #16] 80128fa: f023 0201 bic.w r2, r3, #1 80128fe: 687b ldr r3, [r7, #4] 8012900: 611a str r2, [r3, #16] } } 8012902: bf00 nop 8012904: 3714 adds r7, #20 8012906: 46bd mov sp, r7 8012908: bc80 pop {r7} 801290a: 4770 bx lr 801290c: 40012c00 .word 0x40012c00 8012910: 40000400 .word 0x40000400 8012914: 40000800 .word 0x40000800 8012918: 40000c00 .word 0x40000c00 0801291c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 801291c: b480 push {r7} 801291e: b087 sub sp, #28 8012920: af00 add r7, sp, #0 8012922: 6078 str r0, [r7, #4] 8012924: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8012926: 687b ldr r3, [r7, #4] 8012928: 6a1b ldr r3, [r3, #32] 801292a: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 801292c: 687b ldr r3, [r7, #4] 801292e: 6a1b ldr r3, [r3, #32] 8012930: f023 0201 bic.w r2, r3, #1 8012934: 687b ldr r3, [r7, #4] 8012936: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8012938: 687b ldr r3, [r7, #4] 801293a: 685b ldr r3, [r3, #4] 801293c: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 801293e: 687b ldr r3, [r7, #4] 8012940: 699b ldr r3, [r3, #24] 8012942: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 8012944: 68fb ldr r3, [r7, #12] 8012946: f023 0370 bic.w r3, r3, #112 @ 0x70 801294a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 801294c: 68fb ldr r3, [r7, #12] 801294e: f023 0303 bic.w r3, r3, #3 8012952: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8012954: 683b ldr r3, [r7, #0] 8012956: 681b ldr r3, [r3, #0] 8012958: 68fa ldr r2, [r7, #12] 801295a: 4313 orrs r3, r2 801295c: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 801295e: 697b ldr r3, [r7, #20] 8012960: f023 0302 bic.w r3, r3, #2 8012964: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 8012966: 683b ldr r3, [r7, #0] 8012968: 689b ldr r3, [r3, #8] 801296a: 697a ldr r2, [r7, #20] 801296c: 4313 orrs r3, r2 801296e: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8012970: 687b ldr r3, [r7, #4] 8012972: 4a1c ldr r2, [pc, #112] @ (80129e4 ) 8012974: 4293 cmp r3, r2 8012976: d10c bne.n 8012992 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8012978: 697b ldr r3, [r7, #20] 801297a: f023 0308 bic.w r3, r3, #8 801297e: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8012980: 683b ldr r3, [r7, #0] 8012982: 68db ldr r3, [r3, #12] 8012984: 697a ldr r2, [r7, #20] 8012986: 4313 orrs r3, r2 8012988: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 801298a: 697b ldr r3, [r7, #20] 801298c: f023 0304 bic.w r3, r3, #4 8012990: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8012992: 687b ldr r3, [r7, #4] 8012994: 4a13 ldr r2, [pc, #76] @ (80129e4 ) 8012996: 4293 cmp r3, r2 8012998: d111 bne.n 80129be /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 801299a: 693b ldr r3, [r7, #16] 801299c: f423 7380 bic.w r3, r3, #256 @ 0x100 80129a0: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 80129a2: 693b ldr r3, [r7, #16] 80129a4: f423 7300 bic.w r3, r3, #512 @ 0x200 80129a8: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 80129aa: 683b ldr r3, [r7, #0] 80129ac: 695b ldr r3, [r3, #20] 80129ae: 693a ldr r2, [r7, #16] 80129b0: 4313 orrs r3, r2 80129b2: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 80129b4: 683b ldr r3, [r7, #0] 80129b6: 699b ldr r3, [r3, #24] 80129b8: 693a ldr r2, [r7, #16] 80129ba: 4313 orrs r3, r2 80129bc: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80129be: 687b ldr r3, [r7, #4] 80129c0: 693a ldr r2, [r7, #16] 80129c2: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80129c4: 687b ldr r3, [r7, #4] 80129c6: 68fa ldr r2, [r7, #12] 80129c8: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 80129ca: 683b ldr r3, [r7, #0] 80129cc: 685a ldr r2, [r3, #4] 80129ce: 687b ldr r3, [r7, #4] 80129d0: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80129d2: 687b ldr r3, [r7, #4] 80129d4: 697a ldr r2, [r7, #20] 80129d6: 621a str r2, [r3, #32] } 80129d8: bf00 nop 80129da: 371c adds r7, #28 80129dc: 46bd mov sp, r7 80129de: bc80 pop {r7} 80129e0: 4770 bx lr 80129e2: bf00 nop 80129e4: 40012c00 .word 0x40012c00 080129e8 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80129e8: b480 push {r7} 80129ea: b087 sub sp, #28 80129ec: af00 add r7, sp, #0 80129ee: 6078 str r0, [r7, #4] 80129f0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80129f2: 687b ldr r3, [r7, #4] 80129f4: 6a1b ldr r3, [r3, #32] 80129f6: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 80129f8: 687b ldr r3, [r7, #4] 80129fa: 6a1b ldr r3, [r3, #32] 80129fc: f023 0210 bic.w r2, r3, #16 8012a00: 687b ldr r3, [r7, #4] 8012a02: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8012a04: 687b ldr r3, [r7, #4] 8012a06: 685b ldr r3, [r3, #4] 8012a08: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8012a0a: 687b ldr r3, [r7, #4] 8012a0c: 699b ldr r3, [r3, #24] 8012a0e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 8012a10: 68fb ldr r3, [r7, #12] 8012a12: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8012a16: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8012a18: 68fb ldr r3, [r7, #12] 8012a1a: f423 7340 bic.w r3, r3, #768 @ 0x300 8012a1e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8012a20: 683b ldr r3, [r7, #0] 8012a22: 681b ldr r3, [r3, #0] 8012a24: 021b lsls r3, r3, #8 8012a26: 68fa ldr r2, [r7, #12] 8012a28: 4313 orrs r3, r2 8012a2a: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 8012a2c: 697b ldr r3, [r7, #20] 8012a2e: f023 0320 bic.w r3, r3, #32 8012a32: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 8012a34: 683b ldr r3, [r7, #0] 8012a36: 689b ldr r3, [r3, #8] 8012a38: 011b lsls r3, r3, #4 8012a3a: 697a ldr r2, [r7, #20] 8012a3c: 4313 orrs r3, r2 8012a3e: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 8012a40: 687b ldr r3, [r7, #4] 8012a42: 4a1d ldr r2, [pc, #116] @ (8012ab8 ) 8012a44: 4293 cmp r3, r2 8012a46: d10d bne.n 8012a64 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 8012a48: 697b ldr r3, [r7, #20] 8012a4a: f023 0380 bic.w r3, r3, #128 @ 0x80 8012a4e: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8012a50: 683b ldr r3, [r7, #0] 8012a52: 68db ldr r3, [r3, #12] 8012a54: 011b lsls r3, r3, #4 8012a56: 697a ldr r2, [r7, #20] 8012a58: 4313 orrs r3, r2 8012a5a: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8012a5c: 697b ldr r3, [r7, #20] 8012a5e: f023 0340 bic.w r3, r3, #64 @ 0x40 8012a62: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8012a64: 687b ldr r3, [r7, #4] 8012a66: 4a14 ldr r2, [pc, #80] @ (8012ab8 ) 8012a68: 4293 cmp r3, r2 8012a6a: d113 bne.n 8012a94 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8012a6c: 693b ldr r3, [r7, #16] 8012a6e: f423 6380 bic.w r3, r3, #1024 @ 0x400 8012a72: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8012a74: 693b ldr r3, [r7, #16] 8012a76: f423 6300 bic.w r3, r3, #2048 @ 0x800 8012a7a: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8012a7c: 683b ldr r3, [r7, #0] 8012a7e: 695b ldr r3, [r3, #20] 8012a80: 009b lsls r3, r3, #2 8012a82: 693a ldr r2, [r7, #16] 8012a84: 4313 orrs r3, r2 8012a86: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8012a88: 683b ldr r3, [r7, #0] 8012a8a: 699b ldr r3, [r3, #24] 8012a8c: 009b lsls r3, r3, #2 8012a8e: 693a ldr r2, [r7, #16] 8012a90: 4313 orrs r3, r2 8012a92: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012a94: 687b ldr r3, [r7, #4] 8012a96: 693a ldr r2, [r7, #16] 8012a98: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8012a9a: 687b ldr r3, [r7, #4] 8012a9c: 68fa ldr r2, [r7, #12] 8012a9e: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8012aa0: 683b ldr r3, [r7, #0] 8012aa2: 685a ldr r2, [r3, #4] 8012aa4: 687b ldr r3, [r7, #4] 8012aa6: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012aa8: 687b ldr r3, [r7, #4] 8012aaa: 697a ldr r2, [r7, #20] 8012aac: 621a str r2, [r3, #32] } 8012aae: bf00 nop 8012ab0: 371c adds r7, #28 8012ab2: 46bd mov sp, r7 8012ab4: bc80 pop {r7} 8012ab6: 4770 bx lr 8012ab8: 40012c00 .word 0x40012c00 08012abc : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012abc: b480 push {r7} 8012abe: b087 sub sp, #28 8012ac0: af00 add r7, sp, #0 8012ac2: 6078 str r0, [r7, #4] 8012ac4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8012ac6: 687b ldr r3, [r7, #4] 8012ac8: 6a1b ldr r3, [r3, #32] 8012aca: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8012acc: 687b ldr r3, [r7, #4] 8012ace: 6a1b ldr r3, [r3, #32] 8012ad0: f423 7280 bic.w r2, r3, #256 @ 0x100 8012ad4: 687b ldr r3, [r7, #4] 8012ad6: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8012ad8: 687b ldr r3, [r7, #4] 8012ada: 685b ldr r3, [r3, #4] 8012adc: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8012ade: 687b ldr r3, [r7, #4] 8012ae0: 69db ldr r3, [r3, #28] 8012ae2: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8012ae4: 68fb ldr r3, [r7, #12] 8012ae6: f023 0370 bic.w r3, r3, #112 @ 0x70 8012aea: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8012aec: 68fb ldr r3, [r7, #12] 8012aee: f023 0303 bic.w r3, r3, #3 8012af2: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8012af4: 683b ldr r3, [r7, #0] 8012af6: 681b ldr r3, [r3, #0] 8012af8: 68fa ldr r2, [r7, #12] 8012afa: 4313 orrs r3, r2 8012afc: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8012afe: 697b ldr r3, [r7, #20] 8012b00: f423 7300 bic.w r3, r3, #512 @ 0x200 8012b04: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 8012b06: 683b ldr r3, [r7, #0] 8012b08: 689b ldr r3, [r3, #8] 8012b0a: 021b lsls r3, r3, #8 8012b0c: 697a ldr r2, [r7, #20] 8012b0e: 4313 orrs r3, r2 8012b10: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8012b12: 687b ldr r3, [r7, #4] 8012b14: 4a1d ldr r2, [pc, #116] @ (8012b8c ) 8012b16: 4293 cmp r3, r2 8012b18: d10d bne.n 8012b36 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8012b1a: 697b ldr r3, [r7, #20] 8012b1c: f423 6300 bic.w r3, r3, #2048 @ 0x800 8012b20: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 8012b22: 683b ldr r3, [r7, #0] 8012b24: 68db ldr r3, [r3, #12] 8012b26: 021b lsls r3, r3, #8 8012b28: 697a ldr r2, [r7, #20] 8012b2a: 4313 orrs r3, r2 8012b2c: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8012b2e: 697b ldr r3, [r7, #20] 8012b30: f423 6380 bic.w r3, r3, #1024 @ 0x400 8012b34: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8012b36: 687b ldr r3, [r7, #4] 8012b38: 4a14 ldr r2, [pc, #80] @ (8012b8c ) 8012b3a: 4293 cmp r3, r2 8012b3c: d113 bne.n 8012b66 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8012b3e: 693b ldr r3, [r7, #16] 8012b40: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8012b44: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8012b46: 693b ldr r3, [r7, #16] 8012b48: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8012b4c: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8012b4e: 683b ldr r3, [r7, #0] 8012b50: 695b ldr r3, [r3, #20] 8012b52: 011b lsls r3, r3, #4 8012b54: 693a ldr r2, [r7, #16] 8012b56: 4313 orrs r3, r2 8012b58: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 8012b5a: 683b ldr r3, [r7, #0] 8012b5c: 699b ldr r3, [r3, #24] 8012b5e: 011b lsls r3, r3, #4 8012b60: 693a ldr r2, [r7, #16] 8012b62: 4313 orrs r3, r2 8012b64: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012b66: 687b ldr r3, [r7, #4] 8012b68: 693a ldr r2, [r7, #16] 8012b6a: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8012b6c: 687b ldr r3, [r7, #4] 8012b6e: 68fa ldr r2, [r7, #12] 8012b70: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8012b72: 683b ldr r3, [r7, #0] 8012b74: 685a ldr r2, [r3, #4] 8012b76: 687b ldr r3, [r7, #4] 8012b78: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012b7a: 687b ldr r3, [r7, #4] 8012b7c: 697a ldr r2, [r7, #20] 8012b7e: 621a str r2, [r3, #32] } 8012b80: bf00 nop 8012b82: 371c adds r7, #28 8012b84: 46bd mov sp, r7 8012b86: bc80 pop {r7} 8012b88: 4770 bx lr 8012b8a: bf00 nop 8012b8c: 40012c00 .word 0x40012c00 08012b90 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012b90: b480 push {r7} 8012b92: b087 sub sp, #28 8012b94: af00 add r7, sp, #0 8012b96: 6078 str r0, [r7, #4] 8012b98: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8012b9a: 687b ldr r3, [r7, #4] 8012b9c: 6a1b ldr r3, [r3, #32] 8012b9e: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8012ba0: 687b ldr r3, [r7, #4] 8012ba2: 6a1b ldr r3, [r3, #32] 8012ba4: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8012ba8: 687b ldr r3, [r7, #4] 8012baa: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8012bac: 687b ldr r3, [r7, #4] 8012bae: 685b ldr r3, [r3, #4] 8012bb0: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8012bb2: 687b ldr r3, [r7, #4] 8012bb4: 69db ldr r3, [r3, #28] 8012bb6: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8012bb8: 68fb ldr r3, [r7, #12] 8012bba: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8012bbe: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8012bc0: 68fb ldr r3, [r7, #12] 8012bc2: f423 7340 bic.w r3, r3, #768 @ 0x300 8012bc6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8012bc8: 683b ldr r3, [r7, #0] 8012bca: 681b ldr r3, [r3, #0] 8012bcc: 021b lsls r3, r3, #8 8012bce: 68fa ldr r2, [r7, #12] 8012bd0: 4313 orrs r3, r2 8012bd2: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8012bd4: 693b ldr r3, [r7, #16] 8012bd6: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8012bda: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8012bdc: 683b ldr r3, [r7, #0] 8012bde: 689b ldr r3, [r3, #8] 8012be0: 031b lsls r3, r3, #12 8012be2: 693a ldr r2, [r7, #16] 8012be4: 4313 orrs r3, r2 8012be6: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8012be8: 687b ldr r3, [r7, #4] 8012bea: 4a0f ldr r2, [pc, #60] @ (8012c28 ) 8012bec: 4293 cmp r3, r2 8012bee: d109 bne.n 8012c04 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8012bf0: 697b ldr r3, [r7, #20] 8012bf2: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8012bf6: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8012bf8: 683b ldr r3, [r7, #0] 8012bfa: 695b ldr r3, [r3, #20] 8012bfc: 019b lsls r3, r3, #6 8012bfe: 697a ldr r2, [r7, #20] 8012c00: 4313 orrs r3, r2 8012c02: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012c04: 687b ldr r3, [r7, #4] 8012c06: 697a ldr r2, [r7, #20] 8012c08: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8012c0a: 687b ldr r3, [r7, #4] 8012c0c: 68fa ldr r2, [r7, #12] 8012c0e: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8012c10: 683b ldr r3, [r7, #0] 8012c12: 685a ldr r2, [r3, #4] 8012c14: 687b ldr r3, [r7, #4] 8012c16: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012c18: 687b ldr r3, [r7, #4] 8012c1a: 693a ldr r2, [r7, #16] 8012c1c: 621a str r2, [r3, #32] } 8012c1e: bf00 nop 8012c20: 371c adds r7, #28 8012c22: 46bd mov sp, r7 8012c24: bc80 pop {r7} 8012c26: 4770 bx lr 8012c28: 40012c00 .word 0x40012c00 08012c2c : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8012c2c: b480 push {r7} 8012c2e: b087 sub sp, #28 8012c30: af00 add r7, sp, #0 8012c32: 60f8 str r0, [r7, #12] 8012c34: 60b9 str r1, [r7, #8] 8012c36: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8012c38: 68fb ldr r3, [r7, #12] 8012c3a: 6a1b ldr r3, [r3, #32] 8012c3c: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8012c3e: 68fb ldr r3, [r7, #12] 8012c40: 6a1b ldr r3, [r3, #32] 8012c42: f023 0201 bic.w r2, r3, #1 8012c46: 68fb ldr r3, [r7, #12] 8012c48: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8012c4a: 68fb ldr r3, [r7, #12] 8012c4c: 699b ldr r3, [r3, #24] 8012c4e: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8012c50: 693b ldr r3, [r7, #16] 8012c52: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8012c56: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8012c58: 687b ldr r3, [r7, #4] 8012c5a: 011b lsls r3, r3, #4 8012c5c: 693a ldr r2, [r7, #16] 8012c5e: 4313 orrs r3, r2 8012c60: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8012c62: 697b ldr r3, [r7, #20] 8012c64: f023 030a bic.w r3, r3, #10 8012c68: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8012c6a: 697a ldr r2, [r7, #20] 8012c6c: 68bb ldr r3, [r7, #8] 8012c6e: 4313 orrs r3, r2 8012c70: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8012c72: 68fb ldr r3, [r7, #12] 8012c74: 693a ldr r2, [r7, #16] 8012c76: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8012c78: 68fb ldr r3, [r7, #12] 8012c7a: 697a ldr r2, [r7, #20] 8012c7c: 621a str r2, [r3, #32] } 8012c7e: bf00 nop 8012c80: 371c adds r7, #28 8012c82: 46bd mov sp, r7 8012c84: bc80 pop {r7} 8012c86: 4770 bx lr 08012c88 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8012c88: b480 push {r7} 8012c8a: b087 sub sp, #28 8012c8c: af00 add r7, sp, #0 8012c8e: 60f8 str r0, [r7, #12] 8012c90: 60b9 str r1, [r7, #8] 8012c92: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8012c94: 68fb ldr r3, [r7, #12] 8012c96: 6a1b ldr r3, [r3, #32] 8012c98: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8012c9a: 68fb ldr r3, [r7, #12] 8012c9c: 6a1b ldr r3, [r3, #32] 8012c9e: f023 0210 bic.w r2, r3, #16 8012ca2: 68fb ldr r3, [r7, #12] 8012ca4: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8012ca6: 68fb ldr r3, [r7, #12] 8012ca8: 699b ldr r3, [r3, #24] 8012caa: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8012cac: 693b ldr r3, [r7, #16] 8012cae: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8012cb2: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8012cb4: 687b ldr r3, [r7, #4] 8012cb6: 031b lsls r3, r3, #12 8012cb8: 693a ldr r2, [r7, #16] 8012cba: 4313 orrs r3, r2 8012cbc: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8012cbe: 697b ldr r3, [r7, #20] 8012cc0: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8012cc4: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8012cc6: 68bb ldr r3, [r7, #8] 8012cc8: 011b lsls r3, r3, #4 8012cca: 697a ldr r2, [r7, #20] 8012ccc: 4313 orrs r3, r2 8012cce: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8012cd0: 68fb ldr r3, [r7, #12] 8012cd2: 693a ldr r2, [r7, #16] 8012cd4: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8012cd6: 68fb ldr r3, [r7, #12] 8012cd8: 697a ldr r2, [r7, #20] 8012cda: 621a str r2, [r3, #32] } 8012cdc: bf00 nop 8012cde: 371c adds r7, #28 8012ce0: 46bd mov sp, r7 8012ce2: bc80 pop {r7} 8012ce4: 4770 bx lr 08012ce6 : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8012ce6: b480 push {r7} 8012ce8: b085 sub sp, #20 8012cea: af00 add r7, sp, #0 8012cec: 6078 str r0, [r7, #4] 8012cee: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8012cf0: 687b ldr r3, [r7, #4] 8012cf2: 689b ldr r3, [r3, #8] 8012cf4: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8012cf6: 68fb ldr r3, [r7, #12] 8012cf8: f023 0370 bic.w r3, r3, #112 @ 0x70 8012cfc: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8012cfe: 683a ldr r2, [r7, #0] 8012d00: 68fb ldr r3, [r7, #12] 8012d02: 4313 orrs r3, r2 8012d04: f043 0307 orr.w r3, r3, #7 8012d08: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8012d0a: 687b ldr r3, [r7, #4] 8012d0c: 68fa ldr r2, [r7, #12] 8012d0e: 609a str r2, [r3, #8] } 8012d10: bf00 nop 8012d12: 3714 adds r7, #20 8012d14: 46bd mov sp, r7 8012d16: bc80 pop {r7} 8012d18: 4770 bx lr 08012d1a : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8012d1a: b480 push {r7} 8012d1c: b087 sub sp, #28 8012d1e: af00 add r7, sp, #0 8012d20: 60f8 str r0, [r7, #12] 8012d22: 60b9 str r1, [r7, #8] 8012d24: 607a str r2, [r7, #4] 8012d26: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8012d28: 68fb ldr r3, [r7, #12] 8012d2a: 689b ldr r3, [r3, #8] 8012d2c: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8012d2e: 697b ldr r3, [r7, #20] 8012d30: f423 437f bic.w r3, r3, #65280 @ 0xff00 8012d34: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8012d36: 683b ldr r3, [r7, #0] 8012d38: 021a lsls r2, r3, #8 8012d3a: 687b ldr r3, [r7, #4] 8012d3c: 431a orrs r2, r3 8012d3e: 68bb ldr r3, [r7, #8] 8012d40: 4313 orrs r3, r2 8012d42: 697a ldr r2, [r7, #20] 8012d44: 4313 orrs r3, r2 8012d46: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8012d48: 68fb ldr r3, [r7, #12] 8012d4a: 697a ldr r2, [r7, #20] 8012d4c: 609a str r2, [r3, #8] } 8012d4e: bf00 nop 8012d50: 371c adds r7, #28 8012d52: 46bd mov sp, r7 8012d54: bc80 pop {r7} 8012d56: 4770 bx lr 08012d58 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8012d58: b480 push {r7} 8012d5a: b087 sub sp, #28 8012d5c: af00 add r7, sp, #0 8012d5e: 60f8 str r0, [r7, #12] 8012d60: 60b9 str r1, [r7, #8] 8012d62: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8012d64: 68bb ldr r3, [r7, #8] 8012d66: f003 031f and.w r3, r3, #31 8012d6a: 2201 movs r2, #1 8012d6c: fa02 f303 lsl.w r3, r2, r3 8012d70: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 8012d72: 68fb ldr r3, [r7, #12] 8012d74: 6a1a ldr r2, [r3, #32] 8012d76: 697b ldr r3, [r7, #20] 8012d78: 43db mvns r3, r3 8012d7a: 401a ands r2, r3 8012d7c: 68fb ldr r3, [r7, #12] 8012d7e: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8012d80: 68fb ldr r3, [r7, #12] 8012d82: 6a1a ldr r2, [r3, #32] 8012d84: 68bb ldr r3, [r7, #8] 8012d86: f003 031f and.w r3, r3, #31 8012d8a: 6879 ldr r1, [r7, #4] 8012d8c: fa01 f303 lsl.w r3, r1, r3 8012d90: 431a orrs r2, r3 8012d92: 68fb ldr r3, [r7, #12] 8012d94: 621a str r2, [r3, #32] } 8012d96: bf00 nop 8012d98: 371c adds r7, #28 8012d9a: 46bd mov sp, r7 8012d9c: bc80 pop {r7} 8012d9e: 4770 bx lr 08012da0 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8012da0: b480 push {r7} 8012da2: b085 sub sp, #20 8012da4: af00 add r7, sp, #0 8012da6: 6078 str r0, [r7, #4] 8012da8: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8012daa: 687b ldr r3, [r7, #4] 8012dac: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8012db0: 2b01 cmp r3, #1 8012db2: d101 bne.n 8012db8 8012db4: 2302 movs r3, #2 8012db6: e04b b.n 8012e50 8012db8: 687b ldr r3, [r7, #4] 8012dba: 2201 movs r2, #1 8012dbc: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8012dc0: 687b ldr r3, [r7, #4] 8012dc2: 2202 movs r2, #2 8012dc4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8012dc8: 687b ldr r3, [r7, #4] 8012dca: 681b ldr r3, [r3, #0] 8012dcc: 685b ldr r3, [r3, #4] 8012dce: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8012dd0: 687b ldr r3, [r7, #4] 8012dd2: 681b ldr r3, [r3, #0] 8012dd4: 689b ldr r3, [r3, #8] 8012dd6: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8012dd8: 68fb ldr r3, [r7, #12] 8012dda: f023 0370 bic.w r3, r3, #112 @ 0x70 8012dde: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8012de0: 683b ldr r3, [r7, #0] 8012de2: 681b ldr r3, [r3, #0] 8012de4: 68fa ldr r2, [r7, #12] 8012de6: 4313 orrs r3, r2 8012de8: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8012dea: 687b ldr r3, [r7, #4] 8012dec: 681b ldr r3, [r3, #0] 8012dee: 68fa ldr r2, [r7, #12] 8012df0: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8012df2: 687b ldr r3, [r7, #4] 8012df4: 681b ldr r3, [r3, #0] 8012df6: 4a19 ldr r2, [pc, #100] @ (8012e5c ) 8012df8: 4293 cmp r3, r2 8012dfa: d013 beq.n 8012e24 8012dfc: 687b ldr r3, [r7, #4] 8012dfe: 681b ldr r3, [r3, #0] 8012e00: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8012e04: d00e beq.n 8012e24 8012e06: 687b ldr r3, [r7, #4] 8012e08: 681b ldr r3, [r3, #0] 8012e0a: 4a15 ldr r2, [pc, #84] @ (8012e60 ) 8012e0c: 4293 cmp r3, r2 8012e0e: d009 beq.n 8012e24 8012e10: 687b ldr r3, [r7, #4] 8012e12: 681b ldr r3, [r3, #0] 8012e14: 4a13 ldr r2, [pc, #76] @ (8012e64 ) 8012e16: 4293 cmp r3, r2 8012e18: d004 beq.n 8012e24 8012e1a: 687b ldr r3, [r7, #4] 8012e1c: 681b ldr r3, [r3, #0] 8012e1e: 4a12 ldr r2, [pc, #72] @ (8012e68 ) 8012e20: 4293 cmp r3, r2 8012e22: d10c bne.n 8012e3e { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8012e24: 68bb ldr r3, [r7, #8] 8012e26: f023 0380 bic.w r3, r3, #128 @ 0x80 8012e2a: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8012e2c: 683b ldr r3, [r7, #0] 8012e2e: 685b ldr r3, [r3, #4] 8012e30: 68ba ldr r2, [r7, #8] 8012e32: 4313 orrs r3, r2 8012e34: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8012e36: 687b ldr r3, [r7, #4] 8012e38: 681b ldr r3, [r3, #0] 8012e3a: 68ba ldr r2, [r7, #8] 8012e3c: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8012e3e: 687b ldr r3, [r7, #4] 8012e40: 2201 movs r2, #1 8012e42: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8012e46: 687b ldr r3, [r7, #4] 8012e48: 2200 movs r2, #0 8012e4a: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8012e4e: 2300 movs r3, #0 } 8012e50: 4618 mov r0, r3 8012e52: 3714 adds r7, #20 8012e54: 46bd mov sp, r7 8012e56: bc80 pop {r7} 8012e58: 4770 bx lr 8012e5a: bf00 nop 8012e5c: 40012c00 .word 0x40012c00 8012e60: 40000400 .word 0x40000400 8012e64: 40000800 .word 0x40000800 8012e68: 40000c00 .word 0x40000c00 08012e6c : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8012e6c: b480 push {r7} 8012e6e: b083 sub sp, #12 8012e70: af00 add r7, sp, #0 8012e72: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8012e74: bf00 nop 8012e76: 370c adds r7, #12 8012e78: 46bd mov sp, r7 8012e7a: bc80 pop {r7} 8012e7c: 4770 bx lr 08012e7e : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8012e7e: b480 push {r7} 8012e80: b083 sub sp, #12 8012e82: af00 add r7, sp, #0 8012e84: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8012e86: bf00 nop 8012e88: 370c adds r7, #12 8012e8a: 46bd mov sp, r7 8012e8c: bc80 pop {r7} 8012e8e: 4770 bx lr 08012e90 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8012e90: b580 push {r7, lr} 8012e92: b082 sub sp, #8 8012e94: af00 add r7, sp, #0 8012e96: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8012e98: 687b ldr r3, [r7, #4] 8012e9a: 2b00 cmp r3, #0 8012e9c: d101 bne.n 8012ea2 { return HAL_ERROR; 8012e9e: 2301 movs r3, #1 8012ea0: e042 b.n 8012f28 assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 8012ea2: 687b ldr r3, [r7, #4] 8012ea4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8012ea8: b2db uxtb r3, r3 8012eaa: 2b00 cmp r3, #0 8012eac: d106 bne.n 8012ebc { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8012eae: 687b ldr r3, [r7, #4] 8012eb0: 2200 movs r2, #0 8012eb2: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8012eb6: 6878 ldr r0, [r7, #4] 8012eb8: f7fa ffc2 bl 800de40 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8012ebc: 687b ldr r3, [r7, #4] 8012ebe: 2224 movs r2, #36 @ 0x24 8012ec0: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8012ec4: 687b ldr r3, [r7, #4] 8012ec6: 681b ldr r3, [r3, #0] 8012ec8: 68da ldr r2, [r3, #12] 8012eca: 687b ldr r3, [r7, #4] 8012ecc: 681b ldr r3, [r3, #0] 8012ece: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8012ed2: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8012ed4: 6878 ldr r0, [r7, #4] 8012ed6: f001 f903 bl 80140e0 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8012eda: 687b ldr r3, [r7, #4] 8012edc: 681b ldr r3, [r3, #0] 8012ede: 691a ldr r2, [r3, #16] 8012ee0: 687b ldr r3, [r7, #4] 8012ee2: 681b ldr r3, [r3, #0] 8012ee4: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8012ee8: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8012eea: 687b ldr r3, [r7, #4] 8012eec: 681b ldr r3, [r3, #0] 8012eee: 695a ldr r2, [r3, #20] 8012ef0: 687b ldr r3, [r7, #4] 8012ef2: 681b ldr r3, [r3, #0] 8012ef4: f022 022a bic.w r2, r2, #42 @ 0x2a 8012ef8: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8012efa: 687b ldr r3, [r7, #4] 8012efc: 681b ldr r3, [r3, #0] 8012efe: 68da ldr r2, [r3, #12] 8012f00: 687b ldr r3, [r7, #4] 8012f02: 681b ldr r3, [r3, #0] 8012f04: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8012f08: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012f0a: 687b ldr r3, [r7, #4] 8012f0c: 2200 movs r2, #0 8012f0e: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8012f10: 687b ldr r3, [r7, #4] 8012f12: 2220 movs r2, #32 8012f14: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8012f18: 687b ldr r3, [r7, #4] 8012f1a: 2220 movs r2, #32 8012f1c: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8012f20: 687b ldr r3, [r7, #4] 8012f22: 2200 movs r2, #0 8012f24: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8012f26: 2300 movs r3, #0 } 8012f28: 4618 mov r0, r3 8012f2a: 3708 adds r7, #8 8012f2c: 46bd mov sp, r7 8012f2e: bd80 pop {r7, pc} 08012f30 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8012f30: b580 push {r7, lr} 8012f32: b08c sub sp, #48 @ 0x30 8012f34: af00 add r7, sp, #0 8012f36: 60f8 str r0, [r7, #12] 8012f38: 60b9 str r1, [r7, #8] 8012f3a: 4613 mov r3, r2 8012f3c: 80fb strh r3, [r7, #6] const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8012f3e: 68fb ldr r3, [r7, #12] 8012f40: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8012f44: b2db uxtb r3, r3 8012f46: 2b20 cmp r3, #32 8012f48: d156 bne.n 8012ff8 { if ((pData == NULL) || (Size == 0U)) 8012f4a: 68bb ldr r3, [r7, #8] 8012f4c: 2b00 cmp r3, #0 8012f4e: d002 beq.n 8012f56 8012f50: 88fb ldrh r3, [r7, #6] 8012f52: 2b00 cmp r3, #0 8012f54: d101 bne.n 8012f5a { return HAL_ERROR; 8012f56: 2301 movs r3, #1 8012f58: e04f b.n 8012ffa } huart->pTxBuffPtr = pData; 8012f5a: 68ba ldr r2, [r7, #8] 8012f5c: 68fb ldr r3, [r7, #12] 8012f5e: 621a str r2, [r3, #32] huart->TxXferSize = Size; 8012f60: 68fb ldr r3, [r7, #12] 8012f62: 88fa ldrh r2, [r7, #6] 8012f64: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8012f66: 68fb ldr r3, [r7, #12] 8012f68: 88fa ldrh r2, [r7, #6] 8012f6a: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 8012f6c: 68fb ldr r3, [r7, #12] 8012f6e: 2200 movs r2, #0 8012f70: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8012f72: 68fb ldr r3, [r7, #12] 8012f74: 2221 movs r2, #33 @ 0x21 8012f76: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 8012f7a: 68fb ldr r3, [r7, #12] 8012f7c: 6b9b ldr r3, [r3, #56] @ 0x38 8012f7e: 4a21 ldr r2, [pc, #132] @ (8013004 ) 8012f80: 629a str r2, [r3, #40] @ 0x28 /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 8012f82: 68fb ldr r3, [r7, #12] 8012f84: 6b9b ldr r3, [r3, #56] @ 0x38 8012f86: 4a20 ldr r2, [pc, #128] @ (8013008 ) 8012f88: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 8012f8a: 68fb ldr r3, [r7, #12] 8012f8c: 6b9b ldr r3, [r3, #56] @ 0x38 8012f8e: 4a1f ldr r2, [pc, #124] @ (801300c ) 8012f90: 631a str r2, [r3, #48] @ 0x30 /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 8012f92: 68fb ldr r3, [r7, #12] 8012f94: 6b9b ldr r3, [r3, #56] @ 0x38 8012f96: 2200 movs r2, #0 8012f98: 635a str r2, [r3, #52] @ 0x34 /* Enable the UART transmit DMA channel */ tmp = (const uint32_t *)&pData; 8012f9a: f107 0308 add.w r3, r7, #8 8012f9e: 62fb str r3, [r7, #44] @ 0x2c HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size); 8012fa0: 68fb ldr r3, [r7, #12] 8012fa2: 6b98 ldr r0, [r3, #56] @ 0x38 8012fa4: 6afb ldr r3, [r7, #44] @ 0x2c 8012fa6: 6819 ldr r1, [r3, #0] 8012fa8: 68fb ldr r3, [r7, #12] 8012faa: 681b ldr r3, [r3, #0] 8012fac: 3304 adds r3, #4 8012fae: 461a mov r2, r3 8012fb0: 88fb ldrh r3, [r7, #6] 8012fb2: f7fc ffa5 bl 800ff00 /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); 8012fb6: 68fb ldr r3, [r7, #12] 8012fb8: 681b ldr r3, [r3, #0] 8012fba: f06f 0240 mvn.w r2, #64 @ 0x40 8012fbe: 601a str r2, [r3, #0] /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8012fc0: 68fb ldr r3, [r7, #12] 8012fc2: 681b ldr r3, [r3, #0] 8012fc4: 3314 adds r3, #20 8012fc6: 61bb str r3, [r7, #24] */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012fc8: 69bb ldr r3, [r7, #24] 8012fca: e853 3f00 ldrex r3, [r3] 8012fce: 617b str r3, [r7, #20] return(result); 8012fd0: 697b ldr r3, [r7, #20] 8012fd2: f043 0380 orr.w r3, r3, #128 @ 0x80 8012fd6: 62bb str r3, [r7, #40] @ 0x28 8012fd8: 68fb ldr r3, [r7, #12] 8012fda: 681b ldr r3, [r3, #0] 8012fdc: 3314 adds r3, #20 8012fde: 6aba ldr r2, [r7, #40] @ 0x28 8012fe0: 627a str r2, [r7, #36] @ 0x24 8012fe2: 623b str r3, [r7, #32] */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012fe4: 6a39 ldr r1, [r7, #32] 8012fe6: 6a7a ldr r2, [r7, #36] @ 0x24 8012fe8: e841 2300 strex r3, r2, [r1] 8012fec: 61fb str r3, [r7, #28] return(result); 8012fee: 69fb ldr r3, [r7, #28] 8012ff0: 2b00 cmp r3, #0 8012ff2: d1e5 bne.n 8012fc0 return HAL_OK; 8012ff4: 2300 movs r3, #0 8012ff6: e000 b.n 8012ffa } else { return HAL_BUSY; 8012ff8: 2302 movs r3, #2 } } 8012ffa: 4618 mov r0, r3 8012ffc: 3730 adds r7, #48 @ 0x30 8012ffe: 46bd mov sp, r7 8013000: bd80 pop {r7, pc} 8013002: bf00 nop 8013004: 08013905 .word 0x08013905 8013008: 0801399f .word 0x0801399f 801300c: 08013b23 .word 0x08013b23 08013010 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8013010: b580 push {r7, lr} 8013012: b08c sub sp, #48 @ 0x30 8013014: af00 add r7, sp, #0 8013016: 60f8 str r0, [r7, #12] 8013018: 60b9 str r1, [r7, #8] 801301a: 4613 mov r3, r2 801301c: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 801301e: 68fb ldr r3, [r7, #12] 8013020: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8013024: b2db uxtb r3, r3 8013026: 2b20 cmp r3, #32 8013028: d14a bne.n 80130c0 { if ((pData == NULL) || (Size == 0U)) 801302a: 68bb ldr r3, [r7, #8] 801302c: 2b00 cmp r3, #0 801302e: d002 beq.n 8013036 8013030: 88fb ldrh r3, [r7, #6] 8013032: 2b00 cmp r3, #0 8013034: d101 bne.n 801303a { return HAL_ERROR; 8013036: 2301 movs r3, #1 8013038: e043 b.n 80130c2 } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 801303a: 68fb ldr r3, [r7, #12] 801303c: 2201 movs r2, #1 801303e: 631a str r2, [r3, #48] @ 0x30 huart->RxEventType = HAL_UART_RXEVENT_TC; 8013040: 68fb ldr r3, [r7, #12] 8013042: 2200 movs r2, #0 8013044: 635a str r2, [r3, #52] @ 0x34 status = UART_Start_Receive_IT(huart, pData, Size); 8013046: 88fb ldrh r3, [r7, #6] 8013048: 461a mov r2, r3 801304a: 68b9 ldr r1, [r7, #8] 801304c: 68f8 ldr r0, [r7, #12] 801304e: f000 fdb2 bl 8013bb6 8013052: 4603 mov r3, r0 8013054: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check Rx process has been successfully started */ if (status == HAL_OK) 8013058: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 801305c: 2b00 cmp r3, #0 801305e: d12c bne.n 80130ba { if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013060: 68fb ldr r3, [r7, #12] 8013062: 6b1b ldr r3, [r3, #48] @ 0x30 8013064: 2b01 cmp r3, #1 8013066: d125 bne.n 80130b4 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8013068: 2300 movs r3, #0 801306a: 613b str r3, [r7, #16] 801306c: 68fb ldr r3, [r7, #12] 801306e: 681b ldr r3, [r3, #0] 8013070: 681b ldr r3, [r3, #0] 8013072: 613b str r3, [r7, #16] 8013074: 68fb ldr r3, [r7, #12] 8013076: 681b ldr r3, [r3, #0] 8013078: 685b ldr r3, [r3, #4] 801307a: 613b str r3, [r7, #16] 801307c: 693b ldr r3, [r7, #16] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801307e: 68fb ldr r3, [r7, #12] 8013080: 681b ldr r3, [r3, #0] 8013082: 330c adds r3, #12 8013084: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013086: 69bb ldr r3, [r7, #24] 8013088: e853 3f00 ldrex r3, [r3] 801308c: 617b str r3, [r7, #20] return(result); 801308e: 697b ldr r3, [r7, #20] 8013090: f043 0310 orr.w r3, r3, #16 8013094: 62bb str r3, [r7, #40] @ 0x28 8013096: 68fb ldr r3, [r7, #12] 8013098: 681b ldr r3, [r3, #0] 801309a: 330c adds r3, #12 801309c: 6aba ldr r2, [r7, #40] @ 0x28 801309e: 627a str r2, [r7, #36] @ 0x24 80130a0: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80130a2: 6a39 ldr r1, [r7, #32] 80130a4: 6a7a ldr r2, [r7, #36] @ 0x24 80130a6: e841 2300 strex r3, r2, [r1] 80130aa: 61fb str r3, [r7, #28] return(result); 80130ac: 69fb ldr r3, [r7, #28] 80130ae: 2b00 cmp r3, #0 80130b0: d1e5 bne.n 801307e 80130b2: e002 b.n 80130ba { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 80130b4: 2301 movs r3, #1 80130b6: f887 302f strb.w r3, [r7, #47] @ 0x2f } } return status; 80130ba: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 80130be: e000 b.n 80130c2 } else { return HAL_BUSY; 80130c0: 2302 movs r3, #2 } } 80130c2: 4618 mov r0, r3 80130c4: 3730 adds r7, #48 @ 0x30 80130c6: 46bd mov sp, r7 80130c8: bd80 pop {r7, pc} 080130ca : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80130ca: b580 push {r7, lr} 80130cc: b08c sub sp, #48 @ 0x30 80130ce: af00 add r7, sp, #0 80130d0: 60f8 str r0, [r7, #12] 80130d2: 60b9 str r1, [r7, #8] 80130d4: 4613 mov r3, r2 80130d6: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 80130d8: 68fb ldr r3, [r7, #12] 80130da: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 80130de: b2db uxtb r3, r3 80130e0: 2b20 cmp r3, #32 80130e2: d146 bne.n 8013172 { if ((pData == NULL) || (Size == 0U)) 80130e4: 68bb ldr r3, [r7, #8] 80130e6: 2b00 cmp r3, #0 80130e8: d002 beq.n 80130f0 80130ea: 88fb ldrh r3, [r7, #6] 80130ec: 2b00 cmp r3, #0 80130ee: d101 bne.n 80130f4 { return HAL_ERROR; 80130f0: 2301 movs r3, #1 80130f2: e03f b.n 8013174 } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 80130f4: 68fb ldr r3, [r7, #12] 80130f6: 2201 movs r2, #1 80130f8: 631a str r2, [r3, #48] @ 0x30 huart->RxEventType = HAL_UART_RXEVENT_TC; 80130fa: 68fb ldr r3, [r7, #12] 80130fc: 2200 movs r2, #0 80130fe: 635a str r2, [r3, #52] @ 0x34 status = UART_Start_Receive_DMA(huart, pData, Size); 8013100: 88fb ldrh r3, [r7, #6] 8013102: 461a mov r2, r3 8013104: 68b9 ldr r1, [r7, #8] 8013106: 68f8 ldr r0, [r7, #12] 8013108: f000 fd8e bl 8013c28 801310c: 4603 mov r3, r0 801310e: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check Rx process has been successfully started */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013112: 68fb ldr r3, [r7, #12] 8013114: 6b1b ldr r3, [r3, #48] @ 0x30 8013116: 2b01 cmp r3, #1 8013118: d125 bne.n 8013166 { __HAL_UART_CLEAR_IDLEFLAG(huart); 801311a: 2300 movs r3, #0 801311c: 613b str r3, [r7, #16] 801311e: 68fb ldr r3, [r7, #12] 8013120: 681b ldr r3, [r3, #0] 8013122: 681b ldr r3, [r3, #0] 8013124: 613b str r3, [r7, #16] 8013126: 68fb ldr r3, [r7, #12] 8013128: 681b ldr r3, [r3, #0] 801312a: 685b ldr r3, [r3, #4] 801312c: 613b str r3, [r7, #16] 801312e: 693b ldr r3, [r7, #16] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013130: 68fb ldr r3, [r7, #12] 8013132: 681b ldr r3, [r3, #0] 8013134: 330c adds r3, #12 8013136: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013138: 69bb ldr r3, [r7, #24] 801313a: e853 3f00 ldrex r3, [r3] 801313e: 617b str r3, [r7, #20] return(result); 8013140: 697b ldr r3, [r7, #20] 8013142: f043 0310 orr.w r3, r3, #16 8013146: 62bb str r3, [r7, #40] @ 0x28 8013148: 68fb ldr r3, [r7, #12] 801314a: 681b ldr r3, [r3, #0] 801314c: 330c adds r3, #12 801314e: 6aba ldr r2, [r7, #40] @ 0x28 8013150: 627a str r2, [r7, #36] @ 0x24 8013152: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013154: 6a39 ldr r1, [r7, #32] 8013156: 6a7a ldr r2, [r7, #36] @ 0x24 8013158: e841 2300 strex r3, r2, [r1] 801315c: 61fb str r3, [r7, #28] return(result); 801315e: 69fb ldr r3, [r7, #28] 8013160: 2b00 cmp r3, #0 8013162: d1e5 bne.n 8013130 8013164: e002 b.n 801316c { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8013166: 2301 movs r3, #1 8013168: f887 302f strb.w r3, [r7, #47] @ 0x2f } return status; 801316c: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8013170: e000 b.n 8013174 } else { return HAL_BUSY; 8013172: 2302 movs r3, #2 } } 8013174: 4618 mov r0, r3 8013176: 3730 adds r7, #48 @ 0x30 8013178: 46bd mov sp, r7 801317a: bd80 pop {r7, pc} 0801317c : * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { 801317c: b580 push {r7, lr} 801317e: b08e sub sp, #56 @ 0x38 8013180: af00 add r7, sp, #0 8013182: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 8013184: 687b ldr r3, [r7, #4] 8013186: 681b ldr r3, [r3, #0] 8013188: 330c adds r3, #12 801318a: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801318c: 6a3b ldr r3, [r7, #32] 801318e: e853 3f00 ldrex r3, [r3] 8013192: 61fb str r3, [r7, #28] return(result); 8013194: 69fb ldr r3, [r7, #28] 8013196: f023 03c0 bic.w r3, r3, #192 @ 0xc0 801319a: 637b str r3, [r7, #52] @ 0x34 801319c: 687b ldr r3, [r7, #4] 801319e: 681b ldr r3, [r3, #0] 80131a0: 330c adds r3, #12 80131a2: 6b7a ldr r2, [r7, #52] @ 0x34 80131a4: 62fa str r2, [r7, #44] @ 0x2c 80131a6: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80131a8: 6ab9 ldr r1, [r7, #40] @ 0x28 80131aa: 6afa ldr r2, [r7, #44] @ 0x2c 80131ac: e841 2300 strex r3, r2, [r1] 80131b0: 627b str r3, [r7, #36] @ 0x24 return(result); 80131b2: 6a7b ldr r3, [r7, #36] @ 0x24 80131b4: 2b00 cmp r3, #0 80131b6: d1e5 bne.n 8013184 /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) 80131b8: 687b ldr r3, [r7, #4] 80131ba: 681b ldr r3, [r3, #0] 80131bc: 695b ldr r3, [r3, #20] 80131be: f003 0380 and.w r3, r3, #128 @ 0x80 80131c2: 2b00 cmp r3, #0 80131c4: d036 beq.n 8013234 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 80131c6: 687b ldr r3, [r7, #4] 80131c8: 681b ldr r3, [r3, #0] 80131ca: 3314 adds r3, #20 80131cc: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80131ce: 68fb ldr r3, [r7, #12] 80131d0: e853 3f00 ldrex r3, [r3] 80131d4: 60bb str r3, [r7, #8] return(result); 80131d6: 68bb ldr r3, [r7, #8] 80131d8: f023 0380 bic.w r3, r3, #128 @ 0x80 80131dc: 633b str r3, [r7, #48] @ 0x30 80131de: 687b ldr r3, [r7, #4] 80131e0: 681b ldr r3, [r3, #0] 80131e2: 3314 adds r3, #20 80131e4: 6b3a ldr r2, [r7, #48] @ 0x30 80131e6: 61ba str r2, [r7, #24] 80131e8: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80131ea: 6979 ldr r1, [r7, #20] 80131ec: 69ba ldr r2, [r7, #24] 80131ee: e841 2300 strex r3, r2, [r1] 80131f2: 613b str r3, [r7, #16] return(result); 80131f4: 693b ldr r3, [r7, #16] 80131f6: 2b00 cmp r3, #0 80131f8: d1e5 bne.n 80131c6 /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) 80131fa: 687b ldr r3, [r7, #4] 80131fc: 6b9b ldr r3, [r3, #56] @ 0x38 80131fe: 2b00 cmp r3, #0 8013200: d018 beq.n 8013234 { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = NULL; 8013202: 687b ldr r3, [r7, #4] 8013204: 6b9b ldr r3, [r3, #56] @ 0x38 8013206: 2200 movs r2, #0 8013208: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) 801320a: 687b ldr r3, [r7, #4] 801320c: 6b9b ldr r3, [r3, #56] @ 0x38 801320e: 4618 mov r0, r3 8013210: f7fc fed6 bl 800ffc0 8013214: 4603 mov r3, r0 8013216: 2b00 cmp r3, #0 8013218: d00c beq.n 8013234 { if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) 801321a: 687b ldr r3, [r7, #4] 801321c: 6b9b ldr r3, [r3, #56] @ 0x38 801321e: 4618 mov r0, r3 8013220: f7fd fa4e bl 80106c0 8013224: 4603 mov r3, r0 8013226: 2b20 cmp r3, #32 8013228: d104 bne.n 8013234 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 801322a: 687b ldr r3, [r7, #4] 801322c: 2210 movs r2, #16 801322e: 645a str r2, [r3, #68] @ 0x44 return HAL_TIMEOUT; 8013230: 2303 movs r3, #3 8013232: e007 b.n 8013244 } } } /* Reset Tx transfer counter */ huart->TxXferCount = 0x00U; 8013234: 687b ldr r3, [r7, #4] 8013236: 2200 movs r2, #0 8013238: 84da strh r2, [r3, #38] @ 0x26 /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 801323a: 687b ldr r3, [r7, #4] 801323c: 2220 movs r2, #32 801323e: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_OK; 8013242: 2300 movs r3, #0 } 8013244: 4618 mov r0, r3 8013246: 3738 adds r7, #56 @ 0x38 8013248: 46bd mov sp, r7 801324a: bd80 pop {r7, pc} 0801324c : * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { 801324c: b580 push {r7, lr} 801324e: b09a sub sp, #104 @ 0x68 8013250: af00 add r7, sp, #0 8013252: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8013254: 687b ldr r3, [r7, #4] 8013256: 681b ldr r3, [r3, #0] 8013258: 330c adds r3, #12 801325a: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801325c: 6cbb ldr r3, [r7, #72] @ 0x48 801325e: e853 3f00 ldrex r3, [r3] 8013262: 647b str r3, [r7, #68] @ 0x44 return(result); 8013264: 6c7b ldr r3, [r7, #68] @ 0x44 8013266: f423 7390 bic.w r3, r3, #288 @ 0x120 801326a: 667b str r3, [r7, #100] @ 0x64 801326c: 687b ldr r3, [r7, #4] 801326e: 681b ldr r3, [r3, #0] 8013270: 330c adds r3, #12 8013272: 6e7a ldr r2, [r7, #100] @ 0x64 8013274: 657a str r2, [r7, #84] @ 0x54 8013276: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013278: 6d39 ldr r1, [r7, #80] @ 0x50 801327a: 6d7a ldr r2, [r7, #84] @ 0x54 801327c: e841 2300 strex r3, r2, [r1] 8013280: 64fb str r3, [r7, #76] @ 0x4c return(result); 8013282: 6cfb ldr r3, [r7, #76] @ 0x4c 8013284: 2b00 cmp r3, #0 8013286: d1e5 bne.n 8013254 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013288: 687b ldr r3, [r7, #4] 801328a: 681b ldr r3, [r3, #0] 801328c: 3314 adds r3, #20 801328e: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013290: 6b7b ldr r3, [r7, #52] @ 0x34 8013292: e853 3f00 ldrex r3, [r3] 8013296: 633b str r3, [r7, #48] @ 0x30 return(result); 8013298: 6b3b ldr r3, [r7, #48] @ 0x30 801329a: f023 0301 bic.w r3, r3, #1 801329e: 663b str r3, [r7, #96] @ 0x60 80132a0: 687b ldr r3, [r7, #4] 80132a2: 681b ldr r3, [r3, #0] 80132a4: 3314 adds r3, #20 80132a6: 6e3a ldr r2, [r7, #96] @ 0x60 80132a8: 643a str r2, [r7, #64] @ 0x40 80132aa: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80132ac: 6bf9 ldr r1, [r7, #60] @ 0x3c 80132ae: 6c3a ldr r2, [r7, #64] @ 0x40 80132b0: e841 2300 strex r3, r2, [r1] 80132b4: 63bb str r3, [r7, #56] @ 0x38 return(result); 80132b6: 6bbb ldr r3, [r7, #56] @ 0x38 80132b8: 2b00 cmp r3, #0 80132ba: d1e5 bne.n 8013288 /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80132bc: 687b ldr r3, [r7, #4] 80132be: 6b1b ldr r3, [r3, #48] @ 0x30 80132c0: 2b01 cmp r3, #1 80132c2: d119 bne.n 80132f8 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); 80132c4: 687b ldr r3, [r7, #4] 80132c6: 681b ldr r3, [r3, #0] 80132c8: 330c adds r3, #12 80132ca: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80132cc: 6a3b ldr r3, [r7, #32] 80132ce: e853 3f00 ldrex r3, [r3] 80132d2: 61fb str r3, [r7, #28] return(result); 80132d4: 69fb ldr r3, [r7, #28] 80132d6: f023 0310 bic.w r3, r3, #16 80132da: 65fb str r3, [r7, #92] @ 0x5c 80132dc: 687b ldr r3, [r7, #4] 80132de: 681b ldr r3, [r3, #0] 80132e0: 330c adds r3, #12 80132e2: 6dfa ldr r2, [r7, #92] @ 0x5c 80132e4: 62fa str r2, [r7, #44] @ 0x2c 80132e6: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80132e8: 6ab9 ldr r1, [r7, #40] @ 0x28 80132ea: 6afa ldr r2, [r7, #44] @ 0x2c 80132ec: e841 2300 strex r3, r2, [r1] 80132f0: 627b str r3, [r7, #36] @ 0x24 return(result); 80132f2: 6a7b ldr r3, [r7, #36] @ 0x24 80132f4: 2b00 cmp r3, #0 80132f6: d1e5 bne.n 80132c4 } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80132f8: 687b ldr r3, [r7, #4] 80132fa: 681b ldr r3, [r3, #0] 80132fc: 695b ldr r3, [r3, #20] 80132fe: f003 0340 and.w r3, r3, #64 @ 0x40 8013302: 2b00 cmp r3, #0 8013304: d036 beq.n 8013374 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8013306: 687b ldr r3, [r7, #4] 8013308: 681b ldr r3, [r3, #0] 801330a: 3314 adds r3, #20 801330c: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801330e: 68fb ldr r3, [r7, #12] 8013310: e853 3f00 ldrex r3, [r3] 8013314: 60bb str r3, [r7, #8] return(result); 8013316: 68bb ldr r3, [r7, #8] 8013318: f023 0340 bic.w r3, r3, #64 @ 0x40 801331c: 65bb str r3, [r7, #88] @ 0x58 801331e: 687b ldr r3, [r7, #4] 8013320: 681b ldr r3, [r3, #0] 8013322: 3314 adds r3, #20 8013324: 6dba ldr r2, [r7, #88] @ 0x58 8013326: 61ba str r2, [r7, #24] 8013328: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801332a: 6979 ldr r1, [r7, #20] 801332c: 69ba ldr r2, [r7, #24] 801332e: e841 2300 strex r3, r2, [r1] 8013332: 613b str r3, [r7, #16] return(result); 8013334: 693b ldr r3, [r7, #16] 8013336: 2b00 cmp r3, #0 8013338: d1e5 bne.n 8013306 /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) 801333a: 687b ldr r3, [r7, #4] 801333c: 6bdb ldr r3, [r3, #60] @ 0x3c 801333e: 2b00 cmp r3, #0 8013340: d018 beq.n 8013374 { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = NULL; 8013342: 687b ldr r3, [r7, #4] 8013344: 6bdb ldr r3, [r3, #60] @ 0x3c 8013346: 2200 movs r2, #0 8013348: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) 801334a: 687b ldr r3, [r7, #4] 801334c: 6bdb ldr r3, [r3, #60] @ 0x3c 801334e: 4618 mov r0, r3 8013350: f7fc fe36 bl 800ffc0 8013354: 4603 mov r3, r0 8013356: 2b00 cmp r3, #0 8013358: d00c beq.n 8013374 { if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) 801335a: 687b ldr r3, [r7, #4] 801335c: 6bdb ldr r3, [r3, #60] @ 0x3c 801335e: 4618 mov r0, r3 8013360: f7fd f9ae bl 80106c0 8013364: 4603 mov r3, r0 8013366: 2b20 cmp r3, #32 8013368: d104 bne.n 8013374 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 801336a: 687b ldr r3, [r7, #4] 801336c: 2210 movs r2, #16 801336e: 645a str r2, [r3, #68] @ 0x44 return HAL_TIMEOUT; 8013370: 2303 movs r3, #3 8013372: e00a b.n 801338a } } } /* Reset Rx transfer counter */ huart->RxXferCount = 0x00U; 8013374: 687b ldr r3, [r7, #4] 8013376: 2200 movs r2, #0 8013378: 85da strh r2, [r3, #46] @ 0x2e /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 801337a: 687b ldr r3, [r7, #4] 801337c: 2220 movs r2, #32 801337e: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013382: 687b ldr r3, [r7, #4] 8013384: 2200 movs r2, #0 8013386: 631a str r2, [r3, #48] @ 0x30 return HAL_OK; 8013388: 2300 movs r3, #0 } 801338a: 4618 mov r0, r3 801338c: 3768 adds r7, #104 @ 0x68 801338e: 46bd mov sp, r7 8013390: bd80 pop {r7, pc} ... 08013394 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8013394: b580 push {r7, lr} 8013396: b0ba sub sp, #232 @ 0xe8 8013398: af00 add r7, sp, #0 801339a: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 801339c: 687b ldr r3, [r7, #4] 801339e: 681b ldr r3, [r3, #0] 80133a0: 681b ldr r3, [r3, #0] 80133a2: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 80133a6: 687b ldr r3, [r7, #4] 80133a8: 681b ldr r3, [r3, #0] 80133aa: 68db ldr r3, [r3, #12] 80133ac: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 80133b0: 687b ldr r3, [r7, #4] 80133b2: 681b ldr r3, [r3, #0] 80133b4: 695b ldr r3, [r3, #20] 80133b6: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 80133ba: 2300 movs r3, #0 80133bc: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 80133c0: 2300 movs r3, #0 80133c2: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 80133c6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80133ca: f003 030f and.w r3, r3, #15 80133ce: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 80133d2: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80133d6: 2b00 cmp r3, #0 80133d8: d10f bne.n 80133fa { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 80133da: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80133de: f003 0320 and.w r3, r3, #32 80133e2: 2b00 cmp r3, #0 80133e4: d009 beq.n 80133fa 80133e6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80133ea: f003 0320 and.w r3, r3, #32 80133ee: 2b00 cmp r3, #0 80133f0: d003 beq.n 80133fa { UART_Receive_IT(huart); 80133f2: 6878 ldr r0, [r7, #4] 80133f4: f000 fdb6 bl 8013f64 return; 80133f8: e25b b.n 80138b2 } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 80133fa: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80133fe: 2b00 cmp r3, #0 8013400: f000 80de beq.w 80135c0 8013404: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8013408: f003 0301 and.w r3, r3, #1 801340c: 2b00 cmp r3, #0 801340e: d106 bne.n 801341e || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8013410: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013414: f403 7390 and.w r3, r3, #288 @ 0x120 8013418: 2b00 cmp r3, #0 801341a: f000 80d1 beq.w 80135c0 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 801341e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013422: f003 0301 and.w r3, r3, #1 8013426: 2b00 cmp r3, #0 8013428: d00b beq.n 8013442 801342a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801342e: f403 7380 and.w r3, r3, #256 @ 0x100 8013432: 2b00 cmp r3, #0 8013434: d005 beq.n 8013442 { huart->ErrorCode |= HAL_UART_ERROR_PE; 8013436: 687b ldr r3, [r7, #4] 8013438: 6c5b ldr r3, [r3, #68] @ 0x44 801343a: f043 0201 orr.w r2, r3, #1 801343e: 687b ldr r3, [r7, #4] 8013440: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8013442: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013446: f003 0304 and.w r3, r3, #4 801344a: 2b00 cmp r3, #0 801344c: d00b beq.n 8013466 801344e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8013452: f003 0301 and.w r3, r3, #1 8013456: 2b00 cmp r3, #0 8013458: d005 beq.n 8013466 { huart->ErrorCode |= HAL_UART_ERROR_NE; 801345a: 687b ldr r3, [r7, #4] 801345c: 6c5b ldr r3, [r3, #68] @ 0x44 801345e: f043 0202 orr.w r2, r3, #2 8013462: 687b ldr r3, [r7, #4] 8013464: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8013466: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801346a: f003 0302 and.w r3, r3, #2 801346e: 2b00 cmp r3, #0 8013470: d00b beq.n 801348a 8013472: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8013476: f003 0301 and.w r3, r3, #1 801347a: 2b00 cmp r3, #0 801347c: d005 beq.n 801348a { huart->ErrorCode |= HAL_UART_ERROR_FE; 801347e: 687b ldr r3, [r7, #4] 8013480: 6c5b ldr r3, [r3, #68] @ 0x44 8013482: f043 0204 orr.w r2, r3, #4 8013486: 687b ldr r3, [r7, #4] 8013488: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 801348a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801348e: f003 0308 and.w r3, r3, #8 8013492: 2b00 cmp r3, #0 8013494: d011 beq.n 80134ba 8013496: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801349a: f003 0320 and.w r3, r3, #32 801349e: 2b00 cmp r3, #0 80134a0: d105 bne.n 80134ae || ((cr3its & USART_CR3_EIE) != RESET))) 80134a2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80134a6: f003 0301 and.w r3, r3, #1 80134aa: 2b00 cmp r3, #0 80134ac: d005 beq.n 80134ba { huart->ErrorCode |= HAL_UART_ERROR_ORE; 80134ae: 687b ldr r3, [r7, #4] 80134b0: 6c5b ldr r3, [r3, #68] @ 0x44 80134b2: f043 0208 orr.w r2, r3, #8 80134b6: 687b ldr r3, [r7, #4] 80134b8: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 80134ba: 687b ldr r3, [r7, #4] 80134bc: 6c5b ldr r3, [r3, #68] @ 0x44 80134be: 2b00 cmp r3, #0 80134c0: f000 81f2 beq.w 80138a8 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 80134c4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80134c8: f003 0320 and.w r3, r3, #32 80134cc: 2b00 cmp r3, #0 80134ce: d008 beq.n 80134e2 80134d0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80134d4: f003 0320 and.w r3, r3, #32 80134d8: 2b00 cmp r3, #0 80134da: d002 beq.n 80134e2 { UART_Receive_IT(huart); 80134dc: 6878 ldr r0, [r7, #4] 80134de: f000 fd41 bl 8013f64 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 80134e2: 687b ldr r3, [r7, #4] 80134e4: 681b ldr r3, [r3, #0] 80134e6: 695b ldr r3, [r3, #20] 80134e8: f003 0340 and.w r3, r3, #64 @ 0x40 80134ec: 2b00 cmp r3, #0 80134ee: bf14 ite ne 80134f0: 2301 movne r3, #1 80134f2: 2300 moveq r3, #0 80134f4: b2db uxtb r3, r3 80134f6: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 80134fa: 687b ldr r3, [r7, #4] 80134fc: 6c5b ldr r3, [r3, #68] @ 0x44 80134fe: f003 0308 and.w r3, r3, #8 8013502: 2b00 cmp r3, #0 8013504: d103 bne.n 801350e 8013506: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 801350a: 2b00 cmp r3, #0 801350c: d04f beq.n 80135ae { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 801350e: 6878 ldr r0, [r7, #4] 8013510: f000 fc4b bl 8013daa /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013514: 687b ldr r3, [r7, #4] 8013516: 681b ldr r3, [r3, #0] 8013518: 695b ldr r3, [r3, #20] 801351a: f003 0340 and.w r3, r3, #64 @ 0x40 801351e: 2b00 cmp r3, #0 8013520: d041 beq.n 80135a6 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8013522: 687b ldr r3, [r7, #4] 8013524: 681b ldr r3, [r3, #0] 8013526: 3314 adds r3, #20 8013528: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801352c: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8013530: e853 3f00 ldrex r3, [r3] 8013534: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8013538: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 801353c: f023 0340 bic.w r3, r3, #64 @ 0x40 8013540: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8013544: 687b ldr r3, [r7, #4] 8013546: 681b ldr r3, [r3, #0] 8013548: 3314 adds r3, #20 801354a: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 801354e: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8013552: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013556: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 801355a: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 801355e: e841 2300 strex r3, r2, [r1] 8013562: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8013566: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 801356a: 2b00 cmp r3, #0 801356c: d1d9 bne.n 8013522 /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 801356e: 687b ldr r3, [r7, #4] 8013570: 6bdb ldr r3, [r3, #60] @ 0x3c 8013572: 2b00 cmp r3, #0 8013574: d013 beq.n 801359e { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8013576: 687b ldr r3, [r7, #4] 8013578: 6bdb ldr r3, [r3, #60] @ 0x3c 801357a: 4a7e ldr r2, [pc, #504] @ (8013774 ) 801357c: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 801357e: 687b ldr r3, [r7, #4] 8013580: 6bdb ldr r3, [r3, #60] @ 0x3c 8013582: 4618 mov r0, r3 8013584: f7fc fd58 bl 8010038 8013588: 4603 mov r3, r0 801358a: 2b00 cmp r3, #0 801358c: d016 beq.n 80135bc { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 801358e: 687b ldr r3, [r7, #4] 8013590: 6bdb ldr r3, [r3, #60] @ 0x3c 8013592: 6b5b ldr r3, [r3, #52] @ 0x34 8013594: 687a ldr r2, [r7, #4] 8013596: 6bd2 ldr r2, [r2, #60] @ 0x3c 8013598: 4610 mov r0, r2 801359a: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801359c: e00e b.n 80135bc #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 801359e: 6878 ldr r0, [r7, #4] 80135a0: f7f8 fb92 bl 800bcc8 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80135a4: e00a b.n 80135bc #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80135a6: 6878 ldr r0, [r7, #4] 80135a8: f7f8 fb8e bl 800bcc8 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80135ac: e006 b.n 80135bc #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80135ae: 6878 ldr r0, [r7, #4] 80135b0: f7f8 fb8a bl 800bcc8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80135b4: 687b ldr r3, [r7, #4] 80135b6: 2200 movs r2, #0 80135b8: 645a str r2, [r3, #68] @ 0x44 } } return; 80135ba: e175 b.n 80138a8 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80135bc: bf00 nop return; 80135be: e173 b.n 80138a8 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80135c0: 687b ldr r3, [r7, #4] 80135c2: 6b1b ldr r3, [r3, #48] @ 0x30 80135c4: 2b01 cmp r3, #1 80135c6: f040 814f bne.w 8013868 && ((isrflags & USART_SR_IDLE) != 0U) 80135ca: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80135ce: f003 0310 and.w r3, r3, #16 80135d2: 2b00 cmp r3, #0 80135d4: f000 8148 beq.w 8013868 && ((cr1its & USART_SR_IDLE) != 0U)) 80135d8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80135dc: f003 0310 and.w r3, r3, #16 80135e0: 2b00 cmp r3, #0 80135e2: f000 8141 beq.w 8013868 { __HAL_UART_CLEAR_IDLEFLAG(huart); 80135e6: 2300 movs r3, #0 80135e8: 60bb str r3, [r7, #8] 80135ea: 687b ldr r3, [r7, #4] 80135ec: 681b ldr r3, [r3, #0] 80135ee: 681b ldr r3, [r3, #0] 80135f0: 60bb str r3, [r7, #8] 80135f2: 687b ldr r3, [r7, #4] 80135f4: 681b ldr r3, [r3, #0] 80135f6: 685b ldr r3, [r3, #4] 80135f8: 60bb str r3, [r7, #8] 80135fa: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80135fc: 687b ldr r3, [r7, #4] 80135fe: 681b ldr r3, [r3, #0] 8013600: 695b ldr r3, [r3, #20] 8013602: f003 0340 and.w r3, r3, #64 @ 0x40 8013606: 2b00 cmp r3, #0 8013608: f000 80b6 beq.w 8013778 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 801360c: 687b ldr r3, [r7, #4] 801360e: 6bdb ldr r3, [r3, #60] @ 0x3c 8013610: 681b ldr r3, [r3, #0] 8013612: 685b ldr r3, [r3, #4] 8013614: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8013618: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 801361c: 2b00 cmp r3, #0 801361e: f000 8145 beq.w 80138ac && (nb_remaining_rx_data < huart->RxXferSize)) 8013622: 687b ldr r3, [r7, #4] 8013624: 8d9b ldrh r3, [r3, #44] @ 0x2c 8013626: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 801362a: 429a cmp r2, r3 801362c: f080 813e bcs.w 80138ac { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8013630: 687b ldr r3, [r7, #4] 8013632: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8013636: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8013638: 687b ldr r3, [r7, #4] 801363a: 6bdb ldr r3, [r3, #60] @ 0x3c 801363c: 699b ldr r3, [r3, #24] 801363e: 2b20 cmp r3, #32 8013640: f000 8088 beq.w 8013754 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8013644: 687b ldr r3, [r7, #4] 8013646: 681b ldr r3, [r3, #0] 8013648: 330c adds r3, #12 801364a: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801364e: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8013652: e853 3f00 ldrex r3, [r3] 8013656: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 801365a: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 801365e: f423 7380 bic.w r3, r3, #256 @ 0x100 8013662: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8013666: 687b ldr r3, [r7, #4] 8013668: 681b ldr r3, [r3, #0] 801366a: 330c adds r3, #12 801366c: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 8013670: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8013674: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013678: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 801367c: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8013680: e841 2300 strex r3, r2, [r1] 8013684: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8013688: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 801368c: 2b00 cmp r3, #0 801368e: d1d9 bne.n 8013644 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013690: 687b ldr r3, [r7, #4] 8013692: 681b ldr r3, [r3, #0] 8013694: 3314 adds r3, #20 8013696: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013698: 6f7b ldr r3, [r7, #116] @ 0x74 801369a: e853 3f00 ldrex r3, [r3] 801369e: 673b str r3, [r7, #112] @ 0x70 return(result); 80136a0: 6f3b ldr r3, [r7, #112] @ 0x70 80136a2: f023 0301 bic.w r3, r3, #1 80136a6: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 80136aa: 687b ldr r3, [r7, #4] 80136ac: 681b ldr r3, [r3, #0] 80136ae: 3314 adds r3, #20 80136b0: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 80136b4: f8c7 2080 str.w r2, [r7, #128] @ 0x80 80136b8: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80136ba: 6ff9 ldr r1, [r7, #124] @ 0x7c 80136bc: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 80136c0: e841 2300 strex r3, r2, [r1] 80136c4: 67bb str r3, [r7, #120] @ 0x78 return(result); 80136c6: 6fbb ldr r3, [r7, #120] @ 0x78 80136c8: 2b00 cmp r3, #0 80136ca: d1e1 bne.n 8013690 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80136cc: 687b ldr r3, [r7, #4] 80136ce: 681b ldr r3, [r3, #0] 80136d0: 3314 adds r3, #20 80136d2: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80136d4: 6e3b ldr r3, [r7, #96] @ 0x60 80136d6: e853 3f00 ldrex r3, [r3] 80136da: 65fb str r3, [r7, #92] @ 0x5c return(result); 80136dc: 6dfb ldr r3, [r7, #92] @ 0x5c 80136de: f023 0340 bic.w r3, r3, #64 @ 0x40 80136e2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 80136e6: 687b ldr r3, [r7, #4] 80136e8: 681b ldr r3, [r3, #0] 80136ea: 3314 adds r3, #20 80136ec: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 80136f0: 66fa str r2, [r7, #108] @ 0x6c 80136f2: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80136f4: 6eb9 ldr r1, [r7, #104] @ 0x68 80136f6: 6efa ldr r2, [r7, #108] @ 0x6c 80136f8: e841 2300 strex r3, r2, [r1] 80136fc: 667b str r3, [r7, #100] @ 0x64 return(result); 80136fe: 6e7b ldr r3, [r7, #100] @ 0x64 8013700: 2b00 cmp r3, #0 8013702: d1e3 bne.n 80136cc /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013704: 687b ldr r3, [r7, #4] 8013706: 2220 movs r2, #32 8013708: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801370c: 687b ldr r3, [r7, #4] 801370e: 2200 movs r2, #0 8013710: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013712: 687b ldr r3, [r7, #4] 8013714: 681b ldr r3, [r3, #0] 8013716: 330c adds r3, #12 8013718: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801371a: 6cfb ldr r3, [r7, #76] @ 0x4c 801371c: e853 3f00 ldrex r3, [r3] 8013720: 64bb str r3, [r7, #72] @ 0x48 return(result); 8013722: 6cbb ldr r3, [r7, #72] @ 0x48 8013724: f023 0310 bic.w r3, r3, #16 8013728: f8c7 30ac str.w r3, [r7, #172] @ 0xac 801372c: 687b ldr r3, [r7, #4] 801372e: 681b ldr r3, [r3, #0] 8013730: 330c adds r3, #12 8013732: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 8013736: 65ba str r2, [r7, #88] @ 0x58 8013738: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801373a: 6d79 ldr r1, [r7, #84] @ 0x54 801373c: 6dba ldr r2, [r7, #88] @ 0x58 801373e: e841 2300 strex r3, r2, [r1] 8013742: 653b str r3, [r7, #80] @ 0x50 return(result); 8013744: 6d3b ldr r3, [r7, #80] @ 0x50 8013746: 2b00 cmp r3, #0 8013748: d1e3 bne.n 8013712 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 801374a: 687b ldr r3, [r7, #4] 801374c: 6bdb ldr r3, [r3, #60] @ 0x3c 801374e: 4618 mov r0, r3 8013750: f7fc fc36 bl 800ffc0 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8013754: 687b ldr r3, [r7, #4] 8013756: 2202 movs r2, #2 8013758: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 801375a: 687b ldr r3, [r7, #4] 801375c: 8d9a ldrh r2, [r3, #44] @ 0x2c 801375e: 687b ldr r3, [r7, #4] 8013760: 8ddb ldrh r3, [r3, #46] @ 0x2e 8013762: b29b uxth r3, r3 8013764: 1ad3 subs r3, r2, r3 8013766: b29b uxth r3, r3 8013768: 4619 mov r1, r3 801376a: 6878 ldr r0, [r7, #4] 801376c: f7f9 f9f6 bl 800cb5c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8013770: e09c b.n 80138ac 8013772: bf00 nop 8013774: 08013e6f .word 0x08013e6f else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8013778: 687b ldr r3, [r7, #4] 801377a: 8d9a ldrh r2, [r3, #44] @ 0x2c 801377c: 687b ldr r3, [r7, #4] 801377e: 8ddb ldrh r3, [r3, #46] @ 0x2e 8013780: b29b uxth r3, r3 8013782: 1ad3 subs r3, r2, r3 8013784: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8013788: 687b ldr r3, [r7, #4] 801378a: 8ddb ldrh r3, [r3, #46] @ 0x2e 801378c: b29b uxth r3, r3 801378e: 2b00 cmp r3, #0 8013790: f000 808e beq.w 80138b0 && (nb_rx_data > 0U)) 8013794: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8013798: 2b00 cmp r3, #0 801379a: f000 8089 beq.w 80138b0 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 801379e: 687b ldr r3, [r7, #4] 80137a0: 681b ldr r3, [r3, #0] 80137a2: 330c adds r3, #12 80137a4: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80137a6: 6bbb ldr r3, [r7, #56] @ 0x38 80137a8: e853 3f00 ldrex r3, [r3] 80137ac: 637b str r3, [r7, #52] @ 0x34 return(result); 80137ae: 6b7b ldr r3, [r7, #52] @ 0x34 80137b0: f423 7390 bic.w r3, r3, #288 @ 0x120 80137b4: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 80137b8: 687b ldr r3, [r7, #4] 80137ba: 681b ldr r3, [r3, #0] 80137bc: 330c adds r3, #12 80137be: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 80137c2: 647a str r2, [r7, #68] @ 0x44 80137c4: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80137c6: 6c39 ldr r1, [r7, #64] @ 0x40 80137c8: 6c7a ldr r2, [r7, #68] @ 0x44 80137ca: e841 2300 strex r3, r2, [r1] 80137ce: 63fb str r3, [r7, #60] @ 0x3c return(result); 80137d0: 6bfb ldr r3, [r7, #60] @ 0x3c 80137d2: 2b00 cmp r3, #0 80137d4: d1e3 bne.n 801379e /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80137d6: 687b ldr r3, [r7, #4] 80137d8: 681b ldr r3, [r3, #0] 80137da: 3314 adds r3, #20 80137dc: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80137de: 6a7b ldr r3, [r7, #36] @ 0x24 80137e0: e853 3f00 ldrex r3, [r3] 80137e4: 623b str r3, [r7, #32] return(result); 80137e6: 6a3b ldr r3, [r7, #32] 80137e8: f023 0301 bic.w r3, r3, #1 80137ec: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 80137f0: 687b ldr r3, [r7, #4] 80137f2: 681b ldr r3, [r3, #0] 80137f4: 3314 adds r3, #20 80137f6: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 80137fa: 633a str r2, [r7, #48] @ 0x30 80137fc: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80137fe: 6af9 ldr r1, [r7, #44] @ 0x2c 8013800: 6b3a ldr r2, [r7, #48] @ 0x30 8013802: e841 2300 strex r3, r2, [r1] 8013806: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013808: 6abb ldr r3, [r7, #40] @ 0x28 801380a: 2b00 cmp r3, #0 801380c: d1e3 bne.n 80137d6 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 801380e: 687b ldr r3, [r7, #4] 8013810: 2220 movs r2, #32 8013812: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013816: 687b ldr r3, [r7, #4] 8013818: 2200 movs r2, #0 801381a: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801381c: 687b ldr r3, [r7, #4] 801381e: 681b ldr r3, [r3, #0] 8013820: 330c adds r3, #12 8013822: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013824: 693b ldr r3, [r7, #16] 8013826: e853 3f00 ldrex r3, [r3] 801382a: 60fb str r3, [r7, #12] return(result); 801382c: 68fb ldr r3, [r7, #12] 801382e: f023 0310 bic.w r3, r3, #16 8013832: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8013836: 687b ldr r3, [r7, #4] 8013838: 681b ldr r3, [r3, #0] 801383a: 330c adds r3, #12 801383c: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 8013840: 61fa str r2, [r7, #28] 8013842: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013844: 69b9 ldr r1, [r7, #24] 8013846: 69fa ldr r2, [r7, #28] 8013848: e841 2300 strex r3, r2, [r1] 801384c: 617b str r3, [r7, #20] return(result); 801384e: 697b ldr r3, [r7, #20] 8013850: 2b00 cmp r3, #0 8013852: d1e3 bne.n 801381c /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8013854: 687b ldr r3, [r7, #4] 8013856: 2202 movs r2, #2 8013858: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 801385a: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 801385e: 4619 mov r1, r3 8013860: 6878 ldr r0, [r7, #4] 8013862: f7f9 f97b bl 800cb5c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8013866: e023 b.n 80138b0 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8013868: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801386c: f003 0380 and.w r3, r3, #128 @ 0x80 8013870: 2b00 cmp r3, #0 8013872: d009 beq.n 8013888 8013874: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013878: f003 0380 and.w r3, r3, #128 @ 0x80 801387c: 2b00 cmp r3, #0 801387e: d003 beq.n 8013888 { UART_Transmit_IT(huart); 8013880: 6878 ldr r0, [r7, #4] 8013882: f000 fb08 bl 8013e96 return; 8013886: e014 b.n 80138b2 } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8013888: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801388c: f003 0340 and.w r3, r3, #64 @ 0x40 8013890: 2b00 cmp r3, #0 8013892: d00e beq.n 80138b2 8013894: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013898: f003 0340 and.w r3, r3, #64 @ 0x40 801389c: 2b00 cmp r3, #0 801389e: d008 beq.n 80138b2 { UART_EndTransmit_IT(huart); 80138a0: 6878 ldr r0, [r7, #4] 80138a2: f000 fb47 bl 8013f34 return; 80138a6: e004 b.n 80138b2 return; 80138a8: bf00 nop 80138aa: e002 b.n 80138b2 return; 80138ac: bf00 nop 80138ae: e000 b.n 80138b2 return; 80138b0: bf00 nop } } 80138b2: 37e8 adds r7, #232 @ 0xe8 80138b4: 46bd mov sp, r7 80138b6: bd80 pop {r7, pc} 080138b8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 80138b8: b480 push {r7} 80138ba: b083 sub sp, #12 80138bc: af00 add r7, sp, #0 80138be: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } 80138c0: bf00 nop 80138c2: 370c adds r7, #12 80138c4: 46bd mov sp, r7 80138c6: bc80 pop {r7} 80138c8: 4770 bx lr 080138ca : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 80138ca: b480 push {r7} 80138cc: b083 sub sp, #12 80138ce: af00 add r7, sp, #0 80138d0: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback could be implemented in the user file */ } 80138d2: bf00 nop 80138d4: 370c adds r7, #12 80138d6: 46bd mov sp, r7 80138d8: bc80 pop {r7} 80138da: 4770 bx lr 080138dc : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { 80138dc: b480 push {r7} 80138de: b083 sub sp, #12 80138e0: af00 add r7, sp, #0 80138e2: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback could be implemented in the user file */ } 80138e4: bf00 nop 80138e6: 370c adds r7, #12 80138e8: 46bd mov sp, r7 80138ea: bc80 pop {r7} 80138ec: 4770 bx lr 080138ee : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. * @retval UART Error Code */ uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) { 80138ee: b480 push {r7} 80138f0: b083 sub sp, #12 80138f2: af00 add r7, sp, #0 80138f4: 6078 str r0, [r7, #4] return huart->ErrorCode; 80138f6: 687b ldr r3, [r7, #4] 80138f8: 6c5b ldr r3, [r3, #68] @ 0x44 } 80138fa: 4618 mov r0, r3 80138fc: 370c adds r7, #12 80138fe: 46bd mov sp, r7 8013900: bc80 pop {r7} 8013902: 4770 bx lr 08013904 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 8013904: b580 push {r7, lr} 8013906: b090 sub sp, #64 @ 0x40 8013908: af00 add r7, sp, #0 801390a: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 801390c: 687b ldr r3, [r7, #4] 801390e: 6a5b ldr r3, [r3, #36] @ 0x24 8013910: 63fb str r3, [r7, #60] @ 0x3c /* DMA Normal mode*/ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8013912: 687b ldr r3, [r7, #4] 8013914: 681b ldr r3, [r3, #0] 8013916: 681b ldr r3, [r3, #0] 8013918: f003 0320 and.w r3, r3, #32 801391c: 2b00 cmp r3, #0 801391e: d137 bne.n 8013990 { huart->TxXferCount = 0x00U; 8013920: 6bfb ldr r3, [r7, #60] @ 0x3c 8013922: 2200 movs r2, #0 8013924: 84da strh r2, [r3, #38] @ 0x26 /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8013926: 6bfb ldr r3, [r7, #60] @ 0x3c 8013928: 681b ldr r3, [r3, #0] 801392a: 3314 adds r3, #20 801392c: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801392e: 6a7b ldr r3, [r7, #36] @ 0x24 8013930: e853 3f00 ldrex r3, [r3] 8013934: 623b str r3, [r7, #32] return(result); 8013936: 6a3b ldr r3, [r7, #32] 8013938: f023 0380 bic.w r3, r3, #128 @ 0x80 801393c: 63bb str r3, [r7, #56] @ 0x38 801393e: 6bfb ldr r3, [r7, #60] @ 0x3c 8013940: 681b ldr r3, [r3, #0] 8013942: 3314 adds r3, #20 8013944: 6bba ldr r2, [r7, #56] @ 0x38 8013946: 633a str r2, [r7, #48] @ 0x30 8013948: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801394a: 6af9 ldr r1, [r7, #44] @ 0x2c 801394c: 6b3a ldr r2, [r7, #48] @ 0x30 801394e: e841 2300 strex r3, r2, [r1] 8013952: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013954: 6abb ldr r3, [r7, #40] @ 0x28 8013956: 2b00 cmp r3, #0 8013958: d1e5 bne.n 8013926 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 801395a: 6bfb ldr r3, [r7, #60] @ 0x3c 801395c: 681b ldr r3, [r3, #0] 801395e: 330c adds r3, #12 8013960: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013962: 693b ldr r3, [r7, #16] 8013964: e853 3f00 ldrex r3, [r3] 8013968: 60fb str r3, [r7, #12] return(result); 801396a: 68fb ldr r3, [r7, #12] 801396c: f043 0340 orr.w r3, r3, #64 @ 0x40 8013970: 637b str r3, [r7, #52] @ 0x34 8013972: 6bfb ldr r3, [r7, #60] @ 0x3c 8013974: 681b ldr r3, [r3, #0] 8013976: 330c adds r3, #12 8013978: 6b7a ldr r2, [r7, #52] @ 0x34 801397a: 61fa str r2, [r7, #28] 801397c: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801397e: 69b9 ldr r1, [r7, #24] 8013980: 69fa ldr r2, [r7, #28] 8013982: e841 2300 strex r3, r2, [r1] 8013986: 617b str r3, [r7, #20] return(result); 8013988: 697b ldr r3, [r7, #20] 801398a: 2b00 cmp r3, #0 801398c: d1e5 bne.n 801395a #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 801398e: e002 b.n 8013996 HAL_UART_TxCpltCallback(huart); 8013990: 6bf8 ldr r0, [r7, #60] @ 0x3c 8013992: f7f9 f95d bl 800cc50 } 8013996: bf00 nop 8013998: 3740 adds r7, #64 @ 0x40 801399a: 46bd mov sp, r7 801399c: bd80 pop {r7, pc} 0801399e : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 801399e: b580 push {r7, lr} 80139a0: b084 sub sp, #16 80139a2: af00 add r7, sp, #0 80139a4: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80139a6: 687b ldr r3, [r7, #4] 80139a8: 6a5b ldr r3, [r3, #36] @ 0x24 80139aa: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 80139ac: 68f8 ldr r0, [r7, #12] 80139ae: f7ff ff83 bl 80138b8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80139b2: bf00 nop 80139b4: 3710 adds r7, #16 80139b6: 46bd mov sp, r7 80139b8: bd80 pop {r7, pc} 080139ba : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 80139ba: b580 push {r7, lr} 80139bc: b09c sub sp, #112 @ 0x70 80139be: af00 add r7, sp, #0 80139c0: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80139c2: 687b ldr r3, [r7, #4] 80139c4: 6a5b ldr r3, [r3, #36] @ 0x24 80139c6: 66fb str r3, [r7, #108] @ 0x6c /* DMA Normal mode*/ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 80139c8: 687b ldr r3, [r7, #4] 80139ca: 681b ldr r3, [r3, #0] 80139cc: 681b ldr r3, [r3, #0] 80139ce: f003 0320 and.w r3, r3, #32 80139d2: 2b00 cmp r3, #0 80139d4: d172 bne.n 8013abc { huart->RxXferCount = 0U; 80139d6: 6efb ldr r3, [r7, #108] @ 0x6c 80139d8: 2200 movs r2, #0 80139da: 85da strh r2, [r3, #46] @ 0x2e /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80139dc: 6efb ldr r3, [r7, #108] @ 0x6c 80139de: 681b ldr r3, [r3, #0] 80139e0: 330c adds r3, #12 80139e2: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80139e4: 6cfb ldr r3, [r7, #76] @ 0x4c 80139e6: e853 3f00 ldrex r3, [r3] 80139ea: 64bb str r3, [r7, #72] @ 0x48 return(result); 80139ec: 6cbb ldr r3, [r7, #72] @ 0x48 80139ee: f423 7380 bic.w r3, r3, #256 @ 0x100 80139f2: 66bb str r3, [r7, #104] @ 0x68 80139f4: 6efb ldr r3, [r7, #108] @ 0x6c 80139f6: 681b ldr r3, [r3, #0] 80139f8: 330c adds r3, #12 80139fa: 6eba ldr r2, [r7, #104] @ 0x68 80139fc: 65ba str r2, [r7, #88] @ 0x58 80139fe: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013a00: 6d79 ldr r1, [r7, #84] @ 0x54 8013a02: 6dba ldr r2, [r7, #88] @ 0x58 8013a04: e841 2300 strex r3, r2, [r1] 8013a08: 653b str r3, [r7, #80] @ 0x50 return(result); 8013a0a: 6d3b ldr r3, [r7, #80] @ 0x50 8013a0c: 2b00 cmp r3, #0 8013a0e: d1e5 bne.n 80139dc ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013a10: 6efb ldr r3, [r7, #108] @ 0x6c 8013a12: 681b ldr r3, [r3, #0] 8013a14: 3314 adds r3, #20 8013a16: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013a18: 6bbb ldr r3, [r7, #56] @ 0x38 8013a1a: e853 3f00 ldrex r3, [r3] 8013a1e: 637b str r3, [r7, #52] @ 0x34 return(result); 8013a20: 6b7b ldr r3, [r7, #52] @ 0x34 8013a22: f023 0301 bic.w r3, r3, #1 8013a26: 667b str r3, [r7, #100] @ 0x64 8013a28: 6efb ldr r3, [r7, #108] @ 0x6c 8013a2a: 681b ldr r3, [r3, #0] 8013a2c: 3314 adds r3, #20 8013a2e: 6e7a ldr r2, [r7, #100] @ 0x64 8013a30: 647a str r2, [r7, #68] @ 0x44 8013a32: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013a34: 6c39 ldr r1, [r7, #64] @ 0x40 8013a36: 6c7a ldr r2, [r7, #68] @ 0x44 8013a38: e841 2300 strex r3, r2, [r1] 8013a3c: 63fb str r3, [r7, #60] @ 0x3c return(result); 8013a3e: 6bfb ldr r3, [r7, #60] @ 0x3c 8013a40: 2b00 cmp r3, #0 8013a42: d1e5 bne.n 8013a10 /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8013a44: 6efb ldr r3, [r7, #108] @ 0x6c 8013a46: 681b ldr r3, [r3, #0] 8013a48: 3314 adds r3, #20 8013a4a: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013a4c: 6a7b ldr r3, [r7, #36] @ 0x24 8013a4e: e853 3f00 ldrex r3, [r3] 8013a52: 623b str r3, [r7, #32] return(result); 8013a54: 6a3b ldr r3, [r7, #32] 8013a56: f023 0340 bic.w r3, r3, #64 @ 0x40 8013a5a: 663b str r3, [r7, #96] @ 0x60 8013a5c: 6efb ldr r3, [r7, #108] @ 0x6c 8013a5e: 681b ldr r3, [r3, #0] 8013a60: 3314 adds r3, #20 8013a62: 6e3a ldr r2, [r7, #96] @ 0x60 8013a64: 633a str r2, [r7, #48] @ 0x30 8013a66: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013a68: 6af9 ldr r1, [r7, #44] @ 0x2c 8013a6a: 6b3a ldr r2, [r7, #48] @ 0x30 8013a6c: e841 2300 strex r3, r2, [r1] 8013a70: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013a72: 6abb ldr r3, [r7, #40] @ 0x28 8013a74: 2b00 cmp r3, #0 8013a76: d1e5 bne.n 8013a44 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013a78: 6efb ldr r3, [r7, #108] @ 0x6c 8013a7a: 2220 movs r2, #32 8013a7c: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013a80: 6efb ldr r3, [r7, #108] @ 0x6c 8013a82: 6b1b ldr r3, [r3, #48] @ 0x30 8013a84: 2b01 cmp r3, #1 8013a86: d119 bne.n 8013abc { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013a88: 6efb ldr r3, [r7, #108] @ 0x6c 8013a8a: 681b ldr r3, [r3, #0] 8013a8c: 330c adds r3, #12 8013a8e: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013a90: 693b ldr r3, [r7, #16] 8013a92: e853 3f00 ldrex r3, [r3] 8013a96: 60fb str r3, [r7, #12] return(result); 8013a98: 68fb ldr r3, [r7, #12] 8013a9a: f023 0310 bic.w r3, r3, #16 8013a9e: 65fb str r3, [r7, #92] @ 0x5c 8013aa0: 6efb ldr r3, [r7, #108] @ 0x6c 8013aa2: 681b ldr r3, [r3, #0] 8013aa4: 330c adds r3, #12 8013aa6: 6dfa ldr r2, [r7, #92] @ 0x5c 8013aa8: 61fa str r2, [r7, #28] 8013aaa: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013aac: 69b9 ldr r1, [r7, #24] 8013aae: 69fa ldr r2, [r7, #28] 8013ab0: e841 2300 strex r3, r2, [r1] 8013ab4: 617b str r3, [r7, #20] return(result); 8013ab6: 697b ldr r3, [r7, #20] 8013ab8: 2b00 cmp r3, #0 8013aba: d1e5 bne.n 8013a88 } } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8013abc: 6efb ldr r3, [r7, #108] @ 0x6c 8013abe: 2200 movs r2, #0 8013ac0: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013ac2: 6efb ldr r3, [r7, #108] @ 0x6c 8013ac4: 6b1b ldr r3, [r3, #48] @ 0x30 8013ac6: 2b01 cmp r3, #1 8013ac8: d106 bne.n 8013ad8 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8013aca: 6efb ldr r3, [r7, #108] @ 0x6c 8013acc: 8d9b ldrh r3, [r3, #44] @ 0x2c 8013ace: 4619 mov r1, r3 8013ad0: 6ef8 ldr r0, [r7, #108] @ 0x6c 8013ad2: f7f9 f843 bl 800cb5c #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8013ad6: e002 b.n 8013ade HAL_UART_RxCpltCallback(huart); 8013ad8: 6ef8 ldr r0, [r7, #108] @ 0x6c 8013ada: f7ff fef6 bl 80138ca } 8013ade: bf00 nop 8013ae0: 3770 adds r7, #112 @ 0x70 8013ae2: 46bd mov sp, r7 8013ae4: bd80 pop {r7, pc} 08013ae6 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { 8013ae6: b580 push {r7, lr} 8013ae8: b084 sub sp, #16 8013aea: af00 add r7, sp, #0 8013aec: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013aee: 687b ldr r3, [r7, #4] 8013af0: 6a5b ldr r3, [r3, #36] @ 0x24 8013af2: 60fb str r3, [r7, #12] /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Half Transfer */ huart->RxEventType = HAL_UART_RXEVENT_HT; 8013af4: 68fb ldr r3, [r7, #12] 8013af6: 2201 movs r2, #1 8013af8: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013afa: 68fb ldr r3, [r7, #12] 8013afc: 6b1b ldr r3, [r3, #48] @ 0x30 8013afe: 2b01 cmp r3, #1 8013b00: d108 bne.n 8013b14 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); 8013b02: 68fb ldr r3, [r7, #12] 8013b04: 8d9b ldrh r3, [r3, #44] @ 0x2c 8013b06: 085b lsrs r3, r3, #1 8013b08: b29b uxth r3, r3 8013b0a: 4619 mov r1, r3 8013b0c: 68f8 ldr r0, [r7, #12] 8013b0e: f7f9 f825 bl 800cb5c #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8013b12: e002 b.n 8013b1a HAL_UART_RxHalfCpltCallback(huart); 8013b14: 68f8 ldr r0, [r7, #12] 8013b16: f7ff fee1 bl 80138dc } 8013b1a: bf00 nop 8013b1c: 3710 adds r7, #16 8013b1e: 46bd mov sp, r7 8013b20: bd80 pop {r7, pc} 08013b22 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 8013b22: b580 push {r7, lr} 8013b24: b084 sub sp, #16 8013b26: af00 add r7, sp, #0 8013b28: 6078 str r0, [r7, #4] uint32_t dmarequest = 0x00U; 8013b2a: 2300 movs r3, #0 8013b2c: 60fb str r3, [r7, #12] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013b2e: 687b ldr r3, [r7, #4] 8013b30: 6a5b ldr r3, [r3, #36] @ 0x24 8013b32: 60bb str r3, [r7, #8] /* Stop UART DMA Tx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 8013b34: 68bb ldr r3, [r7, #8] 8013b36: 681b ldr r3, [r3, #0] 8013b38: 695b ldr r3, [r3, #20] 8013b3a: f003 0380 and.w r3, r3, #128 @ 0x80 8013b3e: 2b00 cmp r3, #0 8013b40: bf14 ite ne 8013b42: 2301 movne r3, #1 8013b44: 2300 moveq r3, #0 8013b46: b2db uxtb r3, r3 8013b48: 60fb str r3, [r7, #12] if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 8013b4a: 68bb ldr r3, [r7, #8] 8013b4c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8013b50: b2db uxtb r3, r3 8013b52: 2b21 cmp r3, #33 @ 0x21 8013b54: d108 bne.n 8013b68 8013b56: 68fb ldr r3, [r7, #12] 8013b58: 2b00 cmp r3, #0 8013b5a: d005 beq.n 8013b68 { huart->TxXferCount = 0x00U; 8013b5c: 68bb ldr r3, [r7, #8] 8013b5e: 2200 movs r2, #0 8013b60: 84da strh r2, [r3, #38] @ 0x26 UART_EndTxTransfer(huart); 8013b62: 68b8 ldr r0, [r7, #8] 8013b64: f000 f8fa bl 8013d5c } /* Stop UART DMA Rx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8013b68: 68bb ldr r3, [r7, #8] 8013b6a: 681b ldr r3, [r3, #0] 8013b6c: 695b ldr r3, [r3, #20] 8013b6e: f003 0340 and.w r3, r3, #64 @ 0x40 8013b72: 2b00 cmp r3, #0 8013b74: bf14 ite ne 8013b76: 2301 movne r3, #1 8013b78: 2300 moveq r3, #0 8013b7a: b2db uxtb r3, r3 8013b7c: 60fb str r3, [r7, #12] if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 8013b7e: 68bb ldr r3, [r7, #8] 8013b80: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8013b84: b2db uxtb r3, r3 8013b86: 2b22 cmp r3, #34 @ 0x22 8013b88: d108 bne.n 8013b9c 8013b8a: 68fb ldr r3, [r7, #12] 8013b8c: 2b00 cmp r3, #0 8013b8e: d005 beq.n 8013b9c { huart->RxXferCount = 0x00U; 8013b90: 68bb ldr r3, [r7, #8] 8013b92: 2200 movs r2, #0 8013b94: 85da strh r2, [r3, #46] @ 0x2e UART_EndRxTransfer(huart); 8013b96: 68b8 ldr r0, [r7, #8] 8013b98: f000 f907 bl 8013daa } huart->ErrorCode |= HAL_UART_ERROR_DMA; 8013b9c: 68bb ldr r3, [r7, #8] 8013b9e: 6c5b ldr r3, [r3, #68] @ 0x44 8013ba0: f043 0210 orr.w r2, r3, #16 8013ba4: 68bb ldr r3, [r7, #8] 8013ba6: 645a str r2, [r3, #68] @ 0x44 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013ba8: 68b8 ldr r0, [r7, #8] 8013baa: f7f8 f88d bl 800bcc8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8013bae: bf00 nop 8013bb0: 3710 adds r7, #16 8013bb2: 46bd mov sp, r7 8013bb4: bd80 pop {r7, pc} 08013bb6 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8013bb6: b480 push {r7} 8013bb8: b085 sub sp, #20 8013bba: af00 add r7, sp, #0 8013bbc: 60f8 str r0, [r7, #12] 8013bbe: 60b9 str r1, [r7, #8] 8013bc0: 4613 mov r3, r2 8013bc2: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 8013bc4: 68fb ldr r3, [r7, #12] 8013bc6: 68ba ldr r2, [r7, #8] 8013bc8: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 8013bca: 68fb ldr r3, [r7, #12] 8013bcc: 88fa ldrh r2, [r7, #6] 8013bce: 859a strh r2, [r3, #44] @ 0x2c huart->RxXferCount = Size; 8013bd0: 68fb ldr r3, [r7, #12] 8013bd2: 88fa ldrh r2, [r7, #6] 8013bd4: 85da strh r2, [r3, #46] @ 0x2e huart->ErrorCode = HAL_UART_ERROR_NONE; 8013bd6: 68fb ldr r3, [r7, #12] 8013bd8: 2200 movs r2, #0 8013bda: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 8013bdc: 68fb ldr r3, [r7, #12] 8013bde: 2222 movs r2, #34 @ 0x22 8013be0: f883 2042 strb.w r2, [r3, #66] @ 0x42 if (huart->Init.Parity != UART_PARITY_NONE) 8013be4: 68fb ldr r3, [r7, #12] 8013be6: 691b ldr r3, [r3, #16] 8013be8: 2b00 cmp r3, #0 8013bea: d007 beq.n 8013bfc { /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); 8013bec: 68fb ldr r3, [r7, #12] 8013bee: 681b ldr r3, [r3, #0] 8013bf0: 68da ldr r2, [r3, #12] 8013bf2: 68fb ldr r3, [r7, #12] 8013bf4: 681b ldr r3, [r3, #0] 8013bf6: f442 7280 orr.w r2, r2, #256 @ 0x100 8013bfa: 60da str r2, [r3, #12] } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); 8013bfc: 68fb ldr r3, [r7, #12] 8013bfe: 681b ldr r3, [r3, #0] 8013c00: 695a ldr r2, [r3, #20] 8013c02: 68fb ldr r3, [r7, #12] 8013c04: 681b ldr r3, [r3, #0] 8013c06: f042 0201 orr.w r2, r2, #1 8013c0a: 615a str r2, [r3, #20] /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); 8013c0c: 68fb ldr r3, [r7, #12] 8013c0e: 681b ldr r3, [r3, #0] 8013c10: 68da ldr r2, [r3, #12] 8013c12: 68fb ldr r3, [r7, #12] 8013c14: 681b ldr r3, [r3, #0] 8013c16: f042 0220 orr.w r2, r2, #32 8013c1a: 60da str r2, [r3, #12] return HAL_OK; 8013c1c: 2300 movs r3, #0 } 8013c1e: 4618 mov r0, r3 8013c20: 3714 adds r7, #20 8013c22: 46bd mov sp, r7 8013c24: bc80 pop {r7} 8013c26: 4770 bx lr 08013c28 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8013c28: b580 push {r7, lr} 8013c2a: b098 sub sp, #96 @ 0x60 8013c2c: af00 add r7, sp, #0 8013c2e: 60f8 str r0, [r7, #12] 8013c30: 60b9 str r1, [r7, #8] 8013c32: 4613 mov r3, r2 8013c34: 80fb strh r3, [r7, #6] uint32_t *tmp; huart->pRxBuffPtr = pData; 8013c36: 68ba ldr r2, [r7, #8] 8013c38: 68fb ldr r3, [r7, #12] 8013c3a: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 8013c3c: 68fb ldr r3, [r7, #12] 8013c3e: 88fa ldrh r2, [r7, #6] 8013c40: 859a strh r2, [r3, #44] @ 0x2c huart->ErrorCode = HAL_UART_ERROR_NONE; 8013c42: 68fb ldr r3, [r7, #12] 8013c44: 2200 movs r2, #0 8013c46: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 8013c48: 68fb ldr r3, [r7, #12] 8013c4a: 2222 movs r2, #34 @ 0x22 8013c4c: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 8013c50: 68fb ldr r3, [r7, #12] 8013c52: 6bdb ldr r3, [r3, #60] @ 0x3c 8013c54: 4a3e ldr r2, [pc, #248] @ (8013d50 ) 8013c56: 629a str r2, [r3, #40] @ 0x28 /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 8013c58: 68fb ldr r3, [r7, #12] 8013c5a: 6bdb ldr r3, [r3, #60] @ 0x3c 8013c5c: 4a3d ldr r2, [pc, #244] @ (8013d54 ) 8013c5e: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; 8013c60: 68fb ldr r3, [r7, #12] 8013c62: 6bdb ldr r3, [r3, #60] @ 0x3c 8013c64: 4a3c ldr r2, [pc, #240] @ (8013d58 ) 8013c66: 631a str r2, [r3, #48] @ 0x30 /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; 8013c68: 68fb ldr r3, [r7, #12] 8013c6a: 6bdb ldr r3, [r3, #60] @ 0x3c 8013c6c: 2200 movs r2, #0 8013c6e: 635a str r2, [r3, #52] @ 0x34 /* Enable the DMA stream */ tmp = (uint32_t *)&pData; 8013c70: f107 0308 add.w r3, r7, #8 8013c74: 65fb str r3, [r7, #92] @ 0x5c HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size); 8013c76: 68fb ldr r3, [r7, #12] 8013c78: 6bd8 ldr r0, [r3, #60] @ 0x3c 8013c7a: 68fb ldr r3, [r7, #12] 8013c7c: 681b ldr r3, [r3, #0] 8013c7e: 3304 adds r3, #4 8013c80: 4619 mov r1, r3 8013c82: 6dfb ldr r3, [r7, #92] @ 0x5c 8013c84: 681a ldr r2, [r3, #0] 8013c86: 88fb ldrh r3, [r7, #6] 8013c88: f7fc f93a bl 800ff00 /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); 8013c8c: 2300 movs r3, #0 8013c8e: 613b str r3, [r7, #16] 8013c90: 68fb ldr r3, [r7, #12] 8013c92: 681b ldr r3, [r3, #0] 8013c94: 681b ldr r3, [r3, #0] 8013c96: 613b str r3, [r7, #16] 8013c98: 68fb ldr r3, [r7, #12] 8013c9a: 681b ldr r3, [r3, #0] 8013c9c: 685b ldr r3, [r3, #4] 8013c9e: 613b str r3, [r7, #16] 8013ca0: 693b ldr r3, [r7, #16] if (huart->Init.Parity != UART_PARITY_NONE) 8013ca2: 68fb ldr r3, [r7, #12] 8013ca4: 691b ldr r3, [r3, #16] 8013ca6: 2b00 cmp r3, #0 8013ca8: d019 beq.n 8013cde { /* Enable the UART Parity Error Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8013caa: 68fb ldr r3, [r7, #12] 8013cac: 681b ldr r3, [r3, #0] 8013cae: 330c adds r3, #12 8013cb0: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013cb2: 6c3b ldr r3, [r7, #64] @ 0x40 8013cb4: e853 3f00 ldrex r3, [r3] 8013cb8: 63fb str r3, [r7, #60] @ 0x3c return(result); 8013cba: 6bfb ldr r3, [r7, #60] @ 0x3c 8013cbc: f443 7380 orr.w r3, r3, #256 @ 0x100 8013cc0: 65bb str r3, [r7, #88] @ 0x58 8013cc2: 68fb ldr r3, [r7, #12] 8013cc4: 681b ldr r3, [r3, #0] 8013cc6: 330c adds r3, #12 8013cc8: 6dba ldr r2, [r7, #88] @ 0x58 8013cca: 64fa str r2, [r7, #76] @ 0x4c 8013ccc: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013cce: 6cb9 ldr r1, [r7, #72] @ 0x48 8013cd0: 6cfa ldr r2, [r7, #76] @ 0x4c 8013cd2: e841 2300 strex r3, r2, [r1] 8013cd6: 647b str r3, [r7, #68] @ 0x44 return(result); 8013cd8: 6c7b ldr r3, [r7, #68] @ 0x44 8013cda: 2b00 cmp r3, #0 8013cdc: d1e5 bne.n 8013caa } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013cde: 68fb ldr r3, [r7, #12] 8013ce0: 681b ldr r3, [r3, #0] 8013ce2: 3314 adds r3, #20 8013ce4: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013ce6: 6afb ldr r3, [r7, #44] @ 0x2c 8013ce8: e853 3f00 ldrex r3, [r3] 8013cec: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013cee: 6abb ldr r3, [r7, #40] @ 0x28 8013cf0: f043 0301 orr.w r3, r3, #1 8013cf4: 657b str r3, [r7, #84] @ 0x54 8013cf6: 68fb ldr r3, [r7, #12] 8013cf8: 681b ldr r3, [r3, #0] 8013cfa: 3314 adds r3, #20 8013cfc: 6d7a ldr r2, [r7, #84] @ 0x54 8013cfe: 63ba str r2, [r7, #56] @ 0x38 8013d00: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013d02: 6b79 ldr r1, [r7, #52] @ 0x34 8013d04: 6bba ldr r2, [r7, #56] @ 0x38 8013d06: e841 2300 strex r3, r2, [r1] 8013d0a: 633b str r3, [r7, #48] @ 0x30 return(result); 8013d0c: 6b3b ldr r3, [r7, #48] @ 0x30 8013d0e: 2b00 cmp r3, #0 8013d10: d1e5 bne.n 8013cde /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8013d12: 68fb ldr r3, [r7, #12] 8013d14: 681b ldr r3, [r3, #0] 8013d16: 3314 adds r3, #20 8013d18: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013d1a: 69bb ldr r3, [r7, #24] 8013d1c: e853 3f00 ldrex r3, [r3] 8013d20: 617b str r3, [r7, #20] return(result); 8013d22: 697b ldr r3, [r7, #20] 8013d24: f043 0340 orr.w r3, r3, #64 @ 0x40 8013d28: 653b str r3, [r7, #80] @ 0x50 8013d2a: 68fb ldr r3, [r7, #12] 8013d2c: 681b ldr r3, [r3, #0] 8013d2e: 3314 adds r3, #20 8013d30: 6d3a ldr r2, [r7, #80] @ 0x50 8013d32: 627a str r2, [r7, #36] @ 0x24 8013d34: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013d36: 6a39 ldr r1, [r7, #32] 8013d38: 6a7a ldr r2, [r7, #36] @ 0x24 8013d3a: e841 2300 strex r3, r2, [r1] 8013d3e: 61fb str r3, [r7, #28] return(result); 8013d40: 69fb ldr r3, [r7, #28] 8013d42: 2b00 cmp r3, #0 8013d44: d1e5 bne.n 8013d12 return HAL_OK; 8013d46: 2300 movs r3, #0 } 8013d48: 4618 mov r0, r3 8013d4a: 3760 adds r7, #96 @ 0x60 8013d4c: 46bd mov sp, r7 8013d4e: bd80 pop {r7, pc} 8013d50: 080139bb .word 0x080139bb 8013d54: 08013ae7 .word 0x08013ae7 8013d58: 08013b23 .word 0x08013b23 08013d5c : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 8013d5c: b480 push {r7} 8013d5e: b089 sub sp, #36 @ 0x24 8013d60: af00 add r7, sp, #0 8013d62: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 8013d64: 687b ldr r3, [r7, #4] 8013d66: 681b ldr r3, [r3, #0] 8013d68: 330c adds r3, #12 8013d6a: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013d6c: 68fb ldr r3, [r7, #12] 8013d6e: e853 3f00 ldrex r3, [r3] 8013d72: 60bb str r3, [r7, #8] return(result); 8013d74: 68bb ldr r3, [r7, #8] 8013d76: f023 03c0 bic.w r3, r3, #192 @ 0xc0 8013d7a: 61fb str r3, [r7, #28] 8013d7c: 687b ldr r3, [r7, #4] 8013d7e: 681b ldr r3, [r3, #0] 8013d80: 330c adds r3, #12 8013d82: 69fa ldr r2, [r7, #28] 8013d84: 61ba str r2, [r7, #24] 8013d86: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013d88: 6979 ldr r1, [r7, #20] 8013d8a: 69ba ldr r2, [r7, #24] 8013d8c: e841 2300 strex r3, r2, [r1] 8013d90: 613b str r3, [r7, #16] return(result); 8013d92: 693b ldr r3, [r7, #16] 8013d94: 2b00 cmp r3, #0 8013d96: d1e5 bne.n 8013d64 /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8013d98: 687b ldr r3, [r7, #4] 8013d9a: 2220 movs r2, #32 8013d9c: f883 2041 strb.w r2, [r3, #65] @ 0x41 } 8013da0: bf00 nop 8013da2: 3724 adds r7, #36 @ 0x24 8013da4: 46bd mov sp, r7 8013da6: bc80 pop {r7} 8013da8: 4770 bx lr 08013daa : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8013daa: b480 push {r7} 8013dac: b095 sub sp, #84 @ 0x54 8013dae: af00 add r7, sp, #0 8013db0: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8013db2: 687b ldr r3, [r7, #4] 8013db4: 681b ldr r3, [r3, #0] 8013db6: 330c adds r3, #12 8013db8: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013dba: 6b7b ldr r3, [r7, #52] @ 0x34 8013dbc: e853 3f00 ldrex r3, [r3] 8013dc0: 633b str r3, [r7, #48] @ 0x30 return(result); 8013dc2: 6b3b ldr r3, [r7, #48] @ 0x30 8013dc4: f423 7390 bic.w r3, r3, #288 @ 0x120 8013dc8: 64fb str r3, [r7, #76] @ 0x4c 8013dca: 687b ldr r3, [r7, #4] 8013dcc: 681b ldr r3, [r3, #0] 8013dce: 330c adds r3, #12 8013dd0: 6cfa ldr r2, [r7, #76] @ 0x4c 8013dd2: 643a str r2, [r7, #64] @ 0x40 8013dd4: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013dd6: 6bf9 ldr r1, [r7, #60] @ 0x3c 8013dd8: 6c3a ldr r2, [r7, #64] @ 0x40 8013dda: e841 2300 strex r3, r2, [r1] 8013dde: 63bb str r3, [r7, #56] @ 0x38 return(result); 8013de0: 6bbb ldr r3, [r7, #56] @ 0x38 8013de2: 2b00 cmp r3, #0 8013de4: d1e5 bne.n 8013db2 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013de6: 687b ldr r3, [r7, #4] 8013de8: 681b ldr r3, [r3, #0] 8013dea: 3314 adds r3, #20 8013dec: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013dee: 6a3b ldr r3, [r7, #32] 8013df0: e853 3f00 ldrex r3, [r3] 8013df4: 61fb str r3, [r7, #28] return(result); 8013df6: 69fb ldr r3, [r7, #28] 8013df8: f023 0301 bic.w r3, r3, #1 8013dfc: 64bb str r3, [r7, #72] @ 0x48 8013dfe: 687b ldr r3, [r7, #4] 8013e00: 681b ldr r3, [r3, #0] 8013e02: 3314 adds r3, #20 8013e04: 6cba ldr r2, [r7, #72] @ 0x48 8013e06: 62fa str r2, [r7, #44] @ 0x2c 8013e08: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013e0a: 6ab9 ldr r1, [r7, #40] @ 0x28 8013e0c: 6afa ldr r2, [r7, #44] @ 0x2c 8013e0e: e841 2300 strex r3, r2, [r1] 8013e12: 627b str r3, [r7, #36] @ 0x24 return(result); 8013e14: 6a7b ldr r3, [r7, #36] @ 0x24 8013e16: 2b00 cmp r3, #0 8013e18: d1e5 bne.n 8013de6 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013e1a: 687b ldr r3, [r7, #4] 8013e1c: 6b1b ldr r3, [r3, #48] @ 0x30 8013e1e: 2b01 cmp r3, #1 8013e20: d119 bne.n 8013e56 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013e22: 687b ldr r3, [r7, #4] 8013e24: 681b ldr r3, [r3, #0] 8013e26: 330c adds r3, #12 8013e28: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013e2a: 68fb ldr r3, [r7, #12] 8013e2c: e853 3f00 ldrex r3, [r3] 8013e30: 60bb str r3, [r7, #8] return(result); 8013e32: 68bb ldr r3, [r7, #8] 8013e34: f023 0310 bic.w r3, r3, #16 8013e38: 647b str r3, [r7, #68] @ 0x44 8013e3a: 687b ldr r3, [r7, #4] 8013e3c: 681b ldr r3, [r3, #0] 8013e3e: 330c adds r3, #12 8013e40: 6c7a ldr r2, [r7, #68] @ 0x44 8013e42: 61ba str r2, [r7, #24] 8013e44: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013e46: 6979 ldr r1, [r7, #20] 8013e48: 69ba ldr r2, [r7, #24] 8013e4a: e841 2300 strex r3, r2, [r1] 8013e4e: 613b str r3, [r7, #16] return(result); 8013e50: 693b ldr r3, [r7, #16] 8013e52: 2b00 cmp r3, #0 8013e54: d1e5 bne.n 8013e22 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013e56: 687b ldr r3, [r7, #4] 8013e58: 2220 movs r2, #32 8013e5a: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013e5e: 687b ldr r3, [r7, #4] 8013e60: 2200 movs r2, #0 8013e62: 631a str r2, [r3, #48] @ 0x30 } 8013e64: bf00 nop 8013e66: 3754 adds r7, #84 @ 0x54 8013e68: 46bd mov sp, r7 8013e6a: bc80 pop {r7} 8013e6c: 4770 bx lr 08013e6e : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8013e6e: b580 push {r7, lr} 8013e70: b084 sub sp, #16 8013e72: af00 add r7, sp, #0 8013e74: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013e76: 687b ldr r3, [r7, #4] 8013e78: 6a5b ldr r3, [r3, #36] @ 0x24 8013e7a: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8013e7c: 68fb ldr r3, [r7, #12] 8013e7e: 2200 movs r2, #0 8013e80: 85da strh r2, [r3, #46] @ 0x2e huart->TxXferCount = 0x00U; 8013e82: 68fb ldr r3, [r7, #12] 8013e84: 2200 movs r2, #0 8013e86: 84da strh r2, [r3, #38] @ 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013e88: 68f8 ldr r0, [r7, #12] 8013e8a: f7f7 ff1d bl 800bcc8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8013e8e: bf00 nop 8013e90: 3710 adds r7, #16 8013e92: 46bd mov sp, r7 8013e94: bd80 pop {r7, pc} 08013e96 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 8013e96: b480 push {r7} 8013e98: b085 sub sp, #20 8013e9a: af00 add r7, sp, #0 8013e9c: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8013e9e: 687b ldr r3, [r7, #4] 8013ea0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8013ea4: b2db uxtb r3, r3 8013ea6: 2b21 cmp r3, #33 @ 0x21 8013ea8: d13e bne.n 8013f28 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8013eaa: 687b ldr r3, [r7, #4] 8013eac: 689b ldr r3, [r3, #8] 8013eae: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8013eb2: d114 bne.n 8013ede 8013eb4: 687b ldr r3, [r7, #4] 8013eb6: 691b ldr r3, [r3, #16] 8013eb8: 2b00 cmp r3, #0 8013eba: d110 bne.n 8013ede { tmp = (const uint16_t *) huart->pTxBuffPtr; 8013ebc: 687b ldr r3, [r7, #4] 8013ebe: 6a1b ldr r3, [r3, #32] 8013ec0: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8013ec2: 68fb ldr r3, [r7, #12] 8013ec4: 881b ldrh r3, [r3, #0] 8013ec6: 461a mov r2, r3 8013ec8: 687b ldr r3, [r7, #4] 8013eca: 681b ldr r3, [r3, #0] 8013ecc: f3c2 0208 ubfx r2, r2, #0, #9 8013ed0: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 8013ed2: 687b ldr r3, [r7, #4] 8013ed4: 6a1b ldr r3, [r3, #32] 8013ed6: 1c9a adds r2, r3, #2 8013ed8: 687b ldr r3, [r7, #4] 8013eda: 621a str r2, [r3, #32] 8013edc: e008 b.n 8013ef0 } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 8013ede: 687b ldr r3, [r7, #4] 8013ee0: 6a1b ldr r3, [r3, #32] 8013ee2: 1c59 adds r1, r3, #1 8013ee4: 687a ldr r2, [r7, #4] 8013ee6: 6211 str r1, [r2, #32] 8013ee8: 781a ldrb r2, [r3, #0] 8013eea: 687b ldr r3, [r7, #4] 8013eec: 681b ldr r3, [r3, #0] 8013eee: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 8013ef0: 687b ldr r3, [r7, #4] 8013ef2: 8cdb ldrh r3, [r3, #38] @ 0x26 8013ef4: b29b uxth r3, r3 8013ef6: 3b01 subs r3, #1 8013ef8: b29b uxth r3, r3 8013efa: 687a ldr r2, [r7, #4] 8013efc: 4619 mov r1, r3 8013efe: 84d1 strh r1, [r2, #38] @ 0x26 8013f00: 2b00 cmp r3, #0 8013f02: d10f bne.n 8013f24 { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8013f04: 687b ldr r3, [r7, #4] 8013f06: 681b ldr r3, [r3, #0] 8013f08: 68da ldr r2, [r3, #12] 8013f0a: 687b ldr r3, [r7, #4] 8013f0c: 681b ldr r3, [r3, #0] 8013f0e: f022 0280 bic.w r2, r2, #128 @ 0x80 8013f12: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8013f14: 687b ldr r3, [r7, #4] 8013f16: 681b ldr r3, [r3, #0] 8013f18: 68da ldr r2, [r3, #12] 8013f1a: 687b ldr r3, [r7, #4] 8013f1c: 681b ldr r3, [r3, #0] 8013f1e: f042 0240 orr.w r2, r2, #64 @ 0x40 8013f22: 60da str r2, [r3, #12] } return HAL_OK; 8013f24: 2300 movs r3, #0 8013f26: e000 b.n 8013f2a } else { return HAL_BUSY; 8013f28: 2302 movs r3, #2 } } 8013f2a: 4618 mov r0, r3 8013f2c: 3714 adds r7, #20 8013f2e: 46bd mov sp, r7 8013f30: bc80 pop {r7} 8013f32: 4770 bx lr 08013f34 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8013f34: b580 push {r7, lr} 8013f36: b082 sub sp, #8 8013f38: af00 add r7, sp, #0 8013f3a: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 8013f3c: 687b ldr r3, [r7, #4] 8013f3e: 681b ldr r3, [r3, #0] 8013f40: 68da ldr r2, [r3, #12] 8013f42: 687b ldr r3, [r7, #4] 8013f44: 681b ldr r3, [r3, #0] 8013f46: f022 0240 bic.w r2, r2, #64 @ 0x40 8013f4a: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8013f4c: 687b ldr r3, [r7, #4] 8013f4e: 2220 movs r2, #32 8013f50: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8013f54: 6878 ldr r0, [r7, #4] 8013f56: f7f8 fe7b bl 800cc50 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8013f5a: 2300 movs r3, #0 } 8013f5c: 4618 mov r0, r3 8013f5e: 3708 adds r7, #8 8013f60: 46bd mov sp, r7 8013f62: bd80 pop {r7, pc} 08013f64 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 8013f64: b580 push {r7, lr} 8013f66: b08c sub sp, #48 @ 0x30 8013f68: af00 add r7, sp, #0 8013f6a: 6078 str r0, [r7, #4] uint8_t *pdata8bits; uint16_t *pdata16bits; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8013f6c: 687b ldr r3, [r7, #4] 8013f6e: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8013f72: b2db uxtb r3, r3 8013f74: 2b22 cmp r3, #34 @ 0x22 8013f76: f040 80ae bne.w 80140d6 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8013f7a: 687b ldr r3, [r7, #4] 8013f7c: 689b ldr r3, [r3, #8] 8013f7e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8013f82: d117 bne.n 8013fb4 8013f84: 687b ldr r3, [r7, #4] 8013f86: 691b ldr r3, [r3, #16] 8013f88: 2b00 cmp r3, #0 8013f8a: d113 bne.n 8013fb4 { pdata8bits = NULL; 8013f8c: 2300 movs r3, #0 8013f8e: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = (uint16_t *) huart->pRxBuffPtr; 8013f90: 687b ldr r3, [r7, #4] 8013f92: 6a9b ldr r3, [r3, #40] @ 0x28 8013f94: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8013f96: 687b ldr r3, [r7, #4] 8013f98: 681b ldr r3, [r3, #0] 8013f9a: 685b ldr r3, [r3, #4] 8013f9c: b29b uxth r3, r3 8013f9e: f3c3 0308 ubfx r3, r3, #0, #9 8013fa2: b29a uxth r2, r3 8013fa4: 6abb ldr r3, [r7, #40] @ 0x28 8013fa6: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8013fa8: 687b ldr r3, [r7, #4] 8013faa: 6a9b ldr r3, [r3, #40] @ 0x28 8013fac: 1c9a adds r2, r3, #2 8013fae: 687b ldr r3, [r7, #4] 8013fb0: 629a str r2, [r3, #40] @ 0x28 8013fb2: e026 b.n 8014002 } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8013fb4: 687b ldr r3, [r7, #4] 8013fb6: 6a9b ldr r3, [r3, #40] @ 0x28 8013fb8: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = NULL; 8013fba: 2300 movs r3, #0 8013fbc: 62bb str r3, [r7, #40] @ 0x28 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 8013fbe: 687b ldr r3, [r7, #4] 8013fc0: 689b ldr r3, [r3, #8] 8013fc2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8013fc6: d007 beq.n 8013fd8 8013fc8: 687b ldr r3, [r7, #4] 8013fca: 689b ldr r3, [r3, #8] 8013fcc: 2b00 cmp r3, #0 8013fce: d10a bne.n 8013fe6 8013fd0: 687b ldr r3, [r7, #4] 8013fd2: 691b ldr r3, [r3, #16] 8013fd4: 2b00 cmp r3, #0 8013fd6: d106 bne.n 8013fe6 { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8013fd8: 687b ldr r3, [r7, #4] 8013fda: 681b ldr r3, [r3, #0] 8013fdc: 685b ldr r3, [r3, #4] 8013fde: b2da uxtb r2, r3 8013fe0: 6afb ldr r3, [r7, #44] @ 0x2c 8013fe2: 701a strb r2, [r3, #0] 8013fe4: e008 b.n 8013ff8 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8013fe6: 687b ldr r3, [r7, #4] 8013fe8: 681b ldr r3, [r3, #0] 8013fea: 685b ldr r3, [r3, #4] 8013fec: b2db uxtb r3, r3 8013fee: f003 037f and.w r3, r3, #127 @ 0x7f 8013ff2: b2da uxtb r2, r3 8013ff4: 6afb ldr r3, [r7, #44] @ 0x2c 8013ff6: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8013ff8: 687b ldr r3, [r7, #4] 8013ffa: 6a9b ldr r3, [r3, #40] @ 0x28 8013ffc: 1c5a adds r2, r3, #1 8013ffe: 687b ldr r3, [r7, #4] 8014000: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 8014002: 687b ldr r3, [r7, #4] 8014004: 8ddb ldrh r3, [r3, #46] @ 0x2e 8014006: b29b uxth r3, r3 8014008: 3b01 subs r3, #1 801400a: b29b uxth r3, r3 801400c: 687a ldr r2, [r7, #4] 801400e: 4619 mov r1, r3 8014010: 85d1 strh r1, [r2, #46] @ 0x2e 8014012: 2b00 cmp r3, #0 8014014: d15d bne.n 80140d2 { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8014016: 687b ldr r3, [r7, #4] 8014018: 681b ldr r3, [r3, #0] 801401a: 68da ldr r2, [r3, #12] 801401c: 687b ldr r3, [r7, #4] 801401e: 681b ldr r3, [r3, #0] 8014020: f022 0220 bic.w r2, r2, #32 8014024: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8014026: 687b ldr r3, [r7, #4] 8014028: 681b ldr r3, [r3, #0] 801402a: 68da ldr r2, [r3, #12] 801402c: 687b ldr r3, [r7, #4] 801402e: 681b ldr r3, [r3, #0] 8014030: f422 7280 bic.w r2, r2, #256 @ 0x100 8014034: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8014036: 687b ldr r3, [r7, #4] 8014038: 681b ldr r3, [r3, #0] 801403a: 695a ldr r2, [r3, #20] 801403c: 687b ldr r3, [r7, #4] 801403e: 681b ldr r3, [r3, #0] 8014040: f022 0201 bic.w r2, r2, #1 8014044: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8014046: 687b ldr r3, [r7, #4] 8014048: 2220 movs r2, #32 801404a: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 801404e: 687b ldr r3, [r7, #4] 8014050: 2200 movs r2, #0 8014052: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8014054: 687b ldr r3, [r7, #4] 8014056: 6b1b ldr r3, [r3, #48] @ 0x30 8014058: 2b01 cmp r3, #1 801405a: d135 bne.n 80140c8 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801405c: 687b ldr r3, [r7, #4] 801405e: 2200 movs r2, #0 8014060: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8014062: 687b ldr r3, [r7, #4] 8014064: 681b ldr r3, [r3, #0] 8014066: 330c adds r3, #12 8014068: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801406a: 697b ldr r3, [r7, #20] 801406c: e853 3f00 ldrex r3, [r3] 8014070: 613b str r3, [r7, #16] return(result); 8014072: 693b ldr r3, [r7, #16] 8014074: f023 0310 bic.w r3, r3, #16 8014078: 627b str r3, [r7, #36] @ 0x24 801407a: 687b ldr r3, [r7, #4] 801407c: 681b ldr r3, [r3, #0] 801407e: 330c adds r3, #12 8014080: 6a7a ldr r2, [r7, #36] @ 0x24 8014082: 623a str r2, [r7, #32] 8014084: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8014086: 69f9 ldr r1, [r7, #28] 8014088: 6a3a ldr r2, [r7, #32] 801408a: e841 2300 strex r3, r2, [r1] 801408e: 61bb str r3, [r7, #24] return(result); 8014090: 69bb ldr r3, [r7, #24] 8014092: 2b00 cmp r3, #0 8014094: d1e5 bne.n 8014062 /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 8014096: 687b ldr r3, [r7, #4] 8014098: 681b ldr r3, [r3, #0] 801409a: 681b ldr r3, [r3, #0] 801409c: f003 0310 and.w r3, r3, #16 80140a0: 2b10 cmp r3, #16 80140a2: d10a bne.n 80140ba { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 80140a4: 2300 movs r3, #0 80140a6: 60fb str r3, [r7, #12] 80140a8: 687b ldr r3, [r7, #4] 80140aa: 681b ldr r3, [r3, #0] 80140ac: 681b ldr r3, [r3, #0] 80140ae: 60fb str r3, [r7, #12] 80140b0: 687b ldr r3, [r7, #4] 80140b2: 681b ldr r3, [r3, #0] 80140b4: 685b ldr r3, [r3, #4] 80140b6: 60fb str r3, [r7, #12] 80140b8: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 80140ba: 687b ldr r3, [r7, #4] 80140bc: 8d9b ldrh r3, [r3, #44] @ 0x2c 80140be: 4619 mov r1, r3 80140c0: 6878 ldr r0, [r7, #4] 80140c2: f7f8 fd4b bl 800cb5c 80140c6: e002 b.n 80140ce #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 80140c8: 6878 ldr r0, [r7, #4] 80140ca: f7ff fbfe bl 80138ca #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 80140ce: 2300 movs r3, #0 80140d0: e002 b.n 80140d8 } return HAL_OK; 80140d2: 2300 movs r3, #0 80140d4: e000 b.n 80140d8 } else { return HAL_BUSY; 80140d6: 2302 movs r3, #2 } } 80140d8: 4618 mov r0, r3 80140da: 3730 adds r7, #48 @ 0x30 80140dc: 46bd mov sp, r7 80140de: bd80 pop {r7, pc} 080140e0 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 80140e0: b580 push {r7, lr} 80140e2: b084 sub sp, #16 80140e4: af00 add r7, sp, #0 80140e6: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 80140e8: 687b ldr r3, [r7, #4] 80140ea: 681b ldr r3, [r3, #0] 80140ec: 691b ldr r3, [r3, #16] 80140ee: f423 5140 bic.w r1, r3, #12288 @ 0x3000 80140f2: 687b ldr r3, [r7, #4] 80140f4: 68da ldr r2, [r3, #12] 80140f6: 687b ldr r3, [r7, #4] 80140f8: 681b ldr r3, [r3, #0] 80140fa: 430a orrs r2, r1 80140fc: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 80140fe: 687b ldr r3, [r7, #4] 8014100: 689a ldr r2, [r3, #8] 8014102: 687b ldr r3, [r7, #4] 8014104: 691b ldr r3, [r3, #16] 8014106: 431a orrs r2, r3 8014108: 687b ldr r3, [r7, #4] 801410a: 695b ldr r3, [r3, #20] 801410c: 4313 orrs r3, r2 801410e: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 8014110: 687b ldr r3, [r7, #4] 8014112: 681b ldr r3, [r3, #0] 8014114: 68db ldr r3, [r3, #12] 8014116: f423 53b0 bic.w r3, r3, #5632 @ 0x1600 801411a: f023 030c bic.w r3, r3, #12 801411e: 687a ldr r2, [r7, #4] 8014120: 6812 ldr r2, [r2, #0] 8014122: 68b9 ldr r1, [r7, #8] 8014124: 430b orrs r3, r1 8014126: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8014128: 687b ldr r3, [r7, #4] 801412a: 681b ldr r3, [r3, #0] 801412c: 695b ldr r3, [r3, #20] 801412e: f423 7140 bic.w r1, r3, #768 @ 0x300 8014132: 687b ldr r3, [r7, #4] 8014134: 699a ldr r2, [r3, #24] 8014136: 687b ldr r3, [r7, #4] 8014138: 681b ldr r3, [r3, #0] 801413a: 430a orrs r2, r1 801413c: 615a str r2, [r3, #20] if(huart->Instance == USART1) 801413e: 687b ldr r3, [r7, #4] 8014140: 681b ldr r3, [r3, #0] 8014142: 4a2c ldr r2, [pc, #176] @ (80141f4 ) 8014144: 4293 cmp r3, r2 8014146: d103 bne.n 8014150 { pclk = HAL_RCC_GetPCLK2Freq(); 8014148: f7fd fa5c bl 8011604 801414c: 60f8 str r0, [r7, #12] 801414e: e002 b.n 8014156 } else { pclk = HAL_RCC_GetPCLK1Freq(); 8014150: f7fd fa44 bl 80115dc 8014154: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8014156: 68fa ldr r2, [r7, #12] 8014158: 4613 mov r3, r2 801415a: 009b lsls r3, r3, #2 801415c: 4413 add r3, r2 801415e: 009a lsls r2, r3, #2 8014160: 441a add r2, r3 8014162: 687b ldr r3, [r7, #4] 8014164: 685b ldr r3, [r3, #4] 8014166: 009b lsls r3, r3, #2 8014168: fbb2 f3f3 udiv r3, r2, r3 801416c: 4a22 ldr r2, [pc, #136] @ (80141f8 ) 801416e: fba2 2303 umull r2, r3, r2, r3 8014172: 095b lsrs r3, r3, #5 8014174: 0119 lsls r1, r3, #4 8014176: 68fa ldr r2, [r7, #12] 8014178: 4613 mov r3, r2 801417a: 009b lsls r3, r3, #2 801417c: 4413 add r3, r2 801417e: 009a lsls r2, r3, #2 8014180: 441a add r2, r3 8014182: 687b ldr r3, [r7, #4] 8014184: 685b ldr r3, [r3, #4] 8014186: 009b lsls r3, r3, #2 8014188: fbb2 f2f3 udiv r2, r2, r3 801418c: 4b1a ldr r3, [pc, #104] @ (80141f8 ) 801418e: fba3 0302 umull r0, r3, r3, r2 8014192: 095b lsrs r3, r3, #5 8014194: 2064 movs r0, #100 @ 0x64 8014196: fb00 f303 mul.w r3, r0, r3 801419a: 1ad3 subs r3, r2, r3 801419c: 011b lsls r3, r3, #4 801419e: 3332 adds r3, #50 @ 0x32 80141a0: 4a15 ldr r2, [pc, #84] @ (80141f8 ) 80141a2: fba2 2303 umull r2, r3, r2, r3 80141a6: 095b lsrs r3, r3, #5 80141a8: f003 03f0 and.w r3, r3, #240 @ 0xf0 80141ac: 4419 add r1, r3 80141ae: 68fa ldr r2, [r7, #12] 80141b0: 4613 mov r3, r2 80141b2: 009b lsls r3, r3, #2 80141b4: 4413 add r3, r2 80141b6: 009a lsls r2, r3, #2 80141b8: 441a add r2, r3 80141ba: 687b ldr r3, [r7, #4] 80141bc: 685b ldr r3, [r3, #4] 80141be: 009b lsls r3, r3, #2 80141c0: fbb2 f2f3 udiv r2, r2, r3 80141c4: 4b0c ldr r3, [pc, #48] @ (80141f8 ) 80141c6: fba3 0302 umull r0, r3, r3, r2 80141ca: 095b lsrs r3, r3, #5 80141cc: 2064 movs r0, #100 @ 0x64 80141ce: fb00 f303 mul.w r3, r0, r3 80141d2: 1ad3 subs r3, r2, r3 80141d4: 011b lsls r3, r3, #4 80141d6: 3332 adds r3, #50 @ 0x32 80141d8: 4a07 ldr r2, [pc, #28] @ (80141f8 ) 80141da: fba2 2303 umull r2, r3, r2, r3 80141de: 095b lsrs r3, r3, #5 80141e0: f003 020f and.w r2, r3, #15 80141e4: 687b ldr r3, [r7, #4] 80141e6: 681b ldr r3, [r3, #0] 80141e8: 440a add r2, r1 80141ea: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 80141ec: bf00 nop 80141ee: 3710 adds r7, #16 80141f0: 46bd mov sp, r7 80141f2: bd80 pop {r7, pc} 80141f4: 40013800 .word 0x40013800 80141f8: 51eb851f .word 0x51eb851f 080141fc <__cvt>: 80141fc: 2b00 cmp r3, #0 80141fe: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8014202: 461d mov r5, r3 8014204: bfbb ittet lt 8014206: f103 4300 addlt.w r3, r3, #2147483648 @ 0x80000000 801420a: 461d movlt r5, r3 801420c: 2300 movge r3, #0 801420e: 232d movlt r3, #45 @ 0x2d 8014210: b088 sub sp, #32 8014212: 4614 mov r4, r2 8014214: bfb8 it lt 8014216: 4614 movlt r4, r2 8014218: 9a12 ldr r2, [sp, #72] @ 0x48 801421a: 9e10 ldr r6, [sp, #64] @ 0x40 801421c: 7013 strb r3, [r2, #0] 801421e: 9b14 ldr r3, [sp, #80] @ 0x50 8014220: f8dd a04c ldr.w sl, [sp, #76] @ 0x4c 8014224: f023 0820 bic.w r8, r3, #32 8014228: f1b8 0f46 cmp.w r8, #70 @ 0x46 801422c: d005 beq.n 801423a <__cvt+0x3e> 801422e: f1b8 0f45 cmp.w r8, #69 @ 0x45 8014232: d100 bne.n 8014236 <__cvt+0x3a> 8014234: 3601 adds r6, #1 8014236: 2302 movs r3, #2 8014238: e000 b.n 801423c <__cvt+0x40> 801423a: 2303 movs r3, #3 801423c: aa07 add r2, sp, #28 801423e: 9204 str r2, [sp, #16] 8014240: aa06 add r2, sp, #24 8014242: e9cd a202 strd sl, r2, [sp, #8] 8014246: e9cd 3600 strd r3, r6, [sp] 801424a: 4622 mov r2, r4 801424c: 462b mov r3, r5 801424e: f000 fe2b bl 8014ea8 <_dtoa_r> 8014252: f1b8 0f47 cmp.w r8, #71 @ 0x47 8014256: 4607 mov r7, r0 8014258: d119 bne.n 801428e <__cvt+0x92> 801425a: 9b11 ldr r3, [sp, #68] @ 0x44 801425c: 07db lsls r3, r3, #31 801425e: d50e bpl.n 801427e <__cvt+0x82> 8014260: eb00 0906 add.w r9, r0, r6 8014264: 2200 movs r2, #0 8014266: 2300 movs r3, #0 8014268: 4620 mov r0, r4 801426a: 4629 mov r1, r5 801426c: f7f4 fc08 bl 8008a80 <__aeabi_dcmpeq> 8014270: b108 cbz r0, 8014276 <__cvt+0x7a> 8014272: f8cd 901c str.w r9, [sp, #28] 8014276: 2230 movs r2, #48 @ 0x30 8014278: 9b07 ldr r3, [sp, #28] 801427a: 454b cmp r3, r9 801427c: d31e bcc.n 80142bc <__cvt+0xc0> 801427e: 4638 mov r0, r7 8014280: 9b07 ldr r3, [sp, #28] 8014282: 9a15 ldr r2, [sp, #84] @ 0x54 8014284: 1bdb subs r3, r3, r7 8014286: 6013 str r3, [r2, #0] 8014288: b008 add sp, #32 801428a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801428e: f1b8 0f46 cmp.w r8, #70 @ 0x46 8014292: eb00 0906 add.w r9, r0, r6 8014296: d1e5 bne.n 8014264 <__cvt+0x68> 8014298: 7803 ldrb r3, [r0, #0] 801429a: 2b30 cmp r3, #48 @ 0x30 801429c: d10a bne.n 80142b4 <__cvt+0xb8> 801429e: 2200 movs r2, #0 80142a0: 2300 movs r3, #0 80142a2: 4620 mov r0, r4 80142a4: 4629 mov r1, r5 80142a6: f7f4 fbeb bl 8008a80 <__aeabi_dcmpeq> 80142aa: b918 cbnz r0, 80142b4 <__cvt+0xb8> 80142ac: f1c6 0601 rsb r6, r6, #1 80142b0: f8ca 6000 str.w r6, [sl] 80142b4: f8da 3000 ldr.w r3, [sl] 80142b8: 4499 add r9, r3 80142ba: e7d3 b.n 8014264 <__cvt+0x68> 80142bc: 1c59 adds r1, r3, #1 80142be: 9107 str r1, [sp, #28] 80142c0: 701a strb r2, [r3, #0] 80142c2: e7d9 b.n 8014278 <__cvt+0x7c> 080142c4 <__exponent>: 80142c4: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 80142c6: 2900 cmp r1, #0 80142c8: bfb6 itet lt 80142ca: 232d movlt r3, #45 @ 0x2d 80142cc: 232b movge r3, #43 @ 0x2b 80142ce: 4249 neglt r1, r1 80142d0: 2909 cmp r1, #9 80142d2: 7002 strb r2, [r0, #0] 80142d4: 7043 strb r3, [r0, #1] 80142d6: dd29 ble.n 801432c <__exponent+0x68> 80142d8: f10d 0307 add.w r3, sp, #7 80142dc: 461d mov r5, r3 80142de: 270a movs r7, #10 80142e0: fbb1 f6f7 udiv r6, r1, r7 80142e4: 461a mov r2, r3 80142e6: fb07 1416 mls r4, r7, r6, r1 80142ea: 3430 adds r4, #48 @ 0x30 80142ec: f802 4c01 strb.w r4, [r2, #-1] 80142f0: 460c mov r4, r1 80142f2: 2c63 cmp r4, #99 @ 0x63 80142f4: 4631 mov r1, r6 80142f6: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff 80142fa: dcf1 bgt.n 80142e0 <__exponent+0x1c> 80142fc: 3130 adds r1, #48 @ 0x30 80142fe: 1e94 subs r4, r2, #2 8014300: f803 1c01 strb.w r1, [r3, #-1] 8014304: 4623 mov r3, r4 8014306: 1c41 adds r1, r0, #1 8014308: 42ab cmp r3, r5 801430a: d30a bcc.n 8014322 <__exponent+0x5e> 801430c: f10d 0309 add.w r3, sp, #9 8014310: 1a9b subs r3, r3, r2 8014312: 42ac cmp r4, r5 8014314: bf88 it hi 8014316: 2300 movhi r3, #0 8014318: 3302 adds r3, #2 801431a: 4403 add r3, r0 801431c: 1a18 subs r0, r3, r0 801431e: b003 add sp, #12 8014320: bdf0 pop {r4, r5, r6, r7, pc} 8014322: f813 6b01 ldrb.w r6, [r3], #1 8014326: f801 6f01 strb.w r6, [r1, #1]! 801432a: e7ed b.n 8014308 <__exponent+0x44> 801432c: 2330 movs r3, #48 @ 0x30 801432e: 3130 adds r1, #48 @ 0x30 8014330: 7083 strb r3, [r0, #2] 8014332: 70c1 strb r1, [r0, #3] 8014334: 1d03 adds r3, r0, #4 8014336: e7f1 b.n 801431c <__exponent+0x58> 08014338 <_printf_float>: 8014338: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801433c: b091 sub sp, #68 @ 0x44 801433e: 460c mov r4, r1 8014340: f8dd 8068 ldr.w r8, [sp, #104] @ 0x68 8014344: 4616 mov r6, r2 8014346: 461f mov r7, r3 8014348: 4605 mov r5, r0 801434a: f000 fce5 bl 8014d18 <_localeconv_r> 801434e: 6803 ldr r3, [r0, #0] 8014350: 4618 mov r0, r3 8014352: 9308 str r3, [sp, #32] 8014354: f7f3 ff68 bl 8008228 8014358: 2300 movs r3, #0 801435a: 930e str r3, [sp, #56] @ 0x38 801435c: f8d8 3000 ldr.w r3, [r8] 8014360: 9009 str r0, [sp, #36] @ 0x24 8014362: 3307 adds r3, #7 8014364: f023 0307 bic.w r3, r3, #7 8014368: f103 0208 add.w r2, r3, #8 801436c: f894 a018 ldrb.w sl, [r4, #24] 8014370: f8d4 b000 ldr.w fp, [r4] 8014374: f8c8 2000 str.w r2, [r8] 8014378: e9d3 8900 ldrd r8, r9, [r3] 801437c: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000 8014380: 930b str r3, [sp, #44] @ 0x2c 8014382: f8cd 8028 str.w r8, [sp, #40] @ 0x28 8014386: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801438a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 801438e: e9c4 8912 strd r8, r9, [r4, #72] @ 0x48 8014392: 4b9c ldr r3, [pc, #624] @ (8014604 <_printf_float+0x2cc>) 8014394: f7f4 fba6 bl 8008ae4 <__aeabi_dcmpun> 8014398: bb70 cbnz r0, 80143f8 <_printf_float+0xc0> 801439a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 801439e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80143a2: 4b98 ldr r3, [pc, #608] @ (8014604 <_printf_float+0x2cc>) 80143a4: f7f4 fb80 bl 8008aa8 <__aeabi_dcmple> 80143a8: bb30 cbnz r0, 80143f8 <_printf_float+0xc0> 80143aa: 2200 movs r2, #0 80143ac: 2300 movs r3, #0 80143ae: 4640 mov r0, r8 80143b0: 4649 mov r1, r9 80143b2: f7f4 fb6f bl 8008a94 <__aeabi_dcmplt> 80143b6: b110 cbz r0, 80143be <_printf_float+0x86> 80143b8: 232d movs r3, #45 @ 0x2d 80143ba: f884 3043 strb.w r3, [r4, #67] @ 0x43 80143be: 4a92 ldr r2, [pc, #584] @ (8014608 <_printf_float+0x2d0>) 80143c0: 4b92 ldr r3, [pc, #584] @ (801460c <_printf_float+0x2d4>) 80143c2: f1ba 0f47 cmp.w sl, #71 @ 0x47 80143c6: bf8c ite hi 80143c8: 4690 movhi r8, r2 80143ca: 4698 movls r8, r3 80143cc: 2303 movs r3, #3 80143ce: f04f 0900 mov.w r9, #0 80143d2: 6123 str r3, [r4, #16] 80143d4: f02b 0304 bic.w r3, fp, #4 80143d8: 6023 str r3, [r4, #0] 80143da: 4633 mov r3, r6 80143dc: 4621 mov r1, r4 80143de: 4628 mov r0, r5 80143e0: 9700 str r7, [sp, #0] 80143e2: aa0f add r2, sp, #60 @ 0x3c 80143e4: f000 f9d4 bl 8014790 <_printf_common> 80143e8: 3001 adds r0, #1 80143ea: f040 8090 bne.w 801450e <_printf_float+0x1d6> 80143ee: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80143f2: b011 add sp, #68 @ 0x44 80143f4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80143f8: 4642 mov r2, r8 80143fa: 464b mov r3, r9 80143fc: 4640 mov r0, r8 80143fe: 4649 mov r1, r9 8014400: f7f4 fb70 bl 8008ae4 <__aeabi_dcmpun> 8014404: b148 cbz r0, 801441a <_printf_float+0xe2> 8014406: 464b mov r3, r9 8014408: 2b00 cmp r3, #0 801440a: bfb8 it lt 801440c: 232d movlt r3, #45 @ 0x2d 801440e: 4a80 ldr r2, [pc, #512] @ (8014610 <_printf_float+0x2d8>) 8014410: bfb8 it lt 8014412: f884 3043 strblt.w r3, [r4, #67] @ 0x43 8014416: 4b7f ldr r3, [pc, #508] @ (8014614 <_printf_float+0x2dc>) 8014418: e7d3 b.n 80143c2 <_printf_float+0x8a> 801441a: 6863 ldr r3, [r4, #4] 801441c: f00a 01df and.w r1, sl, #223 @ 0xdf 8014420: 1c5a adds r2, r3, #1 8014422: d13f bne.n 80144a4 <_printf_float+0x16c> 8014424: 2306 movs r3, #6 8014426: 6063 str r3, [r4, #4] 8014428: 2200 movs r2, #0 801442a: f44b 6380 orr.w r3, fp, #1024 @ 0x400 801442e: 6023 str r3, [r4, #0] 8014430: 9206 str r2, [sp, #24] 8014432: aa0e add r2, sp, #56 @ 0x38 8014434: e9cd a204 strd sl, r2, [sp, #16] 8014438: aa0d add r2, sp, #52 @ 0x34 801443a: 9203 str r2, [sp, #12] 801443c: f10d 0233 add.w r2, sp, #51 @ 0x33 8014440: e9cd 3201 strd r3, r2, [sp, #4] 8014444: 6863 ldr r3, [r4, #4] 8014446: 4642 mov r2, r8 8014448: 9300 str r3, [sp, #0] 801444a: 4628 mov r0, r5 801444c: 464b mov r3, r9 801444e: 910a str r1, [sp, #40] @ 0x28 8014450: f7ff fed4 bl 80141fc <__cvt> 8014454: 990a ldr r1, [sp, #40] @ 0x28 8014456: 4680 mov r8, r0 8014458: 2947 cmp r1, #71 @ 0x47 801445a: 990d ldr r1, [sp, #52] @ 0x34 801445c: d128 bne.n 80144b0 <_printf_float+0x178> 801445e: 1cc8 adds r0, r1, #3 8014460: db02 blt.n 8014468 <_printf_float+0x130> 8014462: 6863 ldr r3, [r4, #4] 8014464: 4299 cmp r1, r3 8014466: dd40 ble.n 80144ea <_printf_float+0x1b2> 8014468: f1aa 0a02 sub.w sl, sl, #2 801446c: fa5f fa8a uxtb.w sl, sl 8014470: 4652 mov r2, sl 8014472: 3901 subs r1, #1 8014474: f104 0050 add.w r0, r4, #80 @ 0x50 8014478: 910d str r1, [sp, #52] @ 0x34 801447a: f7ff ff23 bl 80142c4 <__exponent> 801447e: 9a0e ldr r2, [sp, #56] @ 0x38 8014480: 4681 mov r9, r0 8014482: 1813 adds r3, r2, r0 8014484: 2a01 cmp r2, #1 8014486: 6123 str r3, [r4, #16] 8014488: dc02 bgt.n 8014490 <_printf_float+0x158> 801448a: 6822 ldr r2, [r4, #0] 801448c: 07d2 lsls r2, r2, #31 801448e: d501 bpl.n 8014494 <_printf_float+0x15c> 8014490: 3301 adds r3, #1 8014492: 6123 str r3, [r4, #16] 8014494: f89d 3033 ldrb.w r3, [sp, #51] @ 0x33 8014498: 2b00 cmp r3, #0 801449a: d09e beq.n 80143da <_printf_float+0xa2> 801449c: 232d movs r3, #45 @ 0x2d 801449e: f884 3043 strb.w r3, [r4, #67] @ 0x43 80144a2: e79a b.n 80143da <_printf_float+0xa2> 80144a4: 2947 cmp r1, #71 @ 0x47 80144a6: d1bf bne.n 8014428 <_printf_float+0xf0> 80144a8: 2b00 cmp r3, #0 80144aa: d1bd bne.n 8014428 <_printf_float+0xf0> 80144ac: 2301 movs r3, #1 80144ae: e7ba b.n 8014426 <_printf_float+0xee> 80144b0: f1ba 0f65 cmp.w sl, #101 @ 0x65 80144b4: d9dc bls.n 8014470 <_printf_float+0x138> 80144b6: f1ba 0f66 cmp.w sl, #102 @ 0x66 80144ba: d118 bne.n 80144ee <_printf_float+0x1b6> 80144bc: 2900 cmp r1, #0 80144be: 6863 ldr r3, [r4, #4] 80144c0: dd0b ble.n 80144da <_printf_float+0x1a2> 80144c2: 6121 str r1, [r4, #16] 80144c4: b913 cbnz r3, 80144cc <_printf_float+0x194> 80144c6: 6822 ldr r2, [r4, #0] 80144c8: 07d0 lsls r0, r2, #31 80144ca: d502 bpl.n 80144d2 <_printf_float+0x19a> 80144cc: 3301 adds r3, #1 80144ce: 440b add r3, r1 80144d0: 6123 str r3, [r4, #16] 80144d2: f04f 0900 mov.w r9, #0 80144d6: 65a1 str r1, [r4, #88] @ 0x58 80144d8: e7dc b.n 8014494 <_printf_float+0x15c> 80144da: b913 cbnz r3, 80144e2 <_printf_float+0x1aa> 80144dc: 6822 ldr r2, [r4, #0] 80144de: 07d2 lsls r2, r2, #31 80144e0: d501 bpl.n 80144e6 <_printf_float+0x1ae> 80144e2: 3302 adds r3, #2 80144e4: e7f4 b.n 80144d0 <_printf_float+0x198> 80144e6: 2301 movs r3, #1 80144e8: e7f2 b.n 80144d0 <_printf_float+0x198> 80144ea: f04f 0a67 mov.w sl, #103 @ 0x67 80144ee: 9b0e ldr r3, [sp, #56] @ 0x38 80144f0: 4299 cmp r1, r3 80144f2: db05 blt.n 8014500 <_printf_float+0x1c8> 80144f4: 6823 ldr r3, [r4, #0] 80144f6: 6121 str r1, [r4, #16] 80144f8: 07d8 lsls r0, r3, #31 80144fa: d5ea bpl.n 80144d2 <_printf_float+0x19a> 80144fc: 1c4b adds r3, r1, #1 80144fe: e7e7 b.n 80144d0 <_printf_float+0x198> 8014500: 2900 cmp r1, #0 8014502: bfcc ite gt 8014504: 2201 movgt r2, #1 8014506: f1c1 0202 rsble r2, r1, #2 801450a: 4413 add r3, r2 801450c: e7e0 b.n 80144d0 <_printf_float+0x198> 801450e: 6823 ldr r3, [r4, #0] 8014510: 055a lsls r2, r3, #21 8014512: d407 bmi.n 8014524 <_printf_float+0x1ec> 8014514: 6923 ldr r3, [r4, #16] 8014516: 4642 mov r2, r8 8014518: 4631 mov r1, r6 801451a: 4628 mov r0, r5 801451c: 47b8 blx r7 801451e: 3001 adds r0, #1 8014520: d12b bne.n 801457a <_printf_float+0x242> 8014522: e764 b.n 80143ee <_printf_float+0xb6> 8014524: f1ba 0f65 cmp.w sl, #101 @ 0x65 8014528: f240 80dc bls.w 80146e4 <_printf_float+0x3ac> 801452c: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 8014530: 2200 movs r2, #0 8014532: 2300 movs r3, #0 8014534: f7f4 faa4 bl 8008a80 <__aeabi_dcmpeq> 8014538: 2800 cmp r0, #0 801453a: d033 beq.n 80145a4 <_printf_float+0x26c> 801453c: 2301 movs r3, #1 801453e: 4631 mov r1, r6 8014540: 4628 mov r0, r5 8014542: 4a35 ldr r2, [pc, #212] @ (8014618 <_printf_float+0x2e0>) 8014544: 47b8 blx r7 8014546: 3001 adds r0, #1 8014548: f43f af51 beq.w 80143ee <_printf_float+0xb6> 801454c: e9dd 380d ldrd r3, r8, [sp, #52] @ 0x34 8014550: 4543 cmp r3, r8 8014552: db02 blt.n 801455a <_printf_float+0x222> 8014554: 6823 ldr r3, [r4, #0] 8014556: 07d8 lsls r0, r3, #31 8014558: d50f bpl.n 801457a <_printf_float+0x242> 801455a: e9dd 2308 ldrd r2, r3, [sp, #32] 801455e: 4631 mov r1, r6 8014560: 4628 mov r0, r5 8014562: 47b8 blx r7 8014564: 3001 adds r0, #1 8014566: f43f af42 beq.w 80143ee <_printf_float+0xb6> 801456a: f04f 0900 mov.w r9, #0 801456e: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 8014572: f104 0a1a add.w sl, r4, #26 8014576: 45c8 cmp r8, r9 8014578: dc09 bgt.n 801458e <_printf_float+0x256> 801457a: 6823 ldr r3, [r4, #0] 801457c: 079b lsls r3, r3, #30 801457e: f100 8102 bmi.w 8014786 <_printf_float+0x44e> 8014582: 68e0 ldr r0, [r4, #12] 8014584: 9b0f ldr r3, [sp, #60] @ 0x3c 8014586: 4298 cmp r0, r3 8014588: bfb8 it lt 801458a: 4618 movlt r0, r3 801458c: e731 b.n 80143f2 <_printf_float+0xba> 801458e: 2301 movs r3, #1 8014590: 4652 mov r2, sl 8014592: 4631 mov r1, r6 8014594: 4628 mov r0, r5 8014596: 47b8 blx r7 8014598: 3001 adds r0, #1 801459a: f43f af28 beq.w 80143ee <_printf_float+0xb6> 801459e: f109 0901 add.w r9, r9, #1 80145a2: e7e8 b.n 8014576 <_printf_float+0x23e> 80145a4: 9b0d ldr r3, [sp, #52] @ 0x34 80145a6: 2b00 cmp r3, #0 80145a8: dc38 bgt.n 801461c <_printf_float+0x2e4> 80145aa: 2301 movs r3, #1 80145ac: 4631 mov r1, r6 80145ae: 4628 mov r0, r5 80145b0: 4a19 ldr r2, [pc, #100] @ (8014618 <_printf_float+0x2e0>) 80145b2: 47b8 blx r7 80145b4: 3001 adds r0, #1 80145b6: f43f af1a beq.w 80143ee <_printf_float+0xb6> 80145ba: e9dd 390d ldrd r3, r9, [sp, #52] @ 0x34 80145be: ea59 0303 orrs.w r3, r9, r3 80145c2: d102 bne.n 80145ca <_printf_float+0x292> 80145c4: 6823 ldr r3, [r4, #0] 80145c6: 07d9 lsls r1, r3, #31 80145c8: d5d7 bpl.n 801457a <_printf_float+0x242> 80145ca: e9dd 2308 ldrd r2, r3, [sp, #32] 80145ce: 4631 mov r1, r6 80145d0: 4628 mov r0, r5 80145d2: 47b8 blx r7 80145d4: 3001 adds r0, #1 80145d6: f43f af0a beq.w 80143ee <_printf_float+0xb6> 80145da: f04f 0a00 mov.w sl, #0 80145de: f104 0b1a add.w fp, r4, #26 80145e2: 9b0d ldr r3, [sp, #52] @ 0x34 80145e4: 425b negs r3, r3 80145e6: 4553 cmp r3, sl 80145e8: dc01 bgt.n 80145ee <_printf_float+0x2b6> 80145ea: 464b mov r3, r9 80145ec: e793 b.n 8014516 <_printf_float+0x1de> 80145ee: 2301 movs r3, #1 80145f0: 465a mov r2, fp 80145f2: 4631 mov r1, r6 80145f4: 4628 mov r0, r5 80145f6: 47b8 blx r7 80145f8: 3001 adds r0, #1 80145fa: f43f aef8 beq.w 80143ee <_printf_float+0xb6> 80145fe: f10a 0a01 add.w sl, sl, #1 8014602: e7ee b.n 80145e2 <_printf_float+0x2aa> 8014604: 7fefffff .word 0x7fefffff 8014608: 08017958 .word 0x08017958 801460c: 08017954 .word 0x08017954 8014610: 08017960 .word 0x08017960 8014614: 0801795c .word 0x0801795c 8014618: 08017964 .word 0x08017964 801461c: 6da3 ldr r3, [r4, #88] @ 0x58 801461e: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 8014622: 4553 cmp r3, sl 8014624: bfa8 it ge 8014626: 4653 movge r3, sl 8014628: 2b00 cmp r3, #0 801462a: 4699 mov r9, r3 801462c: dc36 bgt.n 801469c <_printf_float+0x364> 801462e: f04f 0b00 mov.w fp, #0 8014632: ea29 79e9 bic.w r9, r9, r9, asr #31 8014636: f104 021a add.w r2, r4, #26 801463a: 6da3 ldr r3, [r4, #88] @ 0x58 801463c: 930a str r3, [sp, #40] @ 0x28 801463e: eba3 0309 sub.w r3, r3, r9 8014642: 455b cmp r3, fp 8014644: dc31 bgt.n 80146aa <_printf_float+0x372> 8014646: 9b0d ldr r3, [sp, #52] @ 0x34 8014648: 459a cmp sl, r3 801464a: dc3a bgt.n 80146c2 <_printf_float+0x38a> 801464c: 6823 ldr r3, [r4, #0] 801464e: 07da lsls r2, r3, #31 8014650: d437 bmi.n 80146c2 <_printf_float+0x38a> 8014652: 9b0d ldr r3, [sp, #52] @ 0x34 8014654: ebaa 0903 sub.w r9, sl, r3 8014658: 9b0a ldr r3, [sp, #40] @ 0x28 801465a: ebaa 0303 sub.w r3, sl, r3 801465e: 4599 cmp r9, r3 8014660: bfa8 it ge 8014662: 4699 movge r9, r3 8014664: f1b9 0f00 cmp.w r9, #0 8014668: dc33 bgt.n 80146d2 <_printf_float+0x39a> 801466a: f04f 0800 mov.w r8, #0 801466e: ea29 79e9 bic.w r9, r9, r9, asr #31 8014672: f104 0b1a add.w fp, r4, #26 8014676: 9b0d ldr r3, [sp, #52] @ 0x34 8014678: ebaa 0303 sub.w r3, sl, r3 801467c: eba3 0309 sub.w r3, r3, r9 8014680: 4543 cmp r3, r8 8014682: f77f af7a ble.w 801457a <_printf_float+0x242> 8014686: 2301 movs r3, #1 8014688: 465a mov r2, fp 801468a: 4631 mov r1, r6 801468c: 4628 mov r0, r5 801468e: 47b8 blx r7 8014690: 3001 adds r0, #1 8014692: f43f aeac beq.w 80143ee <_printf_float+0xb6> 8014696: f108 0801 add.w r8, r8, #1 801469a: e7ec b.n 8014676 <_printf_float+0x33e> 801469c: 4642 mov r2, r8 801469e: 4631 mov r1, r6 80146a0: 4628 mov r0, r5 80146a2: 47b8 blx r7 80146a4: 3001 adds r0, #1 80146a6: d1c2 bne.n 801462e <_printf_float+0x2f6> 80146a8: e6a1 b.n 80143ee <_printf_float+0xb6> 80146aa: 2301 movs r3, #1 80146ac: 4631 mov r1, r6 80146ae: 4628 mov r0, r5 80146b0: 920a str r2, [sp, #40] @ 0x28 80146b2: 47b8 blx r7 80146b4: 3001 adds r0, #1 80146b6: f43f ae9a beq.w 80143ee <_printf_float+0xb6> 80146ba: 9a0a ldr r2, [sp, #40] @ 0x28 80146bc: f10b 0b01 add.w fp, fp, #1 80146c0: e7bb b.n 801463a <_printf_float+0x302> 80146c2: 4631 mov r1, r6 80146c4: e9dd 2308 ldrd r2, r3, [sp, #32] 80146c8: 4628 mov r0, r5 80146ca: 47b8 blx r7 80146cc: 3001 adds r0, #1 80146ce: d1c0 bne.n 8014652 <_printf_float+0x31a> 80146d0: e68d b.n 80143ee <_printf_float+0xb6> 80146d2: 9a0a ldr r2, [sp, #40] @ 0x28 80146d4: 464b mov r3, r9 80146d6: 4631 mov r1, r6 80146d8: 4628 mov r0, r5 80146da: 4442 add r2, r8 80146dc: 47b8 blx r7 80146de: 3001 adds r0, #1 80146e0: d1c3 bne.n 801466a <_printf_float+0x332> 80146e2: e684 b.n 80143ee <_printf_float+0xb6> 80146e4: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 80146e8: f1ba 0f01 cmp.w sl, #1 80146ec: dc01 bgt.n 80146f2 <_printf_float+0x3ba> 80146ee: 07db lsls r3, r3, #31 80146f0: d536 bpl.n 8014760 <_printf_float+0x428> 80146f2: 2301 movs r3, #1 80146f4: 4642 mov r2, r8 80146f6: 4631 mov r1, r6 80146f8: 4628 mov r0, r5 80146fa: 47b8 blx r7 80146fc: 3001 adds r0, #1 80146fe: f43f ae76 beq.w 80143ee <_printf_float+0xb6> 8014702: e9dd 2308 ldrd r2, r3, [sp, #32] 8014706: 4631 mov r1, r6 8014708: 4628 mov r0, r5 801470a: 47b8 blx r7 801470c: 3001 adds r0, #1 801470e: f43f ae6e beq.w 80143ee <_printf_float+0xb6> 8014712: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 8014716: 2200 movs r2, #0 8014718: 2300 movs r3, #0 801471a: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff 801471e: f7f4 f9af bl 8008a80 <__aeabi_dcmpeq> 8014722: b9c0 cbnz r0, 8014756 <_printf_float+0x41e> 8014724: 4653 mov r3, sl 8014726: f108 0201 add.w r2, r8, #1 801472a: 4631 mov r1, r6 801472c: 4628 mov r0, r5 801472e: 47b8 blx r7 8014730: 3001 adds r0, #1 8014732: d10c bne.n 801474e <_printf_float+0x416> 8014734: e65b b.n 80143ee <_printf_float+0xb6> 8014736: 2301 movs r3, #1 8014738: 465a mov r2, fp 801473a: 4631 mov r1, r6 801473c: 4628 mov r0, r5 801473e: 47b8 blx r7 8014740: 3001 adds r0, #1 8014742: f43f ae54 beq.w 80143ee <_printf_float+0xb6> 8014746: f108 0801 add.w r8, r8, #1 801474a: 45d0 cmp r8, sl 801474c: dbf3 blt.n 8014736 <_printf_float+0x3fe> 801474e: 464b mov r3, r9 8014750: f104 0250 add.w r2, r4, #80 @ 0x50 8014754: e6e0 b.n 8014518 <_printf_float+0x1e0> 8014756: f04f 0800 mov.w r8, #0 801475a: f104 0b1a add.w fp, r4, #26 801475e: e7f4 b.n 801474a <_printf_float+0x412> 8014760: 2301 movs r3, #1 8014762: 4642 mov r2, r8 8014764: e7e1 b.n 801472a <_printf_float+0x3f2> 8014766: 2301 movs r3, #1 8014768: 464a mov r2, r9 801476a: 4631 mov r1, r6 801476c: 4628 mov r0, r5 801476e: 47b8 blx r7 8014770: 3001 adds r0, #1 8014772: f43f ae3c beq.w 80143ee <_printf_float+0xb6> 8014776: f108 0801 add.w r8, r8, #1 801477a: 68e3 ldr r3, [r4, #12] 801477c: 990f ldr r1, [sp, #60] @ 0x3c 801477e: 1a5b subs r3, r3, r1 8014780: 4543 cmp r3, r8 8014782: dcf0 bgt.n 8014766 <_printf_float+0x42e> 8014784: e6fd b.n 8014582 <_printf_float+0x24a> 8014786: f04f 0800 mov.w r8, #0 801478a: f104 0919 add.w r9, r4, #25 801478e: e7f4 b.n 801477a <_printf_float+0x442> 08014790 <_printf_common>: 8014790: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8014794: 4616 mov r6, r2 8014796: 4698 mov r8, r3 8014798: 688a ldr r2, [r1, #8] 801479a: 690b ldr r3, [r1, #16] 801479c: 4607 mov r7, r0 801479e: 4293 cmp r3, r2 80147a0: bfb8 it lt 80147a2: 4613 movlt r3, r2 80147a4: 6033 str r3, [r6, #0] 80147a6: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 80147aa: 460c mov r4, r1 80147ac: f8dd 9020 ldr.w r9, [sp, #32] 80147b0: b10a cbz r2, 80147b6 <_printf_common+0x26> 80147b2: 3301 adds r3, #1 80147b4: 6033 str r3, [r6, #0] 80147b6: 6823 ldr r3, [r4, #0] 80147b8: 0699 lsls r1, r3, #26 80147ba: bf42 ittt mi 80147bc: 6833 ldrmi r3, [r6, #0] 80147be: 3302 addmi r3, #2 80147c0: 6033 strmi r3, [r6, #0] 80147c2: 6825 ldr r5, [r4, #0] 80147c4: f015 0506 ands.w r5, r5, #6 80147c8: d106 bne.n 80147d8 <_printf_common+0x48> 80147ca: f104 0a19 add.w sl, r4, #25 80147ce: 68e3 ldr r3, [r4, #12] 80147d0: 6832 ldr r2, [r6, #0] 80147d2: 1a9b subs r3, r3, r2 80147d4: 42ab cmp r3, r5 80147d6: dc2b bgt.n 8014830 <_printf_common+0xa0> 80147d8: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 80147dc: 6822 ldr r2, [r4, #0] 80147de: 3b00 subs r3, #0 80147e0: bf18 it ne 80147e2: 2301 movne r3, #1 80147e4: 0692 lsls r2, r2, #26 80147e6: d430 bmi.n 801484a <_printf_common+0xba> 80147e8: 4641 mov r1, r8 80147ea: 4638 mov r0, r7 80147ec: f104 0243 add.w r2, r4, #67 @ 0x43 80147f0: 47c8 blx r9 80147f2: 3001 adds r0, #1 80147f4: d023 beq.n 801483e <_printf_common+0xae> 80147f6: 6823 ldr r3, [r4, #0] 80147f8: 6922 ldr r2, [r4, #16] 80147fa: f003 0306 and.w r3, r3, #6 80147fe: 2b04 cmp r3, #4 8014800: bf14 ite ne 8014802: 2500 movne r5, #0 8014804: 6833 ldreq r3, [r6, #0] 8014806: f04f 0600 mov.w r6, #0 801480a: bf08 it eq 801480c: 68e5 ldreq r5, [r4, #12] 801480e: f104 041a add.w r4, r4, #26 8014812: bf08 it eq 8014814: 1aed subeq r5, r5, r3 8014816: f854 3c12 ldr.w r3, [r4, #-18] 801481a: bf08 it eq 801481c: ea25 75e5 biceq.w r5, r5, r5, asr #31 8014820: 4293 cmp r3, r2 8014822: bfc4 itt gt 8014824: 1a9b subgt r3, r3, r2 8014826: 18ed addgt r5, r5, r3 8014828: 42b5 cmp r5, r6 801482a: d11a bne.n 8014862 <_printf_common+0xd2> 801482c: 2000 movs r0, #0 801482e: e008 b.n 8014842 <_printf_common+0xb2> 8014830: 2301 movs r3, #1 8014832: 4652 mov r2, sl 8014834: 4641 mov r1, r8 8014836: 4638 mov r0, r7 8014838: 47c8 blx r9 801483a: 3001 adds r0, #1 801483c: d103 bne.n 8014846 <_printf_common+0xb6> 801483e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8014842: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8014846: 3501 adds r5, #1 8014848: e7c1 b.n 80147ce <_printf_common+0x3e> 801484a: 2030 movs r0, #48 @ 0x30 801484c: 18e1 adds r1, r4, r3 801484e: f881 0043 strb.w r0, [r1, #67] @ 0x43 8014852: 1c5a adds r2, r3, #1 8014854: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 8014858: 4422 add r2, r4 801485a: 3302 adds r3, #2 801485c: f882 1043 strb.w r1, [r2, #67] @ 0x43 8014860: e7c2 b.n 80147e8 <_printf_common+0x58> 8014862: 2301 movs r3, #1 8014864: 4622 mov r2, r4 8014866: 4641 mov r1, r8 8014868: 4638 mov r0, r7 801486a: 47c8 blx r9 801486c: 3001 adds r0, #1 801486e: d0e6 beq.n 801483e <_printf_common+0xae> 8014870: 3601 adds r6, #1 8014872: e7d9 b.n 8014828 <_printf_common+0x98> 08014874 <_printf_i>: 8014874: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8014878: 7e0f ldrb r7, [r1, #24] 801487a: 4691 mov r9, r2 801487c: 2f78 cmp r7, #120 @ 0x78 801487e: 4680 mov r8, r0 8014880: 460c mov r4, r1 8014882: 469a mov sl, r3 8014884: 9e0c ldr r6, [sp, #48] @ 0x30 8014886: f101 0243 add.w r2, r1, #67 @ 0x43 801488a: d807 bhi.n 801489c <_printf_i+0x28> 801488c: 2f62 cmp r7, #98 @ 0x62 801488e: d80a bhi.n 80148a6 <_printf_i+0x32> 8014890: 2f00 cmp r7, #0 8014892: f000 80d1 beq.w 8014a38 <_printf_i+0x1c4> 8014896: 2f58 cmp r7, #88 @ 0x58 8014898: f000 80b8 beq.w 8014a0c <_printf_i+0x198> 801489c: f104 0642 add.w r6, r4, #66 @ 0x42 80148a0: f884 7042 strb.w r7, [r4, #66] @ 0x42 80148a4: e03a b.n 801491c <_printf_i+0xa8> 80148a6: f1a7 0363 sub.w r3, r7, #99 @ 0x63 80148aa: 2b15 cmp r3, #21 80148ac: d8f6 bhi.n 801489c <_printf_i+0x28> 80148ae: a101 add r1, pc, #4 @ (adr r1, 80148b4 <_printf_i+0x40>) 80148b0: f851 f023 ldr.w pc, [r1, r3, lsl #2] 80148b4: 0801490d .word 0x0801490d 80148b8: 08014921 .word 0x08014921 80148bc: 0801489d .word 0x0801489d 80148c0: 0801489d .word 0x0801489d 80148c4: 0801489d .word 0x0801489d 80148c8: 0801489d .word 0x0801489d 80148cc: 08014921 .word 0x08014921 80148d0: 0801489d .word 0x0801489d 80148d4: 0801489d .word 0x0801489d 80148d8: 0801489d .word 0x0801489d 80148dc: 0801489d .word 0x0801489d 80148e0: 08014a1f .word 0x08014a1f 80148e4: 0801494b .word 0x0801494b 80148e8: 080149d9 .word 0x080149d9 80148ec: 0801489d .word 0x0801489d 80148f0: 0801489d .word 0x0801489d 80148f4: 08014a41 .word 0x08014a41 80148f8: 0801489d .word 0x0801489d 80148fc: 0801494b .word 0x0801494b 8014900: 0801489d .word 0x0801489d 8014904: 0801489d .word 0x0801489d 8014908: 080149e1 .word 0x080149e1 801490c: 6833 ldr r3, [r6, #0] 801490e: 1d1a adds r2, r3, #4 8014910: 681b ldr r3, [r3, #0] 8014912: 6032 str r2, [r6, #0] 8014914: f104 0642 add.w r6, r4, #66 @ 0x42 8014918: f884 3042 strb.w r3, [r4, #66] @ 0x42 801491c: 2301 movs r3, #1 801491e: e09c b.n 8014a5a <_printf_i+0x1e6> 8014920: 6833 ldr r3, [r6, #0] 8014922: 6820 ldr r0, [r4, #0] 8014924: 1d19 adds r1, r3, #4 8014926: 6031 str r1, [r6, #0] 8014928: 0606 lsls r6, r0, #24 801492a: d501 bpl.n 8014930 <_printf_i+0xbc> 801492c: 681d ldr r5, [r3, #0] 801492e: e003 b.n 8014938 <_printf_i+0xc4> 8014930: 0645 lsls r5, r0, #25 8014932: d5fb bpl.n 801492c <_printf_i+0xb8> 8014934: f9b3 5000 ldrsh.w r5, [r3] 8014938: 2d00 cmp r5, #0 801493a: da03 bge.n 8014944 <_printf_i+0xd0> 801493c: 232d movs r3, #45 @ 0x2d 801493e: 426d negs r5, r5 8014940: f884 3043 strb.w r3, [r4, #67] @ 0x43 8014944: 230a movs r3, #10 8014946: 4858 ldr r0, [pc, #352] @ (8014aa8 <_printf_i+0x234>) 8014948: e011 b.n 801496e <_printf_i+0xfa> 801494a: 6821 ldr r1, [r4, #0] 801494c: 6833 ldr r3, [r6, #0] 801494e: 0608 lsls r0, r1, #24 8014950: f853 5b04 ldr.w r5, [r3], #4 8014954: d402 bmi.n 801495c <_printf_i+0xe8> 8014956: 0649 lsls r1, r1, #25 8014958: bf48 it mi 801495a: b2ad uxthmi r5, r5 801495c: 2f6f cmp r7, #111 @ 0x6f 801495e: 6033 str r3, [r6, #0] 8014960: bf14 ite ne 8014962: 230a movne r3, #10 8014964: 2308 moveq r3, #8 8014966: 4850 ldr r0, [pc, #320] @ (8014aa8 <_printf_i+0x234>) 8014968: 2100 movs r1, #0 801496a: f884 1043 strb.w r1, [r4, #67] @ 0x43 801496e: 6866 ldr r6, [r4, #4] 8014970: 2e00 cmp r6, #0 8014972: 60a6 str r6, [r4, #8] 8014974: db05 blt.n 8014982 <_printf_i+0x10e> 8014976: 6821 ldr r1, [r4, #0] 8014978: 432e orrs r6, r5 801497a: f021 0104 bic.w r1, r1, #4 801497e: 6021 str r1, [r4, #0] 8014980: d04b beq.n 8014a1a <_printf_i+0x1a6> 8014982: 4616 mov r6, r2 8014984: fbb5 f1f3 udiv r1, r5, r3 8014988: fb03 5711 mls r7, r3, r1, r5 801498c: 5dc7 ldrb r7, [r0, r7] 801498e: f806 7d01 strb.w r7, [r6, #-1]! 8014992: 462f mov r7, r5 8014994: 42bb cmp r3, r7 8014996: 460d mov r5, r1 8014998: d9f4 bls.n 8014984 <_printf_i+0x110> 801499a: 2b08 cmp r3, #8 801499c: d10b bne.n 80149b6 <_printf_i+0x142> 801499e: 6823 ldr r3, [r4, #0] 80149a0: 07df lsls r7, r3, #31 80149a2: d508 bpl.n 80149b6 <_printf_i+0x142> 80149a4: 6923 ldr r3, [r4, #16] 80149a6: 6861 ldr r1, [r4, #4] 80149a8: 4299 cmp r1, r3 80149aa: bfde ittt le 80149ac: 2330 movle r3, #48 @ 0x30 80149ae: f806 3c01 strble.w r3, [r6, #-1] 80149b2: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 80149b6: 1b92 subs r2, r2, r6 80149b8: 6122 str r2, [r4, #16] 80149ba: 464b mov r3, r9 80149bc: 4621 mov r1, r4 80149be: 4640 mov r0, r8 80149c0: f8cd a000 str.w sl, [sp] 80149c4: aa03 add r2, sp, #12 80149c6: f7ff fee3 bl 8014790 <_printf_common> 80149ca: 3001 adds r0, #1 80149cc: d14a bne.n 8014a64 <_printf_i+0x1f0> 80149ce: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80149d2: b004 add sp, #16 80149d4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80149d8: 6823 ldr r3, [r4, #0] 80149da: f043 0320 orr.w r3, r3, #32 80149de: 6023 str r3, [r4, #0] 80149e0: 2778 movs r7, #120 @ 0x78 80149e2: 4832 ldr r0, [pc, #200] @ (8014aac <_printf_i+0x238>) 80149e4: f884 7045 strb.w r7, [r4, #69] @ 0x45 80149e8: 6823 ldr r3, [r4, #0] 80149ea: 6831 ldr r1, [r6, #0] 80149ec: 061f lsls r7, r3, #24 80149ee: f851 5b04 ldr.w r5, [r1], #4 80149f2: d402 bmi.n 80149fa <_printf_i+0x186> 80149f4: 065f lsls r7, r3, #25 80149f6: bf48 it mi 80149f8: b2ad uxthmi r5, r5 80149fa: 6031 str r1, [r6, #0] 80149fc: 07d9 lsls r1, r3, #31 80149fe: bf44 itt mi 8014a00: f043 0320 orrmi.w r3, r3, #32 8014a04: 6023 strmi r3, [r4, #0] 8014a06: b11d cbz r5, 8014a10 <_printf_i+0x19c> 8014a08: 2310 movs r3, #16 8014a0a: e7ad b.n 8014968 <_printf_i+0xf4> 8014a0c: 4826 ldr r0, [pc, #152] @ (8014aa8 <_printf_i+0x234>) 8014a0e: e7e9 b.n 80149e4 <_printf_i+0x170> 8014a10: 6823 ldr r3, [r4, #0] 8014a12: f023 0320 bic.w r3, r3, #32 8014a16: 6023 str r3, [r4, #0] 8014a18: e7f6 b.n 8014a08 <_printf_i+0x194> 8014a1a: 4616 mov r6, r2 8014a1c: e7bd b.n 801499a <_printf_i+0x126> 8014a1e: 6833 ldr r3, [r6, #0] 8014a20: 6825 ldr r5, [r4, #0] 8014a22: 1d18 adds r0, r3, #4 8014a24: 6961 ldr r1, [r4, #20] 8014a26: 6030 str r0, [r6, #0] 8014a28: 062e lsls r6, r5, #24 8014a2a: 681b ldr r3, [r3, #0] 8014a2c: d501 bpl.n 8014a32 <_printf_i+0x1be> 8014a2e: 6019 str r1, [r3, #0] 8014a30: e002 b.n 8014a38 <_printf_i+0x1c4> 8014a32: 0668 lsls r0, r5, #25 8014a34: d5fb bpl.n 8014a2e <_printf_i+0x1ba> 8014a36: 8019 strh r1, [r3, #0] 8014a38: 2300 movs r3, #0 8014a3a: 4616 mov r6, r2 8014a3c: 6123 str r3, [r4, #16] 8014a3e: e7bc b.n 80149ba <_printf_i+0x146> 8014a40: 6833 ldr r3, [r6, #0] 8014a42: 2100 movs r1, #0 8014a44: 1d1a adds r2, r3, #4 8014a46: 6032 str r2, [r6, #0] 8014a48: 681e ldr r6, [r3, #0] 8014a4a: 6862 ldr r2, [r4, #4] 8014a4c: 4630 mov r0, r6 8014a4e: f000 f967 bl 8014d20 8014a52: b108 cbz r0, 8014a58 <_printf_i+0x1e4> 8014a54: 1b80 subs r0, r0, r6 8014a56: 6060 str r0, [r4, #4] 8014a58: 6863 ldr r3, [r4, #4] 8014a5a: 6123 str r3, [r4, #16] 8014a5c: 2300 movs r3, #0 8014a5e: f884 3043 strb.w r3, [r4, #67] @ 0x43 8014a62: e7aa b.n 80149ba <_printf_i+0x146> 8014a64: 4632 mov r2, r6 8014a66: 4649 mov r1, r9 8014a68: 4640 mov r0, r8 8014a6a: 6923 ldr r3, [r4, #16] 8014a6c: 47d0 blx sl 8014a6e: 3001 adds r0, #1 8014a70: d0ad beq.n 80149ce <_printf_i+0x15a> 8014a72: 6823 ldr r3, [r4, #0] 8014a74: 079b lsls r3, r3, #30 8014a76: d413 bmi.n 8014aa0 <_printf_i+0x22c> 8014a78: 68e0 ldr r0, [r4, #12] 8014a7a: 9b03 ldr r3, [sp, #12] 8014a7c: 4298 cmp r0, r3 8014a7e: bfb8 it lt 8014a80: 4618 movlt r0, r3 8014a82: e7a6 b.n 80149d2 <_printf_i+0x15e> 8014a84: 2301 movs r3, #1 8014a86: 4632 mov r2, r6 8014a88: 4649 mov r1, r9 8014a8a: 4640 mov r0, r8 8014a8c: 47d0 blx sl 8014a8e: 3001 adds r0, #1 8014a90: d09d beq.n 80149ce <_printf_i+0x15a> 8014a92: 3501 adds r5, #1 8014a94: 68e3 ldr r3, [r4, #12] 8014a96: 9903 ldr r1, [sp, #12] 8014a98: 1a5b subs r3, r3, r1 8014a9a: 42ab cmp r3, r5 8014a9c: dcf2 bgt.n 8014a84 <_printf_i+0x210> 8014a9e: e7eb b.n 8014a78 <_printf_i+0x204> 8014aa0: 2500 movs r5, #0 8014aa2: f104 0619 add.w r6, r4, #25 8014aa6: e7f5 b.n 8014a94 <_printf_i+0x220> 8014aa8: 08017966 .word 0x08017966 8014aac: 08017977 .word 0x08017977 08014ab0 : 8014ab0: 2300 movs r3, #0 8014ab2: b510 push {r4, lr} 8014ab4: 4604 mov r4, r0 8014ab6: e9c0 3300 strd r3, r3, [r0] 8014aba: e9c0 3304 strd r3, r3, [r0, #16] 8014abe: 6083 str r3, [r0, #8] 8014ac0: 8181 strh r1, [r0, #12] 8014ac2: 6643 str r3, [r0, #100] @ 0x64 8014ac4: 81c2 strh r2, [r0, #14] 8014ac6: 6183 str r3, [r0, #24] 8014ac8: 4619 mov r1, r3 8014aca: 2208 movs r2, #8 8014acc: 305c adds r0, #92 @ 0x5c 8014ace: f000 f8ed bl 8014cac 8014ad2: 4b0d ldr r3, [pc, #52] @ (8014b08 ) 8014ad4: 6224 str r4, [r4, #32] 8014ad6: 6263 str r3, [r4, #36] @ 0x24 8014ad8: 4b0c ldr r3, [pc, #48] @ (8014b0c ) 8014ada: 62a3 str r3, [r4, #40] @ 0x28 8014adc: 4b0c ldr r3, [pc, #48] @ (8014b10 ) 8014ade: 62e3 str r3, [r4, #44] @ 0x2c 8014ae0: 4b0c ldr r3, [pc, #48] @ (8014b14 ) 8014ae2: 6323 str r3, [r4, #48] @ 0x30 8014ae4: 4b0c ldr r3, [pc, #48] @ (8014b18 ) 8014ae6: 429c cmp r4, r3 8014ae8: d006 beq.n 8014af8 8014aea: f103 0268 add.w r2, r3, #104 @ 0x68 8014aee: 4294 cmp r4, r2 8014af0: d002 beq.n 8014af8 8014af2: 33d0 adds r3, #208 @ 0xd0 8014af4: 429c cmp r4, r3 8014af6: d105 bne.n 8014b04 8014af8: f104 0058 add.w r0, r4, #88 @ 0x58 8014afc: e8bd 4010 ldmia.w sp!, {r4, lr} 8014b00: f000 b906 b.w 8014d10 <__retarget_lock_init_recursive> 8014b04: bd10 pop {r4, pc} 8014b06: bf00 nop 8014b08: 080166b1 .word 0x080166b1 8014b0c: 080166d3 .word 0x080166d3 8014b10: 0801670b .word 0x0801670b 8014b14: 0801672f .word 0x0801672f 8014b18: 2000148c .word 0x2000148c 08014b1c : 8014b1c: 4a02 ldr r2, [pc, #8] @ (8014b28 ) 8014b1e: 4903 ldr r1, [pc, #12] @ (8014b2c ) 8014b20: 4803 ldr r0, [pc, #12] @ (8014b30 ) 8014b22: f000 b8a5 b.w 8014c70 <_fwalk_sglue> 8014b26: bf00 nop 8014b28: 20000090 .word 0x20000090 8014b2c: 08015f55 .word 0x08015f55 8014b30: 200000a0 .word 0x200000a0 08014b34 : 8014b34: 6841 ldr r1, [r0, #4] 8014b36: 4b0c ldr r3, [pc, #48] @ (8014b68 ) 8014b38: b510 push {r4, lr} 8014b3a: 4299 cmp r1, r3 8014b3c: 4604 mov r4, r0 8014b3e: d001 beq.n 8014b44 8014b40: f001 fa08 bl 8015f54 <_fflush_r> 8014b44: 68a1 ldr r1, [r4, #8] 8014b46: 4b09 ldr r3, [pc, #36] @ (8014b6c ) 8014b48: 4299 cmp r1, r3 8014b4a: d002 beq.n 8014b52 8014b4c: 4620 mov r0, r4 8014b4e: f001 fa01 bl 8015f54 <_fflush_r> 8014b52: 68e1 ldr r1, [r4, #12] 8014b54: 4b06 ldr r3, [pc, #24] @ (8014b70 ) 8014b56: 4299 cmp r1, r3 8014b58: d004 beq.n 8014b64 8014b5a: 4620 mov r0, r4 8014b5c: e8bd 4010 ldmia.w sp!, {r4, lr} 8014b60: f001 b9f8 b.w 8015f54 <_fflush_r> 8014b64: bd10 pop {r4, pc} 8014b66: bf00 nop 8014b68: 2000148c .word 0x2000148c 8014b6c: 200014f4 .word 0x200014f4 8014b70: 2000155c .word 0x2000155c 08014b74 : 8014b74: b510 push {r4, lr} 8014b76: 4b0b ldr r3, [pc, #44] @ (8014ba4 ) 8014b78: 4c0b ldr r4, [pc, #44] @ (8014ba8 ) 8014b7a: 4a0c ldr r2, [pc, #48] @ (8014bac ) 8014b7c: 4620 mov r0, r4 8014b7e: 601a str r2, [r3, #0] 8014b80: 2104 movs r1, #4 8014b82: 2200 movs r2, #0 8014b84: f7ff ff94 bl 8014ab0 8014b88: f104 0068 add.w r0, r4, #104 @ 0x68 8014b8c: 2201 movs r2, #1 8014b8e: 2109 movs r1, #9 8014b90: f7ff ff8e bl 8014ab0 8014b94: f104 00d0 add.w r0, r4, #208 @ 0xd0 8014b98: 2202 movs r2, #2 8014b9a: e8bd 4010 ldmia.w sp!, {r4, lr} 8014b9e: 2112 movs r1, #18 8014ba0: f7ff bf86 b.w 8014ab0 8014ba4: 200015c4 .word 0x200015c4 8014ba8: 2000148c .word 0x2000148c 8014bac: 08014b1d .word 0x08014b1d 08014bb0 <__sfp_lock_acquire>: 8014bb0: 4801 ldr r0, [pc, #4] @ (8014bb8 <__sfp_lock_acquire+0x8>) 8014bb2: f000 b8ae b.w 8014d12 <__retarget_lock_acquire_recursive> 8014bb6: bf00 nop 8014bb8: 200015c9 .word 0x200015c9 08014bbc <__sfp_lock_release>: 8014bbc: 4801 ldr r0, [pc, #4] @ (8014bc4 <__sfp_lock_release+0x8>) 8014bbe: f000 b8a9 b.w 8014d14 <__retarget_lock_release_recursive> 8014bc2: bf00 nop 8014bc4: 200015c9 .word 0x200015c9 08014bc8 <__sinit>: 8014bc8: b510 push {r4, lr} 8014bca: 4604 mov r4, r0 8014bcc: f7ff fff0 bl 8014bb0 <__sfp_lock_acquire> 8014bd0: 6a23 ldr r3, [r4, #32] 8014bd2: b11b cbz r3, 8014bdc <__sinit+0x14> 8014bd4: e8bd 4010 ldmia.w sp!, {r4, lr} 8014bd8: f7ff bff0 b.w 8014bbc <__sfp_lock_release> 8014bdc: 4b04 ldr r3, [pc, #16] @ (8014bf0 <__sinit+0x28>) 8014bde: 6223 str r3, [r4, #32] 8014be0: 4b04 ldr r3, [pc, #16] @ (8014bf4 <__sinit+0x2c>) 8014be2: 681b ldr r3, [r3, #0] 8014be4: 2b00 cmp r3, #0 8014be6: d1f5 bne.n 8014bd4 <__sinit+0xc> 8014be8: f7ff ffc4 bl 8014b74 8014bec: e7f2 b.n 8014bd4 <__sinit+0xc> 8014bee: bf00 nop 8014bf0: 08014b35 .word 0x08014b35 8014bf4: 200015c4 .word 0x200015c4 08014bf8 <_vsniprintf_r>: 8014bf8: b530 push {r4, r5, lr} 8014bfa: 4614 mov r4, r2 8014bfc: 2c00 cmp r4, #0 8014bfe: 4605 mov r5, r0 8014c00: 461a mov r2, r3 8014c02: b09b sub sp, #108 @ 0x6c 8014c04: da05 bge.n 8014c12 <_vsniprintf_r+0x1a> 8014c06: 238b movs r3, #139 @ 0x8b 8014c08: 6003 str r3, [r0, #0] 8014c0a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8014c0e: b01b add sp, #108 @ 0x6c 8014c10: bd30 pop {r4, r5, pc} 8014c12: f44f 7302 mov.w r3, #520 @ 0x208 8014c16: f8ad 300c strh.w r3, [sp, #12] 8014c1a: f04f 0300 mov.w r3, #0 8014c1e: 9319 str r3, [sp, #100] @ 0x64 8014c20: bf0c ite eq 8014c22: 4623 moveq r3, r4 8014c24: f104 33ff addne.w r3, r4, #4294967295 @ 0xffffffff 8014c28: 9302 str r3, [sp, #8] 8014c2a: 9305 str r3, [sp, #20] 8014c2c: f64f 73ff movw r3, #65535 @ 0xffff 8014c30: 9100 str r1, [sp, #0] 8014c32: 9104 str r1, [sp, #16] 8014c34: f8ad 300e strh.w r3, [sp, #14] 8014c38: 4669 mov r1, sp 8014c3a: 9b1e ldr r3, [sp, #120] @ 0x78 8014c3c: f000 ff64 bl 8015b08 <_svfiprintf_r> 8014c40: 1c43 adds r3, r0, #1 8014c42: bfbc itt lt 8014c44: 238b movlt r3, #139 @ 0x8b 8014c46: 602b strlt r3, [r5, #0] 8014c48: 2c00 cmp r4, #0 8014c4a: d0e0 beq.n 8014c0e <_vsniprintf_r+0x16> 8014c4c: 2200 movs r2, #0 8014c4e: 9b00 ldr r3, [sp, #0] 8014c50: 701a strb r2, [r3, #0] 8014c52: e7dc b.n 8014c0e <_vsniprintf_r+0x16> 08014c54 : 8014c54: b507 push {r0, r1, r2, lr} 8014c56: 9300 str r3, [sp, #0] 8014c58: 4613 mov r3, r2 8014c5a: 460a mov r2, r1 8014c5c: 4601 mov r1, r0 8014c5e: 4803 ldr r0, [pc, #12] @ (8014c6c ) 8014c60: 6800 ldr r0, [r0, #0] 8014c62: f7ff ffc9 bl 8014bf8 <_vsniprintf_r> 8014c66: b003 add sp, #12 8014c68: f85d fb04 ldr.w pc, [sp], #4 8014c6c: 2000009c .word 0x2000009c 08014c70 <_fwalk_sglue>: 8014c70: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8014c74: 4607 mov r7, r0 8014c76: 4688 mov r8, r1 8014c78: 4614 mov r4, r2 8014c7a: 2600 movs r6, #0 8014c7c: e9d4 9501 ldrd r9, r5, [r4, #4] 8014c80: f1b9 0901 subs.w r9, r9, #1 8014c84: d505 bpl.n 8014c92 <_fwalk_sglue+0x22> 8014c86: 6824 ldr r4, [r4, #0] 8014c88: 2c00 cmp r4, #0 8014c8a: d1f7 bne.n 8014c7c <_fwalk_sglue+0xc> 8014c8c: 4630 mov r0, r6 8014c8e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8014c92: 89ab ldrh r3, [r5, #12] 8014c94: 2b01 cmp r3, #1 8014c96: d907 bls.n 8014ca8 <_fwalk_sglue+0x38> 8014c98: f9b5 300e ldrsh.w r3, [r5, #14] 8014c9c: 3301 adds r3, #1 8014c9e: d003 beq.n 8014ca8 <_fwalk_sglue+0x38> 8014ca0: 4629 mov r1, r5 8014ca2: 4638 mov r0, r7 8014ca4: 47c0 blx r8 8014ca6: 4306 orrs r6, r0 8014ca8: 3568 adds r5, #104 @ 0x68 8014caa: e7e9 b.n 8014c80 <_fwalk_sglue+0x10> 08014cac : 8014cac: 4603 mov r3, r0 8014cae: 4402 add r2, r0 8014cb0: 4293 cmp r3, r2 8014cb2: d100 bne.n 8014cb6 8014cb4: 4770 bx lr 8014cb6: f803 1b01 strb.w r1, [r3], #1 8014cba: e7f9 b.n 8014cb0 08014cbc <__errno>: 8014cbc: 4b01 ldr r3, [pc, #4] @ (8014cc4 <__errno+0x8>) 8014cbe: 6818 ldr r0, [r3, #0] 8014cc0: 4770 bx lr 8014cc2: bf00 nop 8014cc4: 2000009c .word 0x2000009c 08014cc8 <__libc_init_array>: 8014cc8: b570 push {r4, r5, r6, lr} 8014cca: 2600 movs r6, #0 8014ccc: 4d0c ldr r5, [pc, #48] @ (8014d00 <__libc_init_array+0x38>) 8014cce: 4c0d ldr r4, [pc, #52] @ (8014d04 <__libc_init_array+0x3c>) 8014cd0: 1b64 subs r4, r4, r5 8014cd2: 10a4 asrs r4, r4, #2 8014cd4: 42a6 cmp r6, r4 8014cd6: d109 bne.n 8014cec <__libc_init_array+0x24> 8014cd8: f002 f904 bl 8016ee4 <_init> 8014cdc: 2600 movs r6, #0 8014cde: 4d0a ldr r5, [pc, #40] @ (8014d08 <__libc_init_array+0x40>) 8014ce0: 4c0a ldr r4, [pc, #40] @ (8014d0c <__libc_init_array+0x44>) 8014ce2: 1b64 subs r4, r4, r5 8014ce4: 10a4 asrs r4, r4, #2 8014ce6: 42a6 cmp r6, r4 8014ce8: d105 bne.n 8014cf6 <__libc_init_array+0x2e> 8014cea: bd70 pop {r4, r5, r6, pc} 8014cec: f855 3b04 ldr.w r3, [r5], #4 8014cf0: 4798 blx r3 8014cf2: 3601 adds r6, #1 8014cf4: e7ee b.n 8014cd4 <__libc_init_array+0xc> 8014cf6: f855 3b04 ldr.w r3, [r5], #4 8014cfa: 4798 blx r3 8014cfc: 3601 adds r6, #1 8014cfe: e7f2 b.n 8014ce6 <__libc_init_array+0x1e> 8014d00: 08017cd4 .word 0x08017cd4 8014d04: 08017cd4 .word 0x08017cd4 8014d08: 08017cd4 .word 0x08017cd4 8014d0c: 08017cd8 .word 0x08017cd8 08014d10 <__retarget_lock_init_recursive>: 8014d10: 4770 bx lr 08014d12 <__retarget_lock_acquire_recursive>: 8014d12: 4770 bx lr 08014d14 <__retarget_lock_release_recursive>: 8014d14: 4770 bx lr ... 08014d18 <_localeconv_r>: 8014d18: 4800 ldr r0, [pc, #0] @ (8014d1c <_localeconv_r+0x4>) 8014d1a: 4770 bx lr 8014d1c: 200001dc .word 0x200001dc 08014d20 : 8014d20: 4603 mov r3, r0 8014d22: b510 push {r4, lr} 8014d24: b2c9 uxtb r1, r1 8014d26: 4402 add r2, r0 8014d28: 4293 cmp r3, r2 8014d2a: 4618 mov r0, r3 8014d2c: d101 bne.n 8014d32 8014d2e: 2000 movs r0, #0 8014d30: e003 b.n 8014d3a 8014d32: 7804 ldrb r4, [r0, #0] 8014d34: 3301 adds r3, #1 8014d36: 428c cmp r4, r1 8014d38: d1f6 bne.n 8014d28 8014d3a: bd10 pop {r4, pc} 08014d3c : 8014d3c: 440a add r2, r1 8014d3e: 4291 cmp r1, r2 8014d40: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8014d44: d100 bne.n 8014d48 8014d46: 4770 bx lr 8014d48: b510 push {r4, lr} 8014d4a: f811 4b01 ldrb.w r4, [r1], #1 8014d4e: 4291 cmp r1, r2 8014d50: f803 4f01 strb.w r4, [r3, #1]! 8014d54: d1f9 bne.n 8014d4a 8014d56: bd10 pop {r4, pc} 08014d58 <__assert_func>: 8014d58: b51f push {r0, r1, r2, r3, r4, lr} 8014d5a: 4614 mov r4, r2 8014d5c: 461a mov r2, r3 8014d5e: 4b09 ldr r3, [pc, #36] @ (8014d84 <__assert_func+0x2c>) 8014d60: 4605 mov r5, r0 8014d62: 681b ldr r3, [r3, #0] 8014d64: 68d8 ldr r0, [r3, #12] 8014d66: b14c cbz r4, 8014d7c <__assert_func+0x24> 8014d68: 4b07 ldr r3, [pc, #28] @ (8014d88 <__assert_func+0x30>) 8014d6a: e9cd 3401 strd r3, r4, [sp, #4] 8014d6e: 9100 str r1, [sp, #0] 8014d70: 462b mov r3, r5 8014d72: 4906 ldr r1, [pc, #24] @ (8014d8c <__assert_func+0x34>) 8014d74: f001 fce0 bl 8016738 8014d78: f001 fd8e bl 8016898 8014d7c: 4b04 ldr r3, [pc, #16] @ (8014d90 <__assert_func+0x38>) 8014d7e: 461c mov r4, r3 8014d80: e7f3 b.n 8014d6a <__assert_func+0x12> 8014d82: bf00 nop 8014d84: 2000009c .word 0x2000009c 8014d88: 08017988 .word 0x08017988 8014d8c: 08017995 .word 0x08017995 8014d90: 080179c3 .word 0x080179c3 08014d94 : 8014d94: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8014d98: 6903 ldr r3, [r0, #16] 8014d9a: 690c ldr r4, [r1, #16] 8014d9c: 4607 mov r7, r0 8014d9e: 42a3 cmp r3, r4 8014da0: db7e blt.n 8014ea0 8014da2: 3c01 subs r4, #1 8014da4: 00a3 lsls r3, r4, #2 8014da6: f100 0514 add.w r5, r0, #20 8014daa: f101 0814 add.w r8, r1, #20 8014dae: 9300 str r3, [sp, #0] 8014db0: eb05 0384 add.w r3, r5, r4, lsl #2 8014db4: 9301 str r3, [sp, #4] 8014db6: f858 3024 ldr.w r3, [r8, r4, lsl #2] 8014dba: f855 2024 ldr.w r2, [r5, r4, lsl #2] 8014dbe: 3301 adds r3, #1 8014dc0: 429a cmp r2, r3 8014dc2: fbb2 f6f3 udiv r6, r2, r3 8014dc6: eb08 0984 add.w r9, r8, r4, lsl #2 8014dca: d32e bcc.n 8014e2a 8014dcc: f04f 0a00 mov.w sl, #0 8014dd0: 46c4 mov ip, r8 8014dd2: 46ae mov lr, r5 8014dd4: 46d3 mov fp, sl 8014dd6: f85c 3b04 ldr.w r3, [ip], #4 8014dda: b298 uxth r0, r3 8014ddc: fb06 a000 mla r0, r6, r0, sl 8014de0: 0c1b lsrs r3, r3, #16 8014de2: 0c02 lsrs r2, r0, #16 8014de4: fb06 2303 mla r3, r6, r3, r2 8014de8: f8de 2000 ldr.w r2, [lr] 8014dec: b280 uxth r0, r0 8014dee: b292 uxth r2, r2 8014df0: 1a12 subs r2, r2, r0 8014df2: 445a add r2, fp 8014df4: f8de 0000 ldr.w r0, [lr] 8014df8: ea4f 4a13 mov.w sl, r3, lsr #16 8014dfc: b29b uxth r3, r3 8014dfe: ebc3 4322 rsb r3, r3, r2, asr #16 8014e02: eb03 4310 add.w r3, r3, r0, lsr #16 8014e06: b292 uxth r2, r2 8014e08: ea42 4203 orr.w r2, r2, r3, lsl #16 8014e0c: 45e1 cmp r9, ip 8014e0e: ea4f 4b23 mov.w fp, r3, asr #16 8014e12: f84e 2b04 str.w r2, [lr], #4 8014e16: d2de bcs.n 8014dd6 8014e18: 9b00 ldr r3, [sp, #0] 8014e1a: 58eb ldr r3, [r5, r3] 8014e1c: b92b cbnz r3, 8014e2a 8014e1e: 9b01 ldr r3, [sp, #4] 8014e20: 3b04 subs r3, #4 8014e22: 429d cmp r5, r3 8014e24: 461a mov r2, r3 8014e26: d32f bcc.n 8014e88 8014e28: 613c str r4, [r7, #16] 8014e2a: 4638 mov r0, r7 8014e2c: f001 fb38 bl 80164a0 <__mcmp> 8014e30: 2800 cmp r0, #0 8014e32: db25 blt.n 8014e80 8014e34: 4629 mov r1, r5 8014e36: 2000 movs r0, #0 8014e38: f858 2b04 ldr.w r2, [r8], #4 8014e3c: f8d1 c000 ldr.w ip, [r1] 8014e40: fa1f fe82 uxth.w lr, r2 8014e44: fa1f f38c uxth.w r3, ip 8014e48: eba3 030e sub.w r3, r3, lr 8014e4c: 4403 add r3, r0 8014e4e: 0c12 lsrs r2, r2, #16 8014e50: ebc2 4223 rsb r2, r2, r3, asr #16 8014e54: eb02 421c add.w r2, r2, ip, lsr #16 8014e58: b29b uxth r3, r3 8014e5a: ea43 4302 orr.w r3, r3, r2, lsl #16 8014e5e: 45c1 cmp r9, r8 8014e60: ea4f 4022 mov.w r0, r2, asr #16 8014e64: f841 3b04 str.w r3, [r1], #4 8014e68: d2e6 bcs.n 8014e38 8014e6a: f855 2024 ldr.w r2, [r5, r4, lsl #2] 8014e6e: eb05 0384 add.w r3, r5, r4, lsl #2 8014e72: b922 cbnz r2, 8014e7e 8014e74: 3b04 subs r3, #4 8014e76: 429d cmp r5, r3 8014e78: 461a mov r2, r3 8014e7a: d30b bcc.n 8014e94 8014e7c: 613c str r4, [r7, #16] 8014e7e: 3601 adds r6, #1 8014e80: 4630 mov r0, r6 8014e82: b003 add sp, #12 8014e84: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8014e88: 6812 ldr r2, [r2, #0] 8014e8a: 3b04 subs r3, #4 8014e8c: 2a00 cmp r2, #0 8014e8e: d1cb bne.n 8014e28 8014e90: 3c01 subs r4, #1 8014e92: e7c6 b.n 8014e22 8014e94: 6812 ldr r2, [r2, #0] 8014e96: 3b04 subs r3, #4 8014e98: 2a00 cmp r2, #0 8014e9a: d1ef bne.n 8014e7c 8014e9c: 3c01 subs r4, #1 8014e9e: e7ea b.n 8014e76 8014ea0: 2000 movs r0, #0 8014ea2: e7ee b.n 8014e82 8014ea4: 0000 movs r0, r0 ... 08014ea8 <_dtoa_r>: 8014ea8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8014eac: 4614 mov r4, r2 8014eae: 461d mov r5, r3 8014eb0: 69c7 ldr r7, [r0, #28] 8014eb2: b097 sub sp, #92 @ 0x5c 8014eb4: 4681 mov r9, r0 8014eb6: e9cd 4506 strd r4, r5, [sp, #24] 8014eba: 9e23 ldr r6, [sp, #140] @ 0x8c 8014ebc: b97f cbnz r7, 8014ede <_dtoa_r+0x36> 8014ebe: 2010 movs r0, #16 8014ec0: f000 ff1e bl 8015d00 8014ec4: 4602 mov r2, r0 8014ec6: f8c9 001c str.w r0, [r9, #28] 8014eca: b920 cbnz r0, 8014ed6 <_dtoa_r+0x2e> 8014ecc: 21ef movs r1, #239 @ 0xef 8014ece: 4bac ldr r3, [pc, #688] @ (8015180 <_dtoa_r+0x2d8>) 8014ed0: 48ac ldr r0, [pc, #688] @ (8015184 <_dtoa_r+0x2dc>) 8014ed2: f7ff ff41 bl 8014d58 <__assert_func> 8014ed6: e9c0 7701 strd r7, r7, [r0, #4] 8014eda: 6007 str r7, [r0, #0] 8014edc: 60c7 str r7, [r0, #12] 8014ede: f8d9 301c ldr.w r3, [r9, #28] 8014ee2: 6819 ldr r1, [r3, #0] 8014ee4: b159 cbz r1, 8014efe <_dtoa_r+0x56> 8014ee6: 685a ldr r2, [r3, #4] 8014ee8: 2301 movs r3, #1 8014eea: 4093 lsls r3, r2 8014eec: 604a str r2, [r1, #4] 8014eee: 608b str r3, [r1, #8] 8014ef0: 4648 mov r0, r9 8014ef2: f001 f8a3 bl 801603c <_Bfree> 8014ef6: 2200 movs r2, #0 8014ef8: f8d9 301c ldr.w r3, [r9, #28] 8014efc: 601a str r2, [r3, #0] 8014efe: 1e2b subs r3, r5, #0 8014f00: bfaf iteee ge 8014f02: 2300 movge r3, #0 8014f04: 2201 movlt r2, #1 8014f06: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000 8014f0a: 9307 strlt r3, [sp, #28] 8014f0c: bfa8 it ge 8014f0e: 6033 strge r3, [r6, #0] 8014f10: f8dd 801c ldr.w r8, [sp, #28] 8014f14: 4b9c ldr r3, [pc, #624] @ (8015188 <_dtoa_r+0x2e0>) 8014f16: bfb8 it lt 8014f18: 6032 strlt r2, [r6, #0] 8014f1a: ea33 0308 bics.w r3, r3, r8 8014f1e: d112 bne.n 8014f46 <_dtoa_r+0x9e> 8014f20: f242 730f movw r3, #9999 @ 0x270f 8014f24: 9a22 ldr r2, [sp, #136] @ 0x88 8014f26: 6013 str r3, [r2, #0] 8014f28: f3c8 0313 ubfx r3, r8, #0, #20 8014f2c: 4323 orrs r3, r4 8014f2e: f000 855e beq.w 80159ee <_dtoa_r+0xb46> 8014f32: 9b24 ldr r3, [sp, #144] @ 0x90 8014f34: f8df a254 ldr.w sl, [pc, #596] @ 801518c <_dtoa_r+0x2e4> 8014f38: 2b00 cmp r3, #0 8014f3a: f000 8560 beq.w 80159fe <_dtoa_r+0xb56> 8014f3e: f10a 0303 add.w r3, sl, #3 8014f42: f000 bd5a b.w 80159fa <_dtoa_r+0xb52> 8014f46: e9dd 2306 ldrd r2, r3, [sp, #24] 8014f4a: e9cd 230c strd r2, r3, [sp, #48] @ 0x30 8014f4e: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8014f52: 2200 movs r2, #0 8014f54: 2300 movs r3, #0 8014f56: f7f3 fd93 bl 8008a80 <__aeabi_dcmpeq> 8014f5a: 4607 mov r7, r0 8014f5c: b158 cbz r0, 8014f76 <_dtoa_r+0xce> 8014f5e: 2301 movs r3, #1 8014f60: 9a22 ldr r2, [sp, #136] @ 0x88 8014f62: 6013 str r3, [r2, #0] 8014f64: 9b24 ldr r3, [sp, #144] @ 0x90 8014f66: b113 cbz r3, 8014f6e <_dtoa_r+0xc6> 8014f68: 4b89 ldr r3, [pc, #548] @ (8015190 <_dtoa_r+0x2e8>) 8014f6a: 9a24 ldr r2, [sp, #144] @ 0x90 8014f6c: 6013 str r3, [r2, #0] 8014f6e: f8df a224 ldr.w sl, [pc, #548] @ 8015194 <_dtoa_r+0x2ec> 8014f72: f000 bd44 b.w 80159fe <_dtoa_r+0xb56> 8014f76: ab14 add r3, sp, #80 @ 0x50 8014f78: 9301 str r3, [sp, #4] 8014f7a: ab15 add r3, sp, #84 @ 0x54 8014f7c: 9300 str r3, [sp, #0] 8014f7e: 4648 mov r0, r9 8014f80: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30 8014f84: f001 fb3c bl 8016600 <__d2b> 8014f88: f3c8 560a ubfx r6, r8, #20, #11 8014f8c: 9003 str r0, [sp, #12] 8014f8e: 2e00 cmp r6, #0 8014f90: d078 beq.n 8015084 <_dtoa_r+0x1dc> 8014f92: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8014f96: 9b0d ldr r3, [sp, #52] @ 0x34 8014f98: f2a6 36ff subw r6, r6, #1023 @ 0x3ff 8014f9c: f3c3 0313 ubfx r3, r3, #0, #20 8014fa0: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000 8014fa4: f443 1340 orr.w r3, r3, #3145728 @ 0x300000 8014fa8: 9712 str r7, [sp, #72] @ 0x48 8014faa: 4619 mov r1, r3 8014fac: 2200 movs r2, #0 8014fae: 4b7a ldr r3, [pc, #488] @ (8015198 <_dtoa_r+0x2f0>) 8014fb0: f7f3 f946 bl 8008240 <__aeabi_dsub> 8014fb4: a36c add r3, pc, #432 @ (adr r3, 8015168 <_dtoa_r+0x2c0>) 8014fb6: e9d3 2300 ldrd r2, r3, [r3] 8014fba: f7f3 faf9 bl 80085b0 <__aeabi_dmul> 8014fbe: a36c add r3, pc, #432 @ (adr r3, 8015170 <_dtoa_r+0x2c8>) 8014fc0: e9d3 2300 ldrd r2, r3, [r3] 8014fc4: f7f3 f93e bl 8008244 <__adddf3> 8014fc8: 4604 mov r4, r0 8014fca: 4630 mov r0, r6 8014fcc: 460d mov r5, r1 8014fce: f7f3 fa85 bl 80084dc <__aeabi_i2d> 8014fd2: a369 add r3, pc, #420 @ (adr r3, 8015178 <_dtoa_r+0x2d0>) 8014fd4: e9d3 2300 ldrd r2, r3, [r3] 8014fd8: f7f3 faea bl 80085b0 <__aeabi_dmul> 8014fdc: 4602 mov r2, r0 8014fde: 460b mov r3, r1 8014fe0: 4620 mov r0, r4 8014fe2: 4629 mov r1, r5 8014fe4: f7f3 f92e bl 8008244 <__adddf3> 8014fe8: 4604 mov r4, r0 8014fea: 460d mov r5, r1 8014fec: f7f3 fd90 bl 8008b10 <__aeabi_d2iz> 8014ff0: 2200 movs r2, #0 8014ff2: 4607 mov r7, r0 8014ff4: 2300 movs r3, #0 8014ff6: 4620 mov r0, r4 8014ff8: 4629 mov r1, r5 8014ffa: f7f3 fd4b bl 8008a94 <__aeabi_dcmplt> 8014ffe: b140 cbz r0, 8015012 <_dtoa_r+0x16a> 8015000: 4638 mov r0, r7 8015002: f7f3 fa6b bl 80084dc <__aeabi_i2d> 8015006: 4622 mov r2, r4 8015008: 462b mov r3, r5 801500a: f7f3 fd39 bl 8008a80 <__aeabi_dcmpeq> 801500e: b900 cbnz r0, 8015012 <_dtoa_r+0x16a> 8015010: 3f01 subs r7, #1 8015012: 2f16 cmp r7, #22 8015014: d854 bhi.n 80150c0 <_dtoa_r+0x218> 8015016: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 801501a: 4b60 ldr r3, [pc, #384] @ (801519c <_dtoa_r+0x2f4>) 801501c: eb03 03c7 add.w r3, r3, r7, lsl #3 8015020: e9d3 2300 ldrd r2, r3, [r3] 8015024: f7f3 fd36 bl 8008a94 <__aeabi_dcmplt> 8015028: 2800 cmp r0, #0 801502a: d04b beq.n 80150c4 <_dtoa_r+0x21c> 801502c: 2300 movs r3, #0 801502e: 3f01 subs r7, #1 8015030: 930f str r3, [sp, #60] @ 0x3c 8015032: 9b14 ldr r3, [sp, #80] @ 0x50 8015034: 1b9b subs r3, r3, r6 8015036: 1e5a subs r2, r3, #1 8015038: bf49 itett mi 801503a: f1c3 0301 rsbmi r3, r3, #1 801503e: 2300 movpl r3, #0 8015040: 9304 strmi r3, [sp, #16] 8015042: 2300 movmi r3, #0 8015044: 9209 str r2, [sp, #36] @ 0x24 8015046: bf54 ite pl 8015048: 9304 strpl r3, [sp, #16] 801504a: 9309 strmi r3, [sp, #36] @ 0x24 801504c: 2f00 cmp r7, #0 801504e: db3b blt.n 80150c8 <_dtoa_r+0x220> 8015050: 9b09 ldr r3, [sp, #36] @ 0x24 8015052: 970e str r7, [sp, #56] @ 0x38 8015054: 443b add r3, r7 8015056: 9309 str r3, [sp, #36] @ 0x24 8015058: 2300 movs r3, #0 801505a: 930a str r3, [sp, #40] @ 0x28 801505c: 9b20 ldr r3, [sp, #128] @ 0x80 801505e: 2b09 cmp r3, #9 8015060: d865 bhi.n 801512e <_dtoa_r+0x286> 8015062: 2b05 cmp r3, #5 8015064: bfc4 itt gt 8015066: 3b04 subgt r3, #4 8015068: 9320 strgt r3, [sp, #128] @ 0x80 801506a: 9b20 ldr r3, [sp, #128] @ 0x80 801506c: bfc8 it gt 801506e: 2400 movgt r4, #0 8015070: f1a3 0302 sub.w r3, r3, #2 8015074: bfd8 it le 8015076: 2401 movle r4, #1 8015078: 2b03 cmp r3, #3 801507a: d864 bhi.n 8015146 <_dtoa_r+0x29e> 801507c: e8df f003 tbb [pc, r3] 8015080: 2c385553 .word 0x2c385553 8015084: e9dd 6314 ldrd r6, r3, [sp, #80] @ 0x50 8015088: 441e add r6, r3 801508a: f206 4332 addw r3, r6, #1074 @ 0x432 801508e: 2b20 cmp r3, #32 8015090: bfc1 itttt gt 8015092: f1c3 0340 rsbgt r3, r3, #64 @ 0x40 8015096: fa08 f803 lslgt.w r8, r8, r3 801509a: f206 4312 addwgt r3, r6, #1042 @ 0x412 801509e: fa24 f303 lsrgt.w r3, r4, r3 80150a2: bfd6 itet le 80150a4: f1c3 0320 rsble r3, r3, #32 80150a8: ea48 0003 orrgt.w r0, r8, r3 80150ac: fa04 f003 lslle.w r0, r4, r3 80150b0: f7f3 fa04 bl 80084bc <__aeabi_ui2d> 80150b4: 2201 movs r2, #1 80150b6: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000 80150ba: 3e01 subs r6, #1 80150bc: 9212 str r2, [sp, #72] @ 0x48 80150be: e774 b.n 8014faa <_dtoa_r+0x102> 80150c0: 2301 movs r3, #1 80150c2: e7b5 b.n 8015030 <_dtoa_r+0x188> 80150c4: 900f str r0, [sp, #60] @ 0x3c 80150c6: e7b4 b.n 8015032 <_dtoa_r+0x18a> 80150c8: 9b04 ldr r3, [sp, #16] 80150ca: 1bdb subs r3, r3, r7 80150cc: 9304 str r3, [sp, #16] 80150ce: 427b negs r3, r7 80150d0: 930a str r3, [sp, #40] @ 0x28 80150d2: 2300 movs r3, #0 80150d4: 930e str r3, [sp, #56] @ 0x38 80150d6: e7c1 b.n 801505c <_dtoa_r+0x1b4> 80150d8: 2301 movs r3, #1 80150da: 930b str r3, [sp, #44] @ 0x2c 80150dc: 9b21 ldr r3, [sp, #132] @ 0x84 80150de: eb07 0b03 add.w fp, r7, r3 80150e2: f10b 0301 add.w r3, fp, #1 80150e6: 2b01 cmp r3, #1 80150e8: 9308 str r3, [sp, #32] 80150ea: bfb8 it lt 80150ec: 2301 movlt r3, #1 80150ee: e006 b.n 80150fe <_dtoa_r+0x256> 80150f0: 2301 movs r3, #1 80150f2: 930b str r3, [sp, #44] @ 0x2c 80150f4: 9b21 ldr r3, [sp, #132] @ 0x84 80150f6: 2b00 cmp r3, #0 80150f8: dd28 ble.n 801514c <_dtoa_r+0x2a4> 80150fa: 469b mov fp, r3 80150fc: 9308 str r3, [sp, #32] 80150fe: 2100 movs r1, #0 8015100: 2204 movs r2, #4 8015102: f8d9 001c ldr.w r0, [r9, #28] 8015106: f102 0514 add.w r5, r2, #20 801510a: 429d cmp r5, r3 801510c: d926 bls.n 801515c <_dtoa_r+0x2b4> 801510e: 6041 str r1, [r0, #4] 8015110: 4648 mov r0, r9 8015112: f000 ff53 bl 8015fbc <_Balloc> 8015116: 4682 mov sl, r0 8015118: 2800 cmp r0, #0 801511a: d143 bne.n 80151a4 <_dtoa_r+0x2fc> 801511c: 4602 mov r2, r0 801511e: f240 11af movw r1, #431 @ 0x1af 8015122: 4b1f ldr r3, [pc, #124] @ (80151a0 <_dtoa_r+0x2f8>) 8015124: e6d4 b.n 8014ed0 <_dtoa_r+0x28> 8015126: 2300 movs r3, #0 8015128: e7e3 b.n 80150f2 <_dtoa_r+0x24a> 801512a: 2300 movs r3, #0 801512c: e7d5 b.n 80150da <_dtoa_r+0x232> 801512e: 2401 movs r4, #1 8015130: 2300 movs r3, #0 8015132: 940b str r4, [sp, #44] @ 0x2c 8015134: 9320 str r3, [sp, #128] @ 0x80 8015136: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff 801513a: 2200 movs r2, #0 801513c: 2312 movs r3, #18 801513e: f8cd b020 str.w fp, [sp, #32] 8015142: 9221 str r2, [sp, #132] @ 0x84 8015144: e7db b.n 80150fe <_dtoa_r+0x256> 8015146: 2301 movs r3, #1 8015148: 930b str r3, [sp, #44] @ 0x2c 801514a: e7f4 b.n 8015136 <_dtoa_r+0x28e> 801514c: f04f 0b01 mov.w fp, #1 8015150: 465b mov r3, fp 8015152: f8cd b020 str.w fp, [sp, #32] 8015156: f8cd b084 str.w fp, [sp, #132] @ 0x84 801515a: e7d0 b.n 80150fe <_dtoa_r+0x256> 801515c: 3101 adds r1, #1 801515e: 0052 lsls r2, r2, #1 8015160: e7d1 b.n 8015106 <_dtoa_r+0x25e> 8015162: bf00 nop 8015164: f3af 8000 nop.w 8015168: 636f4361 .word 0x636f4361 801516c: 3fd287a7 .word 0x3fd287a7 8015170: 8b60c8b3 .word 0x8b60c8b3 8015174: 3fc68a28 .word 0x3fc68a28 8015178: 509f79fb .word 0x509f79fb 801517c: 3fd34413 .word 0x3fd34413 8015180: 080179d1 .word 0x080179d1 8015184: 080179e8 .word 0x080179e8 8015188: 7ff00000 .word 0x7ff00000 801518c: 080179cd .word 0x080179cd 8015190: 08017965 .word 0x08017965 8015194: 08017964 .word 0x08017964 8015198: 3ff80000 .word 0x3ff80000 801519c: 08017b00 .word 0x08017b00 80151a0: 08017a40 .word 0x08017a40 80151a4: f8d9 301c ldr.w r3, [r9, #28] 80151a8: 6018 str r0, [r3, #0] 80151aa: 9b08 ldr r3, [sp, #32] 80151ac: 2b0e cmp r3, #14 80151ae: f200 80a1 bhi.w 80152f4 <_dtoa_r+0x44c> 80151b2: 2c00 cmp r4, #0 80151b4: f000 809e beq.w 80152f4 <_dtoa_r+0x44c> 80151b8: 2f00 cmp r7, #0 80151ba: dd33 ble.n 8015224 <_dtoa_r+0x37c> 80151bc: 4b9c ldr r3, [pc, #624] @ (8015430 <_dtoa_r+0x588>) 80151be: f007 020f and.w r2, r7, #15 80151c2: eb03 03c2 add.w r3, r3, r2, lsl #3 80151c6: 05f8 lsls r0, r7, #23 80151c8: e9d3 3400 ldrd r3, r4, [r3] 80151cc: e9cd 3410 strd r3, r4, [sp, #64] @ 0x40 80151d0: ea4f 1427 mov.w r4, r7, asr #4 80151d4: d516 bpl.n 8015204 <_dtoa_r+0x35c> 80151d6: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 80151da: 4b96 ldr r3, [pc, #600] @ (8015434 <_dtoa_r+0x58c>) 80151dc: 2603 movs r6, #3 80151de: e9d3 2308 ldrd r2, r3, [r3, #32] 80151e2: f7f3 fb0f bl 8008804 <__aeabi_ddiv> 80151e6: e9cd 0106 strd r0, r1, [sp, #24] 80151ea: f004 040f and.w r4, r4, #15 80151ee: 4d91 ldr r5, [pc, #580] @ (8015434 <_dtoa_r+0x58c>) 80151f0: b954 cbnz r4, 8015208 <_dtoa_r+0x360> 80151f2: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 80151f6: e9dd 0106 ldrd r0, r1, [sp, #24] 80151fa: f7f3 fb03 bl 8008804 <__aeabi_ddiv> 80151fe: e9cd 0106 strd r0, r1, [sp, #24] 8015202: e028 b.n 8015256 <_dtoa_r+0x3ae> 8015204: 2602 movs r6, #2 8015206: e7f2 b.n 80151ee <_dtoa_r+0x346> 8015208: 07e1 lsls r1, r4, #31 801520a: d508 bpl.n 801521e <_dtoa_r+0x376> 801520c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8015210: e9d5 2300 ldrd r2, r3, [r5] 8015214: f7f3 f9cc bl 80085b0 <__aeabi_dmul> 8015218: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 801521c: 3601 adds r6, #1 801521e: 1064 asrs r4, r4, #1 8015220: 3508 adds r5, #8 8015222: e7e5 b.n 80151f0 <_dtoa_r+0x348> 8015224: f000 80af beq.w 8015386 <_dtoa_r+0x4de> 8015228: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 801522c: 427c negs r4, r7 801522e: 4b80 ldr r3, [pc, #512] @ (8015430 <_dtoa_r+0x588>) 8015230: f004 020f and.w r2, r4, #15 8015234: eb03 03c2 add.w r3, r3, r2, lsl #3 8015238: e9d3 2300 ldrd r2, r3, [r3] 801523c: f7f3 f9b8 bl 80085b0 <__aeabi_dmul> 8015240: 2602 movs r6, #2 8015242: 2300 movs r3, #0 8015244: e9cd 0106 strd r0, r1, [sp, #24] 8015248: 4d7a ldr r5, [pc, #488] @ (8015434 <_dtoa_r+0x58c>) 801524a: 1124 asrs r4, r4, #4 801524c: 2c00 cmp r4, #0 801524e: f040 808f bne.w 8015370 <_dtoa_r+0x4c8> 8015252: 2b00 cmp r3, #0 8015254: d1d3 bne.n 80151fe <_dtoa_r+0x356> 8015256: e9dd 4506 ldrd r4, r5, [sp, #24] 801525a: 9b0f ldr r3, [sp, #60] @ 0x3c 801525c: 2b00 cmp r3, #0 801525e: f000 8094 beq.w 801538a <_dtoa_r+0x4e2> 8015262: 2200 movs r2, #0 8015264: 4620 mov r0, r4 8015266: 4629 mov r1, r5 8015268: 4b73 ldr r3, [pc, #460] @ (8015438 <_dtoa_r+0x590>) 801526a: f7f3 fc13 bl 8008a94 <__aeabi_dcmplt> 801526e: 2800 cmp r0, #0 8015270: f000 808b beq.w 801538a <_dtoa_r+0x4e2> 8015274: 9b08 ldr r3, [sp, #32] 8015276: 2b00 cmp r3, #0 8015278: f000 8087 beq.w 801538a <_dtoa_r+0x4e2> 801527c: f1bb 0f00 cmp.w fp, #0 8015280: dd34 ble.n 80152ec <_dtoa_r+0x444> 8015282: 4620 mov r0, r4 8015284: 2200 movs r2, #0 8015286: 4629 mov r1, r5 8015288: 4b6c ldr r3, [pc, #432] @ (801543c <_dtoa_r+0x594>) 801528a: f7f3 f991 bl 80085b0 <__aeabi_dmul> 801528e: 465c mov r4, fp 8015290: e9cd 0106 strd r0, r1, [sp, #24] 8015294: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 8015298: 3601 adds r6, #1 801529a: 4630 mov r0, r6 801529c: f7f3 f91e bl 80084dc <__aeabi_i2d> 80152a0: e9dd 2306 ldrd r2, r3, [sp, #24] 80152a4: f7f3 f984 bl 80085b0 <__aeabi_dmul> 80152a8: 2200 movs r2, #0 80152aa: 4b65 ldr r3, [pc, #404] @ (8015440 <_dtoa_r+0x598>) 80152ac: f7f2 ffca bl 8008244 <__adddf3> 80152b0: 4605 mov r5, r0 80152b2: f1a1 7650 sub.w r6, r1, #54525952 @ 0x3400000 80152b6: 2c00 cmp r4, #0 80152b8: d16a bne.n 8015390 <_dtoa_r+0x4e8> 80152ba: e9dd 0106 ldrd r0, r1, [sp, #24] 80152be: 2200 movs r2, #0 80152c0: 4b60 ldr r3, [pc, #384] @ (8015444 <_dtoa_r+0x59c>) 80152c2: f7f2 ffbd bl 8008240 <__aeabi_dsub> 80152c6: 4602 mov r2, r0 80152c8: 460b mov r3, r1 80152ca: e9cd 2306 strd r2, r3, [sp, #24] 80152ce: 462a mov r2, r5 80152d0: 4633 mov r3, r6 80152d2: f7f3 fbfd bl 8008ad0 <__aeabi_dcmpgt> 80152d6: 2800 cmp r0, #0 80152d8: f040 8298 bne.w 801580c <_dtoa_r+0x964> 80152dc: e9dd 0106 ldrd r0, r1, [sp, #24] 80152e0: 462a mov r2, r5 80152e2: f106 4300 add.w r3, r6, #2147483648 @ 0x80000000 80152e6: f7f3 fbd5 bl 8008a94 <__aeabi_dcmplt> 80152ea: bb38 cbnz r0, 801533c <_dtoa_r+0x494> 80152ec: e9dd 340c ldrd r3, r4, [sp, #48] @ 0x30 80152f0: e9cd 3406 strd r3, r4, [sp, #24] 80152f4: 9b15 ldr r3, [sp, #84] @ 0x54 80152f6: 2b00 cmp r3, #0 80152f8: f2c0 8157 blt.w 80155aa <_dtoa_r+0x702> 80152fc: 2f0e cmp r7, #14 80152fe: f300 8154 bgt.w 80155aa <_dtoa_r+0x702> 8015302: 4b4b ldr r3, [pc, #300] @ (8015430 <_dtoa_r+0x588>) 8015304: eb03 03c7 add.w r3, r3, r7, lsl #3 8015308: e9d3 3400 ldrd r3, r4, [r3] 801530c: e9cd 3404 strd r3, r4, [sp, #16] 8015310: 9b21 ldr r3, [sp, #132] @ 0x84 8015312: 2b00 cmp r3, #0 8015314: f280 80e5 bge.w 80154e2 <_dtoa_r+0x63a> 8015318: 9b08 ldr r3, [sp, #32] 801531a: 2b00 cmp r3, #0 801531c: f300 80e1 bgt.w 80154e2 <_dtoa_r+0x63a> 8015320: d10c bne.n 801533c <_dtoa_r+0x494> 8015322: e9dd 0104 ldrd r0, r1, [sp, #16] 8015326: 2200 movs r2, #0 8015328: 4b46 ldr r3, [pc, #280] @ (8015444 <_dtoa_r+0x59c>) 801532a: f7f3 f941 bl 80085b0 <__aeabi_dmul> 801532e: e9dd 2306 ldrd r2, r3, [sp, #24] 8015332: f7f3 fbc3 bl 8008abc <__aeabi_dcmpge> 8015336: 2800 cmp r0, #0 8015338: f000 8266 beq.w 8015808 <_dtoa_r+0x960> 801533c: 2400 movs r4, #0 801533e: 4625 mov r5, r4 8015340: 9b21 ldr r3, [sp, #132] @ 0x84 8015342: 4656 mov r6, sl 8015344: ea6f 0803 mvn.w r8, r3 8015348: 2700 movs r7, #0 801534a: 4621 mov r1, r4 801534c: 4648 mov r0, r9 801534e: f000 fe75 bl 801603c <_Bfree> 8015352: 2d00 cmp r5, #0 8015354: f000 80bd beq.w 80154d2 <_dtoa_r+0x62a> 8015358: b12f cbz r7, 8015366 <_dtoa_r+0x4be> 801535a: 42af cmp r7, r5 801535c: d003 beq.n 8015366 <_dtoa_r+0x4be> 801535e: 4639 mov r1, r7 8015360: 4648 mov r0, r9 8015362: f000 fe6b bl 801603c <_Bfree> 8015366: 4629 mov r1, r5 8015368: 4648 mov r0, r9 801536a: f000 fe67 bl 801603c <_Bfree> 801536e: e0b0 b.n 80154d2 <_dtoa_r+0x62a> 8015370: 07e2 lsls r2, r4, #31 8015372: d505 bpl.n 8015380 <_dtoa_r+0x4d8> 8015374: e9d5 2300 ldrd r2, r3, [r5] 8015378: f7f3 f91a bl 80085b0 <__aeabi_dmul> 801537c: 2301 movs r3, #1 801537e: 3601 adds r6, #1 8015380: 1064 asrs r4, r4, #1 8015382: 3508 adds r5, #8 8015384: e762 b.n 801524c <_dtoa_r+0x3a4> 8015386: 2602 movs r6, #2 8015388: e765 b.n 8015256 <_dtoa_r+0x3ae> 801538a: 46b8 mov r8, r7 801538c: 9c08 ldr r4, [sp, #32] 801538e: e784 b.n 801529a <_dtoa_r+0x3f2> 8015390: 4b27 ldr r3, [pc, #156] @ (8015430 <_dtoa_r+0x588>) 8015392: 990b ldr r1, [sp, #44] @ 0x2c 8015394: eb03 03c4 add.w r3, r3, r4, lsl #3 8015398: e953 2302 ldrd r2, r3, [r3, #-8] 801539c: 4454 add r4, sl 801539e: 2900 cmp r1, #0 80153a0: d054 beq.n 801544c <_dtoa_r+0x5a4> 80153a2: 2000 movs r0, #0 80153a4: 4928 ldr r1, [pc, #160] @ (8015448 <_dtoa_r+0x5a0>) 80153a6: f7f3 fa2d bl 8008804 <__aeabi_ddiv> 80153aa: 4633 mov r3, r6 80153ac: 462a mov r2, r5 80153ae: f7f2 ff47 bl 8008240 <__aeabi_dsub> 80153b2: 4656 mov r6, sl 80153b4: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 80153b8: e9dd 0106 ldrd r0, r1, [sp, #24] 80153bc: f7f3 fba8 bl 8008b10 <__aeabi_d2iz> 80153c0: 4605 mov r5, r0 80153c2: f7f3 f88b bl 80084dc <__aeabi_i2d> 80153c6: 4602 mov r2, r0 80153c8: 460b mov r3, r1 80153ca: e9dd 0106 ldrd r0, r1, [sp, #24] 80153ce: f7f2 ff37 bl 8008240 <__aeabi_dsub> 80153d2: 4602 mov r2, r0 80153d4: 460b mov r3, r1 80153d6: 3530 adds r5, #48 @ 0x30 80153d8: e9cd 2306 strd r2, r3, [sp, #24] 80153dc: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 80153e0: f806 5b01 strb.w r5, [r6], #1 80153e4: f7f3 fb56 bl 8008a94 <__aeabi_dcmplt> 80153e8: 2800 cmp r0, #0 80153ea: d172 bne.n 80154d2 <_dtoa_r+0x62a> 80153ec: e9dd 2306 ldrd r2, r3, [sp, #24] 80153f0: 2000 movs r0, #0 80153f2: 4911 ldr r1, [pc, #68] @ (8015438 <_dtoa_r+0x590>) 80153f4: f7f2 ff24 bl 8008240 <__aeabi_dsub> 80153f8: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 80153fc: f7f3 fb4a bl 8008a94 <__aeabi_dcmplt> 8015400: 2800 cmp r0, #0 8015402: f040 80b4 bne.w 801556e <_dtoa_r+0x6c6> 8015406: 42a6 cmp r6, r4 8015408: f43f af70 beq.w 80152ec <_dtoa_r+0x444> 801540c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8015410: 2200 movs r2, #0 8015412: 4b0a ldr r3, [pc, #40] @ (801543c <_dtoa_r+0x594>) 8015414: f7f3 f8cc bl 80085b0 <__aeabi_dmul> 8015418: 2200 movs r2, #0 801541a: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 801541e: e9dd 0106 ldrd r0, r1, [sp, #24] 8015422: 4b06 ldr r3, [pc, #24] @ (801543c <_dtoa_r+0x594>) 8015424: f7f3 f8c4 bl 80085b0 <__aeabi_dmul> 8015428: e9cd 0106 strd r0, r1, [sp, #24] 801542c: e7c4 b.n 80153b8 <_dtoa_r+0x510> 801542e: bf00 nop 8015430: 08017b00 .word 0x08017b00 8015434: 08017ad8 .word 0x08017ad8 8015438: 3ff00000 .word 0x3ff00000 801543c: 40240000 .word 0x40240000 8015440: 401c0000 .word 0x401c0000 8015444: 40140000 .word 0x40140000 8015448: 3fe00000 .word 0x3fe00000 801544c: 4631 mov r1, r6 801544e: 4628 mov r0, r5 8015450: f7f3 f8ae bl 80085b0 <__aeabi_dmul> 8015454: 4656 mov r6, sl 8015456: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 801545a: 9413 str r4, [sp, #76] @ 0x4c 801545c: e9dd 0106 ldrd r0, r1, [sp, #24] 8015460: f7f3 fb56 bl 8008b10 <__aeabi_d2iz> 8015464: 4605 mov r5, r0 8015466: f7f3 f839 bl 80084dc <__aeabi_i2d> 801546a: 4602 mov r2, r0 801546c: 460b mov r3, r1 801546e: e9dd 0106 ldrd r0, r1, [sp, #24] 8015472: f7f2 fee5 bl 8008240 <__aeabi_dsub> 8015476: 4602 mov r2, r0 8015478: 460b mov r3, r1 801547a: 3530 adds r5, #48 @ 0x30 801547c: f806 5b01 strb.w r5, [r6], #1 8015480: 42a6 cmp r6, r4 8015482: e9cd 2306 strd r2, r3, [sp, #24] 8015486: f04f 0200 mov.w r2, #0 801548a: d124 bne.n 80154d6 <_dtoa_r+0x62e> 801548c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8015490: 4bae ldr r3, [pc, #696] @ (801574c <_dtoa_r+0x8a4>) 8015492: f7f2 fed7 bl 8008244 <__adddf3> 8015496: 4602 mov r2, r0 8015498: 460b mov r3, r1 801549a: e9dd 0106 ldrd r0, r1, [sp, #24] 801549e: f7f3 fb17 bl 8008ad0 <__aeabi_dcmpgt> 80154a2: 2800 cmp r0, #0 80154a4: d163 bne.n 801556e <_dtoa_r+0x6c6> 80154a6: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 80154aa: 2000 movs r0, #0 80154ac: 49a7 ldr r1, [pc, #668] @ (801574c <_dtoa_r+0x8a4>) 80154ae: f7f2 fec7 bl 8008240 <__aeabi_dsub> 80154b2: 4602 mov r2, r0 80154b4: 460b mov r3, r1 80154b6: e9dd 0106 ldrd r0, r1, [sp, #24] 80154ba: f7f3 faeb bl 8008a94 <__aeabi_dcmplt> 80154be: 2800 cmp r0, #0 80154c0: f43f af14 beq.w 80152ec <_dtoa_r+0x444> 80154c4: 9e13 ldr r6, [sp, #76] @ 0x4c 80154c6: 1e73 subs r3, r6, #1 80154c8: 9313 str r3, [sp, #76] @ 0x4c 80154ca: f816 3c01 ldrb.w r3, [r6, #-1] 80154ce: 2b30 cmp r3, #48 @ 0x30 80154d0: d0f8 beq.n 80154c4 <_dtoa_r+0x61c> 80154d2: 4647 mov r7, r8 80154d4: e03b b.n 801554e <_dtoa_r+0x6a6> 80154d6: 4b9e ldr r3, [pc, #632] @ (8015750 <_dtoa_r+0x8a8>) 80154d8: f7f3 f86a bl 80085b0 <__aeabi_dmul> 80154dc: e9cd 0106 strd r0, r1, [sp, #24] 80154e0: e7bc b.n 801545c <_dtoa_r+0x5b4> 80154e2: 4656 mov r6, sl 80154e4: e9dd 4506 ldrd r4, r5, [sp, #24] 80154e8: e9dd 2304 ldrd r2, r3, [sp, #16] 80154ec: 4620 mov r0, r4 80154ee: 4629 mov r1, r5 80154f0: f7f3 f988 bl 8008804 <__aeabi_ddiv> 80154f4: f7f3 fb0c bl 8008b10 <__aeabi_d2iz> 80154f8: 4680 mov r8, r0 80154fa: f7f2 ffef bl 80084dc <__aeabi_i2d> 80154fe: e9dd 2304 ldrd r2, r3, [sp, #16] 8015502: f7f3 f855 bl 80085b0 <__aeabi_dmul> 8015506: 4602 mov r2, r0 8015508: 460b mov r3, r1 801550a: 4620 mov r0, r4 801550c: 4629 mov r1, r5 801550e: f7f2 fe97 bl 8008240 <__aeabi_dsub> 8015512: f108 0430 add.w r4, r8, #48 @ 0x30 8015516: 9d08 ldr r5, [sp, #32] 8015518: f806 4b01 strb.w r4, [r6], #1 801551c: eba6 040a sub.w r4, r6, sl 8015520: 42a5 cmp r5, r4 8015522: 4602 mov r2, r0 8015524: 460b mov r3, r1 8015526: d133 bne.n 8015590 <_dtoa_r+0x6e8> 8015528: f7f2 fe8c bl 8008244 <__adddf3> 801552c: e9dd 2304 ldrd r2, r3, [sp, #16] 8015530: 4604 mov r4, r0 8015532: 460d mov r5, r1 8015534: f7f3 facc bl 8008ad0 <__aeabi_dcmpgt> 8015538: b9c0 cbnz r0, 801556c <_dtoa_r+0x6c4> 801553a: e9dd 2304 ldrd r2, r3, [sp, #16] 801553e: 4620 mov r0, r4 8015540: 4629 mov r1, r5 8015542: f7f3 fa9d bl 8008a80 <__aeabi_dcmpeq> 8015546: b110 cbz r0, 801554e <_dtoa_r+0x6a6> 8015548: f018 0f01 tst.w r8, #1 801554c: d10e bne.n 801556c <_dtoa_r+0x6c4> 801554e: 4648 mov r0, r9 8015550: 9903 ldr r1, [sp, #12] 8015552: f000 fd73 bl 801603c <_Bfree> 8015556: 2300 movs r3, #0 8015558: 7033 strb r3, [r6, #0] 801555a: 9b22 ldr r3, [sp, #136] @ 0x88 801555c: 3701 adds r7, #1 801555e: 601f str r7, [r3, #0] 8015560: 9b24 ldr r3, [sp, #144] @ 0x90 8015562: 2b00 cmp r3, #0 8015564: f000 824b beq.w 80159fe <_dtoa_r+0xb56> 8015568: 601e str r6, [r3, #0] 801556a: e248 b.n 80159fe <_dtoa_r+0xb56> 801556c: 46b8 mov r8, r7 801556e: 4633 mov r3, r6 8015570: 461e mov r6, r3 8015572: f813 2d01 ldrb.w r2, [r3, #-1]! 8015576: 2a39 cmp r2, #57 @ 0x39 8015578: d106 bne.n 8015588 <_dtoa_r+0x6e0> 801557a: 459a cmp sl, r3 801557c: d1f8 bne.n 8015570 <_dtoa_r+0x6c8> 801557e: 2230 movs r2, #48 @ 0x30 8015580: f108 0801 add.w r8, r8, #1 8015584: f88a 2000 strb.w r2, [sl] 8015588: 781a ldrb r2, [r3, #0] 801558a: 3201 adds r2, #1 801558c: 701a strb r2, [r3, #0] 801558e: e7a0 b.n 80154d2 <_dtoa_r+0x62a> 8015590: 2200 movs r2, #0 8015592: 4b6f ldr r3, [pc, #444] @ (8015750 <_dtoa_r+0x8a8>) 8015594: f7f3 f80c bl 80085b0 <__aeabi_dmul> 8015598: 2200 movs r2, #0 801559a: 2300 movs r3, #0 801559c: 4604 mov r4, r0 801559e: 460d mov r5, r1 80155a0: f7f3 fa6e bl 8008a80 <__aeabi_dcmpeq> 80155a4: 2800 cmp r0, #0 80155a6: d09f beq.n 80154e8 <_dtoa_r+0x640> 80155a8: e7d1 b.n 801554e <_dtoa_r+0x6a6> 80155aa: 9a0b ldr r2, [sp, #44] @ 0x2c 80155ac: 2a00 cmp r2, #0 80155ae: f000 80ea beq.w 8015786 <_dtoa_r+0x8de> 80155b2: 9a20 ldr r2, [sp, #128] @ 0x80 80155b4: 2a01 cmp r2, #1 80155b6: f300 80cd bgt.w 8015754 <_dtoa_r+0x8ac> 80155ba: 9a12 ldr r2, [sp, #72] @ 0x48 80155bc: 2a00 cmp r2, #0 80155be: f000 80c1 beq.w 8015744 <_dtoa_r+0x89c> 80155c2: f203 4333 addw r3, r3, #1075 @ 0x433 80155c6: 9c0a ldr r4, [sp, #40] @ 0x28 80155c8: 9e04 ldr r6, [sp, #16] 80155ca: 9a04 ldr r2, [sp, #16] 80155cc: 2101 movs r1, #1 80155ce: 441a add r2, r3 80155d0: 9204 str r2, [sp, #16] 80155d2: 9a09 ldr r2, [sp, #36] @ 0x24 80155d4: 4648 mov r0, r9 80155d6: 441a add r2, r3 80155d8: 9209 str r2, [sp, #36] @ 0x24 80155da: f000 fde3 bl 80161a4 <__i2b> 80155de: 4605 mov r5, r0 80155e0: b166 cbz r6, 80155fc <_dtoa_r+0x754> 80155e2: 9b09 ldr r3, [sp, #36] @ 0x24 80155e4: 2b00 cmp r3, #0 80155e6: dd09 ble.n 80155fc <_dtoa_r+0x754> 80155e8: 42b3 cmp r3, r6 80155ea: bfa8 it ge 80155ec: 4633 movge r3, r6 80155ee: 9a04 ldr r2, [sp, #16] 80155f0: 1af6 subs r6, r6, r3 80155f2: 1ad2 subs r2, r2, r3 80155f4: 9204 str r2, [sp, #16] 80155f6: 9a09 ldr r2, [sp, #36] @ 0x24 80155f8: 1ad3 subs r3, r2, r3 80155fa: 9309 str r3, [sp, #36] @ 0x24 80155fc: 9b0a ldr r3, [sp, #40] @ 0x28 80155fe: b30b cbz r3, 8015644 <_dtoa_r+0x79c> 8015600: 9b0b ldr r3, [sp, #44] @ 0x2c 8015602: 2b00 cmp r3, #0 8015604: f000 80c6 beq.w 8015794 <_dtoa_r+0x8ec> 8015608: 2c00 cmp r4, #0 801560a: f000 80c0 beq.w 801578e <_dtoa_r+0x8e6> 801560e: 4629 mov r1, r5 8015610: 4622 mov r2, r4 8015612: 4648 mov r0, r9 8015614: f000 fe7e bl 8016314 <__pow5mult> 8015618: 9a03 ldr r2, [sp, #12] 801561a: 4601 mov r1, r0 801561c: 4605 mov r5, r0 801561e: 4648 mov r0, r9 8015620: f000 fdd6 bl 80161d0 <__multiply> 8015624: 9903 ldr r1, [sp, #12] 8015626: 4680 mov r8, r0 8015628: 4648 mov r0, r9 801562a: f000 fd07 bl 801603c <_Bfree> 801562e: 9b0a ldr r3, [sp, #40] @ 0x28 8015630: 1b1b subs r3, r3, r4 8015632: 930a str r3, [sp, #40] @ 0x28 8015634: f000 80b1 beq.w 801579a <_dtoa_r+0x8f2> 8015638: 4641 mov r1, r8 801563a: 9a0a ldr r2, [sp, #40] @ 0x28 801563c: 4648 mov r0, r9 801563e: f000 fe69 bl 8016314 <__pow5mult> 8015642: 9003 str r0, [sp, #12] 8015644: 2101 movs r1, #1 8015646: 4648 mov r0, r9 8015648: f000 fdac bl 80161a4 <__i2b> 801564c: 9b0e ldr r3, [sp, #56] @ 0x38 801564e: 4604 mov r4, r0 8015650: 2b00 cmp r3, #0 8015652: f000 81d8 beq.w 8015a06 <_dtoa_r+0xb5e> 8015656: 461a mov r2, r3 8015658: 4601 mov r1, r0 801565a: 4648 mov r0, r9 801565c: f000 fe5a bl 8016314 <__pow5mult> 8015660: 9b20 ldr r3, [sp, #128] @ 0x80 8015662: 4604 mov r4, r0 8015664: 2b01 cmp r3, #1 8015666: f300 809f bgt.w 80157a8 <_dtoa_r+0x900> 801566a: 9b06 ldr r3, [sp, #24] 801566c: 2b00 cmp r3, #0 801566e: f040 8097 bne.w 80157a0 <_dtoa_r+0x8f8> 8015672: 9b07 ldr r3, [sp, #28] 8015674: f3c3 0313 ubfx r3, r3, #0, #20 8015678: 2b00 cmp r3, #0 801567a: f040 8093 bne.w 80157a4 <_dtoa_r+0x8fc> 801567e: 9b07 ldr r3, [sp, #28] 8015680: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8015684: 0d1b lsrs r3, r3, #20 8015686: 051b lsls r3, r3, #20 8015688: b133 cbz r3, 8015698 <_dtoa_r+0x7f0> 801568a: 9b04 ldr r3, [sp, #16] 801568c: 3301 adds r3, #1 801568e: 9304 str r3, [sp, #16] 8015690: 9b09 ldr r3, [sp, #36] @ 0x24 8015692: 3301 adds r3, #1 8015694: 9309 str r3, [sp, #36] @ 0x24 8015696: 2301 movs r3, #1 8015698: 930a str r3, [sp, #40] @ 0x28 801569a: 9b0e ldr r3, [sp, #56] @ 0x38 801569c: 2b00 cmp r3, #0 801569e: f000 81b8 beq.w 8015a12 <_dtoa_r+0xb6a> 80156a2: 6923 ldr r3, [r4, #16] 80156a4: eb04 0383 add.w r3, r4, r3, lsl #2 80156a8: 6918 ldr r0, [r3, #16] 80156aa: f000 fd2f bl 801610c <__hi0bits> 80156ae: f1c0 0020 rsb r0, r0, #32 80156b2: 9b09 ldr r3, [sp, #36] @ 0x24 80156b4: 4418 add r0, r3 80156b6: f010 001f ands.w r0, r0, #31 80156ba: f000 8082 beq.w 80157c2 <_dtoa_r+0x91a> 80156be: f1c0 0320 rsb r3, r0, #32 80156c2: 2b04 cmp r3, #4 80156c4: dd73 ble.n 80157ae <_dtoa_r+0x906> 80156c6: 9b04 ldr r3, [sp, #16] 80156c8: f1c0 001c rsb r0, r0, #28 80156cc: 4403 add r3, r0 80156ce: 9304 str r3, [sp, #16] 80156d0: 9b09 ldr r3, [sp, #36] @ 0x24 80156d2: 4406 add r6, r0 80156d4: 4403 add r3, r0 80156d6: 9309 str r3, [sp, #36] @ 0x24 80156d8: 9b04 ldr r3, [sp, #16] 80156da: 2b00 cmp r3, #0 80156dc: dd05 ble.n 80156ea <_dtoa_r+0x842> 80156de: 461a mov r2, r3 80156e0: 4648 mov r0, r9 80156e2: 9903 ldr r1, [sp, #12] 80156e4: f000 fe70 bl 80163c8 <__lshift> 80156e8: 9003 str r0, [sp, #12] 80156ea: 9b09 ldr r3, [sp, #36] @ 0x24 80156ec: 2b00 cmp r3, #0 80156ee: dd05 ble.n 80156fc <_dtoa_r+0x854> 80156f0: 4621 mov r1, r4 80156f2: 461a mov r2, r3 80156f4: 4648 mov r0, r9 80156f6: f000 fe67 bl 80163c8 <__lshift> 80156fa: 4604 mov r4, r0 80156fc: 9b0f ldr r3, [sp, #60] @ 0x3c 80156fe: 2b00 cmp r3, #0 8015700: d061 beq.n 80157c6 <_dtoa_r+0x91e> 8015702: 4621 mov r1, r4 8015704: 9803 ldr r0, [sp, #12] 8015706: f000 fecb bl 80164a0 <__mcmp> 801570a: 2800 cmp r0, #0 801570c: da5b bge.n 80157c6 <_dtoa_r+0x91e> 801570e: 2300 movs r3, #0 8015710: 220a movs r2, #10 8015712: 4648 mov r0, r9 8015714: 9903 ldr r1, [sp, #12] 8015716: f000 fcb3 bl 8016080 <__multadd> 801571a: 9b0b ldr r3, [sp, #44] @ 0x2c 801571c: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 8015720: 9003 str r0, [sp, #12] 8015722: 2b00 cmp r3, #0 8015724: f000 8177 beq.w 8015a16 <_dtoa_r+0xb6e> 8015728: 4629 mov r1, r5 801572a: 2300 movs r3, #0 801572c: 220a movs r2, #10 801572e: 4648 mov r0, r9 8015730: f000 fca6 bl 8016080 <__multadd> 8015734: f1bb 0f00 cmp.w fp, #0 8015738: 4605 mov r5, r0 801573a: dc6f bgt.n 801581c <_dtoa_r+0x974> 801573c: 9b20 ldr r3, [sp, #128] @ 0x80 801573e: 2b02 cmp r3, #2 8015740: dc49 bgt.n 80157d6 <_dtoa_r+0x92e> 8015742: e06b b.n 801581c <_dtoa_r+0x974> 8015744: 9b14 ldr r3, [sp, #80] @ 0x50 8015746: f1c3 0336 rsb r3, r3, #54 @ 0x36 801574a: e73c b.n 80155c6 <_dtoa_r+0x71e> 801574c: 3fe00000 .word 0x3fe00000 8015750: 40240000 .word 0x40240000 8015754: 9b08 ldr r3, [sp, #32] 8015756: 1e5c subs r4, r3, #1 8015758: 9b0a ldr r3, [sp, #40] @ 0x28 801575a: 42a3 cmp r3, r4 801575c: db09 blt.n 8015772 <_dtoa_r+0x8ca> 801575e: 1b1c subs r4, r3, r4 8015760: 9b08 ldr r3, [sp, #32] 8015762: 2b00 cmp r3, #0 8015764: f6bf af30 bge.w 80155c8 <_dtoa_r+0x720> 8015768: 9b04 ldr r3, [sp, #16] 801576a: 9a08 ldr r2, [sp, #32] 801576c: 1a9e subs r6, r3, r2 801576e: 2300 movs r3, #0 8015770: e72b b.n 80155ca <_dtoa_r+0x722> 8015772: 9b0a ldr r3, [sp, #40] @ 0x28 8015774: 9a0e ldr r2, [sp, #56] @ 0x38 8015776: 1ae3 subs r3, r4, r3 8015778: 441a add r2, r3 801577a: 940a str r4, [sp, #40] @ 0x28 801577c: 9e04 ldr r6, [sp, #16] 801577e: 2400 movs r4, #0 8015780: 9b08 ldr r3, [sp, #32] 8015782: 920e str r2, [sp, #56] @ 0x38 8015784: e721 b.n 80155ca <_dtoa_r+0x722> 8015786: 9c0a ldr r4, [sp, #40] @ 0x28 8015788: 9e04 ldr r6, [sp, #16] 801578a: 9d0b ldr r5, [sp, #44] @ 0x2c 801578c: e728 b.n 80155e0 <_dtoa_r+0x738> 801578e: f8dd 800c ldr.w r8, [sp, #12] 8015792: e751 b.n 8015638 <_dtoa_r+0x790> 8015794: 9a0a ldr r2, [sp, #40] @ 0x28 8015796: 9903 ldr r1, [sp, #12] 8015798: e750 b.n 801563c <_dtoa_r+0x794> 801579a: f8cd 800c str.w r8, [sp, #12] 801579e: e751 b.n 8015644 <_dtoa_r+0x79c> 80157a0: 2300 movs r3, #0 80157a2: e779 b.n 8015698 <_dtoa_r+0x7f0> 80157a4: 9b06 ldr r3, [sp, #24] 80157a6: e777 b.n 8015698 <_dtoa_r+0x7f0> 80157a8: 2300 movs r3, #0 80157aa: 930a str r3, [sp, #40] @ 0x28 80157ac: e779 b.n 80156a2 <_dtoa_r+0x7fa> 80157ae: d093 beq.n 80156d8 <_dtoa_r+0x830> 80157b0: 9a04 ldr r2, [sp, #16] 80157b2: 331c adds r3, #28 80157b4: 441a add r2, r3 80157b6: 9204 str r2, [sp, #16] 80157b8: 9a09 ldr r2, [sp, #36] @ 0x24 80157ba: 441e add r6, r3 80157bc: 441a add r2, r3 80157be: 9209 str r2, [sp, #36] @ 0x24 80157c0: e78a b.n 80156d8 <_dtoa_r+0x830> 80157c2: 4603 mov r3, r0 80157c4: e7f4 b.n 80157b0 <_dtoa_r+0x908> 80157c6: 9b08 ldr r3, [sp, #32] 80157c8: 46b8 mov r8, r7 80157ca: 2b00 cmp r3, #0 80157cc: dc20 bgt.n 8015810 <_dtoa_r+0x968> 80157ce: 469b mov fp, r3 80157d0: 9b20 ldr r3, [sp, #128] @ 0x80 80157d2: 2b02 cmp r3, #2 80157d4: dd1e ble.n 8015814 <_dtoa_r+0x96c> 80157d6: f1bb 0f00 cmp.w fp, #0 80157da: f47f adb1 bne.w 8015340 <_dtoa_r+0x498> 80157de: 4621 mov r1, r4 80157e0: 465b mov r3, fp 80157e2: 2205 movs r2, #5 80157e4: 4648 mov r0, r9 80157e6: f000 fc4b bl 8016080 <__multadd> 80157ea: 4601 mov r1, r0 80157ec: 4604 mov r4, r0 80157ee: 9803 ldr r0, [sp, #12] 80157f0: f000 fe56 bl 80164a0 <__mcmp> 80157f4: 2800 cmp r0, #0 80157f6: f77f ada3 ble.w 8015340 <_dtoa_r+0x498> 80157fa: 4656 mov r6, sl 80157fc: 2331 movs r3, #49 @ 0x31 80157fe: f108 0801 add.w r8, r8, #1 8015802: f806 3b01 strb.w r3, [r6], #1 8015806: e59f b.n 8015348 <_dtoa_r+0x4a0> 8015808: 46b8 mov r8, r7 801580a: 9c08 ldr r4, [sp, #32] 801580c: 4625 mov r5, r4 801580e: e7f4 b.n 80157fa <_dtoa_r+0x952> 8015810: f8dd b020 ldr.w fp, [sp, #32] 8015814: 9b0b ldr r3, [sp, #44] @ 0x2c 8015816: 2b00 cmp r3, #0 8015818: f000 8101 beq.w 8015a1e <_dtoa_r+0xb76> 801581c: 2e00 cmp r6, #0 801581e: dd05 ble.n 801582c <_dtoa_r+0x984> 8015820: 4629 mov r1, r5 8015822: 4632 mov r2, r6 8015824: 4648 mov r0, r9 8015826: f000 fdcf bl 80163c8 <__lshift> 801582a: 4605 mov r5, r0 801582c: 9b0a ldr r3, [sp, #40] @ 0x28 801582e: 2b00 cmp r3, #0 8015830: d05c beq.n 80158ec <_dtoa_r+0xa44> 8015832: 4648 mov r0, r9 8015834: 6869 ldr r1, [r5, #4] 8015836: f000 fbc1 bl 8015fbc <_Balloc> 801583a: 4606 mov r6, r0 801583c: b928 cbnz r0, 801584a <_dtoa_r+0x9a2> 801583e: 4602 mov r2, r0 8015840: f240 21ef movw r1, #751 @ 0x2ef 8015844: 4b80 ldr r3, [pc, #512] @ (8015a48 <_dtoa_r+0xba0>) 8015846: f7ff bb43 b.w 8014ed0 <_dtoa_r+0x28> 801584a: 692a ldr r2, [r5, #16] 801584c: f105 010c add.w r1, r5, #12 8015850: 3202 adds r2, #2 8015852: 0092 lsls r2, r2, #2 8015854: 300c adds r0, #12 8015856: f7ff fa71 bl 8014d3c 801585a: 2201 movs r2, #1 801585c: 4631 mov r1, r6 801585e: 4648 mov r0, r9 8015860: f000 fdb2 bl 80163c8 <__lshift> 8015864: 462f mov r7, r5 8015866: 4605 mov r5, r0 8015868: f10a 0301 add.w r3, sl, #1 801586c: 9304 str r3, [sp, #16] 801586e: eb0a 030b add.w r3, sl, fp 8015872: 930a str r3, [sp, #40] @ 0x28 8015874: 9b06 ldr r3, [sp, #24] 8015876: f003 0301 and.w r3, r3, #1 801587a: 9309 str r3, [sp, #36] @ 0x24 801587c: 9b04 ldr r3, [sp, #16] 801587e: 4621 mov r1, r4 8015880: 9803 ldr r0, [sp, #12] 8015882: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff 8015886: f7ff fa85 bl 8014d94 801588a: 4603 mov r3, r0 801588c: 4639 mov r1, r7 801588e: 3330 adds r3, #48 @ 0x30 8015890: 9006 str r0, [sp, #24] 8015892: 9803 ldr r0, [sp, #12] 8015894: 930b str r3, [sp, #44] @ 0x2c 8015896: f000 fe03 bl 80164a0 <__mcmp> 801589a: 462a mov r2, r5 801589c: 9008 str r0, [sp, #32] 801589e: 4621 mov r1, r4 80158a0: 4648 mov r0, r9 80158a2: f000 fe19 bl 80164d8 <__mdiff> 80158a6: 68c2 ldr r2, [r0, #12] 80158a8: 4606 mov r6, r0 80158aa: 9b0b ldr r3, [sp, #44] @ 0x2c 80158ac: bb02 cbnz r2, 80158f0 <_dtoa_r+0xa48> 80158ae: 4601 mov r1, r0 80158b0: 9803 ldr r0, [sp, #12] 80158b2: f000 fdf5 bl 80164a0 <__mcmp> 80158b6: 4602 mov r2, r0 80158b8: 9b0b ldr r3, [sp, #44] @ 0x2c 80158ba: 4631 mov r1, r6 80158bc: 4648 mov r0, r9 80158be: e9cd 320b strd r3, r2, [sp, #44] @ 0x2c 80158c2: f000 fbbb bl 801603c <_Bfree> 80158c6: 9b20 ldr r3, [sp, #128] @ 0x80 80158c8: 9a0c ldr r2, [sp, #48] @ 0x30 80158ca: 9e04 ldr r6, [sp, #16] 80158cc: ea42 0103 orr.w r1, r2, r3 80158d0: 9b09 ldr r3, [sp, #36] @ 0x24 80158d2: 4319 orrs r1, r3 80158d4: 9b0b ldr r3, [sp, #44] @ 0x2c 80158d6: d10d bne.n 80158f4 <_dtoa_r+0xa4c> 80158d8: 2b39 cmp r3, #57 @ 0x39 80158da: d027 beq.n 801592c <_dtoa_r+0xa84> 80158dc: 9a08 ldr r2, [sp, #32] 80158de: 2a00 cmp r2, #0 80158e0: dd01 ble.n 80158e6 <_dtoa_r+0xa3e> 80158e2: 9b06 ldr r3, [sp, #24] 80158e4: 3331 adds r3, #49 @ 0x31 80158e6: f88b 3000 strb.w r3, [fp] 80158ea: e52e b.n 801534a <_dtoa_r+0x4a2> 80158ec: 4628 mov r0, r5 80158ee: e7b9 b.n 8015864 <_dtoa_r+0x9bc> 80158f0: 2201 movs r2, #1 80158f2: e7e2 b.n 80158ba <_dtoa_r+0xa12> 80158f4: 9908 ldr r1, [sp, #32] 80158f6: 2900 cmp r1, #0 80158f8: db04 blt.n 8015904 <_dtoa_r+0xa5c> 80158fa: 9820 ldr r0, [sp, #128] @ 0x80 80158fc: 4301 orrs r1, r0 80158fe: 9809 ldr r0, [sp, #36] @ 0x24 8015900: 4301 orrs r1, r0 8015902: d120 bne.n 8015946 <_dtoa_r+0xa9e> 8015904: 2a00 cmp r2, #0 8015906: ddee ble.n 80158e6 <_dtoa_r+0xa3e> 8015908: 2201 movs r2, #1 801590a: 9903 ldr r1, [sp, #12] 801590c: 4648 mov r0, r9 801590e: 9304 str r3, [sp, #16] 8015910: f000 fd5a bl 80163c8 <__lshift> 8015914: 4621 mov r1, r4 8015916: 9003 str r0, [sp, #12] 8015918: f000 fdc2 bl 80164a0 <__mcmp> 801591c: 2800 cmp r0, #0 801591e: 9b04 ldr r3, [sp, #16] 8015920: dc02 bgt.n 8015928 <_dtoa_r+0xa80> 8015922: d1e0 bne.n 80158e6 <_dtoa_r+0xa3e> 8015924: 07da lsls r2, r3, #31 8015926: d5de bpl.n 80158e6 <_dtoa_r+0xa3e> 8015928: 2b39 cmp r3, #57 @ 0x39 801592a: d1da bne.n 80158e2 <_dtoa_r+0xa3a> 801592c: 2339 movs r3, #57 @ 0x39 801592e: f88b 3000 strb.w r3, [fp] 8015932: 4633 mov r3, r6 8015934: 461e mov r6, r3 8015936: f816 2c01 ldrb.w r2, [r6, #-1] 801593a: 3b01 subs r3, #1 801593c: 2a39 cmp r2, #57 @ 0x39 801593e: d04e beq.n 80159de <_dtoa_r+0xb36> 8015940: 3201 adds r2, #1 8015942: 701a strb r2, [r3, #0] 8015944: e501 b.n 801534a <_dtoa_r+0x4a2> 8015946: 2a00 cmp r2, #0 8015948: dd03 ble.n 8015952 <_dtoa_r+0xaaa> 801594a: 2b39 cmp r3, #57 @ 0x39 801594c: d0ee beq.n 801592c <_dtoa_r+0xa84> 801594e: 3301 adds r3, #1 8015950: e7c9 b.n 80158e6 <_dtoa_r+0xa3e> 8015952: 9a04 ldr r2, [sp, #16] 8015954: 990a ldr r1, [sp, #40] @ 0x28 8015956: f802 3c01 strb.w r3, [r2, #-1] 801595a: 428a cmp r2, r1 801595c: d028 beq.n 80159b0 <_dtoa_r+0xb08> 801595e: 2300 movs r3, #0 8015960: 220a movs r2, #10 8015962: 9903 ldr r1, [sp, #12] 8015964: 4648 mov r0, r9 8015966: f000 fb8b bl 8016080 <__multadd> 801596a: 42af cmp r7, r5 801596c: 9003 str r0, [sp, #12] 801596e: f04f 0300 mov.w r3, #0 8015972: f04f 020a mov.w r2, #10 8015976: 4639 mov r1, r7 8015978: 4648 mov r0, r9 801597a: d107 bne.n 801598c <_dtoa_r+0xae4> 801597c: f000 fb80 bl 8016080 <__multadd> 8015980: 4607 mov r7, r0 8015982: 4605 mov r5, r0 8015984: 9b04 ldr r3, [sp, #16] 8015986: 3301 adds r3, #1 8015988: 9304 str r3, [sp, #16] 801598a: e777 b.n 801587c <_dtoa_r+0x9d4> 801598c: f000 fb78 bl 8016080 <__multadd> 8015990: 4629 mov r1, r5 8015992: 4607 mov r7, r0 8015994: 2300 movs r3, #0 8015996: 220a movs r2, #10 8015998: 4648 mov r0, r9 801599a: f000 fb71 bl 8016080 <__multadd> 801599e: 4605 mov r5, r0 80159a0: e7f0 b.n 8015984 <_dtoa_r+0xadc> 80159a2: f1bb 0f00 cmp.w fp, #0 80159a6: bfcc ite gt 80159a8: 465e movgt r6, fp 80159aa: 2601 movle r6, #1 80159ac: 2700 movs r7, #0 80159ae: 4456 add r6, sl 80159b0: 2201 movs r2, #1 80159b2: 9903 ldr r1, [sp, #12] 80159b4: 4648 mov r0, r9 80159b6: 9304 str r3, [sp, #16] 80159b8: f000 fd06 bl 80163c8 <__lshift> 80159bc: 4621 mov r1, r4 80159be: 9003 str r0, [sp, #12] 80159c0: f000 fd6e bl 80164a0 <__mcmp> 80159c4: 2800 cmp r0, #0 80159c6: dcb4 bgt.n 8015932 <_dtoa_r+0xa8a> 80159c8: d102 bne.n 80159d0 <_dtoa_r+0xb28> 80159ca: 9b04 ldr r3, [sp, #16] 80159cc: 07db lsls r3, r3, #31 80159ce: d4b0 bmi.n 8015932 <_dtoa_r+0xa8a> 80159d0: 4633 mov r3, r6 80159d2: 461e mov r6, r3 80159d4: f813 2d01 ldrb.w r2, [r3, #-1]! 80159d8: 2a30 cmp r2, #48 @ 0x30 80159da: d0fa beq.n 80159d2 <_dtoa_r+0xb2a> 80159dc: e4b5 b.n 801534a <_dtoa_r+0x4a2> 80159de: 459a cmp sl, r3 80159e0: d1a8 bne.n 8015934 <_dtoa_r+0xa8c> 80159e2: 2331 movs r3, #49 @ 0x31 80159e4: f108 0801 add.w r8, r8, #1 80159e8: f88a 3000 strb.w r3, [sl] 80159ec: e4ad b.n 801534a <_dtoa_r+0x4a2> 80159ee: 9b24 ldr r3, [sp, #144] @ 0x90 80159f0: f8df a058 ldr.w sl, [pc, #88] @ 8015a4c <_dtoa_r+0xba4> 80159f4: b11b cbz r3, 80159fe <_dtoa_r+0xb56> 80159f6: f10a 0308 add.w r3, sl, #8 80159fa: 9a24 ldr r2, [sp, #144] @ 0x90 80159fc: 6013 str r3, [r2, #0] 80159fe: 4650 mov r0, sl 8015a00: b017 add sp, #92 @ 0x5c 8015a02: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8015a06: 9b20 ldr r3, [sp, #128] @ 0x80 8015a08: 2b01 cmp r3, #1 8015a0a: f77f ae2e ble.w 801566a <_dtoa_r+0x7c2> 8015a0e: 9b0e ldr r3, [sp, #56] @ 0x38 8015a10: 930a str r3, [sp, #40] @ 0x28 8015a12: 2001 movs r0, #1 8015a14: e64d b.n 80156b2 <_dtoa_r+0x80a> 8015a16: f1bb 0f00 cmp.w fp, #0 8015a1a: f77f aed9 ble.w 80157d0 <_dtoa_r+0x928> 8015a1e: 4656 mov r6, sl 8015a20: 4621 mov r1, r4 8015a22: 9803 ldr r0, [sp, #12] 8015a24: f7ff f9b6 bl 8014d94 8015a28: f100 0330 add.w r3, r0, #48 @ 0x30 8015a2c: f806 3b01 strb.w r3, [r6], #1 8015a30: eba6 020a sub.w r2, r6, sl 8015a34: 4593 cmp fp, r2 8015a36: ddb4 ble.n 80159a2 <_dtoa_r+0xafa> 8015a38: 2300 movs r3, #0 8015a3a: 220a movs r2, #10 8015a3c: 4648 mov r0, r9 8015a3e: 9903 ldr r1, [sp, #12] 8015a40: f000 fb1e bl 8016080 <__multadd> 8015a44: 9003 str r0, [sp, #12] 8015a46: e7eb b.n 8015a20 <_dtoa_r+0xb78> 8015a48: 08017a40 .word 0x08017a40 8015a4c: 080179c4 .word 0x080179c4 08015a50 <__ssputs_r>: 8015a50: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8015a54: 461f mov r7, r3 8015a56: 688e ldr r6, [r1, #8] 8015a58: 4682 mov sl, r0 8015a5a: 42be cmp r6, r7 8015a5c: 460c mov r4, r1 8015a5e: 4690 mov r8, r2 8015a60: 680b ldr r3, [r1, #0] 8015a62: d82d bhi.n 8015ac0 <__ssputs_r+0x70> 8015a64: f9b1 200c ldrsh.w r2, [r1, #12] 8015a68: f412 6f90 tst.w r2, #1152 @ 0x480 8015a6c: d026 beq.n 8015abc <__ssputs_r+0x6c> 8015a6e: 6965 ldr r5, [r4, #20] 8015a70: 6909 ldr r1, [r1, #16] 8015a72: eb05 0545 add.w r5, r5, r5, lsl #1 8015a76: eba3 0901 sub.w r9, r3, r1 8015a7a: eb05 75d5 add.w r5, r5, r5, lsr #31 8015a7e: 1c7b adds r3, r7, #1 8015a80: 444b add r3, r9 8015a82: 106d asrs r5, r5, #1 8015a84: 429d cmp r5, r3 8015a86: bf38 it cc 8015a88: 461d movcc r5, r3 8015a8a: 0553 lsls r3, r2, #21 8015a8c: d527 bpl.n 8015ade <__ssputs_r+0x8e> 8015a8e: 4629 mov r1, r5 8015a90: f000 f960 bl 8015d54 <_malloc_r> 8015a94: 4606 mov r6, r0 8015a96: b360 cbz r0, 8015af2 <__ssputs_r+0xa2> 8015a98: 464a mov r2, r9 8015a9a: 6921 ldr r1, [r4, #16] 8015a9c: f7ff f94e bl 8014d3c 8015aa0: 89a3 ldrh r3, [r4, #12] 8015aa2: f423 6390 bic.w r3, r3, #1152 @ 0x480 8015aa6: f043 0380 orr.w r3, r3, #128 @ 0x80 8015aaa: 81a3 strh r3, [r4, #12] 8015aac: 6126 str r6, [r4, #16] 8015aae: 444e add r6, r9 8015ab0: 6026 str r6, [r4, #0] 8015ab2: 463e mov r6, r7 8015ab4: 6165 str r5, [r4, #20] 8015ab6: eba5 0509 sub.w r5, r5, r9 8015aba: 60a5 str r5, [r4, #8] 8015abc: 42be cmp r6, r7 8015abe: d900 bls.n 8015ac2 <__ssputs_r+0x72> 8015ac0: 463e mov r6, r7 8015ac2: 4632 mov r2, r6 8015ac4: 4641 mov r1, r8 8015ac6: 6820 ldr r0, [r4, #0] 8015ac8: f000 fe76 bl 80167b8 8015acc: 2000 movs r0, #0 8015ace: 68a3 ldr r3, [r4, #8] 8015ad0: 1b9b subs r3, r3, r6 8015ad2: 60a3 str r3, [r4, #8] 8015ad4: 6823 ldr r3, [r4, #0] 8015ad6: 4433 add r3, r6 8015ad8: 6023 str r3, [r4, #0] 8015ada: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8015ade: 462a mov r2, r5 8015ae0: f000 fe3c bl 801675c <_realloc_r> 8015ae4: 4606 mov r6, r0 8015ae6: 2800 cmp r0, #0 8015ae8: d1e0 bne.n 8015aac <__ssputs_r+0x5c> 8015aea: 4650 mov r0, sl 8015aec: 6921 ldr r1, [r4, #16] 8015aee: f000 feef bl 80168d0 <_free_r> 8015af2: 230c movs r3, #12 8015af4: f8ca 3000 str.w r3, [sl] 8015af8: 89a3 ldrh r3, [r4, #12] 8015afa: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015afe: f043 0340 orr.w r3, r3, #64 @ 0x40 8015b02: 81a3 strh r3, [r4, #12] 8015b04: e7e9 b.n 8015ada <__ssputs_r+0x8a> ... 08015b08 <_svfiprintf_r>: 8015b08: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8015b0c: 4698 mov r8, r3 8015b0e: 898b ldrh r3, [r1, #12] 8015b10: 4607 mov r7, r0 8015b12: 061b lsls r3, r3, #24 8015b14: 460d mov r5, r1 8015b16: 4614 mov r4, r2 8015b18: b09d sub sp, #116 @ 0x74 8015b1a: d510 bpl.n 8015b3e <_svfiprintf_r+0x36> 8015b1c: 690b ldr r3, [r1, #16] 8015b1e: b973 cbnz r3, 8015b3e <_svfiprintf_r+0x36> 8015b20: 2140 movs r1, #64 @ 0x40 8015b22: f000 f917 bl 8015d54 <_malloc_r> 8015b26: 6028 str r0, [r5, #0] 8015b28: 6128 str r0, [r5, #16] 8015b2a: b930 cbnz r0, 8015b3a <_svfiprintf_r+0x32> 8015b2c: 230c movs r3, #12 8015b2e: 603b str r3, [r7, #0] 8015b30: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015b34: b01d add sp, #116 @ 0x74 8015b36: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8015b3a: 2340 movs r3, #64 @ 0x40 8015b3c: 616b str r3, [r5, #20] 8015b3e: 2300 movs r3, #0 8015b40: 9309 str r3, [sp, #36] @ 0x24 8015b42: 2320 movs r3, #32 8015b44: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8015b48: 2330 movs r3, #48 @ 0x30 8015b4a: f04f 0901 mov.w r9, #1 8015b4e: f8cd 800c str.w r8, [sp, #12] 8015b52: f8df 8198 ldr.w r8, [pc, #408] @ 8015cec <_svfiprintf_r+0x1e4> 8015b56: f88d 302a strb.w r3, [sp, #42] @ 0x2a 8015b5a: 4623 mov r3, r4 8015b5c: 469a mov sl, r3 8015b5e: f813 2b01 ldrb.w r2, [r3], #1 8015b62: b10a cbz r2, 8015b68 <_svfiprintf_r+0x60> 8015b64: 2a25 cmp r2, #37 @ 0x25 8015b66: d1f9 bne.n 8015b5c <_svfiprintf_r+0x54> 8015b68: ebba 0b04 subs.w fp, sl, r4 8015b6c: d00b beq.n 8015b86 <_svfiprintf_r+0x7e> 8015b6e: 465b mov r3, fp 8015b70: 4622 mov r2, r4 8015b72: 4629 mov r1, r5 8015b74: 4638 mov r0, r7 8015b76: f7ff ff6b bl 8015a50 <__ssputs_r> 8015b7a: 3001 adds r0, #1 8015b7c: f000 80a7 beq.w 8015cce <_svfiprintf_r+0x1c6> 8015b80: 9a09 ldr r2, [sp, #36] @ 0x24 8015b82: 445a add r2, fp 8015b84: 9209 str r2, [sp, #36] @ 0x24 8015b86: f89a 3000 ldrb.w r3, [sl] 8015b8a: 2b00 cmp r3, #0 8015b8c: f000 809f beq.w 8015cce <_svfiprintf_r+0x1c6> 8015b90: 2300 movs r3, #0 8015b92: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8015b96: e9cd 2305 strd r2, r3, [sp, #20] 8015b9a: f10a 0a01 add.w sl, sl, #1 8015b9e: 9304 str r3, [sp, #16] 8015ba0: 9307 str r3, [sp, #28] 8015ba2: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8015ba6: 931a str r3, [sp, #104] @ 0x68 8015ba8: 4654 mov r4, sl 8015baa: 2205 movs r2, #5 8015bac: f814 1b01 ldrb.w r1, [r4], #1 8015bb0: 484e ldr r0, [pc, #312] @ (8015cec <_svfiprintf_r+0x1e4>) 8015bb2: f7ff f8b5 bl 8014d20 8015bb6: 9a04 ldr r2, [sp, #16] 8015bb8: b9d8 cbnz r0, 8015bf2 <_svfiprintf_r+0xea> 8015bba: 06d0 lsls r0, r2, #27 8015bbc: bf44 itt mi 8015bbe: 2320 movmi r3, #32 8015bc0: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8015bc4: 0711 lsls r1, r2, #28 8015bc6: bf44 itt mi 8015bc8: 232b movmi r3, #43 @ 0x2b 8015bca: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8015bce: f89a 3000 ldrb.w r3, [sl] 8015bd2: 2b2a cmp r3, #42 @ 0x2a 8015bd4: d015 beq.n 8015c02 <_svfiprintf_r+0xfa> 8015bd6: 4654 mov r4, sl 8015bd8: 2000 movs r0, #0 8015bda: f04f 0c0a mov.w ip, #10 8015bde: 9a07 ldr r2, [sp, #28] 8015be0: 4621 mov r1, r4 8015be2: f811 3b01 ldrb.w r3, [r1], #1 8015be6: 3b30 subs r3, #48 @ 0x30 8015be8: 2b09 cmp r3, #9 8015bea: d94b bls.n 8015c84 <_svfiprintf_r+0x17c> 8015bec: b1b0 cbz r0, 8015c1c <_svfiprintf_r+0x114> 8015bee: 9207 str r2, [sp, #28] 8015bf0: e014 b.n 8015c1c <_svfiprintf_r+0x114> 8015bf2: eba0 0308 sub.w r3, r0, r8 8015bf6: fa09 f303 lsl.w r3, r9, r3 8015bfa: 4313 orrs r3, r2 8015bfc: 46a2 mov sl, r4 8015bfe: 9304 str r3, [sp, #16] 8015c00: e7d2 b.n 8015ba8 <_svfiprintf_r+0xa0> 8015c02: 9b03 ldr r3, [sp, #12] 8015c04: 1d19 adds r1, r3, #4 8015c06: 681b ldr r3, [r3, #0] 8015c08: 9103 str r1, [sp, #12] 8015c0a: 2b00 cmp r3, #0 8015c0c: bfbb ittet lt 8015c0e: 425b neglt r3, r3 8015c10: f042 0202 orrlt.w r2, r2, #2 8015c14: 9307 strge r3, [sp, #28] 8015c16: 9307 strlt r3, [sp, #28] 8015c18: bfb8 it lt 8015c1a: 9204 strlt r2, [sp, #16] 8015c1c: 7823 ldrb r3, [r4, #0] 8015c1e: 2b2e cmp r3, #46 @ 0x2e 8015c20: d10a bne.n 8015c38 <_svfiprintf_r+0x130> 8015c22: 7863 ldrb r3, [r4, #1] 8015c24: 2b2a cmp r3, #42 @ 0x2a 8015c26: d132 bne.n 8015c8e <_svfiprintf_r+0x186> 8015c28: 9b03 ldr r3, [sp, #12] 8015c2a: 3402 adds r4, #2 8015c2c: 1d1a adds r2, r3, #4 8015c2e: 681b ldr r3, [r3, #0] 8015c30: 9203 str r2, [sp, #12] 8015c32: ea43 73e3 orr.w r3, r3, r3, asr #31 8015c36: 9305 str r3, [sp, #20] 8015c38: f8df a0b4 ldr.w sl, [pc, #180] @ 8015cf0 <_svfiprintf_r+0x1e8> 8015c3c: 2203 movs r2, #3 8015c3e: 4650 mov r0, sl 8015c40: 7821 ldrb r1, [r4, #0] 8015c42: f7ff f86d bl 8014d20 8015c46: b138 cbz r0, 8015c58 <_svfiprintf_r+0x150> 8015c48: 2240 movs r2, #64 @ 0x40 8015c4a: 9b04 ldr r3, [sp, #16] 8015c4c: eba0 000a sub.w r0, r0, sl 8015c50: 4082 lsls r2, r0 8015c52: 4313 orrs r3, r2 8015c54: 3401 adds r4, #1 8015c56: 9304 str r3, [sp, #16] 8015c58: f814 1b01 ldrb.w r1, [r4], #1 8015c5c: 2206 movs r2, #6 8015c5e: 4825 ldr r0, [pc, #148] @ (8015cf4 <_svfiprintf_r+0x1ec>) 8015c60: f88d 1028 strb.w r1, [sp, #40] @ 0x28 8015c64: f7ff f85c bl 8014d20 8015c68: 2800 cmp r0, #0 8015c6a: d036 beq.n 8015cda <_svfiprintf_r+0x1d2> 8015c6c: 4b22 ldr r3, [pc, #136] @ (8015cf8 <_svfiprintf_r+0x1f0>) 8015c6e: bb1b cbnz r3, 8015cb8 <_svfiprintf_r+0x1b0> 8015c70: 9b03 ldr r3, [sp, #12] 8015c72: 3307 adds r3, #7 8015c74: f023 0307 bic.w r3, r3, #7 8015c78: 3308 adds r3, #8 8015c7a: 9303 str r3, [sp, #12] 8015c7c: 9b09 ldr r3, [sp, #36] @ 0x24 8015c7e: 4433 add r3, r6 8015c80: 9309 str r3, [sp, #36] @ 0x24 8015c82: e76a b.n 8015b5a <_svfiprintf_r+0x52> 8015c84: 460c mov r4, r1 8015c86: 2001 movs r0, #1 8015c88: fb0c 3202 mla r2, ip, r2, r3 8015c8c: e7a8 b.n 8015be0 <_svfiprintf_r+0xd8> 8015c8e: 2300 movs r3, #0 8015c90: f04f 0c0a mov.w ip, #10 8015c94: 4619 mov r1, r3 8015c96: 3401 adds r4, #1 8015c98: 9305 str r3, [sp, #20] 8015c9a: 4620 mov r0, r4 8015c9c: f810 2b01 ldrb.w r2, [r0], #1 8015ca0: 3a30 subs r2, #48 @ 0x30 8015ca2: 2a09 cmp r2, #9 8015ca4: d903 bls.n 8015cae <_svfiprintf_r+0x1a6> 8015ca6: 2b00 cmp r3, #0 8015ca8: d0c6 beq.n 8015c38 <_svfiprintf_r+0x130> 8015caa: 9105 str r1, [sp, #20] 8015cac: e7c4 b.n 8015c38 <_svfiprintf_r+0x130> 8015cae: 4604 mov r4, r0 8015cb0: 2301 movs r3, #1 8015cb2: fb0c 2101 mla r1, ip, r1, r2 8015cb6: e7f0 b.n 8015c9a <_svfiprintf_r+0x192> 8015cb8: ab03 add r3, sp, #12 8015cba: 9300 str r3, [sp, #0] 8015cbc: 462a mov r2, r5 8015cbe: 4638 mov r0, r7 8015cc0: 4b0e ldr r3, [pc, #56] @ (8015cfc <_svfiprintf_r+0x1f4>) 8015cc2: a904 add r1, sp, #16 8015cc4: f7fe fb38 bl 8014338 <_printf_float> 8015cc8: 1c42 adds r2, r0, #1 8015cca: 4606 mov r6, r0 8015ccc: d1d6 bne.n 8015c7c <_svfiprintf_r+0x174> 8015cce: 89ab ldrh r3, [r5, #12] 8015cd0: 065b lsls r3, r3, #25 8015cd2: f53f af2d bmi.w 8015b30 <_svfiprintf_r+0x28> 8015cd6: 9809 ldr r0, [sp, #36] @ 0x24 8015cd8: e72c b.n 8015b34 <_svfiprintf_r+0x2c> 8015cda: ab03 add r3, sp, #12 8015cdc: 9300 str r3, [sp, #0] 8015cde: 462a mov r2, r5 8015ce0: 4638 mov r0, r7 8015ce2: 4b06 ldr r3, [pc, #24] @ (8015cfc <_svfiprintf_r+0x1f4>) 8015ce4: a904 add r1, sp, #16 8015ce6: f7fe fdc5 bl 8014874 <_printf_i> 8015cea: e7ed b.n 8015cc8 <_svfiprintf_r+0x1c0> 8015cec: 08017a51 .word 0x08017a51 8015cf0: 08017a57 .word 0x08017a57 8015cf4: 08017a5b .word 0x08017a5b 8015cf8: 08014339 .word 0x08014339 8015cfc: 08015a51 .word 0x08015a51 08015d00 : 8015d00: 4b02 ldr r3, [pc, #8] @ (8015d0c ) 8015d02: 4601 mov r1, r0 8015d04: 6818 ldr r0, [r3, #0] 8015d06: f000 b825 b.w 8015d54 <_malloc_r> 8015d0a: bf00 nop 8015d0c: 2000009c .word 0x2000009c 08015d10 : 8015d10: b570 push {r4, r5, r6, lr} 8015d12: 4e0f ldr r6, [pc, #60] @ (8015d50 ) 8015d14: 460c mov r4, r1 8015d16: 6831 ldr r1, [r6, #0] 8015d18: 4605 mov r5, r0 8015d1a: b911 cbnz r1, 8015d22 8015d1c: f000 fd8a bl 8016834 <_sbrk_r> 8015d20: 6030 str r0, [r6, #0] 8015d22: 4621 mov r1, r4 8015d24: 4628 mov r0, r5 8015d26: f000 fd85 bl 8016834 <_sbrk_r> 8015d2a: 1c43 adds r3, r0, #1 8015d2c: d103 bne.n 8015d36 8015d2e: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 8015d32: 4620 mov r0, r4 8015d34: bd70 pop {r4, r5, r6, pc} 8015d36: 1cc4 adds r4, r0, #3 8015d38: f024 0403 bic.w r4, r4, #3 8015d3c: 42a0 cmp r0, r4 8015d3e: d0f8 beq.n 8015d32 8015d40: 1a21 subs r1, r4, r0 8015d42: 4628 mov r0, r5 8015d44: f000 fd76 bl 8016834 <_sbrk_r> 8015d48: 3001 adds r0, #1 8015d4a: d1f2 bne.n 8015d32 8015d4c: e7ef b.n 8015d2e 8015d4e: bf00 nop 8015d50: 200015cc .word 0x200015cc 08015d54 <_malloc_r>: 8015d54: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8015d58: 1ccd adds r5, r1, #3 8015d5a: f025 0503 bic.w r5, r5, #3 8015d5e: 3508 adds r5, #8 8015d60: 2d0c cmp r5, #12 8015d62: bf38 it cc 8015d64: 250c movcc r5, #12 8015d66: 2d00 cmp r5, #0 8015d68: 4606 mov r6, r0 8015d6a: db01 blt.n 8015d70 <_malloc_r+0x1c> 8015d6c: 42a9 cmp r1, r5 8015d6e: d904 bls.n 8015d7a <_malloc_r+0x26> 8015d70: 230c movs r3, #12 8015d72: 6033 str r3, [r6, #0] 8015d74: 2000 movs r0, #0 8015d76: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8015d7a: f8df 80d4 ldr.w r8, [pc, #212] @ 8015e50 <_malloc_r+0xfc> 8015d7e: f000 f911 bl 8015fa4 <__malloc_lock> 8015d82: f8d8 3000 ldr.w r3, [r8] 8015d86: 461c mov r4, r3 8015d88: bb44 cbnz r4, 8015ddc <_malloc_r+0x88> 8015d8a: 4629 mov r1, r5 8015d8c: 4630 mov r0, r6 8015d8e: f7ff ffbf bl 8015d10 8015d92: 1c43 adds r3, r0, #1 8015d94: 4604 mov r4, r0 8015d96: d158 bne.n 8015e4a <_malloc_r+0xf6> 8015d98: f8d8 4000 ldr.w r4, [r8] 8015d9c: 4627 mov r7, r4 8015d9e: 2f00 cmp r7, #0 8015da0: d143 bne.n 8015e2a <_malloc_r+0xd6> 8015da2: 2c00 cmp r4, #0 8015da4: d04b beq.n 8015e3e <_malloc_r+0xea> 8015da6: 6823 ldr r3, [r4, #0] 8015da8: 4639 mov r1, r7 8015daa: 4630 mov r0, r6 8015dac: eb04 0903 add.w r9, r4, r3 8015db0: f000 fd40 bl 8016834 <_sbrk_r> 8015db4: 4581 cmp r9, r0 8015db6: d142 bne.n 8015e3e <_malloc_r+0xea> 8015db8: 6821 ldr r1, [r4, #0] 8015dba: 4630 mov r0, r6 8015dbc: 1a6d subs r5, r5, r1 8015dbe: 4629 mov r1, r5 8015dc0: f7ff ffa6 bl 8015d10 8015dc4: 3001 adds r0, #1 8015dc6: d03a beq.n 8015e3e <_malloc_r+0xea> 8015dc8: 6823 ldr r3, [r4, #0] 8015dca: 442b add r3, r5 8015dcc: 6023 str r3, [r4, #0] 8015dce: f8d8 3000 ldr.w r3, [r8] 8015dd2: 685a ldr r2, [r3, #4] 8015dd4: bb62 cbnz r2, 8015e30 <_malloc_r+0xdc> 8015dd6: f8c8 7000 str.w r7, [r8] 8015dda: e00f b.n 8015dfc <_malloc_r+0xa8> 8015ddc: 6822 ldr r2, [r4, #0] 8015dde: 1b52 subs r2, r2, r5 8015de0: d420 bmi.n 8015e24 <_malloc_r+0xd0> 8015de2: 2a0b cmp r2, #11 8015de4: d917 bls.n 8015e16 <_malloc_r+0xc2> 8015de6: 1961 adds r1, r4, r5 8015de8: 42a3 cmp r3, r4 8015dea: 6025 str r5, [r4, #0] 8015dec: bf18 it ne 8015dee: 6059 strne r1, [r3, #4] 8015df0: 6863 ldr r3, [r4, #4] 8015df2: bf08 it eq 8015df4: f8c8 1000 streq.w r1, [r8] 8015df8: 5162 str r2, [r4, r5] 8015dfa: 604b str r3, [r1, #4] 8015dfc: 4630 mov r0, r6 8015dfe: f000 f8d7 bl 8015fb0 <__malloc_unlock> 8015e02: f104 000b add.w r0, r4, #11 8015e06: 1d23 adds r3, r4, #4 8015e08: f020 0007 bic.w r0, r0, #7 8015e0c: 1ac2 subs r2, r0, r3 8015e0e: bf1c itt ne 8015e10: 1a1b subne r3, r3, r0 8015e12: 50a3 strne r3, [r4, r2] 8015e14: e7af b.n 8015d76 <_malloc_r+0x22> 8015e16: 6862 ldr r2, [r4, #4] 8015e18: 42a3 cmp r3, r4 8015e1a: bf0c ite eq 8015e1c: f8c8 2000 streq.w r2, [r8] 8015e20: 605a strne r2, [r3, #4] 8015e22: e7eb b.n 8015dfc <_malloc_r+0xa8> 8015e24: 4623 mov r3, r4 8015e26: 6864 ldr r4, [r4, #4] 8015e28: e7ae b.n 8015d88 <_malloc_r+0x34> 8015e2a: 463c mov r4, r7 8015e2c: 687f ldr r7, [r7, #4] 8015e2e: e7b6 b.n 8015d9e <_malloc_r+0x4a> 8015e30: 461a mov r2, r3 8015e32: 685b ldr r3, [r3, #4] 8015e34: 42a3 cmp r3, r4 8015e36: d1fb bne.n 8015e30 <_malloc_r+0xdc> 8015e38: 2300 movs r3, #0 8015e3a: 6053 str r3, [r2, #4] 8015e3c: e7de b.n 8015dfc <_malloc_r+0xa8> 8015e3e: 230c movs r3, #12 8015e40: 4630 mov r0, r6 8015e42: 6033 str r3, [r6, #0] 8015e44: f000 f8b4 bl 8015fb0 <__malloc_unlock> 8015e48: e794 b.n 8015d74 <_malloc_r+0x20> 8015e4a: 6005 str r5, [r0, #0] 8015e4c: e7d6 b.n 8015dfc <_malloc_r+0xa8> 8015e4e: bf00 nop 8015e50: 200015d0 .word 0x200015d0 08015e54 <__sflush_r>: 8015e54: f9b1 200c ldrsh.w r2, [r1, #12] 8015e58: b5f8 push {r3, r4, r5, r6, r7, lr} 8015e5a: 0716 lsls r6, r2, #28 8015e5c: 4605 mov r5, r0 8015e5e: 460c mov r4, r1 8015e60: d454 bmi.n 8015f0c <__sflush_r+0xb8> 8015e62: 684b ldr r3, [r1, #4] 8015e64: 2b00 cmp r3, #0 8015e66: dc02 bgt.n 8015e6e <__sflush_r+0x1a> 8015e68: 6c0b ldr r3, [r1, #64] @ 0x40 8015e6a: 2b00 cmp r3, #0 8015e6c: dd48 ble.n 8015f00 <__sflush_r+0xac> 8015e6e: 6ae6 ldr r6, [r4, #44] @ 0x2c 8015e70: 2e00 cmp r6, #0 8015e72: d045 beq.n 8015f00 <__sflush_r+0xac> 8015e74: 2300 movs r3, #0 8015e76: f412 5280 ands.w r2, r2, #4096 @ 0x1000 8015e7a: 682f ldr r7, [r5, #0] 8015e7c: 6a21 ldr r1, [r4, #32] 8015e7e: 602b str r3, [r5, #0] 8015e80: d030 beq.n 8015ee4 <__sflush_r+0x90> 8015e82: 6d62 ldr r2, [r4, #84] @ 0x54 8015e84: 89a3 ldrh r3, [r4, #12] 8015e86: 0759 lsls r1, r3, #29 8015e88: d505 bpl.n 8015e96 <__sflush_r+0x42> 8015e8a: 6863 ldr r3, [r4, #4] 8015e8c: 1ad2 subs r2, r2, r3 8015e8e: 6b63 ldr r3, [r4, #52] @ 0x34 8015e90: b10b cbz r3, 8015e96 <__sflush_r+0x42> 8015e92: 6c23 ldr r3, [r4, #64] @ 0x40 8015e94: 1ad2 subs r2, r2, r3 8015e96: 2300 movs r3, #0 8015e98: 4628 mov r0, r5 8015e9a: 6ae6 ldr r6, [r4, #44] @ 0x2c 8015e9c: 6a21 ldr r1, [r4, #32] 8015e9e: 47b0 blx r6 8015ea0: 1c43 adds r3, r0, #1 8015ea2: 89a3 ldrh r3, [r4, #12] 8015ea4: d106 bne.n 8015eb4 <__sflush_r+0x60> 8015ea6: 6829 ldr r1, [r5, #0] 8015ea8: 291d cmp r1, #29 8015eaa: d82b bhi.n 8015f04 <__sflush_r+0xb0> 8015eac: 4a28 ldr r2, [pc, #160] @ (8015f50 <__sflush_r+0xfc>) 8015eae: 40ca lsrs r2, r1 8015eb0: 07d6 lsls r6, r2, #31 8015eb2: d527 bpl.n 8015f04 <__sflush_r+0xb0> 8015eb4: 2200 movs r2, #0 8015eb6: 6062 str r2, [r4, #4] 8015eb8: 6922 ldr r2, [r4, #16] 8015eba: 04d9 lsls r1, r3, #19 8015ebc: 6022 str r2, [r4, #0] 8015ebe: d504 bpl.n 8015eca <__sflush_r+0x76> 8015ec0: 1c42 adds r2, r0, #1 8015ec2: d101 bne.n 8015ec8 <__sflush_r+0x74> 8015ec4: 682b ldr r3, [r5, #0] 8015ec6: b903 cbnz r3, 8015eca <__sflush_r+0x76> 8015ec8: 6560 str r0, [r4, #84] @ 0x54 8015eca: 6b61 ldr r1, [r4, #52] @ 0x34 8015ecc: 602f str r7, [r5, #0] 8015ece: b1b9 cbz r1, 8015f00 <__sflush_r+0xac> 8015ed0: f104 0344 add.w r3, r4, #68 @ 0x44 8015ed4: 4299 cmp r1, r3 8015ed6: d002 beq.n 8015ede <__sflush_r+0x8a> 8015ed8: 4628 mov r0, r5 8015eda: f000 fcf9 bl 80168d0 <_free_r> 8015ede: 2300 movs r3, #0 8015ee0: 6363 str r3, [r4, #52] @ 0x34 8015ee2: e00d b.n 8015f00 <__sflush_r+0xac> 8015ee4: 2301 movs r3, #1 8015ee6: 4628 mov r0, r5 8015ee8: 47b0 blx r6 8015eea: 4602 mov r2, r0 8015eec: 1c50 adds r0, r2, #1 8015eee: d1c9 bne.n 8015e84 <__sflush_r+0x30> 8015ef0: 682b ldr r3, [r5, #0] 8015ef2: 2b00 cmp r3, #0 8015ef4: d0c6 beq.n 8015e84 <__sflush_r+0x30> 8015ef6: 2b1d cmp r3, #29 8015ef8: d001 beq.n 8015efe <__sflush_r+0xaa> 8015efa: 2b16 cmp r3, #22 8015efc: d11d bne.n 8015f3a <__sflush_r+0xe6> 8015efe: 602f str r7, [r5, #0] 8015f00: 2000 movs r0, #0 8015f02: e021 b.n 8015f48 <__sflush_r+0xf4> 8015f04: f043 0340 orr.w r3, r3, #64 @ 0x40 8015f08: b21b sxth r3, r3 8015f0a: e01a b.n 8015f42 <__sflush_r+0xee> 8015f0c: 690f ldr r7, [r1, #16] 8015f0e: 2f00 cmp r7, #0 8015f10: d0f6 beq.n 8015f00 <__sflush_r+0xac> 8015f12: 0793 lsls r3, r2, #30 8015f14: bf18 it ne 8015f16: 2300 movne r3, #0 8015f18: 680e ldr r6, [r1, #0] 8015f1a: bf08 it eq 8015f1c: 694b ldreq r3, [r1, #20] 8015f1e: 1bf6 subs r6, r6, r7 8015f20: 600f str r7, [r1, #0] 8015f22: 608b str r3, [r1, #8] 8015f24: 2e00 cmp r6, #0 8015f26: ddeb ble.n 8015f00 <__sflush_r+0xac> 8015f28: 4633 mov r3, r6 8015f2a: 463a mov r2, r7 8015f2c: 4628 mov r0, r5 8015f2e: 6a21 ldr r1, [r4, #32] 8015f30: f8d4 c028 ldr.w ip, [r4, #40] @ 0x28 8015f34: 47e0 blx ip 8015f36: 2800 cmp r0, #0 8015f38: dc07 bgt.n 8015f4a <__sflush_r+0xf6> 8015f3a: f9b4 300c ldrsh.w r3, [r4, #12] 8015f3e: f043 0340 orr.w r3, r3, #64 @ 0x40 8015f42: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015f46: 81a3 strh r3, [r4, #12] 8015f48: bdf8 pop {r3, r4, r5, r6, r7, pc} 8015f4a: 4407 add r7, r0 8015f4c: 1a36 subs r6, r6, r0 8015f4e: e7e9 b.n 8015f24 <__sflush_r+0xd0> 8015f50: 20400001 .word 0x20400001 08015f54 <_fflush_r>: 8015f54: b538 push {r3, r4, r5, lr} 8015f56: 690b ldr r3, [r1, #16] 8015f58: 4605 mov r5, r0 8015f5a: 460c mov r4, r1 8015f5c: b913 cbnz r3, 8015f64 <_fflush_r+0x10> 8015f5e: 2500 movs r5, #0 8015f60: 4628 mov r0, r5 8015f62: bd38 pop {r3, r4, r5, pc} 8015f64: b118 cbz r0, 8015f6e <_fflush_r+0x1a> 8015f66: 6a03 ldr r3, [r0, #32] 8015f68: b90b cbnz r3, 8015f6e <_fflush_r+0x1a> 8015f6a: f7fe fe2d bl 8014bc8 <__sinit> 8015f6e: f9b4 300c ldrsh.w r3, [r4, #12] 8015f72: 2b00 cmp r3, #0 8015f74: d0f3 beq.n 8015f5e <_fflush_r+0xa> 8015f76: 6e62 ldr r2, [r4, #100] @ 0x64 8015f78: 07d0 lsls r0, r2, #31 8015f7a: d404 bmi.n 8015f86 <_fflush_r+0x32> 8015f7c: 0599 lsls r1, r3, #22 8015f7e: d402 bmi.n 8015f86 <_fflush_r+0x32> 8015f80: 6da0 ldr r0, [r4, #88] @ 0x58 8015f82: f7fe fec6 bl 8014d12 <__retarget_lock_acquire_recursive> 8015f86: 4628 mov r0, r5 8015f88: 4621 mov r1, r4 8015f8a: f7ff ff63 bl 8015e54 <__sflush_r> 8015f8e: 6e63 ldr r3, [r4, #100] @ 0x64 8015f90: 4605 mov r5, r0 8015f92: 07da lsls r2, r3, #31 8015f94: d4e4 bmi.n 8015f60 <_fflush_r+0xc> 8015f96: 89a3 ldrh r3, [r4, #12] 8015f98: 059b lsls r3, r3, #22 8015f9a: d4e1 bmi.n 8015f60 <_fflush_r+0xc> 8015f9c: 6da0 ldr r0, [r4, #88] @ 0x58 8015f9e: f7fe feb9 bl 8014d14 <__retarget_lock_release_recursive> 8015fa2: e7dd b.n 8015f60 <_fflush_r+0xc> 08015fa4 <__malloc_lock>: 8015fa4: 4801 ldr r0, [pc, #4] @ (8015fac <__malloc_lock+0x8>) 8015fa6: f7fe beb4 b.w 8014d12 <__retarget_lock_acquire_recursive> 8015faa: bf00 nop 8015fac: 200015c8 .word 0x200015c8 08015fb0 <__malloc_unlock>: 8015fb0: 4801 ldr r0, [pc, #4] @ (8015fb8 <__malloc_unlock+0x8>) 8015fb2: f7fe beaf b.w 8014d14 <__retarget_lock_release_recursive> 8015fb6: bf00 nop 8015fb8: 200015c8 .word 0x200015c8 08015fbc <_Balloc>: 8015fbc: b570 push {r4, r5, r6, lr} 8015fbe: 69c6 ldr r6, [r0, #28] 8015fc0: 4604 mov r4, r0 8015fc2: 460d mov r5, r1 8015fc4: b976 cbnz r6, 8015fe4 <_Balloc+0x28> 8015fc6: 2010 movs r0, #16 8015fc8: f7ff fe9a bl 8015d00 8015fcc: 4602 mov r2, r0 8015fce: 61e0 str r0, [r4, #28] 8015fd0: b920 cbnz r0, 8015fdc <_Balloc+0x20> 8015fd2: 216b movs r1, #107 @ 0x6b 8015fd4: 4b17 ldr r3, [pc, #92] @ (8016034 <_Balloc+0x78>) 8015fd6: 4818 ldr r0, [pc, #96] @ (8016038 <_Balloc+0x7c>) 8015fd8: f7fe febe bl 8014d58 <__assert_func> 8015fdc: e9c0 6601 strd r6, r6, [r0, #4] 8015fe0: 6006 str r6, [r0, #0] 8015fe2: 60c6 str r6, [r0, #12] 8015fe4: 69e6 ldr r6, [r4, #28] 8015fe6: 68f3 ldr r3, [r6, #12] 8015fe8: b183 cbz r3, 801600c <_Balloc+0x50> 8015fea: 69e3 ldr r3, [r4, #28] 8015fec: 68db ldr r3, [r3, #12] 8015fee: f853 0025 ldr.w r0, [r3, r5, lsl #2] 8015ff2: b9b8 cbnz r0, 8016024 <_Balloc+0x68> 8015ff4: 2101 movs r1, #1 8015ff6: fa01 f605 lsl.w r6, r1, r5 8015ffa: 1d72 adds r2, r6, #5 8015ffc: 4620 mov r0, r4 8015ffe: 0092 lsls r2, r2, #2 8016000: f000 fc51 bl 80168a6 <_calloc_r> 8016004: b160 cbz r0, 8016020 <_Balloc+0x64> 8016006: e9c0 5601 strd r5, r6, [r0, #4] 801600a: e00e b.n 801602a <_Balloc+0x6e> 801600c: 2221 movs r2, #33 @ 0x21 801600e: 2104 movs r1, #4 8016010: 4620 mov r0, r4 8016012: f000 fc48 bl 80168a6 <_calloc_r> 8016016: 69e3 ldr r3, [r4, #28] 8016018: 60f0 str r0, [r6, #12] 801601a: 68db ldr r3, [r3, #12] 801601c: 2b00 cmp r3, #0 801601e: d1e4 bne.n 8015fea <_Balloc+0x2e> 8016020: 2000 movs r0, #0 8016022: bd70 pop {r4, r5, r6, pc} 8016024: 6802 ldr r2, [r0, #0] 8016026: f843 2025 str.w r2, [r3, r5, lsl #2] 801602a: 2300 movs r3, #0 801602c: e9c0 3303 strd r3, r3, [r0, #12] 8016030: e7f7 b.n 8016022 <_Balloc+0x66> 8016032: bf00 nop 8016034: 080179d1 .word 0x080179d1 8016038: 08017a62 .word 0x08017a62 0801603c <_Bfree>: 801603c: b570 push {r4, r5, r6, lr} 801603e: 69c6 ldr r6, [r0, #28] 8016040: 4605 mov r5, r0 8016042: 460c mov r4, r1 8016044: b976 cbnz r6, 8016064 <_Bfree+0x28> 8016046: 2010 movs r0, #16 8016048: f7ff fe5a bl 8015d00 801604c: 4602 mov r2, r0 801604e: 61e8 str r0, [r5, #28] 8016050: b920 cbnz r0, 801605c <_Bfree+0x20> 8016052: 218f movs r1, #143 @ 0x8f 8016054: 4b08 ldr r3, [pc, #32] @ (8016078 <_Bfree+0x3c>) 8016056: 4809 ldr r0, [pc, #36] @ (801607c <_Bfree+0x40>) 8016058: f7fe fe7e bl 8014d58 <__assert_func> 801605c: e9c0 6601 strd r6, r6, [r0, #4] 8016060: 6006 str r6, [r0, #0] 8016062: 60c6 str r6, [r0, #12] 8016064: b13c cbz r4, 8016076 <_Bfree+0x3a> 8016066: 69eb ldr r3, [r5, #28] 8016068: 6862 ldr r2, [r4, #4] 801606a: 68db ldr r3, [r3, #12] 801606c: f853 1022 ldr.w r1, [r3, r2, lsl #2] 8016070: 6021 str r1, [r4, #0] 8016072: f843 4022 str.w r4, [r3, r2, lsl #2] 8016076: bd70 pop {r4, r5, r6, pc} 8016078: 080179d1 .word 0x080179d1 801607c: 08017a62 .word 0x08017a62 08016080 <__multadd>: 8016080: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8016084: 4607 mov r7, r0 8016086: 460c mov r4, r1 8016088: 461e mov r6, r3 801608a: 2000 movs r0, #0 801608c: 690d ldr r5, [r1, #16] 801608e: f101 0c14 add.w ip, r1, #20 8016092: f8dc 3000 ldr.w r3, [ip] 8016096: 3001 adds r0, #1 8016098: b299 uxth r1, r3 801609a: fb02 6101 mla r1, r2, r1, r6 801609e: 0c1e lsrs r6, r3, #16 80160a0: 0c0b lsrs r3, r1, #16 80160a2: fb02 3306 mla r3, r2, r6, r3 80160a6: b289 uxth r1, r1 80160a8: eb01 4103 add.w r1, r1, r3, lsl #16 80160ac: 4285 cmp r5, r0 80160ae: ea4f 4613 mov.w r6, r3, lsr #16 80160b2: f84c 1b04 str.w r1, [ip], #4 80160b6: dcec bgt.n 8016092 <__multadd+0x12> 80160b8: b30e cbz r6, 80160fe <__multadd+0x7e> 80160ba: 68a3 ldr r3, [r4, #8] 80160bc: 42ab cmp r3, r5 80160be: dc19 bgt.n 80160f4 <__multadd+0x74> 80160c0: 6861 ldr r1, [r4, #4] 80160c2: 4638 mov r0, r7 80160c4: 3101 adds r1, #1 80160c6: f7ff ff79 bl 8015fbc <_Balloc> 80160ca: 4680 mov r8, r0 80160cc: b928 cbnz r0, 80160da <__multadd+0x5a> 80160ce: 4602 mov r2, r0 80160d0: 21ba movs r1, #186 @ 0xba 80160d2: 4b0c ldr r3, [pc, #48] @ (8016104 <__multadd+0x84>) 80160d4: 480c ldr r0, [pc, #48] @ (8016108 <__multadd+0x88>) 80160d6: f7fe fe3f bl 8014d58 <__assert_func> 80160da: 6922 ldr r2, [r4, #16] 80160dc: f104 010c add.w r1, r4, #12 80160e0: 3202 adds r2, #2 80160e2: 0092 lsls r2, r2, #2 80160e4: 300c adds r0, #12 80160e6: f7fe fe29 bl 8014d3c 80160ea: 4621 mov r1, r4 80160ec: 4638 mov r0, r7 80160ee: f7ff ffa5 bl 801603c <_Bfree> 80160f2: 4644 mov r4, r8 80160f4: eb04 0385 add.w r3, r4, r5, lsl #2 80160f8: 3501 adds r5, #1 80160fa: 615e str r6, [r3, #20] 80160fc: 6125 str r5, [r4, #16] 80160fe: 4620 mov r0, r4 8016100: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8016104: 08017a40 .word 0x08017a40 8016108: 08017a62 .word 0x08017a62 0801610c <__hi0bits>: 801610c: 4603 mov r3, r0 801610e: f5b0 3f80 cmp.w r0, #65536 @ 0x10000 8016112: bf3a itte cc 8016114: 0403 lslcc r3, r0, #16 8016116: 2010 movcc r0, #16 8016118: 2000 movcs r0, #0 801611a: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 801611e: bf3c itt cc 8016120: 021b lslcc r3, r3, #8 8016122: 3008 addcc r0, #8 8016124: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8016128: bf3c itt cc 801612a: 011b lslcc r3, r3, #4 801612c: 3004 addcc r0, #4 801612e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8016132: bf3c itt cc 8016134: 009b lslcc r3, r3, #2 8016136: 3002 addcc r0, #2 8016138: 2b00 cmp r3, #0 801613a: db05 blt.n 8016148 <__hi0bits+0x3c> 801613c: f013 4f80 tst.w r3, #1073741824 @ 0x40000000 8016140: f100 0001 add.w r0, r0, #1 8016144: bf08 it eq 8016146: 2020 moveq r0, #32 8016148: 4770 bx lr 0801614a <__lo0bits>: 801614a: 6803 ldr r3, [r0, #0] 801614c: 4602 mov r2, r0 801614e: f013 0007 ands.w r0, r3, #7 8016152: d00b beq.n 801616c <__lo0bits+0x22> 8016154: 07d9 lsls r1, r3, #31 8016156: d421 bmi.n 801619c <__lo0bits+0x52> 8016158: 0798 lsls r0, r3, #30 801615a: bf49 itett mi 801615c: 085b lsrmi r3, r3, #1 801615e: 089b lsrpl r3, r3, #2 8016160: 2001 movmi r0, #1 8016162: 6013 strmi r3, [r2, #0] 8016164: bf5c itt pl 8016166: 2002 movpl r0, #2 8016168: 6013 strpl r3, [r2, #0] 801616a: 4770 bx lr 801616c: b299 uxth r1, r3 801616e: b909 cbnz r1, 8016174 <__lo0bits+0x2a> 8016170: 2010 movs r0, #16 8016172: 0c1b lsrs r3, r3, #16 8016174: b2d9 uxtb r1, r3 8016176: b909 cbnz r1, 801617c <__lo0bits+0x32> 8016178: 3008 adds r0, #8 801617a: 0a1b lsrs r3, r3, #8 801617c: 0719 lsls r1, r3, #28 801617e: bf04 itt eq 8016180: 091b lsreq r3, r3, #4 8016182: 3004 addeq r0, #4 8016184: 0799 lsls r1, r3, #30 8016186: bf04 itt eq 8016188: 089b lsreq r3, r3, #2 801618a: 3002 addeq r0, #2 801618c: 07d9 lsls r1, r3, #31 801618e: d403 bmi.n 8016198 <__lo0bits+0x4e> 8016190: 085b lsrs r3, r3, #1 8016192: f100 0001 add.w r0, r0, #1 8016196: d003 beq.n 80161a0 <__lo0bits+0x56> 8016198: 6013 str r3, [r2, #0] 801619a: 4770 bx lr 801619c: 2000 movs r0, #0 801619e: 4770 bx lr 80161a0: 2020 movs r0, #32 80161a2: 4770 bx lr 080161a4 <__i2b>: 80161a4: b510 push {r4, lr} 80161a6: 460c mov r4, r1 80161a8: 2101 movs r1, #1 80161aa: f7ff ff07 bl 8015fbc <_Balloc> 80161ae: 4602 mov r2, r0 80161b0: b928 cbnz r0, 80161be <__i2b+0x1a> 80161b2: f240 1145 movw r1, #325 @ 0x145 80161b6: 4b04 ldr r3, [pc, #16] @ (80161c8 <__i2b+0x24>) 80161b8: 4804 ldr r0, [pc, #16] @ (80161cc <__i2b+0x28>) 80161ba: f7fe fdcd bl 8014d58 <__assert_func> 80161be: 2301 movs r3, #1 80161c0: 6144 str r4, [r0, #20] 80161c2: 6103 str r3, [r0, #16] 80161c4: bd10 pop {r4, pc} 80161c6: bf00 nop 80161c8: 08017a40 .word 0x08017a40 80161cc: 08017a62 .word 0x08017a62 080161d0 <__multiply>: 80161d0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80161d4: 4617 mov r7, r2 80161d6: 690a ldr r2, [r1, #16] 80161d8: 693b ldr r3, [r7, #16] 80161da: 4689 mov r9, r1 80161dc: 429a cmp r2, r3 80161de: bfa2 ittt ge 80161e0: 463b movge r3, r7 80161e2: 460f movge r7, r1 80161e4: 4699 movge r9, r3 80161e6: 693d ldr r5, [r7, #16] 80161e8: f8d9 a010 ldr.w sl, [r9, #16] 80161ec: 68bb ldr r3, [r7, #8] 80161ee: 6879 ldr r1, [r7, #4] 80161f0: eb05 060a add.w r6, r5, sl 80161f4: 42b3 cmp r3, r6 80161f6: b085 sub sp, #20 80161f8: bfb8 it lt 80161fa: 3101 addlt r1, #1 80161fc: f7ff fede bl 8015fbc <_Balloc> 8016200: b930 cbnz r0, 8016210 <__multiply+0x40> 8016202: 4602 mov r2, r0 8016204: f44f 71b1 mov.w r1, #354 @ 0x162 8016208: 4b40 ldr r3, [pc, #256] @ (801630c <__multiply+0x13c>) 801620a: 4841 ldr r0, [pc, #260] @ (8016310 <__multiply+0x140>) 801620c: f7fe fda4 bl 8014d58 <__assert_func> 8016210: f100 0414 add.w r4, r0, #20 8016214: 4623 mov r3, r4 8016216: 2200 movs r2, #0 8016218: eb04 0e86 add.w lr, r4, r6, lsl #2 801621c: 4573 cmp r3, lr 801621e: d320 bcc.n 8016262 <__multiply+0x92> 8016220: f107 0814 add.w r8, r7, #20 8016224: f109 0114 add.w r1, r9, #20 8016228: eb08 0585 add.w r5, r8, r5, lsl #2 801622c: eb01 038a add.w r3, r1, sl, lsl #2 8016230: 9302 str r3, [sp, #8] 8016232: 1beb subs r3, r5, r7 8016234: 3b15 subs r3, #21 8016236: f023 0303 bic.w r3, r3, #3 801623a: 3304 adds r3, #4 801623c: 3715 adds r7, #21 801623e: 42bd cmp r5, r7 8016240: bf38 it cc 8016242: 2304 movcc r3, #4 8016244: 9301 str r3, [sp, #4] 8016246: 9b02 ldr r3, [sp, #8] 8016248: 9103 str r1, [sp, #12] 801624a: 428b cmp r3, r1 801624c: d80c bhi.n 8016268 <__multiply+0x98> 801624e: 2e00 cmp r6, #0 8016250: dd03 ble.n 801625a <__multiply+0x8a> 8016252: f85e 3d04 ldr.w r3, [lr, #-4]! 8016256: 2b00 cmp r3, #0 8016258: d055 beq.n 8016306 <__multiply+0x136> 801625a: 6106 str r6, [r0, #16] 801625c: b005 add sp, #20 801625e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8016262: f843 2b04 str.w r2, [r3], #4 8016266: e7d9 b.n 801621c <__multiply+0x4c> 8016268: f8b1 a000 ldrh.w sl, [r1] 801626c: f1ba 0f00 cmp.w sl, #0 8016270: d01f beq.n 80162b2 <__multiply+0xe2> 8016272: 46c4 mov ip, r8 8016274: 46a1 mov r9, r4 8016276: 2700 movs r7, #0 8016278: f85c 2b04 ldr.w r2, [ip], #4 801627c: f8d9 3000 ldr.w r3, [r9] 8016280: fa1f fb82 uxth.w fp, r2 8016284: b29b uxth r3, r3 8016286: fb0a 330b mla r3, sl, fp, r3 801628a: 443b add r3, r7 801628c: f8d9 7000 ldr.w r7, [r9] 8016290: 0c12 lsrs r2, r2, #16 8016292: 0c3f lsrs r7, r7, #16 8016294: fb0a 7202 mla r2, sl, r2, r7 8016298: eb02 4213 add.w r2, r2, r3, lsr #16 801629c: b29b uxth r3, r3 801629e: ea43 4302 orr.w r3, r3, r2, lsl #16 80162a2: 4565 cmp r5, ip 80162a4: ea4f 4712 mov.w r7, r2, lsr #16 80162a8: f849 3b04 str.w r3, [r9], #4 80162ac: d8e4 bhi.n 8016278 <__multiply+0xa8> 80162ae: 9b01 ldr r3, [sp, #4] 80162b0: 50e7 str r7, [r4, r3] 80162b2: 9b03 ldr r3, [sp, #12] 80162b4: 3104 adds r1, #4 80162b6: f8b3 9002 ldrh.w r9, [r3, #2] 80162ba: f1b9 0f00 cmp.w r9, #0 80162be: d020 beq.n 8016302 <__multiply+0x132> 80162c0: 4647 mov r7, r8 80162c2: 46a4 mov ip, r4 80162c4: f04f 0a00 mov.w sl, #0 80162c8: 6823 ldr r3, [r4, #0] 80162ca: f8b7 b000 ldrh.w fp, [r7] 80162ce: f8bc 2002 ldrh.w r2, [ip, #2] 80162d2: b29b uxth r3, r3 80162d4: fb09 220b mla r2, r9, fp, r2 80162d8: 4452 add r2, sl 80162da: ea43 4302 orr.w r3, r3, r2, lsl #16 80162de: f84c 3b04 str.w r3, [ip], #4 80162e2: f857 3b04 ldr.w r3, [r7], #4 80162e6: ea4f 4a13 mov.w sl, r3, lsr #16 80162ea: f8bc 3000 ldrh.w r3, [ip] 80162ee: 42bd cmp r5, r7 80162f0: fb09 330a mla r3, r9, sl, r3 80162f4: eb03 4312 add.w r3, r3, r2, lsr #16 80162f8: ea4f 4a13 mov.w sl, r3, lsr #16 80162fc: d8e5 bhi.n 80162ca <__multiply+0xfa> 80162fe: 9a01 ldr r2, [sp, #4] 8016300: 50a3 str r3, [r4, r2] 8016302: 3404 adds r4, #4 8016304: e79f b.n 8016246 <__multiply+0x76> 8016306: 3e01 subs r6, #1 8016308: e7a1 b.n 801624e <__multiply+0x7e> 801630a: bf00 nop 801630c: 08017a40 .word 0x08017a40 8016310: 08017a62 .word 0x08017a62 08016314 <__pow5mult>: 8016314: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8016318: 4615 mov r5, r2 801631a: f012 0203 ands.w r2, r2, #3 801631e: 4607 mov r7, r0 8016320: 460e mov r6, r1 8016322: d007 beq.n 8016334 <__pow5mult+0x20> 8016324: 4c25 ldr r4, [pc, #148] @ (80163bc <__pow5mult+0xa8>) 8016326: 3a01 subs r2, #1 8016328: 2300 movs r3, #0 801632a: f854 2022 ldr.w r2, [r4, r2, lsl #2] 801632e: f7ff fea7 bl 8016080 <__multadd> 8016332: 4606 mov r6, r0 8016334: 10ad asrs r5, r5, #2 8016336: d03d beq.n 80163b4 <__pow5mult+0xa0> 8016338: 69fc ldr r4, [r7, #28] 801633a: b97c cbnz r4, 801635c <__pow5mult+0x48> 801633c: 2010 movs r0, #16 801633e: f7ff fcdf bl 8015d00 8016342: 4602 mov r2, r0 8016344: 61f8 str r0, [r7, #28] 8016346: b928 cbnz r0, 8016354 <__pow5mult+0x40> 8016348: f240 11b3 movw r1, #435 @ 0x1b3 801634c: 4b1c ldr r3, [pc, #112] @ (80163c0 <__pow5mult+0xac>) 801634e: 481d ldr r0, [pc, #116] @ (80163c4 <__pow5mult+0xb0>) 8016350: f7fe fd02 bl 8014d58 <__assert_func> 8016354: e9c0 4401 strd r4, r4, [r0, #4] 8016358: 6004 str r4, [r0, #0] 801635a: 60c4 str r4, [r0, #12] 801635c: f8d7 801c ldr.w r8, [r7, #28] 8016360: f8d8 4008 ldr.w r4, [r8, #8] 8016364: b94c cbnz r4, 801637a <__pow5mult+0x66> 8016366: f240 2171 movw r1, #625 @ 0x271 801636a: 4638 mov r0, r7 801636c: f7ff ff1a bl 80161a4 <__i2b> 8016370: 2300 movs r3, #0 8016372: 4604 mov r4, r0 8016374: f8c8 0008 str.w r0, [r8, #8] 8016378: 6003 str r3, [r0, #0] 801637a: f04f 0900 mov.w r9, #0 801637e: 07eb lsls r3, r5, #31 8016380: d50a bpl.n 8016398 <__pow5mult+0x84> 8016382: 4631 mov r1, r6 8016384: 4622 mov r2, r4 8016386: 4638 mov r0, r7 8016388: f7ff ff22 bl 80161d0 <__multiply> 801638c: 4680 mov r8, r0 801638e: 4631 mov r1, r6 8016390: 4638 mov r0, r7 8016392: f7ff fe53 bl 801603c <_Bfree> 8016396: 4646 mov r6, r8 8016398: 106d asrs r5, r5, #1 801639a: d00b beq.n 80163b4 <__pow5mult+0xa0> 801639c: 6820 ldr r0, [r4, #0] 801639e: b938 cbnz r0, 80163b0 <__pow5mult+0x9c> 80163a0: 4622 mov r2, r4 80163a2: 4621 mov r1, r4 80163a4: 4638 mov r0, r7 80163a6: f7ff ff13 bl 80161d0 <__multiply> 80163aa: 6020 str r0, [r4, #0] 80163ac: f8c0 9000 str.w r9, [r0] 80163b0: 4604 mov r4, r0 80163b2: e7e4 b.n 801637e <__pow5mult+0x6a> 80163b4: 4630 mov r0, r6 80163b6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 80163ba: bf00 nop 80163bc: 08017ac8 .word 0x08017ac8 80163c0: 080179d1 .word 0x080179d1 80163c4: 08017a62 .word 0x08017a62 080163c8 <__lshift>: 80163c8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80163cc: 460c mov r4, r1 80163ce: 4607 mov r7, r0 80163d0: 4691 mov r9, r2 80163d2: 6923 ldr r3, [r4, #16] 80163d4: 6849 ldr r1, [r1, #4] 80163d6: eb03 1862 add.w r8, r3, r2, asr #5 80163da: 68a3 ldr r3, [r4, #8] 80163dc: ea4f 1a62 mov.w sl, r2, asr #5 80163e0: f108 0601 add.w r6, r8, #1 80163e4: 42b3 cmp r3, r6 80163e6: db0b blt.n 8016400 <__lshift+0x38> 80163e8: 4638 mov r0, r7 80163ea: f7ff fde7 bl 8015fbc <_Balloc> 80163ee: 4605 mov r5, r0 80163f0: b948 cbnz r0, 8016406 <__lshift+0x3e> 80163f2: 4602 mov r2, r0 80163f4: f44f 71ef mov.w r1, #478 @ 0x1de 80163f8: 4b27 ldr r3, [pc, #156] @ (8016498 <__lshift+0xd0>) 80163fa: 4828 ldr r0, [pc, #160] @ (801649c <__lshift+0xd4>) 80163fc: f7fe fcac bl 8014d58 <__assert_func> 8016400: 3101 adds r1, #1 8016402: 005b lsls r3, r3, #1 8016404: e7ee b.n 80163e4 <__lshift+0x1c> 8016406: 2300 movs r3, #0 8016408: f100 0114 add.w r1, r0, #20 801640c: f100 0210 add.w r2, r0, #16 8016410: 4618 mov r0, r3 8016412: 4553 cmp r3, sl 8016414: db33 blt.n 801647e <__lshift+0xb6> 8016416: 6920 ldr r0, [r4, #16] 8016418: ea2a 7aea bic.w sl, sl, sl, asr #31 801641c: f104 0314 add.w r3, r4, #20 8016420: f019 091f ands.w r9, r9, #31 8016424: eb01 018a add.w r1, r1, sl, lsl #2 8016428: eb03 0c80 add.w ip, r3, r0, lsl #2 801642c: d02b beq.n 8016486 <__lshift+0xbe> 801642e: 468a mov sl, r1 8016430: 2200 movs r2, #0 8016432: f1c9 0e20 rsb lr, r9, #32 8016436: 6818 ldr r0, [r3, #0] 8016438: fa00 f009 lsl.w r0, r0, r9 801643c: 4310 orrs r0, r2 801643e: f84a 0b04 str.w r0, [sl], #4 8016442: f853 2b04 ldr.w r2, [r3], #4 8016446: 459c cmp ip, r3 8016448: fa22 f20e lsr.w r2, r2, lr 801644c: d8f3 bhi.n 8016436 <__lshift+0x6e> 801644e: ebac 0304 sub.w r3, ip, r4 8016452: 3b15 subs r3, #21 8016454: f023 0303 bic.w r3, r3, #3 8016458: 3304 adds r3, #4 801645a: f104 0015 add.w r0, r4, #21 801645e: 4560 cmp r0, ip 8016460: bf88 it hi 8016462: 2304 movhi r3, #4 8016464: 50ca str r2, [r1, r3] 8016466: b10a cbz r2, 801646c <__lshift+0xa4> 8016468: f108 0602 add.w r6, r8, #2 801646c: 3e01 subs r6, #1 801646e: 4638 mov r0, r7 8016470: 4621 mov r1, r4 8016472: 612e str r6, [r5, #16] 8016474: f7ff fde2 bl 801603c <_Bfree> 8016478: 4628 mov r0, r5 801647a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801647e: f842 0f04 str.w r0, [r2, #4]! 8016482: 3301 adds r3, #1 8016484: e7c5 b.n 8016412 <__lshift+0x4a> 8016486: 3904 subs r1, #4 8016488: f853 2b04 ldr.w r2, [r3], #4 801648c: 459c cmp ip, r3 801648e: f841 2f04 str.w r2, [r1, #4]! 8016492: d8f9 bhi.n 8016488 <__lshift+0xc0> 8016494: e7ea b.n 801646c <__lshift+0xa4> 8016496: bf00 nop 8016498: 08017a40 .word 0x08017a40 801649c: 08017a62 .word 0x08017a62 080164a0 <__mcmp>: 80164a0: 4603 mov r3, r0 80164a2: 690a ldr r2, [r1, #16] 80164a4: 6900 ldr r0, [r0, #16] 80164a6: b530 push {r4, r5, lr} 80164a8: 1a80 subs r0, r0, r2 80164aa: d10e bne.n 80164ca <__mcmp+0x2a> 80164ac: 3314 adds r3, #20 80164ae: 3114 adds r1, #20 80164b0: eb03 0482 add.w r4, r3, r2, lsl #2 80164b4: eb01 0182 add.w r1, r1, r2, lsl #2 80164b8: f854 5d04 ldr.w r5, [r4, #-4]! 80164bc: f851 2d04 ldr.w r2, [r1, #-4]! 80164c0: 4295 cmp r5, r2 80164c2: d003 beq.n 80164cc <__mcmp+0x2c> 80164c4: d205 bcs.n 80164d2 <__mcmp+0x32> 80164c6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80164ca: bd30 pop {r4, r5, pc} 80164cc: 42a3 cmp r3, r4 80164ce: d3f3 bcc.n 80164b8 <__mcmp+0x18> 80164d0: e7fb b.n 80164ca <__mcmp+0x2a> 80164d2: 2001 movs r0, #1 80164d4: e7f9 b.n 80164ca <__mcmp+0x2a> ... 080164d8 <__mdiff>: 80164d8: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 80164dc: 4689 mov r9, r1 80164de: 4606 mov r6, r0 80164e0: 4611 mov r1, r2 80164e2: 4648 mov r0, r9 80164e4: 4614 mov r4, r2 80164e6: f7ff ffdb bl 80164a0 <__mcmp> 80164ea: 1e05 subs r5, r0, #0 80164ec: d112 bne.n 8016514 <__mdiff+0x3c> 80164ee: 4629 mov r1, r5 80164f0: 4630 mov r0, r6 80164f2: f7ff fd63 bl 8015fbc <_Balloc> 80164f6: 4602 mov r2, r0 80164f8: b928 cbnz r0, 8016506 <__mdiff+0x2e> 80164fa: f240 2137 movw r1, #567 @ 0x237 80164fe: 4b3e ldr r3, [pc, #248] @ (80165f8 <__mdiff+0x120>) 8016500: 483e ldr r0, [pc, #248] @ (80165fc <__mdiff+0x124>) 8016502: f7fe fc29 bl 8014d58 <__assert_func> 8016506: 2301 movs r3, #1 8016508: e9c0 3504 strd r3, r5, [r0, #16] 801650c: 4610 mov r0, r2 801650e: b003 add sp, #12 8016510: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8016514: bfbc itt lt 8016516: 464b movlt r3, r9 8016518: 46a1 movlt r9, r4 801651a: 4630 mov r0, r6 801651c: f8d9 1004 ldr.w r1, [r9, #4] 8016520: bfba itte lt 8016522: 461c movlt r4, r3 8016524: 2501 movlt r5, #1 8016526: 2500 movge r5, #0 8016528: f7ff fd48 bl 8015fbc <_Balloc> 801652c: 4602 mov r2, r0 801652e: b918 cbnz r0, 8016538 <__mdiff+0x60> 8016530: f240 2145 movw r1, #581 @ 0x245 8016534: 4b30 ldr r3, [pc, #192] @ (80165f8 <__mdiff+0x120>) 8016536: e7e3 b.n 8016500 <__mdiff+0x28> 8016538: f100 0b14 add.w fp, r0, #20 801653c: f8d9 7010 ldr.w r7, [r9, #16] 8016540: f109 0310 add.w r3, r9, #16 8016544: 60c5 str r5, [r0, #12] 8016546: f04f 0c00 mov.w ip, #0 801654a: f109 0514 add.w r5, r9, #20 801654e: 46d9 mov r9, fp 8016550: 6926 ldr r6, [r4, #16] 8016552: f104 0e14 add.w lr, r4, #20 8016556: eb05 0887 add.w r8, r5, r7, lsl #2 801655a: eb0e 0686 add.w r6, lr, r6, lsl #2 801655e: 9301 str r3, [sp, #4] 8016560: 9b01 ldr r3, [sp, #4] 8016562: f85e 0b04 ldr.w r0, [lr], #4 8016566: f853 af04 ldr.w sl, [r3, #4]! 801656a: b281 uxth r1, r0 801656c: 9301 str r3, [sp, #4] 801656e: fa1f f38a uxth.w r3, sl 8016572: 1a5b subs r3, r3, r1 8016574: 0c00 lsrs r0, r0, #16 8016576: 4463 add r3, ip 8016578: ebc0 401a rsb r0, r0, sl, lsr #16 801657c: eb00 4023 add.w r0, r0, r3, asr #16 8016580: b29b uxth r3, r3 8016582: ea43 4300 orr.w r3, r3, r0, lsl #16 8016586: 4576 cmp r6, lr 8016588: ea4f 4c20 mov.w ip, r0, asr #16 801658c: f849 3b04 str.w r3, [r9], #4 8016590: d8e6 bhi.n 8016560 <__mdiff+0x88> 8016592: 1b33 subs r3, r6, r4 8016594: 3b15 subs r3, #21 8016596: f023 0303 bic.w r3, r3, #3 801659a: 3415 adds r4, #21 801659c: 3304 adds r3, #4 801659e: 42a6 cmp r6, r4 80165a0: bf38 it cc 80165a2: 2304 movcc r3, #4 80165a4: 441d add r5, r3 80165a6: 445b add r3, fp 80165a8: 461e mov r6, r3 80165aa: 462c mov r4, r5 80165ac: 4544 cmp r4, r8 80165ae: d30e bcc.n 80165ce <__mdiff+0xf6> 80165b0: f108 0103 add.w r1, r8, #3 80165b4: 1b49 subs r1, r1, r5 80165b6: f021 0103 bic.w r1, r1, #3 80165ba: 3d03 subs r5, #3 80165bc: 45a8 cmp r8, r5 80165be: bf38 it cc 80165c0: 2100 movcc r1, #0 80165c2: 440b add r3, r1 80165c4: f853 1d04 ldr.w r1, [r3, #-4]! 80165c8: b199 cbz r1, 80165f2 <__mdiff+0x11a> 80165ca: 6117 str r7, [r2, #16] 80165cc: e79e b.n 801650c <__mdiff+0x34> 80165ce: 46e6 mov lr, ip 80165d0: f854 1b04 ldr.w r1, [r4], #4 80165d4: fa1f fc81 uxth.w ip, r1 80165d8: 44f4 add ip, lr 80165da: 0c08 lsrs r0, r1, #16 80165dc: 4471 add r1, lr 80165de: eb00 402c add.w r0, r0, ip, asr #16 80165e2: b289 uxth r1, r1 80165e4: ea41 4100 orr.w r1, r1, r0, lsl #16 80165e8: ea4f 4c20 mov.w ip, r0, asr #16 80165ec: f846 1b04 str.w r1, [r6], #4 80165f0: e7dc b.n 80165ac <__mdiff+0xd4> 80165f2: 3f01 subs r7, #1 80165f4: e7e6 b.n 80165c4 <__mdiff+0xec> 80165f6: bf00 nop 80165f8: 08017a40 .word 0x08017a40 80165fc: 08017a62 .word 0x08017a62 08016600 <__d2b>: 8016600: e92d 4373 stmdb sp!, {r0, r1, r4, r5, r6, r8, r9, lr} 8016604: 2101 movs r1, #1 8016606: 4690 mov r8, r2 8016608: 4699 mov r9, r3 801660a: 9e08 ldr r6, [sp, #32] 801660c: f7ff fcd6 bl 8015fbc <_Balloc> 8016610: 4604 mov r4, r0 8016612: b930 cbnz r0, 8016622 <__d2b+0x22> 8016614: 4602 mov r2, r0 8016616: f240 310f movw r1, #783 @ 0x30f 801661a: 4b23 ldr r3, [pc, #140] @ (80166a8 <__d2b+0xa8>) 801661c: 4823 ldr r0, [pc, #140] @ (80166ac <__d2b+0xac>) 801661e: f7fe fb9b bl 8014d58 <__assert_func> 8016622: f3c9 550a ubfx r5, r9, #20, #11 8016626: f3c9 0313 ubfx r3, r9, #0, #20 801662a: b10d cbz r5, 8016630 <__d2b+0x30> 801662c: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8016630: 9301 str r3, [sp, #4] 8016632: f1b8 0300 subs.w r3, r8, #0 8016636: d024 beq.n 8016682 <__d2b+0x82> 8016638: 4668 mov r0, sp 801663a: 9300 str r3, [sp, #0] 801663c: f7ff fd85 bl 801614a <__lo0bits> 8016640: e9dd 1200 ldrd r1, r2, [sp] 8016644: b1d8 cbz r0, 801667e <__d2b+0x7e> 8016646: f1c0 0320 rsb r3, r0, #32 801664a: fa02 f303 lsl.w r3, r2, r3 801664e: 430b orrs r3, r1 8016650: 40c2 lsrs r2, r0 8016652: 6163 str r3, [r4, #20] 8016654: 9201 str r2, [sp, #4] 8016656: 9b01 ldr r3, [sp, #4] 8016658: 2b00 cmp r3, #0 801665a: bf0c ite eq 801665c: 2201 moveq r2, #1 801665e: 2202 movne r2, #2 8016660: 61a3 str r3, [r4, #24] 8016662: 6122 str r2, [r4, #16] 8016664: b1ad cbz r5, 8016692 <__d2b+0x92> 8016666: f2a5 4533 subw r5, r5, #1075 @ 0x433 801666a: 4405 add r5, r0 801666c: 6035 str r5, [r6, #0] 801666e: f1c0 0035 rsb r0, r0, #53 @ 0x35 8016672: 9b09 ldr r3, [sp, #36] @ 0x24 8016674: 6018 str r0, [r3, #0] 8016676: 4620 mov r0, r4 8016678: b002 add sp, #8 801667a: e8bd 8370 ldmia.w sp!, {r4, r5, r6, r8, r9, pc} 801667e: 6161 str r1, [r4, #20] 8016680: e7e9 b.n 8016656 <__d2b+0x56> 8016682: a801 add r0, sp, #4 8016684: f7ff fd61 bl 801614a <__lo0bits> 8016688: 9b01 ldr r3, [sp, #4] 801668a: 2201 movs r2, #1 801668c: 6163 str r3, [r4, #20] 801668e: 3020 adds r0, #32 8016690: e7e7 b.n 8016662 <__d2b+0x62> 8016692: f2a0 4032 subw r0, r0, #1074 @ 0x432 8016696: eb04 0382 add.w r3, r4, r2, lsl #2 801669a: 6030 str r0, [r6, #0] 801669c: 6918 ldr r0, [r3, #16] 801669e: f7ff fd35 bl 801610c <__hi0bits> 80166a2: ebc0 1042 rsb r0, r0, r2, lsl #5 80166a6: e7e4 b.n 8016672 <__d2b+0x72> 80166a8: 08017a40 .word 0x08017a40 80166ac: 08017a62 .word 0x08017a62 080166b0 <__sread>: 80166b0: b510 push {r4, lr} 80166b2: 460c mov r4, r1 80166b4: f9b1 100e ldrsh.w r1, [r1, #14] 80166b8: f000 f8aa bl 8016810 <_read_r> 80166bc: 2800 cmp r0, #0 80166be: bfab itete ge 80166c0: 6d63 ldrge r3, [r4, #84] @ 0x54 80166c2: 89a3 ldrhlt r3, [r4, #12] 80166c4: 181b addge r3, r3, r0 80166c6: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 80166ca: bfac ite ge 80166cc: 6563 strge r3, [r4, #84] @ 0x54 80166ce: 81a3 strhlt r3, [r4, #12] 80166d0: bd10 pop {r4, pc} 080166d2 <__swrite>: 80166d2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80166d6: 461f mov r7, r3 80166d8: 898b ldrh r3, [r1, #12] 80166da: 4605 mov r5, r0 80166dc: 05db lsls r3, r3, #23 80166de: 460c mov r4, r1 80166e0: 4616 mov r6, r2 80166e2: d505 bpl.n 80166f0 <__swrite+0x1e> 80166e4: 2302 movs r3, #2 80166e6: 2200 movs r2, #0 80166e8: f9b1 100e ldrsh.w r1, [r1, #14] 80166ec: f000 f87e bl 80167ec <_lseek_r> 80166f0: 89a3 ldrh r3, [r4, #12] 80166f2: 4632 mov r2, r6 80166f4: f423 5380 bic.w r3, r3, #4096 @ 0x1000 80166f8: 81a3 strh r3, [r4, #12] 80166fa: 4628 mov r0, r5 80166fc: 463b mov r3, r7 80166fe: f9b4 100e ldrsh.w r1, [r4, #14] 8016702: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8016706: f000 b8a5 b.w 8016854 <_write_r> 0801670a <__sseek>: 801670a: b510 push {r4, lr} 801670c: 460c mov r4, r1 801670e: f9b1 100e ldrsh.w r1, [r1, #14] 8016712: f000 f86b bl 80167ec <_lseek_r> 8016716: 1c43 adds r3, r0, #1 8016718: 89a3 ldrh r3, [r4, #12] 801671a: bf15 itete ne 801671c: 6560 strne r0, [r4, #84] @ 0x54 801671e: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 8016722: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 8016726: 81a3 strheq r3, [r4, #12] 8016728: bf18 it ne 801672a: 81a3 strhne r3, [r4, #12] 801672c: bd10 pop {r4, pc} 0801672e <__sclose>: 801672e: f9b1 100e ldrsh.w r1, [r1, #14] 8016732: f000 b8a1 b.w 8016878 <_close_r> ... 08016738 : 8016738: b40e push {r1, r2, r3} 801673a: b503 push {r0, r1, lr} 801673c: 4601 mov r1, r0 801673e: ab03 add r3, sp, #12 8016740: 4805 ldr r0, [pc, #20] @ (8016758 ) 8016742: f853 2b04 ldr.w r2, [r3], #4 8016746: 6800 ldr r0, [r0, #0] 8016748: 9301 str r3, [sp, #4] 801674a: f000 f931 bl 80169b0 <_vfiprintf_r> 801674e: b002 add sp, #8 8016750: f85d eb04 ldr.w lr, [sp], #4 8016754: b003 add sp, #12 8016756: 4770 bx lr 8016758: 2000009c .word 0x2000009c 0801675c <_realloc_r>: 801675c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8016760: 4607 mov r7, r0 8016762: 4614 mov r4, r2 8016764: 460d mov r5, r1 8016766: b921 cbnz r1, 8016772 <_realloc_r+0x16> 8016768: 4611 mov r1, r2 801676a: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 801676e: f7ff baf1 b.w 8015d54 <_malloc_r> 8016772: b92a cbnz r2, 8016780 <_realloc_r+0x24> 8016774: f000 f8ac bl 80168d0 <_free_r> 8016778: 4625 mov r5, r4 801677a: 4628 mov r0, r5 801677c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8016780: f000 fa40 bl 8016c04 <_malloc_usable_size_r> 8016784: 4284 cmp r4, r0 8016786: 4606 mov r6, r0 8016788: d802 bhi.n 8016790 <_realloc_r+0x34> 801678a: ebb4 0f50 cmp.w r4, r0, lsr #1 801678e: d8f4 bhi.n 801677a <_realloc_r+0x1e> 8016790: 4621 mov r1, r4 8016792: 4638 mov r0, r7 8016794: f7ff fade bl 8015d54 <_malloc_r> 8016798: 4680 mov r8, r0 801679a: b908 cbnz r0, 80167a0 <_realloc_r+0x44> 801679c: 4645 mov r5, r8 801679e: e7ec b.n 801677a <_realloc_r+0x1e> 80167a0: 42b4 cmp r4, r6 80167a2: 4622 mov r2, r4 80167a4: 4629 mov r1, r5 80167a6: bf28 it cs 80167a8: 4632 movcs r2, r6 80167aa: f7fe fac7 bl 8014d3c 80167ae: 4629 mov r1, r5 80167b0: 4638 mov r0, r7 80167b2: f000 f88d bl 80168d0 <_free_r> 80167b6: e7f1 b.n 801679c <_realloc_r+0x40> 080167b8 : 80167b8: 4288 cmp r0, r1 80167ba: b510 push {r4, lr} 80167bc: eb01 0402 add.w r4, r1, r2 80167c0: d902 bls.n 80167c8 80167c2: 4284 cmp r4, r0 80167c4: 4623 mov r3, r4 80167c6: d807 bhi.n 80167d8 80167c8: 1e43 subs r3, r0, #1 80167ca: 42a1 cmp r1, r4 80167cc: d008 beq.n 80167e0 80167ce: f811 2b01 ldrb.w r2, [r1], #1 80167d2: f803 2f01 strb.w r2, [r3, #1]! 80167d6: e7f8 b.n 80167ca 80167d8: 4601 mov r1, r0 80167da: 4402 add r2, r0 80167dc: 428a cmp r2, r1 80167de: d100 bne.n 80167e2 80167e0: bd10 pop {r4, pc} 80167e2: f813 4d01 ldrb.w r4, [r3, #-1]! 80167e6: f802 4d01 strb.w r4, [r2, #-1]! 80167ea: e7f7 b.n 80167dc 080167ec <_lseek_r>: 80167ec: b538 push {r3, r4, r5, lr} 80167ee: 4604 mov r4, r0 80167f0: 4608 mov r0, r1 80167f2: 4611 mov r1, r2 80167f4: 2200 movs r2, #0 80167f6: 4d05 ldr r5, [pc, #20] @ (801680c <_lseek_r+0x20>) 80167f8: 602a str r2, [r5, #0] 80167fa: 461a mov r2, r3 80167fc: f7f7 f875 bl 800d8ea <_lseek> 8016800: 1c43 adds r3, r0, #1 8016802: d102 bne.n 801680a <_lseek_r+0x1e> 8016804: 682b ldr r3, [r5, #0] 8016806: b103 cbz r3, 801680a <_lseek_r+0x1e> 8016808: 6023 str r3, [r4, #0] 801680a: bd38 pop {r3, r4, r5, pc} 801680c: 200015d4 .word 0x200015d4 08016810 <_read_r>: 8016810: b538 push {r3, r4, r5, lr} 8016812: 4604 mov r4, r0 8016814: 4608 mov r0, r1 8016816: 4611 mov r1, r2 8016818: 2200 movs r2, #0 801681a: 4d05 ldr r5, [pc, #20] @ (8016830 <_read_r+0x20>) 801681c: 602a str r2, [r5, #0] 801681e: 461a mov r2, r3 8016820: f7f7 f822 bl 800d868 <_read> 8016824: 1c43 adds r3, r0, #1 8016826: d102 bne.n 801682e <_read_r+0x1e> 8016828: 682b ldr r3, [r5, #0] 801682a: b103 cbz r3, 801682e <_read_r+0x1e> 801682c: 6023 str r3, [r4, #0] 801682e: bd38 pop {r3, r4, r5, pc} 8016830: 200015d4 .word 0x200015d4 08016834 <_sbrk_r>: 8016834: b538 push {r3, r4, r5, lr} 8016836: 2300 movs r3, #0 8016838: 4d05 ldr r5, [pc, #20] @ (8016850 <_sbrk_r+0x1c>) 801683a: 4604 mov r4, r0 801683c: 4608 mov r0, r1 801683e: 602b str r3, [r5, #0] 8016840: f7f7 f860 bl 800d904 <_sbrk> 8016844: 1c43 adds r3, r0, #1 8016846: d102 bne.n 801684e <_sbrk_r+0x1a> 8016848: 682b ldr r3, [r5, #0] 801684a: b103 cbz r3, 801684e <_sbrk_r+0x1a> 801684c: 6023 str r3, [r4, #0] 801684e: bd38 pop {r3, r4, r5, pc} 8016850: 200015d4 .word 0x200015d4 08016854 <_write_r>: 8016854: b538 push {r3, r4, r5, lr} 8016856: 4604 mov r4, r0 8016858: 4608 mov r0, r1 801685a: 4611 mov r1, r2 801685c: 2200 movs r2, #0 801685e: 4d05 ldr r5, [pc, #20] @ (8016874 <_write_r+0x20>) 8016860: 602a str r2, [r5, #0] 8016862: 461a mov r2, r3 8016864: f7f3 fd90 bl 800a388 <_write> 8016868: 1c43 adds r3, r0, #1 801686a: d102 bne.n 8016872 <_write_r+0x1e> 801686c: 682b ldr r3, [r5, #0] 801686e: b103 cbz r3, 8016872 <_write_r+0x1e> 8016870: 6023 str r3, [r4, #0] 8016872: bd38 pop {r3, r4, r5, pc} 8016874: 200015d4 .word 0x200015d4 08016878 <_close_r>: 8016878: b538 push {r3, r4, r5, lr} 801687a: 2300 movs r3, #0 801687c: 4d05 ldr r5, [pc, #20] @ (8016894 <_close_r+0x1c>) 801687e: 4604 mov r4, r0 8016880: 4608 mov r0, r1 8016882: 602b str r3, [r5, #0] 8016884: f7f7 f80d bl 800d8a2 <_close> 8016888: 1c43 adds r3, r0, #1 801688a: d102 bne.n 8016892 <_close_r+0x1a> 801688c: 682b ldr r3, [r5, #0] 801688e: b103 cbz r3, 8016892 <_close_r+0x1a> 8016890: 6023 str r3, [r4, #0] 8016892: bd38 pop {r3, r4, r5, pc} 8016894: 200015d4 .word 0x200015d4 08016898 : 8016898: 2006 movs r0, #6 801689a: b508 push {r3, lr} 801689c: f000 fae4 bl 8016e68 80168a0: 2001 movs r0, #1 80168a2: f7f6 ffd6 bl 800d852 <_exit> 080168a6 <_calloc_r>: 80168a6: b570 push {r4, r5, r6, lr} 80168a8: fba1 5402 umull r5, r4, r1, r2 80168ac: b934 cbnz r4, 80168bc <_calloc_r+0x16> 80168ae: 4629 mov r1, r5 80168b0: f7ff fa50 bl 8015d54 <_malloc_r> 80168b4: 4606 mov r6, r0 80168b6: b928 cbnz r0, 80168c4 <_calloc_r+0x1e> 80168b8: 4630 mov r0, r6 80168ba: bd70 pop {r4, r5, r6, pc} 80168bc: 220c movs r2, #12 80168be: 2600 movs r6, #0 80168c0: 6002 str r2, [r0, #0] 80168c2: e7f9 b.n 80168b8 <_calloc_r+0x12> 80168c4: 462a mov r2, r5 80168c6: 4621 mov r1, r4 80168c8: f7fe f9f0 bl 8014cac 80168cc: e7f4 b.n 80168b8 <_calloc_r+0x12> ... 080168d0 <_free_r>: 80168d0: b538 push {r3, r4, r5, lr} 80168d2: 4605 mov r5, r0 80168d4: 2900 cmp r1, #0 80168d6: d040 beq.n 801695a <_free_r+0x8a> 80168d8: f851 3c04 ldr.w r3, [r1, #-4] 80168dc: 1f0c subs r4, r1, #4 80168de: 2b00 cmp r3, #0 80168e0: bfb8 it lt 80168e2: 18e4 addlt r4, r4, r3 80168e4: f7ff fb5e bl 8015fa4 <__malloc_lock> 80168e8: 4a1c ldr r2, [pc, #112] @ (801695c <_free_r+0x8c>) 80168ea: 6813 ldr r3, [r2, #0] 80168ec: b933 cbnz r3, 80168fc <_free_r+0x2c> 80168ee: 6063 str r3, [r4, #4] 80168f0: 6014 str r4, [r2, #0] 80168f2: 4628 mov r0, r5 80168f4: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 80168f8: f7ff bb5a b.w 8015fb0 <__malloc_unlock> 80168fc: 42a3 cmp r3, r4 80168fe: d908 bls.n 8016912 <_free_r+0x42> 8016900: 6820 ldr r0, [r4, #0] 8016902: 1821 adds r1, r4, r0 8016904: 428b cmp r3, r1 8016906: bf01 itttt eq 8016908: 6819 ldreq r1, [r3, #0] 801690a: 685b ldreq r3, [r3, #4] 801690c: 1809 addeq r1, r1, r0 801690e: 6021 streq r1, [r4, #0] 8016910: e7ed b.n 80168ee <_free_r+0x1e> 8016912: 461a mov r2, r3 8016914: 685b ldr r3, [r3, #4] 8016916: b10b cbz r3, 801691c <_free_r+0x4c> 8016918: 42a3 cmp r3, r4 801691a: d9fa bls.n 8016912 <_free_r+0x42> 801691c: 6811 ldr r1, [r2, #0] 801691e: 1850 adds r0, r2, r1 8016920: 42a0 cmp r0, r4 8016922: d10b bne.n 801693c <_free_r+0x6c> 8016924: 6820 ldr r0, [r4, #0] 8016926: 4401 add r1, r0 8016928: 1850 adds r0, r2, r1 801692a: 4283 cmp r3, r0 801692c: 6011 str r1, [r2, #0] 801692e: d1e0 bne.n 80168f2 <_free_r+0x22> 8016930: 6818 ldr r0, [r3, #0] 8016932: 685b ldr r3, [r3, #4] 8016934: 4408 add r0, r1 8016936: 6010 str r0, [r2, #0] 8016938: 6053 str r3, [r2, #4] 801693a: e7da b.n 80168f2 <_free_r+0x22> 801693c: d902 bls.n 8016944 <_free_r+0x74> 801693e: 230c movs r3, #12 8016940: 602b str r3, [r5, #0] 8016942: e7d6 b.n 80168f2 <_free_r+0x22> 8016944: 6820 ldr r0, [r4, #0] 8016946: 1821 adds r1, r4, r0 8016948: 428b cmp r3, r1 801694a: bf01 itttt eq 801694c: 6819 ldreq r1, [r3, #0] 801694e: 685b ldreq r3, [r3, #4] 8016950: 1809 addeq r1, r1, r0 8016952: 6021 streq r1, [r4, #0] 8016954: 6063 str r3, [r4, #4] 8016956: 6054 str r4, [r2, #4] 8016958: e7cb b.n 80168f2 <_free_r+0x22> 801695a: bd38 pop {r3, r4, r5, pc} 801695c: 200015d0 .word 0x200015d0 08016960 <__sfputc_r>: 8016960: 6893 ldr r3, [r2, #8] 8016962: b410 push {r4} 8016964: 3b01 subs r3, #1 8016966: 2b00 cmp r3, #0 8016968: 6093 str r3, [r2, #8] 801696a: da07 bge.n 801697c <__sfputc_r+0x1c> 801696c: 6994 ldr r4, [r2, #24] 801696e: 42a3 cmp r3, r4 8016970: db01 blt.n 8016976 <__sfputc_r+0x16> 8016972: 290a cmp r1, #10 8016974: d102 bne.n 801697c <__sfputc_r+0x1c> 8016976: bc10 pop {r4} 8016978: f000 b94c b.w 8016c14 <__swbuf_r> 801697c: 6813 ldr r3, [r2, #0] 801697e: 1c58 adds r0, r3, #1 8016980: 6010 str r0, [r2, #0] 8016982: 7019 strb r1, [r3, #0] 8016984: 4608 mov r0, r1 8016986: bc10 pop {r4} 8016988: 4770 bx lr 0801698a <__sfputs_r>: 801698a: b5f8 push {r3, r4, r5, r6, r7, lr} 801698c: 4606 mov r6, r0 801698e: 460f mov r7, r1 8016990: 4614 mov r4, r2 8016992: 18d5 adds r5, r2, r3 8016994: 42ac cmp r4, r5 8016996: d101 bne.n 801699c <__sfputs_r+0x12> 8016998: 2000 movs r0, #0 801699a: e007 b.n 80169ac <__sfputs_r+0x22> 801699c: 463a mov r2, r7 801699e: 4630 mov r0, r6 80169a0: f814 1b01 ldrb.w r1, [r4], #1 80169a4: f7ff ffdc bl 8016960 <__sfputc_r> 80169a8: 1c43 adds r3, r0, #1 80169aa: d1f3 bne.n 8016994 <__sfputs_r+0xa> 80169ac: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 080169b0 <_vfiprintf_r>: 80169b0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80169b4: 460d mov r5, r1 80169b6: 4614 mov r4, r2 80169b8: 4698 mov r8, r3 80169ba: 4606 mov r6, r0 80169bc: b09d sub sp, #116 @ 0x74 80169be: b118 cbz r0, 80169c8 <_vfiprintf_r+0x18> 80169c0: 6a03 ldr r3, [r0, #32] 80169c2: b90b cbnz r3, 80169c8 <_vfiprintf_r+0x18> 80169c4: f7fe f900 bl 8014bc8 <__sinit> 80169c8: 6e6b ldr r3, [r5, #100] @ 0x64 80169ca: 07d9 lsls r1, r3, #31 80169cc: d405 bmi.n 80169da <_vfiprintf_r+0x2a> 80169ce: 89ab ldrh r3, [r5, #12] 80169d0: 059a lsls r2, r3, #22 80169d2: d402 bmi.n 80169da <_vfiprintf_r+0x2a> 80169d4: 6da8 ldr r0, [r5, #88] @ 0x58 80169d6: f7fe f99c bl 8014d12 <__retarget_lock_acquire_recursive> 80169da: 89ab ldrh r3, [r5, #12] 80169dc: 071b lsls r3, r3, #28 80169de: d501 bpl.n 80169e4 <_vfiprintf_r+0x34> 80169e0: 692b ldr r3, [r5, #16] 80169e2: b99b cbnz r3, 8016a0c <_vfiprintf_r+0x5c> 80169e4: 4629 mov r1, r5 80169e6: 4630 mov r0, r6 80169e8: f000 f952 bl 8016c90 <__swsetup_r> 80169ec: b170 cbz r0, 8016a0c <_vfiprintf_r+0x5c> 80169ee: 6e6b ldr r3, [r5, #100] @ 0x64 80169f0: 07dc lsls r4, r3, #31 80169f2: d504 bpl.n 80169fe <_vfiprintf_r+0x4e> 80169f4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80169f8: b01d add sp, #116 @ 0x74 80169fa: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80169fe: 89ab ldrh r3, [r5, #12] 8016a00: 0598 lsls r0, r3, #22 8016a02: d4f7 bmi.n 80169f4 <_vfiprintf_r+0x44> 8016a04: 6da8 ldr r0, [r5, #88] @ 0x58 8016a06: f7fe f985 bl 8014d14 <__retarget_lock_release_recursive> 8016a0a: e7f3 b.n 80169f4 <_vfiprintf_r+0x44> 8016a0c: 2300 movs r3, #0 8016a0e: 9309 str r3, [sp, #36] @ 0x24 8016a10: 2320 movs r3, #32 8016a12: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8016a16: 2330 movs r3, #48 @ 0x30 8016a18: f04f 0901 mov.w r9, #1 8016a1c: f8cd 800c str.w r8, [sp, #12] 8016a20: f8df 81a8 ldr.w r8, [pc, #424] @ 8016bcc <_vfiprintf_r+0x21c> 8016a24: f88d 302a strb.w r3, [sp, #42] @ 0x2a 8016a28: 4623 mov r3, r4 8016a2a: 469a mov sl, r3 8016a2c: f813 2b01 ldrb.w r2, [r3], #1 8016a30: b10a cbz r2, 8016a36 <_vfiprintf_r+0x86> 8016a32: 2a25 cmp r2, #37 @ 0x25 8016a34: d1f9 bne.n 8016a2a <_vfiprintf_r+0x7a> 8016a36: ebba 0b04 subs.w fp, sl, r4 8016a3a: d00b beq.n 8016a54 <_vfiprintf_r+0xa4> 8016a3c: 465b mov r3, fp 8016a3e: 4622 mov r2, r4 8016a40: 4629 mov r1, r5 8016a42: 4630 mov r0, r6 8016a44: f7ff ffa1 bl 801698a <__sfputs_r> 8016a48: 3001 adds r0, #1 8016a4a: f000 80a7 beq.w 8016b9c <_vfiprintf_r+0x1ec> 8016a4e: 9a09 ldr r2, [sp, #36] @ 0x24 8016a50: 445a add r2, fp 8016a52: 9209 str r2, [sp, #36] @ 0x24 8016a54: f89a 3000 ldrb.w r3, [sl] 8016a58: 2b00 cmp r3, #0 8016a5a: f000 809f beq.w 8016b9c <_vfiprintf_r+0x1ec> 8016a5e: 2300 movs r3, #0 8016a60: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8016a64: e9cd 2305 strd r2, r3, [sp, #20] 8016a68: f10a 0a01 add.w sl, sl, #1 8016a6c: 9304 str r3, [sp, #16] 8016a6e: 9307 str r3, [sp, #28] 8016a70: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8016a74: 931a str r3, [sp, #104] @ 0x68 8016a76: 4654 mov r4, sl 8016a78: 2205 movs r2, #5 8016a7a: f814 1b01 ldrb.w r1, [r4], #1 8016a7e: 4853 ldr r0, [pc, #332] @ (8016bcc <_vfiprintf_r+0x21c>) 8016a80: f7fe f94e bl 8014d20 8016a84: 9a04 ldr r2, [sp, #16] 8016a86: b9d8 cbnz r0, 8016ac0 <_vfiprintf_r+0x110> 8016a88: 06d1 lsls r1, r2, #27 8016a8a: bf44 itt mi 8016a8c: 2320 movmi r3, #32 8016a8e: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8016a92: 0713 lsls r3, r2, #28 8016a94: bf44 itt mi 8016a96: 232b movmi r3, #43 @ 0x2b 8016a98: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8016a9c: f89a 3000 ldrb.w r3, [sl] 8016aa0: 2b2a cmp r3, #42 @ 0x2a 8016aa2: d015 beq.n 8016ad0 <_vfiprintf_r+0x120> 8016aa4: 4654 mov r4, sl 8016aa6: 2000 movs r0, #0 8016aa8: f04f 0c0a mov.w ip, #10 8016aac: 9a07 ldr r2, [sp, #28] 8016aae: 4621 mov r1, r4 8016ab0: f811 3b01 ldrb.w r3, [r1], #1 8016ab4: 3b30 subs r3, #48 @ 0x30 8016ab6: 2b09 cmp r3, #9 8016ab8: d94b bls.n 8016b52 <_vfiprintf_r+0x1a2> 8016aba: b1b0 cbz r0, 8016aea <_vfiprintf_r+0x13a> 8016abc: 9207 str r2, [sp, #28] 8016abe: e014 b.n 8016aea <_vfiprintf_r+0x13a> 8016ac0: eba0 0308 sub.w r3, r0, r8 8016ac4: fa09 f303 lsl.w r3, r9, r3 8016ac8: 4313 orrs r3, r2 8016aca: 46a2 mov sl, r4 8016acc: 9304 str r3, [sp, #16] 8016ace: e7d2 b.n 8016a76 <_vfiprintf_r+0xc6> 8016ad0: 9b03 ldr r3, [sp, #12] 8016ad2: 1d19 adds r1, r3, #4 8016ad4: 681b ldr r3, [r3, #0] 8016ad6: 9103 str r1, [sp, #12] 8016ad8: 2b00 cmp r3, #0 8016ada: bfbb ittet lt 8016adc: 425b neglt r3, r3 8016ade: f042 0202 orrlt.w r2, r2, #2 8016ae2: 9307 strge r3, [sp, #28] 8016ae4: 9307 strlt r3, [sp, #28] 8016ae6: bfb8 it lt 8016ae8: 9204 strlt r2, [sp, #16] 8016aea: 7823 ldrb r3, [r4, #0] 8016aec: 2b2e cmp r3, #46 @ 0x2e 8016aee: d10a bne.n 8016b06 <_vfiprintf_r+0x156> 8016af0: 7863 ldrb r3, [r4, #1] 8016af2: 2b2a cmp r3, #42 @ 0x2a 8016af4: d132 bne.n 8016b5c <_vfiprintf_r+0x1ac> 8016af6: 9b03 ldr r3, [sp, #12] 8016af8: 3402 adds r4, #2 8016afa: 1d1a adds r2, r3, #4 8016afc: 681b ldr r3, [r3, #0] 8016afe: 9203 str r2, [sp, #12] 8016b00: ea43 73e3 orr.w r3, r3, r3, asr #31 8016b04: 9305 str r3, [sp, #20] 8016b06: f8df a0c8 ldr.w sl, [pc, #200] @ 8016bd0 <_vfiprintf_r+0x220> 8016b0a: 2203 movs r2, #3 8016b0c: 4650 mov r0, sl 8016b0e: 7821 ldrb r1, [r4, #0] 8016b10: f7fe f906 bl 8014d20 8016b14: b138 cbz r0, 8016b26 <_vfiprintf_r+0x176> 8016b16: 2240 movs r2, #64 @ 0x40 8016b18: 9b04 ldr r3, [sp, #16] 8016b1a: eba0 000a sub.w r0, r0, sl 8016b1e: 4082 lsls r2, r0 8016b20: 4313 orrs r3, r2 8016b22: 3401 adds r4, #1 8016b24: 9304 str r3, [sp, #16] 8016b26: f814 1b01 ldrb.w r1, [r4], #1 8016b2a: 2206 movs r2, #6 8016b2c: 4829 ldr r0, [pc, #164] @ (8016bd4 <_vfiprintf_r+0x224>) 8016b2e: f88d 1028 strb.w r1, [sp, #40] @ 0x28 8016b32: f7fe f8f5 bl 8014d20 8016b36: 2800 cmp r0, #0 8016b38: d03f beq.n 8016bba <_vfiprintf_r+0x20a> 8016b3a: 4b27 ldr r3, [pc, #156] @ (8016bd8 <_vfiprintf_r+0x228>) 8016b3c: bb1b cbnz r3, 8016b86 <_vfiprintf_r+0x1d6> 8016b3e: 9b03 ldr r3, [sp, #12] 8016b40: 3307 adds r3, #7 8016b42: f023 0307 bic.w r3, r3, #7 8016b46: 3308 adds r3, #8 8016b48: 9303 str r3, [sp, #12] 8016b4a: 9b09 ldr r3, [sp, #36] @ 0x24 8016b4c: 443b add r3, r7 8016b4e: 9309 str r3, [sp, #36] @ 0x24 8016b50: e76a b.n 8016a28 <_vfiprintf_r+0x78> 8016b52: 460c mov r4, r1 8016b54: 2001 movs r0, #1 8016b56: fb0c 3202 mla r2, ip, r2, r3 8016b5a: e7a8 b.n 8016aae <_vfiprintf_r+0xfe> 8016b5c: 2300 movs r3, #0 8016b5e: f04f 0c0a mov.w ip, #10 8016b62: 4619 mov r1, r3 8016b64: 3401 adds r4, #1 8016b66: 9305 str r3, [sp, #20] 8016b68: 4620 mov r0, r4 8016b6a: f810 2b01 ldrb.w r2, [r0], #1 8016b6e: 3a30 subs r2, #48 @ 0x30 8016b70: 2a09 cmp r2, #9 8016b72: d903 bls.n 8016b7c <_vfiprintf_r+0x1cc> 8016b74: 2b00 cmp r3, #0 8016b76: d0c6 beq.n 8016b06 <_vfiprintf_r+0x156> 8016b78: 9105 str r1, [sp, #20] 8016b7a: e7c4 b.n 8016b06 <_vfiprintf_r+0x156> 8016b7c: 4604 mov r4, r0 8016b7e: 2301 movs r3, #1 8016b80: fb0c 2101 mla r1, ip, r1, r2 8016b84: e7f0 b.n 8016b68 <_vfiprintf_r+0x1b8> 8016b86: ab03 add r3, sp, #12 8016b88: 9300 str r3, [sp, #0] 8016b8a: 462a mov r2, r5 8016b8c: 4630 mov r0, r6 8016b8e: 4b13 ldr r3, [pc, #76] @ (8016bdc <_vfiprintf_r+0x22c>) 8016b90: a904 add r1, sp, #16 8016b92: f7fd fbd1 bl 8014338 <_printf_float> 8016b96: 4607 mov r7, r0 8016b98: 1c78 adds r0, r7, #1 8016b9a: d1d6 bne.n 8016b4a <_vfiprintf_r+0x19a> 8016b9c: 6e6b ldr r3, [r5, #100] @ 0x64 8016b9e: 07d9 lsls r1, r3, #31 8016ba0: d405 bmi.n 8016bae <_vfiprintf_r+0x1fe> 8016ba2: 89ab ldrh r3, [r5, #12] 8016ba4: 059a lsls r2, r3, #22 8016ba6: d402 bmi.n 8016bae <_vfiprintf_r+0x1fe> 8016ba8: 6da8 ldr r0, [r5, #88] @ 0x58 8016baa: f7fe f8b3 bl 8014d14 <__retarget_lock_release_recursive> 8016bae: 89ab ldrh r3, [r5, #12] 8016bb0: 065b lsls r3, r3, #25 8016bb2: f53f af1f bmi.w 80169f4 <_vfiprintf_r+0x44> 8016bb6: 9809 ldr r0, [sp, #36] @ 0x24 8016bb8: e71e b.n 80169f8 <_vfiprintf_r+0x48> 8016bba: ab03 add r3, sp, #12 8016bbc: 9300 str r3, [sp, #0] 8016bbe: 462a mov r2, r5 8016bc0: 4630 mov r0, r6 8016bc2: 4b06 ldr r3, [pc, #24] @ (8016bdc <_vfiprintf_r+0x22c>) 8016bc4: a904 add r1, sp, #16 8016bc6: f7fd fe55 bl 8014874 <_printf_i> 8016bca: e7e4 b.n 8016b96 <_vfiprintf_r+0x1e6> 8016bcc: 08017a51 .word 0x08017a51 8016bd0: 08017a57 .word 0x08017a57 8016bd4: 08017a5b .word 0x08017a5b 8016bd8: 08014339 .word 0x08014339 8016bdc: 0801698b .word 0x0801698b 08016be0 <__ascii_mbtowc>: 8016be0: b082 sub sp, #8 8016be2: b901 cbnz r1, 8016be6 <__ascii_mbtowc+0x6> 8016be4: a901 add r1, sp, #4 8016be6: b142 cbz r2, 8016bfa <__ascii_mbtowc+0x1a> 8016be8: b14b cbz r3, 8016bfe <__ascii_mbtowc+0x1e> 8016bea: 7813 ldrb r3, [r2, #0] 8016bec: 600b str r3, [r1, #0] 8016bee: 7812 ldrb r2, [r2, #0] 8016bf0: 1e10 subs r0, r2, #0 8016bf2: bf18 it ne 8016bf4: 2001 movne r0, #1 8016bf6: b002 add sp, #8 8016bf8: 4770 bx lr 8016bfa: 4610 mov r0, r2 8016bfc: e7fb b.n 8016bf6 <__ascii_mbtowc+0x16> 8016bfe: f06f 0001 mvn.w r0, #1 8016c02: e7f8 b.n 8016bf6 <__ascii_mbtowc+0x16> 08016c04 <_malloc_usable_size_r>: 8016c04: f851 3c04 ldr.w r3, [r1, #-4] 8016c08: 1f18 subs r0, r3, #4 8016c0a: 2b00 cmp r3, #0 8016c0c: bfbc itt lt 8016c0e: 580b ldrlt r3, [r1, r0] 8016c10: 18c0 addlt r0, r0, r3 8016c12: 4770 bx lr 08016c14 <__swbuf_r>: 8016c14: b5f8 push {r3, r4, r5, r6, r7, lr} 8016c16: 460e mov r6, r1 8016c18: 4614 mov r4, r2 8016c1a: 4605 mov r5, r0 8016c1c: b118 cbz r0, 8016c26 <__swbuf_r+0x12> 8016c1e: 6a03 ldr r3, [r0, #32] 8016c20: b90b cbnz r3, 8016c26 <__swbuf_r+0x12> 8016c22: f7fd ffd1 bl 8014bc8 <__sinit> 8016c26: 69a3 ldr r3, [r4, #24] 8016c28: 60a3 str r3, [r4, #8] 8016c2a: 89a3 ldrh r3, [r4, #12] 8016c2c: 071a lsls r2, r3, #28 8016c2e: d501 bpl.n 8016c34 <__swbuf_r+0x20> 8016c30: 6923 ldr r3, [r4, #16] 8016c32: b943 cbnz r3, 8016c46 <__swbuf_r+0x32> 8016c34: 4621 mov r1, r4 8016c36: 4628 mov r0, r5 8016c38: f000 f82a bl 8016c90 <__swsetup_r> 8016c3c: b118 cbz r0, 8016c46 <__swbuf_r+0x32> 8016c3e: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff 8016c42: 4638 mov r0, r7 8016c44: bdf8 pop {r3, r4, r5, r6, r7, pc} 8016c46: 6823 ldr r3, [r4, #0] 8016c48: 6922 ldr r2, [r4, #16] 8016c4a: b2f6 uxtb r6, r6 8016c4c: 1a98 subs r0, r3, r2 8016c4e: 6963 ldr r3, [r4, #20] 8016c50: 4637 mov r7, r6 8016c52: 4283 cmp r3, r0 8016c54: dc05 bgt.n 8016c62 <__swbuf_r+0x4e> 8016c56: 4621 mov r1, r4 8016c58: 4628 mov r0, r5 8016c5a: f7ff f97b bl 8015f54 <_fflush_r> 8016c5e: 2800 cmp r0, #0 8016c60: d1ed bne.n 8016c3e <__swbuf_r+0x2a> 8016c62: 68a3 ldr r3, [r4, #8] 8016c64: 3b01 subs r3, #1 8016c66: 60a3 str r3, [r4, #8] 8016c68: 6823 ldr r3, [r4, #0] 8016c6a: 1c5a adds r2, r3, #1 8016c6c: 6022 str r2, [r4, #0] 8016c6e: 701e strb r6, [r3, #0] 8016c70: 6962 ldr r2, [r4, #20] 8016c72: 1c43 adds r3, r0, #1 8016c74: 429a cmp r2, r3 8016c76: d004 beq.n 8016c82 <__swbuf_r+0x6e> 8016c78: 89a3 ldrh r3, [r4, #12] 8016c7a: 07db lsls r3, r3, #31 8016c7c: d5e1 bpl.n 8016c42 <__swbuf_r+0x2e> 8016c7e: 2e0a cmp r6, #10 8016c80: d1df bne.n 8016c42 <__swbuf_r+0x2e> 8016c82: 4621 mov r1, r4 8016c84: 4628 mov r0, r5 8016c86: f7ff f965 bl 8015f54 <_fflush_r> 8016c8a: 2800 cmp r0, #0 8016c8c: d0d9 beq.n 8016c42 <__swbuf_r+0x2e> 8016c8e: e7d6 b.n 8016c3e <__swbuf_r+0x2a> 08016c90 <__swsetup_r>: 8016c90: b538 push {r3, r4, r5, lr} 8016c92: 4b29 ldr r3, [pc, #164] @ (8016d38 <__swsetup_r+0xa8>) 8016c94: 4605 mov r5, r0 8016c96: 6818 ldr r0, [r3, #0] 8016c98: 460c mov r4, r1 8016c9a: b118 cbz r0, 8016ca4 <__swsetup_r+0x14> 8016c9c: 6a03 ldr r3, [r0, #32] 8016c9e: b90b cbnz r3, 8016ca4 <__swsetup_r+0x14> 8016ca0: f7fd ff92 bl 8014bc8 <__sinit> 8016ca4: f9b4 300c ldrsh.w r3, [r4, #12] 8016ca8: 0719 lsls r1, r3, #28 8016caa: d422 bmi.n 8016cf2 <__swsetup_r+0x62> 8016cac: 06da lsls r2, r3, #27 8016cae: d407 bmi.n 8016cc0 <__swsetup_r+0x30> 8016cb0: 2209 movs r2, #9 8016cb2: 602a str r2, [r5, #0] 8016cb4: f043 0340 orr.w r3, r3, #64 @ 0x40 8016cb8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016cbc: 81a3 strh r3, [r4, #12] 8016cbe: e033 b.n 8016d28 <__swsetup_r+0x98> 8016cc0: 0758 lsls r0, r3, #29 8016cc2: d512 bpl.n 8016cea <__swsetup_r+0x5a> 8016cc4: 6b61 ldr r1, [r4, #52] @ 0x34 8016cc6: b141 cbz r1, 8016cda <__swsetup_r+0x4a> 8016cc8: f104 0344 add.w r3, r4, #68 @ 0x44 8016ccc: 4299 cmp r1, r3 8016cce: d002 beq.n 8016cd6 <__swsetup_r+0x46> 8016cd0: 4628 mov r0, r5 8016cd2: f7ff fdfd bl 80168d0 <_free_r> 8016cd6: 2300 movs r3, #0 8016cd8: 6363 str r3, [r4, #52] @ 0x34 8016cda: 89a3 ldrh r3, [r4, #12] 8016cdc: f023 0324 bic.w r3, r3, #36 @ 0x24 8016ce0: 81a3 strh r3, [r4, #12] 8016ce2: 2300 movs r3, #0 8016ce4: 6063 str r3, [r4, #4] 8016ce6: 6923 ldr r3, [r4, #16] 8016ce8: 6023 str r3, [r4, #0] 8016cea: 89a3 ldrh r3, [r4, #12] 8016cec: f043 0308 orr.w r3, r3, #8 8016cf0: 81a3 strh r3, [r4, #12] 8016cf2: 6923 ldr r3, [r4, #16] 8016cf4: b94b cbnz r3, 8016d0a <__swsetup_r+0x7a> 8016cf6: 89a3 ldrh r3, [r4, #12] 8016cf8: f403 7320 and.w r3, r3, #640 @ 0x280 8016cfc: f5b3 7f00 cmp.w r3, #512 @ 0x200 8016d00: d003 beq.n 8016d0a <__swsetup_r+0x7a> 8016d02: 4621 mov r1, r4 8016d04: 4628 mov r0, r5 8016d06: f000 f84b bl 8016da0 <__smakebuf_r> 8016d0a: f9b4 300c ldrsh.w r3, [r4, #12] 8016d0e: f013 0201 ands.w r2, r3, #1 8016d12: d00a beq.n 8016d2a <__swsetup_r+0x9a> 8016d14: 2200 movs r2, #0 8016d16: 60a2 str r2, [r4, #8] 8016d18: 6962 ldr r2, [r4, #20] 8016d1a: 4252 negs r2, r2 8016d1c: 61a2 str r2, [r4, #24] 8016d1e: 6922 ldr r2, [r4, #16] 8016d20: b942 cbnz r2, 8016d34 <__swsetup_r+0xa4> 8016d22: f013 0080 ands.w r0, r3, #128 @ 0x80 8016d26: d1c5 bne.n 8016cb4 <__swsetup_r+0x24> 8016d28: bd38 pop {r3, r4, r5, pc} 8016d2a: 0799 lsls r1, r3, #30 8016d2c: bf58 it pl 8016d2e: 6962 ldrpl r2, [r4, #20] 8016d30: 60a2 str r2, [r4, #8] 8016d32: e7f4 b.n 8016d1e <__swsetup_r+0x8e> 8016d34: 2000 movs r0, #0 8016d36: e7f7 b.n 8016d28 <__swsetup_r+0x98> 8016d38: 2000009c .word 0x2000009c 08016d3c <__ascii_wctomb>: 8016d3c: 4603 mov r3, r0 8016d3e: 4608 mov r0, r1 8016d40: b141 cbz r1, 8016d54 <__ascii_wctomb+0x18> 8016d42: 2aff cmp r2, #255 @ 0xff 8016d44: d904 bls.n 8016d50 <__ascii_wctomb+0x14> 8016d46: 228a movs r2, #138 @ 0x8a 8016d48: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016d4c: 601a str r2, [r3, #0] 8016d4e: 4770 bx lr 8016d50: 2001 movs r0, #1 8016d52: 700a strb r2, [r1, #0] 8016d54: 4770 bx lr 08016d56 <__swhatbuf_r>: 8016d56: b570 push {r4, r5, r6, lr} 8016d58: 460c mov r4, r1 8016d5a: f9b1 100e ldrsh.w r1, [r1, #14] 8016d5e: 4615 mov r5, r2 8016d60: 2900 cmp r1, #0 8016d62: 461e mov r6, r3 8016d64: b096 sub sp, #88 @ 0x58 8016d66: da0c bge.n 8016d82 <__swhatbuf_r+0x2c> 8016d68: 89a3 ldrh r3, [r4, #12] 8016d6a: 2100 movs r1, #0 8016d6c: f013 0f80 tst.w r3, #128 @ 0x80 8016d70: bf14 ite ne 8016d72: 2340 movne r3, #64 @ 0x40 8016d74: f44f 6380 moveq.w r3, #1024 @ 0x400 8016d78: 2000 movs r0, #0 8016d7a: 6031 str r1, [r6, #0] 8016d7c: 602b str r3, [r5, #0] 8016d7e: b016 add sp, #88 @ 0x58 8016d80: bd70 pop {r4, r5, r6, pc} 8016d82: 466a mov r2, sp 8016d84: f000 f89c bl 8016ec0 <_fstat_r> 8016d88: 2800 cmp r0, #0 8016d8a: dbed blt.n 8016d68 <__swhatbuf_r+0x12> 8016d8c: 9901 ldr r1, [sp, #4] 8016d8e: f401 4170 and.w r1, r1, #61440 @ 0xf000 8016d92: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 8016d96: 4259 negs r1, r3 8016d98: 4159 adcs r1, r3 8016d9a: f44f 6380 mov.w r3, #1024 @ 0x400 8016d9e: e7eb b.n 8016d78 <__swhatbuf_r+0x22> 08016da0 <__smakebuf_r>: 8016da0: 898b ldrh r3, [r1, #12] 8016da2: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8016da4: 079d lsls r5, r3, #30 8016da6: 4606 mov r6, r0 8016da8: 460c mov r4, r1 8016daa: d507 bpl.n 8016dbc <__smakebuf_r+0x1c> 8016dac: f104 0347 add.w r3, r4, #71 @ 0x47 8016db0: 6023 str r3, [r4, #0] 8016db2: 6123 str r3, [r4, #16] 8016db4: 2301 movs r3, #1 8016db6: 6163 str r3, [r4, #20] 8016db8: b003 add sp, #12 8016dba: bdf0 pop {r4, r5, r6, r7, pc} 8016dbc: 466a mov r2, sp 8016dbe: ab01 add r3, sp, #4 8016dc0: f7ff ffc9 bl 8016d56 <__swhatbuf_r> 8016dc4: 9f00 ldr r7, [sp, #0] 8016dc6: 4605 mov r5, r0 8016dc8: 4639 mov r1, r7 8016dca: 4630 mov r0, r6 8016dcc: f7fe ffc2 bl 8015d54 <_malloc_r> 8016dd0: b948 cbnz r0, 8016de6 <__smakebuf_r+0x46> 8016dd2: f9b4 300c ldrsh.w r3, [r4, #12] 8016dd6: 059a lsls r2, r3, #22 8016dd8: d4ee bmi.n 8016db8 <__smakebuf_r+0x18> 8016dda: f023 0303 bic.w r3, r3, #3 8016dde: f043 0302 orr.w r3, r3, #2 8016de2: 81a3 strh r3, [r4, #12] 8016de4: e7e2 b.n 8016dac <__smakebuf_r+0xc> 8016de6: 89a3 ldrh r3, [r4, #12] 8016de8: e9c4 0704 strd r0, r7, [r4, #16] 8016dec: f043 0380 orr.w r3, r3, #128 @ 0x80 8016df0: 81a3 strh r3, [r4, #12] 8016df2: 9b01 ldr r3, [sp, #4] 8016df4: 6020 str r0, [r4, #0] 8016df6: b15b cbz r3, 8016e10 <__smakebuf_r+0x70> 8016df8: 4630 mov r0, r6 8016dfa: f9b4 100e ldrsh.w r1, [r4, #14] 8016dfe: f000 f83b bl 8016e78 <_isatty_r> 8016e02: b128 cbz r0, 8016e10 <__smakebuf_r+0x70> 8016e04: 89a3 ldrh r3, [r4, #12] 8016e06: f023 0303 bic.w r3, r3, #3 8016e0a: f043 0301 orr.w r3, r3, #1 8016e0e: 81a3 strh r3, [r4, #12] 8016e10: 89a3 ldrh r3, [r4, #12] 8016e12: 431d orrs r5, r3 8016e14: 81a5 strh r5, [r4, #12] 8016e16: e7cf b.n 8016db8 <__smakebuf_r+0x18> 08016e18 <_raise_r>: 8016e18: 291f cmp r1, #31 8016e1a: b538 push {r3, r4, r5, lr} 8016e1c: 4605 mov r5, r0 8016e1e: 460c mov r4, r1 8016e20: d904 bls.n 8016e2c <_raise_r+0x14> 8016e22: 2316 movs r3, #22 8016e24: 6003 str r3, [r0, #0] 8016e26: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016e2a: bd38 pop {r3, r4, r5, pc} 8016e2c: 6bc2 ldr r2, [r0, #60] @ 0x3c 8016e2e: b112 cbz r2, 8016e36 <_raise_r+0x1e> 8016e30: f852 3021 ldr.w r3, [r2, r1, lsl #2] 8016e34: b94b cbnz r3, 8016e4a <_raise_r+0x32> 8016e36: 4628 mov r0, r5 8016e38: f000 f840 bl 8016ebc <_getpid_r> 8016e3c: 4622 mov r2, r4 8016e3e: 4601 mov r1, r0 8016e40: 4628 mov r0, r5 8016e42: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8016e46: f000 b827 b.w 8016e98 <_kill_r> 8016e4a: 2b01 cmp r3, #1 8016e4c: d00a beq.n 8016e64 <_raise_r+0x4c> 8016e4e: 1c59 adds r1, r3, #1 8016e50: d103 bne.n 8016e5a <_raise_r+0x42> 8016e52: 2316 movs r3, #22 8016e54: 6003 str r3, [r0, #0] 8016e56: 2001 movs r0, #1 8016e58: e7e7 b.n 8016e2a <_raise_r+0x12> 8016e5a: 2100 movs r1, #0 8016e5c: 4620 mov r0, r4 8016e5e: f842 1024 str.w r1, [r2, r4, lsl #2] 8016e62: 4798 blx r3 8016e64: 2000 movs r0, #0 8016e66: e7e0 b.n 8016e2a <_raise_r+0x12> 08016e68 : 8016e68: 4b02 ldr r3, [pc, #8] @ (8016e74 ) 8016e6a: 4601 mov r1, r0 8016e6c: 6818 ldr r0, [r3, #0] 8016e6e: f7ff bfd3 b.w 8016e18 <_raise_r> 8016e72: bf00 nop 8016e74: 2000009c .word 0x2000009c 08016e78 <_isatty_r>: 8016e78: b538 push {r3, r4, r5, lr} 8016e7a: 2300 movs r3, #0 8016e7c: 4d05 ldr r5, [pc, #20] @ (8016e94 <_isatty_r+0x1c>) 8016e7e: 4604 mov r4, r0 8016e80: 4608 mov r0, r1 8016e82: 602b str r3, [r5, #0] 8016e84: f7f6 fd27 bl 800d8d6 <_isatty> 8016e88: 1c43 adds r3, r0, #1 8016e8a: d102 bne.n 8016e92 <_isatty_r+0x1a> 8016e8c: 682b ldr r3, [r5, #0] 8016e8e: b103 cbz r3, 8016e92 <_isatty_r+0x1a> 8016e90: 6023 str r3, [r4, #0] 8016e92: bd38 pop {r3, r4, r5, pc} 8016e94: 200015d4 .word 0x200015d4 08016e98 <_kill_r>: 8016e98: b538 push {r3, r4, r5, lr} 8016e9a: 2300 movs r3, #0 8016e9c: 4d06 ldr r5, [pc, #24] @ (8016eb8 <_kill_r+0x20>) 8016e9e: 4604 mov r4, r0 8016ea0: 4608 mov r0, r1 8016ea2: 4611 mov r1, r2 8016ea4: 602b str r3, [r5, #0] 8016ea6: f7f6 fcc4 bl 800d832 <_kill> 8016eaa: 1c43 adds r3, r0, #1 8016eac: d102 bne.n 8016eb4 <_kill_r+0x1c> 8016eae: 682b ldr r3, [r5, #0] 8016eb0: b103 cbz r3, 8016eb4 <_kill_r+0x1c> 8016eb2: 6023 str r3, [r4, #0] 8016eb4: bd38 pop {r3, r4, r5, pc} 8016eb6: bf00 nop 8016eb8: 200015d4 .word 0x200015d4 08016ebc <_getpid_r>: 8016ebc: f7f6 bcb2 b.w 800d824 <_getpid> 08016ec0 <_fstat_r>: 8016ec0: b538 push {r3, r4, r5, lr} 8016ec2: 2300 movs r3, #0 8016ec4: 4d06 ldr r5, [pc, #24] @ (8016ee0 <_fstat_r+0x20>) 8016ec6: 4604 mov r4, r0 8016ec8: 4608 mov r0, r1 8016eca: 4611 mov r1, r2 8016ecc: 602b str r3, [r5, #0] 8016ece: f7f6 fcf3 bl 800d8b8 <_fstat> 8016ed2: 1c43 adds r3, r0, #1 8016ed4: d102 bne.n 8016edc <_fstat_r+0x1c> 8016ed6: 682b ldr r3, [r5, #0] 8016ed8: b103 cbz r3, 8016edc <_fstat_r+0x1c> 8016eda: 6023 str r3, [r4, #0] 8016edc: bd38 pop {r3, r4, r5, pc} 8016ede: bf00 nop 8016ee0: 200015d4 .word 0x200015d4 08016ee4 <_init>: 8016ee4: b5f8 push {r3, r4, r5, r6, r7, lr} 8016ee6: bf00 nop 8016ee8: bcf8 pop {r3, r4, r5, r6, r7} 8016eea: bc08 pop {r3} 8016eec: 469e mov lr, r3 8016eee: 4770 bx lr 08016ef0 <_fini>: 8016ef0: b5f8 push {r3, r4, r5, r6, r7, lr} 8016ef2: bf00 nop 8016ef4: bcf8 pop {r3, r4, r5, r6, r7} 8016ef6: bc08 pop {r3} 8016ef8: 469e mov lr, r3 8016efa: 4770 bx lr