CCSModuleSW30Web.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001e4 08008000 08008000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000dae8 080081e8 080081e8 000011e8 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 000007ec 08015cd0 08015cd0 0000ecd0 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 080164bc 080164bc 00010240 2**0 CONTENTS 4 .ARM 00000008 080164bc 080164bc 0000f4bc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 080164c4 080164c4 00010240 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 080164c4 080164c4 0000f4c4 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 080164c8 080164c8 0000f4c8 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000240 20000000 080164cc 00010000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000010ec 20000240 0801670c 00010240 2**3 ALLOC 10 ._user_heap_stack 00000604 2000132c 0801670c 0001032c 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 00010240 2**0 CONTENTS, READONLY 12 .debug_info 0001bc86 00000000 00000000 00010269 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00005452 00000000 00000000 0002beef 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 000016c0 00000000 00000000 00031348 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00001178 00000000 00000000 00032a08 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00026207 00000000 00000000 00033b80 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 000201e3 00000000 00000000 00059d87 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000c9740 00000000 00000000 00079f6a 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 001436aa 2**0 CONTENTS, READONLY 20 .debug_frame 00006d24 00000000 00000000 001436f0 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000073 00000000 00000000 0014a414 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080081e8 <__do_global_dtors_aux>: 80081e8: b510 push {r4, lr} 80081ea: 4c05 ldr r4, [pc, #20] @ (8008200 <__do_global_dtors_aux+0x18>) 80081ec: 7823 ldrb r3, [r4, #0] 80081ee: b933 cbnz r3, 80081fe <__do_global_dtors_aux+0x16> 80081f0: 4b04 ldr r3, [pc, #16] @ (8008204 <__do_global_dtors_aux+0x1c>) 80081f2: b113 cbz r3, 80081fa <__do_global_dtors_aux+0x12> 80081f4: 4804 ldr r0, [pc, #16] @ (8008208 <__do_global_dtors_aux+0x20>) 80081f6: f3af 8000 nop.w 80081fa: 2301 movs r3, #1 80081fc: 7023 strb r3, [r4, #0] 80081fe: bd10 pop {r4, pc} 8008200: 20000240 .word 0x20000240 8008204: 00000000 .word 0x00000000 8008208: 08015cb8 .word 0x08015cb8 0800820c : 800820c: b508 push {r3, lr} 800820e: 4b03 ldr r3, [pc, #12] @ (800821c ) 8008210: b11b cbz r3, 800821a 8008212: 4903 ldr r1, [pc, #12] @ (8008220 ) 8008214: 4803 ldr r0, [pc, #12] @ (8008224 ) 8008216: f3af 8000 nop.w 800821a: bd08 pop {r3, pc} 800821c: 00000000 .word 0x00000000 8008220: 20000244 .word 0x20000244 8008224: 08015cb8 .word 0x08015cb8 08008228 : 8008228: 4603 mov r3, r0 800822a: f813 2b01 ldrb.w r2, [r3], #1 800822e: 2a00 cmp r2, #0 8008230: d1fb bne.n 800822a 8008232: 1a18 subs r0, r3, r0 8008234: 3801 subs r0, #1 8008236: 4770 bx lr 08008238 <__aeabi_drsub>: 8008238: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 800823c: e002 b.n 8008244 <__adddf3> 800823e: bf00 nop 08008240 <__aeabi_dsub>: 8008240: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 08008244 <__adddf3>: 8008244: b530 push {r4, r5, lr} 8008246: ea4f 0441 mov.w r4, r1, lsl #1 800824a: ea4f 0543 mov.w r5, r3, lsl #1 800824e: ea94 0f05 teq r4, r5 8008252: bf08 it eq 8008254: ea90 0f02 teqeq r0, r2 8008258: bf1f itttt ne 800825a: ea54 0c00 orrsne.w ip, r4, r0 800825e: ea55 0c02 orrsne.w ip, r5, r2 8008262: ea7f 5c64 mvnsne.w ip, r4, asr #21 8008266: ea7f 5c65 mvnsne.w ip, r5, asr #21 800826a: f000 80e2 beq.w 8008432 <__adddf3+0x1ee> 800826e: ea4f 5454 mov.w r4, r4, lsr #21 8008272: ebd4 5555 rsbs r5, r4, r5, lsr #21 8008276: bfb8 it lt 8008278: 426d neglt r5, r5 800827a: dd0c ble.n 8008296 <__adddf3+0x52> 800827c: 442c add r4, r5 800827e: ea80 0202 eor.w r2, r0, r2 8008282: ea81 0303 eor.w r3, r1, r3 8008286: ea82 0000 eor.w r0, r2, r0 800828a: ea83 0101 eor.w r1, r3, r1 800828e: ea80 0202 eor.w r2, r0, r2 8008292: ea81 0303 eor.w r3, r1, r3 8008296: 2d36 cmp r5, #54 @ 0x36 8008298: bf88 it hi 800829a: bd30 pophi {r4, r5, pc} 800829c: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 80082a0: ea4f 3101 mov.w r1, r1, lsl #12 80082a4: f44f 1c80 mov.w ip, #1048576 @ 0x100000 80082a8: ea4c 3111 orr.w r1, ip, r1, lsr #12 80082ac: d002 beq.n 80082b4 <__adddf3+0x70> 80082ae: 4240 negs r0, r0 80082b0: eb61 0141 sbc.w r1, r1, r1, lsl #1 80082b4: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 80082b8: ea4f 3303 mov.w r3, r3, lsl #12 80082bc: ea4c 3313 orr.w r3, ip, r3, lsr #12 80082c0: d002 beq.n 80082c8 <__adddf3+0x84> 80082c2: 4252 negs r2, r2 80082c4: eb63 0343 sbc.w r3, r3, r3, lsl #1 80082c8: ea94 0f05 teq r4, r5 80082cc: f000 80a7 beq.w 800841e <__adddf3+0x1da> 80082d0: f1a4 0401 sub.w r4, r4, #1 80082d4: f1d5 0e20 rsbs lr, r5, #32 80082d8: db0d blt.n 80082f6 <__adddf3+0xb2> 80082da: fa02 fc0e lsl.w ip, r2, lr 80082de: fa22 f205 lsr.w r2, r2, r5 80082e2: 1880 adds r0, r0, r2 80082e4: f141 0100 adc.w r1, r1, #0 80082e8: fa03 f20e lsl.w r2, r3, lr 80082ec: 1880 adds r0, r0, r2 80082ee: fa43 f305 asr.w r3, r3, r5 80082f2: 4159 adcs r1, r3 80082f4: e00e b.n 8008314 <__adddf3+0xd0> 80082f6: f1a5 0520 sub.w r5, r5, #32 80082fa: f10e 0e20 add.w lr, lr, #32 80082fe: 2a01 cmp r2, #1 8008300: fa03 fc0e lsl.w ip, r3, lr 8008304: bf28 it cs 8008306: f04c 0c02 orrcs.w ip, ip, #2 800830a: fa43 f305 asr.w r3, r3, r5 800830e: 18c0 adds r0, r0, r3 8008310: eb51 71e3 adcs.w r1, r1, r3, asr #31 8008314: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008318: d507 bpl.n 800832a <__adddf3+0xe6> 800831a: f04f 0e00 mov.w lr, #0 800831e: f1dc 0c00 rsbs ip, ip, #0 8008322: eb7e 0000 sbcs.w r0, lr, r0 8008326: eb6e 0101 sbc.w r1, lr, r1 800832a: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 800832e: d31b bcc.n 8008368 <__adddf3+0x124> 8008330: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 8008334: d30c bcc.n 8008350 <__adddf3+0x10c> 8008336: 0849 lsrs r1, r1, #1 8008338: ea5f 0030 movs.w r0, r0, rrx 800833c: ea4f 0c3c mov.w ip, ip, rrx 8008340: f104 0401 add.w r4, r4, #1 8008344: ea4f 5244 mov.w r2, r4, lsl #21 8008348: f512 0f80 cmn.w r2, #4194304 @ 0x400000 800834c: f080 809a bcs.w 8008484 <__adddf3+0x240> 8008350: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008354: bf08 it eq 8008356: ea5f 0c50 movseq.w ip, r0, lsr #1 800835a: f150 0000 adcs.w r0, r0, #0 800835e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008362: ea41 0105 orr.w r1, r1, r5 8008366: bd30 pop {r4, r5, pc} 8008368: ea5f 0c4c movs.w ip, ip, lsl #1 800836c: 4140 adcs r0, r0 800836e: eb41 0101 adc.w r1, r1, r1 8008372: 3c01 subs r4, #1 8008374: bf28 it cs 8008376: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 800837a: d2e9 bcs.n 8008350 <__adddf3+0x10c> 800837c: f091 0f00 teq r1, #0 8008380: bf04 itt eq 8008382: 4601 moveq r1, r0 8008384: 2000 moveq r0, #0 8008386: fab1 f381 clz r3, r1 800838a: bf08 it eq 800838c: 3320 addeq r3, #32 800838e: f1a3 030b sub.w r3, r3, #11 8008392: f1b3 0220 subs.w r2, r3, #32 8008396: da0c bge.n 80083b2 <__adddf3+0x16e> 8008398: 320c adds r2, #12 800839a: dd08 ble.n 80083ae <__adddf3+0x16a> 800839c: f102 0c14 add.w ip, r2, #20 80083a0: f1c2 020c rsb r2, r2, #12 80083a4: fa01 f00c lsl.w r0, r1, ip 80083a8: fa21 f102 lsr.w r1, r1, r2 80083ac: e00c b.n 80083c8 <__adddf3+0x184> 80083ae: f102 0214 add.w r2, r2, #20 80083b2: bfd8 it le 80083b4: f1c2 0c20 rsble ip, r2, #32 80083b8: fa01 f102 lsl.w r1, r1, r2 80083bc: fa20 fc0c lsr.w ip, r0, ip 80083c0: bfdc itt le 80083c2: ea41 010c orrle.w r1, r1, ip 80083c6: 4090 lslle r0, r2 80083c8: 1ae4 subs r4, r4, r3 80083ca: bfa2 ittt ge 80083cc: eb01 5104 addge.w r1, r1, r4, lsl #20 80083d0: 4329 orrge r1, r5 80083d2: bd30 popge {r4, r5, pc} 80083d4: ea6f 0404 mvn.w r4, r4 80083d8: 3c1f subs r4, #31 80083da: da1c bge.n 8008416 <__adddf3+0x1d2> 80083dc: 340c adds r4, #12 80083de: dc0e bgt.n 80083fe <__adddf3+0x1ba> 80083e0: f104 0414 add.w r4, r4, #20 80083e4: f1c4 0220 rsb r2, r4, #32 80083e8: fa20 f004 lsr.w r0, r0, r4 80083ec: fa01 f302 lsl.w r3, r1, r2 80083f0: ea40 0003 orr.w r0, r0, r3 80083f4: fa21 f304 lsr.w r3, r1, r4 80083f8: ea45 0103 orr.w r1, r5, r3 80083fc: bd30 pop {r4, r5, pc} 80083fe: f1c4 040c rsb r4, r4, #12 8008402: f1c4 0220 rsb r2, r4, #32 8008406: fa20 f002 lsr.w r0, r0, r2 800840a: fa01 f304 lsl.w r3, r1, r4 800840e: ea40 0003 orr.w r0, r0, r3 8008412: 4629 mov r1, r5 8008414: bd30 pop {r4, r5, pc} 8008416: fa21 f004 lsr.w r0, r1, r4 800841a: 4629 mov r1, r5 800841c: bd30 pop {r4, r5, pc} 800841e: f094 0f00 teq r4, #0 8008422: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 8008426: bf06 itte eq 8008428: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 800842c: 3401 addeq r4, #1 800842e: 3d01 subne r5, #1 8008430: e74e b.n 80082d0 <__adddf3+0x8c> 8008432: ea7f 5c64 mvns.w ip, r4, asr #21 8008436: bf18 it ne 8008438: ea7f 5c65 mvnsne.w ip, r5, asr #21 800843c: d029 beq.n 8008492 <__adddf3+0x24e> 800843e: ea94 0f05 teq r4, r5 8008442: bf08 it eq 8008444: ea90 0f02 teqeq r0, r2 8008448: d005 beq.n 8008456 <__adddf3+0x212> 800844a: ea54 0c00 orrs.w ip, r4, r0 800844e: bf04 itt eq 8008450: 4619 moveq r1, r3 8008452: 4610 moveq r0, r2 8008454: bd30 pop {r4, r5, pc} 8008456: ea91 0f03 teq r1, r3 800845a: bf1e ittt ne 800845c: 2100 movne r1, #0 800845e: 2000 movne r0, #0 8008460: bd30 popne {r4, r5, pc} 8008462: ea5f 5c54 movs.w ip, r4, lsr #21 8008466: d105 bne.n 8008474 <__adddf3+0x230> 8008468: 0040 lsls r0, r0, #1 800846a: 4149 adcs r1, r1 800846c: bf28 it cs 800846e: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 8008472: bd30 pop {r4, r5, pc} 8008474: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 8008478: bf3c itt cc 800847a: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 800847e: bd30 popcc {r4, r5, pc} 8008480: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008484: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 8008488: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 800848c: f04f 0000 mov.w r0, #0 8008490: bd30 pop {r4, r5, pc} 8008492: ea7f 5c64 mvns.w ip, r4, asr #21 8008496: bf1a itte ne 8008498: 4619 movne r1, r3 800849a: 4610 movne r0, r2 800849c: ea7f 5c65 mvnseq.w ip, r5, asr #21 80084a0: bf1c itt ne 80084a2: 460b movne r3, r1 80084a4: 4602 movne r2, r0 80084a6: ea50 3401 orrs.w r4, r0, r1, lsl #12 80084aa: bf06 itte eq 80084ac: ea52 3503 orrseq.w r5, r2, r3, lsl #12 80084b0: ea91 0f03 teqeq r1, r3 80084b4: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 80084b8: bd30 pop {r4, r5, pc} 80084ba: bf00 nop 080084bc <__aeabi_ui2d>: 80084bc: f090 0f00 teq r0, #0 80084c0: bf04 itt eq 80084c2: 2100 moveq r1, #0 80084c4: 4770 bxeq lr 80084c6: b530 push {r4, r5, lr} 80084c8: f44f 6480 mov.w r4, #1024 @ 0x400 80084cc: f104 0432 add.w r4, r4, #50 @ 0x32 80084d0: f04f 0500 mov.w r5, #0 80084d4: f04f 0100 mov.w r1, #0 80084d8: e750 b.n 800837c <__adddf3+0x138> 80084da: bf00 nop 080084dc <__aeabi_i2d>: 80084dc: f090 0f00 teq r0, #0 80084e0: bf04 itt eq 80084e2: 2100 moveq r1, #0 80084e4: 4770 bxeq lr 80084e6: b530 push {r4, r5, lr} 80084e8: f44f 6480 mov.w r4, #1024 @ 0x400 80084ec: f104 0432 add.w r4, r4, #50 @ 0x32 80084f0: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 80084f4: bf48 it mi 80084f6: 4240 negmi r0, r0 80084f8: f04f 0100 mov.w r1, #0 80084fc: e73e b.n 800837c <__adddf3+0x138> 80084fe: bf00 nop 08008500 <__aeabi_f2d>: 8008500: 0042 lsls r2, r0, #1 8008502: ea4f 01e2 mov.w r1, r2, asr #3 8008506: ea4f 0131 mov.w r1, r1, rrx 800850a: ea4f 7002 mov.w r0, r2, lsl #28 800850e: bf1f itttt ne 8008510: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 8008514: f093 4f7f teqne r3, #4278190080 @ 0xff000000 8008518: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 800851c: 4770 bxne lr 800851e: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 8008522: bf08 it eq 8008524: 4770 bxeq lr 8008526: f093 4f7f teq r3, #4278190080 @ 0xff000000 800852a: bf04 itt eq 800852c: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 8008530: 4770 bxeq lr 8008532: b530 push {r4, r5, lr} 8008534: f44f 7460 mov.w r4, #896 @ 0x380 8008538: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 800853c: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 8008540: e71c b.n 800837c <__adddf3+0x138> 8008542: bf00 nop 08008544 <__aeabi_ul2d>: 8008544: ea50 0201 orrs.w r2, r0, r1 8008548: bf08 it eq 800854a: 4770 bxeq lr 800854c: b530 push {r4, r5, lr} 800854e: f04f 0500 mov.w r5, #0 8008552: e00a b.n 800856a <__aeabi_l2d+0x16> 08008554 <__aeabi_l2d>: 8008554: ea50 0201 orrs.w r2, r0, r1 8008558: bf08 it eq 800855a: 4770 bxeq lr 800855c: b530 push {r4, r5, lr} 800855e: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 8008562: d502 bpl.n 800856a <__aeabi_l2d+0x16> 8008564: 4240 negs r0, r0 8008566: eb61 0141 sbc.w r1, r1, r1, lsl #1 800856a: f44f 6480 mov.w r4, #1024 @ 0x400 800856e: f104 0432 add.w r4, r4, #50 @ 0x32 8008572: ea5f 5c91 movs.w ip, r1, lsr #22 8008576: f43f aed8 beq.w 800832a <__adddf3+0xe6> 800857a: f04f 0203 mov.w r2, #3 800857e: ea5f 0cdc movs.w ip, ip, lsr #3 8008582: bf18 it ne 8008584: 3203 addne r2, #3 8008586: ea5f 0cdc movs.w ip, ip, lsr #3 800858a: bf18 it ne 800858c: 3203 addne r2, #3 800858e: eb02 02dc add.w r2, r2, ip, lsr #3 8008592: f1c2 0320 rsb r3, r2, #32 8008596: fa00 fc03 lsl.w ip, r0, r3 800859a: fa20 f002 lsr.w r0, r0, r2 800859e: fa01 fe03 lsl.w lr, r1, r3 80085a2: ea40 000e orr.w r0, r0, lr 80085a6: fa21 f102 lsr.w r1, r1, r2 80085aa: 4414 add r4, r2 80085ac: e6bd b.n 800832a <__adddf3+0xe6> 80085ae: bf00 nop 080085b0 <__aeabi_dmul>: 80085b0: b570 push {r4, r5, r6, lr} 80085b2: f04f 0cff mov.w ip, #255 @ 0xff 80085b6: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 80085ba: ea1c 5411 ands.w r4, ip, r1, lsr #20 80085be: bf1d ittte ne 80085c0: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80085c4: ea94 0f0c teqne r4, ip 80085c8: ea95 0f0c teqne r5, ip 80085cc: f000 f8de bleq 800878c <__aeabi_dmul+0x1dc> 80085d0: 442c add r4, r5 80085d2: ea81 0603 eor.w r6, r1, r3 80085d6: ea21 514c bic.w r1, r1, ip, lsl #21 80085da: ea23 534c bic.w r3, r3, ip, lsl #21 80085de: ea50 3501 orrs.w r5, r0, r1, lsl #12 80085e2: bf18 it ne 80085e4: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80085e8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 80085ec: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80085f0: d038 beq.n 8008664 <__aeabi_dmul+0xb4> 80085f2: fba0 ce02 umull ip, lr, r0, r2 80085f6: f04f 0500 mov.w r5, #0 80085fa: fbe1 e502 umlal lr, r5, r1, r2 80085fe: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 8008602: fbe0 e503 umlal lr, r5, r0, r3 8008606: f04f 0600 mov.w r6, #0 800860a: fbe1 5603 umlal r5, r6, r1, r3 800860e: f09c 0f00 teq ip, #0 8008612: bf18 it ne 8008614: f04e 0e01 orrne.w lr, lr, #1 8008618: f1a4 04ff sub.w r4, r4, #255 @ 0xff 800861c: f5b6 7f00 cmp.w r6, #512 @ 0x200 8008620: f564 7440 sbc.w r4, r4, #768 @ 0x300 8008624: d204 bcs.n 8008630 <__aeabi_dmul+0x80> 8008626: ea5f 0e4e movs.w lr, lr, lsl #1 800862a: 416d adcs r5, r5 800862c: eb46 0606 adc.w r6, r6, r6 8008630: ea42 21c6 orr.w r1, r2, r6, lsl #11 8008634: ea41 5155 orr.w r1, r1, r5, lsr #21 8008638: ea4f 20c5 mov.w r0, r5, lsl #11 800863c: ea40 505e orr.w r0, r0, lr, lsr #21 8008640: ea4f 2ece mov.w lr, lr, lsl #11 8008644: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008648: bf88 it hi 800864a: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800864e: d81e bhi.n 800868e <__aeabi_dmul+0xde> 8008650: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 8008654: bf08 it eq 8008656: ea5f 0e50 movseq.w lr, r0, lsr #1 800865a: f150 0000 adcs.w r0, r0, #0 800865e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008662: bd70 pop {r4, r5, r6, pc} 8008664: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 8008668: ea46 0101 orr.w r1, r6, r1 800866c: ea40 0002 orr.w r0, r0, r2 8008670: ea81 0103 eor.w r1, r1, r3 8008674: ebb4 045c subs.w r4, r4, ip, lsr #1 8008678: bfc2 ittt gt 800867a: ebd4 050c rsbsgt r5, r4, ip 800867e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8008682: bd70 popgt {r4, r5, r6, pc} 8008684: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008688: f04f 0e00 mov.w lr, #0 800868c: 3c01 subs r4, #1 800868e: f300 80ab bgt.w 80087e8 <__aeabi_dmul+0x238> 8008692: f114 0f36 cmn.w r4, #54 @ 0x36 8008696: bfde ittt le 8008698: 2000 movle r0, #0 800869a: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 800869e: bd70 pople {r4, r5, r6, pc} 80086a0: f1c4 0400 rsb r4, r4, #0 80086a4: 3c20 subs r4, #32 80086a6: da35 bge.n 8008714 <__aeabi_dmul+0x164> 80086a8: 340c adds r4, #12 80086aa: dc1b bgt.n 80086e4 <__aeabi_dmul+0x134> 80086ac: f104 0414 add.w r4, r4, #20 80086b0: f1c4 0520 rsb r5, r4, #32 80086b4: fa00 f305 lsl.w r3, r0, r5 80086b8: fa20 f004 lsr.w r0, r0, r4 80086bc: fa01 f205 lsl.w r2, r1, r5 80086c0: ea40 0002 orr.w r0, r0, r2 80086c4: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 80086c8: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 80086cc: eb10 70d3 adds.w r0, r0, r3, lsr #31 80086d0: fa21 f604 lsr.w r6, r1, r4 80086d4: eb42 0106 adc.w r1, r2, r6 80086d8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80086dc: bf08 it eq 80086de: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80086e2: bd70 pop {r4, r5, r6, pc} 80086e4: f1c4 040c rsb r4, r4, #12 80086e8: f1c4 0520 rsb r5, r4, #32 80086ec: fa00 f304 lsl.w r3, r0, r4 80086f0: fa20 f005 lsr.w r0, r0, r5 80086f4: fa01 f204 lsl.w r2, r1, r4 80086f8: ea40 0002 orr.w r0, r0, r2 80086fc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008700: eb10 70d3 adds.w r0, r0, r3, lsr #31 8008704: f141 0100 adc.w r1, r1, #0 8008708: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800870c: bf08 it eq 800870e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8008712: bd70 pop {r4, r5, r6, pc} 8008714: f1c4 0520 rsb r5, r4, #32 8008718: fa00 f205 lsl.w r2, r0, r5 800871c: ea4e 0e02 orr.w lr, lr, r2 8008720: fa20 f304 lsr.w r3, r0, r4 8008724: fa01 f205 lsl.w r2, r1, r5 8008728: ea43 0302 orr.w r3, r3, r2 800872c: fa21 f004 lsr.w r0, r1, r4 8008730: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008734: fa21 f204 lsr.w r2, r1, r4 8008738: ea20 0002 bic.w r0, r0, r2 800873c: eb00 70d3 add.w r0, r0, r3, lsr #31 8008740: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8008744: bf08 it eq 8008746: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800874a: bd70 pop {r4, r5, r6, pc} 800874c: f094 0f00 teq r4, #0 8008750: d10f bne.n 8008772 <__aeabi_dmul+0x1c2> 8008752: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 8008756: 0040 lsls r0, r0, #1 8008758: eb41 0101 adc.w r1, r1, r1 800875c: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008760: bf08 it eq 8008762: 3c01 subeq r4, #1 8008764: d0f7 beq.n 8008756 <__aeabi_dmul+0x1a6> 8008766: ea41 0106 orr.w r1, r1, r6 800876a: f095 0f00 teq r5, #0 800876e: bf18 it ne 8008770: 4770 bxne lr 8008772: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 8008776: 0052 lsls r2, r2, #1 8008778: eb43 0303 adc.w r3, r3, r3 800877c: f413 1f80 tst.w r3, #1048576 @ 0x100000 8008780: bf08 it eq 8008782: 3d01 subeq r5, #1 8008784: d0f7 beq.n 8008776 <__aeabi_dmul+0x1c6> 8008786: ea43 0306 orr.w r3, r3, r6 800878a: 4770 bx lr 800878c: ea94 0f0c teq r4, ip 8008790: ea0c 5513 and.w r5, ip, r3, lsr #20 8008794: bf18 it ne 8008796: ea95 0f0c teqne r5, ip 800879a: d00c beq.n 80087b6 <__aeabi_dmul+0x206> 800879c: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087a0: bf18 it ne 80087a2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087a6: d1d1 bne.n 800874c <__aeabi_dmul+0x19c> 80087a8: ea81 0103 eor.w r1, r1, r3 80087ac: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087b0: f04f 0000 mov.w r0, #0 80087b4: bd70 pop {r4, r5, r6, pc} 80087b6: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087ba: bf06 itte eq 80087bc: 4610 moveq r0, r2 80087be: 4619 moveq r1, r3 80087c0: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087c4: d019 beq.n 80087fa <__aeabi_dmul+0x24a> 80087c6: ea94 0f0c teq r4, ip 80087ca: d102 bne.n 80087d2 <__aeabi_dmul+0x222> 80087cc: ea50 3601 orrs.w r6, r0, r1, lsl #12 80087d0: d113 bne.n 80087fa <__aeabi_dmul+0x24a> 80087d2: ea95 0f0c teq r5, ip 80087d6: d105 bne.n 80087e4 <__aeabi_dmul+0x234> 80087d8: ea52 3603 orrs.w r6, r2, r3, lsl #12 80087dc: bf1c itt ne 80087de: 4610 movne r0, r2 80087e0: 4619 movne r1, r3 80087e2: d10a bne.n 80087fa <__aeabi_dmul+0x24a> 80087e4: ea81 0103 eor.w r1, r1, r3 80087e8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087ec: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087f0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 80087f4: f04f 0000 mov.w r0, #0 80087f8: bd70 pop {r4, r5, r6, pc} 80087fa: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087fe: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 8008802: bd70 pop {r4, r5, r6, pc} 08008804 <__aeabi_ddiv>: 8008804: b570 push {r4, r5, r6, lr} 8008806: f04f 0cff mov.w ip, #255 @ 0xff 800880a: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 800880e: ea1c 5411 ands.w r4, ip, r1, lsr #20 8008812: bf1d ittte ne 8008814: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8008818: ea94 0f0c teqne r4, ip 800881c: ea95 0f0c teqne r5, ip 8008820: f000 f8a7 bleq 8008972 <__aeabi_ddiv+0x16e> 8008824: eba4 0405 sub.w r4, r4, r5 8008828: ea81 0e03 eor.w lr, r1, r3 800882c: ea52 3503 orrs.w r5, r2, r3, lsl #12 8008830: ea4f 3101 mov.w r1, r1, lsl #12 8008834: f000 8088 beq.w 8008948 <__aeabi_ddiv+0x144> 8008838: ea4f 3303 mov.w r3, r3, lsl #12 800883c: f04f 5580 mov.w r5, #268435456 @ 0x10000000 8008840: ea45 1313 orr.w r3, r5, r3, lsr #4 8008844: ea43 6312 orr.w r3, r3, r2, lsr #24 8008848: ea4f 2202 mov.w r2, r2, lsl #8 800884c: ea45 1511 orr.w r5, r5, r1, lsr #4 8008850: ea45 6510 orr.w r5, r5, r0, lsr #24 8008854: ea4f 2600 mov.w r6, r0, lsl #8 8008858: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000 800885c: 429d cmp r5, r3 800885e: bf08 it eq 8008860: 4296 cmpeq r6, r2 8008862: f144 04fd adc.w r4, r4, #253 @ 0xfd 8008866: f504 7440 add.w r4, r4, #768 @ 0x300 800886a: d202 bcs.n 8008872 <__aeabi_ddiv+0x6e> 800886c: 085b lsrs r3, r3, #1 800886e: ea4f 0232 mov.w r2, r2, rrx 8008872: 1ab6 subs r6, r6, r2 8008874: eb65 0503 sbc.w r5, r5, r3 8008878: 085b lsrs r3, r3, #1 800887a: ea4f 0232 mov.w r2, r2, rrx 800887e: f44f 1080 mov.w r0, #1048576 @ 0x100000 8008882: f44f 2c00 mov.w ip, #524288 @ 0x80000 8008886: ebb6 0e02 subs.w lr, r6, r2 800888a: eb75 0e03 sbcs.w lr, r5, r3 800888e: bf22 ittt cs 8008890: 1ab6 subcs r6, r6, r2 8008892: 4675 movcs r5, lr 8008894: ea40 000c orrcs.w r0, r0, ip 8008898: 085b lsrs r3, r3, #1 800889a: ea4f 0232 mov.w r2, r2, rrx 800889e: ebb6 0e02 subs.w lr, r6, r2 80088a2: eb75 0e03 sbcs.w lr, r5, r3 80088a6: bf22 ittt cs 80088a8: 1ab6 subcs r6, r6, r2 80088aa: 4675 movcs r5, lr 80088ac: ea40 005c orrcs.w r0, r0, ip, lsr #1 80088b0: 085b lsrs r3, r3, #1 80088b2: ea4f 0232 mov.w r2, r2, rrx 80088b6: ebb6 0e02 subs.w lr, r6, r2 80088ba: eb75 0e03 sbcs.w lr, r5, r3 80088be: bf22 ittt cs 80088c0: 1ab6 subcs r6, r6, r2 80088c2: 4675 movcs r5, lr 80088c4: ea40 009c orrcs.w r0, r0, ip, lsr #2 80088c8: 085b lsrs r3, r3, #1 80088ca: ea4f 0232 mov.w r2, r2, rrx 80088ce: ebb6 0e02 subs.w lr, r6, r2 80088d2: eb75 0e03 sbcs.w lr, r5, r3 80088d6: bf22 ittt cs 80088d8: 1ab6 subcs r6, r6, r2 80088da: 4675 movcs r5, lr 80088dc: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80088e0: ea55 0e06 orrs.w lr, r5, r6 80088e4: d018 beq.n 8008918 <__aeabi_ddiv+0x114> 80088e6: ea4f 1505 mov.w r5, r5, lsl #4 80088ea: ea45 7516 orr.w r5, r5, r6, lsr #28 80088ee: ea4f 1606 mov.w r6, r6, lsl #4 80088f2: ea4f 03c3 mov.w r3, r3, lsl #3 80088f6: ea43 7352 orr.w r3, r3, r2, lsr #29 80088fa: ea4f 02c2 mov.w r2, r2, lsl #3 80088fe: ea5f 1c1c movs.w ip, ip, lsr #4 8008902: d1c0 bne.n 8008886 <__aeabi_ddiv+0x82> 8008904: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008908: d10b bne.n 8008922 <__aeabi_ddiv+0x11e> 800890a: ea41 0100 orr.w r1, r1, r0 800890e: f04f 0000 mov.w r0, #0 8008912: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000 8008916: e7b6 b.n 8008886 <__aeabi_ddiv+0x82> 8008918: f411 1f80 tst.w r1, #1048576 @ 0x100000 800891c: bf04 itt eq 800891e: 4301 orreq r1, r0 8008920: 2000 moveq r0, #0 8008922: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008926: bf88 it hi 8008928: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800892c: f63f aeaf bhi.w 800868e <__aeabi_dmul+0xde> 8008930: ebb5 0c03 subs.w ip, r5, r3 8008934: bf04 itt eq 8008936: ebb6 0c02 subseq.w ip, r6, r2 800893a: ea5f 0c50 movseq.w ip, r0, lsr #1 800893e: f150 0000 adcs.w r0, r0, #0 8008942: eb41 5104 adc.w r1, r1, r4, lsl #20 8008946: bd70 pop {r4, r5, r6, pc} 8008948: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000 800894c: ea4e 3111 orr.w r1, lr, r1, lsr #12 8008950: eb14 045c adds.w r4, r4, ip, lsr #1 8008954: bfc2 ittt gt 8008956: ebd4 050c rsbsgt r5, r4, ip 800895a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800895e: bd70 popgt {r4, r5, r6, pc} 8008960: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008964: f04f 0e00 mov.w lr, #0 8008968: 3c01 subs r4, #1 800896a: e690 b.n 800868e <__aeabi_dmul+0xde> 800896c: ea45 0e06 orr.w lr, r5, r6 8008970: e68d b.n 800868e <__aeabi_dmul+0xde> 8008972: ea0c 5513 and.w r5, ip, r3, lsr #20 8008976: ea94 0f0c teq r4, ip 800897a: bf08 it eq 800897c: ea95 0f0c teqeq r5, ip 8008980: f43f af3b beq.w 80087fa <__aeabi_dmul+0x24a> 8008984: ea94 0f0c teq r4, ip 8008988: d10a bne.n 80089a0 <__aeabi_ddiv+0x19c> 800898a: ea50 3401 orrs.w r4, r0, r1, lsl #12 800898e: f47f af34 bne.w 80087fa <__aeabi_dmul+0x24a> 8008992: ea95 0f0c teq r5, ip 8008996: f47f af25 bne.w 80087e4 <__aeabi_dmul+0x234> 800899a: 4610 mov r0, r2 800899c: 4619 mov r1, r3 800899e: e72c b.n 80087fa <__aeabi_dmul+0x24a> 80089a0: ea95 0f0c teq r5, ip 80089a4: d106 bne.n 80089b4 <__aeabi_ddiv+0x1b0> 80089a6: ea52 3503 orrs.w r5, r2, r3, lsl #12 80089aa: f43f aefd beq.w 80087a8 <__aeabi_dmul+0x1f8> 80089ae: 4610 mov r0, r2 80089b0: 4619 mov r1, r3 80089b2: e722 b.n 80087fa <__aeabi_dmul+0x24a> 80089b4: ea50 0641 orrs.w r6, r0, r1, lsl #1 80089b8: bf18 it ne 80089ba: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80089be: f47f aec5 bne.w 800874c <__aeabi_dmul+0x19c> 80089c2: ea50 0441 orrs.w r4, r0, r1, lsl #1 80089c6: f47f af0d bne.w 80087e4 <__aeabi_dmul+0x234> 80089ca: ea52 0543 orrs.w r5, r2, r3, lsl #1 80089ce: f47f aeeb bne.w 80087a8 <__aeabi_dmul+0x1f8> 80089d2: e712 b.n 80087fa <__aeabi_dmul+0x24a> 080089d4 <__gedf2>: 80089d4: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80089d8: e006 b.n 80089e8 <__cmpdf2+0x4> 80089da: bf00 nop 080089dc <__ledf2>: 80089dc: f04f 0c01 mov.w ip, #1 80089e0: e002 b.n 80089e8 <__cmpdf2+0x4> 80089e2: bf00 nop 080089e4 <__cmpdf2>: 80089e4: f04f 0c01 mov.w ip, #1 80089e8: f84d cd04 str.w ip, [sp, #-4]! 80089ec: ea4f 0c41 mov.w ip, r1, lsl #1 80089f0: ea7f 5c6c mvns.w ip, ip, asr #21 80089f4: ea4f 0c43 mov.w ip, r3, lsl #1 80089f8: bf18 it ne 80089fa: ea7f 5c6c mvnsne.w ip, ip, asr #21 80089fe: d01b beq.n 8008a38 <__cmpdf2+0x54> 8008a00: b001 add sp, #4 8008a02: ea50 0c41 orrs.w ip, r0, r1, lsl #1 8008a06: bf0c ite eq 8008a08: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 8008a0c: ea91 0f03 teqne r1, r3 8008a10: bf02 ittt eq 8008a12: ea90 0f02 teqeq r0, r2 8008a16: 2000 moveq r0, #0 8008a18: 4770 bxeq lr 8008a1a: f110 0f00 cmn.w r0, #0 8008a1e: ea91 0f03 teq r1, r3 8008a22: bf58 it pl 8008a24: 4299 cmppl r1, r3 8008a26: bf08 it eq 8008a28: 4290 cmpeq r0, r2 8008a2a: bf2c ite cs 8008a2c: 17d8 asrcs r0, r3, #31 8008a2e: ea6f 70e3 mvncc.w r0, r3, asr #31 8008a32: f040 0001 orr.w r0, r0, #1 8008a36: 4770 bx lr 8008a38: ea4f 0c41 mov.w ip, r1, lsl #1 8008a3c: ea7f 5c6c mvns.w ip, ip, asr #21 8008a40: d102 bne.n 8008a48 <__cmpdf2+0x64> 8008a42: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8008a46: d107 bne.n 8008a58 <__cmpdf2+0x74> 8008a48: ea4f 0c43 mov.w ip, r3, lsl #1 8008a4c: ea7f 5c6c mvns.w ip, ip, asr #21 8008a50: d1d6 bne.n 8008a00 <__cmpdf2+0x1c> 8008a52: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8008a56: d0d3 beq.n 8008a00 <__cmpdf2+0x1c> 8008a58: f85d 0b04 ldr.w r0, [sp], #4 8008a5c: 4770 bx lr 8008a5e: bf00 nop 08008a60 <__aeabi_cdrcmple>: 8008a60: 4684 mov ip, r0 8008a62: 4610 mov r0, r2 8008a64: 4662 mov r2, ip 8008a66: 468c mov ip, r1 8008a68: 4619 mov r1, r3 8008a6a: 4663 mov r3, ip 8008a6c: e000 b.n 8008a70 <__aeabi_cdcmpeq> 8008a6e: bf00 nop 08008a70 <__aeabi_cdcmpeq>: 8008a70: b501 push {r0, lr} 8008a72: f7ff ffb7 bl 80089e4 <__cmpdf2> 8008a76: 2800 cmp r0, #0 8008a78: bf48 it mi 8008a7a: f110 0f00 cmnmi.w r0, #0 8008a7e: bd01 pop {r0, pc} 08008a80 <__aeabi_dcmpeq>: 8008a80: f84d ed08 str.w lr, [sp, #-8]! 8008a84: f7ff fff4 bl 8008a70 <__aeabi_cdcmpeq> 8008a88: bf0c ite eq 8008a8a: 2001 moveq r0, #1 8008a8c: 2000 movne r0, #0 8008a8e: f85d fb08 ldr.w pc, [sp], #8 8008a92: bf00 nop 08008a94 <__aeabi_dcmplt>: 8008a94: f84d ed08 str.w lr, [sp, #-8]! 8008a98: f7ff ffea bl 8008a70 <__aeabi_cdcmpeq> 8008a9c: bf34 ite cc 8008a9e: 2001 movcc r0, #1 8008aa0: 2000 movcs r0, #0 8008aa2: f85d fb08 ldr.w pc, [sp], #8 8008aa6: bf00 nop 08008aa8 <__aeabi_dcmple>: 8008aa8: f84d ed08 str.w lr, [sp, #-8]! 8008aac: f7ff ffe0 bl 8008a70 <__aeabi_cdcmpeq> 8008ab0: bf94 ite ls 8008ab2: 2001 movls r0, #1 8008ab4: 2000 movhi r0, #0 8008ab6: f85d fb08 ldr.w pc, [sp], #8 8008aba: bf00 nop 08008abc <__aeabi_dcmpge>: 8008abc: f84d ed08 str.w lr, [sp, #-8]! 8008ac0: f7ff ffce bl 8008a60 <__aeabi_cdrcmple> 8008ac4: bf94 ite ls 8008ac6: 2001 movls r0, #1 8008ac8: 2000 movhi r0, #0 8008aca: f85d fb08 ldr.w pc, [sp], #8 8008ace: bf00 nop 08008ad0 <__aeabi_dcmpgt>: 8008ad0: f84d ed08 str.w lr, [sp, #-8]! 8008ad4: f7ff ffc4 bl 8008a60 <__aeabi_cdrcmple> 8008ad8: bf34 ite cc 8008ada: 2001 movcc r0, #1 8008adc: 2000 movcs r0, #0 8008ade: f85d fb08 ldr.w pc, [sp], #8 8008ae2: bf00 nop 08008ae4 <__aeabi_dcmpun>: 8008ae4: ea4f 0c41 mov.w ip, r1, lsl #1 8008ae8: ea7f 5c6c mvns.w ip, ip, asr #21 8008aec: d102 bne.n 8008af4 <__aeabi_dcmpun+0x10> 8008aee: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8008af2: d10a bne.n 8008b0a <__aeabi_dcmpun+0x26> 8008af4: ea4f 0c43 mov.w ip, r3, lsl #1 8008af8: ea7f 5c6c mvns.w ip, ip, asr #21 8008afc: d102 bne.n 8008b04 <__aeabi_dcmpun+0x20> 8008afe: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8008b02: d102 bne.n 8008b0a <__aeabi_dcmpun+0x26> 8008b04: f04f 0000 mov.w r0, #0 8008b08: 4770 bx lr 8008b0a: f04f 0001 mov.w r0, #1 8008b0e: 4770 bx lr 08008b10 <__aeabi_d2iz>: 8008b10: ea4f 0241 mov.w r2, r1, lsl #1 8008b14: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 8008b18: d215 bcs.n 8008b46 <__aeabi_d2iz+0x36> 8008b1a: d511 bpl.n 8008b40 <__aeabi_d2iz+0x30> 8008b1c: f46f 7378 mvn.w r3, #992 @ 0x3e0 8008b20: ebb3 5262 subs.w r2, r3, r2, asr #21 8008b24: d912 bls.n 8008b4c <__aeabi_d2iz+0x3c> 8008b26: ea4f 23c1 mov.w r3, r1, lsl #11 8008b2a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8008b2e: ea43 5350 orr.w r3, r3, r0, lsr #21 8008b32: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008b36: fa23 f002 lsr.w r0, r3, r2 8008b3a: bf18 it ne 8008b3c: 4240 negne r0, r0 8008b3e: 4770 bx lr 8008b40: f04f 0000 mov.w r0, #0 8008b44: 4770 bx lr 8008b46: ea50 3001 orrs.w r0, r0, r1, lsl #12 8008b4a: d105 bne.n 8008b58 <__aeabi_d2iz+0x48> 8008b4c: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000 8008b50: bf08 it eq 8008b52: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 8008b56: 4770 bx lr 8008b58: f04f 0000 mov.w r0, #0 8008b5c: 4770 bx lr 8008b5e: bf00 nop 08008b60 <__aeabi_d2f>: 8008b60: ea4f 0241 mov.w r2, r1, lsl #1 8008b64: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000 8008b68: bf24 itt cs 8008b6a: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000 8008b6e: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000 8008b72: d90d bls.n 8008b90 <__aeabi_d2f+0x30> 8008b74: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008b78: ea4f 02c0 mov.w r2, r0, lsl #3 8008b7c: ea4c 7050 orr.w r0, ip, r0, lsr #29 8008b80: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000 8008b84: eb40 0083 adc.w r0, r0, r3, lsl #2 8008b88: bf08 it eq 8008b8a: f020 0001 biceq.w r0, r0, #1 8008b8e: 4770 bx lr 8008b90: f011 4f80 tst.w r1, #1073741824 @ 0x40000000 8008b94: d121 bne.n 8008bda <__aeabi_d2f+0x7a> 8008b96: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000 8008b9a: bfbc itt lt 8008b9c: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000 8008ba0: 4770 bxlt lr 8008ba2: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008ba6: ea4f 5252 mov.w r2, r2, lsr #21 8008baa: f1c2 0218 rsb r2, r2, #24 8008bae: f1c2 0c20 rsb ip, r2, #32 8008bb2: fa10 f30c lsls.w r3, r0, ip 8008bb6: fa20 f002 lsr.w r0, r0, r2 8008bba: bf18 it ne 8008bbc: f040 0001 orrne.w r0, r0, #1 8008bc0: ea4f 23c1 mov.w r3, r1, lsl #11 8008bc4: ea4f 23d3 mov.w r3, r3, lsr #11 8008bc8: fa03 fc0c lsl.w ip, r3, ip 8008bcc: ea40 000c orr.w r0, r0, ip 8008bd0: fa23 f302 lsr.w r3, r3, r2 8008bd4: ea4f 0343 mov.w r3, r3, lsl #1 8008bd8: e7cc b.n 8008b74 <__aeabi_d2f+0x14> 8008bda: ea7f 5362 mvns.w r3, r2, asr #21 8008bde: d107 bne.n 8008bf0 <__aeabi_d2f+0x90> 8008be0: ea50 3301 orrs.w r3, r0, r1, lsl #12 8008be4: bf1e ittt ne 8008be6: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000 8008bea: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000 8008bee: 4770 bxne lr 8008bf0: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000 8008bf4: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008bf8: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008bfc: 4770 bx lr 8008bfe: bf00 nop 08008c00 <__aeabi_frsub>: 8008c00: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000 8008c04: e002 b.n 8008c0c <__addsf3> 8008c06: bf00 nop 08008c08 <__aeabi_fsub>: 8008c08: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 08008c0c <__addsf3>: 8008c0c: 0042 lsls r2, r0, #1 8008c0e: bf1f itttt ne 8008c10: ea5f 0341 movsne.w r3, r1, lsl #1 8008c14: ea92 0f03 teqne r2, r3 8008c18: ea7f 6c22 mvnsne.w ip, r2, asr #24 8008c1c: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008c20: d06a beq.n 8008cf8 <__addsf3+0xec> 8008c22: ea4f 6212 mov.w r2, r2, lsr #24 8008c26: ebd2 6313 rsbs r3, r2, r3, lsr #24 8008c2a: bfc1 itttt gt 8008c2c: 18d2 addgt r2, r2, r3 8008c2e: 4041 eorgt r1, r0 8008c30: 4048 eorgt r0, r1 8008c32: 4041 eorgt r1, r0 8008c34: bfb8 it lt 8008c36: 425b neglt r3, r3 8008c38: 2b19 cmp r3, #25 8008c3a: bf88 it hi 8008c3c: 4770 bxhi lr 8008c3e: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 8008c42: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008c46: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000 8008c4a: bf18 it ne 8008c4c: 4240 negne r0, r0 8008c4e: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008c52: f441 0100 orr.w r1, r1, #8388608 @ 0x800000 8008c56: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000 8008c5a: bf18 it ne 8008c5c: 4249 negne r1, r1 8008c5e: ea92 0f03 teq r2, r3 8008c62: d03f beq.n 8008ce4 <__addsf3+0xd8> 8008c64: f1a2 0201 sub.w r2, r2, #1 8008c68: fa41 fc03 asr.w ip, r1, r3 8008c6c: eb10 000c adds.w r0, r0, ip 8008c70: f1c3 0320 rsb r3, r3, #32 8008c74: fa01 f103 lsl.w r1, r1, r3 8008c78: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008c7c: d502 bpl.n 8008c84 <__addsf3+0x78> 8008c7e: 4249 negs r1, r1 8008c80: eb60 0040 sbc.w r0, r0, r0, lsl #1 8008c84: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000 8008c88: d313 bcc.n 8008cb2 <__addsf3+0xa6> 8008c8a: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000 8008c8e: d306 bcc.n 8008c9e <__addsf3+0x92> 8008c90: 0840 lsrs r0, r0, #1 8008c92: ea4f 0131 mov.w r1, r1, rrx 8008c96: f102 0201 add.w r2, r2, #1 8008c9a: 2afe cmp r2, #254 @ 0xfe 8008c9c: d251 bcs.n 8008d42 <__addsf3+0x136> 8008c9e: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000 8008ca2: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008ca6: bf08 it eq 8008ca8: f020 0001 biceq.w r0, r0, #1 8008cac: ea40 0003 orr.w r0, r0, r3 8008cb0: 4770 bx lr 8008cb2: 0049 lsls r1, r1, #1 8008cb4: eb40 0000 adc.w r0, r0, r0 8008cb8: 3a01 subs r2, #1 8008cba: bf28 it cs 8008cbc: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000 8008cc0: d2ed bcs.n 8008c9e <__addsf3+0x92> 8008cc2: fab0 fc80 clz ip, r0 8008cc6: f1ac 0c08 sub.w ip, ip, #8 8008cca: ebb2 020c subs.w r2, r2, ip 8008cce: fa00 f00c lsl.w r0, r0, ip 8008cd2: bfaa itet ge 8008cd4: eb00 50c2 addge.w r0, r0, r2, lsl #23 8008cd8: 4252 neglt r2, r2 8008cda: 4318 orrge r0, r3 8008cdc: bfbc itt lt 8008cde: 40d0 lsrlt r0, r2 8008ce0: 4318 orrlt r0, r3 8008ce2: 4770 bx lr 8008ce4: f092 0f00 teq r2, #0 8008ce8: f481 0100 eor.w r1, r1, #8388608 @ 0x800000 8008cec: bf06 itte eq 8008cee: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000 8008cf2: 3201 addeq r2, #1 8008cf4: 3b01 subne r3, #1 8008cf6: e7b5 b.n 8008c64 <__addsf3+0x58> 8008cf8: ea4f 0341 mov.w r3, r1, lsl #1 8008cfc: ea7f 6c22 mvns.w ip, r2, asr #24 8008d00: bf18 it ne 8008d02: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008d06: d021 beq.n 8008d4c <__addsf3+0x140> 8008d08: ea92 0f03 teq r2, r3 8008d0c: d004 beq.n 8008d18 <__addsf3+0x10c> 8008d0e: f092 0f00 teq r2, #0 8008d12: bf08 it eq 8008d14: 4608 moveq r0, r1 8008d16: 4770 bx lr 8008d18: ea90 0f01 teq r0, r1 8008d1c: bf1c itt ne 8008d1e: 2000 movne r0, #0 8008d20: 4770 bxne lr 8008d22: f012 4f7f tst.w r2, #4278190080 @ 0xff000000 8008d26: d104 bne.n 8008d32 <__addsf3+0x126> 8008d28: 0040 lsls r0, r0, #1 8008d2a: bf28 it cs 8008d2c: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000 8008d30: 4770 bx lr 8008d32: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000 8008d36: bf3c itt cc 8008d38: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000 8008d3c: 4770 bxcc lr 8008d3e: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008d42: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000 8008d46: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008d4a: 4770 bx lr 8008d4c: ea7f 6222 mvns.w r2, r2, asr #24 8008d50: bf16 itet ne 8008d52: 4608 movne r0, r1 8008d54: ea7f 6323 mvnseq.w r3, r3, asr #24 8008d58: 4601 movne r1, r0 8008d5a: 0242 lsls r2, r0, #9 8008d5c: bf06 itte eq 8008d5e: ea5f 2341 movseq.w r3, r1, lsl #9 8008d62: ea90 0f01 teqeq r0, r1 8008d66: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000 8008d6a: 4770 bx lr 08008d6c <__aeabi_ui2f>: 8008d6c: f04f 0300 mov.w r3, #0 8008d70: e004 b.n 8008d7c <__aeabi_i2f+0x8> 8008d72: bf00 nop 08008d74 <__aeabi_i2f>: 8008d74: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000 8008d78: bf48 it mi 8008d7a: 4240 negmi r0, r0 8008d7c: ea5f 0c00 movs.w ip, r0 8008d80: bf08 it eq 8008d82: 4770 bxeq lr 8008d84: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000 8008d88: 4601 mov r1, r0 8008d8a: f04f 0000 mov.w r0, #0 8008d8e: e01c b.n 8008dca <__aeabi_l2f+0x2a> 08008d90 <__aeabi_ul2f>: 8008d90: ea50 0201 orrs.w r2, r0, r1 8008d94: bf08 it eq 8008d96: 4770 bxeq lr 8008d98: f04f 0300 mov.w r3, #0 8008d9c: e00a b.n 8008db4 <__aeabi_l2f+0x14> 8008d9e: bf00 nop 08008da0 <__aeabi_l2f>: 8008da0: ea50 0201 orrs.w r2, r0, r1 8008da4: bf08 it eq 8008da6: 4770 bxeq lr 8008da8: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000 8008dac: d502 bpl.n 8008db4 <__aeabi_l2f+0x14> 8008dae: 4240 negs r0, r0 8008db0: eb61 0141 sbc.w r1, r1, r1, lsl #1 8008db4: ea5f 0c01 movs.w ip, r1 8008db8: bf02 ittt eq 8008dba: 4684 moveq ip, r0 8008dbc: 4601 moveq r1, r0 8008dbe: 2000 moveq r0, #0 8008dc0: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000 8008dc4: bf08 it eq 8008dc6: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000 8008dca: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 8008dce: fabc f28c clz r2, ip 8008dd2: 3a08 subs r2, #8 8008dd4: eba3 53c2 sub.w r3, r3, r2, lsl #23 8008dd8: db10 blt.n 8008dfc <__aeabi_l2f+0x5c> 8008dda: fa01 fc02 lsl.w ip, r1, r2 8008dde: 4463 add r3, ip 8008de0: fa00 fc02 lsl.w ip, r0, r2 8008de4: f1c2 0220 rsb r2, r2, #32 8008de8: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008dec: fa20 f202 lsr.w r2, r0, r2 8008df0: eb43 0002 adc.w r0, r3, r2 8008df4: bf08 it eq 8008df6: f020 0001 biceq.w r0, r0, #1 8008dfa: 4770 bx lr 8008dfc: f102 0220 add.w r2, r2, #32 8008e00: fa01 fc02 lsl.w ip, r1, r2 8008e04: f1c2 0220 rsb r2, r2, #32 8008e08: ea50 004c orrs.w r0, r0, ip, lsl #1 8008e0c: fa21 f202 lsr.w r2, r1, r2 8008e10: eb43 0002 adc.w r0, r3, r2 8008e14: bf08 it eq 8008e16: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008e1a: 4770 bx lr 08008e1c <__aeabi_fmul>: 8008e1c: f04f 0cff mov.w ip, #255 @ 0xff 8008e20: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008e24: bf1e ittt ne 8008e26: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008e2a: ea92 0f0c teqne r2, ip 8008e2e: ea93 0f0c teqne r3, ip 8008e32: d06f beq.n 8008f14 <__aeabi_fmul+0xf8> 8008e34: 441a add r2, r3 8008e36: ea80 0c01 eor.w ip, r0, r1 8008e3a: 0240 lsls r0, r0, #9 8008e3c: bf18 it ne 8008e3e: ea5f 2141 movsne.w r1, r1, lsl #9 8008e42: d01e beq.n 8008e82 <__aeabi_fmul+0x66> 8008e44: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8008e48: ea43 1050 orr.w r0, r3, r0, lsr #5 8008e4c: ea43 1151 orr.w r1, r3, r1, lsr #5 8008e50: fba0 3101 umull r3, r1, r0, r1 8008e54: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008e58: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000 8008e5c: bf3e ittt cc 8008e5e: 0049 lslcc r1, r1, #1 8008e60: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 8008e64: 005b lslcc r3, r3, #1 8008e66: ea40 0001 orr.w r0, r0, r1 8008e6a: f162 027f sbc.w r2, r2, #127 @ 0x7f 8008e6e: 2afd cmp r2, #253 @ 0xfd 8008e70: d81d bhi.n 8008eae <__aeabi_fmul+0x92> 8008e72: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008e76: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008e7a: bf08 it eq 8008e7c: f020 0001 biceq.w r0, r0, #1 8008e80: 4770 bx lr 8008e82: f090 0f00 teq r0, #0 8008e86: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8008e8a: bf08 it eq 8008e8c: 0249 lsleq r1, r1, #9 8008e8e: ea4c 2050 orr.w r0, ip, r0, lsr #9 8008e92: ea40 2051 orr.w r0, r0, r1, lsr #9 8008e96: 3a7f subs r2, #127 @ 0x7f 8008e98: bfc2 ittt gt 8008e9a: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 8008e9e: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8008ea2: 4770 bxgt lr 8008ea4: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008ea8: f04f 0300 mov.w r3, #0 8008eac: 3a01 subs r2, #1 8008eae: dc5d bgt.n 8008f6c <__aeabi_fmul+0x150> 8008eb0: f112 0f19 cmn.w r2, #25 8008eb4: bfdc itt le 8008eb6: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000 8008eba: 4770 bxle lr 8008ebc: f1c2 0200 rsb r2, r2, #0 8008ec0: 0041 lsls r1, r0, #1 8008ec2: fa21 f102 lsr.w r1, r1, r2 8008ec6: f1c2 0220 rsb r2, r2, #32 8008eca: fa00 fc02 lsl.w ip, r0, r2 8008ece: ea5f 0031 movs.w r0, r1, rrx 8008ed2: f140 0000 adc.w r0, r0, #0 8008ed6: ea53 034c orrs.w r3, r3, ip, lsl #1 8008eda: bf08 it eq 8008edc: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008ee0: 4770 bx lr 8008ee2: f092 0f00 teq r2, #0 8008ee6: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8008eea: bf02 ittt eq 8008eec: 0040 lsleq r0, r0, #1 8008eee: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 8008ef2: 3a01 subeq r2, #1 8008ef4: d0f9 beq.n 8008eea <__aeabi_fmul+0xce> 8008ef6: ea40 000c orr.w r0, r0, ip 8008efa: f093 0f00 teq r3, #0 8008efe: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008f02: bf02 ittt eq 8008f04: 0049 lsleq r1, r1, #1 8008f06: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8008f0a: 3b01 subeq r3, #1 8008f0c: d0f9 beq.n 8008f02 <__aeabi_fmul+0xe6> 8008f0e: ea41 010c orr.w r1, r1, ip 8008f12: e78f b.n 8008e34 <__aeabi_fmul+0x18> 8008f14: ea0c 53d1 and.w r3, ip, r1, lsr #23 8008f18: ea92 0f0c teq r2, ip 8008f1c: bf18 it ne 8008f1e: ea93 0f0c teqne r3, ip 8008f22: d00a beq.n 8008f3a <__aeabi_fmul+0x11e> 8008f24: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 8008f28: bf18 it ne 8008f2a: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 8008f2e: d1d8 bne.n 8008ee2 <__aeabi_fmul+0xc6> 8008f30: ea80 0001 eor.w r0, r0, r1 8008f34: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008f38: 4770 bx lr 8008f3a: f090 0f00 teq r0, #0 8008f3e: bf17 itett ne 8008f40: f090 4f00 teqne r0, #2147483648 @ 0x80000000 8008f44: 4608 moveq r0, r1 8008f46: f091 0f00 teqne r1, #0 8008f4a: f091 4f00 teqne r1, #2147483648 @ 0x80000000 8008f4e: d014 beq.n 8008f7a <__aeabi_fmul+0x15e> 8008f50: ea92 0f0c teq r2, ip 8008f54: d101 bne.n 8008f5a <__aeabi_fmul+0x13e> 8008f56: 0242 lsls r2, r0, #9 8008f58: d10f bne.n 8008f7a <__aeabi_fmul+0x15e> 8008f5a: ea93 0f0c teq r3, ip 8008f5e: d103 bne.n 8008f68 <__aeabi_fmul+0x14c> 8008f60: 024b lsls r3, r1, #9 8008f62: bf18 it ne 8008f64: 4608 movne r0, r1 8008f66: d108 bne.n 8008f7a <__aeabi_fmul+0x15e> 8008f68: ea80 0001 eor.w r0, r0, r1 8008f6c: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008f70: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008f74: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008f78: 4770 bx lr 8008f7a: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008f7e: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000 8008f82: 4770 bx lr 08008f84 <__aeabi_fdiv>: 8008f84: f04f 0cff mov.w ip, #255 @ 0xff 8008f88: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008f8c: bf1e ittt ne 8008f8e: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008f92: ea92 0f0c teqne r2, ip 8008f96: ea93 0f0c teqne r3, ip 8008f9a: d069 beq.n 8009070 <__aeabi_fdiv+0xec> 8008f9c: eba2 0203 sub.w r2, r2, r3 8008fa0: ea80 0c01 eor.w ip, r0, r1 8008fa4: 0249 lsls r1, r1, #9 8008fa6: ea4f 2040 mov.w r0, r0, lsl #9 8008faa: d037 beq.n 800901c <__aeabi_fdiv+0x98> 8008fac: f04f 5380 mov.w r3, #268435456 @ 0x10000000 8008fb0: ea43 1111 orr.w r1, r3, r1, lsr #4 8008fb4: ea43 1310 orr.w r3, r3, r0, lsr #4 8008fb8: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008fbc: 428b cmp r3, r1 8008fbe: bf38 it cc 8008fc0: 005b lslcc r3, r3, #1 8008fc2: f142 027d adc.w r2, r2, #125 @ 0x7d 8008fc6: f44f 0c00 mov.w ip, #8388608 @ 0x800000 8008fca: 428b cmp r3, r1 8008fcc: bf24 itt cs 8008fce: 1a5b subcs r3, r3, r1 8008fd0: ea40 000c orrcs.w r0, r0, ip 8008fd4: ebb3 0f51 cmp.w r3, r1, lsr #1 8008fd8: bf24 itt cs 8008fda: eba3 0351 subcs.w r3, r3, r1, lsr #1 8008fde: ea40 005c orrcs.w r0, r0, ip, lsr #1 8008fe2: ebb3 0f91 cmp.w r3, r1, lsr #2 8008fe6: bf24 itt cs 8008fe8: eba3 0391 subcs.w r3, r3, r1, lsr #2 8008fec: ea40 009c orrcs.w r0, r0, ip, lsr #2 8008ff0: ebb3 0fd1 cmp.w r3, r1, lsr #3 8008ff4: bf24 itt cs 8008ff6: eba3 03d1 subcs.w r3, r3, r1, lsr #3 8008ffa: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8008ffe: 011b lsls r3, r3, #4 8009000: bf18 it ne 8009002: ea5f 1c1c movsne.w ip, ip, lsr #4 8009006: d1e0 bne.n 8008fca <__aeabi_fdiv+0x46> 8009008: 2afd cmp r2, #253 @ 0xfd 800900a: f63f af50 bhi.w 8008eae <__aeabi_fmul+0x92> 800900e: 428b cmp r3, r1 8009010: eb40 50c2 adc.w r0, r0, r2, lsl #23 8009014: bf08 it eq 8009016: f020 0001 biceq.w r0, r0, #1 800901a: 4770 bx lr 800901c: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8009020: ea4c 2050 orr.w r0, ip, r0, lsr #9 8009024: 327f adds r2, #127 @ 0x7f 8009026: bfc2 ittt gt 8009028: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 800902c: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8009030: 4770 bxgt lr 8009032: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8009036: f04f 0300 mov.w r3, #0 800903a: 3a01 subs r2, #1 800903c: e737 b.n 8008eae <__aeabi_fmul+0x92> 800903e: f092 0f00 teq r2, #0 8009042: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8009046: bf02 ittt eq 8009048: 0040 lsleq r0, r0, #1 800904a: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 800904e: 3a01 subeq r2, #1 8009050: d0f9 beq.n 8009046 <__aeabi_fdiv+0xc2> 8009052: ea40 000c orr.w r0, r0, ip 8009056: f093 0f00 teq r3, #0 800905a: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 800905e: bf02 ittt eq 8009060: 0049 lsleq r1, r1, #1 8009062: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8009066: 3b01 subeq r3, #1 8009068: d0f9 beq.n 800905e <__aeabi_fdiv+0xda> 800906a: ea41 010c orr.w r1, r1, ip 800906e: e795 b.n 8008f9c <__aeabi_fdiv+0x18> 8009070: ea0c 53d1 and.w r3, ip, r1, lsr #23 8009074: ea92 0f0c teq r2, ip 8009078: d108 bne.n 800908c <__aeabi_fdiv+0x108> 800907a: 0242 lsls r2, r0, #9 800907c: f47f af7d bne.w 8008f7a <__aeabi_fmul+0x15e> 8009080: ea93 0f0c teq r3, ip 8009084: f47f af70 bne.w 8008f68 <__aeabi_fmul+0x14c> 8009088: 4608 mov r0, r1 800908a: e776 b.n 8008f7a <__aeabi_fmul+0x15e> 800908c: ea93 0f0c teq r3, ip 8009090: d104 bne.n 800909c <__aeabi_fdiv+0x118> 8009092: 024b lsls r3, r1, #9 8009094: f43f af4c beq.w 8008f30 <__aeabi_fmul+0x114> 8009098: 4608 mov r0, r1 800909a: e76e b.n 8008f7a <__aeabi_fmul+0x15e> 800909c: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 80090a0: bf18 it ne 80090a2: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 80090a6: d1ca bne.n 800903e <__aeabi_fdiv+0xba> 80090a8: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000 80090ac: f47f af5c bne.w 8008f68 <__aeabi_fmul+0x14c> 80090b0: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000 80090b4: f47f af3c bne.w 8008f30 <__aeabi_fmul+0x114> 80090b8: e75f b.n 8008f7a <__aeabi_fmul+0x15e> 80090ba: bf00 nop 080090bc <__gesf2>: 80090bc: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80090c0: e006 b.n 80090d0 <__cmpsf2+0x4> 80090c2: bf00 nop 080090c4 <__lesf2>: 80090c4: f04f 0c01 mov.w ip, #1 80090c8: e002 b.n 80090d0 <__cmpsf2+0x4> 80090ca: bf00 nop 080090cc <__cmpsf2>: 80090cc: f04f 0c01 mov.w ip, #1 80090d0: f84d cd04 str.w ip, [sp, #-4]! 80090d4: ea4f 0240 mov.w r2, r0, lsl #1 80090d8: ea4f 0341 mov.w r3, r1, lsl #1 80090dc: ea7f 6c22 mvns.w ip, r2, asr #24 80090e0: bf18 it ne 80090e2: ea7f 6c23 mvnsne.w ip, r3, asr #24 80090e6: d011 beq.n 800910c <__cmpsf2+0x40> 80090e8: b001 add sp, #4 80090ea: ea52 0c53 orrs.w ip, r2, r3, lsr #1 80090ee: bf18 it ne 80090f0: ea90 0f01 teqne r0, r1 80090f4: bf58 it pl 80090f6: ebb2 0003 subspl.w r0, r2, r3 80090fa: bf88 it hi 80090fc: 17c8 asrhi r0, r1, #31 80090fe: bf38 it cc 8009100: ea6f 70e1 mvncc.w r0, r1, asr #31 8009104: bf18 it ne 8009106: f040 0001 orrne.w r0, r0, #1 800910a: 4770 bx lr 800910c: ea7f 6c22 mvns.w ip, r2, asr #24 8009110: d102 bne.n 8009118 <__cmpsf2+0x4c> 8009112: ea5f 2c40 movs.w ip, r0, lsl #9 8009116: d105 bne.n 8009124 <__cmpsf2+0x58> 8009118: ea7f 6c23 mvns.w ip, r3, asr #24 800911c: d1e4 bne.n 80090e8 <__cmpsf2+0x1c> 800911e: ea5f 2c41 movs.w ip, r1, lsl #9 8009122: d0e1 beq.n 80090e8 <__cmpsf2+0x1c> 8009124: f85d 0b04 ldr.w r0, [sp], #4 8009128: 4770 bx lr 800912a: bf00 nop 0800912c <__aeabi_cfrcmple>: 800912c: 4684 mov ip, r0 800912e: 4608 mov r0, r1 8009130: 4661 mov r1, ip 8009132: e7ff b.n 8009134 <__aeabi_cfcmpeq> 08009134 <__aeabi_cfcmpeq>: 8009134: b50f push {r0, r1, r2, r3, lr} 8009136: f7ff ffc9 bl 80090cc <__cmpsf2> 800913a: 2800 cmp r0, #0 800913c: bf48 it mi 800913e: f110 0f00 cmnmi.w r0, #0 8009142: bd0f pop {r0, r1, r2, r3, pc} 08009144 <__aeabi_fcmpeq>: 8009144: f84d ed08 str.w lr, [sp, #-8]! 8009148: f7ff fff4 bl 8009134 <__aeabi_cfcmpeq> 800914c: bf0c ite eq 800914e: 2001 moveq r0, #1 8009150: 2000 movne r0, #0 8009152: f85d fb08 ldr.w pc, [sp], #8 8009156: bf00 nop 08009158 <__aeabi_fcmplt>: 8009158: f84d ed08 str.w lr, [sp, #-8]! 800915c: f7ff ffea bl 8009134 <__aeabi_cfcmpeq> 8009160: bf34 ite cc 8009162: 2001 movcc r0, #1 8009164: 2000 movcs r0, #0 8009166: f85d fb08 ldr.w pc, [sp], #8 800916a: bf00 nop 0800916c <__aeabi_fcmple>: 800916c: f84d ed08 str.w lr, [sp, #-8]! 8009170: f7ff ffe0 bl 8009134 <__aeabi_cfcmpeq> 8009174: bf94 ite ls 8009176: 2001 movls r0, #1 8009178: 2000 movhi r0, #0 800917a: f85d fb08 ldr.w pc, [sp], #8 800917e: bf00 nop 08009180 <__aeabi_fcmpge>: 8009180: f84d ed08 str.w lr, [sp, #-8]! 8009184: f7ff ffd2 bl 800912c <__aeabi_cfrcmple> 8009188: bf94 ite ls 800918a: 2001 movls r0, #1 800918c: 2000 movhi r0, #0 800918e: f85d fb08 ldr.w pc, [sp], #8 8009192: bf00 nop 08009194 <__aeabi_fcmpgt>: 8009194: f84d ed08 str.w lr, [sp, #-8]! 8009198: f7ff ffc8 bl 800912c <__aeabi_cfrcmple> 800919c: bf34 ite cc 800919e: 2001 movcc r0, #1 80091a0: 2000 movcs r0, #0 80091a2: f85d fb08 ldr.w pc, [sp], #8 80091a6: bf00 nop 080091a8 <__aeabi_f2iz>: 80091a8: ea4f 0240 mov.w r2, r0, lsl #1 80091ac: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000 80091b0: d30f bcc.n 80091d2 <__aeabi_f2iz+0x2a> 80091b2: f04f 039e mov.w r3, #158 @ 0x9e 80091b6: ebb3 6212 subs.w r2, r3, r2, lsr #24 80091ba: d90d bls.n 80091d8 <__aeabi_f2iz+0x30> 80091bc: ea4f 2300 mov.w r3, r0, lsl #8 80091c0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80091c4: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 80091c8: fa23 f002 lsr.w r0, r3, r2 80091cc: bf18 it ne 80091ce: 4240 negne r0, r0 80091d0: 4770 bx lr 80091d2: f04f 0000 mov.w r0, #0 80091d6: 4770 bx lr 80091d8: f112 0f61 cmn.w r2, #97 @ 0x61 80091dc: d101 bne.n 80091e2 <__aeabi_f2iz+0x3a> 80091de: 0242 lsls r2, r0, #9 80091e0: d105 bne.n 80091ee <__aeabi_f2iz+0x46> 80091e2: f010 4000 ands.w r0, r0, #2147483648 @ 0x80000000 80091e6: bf08 it eq 80091e8: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 80091ec: 4770 bx lr 80091ee: f04f 0000 mov.w r0, #0 80091f2: 4770 bx lr 080091f4 <__aeabi_uldivmod>: 80091f4: b953 cbnz r3, 800920c <__aeabi_uldivmod+0x18> 80091f6: b94a cbnz r2, 800920c <__aeabi_uldivmod+0x18> 80091f8: 2900 cmp r1, #0 80091fa: bf08 it eq 80091fc: 2800 cmpeq r0, #0 80091fe: bf1c itt ne 8009200: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8009204: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8009208: f000 b98c b.w 8009524 <__aeabi_idiv0> 800920c: f1ad 0c08 sub.w ip, sp, #8 8009210: e96d ce04 strd ip, lr, [sp, #-16]! 8009214: f000 f806 bl 8009224 <__udivmoddi4> 8009218: f8dd e004 ldr.w lr, [sp, #4] 800921c: e9dd 2302 ldrd r2, r3, [sp, #8] 8009220: b004 add sp, #16 8009222: 4770 bx lr 08009224 <__udivmoddi4>: 8009224: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8009228: 9d08 ldr r5, [sp, #32] 800922a: 468e mov lr, r1 800922c: 4604 mov r4, r0 800922e: 4688 mov r8, r1 8009230: 2b00 cmp r3, #0 8009232: d14a bne.n 80092ca <__udivmoddi4+0xa6> 8009234: 428a cmp r2, r1 8009236: 4617 mov r7, r2 8009238: d962 bls.n 8009300 <__udivmoddi4+0xdc> 800923a: fab2 f682 clz r6, r2 800923e: b14e cbz r6, 8009254 <__udivmoddi4+0x30> 8009240: f1c6 0320 rsb r3, r6, #32 8009244: fa01 f806 lsl.w r8, r1, r6 8009248: fa20 f303 lsr.w r3, r0, r3 800924c: 40b7 lsls r7, r6 800924e: ea43 0808 orr.w r8, r3, r8 8009252: 40b4 lsls r4, r6 8009254: ea4f 4e17 mov.w lr, r7, lsr #16 8009258: fbb8 f1fe udiv r1, r8, lr 800925c: fa1f fc87 uxth.w ip, r7 8009260: fb0e 8811 mls r8, lr, r1, r8 8009264: fb01 f20c mul.w r2, r1, ip 8009268: 0c23 lsrs r3, r4, #16 800926a: ea43 4308 orr.w r3, r3, r8, lsl #16 800926e: 429a cmp r2, r3 8009270: d909 bls.n 8009286 <__udivmoddi4+0x62> 8009272: 18fb adds r3, r7, r3 8009274: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8009278: f080 80eb bcs.w 8009452 <__udivmoddi4+0x22e> 800927c: 429a cmp r2, r3 800927e: f240 80e8 bls.w 8009452 <__udivmoddi4+0x22e> 8009282: 3902 subs r1, #2 8009284: 443b add r3, r7 8009286: 1a9a subs r2, r3, r2 8009288: fbb2 f0fe udiv r0, r2, lr 800928c: fb0e 2210 mls r2, lr, r0, r2 8009290: fb00 fc0c mul.w ip, r0, ip 8009294: b2a3 uxth r3, r4 8009296: ea43 4302 orr.w r3, r3, r2, lsl #16 800929a: 459c cmp ip, r3 800929c: d909 bls.n 80092b2 <__udivmoddi4+0x8e> 800929e: 18fb adds r3, r7, r3 80092a0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80092a4: f080 80d7 bcs.w 8009456 <__udivmoddi4+0x232> 80092a8: 459c cmp ip, r3 80092aa: f240 80d4 bls.w 8009456 <__udivmoddi4+0x232> 80092ae: 443b add r3, r7 80092b0: 3802 subs r0, #2 80092b2: ea40 4001 orr.w r0, r0, r1, lsl #16 80092b6: 2100 movs r1, #0 80092b8: eba3 030c sub.w r3, r3, ip 80092bc: b11d cbz r5, 80092c6 <__udivmoddi4+0xa2> 80092be: 2200 movs r2, #0 80092c0: 40f3 lsrs r3, r6 80092c2: e9c5 3200 strd r3, r2, [r5] 80092c6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80092ca: 428b cmp r3, r1 80092cc: d905 bls.n 80092da <__udivmoddi4+0xb6> 80092ce: b10d cbz r5, 80092d4 <__udivmoddi4+0xb0> 80092d0: e9c5 0100 strd r0, r1, [r5] 80092d4: 2100 movs r1, #0 80092d6: 4608 mov r0, r1 80092d8: e7f5 b.n 80092c6 <__udivmoddi4+0xa2> 80092da: fab3 f183 clz r1, r3 80092de: 2900 cmp r1, #0 80092e0: d146 bne.n 8009370 <__udivmoddi4+0x14c> 80092e2: 4573 cmp r3, lr 80092e4: d302 bcc.n 80092ec <__udivmoddi4+0xc8> 80092e6: 4282 cmp r2, r0 80092e8: f200 8108 bhi.w 80094fc <__udivmoddi4+0x2d8> 80092ec: 1a84 subs r4, r0, r2 80092ee: eb6e 0203 sbc.w r2, lr, r3 80092f2: 2001 movs r0, #1 80092f4: 4690 mov r8, r2 80092f6: 2d00 cmp r5, #0 80092f8: d0e5 beq.n 80092c6 <__udivmoddi4+0xa2> 80092fa: e9c5 4800 strd r4, r8, [r5] 80092fe: e7e2 b.n 80092c6 <__udivmoddi4+0xa2> 8009300: 2a00 cmp r2, #0 8009302: f000 8091 beq.w 8009428 <__udivmoddi4+0x204> 8009306: fab2 f682 clz r6, r2 800930a: 2e00 cmp r6, #0 800930c: f040 80a5 bne.w 800945a <__udivmoddi4+0x236> 8009310: 1a8a subs r2, r1, r2 8009312: 2101 movs r1, #1 8009314: 0c03 lsrs r3, r0, #16 8009316: ea4f 4e17 mov.w lr, r7, lsr #16 800931a: b280 uxth r0, r0 800931c: b2bc uxth r4, r7 800931e: fbb2 fcfe udiv ip, r2, lr 8009322: fb0e 221c mls r2, lr, ip, r2 8009326: ea43 4302 orr.w r3, r3, r2, lsl #16 800932a: fb04 f20c mul.w r2, r4, ip 800932e: 429a cmp r2, r3 8009330: d907 bls.n 8009342 <__udivmoddi4+0x11e> 8009332: 18fb adds r3, r7, r3 8009334: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8009338: d202 bcs.n 8009340 <__udivmoddi4+0x11c> 800933a: 429a cmp r2, r3 800933c: f200 80e3 bhi.w 8009506 <__udivmoddi4+0x2e2> 8009340: 46c4 mov ip, r8 8009342: 1a9b subs r3, r3, r2 8009344: fbb3 f2fe udiv r2, r3, lr 8009348: fb0e 3312 mls r3, lr, r2, r3 800934c: fb02 f404 mul.w r4, r2, r4 8009350: ea40 4303 orr.w r3, r0, r3, lsl #16 8009354: 429c cmp r4, r3 8009356: d907 bls.n 8009368 <__udivmoddi4+0x144> 8009358: 18fb adds r3, r7, r3 800935a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800935e: d202 bcs.n 8009366 <__udivmoddi4+0x142> 8009360: 429c cmp r4, r3 8009362: f200 80cd bhi.w 8009500 <__udivmoddi4+0x2dc> 8009366: 4602 mov r2, r0 8009368: 1b1b subs r3, r3, r4 800936a: ea42 400c orr.w r0, r2, ip, lsl #16 800936e: e7a5 b.n 80092bc <__udivmoddi4+0x98> 8009370: f1c1 0620 rsb r6, r1, #32 8009374: 408b lsls r3, r1 8009376: fa22 f706 lsr.w r7, r2, r6 800937a: 431f orrs r7, r3 800937c: fa2e fa06 lsr.w sl, lr, r6 8009380: ea4f 4917 mov.w r9, r7, lsr #16 8009384: fbba f8f9 udiv r8, sl, r9 8009388: fa0e fe01 lsl.w lr, lr, r1 800938c: fa20 f306 lsr.w r3, r0, r6 8009390: fb09 aa18 mls sl, r9, r8, sl 8009394: fa1f fc87 uxth.w ip, r7 8009398: ea43 030e orr.w r3, r3, lr 800939c: fa00 fe01 lsl.w lr, r0, r1 80093a0: fb08 f00c mul.w r0, r8, ip 80093a4: 0c1c lsrs r4, r3, #16 80093a6: ea44 440a orr.w r4, r4, sl, lsl #16 80093aa: 42a0 cmp r0, r4 80093ac: fa02 f201 lsl.w r2, r2, r1 80093b0: d90a bls.n 80093c8 <__udivmoddi4+0x1a4> 80093b2: 193c adds r4, r7, r4 80093b4: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff 80093b8: f080 809e bcs.w 80094f8 <__udivmoddi4+0x2d4> 80093bc: 42a0 cmp r0, r4 80093be: f240 809b bls.w 80094f8 <__udivmoddi4+0x2d4> 80093c2: f1a8 0802 sub.w r8, r8, #2 80093c6: 443c add r4, r7 80093c8: 1a24 subs r4, r4, r0 80093ca: b298 uxth r0, r3 80093cc: fbb4 f3f9 udiv r3, r4, r9 80093d0: fb09 4413 mls r4, r9, r3, r4 80093d4: fb03 fc0c mul.w ip, r3, ip 80093d8: ea40 4404 orr.w r4, r0, r4, lsl #16 80093dc: 45a4 cmp ip, r4 80093de: d909 bls.n 80093f4 <__udivmoddi4+0x1d0> 80093e0: 193c adds r4, r7, r4 80093e2: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 80093e6: f080 8085 bcs.w 80094f4 <__udivmoddi4+0x2d0> 80093ea: 45a4 cmp ip, r4 80093ec: f240 8082 bls.w 80094f4 <__udivmoddi4+0x2d0> 80093f0: 3b02 subs r3, #2 80093f2: 443c add r4, r7 80093f4: ea43 4008 orr.w r0, r3, r8, lsl #16 80093f8: eba4 040c sub.w r4, r4, ip 80093fc: fba0 8c02 umull r8, ip, r0, r2 8009400: 4564 cmp r4, ip 8009402: 4643 mov r3, r8 8009404: 46e1 mov r9, ip 8009406: d364 bcc.n 80094d2 <__udivmoddi4+0x2ae> 8009408: d061 beq.n 80094ce <__udivmoddi4+0x2aa> 800940a: b15d cbz r5, 8009424 <__udivmoddi4+0x200> 800940c: ebbe 0203 subs.w r2, lr, r3 8009410: eb64 0409 sbc.w r4, r4, r9 8009414: fa04 f606 lsl.w r6, r4, r6 8009418: fa22 f301 lsr.w r3, r2, r1 800941c: 431e orrs r6, r3 800941e: 40cc lsrs r4, r1 8009420: e9c5 6400 strd r6, r4, [r5] 8009424: 2100 movs r1, #0 8009426: e74e b.n 80092c6 <__udivmoddi4+0xa2> 8009428: fbb1 fcf2 udiv ip, r1, r2 800942c: 0c01 lsrs r1, r0, #16 800942e: ea41 410e orr.w r1, r1, lr, lsl #16 8009432: b280 uxth r0, r0 8009434: ea40 4201 orr.w r2, r0, r1, lsl #16 8009438: 463b mov r3, r7 800943a: fbb1 f1f7 udiv r1, r1, r7 800943e: 4638 mov r0, r7 8009440: 463c mov r4, r7 8009442: 46b8 mov r8, r7 8009444: 46be mov lr, r7 8009446: 2620 movs r6, #32 8009448: eba2 0208 sub.w r2, r2, r8 800944c: ea41 410c orr.w r1, r1, ip, lsl #16 8009450: e765 b.n 800931e <__udivmoddi4+0xfa> 8009452: 4601 mov r1, r0 8009454: e717 b.n 8009286 <__udivmoddi4+0x62> 8009456: 4610 mov r0, r2 8009458: e72b b.n 80092b2 <__udivmoddi4+0x8e> 800945a: f1c6 0120 rsb r1, r6, #32 800945e: fa2e fc01 lsr.w ip, lr, r1 8009462: 40b7 lsls r7, r6 8009464: fa0e fe06 lsl.w lr, lr, r6 8009468: fa20 f101 lsr.w r1, r0, r1 800946c: ea41 010e orr.w r1, r1, lr 8009470: ea4f 4e17 mov.w lr, r7, lsr #16 8009474: fbbc f8fe udiv r8, ip, lr 8009478: b2bc uxth r4, r7 800947a: fb0e cc18 mls ip, lr, r8, ip 800947e: fb08 f904 mul.w r9, r8, r4 8009482: 0c0a lsrs r2, r1, #16 8009484: ea42 420c orr.w r2, r2, ip, lsl #16 8009488: 40b0 lsls r0, r6 800948a: 4591 cmp r9, r2 800948c: ea4f 4310 mov.w r3, r0, lsr #16 8009490: b280 uxth r0, r0 8009492: d93e bls.n 8009512 <__udivmoddi4+0x2ee> 8009494: 18ba adds r2, r7, r2 8009496: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 800949a: d201 bcs.n 80094a0 <__udivmoddi4+0x27c> 800949c: 4591 cmp r9, r2 800949e: d81f bhi.n 80094e0 <__udivmoddi4+0x2bc> 80094a0: eba2 0209 sub.w r2, r2, r9 80094a4: fbb2 f9fe udiv r9, r2, lr 80094a8: fb09 f804 mul.w r8, r9, r4 80094ac: fb0e 2a19 mls sl, lr, r9, r2 80094b0: b28a uxth r2, r1 80094b2: ea42 420a orr.w r2, r2, sl, lsl #16 80094b6: 4542 cmp r2, r8 80094b8: d229 bcs.n 800950e <__udivmoddi4+0x2ea> 80094ba: 18ba adds r2, r7, r2 80094bc: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80094c0: d2c2 bcs.n 8009448 <__udivmoddi4+0x224> 80094c2: 4542 cmp r2, r8 80094c4: d2c0 bcs.n 8009448 <__udivmoddi4+0x224> 80094c6: f1a9 0102 sub.w r1, r9, #2 80094ca: 443a add r2, r7 80094cc: e7bc b.n 8009448 <__udivmoddi4+0x224> 80094ce: 45c6 cmp lr, r8 80094d0: d29b bcs.n 800940a <__udivmoddi4+0x1e6> 80094d2: ebb8 0302 subs.w r3, r8, r2 80094d6: eb6c 0c07 sbc.w ip, ip, r7 80094da: 3801 subs r0, #1 80094dc: 46e1 mov r9, ip 80094de: e794 b.n 800940a <__udivmoddi4+0x1e6> 80094e0: eba7 0909 sub.w r9, r7, r9 80094e4: 444a add r2, r9 80094e6: fbb2 f9fe udiv r9, r2, lr 80094ea: f1a8 0c02 sub.w ip, r8, #2 80094ee: fb09 f804 mul.w r8, r9, r4 80094f2: e7db b.n 80094ac <__udivmoddi4+0x288> 80094f4: 4603 mov r3, r0 80094f6: e77d b.n 80093f4 <__udivmoddi4+0x1d0> 80094f8: 46d0 mov r8, sl 80094fa: e765 b.n 80093c8 <__udivmoddi4+0x1a4> 80094fc: 4608 mov r0, r1 80094fe: e6fa b.n 80092f6 <__udivmoddi4+0xd2> 8009500: 443b add r3, r7 8009502: 3a02 subs r2, #2 8009504: e730 b.n 8009368 <__udivmoddi4+0x144> 8009506: f1ac 0c02 sub.w ip, ip, #2 800950a: 443b add r3, r7 800950c: e719 b.n 8009342 <__udivmoddi4+0x11e> 800950e: 4649 mov r1, r9 8009510: e79a b.n 8009448 <__udivmoddi4+0x224> 8009512: eba2 0209 sub.w r2, r2, r9 8009516: fbb2 f9fe udiv r9, r2, lr 800951a: 46c4 mov ip, r8 800951c: fb09 f804 mul.w r8, r9, r4 8009520: e7c4 b.n 80094ac <__udivmoddi4+0x288> 8009522: bf00 nop 08009524 <__aeabi_idiv0>: 8009524: 4770 bx lr 8009526: bf00 nop 08009528 : ADC_HandleTypeDef hadc1; /* ADC1 init function */ void MX_ADC1_Init(void) { 8009528: b580 push {r7, lr} 800952a: b084 sub sp, #16 800952c: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 800952e: 1d3b adds r3, r7, #4 8009530: 2200 movs r2, #0 8009532: 601a str r2, [r3, #0] 8009534: 605a str r2, [r3, #4] 8009536: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 8009538: 4b18 ldr r3, [pc, #96] @ (800959c ) 800953a: 4a19 ldr r2, [pc, #100] @ (80095a0 ) 800953c: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 800953e: 4b17 ldr r3, [pc, #92] @ (800959c ) 8009540: 2200 movs r2, #0 8009542: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = DISABLE; 8009544: 4b15 ldr r3, [pc, #84] @ (800959c ) 8009546: 2200 movs r2, #0 8009548: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 800954a: 4b14 ldr r3, [pc, #80] @ (800959c ) 800954c: 2200 movs r2, #0 800954e: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8009550: 4b12 ldr r3, [pc, #72] @ (800959c ) 8009552: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009556: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 8009558: 4b10 ldr r3, [pc, #64] @ (800959c ) 800955a: 2200 movs r2, #0 800955c: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 1; 800955e: 4b0f ldr r3, [pc, #60] @ (800959c ) 8009560: 2201 movs r2, #1 8009562: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 8009564: 480d ldr r0, [pc, #52] @ (800959c ) 8009566: f004 fb31 bl 800dbcc 800956a: 4603 mov r3, r0 800956c: 2b00 cmp r3, #0 800956e: d001 beq.n 8009574 { Error_Handler(); 8009570: f001 fb14 bl 800ab9c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8009574: 2308 movs r3, #8 8009576: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8009578: 2301 movs r3, #1 800957a: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 800957c: 2300 movs r3, #0 800957e: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8009580: 1d3b adds r3, r7, #4 8009582: 4619 mov r1, r3 8009584: 4805 ldr r0, [pc, #20] @ (800959c ) 8009586: f004 fde5 bl 800e154 800958a: 4603 mov r3, r0 800958c: 2b00 cmp r3, #0 800958e: d001 beq.n 8009594 { Error_Handler(); 8009590: f001 fb04 bl 800ab9c } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 8009594: bf00 nop 8009596: 3710 adds r7, #16 8009598: 46bd mov sp, r7 800959a: bd80 pop {r7, pc} 800959c: 2000025c .word 0x2000025c 80095a0: 40012400 .word 0x40012400 080095a4 : void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 80095a4: b580 push {r7, lr} 80095a6: b08a sub sp, #40 @ 0x28 80095a8: af00 add r7, sp, #0 80095aa: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80095ac: f107 0318 add.w r3, r7, #24 80095b0: 2200 movs r2, #0 80095b2: 601a str r2, [r3, #0] 80095b4: 605a str r2, [r3, #4] 80095b6: 609a str r2, [r3, #8] 80095b8: 60da str r2, [r3, #12] if(adcHandle->Instance==ADC1) 80095ba: 687b ldr r3, [r7, #4] 80095bc: 681b ldr r3, [r3, #0] 80095be: 4a1f ldr r2, [pc, #124] @ (800963c ) 80095c0: 4293 cmp r3, r2 80095c2: d137 bne.n 8009634 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 80095c4: 4b1e ldr r3, [pc, #120] @ (8009640 ) 80095c6: 699b ldr r3, [r3, #24] 80095c8: 4a1d ldr r2, [pc, #116] @ (8009640 ) 80095ca: f443 7300 orr.w r3, r3, #512 @ 0x200 80095ce: 6193 str r3, [r2, #24] 80095d0: 4b1b ldr r3, [pc, #108] @ (8009640 ) 80095d2: 699b ldr r3, [r3, #24] 80095d4: f403 7300 and.w r3, r3, #512 @ 0x200 80095d8: 617b str r3, [r7, #20] 80095da: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 80095dc: 4b18 ldr r3, [pc, #96] @ (8009640 ) 80095de: 699b ldr r3, [r3, #24] 80095e0: 4a17 ldr r2, [pc, #92] @ (8009640 ) 80095e2: f043 0304 orr.w r3, r3, #4 80095e6: 6193 str r3, [r2, #24] 80095e8: 4b15 ldr r3, [pc, #84] @ (8009640 ) 80095ea: 699b ldr r3, [r3, #24] 80095ec: f003 0304 and.w r3, r3, #4 80095f0: 613b str r3, [r7, #16] 80095f2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80095f4: 4b12 ldr r3, [pc, #72] @ (8009640 ) 80095f6: 699b ldr r3, [r3, #24] 80095f8: 4a11 ldr r2, [pc, #68] @ (8009640 ) 80095fa: f043 0308 orr.w r3, r3, #8 80095fe: 6193 str r3, [r2, #24] 8009600: 4b0f ldr r3, [pc, #60] @ (8009640 ) 8009602: 699b ldr r3, [r3, #24] 8009604: f003 0308 and.w r3, r3, #8 8009608: 60fb str r3, [r7, #12] 800960a: 68fb ldr r3, [r7, #12] PA3 ------> ADC1_IN3 PA4 ------> ADC1_IN4 PB0 ------> ADC1_IN8 PB1 ------> ADC1_IN9 */ GPIO_InitStruct.Pin = GPIO_PIN_3|CP_ADC_Pin; 800960c: 2318 movs r3, #24 800960e: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009610: 2303 movs r3, #3 8009612: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8009614: f107 0318 add.w r3, r7, #24 8009618: 4619 mov r1, r3 800961a: 480a ldr r0, [pc, #40] @ (8009644 ) 800961c: f006 f91e bl 800f85c GPIO_InitStruct.Pin = ADC_NTC1_Pin|ADC_NTC2_Pin; 8009620: 2303 movs r3, #3 8009622: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009624: 2303 movs r3, #3 8009626: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009628: f107 0318 add.w r3, r7, #24 800962c: 4619 mov r1, r3 800962e: 4806 ldr r0, [pc, #24] @ (8009648 ) 8009630: f006 f914 bl 800f85c /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8009634: bf00 nop 8009636: 3728 adds r7, #40 @ 0x28 8009638: 46bd mov sp, r7 800963a: bd80 pop {r7, pc} 800963c: 40012400 .word 0x40012400 8009640: 40021000 .word 0x40021000 8009644: 40010800 .word 0x40010800 8009648: 40010c00 .word 0x40010c00 0800964c : uint8_t RELAY_State[RELAY_COUNT]; static volatile uint8_t adc_lock = 0; static SMAFilter_t conn_temp_adc_filter[2]; void RELAY_Write(relay_t num, uint8_t state){ 800964c: b580 push {r7, lr} 800964e: b082 sub sp, #8 8009650: af00 add r7, sp, #0 8009652: 4603 mov r3, r0 8009654: 460a mov r2, r1 8009656: 71fb strb r3, [r7, #7] 8009658: 4613 mov r3, r2 800965a: 71bb strb r3, [r7, #6] switch (num) { 800965c: 79fb ldrb r3, [r7, #7] 800965e: 2b07 cmp r3, #7 8009660: d850 bhi.n 8009704 8009662: a201 add r2, pc, #4 @ (adr r2, 8009668 ) 8009664: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009668: 08009689 .word 0x08009689 800966c: 08009699 .word 0x08009699 8009670: 080096a9 .word 0x080096a9 8009674: 080096b9 .word 0x080096b9 8009678: 080096c9 .word 0x080096c9 800967c: 080096d9 .word 0x080096d9 8009680: 080096e7 .word 0x080096e7 8009684: 080096f7 .word 0x080096f7 case RELAY_AUX0: HAL_GPIO_WritePin(RELAY1_GPIO_Port, RELAY1_Pin, state); 8009688: 79bb ldrb r3, [r7, #6] 800968a: 461a mov r2, r3 800968c: f44f 7180 mov.w r1, #256 @ 0x100 8009690: 4821 ldr r0, [pc, #132] @ (8009718 ) 8009692: f006 fa7e bl 800fb92 break; 8009696: e036 b.n 8009706 case RELAY_AUX1: HAL_GPIO_WritePin(RELAY2_GPIO_Port, RELAY2_Pin, state); 8009698: 79bb ldrb r3, [r7, #6] 800969a: 461a mov r2, r3 800969c: f44f 7100 mov.w r1, #512 @ 0x200 80096a0: 481d ldr r0, [pc, #116] @ (8009718 ) 80096a2: f006 fa76 bl 800fb92 break; 80096a6: e02e b.n 8009706 case RELAY3: HAL_GPIO_WritePin(RELAY3_GPIO_Port, RELAY3_Pin, state); 80096a8: 79bb ldrb r3, [r7, #6] 80096aa: 461a mov r2, r3 80096ac: f44f 6180 mov.w r1, #1024 @ 0x400 80096b0: 4819 ldr r0, [pc, #100] @ (8009718 ) 80096b2: f006 fa6e bl 800fb92 break; 80096b6: e026 b.n 8009706 case RELAY_DC: HAL_GPIO_WritePin(RELAY4_GPIO_Port, RELAY4_Pin, state); 80096b8: 79bb ldrb r3, [r7, #6] 80096ba: 461a mov r2, r3 80096bc: f44f 6100 mov.w r1, #2048 @ 0x800 80096c0: 4815 ldr r0, [pc, #84] @ (8009718 ) 80096c2: f006 fa66 bl 800fb92 break; 80096c6: e01e b.n 8009706 case RELAY_AC: HAL_GPIO_WritePin(RELAY5_GPIO_Port, RELAY5_Pin, state); 80096c8: 79bb ldrb r3, [r7, #6] 80096ca: 461a mov r2, r3 80096cc: f44f 5180 mov.w r1, #4096 @ 0x1000 80096d0: 4811 ldr r0, [pc, #68] @ (8009718 ) 80096d2: f006 fa5e bl 800fb92 break; 80096d6: e016 b.n 8009706 case RELAY_CP: HAL_GPIO_WritePin(RELAY_CP_GPIO_Port, RELAY_CP_Pin, state); 80096d8: 79bb ldrb r3, [r7, #6] 80096da: 461a mov r2, r3 80096dc: 2108 movs r1, #8 80096de: 480f ldr r0, [pc, #60] @ (800971c ) 80096e0: f006 fa57 bl 800fb92 break; 80096e4: e00f b.n 8009706 case RELAY_CC: HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, state); 80096e6: 79bb ldrb r3, [r7, #6] 80096e8: 461a mov r2, r3 80096ea: f44f 4100 mov.w r1, #32768 @ 0x8000 80096ee: 480c ldr r0, [pc, #48] @ (8009720 ) 80096f0: f006 fa4f bl 800fb92 break; 80096f4: e007 b.n 8009706 case RELAY_DC1: HAL_GPIO_WritePin(RELAY_DC_GPIO_Port, RELAY_DC_Pin, state); 80096f6: 79bb ldrb r3, [r7, #6] 80096f8: 461a mov r2, r3 80096fa: 2108 movs r1, #8 80096fc: 4809 ldr r0, [pc, #36] @ (8009724 ) 80096fe: f006 fa48 bl 800fb92 break; 8009702: e000 b.n 8009706 default: break; 8009704: bf00 nop } RELAY_State[num] = state; 8009706: 79fb ldrb r3, [r7, #7] 8009708: 4907 ldr r1, [pc, #28] @ (8009728 ) 800970a: 79ba ldrb r2, [r7, #6] 800970c: 54ca strb r2, [r1, r3] } 800970e: bf00 nop 8009710: 3708 adds r7, #8 8009712: 46bd mov sp, r7 8009714: bd80 pop {r7, pc} 8009716: bf00 nop 8009718: 40011800 .word 0x40011800 800971c: 40011000 .word 0x40011000 8009720: 40010800 .word 0x40010800 8009724: 40011400 .word 0x40011400 8009728: 2000028c .word 0x2000028c 0800972c : uint8_t RELAY_Read(relay_t num){ 800972c: b480 push {r7} 800972e: b083 sub sp, #12 8009730: af00 add r7, sp, #0 8009732: 4603 mov r3, r0 8009734: 71fb strb r3, [r7, #7] return RELAY_State[num]; 8009736: 79fb ldrb r3, [r7, #7] 8009738: 4a03 ldr r2, [pc, #12] @ (8009748 ) 800973a: 5cd3 ldrb r3, [r2, r3] } 800973c: 4618 mov r0, r3 800973e: 370c adds r7, #12 8009740: 46bd mov sp, r7 8009742: bc80 pop {r7} 8009744: 4770 bx lr 8009746: bf00 nop 8009748: 2000028c .word 0x2000028c 0800974c : uint8_t IN_ReadInput(inputNum_t input_n){ 800974c: b580 push {r7, lr} 800974e: b082 sub sp, #8 8009750: af00 add r7, sp, #0 8009752: 4603 mov r3, r0 8009754: 71fb strb r3, [r7, #7] switch(input_n){ 8009756: 79fb ldrb r3, [r7, #7] 8009758: 2b06 cmp r3, #6 800975a: d83b bhi.n 80097d4 800975c: a201 add r2, pc, #4 @ (adr r2, 8009764 ) 800975e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009762: bf00 nop 8009764: 08009781 .word 0x08009781 8009768: 0800978d .word 0x0800978d 800976c: 08009799 .word 0x08009799 8009770: 080097a5 .word 0x080097a5 8009774: 080097b1 .word 0x080097b1 8009778: 080097bd .word 0x080097bd 800977c: 080097c9 .word 0x080097c9 case IN_SW0: return HAL_GPIO_ReadPin(IN_SW0_GPIO_Port, IN_SW0_Pin); 8009780: 2102 movs r1, #2 8009782: 4817 ldr r0, [pc, #92] @ (80097e0 ) 8009784: f006 f9ee bl 800fb64 8009788: 4603 mov r3, r0 800978a: e024 b.n 80097d6 case IN_SW1: return HAL_GPIO_ReadPin(IN_SW1_GPIO_Port, IN_SW1_Pin); 800978c: 2104 movs r1, #4 800978e: 4814 ldr r0, [pc, #80] @ (80097e0 ) 8009790: f006 f9e8 bl 800fb64 8009794: 4603 mov r3, r0 8009796: e01e b.n 80097d6 case IN0: return HAL_GPIO_ReadPin(IN0_GPIO_Port, IN0_Pin); 8009798: 2180 movs r1, #128 @ 0x80 800979a: 4812 ldr r0, [pc, #72] @ (80097e4 ) 800979c: f006 f9e2 bl 800fb64 80097a0: 4603 mov r3, r0 80097a2: e018 b.n 80097d6 case IN_ESTOP: return HAL_GPIO_ReadPin(IN_ESTOP_GPIO_Port, IN_ESTOP_Pin); 80097a4: 2180 movs r1, #128 @ 0x80 80097a6: 4810 ldr r0, [pc, #64] @ (80097e8 ) 80097a8: f006 f9dc bl 800fb64 80097ac: 4603 mov r3, r0 80097ae: e012 b.n 80097d6 case IN_FB1: return HAL_GPIO_ReadPin(IN_FB1_GPIO_Port, IN_FB1_Pin); 80097b0: 2110 movs r1, #16 80097b2: 480e ldr r0, [pc, #56] @ (80097ec ) 80097b4: f006 f9d6 bl 800fb64 80097b8: 4603 mov r3, r0 80097ba: e00c b.n 80097d6 case IN_CONT_FB_DC: return HAL_GPIO_ReadPin(IN_FB2_GPIO_Port, IN_FB2_Pin); 80097bc: 2108 movs r1, #8 80097be: 480b ldr r0, [pc, #44] @ (80097ec ) 80097c0: f006 f9d0 bl 800fb64 80097c4: 4603 mov r3, r0 80097c6: e006 b.n 80097d6 case ISO_IN: return HAL_GPIO_ReadPin(ISO_IN_GPIO_Port, ISO_IN_Pin); 80097c8: 2102 movs r1, #2 80097ca: 4806 ldr r0, [pc, #24] @ (80097e4 ) 80097cc: f006 f9ca bl 800fb64 80097d0: 4603 mov r3, r0 80097d2: e000 b.n 80097d6 default: return 0; 80097d4: 2300 movs r3, #0 } } 80097d6: 4618 mov r0, r3 80097d8: 3708 adds r7, #8 80097da: 46bd mov sp, r7 80097dc: bd80 pop {r7, pc} 80097de: bf00 nop 80097e0: 40010800 .word 0x40010800 80097e4: 40011800 .word 0x40011800 80097e8: 40011400 .word 0x40011400 80097ec: 40010c00 .word 0x40010c00 080097f0 : // // HAL_ADC_Stop(&hadc1); // stop adc return 0; } void Init_Peripheral(){ 80097f0: b580 push {r7, lr} 80097f2: af00 add r7, sp, #0 HAL_ADCEx_Calibration_Start(&hadc1); 80097f4: 4815 ldr r0, [pc, #84] @ (800984c ) 80097f6: f004 fe41 bl 800e47c RELAY_Write(RELAY_AUX0, 0); 80097fa: 2100 movs r1, #0 80097fc: 2000 movs r0, #0 80097fe: f7ff ff25 bl 800964c RELAY_Write(RELAY_AUX1, 0); 8009802: 2100 movs r1, #0 8009804: 2001 movs r0, #1 8009806: f7ff ff21 bl 800964c RELAY_Write(RELAY3, 0); 800980a: 2100 movs r1, #0 800980c: 2002 movs r0, #2 800980e: f7ff ff1d bl 800964c RELAY_Write(RELAY_DC, 0); 8009812: 2100 movs r1, #0 8009814: 2003 movs r0, #3 8009816: f7ff ff19 bl 800964c RELAY_Write(RELAY_AC, 0); 800981a: 2100 movs r1, #0 800981c: 2004 movs r0, #4 800981e: f7ff ff15 bl 800964c RELAY_Write(RELAY_CP, 1); 8009822: 2101 movs r1, #1 8009824: 2005 movs r0, #5 8009826: f7ff ff11 bl 800964c RELAY_Write(RELAY_CC, 1); 800982a: 2101 movs r1, #1 800982c: 2006 movs r0, #6 800982e: f7ff ff0d bl 800964c RELAY_Write(RELAY_DC1, 0); 8009832: 2100 movs r1, #0 8009834: 2007 movs r0, #7 8009836: f7ff ff09 bl 800964c SMAFilter_Init(&conn_temp_adc_filter[0]); 800983a: 4805 ldr r0, [pc, #20] @ (8009850 ) 800983c: f003 fba0 bl 800cf80 SMAFilter_Init(&conn_temp_adc_filter[1]); 8009840: 4804 ldr r0, [pc, #16] @ (8009854 ) 8009842: f003 fb9d bl 800cf80 } 8009846: bf00 nop 8009848: bd80 pop {r7, pc} 800984a: bf00 nop 800984c: 2000025c .word 0x2000025c 8009850: 20000298 .word 0x20000298 8009854: 200002c0 .word 0x200002c0 08009858 : float pt1000_to_temperature(float resistance) { 8009858: b590 push {r4, r7, lr} 800985a: b087 sub sp, #28 800985c: af00 add r7, sp, #0 800985e: 6078 str r0, [r7, #4] // Константы для PT1000 const float R0 = 1000.0; // Сопротивление при 0 °C 8009860: 4b0c ldr r3, [pc, #48] @ (8009894 ) 8009862: 617b str r3, [r7, #20] const float C_A = 3.9083E-3f; 8009864: 4b0c ldr r3, [pc, #48] @ (8009898 ) 8009866: 613b str r3, [r7, #16] float temperature = (resistance-R0) / ( R0 * C_A); 8009868: 6979 ldr r1, [r7, #20] 800986a: 6878 ldr r0, [r7, #4] 800986c: f7ff f9cc bl 8008c08 <__aeabi_fsub> 8009870: 4603 mov r3, r0 8009872: 461c mov r4, r3 8009874: 6939 ldr r1, [r7, #16] 8009876: 6978 ldr r0, [r7, #20] 8009878: f7ff fad0 bl 8008e1c <__aeabi_fmul> 800987c: 4603 mov r3, r0 800987e: 4619 mov r1, r3 8009880: 4620 mov r0, r4 8009882: f7ff fb7f bl 8008f84 <__aeabi_fdiv> 8009886: 4603 mov r3, r0 8009888: 60fb str r3, [r7, #12] return temperature; 800988a: 68fb ldr r3, [r7, #12] } 800988c: 4618 mov r0, r3 800988e: 371c adds r7, #28 8009890: 46bd mov sp, r7 8009892: bd90 pop {r4, r7, pc} 8009894: 447a0000 .word 0x447a0000 8009898: 3b801132 .word 0x3b801132 800989c: 00000000 .word 0x00000000 080098a0 : float calculate_NTC_resistance(int adc_value, float Vref, float Vin, float R) { 80098a0: b5b0 push {r4, r5, r7, lr} 80098a2: b086 sub sp, #24 80098a4: af00 add r7, sp, #0 80098a6: 60f8 str r0, [r7, #12] 80098a8: 60b9 str r1, [r7, #8] 80098aa: 607a str r2, [r7, #4] 80098ac: 603b str r3, [r7, #0] // Преобразуем значение АЦП в выходное напряжение float Vout = (adc_value / 4095.0) * Vref; 80098ae: 68f8 ldr r0, [r7, #12] 80098b0: f7fe fe14 bl 80084dc <__aeabi_i2d> 80098b4: a31c add r3, pc, #112 @ (adr r3, 8009928 ) 80098b6: e9d3 2300 ldrd r2, r3, [r3] 80098ba: f7fe ffa3 bl 8008804 <__aeabi_ddiv> 80098be: 4602 mov r2, r0 80098c0: 460b mov r3, r1 80098c2: 4614 mov r4, r2 80098c4: 461d mov r5, r3 80098c6: 68b8 ldr r0, [r7, #8] 80098c8: f7fe fe1a bl 8008500 <__aeabi_f2d> 80098cc: 4602 mov r2, r0 80098ce: 460b mov r3, r1 80098d0: 4620 mov r0, r4 80098d2: 4629 mov r1, r5 80098d4: f7fe fe6c bl 80085b0 <__aeabi_dmul> 80098d8: 4602 mov r2, r0 80098da: 460b mov r3, r1 80098dc: 4610 mov r0, r2 80098de: 4619 mov r1, r3 80098e0: f7ff f93e bl 8008b60 <__aeabi_d2f> 80098e4: 4603 mov r3, r0 80098e6: 617b str r3, [r7, #20] // Проверяем, чтобы Vout не было равно Vin if (Vout >= Vin) { 80098e8: 6879 ldr r1, [r7, #4] 80098ea: 6978 ldr r0, [r7, #20] 80098ec: f7ff fc48 bl 8009180 <__aeabi_fcmpge> 80098f0: 4603 mov r3, r0 80098f2: 2b00 cmp r3, #0 80098f4: d001 beq.n 80098fa return -1; // Ошибка: Vout не может быть больше или равно Vin 80098f6: 4b0e ldr r3, [pc, #56] @ (8009930 ) 80098f8: e010 b.n 800991c } // Вычисляем сопротивление термистора float R_NTC = R * (Vout / (Vin - Vout)); 80098fa: 6979 ldr r1, [r7, #20] 80098fc: 6878 ldr r0, [r7, #4] 80098fe: f7ff f983 bl 8008c08 <__aeabi_fsub> 8009902: 4603 mov r3, r0 8009904: 4619 mov r1, r3 8009906: 6978 ldr r0, [r7, #20] 8009908: f7ff fb3c bl 8008f84 <__aeabi_fdiv> 800990c: 4603 mov r3, r0 800990e: 4619 mov r1, r3 8009910: 6838 ldr r0, [r7, #0] 8009912: f7ff fa83 bl 8008e1c <__aeabi_fmul> 8009916: 4603 mov r3, r0 8009918: 613b str r3, [r7, #16] return R_NTC; 800991a: 693b ldr r3, [r7, #16] } 800991c: 4618 mov r0, r3 800991e: 3718 adds r7, #24 8009920: 46bd mov sp, r7 8009922: bdb0 pop {r4, r5, r7, pc} 8009924: f3af 8000 nop.w 8009928: 00000000 .word 0x00000000 800992c: 40affe00 .word 0x40affe00 8009930: bf800000 .word 0xbf800000 08009934 : int16_t CONN_ReadTemp(uint8_t ch){ 8009934: b580 push {r7, lr} 8009936: b088 sub sp, #32 8009938: af00 add r7, sp, #0 800993a: 4603 mov r3, r0 800993c: 71fb strb r3, [r7, #7] ADC_LockBlocking(); 800993e: f000 f89b bl 8009a78 //TODO if(ch)ADC_Select_Channel(ADC_CHANNEL_8); 8009942: 79fb ldrb r3, [r7, #7] 8009944: 2b00 cmp r3, #0 8009946: d003 beq.n 8009950 8009948: 2008 movs r0, #8 800994a: f000 f853 bl 80099f4 800994e: e002 b.n 8009956 else ADC_Select_Channel(ADC_CHANNEL_9); 8009950: 2009 movs r0, #9 8009952: f000 f84f bl 80099f4 // Начало конверсии HAL_ADC_Start(&hadc1); 8009956: 4822 ldr r0, [pc, #136] @ (80099e0 ) 8009958: f004 fa10 bl 800dd7c // Ожидание окончания конверсии HAL_ADC_PollForConversion(&hadc1, HAL_MAX_DELAY); 800995c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8009960: 481f ldr r0, [pc, #124] @ (80099e0 ) 8009962: f004 fae5 bl 800df30 // Получение значения uint32_t adcValue = HAL_ADC_GetValue(&hadc1); 8009966: 481e ldr r0, [pc, #120] @ (80099e0 ) 8009968: f004 fbe8 bl 800e13c 800996c: 61f8 str r0, [r7, #28] // Остановка АЦП (по желанию) HAL_ADC_Stop(&hadc1); 800996e: 481c ldr r0, [pc, #112] @ (80099e0 ) 8009970: f004 fab2 bl 800ded8 int32_t adc_filtered = SMAFilter_Update(&conn_temp_adc_filter[ch ? 1u : 0u], (int32_t)adcValue); 8009974: 79fb ldrb r3, [r7, #7] 8009976: 2b00 cmp r3, #0 8009978: d001 beq.n 800997e 800997a: 2201 movs r2, #1 800997c: e000 b.n 8009980 800997e: 2200 movs r2, #0 8009980: 4613 mov r3, r2 8009982: 009b lsls r3, r3, #2 8009984: 4413 add r3, r2 8009986: 00db lsls r3, r3, #3 8009988: 4a16 ldr r2, [pc, #88] @ (80099e4 ) 800998a: 4413 add r3, r2 800998c: 69fa ldr r2, [r7, #28] 800998e: 4611 mov r1, r2 8009990: 4618 mov r0, r3 8009992: f003 fb1a bl 800cfca 8009996: 61b8 str r0, [r7, #24] if((uint32_t)adc_filtered > 4000u) { 8009998: 69bb ldr r3, [r7, #24] 800999a: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800999e: d903 bls.n 80099a8 ADC_Unlock(); 80099a0: f000 f876 bl 8009a90 return 20; //Термодатчик не подключен 80099a4: 2314 movs r3, #20 80099a6: e017 b.n 80099d8 } // int adc_value = 2048; // Пример значения АЦП float Vref = 3.3; // Напряжение опорное 80099a8: 4b0f ldr r3, [pc, #60] @ (80099e8 ) 80099aa: 617b str r3, [r7, #20] float Vin = 5.0; // Входное напряжение 80099ac: 4b0f ldr r3, [pc, #60] @ (80099ec ) 80099ae: 613b str r3, [r7, #16] float R = 1000; // Сопротивление резистора в Омах 80099b0: 4b0f ldr r3, [pc, #60] @ (80099f0 ) 80099b2: 60fb str r3, [r7, #12] float temp = pt1000_to_temperature(calculate_NTC_resistance((int)adc_filtered, Vref, Vin, R)); 80099b4: 68fb ldr r3, [r7, #12] 80099b6: 693a ldr r2, [r7, #16] 80099b8: 6979 ldr r1, [r7, #20] 80099ba: 69b8 ldr r0, [r7, #24] 80099bc: f7ff ff70 bl 80098a0 80099c0: 4603 mov r3, r0 80099c2: 4618 mov r0, r3 80099c4: f7ff ff48 bl 8009858 80099c8: 60b8 str r0, [r7, #8] ADC_Unlock(); 80099ca: f000 f861 bl 8009a90 return (int16_t)temp; 80099ce: 68b8 ldr r0, [r7, #8] 80099d0: f7ff fbea bl 80091a8 <__aeabi_f2iz> 80099d4: 4603 mov r3, r0 80099d6: b21b sxth r3, r3 } 80099d8: 4618 mov r0, r3 80099da: 3720 adds r7, #32 80099dc: 46bd mov sp, r7 80099de: bd80 pop {r7, pc} 80099e0: 2000025c .word 0x2000025c 80099e4: 20000298 .word 0x20000298 80099e8: 40533333 .word 0x40533333 80099ec: 40a00000 .word 0x40a00000 80099f0: 447a0000 .word 0x447a0000 080099f4 : int16_t GBT_ReadTemp(uint8_t ch){ return CONN_ReadTemp(ch); } void ADC_Select_Channel(uint32_t ch) { 80099f4: b580 push {r7, lr} 80099f6: b086 sub sp, #24 80099f8: af00 add r7, sp, #0 80099fa: 6078 str r0, [r7, #4] ADC_ChannelConfTypeDef conf = { 80099fc: 687b ldr r3, [r7, #4] 80099fe: 60fb str r3, [r7, #12] 8009a00: 2301 movs r3, #1 8009a02: 613b str r3, [r7, #16] 8009a04: 2303 movs r3, #3 8009a06: 617b str r3, [r7, #20] .Channel = ch, .Rank = 1, .SamplingTime = ADC_SAMPLETIME_28CYCLES_5, }; if (HAL_ADC_ConfigChannel(&hadc1, &conf) != HAL_OK) { 8009a08: f107 030c add.w r3, r7, #12 8009a0c: 4619 mov r1, r3 8009a0e: 4806 ldr r0, [pc, #24] @ (8009a28 ) 8009a10: f004 fba0 bl 800e154 8009a14: 4603 mov r3, r0 8009a16: 2b00 cmp r3, #0 8009a18: d001 beq.n 8009a1e Error_Handler(); 8009a1a: f001 f8bf bl 800ab9c } } 8009a1e: bf00 nop 8009a20: 3718 adds r7, #24 8009a22: 46bd mov sp, r7 8009a24: bd80 pop {r7, pc} 8009a26: bf00 nop 8009a28: 2000025c .word 0x2000025c 08009a2c : uint8_t ADC_TryLock(void) { 8009a2c: b480 push {r7} 8009a2e: b083 sub sp, #12 8009a30: af00 add r7, sp, #0 */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8009a32: f3ef 8310 mrs r3, PRIMASK 8009a36: 603b str r3, [r7, #0] return(result); 8009a38: 683b ldr r3, [r7, #0] uint32_t primask = __get_PRIMASK(); 8009a3a: 607b str r3, [r7, #4] __ASM volatile ("cpsid i" : : : "memory"); 8009a3c: b672 cpsid i } 8009a3e: bf00 nop __disable_irq(); if (adc_lock != 0u) { 8009a40: 4b0c ldr r3, [pc, #48] @ (8009a74 ) 8009a42: 781b ldrb r3, [r3, #0] 8009a44: b2db uxtb r3, r3 8009a46: 2b00 cmp r3, #0 8009a48: d006 beq.n 8009a58 if (primask == 0u) { 8009a4a: 687b ldr r3, [r7, #4] 8009a4c: 2b00 cmp r3, #0 8009a4e: d101 bne.n 8009a54 __ASM volatile ("cpsie i" : : : "memory"); 8009a50: b662 cpsie i } 8009a52: bf00 nop __enable_irq(); } return 0u; 8009a54: 2300 movs r3, #0 8009a56: e008 b.n 8009a6a } adc_lock = 1u; 8009a58: 4b06 ldr r3, [pc, #24] @ (8009a74 ) 8009a5a: 2201 movs r2, #1 8009a5c: 701a strb r2, [r3, #0] if (primask == 0u) { 8009a5e: 687b ldr r3, [r7, #4] 8009a60: 2b00 cmp r3, #0 8009a62: d101 bne.n 8009a68 __ASM volatile ("cpsie i" : : : "memory"); 8009a64: b662 cpsie i } 8009a66: bf00 nop __enable_irq(); } return 1u; 8009a68: 2301 movs r3, #1 } 8009a6a: 4618 mov r0, r3 8009a6c: 370c adds r7, #12 8009a6e: 46bd mov sp, r7 8009a70: bc80 pop {r7} 8009a72: 4770 bx lr 8009a74: 20000294 .word 0x20000294 08009a78 : void ADC_LockBlocking(void) { 8009a78: b580 push {r7, lr} 8009a7a: af00 add r7, sp, #0 while (ADC_TryLock() == 0u) { 8009a7c: bf00 nop 8009a7e: f7ff ffd5 bl 8009a2c 8009a82: 4603 mov r3, r0 8009a84: 2b00 cmp r3, #0 8009a86: d0fa beq.n 8009a7e /* wait in main context until ADC is free */ } } 8009a88: bf00 nop 8009a8a: bf00 nop 8009a8c: bd80 pop {r7, pc} ... 08009a90 : void ADC_Unlock(void) { 8009a90: b480 push {r7} 8009a92: b083 sub sp, #12 8009a94: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8009a96: f3ef 8310 mrs r3, PRIMASK 8009a9a: 603b str r3, [r7, #0] return(result); 8009a9c: 683b ldr r3, [r7, #0] uint32_t primask = __get_PRIMASK(); 8009a9e: 607b str r3, [r7, #4] __ASM volatile ("cpsid i" : : : "memory"); 8009aa0: b672 cpsid i } 8009aa2: bf00 nop __disable_irq(); adc_lock = 0u; 8009aa4: 4b06 ldr r3, [pc, #24] @ (8009ac0 ) 8009aa6: 2200 movs r2, #0 8009aa8: 701a strb r2, [r3, #0] if (primask == 0u) { 8009aaa: 687b ldr r3, [r7, #4] 8009aac: 2b00 cmp r3, #0 8009aae: d101 bne.n 8009ab4 __ASM volatile ("cpsie i" : : : "memory"); 8009ab0: b662 cpsie i } 8009ab2: bf00 nop __enable_irq(); } } 8009ab4: bf00 nop 8009ab6: 370c adds r7, #12 8009ab8: 46bd mov sp, r7 8009aba: bc80 pop {r7} 8009abc: 4770 bx lr 8009abe: bf00 nop 8009ac0: 20000294 .word 0x20000294 08009ac4 : CAN_HandleTypeDef hcan1; CAN_HandleTypeDef hcan2; /* CAN1 init function */ void MX_CAN1_Init(void) { 8009ac4: b580 push {r7, lr} 8009ac6: af00 add r7, sp, #0 /* USER CODE END CAN1_Init 0 */ /* USER CODE BEGIN CAN1_Init 1 */ /* USER CODE END CAN1_Init 1 */ hcan1.Instance = CAN1; 8009ac8: 4b17 ldr r3, [pc, #92] @ (8009b28 ) 8009aca: 4a18 ldr r2, [pc, #96] @ (8009b2c ) 8009acc: 601a str r2, [r3, #0] hcan1.Init.Prescaler = 8; 8009ace: 4b16 ldr r3, [pc, #88] @ (8009b28 ) 8009ad0: 2208 movs r2, #8 8009ad2: 605a str r2, [r3, #4] hcan1.Init.Mode = CAN_MODE_NORMAL; 8009ad4: 4b14 ldr r3, [pc, #80] @ (8009b28 ) 8009ad6: 2200 movs r2, #0 8009ad8: 609a str r2, [r3, #8] hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; 8009ada: 4b13 ldr r3, [pc, #76] @ (8009b28 ) 8009adc: 2200 movs r2, #0 8009ade: 60da str r2, [r3, #12] hcan1.Init.TimeSeg1 = CAN_BS1_15TQ; 8009ae0: 4b11 ldr r3, [pc, #68] @ (8009b28 ) 8009ae2: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009ae6: 611a str r2, [r3, #16] hcan1.Init.TimeSeg2 = CAN_BS2_2TQ; 8009ae8: 4b0f ldr r3, [pc, #60] @ (8009b28 ) 8009aea: f44f 1280 mov.w r2, #1048576 @ 0x100000 8009aee: 615a str r2, [r3, #20] hcan1.Init.TimeTriggeredMode = DISABLE; 8009af0: 4b0d ldr r3, [pc, #52] @ (8009b28 ) 8009af2: 2200 movs r2, #0 8009af4: 761a strb r2, [r3, #24] hcan1.Init.AutoBusOff = ENABLE; 8009af6: 4b0c ldr r3, [pc, #48] @ (8009b28 ) 8009af8: 2201 movs r2, #1 8009afa: 765a strb r2, [r3, #25] hcan1.Init.AutoWakeUp = ENABLE; 8009afc: 4b0a ldr r3, [pc, #40] @ (8009b28 ) 8009afe: 2201 movs r2, #1 8009b00: 769a strb r2, [r3, #26] hcan1.Init.AutoRetransmission = ENABLE; 8009b02: 4b09 ldr r3, [pc, #36] @ (8009b28 ) 8009b04: 2201 movs r2, #1 8009b06: 76da strb r2, [r3, #27] hcan1.Init.ReceiveFifoLocked = DISABLE; 8009b08: 4b07 ldr r3, [pc, #28] @ (8009b28 ) 8009b0a: 2200 movs r2, #0 8009b0c: 771a strb r2, [r3, #28] hcan1.Init.TransmitFifoPriority = ENABLE; 8009b0e: 4b06 ldr r3, [pc, #24] @ (8009b28 ) 8009b10: 2201 movs r2, #1 8009b12: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan1) != HAL_OK) 8009b14: 4804 ldr r0, [pc, #16] @ (8009b28 ) 8009b16: f004 fd5f bl 800e5d8 8009b1a: 4603 mov r3, r0 8009b1c: 2b00 cmp r3, #0 8009b1e: d001 beq.n 8009b24 { Error_Handler(); 8009b20: f001 f83c bl 800ab9c } /* USER CODE BEGIN CAN1_Init 2 */ /* USER CODE END CAN1_Init 2 */ } 8009b24: bf00 nop 8009b26: bd80 pop {r7, pc} 8009b28: 200002e8 .word 0x200002e8 8009b2c: 40006400 .word 0x40006400 08009b30 : /* CAN2 init function */ void MX_CAN2_Init(void) { 8009b30: b580 push {r7, lr} 8009b32: af00 add r7, sp, #0 /* USER CODE END CAN2_Init 0 */ /* USER CODE BEGIN CAN2_Init 1 */ /* USER CODE END CAN2_Init 1 */ hcan2.Instance = CAN2; 8009b34: 4b17 ldr r3, [pc, #92] @ (8009b94 ) 8009b36: 4a18 ldr r2, [pc, #96] @ (8009b98 ) 8009b38: 601a str r2, [r3, #0] hcan2.Init.Prescaler = 16; 8009b3a: 4b16 ldr r3, [pc, #88] @ (8009b94 ) 8009b3c: 2210 movs r2, #16 8009b3e: 605a str r2, [r3, #4] hcan2.Init.Mode = CAN_MODE_NORMAL; 8009b40: 4b14 ldr r3, [pc, #80] @ (8009b94 ) 8009b42: 2200 movs r2, #0 8009b44: 609a str r2, [r3, #8] hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; 8009b46: 4b13 ldr r3, [pc, #76] @ (8009b94 ) 8009b48: 2200 movs r2, #0 8009b4a: 60da str r2, [r3, #12] hcan2.Init.TimeSeg1 = CAN_BS1_15TQ; 8009b4c: 4b11 ldr r3, [pc, #68] @ (8009b94 ) 8009b4e: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009b52: 611a str r2, [r3, #16] hcan2.Init.TimeSeg2 = CAN_BS2_2TQ; 8009b54: 4b0f ldr r3, [pc, #60] @ (8009b94 ) 8009b56: f44f 1280 mov.w r2, #1048576 @ 0x100000 8009b5a: 615a str r2, [r3, #20] hcan2.Init.TimeTriggeredMode = DISABLE; 8009b5c: 4b0d ldr r3, [pc, #52] @ (8009b94 ) 8009b5e: 2200 movs r2, #0 8009b60: 761a strb r2, [r3, #24] hcan2.Init.AutoBusOff = ENABLE; 8009b62: 4b0c ldr r3, [pc, #48] @ (8009b94 ) 8009b64: 2201 movs r2, #1 8009b66: 765a strb r2, [r3, #25] hcan2.Init.AutoWakeUp = ENABLE; 8009b68: 4b0a ldr r3, [pc, #40] @ (8009b94 ) 8009b6a: 2201 movs r2, #1 8009b6c: 769a strb r2, [r3, #26] hcan2.Init.AutoRetransmission = ENABLE; 8009b6e: 4b09 ldr r3, [pc, #36] @ (8009b94 ) 8009b70: 2201 movs r2, #1 8009b72: 76da strb r2, [r3, #27] hcan2.Init.ReceiveFifoLocked = DISABLE; 8009b74: 4b07 ldr r3, [pc, #28] @ (8009b94 ) 8009b76: 2200 movs r2, #0 8009b78: 771a strb r2, [r3, #28] hcan2.Init.TransmitFifoPriority = ENABLE; 8009b7a: 4b06 ldr r3, [pc, #24] @ (8009b94 ) 8009b7c: 2201 movs r2, #1 8009b7e: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan2) != HAL_OK) 8009b80: 4804 ldr r0, [pc, #16] @ (8009b94 ) 8009b82: f004 fd29 bl 800e5d8 8009b86: 4603 mov r3, r0 8009b88: 2b00 cmp r3, #0 8009b8a: d001 beq.n 8009b90 { Error_Handler(); 8009b8c: f001 f806 bl 800ab9c } /* USER CODE BEGIN CAN2_Init 2 */ /* USER CODE END CAN2_Init 2 */ } 8009b90: bf00 nop 8009b92: bd80 pop {r7, pc} 8009b94: 20000310 .word 0x20000310 8009b98: 40006800 .word 0x40006800 08009b9c : static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0; void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) { 8009b9c: b580 push {r7, lr} 8009b9e: b08e sub sp, #56 @ 0x38 8009ba0: af00 add r7, sp, #0 8009ba2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8009ba4: f107 0320 add.w r3, r7, #32 8009ba8: 2200 movs r2, #0 8009baa: 601a str r2, [r3, #0] 8009bac: 605a str r2, [r3, #4] 8009bae: 609a str r2, [r3, #8] 8009bb0: 60da str r2, [r3, #12] if(canHandle->Instance==CAN1) 8009bb2: 687b ldr r3, [r7, #4] 8009bb4: 681b ldr r3, [r3, #0] 8009bb6: 4a61 ldr r2, [pc, #388] @ (8009d3c ) 8009bb8: 4293 cmp r3, r2 8009bba: d153 bne.n 8009c64 { /* USER CODE BEGIN CAN1_MspInit 0 */ /* USER CODE END CAN1_MspInit 0 */ /* CAN1 clock enable */ HAL_RCC_CAN1_CLK_ENABLED++; 8009bbc: 4b60 ldr r3, [pc, #384] @ (8009d40 ) 8009bbe: 681b ldr r3, [r3, #0] 8009bc0: 3301 adds r3, #1 8009bc2: 4a5f ldr r2, [pc, #380] @ (8009d40 ) 8009bc4: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009bc6: 4b5e ldr r3, [pc, #376] @ (8009d40 ) 8009bc8: 681b ldr r3, [r3, #0] 8009bca: 2b01 cmp r3, #1 8009bcc: d10b bne.n 8009be6 __HAL_RCC_CAN1_CLK_ENABLE(); 8009bce: 4b5d ldr r3, [pc, #372] @ (8009d44 ) 8009bd0: 69db ldr r3, [r3, #28] 8009bd2: 4a5c ldr r2, [pc, #368] @ (8009d44 ) 8009bd4: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009bd8: 61d3 str r3, [r2, #28] 8009bda: 4b5a ldr r3, [pc, #360] @ (8009d44 ) 8009bdc: 69db ldr r3, [r3, #28] 8009bde: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009be2: 61fb str r3, [r7, #28] 8009be4: 69fb ldr r3, [r7, #28] } __HAL_RCC_GPIOD_CLK_ENABLE(); 8009be6: 4b57 ldr r3, [pc, #348] @ (8009d44 ) 8009be8: 699b ldr r3, [r3, #24] 8009bea: 4a56 ldr r2, [pc, #344] @ (8009d44 ) 8009bec: f043 0320 orr.w r3, r3, #32 8009bf0: 6193 str r3, [r2, #24] 8009bf2: 4b54 ldr r3, [pc, #336] @ (8009d44 ) 8009bf4: 699b ldr r3, [r3, #24] 8009bf6: f003 0320 and.w r3, r3, #32 8009bfa: 61bb str r3, [r7, #24] 8009bfc: 69bb ldr r3, [r7, #24] /**CAN1 GPIO Configuration PD0 ------> CAN1_RX PD1 ------> CAN1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0; 8009bfe: 2301 movs r3, #1 8009c00: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009c02: 2300 movs r3, #0 8009c04: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009c06: 2300 movs r3, #0 8009c08: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009c0a: f107 0320 add.w r3, r7, #32 8009c0e: 4619 mov r1, r3 8009c10: 484d ldr r0, [pc, #308] @ (8009d48 ) 8009c12: f005 fe23 bl 800f85c GPIO_InitStruct.Pin = GPIO_PIN_1; 8009c16: 2302 movs r3, #2 8009c18: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009c1a: 2302 movs r3, #2 8009c1c: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009c1e: 2303 movs r3, #3 8009c20: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009c22: f107 0320 add.w r3, r7, #32 8009c26: 4619 mov r1, r3 8009c28: 4847 ldr r0, [pc, #284] @ (8009d48 ) 8009c2a: f005 fe17 bl 800f85c __HAL_AFIO_REMAP_CAN1_3(); 8009c2e: 4b47 ldr r3, [pc, #284] @ (8009d4c ) 8009c30: 685b ldr r3, [r3, #4] 8009c32: 633b str r3, [r7, #48] @ 0x30 8009c34: 6b3b ldr r3, [r7, #48] @ 0x30 8009c36: f423 43c0 bic.w r3, r3, #24576 @ 0x6000 8009c3a: 633b str r3, [r7, #48] @ 0x30 8009c3c: 6b3b ldr r3, [r7, #48] @ 0x30 8009c3e: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009c42: 633b str r3, [r7, #48] @ 0x30 8009c44: 6b3b ldr r3, [r7, #48] @ 0x30 8009c46: f443 43c0 orr.w r3, r3, #24576 @ 0x6000 8009c4a: 633b str r3, [r7, #48] @ 0x30 8009c4c: 4a3f ldr r2, [pc, #252] @ (8009d4c ) 8009c4e: 6b3b ldr r3, [r7, #48] @ 0x30 8009c50: 6053 str r3, [r2, #4] /* CAN1 interrupt Init */ HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0); 8009c52: 2200 movs r2, #0 8009c54: 2100 movs r1, #0 8009c56: 2014 movs r0, #20 8009c58: f005 fc6b bl 800f532 HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn); 8009c5c: 2014 movs r0, #20 8009c5e: f005 fc84 bl 800f56a HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); /* USER CODE BEGIN CAN2_MspInit 1 */ /* USER CODE END CAN2_MspInit 1 */ } } 8009c62: e067 b.n 8009d34 else if(canHandle->Instance==CAN2) 8009c64: 687b ldr r3, [r7, #4] 8009c66: 681b ldr r3, [r3, #0] 8009c68: 4a39 ldr r2, [pc, #228] @ (8009d50 ) 8009c6a: 4293 cmp r3, r2 8009c6c: d162 bne.n 8009d34 __HAL_RCC_CAN2_CLK_ENABLE(); 8009c6e: 4b35 ldr r3, [pc, #212] @ (8009d44 ) 8009c70: 69db ldr r3, [r3, #28] 8009c72: 4a34 ldr r2, [pc, #208] @ (8009d44 ) 8009c74: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 8009c78: 61d3 str r3, [r2, #28] 8009c7a: 4b32 ldr r3, [pc, #200] @ (8009d44 ) 8009c7c: 69db ldr r3, [r3, #28] 8009c7e: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8009c82: 617b str r3, [r7, #20] 8009c84: 697b ldr r3, [r7, #20] HAL_RCC_CAN1_CLK_ENABLED++; 8009c86: 4b2e ldr r3, [pc, #184] @ (8009d40 ) 8009c88: 681b ldr r3, [r3, #0] 8009c8a: 3301 adds r3, #1 8009c8c: 4a2c ldr r2, [pc, #176] @ (8009d40 ) 8009c8e: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009c90: 4b2b ldr r3, [pc, #172] @ (8009d40 ) 8009c92: 681b ldr r3, [r3, #0] 8009c94: 2b01 cmp r3, #1 8009c96: d10b bne.n 8009cb0 __HAL_RCC_CAN1_CLK_ENABLE(); 8009c98: 4b2a ldr r3, [pc, #168] @ (8009d44 ) 8009c9a: 69db ldr r3, [r3, #28] 8009c9c: 4a29 ldr r2, [pc, #164] @ (8009d44 ) 8009c9e: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009ca2: 61d3 str r3, [r2, #28] 8009ca4: 4b27 ldr r3, [pc, #156] @ (8009d44 ) 8009ca6: 69db ldr r3, [r3, #28] 8009ca8: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009cac: 613b str r3, [r7, #16] 8009cae: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8009cb0: 4b24 ldr r3, [pc, #144] @ (8009d44 ) 8009cb2: 699b ldr r3, [r3, #24] 8009cb4: 4a23 ldr r2, [pc, #140] @ (8009d44 ) 8009cb6: f043 0308 orr.w r3, r3, #8 8009cba: 6193 str r3, [r2, #24] 8009cbc: 4b21 ldr r3, [pc, #132] @ (8009d44 ) 8009cbe: 699b ldr r3, [r3, #24] 8009cc0: f003 0308 and.w r3, r3, #8 8009cc4: 60fb str r3, [r7, #12] 8009cc6: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_5; 8009cc8: 2320 movs r3, #32 8009cca: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009ccc: 2300 movs r3, #0 8009cce: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009cd0: 2300 movs r3, #0 8009cd2: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009cd4: f107 0320 add.w r3, r7, #32 8009cd8: 4619 mov r1, r3 8009cda: 481e ldr r0, [pc, #120] @ (8009d54 ) 8009cdc: f005 fdbe bl 800f85c GPIO_InitStruct.Pin = GPIO_PIN_6; 8009ce0: 2340 movs r3, #64 @ 0x40 8009ce2: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009ce4: 2302 movs r3, #2 8009ce6: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009ce8: 2303 movs r3, #3 8009cea: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009cec: f107 0320 add.w r3, r7, #32 8009cf0: 4619 mov r1, r3 8009cf2: 4818 ldr r0, [pc, #96] @ (8009d54 ) 8009cf4: f005 fdb2 bl 800f85c __HAL_AFIO_REMAP_CAN2_ENABLE(); 8009cf8: 4b14 ldr r3, [pc, #80] @ (8009d4c ) 8009cfa: 685b ldr r3, [r3, #4] 8009cfc: 637b str r3, [r7, #52] @ 0x34 8009cfe: 6b7b ldr r3, [r7, #52] @ 0x34 8009d00: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009d04: 637b str r3, [r7, #52] @ 0x34 8009d06: 6b7b ldr r3, [r7, #52] @ 0x34 8009d08: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8009d0c: 637b str r3, [r7, #52] @ 0x34 8009d0e: 4a0f ldr r2, [pc, #60] @ (8009d4c ) 8009d10: 6b7b ldr r3, [r7, #52] @ 0x34 8009d12: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(CAN2_TX_IRQn, 0, 0); 8009d14: 2200 movs r2, #0 8009d16: 2100 movs r1, #0 8009d18: 203f movs r0, #63 @ 0x3f 8009d1a: f005 fc0a bl 800f532 HAL_NVIC_EnableIRQ(CAN2_TX_IRQn); 8009d1e: 203f movs r0, #63 @ 0x3f 8009d20: f005 fc23 bl 800f56a HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 0, 0); 8009d24: 2200 movs r2, #0 8009d26: 2100 movs r1, #0 8009d28: 2041 movs r0, #65 @ 0x41 8009d2a: f005 fc02 bl 800f532 HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); 8009d2e: 2041 movs r0, #65 @ 0x41 8009d30: f005 fc1b bl 800f56a } 8009d34: bf00 nop 8009d36: 3738 adds r7, #56 @ 0x38 8009d38: 46bd mov sp, r7 8009d3a: bd80 pop {r7, pc} 8009d3c: 40006400 .word 0x40006400 8009d40: 20000338 .word 0x20000338 8009d44: 40021000 .word 0x40021000 8009d48: 40011400 .word 0x40011400 8009d4c: 40010000 .word 0x40010000 8009d50: 40006800 .word 0x40006800 8009d54: 40010c00 .word 0x40010c00 08009d58 : ChargingConnector_t CONN; CONN_State_t connectorState; extern uint8_t config_initialized; void CONN_Init(){ 8009d58: b480 push {r7} 8009d5a: af00 add r7, sp, #0 CONN.connControl = CMD_NONE; 8009d5c: 4b08 ldr r3, [pc, #32] @ (8009d80 ) 8009d5e: 2200 movs r2, #0 8009d60: 701a strb r2, [r3, #0] CONN.connState = Unknown; 8009d62: 4b07 ldr r3, [pc, #28] @ (8009d80 ) 8009d64: 2200 movs r2, #0 8009d66: 705a strb r2, [r3, #1] CONN.RequestedVoltage = PSU_MIN_VOLTAGE; 8009d68: 4b05 ldr r3, [pc, #20] @ (8009d80 ) 8009d6a: 2200 movs r2, #0 8009d6c: f062 0269 orn r2, r2, #105 @ 0x69 8009d70: 73da strb r2, [r3, #15] 8009d72: 2200 movs r2, #0 8009d74: 741a strb r2, [r3, #16] } 8009d76: bf00 nop 8009d78: 46bd mov sp, r7 8009d7a: bc80 pop {r7} 8009d7c: 4770 bx lr 8009d7e: bf00 nop 8009d80: 2000033c .word 0x2000033c 08009d84 : void CONN_Loop(){ 8009d84: b580 push {r7, lr} 8009d86: af00 add r7, sp, #0 static CONN_State_t last_connState = Unknown; if(last_connState != CONN.connState){ 8009d88: 4b1a ldr r3, [pc, #104] @ (8009df4 ) 8009d8a: 785a ldrb r2, [r3, #1] 8009d8c: 4b1a ldr r3, [pc, #104] @ (8009df8 ) 8009d8e: 781b ldrb r3, [r3, #0] 8009d90: 429a cmp r2, r3 8009d92: d006 beq.n 8009da2 last_connState = CONN.connState; 8009d94: 4b17 ldr r3, [pc, #92] @ (8009df4 ) 8009d96: 785a ldrb r2, [r3, #1] 8009d98: 4b17 ldr r3, [pc, #92] @ (8009df8 ) 8009d9a: 701a strb r2, [r3, #0] CONN.connControl = CMD_NONE; 8009d9c: 4b15 ldr r3, [pc, #84] @ (8009df4 ) 8009d9e: 2200 movs r2, #0 8009da0: 701a strb r2, [r3, #0] } if(PSU0.cont_fault){ 8009da2: 4b16 ldr r3, [pc, #88] @ (8009dfc ) 8009da4: 7b1b ldrb r3, [r3, #12] 8009da6: 2b00 cmp r3, #0 8009da8: d003 beq.n 8009db2 CONN.chargingError = CONN_ERR_CONTACTOR; 8009daa: 4b12 ldr r3, [pc, #72] @ (8009df4 ) 8009dac: 2207 movs r2, #7 8009dae: 775a strb r2, [r3, #29] 8009db0: e00e b.n 8009dd0 } else if(PSU0.psu_fault){ 8009db2: 4b12 ldr r3, [pc, #72] @ (8009dfc ) 8009db4: 7b5b ldrb r3, [r3, #13] 8009db6: 2b00 cmp r3, #0 8009db8: d003 beq.n 8009dc2 CONN.chargingError = CONN_ERR_PSU_FAULT; 8009dba: 4b0e ldr r3, [pc, #56] @ (8009df4 ) 8009dbc: 220a movs r2, #10 8009dbe: 775a strb r2, [r3, #29] 8009dc0: e006 b.n 8009dd0 // } else if(!CTRL.ac_ok) { // CONN.chargingError = CONN_ERR_AC_FAULT; // } else }else if (CONN.EvConnected == 0){ 8009dc2: 4b0c ldr r3, [pc, #48] @ (8009df4 ) 8009dc4: 7f9b ldrb r3, [r3, #30] 8009dc6: 2b00 cmp r3, #0 8009dc8: d102 bne.n 8009dd0 CONN.chargingError = CONN_NO_ERROR; 8009dca: 4b0a ldr r3, [pc, #40] @ (8009df4 ) 8009dcc: 2200 movs r2, #0 8009dce: 775a strb r2, [r3, #29] } if(ED_TraceWarning(CONN.chargingError, 0)) printf("CONN%d Error: %d\n", 0, CONN.chargingError); 8009dd0: 4b08 ldr r3, [pc, #32] @ (8009df4 ) 8009dd2: 7f5b ldrb r3, [r3, #29] 8009dd4: 2100 movs r1, #0 8009dd6: 4618 mov r0, r3 8009dd8: f000 fd78 bl 800a8cc 8009ddc: 4603 mov r3, r0 8009dde: 2b00 cmp r3, #0 8009de0: d006 beq.n 8009df0 8009de2: 4b04 ldr r3, [pc, #16] @ (8009df4 ) 8009de4: 7f5b ldrb r3, [r3, #29] 8009de6: 461a mov r2, r3 8009de8: 2100 movs r1, #0 8009dea: 4805 ldr r0, [pc, #20] @ (8009e00 ) 8009dec: f009 fe36 bl 8013a5c } 8009df0: bf00 nop 8009df2: bd80 pop {r7, pc} 8009df4: 2000033c .word 0x2000033c 8009df8: 2000035c .word 0x2000035c 8009dfc: 2000088c .word 0x2000088c 8009e00: 08015cd0 .word 0x08015cd0 08009e04 : void CONN_Task(){ 8009e04: b580 push {r7, lr} 8009e06: af00 add r7, sp, #0 /* CCS state machine is handled in serial.c. * Keep this task lightweight for scheduler compatibility. */ if (CONN.chargingError != CONN_NO_ERROR) { 8009e08: 4b0f ldr r3, [pc, #60] @ (8009e48 ) 8009e0a: 7f5b ldrb r3, [r3, #29] 8009e0c: 2b00 cmp r3, #0 8009e0e: d003 beq.n 8009e18 CONN_SetState(Disabled); 8009e10: 2002 movs r0, #2 8009e12: f000 f81f bl 8009e54 return; 8009e16: e016 b.n 8009e46 } if (connectorState == Unknown && config_initialized) { 8009e18: 4b0c ldr r3, [pc, #48] @ (8009e4c ) 8009e1a: 781b ldrb r3, [r3, #0] 8009e1c: 2b00 cmp r3, #0 8009e1e: d107 bne.n 8009e30 8009e20: 4b0b ldr r3, [pc, #44] @ (8009e50 ) 8009e22: 781b ldrb r3, [r3, #0] 8009e24: 2b00 cmp r3, #0 8009e26: d003 beq.n 8009e30 CONN_SetState(Unplugged); 8009e28: 2001 movs r0, #1 8009e2a: f000 f813 bl 8009e54 8009e2e: e00a b.n 8009e46 } else if (connectorState == Disabled && CONN.chargingError == CONN_NO_ERROR) { 8009e30: 4b06 ldr r3, [pc, #24] @ (8009e4c ) 8009e32: 781b ldrb r3, [r3, #0] 8009e34: 2b02 cmp r3, #2 8009e36: d106 bne.n 8009e46 8009e38: 4b03 ldr r3, [pc, #12] @ (8009e48 ) 8009e3a: 7f5b ldrb r3, [r3, #29] 8009e3c: 2b00 cmp r3, #0 8009e3e: d102 bne.n 8009e46 CONN_SetState(Unplugged); 8009e40: 2001 movs r0, #1 8009e42: f000 f807 bl 8009e54 } } 8009e46: bd80 pop {r7, pc} 8009e48: 2000033c .word 0x2000033c 8009e4c: 2000035b .word 0x2000035b 8009e50: 20001026 .word 0x20001026 08009e54 : void CONN_SetState(CONN_State_t state){ 8009e54: b580 push {r7, lr} 8009e56: b082 sub sp, #8 8009e58: af00 add r7, sp, #0 8009e5a: 4603 mov r3, r0 8009e5c: 71fb strb r3, [r7, #7] if (connectorState == state) { 8009e5e: 4b41 ldr r3, [pc, #260] @ (8009f64 ) 8009e60: 781b ldrb r3, [r3, #0] 8009e62: 79fa ldrb r2, [r7, #7] 8009e64: 429a cmp r2, r3 8009e66: d103 bne.n 8009e70 CONN.connState = state; 8009e68: 4a3f ldr r2, [pc, #252] @ (8009f68 ) 8009e6a: 79fb ldrb r3, [r7, #7] 8009e6c: 7053 strb r3, [r2, #1] return; 8009e6e: e075 b.n 8009f5c } connectorState = state; 8009e70: 4a3c ldr r2, [pc, #240] @ (8009f64 ) 8009e72: 79fb ldrb r3, [r7, #7] 8009e74: 7013 strb r3, [r2, #0] if(connectorState == Unknown) log_printf(LOG_INFO, "Connector: Unknown\n"); 8009e76: 4b3b ldr r3, [pc, #236] @ (8009f64 ) 8009e78: 781b ldrb r3, [r3, #0] 8009e7a: 2b00 cmp r3, #0 8009e7c: d103 bne.n 8009e86 8009e7e: 493b ldr r1, [pc, #236] @ (8009f6c ) 8009e80: 2007 movs r0, #7 8009e82: f000 fbcb bl 800a61c if(connectorState == Unplugged) log_printf(LOG_INFO, "Connector: Unplugged\n"); 8009e86: 4b37 ldr r3, [pc, #220] @ (8009f64 ) 8009e88: 781b ldrb r3, [r3, #0] 8009e8a: 2b01 cmp r3, #1 8009e8c: d103 bne.n 8009e96 8009e8e: 4938 ldr r1, [pc, #224] @ (8009f70 ) 8009e90: 2007 movs r0, #7 8009e92: f000 fbc3 bl 800a61c if(connectorState == Disabled) log_printf(LOG_INFO, "Connector: Disabled\n"); 8009e96: 4b33 ldr r3, [pc, #204] @ (8009f64 ) 8009e98: 781b ldrb r3, [r3, #0] 8009e9a: 2b02 cmp r3, #2 8009e9c: d103 bne.n 8009ea6 8009e9e: 4935 ldr r1, [pc, #212] @ (8009f74 ) 8009ea0: 2007 movs r0, #7 8009ea2: f000 fbbb bl 800a61c if(connectorState == Preparing) log_printf(LOG_INFO, "Connector: Preparing\n"); 8009ea6: 4b2f ldr r3, [pc, #188] @ (8009f64 ) 8009ea8: 781b ldrb r3, [r3, #0] 8009eaa: 2b03 cmp r3, #3 8009eac: d103 bne.n 8009eb6 8009eae: 4932 ldr r1, [pc, #200] @ (8009f78 ) 8009eb0: 2007 movs r0, #7 8009eb2: f000 fbb3 bl 800a61c if(connectorState == AuthRequired) log_printf(LOG_INFO, "Connector: AuthRequired\n"); 8009eb6: 4b2b ldr r3, [pc, #172] @ (8009f64 ) 8009eb8: 781b ldrb r3, [r3, #0] 8009eba: 2b04 cmp r3, #4 8009ebc: d103 bne.n 8009ec6 8009ebe: 492f ldr r1, [pc, #188] @ (8009f7c ) 8009ec0: 2007 movs r0, #7 8009ec2: f000 fbab bl 800a61c if(connectorState == WaitingForEnergy) log_printf(LOG_INFO, "Connector: WaitingForEnergy\n"); 8009ec6: 4b27 ldr r3, [pc, #156] @ (8009f64 ) 8009ec8: 781b ldrb r3, [r3, #0] 8009eca: 2b05 cmp r3, #5 8009ecc: d103 bne.n 8009ed6 8009ece: 492c ldr r1, [pc, #176] @ (8009f80 ) 8009ed0: 2007 movs r0, #7 8009ed2: f000 fba3 bl 800a61c if(connectorState == ChargingPausedEV) log_printf(LOG_INFO, "Connector: ChargingPausedEV\n"); 8009ed6: 4b23 ldr r3, [pc, #140] @ (8009f64 ) 8009ed8: 781b ldrb r3, [r3, #0] 8009eda: 2b06 cmp r3, #6 8009edc: d103 bne.n 8009ee6 8009ede: 4929 ldr r1, [pc, #164] @ (8009f84 ) 8009ee0: 2007 movs r0, #7 8009ee2: f000 fb9b bl 800a61c if(connectorState == ChargingPausedEVSE) log_printf(LOG_INFO, "Connector: ChargingPausedEVSE\n"); 8009ee6: 4b1f ldr r3, [pc, #124] @ (8009f64 ) 8009ee8: 781b ldrb r3, [r3, #0] 8009eea: 2b07 cmp r3, #7 8009eec: d103 bne.n 8009ef6 8009eee: 4926 ldr r1, [pc, #152] @ (8009f88 ) 8009ef0: 2007 movs r0, #7 8009ef2: f000 fb93 bl 800a61c if(connectorState == Charging) log_printf(LOG_INFO, "Connector: Charging\n"); 8009ef6: 4b1b ldr r3, [pc, #108] @ (8009f64 ) 8009ef8: 781b ldrb r3, [r3, #0] 8009efa: 2b08 cmp r3, #8 8009efc: d103 bne.n 8009f06 8009efe: 4923 ldr r1, [pc, #140] @ (8009f8c ) 8009f00: 2007 movs r0, #7 8009f02: f000 fb8b bl 800a61c if(connectorState == AuthTimeout) log_printf(LOG_INFO, "Connector: AuthTimeout\n"); 8009f06: 4b17 ldr r3, [pc, #92] @ (8009f64 ) 8009f08: 781b ldrb r3, [r3, #0] 8009f0a: 2b09 cmp r3, #9 8009f0c: d103 bne.n 8009f16 8009f0e: 4920 ldr r1, [pc, #128] @ (8009f90 ) 8009f10: 2007 movs r0, #7 8009f12: f000 fb83 bl 800a61c if(connectorState == Finished) log_printf(LOG_INFO, "Connector: Finished\n"); 8009f16: 4b13 ldr r3, [pc, #76] @ (8009f64 ) 8009f18: 781b ldrb r3, [r3, #0] 8009f1a: 2b0a cmp r3, #10 8009f1c: d103 bne.n 8009f26 8009f1e: 491d ldr r1, [pc, #116] @ (8009f94 ) 8009f20: 2007 movs r0, #7 8009f22: f000 fb7b bl 800a61c if(connectorState == FinishedEVSE) log_printf(LOG_INFO, "Connector: FinishedEVSE\n"); 8009f26: 4b0f ldr r3, [pc, #60] @ (8009f64 ) 8009f28: 781b ldrb r3, [r3, #0] 8009f2a: 2b0b cmp r3, #11 8009f2c: d103 bne.n 8009f36 8009f2e: 491a ldr r1, [pc, #104] @ (8009f98 ) 8009f30: 2007 movs r0, #7 8009f32: f000 fb73 bl 800a61c if(connectorState == FinishedEV) log_printf(LOG_INFO, "Connector: FinishedEV\n"); 8009f36: 4b0b ldr r3, [pc, #44] @ (8009f64 ) 8009f38: 781b ldrb r3, [r3, #0] 8009f3a: 2b0c cmp r3, #12 8009f3c: d103 bne.n 8009f46 8009f3e: 4917 ldr r1, [pc, #92] @ (8009f9c ) 8009f40: 2007 movs r0, #7 8009f42: f000 fb6b bl 800a61c if(connectorState == Replugging) log_printf(LOG_INFO, "Connector: Replugging\n"); 8009f46: 4b07 ldr r3, [pc, #28] @ (8009f64 ) 8009f48: 781b ldrb r3, [r3, #0] 8009f4a: 2b0d cmp r3, #13 8009f4c: d103 bne.n 8009f56 8009f4e: 4914 ldr r1, [pc, #80] @ (8009fa0 ) 8009f50: 2007 movs r0, #7 8009f52: f000 fb63 bl 800a61c CONN.connState = state; 8009f56: 4a04 ldr r2, [pc, #16] @ (8009f68 ) 8009f58: 79fb ldrb r3, [r7, #7] 8009f5a: 7053 strb r3, [r2, #1] } 8009f5c: 3708 adds r7, #8 8009f5e: 46bd mov sp, r7 8009f60: bd80 pop {r7, pc} 8009f62: bf00 nop 8009f64: 2000035b .word 0x2000035b 8009f68: 2000033c .word 0x2000033c 8009f6c: 08015ce4 .word 0x08015ce4 8009f70: 08015cf8 .word 0x08015cf8 8009f74: 08015d10 .word 0x08015d10 8009f78: 08015d28 .word 0x08015d28 8009f7c: 08015d40 .word 0x08015d40 8009f80: 08015d5c .word 0x08015d5c 8009f84: 08015d7c .word 0x08015d7c 8009f88: 08015d9c .word 0x08015d9c 8009f8c: 08015dbc .word 0x08015dbc 8009f90: 08015dd4 .word 0x08015dd4 8009f94: 08015dec .word 0x08015dec 8009f98: 08015e04 .word 0x08015e04 8009f9c: 08015e20 .word 0x08015e20 8009fa0: 08015e38 .word 0x08015e38 08009fa4 : CP_State_t fake_cp_state = EV_STATE_ACQUIRING; static CP_State_t cp_stable_state = EV_STATE_ACQUIRING; static CP_State_t cp_candidate_state = EV_STATE_ACQUIRING; static uint32_t cp_candidate_since_ms = 0; static uint32_t CP_ReadAdcChannel(uint32_t ch) { 8009fa4: b580 push {r7, lr} 8009fa6: b084 sub sp, #16 8009fa8: af00 add r7, sp, #0 8009faa: 6078 str r0, [r7, #4] uint32_t adc = 0; 8009fac: 2300 movs r3, #0 8009fae: 60fb str r3, [r7, #12] ADC_Select_Channel(ch); 8009fb0: 6878 ldr r0, [r7, #4] 8009fb2: f7ff fd1f bl 80099f4 HAL_ADC_Start(&hadc1); 8009fb6: 4809 ldr r0, [pc, #36] @ (8009fdc ) 8009fb8: f003 fee0 bl 800dd7c HAL_ADC_PollForConversion(&hadc1, 10); 8009fbc: 210a movs r1, #10 8009fbe: 4807 ldr r0, [pc, #28] @ (8009fdc ) 8009fc0: f003 ffb6 bl 800df30 adc = HAL_ADC_GetValue(&hadc1); 8009fc4: 4805 ldr r0, [pc, #20] @ (8009fdc ) 8009fc6: f004 f8b9 bl 800e13c 8009fca: 60f8 str r0, [r7, #12] HAL_ADC_Stop(&hadc1); 8009fcc: 4803 ldr r0, [pc, #12] @ (8009fdc ) 8009fce: f003 ff83 bl 800ded8 return adc; 8009fd2: 68fb ldr r3, [r7, #12] } 8009fd4: 4618 mov r0, r3 8009fd6: 3710 adds r7, #16 8009fd8: 46bd mov sp, r7 8009fda: bd80 pop {r7, pc} 8009fdc: 2000025c .word 0x2000025c 08009fe0 : #define VREFINT_CAL_ADDR ((uint16_t*)0x1FFFF7BA) // для STM32F1! static uint8_t CP_IsInRange(int32_t v, int32_t lo, int32_t hi) { 8009fe0: b480 push {r7} 8009fe2: b085 sub sp, #20 8009fe4: af00 add r7, sp, #0 8009fe6: 60f8 str r0, [r7, #12] 8009fe8: 60b9 str r1, [r7, #8] 8009fea: 607a str r2, [r7, #4] return (v >= lo && v <= hi) ? 1u : 0u; 8009fec: 68fa ldr r2, [r7, #12] 8009fee: 68bb ldr r3, [r7, #8] 8009ff0: 429a cmp r2, r3 8009ff2: db05 blt.n 800a000 8009ff4: 68fa ldr r2, [r7, #12] 8009ff6: 687b ldr r3, [r7, #4] 8009ff8: 429a cmp r2, r3 8009ffa: dc01 bgt.n 800a000 8009ffc: 2301 movs r3, #1 8009ffe: e000 b.n 800a002 800a000: 2300 movs r3, #0 } 800a002: 4618 mov r0, r3 800a004: 3714 adds r7, #20 800a006: 46bd mov sp, r7 800a008: bc80 pop {r7} 800a00a: 4770 bx lr 0800a00c : static int32_t CP_ApplyEma(int32_t raw_mv) { 800a00c: b480 push {r7} 800a00e: b083 sub sp, #12 800a010: af00 add r7, sp, #0 800a012: 6078 str r0, [r7, #4] if (!cp_filter_initialized) { 800a014: 4b12 ldr r3, [pc, #72] @ (800a060 ) 800a016: 781b ldrb r3, [r3, #0] 800a018: 2b00 cmp r3, #0 800a01a: d108 bne.n 800a02e cp_voltage_filt_mv = raw_mv; 800a01c: 4a11 ldr r2, [pc, #68] @ (800a064 ) 800a01e: 687b ldr r3, [r7, #4] 800a020: 6013 str r3, [r2, #0] cp_filter_initialized = 1; 800a022: 4b0f ldr r3, [pc, #60] @ (800a060 ) 800a024: 2201 movs r2, #1 800a026: 701a strb r2, [r3, #0] return cp_voltage_filt_mv; 800a028: 4b0e ldr r3, [pc, #56] @ (800a064 ) 800a02a: 681b ldr r3, [r3, #0] 800a02c: e012 b.n 800a054 } cp_voltage_filt_mv += ((raw_mv - cp_voltage_filt_mv) * CP_EMA_ALPHA_Q8) / 256; 800a02e: 4b0d ldr r3, [pc, #52] @ (800a064 ) 800a030: 681b ldr r3, [r3, #0] 800a032: 687a ldr r2, [r7, #4] 800a034: 1ad3 subs r3, r2, r3 800a036: 2226 movs r2, #38 @ 0x26 800a038: fb02 f303 mul.w r3, r2, r3 800a03c: 2b00 cmp r3, #0 800a03e: da00 bge.n 800a042 800a040: 33ff adds r3, #255 @ 0xff 800a042: 121b asrs r3, r3, #8 800a044: 461a mov r2, r3 800a046: 4b07 ldr r3, [pc, #28] @ (800a064 ) 800a048: 681b ldr r3, [r3, #0] 800a04a: 4413 add r3, r2 800a04c: 4a05 ldr r2, [pc, #20] @ (800a064 ) 800a04e: 6013 str r3, [r2, #0] return cp_voltage_filt_mv; 800a050: 4b04 ldr r3, [pc, #16] @ (800a064 ) 800a052: 681b ldr r3, [r3, #0] } 800a054: 4618 mov r0, r3 800a056: 370c adds r7, #12 800a058: 46bd mov sp, r7 800a05a: bc80 pop {r7} 800a05c: 4770 bx lr 800a05e: bf00 nop 800a060: 20000368 .word 0x20000368 800a064: 20000364 .word 0x20000364 0800a068 : static CP_State_t CP_ClassifyWithHysteresis(int32_t v, CP_State_t prev) { 800a068: b580 push {r7, lr} 800a06a: b082 sub sp, #8 800a06c: af00 add r7, sp, #0 800a06e: 6078 str r0, [r7, #4] 800a070: 460b mov r3, r1 800a072: 70fb strb r3, [r7, #3] switch (prev) { 800a074: 78fb ldrb r3, [r7, #3] 800a076: 2b05 cmp r3, #5 800a078: d84a bhi.n 800a110 800a07a: a201 add r2, pc, #4 @ (adr r2, 800a080 ) 800a07c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a080: 0800a099 .word 0x0800a099 800a084: 0800a0a7 .word 0x0800a0a7 800a088: 0800a0bf .word 0x0800a0bf 800a08c: 0800a0d7 .word 0x0800a0d7 800a090: 0800a0ef .word 0x0800a0ef 800a094: 0800a105 .word 0x0800a105 case EV_STATE_A_IDLE: if (v >= CP_A_EXIT_MV) return EV_STATE_A_IDLE; 800a098: 687b ldr r3, [r7, #4] 800a09a: f242 720f movw r2, #9999 @ 0x270f 800a09e: 4293 cmp r3, r2 800a0a0: dd38 ble.n 800a114 800a0a2: 2300 movs r3, #0 800a0a4: e07e b.n 800a1a4 break; case EV_STATE_B_CONN_PREP: if (CP_IsInRange(v, CP_B_EXIT_LOW_MV, CP_B_EXIT_HIGH_MV)) return EV_STATE_B_CONN_PREP; 800a0a6: f642 1204 movw r2, #10500 @ 0x2904 800a0aa: f641 514c movw r1, #7500 @ 0x1d4c 800a0ae: 6878 ldr r0, [r7, #4] 800a0b0: f7ff ff96 bl 8009fe0 800a0b4: 4603 mov r3, r0 800a0b6: 2b00 cmp r3, #0 800a0b8: d02e beq.n 800a118 800a0ba: 2301 movs r3, #1 800a0bc: e072 b.n 800a1a4 break; case EV_STATE_C_CONN_ACTIVE: if (CP_IsInRange(v, CP_C_EXIT_LOW_MV, CP_C_EXIT_HIGH_MV)) return EV_STATE_C_CONN_ACTIVE; 800a0be: f641 524c movw r2, #7500 @ 0x1d4c 800a0c2: f241 1194 movw r1, #4500 @ 0x1194 800a0c6: 6878 ldr r0, [r7, #4] 800a0c8: f7ff ff8a bl 8009fe0 800a0cc: 4603 mov r3, r0 800a0ce: 2b00 cmp r3, #0 800a0d0: d024 beq.n 800a11c 800a0d2: 2302 movs r3, #2 800a0d4: e066 b.n 800a1a4 break; case EV_STATE_D_CONN_ACT_VENT: if (CP_IsInRange(v, CP_D_EXIT_LOW_MV, CP_D_EXIT_HIGH_MV)) return EV_STATE_D_CONN_ACT_VENT; 800a0d6: f241 1294 movw r2, #4500 @ 0x1194 800a0da: f240 51dc movw r1, #1500 @ 0x5dc 800a0de: 6878 ldr r0, [r7, #4] 800a0e0: f7ff ff7e bl 8009fe0 800a0e4: 4603 mov r3, r0 800a0e6: 2b00 cmp r3, #0 800a0e8: d01a beq.n 800a120 800a0ea: 2303 movs r3, #3 800a0ec: e05a b.n 800a1a4 break; case EV_STATE_E_NO_POWER: if (CP_IsInRange(v, CP_E_EXIT_LOW_MV, CP_E_EXIT_HIGH_MV)) return EV_STATE_E_NO_POWER; 800a0ee: f640 12c4 movw r2, #2500 @ 0x9c4 800a0f2: 492e ldr r1, [pc, #184] @ (800a1ac ) 800a0f4: 6878 ldr r0, [r7, #4] 800a0f6: f7ff ff73 bl 8009fe0 800a0fa: 4603 mov r3, r0 800a0fc: 2b00 cmp r3, #0 800a0fe: d011 beq.n 800a124 800a100: 2304 movs r3, #4 800a102: e04f b.n 800a1a4 break; case EV_STATE_F_ERROR: if (v <= CP_F_EXIT_MV) return EV_STATE_F_ERROR; 800a104: 687b ldr r3, [r7, #4] 800a106: 4a2a ldr r2, [pc, #168] @ (800a1b0 ) 800a108: 4293 cmp r3, r2 800a10a: da0d bge.n 800a128 800a10c: 2305 movs r3, #5 800a10e: e049 b.n 800a1a4 break; default: break; 800a110: bf00 nop 800a112: e00a b.n 800a12a break; 800a114: bf00 nop 800a116: e008 b.n 800a12a break; 800a118: bf00 nop 800a11a: e006 b.n 800a12a break; 800a11c: bf00 nop 800a11e: e004 b.n 800a12a break; 800a120: bf00 nop 800a122: e002 b.n 800a12a break; 800a124: bf00 nop 800a126: e000 b.n 800a12a break; 800a128: bf00 nop } if (v >= CP_A_ENTER_MV) return EV_STATE_A_IDLE; 800a12a: 687b ldr r3, [r7, #4] 800a12c: f642 22f7 movw r2, #10999 @ 0x2af7 800a130: 4293 cmp r3, r2 800a132: dd01 ble.n 800a138 800a134: 2300 movs r3, #0 800a136: e035 b.n 800a1a4 if (CP_IsInRange(v, CP_B_ENTER_LOW_MV, CP_B_ENTER_HIGH_MV)) return EV_STATE_B_CONN_PREP; 800a138: f242 7210 movw r2, #10000 @ 0x2710 800a13c: f44f 51fa mov.w r1, #8000 @ 0x1f40 800a140: 6878 ldr r0, [r7, #4] 800a142: f7ff ff4d bl 8009fe0 800a146: 4603 mov r3, r0 800a148: 2b00 cmp r3, #0 800a14a: d001 beq.n 800a150 800a14c: 2301 movs r3, #1 800a14e: e029 b.n 800a1a4 if (CP_IsInRange(v, CP_C_ENTER_LOW_MV, CP_C_ENTER_HIGH_MV)) return EV_STATE_C_CONN_ACTIVE; 800a150: f641 3258 movw r2, #7000 @ 0x1b58 800a154: f241 3188 movw r1, #5000 @ 0x1388 800a158: 6878 ldr r0, [r7, #4] 800a15a: f7ff ff41 bl 8009fe0 800a15e: 4603 mov r3, r0 800a160: 2b00 cmp r3, #0 800a162: d001 beq.n 800a168 800a164: 2302 movs r3, #2 800a166: e01d b.n 800a1a4 if (CP_IsInRange(v, CP_D_ENTER_LOW_MV, CP_D_ENTER_HIGH_MV)) return EV_STATE_D_CONN_ACT_VENT; 800a168: f44f 627a mov.w r2, #4000 @ 0xfa0 800a16c: f44f 61fa mov.w r1, #2000 @ 0x7d0 800a170: 6878 ldr r0, [r7, #4] 800a172: f7ff ff35 bl 8009fe0 800a176: 4603 mov r3, r0 800a178: 2b00 cmp r3, #0 800a17a: d001 beq.n 800a180 800a17c: 2303 movs r3, #3 800a17e: e011 b.n 800a1a4 if (CP_IsInRange(v, CP_E_ENTER_LOW_MV, CP_E_ENTER_HIGH_MV)) return EV_STATE_E_NO_POWER; 800a180: f44f 62fa mov.w r2, #2000 @ 0x7d0 800a184: 490b ldr r1, [pc, #44] @ (800a1b4 ) 800a186: 6878 ldr r0, [r7, #4] 800a188: f7ff ff2a bl 8009fe0 800a18c: 4603 mov r3, r0 800a18e: 2b00 cmp r3, #0 800a190: d001 beq.n 800a196 800a192: 2304 movs r3, #4 800a194: e006 b.n 800a1a4 if (v <= CP_F_ENTER_MV) return EV_STATE_F_ERROR; 800a196: 687b ldr r3, [r7, #4] 800a198: 4a07 ldr r2, [pc, #28] @ (800a1b8 ) 800a19a: 4293 cmp r3, r2 800a19c: da01 bge.n 800a1a2 800a19e: 2305 movs r3, #5 800a1a0: e000 b.n 800a1a4 return EV_STATE_ACQUIRING; 800a1a2: 2306 movs r3, #6 } 800a1a4: 4618 mov r0, r3 800a1a6: 3708 adds r7, #8 800a1a8: 46bd mov sp, r7 800a1aa: bd80 pop {r7, pc} 800a1ac: fffffa24 .word 0xfffffa24 800a1b0: ffffd6fd .word 0xffffd6fd 800a1b4: fffffc18 .word 0xfffffc18 800a1b8: ffffd315 .word 0xffffd315 0800a1bc : static uint32_t CP_GetDebounceMs(CP_State_t next_state) { 800a1bc: b480 push {r7} 800a1be: b083 sub sp, #12 800a1c0: af00 add r7, sp, #0 800a1c2: 4603 mov r3, r0 800a1c4: 71fb strb r3, [r7, #7] if (next_state == EV_STATE_F_ERROR) { 800a1c6: 79fb ldrb r3, [r7, #7] 800a1c8: 2b05 cmp r3, #5 800a1ca: d107 bne.n 800a1dc if (cp_duty <= CP_LOW_DUTY_THRESHOLD_PERCENT) { 800a1cc: 4b06 ldr r3, [pc, #24] @ (800a1e8 ) 800a1ce: 781b ldrb r3, [r3, #0] 800a1d0: 2b0a cmp r3, #10 800a1d2: d801 bhi.n 800a1d8 return CP_DEBOUNCE_MS_F_LOW_DUTY; 800a1d4: 2364 movs r3, #100 @ 0x64 800a1d6: e002 b.n 800a1de } return CP_DEBOUNCE_MS_F; 800a1d8: 233c movs r3, #60 @ 0x3c 800a1da: e000 b.n 800a1de } return CP_DEBOUNCE_MS_DEFAULT; 800a1dc: 230a movs r3, #10 } 800a1de: 4618 mov r0, r3 800a1e0: 370c adds r7, #12 800a1e2: 46bd mov sp, r7 800a1e4: bc80 pop {r7} 800a1e6: 4770 bx lr 800a1e8: 20000369 .word 0x20000369 0800a1ec : static int32_t CP_ReadVoltageMv(void) { 800a1ec: b580 push {r7, lr} 800a1ee: b084 sub sp, #16 800a1f0: af00 add r7, sp, #0 uint32_t adc = 0; 800a1f2: 2300 movs r3, #0 800a1f4: 60fb str r3, [r7, #12] int32_t v_adc_mv = 0; 800a1f6: 2300 movs r3, #0 800a1f8: 60bb str r3, [r7, #8] int32_t v_out_mv = 0; 800a1fa: 2300 movs r3, #0 800a1fc: 607b str r3, [r7, #4] adc = CP_ReadAdcChannel((uint32_t)4u); 800a1fe: 2004 movs r0, #4 800a200: f7ff fed0 bl 8009fa4 800a204: 60f8 str r0, [r7, #12] v_adc_mv = (int32_t)((adc * 3300u) / 4095u); 800a206: 68fb ldr r3, [r7, #12] 800a208: f640 42e4 movw r2, #3300 @ 0xce4 800a20c: fb03 f202 mul.w r2, r3, r2 800a210: 4b0d ldr r3, [pc, #52] @ (800a248 ) 800a212: fba3 1302 umull r1, r3, r3, r2 800a216: 1ad2 subs r2, r2, r3 800a218: 0852 lsrs r2, r2, #1 800a21a: 4413 add r3, r2 800a21c: 0adb lsrs r3, r3, #11 800a21e: 60bb str r3, [r7, #8] v_out_mv = ((v_adc_mv - 1723) * 1000) / 130; 800a220: 68bb ldr r3, [r7, #8] 800a222: f2a3 63bb subw r3, r3, #1723 @ 0x6bb 800a226: f44f 727a mov.w r2, #1000 @ 0x3e8 800a22a: fb02 f303 mul.w r3, r2, r3 800a22e: 4a07 ldr r2, [pc, #28] @ (800a24c ) 800a230: fb82 1203 smull r1, r2, r2, r3 800a234: 1192 asrs r2, r2, #6 800a236: 17db asrs r3, r3, #31 800a238: 1ad3 subs r3, r2, r3 800a23a: 607b str r3, [r7, #4] return v_out_mv; 800a23c: 687b ldr r3, [r7, #4] } 800a23e: 4618 mov r0, r3 800a240: 3710 adds r7, #16 800a242: 46bd mov sp, r7 800a244: bd80 pop {r7, pc} 800a246: bf00 nop 800a248: 00100101 .word 0x00100101 800a24c: 7e07e07f .word 0x7e07e07f 0800a250 : void CP_Init(void) { 800a250: b580 push {r7, lr} 800a252: af00 add r7, sp, #0 /* TIM3_CH2 (PA7): set 1kHz PWM like original CCS logic. */ htim3.Instance->PSC = 160 - 1; 800a254: 4b0e ldr r3, [pc, #56] @ (800a290 ) 800a256: 681b ldr r3, [r3, #0] 800a258: 229f movs r2, #159 @ 0x9f 800a25a: 629a str r2, [r3, #40] @ 0x28 htim3.Instance->ARR = MAX_DUTY - 1; 800a25c: 4b0c ldr r3, [pc, #48] @ (800a290 ) 800a25e: 681b ldr r3, [r3, #0] 800a260: f240 12c1 movw r2, #449 @ 0x1c1 800a264: 62da str r2, [r3, #44] @ 0x2c #if DUTY_INVERT == 0 htim3.Instance->CCR2 = MAX_DUTY; 800a266: 4b0a ldr r3, [pc, #40] @ (800a290 ) 800a268: 681b ldr r3, [r3, #0] 800a26a: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a26e: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = MAX_DUTY + 5; 800a270: 4b07 ldr r3, [pc, #28] @ (800a290 ) 800a272: 681b ldr r3, [r3, #0] 800a274: f240 12c7 movw r2, #455 @ 0x1c7 800a278: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = 0; htim3.Instance->CCR1 = 0; #endif HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_2); 800a27a: 2104 movs r1, #4 800a27c: 4804 ldr r0, [pc, #16] @ (800a290 ) 800a27e: f006 ffb3 bl 80111e8 HAL_TIM_OC_Start_IT(&htim3, TIM_CHANNEL_1); 800a282: 2100 movs r1, #0 800a284: 4802 ldr r0, [pc, #8] @ (800a290 ) 800a286: f006 fe61 bl 8010f4c } 800a28a: bf00 nop 800a28c: bd80 pop {r7, pc} 800a28e: bf00 nop 800a290: 2000102c .word 0x2000102c 0800a294 : void CP_SetDuty(uint8_t percentage) { 800a294: b480 push {r7} 800a296: b085 sub sp, #20 800a298: af00 add r7, sp, #0 800a29a: 4603 mov r3, r0 800a29c: 71fb strb r3, [r7, #7] uint32_t pwmduty = MAX_DUTY * percentage / 100; 800a29e: 79fb ldrb r3, [r7, #7] 800a2a0: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a2a4: fb02 f303 mul.w r3, r2, r3 800a2a8: 4a0b ldr r2, [pc, #44] @ (800a2d8 ) 800a2aa: fb82 1203 smull r1, r2, r2, r3 800a2ae: 1152 asrs r2, r2, #5 800a2b0: 17db asrs r3, r3, #31 800a2b2: 1ad3 subs r3, r2, r3 800a2b4: 60fb str r3, [r7, #12] cp_duty = percentage; 800a2b6: 4a09 ldr r2, [pc, #36] @ (800a2dc ) 800a2b8: 79fb ldrb r3, [r7, #7] 800a2ba: 7013 strb r3, [r2, #0] #if DUTY_INVERT == 0 htim3.Instance->CCR2 = pwmduty; 800a2bc: 4b08 ldr r3, [pc, #32] @ (800a2e0 ) 800a2be: 681b ldr r3, [r3, #0] 800a2c0: 68fa ldr r2, [r7, #12] 800a2c2: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = 0 + 1; 800a2c4: 4b06 ldr r3, [pc, #24] @ (800a2e0 ) 800a2c6: 681b ldr r3, [r3, #0] 800a2c8: 2201 movs r2, #1 800a2ca: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = MAX_DUTY - pwmduty; htim3.Instance->CCR1 = MAX_DUTY - pwmduty + 5; #endif } 800a2cc: bf00 nop 800a2ce: 3714 adds r7, #20 800a2d0: 46bd mov sp, r7 800a2d2: bc80 pop {r7} 800a2d4: 4770 bx lr 800a2d6: bf00 nop 800a2d8: 51eb851f .word 0x51eb851f 800a2dc: 20000369 .word 0x20000369 800a2e0: 2000102c .word 0x2000102c 0800a2e4 : uint8_t CP_GetDuty(void) { 800a2e4: b480 push {r7} 800a2e6: af00 add r7, sp, #0 return cp_duty; 800a2e8: 4b02 ldr r3, [pc, #8] @ (800a2f4 ) 800a2ea: 781b ldrb r3, [r3, #0] } 800a2ec: 4618 mov r0, r3 800a2ee: 46bd mov sp, r7 800a2f0: bc80 pop {r7} 800a2f2: 4770 bx lr 800a2f4: 20000369 .word 0x20000369 0800a2f8 : int32_t CP_GetVoltage(void) { return cp_voltage_mv; } CP_State_t CP_GetState(void) { 800a2f8: b590 push {r4, r7, lr} 800a2fa: b085 sub sp, #20 800a2fc: af00 add r7, sp, #0 int32_t voltage_real = cp_voltage_filt_mv; 800a2fe: 4b22 ldr r3, [pc, #136] @ (800a388 ) 800a300: 681b ldr r3, [r3, #0] 800a302: 60fb str r3, [r7, #12] uint32_t now = HAL_GetTick(); 800a304: f003 fc34 bl 800db70 800a308: 60b8 str r0, [r7, #8] if(fake_cp_state != EV_STATE_ACQUIRING) { 800a30a: 4b20 ldr r3, [pc, #128] @ (800a38c ) 800a30c: 781b ldrb r3, [r3, #0] 800a30e: 2b06 cmp r3, #6 800a310: d002 beq.n 800a318 return fake_cp_state; 800a312: 4b1e ldr r3, [pc, #120] @ (800a38c ) 800a314: 781b ldrb r3, [r3, #0] 800a316: e032 b.n 800a37e } CP_State_t instant_state = CP_ClassifyWithHysteresis(voltage_real, cp_stable_state); 800a318: 4b1d ldr r3, [pc, #116] @ (800a390 ) 800a31a: 781b ldrb r3, [r3, #0] 800a31c: 4619 mov r1, r3 800a31e: 68f8 ldr r0, [r7, #12] 800a320: f7ff fea2 bl 800a068 800a324: 4603 mov r3, r0 800a326: 71fb strb r3, [r7, #7] if (instant_state == cp_stable_state) { 800a328: 4b19 ldr r3, [pc, #100] @ (800a390 ) 800a32a: 781b ldrb r3, [r3, #0] 800a32c: 79fa ldrb r2, [r7, #7] 800a32e: 429a cmp r2, r3 800a330: d107 bne.n 800a342 cp_candidate_state = cp_stable_state; 800a332: 4b17 ldr r3, [pc, #92] @ (800a390 ) 800a334: 781a ldrb r2, [r3, #0] 800a336: 4b17 ldr r3, [pc, #92] @ (800a394 ) 800a338: 701a strb r2, [r3, #0] cp_candidate_since_ms = now; 800a33a: 4a17 ldr r2, [pc, #92] @ (800a398 ) 800a33c: 68bb ldr r3, [r7, #8] 800a33e: 6013 str r3, [r2, #0] 800a340: e01b b.n 800a37a } else { if (cp_candidate_state != instant_state) { 800a342: 4b14 ldr r3, [pc, #80] @ (800a394 ) 800a344: 781b ldrb r3, [r3, #0] 800a346: 79fa ldrb r2, [r7, #7] 800a348: 429a cmp r2, r3 800a34a: d006 beq.n 800a35a cp_candidate_state = instant_state; 800a34c: 4a11 ldr r2, [pc, #68] @ (800a394 ) 800a34e: 79fb ldrb r3, [r7, #7] 800a350: 7013 strb r3, [r2, #0] cp_candidate_since_ms = now; 800a352: 4a11 ldr r2, [pc, #68] @ (800a398 ) 800a354: 68bb ldr r3, [r7, #8] 800a356: 6013 str r3, [r2, #0] 800a358: e00f b.n 800a37a } else if ((now - cp_candidate_since_ms) >= CP_GetDebounceMs(cp_candidate_state)) { 800a35a: 4b0f ldr r3, [pc, #60] @ (800a398 ) 800a35c: 681b ldr r3, [r3, #0] 800a35e: 68ba ldr r2, [r7, #8] 800a360: 1ad4 subs r4, r2, r3 800a362: 4b0c ldr r3, [pc, #48] @ (800a394 ) 800a364: 781b ldrb r3, [r3, #0] 800a366: 4618 mov r0, r3 800a368: f7ff ff28 bl 800a1bc 800a36c: 4603 mov r3, r0 800a36e: 429c cmp r4, r3 800a370: d303 bcc.n 800a37a cp_stable_state = cp_candidate_state; 800a372: 4b08 ldr r3, [pc, #32] @ (800a394 ) 800a374: 781a ldrb r2, [r3, #0] 800a376: 4b06 ldr r3, [pc, #24] @ (800a390 ) 800a378: 701a strb r2, [r3, #0] } } return cp_stable_state; 800a37a: 4b05 ldr r3, [pc, #20] @ (800a390 ) 800a37c: 781b ldrb r3, [r3, #0] } 800a37e: 4618 mov r0, r3 800a380: 3714 adds r7, #20 800a382: 46bd mov sp, r7 800a384: bd90 pop {r4, r7, pc} 800a386: bf00 nop 800a388: 20000364 .word 0x20000364 800a38c: 20000004 .word 0x20000004 800a390: 20000005 .word 0x20000005 800a394: 20000006 .word 0x20000006 800a398: 2000036c .word 0x2000036c 0800a39c : void CP_Loop(void) { (void)CP_GetState(); } void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 800a39c: b580 push {r7, lr} 800a39e: b082 sub sp, #8 800a3a0: af00 add r7, sp, #0 800a3a2: 6078 str r0, [r7, #4] if (htim->Instance == TIM3 && htim->Channel == HAL_TIM_ACTIVE_CHANNEL_1) { 800a3a4: 687b ldr r3, [r7, #4] 800a3a6: 681b ldr r3, [r3, #0] 800a3a8: 4a0e ldr r2, [pc, #56] @ (800a3e4 ) 800a3aa: 4293 cmp r3, r2 800a3ac: d116 bne.n 800a3dc 800a3ae: 687b ldr r3, [r7, #4] 800a3b0: 7f1b ldrb r3, [r3, #28] 800a3b2: 2b01 cmp r3, #1 800a3b4: d112 bne.n 800a3dc if (ADC_TryLock() == 0u) { 800a3b6: f7ff fb39 bl 8009a2c 800a3ba: 4603 mov r3, r0 800a3bc: 2b00 cmp r3, #0 800a3be: d00c beq.n 800a3da return; } cp_voltage_mv = CP_ReadVoltageMv(); 800a3c0: f7ff ff14 bl 800a1ec 800a3c4: 4603 mov r3, r0 800a3c6: 4a08 ldr r2, [pc, #32] @ (800a3e8 ) 800a3c8: 6013 str r3, [r2, #0] (void)CP_ApplyEma(cp_voltage_mv); 800a3ca: 4b07 ldr r3, [pc, #28] @ (800a3e8 ) 800a3cc: 681b ldr r3, [r3, #0] 800a3ce: 4618 mov r0, r3 800a3d0: f7ff fe1c bl 800a00c ADC_Unlock(); 800a3d4: f7ff fb5c bl 8009a90 800a3d8: e000 b.n 800a3dc return; 800a3da: bf00 nop } } 800a3dc: 3708 adds r7, #8 800a3de: 46bd mov sp, r7 800a3e0: bd80 pop {r7, pc} 800a3e2: bf00 nop 800a3e4: 40000400 .word 0x40000400 800a3e8: 20000360 .word 0x20000360 0800a3ec : CRC_HandleTypeDef hcrc; /* CRC init function */ void MX_CRC_Init(void) { 800a3ec: b580 push {r7, lr} 800a3ee: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 800a3f0: 4b06 ldr r3, [pc, #24] @ (800a40c ) 800a3f2: 4a07 ldr r2, [pc, #28] @ (800a410 ) 800a3f4: 601a str r2, [r3, #0] if (HAL_CRC_Init(&hcrc) != HAL_OK) 800a3f6: 4805 ldr r0, [pc, #20] @ (800a40c ) 800a3f8: f005 f8d1 bl 800f59e 800a3fc: 4603 mov r3, r0 800a3fe: 2b00 cmp r3, #0 800a400: d001 beq.n 800a406 { Error_Handler(); 800a402: f000 fbcb bl 800ab9c } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 800a406: bf00 nop 800a408: bd80 pop {r7, pc} 800a40a: bf00 nop 800a40c: 20000370 .word 0x20000370 800a410: 40023000 .word 0x40023000 0800a414 : void HAL_CRC_MspInit(CRC_HandleTypeDef* crcHandle) { 800a414: b480 push {r7} 800a416: b085 sub sp, #20 800a418: af00 add r7, sp, #0 800a41a: 6078 str r0, [r7, #4] if(crcHandle->Instance==CRC) 800a41c: 687b ldr r3, [r7, #4] 800a41e: 681b ldr r3, [r3, #0] 800a420: 4a09 ldr r2, [pc, #36] @ (800a448 ) 800a422: 4293 cmp r3, r2 800a424: d10b bne.n 800a43e { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* CRC clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 800a426: 4b09 ldr r3, [pc, #36] @ (800a44c ) 800a428: 695b ldr r3, [r3, #20] 800a42a: 4a08 ldr r2, [pc, #32] @ (800a44c ) 800a42c: f043 0340 orr.w r3, r3, #64 @ 0x40 800a430: 6153 str r3, [r2, #20] 800a432: 4b06 ldr r3, [pc, #24] @ (800a44c ) 800a434: 695b ldr r3, [r3, #20] 800a436: f003 0340 and.w r3, r3, #64 @ 0x40 800a43a: 60fb str r3, [r7, #12] 800a43c: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 800a43e: bf00 nop 800a440: 3714 adds r7, #20 800a442: 46bd mov sp, r7 800a444: bc80 pop {r7} 800a446: 4770 bx lr 800a448: 40023000 .word 0x40023000 800a44c: 40021000 .word 0x40021000 0800a450 <_write>: #if defined(__GNUC__) int _write(int fd, char * ptr, int len) { 800a450: b580 push {r7, lr} 800a452: b084 sub sp, #16 800a454: af00 add r7, sp, #0 800a456: 60f8 str r0, [r7, #12] 800a458: 60b9 str r1, [r7, #8] 800a45a: 607a str r2, [r7, #4] debug_buffer_add((const uint8_t*)ptr, len); 800a45c: 687b ldr r3, [r7, #4] 800a45e: b29b uxth r3, r3 800a460: 4619 mov r1, r3 800a462: 68b8 ldr r0, [r7, #8] 800a464: f000 f806 bl 800a474 return len; 800a468: 687b ldr r3, [r7, #4] } 800a46a: 4618 mov r0, r3 800a46c: 3710 adds r7, #16 800a46e: 46bd mov sp, r7 800a470: bd80 pop {r7, pc} ... 0800a474 : #endif // Добавляет данные в кольцевой буфер void debug_buffer_add(const uint8_t* data, uint16_t len) { 800a474: b480 push {r7} 800a476: b085 sub sp, #20 800a478: af00 add r7, sp, #0 800a47a: 6078 str r0, [r7, #4] 800a47c: 460b mov r3, r1 800a47e: 807b strh r3, [r7, #2] __ASM volatile ("cpsid i" : : : "memory"); 800a480: b672 cpsid i } 800a482: bf00 nop __disable_irq(); for (uint16_t i = 0; i < len; i++) { 800a484: 2300 movs r3, #0 800a486: 81fb strh r3, [r7, #14] 800a488: e045 b.n 800a516 // Если буфер полон, перезаписываем старые данные if (debug_buffer.count >= DEBUG_BUFFER_SIZE) { 800a48a: 4b28 ldr r3, [pc, #160] @ (800a52c ) 800a48c: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a490: b29b uxth r3, r3 800a492: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800a496: d318 bcc.n 800a4ca debug_buffer.read_index = (debug_buffer.read_index + 1) % DEBUG_BUFFER_SIZE; 800a498: 4b24 ldr r3, [pc, #144] @ (800a52c ) 800a49a: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a49e: b29b uxth r3, r3 800a4a0: 3301 adds r3, #1 800a4a2: 425a negs r2, r3 800a4a4: f3c3 0309 ubfx r3, r3, #0, #10 800a4a8: f3c2 0209 ubfx r2, r2, #0, #10 800a4ac: bf58 it pl 800a4ae: 4253 negpl r3, r2 800a4b0: b29a uxth r2, r3 800a4b2: 4b1e ldr r3, [pc, #120] @ (800a52c ) 800a4b4: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count--; 800a4b8: 4b1c ldr r3, [pc, #112] @ (800a52c ) 800a4ba: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a4be: b29b uxth r3, r3 800a4c0: 3b01 subs r3, #1 800a4c2: b29a uxth r2, r3 800a4c4: 4b19 ldr r3, [pc, #100] @ (800a52c ) 800a4c6: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 } debug_buffer.buffer[debug_buffer.write_index] = data[i]; 800a4ca: 89fb ldrh r3, [r7, #14] 800a4cc: 687a ldr r2, [r7, #4] 800a4ce: 4413 add r3, r2 800a4d0: 4a16 ldr r2, [pc, #88] @ (800a52c ) 800a4d2: f8b2 2400 ldrh.w r2, [r2, #1024] @ 0x400 800a4d6: b292 uxth r2, r2 800a4d8: 7819 ldrb r1, [r3, #0] 800a4da: 4b14 ldr r3, [pc, #80] @ (800a52c ) 800a4dc: 5499 strb r1, [r3, r2] debug_buffer.write_index = (debug_buffer.write_index + 1) % DEBUG_BUFFER_SIZE; 800a4de: 4b13 ldr r3, [pc, #76] @ (800a52c ) 800a4e0: f8b3 3400 ldrh.w r3, [r3, #1024] @ 0x400 800a4e4: b29b uxth r3, r3 800a4e6: 3301 adds r3, #1 800a4e8: 425a negs r2, r3 800a4ea: f3c3 0309 ubfx r3, r3, #0, #10 800a4ee: f3c2 0209 ubfx r2, r2, #0, #10 800a4f2: bf58 it pl 800a4f4: 4253 negpl r3, r2 800a4f6: b29a uxth r2, r3 800a4f8: 4b0c ldr r3, [pc, #48] @ (800a52c ) 800a4fa: f8a3 2400 strh.w r2, [r3, #1024] @ 0x400 debug_buffer.count++; 800a4fe: 4b0b ldr r3, [pc, #44] @ (800a52c ) 800a500: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a504: b29b uxth r3, r3 800a506: 3301 adds r3, #1 800a508: b29a uxth r2, r3 800a50a: 4b08 ldr r3, [pc, #32] @ (800a52c ) 800a50c: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 for (uint16_t i = 0; i < len; i++) { 800a510: 89fb ldrh r3, [r7, #14] 800a512: 3301 adds r3, #1 800a514: 81fb strh r3, [r7, #14] 800a516: 89fa ldrh r2, [r7, #14] 800a518: 887b ldrh r3, [r7, #2] 800a51a: 429a cmp r2, r3 800a51c: d3b5 bcc.n 800a48a __ASM volatile ("cpsie i" : : : "memory"); 800a51e: b662 cpsie i } 800a520: bf00 nop } __enable_irq(); } 800a522: bf00 nop 800a524: 3714 adds r7, #20 800a526: 46bd mov sp, r7 800a528: bc80 pop {r7} 800a52a: 4770 bx lr 800a52c: 20000378 .word 0x20000378 0800a530 : // Возвращает количество доступных данных в буфере uint16_t debug_buffer_available(void) { 800a530: b480 push {r7} 800a532: b083 sub sp, #12 800a534: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a536: b672 cpsid i } 800a538: bf00 nop __disable_irq(); uint16_t count = debug_buffer.count; 800a53a: 4b06 ldr r3, [pc, #24] @ (800a554 ) 800a53c: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a540: 80fb strh r3, [r7, #6] __ASM volatile ("cpsie i" : : : "memory"); 800a542: b662 cpsie i } 800a544: bf00 nop __enable_irq(); return count; 800a546: 88fb ldrh r3, [r7, #6] } 800a548: 4618 mov r0, r3 800a54a: 370c adds r7, #12 800a54c: 46bd mov sp, r7 800a54e: bc80 pop {r7} 800a550: 4770 bx lr 800a552: bf00 nop 800a554: 20000378 .word 0x20000378 0800a558 : // Отправляет один пакет данных из буфера через SC_SendPacket (не более 250 байт) void debug_buffer_send(void) { 800a558: b580 push {r7, lr} 800a55a: b082 sub sp, #8 800a55c: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a55e: b672 cpsid i } 800a560: bf00 nop __disable_irq(); // Если буфер пуст, ничего не делаем if (debug_buffer.count == 0) { 800a562: 4b2d ldr r3, [pc, #180] @ (800a618 ) 800a564: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a568: b29b uxth r3, r3 800a56a: 2b00 cmp r3, #0 800a56c: d102 bne.n 800a574 __ASM volatile ("cpsie i" : : : "memory"); 800a56e: b662 cpsie i } 800a570: bf00 nop __enable_irq(); return; 800a572: e04e b.n 800a612 } // Определяем сколько байт можно отправить (не более 250) uint16_t bytes_to_send = debug_buffer.count; 800a574: 4b28 ldr r3, [pc, #160] @ (800a618 ) 800a576: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a57a: 80fb strh r3, [r7, #6] if (bytes_to_send > DEBUG_BUFFER_MAX_COUNT) { 800a57c: 88fb ldrh r3, [r7, #6] 800a57e: 2b80 cmp r3, #128 @ 0x80 800a580: d901 bls.n 800a586 bytes_to_send = DEBUG_BUFFER_MAX_COUNT; 800a582: 2380 movs r3, #128 @ 0x80 800a584: 80fb strh r3, [r7, #6] } // Вычисляем сколько байт до конца буфера uint16_t bytes_to_end = DEBUG_BUFFER_SIZE - debug_buffer.read_index; 800a586: 4b24 ldr r3, [pc, #144] @ (800a618 ) 800a588: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a58c: b29b uxth r3, r3 800a58e: f5c3 6380 rsb r3, r3, #1024 @ 0x400 800a592: 80bb strh r3, [r7, #4] // Отправляем только непрерывный блок (до конца буфера или до bytes_to_send) if (bytes_to_send > bytes_to_end) { 800a594: 88fa ldrh r2, [r7, #6] 800a596: 88bb ldrh r3, [r7, #4] 800a598: 429a cmp r2, r3 800a59a: d901 bls.n 800a5a0 bytes_to_send = bytes_to_end; 800a59c: 88bb ldrh r3, [r7, #4] 800a59e: 80fb strh r3, [r7, #6] } // Отправляем данные напрямую из буфера if(bytes_to_send == debug_buffer.count){ 800a5a0: 4b1d ldr r3, [pc, #116] @ (800a618 ) 800a5a2: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a5a6: b29b uxth r3, r3 800a5a8: 88fa ldrh r2, [r7, #6] 800a5aa: 429a cmp r2, r3 800a5ac: d10c bne.n 800a5c8 SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG); 800a5ae: 4b1a ldr r3, [pc, #104] @ (800a618 ) 800a5b0: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a5b4: b29b uxth r3, r3 800a5b6: 461a mov r2, r3 800a5b8: 4b17 ldr r3, [pc, #92] @ (800a618 ) 800a5ba: 4413 add r3, r2 800a5bc: 88f9 ldrh r1, [r7, #6] 800a5be: 2250 movs r2, #80 @ 0x50 800a5c0: 4618 mov r0, r3 800a5c2: f002 f9ef bl 800c9a4 800a5c6: e00b b.n 800a5e0 }else{ SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG_CONTINUE); 800a5c8: 4b13 ldr r3, [pc, #76] @ (800a618 ) 800a5ca: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a5ce: b29b uxth r3, r3 800a5d0: 461a mov r2, r3 800a5d2: 4b11 ldr r3, [pc, #68] @ (800a618 ) 800a5d4: 4413 add r3, r2 800a5d6: 88f9 ldrh r1, [r7, #6] 800a5d8: 2251 movs r2, #81 @ 0x51 800a5da: 4618 mov r0, r3 800a5dc: f002 f9e2 bl 800c9a4 } debug_buffer.read_index = (debug_buffer.read_index + bytes_to_send) % DEBUG_BUFFER_SIZE; 800a5e0: 4b0d ldr r3, [pc, #52] @ (800a618 ) 800a5e2: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a5e6: b29a uxth r2, r3 800a5e8: 88fb ldrh r3, [r7, #6] 800a5ea: 4413 add r3, r2 800a5ec: b29b uxth r3, r3 800a5ee: f3c3 0309 ubfx r3, r3, #0, #10 800a5f2: b29a uxth r2, r3 800a5f4: 4b08 ldr r3, [pc, #32] @ (800a618 ) 800a5f6: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count -= bytes_to_send; 800a5fa: 4b07 ldr r3, [pc, #28] @ (800a618 ) 800a5fc: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a600: b29a uxth r2, r3 800a602: 88fb ldrh r3, [r7, #6] 800a604: 1ad3 subs r3, r2, r3 800a606: b29a uxth r2, r3 800a608: 4b03 ldr r3, [pc, #12] @ (800a618 ) 800a60a: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 __ASM volatile ("cpsie i" : : : "memory"); 800a60e: b662 cpsie i } 800a610: bf00 nop __enable_irq(); } 800a612: 3708 adds r7, #8 800a614: 46bd mov sp, r7 800a616: bd80 pop {r7, pc} 800a618: 20000378 .word 0x20000378 0800a61c : #define LOG_BUFFER_SIZE 128 uint8_t log_buffer[LOG_BUFFER_SIZE]; // Кастомный printf с приоритетом лога int log_printf(LogLevel_t level, const char *format, ...) { 800a61c: b40e push {r1, r2, r3} 800a61e: b580 push {r7, lr} 800a620: b085 sub sp, #20 800a622: af00 add r7, sp, #0 800a624: 4603 mov r3, r0 800a626: 71fb strb r3, [r7, #7] va_list args; int result; // Добавляем приоритет первым байтом log_buffer[0] = (uint8_t)level; 800a628: 4a15 ldr r2, [pc, #84] @ (800a680 ) 800a62a: 79fb ldrb r3, [r7, #7] 800a62c: 7013 strb r3, [r2, #0] // Форматируем строку начиная со второго байта va_start(args, format); 800a62e: f107 0320 add.w r3, r7, #32 800a632: 60bb str r3, [r7, #8] result = vsnprintf((char*)&log_buffer[1], LOG_BUFFER_SIZE - 2, format, args); 800a634: 68bb ldr r3, [r7, #8] 800a636: 69fa ldr r2, [r7, #28] 800a638: 217e movs r1, #126 @ 0x7e 800a63a: 4812 ldr r0, [pc, #72] @ (800a684 ) 800a63c: f009 f9e2 bl 8013a04 800a640: 60f8 str r0, [r7, #12] va_end(args); // Проверяем, не переполнился ли буфер if (result < 0) { 800a642: 68fb ldr r3, [r7, #12] 800a644: 2b00 cmp r3, #0 800a646: da01 bge.n 800a64c return result; 800a648: 68fb ldr r3, [r7, #12] 800a64a: e012 b.n 800a672 } // Ограничиваем размер, чтобы оставить место для нуль-терминатора if (result >= (LOG_BUFFER_SIZE - 2)) { 800a64c: 68fb ldr r3, [r7, #12] 800a64e: 2b7d cmp r3, #125 @ 0x7d 800a650: dd01 ble.n 800a656 result = LOG_BUFFER_SIZE - 2; 800a652: 237e movs r3, #126 @ 0x7e 800a654: 60fb str r3, [r7, #12] } // Добавляем нуль-терминатор в конец log_buffer[result + 1] = '\0'; 800a656: 68fb ldr r3, [r7, #12] 800a658: 3301 adds r3, #1 800a65a: 4a09 ldr r2, [pc, #36] @ (800a680 ) 800a65c: 2100 movs r1, #0 800a65e: 54d1 strb r1, [r2, r3] // Отправляем в буфер (приоритет + строка + нуль-терминатор) debug_buffer_add(log_buffer, result + 2); 800a660: 68fb ldr r3, [r7, #12] 800a662: b29b uxth r3, r3 800a664: 3302 adds r3, #2 800a666: b29b uxth r3, r3 800a668: 4619 mov r1, r3 800a66a: 4805 ldr r0, [pc, #20] @ (800a680 ) 800a66c: f7ff ff02 bl 800a474 return result; 800a670: 68fb ldr r3, [r7, #12] } 800a672: 4618 mov r0, r3 800a674: 3714 adds r7, #20 800a676: 46bd mov sp, r7 800a678: e8bd 4080 ldmia.w sp!, {r7, lr} 800a67c: b003 add sp, #12 800a67e: 4770 bx lr 800a680: 20000780 .word 0x20000780 800a684: 20000781 .word 0x20000781 0800a688 : * EXTI PB8 ------> I2C1_SCL PB9 ------> I2C1_SDA */ void MX_GPIO_Init(void) { 800a688: b580 push {r7, lr} 800a68a: b08a sub sp, #40 @ 0x28 800a68c: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800a68e: f107 0314 add.w r3, r7, #20 800a692: 2200 movs r2, #0 800a694: 601a str r2, [r3, #0] 800a696: 605a str r2, [r3, #4] 800a698: 609a str r2, [r3, #8] 800a69a: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 800a69c: 4b7d ldr r3, [pc, #500] @ (800a894 ) 800a69e: 699b ldr r3, [r3, #24] 800a6a0: 4a7c ldr r2, [pc, #496] @ (800a894 ) 800a6a2: f043 0310 orr.w r3, r3, #16 800a6a6: 6193 str r3, [r2, #24] 800a6a8: 4b7a ldr r3, [pc, #488] @ (800a894 ) 800a6aa: 699b ldr r3, [r3, #24] 800a6ac: f003 0310 and.w r3, r3, #16 800a6b0: 613b str r3, [r7, #16] 800a6b2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800a6b4: 4b77 ldr r3, [pc, #476] @ (800a894 ) 800a6b6: 699b ldr r3, [r3, #24] 800a6b8: 4a76 ldr r2, [pc, #472] @ (800a894 ) 800a6ba: f043 0304 orr.w r3, r3, #4 800a6be: 6193 str r3, [r2, #24] 800a6c0: 4b74 ldr r3, [pc, #464] @ (800a894 ) 800a6c2: 699b ldr r3, [r3, #24] 800a6c4: f003 0304 and.w r3, r3, #4 800a6c8: 60fb str r3, [r7, #12] 800a6ca: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 800a6cc: 4b71 ldr r3, [pc, #452] @ (800a894 ) 800a6ce: 699b ldr r3, [r3, #24] 800a6d0: 4a70 ldr r2, [pc, #448] @ (800a894 ) 800a6d2: f043 0308 orr.w r3, r3, #8 800a6d6: 6193 str r3, [r2, #24] 800a6d8: 4b6e ldr r3, [pc, #440] @ (800a894 ) 800a6da: 699b ldr r3, [r3, #24] 800a6dc: f003 0308 and.w r3, r3, #8 800a6e0: 60bb str r3, [r7, #8] 800a6e2: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOE_CLK_ENABLE(); 800a6e4: 4b6b ldr r3, [pc, #428] @ (800a894 ) 800a6e6: 699b ldr r3, [r3, #24] 800a6e8: 4a6a ldr r2, [pc, #424] @ (800a894 ) 800a6ea: f043 0340 orr.w r3, r3, #64 @ 0x40 800a6ee: 6193 str r3, [r2, #24] 800a6f0: 4b68 ldr r3, [pc, #416] @ (800a894 ) 800a6f2: 699b ldr r3, [r3, #24] 800a6f4: f003 0340 and.w r3, r3, #64 @ 0x40 800a6f8: 607b str r3, [r7, #4] 800a6fa: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 800a6fc: 4b65 ldr r3, [pc, #404] @ (800a894 ) 800a6fe: 699b ldr r3, [r3, #24] 800a700: 4a64 ldr r2, [pc, #400] @ (800a894 ) 800a702: f043 0320 orr.w r3, r3, #32 800a706: 6193 str r3, [r2, #24] 800a708: 4b62 ldr r3, [pc, #392] @ (800a894 ) 800a70a: 699b ldr r3, [r3, #24] 800a70c: f003 0320 and.w r3, r3, #32 800a710: 603b str r3, [r7, #0] 800a712: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin, GPIO_PIN_RESET); 800a714: 2200 movs r2, #0 800a716: 2138 movs r1, #56 @ 0x38 800a718: 485f ldr r0, [pc, #380] @ (800a898 ) 800a71a: f005 fa3a bl 800fb92 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a71e: 2200 movs r2, #0 800a720: f44f 51f8 mov.w r1, #7936 @ 0x1f00 800a724: 485d ldr r0, [pc, #372] @ (800a89c ) 800a726: f005 fa34 bl 800fb92 |RELAY5_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, GPIO_PIN_RESET); 800a72a: 2200 movs r2, #0 800a72c: f44f 4100 mov.w r1, #32768 @ 0x8000 800a730: 485b ldr r0, [pc, #364] @ (800a8a0 ) 800a732: f005 fa2e bl 800fb92 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, RELAY_DC_Pin|USART2_DIR_Pin, GPIO_PIN_RESET); 800a736: 2200 movs r2, #0 800a738: 2118 movs r1, #24 800a73a: 485a ldr r0, [pc, #360] @ (800a8a4 ) 800a73c: f005 fa29 bl 800fb92 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(EE_WP_GPIO_Port, EE_WP_Pin, GPIO_PIN_RESET); 800a740: 2200 movs r2, #0 800a742: 2180 movs r1, #128 @ 0x80 800a744: 4858 ldr r0, [pc, #352] @ (800a8a8 ) 800a746: f005 fa24 bl 800fb92 /*Configure GPIO pins : RELAY_CP_Pin LOCK_A_Pin LOCK_B_Pin */ GPIO_InitStruct.Pin = RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin; 800a74a: 2338 movs r3, #56 @ 0x38 800a74c: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a74e: 2301 movs r3, #1 800a750: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a752: 2300 movs r3, #0 800a754: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a756: 2302 movs r3, #2 800a758: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800a75a: f107 0314 add.w r3, r7, #20 800a75e: 4619 mov r1, r3 800a760: 484d ldr r0, [pc, #308] @ (800a898 ) 800a762: f005 f87b bl 800f85c /*Configure GPIO pin : IN_SW0_Pin */ GPIO_InitStruct.Pin = IN_SW0_Pin; 800a766: 2302 movs r3, #2 800a768: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a76a: 2300 movs r3, #0 800a76c: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a76e: 2300 movs r3, #0 800a770: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW0_GPIO_Port, &GPIO_InitStruct); 800a772: f107 0314 add.w r3, r7, #20 800a776: 4619 mov r1, r3 800a778: 4849 ldr r0, [pc, #292] @ (800a8a0 ) 800a77a: f005 f86f bl 800f85c /*Configure GPIO pin : IN_SW1_Pin */ GPIO_InitStruct.Pin = IN_SW1_Pin; 800a77e: 2304 movs r3, #4 800a780: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a782: 2300 movs r3, #0 800a784: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 800a786: 2302 movs r3, #2 800a788: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW1_GPIO_Port, &GPIO_InitStruct); 800a78a: f107 0314 add.w r3, r7, #20 800a78e: 4619 mov r1, r3 800a790: 4843 ldr r0, [pc, #268] @ (800a8a0 ) 800a792: f005 f863 bl 800f85c /*Configure GPIO pins : IN0_Pin AC_OK_Pin ISO_IN_Pin */ GPIO_InitStruct.Pin = IN0_Pin|AC_OK_Pin|ISO_IN_Pin; 800a796: f244 0382 movw r3, #16514 @ 0x4082 800a79a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a79c: 2300 movs r3, #0 800a79e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a7a0: 2300 movs r3, #0 800a7a2: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a7a4: f107 0314 add.w r3, r7, #20 800a7a8: 4619 mov r1, r3 800a7aa: 483c ldr r0, [pc, #240] @ (800a89c ) 800a7ac: f005 f856 bl 800f85c /*Configure GPIO pins : RELAY1_Pin RELAY2_Pin RELAY3_Pin RELAY4_Pin RELAY5_Pin */ GPIO_InitStruct.Pin = RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a7b0: f44f 53f8 mov.w r3, #7936 @ 0x1f00 800a7b4: 617b str r3, [r7, #20] |RELAY5_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a7b6: 2301 movs r3, #1 800a7b8: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a7ba: 2300 movs r3, #0 800a7bc: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a7be: 2302 movs r3, #2 800a7c0: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a7c2: f107 0314 add.w r3, r7, #20 800a7c6: 4619 mov r1, r3 800a7c8: 4834 ldr r0, [pc, #208] @ (800a89c ) 800a7ca: f005 f847 bl 800f85c /*Configure GPIO pin : RELAY_CC_Pin */ GPIO_InitStruct.Pin = RELAY_CC_Pin; 800a7ce: f44f 4300 mov.w r3, #32768 @ 0x8000 800a7d2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a7d4: 2301 movs r3, #1 800a7d6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a7d8: 2300 movs r3, #0 800a7da: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a7dc: 2302 movs r3, #2 800a7de: 623b str r3, [r7, #32] HAL_GPIO_Init(RELAY_CC_GPIO_Port, &GPIO_InitStruct); 800a7e0: f107 0314 add.w r3, r7, #20 800a7e4: 4619 mov r1, r3 800a7e6: 482e ldr r0, [pc, #184] @ (800a8a0 ) 800a7e8: f005 f838 bl 800f85c /*Configure GPIO pins : RELAY_DC_Pin USART2_DIR_Pin */ GPIO_InitStruct.Pin = RELAY_DC_Pin|USART2_DIR_Pin; 800a7ec: 2318 movs r3, #24 800a7ee: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a7f0: 2301 movs r3, #1 800a7f2: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a7f4: 2300 movs r3, #0 800a7f6: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a7f8: 2302 movs r3, #2 800a7fa: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800a7fc: f107 0314 add.w r3, r7, #20 800a800: 4619 mov r1, r3 800a802: 4828 ldr r0, [pc, #160] @ (800a8a4 ) 800a804: f005 f82a bl 800f85c /*Configure GPIO pin : IN_ESTOP_Pin */ GPIO_InitStruct.Pin = IN_ESTOP_Pin; 800a808: 2380 movs r3, #128 @ 0x80 800a80a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a80c: 2300 movs r3, #0 800a80e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a810: 2300 movs r3, #0 800a812: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_ESTOP_GPIO_Port, &GPIO_InitStruct); 800a814: f107 0314 add.w r3, r7, #20 800a818: 4619 mov r1, r3 800a81a: 4822 ldr r0, [pc, #136] @ (800a8a4 ) 800a81c: f005 f81e bl 800f85c /*Configure GPIO pins : IN_FB2_Pin IN_FB1_Pin */ GPIO_InitStruct.Pin = IN_FB2_Pin|IN_FB1_Pin; 800a820: 2318 movs r3, #24 800a822: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a824: 2300 movs r3, #0 800a826: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a828: 2300 movs r3, #0 800a82a: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a82c: f107 0314 add.w r3, r7, #20 800a830: 4619 mov r1, r3 800a832: 481d ldr r0, [pc, #116] @ (800a8a8 ) 800a834: f005 f812 bl 800f85c /*Configure GPIO pin : EE_WP_Pin */ GPIO_InitStruct.Pin = EE_WP_Pin; 800a838: 2380 movs r3, #128 @ 0x80 800a83a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a83c: 2301 movs r3, #1 800a83e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a840: 2300 movs r3, #0 800a842: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a844: 2302 movs r3, #2 800a846: 623b str r3, [r7, #32] HAL_GPIO_Init(EE_WP_GPIO_Port, &GPIO_InitStruct); 800a848: f107 0314 add.w r3, r7, #20 800a84c: 4619 mov r1, r3 800a84e: 4816 ldr r0, [pc, #88] @ (800a8a8 ) 800a850: f005 f804 bl 800f85c /*Configure GPIO pins : PB8 PB9 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 800a854: f44f 7340 mov.w r3, #768 @ 0x300 800a858: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 800a85a: 2312 movs r3, #18 800a85c: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a85e: 2303 movs r3, #3 800a860: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a862: f107 0314 add.w r3, r7, #20 800a866: 4619 mov r1, r3 800a868: 480f ldr r0, [pc, #60] @ (800a8a8 ) 800a86a: f004 fff7 bl 800f85c /*Configure peripheral I/O remapping */ __HAL_AFIO_REMAP_I2C1_ENABLE(); 800a86e: 4b0f ldr r3, [pc, #60] @ (800a8ac ) 800a870: 685b ldr r3, [r3, #4] 800a872: 627b str r3, [r7, #36] @ 0x24 800a874: 6a7b ldr r3, [r7, #36] @ 0x24 800a876: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800a87a: 627b str r3, [r7, #36] @ 0x24 800a87c: 6a7b ldr r3, [r7, #36] @ 0x24 800a87e: f043 0302 orr.w r3, r3, #2 800a882: 627b str r3, [r7, #36] @ 0x24 800a884: 4a09 ldr r2, [pc, #36] @ (800a8ac ) 800a886: 6a7b ldr r3, [r7, #36] @ 0x24 800a888: 6053 str r3, [r2, #4] } 800a88a: bf00 nop 800a88c: 3728 adds r7, #40 @ 0x28 800a88e: 46bd mov sp, r7 800a890: bd80 pop {r7, pc} 800a892: bf00 nop 800a894: 40021000 .word 0x40021000 800a898: 40011000 .word 0x40011000 800a89c: 40011800 .word 0x40011800 800a8a0: 40010800 .word 0x40010800 800a8a4: 40011400 .word 0x40011400 800a8a8: 40010c00 .word 0x40010c00 800a8ac: 40010000 .word 0x40010000 0800a8b0 : * bootloader before starting this program. Unfortunately, function * SystemInit() overwrites this change again. * @return none. */ static void VectorBase_Config(void) { 800a8b0: b480 push {r7} 800a8b2: af00 add r7, sp, #0 * c-startup code. */ extern const unsigned long g_pfnVectors[]; /* Remap the vector table to where the vector table is located for this program. */ SCB->VTOR = (unsigned long)&g_pfnVectors[0]; 800a8b4: 4b03 ldr r3, [pc, #12] @ (800a8c4 ) 800a8b6: 4a04 ldr r2, [pc, #16] @ (800a8c8 ) 800a8b8: 609a str r2, [r3, #8] } 800a8ba: bf00 nop 800a8bc: 46bd mov sp, r7 800a8be: bc80 pop {r7} 800a8c0: 4770 bx lr 800a8c2: bf00 nop 800a8c4: e000ed00 .word 0xe000ed00 800a8c8: 08008000 .word 0x08008000 0800a8cc : uint8_t ED_TraceWarning(uint8_t flag, uint8_t id){ 800a8cc: b480 push {r7} 800a8ce: b085 sub sp, #20 800a8d0: af00 add r7, sp, #0 800a8d2: 4603 mov r3, r0 800a8d4: 460a mov r2, r1 800a8d6: 71fb strb r3, [r7, #7] 800a8d8: 4613 mov r3, r2 800a8da: 71bb strb r3, [r7, #6] static uint8_t memory[32]; if(id > 31) return 0; 800a8dc: 79bb ldrb r3, [r7, #6] 800a8de: 2b1f cmp r3, #31 800a8e0: d901 bls.n 800a8e6 800a8e2: 2300 movs r3, #0 800a8e4: e00e b.n 800a904 uint8_t result = 0; 800a8e6: 2300 movs r3, #0 800a8e8: 73fb strb r3, [r7, #15] if(memory[id] != flag){ 800a8ea: 79bb ldrb r3, [r7, #6] 800a8ec: 4a08 ldr r2, [pc, #32] @ (800a910 ) 800a8ee: 5cd3 ldrb r3, [r2, r3] 800a8f0: 79fa ldrb r2, [r7, #7] 800a8f2: 429a cmp r2, r3 800a8f4: d001 beq.n 800a8fa result = 1; 800a8f6: 2301 movs r3, #1 800a8f8: 73fb strb r3, [r7, #15] } memory[id] = flag; 800a8fa: 79bb ldrb r3, [r7, #6] 800a8fc: 4904 ldr r1, [pc, #16] @ (800a910 ) 800a8fe: 79fa ldrb r2, [r7, #7] 800a900: 54ca strb r2, [r1, r3] return result; 800a902: 7bfb ldrb r3, [r7, #15] } 800a904: 4618 mov r0, r3 800a906: 3714 adds r7, #20 800a908: 46bd mov sp, r7 800a90a: bc80 pop {r7} 800a90c: 4770 bx lr 800a90e: bf00 nop 800a910: 20000800 .word 0x20000800 0800a914 : void ED_Delay(uint32_t Delay) { 800a914: b580 push {r7, lr} 800a916: b084 sub sp, #16 800a918: af00 add r7, sp, #0 800a91a: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800a91c: f003 f928 bl 800db70 800a920: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800a922: 687b ldr r3, [r7, #4] 800a924: 60fb str r3, [r7, #12] if (wait < HAL_MAX_DELAY) 800a926: 68fb ldr r3, [r7, #12] 800a928: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800a92c: d00e beq.n 800a94c { wait += (uint32_t)(uwTickFreq); 800a92e: 4b0e ldr r3, [pc, #56] @ (800a968 ) 800a930: 781b ldrb r3, [r3, #0] 800a932: 461a mov r2, r3 800a934: 68fb ldr r3, [r7, #12] 800a936: 4413 add r3, r2 800a938: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait){ 800a93a: e007 b.n 800a94c CCS_SerialLoop(); 800a93c: f001 f936 bl 800bbac // CP_Loop(); CONN_Task(); 800a940: f7ff fa60 bl 8009e04 LED_Task(); 800a944: f001 f81e bl 800b984 SC_Task(); 800a948: f001 feb2 bl 800c6b0 while ((HAL_GetTick() - tickstart) < wait){ 800a94c: f003 f910 bl 800db70 800a950: 4602 mov r2, r0 800a952: 68bb ldr r3, [r7, #8] 800a954: 1ad3 subs r3, r2, r3 800a956: 68fa ldr r2, [r7, #12] 800a958: 429a cmp r2, r3 800a95a: d8ef bhi.n 800a93c } } 800a95c: bf00 nop 800a95e: bf00 nop 800a960: 3710 adds r7, #16 800a962: 46bd mov sp, r7 800a964: bd80 pop {r7, pc} 800a966: bf00 nop 800a968: 20000074 .word 0x20000074 0800a96c : void StopButtonControl(){ 800a96c: b580 push {r7, lr} 800a96e: af00 add r7, sp, #0 //Charging do nothing if(!IN_ReadInput(IN_ESTOP)){ 800a970: 2003 movs r0, #3 800a972: f7fe feeb bl 800974c 800a976: 4603 mov r3, r0 800a978: 2b00 cmp r3, #0 800a97a: d102 bne.n 800a982 CONN.connControl = CMD_STOP; 800a97c: 4b02 ldr r3, [pc, #8] @ (800a988 ) 800a97e: 2201 movs r2, #1 800a980: 701a strb r2, [r3, #0] } } 800a982: bf00 nop 800a984: bd80 pop {r7, pc} 800a986: bf00 nop 800a988: 2000033c .word 0x2000033c 0800a98c : uint8_t temp0, temp1; static void CAN1_MinimalReInit(void) { 800a98c: b580 push {r7, lr} 800a98e: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan1); 800a990: 480b ldr r0, [pc, #44] @ (800a9c0 ) 800a992: f004 f841 bl 800ea18 MX_CAN1_Init(); 800a996: f7ff f895 bl 8009ac4 if (HAL_CAN_Start(&hcan1) != HAL_OK) { 800a99a: 4809 ldr r0, [pc, #36] @ (800a9c0 ) 800a99c: f003 fff8 bl 800e990 800a9a0: 4603 mov r3, r0 800a9a2: 2b00 cmp r3, #0 800a9a4: d001 beq.n 800a9aa Error_Handler(); 800a9a6: f000 f8f9 bl 800ab9c } if (HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) { 800a9aa: 2102 movs r1, #2 800a9ac: 4804 ldr r0, [pc, #16] @ (800a9c0 ) 800a9ae: f004 faa0 bl 800eef2 800a9b2: 4603 mov r3, r0 800a9b4: 2b00 cmp r3, #0 800a9b6: d001 beq.n 800a9bc Error_Handler(); 800a9b8: f000 f8f0 bl 800ab9c } } 800a9bc: bf00 nop 800a9be: bd80 pop {r7, pc} 800a9c0: 200002e8 .word 0x200002e8 0800a9c4
: /** * @brief The application entry point. * @retval int */ int main(void) { 800a9c4: b580 push {r7, lr} 800a9c6: b082 sub sp, #8 800a9c8: af02 add r7, sp, #8 /* USER CODE BEGIN 1 */ VectorBase_Config(); 800a9ca: f7ff ff71 bl 800a8b0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800a9ce: f003 f877 bl 800dac0 /* USER CODE BEGIN Init */ HAL_RCC_DeInit(); 800a9d2: f005 f903 bl 800fbdc /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800a9d6: f000 f871 bl 800aabc /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800a9da: f7ff fe55 bl 800a688 MX_ADC1_Init(); 800a9de: f7fe fda3 bl 8009528 MX_CAN1_Init(); 800a9e2: f7ff f86f bl 8009ac4 MX_CAN2_Init(); 800a9e6: f7ff f8a3 bl 8009b30 MX_RTC_Init(); 800a9ea: f001 f869 bl 800bac0 MX_TIM4_Init(); 800a9ee: f002 fd23 bl 800d438 MX_USART2_UART_Init(); 800a9f2: f002 fea1 bl 800d738 MX_CRC_Init(); 800a9f6: f7ff fcf9 bl 800a3ec MX_UART5_Init(); 800a9fa: f002 fe49 bl 800d690 MX_USART1_UART_Init(); 800a9fe: f002 fe71 bl 800d6e4 MX_USART3_UART_Init(); 800aa02: f002 fec3 bl 800d78c MX_TIM3_Init(); 800aa06: f002 fca1 bl 800d34c /* USER CODE BEGIN 2 */ Init_Peripheral(); 800aa0a: f7fe fef1 bl 80097f0 LED_Init(); 800aa0e: f000 ff99 bl 800b944 HAL_Delay(300); 800aa12: f44f 7096 mov.w r0, #300 @ 0x12c 800aa16: f003 f8b5 bl 800db84 CCS_Init(); 800aa1a: f001 fad9 bl 800bfd0 SC_Init(); 800aa1e: f001 fe33 bl 800c688 log_printf(LOG_INFO, "CCS module start\n"); 800aa22: 4921 ldr r1, [pc, #132] @ (800aaa8 ) 800aa24: 2007 movs r0, #7 800aa26: f7ff fdf9 bl 800a61c ReadVersion(); 800aa2a: f001 fe09 bl 800c640 log_printf(LOG_INFO, "Serial number: %d\n", infoPacket.serialNumber); 800aa2e: 4b1f ldr r3, [pc, #124] @ (800aaac ) 800aa30: 881b ldrh r3, [r3, #0] 800aa32: b29b uxth r3, r3 800aa34: 461a mov r2, r3 800aa36: 491e ldr r1, [pc, #120] @ (800aab0 ) 800aa38: 2007 movs r0, #7 800aa3a: f7ff fdef bl 800a61c log_printf(LOG_INFO, "Board revision: %d\n", infoPacket.boardVersion); 800aa3e: 4b1b ldr r3, [pc, #108] @ (800aaac ) 800aa40: 789b ldrb r3, [r3, #2] 800aa42: 461a mov r2, r3 800aa44: 491b ldr r1, [pc, #108] @ (800aab4 ) 800aa46: 2007 movs r0, #7 800aa48: f7ff fde8 bl 800a61c log_printf(LOG_INFO, "FW version: %d.%d.%d\n", infoPacket.fw_version_major, infoPacket.fw_version_minor, infoPacket.fw_version_patch); 800aa4c: 4b17 ldr r3, [pc, #92] @ (800aaac ) 800aa4e: 889b ldrh r3, [r3, #4] 800aa50: b29b uxth r3, r3 800aa52: 461a mov r2, r3 800aa54: 4b15 ldr r3, [pc, #84] @ (800aaac ) 800aa56: 88db ldrh r3, [r3, #6] 800aa58: b29b uxth r3, r3 800aa5a: 4619 mov r1, r3 800aa5c: 4b13 ldr r3, [pc, #76] @ (800aaac ) 800aa5e: 891b ldrh r3, [r3, #8] 800aa60: b29b uxth r3, r3 800aa62: 9300 str r3, [sp, #0] 800aa64: 460b mov r3, r1 800aa66: 4914 ldr r1, [pc, #80] @ (800aab8 ) 800aa68: 2007 movs r0, #7 800aa6a: f7ff fdd7 bl 800a61c CAN1_MinimalReInit(); 800aa6e: f7ff ff8d bl 800a98c PSU_Init(); 800aa72: f000 fa7d bl 800af70 CONN_Init(); 800aa76: f7ff f96f bl 8009d58 /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ PSU_ReadWrite(); 800aa7a: f000 fb87 bl 800b18c PSU_Task(); 800aa7e: f000 fc33 bl 800b2e8 ED_Delay(10); 800aa82: 200a movs r0, #10 800aa84: f7ff ff46 bl 800a914 METER_CalculateEnergy(); 800aa88: f000 f88e bl 800aba8 CONN_Loop(); 800aa8c: f7ff f97a bl 8009d84 LED_Write(); 800aa90: f000 fe1e bl 800b6d0 ED_Delay(10); 800aa94: 200a movs r0, #10 800aa96: f7ff ff3d bl 800a914 StopButtonControl(); 800aa9a: f7ff ff67 bl 800a96c ED_Delay(50); 800aa9e: 2032 movs r0, #50 @ 0x32 800aaa0: f7ff ff38 bl 800a914 { 800aaa4: bf00 nop 800aaa6: e7e8 b.n 800aa7a 800aaa8: 08015e84 .word 0x08015e84 800aaac: 2000101c .word 0x2000101c 800aab0: 08015e98 .word 0x08015e98 800aab4: 08015eac .word 0x08015eac 800aab8: 08015ec0 .word 0x08015ec0 0800aabc : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800aabc: b580 push {r7, lr} 800aabe: b09c sub sp, #112 @ 0x70 800aac0: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800aac2: f107 0338 add.w r3, r7, #56 @ 0x38 800aac6: 2238 movs r2, #56 @ 0x38 800aac8: 2100 movs r1, #0 800aaca: 4618 mov r0, r3 800aacc: f008 ffd8 bl 8013a80 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800aad0: f107 0324 add.w r3, r7, #36 @ 0x24 800aad4: 2200 movs r2, #0 800aad6: 601a str r2, [r3, #0] 800aad8: 605a str r2, [r3, #4] 800aada: 609a str r2, [r3, #8] 800aadc: 60da str r2, [r3, #12] 800aade: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 800aae0: 1d3b adds r3, r7, #4 800aae2: 2220 movs r2, #32 800aae4: 2100 movs r1, #0 800aae6: 4618 mov r0, r3 800aae8: f008 ffca bl 8013a80 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; 800aaec: 2305 movs r3, #5 800aaee: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800aaf0: f44f 3380 mov.w r3, #65536 @ 0x10000 800aaf4: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV5; 800aaf6: 2304 movs r3, #4 800aaf8: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 800aafa: 2301 movs r3, #1 800aafc: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800aafe: 2301 movs r3, #1 800ab00: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.Prediv1Source = RCC_PREDIV1_SOURCE_PLL2; 800ab02: f44f 3380 mov.w r3, #65536 @ 0x10000 800ab06: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800ab08: 2302 movs r3, #2 800ab0a: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800ab0c: f44f 3380 mov.w r3, #65536 @ 0x10000 800ab10: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 800ab12: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000 800ab16: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL2.PLL2State = RCC_PLL2_ON; 800ab18: 2302 movs r3, #2 800ab1a: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL2.PLL2MUL = RCC_PLL2_MUL8; 800ab1c: f44f 63c0 mov.w r3, #1536 @ 0x600 800ab20: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL2.HSEPrediv2Value = RCC_HSE_PREDIV2_DIV5; 800ab22: 2340 movs r3, #64 @ 0x40 800ab24: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800ab26: f107 0338 add.w r3, r7, #56 @ 0x38 800ab2a: 4618 mov r0, r3 800ab2c: f005 f926 bl 800fd7c 800ab30: 4603 mov r3, r0 800ab32: 2b00 cmp r3, #0 800ab34: d001 beq.n 800ab3a { Error_Handler(); 800ab36: f000 f831 bl 800ab9c } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800ab3a: 230f movs r3, #15 800ab3c: 627b str r3, [r7, #36] @ 0x24 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800ab3e: 2302 movs r3, #2 800ab40: 62bb str r3, [r7, #40] @ 0x28 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800ab42: 2300 movs r3, #0 800ab44: 62fb str r3, [r7, #44] @ 0x2c RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 800ab46: f44f 6380 mov.w r3, #1024 @ 0x400 800ab4a: 633b str r3, [r7, #48] @ 0x30 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 800ab4c: 2300 movs r3, #0 800ab4e: 637b str r3, [r7, #52] @ 0x34 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800ab50: f107 0324 add.w r3, r7, #36 @ 0x24 800ab54: 2102 movs r1, #2 800ab56: 4618 mov r0, r3 800ab58: f005 fc26 bl 80103a8 800ab5c: 4603 mov r3, r0 800ab5e: 2b00 cmp r3, #0 800ab60: d001 beq.n 800ab66 { Error_Handler(); 800ab62: f000 f81b bl 800ab9c } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; 800ab66: 2303 movs r3, #3 800ab68: 607b str r3, [r7, #4] PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 800ab6a: f44f 7380 mov.w r3, #256 @ 0x100 800ab6e: 60bb str r3, [r7, #8] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 800ab70: f44f 4300 mov.w r3, #32768 @ 0x8000 800ab74: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 800ab76: 1d3b adds r3, r7, #4 800ab78: 4618 mov r0, r3 800ab7a: f005 fe0b bl 8010794 800ab7e: 4603 mov r3, r0 800ab80: 2b00 cmp r3, #0 800ab82: d001 beq.n 800ab88 { Error_Handler(); 800ab84: f000 f80a bl 800ab9c } /** Configure the Systick interrupt time */ __HAL_RCC_PLLI2S_ENABLE(); 800ab88: 4b03 ldr r3, [pc, #12] @ (800ab98 ) 800ab8a: 2201 movs r2, #1 800ab8c: 601a str r2, [r3, #0] } 800ab8e: bf00 nop 800ab90: 3770 adds r7, #112 @ 0x70 800ab92: 46bd mov sp, r7 800ab94: bd80 pop {r7, pc} 800ab96: bf00 nop 800ab98: 42420070 .word 0x42420070 0800ab9c : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800ab9c: b480 push {r7} 800ab9e: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800aba0: b672 cpsid i } 800aba2: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 800aba4: bf00 nop 800aba6: e7fd b.n 800aba4 0800aba8 : METER_t METER; // Функция для расчета и накопления энергии c дробной частью без счетчиков void METER_CalculateEnergy() { 800aba8: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} 800abac: b084 sub sp, #16 800abae: af00 add r7, sp, #0 // Проверяем, что индекс находится в пределах массива METER.online = 0; 800abb0: 4b2e ldr r3, [pc, #184] @ (800ac6c ) 800abb2: 2200 movs r2, #0 800abb4: 711a strb r2, [r3, #4] if(CONN.connState == Charging){ 800abb6: 4b2e ldr r3, [pc, #184] @ (800ac70 ) 800abb8: 785b ldrb r3, [r3, #1] 800abba: 2b08 cmp r3, #8 800abbc: d104 bne.n 800abc8 METER.enable = 1; 800abbe: 4b2b ldr r3, [pc, #172] @ (800ac6c ) 800abc0: 2201 movs r2, #1 800abc2: f883 2024 strb.w r2, [r3, #36] @ 0x24 800abc6: e003 b.n 800abd0 }else{ METER.enable = 0; 800abc8: 4b28 ldr r3, [pc, #160] @ (800ac6c ) 800abca: 2200 movs r2, #0 800abcc: f883 2024 strb.w r2, [r3, #36] @ 0x24 } uint32_t currentTick = HAL_GetTick(); // Получаем текущее время в миллисекундах 800abd0: f002 ffce bl 800db70 800abd4: 60f8 str r0, [r7, #12] uint32_t elapsedTimeMs = currentTick - METER.lastTick; // Вычисляем время, прошедшее с последнего вызова в секундах 800abd6: 4b25 ldr r3, [pc, #148] @ (800ac6c ) 800abd8: 689b ldr r3, [r3, #8] 800abda: 68fa ldr r2, [r7, #12] 800abdc: 1ad3 subs r3, r2, r3 800abde: 60bb str r3, [r7, #8] METER.lastTick = currentTick; // Обновляем время последнего вызова для текущего коннектора 800abe0: 4a22 ldr r2, [pc, #136] @ (800ac6c ) 800abe2: 68fb ldr r3, [r7, #12] 800abe4: 6093 str r3, [r2, #8] uint32_t energyWs = CONN.Power * elapsedTimeMs / 1000; // Рассчитываем энергию в ватт-секундах за прошедший промежуток времени 800abe6: 4b22 ldr r3, [pc, #136] @ (800ac70 ) 800abe8: f8d3 3003 ldr.w r3, [r3, #3] 800abec: 68ba ldr r2, [r7, #8] 800abee: fb02 f303 mul.w r3, r2, r3 800abf2: 4a20 ldr r2, [pc, #128] @ (800ac74 ) 800abf4: fba2 2303 umull r2, r3, r2, r3 800abf8: 099b lsrs r3, r3, #6 800abfa: 607b str r3, [r7, #4] //Расчет энергии теперь идет всегда, смещение берем суммарное METER.EnergyPSU_Ws += energyWs; 800abfc: 4b1b ldr r3, [pc, #108] @ (800ac6c ) 800abfe: e9d3 2304 ldrd r2, r3, [r3, #16] 800ac02: 6879 ldr r1, [r7, #4] 800ac04: 2000 movs r0, #0 800ac06: 460c mov r4, r1 800ac08: 4605 mov r5, r0 800ac0a: eb12 0804 adds.w r8, r2, r4 800ac0e: eb43 0905 adc.w r9, r3, r5 800ac12: 4b16 ldr r3, [pc, #88] @ (800ac6c ) 800ac14: e9c3 8904 strd r8, r9, [r3, #16] // Абсолютное значение энергии разъема складывается из накопленной дробной части и значения со счетчиков METER.AbsoluteEnergy = (uint32_t)METER.EnergyPSU_Ws/3600; //переводим в Вт*час 800ac18: 4b14 ldr r3, [pc, #80] @ (800ac6c ) 800ac1a: e9d3 2304 ldrd r2, r3, [r3, #16] 800ac1e: 4b16 ldr r3, [pc, #88] @ (800ac78 ) 800ac20: fba3 2302 umull r2, r3, r3, r2 800ac24: 0adb lsrs r3, r3, #11 800ac26: 4a11 ldr r2, [pc, #68] @ (800ac6c ) 800ac28: 6193 str r3, [r2, #24] if(METER.enable) { 800ac2a: 4b10 ldr r3, [pc, #64] @ (800ac6c ) 800ac2c: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800ac30: 2b00 cmp r3, #0 800ac32: d008 beq.n 800ac46 //enabled state CONN.Energy = METER.AbsoluteEnergy - METER.EnergyOffset;//переводим в Вт*час 800ac34: 4b0d ldr r3, [pc, #52] @ (800ac6c ) 800ac36: 699a ldr r2, [r3, #24] 800ac38: 4b0c ldr r3, [pc, #48] @ (800ac6c ) 800ac3a: 69db ldr r3, [r3, #28] 800ac3c: 1ad3 subs r3, r2, r3 800ac3e: 4a0c ldr r2, [pc, #48] @ (800ac70 ) 800ac40: f8c2 3007 str.w r3, [r2, #7] METER.EnergyOffset = METER.AbsoluteEnergy; } } 800ac44: e00c b.n 800ac60 CONN.Energy = 0; 800ac46: 4b0a ldr r3, [pc, #40] @ (800ac70 ) 800ac48: 2200 movs r2, #0 800ac4a: 71da strb r2, [r3, #7] 800ac4c: 2200 movs r2, #0 800ac4e: 721a strb r2, [r3, #8] 800ac50: 2200 movs r2, #0 800ac52: 725a strb r2, [r3, #9] 800ac54: 2200 movs r2, #0 800ac56: 729a strb r2, [r3, #10] METER.EnergyOffset = METER.AbsoluteEnergy; 800ac58: 4b04 ldr r3, [pc, #16] @ (800ac6c ) 800ac5a: 699b ldr r3, [r3, #24] 800ac5c: 4a03 ldr r2, [pc, #12] @ (800ac6c ) 800ac5e: 61d3 str r3, [r2, #28] } 800ac60: bf00 nop 800ac62: 3710 adds r7, #16 800ac64: 46bd mov sp, r7 800ac66: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} 800ac6a: bf00 nop 800ac6c: 20000820 .word 0x20000820 800ac70: 2000033c .word 0x2000033c 800ac74: 10624dd3 .word 0x10624dd3 800ac78: 91a2b3c5 .word 0x91a2b3c5 0800ac7c : uint32_t can_lastpacket; extern CAN_HandleTypeDef hcan2; static void PSU_SwitchState(PSU_State_t state){ 800ac7c: b580 push {r7, lr} 800ac7e: b082 sub sp, #8 800ac80: af00 add r7, sp, #0 800ac82: 4603 mov r3, r0 800ac84: 71fb strb r3, [r7, #7] PSU0.state = state; 800ac86: 4a06 ldr r2, [pc, #24] @ (800aca0 ) 800ac88: 79fb ldrb r3, [r7, #7] 800ac8a: 71d3 strb r3, [r2, #7] PSU0.statetick = HAL_GetTick(); 800ac8c: f002 ff70 bl 800db70 800ac90: 4603 mov r3, r0 800ac92: 4a03 ldr r2, [pc, #12] @ (800aca0 ) 800ac94: 6113 str r3, [r2, #16] } 800ac96: bf00 nop 800ac98: 3708 adds r7, #8 800ac9a: 46bd mov sp, r7 800ac9c: bd80 pop {r7, pc} 800ac9e: bf00 nop 800aca0: 2000088c .word 0x2000088c 0800aca4 : static uint32_t PSU_StateTime(void){ 800aca4: b580 push {r7, lr} 800aca6: af00 add r7, sp, #0 return HAL_GetTick() - PSU0.statetick; 800aca8: f002 ff62 bl 800db70 800acac: 4602 mov r2, r0 800acae: 4b02 ldr r3, [pc, #8] @ (800acb8 ) 800acb0: 691b ldr r3, [r3, #16] 800acb2: 1ad3 subs r3, r2, r3 } 800acb4: 4618 mov r0, r3 800acb6: bd80 pop {r7, pc} 800acb8: 2000088c .word 0x2000088c 0800acbc : void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan){ 800acbc: b580 push {r7, lr} 800acbe: b084 sub sp, #16 800acc0: af00 add r7, sp, #0 800acc2: 6078 str r0, [r7, #4] static CAN_RxHeaderTypeDef RxHeader; static uint8_t RxData[8] = {0,}; CanId_t CanId; if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO1, &RxHeader, RxData) == HAL_OK) 800acc4: 4b88 ldr r3, [pc, #544] @ (800aee8 ) 800acc6: 4a89 ldr r2, [pc, #548] @ (800aeec ) 800acc8: 2101 movs r1, #1 800acca: 6878 ldr r0, [r7, #4] 800accc: f003 fff0 bl 800ecb0 800acd0: 4603 mov r3, r0 800acd2: 2b00 cmp r3, #0 800acd4: f040 8104 bne.w 800aee0 { memcpy(&CanId, &RxHeader.ExtId, sizeof(CanId_t)); 800acd8: 4b84 ldr r3, [pc, #528] @ (800aeec ) 800acda: 685b ldr r3, [r3, #4] 800acdc: 60bb str r3, [r7, #8] /* Для DC30 поддерживается только один силовой модуль (source == 0) */ if(CanId.source != 0) return; 800acde: 7a3b ldrb r3, [r7, #8] 800ace0: 2b00 cmp r3, #0 800ace2: f040 80fc bne.w 800aede can_lastpacket = HAL_GetTick(); 800ace6: f002 ff43 bl 800db70 800acea: 4603 mov r3, r0 800acec: 4a80 ldr r2, [pc, #512] @ (800aef0 ) 800acee: 6013 str r3, [r2, #0] if(CanId.command==0x02){ 800acf0: 7abb ldrb r3, [r7, #10] 800acf2: f003 033f and.w r3, r3, #63 @ 0x3f 800acf6: b2db uxtb r3, r3 800acf8: 2b02 cmp r3, #2 800acfa: d105 bne.n 800ad08 memcpy(&PSU_02, RxData, 8); 800acfc: 4b7d ldr r3, [pc, #500] @ (800aef4 ) 800acfe: 4a7a ldr r2, [pc, #488] @ (800aee8 ) 800ad00: e892 0003 ldmia.w r2, {r0, r1} 800ad04: e883 0003 stmia.w r3, {r0, r1} } if(CanId.command==0x04){ 800ad08: 7abb ldrb r3, [r7, #10] 800ad0a: f003 033f and.w r3, r3, #63 @ 0x3f 800ad0e: b2db uxtb r3, r3 800ad10: 2b04 cmp r3, #4 800ad12: d119 bne.n 800ad48 memcpy(&PSU_04, RxData, 8); 800ad14: 4b78 ldr r3, [pc, #480] @ (800aef8 ) 800ad16: 4a74 ldr r2, [pc, #464] @ (800aee8 ) 800ad18: e892 0003 ldmia.w r2, {r0, r1} 800ad1c: e883 0003 stmia.w r3, {r0, r1} PSU0.tempAmbient = PSU_04.moduleTemperature; 800ad20: 4b75 ldr r3, [pc, #468] @ (800aef8 ) 800ad22: 791b ldrb r3, [r3, #4] 800ad24: 461a mov r2, r3 800ad26: 4b75 ldr r3, [pc, #468] @ (800aefc ) 800ad28: 61da str r2, [r3, #28] PSU0.status0.raw = PSU_04.modularForm0; 800ad2a: 4b73 ldr r3, [pc, #460] @ (800aef8 ) 800ad2c: 7a1a ldrb r2, [r3, #8] 800ad2e: 4b73 ldr r3, [pc, #460] @ (800aefc ) 800ad30: f883 2020 strb.w r2, [r3, #32] PSU0.status1.raw = PSU_04.modularForm1; 800ad34: 4b70 ldr r3, [pc, #448] @ (800aef8 ) 800ad36: 79da ldrb r2, [r3, #7] 800ad38: 4b70 ldr r3, [pc, #448] @ (800aefc ) 800ad3a: f883 2021 strb.w r2, [r3, #33] @ 0x21 PSU0.status2.raw = PSU_04.modularForm2; 800ad3e: 4b6e ldr r3, [pc, #440] @ (800aef8 ) 800ad40: 799a ldrb r2, [r3, #6] 800ad42: 4b6e ldr r3, [pc, #440] @ (800aefc ) 800ad44: f883 2022 strb.w r2, [r3, #34] @ 0x22 } if(CanId.command==0x06){ 800ad48: 7abb ldrb r3, [r7, #10] 800ad4a: f003 033f and.w r3, r3, #63 @ 0x3f 800ad4e: b2db uxtb r3, r3 800ad50: 2b06 cmp r3, #6 800ad52: d123 bne.n 800ad9c memcpy(&PSU_06, RxData, 8); 800ad54: 4b6a ldr r3, [pc, #424] @ (800af00 ) 800ad56: 4a64 ldr r2, [pc, #400] @ (800aee8 ) 800ad58: e892 0003 ldmia.w r2, {r0, r1} 800ad5c: e883 0003 stmia.w r3, {r0, r1} PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800ad60: 4b67 ldr r3, [pc, #412] @ (800af00 ) 800ad62: 785b ldrb r3, [r3, #1] 800ad64: 461a mov r2, r3 800ad66: 4b66 ldr r3, [pc, #408] @ (800af00 ) 800ad68: 781b ldrb r3, [r3, #0] 800ad6a: 021b lsls r3, r3, #8 800ad6c: 4413 add r3, r2 800ad6e: 461a mov r2, r3 800ad70: 4b63 ldr r3, [pc, #396] @ (800af00 ) 800ad72: 609a str r2, [r3, #8] PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ad74: 4b62 ldr r3, [pc, #392] @ (800af00 ) 800ad76: 78db ldrb r3, [r3, #3] 800ad78: 461a mov r2, r3 800ad7a: 4b61 ldr r3, [pc, #388] @ (800af00 ) 800ad7c: 789b ldrb r3, [r3, #2] 800ad7e: 021b lsls r3, r3, #8 800ad80: 4413 add r3, r2 800ad82: 461a mov r2, r3 800ad84: 4b5e ldr r3, [pc, #376] @ (800af00 ) 800ad86: 60da str r2, [r3, #12] PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ad88: 4b5d ldr r3, [pc, #372] @ (800af00 ) 800ad8a: 795b ldrb r3, [r3, #5] 800ad8c: 461a mov r2, r3 800ad8e: 4b5c ldr r3, [pc, #368] @ (800af00 ) 800ad90: 791b ldrb r3, [r3, #4] 800ad92: 021b lsls r3, r3, #8 800ad94: 4413 add r3, r2 800ad96: 461a mov r2, r3 800ad98: 4b59 ldr r3, [pc, #356] @ (800af00 ) 800ad9a: 611a str r2, [r3, #16] } if(CanId.command==0x08){ 800ad9c: 7abb ldrb r3, [r7, #10] 800ad9e: f003 033f and.w r3, r3, #63 @ 0x3f 800ada2: b2db uxtb r3, r3 800ada4: 2b08 cmp r3, #8 800ada6: d105 bne.n 800adb4 memcpy(&PSU_08, RxData, 8); 800ada8: 4b56 ldr r3, [pc, #344] @ (800af04 ) 800adaa: 4a4f ldr r2, [pc, #316] @ (800aee8 ) 800adac: e892 0003 ldmia.w r2, {r0, r1} 800adb0: e883 0003 stmia.w r3, {r0, r1} } if(CanId.command==0x09){ 800adb4: 7abb ldrb r3, [r7, #10] 800adb6: f003 033f and.w r3, r3, #63 @ 0x3f 800adba: b2db uxtb r3, r3 800adbc: 2b09 cmp r3, #9 800adbe: f040 808f bne.w 800aee0 memcpy(&PSU_09, RxData, 8); 800adc2: 4b51 ldr r3, [pc, #324] @ (800af08 ) 800adc4: 4a48 ldr r2, [pc, #288] @ (800aee8 ) 800adc6: e892 0003 ldmia.w r2, {r0, r1} 800adca: e883 0003 stmia.w r3, {r0, r1} PSU_09.moduleNCurrent = PSU_09.moduleNCurrent_[3]; 800adce: 4b4e ldr r3, [pc, #312] @ (800af08 ) 800add0: 79db ldrb r3, [r3, #7] 800add2: 461a mov r2, r3 800add4: 4b4c ldr r3, [pc, #304] @ (800af08 ) 800add6: 60da str r2, [r3, #12] PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[2]<<8; 800add8: 4b4b ldr r3, [pc, #300] @ (800af08 ) 800adda: 68da ldr r2, [r3, #12] 800addc: 4b4a ldr r3, [pc, #296] @ (800af08 ) 800adde: 799b ldrb r3, [r3, #6] 800ade0: 021b lsls r3, r3, #8 800ade2: 4313 orrs r3, r2 800ade4: 4a48 ldr r2, [pc, #288] @ (800af08 ) 800ade6: 60d3 str r3, [r2, #12] PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[1]<<16; 800ade8: 4b47 ldr r3, [pc, #284] @ (800af08 ) 800adea: 68da ldr r2, [r3, #12] 800adec: 4b46 ldr r3, [pc, #280] @ (800af08 ) 800adee: 795b ldrb r3, [r3, #5] 800adf0: 041b lsls r3, r3, #16 800adf2: 4313 orrs r3, r2 800adf4: 4a44 ldr r2, [pc, #272] @ (800af08 ) 800adf6: 60d3 str r3, [r2, #12] PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[0]<<24; 800adf8: 4b43 ldr r3, [pc, #268] @ (800af08 ) 800adfa: 68da ldr r2, [r3, #12] 800adfc: 4b42 ldr r3, [pc, #264] @ (800af08 ) 800adfe: 791b ldrb r3, [r3, #4] 800ae00: 061b lsls r3, r3, #24 800ae02: 4313 orrs r3, r2 800ae04: 4a40 ldr r2, [pc, #256] @ (800af08 ) 800ae06: 60d3 str r3, [r2, #12] PSU_09.moduleNVoltage = PSU_09.moduleNVoltage_[3]; 800ae08: 4b3f ldr r3, [pc, #252] @ (800af08 ) 800ae0a: 78db ldrb r3, [r3, #3] 800ae0c: 461a mov r2, r3 800ae0e: 4b3e ldr r3, [pc, #248] @ (800af08 ) 800ae10: 609a str r2, [r3, #8] PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[2]<<8; 800ae12: 4b3d ldr r3, [pc, #244] @ (800af08 ) 800ae14: 689a ldr r2, [r3, #8] 800ae16: 4b3c ldr r3, [pc, #240] @ (800af08 ) 800ae18: 789b ldrb r3, [r3, #2] 800ae1a: 021b lsls r3, r3, #8 800ae1c: 4313 orrs r3, r2 800ae1e: 4a3a ldr r2, [pc, #232] @ (800af08 ) 800ae20: 6093 str r3, [r2, #8] PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[1]<<16; 800ae22: 4b39 ldr r3, [pc, #228] @ (800af08 ) 800ae24: 689a ldr r2, [r3, #8] 800ae26: 4b38 ldr r3, [pc, #224] @ (800af08 ) 800ae28: 785b ldrb r3, [r3, #1] 800ae2a: 041b lsls r3, r3, #16 800ae2c: 4313 orrs r3, r2 800ae2e: 4a36 ldr r2, [pc, #216] @ (800af08 ) 800ae30: 6093 str r3, [r2, #8] PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[0]<<24; 800ae32: 4b35 ldr r3, [pc, #212] @ (800af08 ) 800ae34: 689a ldr r2, [r3, #8] 800ae36: 4b34 ldr r3, [pc, #208] @ (800af08 ) 800ae38: 781b ldrb r3, [r3, #0] 800ae3a: 061b lsls r3, r3, #24 800ae3c: 4313 orrs r3, r2 800ae3e: 4a32 ldr r2, [pc, #200] @ (800af08 ) 800ae40: 6093 str r3, [r2, #8] // PSU_09 -> PSU -> CONN (один модуль) { uint16_t v = PSU_09.moduleNVoltage / 1000; 800ae42: 4b31 ldr r3, [pc, #196] @ (800af08 ) 800ae44: 689b ldr r3, [r3, #8] 800ae46: 4a31 ldr r2, [pc, #196] @ (800af0c ) 800ae48: fba2 2303 umull r2, r3, r2, r3 800ae4c: 099b lsrs r3, r3, #6 800ae4e: 81fb strh r3, [r7, #14] int16_t i = PSU_09.moduleNCurrent / 100; 800ae50: 4b2d ldr r3, [pc, #180] @ (800af08 ) 800ae52: 68db ldr r3, [r3, #12] 800ae54: 4a2e ldr r2, [pc, #184] @ (800af10 ) 800ae56: fba2 2303 umull r2, r3, r2, r3 800ae5a: 095b lsrs r3, r3, #5 800ae5c: 81bb strh r3, [r7, #12] // Обновляем модель PSU0 по телеметрии PSU0.outputVoltage = v; 800ae5e: 4a27 ldr r2, [pc, #156] @ (800aefc ) 800ae60: 89fb ldrh r3, [r7, #14] 800ae62: 8053 strh r3, [r2, #2] PSU0.outputCurrent = i; 800ae64: 4a25 ldr r2, [pc, #148] @ (800aefc ) 800ae66: 89bb ldrh r3, [r7, #12] 800ae68: 8093 strh r3, [r2, #4] PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800ae6a: 89fb ldrh r3, [r7, #14] 800ae6c: 2b13 cmp r3, #19 800ae6e: bf8c ite hi 800ae70: 2301 movhi r3, #1 800ae72: 2300 movls r3, #0 800ae74: b2db uxtb r3, r3 800ae76: 461a mov r2, r3 800ae78: 4b20 ldr r3, [pc, #128] @ (800aefc ) 800ae7a: 729a strb r2, [r3, #10] PSU0.online = 1; 800ae7c: 4b1f ldr r3, [pc, #124] @ (800aefc ) 800ae7e: 2201 movs r2, #1 800ae80: 721a strb r2, [r3, #8] PSU0.temperature = PSU_04.moduleTemperature; 800ae82: 4b1d ldr r3, [pc, #116] @ (800aef8 ) 800ae84: 791a ldrb r2, [r3, #4] 800ae86: 4b1d ldr r3, [pc, #116] @ (800aefc ) 800ae88: 719a strb r2, [r3, #6] // Экспортируем значения из PSU0 в CONN только, // когда модуль хотя бы в состоянии READY и выше if(PSU0.state >= PSU_READY){ 800ae8a: 4b1c ldr r3, [pc, #112] @ (800aefc ) 800ae8c: 79db ldrb r3, [r3, #7] 800ae8e: 2b01 cmp r3, #1 800ae90: d926 bls.n 800aee0 CONN.MeasuredVoltage = PSU0.outputVoltage; 800ae92: 4b1a ldr r3, [pc, #104] @ (800aefc ) 800ae94: 885a ldrh r2, [r3, #2] 800ae96: 4b1f ldr r3, [pc, #124] @ (800af14 ) 800ae98: f8a3 2013 strh.w r2, [r3, #19] CONN.MeasuredCurrent = PSU0.outputCurrent; 800ae9c: 4b17 ldr r3, [pc, #92] @ (800aefc ) 800ae9e: f9b3 3004 ldrsh.w r3, [r3, #4] 800aea2: b29a uxth r2, r3 800aea4: 4b1b ldr r3, [pc, #108] @ (800af14 ) 800aea6: f8a3 2015 strh.w r2, [r3, #21] CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800aeaa: 4b1a ldr r3, [pc, #104] @ (800af14 ) 800aeac: f8b3 3015 ldrh.w r3, [r3, #21] 800aeb0: b29b uxth r3, r3 800aeb2: 461a mov r2, r3 800aeb4: 4b17 ldr r3, [pc, #92] @ (800af14 ) 800aeb6: f8b3 3013 ldrh.w r3, [r3, #19] 800aeba: b29b uxth r3, r3 800aebc: fb02 f303 mul.w r3, r2, r3 800aec0: 4a15 ldr r2, [pc, #84] @ (800af18 ) 800aec2: fb82 1203 smull r1, r2, r2, r3 800aec6: 1092 asrs r2, r2, #2 800aec8: 17db asrs r3, r3, #31 800aeca: 1ad3 subs r3, r2, r3 800aecc: 461a mov r2, r3 800aece: 4b11 ldr r3, [pc, #68] @ (800af14 ) 800aed0: f8c3 2003 str.w r2, [r3, #3] CONN.outputEnabled = PSU0.PSU_enabled; 800aed4: 4b09 ldr r3, [pc, #36] @ (800aefc ) 800aed6: 7a9a ldrb r2, [r3, #10] 800aed8: 4b0e ldr r3, [pc, #56] @ (800af14 ) 800aeda: 761a strb r2, [r3, #24] 800aedc: e000 b.n 800aee0 if(CanId.source != 0) return; 800aede: bf00 nop } } } } } 800aee0: 3710 adds r7, #16 800aee2: 46bd mov sp, r7 800aee4: bd80 pop {r7, pc} 800aee6: bf00 nop 800aee8: 200008d0 .word 0x200008d0 800aeec: 200008b4 .word 0x200008b4 800aef0: 200008b0 .word 0x200008b0 800aef4: 20000848 .word 0x20000848 800aef8: 20000854 .word 0x20000854 800aefc: 2000088c .word 0x2000088c 800af00: 20000860 .word 0x20000860 800af04: 20000874 .word 0x20000874 800af08: 2000087c .word 0x2000087c 800af0c: 10624dd3 .word 0x10624dd3 800af10: 51eb851f .word 0x51eb851f 800af14: 2000033c .word 0x2000033c 800af18: 66666667 .word 0x66666667 0800af1c : void PSU_CAN_FilterInit(){ 800af1c: b580 push {r7, lr} 800af1e: b08a sub sp, #40 @ 0x28 800af20: af00 add r7, sp, #0 CAN_FilterTypeDef sFilterConfig; sFilterConfig.FilterBank = 14; 800af22: 230e movs r3, #14 800af24: 617b str r3, [r7, #20] sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; 800af26: 2300 movs r3, #0 800af28: 61bb str r3, [r7, #24] sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; 800af2a: 2301 movs r3, #1 800af2c: 61fb str r3, [r7, #28] sFilterConfig.FilterIdHigh = 0x0000; 800af2e: 2300 movs r3, #0 800af30: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = 0x0000; 800af32: 2300 movs r3, #0 800af34: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 800af36: 2300 movs r3, #0 800af38: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = 0x0000; 800af3a: 2300 movs r3, #0 800af3c: 60fb str r3, [r7, #12] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; 800af3e: 2300 movs r3, #0 800af40: 613b str r3, [r7, #16] sFilterConfig.FilterActivation = ENABLE; 800af42: 2301 movs r3, #1 800af44: 623b str r3, [r7, #32] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 800af46: 2301 movs r3, #1 800af48: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 800af4a: 230e movs r3, #14 800af4c: 627b str r3, [r7, #36] @ 0x24 if(HAL_CAN_ConfigFilter(&hcan2, &sFilterConfig) != HAL_OK) 800af4e: 463b mov r3, r7 800af50: 4619 mov r1, r3 800af52: 4806 ldr r0, [pc, #24] @ (800af6c ) 800af54: f003 fc3c bl 800e7d0 800af58: 4603 mov r3, r0 800af5a: 2b00 cmp r3, #0 800af5c: d001 beq.n 800af62 { Error_Handler(); 800af5e: f7ff fe1d bl 800ab9c } } 800af62: bf00 nop 800af64: 3728 adds r7, #40 @ 0x28 800af66: 46bd mov sp, r7 800af68: bd80 pop {r7, pc} 800af6a: bf00 nop 800af6c: 20000310 .word 0x20000310 0800af70 : void PSU_Init(){ 800af70: b580 push {r7, lr} 800af72: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan2); 800af74: 4813 ldr r0, [pc, #76] @ (800afc4 ) 800af76: f003 fd4f bl 800ea18 MX_CAN2_Init(); 800af7a: f7fe fdd9 bl 8009b30 PSU_CAN_FilterInit(); 800af7e: f7ff ffcd bl 800af1c HAL_CAN_Start(&hcan2); 800af82: 4810 ldr r0, [pc, #64] @ (800afc4 ) 800af84: f003 fd04 bl 800e990 HAL_CAN_ActivateNotification(&hcan2, CAN_IT_RX_FIFO1_MSG_PENDING /* | CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | CAN_IT_TX_MAILBOX_EMPTY*/); 800af88: 2110 movs r1, #16 800af8a: 480e ldr r0, [pc, #56] @ (800afc4 ) 800af8c: f003 ffb1 bl 800eef2 memset(&PSU0, 0, sizeof(PSU0)); 800af90: 2224 movs r2, #36 @ 0x24 800af92: 2100 movs r1, #0 800af94: 480c ldr r0, [pc, #48] @ (800afc8 ) 800af96: f008 fd73 bl 8013a80 PSU0.state = PSU_UNREADY; 800af9a: 4b0b ldr r3, [pc, #44] @ (800afc8 ) 800af9c: 2200 movs r2, #0 800af9e: 71da strb r2, [r3, #7] PSU0.statetick = HAL_GetTick(); 800afa0: f002 fde6 bl 800db70 800afa4: 4603 mov r3, r0 800afa6: 4a08 ldr r2, [pc, #32] @ (800afc8 ) 800afa8: 6113 str r3, [r2, #16] PSU0.power_limit = PSU_MAX_POWER; // kW 800afaa: 4b07 ldr r3, [pc, #28] @ (800afc8 ) 800afac: f247 5230 movw r2, #30000 @ 0x7530 800afb0: 615a str r2, [r3, #20] PSU0.hv_mode = 0; 800afb2: 4b05 ldr r3, [pc, #20] @ (800afc8 ) 800afb4: 2200 movs r2, #0 800afb6: 761a strb r2, [r3, #24] PSU_Enable(0, 0); 800afb8: 2100 movs r1, #0 800afba: 2000 movs r0, #0 800afbc: f000 f806 bl 800afcc } 800afc0: bf00 nop 800afc2: bd80 pop {r7, pc} 800afc4: 20000310 .word 0x20000310 800afc8: 2000088c .word 0x2000088c 0800afcc : void PSU_Enable(uint8_t addr, uint8_t enable){ 800afcc: b580 push {r7, lr} 800afce: b084 sub sp, #16 800afd0: af00 add r7, sp, #0 800afd2: 4603 mov r3, r0 800afd4: 460a mov r2, r1 800afd6: 71fb strb r3, [r7, #7] 800afd8: 4613 mov r3, r2 800afda: 71bb strb r3, [r7, #6] PSU_1A_t data; memset(&data, 0, sizeof(data)); 800afdc: f107 0308 add.w r3, r7, #8 800afe0: 2208 movs r2, #8 800afe2: 2100 movs r1, #0 800afe4: 4618 mov r0, r3 800afe6: f008 fd4b bl 8013a80 /* Для DC30 поддерживается только один модуль с адресом 0 */ if(addr != 0) return; 800afea: 79fb ldrb r3, [r7, #7] 800afec: 2b00 cmp r3, #0 800afee: d115 bne.n 800b01c if(PSU0.online == 0) return; 800aff0: 4b0d ldr r3, [pc, #52] @ (800b028 ) 800aff2: 7a1b ldrb r3, [r3, #8] 800aff4: 2b00 cmp r3, #0 800aff6: d013 beq.n 800b020 data.enable = !enable; 800aff8: 79bb ldrb r3, [r7, #6] 800affa: 2b00 cmp r3, #0 800affc: bf0c ite eq 800affe: 2301 moveq r3, #1 800b000: 2300 movne r3, #0 800b002: b2db uxtb r3, r3 800b004: 723b strb r3, [r7, #8] PSU_SendCmd(0xF0, addr, 0x1A, &data); 800b006: 79f9 ldrb r1, [r7, #7] 800b008: f107 0308 add.w r3, r7, #8 800b00c: 221a movs r2, #26 800b00e: 20f0 movs r0, #240 @ 0xf0 800b010: f000 f866 bl 800b0e0 ED_Delay(CAN_DELAY); 800b014: 2014 movs r0, #20 800b016: f7ff fc7d bl 800a914 800b01a: e002 b.n 800b022 if(addr != 0) return; 800b01c: bf00 nop 800b01e: e000 b.n 800b022 if(PSU0.online == 0) return; 800b020: bf00 nop } 800b022: 3710 adds r7, #16 800b024: 46bd mov sp, r7 800b026: bd80 pop {r7, pc} 800b028: 2000088c .word 0x2000088c 0800b02c : memset(&data, 0, sizeof(data)); data.enable = !enable; if(addr != 0) return; PSU_SendCmd(0xF0, addr, 0x1D, &data); } void PSU_SetVoltageCurrent(uint8_t addr, uint16_t voltage, uint16_t current){ 800b02c: b580 push {r7, lr} 800b02e: b086 sub sp, #24 800b030: af00 add r7, sp, #0 800b032: 4603 mov r3, r0 800b034: 71fb strb r3, [r7, #7] 800b036: 460b mov r3, r1 800b038: 80bb strh r3, [r7, #4] 800b03a: 4613 mov r3, r2 800b03c: 807b strh r3, [r7, #2] PSU_1C_t data; memset(&data, 0, sizeof(data)); 800b03e: f107 0308 add.w r3, r7, #8 800b042: 2208 movs r2, #8 800b044: 2100 movs r1, #0 800b046: 4618 mov r0, r3 800b048: f008 fd1a bl 8013a80 if(addr != 0) return; 800b04c: 79fb ldrb r3, [r7, #7] 800b04e: 2b00 cmp r3, #0 800b050: d140 bne.n 800b0d4 if(voltage 800b058: 2396 movs r3, #150 @ 0x96 800b05a: 80bb strh r3, [r7, #4] if((PSU0.hv_mode==0) && voltage>499) voltage = 499; 800b05c: 4b1f ldr r3, [pc, #124] @ (800b0dc ) 800b05e: 7e1b ldrb r3, [r3, #24] 800b060: 2b00 cmp r3, #0 800b062: d106 bne.n 800b072 800b064: 88bb ldrh r3, [r7, #4] 800b066: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b06a: d302 bcc.n 800b072 800b06c: f240 13f3 movw r3, #499 @ 0x1f3 800b070: 80bb strh r3, [r7, #4] uint32_t current_ma = current * 100; 800b072: 887b ldrh r3, [r7, #2] 800b074: 2264 movs r2, #100 @ 0x64 800b076: fb02 f303 mul.w r3, r2, r3 800b07a: 617b str r3, [r7, #20] uint32_t voltage_mv = voltage * 1000; 800b07c: 88bb ldrh r3, [r7, #4] 800b07e: f44f 727a mov.w r2, #1000 @ 0x3e8 800b082: fb02 f303 mul.w r3, r2, r3 800b086: 613b str r3, [r7, #16] data.moduleCurrentTotal[0] = (current_ma >> 24) & 0xFF; 800b088: 697b ldr r3, [r7, #20] 800b08a: 0e1b lsrs r3, r3, #24 800b08c: b2db uxtb r3, r3 800b08e: 733b strb r3, [r7, #12] data.moduleCurrentTotal[1] = (current_ma >> 16) & 0xFF; 800b090: 697b ldr r3, [r7, #20] 800b092: 0c1b lsrs r3, r3, #16 800b094: b2db uxtb r3, r3 800b096: 737b strb r3, [r7, #13] data.moduleCurrentTotal[2] = (current_ma >> 8) & 0xFF; 800b098: 697b ldr r3, [r7, #20] 800b09a: 0a1b lsrs r3, r3, #8 800b09c: b2db uxtb r3, r3 800b09e: 73bb strb r3, [r7, #14] data.moduleCurrentTotal[3] = (current_ma >> 0) & 0xFF; 800b0a0: 697b ldr r3, [r7, #20] 800b0a2: b2db uxtb r3, r3 800b0a4: 73fb strb r3, [r7, #15] data.moduleVoltage[0] = (voltage_mv >> 24) & 0xFF; 800b0a6: 693b ldr r3, [r7, #16] 800b0a8: 0e1b lsrs r3, r3, #24 800b0aa: b2db uxtb r3, r3 800b0ac: 723b strb r3, [r7, #8] data.moduleVoltage[1] = (voltage_mv >> 16) & 0xFF; 800b0ae: 693b ldr r3, [r7, #16] 800b0b0: 0c1b lsrs r3, r3, #16 800b0b2: b2db uxtb r3, r3 800b0b4: 727b strb r3, [r7, #9] data.moduleVoltage[2] = (voltage_mv >> 8) & 0xFF; 800b0b6: 693b ldr r3, [r7, #16] 800b0b8: 0a1b lsrs r3, r3, #8 800b0ba: b2db uxtb r3, r3 800b0bc: 72bb strb r3, [r7, #10] data.moduleVoltage[3] = (voltage_mv >> 0) & 0xFF; 800b0be: 693b ldr r3, [r7, #16] 800b0c0: b2db uxtb r3, r3 800b0c2: 72fb strb r3, [r7, #11] PSU_SendCmd(0xF0, addr, 0x1C, &data); 800b0c4: 79f9 ldrb r1, [r7, #7] 800b0c6: f107 0308 add.w r3, r7, #8 800b0ca: 221c movs r2, #28 800b0cc: 20f0 movs r0, #240 @ 0xf0 800b0ce: f000 f807 bl 800b0e0 800b0d2: e000 b.n 800b0d6 if(addr != 0) return; 800b0d4: bf00 nop } 800b0d6: 3718 adds r7, #24 800b0d8: 46bd mov sp, r7 800b0da: bd80 pop {r7, pc} 800b0dc: 2000088c .word 0x2000088c 0800b0e0 : void PSU_SendCmd(uint8_t source, uint8_t destination, uint8_t cmd, void *data){ 800b0e0: b580 push {r7, lr} 800b0e2: b08c sub sp, #48 @ 0x30 800b0e4: af00 add r7, sp, #0 800b0e6: 603b str r3, [r7, #0] 800b0e8: 4603 mov r3, r0 800b0ea: 71fb strb r3, [r7, #7] 800b0ec: 460b mov r3, r1 800b0ee: 71bb strb r3, [r7, #6] 800b0f0: 4613 mov r3, r2 800b0f2: 717b strb r3, [r7, #5] CanId_t CanId; CanId.source = source; 800b0f4: 79fb ldrb r3, [r7, #7] 800b0f6: f887 3028 strb.w r3, [r7, #40] @ 0x28 CanId.destination = destination; 800b0fa: 79bb ldrb r3, [r7, #6] 800b0fc: f887 3029 strb.w r3, [r7, #41] @ 0x29 CanId.command = cmd; 800b100: 797b ldrb r3, [r7, #5] 800b102: f003 033f and.w r3, r3, #63 @ 0x3f 800b106: b2da uxtb r2, r3 800b108: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 800b10c: f362 0305 bfi r3, r2, #0, #6 800b110: f887 302a strb.w r3, [r7, #42] @ 0x2a CanId.device = 0x0A; 800b114: 8d7b ldrh r3, [r7, #42] @ 0x2a 800b116: 220a movs r2, #10 800b118: f362 1389 bfi r3, r2, #6, #4 800b11c: 857b strh r3, [r7, #42] @ 0x2a int8_t retry_counter = 10; 800b11e: 230a movs r3, #10 800b120: f887 302f strb.w r3, [r7, #47] @ 0x2f CAN_TxHeaderTypeDef tx_header; uint32_t tx_mailbox; HAL_StatusTypeDef CAN_result; memcpy(&tx_header.ExtId, &CanId, sizeof(CanId_t)); 800b124: 6abb ldr r3, [r7, #40] @ 0x28 800b126: 617b str r3, [r7, #20] tx_header.RTR = CAN_RTR_DATA; 800b128: 2300 movs r3, #0 800b12a: 61fb str r3, [r7, #28] tx_header.IDE = CAN_ID_EXT; 800b12c: 2304 movs r3, #4 800b12e: 61bb str r3, [r7, #24] tx_header.DLC = 8; 800b130: 2308 movs r3, #8 800b132: 623b str r3, [r7, #32] while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800b134: e01e b.n 800b174 if (HAL_CAN_GetTxMailboxesFreeLevel(&hcan2) > 0){ 800b136: 4814 ldr r0, [pc, #80] @ (800b188 ) 800b138: f003 fd86 bl 800ec48 800b13c: 4603 mov r3, r0 800b13e: 2b00 cmp r3, #0 800b140: d00e beq.n 800b160 /* отправка сообщения */ CAN_result = HAL_CAN_AddTxMessage(&hcan2, &tx_header, (uint8_t*)data, &tx_mailbox); 800b142: f107 030c add.w r3, r7, #12 800b146: f107 0110 add.w r1, r7, #16 800b14a: 683a ldr r2, [r7, #0] 800b14c: 480e ldr r0, [pc, #56] @ (800b188 ) 800b14e: f003 fcac bl 800eaaa 800b152: 4603 mov r3, r0 800b154: f887 302e strb.w r3, [r7, #46] @ 0x2e /* если отправка удалась, выход */ if(CAN_result == HAL_OK) { 800b158: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 800b15c: 2b00 cmp r3, #0 800b15e: d00e beq.n 800b17e return; retry_counter = 0; } } ED_Delay(1); 800b160: 2001 movs r0, #1 800b162: f7ff fbd7 bl 800a914 retry_counter--; 800b166: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800b16a: b2db uxtb r3, r3 800b16c: 3b01 subs r3, #1 800b16e: b2db uxtb r3, r3 800b170: f887 302f strb.w r3, [r7, #47] @ 0x2f while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800b174: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800b178: 2b00 cmp r3, #0 800b17a: dcdc bgt.n 800b136 800b17c: e000 b.n 800b180 return; 800b17e: bf00 nop } } 800b180: 3730 adds r7, #48 @ 0x30 800b182: 46bd mov sp, r7 800b184: bd80 pop {r7, pc} 800b186: bf00 nop 800b188: 20000310 .word 0x20000310 0800b18c : uint32_t max(uint32_t a, uint32_t b){ if(a>b) return a; else return b; } void PSU_ReadWrite(){ 800b18c: b580 push {r7, lr} 800b18e: b082 sub sp, #8 800b190: af00 add r7, sp, #0 uint8_t zero_data[8] = {0,0,0,0,0,0,0,0}; 800b192: 463b mov r3, r7 800b194: 2200 movs r2, #0 800b196: 601a str r2, [r3, #0] 800b198: 605a str r2, [r3, #4] PSU_SendCmd(0xF0, 0, 0x04, zero_data);ED_Delay(CAN_DELAY); 800b19a: 463b mov r3, r7 800b19c: 2204 movs r2, #4 800b19e: 2100 movs r1, #0 800b1a0: 20f0 movs r0, #240 @ 0xf0 800b1a2: f7ff ff9d bl 800b0e0 800b1a6: 2014 movs r0, #20 800b1a8: f7ff fbb4 bl 800a914 PSU_SendCmd(0xF0, 0, 0x06, zero_data);ED_Delay(CAN_DELAY); 800b1ac: 463b mov r3, r7 800b1ae: 2206 movs r2, #6 800b1b0: 2100 movs r1, #0 800b1b2: 20f0 movs r0, #240 @ 0xf0 800b1b4: f7ff ff94 bl 800b0e0 800b1b8: 2014 movs r0, #20 800b1ba: f7ff fbab bl 800a914 // PSU_SendCmd(0xF0, 0, 0x08, zero_data);ED_Delay(CAN_DELAY); PSU_SendCmd(0xF0, 0, 0x09, zero_data);ED_Delay(CAN_DELAY); 800b1be: 463b mov r3, r7 800b1c0: 2209 movs r2, #9 800b1c2: 2100 movs r1, #0 800b1c4: 20f0 movs r0, #240 @ 0xf0 800b1c6: f7ff ff8b bl 800b0e0 800b1ca: 2014 movs r0, #20 800b1cc: f7ff fba2 bl 800a914 // Power Limit if ((CONN.WantedCurrent/10) * CONN.MeasuredVoltage > PSU0.power_limit){ 800b1d0: 4b41 ldr r3, [pc, #260] @ (800b2d8 ) 800b1d2: f8b3 301b ldrh.w r3, [r3, #27] 800b1d6: b29b uxth r3, r3 800b1d8: 4a40 ldr r2, [pc, #256] @ (800b2dc ) 800b1da: fba2 2303 umull r2, r3, r2, r3 800b1de: 08db lsrs r3, r3, #3 800b1e0: b29b uxth r3, r3 800b1e2: 461a mov r2, r3 800b1e4: 4b3c ldr r3, [pc, #240] @ (800b2d8 ) 800b1e6: f8b3 3013 ldrh.w r3, [r3, #19] 800b1ea: b29b uxth r3, r3 800b1ec: fb02 f303 mul.w r3, r2, r3 800b1f0: 461a mov r2, r3 800b1f2: 4b3b ldr r3, [pc, #236] @ (800b2e0 ) 800b1f4: 695b ldr r3, [r3, #20] 800b1f6: 429a cmp r2, r3 800b1f8: d911 bls.n 800b21e CONN.RequestedCurrent = PSU0.power_limit * 10 / CONN.MeasuredVoltage; 800b1fa: 4b39 ldr r3, [pc, #228] @ (800b2e0 ) 800b1fc: 695a ldr r2, [r3, #20] 800b1fe: 4613 mov r3, r2 800b200: 009b lsls r3, r3, #2 800b202: 4413 add r3, r2 800b204: 005b lsls r3, r3, #1 800b206: 461a mov r2, r3 800b208: 4b33 ldr r3, [pc, #204] @ (800b2d8 ) 800b20a: f8b3 3013 ldrh.w r3, [r3, #19] 800b20e: b29b uxth r3, r3 800b210: fbb2 f3f3 udiv r3, r2, r3 800b214: b29a uxth r2, r3 800b216: 4b30 ldr r3, [pc, #192] @ (800b2d8 ) 800b218: f8a3 2011 strh.w r2, [r3, #17] 800b21c: e006 b.n 800b22c }else{ CONN.RequestedCurrent = CONN.WantedCurrent; 800b21e: 4b2e ldr r3, [pc, #184] @ (800b2d8 ) 800b220: f8b3 301b ldrh.w r3, [r3, #27] 800b224: b29a uxth r2, r3 800b226: 4b2c ldr r3, [pc, #176] @ (800b2d8 ) 800b228: f8a3 2011 strh.w r2, [r3, #17] } if(CONN.RequestedCurrent > (PSU_MAX_CURRENT*10)){ 800b22c: 4b2a ldr r3, [pc, #168] @ (800b2d8 ) 800b22e: f8b3 3011 ldrh.w r3, [r3, #17] 800b232: b29b uxth r3, r3 800b234: f240 5232 movw r2, #1330 @ 0x532 800b238: 4293 cmp r3, r2 800b23a: d908 bls.n 800b24e CONN.RequestedCurrent = PSU_MAX_CURRENT*10; 800b23c: 4b26 ldr r3, [pc, #152] @ (800b2d8 ) 800b23e: 2200 movs r2, #0 800b240: f042 0232 orr.w r2, r2, #50 @ 0x32 800b244: 745a strb r2, [r3, #17] 800b246: 2200 movs r2, #0 800b248: f042 0205 orr.w r2, r2, #5 800b24c: 749a strb r2, [r3, #18] } CONN.RequestedPower = CONN.RequestedCurrent * CONN.RequestedVoltage / 10; 800b24e: 4b22 ldr r3, [pc, #136] @ (800b2d8 ) 800b250: f8b3 3011 ldrh.w r3, [r3, #17] 800b254: b29b uxth r3, r3 800b256: 461a mov r2, r3 800b258: 4b1f ldr r3, [pc, #124] @ (800b2d8 ) 800b25a: f8b3 300f ldrh.w r3, [r3, #15] 800b25e: b29b uxth r3, r3 800b260: fb02 f303 mul.w r3, r2, r3 800b264: 4a1f ldr r2, [pc, #124] @ (800b2e4 ) 800b266: fb82 1203 smull r1, r2, r2, r3 800b26a: 1092 asrs r2, r2, #2 800b26c: 17db asrs r3, r3, #31 800b26e: 1ad3 subs r3, r2, r3 800b270: 461a mov r2, r3 800b272: 4b19 ldr r3, [pc, #100] @ (800b2d8 ) 800b274: f8c3 200b str.w r2, [r3, #11] if(PSU0.ready){ 800b278: 4b19 ldr r3, [pc, #100] @ (800b2e0 ) 800b27a: 7a5b ldrb r3, [r3, #9] 800b27c: 2b00 cmp r3, #0 800b27e: d026 beq.n 800b2ce if (CONN.RequestedVoltage == 500) { // fake 800b280: 4b15 ldr r3, [pc, #84] @ (800b2d8 ) 800b282: f8b3 300f ldrh.w r3, [r3, #15] 800b286: b29b uxth r3, r3 800b288: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b28c: d106 bne.n 800b29c PSU_SetVoltageCurrent(0, 300, 10); // Normal mode 800b28e: 220a movs r2, #10 800b290: f44f 7196 mov.w r1, #300 @ 0x12c 800b294: 2000 movs r0, #0 800b296: f7ff fec9 bl 800b02c 800b29a: e00b b.n 800b2b4 }else{ PSU_SetVoltageCurrent(0, CONN.RequestedVoltage, CONN.RequestedCurrent); // Normal mode 800b29c: 4b0e ldr r3, [pc, #56] @ (800b2d8 ) 800b29e: f8b3 300f ldrh.w r3, [r3, #15] 800b2a2: b29b uxth r3, r3 800b2a4: 4a0c ldr r2, [pc, #48] @ (800b2d8 ) 800b2a6: f8b2 2011 ldrh.w r2, [r2, #17] 800b2aa: b292 uxth r2, r2 800b2ac: 4619 mov r1, r3 800b2ae: 2000 movs r0, #0 800b2b0: f7ff febc bl 800b02c } ED_Delay(CAN_DELAY); 800b2b4: 2014 movs r0, #20 800b2b6: f7ff fb2d bl 800a914 if(CONN.MeasuredVoltage>490) PSU0.hv_mode = 1; 800b2ba: 4b07 ldr r3, [pc, #28] @ (800b2d8 ) 800b2bc: f8b3 3013 ldrh.w r3, [r3, #19] 800b2c0: b29b uxth r3, r3 800b2c2: f5b3 7ff5 cmp.w r3, #490 @ 0x1ea 800b2c6: d902 bls.n 800b2ce 800b2c8: 4b05 ldr r3, [pc, #20] @ (800b2e0 ) 800b2ca: 2201 movs r2, #1 800b2cc: 761a strb r2, [r3, #24] } // PSU_SetHVMode(0, PSU0.hv_mode); // auto set, no need // ED_Delay(CAN_DELAY); } 800b2ce: bf00 nop 800b2d0: 3708 adds r7, #8 800b2d2: 46bd mov sp, r7 800b2d4: bd80 pop {r7, pc} 800b2d6: bf00 nop 800b2d8: 2000033c .word 0x2000033c 800b2dc: cccccccd .word 0xcccccccd 800b2e0: 2000088c .word 0x2000088c 800b2e4: 66666667 .word 0x66666667 0800b2e8 : void PSU_Task(void){ 800b2e8: b598 push {r3, r4, r7, lr} 800b2ea: af00 add r7, sp, #0 static uint32_t psu_on_tick = 0; static uint32_t dc_on_tick = 0; static uint32_t cont_ok_tick = 0; // Обновляем ONLINE/READY по таймауту if((HAL_GetTick() - can_lastpacket) > PSU_ONLINE_TIMEOUT){ 800b2ec: f002 fc40 bl 800db70 800b2f0: 4602 mov r2, r0 800b2f2: 4bb4 ldr r3, [pc, #720] @ (800b5c4 ) 800b2f4: 681b ldr r3, [r3, #0] 800b2f6: 1ad3 subs r3, r2, r3 800b2f8: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b2fc: d920 bls.n 800b340 PSU0.online = 0; 800b2fe: 4bb2 ldr r3, [pc, #712] @ (800b5c8 ) 800b300: 2200 movs r2, #0 800b302: 721a strb r2, [r3, #8] PSU0.PSU_enabled = 0; 800b304: 4bb0 ldr r3, [pc, #704] @ (800b5c8 ) 800b306: 2200 movs r2, #0 800b308: 729a strb r2, [r3, #10] PSU_04.moduleTemperature = 0; 800b30a: 4bb0 ldr r3, [pc, #704] @ (800b5cc ) 800b30c: 2200 movs r2, #0 800b30e: 711a strb r2, [r3, #4] PSU_04.modularForm0 = 0; 800b310: 4bae ldr r3, [pc, #696] @ (800b5cc ) 800b312: 2200 movs r2, #0 800b314: 721a strb r2, [r3, #8] PSU_04.modularForm1 = 0; 800b316: 4bad ldr r3, [pc, #692] @ (800b5cc ) 800b318: 2200 movs r2, #0 800b31a: 71da strb r2, [r3, #7] PSU_04.modularForm2 = 0; 800b31c: 4bab ldr r3, [pc, #684] @ (800b5cc ) 800b31e: 2200 movs r2, #0 800b320: 719a strb r2, [r3, #6] PSU_06.VAB = 0; 800b322: 4bab ldr r3, [pc, #684] @ (800b5d0 ) 800b324: 2200 movs r2, #0 800b326: 609a str r2, [r3, #8] PSU_06.VBC = 0; 800b328: 4ba9 ldr r3, [pc, #676] @ (800b5d0 ) 800b32a: 2200 movs r2, #0 800b32c: 60da str r2, [r3, #12] PSU_06.VCA = 0; 800b32e: 4ba8 ldr r3, [pc, #672] @ (800b5d0 ) 800b330: 2200 movs r2, #0 800b332: 611a str r2, [r3, #16] PSU_09.moduleNCurrent = 0; 800b334: 4ba7 ldr r3, [pc, #668] @ (800b5d4 ) 800b336: 2200 movs r2, #0 800b338: 60da str r2, [r3, #12] PSU_09.moduleNVoltage = 0; 800b33a: 4ba6 ldr r3, [pc, #664] @ (800b5d4 ) 800b33c: 2200 movs r2, #0 800b33e: 609a str r2, [r3, #8] } if(!PSU0.online || !PSU0.enableAC){ 800b340: 4ba1 ldr r3, [pc, #644] @ (800b5c8 ) 800b342: 7a1b ldrb r3, [r3, #8] 800b344: 2b00 cmp r3, #0 800b346: d003 beq.n 800b350 800b348: 4b9f ldr r3, [pc, #636] @ (800b5c8 ) 800b34a: 781b ldrb r3, [r3, #0] 800b34c: 2b00 cmp r3, #0 800b34e: d10c bne.n 800b36a CONN.MeasuredVoltage = 0; 800b350: 4ba1 ldr r3, [pc, #644] @ (800b5d8 ) 800b352: 2200 movs r2, #0 800b354: 74da strb r2, [r3, #19] 800b356: 2200 movs r2, #0 800b358: 751a strb r2, [r3, #20] CONN.MeasuredCurrent = 0; 800b35a: 4b9f ldr r3, [pc, #636] @ (800b5d8 ) 800b35c: 2200 movs r2, #0 800b35e: 755a strb r2, [r3, #21] 800b360: 2200 movs r2, #0 800b362: 759a strb r2, [r3, #22] CONN.outputEnabled = 0; 800b364: 4b9c ldr r3, [pc, #624] @ (800b5d8 ) 800b366: 2200 movs r2, #0 800b368: 761a strb r2, [r3, #24] } // Управление AC-контактором с задержкой отключения 1 минута if(CONN.EvConnected){ 800b36a: 4b9b ldr r3, [pc, #620] @ (800b5d8 ) 800b36c: 7f9b ldrb r3, [r3, #30] 800b36e: 2b00 cmp r3, #0 800b370: d00c beq.n 800b38c RELAY_Write(RELAY_AC, 1); 800b372: 2101 movs r1, #1 800b374: 2004 movs r0, #4 800b376: f7fe f969 bl 800964c psu_on_tick = HAL_GetTick(); 800b37a: f002 fbf9 bl 800db70 800b37e: 4603 mov r3, r0 800b380: 4a96 ldr r2, [pc, #600] @ (800b5dc ) 800b382: 6013 str r3, [r2, #0] PSU0.enableAC = 1; 800b384: 4b90 ldr r3, [pc, #576] @ (800b5c8 ) 800b386: 2201 movs r2, #1 800b388: 701a strb r2, [r3, #0] 800b38a: e010 b.n 800b3ae }else{ if((HAL_GetTick() - psu_on_tick) > 1 * 60000){ 800b38c: f002 fbf0 bl 800db70 800b390: 4602 mov r2, r0 800b392: 4b92 ldr r3, [pc, #584] @ (800b5dc ) 800b394: 681b ldr r3, [r3, #0] 800b396: 1ad3 subs r3, r2, r3 800b398: f64e 2260 movw r2, #60000 @ 0xea60 800b39c: 4293 cmp r3, r2 800b39e: d906 bls.n 800b3ae RELAY_Write(RELAY_AC, 0); 800b3a0: 2100 movs r1, #0 800b3a2: 2004 movs r0, #4 800b3a4: f7fe f952 bl 800964c PSU0.enableAC = 0; 800b3a8: 4b87 ldr r3, [pc, #540] @ (800b5c8 ) 800b3aa: 2200 movs r2, #0 800b3ac: 701a strb r2, [r3, #0] } } // Текущее состояние DC-контактора по обратной связи PSU0.CONT_enabled = IN_ReadInput(IN_CONT_FB_DC); 800b3ae: 2005 movs r0, #5 800b3b0: f7fe f9cc bl 800974c 800b3b4: 4603 mov r3, r0 800b3b6: 461a mov r2, r3 800b3b8: 4b83 ldr r3, [pc, #524] @ (800b5c8 ) 800b3ba: 72da strb r2, [r3, #11] // Обновляем ready с учётом ошибок if(PSU0.online && !PSU0.cont_fault && PSU0.enableAC){ 800b3bc: 4b82 ldr r3, [pc, #520] @ (800b5c8 ) 800b3be: 7a1b ldrb r3, [r3, #8] 800b3c0: 2b00 cmp r3, #0 800b3c2: d007 beq.n 800b3d4 800b3c4: 4b80 ldr r3, [pc, #512] @ (800b5c8 ) 800b3c6: 7b1b ldrb r3, [r3, #12] 800b3c8: 2b00 cmp r3, #0 800b3ca: d103 bne.n 800b3d4 800b3cc: 4b7e ldr r3, [pc, #504] @ (800b5c8 ) 800b3ce: 781b ldrb r3, [r3, #0] 800b3d0: 2b00 cmp r3, #0 800b3d2: d102 bne.n 800b3da // PSU0.ready = 1; }else{ PSU0.ready = 0; 800b3d4: 4b7c ldr r3, [pc, #496] @ (800b5c8 ) 800b3d6: 2200 movs r2, #0 800b3d8: 725a strb r2, [r3, #9] } switch(PSU0.state){ 800b3da: 4b7b ldr r3, [pc, #492] @ (800b5c8 ) 800b3dc: 79db ldrb r3, [r3, #7] 800b3de: 2b09 cmp r3, #9 800b3e0: f200 8155 bhi.w 800b68e 800b3e4: a201 add r2, pc, #4 @ (adr r2, 800b3ec ) 800b3e6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b3ea: bf00 nop 800b3ec: 0800b415 .word 0x0800b415 800b3f0: 0800b449 .word 0x0800b449 800b3f4: 0800b465 .word 0x0800b465 800b3f8: 0800b49d .word 0x0800b49d 800b3fc: 0800b4eb .word 0x0800b4eb 800b400: 0800b52d .word 0x0800b52d 800b404: 0800b597 .word 0x0800b597 800b408: 0800b641 .word 0x0800b641 800b40c: 0800b5f1 .word 0x0800b5f1 800b410: 0800b67b .word 0x0800b67b case PSU_UNREADY: PSU0.enableOutput = 0; 800b414: 4b6c ldr r3, [pc, #432] @ (800b5c8 ) 800b416: 2200 movs r2, #0 800b418: 705a strb r2, [r3, #1] RELAY_Write(RELAY_DC, 0); 800b41a: 2100 movs r1, #0 800b41c: 2003 movs r0, #3 800b41e: f7fe f915 bl 800964c if(PSU0.online && PSU0.enableAC && !PSU0.cont_fault){ 800b422: 4b69 ldr r3, [pc, #420] @ (800b5c8 ) 800b424: 7a1b ldrb r3, [r3, #8] 800b426: 2b00 cmp r3, #0 800b428: f000 8135 beq.w 800b696 800b42c: 4b66 ldr r3, [pc, #408] @ (800b5c8 ) 800b42e: 781b ldrb r3, [r3, #0] 800b430: 2b00 cmp r3, #0 800b432: f000 8130 beq.w 800b696 800b436: 4b64 ldr r3, [pc, #400] @ (800b5c8 ) 800b438: 7b1b ldrb r3, [r3, #12] 800b43a: 2b00 cmp r3, #0 800b43c: f040 812b bne.w 800b696 PSU_SwitchState(PSU_INITIALIZING); 800b440: 2001 movs r0, #1 800b442: f7ff fc1b bl 800ac7c } break; 800b446: e126 b.n 800b696 case PSU_INITIALIZING: if(PSU_StateTime() > 4000){ // Wait 4s for PSU to initialize 800b448: f7ff fc2c bl 800aca4 800b44c: 4603 mov r3, r0 800b44e: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b452: f240 8122 bls.w 800b69a PSU0.ready = 1; 800b456: 4b5c ldr r3, [pc, #368] @ (800b5c8 ) 800b458: 2201 movs r2, #1 800b45a: 725a strb r2, [r3, #9] PSU_SwitchState(PSU_READY); 800b45c: 2002 movs r0, #2 800b45e: f7ff fc0d bl 800ac7c } break; 800b462: e11a b.n 800b69a case PSU_READY: // модуль готов, но выключен PSU0.hv_mode = 0; 800b464: 4b58 ldr r3, [pc, #352] @ (800b5c8 ) 800b466: 2200 movs r2, #0 800b468: 761a strb r2, [r3, #24] RELAY_Write(RELAY_DC, 0); 800b46a: 2100 movs r1, #0 800b46c: 2003 movs r0, #3 800b46e: f7fe f8ed bl 800964c if(!PSU0.ready){ 800b472: 4b55 ldr r3, [pc, #340] @ (800b5c8 ) 800b474: 7a5b ldrb r3, [r3, #9] 800b476: 2b00 cmp r3, #0 800b478: d103 bne.n 800b482 PSU_SwitchState(PSU_UNREADY); 800b47a: 2000 movs r0, #0 800b47c: f7ff fbfe bl 800ac7c break; 800b480: e11c b.n 800b6bc } if(CONN.EnableOutput){ 800b482: 4b55 ldr r3, [pc, #340] @ (800b5d8 ) 800b484: 7ddb ldrb r3, [r3, #23] 800b486: 2b00 cmp r3, #0 800b488: f000 8109 beq.w 800b69e PSU_Enable(0, 1); 800b48c: 2101 movs r1, #1 800b48e: 2000 movs r0, #0 800b490: f7ff fd9c bl 800afcc PSU_SwitchState(PSU_WAIT_ACK_ON); 800b494: 2003 movs r0, #3 800b496: f7ff fbf1 bl 800ac7c } break; 800b49a: e100 b.n 800b69e case PSU_WAIT_ACK_ON: if(PSU0.PSU_enabled && PSU0.ready){ 800b49c: 4b4a ldr r3, [pc, #296] @ (800b5c8 ) 800b49e: 7a9b ldrb r3, [r3, #10] 800b4a0: 2b00 cmp r3, #0 800b4a2: d00c beq.n 800b4be 800b4a4: 4b48 ldr r3, [pc, #288] @ (800b5c8 ) 800b4a6: 7a5b ldrb r3, [r3, #9] 800b4a8: 2b00 cmp r3, #0 800b4aa: d008 beq.n 800b4be dc_on_tick = HAL_GetTick(); 800b4ac: f002 fb60 bl 800db70 800b4b0: 4603 mov r3, r0 800b4b2: 4a4b ldr r2, [pc, #300] @ (800b5e0 ) 800b4b4: 6013 str r3, [r2, #0] PSU_SwitchState(PSU_CONT_WAIT_ACK_ON); 800b4b6: 2004 movs r0, #4 800b4b8: f7ff fbe0 bl 800ac7c PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU on timeout\n"); } break; 800b4bc: e0f1 b.n 800b6a2 }else if(PSU_StateTime() > 10000){ 800b4be: f7ff fbf1 bl 800aca4 800b4c2: 4603 mov r3, r0 800b4c4: f242 7210 movw r2, #10000 @ 0x2710 800b4c8: 4293 cmp r3, r2 800b4ca: f240 80ea bls.w 800b6a2 PSU0.psu_fault = 1; 800b4ce: 4b3e ldr r3, [pc, #248] @ (800b5c8 ) 800b4d0: 2201 movs r2, #1 800b4d2: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b4d4: 4b40 ldr r3, [pc, #256] @ (800b5d8 ) 800b4d6: 220a movs r2, #10 800b4d8: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b4da: 2000 movs r0, #0 800b4dc: f7ff fbce bl 800ac7c log_printf(LOG_ERR, "PSU on timeout\n"); 800b4e0: 4940 ldr r1, [pc, #256] @ (800b5e4 ) 800b4e2: 2004 movs r0, #4 800b4e4: f7ff f89a bl 800a61c break; 800b4e8: e0db b.n 800b6a2 case PSU_CONT_WAIT_ACK_ON: // замыкаем DC-контактор и ждём подтверждение RELAY_Write(RELAY_DC, 1); 800b4ea: 2101 movs r1, #1 800b4ec: 2003 movs r0, #3 800b4ee: f7fe f8ad bl 800964c if(PSU0.CONT_enabled){ 800b4f2: 4b35 ldr r3, [pc, #212] @ (800b5c8 ) 800b4f4: 7adb ldrb r3, [r3, #11] 800b4f6: 2b00 cmp r3, #0 800b4f8: d003 beq.n 800b502 PSU_SwitchState(PSU_CONNECTED); 800b4fa: 2005 movs r0, #5 800b4fc: f7ff fbbe bl 800ac7c PSU0.cont_fault = 1; CONN.chargingError = CONN_ERR_CONTACTOR; PSU_SwitchState(PSU_CURRENT_DROP); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b500: e0d1 b.n 800b6a6 }else if(PSU_StateTime() > 1000){ 800b502: f7ff fbcf bl 800aca4 800b506: 4603 mov r3, r0 800b508: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b50c: f240 80cb bls.w 800b6a6 PSU0.cont_fault = 1; 800b510: 4b2d ldr r3, [pc, #180] @ (800b5c8 ) 800b512: 2201 movs r2, #1 800b514: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b516: 4b30 ldr r3, [pc, #192] @ (800b5d8 ) 800b518: 2207 movs r2, #7 800b51a: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_CURRENT_DROP); 800b51c: 2006 movs r0, #6 800b51e: f7ff fbad bl 800ac7c log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b522: 4931 ldr r1, [pc, #196] @ (800b5e8 ) 800b524: 2004 movs r0, #4 800b526: f7ff f879 bl 800a61c break; 800b52a: e0bc b.n 800b6a6 case PSU_CONNECTED: // Основное рабочее состояние if(!CONN.EnableOutput || !PSU0.ready){ 800b52c: 4b2a ldr r3, [pc, #168] @ (800b5d8 ) 800b52e: 7ddb ldrb r3, [r3, #23] 800b530: 2b00 cmp r3, #0 800b532: d003 beq.n 800b53c 800b534: 4b24 ldr r3, [pc, #144] @ (800b5c8 ) 800b536: 7a5b ldrb r3, [r3, #9] 800b538: 2b00 cmp r3, #0 800b53a: d103 bne.n 800b544 PSU_SwitchState(PSU_CURRENT_DROP); 800b53c: 2006 movs r0, #6 800b53e: f7ff fb9d bl 800ac7c break; 800b542: e0bb b.n 800b6bc } // контроль контактора: 1 c таймаут if (IN_ReadInput(IN_CONT_FB_DC) != RELAY_Read(RELAY_DC)){ 800b544: 2005 movs r0, #5 800b546: f7fe f901 bl 800974c 800b54a: 4603 mov r3, r0 800b54c: 461c mov r4, r3 800b54e: 2003 movs r0, #3 800b550: f7fe f8ec bl 800972c 800b554: 4603 mov r3, r0 800b556: 429c cmp r4, r3 800b558: d017 beq.n 800b58a if((HAL_GetTick() - cont_ok_tick) > 1000){ 800b55a: f002 fb09 bl 800db70 800b55e: 4602 mov r2, r0 800b560: 4b22 ldr r3, [pc, #136] @ (800b5ec ) 800b562: 681b ldr r3, [r3, #0] 800b564: 1ad3 subs r3, r2, r3 800b566: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b56a: f240 809e bls.w 800b6aa CONN.chargingError = CONN_ERR_CONTACTOR; 800b56e: 4b1a ldr r3, [pc, #104] @ (800b5d8 ) 800b570: 2207 movs r2, #7 800b572: 775a strb r2, [r3, #29] PSU0.cont_fault = 1; 800b574: 4b14 ldr r3, [pc, #80] @ (800b5c8 ) 800b576: 2201 movs r2, #1 800b578: 731a strb r2, [r3, #12] PSU_SwitchState(PSU_CURRENT_DROP); 800b57a: 2006 movs r0, #6 800b57c: f7ff fb7e bl 800ac7c log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b580: 4919 ldr r1, [pc, #100] @ (800b5e8 ) 800b582: 2004 movs r0, #4 800b584: f7ff f84a bl 800a61c } }else{ cont_ok_tick = HAL_GetTick(); } break; 800b588: e08f b.n 800b6aa cont_ok_tick = HAL_GetTick(); 800b58a: f002 faf1 bl 800db70 800b58e: 4603 mov r3, r0 800b590: 4a16 ldr r2, [pc, #88] @ (800b5ec ) 800b592: 6013 str r3, [r2, #0] break; 800b594: e089 b.n 800b6aa case PSU_CURRENT_DROP: // снижаем ток до нуля перед отключением DC CONN.RequestedCurrent = 0; 800b596: 4b10 ldr r3, [pc, #64] @ (800b5d8 ) 800b598: 2200 movs r2, #0 800b59a: 745a strb r2, [r3, #17] 800b59c: 2200 movs r2, #0 800b59e: 749a strb r2, [r3, #18] // если ток действительно упал или вышло время, отключаем DC if((CONN.MeasuredCurrent < 30) || (PSU_StateTime() > 5000)){ 800b5a0: 4b0d ldr r3, [pc, #52] @ (800b5d8 ) 800b5a2: f8b3 3015 ldrh.w r3, [r3, #21] 800b5a6: b29b uxth r3, r3 800b5a8: 2b1d cmp r3, #29 800b5aa: d906 bls.n 800b5ba 800b5ac: f7ff fb7a bl 800aca4 800b5b0: 4603 mov r3, r0 800b5b2: f241 3288 movw r2, #5000 @ 0x1388 800b5b6: 4293 cmp r3, r2 800b5b8: d979 bls.n 800b6ae PSU_SwitchState(PSU_CONT_WAIT_ACK_OFF); 800b5ba: 2008 movs r0, #8 800b5bc: f7ff fb5e bl 800ac7c } break; 800b5c0: e075 b.n 800b6ae 800b5c2: bf00 nop 800b5c4: 200008b0 .word 0x200008b0 800b5c8: 2000088c .word 0x2000088c 800b5cc: 20000854 .word 0x20000854 800b5d0: 20000860 .word 0x20000860 800b5d4: 2000087c .word 0x2000087c 800b5d8: 2000033c .word 0x2000033c 800b5dc: 200008d8 .word 0x200008d8 800b5e0: 200008dc .word 0x200008dc 800b5e4: 08015ed8 .word 0x08015ed8 800b5e8: 08015ee8 .word 0x08015ee8 800b5ec: 200008e0 .word 0x200008e0 case PSU_CONT_WAIT_ACK_OFF: RELAY_Write(RELAY_DC, 0); 800b5f0: 2100 movs r1, #0 800b5f2: 2003 movs r0, #3 800b5f4: f7fe f82a bl 800964c if(!PSU0.CONT_enabled){ 800b5f8: 4b31 ldr r3, [pc, #196] @ (800b6c0 ) 800b5fa: 7adb ldrb r3, [r3, #11] 800b5fc: 2b00 cmp r3, #0 800b5fe: d107 bne.n 800b610 PSU_Enable(0, 0); 800b600: 2100 movs r1, #0 800b602: 2000 movs r0, #0 800b604: f7ff fce2 bl 800afcc PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b608: 2007 movs r0, #7 800b60a: f7ff fb37 bl 800ac7c CONN.chargingError = CONN_ERR_CONTACTOR; PSU_Enable(0, 0); PSU_SwitchState(PSU_WAIT_ACK_OFF); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b60e: e050 b.n 800b6b2 }else if(PSU_StateTime() > 1000){ 800b610: f7ff fb48 bl 800aca4 800b614: 4603 mov r3, r0 800b616: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b61a: d94a bls.n 800b6b2 PSU0.cont_fault = 1; 800b61c: 4b28 ldr r3, [pc, #160] @ (800b6c0 ) 800b61e: 2201 movs r2, #1 800b620: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b622: 4b28 ldr r3, [pc, #160] @ (800b6c4 ) 800b624: 2207 movs r2, #7 800b626: 775a strb r2, [r3, #29] PSU_Enable(0, 0); 800b628: 2100 movs r1, #0 800b62a: 2000 movs r0, #0 800b62c: f7ff fcce bl 800afcc PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b630: 2007 movs r0, #7 800b632: f7ff fb23 bl 800ac7c log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b636: 4924 ldr r1, [pc, #144] @ (800b6c8 ) 800b638: 2004 movs r0, #4 800b63a: f7fe ffef bl 800a61c break; 800b63e: e038 b.n 800b6b2 case PSU_WAIT_ACK_OFF: if(!PSU0.PSU_enabled){ 800b640: 4b1f ldr r3, [pc, #124] @ (800b6c0 ) 800b642: 7a9b ldrb r3, [r3, #10] 800b644: 2b00 cmp r3, #0 800b646: d103 bne.n 800b650 PSU_SwitchState(PSU_OFF_PAUSE); 800b648: 2009 movs r0, #9 800b64a: f7ff fb17 bl 800ac7c PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU off timeout\n"); } break; 800b64e: e032 b.n 800b6b6 }else if(PSU_StateTime() > 10000){ 800b650: f7ff fb28 bl 800aca4 800b654: 4603 mov r3, r0 800b656: f242 7210 movw r2, #10000 @ 0x2710 800b65a: 4293 cmp r3, r2 800b65c: d92b bls.n 800b6b6 PSU0.psu_fault = 1; 800b65e: 4b18 ldr r3, [pc, #96] @ (800b6c0 ) 800b660: 2201 movs r2, #1 800b662: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b664: 4b17 ldr r3, [pc, #92] @ (800b6c4 ) 800b666: 220a movs r2, #10 800b668: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b66a: 2000 movs r0, #0 800b66c: f7ff fb06 bl 800ac7c log_printf(LOG_ERR, "PSU off timeout\n"); 800b670: 4916 ldr r1, [pc, #88] @ (800b6cc ) 800b672: 2004 movs r0, #4 800b674: f7fe ffd2 bl 800a61c break; 800b678: e01d b.n 800b6b6 case PSU_OFF_PAUSE: if(PSU_StateTime() > 4000){ 800b67a: f7ff fb13 bl 800aca4 800b67e: 4603 mov r3, r0 800b680: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b684: d919 bls.n 800b6ba PSU_SwitchState(PSU_READY); 800b686: 2002 movs r0, #2 800b688: f7ff faf8 bl 800ac7c } break; 800b68c: e015 b.n 800b6ba default: PSU_SwitchState(PSU_UNREADY); 800b68e: 2000 movs r0, #0 800b690: f7ff faf4 bl 800ac7c break; 800b694: e012 b.n 800b6bc break; 800b696: bf00 nop 800b698: e010 b.n 800b6bc break; 800b69a: bf00 nop 800b69c: e00e b.n 800b6bc break; 800b69e: bf00 nop 800b6a0: e00c b.n 800b6bc break; 800b6a2: bf00 nop 800b6a4: e00a b.n 800b6bc break; 800b6a6: bf00 nop 800b6a8: e008 b.n 800b6bc break; 800b6aa: bf00 nop 800b6ac: e006 b.n 800b6bc break; 800b6ae: bf00 nop 800b6b0: e004 b.n 800b6bc break; 800b6b2: bf00 nop 800b6b4: e002 b.n 800b6bc break; 800b6b6: bf00 nop 800b6b8: e000 b.n 800b6bc break; 800b6ba: bf00 nop } } 800b6bc: bf00 nop 800b6be: bd98 pop {r3, r4, r7, pc} 800b6c0: 2000088c .word 0x2000088c 800b6c4: 2000033c .word 0x2000033c 800b6c8: 08015ee8 .word 0x08015ee8 800b6cc: 08015f08 .word 0x08015f08 0800b6d0 : .Th = 10, .Tf = 50, .Tl = 0, }; void LED_Write(){ 800b6d0: b580 push {r7, lr} 800b6d2: af00 add r7, sp, #0 if(CONN.chargingError != CONN_NO_ERROR){ 800b6d4: 4b34 ldr r3, [pc, #208] @ (800b7a8 ) 800b6d6: 7f5b ldrb r3, [r3, #29] 800b6d8: 2b00 cmp r3, #0 800b6da: d003 beq.n 800b6e4 LED_SetColor(&color_error); 800b6dc: 4833 ldr r0, [pc, #204] @ (800b7ac ) 800b6de: f000 f91f bl 800b920 return; 800b6e2: e05f b.n 800b7a4 } switch(CONN.connState){ 800b6e4: 4b30 ldr r3, [pc, #192] @ (800b7a8 ) 800b6e6: 785b ldrb r3, [r3, #1] 800b6e8: 2b0d cmp r3, #13 800b6ea: d857 bhi.n 800b79c 800b6ec: a201 add r2, pc, #4 @ (adr r2, 800b6f4 ) 800b6ee: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b6f2: bf00 nop 800b6f4: 0800b72d .word 0x0800b72d 800b6f8: 0800b735 .word 0x0800b735 800b6fc: 0800b73d .word 0x0800b73d 800b700: 0800b745 .word 0x0800b745 800b704: 0800b74d .word 0x0800b74d 800b708: 0800b755 .word 0x0800b755 800b70c: 0800b75d .word 0x0800b75d 800b710: 0800b765 .word 0x0800b765 800b714: 0800b76d .word 0x0800b76d 800b718: 0800b775 .word 0x0800b775 800b71c: 0800b77d .word 0x0800b77d 800b720: 0800b785 .word 0x0800b785 800b724: 0800b78d .word 0x0800b78d 800b728: 0800b795 .word 0x0800b795 case Unknown: LED_SetColor(&color_unknown); 800b72c: 4820 ldr r0, [pc, #128] @ (800b7b0 ) 800b72e: f000 f8f7 bl 800b920 break; 800b732: e037 b.n 800b7a4 case Unplugged: LED_SetColor(&color_unplugged); 800b734: 481f ldr r0, [pc, #124] @ (800b7b4 ) 800b736: f000 f8f3 bl 800b920 break; 800b73a: e033 b.n 800b7a4 case Disabled: LED_SetColor(&color_error); 800b73c: 481b ldr r0, [pc, #108] @ (800b7ac ) 800b73e: f000 f8ef bl 800b920 break; 800b742: e02f b.n 800b7a4 case Preparing: LED_SetColor(&color_preparing); 800b744: 481c ldr r0, [pc, #112] @ (800b7b8 ) 800b746: f000 f8eb bl 800b920 break; 800b74a: e02b b.n 800b7a4 case AuthRequired: LED_SetColor(&color_preparing); 800b74c: 481a ldr r0, [pc, #104] @ (800b7b8 ) 800b74e: f000 f8e7 bl 800b920 break; 800b752: e027 b.n 800b7a4 case WaitingForEnergy: LED_SetColor(&color_charging); 800b754: 4819 ldr r0, [pc, #100] @ (800b7bc ) 800b756: f000 f8e3 bl 800b920 break; 800b75a: e023 b.n 800b7a4 case ChargingPausedEV: LED_SetColor(&color_charging); 800b75c: 4817 ldr r0, [pc, #92] @ (800b7bc ) 800b75e: f000 f8df bl 800b920 break; 800b762: e01f b.n 800b7a4 case ChargingPausedEVSE: LED_SetColor(&color_charging); 800b764: 4815 ldr r0, [pc, #84] @ (800b7bc ) 800b766: f000 f8db bl 800b920 break; 800b76a: e01b b.n 800b7a4 case Charging: LED_SetColor(&color_charging); 800b76c: 4813 ldr r0, [pc, #76] @ (800b7bc ) 800b76e: f000 f8d7 bl 800b920 break; 800b772: e017 b.n 800b7a4 case AuthTimeout: LED_SetColor(&color_finished); 800b774: 4812 ldr r0, [pc, #72] @ (800b7c0 ) 800b776: f000 f8d3 bl 800b920 break; 800b77a: e013 b.n 800b7a4 case Finished: LED_SetColor(&color_finished); 800b77c: 4810 ldr r0, [pc, #64] @ (800b7c0 ) 800b77e: f000 f8cf bl 800b920 break; 800b782: e00f b.n 800b7a4 case FinishedEVSE: LED_SetColor(&color_finished); 800b784: 480e ldr r0, [pc, #56] @ (800b7c0 ) 800b786: f000 f8cb bl 800b920 break; 800b78a: e00b b.n 800b7a4 case FinishedEV: LED_SetColor(&color_finished); 800b78c: 480c ldr r0, [pc, #48] @ (800b7c0 ) 800b78e: f000 f8c7 bl 800b920 break; 800b792: e007 b.n 800b7a4 case Replugging: LED_SetColor(&color_preparing); 800b794: 4808 ldr r0, [pc, #32] @ (800b7b8 ) 800b796: f000 f8c3 bl 800b920 break; 800b79a: e003 b.n 800b7a4 default: LED_SetColor(&color_unknown); 800b79c: 4804 ldr r0, [pc, #16] @ (800b7b0 ) 800b79e: f000 f8bf bl 800b920 break; 800b7a2: bf00 nop } } 800b7a4: bd80 pop {r7, pc} 800b7a6: bf00 nop 800b7a8: 2000033c .word 0x2000033c 800b7ac: 20000044 .word 0x20000044 800b7b0: 20000008 .word 0x20000008 800b7b4: 20000014 .word 0x20000014 800b7b8: 20000020 .word 0x20000020 800b7bc: 2000002c .word 0x2000002c 800b7c0: 20000038 .word 0x20000038 0800b7c4 : void interpolateColors(RGB_t* color1, RGB_t* color2, uint16_t a, uint16_t b, RGB_t *result) { 800b7c4: b480 push {r7} 800b7c6: b087 sub sp, #28 800b7c8: af00 add r7, sp, #0 800b7ca: 60f8 str r0, [r7, #12] 800b7cc: 60b9 str r1, [r7, #8] 800b7ce: 4611 mov r1, r2 800b7d0: 461a mov r2, r3 800b7d2: 460b mov r3, r1 800b7d4: 80fb strh r3, [r7, #6] 800b7d6: 4613 mov r3, r2 800b7d8: 80bb strh r3, [r7, #4] // Проверяем, чтобы a не выходила за пределы диапазона if (a > b) a = b; 800b7da: 88fa ldrh r2, [r7, #6] 800b7dc: 88bb ldrh r3, [r7, #4] 800b7de: 429a cmp r2, r3 800b7e0: d901 bls.n 800b7e6 800b7e2: 88bb ldrh r3, [r7, #4] 800b7e4: 80fb strh r3, [r7, #6] if(b==0) b = 1; 800b7e6: 88bb ldrh r3, [r7, #4] 800b7e8: 2b00 cmp r3, #0 800b7ea: d101 bne.n 800b7f0 800b7ec: 2301 movs r3, #1 800b7ee: 80bb strh r3, [r7, #4] // Вычисляем коэффициент смешивания в виде целого числа uint16_t t = (a * 255) / b; // t будет от 0 до 255 800b7f0: 88fa ldrh r2, [r7, #6] 800b7f2: 4613 mov r3, r2 800b7f4: 021b lsls r3, r3, #8 800b7f6: 1a9a subs r2, r3, r2 800b7f8: 88bb ldrh r3, [r7, #4] 800b7fa: fb92 f3f3 sdiv r3, r2, r3 800b7fe: 82fb strh r3, [r7, #22] // Линейная интерполяция с использованием целых чисел result->R = (color1->R * (255 - t) + color2->R * t) / 255; 800b800: 68fb ldr r3, [r7, #12] 800b802: 781b ldrb r3, [r3, #0] 800b804: 461a mov r2, r3 800b806: 8afb ldrh r3, [r7, #22] 800b808: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b80c: fb03 f202 mul.w r2, r3, r2 800b810: 68bb ldr r3, [r7, #8] 800b812: 781b ldrb r3, [r3, #0] 800b814: 4619 mov r1, r3 800b816: 8afb ldrh r3, [r7, #22] 800b818: fb01 f303 mul.w r3, r1, r3 800b81c: 4413 add r3, r2 800b81e: 4a20 ldr r2, [pc, #128] @ (800b8a0 ) 800b820: fb82 1203 smull r1, r2, r2, r3 800b824: 441a add r2, r3 800b826: 11d2 asrs r2, r2, #7 800b828: 17db asrs r3, r3, #31 800b82a: 1ad3 subs r3, r2, r3 800b82c: b2da uxtb r2, r3 800b82e: 6a3b ldr r3, [r7, #32] 800b830: 701a strb r2, [r3, #0] result->G = (color1->G * (255 - t) + color2->G * t) / 255; 800b832: 68fb ldr r3, [r7, #12] 800b834: 785b ldrb r3, [r3, #1] 800b836: 461a mov r2, r3 800b838: 8afb ldrh r3, [r7, #22] 800b83a: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b83e: fb03 f202 mul.w r2, r3, r2 800b842: 68bb ldr r3, [r7, #8] 800b844: 785b ldrb r3, [r3, #1] 800b846: 4619 mov r1, r3 800b848: 8afb ldrh r3, [r7, #22] 800b84a: fb01 f303 mul.w r3, r1, r3 800b84e: 4413 add r3, r2 800b850: 4a13 ldr r2, [pc, #76] @ (800b8a0 ) 800b852: fb82 1203 smull r1, r2, r2, r3 800b856: 441a add r2, r3 800b858: 11d2 asrs r2, r2, #7 800b85a: 17db asrs r3, r3, #31 800b85c: 1ad3 subs r3, r2, r3 800b85e: b2da uxtb r2, r3 800b860: 6a3b ldr r3, [r7, #32] 800b862: 705a strb r2, [r3, #1] result->B = (color1->B * (255 - t) + color2->B * t) / 255; 800b864: 68fb ldr r3, [r7, #12] 800b866: 789b ldrb r3, [r3, #2] 800b868: 461a mov r2, r3 800b86a: 8afb ldrh r3, [r7, #22] 800b86c: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b870: fb03 f202 mul.w r2, r3, r2 800b874: 68bb ldr r3, [r7, #8] 800b876: 789b ldrb r3, [r3, #2] 800b878: 4619 mov r1, r3 800b87a: 8afb ldrh r3, [r7, #22] 800b87c: fb01 f303 mul.w r3, r1, r3 800b880: 4413 add r3, r2 800b882: 4a07 ldr r2, [pc, #28] @ (800b8a0 ) 800b884: fb82 1203 smull r1, r2, r2, r3 800b888: 441a add r2, r3 800b88a: 11d2 asrs r2, r2, #7 800b88c: 17db asrs r3, r3, #31 800b88e: 1ad3 subs r3, r2, r3 800b890: b2da uxtb r2, r3 800b892: 6a3b ldr r3, [r7, #32] 800b894: 709a strb r2, [r3, #2] } 800b896: bf00 nop 800b898: 371c adds r7, #28 800b89a: 46bd mov sp, r7 800b89c: bc80 pop {r7} 800b89e: 4770 bx lr 800b8a0: 80808081 .word 0x80808081 0800b8a4 : void RGB_SetColor(RGB_t *color){ 800b8a4: b480 push {r7} 800b8a6: b083 sub sp, #12 800b8a8: af00 add r7, sp, #0 800b8aa: 6078 str r0, [r7, #4] htim4.Instance->CCR2 = color->R * 100 / 255; 800b8ac: 687b ldr r3, [r7, #4] 800b8ae: 781b ldrb r3, [r3, #0] 800b8b0: 461a mov r2, r3 800b8b2: 2364 movs r3, #100 @ 0x64 800b8b4: fb02 f303 mul.w r3, r2, r3 800b8b8: 4a17 ldr r2, [pc, #92] @ (800b918 ) 800b8ba: fb82 1203 smull r1, r2, r2, r3 800b8be: 441a add r2, r3 800b8c0: 11d2 asrs r2, r2, #7 800b8c2: 17db asrs r3, r3, #31 800b8c4: 1ad2 subs r2, r2, r3 800b8c6: 4b15 ldr r3, [pc, #84] @ (800b91c ) 800b8c8: 681b ldr r3, [r3, #0] 800b8ca: 639a str r2, [r3, #56] @ 0x38 htim4.Instance->CCR3 = color->G * 100 / 255; 800b8cc: 687b ldr r3, [r7, #4] 800b8ce: 785b ldrb r3, [r3, #1] 800b8d0: 461a mov r2, r3 800b8d2: 2364 movs r3, #100 @ 0x64 800b8d4: fb02 f303 mul.w r3, r2, r3 800b8d8: 4a0f ldr r2, [pc, #60] @ (800b918 ) 800b8da: fb82 1203 smull r1, r2, r2, r3 800b8de: 441a add r2, r3 800b8e0: 11d2 asrs r2, r2, #7 800b8e2: 17db asrs r3, r3, #31 800b8e4: 1ad2 subs r2, r2, r3 800b8e6: 4b0d ldr r3, [pc, #52] @ (800b91c ) 800b8e8: 681b ldr r3, [r3, #0] 800b8ea: 63da str r2, [r3, #60] @ 0x3c htim4.Instance->CCR4 = color->B * 100 / 255; 800b8ec: 687b ldr r3, [r7, #4] 800b8ee: 789b ldrb r3, [r3, #2] 800b8f0: 461a mov r2, r3 800b8f2: 2364 movs r3, #100 @ 0x64 800b8f4: fb02 f303 mul.w r3, r2, r3 800b8f8: 4a07 ldr r2, [pc, #28] @ (800b918 ) 800b8fa: fb82 1203 smull r1, r2, r2, r3 800b8fe: 441a add r2, r3 800b900: 11d2 asrs r2, r2, #7 800b902: 17db asrs r3, r3, #31 800b904: 1ad2 subs r2, r2, r3 800b906: 4b05 ldr r3, [pc, #20] @ (800b91c ) 800b908: 681b ldr r3, [r3, #0] 800b90a: 641a str r2, [r3, #64] @ 0x40 } 800b90c: bf00 nop 800b90e: 370c adds r7, #12 800b910: 46bd mov sp, r7 800b912: bc80 pop {r7} 800b914: 4770 bx lr 800b916: bf00 nop 800b918: 80808081 .word 0x80808081 800b91c: 20001074 .word 0x20001074 0800b920 : void LED_SetColor(RGB_Cycle_t *color){ 800b920: b480 push {r7} 800b922: b083 sub sp, #12 800b924: af00 add r7, sp, #0 800b926: 6078 str r0, [r7, #4] memcpy(&LED_Cycle, color, sizeof(RGB_Cycle_t)); 800b928: 4b05 ldr r3, [pc, #20] @ (800b940 ) 800b92a: 687a ldr r2, [r7, #4] 800b92c: 6810 ldr r0, [r2, #0] 800b92e: 6851 ldr r1, [r2, #4] 800b930: c303 stmia r3!, {r0, r1} 800b932: 8912 ldrh r2, [r2, #8] 800b934: 801a strh r2, [r3, #0] } 800b936: bf00 nop 800b938: 370c adds r7, #12 800b93a: 46bd mov sp, r7 800b93c: bc80 pop {r7} 800b93e: 4770 bx lr 800b940: 200008ec .word 0x200008ec 0800b944 : void LED_Init(){ 800b944: b580 push {r7, lr} 800b946: b082 sub sp, #8 800b948: af00 add r7, sp, #0 RGB_t color = {.R=0, .G=0, .B=0}; 800b94a: 2300 movs r3, #0 800b94c: 713b strb r3, [r7, #4] 800b94e: 2300 movs r3, #0 800b950: 717b strb r3, [r7, #5] 800b952: 2300 movs r3, #0 800b954: 71bb strb r3, [r7, #6] HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_2); 800b956: 2104 movs r1, #4 800b958: 4809 ldr r0, [pc, #36] @ (800b980 ) 800b95a: f005 fc45 bl 80111e8 HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); 800b95e: 2108 movs r1, #8 800b960: 4807 ldr r0, [pc, #28] @ (800b980 ) 800b962: f005 fc41 bl 80111e8 HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4); 800b966: 210c movs r1, #12 800b968: 4805 ldr r0, [pc, #20] @ (800b980 ) 800b96a: f005 fc3d bl 80111e8 RGB_SetColor(&color); 800b96e: 1d3b adds r3, r7, #4 800b970: 4618 mov r0, r3 800b972: f7ff ff97 bl 800b8a4 } 800b976: bf00 nop 800b978: 3708 adds r7, #8 800b97a: 46bd mov sp, r7 800b97c: bd80 pop {r7, pc} 800b97e: bf00 nop 800b980: 20001074 .word 0x20001074 0800b984 : // } // } // } // } void LED_Task(){ 800b984: b580 push {r7, lr} 800b986: b082 sub sp, #8 800b988: af02 add r7, sp, #8 static uint32_t led_tick; if((HAL_GetTick() - led_tick) > 20){ 800b98a: f002 f8f1 bl 800db70 800b98e: 4602 mov r2, r0 800b990: 4b46 ldr r3, [pc, #280] @ (800baac ) 800b992: 681b ldr r3, [r3, #0] 800b994: 1ad3 subs r3, r2, r3 800b996: 2b14 cmp r3, #20 800b998: f240 8085 bls.w 800baa6 led_tick = HAL_GetTick(); 800b99c: f002 f8e8 bl 800db70 800b9a0: 4603 mov r3, r0 800b9a2: 4a42 ldr r2, [pc, #264] @ (800baac ) 800b9a4: 6013 str r3, [r2, #0] LED_State.tick++; 800b9a6: 4b42 ldr r3, [pc, #264] @ (800bab0 ) 800b9a8: 885b ldrh r3, [r3, #2] 800b9aa: 3301 adds r3, #1 800b9ac: b29a uxth r2, r3 800b9ae: 4b40 ldr r3, [pc, #256] @ (800bab0 ) 800b9b0: 805a strh r2, [r3, #2] // LED_PhaseSync(led_n); switch(LED_State.state){ 800b9b2: 4b3f ldr r3, [pc, #252] @ (800bab0 ) 800b9b4: 781b ldrb r3, [r3, #0] 800b9b6: 2b03 cmp r3, #3 800b9b8: d867 bhi.n 800ba8a 800b9ba: a201 add r2, pc, #4 @ (adr r2, 800b9c0 ) 800b9bc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b9c0: 0800b9d1 .word 0x0800b9d1 800b9c4: 0800ba03 .word 0x0800ba03 800b9c8: 0800ba2f .word 0x0800ba2f 800b9cc: 0800ba61 .word 0x0800ba61 case LED_RISING: interpolateColors(&LED_Cycle.Color2, &LED_Cycle.Color1, LED_State.tick, LED_Cycle.Tr, &LED_State.color); 800b9d0: 4b37 ldr r3, [pc, #220] @ (800bab0 ) 800b9d2: 885a ldrh r2, [r3, #2] 800b9d4: 4b37 ldr r3, [pc, #220] @ (800bab4 ) 800b9d6: 78db ldrb r3, [r3, #3] 800b9d8: 4619 mov r1, r3 800b9da: 4b37 ldr r3, [pc, #220] @ (800bab8 ) 800b9dc: 9300 str r3, [sp, #0] 800b9de: 460b mov r3, r1 800b9e0: 4934 ldr r1, [pc, #208] @ (800bab4 ) 800b9e2: 4836 ldr r0, [pc, #216] @ (800babc ) 800b9e4: f7ff feee bl 800b7c4 if(LED_State.tick>LED_Cycle.Tr){ 800b9e8: 4b31 ldr r3, [pc, #196] @ (800bab0 ) 800b9ea: 885b ldrh r3, [r3, #2] 800b9ec: 4a31 ldr r2, [pc, #196] @ (800bab4 ) 800b9ee: 78d2 ldrb r2, [r2, #3] 800b9f0: 4293 cmp r3, r2 800b9f2: d94e bls.n 800ba92 LED_State.state = LED_HIGH; 800b9f4: 4b2e ldr r3, [pc, #184] @ (800bab0 ) 800b9f6: 2201 movs r2, #1 800b9f8: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b9fa: 4b2d ldr r3, [pc, #180] @ (800bab0 ) 800b9fc: 2200 movs r2, #0 800b9fe: 805a strh r2, [r3, #2] } break; 800ba00: e047 b.n 800ba92 case LED_HIGH: memcpy(&LED_State.color, &LED_Cycle.Color1, sizeof(RGB_t)); 800ba02: 4b2b ldr r3, [pc, #172] @ (800bab0 ) 800ba04: 4a2b ldr r2, [pc, #172] @ (800bab4 ) 800ba06: 3304 adds r3, #4 800ba08: 6812 ldr r2, [r2, #0] 800ba0a: 4611 mov r1, r2 800ba0c: 8019 strh r1, [r3, #0] 800ba0e: 3302 adds r3, #2 800ba10: 0c12 lsrs r2, r2, #16 800ba12: 701a strb r2, [r3, #0] if(LED_State.tick>LED_Cycle.Th){ 800ba14: 4b26 ldr r3, [pc, #152] @ (800bab0 ) 800ba16: 885b ldrh r3, [r3, #2] 800ba18: 4a26 ldr r2, [pc, #152] @ (800bab4 ) 800ba1a: 7912 ldrb r2, [r2, #4] 800ba1c: 4293 cmp r3, r2 800ba1e: d93a bls.n 800ba96 LED_State.state = LED_FALLING; 800ba20: 4b23 ldr r3, [pc, #140] @ (800bab0 ) 800ba22: 2202 movs r2, #2 800ba24: 701a strb r2, [r3, #0] LED_State.tick = 0; 800ba26: 4b22 ldr r3, [pc, #136] @ (800bab0 ) 800ba28: 2200 movs r2, #0 800ba2a: 805a strh r2, [r3, #2] } break; 800ba2c: e033 b.n 800ba96 case LED_FALLING: interpolateColors(&LED_Cycle.Color1, &LED_Cycle.Color2, LED_State.tick, LED_Cycle.Tf, &LED_State.color); 800ba2e: 4b20 ldr r3, [pc, #128] @ (800bab0 ) 800ba30: 885a ldrh r2, [r3, #2] 800ba32: 4b20 ldr r3, [pc, #128] @ (800bab4 ) 800ba34: 795b ldrb r3, [r3, #5] 800ba36: 4619 mov r1, r3 800ba38: 4b1f ldr r3, [pc, #124] @ (800bab8 ) 800ba3a: 9300 str r3, [sp, #0] 800ba3c: 460b mov r3, r1 800ba3e: 491f ldr r1, [pc, #124] @ (800babc ) 800ba40: 481c ldr r0, [pc, #112] @ (800bab4 ) 800ba42: f7ff febf bl 800b7c4 if(LED_State.tick>LED_Cycle.Tf){ 800ba46: 4b1a ldr r3, [pc, #104] @ (800bab0 ) 800ba48: 885b ldrh r3, [r3, #2] 800ba4a: 4a1a ldr r2, [pc, #104] @ (800bab4 ) 800ba4c: 7952 ldrb r2, [r2, #5] 800ba4e: 4293 cmp r3, r2 800ba50: d923 bls.n 800ba9a LED_State.state = LED_LOW; 800ba52: 4b17 ldr r3, [pc, #92] @ (800bab0 ) 800ba54: 2203 movs r2, #3 800ba56: 701a strb r2, [r3, #0] LED_State.tick = 0; 800ba58: 4b15 ldr r3, [pc, #84] @ (800bab0 ) 800ba5a: 2200 movs r2, #0 800ba5c: 805a strh r2, [r3, #2] } break; 800ba5e: e01c b.n 800ba9a case LED_LOW: memcpy(&LED_State.color, &LED_Cycle.Color2, sizeof(RGB_t)); 800ba60: 4b13 ldr r3, [pc, #76] @ (800bab0 ) 800ba62: 4a14 ldr r2, [pc, #80] @ (800bab4 ) 800ba64: 3304 adds r3, #4 800ba66: 3207 adds r2, #7 800ba68: 8811 ldrh r1, [r2, #0] 800ba6a: 7892 ldrb r2, [r2, #2] 800ba6c: 8019 strh r1, [r3, #0] 800ba6e: 709a strb r2, [r3, #2] if(LED_State.tick>LED_Cycle.Tl){ 800ba70: 4b0f ldr r3, [pc, #60] @ (800bab0 ) 800ba72: 885b ldrh r3, [r3, #2] 800ba74: 4a0f ldr r2, [pc, #60] @ (800bab4 ) 800ba76: 7992 ldrb r2, [r2, #6] 800ba78: 4293 cmp r3, r2 800ba7a: d910 bls.n 800ba9e LED_State.state = LED_RISING; 800ba7c: 4b0c ldr r3, [pc, #48] @ (800bab0 ) 800ba7e: 2200 movs r2, #0 800ba80: 701a strb r2, [r3, #0] LED_State.tick = 0; 800ba82: 4b0b ldr r3, [pc, #44] @ (800bab0 ) 800ba84: 2200 movs r2, #0 800ba86: 805a strh r2, [r3, #2] } break; 800ba88: e009 b.n 800ba9e default: LED_State.state = LED_RISING; 800ba8a: 4b09 ldr r3, [pc, #36] @ (800bab0 ) 800ba8c: 2200 movs r2, #0 800ba8e: 701a strb r2, [r3, #0] 800ba90: e006 b.n 800baa0 break; 800ba92: bf00 nop 800ba94: e004 b.n 800baa0 break; 800ba96: bf00 nop 800ba98: e002 b.n 800baa0 break; 800ba9a: bf00 nop 800ba9c: e000 b.n 800baa0 break; 800ba9e: bf00 nop } RGB_SetColor(&LED_State.color); 800baa0: 4805 ldr r0, [pc, #20] @ (800bab8 ) 800baa2: f7ff feff bl 800b8a4 } } 800baa6: bf00 nop 800baa8: 46bd mov sp, r7 800baaa: bd80 pop {r7, pc} 800baac: 200008f8 .word 0x200008f8 800bab0: 200008e4 .word 0x200008e4 800bab4: 200008ec .word 0x200008ec 800bab8: 200008e8 .word 0x200008e8 800babc: 200008f3 .word 0x200008f3 0800bac0 : RTC_HandleTypeDef hrtc; /* RTC init function */ void MX_RTC_Init(void) { 800bac0: b580 push {r7, lr} 800bac2: af00 add r7, sp, #0 /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 800bac4: 4b0a ldr r3, [pc, #40] @ (800baf0 ) 800bac6: 4a0b ldr r2, [pc, #44] @ (800baf4 ) 800bac8: 601a str r2, [r3, #0] hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; 800baca: 4b09 ldr r3, [pc, #36] @ (800baf0 ) 800bacc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800bad0: 605a str r2, [r3, #4] hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; 800bad2: 4b07 ldr r3, [pc, #28] @ (800baf0 ) 800bad4: f44f 7280 mov.w r2, #256 @ 0x100 800bad8: 609a str r2, [r3, #8] if (HAL_RTC_Init(&hrtc) != HAL_OK) 800bada: 4805 ldr r0, [pc, #20] @ (800baf0 ) 800badc: f005 f8de bl 8010c9c 800bae0: 4603 mov r3, r0 800bae2: 2b00 cmp r3, #0 800bae4: d001 beq.n 800baea { Error_Handler(); 800bae6: f7ff f859 bl 800ab9c } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 800baea: bf00 nop 800baec: bd80 pop {r7, pc} 800baee: bf00 nop 800baf0: 200008fc .word 0x200008fc 800baf4: 40002800 .word 0x40002800 0800baf8 : void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) { 800baf8: b580 push {r7, lr} 800bafa: b084 sub sp, #16 800bafc: af00 add r7, sp, #0 800bafe: 6078 str r0, [r7, #4] if(rtcHandle->Instance==RTC) 800bb00: 687b ldr r3, [r7, #4] 800bb02: 681b ldr r3, [r3, #0] 800bb04: 4a0b ldr r2, [pc, #44] @ (800bb34 ) 800bb06: 4293 cmp r3, r2 800bb08: d110 bne.n 800bb2c { /* USER CODE BEGIN RTC_MspInit 0 */ /* USER CODE END RTC_MspInit 0 */ HAL_PWR_EnableBkUpAccess(); 800bb0a: f004 f85b bl 800fbc4 /* Enable BKP CLK enable for backup registers */ __HAL_RCC_BKP_CLK_ENABLE(); 800bb0e: 4b0a ldr r3, [pc, #40] @ (800bb38 ) 800bb10: 69db ldr r3, [r3, #28] 800bb12: 4a09 ldr r2, [pc, #36] @ (800bb38 ) 800bb14: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800bb18: 61d3 str r3, [r2, #28] 800bb1a: 4b07 ldr r3, [pc, #28] @ (800bb38 ) 800bb1c: 69db ldr r3, [r3, #28] 800bb1e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800bb22: 60fb str r3, [r7, #12] 800bb24: 68fb ldr r3, [r7, #12] /* RTC clock enable */ __HAL_RCC_RTC_ENABLE(); 800bb26: 4b05 ldr r3, [pc, #20] @ (800bb3c ) 800bb28: 2201 movs r2, #1 800bb2a: 601a str r2, [r3, #0] /* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE END RTC_MspInit 1 */ } } 800bb2c: bf00 nop 800bb2e: 3710 adds r7, #16 800bb30: 46bd mov sp, r7 800bb32: bd80 pop {r7, pc} 800bb34: 40002800 .word 0x40002800 800bb38: 40021000 .word 0x40021000 800bb3c: 4242043c .word 0x4242043c 0800bb40 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 800bb40: b480 push {r7} 800bb42: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 800bb44: f3bf 8f4f dsb sy } 800bb48: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800bb4a: 4b06 ldr r3, [pc, #24] @ (800bb64 <__NVIC_SystemReset+0x24>) 800bb4c: 68db ldr r3, [r3, #12] 800bb4e: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800bb52: 4904 ldr r1, [pc, #16] @ (800bb64 <__NVIC_SystemReset+0x24>) 800bb54: 4b04 ldr r3, [pc, #16] @ (800bb68 <__NVIC_SystemReset+0x28>) 800bb56: 4313 orrs r3, r2 800bb58: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800bb5a: f3bf 8f4f dsb sy } 800bb5e: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 800bb60: bf00 nop 800bb62: e7fd b.n 800bb60 <__NVIC_SystemReset+0x20> 800bb64: e000ed00 .word 0xe000ed00 800bb68: 05fa0004 .word 0x05fa0004 0800bb6c : CONN_State_t CCS_EvseState; CCS_ConnectorState_t CCS_ConnectorState = CCS_UNPLUGGED; static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len); void CCS_RxEventCallback(UART_HandleTypeDef *huart, uint16_t size) { 800bb6c: b580 push {r7, lr} 800bb6e: b082 sub sp, #8 800bb70: af00 add r7, sp, #0 800bb72: 6078 str r0, [r7, #4] 800bb74: 460b mov r3, r1 800bb76: 807b strh r3, [r7, #2] if (huart != &huart3) { 800bb78: 687b ldr r3, [r7, #4] 800bb7a: 4a0a ldr r2, [pc, #40] @ (800bba4 ) 800bb7c: 4293 cmp r3, r2 800bb7e: d10c bne.n 800bb9a return; } if (size > 0 && size <= sizeof(rx_buffer)) { 800bb80: 887b ldrh r3, [r7, #2] 800bb82: 2b00 cmp r3, #0 800bb84: d00a beq.n 800bb9c 800bb86: 887b ldrh r3, [r7, #2] 800bb88: f5b3 7f80 cmp.w r3, #256 @ 0x100 800bb8c: d806 bhi.n 800bb9c process_received_packet(rx_buffer, size); 800bb8e: 887b ldrh r3, [r7, #2] 800bb90: 4619 mov r1, r3 800bb92: 4805 ldr r0, [pc, #20] @ (800bba8 ) 800bb94: f000 fce4 bl 800c560 800bb98: e000 b.n 800bb9c return; 800bb9a: bf00 nop } } 800bb9c: 3708 adds r7, #8 800bb9e: 46bd mov sp, r7 800bba0: bd80 pop {r7, pc} 800bba2: bf00 nop 800bba4: 20001194 .word 0x20001194 800bba8: 20000934 .word 0x20000934 0800bbac : void CCS_SerialLoop(void) { 800bbac: b580 push {r7, lr} 800bbae: af00 add r7, sp, #0 static uint32_t replug_tick = 0; static uint32_t replug_watchdog_tick = 0; static uint32_t replug_watchdog1_tick = 0; static uint32_t last_state_sent = 0; if (HAL_UART_GetState(&huart3) == HAL_UART_STATE_READY) { 800bbb0: 48a7 ldr r0, [pc, #668] @ (800be50 ) 800bbb2: f006 fec2 bl 801293a 800bbb6: 4603 mov r3, r0 800bbb8: 2b20 cmp r3, #32 800bbba: d105 bne.n 800bbc8 (void)HAL_UARTEx_ReceiveToIdle_IT(&huart3, rx_buffer, sizeof(rx_buffer)); 800bbbc: f44f 7280 mov.w r2, #256 @ 0x100 800bbc0: 49a4 ldr r1, [pc, #656] @ (800be54 ) 800bbc2: 48a3 ldr r0, [pc, #652] @ (800be50 ) 800bbc4: f006 fa9a bl 80120fc } /* Read CP once per loop and use buffered value below. */ cp_state_buffer = CP_GetState(); 800bbc8: f7fe fb96 bl 800a2f8 800bbcc: 4603 mov r3, r0 800bbce: 461a mov r2, r3 800bbd0: 4ba1 ldr r3, [pc, #644] @ (800be58 ) 800bbd2: 701a strb r2, [r3, #0] if (CONN.connControl != CMD_NONE) { 800bbd4: 4ba1 ldr r3, [pc, #644] @ (800be5c ) 800bbd6: 781b ldrb r3, [r3, #0] 800bbd8: 2b00 cmp r3, #0 800bbda: d003 beq.n 800bbe4 last_cmd = CONN.connControl; 800bbdc: 4b9f ldr r3, [pc, #636] @ (800be5c ) 800bbde: 781a ldrb r2, [r3, #0] 800bbe0: 4b9f ldr r3, [pc, #636] @ (800be60 ) 800bbe2: 701a strb r2, [r3, #0] } if((HAL_GetTick() - last_cmd_sent) > CMD_INTERVAL){ 800bbe4: f001 ffc4 bl 800db70 800bbe8: 4602 mov r2, r0 800bbea: 4b9e ldr r3, [pc, #632] @ (800be64 ) 800bbec: 681b ldr r3, [r3, #0] 800bbee: 1ad3 subs r3, r2, r3 800bbf0: 2b0a cmp r3, #10 800bbf2: d953 bls.n 800bc9c if ((HAL_GetTick() - last_state_sent) >= 200) { 800bbf4: f001 ffbc bl 800db70 800bbf8: 4602 mov r2, r0 800bbfa: 4b9b ldr r3, [pc, #620] @ (800be68 ) 800bbfc: 681b ldr r3, [r3, #0] 800bbfe: 1ad3 subs r3, r2, r3 800bc00: 2bc7 cmp r3, #199 @ 0xc7 800bc02: d906 bls.n 800bc12 send_state(); 800bc04: f000 fb1a bl 800c23c last_state_sent = HAL_GetTick(); 800bc08: f001 ffb2 bl 800db70 800bc0c: 4603 mov r3, r0 800bc0e: 4a96 ldr r2, [pc, #600] @ (800be68 ) 800bc10: 6013 str r3, [r2, #0] } if (ESTOP) { 800bc12: 4b96 ldr r3, [pc, #600] @ (800be6c ) 800bc14: 781b ldrb r3, [r3, #0] 800bc16: 2b00 cmp r3, #0 800bc18: d008 beq.n 800bc2c log_printf(LOG_ERR, "ESTOP triggered\n"); 800bc1a: 4995 ldr r1, [pc, #596] @ (800be70 ) 800bc1c: 2004 movs r0, #4 800bc1e: f7fe fcfd bl 800a61c CCS_SendEmergencyStop(); 800bc22: f000 faac bl 800c17e ESTOP = 0; 800bc26: 4b91 ldr r3, [pc, #580] @ (800be6c ) 800bc28: 2200 movs r2, #0 800bc2a: 701a strb r2, [r3, #0] } if (((CONN.connControl == CMD_STOP) || 800bc2c: 4b8b ldr r3, [pc, #556] @ (800be5c ) 800bc2e: 781b ldrb r3, [r3, #0] 800bc30: 2b01 cmp r3, #1 800bc32: d003 beq.n 800bc3c (CONN.chargingError != CONN_NO_ERROR)) && 800bc34: 4b89 ldr r3, [pc, #548] @ (800be5c ) 800bc36: 7f5b ldrb r3, [r3, #29] if (((CONN.connControl == CMD_STOP) || 800bc38: 2b00 cmp r3, #0 800bc3a: d013 beq.n 800bc64 ((HAL_GetTick() - last_stop_sent) > 1000)) { 800bc3c: f001 ff98 bl 800db70 800bc40: 4602 mov r2, r0 800bc42: 4b8c ldr r3, [pc, #560] @ (800be74 ) 800bc44: 681b ldr r3, [r3, #0] 800bc46: 1ad3 subs r3, r2, r3 (CONN.chargingError != CONN_NO_ERROR)) && 800bc48: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bc4c: d90a bls.n 800bc64 last_stop_sent = HAL_GetTick(); 800bc4e: f001 ff8f bl 800db70 800bc52: 4603 mov r3, r0 800bc54: 4a87 ldr r2, [pc, #540] @ (800be74 ) 800bc56: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "Stopping charging...\n"); 800bc58: 4987 ldr r1, [pc, #540] @ (800be78 ) 800bc5a: 2005 movs r0, #5 800bc5c: f7fe fcde bl 800a61c CCS_SendEmergencyStop(); 800bc60: f000 fa8d bl 800c17e } if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800bc64: 4b85 ldr r3, [pc, #532] @ (800be7c ) 800bc66: 781b ldrb r3, [r3, #0] 800bc68: 2b0c cmp r3, #12 800bc6a: d003 beq.n 800bc74 800bc6c: 4b83 ldr r3, [pc, #524] @ (800be7c ) 800bc6e: 781b ldrb r3, [r3, #0] 800bc70: 2b0b cmp r3, #11 800bc72: d113 bne.n 800bc9c ((HAL_GetTick() - last_stop_sent) > 1000)) { 800bc74: f001 ff7c bl 800db70 800bc78: 4602 mov r2, r0 800bc7a: 4b7e ldr r3, [pc, #504] @ (800be74 ) 800bc7c: 681b ldr r3, [r3, #0] 800bc7e: 1ad3 subs r3, r2, r3 if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800bc80: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bc84: d90a bls.n 800bc9c last_stop_sent = HAL_GetTick(); 800bc86: f001 ff73 bl 800db70 800bc8a: 4603 mov r3, r0 800bc8c: 4a79 ldr r2, [pc, #484] @ (800be74 ) 800bc8e: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "FinishedEV, stopping...\n"); 800bc90: 497b ldr r1, [pc, #492] @ (800be80 ) 800bc92: 2005 movs r0, #5 800bc94: f7fe fcc2 bl 800a61c CCS_SendEmergencyStop(); 800bc98: f000 fa71 bl 800c17e } (void)replug_watchdog_tick; (void)replug_watchdog1_tick; if (!config_initialized) { 800bc9c: 4b79 ldr r3, [pc, #484] @ (800be84 ) 800bc9e: 781b ldrb r3, [r3, #0] 800bca0: 2b00 cmp r3, #0 800bca2: d107 bne.n 800bcb4 // Keep connector in Unknown until host sends valid SET_CONFIG. RELAY_Write(RELAY_CP, 1); 800bca4: 2101 movs r1, #1 800bca6: 2005 movs r0, #5 800bca8: f7fd fcd0 bl 800964c CONN_SetState(Unknown); 800bcac: 2000 movs r0, #0 800bcae: f7fe f8d1 bl 8009e54 800bcb2: e0fc b.n 800beae } else { switch(CCS_ConnectorState){ 800bcb4: 4b74 ldr r3, [pc, #464] @ (800be88 ) 800bcb6: 781b ldrb r3, [r3, #0] 800bcb8: 2b04 cmp r3, #4 800bcba: f200 80f8 bhi.w 800beae 800bcbe: a201 add r2, pc, #4 @ (adr r2, 800bcc4 ) 800bcc0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800bcc4: 0800bcd9 .word 0x0800bcd9 800bcc8: 0800bcf9 .word 0x0800bcf9 800bccc: 0800bd3d .word 0x0800bd3d 800bcd0: 0800bd79 .word 0x0800bd79 800bcd4: 0800bdc9 .word 0x0800bdc9 case CCS_DISABLED: RELAY_Write(RELAY_CP, 0); 800bcd8: 2100 movs r1, #0 800bcda: 2005 movs r0, #5 800bcdc: f7fd fcb6 bl 800964c CONN_SetState(Disabled); 800bce0: 2002 movs r0, #2 800bce2: f7fe f8b7 bl 8009e54 if (CONN.chargingError == CONN_NO_ERROR){ 800bce6: 4b5d ldr r3, [pc, #372] @ (800be5c ) 800bce8: 7f5b ldrb r3, [r3, #29] 800bcea: 2b00 cmp r3, #0 800bcec: f040 80a7 bne.w 800be3e CCS_ConnectorState = CCS_UNPLUGGED; 800bcf0: 4b65 ldr r3, [pc, #404] @ (800be88 ) 800bcf2: 2201 movs r2, #1 800bcf4: 701a strb r2, [r3, #0] } break; 800bcf6: e0a2 b.n 800be3e case CCS_UNPLUGGED: RELAY_Write(RELAY_CP, 1); 800bcf8: 2101 movs r1, #1 800bcfa: 2005 movs r0, #5 800bcfc: f7fd fca6 bl 800964c CONN_SetState(Unplugged); 800bd00: 2001 movs r0, #1 800bd02: f7fe f8a7 bl 8009e54 if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || (cp_state_buffer == EV_STATE_C_CONN_ACTIVE)){ 800bd06: 4b54 ldr r3, [pc, #336] @ (800be58 ) 800bd08: 781b ldrb r3, [r3, #0] 800bd0a: 2b01 cmp r3, #1 800bd0c: d003 beq.n 800bd16 800bd0e: 4b52 ldr r3, [pc, #328] @ (800be58 ) 800bd10: 781b ldrb r3, [r3, #0] 800bd12: 2b02 cmp r3, #2 800bd14: d102 bne.n 800bd1c CCS_ConnectorState = CCS_AUTH_REQUIRED; 800bd16: 4b5c ldr r3, [pc, #368] @ (800be88 ) 800bd18: 2202 movs r2, #2 800bd1a: 701a strb r2, [r3, #0] } if (CONN.chargingError != CONN_NO_ERROR){ 800bd1c: 4b4f ldr r3, [pc, #316] @ (800be5c ) 800bd1e: 7f5b ldrb r3, [r3, #29] 800bd20: 2b00 cmp r3, #0 800bd22: f000 808e beq.w 800be42 log_printf(LOG_ERR, "Charging error %d, state -> disabled\n", CONN.chargingError); 800bd26: 4b4d ldr r3, [pc, #308] @ (800be5c ) 800bd28: 7f5b ldrb r3, [r3, #29] 800bd2a: 461a mov r2, r3 800bd2c: 4957 ldr r1, [pc, #348] @ (800be8c ) 800bd2e: 2004 movs r0, #4 800bd30: f7fe fc74 bl 800a61c CCS_ConnectorState = CCS_DISABLED; 800bd34: 4b54 ldr r3, [pc, #336] @ (800be88 ) 800bd36: 2200 movs r2, #0 800bd38: 701a strb r2, [r3, #0] } break; 800bd3a: e082 b.n 800be42 case CCS_AUTH_REQUIRED: RELAY_Write(RELAY_CP, 1); 800bd3c: 2101 movs r1, #1 800bd3e: 2005 movs r0, #5 800bd40: f7fd fc84 bl 800964c CONN_SetState(AuthRequired); 800bd44: 2004 movs r0, #4 800bd46: f7fe f885 bl 8009e54 if(CONN.connControl == CMD_START){ 800bd4a: 4b44 ldr r3, [pc, #272] @ (800be5c ) 800bd4c: 781b ldrb r3, [r3, #0] 800bd4e: 2b02 cmp r3, #2 800bd50: d106 bne.n 800bd60 log_printf(LOG_INFO, "Charging permitted, start charging\n"); 800bd52: 494f ldr r1, [pc, #316] @ (800be90 ) 800bd54: 2007 movs r0, #7 800bd56: f7fe fc61 bl 800a61c CCS_ConnectorState = CCS_CONNECTED; 800bd5a: 4b4b ldr r3, [pc, #300] @ (800be88 ) 800bd5c: 2203 movs r2, #3 800bd5e: 701a strb r2, [r3, #0] } if (cp_state_buffer == EV_STATE_A_IDLE){ 800bd60: 4b3d ldr r3, [pc, #244] @ (800be58 ) 800bd62: 781b ldrb r3, [r3, #0] 800bd64: 2b00 cmp r3, #0 800bd66: d16e bne.n 800be46 log_printf(LOG_INFO, "Car unplugged\n"); 800bd68: 494a ldr r1, [pc, #296] @ (800be94 ) 800bd6a: 2007 movs r0, #7 800bd6c: f7fe fc56 bl 800a61c CCS_ConnectorState = CCS_UNPLUGGED; 800bd70: 4b45 ldr r3, [pc, #276] @ (800be88 ) 800bd72: 2201 movs r2, #1 800bd74: 701a strb r2, [r3, #0] } break; 800bd76: e066 b.n 800be46 case CCS_CONNECTED: RELAY_Write(RELAY_CP, 1); 800bd78: 2101 movs r1, #1 800bd7a: 2005 movs r0, #5 800bd7c: f7fd fc66 bl 800964c if(CCS_EvseState < Preparing) { 800bd80: 4b3e ldr r3, [pc, #248] @ (800be7c ) 800bd82: 781b ldrb r3, [r3, #0] 800bd84: 2b02 cmp r3, #2 800bd86: d803 bhi.n 800bd90 CONN_SetState(Preparing); 800bd88: 2003 movs r0, #3 800bd8a: f7fe f863 bl 8009e54 800bd8e: e004 b.n 800bd9a } else { CONN_SetState(CCS_EvseState); 800bd90: 4b3a ldr r3, [pc, #232] @ (800be7c ) 800bd92: 781b ldrb r3, [r3, #0] 800bd94: 4618 mov r0, r3 800bd96: f7fe f85d bl 8009e54 } if (cp_state_buffer == EV_STATE_A_IDLE){ 800bd9a: 4b2f ldr r3, [pc, #188] @ (800be58 ) 800bd9c: 781b ldrb r3, [r3, #0] 800bd9e: 2b00 cmp r3, #0 800bda0: d106 bne.n 800bdb0 log_printf(LOG_INFO, "Car unplugged\n"); 800bda2: 493c ldr r1, [pc, #240] @ (800be94 ) 800bda4: 2007 movs r0, #7 800bda6: f7fe fc39 bl 800a61c CCS_ConnectorState = CCS_UNPLUGGED; 800bdaa: 4b37 ldr r3, [pc, #220] @ (800be88 ) 800bdac: 2201 movs r2, #1 800bdae: 701a strb r2, [r3, #0] } if(REPLUG > 0){ 800bdb0: 4b39 ldr r3, [pc, #228] @ (800be98 ) 800bdb2: 781b ldrb r3, [r3, #0] 800bdb4: 2b00 cmp r3, #0 800bdb6: d048 beq.n 800be4a log_printf(LOG_INFO, "Replugging...\n"); 800bdb8: 4938 ldr r1, [pc, #224] @ (800be9c ) 800bdba: 2007 movs r0, #7 800bdbc: f7fe fc2e bl 800a61c CCS_ConnectorState = CCS_REPLUGGING; 800bdc0: 4b31 ldr r3, [pc, #196] @ (800be88 ) 800bdc2: 2204 movs r2, #4 800bdc4: 701a strb r2, [r3, #0] } break; 800bdc6: e040 b.n 800be4a case CCS_REPLUGGING: RELAY_Write(RELAY_CP, 0); 800bdc8: 2100 movs r1, #0 800bdca: 2005 movs r0, #5 800bdcc: f7fd fc3e bl 800964c CONN_SetState(Replugging); 800bdd0: 200d movs r0, #13 800bdd2: f7fe f83f bl 8009e54 if((HAL_GetTick() - replug_tick) > 1000){ 800bdd6: f001 fecb bl 800db70 800bdda: 4602 mov r2, r0 800bddc: 4b30 ldr r3, [pc, #192] @ (800bea0 ) 800bdde: 681b ldr r3, [r3, #0] 800bde0: 1ad3 subs r3, r2, r3 800bde2: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bde6: d91a bls.n 800be1e replug_tick = HAL_GetTick(); 800bde8: f001 fec2 bl 800db70 800bdec: 4603 mov r3, r0 800bdee: 4a2c ldr r2, [pc, #176] @ (800bea0 ) 800bdf0: 6013 str r3, [r2, #0] if(REPLUG > 0){ 800bdf2: 4b29 ldr r3, [pc, #164] @ (800be98 ) 800bdf4: 781b ldrb r3, [r3, #0] 800bdf6: 2b00 cmp r3, #0 800bdf8: d00a beq.n 800be10 if (REPLUG != 0xFF) REPLUG--; 800bdfa: 4b27 ldr r3, [pc, #156] @ (800be98 ) 800bdfc: 781b ldrb r3, [r3, #0] 800bdfe: 2bff cmp r3, #255 @ 0xff 800be00: d00d beq.n 800be1e 800be02: 4b25 ldr r3, [pc, #148] @ (800be98 ) 800be04: 781b ldrb r3, [r3, #0] 800be06: 3b01 subs r3, #1 800be08: b2da uxtb r2, r3 800be0a: 4b23 ldr r3, [pc, #140] @ (800be98 ) 800be0c: 701a strb r2, [r3, #0] 800be0e: e006 b.n 800be1e } else { log_printf(LOG_INFO, "Replugging finished, but car unplugged\n"); 800be10: 4924 ldr r1, [pc, #144] @ (800bea4 ) 800be12: 2007 movs r0, #7 800be14: f7fe fc02 bl 800a61c CCS_ConnectorState = CCS_UNPLUGGED; 800be18: 4b1b ldr r3, [pc, #108] @ (800be88 ) 800be1a: 2201 movs r2, #1 800be1c: 701a strb r2, [r3, #0] } } if(REPLUG == 0){ 800be1e: 4b1e ldr r3, [pc, #120] @ (800be98 ) 800be20: 781b ldrb r3, [r3, #0] 800be22: 2b00 cmp r3, #0 800be24: d142 bne.n 800beac if(cp_state_buffer == EV_STATE_B_CONN_PREP){ 800be26: 4b0c ldr r3, [pc, #48] @ (800be58 ) 800be28: 781b ldrb r3, [r3, #0] 800be2a: 2b01 cmp r3, #1 800be2c: d13e bne.n 800beac log_printf(LOG_INFO, "Replugging finished, car plugged, state -> auth required\n"); 800be2e: 491e ldr r1, [pc, #120] @ (800bea8 ) 800be30: 2007 movs r0, #7 800be32: f7fe fbf3 bl 800a61c CCS_ConnectorState = CCS_AUTH_REQUIRED; 800be36: 4b14 ldr r3, [pc, #80] @ (800be88 ) 800be38: 2202 movs r2, #2 800be3a: 701a strb r2, [r3, #0] } } break; 800be3c: e036 b.n 800beac break; 800be3e: bf00 nop 800be40: e035 b.n 800beae break; 800be42: bf00 nop 800be44: e033 b.n 800beae break; 800be46: bf00 nop 800be48: e031 b.n 800beae break; 800be4a: bf00 nop 800be4c: e02f b.n 800beae 800be4e: bf00 nop 800be50: 20001194 .word 0x20001194 800be54: 20000934 .word 0x20000934 800be58: 2000004f .word 0x2000004f 800be5c: 2000033c .word 0x2000033c 800be60: 20000930 .word 0x20000930 800be64: 20000928 .word 0x20000928 800be68: 20000b94 .word 0x20000b94 800be6c: 20000b34 .word 0x20000b34 800be70: 08015f1c .word 0x08015f1c 800be74: 2000092c .word 0x2000092c 800be78: 08015f30 .word 0x08015f30 800be7c: 20000b90 .word 0x20000b90 800be80: 08015f48 .word 0x08015f48 800be84: 20001026 .word 0x20001026 800be88: 20000050 .word 0x20000050 800be8c: 08015f64 .word 0x08015f64 800be90: 08015f8c .word 0x08015f8c 800be94: 08015fb0 .word 0x08015fb0 800be98: 20000b35 .word 0x20000b35 800be9c: 08015fc0 .word 0x08015fc0 800bea0: 20000b98 .word 0x20000b98 800bea4: 08015fd0 .word 0x08015fd0 800bea8: 08015ff8 .word 0x08015ff8 break; 800beac: bf00 nop } } // If Everest timeout happened, keep safe-state and limit log frequency. // The safe-state must remain until we receive a valid packet from the host. if (everest_timed_out) { 800beae: 4b3f ldr r3, [pc, #252] @ (800bfac ) 800beb0: 781b ldrb r3, [r3, #0] 800beb2: 2b00 cmp r3, #0 800beb4: d01f beq.n 800bef6 if (last_everest_timeout_log_tick == 0 || 800beb6: 4b3e ldr r3, [pc, #248] @ (800bfb0 ) 800beb8: 681b ldr r3, [r3, #0] 800beba: 2b00 cmp r3, #0 800bebc: d008 beq.n 800bed0 (HAL_GetTick() - last_everest_timeout_log_tick) >= EVEREST_TIMEOUT_MS) { 800bebe: f001 fe57 bl 800db70 800bec2: 4602 mov r2, r0 800bec4: 4b3a ldr r3, [pc, #232] @ (800bfb0 ) 800bec6: 681b ldr r3, [r3, #0] 800bec8: 1ad3 subs r3, r2, r3 if (last_everest_timeout_log_tick == 0 || 800beca: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800bece: d308 bcc.n 800bee2 log_printf(LOG_ERR, "Everest timeout\n"); 800bed0: 4938 ldr r1, [pc, #224] @ (800bfb4 ) 800bed2: 2004 movs r0, #4 800bed4: f7fe fba2 bl 800a61c last_everest_timeout_log_tick = HAL_GetTick(); 800bed8: f001 fe4a bl 800db70 800bedc: 4603 mov r3, r0 800bede: 4a34 ldr r2, [pc, #208] @ (800bfb0 ) 800bee0: 6013 str r3, [r2, #0] } CONN.EnableOutput = 0; 800bee2: 4b35 ldr r3, [pc, #212] @ (800bfb8 ) 800bee4: 2200 movs r2, #0 800bee6: 75da strb r2, [r3, #23] CCS_EvseState = Unknown; 800bee8: 4b34 ldr r3, [pc, #208] @ (800bfbc ) 800beea: 2200 movs r2, #0 800beec: 701a strb r2, [r3, #0] CP_SetDuty(100); 800beee: 2064 movs r0, #100 @ 0x64 800bef0: f7fe f9d0 bl 800a294 800bef4: e044 b.n 800bf80 } else if (last_host_seen > 0 && (HAL_GetTick() - last_host_seen) > EVEREST_TIMEOUT_MS) { 800bef6: 4b32 ldr r3, [pc, #200] @ (800bfc0 ) 800bef8: 681b ldr r3, [r3, #0] 800befa: 2b00 cmp r3, #0 800befc: d023 beq.n 800bf46 800befe: f001 fe37 bl 800db70 800bf02: 4602 mov r2, r0 800bf04: 4b2e ldr r3, [pc, #184] @ (800bfc0 ) 800bf06: 681b ldr r3, [r3, #0] 800bf08: 1ad3 subs r3, r2, r3 800bf0a: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800bf0e: d91a bls.n 800bf46 log_printf(LOG_ERR, "Everest timeout\n"); 800bf10: 4928 ldr r1, [pc, #160] @ (800bfb4 ) 800bf12: 2004 movs r0, #4 800bf14: f7fe fb82 bl 800a61c everest_timed_out = 1; 800bf18: 4b24 ldr r3, [pc, #144] @ (800bfac ) 800bf1a: 2201 movs r2, #1 800bf1c: 701a strb r2, [r3, #0] last_host_seen = HAL_GetTick(); // reset after the first timeout 800bf1e: f001 fe27 bl 800db70 800bf22: 4603 mov r3, r0 800bf24: 4a26 ldr r2, [pc, #152] @ (800bfc0 ) 800bf26: 6013 str r3, [r2, #0] last_everest_timeout_log_tick = HAL_GetTick(); 800bf28: f001 fe22 bl 800db70 800bf2c: 4603 mov r3, r0 800bf2e: 4a20 ldr r2, [pc, #128] @ (800bfb0 ) 800bf30: 6013 str r3, [r2, #0] CONN.EnableOutput = 0; 800bf32: 4b21 ldr r3, [pc, #132] @ (800bfb8 ) 800bf34: 2200 movs r2, #0 800bf36: 75da strb r2, [r3, #23] CCS_EvseState = Unknown; 800bf38: 4b20 ldr r3, [pc, #128] @ (800bfbc ) 800bf3a: 2200 movs r2, #0 800bf3c: 701a strb r2, [r3, #0] CP_SetDuty(100); 800bf3e: 2064 movs r0, #100 @ 0x64 800bf40: f7fe f9a8 bl 800a294 800bf44: e01c b.n 800bf80 } else { if (last_cmd == CMD_STOP) { 800bf46: 4b1f ldr r3, [pc, #124] @ (800bfc4 ) 800bf48: 781b ldrb r3, [r3, #0] 800bf4a: 2b01 cmp r3, #1 800bf4c: d103 bne.n 800bf56 CONN.EnableOutput = 0; 800bf4e: 4b1a ldr r3, [pc, #104] @ (800bfb8 ) 800bf50: 2200 movs r2, #0 800bf52: 75da strb r2, [r3, #23] 800bf54: e014 b.n 800bf80 } else { CONN.EnableOutput = ev_enable_output ? 1 : 0; 800bf56: 4b1c ldr r3, [pc, #112] @ (800bfc8 ) 800bf58: 781b ldrb r3, [r3, #0] 800bf5a: 2b00 cmp r3, #0 800bf5c: bf14 ite ne 800bf5e: 2301 movne r3, #1 800bf60: 2300 moveq r3, #0 800bf62: b2db uxtb r3, r3 800bf64: 461a mov r2, r3 800bf66: 4b14 ldr r3, [pc, #80] @ (800bfb8 ) 800bf68: 75da strb r2, [r3, #23] if((CONN.EnableOutput == 0) && (CONN.connState == Preparing)){ 800bf6a: 4b13 ldr r3, [pc, #76] @ (800bfb8 ) 800bf6c: 7ddb ldrb r3, [r3, #23] 800bf6e: 2b00 cmp r3, #0 800bf70: d106 bne.n 800bf80 800bf72: 4b11 ldr r3, [pc, #68] @ (800bfb8 ) 800bf74: 785b ldrb r3, [r3, #1] 800bf76: 2b03 cmp r3, #3 800bf78: d102 bne.n 800bf80 CONN.EnableOutput = 0; 800bf7a: 4b0f ldr r3, [pc, #60] @ (800bfb8 ) 800bf7c: 2200 movs r2, #0 800bf7e: 75da strb r2, [r3, #23] } } } if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800bf80: 4b12 ldr r3, [pc, #72] @ (800bfcc ) 800bf82: 781b ldrb r3, [r3, #0] 800bf84: 2b01 cmp r3, #1 800bf86: d007 beq.n 800bf98 (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800bf88: 4b10 ldr r3, [pc, #64] @ (800bfcc ) 800bf8a: 781b ldrb r3, [r3, #0] if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800bf8c: 2b02 cmp r3, #2 800bf8e: d003 beq.n 800bf98 (cp_state_buffer == EV_STATE_D_CONN_ACT_VENT)) { 800bf90: 4b0e ldr r3, [pc, #56] @ (800bfcc ) 800bf92: 781b ldrb r3, [r3, #0] (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800bf94: 2b03 cmp r3, #3 800bf96: d103 bne.n 800bfa0 CONN.EvConnected = 1; 800bf98: 4b07 ldr r3, [pc, #28] @ (800bfb8 ) 800bf9a: 2201 movs r2, #1 800bf9c: 779a strb r2, [r3, #30] 800bf9e: e003 b.n 800bfa8 } else { CONN.EvConnected = 0; 800bfa0: 4b05 ldr r3, [pc, #20] @ (800bfb8 ) 800bfa2: 2200 movs r2, #0 800bfa4: 779a strb r2, [r3, #30] } } 800bfa6: bf00 nop 800bfa8: bf00 nop 800bfaa: bd80 pop {r7, pc} 800bfac: 20000b3c .word 0x20000b3c 800bfb0: 20000b40 .word 0x20000b40 800bfb4: 08016034 .word 0x08016034 800bfb8: 2000033c .word 0x2000033c 800bfbc: 20000b90 .word 0x20000b90 800bfc0: 20000b38 .word 0x20000b38 800bfc4: 20000930 .word 0x20000930 800bfc8: 20000931 .word 0x20000931 800bfcc: 2000004f .word 0x2000004f 0800bfd0 : void CCS_Init(void){ 800bfd0: b580 push {r7, lr} 800bfd2: af00 add r7, sp, #0 CP_Init(); 800bfd4: f7fe f93c bl 800a250 CP_SetDuty(100); 800bfd8: 2064 movs r0, #100 @ 0x64 800bfda: f7fe f95b bl 800a294 CCS_MaxLoad.maxVoltage = PSU_MAX_VOLTAGE; // 1000V 800bfde: 4b0d ldr r3, [pc, #52] @ (800c014 ) 800bfe0: f44f 727a mov.w r2, #1000 @ 0x3e8 800bfe4: 801a strh r2, [r3, #0] CCS_MaxLoad.minVoltage = PSU_MIN_VOLTAGE; //150V 800bfe6: 4b0b ldr r3, [pc, #44] @ (800c014 ) 800bfe8: 2296 movs r2, #150 @ 0x96 800bfea: 805a strh r2, [r3, #2] CCS_MaxLoad.maxCurrent = PSU_MAX_CURRENT*10; //100A 800bfec: 4b09 ldr r3, [pc, #36] @ (800c014 ) 800bfee: f240 5232 movw r2, #1330 @ 0x532 800bff2: 809a strh r2, [r3, #4] CCS_MaxLoad.minCurrent = PSU_MIN_CURRENT*10; //1A 800bff4: 4b07 ldr r3, [pc, #28] @ (800c014 ) 800bff6: 220a movs r2, #10 800bff8: 80da strh r2, [r3, #6] CCS_MaxLoad.maxPower = PSU_MAX_POWER; //30000W 800bffa: 4b06 ldr r3, [pc, #24] @ (800c014 ) 800bffc: f247 5230 movw r2, #30000 @ 0x7530 800c000: 609a str r2, [r3, #8] CCS_SendResetReason(); 800c002: f000 f8b3 bl 800c16c log_printf(LOG_INFO, "CCS init\n"); 800c006: 4904 ldr r1, [pc, #16] @ (800c018 ) 800c008: 2007 movs r0, #7 800c00a: f7fe fb07 bl 800a61c } 800c00e: bf00 nop 800c010: bd80 pop {r7, pc} 800c012: bf00 nop 800c014: 20000910 .word 0x20000910 800c018: 08016048 .word 0x08016048 0800c01c : static uint16_t crc16_ibm(const uint8_t* data, uint16_t length) { 800c01c: b480 push {r7} 800c01e: b085 sub sp, #20 800c020: af00 add r7, sp, #0 800c022: 6078 str r0, [r7, #4] 800c024: 460b mov r3, r1 800c026: 807b strh r3, [r7, #2] uint16_t crc = 0xFFFFu; 800c028: f64f 73ff movw r3, #65535 @ 0xffff 800c02c: 81fb strh r3, [r7, #14] for (uint16_t i = 0; i < length; i++) { 800c02e: 2300 movs r3, #0 800c030: 81bb strh r3, [r7, #12] 800c032: e022 b.n 800c07a crc ^= data[i]; 800c034: 89bb ldrh r3, [r7, #12] 800c036: 687a ldr r2, [r7, #4] 800c038: 4413 add r3, r2 800c03a: 781b ldrb r3, [r3, #0] 800c03c: 461a mov r2, r3 800c03e: 89fb ldrh r3, [r7, #14] 800c040: 4053 eors r3, r2 800c042: 81fb strh r3, [r7, #14] for (uint8_t j = 0; j < 8; j++) { 800c044: 2300 movs r3, #0 800c046: 72fb strb r3, [r7, #11] 800c048: e011 b.n 800c06e if (crc & 1u) { 800c04a: 89fb ldrh r3, [r7, #14] 800c04c: f003 0301 and.w r3, r3, #1 800c050: 2b00 cmp r3, #0 800c052: d006 beq.n 800c062 crc = (crc >> 1) ^ 0xA001u; 800c054: 89fb ldrh r3, [r7, #14] 800c056: 085b lsrs r3, r3, #1 800c058: b29a uxth r2, r3 800c05a: 4b0d ldr r3, [pc, #52] @ (800c090 ) 800c05c: 4053 eors r3, r2 800c05e: 81fb strh r3, [r7, #14] 800c060: e002 b.n 800c068 } else { crc >>= 1; 800c062: 89fb ldrh r3, [r7, #14] 800c064: 085b lsrs r3, r3, #1 800c066: 81fb strh r3, [r7, #14] for (uint8_t j = 0; j < 8; j++) { 800c068: 7afb ldrb r3, [r7, #11] 800c06a: 3301 adds r3, #1 800c06c: 72fb strb r3, [r7, #11] 800c06e: 7afb ldrb r3, [r7, #11] 800c070: 2b07 cmp r3, #7 800c072: d9ea bls.n 800c04a for (uint16_t i = 0; i < length; i++) { 800c074: 89bb ldrh r3, [r7, #12] 800c076: 3301 adds r3, #1 800c078: 81bb strh r3, [r7, #12] 800c07a: 89ba ldrh r2, [r7, #12] 800c07c: 887b ldrh r3, [r7, #2] 800c07e: 429a cmp r2, r3 800c080: d3d8 bcc.n 800c034 } } } return crc; 800c082: 89fb ldrh r3, [r7, #14] } 800c084: 4618 mov r0, r3 800c086: 3714 adds r7, #20 800c088: 46bd mov sp, r7 800c08a: bc80 pop {r7} 800c08c: 4770 bx lr 800c08e: bf00 nop 800c090: ffffa001 .word 0xffffa001 0800c094 : static uint16_t CCS_BuildPacket(uint8_t cmd, const void* payload, uint16_t payload_len, uint8_t* out, uint16_t out_max) { 800c094: b580 push {r7, lr} 800c096: b086 sub sp, #24 800c098: af00 add r7, sp, #0 800c09a: 60b9 str r1, [r7, #8] 800c09c: 607b str r3, [r7, #4] 800c09e: 4603 mov r3, r0 800c0a0: 73fb strb r3, [r7, #15] 800c0a2: 4613 mov r3, r2 800c0a4: 81bb strh r3, [r7, #12] uint16_t total_len = (uint16_t)(1u + payload_len + 2u); 800c0a6: 89bb ldrh r3, [r7, #12] 800c0a8: 3303 adds r3, #3 800c0aa: 82fb strh r3, [r7, #22] if (total_len > out_max) return 0; 800c0ac: 8afa ldrh r2, [r7, #22] 800c0ae: 8c3b ldrh r3, [r7, #32] 800c0b0: 429a cmp r2, r3 800c0b2: d901 bls.n 800c0b8 800c0b4: 2300 movs r3, #0 800c0b6: e029 b.n 800c10c out[0] = cmd; 800c0b8: 687b ldr r3, [r7, #4] 800c0ba: 7bfa ldrb r2, [r7, #15] 800c0bc: 701a strb r2, [r3, #0] if (payload_len && payload != NULL) { 800c0be: 89bb ldrh r3, [r7, #12] 800c0c0: 2b00 cmp r3, #0 800c0c2: d009 beq.n 800c0d8 800c0c4: 68bb ldr r3, [r7, #8] 800c0c6: 2b00 cmp r3, #0 800c0c8: d006 beq.n 800c0d8 memcpy(&out[1], payload, payload_len); 800c0ca: 687b ldr r3, [r7, #4] 800c0cc: 3301 adds r3, #1 800c0ce: 89ba ldrh r2, [r7, #12] 800c0d0: 68b9 ldr r1, [r7, #8] 800c0d2: 4618 mov r0, r3 800c0d4: f007 fd1c bl 8013b10 } uint16_t crc = crc16_ibm(out, (uint16_t)(1u + payload_len)); 800c0d8: 89bb ldrh r3, [r7, #12] 800c0da: 3301 adds r3, #1 800c0dc: b29b uxth r3, r3 800c0de: 4619 mov r1, r3 800c0e0: 6878 ldr r0, [r7, #4] 800c0e2: f7ff ff9b bl 800c01c 800c0e6: 4603 mov r3, r0 800c0e8: 82bb strh r3, [r7, #20] out[1u + payload_len] = (uint8_t)(crc & 0xFFu); 800c0ea: 89bb ldrh r3, [r7, #12] 800c0ec: 3301 adds r3, #1 800c0ee: 687a ldr r2, [r7, #4] 800c0f0: 4413 add r3, r2 800c0f2: 8aba ldrh r2, [r7, #20] 800c0f4: b2d2 uxtb r2, r2 800c0f6: 701a strb r2, [r3, #0] out[1u + payload_len + 1u] = (uint8_t)((crc >> 8) & 0xFFu); 800c0f8: 8abb ldrh r3, [r7, #20] 800c0fa: 0a1b lsrs r3, r3, #8 800c0fc: b299 uxth r1, r3 800c0fe: 89bb ldrh r3, [r7, #12] 800c100: 3302 adds r3, #2 800c102: 687a ldr r2, [r7, #4] 800c104: 4413 add r3, r2 800c106: b2ca uxtb r2, r1 800c108: 701a strb r2, [r3, #0] return total_len; 800c10a: 8afb ldrh r3, [r7, #22] } 800c10c: 4618 mov r0, r3 800c10e: 3718 adds r7, #24 800c110: 46bd mov sp, r7 800c112: bd80 pop {r7, pc} 0800c114 : static void CCS_SendPacket(uint8_t cmd, const void* payload, uint16_t payload_len) { 800c114: b580 push {r7, lr} 800c116: b086 sub sp, #24 800c118: af02 add r7, sp, #8 800c11a: 4603 mov r3, r0 800c11c: 6039 str r1, [r7, #0] 800c11e: 71fb strb r3, [r7, #7] 800c120: 4613 mov r3, r2 800c122: 80bb strh r3, [r7, #4] uint16_t len = CCS_BuildPacket(cmd, payload, payload_len, tx_buffer, sizeof(tx_buffer)); 800c124: 88ba ldrh r2, [r7, #4] 800c126: 79f8 ldrb r0, [r7, #7] 800c128: f44f 7380 mov.w r3, #256 @ 0x100 800c12c: 9300 str r3, [sp, #0] 800c12e: 4b0c ldr r3, [pc, #48] @ (800c160 ) 800c130: 6839 ldr r1, [r7, #0] 800c132: f7ff ffaf bl 800c094 800c136: 4603 mov r3, r0 800c138: 81fb strh r3, [r7, #14] if (len > 0) { 800c13a: 89fb ldrh r3, [r7, #14] 800c13c: 2b00 cmp r3, #0 800c13e: d006 beq.n 800c14e HAL_UART_Transmit(&huart3, tx_buffer, len, 1000); 800c140: 89fa ldrh r2, [r7, #14] 800c142: f44f 737a mov.w r3, #1000 @ 0x3e8 800c146: 4906 ldr r1, [pc, #24] @ (800c160 ) 800c148: 4806 ldr r0, [pc, #24] @ (800c164 ) 800c14a: f005 ff17 bl 8011f7c } last_cmd_sent = HAL_GetTick(); 800c14e: f001 fd0f bl 800db70 800c152: 4603 mov r3, r0 800c154: 4a04 ldr r2, [pc, #16] @ (800c168 ) 800c156: 6013 str r3, [r2, #0] } 800c158: bf00 nop 800c15a: 3710 adds r7, #16 800c15c: 46bd mov sp, r7 800c15e: bd80 pop {r7, pc} 800c160: 20000a34 .word 0x20000a34 800c164: 20001194 .word 0x20001194 800c168: 20000928 .word 0x20000928 0800c16c : static void CCS_SendResetReason(void) { 800c16c: b580 push {r7, lr} 800c16e: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_RESET, NULL, 0); 800c170: 2200 movs r2, #0 800c172: 2100 movs r1, #0 800c174: 2052 movs r0, #82 @ 0x52 800c176: f7ff ffcd bl 800c114 } 800c17a: bf00 nop 800c17c: bd80 pop {r7, pc} 0800c17e : void CCS_SendEmergencyStop(void) { 800c17e: b580 push {r7, lr} 800c180: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_ESTOP, NULL, 0); 800c182: 2200 movs r2, #0 800c184: 2100 movs r1, #0 800c186: 2053 movs r0, #83 @ 0x53 800c188: f7ff ffc4 bl 800c114 } 800c18c: bf00 nop 800c18e: bd80 pop {r7, pc} 0800c190 : void CCS_SendStart(void) { CCS_SendPacket(CMD_M2E_START, NULL, 0); } static void CCS_CalculateEnergy(void) { 800c190: b580 push {r7, lr} 800c192: b082 sub sp, #8 800c194: af00 add r7, sp, #0 static uint32_t lastTick = 0; uint32_t currentTick = HAL_GetTick(); 800c196: f001 fceb bl 800db70 800c19a: 6078 str r0, [r7, #4] uint32_t elapsedTimeMs = currentTick - lastTick; 800c19c: 4b1e ldr r3, [pc, #120] @ (800c218 ) 800c19e: 681b ldr r3, [r3, #0] 800c1a0: 687a ldr r2, [r7, #4] 800c1a2: 1ad3 subs r3, r2, r3 800c1a4: 603b str r3, [r7, #0] lastTick = currentTick; 800c1a6: 4a1c ldr r2, [pc, #112] @ (800c218 ) 800c1a8: 687b ldr r3, [r7, #4] 800c1aa: 6013 str r3, [r2, #0] CCS_Power = CONN.MeasuredVoltage * CONN.MeasuredCurrent / 10; 800c1ac: 4b1b ldr r3, [pc, #108] @ (800c21c ) 800c1ae: f8b3 3013 ldrh.w r3, [r3, #19] 800c1b2: b29b uxth r3, r3 800c1b4: 461a mov r2, r3 800c1b6: 4b19 ldr r3, [pc, #100] @ (800c21c ) 800c1b8: f8b3 3015 ldrh.w r3, [r3, #21] 800c1bc: b29b uxth r3, r3 800c1be: fb02 f303 mul.w r3, r2, r3 800c1c2: 4a17 ldr r2, [pc, #92] @ (800c220 ) 800c1c4: fb82 1203 smull r1, r2, r2, r3 800c1c8: 1092 asrs r2, r2, #2 800c1ca: 17db asrs r3, r3, #31 800c1cc: 1ad3 subs r3, r2, r3 800c1ce: 461a mov r2, r3 800c1d0: 4b14 ldr r3, [pc, #80] @ (800c224 ) 800c1d2: 601a str r2, [r3, #0] CCS_EnergyWs += (CCS_Power * elapsedTimeMs) / 1000; 800c1d4: 4b13 ldr r3, [pc, #76] @ (800c224 ) 800c1d6: 681b ldr r3, [r3, #0] 800c1d8: 683a ldr r2, [r7, #0] 800c1da: fb02 f303 mul.w r3, r2, r3 800c1de: 4a12 ldr r2, [pc, #72] @ (800c228 ) 800c1e0: fba2 2303 umull r2, r3, r2, r3 800c1e4: 099a lsrs r2, r3, #6 800c1e6: 4b11 ldr r3, [pc, #68] @ (800c22c ) 800c1e8: 681b ldr r3, [r3, #0] 800c1ea: 4413 add r3, r2 800c1ec: 4a0f ldr r2, [pc, #60] @ (800c22c ) 800c1ee: 6013 str r3, [r2, #0] if(CCS_EvseState == Unplugged) { 800c1f0: 4b0f ldr r3, [pc, #60] @ (800c230 ) 800c1f2: 781b ldrb r3, [r3, #0] 800c1f4: 2b01 cmp r3, #1 800c1f6: d102 bne.n 800c1fe CCS_EnergyWs = 0; 800c1f8: 4b0c ldr r3, [pc, #48] @ (800c22c ) 800c1fa: 2200 movs r2, #0 800c1fc: 601a str r2, [r3, #0] } CCS_Energy = CCS_EnergyWs / 3600; 800c1fe: 4b0b ldr r3, [pc, #44] @ (800c22c ) 800c200: 681b ldr r3, [r3, #0] 800c202: 4a0c ldr r2, [pc, #48] @ (800c234 ) 800c204: fba2 2303 umull r2, r3, r2, r3 800c208: 0adb lsrs r3, r3, #11 800c20a: 4a0b ldr r2, [pc, #44] @ (800c238 ) 800c20c: 6013 str r3, [r2, #0] } 800c20e: bf00 nop 800c210: 3708 adds r7, #8 800c212: 46bd mov sp, r7 800c214: bd80 pop {r7, pc} 800c216: bf00 nop 800c218: 20000b9c .word 0x20000b9c 800c21c: 2000033c .word 0x2000033c 800c220: 66666667 .word 0x66666667 800c224: 2000091c .word 0x2000091c 800c228: 10624dd3 .word 0x10624dd3 800c22c: 20000920 .word 0x20000920 800c230: 20000b90 .word 0x20000b90 800c234: 91a2b3c5 .word 0x91a2b3c5 800c238: 20000924 .word 0x20000924 0800c23c : static void send_state(void) { 800c23c: b580 push {r7, lr} 800c23e: af00 add r7, sp, #0 CCS_CalculateEnergy(); 800c240: f7ff ffa6 bl 800c190 CCS_State.DutyCycle = CP_GetDuty(); 800c244: f7fe f84e bl 800a2e4 800c248: 4603 mov r3, r0 800c24a: 461a mov r2, r3 800c24c: 4b30 ldr r3, [pc, #192] @ (800c310 ) 800c24e: 701a strb r2, [r3, #0] CCS_State.OutputEnabled = PSU0.CONT_enabled; 800c250: 4b30 ldr r3, [pc, #192] @ (800c314 ) 800c252: 7ada ldrb r2, [r3, #11] 800c254: 4b2e ldr r3, [pc, #184] @ (800c310 ) 800c256: 705a strb r2, [r3, #1] CCS_State.MeasuredVoltage = (uint16_t)CONN.MeasuredVoltage; 800c258: 4b2f ldr r3, [pc, #188] @ (800c318 ) 800c25a: f8b3 3013 ldrh.w r3, [r3, #19] 800c25e: b29a uxth r2, r3 800c260: 4b2b ldr r3, [pc, #172] @ (800c310 ) 800c262: 805a strh r2, [r3, #2] if (CONN.RequestedVoltage == 500) CCS_State.MeasuredVoltage = 500; // fake 800c264: 4b2c ldr r3, [pc, #176] @ (800c318 ) 800c266: f8b3 300f ldrh.w r3, [r3, #15] 800c26a: b29b uxth r3, r3 800c26c: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800c270: d103 bne.n 800c27a 800c272: 4b27 ldr r3, [pc, #156] @ (800c310 ) 800c274: f44f 72fa mov.w r2, #500 @ 0x1f4 800c278: 805a strh r2, [r3, #2] CCS_State.MeasuredCurrent = (uint16_t)CONN.MeasuredCurrent; 800c27a: 4b27 ldr r3, [pc, #156] @ (800c318 ) 800c27c: f8b3 3015 ldrh.w r3, [r3, #21] 800c280: b29a uxth r2, r3 800c282: 4b23 ldr r3, [pc, #140] @ (800c310 ) 800c284: 809a strh r2, [r3, #4] CCS_State.Power = CCS_Power; 800c286: 4b25 ldr r3, [pc, #148] @ (800c31c ) 800c288: 681b ldr r3, [r3, #0] 800c28a: 4a21 ldr r2, [pc, #132] @ (800c310 ) 800c28c: f8c2 3006 str.w r3, [r2, #6] CCS_State.Energy = CCS_Energy; 800c290: 4b23 ldr r3, [pc, #140] @ (800c320 ) 800c292: 681b ldr r3, [r3, #0] 800c294: 4a1e ldr r2, [pc, #120] @ (800c310 ) 800c296: f8c2 300a str.w r3, [r2, #10] if(CCS_ConnectorState == CCS_CONNECTED){ 800c29a: 4b22 ldr r3, [pc, #136] @ (800c324 ) 800c29c: 781b ldrb r3, [r3, #0] 800c29e: 2b03 cmp r3, #3 800c2a0: d104 bne.n 800c2ac CCS_State.CpState = cp_state_buffer; 800c2a2: 4b21 ldr r3, [pc, #132] @ (800c328 ) 800c2a4: 781a ldrb r2, [r3, #0] 800c2a6: 4b1a ldr r3, [pc, #104] @ (800c310 ) 800c2a8: 74da strb r2, [r3, #19] 800c2aa: e002 b.n 800c2b2 } else { CCS_State.CpState = EV_STATE_A_IDLE; 800c2ac: 4b18 ldr r3, [pc, #96] @ (800c310 ) 800c2ae: 2200 movs r2, #0 800c2b0: 74da strb r2, [r3, #19] } CCS_State.MaxVoltage = CCS_MaxLoad.maxVoltage; 800c2b2: 4b1e ldr r3, [pc, #120] @ (800c32c ) 800c2b4: 881a ldrh r2, [r3, #0] 800c2b6: 4b16 ldr r3, [pc, #88] @ (800c310 ) 800c2b8: 829a strh r2, [r3, #20] CCS_State.MinVoltage = CCS_MaxLoad.minVoltage; 800c2ba: 4b1c ldr r3, [pc, #112] @ (800c32c ) 800c2bc: 885a ldrh r2, [r3, #2] 800c2be: 4b14 ldr r3, [pc, #80] @ (800c310 ) 800c2c0: 82da strh r2, [r3, #22] CCS_State.MaxCurrent = CCS_MaxLoad.maxCurrent; 800c2c2: 4b1a ldr r3, [pc, #104] @ (800c32c ) 800c2c4: 889a ldrh r2, [r3, #4] 800c2c6: 4b12 ldr r3, [pc, #72] @ (800c310 ) 800c2c8: 831a strh r2, [r3, #24] CCS_State.MinCurrent = CCS_MaxLoad.minCurrent; 800c2ca: 4b18 ldr r3, [pc, #96] @ (800c32c ) 800c2cc: 88da ldrh r2, [r3, #6] 800c2ce: 4b10 ldr r3, [pc, #64] @ (800c310 ) 800c2d0: 835a strh r2, [r3, #26] CCS_State.MaxPower = CCS_MaxLoad.maxPower; 800c2d2: 4b16 ldr r3, [pc, #88] @ (800c32c ) 800c2d4: 689b ldr r3, [r3, #8] 800c2d6: 4a0e ldr r2, [pc, #56] @ (800c310 ) 800c2d8: 61d3 str r3, [r2, #28] CCS_State.IsolationValid = isolation_enable; 800c2da: 4b15 ldr r3, [pc, #84] @ (800c330 ) 800c2dc: 781a ldrb r2, [r3, #0] 800c2de: 4b0c ldr r3, [pc, #48] @ (800c310 ) 800c2e0: 749a strb r2, [r3, #18] CCS_State.IsolationResistance = 900000; 800c2e2: 4a0b ldr r2, [pc, #44] @ (800c310 ) 800c2e4: 2300 movs r3, #0 800c2e6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800c2ea: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800c2ee: f443 433b orr.w r3, r3, #47872 @ 0xbb00 800c2f2: f043 03a0 orr.w r3, r3, #160 @ 0xa0 800c2f6: 81d3 strh r3, [r2, #14] 800c2f8: 2300 movs r3, #0 800c2fa: f043 030d orr.w r3, r3, #13 800c2fe: 8213 strh r3, [r2, #16] CCS_SendPacket(CMD_M2E_STATE, &CCS_State, sizeof(CCS_State)); 800c300: 2220 movs r2, #32 800c302: 4903 ldr r1, [pc, #12] @ (800c310 ) 800c304: 2050 movs r0, #80 @ 0x50 800c306: f7ff ff05 bl 800c114 } 800c30a: bf00 nop 800c30c: bd80 pop {r7, pc} 800c30e: bf00 nop 800c310: 20000b44 .word 0x20000b44 800c314: 2000088c .word 0x2000088c 800c318: 2000033c .word 0x2000033c 800c31c: 2000091c .word 0x2000091c 800c320: 20000924 .word 0x20000924 800c324: 20000050 .word 0x20000050 800c328: 2000004f .word 0x2000004f 800c32c: 20000910 .word 0x20000910 800c330: 20000b37 .word 0x20000b37 0800c334 : static uint16_t expected_payload_len(uint8_t cmd) { 800c334: b480 push {r7} 800c336: b083 sub sp, #12 800c338: af00 add r7, sp, #0 800c33a: 4603 mov r3, r0 800c33c: 71fb strb r3, [r7, #7] switch (cmd) { 800c33e: 79fb ldrb r3, [r7, #7] 800c340: 3b40 subs r3, #64 @ 0x40 800c342: 2b09 cmp r3, #9 800c344: d82a bhi.n 800c39c 800c346: a201 add r2, pc, #4 @ (adr r2, 800c34c ) 800c348: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c34c: 0800c375 .word 0x0800c375 800c350: 0800c379 .word 0x0800c379 800c354: 0800c37d .word 0x0800c37d 800c358: 0800c381 .word 0x0800c381 800c35c: 0800c385 .word 0x0800c385 800c360: 0800c389 .word 0x0800c389 800c364: 0800c38d .word 0x0800c38d 800c368: 0800c391 .word 0x0800c391 800c36c: 0800c395 .word 0x0800c395 800c370: 0800c399 .word 0x0800c399 case CMD_E2M_PWM_DUTY: return sizeof(e2m_pwm_duty_t); 800c374: 2301 movs r3, #1 800c376: e013 b.n 800c3a0 case CMD_E2M_ENABLE_OUTPUT: return sizeof(e2m_enable_output_t); 800c378: 2301 movs r3, #1 800c37a: e011 b.n 800c3a0 case CMD_E2M_RESET: return sizeof(e2m_reset_t); 800c37c: 2301 movs r3, #1 800c37e: e00f b.n 800c3a0 case CMD_E2M_ENABLE: return sizeof(e2m_enable_t); 800c380: 2301 movs r3, #1 800c382: e00d b.n 800c3a0 case CMD_E2M_REPLUG: return sizeof(e2m_replug_t); 800c384: 2301 movs r3, #1 800c386: e00b b.n 800c3a0 case CMD_E2M_SET_OUTPUT_VOLTAGE: return sizeof(e2m_set_output_t); 800c388: 2304 movs r3, #4 800c38a: e009 b.n 800c3a0 case CMD_E2M_ISOLATION_CONTROL: return sizeof(e2m_isolation_control_t); 800c38c: 2301 movs r3, #1 800c38e: e007 b.n 800c3a0 case CMD_E2M_EV_INFO: return sizeof(CCS_EvInfo_t); 800c390: 232c movs r3, #44 @ 0x2c 800c392: e005 b.n 800c3a0 case CMD_E2M_EVSE_STATE: return sizeof(CONN_State_t); 800c394: 2301 movs r3, #1 800c396: e003 b.n 800c3a0 case CMD_E2M_KEEP_ALIVE: return 0; 800c398: 2300 movs r3, #0 800c39a: e001 b.n 800c3a0 default: return 0xFFFFu; 800c39c: f64f 73ff movw r3, #65535 @ 0xffff } } 800c3a0: 4618 mov r0, r3 800c3a2: 370c adds r7, #12 800c3a4: 46bd mov sp, r7 800c3a6: bc80 pop {r7} 800c3a8: 4770 bx lr 800c3aa: bf00 nop 0800c3ac : static void apply_command(uint8_t cmd, const uint8_t* payload, uint16_t payload_len) { 800c3ac: b5f0 push {r4, r5, r6, r7, lr} 800c3ae: b08b sub sp, #44 @ 0x2c 800c3b0: af00 add r7, sp, #0 800c3b2: 4603 mov r3, r0 800c3b4: 6039 str r1, [r7, #0] 800c3b6: 71fb strb r3, [r7, #7] 800c3b8: 4613 mov r3, r2 800c3ba: 80bb strh r3, [r7, #4] (void)payload_len; last_host_seen = HAL_GetTick(); 800c3bc: f001 fbd8 bl 800db70 800c3c0: 4603 mov r3, r0 800c3c2: 4a5b ldr r2, [pc, #364] @ (800c530 ) 800c3c4: 6013 str r3, [r2, #0] everest_timed_out = 0; 800c3c6: 4b5b ldr r3, [pc, #364] @ (800c534 ) 800c3c8: 2200 movs r2, #0 800c3ca: 701a strb r2, [r3, #0] last_everest_timeout_log_tick = 0; 800c3cc: 4b5a ldr r3, [pc, #360] @ (800c538 ) 800c3ce: 2200 movs r2, #0 800c3d0: 601a str r2, [r3, #0] switch (cmd) { 800c3d2: 79fb ldrb r3, [r7, #7] 800c3d4: 3b40 subs r3, #64 @ 0x40 800c3d6: 2b09 cmp r3, #9 800c3d8: f200 80a3 bhi.w 800c522 800c3dc: a201 add r2, pc, #4 @ (adr r2, 800c3e4 ) 800c3de: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c3e2: bf00 nop 800c3e4: 0800c40d .word 0x0800c40d 800c3e8: 0800c43b .word 0x0800c43b 800c3ec: 0800c455 .word 0x0800c455 800c3f0: 0800c477 .word 0x0800c477 800c3f4: 0800c50b .word 0x0800c50b 800c3f8: 0800c491 .word 0x0800c491 800c3fc: 0800c4af .word 0x0800c4af 800c400: 0800c4bd .word 0x0800c4bd 800c404: 0800c501 .word 0x0800c501 800c408: 0800c517 .word 0x0800c517 case CMD_E2M_PWM_DUTY: { const e2m_pwm_duty_t* p = (const e2m_pwm_duty_t*)payload; 800c40c: 683b ldr r3, [r7, #0] 800c40e: 60fb str r3, [r7, #12] uint8_t duty = p->pwm_duty_percent; 800c410: 68fb ldr r3, [r7, #12] 800c412: 781b ldrb r3, [r3, #0] 800c414: f887 3027 strb.w r3, [r7, #39] @ 0x27 if (duty > 100) duty = 100; 800c418: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 800c41c: 2b64 cmp r3, #100 @ 0x64 800c41e: d902 bls.n 800c426 800c420: 2364 movs r3, #100 @ 0x64 800c422: f887 3027 strb.w r3, [r7, #39] @ 0x27 pwm_duty_percent = duty; 800c426: 4a45 ldr r2, [pc, #276] @ (800c53c ) 800c428: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 800c42c: 7013 strb r3, [r2, #0] CP_SetDuty(duty); 800c42e: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 800c432: 4618 mov r0, r3 800c434: f7fd ff2e bl 800a294 break; 800c438: e076 b.n 800c528 } case CMD_E2M_ENABLE_OUTPUT: { const e2m_enable_output_t* p = (const e2m_enable_output_t*)payload; 800c43a: 683b ldr r3, [r7, #0] 800c43c: 613b str r3, [r7, #16] ev_enable_output = (p->enable_output != 0); 800c43e: 693b ldr r3, [r7, #16] 800c440: 781b ldrb r3, [r3, #0] 800c442: 2b00 cmp r3, #0 800c444: bf14 ite ne 800c446: 2301 movne r3, #1 800c448: 2300 moveq r3, #0 800c44a: b2db uxtb r3, r3 800c44c: 461a mov r2, r3 800c44e: 4b3c ldr r3, [pc, #240] @ (800c540 ) 800c450: 701a strb r2, [r3, #0] break; 800c452: e069 b.n 800c528 } case CMD_E2M_RESET: { const e2m_reset_t* p = (const e2m_reset_t*)payload; 800c454: 683b ldr r3, [r7, #0] 800c456: 617b str r3, [r7, #20] if (p->reset) { 800c458: 697b ldr r3, [r7, #20] 800c45a: 781b ldrb r3, [r3, #0] 800c45c: 2b00 cmp r3, #0 800c45e: d062 beq.n 800c526 log_printf(LOG_WARN, "Everest reset command\n"); 800c460: 4938 ldr r1, [pc, #224] @ (800c544 ) 800c462: 2005 movs r0, #5 800c464: f7fe f8da bl 800a61c CCS_SendResetReason(); 800c468: f7ff fe80 bl 800c16c HAL_Delay(10); 800c46c: 200a movs r0, #10 800c46e: f001 fb89 bl 800db84 NVIC_SystemReset(); 800c472: f7ff fb65 bl 800bb40 <__NVIC_SystemReset> } break; } case CMD_E2M_ENABLE: { const e2m_enable_t* p = (const e2m_enable_t*)payload; 800c476: 683b ldr r3, [r7, #0] 800c478: 61bb str r3, [r7, #24] enabled = (p->enable != 0); 800c47a: 69bb ldr r3, [r7, #24] 800c47c: 781b ldrb r3, [r3, #0] 800c47e: 2b00 cmp r3, #0 800c480: bf14 ite ne 800c482: 2301 movne r3, #1 800c484: 2300 moveq r3, #0 800c486: b2db uxtb r3, r3 800c488: 461a mov r2, r3 800c48a: 4b2f ldr r3, [pc, #188] @ (800c548 ) 800c48c: 701a strb r2, [r3, #0] (void)enabled; break; 800c48e: e04b b.n 800c528 } case CMD_E2M_SET_OUTPUT_VOLTAGE: { const e2m_set_output_t* p = (const e2m_set_output_t*)payload; 800c490: 683b ldr r3, [r7, #0] 800c492: 61fb str r3, [r7, #28] CONN.RequestedVoltage = p->voltage_V; 800c494: 69fb ldr r3, [r7, #28] 800c496: 881b ldrh r3, [r3, #0] 800c498: b29a uxth r2, r3 800c49a: 4b2c ldr r3, [pc, #176] @ (800c54c ) 800c49c: f8a3 200f strh.w r2, [r3, #15] CONN.WantedCurrent = p->current_0p1A; 800c4a0: 69fb ldr r3, [r7, #28] 800c4a2: 885b ldrh r3, [r3, #2] 800c4a4: b29a uxth r2, r3 800c4a6: 4b29 ldr r3, [pc, #164] @ (800c54c ) 800c4a8: f8a3 201b strh.w r2, [r3, #27] break; 800c4ac: e03c b.n 800c528 } case CMD_E2M_ISOLATION_CONTROL: { const e2m_isolation_control_t* p = (const e2m_isolation_control_t*)payload; 800c4ae: 683b ldr r3, [r7, #0] 800c4b0: 623b str r3, [r7, #32] isolation_enable = p->command; 800c4b2: 6a3b ldr r3, [r7, #32] 800c4b4: 781a ldrb r2, [r3, #0] 800c4b6: 4b26 ldr r3, [pc, #152] @ (800c550 ) 800c4b8: 701a strb r2, [r3, #0] break; 800c4ba: e035 b.n 800c528 } case CMD_E2M_EV_INFO: { memcpy(&CCS_EvInfo, payload, sizeof(CCS_EvInfo_t)); 800c4bc: 4a25 ldr r2, [pc, #148] @ (800c554 ) 800c4be: 683b ldr r3, [r7, #0] 800c4c0: 461c mov r4, r3 800c4c2: 4616 mov r6, r2 800c4c4: f104 0c20 add.w ip, r4, #32 800c4c8: 4635 mov r5, r6 800c4ca: 4623 mov r3, r4 800c4cc: 6818 ldr r0, [r3, #0] 800c4ce: 6859 ldr r1, [r3, #4] 800c4d0: 689a ldr r2, [r3, #8] 800c4d2: 68db ldr r3, [r3, #12] 800c4d4: c50f stmia r5!, {r0, r1, r2, r3} 800c4d6: 3410 adds r4, #16 800c4d8: 3610 adds r6, #16 800c4da: 4564 cmp r4, ip 800c4dc: d1f4 bne.n 800c4c8 800c4de: 4633 mov r3, r6 800c4e0: 4622 mov r2, r4 800c4e2: 6810 ldr r0, [r2, #0] 800c4e4: 6851 ldr r1, [r2, #4] 800c4e6: 6892 ldr r2, [r2, #8] 800c4e8: c307 stmia r3!, {r0, r1, r2} CONN.SOC = (uint8_t)(CCS_EvInfo.soc / 10); 800c4ea: 4b1a ldr r3, [pc, #104] @ (800c554 ) 800c4ec: 885b ldrh r3, [r3, #2] 800c4ee: 4a1a ldr r2, [pc, #104] @ (800c558 ) 800c4f0: fba2 2303 umull r2, r3, r2, r3 800c4f4: 08db lsrs r3, r3, #3 800c4f6: b29b uxth r3, r3 800c4f8: b2da uxtb r2, r3 800c4fa: 4b14 ldr r3, [pc, #80] @ (800c54c ) 800c4fc: 709a strb r2, [r3, #2] break; 800c4fe: e013 b.n 800c528 } case CMD_E2M_EVSE_STATE: { CCS_EvseState = (CONN_State_t)payload[0]; 800c500: 683b ldr r3, [r7, #0] 800c502: 781a ldrb r2, [r3, #0] 800c504: 4b15 ldr r3, [pc, #84] @ (800c55c ) 800c506: 701a strb r2, [r3, #0] break; 800c508: e00e b.n 800c528 } case CMD_E2M_REPLUG: { (void)payload; CP_SetDuty(pwm_duty_percent); 800c50a: 4b0c ldr r3, [pc, #48] @ (800c53c ) 800c50c: 781b ldrb r3, [r3, #0] 800c50e: 4618 mov r0, r3 800c510: f7fd fec0 bl 800a294 break; 800c514: e008 b.n 800c528 } case CMD_E2M_KEEP_ALIVE: { last_host_seen = HAL_GetTick(); 800c516: f001 fb2b bl 800db70 800c51a: 4603 mov r3, r0 800c51c: 4a04 ldr r2, [pc, #16] @ (800c530 ) 800c51e: 6013 str r3, [r2, #0] break; 800c520: e002 b.n 800c528 } default: break; 800c522: bf00 nop 800c524: e000 b.n 800c528 break; 800c526: bf00 nop } } 800c528: bf00 nop 800c52a: 372c adds r7, #44 @ 0x2c 800c52c: 46bd mov sp, r7 800c52e: bdf0 pop {r4, r5, r6, r7, pc} 800c530: 20000b38 .word 0x20000b38 800c534: 20000b3c .word 0x20000b3c 800c538: 20000b40 .word 0x20000b40 800c53c: 2000004e .word 0x2000004e 800c540: 20000931 .word 0x20000931 800c544: 08016054 .word 0x08016054 800c548: 20000b36 .word 0x20000b36 800c54c: 2000033c .word 0x2000033c 800c550: 20000b37 .word 0x20000b37 800c554: 20000b64 .word 0x20000b64 800c558: cccccccd .word 0xcccccccd 800c55c: 20000b90 .word 0x20000b90 0800c560 : static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len) { 800c560: b580 push {r7, lr} 800c562: b086 sub sp, #24 800c564: af00 add r7, sp, #0 800c566: 6078 str r0, [r7, #4] 800c568: 460b mov r3, r1 800c56a: 807b strh r3, [r7, #2] if (packet_len < 3) return 0; 800c56c: 887b ldrh r3, [r7, #2] 800c56e: 2b02 cmp r3, #2 800c570: d801 bhi.n 800c576 800c572: 2300 movs r3, #0 800c574: e05a b.n 800c62c uint8_t cmd = packet[0]; 800c576: 687b ldr r3, [r7, #4] 800c578: 781b ldrb r3, [r3, #0] 800c57a: 75fb strb r3, [r7, #23] uint16_t payload_len = (uint16_t)(packet_len - 3); 800c57c: 887b ldrh r3, [r7, #2] 800c57e: 3b03 subs r3, #3 800c580: 82bb strh r3, [r7, #20] uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c582: 887b ldrh r3, [r7, #2] 800c584: 3b02 subs r3, #2 800c586: 687a ldr r2, [r7, #4] 800c588: 4413 add r3, r2 800c58a: 781b ldrb r3, [r3, #0] 800c58c: b21a sxth r2, r3 (uint16_t)packet[packet_len - 1u] << 8; 800c58e: 887b ldrh r3, [r7, #2] 800c590: 3b01 subs r3, #1 800c592: 6879 ldr r1, [r7, #4] 800c594: 440b add r3, r1 800c596: 781b ldrb r3, [r3, #0] uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c598: b21b sxth r3, r3 800c59a: 021b lsls r3, r3, #8 800c59c: b21b sxth r3, r3 800c59e: 4313 orrs r3, r2 800c5a0: b21b sxth r3, r3 800c5a2: 827b strh r3, [r7, #18] uint16_t calculated_crc = crc16_ibm(packet, (uint16_t)(1 + payload_len)); 800c5a4: 8abb ldrh r3, [r7, #20] 800c5a6: 3301 adds r3, #1 800c5a8: b29b uxth r3, r3 800c5aa: 4619 mov r1, r3 800c5ac: 6878 ldr r0, [r7, #4] 800c5ae: f7ff fd35 bl 800c01c 800c5b2: 4603 mov r3, r0 800c5b4: 823b strh r3, [r7, #16] if (received_crc != calculated_crc) { 800c5b6: 8a7a ldrh r2, [r7, #18] 800c5b8: 8a3b ldrh r3, [r7, #16] 800c5ba: 429a cmp r2, r3 800c5bc: d005 beq.n 800c5ca log_printf(LOG_ERR, "Packet CRC error\n"); 800c5be: 491d ldr r1, [pc, #116] @ (800c634 ) 800c5c0: 2004 movs r0, #4 800c5c2: f7fe f82b bl 800a61c return 0; 800c5c6: 2300 movs r3, #0 800c5c8: e030 b.n 800c62c } uint16_t expected_len = expected_payload_len(cmd); 800c5ca: 7dfb ldrb r3, [r7, #23] 800c5cc: 4618 mov r0, r3 800c5ce: f7ff feb1 bl 800c334 800c5d2: 4603 mov r3, r0 800c5d4: 81fb strh r3, [r7, #14] if (expected_len == 0xFFFF) { 800c5d6: 89fb ldrh r3, [r7, #14] 800c5d8: f64f 72ff movw r2, #65535 @ 0xffff 800c5dc: 4293 cmp r3, r2 800c5de: d107 bne.n 800c5f0 log_printf(LOG_WARN, "Unknown cmd 0x%02x\n", cmd); 800c5e0: 7dfb ldrb r3, [r7, #23] 800c5e2: 461a mov r2, r3 800c5e4: 4914 ldr r1, [pc, #80] @ (800c638 ) 800c5e6: 2005 movs r0, #5 800c5e8: f7fe f818 bl 800a61c return 0; 800c5ec: 2300 movs r3, #0 800c5ee: e01d b.n 800c62c } if (expected_len != payload_len) { 800c5f0: 89fa ldrh r2, [r7, #14] 800c5f2: 8abb ldrh r3, [r7, #20] 800c5f4: 429a cmp r2, r3 800c5f6: d007 beq.n 800c608 log_printf(LOG_ERR, "Packet len mismatch cmd=0x%02x\n", cmd); 800c5f8: 7dfb ldrb r3, [r7, #23] 800c5fa: 461a mov r2, r3 800c5fc: 490f ldr r1, [pc, #60] @ (800c63c ) 800c5fe: 2004 movs r0, #4 800c600: f7fe f80c bl 800a61c return 0; 800c604: 2300 movs r3, #0 800c606: e011 b.n 800c62c } if (payload_len > 0) { 800c608: 8abb ldrh r3, [r7, #20] 800c60a: 2b00 cmp r3, #0 800c60c: d007 beq.n 800c61e apply_command(cmd, &packet[1], payload_len); 800c60e: 687b ldr r3, [r7, #4] 800c610: 1c59 adds r1, r3, #1 800c612: 8aba ldrh r2, [r7, #20] 800c614: 7dfb ldrb r3, [r7, #23] 800c616: 4618 mov r0, r3 800c618: f7ff fec8 bl 800c3ac 800c61c: e005 b.n 800c62a } else { apply_command(cmd, NULL, 0); 800c61e: 7dfb ldrb r3, [r7, #23] 800c620: 2200 movs r2, #0 800c622: 2100 movs r1, #0 800c624: 4618 mov r0, r3 800c626: f7ff fec1 bl 800c3ac } return 1; 800c62a: 2301 movs r3, #1 } 800c62c: 4618 mov r0, r3 800c62e: 3718 adds r7, #24 800c630: 46bd mov sp, r7 800c632: bd80 pop {r7, pc} 800c634: 0801606c .word 0x0801606c 800c638: 08016080 .word 0x08016080 800c63c: 08016094 .word 0x08016094 0800c640 : .fw_version_major = 0, .fw_version_minor = 0, .fw_version_patch = 0, }; void ReadVersion(){ 800c640: b480 push {r7} 800c642: af00 add r7, sp, #0 infoPacket.serialNumber = InfoBlock->serialNumber; 800c644: 4b0e ldr r3, [pc, #56] @ (800c680 ) 800c646: 681b ldr r3, [r3, #0] 800c648: 681b ldr r3, [r3, #0] 800c64a: b29a uxth r2, r3 800c64c: 4b0d ldr r3, [pc, #52] @ (800c684 ) 800c64e: 801a strh r2, [r3, #0] infoPacket.boardVersion = InfoBlock->boardVersion; 800c650: 4b0b ldr r3, [pc, #44] @ (800c680 ) 800c652: 681b ldr r3, [r3, #0] 800c654: 795a ldrb r2, [r3, #5] 800c656: 4b0b ldr r3, [pc, #44] @ (800c684 ) 800c658: 709a strb r2, [r3, #2] infoPacket.stationType = InfoBlock->stationType; 800c65a: 4b09 ldr r3, [pc, #36] @ (800c680 ) 800c65c: 681b ldr r3, [r3, #0] 800c65e: 791a ldrb r2, [r3, #4] 800c660: 4b08 ldr r3, [pc, #32] @ (800c684 ) 800c662: 70da strb r2, [r3, #3] infoPacket.fw_version_major = FW_VERSION_MAJOR; 800c664: 4b07 ldr r3, [pc, #28] @ (800c684 ) 800c666: 2201 movs r2, #1 800c668: 809a strh r2, [r3, #4] infoPacket.fw_version_minor = FW_VERSION_MINOR; 800c66a: 4b06 ldr r3, [pc, #24] @ (800c684 ) 800c66c: 2200 movs r2, #0 800c66e: 80da strh r2, [r3, #6] infoPacket.fw_version_patch = FW_VERSION_PATCH; 800c670: 4b04 ldr r3, [pc, #16] @ (800c684 ) 800c672: 220a movs r2, #10 800c674: 811a strh r2, [r3, #8] } 800c676: bf00 nop 800c678: 46bd mov sp, r7 800c67a: bc80 pop {r7} 800c67c: 4770 bx lr 800c67e: bf00 nop 800c680: 20000000 .word 0x20000000 800c684: 2000101c .word 0x2000101c 0800c688 : // Внешняя функция обработки команд (определена в serial_handler.c) extern void SC_CommandHandler(ReceivedCommand_t* cmd); void SC_Init() { 800c688: b580 push {r7, lr} 800c68a: af00 add r7, sp, #0 // Обнуляем структуру memset(&serial_control, 0, sizeof(SerialControl_t)); 800c68c: f44f 7204 mov.w r2, #528 @ 0x210 800c690: 2100 movs r1, #0 800c692: 4805 ldr r0, [pc, #20] @ (800c6a8 ) 800c694: f007 f9f4 bl 8013a80 memset(&serial_iso, 0, sizeof(serial_iso)); 800c698: f44f 7204 mov.w r2, #528 @ 0x210 800c69c: 2100 movs r1, #0 800c69e: 4803 ldr r0, [pc, #12] @ (800c6ac ) 800c6a0: f007 f9ee bl 8013a80 } 800c6a4: bf00 nop 800c6a6: bd80 pop {r7, pc} 800c6a8: 20000ba0 .word 0x20000ba0 800c6ac: 20000db0 .word 0x20000db0 0800c6b0 : void SC_Task() { 800c6b0: b580 push {r7, lr} 800c6b2: af00 add r7, sp, #0 // Запуск приема в режиме прерывания с ожиданием idle if((huart2.RxState == HAL_UART_STATE_READY) && (serial_control.command_ready == 0)) HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c6b4: 4b2a ldr r3, [pc, #168] @ (800c760 ) 800c6b6: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800c6ba: b2db uxtb r3, r3 800c6bc: 2b20 cmp r3, #32 800c6be: d10a bne.n 800c6d6 800c6c0: 4b28 ldr r3, [pc, #160] @ (800c764 ) 800c6c2: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800c6c6: b2db uxtb r3, r3 800c6c8: 2b00 cmp r3, #0 800c6ca: d104 bne.n 800c6d6 800c6cc: 22ff movs r2, #255 @ 0xff 800c6ce: 4926 ldr r1, [pc, #152] @ (800c768 ) 800c6d0: 4823 ldr r0, [pc, #140] @ (800c760 ) 800c6d2: f005 fd13 bl 80120fc if((huart5.RxState == HAL_UART_STATE_READY)) HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c6d6: 4b25 ldr r3, [pc, #148] @ (800c76c ) 800c6d8: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800c6dc: b2db uxtb r3, r3 800c6de: 2b20 cmp r3, #32 800c6e0: d104 bne.n 800c6ec 800c6e2: 22ff movs r2, #255 @ 0xff 800c6e4: 4922 ldr r1, [pc, #136] @ (800c770 ) 800c6e6: 4821 ldr r0, [pc, #132] @ (800c76c ) 800c6e8: f005 fd08 bl 80120fc // Проверка таймаута отправки пакета (больше 100 мс) if (huart2.gState == HAL_UART_STATE_BUSY_TX && serial_control.tx_tick != 0) { 800c6ec: 4b1c ldr r3, [pc, #112] @ (800c760 ) 800c6ee: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800c6f2: b2db uxtb r3, r3 800c6f4: 2b21 cmp r3, #33 @ 0x21 800c6f6: d119 bne.n 800c72c 800c6f8: 4b1a ldr r3, [pc, #104] @ (800c764 ) 800c6fa: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800c6fe: 2b00 cmp r3, #0 800c700: d014 beq.n 800c72c if ((HAL_GetTick() - serial_control.tx_tick) > 100) { 800c702: f001 fa35 bl 800db70 800c706: 4602 mov r2, r0 800c708: 4b16 ldr r3, [pc, #88] @ (800c764 ) 800c70a: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800c70e: 1ad3 subs r3, r2, r3 800c710: 2b64 cmp r3, #100 @ 0x64 800c712: d90b bls.n 800c72c // Таймаут: принудительно сбрасываем передачу HAL_UART_Abort_IT(&huart2); 800c714: 4812 ldr r0, [pc, #72] @ (800c760 ) 800c716: f005 fd4f bl 80121b8 // Выключаем DIR при сбросе передачи HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800c71a: 2200 movs r2, #0 800c71c: 2110 movs r1, #16 800c71e: 4815 ldr r0, [pc, #84] @ (800c774 ) 800c720: f003 fa37 bl 800fb92 serial_control.tx_tick = 0; // Сбрасываем tick 800c724: 4b0f ldr r3, [pc, #60] @ (800c764 ) 800c726: 2200 movs r2, #0 800c728: f8c3 220c str.w r2, [r3, #524] @ 0x20c } } // Проверка наличия принятой команды для обработки if (serial_control.command_ready && (huart2.gState != HAL_UART_STATE_BUSY_TX)) { 800c72c: 4b0d ldr r3, [pc, #52] @ (800c764 ) 800c72e: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800c732: b2db uxtb r3, r3 800c734: 2b00 cmp r3, #0 800c736: d011 beq.n 800c75c 800c738: 4b09 ldr r3, [pc, #36] @ (800c760 ) 800c73a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800c73e: b2db uxtb r3, r3 800c740: 2b21 cmp r3, #33 @ 0x21 800c742: d00b beq.n 800c75c // HAL_Delay(2); SC_CommandHandler(&serial_control.received_command); 800c744: 480c ldr r0, [pc, #48] @ (800c778 ) 800c746: f000 f9ed bl 800cb24 HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c74a: 22ff movs r2, #255 @ 0xff 800c74c: 4906 ldr r1, [pc, #24] @ (800c768 ) 800c74e: 4804 ldr r0, [pc, #16] @ (800c760 ) 800c750: f005 fcd4 bl 80120fc serial_control.command_ready = 0; // Сбрасываем флаг 800c754: 4b03 ldr r3, [pc, #12] @ (800c764 ) 800c756: 2200 movs r2, #0 800c758: f883 2208 strb.w r2, [r3, #520] @ 0x208 } } 800c75c: bf00 nop 800c75e: bd80 pop {r7, pc} 800c760: 2000114c .word 0x2000114c 800c764: 20000ba0 .word 0x20000ba0 800c768: 20000ca0 .word 0x20000ca0 800c76c: 200010bc .word 0x200010bc 800c770: 20000eb0 .word 0x20000eb0 800c774: 40011400 .word 0x40011400 800c778: 20000da0 .word 0x20000da0 0800c77c : void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800c77c: b580 push {r7, lr} 800c77e: b082 sub sp, #8 800c780: af00 add r7, sp, #0 800c782: 6078 str r0, [r7, #4] 800c784: 460b mov r3, r1 800c786: 807b strh r3, [r7, #2] if (huart->Instance == huart2.Instance) { 800c788: 687b ldr r3, [r7, #4] 800c78a: 681a ldr r2, [r3, #0] 800c78c: 4b22 ldr r3, [pc, #136] @ (800c818 ) 800c78e: 681b ldr r3, [r3, #0] 800c790: 429a cmp r2, r3 800c792: d116 bne.n 800c7c2 if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800c794: 887b ldrh r3, [r7, #2] 800c796: 461a mov r2, r3 800c798: 4920 ldr r1, [pc, #128] @ (800c81c ) 800c79a: 4821 ldr r0, [pc, #132] @ (800c820 ) 800c79c: f000 f98e bl 800cabc 800c7a0: 4603 mov r3, r0 800c7a2: 2b00 cmp r3, #0 800c7a4: d104 bne.n 800c7b0 SC_SendPacket(NULL, 0, RESP_INVALID); 800c7a6: 2214 movs r2, #20 800c7a8: 2100 movs r1, #0 800c7aa: 2000 movs r0, #0 800c7ac: f000 f8fa bl 800c9a4 } g_sc_command_source = SC_SOURCE_UART2; 800c7b0: 4b1c ldr r3, [pc, #112] @ (800c824 ) 800c7b2: 2200 movs r2, #0 800c7b4: 701a strb r2, [r3, #0] HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c7b6: 22ff movs r2, #255 @ 0xff 800c7b8: 4918 ldr r1, [pc, #96] @ (800c81c ) 800c7ba: 4817 ldr r0, [pc, #92] @ (800c818 ) 800c7bc: f005 fc9e bl 80120fc } HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1); } else if (huart->Instance == huart3.Instance) { CCS_RxEventCallback(huart, Size); } } 800c7c0: e025 b.n 800c80e } else if (huart->Instance == huart5.Instance) { 800c7c2: 687b ldr r3, [r7, #4] 800c7c4: 681a ldr r2, [r3, #0] 800c7c6: 4b18 ldr r3, [pc, #96] @ (800c828 ) 800c7c8: 681b ldr r3, [r3, #0] 800c7ca: 429a cmp r2, r3 800c7cc: d114 bne.n 800c7f8 if (process_received_packet(&serial_iso, serial_iso.rx_buffer, Size)) { 800c7ce: 887b ldrh r3, [r7, #2] 800c7d0: 461a mov r2, r3 800c7d2: 4916 ldr r1, [pc, #88] @ (800c82c ) 800c7d4: 4816 ldr r0, [pc, #88] @ (800c830 ) 800c7d6: f000 f971 bl 800cabc 800c7da: 4603 mov r3, r0 800c7dc: 2b00 cmp r3, #0 800c7de: d005 beq.n 800c7ec g_sc_command_source = SC_SOURCE_UART5; 800c7e0: 4b10 ldr r3, [pc, #64] @ (800c824 ) 800c7e2: 2201 movs r2, #1 800c7e4: 701a strb r2, [r3, #0] SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); 800c7e6: 4813 ldr r0, [pc, #76] @ (800c834 ) 800c7e8: f000 f99c bl 800cb24 HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c7ec: 22ff movs r2, #255 @ 0xff 800c7ee: 490f ldr r1, [pc, #60] @ (800c82c ) 800c7f0: 480d ldr r0, [pc, #52] @ (800c828 ) 800c7f2: f005 fc83 bl 80120fc } 800c7f6: e00a b.n 800c80e } else if (huart->Instance == huart3.Instance) { 800c7f8: 687b ldr r3, [r7, #4] 800c7fa: 681a ldr r2, [r3, #0] 800c7fc: 4b0e ldr r3, [pc, #56] @ (800c838 ) 800c7fe: 681b ldr r3, [r3, #0] 800c800: 429a cmp r2, r3 800c802: d104 bne.n 800c80e CCS_RxEventCallback(huart, Size); 800c804: 887b ldrh r3, [r7, #2] 800c806: 4619 mov r1, r3 800c808: 6878 ldr r0, [r7, #4] 800c80a: f7ff f9af bl 800bb6c } 800c80e: bf00 nop 800c810: 3708 adds r7, #8 800c812: 46bd mov sp, r7 800c814: bd80 pop {r7, pc} 800c816: bf00 nop 800c818: 2000114c .word 0x2000114c 800c81c: 20000ca0 .word 0x20000ca0 800c820: 20000ba0 .word 0x20000ba0 800c824: 20000fc0 .word 0x20000fc0 800c828: 200010bc .word 0x200010bc 800c82c: 20000eb0 .word 0x20000eb0 800c830: 20000db0 .word 0x20000db0 800c834: 20000fb0 .word 0x20000fb0 800c838: 20001194 .word 0x20001194 0800c83c : void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 800c83c: b580 push {r7, lr} 800c83e: b082 sub sp, #8 800c840: af00 add r7, sp, #0 800c842: 6078 str r0, [r7, #4] if (huart->Instance == huart2.Instance) { 800c844: 687b ldr r3, [r7, #4] 800c846: 681a ldr r2, [r3, #0] 800c848: 4b08 ldr r3, [pc, #32] @ (800c86c ) 800c84a: 681b ldr r3, [r3, #0] 800c84c: 429a cmp r2, r3 800c84e: d108 bne.n 800c862 HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800c850: 2200 movs r2, #0 800c852: 2110 movs r1, #16 800c854: 4806 ldr r0, [pc, #24] @ (800c870 ) 800c856: f003 f99c bl 800fb92 serial_control.tx_tick = 0; 800c85a: 4b06 ldr r3, [pc, #24] @ (800c874 ) 800c85c: 2200 movs r2, #0 800c85e: f8c3 220c str.w r2, [r3, #524] @ 0x20c } } 800c862: bf00 nop 800c864: 3708 adds r7, #8 800c866: 46bd mov sp, r7 800c868: bd80 pop {r7, pc} 800c86a: bf00 nop 800c86c: 2000114c .word 0x2000114c 800c870: 40011400 .word 0x40011400 800c874: 20000ba0 .word 0x20000ba0 0800c878 : // Приватные функции реализации // Полностью программная реализация CRC-32 (полином CRC32_POLYNOMIAL, порядок little-endian) static uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { 800c878: b480 push {r7} 800c87a: b085 sub sp, #20 800c87c: af00 add r7, sp, #0 800c87e: 6078 str r0, [r7, #4] 800c880: 460b mov r3, r1 800c882: 807b strh r3, [r7, #2] uint32_t crc = 0xFFFFFFFFu; 800c884: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800c888: 60fb str r3, [r7, #12] for (uint16_t i = 0; i < length; i++) { 800c88a: 2300 movs r3, #0 800c88c: 817b strh r3, [r7, #10] 800c88e: e021 b.n 800c8d4 crc ^= data[i]; 800c890: 897b ldrh r3, [r7, #10] 800c892: 687a ldr r2, [r7, #4] 800c894: 4413 add r3, r2 800c896: 781b ldrb r3, [r3, #0] 800c898: 461a mov r2, r3 800c89a: 68fb ldr r3, [r7, #12] 800c89c: 4053 eors r3, r2 800c89e: 60fb str r3, [r7, #12] for (uint8_t bit = 0; bit < 8; bit++) { 800c8a0: 2300 movs r3, #0 800c8a2: 727b strb r3, [r7, #9] 800c8a4: e010 b.n 800c8c8 if (crc & 0x1u) { 800c8a6: 68fb ldr r3, [r7, #12] 800c8a8: f003 0301 and.w r3, r3, #1 800c8ac: 2b00 cmp r3, #0 800c8ae: d005 beq.n 800c8bc crc = (crc >> 1) ^ CRC32_POLYNOMIAL; 800c8b0: 68fb ldr r3, [r7, #12] 800c8b2: 085a lsrs r2, r3, #1 800c8b4: 4b0d ldr r3, [pc, #52] @ (800c8ec ) 800c8b6: 4053 eors r3, r2 800c8b8: 60fb str r3, [r7, #12] 800c8ba: e002 b.n 800c8c2 } else { crc >>= 1; 800c8bc: 68fb ldr r3, [r7, #12] 800c8be: 085b lsrs r3, r3, #1 800c8c0: 60fb str r3, [r7, #12] for (uint8_t bit = 0; bit < 8; bit++) { 800c8c2: 7a7b ldrb r3, [r7, #9] 800c8c4: 3301 adds r3, #1 800c8c6: 727b strb r3, [r7, #9] 800c8c8: 7a7b ldrb r3, [r7, #9] 800c8ca: 2b07 cmp r3, #7 800c8cc: d9eb bls.n 800c8a6 for (uint16_t i = 0; i < length; i++) { 800c8ce: 897b ldrh r3, [r7, #10] 800c8d0: 3301 adds r3, #1 800c8d2: 817b strh r3, [r7, #10] 800c8d4: 897a ldrh r2, [r7, #10] 800c8d6: 887b ldrh r3, [r7, #2] 800c8d8: 429a cmp r2, r3 800c8da: d3d9 bcc.n 800c890 } } } return crc ^ 0xFFFFFFFFu; 800c8dc: 68fb ldr r3, [r7, #12] 800c8de: 43db mvns r3, r3 } 800c8e0: 4618 mov r0, r3 800c8e2: 3714 adds r7, #20 800c8e4: 46bd mov sp, r7 800c8e6: bc80 pop {r7} 800c8e8: 4770 bx lr 800c8ea: bf00 nop 800c8ec: edb88320 .word 0xedb88320 0800c8f0 : static uint16_t encode_packet(const uint8_t* payload, uint16_t payload_len, uint8_t* output, uint8_t response_code) { 800c8f0: b580 push {r7, lr} 800c8f2: b088 sub sp, #32 800c8f4: af00 add r7, sp, #0 800c8f6: 60f8 str r0, [r7, #12] 800c8f8: 607a str r2, [r7, #4] 800c8fa: 461a mov r2, r3 800c8fc: 460b mov r3, r1 800c8fe: 817b strh r3, [r7, #10] 800c900: 4613 mov r3, r2 800c902: 727b strb r3, [r7, #9] uint16_t out_index = 0; 800c904: 2300 movs r3, #0 800c906: 83fb strh r3, [r7, #30] output[out_index++] = response_code; 800c908: 8bfb ldrh r3, [r7, #30] 800c90a: 1c5a adds r2, r3, #1 800c90c: 83fa strh r2, [r7, #30] 800c90e: 461a mov r2, r3 800c910: 687b ldr r3, [r7, #4] 800c912: 4413 add r3, r2 800c914: 7a7a ldrb r2, [r7, #9] 800c916: 701a strb r2, [r3, #0] if (payload != NULL) { 800c918: 68fb ldr r3, [r7, #12] 800c91a: 2b00 cmp r3, #0 800c91c: d019 beq.n 800c952 // Просто копируем полезную нагрузку без какого‑либо экранирования for (uint16_t i = 0; i < payload_len; i++) { 800c91e: 2300 movs r3, #0 800c920: 83bb strh r3, [r7, #28] 800c922: e012 b.n 800c94a output[out_index++] = payload[i]; 800c924: 8bbb ldrh r3, [r7, #28] 800c926: 68fa ldr r2, [r7, #12] 800c928: 441a add r2, r3 800c92a: 8bfb ldrh r3, [r7, #30] 800c92c: 1c59 adds r1, r3, #1 800c92e: 83f9 strh r1, [r7, #30] 800c930: 4619 mov r1, r3 800c932: 687b ldr r3, [r7, #4] 800c934: 440b add r3, r1 800c936: 7812 ldrb r2, [r2, #0] 800c938: 701a strb r2, [r3, #0] // Проверка переполнения if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800c93a: 8bfb ldrh r3, [r7, #30] 800c93c: 2bfa cmp r3, #250 @ 0xfa 800c93e: d901 bls.n 800c944 return 0; 800c940: 2300 movs r3, #0 800c942: e02a b.n 800c99a for (uint16_t i = 0; i < payload_len; i++) { 800c944: 8bbb ldrh r3, [r7, #28] 800c946: 3301 adds r3, #1 800c948: 83bb strh r3, [r7, #28] 800c94a: 8bba ldrh r2, [r7, #28] 800c94c: 897b ldrh r3, [r7, #10] 800c94e: 429a cmp r2, r3 800c950: d3e8 bcc.n 800c924 } } } // Вычисляем CRC для всего содержимого (код ответа + полезная нагрузка) uint32_t crc = calculate_crc32(output, out_index); 800c952: 8bfb ldrh r3, [r7, #30] 800c954: 4619 mov r1, r3 800c956: 6878 ldr r0, [r7, #4] 800c958: f7ff ff8e bl 800c878 800c95c: 4603 mov r3, r0 800c95e: 613b str r3, [r7, #16] uint8_t* crc_bytes = (uint8_t*)&crc; 800c960: f107 0310 add.w r3, r7, #16 800c964: 617b str r3, [r7, #20] // Добавляем CRC без экранирования for (int i = 0; i < 4; i++) { 800c966: 2300 movs r3, #0 800c968: 61bb str r3, [r7, #24] 800c96a: e012 b.n 800c992 output[out_index++] = crc_bytes[i]; 800c96c: 69bb ldr r3, [r7, #24] 800c96e: 697a ldr r2, [r7, #20] 800c970: 441a add r2, r3 800c972: 8bfb ldrh r3, [r7, #30] 800c974: 1c59 adds r1, r3, #1 800c976: 83f9 strh r1, [r7, #30] 800c978: 4619 mov r1, r3 800c97a: 687b ldr r3, [r7, #4] 800c97c: 440b add r3, r1 800c97e: 7812 ldrb r2, [r2, #0] 800c980: 701a strb r2, [r3, #0] if (out_index >= MAX_TX_BUFFER_SIZE - 1) { // место для END_BYTE 800c982: 8bfb ldrh r3, [r7, #30] 800c984: 2bfe cmp r3, #254 @ 0xfe 800c986: d901 bls.n 800c98c return 0; 800c988: 2300 movs r3, #0 800c98a: e006 b.n 800c99a for (int i = 0; i < 4; i++) { 800c98c: 69bb ldr r3, [r7, #24] 800c98e: 3301 adds r3, #1 800c990: 61bb str r3, [r7, #24] 800c992: 69bb ldr r3, [r7, #24] 800c994: 2b03 cmp r3, #3 800c996: dde9 ble.n 800c96c } } return out_index; 800c998: 8bfb ldrh r3, [r7, #30] } 800c99a: 4618 mov r0, r3 800c99c: 3720 adds r7, #32 800c99e: 46bd mov sp, r7 800c9a0: bd80 pop {r7, pc} ... 0800c9a4 : void SC_SendPacket(const uint8_t* payload, uint16_t payload_len, uint8_t response_code) { 800c9a4: b580 push {r7, lr} 800c9a6: b084 sub sp, #16 800c9a8: af00 add r7, sp, #0 800c9aa: 6078 str r0, [r7, #4] 800c9ac: 460b mov r3, r1 800c9ae: 807b strh r3, [r7, #2] 800c9b0: 4613 mov r3, r2 800c9b2: 707b strb r3, [r7, #1] uint16_t packet_len = encode_packet(payload, payload_len, serial_control.tx_buffer, response_code); 800c9b4: 787b ldrb r3, [r7, #1] 800c9b6: 8879 ldrh r1, [r7, #2] 800c9b8: 4a15 ldr r2, [pc, #84] @ (800ca10 ) 800c9ba: 6878 ldr r0, [r7, #4] 800c9bc: f7ff ff98 bl 800c8f0 800c9c0: 4603 mov r3, r0 800c9c2: 81fb strh r3, [r7, #14] if (packet_len > 0) { 800c9c4: 89fb ldrh r3, [r7, #14] 800c9c6: 2b00 cmp r3, #0 800c9c8: d01e beq.n 800ca08 if (huart2.gState == HAL_UART_STATE_BUSY_TX) { 800c9ca: 4b12 ldr r3, [pc, #72] @ (800ca14 ) 800c9cc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800c9d0: b2db uxtb r3, r3 800c9d2: 2b21 cmp r3, #33 @ 0x21 800c9d4: d107 bne.n 800c9e6 HAL_UART_Abort_IT(&huart2); 800c9d6: 480f ldr r0, [pc, #60] @ (800ca14 ) 800c9d8: f005 fbee bl 80121b8 HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800c9dc: 2200 movs r2, #0 800c9de: 2110 movs r1, #16 800c9e0: 480d ldr r0, [pc, #52] @ (800ca18 ) 800c9e2: f003 f8d6 bl 800fb92 } HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_SET); 800c9e6: 2201 movs r2, #1 800c9e8: 2110 movs r1, #16 800c9ea: 480b ldr r0, [pc, #44] @ (800ca18 ) 800c9ec: f003 f8d1 bl 800fb92 HAL_UART_Transmit_IT(&huart2, serial_control.tx_buffer, packet_len); 800c9f0: 89fb ldrh r3, [r7, #14] 800c9f2: 461a mov r2, r3 800c9f4: 4906 ldr r1, [pc, #24] @ (800ca10 ) 800c9f6: 4807 ldr r0, [pc, #28] @ (800ca14 ) 800c9f8: f005 fb4b bl 8012092 serial_control.tx_tick = HAL_GetTick(); 800c9fc: f001 f8b8 bl 800db70 800ca00: 4603 mov r3, r0 800ca02: 4a03 ldr r2, [pc, #12] @ (800ca10 ) 800ca04: f8c2 320c str.w r3, [r2, #524] @ 0x20c } } 800ca08: bf00 nop 800ca0a: 3710 adds r7, #16 800ca0c: 46bd mov sp, r7 800ca0e: bd80 pop {r7, pc} 800ca10: 20000ba0 .word 0x20000ba0 800ca14: 2000114c .word 0x2000114c 800ca18: 40011400 .word 0x40011400 0800ca1c : static uint8_t parse_packet(const uint8_t* packet_data, uint16_t packet_len, ReceivedCommand_t* out_cmd) { 800ca1c: b580 push {r7, lr} 800ca1e: b088 sub sp, #32 800ca20: af00 add r7, sp, #0 800ca22: 60f8 str r0, [r7, #12] 800ca24: 460b mov r3, r1 800ca26: 607a str r2, [r7, #4] 800ca28: 817b strh r3, [r7, #10] // }else{ // test_crc_invalid = 5; // } // Минимальный размер: 1 байт команды + 4 байта CRC if (packet_len < 5) return 0; 800ca2a: 897b ldrh r3, [r7, #10] 800ca2c: 2b04 cmp r3, #4 800ca2e: d801 bhi.n 800ca34 800ca30: 2300 movs r3, #0 800ca32: e03f b.n 800cab4 if (packet_len > MAX_RX_BUFFER_SIZE) return 0; 800ca34: 897b ldrh r3, [r7, #10] 800ca36: f5b3 7f80 cmp.w r3, #256 @ 0x100 800ca3a: d901 bls.n 800ca40 800ca3c: 2300 movs r3, #0 800ca3e: e039 b.n 800cab4 uint16_t payload_length = packet_len - 4; 800ca40: 897b ldrh r3, [r7, #10] 800ca42: 3b04 subs r3, #4 800ca44: 83fb strh r3, [r7, #30] // Извлекаем принятую CRC (последние 4 байта, little-endian) uint32_t received_checksum = ((uint32_t)packet_data[payload_length] << 0) | 800ca46: 8bfb ldrh r3, [r7, #30] 800ca48: 68fa ldr r2, [r7, #12] 800ca4a: 4413 add r3, r2 800ca4c: 781b ldrb r3, [r3, #0] 800ca4e: 4619 mov r1, r3 ((uint32_t)packet_data[payload_length + 1] << 8) | 800ca50: 8bfb ldrh r3, [r7, #30] 800ca52: 3301 adds r3, #1 800ca54: 68fa ldr r2, [r7, #12] 800ca56: 4413 add r3, r2 800ca58: 781b ldrb r3, [r3, #0] 800ca5a: 021b lsls r3, r3, #8 ((uint32_t)packet_data[payload_length] << 0) | 800ca5c: ea41 0203 orr.w r2, r1, r3 ((uint32_t)packet_data[payload_length + 2] << 16) | 800ca60: 8bfb ldrh r3, [r7, #30] 800ca62: 3302 adds r3, #2 800ca64: 68f9 ldr r1, [r7, #12] 800ca66: 440b add r3, r1 800ca68: 781b ldrb r3, [r3, #0] 800ca6a: 041b lsls r3, r3, #16 ((uint32_t)packet_data[payload_length + 1] << 8) | 800ca6c: 431a orrs r2, r3 ((uint32_t)packet_data[payload_length + 3] << 24); 800ca6e: 8bfb ldrh r3, [r7, #30] 800ca70: 3303 adds r3, #3 800ca72: 68f9 ldr r1, [r7, #12] 800ca74: 440b add r3, r1 800ca76: 781b ldrb r3, [r3, #0] 800ca78: 061b lsls r3, r3, #24 uint32_t received_checksum = 800ca7a: 4313 orrs r3, r2 800ca7c: 61bb str r3, [r7, #24] // Вычисляем CRC для полезной нагрузки uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); 800ca7e: 8bfb ldrh r3, [r7, #30] 800ca80: 4619 mov r1, r3 800ca82: 68f8 ldr r0, [r7, #12] 800ca84: f7ff fef8 bl 800c878 800ca88: 6178 str r0, [r7, #20] if (received_checksum != calculated_checksum) return 0; // CRC не совпадает 800ca8a: 69ba ldr r2, [r7, #24] 800ca8c: 697b ldr r3, [r7, #20] 800ca8e: 429a cmp r2, r3 800ca90: d001 beq.n 800ca96 800ca92: 2300 movs r3, #0 800ca94: e00e b.n 800cab4 out_cmd->argument = (void *)&packet_data[1]; 800ca96: 68fb ldr r3, [r7, #12] 800ca98: 1c5a adds r2, r3, #1 800ca9a: 687b ldr r3, [r7, #4] 800ca9c: 605a str r2, [r3, #4] out_cmd->command = packet_data[0]; 800ca9e: 68fb ldr r3, [r7, #12] 800caa0: 781a ldrb r2, [r3, #0] 800caa2: 687b ldr r3, [r7, #4] 800caa4: 701a strb r2, [r3, #0] out_cmd->argument_length = (uint8_t)(payload_length - 1); 800caa6: 8bfb ldrh r3, [r7, #30] 800caa8: b2db uxtb r3, r3 800caaa: 3b01 subs r3, #1 800caac: b2da uxtb r2, r3 800caae: 687b ldr r3, [r7, #4] 800cab0: 705a strb r2, [r3, #1] return 1; 800cab2: 2301 movs r3, #1 } 800cab4: 4618 mov r0, r3 800cab6: 3720 adds r7, #32 800cab8: 46bd mov sp, r7 800caba: bd80 pop {r7, pc} 0800cabc : static uint8_t process_received_packet(SerialControl_t *ctx, const uint8_t* packet_data, uint16_t packet_len) { 800cabc: b580 push {r7, lr} 800cabe: b084 sub sp, #16 800cac0: af00 add r7, sp, #0 800cac2: 60f8 str r0, [r7, #12] 800cac4: 60b9 str r1, [r7, #8] 800cac6: 4613 mov r3, r2 800cac8: 80fb strh r3, [r7, #6] if (!parse_packet(packet_data, packet_len, (ReceivedCommand_t *)&ctx->received_command)) { 800caca: 68fb ldr r3, [r7, #12] 800cacc: f503 7200 add.w r2, r3, #512 @ 0x200 800cad0: 88fb ldrh r3, [r7, #6] 800cad2: 4619 mov r1, r3 800cad4: 68b8 ldr r0, [r7, #8] 800cad6: f7ff ffa1 bl 800ca1c 800cada: 4603 mov r3, r0 800cadc: 2b00 cmp r3, #0 800cade: d101 bne.n 800cae4 return 0; 800cae0: 2300 movs r3, #0 800cae2: e004 b.n 800caee } ctx->command_ready = 1; 800cae4: 68fb ldr r3, [r7, #12] 800cae6: 2201 movs r2, #1 800cae8: f883 2208 strb.w r2, [r3, #520] @ 0x208 return 1; 800caec: 2301 movs r3, #1 } 800caee: 4618 mov r0, r3 800caf0: 3710 adds r7, #16 800caf2: 46bd mov sp, r7 800caf4: bd80 pop {r7, pc} ... 0800caf8 <__NVIC_SystemReset>: { 800caf8: b480 push {r7} 800cafa: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 800cafc: f3bf 8f4f dsb sy } 800cb00: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800cb02: 4b06 ldr r3, [pc, #24] @ (800cb1c <__NVIC_SystemReset+0x24>) 800cb04: 68db ldr r3, [r3, #12] 800cb06: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800cb0a: 4904 ldr r1, [pc, #16] @ (800cb1c <__NVIC_SystemReset+0x24>) 800cb0c: 4b04 ldr r3, [pc, #16] @ (800cb20 <__NVIC_SystemReset+0x28>) 800cb0e: 4313 orrs r3, r2 800cb10: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800cb12: f3bf 8f4f dsb sy } 800cb16: bf00 nop __NOP(); 800cb18: bf00 nop 800cb1a: e7fd b.n 800cb18 <__NVIC_SystemReset+0x20> 800cb1c: e000ed00 .word 0xe000ed00 800cb20: 05fa0004 .word 0x05fa0004 0800cb24 : .chargerNumber = 00001, .unixTime = 1721651966, }; // Единая функция-обработчик всех команд со switch-case void SC_CommandHandler(ReceivedCommand_t* cmd) { 800cb24: b580 push {r7, lr} 800cb26: b084 sub sp, #16 800cb28: af00 add r7, sp, #0 800cb2a: 6078 str r0, [r7, #4] uint8_t response_code = RESP_FAILED; 800cb2c: 2313 movs r3, #19 800cb2e: 73fb strb r3, [r7, #15] switch (cmd->command) { 800cb30: 687b ldr r3, [r7, #4] 800cb32: 781b ldrb r3, [r3, #0] 800cb34: 2bc2 cmp r3, #194 @ 0xc2 800cb36: f300 80cc bgt.w 800ccd2 800cb3a: 2bb0 cmp r3, #176 @ 0xb0 800cb3c: da0f bge.n 800cb5e 800cb3e: 2b60 cmp r3, #96 @ 0x60 800cb40: d042 beq.n 800cbc8 800cb42: 2b60 cmp r3, #96 @ 0x60 800cb44: f300 80c5 bgt.w 800ccd2 800cb48: 2b50 cmp r3, #80 @ 0x50 800cb4a: d043 beq.n 800cbd4 800cb4c: 2b50 cmp r3, #80 @ 0x50 800cb4e: f300 80c0 bgt.w 800ccd2 800cb52: 2b01 cmp r3, #1 800cb54: f000 80a6 beq.w 800cca4 800cb58: 2b40 cmp r3, #64 @ 0x40 800cb5a: d02d beq.n 800cbb8 800cb5c: e0b9 b.n 800ccd2 800cb5e: 3bb0 subs r3, #176 @ 0xb0 800cb60: 2b12 cmp r3, #18 800cb62: f200 80b6 bhi.w 800ccd2 800cb66: a201 add r2, pc, #4 @ (adr r2, 800cb6c ) 800cb68: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800cb6c: 0800cbdb .word 0x0800cbdb 800cb70: 0800ccd3 .word 0x0800ccd3 800cb74: 0800ccd3 .word 0x0800ccd3 800cb78: 0800ccd3 .word 0x0800ccd3 800cb7c: 0800ccd3 .word 0x0800ccd3 800cb80: 0800cc83 .word 0x0800cc83 800cb84: 0800ccd3 .word 0x0800ccd3 800cb88: 0800ccd3 .word 0x0800ccd3 800cb8c: 0800ccd3 .word 0x0800ccd3 800cb90: 0800ccd3 .word 0x0800ccd3 800cb94: 0800ccd3 .word 0x0800ccd3 800cb98: 0800ccd3 .word 0x0800ccd3 800cb9c: 0800ccd3 .word 0x0800ccd3 800cba0: 0800ccd3 .word 0x0800ccd3 800cba4: 0800ccd3 .word 0x0800ccd3 800cba8: 0800ccd3 .word 0x0800ccd3 800cbac: 0800cc19 .word 0x0800cc19 800cbb0: 0800cc7d .word 0x0800cc7d 800cbb4: 0800cc51 .word 0x0800cc51 // Команды БЕЗ аргументов case CMD_GET_STATUS: // Логика получения информации monitoring_data_callback(); 800cbb8: f000 f8b2 bl 800cd20 // Отправляем с нормальным приоритетом SC_SendPacket((uint8_t*)&statusPacket, sizeof(statusPacket), CMD_GET_STATUS); 800cbbc: 2240 movs r2, #64 @ 0x40 800cbbe: 2158 movs r1, #88 @ 0x58 800cbc0: 484b ldr r0, [pc, #300] @ (800ccf0 ) 800cbc2: f7ff feef bl 800c9a4 return; // Специальный ответ уже отправлен 800cbc6: e08f b.n 800cce8 case CMD_GET_INFO: SC_SendPacket((uint8_t*)&infoPacket, sizeof(infoPacket), CMD_GET_INFO); 800cbc8: 2260 movs r2, #96 @ 0x60 800cbca: 210a movs r1, #10 800cbcc: 4849 ldr r0, [pc, #292] @ (800ccf4 ) 800cbce: f7ff fee9 bl 800c9a4 return; 800cbd2: e089 b.n 800cce8 case CMD_GET_LOG: debug_buffer_send(); 800cbd4: f7fd fcc0 bl 800a558 return; // Ответ формируется внутри debug_buffer_send 800cbd8: e086 b.n 800cce8 // Команды С аргументами case CMD_SET_CONFIG: if (cmd->argument_length == sizeof(ConfigBlock_t)) { 800cbda: 687b ldr r3, [r7, #4] 800cbdc: 785b ldrb r3, [r3, #1] 800cbde: 2b0b cmp r3, #11 800cbe0: d117 bne.n 800cc12 memcpy(&config, cmd->argument, sizeof(ConfigBlock_t)); 800cbe2: 687b ldr r3, [r7, #4] 800cbe4: 685a ldr r2, [r3, #4] 800cbe6: 4b44 ldr r3, [pc, #272] @ (800ccf8 ) 800cbe8: 6810 ldr r0, [r2, #0] 800cbea: 6851 ldr r1, [r2, #4] 800cbec: c303 stmia r3!, {r0, r1} 800cbee: 8911 ldrh r1, [r2, #8] 800cbf0: 7a92 ldrb r2, [r2, #10] 800cbf2: 8019 strh r1, [r3, #0] 800cbf4: 709a strb r2, [r3, #2] config_initialized = 1; 800cbf6: 4b41 ldr r3, [pc, #260] @ (800ccfc ) 800cbf8: 2201 movs r2, #1 800cbfa: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Set Config: %s %d\n", config.location, config.chargerNumber); 800cbfc: 4b3e ldr r3, [pc, #248] @ (800ccf8 ) 800cbfe: f8d3 3003 ldr.w r3, [r3, #3] 800cc02: 4a3d ldr r2, [pc, #244] @ (800ccf8 ) 800cc04: 493e ldr r1, [pc, #248] @ (800cd00 ) 800cc06: 2007 movs r0, #7 800cc08: f7fd fd08 bl 800a61c response_code = RESP_SUCCESS; 800cc0c: 2312 movs r3, #18 800cc0e: 73fb strb r3, [r7, #15] break; 800cc10: e062 b.n 800ccd8 } response_code = RESP_FAILED; 800cc12: 2313 movs r3, #19 800cc14: 73fb strb r3, [r7, #15] break; 800cc16: e05f b.n 800ccd8 case CMD_SET_POWER_LIMIT: if (cmd->argument_length == 1) { 800cc18: 687b ldr r3, [r7, #4] 800cc1a: 785b ldrb r3, [r3, #1] 800cc1c: 2b01 cmp r3, #1 800cc1e: d114 bne.n 800cc4a PSU0.power_limit = ((uint8_t*)cmd->argument)[0] * 1000; 800cc20: 687b ldr r3, [r7, #4] 800cc22: 685b ldr r3, [r3, #4] 800cc24: 781b ldrb r3, [r3, #0] 800cc26: 461a mov r2, r3 800cc28: f44f 737a mov.w r3, #1000 @ 0x3e8 800cc2c: fb02 f303 mul.w r3, r2, r3 800cc30: 461a mov r2, r3 800cc32: 4b34 ldr r3, [pc, #208] @ (800cd04 ) 800cc34: 615a str r2, [r3, #20] log_printf(LOG_INFO, "Power limit: %d\n", PSU0.power_limit); 800cc36: 4b33 ldr r3, [pc, #204] @ (800cd04 ) 800cc38: 695b ldr r3, [r3, #20] 800cc3a: 461a mov r2, r3 800cc3c: 4932 ldr r1, [pc, #200] @ (800cd08 ) 800cc3e: 2007 movs r0, #7 800cc40: f7fd fcec bl 800a61c //CONN.connState = (((uint8_t*)cmd->argument)[0])/4; response_code = RESP_SUCCESS; 800cc44: 2312 movs r3, #18 800cc46: 73fb strb r3, [r7, #15] break; 800cc48: e046 b.n 800ccd8 } response_code = RESP_FAILED; 800cc4a: 2313 movs r3, #19 800cc4c: 73fb strb r3, [r7, #15] break; 800cc4e: e043 b.n 800ccd8 case CMD_CHARGE_PERMIT: if (cmd->argument_length == 1) { 800cc50: 687b ldr r3, [r7, #4] 800cc52: 785b ldrb r3, [r3, #1] 800cc54: 2b01 cmp r3, #1 800cc56: d10e bne.n 800cc76 CONN.connControl = ((uint8_t*)cmd->argument)[0]; 800cc58: 687b ldr r3, [r7, #4] 800cc5a: 685b ldr r3, [r3, #4] 800cc5c: 781a ldrb r2, [r3, #0] 800cc5e: 4b2b ldr r3, [pc, #172] @ (800cd0c ) 800cc60: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Charge permit: %d\n", CONN.connControl); 800cc62: 4b2a ldr r3, [pc, #168] @ (800cd0c ) 800cc64: 781b ldrb r3, [r3, #0] 800cc66: 461a mov r2, r3 800cc68: 4929 ldr r1, [pc, #164] @ (800cd10 ) 800cc6a: 2007 movs r0, #7 800cc6c: f7fd fcd6 bl 800a61c response_code = RESP_SUCCESS; 800cc70: 2312 movs r3, #18 800cc72: 73fb strb r3, [r7, #15] break; 800cc74: e030 b.n 800ccd8 } response_code = RESP_FAILED; 800cc76: 2313 movs r3, #19 800cc78: 73fb strb r3, [r7, #15] break; 800cc7a: e02d b.n 800ccd8 // memcpy(&PSU_TestMode, cmd->argument, sizeof(PSU_TestMode_t)); // log_printf(LOG_INFO, "Test PSU: %d %d %d\n", PSU_TestMode.enable, PSU_TestMode.voltage, PSU_TestMode.current); // response_code = RESP_SUCCESS; // break; // } response_code = RESP_FAILED; 800cc7c: 2313 movs r3, #19 800cc7e: 73fb strb r3, [r7, #15] break; 800cc80: e02a b.n 800ccd8 case CMD_DEVICE_RESET: // 2. Отправляем SUCCESS (хост может успеть получить его перед ребутом) SC_SendPacket(NULL, 0, RESP_SUCCESS); 800cc82: 2212 movs r2, #18 800cc84: 2100 movs r1, #0 800cc86: 2000 movs r0, #0 800cc88: f7ff fe8c bl 800c9a4 while(huart2.gState == HAL_UART_STATE_BUSY_TX); // Ожидание завершения передачи 800cc8c: bf00 nop 800cc8e: 4b21 ldr r3, [pc, #132] @ (800cd14 ) 800cc90: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800cc94: b2db uxtb r3, r3 800cc96: 2b21 cmp r3, #33 @ 0x21 800cc98: d0f9 beq.n 800cc8e HAL_Delay(10); 800cc9a: 200a movs r0, #10 800cc9c: f000 ff72 bl 800db84 // 3. Выполняем программный сброс NVIC_SystemReset(); 800cca0: f7ff ff2a bl 800caf8 <__NVIC_SystemReset> return; // Сюда код уже не дойдет, но для компилятора нxужно case CMD_ISOLATION_STATUS: if (cmd->argument_length == sizeof(IsolationStatusPacket_t)) { 800cca4: 687b ldr r3, [r7, #4] 800cca6: 785b ldrb r3, [r3, #1] 800cca8: 2b09 cmp r3, #9 800ccaa: d10f bne.n 800cccc memcpy(&ISO, cmd->argument, sizeof(IsolationStatusPacket_t)); 800ccac: 687b ldr r3, [r7, #4] 800ccae: 685a ldr r2, [r3, #4] 800ccb0: 4b19 ldr r3, [pc, #100] @ (800cd18 ) 800ccb2: 6810 ldr r0, [r2, #0] 800ccb4: 6851 ldr r1, [r2, #4] 800ccb6: c303 stmia r3!, {r0, r1} 800ccb8: 7a12 ldrb r2, [r2, #8] 800ccba: 701a strb r2, [r3, #0] // Для однонаправленного UART5 ответ не нужен if (g_sc_command_source == SC_SOURCE_UART5) { 800ccbc: 4b17 ldr r3, [pc, #92] @ (800cd1c ) 800ccbe: 781b ldrb r3, [r3, #0] 800ccc0: b2db uxtb r3, r3 800ccc2: 2b01 cmp r3, #1 800ccc4: d00f beq.n 800cce6 return; } response_code = RESP_SUCCESS; 800ccc6: 2312 movs r3, #18 800ccc8: 73fb strb r3, [r7, #15] break; 800ccca: e005 b.n 800ccd8 } response_code = RESP_FAILED; 800cccc: 2313 movs r3, #19 800ccce: 73fb strb r3, [r7, #15] break; 800ccd0: e002 b.n 800ccd8 default: // Неизвестная команда response_code = RESP_FAILED; 800ccd2: 2313 movs r3, #19 800ccd4: 73fb strb r3, [r7, #15] break; 800ccd6: bf00 nop } // Отправляем финальный ответ (для команд без собственного ответа) SC_SendPacket(NULL, 0, response_code); 800ccd8: 7bfb ldrb r3, [r7, #15] 800ccda: 461a mov r2, r3 800ccdc: 2100 movs r1, #0 800ccde: 2000 movs r0, #0 800cce0: f7ff fe60 bl 800c9a4 800cce4: e000 b.n 800cce8 return; 800cce6: bf00 nop } 800cce8: 3710 adds r7, #16 800ccea: 46bd mov sp, r7 800ccec: bd80 pop {r7, pc} 800ccee: bf00 nop 800ccf0: 20000fc4 .word 0x20000fc4 800ccf4: 2000101c .word 0x2000101c 800ccf8: 20000060 .word 0x20000060 800ccfc: 20001026 .word 0x20001026 800cd00: 080160b4 .word 0x080160b4 800cd04: 2000088c .word 0x2000088c 800cd08: 080160c8 .word 0x080160c8 800cd0c: 2000033c .word 0x2000033c 800cd10: 080160dc .word 0x080160dc 800cd14: 2000114c .word 0x2000114c 800cd18: 20000054 .word 0x20000054 800cd1c: 20000fc0 .word 0x20000fc0 0800cd20 : // Колбэк для заполнения данных мониторинга void monitoring_data_callback() { 800cd20: b580 push {r7, lr} 800cd22: af00 add r7, sp, #0 // Информация о зарядной сессии statusPacket.SOC = CONN.SOC; 800cd24: 4b8f ldr r3, [pc, #572] @ (800cf64 ) 800cd26: 789a ldrb r2, [r3, #2] 800cd28: 4b8f ldr r3, [pc, #572] @ (800cf68 ) 800cd2a: 709a strb r2, [r3, #2] statusPacket.Energy = CONN.Energy; 800cd2c: 4b8d ldr r3, [pc, #564] @ (800cf64 ) 800cd2e: f8d3 3007 ldr.w r3, [r3, #7] 800cd32: 4a8d ldr r2, [pc, #564] @ (800cf68 ) 800cd34: f8c2 3003 str.w r3, [r2, #3] statusPacket.RequestedVoltage = CONN.RequestedVoltage; 800cd38: 4b8a ldr r3, [pc, #552] @ (800cf64 ) 800cd3a: f8b3 300f ldrh.w r3, [r3, #15] 800cd3e: b29a uxth r2, r3 800cd40: 4b89 ldr r3, [pc, #548] @ (800cf68 ) 800cd42: f8a3 2007 strh.w r2, [r3, #7] statusPacket.RequestedCurrent = CONN.WantedCurrent; 800cd46: 4b87 ldr r3, [pc, #540] @ (800cf64 ) 800cd48: f8b3 301b ldrh.w r3, [r3, #27] 800cd4c: b29a uxth r2, r3 800cd4e: 4b86 ldr r3, [pc, #536] @ (800cf68 ) 800cd50: f8a3 2009 strh.w r2, [r3, #9] statusPacket.MeasuredVoltage = CONN.MeasuredVoltage; 800cd54: 4b83 ldr r3, [pc, #524] @ (800cf64 ) 800cd56: f8b3 3013 ldrh.w r3, [r3, #19] 800cd5a: b29a uxth r2, r3 800cd5c: 4b82 ldr r3, [pc, #520] @ (800cf68 ) 800cd5e: f8a3 200b strh.w r2, [r3, #11] statusPacket.MeasuredCurrent = CONN.MeasuredCurrent; 800cd62: 4b80 ldr r3, [pc, #512] @ (800cf64 ) 800cd64: f8b3 3015 ldrh.w r3, [r3, #21] 800cd68: b29a uxth r2, r3 800cd6a: 4b7f ldr r3, [pc, #508] @ (800cf68 ) 800cd6c: f8a3 200d strh.w r2, [r3, #13] statusPacket.outputEnabled = CONN.outputEnabled; 800cd70: 4b7c ldr r3, [pc, #496] @ (800cf64 ) 800cd72: 7e1a ldrb r2, [r3, #24] 800cd74: 4b7c ldr r3, [pc, #496] @ (800cf68 ) 800cd76: 73da strb r2, [r3, #15] statusPacket.chargingError = CONN.chargingError; 800cd78: 4b7a ldr r3, [pc, #488] @ (800cf64 ) 800cd7a: 7f5a ldrb r2, [r3, #29] 800cd7c: 4b7a ldr r3, [pc, #488] @ (800cf68 ) 800cd7e: 705a strb r2, [r3, #1] statusPacket.connState = CONN.connState; 800cd80: 4b78 ldr r3, [pc, #480] @ (800cf64 ) 800cd82: 785a ldrb r2, [r3, #1] 800cd84: 4b78 ldr r3, [pc, #480] @ (800cf68 ) 800cd86: 701a strb r2, [r3, #0] statusPacket.chargingElapsedTimeMin = 0; 800cd88: 4b77 ldr r3, [pc, #476] @ (800cf68 ) 800cd8a: 2200 movs r2, #0 800cd8c: 741a strb r2, [r3, #16] 800cd8e: 2200 movs r2, #0 800cd90: 745a strb r2, [r3, #17] statusPacket.chargingElapsedTimeSec = 0; 800cd92: 4b75 ldr r3, [pc, #468] @ (800cf68 ) 800cd94: 2200 movs r2, #0 800cd96: 749a strb r2, [r3, #18] statusPacket.estimatedRemainingChargingTime = 0; 800cd98: 4b73 ldr r3, [pc, #460] @ (800cf68 ) 800cd9a: 2200 movs r2, #0 800cd9c: 74da strb r2, [r3, #19] 800cd9e: 2200 movs r2, #0 800cda0: 751a strb r2, [r3, #20] // состояние зарядной станции statusPacket.relayAC = RELAY_Read(RELAY_AC); 800cda2: 2004 movs r0, #4 800cda4: f7fc fcc2 bl 800972c 800cda8: 4603 mov r3, r0 800cdaa: f003 0301 and.w r3, r3, #1 800cdae: b2d9 uxtb r1, r3 800cdb0: 4a6d ldr r2, [pc, #436] @ (800cf68 ) 800cdb2: 7d53 ldrb r3, [r2, #21] 800cdb4: f361 0300 bfi r3, r1, #0, #1 800cdb8: 7553 strb r3, [r2, #21] statusPacket.relayDC = RELAY_Read(RELAY_DC); 800cdba: 2003 movs r0, #3 800cdbc: f7fc fcb6 bl 800972c 800cdc0: 4603 mov r3, r0 800cdc2: f003 0301 and.w r3, r3, #1 800cdc6: b2d9 uxtb r1, r3 800cdc8: 4a67 ldr r2, [pc, #412] @ (800cf68 ) 800cdca: 7d53 ldrb r3, [r2, #21] 800cdcc: f361 0341 bfi r3, r1, #1, #1 800cdd0: 7553 strb r3, [r2, #21] statusPacket.relayAUX = RELAY_Read(RELAY_AUX0); 800cdd2: 2000 movs r0, #0 800cdd4: f7fc fcaa bl 800972c 800cdd8: 4603 mov r3, r0 800cdda: f003 0301 and.w r3, r3, #1 800cdde: b2d9 uxtb r1, r3 800cde0: 4a61 ldr r2, [pc, #388] @ (800cf68 ) 800cde2: 7d53 ldrb r3, [r2, #21] 800cde4: f361 0382 bfi r3, r1, #2, #1 800cde8: 7553 strb r3, [r2, #21] statusPacket.lockState = 0; 800cdea: 4a5f ldr r2, [pc, #380] @ (800cf68 ) 800cdec: 7d53 ldrb r3, [r2, #21] 800cdee: f023 0308 bic.w r3, r3, #8 800cdf2: 7553 strb r3, [r2, #21] statusPacket.stopButton = !IN_ReadInput(IN_ESTOP); 800cdf4: 2003 movs r0, #3 800cdf6: f7fc fca9 bl 800974c 800cdfa: 4603 mov r3, r0 800cdfc: 2b00 cmp r3, #0 800cdfe: bf0c ite eq 800ce00: 2301 moveq r3, #1 800ce02: 2300 movne r3, #0 800ce04: b2d9 uxtb r1, r3 800ce06: 4a58 ldr r2, [pc, #352] @ (800cf68 ) 800ce08: 7d53 ldrb r3, [r2, #21] 800ce0a: f361 1304 bfi r3, r1, #4, #1 800ce0e: 7553 strb r3, [r2, #21] statusPacket.logAvailable = (debug_buffer_available()>0)?1:0; 800ce10: f7fd fb8e bl 800a530 800ce14: 4603 mov r3, r0 800ce16: 2b00 cmp r3, #0 800ce18: bf14 ite ne 800ce1a: 2301 movne r3, #1 800ce1c: 2300 moveq r3, #0 800ce1e: b2d9 uxtb r1, r3 800ce20: 4a51 ldr r2, [pc, #324] @ (800cf68 ) 800ce22: 7d53 ldrb r3, [r2, #21] 800ce24: f361 1345 bfi r3, r1, #5, #1 800ce28: 7553 strb r3, [r2, #21] statusPacket.evInfoAvailable = 0; 800ce2a: 4a4f ldr r2, [pc, #316] @ (800cf68 ) 800ce2c: 7d53 ldrb r3, [r2, #21] 800ce2e: f023 0340 bic.w r3, r3, #64 @ 0x40 800ce32: 7553 strb r3, [r2, #21] statusPacket.psuOnline = PSU0.online; 800ce34: 4b4d ldr r3, [pc, #308] @ (800cf6c ) 800ce36: 7a1b ldrb r3, [r3, #8] 800ce38: f003 0301 and.w r3, r3, #1 800ce3c: b2d9 uxtb r1, r3 800ce3e: 4a4a ldr r2, [pc, #296] @ (800cf68 ) 800ce40: 7d53 ldrb r3, [r2, #21] 800ce42: f361 13c7 bfi r3, r1, #7, #1 800ce46: 7553 strb r3, [r2, #21] statusPacket.tempConnector0 = CONN_ReadTemp(0); // температура коннектора 800ce48: 2000 movs r0, #0 800ce4a: f7fc fd73 bl 8009934 800ce4e: 4603 mov r3, r0 800ce50: b25a sxtb r2, r3 800ce52: 4b45 ldr r3, [pc, #276] @ (800cf68 ) 800ce54: 765a strb r2, [r3, #25] statusPacket.tempConnector1 = CONN_ReadTemp(1); 800ce56: 2001 movs r0, #1 800ce58: f7fc fd6c bl 8009934 800ce5c: 4603 mov r3, r0 800ce5e: b25a sxtb r2, r3 800ce60: 4b41 ldr r3, [pc, #260] @ (800cf68 ) 800ce62: 769a strb r2, [r3, #26] statusPacket.tempAmbient = PSU0.tempAmbient; // температура окружающего воздуха 800ce64: 4b41 ldr r3, [pc, #260] @ (800cf6c ) 800ce66: 69db ldr r3, [r3, #28] 800ce68: b25a sxtb r2, r3 800ce6a: 4b3f ldr r3, [pc, #252] @ (800cf68 ) 800ce6c: 76da strb r2, [r3, #27] statusPacket.tempBatteryMax = 0; 800ce6e: 4b3e ldr r3, [pc, #248] @ (800cf68 ) 800ce70: 2200 movs r2, #0 800ce72: 771a strb r2, [r3, #28] statusPacket.tempBatteryMin = 0; 800ce74: 4b3c ldr r3, [pc, #240] @ (800cf68 ) 800ce76: 2200 movs r2, #0 800ce78: 775a strb r2, [r3, #29] statusPacket.highestVoltageOfBatteryCell = 0; 800ce7a: 4b3b ldr r3, [pc, #236] @ (800cf68 ) 800ce7c: 2200 movs r2, #0 800ce7e: 779a strb r2, [r3, #30] 800ce80: 2200 movs r2, #0 800ce82: 77da strb r2, [r3, #31] statusPacket.batteryStatus = 0; 800ce84: 4b38 ldr r3, [pc, #224] @ (800cf68 ) 800ce86: 2200 movs r2, #0 800ce88: f883 2020 strb.w r2, [r3, #32] statusPacket.phaseVoltageAB = PSU_06.VAB; 800ce8c: 4b38 ldr r3, [pc, #224] @ (800cf70 ) 800ce8e: 689b ldr r3, [r3, #8] 800ce90: b29a uxth r2, r3 800ce92: 4b35 ldr r3, [pc, #212] @ (800cf68 ) 800ce94: f8a3 2021 strh.w r2, [r3, #33] @ 0x21 statusPacket.phaseVoltageBC = PSU_06.VBC; 800ce98: 4b35 ldr r3, [pc, #212] @ (800cf70 ) 800ce9a: 68db ldr r3, [r3, #12] 800ce9c: b29a uxth r2, r3 800ce9e: 4b32 ldr r3, [pc, #200] @ (800cf68 ) 800cea0: f8a3 2023 strh.w r2, [r3, #35] @ 0x23 statusPacket.phaseVoltageCA = PSU_06.VCA; 800cea4: 4b32 ldr r3, [pc, #200] @ (800cf70 ) 800cea6: 691b ldr r3, [r3, #16] 800cea8: b29a uxth r2, r3 800ceaa: 4b2f ldr r3, [pc, #188] @ (800cf68 ) 800ceac: f8a3 2025 strh.w r2, [r3, #37] @ 0x25 // GBT TODO memset(statusPacket.VIN, 0, sizeof(statusPacket.VIN)); 800ceb0: 2211 movs r2, #17 800ceb2: 2100 movs r1, #0 800ceb4: 482f ldr r0, [pc, #188] @ (800cf74 ) 800ceb6: f006 fde3 bl 8013a80 // GBT TODO statusPacket.batteryType = 0; 800ceba: 4b2b ldr r3, [pc, #172] @ (800cf68 ) 800cebc: 2200 movs r2, #0 800cebe: f883 2038 strb.w r2, [r3, #56] @ 0x38 statusPacket.batteryCapacity = 0; 800cec2: 4b29 ldr r3, [pc, #164] @ (800cf68 ) 800cec4: 2200 movs r2, #0 800cec6: f883 2039 strb.w r2, [r3, #57] @ 0x39 800ceca: 2200 movs r2, #0 800cecc: f883 203a strb.w r2, [r3, #58] @ 0x3a statusPacket.batteryVoltage = 0; 800ced0: 4b25 ldr r3, [pc, #148] @ (800cf68 ) 800ced2: 2200 movs r2, #0 800ced4: f883 203b strb.w r2, [r3, #59] @ 0x3b 800ced8: 2200 movs r2, #0 800ceda: f883 203c strb.w r2, [r3, #60] @ 0x3c memset(statusPacket.batteryVendor, 0, sizeof(statusPacket.batteryVendor)); 800cede: 2204 movs r2, #4 800cee0: 2100 movs r1, #0 800cee2: 4825 ldr r0, [pc, #148] @ (800cf78 ) 800cee4: f006 fdcc bl 8013a80 statusPacket.batterySN = 0; 800cee8: 4b1f ldr r3, [pc, #124] @ (800cf68 ) 800ceea: 2200 movs r2, #0 800ceec: f883 2041 strb.w r2, [r3, #65] @ 0x41 800cef0: 2200 movs r2, #0 800cef2: f883 2042 strb.w r2, [r3, #66] @ 0x42 800cef6: 2200 movs r2, #0 800cef8: f883 2043 strb.w r2, [r3, #67] @ 0x43 800cefc: 2200 movs r2, #0 800cefe: f883 2044 strb.w r2, [r3, #68] @ 0x44 statusPacket.batteryManuD = 0; 800cf02: 4b19 ldr r3, [pc, #100] @ (800cf68 ) 800cf04: 2200 movs r2, #0 800cf06: f883 2047 strb.w r2, [r3, #71] @ 0x47 statusPacket.batteryManuM = 0; 800cf0a: 4b17 ldr r3, [pc, #92] @ (800cf68 ) 800cf0c: 2200 movs r2, #0 800cf0e: f883 2046 strb.w r2, [r3, #70] @ 0x46 statusPacket.batteryManuY = 0; 800cf12: 4b15 ldr r3, [pc, #84] @ (800cf68 ) 800cf14: 2200 movs r2, #0 800cf16: f883 2045 strb.w r2, [r3, #69] @ 0x45 statusPacket.batteryCycleCount = 0; 800cf1a: 4b13 ldr r3, [pc, #76] @ (800cf68 ) 800cf1c: 2200 movs r2, #0 800cf1e: f883 2048 strb.w r2, [r3, #72] @ 0x48 800cf22: 2200 movs r2, #0 800cf24: f883 2049 strb.w r2, [r3, #73] @ 0x49 statusPacket.ownAuto = 0; 800cf28: 4b0f ldr r3, [pc, #60] @ (800cf68 ) 800cf2a: 2200 movs r2, #0 800cf2c: f883 204a strb.w r2, [r3, #74] @ 0x4a memset(statusPacket.EV_SW_VER, 0, sizeof(statusPacket.EV_SW_VER)); 800cf30: 2208 movs r2, #8 800cf32: 2100 movs r1, #0 800cf34: 4811 ldr r0, [pc, #68] @ (800cf7c ) 800cf36: f006 fda3 bl 8013a80 statusPacket.testMode = 0; 800cf3a: 4b0b ldr r3, [pc, #44] @ (800cf68 ) 800cf3c: 2200 movs r2, #0 800cf3e: f883 2053 strb.w r2, [r3, #83] @ 0x53 statusPacket.testVoltage = 0; 800cf42: 4b09 ldr r3, [pc, #36] @ (800cf68 ) 800cf44: 2200 movs r2, #0 800cf46: f883 2054 strb.w r2, [r3, #84] @ 0x54 800cf4a: 2200 movs r2, #0 800cf4c: f883 2055 strb.w r2, [r3, #85] @ 0x55 statusPacket.testCurrent = 0; 800cf50: 4b05 ldr r3, [pc, #20] @ (800cf68 ) 800cf52: 2200 movs r2, #0 800cf54: f883 2056 strb.w r2, [r3, #86] @ 0x56 800cf58: 2200 movs r2, #0 800cf5a: f883 2057 strb.w r2, [r3, #87] @ 0x57 // В debug.c есть CONN_SetState, предполагаем наличие CONN_GetState() // Если такой функции нет, закомментируйте следующую строку: // statusPacket.connState = CONN_GetState(); } 800cf5e: bf00 nop 800cf60: bd80 pop {r7, pc} 800cf62: bf00 nop 800cf64: 2000033c .word 0x2000033c 800cf68: 20000fc4 .word 0x20000fc4 800cf6c: 2000088c .word 0x2000088c 800cf70: 20000860 .word 0x20000860 800cf74: 20000feb .word 0x20000feb 800cf78: 20001001 .word 0x20001001 800cf7c: 2000100f .word 0x2000100f 0800cf80 : #include "sma_filter.h" void SMAFilter_Init(SMAFilter_t* f) { 800cf80: b480 push {r7} 800cf82: b085 sub sp, #20 800cf84: af00 add r7, sp, #0 800cf86: 6078 str r0, [r7, #4] if (f == 0) return; 800cf88: 687b ldr r3, [r7, #4] 800cf8a: 2b00 cmp r3, #0 800cf8c: d018 beq.n 800cfc0 f->sum = 0; 800cf8e: 687b ldr r3, [r7, #4] 800cf90: 2200 movs r2, #0 800cf92: 601a str r2, [r3, #0] f->idx = 0; 800cf94: 687b ldr r3, [r7, #4] 800cf96: 2200 movs r2, #0 800cf98: 809a strh r2, [r3, #4] f->count = 0; 800cf9a: 687b ldr r3, [r7, #4] 800cf9c: 2200 movs r2, #0 800cf9e: 80da strh r2, [r3, #6] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800cfa0: 2300 movs r3, #0 800cfa2: 81fb strh r3, [r7, #14] 800cfa4: e008 b.n 800cfb8 f->buffer[i] = 0; 800cfa6: 89fa ldrh r2, [r7, #14] 800cfa8: 687b ldr r3, [r7, #4] 800cfaa: 3202 adds r2, #2 800cfac: 2100 movs r1, #0 800cfae: f843 1022 str.w r1, [r3, r2, lsl #2] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800cfb2: 89fb ldrh r3, [r7, #14] 800cfb4: 3301 adds r3, #1 800cfb6: 81fb strh r3, [r7, #14] 800cfb8: 89fb ldrh r3, [r7, #14] 800cfba: 2b07 cmp r3, #7 800cfbc: d9f3 bls.n 800cfa6 800cfbe: e000 b.n 800cfc2 if (f == 0) return; 800cfc0: bf00 nop } } 800cfc2: 3714 adds r7, #20 800cfc4: 46bd mov sp, r7 800cfc6: bc80 pop {r7} 800cfc8: 4770 bx lr 0800cfca : int32_t SMAFilter_Update(SMAFilter_t* f, int32_t x) { 800cfca: b480 push {r7} 800cfcc: b085 sub sp, #20 800cfce: af00 add r7, sp, #0 800cfd0: 6078 str r0, [r7, #4] 800cfd2: 6039 str r1, [r7, #0] if (f == 0) return x; 800cfd4: 687b ldr r3, [r7, #4] 800cfd6: 2b00 cmp r3, #0 800cfd8: d101 bne.n 800cfde 800cfda: 683b ldr r3, [r7, #0] 800cfdc: e056 b.n 800d08c // Пока окно не заполнено полностью, делим по фактическому count. if (f->count < SMA_FILTER_WINDOW) { 800cfde: 687b ldr r3, [r7, #4] 800cfe0: 88db ldrh r3, [r3, #6] 800cfe2: 2b07 cmp r3, #7 800cfe4: d827 bhi.n 800d036 f->buffer[f->idx] = x; 800cfe6: 687b ldr r3, [r7, #4] 800cfe8: 889b ldrh r3, [r3, #4] 800cfea: 461a mov r2, r3 800cfec: 687b ldr r3, [r7, #4] 800cfee: 3202 adds r2, #2 800cff0: 6839 ldr r1, [r7, #0] 800cff2: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += x; 800cff6: 687b ldr r3, [r7, #4] 800cff8: 681a ldr r2, [r3, #0] 800cffa: 683b ldr r3, [r7, #0] 800cffc: 441a add r2, r3 800cffe: 687b ldr r3, [r7, #4] 800d000: 601a str r2, [r3, #0] f->idx++; 800d002: 687b ldr r3, [r7, #4] 800d004: 889b ldrh r3, [r3, #4] 800d006: 3301 adds r3, #1 800d008: b29a uxth r2, r3 800d00a: 687b ldr r3, [r7, #4] 800d00c: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800d00e: 687b ldr r3, [r7, #4] 800d010: 889b ldrh r3, [r3, #4] 800d012: 2b07 cmp r3, #7 800d014: d902 bls.n 800d01c 800d016: 687b ldr r3, [r7, #4] 800d018: 2200 movs r2, #0 800d01a: 809a strh r2, [r3, #4] f->count++; 800d01c: 687b ldr r3, [r7, #4] 800d01e: 88db ldrh r3, [r3, #6] 800d020: 3301 adds r3, #1 800d022: b29a uxth r2, r3 800d024: 687b ldr r3, [r7, #4] 800d026: 80da strh r2, [r3, #6] return (int32_t)(f->sum / (int32_t)f->count); 800d028: 687b ldr r3, [r7, #4] 800d02a: 681b ldr r3, [r3, #0] 800d02c: 687a ldr r2, [r7, #4] 800d02e: 88d2 ldrh r2, [r2, #6] 800d030: fb93 f3f2 sdiv r3, r3, r2 800d034: e02a b.n 800d08c } // Окно заполнено: "вычитаем старое + добавляем новое". int32_t old = f->buffer[f->idx]; 800d036: 687b ldr r3, [r7, #4] 800d038: 889b ldrh r3, [r3, #4] 800d03a: 461a mov r2, r3 800d03c: 687b ldr r3, [r7, #4] 800d03e: 3202 adds r2, #2 800d040: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800d044: 60fb str r3, [r7, #12] f->buffer[f->idx] = x; 800d046: 687b ldr r3, [r7, #4] 800d048: 889b ldrh r3, [r3, #4] 800d04a: 461a mov r2, r3 800d04c: 687b ldr r3, [r7, #4] 800d04e: 3202 adds r2, #2 800d050: 6839 ldr r1, [r7, #0] 800d052: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += (x - old); 800d056: 687b ldr r3, [r7, #4] 800d058: 681a ldr r2, [r3, #0] 800d05a: 6839 ldr r1, [r7, #0] 800d05c: 68fb ldr r3, [r7, #12] 800d05e: 1acb subs r3, r1, r3 800d060: 441a add r2, r3 800d062: 687b ldr r3, [r7, #4] 800d064: 601a str r2, [r3, #0] f->idx++; 800d066: 687b ldr r3, [r7, #4] 800d068: 889b ldrh r3, [r3, #4] 800d06a: 3301 adds r3, #1 800d06c: b29a uxth r2, r3 800d06e: 687b ldr r3, [r7, #4] 800d070: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800d072: 687b ldr r3, [r7, #4] 800d074: 889b ldrh r3, [r3, #4] 800d076: 2b07 cmp r3, #7 800d078: d902 bls.n 800d080 800d07a: 687b ldr r3, [r7, #4] 800d07c: 2200 movs r2, #0 800d07e: 809a strh r2, [r3, #4] return (int32_t)(f->sum / (int32_t)SMA_FILTER_WINDOW); 800d080: 687b ldr r3, [r7, #4] 800d082: 681b ldr r3, [r3, #0] 800d084: 2b00 cmp r3, #0 800d086: da00 bge.n 800d08a 800d088: 3307 adds r3, #7 800d08a: 10db asrs r3, r3, #3 } 800d08c: 4618 mov r0, r3 800d08e: 3714 adds r7, #20 800d090: 46bd mov sp, r7 800d092: bc80 pop {r7} 800d094: 4770 bx lr ... 0800d098 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800d098: b480 push {r7} 800d09a: b085 sub sp, #20 800d09c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 800d09e: 4b15 ldr r3, [pc, #84] @ (800d0f4 ) 800d0a0: 699b ldr r3, [r3, #24] 800d0a2: 4a14 ldr r2, [pc, #80] @ (800d0f4 ) 800d0a4: f043 0301 orr.w r3, r3, #1 800d0a8: 6193 str r3, [r2, #24] 800d0aa: 4b12 ldr r3, [pc, #72] @ (800d0f4 ) 800d0ac: 699b ldr r3, [r3, #24] 800d0ae: f003 0301 and.w r3, r3, #1 800d0b2: 60bb str r3, [r7, #8] 800d0b4: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800d0b6: 4b0f ldr r3, [pc, #60] @ (800d0f4 ) 800d0b8: 69db ldr r3, [r3, #28] 800d0ba: 4a0e ldr r2, [pc, #56] @ (800d0f4 ) 800d0bc: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800d0c0: 61d3 str r3, [r2, #28] 800d0c2: 4b0c ldr r3, [pc, #48] @ (800d0f4 ) 800d0c4: 69db ldr r3, [r3, #28] 800d0c6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800d0ca: 607b str r3, [r7, #4] 800d0cc: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 800d0ce: 4b0a ldr r3, [pc, #40] @ (800d0f8 ) 800d0d0: 685b ldr r3, [r3, #4] 800d0d2: 60fb str r3, [r7, #12] 800d0d4: 68fb ldr r3, [r7, #12] 800d0d6: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 800d0da: 60fb str r3, [r7, #12] 800d0dc: 68fb ldr r3, [r7, #12] 800d0de: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 800d0e2: 60fb str r3, [r7, #12] 800d0e4: 4a04 ldr r2, [pc, #16] @ (800d0f8 ) 800d0e6: 68fb ldr r3, [r7, #12] 800d0e8: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800d0ea: bf00 nop 800d0ec: 3714 adds r7, #20 800d0ee: 46bd mov sp, r7 800d0f0: bc80 pop {r7} 800d0f2: 4770 bx lr 800d0f4: 40021000 .word 0x40021000 800d0f8: 40010000 .word 0x40010000 0800d0fc : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 800d0fc: b480 push {r7} 800d0fe: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800d100: bf00 nop 800d102: e7fd b.n 800d100 0800d104 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800d104: b480 push {r7} 800d106: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800d108: bf00 nop 800d10a: e7fd b.n 800d108 0800d10c : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 800d10c: b480 push {r7} 800d10e: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800d110: bf00 nop 800d112: e7fd b.n 800d110 0800d114 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 800d114: b480 push {r7} 800d116: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800d118: bf00 nop 800d11a: e7fd b.n 800d118 0800d11c : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 800d11c: b480 push {r7} 800d11e: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 800d120: bf00 nop 800d122: e7fd b.n 800d120 0800d124 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 800d124: b480 push {r7} 800d126: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800d128: bf00 nop 800d12a: 46bd mov sp, r7 800d12c: bc80 pop {r7} 800d12e: 4770 bx lr 0800d130 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 800d130: b480 push {r7} 800d132: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800d134: bf00 nop 800d136: 46bd mov sp, r7 800d138: bc80 pop {r7} 800d13a: 4770 bx lr 0800d13c : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800d13c: b480 push {r7} 800d13e: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800d140: bf00 nop 800d142: 46bd mov sp, r7 800d144: bc80 pop {r7} 800d146: 4770 bx lr 0800d148 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800d148: b580 push {r7, lr} 800d14a: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800d14c: f000 fcfe bl 800db4c /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 800d150: bf00 nop 800d152: bd80 pop {r7, pc} 0800d154 : /** * @brief This function handles CAN1 RX0 interrupt. */ void CAN1_RX0_IRQHandler(void) { 800d154: b580 push {r7, lr} 800d156: af00 add r7, sp, #0 /* USER CODE BEGIN CAN1_RX0_IRQn 0 */ /* USER CODE END CAN1_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan1); 800d158: 4802 ldr r0, [pc, #8] @ (800d164 ) 800d15a: f001 feef bl 800ef3c /* USER CODE BEGIN CAN1_RX0_IRQn 1 */ /* USER CODE END CAN1_RX0_IRQn 1 */ } 800d15e: bf00 nop 800d160: bd80 pop {r7, pc} 800d162: bf00 nop 800d164: 200002e8 .word 0x200002e8 0800d168 : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 800d168: b580 push {r7, lr} 800d16a: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_IRQn 0 */ /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 800d16c: 4802 ldr r0, [pc, #8] @ (800d178 ) 800d16e: f004 f8e5 bl 801133c /* USER CODE BEGIN TIM3_IRQn 1 */ /* USER CODE END TIM3_IRQn 1 */ } 800d172: bf00 nop 800d174: bd80 pop {r7, pc} 800d176: bf00 nop 800d178: 2000102c .word 0x2000102c 0800d17c : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 800d17c: b580 push {r7, lr} 800d17e: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 800d180: 4802 ldr r0, [pc, #8] @ (800d18c ) 800d182: f005 f92d bl 80123e0 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 800d186: bf00 nop 800d188: bd80 pop {r7, pc} 800d18a: bf00 nop 800d18c: 20001104 .word 0x20001104 0800d190 : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 800d190: b580 push {r7, lr} 800d192: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 800d194: 4802 ldr r0, [pc, #8] @ (800d1a0 ) 800d196: f005 f923 bl 80123e0 /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 800d19a: bf00 nop 800d19c: bd80 pop {r7, pc} 800d19e: bf00 nop 800d1a0: 2000114c .word 0x2000114c 0800d1a4 : /** * @brief This function handles USART3 global interrupt. */ void USART3_IRQHandler(void) { 800d1a4: b580 push {r7, lr} 800d1a6: af00 add r7, sp, #0 /* USER CODE BEGIN USART3_IRQn 0 */ /* USER CODE END USART3_IRQn 0 */ HAL_UART_IRQHandler(&huart3); 800d1a8: 4802 ldr r0, [pc, #8] @ (800d1b4 ) 800d1aa: f005 f919 bl 80123e0 /* USER CODE BEGIN USART3_IRQn 1 */ /* USER CODE END USART3_IRQn 1 */ } 800d1ae: bf00 nop 800d1b0: bd80 pop {r7, pc} 800d1b2: bf00 nop 800d1b4: 20001194 .word 0x20001194 0800d1b8 : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 800d1b8: b580 push {r7, lr} 800d1ba: af00 add r7, sp, #0 /* USER CODE BEGIN UART5_IRQn 0 */ /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 800d1bc: 4802 ldr r0, [pc, #8] @ (800d1c8 ) 800d1be: f005 f90f bl 80123e0 /* USER CODE BEGIN UART5_IRQn 1 */ /* USER CODE END UART5_IRQn 1 */ } 800d1c2: bf00 nop 800d1c4: bd80 pop {r7, pc} 800d1c6: bf00 nop 800d1c8: 200010bc .word 0x200010bc 0800d1cc : /** * @brief This function handles CAN2 TX interrupt. */ void CAN2_TX_IRQHandler(void) { 800d1cc: b580 push {r7, lr} 800d1ce: af00 add r7, sp, #0 /* USER CODE BEGIN CAN2_TX_IRQn 0 */ /* USER CODE END CAN2_TX_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800d1d0: 4802 ldr r0, [pc, #8] @ (800d1dc ) 800d1d2: f001 feb3 bl 800ef3c /* USER CODE BEGIN CAN2_TX_IRQn 1 */ /* USER CODE END CAN2_TX_IRQn 1 */ } 800d1d6: bf00 nop 800d1d8: bd80 pop {r7, pc} 800d1da: bf00 nop 800d1dc: 20000310 .word 0x20000310 0800d1e0 : /** * @brief This function handles CAN2 RX1 interrupt. */ void CAN2_RX1_IRQHandler(void) { 800d1e0: b580 push {r7, lr} 800d1e2: af00 add r7, sp, #0 /* USER CODE BEGIN CAN2_RX1_IRQn 0 */ /* USER CODE END CAN2_RX1_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800d1e4: 4802 ldr r0, [pc, #8] @ (800d1f0 ) 800d1e6: f001 fea9 bl 800ef3c /* USER CODE BEGIN CAN2_RX1_IRQn 1 */ /* USER CODE END CAN2_RX1_IRQn 1 */ } 800d1ea: bf00 nop 800d1ec: bd80 pop {r7, pc} 800d1ee: bf00 nop 800d1f0: 20000310 .word 0x20000310 0800d1f4 <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 800d1f4: b480 push {r7} 800d1f6: af00 add r7, sp, #0 return 1; 800d1f8: 2301 movs r3, #1 } 800d1fa: 4618 mov r0, r3 800d1fc: 46bd mov sp, r7 800d1fe: bc80 pop {r7} 800d200: 4770 bx lr 0800d202 <_kill>: int _kill(int pid, int sig) { 800d202: b580 push {r7, lr} 800d204: b082 sub sp, #8 800d206: af00 add r7, sp, #0 800d208: 6078 str r0, [r7, #4] 800d20a: 6039 str r1, [r7, #0] (void)pid; (void)sig; errno = EINVAL; 800d20c: f006 fc40 bl 8013a90 <__errno> 800d210: 4603 mov r3, r0 800d212: 2216 movs r2, #22 800d214: 601a str r2, [r3, #0] return -1; 800d216: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800d21a: 4618 mov r0, r3 800d21c: 3708 adds r7, #8 800d21e: 46bd mov sp, r7 800d220: bd80 pop {r7, pc} 0800d222 <_exit>: void _exit (int status) { 800d222: b580 push {r7, lr} 800d224: b082 sub sp, #8 800d226: af00 add r7, sp, #0 800d228: 6078 str r0, [r7, #4] _kill(status, -1); 800d22a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800d22e: 6878 ldr r0, [r7, #4] 800d230: f7ff ffe7 bl 800d202 <_kill> while (1) {} /* Make sure we hang here */ 800d234: bf00 nop 800d236: e7fd b.n 800d234 <_exit+0x12> 0800d238 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 800d238: b580 push {r7, lr} 800d23a: b086 sub sp, #24 800d23c: af00 add r7, sp, #0 800d23e: 60f8 str r0, [r7, #12] 800d240: 60b9 str r1, [r7, #8] 800d242: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800d244: 2300 movs r3, #0 800d246: 617b str r3, [r7, #20] 800d248: e00a b.n 800d260 <_read+0x28> { *ptr++ = __io_getchar(); 800d24a: f3af 8000 nop.w 800d24e: 4601 mov r1, r0 800d250: 68bb ldr r3, [r7, #8] 800d252: 1c5a adds r2, r3, #1 800d254: 60ba str r2, [r7, #8] 800d256: b2ca uxtb r2, r1 800d258: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 800d25a: 697b ldr r3, [r7, #20] 800d25c: 3301 adds r3, #1 800d25e: 617b str r3, [r7, #20] 800d260: 697a ldr r2, [r7, #20] 800d262: 687b ldr r3, [r7, #4] 800d264: 429a cmp r2, r3 800d266: dbf0 blt.n 800d24a <_read+0x12> } return len; 800d268: 687b ldr r3, [r7, #4] } 800d26a: 4618 mov r0, r3 800d26c: 3718 adds r7, #24 800d26e: 46bd mov sp, r7 800d270: bd80 pop {r7, pc} 0800d272 <_close>: } return len; } int _close(int file) { 800d272: b480 push {r7} 800d274: b083 sub sp, #12 800d276: af00 add r7, sp, #0 800d278: 6078 str r0, [r7, #4] (void)file; return -1; 800d27a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800d27e: 4618 mov r0, r3 800d280: 370c adds r7, #12 800d282: 46bd mov sp, r7 800d284: bc80 pop {r7} 800d286: 4770 bx lr 0800d288 <_fstat>: int _fstat(int file, struct stat *st) { 800d288: b480 push {r7} 800d28a: b083 sub sp, #12 800d28c: af00 add r7, sp, #0 800d28e: 6078 str r0, [r7, #4] 800d290: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 800d292: 683b ldr r3, [r7, #0] 800d294: f44f 5200 mov.w r2, #8192 @ 0x2000 800d298: 605a str r2, [r3, #4] return 0; 800d29a: 2300 movs r3, #0 } 800d29c: 4618 mov r0, r3 800d29e: 370c adds r7, #12 800d2a0: 46bd mov sp, r7 800d2a2: bc80 pop {r7} 800d2a4: 4770 bx lr 0800d2a6 <_isatty>: int _isatty(int file) { 800d2a6: b480 push {r7} 800d2a8: b083 sub sp, #12 800d2aa: af00 add r7, sp, #0 800d2ac: 6078 str r0, [r7, #4] (void)file; return 1; 800d2ae: 2301 movs r3, #1 } 800d2b0: 4618 mov r0, r3 800d2b2: 370c adds r7, #12 800d2b4: 46bd mov sp, r7 800d2b6: bc80 pop {r7} 800d2b8: 4770 bx lr 0800d2ba <_lseek>: int _lseek(int file, int ptr, int dir) { 800d2ba: b480 push {r7} 800d2bc: b085 sub sp, #20 800d2be: af00 add r7, sp, #0 800d2c0: 60f8 str r0, [r7, #12] 800d2c2: 60b9 str r1, [r7, #8] 800d2c4: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 800d2c6: 2300 movs r3, #0 } 800d2c8: 4618 mov r0, r3 800d2ca: 3714 adds r7, #20 800d2cc: 46bd mov sp, r7 800d2ce: bc80 pop {r7} 800d2d0: 4770 bx lr ... 0800d2d4 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 800d2d4: b580 push {r7, lr} 800d2d6: b086 sub sp, #24 800d2d8: af00 add r7, sp, #0 800d2da: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 800d2dc: 4a14 ldr r2, [pc, #80] @ (800d330 <_sbrk+0x5c>) 800d2de: 4b15 ldr r3, [pc, #84] @ (800d334 <_sbrk+0x60>) 800d2e0: 1ad3 subs r3, r2, r3 800d2e2: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 800d2e4: 697b ldr r3, [r7, #20] 800d2e6: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 800d2e8: 4b13 ldr r3, [pc, #76] @ (800d338 <_sbrk+0x64>) 800d2ea: 681b ldr r3, [r3, #0] 800d2ec: 2b00 cmp r3, #0 800d2ee: d102 bne.n 800d2f6 <_sbrk+0x22> { __sbrk_heap_end = &_end; 800d2f0: 4b11 ldr r3, [pc, #68] @ (800d338 <_sbrk+0x64>) 800d2f2: 4a12 ldr r2, [pc, #72] @ (800d33c <_sbrk+0x68>) 800d2f4: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 800d2f6: 4b10 ldr r3, [pc, #64] @ (800d338 <_sbrk+0x64>) 800d2f8: 681a ldr r2, [r3, #0] 800d2fa: 687b ldr r3, [r7, #4] 800d2fc: 4413 add r3, r2 800d2fe: 693a ldr r2, [r7, #16] 800d300: 429a cmp r2, r3 800d302: d207 bcs.n 800d314 <_sbrk+0x40> { errno = ENOMEM; 800d304: f006 fbc4 bl 8013a90 <__errno> 800d308: 4603 mov r3, r0 800d30a: 220c movs r2, #12 800d30c: 601a str r2, [r3, #0] return (void *)-1; 800d30e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800d312: e009 b.n 800d328 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 800d314: 4b08 ldr r3, [pc, #32] @ (800d338 <_sbrk+0x64>) 800d316: 681b ldr r3, [r3, #0] 800d318: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 800d31a: 4b07 ldr r3, [pc, #28] @ (800d338 <_sbrk+0x64>) 800d31c: 681a ldr r2, [r3, #0] 800d31e: 687b ldr r3, [r7, #4] 800d320: 4413 add r3, r2 800d322: 4a05 ldr r2, [pc, #20] @ (800d338 <_sbrk+0x64>) 800d324: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 800d326: 68fb ldr r3, [r7, #12] } 800d328: 4618 mov r0, r3 800d32a: 3718 adds r7, #24 800d32c: 46bd mov sp, r7 800d32e: bd80 pop {r7, pc} 800d330: 20010000 .word 0x20010000 800d334: 00000400 .word 0x00000400 800d338: 20001028 .word 0x20001028 800d33c: 20001330 .word 0x20001330 0800d340 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 800d340: b480 push {r7} 800d342: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 800d344: bf00 nop 800d346: 46bd mov sp, r7 800d348: bc80 pop {r7} 800d34a: 4770 bx lr 0800d34c : TIM_HandleTypeDef htim3; TIM_HandleTypeDef htim4; /* TIM3 init function */ void MX_TIM3_Init(void) { 800d34c: b580 push {r7, lr} 800d34e: b08e sub sp, #56 @ 0x38 800d350: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800d352: f107 0328 add.w r3, r7, #40 @ 0x28 800d356: 2200 movs r2, #0 800d358: 601a str r2, [r3, #0] 800d35a: 605a str r2, [r3, #4] 800d35c: 609a str r2, [r3, #8] 800d35e: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800d360: f107 0320 add.w r3, r7, #32 800d364: 2200 movs r2, #0 800d366: 601a str r2, [r3, #0] 800d368: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800d36a: 1d3b adds r3, r7, #4 800d36c: 2200 movs r2, #0 800d36e: 601a str r2, [r3, #0] 800d370: 605a str r2, [r3, #4] 800d372: 609a str r2, [r3, #8] 800d374: 60da str r2, [r3, #12] 800d376: 611a str r2, [r3, #16] 800d378: 615a str r2, [r3, #20] 800d37a: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 800d37c: 4b2c ldr r3, [pc, #176] @ (800d430 ) 800d37e: 4a2d ldr r2, [pc, #180] @ (800d434 ) 800d380: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 800d382: 4b2b ldr r3, [pc, #172] @ (800d430 ) 800d384: 2200 movs r2, #0 800d386: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 800d388: 4b29 ldr r3, [pc, #164] @ (800d430 ) 800d38a: 2200 movs r2, #0 800d38c: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 800d38e: 4b28 ldr r3, [pc, #160] @ (800d430 ) 800d390: f64f 72ff movw r2, #65535 @ 0xffff 800d394: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800d396: 4b26 ldr r3, [pc, #152] @ (800d430 ) 800d398: 2200 movs r2, #0 800d39a: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800d39c: 4b24 ldr r3, [pc, #144] @ (800d430 ) 800d39e: 2200 movs r2, #0 800d3a0: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 800d3a2: 4823 ldr r0, [pc, #140] @ (800d430 ) 800d3a4: f003 fd83 bl 8010eae 800d3a8: 4603 mov r3, r0 800d3aa: 2b00 cmp r3, #0 800d3ac: d001 beq.n 800d3b2 { Error_Handler(); 800d3ae: f7fd fbf5 bl 800ab9c } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800d3b2: f44f 5380 mov.w r3, #4096 @ 0x1000 800d3b6: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 800d3b8: f107 0328 add.w r3, r7, #40 @ 0x28 800d3bc: 4619 mov r1, r3 800d3be: 481c ldr r0, [pc, #112] @ (800d430 ) 800d3c0: f004 f96e bl 80116a0 800d3c4: 4603 mov r3, r0 800d3c6: 2b00 cmp r3, #0 800d3c8: d001 beq.n 800d3ce { Error_Handler(); 800d3ca: f7fd fbe7 bl 800ab9c } if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 800d3ce: 4818 ldr r0, [pc, #96] @ (800d430 ) 800d3d0: f003 feb2 bl 8011138 800d3d4: 4603 mov r3, r0 800d3d6: 2b00 cmp r3, #0 800d3d8: d001 beq.n 800d3de { Error_Handler(); 800d3da: f7fd fbdf bl 800ab9c } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800d3de: 2300 movs r3, #0 800d3e0: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800d3e2: 2300 movs r3, #0 800d3e4: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800d3e6: f107 0320 add.w r3, r7, #32 800d3ea: 4619 mov r1, r3 800d3ec: 4810 ldr r0, [pc, #64] @ (800d430 ) 800d3ee: f004 fcfd bl 8011dec 800d3f2: 4603 mov r3, r0 800d3f4: 2b00 cmp r3, #0 800d3f6: d001 beq.n 800d3fc { Error_Handler(); 800d3f8: f7fd fbd0 bl 800ab9c } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800d3fc: 2360 movs r3, #96 @ 0x60 800d3fe: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800d400: 2300 movs r3, #0 800d402: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800d404: 2300 movs r3, #0 800d406: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800d408: 2300 movs r3, #0 800d40a: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800d40c: 1d3b adds r3, r7, #4 800d40e: 2204 movs r2, #4 800d410: 4619 mov r1, r3 800d412: 4807 ldr r0, [pc, #28] @ (800d430 ) 800d414: f004 f882 bl 801151c 800d418: 4603 mov r3, r0 800d41a: 2b00 cmp r3, #0 800d41c: d001 beq.n 800d422 { Error_Handler(); 800d41e: f7fd fbbd bl 800ab9c } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 800d422: 4803 ldr r0, [pc, #12] @ (800d430 ) 800d424: f000 f8ce bl 800d5c4 } 800d428: bf00 nop 800d42a: 3738 adds r7, #56 @ 0x38 800d42c: 46bd mov sp, r7 800d42e: bd80 pop {r7, pc} 800d430: 2000102c .word 0x2000102c 800d434: 40000400 .word 0x40000400 0800d438 : /* TIM4 init function */ void MX_TIM4_Init(void) { 800d438: b580 push {r7, lr} 800d43a: b08e sub sp, #56 @ 0x38 800d43c: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800d43e: f107 0328 add.w r3, r7, #40 @ 0x28 800d442: 2200 movs r2, #0 800d444: 601a str r2, [r3, #0] 800d446: 605a str r2, [r3, #4] 800d448: 609a str r2, [r3, #8] 800d44a: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800d44c: f107 0320 add.w r3, r7, #32 800d450: 2200 movs r2, #0 800d452: 601a str r2, [r3, #0] 800d454: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800d456: 1d3b adds r3, r7, #4 800d458: 2200 movs r2, #0 800d45a: 601a str r2, [r3, #0] 800d45c: 605a str r2, [r3, #4] 800d45e: 609a str r2, [r3, #8] 800d460: 60da str r2, [r3, #12] 800d462: 611a str r2, [r3, #16] 800d464: 615a str r2, [r3, #20] 800d466: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM4_Init 1 */ /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; 800d468: 4b37 ldr r3, [pc, #220] @ (800d548 ) 800d46a: 4a38 ldr r2, [pc, #224] @ (800d54c ) 800d46c: 601a str r2, [r3, #0] htim4.Init.Prescaler = 720; 800d46e: 4b36 ldr r3, [pc, #216] @ (800d548 ) 800d470: f44f 7234 mov.w r2, #720 @ 0x2d0 800d474: 605a str r2, [r3, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 800d476: 4b34 ldr r3, [pc, #208] @ (800d548 ) 800d478: 2200 movs r2, #0 800d47a: 609a str r2, [r3, #8] htim4.Init.Period = 100; 800d47c: 4b32 ldr r3, [pc, #200] @ (800d548 ) 800d47e: 2264 movs r2, #100 @ 0x64 800d480: 60da str r2, [r3, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800d482: 4b31 ldr r3, [pc, #196] @ (800d548 ) 800d484: 2200 movs r2, #0 800d486: 611a str r2, [r3, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800d488: 4b2f ldr r3, [pc, #188] @ (800d548 ) 800d48a: 2200 movs r2, #0 800d48c: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 800d48e: 482e ldr r0, [pc, #184] @ (800d548 ) 800d490: f003 fd0d bl 8010eae 800d494: 4603 mov r3, r0 800d496: 2b00 cmp r3, #0 800d498: d001 beq.n 800d49e { Error_Handler(); 800d49a: f7fd fb7f bl 800ab9c } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800d49e: f44f 5380 mov.w r3, #4096 @ 0x1000 800d4a2: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 800d4a4: f107 0328 add.w r3, r7, #40 @ 0x28 800d4a8: 4619 mov r1, r3 800d4aa: 4827 ldr r0, [pc, #156] @ (800d548 ) 800d4ac: f004 f8f8 bl 80116a0 800d4b0: 4603 mov r3, r0 800d4b2: 2b00 cmp r3, #0 800d4b4: d001 beq.n 800d4ba { Error_Handler(); 800d4b6: f7fd fb71 bl 800ab9c } if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) 800d4ba: 4823 ldr r0, [pc, #140] @ (800d548 ) 800d4bc: f003 fe3c bl 8011138 800d4c0: 4603 mov r3, r0 800d4c2: 2b00 cmp r3, #0 800d4c4: d001 beq.n 800d4ca { Error_Handler(); 800d4c6: f7fd fb69 bl 800ab9c } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800d4ca: 2300 movs r3, #0 800d4cc: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800d4ce: 2300 movs r3, #0 800d4d0: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 800d4d2: f107 0320 add.w r3, r7, #32 800d4d6: 4619 mov r1, r3 800d4d8: 481b ldr r0, [pc, #108] @ (800d548 ) 800d4da: f004 fc87 bl 8011dec 800d4de: 4603 mov r3, r0 800d4e0: 2b00 cmp r3, #0 800d4e2: d001 beq.n 800d4e8 { Error_Handler(); 800d4e4: f7fd fb5a bl 800ab9c } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800d4e8: 2360 movs r3, #96 @ 0x60 800d4ea: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800d4ec: 2300 movs r3, #0 800d4ee: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800d4f0: 2300 movs r3, #0 800d4f2: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800d4f4: 2300 movs r3, #0 800d4f6: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800d4f8: 1d3b adds r3, r7, #4 800d4fa: 2204 movs r2, #4 800d4fc: 4619 mov r1, r3 800d4fe: 4812 ldr r0, [pc, #72] @ (800d548 ) 800d500: f004 f80c bl 801151c 800d504: 4603 mov r3, r0 800d506: 2b00 cmp r3, #0 800d508: d001 beq.n 800d50e { Error_Handler(); 800d50a: f7fd fb47 bl 800ab9c } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 800d50e: 1d3b adds r3, r7, #4 800d510: 2208 movs r2, #8 800d512: 4619 mov r1, r3 800d514: 480c ldr r0, [pc, #48] @ (800d548 ) 800d516: f004 f801 bl 801151c 800d51a: 4603 mov r3, r0 800d51c: 2b00 cmp r3, #0 800d51e: d001 beq.n 800d524 { Error_Handler(); 800d520: f7fd fb3c bl 800ab9c } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 800d524: 1d3b adds r3, r7, #4 800d526: 220c movs r2, #12 800d528: 4619 mov r1, r3 800d52a: 4807 ldr r0, [pc, #28] @ (800d548 ) 800d52c: f003 fff6 bl 801151c 800d530: 4603 mov r3, r0 800d532: 2b00 cmp r3, #0 800d534: d001 beq.n 800d53a { Error_Handler(); 800d536: f7fd fb31 bl 800ab9c } /* USER CODE BEGIN TIM4_Init 2 */ /* USER CODE END TIM4_Init 2 */ HAL_TIM_MspPostInit(&htim4); 800d53a: 4803 ldr r0, [pc, #12] @ (800d548 ) 800d53c: f000 f842 bl 800d5c4 } 800d540: bf00 nop 800d542: 3738 adds r7, #56 @ 0x38 800d544: 46bd mov sp, r7 800d546: bd80 pop {r7, pc} 800d548: 20001074 .word 0x20001074 800d54c: 40000800 .word 0x40000800 0800d550 : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 800d550: b580 push {r7, lr} 800d552: b084 sub sp, #16 800d554: af00 add r7, sp, #0 800d556: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM3) 800d558: 687b ldr r3, [r7, #4] 800d55a: 681b ldr r3, [r3, #0] 800d55c: 4a16 ldr r2, [pc, #88] @ (800d5b8 ) 800d55e: 4293 cmp r3, r2 800d560: d114 bne.n 800d58c { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 800d562: 4b16 ldr r3, [pc, #88] @ (800d5bc ) 800d564: 69db ldr r3, [r3, #28] 800d566: 4a15 ldr r2, [pc, #84] @ (800d5bc ) 800d568: f043 0302 orr.w r3, r3, #2 800d56c: 61d3 str r3, [r2, #28] 800d56e: 4b13 ldr r3, [pc, #76] @ (800d5bc ) 800d570: 69db ldr r3, [r3, #28] 800d572: f003 0302 and.w r3, r3, #2 800d576: 60fb str r3, [r7, #12] 800d578: 68fb ldr r3, [r7, #12] /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); 800d57a: 2200 movs r2, #0 800d57c: 2100 movs r1, #0 800d57e: 201d movs r0, #29 800d580: f001 ffd7 bl 800f532 HAL_NVIC_EnableIRQ(TIM3_IRQn); 800d584: 201d movs r0, #29 800d586: f001 fff0 bl 800f56a __HAL_RCC_TIM4_CLK_ENABLE(); /* USER CODE BEGIN TIM4_MspInit 1 */ /* USER CODE END TIM4_MspInit 1 */ } } 800d58a: e010 b.n 800d5ae else if(tim_baseHandle->Instance==TIM4) 800d58c: 687b ldr r3, [r7, #4] 800d58e: 681b ldr r3, [r3, #0] 800d590: 4a0b ldr r2, [pc, #44] @ (800d5c0 ) 800d592: 4293 cmp r3, r2 800d594: d10b bne.n 800d5ae __HAL_RCC_TIM4_CLK_ENABLE(); 800d596: 4b09 ldr r3, [pc, #36] @ (800d5bc ) 800d598: 69db ldr r3, [r3, #28] 800d59a: 4a08 ldr r2, [pc, #32] @ (800d5bc ) 800d59c: f043 0304 orr.w r3, r3, #4 800d5a0: 61d3 str r3, [r2, #28] 800d5a2: 4b06 ldr r3, [pc, #24] @ (800d5bc ) 800d5a4: 69db ldr r3, [r3, #28] 800d5a6: f003 0304 and.w r3, r3, #4 800d5aa: 60bb str r3, [r7, #8] 800d5ac: 68bb ldr r3, [r7, #8] } 800d5ae: bf00 nop 800d5b0: 3710 adds r7, #16 800d5b2: 46bd mov sp, r7 800d5b4: bd80 pop {r7, pc} 800d5b6: bf00 nop 800d5b8: 40000400 .word 0x40000400 800d5bc: 40021000 .word 0x40021000 800d5c0: 40000800 .word 0x40000800 0800d5c4 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 800d5c4: b580 push {r7, lr} 800d5c6: b08a sub sp, #40 @ 0x28 800d5c8: af00 add r7, sp, #0 800d5ca: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800d5cc: f107 0314 add.w r3, r7, #20 800d5d0: 2200 movs r2, #0 800d5d2: 601a str r2, [r3, #0] 800d5d4: 605a str r2, [r3, #4] 800d5d6: 609a str r2, [r3, #8] 800d5d8: 60da str r2, [r3, #12] if(timHandle->Instance==TIM3) 800d5da: 687b ldr r3, [r7, #4] 800d5dc: 681b ldr r3, [r3, #0] 800d5de: 4a26 ldr r2, [pc, #152] @ (800d678 ) 800d5e0: 4293 cmp r3, r2 800d5e2: d118 bne.n 800d616 { /* USER CODE BEGIN TIM3_MspPostInit 0 */ /* USER CODE END TIM3_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800d5e4: 4b25 ldr r3, [pc, #148] @ (800d67c ) 800d5e6: 699b ldr r3, [r3, #24] 800d5e8: 4a24 ldr r2, [pc, #144] @ (800d67c ) 800d5ea: f043 0304 orr.w r3, r3, #4 800d5ee: 6193 str r3, [r2, #24] 800d5f0: 4b22 ldr r3, [pc, #136] @ (800d67c ) 800d5f2: 699b ldr r3, [r3, #24] 800d5f4: f003 0304 and.w r3, r3, #4 800d5f8: 613b str r3, [r7, #16] 800d5fa: 693b ldr r3, [r7, #16] /**TIM3 GPIO Configuration PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = CP_PWM_Pin; 800d5fc: 2380 movs r3, #128 @ 0x80 800d5fe: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d600: 2302 movs r3, #2 800d602: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800d604: 2302 movs r3, #2 800d606: 623b str r3, [r7, #32] HAL_GPIO_Init(CP_PWM_GPIO_Port, &GPIO_InitStruct); 800d608: f107 0314 add.w r3, r7, #20 800d60c: 4619 mov r1, r3 800d60e: 481c ldr r0, [pc, #112] @ (800d680 ) 800d610: f002 f924 bl 800f85c /* USER CODE BEGIN TIM4_MspPostInit 1 */ /* USER CODE END TIM4_MspPostInit 1 */ } } 800d614: e02b b.n 800d66e else if(timHandle->Instance==TIM4) 800d616: 687b ldr r3, [r7, #4] 800d618: 681b ldr r3, [r3, #0] 800d61a: 4a1a ldr r2, [pc, #104] @ (800d684 ) 800d61c: 4293 cmp r3, r2 800d61e: d126 bne.n 800d66e __HAL_RCC_GPIOD_CLK_ENABLE(); 800d620: 4b16 ldr r3, [pc, #88] @ (800d67c ) 800d622: 699b ldr r3, [r3, #24] 800d624: 4a15 ldr r2, [pc, #84] @ (800d67c ) 800d626: f043 0320 orr.w r3, r3, #32 800d62a: 6193 str r3, [r2, #24] 800d62c: 4b13 ldr r3, [pc, #76] @ (800d67c ) 800d62e: 699b ldr r3, [r3, #24] 800d630: f003 0320 and.w r3, r3, #32 800d634: 60fb str r3, [r7, #12] 800d636: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; 800d638: f44f 4360 mov.w r3, #57344 @ 0xe000 800d63c: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d63e: 2302 movs r3, #2 800d640: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800d642: 2302 movs r3, #2 800d644: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d646: f107 0314 add.w r3, r7, #20 800d64a: 4619 mov r1, r3 800d64c: 480e ldr r0, [pc, #56] @ (800d688 ) 800d64e: f002 f905 bl 800f85c __HAL_AFIO_REMAP_TIM4_ENABLE(); 800d652: 4b0e ldr r3, [pc, #56] @ (800d68c ) 800d654: 685b ldr r3, [r3, #4] 800d656: 627b str r3, [r7, #36] @ 0x24 800d658: 6a7b ldr r3, [r7, #36] @ 0x24 800d65a: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800d65e: 627b str r3, [r7, #36] @ 0x24 800d660: 6a7b ldr r3, [r7, #36] @ 0x24 800d662: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800d666: 627b str r3, [r7, #36] @ 0x24 800d668: 4a08 ldr r2, [pc, #32] @ (800d68c ) 800d66a: 6a7b ldr r3, [r7, #36] @ 0x24 800d66c: 6053 str r3, [r2, #4] } 800d66e: bf00 nop 800d670: 3728 adds r7, #40 @ 0x28 800d672: 46bd mov sp, r7 800d674: bd80 pop {r7, pc} 800d676: bf00 nop 800d678: 40000400 .word 0x40000400 800d67c: 40021000 .word 0x40021000 800d680: 40010800 .word 0x40010800 800d684: 40000800 .word 0x40000800 800d688: 40011400 .word 0x40011400 800d68c: 40010000 .word 0x40010000 0800d690 : UART_HandleTypeDef huart2; UART_HandleTypeDef huart3; /* UART5 init function */ void MX_UART5_Init(void) { 800d690: b580 push {r7, lr} 800d692: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 800d694: 4b11 ldr r3, [pc, #68] @ (800d6dc ) 800d696: 4a12 ldr r2, [pc, #72] @ (800d6e0 ) 800d698: 601a str r2, [r3, #0] huart5.Init.BaudRate = 9600; 800d69a: 4b10 ldr r3, [pc, #64] @ (800d6dc ) 800d69c: f44f 5216 mov.w r2, #9600 @ 0x2580 800d6a0: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 800d6a2: 4b0e ldr r3, [pc, #56] @ (800d6dc ) 800d6a4: 2200 movs r2, #0 800d6a6: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 800d6a8: 4b0c ldr r3, [pc, #48] @ (800d6dc ) 800d6aa: 2200 movs r2, #0 800d6ac: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 800d6ae: 4b0b ldr r3, [pc, #44] @ (800d6dc ) 800d6b0: 2200 movs r2, #0 800d6b2: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 800d6b4: 4b09 ldr r3, [pc, #36] @ (800d6dc ) 800d6b6: 220c movs r2, #12 800d6b8: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d6ba: 4b08 ldr r3, [pc, #32] @ (800d6dc ) 800d6bc: 2200 movs r2, #0 800d6be: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 800d6c0: 4b06 ldr r3, [pc, #24] @ (800d6dc ) 800d6c2: 2200 movs r2, #0 800d6c4: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 800d6c6: 4805 ldr r0, [pc, #20] @ (800d6dc ) 800d6c8: f004 fc08 bl 8011edc 800d6cc: 4603 mov r3, r0 800d6ce: 2b00 cmp r3, #0 800d6d0: d001 beq.n 800d6d6 { Error_Handler(); 800d6d2: f7fd fa63 bl 800ab9c } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 800d6d6: bf00 nop 800d6d8: bd80 pop {r7, pc} 800d6da: bf00 nop 800d6dc: 200010bc .word 0x200010bc 800d6e0: 40005000 .word 0x40005000 0800d6e4 : /* USART1 init function */ void MX_USART1_UART_Init(void) { 800d6e4: b580 push {r7, lr} 800d6e6: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 800d6e8: 4b11 ldr r3, [pc, #68] @ (800d730 ) 800d6ea: 4a12 ldr r2, [pc, #72] @ (800d734 ) 800d6ec: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800d6ee: 4b10 ldr r3, [pc, #64] @ (800d730 ) 800d6f0: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800d6f4: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800d6f6: 4b0e ldr r3, [pc, #56] @ (800d730 ) 800d6f8: 2200 movs r2, #0 800d6fa: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 800d6fc: 4b0c ldr r3, [pc, #48] @ (800d730 ) 800d6fe: 2200 movs r2, #0 800d700: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800d702: 4b0b ldr r3, [pc, #44] @ (800d730 ) 800d704: 2200 movs r2, #0 800d706: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 800d708: 4b09 ldr r3, [pc, #36] @ (800d730 ) 800d70a: 220c movs r2, #12 800d70c: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d70e: 4b08 ldr r3, [pc, #32] @ (800d730 ) 800d710: 2200 movs r2, #0 800d712: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800d714: 4b06 ldr r3, [pc, #24] @ (800d730 ) 800d716: 2200 movs r2, #0 800d718: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 800d71a: 4805 ldr r0, [pc, #20] @ (800d730 ) 800d71c: f004 fbde bl 8011edc 800d720: 4603 mov r3, r0 800d722: 2b00 cmp r3, #0 800d724: d001 beq.n 800d72a { Error_Handler(); 800d726: f7fd fa39 bl 800ab9c } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 800d72a: bf00 nop 800d72c: bd80 pop {r7, pc} 800d72e: bf00 nop 800d730: 20001104 .word 0x20001104 800d734: 40013800 .word 0x40013800 0800d738 : /* USART2 init function */ void MX_USART2_UART_Init(void) { 800d738: b580 push {r7, lr} 800d73a: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 800d73c: 4b11 ldr r3, [pc, #68] @ (800d784 ) 800d73e: 4a12 ldr r2, [pc, #72] @ (800d788 ) 800d740: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 800d742: 4b10 ldr r3, [pc, #64] @ (800d784 ) 800d744: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800d748: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 800d74a: 4b0e ldr r3, [pc, #56] @ (800d784 ) 800d74c: 2200 movs r2, #0 800d74e: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 800d750: 4b0c ldr r3, [pc, #48] @ (800d784 ) 800d752: 2200 movs r2, #0 800d754: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800d756: 4b0b ldr r3, [pc, #44] @ (800d784 ) 800d758: 2200 movs r2, #0 800d75a: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 800d75c: 4b09 ldr r3, [pc, #36] @ (800d784 ) 800d75e: 220c movs r2, #12 800d760: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d762: 4b08 ldr r3, [pc, #32] @ (800d784 ) 800d764: 2200 movs r2, #0 800d766: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 800d768: 4b06 ldr r3, [pc, #24] @ (800d784 ) 800d76a: 2200 movs r2, #0 800d76c: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 800d76e: 4805 ldr r0, [pc, #20] @ (800d784 ) 800d770: f004 fbb4 bl 8011edc 800d774: 4603 mov r3, r0 800d776: 2b00 cmp r3, #0 800d778: d001 beq.n 800d77e { Error_Handler(); 800d77a: f7fd fa0f bl 800ab9c } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 800d77e: bf00 nop 800d780: bd80 pop {r7, pc} 800d782: bf00 nop 800d784: 2000114c .word 0x2000114c 800d788: 40004400 .word 0x40004400 0800d78c : /* USART3 init function */ void MX_USART3_UART_Init(void) { 800d78c: b580 push {r7, lr} 800d78e: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 800d790: 4b11 ldr r3, [pc, #68] @ (800d7d8 ) 800d792: 4a12 ldr r2, [pc, #72] @ (800d7dc ) 800d794: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 800d796: 4b10 ldr r3, [pc, #64] @ (800d7d8 ) 800d798: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800d79c: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 800d79e: 4b0e ldr r3, [pc, #56] @ (800d7d8 ) 800d7a0: 2200 movs r2, #0 800d7a2: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 800d7a4: 4b0c ldr r3, [pc, #48] @ (800d7d8 ) 800d7a6: 2200 movs r2, #0 800d7a8: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 800d7aa: 4b0b ldr r3, [pc, #44] @ (800d7d8 ) 800d7ac: 2200 movs r2, #0 800d7ae: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 800d7b0: 4b09 ldr r3, [pc, #36] @ (800d7d8 ) 800d7b2: 220c movs r2, #12 800d7b4: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d7b6: 4b08 ldr r3, [pc, #32] @ (800d7d8 ) 800d7b8: 2200 movs r2, #0 800d7ba: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 800d7bc: 4b06 ldr r3, [pc, #24] @ (800d7d8 ) 800d7be: 2200 movs r2, #0 800d7c0: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart3) != HAL_OK) 800d7c2: 4805 ldr r0, [pc, #20] @ (800d7d8 ) 800d7c4: f004 fb8a bl 8011edc 800d7c8: 4603 mov r3, r0 800d7ca: 2b00 cmp r3, #0 800d7cc: d001 beq.n 800d7d2 { Error_Handler(); 800d7ce: f7fd f9e5 bl 800ab9c } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 800d7d2: bf00 nop 800d7d4: bd80 pop {r7, pc} 800d7d6: bf00 nop 800d7d8: 20001194 .word 0x20001194 800d7dc: 40004800 .word 0x40004800 0800d7e0 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 800d7e0: b580 push {r7, lr} 800d7e2: b092 sub sp, #72 @ 0x48 800d7e4: af00 add r7, sp, #0 800d7e6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800d7e8: f107 0330 add.w r3, r7, #48 @ 0x30 800d7ec: 2200 movs r2, #0 800d7ee: 601a str r2, [r3, #0] 800d7f0: 605a str r2, [r3, #4] 800d7f2: 609a str r2, [r3, #8] 800d7f4: 60da str r2, [r3, #12] if(uartHandle->Instance==UART5) 800d7f6: 687b ldr r3, [r7, #4] 800d7f8: 681b ldr r3, [r3, #0] 800d7fa: 4a95 ldr r2, [pc, #596] @ (800da50 ) 800d7fc: 4293 cmp r3, r2 800d7fe: d145 bne.n 800d88c { /* USER CODE BEGIN UART5_MspInit 0 */ /* USER CODE END UART5_MspInit 0 */ /* UART5 clock enable */ __HAL_RCC_UART5_CLK_ENABLE(); 800d800: 4b94 ldr r3, [pc, #592] @ (800da54 ) 800d802: 69db ldr r3, [r3, #28] 800d804: 4a93 ldr r2, [pc, #588] @ (800da54 ) 800d806: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800d80a: 61d3 str r3, [r2, #28] 800d80c: 4b91 ldr r3, [pc, #580] @ (800da54 ) 800d80e: 69db ldr r3, [r3, #28] 800d810: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800d814: 62fb str r3, [r7, #44] @ 0x2c 800d816: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 800d818: 4b8e ldr r3, [pc, #568] @ (800da54 ) 800d81a: 699b ldr r3, [r3, #24] 800d81c: 4a8d ldr r2, [pc, #564] @ (800da54 ) 800d81e: f043 0310 orr.w r3, r3, #16 800d822: 6193 str r3, [r2, #24] 800d824: 4b8b ldr r3, [pc, #556] @ (800da54 ) 800d826: 699b ldr r3, [r3, #24] 800d828: f003 0310 and.w r3, r3, #16 800d82c: 62bb str r3, [r7, #40] @ 0x28 800d82e: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOD_CLK_ENABLE(); 800d830: 4b88 ldr r3, [pc, #544] @ (800da54 ) 800d832: 699b ldr r3, [r3, #24] 800d834: 4a87 ldr r2, [pc, #540] @ (800da54 ) 800d836: f043 0320 orr.w r3, r3, #32 800d83a: 6193 str r3, [r2, #24] 800d83c: 4b85 ldr r3, [pc, #532] @ (800da54 ) 800d83e: 699b ldr r3, [r3, #24] 800d840: f003 0320 and.w r3, r3, #32 800d844: 627b str r3, [r7, #36] @ 0x24 800d846: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART5 GPIO Configuration PC12 ------> UART5_TX PD2 ------> UART5_RX */ GPIO_InitStruct.Pin = GPIO_PIN_12; 800d848: f44f 5380 mov.w r3, #4096 @ 0x1000 800d84c: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d84e: 2302 movs r3, #2 800d850: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800d852: 2303 movs r3, #3 800d854: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800d856: f107 0330 add.w r3, r7, #48 @ 0x30 800d85a: 4619 mov r1, r3 800d85c: 487e ldr r0, [pc, #504] @ (800da58 ) 800d85e: f001 fffd bl 800f85c GPIO_InitStruct.Pin = GPIO_PIN_2; 800d862: 2304 movs r3, #4 800d864: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800d866: 2300 movs r3, #0 800d868: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800d86a: 2300 movs r3, #0 800d86c: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d86e: f107 0330 add.w r3, r7, #48 @ 0x30 800d872: 4619 mov r1, r3 800d874: 4879 ldr r0, [pc, #484] @ (800da5c ) 800d876: f001 fff1 bl 800f85c /* UART5 interrupt Init */ HAL_NVIC_SetPriority(UART5_IRQn, 0, 0); 800d87a: 2200 movs r2, #0 800d87c: 2100 movs r1, #0 800d87e: 2035 movs r0, #53 @ 0x35 800d880: f001 fe57 bl 800f532 HAL_NVIC_EnableIRQ(UART5_IRQn); 800d884: 2035 movs r0, #53 @ 0x35 800d886: f001 fe70 bl 800f56a HAL_NVIC_EnableIRQ(USART3_IRQn); /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 800d88a: e0dc b.n 800da46 else if(uartHandle->Instance==USART1) 800d88c: 687b ldr r3, [r7, #4] 800d88e: 681b ldr r3, [r3, #0] 800d890: 4a73 ldr r2, [pc, #460] @ (800da60 ) 800d892: 4293 cmp r3, r2 800d894: d13a bne.n 800d90c __HAL_RCC_USART1_CLK_ENABLE(); 800d896: 4b6f ldr r3, [pc, #444] @ (800da54 ) 800d898: 699b ldr r3, [r3, #24] 800d89a: 4a6e ldr r2, [pc, #440] @ (800da54 ) 800d89c: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800d8a0: 6193 str r3, [r2, #24] 800d8a2: 4b6c ldr r3, [pc, #432] @ (800da54 ) 800d8a4: 699b ldr r3, [r3, #24] 800d8a6: f403 4380 and.w r3, r3, #16384 @ 0x4000 800d8aa: 623b str r3, [r7, #32] 800d8ac: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 800d8ae: 4b69 ldr r3, [pc, #420] @ (800da54 ) 800d8b0: 699b ldr r3, [r3, #24] 800d8b2: 4a68 ldr r2, [pc, #416] @ (800da54 ) 800d8b4: f043 0304 orr.w r3, r3, #4 800d8b8: 6193 str r3, [r2, #24] 800d8ba: 4b66 ldr r3, [pc, #408] @ (800da54 ) 800d8bc: 699b ldr r3, [r3, #24] 800d8be: f003 0304 and.w r3, r3, #4 800d8c2: 61fb str r3, [r7, #28] 800d8c4: 69fb ldr r3, [r7, #28] GPIO_InitStruct.Pin = GPIO_PIN_9; 800d8c6: f44f 7300 mov.w r3, #512 @ 0x200 800d8ca: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d8cc: 2302 movs r3, #2 800d8ce: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800d8d0: 2303 movs r3, #3 800d8d2: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800d8d4: f107 0330 add.w r3, r7, #48 @ 0x30 800d8d8: 4619 mov r1, r3 800d8da: 4862 ldr r0, [pc, #392] @ (800da64 ) 800d8dc: f001 ffbe bl 800f85c GPIO_InitStruct.Pin = GPIO_PIN_10; 800d8e0: f44f 6380 mov.w r3, #1024 @ 0x400 800d8e4: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800d8e6: 2300 movs r3, #0 800d8e8: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800d8ea: 2300 movs r3, #0 800d8ec: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800d8ee: f107 0330 add.w r3, r7, #48 @ 0x30 800d8f2: 4619 mov r1, r3 800d8f4: 485b ldr r0, [pc, #364] @ (800da64 ) 800d8f6: f001 ffb1 bl 800f85c HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 800d8fa: 2200 movs r2, #0 800d8fc: 2100 movs r1, #0 800d8fe: 2025 movs r0, #37 @ 0x25 800d900: f001 fe17 bl 800f532 HAL_NVIC_EnableIRQ(USART1_IRQn); 800d904: 2025 movs r0, #37 @ 0x25 800d906: f001 fe30 bl 800f56a } 800d90a: e09c b.n 800da46 else if(uartHandle->Instance==USART2) 800d90c: 687b ldr r3, [r7, #4] 800d90e: 681b ldr r3, [r3, #0] 800d910: 4a55 ldr r2, [pc, #340] @ (800da68 ) 800d912: 4293 cmp r3, r2 800d914: d146 bne.n 800d9a4 __HAL_RCC_USART2_CLK_ENABLE(); 800d916: 4b4f ldr r3, [pc, #316] @ (800da54 ) 800d918: 69db ldr r3, [r3, #28] 800d91a: 4a4e ldr r2, [pc, #312] @ (800da54 ) 800d91c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d920: 61d3 str r3, [r2, #28] 800d922: 4b4c ldr r3, [pc, #304] @ (800da54 ) 800d924: 69db ldr r3, [r3, #28] 800d926: f403 3300 and.w r3, r3, #131072 @ 0x20000 800d92a: 61bb str r3, [r7, #24] 800d92c: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOD_CLK_ENABLE(); 800d92e: 4b49 ldr r3, [pc, #292] @ (800da54 ) 800d930: 699b ldr r3, [r3, #24] 800d932: 4a48 ldr r2, [pc, #288] @ (800da54 ) 800d934: f043 0320 orr.w r3, r3, #32 800d938: 6193 str r3, [r2, #24] 800d93a: 4b46 ldr r3, [pc, #280] @ (800da54 ) 800d93c: 699b ldr r3, [r3, #24] 800d93e: f003 0320 and.w r3, r3, #32 800d942: 617b str r3, [r7, #20] 800d944: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_5; 800d946: 2320 movs r3, #32 800d948: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d94a: 2302 movs r3, #2 800d94c: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800d94e: 2303 movs r3, #3 800d950: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d952: f107 0330 add.w r3, r7, #48 @ 0x30 800d956: 4619 mov r1, r3 800d958: 4840 ldr r0, [pc, #256] @ (800da5c ) 800d95a: f001 ff7f bl 800f85c GPIO_InitStruct.Pin = GPIO_PIN_6; 800d95e: 2340 movs r3, #64 @ 0x40 800d960: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800d962: 2300 movs r3, #0 800d964: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800d966: 2300 movs r3, #0 800d968: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d96a: f107 0330 add.w r3, r7, #48 @ 0x30 800d96e: 4619 mov r1, r3 800d970: 483a ldr r0, [pc, #232] @ (800da5c ) 800d972: f001 ff73 bl 800f85c __HAL_AFIO_REMAP_USART2_ENABLE(); 800d976: 4b3d ldr r3, [pc, #244] @ (800da6c ) 800d978: 685b ldr r3, [r3, #4] 800d97a: 643b str r3, [r7, #64] @ 0x40 800d97c: 6c3b ldr r3, [r7, #64] @ 0x40 800d97e: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800d982: 643b str r3, [r7, #64] @ 0x40 800d984: 6c3b ldr r3, [r7, #64] @ 0x40 800d986: f043 0308 orr.w r3, r3, #8 800d98a: 643b str r3, [r7, #64] @ 0x40 800d98c: 4a37 ldr r2, [pc, #220] @ (800da6c ) 800d98e: 6c3b ldr r3, [r7, #64] @ 0x40 800d990: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); 800d992: 2200 movs r2, #0 800d994: 2100 movs r1, #0 800d996: 2026 movs r0, #38 @ 0x26 800d998: f001 fdcb bl 800f532 HAL_NVIC_EnableIRQ(USART2_IRQn); 800d99c: 2026 movs r0, #38 @ 0x26 800d99e: f001 fde4 bl 800f56a } 800d9a2: e050 b.n 800da46 else if(uartHandle->Instance==USART3) 800d9a4: 687b ldr r3, [r7, #4] 800d9a6: 681b ldr r3, [r3, #0] 800d9a8: 4a31 ldr r2, [pc, #196] @ (800da70 ) 800d9aa: 4293 cmp r3, r2 800d9ac: d14b bne.n 800da46 __HAL_RCC_USART3_CLK_ENABLE(); 800d9ae: 4b29 ldr r3, [pc, #164] @ (800da54 ) 800d9b0: 69db ldr r3, [r3, #28] 800d9b2: 4a28 ldr r2, [pc, #160] @ (800da54 ) 800d9b4: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800d9b8: 61d3 str r3, [r2, #28] 800d9ba: 4b26 ldr r3, [pc, #152] @ (800da54 ) 800d9bc: 69db ldr r3, [r3, #28] 800d9be: f403 2380 and.w r3, r3, #262144 @ 0x40000 800d9c2: 613b str r3, [r7, #16] 800d9c4: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 800d9c6: 4b23 ldr r3, [pc, #140] @ (800da54 ) 800d9c8: 699b ldr r3, [r3, #24] 800d9ca: 4a22 ldr r2, [pc, #136] @ (800da54 ) 800d9cc: f043 0310 orr.w r3, r3, #16 800d9d0: 6193 str r3, [r2, #24] 800d9d2: 4b20 ldr r3, [pc, #128] @ (800da54 ) 800d9d4: 699b ldr r3, [r3, #24] 800d9d6: f003 0310 and.w r3, r3, #16 800d9da: 60fb str r3, [r7, #12] 800d9dc: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_10; 800d9de: f44f 6380 mov.w r3, #1024 @ 0x400 800d9e2: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d9e4: 2302 movs r3, #2 800d9e6: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800d9e8: 2303 movs r3, #3 800d9ea: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800d9ec: f107 0330 add.w r3, r7, #48 @ 0x30 800d9f0: 4619 mov r1, r3 800d9f2: 4819 ldr r0, [pc, #100] @ (800da58 ) 800d9f4: f001 ff32 bl 800f85c GPIO_InitStruct.Pin = GPIO_PIN_11; 800d9f8: f44f 6300 mov.w r3, #2048 @ 0x800 800d9fc: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800d9fe: 2300 movs r3, #0 800da00: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800da02: 2300 movs r3, #0 800da04: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800da06: f107 0330 add.w r3, r7, #48 @ 0x30 800da0a: 4619 mov r1, r3 800da0c: 4812 ldr r0, [pc, #72] @ (800da58 ) 800da0e: f001 ff25 bl 800f85c __HAL_AFIO_REMAP_USART3_PARTIAL(); 800da12: 4b16 ldr r3, [pc, #88] @ (800da6c ) 800da14: 685b ldr r3, [r3, #4] 800da16: 647b str r3, [r7, #68] @ 0x44 800da18: 6c7b ldr r3, [r7, #68] @ 0x44 800da1a: f023 0330 bic.w r3, r3, #48 @ 0x30 800da1e: 647b str r3, [r7, #68] @ 0x44 800da20: 6c7b ldr r3, [r7, #68] @ 0x44 800da22: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800da26: 647b str r3, [r7, #68] @ 0x44 800da28: 6c7b ldr r3, [r7, #68] @ 0x44 800da2a: f043 0310 orr.w r3, r3, #16 800da2e: 647b str r3, [r7, #68] @ 0x44 800da30: 4a0e ldr r2, [pc, #56] @ (800da6c ) 800da32: 6c7b ldr r3, [r7, #68] @ 0x44 800da34: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); 800da36: 2200 movs r2, #0 800da38: 2100 movs r1, #0 800da3a: 2027 movs r0, #39 @ 0x27 800da3c: f001 fd79 bl 800f532 HAL_NVIC_EnableIRQ(USART3_IRQn); 800da40: 2027 movs r0, #39 @ 0x27 800da42: f001 fd92 bl 800f56a } 800da46: bf00 nop 800da48: 3748 adds r7, #72 @ 0x48 800da4a: 46bd mov sp, r7 800da4c: bd80 pop {r7, pc} 800da4e: bf00 nop 800da50: 40005000 .word 0x40005000 800da54: 40021000 .word 0x40021000 800da58: 40011000 .word 0x40011000 800da5c: 40011400 .word 0x40011400 800da60: 40013800 .word 0x40013800 800da64: 40010800 .word 0x40010800 800da68: 40004400 .word 0x40004400 800da6c: 40010000 .word 0x40010000 800da70: 40004800 .word 0x40004800 0800da74 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 800da74: f7ff fc64 bl 800d340 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 800da78: 480b ldr r0, [pc, #44] @ (800daa8 ) ldr r1, =_edata 800da7a: 490c ldr r1, [pc, #48] @ (800daac ) ldr r2, =_sidata 800da7c: 4a0c ldr r2, [pc, #48] @ (800dab0 ) movs r3, #0 800da7e: 2300 movs r3, #0 b LoopCopyDataInit 800da80: e002 b.n 800da88 0800da82 : CopyDataInit: ldr r4, [r2, r3] 800da82: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800da84: 50c4 str r4, [r0, r3] adds r3, r3, #4 800da86: 3304 adds r3, #4 0800da88 : LoopCopyDataInit: adds r4, r0, r3 800da88: 18c4 adds r4, r0, r3 cmp r4, r1 800da8a: 428c cmp r4, r1 bcc CopyDataInit 800da8c: d3f9 bcc.n 800da82 /* Zero fill the bss segment. */ ldr r2, =_sbss 800da8e: 4a09 ldr r2, [pc, #36] @ (800dab4 ) ldr r4, =_ebss 800da90: 4c09 ldr r4, [pc, #36] @ (800dab8 ) movs r3, #0 800da92: 2300 movs r3, #0 b LoopFillZerobss 800da94: e001 b.n 800da9a 0800da96 : FillZerobss: str r3, [r2] 800da96: 6013 str r3, [r2, #0] adds r2, r2, #4 800da98: 3204 adds r2, #4 0800da9a : LoopFillZerobss: cmp r2, r4 800da9a: 42a2 cmp r2, r4 bcc FillZerobss 800da9c: d3fb bcc.n 800da96 /* Call static constructors */ bl __libc_init_array 800da9e: f005 fffd bl 8013a9c <__libc_init_array> /* Call the application's entry point.*/ bl main 800daa2: f7fc ff8f bl 800a9c4
bx lr 800daa6: 4770 bx lr ldr r0, =_sdata 800daa8: 20000000 .word 0x20000000 ldr r1, =_edata 800daac: 20000240 .word 0x20000240 ldr r2, =_sidata 800dab0: 080164cc .word 0x080164cc ldr r2, =_sbss 800dab4: 20000240 .word 0x20000240 ldr r4, =_ebss 800dab8: 2000132c .word 0x2000132c 0800dabc : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 800dabc: e7fe b.n 800dabc ... 0800dac0 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800dac0: b580 push {r7, lr} 800dac2: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 800dac4: 4b08 ldr r3, [pc, #32] @ (800dae8 ) 800dac6: 681b ldr r3, [r3, #0] 800dac8: 4a07 ldr r2, [pc, #28] @ (800dae8 ) 800daca: f043 0310 orr.w r3, r3, #16 800dace: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800dad0: 2003 movs r0, #3 800dad2: f001 fd23 bl 800f51c /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800dad6: 200f movs r0, #15 800dad8: f000 f808 bl 800daec /* Init the low level hardware */ HAL_MspInit(); 800dadc: f7ff fadc bl 800d098 /* Return function status */ return HAL_OK; 800dae0: 2300 movs r3, #0 } 800dae2: 4618 mov r0, r3 800dae4: bd80 pop {r7, pc} 800dae6: bf00 nop 800dae8: 40022000 .word 0x40022000 0800daec : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800daec: b580 push {r7, lr} 800daee: b082 sub sp, #8 800daf0: af00 add r7, sp, #0 800daf2: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 800daf4: 4b12 ldr r3, [pc, #72] @ (800db40 ) 800daf6: 681a ldr r2, [r3, #0] 800daf8: 4b12 ldr r3, [pc, #72] @ (800db44 ) 800dafa: 781b ldrb r3, [r3, #0] 800dafc: 4619 mov r1, r3 800dafe: f44f 737a mov.w r3, #1000 @ 0x3e8 800db02: fbb3 f3f1 udiv r3, r3, r1 800db06: fbb2 f3f3 udiv r3, r2, r3 800db0a: 4618 mov r0, r3 800db0c: f001 fd3b bl 800f586 800db10: 4603 mov r3, r0 800db12: 2b00 cmp r3, #0 800db14: d001 beq.n 800db1a { return HAL_ERROR; 800db16: 2301 movs r3, #1 800db18: e00e b.n 800db38 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800db1a: 687b ldr r3, [r7, #4] 800db1c: 2b0f cmp r3, #15 800db1e: d80a bhi.n 800db36 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800db20: 2200 movs r2, #0 800db22: 6879 ldr r1, [r7, #4] 800db24: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800db28: f001 fd03 bl 800f532 uwTickPrio = TickPriority; 800db2c: 4a06 ldr r2, [pc, #24] @ (800db48 ) 800db2e: 687b ldr r3, [r7, #4] 800db30: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800db32: 2300 movs r3, #0 800db34: e000 b.n 800db38 return HAL_ERROR; 800db36: 2301 movs r3, #1 } 800db38: 4618 mov r0, r3 800db3a: 3708 adds r7, #8 800db3c: 46bd mov sp, r7 800db3e: bd80 pop {r7, pc} 800db40: 2000006c .word 0x2000006c 800db44: 20000074 .word 0x20000074 800db48: 20000070 .word 0x20000070 0800db4c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800db4c: b480 push {r7} 800db4e: af00 add r7, sp, #0 uwTick += uwTickFreq; 800db50: 4b05 ldr r3, [pc, #20] @ (800db68 ) 800db52: 781b ldrb r3, [r3, #0] 800db54: 461a mov r2, r3 800db56: 4b05 ldr r3, [pc, #20] @ (800db6c ) 800db58: 681b ldr r3, [r3, #0] 800db5a: 4413 add r3, r2 800db5c: 4a03 ldr r2, [pc, #12] @ (800db6c ) 800db5e: 6013 str r3, [r2, #0] } 800db60: bf00 nop 800db62: 46bd mov sp, r7 800db64: bc80 pop {r7} 800db66: 4770 bx lr 800db68: 20000074 .word 0x20000074 800db6c: 200011dc .word 0x200011dc 0800db70 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 800db70: b480 push {r7} 800db72: af00 add r7, sp, #0 return uwTick; 800db74: 4b02 ldr r3, [pc, #8] @ (800db80 ) 800db76: 681b ldr r3, [r3, #0] } 800db78: 4618 mov r0, r3 800db7a: 46bd mov sp, r7 800db7c: bc80 pop {r7} 800db7e: 4770 bx lr 800db80: 200011dc .word 0x200011dc 0800db84 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 800db84: b580 push {r7, lr} 800db86: b084 sub sp, #16 800db88: af00 add r7, sp, #0 800db8a: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800db8c: f7ff fff0 bl 800db70 800db90: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800db92: 687b ldr r3, [r7, #4] 800db94: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800db96: 68fb ldr r3, [r7, #12] 800db98: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800db9c: d005 beq.n 800dbaa { wait += (uint32_t)(uwTickFreq); 800db9e: 4b0a ldr r3, [pc, #40] @ (800dbc8 ) 800dba0: 781b ldrb r3, [r3, #0] 800dba2: 461a mov r2, r3 800dba4: 68fb ldr r3, [r7, #12] 800dba6: 4413 add r3, r2 800dba8: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 800dbaa: bf00 nop 800dbac: f7ff ffe0 bl 800db70 800dbb0: 4602 mov r2, r0 800dbb2: 68bb ldr r3, [r7, #8] 800dbb4: 1ad3 subs r3, r2, r3 800dbb6: 68fa ldr r2, [r7, #12] 800dbb8: 429a cmp r2, r3 800dbba: d8f7 bhi.n 800dbac { } } 800dbbc: bf00 nop 800dbbe: bf00 nop 800dbc0: 3710 adds r7, #16 800dbc2: 46bd mov sp, r7 800dbc4: bd80 pop {r7, pc} 800dbc6: bf00 nop 800dbc8: 20000074 .word 0x20000074 0800dbcc : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 800dbcc: b580 push {r7, lr} 800dbce: b086 sub sp, #24 800dbd0: af00 add r7, sp, #0 800dbd2: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800dbd4: 2300 movs r3, #0 800dbd6: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 800dbd8: 2300 movs r3, #0 800dbda: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 800dbdc: 2300 movs r3, #0 800dbde: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 800dbe0: 2300 movs r3, #0 800dbe2: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 800dbe4: 687b ldr r3, [r7, #4] 800dbe6: 2b00 cmp r3, #0 800dbe8: d101 bne.n 800dbee { return HAL_ERROR; 800dbea: 2301 movs r3, #1 800dbec: e0be b.n 800dd6c assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 800dbee: 687b ldr r3, [r7, #4] 800dbf0: 689b ldr r3, [r3, #8] 800dbf2: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 800dbf4: 687b ldr r3, [r7, #4] 800dbf6: 6a9b ldr r3, [r3, #40] @ 0x28 800dbf8: 2b00 cmp r3, #0 800dbfa: d109 bne.n 800dc10 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 800dbfc: 687b ldr r3, [r7, #4] 800dbfe: 2200 movs r2, #0 800dc00: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 800dc02: 687b ldr r3, [r7, #4] 800dc04: 2200 movs r2, #0 800dc06: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800dc0a: 6878 ldr r0, [r7, #4] 800dc0c: f7fb fcca bl 80095a4 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800dc10: 6878 ldr r0, [r7, #4] 800dc12: f000 fbf1 bl 800e3f8 800dc16: 4603 mov r3, r0 800dc18: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 800dc1a: 687b ldr r3, [r7, #4] 800dc1c: 6a9b ldr r3, [r3, #40] @ 0x28 800dc1e: f003 0310 and.w r3, r3, #16 800dc22: 2b00 cmp r3, #0 800dc24: f040 8099 bne.w 800dd5a 800dc28: 7dfb ldrb r3, [r7, #23] 800dc2a: 2b00 cmp r3, #0 800dc2c: f040 8095 bne.w 800dd5a (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800dc30: 687b ldr r3, [r7, #4] 800dc32: 6a9b ldr r3, [r3, #40] @ 0x28 800dc34: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800dc38: f023 0302 bic.w r3, r3, #2 800dc3c: f043 0202 orr.w r2, r3, #2 800dc40: 687b ldr r3, [r7, #4] 800dc42: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 800dc44: 687b ldr r3, [r7, #4] 800dc46: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800dc48: 687b ldr r3, [r7, #4] 800dc4a: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 800dc4c: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 800dc4e: 687b ldr r3, [r7, #4] 800dc50: 7b1b ldrb r3, [r3, #12] 800dc52: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800dc54: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 800dc56: 68ba ldr r2, [r7, #8] 800dc58: 4313 orrs r3, r2 800dc5a: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 800dc5c: 687b ldr r3, [r7, #4] 800dc5e: 689b ldr r3, [r3, #8] 800dc60: f5b3 7f80 cmp.w r3, #256 @ 0x100 800dc64: d003 beq.n 800dc6e 800dc66: 687b ldr r3, [r7, #4] 800dc68: 689b ldr r3, [r3, #8] 800dc6a: 2b01 cmp r3, #1 800dc6c: d102 bne.n 800dc74 800dc6e: f44f 7380 mov.w r3, #256 @ 0x100 800dc72: e000 b.n 800dc76 800dc74: 2300 movs r3, #0 800dc76: 693a ldr r2, [r7, #16] 800dc78: 4313 orrs r3, r2 800dc7a: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 800dc7c: 687b ldr r3, [r7, #4] 800dc7e: 7d1b ldrb r3, [r3, #20] 800dc80: 2b01 cmp r3, #1 800dc82: d119 bne.n 800dcb8 { if (hadc->Init.ContinuousConvMode == DISABLE) 800dc84: 687b ldr r3, [r7, #4] 800dc86: 7b1b ldrb r3, [r3, #12] 800dc88: 2b00 cmp r3, #0 800dc8a: d109 bne.n 800dca0 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 800dc8c: 687b ldr r3, [r7, #4] 800dc8e: 699b ldr r3, [r3, #24] 800dc90: 3b01 subs r3, #1 800dc92: 035a lsls r2, r3, #13 800dc94: 693b ldr r3, [r7, #16] 800dc96: 4313 orrs r3, r2 800dc98: f443 6300 orr.w r3, r3, #2048 @ 0x800 800dc9c: 613b str r3, [r7, #16] 800dc9e: e00b b.n 800dcb8 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800dca0: 687b ldr r3, [r7, #4] 800dca2: 6a9b ldr r3, [r3, #40] @ 0x28 800dca4: f043 0220 orr.w r2, r3, #32 800dca8: 687b ldr r3, [r7, #4] 800dcaa: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800dcac: 687b ldr r3, [r7, #4] 800dcae: 6adb ldr r3, [r3, #44] @ 0x2c 800dcb0: f043 0201 orr.w r2, r3, #1 800dcb4: 687b ldr r3, [r7, #4] 800dcb6: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 800dcb8: 687b ldr r3, [r7, #4] 800dcba: 681b ldr r3, [r3, #0] 800dcbc: 685b ldr r3, [r3, #4] 800dcbe: f423 4169 bic.w r1, r3, #59648 @ 0xe900 800dcc2: 687b ldr r3, [r7, #4] 800dcc4: 681b ldr r3, [r3, #0] 800dcc6: 693a ldr r2, [r7, #16] 800dcc8: 430a orrs r2, r1 800dcca: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 800dccc: 687b ldr r3, [r7, #4] 800dcce: 681b ldr r3, [r3, #0] 800dcd0: 689a ldr r2, [r3, #8] 800dcd2: 4b28 ldr r3, [pc, #160] @ (800dd74 ) 800dcd4: 4013 ands r3, r2 800dcd6: 687a ldr r2, [r7, #4] 800dcd8: 6812 ldr r2, [r2, #0] 800dcda: 68b9 ldr r1, [r7, #8] 800dcdc: 430b orrs r3, r1 800dcde: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 800dce0: 687b ldr r3, [r7, #4] 800dce2: 689b ldr r3, [r3, #8] 800dce4: f5b3 7f80 cmp.w r3, #256 @ 0x100 800dce8: d003 beq.n 800dcf2 800dcea: 687b ldr r3, [r7, #4] 800dcec: 689b ldr r3, [r3, #8] 800dcee: 2b01 cmp r3, #1 800dcf0: d104 bne.n 800dcfc { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 800dcf2: 687b ldr r3, [r7, #4] 800dcf4: 691b ldr r3, [r3, #16] 800dcf6: 3b01 subs r3, #1 800dcf8: 051b lsls r3, r3, #20 800dcfa: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 800dcfc: 687b ldr r3, [r7, #4] 800dcfe: 681b ldr r3, [r3, #0] 800dd00: 6adb ldr r3, [r3, #44] @ 0x2c 800dd02: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 800dd06: 687b ldr r3, [r7, #4] 800dd08: 681b ldr r3, [r3, #0] 800dd0a: 68fa ldr r2, [r7, #12] 800dd0c: 430a orrs r2, r1 800dd0e: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800dd10: 687b ldr r3, [r7, #4] 800dd12: 681b ldr r3, [r3, #0] 800dd14: 689a ldr r2, [r3, #8] 800dd16: 4b18 ldr r3, [pc, #96] @ (800dd78 ) 800dd18: 4013 ands r3, r2 800dd1a: 68ba ldr r2, [r7, #8] 800dd1c: 429a cmp r2, r3 800dd1e: d10b bne.n 800dd38 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 800dd20: 687b ldr r3, [r7, #4] 800dd22: 2200 movs r2, #0 800dd24: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 800dd26: 687b ldr r3, [r7, #4] 800dd28: 6a9b ldr r3, [r3, #40] @ 0x28 800dd2a: f023 0303 bic.w r3, r3, #3 800dd2e: f043 0201 orr.w r2, r3, #1 800dd32: 687b ldr r3, [r7, #4] 800dd34: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800dd36: e018 b.n 800dd6a HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800dd38: 687b ldr r3, [r7, #4] 800dd3a: 6a9b ldr r3, [r3, #40] @ 0x28 800dd3c: f023 0312 bic.w r3, r3, #18 800dd40: f043 0210 orr.w r2, r3, #16 800dd44: 687b ldr r3, [r7, #4] 800dd46: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800dd48: 687b ldr r3, [r7, #4] 800dd4a: 6adb ldr r3, [r3, #44] @ 0x2c 800dd4c: f043 0201 orr.w r2, r3, #1 800dd50: 687b ldr r3, [r7, #4] 800dd52: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 800dd54: 2301 movs r3, #1 800dd56: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800dd58: e007 b.n 800dd6a } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800dd5a: 687b ldr r3, [r7, #4] 800dd5c: 6a9b ldr r3, [r3, #40] @ 0x28 800dd5e: f043 0210 orr.w r2, r3, #16 800dd62: 687b ldr r3, [r7, #4] 800dd64: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800dd66: 2301 movs r3, #1 800dd68: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800dd6a: 7dfb ldrb r3, [r7, #23] } 800dd6c: 4618 mov r0, r3 800dd6e: 3718 adds r7, #24 800dd70: 46bd mov sp, r7 800dd72: bd80 pop {r7, pc} 800dd74: ffe1f7fd .word 0xffe1f7fd 800dd78: ff1f0efe .word 0xff1f0efe 0800dd7c : * Interruptions enabled in this function: None. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { 800dd7c: b580 push {r7, lr} 800dd7e: b084 sub sp, #16 800dd80: af00 add r7, sp, #0 800dd82: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800dd84: 2300 movs r3, #0 800dd86: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800dd88: 687b ldr r3, [r7, #4] 800dd8a: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800dd8e: 2b01 cmp r3, #1 800dd90: d101 bne.n 800dd96 800dd92: 2302 movs r3, #2 800dd94: e098 b.n 800dec8 800dd96: 687b ldr r3, [r7, #4] 800dd98: 2201 movs r2, #1 800dd9a: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 800dd9e: 6878 ldr r0, [r7, #4] 800dda0: f000 fad0 bl 800e344 800dda4: 4603 mov r3, r0 800dda6: 73fb strb r3, [r7, #15] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800dda8: 7bfb ldrb r3, [r7, #15] 800ddaa: 2b00 cmp r3, #0 800ddac: f040 8087 bne.w 800debe { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 800ddb0: 687b ldr r3, [r7, #4] 800ddb2: 6a9b ldr r3, [r3, #40] @ 0x28 800ddb4: f423 7340 bic.w r3, r3, #768 @ 0x300 800ddb8: f023 0301 bic.w r3, r3, #1 800ddbc: f443 7280 orr.w r2, r3, #256 @ 0x100 800ddc0: 687b ldr r3, [r7, #4] 800ddc2: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 800ddc4: 687b ldr r3, [r7, #4] 800ddc6: 681b ldr r3, [r3, #0] 800ddc8: 4a41 ldr r2, [pc, #260] @ (800ded0 ) 800ddca: 4293 cmp r3, r2 800ddcc: d105 bne.n 800ddda 800ddce: 4b41 ldr r3, [pc, #260] @ (800ded4 ) 800ddd0: 685b ldr r3, [r3, #4] 800ddd2: f403 2370 and.w r3, r3, #983040 @ 0xf0000 800ddd6: 2b00 cmp r3, #0 800ddd8: d115 bne.n 800de06 { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800ddda: 687b ldr r3, [r7, #4] 800dddc: 6a9b ldr r3, [r3, #40] @ 0x28 800ddde: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 800dde2: 687b ldr r3, [r7, #4] 800dde4: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800dde6: 687b ldr r3, [r7, #4] 800dde8: 681b ldr r3, [r3, #0] 800ddea: 685b ldr r3, [r3, #4] 800ddec: f403 6380 and.w r3, r3, #1024 @ 0x400 800ddf0: 2b00 cmp r3, #0 800ddf2: d026 beq.n 800de42 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800ddf4: 687b ldr r3, [r7, #4] 800ddf6: 6a9b ldr r3, [r3, #40] @ 0x28 800ddf8: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800ddfc: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800de00: 687b ldr r3, [r7, #4] 800de02: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800de04: e01d b.n 800de42 } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800de06: 687b ldr r3, [r7, #4] 800de08: 6a9b ldr r3, [r3, #40] @ 0x28 800de0a: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800de0e: 687b ldr r3, [r7, #4] 800de10: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 800de12: 687b ldr r3, [r7, #4] 800de14: 681b ldr r3, [r3, #0] 800de16: 4a2f ldr r2, [pc, #188] @ (800ded4 ) 800de18: 4293 cmp r3, r2 800de1a: d004 beq.n 800de26 800de1c: 687b ldr r3, [r7, #4] 800de1e: 681b ldr r3, [r3, #0] 800de20: 4a2b ldr r2, [pc, #172] @ (800ded0 ) 800de22: 4293 cmp r3, r2 800de24: d10d bne.n 800de42 800de26: 4b2b ldr r3, [pc, #172] @ (800ded4 ) 800de28: 685b ldr r3, [r3, #4] 800de2a: f403 6380 and.w r3, r3, #1024 @ 0x400 800de2e: 2b00 cmp r3, #0 800de30: d007 beq.n 800de42 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800de32: 687b ldr r3, [r7, #4] 800de34: 6a9b ldr r3, [r3, #40] @ 0x28 800de36: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800de3a: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800de3e: 687b ldr r3, [r7, #4] 800de40: 629a str r2, [r3, #40] @ 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800de42: 687b ldr r3, [r7, #4] 800de44: 6a9b ldr r3, [r3, #40] @ 0x28 800de46: f403 5380 and.w r3, r3, #4096 @ 0x1000 800de4a: 2b00 cmp r3, #0 800de4c: d006 beq.n 800de5c { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 800de4e: 687b ldr r3, [r7, #4] 800de50: 6adb ldr r3, [r3, #44] @ 0x2c 800de52: f023 0206 bic.w r2, r3, #6 800de56: 687b ldr r3, [r7, #4] 800de58: 62da str r2, [r3, #44] @ 0x2c 800de5a: e002 b.n 800de62 } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 800de5c: 687b ldr r3, [r7, #4] 800de5e: 2200 movs r2, #0 800de60: 62da str r2, [r3, #44] @ 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 800de62: 687b ldr r3, [r7, #4] 800de64: 2200 movs r2, #0 800de66: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Clear regular group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 800de6a: 687b ldr r3, [r7, #4] 800de6c: 681b ldr r3, [r3, #0] 800de6e: f06f 0202 mvn.w r2, #2 800de72: 601a str r2, [r3, #0] /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ /* If ADC is master, ADC is enabled and conversion is started. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800de74: 687b ldr r3, [r7, #4] 800de76: 681b ldr r3, [r3, #0] 800de78: 689b ldr r3, [r3, #8] 800de7a: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800de7e: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800de82: d113 bne.n 800deac ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 800de84: 687b ldr r3, [r7, #4] 800de86: 681b ldr r3, [r3, #0] if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800de88: 4a11 ldr r2, [pc, #68] @ (800ded0 ) 800de8a: 4293 cmp r3, r2 800de8c: d105 bne.n 800de9a ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 800de8e: 4b11 ldr r3, [pc, #68] @ (800ded4 ) 800de90: 685b ldr r3, [r3, #4] 800de92: f403 2370 and.w r3, r3, #983040 @ 0xf0000 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800de96: 2b00 cmp r3, #0 800de98: d108 bne.n 800deac { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 800de9a: 687b ldr r3, [r7, #4] 800de9c: 681b ldr r3, [r3, #0] 800de9e: 689a ldr r2, [r3, #8] 800dea0: 687b ldr r3, [r7, #4] 800dea2: 681b ldr r3, [r3, #0] 800dea4: f442 02a0 orr.w r2, r2, #5242880 @ 0x500000 800dea8: 609a str r2, [r3, #8] 800deaa: e00c b.n 800dec6 } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 800deac: 687b ldr r3, [r7, #4] 800deae: 681b ldr r3, [r3, #0] 800deb0: 689a ldr r2, [r3, #8] 800deb2: 687b ldr r3, [r7, #4] 800deb4: 681b ldr r3, [r3, #0] 800deb6: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 800deba: 609a str r2, [r3, #8] 800debc: e003 b.n 800dec6 } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 800debe: 687b ldr r3, [r7, #4] 800dec0: 2200 movs r2, #0 800dec2: f883 2024 strb.w r2, [r3, #36] @ 0x24 } /* Return function status */ return tmp_hal_status; 800dec6: 7bfb ldrb r3, [r7, #15] } 800dec8: 4618 mov r0, r3 800deca: 3710 adds r7, #16 800decc: 46bd mov sp, r7 800dece: bd80 pop {r7, pc} 800ded0: 40012800 .word 0x40012800 800ded4: 40012400 .word 0x40012400 0800ded8 : * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { 800ded8: b580 push {r7, lr} 800deda: b084 sub sp, #16 800dedc: af00 add r7, sp, #0 800dede: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800dee0: 2300 movs r3, #0 800dee2: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800dee4: 687b ldr r3, [r7, #4] 800dee6: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800deea: 2b01 cmp r3, #1 800deec: d101 bne.n 800def2 800deee: 2302 movs r3, #2 800def0: e01a b.n 800df28 800def2: 687b ldr r3, [r7, #4] 800def4: 2201 movs r2, #1 800def6: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800defa: 6878 ldr r0, [r7, #4] 800defc: f000 fa7c bl 800e3f8 800df00: 4603 mov r3, r0 800df02: 73fb strb r3, [r7, #15] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 800df04: 7bfb ldrb r3, [r7, #15] 800df06: 2b00 cmp r3, #0 800df08: d109 bne.n 800df1e { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800df0a: 687b ldr r3, [r7, #4] 800df0c: 6a9b ldr r3, [r3, #40] @ 0x28 800df0e: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800df12: f023 0301 bic.w r3, r3, #1 800df16: f043 0201 orr.w r2, r3, #1 800df1a: 687b ldr r3, [r7, #4] 800df1c: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 800df1e: 687b ldr r3, [r7, #4] 800df20: 2200 movs r2, #0 800df22: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800df26: 7bfb ldrb r3, [r7, #15] } 800df28: 4618 mov r0, r3 800df2a: 3710 adds r7, #16 800df2c: 46bd mov sp, r7 800df2e: bd80 pop {r7, pc} 0800df30 : * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { 800df30: b590 push {r4, r7, lr} 800df32: b087 sub sp, #28 800df34: af00 add r7, sp, #0 800df36: 6078 str r0, [r7, #4] 800df38: 6039 str r1, [r7, #0] uint32_t tickstart = 0U; 800df3a: 2300 movs r3, #0 800df3c: 617b str r3, [r7, #20] /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; 800df3e: 2300 movs r3, #0 800df40: 60fb str r3, [r7, #12] uint32_t Conversion_Timeout_CPU_cycles_max = 0U; 800df42: 2300 movs r3, #0 800df44: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Get tick count */ tickstart = HAL_GetTick(); 800df46: f7ff fe13 bl 800db70 800df4a: 6178 str r0, [r7, #20] /* Verification that ADC configuration is compliant with polling for */ /* each conversion: */ /* Particular case is ADC configured in DMA mode */ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) 800df4c: 687b ldr r3, [r7, #4] 800df4e: 681b ldr r3, [r3, #0] 800df50: 689b ldr r3, [r3, #8] 800df52: f403 7380 and.w r3, r3, #256 @ 0x100 800df56: 2b00 cmp r3, #0 800df58: d00b beq.n 800df72 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800df5a: 687b ldr r3, [r7, #4] 800df5c: 6a9b ldr r3, [r3, #40] @ 0x28 800df5e: f043 0220 orr.w r2, r3, #32 800df62: 687b ldr r3, [r7, #4] 800df64: 629a str r2, [r3, #40] @ 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 800df66: 687b ldr r3, [r7, #4] 800df68: 2200 movs r2, #0 800df6a: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800df6e: 2301 movs r3, #1 800df70: e0d3 b.n 800e11a /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ /* As flag EOC is not set after each conversion, no timeout status can */ /* be set. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 800df72: 687b ldr r3, [r7, #4] 800df74: 681b ldr r3, [r3, #0] 800df76: 685b ldr r3, [r3, #4] 800df78: f403 7380 and.w r3, r3, #256 @ 0x100 800df7c: 2b00 cmp r3, #0 800df7e: d131 bne.n 800dfe4 HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ) 800df80: 687b ldr r3, [r7, #4] 800df82: 681b ldr r3, [r3, #0] 800df84: 6adb ldr r3, [r3, #44] @ 0x2c 800df86: f403 0370 and.w r3, r3, #15728640 @ 0xf00000 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 800df8a: 2b00 cmp r3, #0 800df8c: d12a bne.n 800dfe4 { /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 800df8e: e021 b.n 800dfd4 { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 800df90: 683b ldr r3, [r7, #0] 800df92: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800df96: d01d beq.n 800dfd4 { if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) 800df98: 683b ldr r3, [r7, #0] 800df9a: 2b00 cmp r3, #0 800df9c: d007 beq.n 800dfae 800df9e: f7ff fde7 bl 800db70 800dfa2: 4602 mov r2, r0 800dfa4: 697b ldr r3, [r7, #20] 800dfa6: 1ad3 subs r3, r2, r3 800dfa8: 683a ldr r2, [r7, #0] 800dfaa: 429a cmp r2, r3 800dfac: d212 bcs.n 800dfd4 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 800dfae: 687b ldr r3, [r7, #4] 800dfb0: 681b ldr r3, [r3, #0] 800dfb2: 681b ldr r3, [r3, #0] 800dfb4: f003 0302 and.w r3, r3, #2 800dfb8: 2b00 cmp r3, #0 800dfba: d10b bne.n 800dfd4 { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 800dfbc: 687b ldr r3, [r7, #4] 800dfbe: 6a9b ldr r3, [r3, #40] @ 0x28 800dfc0: f043 0204 orr.w r2, r3, #4 800dfc4: 687b ldr r3, [r7, #4] 800dfc6: 629a str r2, [r3, #40] @ 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 800dfc8: 687b ldr r3, [r7, #4] 800dfca: 2200 movs r2, #0 800dfcc: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_TIMEOUT; 800dfd0: 2303 movs r3, #3 800dfd2: e0a2 b.n 800e11a while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 800dfd4: 687b ldr r3, [r7, #4] 800dfd6: 681b ldr r3, [r3, #0] 800dfd8: 681b ldr r3, [r3, #0] 800dfda: f003 0302 and.w r3, r3, #2 800dfde: 2b00 cmp r3, #0 800dfe0: d0d6 beq.n 800df90 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 800dfe2: e070 b.n 800e0c6 /* Replace polling by wait for maximum conversion time */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ /* and ADC maximum conversion cycles on all channels. */ /* - Wait for the expected ADC clock cycles delay */ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 800dfe4: 4b4f ldr r3, [pc, #316] @ (800e124 ) 800dfe6: 681c ldr r4, [r3, #0] 800dfe8: 2002 movs r0, #2 800dfea: f002 fd05 bl 80109f8 800dfee: 4603 mov r3, r0 800dff0: fbb4 f2f3 udiv r2, r4, r3 * ADC_CONVCYCLES_MAX_RANGE(hadc) ); 800dff4: 687b ldr r3, [r7, #4] 800dff6: 681b ldr r3, [r3, #0] 800dff8: 6919 ldr r1, [r3, #16] 800dffa: 4b4b ldr r3, [pc, #300] @ (800e128 ) 800dffc: 400b ands r3, r1 800dffe: 2b00 cmp r3, #0 800e000: d118 bne.n 800e034 800e002: 687b ldr r3, [r7, #4] 800e004: 681b ldr r3, [r3, #0] 800e006: 68d9 ldr r1, [r3, #12] 800e008: 4b48 ldr r3, [pc, #288] @ (800e12c ) 800e00a: 400b ands r3, r1 800e00c: 2b00 cmp r3, #0 800e00e: d111 bne.n 800e034 800e010: 687b ldr r3, [r7, #4] 800e012: 681b ldr r3, [r3, #0] 800e014: 6919 ldr r1, [r3, #16] 800e016: 4b46 ldr r3, [pc, #280] @ (800e130 ) 800e018: 400b ands r3, r1 800e01a: 2b00 cmp r3, #0 800e01c: d108 bne.n 800e030 800e01e: 687b ldr r3, [r7, #4] 800e020: 681b ldr r3, [r3, #0] 800e022: 68d9 ldr r1, [r3, #12] 800e024: 4b43 ldr r3, [pc, #268] @ (800e134 ) 800e026: 400b ands r3, r1 800e028: 2b00 cmp r3, #0 800e02a: d101 bne.n 800e030 800e02c: 2314 movs r3, #20 800e02e: e020 b.n 800e072 800e030: 2329 movs r3, #41 @ 0x29 800e032: e01e b.n 800e072 800e034: 687b ldr r3, [r7, #4] 800e036: 681b ldr r3, [r3, #0] 800e038: 6919 ldr r1, [r3, #16] 800e03a: 4b3d ldr r3, [pc, #244] @ (800e130 ) 800e03c: 400b ands r3, r1 800e03e: 2b00 cmp r3, #0 800e040: d106 bne.n 800e050 800e042: 687b ldr r3, [r7, #4] 800e044: 681b ldr r3, [r3, #0] 800e046: 68d9 ldr r1, [r3, #12] 800e048: 4b3a ldr r3, [pc, #232] @ (800e134 ) 800e04a: 400b ands r3, r1 800e04c: 2b00 cmp r3, #0 800e04e: d00d beq.n 800e06c 800e050: 687b ldr r3, [r7, #4] 800e052: 681b ldr r3, [r3, #0] 800e054: 6919 ldr r1, [r3, #16] 800e056: 4b38 ldr r3, [pc, #224] @ (800e138 ) 800e058: 400b ands r3, r1 800e05a: 2b00 cmp r3, #0 800e05c: d108 bne.n 800e070 800e05e: 687b ldr r3, [r7, #4] 800e060: 681b ldr r3, [r3, #0] 800e062: 68d9 ldr r1, [r3, #12] 800e064: 4b34 ldr r3, [pc, #208] @ (800e138 ) 800e066: 400b ands r3, r1 800e068: 2b00 cmp r3, #0 800e06a: d101 bne.n 800e070 800e06c: 2354 movs r3, #84 @ 0x54 800e06e: e000 b.n 800e072 800e070: 23fc movs r3, #252 @ 0xfc Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock 800e072: fb02 f303 mul.w r3, r2, r3 800e076: 613b str r3, [r7, #16] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 800e078: e021 b.n 800e0be { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 800e07a: 683b ldr r3, [r7, #0] 800e07c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800e080: d01a beq.n 800e0b8 { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) 800e082: 683b ldr r3, [r7, #0] 800e084: 2b00 cmp r3, #0 800e086: d007 beq.n 800e098 800e088: f7ff fd72 bl 800db70 800e08c: 4602 mov r2, r0 800e08e: 697b ldr r3, [r7, #20] 800e090: 1ad3 subs r3, r2, r3 800e092: 683a ldr r2, [r7, #0] 800e094: 429a cmp r2, r3 800e096: d20f bcs.n 800e0b8 { /* New check to avoid false timeout detection in case of preemption */ if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 800e098: 68fb ldr r3, [r7, #12] 800e09a: 693a ldr r2, [r7, #16] 800e09c: 429a cmp r2, r3 800e09e: d90b bls.n 800e0b8 { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 800e0a0: 687b ldr r3, [r7, #4] 800e0a2: 6a9b ldr r3, [r3, #40] @ 0x28 800e0a4: f043 0204 orr.w r2, r3, #4 800e0a8: 687b ldr r3, [r7, #4] 800e0aa: 629a str r2, [r3, #40] @ 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 800e0ac: 687b ldr r3, [r7, #4] 800e0ae: 2200 movs r2, #0 800e0b0: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_TIMEOUT; 800e0b4: 2303 movs r3, #3 800e0b6: e030 b.n 800e11a } } } Conversion_Timeout_CPU_cycles ++; 800e0b8: 68fb ldr r3, [r7, #12] 800e0ba: 3301 adds r3, #1 800e0bc: 60fb str r3, [r7, #12] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 800e0be: 68fb ldr r3, [r7, #12] 800e0c0: 693a ldr r2, [r7, #16] 800e0c2: 429a cmp r2, r3 800e0c4: d8d9 bhi.n 800e07a } } /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 800e0c6: 687b ldr r3, [r7, #4] 800e0c8: 681b ldr r3, [r3, #0] 800e0ca: f06f 0212 mvn.w r2, #18 800e0ce: 601a str r2, [r3, #0] /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800e0d0: 687b ldr r3, [r7, #4] 800e0d2: 6a9b ldr r3, [r3, #40] @ 0x28 800e0d4: f443 7200 orr.w r2, r3, #512 @ 0x200 800e0d8: 687b ldr r3, [r7, #4] 800e0da: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e0dc: 687b ldr r3, [r7, #4] 800e0de: 681b ldr r3, [r3, #0] 800e0e0: 689b ldr r3, [r3, #8] 800e0e2: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800e0e6: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e0ea: d115 bne.n 800e118 (hadc->Init.ContinuousConvMode == DISABLE) ) 800e0ec: 687b ldr r3, [r7, #4] 800e0ee: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e0f0: 2b00 cmp r3, #0 800e0f2: d111 bne.n 800e118 { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800e0f4: 687b ldr r3, [r7, #4] 800e0f6: 6a9b ldr r3, [r3, #40] @ 0x28 800e0f8: f423 7280 bic.w r2, r3, #256 @ 0x100 800e0fc: 687b ldr r3, [r7, #4] 800e0fe: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800e100: 687b ldr r3, [r7, #4] 800e102: 6a9b ldr r3, [r3, #40] @ 0x28 800e104: f403 5380 and.w r3, r3, #4096 @ 0x1000 800e108: 2b00 cmp r3, #0 800e10a: d105 bne.n 800e118 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800e10c: 687b ldr r3, [r7, #4] 800e10e: 6a9b ldr r3, [r3, #40] @ 0x28 800e110: f043 0201 orr.w r2, r3, #1 800e114: 687b ldr r3, [r7, #4] 800e116: 629a str r2, [r3, #40] @ 0x28 } } /* Return ADC state */ return HAL_OK; 800e118: 2300 movs r3, #0 } 800e11a: 4618 mov r0, r3 800e11c: 371c adds r7, #28 800e11e: 46bd mov sp, r7 800e120: bd90 pop {r4, r7, pc} 800e122: bf00 nop 800e124: 2000006c .word 0x2000006c 800e128: 24924924 .word 0x24924924 800e12c: 00924924 .word 0x00924924 800e130: 12492492 .word 0x12492492 800e134: 00492492 .word 0x00492492 800e138: 00249249 .word 0x00249249 0800e13c : * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc: ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { 800e13c: b480 push {r7} 800e13e: b083 sub sp, #12 800e140: af00 add r7, sp, #0 800e142: 6078 str r0, [r7, #4] /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; 800e144: 687b ldr r3, [r7, #4] 800e146: 681b ldr r3, [r3, #0] 800e148: 6cdb ldr r3, [r3, #76] @ 0x4c } 800e14a: 4618 mov r0, r3 800e14c: 370c adds r7, #12 800e14e: 46bd mov sp, r7 800e150: bc80 pop {r7} 800e152: 4770 bx lr 0800e154 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 800e154: b480 push {r7} 800e156: b085 sub sp, #20 800e158: af00 add r7, sp, #0 800e15a: 6078 str r0, [r7, #4] 800e15c: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e15e: 2300 movs r3, #0 800e160: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 800e162: 2300 movs r3, #0 800e164: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 800e166: 687b ldr r3, [r7, #4] 800e168: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e16c: 2b01 cmp r3, #1 800e16e: d101 bne.n 800e174 800e170: 2302 movs r3, #2 800e172: e0dc b.n 800e32e 800e174: 687b ldr r3, [r7, #4] 800e176: 2201 movs r2, #1 800e178: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 800e17c: 683b ldr r3, [r7, #0] 800e17e: 685b ldr r3, [r3, #4] 800e180: 2b06 cmp r3, #6 800e182: d81c bhi.n 800e1be { MODIFY_REG(hadc->Instance->SQR3 , 800e184: 687b ldr r3, [r7, #4] 800e186: 681b ldr r3, [r3, #0] 800e188: 6b59 ldr r1, [r3, #52] @ 0x34 800e18a: 683b ldr r3, [r7, #0] 800e18c: 685a ldr r2, [r3, #4] 800e18e: 4613 mov r3, r2 800e190: 009b lsls r3, r3, #2 800e192: 4413 add r3, r2 800e194: 3b05 subs r3, #5 800e196: 221f movs r2, #31 800e198: fa02 f303 lsl.w r3, r2, r3 800e19c: 43db mvns r3, r3 800e19e: 4019 ands r1, r3 800e1a0: 683b ldr r3, [r7, #0] 800e1a2: 6818 ldr r0, [r3, #0] 800e1a4: 683b ldr r3, [r7, #0] 800e1a6: 685a ldr r2, [r3, #4] 800e1a8: 4613 mov r3, r2 800e1aa: 009b lsls r3, r3, #2 800e1ac: 4413 add r3, r2 800e1ae: 3b05 subs r3, #5 800e1b0: fa00 f203 lsl.w r2, r0, r3 800e1b4: 687b ldr r3, [r7, #4] 800e1b6: 681b ldr r3, [r3, #0] 800e1b8: 430a orrs r2, r1 800e1ba: 635a str r2, [r3, #52] @ 0x34 800e1bc: e03c b.n 800e238 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 800e1be: 683b ldr r3, [r7, #0] 800e1c0: 685b ldr r3, [r3, #4] 800e1c2: 2b0c cmp r3, #12 800e1c4: d81c bhi.n 800e200 { MODIFY_REG(hadc->Instance->SQR2 , 800e1c6: 687b ldr r3, [r7, #4] 800e1c8: 681b ldr r3, [r3, #0] 800e1ca: 6b19 ldr r1, [r3, #48] @ 0x30 800e1cc: 683b ldr r3, [r7, #0] 800e1ce: 685a ldr r2, [r3, #4] 800e1d0: 4613 mov r3, r2 800e1d2: 009b lsls r3, r3, #2 800e1d4: 4413 add r3, r2 800e1d6: 3b23 subs r3, #35 @ 0x23 800e1d8: 221f movs r2, #31 800e1da: fa02 f303 lsl.w r3, r2, r3 800e1de: 43db mvns r3, r3 800e1e0: 4019 ands r1, r3 800e1e2: 683b ldr r3, [r7, #0] 800e1e4: 6818 ldr r0, [r3, #0] 800e1e6: 683b ldr r3, [r7, #0] 800e1e8: 685a ldr r2, [r3, #4] 800e1ea: 4613 mov r3, r2 800e1ec: 009b lsls r3, r3, #2 800e1ee: 4413 add r3, r2 800e1f0: 3b23 subs r3, #35 @ 0x23 800e1f2: fa00 f203 lsl.w r2, r0, r3 800e1f6: 687b ldr r3, [r7, #4] 800e1f8: 681b ldr r3, [r3, #0] 800e1fa: 430a orrs r2, r1 800e1fc: 631a str r2, [r3, #48] @ 0x30 800e1fe: e01b b.n 800e238 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 800e200: 687b ldr r3, [r7, #4] 800e202: 681b ldr r3, [r3, #0] 800e204: 6ad9 ldr r1, [r3, #44] @ 0x2c 800e206: 683b ldr r3, [r7, #0] 800e208: 685a ldr r2, [r3, #4] 800e20a: 4613 mov r3, r2 800e20c: 009b lsls r3, r3, #2 800e20e: 4413 add r3, r2 800e210: 3b41 subs r3, #65 @ 0x41 800e212: 221f movs r2, #31 800e214: fa02 f303 lsl.w r3, r2, r3 800e218: 43db mvns r3, r3 800e21a: 4019 ands r1, r3 800e21c: 683b ldr r3, [r7, #0] 800e21e: 6818 ldr r0, [r3, #0] 800e220: 683b ldr r3, [r7, #0] 800e222: 685a ldr r2, [r3, #4] 800e224: 4613 mov r3, r2 800e226: 009b lsls r3, r3, #2 800e228: 4413 add r3, r2 800e22a: 3b41 subs r3, #65 @ 0x41 800e22c: fa00 f203 lsl.w r2, r0, r3 800e230: 687b ldr r3, [r7, #4] 800e232: 681b ldr r3, [r3, #0] 800e234: 430a orrs r2, r1 800e236: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 800e238: 683b ldr r3, [r7, #0] 800e23a: 681b ldr r3, [r3, #0] 800e23c: 2b09 cmp r3, #9 800e23e: d91c bls.n 800e27a { MODIFY_REG(hadc->Instance->SMPR1 , 800e240: 687b ldr r3, [r7, #4] 800e242: 681b ldr r3, [r3, #0] 800e244: 68d9 ldr r1, [r3, #12] 800e246: 683b ldr r3, [r7, #0] 800e248: 681a ldr r2, [r3, #0] 800e24a: 4613 mov r3, r2 800e24c: 005b lsls r3, r3, #1 800e24e: 4413 add r3, r2 800e250: 3b1e subs r3, #30 800e252: 2207 movs r2, #7 800e254: fa02 f303 lsl.w r3, r2, r3 800e258: 43db mvns r3, r3 800e25a: 4019 ands r1, r3 800e25c: 683b ldr r3, [r7, #0] 800e25e: 6898 ldr r0, [r3, #8] 800e260: 683b ldr r3, [r7, #0] 800e262: 681a ldr r2, [r3, #0] 800e264: 4613 mov r3, r2 800e266: 005b lsls r3, r3, #1 800e268: 4413 add r3, r2 800e26a: 3b1e subs r3, #30 800e26c: fa00 f203 lsl.w r2, r0, r3 800e270: 687b ldr r3, [r7, #4] 800e272: 681b ldr r3, [r3, #0] 800e274: 430a orrs r2, r1 800e276: 60da str r2, [r3, #12] 800e278: e019 b.n 800e2ae ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 800e27a: 687b ldr r3, [r7, #4] 800e27c: 681b ldr r3, [r3, #0] 800e27e: 6919 ldr r1, [r3, #16] 800e280: 683b ldr r3, [r7, #0] 800e282: 681a ldr r2, [r3, #0] 800e284: 4613 mov r3, r2 800e286: 005b lsls r3, r3, #1 800e288: 4413 add r3, r2 800e28a: 2207 movs r2, #7 800e28c: fa02 f303 lsl.w r3, r2, r3 800e290: 43db mvns r3, r3 800e292: 4019 ands r1, r3 800e294: 683b ldr r3, [r7, #0] 800e296: 6898 ldr r0, [r3, #8] 800e298: 683b ldr r3, [r7, #0] 800e29a: 681a ldr r2, [r3, #0] 800e29c: 4613 mov r3, r2 800e29e: 005b lsls r3, r3, #1 800e2a0: 4413 add r3, r2 800e2a2: fa00 f203 lsl.w r2, r0, r3 800e2a6: 687b ldr r3, [r7, #4] 800e2a8: 681b ldr r3, [r3, #0] 800e2aa: 430a orrs r2, r1 800e2ac: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800e2ae: 683b ldr r3, [r7, #0] 800e2b0: 681b ldr r3, [r3, #0] 800e2b2: 2b10 cmp r3, #16 800e2b4: d003 beq.n 800e2be (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 800e2b6: 683b ldr r3, [r7, #0] 800e2b8: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800e2ba: 2b11 cmp r3, #17 800e2bc: d132 bne.n 800e324 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 800e2be: 687b ldr r3, [r7, #4] 800e2c0: 681b ldr r3, [r3, #0] 800e2c2: 4a1d ldr r2, [pc, #116] @ (800e338 ) 800e2c4: 4293 cmp r3, r2 800e2c6: d125 bne.n 800e314 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 800e2c8: 687b ldr r3, [r7, #4] 800e2ca: 681b ldr r3, [r3, #0] 800e2cc: 689b ldr r3, [r3, #8] 800e2ce: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800e2d2: 2b00 cmp r3, #0 800e2d4: d126 bne.n 800e324 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 800e2d6: 687b ldr r3, [r7, #4] 800e2d8: 681b ldr r3, [r3, #0] 800e2da: 689a ldr r2, [r3, #8] 800e2dc: 687b ldr r3, [r7, #4] 800e2de: 681b ldr r3, [r3, #0] 800e2e0: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 800e2e4: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 800e2e6: 683b ldr r3, [r7, #0] 800e2e8: 681b ldr r3, [r3, #0] 800e2ea: 2b10 cmp r3, #16 800e2ec: d11a bne.n 800e324 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 800e2ee: 4b13 ldr r3, [pc, #76] @ (800e33c ) 800e2f0: 681b ldr r3, [r3, #0] 800e2f2: 4a13 ldr r2, [pc, #76] @ (800e340 ) 800e2f4: fba2 2303 umull r2, r3, r2, r3 800e2f8: 0c9a lsrs r2, r3, #18 800e2fa: 4613 mov r3, r2 800e2fc: 009b lsls r3, r3, #2 800e2fe: 4413 add r3, r2 800e300: 005b lsls r3, r3, #1 800e302: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e304: e002 b.n 800e30c { wait_loop_index--; 800e306: 68bb ldr r3, [r7, #8] 800e308: 3b01 subs r3, #1 800e30a: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e30c: 68bb ldr r3, [r7, #8] 800e30e: 2b00 cmp r3, #0 800e310: d1f9 bne.n 800e306 800e312: e007 b.n 800e324 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800e314: 687b ldr r3, [r7, #4] 800e316: 6a9b ldr r3, [r3, #40] @ 0x28 800e318: f043 0220 orr.w r2, r3, #32 800e31c: 687b ldr r3, [r7, #4] 800e31e: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800e320: 2301 movs r3, #1 800e322: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 800e324: 687b ldr r3, [r7, #4] 800e326: 2200 movs r2, #0 800e328: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800e32c: 7bfb ldrb r3, [r7, #15] } 800e32e: 4618 mov r0, r3 800e330: 3714 adds r7, #20 800e332: 46bd mov sp, r7 800e334: bc80 pop {r7} 800e336: 4770 bx lr 800e338: 40012400 .word 0x40012400 800e33c: 2000006c .word 0x2000006c 800e340: 431bde83 .word 0x431bde83 0800e344 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 800e344: b580 push {r7, lr} 800e346: b084 sub sp, #16 800e348: af00 add r7, sp, #0 800e34a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800e34c: 2300 movs r3, #0 800e34e: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 800e350: 2300 movs r3, #0 800e352: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 800e354: 687b ldr r3, [r7, #4] 800e356: 681b ldr r3, [r3, #0] 800e358: 689b ldr r3, [r3, #8] 800e35a: f003 0301 and.w r3, r3, #1 800e35e: 2b01 cmp r3, #1 800e360: d040 beq.n 800e3e4 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 800e362: 687b ldr r3, [r7, #4] 800e364: 681b ldr r3, [r3, #0] 800e366: 689a ldr r2, [r3, #8] 800e368: 687b ldr r3, [r7, #4] 800e36a: 681b ldr r3, [r3, #0] 800e36c: f042 0201 orr.w r2, r2, #1 800e370: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 800e372: 4b1f ldr r3, [pc, #124] @ (800e3f0 ) 800e374: 681b ldr r3, [r3, #0] 800e376: 4a1f ldr r2, [pc, #124] @ (800e3f4 ) 800e378: fba2 2303 umull r2, r3, r2, r3 800e37c: 0c9b lsrs r3, r3, #18 800e37e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e380: e002 b.n 800e388 { wait_loop_index--; 800e382: 68bb ldr r3, [r7, #8] 800e384: 3b01 subs r3, #1 800e386: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e388: 68bb ldr r3, [r7, #8] 800e38a: 2b00 cmp r3, #0 800e38c: d1f9 bne.n 800e382 } /* Get tick count */ tickstart = HAL_GetTick(); 800e38e: f7ff fbef bl 800db70 800e392: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 800e394: e01f b.n 800e3d6 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 800e396: f7ff fbeb bl 800db70 800e39a: 4602 mov r2, r0 800e39c: 68fb ldr r3, [r7, #12] 800e39e: 1ad3 subs r3, r2, r3 800e3a0: 2b02 cmp r3, #2 800e3a2: d918 bls.n 800e3d6 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 800e3a4: 687b ldr r3, [r7, #4] 800e3a6: 681b ldr r3, [r3, #0] 800e3a8: 689b ldr r3, [r3, #8] 800e3aa: f003 0301 and.w r3, r3, #1 800e3ae: 2b01 cmp r3, #1 800e3b0: d011 beq.n 800e3d6 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800e3b2: 687b ldr r3, [r7, #4] 800e3b4: 6a9b ldr r3, [r3, #40] @ 0x28 800e3b6: f043 0210 orr.w r2, r3, #16 800e3ba: 687b ldr r3, [r7, #4] 800e3bc: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e3be: 687b ldr r3, [r7, #4] 800e3c0: 6adb ldr r3, [r3, #44] @ 0x2c 800e3c2: f043 0201 orr.w r2, r3, #1 800e3c6: 687b ldr r3, [r7, #4] 800e3c8: 62da str r2, [r3, #44] @ 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 800e3ca: 687b ldr r3, [r7, #4] 800e3cc: 2200 movs r2, #0 800e3ce: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e3d2: 2301 movs r3, #1 800e3d4: e007 b.n 800e3e6 while(ADC_IS_ENABLE(hadc) == RESET) 800e3d6: 687b ldr r3, [r7, #4] 800e3d8: 681b ldr r3, [r3, #0] 800e3da: 689b ldr r3, [r3, #8] 800e3dc: f003 0301 and.w r3, r3, #1 800e3e0: 2b01 cmp r3, #1 800e3e2: d1d8 bne.n 800e396 } } } /* Return HAL status */ return HAL_OK; 800e3e4: 2300 movs r3, #0 } 800e3e6: 4618 mov r0, r3 800e3e8: 3710 adds r7, #16 800e3ea: 46bd mov sp, r7 800e3ec: bd80 pop {r7, pc} 800e3ee: bf00 nop 800e3f0: 2000006c .word 0x2000006c 800e3f4: 431bde83 .word 0x431bde83 0800e3f8 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 800e3f8: b580 push {r7, lr} 800e3fa: b084 sub sp, #16 800e3fc: af00 add r7, sp, #0 800e3fe: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800e400: 2300 movs r3, #0 800e402: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 800e404: 687b ldr r3, [r7, #4] 800e406: 681b ldr r3, [r3, #0] 800e408: 689b ldr r3, [r3, #8] 800e40a: f003 0301 and.w r3, r3, #1 800e40e: 2b01 cmp r3, #1 800e410: d12e bne.n 800e470 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 800e412: 687b ldr r3, [r7, #4] 800e414: 681b ldr r3, [r3, #0] 800e416: 689a ldr r2, [r3, #8] 800e418: 687b ldr r3, [r7, #4] 800e41a: 681b ldr r3, [r3, #0] 800e41c: f022 0201 bic.w r2, r2, #1 800e420: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 800e422: f7ff fba5 bl 800db70 800e426: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 800e428: e01b b.n 800e462 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800e42a: f7ff fba1 bl 800db70 800e42e: 4602 mov r2, r0 800e430: 68fb ldr r3, [r7, #12] 800e432: 1ad3 subs r3, r2, r3 800e434: 2b02 cmp r3, #2 800e436: d914 bls.n 800e462 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 800e438: 687b ldr r3, [r7, #4] 800e43a: 681b ldr r3, [r3, #0] 800e43c: 689b ldr r3, [r3, #8] 800e43e: f003 0301 and.w r3, r3, #1 800e442: 2b01 cmp r3, #1 800e444: d10d bne.n 800e462 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800e446: 687b ldr r3, [r7, #4] 800e448: 6a9b ldr r3, [r3, #40] @ 0x28 800e44a: f043 0210 orr.w r2, r3, #16 800e44e: 687b ldr r3, [r7, #4] 800e450: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e452: 687b ldr r3, [r7, #4] 800e454: 6adb ldr r3, [r3, #44] @ 0x2c 800e456: f043 0201 orr.w r2, r3, #1 800e45a: 687b ldr r3, [r7, #4] 800e45c: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 800e45e: 2301 movs r3, #1 800e460: e007 b.n 800e472 while(ADC_IS_ENABLE(hadc) != RESET) 800e462: 687b ldr r3, [r7, #4] 800e464: 681b ldr r3, [r3, #0] 800e466: 689b ldr r3, [r3, #8] 800e468: f003 0301 and.w r3, r3, #1 800e46c: 2b01 cmp r3, #1 800e46e: d0dc beq.n 800e42a } } } /* Return HAL status */ return HAL_OK; 800e470: 2300 movs r3, #0 } 800e472: 4618 mov r0, r3 800e474: 3710 adds r7, #16 800e476: 46bd mov sp, r7 800e478: bd80 pop {r7, pc} ... 0800e47c : * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { 800e47c: b590 push {r4, r7, lr} 800e47e: b087 sub sp, #28 800e480: af00 add r7, sp, #0 800e482: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e484: 2300 movs r3, #0 800e486: 75fb strb r3, [r7, #23] uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; 800e488: 2300 movs r3, #0 800e48a: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800e48c: 687b ldr r3, [r7, #4] 800e48e: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e492: 2b01 cmp r3, #1 800e494: d101 bne.n 800e49a 800e496: 2302 movs r3, #2 800e498: e097 b.n 800e5ca 800e49a: 687b ldr r3, [r7, #4] 800e49c: 2201 movs r2, #1 800e49e: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* 1. Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800e4a2: 6878 ldr r0, [r7, #4] 800e4a4: f7ff ffa8 bl 800e3f8 800e4a8: 4603 mov r3, r0 800e4aa: 75fb strb r3, [r7, #23] /* 2. Calibration prerequisite delay before starting the calibration. */ /* - ADC must be enabled for at least two ADC clock cycles */ tmp_hal_status = ADC_Enable(hadc); 800e4ac: 6878 ldr r0, [r7, #4] 800e4ae: f7ff ff49 bl 800e344 800e4b2: 4603 mov r3, r0 800e4b4: 75fb strb r3, [r7, #23] /* Check if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800e4b6: 7dfb ldrb r3, [r7, #23] 800e4b8: 2b00 cmp r3, #0 800e4ba: f040 8081 bne.w 800e5c0 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e4be: 687b ldr r3, [r7, #4] 800e4c0: 6a9b ldr r3, [r3, #40] @ 0x28 800e4c2: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800e4c6: f023 0302 bic.w r3, r3, #2 800e4ca: f043 0202 orr.w r2, r3, #2 800e4ce: 687b ldr r3, [r7, #4] 800e4d0: 629a str r2, [r3, #40] @ 0x28 /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 800e4d2: 4b40 ldr r3, [pc, #256] @ (800e5d4 ) 800e4d4: 681c ldr r4, [r3, #0] 800e4d6: 2002 movs r0, #2 800e4d8: f002 fa8e bl 80109f8 800e4dc: 4603 mov r3, r0 800e4de: fbb4 f3f3 udiv r3, r4, r3 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 800e4e2: 005b lsls r3, r3, #1 wait_loop_index = ((SystemCoreClock 800e4e4: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800e4e6: e002 b.n 800e4ee { wait_loop_index--; 800e4e8: 68fb ldr r3, [r7, #12] 800e4ea: 3b01 subs r3, #1 800e4ec: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800e4ee: 68fb ldr r3, [r7, #12] 800e4f0: 2b00 cmp r3, #0 800e4f2: d1f9 bne.n 800e4e8 } /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 800e4f4: 687b ldr r3, [r7, #4] 800e4f6: 681b ldr r3, [r3, #0] 800e4f8: 689a ldr r2, [r3, #8] 800e4fa: 687b ldr r3, [r7, #4] 800e4fc: 681b ldr r3, [r3, #0] 800e4fe: f042 0208 orr.w r2, r2, #8 800e502: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800e504: f7ff fb34 bl 800db70 800e508: 6138 str r0, [r7, #16] /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800e50a: e01b b.n 800e544 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800e50c: f7ff fb30 bl 800db70 800e510: 4602 mov r2, r0 800e512: 693b ldr r3, [r7, #16] 800e514: 1ad3 subs r3, r2, r3 800e516: 2b0a cmp r3, #10 800e518: d914 bls.n 800e544 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800e51a: 687b ldr r3, [r7, #4] 800e51c: 681b ldr r3, [r3, #0] 800e51e: 689b ldr r3, [r3, #8] 800e520: f003 0308 and.w r3, r3, #8 800e524: 2b00 cmp r3, #0 800e526: d00d beq.n 800e544 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800e528: 687b ldr r3, [r7, #4] 800e52a: 6a9b ldr r3, [r3, #40] @ 0x28 800e52c: f023 0312 bic.w r3, r3, #18 800e530: f043 0210 orr.w r2, r3, #16 800e534: 687b ldr r3, [r7, #4] 800e536: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800e538: 687b ldr r3, [r7, #4] 800e53a: 2200 movs r2, #0 800e53c: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e540: 2301 movs r3, #1 800e542: e042 b.n 800e5ca while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800e544: 687b ldr r3, [r7, #4] 800e546: 681b ldr r3, [r3, #0] 800e548: 689b ldr r3, [r3, #8] 800e54a: f003 0308 and.w r3, r3, #8 800e54e: 2b00 cmp r3, #0 800e550: d1dc bne.n 800e50c } } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 800e552: 687b ldr r3, [r7, #4] 800e554: 681b ldr r3, [r3, #0] 800e556: 689a ldr r2, [r3, #8] 800e558: 687b ldr r3, [r7, #4] 800e55a: 681b ldr r3, [r3, #0] 800e55c: f042 0204 orr.w r2, r2, #4 800e560: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800e562: f7ff fb05 bl 800db70 800e566: 6138 str r0, [r7, #16] /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800e568: e01b b.n 800e5a2 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800e56a: f7ff fb01 bl 800db70 800e56e: 4602 mov r2, r0 800e570: 693b ldr r3, [r7, #16] 800e572: 1ad3 subs r3, r2, r3 800e574: 2b0a cmp r3, #10 800e576: d914 bls.n 800e5a2 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800e578: 687b ldr r3, [r7, #4] 800e57a: 681b ldr r3, [r3, #0] 800e57c: 689b ldr r3, [r3, #8] 800e57e: f003 0304 and.w r3, r3, #4 800e582: 2b00 cmp r3, #0 800e584: d00d beq.n 800e5a2 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800e586: 687b ldr r3, [r7, #4] 800e588: 6a9b ldr r3, [r3, #40] @ 0x28 800e58a: f023 0312 bic.w r3, r3, #18 800e58e: f043 0210 orr.w r2, r3, #16 800e592: 687b ldr r3, [r7, #4] 800e594: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800e596: 687b ldr r3, [r7, #4] 800e598: 2200 movs r2, #0 800e59a: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e59e: 2301 movs r3, #1 800e5a0: e013 b.n 800e5ca while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800e5a2: 687b ldr r3, [r7, #4] 800e5a4: 681b ldr r3, [r3, #0] 800e5a6: 689b ldr r3, [r3, #8] 800e5a8: f003 0304 and.w r3, r3, #4 800e5ac: 2b00 cmp r3, #0 800e5ae: d1dc bne.n 800e56a } } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e5b0: 687b ldr r3, [r7, #4] 800e5b2: 6a9b ldr r3, [r3, #40] @ 0x28 800e5b4: f023 0303 bic.w r3, r3, #3 800e5b8: f043 0201 orr.w r2, r3, #1 800e5bc: 687b ldr r3, [r7, #4] 800e5be: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 800e5c0: 687b ldr r3, [r7, #4] 800e5c2: 2200 movs r2, #0 800e5c4: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800e5c8: 7dfb ldrb r3, [r7, #23] } 800e5ca: 4618 mov r0, r3 800e5cc: 371c adds r7, #28 800e5ce: 46bd mov sp, r7 800e5d0: bd90 pop {r4, r7, pc} 800e5d2: bf00 nop 800e5d4: 2000006c .word 0x2000006c 0800e5d8 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { 800e5d8: b580 push {r7, lr} 800e5da: b084 sub sp, #16 800e5dc: af00 add r7, sp, #0 800e5de: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) 800e5e0: 687b ldr r3, [r7, #4] 800e5e2: 2b00 cmp r3, #0 800e5e4: d101 bne.n 800e5ea { return HAL_ERROR; 800e5e6: 2301 movs r3, #1 800e5e8: e0ed b.n 800e7c6 /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) 800e5ea: 687b ldr r3, [r7, #4] 800e5ec: f893 3020 ldrb.w r3, [r3, #32] 800e5f0: b2db uxtb r3, r3 800e5f2: 2b00 cmp r3, #0 800e5f4: d102 bne.n 800e5fc { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); 800e5f6: 6878 ldr r0, [r7, #4] 800e5f8: f7fb fad0 bl 8009b9c } #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800e5fc: 687b ldr r3, [r7, #4] 800e5fe: 681b ldr r3, [r3, #0] 800e600: 681a ldr r2, [r3, #0] 800e602: 687b ldr r3, [r7, #4] 800e604: 681b ldr r3, [r3, #0] 800e606: f042 0201 orr.w r2, r2, #1 800e60a: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800e60c: f7ff fab0 bl 800db70 800e610: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800e612: e012 b.n 800e63a { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800e614: f7ff faac bl 800db70 800e618: 4602 mov r2, r0 800e61a: 68fb ldr r3, [r7, #12] 800e61c: 1ad3 subs r3, r2, r3 800e61e: 2b0a cmp r3, #10 800e620: d90b bls.n 800e63a { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800e622: 687b ldr r3, [r7, #4] 800e624: 6a5b ldr r3, [r3, #36] @ 0x24 800e626: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800e62a: 687b ldr r3, [r7, #4] 800e62c: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800e62e: 687b ldr r3, [r7, #4] 800e630: 2205 movs r2, #5 800e632: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800e636: 2301 movs r3, #1 800e638: e0c5 b.n 800e7c6 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800e63a: 687b ldr r3, [r7, #4] 800e63c: 681b ldr r3, [r3, #0] 800e63e: 685b ldr r3, [r3, #4] 800e640: f003 0301 and.w r3, r3, #1 800e644: 2b00 cmp r3, #0 800e646: d0e5 beq.n 800e614 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800e648: 687b ldr r3, [r7, #4] 800e64a: 681b ldr r3, [r3, #0] 800e64c: 681a ldr r2, [r3, #0] 800e64e: 687b ldr r3, [r7, #4] 800e650: 681b ldr r3, [r3, #0] 800e652: f022 0202 bic.w r2, r2, #2 800e656: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800e658: f7ff fa8a bl 800db70 800e65c: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800e65e: e012 b.n 800e686 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800e660: f7ff fa86 bl 800db70 800e664: 4602 mov r2, r0 800e666: 68fb ldr r3, [r7, #12] 800e668: 1ad3 subs r3, r2, r3 800e66a: 2b0a cmp r3, #10 800e66c: d90b bls.n 800e686 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800e66e: 687b ldr r3, [r7, #4] 800e670: 6a5b ldr r3, [r3, #36] @ 0x24 800e672: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800e676: 687b ldr r3, [r7, #4] 800e678: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800e67a: 687b ldr r3, [r7, #4] 800e67c: 2205 movs r2, #5 800e67e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800e682: 2301 movs r3, #1 800e684: e09f b.n 800e7c6 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800e686: 687b ldr r3, [r7, #4] 800e688: 681b ldr r3, [r3, #0] 800e68a: 685b ldr r3, [r3, #4] 800e68c: f003 0302 and.w r3, r3, #2 800e690: 2b00 cmp r3, #0 800e692: d1e5 bne.n 800e660 } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) 800e694: 687b ldr r3, [r7, #4] 800e696: 7e1b ldrb r3, [r3, #24] 800e698: 2b01 cmp r3, #1 800e69a: d108 bne.n 800e6ae { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800e69c: 687b ldr r3, [r7, #4] 800e69e: 681b ldr r3, [r3, #0] 800e6a0: 681a ldr r2, [r3, #0] 800e6a2: 687b ldr r3, [r7, #4] 800e6a4: 681b ldr r3, [r3, #0] 800e6a6: f042 0280 orr.w r2, r2, #128 @ 0x80 800e6aa: 601a str r2, [r3, #0] 800e6ac: e007 b.n 800e6be } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800e6ae: 687b ldr r3, [r7, #4] 800e6b0: 681b ldr r3, [r3, #0] 800e6b2: 681a ldr r2, [r3, #0] 800e6b4: 687b ldr r3, [r7, #4] 800e6b6: 681b ldr r3, [r3, #0] 800e6b8: f022 0280 bic.w r2, r2, #128 @ 0x80 800e6bc: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) 800e6be: 687b ldr r3, [r7, #4] 800e6c0: 7e5b ldrb r3, [r3, #25] 800e6c2: 2b01 cmp r3, #1 800e6c4: d108 bne.n 800e6d8 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800e6c6: 687b ldr r3, [r7, #4] 800e6c8: 681b ldr r3, [r3, #0] 800e6ca: 681a ldr r2, [r3, #0] 800e6cc: 687b ldr r3, [r7, #4] 800e6ce: 681b ldr r3, [r3, #0] 800e6d0: f042 0240 orr.w r2, r2, #64 @ 0x40 800e6d4: 601a str r2, [r3, #0] 800e6d6: e007 b.n 800e6e8 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800e6d8: 687b ldr r3, [r7, #4] 800e6da: 681b ldr r3, [r3, #0] 800e6dc: 681a ldr r2, [r3, #0] 800e6de: 687b ldr r3, [r7, #4] 800e6e0: 681b ldr r3, [r3, #0] 800e6e2: f022 0240 bic.w r2, r2, #64 @ 0x40 800e6e6: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) 800e6e8: 687b ldr r3, [r7, #4] 800e6ea: 7e9b ldrb r3, [r3, #26] 800e6ec: 2b01 cmp r3, #1 800e6ee: d108 bne.n 800e702 { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800e6f0: 687b ldr r3, [r7, #4] 800e6f2: 681b ldr r3, [r3, #0] 800e6f4: 681a ldr r2, [r3, #0] 800e6f6: 687b ldr r3, [r7, #4] 800e6f8: 681b ldr r3, [r3, #0] 800e6fa: f042 0220 orr.w r2, r2, #32 800e6fe: 601a str r2, [r3, #0] 800e700: e007 b.n 800e712 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800e702: 687b ldr r3, [r7, #4] 800e704: 681b ldr r3, [r3, #0] 800e706: 681a ldr r2, [r3, #0] 800e708: 687b ldr r3, [r7, #4] 800e70a: 681b ldr r3, [r3, #0] 800e70c: f022 0220 bic.w r2, r2, #32 800e710: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) 800e712: 687b ldr r3, [r7, #4] 800e714: 7edb ldrb r3, [r3, #27] 800e716: 2b01 cmp r3, #1 800e718: d108 bne.n 800e72c { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800e71a: 687b ldr r3, [r7, #4] 800e71c: 681b ldr r3, [r3, #0] 800e71e: 681a ldr r2, [r3, #0] 800e720: 687b ldr r3, [r7, #4] 800e722: 681b ldr r3, [r3, #0] 800e724: f022 0210 bic.w r2, r2, #16 800e728: 601a str r2, [r3, #0] 800e72a: e007 b.n 800e73c } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800e72c: 687b ldr r3, [r7, #4] 800e72e: 681b ldr r3, [r3, #0] 800e730: 681a ldr r2, [r3, #0] 800e732: 687b ldr r3, [r7, #4] 800e734: 681b ldr r3, [r3, #0] 800e736: f042 0210 orr.w r2, r2, #16 800e73a: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) 800e73c: 687b ldr r3, [r7, #4] 800e73e: 7f1b ldrb r3, [r3, #28] 800e740: 2b01 cmp r3, #1 800e742: d108 bne.n 800e756 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800e744: 687b ldr r3, [r7, #4] 800e746: 681b ldr r3, [r3, #0] 800e748: 681a ldr r2, [r3, #0] 800e74a: 687b ldr r3, [r7, #4] 800e74c: 681b ldr r3, [r3, #0] 800e74e: f042 0208 orr.w r2, r2, #8 800e752: 601a str r2, [r3, #0] 800e754: e007 b.n 800e766 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800e756: 687b ldr r3, [r7, #4] 800e758: 681b ldr r3, [r3, #0] 800e75a: 681a ldr r2, [r3, #0] 800e75c: 687b ldr r3, [r7, #4] 800e75e: 681b ldr r3, [r3, #0] 800e760: f022 0208 bic.w r2, r2, #8 800e764: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) 800e766: 687b ldr r3, [r7, #4] 800e768: 7f5b ldrb r3, [r3, #29] 800e76a: 2b01 cmp r3, #1 800e76c: d108 bne.n 800e780 { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800e76e: 687b ldr r3, [r7, #4] 800e770: 681b ldr r3, [r3, #0] 800e772: 681a ldr r2, [r3, #0] 800e774: 687b ldr r3, [r7, #4] 800e776: 681b ldr r3, [r3, #0] 800e778: f042 0204 orr.w r2, r2, #4 800e77c: 601a str r2, [r3, #0] 800e77e: e007 b.n 800e790 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800e780: 687b ldr r3, [r7, #4] 800e782: 681b ldr r3, [r3, #0] 800e784: 681a ldr r2, [r3, #0] 800e786: 687b ldr r3, [r7, #4] 800e788: 681b ldr r3, [r3, #0] 800e78a: f022 0204 bic.w r2, r2, #4 800e78e: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | 800e790: 687b ldr r3, [r7, #4] 800e792: 689a ldr r2, [r3, #8] 800e794: 687b ldr r3, [r7, #4] 800e796: 68db ldr r3, [r3, #12] 800e798: 431a orrs r2, r3 800e79a: 687b ldr r3, [r7, #4] 800e79c: 691b ldr r3, [r3, #16] 800e79e: 431a orrs r2, r3 800e7a0: 687b ldr r3, [r7, #4] 800e7a2: 695b ldr r3, [r3, #20] 800e7a4: ea42 0103 orr.w r1, r2, r3 800e7a8: 687b ldr r3, [r7, #4] 800e7aa: 685b ldr r3, [r3, #4] 800e7ac: 1e5a subs r2, r3, #1 800e7ae: 687b ldr r3, [r7, #4] 800e7b0: 681b ldr r3, [r3, #0] 800e7b2: 430a orrs r2, r1 800e7b4: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800e7b6: 687b ldr r3, [r7, #4] 800e7b8: 2200 movs r2, #0 800e7ba: 625a str r2, [r3, #36] @ 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; 800e7bc: 687b ldr r3, [r7, #4] 800e7be: 2201 movs r2, #1 800e7c0: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800e7c4: 2300 movs r3, #0 } 800e7c6: 4618 mov r0, r3 800e7c8: 3710 adds r7, #16 800e7ca: 46bd mov sp, r7 800e7cc: bd80 pop {r7, pc} ... 0800e7d0 : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { 800e7d0: b480 push {r7} 800e7d2: b087 sub sp, #28 800e7d4: af00 add r7, sp, #0 800e7d6: 6078 str r0, [r7, #4] 800e7d8: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; 800e7da: 687b ldr r3, [r7, #4] 800e7dc: 681b ldr r3, [r3, #0] 800e7de: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; 800e7e0: 687b ldr r3, [r7, #4] 800e7e2: f893 3020 ldrb.w r3, [r3, #32] 800e7e6: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || 800e7e8: 7cfb ldrb r3, [r7, #19] 800e7ea: 2b01 cmp r3, #1 800e7ec: d003 beq.n 800e7f6 800e7ee: 7cfb ldrb r3, [r7, #19] 800e7f0: 2b02 cmp r3, #2 800e7f2: f040 80be bne.w 800e972 assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); #if defined(CAN2) /* CAN1 and CAN2 are dual instances with 28 common filters banks */ /* Select master instance to access the filter banks */ can_ip = CAN1; 800e7f6: 4b65 ldr r3, [pc, #404] @ (800e98c ) 800e7f8: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); #endif /* CAN3 */ /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); 800e7fa: 697b ldr r3, [r7, #20] 800e7fc: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800e800: f043 0201 orr.w r2, r3, #1 800e804: 697b ldr r3, [r7, #20] 800e806: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #if defined(CAN2) /* Select the start filter number of CAN2 slave instance */ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); 800e80a: 697b ldr r3, [r7, #20] 800e80c: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800e810: f423 527c bic.w r2, r3, #16128 @ 0x3f00 800e814: 697b ldr r3, [r7, #20] 800e816: f8c3 2200 str.w r2, [r3, #512] @ 0x200 SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); 800e81a: 697b ldr r3, [r7, #20] 800e81c: f8d3 2200 ldr.w r2, [r3, #512] @ 0x200 800e820: 683b ldr r3, [r7, #0] 800e822: 6a5b ldr r3, [r3, #36] @ 0x24 800e824: 021b lsls r3, r3, #8 800e826: 431a orrs r2, r3 800e828: 697b ldr r3, [r7, #20] 800e82a: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #endif /* CAN3 */ /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); 800e82e: 683b ldr r3, [r7, #0] 800e830: 695b ldr r3, [r3, #20] 800e832: f003 031f and.w r3, r3, #31 800e836: 2201 movs r2, #1 800e838: fa02 f303 lsl.w r3, r2, r3 800e83c: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); 800e83e: 697b ldr r3, [r7, #20] 800e840: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800e844: 68fb ldr r3, [r7, #12] 800e846: 43db mvns r3, r3 800e848: 401a ands r2, r3 800e84a: 697b ldr r3, [r7, #20] 800e84c: f8c3 221c str.w r2, [r3, #540] @ 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) 800e850: 683b ldr r3, [r7, #0] 800e852: 69db ldr r3, [r3, #28] 800e854: 2b00 cmp r3, #0 800e856: d123 bne.n 800e8a0 { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); 800e858: 697b ldr r3, [r7, #20] 800e85a: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800e85e: 68fb ldr r3, [r7, #12] 800e860: 43db mvns r3, r3 800e862: 401a ands r2, r3 800e864: 697b ldr r3, [r7, #20] 800e866: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800e86a: 683b ldr r3, [r7, #0] 800e86c: 68db ldr r3, [r3, #12] 800e86e: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800e870: 683b ldr r3, [r7, #0] 800e872: 685b ldr r3, [r3, #4] 800e874: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800e876: 683a ldr r2, [r7, #0] 800e878: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800e87a: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800e87c: 697b ldr r3, [r7, #20] 800e87e: 3248 adds r2, #72 @ 0x48 800e880: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800e884: 683b ldr r3, [r7, #0] 800e886: 689b ldr r3, [r3, #8] 800e888: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); 800e88a: 683b ldr r3, [r7, #0] 800e88c: 681b ldr r3, [r3, #0] 800e88e: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800e890: 683b ldr r3, [r7, #0] 800e892: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800e894: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800e896: 6979 ldr r1, [r7, #20] 800e898: 3348 adds r3, #72 @ 0x48 800e89a: 00db lsls r3, r3, #3 800e89c: 440b add r3, r1 800e89e: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) 800e8a0: 683b ldr r3, [r7, #0] 800e8a2: 69db ldr r3, [r3, #28] 800e8a4: 2b01 cmp r3, #1 800e8a6: d122 bne.n 800e8ee { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); 800e8a8: 697b ldr r3, [r7, #20] 800e8aa: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800e8ae: 68fb ldr r3, [r7, #12] 800e8b0: 431a orrs r2, r3 800e8b2: 697b ldr r3, [r7, #20] 800e8b4: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800e8b8: 683b ldr r3, [r7, #0] 800e8ba: 681b ldr r3, [r3, #0] 800e8bc: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800e8be: 683b ldr r3, [r7, #0] 800e8c0: 685b ldr r3, [r3, #4] 800e8c2: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800e8c4: 683a ldr r2, [r7, #0] 800e8c6: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800e8c8: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800e8ca: 697b ldr r3, [r7, #20] 800e8cc: 3248 adds r2, #72 @ 0x48 800e8ce: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800e8d2: 683b ldr r3, [r7, #0] 800e8d4: 689b ldr r3, [r3, #8] 800e8d6: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); 800e8d8: 683b ldr r3, [r7, #0] 800e8da: 68db ldr r3, [r3, #12] 800e8dc: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800e8de: 683b ldr r3, [r7, #0] 800e8e0: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800e8e2: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800e8e4: 6979 ldr r1, [r7, #20] 800e8e6: 3348 adds r3, #72 @ 0x48 800e8e8: 00db lsls r3, r3, #3 800e8ea: 440b add r3, r1 800e8ec: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) 800e8ee: 683b ldr r3, [r7, #0] 800e8f0: 699b ldr r3, [r3, #24] 800e8f2: 2b00 cmp r3, #0 800e8f4: d109 bne.n 800e90a { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); 800e8f6: 697b ldr r3, [r7, #20] 800e8f8: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800e8fc: 68fb ldr r3, [r7, #12] 800e8fe: 43db mvns r3, r3 800e900: 401a ands r2, r3 800e902: 697b ldr r3, [r7, #20] 800e904: f8c3 2204 str.w r2, [r3, #516] @ 0x204 800e908: e007 b.n 800e91a } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); 800e90a: 697b ldr r3, [r7, #20] 800e90c: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800e910: 68fb ldr r3, [r7, #12] 800e912: 431a orrs r2, r3 800e914: 697b ldr r3, [r7, #20] 800e916: f8c3 2204 str.w r2, [r3, #516] @ 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) 800e91a: 683b ldr r3, [r7, #0] 800e91c: 691b ldr r3, [r3, #16] 800e91e: 2b00 cmp r3, #0 800e920: d109 bne.n 800e936 { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); 800e922: 697b ldr r3, [r7, #20] 800e924: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800e928: 68fb ldr r3, [r7, #12] 800e92a: 43db mvns r3, r3 800e92c: 401a ands r2, r3 800e92e: 697b ldr r3, [r7, #20] 800e930: f8c3 2214 str.w r2, [r3, #532] @ 0x214 800e934: e007 b.n 800e946 } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); 800e936: 697b ldr r3, [r7, #20] 800e938: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800e93c: 68fb ldr r3, [r7, #12] 800e93e: 431a orrs r2, r3 800e940: 697b ldr r3, [r7, #20] 800e942: f8c3 2214 str.w r2, [r3, #532] @ 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) 800e946: 683b ldr r3, [r7, #0] 800e948: 6a1b ldr r3, [r3, #32] 800e94a: 2b01 cmp r3, #1 800e94c: d107 bne.n 800e95e { SET_BIT(can_ip->FA1R, filternbrbitpos); 800e94e: 697b ldr r3, [r7, #20] 800e950: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800e954: 68fb ldr r3, [r7, #12] 800e956: 431a orrs r2, r3 800e958: 697b ldr r3, [r7, #20] 800e95a: f8c3 221c str.w r2, [r3, #540] @ 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); 800e95e: 697b ldr r3, [r7, #20] 800e960: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800e964: f023 0201 bic.w r2, r3, #1 800e968: 697b ldr r3, [r7, #20] 800e96a: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Return function status */ return HAL_OK; 800e96e: 2300 movs r3, #0 800e970: e006 b.n 800e980 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800e972: 687b ldr r3, [r7, #4] 800e974: 6a5b ldr r3, [r3, #36] @ 0x24 800e976: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800e97a: 687b ldr r3, [r7, #4] 800e97c: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e97e: 2301 movs r3, #1 } } 800e980: 4618 mov r0, r3 800e982: 371c adds r7, #28 800e984: 46bd mov sp, r7 800e986: bc80 pop {r7} 800e988: 4770 bx lr 800e98a: bf00 nop 800e98c: 40006400 .word 0x40006400 0800e990 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { 800e990: b580 push {r7, lr} 800e992: b084 sub sp, #16 800e994: af00 add r7, sp, #0 800e996: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) 800e998: 687b ldr r3, [r7, #4] 800e99a: f893 3020 ldrb.w r3, [r3, #32] 800e99e: b2db uxtb r3, r3 800e9a0: 2b01 cmp r3, #1 800e9a2: d12e bne.n 800ea02 { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; 800e9a4: 687b ldr r3, [r7, #4] 800e9a6: 2202 movs r2, #2 800e9a8: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800e9ac: 687b ldr r3, [r7, #4] 800e9ae: 681b ldr r3, [r3, #0] 800e9b0: 681a ldr r2, [r3, #0] 800e9b2: 687b ldr r3, [r7, #4] 800e9b4: 681b ldr r3, [r3, #0] 800e9b6: f022 0201 bic.w r2, r2, #1 800e9ba: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800e9bc: f7ff f8d8 bl 800db70 800e9c0: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800e9c2: e012 b.n 800e9ea { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800e9c4: f7ff f8d4 bl 800db70 800e9c8: 4602 mov r2, r0 800e9ca: 68fb ldr r3, [r7, #12] 800e9cc: 1ad3 subs r3, r2, r3 800e9ce: 2b0a cmp r3, #10 800e9d0: d90b bls.n 800e9ea { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800e9d2: 687b ldr r3, [r7, #4] 800e9d4: 6a5b ldr r3, [r3, #36] @ 0x24 800e9d6: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800e9da: 687b ldr r3, [r7, #4] 800e9dc: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800e9de: 687b ldr r3, [r7, #4] 800e9e0: 2205 movs r2, #5 800e9e2: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800e9e6: 2301 movs r3, #1 800e9e8: e012 b.n 800ea10 while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800e9ea: 687b ldr r3, [r7, #4] 800e9ec: 681b ldr r3, [r3, #0] 800e9ee: 685b ldr r3, [r3, #4] 800e9f0: f003 0301 and.w r3, r3, #1 800e9f4: 2b00 cmp r3, #0 800e9f6: d1e5 bne.n 800e9c4 } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800e9f8: 687b ldr r3, [r7, #4] 800e9fa: 2200 movs r2, #0 800e9fc: 625a str r2, [r3, #36] @ 0x24 /* Return function status */ return HAL_OK; 800e9fe: 2300 movs r3, #0 800ea00: e006 b.n 800ea10 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; 800ea02: 687b ldr r3, [r7, #4] 800ea04: 6a5b ldr r3, [r3, #36] @ 0x24 800ea06: f443 2200 orr.w r2, r3, #524288 @ 0x80000 800ea0a: 687b ldr r3, [r7, #4] 800ea0c: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ea0e: 2301 movs r3, #1 } } 800ea10: 4618 mov r0, r3 800ea12: 3710 adds r7, #16 800ea14: 46bd mov sp, r7 800ea16: bd80 pop {r7, pc} 0800ea18 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { 800ea18: b580 push {r7, lr} 800ea1a: b084 sub sp, #16 800ea1c: af00 add r7, sp, #0 800ea1e: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_LISTENING) 800ea20: 687b ldr r3, [r7, #4] 800ea22: f893 3020 ldrb.w r3, [r3, #32] 800ea26: b2db uxtb r3, r3 800ea28: 2b02 cmp r3, #2 800ea2a: d133 bne.n 800ea94 { /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800ea2c: 687b ldr r3, [r7, #4] 800ea2e: 681b ldr r3, [r3, #0] 800ea30: 681a ldr r2, [r3, #0] 800ea32: 687b ldr r3, [r7, #4] 800ea34: 681b ldr r3, [r3, #0] 800ea36: f042 0201 orr.w r2, r2, #1 800ea3a: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800ea3c: f7ff f898 bl 800db70 800ea40: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800ea42: e012 b.n 800ea6a { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800ea44: f7ff f894 bl 800db70 800ea48: 4602 mov r2, r0 800ea4a: 68fb ldr r3, [r7, #12] 800ea4c: 1ad3 subs r3, r2, r3 800ea4e: 2b0a cmp r3, #10 800ea50: d90b bls.n 800ea6a { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800ea52: 687b ldr r3, [r7, #4] 800ea54: 6a5b ldr r3, [r3, #36] @ 0x24 800ea56: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800ea5a: 687b ldr r3, [r7, #4] 800ea5c: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800ea5e: 687b ldr r3, [r7, #4] 800ea60: 2205 movs r2, #5 800ea62: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800ea66: 2301 movs r3, #1 800ea68: e01b b.n 800eaa2 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800ea6a: 687b ldr r3, [r7, #4] 800ea6c: 681b ldr r3, [r3, #0] 800ea6e: 685b ldr r3, [r3, #4] 800ea70: f003 0301 and.w r3, r3, #1 800ea74: 2b00 cmp r3, #0 800ea76: d0e5 beq.n 800ea44 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800ea78: 687b ldr r3, [r7, #4] 800ea7a: 681b ldr r3, [r3, #0] 800ea7c: 681a ldr r2, [r3, #0] 800ea7e: 687b ldr r3, [r7, #4] 800ea80: 681b ldr r3, [r3, #0] 800ea82: f022 0202 bic.w r2, r2, #2 800ea86: 601a str r2, [r3, #0] /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_READY; 800ea88: 687b ldr r3, [r7, #4] 800ea8a: 2201 movs r2, #1 800ea8c: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800ea90: 2300 movs r3, #0 800ea92: e006 b.n 800eaa2 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; 800ea94: 687b ldr r3, [r7, #4] 800ea96: 6a5b ldr r3, [r3, #36] @ 0x24 800ea98: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800ea9c: 687b ldr r3, [r7, #4] 800ea9e: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800eaa0: 2301 movs r3, #1 } } 800eaa2: 4618 mov r0, r3 800eaa4: 3710 adds r7, #16 800eaa6: 46bd mov sp, r7 800eaa8: bd80 pop {r7, pc} 0800eaaa : * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, const uint8_t aData[], uint32_t *pTxMailbox) { 800eaaa: b480 push {r7} 800eaac: b089 sub sp, #36 @ 0x24 800eaae: af00 add r7, sp, #0 800eab0: 60f8 str r0, [r7, #12] 800eab2: 60b9 str r1, [r7, #8] 800eab4: 607a str r2, [r7, #4] 800eab6: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; 800eab8: 68fb ldr r3, [r7, #12] 800eaba: f893 3020 ldrb.w r3, [r3, #32] 800eabe: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); 800eac0: 68fb ldr r3, [r7, #12] 800eac2: 681b ldr r3, [r3, #0] 800eac4: 689b ldr r3, [r3, #8] 800eac6: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || 800eac8: 7ffb ldrb r3, [r7, #31] 800eaca: 2b01 cmp r3, #1 800eacc: d003 beq.n 800ead6 800eace: 7ffb ldrb r3, [r7, #31] 800ead0: 2b02 cmp r3, #2 800ead2: f040 80ad bne.w 800ec30 (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || 800ead6: 69bb ldr r3, [r7, #24] 800ead8: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800eadc: 2b00 cmp r3, #0 800eade: d10a bne.n 800eaf6 ((tsr & CAN_TSR_TME1) != 0U) || 800eae0: 69bb ldr r3, [r7, #24] 800eae2: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || 800eae6: 2b00 cmp r3, #0 800eae8: d105 bne.n 800eaf6 ((tsr & CAN_TSR_TME2) != 0U)) 800eaea: 69bb ldr r3, [r7, #24] 800eaec: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || 800eaf0: 2b00 cmp r3, #0 800eaf2: f000 8095 beq.w 800ec20 { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; 800eaf6: 69bb ldr r3, [r7, #24] 800eaf8: 0e1b lsrs r3, r3, #24 800eafa: f003 0303 and.w r3, r3, #3 800eafe: 617b str r3, [r7, #20] /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; 800eb00: 2201 movs r2, #1 800eb02: 697b ldr r3, [r7, #20] 800eb04: 409a lsls r2, r3 800eb06: 683b ldr r3, [r7, #0] 800eb08: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) 800eb0a: 68bb ldr r3, [r7, #8] 800eb0c: 689b ldr r3, [r3, #8] 800eb0e: 2b00 cmp r3, #0 800eb10: d10d bne.n 800eb2e { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800eb12: 68bb ldr r3, [r7, #8] 800eb14: 681b ldr r3, [r3, #0] 800eb16: 055a lsls r2, r3, #21 pHeader->RTR); 800eb18: 68bb ldr r3, [r7, #8] 800eb1a: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800eb1c: 68f9 ldr r1, [r7, #12] 800eb1e: 6809 ldr r1, [r1, #0] 800eb20: 431a orrs r2, r3 800eb22: 697b ldr r3, [r7, #20] 800eb24: 3318 adds r3, #24 800eb26: 011b lsls r3, r3, #4 800eb28: 440b add r3, r1 800eb2a: 601a str r2, [r3, #0] 800eb2c: e00f b.n 800eb4e } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800eb2e: 68bb ldr r3, [r7, #8] 800eb30: 685b ldr r3, [r3, #4] 800eb32: 00da lsls r2, r3, #3 pHeader->IDE | 800eb34: 68bb ldr r3, [r7, #8] 800eb36: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800eb38: 431a orrs r2, r3 pHeader->RTR); 800eb3a: 68bb ldr r3, [r7, #8] 800eb3c: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800eb3e: 68f9 ldr r1, [r7, #12] 800eb40: 6809 ldr r1, [r1, #0] pHeader->IDE | 800eb42: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800eb44: 697b ldr r3, [r7, #20] 800eb46: 3318 adds r3, #24 800eb48: 011b lsls r3, r3, #4 800eb4a: 440b add r3, r1 800eb4c: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); 800eb4e: 68fb ldr r3, [r7, #12] 800eb50: 6819 ldr r1, [r3, #0] 800eb52: 68bb ldr r3, [r7, #8] 800eb54: 691a ldr r2, [r3, #16] 800eb56: 697b ldr r3, [r7, #20] 800eb58: 3318 adds r3, #24 800eb5a: 011b lsls r3, r3, #4 800eb5c: 440b add r3, r1 800eb5e: 3304 adds r3, #4 800eb60: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) 800eb62: 68bb ldr r3, [r7, #8] 800eb64: 7d1b ldrb r3, [r3, #20] 800eb66: 2b01 cmp r3, #1 800eb68: d111 bne.n 800eb8e { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); 800eb6a: 68fb ldr r3, [r7, #12] 800eb6c: 681a ldr r2, [r3, #0] 800eb6e: 697b ldr r3, [r7, #20] 800eb70: 3318 adds r3, #24 800eb72: 011b lsls r3, r3, #4 800eb74: 4413 add r3, r2 800eb76: 3304 adds r3, #4 800eb78: 681b ldr r3, [r3, #0] 800eb7a: 68fa ldr r2, [r7, #12] 800eb7c: 6811 ldr r1, [r2, #0] 800eb7e: f443 7280 orr.w r2, r3, #256 @ 0x100 800eb82: 697b ldr r3, [r7, #20] 800eb84: 3318 adds r3, #24 800eb86: 011b lsls r3, r3, #4 800eb88: 440b add r3, r1 800eb8a: 3304 adds r3, #4 800eb8c: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, 800eb8e: 687b ldr r3, [r7, #4] 800eb90: 3307 adds r3, #7 800eb92: 781b ldrb r3, [r3, #0] 800eb94: 061a lsls r2, r3, #24 800eb96: 687b ldr r3, [r7, #4] 800eb98: 3306 adds r3, #6 800eb9a: 781b ldrb r3, [r3, #0] 800eb9c: 041b lsls r3, r3, #16 800eb9e: 431a orrs r2, r3 800eba0: 687b ldr r3, [r7, #4] 800eba2: 3305 adds r3, #5 800eba4: 781b ldrb r3, [r3, #0] 800eba6: 021b lsls r3, r3, #8 800eba8: 4313 orrs r3, r2 800ebaa: 687a ldr r2, [r7, #4] 800ebac: 3204 adds r2, #4 800ebae: 7812 ldrb r2, [r2, #0] 800ebb0: 4610 mov r0, r2 800ebb2: 68fa ldr r2, [r7, #12] 800ebb4: 6811 ldr r1, [r2, #0] 800ebb6: ea43 0200 orr.w r2, r3, r0 800ebba: 697b ldr r3, [r7, #20] 800ebbc: 011b lsls r3, r3, #4 800ebbe: 440b add r3, r1 800ebc0: f503 73c6 add.w r3, r3, #396 @ 0x18c 800ebc4: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, 800ebc6: 687b ldr r3, [r7, #4] 800ebc8: 3303 adds r3, #3 800ebca: 781b ldrb r3, [r3, #0] 800ebcc: 061a lsls r2, r3, #24 800ebce: 687b ldr r3, [r7, #4] 800ebd0: 3302 adds r3, #2 800ebd2: 781b ldrb r3, [r3, #0] 800ebd4: 041b lsls r3, r3, #16 800ebd6: 431a orrs r2, r3 800ebd8: 687b ldr r3, [r7, #4] 800ebda: 3301 adds r3, #1 800ebdc: 781b ldrb r3, [r3, #0] 800ebde: 021b lsls r3, r3, #8 800ebe0: 4313 orrs r3, r2 800ebe2: 687a ldr r2, [r7, #4] 800ebe4: 7812 ldrb r2, [r2, #0] 800ebe6: 4610 mov r0, r2 800ebe8: 68fa ldr r2, [r7, #12] 800ebea: 6811 ldr r1, [r2, #0] 800ebec: ea43 0200 orr.w r2, r3, r0 800ebf0: 697b ldr r3, [r7, #20] 800ebf2: 011b lsls r3, r3, #4 800ebf4: 440b add r3, r1 800ebf6: f503 73c4 add.w r3, r3, #392 @ 0x188 800ebfa: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); 800ebfc: 68fb ldr r3, [r7, #12] 800ebfe: 681a ldr r2, [r3, #0] 800ec00: 697b ldr r3, [r7, #20] 800ec02: 3318 adds r3, #24 800ec04: 011b lsls r3, r3, #4 800ec06: 4413 add r3, r2 800ec08: 681b ldr r3, [r3, #0] 800ec0a: 68fa ldr r2, [r7, #12] 800ec0c: 6811 ldr r1, [r2, #0] 800ec0e: f043 0201 orr.w r2, r3, #1 800ec12: 697b ldr r3, [r7, #20] 800ec14: 3318 adds r3, #24 800ec16: 011b lsls r3, r3, #4 800ec18: 440b add r3, r1 800ec1a: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800ec1c: 2300 movs r3, #0 800ec1e: e00e b.n 800ec3e } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800ec20: 68fb ldr r3, [r7, #12] 800ec22: 6a5b ldr r3, [r3, #36] @ 0x24 800ec24: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800ec28: 68fb ldr r3, [r7, #12] 800ec2a: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ec2c: 2301 movs r3, #1 800ec2e: e006 b.n 800ec3e } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800ec30: 68fb ldr r3, [r7, #12] 800ec32: 6a5b ldr r3, [r3, #36] @ 0x24 800ec34: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800ec38: 68fb ldr r3, [r7, #12] 800ec3a: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ec3c: 2301 movs r3, #1 } } 800ec3e: 4618 mov r0, r3 800ec40: 3724 adds r7, #36 @ 0x24 800ec42: 46bd mov sp, r7 800ec44: bc80 pop {r7} 800ec46: 4770 bx lr 0800ec48 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval Number of free Tx Mailboxes. */ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) { 800ec48: b480 push {r7} 800ec4a: b085 sub sp, #20 800ec4c: af00 add r7, sp, #0 800ec4e: 6078 str r0, [r7, #4] uint32_t freelevel = 0U; 800ec50: 2300 movs r3, #0 800ec52: 60fb str r3, [r7, #12] HAL_CAN_StateTypeDef state = hcan->State; 800ec54: 687b ldr r3, [r7, #4] 800ec56: f893 3020 ldrb.w r3, [r3, #32] 800ec5a: 72fb strb r3, [r7, #11] if ((state == HAL_CAN_STATE_READY) || 800ec5c: 7afb ldrb r3, [r7, #11] 800ec5e: 2b01 cmp r3, #1 800ec60: d002 beq.n 800ec68 800ec62: 7afb ldrb r3, [r7, #11] 800ec64: 2b02 cmp r3, #2 800ec66: d11d bne.n 800eca4 (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 status */ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) 800ec68: 687b ldr r3, [r7, #4] 800ec6a: 681b ldr r3, [r3, #0] 800ec6c: 689b ldr r3, [r3, #8] 800ec6e: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800ec72: 2b00 cmp r3, #0 800ec74: d002 beq.n 800ec7c { freelevel++; 800ec76: 68fb ldr r3, [r7, #12] 800ec78: 3301 adds r3, #1 800ec7a: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 1 status */ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) 800ec7c: 687b ldr r3, [r7, #4] 800ec7e: 681b ldr r3, [r3, #0] 800ec80: 689b ldr r3, [r3, #8] 800ec82: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800ec86: 2b00 cmp r3, #0 800ec88: d002 beq.n 800ec90 { freelevel++; 800ec8a: 68fb ldr r3, [r7, #12] 800ec8c: 3301 adds r3, #1 800ec8e: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 2 status */ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) 800ec90: 687b ldr r3, [r7, #4] 800ec92: 681b ldr r3, [r3, #0] 800ec94: 689b ldr r3, [r3, #8] 800ec96: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800ec9a: 2b00 cmp r3, #0 800ec9c: d002 beq.n 800eca4 { freelevel++; 800ec9e: 68fb ldr r3, [r7, #12] 800eca0: 3301 adds r3, #1 800eca2: 60fb str r3, [r7, #12] } } /* Return Tx Mailboxes free level */ return freelevel; 800eca4: 68fb ldr r3, [r7, #12] } 800eca6: 4618 mov r0, r3 800eca8: 3714 adds r7, #20 800ecaa: 46bd mov sp, r7 800ecac: bc80 pop {r7} 800ecae: 4770 bx lr 0800ecb0 : * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { 800ecb0: b480 push {r7} 800ecb2: b087 sub sp, #28 800ecb4: af00 add r7, sp, #0 800ecb6: 60f8 str r0, [r7, #12] 800ecb8: 60b9 str r1, [r7, #8] 800ecba: 607a str r2, [r7, #4] 800ecbc: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800ecbe: 68fb ldr r3, [r7, #12] 800ecc0: f893 3020 ldrb.w r3, [r3, #32] 800ecc4: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || 800ecc6: 7dfb ldrb r3, [r7, #23] 800ecc8: 2b01 cmp r3, #1 800ecca: d003 beq.n 800ecd4 800eccc: 7dfb ldrb r3, [r7, #23] 800ecce: 2b02 cmp r3, #2 800ecd0: f040 8103 bne.w 800eeda (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800ecd4: 68bb ldr r3, [r7, #8] 800ecd6: 2b00 cmp r3, #0 800ecd8: d10e bne.n 800ecf8 { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) 800ecda: 68fb ldr r3, [r7, #12] 800ecdc: 681b ldr r3, [r3, #0] 800ecde: 68db ldr r3, [r3, #12] 800ece0: f003 0303 and.w r3, r3, #3 800ece4: 2b00 cmp r3, #0 800ece6: d116 bne.n 800ed16 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800ece8: 68fb ldr r3, [r7, #12] 800ecea: 6a5b ldr r3, [r3, #36] @ 0x24 800ecec: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800ecf0: 68fb ldr r3, [r7, #12] 800ecf2: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ecf4: 2301 movs r3, #1 800ecf6: e0f7 b.n 800eee8 } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) 800ecf8: 68fb ldr r3, [r7, #12] 800ecfa: 681b ldr r3, [r3, #0] 800ecfc: 691b ldr r3, [r3, #16] 800ecfe: f003 0303 and.w r3, r3, #3 800ed02: 2b00 cmp r3, #0 800ed04: d107 bne.n 800ed16 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800ed06: 68fb ldr r3, [r7, #12] 800ed08: 6a5b ldr r3, [r3, #36] @ 0x24 800ed0a: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800ed0e: 68fb ldr r3, [r7, #12] 800ed10: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ed12: 2301 movs r3, #1 800ed14: e0e8 b.n 800eee8 } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; 800ed16: 68fb ldr r3, [r7, #12] 800ed18: 681a ldr r2, [r3, #0] 800ed1a: 68bb ldr r3, [r7, #8] 800ed1c: 331b adds r3, #27 800ed1e: 011b lsls r3, r3, #4 800ed20: 4413 add r3, r2 800ed22: 681b ldr r3, [r3, #0] 800ed24: f003 0204 and.w r2, r3, #4 800ed28: 687b ldr r3, [r7, #4] 800ed2a: 609a str r2, [r3, #8] if (pHeader->IDE == CAN_ID_STD) 800ed2c: 687b ldr r3, [r7, #4] 800ed2e: 689b ldr r3, [r3, #8] 800ed30: 2b00 cmp r3, #0 800ed32: d10c bne.n 800ed4e { pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; 800ed34: 68fb ldr r3, [r7, #12] 800ed36: 681a ldr r2, [r3, #0] 800ed38: 68bb ldr r3, [r7, #8] 800ed3a: 331b adds r3, #27 800ed3c: 011b lsls r3, r3, #4 800ed3e: 4413 add r3, r2 800ed40: 681b ldr r3, [r3, #0] 800ed42: 0d5b lsrs r3, r3, #21 800ed44: f3c3 020a ubfx r2, r3, #0, #11 800ed48: 687b ldr r3, [r7, #4] 800ed4a: 601a str r2, [r3, #0] 800ed4c: e00b b.n 800ed66 } else { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; 800ed4e: 68fb ldr r3, [r7, #12] 800ed50: 681a ldr r2, [r3, #0] 800ed52: 68bb ldr r3, [r7, #8] 800ed54: 331b adds r3, #27 800ed56: 011b lsls r3, r3, #4 800ed58: 4413 add r3, r2 800ed5a: 681b ldr r3, [r3, #0] 800ed5c: 08db lsrs r3, r3, #3 800ed5e: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & 800ed62: 687b ldr r3, [r7, #4] 800ed64: 605a str r2, [r3, #4] } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); 800ed66: 68fb ldr r3, [r7, #12] 800ed68: 681a ldr r2, [r3, #0] 800ed6a: 68bb ldr r3, [r7, #8] 800ed6c: 331b adds r3, #27 800ed6e: 011b lsls r3, r3, #4 800ed70: 4413 add r3, r2 800ed72: 681b ldr r3, [r3, #0] 800ed74: f003 0202 and.w r2, r3, #2 800ed78: 687b ldr r3, [r7, #4] 800ed7a: 60da str r2, [r3, #12] if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) 800ed7c: 68fb ldr r3, [r7, #12] 800ed7e: 681a ldr r2, [r3, #0] 800ed80: 68bb ldr r3, [r7, #8] 800ed82: 331b adds r3, #27 800ed84: 011b lsls r3, r3, #4 800ed86: 4413 add r3, r2 800ed88: 3304 adds r3, #4 800ed8a: 681b ldr r3, [r3, #0] 800ed8c: f003 0308 and.w r3, r3, #8 800ed90: 2b00 cmp r3, #0 800ed92: d003 beq.n 800ed9c { /* Truncate DLC to 8 if received field is over range */ pHeader->DLC = 8U; 800ed94: 687b ldr r3, [r7, #4] 800ed96: 2208 movs r2, #8 800ed98: 611a str r2, [r3, #16] 800ed9a: e00b b.n 800edb4 } else { pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; 800ed9c: 68fb ldr r3, [r7, #12] 800ed9e: 681a ldr r2, [r3, #0] 800eda0: 68bb ldr r3, [r7, #8] 800eda2: 331b adds r3, #27 800eda4: 011b lsls r3, r3, #4 800eda6: 4413 add r3, r2 800eda8: 3304 adds r3, #4 800edaa: 681b ldr r3, [r3, #0] 800edac: f003 020f and.w r2, r3, #15 800edb0: 687b ldr r3, [r7, #4] 800edb2: 611a str r2, [r3, #16] } pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; 800edb4: 68fb ldr r3, [r7, #12] 800edb6: 681a ldr r2, [r3, #0] 800edb8: 68bb ldr r3, [r7, #8] 800edba: 331b adds r3, #27 800edbc: 011b lsls r3, r3, #4 800edbe: 4413 add r3, r2 800edc0: 3304 adds r3, #4 800edc2: 681b ldr r3, [r3, #0] 800edc4: 0a1b lsrs r3, r3, #8 800edc6: b2da uxtb r2, r3 800edc8: 687b ldr r3, [r7, #4] 800edca: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; 800edcc: 68fb ldr r3, [r7, #12] 800edce: 681a ldr r2, [r3, #0] 800edd0: 68bb ldr r3, [r7, #8] 800edd2: 331b adds r3, #27 800edd4: 011b lsls r3, r3, #4 800edd6: 4413 add r3, r2 800edd8: 3304 adds r3, #4 800edda: 681b ldr r3, [r3, #0] 800eddc: 0c1b lsrs r3, r3, #16 800edde: b29a uxth r2, r3 800ede0: 687b ldr r3, [r7, #4] 800ede2: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); 800ede4: 68fb ldr r3, [r7, #12] 800ede6: 681a ldr r2, [r3, #0] 800ede8: 68bb ldr r3, [r7, #8] 800edea: 011b lsls r3, r3, #4 800edec: 4413 add r3, r2 800edee: f503 73dc add.w r3, r3, #440 @ 0x1b8 800edf2: 681b ldr r3, [r3, #0] 800edf4: b2da uxtb r2, r3 800edf6: 683b ldr r3, [r7, #0] 800edf8: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); 800edfa: 68fb ldr r3, [r7, #12] 800edfc: 681a ldr r2, [r3, #0] 800edfe: 68bb ldr r3, [r7, #8] 800ee00: 011b lsls r3, r3, #4 800ee02: 4413 add r3, r2 800ee04: f503 73dc add.w r3, r3, #440 @ 0x1b8 800ee08: 681b ldr r3, [r3, #0] 800ee0a: 0a1a lsrs r2, r3, #8 800ee0c: 683b ldr r3, [r7, #0] 800ee0e: 3301 adds r3, #1 800ee10: b2d2 uxtb r2, r2 800ee12: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); 800ee14: 68fb ldr r3, [r7, #12] 800ee16: 681a ldr r2, [r3, #0] 800ee18: 68bb ldr r3, [r7, #8] 800ee1a: 011b lsls r3, r3, #4 800ee1c: 4413 add r3, r2 800ee1e: f503 73dc add.w r3, r3, #440 @ 0x1b8 800ee22: 681b ldr r3, [r3, #0] 800ee24: 0c1a lsrs r2, r3, #16 800ee26: 683b ldr r3, [r7, #0] 800ee28: 3302 adds r3, #2 800ee2a: b2d2 uxtb r2, r2 800ee2c: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); 800ee2e: 68fb ldr r3, [r7, #12] 800ee30: 681a ldr r2, [r3, #0] 800ee32: 68bb ldr r3, [r7, #8] 800ee34: 011b lsls r3, r3, #4 800ee36: 4413 add r3, r2 800ee38: f503 73dc add.w r3, r3, #440 @ 0x1b8 800ee3c: 681b ldr r3, [r3, #0] 800ee3e: 0e1a lsrs r2, r3, #24 800ee40: 683b ldr r3, [r7, #0] 800ee42: 3303 adds r3, #3 800ee44: b2d2 uxtb r2, r2 800ee46: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); 800ee48: 68fb ldr r3, [r7, #12] 800ee4a: 681a ldr r2, [r3, #0] 800ee4c: 68bb ldr r3, [r7, #8] 800ee4e: 011b lsls r3, r3, #4 800ee50: 4413 add r3, r2 800ee52: f503 73de add.w r3, r3, #444 @ 0x1bc 800ee56: 681a ldr r2, [r3, #0] 800ee58: 683b ldr r3, [r7, #0] 800ee5a: 3304 adds r3, #4 800ee5c: b2d2 uxtb r2, r2 800ee5e: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); 800ee60: 68fb ldr r3, [r7, #12] 800ee62: 681a ldr r2, [r3, #0] 800ee64: 68bb ldr r3, [r7, #8] 800ee66: 011b lsls r3, r3, #4 800ee68: 4413 add r3, r2 800ee6a: f503 73de add.w r3, r3, #444 @ 0x1bc 800ee6e: 681b ldr r3, [r3, #0] 800ee70: 0a1a lsrs r2, r3, #8 800ee72: 683b ldr r3, [r7, #0] 800ee74: 3305 adds r3, #5 800ee76: b2d2 uxtb r2, r2 800ee78: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); 800ee7a: 68fb ldr r3, [r7, #12] 800ee7c: 681a ldr r2, [r3, #0] 800ee7e: 68bb ldr r3, [r7, #8] 800ee80: 011b lsls r3, r3, #4 800ee82: 4413 add r3, r2 800ee84: f503 73de add.w r3, r3, #444 @ 0x1bc 800ee88: 681b ldr r3, [r3, #0] 800ee8a: 0c1a lsrs r2, r3, #16 800ee8c: 683b ldr r3, [r7, #0] 800ee8e: 3306 adds r3, #6 800ee90: b2d2 uxtb r2, r2 800ee92: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); 800ee94: 68fb ldr r3, [r7, #12] 800ee96: 681a ldr r2, [r3, #0] 800ee98: 68bb ldr r3, [r7, #8] 800ee9a: 011b lsls r3, r3, #4 800ee9c: 4413 add r3, r2 800ee9e: f503 73de add.w r3, r3, #444 @ 0x1bc 800eea2: 681b ldr r3, [r3, #0] 800eea4: 0e1a lsrs r2, r3, #24 800eea6: 683b ldr r3, [r7, #0] 800eea8: 3307 adds r3, #7 800eeaa: b2d2 uxtb r2, r2 800eeac: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800eeae: 68bb ldr r3, [r7, #8] 800eeb0: 2b00 cmp r3, #0 800eeb2: d108 bne.n 800eec6 { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); 800eeb4: 68fb ldr r3, [r7, #12] 800eeb6: 681b ldr r3, [r3, #0] 800eeb8: 68da ldr r2, [r3, #12] 800eeba: 68fb ldr r3, [r7, #12] 800eebc: 681b ldr r3, [r3, #0] 800eebe: f042 0220 orr.w r2, r2, #32 800eec2: 60da str r2, [r3, #12] 800eec4: e007 b.n 800eed6 } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); 800eec6: 68fb ldr r3, [r7, #12] 800eec8: 681b ldr r3, [r3, #0] 800eeca: 691a ldr r2, [r3, #16] 800eecc: 68fb ldr r3, [r7, #12] 800eece: 681b ldr r3, [r3, #0] 800eed0: f042 0220 orr.w r2, r2, #32 800eed4: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; 800eed6: 2300 movs r3, #0 800eed8: e006 b.n 800eee8 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800eeda: 68fb ldr r3, [r7, #12] 800eedc: 6a5b ldr r3, [r3, #36] @ 0x24 800eede: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800eee2: 68fb ldr r3, [r7, #12] 800eee4: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800eee6: 2301 movs r3, #1 } } 800eee8: 4618 mov r0, r3 800eeea: 371c adds r7, #28 800eeec: 46bd mov sp, r7 800eeee: bc80 pop {r7} 800eef0: 4770 bx lr 0800eef2 : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { 800eef2: b480 push {r7} 800eef4: b085 sub sp, #20 800eef6: af00 add r7, sp, #0 800eef8: 6078 str r0, [r7, #4] 800eefa: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800eefc: 687b ldr r3, [r7, #4] 800eefe: f893 3020 ldrb.w r3, [r3, #32] 800ef02: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || 800ef04: 7bfb ldrb r3, [r7, #15] 800ef06: 2b01 cmp r3, #1 800ef08: d002 beq.n 800ef10 800ef0a: 7bfb ldrb r3, [r7, #15] 800ef0c: 2b02 cmp r3, #2 800ef0e: d109 bne.n 800ef24 (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); 800ef10: 687b ldr r3, [r7, #4] 800ef12: 681b ldr r3, [r3, #0] 800ef14: 6959 ldr r1, [r3, #20] 800ef16: 687b ldr r3, [r7, #4] 800ef18: 681b ldr r3, [r3, #0] 800ef1a: 683a ldr r2, [r7, #0] 800ef1c: 430a orrs r2, r1 800ef1e: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; 800ef20: 2300 movs r3, #0 800ef22: e006 b.n 800ef32 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800ef24: 687b ldr r3, [r7, #4] 800ef26: 6a5b ldr r3, [r3, #36] @ 0x24 800ef28: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800ef2c: 687b ldr r3, [r7, #4] 800ef2e: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ef30: 2301 movs r3, #1 } } 800ef32: 4618 mov r0, r3 800ef34: 3714 adds r7, #20 800ef36: 46bd mov sp, r7 800ef38: bc80 pop {r7} 800ef3a: 4770 bx lr 0800ef3c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { 800ef3c: b580 push {r7, lr} 800ef3e: b08a sub sp, #40 @ 0x28 800ef40: af00 add r7, sp, #0 800ef42: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; 800ef44: 2300 movs r3, #0 800ef46: 627b str r3, [r7, #36] @ 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); 800ef48: 687b ldr r3, [r7, #4] 800ef4a: 681b ldr r3, [r3, #0] 800ef4c: 695b ldr r3, [r3, #20] 800ef4e: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); 800ef50: 687b ldr r3, [r7, #4] 800ef52: 681b ldr r3, [r3, #0] 800ef54: 685b ldr r3, [r3, #4] 800ef56: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); 800ef58: 687b ldr r3, [r7, #4] 800ef5a: 681b ldr r3, [r3, #0] 800ef5c: 689b ldr r3, [r3, #8] 800ef5e: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); 800ef60: 687b ldr r3, [r7, #4] 800ef62: 681b ldr r3, [r3, #0] 800ef64: 68db ldr r3, [r3, #12] 800ef66: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); 800ef68: 687b ldr r3, [r7, #4] 800ef6a: 681b ldr r3, [r3, #0] 800ef6c: 691b ldr r3, [r3, #16] 800ef6e: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); 800ef70: 687b ldr r3, [r7, #4] 800ef72: 681b ldr r3, [r3, #0] 800ef74: 699b ldr r3, [r3, #24] 800ef76: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) 800ef78: 6a3b ldr r3, [r7, #32] 800ef7a: f003 0301 and.w r3, r3, #1 800ef7e: 2b00 cmp r3, #0 800ef80: d07c beq.n 800f07c { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) 800ef82: 69bb ldr r3, [r7, #24] 800ef84: f003 0301 and.w r3, r3, #1 800ef88: 2b00 cmp r3, #0 800ef8a: d023 beq.n 800efd4 { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); 800ef8c: 687b ldr r3, [r7, #4] 800ef8e: 681b ldr r3, [r3, #0] 800ef90: 2201 movs r2, #1 800ef92: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) 800ef94: 69bb ldr r3, [r7, #24] 800ef96: f003 0302 and.w r3, r3, #2 800ef9a: 2b00 cmp r3, #0 800ef9c: d003 beq.n 800efa6 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); 800ef9e: 6878 ldr r0, [r7, #4] 800efa0: f000 f983 bl 800f2aa 800efa4: e016 b.n 800efd4 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) 800efa6: 69bb ldr r3, [r7, #24] 800efa8: f003 0304 and.w r3, r3, #4 800efac: 2b00 cmp r3, #0 800efae: d004 beq.n 800efba { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; 800efb0: 6a7b ldr r3, [r7, #36] @ 0x24 800efb2: f443 6300 orr.w r3, r3, #2048 @ 0x800 800efb6: 627b str r3, [r7, #36] @ 0x24 800efb8: e00c b.n 800efd4 } else if ((tsrflags & CAN_TSR_TERR0) != 0U) 800efba: 69bb ldr r3, [r7, #24] 800efbc: f003 0308 and.w r3, r3, #8 800efc0: 2b00 cmp r3, #0 800efc2: d004 beq.n 800efce { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; 800efc4: 6a7b ldr r3, [r7, #36] @ 0x24 800efc6: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800efca: 627b str r3, [r7, #36] @ 0x24 800efcc: e002 b.n 800efd4 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); 800efce: 6878 ldr r0, [r7, #4] 800efd0: f000 f986 bl 800f2e0 } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) 800efd4: 69bb ldr r3, [r7, #24] 800efd6: f403 7380 and.w r3, r3, #256 @ 0x100 800efda: 2b00 cmp r3, #0 800efdc: d024 beq.n 800f028 { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); 800efde: 687b ldr r3, [r7, #4] 800efe0: 681b ldr r3, [r3, #0] 800efe2: f44f 7280 mov.w r2, #256 @ 0x100 800efe6: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) 800efe8: 69bb ldr r3, [r7, #24] 800efea: f403 7300 and.w r3, r3, #512 @ 0x200 800efee: 2b00 cmp r3, #0 800eff0: d003 beq.n 800effa #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); 800eff2: 6878 ldr r0, [r7, #4] 800eff4: f000 f962 bl 800f2bc 800eff8: e016 b.n 800f028 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) 800effa: 69bb ldr r3, [r7, #24] 800effc: f403 6380 and.w r3, r3, #1024 @ 0x400 800f000: 2b00 cmp r3, #0 800f002: d004 beq.n 800f00e { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; 800f004: 6a7b ldr r3, [r7, #36] @ 0x24 800f006: f443 5300 orr.w r3, r3, #8192 @ 0x2000 800f00a: 627b str r3, [r7, #36] @ 0x24 800f00c: e00c b.n 800f028 } else if ((tsrflags & CAN_TSR_TERR1) != 0U) 800f00e: 69bb ldr r3, [r7, #24] 800f010: f403 6300 and.w r3, r3, #2048 @ 0x800 800f014: 2b00 cmp r3, #0 800f016: d004 beq.n 800f022 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; 800f018: 6a7b ldr r3, [r7, #36] @ 0x24 800f01a: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800f01e: 627b str r3, [r7, #36] @ 0x24 800f020: e002 b.n 800f028 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); 800f022: 6878 ldr r0, [r7, #4] 800f024: f000 f965 bl 800f2f2 } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) 800f028: 69bb ldr r3, [r7, #24] 800f02a: f403 3380 and.w r3, r3, #65536 @ 0x10000 800f02e: 2b00 cmp r3, #0 800f030: d024 beq.n 800f07c { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); 800f032: 687b ldr r3, [r7, #4] 800f034: 681b ldr r3, [r3, #0] 800f036: f44f 3280 mov.w r2, #65536 @ 0x10000 800f03a: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) 800f03c: 69bb ldr r3, [r7, #24] 800f03e: f403 3300 and.w r3, r3, #131072 @ 0x20000 800f042: 2b00 cmp r3, #0 800f044: d003 beq.n 800f04e #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); 800f046: 6878 ldr r0, [r7, #4] 800f048: f000 f941 bl 800f2ce 800f04c: e016 b.n 800f07c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) 800f04e: 69bb ldr r3, [r7, #24] 800f050: f403 2380 and.w r3, r3, #262144 @ 0x40000 800f054: 2b00 cmp r3, #0 800f056: d004 beq.n 800f062 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; 800f058: 6a7b ldr r3, [r7, #36] @ 0x24 800f05a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f05e: 627b str r3, [r7, #36] @ 0x24 800f060: e00c b.n 800f07c } else if ((tsrflags & CAN_TSR_TERR2) != 0U) 800f062: 69bb ldr r3, [r7, #24] 800f064: f403 2300 and.w r3, r3, #524288 @ 0x80000 800f068: 2b00 cmp r3, #0 800f06a: d004 beq.n 800f076 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; 800f06c: 6a7b ldr r3, [r7, #36] @ 0x24 800f06e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800f072: 627b str r3, [r7, #36] @ 0x24 800f074: e002 b.n 800f07c #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); 800f076: 6878 ldr r0, [r7, #4] 800f078: f000 f944 bl 800f304 } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) 800f07c: 6a3b ldr r3, [r7, #32] 800f07e: f003 0308 and.w r3, r3, #8 800f082: 2b00 cmp r3, #0 800f084: d00c beq.n 800f0a0 { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) 800f086: 697b ldr r3, [r7, #20] 800f088: f003 0310 and.w r3, r3, #16 800f08c: 2b00 cmp r3, #0 800f08e: d007 beq.n 800f0a0 { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; 800f090: 6a7b ldr r3, [r7, #36] @ 0x24 800f092: f443 7300 orr.w r3, r3, #512 @ 0x200 800f096: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); 800f098: 687b ldr r3, [r7, #4] 800f09a: 681b ldr r3, [r3, #0] 800f09c: 2210 movs r2, #16 800f09e: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) 800f0a0: 6a3b ldr r3, [r7, #32] 800f0a2: f003 0304 and.w r3, r3, #4 800f0a6: 2b00 cmp r3, #0 800f0a8: d00b beq.n 800f0c2 { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) 800f0aa: 697b ldr r3, [r7, #20] 800f0ac: f003 0308 and.w r3, r3, #8 800f0b0: 2b00 cmp r3, #0 800f0b2: d006 beq.n 800f0c2 { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); 800f0b4: 687b ldr r3, [r7, #4] 800f0b6: 681b ldr r3, [r3, #0] 800f0b8: 2208 movs r2, #8 800f0ba: 60da str r2, [r3, #12] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); 800f0bc: 6878 ldr r0, [r7, #4] 800f0be: f000 f933 bl 800f328 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) 800f0c2: 6a3b ldr r3, [r7, #32] 800f0c4: f003 0302 and.w r3, r3, #2 800f0c8: 2b00 cmp r3, #0 800f0ca: d009 beq.n 800f0e0 { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) 800f0cc: 687b ldr r3, [r7, #4] 800f0ce: 681b ldr r3, [r3, #0] 800f0d0: 68db ldr r3, [r3, #12] 800f0d2: f003 0303 and.w r3, r3, #3 800f0d6: 2b00 cmp r3, #0 800f0d8: d002 beq.n 800f0e0 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); 800f0da: 6878 ldr r0, [r7, #4] 800f0dc: f000 f91b bl 800f316 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) 800f0e0: 6a3b ldr r3, [r7, #32] 800f0e2: f003 0340 and.w r3, r3, #64 @ 0x40 800f0e6: 2b00 cmp r3, #0 800f0e8: d00c beq.n 800f104 { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) 800f0ea: 693b ldr r3, [r7, #16] 800f0ec: f003 0310 and.w r3, r3, #16 800f0f0: 2b00 cmp r3, #0 800f0f2: d007 beq.n 800f104 { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; 800f0f4: 6a7b ldr r3, [r7, #36] @ 0x24 800f0f6: f443 6380 orr.w r3, r3, #1024 @ 0x400 800f0fa: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); 800f0fc: 687b ldr r3, [r7, #4] 800f0fe: 681b ldr r3, [r3, #0] 800f100: 2210 movs r2, #16 800f102: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) 800f104: 6a3b ldr r3, [r7, #32] 800f106: f003 0320 and.w r3, r3, #32 800f10a: 2b00 cmp r3, #0 800f10c: d00b beq.n 800f126 { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) 800f10e: 693b ldr r3, [r7, #16] 800f110: f003 0308 and.w r3, r3, #8 800f114: 2b00 cmp r3, #0 800f116: d006 beq.n 800f126 { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); 800f118: 687b ldr r3, [r7, #4] 800f11a: 681b ldr r3, [r3, #0] 800f11c: 2208 movs r2, #8 800f11e: 611a str r2, [r3, #16] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); 800f120: 6878 ldr r0, [r7, #4] 800f122: f000 f90a bl 800f33a #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) 800f126: 6a3b ldr r3, [r7, #32] 800f128: f003 0310 and.w r3, r3, #16 800f12c: 2b00 cmp r3, #0 800f12e: d009 beq.n 800f144 { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) 800f130: 687b ldr r3, [r7, #4] 800f132: 681b ldr r3, [r3, #0] 800f134: 691b ldr r3, [r3, #16] 800f136: f003 0303 and.w r3, r3, #3 800f13a: 2b00 cmp r3, #0 800f13c: d002 beq.n 800f144 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); 800f13e: 6878 ldr r0, [r7, #4] 800f140: f7fb fdbc bl 800acbc #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) 800f144: 6a3b ldr r3, [r7, #32] 800f146: f403 3300 and.w r3, r3, #131072 @ 0x20000 800f14a: 2b00 cmp r3, #0 800f14c: d00b beq.n 800f166 { if ((msrflags & CAN_MSR_SLAKI) != 0U) 800f14e: 69fb ldr r3, [r7, #28] 800f150: f003 0310 and.w r3, r3, #16 800f154: 2b00 cmp r3, #0 800f156: d006 beq.n 800f166 { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); 800f158: 687b ldr r3, [r7, #4] 800f15a: 681b ldr r3, [r3, #0] 800f15c: 2210 movs r2, #16 800f15e: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->SleepCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); 800f160: 6878 ldr r0, [r7, #4] 800f162: f000 f8f3 bl 800f34c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ if ((interrupts & CAN_IT_WAKEUP) != 0U) 800f166: 6a3b ldr r3, [r7, #32] 800f168: f403 3380 and.w r3, r3, #65536 @ 0x10000 800f16c: 2b00 cmp r3, #0 800f16e: d00b beq.n 800f188 { if ((msrflags & CAN_MSR_WKUI) != 0U) 800f170: 69fb ldr r3, [r7, #28] 800f172: f003 0308 and.w r3, r3, #8 800f176: 2b00 cmp r3, #0 800f178: d006 beq.n 800f188 { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); 800f17a: 687b ldr r3, [r7, #4] 800f17c: 681b ldr r3, [r3, #0] 800f17e: 2208 movs r2, #8 800f180: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->WakeUpFromRxMsgCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); 800f182: 6878 ldr r0, [r7, #4] 800f184: f000 f8eb bl 800f35e #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ if ((interrupts & CAN_IT_ERROR) != 0U) 800f188: 6a3b ldr r3, [r7, #32] 800f18a: f403 4300 and.w r3, r3, #32768 @ 0x8000 800f18e: 2b00 cmp r3, #0 800f190: d07b beq.n 800f28a { if ((msrflags & CAN_MSR_ERRI) != 0U) 800f192: 69fb ldr r3, [r7, #28] 800f194: f003 0304 and.w r3, r3, #4 800f198: 2b00 cmp r3, #0 800f19a: d072 beq.n 800f282 { /* Check Error Warning Flag */ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800f19c: 6a3b ldr r3, [r7, #32] 800f19e: f403 7380 and.w r3, r3, #256 @ 0x100 800f1a2: 2b00 cmp r3, #0 800f1a4: d008 beq.n 800f1b8 ((esrflags & CAN_ESR_EWGF) != 0U)) 800f1a6: 68fb ldr r3, [r7, #12] 800f1a8: f003 0301 and.w r3, r3, #1 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800f1ac: 2b00 cmp r3, #0 800f1ae: d003 beq.n 800f1b8 { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; 800f1b0: 6a7b ldr r3, [r7, #36] @ 0x24 800f1b2: f043 0301 orr.w r3, r3, #1 800f1b6: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Warning Flag as read-only */ } /* Check Error Passive Flag */ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800f1b8: 6a3b ldr r3, [r7, #32] 800f1ba: f403 7300 and.w r3, r3, #512 @ 0x200 800f1be: 2b00 cmp r3, #0 800f1c0: d008 beq.n 800f1d4 ((esrflags & CAN_ESR_EPVF) != 0U)) 800f1c2: 68fb ldr r3, [r7, #12] 800f1c4: f003 0302 and.w r3, r3, #2 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800f1c8: 2b00 cmp r3, #0 800f1ca: d003 beq.n 800f1d4 { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; 800f1cc: 6a7b ldr r3, [r7, #36] @ 0x24 800f1ce: f043 0302 orr.w r3, r3, #2 800f1d2: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-off Flag */ if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800f1d4: 6a3b ldr r3, [r7, #32] 800f1d6: f403 6380 and.w r3, r3, #1024 @ 0x400 800f1da: 2b00 cmp r3, #0 800f1dc: d008 beq.n 800f1f0 ((esrflags & CAN_ESR_BOFF) != 0U)) 800f1de: 68fb ldr r3, [r7, #12] 800f1e0: f003 0304 and.w r3, r3, #4 if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800f1e4: 2b00 cmp r3, #0 800f1e6: d003 beq.n 800f1f0 { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; 800f1e8: 6a7b ldr r3, [r7, #36] @ 0x24 800f1ea: f043 0304 orr.w r3, r3, #4 800f1ee: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Bus-Off as read-only */ } /* Check Last Error Code Flag */ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800f1f0: 6a3b ldr r3, [r7, #32] 800f1f2: f403 6300 and.w r3, r3, #2048 @ 0x800 800f1f6: 2b00 cmp r3, #0 800f1f8: d043 beq.n 800f282 ((esrflags & CAN_ESR_LEC) != 0U)) 800f1fa: 68fb ldr r3, [r7, #12] 800f1fc: f003 0370 and.w r3, r3, #112 @ 0x70 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800f200: 2b00 cmp r3, #0 800f202: d03e beq.n 800f282 { switch (esrflags & CAN_ESR_LEC) 800f204: 68fb ldr r3, [r7, #12] 800f206: f003 0370 and.w r3, r3, #112 @ 0x70 800f20a: 2b60 cmp r3, #96 @ 0x60 800f20c: d02b beq.n 800f266 800f20e: 2b60 cmp r3, #96 @ 0x60 800f210: d82e bhi.n 800f270 800f212: 2b50 cmp r3, #80 @ 0x50 800f214: d022 beq.n 800f25c 800f216: 2b50 cmp r3, #80 @ 0x50 800f218: d82a bhi.n 800f270 800f21a: 2b40 cmp r3, #64 @ 0x40 800f21c: d019 beq.n 800f252 800f21e: 2b40 cmp r3, #64 @ 0x40 800f220: d826 bhi.n 800f270 800f222: 2b30 cmp r3, #48 @ 0x30 800f224: d010 beq.n 800f248 800f226: 2b30 cmp r3, #48 @ 0x30 800f228: d822 bhi.n 800f270 800f22a: 2b10 cmp r3, #16 800f22c: d002 beq.n 800f234 800f22e: 2b20 cmp r3, #32 800f230: d005 beq.n 800f23e case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): /* Set CAN error code to CRC error */ errorcode |= HAL_CAN_ERROR_CRC; break; default: break; 800f232: e01d b.n 800f270 errorcode |= HAL_CAN_ERROR_STF; 800f234: 6a7b ldr r3, [r7, #36] @ 0x24 800f236: f043 0308 orr.w r3, r3, #8 800f23a: 627b str r3, [r7, #36] @ 0x24 break; 800f23c: e019 b.n 800f272 errorcode |= HAL_CAN_ERROR_FOR; 800f23e: 6a7b ldr r3, [r7, #36] @ 0x24 800f240: f043 0310 orr.w r3, r3, #16 800f244: 627b str r3, [r7, #36] @ 0x24 break; 800f246: e014 b.n 800f272 errorcode |= HAL_CAN_ERROR_ACK; 800f248: 6a7b ldr r3, [r7, #36] @ 0x24 800f24a: f043 0320 orr.w r3, r3, #32 800f24e: 627b str r3, [r7, #36] @ 0x24 break; 800f250: e00f b.n 800f272 errorcode |= HAL_CAN_ERROR_BR; 800f252: 6a7b ldr r3, [r7, #36] @ 0x24 800f254: f043 0340 orr.w r3, r3, #64 @ 0x40 800f258: 627b str r3, [r7, #36] @ 0x24 break; 800f25a: e00a b.n 800f272 errorcode |= HAL_CAN_ERROR_BD; 800f25c: 6a7b ldr r3, [r7, #36] @ 0x24 800f25e: f043 0380 orr.w r3, r3, #128 @ 0x80 800f262: 627b str r3, [r7, #36] @ 0x24 break; 800f264: e005 b.n 800f272 errorcode |= HAL_CAN_ERROR_CRC; 800f266: 6a7b ldr r3, [r7, #36] @ 0x24 800f268: f443 7380 orr.w r3, r3, #256 @ 0x100 800f26c: 627b str r3, [r7, #36] @ 0x24 break; 800f26e: e000 b.n 800f272 break; 800f270: bf00 nop } /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); 800f272: 687b ldr r3, [r7, #4] 800f274: 681b ldr r3, [r3, #0] 800f276: 699a ldr r2, [r3, #24] 800f278: 687b ldr r3, [r7, #4] 800f27a: 681b ldr r3, [r3, #0] 800f27c: f022 0270 bic.w r2, r2, #112 @ 0x70 800f280: 619a str r2, [r3, #24] } } /* Clear ERRI Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); 800f282: 687b ldr r3, [r7, #4] 800f284: 681b ldr r3, [r3, #0] 800f286: 2204 movs r2, #4 800f288: 605a str r2, [r3, #4] } /* Call the Error call Back in case of Errors */ if (errorcode != HAL_CAN_ERROR_NONE) 800f28a: 6a7b ldr r3, [r7, #36] @ 0x24 800f28c: 2b00 cmp r3, #0 800f28e: d008 beq.n 800f2a2 { /* Update error code in handle */ hcan->ErrorCode |= errorcode; 800f290: 687b ldr r3, [r7, #4] 800f292: 6a5a ldr r2, [r3, #36] @ 0x24 800f294: 6a7b ldr r3, [r7, #36] @ 0x24 800f296: 431a orrs r2, r3 800f298: 687b ldr r3, [r7, #4] 800f29a: 625a str r2, [r3, #36] @ 0x24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->ErrorCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); 800f29c: 6878 ldr r0, [r7, #4] 800f29e: f000 f867 bl 800f370 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } 800f2a2: bf00 nop 800f2a4: 3728 adds r7, #40 @ 0x28 800f2a6: 46bd mov sp, r7 800f2a8: bd80 pop {r7, pc} 0800f2aa : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { 800f2aa: b480 push {r7} 800f2ac: b083 sub sp, #12 800f2ae: af00 add r7, sp, #0 800f2b0: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the user file */ } 800f2b2: bf00 nop 800f2b4: 370c adds r7, #12 800f2b6: 46bd mov sp, r7 800f2b8: bc80 pop {r7} 800f2ba: 4770 bx lr 0800f2bc : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { 800f2bc: b480 push {r7} 800f2be: b083 sub sp, #12 800f2c0: af00 add r7, sp, #0 800f2c2: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the user file */ } 800f2c4: bf00 nop 800f2c6: 370c adds r7, #12 800f2c8: 46bd mov sp, r7 800f2ca: bc80 pop {r7} 800f2cc: 4770 bx lr 0800f2ce : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) { 800f2ce: b480 push {r7} 800f2d0: b083 sub sp, #12 800f2d2: af00 add r7, sp, #0 800f2d4: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the user file */ } 800f2d6: bf00 nop 800f2d8: 370c adds r7, #12 800f2da: 46bd mov sp, r7 800f2dc: bc80 pop {r7} 800f2de: 4770 bx lr 0800f2e0 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { 800f2e0: b480 push {r7} 800f2e2: b083 sub sp, #12 800f2e4: af00 add r7, sp, #0 800f2e6: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } 800f2e8: bf00 nop 800f2ea: 370c adds r7, #12 800f2ec: 46bd mov sp, r7 800f2ee: bc80 pop {r7} 800f2f0: 4770 bx lr 0800f2f2 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { 800f2f2: b480 push {r7} 800f2f4: b083 sub sp, #12 800f2f6: af00 add r7, sp, #0 800f2f8: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } 800f2fa: bf00 nop 800f2fc: 370c adds r7, #12 800f2fe: 46bd mov sp, r7 800f300: bc80 pop {r7} 800f302: 4770 bx lr 0800f304 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { 800f304: b480 push {r7} 800f306: b083 sub sp, #12 800f308: af00 add r7, sp, #0 800f30a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } 800f30c: bf00 nop 800f30e: 370c adds r7, #12 800f310: 46bd mov sp, r7 800f312: bc80 pop {r7} 800f314: 4770 bx lr 0800f316 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { 800f316: b480 push {r7} 800f318: b083 sub sp, #12 800f31a: af00 add r7, sp, #0 800f31c: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the user file */ } 800f31e: bf00 nop 800f320: 370c adds r7, #12 800f322: 46bd mov sp, r7 800f324: bc80 pop {r7} 800f326: 4770 bx lr 0800f328 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { 800f328: b480 push {r7} 800f32a: b083 sub sp, #12 800f32c: af00 add r7, sp, #0 800f32e: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } 800f330: bf00 nop 800f332: 370c adds r7, #12 800f334: 46bd mov sp, r7 800f336: bc80 pop {r7} 800f338: 4770 bx lr 0800f33a : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { 800f33a: b480 push {r7} 800f33c: b083 sub sp, #12 800f33e: af00 add r7, sp, #0 800f340: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } 800f342: bf00 nop 800f344: 370c adds r7, #12 800f346: 46bd mov sp, r7 800f348: bc80 pop {r7} 800f34a: 4770 bx lr 0800f34c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { 800f34c: b480 push {r7} 800f34e: b083 sub sp, #12 800f350: af00 add r7, sp, #0 800f352: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } 800f354: bf00 nop 800f356: 370c adds r7, #12 800f358: 46bd mov sp, r7 800f35a: bc80 pop {r7} 800f35c: 4770 bx lr 0800f35e : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { 800f35e: b480 push {r7} 800f360: b083 sub sp, #12 800f362: af00 add r7, sp, #0 800f364: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } 800f366: bf00 nop 800f368: 370c adds r7, #12 800f36a: 46bd mov sp, r7 800f36c: bc80 pop {r7} 800f36e: 4770 bx lr 0800f370 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { 800f370: b480 push {r7} 800f372: b083 sub sp, #12 800f374: af00 add r7, sp, #0 800f376: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } 800f378: bf00 nop 800f37a: 370c adds r7, #12 800f37c: 46bd mov sp, r7 800f37e: bc80 pop {r7} 800f380: 4770 bx lr ... 0800f384 <__NVIC_SetPriorityGrouping>: { 800f384: b480 push {r7} 800f386: b085 sub sp, #20 800f388: af00 add r7, sp, #0 800f38a: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800f38c: 687b ldr r3, [r7, #4] 800f38e: f003 0307 and.w r3, r3, #7 800f392: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 800f394: 4b0c ldr r3, [pc, #48] @ (800f3c8 <__NVIC_SetPriorityGrouping+0x44>) 800f396: 68db ldr r3, [r3, #12] 800f398: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800f39a: 68ba ldr r2, [r7, #8] 800f39c: f64f 03ff movw r3, #63743 @ 0xf8ff 800f3a0: 4013 ands r3, r2 800f3a2: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800f3a4: 68fb ldr r3, [r7, #12] 800f3a6: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800f3a8: 68bb ldr r3, [r7, #8] 800f3aa: 4313 orrs r3, r2 reg_value = (reg_value | 800f3ac: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 800f3b0: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800f3b4: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800f3b6: 4a04 ldr r2, [pc, #16] @ (800f3c8 <__NVIC_SetPriorityGrouping+0x44>) 800f3b8: 68bb ldr r3, [r7, #8] 800f3ba: 60d3 str r3, [r2, #12] } 800f3bc: bf00 nop 800f3be: 3714 adds r7, #20 800f3c0: 46bd mov sp, r7 800f3c2: bc80 pop {r7} 800f3c4: 4770 bx lr 800f3c6: bf00 nop 800f3c8: e000ed00 .word 0xe000ed00 0800f3cc <__NVIC_GetPriorityGrouping>: { 800f3cc: b480 push {r7} 800f3ce: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800f3d0: 4b04 ldr r3, [pc, #16] @ (800f3e4 <__NVIC_GetPriorityGrouping+0x18>) 800f3d2: 68db ldr r3, [r3, #12] 800f3d4: 0a1b lsrs r3, r3, #8 800f3d6: f003 0307 and.w r3, r3, #7 } 800f3da: 4618 mov r0, r3 800f3dc: 46bd mov sp, r7 800f3de: bc80 pop {r7} 800f3e0: 4770 bx lr 800f3e2: bf00 nop 800f3e4: e000ed00 .word 0xe000ed00 0800f3e8 <__NVIC_EnableIRQ>: { 800f3e8: b480 push {r7} 800f3ea: b083 sub sp, #12 800f3ec: af00 add r7, sp, #0 800f3ee: 4603 mov r3, r0 800f3f0: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800f3f2: f997 3007 ldrsb.w r3, [r7, #7] 800f3f6: 2b00 cmp r3, #0 800f3f8: db0b blt.n 800f412 <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800f3fa: 79fb ldrb r3, [r7, #7] 800f3fc: f003 021f and.w r2, r3, #31 800f400: 4906 ldr r1, [pc, #24] @ (800f41c <__NVIC_EnableIRQ+0x34>) 800f402: f997 3007 ldrsb.w r3, [r7, #7] 800f406: 095b lsrs r3, r3, #5 800f408: 2001 movs r0, #1 800f40a: fa00 f202 lsl.w r2, r0, r2 800f40e: f841 2023 str.w r2, [r1, r3, lsl #2] } 800f412: bf00 nop 800f414: 370c adds r7, #12 800f416: 46bd mov sp, r7 800f418: bc80 pop {r7} 800f41a: 4770 bx lr 800f41c: e000e100 .word 0xe000e100 0800f420 <__NVIC_SetPriority>: { 800f420: b480 push {r7} 800f422: b083 sub sp, #12 800f424: af00 add r7, sp, #0 800f426: 4603 mov r3, r0 800f428: 6039 str r1, [r7, #0] 800f42a: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800f42c: f997 3007 ldrsb.w r3, [r7, #7] 800f430: 2b00 cmp r3, #0 800f432: db0a blt.n 800f44a <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800f434: 683b ldr r3, [r7, #0] 800f436: b2da uxtb r2, r3 800f438: 490c ldr r1, [pc, #48] @ (800f46c <__NVIC_SetPriority+0x4c>) 800f43a: f997 3007 ldrsb.w r3, [r7, #7] 800f43e: 0112 lsls r2, r2, #4 800f440: b2d2 uxtb r2, r2 800f442: 440b add r3, r1 800f444: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 800f448: e00a b.n 800f460 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800f44a: 683b ldr r3, [r7, #0] 800f44c: b2da uxtb r2, r3 800f44e: 4908 ldr r1, [pc, #32] @ (800f470 <__NVIC_SetPriority+0x50>) 800f450: 79fb ldrb r3, [r7, #7] 800f452: f003 030f and.w r3, r3, #15 800f456: 3b04 subs r3, #4 800f458: 0112 lsls r2, r2, #4 800f45a: b2d2 uxtb r2, r2 800f45c: 440b add r3, r1 800f45e: 761a strb r2, [r3, #24] } 800f460: bf00 nop 800f462: 370c adds r7, #12 800f464: 46bd mov sp, r7 800f466: bc80 pop {r7} 800f468: 4770 bx lr 800f46a: bf00 nop 800f46c: e000e100 .word 0xe000e100 800f470: e000ed00 .word 0xe000ed00 0800f474 : { 800f474: b480 push {r7} 800f476: b089 sub sp, #36 @ 0x24 800f478: af00 add r7, sp, #0 800f47a: 60f8 str r0, [r7, #12] 800f47c: 60b9 str r1, [r7, #8] 800f47e: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800f480: 68fb ldr r3, [r7, #12] 800f482: f003 0307 and.w r3, r3, #7 800f486: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 800f488: 69fb ldr r3, [r7, #28] 800f48a: f1c3 0307 rsb r3, r3, #7 800f48e: 2b04 cmp r3, #4 800f490: bf28 it cs 800f492: 2304 movcs r3, #4 800f494: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800f496: 69fb ldr r3, [r7, #28] 800f498: 3304 adds r3, #4 800f49a: 2b06 cmp r3, #6 800f49c: d902 bls.n 800f4a4 800f49e: 69fb ldr r3, [r7, #28] 800f4a0: 3b03 subs r3, #3 800f4a2: e000 b.n 800f4a6 800f4a4: 2300 movs r3, #0 800f4a6: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800f4a8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800f4ac: 69bb ldr r3, [r7, #24] 800f4ae: fa02 f303 lsl.w r3, r2, r3 800f4b2: 43da mvns r2, r3 800f4b4: 68bb ldr r3, [r7, #8] 800f4b6: 401a ands r2, r3 800f4b8: 697b ldr r3, [r7, #20] 800f4ba: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800f4bc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800f4c0: 697b ldr r3, [r7, #20] 800f4c2: fa01 f303 lsl.w r3, r1, r3 800f4c6: 43d9 mvns r1, r3 800f4c8: 687b ldr r3, [r7, #4] 800f4ca: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800f4cc: 4313 orrs r3, r2 } 800f4ce: 4618 mov r0, r3 800f4d0: 3724 adds r7, #36 @ 0x24 800f4d2: 46bd mov sp, r7 800f4d4: bc80 pop {r7} 800f4d6: 4770 bx lr 0800f4d8 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800f4d8: b580 push {r7, lr} 800f4da: b082 sub sp, #8 800f4dc: af00 add r7, sp, #0 800f4de: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 800f4e0: 687b ldr r3, [r7, #4] 800f4e2: 3b01 subs r3, #1 800f4e4: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800f4e8: d301 bcc.n 800f4ee { return (1UL); /* Reload value impossible */ 800f4ea: 2301 movs r3, #1 800f4ec: e00f b.n 800f50e } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800f4ee: 4a0a ldr r2, [pc, #40] @ (800f518 ) 800f4f0: 687b ldr r3, [r7, #4] 800f4f2: 3b01 subs r3, #1 800f4f4: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800f4f6: 210f movs r1, #15 800f4f8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800f4fc: f7ff ff90 bl 800f420 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800f500: 4b05 ldr r3, [pc, #20] @ (800f518 ) 800f502: 2200 movs r2, #0 800f504: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800f506: 4b04 ldr r3, [pc, #16] @ (800f518 ) 800f508: 2207 movs r2, #7 800f50a: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 800f50c: 2300 movs r3, #0 } 800f50e: 4618 mov r0, r3 800f510: 3708 adds r7, #8 800f512: 46bd mov sp, r7 800f514: bd80 pop {r7, pc} 800f516: bf00 nop 800f518: e000e010 .word 0xe000e010 0800f51c : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 800f51c: b580 push {r7, lr} 800f51e: b082 sub sp, #8 800f520: af00 add r7, sp, #0 800f522: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800f524: 6878 ldr r0, [r7, #4] 800f526: f7ff ff2d bl 800f384 <__NVIC_SetPriorityGrouping> } 800f52a: bf00 nop 800f52c: 3708 adds r7, #8 800f52e: 46bd mov sp, r7 800f530: bd80 pop {r7, pc} 0800f532 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800f532: b580 push {r7, lr} 800f534: b086 sub sp, #24 800f536: af00 add r7, sp, #0 800f538: 4603 mov r3, r0 800f53a: 60b9 str r1, [r7, #8] 800f53c: 607a str r2, [r7, #4] 800f53e: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 800f540: 2300 movs r3, #0 800f542: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800f544: f7ff ff42 bl 800f3cc <__NVIC_GetPriorityGrouping> 800f548: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800f54a: 687a ldr r2, [r7, #4] 800f54c: 68b9 ldr r1, [r7, #8] 800f54e: 6978 ldr r0, [r7, #20] 800f550: f7ff ff90 bl 800f474 800f554: 4602 mov r2, r0 800f556: f997 300f ldrsb.w r3, [r7, #15] 800f55a: 4611 mov r1, r2 800f55c: 4618 mov r0, r3 800f55e: f7ff ff5f bl 800f420 <__NVIC_SetPriority> } 800f562: bf00 nop 800f564: 3718 adds r7, #24 800f566: 46bd mov sp, r7 800f568: bd80 pop {r7, pc} 0800f56a : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 800f56a: b580 push {r7, lr} 800f56c: b082 sub sp, #8 800f56e: af00 add r7, sp, #0 800f570: 4603 mov r3, r0 800f572: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800f574: f997 3007 ldrsb.w r3, [r7, #7] 800f578: 4618 mov r0, r3 800f57a: f7ff ff35 bl 800f3e8 <__NVIC_EnableIRQ> } 800f57e: bf00 nop 800f580: 3708 adds r7, #8 800f582: 46bd mov sp, r7 800f584: bd80 pop {r7, pc} 0800f586 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800f586: b580 push {r7, lr} 800f588: b082 sub sp, #8 800f58a: af00 add r7, sp, #0 800f58c: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800f58e: 6878 ldr r0, [r7, #4] 800f590: f7ff ffa2 bl 800f4d8 800f594: 4603 mov r3, r0 } 800f596: 4618 mov r0, r3 800f598: 3708 adds r7, #8 800f59a: 46bd mov sp, r7 800f59c: bd80 pop {r7, pc} 0800f59e : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 800f59e: b580 push {r7, lr} 800f5a0: b082 sub sp, #8 800f5a2: af00 add r7, sp, #0 800f5a4: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 800f5a6: 687b ldr r3, [r7, #4] 800f5a8: 2b00 cmp r3, #0 800f5aa: d101 bne.n 800f5b0 { return HAL_ERROR; 800f5ac: 2301 movs r3, #1 800f5ae: e00e b.n 800f5ce } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 800f5b0: 687b ldr r3, [r7, #4] 800f5b2: 795b ldrb r3, [r3, #5] 800f5b4: b2db uxtb r3, r3 800f5b6: 2b00 cmp r3, #0 800f5b8: d105 bne.n 800f5c6 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 800f5ba: 687b ldr r3, [r7, #4] 800f5bc: 2200 movs r2, #0 800f5be: 711a strb r2, [r3, #4] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 800f5c0: 6878 ldr r0, [r7, #4] 800f5c2: f7fa ff27 bl 800a414 } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 800f5c6: 687b ldr r3, [r7, #4] 800f5c8: 2201 movs r2, #1 800f5ca: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 800f5cc: 2300 movs r3, #0 } 800f5ce: 4618 mov r0, r3 800f5d0: 3708 adds r7, #8 800f5d2: 46bd mov sp, r7 800f5d4: bd80 pop {r7, pc} 0800f5d6 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 800f5d6: b480 push {r7} 800f5d8: b085 sub sp, #20 800f5da: af00 add r7, sp, #0 800f5dc: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800f5de: 2300 movs r3, #0 800f5e0: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 800f5e2: 687b ldr r3, [r7, #4] 800f5e4: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800f5e8: b2db uxtb r3, r3 800f5ea: 2b02 cmp r3, #2 800f5ec: d008 beq.n 800f600 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800f5ee: 687b ldr r3, [r7, #4] 800f5f0: 2204 movs r2, #4 800f5f2: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800f5f4: 687b ldr r3, [r7, #4] 800f5f6: 2200 movs r2, #0 800f5f8: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800f5fc: 2301 movs r3, #1 800f5fe: e020 b.n 800f642 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800f600: 687b ldr r3, [r7, #4] 800f602: 681b ldr r3, [r3, #0] 800f604: 681a ldr r2, [r3, #0] 800f606: 687b ldr r3, [r7, #4] 800f608: 681b ldr r3, [r3, #0] 800f60a: f022 020e bic.w r2, r2, #14 800f60e: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800f610: 687b ldr r3, [r7, #4] 800f612: 681b ldr r3, [r3, #0] 800f614: 681a ldr r2, [r3, #0] 800f616: 687b ldr r3, [r7, #4] 800f618: 681b ldr r3, [r3, #0] 800f61a: f022 0201 bic.w r2, r2, #1 800f61e: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 800f620: 687b ldr r3, [r7, #4] 800f622: 6c1a ldr r2, [r3, #64] @ 0x40 800f624: 687b ldr r3, [r7, #4] 800f626: 6bdb ldr r3, [r3, #60] @ 0x3c 800f628: 2101 movs r1, #1 800f62a: fa01 f202 lsl.w r2, r1, r2 800f62e: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800f630: 687b ldr r3, [r7, #4] 800f632: 2201 movs r2, #1 800f634: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800f638: 687b ldr r3, [r7, #4] 800f63a: 2200 movs r2, #0 800f63c: f883 2020 strb.w r2, [r3, #32] return status; 800f640: 7bfb ldrb r3, [r7, #15] } 800f642: 4618 mov r0, r3 800f644: 3714 adds r7, #20 800f646: 46bd mov sp, r7 800f648: bc80 pop {r7} 800f64a: 4770 bx lr 0800f64c : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 800f64c: b580 push {r7, lr} 800f64e: b084 sub sp, #16 800f650: af00 add r7, sp, #0 800f652: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800f654: 2300 movs r3, #0 800f656: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 800f658: 687b ldr r3, [r7, #4] 800f65a: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800f65e: b2db uxtb r3, r3 800f660: 2b02 cmp r3, #2 800f662: d005 beq.n 800f670 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800f664: 687b ldr r3, [r7, #4] 800f666: 2204 movs r2, #4 800f668: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 800f66a: 2301 movs r3, #1 800f66c: 73fb strb r3, [r7, #15] 800f66e: e0d6 b.n 800f81e } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800f670: 687b ldr r3, [r7, #4] 800f672: 681b ldr r3, [r3, #0] 800f674: 681a ldr r2, [r3, #0] 800f676: 687b ldr r3, [r7, #4] 800f678: 681b ldr r3, [r3, #0] 800f67a: f022 020e bic.w r2, r2, #14 800f67e: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800f680: 687b ldr r3, [r7, #4] 800f682: 681b ldr r3, [r3, #0] 800f684: 681a ldr r2, [r3, #0] 800f686: 687b ldr r3, [r7, #4] 800f688: 681b ldr r3, [r3, #0] 800f68a: f022 0201 bic.w r2, r2, #1 800f68e: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 800f690: 687b ldr r3, [r7, #4] 800f692: 681b ldr r3, [r3, #0] 800f694: 461a mov r2, r3 800f696: 4b64 ldr r3, [pc, #400] @ (800f828 ) 800f698: 429a cmp r2, r3 800f69a: d958 bls.n 800f74e 800f69c: 687b ldr r3, [r7, #4] 800f69e: 681b ldr r3, [r3, #0] 800f6a0: 4a62 ldr r2, [pc, #392] @ (800f82c ) 800f6a2: 4293 cmp r3, r2 800f6a4: d04f beq.n 800f746 800f6a6: 687b ldr r3, [r7, #4] 800f6a8: 681b ldr r3, [r3, #0] 800f6aa: 4a61 ldr r2, [pc, #388] @ (800f830 ) 800f6ac: 4293 cmp r3, r2 800f6ae: d048 beq.n 800f742 800f6b0: 687b ldr r3, [r7, #4] 800f6b2: 681b ldr r3, [r3, #0] 800f6b4: 4a5f ldr r2, [pc, #380] @ (800f834 ) 800f6b6: 4293 cmp r3, r2 800f6b8: d040 beq.n 800f73c 800f6ba: 687b ldr r3, [r7, #4] 800f6bc: 681b ldr r3, [r3, #0] 800f6be: 4a5e ldr r2, [pc, #376] @ (800f838 ) 800f6c0: 4293 cmp r3, r2 800f6c2: d038 beq.n 800f736 800f6c4: 687b ldr r3, [r7, #4] 800f6c6: 681b ldr r3, [r3, #0] 800f6c8: 4a5c ldr r2, [pc, #368] @ (800f83c ) 800f6ca: 4293 cmp r3, r2 800f6cc: d030 beq.n 800f730 800f6ce: 687b ldr r3, [r7, #4] 800f6d0: 681b ldr r3, [r3, #0] 800f6d2: 4a5b ldr r2, [pc, #364] @ (800f840 ) 800f6d4: 4293 cmp r3, r2 800f6d6: d028 beq.n 800f72a 800f6d8: 687b ldr r3, [r7, #4] 800f6da: 681b ldr r3, [r3, #0] 800f6dc: 4a52 ldr r2, [pc, #328] @ (800f828 ) 800f6de: 4293 cmp r3, r2 800f6e0: d020 beq.n 800f724 800f6e2: 687b ldr r3, [r7, #4] 800f6e4: 681b ldr r3, [r3, #0] 800f6e6: 4a57 ldr r2, [pc, #348] @ (800f844 ) 800f6e8: 4293 cmp r3, r2 800f6ea: d019 beq.n 800f720 800f6ec: 687b ldr r3, [r7, #4] 800f6ee: 681b ldr r3, [r3, #0] 800f6f0: 4a55 ldr r2, [pc, #340] @ (800f848 ) 800f6f2: 4293 cmp r3, r2 800f6f4: d012 beq.n 800f71c 800f6f6: 687b ldr r3, [r7, #4] 800f6f8: 681b ldr r3, [r3, #0] 800f6fa: 4a54 ldr r2, [pc, #336] @ (800f84c ) 800f6fc: 4293 cmp r3, r2 800f6fe: d00a beq.n 800f716 800f700: 687b ldr r3, [r7, #4] 800f702: 681b ldr r3, [r3, #0] 800f704: 4a52 ldr r2, [pc, #328] @ (800f850 ) 800f706: 4293 cmp r3, r2 800f708: d102 bne.n 800f710 800f70a: f44f 5380 mov.w r3, #4096 @ 0x1000 800f70e: e01b b.n 800f748 800f710: f44f 3380 mov.w r3, #65536 @ 0x10000 800f714: e018 b.n 800f748 800f716: f44f 7380 mov.w r3, #256 @ 0x100 800f71a: e015 b.n 800f748 800f71c: 2310 movs r3, #16 800f71e: e013 b.n 800f748 800f720: 2301 movs r3, #1 800f722: e011 b.n 800f748 800f724: f04f 7380 mov.w r3, #16777216 @ 0x1000000 800f728: e00e b.n 800f748 800f72a: f44f 1380 mov.w r3, #1048576 @ 0x100000 800f72e: e00b b.n 800f748 800f730: f44f 3380 mov.w r3, #65536 @ 0x10000 800f734: e008 b.n 800f748 800f736: f44f 5380 mov.w r3, #4096 @ 0x1000 800f73a: e005 b.n 800f748 800f73c: f44f 7380 mov.w r3, #256 @ 0x100 800f740: e002 b.n 800f748 800f742: 2310 movs r3, #16 800f744: e000 b.n 800f748 800f746: 2301 movs r3, #1 800f748: 4a42 ldr r2, [pc, #264] @ (800f854 ) 800f74a: 6053 str r3, [r2, #4] 800f74c: e057 b.n 800f7fe 800f74e: 687b ldr r3, [r7, #4] 800f750: 681b ldr r3, [r3, #0] 800f752: 4a36 ldr r2, [pc, #216] @ (800f82c ) 800f754: 4293 cmp r3, r2 800f756: d04f beq.n 800f7f8 800f758: 687b ldr r3, [r7, #4] 800f75a: 681b ldr r3, [r3, #0] 800f75c: 4a34 ldr r2, [pc, #208] @ (800f830 ) 800f75e: 4293 cmp r3, r2 800f760: d048 beq.n 800f7f4 800f762: 687b ldr r3, [r7, #4] 800f764: 681b ldr r3, [r3, #0] 800f766: 4a33 ldr r2, [pc, #204] @ (800f834 ) 800f768: 4293 cmp r3, r2 800f76a: d040 beq.n 800f7ee 800f76c: 687b ldr r3, [r7, #4] 800f76e: 681b ldr r3, [r3, #0] 800f770: 4a31 ldr r2, [pc, #196] @ (800f838 ) 800f772: 4293 cmp r3, r2 800f774: d038 beq.n 800f7e8 800f776: 687b ldr r3, [r7, #4] 800f778: 681b ldr r3, [r3, #0] 800f77a: 4a30 ldr r2, [pc, #192] @ (800f83c ) 800f77c: 4293 cmp r3, r2 800f77e: d030 beq.n 800f7e2 800f780: 687b ldr r3, [r7, #4] 800f782: 681b ldr r3, [r3, #0] 800f784: 4a2e ldr r2, [pc, #184] @ (800f840 ) 800f786: 4293 cmp r3, r2 800f788: d028 beq.n 800f7dc 800f78a: 687b ldr r3, [r7, #4] 800f78c: 681b ldr r3, [r3, #0] 800f78e: 4a26 ldr r2, [pc, #152] @ (800f828 ) 800f790: 4293 cmp r3, r2 800f792: d020 beq.n 800f7d6 800f794: 687b ldr r3, [r7, #4] 800f796: 681b ldr r3, [r3, #0] 800f798: 4a2a ldr r2, [pc, #168] @ (800f844 ) 800f79a: 4293 cmp r3, r2 800f79c: d019 beq.n 800f7d2 800f79e: 687b ldr r3, [r7, #4] 800f7a0: 681b ldr r3, [r3, #0] 800f7a2: 4a29 ldr r2, [pc, #164] @ (800f848 ) 800f7a4: 4293 cmp r3, r2 800f7a6: d012 beq.n 800f7ce 800f7a8: 687b ldr r3, [r7, #4] 800f7aa: 681b ldr r3, [r3, #0] 800f7ac: 4a27 ldr r2, [pc, #156] @ (800f84c ) 800f7ae: 4293 cmp r3, r2 800f7b0: d00a beq.n 800f7c8 800f7b2: 687b ldr r3, [r7, #4] 800f7b4: 681b ldr r3, [r3, #0] 800f7b6: 4a26 ldr r2, [pc, #152] @ (800f850 ) 800f7b8: 4293 cmp r3, r2 800f7ba: d102 bne.n 800f7c2 800f7bc: f44f 5380 mov.w r3, #4096 @ 0x1000 800f7c0: e01b b.n 800f7fa 800f7c2: f44f 3380 mov.w r3, #65536 @ 0x10000 800f7c6: e018 b.n 800f7fa 800f7c8: f44f 7380 mov.w r3, #256 @ 0x100 800f7cc: e015 b.n 800f7fa 800f7ce: 2310 movs r3, #16 800f7d0: e013 b.n 800f7fa 800f7d2: 2301 movs r3, #1 800f7d4: e011 b.n 800f7fa 800f7d6: f04f 7380 mov.w r3, #16777216 @ 0x1000000 800f7da: e00e b.n 800f7fa 800f7dc: f44f 1380 mov.w r3, #1048576 @ 0x100000 800f7e0: e00b b.n 800f7fa 800f7e2: f44f 3380 mov.w r3, #65536 @ 0x10000 800f7e6: e008 b.n 800f7fa 800f7e8: f44f 5380 mov.w r3, #4096 @ 0x1000 800f7ec: e005 b.n 800f7fa 800f7ee: f44f 7380 mov.w r3, #256 @ 0x100 800f7f2: e002 b.n 800f7fa 800f7f4: 2310 movs r3, #16 800f7f6: e000 b.n 800f7fa 800f7f8: 2301 movs r3, #1 800f7fa: 4a17 ldr r2, [pc, #92] @ (800f858 ) 800f7fc: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800f7fe: 687b ldr r3, [r7, #4] 800f800: 2201 movs r2, #1 800f802: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800f806: 687b ldr r3, [r7, #4] 800f808: 2200 movs r2, #0 800f80a: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 800f80e: 687b ldr r3, [r7, #4] 800f810: 6b5b ldr r3, [r3, #52] @ 0x34 800f812: 2b00 cmp r3, #0 800f814: d003 beq.n 800f81e { hdma->XferAbortCallback(hdma); 800f816: 687b ldr r3, [r7, #4] 800f818: 6b5b ldr r3, [r3, #52] @ 0x34 800f81a: 6878 ldr r0, [r7, #4] 800f81c: 4798 blx r3 } } return status; 800f81e: 7bfb ldrb r3, [r7, #15] } 800f820: 4618 mov r0, r3 800f822: 3710 adds r7, #16 800f824: 46bd mov sp, r7 800f826: bd80 pop {r7, pc} 800f828: 40020080 .word 0x40020080 800f82c: 40020008 .word 0x40020008 800f830: 4002001c .word 0x4002001c 800f834: 40020030 .word 0x40020030 800f838: 40020044 .word 0x40020044 800f83c: 40020058 .word 0x40020058 800f840: 4002006c .word 0x4002006c 800f844: 40020408 .word 0x40020408 800f848: 4002041c .word 0x4002041c 800f84c: 40020430 .word 0x40020430 800f850: 40020444 .word 0x40020444 800f854: 40020400 .word 0x40020400 800f858: 40020000 .word 0x40020000 0800f85c : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800f85c: b480 push {r7} 800f85e: b08b sub sp, #44 @ 0x2c 800f860: af00 add r7, sp, #0 800f862: 6078 str r0, [r7, #4] 800f864: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 800f866: 2300 movs r3, #0 800f868: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 800f86a: 2300 movs r3, #0 800f86c: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800f86e: e169 b.n 800fb44 { /* Get the IO position */ ioposition = (0x01uL << position); 800f870: 2201 movs r2, #1 800f872: 6a7b ldr r3, [r7, #36] @ 0x24 800f874: fa02 f303 lsl.w r3, r2, r3 800f878: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 800f87a: 683b ldr r3, [r7, #0] 800f87c: 681b ldr r3, [r3, #0] 800f87e: 69fa ldr r2, [r7, #28] 800f880: 4013 ands r3, r2 800f882: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 800f884: 69ba ldr r2, [r7, #24] 800f886: 69fb ldr r3, [r7, #28] 800f888: 429a cmp r2, r3 800f88a: f040 8158 bne.w 800fb3e { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 800f88e: 683b ldr r3, [r7, #0] 800f890: 685b ldr r3, [r3, #4] 800f892: 4a9a ldr r2, [pc, #616] @ (800fafc ) 800f894: 4293 cmp r3, r2 800f896: d05e beq.n 800f956 800f898: 4a98 ldr r2, [pc, #608] @ (800fafc ) 800f89a: 4293 cmp r3, r2 800f89c: d875 bhi.n 800f98a 800f89e: 4a98 ldr r2, [pc, #608] @ (800fb00 ) 800f8a0: 4293 cmp r3, r2 800f8a2: d058 beq.n 800f956 800f8a4: 4a96 ldr r2, [pc, #600] @ (800fb00 ) 800f8a6: 4293 cmp r3, r2 800f8a8: d86f bhi.n 800f98a 800f8aa: 4a96 ldr r2, [pc, #600] @ (800fb04 ) 800f8ac: 4293 cmp r3, r2 800f8ae: d052 beq.n 800f956 800f8b0: 4a94 ldr r2, [pc, #592] @ (800fb04 ) 800f8b2: 4293 cmp r3, r2 800f8b4: d869 bhi.n 800f98a 800f8b6: 4a94 ldr r2, [pc, #592] @ (800fb08 ) 800f8b8: 4293 cmp r3, r2 800f8ba: d04c beq.n 800f956 800f8bc: 4a92 ldr r2, [pc, #584] @ (800fb08 ) 800f8be: 4293 cmp r3, r2 800f8c0: d863 bhi.n 800f98a 800f8c2: 4a92 ldr r2, [pc, #584] @ (800fb0c ) 800f8c4: 4293 cmp r3, r2 800f8c6: d046 beq.n 800f956 800f8c8: 4a90 ldr r2, [pc, #576] @ (800fb0c ) 800f8ca: 4293 cmp r3, r2 800f8cc: d85d bhi.n 800f98a 800f8ce: 2b12 cmp r3, #18 800f8d0: d82a bhi.n 800f928 800f8d2: 2b12 cmp r3, #18 800f8d4: d859 bhi.n 800f98a 800f8d6: a201 add r2, pc, #4 @ (adr r2, 800f8dc ) 800f8d8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800f8dc: 0800f957 .word 0x0800f957 800f8e0: 0800f931 .word 0x0800f931 800f8e4: 0800f943 .word 0x0800f943 800f8e8: 0800f985 .word 0x0800f985 800f8ec: 0800f98b .word 0x0800f98b 800f8f0: 0800f98b .word 0x0800f98b 800f8f4: 0800f98b .word 0x0800f98b 800f8f8: 0800f98b .word 0x0800f98b 800f8fc: 0800f98b .word 0x0800f98b 800f900: 0800f98b .word 0x0800f98b 800f904: 0800f98b .word 0x0800f98b 800f908: 0800f98b .word 0x0800f98b 800f90c: 0800f98b .word 0x0800f98b 800f910: 0800f98b .word 0x0800f98b 800f914: 0800f98b .word 0x0800f98b 800f918: 0800f98b .word 0x0800f98b 800f91c: 0800f98b .word 0x0800f98b 800f920: 0800f939 .word 0x0800f939 800f924: 0800f94d .word 0x0800f94d 800f928: 4a79 ldr r2, [pc, #484] @ (800fb10 ) 800f92a: 4293 cmp r3, r2 800f92c: d013 beq.n 800f956 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 800f92e: e02c b.n 800f98a config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 800f930: 683b ldr r3, [r7, #0] 800f932: 68db ldr r3, [r3, #12] 800f934: 623b str r3, [r7, #32] break; 800f936: e029 b.n 800f98c config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 800f938: 683b ldr r3, [r7, #0] 800f93a: 68db ldr r3, [r3, #12] 800f93c: 3304 adds r3, #4 800f93e: 623b str r3, [r7, #32] break; 800f940: e024 b.n 800f98c config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 800f942: 683b ldr r3, [r7, #0] 800f944: 68db ldr r3, [r3, #12] 800f946: 3308 adds r3, #8 800f948: 623b str r3, [r7, #32] break; 800f94a: e01f b.n 800f98c config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 800f94c: 683b ldr r3, [r7, #0] 800f94e: 68db ldr r3, [r3, #12] 800f950: 330c adds r3, #12 800f952: 623b str r3, [r7, #32] break; 800f954: e01a b.n 800f98c if (GPIO_Init->Pull == GPIO_NOPULL) 800f956: 683b ldr r3, [r7, #0] 800f958: 689b ldr r3, [r3, #8] 800f95a: 2b00 cmp r3, #0 800f95c: d102 bne.n 800f964 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 800f95e: 2304 movs r3, #4 800f960: 623b str r3, [r7, #32] break; 800f962: e013 b.n 800f98c else if (GPIO_Init->Pull == GPIO_PULLUP) 800f964: 683b ldr r3, [r7, #0] 800f966: 689b ldr r3, [r3, #8] 800f968: 2b01 cmp r3, #1 800f96a: d105 bne.n 800f978 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 800f96c: 2308 movs r3, #8 800f96e: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 800f970: 687b ldr r3, [r7, #4] 800f972: 69fa ldr r2, [r7, #28] 800f974: 611a str r2, [r3, #16] break; 800f976: e009 b.n 800f98c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 800f978: 2308 movs r3, #8 800f97a: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 800f97c: 687b ldr r3, [r7, #4] 800f97e: 69fa ldr r2, [r7, #28] 800f980: 615a str r2, [r3, #20] break; 800f982: e003 b.n 800f98c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 800f984: 2300 movs r3, #0 800f986: 623b str r3, [r7, #32] break; 800f988: e000 b.n 800f98c break; 800f98a: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 800f98c: 69bb ldr r3, [r7, #24] 800f98e: 2bff cmp r3, #255 @ 0xff 800f990: d801 bhi.n 800f996 800f992: 687b ldr r3, [r7, #4] 800f994: e001 b.n 800f99a 800f996: 687b ldr r3, [r7, #4] 800f998: 3304 adds r3, #4 800f99a: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 800f99c: 69bb ldr r3, [r7, #24] 800f99e: 2bff cmp r3, #255 @ 0xff 800f9a0: d802 bhi.n 800f9a8 800f9a2: 6a7b ldr r3, [r7, #36] @ 0x24 800f9a4: 009b lsls r3, r3, #2 800f9a6: e002 b.n 800f9ae 800f9a8: 6a7b ldr r3, [r7, #36] @ 0x24 800f9aa: 3b08 subs r3, #8 800f9ac: 009b lsls r3, r3, #2 800f9ae: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 800f9b0: 697b ldr r3, [r7, #20] 800f9b2: 681a ldr r2, [r3, #0] 800f9b4: 210f movs r1, #15 800f9b6: 693b ldr r3, [r7, #16] 800f9b8: fa01 f303 lsl.w r3, r1, r3 800f9bc: 43db mvns r3, r3 800f9be: 401a ands r2, r3 800f9c0: 6a39 ldr r1, [r7, #32] 800f9c2: 693b ldr r3, [r7, #16] 800f9c4: fa01 f303 lsl.w r3, r1, r3 800f9c8: 431a orrs r2, r3 800f9ca: 697b ldr r3, [r7, #20] 800f9cc: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 800f9ce: 683b ldr r3, [r7, #0] 800f9d0: 685b ldr r3, [r3, #4] 800f9d2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800f9d6: 2b00 cmp r3, #0 800f9d8: f000 80b1 beq.w 800fb3e { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 800f9dc: 4b4d ldr r3, [pc, #308] @ (800fb14 ) 800f9de: 699b ldr r3, [r3, #24] 800f9e0: 4a4c ldr r2, [pc, #304] @ (800fb14 ) 800f9e2: f043 0301 orr.w r3, r3, #1 800f9e6: 6193 str r3, [r2, #24] 800f9e8: 4b4a ldr r3, [pc, #296] @ (800fb14 ) 800f9ea: 699b ldr r3, [r3, #24] 800f9ec: f003 0301 and.w r3, r3, #1 800f9f0: 60bb str r3, [r7, #8] 800f9f2: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 800f9f4: 4a48 ldr r2, [pc, #288] @ (800fb18 ) 800f9f6: 6a7b ldr r3, [r7, #36] @ 0x24 800f9f8: 089b lsrs r3, r3, #2 800f9fa: 3302 adds r3, #2 800f9fc: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800fa00: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 800fa02: 6a7b ldr r3, [r7, #36] @ 0x24 800fa04: f003 0303 and.w r3, r3, #3 800fa08: 009b lsls r3, r3, #2 800fa0a: 220f movs r2, #15 800fa0c: fa02 f303 lsl.w r3, r2, r3 800fa10: 43db mvns r3, r3 800fa12: 68fa ldr r2, [r7, #12] 800fa14: 4013 ands r3, r2 800fa16: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 800fa18: 687b ldr r3, [r7, #4] 800fa1a: 4a40 ldr r2, [pc, #256] @ (800fb1c ) 800fa1c: 4293 cmp r3, r2 800fa1e: d013 beq.n 800fa48 800fa20: 687b ldr r3, [r7, #4] 800fa22: 4a3f ldr r2, [pc, #252] @ (800fb20 ) 800fa24: 4293 cmp r3, r2 800fa26: d00d beq.n 800fa44 800fa28: 687b ldr r3, [r7, #4] 800fa2a: 4a3e ldr r2, [pc, #248] @ (800fb24 ) 800fa2c: 4293 cmp r3, r2 800fa2e: d007 beq.n 800fa40 800fa30: 687b ldr r3, [r7, #4] 800fa32: 4a3d ldr r2, [pc, #244] @ (800fb28 ) 800fa34: 4293 cmp r3, r2 800fa36: d101 bne.n 800fa3c 800fa38: 2303 movs r3, #3 800fa3a: e006 b.n 800fa4a 800fa3c: 2304 movs r3, #4 800fa3e: e004 b.n 800fa4a 800fa40: 2302 movs r3, #2 800fa42: e002 b.n 800fa4a 800fa44: 2301 movs r3, #1 800fa46: e000 b.n 800fa4a 800fa48: 2300 movs r3, #0 800fa4a: 6a7a ldr r2, [r7, #36] @ 0x24 800fa4c: f002 0203 and.w r2, r2, #3 800fa50: 0092 lsls r2, r2, #2 800fa52: 4093 lsls r3, r2 800fa54: 68fa ldr r2, [r7, #12] 800fa56: 4313 orrs r3, r2 800fa58: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 800fa5a: 492f ldr r1, [pc, #188] @ (800fb18 ) 800fa5c: 6a7b ldr r3, [r7, #36] @ 0x24 800fa5e: 089b lsrs r3, r3, #2 800fa60: 3302 adds r3, #2 800fa62: 68fa ldr r2, [r7, #12] 800fa64: f841 2023 str.w r2, [r1, r3, lsl #2] /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 800fa68: 683b ldr r3, [r7, #0] 800fa6a: 685b ldr r3, [r3, #4] 800fa6c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800fa70: 2b00 cmp r3, #0 800fa72: d006 beq.n 800fa82 { SET_BIT(EXTI->RTSR, iocurrent); 800fa74: 4b2d ldr r3, [pc, #180] @ (800fb2c ) 800fa76: 689a ldr r2, [r3, #8] 800fa78: 492c ldr r1, [pc, #176] @ (800fb2c ) 800fa7a: 69bb ldr r3, [r7, #24] 800fa7c: 4313 orrs r3, r2 800fa7e: 608b str r3, [r1, #8] 800fa80: e006 b.n 800fa90 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 800fa82: 4b2a ldr r3, [pc, #168] @ (800fb2c ) 800fa84: 689a ldr r2, [r3, #8] 800fa86: 69bb ldr r3, [r7, #24] 800fa88: 43db mvns r3, r3 800fa8a: 4928 ldr r1, [pc, #160] @ (800fb2c ) 800fa8c: 4013 ands r3, r2 800fa8e: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 800fa90: 683b ldr r3, [r7, #0] 800fa92: 685b ldr r3, [r3, #4] 800fa94: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800fa98: 2b00 cmp r3, #0 800fa9a: d006 beq.n 800faaa { SET_BIT(EXTI->FTSR, iocurrent); 800fa9c: 4b23 ldr r3, [pc, #140] @ (800fb2c ) 800fa9e: 68da ldr r2, [r3, #12] 800faa0: 4922 ldr r1, [pc, #136] @ (800fb2c ) 800faa2: 69bb ldr r3, [r7, #24] 800faa4: 4313 orrs r3, r2 800faa6: 60cb str r3, [r1, #12] 800faa8: e006 b.n 800fab8 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 800faaa: 4b20 ldr r3, [pc, #128] @ (800fb2c ) 800faac: 68da ldr r2, [r3, #12] 800faae: 69bb ldr r3, [r7, #24] 800fab0: 43db mvns r3, r3 800fab2: 491e ldr r1, [pc, #120] @ (800fb2c ) 800fab4: 4013 ands r3, r2 800fab6: 60cb str r3, [r1, #12] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 800fab8: 683b ldr r3, [r7, #0] 800faba: 685b ldr r3, [r3, #4] 800fabc: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fac0: 2b00 cmp r3, #0 800fac2: d006 beq.n 800fad2 { SET_BIT(EXTI->EMR, iocurrent); 800fac4: 4b19 ldr r3, [pc, #100] @ (800fb2c ) 800fac6: 685a ldr r2, [r3, #4] 800fac8: 4918 ldr r1, [pc, #96] @ (800fb2c ) 800faca: 69bb ldr r3, [r7, #24] 800facc: 4313 orrs r3, r2 800face: 604b str r3, [r1, #4] 800fad0: e006 b.n 800fae0 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 800fad2: 4b16 ldr r3, [pc, #88] @ (800fb2c ) 800fad4: 685a ldr r2, [r3, #4] 800fad6: 69bb ldr r3, [r7, #24] 800fad8: 43db mvns r3, r3 800fada: 4914 ldr r1, [pc, #80] @ (800fb2c ) 800fadc: 4013 ands r3, r2 800fade: 604b str r3, [r1, #4] } /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 800fae0: 683b ldr r3, [r7, #0] 800fae2: 685b ldr r3, [r3, #4] 800fae4: f403 3380 and.w r3, r3, #65536 @ 0x10000 800fae8: 2b00 cmp r3, #0 800faea: d021 beq.n 800fb30 { SET_BIT(EXTI->IMR, iocurrent); 800faec: 4b0f ldr r3, [pc, #60] @ (800fb2c ) 800faee: 681a ldr r2, [r3, #0] 800faf0: 490e ldr r1, [pc, #56] @ (800fb2c ) 800faf2: 69bb ldr r3, [r7, #24] 800faf4: 4313 orrs r3, r2 800faf6: 600b str r3, [r1, #0] 800faf8: e021 b.n 800fb3e 800fafa: bf00 nop 800fafc: 10320000 .word 0x10320000 800fb00: 10310000 .word 0x10310000 800fb04: 10220000 .word 0x10220000 800fb08: 10210000 .word 0x10210000 800fb0c: 10120000 .word 0x10120000 800fb10: 10110000 .word 0x10110000 800fb14: 40021000 .word 0x40021000 800fb18: 40010000 .word 0x40010000 800fb1c: 40010800 .word 0x40010800 800fb20: 40010c00 .word 0x40010c00 800fb24: 40011000 .word 0x40011000 800fb28: 40011400 .word 0x40011400 800fb2c: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 800fb30: 4b0b ldr r3, [pc, #44] @ (800fb60 ) 800fb32: 681a ldr r2, [r3, #0] 800fb34: 69bb ldr r3, [r7, #24] 800fb36: 43db mvns r3, r3 800fb38: 4909 ldr r1, [pc, #36] @ (800fb60 ) 800fb3a: 4013 ands r3, r2 800fb3c: 600b str r3, [r1, #0] } } } position++; 800fb3e: 6a7b ldr r3, [r7, #36] @ 0x24 800fb40: 3301 adds r3, #1 800fb42: 627b str r3, [r7, #36] @ 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 800fb44: 683b ldr r3, [r7, #0] 800fb46: 681a ldr r2, [r3, #0] 800fb48: 6a7b ldr r3, [r7, #36] @ 0x24 800fb4a: fa22 f303 lsr.w r3, r2, r3 800fb4e: 2b00 cmp r3, #0 800fb50: f47f ae8e bne.w 800f870 } } 800fb54: bf00 nop 800fb56: bf00 nop 800fb58: 372c adds r7, #44 @ 0x2c 800fb5a: 46bd mov sp, r7 800fb5c: bc80 pop {r7} 800fb5e: 4770 bx lr 800fb60: 40010400 .word 0x40010400 0800fb64 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800fb64: b480 push {r7} 800fb66: b085 sub sp, #20 800fb68: af00 add r7, sp, #0 800fb6a: 6078 str r0, [r7, #4] 800fb6c: 460b mov r3, r1 800fb6e: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 800fb70: 687b ldr r3, [r7, #4] 800fb72: 689a ldr r2, [r3, #8] 800fb74: 887b ldrh r3, [r7, #2] 800fb76: 4013 ands r3, r2 800fb78: 2b00 cmp r3, #0 800fb7a: d002 beq.n 800fb82 { bitstatus = GPIO_PIN_SET; 800fb7c: 2301 movs r3, #1 800fb7e: 73fb strb r3, [r7, #15] 800fb80: e001 b.n 800fb86 } else { bitstatus = GPIO_PIN_RESET; 800fb82: 2300 movs r3, #0 800fb84: 73fb strb r3, [r7, #15] } return bitstatus; 800fb86: 7bfb ldrb r3, [r7, #15] } 800fb88: 4618 mov r0, r3 800fb8a: 3714 adds r7, #20 800fb8c: 46bd mov sp, r7 800fb8e: bc80 pop {r7} 800fb90: 4770 bx lr 0800fb92 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800fb92: b480 push {r7} 800fb94: b083 sub sp, #12 800fb96: af00 add r7, sp, #0 800fb98: 6078 str r0, [r7, #4] 800fb9a: 460b mov r3, r1 800fb9c: 807b strh r3, [r7, #2] 800fb9e: 4613 mov r3, r2 800fba0: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800fba2: 787b ldrb r3, [r7, #1] 800fba4: 2b00 cmp r3, #0 800fba6: d003 beq.n 800fbb0 { GPIOx->BSRR = GPIO_Pin; 800fba8: 887a ldrh r2, [r7, #2] 800fbaa: 687b ldr r3, [r7, #4] 800fbac: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 800fbae: e003 b.n 800fbb8 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 800fbb0: 887b ldrh r3, [r7, #2] 800fbb2: 041a lsls r2, r3, #16 800fbb4: 687b ldr r3, [r7, #4] 800fbb6: 611a str r2, [r3, #16] } 800fbb8: bf00 nop 800fbba: 370c adds r7, #12 800fbbc: 46bd mov sp, r7 800fbbe: bc80 pop {r7} 800fbc0: 4770 bx lr ... 0800fbc4 : * @note If the HSE divided by 128 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 800fbc4: b480 push {r7} 800fbc6: af00 add r7, sp, #0 /* Enable access to RTC and backup registers */ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 800fbc8: 4b03 ldr r3, [pc, #12] @ (800fbd8 ) 800fbca: 2201 movs r2, #1 800fbcc: 601a str r2, [r3, #0] } 800fbce: bf00 nop 800fbd0: 46bd mov sp, r7 800fbd2: bc80 pop {r7} 800fbd4: 4770 bx lr 800fbd6: bf00 nop 800fbd8: 420e0020 .word 0x420e0020 0800fbdc : * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval HAL_StatusTypeDef */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { 800fbdc: b580 push {r7, lr} 800fbde: b082 sub sp, #8 800fbe0: af00 add r7, sp, #0 uint32_t tickstart; /* Get Start Tick */ tickstart = HAL_GetTick(); 800fbe2: f7fd ffc5 bl 800db70 800fbe6: 6078 str r0, [r7, #4] /* Set HSION bit */ SET_BIT(RCC->CR, RCC_CR_HSION); 800fbe8: 4b60 ldr r3, [pc, #384] @ (800fd6c ) 800fbea: 681b ldr r3, [r3, #0] 800fbec: 4a5f ldr r2, [pc, #380] @ (800fd6c ) 800fbee: f043 0301 orr.w r3, r3, #1 800fbf2: 6013 str r3, [r2, #0] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 800fbf4: e008 b.n 800fc08 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800fbf6: f7fd ffbb bl 800db70 800fbfa: 4602 mov r2, r0 800fbfc: 687b ldr r3, [r7, #4] 800fbfe: 1ad3 subs r3, r2, r3 800fc00: 2b02 cmp r3, #2 800fc02: d901 bls.n 800fc08 { return HAL_TIMEOUT; 800fc04: 2303 movs r3, #3 800fc06: e0ac b.n 800fd62 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 800fc08: 4b58 ldr r3, [pc, #352] @ (800fd6c ) 800fc0a: 681b ldr r3, [r3, #0] 800fc0c: f003 0302 and.w r3, r3, #2 800fc10: 2b00 cmp r3, #0 800fc12: d0f0 beq.n 800fbf6 } } /* Set HSITRIM bits to the reset value */ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); 800fc14: 4b55 ldr r3, [pc, #340] @ (800fd6c ) 800fc16: 681b ldr r3, [r3, #0] 800fc18: f023 03f8 bic.w r3, r3, #248 @ 0xf8 800fc1c: 4a53 ldr r2, [pc, #332] @ (800fd6c ) 800fc1e: f043 0380 orr.w r3, r3, #128 @ 0x80 800fc22: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800fc24: f7fd ffa4 bl 800db70 800fc28: 6078 str r0, [r7, #4] /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); 800fc2a: 4b50 ldr r3, [pc, #320] @ (800fd6c ) 800fc2c: 2200 movs r2, #0 800fc2e: 605a str r2, [r3, #4] /* Wait till clock switch is ready */ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 800fc30: e00a b.n 800fc48 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800fc32: f7fd ff9d bl 800db70 800fc36: 4602 mov r2, r0 800fc38: 687b ldr r3, [r7, #4] 800fc3a: 1ad3 subs r3, r2, r3 800fc3c: f241 3288 movw r2, #5000 @ 0x1388 800fc40: 4293 cmp r3, r2 800fc42: d901 bls.n 800fc48 { return HAL_TIMEOUT; 800fc44: 2303 movs r3, #3 800fc46: e08c b.n 800fd62 while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 800fc48: 4b48 ldr r3, [pc, #288] @ (800fd6c ) 800fc4a: 685b ldr r3, [r3, #4] 800fc4c: f003 030c and.w r3, r3, #12 800fc50: 2b00 cmp r3, #0 800fc52: d1ee bne.n 800fc32 } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; 800fc54: 4b46 ldr r3, [pc, #280] @ (800fd70 ) 800fc56: 4a47 ldr r2, [pc, #284] @ (800fd74 ) 800fc58: 601a str r2, [r3, #0] /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 800fc5a: 4b47 ldr r3, [pc, #284] @ (800fd78 ) 800fc5c: 681b ldr r3, [r3, #0] 800fc5e: 4618 mov r0, r3 800fc60: f7fd ff44 bl 800daec 800fc64: 4603 mov r3, r0 800fc66: 2b00 cmp r3, #0 800fc68: d001 beq.n 800fc6e { return HAL_ERROR; 800fc6a: 2301 movs r3, #1 800fc6c: e079 b.n 800fd62 } /* Get Start Tick */ tickstart = HAL_GetTick(); 800fc6e: f7fd ff7f bl 800db70 800fc72: 6078 str r0, [r7, #4] /* Second step is to clear PLLON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 800fc74: 4b3d ldr r3, [pc, #244] @ (800fd6c ) 800fc76: 681b ldr r3, [r3, #0] 800fc78: 4a3c ldr r2, [pc, #240] @ (800fd6c ) 800fc7a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800fc7e: 6013 str r3, [r2, #0] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 800fc80: e008 b.n 800fc94 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800fc82: f7fd ff75 bl 800db70 800fc86: 4602 mov r2, r0 800fc88: 687b ldr r3, [r7, #4] 800fc8a: 1ad3 subs r3, r2, r3 800fc8c: 2b02 cmp r3, #2 800fc8e: d901 bls.n 800fc94 { return HAL_TIMEOUT; 800fc90: 2303 movs r3, #3 800fc92: e066 b.n 800fd62 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 800fc94: 4b35 ldr r3, [pc, #212] @ (800fd6c ) 800fc96: 681b ldr r3, [r3, #0] 800fc98: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800fc9c: 2b00 cmp r3, #0 800fc9e: d1f0 bne.n 800fc82 } } /* Ensure to reset PLLSRC and PLLMUL bits */ CLEAR_REG(RCC->CFGR); 800fca0: 4b32 ldr r3, [pc, #200] @ (800fd6c ) 800fca2: 2200 movs r2, #0 800fca4: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 800fca6: f7fd ff63 bl 800db70 800fcaa: 6078 str r0, [r7, #4] /* Reset HSEON & CSSON bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON); 800fcac: 4b2f ldr r3, [pc, #188] @ (800fd6c ) 800fcae: 681b ldr r3, [r3, #0] 800fcb0: 4a2e ldr r2, [pc, #184] @ (800fd6c ) 800fcb2: f423 2310 bic.w r3, r3, #589824 @ 0x90000 800fcb6: 6013 str r3, [r2, #0] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 800fcb8: e008 b.n 800fccc { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800fcba: f7fd ff59 bl 800db70 800fcbe: 4602 mov r2, r0 800fcc0: 687b ldr r3, [r7, #4] 800fcc2: 1ad3 subs r3, r2, r3 800fcc4: 2b64 cmp r3, #100 @ 0x64 800fcc6: d901 bls.n 800fccc { return HAL_TIMEOUT; 800fcc8: 2303 movs r3, #3 800fcca: e04a b.n 800fd62 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 800fccc: 4b27 ldr r3, [pc, #156] @ (800fd6c ) 800fcce: 681b ldr r3, [r3, #0] 800fcd0: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fcd4: 2b00 cmp r3, #0 800fcd6: d1f0 bne.n 800fcba } } /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 800fcd8: 4b24 ldr r3, [pc, #144] @ (800fd6c ) 800fcda: 681b ldr r3, [r3, #0] 800fcdc: 4a23 ldr r2, [pc, #140] @ (800fd6c ) 800fcde: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800fce2: 6013 str r3, [r2, #0] #if defined(RCC_PLL2_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 800fce4: f7fd ff44 bl 800db70 800fce8: 6078 str r0, [r7, #4] /* Clear PLL2ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); 800fcea: 4b20 ldr r3, [pc, #128] @ (800fd6c ) 800fcec: 681b ldr r3, [r3, #0] 800fcee: 4a1f ldr r2, [pc, #124] @ (800fd6c ) 800fcf0: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800fcf4: 6013 str r3, [r2, #0] /* Wait till PLL2 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 800fcf6: e008 b.n 800fd0a { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800fcf8: f7fd ff3a bl 800db70 800fcfc: 4602 mov r2, r0 800fcfe: 687b ldr r3, [r7, #4] 800fd00: 1ad3 subs r3, r2, r3 800fd02: 2b64 cmp r3, #100 @ 0x64 800fd04: d901 bls.n 800fd0a { return HAL_TIMEOUT; 800fd06: 2303 movs r3, #3 800fd08: e02b b.n 800fd62 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 800fd0a: 4b18 ldr r3, [pc, #96] @ (800fd6c ) 800fd0c: 681b ldr r3, [r3, #0] 800fd0e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800fd12: 2b00 cmp r3, #0 800fd14: d1f0 bne.n 800fcf8 } #endif /* RCC_PLL2_SUPPORT */ #if defined(RCC_PLLI2S_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 800fd16: f7fd ff2b bl 800db70 800fd1a: 6078 str r0, [r7, #4] /* Clear PLL3ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); 800fd1c: 4b13 ldr r3, [pc, #76] @ (800fd6c ) 800fd1e: 681b ldr r3, [r3, #0] 800fd20: 4a12 ldr r2, [pc, #72] @ (800fd6c ) 800fd22: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800fd26: 6013 str r3, [r2, #0] /* Wait till PLL3 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 800fd28: e008 b.n 800fd3c { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 800fd2a: f7fd ff21 bl 800db70 800fd2e: 4602 mov r2, r0 800fd30: 687b ldr r3, [r7, #4] 800fd32: 1ad3 subs r3, r2, r3 800fd34: 2b64 cmp r3, #100 @ 0x64 800fd36: d901 bls.n 800fd3c { return HAL_TIMEOUT; 800fd38: 2303 movs r3, #3 800fd3a: e012 b.n 800fd62 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 800fd3c: 4b0b ldr r3, [pc, #44] @ (800fd6c ) 800fd3e: 681b ldr r3, [r3, #0] 800fd40: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800fd44: 2b00 cmp r3, #0 800fd46: d1f0 bne.n 800fd2a } #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_CFGR2_PREDIV1) /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); 800fd48: 4b08 ldr r3, [pc, #32] @ (800fd6c ) 800fd4a: 2200 movs r2, #0 800fd4c: 62da str r2, [r3, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1 */ /* Reset all CSR flags */ SET_BIT(RCC->CSR, RCC_CSR_RMVF); 800fd4e: 4b07 ldr r3, [pc, #28] @ (800fd6c ) 800fd50: 6a5b ldr r3, [r3, #36] @ 0x24 800fd52: 4a06 ldr r2, [pc, #24] @ (800fd6c ) 800fd54: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800fd58: 6253 str r3, [r2, #36] @ 0x24 /* Disable all interrupts */ CLEAR_REG(RCC->CIR); 800fd5a: 4b04 ldr r3, [pc, #16] @ (800fd6c ) 800fd5c: 2200 movs r2, #0 800fd5e: 609a str r2, [r3, #8] return HAL_OK; 800fd60: 2300 movs r3, #0 } 800fd62: 4618 mov r0, r3 800fd64: 3708 adds r7, #8 800fd66: 46bd mov sp, r7 800fd68: bd80 pop {r7, pc} 800fd6a: bf00 nop 800fd6c: 40021000 .word 0x40021000 800fd70: 2000006c .word 0x2000006c 800fd74: 007a1200 .word 0x007a1200 800fd78: 20000070 .word 0x20000070 0800fd7c : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800fd7c: b580 push {r7, lr} 800fd7e: b086 sub sp, #24 800fd80: af00 add r7, sp, #0 800fd82: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 800fd84: 687b ldr r3, [r7, #4] 800fd86: 2b00 cmp r3, #0 800fd88: d101 bne.n 800fd8e { return HAL_ERROR; 800fd8a: 2301 movs r3, #1 800fd8c: e304 b.n 8010398 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800fd8e: 687b ldr r3, [r7, #4] 800fd90: 681b ldr r3, [r3, #0] 800fd92: f003 0301 and.w r3, r3, #1 800fd96: 2b00 cmp r3, #0 800fd98: f000 8087 beq.w 800feaa { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 800fd9c: 4b92 ldr r3, [pc, #584] @ (800ffe8 ) 800fd9e: 685b ldr r3, [r3, #4] 800fda0: f003 030c and.w r3, r3, #12 800fda4: 2b04 cmp r3, #4 800fda6: d00c beq.n 800fdc2 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 800fda8: 4b8f ldr r3, [pc, #572] @ (800ffe8 ) 800fdaa: 685b ldr r3, [r3, #4] 800fdac: f003 030c and.w r3, r3, #12 800fdb0: 2b08 cmp r3, #8 800fdb2: d112 bne.n 800fdda 800fdb4: 4b8c ldr r3, [pc, #560] @ (800ffe8 ) 800fdb6: 685b ldr r3, [r3, #4] 800fdb8: f403 3380 and.w r3, r3, #65536 @ 0x10000 800fdbc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800fdc0: d10b bne.n 800fdda { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800fdc2: 4b89 ldr r3, [pc, #548] @ (800ffe8 ) 800fdc4: 681b ldr r3, [r3, #0] 800fdc6: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fdca: 2b00 cmp r3, #0 800fdcc: d06c beq.n 800fea8 800fdce: 687b ldr r3, [r7, #4] 800fdd0: 689b ldr r3, [r3, #8] 800fdd2: 2b00 cmp r3, #0 800fdd4: d168 bne.n 800fea8 { return HAL_ERROR; 800fdd6: 2301 movs r3, #1 800fdd8: e2de b.n 8010398 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800fdda: 687b ldr r3, [r7, #4] 800fddc: 689b ldr r3, [r3, #8] 800fdde: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800fde2: d106 bne.n 800fdf2 800fde4: 4b80 ldr r3, [pc, #512] @ (800ffe8 ) 800fde6: 681b ldr r3, [r3, #0] 800fde8: 4a7f ldr r2, [pc, #508] @ (800ffe8 ) 800fdea: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800fdee: 6013 str r3, [r2, #0] 800fdf0: e02e b.n 800fe50 800fdf2: 687b ldr r3, [r7, #4] 800fdf4: 689b ldr r3, [r3, #8] 800fdf6: 2b00 cmp r3, #0 800fdf8: d10c bne.n 800fe14 800fdfa: 4b7b ldr r3, [pc, #492] @ (800ffe8 ) 800fdfc: 681b ldr r3, [r3, #0] 800fdfe: 4a7a ldr r2, [pc, #488] @ (800ffe8 ) 800fe00: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800fe04: 6013 str r3, [r2, #0] 800fe06: 4b78 ldr r3, [pc, #480] @ (800ffe8 ) 800fe08: 681b ldr r3, [r3, #0] 800fe0a: 4a77 ldr r2, [pc, #476] @ (800ffe8 ) 800fe0c: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800fe10: 6013 str r3, [r2, #0] 800fe12: e01d b.n 800fe50 800fe14: 687b ldr r3, [r7, #4] 800fe16: 689b ldr r3, [r3, #8] 800fe18: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800fe1c: d10c bne.n 800fe38 800fe1e: 4b72 ldr r3, [pc, #456] @ (800ffe8 ) 800fe20: 681b ldr r3, [r3, #0] 800fe22: 4a71 ldr r2, [pc, #452] @ (800ffe8 ) 800fe24: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800fe28: 6013 str r3, [r2, #0] 800fe2a: 4b6f ldr r3, [pc, #444] @ (800ffe8 ) 800fe2c: 681b ldr r3, [r3, #0] 800fe2e: 4a6e ldr r2, [pc, #440] @ (800ffe8 ) 800fe30: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800fe34: 6013 str r3, [r2, #0] 800fe36: e00b b.n 800fe50 800fe38: 4b6b ldr r3, [pc, #428] @ (800ffe8 ) 800fe3a: 681b ldr r3, [r3, #0] 800fe3c: 4a6a ldr r2, [pc, #424] @ (800ffe8 ) 800fe3e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800fe42: 6013 str r3, [r2, #0] 800fe44: 4b68 ldr r3, [pc, #416] @ (800ffe8 ) 800fe46: 681b ldr r3, [r3, #0] 800fe48: 4a67 ldr r2, [pc, #412] @ (800ffe8 ) 800fe4a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800fe4e: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 800fe50: 687b ldr r3, [r7, #4] 800fe52: 689b ldr r3, [r3, #8] 800fe54: 2b00 cmp r3, #0 800fe56: d013 beq.n 800fe80 { /* Get Start Tick */ tickstart = HAL_GetTick(); 800fe58: f7fd fe8a bl 800db70 800fe5c: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800fe5e: e008 b.n 800fe72 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800fe60: f7fd fe86 bl 800db70 800fe64: 4602 mov r2, r0 800fe66: 693b ldr r3, [r7, #16] 800fe68: 1ad3 subs r3, r2, r3 800fe6a: 2b64 cmp r3, #100 @ 0x64 800fe6c: d901 bls.n 800fe72 { return HAL_TIMEOUT; 800fe6e: 2303 movs r3, #3 800fe70: e292 b.n 8010398 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800fe72: 4b5d ldr r3, [pc, #372] @ (800ffe8 ) 800fe74: 681b ldr r3, [r3, #0] 800fe76: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fe7a: 2b00 cmp r3, #0 800fe7c: d0f0 beq.n 800fe60 800fe7e: e014 b.n 800feaa } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 800fe80: f7fd fe76 bl 800db70 800fe84: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800fe86: e008 b.n 800fe9a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800fe88: f7fd fe72 bl 800db70 800fe8c: 4602 mov r2, r0 800fe8e: 693b ldr r3, [r7, #16] 800fe90: 1ad3 subs r3, r2, r3 800fe92: 2b64 cmp r3, #100 @ 0x64 800fe94: d901 bls.n 800fe9a { return HAL_TIMEOUT; 800fe96: 2303 movs r3, #3 800fe98: e27e b.n 8010398 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800fe9a: 4b53 ldr r3, [pc, #332] @ (800ffe8 ) 800fe9c: 681b ldr r3, [r3, #0] 800fe9e: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fea2: 2b00 cmp r3, #0 800fea4: d1f0 bne.n 800fe88 800fea6: e000 b.n 800feaa if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800fea8: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800feaa: 687b ldr r3, [r7, #4] 800feac: 681b ldr r3, [r3, #0] 800feae: f003 0302 and.w r3, r3, #2 800feb2: 2b00 cmp r3, #0 800feb4: d063 beq.n 800ff7e /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 800feb6: 4b4c ldr r3, [pc, #304] @ (800ffe8 ) 800feb8: 685b ldr r3, [r3, #4] 800feba: f003 030c and.w r3, r3, #12 800febe: 2b00 cmp r3, #0 800fec0: d00b beq.n 800feda || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 800fec2: 4b49 ldr r3, [pc, #292] @ (800ffe8 ) 800fec4: 685b ldr r3, [r3, #4] 800fec6: f003 030c and.w r3, r3, #12 800feca: 2b08 cmp r3, #8 800fecc: d11c bne.n 800ff08 800fece: 4b46 ldr r3, [pc, #280] @ (800ffe8 ) 800fed0: 685b ldr r3, [r3, #4] 800fed2: f403 3380 and.w r3, r3, #65536 @ 0x10000 800fed6: 2b00 cmp r3, #0 800fed8: d116 bne.n 800ff08 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800feda: 4b43 ldr r3, [pc, #268] @ (800ffe8 ) 800fedc: 681b ldr r3, [r3, #0] 800fede: f003 0302 and.w r3, r3, #2 800fee2: 2b00 cmp r3, #0 800fee4: d005 beq.n 800fef2 800fee6: 687b ldr r3, [r7, #4] 800fee8: 695b ldr r3, [r3, #20] 800feea: 2b01 cmp r3, #1 800feec: d001 beq.n 800fef2 { return HAL_ERROR; 800feee: 2301 movs r3, #1 800fef0: e252 b.n 8010398 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800fef2: 4b3d ldr r3, [pc, #244] @ (800ffe8 ) 800fef4: 681b ldr r3, [r3, #0] 800fef6: f023 02f8 bic.w r2, r3, #248 @ 0xf8 800fefa: 687b ldr r3, [r7, #4] 800fefc: 699b ldr r3, [r3, #24] 800fefe: 00db lsls r3, r3, #3 800ff00: 4939 ldr r1, [pc, #228] @ (800ffe8 ) 800ff02: 4313 orrs r3, r2 800ff04: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800ff06: e03a b.n 800ff7e } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 800ff08: 687b ldr r3, [r7, #4] 800ff0a: 695b ldr r3, [r3, #20] 800ff0c: 2b00 cmp r3, #0 800ff0e: d020 beq.n 800ff52 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 800ff10: 4b36 ldr r3, [pc, #216] @ (800ffec ) 800ff12: 2201 movs r2, #1 800ff14: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800ff16: f7fd fe2b bl 800db70 800ff1a: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800ff1c: e008 b.n 800ff30 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800ff1e: f7fd fe27 bl 800db70 800ff22: 4602 mov r2, r0 800ff24: 693b ldr r3, [r7, #16] 800ff26: 1ad3 subs r3, r2, r3 800ff28: 2b02 cmp r3, #2 800ff2a: d901 bls.n 800ff30 { return HAL_TIMEOUT; 800ff2c: 2303 movs r3, #3 800ff2e: e233 b.n 8010398 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800ff30: 4b2d ldr r3, [pc, #180] @ (800ffe8 ) 800ff32: 681b ldr r3, [r3, #0] 800ff34: f003 0302 and.w r3, r3, #2 800ff38: 2b00 cmp r3, #0 800ff3a: d0f0 beq.n 800ff1e } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800ff3c: 4b2a ldr r3, [pc, #168] @ (800ffe8 ) 800ff3e: 681b ldr r3, [r3, #0] 800ff40: f023 02f8 bic.w r2, r3, #248 @ 0xf8 800ff44: 687b ldr r3, [r7, #4] 800ff46: 699b ldr r3, [r3, #24] 800ff48: 00db lsls r3, r3, #3 800ff4a: 4927 ldr r1, [pc, #156] @ (800ffe8 ) 800ff4c: 4313 orrs r3, r2 800ff4e: 600b str r3, [r1, #0] 800ff50: e015 b.n 800ff7e } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800ff52: 4b26 ldr r3, [pc, #152] @ (800ffec ) 800ff54: 2200 movs r2, #0 800ff56: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800ff58: f7fd fe0a bl 800db70 800ff5c: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800ff5e: e008 b.n 800ff72 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800ff60: f7fd fe06 bl 800db70 800ff64: 4602 mov r2, r0 800ff66: 693b ldr r3, [r7, #16] 800ff68: 1ad3 subs r3, r2, r3 800ff6a: 2b02 cmp r3, #2 800ff6c: d901 bls.n 800ff72 { return HAL_TIMEOUT; 800ff6e: 2303 movs r3, #3 800ff70: e212 b.n 8010398 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800ff72: 4b1d ldr r3, [pc, #116] @ (800ffe8 ) 800ff74: 681b ldr r3, [r3, #0] 800ff76: f003 0302 and.w r3, r3, #2 800ff7a: 2b00 cmp r3, #0 800ff7c: d1f0 bne.n 800ff60 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800ff7e: 687b ldr r3, [r7, #4] 800ff80: 681b ldr r3, [r3, #0] 800ff82: f003 0308 and.w r3, r3, #8 800ff86: 2b00 cmp r3, #0 800ff88: d03a beq.n 8010000 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 800ff8a: 687b ldr r3, [r7, #4] 800ff8c: 69db ldr r3, [r3, #28] 800ff8e: 2b00 cmp r3, #0 800ff90: d019 beq.n 800ffc6 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800ff92: 4b17 ldr r3, [pc, #92] @ (800fff0 ) 800ff94: 2201 movs r2, #1 800ff96: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800ff98: f7fd fdea bl 800db70 800ff9c: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800ff9e: e008 b.n 800ffb2 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800ffa0: f7fd fde6 bl 800db70 800ffa4: 4602 mov r2, r0 800ffa6: 693b ldr r3, [r7, #16] 800ffa8: 1ad3 subs r3, r2, r3 800ffaa: 2b02 cmp r3, #2 800ffac: d901 bls.n 800ffb2 { return HAL_TIMEOUT; 800ffae: 2303 movs r3, #3 800ffb0: e1f2 b.n 8010398 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800ffb2: 4b0d ldr r3, [pc, #52] @ (800ffe8 ) 800ffb4: 6a5b ldr r3, [r3, #36] @ 0x24 800ffb6: f003 0302 and.w r3, r3, #2 800ffba: 2b00 cmp r3, #0 800ffbc: d0f0 beq.n 800ffa0 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 800ffbe: 2001 movs r0, #1 800ffc0: f000 fbca bl 8010758 800ffc4: e01c b.n 8010000 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800ffc6: 4b0a ldr r3, [pc, #40] @ (800fff0 ) 800ffc8: 2200 movs r2, #0 800ffca: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800ffcc: f7fd fdd0 bl 800db70 800ffd0: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800ffd2: e00f b.n 800fff4 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800ffd4: f7fd fdcc bl 800db70 800ffd8: 4602 mov r2, r0 800ffda: 693b ldr r3, [r7, #16] 800ffdc: 1ad3 subs r3, r2, r3 800ffde: 2b02 cmp r3, #2 800ffe0: d908 bls.n 800fff4 { return HAL_TIMEOUT; 800ffe2: 2303 movs r3, #3 800ffe4: e1d8 b.n 8010398 800ffe6: bf00 nop 800ffe8: 40021000 .word 0x40021000 800ffec: 42420000 .word 0x42420000 800fff0: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800fff4: 4b9b ldr r3, [pc, #620] @ (8010264 ) 800fff6: 6a5b ldr r3, [r3, #36] @ 0x24 800fff8: f003 0302 and.w r3, r3, #2 800fffc: 2b00 cmp r3, #0 800fffe: d1e9 bne.n 800ffd4 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8010000: 687b ldr r3, [r7, #4] 8010002: 681b ldr r3, [r3, #0] 8010004: f003 0304 and.w r3, r3, #4 8010008: 2b00 cmp r3, #0 801000a: f000 80a6 beq.w 801015a { FlagStatus pwrclkchanged = RESET; 801000e: 2300 movs r3, #0 8010010: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8010012: 4b94 ldr r3, [pc, #592] @ (8010264 ) 8010014: 69db ldr r3, [r3, #28] 8010016: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 801001a: 2b00 cmp r3, #0 801001c: d10d bne.n 801003a { __HAL_RCC_PWR_CLK_ENABLE(); 801001e: 4b91 ldr r3, [pc, #580] @ (8010264 ) 8010020: 69db ldr r3, [r3, #28] 8010022: 4a90 ldr r2, [pc, #576] @ (8010264 ) 8010024: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8010028: 61d3 str r3, [r2, #28] 801002a: 4b8e ldr r3, [pc, #568] @ (8010264 ) 801002c: 69db ldr r3, [r3, #28] 801002e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010032: 60bb str r3, [r7, #8] 8010034: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8010036: 2301 movs r3, #1 8010038: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 801003a: 4b8b ldr r3, [pc, #556] @ (8010268 ) 801003c: 681b ldr r3, [r3, #0] 801003e: f403 7380 and.w r3, r3, #256 @ 0x100 8010042: 2b00 cmp r3, #0 8010044: d118 bne.n 8010078 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8010046: 4b88 ldr r3, [pc, #544] @ (8010268 ) 8010048: 681b ldr r3, [r3, #0] 801004a: 4a87 ldr r2, [pc, #540] @ (8010268 ) 801004c: f443 7380 orr.w r3, r3, #256 @ 0x100 8010050: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8010052: f7fd fd8d bl 800db70 8010056: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010058: e008 b.n 801006c { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 801005a: f7fd fd89 bl 800db70 801005e: 4602 mov r2, r0 8010060: 693b ldr r3, [r7, #16] 8010062: 1ad3 subs r3, r2, r3 8010064: 2b64 cmp r3, #100 @ 0x64 8010066: d901 bls.n 801006c { return HAL_TIMEOUT; 8010068: 2303 movs r3, #3 801006a: e195 b.n 8010398 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 801006c: 4b7e ldr r3, [pc, #504] @ (8010268 ) 801006e: 681b ldr r3, [r3, #0] 8010070: f403 7380 and.w r3, r3, #256 @ 0x100 8010074: 2b00 cmp r3, #0 8010076: d0f0 beq.n 801005a } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8010078: 687b ldr r3, [r7, #4] 801007a: 691b ldr r3, [r3, #16] 801007c: 2b01 cmp r3, #1 801007e: d106 bne.n 801008e 8010080: 4b78 ldr r3, [pc, #480] @ (8010264 ) 8010082: 6a1b ldr r3, [r3, #32] 8010084: 4a77 ldr r2, [pc, #476] @ (8010264 ) 8010086: f043 0301 orr.w r3, r3, #1 801008a: 6213 str r3, [r2, #32] 801008c: e02d b.n 80100ea 801008e: 687b ldr r3, [r7, #4] 8010090: 691b ldr r3, [r3, #16] 8010092: 2b00 cmp r3, #0 8010094: d10c bne.n 80100b0 8010096: 4b73 ldr r3, [pc, #460] @ (8010264 ) 8010098: 6a1b ldr r3, [r3, #32] 801009a: 4a72 ldr r2, [pc, #456] @ (8010264 ) 801009c: f023 0301 bic.w r3, r3, #1 80100a0: 6213 str r3, [r2, #32] 80100a2: 4b70 ldr r3, [pc, #448] @ (8010264 ) 80100a4: 6a1b ldr r3, [r3, #32] 80100a6: 4a6f ldr r2, [pc, #444] @ (8010264 ) 80100a8: f023 0304 bic.w r3, r3, #4 80100ac: 6213 str r3, [r2, #32] 80100ae: e01c b.n 80100ea 80100b0: 687b ldr r3, [r7, #4] 80100b2: 691b ldr r3, [r3, #16] 80100b4: 2b05 cmp r3, #5 80100b6: d10c bne.n 80100d2 80100b8: 4b6a ldr r3, [pc, #424] @ (8010264 ) 80100ba: 6a1b ldr r3, [r3, #32] 80100bc: 4a69 ldr r2, [pc, #420] @ (8010264 ) 80100be: f043 0304 orr.w r3, r3, #4 80100c2: 6213 str r3, [r2, #32] 80100c4: 4b67 ldr r3, [pc, #412] @ (8010264 ) 80100c6: 6a1b ldr r3, [r3, #32] 80100c8: 4a66 ldr r2, [pc, #408] @ (8010264 ) 80100ca: f043 0301 orr.w r3, r3, #1 80100ce: 6213 str r3, [r2, #32] 80100d0: e00b b.n 80100ea 80100d2: 4b64 ldr r3, [pc, #400] @ (8010264 ) 80100d4: 6a1b ldr r3, [r3, #32] 80100d6: 4a63 ldr r2, [pc, #396] @ (8010264 ) 80100d8: f023 0301 bic.w r3, r3, #1 80100dc: 6213 str r3, [r2, #32] 80100de: 4b61 ldr r3, [pc, #388] @ (8010264 ) 80100e0: 6a1b ldr r3, [r3, #32] 80100e2: 4a60 ldr r2, [pc, #384] @ (8010264 ) 80100e4: f023 0304 bic.w r3, r3, #4 80100e8: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 80100ea: 687b ldr r3, [r7, #4] 80100ec: 691b ldr r3, [r3, #16] 80100ee: 2b00 cmp r3, #0 80100f0: d015 beq.n 801011e { /* Get Start Tick */ tickstart = HAL_GetTick(); 80100f2: f7fd fd3d bl 800db70 80100f6: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80100f8: e00a b.n 8010110 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80100fa: f7fd fd39 bl 800db70 80100fe: 4602 mov r2, r0 8010100: 693b ldr r3, [r7, #16] 8010102: 1ad3 subs r3, r2, r3 8010104: f241 3288 movw r2, #5000 @ 0x1388 8010108: 4293 cmp r3, r2 801010a: d901 bls.n 8010110 { return HAL_TIMEOUT; 801010c: 2303 movs r3, #3 801010e: e143 b.n 8010398 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8010110: 4b54 ldr r3, [pc, #336] @ (8010264 ) 8010112: 6a1b ldr r3, [r3, #32] 8010114: f003 0302 and.w r3, r3, #2 8010118: 2b00 cmp r3, #0 801011a: d0ee beq.n 80100fa 801011c: e014 b.n 8010148 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 801011e: f7fd fd27 bl 800db70 8010122: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8010124: e00a b.n 801013c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8010126: f7fd fd23 bl 800db70 801012a: 4602 mov r2, r0 801012c: 693b ldr r3, [r7, #16] 801012e: 1ad3 subs r3, r2, r3 8010130: f241 3288 movw r2, #5000 @ 0x1388 8010134: 4293 cmp r3, r2 8010136: d901 bls.n 801013c { return HAL_TIMEOUT; 8010138: 2303 movs r3, #3 801013a: e12d b.n 8010398 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 801013c: 4b49 ldr r3, [pc, #292] @ (8010264 ) 801013e: 6a1b ldr r3, [r3, #32] 8010140: f003 0302 and.w r3, r3, #2 8010144: 2b00 cmp r3, #0 8010146: d1ee bne.n 8010126 } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8010148: 7dfb ldrb r3, [r7, #23] 801014a: 2b01 cmp r3, #1 801014c: d105 bne.n 801015a { __HAL_RCC_PWR_CLK_DISABLE(); 801014e: 4b45 ldr r3, [pc, #276] @ (8010264 ) 8010150: 69db ldr r3, [r3, #28] 8010152: 4a44 ldr r2, [pc, #272] @ (8010264 ) 8010154: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8010158: 61d3 str r3, [r2, #28] #if defined(RCC_CR_PLL2ON) /*-------------------------------- PLL2 Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) 801015a: 687b ldr r3, [r7, #4] 801015c: 6adb ldr r3, [r3, #44] @ 0x2c 801015e: 2b00 cmp r3, #0 8010160: f000 808c beq.w 801027c { /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 8010164: 4b3f ldr r3, [pc, #252] @ (8010264 ) 8010166: 685b ldr r3, [r3, #4] 8010168: f403 3380 and.w r3, r3, #65536 @ 0x10000 801016c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010170: d10e bne.n 8010190 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 8010172: 4b3c ldr r3, [pc, #240] @ (8010264 ) 8010174: 685b ldr r3, [r3, #4] 8010176: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 801017a: 2b08 cmp r3, #8 801017c: d108 bne.n 8010190 ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) 801017e: 4b39 ldr r3, [pc, #228] @ (8010264 ) 8010180: 6adb ldr r3, [r3, #44] @ 0x2c 8010182: f403 3380 and.w r3, r3, #65536 @ 0x10000 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 8010186: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 801018a: d101 bne.n 8010190 { return HAL_ERROR; 801018c: 2301 movs r3, #1 801018e: e103 b.n 8010398 } else { if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) 8010190: 687b ldr r3, [r7, #4] 8010192: 6adb ldr r3, [r3, #44] @ 0x2c 8010194: 2b02 cmp r3, #2 8010196: d14e bne.n 8010236 assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); /* Prediv2 can be written only when the PLLI2S is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 8010198: 4b32 ldr r3, [pc, #200] @ (8010264 ) 801019a: 681b ldr r3, [r3, #0] 801019c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80101a0: 2b00 cmp r3, #0 80101a2: d009 beq.n 80101b8 (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) 80101a4: 4b2f ldr r3, [pc, #188] @ (8010264 ) 80101a6: 6adb ldr r3, [r3, #44] @ 0x2c 80101a8: f003 02f0 and.w r2, r3, #240 @ 0xf0 80101ac: 687b ldr r3, [r7, #4] 80101ae: 6b5b ldr r3, [r3, #52] @ 0x34 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 80101b0: 429a cmp r2, r3 80101b2: d001 beq.n 80101b8 { return HAL_ERROR; 80101b4: 2301 movs r3, #1 80101b6: e0ef b.n 8010398 } /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 80101b8: 4b2c ldr r3, [pc, #176] @ (801026c ) 80101ba: 2200 movs r2, #0 80101bc: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80101be: f7fd fcd7 bl 800db70 80101c2: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 80101c4: e008 b.n 80101d8 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 80101c6: f7fd fcd3 bl 800db70 80101ca: 4602 mov r2, r0 80101cc: 693b ldr r3, [r7, #16] 80101ce: 1ad3 subs r3, r2, r3 80101d0: 2b64 cmp r3, #100 @ 0x64 80101d2: d901 bls.n 80101d8 { return HAL_TIMEOUT; 80101d4: 2303 movs r3, #3 80101d6: e0df b.n 8010398 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 80101d8: 4b22 ldr r3, [pc, #136] @ (8010264 ) 80101da: 681b ldr r3, [r3, #0] 80101dc: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80101e0: 2b00 cmp r3, #0 80101e2: d1f0 bne.n 80101c6 } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); 80101e4: 4b1f ldr r3, [pc, #124] @ (8010264 ) 80101e6: 6adb ldr r3, [r3, #44] @ 0x2c 80101e8: f023 02f0 bic.w r2, r3, #240 @ 0xf0 80101ec: 687b ldr r3, [r7, #4] 80101ee: 6b5b ldr r3, [r3, #52] @ 0x34 80101f0: 491c ldr r1, [pc, #112] @ (8010264 ) 80101f2: 4313 orrs r3, r2 80101f4: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); 80101f6: 4b1b ldr r3, [pc, #108] @ (8010264 ) 80101f8: 6adb ldr r3, [r3, #44] @ 0x2c 80101fa: f423 6270 bic.w r2, r3, #3840 @ 0xf00 80101fe: 687b ldr r3, [r7, #4] 8010200: 6b1b ldr r3, [r3, #48] @ 0x30 8010202: 4918 ldr r1, [pc, #96] @ (8010264 ) 8010204: 4313 orrs r3, r2 8010206: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); 8010208: 4b18 ldr r3, [pc, #96] @ (801026c ) 801020a: 2201 movs r2, #1 801020c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 801020e: f7fd fcaf bl 800db70 8010212: 6138 str r0, [r7, #16] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8010214: e008 b.n 8010228 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8010216: f7fd fcab bl 800db70 801021a: 4602 mov r2, r0 801021c: 693b ldr r3, [r7, #16] 801021e: 1ad3 subs r3, r2, r3 8010220: 2b64 cmp r3, #100 @ 0x64 8010222: d901 bls.n 8010228 { return HAL_TIMEOUT; 8010224: 2303 movs r3, #3 8010226: e0b7 b.n 8010398 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8010228: 4b0e ldr r3, [pc, #56] @ (8010264 ) 801022a: 681b ldr r3, [r3, #0] 801022c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8010230: 2b00 cmp r3, #0 8010232: d0f0 beq.n 8010216 8010234: e022 b.n 801027c } } else { /* Set PREDIV1 source to HSE */ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); 8010236: 4b0b ldr r3, [pc, #44] @ (8010264 ) 8010238: 6adb ldr r3, [r3, #44] @ 0x2c 801023a: 4a0a ldr r2, [pc, #40] @ (8010264 ) 801023c: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8010240: 62d3 str r3, [r2, #44] @ 0x2c /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 8010242: 4b0a ldr r3, [pc, #40] @ (801026c ) 8010244: 2200 movs r2, #0 8010246: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010248: f7fd fc92 bl 800db70 801024c: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 801024e: e00f b.n 8010270 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8010250: f7fd fc8e bl 800db70 8010254: 4602 mov r2, r0 8010256: 693b ldr r3, [r7, #16] 8010258: 1ad3 subs r3, r2, r3 801025a: 2b64 cmp r3, #100 @ 0x64 801025c: d908 bls.n 8010270 { return HAL_TIMEOUT; 801025e: 2303 movs r3, #3 8010260: e09a b.n 8010398 8010262: bf00 nop 8010264: 40021000 .word 0x40021000 8010268: 40007000 .word 0x40007000 801026c: 42420068 .word 0x42420068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8010270: 4b4b ldr r3, [pc, #300] @ (80103a0 ) 8010272: 681b ldr r3, [r3, #0] 8010274: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8010278: 2b00 cmp r3, #0 801027a: d1e9 bne.n 8010250 #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 801027c: 687b ldr r3, [r7, #4] 801027e: 6a1b ldr r3, [r3, #32] 8010280: 2b00 cmp r3, #0 8010282: f000 8088 beq.w 8010396 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8010286: 4b46 ldr r3, [pc, #280] @ (80103a0 ) 8010288: 685b ldr r3, [r3, #4] 801028a: f003 030c and.w r3, r3, #12 801028e: 2b08 cmp r3, #8 8010290: d068 beq.n 8010364 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8010292: 687b ldr r3, [r7, #4] 8010294: 6a1b ldr r3, [r3, #32] 8010296: 2b02 cmp r3, #2 8010298: d14d bne.n 8010336 /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 801029a: 4b42 ldr r3, [pc, #264] @ (80103a4 ) 801029c: 2200 movs r2, #0 801029e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80102a0: f7fd fc66 bl 800db70 80102a4: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80102a6: e008 b.n 80102ba { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80102a8: f7fd fc62 bl 800db70 80102ac: 4602 mov r2, r0 80102ae: 693b ldr r3, [r7, #16] 80102b0: 1ad3 subs r3, r2, r3 80102b2: 2b02 cmp r3, #2 80102b4: d901 bls.n 80102ba { return HAL_TIMEOUT; 80102b6: 2303 movs r3, #3 80102b8: e06e b.n 8010398 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80102ba: 4b39 ldr r3, [pc, #228] @ (80103a0 ) 80102bc: 681b ldr r3, [r3, #0] 80102be: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80102c2: 2b00 cmp r3, #0 80102c4: d1f0 bne.n 80102a8 } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 80102c6: 687b ldr r3, [r7, #4] 80102c8: 6a5b ldr r3, [r3, #36] @ 0x24 80102ca: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80102ce: d10f bne.n 80102f0 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); #if defined(RCC_CFGR2_PREDIV1SRC) assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); 80102d0: 4b33 ldr r3, [pc, #204] @ (80103a0 ) 80102d2: 6ada ldr r2, [r3, #44] @ 0x2c 80102d4: 687b ldr r3, [r7, #4] 80102d6: 685b ldr r3, [r3, #4] 80102d8: 4931 ldr r1, [pc, #196] @ (80103a0 ) 80102da: 4313 orrs r3, r2 80102dc: 62cb str r3, [r1, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 80102de: 4b30 ldr r3, [pc, #192] @ (80103a0 ) 80102e0: 6adb ldr r3, [r3, #44] @ 0x2c 80102e2: f023 020f bic.w r2, r3, #15 80102e6: 687b ldr r3, [r7, #4] 80102e8: 68db ldr r3, [r3, #12] 80102ea: 492d ldr r1, [pc, #180] @ (80103a0 ) 80102ec: 4313 orrs r3, r2 80102ee: 62cb str r3, [r1, #44] @ 0x2c } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80102f0: 4b2b ldr r3, [pc, #172] @ (80103a0 ) 80102f2: 685b ldr r3, [r3, #4] 80102f4: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 80102f8: 687b ldr r3, [r7, #4] 80102fa: 6a59 ldr r1, [r3, #36] @ 0x24 80102fc: 687b ldr r3, [r7, #4] 80102fe: 6a9b ldr r3, [r3, #40] @ 0x28 8010300: 430b orrs r3, r1 8010302: 4927 ldr r1, [pc, #156] @ (80103a0 ) 8010304: 4313 orrs r3, r2 8010306: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8010308: 4b26 ldr r3, [pc, #152] @ (80103a4 ) 801030a: 2201 movs r2, #1 801030c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 801030e: f7fd fc2f bl 800db70 8010312: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8010314: e008 b.n 8010328 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8010316: f7fd fc2b bl 800db70 801031a: 4602 mov r2, r0 801031c: 693b ldr r3, [r7, #16] 801031e: 1ad3 subs r3, r2, r3 8010320: 2b02 cmp r3, #2 8010322: d901 bls.n 8010328 { return HAL_TIMEOUT; 8010324: 2303 movs r3, #3 8010326: e037 b.n 8010398 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8010328: 4b1d ldr r3, [pc, #116] @ (80103a0 ) 801032a: 681b ldr r3, [r3, #0] 801032c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8010330: 2b00 cmp r3, #0 8010332: d0f0 beq.n 8010316 8010334: e02f b.n 8010396 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8010336: 4b1b ldr r3, [pc, #108] @ (80103a4 ) 8010338: 2200 movs r2, #0 801033a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 801033c: f7fd fc18 bl 800db70 8010340: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8010342: e008 b.n 8010356 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8010344: f7fd fc14 bl 800db70 8010348: 4602 mov r2, r0 801034a: 693b ldr r3, [r7, #16] 801034c: 1ad3 subs r3, r2, r3 801034e: 2b02 cmp r3, #2 8010350: d901 bls.n 8010356 { return HAL_TIMEOUT; 8010352: 2303 movs r3, #3 8010354: e020 b.n 8010398 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8010356: 4b12 ldr r3, [pc, #72] @ (80103a0 ) 8010358: 681b ldr r3, [r3, #0] 801035a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 801035e: 2b00 cmp r3, #0 8010360: d1f0 bne.n 8010344 8010362: e018 b.n 8010396 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8010364: 687b ldr r3, [r7, #4] 8010366: 6a1b ldr r3, [r3, #32] 8010368: 2b01 cmp r3, #1 801036a: d101 bne.n 8010370 { return HAL_ERROR; 801036c: 2301 movs r3, #1 801036e: e013 b.n 8010398 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8010370: 4b0b ldr r3, [pc, #44] @ (80103a0 ) 8010372: 685b ldr r3, [r3, #4] 8010374: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8010376: 68fb ldr r3, [r7, #12] 8010378: f403 3280 and.w r2, r3, #65536 @ 0x10000 801037c: 687b ldr r3, [r7, #4] 801037e: 6a5b ldr r3, [r3, #36] @ 0x24 8010380: 429a cmp r2, r3 8010382: d106 bne.n 8010392 (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8010384: 68fb ldr r3, [r7, #12] 8010386: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 801038a: 687b ldr r3, [r7, #4] 801038c: 6a9b ldr r3, [r3, #40] @ 0x28 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 801038e: 429a cmp r2, r3 8010390: d001 beq.n 8010396 { return HAL_ERROR; 8010392: 2301 movs r3, #1 8010394: e000 b.n 8010398 } } } } return HAL_OK; 8010396: 2300 movs r3, #0 } 8010398: 4618 mov r0, r3 801039a: 3718 adds r7, #24 801039c: 46bd mov sp, r7 801039e: bd80 pop {r7, pc} 80103a0: 40021000 .word 0x40021000 80103a4: 42420060 .word 0x42420060 080103a8 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 80103a8: b580 push {r7, lr} 80103aa: b084 sub sp, #16 80103ac: af00 add r7, sp, #0 80103ae: 6078 str r0, [r7, #4] 80103b0: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 80103b2: 687b ldr r3, [r7, #4] 80103b4: 2b00 cmp r3, #0 80103b6: d101 bne.n 80103bc { return HAL_ERROR; 80103b8: 2301 movs r3, #1 80103ba: e0d0 b.n 801055e must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 80103bc: 4b6a ldr r3, [pc, #424] @ (8010568 ) 80103be: 681b ldr r3, [r3, #0] 80103c0: f003 0307 and.w r3, r3, #7 80103c4: 683a ldr r2, [r7, #0] 80103c6: 429a cmp r2, r3 80103c8: d910 bls.n 80103ec { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80103ca: 4b67 ldr r3, [pc, #412] @ (8010568 ) 80103cc: 681b ldr r3, [r3, #0] 80103ce: f023 0207 bic.w r2, r3, #7 80103d2: 4965 ldr r1, [pc, #404] @ (8010568 ) 80103d4: 683b ldr r3, [r7, #0] 80103d6: 4313 orrs r3, r2 80103d8: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80103da: 4b63 ldr r3, [pc, #396] @ (8010568 ) 80103dc: 681b ldr r3, [r3, #0] 80103de: f003 0307 and.w r3, r3, #7 80103e2: 683a ldr r2, [r7, #0] 80103e4: 429a cmp r2, r3 80103e6: d001 beq.n 80103ec { return HAL_ERROR; 80103e8: 2301 movs r3, #1 80103ea: e0b8 b.n 801055e } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 80103ec: 687b ldr r3, [r7, #4] 80103ee: 681b ldr r3, [r3, #0] 80103f0: f003 0302 and.w r3, r3, #2 80103f4: 2b00 cmp r3, #0 80103f6: d020 beq.n 801043a { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80103f8: 687b ldr r3, [r7, #4] 80103fa: 681b ldr r3, [r3, #0] 80103fc: f003 0304 and.w r3, r3, #4 8010400: 2b00 cmp r3, #0 8010402: d005 beq.n 8010410 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8010404: 4b59 ldr r3, [pc, #356] @ (801056c ) 8010406: 685b ldr r3, [r3, #4] 8010408: 4a58 ldr r2, [pc, #352] @ (801056c ) 801040a: f443 63e0 orr.w r3, r3, #1792 @ 0x700 801040e: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8010410: 687b ldr r3, [r7, #4] 8010412: 681b ldr r3, [r3, #0] 8010414: f003 0308 and.w r3, r3, #8 8010418: 2b00 cmp r3, #0 801041a: d005 beq.n 8010428 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 801041c: 4b53 ldr r3, [pc, #332] @ (801056c ) 801041e: 685b ldr r3, [r3, #4] 8010420: 4a52 ldr r2, [pc, #328] @ (801056c ) 8010422: f443 5360 orr.w r3, r3, #14336 @ 0x3800 8010426: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8010428: 4b50 ldr r3, [pc, #320] @ (801056c ) 801042a: 685b ldr r3, [r3, #4] 801042c: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8010430: 687b ldr r3, [r7, #4] 8010432: 689b ldr r3, [r3, #8] 8010434: 494d ldr r1, [pc, #308] @ (801056c ) 8010436: 4313 orrs r3, r2 8010438: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 801043a: 687b ldr r3, [r7, #4] 801043c: 681b ldr r3, [r3, #0] 801043e: f003 0301 and.w r3, r3, #1 8010442: 2b00 cmp r3, #0 8010444: d040 beq.n 80104c8 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8010446: 687b ldr r3, [r7, #4] 8010448: 685b ldr r3, [r3, #4] 801044a: 2b01 cmp r3, #1 801044c: d107 bne.n 801045e { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 801044e: 4b47 ldr r3, [pc, #284] @ (801056c ) 8010450: 681b ldr r3, [r3, #0] 8010452: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010456: 2b00 cmp r3, #0 8010458: d115 bne.n 8010486 { return HAL_ERROR; 801045a: 2301 movs r3, #1 801045c: e07f b.n 801055e } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 801045e: 687b ldr r3, [r7, #4] 8010460: 685b ldr r3, [r3, #4] 8010462: 2b02 cmp r3, #2 8010464: d107 bne.n 8010476 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8010466: 4b41 ldr r3, [pc, #260] @ (801056c ) 8010468: 681b ldr r3, [r3, #0] 801046a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 801046e: 2b00 cmp r3, #0 8010470: d109 bne.n 8010486 { return HAL_ERROR; 8010472: 2301 movs r3, #1 8010474: e073 b.n 801055e } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8010476: 4b3d ldr r3, [pc, #244] @ (801056c ) 8010478: 681b ldr r3, [r3, #0] 801047a: f003 0302 and.w r3, r3, #2 801047e: 2b00 cmp r3, #0 8010480: d101 bne.n 8010486 { return HAL_ERROR; 8010482: 2301 movs r3, #1 8010484: e06b b.n 801055e } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8010486: 4b39 ldr r3, [pc, #228] @ (801056c ) 8010488: 685b ldr r3, [r3, #4] 801048a: f023 0203 bic.w r2, r3, #3 801048e: 687b ldr r3, [r7, #4] 8010490: 685b ldr r3, [r3, #4] 8010492: 4936 ldr r1, [pc, #216] @ (801056c ) 8010494: 4313 orrs r3, r2 8010496: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010498: f7fd fb6a bl 800db70 801049c: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 801049e: e00a b.n 80104b6 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80104a0: f7fd fb66 bl 800db70 80104a4: 4602 mov r2, r0 80104a6: 68fb ldr r3, [r7, #12] 80104a8: 1ad3 subs r3, r2, r3 80104aa: f241 3288 movw r2, #5000 @ 0x1388 80104ae: 4293 cmp r3, r2 80104b0: d901 bls.n 80104b6 { return HAL_TIMEOUT; 80104b2: 2303 movs r3, #3 80104b4: e053 b.n 801055e while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80104b6: 4b2d ldr r3, [pc, #180] @ (801056c ) 80104b8: 685b ldr r3, [r3, #4] 80104ba: f003 020c and.w r2, r3, #12 80104be: 687b ldr r3, [r7, #4] 80104c0: 685b ldr r3, [r3, #4] 80104c2: 009b lsls r3, r3, #2 80104c4: 429a cmp r2, r3 80104c6: d1eb bne.n 80104a0 } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 80104c8: 4b27 ldr r3, [pc, #156] @ (8010568 ) 80104ca: 681b ldr r3, [r3, #0] 80104cc: f003 0307 and.w r3, r3, #7 80104d0: 683a ldr r2, [r7, #0] 80104d2: 429a cmp r2, r3 80104d4: d210 bcs.n 80104f8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80104d6: 4b24 ldr r3, [pc, #144] @ (8010568 ) 80104d8: 681b ldr r3, [r3, #0] 80104da: f023 0207 bic.w r2, r3, #7 80104de: 4922 ldr r1, [pc, #136] @ (8010568 ) 80104e0: 683b ldr r3, [r7, #0] 80104e2: 4313 orrs r3, r2 80104e4: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80104e6: 4b20 ldr r3, [pc, #128] @ (8010568 ) 80104e8: 681b ldr r3, [r3, #0] 80104ea: f003 0307 and.w r3, r3, #7 80104ee: 683a ldr r2, [r7, #0] 80104f0: 429a cmp r2, r3 80104f2: d001 beq.n 80104f8 { return HAL_ERROR; 80104f4: 2301 movs r3, #1 80104f6: e032 b.n 801055e } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80104f8: 687b ldr r3, [r7, #4] 80104fa: 681b ldr r3, [r3, #0] 80104fc: f003 0304 and.w r3, r3, #4 8010500: 2b00 cmp r3, #0 8010502: d008 beq.n 8010516 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8010504: 4b19 ldr r3, [pc, #100] @ (801056c ) 8010506: 685b ldr r3, [r3, #4] 8010508: f423 62e0 bic.w r2, r3, #1792 @ 0x700 801050c: 687b ldr r3, [r7, #4] 801050e: 68db ldr r3, [r3, #12] 8010510: 4916 ldr r1, [pc, #88] @ (801056c ) 8010512: 4313 orrs r3, r2 8010514: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8010516: 687b ldr r3, [r7, #4] 8010518: 681b ldr r3, [r3, #0] 801051a: f003 0308 and.w r3, r3, #8 801051e: 2b00 cmp r3, #0 8010520: d009 beq.n 8010536 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 8010522: 4b12 ldr r3, [pc, #72] @ (801056c ) 8010524: 685b ldr r3, [r3, #4] 8010526: f423 5260 bic.w r2, r3, #14336 @ 0x3800 801052a: 687b ldr r3, [r7, #4] 801052c: 691b ldr r3, [r3, #16] 801052e: 00db lsls r3, r3, #3 8010530: 490e ldr r1, [pc, #56] @ (801056c ) 8010532: 4313 orrs r3, r2 8010534: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8010536: f000 f821 bl 801057c 801053a: 4602 mov r2, r0 801053c: 4b0b ldr r3, [pc, #44] @ (801056c ) 801053e: 685b ldr r3, [r3, #4] 8010540: 091b lsrs r3, r3, #4 8010542: f003 030f and.w r3, r3, #15 8010546: 490a ldr r1, [pc, #40] @ (8010570 ) 8010548: 5ccb ldrb r3, [r1, r3] 801054a: fa22 f303 lsr.w r3, r2, r3 801054e: 4a09 ldr r2, [pc, #36] @ (8010574 ) 8010550: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 8010552: 4b09 ldr r3, [pc, #36] @ (8010578 ) 8010554: 681b ldr r3, [r3, #0] 8010556: 4618 mov r0, r3 8010558: f7fd fac8 bl 800daec return HAL_OK; 801055c: 2300 movs r3, #0 } 801055e: 4618 mov r0, r3 8010560: 3710 adds r7, #16 8010562: 46bd mov sp, r7 8010564: bd80 pop {r7, pc} 8010566: bf00 nop 8010568: 40022000 .word 0x40022000 801056c: 40021000 .word 0x40021000 8010570: 080160f0 .word 0x080160f0 8010574: 2000006c .word 0x2000006c 8010578: 20000070 .word 0x20000070 0801057c : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 801057c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8010580: b08e sub sp, #56 @ 0x38 8010582: af00 add r7, sp, #0 #else static const uint8_t aPredivFactorTable[2U] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8010584: 2300 movs r3, #0 8010586: 62fb str r3, [r7, #44] @ 0x2c 8010588: 2300 movs r3, #0 801058a: 62bb str r3, [r7, #40] @ 0x28 801058c: 2300 movs r3, #0 801058e: 637b str r3, [r7, #52] @ 0x34 8010590: 2300 movs r3, #0 8010592: 627b str r3, [r7, #36] @ 0x24 uint32_t sysclockfreq = 0U; 8010594: 2300 movs r3, #0 8010596: 633b str r3, [r7, #48] @ 0x30 #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; 8010598: 2300 movs r3, #0 801059a: 623b str r3, [r7, #32] 801059c: 2300 movs r3, #0 801059e: 61fb str r3, [r7, #28] #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 80105a0: 4b4e ldr r3, [pc, #312] @ (80106dc ) 80105a2: 685b ldr r3, [r3, #4] 80105a4: 62fb str r3, [r7, #44] @ 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 80105a6: 6afb ldr r3, [r7, #44] @ 0x2c 80105a8: f003 030c and.w r3, r3, #12 80105ac: 2b04 cmp r3, #4 80105ae: d002 beq.n 80105b6 80105b0: 2b08 cmp r3, #8 80105b2: d003 beq.n 80105bc 80105b4: e089 b.n 80106ca { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 80105b6: 4b4a ldr r3, [pc, #296] @ (80106e0 ) 80105b8: 633b str r3, [r7, #48] @ 0x30 break; 80105ba: e089 b.n 80106d0 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 80105bc: 6afb ldr r3, [r7, #44] @ 0x2c 80105be: 0c9b lsrs r3, r3, #18 80105c0: f003 020f and.w r2, r3, #15 80105c4: 4b47 ldr r3, [pc, #284] @ (80106e4 ) 80105c6: 5c9b ldrb r3, [r3, r2] 80105c8: 627b str r3, [r7, #36] @ 0x24 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 80105ca: 6afb ldr r3, [r7, #44] @ 0x2c 80105cc: f403 3380 and.w r3, r3, #65536 @ 0x10000 80105d0: 2b00 cmp r3, #0 80105d2: d072 beq.n 80106ba { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 80105d4: 4b41 ldr r3, [pc, #260] @ (80106dc ) 80105d6: 6adb ldr r3, [r3, #44] @ 0x2c 80105d8: f003 020f and.w r2, r3, #15 80105dc: 4b42 ldr r3, [pc, #264] @ (80106e8 ) 80105de: 5c9b ldrb r3, [r3, r2] 80105e0: 62bb str r3, [r7, #40] @ 0x28 #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /*RCC_CFGR2_PREDIV1*/ #if defined(RCC_CFGR2_PREDIV1SRC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 80105e2: 4b3e ldr r3, [pc, #248] @ (80106dc ) 80105e4: 6adb ldr r3, [r3, #44] @ 0x2c 80105e6: f403 3380 and.w r3, r3, #65536 @ 0x10000 80105ea: 2b00 cmp r3, #0 80105ec: d053 beq.n 8010696 { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 80105ee: 4b3b ldr r3, [pc, #236] @ (80106dc ) 80105f0: 6adb ldr r3, [r3, #44] @ 0x2c 80105f2: 091b lsrs r3, r3, #4 80105f4: f003 030f and.w r3, r3, #15 80105f8: 3301 adds r3, #1 80105fa: 623b str r3, [r7, #32] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 80105fc: 4b37 ldr r3, [pc, #220] @ (80106dc ) 80105fe: 6adb ldr r3, [r3, #44] @ 0x2c 8010600: 0a1b lsrs r3, r3, #8 8010602: f003 030f and.w r3, r3, #15 8010606: 3302 adds r3, #2 8010608: 61fb str r3, [r7, #28] pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); 801060a: 69fb ldr r3, [r7, #28] 801060c: 2200 movs r2, #0 801060e: 469a mov sl, r3 8010610: 4693 mov fp, r2 8010612: 6a7b ldr r3, [r7, #36] @ 0x24 8010614: 2200 movs r2, #0 8010616: 613b str r3, [r7, #16] 8010618: 617a str r2, [r7, #20] 801061a: 693b ldr r3, [r7, #16] 801061c: fb03 f20b mul.w r2, r3, fp 8010620: 697b ldr r3, [r7, #20] 8010622: fb0a f303 mul.w r3, sl, r3 8010626: 4413 add r3, r2 8010628: 693a ldr r2, [r7, #16] 801062a: fbaa 0102 umull r0, r1, sl, r2 801062e: 440b add r3, r1 8010630: 4619 mov r1, r3 8010632: 4b2b ldr r3, [pc, #172] @ (80106e0 ) 8010634: fb03 f201 mul.w r2, r3, r1 8010638: 2300 movs r3, #0 801063a: fb00 f303 mul.w r3, r0, r3 801063e: 4413 add r3, r2 8010640: 4a27 ldr r2, [pc, #156] @ (80106e0 ) 8010642: fba0 4502 umull r4, r5, r0, r2 8010646: 442b add r3, r5 8010648: 461d mov r5, r3 801064a: 6a3b ldr r3, [r7, #32] 801064c: 2200 movs r2, #0 801064e: 60bb str r3, [r7, #8] 8010650: 60fa str r2, [r7, #12] 8010652: 6abb ldr r3, [r7, #40] @ 0x28 8010654: 2200 movs r2, #0 8010656: 603b str r3, [r7, #0] 8010658: 607a str r2, [r7, #4] 801065a: e9d7 0102 ldrd r0, r1, [r7, #8] 801065e: 460b mov r3, r1 8010660: e9d7 ab00 ldrd sl, fp, [r7] 8010664: 4652 mov r2, sl 8010666: fb02 f203 mul.w r2, r2, r3 801066a: 465b mov r3, fp 801066c: 4684 mov ip, r0 801066e: fb0c f303 mul.w r3, ip, r3 8010672: 4413 add r3, r2 8010674: 4602 mov r2, r0 8010676: 4651 mov r1, sl 8010678: fba2 8901 umull r8, r9, r2, r1 801067c: 444b add r3, r9 801067e: 4699 mov r9, r3 8010680: 4642 mov r2, r8 8010682: 464b mov r3, r9 8010684: 4620 mov r0, r4 8010686: 4629 mov r1, r5 8010688: f7f8 fdb4 bl 80091f4 <__aeabi_uldivmod> 801068c: 4602 mov r2, r0 801068e: 460b mov r3, r1 8010690: 4613 mov r3, r2 8010692: 637b str r3, [r7, #52] @ 0x34 8010694: e007 b.n 80106a6 } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8010696: 6a7b ldr r3, [r7, #36] @ 0x24 8010698: 4a11 ldr r2, [pc, #68] @ (80106e0 ) 801069a: fb03 f202 mul.w r2, r3, r2 801069e: 6abb ldr r3, [r7, #40] @ 0x28 80106a0: fbb2 f3f3 udiv r3, r2, r3 80106a4: 637b str r3, [r7, #52] @ 0x34 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 80106a6: 4b0f ldr r3, [pc, #60] @ (80106e4 ) 80106a8: 7b5b ldrb r3, [r3, #13] 80106aa: 461a mov r2, r3 80106ac: 6a7b ldr r3, [r7, #36] @ 0x24 80106ae: 4293 cmp r3, r2 80106b0: d108 bne.n 80106c4 { pllclk = pllclk / 2; 80106b2: 6b7b ldr r3, [r7, #52] @ 0x34 80106b4: 085b lsrs r3, r3, #1 80106b6: 637b str r3, [r7, #52] @ 0x34 80106b8: e004 b.n 80106c4 #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 80106ba: 6a7b ldr r3, [r7, #36] @ 0x24 80106bc: 4a0b ldr r2, [pc, #44] @ (80106ec ) 80106be: fb02 f303 mul.w r3, r2, r3 80106c2: 637b str r3, [r7, #52] @ 0x34 } sysclockfreq = pllclk; 80106c4: 6b7b ldr r3, [r7, #52] @ 0x34 80106c6: 633b str r3, [r7, #48] @ 0x30 break; 80106c8: e002 b.n 80106d0 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 80106ca: 4b09 ldr r3, [pc, #36] @ (80106f0 ) 80106cc: 633b str r3, [r7, #48] @ 0x30 break; 80106ce: bf00 nop } } return sysclockfreq; 80106d0: 6b3b ldr r3, [r7, #48] @ 0x30 } 80106d2: 4618 mov r0, r3 80106d4: 3738 adds r7, #56 @ 0x38 80106d6: 46bd mov sp, r7 80106d8: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 80106dc: 40021000 .word 0x40021000 80106e0: 017d7840 .word 0x017d7840 80106e4: 08016108 .word 0x08016108 80106e8: 08016118 .word 0x08016118 80106ec: 003d0900 .word 0x003d0900 80106f0: 007a1200 .word 0x007a1200 080106f4 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 80106f4: b480 push {r7} 80106f6: af00 add r7, sp, #0 return SystemCoreClock; 80106f8: 4b02 ldr r3, [pc, #8] @ (8010704 ) 80106fa: 681b ldr r3, [r3, #0] } 80106fc: 4618 mov r0, r3 80106fe: 46bd mov sp, r7 8010700: bc80 pop {r7} 8010702: 4770 bx lr 8010704: 2000006c .word 0x2000006c 08010708 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8010708: b580 push {r7, lr} 801070a: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 801070c: f7ff fff2 bl 80106f4 8010710: 4602 mov r2, r0 8010712: 4b05 ldr r3, [pc, #20] @ (8010728 ) 8010714: 685b ldr r3, [r3, #4] 8010716: 0a1b lsrs r3, r3, #8 8010718: f003 0307 and.w r3, r3, #7 801071c: 4903 ldr r1, [pc, #12] @ (801072c ) 801071e: 5ccb ldrb r3, [r1, r3] 8010720: fa22 f303 lsr.w r3, r2, r3 } 8010724: 4618 mov r0, r3 8010726: bd80 pop {r7, pc} 8010728: 40021000 .word 0x40021000 801072c: 08016100 .word 0x08016100 08010730 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8010730: b580 push {r7, lr} 8010732: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8010734: f7ff ffde bl 80106f4 8010738: 4602 mov r2, r0 801073a: 4b05 ldr r3, [pc, #20] @ (8010750 ) 801073c: 685b ldr r3, [r3, #4] 801073e: 0adb lsrs r3, r3, #11 8010740: f003 0307 and.w r3, r3, #7 8010744: 4903 ldr r1, [pc, #12] @ (8010754 ) 8010746: 5ccb ldrb r3, [r1, r3] 8010748: fa22 f303 lsr.w r3, r2, r3 } 801074c: 4618 mov r0, r3 801074e: bd80 pop {r7, pc} 8010750: 40021000 .word 0x40021000 8010754: 08016100 .word 0x08016100 08010758 : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8010758: b480 push {r7} 801075a: b085 sub sp, #20 801075c: af00 add r7, sp, #0 801075e: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8010760: 4b0a ldr r3, [pc, #40] @ (801078c ) 8010762: 681b ldr r3, [r3, #0] 8010764: 4a0a ldr r2, [pc, #40] @ (8010790 ) 8010766: fba2 2303 umull r2, r3, r2, r3 801076a: 0a5b lsrs r3, r3, #9 801076c: 687a ldr r2, [r7, #4] 801076e: fb02 f303 mul.w r3, r2, r3 8010772: 60fb str r3, [r7, #12] do { __NOP(); 8010774: bf00 nop } while (Delay --); 8010776: 68fb ldr r3, [r7, #12] 8010778: 1e5a subs r2, r3, #1 801077a: 60fa str r2, [r7, #12] 801077c: 2b00 cmp r3, #0 801077e: d1f9 bne.n 8010774 } 8010780: bf00 nop 8010782: bf00 nop 8010784: 3714 adds r7, #20 8010786: 46bd mov sp, r7 8010788: bc80 pop {r7} 801078a: 4770 bx lr 801078c: 2000006c .word 0x2000006c 8010790: 10624dd3 .word 0x10624dd3 08010794 : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8010794: b580 push {r7, lr} 8010796: b088 sub sp, #32 8010798: af00 add r7, sp, #0 801079a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 801079c: 2300 movs r3, #0 801079e: 617b str r3, [r7, #20] 80107a0: 2300 movs r3, #0 80107a2: 613b str r3, [r7, #16] #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t pllactive = 0U; 80107a4: 2300 movs r3, #0 80107a6: 61fb str r3, [r7, #28] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 80107a8: 687b ldr r3, [r7, #4] 80107aa: 681b ldr r3, [r3, #0] 80107ac: f003 0301 and.w r3, r3, #1 80107b0: 2b00 cmp r3, #0 80107b2: d07d beq.n 80108b0 { FlagStatus pwrclkchanged = RESET; 80107b4: 2300 movs r3, #0 80107b6: 76fb strb r3, [r7, #27] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80107b8: 4b8b ldr r3, [pc, #556] @ (80109e8 ) 80107ba: 69db ldr r3, [r3, #28] 80107bc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80107c0: 2b00 cmp r3, #0 80107c2: d10d bne.n 80107e0 { __HAL_RCC_PWR_CLK_ENABLE(); 80107c4: 4b88 ldr r3, [pc, #544] @ (80109e8 ) 80107c6: 69db ldr r3, [r3, #28] 80107c8: 4a87 ldr r2, [pc, #540] @ (80109e8 ) 80107ca: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80107ce: 61d3 str r3, [r2, #28] 80107d0: 4b85 ldr r3, [pc, #532] @ (80109e8 ) 80107d2: 69db ldr r3, [r3, #28] 80107d4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80107d8: 60fb str r3, [r7, #12] 80107da: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 80107dc: 2301 movs r3, #1 80107de: 76fb strb r3, [r7, #27] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80107e0: 4b82 ldr r3, [pc, #520] @ (80109ec ) 80107e2: 681b ldr r3, [r3, #0] 80107e4: f403 7380 and.w r3, r3, #256 @ 0x100 80107e8: 2b00 cmp r3, #0 80107ea: d118 bne.n 801081e { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80107ec: 4b7f ldr r3, [pc, #508] @ (80109ec ) 80107ee: 681b ldr r3, [r3, #0] 80107f0: 4a7e ldr r2, [pc, #504] @ (80109ec ) 80107f2: f443 7380 orr.w r3, r3, #256 @ 0x100 80107f6: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80107f8: f7fd f9ba bl 800db70 80107fc: 6178 str r0, [r7, #20] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80107fe: e008 b.n 8010812 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8010800: f7fd f9b6 bl 800db70 8010804: 4602 mov r2, r0 8010806: 697b ldr r3, [r7, #20] 8010808: 1ad3 subs r3, r2, r3 801080a: 2b64 cmp r3, #100 @ 0x64 801080c: d901 bls.n 8010812 { return HAL_TIMEOUT; 801080e: 2303 movs r3, #3 8010810: e0e5 b.n 80109de while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010812: 4b76 ldr r3, [pc, #472] @ (80109ec ) 8010814: 681b ldr r3, [r3, #0] 8010816: f403 7380 and.w r3, r3, #256 @ 0x100 801081a: 2b00 cmp r3, #0 801081c: d0f0 beq.n 8010800 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 801081e: 4b72 ldr r3, [pc, #456] @ (80109e8 ) 8010820: 6a1b ldr r3, [r3, #32] 8010822: f403 7340 and.w r3, r3, #768 @ 0x300 8010826: 613b str r3, [r7, #16] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8010828: 693b ldr r3, [r7, #16] 801082a: 2b00 cmp r3, #0 801082c: d02e beq.n 801088c 801082e: 687b ldr r3, [r7, #4] 8010830: 685b ldr r3, [r3, #4] 8010832: f403 7340 and.w r3, r3, #768 @ 0x300 8010836: 693a ldr r2, [r7, #16] 8010838: 429a cmp r2, r3 801083a: d027 beq.n 801088c { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 801083c: 4b6a ldr r3, [pc, #424] @ (80109e8 ) 801083e: 6a1b ldr r3, [r3, #32] 8010840: f423 7340 bic.w r3, r3, #768 @ 0x300 8010844: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8010846: 4b6a ldr r3, [pc, #424] @ (80109f0 ) 8010848: 2201 movs r2, #1 801084a: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 801084c: 4b68 ldr r3, [pc, #416] @ (80109f0 ) 801084e: 2200 movs r2, #0 8010850: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 8010852: 4a65 ldr r2, [pc, #404] @ (80109e8 ) 8010854: 693b ldr r3, [r7, #16] 8010856: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8010858: 693b ldr r3, [r7, #16] 801085a: f003 0301 and.w r3, r3, #1 801085e: 2b00 cmp r3, #0 8010860: d014 beq.n 801088c { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010862: f7fd f985 bl 800db70 8010866: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8010868: e00a b.n 8010880 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 801086a: f7fd f981 bl 800db70 801086e: 4602 mov r2, r0 8010870: 697b ldr r3, [r7, #20] 8010872: 1ad3 subs r3, r2, r3 8010874: f241 3288 movw r2, #5000 @ 0x1388 8010878: 4293 cmp r3, r2 801087a: d901 bls.n 8010880 { return HAL_TIMEOUT; 801087c: 2303 movs r3, #3 801087e: e0ae b.n 80109de while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8010880: 4b59 ldr r3, [pc, #356] @ (80109e8 ) 8010882: 6a1b ldr r3, [r3, #32] 8010884: f003 0302 and.w r3, r3, #2 8010888: 2b00 cmp r3, #0 801088a: d0ee beq.n 801086a } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 801088c: 4b56 ldr r3, [pc, #344] @ (80109e8 ) 801088e: 6a1b ldr r3, [r3, #32] 8010890: f423 7240 bic.w r2, r3, #768 @ 0x300 8010894: 687b ldr r3, [r7, #4] 8010896: 685b ldr r3, [r3, #4] 8010898: 4953 ldr r1, [pc, #332] @ (80109e8 ) 801089a: 4313 orrs r3, r2 801089c: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 801089e: 7efb ldrb r3, [r7, #27] 80108a0: 2b01 cmp r3, #1 80108a2: d105 bne.n 80108b0 { __HAL_RCC_PWR_CLK_DISABLE(); 80108a4: 4b50 ldr r3, [pc, #320] @ (80109e8 ) 80108a6: 69db ldr r3, [r3, #28] 80108a8: 4a4f ldr r2, [pc, #316] @ (80109e8 ) 80108aa: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80108ae: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 80108b0: 687b ldr r3, [r7, #4] 80108b2: 681b ldr r3, [r3, #0] 80108b4: f003 0302 and.w r3, r3, #2 80108b8: 2b00 cmp r3, #0 80108ba: d008 beq.n 80108ce { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 80108bc: 4b4a ldr r3, [pc, #296] @ (80109e8 ) 80108be: 685b ldr r3, [r3, #4] 80108c0: f423 4240 bic.w r2, r3, #49152 @ 0xc000 80108c4: 687b ldr r3, [r7, #4] 80108c6: 689b ldr r3, [r3, #8] 80108c8: 4947 ldr r1, [pc, #284] @ (80109e8 ) 80108ca: 4313 orrs r3, r2 80108cc: 604b str r3, [r1, #4] } #if defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ I2S2 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) 80108ce: 687b ldr r3, [r7, #4] 80108d0: 681b ldr r3, [r3, #0] 80108d2: f003 0304 and.w r3, r3, #4 80108d6: 2b00 cmp r3, #0 80108d8: d008 beq.n 80108ec { /* Check the parameters */ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); /* Configure the I2S2 clock source */ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); 80108da: 4b43 ldr r3, [pc, #268] @ (80109e8 ) 80108dc: 6adb ldr r3, [r3, #44] @ 0x2c 80108de: f423 3200 bic.w r2, r3, #131072 @ 0x20000 80108e2: 687b ldr r3, [r7, #4] 80108e4: 68db ldr r3, [r3, #12] 80108e6: 4940 ldr r1, [pc, #256] @ (80109e8 ) 80108e8: 4313 orrs r3, r2 80108ea: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ I2S3 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) 80108ec: 687b ldr r3, [r7, #4] 80108ee: 681b ldr r3, [r3, #0] 80108f0: f003 0308 and.w r3, r3, #8 80108f4: 2b00 cmp r3, #0 80108f6: d008 beq.n 801090a { /* Check the parameters */ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); /* Configure the I2S3 clock source */ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); 80108f8: 4b3b ldr r3, [pc, #236] @ (80109e8 ) 80108fa: 6adb ldr r3, [r3, #44] @ 0x2c 80108fc: f423 2280 bic.w r2, r3, #262144 @ 0x40000 8010900: 687b ldr r3, [r7, #4] 8010902: 691b ldr r3, [r3, #16] 8010904: 4938 ldr r1, [pc, #224] @ (80109e8 ) 8010906: 4313 orrs r3, r2 8010908: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ PLL I2S Configuration ----------------------*/ /* Check that PLLI2S need to be enabled */ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) 801090a: 4b37 ldr r3, [pc, #220] @ (80109e8 ) 801090c: 6adb ldr r3, [r3, #44] @ 0x2c 801090e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010912: 2b00 cmp r3, #0 8010914: d105 bne.n 8010922 8010916: 4b34 ldr r3, [pc, #208] @ (80109e8 ) 8010918: 6adb ldr r3, [r3, #44] @ 0x2c 801091a: f403 2380 and.w r3, r3, #262144 @ 0x40000 801091e: 2b00 cmp r3, #0 8010920: d001 beq.n 8010926 { /* Update flag to indicate that PLL I2S should be active */ pllactive = 1; 8010922: 2301 movs r3, #1 8010924: 61fb str r3, [r7, #28] } /* Check if PLL I2S need to be enabled */ if (pllactive == 1) 8010926: 69fb ldr r3, [r7, #28] 8010928: 2b01 cmp r3, #1 801092a: d148 bne.n 80109be { /* Enable PLL I2S only if not active */ if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) 801092c: 4b2e ldr r3, [pc, #184] @ (80109e8 ) 801092e: 681b ldr r3, [r3, #0] 8010930: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010934: 2b00 cmp r3, #0 8010936: d138 bne.n 80109aa assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); /* Prediv2 can be written only when the PLL2 is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 8010938: 4b2b ldr r3, [pc, #172] @ (80109e8 ) 801093a: 681b ldr r3, [r3, #0] 801093c: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8010940: 2b00 cmp r3, #0 8010942: d009 beq.n 8010958 (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) 8010944: 4b28 ldr r3, [pc, #160] @ (80109e8 ) 8010946: 6adb ldr r3, [r3, #44] @ 0x2c 8010948: f003 02f0 and.w r2, r3, #240 @ 0xf0 801094c: 687b ldr r3, [r7, #4] 801094e: 699b ldr r3, [r3, #24] if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 8010950: 429a cmp r2, r3 8010952: d001 beq.n 8010958 { return HAL_ERROR; 8010954: 2301 movs r3, #1 8010956: e042 b.n 80109de } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); 8010958: 4b23 ldr r3, [pc, #140] @ (80109e8 ) 801095a: 6adb ldr r3, [r3, #44] @ 0x2c 801095c: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8010960: 687b ldr r3, [r7, #4] 8010962: 699b ldr r3, [r3, #24] 8010964: 4920 ldr r1, [pc, #128] @ (80109e8 ) 8010966: 4313 orrs r3, r2 8010968: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); 801096a: 4b1f ldr r3, [pc, #124] @ (80109e8 ) 801096c: 6adb ldr r3, [r3, #44] @ 0x2c 801096e: f423 4270 bic.w r2, r3, #61440 @ 0xf000 8010972: 687b ldr r3, [r7, #4] 8010974: 695b ldr r3, [r3, #20] 8010976: 491c ldr r1, [pc, #112] @ (80109e8 ) 8010978: 4313 orrs r3, r2 801097a: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); 801097c: 4b1d ldr r3, [pc, #116] @ (80109f4 ) 801097e: 2201 movs r2, #1 8010980: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8010982: f7fd f8f5 bl 800db70 8010986: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8010988: e008 b.n 801099c { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 801098a: f7fd f8f1 bl 800db70 801098e: 4602 mov r2, r0 8010990: 697b ldr r3, [r7, #20] 8010992: 1ad3 subs r3, r2, r3 8010994: 2b64 cmp r3, #100 @ 0x64 8010996: d901 bls.n 801099c { return HAL_TIMEOUT; 8010998: 2303 movs r3, #3 801099a: e020 b.n 80109de while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 801099c: 4b12 ldr r3, [pc, #72] @ (80109e8 ) 801099e: 681b ldr r3, [r3, #0] 80109a0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80109a4: 2b00 cmp r3, #0 80109a6: d0f0 beq.n 801098a 80109a8: e009 b.n 80109be } } else { /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) 80109aa: 4b0f ldr r3, [pc, #60] @ (80109e8 ) 80109ac: 6adb ldr r3, [r3, #44] @ 0x2c 80109ae: f403 4270 and.w r2, r3, #61440 @ 0xf000 80109b2: 687b ldr r3, [r7, #4] 80109b4: 695b ldr r3, [r3, #20] 80109b6: 429a cmp r2, r3 80109b8: d001 beq.n 80109be { return HAL_ERROR; 80109ba: 2301 movs r3, #1 80109bc: e00f b.n 80109de #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 80109be: 687b ldr r3, [r7, #4] 80109c0: 681b ldr r3, [r3, #0] 80109c2: f003 0310 and.w r3, r3, #16 80109c6: 2b00 cmp r3, #0 80109c8: d008 beq.n 80109dc { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 80109ca: 4b07 ldr r3, [pc, #28] @ (80109e8 ) 80109cc: 685b ldr r3, [r3, #4] 80109ce: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 80109d2: 687b ldr r3, [r7, #4] 80109d4: 69db ldr r3, [r3, #28] 80109d6: 4904 ldr r1, [pc, #16] @ (80109e8 ) 80109d8: 4313 orrs r3, r2 80109da: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 80109dc: 2300 movs r3, #0 } 80109de: 4618 mov r0, r3 80109e0: 3720 adds r7, #32 80109e2: 46bd mov sp, r7 80109e4: bd80 pop {r7, pc} 80109e6: bf00 nop 80109e8: 40021000 .word 0x40021000 80109ec: 40007000 .word 0x40007000 80109f0: 42420440 .word 0x42420440 80109f4: 42420070 .word 0x42420070 080109f8 : * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 80109f8: b580 push {r7, lr} 80109fa: b08a sub sp, #40 @ 0x28 80109fc: af00 add r7, sp, #0 80109fe: 6078 str r0, [r7, #4] #if defined(STM32F105xC) || defined(STM32F107xC) static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; 8010a00: 2300 movs r3, #0 8010a02: 61fb str r3, [r7, #28] 8010a04: 2300 movs r3, #0 8010a06: 627b str r3, [r7, #36] @ 0x24 8010a08: 2300 movs r3, #0 8010a0a: 61bb str r3, [r7, #24] uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; 8010a0c: 2300 movs r3, #0 8010a0e: 617b str r3, [r7, #20] 8010a10: 2300 movs r3, #0 8010a12: 613b str r3, [r7, #16] 8010a14: 2300 movs r3, #0 8010a16: 60fb str r3, [r7, #12] static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; static const uint8_t aPredivFactorTable[2U] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 8010a18: 2300 movs r3, #0 8010a1a: 60bb str r3, [r7, #8] 8010a1c: 2300 movs r3, #0 8010a1e: 623b str r3, [r7, #32] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 8010a20: 687b ldr r3, [r7, #4] 8010a22: 3b01 subs r3, #1 8010a24: 2b0f cmp r3, #15 8010a26: f200 811d bhi.w 8010c64 8010a2a: a201 add r2, pc, #4 @ (adr r2, 8010a30 ) 8010a2c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8010a30: 08010be5 .word 0x08010be5 8010a34: 08010c49 .word 0x08010c49 8010a38: 08010c65 .word 0x08010c65 8010a3c: 08010b43 .word 0x08010b43 8010a40: 08010c65 .word 0x08010c65 8010a44: 08010c65 .word 0x08010c65 8010a48: 08010c65 .word 0x08010c65 8010a4c: 08010b95 .word 0x08010b95 8010a50: 08010c65 .word 0x08010c65 8010a54: 08010c65 .word 0x08010c65 8010a58: 08010c65 .word 0x08010c65 8010a5c: 08010c65 .word 0x08010c65 8010a60: 08010c65 .word 0x08010c65 8010a64: 08010c65 .word 0x08010c65 8010a68: 08010c65 .word 0x08010c65 8010a6c: 08010a71 .word 0x08010a71 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_USB: { /* Get RCC configuration ------------------------------------------------------*/ temp_reg = RCC->CFGR; 8010a70: 4b83 ldr r3, [pc, #524] @ (8010c80 ) 8010a72: 685b ldr r3, [r3, #4] 8010a74: 60bb str r3, [r7, #8] /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) 8010a76: 4b82 ldr r3, [pc, #520] @ (8010c80 ) 8010a78: 681b ldr r3, [r3, #0] 8010a7a: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8010a7e: 2b00 cmp r3, #0 8010a80: f000 80f2 beq.w 8010c68 { pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8010a84: 68bb ldr r3, [r7, #8] 8010a86: 0c9b lsrs r3, r3, #18 8010a88: f003 030f and.w r3, r3, #15 8010a8c: 4a7d ldr r2, [pc, #500] @ (8010c84 ) 8010a8e: 5cd3 ldrb r3, [r2, r3] 8010a90: 61bb str r3, [r7, #24] if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8010a92: 68bb ldr r3, [r7, #8] 8010a94: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010a98: 2b00 cmp r3, #0 8010a9a: d03b beq.n 8010b14 { #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ || defined(STM32F100xE) prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 8010a9c: 4b78 ldr r3, [pc, #480] @ (8010c80 ) 8010a9e: 6adb ldr r3, [r3, #44] @ 0x2c 8010aa0: f003 030f and.w r3, r3, #15 8010aa4: 4a78 ldr r2, [pc, #480] @ (8010c88 ) 8010aa6: 5cd3 ldrb r3, [r2, r3] 8010aa8: 61fb str r3, [r7, #28] #else prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 8010aaa: 4b75 ldr r3, [pc, #468] @ (8010c80 ) 8010aac: 6adb ldr r3, [r3, #44] @ 0x2c 8010aae: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010ab2: 2b00 cmp r3, #0 8010ab4: d01c beq.n 8010af0 { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8010ab6: 4b72 ldr r3, [pc, #456] @ (8010c80 ) 8010ab8: 6adb ldr r3, [r3, #44] @ 0x2c 8010aba: 091b lsrs r3, r3, #4 8010abc: f003 030f and.w r3, r3, #15 8010ac0: 3301 adds r3, #1 8010ac2: 60fb str r3, [r7, #12] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 8010ac4: 4b6e ldr r3, [pc, #440] @ (8010c80 ) 8010ac6: 6adb ldr r3, [r3, #44] @ 0x2c 8010ac8: 0a1b lsrs r3, r3, #8 8010aca: f003 030f and.w r3, r3, #15 8010ace: 3302 adds r3, #2 8010ad0: 617b str r3, [r7, #20] pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); 8010ad2: 4a6e ldr r2, [pc, #440] @ (8010c8c ) 8010ad4: 68fb ldr r3, [r7, #12] 8010ad6: fbb2 f3f3 udiv r3, r2, r3 8010ada: 697a ldr r2, [r7, #20] 8010adc: fb03 f202 mul.w r2, r3, r2 8010ae0: 69fb ldr r3, [r7, #28] 8010ae2: fbb2 f2f3 udiv r2, r2, r3 8010ae6: 69bb ldr r3, [r7, #24] 8010ae8: fb02 f303 mul.w r3, r2, r3 8010aec: 627b str r3, [r7, #36] @ 0x24 8010aee: e007 b.n 8010b00 } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); 8010af0: 4a66 ldr r2, [pc, #408] @ (8010c8c ) 8010af2: 69fb ldr r3, [r7, #28] 8010af4: fbb2 f2f3 udiv r2, r2, r3 8010af8: 69bb ldr r3, [r7, #24] 8010afa: fb02 f303 mul.w r3, r2, r3 8010afe: 627b str r3, [r7, #36] @ 0x24 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 8010b00: 4b60 ldr r3, [pc, #384] @ (8010c84 ) 8010b02: 7b5b ldrb r3, [r3, #13] 8010b04: 461a mov r2, r3 8010b06: 69bb ldr r3, [r7, #24] 8010b08: 4293 cmp r3, r2 8010b0a: d108 bne.n 8010b1e { pllclk = pllclk / 2; 8010b0c: 6a7b ldr r3, [r7, #36] @ 0x24 8010b0e: 085b lsrs r3, r3, #1 8010b10: 627b str r3, [r7, #36] @ 0x24 8010b12: e004 b.n 8010b1e #endif /* STM32F105xC || STM32F107xC */ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8010b14: 69bb ldr r3, [r7, #24] 8010b16: 4a5e ldr r2, [pc, #376] @ (8010c90 ) 8010b18: fb02 f303 mul.w r3, r2, r3 8010b1c: 627b str r3, [r7, #36] @ 0x24 } /* Calcul of the USB frequency*/ #if defined(STM32F105xC) || defined(STM32F107xC) /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) 8010b1e: 4b58 ldr r3, [pc, #352] @ (8010c80 ) 8010b20: 685b ldr r3, [r3, #4] 8010b22: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8010b26: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8010b2a: d102 bne.n 8010b32 { /* Prescaler of 2 selected for USB */ frequency = pllclk; 8010b2c: 6a7b ldr r3, [r7, #36] @ 0x24 8010b2e: 623b str r3, [r7, #32] /* Prescaler of 1.5 selected for USB */ frequency = (pllclk * 2) / 3; } #endif } break; 8010b30: e09a b.n 8010c68 frequency = (2 * pllclk) / 3; 8010b32: 6a7b ldr r3, [r7, #36] @ 0x24 8010b34: 005b lsls r3, r3, #1 8010b36: 4a57 ldr r2, [pc, #348] @ (8010c94 ) 8010b38: fba2 2303 umull r2, r3, r2, r3 8010b3c: 085b lsrs r3, r3, #1 8010b3e: 623b str r3, [r7, #32] break; 8010b40: e092 b.n 8010c68 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) 8010b42: 4b4f ldr r3, [pc, #316] @ (8010c80 ) 8010b44: 6adb ldr r3, [r3, #44] @ 0x2c 8010b46: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010b4a: 2b00 cmp r3, #0 8010b4c: d103 bne.n 8010b56 { /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); 8010b4e: f7ff fd15 bl 801057c 8010b52: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8010b54: e08a b.n 8010c6c if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8010b56: 4b4a ldr r3, [pc, #296] @ (8010c80 ) 8010b58: 681b ldr r3, [r3, #0] 8010b5a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010b5e: 2b00 cmp r3, #0 8010b60: f000 8084 beq.w 8010c6c prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8010b64: 4b46 ldr r3, [pc, #280] @ (8010c80 ) 8010b66: 6adb ldr r3, [r3, #44] @ 0x2c 8010b68: 091b lsrs r3, r3, #4 8010b6a: f003 030f and.w r3, r3, #15 8010b6e: 3301 adds r3, #1 8010b70: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 8010b72: 4b43 ldr r3, [pc, #268] @ (8010c80 ) 8010b74: 6adb ldr r3, [r3, #44] @ 0x2c 8010b76: 0b1b lsrs r3, r3, #12 8010b78: f003 030f and.w r3, r3, #15 8010b7c: 3302 adds r3, #2 8010b7e: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8010b80: 4a42 ldr r2, [pc, #264] @ (8010c8c ) 8010b82: 68fb ldr r3, [r7, #12] 8010b84: fbb2 f3f3 udiv r3, r2, r3 8010b88: 693a ldr r2, [r7, #16] 8010b8a: fb02 f303 mul.w r3, r2, r3 8010b8e: 005b lsls r3, r3, #1 8010b90: 623b str r3, [r7, #32] break; 8010b92: e06b b.n 8010c6c { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) 8010b94: 4b3a ldr r3, [pc, #232] @ (8010c80 ) 8010b96: 6adb ldr r3, [r3, #44] @ 0x2c 8010b98: f403 2380 and.w r3, r3, #262144 @ 0x40000 8010b9c: 2b00 cmp r3, #0 8010b9e: d103 bne.n 8010ba8 { /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); 8010ba0: f7ff fcec bl 801057c 8010ba4: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8010ba6: e063 b.n 8010c70 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8010ba8: 4b35 ldr r3, [pc, #212] @ (8010c80 ) 8010baa: 681b ldr r3, [r3, #0] 8010bac: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010bb0: 2b00 cmp r3, #0 8010bb2: d05d beq.n 8010c70 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8010bb4: 4b32 ldr r3, [pc, #200] @ (8010c80 ) 8010bb6: 6adb ldr r3, [r3, #44] @ 0x2c 8010bb8: 091b lsrs r3, r3, #4 8010bba: f003 030f and.w r3, r3, #15 8010bbe: 3301 adds r3, #1 8010bc0: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 8010bc2: 4b2f ldr r3, [pc, #188] @ (8010c80 ) 8010bc4: 6adb ldr r3, [r3, #44] @ 0x2c 8010bc6: 0b1b lsrs r3, r3, #12 8010bc8: f003 030f and.w r3, r3, #15 8010bcc: 3302 adds r3, #2 8010bce: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8010bd0: 4a2e ldr r2, [pc, #184] @ (8010c8c ) 8010bd2: 68fb ldr r3, [r7, #12] 8010bd4: fbb2 f3f3 udiv r3, r2, r3 8010bd8: 693a ldr r2, [r7, #16] 8010bda: fb02 f303 mul.w r3, r2, r3 8010bde: 005b lsls r3, r3, #1 8010be0: 623b str r3, [r7, #32] break; 8010be2: e045 b.n 8010c70 } #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ case RCC_PERIPHCLK_RTC: { /* Get RCC BDCR configuration ------------------------------------------------------*/ temp_reg = RCC->BDCR; 8010be4: 4b26 ldr r3, [pc, #152] @ (8010c80 ) 8010be6: 6a1b ldr r3, [r3, #32] 8010be8: 60bb str r3, [r7, #8] /* Check if LSE is ready if RTC clock selection is LSE */ if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 8010bea: 68bb ldr r3, [r7, #8] 8010bec: f403 7340 and.w r3, r3, #768 @ 0x300 8010bf0: f5b3 7f80 cmp.w r3, #256 @ 0x100 8010bf4: d108 bne.n 8010c08 8010bf6: 68bb ldr r3, [r7, #8] 8010bf8: f003 0302 and.w r3, r3, #2 8010bfc: 2b00 cmp r3, #0 8010bfe: d003 beq.n 8010c08 { frequency = LSE_VALUE; 8010c00: f44f 4300 mov.w r3, #32768 @ 0x8000 8010c04: 623b str r3, [r7, #32] 8010c06: e01e b.n 8010c46 } /* Check if LSI is ready if RTC clock selection is LSI */ else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 8010c08: 68bb ldr r3, [r7, #8] 8010c0a: f403 7340 and.w r3, r3, #768 @ 0x300 8010c0e: f5b3 7f00 cmp.w r3, #512 @ 0x200 8010c12: d109 bne.n 8010c28 8010c14: 4b1a ldr r3, [pc, #104] @ (8010c80 ) 8010c16: 6a5b ldr r3, [r3, #36] @ 0x24 8010c18: f003 0302 and.w r3, r3, #2 8010c1c: 2b00 cmp r3, #0 8010c1e: d003 beq.n 8010c28 { frequency = LSI_VALUE; 8010c20: f649 4340 movw r3, #40000 @ 0x9c40 8010c24: 623b str r3, [r7, #32] 8010c26: e00e b.n 8010c46 } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 8010c28: 68bb ldr r3, [r7, #8] 8010c2a: f403 7340 and.w r3, r3, #768 @ 0x300 8010c2e: f5b3 7f40 cmp.w r3, #768 @ 0x300 8010c32: d11f bne.n 8010c74 8010c34: 4b12 ldr r3, [pc, #72] @ (8010c80 ) 8010c36: 681b ldr r3, [r3, #0] 8010c38: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010c3c: 2b00 cmp r3, #0 8010c3e: d019 beq.n 8010c74 { frequency = HSE_VALUE / 128U; 8010c40: 4b15 ldr r3, [pc, #84] @ (8010c98 ) 8010c42: 623b str r3, [r7, #32] /* Clock not enabled for RTC*/ else { /* nothing to do: frequency already initialized to 0U */ } break; 8010c44: e016 b.n 8010c74 8010c46: e015 b.n 8010c74 } case RCC_PERIPHCLK_ADC: { frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 8010c48: f7ff fd72 bl 8010730 8010c4c: 4602 mov r2, r0 8010c4e: 4b0c ldr r3, [pc, #48] @ (8010c80 ) 8010c50: 685b ldr r3, [r3, #4] 8010c52: 0b9b lsrs r3, r3, #14 8010c54: f003 0303 and.w r3, r3, #3 8010c58: 3301 adds r3, #1 8010c5a: 005b lsls r3, r3, #1 8010c5c: fbb2 f3f3 udiv r3, r2, r3 8010c60: 623b str r3, [r7, #32] break; 8010c62: e008 b.n 8010c76 } default: { break; 8010c64: bf00 nop 8010c66: e006 b.n 8010c76 break; 8010c68: bf00 nop 8010c6a: e004 b.n 8010c76 break; 8010c6c: bf00 nop 8010c6e: e002 b.n 8010c76 break; 8010c70: bf00 nop 8010c72: e000 b.n 8010c76 break; 8010c74: bf00 nop } } return (frequency); 8010c76: 6a3b ldr r3, [r7, #32] } 8010c78: 4618 mov r0, r3 8010c7a: 3728 adds r7, #40 @ 0x28 8010c7c: 46bd mov sp, r7 8010c7e: bd80 pop {r7, pc} 8010c80: 40021000 .word 0x40021000 8010c84: 08016128 .word 0x08016128 8010c88: 08016138 .word 0x08016138 8010c8c: 017d7840 .word 0x017d7840 8010c90: 003d0900 .word 0x003d0900 8010c94: aaaaaaab .word 0xaaaaaaab 8010c98: 0002faf0 .word 0x0002faf0 08010c9c : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { 8010c9c: b580 push {r7, lr} 8010c9e: b084 sub sp, #16 8010ca0: af00 add r7, sp, #0 8010ca2: 6078 str r0, [r7, #4] uint32_t prescaler = 0U; 8010ca4: 2300 movs r3, #0 8010ca6: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8010ca8: 687b ldr r3, [r7, #4] 8010caa: 2b00 cmp r3, #0 8010cac: d101 bne.n 8010cb2 { return HAL_ERROR; 8010cae: 2301 movs r3, #1 8010cb0: e07a b.n 8010da8 { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else if (hrtc->State == HAL_RTC_STATE_RESET) 8010cb2: 687b ldr r3, [r7, #4] 8010cb4: 7c5b ldrb r3, [r3, #17] 8010cb6: b2db uxtb r3, r3 8010cb8: 2b00 cmp r3, #0 8010cba: d105 bne.n 8010cc8 { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; 8010cbc: 687b ldr r3, [r7, #4] 8010cbe: 2200 movs r2, #0 8010cc0: 741a strb r2, [r3, #16] /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); 8010cc2: 6878 ldr r0, [r7, #4] 8010cc4: f7fa ff18 bl 800baf8 } #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; 8010cc8: 687b ldr r3, [r7, #4] 8010cca: 2202 movs r2, #2 8010ccc: 745a strb r2, [r3, #17] /* Waiting for synchro */ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 8010cce: 6878 ldr r0, [r7, #4] 8010cd0: f000 f870 bl 8010db4 8010cd4: 4603 mov r3, r0 8010cd6: 2b00 cmp r3, #0 8010cd8: d004 beq.n 8010ce4 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8010cda: 687b ldr r3, [r7, #4] 8010cdc: 2204 movs r2, #4 8010cde: 745a strb r2, [r3, #17] return HAL_ERROR; 8010ce0: 2301 movs r3, #1 8010ce2: e061 b.n 8010da8 } /* Set Initialization mode */ if (RTC_EnterInitMode(hrtc) != HAL_OK) 8010ce4: 6878 ldr r0, [r7, #4] 8010ce6: f000 f892 bl 8010e0e 8010cea: 4603 mov r3, r0 8010cec: 2b00 cmp r3, #0 8010cee: d004 beq.n 8010cfa { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8010cf0: 687b ldr r3, [r7, #4] 8010cf2: 2204 movs r2, #4 8010cf4: 745a strb r2, [r3, #17] return HAL_ERROR; 8010cf6: 2301 movs r3, #1 8010cf8: e056 b.n 8010da8 } else { /* Clear Flags Bits */ CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); 8010cfa: 687b ldr r3, [r7, #4] 8010cfc: 681b ldr r3, [r3, #0] 8010cfe: 685a ldr r2, [r3, #4] 8010d00: 687b ldr r3, [r7, #4] 8010d02: 681b ldr r3, [r3, #0] 8010d04: f022 0207 bic.w r2, r2, #7 8010d08: 605a str r2, [r3, #4] if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) 8010d0a: 687b ldr r3, [r7, #4] 8010d0c: 689b ldr r3, [r3, #8] 8010d0e: 2b00 cmp r3, #0 8010d10: d005 beq.n 8010d1e { /* Disable the selected Tamper pin */ CLEAR_BIT(BKP->CR, BKP_CR_TPE); 8010d12: 4b27 ldr r3, [pc, #156] @ (8010db0 ) 8010d14: 6b1b ldr r3, [r3, #48] @ 0x30 8010d16: 4a26 ldr r2, [pc, #152] @ (8010db0 ) 8010d18: f023 0301 bic.w r3, r3, #1 8010d1c: 6313 str r3, [r2, #48] @ 0x30 } /* Set the signal which will be routed to RTC Tamper pin*/ MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); 8010d1e: 4b24 ldr r3, [pc, #144] @ (8010db0 ) 8010d20: 6adb ldr r3, [r3, #44] @ 0x2c 8010d22: f423 7260 bic.w r2, r3, #896 @ 0x380 8010d26: 687b ldr r3, [r7, #4] 8010d28: 689b ldr r3, [r3, #8] 8010d2a: 4921 ldr r1, [pc, #132] @ (8010db0 ) 8010d2c: 4313 orrs r3, r2 8010d2e: 62cb str r3, [r1, #44] @ 0x2c if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) 8010d30: 687b ldr r3, [r7, #4] 8010d32: 685b ldr r3, [r3, #4] 8010d34: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8010d38: d003 beq.n 8010d42 { /* RTC Prescaler provided directly by end-user*/ prescaler = hrtc->Init.AsynchPrediv; 8010d3a: 687b ldr r3, [r7, #4] 8010d3c: 685b ldr r3, [r3, #4] 8010d3e: 60fb str r3, [r7, #12] 8010d40: e00e b.n 8010d60 } else { /* RTC Prescaler will be automatically calculated to get 1 second timebase */ /* Get the RTCCLK frequency */ prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); 8010d42: 2001 movs r0, #1 8010d44: f7ff fe58 bl 80109f8 8010d48: 60f8 str r0, [r7, #12] /* Check that RTC clock is enabled*/ if (prescaler == 0U) 8010d4a: 68fb ldr r3, [r7, #12] 8010d4c: 2b00 cmp r3, #0 8010d4e: d104 bne.n 8010d5a { /* Should not happen. Frequency is not available*/ hrtc->State = HAL_RTC_STATE_ERROR; 8010d50: 687b ldr r3, [r7, #4] 8010d52: 2204 movs r2, #4 8010d54: 745a strb r2, [r3, #17] return HAL_ERROR; 8010d56: 2301 movs r3, #1 8010d58: e026 b.n 8010da8 } else { /* RTC period = RTCCLK/(RTC_PR + 1) */ prescaler = prescaler - 1U; 8010d5a: 68fb ldr r3, [r7, #12] 8010d5c: 3b01 subs r3, #1 8010d5e: 60fb str r3, [r7, #12] } } /* Configure the RTC_PRLH / RTC_PRLL */ WRITE_REG(hrtc->Instance->PRLH, ((prescaler >> 16U) & RTC_PRLH_PRL)); 8010d60: 68fb ldr r3, [r7, #12] 8010d62: 0c1a lsrs r2, r3, #16 8010d64: 687b ldr r3, [r7, #4] 8010d66: 681b ldr r3, [r3, #0] 8010d68: f002 020f and.w r2, r2, #15 8010d6c: 609a str r2, [r3, #8] WRITE_REG(hrtc->Instance->PRLL, (prescaler & RTC_PRLL_PRL)); 8010d6e: 687b ldr r3, [r7, #4] 8010d70: 681b ldr r3, [r3, #0] 8010d72: 68fa ldr r2, [r7, #12] 8010d74: b292 uxth r2, r2 8010d76: 60da str r2, [r3, #12] /* Wait for synchro */ if (RTC_ExitInitMode(hrtc) != HAL_OK) 8010d78: 6878 ldr r0, [r7, #4] 8010d7a: f000 f870 bl 8010e5e 8010d7e: 4603 mov r3, r0 8010d80: 2b00 cmp r3, #0 8010d82: d004 beq.n 8010d8e { hrtc->State = HAL_RTC_STATE_ERROR; 8010d84: 687b ldr r3, [r7, #4] 8010d86: 2204 movs r2, #4 8010d88: 745a strb r2, [r3, #17] return HAL_ERROR; 8010d8a: 2301 movs r3, #1 8010d8c: e00c b.n 8010da8 } /* Initialize date to 1st of January 2000 */ hrtc->DateToUpdate.Year = 0x00U; 8010d8e: 687b ldr r3, [r7, #4] 8010d90: 2200 movs r2, #0 8010d92: 73da strb r2, [r3, #15] hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; 8010d94: 687b ldr r3, [r7, #4] 8010d96: 2201 movs r2, #1 8010d98: 735a strb r2, [r3, #13] hrtc->DateToUpdate.Date = 0x01U; 8010d9a: 687b ldr r3, [r7, #4] 8010d9c: 2201 movs r2, #1 8010d9e: 739a strb r2, [r3, #14] /* Set RTC state */ hrtc->State = HAL_RTC_STATE_READY; 8010da0: 687b ldr r3, [r7, #4] 8010da2: 2201 movs r2, #1 8010da4: 745a strb r2, [r3, #17] return HAL_OK; 8010da6: 2300 movs r3, #0 } } 8010da8: 4618 mov r0, r3 8010daa: 3710 adds r7, #16 8010dac: 46bd mov sp, r7 8010dae: bd80 pop {r7, pc} 8010db0: 40006c00 .word 0x40006c00 08010db4 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { 8010db4: b580 push {r7, lr} 8010db6: b084 sub sp, #16 8010db8: af00 add r7, sp, #0 8010dba: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8010dbc: 2300 movs r3, #0 8010dbe: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8010dc0: 687b ldr r3, [r7, #4] 8010dc2: 2b00 cmp r3, #0 8010dc4: d101 bne.n 8010dca { return HAL_ERROR; 8010dc6: 2301 movs r3, #1 8010dc8: e01d b.n 8010e06 } /* Clear RSF flag */ CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); 8010dca: 687b ldr r3, [r7, #4] 8010dcc: 681b ldr r3, [r3, #0] 8010dce: 685a ldr r2, [r3, #4] 8010dd0: 687b ldr r3, [r7, #4] 8010dd2: 681b ldr r3, [r3, #0] 8010dd4: f022 0208 bic.w r2, r2, #8 8010dd8: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8010dda: f7fc fec9 bl 800db70 8010dde: 60f8 str r0, [r7, #12] /* Wait the registers to be synchronised */ while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8010de0: e009 b.n 8010df6 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8010de2: f7fc fec5 bl 800db70 8010de6: 4602 mov r2, r0 8010de8: 68fb ldr r3, [r7, #12] 8010dea: 1ad3 subs r3, r2, r3 8010dec: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8010df0: d901 bls.n 8010df6 { return HAL_TIMEOUT; 8010df2: 2303 movs r3, #3 8010df4: e007 b.n 8010e06 while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8010df6: 687b ldr r3, [r7, #4] 8010df8: 681b ldr r3, [r3, #0] 8010dfa: 685b ldr r3, [r3, #4] 8010dfc: f003 0308 and.w r3, r3, #8 8010e00: 2b00 cmp r3, #0 8010e02: d0ee beq.n 8010de2 } } return HAL_OK; 8010e04: 2300 movs r3, #0 } 8010e06: 4618 mov r0, r3 8010e08: 3710 adds r7, #16 8010e0a: 46bd mov sp, r7 8010e0c: bd80 pop {r7, pc} 08010e0e : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { 8010e0e: b580 push {r7, lr} 8010e10: b084 sub sp, #16 8010e12: af00 add r7, sp, #0 8010e14: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8010e16: 2300 movs r3, #0 8010e18: 60fb str r3, [r7, #12] tickstart = HAL_GetTick(); 8010e1a: f7fc fea9 bl 800db70 8010e1e: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8010e20: e009 b.n 8010e36 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8010e22: f7fc fea5 bl 800db70 8010e26: 4602 mov r2, r0 8010e28: 68fb ldr r3, [r7, #12] 8010e2a: 1ad3 subs r3, r2, r3 8010e2c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8010e30: d901 bls.n 8010e36 { return HAL_TIMEOUT; 8010e32: 2303 movs r3, #3 8010e34: e00f b.n 8010e56 while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8010e36: 687b ldr r3, [r7, #4] 8010e38: 681b ldr r3, [r3, #0] 8010e3a: 685b ldr r3, [r3, #4] 8010e3c: f003 0320 and.w r3, r3, #32 8010e40: 2b00 cmp r3, #0 8010e42: d0ee beq.n 8010e22 } } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 8010e44: 687b ldr r3, [r7, #4] 8010e46: 681b ldr r3, [r3, #0] 8010e48: 685a ldr r2, [r3, #4] 8010e4a: 687b ldr r3, [r7, #4] 8010e4c: 681b ldr r3, [r3, #0] 8010e4e: f042 0210 orr.w r2, r2, #16 8010e52: 605a str r2, [r3, #4] return HAL_OK; 8010e54: 2300 movs r3, #0 } 8010e56: 4618 mov r0, r3 8010e58: 3710 adds r7, #16 8010e5a: 46bd mov sp, r7 8010e5c: bd80 pop {r7, pc} 08010e5e : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) { 8010e5e: b580 push {r7, lr} 8010e60: b084 sub sp, #16 8010e62: af00 add r7, sp, #0 8010e64: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8010e66: 2300 movs r3, #0 8010e68: 60fb str r3, [r7, #12] /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 8010e6a: 687b ldr r3, [r7, #4] 8010e6c: 681b ldr r3, [r3, #0] 8010e6e: 685a ldr r2, [r3, #4] 8010e70: 687b ldr r3, [r7, #4] 8010e72: 681b ldr r3, [r3, #0] 8010e74: f022 0210 bic.w r2, r2, #16 8010e78: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8010e7a: f7fc fe79 bl 800db70 8010e7e: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8010e80: e009 b.n 8010e96 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8010e82: f7fc fe75 bl 800db70 8010e86: 4602 mov r2, r0 8010e88: 68fb ldr r3, [r7, #12] 8010e8a: 1ad3 subs r3, r2, r3 8010e8c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8010e90: d901 bls.n 8010e96 { return HAL_TIMEOUT; 8010e92: 2303 movs r3, #3 8010e94: e007 b.n 8010ea6 while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8010e96: 687b ldr r3, [r7, #4] 8010e98: 681b ldr r3, [r3, #0] 8010e9a: 685b ldr r3, [r3, #4] 8010e9c: f003 0320 and.w r3, r3, #32 8010ea0: 2b00 cmp r3, #0 8010ea2: d0ee beq.n 8010e82 } } return HAL_OK; 8010ea4: 2300 movs r3, #0 } 8010ea6: 4618 mov r0, r3 8010ea8: 3710 adds r7, #16 8010eaa: 46bd mov sp, r7 8010eac: bd80 pop {r7, pc} 08010eae : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8010eae: b580 push {r7, lr} 8010eb0: b082 sub sp, #8 8010eb2: af00 add r7, sp, #0 8010eb4: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8010eb6: 687b ldr r3, [r7, #4] 8010eb8: 2b00 cmp r3, #0 8010eba: d101 bne.n 8010ec0 { return HAL_ERROR; 8010ebc: 2301 movs r3, #1 8010ebe: e041 b.n 8010f44 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8010ec0: 687b ldr r3, [r7, #4] 8010ec2: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8010ec6: b2db uxtb r3, r3 8010ec8: 2b00 cmp r3, #0 8010eca: d106 bne.n 8010eda { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8010ecc: 687b ldr r3, [r7, #4] 8010ece: 2200 movs r2, #0 8010ed0: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8010ed4: 6878 ldr r0, [r7, #4] 8010ed6: f7fc fb3b bl 800d550 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8010eda: 687b ldr r3, [r7, #4] 8010edc: 2202 movs r2, #2 8010ede: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8010ee2: 687b ldr r3, [r7, #4] 8010ee4: 681a ldr r2, [r3, #0] 8010ee6: 687b ldr r3, [r7, #4] 8010ee8: 3304 adds r3, #4 8010eea: 4619 mov r1, r3 8010eec: 4610 mov r0, r2 8010eee: f000 fcc3 bl 8011878 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8010ef2: 687b ldr r3, [r7, #4] 8010ef4: 2201 movs r2, #1 8010ef6: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8010efa: 687b ldr r3, [r7, #4] 8010efc: 2201 movs r2, #1 8010efe: f883 203e strb.w r2, [r3, #62] @ 0x3e 8010f02: 687b ldr r3, [r7, #4] 8010f04: 2201 movs r2, #1 8010f06: f883 203f strb.w r2, [r3, #63] @ 0x3f 8010f0a: 687b ldr r3, [r7, #4] 8010f0c: 2201 movs r2, #1 8010f0e: f883 2040 strb.w r2, [r3, #64] @ 0x40 8010f12: 687b ldr r3, [r7, #4] 8010f14: 2201 movs r2, #1 8010f16: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8010f1a: 687b ldr r3, [r7, #4] 8010f1c: 2201 movs r2, #1 8010f1e: f883 2042 strb.w r2, [r3, #66] @ 0x42 8010f22: 687b ldr r3, [r7, #4] 8010f24: 2201 movs r2, #1 8010f26: f883 2043 strb.w r2, [r3, #67] @ 0x43 8010f2a: 687b ldr r3, [r7, #4] 8010f2c: 2201 movs r2, #1 8010f2e: f883 2044 strb.w r2, [r3, #68] @ 0x44 8010f32: 687b ldr r3, [r7, #4] 8010f34: 2201 movs r2, #1 8010f36: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8010f3a: 687b ldr r3, [r7, #4] 8010f3c: 2201 movs r2, #1 8010f3e: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8010f42: 2300 movs r3, #0 } 8010f44: 4618 mov r0, r3 8010f46: 3708 adds r7, #8 8010f48: 46bd mov sp, r7 8010f4a: bd80 pop {r7, pc} 08010f4c : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { 8010f4c: b580 push {r7, lr} 8010f4e: b084 sub sp, #16 8010f50: af00 add r7, sp, #0 8010f52: 6078 str r0, [r7, #4] 8010f54: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8010f56: 2300 movs r3, #0 8010f58: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 8010f5a: 683b ldr r3, [r7, #0] 8010f5c: 2b00 cmp r3, #0 8010f5e: d109 bne.n 8010f74 8010f60: 687b ldr r3, [r7, #4] 8010f62: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8010f66: b2db uxtb r3, r3 8010f68: 2b01 cmp r3, #1 8010f6a: bf14 ite ne 8010f6c: 2301 movne r3, #1 8010f6e: 2300 moveq r3, #0 8010f70: b2db uxtb r3, r3 8010f72: e022 b.n 8010fba 8010f74: 683b ldr r3, [r7, #0] 8010f76: 2b04 cmp r3, #4 8010f78: d109 bne.n 8010f8e 8010f7a: 687b ldr r3, [r7, #4] 8010f7c: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8010f80: b2db uxtb r3, r3 8010f82: 2b01 cmp r3, #1 8010f84: bf14 ite ne 8010f86: 2301 movne r3, #1 8010f88: 2300 moveq r3, #0 8010f8a: b2db uxtb r3, r3 8010f8c: e015 b.n 8010fba 8010f8e: 683b ldr r3, [r7, #0] 8010f90: 2b08 cmp r3, #8 8010f92: d109 bne.n 8010fa8 8010f94: 687b ldr r3, [r7, #4] 8010f96: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8010f9a: b2db uxtb r3, r3 8010f9c: 2b01 cmp r3, #1 8010f9e: bf14 ite ne 8010fa0: 2301 movne r3, #1 8010fa2: 2300 moveq r3, #0 8010fa4: b2db uxtb r3, r3 8010fa6: e008 b.n 8010fba 8010fa8: 687b ldr r3, [r7, #4] 8010faa: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8010fae: b2db uxtb r3, r3 8010fb0: 2b01 cmp r3, #1 8010fb2: bf14 ite ne 8010fb4: 2301 movne r3, #1 8010fb6: 2300 moveq r3, #0 8010fb8: b2db uxtb r3, r3 8010fba: 2b00 cmp r3, #0 8010fbc: d001 beq.n 8010fc2 { return HAL_ERROR; 8010fbe: 2301 movs r3, #1 8010fc0: e0ae b.n 8011120 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8010fc2: 683b ldr r3, [r7, #0] 8010fc4: 2b00 cmp r3, #0 8010fc6: d104 bne.n 8010fd2 8010fc8: 687b ldr r3, [r7, #4] 8010fca: 2202 movs r2, #2 8010fcc: f883 203e strb.w r2, [r3, #62] @ 0x3e 8010fd0: e013 b.n 8010ffa 8010fd2: 683b ldr r3, [r7, #0] 8010fd4: 2b04 cmp r3, #4 8010fd6: d104 bne.n 8010fe2 8010fd8: 687b ldr r3, [r7, #4] 8010fda: 2202 movs r2, #2 8010fdc: f883 203f strb.w r2, [r3, #63] @ 0x3f 8010fe0: e00b b.n 8010ffa 8010fe2: 683b ldr r3, [r7, #0] 8010fe4: 2b08 cmp r3, #8 8010fe6: d104 bne.n 8010ff2 8010fe8: 687b ldr r3, [r7, #4] 8010fea: 2202 movs r2, #2 8010fec: f883 2040 strb.w r2, [r3, #64] @ 0x40 8010ff0: e003 b.n 8010ffa 8010ff2: 687b ldr r3, [r7, #4] 8010ff4: 2202 movs r2, #2 8010ff6: f883 2041 strb.w r2, [r3, #65] @ 0x41 switch (Channel) 8010ffa: 683b ldr r3, [r7, #0] 8010ffc: 2b0c cmp r3, #12 8010ffe: d841 bhi.n 8011084 8011000: a201 add r2, pc, #4 @ (adr r2, 8011008 ) 8011002: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011006: bf00 nop 8011008: 0801103d .word 0x0801103d 801100c: 08011085 .word 0x08011085 8011010: 08011085 .word 0x08011085 8011014: 08011085 .word 0x08011085 8011018: 0801104f .word 0x0801104f 801101c: 08011085 .word 0x08011085 8011020: 08011085 .word 0x08011085 8011024: 08011085 .word 0x08011085 8011028: 08011061 .word 0x08011061 801102c: 08011085 .word 0x08011085 8011030: 08011085 .word 0x08011085 8011034: 08011085 .word 0x08011085 8011038: 08011073 .word 0x08011073 { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 801103c: 687b ldr r3, [r7, #4] 801103e: 681b ldr r3, [r3, #0] 8011040: 68da ldr r2, [r3, #12] 8011042: 687b ldr r3, [r7, #4] 8011044: 681b ldr r3, [r3, #0] 8011046: f042 0202 orr.w r2, r2, #2 801104a: 60da str r2, [r3, #12] break; 801104c: e01d b.n 801108a } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 801104e: 687b ldr r3, [r7, #4] 8011050: 681b ldr r3, [r3, #0] 8011052: 68da ldr r2, [r3, #12] 8011054: 687b ldr r3, [r7, #4] 8011056: 681b ldr r3, [r3, #0] 8011058: f042 0204 orr.w r2, r2, #4 801105c: 60da str r2, [r3, #12] break; 801105e: e014 b.n 801108a } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 8011060: 687b ldr r3, [r7, #4] 8011062: 681b ldr r3, [r3, #0] 8011064: 68da ldr r2, [r3, #12] 8011066: 687b ldr r3, [r7, #4] 8011068: 681b ldr r3, [r3, #0] 801106a: f042 0208 orr.w r2, r2, #8 801106e: 60da str r2, [r3, #12] break; 8011070: e00b b.n 801108a } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 8011072: 687b ldr r3, [r7, #4] 8011074: 681b ldr r3, [r3, #0] 8011076: 68da ldr r2, [r3, #12] 8011078: 687b ldr r3, [r7, #4] 801107a: 681b ldr r3, [r3, #0] 801107c: f042 0210 orr.w r2, r2, #16 8011080: 60da str r2, [r3, #12] break; 8011082: e002 b.n 801108a } default: status = HAL_ERROR; 8011084: 2301 movs r3, #1 8011086: 73fb strb r3, [r7, #15] break; 8011088: bf00 nop } if (status == HAL_OK) 801108a: 7bfb ldrb r3, [r7, #15] 801108c: 2b00 cmp r3, #0 801108e: d146 bne.n 801111e { /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 8011090: 687b ldr r3, [r7, #4] 8011092: 681b ldr r3, [r3, #0] 8011094: 2201 movs r2, #1 8011096: 6839 ldr r1, [r7, #0] 8011098: 4618 mov r0, r3 801109a: f000 fe83 bl 8011da4 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 801109e: 687b ldr r3, [r7, #4] 80110a0: 681b ldr r3, [r3, #0] 80110a2: 4a21 ldr r2, [pc, #132] @ (8011128 ) 80110a4: 4293 cmp r3, r2 80110a6: d107 bne.n 80110b8 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 80110a8: 687b ldr r3, [r7, #4] 80110aa: 681b ldr r3, [r3, #0] 80110ac: 6c5a ldr r2, [r3, #68] @ 0x44 80110ae: 687b ldr r3, [r7, #4] 80110b0: 681b ldr r3, [r3, #0] 80110b2: f442 4200 orr.w r2, r2, #32768 @ 0x8000 80110b6: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80110b8: 687b ldr r3, [r7, #4] 80110ba: 681b ldr r3, [r3, #0] 80110bc: 4a1a ldr r2, [pc, #104] @ (8011128 ) 80110be: 4293 cmp r3, r2 80110c0: d013 beq.n 80110ea 80110c2: 687b ldr r3, [r7, #4] 80110c4: 681b ldr r3, [r3, #0] 80110c6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80110ca: d00e beq.n 80110ea 80110cc: 687b ldr r3, [r7, #4] 80110ce: 681b ldr r3, [r3, #0] 80110d0: 4a16 ldr r2, [pc, #88] @ (801112c ) 80110d2: 4293 cmp r3, r2 80110d4: d009 beq.n 80110ea 80110d6: 687b ldr r3, [r7, #4] 80110d8: 681b ldr r3, [r3, #0] 80110da: 4a15 ldr r2, [pc, #84] @ (8011130 ) 80110dc: 4293 cmp r3, r2 80110de: d004 beq.n 80110ea 80110e0: 687b ldr r3, [r7, #4] 80110e2: 681b ldr r3, [r3, #0] 80110e4: 4a13 ldr r2, [pc, #76] @ (8011134 ) 80110e6: 4293 cmp r3, r2 80110e8: d111 bne.n 801110e { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 80110ea: 687b ldr r3, [r7, #4] 80110ec: 681b ldr r3, [r3, #0] 80110ee: 689b ldr r3, [r3, #8] 80110f0: f003 0307 and.w r3, r3, #7 80110f4: 60bb str r3, [r7, #8] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80110f6: 68bb ldr r3, [r7, #8] 80110f8: 2b06 cmp r3, #6 80110fa: d010 beq.n 801111e { __HAL_TIM_ENABLE(htim); 80110fc: 687b ldr r3, [r7, #4] 80110fe: 681b ldr r3, [r3, #0] 8011100: 681a ldr r2, [r3, #0] 8011102: 687b ldr r3, [r7, #4] 8011104: 681b ldr r3, [r3, #0] 8011106: f042 0201 orr.w r2, r2, #1 801110a: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 801110c: e007 b.n 801111e } } else { __HAL_TIM_ENABLE(htim); 801110e: 687b ldr r3, [r7, #4] 8011110: 681b ldr r3, [r3, #0] 8011112: 681a ldr r2, [r3, #0] 8011114: 687b ldr r3, [r7, #4] 8011116: 681b ldr r3, [r3, #0] 8011118: f042 0201 orr.w r2, r2, #1 801111c: 601a str r2, [r3, #0] } } /* Return function status */ return status; 801111e: 7bfb ldrb r3, [r7, #15] } 8011120: 4618 mov r0, r3 8011122: 3710 adds r7, #16 8011124: 46bd mov sp, r7 8011126: bd80 pop {r7, pc} 8011128: 40012c00 .word 0x40012c00 801112c: 40000400 .word 0x40000400 8011130: 40000800 .word 0x40000800 8011134: 40000c00 .word 0x40000c00 08011138 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 8011138: b580 push {r7, lr} 801113a: b082 sub sp, #8 801113c: af00 add r7, sp, #0 801113e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8011140: 687b ldr r3, [r7, #4] 8011142: 2b00 cmp r3, #0 8011144: d101 bne.n 801114a { return HAL_ERROR; 8011146: 2301 movs r3, #1 8011148: e041 b.n 80111ce assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 801114a: 687b ldr r3, [r7, #4] 801114c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8011150: b2db uxtb r3, r3 8011152: 2b00 cmp r3, #0 8011154: d106 bne.n 8011164 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8011156: 687b ldr r3, [r7, #4] 8011158: 2200 movs r2, #0 801115a: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 801115e: 6878 ldr r0, [r7, #4] 8011160: f000 f839 bl 80111d6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8011164: 687b ldr r3, [r7, #4] 8011166: 2202 movs r2, #2 8011168: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 801116c: 687b ldr r3, [r7, #4] 801116e: 681a ldr r2, [r3, #0] 8011170: 687b ldr r3, [r7, #4] 8011172: 3304 adds r3, #4 8011174: 4619 mov r1, r3 8011176: 4610 mov r0, r2 8011178: f000 fb7e bl 8011878 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 801117c: 687b ldr r3, [r7, #4] 801117e: 2201 movs r2, #1 8011180: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011184: 687b ldr r3, [r7, #4] 8011186: 2201 movs r2, #1 8011188: f883 203e strb.w r2, [r3, #62] @ 0x3e 801118c: 687b ldr r3, [r7, #4] 801118e: 2201 movs r2, #1 8011190: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011194: 687b ldr r3, [r7, #4] 8011196: 2201 movs r2, #1 8011198: f883 2040 strb.w r2, [r3, #64] @ 0x40 801119c: 687b ldr r3, [r7, #4] 801119e: 2201 movs r2, #1 80111a0: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80111a4: 687b ldr r3, [r7, #4] 80111a6: 2201 movs r2, #1 80111a8: f883 2042 strb.w r2, [r3, #66] @ 0x42 80111ac: 687b ldr r3, [r7, #4] 80111ae: 2201 movs r2, #1 80111b0: f883 2043 strb.w r2, [r3, #67] @ 0x43 80111b4: 687b ldr r3, [r7, #4] 80111b6: 2201 movs r2, #1 80111b8: f883 2044 strb.w r2, [r3, #68] @ 0x44 80111bc: 687b ldr r3, [r7, #4] 80111be: 2201 movs r2, #1 80111c0: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80111c4: 687b ldr r3, [r7, #4] 80111c6: 2201 movs r2, #1 80111c8: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 80111cc: 2300 movs r3, #0 } 80111ce: 4618 mov r0, r3 80111d0: 3708 adds r7, #8 80111d2: 46bd mov sp, r7 80111d4: bd80 pop {r7, pc} 080111d6 : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 80111d6: b480 push {r7} 80111d8: b083 sub sp, #12 80111da: af00 add r7, sp, #0 80111dc: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 80111de: bf00 nop 80111e0: 370c adds r7, #12 80111e2: 46bd mov sp, r7 80111e4: bc80 pop {r7} 80111e6: 4770 bx lr 080111e8 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 80111e8: b580 push {r7, lr} 80111ea: b084 sub sp, #16 80111ec: af00 add r7, sp, #0 80111ee: 6078 str r0, [r7, #4] 80111f0: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 80111f2: 683b ldr r3, [r7, #0] 80111f4: 2b00 cmp r3, #0 80111f6: d109 bne.n 801120c 80111f8: 687b ldr r3, [r7, #4] 80111fa: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 80111fe: b2db uxtb r3, r3 8011200: 2b01 cmp r3, #1 8011202: bf14 ite ne 8011204: 2301 movne r3, #1 8011206: 2300 moveq r3, #0 8011208: b2db uxtb r3, r3 801120a: e022 b.n 8011252 801120c: 683b ldr r3, [r7, #0] 801120e: 2b04 cmp r3, #4 8011210: d109 bne.n 8011226 8011212: 687b ldr r3, [r7, #4] 8011214: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8011218: b2db uxtb r3, r3 801121a: 2b01 cmp r3, #1 801121c: bf14 ite ne 801121e: 2301 movne r3, #1 8011220: 2300 moveq r3, #0 8011222: b2db uxtb r3, r3 8011224: e015 b.n 8011252 8011226: 683b ldr r3, [r7, #0] 8011228: 2b08 cmp r3, #8 801122a: d109 bne.n 8011240 801122c: 687b ldr r3, [r7, #4] 801122e: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8011232: b2db uxtb r3, r3 8011234: 2b01 cmp r3, #1 8011236: bf14 ite ne 8011238: 2301 movne r3, #1 801123a: 2300 moveq r3, #0 801123c: b2db uxtb r3, r3 801123e: e008 b.n 8011252 8011240: 687b ldr r3, [r7, #4] 8011242: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011246: b2db uxtb r3, r3 8011248: 2b01 cmp r3, #1 801124a: bf14 ite ne 801124c: 2301 movne r3, #1 801124e: 2300 moveq r3, #0 8011250: b2db uxtb r3, r3 8011252: 2b00 cmp r3, #0 8011254: d001 beq.n 801125a { return HAL_ERROR; 8011256: 2301 movs r3, #1 8011258: e063 b.n 8011322 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 801125a: 683b ldr r3, [r7, #0] 801125c: 2b00 cmp r3, #0 801125e: d104 bne.n 801126a 8011260: 687b ldr r3, [r7, #4] 8011262: 2202 movs r2, #2 8011264: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011268: e013 b.n 8011292 801126a: 683b ldr r3, [r7, #0] 801126c: 2b04 cmp r3, #4 801126e: d104 bne.n 801127a 8011270: 687b ldr r3, [r7, #4] 8011272: 2202 movs r2, #2 8011274: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011278: e00b b.n 8011292 801127a: 683b ldr r3, [r7, #0] 801127c: 2b08 cmp r3, #8 801127e: d104 bne.n 801128a 8011280: 687b ldr r3, [r7, #4] 8011282: 2202 movs r2, #2 8011284: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011288: e003 b.n 8011292 801128a: 687b ldr r3, [r7, #4] 801128c: 2202 movs r2, #2 801128e: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 8011292: 687b ldr r3, [r7, #4] 8011294: 681b ldr r3, [r3, #0] 8011296: 2201 movs r2, #1 8011298: 6839 ldr r1, [r7, #0] 801129a: 4618 mov r0, r3 801129c: f000 fd82 bl 8011da4 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 80112a0: 687b ldr r3, [r7, #4] 80112a2: 681b ldr r3, [r3, #0] 80112a4: 4a21 ldr r2, [pc, #132] @ (801132c ) 80112a6: 4293 cmp r3, r2 80112a8: d107 bne.n 80112ba { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 80112aa: 687b ldr r3, [r7, #4] 80112ac: 681b ldr r3, [r3, #0] 80112ae: 6c5a ldr r2, [r3, #68] @ 0x44 80112b0: 687b ldr r3, [r7, #4] 80112b2: 681b ldr r3, [r3, #0] 80112b4: f442 4200 orr.w r2, r2, #32768 @ 0x8000 80112b8: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80112ba: 687b ldr r3, [r7, #4] 80112bc: 681b ldr r3, [r3, #0] 80112be: 4a1b ldr r2, [pc, #108] @ (801132c ) 80112c0: 4293 cmp r3, r2 80112c2: d013 beq.n 80112ec 80112c4: 687b ldr r3, [r7, #4] 80112c6: 681b ldr r3, [r3, #0] 80112c8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80112cc: d00e beq.n 80112ec 80112ce: 687b ldr r3, [r7, #4] 80112d0: 681b ldr r3, [r3, #0] 80112d2: 4a17 ldr r2, [pc, #92] @ (8011330 ) 80112d4: 4293 cmp r3, r2 80112d6: d009 beq.n 80112ec 80112d8: 687b ldr r3, [r7, #4] 80112da: 681b ldr r3, [r3, #0] 80112dc: 4a15 ldr r2, [pc, #84] @ (8011334 ) 80112de: 4293 cmp r3, r2 80112e0: d004 beq.n 80112ec 80112e2: 687b ldr r3, [r7, #4] 80112e4: 681b ldr r3, [r3, #0] 80112e6: 4a14 ldr r2, [pc, #80] @ (8011338 ) 80112e8: 4293 cmp r3, r2 80112ea: d111 bne.n 8011310 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 80112ec: 687b ldr r3, [r7, #4] 80112ee: 681b ldr r3, [r3, #0] 80112f0: 689b ldr r3, [r3, #8] 80112f2: f003 0307 and.w r3, r3, #7 80112f6: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80112f8: 68fb ldr r3, [r7, #12] 80112fa: 2b06 cmp r3, #6 80112fc: d010 beq.n 8011320 { __HAL_TIM_ENABLE(htim); 80112fe: 687b ldr r3, [r7, #4] 8011300: 681b ldr r3, [r3, #0] 8011302: 681a ldr r2, [r3, #0] 8011304: 687b ldr r3, [r7, #4] 8011306: 681b ldr r3, [r3, #0] 8011308: f042 0201 orr.w r2, r2, #1 801130c: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 801130e: e007 b.n 8011320 } } else { __HAL_TIM_ENABLE(htim); 8011310: 687b ldr r3, [r7, #4] 8011312: 681b ldr r3, [r3, #0] 8011314: 681a ldr r2, [r3, #0] 8011316: 687b ldr r3, [r7, #4] 8011318: 681b ldr r3, [r3, #0] 801131a: f042 0201 orr.w r2, r2, #1 801131e: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8011320: 2300 movs r3, #0 } 8011322: 4618 mov r0, r3 8011324: 3710 adds r7, #16 8011326: 46bd mov sp, r7 8011328: bd80 pop {r7, pc} 801132a: bf00 nop 801132c: 40012c00 .word 0x40012c00 8011330: 40000400 .word 0x40000400 8011334: 40000800 .word 0x40000800 8011338: 40000c00 .word 0x40000c00 0801133c : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 801133c: b580 push {r7, lr} 801133e: b084 sub sp, #16 8011340: af00 add r7, sp, #0 8011342: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 8011344: 687b ldr r3, [r7, #4] 8011346: 681b ldr r3, [r3, #0] 8011348: 68db ldr r3, [r3, #12] 801134a: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 801134c: 687b ldr r3, [r7, #4] 801134e: 681b ldr r3, [r3, #0] 8011350: 691b ldr r3, [r3, #16] 8011352: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 8011354: 68bb ldr r3, [r7, #8] 8011356: f003 0302 and.w r3, r3, #2 801135a: 2b00 cmp r3, #0 801135c: d020 beq.n 80113a0 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 801135e: 68fb ldr r3, [r7, #12] 8011360: f003 0302 and.w r3, r3, #2 8011364: 2b00 cmp r3, #0 8011366: d01b beq.n 80113a0 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 8011368: 687b ldr r3, [r7, #4] 801136a: 681b ldr r3, [r3, #0] 801136c: f06f 0202 mvn.w r2, #2 8011370: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 8011372: 687b ldr r3, [r7, #4] 8011374: 2201 movs r2, #1 8011376: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8011378: 687b ldr r3, [r7, #4] 801137a: 681b ldr r3, [r3, #0] 801137c: 699b ldr r3, [r3, #24] 801137e: f003 0303 and.w r3, r3, #3 8011382: 2b00 cmp r3, #0 8011384: d003 beq.n 801138e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8011386: 6878 ldr r0, [r7, #4] 8011388: f000 fa5a bl 8011840 801138c: e005 b.n 801139a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 801138e: 6878 ldr r0, [r7, #4] 8011390: f7f9 f804 bl 800a39c HAL_TIM_PWM_PulseFinishedCallback(htim); 8011394: 6878 ldr r0, [r7, #4] 8011396: f000 fa5c bl 8011852 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 801139a: 687b ldr r3, [r7, #4] 801139c: 2200 movs r2, #0 801139e: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 80113a0: 68bb ldr r3, [r7, #8] 80113a2: f003 0304 and.w r3, r3, #4 80113a6: 2b00 cmp r3, #0 80113a8: d020 beq.n 80113ec { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 80113aa: 68fb ldr r3, [r7, #12] 80113ac: f003 0304 and.w r3, r3, #4 80113b0: 2b00 cmp r3, #0 80113b2: d01b beq.n 80113ec { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 80113b4: 687b ldr r3, [r7, #4] 80113b6: 681b ldr r3, [r3, #0] 80113b8: f06f 0204 mvn.w r2, #4 80113bc: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 80113be: 687b ldr r3, [r7, #4] 80113c0: 2202 movs r2, #2 80113c2: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 80113c4: 687b ldr r3, [r7, #4] 80113c6: 681b ldr r3, [r3, #0] 80113c8: 699b ldr r3, [r3, #24] 80113ca: f403 7340 and.w r3, r3, #768 @ 0x300 80113ce: 2b00 cmp r3, #0 80113d0: d003 beq.n 80113da { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80113d2: 6878 ldr r0, [r7, #4] 80113d4: f000 fa34 bl 8011840 80113d8: e005 b.n 80113e6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80113da: 6878 ldr r0, [r7, #4] 80113dc: f7f8 ffde bl 800a39c HAL_TIM_PWM_PulseFinishedCallback(htim); 80113e0: 6878 ldr r0, [r7, #4] 80113e2: f000 fa36 bl 8011852 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80113e6: 687b ldr r3, [r7, #4] 80113e8: 2200 movs r2, #0 80113ea: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 80113ec: 68bb ldr r3, [r7, #8] 80113ee: f003 0308 and.w r3, r3, #8 80113f2: 2b00 cmp r3, #0 80113f4: d020 beq.n 8011438 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 80113f6: 68fb ldr r3, [r7, #12] 80113f8: f003 0308 and.w r3, r3, #8 80113fc: 2b00 cmp r3, #0 80113fe: d01b beq.n 8011438 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 8011400: 687b ldr r3, [r7, #4] 8011402: 681b ldr r3, [r3, #0] 8011404: f06f 0208 mvn.w r2, #8 8011408: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 801140a: 687b ldr r3, [r7, #4] 801140c: 2204 movs r2, #4 801140e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8011410: 687b ldr r3, [r7, #4] 8011412: 681b ldr r3, [r3, #0] 8011414: 69db ldr r3, [r3, #28] 8011416: f003 0303 and.w r3, r3, #3 801141a: 2b00 cmp r3, #0 801141c: d003 beq.n 8011426 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 801141e: 6878 ldr r0, [r7, #4] 8011420: f000 fa0e bl 8011840 8011424: e005 b.n 8011432 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8011426: 6878 ldr r0, [r7, #4] 8011428: f7f8 ffb8 bl 800a39c HAL_TIM_PWM_PulseFinishedCallback(htim); 801142c: 6878 ldr r0, [r7, #4] 801142e: f000 fa10 bl 8011852 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8011432: 687b ldr r3, [r7, #4] 8011434: 2200 movs r2, #0 8011436: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 8011438: 68bb ldr r3, [r7, #8] 801143a: f003 0310 and.w r3, r3, #16 801143e: 2b00 cmp r3, #0 8011440: d020 beq.n 8011484 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 8011442: 68fb ldr r3, [r7, #12] 8011444: f003 0310 and.w r3, r3, #16 8011448: 2b00 cmp r3, #0 801144a: d01b beq.n 8011484 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 801144c: 687b ldr r3, [r7, #4] 801144e: 681b ldr r3, [r3, #0] 8011450: f06f 0210 mvn.w r2, #16 8011454: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8011456: 687b ldr r3, [r7, #4] 8011458: 2208 movs r2, #8 801145a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 801145c: 687b ldr r3, [r7, #4] 801145e: 681b ldr r3, [r3, #0] 8011460: 69db ldr r3, [r3, #28] 8011462: f403 7340 and.w r3, r3, #768 @ 0x300 8011466: 2b00 cmp r3, #0 8011468: d003 beq.n 8011472 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 801146a: 6878 ldr r0, [r7, #4] 801146c: f000 f9e8 bl 8011840 8011470: e005 b.n 801147e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8011472: 6878 ldr r0, [r7, #4] 8011474: f7f8 ff92 bl 800a39c HAL_TIM_PWM_PulseFinishedCallback(htim); 8011478: 6878 ldr r0, [r7, #4] 801147a: f000 f9ea bl 8011852 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 801147e: 687b ldr r3, [r7, #4] 8011480: 2200 movs r2, #0 8011482: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 8011484: 68bb ldr r3, [r7, #8] 8011486: f003 0301 and.w r3, r3, #1 801148a: 2b00 cmp r3, #0 801148c: d00c beq.n 80114a8 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 801148e: 68fb ldr r3, [r7, #12] 8011490: f003 0301 and.w r3, r3, #1 8011494: 2b00 cmp r3, #0 8011496: d007 beq.n 80114a8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 8011498: 687b ldr r3, [r7, #4] 801149a: 681b ldr r3, [r3, #0] 801149c: f06f 0201 mvn.w r2, #1 80114a0: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 80114a2: 6878 ldr r0, [r7, #4] 80114a4: f000 f9c3 bl 801182e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) 80114a8: 68bb ldr r3, [r7, #8] 80114aa: f003 0380 and.w r3, r3, #128 @ 0x80 80114ae: 2b00 cmp r3, #0 80114b0: d00c beq.n 80114cc { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 80114b2: 68fb ldr r3, [r7, #12] 80114b4: f003 0380 and.w r3, r3, #128 @ 0x80 80114b8: 2b00 cmp r3, #0 80114ba: d007 beq.n 80114cc { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); 80114bc: 687b ldr r3, [r7, #4] 80114be: 681b ldr r3, [r3, #0] 80114c0: f06f 0280 mvn.w r2, #128 @ 0x80 80114c4: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 80114c6: 6878 ldr r0, [r7, #4] 80114c8: f000 fcff bl 8011eca #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 80114cc: 68bb ldr r3, [r7, #8] 80114ce: f003 0340 and.w r3, r3, #64 @ 0x40 80114d2: 2b00 cmp r3, #0 80114d4: d00c beq.n 80114f0 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 80114d6: 68fb ldr r3, [r7, #12] 80114d8: f003 0340 and.w r3, r3, #64 @ 0x40 80114dc: 2b00 cmp r3, #0 80114de: d007 beq.n 80114f0 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 80114e0: 687b ldr r3, [r7, #4] 80114e2: 681b ldr r3, [r3, #0] 80114e4: f06f 0240 mvn.w r2, #64 @ 0x40 80114e8: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 80114ea: 6878 ldr r0, [r7, #4] 80114ec: f000 f9ba bl 8011864 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 80114f0: 68bb ldr r3, [r7, #8] 80114f2: f003 0320 and.w r3, r3, #32 80114f6: 2b00 cmp r3, #0 80114f8: d00c beq.n 8011514 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 80114fa: 68fb ldr r3, [r7, #12] 80114fc: f003 0320 and.w r3, r3, #32 8011500: 2b00 cmp r3, #0 8011502: d007 beq.n 8011514 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 8011504: 687b ldr r3, [r7, #4] 8011506: 681b ldr r3, [r3, #0] 8011508: f06f 0220 mvn.w r2, #32 801150c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 801150e: 6878 ldr r0, [r7, #4] 8011510: f000 fcd2 bl 8011eb8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8011514: bf00 nop 8011516: 3710 adds r7, #16 8011518: 46bd mov sp, r7 801151a: bd80 pop {r7, pc} 0801151c : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 801151c: b580 push {r7, lr} 801151e: b086 sub sp, #24 8011520: af00 add r7, sp, #0 8011522: 60f8 str r0, [r7, #12] 8011524: 60b9 str r1, [r7, #8] 8011526: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8011528: 2300 movs r3, #0 801152a: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 801152c: 68fb ldr r3, [r7, #12] 801152e: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8011532: 2b01 cmp r3, #1 8011534: d101 bne.n 801153a 8011536: 2302 movs r3, #2 8011538: e0ae b.n 8011698 801153a: 68fb ldr r3, [r7, #12] 801153c: 2201 movs r2, #1 801153e: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 8011542: 687b ldr r3, [r7, #4] 8011544: 2b0c cmp r3, #12 8011546: f200 809f bhi.w 8011688 801154a: a201 add r2, pc, #4 @ (adr r2, 8011550 ) 801154c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011550: 08011585 .word 0x08011585 8011554: 08011689 .word 0x08011689 8011558: 08011689 .word 0x08011689 801155c: 08011689 .word 0x08011689 8011560: 080115c5 .word 0x080115c5 8011564: 08011689 .word 0x08011689 8011568: 08011689 .word 0x08011689 801156c: 08011689 .word 0x08011689 8011570: 08011607 .word 0x08011607 8011574: 08011689 .word 0x08011689 8011578: 08011689 .word 0x08011689 801157c: 08011689 .word 0x08011689 8011580: 08011647 .word 0x08011647 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8011584: 68fb ldr r3, [r7, #12] 8011586: 681b ldr r3, [r3, #0] 8011588: 68b9 ldr r1, [r7, #8] 801158a: 4618 mov r0, r3 801158c: f000 f9ec bl 8011968 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 8011590: 68fb ldr r3, [r7, #12] 8011592: 681b ldr r3, [r3, #0] 8011594: 699a ldr r2, [r3, #24] 8011596: 68fb ldr r3, [r7, #12] 8011598: 681b ldr r3, [r3, #0] 801159a: f042 0208 orr.w r2, r2, #8 801159e: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 80115a0: 68fb ldr r3, [r7, #12] 80115a2: 681b ldr r3, [r3, #0] 80115a4: 699a ldr r2, [r3, #24] 80115a6: 68fb ldr r3, [r7, #12] 80115a8: 681b ldr r3, [r3, #0] 80115aa: f022 0204 bic.w r2, r2, #4 80115ae: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 80115b0: 68fb ldr r3, [r7, #12] 80115b2: 681b ldr r3, [r3, #0] 80115b4: 6999 ldr r1, [r3, #24] 80115b6: 68bb ldr r3, [r7, #8] 80115b8: 691a ldr r2, [r3, #16] 80115ba: 68fb ldr r3, [r7, #12] 80115bc: 681b ldr r3, [r3, #0] 80115be: 430a orrs r2, r1 80115c0: 619a str r2, [r3, #24] break; 80115c2: e064 b.n 801168e { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 80115c4: 68fb ldr r3, [r7, #12] 80115c6: 681b ldr r3, [r3, #0] 80115c8: 68b9 ldr r1, [r7, #8] 80115ca: 4618 mov r0, r3 80115cc: f000 fa32 bl 8011a34 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 80115d0: 68fb ldr r3, [r7, #12] 80115d2: 681b ldr r3, [r3, #0] 80115d4: 699a ldr r2, [r3, #24] 80115d6: 68fb ldr r3, [r7, #12] 80115d8: 681b ldr r3, [r3, #0] 80115da: f442 6200 orr.w r2, r2, #2048 @ 0x800 80115de: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 80115e0: 68fb ldr r3, [r7, #12] 80115e2: 681b ldr r3, [r3, #0] 80115e4: 699a ldr r2, [r3, #24] 80115e6: 68fb ldr r3, [r7, #12] 80115e8: 681b ldr r3, [r3, #0] 80115ea: f422 6280 bic.w r2, r2, #1024 @ 0x400 80115ee: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 80115f0: 68fb ldr r3, [r7, #12] 80115f2: 681b ldr r3, [r3, #0] 80115f4: 6999 ldr r1, [r3, #24] 80115f6: 68bb ldr r3, [r7, #8] 80115f8: 691b ldr r3, [r3, #16] 80115fa: 021a lsls r2, r3, #8 80115fc: 68fb ldr r3, [r7, #12] 80115fe: 681b ldr r3, [r3, #0] 8011600: 430a orrs r2, r1 8011602: 619a str r2, [r3, #24] break; 8011604: e043 b.n 801168e { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8011606: 68fb ldr r3, [r7, #12] 8011608: 681b ldr r3, [r3, #0] 801160a: 68b9 ldr r1, [r7, #8] 801160c: 4618 mov r0, r3 801160e: f000 fa7b bl 8011b08 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 8011612: 68fb ldr r3, [r7, #12] 8011614: 681b ldr r3, [r3, #0] 8011616: 69da ldr r2, [r3, #28] 8011618: 68fb ldr r3, [r7, #12] 801161a: 681b ldr r3, [r3, #0] 801161c: f042 0208 orr.w r2, r2, #8 8011620: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 8011622: 68fb ldr r3, [r7, #12] 8011624: 681b ldr r3, [r3, #0] 8011626: 69da ldr r2, [r3, #28] 8011628: 68fb ldr r3, [r7, #12] 801162a: 681b ldr r3, [r3, #0] 801162c: f022 0204 bic.w r2, r2, #4 8011630: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 8011632: 68fb ldr r3, [r7, #12] 8011634: 681b ldr r3, [r3, #0] 8011636: 69d9 ldr r1, [r3, #28] 8011638: 68bb ldr r3, [r7, #8] 801163a: 691a ldr r2, [r3, #16] 801163c: 68fb ldr r3, [r7, #12] 801163e: 681b ldr r3, [r3, #0] 8011640: 430a orrs r2, r1 8011642: 61da str r2, [r3, #28] break; 8011644: e023 b.n 801168e { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8011646: 68fb ldr r3, [r7, #12] 8011648: 681b ldr r3, [r3, #0] 801164a: 68b9 ldr r1, [r7, #8] 801164c: 4618 mov r0, r3 801164e: f000 fac5 bl 8011bdc /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 8011652: 68fb ldr r3, [r7, #12] 8011654: 681b ldr r3, [r3, #0] 8011656: 69da ldr r2, [r3, #28] 8011658: 68fb ldr r3, [r7, #12] 801165a: 681b ldr r3, [r3, #0] 801165c: f442 6200 orr.w r2, r2, #2048 @ 0x800 8011660: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 8011662: 68fb ldr r3, [r7, #12] 8011664: 681b ldr r3, [r3, #0] 8011666: 69da ldr r2, [r3, #28] 8011668: 68fb ldr r3, [r7, #12] 801166a: 681b ldr r3, [r3, #0] 801166c: f422 6280 bic.w r2, r2, #1024 @ 0x400 8011670: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 8011672: 68fb ldr r3, [r7, #12] 8011674: 681b ldr r3, [r3, #0] 8011676: 69d9 ldr r1, [r3, #28] 8011678: 68bb ldr r3, [r7, #8] 801167a: 691b ldr r3, [r3, #16] 801167c: 021a lsls r2, r3, #8 801167e: 68fb ldr r3, [r7, #12] 8011680: 681b ldr r3, [r3, #0] 8011682: 430a orrs r2, r1 8011684: 61da str r2, [r3, #28] break; 8011686: e002 b.n 801168e } default: status = HAL_ERROR; 8011688: 2301 movs r3, #1 801168a: 75fb strb r3, [r7, #23] break; 801168c: bf00 nop } __HAL_UNLOCK(htim); 801168e: 68fb ldr r3, [r7, #12] 8011690: 2200 movs r2, #0 8011692: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8011696: 7dfb ldrb r3, [r7, #23] } 8011698: 4618 mov r0, r3 801169a: 3718 adds r7, #24 801169c: 46bd mov sp, r7 801169e: bd80 pop {r7, pc} 080116a0 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 80116a0: b580 push {r7, lr} 80116a2: b084 sub sp, #16 80116a4: af00 add r7, sp, #0 80116a6: 6078 str r0, [r7, #4] 80116a8: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 80116aa: 2300 movs r3, #0 80116ac: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 80116ae: 687b ldr r3, [r7, #4] 80116b0: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80116b4: 2b01 cmp r3, #1 80116b6: d101 bne.n 80116bc 80116b8: 2302 movs r3, #2 80116ba: e0b4 b.n 8011826 80116bc: 687b ldr r3, [r7, #4] 80116be: 2201 movs r2, #1 80116c0: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 80116c4: 687b ldr r3, [r7, #4] 80116c6: 2202 movs r2, #2 80116c8: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 80116cc: 687b ldr r3, [r7, #4] 80116ce: 681b ldr r3, [r3, #0] 80116d0: 689b ldr r3, [r3, #8] 80116d2: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 80116d4: 68bb ldr r3, [r7, #8] 80116d6: f023 0377 bic.w r3, r3, #119 @ 0x77 80116da: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80116dc: 68bb ldr r3, [r7, #8] 80116de: f423 437f bic.w r3, r3, #65280 @ 0xff00 80116e2: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 80116e4: 687b ldr r3, [r7, #4] 80116e6: 681b ldr r3, [r3, #0] 80116e8: 68ba ldr r2, [r7, #8] 80116ea: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 80116ec: 683b ldr r3, [r7, #0] 80116ee: 681b ldr r3, [r3, #0] 80116f0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80116f4: d03e beq.n 8011774 80116f6: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80116fa: f200 8087 bhi.w 801180c 80116fe: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8011702: f000 8086 beq.w 8011812 8011706: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 801170a: d87f bhi.n 801180c 801170c: 2b70 cmp r3, #112 @ 0x70 801170e: d01a beq.n 8011746 8011710: 2b70 cmp r3, #112 @ 0x70 8011712: d87b bhi.n 801180c 8011714: 2b60 cmp r3, #96 @ 0x60 8011716: d050 beq.n 80117ba 8011718: 2b60 cmp r3, #96 @ 0x60 801171a: d877 bhi.n 801180c 801171c: 2b50 cmp r3, #80 @ 0x50 801171e: d03c beq.n 801179a 8011720: 2b50 cmp r3, #80 @ 0x50 8011722: d873 bhi.n 801180c 8011724: 2b40 cmp r3, #64 @ 0x40 8011726: d058 beq.n 80117da 8011728: 2b40 cmp r3, #64 @ 0x40 801172a: d86f bhi.n 801180c 801172c: 2b30 cmp r3, #48 @ 0x30 801172e: d064 beq.n 80117fa 8011730: 2b30 cmp r3, #48 @ 0x30 8011732: d86b bhi.n 801180c 8011734: 2b20 cmp r3, #32 8011736: d060 beq.n 80117fa 8011738: 2b20 cmp r3, #32 801173a: d867 bhi.n 801180c 801173c: 2b00 cmp r3, #0 801173e: d05c beq.n 80117fa 8011740: 2b10 cmp r3, #16 8011742: d05a beq.n 80117fa 8011744: e062 b.n 801180c assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8011746: 687b ldr r3, [r7, #4] 8011748: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 801174a: 683b ldr r3, [r7, #0] 801174c: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 801174e: 683b ldr r3, [r7, #0] 8011750: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8011752: 683b ldr r3, [r7, #0] 8011754: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8011756: f000 fb06 bl 8011d66 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 801175a: 687b ldr r3, [r7, #4] 801175c: 681b ldr r3, [r3, #0] 801175e: 689b ldr r3, [r3, #8] 8011760: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 8011762: 68bb ldr r3, [r7, #8] 8011764: f043 0377 orr.w r3, r3, #119 @ 0x77 8011768: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 801176a: 687b ldr r3, [r7, #4] 801176c: 681b ldr r3, [r3, #0] 801176e: 68ba ldr r2, [r7, #8] 8011770: 609a str r2, [r3, #8] break; 8011772: e04f b.n 8011814 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8011774: 687b ldr r3, [r7, #4] 8011776: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8011778: 683b ldr r3, [r7, #0] 801177a: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 801177c: 683b ldr r3, [r7, #0] 801177e: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8011780: 683b ldr r3, [r7, #0] 8011782: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8011784: f000 faef bl 8011d66 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 8011788: 687b ldr r3, [r7, #4] 801178a: 681b ldr r3, [r3, #0] 801178c: 689a ldr r2, [r3, #8] 801178e: 687b ldr r3, [r7, #4] 8011790: 681b ldr r3, [r3, #0] 8011792: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8011796: 609a str r2, [r3, #8] break; 8011798: e03c b.n 8011814 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 801179a: 687b ldr r3, [r7, #4] 801179c: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 801179e: 683b ldr r3, [r7, #0] 80117a0: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80117a2: 683b ldr r3, [r7, #0] 80117a4: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 80117a6: 461a mov r2, r3 80117a8: f000 fa66 bl 8011c78 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 80117ac: 687b ldr r3, [r7, #4] 80117ae: 681b ldr r3, [r3, #0] 80117b0: 2150 movs r1, #80 @ 0x50 80117b2: 4618 mov r0, r3 80117b4: f000 fabd bl 8011d32 break; 80117b8: e02c b.n 8011814 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 80117ba: 687b ldr r3, [r7, #4] 80117bc: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80117be: 683b ldr r3, [r7, #0] 80117c0: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80117c2: 683b ldr r3, [r7, #0] 80117c4: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 80117c6: 461a mov r2, r3 80117c8: f000 fa84 bl 8011cd4 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 80117cc: 687b ldr r3, [r7, #4] 80117ce: 681b ldr r3, [r3, #0] 80117d0: 2160 movs r1, #96 @ 0x60 80117d2: 4618 mov r0, r3 80117d4: f000 faad bl 8011d32 break; 80117d8: e01c b.n 8011814 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 80117da: 687b ldr r3, [r7, #4] 80117dc: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80117de: 683b ldr r3, [r7, #0] 80117e0: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80117e2: 683b ldr r3, [r7, #0] 80117e4: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 80117e6: 461a mov r2, r3 80117e8: f000 fa46 bl 8011c78 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 80117ec: 687b ldr r3, [r7, #4] 80117ee: 681b ldr r3, [r3, #0] 80117f0: 2140 movs r1, #64 @ 0x40 80117f2: 4618 mov r0, r3 80117f4: f000 fa9d bl 8011d32 break; 80117f8: e00c b.n 8011814 case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 80117fa: 687b ldr r3, [r7, #4] 80117fc: 681a ldr r2, [r3, #0] 80117fe: 683b ldr r3, [r7, #0] 8011800: 681b ldr r3, [r3, #0] 8011802: 4619 mov r1, r3 8011804: 4610 mov r0, r2 8011806: f000 fa94 bl 8011d32 break; 801180a: e003 b.n 8011814 } default: status = HAL_ERROR; 801180c: 2301 movs r3, #1 801180e: 73fb strb r3, [r7, #15] break; 8011810: e000 b.n 8011814 break; 8011812: bf00 nop } htim->State = HAL_TIM_STATE_READY; 8011814: 687b ldr r3, [r7, #4] 8011816: 2201 movs r2, #1 8011818: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 801181c: 687b ldr r3, [r7, #4] 801181e: 2200 movs r2, #0 8011820: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8011824: 7bfb ldrb r3, [r7, #15] } 8011826: 4618 mov r0, r3 8011828: 3710 adds r7, #16 801182a: 46bd mov sp, r7 801182c: bd80 pop {r7, pc} 0801182e : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 801182e: b480 push {r7} 8011830: b083 sub sp, #12 8011832: af00 add r7, sp, #0 8011834: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } 8011836: bf00 nop 8011838: 370c adds r7, #12 801183a: 46bd mov sp, r7 801183c: bc80 pop {r7} 801183e: 4770 bx lr 08011840 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 8011840: b480 push {r7} 8011842: b083 sub sp, #12 8011844: af00 add r7, sp, #0 8011846: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 8011848: bf00 nop 801184a: 370c adds r7, #12 801184c: 46bd mov sp, r7 801184e: bc80 pop {r7} 8011850: 4770 bx lr 08011852 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8011852: b480 push {r7} 8011854: b083 sub sp, #12 8011856: af00 add r7, sp, #0 8011858: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 801185a: bf00 nop 801185c: 370c adds r7, #12 801185e: 46bd mov sp, r7 8011860: bc80 pop {r7} 8011862: 4770 bx lr 08011864 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8011864: b480 push {r7} 8011866: b083 sub sp, #12 8011868: af00 add r7, sp, #0 801186a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 801186c: bf00 nop 801186e: 370c adds r7, #12 8011870: 46bd mov sp, r7 8011872: bc80 pop {r7} 8011874: 4770 bx lr ... 08011878 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8011878: b480 push {r7} 801187a: b085 sub sp, #20 801187c: af00 add r7, sp, #0 801187e: 6078 str r0, [r7, #4] 8011880: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8011882: 687b ldr r3, [r7, #4] 8011884: 681b ldr r3, [r3, #0] 8011886: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8011888: 687b ldr r3, [r7, #4] 801188a: 4a33 ldr r2, [pc, #204] @ (8011958 ) 801188c: 4293 cmp r3, r2 801188e: d00f beq.n 80118b0 8011890: 687b ldr r3, [r7, #4] 8011892: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8011896: d00b beq.n 80118b0 8011898: 687b ldr r3, [r7, #4] 801189a: 4a30 ldr r2, [pc, #192] @ (801195c ) 801189c: 4293 cmp r3, r2 801189e: d007 beq.n 80118b0 80118a0: 687b ldr r3, [r7, #4] 80118a2: 4a2f ldr r2, [pc, #188] @ (8011960 ) 80118a4: 4293 cmp r3, r2 80118a6: d003 beq.n 80118b0 80118a8: 687b ldr r3, [r7, #4] 80118aa: 4a2e ldr r2, [pc, #184] @ (8011964 ) 80118ac: 4293 cmp r3, r2 80118ae: d108 bne.n 80118c2 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80118b0: 68fb ldr r3, [r7, #12] 80118b2: f023 0370 bic.w r3, r3, #112 @ 0x70 80118b6: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80118b8: 683b ldr r3, [r7, #0] 80118ba: 685b ldr r3, [r3, #4] 80118bc: 68fa ldr r2, [r7, #12] 80118be: 4313 orrs r3, r2 80118c0: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80118c2: 687b ldr r3, [r7, #4] 80118c4: 4a24 ldr r2, [pc, #144] @ (8011958 ) 80118c6: 4293 cmp r3, r2 80118c8: d00f beq.n 80118ea 80118ca: 687b ldr r3, [r7, #4] 80118cc: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80118d0: d00b beq.n 80118ea 80118d2: 687b ldr r3, [r7, #4] 80118d4: 4a21 ldr r2, [pc, #132] @ (801195c ) 80118d6: 4293 cmp r3, r2 80118d8: d007 beq.n 80118ea 80118da: 687b ldr r3, [r7, #4] 80118dc: 4a20 ldr r2, [pc, #128] @ (8011960 ) 80118de: 4293 cmp r3, r2 80118e0: d003 beq.n 80118ea 80118e2: 687b ldr r3, [r7, #4] 80118e4: 4a1f ldr r2, [pc, #124] @ (8011964 ) 80118e6: 4293 cmp r3, r2 80118e8: d108 bne.n 80118fc { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 80118ea: 68fb ldr r3, [r7, #12] 80118ec: f423 7340 bic.w r3, r3, #768 @ 0x300 80118f0: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80118f2: 683b ldr r3, [r7, #0] 80118f4: 68db ldr r3, [r3, #12] 80118f6: 68fa ldr r2, [r7, #12] 80118f8: 4313 orrs r3, r2 80118fa: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80118fc: 68fb ldr r3, [r7, #12] 80118fe: f023 0280 bic.w r2, r3, #128 @ 0x80 8011902: 683b ldr r3, [r7, #0] 8011904: 695b ldr r3, [r3, #20] 8011906: 4313 orrs r3, r2 8011908: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 801190a: 687b ldr r3, [r7, #4] 801190c: 68fa ldr r2, [r7, #12] 801190e: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8011910: 683b ldr r3, [r7, #0] 8011912: 689a ldr r2, [r3, #8] 8011914: 687b ldr r3, [r7, #4] 8011916: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8011918: 683b ldr r3, [r7, #0] 801191a: 681a ldr r2, [r3, #0] 801191c: 687b ldr r3, [r7, #4] 801191e: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8011920: 687b ldr r3, [r7, #4] 8011922: 4a0d ldr r2, [pc, #52] @ (8011958 ) 8011924: 4293 cmp r3, r2 8011926: d103 bne.n 8011930 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8011928: 683b ldr r3, [r7, #0] 801192a: 691a ldr r2, [r3, #16] 801192c: 687b ldr r3, [r7, #4] 801192e: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8011930: 687b ldr r3, [r7, #4] 8011932: 2201 movs r2, #1 8011934: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 8011936: 687b ldr r3, [r7, #4] 8011938: 691b ldr r3, [r3, #16] 801193a: f003 0301 and.w r3, r3, #1 801193e: 2b00 cmp r3, #0 8011940: d005 beq.n 801194e { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 8011942: 687b ldr r3, [r7, #4] 8011944: 691b ldr r3, [r3, #16] 8011946: f023 0201 bic.w r2, r3, #1 801194a: 687b ldr r3, [r7, #4] 801194c: 611a str r2, [r3, #16] } } 801194e: bf00 nop 8011950: 3714 adds r7, #20 8011952: 46bd mov sp, r7 8011954: bc80 pop {r7} 8011956: 4770 bx lr 8011958: 40012c00 .word 0x40012c00 801195c: 40000400 .word 0x40000400 8011960: 40000800 .word 0x40000800 8011964: 40000c00 .word 0x40000c00 08011968 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8011968: b480 push {r7} 801196a: b087 sub sp, #28 801196c: af00 add r7, sp, #0 801196e: 6078 str r0, [r7, #4] 8011970: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8011972: 687b ldr r3, [r7, #4] 8011974: 6a1b ldr r3, [r3, #32] 8011976: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 8011978: 687b ldr r3, [r7, #4] 801197a: 6a1b ldr r3, [r3, #32] 801197c: f023 0201 bic.w r2, r3, #1 8011980: 687b ldr r3, [r7, #4] 8011982: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8011984: 687b ldr r3, [r7, #4] 8011986: 685b ldr r3, [r3, #4] 8011988: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 801198a: 687b ldr r3, [r7, #4] 801198c: 699b ldr r3, [r3, #24] 801198e: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 8011990: 68fb ldr r3, [r7, #12] 8011992: f023 0370 bic.w r3, r3, #112 @ 0x70 8011996: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 8011998: 68fb ldr r3, [r7, #12] 801199a: f023 0303 bic.w r3, r3, #3 801199e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80119a0: 683b ldr r3, [r7, #0] 80119a2: 681b ldr r3, [r3, #0] 80119a4: 68fa ldr r2, [r7, #12] 80119a6: 4313 orrs r3, r2 80119a8: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 80119aa: 697b ldr r3, [r7, #20] 80119ac: f023 0302 bic.w r3, r3, #2 80119b0: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 80119b2: 683b ldr r3, [r7, #0] 80119b4: 689b ldr r3, [r3, #8] 80119b6: 697a ldr r2, [r7, #20] 80119b8: 4313 orrs r3, r2 80119ba: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 80119bc: 687b ldr r3, [r7, #4] 80119be: 4a1c ldr r2, [pc, #112] @ (8011a30 ) 80119c0: 4293 cmp r3, r2 80119c2: d10c bne.n 80119de { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 80119c4: 697b ldr r3, [r7, #20] 80119c6: f023 0308 bic.w r3, r3, #8 80119ca: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 80119cc: 683b ldr r3, [r7, #0] 80119ce: 68db ldr r3, [r3, #12] 80119d0: 697a ldr r2, [r7, #20] 80119d2: 4313 orrs r3, r2 80119d4: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 80119d6: 697b ldr r3, [r7, #20] 80119d8: f023 0304 bic.w r3, r3, #4 80119dc: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80119de: 687b ldr r3, [r7, #4] 80119e0: 4a13 ldr r2, [pc, #76] @ (8011a30 ) 80119e2: 4293 cmp r3, r2 80119e4: d111 bne.n 8011a0a /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 80119e6: 693b ldr r3, [r7, #16] 80119e8: f423 7380 bic.w r3, r3, #256 @ 0x100 80119ec: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 80119ee: 693b ldr r3, [r7, #16] 80119f0: f423 7300 bic.w r3, r3, #512 @ 0x200 80119f4: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 80119f6: 683b ldr r3, [r7, #0] 80119f8: 695b ldr r3, [r3, #20] 80119fa: 693a ldr r2, [r7, #16] 80119fc: 4313 orrs r3, r2 80119fe: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8011a00: 683b ldr r3, [r7, #0] 8011a02: 699b ldr r3, [r3, #24] 8011a04: 693a ldr r2, [r7, #16] 8011a06: 4313 orrs r3, r2 8011a08: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8011a0a: 687b ldr r3, [r7, #4] 8011a0c: 693a ldr r2, [r7, #16] 8011a0e: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8011a10: 687b ldr r3, [r7, #4] 8011a12: 68fa ldr r2, [r7, #12] 8011a14: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 8011a16: 683b ldr r3, [r7, #0] 8011a18: 685a ldr r2, [r3, #4] 8011a1a: 687b ldr r3, [r7, #4] 8011a1c: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8011a1e: 687b ldr r3, [r7, #4] 8011a20: 697a ldr r2, [r7, #20] 8011a22: 621a str r2, [r3, #32] } 8011a24: bf00 nop 8011a26: 371c adds r7, #28 8011a28: 46bd mov sp, r7 8011a2a: bc80 pop {r7} 8011a2c: 4770 bx lr 8011a2e: bf00 nop 8011a30: 40012c00 .word 0x40012c00 08011a34 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8011a34: b480 push {r7} 8011a36: b087 sub sp, #28 8011a38: af00 add r7, sp, #0 8011a3a: 6078 str r0, [r7, #4] 8011a3c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8011a3e: 687b ldr r3, [r7, #4] 8011a40: 6a1b ldr r3, [r3, #32] 8011a42: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8011a44: 687b ldr r3, [r7, #4] 8011a46: 6a1b ldr r3, [r3, #32] 8011a48: f023 0210 bic.w r2, r3, #16 8011a4c: 687b ldr r3, [r7, #4] 8011a4e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8011a50: 687b ldr r3, [r7, #4] 8011a52: 685b ldr r3, [r3, #4] 8011a54: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8011a56: 687b ldr r3, [r7, #4] 8011a58: 699b ldr r3, [r3, #24] 8011a5a: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 8011a5c: 68fb ldr r3, [r7, #12] 8011a5e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8011a62: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8011a64: 68fb ldr r3, [r7, #12] 8011a66: f423 7340 bic.w r3, r3, #768 @ 0x300 8011a6a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8011a6c: 683b ldr r3, [r7, #0] 8011a6e: 681b ldr r3, [r3, #0] 8011a70: 021b lsls r3, r3, #8 8011a72: 68fa ldr r2, [r7, #12] 8011a74: 4313 orrs r3, r2 8011a76: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 8011a78: 697b ldr r3, [r7, #20] 8011a7a: f023 0320 bic.w r3, r3, #32 8011a7e: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 8011a80: 683b ldr r3, [r7, #0] 8011a82: 689b ldr r3, [r3, #8] 8011a84: 011b lsls r3, r3, #4 8011a86: 697a ldr r2, [r7, #20] 8011a88: 4313 orrs r3, r2 8011a8a: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 8011a8c: 687b ldr r3, [r7, #4] 8011a8e: 4a1d ldr r2, [pc, #116] @ (8011b04 ) 8011a90: 4293 cmp r3, r2 8011a92: d10d bne.n 8011ab0 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 8011a94: 697b ldr r3, [r7, #20] 8011a96: f023 0380 bic.w r3, r3, #128 @ 0x80 8011a9a: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8011a9c: 683b ldr r3, [r7, #0] 8011a9e: 68db ldr r3, [r3, #12] 8011aa0: 011b lsls r3, r3, #4 8011aa2: 697a ldr r2, [r7, #20] 8011aa4: 4313 orrs r3, r2 8011aa6: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8011aa8: 697b ldr r3, [r7, #20] 8011aaa: f023 0340 bic.w r3, r3, #64 @ 0x40 8011aae: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8011ab0: 687b ldr r3, [r7, #4] 8011ab2: 4a14 ldr r2, [pc, #80] @ (8011b04 ) 8011ab4: 4293 cmp r3, r2 8011ab6: d113 bne.n 8011ae0 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8011ab8: 693b ldr r3, [r7, #16] 8011aba: f423 6380 bic.w r3, r3, #1024 @ 0x400 8011abe: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8011ac0: 693b ldr r3, [r7, #16] 8011ac2: f423 6300 bic.w r3, r3, #2048 @ 0x800 8011ac6: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8011ac8: 683b ldr r3, [r7, #0] 8011aca: 695b ldr r3, [r3, #20] 8011acc: 009b lsls r3, r3, #2 8011ace: 693a ldr r2, [r7, #16] 8011ad0: 4313 orrs r3, r2 8011ad2: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8011ad4: 683b ldr r3, [r7, #0] 8011ad6: 699b ldr r3, [r3, #24] 8011ad8: 009b lsls r3, r3, #2 8011ada: 693a ldr r2, [r7, #16] 8011adc: 4313 orrs r3, r2 8011ade: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8011ae0: 687b ldr r3, [r7, #4] 8011ae2: 693a ldr r2, [r7, #16] 8011ae4: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8011ae6: 687b ldr r3, [r7, #4] 8011ae8: 68fa ldr r2, [r7, #12] 8011aea: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8011aec: 683b ldr r3, [r7, #0] 8011aee: 685a ldr r2, [r3, #4] 8011af0: 687b ldr r3, [r7, #4] 8011af2: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8011af4: 687b ldr r3, [r7, #4] 8011af6: 697a ldr r2, [r7, #20] 8011af8: 621a str r2, [r3, #32] } 8011afa: bf00 nop 8011afc: 371c adds r7, #28 8011afe: 46bd mov sp, r7 8011b00: bc80 pop {r7} 8011b02: 4770 bx lr 8011b04: 40012c00 .word 0x40012c00 08011b08 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8011b08: b480 push {r7} 8011b0a: b087 sub sp, #28 8011b0c: af00 add r7, sp, #0 8011b0e: 6078 str r0, [r7, #4] 8011b10: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8011b12: 687b ldr r3, [r7, #4] 8011b14: 6a1b ldr r3, [r3, #32] 8011b16: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8011b18: 687b ldr r3, [r7, #4] 8011b1a: 6a1b ldr r3, [r3, #32] 8011b1c: f423 7280 bic.w r2, r3, #256 @ 0x100 8011b20: 687b ldr r3, [r7, #4] 8011b22: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8011b24: 687b ldr r3, [r7, #4] 8011b26: 685b ldr r3, [r3, #4] 8011b28: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8011b2a: 687b ldr r3, [r7, #4] 8011b2c: 69db ldr r3, [r3, #28] 8011b2e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8011b30: 68fb ldr r3, [r7, #12] 8011b32: f023 0370 bic.w r3, r3, #112 @ 0x70 8011b36: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8011b38: 68fb ldr r3, [r7, #12] 8011b3a: f023 0303 bic.w r3, r3, #3 8011b3e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8011b40: 683b ldr r3, [r7, #0] 8011b42: 681b ldr r3, [r3, #0] 8011b44: 68fa ldr r2, [r7, #12] 8011b46: 4313 orrs r3, r2 8011b48: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8011b4a: 697b ldr r3, [r7, #20] 8011b4c: f423 7300 bic.w r3, r3, #512 @ 0x200 8011b50: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 8011b52: 683b ldr r3, [r7, #0] 8011b54: 689b ldr r3, [r3, #8] 8011b56: 021b lsls r3, r3, #8 8011b58: 697a ldr r2, [r7, #20] 8011b5a: 4313 orrs r3, r2 8011b5c: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8011b5e: 687b ldr r3, [r7, #4] 8011b60: 4a1d ldr r2, [pc, #116] @ (8011bd8 ) 8011b62: 4293 cmp r3, r2 8011b64: d10d bne.n 8011b82 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8011b66: 697b ldr r3, [r7, #20] 8011b68: f423 6300 bic.w r3, r3, #2048 @ 0x800 8011b6c: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 8011b6e: 683b ldr r3, [r7, #0] 8011b70: 68db ldr r3, [r3, #12] 8011b72: 021b lsls r3, r3, #8 8011b74: 697a ldr r2, [r7, #20] 8011b76: 4313 orrs r3, r2 8011b78: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8011b7a: 697b ldr r3, [r7, #20] 8011b7c: f423 6380 bic.w r3, r3, #1024 @ 0x400 8011b80: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8011b82: 687b ldr r3, [r7, #4] 8011b84: 4a14 ldr r2, [pc, #80] @ (8011bd8 ) 8011b86: 4293 cmp r3, r2 8011b88: d113 bne.n 8011bb2 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8011b8a: 693b ldr r3, [r7, #16] 8011b8c: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8011b90: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8011b92: 693b ldr r3, [r7, #16] 8011b94: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8011b98: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8011b9a: 683b ldr r3, [r7, #0] 8011b9c: 695b ldr r3, [r3, #20] 8011b9e: 011b lsls r3, r3, #4 8011ba0: 693a ldr r2, [r7, #16] 8011ba2: 4313 orrs r3, r2 8011ba4: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 8011ba6: 683b ldr r3, [r7, #0] 8011ba8: 699b ldr r3, [r3, #24] 8011baa: 011b lsls r3, r3, #4 8011bac: 693a ldr r2, [r7, #16] 8011bae: 4313 orrs r3, r2 8011bb0: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8011bb2: 687b ldr r3, [r7, #4] 8011bb4: 693a ldr r2, [r7, #16] 8011bb6: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8011bb8: 687b ldr r3, [r7, #4] 8011bba: 68fa ldr r2, [r7, #12] 8011bbc: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8011bbe: 683b ldr r3, [r7, #0] 8011bc0: 685a ldr r2, [r3, #4] 8011bc2: 687b ldr r3, [r7, #4] 8011bc4: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8011bc6: 687b ldr r3, [r7, #4] 8011bc8: 697a ldr r2, [r7, #20] 8011bca: 621a str r2, [r3, #32] } 8011bcc: bf00 nop 8011bce: 371c adds r7, #28 8011bd0: 46bd mov sp, r7 8011bd2: bc80 pop {r7} 8011bd4: 4770 bx lr 8011bd6: bf00 nop 8011bd8: 40012c00 .word 0x40012c00 08011bdc : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8011bdc: b480 push {r7} 8011bde: b087 sub sp, #28 8011be0: af00 add r7, sp, #0 8011be2: 6078 str r0, [r7, #4] 8011be4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8011be6: 687b ldr r3, [r7, #4] 8011be8: 6a1b ldr r3, [r3, #32] 8011bea: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8011bec: 687b ldr r3, [r7, #4] 8011bee: 6a1b ldr r3, [r3, #32] 8011bf0: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8011bf4: 687b ldr r3, [r7, #4] 8011bf6: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8011bf8: 687b ldr r3, [r7, #4] 8011bfa: 685b ldr r3, [r3, #4] 8011bfc: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8011bfe: 687b ldr r3, [r7, #4] 8011c00: 69db ldr r3, [r3, #28] 8011c02: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8011c04: 68fb ldr r3, [r7, #12] 8011c06: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8011c0a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8011c0c: 68fb ldr r3, [r7, #12] 8011c0e: f423 7340 bic.w r3, r3, #768 @ 0x300 8011c12: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8011c14: 683b ldr r3, [r7, #0] 8011c16: 681b ldr r3, [r3, #0] 8011c18: 021b lsls r3, r3, #8 8011c1a: 68fa ldr r2, [r7, #12] 8011c1c: 4313 orrs r3, r2 8011c1e: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8011c20: 693b ldr r3, [r7, #16] 8011c22: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8011c26: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8011c28: 683b ldr r3, [r7, #0] 8011c2a: 689b ldr r3, [r3, #8] 8011c2c: 031b lsls r3, r3, #12 8011c2e: 693a ldr r2, [r7, #16] 8011c30: 4313 orrs r3, r2 8011c32: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8011c34: 687b ldr r3, [r7, #4] 8011c36: 4a0f ldr r2, [pc, #60] @ (8011c74 ) 8011c38: 4293 cmp r3, r2 8011c3a: d109 bne.n 8011c50 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8011c3c: 697b ldr r3, [r7, #20] 8011c3e: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8011c42: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8011c44: 683b ldr r3, [r7, #0] 8011c46: 695b ldr r3, [r3, #20] 8011c48: 019b lsls r3, r3, #6 8011c4a: 697a ldr r2, [r7, #20] 8011c4c: 4313 orrs r3, r2 8011c4e: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8011c50: 687b ldr r3, [r7, #4] 8011c52: 697a ldr r2, [r7, #20] 8011c54: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8011c56: 687b ldr r3, [r7, #4] 8011c58: 68fa ldr r2, [r7, #12] 8011c5a: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8011c5c: 683b ldr r3, [r7, #0] 8011c5e: 685a ldr r2, [r3, #4] 8011c60: 687b ldr r3, [r7, #4] 8011c62: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8011c64: 687b ldr r3, [r7, #4] 8011c66: 693a ldr r2, [r7, #16] 8011c68: 621a str r2, [r3, #32] } 8011c6a: bf00 nop 8011c6c: 371c adds r7, #28 8011c6e: 46bd mov sp, r7 8011c70: bc80 pop {r7} 8011c72: 4770 bx lr 8011c74: 40012c00 .word 0x40012c00 08011c78 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8011c78: b480 push {r7} 8011c7a: b087 sub sp, #28 8011c7c: af00 add r7, sp, #0 8011c7e: 60f8 str r0, [r7, #12] 8011c80: 60b9 str r1, [r7, #8] 8011c82: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8011c84: 68fb ldr r3, [r7, #12] 8011c86: 6a1b ldr r3, [r3, #32] 8011c88: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8011c8a: 68fb ldr r3, [r7, #12] 8011c8c: 6a1b ldr r3, [r3, #32] 8011c8e: f023 0201 bic.w r2, r3, #1 8011c92: 68fb ldr r3, [r7, #12] 8011c94: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8011c96: 68fb ldr r3, [r7, #12] 8011c98: 699b ldr r3, [r3, #24] 8011c9a: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8011c9c: 693b ldr r3, [r7, #16] 8011c9e: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8011ca2: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8011ca4: 687b ldr r3, [r7, #4] 8011ca6: 011b lsls r3, r3, #4 8011ca8: 693a ldr r2, [r7, #16] 8011caa: 4313 orrs r3, r2 8011cac: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8011cae: 697b ldr r3, [r7, #20] 8011cb0: f023 030a bic.w r3, r3, #10 8011cb4: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8011cb6: 697a ldr r2, [r7, #20] 8011cb8: 68bb ldr r3, [r7, #8] 8011cba: 4313 orrs r3, r2 8011cbc: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8011cbe: 68fb ldr r3, [r7, #12] 8011cc0: 693a ldr r2, [r7, #16] 8011cc2: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8011cc4: 68fb ldr r3, [r7, #12] 8011cc6: 697a ldr r2, [r7, #20] 8011cc8: 621a str r2, [r3, #32] } 8011cca: bf00 nop 8011ccc: 371c adds r7, #28 8011cce: 46bd mov sp, r7 8011cd0: bc80 pop {r7} 8011cd2: 4770 bx lr 08011cd4 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8011cd4: b480 push {r7} 8011cd6: b087 sub sp, #28 8011cd8: af00 add r7, sp, #0 8011cda: 60f8 str r0, [r7, #12] 8011cdc: 60b9 str r1, [r7, #8] 8011cde: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8011ce0: 68fb ldr r3, [r7, #12] 8011ce2: 6a1b ldr r3, [r3, #32] 8011ce4: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8011ce6: 68fb ldr r3, [r7, #12] 8011ce8: 6a1b ldr r3, [r3, #32] 8011cea: f023 0210 bic.w r2, r3, #16 8011cee: 68fb ldr r3, [r7, #12] 8011cf0: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8011cf2: 68fb ldr r3, [r7, #12] 8011cf4: 699b ldr r3, [r3, #24] 8011cf6: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8011cf8: 693b ldr r3, [r7, #16] 8011cfa: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8011cfe: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8011d00: 687b ldr r3, [r7, #4] 8011d02: 031b lsls r3, r3, #12 8011d04: 693a ldr r2, [r7, #16] 8011d06: 4313 orrs r3, r2 8011d08: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8011d0a: 697b ldr r3, [r7, #20] 8011d0c: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8011d10: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8011d12: 68bb ldr r3, [r7, #8] 8011d14: 011b lsls r3, r3, #4 8011d16: 697a ldr r2, [r7, #20] 8011d18: 4313 orrs r3, r2 8011d1a: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8011d1c: 68fb ldr r3, [r7, #12] 8011d1e: 693a ldr r2, [r7, #16] 8011d20: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8011d22: 68fb ldr r3, [r7, #12] 8011d24: 697a ldr r2, [r7, #20] 8011d26: 621a str r2, [r3, #32] } 8011d28: bf00 nop 8011d2a: 371c adds r7, #28 8011d2c: 46bd mov sp, r7 8011d2e: bc80 pop {r7} 8011d30: 4770 bx lr 08011d32 : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8011d32: b480 push {r7} 8011d34: b085 sub sp, #20 8011d36: af00 add r7, sp, #0 8011d38: 6078 str r0, [r7, #4] 8011d3a: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8011d3c: 687b ldr r3, [r7, #4] 8011d3e: 689b ldr r3, [r3, #8] 8011d40: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8011d42: 68fb ldr r3, [r7, #12] 8011d44: f023 0370 bic.w r3, r3, #112 @ 0x70 8011d48: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8011d4a: 683a ldr r2, [r7, #0] 8011d4c: 68fb ldr r3, [r7, #12] 8011d4e: 4313 orrs r3, r2 8011d50: f043 0307 orr.w r3, r3, #7 8011d54: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8011d56: 687b ldr r3, [r7, #4] 8011d58: 68fa ldr r2, [r7, #12] 8011d5a: 609a str r2, [r3, #8] } 8011d5c: bf00 nop 8011d5e: 3714 adds r7, #20 8011d60: 46bd mov sp, r7 8011d62: bc80 pop {r7} 8011d64: 4770 bx lr 08011d66 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8011d66: b480 push {r7} 8011d68: b087 sub sp, #28 8011d6a: af00 add r7, sp, #0 8011d6c: 60f8 str r0, [r7, #12] 8011d6e: 60b9 str r1, [r7, #8] 8011d70: 607a str r2, [r7, #4] 8011d72: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8011d74: 68fb ldr r3, [r7, #12] 8011d76: 689b ldr r3, [r3, #8] 8011d78: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8011d7a: 697b ldr r3, [r7, #20] 8011d7c: f423 437f bic.w r3, r3, #65280 @ 0xff00 8011d80: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8011d82: 683b ldr r3, [r7, #0] 8011d84: 021a lsls r2, r3, #8 8011d86: 687b ldr r3, [r7, #4] 8011d88: 431a orrs r2, r3 8011d8a: 68bb ldr r3, [r7, #8] 8011d8c: 4313 orrs r3, r2 8011d8e: 697a ldr r2, [r7, #20] 8011d90: 4313 orrs r3, r2 8011d92: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8011d94: 68fb ldr r3, [r7, #12] 8011d96: 697a ldr r2, [r7, #20] 8011d98: 609a str r2, [r3, #8] } 8011d9a: bf00 nop 8011d9c: 371c adds r7, #28 8011d9e: 46bd mov sp, r7 8011da0: bc80 pop {r7} 8011da2: 4770 bx lr 08011da4 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8011da4: b480 push {r7} 8011da6: b087 sub sp, #28 8011da8: af00 add r7, sp, #0 8011daa: 60f8 str r0, [r7, #12] 8011dac: 60b9 str r1, [r7, #8] 8011dae: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8011db0: 68bb ldr r3, [r7, #8] 8011db2: f003 031f and.w r3, r3, #31 8011db6: 2201 movs r2, #1 8011db8: fa02 f303 lsl.w r3, r2, r3 8011dbc: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 8011dbe: 68fb ldr r3, [r7, #12] 8011dc0: 6a1a ldr r2, [r3, #32] 8011dc2: 697b ldr r3, [r7, #20] 8011dc4: 43db mvns r3, r3 8011dc6: 401a ands r2, r3 8011dc8: 68fb ldr r3, [r7, #12] 8011dca: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8011dcc: 68fb ldr r3, [r7, #12] 8011dce: 6a1a ldr r2, [r3, #32] 8011dd0: 68bb ldr r3, [r7, #8] 8011dd2: f003 031f and.w r3, r3, #31 8011dd6: 6879 ldr r1, [r7, #4] 8011dd8: fa01 f303 lsl.w r3, r1, r3 8011ddc: 431a orrs r2, r3 8011dde: 68fb ldr r3, [r7, #12] 8011de0: 621a str r2, [r3, #32] } 8011de2: bf00 nop 8011de4: 371c adds r7, #28 8011de6: 46bd mov sp, r7 8011de8: bc80 pop {r7} 8011dea: 4770 bx lr 08011dec : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8011dec: b480 push {r7} 8011dee: b085 sub sp, #20 8011df0: af00 add r7, sp, #0 8011df2: 6078 str r0, [r7, #4] 8011df4: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8011df6: 687b ldr r3, [r7, #4] 8011df8: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8011dfc: 2b01 cmp r3, #1 8011dfe: d101 bne.n 8011e04 8011e00: 2302 movs r3, #2 8011e02: e04b b.n 8011e9c 8011e04: 687b ldr r3, [r7, #4] 8011e06: 2201 movs r2, #1 8011e08: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8011e0c: 687b ldr r3, [r7, #4] 8011e0e: 2202 movs r2, #2 8011e10: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8011e14: 687b ldr r3, [r7, #4] 8011e16: 681b ldr r3, [r3, #0] 8011e18: 685b ldr r3, [r3, #4] 8011e1a: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8011e1c: 687b ldr r3, [r7, #4] 8011e1e: 681b ldr r3, [r3, #0] 8011e20: 689b ldr r3, [r3, #8] 8011e22: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8011e24: 68fb ldr r3, [r7, #12] 8011e26: f023 0370 bic.w r3, r3, #112 @ 0x70 8011e2a: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8011e2c: 683b ldr r3, [r7, #0] 8011e2e: 681b ldr r3, [r3, #0] 8011e30: 68fa ldr r2, [r7, #12] 8011e32: 4313 orrs r3, r2 8011e34: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8011e36: 687b ldr r3, [r7, #4] 8011e38: 681b ldr r3, [r3, #0] 8011e3a: 68fa ldr r2, [r7, #12] 8011e3c: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8011e3e: 687b ldr r3, [r7, #4] 8011e40: 681b ldr r3, [r3, #0] 8011e42: 4a19 ldr r2, [pc, #100] @ (8011ea8 ) 8011e44: 4293 cmp r3, r2 8011e46: d013 beq.n 8011e70 8011e48: 687b ldr r3, [r7, #4] 8011e4a: 681b ldr r3, [r3, #0] 8011e4c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8011e50: d00e beq.n 8011e70 8011e52: 687b ldr r3, [r7, #4] 8011e54: 681b ldr r3, [r3, #0] 8011e56: 4a15 ldr r2, [pc, #84] @ (8011eac ) 8011e58: 4293 cmp r3, r2 8011e5a: d009 beq.n 8011e70 8011e5c: 687b ldr r3, [r7, #4] 8011e5e: 681b ldr r3, [r3, #0] 8011e60: 4a13 ldr r2, [pc, #76] @ (8011eb0 ) 8011e62: 4293 cmp r3, r2 8011e64: d004 beq.n 8011e70 8011e66: 687b ldr r3, [r7, #4] 8011e68: 681b ldr r3, [r3, #0] 8011e6a: 4a12 ldr r2, [pc, #72] @ (8011eb4 ) 8011e6c: 4293 cmp r3, r2 8011e6e: d10c bne.n 8011e8a { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8011e70: 68bb ldr r3, [r7, #8] 8011e72: f023 0380 bic.w r3, r3, #128 @ 0x80 8011e76: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8011e78: 683b ldr r3, [r7, #0] 8011e7a: 685b ldr r3, [r3, #4] 8011e7c: 68ba ldr r2, [r7, #8] 8011e7e: 4313 orrs r3, r2 8011e80: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8011e82: 687b ldr r3, [r7, #4] 8011e84: 681b ldr r3, [r3, #0] 8011e86: 68ba ldr r2, [r7, #8] 8011e88: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8011e8a: 687b ldr r3, [r7, #4] 8011e8c: 2201 movs r2, #1 8011e8e: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8011e92: 687b ldr r3, [r7, #4] 8011e94: 2200 movs r2, #0 8011e96: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8011e9a: 2300 movs r3, #0 } 8011e9c: 4618 mov r0, r3 8011e9e: 3714 adds r7, #20 8011ea0: 46bd mov sp, r7 8011ea2: bc80 pop {r7} 8011ea4: 4770 bx lr 8011ea6: bf00 nop 8011ea8: 40012c00 .word 0x40012c00 8011eac: 40000400 .word 0x40000400 8011eb0: 40000800 .word 0x40000800 8011eb4: 40000c00 .word 0x40000c00 08011eb8 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8011eb8: b480 push {r7} 8011eba: b083 sub sp, #12 8011ebc: af00 add r7, sp, #0 8011ebe: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8011ec0: bf00 nop 8011ec2: 370c adds r7, #12 8011ec4: 46bd mov sp, r7 8011ec6: bc80 pop {r7} 8011ec8: 4770 bx lr 08011eca : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8011eca: b480 push {r7} 8011ecc: b083 sub sp, #12 8011ece: af00 add r7, sp, #0 8011ed0: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8011ed2: bf00 nop 8011ed4: 370c adds r7, #12 8011ed6: 46bd mov sp, r7 8011ed8: bc80 pop {r7} 8011eda: 4770 bx lr 08011edc : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8011edc: b580 push {r7, lr} 8011ede: b082 sub sp, #8 8011ee0: af00 add r7, sp, #0 8011ee2: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8011ee4: 687b ldr r3, [r7, #4] 8011ee6: 2b00 cmp r3, #0 8011ee8: d101 bne.n 8011eee { return HAL_ERROR; 8011eea: 2301 movs r3, #1 8011eec: e042 b.n 8011f74 assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 8011eee: 687b ldr r3, [r7, #4] 8011ef0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011ef4: b2db uxtb r3, r3 8011ef6: 2b00 cmp r3, #0 8011ef8: d106 bne.n 8011f08 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8011efa: 687b ldr r3, [r7, #4] 8011efc: 2200 movs r2, #0 8011efe: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8011f02: 6878 ldr r0, [r7, #4] 8011f04: f7fb fc6c bl 800d7e0 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8011f08: 687b ldr r3, [r7, #4] 8011f0a: 2224 movs r2, #36 @ 0x24 8011f0c: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8011f10: 687b ldr r3, [r7, #4] 8011f12: 681b ldr r3, [r3, #0] 8011f14: 68da ldr r2, [r3, #12] 8011f16: 687b ldr r3, [r7, #4] 8011f18: 681b ldr r3, [r3, #0] 8011f1a: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8011f1e: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8011f20: 6878 ldr r0, [r7, #4] 8011f22: f000 ffb5 bl 8012e90 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8011f26: 687b ldr r3, [r7, #4] 8011f28: 681b ldr r3, [r3, #0] 8011f2a: 691a ldr r2, [r3, #16] 8011f2c: 687b ldr r3, [r7, #4] 8011f2e: 681b ldr r3, [r3, #0] 8011f30: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8011f34: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8011f36: 687b ldr r3, [r7, #4] 8011f38: 681b ldr r3, [r3, #0] 8011f3a: 695a ldr r2, [r3, #20] 8011f3c: 687b ldr r3, [r7, #4] 8011f3e: 681b ldr r3, [r3, #0] 8011f40: f022 022a bic.w r2, r2, #42 @ 0x2a 8011f44: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8011f46: 687b ldr r3, [r7, #4] 8011f48: 681b ldr r3, [r3, #0] 8011f4a: 68da ldr r2, [r3, #12] 8011f4c: 687b ldr r3, [r7, #4] 8011f4e: 681b ldr r3, [r3, #0] 8011f50: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8011f54: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8011f56: 687b ldr r3, [r7, #4] 8011f58: 2200 movs r2, #0 8011f5a: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8011f5c: 687b ldr r3, [r7, #4] 8011f5e: 2220 movs r2, #32 8011f60: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8011f64: 687b ldr r3, [r7, #4] 8011f66: 2220 movs r2, #32 8011f68: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8011f6c: 687b ldr r3, [r7, #4] 8011f6e: 2200 movs r2, #0 8011f70: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8011f72: 2300 movs r3, #0 } 8011f74: 4618 mov r0, r3 8011f76: 3708 adds r7, #8 8011f78: 46bd mov sp, r7 8011f7a: bd80 pop {r7, pc} 08011f7c : * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8011f7c: b580 push {r7, lr} 8011f7e: b08a sub sp, #40 @ 0x28 8011f80: af02 add r7, sp, #8 8011f82: 60f8 str r0, [r7, #12] 8011f84: 60b9 str r1, [r7, #8] 8011f86: 603b str r3, [r7, #0] 8011f88: 4613 mov r3, r2 8011f8a: 80fb strh r3, [r7, #6] const uint8_t *pdata8bits; const uint16_t *pdata16bits; uint32_t tickstart = 0U; 8011f8c: 2300 movs r3, #0 8011f8e: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8011f90: 68fb ldr r3, [r7, #12] 8011f92: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011f96: b2db uxtb r3, r3 8011f98: 2b20 cmp r3, #32 8011f9a: d175 bne.n 8012088 { if ((pData == NULL) || (Size == 0U)) 8011f9c: 68bb ldr r3, [r7, #8] 8011f9e: 2b00 cmp r3, #0 8011fa0: d002 beq.n 8011fa8 8011fa2: 88fb ldrh r3, [r7, #6] 8011fa4: 2b00 cmp r3, #0 8011fa6: d101 bne.n 8011fac { return HAL_ERROR; 8011fa8: 2301 movs r3, #1 8011faa: e06e b.n 801208a } huart->ErrorCode = HAL_UART_ERROR_NONE; 8011fac: 68fb ldr r3, [r7, #12] 8011fae: 2200 movs r2, #0 8011fb0: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8011fb2: 68fb ldr r3, [r7, #12] 8011fb4: 2221 movs r2, #33 @ 0x21 8011fb6: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8011fba: f7fb fdd9 bl 800db70 8011fbe: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 8011fc0: 68fb ldr r3, [r7, #12] 8011fc2: 88fa ldrh r2, [r7, #6] 8011fc4: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8011fc6: 68fb ldr r3, [r7, #12] 8011fc8: 88fa ldrh r2, [r7, #6] 8011fca: 84da strh r2, [r3, #38] @ 0x26 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8011fcc: 68fb ldr r3, [r7, #12] 8011fce: 689b ldr r3, [r3, #8] 8011fd0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8011fd4: d108 bne.n 8011fe8 8011fd6: 68fb ldr r3, [r7, #12] 8011fd8: 691b ldr r3, [r3, #16] 8011fda: 2b00 cmp r3, #0 8011fdc: d104 bne.n 8011fe8 { pdata8bits = NULL; 8011fde: 2300 movs r3, #0 8011fe0: 61fb str r3, [r7, #28] pdata16bits = (const uint16_t *) pData; 8011fe2: 68bb ldr r3, [r7, #8] 8011fe4: 61bb str r3, [r7, #24] 8011fe6: e003 b.n 8011ff0 } else { pdata8bits = pData; 8011fe8: 68bb ldr r3, [r7, #8] 8011fea: 61fb str r3, [r7, #28] pdata16bits = NULL; 8011fec: 2300 movs r3, #0 8011fee: 61bb str r3, [r7, #24] } while (huart->TxXferCount > 0U) 8011ff0: e02e b.n 8012050 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8011ff2: 683b ldr r3, [r7, #0] 8011ff4: 9300 str r3, [sp, #0] 8011ff6: 697b ldr r3, [r7, #20] 8011ff8: 2200 movs r2, #0 8011ffa: 2180 movs r1, #128 @ 0x80 8011ffc: 68f8 ldr r0, [r7, #12] 8011ffe: f000 fcb9 bl 8012974 8012002: 4603 mov r3, r0 8012004: 2b00 cmp r3, #0 8012006: d005 beq.n 8012014 { huart->gState = HAL_UART_STATE_READY; 8012008: 68fb ldr r3, [r7, #12] 801200a: 2220 movs r2, #32 801200c: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_TIMEOUT; 8012010: 2303 movs r3, #3 8012012: e03a b.n 801208a } if (pdata8bits == NULL) 8012014: 69fb ldr r3, [r7, #28] 8012016: 2b00 cmp r3, #0 8012018: d10b bne.n 8012032 { huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); 801201a: 69bb ldr r3, [r7, #24] 801201c: 881b ldrh r3, [r3, #0] 801201e: 461a mov r2, r3 8012020: 68fb ldr r3, [r7, #12] 8012022: 681b ldr r3, [r3, #0] 8012024: f3c2 0208 ubfx r2, r2, #0, #9 8012028: 605a str r2, [r3, #4] pdata16bits++; 801202a: 69bb ldr r3, [r7, #24] 801202c: 3302 adds r3, #2 801202e: 61bb str r3, [r7, #24] 8012030: e007 b.n 8012042 } else { huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); 8012032: 69fb ldr r3, [r7, #28] 8012034: 781a ldrb r2, [r3, #0] 8012036: 68fb ldr r3, [r7, #12] 8012038: 681b ldr r3, [r3, #0] 801203a: 605a str r2, [r3, #4] pdata8bits++; 801203c: 69fb ldr r3, [r7, #28] 801203e: 3301 adds r3, #1 8012040: 61fb str r3, [r7, #28] } huart->TxXferCount--; 8012042: 68fb ldr r3, [r7, #12] 8012044: 8cdb ldrh r3, [r3, #38] @ 0x26 8012046: b29b uxth r3, r3 8012048: 3b01 subs r3, #1 801204a: b29a uxth r2, r3 801204c: 68fb ldr r3, [r7, #12] 801204e: 84da strh r2, [r3, #38] @ 0x26 while (huart->TxXferCount > 0U) 8012050: 68fb ldr r3, [r7, #12] 8012052: 8cdb ldrh r3, [r3, #38] @ 0x26 8012054: b29b uxth r3, r3 8012056: 2b00 cmp r3, #0 8012058: d1cb bne.n 8011ff2 } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 801205a: 683b ldr r3, [r7, #0] 801205c: 9300 str r3, [sp, #0] 801205e: 697b ldr r3, [r7, #20] 8012060: 2200 movs r2, #0 8012062: 2140 movs r1, #64 @ 0x40 8012064: 68f8 ldr r0, [r7, #12] 8012066: f000 fc85 bl 8012974 801206a: 4603 mov r3, r0 801206c: 2b00 cmp r3, #0 801206e: d005 beq.n 801207c { huart->gState = HAL_UART_STATE_READY; 8012070: 68fb ldr r3, [r7, #12] 8012072: 2220 movs r2, #32 8012074: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_TIMEOUT; 8012078: 2303 movs r3, #3 801207a: e006 b.n 801208a } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 801207c: 68fb ldr r3, [r7, #12] 801207e: 2220 movs r2, #32 8012080: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_OK; 8012084: 2300 movs r3, #0 8012086: e000 b.n 801208a } else { return HAL_BUSY; 8012088: 2302 movs r3, #2 } } 801208a: 4618 mov r0, r3 801208c: 3720 adds r7, #32 801208e: 46bd mov sp, r7 8012090: bd80 pop {r7, pc} 08012092 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8012092: b480 push {r7} 8012094: b085 sub sp, #20 8012096: af00 add r7, sp, #0 8012098: 60f8 str r0, [r7, #12] 801209a: 60b9 str r1, [r7, #8] 801209c: 4613 mov r3, r2 801209e: 80fb strh r3, [r7, #6] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 80120a0: 68fb ldr r3, [r7, #12] 80120a2: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80120a6: b2db uxtb r3, r3 80120a8: 2b20 cmp r3, #32 80120aa: d121 bne.n 80120f0 { if ((pData == NULL) || (Size == 0U)) 80120ac: 68bb ldr r3, [r7, #8] 80120ae: 2b00 cmp r3, #0 80120b0: d002 beq.n 80120b8 80120b2: 88fb ldrh r3, [r7, #6] 80120b4: 2b00 cmp r3, #0 80120b6: d101 bne.n 80120bc { return HAL_ERROR; 80120b8: 2301 movs r3, #1 80120ba: e01a b.n 80120f2 } huart->pTxBuffPtr = pData; 80120bc: 68fb ldr r3, [r7, #12] 80120be: 68ba ldr r2, [r7, #8] 80120c0: 621a str r2, [r3, #32] huart->TxXferSize = Size; 80120c2: 68fb ldr r3, [r7, #12] 80120c4: 88fa ldrh r2, [r7, #6] 80120c6: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 80120c8: 68fb ldr r3, [r7, #12] 80120ca: 88fa ldrh r2, [r7, #6] 80120cc: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 80120ce: 68fb ldr r3, [r7, #12] 80120d0: 2200 movs r2, #0 80120d2: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 80120d4: 68fb ldr r3, [r7, #12] 80120d6: 2221 movs r2, #33 @ 0x21 80120d8: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the UART Transmit data register empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); 80120dc: 68fb ldr r3, [r7, #12] 80120de: 681b ldr r3, [r3, #0] 80120e0: 68da ldr r2, [r3, #12] 80120e2: 68fb ldr r3, [r7, #12] 80120e4: 681b ldr r3, [r3, #0] 80120e6: f042 0280 orr.w r2, r2, #128 @ 0x80 80120ea: 60da str r2, [r3, #12] return HAL_OK; 80120ec: 2300 movs r3, #0 80120ee: e000 b.n 80120f2 } else { return HAL_BUSY; 80120f0: 2302 movs r3, #2 } } 80120f2: 4618 mov r0, r3 80120f4: 3714 adds r7, #20 80120f6: 46bd mov sp, r7 80120f8: bc80 pop {r7} 80120fa: 4770 bx lr 080120fc : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80120fc: b580 push {r7, lr} 80120fe: b08c sub sp, #48 @ 0x30 8012100: af00 add r7, sp, #0 8012102: 60f8 str r0, [r7, #12] 8012104: 60b9 str r1, [r7, #8] 8012106: 4613 mov r3, r2 8012108: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 801210a: 68fb ldr r3, [r7, #12] 801210c: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8012110: b2db uxtb r3, r3 8012112: 2b20 cmp r3, #32 8012114: d14a bne.n 80121ac { if ((pData == NULL) || (Size == 0U)) 8012116: 68bb ldr r3, [r7, #8] 8012118: 2b00 cmp r3, #0 801211a: d002 beq.n 8012122 801211c: 88fb ldrh r3, [r7, #6] 801211e: 2b00 cmp r3, #0 8012120: d101 bne.n 8012126 { return HAL_ERROR; 8012122: 2301 movs r3, #1 8012124: e043 b.n 80121ae } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8012126: 68fb ldr r3, [r7, #12] 8012128: 2201 movs r2, #1 801212a: 631a str r2, [r3, #48] @ 0x30 huart->RxEventType = HAL_UART_RXEVENT_TC; 801212c: 68fb ldr r3, [r7, #12] 801212e: 2200 movs r2, #0 8012130: 635a str r2, [r3, #52] @ 0x34 status = UART_Start_Receive_IT(huart, pData, Size); 8012132: 88fb ldrh r3, [r7, #6] 8012134: 461a mov r2, r3 8012136: 68b9 ldr r1, [r7, #8] 8012138: 68f8 ldr r0, [r7, #12] 801213a: f000 fc74 bl 8012a26 801213e: 4603 mov r3, r0 8012140: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check Rx process has been successfully started */ if (status == HAL_OK) 8012144: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8012148: 2b00 cmp r3, #0 801214a: d12c bne.n 80121a6 { if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 801214c: 68fb ldr r3, [r7, #12] 801214e: 6b1b ldr r3, [r3, #48] @ 0x30 8012150: 2b01 cmp r3, #1 8012152: d125 bne.n 80121a0 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8012154: 2300 movs r3, #0 8012156: 613b str r3, [r7, #16] 8012158: 68fb ldr r3, [r7, #12] 801215a: 681b ldr r3, [r3, #0] 801215c: 681b ldr r3, [r3, #0] 801215e: 613b str r3, [r7, #16] 8012160: 68fb ldr r3, [r7, #12] 8012162: 681b ldr r3, [r3, #0] 8012164: 685b ldr r3, [r3, #4] 8012166: 613b str r3, [r7, #16] 8012168: 693b ldr r3, [r7, #16] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801216a: 68fb ldr r3, [r7, #12] 801216c: 681b ldr r3, [r3, #0] 801216e: 330c adds r3, #12 8012170: 61bb str r3, [r7, #24] */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012172: 69bb ldr r3, [r7, #24] 8012174: e853 3f00 ldrex r3, [r3] 8012178: 617b str r3, [r7, #20] return(result); 801217a: 697b ldr r3, [r7, #20] 801217c: f043 0310 orr.w r3, r3, #16 8012180: 62bb str r3, [r7, #40] @ 0x28 8012182: 68fb ldr r3, [r7, #12] 8012184: 681b ldr r3, [r3, #0] 8012186: 330c adds r3, #12 8012188: 6aba ldr r2, [r7, #40] @ 0x28 801218a: 627a str r2, [r7, #36] @ 0x24 801218c: 623b str r3, [r7, #32] */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801218e: 6a39 ldr r1, [r7, #32] 8012190: 6a7a ldr r2, [r7, #36] @ 0x24 8012192: e841 2300 strex r3, r2, [r1] 8012196: 61fb str r3, [r7, #28] return(result); 8012198: 69fb ldr r3, [r7, #28] 801219a: 2b00 cmp r3, #0 801219c: d1e5 bne.n 801216a 801219e: e002 b.n 80121a6 { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 80121a0: 2301 movs r3, #1 80121a2: f887 302f strb.w r3, [r7, #47] @ 0x2f } } return status; 80121a6: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 80121aa: e000 b.n 80121ae } else { return HAL_BUSY; 80121ac: 2302 movs r3, #2 } } 80121ae: 4618 mov r0, r3 80121b0: 3730 adds r7, #48 @ 0x30 80121b2: 46bd mov sp, r7 80121b4: bd80 pop {r7, pc} ... 080121b8 : * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { 80121b8: b580 push {r7, lr} 80121ba: b0a2 sub sp, #136 @ 0x88 80121bc: af00 add r7, sp, #0 80121be: 6078 str r0, [r7, #4] uint32_t AbortCplt = 0x01U; 80121c0: 2301 movs r3, #1 80121c2: f8c7 3084 str.w r3, [r7, #132] @ 0x84 /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); 80121c6: 687b ldr r3, [r7, #4] 80121c8: 681b ldr r3, [r3, #0] 80121ca: 330c adds r3, #12 80121cc: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80121ce: 6e3b ldr r3, [r7, #96] @ 0x60 80121d0: e853 3f00 ldrex r3, [r3] 80121d4: 65fb str r3, [r7, #92] @ 0x5c return(result); 80121d6: 6dfb ldr r3, [r7, #92] @ 0x5c 80121d8: f423 73f0 bic.w r3, r3, #480 @ 0x1e0 80121dc: f8c7 3080 str.w r3, [r7, #128] @ 0x80 80121e0: 687b ldr r3, [r7, #4] 80121e2: 681b ldr r3, [r3, #0] 80121e4: 330c adds r3, #12 80121e6: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 80121ea: 66fa str r2, [r7, #108] @ 0x6c 80121ec: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80121ee: 6eb9 ldr r1, [r7, #104] @ 0x68 80121f0: 6efa ldr r2, [r7, #108] @ 0x6c 80121f2: e841 2300 strex r3, r2, [r1] 80121f6: 667b str r3, [r7, #100] @ 0x64 return(result); 80121f8: 6e7b ldr r3, [r7, #100] @ 0x64 80121fa: 2b00 cmp r3, #0 80121fc: d1e3 bne.n 80121c6 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80121fe: 687b ldr r3, [r7, #4] 8012200: 681b ldr r3, [r3, #0] 8012202: 3314 adds r3, #20 8012204: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012206: 6cfb ldr r3, [r7, #76] @ 0x4c 8012208: e853 3f00 ldrex r3, [r3] 801220c: 64bb str r3, [r7, #72] @ 0x48 return(result); 801220e: 6cbb ldr r3, [r7, #72] @ 0x48 8012210: f023 0301 bic.w r3, r3, #1 8012214: 67fb str r3, [r7, #124] @ 0x7c 8012216: 687b ldr r3, [r7, #4] 8012218: 681b ldr r3, [r3, #0] 801221a: 3314 adds r3, #20 801221c: 6ffa ldr r2, [r7, #124] @ 0x7c 801221e: 65ba str r2, [r7, #88] @ 0x58 8012220: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012222: 6d79 ldr r1, [r7, #84] @ 0x54 8012224: 6dba ldr r2, [r7, #88] @ 0x58 8012226: e841 2300 strex r3, r2, [r1] 801222a: 653b str r3, [r7, #80] @ 0x50 return(result); 801222c: 6d3b ldr r3, [r7, #80] @ 0x50 801222e: 2b00 cmp r3, #0 8012230: d1e5 bne.n 80121fe /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012232: 687b ldr r3, [r7, #4] 8012234: 6b1b ldr r3, [r3, #48] @ 0x30 8012236: 2b01 cmp r3, #1 8012238: d119 bne.n 801226e { ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); 801223a: 687b ldr r3, [r7, #4] 801223c: 681b ldr r3, [r3, #0] 801223e: 330c adds r3, #12 8012240: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012242: 6bbb ldr r3, [r7, #56] @ 0x38 8012244: e853 3f00 ldrex r3, [r3] 8012248: 637b str r3, [r7, #52] @ 0x34 return(result); 801224a: 6b7b ldr r3, [r7, #52] @ 0x34 801224c: f023 0310 bic.w r3, r3, #16 8012250: 67bb str r3, [r7, #120] @ 0x78 8012252: 687b ldr r3, [r7, #4] 8012254: 681b ldr r3, [r3, #0] 8012256: 330c adds r3, #12 8012258: 6fba ldr r2, [r7, #120] @ 0x78 801225a: 647a str r2, [r7, #68] @ 0x44 801225c: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801225e: 6c39 ldr r1, [r7, #64] @ 0x40 8012260: 6c7a ldr r2, [r7, #68] @ 0x44 8012262: e841 2300 strex r3, r2, [r1] 8012266: 63fb str r3, [r7, #60] @ 0x3c return(result); 8012268: 6bfb ldr r3, [r7, #60] @ 0x3c 801226a: 2b00 cmp r3, #0 801226c: d1e5 bne.n 801223a } /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ if (huart->hdmatx != NULL) 801226e: 687b ldr r3, [r7, #4] 8012270: 6b9b ldr r3, [r3, #56] @ 0x38 8012272: 2b00 cmp r3, #0 8012274: d00f beq.n 8012296 { /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. Otherwise, set it to NULL */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) 8012276: 687b ldr r3, [r7, #4] 8012278: 681b ldr r3, [r3, #0] 801227a: 695b ldr r3, [r3, #20] 801227c: f003 0380 and.w r3, r3, #128 @ 0x80 8012280: 2b00 cmp r3, #0 8012282: d004 beq.n 801228e { huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; 8012284: 687b ldr r3, [r7, #4] 8012286: 6b9b ldr r3, [r3, #56] @ 0x38 8012288: 4a53 ldr r2, [pc, #332] @ (80123d8 ) 801228a: 635a str r2, [r3, #52] @ 0x34 801228c: e003 b.n 8012296 } else { huart->hdmatx->XferAbortCallback = NULL; 801228e: 687b ldr r3, [r7, #4] 8012290: 6b9b ldr r3, [r3, #56] @ 0x38 8012292: 2200 movs r2, #0 8012294: 635a str r2, [r3, #52] @ 0x34 } } /* DMA Rx Handle is valid */ if (huart->hdmarx != NULL) 8012296: 687b ldr r3, [r7, #4] 8012298: 6bdb ldr r3, [r3, #60] @ 0x3c 801229a: 2b00 cmp r3, #0 801229c: d00f beq.n 80122be { /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. Otherwise, set it to NULL */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801229e: 687b ldr r3, [r7, #4] 80122a0: 681b ldr r3, [r3, #0] 80122a2: 695b ldr r3, [r3, #20] 80122a4: f003 0340 and.w r3, r3, #64 @ 0x40 80122a8: 2b00 cmp r3, #0 80122aa: d004 beq.n 80122b6 { huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; 80122ac: 687b ldr r3, [r7, #4] 80122ae: 6bdb ldr r3, [r3, #60] @ 0x3c 80122b0: 4a4a ldr r2, [pc, #296] @ (80123dc ) 80122b2: 635a str r2, [r3, #52] @ 0x34 80122b4: e003 b.n 80122be } else { huart->hdmarx->XferAbortCallback = NULL; 80122b6: 687b ldr r3, [r7, #4] 80122b8: 6bdb ldr r3, [r3, #60] @ 0x3c 80122ba: 2200 movs r2, #0 80122bc: 635a str r2, [r3, #52] @ 0x34 } } /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) 80122be: 687b ldr r3, [r7, #4] 80122c0: 681b ldr r3, [r3, #0] 80122c2: 695b ldr r3, [r3, #20] 80122c4: f003 0380 and.w r3, r3, #128 @ 0x80 80122c8: 2b00 cmp r3, #0 80122ca: d02d beq.n 8012328 { /* Disable DMA Tx at UART level */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 80122cc: 687b ldr r3, [r7, #4] 80122ce: 681b ldr r3, [r3, #0] 80122d0: 3314 adds r3, #20 80122d2: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80122d4: 6a7b ldr r3, [r7, #36] @ 0x24 80122d6: e853 3f00 ldrex r3, [r3] 80122da: 623b str r3, [r7, #32] return(result); 80122dc: 6a3b ldr r3, [r7, #32] 80122de: f023 0380 bic.w r3, r3, #128 @ 0x80 80122e2: 677b str r3, [r7, #116] @ 0x74 80122e4: 687b ldr r3, [r7, #4] 80122e6: 681b ldr r3, [r3, #0] 80122e8: 3314 adds r3, #20 80122ea: 6f7a ldr r2, [r7, #116] @ 0x74 80122ec: 633a str r2, [r7, #48] @ 0x30 80122ee: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80122f0: 6af9 ldr r1, [r7, #44] @ 0x2c 80122f2: 6b3a ldr r2, [r7, #48] @ 0x30 80122f4: e841 2300 strex r3, r2, [r1] 80122f8: 62bb str r3, [r7, #40] @ 0x28 return(result); 80122fa: 6abb ldr r3, [r7, #40] @ 0x28 80122fc: 2b00 cmp r3, #0 80122fe: d1e5 bne.n 80122cc /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) 8012300: 687b ldr r3, [r7, #4] 8012302: 6b9b ldr r3, [r3, #56] @ 0x38 8012304: 2b00 cmp r3, #0 8012306: d00f beq.n 8012328 { /* UART Tx DMA Abort callback has already been initialised : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA TX */ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) 8012308: 687b ldr r3, [r7, #4] 801230a: 6b9b ldr r3, [r3, #56] @ 0x38 801230c: 4618 mov r0, r3 801230e: f7fd f99d bl 800f64c 8012312: 4603 mov r3, r0 8012314: 2b00 cmp r3, #0 8012316: d004 beq.n 8012322 { huart->hdmatx->XferAbortCallback = NULL; 8012318: 687b ldr r3, [r7, #4] 801231a: 6b9b ldr r3, [r3, #56] @ 0x38 801231c: 2200 movs r2, #0 801231e: 635a str r2, [r3, #52] @ 0x34 8012320: e002 b.n 8012328 } else { AbortCplt = 0x00U; 8012322: 2300 movs r3, #0 8012324: f8c7 3084 str.w r3, [r7, #132] @ 0x84 } } } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8012328: 687b ldr r3, [r7, #4] 801232a: 681b ldr r3, [r3, #0] 801232c: 695b ldr r3, [r3, #20] 801232e: f003 0340 and.w r3, r3, #64 @ 0x40 8012332: 2b00 cmp r3, #0 8012334: d030 beq.n 8012398 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8012336: 687b ldr r3, [r7, #4] 8012338: 681b ldr r3, [r3, #0] 801233a: 3314 adds r3, #20 801233c: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801233e: 693b ldr r3, [r7, #16] 8012340: e853 3f00 ldrex r3, [r3] 8012344: 60fb str r3, [r7, #12] return(result); 8012346: 68fb ldr r3, [r7, #12] 8012348: f023 0340 bic.w r3, r3, #64 @ 0x40 801234c: 673b str r3, [r7, #112] @ 0x70 801234e: 687b ldr r3, [r7, #4] 8012350: 681b ldr r3, [r3, #0] 8012352: 3314 adds r3, #20 8012354: 6f3a ldr r2, [r7, #112] @ 0x70 8012356: 61fa str r2, [r7, #28] 8012358: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801235a: 69b9 ldr r1, [r7, #24] 801235c: 69fa ldr r2, [r7, #28] 801235e: e841 2300 strex r3, r2, [r1] 8012362: 617b str r3, [r7, #20] return(result); 8012364: 697b ldr r3, [r7, #20] 8012366: 2b00 cmp r3, #0 8012368: d1e5 bne.n 8012336 /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) 801236a: 687b ldr r3, [r7, #4] 801236c: 6bdb ldr r3, [r3, #60] @ 0x3c 801236e: 2b00 cmp r3, #0 8012370: d012 beq.n 8012398 { /* UART Rx DMA Abort callback has already been initialised : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8012372: 687b ldr r3, [r7, #4] 8012374: 6bdb ldr r3, [r3, #60] @ 0x3c 8012376: 4618 mov r0, r3 8012378: f7fd f968 bl 800f64c 801237c: 4603 mov r3, r0 801237e: 2b00 cmp r3, #0 8012380: d007 beq.n 8012392 { huart->hdmarx->XferAbortCallback = NULL; 8012382: 687b ldr r3, [r7, #4] 8012384: 6bdb ldr r3, [r3, #60] @ 0x3c 8012386: 2200 movs r2, #0 8012388: 635a str r2, [r3, #52] @ 0x34 AbortCplt = 0x01U; 801238a: 2301 movs r3, #1 801238c: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8012390: e002 b.n 8012398 } else { AbortCplt = 0x00U; 8012392: 2300 movs r3, #0 8012394: f8c7 3084 str.w r3, [r7, #132] @ 0x84 } } } /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (AbortCplt == 0x01U) 8012398: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 801239c: 2b01 cmp r3, #1 801239e: d116 bne.n 80123ce { /* Reset Tx and Rx transfer counters */ huart->TxXferCount = 0x00U; 80123a0: 687b ldr r3, [r7, #4] 80123a2: 2200 movs r2, #0 80123a4: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 80123a6: 687b ldr r3, [r7, #4] 80123a8: 2200 movs r2, #0 80123aa: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80123ac: 687b ldr r3, [r7, #4] 80123ae: 2200 movs r2, #0 80123b0: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 80123b2: 687b ldr r3, [r7, #4] 80123b4: 2220 movs r2, #32 80123b6: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 80123ba: 687b ldr r3, [r7, #4] 80123bc: 2220 movs r2, #32 80123be: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80123c2: 687b ldr r3, [r7, #4] 80123c4: 2200 movs r2, #0 80123c6: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 80123c8: 6878 ldr r0, [r7, #4] 80123ca: f000 faad bl 8012928 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 80123ce: 2300 movs r3, #0 } 80123d0: 4618 mov r0, r3 80123d2: 3788 adds r7, #136 @ 0x88 80123d4: 46bd mov sp, r7 80123d6: bd80 pop {r7, pc} 80123d8: 08012b85 .word 0x08012b85 80123dc: 08012be5 .word 0x08012be5 080123e0 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 80123e0: b580 push {r7, lr} 80123e2: b0ba sub sp, #232 @ 0xe8 80123e4: af00 add r7, sp, #0 80123e6: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 80123e8: 687b ldr r3, [r7, #4] 80123ea: 681b ldr r3, [r3, #0] 80123ec: 681b ldr r3, [r3, #0] 80123ee: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 80123f2: 687b ldr r3, [r7, #4] 80123f4: 681b ldr r3, [r3, #0] 80123f6: 68db ldr r3, [r3, #12] 80123f8: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 80123fc: 687b ldr r3, [r7, #4] 80123fe: 681b ldr r3, [r3, #0] 8012400: 695b ldr r3, [r3, #20] 8012402: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 8012406: 2300 movs r3, #0 8012408: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 801240c: 2300 movs r3, #0 801240e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8012412: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012416: f003 030f and.w r3, r3, #15 801241a: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 801241e: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8012422: 2b00 cmp r3, #0 8012424: d10f bne.n 8012446 { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8012426: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801242a: f003 0320 and.w r3, r3, #32 801242e: 2b00 cmp r3, #0 8012430: d009 beq.n 8012446 8012432: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012436: f003 0320 and.w r3, r3, #32 801243a: 2b00 cmp r3, #0 801243c: d003 beq.n 8012446 { UART_Receive_IT(huart); 801243e: 6878 ldr r0, [r7, #4] 8012440: f000 fc67 bl 8012d12 return; 8012444: e25b b.n 80128fe } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 8012446: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 801244a: 2b00 cmp r3, #0 801244c: f000 80de beq.w 801260c 8012450: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8012454: f003 0301 and.w r3, r3, #1 8012458: 2b00 cmp r3, #0 801245a: d106 bne.n 801246a || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 801245c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012460: f403 7390 and.w r3, r3, #288 @ 0x120 8012464: 2b00 cmp r3, #0 8012466: f000 80d1 beq.w 801260c { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 801246a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801246e: f003 0301 and.w r3, r3, #1 8012472: 2b00 cmp r3, #0 8012474: d00b beq.n 801248e 8012476: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801247a: f403 7380 and.w r3, r3, #256 @ 0x100 801247e: 2b00 cmp r3, #0 8012480: d005 beq.n 801248e { huart->ErrorCode |= HAL_UART_ERROR_PE; 8012482: 687b ldr r3, [r7, #4] 8012484: 6c5b ldr r3, [r3, #68] @ 0x44 8012486: f043 0201 orr.w r2, r3, #1 801248a: 687b ldr r3, [r7, #4] 801248c: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 801248e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012492: f003 0304 and.w r3, r3, #4 8012496: 2b00 cmp r3, #0 8012498: d00b beq.n 80124b2 801249a: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 801249e: f003 0301 and.w r3, r3, #1 80124a2: 2b00 cmp r3, #0 80124a4: d005 beq.n 80124b2 { huart->ErrorCode |= HAL_UART_ERROR_NE; 80124a6: 687b ldr r3, [r7, #4] 80124a8: 6c5b ldr r3, [r3, #68] @ 0x44 80124aa: f043 0202 orr.w r2, r3, #2 80124ae: 687b ldr r3, [r7, #4] 80124b0: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 80124b2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80124b6: f003 0302 and.w r3, r3, #2 80124ba: 2b00 cmp r3, #0 80124bc: d00b beq.n 80124d6 80124be: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80124c2: f003 0301 and.w r3, r3, #1 80124c6: 2b00 cmp r3, #0 80124c8: d005 beq.n 80124d6 { huart->ErrorCode |= HAL_UART_ERROR_FE; 80124ca: 687b ldr r3, [r7, #4] 80124cc: 6c5b ldr r3, [r3, #68] @ 0x44 80124ce: f043 0204 orr.w r2, r3, #4 80124d2: 687b ldr r3, [r7, #4] 80124d4: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 80124d6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80124da: f003 0308 and.w r3, r3, #8 80124de: 2b00 cmp r3, #0 80124e0: d011 beq.n 8012506 80124e2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80124e6: f003 0320 and.w r3, r3, #32 80124ea: 2b00 cmp r3, #0 80124ec: d105 bne.n 80124fa || ((cr3its & USART_CR3_EIE) != RESET))) 80124ee: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80124f2: f003 0301 and.w r3, r3, #1 80124f6: 2b00 cmp r3, #0 80124f8: d005 beq.n 8012506 { huart->ErrorCode |= HAL_UART_ERROR_ORE; 80124fa: 687b ldr r3, [r7, #4] 80124fc: 6c5b ldr r3, [r3, #68] @ 0x44 80124fe: f043 0208 orr.w r2, r3, #8 8012502: 687b ldr r3, [r7, #4] 8012504: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8012506: 687b ldr r3, [r7, #4] 8012508: 6c5b ldr r3, [r3, #68] @ 0x44 801250a: 2b00 cmp r3, #0 801250c: f000 81f2 beq.w 80128f4 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8012510: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012514: f003 0320 and.w r3, r3, #32 8012518: 2b00 cmp r3, #0 801251a: d008 beq.n 801252e 801251c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012520: f003 0320 and.w r3, r3, #32 8012524: 2b00 cmp r3, #0 8012526: d002 beq.n 801252e { UART_Receive_IT(huart); 8012528: 6878 ldr r0, [r7, #4] 801252a: f000 fbf2 bl 8012d12 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 801252e: 687b ldr r3, [r7, #4] 8012530: 681b ldr r3, [r3, #0] 8012532: 695b ldr r3, [r3, #20] 8012534: f003 0340 and.w r3, r3, #64 @ 0x40 8012538: 2b00 cmp r3, #0 801253a: bf14 ite ne 801253c: 2301 movne r3, #1 801253e: 2300 moveq r3, #0 8012540: b2db uxtb r3, r3 8012542: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8012546: 687b ldr r3, [r7, #4] 8012548: 6c5b ldr r3, [r3, #68] @ 0x44 801254a: f003 0308 and.w r3, r3, #8 801254e: 2b00 cmp r3, #0 8012550: d103 bne.n 801255a 8012552: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8012556: 2b00 cmp r3, #0 8012558: d04f beq.n 80125fa { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 801255a: 6878 ldr r0, [r7, #4] 801255c: f000 fa9c bl 8012a98 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8012560: 687b ldr r3, [r7, #4] 8012562: 681b ldr r3, [r3, #0] 8012564: 695b ldr r3, [r3, #20] 8012566: f003 0340 and.w r3, r3, #64 @ 0x40 801256a: 2b00 cmp r3, #0 801256c: d041 beq.n 80125f2 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 801256e: 687b ldr r3, [r7, #4] 8012570: 681b ldr r3, [r3, #0] 8012572: 3314 adds r3, #20 8012574: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012578: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 801257c: e853 3f00 ldrex r3, [r3] 8012580: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8012584: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8012588: f023 0340 bic.w r3, r3, #64 @ 0x40 801258c: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8012590: 687b ldr r3, [r7, #4] 8012592: 681b ldr r3, [r3, #0] 8012594: 3314 adds r3, #20 8012596: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 801259a: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 801259e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80125a2: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 80125a6: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 80125aa: e841 2300 strex r3, r2, [r1] 80125ae: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 80125b2: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80125b6: 2b00 cmp r3, #0 80125b8: d1d9 bne.n 801256e /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 80125ba: 687b ldr r3, [r7, #4] 80125bc: 6bdb ldr r3, [r3, #60] @ 0x3c 80125be: 2b00 cmp r3, #0 80125c0: d013 beq.n 80125ea { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 80125c2: 687b ldr r3, [r7, #4] 80125c4: 6bdb ldr r3, [r3, #60] @ 0x3c 80125c6: 4a7e ldr r2, [pc, #504] @ (80127c0 ) 80125c8: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 80125ca: 687b ldr r3, [r7, #4] 80125cc: 6bdb ldr r3, [r3, #60] @ 0x3c 80125ce: 4618 mov r0, r3 80125d0: f7fd f83c bl 800f64c 80125d4: 4603 mov r3, r0 80125d6: 2b00 cmp r3, #0 80125d8: d016 beq.n 8012608 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 80125da: 687b ldr r3, [r7, #4] 80125dc: 6bdb ldr r3, [r3, #60] @ 0x3c 80125de: 6b5b ldr r3, [r3, #52] @ 0x34 80125e0: 687a ldr r2, [r7, #4] 80125e2: 6bd2 ldr r2, [r2, #60] @ 0x3c 80125e4: 4610 mov r0, r2 80125e6: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80125e8: e00e b.n 8012608 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80125ea: 6878 ldr r0, [r7, #4] 80125ec: f000 f993 bl 8012916 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80125f0: e00a b.n 8012608 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80125f2: 6878 ldr r0, [r7, #4] 80125f4: f000 f98f bl 8012916 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80125f8: e006 b.n 8012608 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80125fa: 6878 ldr r0, [r7, #4] 80125fc: f000 f98b bl 8012916 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012600: 687b ldr r3, [r7, #4] 8012602: 2200 movs r2, #0 8012604: 645a str r2, [r3, #68] @ 0x44 } } return; 8012606: e175 b.n 80128f4 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8012608: bf00 nop return; 801260a: e173 b.n 80128f4 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 801260c: 687b ldr r3, [r7, #4] 801260e: 6b1b ldr r3, [r3, #48] @ 0x30 8012610: 2b01 cmp r3, #1 8012612: f040 814f bne.w 80128b4 && ((isrflags & USART_SR_IDLE) != 0U) 8012616: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801261a: f003 0310 and.w r3, r3, #16 801261e: 2b00 cmp r3, #0 8012620: f000 8148 beq.w 80128b4 && ((cr1its & USART_SR_IDLE) != 0U)) 8012624: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012628: f003 0310 and.w r3, r3, #16 801262c: 2b00 cmp r3, #0 801262e: f000 8141 beq.w 80128b4 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8012632: 2300 movs r3, #0 8012634: 60bb str r3, [r7, #8] 8012636: 687b ldr r3, [r7, #4] 8012638: 681b ldr r3, [r3, #0] 801263a: 681b ldr r3, [r3, #0] 801263c: 60bb str r3, [r7, #8] 801263e: 687b ldr r3, [r7, #4] 8012640: 681b ldr r3, [r3, #0] 8012642: 685b ldr r3, [r3, #4] 8012644: 60bb str r3, [r7, #8] 8012646: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8012648: 687b ldr r3, [r7, #4] 801264a: 681b ldr r3, [r3, #0] 801264c: 695b ldr r3, [r3, #20] 801264e: f003 0340 and.w r3, r3, #64 @ 0x40 8012652: 2b00 cmp r3, #0 8012654: f000 80b6 beq.w 80127c4 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8012658: 687b ldr r3, [r7, #4] 801265a: 6bdb ldr r3, [r3, #60] @ 0x3c 801265c: 681b ldr r3, [r3, #0] 801265e: 685b ldr r3, [r3, #4] 8012660: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8012664: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8012668: 2b00 cmp r3, #0 801266a: f000 8145 beq.w 80128f8 && (nb_remaining_rx_data < huart->RxXferSize)) 801266e: 687b ldr r3, [r7, #4] 8012670: 8d9b ldrh r3, [r3, #44] @ 0x2c 8012672: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8012676: 429a cmp r2, r3 8012678: f080 813e bcs.w 80128f8 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 801267c: 687b ldr r3, [r7, #4] 801267e: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8012682: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8012684: 687b ldr r3, [r7, #4] 8012686: 6bdb ldr r3, [r3, #60] @ 0x3c 8012688: 699b ldr r3, [r3, #24] 801268a: 2b20 cmp r3, #32 801268c: f000 8088 beq.w 80127a0 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8012690: 687b ldr r3, [r7, #4] 8012692: 681b ldr r3, [r3, #0] 8012694: 330c adds r3, #12 8012696: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801269a: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 801269e: e853 3f00 ldrex r3, [r3] 80126a2: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 80126a6: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 80126aa: f423 7380 bic.w r3, r3, #256 @ 0x100 80126ae: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 80126b2: 687b ldr r3, [r7, #4] 80126b4: 681b ldr r3, [r3, #0] 80126b6: 330c adds r3, #12 80126b8: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 80126bc: f8c7 2094 str.w r2, [r7, #148] @ 0x94 80126c0: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80126c4: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 80126c8: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 80126cc: e841 2300 strex r3, r2, [r1] 80126d0: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 80126d4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 80126d8: 2b00 cmp r3, #0 80126da: d1d9 bne.n 8012690 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80126dc: 687b ldr r3, [r7, #4] 80126de: 681b ldr r3, [r3, #0] 80126e0: 3314 adds r3, #20 80126e2: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80126e4: 6f7b ldr r3, [r7, #116] @ 0x74 80126e6: e853 3f00 ldrex r3, [r3] 80126ea: 673b str r3, [r7, #112] @ 0x70 return(result); 80126ec: 6f3b ldr r3, [r7, #112] @ 0x70 80126ee: f023 0301 bic.w r3, r3, #1 80126f2: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 80126f6: 687b ldr r3, [r7, #4] 80126f8: 681b ldr r3, [r3, #0] 80126fa: 3314 adds r3, #20 80126fc: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8012700: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8012704: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012706: 6ff9 ldr r1, [r7, #124] @ 0x7c 8012708: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 801270c: e841 2300 strex r3, r2, [r1] 8012710: 67bb str r3, [r7, #120] @ 0x78 return(result); 8012712: 6fbb ldr r3, [r7, #120] @ 0x78 8012714: 2b00 cmp r3, #0 8012716: d1e1 bne.n 80126dc /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8012718: 687b ldr r3, [r7, #4] 801271a: 681b ldr r3, [r3, #0] 801271c: 3314 adds r3, #20 801271e: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012720: 6e3b ldr r3, [r7, #96] @ 0x60 8012722: e853 3f00 ldrex r3, [r3] 8012726: 65fb str r3, [r7, #92] @ 0x5c return(result); 8012728: 6dfb ldr r3, [r7, #92] @ 0x5c 801272a: f023 0340 bic.w r3, r3, #64 @ 0x40 801272e: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8012732: 687b ldr r3, [r7, #4] 8012734: 681b ldr r3, [r3, #0] 8012736: 3314 adds r3, #20 8012738: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 801273c: 66fa str r2, [r7, #108] @ 0x6c 801273e: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012740: 6eb9 ldr r1, [r7, #104] @ 0x68 8012742: 6efa ldr r2, [r7, #108] @ 0x6c 8012744: e841 2300 strex r3, r2, [r1] 8012748: 667b str r3, [r7, #100] @ 0x64 return(result); 801274a: 6e7b ldr r3, [r7, #100] @ 0x64 801274c: 2b00 cmp r3, #0 801274e: d1e3 bne.n 8012718 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012750: 687b ldr r3, [r7, #4] 8012752: 2220 movs r2, #32 8012754: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012758: 687b ldr r3, [r7, #4] 801275a: 2200 movs r2, #0 801275c: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801275e: 687b ldr r3, [r7, #4] 8012760: 681b ldr r3, [r3, #0] 8012762: 330c adds r3, #12 8012764: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012766: 6cfb ldr r3, [r7, #76] @ 0x4c 8012768: e853 3f00 ldrex r3, [r3] 801276c: 64bb str r3, [r7, #72] @ 0x48 return(result); 801276e: 6cbb ldr r3, [r7, #72] @ 0x48 8012770: f023 0310 bic.w r3, r3, #16 8012774: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8012778: 687b ldr r3, [r7, #4] 801277a: 681b ldr r3, [r3, #0] 801277c: 330c adds r3, #12 801277e: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 8012782: 65ba str r2, [r7, #88] @ 0x58 8012784: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012786: 6d79 ldr r1, [r7, #84] @ 0x54 8012788: 6dba ldr r2, [r7, #88] @ 0x58 801278a: e841 2300 strex r3, r2, [r1] 801278e: 653b str r3, [r7, #80] @ 0x50 return(result); 8012790: 6d3b ldr r3, [r7, #80] @ 0x50 8012792: 2b00 cmp r3, #0 8012794: d1e3 bne.n 801275e /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8012796: 687b ldr r3, [r7, #4] 8012798: 6bdb ldr r3, [r3, #60] @ 0x3c 801279a: 4618 mov r0, r3 801279c: f7fc ff1b bl 800f5d6 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 80127a0: 687b ldr r3, [r7, #4] 80127a2: 2202 movs r2, #2 80127a4: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 80127a6: 687b ldr r3, [r7, #4] 80127a8: 8d9a ldrh r2, [r3, #44] @ 0x2c 80127aa: 687b ldr r3, [r7, #4] 80127ac: 8ddb ldrh r3, [r3, #46] @ 0x2e 80127ae: b29b uxth r3, r3 80127b0: 1ad3 subs r3, r2, r3 80127b2: b29b uxth r3, r3 80127b4: 4619 mov r1, r3 80127b6: 6878 ldr r0, [r7, #4] 80127b8: f7f9 ffe0 bl 800c77c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 80127bc: e09c b.n 80128f8 80127be: bf00 nop 80127c0: 08012b5d .word 0x08012b5d else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 80127c4: 687b ldr r3, [r7, #4] 80127c6: 8d9a ldrh r2, [r3, #44] @ 0x2c 80127c8: 687b ldr r3, [r7, #4] 80127ca: 8ddb ldrh r3, [r3, #46] @ 0x2e 80127cc: b29b uxth r3, r3 80127ce: 1ad3 subs r3, r2, r3 80127d0: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 80127d4: 687b ldr r3, [r7, #4] 80127d6: 8ddb ldrh r3, [r3, #46] @ 0x2e 80127d8: b29b uxth r3, r3 80127da: 2b00 cmp r3, #0 80127dc: f000 808e beq.w 80128fc && (nb_rx_data > 0U)) 80127e0: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 80127e4: 2b00 cmp r3, #0 80127e6: f000 8089 beq.w 80128fc { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 80127ea: 687b ldr r3, [r7, #4] 80127ec: 681b ldr r3, [r3, #0] 80127ee: 330c adds r3, #12 80127f0: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80127f2: 6bbb ldr r3, [r7, #56] @ 0x38 80127f4: e853 3f00 ldrex r3, [r3] 80127f8: 637b str r3, [r7, #52] @ 0x34 return(result); 80127fa: 6b7b ldr r3, [r7, #52] @ 0x34 80127fc: f423 7390 bic.w r3, r3, #288 @ 0x120 8012800: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8012804: 687b ldr r3, [r7, #4] 8012806: 681b ldr r3, [r3, #0] 8012808: 330c adds r3, #12 801280a: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 801280e: 647a str r2, [r7, #68] @ 0x44 8012810: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012812: 6c39 ldr r1, [r7, #64] @ 0x40 8012814: 6c7a ldr r2, [r7, #68] @ 0x44 8012816: e841 2300 strex r3, r2, [r1] 801281a: 63fb str r3, [r7, #60] @ 0x3c return(result); 801281c: 6bfb ldr r3, [r7, #60] @ 0x3c 801281e: 2b00 cmp r3, #0 8012820: d1e3 bne.n 80127ea /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012822: 687b ldr r3, [r7, #4] 8012824: 681b ldr r3, [r3, #0] 8012826: 3314 adds r3, #20 8012828: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801282a: 6a7b ldr r3, [r7, #36] @ 0x24 801282c: e853 3f00 ldrex r3, [r3] 8012830: 623b str r3, [r7, #32] return(result); 8012832: 6a3b ldr r3, [r7, #32] 8012834: f023 0301 bic.w r3, r3, #1 8012838: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 801283c: 687b ldr r3, [r7, #4] 801283e: 681b ldr r3, [r3, #0] 8012840: 3314 adds r3, #20 8012842: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8012846: 633a str r2, [r7, #48] @ 0x30 8012848: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801284a: 6af9 ldr r1, [r7, #44] @ 0x2c 801284c: 6b3a ldr r2, [r7, #48] @ 0x30 801284e: e841 2300 strex r3, r2, [r1] 8012852: 62bb str r3, [r7, #40] @ 0x28 return(result); 8012854: 6abb ldr r3, [r7, #40] @ 0x28 8012856: 2b00 cmp r3, #0 8012858: d1e3 bne.n 8012822 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 801285a: 687b ldr r3, [r7, #4] 801285c: 2220 movs r2, #32 801285e: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012862: 687b ldr r3, [r7, #4] 8012864: 2200 movs r2, #0 8012866: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012868: 687b ldr r3, [r7, #4] 801286a: 681b ldr r3, [r3, #0] 801286c: 330c adds r3, #12 801286e: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012870: 693b ldr r3, [r7, #16] 8012872: e853 3f00 ldrex r3, [r3] 8012876: 60fb str r3, [r7, #12] return(result); 8012878: 68fb ldr r3, [r7, #12] 801287a: f023 0310 bic.w r3, r3, #16 801287e: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8012882: 687b ldr r3, [r7, #4] 8012884: 681b ldr r3, [r3, #0] 8012886: 330c adds r3, #12 8012888: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 801288c: 61fa str r2, [r7, #28] 801288e: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012890: 69b9 ldr r1, [r7, #24] 8012892: 69fa ldr r2, [r7, #28] 8012894: e841 2300 strex r3, r2, [r1] 8012898: 617b str r3, [r7, #20] return(result); 801289a: 697b ldr r3, [r7, #20] 801289c: 2b00 cmp r3, #0 801289e: d1e3 bne.n 8012868 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 80128a0: 687b ldr r3, [r7, #4] 80128a2: 2202 movs r2, #2 80128a4: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 80128a6: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 80128aa: 4619 mov r1, r3 80128ac: 6878 ldr r0, [r7, #4] 80128ae: f7f9 ff65 bl 800c77c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 80128b2: e023 b.n 80128fc } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 80128b4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80128b8: f003 0380 and.w r3, r3, #128 @ 0x80 80128bc: 2b00 cmp r3, #0 80128be: d009 beq.n 80128d4 80128c0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80128c4: f003 0380 and.w r3, r3, #128 @ 0x80 80128c8: 2b00 cmp r3, #0 80128ca: d003 beq.n 80128d4 { UART_Transmit_IT(huart); 80128cc: 6878 ldr r0, [r7, #4] 80128ce: f000 f9b9 bl 8012c44 return; 80128d2: e014 b.n 80128fe } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 80128d4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80128d8: f003 0340 and.w r3, r3, #64 @ 0x40 80128dc: 2b00 cmp r3, #0 80128de: d00e beq.n 80128fe 80128e0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80128e4: f003 0340 and.w r3, r3, #64 @ 0x40 80128e8: 2b00 cmp r3, #0 80128ea: d008 beq.n 80128fe { UART_EndTransmit_IT(huart); 80128ec: 6878 ldr r0, [r7, #4] 80128ee: f000 f9f8 bl 8012ce2 return; 80128f2: e004 b.n 80128fe return; 80128f4: bf00 nop 80128f6: e002 b.n 80128fe return; 80128f8: bf00 nop 80128fa: e000 b.n 80128fe return; 80128fc: bf00 nop } } 80128fe: 37e8 adds r7, #232 @ 0xe8 8012900: 46bd mov sp, r7 8012902: bd80 pop {r7, pc} 08012904 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8012904: b480 push {r7} 8012906: b083 sub sp, #12 8012908: af00 add r7, sp, #0 801290a: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback could be implemented in the user file */ } 801290c: bf00 nop 801290e: 370c adds r7, #12 8012910: 46bd mov sp, r7 8012912: bc80 pop {r7} 8012914: 4770 bx lr 08012916 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8012916: b480 push {r7} 8012918: b083 sub sp, #12 801291a: af00 add r7, sp, #0 801291c: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback could be implemented in the user file */ } 801291e: bf00 nop 8012920: 370c adds r7, #12 8012922: 46bd mov sp, r7 8012924: bc80 pop {r7} 8012926: 4770 bx lr 08012928 : * @brief UART Abort Complete callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) { 8012928: b480 push {r7} 801292a: b083 sub sp, #12 801292c: af00 add r7, sp, #0 801292e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_AbortCpltCallback can be implemented in the user file. */ } 8012930: bf00 nop 8012932: 370c adds r7, #12 8012934: 46bd mov sp, r7 8012936: bc80 pop {r7} 8012938: 4770 bx lr 0801293a : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL state */ HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) { 801293a: b480 push {r7} 801293c: b085 sub sp, #20 801293e: af00 add r7, sp, #0 8012940: 6078 str r0, [r7, #4] uint32_t temp1 = 0x00U, temp2 = 0x00U; 8012942: 2300 movs r3, #0 8012944: 60fb str r3, [r7, #12] 8012946: 2300 movs r3, #0 8012948: 60bb str r3, [r7, #8] temp1 = huart->gState; 801294a: 687b ldr r3, [r7, #4] 801294c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8012950: b2db uxtb r3, r3 8012952: 60fb str r3, [r7, #12] temp2 = huart->RxState; 8012954: 687b ldr r3, [r7, #4] 8012956: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 801295a: b2db uxtb r3, r3 801295c: 60bb str r3, [r7, #8] return (HAL_UART_StateTypeDef)(temp1 | temp2); 801295e: 68fb ldr r3, [r7, #12] 8012960: b2da uxtb r2, r3 8012962: 68bb ldr r3, [r7, #8] 8012964: b2db uxtb r3, r3 8012966: 4313 orrs r3, r2 8012968: b2db uxtb r3, r3 } 801296a: 4618 mov r0, r3 801296c: 3714 adds r7, #20 801296e: 46bd mov sp, r7 8012970: bc80 pop {r7} 8012972: 4770 bx lr 08012974 : * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8012974: b580 push {r7, lr} 8012976: b086 sub sp, #24 8012978: af00 add r7, sp, #0 801297a: 60f8 str r0, [r7, #12] 801297c: 60b9 str r1, [r7, #8] 801297e: 603b str r3, [r7, #0] 8012980: 4613 mov r3, r2 8012982: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8012984: e03b b.n 80129fe { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8012986: 6a3b ldr r3, [r7, #32] 8012988: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801298c: d037 beq.n 80129fe { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 801298e: f7fb f8ef bl 800db70 8012992: 4602 mov r2, r0 8012994: 683b ldr r3, [r7, #0] 8012996: 1ad3 subs r3, r2, r3 8012998: 6a3a ldr r2, [r7, #32] 801299a: 429a cmp r2, r3 801299c: d302 bcc.n 80129a4 801299e: 6a3b ldr r3, [r7, #32] 80129a0: 2b00 cmp r3, #0 80129a2: d101 bne.n 80129a8 { return HAL_TIMEOUT; 80129a4: 2303 movs r3, #3 80129a6: e03a b.n 8012a1e } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 80129a8: 68fb ldr r3, [r7, #12] 80129aa: 681b ldr r3, [r3, #0] 80129ac: 68db ldr r3, [r3, #12] 80129ae: f003 0304 and.w r3, r3, #4 80129b2: 2b00 cmp r3, #0 80129b4: d023 beq.n 80129fe 80129b6: 68bb ldr r3, [r7, #8] 80129b8: 2b80 cmp r3, #128 @ 0x80 80129ba: d020 beq.n 80129fe 80129bc: 68bb ldr r3, [r7, #8] 80129be: 2b40 cmp r3, #64 @ 0x40 80129c0: d01d beq.n 80129fe { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 80129c2: 68fb ldr r3, [r7, #12] 80129c4: 681b ldr r3, [r3, #0] 80129c6: 681b ldr r3, [r3, #0] 80129c8: f003 0308 and.w r3, r3, #8 80129cc: 2b08 cmp r3, #8 80129ce: d116 bne.n 80129fe { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_OREFLAG(huart); 80129d0: 2300 movs r3, #0 80129d2: 617b str r3, [r7, #20] 80129d4: 68fb ldr r3, [r7, #12] 80129d6: 681b ldr r3, [r3, #0] 80129d8: 681b ldr r3, [r3, #0] 80129da: 617b str r3, [r7, #20] 80129dc: 68fb ldr r3, [r7, #12] 80129de: 681b ldr r3, [r3, #0] 80129e0: 685b ldr r3, [r3, #4] 80129e2: 617b str r3, [r7, #20] 80129e4: 697b ldr r3, [r7, #20] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 80129e6: 68f8 ldr r0, [r7, #12] 80129e8: f000 f856 bl 8012a98 huart->ErrorCode = HAL_UART_ERROR_ORE; 80129ec: 68fb ldr r3, [r7, #12] 80129ee: 2208 movs r2, #8 80129f0: 645a str r2, [r3, #68] @ 0x44 /* Process Unlocked */ __HAL_UNLOCK(huart); 80129f2: 68fb ldr r3, [r7, #12] 80129f4: 2200 movs r2, #0 80129f6: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_ERROR; 80129fa: 2301 movs r3, #1 80129fc: e00f b.n 8012a1e while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 80129fe: 68fb ldr r3, [r7, #12] 8012a00: 681b ldr r3, [r3, #0] 8012a02: 681a ldr r2, [r3, #0] 8012a04: 68bb ldr r3, [r7, #8] 8012a06: 4013 ands r3, r2 8012a08: 68ba ldr r2, [r7, #8] 8012a0a: 429a cmp r2, r3 8012a0c: bf0c ite eq 8012a0e: 2301 moveq r3, #1 8012a10: 2300 movne r3, #0 8012a12: b2db uxtb r3, r3 8012a14: 461a mov r2, r3 8012a16: 79fb ldrb r3, [r7, #7] 8012a18: 429a cmp r2, r3 8012a1a: d0b4 beq.n 8012986 } } } } return HAL_OK; 8012a1c: 2300 movs r3, #0 } 8012a1e: 4618 mov r0, r3 8012a20: 3718 adds r7, #24 8012a22: 46bd mov sp, r7 8012a24: bd80 pop {r7, pc} 08012a26 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8012a26: b480 push {r7} 8012a28: b085 sub sp, #20 8012a2a: af00 add r7, sp, #0 8012a2c: 60f8 str r0, [r7, #12] 8012a2e: 60b9 str r1, [r7, #8] 8012a30: 4613 mov r3, r2 8012a32: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 8012a34: 68fb ldr r3, [r7, #12] 8012a36: 68ba ldr r2, [r7, #8] 8012a38: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 8012a3a: 68fb ldr r3, [r7, #12] 8012a3c: 88fa ldrh r2, [r7, #6] 8012a3e: 859a strh r2, [r3, #44] @ 0x2c huart->RxXferCount = Size; 8012a40: 68fb ldr r3, [r7, #12] 8012a42: 88fa ldrh r2, [r7, #6] 8012a44: 85da strh r2, [r3, #46] @ 0x2e huart->ErrorCode = HAL_UART_ERROR_NONE; 8012a46: 68fb ldr r3, [r7, #12] 8012a48: 2200 movs r2, #0 8012a4a: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 8012a4c: 68fb ldr r3, [r7, #12] 8012a4e: 2222 movs r2, #34 @ 0x22 8012a50: f883 2042 strb.w r2, [r3, #66] @ 0x42 if (huart->Init.Parity != UART_PARITY_NONE) 8012a54: 68fb ldr r3, [r7, #12] 8012a56: 691b ldr r3, [r3, #16] 8012a58: 2b00 cmp r3, #0 8012a5a: d007 beq.n 8012a6c { /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); 8012a5c: 68fb ldr r3, [r7, #12] 8012a5e: 681b ldr r3, [r3, #0] 8012a60: 68da ldr r2, [r3, #12] 8012a62: 68fb ldr r3, [r7, #12] 8012a64: 681b ldr r3, [r3, #0] 8012a66: f442 7280 orr.w r2, r2, #256 @ 0x100 8012a6a: 60da str r2, [r3, #12] } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); 8012a6c: 68fb ldr r3, [r7, #12] 8012a6e: 681b ldr r3, [r3, #0] 8012a70: 695a ldr r2, [r3, #20] 8012a72: 68fb ldr r3, [r7, #12] 8012a74: 681b ldr r3, [r3, #0] 8012a76: f042 0201 orr.w r2, r2, #1 8012a7a: 615a str r2, [r3, #20] /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); 8012a7c: 68fb ldr r3, [r7, #12] 8012a7e: 681b ldr r3, [r3, #0] 8012a80: 68da ldr r2, [r3, #12] 8012a82: 68fb ldr r3, [r7, #12] 8012a84: 681b ldr r3, [r3, #0] 8012a86: f042 0220 orr.w r2, r2, #32 8012a8a: 60da str r2, [r3, #12] return HAL_OK; 8012a8c: 2300 movs r3, #0 } 8012a8e: 4618 mov r0, r3 8012a90: 3714 adds r7, #20 8012a92: 46bd mov sp, r7 8012a94: bc80 pop {r7} 8012a96: 4770 bx lr 08012a98 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8012a98: b480 push {r7} 8012a9a: b095 sub sp, #84 @ 0x54 8012a9c: af00 add r7, sp, #0 8012a9e: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8012aa0: 687b ldr r3, [r7, #4] 8012aa2: 681b ldr r3, [r3, #0] 8012aa4: 330c adds r3, #12 8012aa6: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012aa8: 6b7b ldr r3, [r7, #52] @ 0x34 8012aaa: e853 3f00 ldrex r3, [r3] 8012aae: 633b str r3, [r7, #48] @ 0x30 return(result); 8012ab0: 6b3b ldr r3, [r7, #48] @ 0x30 8012ab2: f423 7390 bic.w r3, r3, #288 @ 0x120 8012ab6: 64fb str r3, [r7, #76] @ 0x4c 8012ab8: 687b ldr r3, [r7, #4] 8012aba: 681b ldr r3, [r3, #0] 8012abc: 330c adds r3, #12 8012abe: 6cfa ldr r2, [r7, #76] @ 0x4c 8012ac0: 643a str r2, [r7, #64] @ 0x40 8012ac2: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012ac4: 6bf9 ldr r1, [r7, #60] @ 0x3c 8012ac6: 6c3a ldr r2, [r7, #64] @ 0x40 8012ac8: e841 2300 strex r3, r2, [r1] 8012acc: 63bb str r3, [r7, #56] @ 0x38 return(result); 8012ace: 6bbb ldr r3, [r7, #56] @ 0x38 8012ad0: 2b00 cmp r3, #0 8012ad2: d1e5 bne.n 8012aa0 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012ad4: 687b ldr r3, [r7, #4] 8012ad6: 681b ldr r3, [r3, #0] 8012ad8: 3314 adds r3, #20 8012ada: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012adc: 6a3b ldr r3, [r7, #32] 8012ade: e853 3f00 ldrex r3, [r3] 8012ae2: 61fb str r3, [r7, #28] return(result); 8012ae4: 69fb ldr r3, [r7, #28] 8012ae6: f023 0301 bic.w r3, r3, #1 8012aea: 64bb str r3, [r7, #72] @ 0x48 8012aec: 687b ldr r3, [r7, #4] 8012aee: 681b ldr r3, [r3, #0] 8012af0: 3314 adds r3, #20 8012af2: 6cba ldr r2, [r7, #72] @ 0x48 8012af4: 62fa str r2, [r7, #44] @ 0x2c 8012af6: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012af8: 6ab9 ldr r1, [r7, #40] @ 0x28 8012afa: 6afa ldr r2, [r7, #44] @ 0x2c 8012afc: e841 2300 strex r3, r2, [r1] 8012b00: 627b str r3, [r7, #36] @ 0x24 return(result); 8012b02: 6a7b ldr r3, [r7, #36] @ 0x24 8012b04: 2b00 cmp r3, #0 8012b06: d1e5 bne.n 8012ad4 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012b08: 687b ldr r3, [r7, #4] 8012b0a: 6b1b ldr r3, [r3, #48] @ 0x30 8012b0c: 2b01 cmp r3, #1 8012b0e: d119 bne.n 8012b44 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012b10: 687b ldr r3, [r7, #4] 8012b12: 681b ldr r3, [r3, #0] 8012b14: 330c adds r3, #12 8012b16: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012b18: 68fb ldr r3, [r7, #12] 8012b1a: e853 3f00 ldrex r3, [r3] 8012b1e: 60bb str r3, [r7, #8] return(result); 8012b20: 68bb ldr r3, [r7, #8] 8012b22: f023 0310 bic.w r3, r3, #16 8012b26: 647b str r3, [r7, #68] @ 0x44 8012b28: 687b ldr r3, [r7, #4] 8012b2a: 681b ldr r3, [r3, #0] 8012b2c: 330c adds r3, #12 8012b2e: 6c7a ldr r2, [r7, #68] @ 0x44 8012b30: 61ba str r2, [r7, #24] 8012b32: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012b34: 6979 ldr r1, [r7, #20] 8012b36: 69ba ldr r2, [r7, #24] 8012b38: e841 2300 strex r3, r2, [r1] 8012b3c: 613b str r3, [r7, #16] return(result); 8012b3e: 693b ldr r3, [r7, #16] 8012b40: 2b00 cmp r3, #0 8012b42: d1e5 bne.n 8012b10 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012b44: 687b ldr r3, [r7, #4] 8012b46: 2220 movs r2, #32 8012b48: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012b4c: 687b ldr r3, [r7, #4] 8012b4e: 2200 movs r2, #0 8012b50: 631a str r2, [r3, #48] @ 0x30 } 8012b52: bf00 nop 8012b54: 3754 adds r7, #84 @ 0x54 8012b56: 46bd mov sp, r7 8012b58: bc80 pop {r7} 8012b5a: 4770 bx lr 08012b5c : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8012b5c: b580 push {r7, lr} 8012b5e: b084 sub sp, #16 8012b60: af00 add r7, sp, #0 8012b62: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8012b64: 687b ldr r3, [r7, #4] 8012b66: 6a5b ldr r3, [r3, #36] @ 0x24 8012b68: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8012b6a: 68fb ldr r3, [r7, #12] 8012b6c: 2200 movs r2, #0 8012b6e: 85da strh r2, [r3, #46] @ 0x2e huart->TxXferCount = 0x00U; 8012b70: 68fb ldr r3, [r7, #12] 8012b72: 2200 movs r2, #0 8012b74: 84da strh r2, [r3, #38] @ 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8012b76: 68f8 ldr r0, [r7, #12] 8012b78: f7ff fecd bl 8012916 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8012b7c: bf00 nop 8012b7e: 3710 adds r7, #16 8012b80: 46bd mov sp, r7 8012b82: bd80 pop {r7, pc} 08012b84 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { 8012b84: b580 push {r7, lr} 8012b86: b084 sub sp, #16 8012b88: af00 add r7, sp, #0 8012b8a: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8012b8c: 687b ldr r3, [r7, #4] 8012b8e: 6a5b ldr r3, [r3, #36] @ 0x24 8012b90: 60fb str r3, [r7, #12] huart->hdmatx->XferAbortCallback = NULL; 8012b92: 68fb ldr r3, [r7, #12] 8012b94: 6b9b ldr r3, [r3, #56] @ 0x38 8012b96: 2200 movs r2, #0 8012b98: 635a str r2, [r3, #52] @ 0x34 /* Check if an Abort process is still ongoing */ if (huart->hdmarx != NULL) 8012b9a: 68fb ldr r3, [r7, #12] 8012b9c: 6bdb ldr r3, [r3, #60] @ 0x3c 8012b9e: 2b00 cmp r3, #0 8012ba0: d004 beq.n 8012bac { if (huart->hdmarx->XferAbortCallback != NULL) 8012ba2: 68fb ldr r3, [r7, #12] 8012ba4: 6bdb ldr r3, [r3, #60] @ 0x3c 8012ba6: 6b5b ldr r3, [r3, #52] @ 0x34 8012ba8: 2b00 cmp r3, #0 8012baa: d117 bne.n 8012bdc return; } } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ huart->TxXferCount = 0x00U; 8012bac: 68fb ldr r3, [r7, #12] 8012bae: 2200 movs r2, #0 8012bb0: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 8012bb2: 68fb ldr r3, [r7, #12] 8012bb4: 2200 movs r2, #0 8012bb6: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012bb8: 68fb ldr r3, [r7, #12] 8012bba: 2200 movs r2, #0 8012bbc: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 8012bbe: 68fb ldr r3, [r7, #12] 8012bc0: 2220 movs r2, #32 8012bc2: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8012bc6: 68fb ldr r3, [r7, #12] 8012bc8: 2220 movs r2, #32 8012bca: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012bce: 68fb ldr r3, [r7, #12] 8012bd0: 2200 movs r2, #0 8012bd2: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 8012bd4: 68f8 ldr r0, [r7, #12] 8012bd6: f7ff fea7 bl 8012928 8012bda: e000 b.n 8012bde return; 8012bdc: bf00 nop #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8012bde: 3710 adds r7, #16 8012be0: 46bd mov sp, r7 8012be2: bd80 pop {r7, pc} 08012be4 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { 8012be4: b580 push {r7, lr} 8012be6: b084 sub sp, #16 8012be8: af00 add r7, sp, #0 8012bea: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8012bec: 687b ldr r3, [r7, #4] 8012bee: 6a5b ldr r3, [r3, #36] @ 0x24 8012bf0: 60fb str r3, [r7, #12] huart->hdmarx->XferAbortCallback = NULL; 8012bf2: 68fb ldr r3, [r7, #12] 8012bf4: 6bdb ldr r3, [r3, #60] @ 0x3c 8012bf6: 2200 movs r2, #0 8012bf8: 635a str r2, [r3, #52] @ 0x34 /* Check if an Abort process is still ongoing */ if (huart->hdmatx != NULL) 8012bfa: 68fb ldr r3, [r7, #12] 8012bfc: 6b9b ldr r3, [r3, #56] @ 0x38 8012bfe: 2b00 cmp r3, #0 8012c00: d004 beq.n 8012c0c { if (huart->hdmatx->XferAbortCallback != NULL) 8012c02: 68fb ldr r3, [r7, #12] 8012c04: 6b9b ldr r3, [r3, #56] @ 0x38 8012c06: 6b5b ldr r3, [r3, #52] @ 0x34 8012c08: 2b00 cmp r3, #0 8012c0a: d117 bne.n 8012c3c return; } } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ huart->TxXferCount = 0x00U; 8012c0c: 68fb ldr r3, [r7, #12] 8012c0e: 2200 movs r2, #0 8012c10: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 8012c12: 68fb ldr r3, [r7, #12] 8012c14: 2200 movs r2, #0 8012c16: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012c18: 68fb ldr r3, [r7, #12] 8012c1a: 2200 movs r2, #0 8012c1c: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 8012c1e: 68fb ldr r3, [r7, #12] 8012c20: 2220 movs r2, #32 8012c22: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8012c26: 68fb ldr r3, [r7, #12] 8012c28: 2220 movs r2, #32 8012c2a: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012c2e: 68fb ldr r3, [r7, #12] 8012c30: 2200 movs r2, #0 8012c32: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 8012c34: 68f8 ldr r0, [r7, #12] 8012c36: f7ff fe77 bl 8012928 8012c3a: e000 b.n 8012c3e return; 8012c3c: bf00 nop #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8012c3e: 3710 adds r7, #16 8012c40: 46bd mov sp, r7 8012c42: bd80 pop {r7, pc} 08012c44 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 8012c44: b480 push {r7} 8012c46: b085 sub sp, #20 8012c48: af00 add r7, sp, #0 8012c4a: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8012c4c: 687b ldr r3, [r7, #4] 8012c4e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8012c52: b2db uxtb r3, r3 8012c54: 2b21 cmp r3, #33 @ 0x21 8012c56: d13e bne.n 8012cd6 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012c58: 687b ldr r3, [r7, #4] 8012c5a: 689b ldr r3, [r3, #8] 8012c5c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012c60: d114 bne.n 8012c8c 8012c62: 687b ldr r3, [r7, #4] 8012c64: 691b ldr r3, [r3, #16] 8012c66: 2b00 cmp r3, #0 8012c68: d110 bne.n 8012c8c { tmp = (const uint16_t *) huart->pTxBuffPtr; 8012c6a: 687b ldr r3, [r7, #4] 8012c6c: 6a1b ldr r3, [r3, #32] 8012c6e: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8012c70: 68fb ldr r3, [r7, #12] 8012c72: 881b ldrh r3, [r3, #0] 8012c74: 461a mov r2, r3 8012c76: 687b ldr r3, [r7, #4] 8012c78: 681b ldr r3, [r3, #0] 8012c7a: f3c2 0208 ubfx r2, r2, #0, #9 8012c7e: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 8012c80: 687b ldr r3, [r7, #4] 8012c82: 6a1b ldr r3, [r3, #32] 8012c84: 1c9a adds r2, r3, #2 8012c86: 687b ldr r3, [r7, #4] 8012c88: 621a str r2, [r3, #32] 8012c8a: e008 b.n 8012c9e } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 8012c8c: 687b ldr r3, [r7, #4] 8012c8e: 6a1b ldr r3, [r3, #32] 8012c90: 1c59 adds r1, r3, #1 8012c92: 687a ldr r2, [r7, #4] 8012c94: 6211 str r1, [r2, #32] 8012c96: 781a ldrb r2, [r3, #0] 8012c98: 687b ldr r3, [r7, #4] 8012c9a: 681b ldr r3, [r3, #0] 8012c9c: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 8012c9e: 687b ldr r3, [r7, #4] 8012ca0: 8cdb ldrh r3, [r3, #38] @ 0x26 8012ca2: b29b uxth r3, r3 8012ca4: 3b01 subs r3, #1 8012ca6: b29b uxth r3, r3 8012ca8: 687a ldr r2, [r7, #4] 8012caa: 4619 mov r1, r3 8012cac: 84d1 strh r1, [r2, #38] @ 0x26 8012cae: 2b00 cmp r3, #0 8012cb0: d10f bne.n 8012cd2 { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8012cb2: 687b ldr r3, [r7, #4] 8012cb4: 681b ldr r3, [r3, #0] 8012cb6: 68da ldr r2, [r3, #12] 8012cb8: 687b ldr r3, [r7, #4] 8012cba: 681b ldr r3, [r3, #0] 8012cbc: f022 0280 bic.w r2, r2, #128 @ 0x80 8012cc0: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8012cc2: 687b ldr r3, [r7, #4] 8012cc4: 681b ldr r3, [r3, #0] 8012cc6: 68da ldr r2, [r3, #12] 8012cc8: 687b ldr r3, [r7, #4] 8012cca: 681b ldr r3, [r3, #0] 8012ccc: f042 0240 orr.w r2, r2, #64 @ 0x40 8012cd0: 60da str r2, [r3, #12] } return HAL_OK; 8012cd2: 2300 movs r3, #0 8012cd4: e000 b.n 8012cd8 } else { return HAL_BUSY; 8012cd6: 2302 movs r3, #2 } } 8012cd8: 4618 mov r0, r3 8012cda: 3714 adds r7, #20 8012cdc: 46bd mov sp, r7 8012cde: bc80 pop {r7} 8012ce0: 4770 bx lr 08012ce2 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8012ce2: b580 push {r7, lr} 8012ce4: b082 sub sp, #8 8012ce6: af00 add r7, sp, #0 8012ce8: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 8012cea: 687b ldr r3, [r7, #4] 8012cec: 681b ldr r3, [r3, #0] 8012cee: 68da ldr r2, [r3, #12] 8012cf0: 687b ldr r3, [r7, #4] 8012cf2: 681b ldr r3, [r3, #0] 8012cf4: f022 0240 bic.w r2, r2, #64 @ 0x40 8012cf8: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8012cfa: 687b ldr r3, [r7, #4] 8012cfc: 2220 movs r2, #32 8012cfe: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8012d02: 6878 ldr r0, [r7, #4] 8012d04: f7f9 fd9a bl 800c83c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8012d08: 2300 movs r3, #0 } 8012d0a: 4618 mov r0, r3 8012d0c: 3708 adds r7, #8 8012d0e: 46bd mov sp, r7 8012d10: bd80 pop {r7, pc} 08012d12 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 8012d12: b580 push {r7, lr} 8012d14: b08c sub sp, #48 @ 0x30 8012d16: af00 add r7, sp, #0 8012d18: 6078 str r0, [r7, #4] uint8_t *pdata8bits; uint16_t *pdata16bits; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8012d1a: 687b ldr r3, [r7, #4] 8012d1c: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8012d20: b2db uxtb r3, r3 8012d22: 2b22 cmp r3, #34 @ 0x22 8012d24: f040 80ae bne.w 8012e84 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012d28: 687b ldr r3, [r7, #4] 8012d2a: 689b ldr r3, [r3, #8] 8012d2c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012d30: d117 bne.n 8012d62 8012d32: 687b ldr r3, [r7, #4] 8012d34: 691b ldr r3, [r3, #16] 8012d36: 2b00 cmp r3, #0 8012d38: d113 bne.n 8012d62 { pdata8bits = NULL; 8012d3a: 2300 movs r3, #0 8012d3c: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = (uint16_t *) huart->pRxBuffPtr; 8012d3e: 687b ldr r3, [r7, #4] 8012d40: 6a9b ldr r3, [r3, #40] @ 0x28 8012d42: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8012d44: 687b ldr r3, [r7, #4] 8012d46: 681b ldr r3, [r3, #0] 8012d48: 685b ldr r3, [r3, #4] 8012d4a: b29b uxth r3, r3 8012d4c: f3c3 0308 ubfx r3, r3, #0, #9 8012d50: b29a uxth r2, r3 8012d52: 6abb ldr r3, [r7, #40] @ 0x28 8012d54: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8012d56: 687b ldr r3, [r7, #4] 8012d58: 6a9b ldr r3, [r3, #40] @ 0x28 8012d5a: 1c9a adds r2, r3, #2 8012d5c: 687b ldr r3, [r7, #4] 8012d5e: 629a str r2, [r3, #40] @ 0x28 8012d60: e026 b.n 8012db0 } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8012d62: 687b ldr r3, [r7, #4] 8012d64: 6a9b ldr r3, [r3, #40] @ 0x28 8012d66: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = NULL; 8012d68: 2300 movs r3, #0 8012d6a: 62bb str r3, [r7, #40] @ 0x28 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 8012d6c: 687b ldr r3, [r7, #4] 8012d6e: 689b ldr r3, [r3, #8] 8012d70: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012d74: d007 beq.n 8012d86 8012d76: 687b ldr r3, [r7, #4] 8012d78: 689b ldr r3, [r3, #8] 8012d7a: 2b00 cmp r3, #0 8012d7c: d10a bne.n 8012d94 8012d7e: 687b ldr r3, [r7, #4] 8012d80: 691b ldr r3, [r3, #16] 8012d82: 2b00 cmp r3, #0 8012d84: d106 bne.n 8012d94 { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8012d86: 687b ldr r3, [r7, #4] 8012d88: 681b ldr r3, [r3, #0] 8012d8a: 685b ldr r3, [r3, #4] 8012d8c: b2da uxtb r2, r3 8012d8e: 6afb ldr r3, [r7, #44] @ 0x2c 8012d90: 701a strb r2, [r3, #0] 8012d92: e008 b.n 8012da6 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8012d94: 687b ldr r3, [r7, #4] 8012d96: 681b ldr r3, [r3, #0] 8012d98: 685b ldr r3, [r3, #4] 8012d9a: b2db uxtb r3, r3 8012d9c: f003 037f and.w r3, r3, #127 @ 0x7f 8012da0: b2da uxtb r2, r3 8012da2: 6afb ldr r3, [r7, #44] @ 0x2c 8012da4: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8012da6: 687b ldr r3, [r7, #4] 8012da8: 6a9b ldr r3, [r3, #40] @ 0x28 8012daa: 1c5a adds r2, r3, #1 8012dac: 687b ldr r3, [r7, #4] 8012dae: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 8012db0: 687b ldr r3, [r7, #4] 8012db2: 8ddb ldrh r3, [r3, #46] @ 0x2e 8012db4: b29b uxth r3, r3 8012db6: 3b01 subs r3, #1 8012db8: b29b uxth r3, r3 8012dba: 687a ldr r2, [r7, #4] 8012dbc: 4619 mov r1, r3 8012dbe: 85d1 strh r1, [r2, #46] @ 0x2e 8012dc0: 2b00 cmp r3, #0 8012dc2: d15d bne.n 8012e80 { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8012dc4: 687b ldr r3, [r7, #4] 8012dc6: 681b ldr r3, [r3, #0] 8012dc8: 68da ldr r2, [r3, #12] 8012dca: 687b ldr r3, [r7, #4] 8012dcc: 681b ldr r3, [r3, #0] 8012dce: f022 0220 bic.w r2, r2, #32 8012dd2: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8012dd4: 687b ldr r3, [r7, #4] 8012dd6: 681b ldr r3, [r3, #0] 8012dd8: 68da ldr r2, [r3, #12] 8012dda: 687b ldr r3, [r7, #4] 8012ddc: 681b ldr r3, [r3, #0] 8012dde: f422 7280 bic.w r2, r2, #256 @ 0x100 8012de2: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8012de4: 687b ldr r3, [r7, #4] 8012de6: 681b ldr r3, [r3, #0] 8012de8: 695a ldr r2, [r3, #20] 8012dea: 687b ldr r3, [r7, #4] 8012dec: 681b ldr r3, [r3, #0] 8012dee: f022 0201 bic.w r2, r2, #1 8012df2: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012df4: 687b ldr r3, [r7, #4] 8012df6: 2220 movs r2, #32 8012df8: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8012dfc: 687b ldr r3, [r7, #4] 8012dfe: 2200 movs r2, #0 8012e00: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012e02: 687b ldr r3, [r7, #4] 8012e04: 6b1b ldr r3, [r3, #48] @ 0x30 8012e06: 2b01 cmp r3, #1 8012e08: d135 bne.n 8012e76 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012e0a: 687b ldr r3, [r7, #4] 8012e0c: 2200 movs r2, #0 8012e0e: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012e10: 687b ldr r3, [r7, #4] 8012e12: 681b ldr r3, [r3, #0] 8012e14: 330c adds r3, #12 8012e16: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012e18: 697b ldr r3, [r7, #20] 8012e1a: e853 3f00 ldrex r3, [r3] 8012e1e: 613b str r3, [r7, #16] return(result); 8012e20: 693b ldr r3, [r7, #16] 8012e22: f023 0310 bic.w r3, r3, #16 8012e26: 627b str r3, [r7, #36] @ 0x24 8012e28: 687b ldr r3, [r7, #4] 8012e2a: 681b ldr r3, [r3, #0] 8012e2c: 330c adds r3, #12 8012e2e: 6a7a ldr r2, [r7, #36] @ 0x24 8012e30: 623a str r2, [r7, #32] 8012e32: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012e34: 69f9 ldr r1, [r7, #28] 8012e36: 6a3a ldr r2, [r7, #32] 8012e38: e841 2300 strex r3, r2, [r1] 8012e3c: 61bb str r3, [r7, #24] return(result); 8012e3e: 69bb ldr r3, [r7, #24] 8012e40: 2b00 cmp r3, #0 8012e42: d1e5 bne.n 8012e10 /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 8012e44: 687b ldr r3, [r7, #4] 8012e46: 681b ldr r3, [r3, #0] 8012e48: 681b ldr r3, [r3, #0] 8012e4a: f003 0310 and.w r3, r3, #16 8012e4e: 2b10 cmp r3, #16 8012e50: d10a bne.n 8012e68 { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 8012e52: 2300 movs r3, #0 8012e54: 60fb str r3, [r7, #12] 8012e56: 687b ldr r3, [r7, #4] 8012e58: 681b ldr r3, [r3, #0] 8012e5a: 681b ldr r3, [r3, #0] 8012e5c: 60fb str r3, [r7, #12] 8012e5e: 687b ldr r3, [r7, #4] 8012e60: 681b ldr r3, [r3, #0] 8012e62: 685b ldr r3, [r3, #4] 8012e64: 60fb str r3, [r7, #12] 8012e66: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8012e68: 687b ldr r3, [r7, #4] 8012e6a: 8d9b ldrh r3, [r3, #44] @ 0x2c 8012e6c: 4619 mov r1, r3 8012e6e: 6878 ldr r0, [r7, #4] 8012e70: f7f9 fc84 bl 800c77c 8012e74: e002 b.n 8012e7c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8012e76: 6878 ldr r0, [r7, #4] 8012e78: f7ff fd44 bl 8012904 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8012e7c: 2300 movs r3, #0 8012e7e: e002 b.n 8012e86 } return HAL_OK; 8012e80: 2300 movs r3, #0 8012e82: e000 b.n 8012e86 } else { return HAL_BUSY; 8012e84: 2302 movs r3, #2 } } 8012e86: 4618 mov r0, r3 8012e88: 3730 adds r7, #48 @ 0x30 8012e8a: 46bd mov sp, r7 8012e8c: bd80 pop {r7, pc} ... 08012e90 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8012e90: b580 push {r7, lr} 8012e92: b084 sub sp, #16 8012e94: af00 add r7, sp, #0 8012e96: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8012e98: 687b ldr r3, [r7, #4] 8012e9a: 681b ldr r3, [r3, #0] 8012e9c: 691b ldr r3, [r3, #16] 8012e9e: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8012ea2: 687b ldr r3, [r7, #4] 8012ea4: 68da ldr r2, [r3, #12] 8012ea6: 687b ldr r3, [r7, #4] 8012ea8: 681b ldr r3, [r3, #0] 8012eaa: 430a orrs r2, r1 8012eac: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 8012eae: 687b ldr r3, [r7, #4] 8012eb0: 689a ldr r2, [r3, #8] 8012eb2: 687b ldr r3, [r7, #4] 8012eb4: 691b ldr r3, [r3, #16] 8012eb6: 431a orrs r2, r3 8012eb8: 687b ldr r3, [r7, #4] 8012eba: 695b ldr r3, [r3, #20] 8012ebc: 4313 orrs r3, r2 8012ebe: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 8012ec0: 687b ldr r3, [r7, #4] 8012ec2: 681b ldr r3, [r3, #0] 8012ec4: 68db ldr r3, [r3, #12] 8012ec6: f423 53b0 bic.w r3, r3, #5632 @ 0x1600 8012eca: f023 030c bic.w r3, r3, #12 8012ece: 687a ldr r2, [r7, #4] 8012ed0: 6812 ldr r2, [r2, #0] 8012ed2: 68b9 ldr r1, [r7, #8] 8012ed4: 430b orrs r3, r1 8012ed6: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8012ed8: 687b ldr r3, [r7, #4] 8012eda: 681b ldr r3, [r3, #0] 8012edc: 695b ldr r3, [r3, #20] 8012ede: f423 7140 bic.w r1, r3, #768 @ 0x300 8012ee2: 687b ldr r3, [r7, #4] 8012ee4: 699a ldr r2, [r3, #24] 8012ee6: 687b ldr r3, [r7, #4] 8012ee8: 681b ldr r3, [r3, #0] 8012eea: 430a orrs r2, r1 8012eec: 615a str r2, [r3, #20] if(huart->Instance == USART1) 8012eee: 687b ldr r3, [r7, #4] 8012ef0: 681b ldr r3, [r3, #0] 8012ef2: 4a2c ldr r2, [pc, #176] @ (8012fa4 ) 8012ef4: 4293 cmp r3, r2 8012ef6: d103 bne.n 8012f00 { pclk = HAL_RCC_GetPCLK2Freq(); 8012ef8: f7fd fc1a bl 8010730 8012efc: 60f8 str r0, [r7, #12] 8012efe: e002 b.n 8012f06 } else { pclk = HAL_RCC_GetPCLK1Freq(); 8012f00: f7fd fc02 bl 8010708 8012f04: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8012f06: 68fa ldr r2, [r7, #12] 8012f08: 4613 mov r3, r2 8012f0a: 009b lsls r3, r3, #2 8012f0c: 4413 add r3, r2 8012f0e: 009a lsls r2, r3, #2 8012f10: 441a add r2, r3 8012f12: 687b ldr r3, [r7, #4] 8012f14: 685b ldr r3, [r3, #4] 8012f16: 009b lsls r3, r3, #2 8012f18: fbb2 f3f3 udiv r3, r2, r3 8012f1c: 4a22 ldr r2, [pc, #136] @ (8012fa8 ) 8012f1e: fba2 2303 umull r2, r3, r2, r3 8012f22: 095b lsrs r3, r3, #5 8012f24: 0119 lsls r1, r3, #4 8012f26: 68fa ldr r2, [r7, #12] 8012f28: 4613 mov r3, r2 8012f2a: 009b lsls r3, r3, #2 8012f2c: 4413 add r3, r2 8012f2e: 009a lsls r2, r3, #2 8012f30: 441a add r2, r3 8012f32: 687b ldr r3, [r7, #4] 8012f34: 685b ldr r3, [r3, #4] 8012f36: 009b lsls r3, r3, #2 8012f38: fbb2 f2f3 udiv r2, r2, r3 8012f3c: 4b1a ldr r3, [pc, #104] @ (8012fa8 ) 8012f3e: fba3 0302 umull r0, r3, r3, r2 8012f42: 095b lsrs r3, r3, #5 8012f44: 2064 movs r0, #100 @ 0x64 8012f46: fb00 f303 mul.w r3, r0, r3 8012f4a: 1ad3 subs r3, r2, r3 8012f4c: 011b lsls r3, r3, #4 8012f4e: 3332 adds r3, #50 @ 0x32 8012f50: 4a15 ldr r2, [pc, #84] @ (8012fa8 ) 8012f52: fba2 2303 umull r2, r3, r2, r3 8012f56: 095b lsrs r3, r3, #5 8012f58: f003 03f0 and.w r3, r3, #240 @ 0xf0 8012f5c: 4419 add r1, r3 8012f5e: 68fa ldr r2, [r7, #12] 8012f60: 4613 mov r3, r2 8012f62: 009b lsls r3, r3, #2 8012f64: 4413 add r3, r2 8012f66: 009a lsls r2, r3, #2 8012f68: 441a add r2, r3 8012f6a: 687b ldr r3, [r7, #4] 8012f6c: 685b ldr r3, [r3, #4] 8012f6e: 009b lsls r3, r3, #2 8012f70: fbb2 f2f3 udiv r2, r2, r3 8012f74: 4b0c ldr r3, [pc, #48] @ (8012fa8 ) 8012f76: fba3 0302 umull r0, r3, r3, r2 8012f7a: 095b lsrs r3, r3, #5 8012f7c: 2064 movs r0, #100 @ 0x64 8012f7e: fb00 f303 mul.w r3, r0, r3 8012f82: 1ad3 subs r3, r2, r3 8012f84: 011b lsls r3, r3, #4 8012f86: 3332 adds r3, #50 @ 0x32 8012f88: 4a07 ldr r2, [pc, #28] @ (8012fa8 ) 8012f8a: fba2 2303 umull r2, r3, r2, r3 8012f8e: 095b lsrs r3, r3, #5 8012f90: f003 020f and.w r2, r3, #15 8012f94: 687b ldr r3, [r7, #4] 8012f96: 681b ldr r3, [r3, #0] 8012f98: 440a add r2, r1 8012f9a: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 8012f9c: bf00 nop 8012f9e: 3710 adds r7, #16 8012fa0: 46bd mov sp, r7 8012fa2: bd80 pop {r7, pc} 8012fa4: 40013800 .word 0x40013800 8012fa8: 51eb851f .word 0x51eb851f 08012fac <__cvt>: 8012fac: 2b00 cmp r3, #0 8012fae: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8012fb2: 461d mov r5, r3 8012fb4: bfbb ittet lt 8012fb6: f103 4300 addlt.w r3, r3, #2147483648 @ 0x80000000 8012fba: 461d movlt r5, r3 8012fbc: 2300 movge r3, #0 8012fbe: 232d movlt r3, #45 @ 0x2d 8012fc0: b088 sub sp, #32 8012fc2: 4614 mov r4, r2 8012fc4: bfb8 it lt 8012fc6: 4614 movlt r4, r2 8012fc8: 9a12 ldr r2, [sp, #72] @ 0x48 8012fca: 9e10 ldr r6, [sp, #64] @ 0x40 8012fcc: 7013 strb r3, [r2, #0] 8012fce: 9b14 ldr r3, [sp, #80] @ 0x50 8012fd0: f8dd a04c ldr.w sl, [sp, #76] @ 0x4c 8012fd4: f023 0820 bic.w r8, r3, #32 8012fd8: f1b8 0f46 cmp.w r8, #70 @ 0x46 8012fdc: d005 beq.n 8012fea <__cvt+0x3e> 8012fde: f1b8 0f45 cmp.w r8, #69 @ 0x45 8012fe2: d100 bne.n 8012fe6 <__cvt+0x3a> 8012fe4: 3601 adds r6, #1 8012fe6: 2302 movs r3, #2 8012fe8: e000 b.n 8012fec <__cvt+0x40> 8012fea: 2303 movs r3, #3 8012fec: aa07 add r2, sp, #28 8012fee: 9204 str r2, [sp, #16] 8012ff0: aa06 add r2, sp, #24 8012ff2: e9cd a202 strd sl, r2, [sp, #8] 8012ff6: e9cd 3600 strd r3, r6, [sp] 8012ffa: 4622 mov r2, r4 8012ffc: 462b mov r3, r5 8012ffe: f000 fe3b bl 8013c78 <_dtoa_r> 8013002: f1b8 0f47 cmp.w r8, #71 @ 0x47 8013006: 4607 mov r7, r0 8013008: d119 bne.n 801303e <__cvt+0x92> 801300a: 9b11 ldr r3, [sp, #68] @ 0x44 801300c: 07db lsls r3, r3, #31 801300e: d50e bpl.n 801302e <__cvt+0x82> 8013010: eb00 0906 add.w r9, r0, r6 8013014: 2200 movs r2, #0 8013016: 2300 movs r3, #0 8013018: 4620 mov r0, r4 801301a: 4629 mov r1, r5 801301c: f7f5 fd30 bl 8008a80 <__aeabi_dcmpeq> 8013020: b108 cbz r0, 8013026 <__cvt+0x7a> 8013022: f8cd 901c str.w r9, [sp, #28] 8013026: 2230 movs r2, #48 @ 0x30 8013028: 9b07 ldr r3, [sp, #28] 801302a: 454b cmp r3, r9 801302c: d31e bcc.n 801306c <__cvt+0xc0> 801302e: 4638 mov r0, r7 8013030: 9b07 ldr r3, [sp, #28] 8013032: 9a15 ldr r2, [sp, #84] @ 0x54 8013034: 1bdb subs r3, r3, r7 8013036: 6013 str r3, [r2, #0] 8013038: b008 add sp, #32 801303a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801303e: f1b8 0f46 cmp.w r8, #70 @ 0x46 8013042: eb00 0906 add.w r9, r0, r6 8013046: d1e5 bne.n 8013014 <__cvt+0x68> 8013048: 7803 ldrb r3, [r0, #0] 801304a: 2b30 cmp r3, #48 @ 0x30 801304c: d10a bne.n 8013064 <__cvt+0xb8> 801304e: 2200 movs r2, #0 8013050: 2300 movs r3, #0 8013052: 4620 mov r0, r4 8013054: 4629 mov r1, r5 8013056: f7f5 fd13 bl 8008a80 <__aeabi_dcmpeq> 801305a: b918 cbnz r0, 8013064 <__cvt+0xb8> 801305c: f1c6 0601 rsb r6, r6, #1 8013060: f8ca 6000 str.w r6, [sl] 8013064: f8da 3000 ldr.w r3, [sl] 8013068: 4499 add r9, r3 801306a: e7d3 b.n 8013014 <__cvt+0x68> 801306c: 1c59 adds r1, r3, #1 801306e: 9107 str r1, [sp, #28] 8013070: 701a strb r2, [r3, #0] 8013072: e7d9 b.n 8013028 <__cvt+0x7c> 08013074 <__exponent>: 8013074: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8013076: 2900 cmp r1, #0 8013078: bfb6 itet lt 801307a: 232d movlt r3, #45 @ 0x2d 801307c: 232b movge r3, #43 @ 0x2b 801307e: 4249 neglt r1, r1 8013080: 2909 cmp r1, #9 8013082: 7002 strb r2, [r0, #0] 8013084: 7043 strb r3, [r0, #1] 8013086: dd29 ble.n 80130dc <__exponent+0x68> 8013088: f10d 0307 add.w r3, sp, #7 801308c: 461d mov r5, r3 801308e: 270a movs r7, #10 8013090: fbb1 f6f7 udiv r6, r1, r7 8013094: 461a mov r2, r3 8013096: fb07 1416 mls r4, r7, r6, r1 801309a: 3430 adds r4, #48 @ 0x30 801309c: f802 4c01 strb.w r4, [r2, #-1] 80130a0: 460c mov r4, r1 80130a2: 2c63 cmp r4, #99 @ 0x63 80130a4: 4631 mov r1, r6 80130a6: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff 80130aa: dcf1 bgt.n 8013090 <__exponent+0x1c> 80130ac: 3130 adds r1, #48 @ 0x30 80130ae: 1e94 subs r4, r2, #2 80130b0: f803 1c01 strb.w r1, [r3, #-1] 80130b4: 4623 mov r3, r4 80130b6: 1c41 adds r1, r0, #1 80130b8: 42ab cmp r3, r5 80130ba: d30a bcc.n 80130d2 <__exponent+0x5e> 80130bc: f10d 0309 add.w r3, sp, #9 80130c0: 1a9b subs r3, r3, r2 80130c2: 42ac cmp r4, r5 80130c4: bf88 it hi 80130c6: 2300 movhi r3, #0 80130c8: 3302 adds r3, #2 80130ca: 4403 add r3, r0 80130cc: 1a18 subs r0, r3, r0 80130ce: b003 add sp, #12 80130d0: bdf0 pop {r4, r5, r6, r7, pc} 80130d2: f813 6b01 ldrb.w r6, [r3], #1 80130d6: f801 6f01 strb.w r6, [r1, #1]! 80130da: e7ed b.n 80130b8 <__exponent+0x44> 80130dc: 2330 movs r3, #48 @ 0x30 80130de: 3130 adds r1, #48 @ 0x30 80130e0: 7083 strb r3, [r0, #2] 80130e2: 70c1 strb r1, [r0, #3] 80130e4: 1d03 adds r3, r0, #4 80130e6: e7f1 b.n 80130cc <__exponent+0x58> 080130e8 <_printf_float>: 80130e8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80130ec: b091 sub sp, #68 @ 0x44 80130ee: 460c mov r4, r1 80130f0: f8dd 8068 ldr.w r8, [sp, #104] @ 0x68 80130f4: 4616 mov r6, r2 80130f6: 461f mov r7, r3 80130f8: 4605 mov r5, r0 80130fa: f000 fcf7 bl 8013aec <_localeconv_r> 80130fe: 6803 ldr r3, [r0, #0] 8013100: 4618 mov r0, r3 8013102: 9308 str r3, [sp, #32] 8013104: f7f5 f890 bl 8008228 8013108: 2300 movs r3, #0 801310a: 930e str r3, [sp, #56] @ 0x38 801310c: f8d8 3000 ldr.w r3, [r8] 8013110: 9009 str r0, [sp, #36] @ 0x24 8013112: 3307 adds r3, #7 8013114: f023 0307 bic.w r3, r3, #7 8013118: f103 0208 add.w r2, r3, #8 801311c: f894 a018 ldrb.w sl, [r4, #24] 8013120: f8d4 b000 ldr.w fp, [r4] 8013124: f8c8 2000 str.w r2, [r8] 8013128: e9d3 8900 ldrd r8, r9, [r3] 801312c: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000 8013130: 930b str r3, [sp, #44] @ 0x2c 8013132: f8cd 8028 str.w r8, [sp, #40] @ 0x28 8013136: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801313a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 801313e: e9c4 8912 strd r8, r9, [r4, #72] @ 0x48 8013142: 4b9c ldr r3, [pc, #624] @ (80133b4 <_printf_float+0x2cc>) 8013144: f7f5 fcce bl 8008ae4 <__aeabi_dcmpun> 8013148: bb70 cbnz r0, 80131a8 <_printf_float+0xc0> 801314a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 801314e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8013152: 4b98 ldr r3, [pc, #608] @ (80133b4 <_printf_float+0x2cc>) 8013154: f7f5 fca8 bl 8008aa8 <__aeabi_dcmple> 8013158: bb30 cbnz r0, 80131a8 <_printf_float+0xc0> 801315a: 2200 movs r2, #0 801315c: 2300 movs r3, #0 801315e: 4640 mov r0, r8 8013160: 4649 mov r1, r9 8013162: f7f5 fc97 bl 8008a94 <__aeabi_dcmplt> 8013166: b110 cbz r0, 801316e <_printf_float+0x86> 8013168: 232d movs r3, #45 @ 0x2d 801316a: f884 3043 strb.w r3, [r4, #67] @ 0x43 801316e: 4a92 ldr r2, [pc, #584] @ (80133b8 <_printf_float+0x2d0>) 8013170: 4b92 ldr r3, [pc, #584] @ (80133bc <_printf_float+0x2d4>) 8013172: f1ba 0f47 cmp.w sl, #71 @ 0x47 8013176: bf8c ite hi 8013178: 4690 movhi r8, r2 801317a: 4698 movls r8, r3 801317c: 2303 movs r3, #3 801317e: f04f 0900 mov.w r9, #0 8013182: 6123 str r3, [r4, #16] 8013184: f02b 0304 bic.w r3, fp, #4 8013188: 6023 str r3, [r4, #0] 801318a: 4633 mov r3, r6 801318c: 4621 mov r1, r4 801318e: 4628 mov r0, r5 8013190: 9700 str r7, [sp, #0] 8013192: aa0f add r2, sp, #60 @ 0x3c 8013194: f000 f9d4 bl 8013540 <_printf_common> 8013198: 3001 adds r0, #1 801319a: f040 8090 bne.w 80132be <_printf_float+0x1d6> 801319e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80131a2: b011 add sp, #68 @ 0x44 80131a4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80131a8: 4642 mov r2, r8 80131aa: 464b mov r3, r9 80131ac: 4640 mov r0, r8 80131ae: 4649 mov r1, r9 80131b0: f7f5 fc98 bl 8008ae4 <__aeabi_dcmpun> 80131b4: b148 cbz r0, 80131ca <_printf_float+0xe2> 80131b6: 464b mov r3, r9 80131b8: 2b00 cmp r3, #0 80131ba: bfb8 it lt 80131bc: 232d movlt r3, #45 @ 0x2d 80131be: 4a80 ldr r2, [pc, #512] @ (80133c0 <_printf_float+0x2d8>) 80131c0: bfb8 it lt 80131c2: f884 3043 strblt.w r3, [r4, #67] @ 0x43 80131c6: 4b7f ldr r3, [pc, #508] @ (80133c4 <_printf_float+0x2dc>) 80131c8: e7d3 b.n 8013172 <_printf_float+0x8a> 80131ca: 6863 ldr r3, [r4, #4] 80131cc: f00a 01df and.w r1, sl, #223 @ 0xdf 80131d0: 1c5a adds r2, r3, #1 80131d2: d13f bne.n 8013254 <_printf_float+0x16c> 80131d4: 2306 movs r3, #6 80131d6: 6063 str r3, [r4, #4] 80131d8: 2200 movs r2, #0 80131da: f44b 6380 orr.w r3, fp, #1024 @ 0x400 80131de: 6023 str r3, [r4, #0] 80131e0: 9206 str r2, [sp, #24] 80131e2: aa0e add r2, sp, #56 @ 0x38 80131e4: e9cd a204 strd sl, r2, [sp, #16] 80131e8: aa0d add r2, sp, #52 @ 0x34 80131ea: 9203 str r2, [sp, #12] 80131ec: f10d 0233 add.w r2, sp, #51 @ 0x33 80131f0: e9cd 3201 strd r3, r2, [sp, #4] 80131f4: 6863 ldr r3, [r4, #4] 80131f6: 4642 mov r2, r8 80131f8: 9300 str r3, [sp, #0] 80131fa: 4628 mov r0, r5 80131fc: 464b mov r3, r9 80131fe: 910a str r1, [sp, #40] @ 0x28 8013200: f7ff fed4 bl 8012fac <__cvt> 8013204: 990a ldr r1, [sp, #40] @ 0x28 8013206: 4680 mov r8, r0 8013208: 2947 cmp r1, #71 @ 0x47 801320a: 990d ldr r1, [sp, #52] @ 0x34 801320c: d128 bne.n 8013260 <_printf_float+0x178> 801320e: 1cc8 adds r0, r1, #3 8013210: db02 blt.n 8013218 <_printf_float+0x130> 8013212: 6863 ldr r3, [r4, #4] 8013214: 4299 cmp r1, r3 8013216: dd40 ble.n 801329a <_printf_float+0x1b2> 8013218: f1aa 0a02 sub.w sl, sl, #2 801321c: fa5f fa8a uxtb.w sl, sl 8013220: 4652 mov r2, sl 8013222: 3901 subs r1, #1 8013224: f104 0050 add.w r0, r4, #80 @ 0x50 8013228: 910d str r1, [sp, #52] @ 0x34 801322a: f7ff ff23 bl 8013074 <__exponent> 801322e: 9a0e ldr r2, [sp, #56] @ 0x38 8013230: 4681 mov r9, r0 8013232: 1813 adds r3, r2, r0 8013234: 2a01 cmp r2, #1 8013236: 6123 str r3, [r4, #16] 8013238: dc02 bgt.n 8013240 <_printf_float+0x158> 801323a: 6822 ldr r2, [r4, #0] 801323c: 07d2 lsls r2, r2, #31 801323e: d501 bpl.n 8013244 <_printf_float+0x15c> 8013240: 3301 adds r3, #1 8013242: 6123 str r3, [r4, #16] 8013244: f89d 3033 ldrb.w r3, [sp, #51] @ 0x33 8013248: 2b00 cmp r3, #0 801324a: d09e beq.n 801318a <_printf_float+0xa2> 801324c: 232d movs r3, #45 @ 0x2d 801324e: f884 3043 strb.w r3, [r4, #67] @ 0x43 8013252: e79a b.n 801318a <_printf_float+0xa2> 8013254: 2947 cmp r1, #71 @ 0x47 8013256: d1bf bne.n 80131d8 <_printf_float+0xf0> 8013258: 2b00 cmp r3, #0 801325a: d1bd bne.n 80131d8 <_printf_float+0xf0> 801325c: 2301 movs r3, #1 801325e: e7ba b.n 80131d6 <_printf_float+0xee> 8013260: f1ba 0f65 cmp.w sl, #101 @ 0x65 8013264: d9dc bls.n 8013220 <_printf_float+0x138> 8013266: f1ba 0f66 cmp.w sl, #102 @ 0x66 801326a: d118 bne.n 801329e <_printf_float+0x1b6> 801326c: 2900 cmp r1, #0 801326e: 6863 ldr r3, [r4, #4] 8013270: dd0b ble.n 801328a <_printf_float+0x1a2> 8013272: 6121 str r1, [r4, #16] 8013274: b913 cbnz r3, 801327c <_printf_float+0x194> 8013276: 6822 ldr r2, [r4, #0] 8013278: 07d0 lsls r0, r2, #31 801327a: d502 bpl.n 8013282 <_printf_float+0x19a> 801327c: 3301 adds r3, #1 801327e: 440b add r3, r1 8013280: 6123 str r3, [r4, #16] 8013282: f04f 0900 mov.w r9, #0 8013286: 65a1 str r1, [r4, #88] @ 0x58 8013288: e7dc b.n 8013244 <_printf_float+0x15c> 801328a: b913 cbnz r3, 8013292 <_printf_float+0x1aa> 801328c: 6822 ldr r2, [r4, #0] 801328e: 07d2 lsls r2, r2, #31 8013290: d501 bpl.n 8013296 <_printf_float+0x1ae> 8013292: 3302 adds r3, #2 8013294: e7f4 b.n 8013280 <_printf_float+0x198> 8013296: 2301 movs r3, #1 8013298: e7f2 b.n 8013280 <_printf_float+0x198> 801329a: f04f 0a67 mov.w sl, #103 @ 0x67 801329e: 9b0e ldr r3, [sp, #56] @ 0x38 80132a0: 4299 cmp r1, r3 80132a2: db05 blt.n 80132b0 <_printf_float+0x1c8> 80132a4: 6823 ldr r3, [r4, #0] 80132a6: 6121 str r1, [r4, #16] 80132a8: 07d8 lsls r0, r3, #31 80132aa: d5ea bpl.n 8013282 <_printf_float+0x19a> 80132ac: 1c4b adds r3, r1, #1 80132ae: e7e7 b.n 8013280 <_printf_float+0x198> 80132b0: 2900 cmp r1, #0 80132b2: bfcc ite gt 80132b4: 2201 movgt r2, #1 80132b6: f1c1 0202 rsble r2, r1, #2 80132ba: 4413 add r3, r2 80132bc: e7e0 b.n 8013280 <_printf_float+0x198> 80132be: 6823 ldr r3, [r4, #0] 80132c0: 055a lsls r2, r3, #21 80132c2: d407 bmi.n 80132d4 <_printf_float+0x1ec> 80132c4: 6923 ldr r3, [r4, #16] 80132c6: 4642 mov r2, r8 80132c8: 4631 mov r1, r6 80132ca: 4628 mov r0, r5 80132cc: 47b8 blx r7 80132ce: 3001 adds r0, #1 80132d0: d12b bne.n 801332a <_printf_float+0x242> 80132d2: e764 b.n 801319e <_printf_float+0xb6> 80132d4: f1ba 0f65 cmp.w sl, #101 @ 0x65 80132d8: f240 80dc bls.w 8013494 <_printf_float+0x3ac> 80132dc: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 80132e0: 2200 movs r2, #0 80132e2: 2300 movs r3, #0 80132e4: f7f5 fbcc bl 8008a80 <__aeabi_dcmpeq> 80132e8: 2800 cmp r0, #0 80132ea: d033 beq.n 8013354 <_printf_float+0x26c> 80132ec: 2301 movs r3, #1 80132ee: 4631 mov r1, r6 80132f0: 4628 mov r0, r5 80132f2: 4a35 ldr r2, [pc, #212] @ (80133c8 <_printf_float+0x2e0>) 80132f4: 47b8 blx r7 80132f6: 3001 adds r0, #1 80132f8: f43f af51 beq.w 801319e <_printf_float+0xb6> 80132fc: e9dd 380d ldrd r3, r8, [sp, #52] @ 0x34 8013300: 4543 cmp r3, r8 8013302: db02 blt.n 801330a <_printf_float+0x222> 8013304: 6823 ldr r3, [r4, #0] 8013306: 07d8 lsls r0, r3, #31 8013308: d50f bpl.n 801332a <_printf_float+0x242> 801330a: e9dd 2308 ldrd r2, r3, [sp, #32] 801330e: 4631 mov r1, r6 8013310: 4628 mov r0, r5 8013312: 47b8 blx r7 8013314: 3001 adds r0, #1 8013316: f43f af42 beq.w 801319e <_printf_float+0xb6> 801331a: f04f 0900 mov.w r9, #0 801331e: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 8013322: f104 0a1a add.w sl, r4, #26 8013326: 45c8 cmp r8, r9 8013328: dc09 bgt.n 801333e <_printf_float+0x256> 801332a: 6823 ldr r3, [r4, #0] 801332c: 079b lsls r3, r3, #30 801332e: f100 8102 bmi.w 8013536 <_printf_float+0x44e> 8013332: 68e0 ldr r0, [r4, #12] 8013334: 9b0f ldr r3, [sp, #60] @ 0x3c 8013336: 4298 cmp r0, r3 8013338: bfb8 it lt 801333a: 4618 movlt r0, r3 801333c: e731 b.n 80131a2 <_printf_float+0xba> 801333e: 2301 movs r3, #1 8013340: 4652 mov r2, sl 8013342: 4631 mov r1, r6 8013344: 4628 mov r0, r5 8013346: 47b8 blx r7 8013348: 3001 adds r0, #1 801334a: f43f af28 beq.w 801319e <_printf_float+0xb6> 801334e: f109 0901 add.w r9, r9, #1 8013352: e7e8 b.n 8013326 <_printf_float+0x23e> 8013354: 9b0d ldr r3, [sp, #52] @ 0x34 8013356: 2b00 cmp r3, #0 8013358: dc38 bgt.n 80133cc <_printf_float+0x2e4> 801335a: 2301 movs r3, #1 801335c: 4631 mov r1, r6 801335e: 4628 mov r0, r5 8013360: 4a19 ldr r2, [pc, #100] @ (80133c8 <_printf_float+0x2e0>) 8013362: 47b8 blx r7 8013364: 3001 adds r0, #1 8013366: f43f af1a beq.w 801319e <_printf_float+0xb6> 801336a: e9dd 390d ldrd r3, r9, [sp, #52] @ 0x34 801336e: ea59 0303 orrs.w r3, r9, r3 8013372: d102 bne.n 801337a <_printf_float+0x292> 8013374: 6823 ldr r3, [r4, #0] 8013376: 07d9 lsls r1, r3, #31 8013378: d5d7 bpl.n 801332a <_printf_float+0x242> 801337a: e9dd 2308 ldrd r2, r3, [sp, #32] 801337e: 4631 mov r1, r6 8013380: 4628 mov r0, r5 8013382: 47b8 blx r7 8013384: 3001 adds r0, #1 8013386: f43f af0a beq.w 801319e <_printf_float+0xb6> 801338a: f04f 0a00 mov.w sl, #0 801338e: f104 0b1a add.w fp, r4, #26 8013392: 9b0d ldr r3, [sp, #52] @ 0x34 8013394: 425b negs r3, r3 8013396: 4553 cmp r3, sl 8013398: dc01 bgt.n 801339e <_printf_float+0x2b6> 801339a: 464b mov r3, r9 801339c: e793 b.n 80132c6 <_printf_float+0x1de> 801339e: 2301 movs r3, #1 80133a0: 465a mov r2, fp 80133a2: 4631 mov r1, r6 80133a4: 4628 mov r0, r5 80133a6: 47b8 blx r7 80133a8: 3001 adds r0, #1 80133aa: f43f aef8 beq.w 801319e <_printf_float+0xb6> 80133ae: f10a 0a01 add.w sl, sl, #1 80133b2: e7ee b.n 8013392 <_printf_float+0x2aa> 80133b4: 7fefffff .word 0x7fefffff 80133b8: 0801614c .word 0x0801614c 80133bc: 08016148 .word 0x08016148 80133c0: 08016154 .word 0x08016154 80133c4: 08016150 .word 0x08016150 80133c8: 08016158 .word 0x08016158 80133cc: 6da3 ldr r3, [r4, #88] @ 0x58 80133ce: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 80133d2: 4553 cmp r3, sl 80133d4: bfa8 it ge 80133d6: 4653 movge r3, sl 80133d8: 2b00 cmp r3, #0 80133da: 4699 mov r9, r3 80133dc: dc36 bgt.n 801344c <_printf_float+0x364> 80133de: f04f 0b00 mov.w fp, #0 80133e2: ea29 79e9 bic.w r9, r9, r9, asr #31 80133e6: f104 021a add.w r2, r4, #26 80133ea: 6da3 ldr r3, [r4, #88] @ 0x58 80133ec: 930a str r3, [sp, #40] @ 0x28 80133ee: eba3 0309 sub.w r3, r3, r9 80133f2: 455b cmp r3, fp 80133f4: dc31 bgt.n 801345a <_printf_float+0x372> 80133f6: 9b0d ldr r3, [sp, #52] @ 0x34 80133f8: 459a cmp sl, r3 80133fa: dc3a bgt.n 8013472 <_printf_float+0x38a> 80133fc: 6823 ldr r3, [r4, #0] 80133fe: 07da lsls r2, r3, #31 8013400: d437 bmi.n 8013472 <_printf_float+0x38a> 8013402: 9b0d ldr r3, [sp, #52] @ 0x34 8013404: ebaa 0903 sub.w r9, sl, r3 8013408: 9b0a ldr r3, [sp, #40] @ 0x28 801340a: ebaa 0303 sub.w r3, sl, r3 801340e: 4599 cmp r9, r3 8013410: bfa8 it ge 8013412: 4699 movge r9, r3 8013414: f1b9 0f00 cmp.w r9, #0 8013418: dc33 bgt.n 8013482 <_printf_float+0x39a> 801341a: f04f 0800 mov.w r8, #0 801341e: ea29 79e9 bic.w r9, r9, r9, asr #31 8013422: f104 0b1a add.w fp, r4, #26 8013426: 9b0d ldr r3, [sp, #52] @ 0x34 8013428: ebaa 0303 sub.w r3, sl, r3 801342c: eba3 0309 sub.w r3, r3, r9 8013430: 4543 cmp r3, r8 8013432: f77f af7a ble.w 801332a <_printf_float+0x242> 8013436: 2301 movs r3, #1 8013438: 465a mov r2, fp 801343a: 4631 mov r1, r6 801343c: 4628 mov r0, r5 801343e: 47b8 blx r7 8013440: 3001 adds r0, #1 8013442: f43f aeac beq.w 801319e <_printf_float+0xb6> 8013446: f108 0801 add.w r8, r8, #1 801344a: e7ec b.n 8013426 <_printf_float+0x33e> 801344c: 4642 mov r2, r8 801344e: 4631 mov r1, r6 8013450: 4628 mov r0, r5 8013452: 47b8 blx r7 8013454: 3001 adds r0, #1 8013456: d1c2 bne.n 80133de <_printf_float+0x2f6> 8013458: e6a1 b.n 801319e <_printf_float+0xb6> 801345a: 2301 movs r3, #1 801345c: 4631 mov r1, r6 801345e: 4628 mov r0, r5 8013460: 920a str r2, [sp, #40] @ 0x28 8013462: 47b8 blx r7 8013464: 3001 adds r0, #1 8013466: f43f ae9a beq.w 801319e <_printf_float+0xb6> 801346a: 9a0a ldr r2, [sp, #40] @ 0x28 801346c: f10b 0b01 add.w fp, fp, #1 8013470: e7bb b.n 80133ea <_printf_float+0x302> 8013472: 4631 mov r1, r6 8013474: e9dd 2308 ldrd r2, r3, [sp, #32] 8013478: 4628 mov r0, r5 801347a: 47b8 blx r7 801347c: 3001 adds r0, #1 801347e: d1c0 bne.n 8013402 <_printf_float+0x31a> 8013480: e68d b.n 801319e <_printf_float+0xb6> 8013482: 9a0a ldr r2, [sp, #40] @ 0x28 8013484: 464b mov r3, r9 8013486: 4631 mov r1, r6 8013488: 4628 mov r0, r5 801348a: 4442 add r2, r8 801348c: 47b8 blx r7 801348e: 3001 adds r0, #1 8013490: d1c3 bne.n 801341a <_printf_float+0x332> 8013492: e684 b.n 801319e <_printf_float+0xb6> 8013494: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 8013498: f1ba 0f01 cmp.w sl, #1 801349c: dc01 bgt.n 80134a2 <_printf_float+0x3ba> 801349e: 07db lsls r3, r3, #31 80134a0: d536 bpl.n 8013510 <_printf_float+0x428> 80134a2: 2301 movs r3, #1 80134a4: 4642 mov r2, r8 80134a6: 4631 mov r1, r6 80134a8: 4628 mov r0, r5 80134aa: 47b8 blx r7 80134ac: 3001 adds r0, #1 80134ae: f43f ae76 beq.w 801319e <_printf_float+0xb6> 80134b2: e9dd 2308 ldrd r2, r3, [sp, #32] 80134b6: 4631 mov r1, r6 80134b8: 4628 mov r0, r5 80134ba: 47b8 blx r7 80134bc: 3001 adds r0, #1 80134be: f43f ae6e beq.w 801319e <_printf_float+0xb6> 80134c2: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 80134c6: 2200 movs r2, #0 80134c8: 2300 movs r3, #0 80134ca: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff 80134ce: f7f5 fad7 bl 8008a80 <__aeabi_dcmpeq> 80134d2: b9c0 cbnz r0, 8013506 <_printf_float+0x41e> 80134d4: 4653 mov r3, sl 80134d6: f108 0201 add.w r2, r8, #1 80134da: 4631 mov r1, r6 80134dc: 4628 mov r0, r5 80134de: 47b8 blx r7 80134e0: 3001 adds r0, #1 80134e2: d10c bne.n 80134fe <_printf_float+0x416> 80134e4: e65b b.n 801319e <_printf_float+0xb6> 80134e6: 2301 movs r3, #1 80134e8: 465a mov r2, fp 80134ea: 4631 mov r1, r6 80134ec: 4628 mov r0, r5 80134ee: 47b8 blx r7 80134f0: 3001 adds r0, #1 80134f2: f43f ae54 beq.w 801319e <_printf_float+0xb6> 80134f6: f108 0801 add.w r8, r8, #1 80134fa: 45d0 cmp r8, sl 80134fc: dbf3 blt.n 80134e6 <_printf_float+0x3fe> 80134fe: 464b mov r3, r9 8013500: f104 0250 add.w r2, r4, #80 @ 0x50 8013504: e6e0 b.n 80132c8 <_printf_float+0x1e0> 8013506: f04f 0800 mov.w r8, #0 801350a: f104 0b1a add.w fp, r4, #26 801350e: e7f4 b.n 80134fa <_printf_float+0x412> 8013510: 2301 movs r3, #1 8013512: 4642 mov r2, r8 8013514: e7e1 b.n 80134da <_printf_float+0x3f2> 8013516: 2301 movs r3, #1 8013518: 464a mov r2, r9 801351a: 4631 mov r1, r6 801351c: 4628 mov r0, r5 801351e: 47b8 blx r7 8013520: 3001 adds r0, #1 8013522: f43f ae3c beq.w 801319e <_printf_float+0xb6> 8013526: f108 0801 add.w r8, r8, #1 801352a: 68e3 ldr r3, [r4, #12] 801352c: 990f ldr r1, [sp, #60] @ 0x3c 801352e: 1a5b subs r3, r3, r1 8013530: 4543 cmp r3, r8 8013532: dcf0 bgt.n 8013516 <_printf_float+0x42e> 8013534: e6fd b.n 8013332 <_printf_float+0x24a> 8013536: f04f 0800 mov.w r8, #0 801353a: f104 0919 add.w r9, r4, #25 801353e: e7f4 b.n 801352a <_printf_float+0x442> 08013540 <_printf_common>: 8013540: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8013544: 4616 mov r6, r2 8013546: 4698 mov r8, r3 8013548: 688a ldr r2, [r1, #8] 801354a: 690b ldr r3, [r1, #16] 801354c: 4607 mov r7, r0 801354e: 4293 cmp r3, r2 8013550: bfb8 it lt 8013552: 4613 movlt r3, r2 8013554: 6033 str r3, [r6, #0] 8013556: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 801355a: 460c mov r4, r1 801355c: f8dd 9020 ldr.w r9, [sp, #32] 8013560: b10a cbz r2, 8013566 <_printf_common+0x26> 8013562: 3301 adds r3, #1 8013564: 6033 str r3, [r6, #0] 8013566: 6823 ldr r3, [r4, #0] 8013568: 0699 lsls r1, r3, #26 801356a: bf42 ittt mi 801356c: 6833 ldrmi r3, [r6, #0] 801356e: 3302 addmi r3, #2 8013570: 6033 strmi r3, [r6, #0] 8013572: 6825 ldr r5, [r4, #0] 8013574: f015 0506 ands.w r5, r5, #6 8013578: d106 bne.n 8013588 <_printf_common+0x48> 801357a: f104 0a19 add.w sl, r4, #25 801357e: 68e3 ldr r3, [r4, #12] 8013580: 6832 ldr r2, [r6, #0] 8013582: 1a9b subs r3, r3, r2 8013584: 42ab cmp r3, r5 8013586: dc2b bgt.n 80135e0 <_printf_common+0xa0> 8013588: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 801358c: 6822 ldr r2, [r4, #0] 801358e: 3b00 subs r3, #0 8013590: bf18 it ne 8013592: 2301 movne r3, #1 8013594: 0692 lsls r2, r2, #26 8013596: d430 bmi.n 80135fa <_printf_common+0xba> 8013598: 4641 mov r1, r8 801359a: 4638 mov r0, r7 801359c: f104 0243 add.w r2, r4, #67 @ 0x43 80135a0: 47c8 blx r9 80135a2: 3001 adds r0, #1 80135a4: d023 beq.n 80135ee <_printf_common+0xae> 80135a6: 6823 ldr r3, [r4, #0] 80135a8: 6922 ldr r2, [r4, #16] 80135aa: f003 0306 and.w r3, r3, #6 80135ae: 2b04 cmp r3, #4 80135b0: bf14 ite ne 80135b2: 2500 movne r5, #0 80135b4: 6833 ldreq r3, [r6, #0] 80135b6: f04f 0600 mov.w r6, #0 80135ba: bf08 it eq 80135bc: 68e5 ldreq r5, [r4, #12] 80135be: f104 041a add.w r4, r4, #26 80135c2: bf08 it eq 80135c4: 1aed subeq r5, r5, r3 80135c6: f854 3c12 ldr.w r3, [r4, #-18] 80135ca: bf08 it eq 80135cc: ea25 75e5 biceq.w r5, r5, r5, asr #31 80135d0: 4293 cmp r3, r2 80135d2: bfc4 itt gt 80135d4: 1a9b subgt r3, r3, r2 80135d6: 18ed addgt r5, r5, r3 80135d8: 42b5 cmp r5, r6 80135da: d11a bne.n 8013612 <_printf_common+0xd2> 80135dc: 2000 movs r0, #0 80135de: e008 b.n 80135f2 <_printf_common+0xb2> 80135e0: 2301 movs r3, #1 80135e2: 4652 mov r2, sl 80135e4: 4641 mov r1, r8 80135e6: 4638 mov r0, r7 80135e8: 47c8 blx r9 80135ea: 3001 adds r0, #1 80135ec: d103 bne.n 80135f6 <_printf_common+0xb6> 80135ee: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80135f2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80135f6: 3501 adds r5, #1 80135f8: e7c1 b.n 801357e <_printf_common+0x3e> 80135fa: 2030 movs r0, #48 @ 0x30 80135fc: 18e1 adds r1, r4, r3 80135fe: f881 0043 strb.w r0, [r1, #67] @ 0x43 8013602: 1c5a adds r2, r3, #1 8013604: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 8013608: 4422 add r2, r4 801360a: 3302 adds r3, #2 801360c: f882 1043 strb.w r1, [r2, #67] @ 0x43 8013610: e7c2 b.n 8013598 <_printf_common+0x58> 8013612: 2301 movs r3, #1 8013614: 4622 mov r2, r4 8013616: 4641 mov r1, r8 8013618: 4638 mov r0, r7 801361a: 47c8 blx r9 801361c: 3001 adds r0, #1 801361e: d0e6 beq.n 80135ee <_printf_common+0xae> 8013620: 3601 adds r6, #1 8013622: e7d9 b.n 80135d8 <_printf_common+0x98> 08013624 <_printf_i>: 8013624: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8013628: 7e0f ldrb r7, [r1, #24] 801362a: 4691 mov r9, r2 801362c: 2f78 cmp r7, #120 @ 0x78 801362e: 4680 mov r8, r0 8013630: 460c mov r4, r1 8013632: 469a mov sl, r3 8013634: 9e0c ldr r6, [sp, #48] @ 0x30 8013636: f101 0243 add.w r2, r1, #67 @ 0x43 801363a: d807 bhi.n 801364c <_printf_i+0x28> 801363c: 2f62 cmp r7, #98 @ 0x62 801363e: d80a bhi.n 8013656 <_printf_i+0x32> 8013640: 2f00 cmp r7, #0 8013642: f000 80d1 beq.w 80137e8 <_printf_i+0x1c4> 8013646: 2f58 cmp r7, #88 @ 0x58 8013648: f000 80b8 beq.w 80137bc <_printf_i+0x198> 801364c: f104 0642 add.w r6, r4, #66 @ 0x42 8013650: f884 7042 strb.w r7, [r4, #66] @ 0x42 8013654: e03a b.n 80136cc <_printf_i+0xa8> 8013656: f1a7 0363 sub.w r3, r7, #99 @ 0x63 801365a: 2b15 cmp r3, #21 801365c: d8f6 bhi.n 801364c <_printf_i+0x28> 801365e: a101 add r1, pc, #4 @ (adr r1, 8013664 <_printf_i+0x40>) 8013660: f851 f023 ldr.w pc, [r1, r3, lsl #2] 8013664: 080136bd .word 0x080136bd 8013668: 080136d1 .word 0x080136d1 801366c: 0801364d .word 0x0801364d 8013670: 0801364d .word 0x0801364d 8013674: 0801364d .word 0x0801364d 8013678: 0801364d .word 0x0801364d 801367c: 080136d1 .word 0x080136d1 8013680: 0801364d .word 0x0801364d 8013684: 0801364d .word 0x0801364d 8013688: 0801364d .word 0x0801364d 801368c: 0801364d .word 0x0801364d 8013690: 080137cf .word 0x080137cf 8013694: 080136fb .word 0x080136fb 8013698: 08013789 .word 0x08013789 801369c: 0801364d .word 0x0801364d 80136a0: 0801364d .word 0x0801364d 80136a4: 080137f1 .word 0x080137f1 80136a8: 0801364d .word 0x0801364d 80136ac: 080136fb .word 0x080136fb 80136b0: 0801364d .word 0x0801364d 80136b4: 0801364d .word 0x0801364d 80136b8: 08013791 .word 0x08013791 80136bc: 6833 ldr r3, [r6, #0] 80136be: 1d1a adds r2, r3, #4 80136c0: 681b ldr r3, [r3, #0] 80136c2: 6032 str r2, [r6, #0] 80136c4: f104 0642 add.w r6, r4, #66 @ 0x42 80136c8: f884 3042 strb.w r3, [r4, #66] @ 0x42 80136cc: 2301 movs r3, #1 80136ce: e09c b.n 801380a <_printf_i+0x1e6> 80136d0: 6833 ldr r3, [r6, #0] 80136d2: 6820 ldr r0, [r4, #0] 80136d4: 1d19 adds r1, r3, #4 80136d6: 6031 str r1, [r6, #0] 80136d8: 0606 lsls r6, r0, #24 80136da: d501 bpl.n 80136e0 <_printf_i+0xbc> 80136dc: 681d ldr r5, [r3, #0] 80136de: e003 b.n 80136e8 <_printf_i+0xc4> 80136e0: 0645 lsls r5, r0, #25 80136e2: d5fb bpl.n 80136dc <_printf_i+0xb8> 80136e4: f9b3 5000 ldrsh.w r5, [r3] 80136e8: 2d00 cmp r5, #0 80136ea: da03 bge.n 80136f4 <_printf_i+0xd0> 80136ec: 232d movs r3, #45 @ 0x2d 80136ee: 426d negs r5, r5 80136f0: f884 3043 strb.w r3, [r4, #67] @ 0x43 80136f4: 230a movs r3, #10 80136f6: 4858 ldr r0, [pc, #352] @ (8013858 <_printf_i+0x234>) 80136f8: e011 b.n 801371e <_printf_i+0xfa> 80136fa: 6821 ldr r1, [r4, #0] 80136fc: 6833 ldr r3, [r6, #0] 80136fe: 0608 lsls r0, r1, #24 8013700: f853 5b04 ldr.w r5, [r3], #4 8013704: d402 bmi.n 801370c <_printf_i+0xe8> 8013706: 0649 lsls r1, r1, #25 8013708: bf48 it mi 801370a: b2ad uxthmi r5, r5 801370c: 2f6f cmp r7, #111 @ 0x6f 801370e: 6033 str r3, [r6, #0] 8013710: bf14 ite ne 8013712: 230a movne r3, #10 8013714: 2308 moveq r3, #8 8013716: 4850 ldr r0, [pc, #320] @ (8013858 <_printf_i+0x234>) 8013718: 2100 movs r1, #0 801371a: f884 1043 strb.w r1, [r4, #67] @ 0x43 801371e: 6866 ldr r6, [r4, #4] 8013720: 2e00 cmp r6, #0 8013722: 60a6 str r6, [r4, #8] 8013724: db05 blt.n 8013732 <_printf_i+0x10e> 8013726: 6821 ldr r1, [r4, #0] 8013728: 432e orrs r6, r5 801372a: f021 0104 bic.w r1, r1, #4 801372e: 6021 str r1, [r4, #0] 8013730: d04b beq.n 80137ca <_printf_i+0x1a6> 8013732: 4616 mov r6, r2 8013734: fbb5 f1f3 udiv r1, r5, r3 8013738: fb03 5711 mls r7, r3, r1, r5 801373c: 5dc7 ldrb r7, [r0, r7] 801373e: f806 7d01 strb.w r7, [r6, #-1]! 8013742: 462f mov r7, r5 8013744: 42bb cmp r3, r7 8013746: 460d mov r5, r1 8013748: d9f4 bls.n 8013734 <_printf_i+0x110> 801374a: 2b08 cmp r3, #8 801374c: d10b bne.n 8013766 <_printf_i+0x142> 801374e: 6823 ldr r3, [r4, #0] 8013750: 07df lsls r7, r3, #31 8013752: d508 bpl.n 8013766 <_printf_i+0x142> 8013754: 6923 ldr r3, [r4, #16] 8013756: 6861 ldr r1, [r4, #4] 8013758: 4299 cmp r1, r3 801375a: bfde ittt le 801375c: 2330 movle r3, #48 @ 0x30 801375e: f806 3c01 strble.w r3, [r6, #-1] 8013762: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 8013766: 1b92 subs r2, r2, r6 8013768: 6122 str r2, [r4, #16] 801376a: 464b mov r3, r9 801376c: 4621 mov r1, r4 801376e: 4640 mov r0, r8 8013770: f8cd a000 str.w sl, [sp] 8013774: aa03 add r2, sp, #12 8013776: f7ff fee3 bl 8013540 <_printf_common> 801377a: 3001 adds r0, #1 801377c: d14a bne.n 8013814 <_printf_i+0x1f0> 801377e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8013782: b004 add sp, #16 8013784: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8013788: 6823 ldr r3, [r4, #0] 801378a: f043 0320 orr.w r3, r3, #32 801378e: 6023 str r3, [r4, #0] 8013790: 2778 movs r7, #120 @ 0x78 8013792: 4832 ldr r0, [pc, #200] @ (801385c <_printf_i+0x238>) 8013794: f884 7045 strb.w r7, [r4, #69] @ 0x45 8013798: 6823 ldr r3, [r4, #0] 801379a: 6831 ldr r1, [r6, #0] 801379c: 061f lsls r7, r3, #24 801379e: f851 5b04 ldr.w r5, [r1], #4 80137a2: d402 bmi.n 80137aa <_printf_i+0x186> 80137a4: 065f lsls r7, r3, #25 80137a6: bf48 it mi 80137a8: b2ad uxthmi r5, r5 80137aa: 6031 str r1, [r6, #0] 80137ac: 07d9 lsls r1, r3, #31 80137ae: bf44 itt mi 80137b0: f043 0320 orrmi.w r3, r3, #32 80137b4: 6023 strmi r3, [r4, #0] 80137b6: b11d cbz r5, 80137c0 <_printf_i+0x19c> 80137b8: 2310 movs r3, #16 80137ba: e7ad b.n 8013718 <_printf_i+0xf4> 80137bc: 4826 ldr r0, [pc, #152] @ (8013858 <_printf_i+0x234>) 80137be: e7e9 b.n 8013794 <_printf_i+0x170> 80137c0: 6823 ldr r3, [r4, #0] 80137c2: f023 0320 bic.w r3, r3, #32 80137c6: 6023 str r3, [r4, #0] 80137c8: e7f6 b.n 80137b8 <_printf_i+0x194> 80137ca: 4616 mov r6, r2 80137cc: e7bd b.n 801374a <_printf_i+0x126> 80137ce: 6833 ldr r3, [r6, #0] 80137d0: 6825 ldr r5, [r4, #0] 80137d2: 1d18 adds r0, r3, #4 80137d4: 6961 ldr r1, [r4, #20] 80137d6: 6030 str r0, [r6, #0] 80137d8: 062e lsls r6, r5, #24 80137da: 681b ldr r3, [r3, #0] 80137dc: d501 bpl.n 80137e2 <_printf_i+0x1be> 80137de: 6019 str r1, [r3, #0] 80137e0: e002 b.n 80137e8 <_printf_i+0x1c4> 80137e2: 0668 lsls r0, r5, #25 80137e4: d5fb bpl.n 80137de <_printf_i+0x1ba> 80137e6: 8019 strh r1, [r3, #0] 80137e8: 2300 movs r3, #0 80137ea: 4616 mov r6, r2 80137ec: 6123 str r3, [r4, #16] 80137ee: e7bc b.n 801376a <_printf_i+0x146> 80137f0: 6833 ldr r3, [r6, #0] 80137f2: 2100 movs r1, #0 80137f4: 1d1a adds r2, r3, #4 80137f6: 6032 str r2, [r6, #0] 80137f8: 681e ldr r6, [r3, #0] 80137fa: 6862 ldr r2, [r4, #4] 80137fc: 4630 mov r0, r6 80137fe: f000 f979 bl 8013af4 8013802: b108 cbz r0, 8013808 <_printf_i+0x1e4> 8013804: 1b80 subs r0, r0, r6 8013806: 6060 str r0, [r4, #4] 8013808: 6863 ldr r3, [r4, #4] 801380a: 6123 str r3, [r4, #16] 801380c: 2300 movs r3, #0 801380e: f884 3043 strb.w r3, [r4, #67] @ 0x43 8013812: e7aa b.n 801376a <_printf_i+0x146> 8013814: 4632 mov r2, r6 8013816: 4649 mov r1, r9 8013818: 4640 mov r0, r8 801381a: 6923 ldr r3, [r4, #16] 801381c: 47d0 blx sl 801381e: 3001 adds r0, #1 8013820: d0ad beq.n 801377e <_printf_i+0x15a> 8013822: 6823 ldr r3, [r4, #0] 8013824: 079b lsls r3, r3, #30 8013826: d413 bmi.n 8013850 <_printf_i+0x22c> 8013828: 68e0 ldr r0, [r4, #12] 801382a: 9b03 ldr r3, [sp, #12] 801382c: 4298 cmp r0, r3 801382e: bfb8 it lt 8013830: 4618 movlt r0, r3 8013832: e7a6 b.n 8013782 <_printf_i+0x15e> 8013834: 2301 movs r3, #1 8013836: 4632 mov r2, r6 8013838: 4649 mov r1, r9 801383a: 4640 mov r0, r8 801383c: 47d0 blx sl 801383e: 3001 adds r0, #1 8013840: d09d beq.n 801377e <_printf_i+0x15a> 8013842: 3501 adds r5, #1 8013844: 68e3 ldr r3, [r4, #12] 8013846: 9903 ldr r1, [sp, #12] 8013848: 1a5b subs r3, r3, r1 801384a: 42ab cmp r3, r5 801384c: dcf2 bgt.n 8013834 <_printf_i+0x210> 801384e: e7eb b.n 8013828 <_printf_i+0x204> 8013850: 2500 movs r5, #0 8013852: f104 0619 add.w r6, r4, #25 8013856: e7f5 b.n 8013844 <_printf_i+0x220> 8013858: 0801615a .word 0x0801615a 801385c: 0801616b .word 0x0801616b 08013860 : 8013860: 2300 movs r3, #0 8013862: b510 push {r4, lr} 8013864: 4604 mov r4, r0 8013866: e9c0 3300 strd r3, r3, [r0] 801386a: e9c0 3304 strd r3, r3, [r0, #16] 801386e: 6083 str r3, [r0, #8] 8013870: 8181 strh r1, [r0, #12] 8013872: 6643 str r3, [r0, #100] @ 0x64 8013874: 81c2 strh r2, [r0, #14] 8013876: 6183 str r3, [r0, #24] 8013878: 4619 mov r1, r3 801387a: 2208 movs r2, #8 801387c: 305c adds r0, #92 @ 0x5c 801387e: f000 f8ff bl 8013a80 8013882: 4b0d ldr r3, [pc, #52] @ (80138b8 ) 8013884: 6224 str r4, [r4, #32] 8013886: 6263 str r3, [r4, #36] @ 0x24 8013888: 4b0c ldr r3, [pc, #48] @ (80138bc ) 801388a: 62a3 str r3, [r4, #40] @ 0x28 801388c: 4b0c ldr r3, [pc, #48] @ (80138c0 ) 801388e: 62e3 str r3, [r4, #44] @ 0x2c 8013890: 4b0c ldr r3, [pc, #48] @ (80138c4 ) 8013892: 6323 str r3, [r4, #48] @ 0x30 8013894: 4b0c ldr r3, [pc, #48] @ (80138c8 ) 8013896: 429c cmp r4, r3 8013898: d006 beq.n 80138a8 801389a: f103 0268 add.w r2, r3, #104 @ 0x68 801389e: 4294 cmp r4, r2 80138a0: d002 beq.n 80138a8 80138a2: 33d0 adds r3, #208 @ 0xd0 80138a4: 429c cmp r4, r3 80138a6: d105 bne.n 80138b4 80138a8: f104 0058 add.w r0, r4, #88 @ 0x58 80138ac: e8bd 4010 ldmia.w sp!, {r4, lr} 80138b0: f000 b918 b.w 8013ae4 <__retarget_lock_init_recursive> 80138b4: bd10 pop {r4, pc} 80138b6: bf00 nop 80138b8: 08015701 .word 0x08015701 80138bc: 08015723 .word 0x08015723 80138c0: 0801575b .word 0x0801575b 80138c4: 0801577f .word 0x0801577f 80138c8: 200011e0 .word 0x200011e0 080138cc : 80138cc: 4a02 ldr r2, [pc, #8] @ (80138d8 ) 80138ce: 4903 ldr r1, [pc, #12] @ (80138dc ) 80138d0: 4803 ldr r0, [pc, #12] @ (80138e0 ) 80138d2: f000 b8a5 b.w 8013a20 <_fwalk_sglue> 80138d6: bf00 nop 80138d8: 20000078 .word 0x20000078 80138dc: 08014fa5 .word 0x08014fa5 80138e0: 20000088 .word 0x20000088 080138e4 : 80138e4: 6841 ldr r1, [r0, #4] 80138e6: 4b0c ldr r3, [pc, #48] @ (8013918 ) 80138e8: b510 push {r4, lr} 80138ea: 4299 cmp r1, r3 80138ec: 4604 mov r4, r0 80138ee: d001 beq.n 80138f4 80138f0: f001 fb58 bl 8014fa4 <_fflush_r> 80138f4: 68a1 ldr r1, [r4, #8] 80138f6: 4b09 ldr r3, [pc, #36] @ (801391c ) 80138f8: 4299 cmp r1, r3 80138fa: d002 beq.n 8013902 80138fc: 4620 mov r0, r4 80138fe: f001 fb51 bl 8014fa4 <_fflush_r> 8013902: 68e1 ldr r1, [r4, #12] 8013904: 4b06 ldr r3, [pc, #24] @ (8013920 ) 8013906: 4299 cmp r1, r3 8013908: d004 beq.n 8013914 801390a: 4620 mov r0, r4 801390c: e8bd 4010 ldmia.w sp!, {r4, lr} 8013910: f001 bb48 b.w 8014fa4 <_fflush_r> 8013914: bd10 pop {r4, pc} 8013916: bf00 nop 8013918: 200011e0 .word 0x200011e0 801391c: 20001248 .word 0x20001248 8013920: 200012b0 .word 0x200012b0 08013924 : 8013924: b510 push {r4, lr} 8013926: 4b0b ldr r3, [pc, #44] @ (8013954 ) 8013928: 4c0b ldr r4, [pc, #44] @ (8013958 ) 801392a: 4a0c ldr r2, [pc, #48] @ (801395c ) 801392c: 4620 mov r0, r4 801392e: 601a str r2, [r3, #0] 8013930: 2104 movs r1, #4 8013932: 2200 movs r2, #0 8013934: f7ff ff94 bl 8013860 8013938: f104 0068 add.w r0, r4, #104 @ 0x68 801393c: 2201 movs r2, #1 801393e: 2109 movs r1, #9 8013940: f7ff ff8e bl 8013860 8013944: f104 00d0 add.w r0, r4, #208 @ 0xd0 8013948: 2202 movs r2, #2 801394a: e8bd 4010 ldmia.w sp!, {r4, lr} 801394e: 2112 movs r1, #18 8013950: f7ff bf86 b.w 8013860 8013954: 20001318 .word 0x20001318 8013958: 200011e0 .word 0x200011e0 801395c: 080138cd .word 0x080138cd 08013960 <__sfp_lock_acquire>: 8013960: 4801 ldr r0, [pc, #4] @ (8013968 <__sfp_lock_acquire+0x8>) 8013962: f000 b8c0 b.w 8013ae6 <__retarget_lock_acquire_recursive> 8013966: bf00 nop 8013968: 2000131d .word 0x2000131d 0801396c <__sfp_lock_release>: 801396c: 4801 ldr r0, [pc, #4] @ (8013974 <__sfp_lock_release+0x8>) 801396e: f000 b8bb b.w 8013ae8 <__retarget_lock_release_recursive> 8013972: bf00 nop 8013974: 2000131d .word 0x2000131d 08013978 <__sinit>: 8013978: b510 push {r4, lr} 801397a: 4604 mov r4, r0 801397c: f7ff fff0 bl 8013960 <__sfp_lock_acquire> 8013980: 6a23 ldr r3, [r4, #32] 8013982: b11b cbz r3, 801398c <__sinit+0x14> 8013984: e8bd 4010 ldmia.w sp!, {r4, lr} 8013988: f7ff bff0 b.w 801396c <__sfp_lock_release> 801398c: 4b04 ldr r3, [pc, #16] @ (80139a0 <__sinit+0x28>) 801398e: 6223 str r3, [r4, #32] 8013990: 4b04 ldr r3, [pc, #16] @ (80139a4 <__sinit+0x2c>) 8013992: 681b ldr r3, [r3, #0] 8013994: 2b00 cmp r3, #0 8013996: d1f5 bne.n 8013984 <__sinit+0xc> 8013998: f7ff ffc4 bl 8013924 801399c: e7f2 b.n 8013984 <__sinit+0xc> 801399e: bf00 nop 80139a0: 080138e5 .word 0x080138e5 80139a4: 20001318 .word 0x20001318 080139a8 <_vsniprintf_r>: 80139a8: b530 push {r4, r5, lr} 80139aa: 4614 mov r4, r2 80139ac: 2c00 cmp r4, #0 80139ae: 4605 mov r5, r0 80139b0: 461a mov r2, r3 80139b2: b09b sub sp, #108 @ 0x6c 80139b4: da05 bge.n 80139c2 <_vsniprintf_r+0x1a> 80139b6: 238b movs r3, #139 @ 0x8b 80139b8: 6003 str r3, [r0, #0] 80139ba: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80139be: b01b add sp, #108 @ 0x6c 80139c0: bd30 pop {r4, r5, pc} 80139c2: f44f 7302 mov.w r3, #520 @ 0x208 80139c6: f8ad 300c strh.w r3, [sp, #12] 80139ca: f04f 0300 mov.w r3, #0 80139ce: 9319 str r3, [sp, #100] @ 0x64 80139d0: bf0c ite eq 80139d2: 4623 moveq r3, r4 80139d4: f104 33ff addne.w r3, r4, #4294967295 @ 0xffffffff 80139d8: 9302 str r3, [sp, #8] 80139da: 9305 str r3, [sp, #20] 80139dc: f64f 73ff movw r3, #65535 @ 0xffff 80139e0: 9100 str r1, [sp, #0] 80139e2: 9104 str r1, [sp, #16] 80139e4: f8ad 300e strh.w r3, [sp, #14] 80139e8: 4669 mov r1, sp 80139ea: 9b1e ldr r3, [sp, #120] @ 0x78 80139ec: f000 ff74 bl 80148d8 <_svfiprintf_r> 80139f0: 1c43 adds r3, r0, #1 80139f2: bfbc itt lt 80139f4: 238b movlt r3, #139 @ 0x8b 80139f6: 602b strlt r3, [r5, #0] 80139f8: 2c00 cmp r4, #0 80139fa: d0e0 beq.n 80139be <_vsniprintf_r+0x16> 80139fc: 2200 movs r2, #0 80139fe: 9b00 ldr r3, [sp, #0] 8013a00: 701a strb r2, [r3, #0] 8013a02: e7dc b.n 80139be <_vsniprintf_r+0x16> 08013a04 : 8013a04: b507 push {r0, r1, r2, lr} 8013a06: 9300 str r3, [sp, #0] 8013a08: 4613 mov r3, r2 8013a0a: 460a mov r2, r1 8013a0c: 4601 mov r1, r0 8013a0e: 4803 ldr r0, [pc, #12] @ (8013a1c ) 8013a10: 6800 ldr r0, [r0, #0] 8013a12: f7ff ffc9 bl 80139a8 <_vsniprintf_r> 8013a16: b003 add sp, #12 8013a18: f85d fb04 ldr.w pc, [sp], #4 8013a1c: 20000084 .word 0x20000084 08013a20 <_fwalk_sglue>: 8013a20: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8013a24: 4607 mov r7, r0 8013a26: 4688 mov r8, r1 8013a28: 4614 mov r4, r2 8013a2a: 2600 movs r6, #0 8013a2c: e9d4 9501 ldrd r9, r5, [r4, #4] 8013a30: f1b9 0901 subs.w r9, r9, #1 8013a34: d505 bpl.n 8013a42 <_fwalk_sglue+0x22> 8013a36: 6824 ldr r4, [r4, #0] 8013a38: 2c00 cmp r4, #0 8013a3a: d1f7 bne.n 8013a2c <_fwalk_sglue+0xc> 8013a3c: 4630 mov r0, r6 8013a3e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8013a42: 89ab ldrh r3, [r5, #12] 8013a44: 2b01 cmp r3, #1 8013a46: d907 bls.n 8013a58 <_fwalk_sglue+0x38> 8013a48: f9b5 300e ldrsh.w r3, [r5, #14] 8013a4c: 3301 adds r3, #1 8013a4e: d003 beq.n 8013a58 <_fwalk_sglue+0x38> 8013a50: 4629 mov r1, r5 8013a52: 4638 mov r0, r7 8013a54: 47c0 blx r8 8013a56: 4306 orrs r6, r0 8013a58: 3568 adds r5, #104 @ 0x68 8013a5a: e7e9 b.n 8013a30 <_fwalk_sglue+0x10> 08013a5c : 8013a5c: b40f push {r0, r1, r2, r3} 8013a5e: b507 push {r0, r1, r2, lr} 8013a60: 4906 ldr r1, [pc, #24] @ (8013a7c ) 8013a62: ab04 add r3, sp, #16 8013a64: 6808 ldr r0, [r1, #0] 8013a66: f853 2b04 ldr.w r2, [r3], #4 8013a6a: 6881 ldr r1, [r0, #8] 8013a6c: 9301 str r3, [sp, #4] 8013a6e: f001 f857 bl 8014b20 <_vfiprintf_r> 8013a72: b003 add sp, #12 8013a74: f85d eb04 ldr.w lr, [sp], #4 8013a78: b004 add sp, #16 8013a7a: 4770 bx lr 8013a7c: 20000084 .word 0x20000084 08013a80 : 8013a80: 4603 mov r3, r0 8013a82: 4402 add r2, r0 8013a84: 4293 cmp r3, r2 8013a86: d100 bne.n 8013a8a 8013a88: 4770 bx lr 8013a8a: f803 1b01 strb.w r1, [r3], #1 8013a8e: e7f9 b.n 8013a84 08013a90 <__errno>: 8013a90: 4b01 ldr r3, [pc, #4] @ (8013a98 <__errno+0x8>) 8013a92: 6818 ldr r0, [r3, #0] 8013a94: 4770 bx lr 8013a96: bf00 nop 8013a98: 20000084 .word 0x20000084 08013a9c <__libc_init_array>: 8013a9c: b570 push {r4, r5, r6, lr} 8013a9e: 2600 movs r6, #0 8013aa0: 4d0c ldr r5, [pc, #48] @ (8013ad4 <__libc_init_array+0x38>) 8013aa2: 4c0d ldr r4, [pc, #52] @ (8013ad8 <__libc_init_array+0x3c>) 8013aa4: 1b64 subs r4, r4, r5 8013aa6: 10a4 asrs r4, r4, #2 8013aa8: 42a6 cmp r6, r4 8013aaa: d109 bne.n 8013ac0 <__libc_init_array+0x24> 8013aac: f002 f904 bl 8015cb8 <_init> 8013ab0: 2600 movs r6, #0 8013ab2: 4d0a ldr r5, [pc, #40] @ (8013adc <__libc_init_array+0x40>) 8013ab4: 4c0a ldr r4, [pc, #40] @ (8013ae0 <__libc_init_array+0x44>) 8013ab6: 1b64 subs r4, r4, r5 8013ab8: 10a4 asrs r4, r4, #2 8013aba: 42a6 cmp r6, r4 8013abc: d105 bne.n 8013aca <__libc_init_array+0x2e> 8013abe: bd70 pop {r4, r5, r6, pc} 8013ac0: f855 3b04 ldr.w r3, [r5], #4 8013ac4: 4798 blx r3 8013ac6: 3601 adds r6, #1 8013ac8: e7ee b.n 8013aa8 <__libc_init_array+0xc> 8013aca: f855 3b04 ldr.w r3, [r5], #4 8013ace: 4798 blx r3 8013ad0: 3601 adds r6, #1 8013ad2: e7f2 b.n 8013aba <__libc_init_array+0x1e> 8013ad4: 080164c4 .word 0x080164c4 8013ad8: 080164c4 .word 0x080164c4 8013adc: 080164c4 .word 0x080164c4 8013ae0: 080164c8 .word 0x080164c8 08013ae4 <__retarget_lock_init_recursive>: 8013ae4: 4770 bx lr 08013ae6 <__retarget_lock_acquire_recursive>: 8013ae6: 4770 bx lr 08013ae8 <__retarget_lock_release_recursive>: 8013ae8: 4770 bx lr ... 08013aec <_localeconv_r>: 8013aec: 4800 ldr r0, [pc, #0] @ (8013af0 <_localeconv_r+0x4>) 8013aee: 4770 bx lr 8013af0: 200001c4 .word 0x200001c4 08013af4 : 8013af4: 4603 mov r3, r0 8013af6: b510 push {r4, lr} 8013af8: b2c9 uxtb r1, r1 8013afa: 4402 add r2, r0 8013afc: 4293 cmp r3, r2 8013afe: 4618 mov r0, r3 8013b00: d101 bne.n 8013b06 8013b02: 2000 movs r0, #0 8013b04: e003 b.n 8013b0e 8013b06: 7804 ldrb r4, [r0, #0] 8013b08: 3301 adds r3, #1 8013b0a: 428c cmp r4, r1 8013b0c: d1f6 bne.n 8013afc 8013b0e: bd10 pop {r4, pc} 08013b10 : 8013b10: 440a add r2, r1 8013b12: 4291 cmp r1, r2 8013b14: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8013b18: d100 bne.n 8013b1c 8013b1a: 4770 bx lr 8013b1c: b510 push {r4, lr} 8013b1e: f811 4b01 ldrb.w r4, [r1], #1 8013b22: 4291 cmp r1, r2 8013b24: f803 4f01 strb.w r4, [r3, #1]! 8013b28: d1f9 bne.n 8013b1e 8013b2a: bd10 pop {r4, pc} 08013b2c <__assert_func>: 8013b2c: b51f push {r0, r1, r2, r3, r4, lr} 8013b2e: 4614 mov r4, r2 8013b30: 461a mov r2, r3 8013b32: 4b09 ldr r3, [pc, #36] @ (8013b58 <__assert_func+0x2c>) 8013b34: 4605 mov r5, r0 8013b36: 681b ldr r3, [r3, #0] 8013b38: 68d8 ldr r0, [r3, #12] 8013b3a: b14c cbz r4, 8013b50 <__assert_func+0x24> 8013b3c: 4b07 ldr r3, [pc, #28] @ (8013b5c <__assert_func+0x30>) 8013b3e: e9cd 3401 strd r3, r4, [sp, #4] 8013b42: 9100 str r1, [sp, #0] 8013b44: 462b mov r3, r5 8013b46: 4906 ldr r1, [pc, #24] @ (8013b60 <__assert_func+0x34>) 8013b48: f001 fe1e bl 8015788 8013b4c: f001 ffe4 bl 8015b18 8013b50: 4b04 ldr r3, [pc, #16] @ (8013b64 <__assert_func+0x38>) 8013b52: 461c mov r4, r3 8013b54: e7f3 b.n 8013b3e <__assert_func+0x12> 8013b56: bf00 nop 8013b58: 20000084 .word 0x20000084 8013b5c: 0801617c .word 0x0801617c 8013b60: 08016189 .word 0x08016189 8013b64: 080161b7 .word 0x080161b7 08013b68 : 8013b68: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8013b6c: 6903 ldr r3, [r0, #16] 8013b6e: 690c ldr r4, [r1, #16] 8013b70: 4607 mov r7, r0 8013b72: 42a3 cmp r3, r4 8013b74: db7e blt.n 8013c74 8013b76: 3c01 subs r4, #1 8013b78: 00a3 lsls r3, r4, #2 8013b7a: f100 0514 add.w r5, r0, #20 8013b7e: f101 0814 add.w r8, r1, #20 8013b82: 9300 str r3, [sp, #0] 8013b84: eb05 0384 add.w r3, r5, r4, lsl #2 8013b88: 9301 str r3, [sp, #4] 8013b8a: f858 3024 ldr.w r3, [r8, r4, lsl #2] 8013b8e: f855 2024 ldr.w r2, [r5, r4, lsl #2] 8013b92: 3301 adds r3, #1 8013b94: 429a cmp r2, r3 8013b96: fbb2 f6f3 udiv r6, r2, r3 8013b9a: eb08 0984 add.w r9, r8, r4, lsl #2 8013b9e: d32e bcc.n 8013bfe 8013ba0: f04f 0a00 mov.w sl, #0 8013ba4: 46c4 mov ip, r8 8013ba6: 46ae mov lr, r5 8013ba8: 46d3 mov fp, sl 8013baa: f85c 3b04 ldr.w r3, [ip], #4 8013bae: b298 uxth r0, r3 8013bb0: fb06 a000 mla r0, r6, r0, sl 8013bb4: 0c1b lsrs r3, r3, #16 8013bb6: 0c02 lsrs r2, r0, #16 8013bb8: fb06 2303 mla r3, r6, r3, r2 8013bbc: f8de 2000 ldr.w r2, [lr] 8013bc0: b280 uxth r0, r0 8013bc2: b292 uxth r2, r2 8013bc4: 1a12 subs r2, r2, r0 8013bc6: 445a add r2, fp 8013bc8: f8de 0000 ldr.w r0, [lr] 8013bcc: ea4f 4a13 mov.w sl, r3, lsr #16 8013bd0: b29b uxth r3, r3 8013bd2: ebc3 4322 rsb r3, r3, r2, asr #16 8013bd6: eb03 4310 add.w r3, r3, r0, lsr #16 8013bda: b292 uxth r2, r2 8013bdc: ea42 4203 orr.w r2, r2, r3, lsl #16 8013be0: 45e1 cmp r9, ip 8013be2: ea4f 4b23 mov.w fp, r3, asr #16 8013be6: f84e 2b04 str.w r2, [lr], #4 8013bea: d2de bcs.n 8013baa 8013bec: 9b00 ldr r3, [sp, #0] 8013bee: 58eb ldr r3, [r5, r3] 8013bf0: b92b cbnz r3, 8013bfe 8013bf2: 9b01 ldr r3, [sp, #4] 8013bf4: 3b04 subs r3, #4 8013bf6: 429d cmp r5, r3 8013bf8: 461a mov r2, r3 8013bfa: d32f bcc.n 8013c5c 8013bfc: 613c str r4, [r7, #16] 8013bfe: 4638 mov r0, r7 8013c00: f001 fc76 bl 80154f0 <__mcmp> 8013c04: 2800 cmp r0, #0 8013c06: db25 blt.n 8013c54 8013c08: 4629 mov r1, r5 8013c0a: 2000 movs r0, #0 8013c0c: f858 2b04 ldr.w r2, [r8], #4 8013c10: f8d1 c000 ldr.w ip, [r1] 8013c14: fa1f fe82 uxth.w lr, r2 8013c18: fa1f f38c uxth.w r3, ip 8013c1c: eba3 030e sub.w r3, r3, lr 8013c20: 4403 add r3, r0 8013c22: 0c12 lsrs r2, r2, #16 8013c24: ebc2 4223 rsb r2, r2, r3, asr #16 8013c28: eb02 421c add.w r2, r2, ip, lsr #16 8013c2c: b29b uxth r3, r3 8013c2e: ea43 4302 orr.w r3, r3, r2, lsl #16 8013c32: 45c1 cmp r9, r8 8013c34: ea4f 4022 mov.w r0, r2, asr #16 8013c38: f841 3b04 str.w r3, [r1], #4 8013c3c: d2e6 bcs.n 8013c0c 8013c3e: f855 2024 ldr.w r2, [r5, r4, lsl #2] 8013c42: eb05 0384 add.w r3, r5, r4, lsl #2 8013c46: b922 cbnz r2, 8013c52 8013c48: 3b04 subs r3, #4 8013c4a: 429d cmp r5, r3 8013c4c: 461a mov r2, r3 8013c4e: d30b bcc.n 8013c68 8013c50: 613c str r4, [r7, #16] 8013c52: 3601 adds r6, #1 8013c54: 4630 mov r0, r6 8013c56: b003 add sp, #12 8013c58: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8013c5c: 6812 ldr r2, [r2, #0] 8013c5e: 3b04 subs r3, #4 8013c60: 2a00 cmp r2, #0 8013c62: d1cb bne.n 8013bfc 8013c64: 3c01 subs r4, #1 8013c66: e7c6 b.n 8013bf6 8013c68: 6812 ldr r2, [r2, #0] 8013c6a: 3b04 subs r3, #4 8013c6c: 2a00 cmp r2, #0 8013c6e: d1ef bne.n 8013c50 8013c70: 3c01 subs r4, #1 8013c72: e7ea b.n 8013c4a 8013c74: 2000 movs r0, #0 8013c76: e7ee b.n 8013c56 08013c78 <_dtoa_r>: 8013c78: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8013c7c: 4614 mov r4, r2 8013c7e: 461d mov r5, r3 8013c80: 69c7 ldr r7, [r0, #28] 8013c82: b097 sub sp, #92 @ 0x5c 8013c84: 4681 mov r9, r0 8013c86: e9cd 4506 strd r4, r5, [sp, #24] 8013c8a: 9e23 ldr r6, [sp, #140] @ 0x8c 8013c8c: b97f cbnz r7, 8013cae <_dtoa_r+0x36> 8013c8e: 2010 movs r0, #16 8013c90: f001 f85e bl 8014d50 8013c94: 4602 mov r2, r0 8013c96: f8c9 001c str.w r0, [r9, #28] 8013c9a: b920 cbnz r0, 8013ca6 <_dtoa_r+0x2e> 8013c9c: 21ef movs r1, #239 @ 0xef 8013c9e: 4bac ldr r3, [pc, #688] @ (8013f50 <_dtoa_r+0x2d8>) 8013ca0: 48ac ldr r0, [pc, #688] @ (8013f54 <_dtoa_r+0x2dc>) 8013ca2: f7ff ff43 bl 8013b2c <__assert_func> 8013ca6: e9c0 7701 strd r7, r7, [r0, #4] 8013caa: 6007 str r7, [r0, #0] 8013cac: 60c7 str r7, [r0, #12] 8013cae: f8d9 301c ldr.w r3, [r9, #28] 8013cb2: 6819 ldr r1, [r3, #0] 8013cb4: b159 cbz r1, 8013cce <_dtoa_r+0x56> 8013cb6: 685a ldr r2, [r3, #4] 8013cb8: 2301 movs r3, #1 8013cba: 4093 lsls r3, r2 8013cbc: 604a str r2, [r1, #4] 8013cbe: 608b str r3, [r1, #8] 8013cc0: 4648 mov r0, r9 8013cc2: f001 f9e3 bl 801508c <_Bfree> 8013cc6: 2200 movs r2, #0 8013cc8: f8d9 301c ldr.w r3, [r9, #28] 8013ccc: 601a str r2, [r3, #0] 8013cce: 1e2b subs r3, r5, #0 8013cd0: bfaf iteee ge 8013cd2: 2300 movge r3, #0 8013cd4: 2201 movlt r2, #1 8013cd6: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000 8013cda: 9307 strlt r3, [sp, #28] 8013cdc: bfa8 it ge 8013cde: 6033 strge r3, [r6, #0] 8013ce0: f8dd 801c ldr.w r8, [sp, #28] 8013ce4: 4b9c ldr r3, [pc, #624] @ (8013f58 <_dtoa_r+0x2e0>) 8013ce6: bfb8 it lt 8013ce8: 6032 strlt r2, [r6, #0] 8013cea: ea33 0308 bics.w r3, r3, r8 8013cee: d112 bne.n 8013d16 <_dtoa_r+0x9e> 8013cf0: f242 730f movw r3, #9999 @ 0x270f 8013cf4: 9a22 ldr r2, [sp, #136] @ 0x88 8013cf6: 6013 str r3, [r2, #0] 8013cf8: f3c8 0313 ubfx r3, r8, #0, #20 8013cfc: 4323 orrs r3, r4 8013cfe: f000 855e beq.w 80147be <_dtoa_r+0xb46> 8013d02: 9b24 ldr r3, [sp, #144] @ 0x90 8013d04: f8df a254 ldr.w sl, [pc, #596] @ 8013f5c <_dtoa_r+0x2e4> 8013d08: 2b00 cmp r3, #0 8013d0a: f000 8560 beq.w 80147ce <_dtoa_r+0xb56> 8013d0e: f10a 0303 add.w r3, sl, #3 8013d12: f000 bd5a b.w 80147ca <_dtoa_r+0xb52> 8013d16: e9dd 2306 ldrd r2, r3, [sp, #24] 8013d1a: e9cd 230c strd r2, r3, [sp, #48] @ 0x30 8013d1e: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8013d22: 2200 movs r2, #0 8013d24: 2300 movs r3, #0 8013d26: f7f4 feab bl 8008a80 <__aeabi_dcmpeq> 8013d2a: 4607 mov r7, r0 8013d2c: b158 cbz r0, 8013d46 <_dtoa_r+0xce> 8013d2e: 2301 movs r3, #1 8013d30: 9a22 ldr r2, [sp, #136] @ 0x88 8013d32: 6013 str r3, [r2, #0] 8013d34: 9b24 ldr r3, [sp, #144] @ 0x90 8013d36: b113 cbz r3, 8013d3e <_dtoa_r+0xc6> 8013d38: 4b89 ldr r3, [pc, #548] @ (8013f60 <_dtoa_r+0x2e8>) 8013d3a: 9a24 ldr r2, [sp, #144] @ 0x90 8013d3c: 6013 str r3, [r2, #0] 8013d3e: f8df a224 ldr.w sl, [pc, #548] @ 8013f64 <_dtoa_r+0x2ec> 8013d42: f000 bd44 b.w 80147ce <_dtoa_r+0xb56> 8013d46: ab14 add r3, sp, #80 @ 0x50 8013d48: 9301 str r3, [sp, #4] 8013d4a: ab15 add r3, sp, #84 @ 0x54 8013d4c: 9300 str r3, [sp, #0] 8013d4e: 4648 mov r0, r9 8013d50: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30 8013d54: f001 fc7c bl 8015650 <__d2b> 8013d58: f3c8 560a ubfx r6, r8, #20, #11 8013d5c: 9003 str r0, [sp, #12] 8013d5e: 2e00 cmp r6, #0 8013d60: d078 beq.n 8013e54 <_dtoa_r+0x1dc> 8013d62: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8013d66: 9b0d ldr r3, [sp, #52] @ 0x34 8013d68: f2a6 36ff subw r6, r6, #1023 @ 0x3ff 8013d6c: f3c3 0313 ubfx r3, r3, #0, #20 8013d70: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000 8013d74: f443 1340 orr.w r3, r3, #3145728 @ 0x300000 8013d78: 9712 str r7, [sp, #72] @ 0x48 8013d7a: 4619 mov r1, r3 8013d7c: 2200 movs r2, #0 8013d7e: 4b7a ldr r3, [pc, #488] @ (8013f68 <_dtoa_r+0x2f0>) 8013d80: f7f4 fa5e bl 8008240 <__aeabi_dsub> 8013d84: a36c add r3, pc, #432 @ (adr r3, 8013f38 <_dtoa_r+0x2c0>) 8013d86: e9d3 2300 ldrd r2, r3, [r3] 8013d8a: f7f4 fc11 bl 80085b0 <__aeabi_dmul> 8013d8e: a36c add r3, pc, #432 @ (adr r3, 8013f40 <_dtoa_r+0x2c8>) 8013d90: e9d3 2300 ldrd r2, r3, [r3] 8013d94: f7f4 fa56 bl 8008244 <__adddf3> 8013d98: 4604 mov r4, r0 8013d9a: 4630 mov r0, r6 8013d9c: 460d mov r5, r1 8013d9e: f7f4 fb9d bl 80084dc <__aeabi_i2d> 8013da2: a369 add r3, pc, #420 @ (adr r3, 8013f48 <_dtoa_r+0x2d0>) 8013da4: e9d3 2300 ldrd r2, r3, [r3] 8013da8: f7f4 fc02 bl 80085b0 <__aeabi_dmul> 8013dac: 4602 mov r2, r0 8013dae: 460b mov r3, r1 8013db0: 4620 mov r0, r4 8013db2: 4629 mov r1, r5 8013db4: f7f4 fa46 bl 8008244 <__adddf3> 8013db8: 4604 mov r4, r0 8013dba: 460d mov r5, r1 8013dbc: f7f4 fea8 bl 8008b10 <__aeabi_d2iz> 8013dc0: 2200 movs r2, #0 8013dc2: 4607 mov r7, r0 8013dc4: 2300 movs r3, #0 8013dc6: 4620 mov r0, r4 8013dc8: 4629 mov r1, r5 8013dca: f7f4 fe63 bl 8008a94 <__aeabi_dcmplt> 8013dce: b140 cbz r0, 8013de2 <_dtoa_r+0x16a> 8013dd0: 4638 mov r0, r7 8013dd2: f7f4 fb83 bl 80084dc <__aeabi_i2d> 8013dd6: 4622 mov r2, r4 8013dd8: 462b mov r3, r5 8013dda: f7f4 fe51 bl 8008a80 <__aeabi_dcmpeq> 8013dde: b900 cbnz r0, 8013de2 <_dtoa_r+0x16a> 8013de0: 3f01 subs r7, #1 8013de2: 2f16 cmp r7, #22 8013de4: d854 bhi.n 8013e90 <_dtoa_r+0x218> 8013de6: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8013dea: 4b60 ldr r3, [pc, #384] @ (8013f6c <_dtoa_r+0x2f4>) 8013dec: eb03 03c7 add.w r3, r3, r7, lsl #3 8013df0: e9d3 2300 ldrd r2, r3, [r3] 8013df4: f7f4 fe4e bl 8008a94 <__aeabi_dcmplt> 8013df8: 2800 cmp r0, #0 8013dfa: d04b beq.n 8013e94 <_dtoa_r+0x21c> 8013dfc: 2300 movs r3, #0 8013dfe: 3f01 subs r7, #1 8013e00: 930f str r3, [sp, #60] @ 0x3c 8013e02: 9b14 ldr r3, [sp, #80] @ 0x50 8013e04: 1b9b subs r3, r3, r6 8013e06: 1e5a subs r2, r3, #1 8013e08: bf49 itett mi 8013e0a: f1c3 0301 rsbmi r3, r3, #1 8013e0e: 2300 movpl r3, #0 8013e10: 9304 strmi r3, [sp, #16] 8013e12: 2300 movmi r3, #0 8013e14: 9209 str r2, [sp, #36] @ 0x24 8013e16: bf54 ite pl 8013e18: 9304 strpl r3, [sp, #16] 8013e1a: 9309 strmi r3, [sp, #36] @ 0x24 8013e1c: 2f00 cmp r7, #0 8013e1e: db3b blt.n 8013e98 <_dtoa_r+0x220> 8013e20: 9b09 ldr r3, [sp, #36] @ 0x24 8013e22: 970e str r7, [sp, #56] @ 0x38 8013e24: 443b add r3, r7 8013e26: 9309 str r3, [sp, #36] @ 0x24 8013e28: 2300 movs r3, #0 8013e2a: 930a str r3, [sp, #40] @ 0x28 8013e2c: 9b20 ldr r3, [sp, #128] @ 0x80 8013e2e: 2b09 cmp r3, #9 8013e30: d865 bhi.n 8013efe <_dtoa_r+0x286> 8013e32: 2b05 cmp r3, #5 8013e34: bfc4 itt gt 8013e36: 3b04 subgt r3, #4 8013e38: 9320 strgt r3, [sp, #128] @ 0x80 8013e3a: 9b20 ldr r3, [sp, #128] @ 0x80 8013e3c: bfc8 it gt 8013e3e: 2400 movgt r4, #0 8013e40: f1a3 0302 sub.w r3, r3, #2 8013e44: bfd8 it le 8013e46: 2401 movle r4, #1 8013e48: 2b03 cmp r3, #3 8013e4a: d864 bhi.n 8013f16 <_dtoa_r+0x29e> 8013e4c: e8df f003 tbb [pc, r3] 8013e50: 2c385553 .word 0x2c385553 8013e54: e9dd 6314 ldrd r6, r3, [sp, #80] @ 0x50 8013e58: 441e add r6, r3 8013e5a: f206 4332 addw r3, r6, #1074 @ 0x432 8013e5e: 2b20 cmp r3, #32 8013e60: bfc1 itttt gt 8013e62: f1c3 0340 rsbgt r3, r3, #64 @ 0x40 8013e66: fa08 f803 lslgt.w r8, r8, r3 8013e6a: f206 4312 addwgt r3, r6, #1042 @ 0x412 8013e6e: fa24 f303 lsrgt.w r3, r4, r3 8013e72: bfd6 itet le 8013e74: f1c3 0320 rsble r3, r3, #32 8013e78: ea48 0003 orrgt.w r0, r8, r3 8013e7c: fa04 f003 lslle.w r0, r4, r3 8013e80: f7f4 fb1c bl 80084bc <__aeabi_ui2d> 8013e84: 2201 movs r2, #1 8013e86: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000 8013e8a: 3e01 subs r6, #1 8013e8c: 9212 str r2, [sp, #72] @ 0x48 8013e8e: e774 b.n 8013d7a <_dtoa_r+0x102> 8013e90: 2301 movs r3, #1 8013e92: e7b5 b.n 8013e00 <_dtoa_r+0x188> 8013e94: 900f str r0, [sp, #60] @ 0x3c 8013e96: e7b4 b.n 8013e02 <_dtoa_r+0x18a> 8013e98: 9b04 ldr r3, [sp, #16] 8013e9a: 1bdb subs r3, r3, r7 8013e9c: 9304 str r3, [sp, #16] 8013e9e: 427b negs r3, r7 8013ea0: 930a str r3, [sp, #40] @ 0x28 8013ea2: 2300 movs r3, #0 8013ea4: 930e str r3, [sp, #56] @ 0x38 8013ea6: e7c1 b.n 8013e2c <_dtoa_r+0x1b4> 8013ea8: 2301 movs r3, #1 8013eaa: 930b str r3, [sp, #44] @ 0x2c 8013eac: 9b21 ldr r3, [sp, #132] @ 0x84 8013eae: eb07 0b03 add.w fp, r7, r3 8013eb2: f10b 0301 add.w r3, fp, #1 8013eb6: 2b01 cmp r3, #1 8013eb8: 9308 str r3, [sp, #32] 8013eba: bfb8 it lt 8013ebc: 2301 movlt r3, #1 8013ebe: e006 b.n 8013ece <_dtoa_r+0x256> 8013ec0: 2301 movs r3, #1 8013ec2: 930b str r3, [sp, #44] @ 0x2c 8013ec4: 9b21 ldr r3, [sp, #132] @ 0x84 8013ec6: 2b00 cmp r3, #0 8013ec8: dd28 ble.n 8013f1c <_dtoa_r+0x2a4> 8013eca: 469b mov fp, r3 8013ecc: 9308 str r3, [sp, #32] 8013ece: 2100 movs r1, #0 8013ed0: 2204 movs r2, #4 8013ed2: f8d9 001c ldr.w r0, [r9, #28] 8013ed6: f102 0514 add.w r5, r2, #20 8013eda: 429d cmp r5, r3 8013edc: d926 bls.n 8013f2c <_dtoa_r+0x2b4> 8013ede: 6041 str r1, [r0, #4] 8013ee0: 4648 mov r0, r9 8013ee2: f001 f893 bl 801500c <_Balloc> 8013ee6: 4682 mov sl, r0 8013ee8: 2800 cmp r0, #0 8013eea: d143 bne.n 8013f74 <_dtoa_r+0x2fc> 8013eec: 4602 mov r2, r0 8013eee: f240 11af movw r1, #431 @ 0x1af 8013ef2: 4b1f ldr r3, [pc, #124] @ (8013f70 <_dtoa_r+0x2f8>) 8013ef4: e6d4 b.n 8013ca0 <_dtoa_r+0x28> 8013ef6: 2300 movs r3, #0 8013ef8: e7e3 b.n 8013ec2 <_dtoa_r+0x24a> 8013efa: 2300 movs r3, #0 8013efc: e7d5 b.n 8013eaa <_dtoa_r+0x232> 8013efe: 2401 movs r4, #1 8013f00: 2300 movs r3, #0 8013f02: 940b str r4, [sp, #44] @ 0x2c 8013f04: 9320 str r3, [sp, #128] @ 0x80 8013f06: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff 8013f0a: 2200 movs r2, #0 8013f0c: 2312 movs r3, #18 8013f0e: f8cd b020 str.w fp, [sp, #32] 8013f12: 9221 str r2, [sp, #132] @ 0x84 8013f14: e7db b.n 8013ece <_dtoa_r+0x256> 8013f16: 2301 movs r3, #1 8013f18: 930b str r3, [sp, #44] @ 0x2c 8013f1a: e7f4 b.n 8013f06 <_dtoa_r+0x28e> 8013f1c: f04f 0b01 mov.w fp, #1 8013f20: 465b mov r3, fp 8013f22: f8cd b020 str.w fp, [sp, #32] 8013f26: f8cd b084 str.w fp, [sp, #132] @ 0x84 8013f2a: e7d0 b.n 8013ece <_dtoa_r+0x256> 8013f2c: 3101 adds r1, #1 8013f2e: 0052 lsls r2, r2, #1 8013f30: e7d1 b.n 8013ed6 <_dtoa_r+0x25e> 8013f32: bf00 nop 8013f34: f3af 8000 nop.w 8013f38: 636f4361 .word 0x636f4361 8013f3c: 3fd287a7 .word 0x3fd287a7 8013f40: 8b60c8b3 .word 0x8b60c8b3 8013f44: 3fc68a28 .word 0x3fc68a28 8013f48: 509f79fb .word 0x509f79fb 8013f4c: 3fd34413 .word 0x3fd34413 8013f50: 080161c5 .word 0x080161c5 8013f54: 080161dc .word 0x080161dc 8013f58: 7ff00000 .word 0x7ff00000 8013f5c: 080161c1 .word 0x080161c1 8013f60: 08016159 .word 0x08016159 8013f64: 08016158 .word 0x08016158 8013f68: 3ff80000 .word 0x3ff80000 8013f6c: 080162f0 .word 0x080162f0 8013f70: 08016234 .word 0x08016234 8013f74: f8d9 301c ldr.w r3, [r9, #28] 8013f78: 6018 str r0, [r3, #0] 8013f7a: 9b08 ldr r3, [sp, #32] 8013f7c: 2b0e cmp r3, #14 8013f7e: f200 80a1 bhi.w 80140c4 <_dtoa_r+0x44c> 8013f82: 2c00 cmp r4, #0 8013f84: f000 809e beq.w 80140c4 <_dtoa_r+0x44c> 8013f88: 2f00 cmp r7, #0 8013f8a: dd33 ble.n 8013ff4 <_dtoa_r+0x37c> 8013f8c: 4b9c ldr r3, [pc, #624] @ (8014200 <_dtoa_r+0x588>) 8013f8e: f007 020f and.w r2, r7, #15 8013f92: eb03 03c2 add.w r3, r3, r2, lsl #3 8013f96: 05f8 lsls r0, r7, #23 8013f98: e9d3 3400 ldrd r3, r4, [r3] 8013f9c: e9cd 3410 strd r3, r4, [sp, #64] @ 0x40 8013fa0: ea4f 1427 mov.w r4, r7, asr #4 8013fa4: d516 bpl.n 8013fd4 <_dtoa_r+0x35c> 8013fa6: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8013faa: 4b96 ldr r3, [pc, #600] @ (8014204 <_dtoa_r+0x58c>) 8013fac: 2603 movs r6, #3 8013fae: e9d3 2308 ldrd r2, r3, [r3, #32] 8013fb2: f7f4 fc27 bl 8008804 <__aeabi_ddiv> 8013fb6: e9cd 0106 strd r0, r1, [sp, #24] 8013fba: f004 040f and.w r4, r4, #15 8013fbe: 4d91 ldr r5, [pc, #580] @ (8014204 <_dtoa_r+0x58c>) 8013fc0: b954 cbnz r4, 8013fd8 <_dtoa_r+0x360> 8013fc2: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8013fc6: e9dd 0106 ldrd r0, r1, [sp, #24] 8013fca: f7f4 fc1b bl 8008804 <__aeabi_ddiv> 8013fce: e9cd 0106 strd r0, r1, [sp, #24] 8013fd2: e028 b.n 8014026 <_dtoa_r+0x3ae> 8013fd4: 2602 movs r6, #2 8013fd6: e7f2 b.n 8013fbe <_dtoa_r+0x346> 8013fd8: 07e1 lsls r1, r4, #31 8013fda: d508 bpl.n 8013fee <_dtoa_r+0x376> 8013fdc: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8013fe0: e9d5 2300 ldrd r2, r3, [r5] 8013fe4: f7f4 fae4 bl 80085b0 <__aeabi_dmul> 8013fe8: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 8013fec: 3601 adds r6, #1 8013fee: 1064 asrs r4, r4, #1 8013ff0: 3508 adds r5, #8 8013ff2: e7e5 b.n 8013fc0 <_dtoa_r+0x348> 8013ff4: f000 80af beq.w 8014156 <_dtoa_r+0x4de> 8013ff8: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8013ffc: 427c negs r4, r7 8013ffe: 4b80 ldr r3, [pc, #512] @ (8014200 <_dtoa_r+0x588>) 8014000: f004 020f and.w r2, r4, #15 8014004: eb03 03c2 add.w r3, r3, r2, lsl #3 8014008: e9d3 2300 ldrd r2, r3, [r3] 801400c: f7f4 fad0 bl 80085b0 <__aeabi_dmul> 8014010: 2602 movs r6, #2 8014012: 2300 movs r3, #0 8014014: e9cd 0106 strd r0, r1, [sp, #24] 8014018: 4d7a ldr r5, [pc, #488] @ (8014204 <_dtoa_r+0x58c>) 801401a: 1124 asrs r4, r4, #4 801401c: 2c00 cmp r4, #0 801401e: f040 808f bne.w 8014140 <_dtoa_r+0x4c8> 8014022: 2b00 cmp r3, #0 8014024: d1d3 bne.n 8013fce <_dtoa_r+0x356> 8014026: e9dd 4506 ldrd r4, r5, [sp, #24] 801402a: 9b0f ldr r3, [sp, #60] @ 0x3c 801402c: 2b00 cmp r3, #0 801402e: f000 8094 beq.w 801415a <_dtoa_r+0x4e2> 8014032: 2200 movs r2, #0 8014034: 4620 mov r0, r4 8014036: 4629 mov r1, r5 8014038: 4b73 ldr r3, [pc, #460] @ (8014208 <_dtoa_r+0x590>) 801403a: f7f4 fd2b bl 8008a94 <__aeabi_dcmplt> 801403e: 2800 cmp r0, #0 8014040: f000 808b beq.w 801415a <_dtoa_r+0x4e2> 8014044: 9b08 ldr r3, [sp, #32] 8014046: 2b00 cmp r3, #0 8014048: f000 8087 beq.w 801415a <_dtoa_r+0x4e2> 801404c: f1bb 0f00 cmp.w fp, #0 8014050: dd34 ble.n 80140bc <_dtoa_r+0x444> 8014052: 4620 mov r0, r4 8014054: 2200 movs r2, #0 8014056: 4629 mov r1, r5 8014058: 4b6c ldr r3, [pc, #432] @ (801420c <_dtoa_r+0x594>) 801405a: f7f4 faa9 bl 80085b0 <__aeabi_dmul> 801405e: 465c mov r4, fp 8014060: e9cd 0106 strd r0, r1, [sp, #24] 8014064: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 8014068: 3601 adds r6, #1 801406a: 4630 mov r0, r6 801406c: f7f4 fa36 bl 80084dc <__aeabi_i2d> 8014070: e9dd 2306 ldrd r2, r3, [sp, #24] 8014074: f7f4 fa9c bl 80085b0 <__aeabi_dmul> 8014078: 2200 movs r2, #0 801407a: 4b65 ldr r3, [pc, #404] @ (8014210 <_dtoa_r+0x598>) 801407c: f7f4 f8e2 bl 8008244 <__adddf3> 8014080: 4605 mov r5, r0 8014082: f1a1 7650 sub.w r6, r1, #54525952 @ 0x3400000 8014086: 2c00 cmp r4, #0 8014088: d16a bne.n 8014160 <_dtoa_r+0x4e8> 801408a: e9dd 0106 ldrd r0, r1, [sp, #24] 801408e: 2200 movs r2, #0 8014090: 4b60 ldr r3, [pc, #384] @ (8014214 <_dtoa_r+0x59c>) 8014092: f7f4 f8d5 bl 8008240 <__aeabi_dsub> 8014096: 4602 mov r2, r0 8014098: 460b mov r3, r1 801409a: e9cd 2306 strd r2, r3, [sp, #24] 801409e: 462a mov r2, r5 80140a0: 4633 mov r3, r6 80140a2: f7f4 fd15 bl 8008ad0 <__aeabi_dcmpgt> 80140a6: 2800 cmp r0, #0 80140a8: f040 8298 bne.w 80145dc <_dtoa_r+0x964> 80140ac: e9dd 0106 ldrd r0, r1, [sp, #24] 80140b0: 462a mov r2, r5 80140b2: f106 4300 add.w r3, r6, #2147483648 @ 0x80000000 80140b6: f7f4 fced bl 8008a94 <__aeabi_dcmplt> 80140ba: bb38 cbnz r0, 801410c <_dtoa_r+0x494> 80140bc: e9dd 340c ldrd r3, r4, [sp, #48] @ 0x30 80140c0: e9cd 3406 strd r3, r4, [sp, #24] 80140c4: 9b15 ldr r3, [sp, #84] @ 0x54 80140c6: 2b00 cmp r3, #0 80140c8: f2c0 8157 blt.w 801437a <_dtoa_r+0x702> 80140cc: 2f0e cmp r7, #14 80140ce: f300 8154 bgt.w 801437a <_dtoa_r+0x702> 80140d2: 4b4b ldr r3, [pc, #300] @ (8014200 <_dtoa_r+0x588>) 80140d4: eb03 03c7 add.w r3, r3, r7, lsl #3 80140d8: e9d3 3400 ldrd r3, r4, [r3] 80140dc: e9cd 3404 strd r3, r4, [sp, #16] 80140e0: 9b21 ldr r3, [sp, #132] @ 0x84 80140e2: 2b00 cmp r3, #0 80140e4: f280 80e5 bge.w 80142b2 <_dtoa_r+0x63a> 80140e8: 9b08 ldr r3, [sp, #32] 80140ea: 2b00 cmp r3, #0 80140ec: f300 80e1 bgt.w 80142b2 <_dtoa_r+0x63a> 80140f0: d10c bne.n 801410c <_dtoa_r+0x494> 80140f2: e9dd 0104 ldrd r0, r1, [sp, #16] 80140f6: 2200 movs r2, #0 80140f8: 4b46 ldr r3, [pc, #280] @ (8014214 <_dtoa_r+0x59c>) 80140fa: f7f4 fa59 bl 80085b0 <__aeabi_dmul> 80140fe: e9dd 2306 ldrd r2, r3, [sp, #24] 8014102: f7f4 fcdb bl 8008abc <__aeabi_dcmpge> 8014106: 2800 cmp r0, #0 8014108: f000 8266 beq.w 80145d8 <_dtoa_r+0x960> 801410c: 2400 movs r4, #0 801410e: 4625 mov r5, r4 8014110: 9b21 ldr r3, [sp, #132] @ 0x84 8014112: 4656 mov r6, sl 8014114: ea6f 0803 mvn.w r8, r3 8014118: 2700 movs r7, #0 801411a: 4621 mov r1, r4 801411c: 4648 mov r0, r9 801411e: f000 ffb5 bl 801508c <_Bfree> 8014122: 2d00 cmp r5, #0 8014124: f000 80bd beq.w 80142a2 <_dtoa_r+0x62a> 8014128: b12f cbz r7, 8014136 <_dtoa_r+0x4be> 801412a: 42af cmp r7, r5 801412c: d003 beq.n 8014136 <_dtoa_r+0x4be> 801412e: 4639 mov r1, r7 8014130: 4648 mov r0, r9 8014132: f000 ffab bl 801508c <_Bfree> 8014136: 4629 mov r1, r5 8014138: 4648 mov r0, r9 801413a: f000 ffa7 bl 801508c <_Bfree> 801413e: e0b0 b.n 80142a2 <_dtoa_r+0x62a> 8014140: 07e2 lsls r2, r4, #31 8014142: d505 bpl.n 8014150 <_dtoa_r+0x4d8> 8014144: e9d5 2300 ldrd r2, r3, [r5] 8014148: f7f4 fa32 bl 80085b0 <__aeabi_dmul> 801414c: 2301 movs r3, #1 801414e: 3601 adds r6, #1 8014150: 1064 asrs r4, r4, #1 8014152: 3508 adds r5, #8 8014154: e762 b.n 801401c <_dtoa_r+0x3a4> 8014156: 2602 movs r6, #2 8014158: e765 b.n 8014026 <_dtoa_r+0x3ae> 801415a: 46b8 mov r8, r7 801415c: 9c08 ldr r4, [sp, #32] 801415e: e784 b.n 801406a <_dtoa_r+0x3f2> 8014160: 4b27 ldr r3, [pc, #156] @ (8014200 <_dtoa_r+0x588>) 8014162: 990b ldr r1, [sp, #44] @ 0x2c 8014164: eb03 03c4 add.w r3, r3, r4, lsl #3 8014168: e953 2302 ldrd r2, r3, [r3, #-8] 801416c: 4454 add r4, sl 801416e: 2900 cmp r1, #0 8014170: d054 beq.n 801421c <_dtoa_r+0x5a4> 8014172: 2000 movs r0, #0 8014174: 4928 ldr r1, [pc, #160] @ (8014218 <_dtoa_r+0x5a0>) 8014176: f7f4 fb45 bl 8008804 <__aeabi_ddiv> 801417a: 4633 mov r3, r6 801417c: 462a mov r2, r5 801417e: f7f4 f85f bl 8008240 <__aeabi_dsub> 8014182: 4656 mov r6, sl 8014184: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 8014188: e9dd 0106 ldrd r0, r1, [sp, #24] 801418c: f7f4 fcc0 bl 8008b10 <__aeabi_d2iz> 8014190: 4605 mov r5, r0 8014192: f7f4 f9a3 bl 80084dc <__aeabi_i2d> 8014196: 4602 mov r2, r0 8014198: 460b mov r3, r1 801419a: e9dd 0106 ldrd r0, r1, [sp, #24] 801419e: f7f4 f84f bl 8008240 <__aeabi_dsub> 80141a2: 4602 mov r2, r0 80141a4: 460b mov r3, r1 80141a6: 3530 adds r5, #48 @ 0x30 80141a8: e9cd 2306 strd r2, r3, [sp, #24] 80141ac: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 80141b0: f806 5b01 strb.w r5, [r6], #1 80141b4: f7f4 fc6e bl 8008a94 <__aeabi_dcmplt> 80141b8: 2800 cmp r0, #0 80141ba: d172 bne.n 80142a2 <_dtoa_r+0x62a> 80141bc: e9dd 2306 ldrd r2, r3, [sp, #24] 80141c0: 2000 movs r0, #0 80141c2: 4911 ldr r1, [pc, #68] @ (8014208 <_dtoa_r+0x590>) 80141c4: f7f4 f83c bl 8008240 <__aeabi_dsub> 80141c8: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 80141cc: f7f4 fc62 bl 8008a94 <__aeabi_dcmplt> 80141d0: 2800 cmp r0, #0 80141d2: f040 80b4 bne.w 801433e <_dtoa_r+0x6c6> 80141d6: 42a6 cmp r6, r4 80141d8: f43f af70 beq.w 80140bc <_dtoa_r+0x444> 80141dc: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 80141e0: 2200 movs r2, #0 80141e2: 4b0a ldr r3, [pc, #40] @ (801420c <_dtoa_r+0x594>) 80141e4: f7f4 f9e4 bl 80085b0 <__aeabi_dmul> 80141e8: 2200 movs r2, #0 80141ea: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 80141ee: e9dd 0106 ldrd r0, r1, [sp, #24] 80141f2: 4b06 ldr r3, [pc, #24] @ (801420c <_dtoa_r+0x594>) 80141f4: f7f4 f9dc bl 80085b0 <__aeabi_dmul> 80141f8: e9cd 0106 strd r0, r1, [sp, #24] 80141fc: e7c4 b.n 8014188 <_dtoa_r+0x510> 80141fe: bf00 nop 8014200: 080162f0 .word 0x080162f0 8014204: 080162c8 .word 0x080162c8 8014208: 3ff00000 .word 0x3ff00000 801420c: 40240000 .word 0x40240000 8014210: 401c0000 .word 0x401c0000 8014214: 40140000 .word 0x40140000 8014218: 3fe00000 .word 0x3fe00000 801421c: 4631 mov r1, r6 801421e: 4628 mov r0, r5 8014220: f7f4 f9c6 bl 80085b0 <__aeabi_dmul> 8014224: 4656 mov r6, sl 8014226: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 801422a: 9413 str r4, [sp, #76] @ 0x4c 801422c: e9dd 0106 ldrd r0, r1, [sp, #24] 8014230: f7f4 fc6e bl 8008b10 <__aeabi_d2iz> 8014234: 4605 mov r5, r0 8014236: f7f4 f951 bl 80084dc <__aeabi_i2d> 801423a: 4602 mov r2, r0 801423c: 460b mov r3, r1 801423e: e9dd 0106 ldrd r0, r1, [sp, #24] 8014242: f7f3 fffd bl 8008240 <__aeabi_dsub> 8014246: 4602 mov r2, r0 8014248: 460b mov r3, r1 801424a: 3530 adds r5, #48 @ 0x30 801424c: f806 5b01 strb.w r5, [r6], #1 8014250: 42a6 cmp r6, r4 8014252: e9cd 2306 strd r2, r3, [sp, #24] 8014256: f04f 0200 mov.w r2, #0 801425a: d124 bne.n 80142a6 <_dtoa_r+0x62e> 801425c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8014260: 4bae ldr r3, [pc, #696] @ (801451c <_dtoa_r+0x8a4>) 8014262: f7f3 ffef bl 8008244 <__adddf3> 8014266: 4602 mov r2, r0 8014268: 460b mov r3, r1 801426a: e9dd 0106 ldrd r0, r1, [sp, #24] 801426e: f7f4 fc2f bl 8008ad0 <__aeabi_dcmpgt> 8014272: 2800 cmp r0, #0 8014274: d163 bne.n 801433e <_dtoa_r+0x6c6> 8014276: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 801427a: 2000 movs r0, #0 801427c: 49a7 ldr r1, [pc, #668] @ (801451c <_dtoa_r+0x8a4>) 801427e: f7f3 ffdf bl 8008240 <__aeabi_dsub> 8014282: 4602 mov r2, r0 8014284: 460b mov r3, r1 8014286: e9dd 0106 ldrd r0, r1, [sp, #24] 801428a: f7f4 fc03 bl 8008a94 <__aeabi_dcmplt> 801428e: 2800 cmp r0, #0 8014290: f43f af14 beq.w 80140bc <_dtoa_r+0x444> 8014294: 9e13 ldr r6, [sp, #76] @ 0x4c 8014296: 1e73 subs r3, r6, #1 8014298: 9313 str r3, [sp, #76] @ 0x4c 801429a: f816 3c01 ldrb.w r3, [r6, #-1] 801429e: 2b30 cmp r3, #48 @ 0x30 80142a0: d0f8 beq.n 8014294 <_dtoa_r+0x61c> 80142a2: 4647 mov r7, r8 80142a4: e03b b.n 801431e <_dtoa_r+0x6a6> 80142a6: 4b9e ldr r3, [pc, #632] @ (8014520 <_dtoa_r+0x8a8>) 80142a8: f7f4 f982 bl 80085b0 <__aeabi_dmul> 80142ac: e9cd 0106 strd r0, r1, [sp, #24] 80142b0: e7bc b.n 801422c <_dtoa_r+0x5b4> 80142b2: 4656 mov r6, sl 80142b4: e9dd 4506 ldrd r4, r5, [sp, #24] 80142b8: e9dd 2304 ldrd r2, r3, [sp, #16] 80142bc: 4620 mov r0, r4 80142be: 4629 mov r1, r5 80142c0: f7f4 faa0 bl 8008804 <__aeabi_ddiv> 80142c4: f7f4 fc24 bl 8008b10 <__aeabi_d2iz> 80142c8: 4680 mov r8, r0 80142ca: f7f4 f907 bl 80084dc <__aeabi_i2d> 80142ce: e9dd 2304 ldrd r2, r3, [sp, #16] 80142d2: f7f4 f96d bl 80085b0 <__aeabi_dmul> 80142d6: 4602 mov r2, r0 80142d8: 460b mov r3, r1 80142da: 4620 mov r0, r4 80142dc: 4629 mov r1, r5 80142de: f7f3 ffaf bl 8008240 <__aeabi_dsub> 80142e2: f108 0430 add.w r4, r8, #48 @ 0x30 80142e6: 9d08 ldr r5, [sp, #32] 80142e8: f806 4b01 strb.w r4, [r6], #1 80142ec: eba6 040a sub.w r4, r6, sl 80142f0: 42a5 cmp r5, r4 80142f2: 4602 mov r2, r0 80142f4: 460b mov r3, r1 80142f6: d133 bne.n 8014360 <_dtoa_r+0x6e8> 80142f8: f7f3 ffa4 bl 8008244 <__adddf3> 80142fc: e9dd 2304 ldrd r2, r3, [sp, #16] 8014300: 4604 mov r4, r0 8014302: 460d mov r5, r1 8014304: f7f4 fbe4 bl 8008ad0 <__aeabi_dcmpgt> 8014308: b9c0 cbnz r0, 801433c <_dtoa_r+0x6c4> 801430a: e9dd 2304 ldrd r2, r3, [sp, #16] 801430e: 4620 mov r0, r4 8014310: 4629 mov r1, r5 8014312: f7f4 fbb5 bl 8008a80 <__aeabi_dcmpeq> 8014316: b110 cbz r0, 801431e <_dtoa_r+0x6a6> 8014318: f018 0f01 tst.w r8, #1 801431c: d10e bne.n 801433c <_dtoa_r+0x6c4> 801431e: 4648 mov r0, r9 8014320: 9903 ldr r1, [sp, #12] 8014322: f000 feb3 bl 801508c <_Bfree> 8014326: 2300 movs r3, #0 8014328: 7033 strb r3, [r6, #0] 801432a: 9b22 ldr r3, [sp, #136] @ 0x88 801432c: 3701 adds r7, #1 801432e: 601f str r7, [r3, #0] 8014330: 9b24 ldr r3, [sp, #144] @ 0x90 8014332: 2b00 cmp r3, #0 8014334: f000 824b beq.w 80147ce <_dtoa_r+0xb56> 8014338: 601e str r6, [r3, #0] 801433a: e248 b.n 80147ce <_dtoa_r+0xb56> 801433c: 46b8 mov r8, r7 801433e: 4633 mov r3, r6 8014340: 461e mov r6, r3 8014342: f813 2d01 ldrb.w r2, [r3, #-1]! 8014346: 2a39 cmp r2, #57 @ 0x39 8014348: d106 bne.n 8014358 <_dtoa_r+0x6e0> 801434a: 459a cmp sl, r3 801434c: d1f8 bne.n 8014340 <_dtoa_r+0x6c8> 801434e: 2230 movs r2, #48 @ 0x30 8014350: f108 0801 add.w r8, r8, #1 8014354: f88a 2000 strb.w r2, [sl] 8014358: 781a ldrb r2, [r3, #0] 801435a: 3201 adds r2, #1 801435c: 701a strb r2, [r3, #0] 801435e: e7a0 b.n 80142a2 <_dtoa_r+0x62a> 8014360: 2200 movs r2, #0 8014362: 4b6f ldr r3, [pc, #444] @ (8014520 <_dtoa_r+0x8a8>) 8014364: f7f4 f924 bl 80085b0 <__aeabi_dmul> 8014368: 2200 movs r2, #0 801436a: 2300 movs r3, #0 801436c: 4604 mov r4, r0 801436e: 460d mov r5, r1 8014370: f7f4 fb86 bl 8008a80 <__aeabi_dcmpeq> 8014374: 2800 cmp r0, #0 8014376: d09f beq.n 80142b8 <_dtoa_r+0x640> 8014378: e7d1 b.n 801431e <_dtoa_r+0x6a6> 801437a: 9a0b ldr r2, [sp, #44] @ 0x2c 801437c: 2a00 cmp r2, #0 801437e: f000 80ea beq.w 8014556 <_dtoa_r+0x8de> 8014382: 9a20 ldr r2, [sp, #128] @ 0x80 8014384: 2a01 cmp r2, #1 8014386: f300 80cd bgt.w 8014524 <_dtoa_r+0x8ac> 801438a: 9a12 ldr r2, [sp, #72] @ 0x48 801438c: 2a00 cmp r2, #0 801438e: f000 80c1 beq.w 8014514 <_dtoa_r+0x89c> 8014392: f203 4333 addw r3, r3, #1075 @ 0x433 8014396: 9c0a ldr r4, [sp, #40] @ 0x28 8014398: 9e04 ldr r6, [sp, #16] 801439a: 9a04 ldr r2, [sp, #16] 801439c: 2101 movs r1, #1 801439e: 441a add r2, r3 80143a0: 9204 str r2, [sp, #16] 80143a2: 9a09 ldr r2, [sp, #36] @ 0x24 80143a4: 4648 mov r0, r9 80143a6: 441a add r2, r3 80143a8: 9209 str r2, [sp, #36] @ 0x24 80143aa: f000 ff23 bl 80151f4 <__i2b> 80143ae: 4605 mov r5, r0 80143b0: b166 cbz r6, 80143cc <_dtoa_r+0x754> 80143b2: 9b09 ldr r3, [sp, #36] @ 0x24 80143b4: 2b00 cmp r3, #0 80143b6: dd09 ble.n 80143cc <_dtoa_r+0x754> 80143b8: 42b3 cmp r3, r6 80143ba: bfa8 it ge 80143bc: 4633 movge r3, r6 80143be: 9a04 ldr r2, [sp, #16] 80143c0: 1af6 subs r6, r6, r3 80143c2: 1ad2 subs r2, r2, r3 80143c4: 9204 str r2, [sp, #16] 80143c6: 9a09 ldr r2, [sp, #36] @ 0x24 80143c8: 1ad3 subs r3, r2, r3 80143ca: 9309 str r3, [sp, #36] @ 0x24 80143cc: 9b0a ldr r3, [sp, #40] @ 0x28 80143ce: b30b cbz r3, 8014414 <_dtoa_r+0x79c> 80143d0: 9b0b ldr r3, [sp, #44] @ 0x2c 80143d2: 2b00 cmp r3, #0 80143d4: f000 80c6 beq.w 8014564 <_dtoa_r+0x8ec> 80143d8: 2c00 cmp r4, #0 80143da: f000 80c0 beq.w 801455e <_dtoa_r+0x8e6> 80143de: 4629 mov r1, r5 80143e0: 4622 mov r2, r4 80143e2: 4648 mov r0, r9 80143e4: f000 ffbe bl 8015364 <__pow5mult> 80143e8: 9a03 ldr r2, [sp, #12] 80143ea: 4601 mov r1, r0 80143ec: 4605 mov r5, r0 80143ee: 4648 mov r0, r9 80143f0: f000 ff16 bl 8015220 <__multiply> 80143f4: 9903 ldr r1, [sp, #12] 80143f6: 4680 mov r8, r0 80143f8: 4648 mov r0, r9 80143fa: f000 fe47 bl 801508c <_Bfree> 80143fe: 9b0a ldr r3, [sp, #40] @ 0x28 8014400: 1b1b subs r3, r3, r4 8014402: 930a str r3, [sp, #40] @ 0x28 8014404: f000 80b1 beq.w 801456a <_dtoa_r+0x8f2> 8014408: 4641 mov r1, r8 801440a: 9a0a ldr r2, [sp, #40] @ 0x28 801440c: 4648 mov r0, r9 801440e: f000 ffa9 bl 8015364 <__pow5mult> 8014412: 9003 str r0, [sp, #12] 8014414: 2101 movs r1, #1 8014416: 4648 mov r0, r9 8014418: f000 feec bl 80151f4 <__i2b> 801441c: 9b0e ldr r3, [sp, #56] @ 0x38 801441e: 4604 mov r4, r0 8014420: 2b00 cmp r3, #0 8014422: f000 81d8 beq.w 80147d6 <_dtoa_r+0xb5e> 8014426: 461a mov r2, r3 8014428: 4601 mov r1, r0 801442a: 4648 mov r0, r9 801442c: f000 ff9a bl 8015364 <__pow5mult> 8014430: 9b20 ldr r3, [sp, #128] @ 0x80 8014432: 4604 mov r4, r0 8014434: 2b01 cmp r3, #1 8014436: f300 809f bgt.w 8014578 <_dtoa_r+0x900> 801443a: 9b06 ldr r3, [sp, #24] 801443c: 2b00 cmp r3, #0 801443e: f040 8097 bne.w 8014570 <_dtoa_r+0x8f8> 8014442: 9b07 ldr r3, [sp, #28] 8014444: f3c3 0313 ubfx r3, r3, #0, #20 8014448: 2b00 cmp r3, #0 801444a: f040 8093 bne.w 8014574 <_dtoa_r+0x8fc> 801444e: 9b07 ldr r3, [sp, #28] 8014450: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8014454: 0d1b lsrs r3, r3, #20 8014456: 051b lsls r3, r3, #20 8014458: b133 cbz r3, 8014468 <_dtoa_r+0x7f0> 801445a: 9b04 ldr r3, [sp, #16] 801445c: 3301 adds r3, #1 801445e: 9304 str r3, [sp, #16] 8014460: 9b09 ldr r3, [sp, #36] @ 0x24 8014462: 3301 adds r3, #1 8014464: 9309 str r3, [sp, #36] @ 0x24 8014466: 2301 movs r3, #1 8014468: 930a str r3, [sp, #40] @ 0x28 801446a: 9b0e ldr r3, [sp, #56] @ 0x38 801446c: 2b00 cmp r3, #0 801446e: f000 81b8 beq.w 80147e2 <_dtoa_r+0xb6a> 8014472: 6923 ldr r3, [r4, #16] 8014474: eb04 0383 add.w r3, r4, r3, lsl #2 8014478: 6918 ldr r0, [r3, #16] 801447a: f000 fe6f bl 801515c <__hi0bits> 801447e: f1c0 0020 rsb r0, r0, #32 8014482: 9b09 ldr r3, [sp, #36] @ 0x24 8014484: 4418 add r0, r3 8014486: f010 001f ands.w r0, r0, #31 801448a: f000 8082 beq.w 8014592 <_dtoa_r+0x91a> 801448e: f1c0 0320 rsb r3, r0, #32 8014492: 2b04 cmp r3, #4 8014494: dd73 ble.n 801457e <_dtoa_r+0x906> 8014496: 9b04 ldr r3, [sp, #16] 8014498: f1c0 001c rsb r0, r0, #28 801449c: 4403 add r3, r0 801449e: 9304 str r3, [sp, #16] 80144a0: 9b09 ldr r3, [sp, #36] @ 0x24 80144a2: 4406 add r6, r0 80144a4: 4403 add r3, r0 80144a6: 9309 str r3, [sp, #36] @ 0x24 80144a8: 9b04 ldr r3, [sp, #16] 80144aa: 2b00 cmp r3, #0 80144ac: dd05 ble.n 80144ba <_dtoa_r+0x842> 80144ae: 461a mov r2, r3 80144b0: 4648 mov r0, r9 80144b2: 9903 ldr r1, [sp, #12] 80144b4: f000 ffb0 bl 8015418 <__lshift> 80144b8: 9003 str r0, [sp, #12] 80144ba: 9b09 ldr r3, [sp, #36] @ 0x24 80144bc: 2b00 cmp r3, #0 80144be: dd05 ble.n 80144cc <_dtoa_r+0x854> 80144c0: 4621 mov r1, r4 80144c2: 461a mov r2, r3 80144c4: 4648 mov r0, r9 80144c6: f000 ffa7 bl 8015418 <__lshift> 80144ca: 4604 mov r4, r0 80144cc: 9b0f ldr r3, [sp, #60] @ 0x3c 80144ce: 2b00 cmp r3, #0 80144d0: d061 beq.n 8014596 <_dtoa_r+0x91e> 80144d2: 4621 mov r1, r4 80144d4: 9803 ldr r0, [sp, #12] 80144d6: f001 f80b bl 80154f0 <__mcmp> 80144da: 2800 cmp r0, #0 80144dc: da5b bge.n 8014596 <_dtoa_r+0x91e> 80144de: 2300 movs r3, #0 80144e0: 220a movs r2, #10 80144e2: 4648 mov r0, r9 80144e4: 9903 ldr r1, [sp, #12] 80144e6: f000 fdf3 bl 80150d0 <__multadd> 80144ea: 9b0b ldr r3, [sp, #44] @ 0x2c 80144ec: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 80144f0: 9003 str r0, [sp, #12] 80144f2: 2b00 cmp r3, #0 80144f4: f000 8177 beq.w 80147e6 <_dtoa_r+0xb6e> 80144f8: 4629 mov r1, r5 80144fa: 2300 movs r3, #0 80144fc: 220a movs r2, #10 80144fe: 4648 mov r0, r9 8014500: f000 fde6 bl 80150d0 <__multadd> 8014504: f1bb 0f00 cmp.w fp, #0 8014508: 4605 mov r5, r0 801450a: dc6f bgt.n 80145ec <_dtoa_r+0x974> 801450c: 9b20 ldr r3, [sp, #128] @ 0x80 801450e: 2b02 cmp r3, #2 8014510: dc49 bgt.n 80145a6 <_dtoa_r+0x92e> 8014512: e06b b.n 80145ec <_dtoa_r+0x974> 8014514: 9b14 ldr r3, [sp, #80] @ 0x50 8014516: f1c3 0336 rsb r3, r3, #54 @ 0x36 801451a: e73c b.n 8014396 <_dtoa_r+0x71e> 801451c: 3fe00000 .word 0x3fe00000 8014520: 40240000 .word 0x40240000 8014524: 9b08 ldr r3, [sp, #32] 8014526: 1e5c subs r4, r3, #1 8014528: 9b0a ldr r3, [sp, #40] @ 0x28 801452a: 42a3 cmp r3, r4 801452c: db09 blt.n 8014542 <_dtoa_r+0x8ca> 801452e: 1b1c subs r4, r3, r4 8014530: 9b08 ldr r3, [sp, #32] 8014532: 2b00 cmp r3, #0 8014534: f6bf af30 bge.w 8014398 <_dtoa_r+0x720> 8014538: 9b04 ldr r3, [sp, #16] 801453a: 9a08 ldr r2, [sp, #32] 801453c: 1a9e subs r6, r3, r2 801453e: 2300 movs r3, #0 8014540: e72b b.n 801439a <_dtoa_r+0x722> 8014542: 9b0a ldr r3, [sp, #40] @ 0x28 8014544: 9a0e ldr r2, [sp, #56] @ 0x38 8014546: 1ae3 subs r3, r4, r3 8014548: 441a add r2, r3 801454a: 940a str r4, [sp, #40] @ 0x28 801454c: 9e04 ldr r6, [sp, #16] 801454e: 2400 movs r4, #0 8014550: 9b08 ldr r3, [sp, #32] 8014552: 920e str r2, [sp, #56] @ 0x38 8014554: e721 b.n 801439a <_dtoa_r+0x722> 8014556: 9c0a ldr r4, [sp, #40] @ 0x28 8014558: 9e04 ldr r6, [sp, #16] 801455a: 9d0b ldr r5, [sp, #44] @ 0x2c 801455c: e728 b.n 80143b0 <_dtoa_r+0x738> 801455e: f8dd 800c ldr.w r8, [sp, #12] 8014562: e751 b.n 8014408 <_dtoa_r+0x790> 8014564: 9a0a ldr r2, [sp, #40] @ 0x28 8014566: 9903 ldr r1, [sp, #12] 8014568: e750 b.n 801440c <_dtoa_r+0x794> 801456a: f8cd 800c str.w r8, [sp, #12] 801456e: e751 b.n 8014414 <_dtoa_r+0x79c> 8014570: 2300 movs r3, #0 8014572: e779 b.n 8014468 <_dtoa_r+0x7f0> 8014574: 9b06 ldr r3, [sp, #24] 8014576: e777 b.n 8014468 <_dtoa_r+0x7f0> 8014578: 2300 movs r3, #0 801457a: 930a str r3, [sp, #40] @ 0x28 801457c: e779 b.n 8014472 <_dtoa_r+0x7fa> 801457e: d093 beq.n 80144a8 <_dtoa_r+0x830> 8014580: 9a04 ldr r2, [sp, #16] 8014582: 331c adds r3, #28 8014584: 441a add r2, r3 8014586: 9204 str r2, [sp, #16] 8014588: 9a09 ldr r2, [sp, #36] @ 0x24 801458a: 441e add r6, r3 801458c: 441a add r2, r3 801458e: 9209 str r2, [sp, #36] @ 0x24 8014590: e78a b.n 80144a8 <_dtoa_r+0x830> 8014592: 4603 mov r3, r0 8014594: e7f4 b.n 8014580 <_dtoa_r+0x908> 8014596: 9b08 ldr r3, [sp, #32] 8014598: 46b8 mov r8, r7 801459a: 2b00 cmp r3, #0 801459c: dc20 bgt.n 80145e0 <_dtoa_r+0x968> 801459e: 469b mov fp, r3 80145a0: 9b20 ldr r3, [sp, #128] @ 0x80 80145a2: 2b02 cmp r3, #2 80145a4: dd1e ble.n 80145e4 <_dtoa_r+0x96c> 80145a6: f1bb 0f00 cmp.w fp, #0 80145aa: f47f adb1 bne.w 8014110 <_dtoa_r+0x498> 80145ae: 4621 mov r1, r4 80145b0: 465b mov r3, fp 80145b2: 2205 movs r2, #5 80145b4: 4648 mov r0, r9 80145b6: f000 fd8b bl 80150d0 <__multadd> 80145ba: 4601 mov r1, r0 80145bc: 4604 mov r4, r0 80145be: 9803 ldr r0, [sp, #12] 80145c0: f000 ff96 bl 80154f0 <__mcmp> 80145c4: 2800 cmp r0, #0 80145c6: f77f ada3 ble.w 8014110 <_dtoa_r+0x498> 80145ca: 4656 mov r6, sl 80145cc: 2331 movs r3, #49 @ 0x31 80145ce: f108 0801 add.w r8, r8, #1 80145d2: f806 3b01 strb.w r3, [r6], #1 80145d6: e59f b.n 8014118 <_dtoa_r+0x4a0> 80145d8: 46b8 mov r8, r7 80145da: 9c08 ldr r4, [sp, #32] 80145dc: 4625 mov r5, r4 80145de: e7f4 b.n 80145ca <_dtoa_r+0x952> 80145e0: f8dd b020 ldr.w fp, [sp, #32] 80145e4: 9b0b ldr r3, [sp, #44] @ 0x2c 80145e6: 2b00 cmp r3, #0 80145e8: f000 8101 beq.w 80147ee <_dtoa_r+0xb76> 80145ec: 2e00 cmp r6, #0 80145ee: dd05 ble.n 80145fc <_dtoa_r+0x984> 80145f0: 4629 mov r1, r5 80145f2: 4632 mov r2, r6 80145f4: 4648 mov r0, r9 80145f6: f000 ff0f bl 8015418 <__lshift> 80145fa: 4605 mov r5, r0 80145fc: 9b0a ldr r3, [sp, #40] @ 0x28 80145fe: 2b00 cmp r3, #0 8014600: d05c beq.n 80146bc <_dtoa_r+0xa44> 8014602: 4648 mov r0, r9 8014604: 6869 ldr r1, [r5, #4] 8014606: f000 fd01 bl 801500c <_Balloc> 801460a: 4606 mov r6, r0 801460c: b928 cbnz r0, 801461a <_dtoa_r+0x9a2> 801460e: 4602 mov r2, r0 8014610: f240 21ef movw r1, #751 @ 0x2ef 8014614: 4b80 ldr r3, [pc, #512] @ (8014818 <_dtoa_r+0xba0>) 8014616: f7ff bb43 b.w 8013ca0 <_dtoa_r+0x28> 801461a: 692a ldr r2, [r5, #16] 801461c: f105 010c add.w r1, r5, #12 8014620: 3202 adds r2, #2 8014622: 0092 lsls r2, r2, #2 8014624: 300c adds r0, #12 8014626: f7ff fa73 bl 8013b10 801462a: 2201 movs r2, #1 801462c: 4631 mov r1, r6 801462e: 4648 mov r0, r9 8014630: f000 fef2 bl 8015418 <__lshift> 8014634: 462f mov r7, r5 8014636: 4605 mov r5, r0 8014638: f10a 0301 add.w r3, sl, #1 801463c: 9304 str r3, [sp, #16] 801463e: eb0a 030b add.w r3, sl, fp 8014642: 930a str r3, [sp, #40] @ 0x28 8014644: 9b06 ldr r3, [sp, #24] 8014646: f003 0301 and.w r3, r3, #1 801464a: 9309 str r3, [sp, #36] @ 0x24 801464c: 9b04 ldr r3, [sp, #16] 801464e: 4621 mov r1, r4 8014650: 9803 ldr r0, [sp, #12] 8014652: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff 8014656: f7ff fa87 bl 8013b68 801465a: 4603 mov r3, r0 801465c: 4639 mov r1, r7 801465e: 3330 adds r3, #48 @ 0x30 8014660: 9006 str r0, [sp, #24] 8014662: 9803 ldr r0, [sp, #12] 8014664: 930b str r3, [sp, #44] @ 0x2c 8014666: f000 ff43 bl 80154f0 <__mcmp> 801466a: 462a mov r2, r5 801466c: 9008 str r0, [sp, #32] 801466e: 4621 mov r1, r4 8014670: 4648 mov r0, r9 8014672: f000 ff59 bl 8015528 <__mdiff> 8014676: 68c2 ldr r2, [r0, #12] 8014678: 4606 mov r6, r0 801467a: 9b0b ldr r3, [sp, #44] @ 0x2c 801467c: bb02 cbnz r2, 80146c0 <_dtoa_r+0xa48> 801467e: 4601 mov r1, r0 8014680: 9803 ldr r0, [sp, #12] 8014682: f000 ff35 bl 80154f0 <__mcmp> 8014686: 4602 mov r2, r0 8014688: 9b0b ldr r3, [sp, #44] @ 0x2c 801468a: 4631 mov r1, r6 801468c: 4648 mov r0, r9 801468e: e9cd 320b strd r3, r2, [sp, #44] @ 0x2c 8014692: f000 fcfb bl 801508c <_Bfree> 8014696: 9b20 ldr r3, [sp, #128] @ 0x80 8014698: 9a0c ldr r2, [sp, #48] @ 0x30 801469a: 9e04 ldr r6, [sp, #16] 801469c: ea42 0103 orr.w r1, r2, r3 80146a0: 9b09 ldr r3, [sp, #36] @ 0x24 80146a2: 4319 orrs r1, r3 80146a4: 9b0b ldr r3, [sp, #44] @ 0x2c 80146a6: d10d bne.n 80146c4 <_dtoa_r+0xa4c> 80146a8: 2b39 cmp r3, #57 @ 0x39 80146aa: d027 beq.n 80146fc <_dtoa_r+0xa84> 80146ac: 9a08 ldr r2, [sp, #32] 80146ae: 2a00 cmp r2, #0 80146b0: dd01 ble.n 80146b6 <_dtoa_r+0xa3e> 80146b2: 9b06 ldr r3, [sp, #24] 80146b4: 3331 adds r3, #49 @ 0x31 80146b6: f88b 3000 strb.w r3, [fp] 80146ba: e52e b.n 801411a <_dtoa_r+0x4a2> 80146bc: 4628 mov r0, r5 80146be: e7b9 b.n 8014634 <_dtoa_r+0x9bc> 80146c0: 2201 movs r2, #1 80146c2: e7e2 b.n 801468a <_dtoa_r+0xa12> 80146c4: 9908 ldr r1, [sp, #32] 80146c6: 2900 cmp r1, #0 80146c8: db04 blt.n 80146d4 <_dtoa_r+0xa5c> 80146ca: 9820 ldr r0, [sp, #128] @ 0x80 80146cc: 4301 orrs r1, r0 80146ce: 9809 ldr r0, [sp, #36] @ 0x24 80146d0: 4301 orrs r1, r0 80146d2: d120 bne.n 8014716 <_dtoa_r+0xa9e> 80146d4: 2a00 cmp r2, #0 80146d6: ddee ble.n 80146b6 <_dtoa_r+0xa3e> 80146d8: 2201 movs r2, #1 80146da: 9903 ldr r1, [sp, #12] 80146dc: 4648 mov r0, r9 80146de: 9304 str r3, [sp, #16] 80146e0: f000 fe9a bl 8015418 <__lshift> 80146e4: 4621 mov r1, r4 80146e6: 9003 str r0, [sp, #12] 80146e8: f000 ff02 bl 80154f0 <__mcmp> 80146ec: 2800 cmp r0, #0 80146ee: 9b04 ldr r3, [sp, #16] 80146f0: dc02 bgt.n 80146f8 <_dtoa_r+0xa80> 80146f2: d1e0 bne.n 80146b6 <_dtoa_r+0xa3e> 80146f4: 07da lsls r2, r3, #31 80146f6: d5de bpl.n 80146b6 <_dtoa_r+0xa3e> 80146f8: 2b39 cmp r3, #57 @ 0x39 80146fa: d1da bne.n 80146b2 <_dtoa_r+0xa3a> 80146fc: 2339 movs r3, #57 @ 0x39 80146fe: f88b 3000 strb.w r3, [fp] 8014702: 4633 mov r3, r6 8014704: 461e mov r6, r3 8014706: f816 2c01 ldrb.w r2, [r6, #-1] 801470a: 3b01 subs r3, #1 801470c: 2a39 cmp r2, #57 @ 0x39 801470e: d04e beq.n 80147ae <_dtoa_r+0xb36> 8014710: 3201 adds r2, #1 8014712: 701a strb r2, [r3, #0] 8014714: e501 b.n 801411a <_dtoa_r+0x4a2> 8014716: 2a00 cmp r2, #0 8014718: dd03 ble.n 8014722 <_dtoa_r+0xaaa> 801471a: 2b39 cmp r3, #57 @ 0x39 801471c: d0ee beq.n 80146fc <_dtoa_r+0xa84> 801471e: 3301 adds r3, #1 8014720: e7c9 b.n 80146b6 <_dtoa_r+0xa3e> 8014722: 9a04 ldr r2, [sp, #16] 8014724: 990a ldr r1, [sp, #40] @ 0x28 8014726: f802 3c01 strb.w r3, [r2, #-1] 801472a: 428a cmp r2, r1 801472c: d028 beq.n 8014780 <_dtoa_r+0xb08> 801472e: 2300 movs r3, #0 8014730: 220a movs r2, #10 8014732: 9903 ldr r1, [sp, #12] 8014734: 4648 mov r0, r9 8014736: f000 fccb bl 80150d0 <__multadd> 801473a: 42af cmp r7, r5 801473c: 9003 str r0, [sp, #12] 801473e: f04f 0300 mov.w r3, #0 8014742: f04f 020a mov.w r2, #10 8014746: 4639 mov r1, r7 8014748: 4648 mov r0, r9 801474a: d107 bne.n 801475c <_dtoa_r+0xae4> 801474c: f000 fcc0 bl 80150d0 <__multadd> 8014750: 4607 mov r7, r0 8014752: 4605 mov r5, r0 8014754: 9b04 ldr r3, [sp, #16] 8014756: 3301 adds r3, #1 8014758: 9304 str r3, [sp, #16] 801475a: e777 b.n 801464c <_dtoa_r+0x9d4> 801475c: f000 fcb8 bl 80150d0 <__multadd> 8014760: 4629 mov r1, r5 8014762: 4607 mov r7, r0 8014764: 2300 movs r3, #0 8014766: 220a movs r2, #10 8014768: 4648 mov r0, r9 801476a: f000 fcb1 bl 80150d0 <__multadd> 801476e: 4605 mov r5, r0 8014770: e7f0 b.n 8014754 <_dtoa_r+0xadc> 8014772: f1bb 0f00 cmp.w fp, #0 8014776: bfcc ite gt 8014778: 465e movgt r6, fp 801477a: 2601 movle r6, #1 801477c: 2700 movs r7, #0 801477e: 4456 add r6, sl 8014780: 2201 movs r2, #1 8014782: 9903 ldr r1, [sp, #12] 8014784: 4648 mov r0, r9 8014786: 9304 str r3, [sp, #16] 8014788: f000 fe46 bl 8015418 <__lshift> 801478c: 4621 mov r1, r4 801478e: 9003 str r0, [sp, #12] 8014790: f000 feae bl 80154f0 <__mcmp> 8014794: 2800 cmp r0, #0 8014796: dcb4 bgt.n 8014702 <_dtoa_r+0xa8a> 8014798: d102 bne.n 80147a0 <_dtoa_r+0xb28> 801479a: 9b04 ldr r3, [sp, #16] 801479c: 07db lsls r3, r3, #31 801479e: d4b0 bmi.n 8014702 <_dtoa_r+0xa8a> 80147a0: 4633 mov r3, r6 80147a2: 461e mov r6, r3 80147a4: f813 2d01 ldrb.w r2, [r3, #-1]! 80147a8: 2a30 cmp r2, #48 @ 0x30 80147aa: d0fa beq.n 80147a2 <_dtoa_r+0xb2a> 80147ac: e4b5 b.n 801411a <_dtoa_r+0x4a2> 80147ae: 459a cmp sl, r3 80147b0: d1a8 bne.n 8014704 <_dtoa_r+0xa8c> 80147b2: 2331 movs r3, #49 @ 0x31 80147b4: f108 0801 add.w r8, r8, #1 80147b8: f88a 3000 strb.w r3, [sl] 80147bc: e4ad b.n 801411a <_dtoa_r+0x4a2> 80147be: 9b24 ldr r3, [sp, #144] @ 0x90 80147c0: f8df a058 ldr.w sl, [pc, #88] @ 801481c <_dtoa_r+0xba4> 80147c4: b11b cbz r3, 80147ce <_dtoa_r+0xb56> 80147c6: f10a 0308 add.w r3, sl, #8 80147ca: 9a24 ldr r2, [sp, #144] @ 0x90 80147cc: 6013 str r3, [r2, #0] 80147ce: 4650 mov r0, sl 80147d0: b017 add sp, #92 @ 0x5c 80147d2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80147d6: 9b20 ldr r3, [sp, #128] @ 0x80 80147d8: 2b01 cmp r3, #1 80147da: f77f ae2e ble.w 801443a <_dtoa_r+0x7c2> 80147de: 9b0e ldr r3, [sp, #56] @ 0x38 80147e0: 930a str r3, [sp, #40] @ 0x28 80147e2: 2001 movs r0, #1 80147e4: e64d b.n 8014482 <_dtoa_r+0x80a> 80147e6: f1bb 0f00 cmp.w fp, #0 80147ea: f77f aed9 ble.w 80145a0 <_dtoa_r+0x928> 80147ee: 4656 mov r6, sl 80147f0: 4621 mov r1, r4 80147f2: 9803 ldr r0, [sp, #12] 80147f4: f7ff f9b8 bl 8013b68 80147f8: f100 0330 add.w r3, r0, #48 @ 0x30 80147fc: f806 3b01 strb.w r3, [r6], #1 8014800: eba6 020a sub.w r2, r6, sl 8014804: 4593 cmp fp, r2 8014806: ddb4 ble.n 8014772 <_dtoa_r+0xafa> 8014808: 2300 movs r3, #0 801480a: 220a movs r2, #10 801480c: 4648 mov r0, r9 801480e: 9903 ldr r1, [sp, #12] 8014810: f000 fc5e bl 80150d0 <__multadd> 8014814: 9003 str r0, [sp, #12] 8014816: e7eb b.n 80147f0 <_dtoa_r+0xb78> 8014818: 08016234 .word 0x08016234 801481c: 080161b8 .word 0x080161b8 08014820 <__ssputs_r>: 8014820: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8014824: 461f mov r7, r3 8014826: 688e ldr r6, [r1, #8] 8014828: 4682 mov sl, r0 801482a: 42be cmp r6, r7 801482c: 460c mov r4, r1 801482e: 4690 mov r8, r2 8014830: 680b ldr r3, [r1, #0] 8014832: d82d bhi.n 8014890 <__ssputs_r+0x70> 8014834: f9b1 200c ldrsh.w r2, [r1, #12] 8014838: f412 6f90 tst.w r2, #1152 @ 0x480 801483c: d026 beq.n 801488c <__ssputs_r+0x6c> 801483e: 6965 ldr r5, [r4, #20] 8014840: 6909 ldr r1, [r1, #16] 8014842: eb05 0545 add.w r5, r5, r5, lsl #1 8014846: eba3 0901 sub.w r9, r3, r1 801484a: eb05 75d5 add.w r5, r5, r5, lsr #31 801484e: 1c7b adds r3, r7, #1 8014850: 444b add r3, r9 8014852: 106d asrs r5, r5, #1 8014854: 429d cmp r5, r3 8014856: bf38 it cc 8014858: 461d movcc r5, r3 801485a: 0553 lsls r3, r2, #21 801485c: d527 bpl.n 80148ae <__ssputs_r+0x8e> 801485e: 4629 mov r1, r5 8014860: f000 faa0 bl 8014da4 <_malloc_r> 8014864: 4606 mov r6, r0 8014866: b360 cbz r0, 80148c2 <__ssputs_r+0xa2> 8014868: 464a mov r2, r9 801486a: 6921 ldr r1, [r4, #16] 801486c: f7ff f950 bl 8013b10 8014870: 89a3 ldrh r3, [r4, #12] 8014872: f423 6390 bic.w r3, r3, #1152 @ 0x480 8014876: f043 0380 orr.w r3, r3, #128 @ 0x80 801487a: 81a3 strh r3, [r4, #12] 801487c: 6126 str r6, [r4, #16] 801487e: 444e add r6, r9 8014880: 6026 str r6, [r4, #0] 8014882: 463e mov r6, r7 8014884: 6165 str r5, [r4, #20] 8014886: eba5 0509 sub.w r5, r5, r9 801488a: 60a5 str r5, [r4, #8] 801488c: 42be cmp r6, r7 801488e: d900 bls.n 8014892 <__ssputs_r+0x72> 8014890: 463e mov r6, r7 8014892: 4632 mov r2, r6 8014894: 4641 mov r1, r8 8014896: 6820 ldr r0, [r4, #0] 8014898: f001 f8ab bl 80159f2 801489c: 2000 movs r0, #0 801489e: 68a3 ldr r3, [r4, #8] 80148a0: 1b9b subs r3, r3, r6 80148a2: 60a3 str r3, [r4, #8] 80148a4: 6823 ldr r3, [r4, #0] 80148a6: 4433 add r3, r6 80148a8: 6023 str r3, [r4, #0] 80148aa: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80148ae: 462a mov r2, r5 80148b0: f000 ff7c bl 80157ac <_realloc_r> 80148b4: 4606 mov r6, r0 80148b6: 2800 cmp r0, #0 80148b8: d1e0 bne.n 801487c <__ssputs_r+0x5c> 80148ba: 4650 mov r0, sl 80148bc: 6921 ldr r1, [r4, #16] 80148be: f001 f947 bl 8015b50 <_free_r> 80148c2: 230c movs r3, #12 80148c4: f8ca 3000 str.w r3, [sl] 80148c8: 89a3 ldrh r3, [r4, #12] 80148ca: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80148ce: f043 0340 orr.w r3, r3, #64 @ 0x40 80148d2: 81a3 strh r3, [r4, #12] 80148d4: e7e9 b.n 80148aa <__ssputs_r+0x8a> ... 080148d8 <_svfiprintf_r>: 80148d8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80148dc: 4698 mov r8, r3 80148de: 898b ldrh r3, [r1, #12] 80148e0: 4607 mov r7, r0 80148e2: 061b lsls r3, r3, #24 80148e4: 460d mov r5, r1 80148e6: 4614 mov r4, r2 80148e8: b09d sub sp, #116 @ 0x74 80148ea: d510 bpl.n 801490e <_svfiprintf_r+0x36> 80148ec: 690b ldr r3, [r1, #16] 80148ee: b973 cbnz r3, 801490e <_svfiprintf_r+0x36> 80148f0: 2140 movs r1, #64 @ 0x40 80148f2: f000 fa57 bl 8014da4 <_malloc_r> 80148f6: 6028 str r0, [r5, #0] 80148f8: 6128 str r0, [r5, #16] 80148fa: b930 cbnz r0, 801490a <_svfiprintf_r+0x32> 80148fc: 230c movs r3, #12 80148fe: 603b str r3, [r7, #0] 8014900: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8014904: b01d add sp, #116 @ 0x74 8014906: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801490a: 2340 movs r3, #64 @ 0x40 801490c: 616b str r3, [r5, #20] 801490e: 2300 movs r3, #0 8014910: 9309 str r3, [sp, #36] @ 0x24 8014912: 2320 movs r3, #32 8014914: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8014918: 2330 movs r3, #48 @ 0x30 801491a: f04f 0901 mov.w r9, #1 801491e: f8cd 800c str.w r8, [sp, #12] 8014922: f8df 8198 ldr.w r8, [pc, #408] @ 8014abc <_svfiprintf_r+0x1e4> 8014926: f88d 302a strb.w r3, [sp, #42] @ 0x2a 801492a: 4623 mov r3, r4 801492c: 469a mov sl, r3 801492e: f813 2b01 ldrb.w r2, [r3], #1 8014932: b10a cbz r2, 8014938 <_svfiprintf_r+0x60> 8014934: 2a25 cmp r2, #37 @ 0x25 8014936: d1f9 bne.n 801492c <_svfiprintf_r+0x54> 8014938: ebba 0b04 subs.w fp, sl, r4 801493c: d00b beq.n 8014956 <_svfiprintf_r+0x7e> 801493e: 465b mov r3, fp 8014940: 4622 mov r2, r4 8014942: 4629 mov r1, r5 8014944: 4638 mov r0, r7 8014946: f7ff ff6b bl 8014820 <__ssputs_r> 801494a: 3001 adds r0, #1 801494c: f000 80a7 beq.w 8014a9e <_svfiprintf_r+0x1c6> 8014950: 9a09 ldr r2, [sp, #36] @ 0x24 8014952: 445a add r2, fp 8014954: 9209 str r2, [sp, #36] @ 0x24 8014956: f89a 3000 ldrb.w r3, [sl] 801495a: 2b00 cmp r3, #0 801495c: f000 809f beq.w 8014a9e <_svfiprintf_r+0x1c6> 8014960: 2300 movs r3, #0 8014962: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8014966: e9cd 2305 strd r2, r3, [sp, #20] 801496a: f10a 0a01 add.w sl, sl, #1 801496e: 9304 str r3, [sp, #16] 8014970: 9307 str r3, [sp, #28] 8014972: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8014976: 931a str r3, [sp, #104] @ 0x68 8014978: 4654 mov r4, sl 801497a: 2205 movs r2, #5 801497c: f814 1b01 ldrb.w r1, [r4], #1 8014980: 484e ldr r0, [pc, #312] @ (8014abc <_svfiprintf_r+0x1e4>) 8014982: f7ff f8b7 bl 8013af4 8014986: 9a04 ldr r2, [sp, #16] 8014988: b9d8 cbnz r0, 80149c2 <_svfiprintf_r+0xea> 801498a: 06d0 lsls r0, r2, #27 801498c: bf44 itt mi 801498e: 2320 movmi r3, #32 8014990: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8014994: 0711 lsls r1, r2, #28 8014996: bf44 itt mi 8014998: 232b movmi r3, #43 @ 0x2b 801499a: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 801499e: f89a 3000 ldrb.w r3, [sl] 80149a2: 2b2a cmp r3, #42 @ 0x2a 80149a4: d015 beq.n 80149d2 <_svfiprintf_r+0xfa> 80149a6: 4654 mov r4, sl 80149a8: 2000 movs r0, #0 80149aa: f04f 0c0a mov.w ip, #10 80149ae: 9a07 ldr r2, [sp, #28] 80149b0: 4621 mov r1, r4 80149b2: f811 3b01 ldrb.w r3, [r1], #1 80149b6: 3b30 subs r3, #48 @ 0x30 80149b8: 2b09 cmp r3, #9 80149ba: d94b bls.n 8014a54 <_svfiprintf_r+0x17c> 80149bc: b1b0 cbz r0, 80149ec <_svfiprintf_r+0x114> 80149be: 9207 str r2, [sp, #28] 80149c0: e014 b.n 80149ec <_svfiprintf_r+0x114> 80149c2: eba0 0308 sub.w r3, r0, r8 80149c6: fa09 f303 lsl.w r3, r9, r3 80149ca: 4313 orrs r3, r2 80149cc: 46a2 mov sl, r4 80149ce: 9304 str r3, [sp, #16] 80149d0: e7d2 b.n 8014978 <_svfiprintf_r+0xa0> 80149d2: 9b03 ldr r3, [sp, #12] 80149d4: 1d19 adds r1, r3, #4 80149d6: 681b ldr r3, [r3, #0] 80149d8: 9103 str r1, [sp, #12] 80149da: 2b00 cmp r3, #0 80149dc: bfbb ittet lt 80149de: 425b neglt r3, r3 80149e0: f042 0202 orrlt.w r2, r2, #2 80149e4: 9307 strge r3, [sp, #28] 80149e6: 9307 strlt r3, [sp, #28] 80149e8: bfb8 it lt 80149ea: 9204 strlt r2, [sp, #16] 80149ec: 7823 ldrb r3, [r4, #0] 80149ee: 2b2e cmp r3, #46 @ 0x2e 80149f0: d10a bne.n 8014a08 <_svfiprintf_r+0x130> 80149f2: 7863 ldrb r3, [r4, #1] 80149f4: 2b2a cmp r3, #42 @ 0x2a 80149f6: d132 bne.n 8014a5e <_svfiprintf_r+0x186> 80149f8: 9b03 ldr r3, [sp, #12] 80149fa: 3402 adds r4, #2 80149fc: 1d1a adds r2, r3, #4 80149fe: 681b ldr r3, [r3, #0] 8014a00: 9203 str r2, [sp, #12] 8014a02: ea43 73e3 orr.w r3, r3, r3, asr #31 8014a06: 9305 str r3, [sp, #20] 8014a08: f8df a0b4 ldr.w sl, [pc, #180] @ 8014ac0 <_svfiprintf_r+0x1e8> 8014a0c: 2203 movs r2, #3 8014a0e: 4650 mov r0, sl 8014a10: 7821 ldrb r1, [r4, #0] 8014a12: f7ff f86f bl 8013af4 8014a16: b138 cbz r0, 8014a28 <_svfiprintf_r+0x150> 8014a18: 2240 movs r2, #64 @ 0x40 8014a1a: 9b04 ldr r3, [sp, #16] 8014a1c: eba0 000a sub.w r0, r0, sl 8014a20: 4082 lsls r2, r0 8014a22: 4313 orrs r3, r2 8014a24: 3401 adds r4, #1 8014a26: 9304 str r3, [sp, #16] 8014a28: f814 1b01 ldrb.w r1, [r4], #1 8014a2c: 2206 movs r2, #6 8014a2e: 4825 ldr r0, [pc, #148] @ (8014ac4 <_svfiprintf_r+0x1ec>) 8014a30: f88d 1028 strb.w r1, [sp, #40] @ 0x28 8014a34: f7ff f85e bl 8013af4 8014a38: 2800 cmp r0, #0 8014a3a: d036 beq.n 8014aaa <_svfiprintf_r+0x1d2> 8014a3c: 4b22 ldr r3, [pc, #136] @ (8014ac8 <_svfiprintf_r+0x1f0>) 8014a3e: bb1b cbnz r3, 8014a88 <_svfiprintf_r+0x1b0> 8014a40: 9b03 ldr r3, [sp, #12] 8014a42: 3307 adds r3, #7 8014a44: f023 0307 bic.w r3, r3, #7 8014a48: 3308 adds r3, #8 8014a4a: 9303 str r3, [sp, #12] 8014a4c: 9b09 ldr r3, [sp, #36] @ 0x24 8014a4e: 4433 add r3, r6 8014a50: 9309 str r3, [sp, #36] @ 0x24 8014a52: e76a b.n 801492a <_svfiprintf_r+0x52> 8014a54: 460c mov r4, r1 8014a56: 2001 movs r0, #1 8014a58: fb0c 3202 mla r2, ip, r2, r3 8014a5c: e7a8 b.n 80149b0 <_svfiprintf_r+0xd8> 8014a5e: 2300 movs r3, #0 8014a60: f04f 0c0a mov.w ip, #10 8014a64: 4619 mov r1, r3 8014a66: 3401 adds r4, #1 8014a68: 9305 str r3, [sp, #20] 8014a6a: 4620 mov r0, r4 8014a6c: f810 2b01 ldrb.w r2, [r0], #1 8014a70: 3a30 subs r2, #48 @ 0x30 8014a72: 2a09 cmp r2, #9 8014a74: d903 bls.n 8014a7e <_svfiprintf_r+0x1a6> 8014a76: 2b00 cmp r3, #0 8014a78: d0c6 beq.n 8014a08 <_svfiprintf_r+0x130> 8014a7a: 9105 str r1, [sp, #20] 8014a7c: e7c4 b.n 8014a08 <_svfiprintf_r+0x130> 8014a7e: 4604 mov r4, r0 8014a80: 2301 movs r3, #1 8014a82: fb0c 2101 mla r1, ip, r1, r2 8014a86: e7f0 b.n 8014a6a <_svfiprintf_r+0x192> 8014a88: ab03 add r3, sp, #12 8014a8a: 9300 str r3, [sp, #0] 8014a8c: 462a mov r2, r5 8014a8e: 4638 mov r0, r7 8014a90: 4b0e ldr r3, [pc, #56] @ (8014acc <_svfiprintf_r+0x1f4>) 8014a92: a904 add r1, sp, #16 8014a94: f7fe fb28 bl 80130e8 <_printf_float> 8014a98: 1c42 adds r2, r0, #1 8014a9a: 4606 mov r6, r0 8014a9c: d1d6 bne.n 8014a4c <_svfiprintf_r+0x174> 8014a9e: 89ab ldrh r3, [r5, #12] 8014aa0: 065b lsls r3, r3, #25 8014aa2: f53f af2d bmi.w 8014900 <_svfiprintf_r+0x28> 8014aa6: 9809 ldr r0, [sp, #36] @ 0x24 8014aa8: e72c b.n 8014904 <_svfiprintf_r+0x2c> 8014aaa: ab03 add r3, sp, #12 8014aac: 9300 str r3, [sp, #0] 8014aae: 462a mov r2, r5 8014ab0: 4638 mov r0, r7 8014ab2: 4b06 ldr r3, [pc, #24] @ (8014acc <_svfiprintf_r+0x1f4>) 8014ab4: a904 add r1, sp, #16 8014ab6: f7fe fdb5 bl 8013624 <_printf_i> 8014aba: e7ed b.n 8014a98 <_svfiprintf_r+0x1c0> 8014abc: 08016245 .word 0x08016245 8014ac0: 0801624b .word 0x0801624b 8014ac4: 0801624f .word 0x0801624f 8014ac8: 080130e9 .word 0x080130e9 8014acc: 08014821 .word 0x08014821 08014ad0 <__sfputc_r>: 8014ad0: 6893 ldr r3, [r2, #8] 8014ad2: b410 push {r4} 8014ad4: 3b01 subs r3, #1 8014ad6: 2b00 cmp r3, #0 8014ad8: 6093 str r3, [r2, #8] 8014ada: da07 bge.n 8014aec <__sfputc_r+0x1c> 8014adc: 6994 ldr r4, [r2, #24] 8014ade: 42a3 cmp r3, r4 8014ae0: db01 blt.n 8014ae6 <__sfputc_r+0x16> 8014ae2: 290a cmp r1, #10 8014ae4: d102 bne.n 8014aec <__sfputc_r+0x1c> 8014ae6: bc10 pop {r4} 8014ae8: f000 be8e b.w 8015808 <__swbuf_r> 8014aec: 6813 ldr r3, [r2, #0] 8014aee: 1c58 adds r0, r3, #1 8014af0: 6010 str r0, [r2, #0] 8014af2: 7019 strb r1, [r3, #0] 8014af4: 4608 mov r0, r1 8014af6: bc10 pop {r4} 8014af8: 4770 bx lr 08014afa <__sfputs_r>: 8014afa: b5f8 push {r3, r4, r5, r6, r7, lr} 8014afc: 4606 mov r6, r0 8014afe: 460f mov r7, r1 8014b00: 4614 mov r4, r2 8014b02: 18d5 adds r5, r2, r3 8014b04: 42ac cmp r4, r5 8014b06: d101 bne.n 8014b0c <__sfputs_r+0x12> 8014b08: 2000 movs r0, #0 8014b0a: e007 b.n 8014b1c <__sfputs_r+0x22> 8014b0c: 463a mov r2, r7 8014b0e: 4630 mov r0, r6 8014b10: f814 1b01 ldrb.w r1, [r4], #1 8014b14: f7ff ffdc bl 8014ad0 <__sfputc_r> 8014b18: 1c43 adds r3, r0, #1 8014b1a: d1f3 bne.n 8014b04 <__sfputs_r+0xa> 8014b1c: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 08014b20 <_vfiprintf_r>: 8014b20: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8014b24: 460d mov r5, r1 8014b26: 4614 mov r4, r2 8014b28: 4698 mov r8, r3 8014b2a: 4606 mov r6, r0 8014b2c: b09d sub sp, #116 @ 0x74 8014b2e: b118 cbz r0, 8014b38 <_vfiprintf_r+0x18> 8014b30: 6a03 ldr r3, [r0, #32] 8014b32: b90b cbnz r3, 8014b38 <_vfiprintf_r+0x18> 8014b34: f7fe ff20 bl 8013978 <__sinit> 8014b38: 6e6b ldr r3, [r5, #100] @ 0x64 8014b3a: 07d9 lsls r1, r3, #31 8014b3c: d405 bmi.n 8014b4a <_vfiprintf_r+0x2a> 8014b3e: 89ab ldrh r3, [r5, #12] 8014b40: 059a lsls r2, r3, #22 8014b42: d402 bmi.n 8014b4a <_vfiprintf_r+0x2a> 8014b44: 6da8 ldr r0, [r5, #88] @ 0x58 8014b46: f7fe ffce bl 8013ae6 <__retarget_lock_acquire_recursive> 8014b4a: 89ab ldrh r3, [r5, #12] 8014b4c: 071b lsls r3, r3, #28 8014b4e: d501 bpl.n 8014b54 <_vfiprintf_r+0x34> 8014b50: 692b ldr r3, [r5, #16] 8014b52: b99b cbnz r3, 8014b7c <_vfiprintf_r+0x5c> 8014b54: 4629 mov r1, r5 8014b56: 4630 mov r0, r6 8014b58: f000 fe94 bl 8015884 <__swsetup_r> 8014b5c: b170 cbz r0, 8014b7c <_vfiprintf_r+0x5c> 8014b5e: 6e6b ldr r3, [r5, #100] @ 0x64 8014b60: 07dc lsls r4, r3, #31 8014b62: d504 bpl.n 8014b6e <_vfiprintf_r+0x4e> 8014b64: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8014b68: b01d add sp, #116 @ 0x74 8014b6a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8014b6e: 89ab ldrh r3, [r5, #12] 8014b70: 0598 lsls r0, r3, #22 8014b72: d4f7 bmi.n 8014b64 <_vfiprintf_r+0x44> 8014b74: 6da8 ldr r0, [r5, #88] @ 0x58 8014b76: f7fe ffb7 bl 8013ae8 <__retarget_lock_release_recursive> 8014b7a: e7f3 b.n 8014b64 <_vfiprintf_r+0x44> 8014b7c: 2300 movs r3, #0 8014b7e: 9309 str r3, [sp, #36] @ 0x24 8014b80: 2320 movs r3, #32 8014b82: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8014b86: 2330 movs r3, #48 @ 0x30 8014b88: f04f 0901 mov.w r9, #1 8014b8c: f8cd 800c str.w r8, [sp, #12] 8014b90: f8df 81a8 ldr.w r8, [pc, #424] @ 8014d3c <_vfiprintf_r+0x21c> 8014b94: f88d 302a strb.w r3, [sp, #42] @ 0x2a 8014b98: 4623 mov r3, r4 8014b9a: 469a mov sl, r3 8014b9c: f813 2b01 ldrb.w r2, [r3], #1 8014ba0: b10a cbz r2, 8014ba6 <_vfiprintf_r+0x86> 8014ba2: 2a25 cmp r2, #37 @ 0x25 8014ba4: d1f9 bne.n 8014b9a <_vfiprintf_r+0x7a> 8014ba6: ebba 0b04 subs.w fp, sl, r4 8014baa: d00b beq.n 8014bc4 <_vfiprintf_r+0xa4> 8014bac: 465b mov r3, fp 8014bae: 4622 mov r2, r4 8014bb0: 4629 mov r1, r5 8014bb2: 4630 mov r0, r6 8014bb4: f7ff ffa1 bl 8014afa <__sfputs_r> 8014bb8: 3001 adds r0, #1 8014bba: f000 80a7 beq.w 8014d0c <_vfiprintf_r+0x1ec> 8014bbe: 9a09 ldr r2, [sp, #36] @ 0x24 8014bc0: 445a add r2, fp 8014bc2: 9209 str r2, [sp, #36] @ 0x24 8014bc4: f89a 3000 ldrb.w r3, [sl] 8014bc8: 2b00 cmp r3, #0 8014bca: f000 809f beq.w 8014d0c <_vfiprintf_r+0x1ec> 8014bce: 2300 movs r3, #0 8014bd0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8014bd4: e9cd 2305 strd r2, r3, [sp, #20] 8014bd8: f10a 0a01 add.w sl, sl, #1 8014bdc: 9304 str r3, [sp, #16] 8014bde: 9307 str r3, [sp, #28] 8014be0: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8014be4: 931a str r3, [sp, #104] @ 0x68 8014be6: 4654 mov r4, sl 8014be8: 2205 movs r2, #5 8014bea: f814 1b01 ldrb.w r1, [r4], #1 8014bee: 4853 ldr r0, [pc, #332] @ (8014d3c <_vfiprintf_r+0x21c>) 8014bf0: f7fe ff80 bl 8013af4 8014bf4: 9a04 ldr r2, [sp, #16] 8014bf6: b9d8 cbnz r0, 8014c30 <_vfiprintf_r+0x110> 8014bf8: 06d1 lsls r1, r2, #27 8014bfa: bf44 itt mi 8014bfc: 2320 movmi r3, #32 8014bfe: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8014c02: 0713 lsls r3, r2, #28 8014c04: bf44 itt mi 8014c06: 232b movmi r3, #43 @ 0x2b 8014c08: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8014c0c: f89a 3000 ldrb.w r3, [sl] 8014c10: 2b2a cmp r3, #42 @ 0x2a 8014c12: d015 beq.n 8014c40 <_vfiprintf_r+0x120> 8014c14: 4654 mov r4, sl 8014c16: 2000 movs r0, #0 8014c18: f04f 0c0a mov.w ip, #10 8014c1c: 9a07 ldr r2, [sp, #28] 8014c1e: 4621 mov r1, r4 8014c20: f811 3b01 ldrb.w r3, [r1], #1 8014c24: 3b30 subs r3, #48 @ 0x30 8014c26: 2b09 cmp r3, #9 8014c28: d94b bls.n 8014cc2 <_vfiprintf_r+0x1a2> 8014c2a: b1b0 cbz r0, 8014c5a <_vfiprintf_r+0x13a> 8014c2c: 9207 str r2, [sp, #28] 8014c2e: e014 b.n 8014c5a <_vfiprintf_r+0x13a> 8014c30: eba0 0308 sub.w r3, r0, r8 8014c34: fa09 f303 lsl.w r3, r9, r3 8014c38: 4313 orrs r3, r2 8014c3a: 46a2 mov sl, r4 8014c3c: 9304 str r3, [sp, #16] 8014c3e: e7d2 b.n 8014be6 <_vfiprintf_r+0xc6> 8014c40: 9b03 ldr r3, [sp, #12] 8014c42: 1d19 adds r1, r3, #4 8014c44: 681b ldr r3, [r3, #0] 8014c46: 9103 str r1, [sp, #12] 8014c48: 2b00 cmp r3, #0 8014c4a: bfbb ittet lt 8014c4c: 425b neglt r3, r3 8014c4e: f042 0202 orrlt.w r2, r2, #2 8014c52: 9307 strge r3, [sp, #28] 8014c54: 9307 strlt r3, [sp, #28] 8014c56: bfb8 it lt 8014c58: 9204 strlt r2, [sp, #16] 8014c5a: 7823 ldrb r3, [r4, #0] 8014c5c: 2b2e cmp r3, #46 @ 0x2e 8014c5e: d10a bne.n 8014c76 <_vfiprintf_r+0x156> 8014c60: 7863 ldrb r3, [r4, #1] 8014c62: 2b2a cmp r3, #42 @ 0x2a 8014c64: d132 bne.n 8014ccc <_vfiprintf_r+0x1ac> 8014c66: 9b03 ldr r3, [sp, #12] 8014c68: 3402 adds r4, #2 8014c6a: 1d1a adds r2, r3, #4 8014c6c: 681b ldr r3, [r3, #0] 8014c6e: 9203 str r2, [sp, #12] 8014c70: ea43 73e3 orr.w r3, r3, r3, asr #31 8014c74: 9305 str r3, [sp, #20] 8014c76: f8df a0c8 ldr.w sl, [pc, #200] @ 8014d40 <_vfiprintf_r+0x220> 8014c7a: 2203 movs r2, #3 8014c7c: 4650 mov r0, sl 8014c7e: 7821 ldrb r1, [r4, #0] 8014c80: f7fe ff38 bl 8013af4 8014c84: b138 cbz r0, 8014c96 <_vfiprintf_r+0x176> 8014c86: 2240 movs r2, #64 @ 0x40 8014c88: 9b04 ldr r3, [sp, #16] 8014c8a: eba0 000a sub.w r0, r0, sl 8014c8e: 4082 lsls r2, r0 8014c90: 4313 orrs r3, r2 8014c92: 3401 adds r4, #1 8014c94: 9304 str r3, [sp, #16] 8014c96: f814 1b01 ldrb.w r1, [r4], #1 8014c9a: 2206 movs r2, #6 8014c9c: 4829 ldr r0, [pc, #164] @ (8014d44 <_vfiprintf_r+0x224>) 8014c9e: f88d 1028 strb.w r1, [sp, #40] @ 0x28 8014ca2: f7fe ff27 bl 8013af4 8014ca6: 2800 cmp r0, #0 8014ca8: d03f beq.n 8014d2a <_vfiprintf_r+0x20a> 8014caa: 4b27 ldr r3, [pc, #156] @ (8014d48 <_vfiprintf_r+0x228>) 8014cac: bb1b cbnz r3, 8014cf6 <_vfiprintf_r+0x1d6> 8014cae: 9b03 ldr r3, [sp, #12] 8014cb0: 3307 adds r3, #7 8014cb2: f023 0307 bic.w r3, r3, #7 8014cb6: 3308 adds r3, #8 8014cb8: 9303 str r3, [sp, #12] 8014cba: 9b09 ldr r3, [sp, #36] @ 0x24 8014cbc: 443b add r3, r7 8014cbe: 9309 str r3, [sp, #36] @ 0x24 8014cc0: e76a b.n 8014b98 <_vfiprintf_r+0x78> 8014cc2: 460c mov r4, r1 8014cc4: 2001 movs r0, #1 8014cc6: fb0c 3202 mla r2, ip, r2, r3 8014cca: e7a8 b.n 8014c1e <_vfiprintf_r+0xfe> 8014ccc: 2300 movs r3, #0 8014cce: f04f 0c0a mov.w ip, #10 8014cd2: 4619 mov r1, r3 8014cd4: 3401 adds r4, #1 8014cd6: 9305 str r3, [sp, #20] 8014cd8: 4620 mov r0, r4 8014cda: f810 2b01 ldrb.w r2, [r0], #1 8014cde: 3a30 subs r2, #48 @ 0x30 8014ce0: 2a09 cmp r2, #9 8014ce2: d903 bls.n 8014cec <_vfiprintf_r+0x1cc> 8014ce4: 2b00 cmp r3, #0 8014ce6: d0c6 beq.n 8014c76 <_vfiprintf_r+0x156> 8014ce8: 9105 str r1, [sp, #20] 8014cea: e7c4 b.n 8014c76 <_vfiprintf_r+0x156> 8014cec: 4604 mov r4, r0 8014cee: 2301 movs r3, #1 8014cf0: fb0c 2101 mla r1, ip, r1, r2 8014cf4: e7f0 b.n 8014cd8 <_vfiprintf_r+0x1b8> 8014cf6: ab03 add r3, sp, #12 8014cf8: 9300 str r3, [sp, #0] 8014cfa: 462a mov r2, r5 8014cfc: 4630 mov r0, r6 8014cfe: 4b13 ldr r3, [pc, #76] @ (8014d4c <_vfiprintf_r+0x22c>) 8014d00: a904 add r1, sp, #16 8014d02: f7fe f9f1 bl 80130e8 <_printf_float> 8014d06: 4607 mov r7, r0 8014d08: 1c78 adds r0, r7, #1 8014d0a: d1d6 bne.n 8014cba <_vfiprintf_r+0x19a> 8014d0c: 6e6b ldr r3, [r5, #100] @ 0x64 8014d0e: 07d9 lsls r1, r3, #31 8014d10: d405 bmi.n 8014d1e <_vfiprintf_r+0x1fe> 8014d12: 89ab ldrh r3, [r5, #12] 8014d14: 059a lsls r2, r3, #22 8014d16: d402 bmi.n 8014d1e <_vfiprintf_r+0x1fe> 8014d18: 6da8 ldr r0, [r5, #88] @ 0x58 8014d1a: f7fe fee5 bl 8013ae8 <__retarget_lock_release_recursive> 8014d1e: 89ab ldrh r3, [r5, #12] 8014d20: 065b lsls r3, r3, #25 8014d22: f53f af1f bmi.w 8014b64 <_vfiprintf_r+0x44> 8014d26: 9809 ldr r0, [sp, #36] @ 0x24 8014d28: e71e b.n 8014b68 <_vfiprintf_r+0x48> 8014d2a: ab03 add r3, sp, #12 8014d2c: 9300 str r3, [sp, #0] 8014d2e: 462a mov r2, r5 8014d30: 4630 mov r0, r6 8014d32: 4b06 ldr r3, [pc, #24] @ (8014d4c <_vfiprintf_r+0x22c>) 8014d34: a904 add r1, sp, #16 8014d36: f7fe fc75 bl 8013624 <_printf_i> 8014d3a: e7e4 b.n 8014d06 <_vfiprintf_r+0x1e6> 8014d3c: 08016245 .word 0x08016245 8014d40: 0801624b .word 0x0801624b 8014d44: 0801624f .word 0x0801624f 8014d48: 080130e9 .word 0x080130e9 8014d4c: 08014afb .word 0x08014afb 08014d50 : 8014d50: 4b02 ldr r3, [pc, #8] @ (8014d5c ) 8014d52: 4601 mov r1, r0 8014d54: 6818 ldr r0, [r3, #0] 8014d56: f000 b825 b.w 8014da4 <_malloc_r> 8014d5a: bf00 nop 8014d5c: 20000084 .word 0x20000084 08014d60 : 8014d60: b570 push {r4, r5, r6, lr} 8014d62: 4e0f ldr r6, [pc, #60] @ (8014da0 ) 8014d64: 460c mov r4, r1 8014d66: 6831 ldr r1, [r6, #0] 8014d68: 4605 mov r5, r0 8014d6a: b911 cbnz r1, 8014d72 8014d6c: f000 fe90 bl 8015a90 <_sbrk_r> 8014d70: 6030 str r0, [r6, #0] 8014d72: 4621 mov r1, r4 8014d74: 4628 mov r0, r5 8014d76: f000 fe8b bl 8015a90 <_sbrk_r> 8014d7a: 1c43 adds r3, r0, #1 8014d7c: d103 bne.n 8014d86 8014d7e: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 8014d82: 4620 mov r0, r4 8014d84: bd70 pop {r4, r5, r6, pc} 8014d86: 1cc4 adds r4, r0, #3 8014d88: f024 0403 bic.w r4, r4, #3 8014d8c: 42a0 cmp r0, r4 8014d8e: d0f8 beq.n 8014d82 8014d90: 1a21 subs r1, r4, r0 8014d92: 4628 mov r0, r5 8014d94: f000 fe7c bl 8015a90 <_sbrk_r> 8014d98: 3001 adds r0, #1 8014d9a: d1f2 bne.n 8014d82 8014d9c: e7ef b.n 8014d7e 8014d9e: bf00 nop 8014da0: 20001320 .word 0x20001320 08014da4 <_malloc_r>: 8014da4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8014da8: 1ccd adds r5, r1, #3 8014daa: f025 0503 bic.w r5, r5, #3 8014dae: 3508 adds r5, #8 8014db0: 2d0c cmp r5, #12 8014db2: bf38 it cc 8014db4: 250c movcc r5, #12 8014db6: 2d00 cmp r5, #0 8014db8: 4606 mov r6, r0 8014dba: db01 blt.n 8014dc0 <_malloc_r+0x1c> 8014dbc: 42a9 cmp r1, r5 8014dbe: d904 bls.n 8014dca <_malloc_r+0x26> 8014dc0: 230c movs r3, #12 8014dc2: 6033 str r3, [r6, #0] 8014dc4: 2000 movs r0, #0 8014dc6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8014dca: f8df 80d4 ldr.w r8, [pc, #212] @ 8014ea0 <_malloc_r+0xfc> 8014dce: f000 f911 bl 8014ff4 <__malloc_lock> 8014dd2: f8d8 3000 ldr.w r3, [r8] 8014dd6: 461c mov r4, r3 8014dd8: bb44 cbnz r4, 8014e2c <_malloc_r+0x88> 8014dda: 4629 mov r1, r5 8014ddc: 4630 mov r0, r6 8014dde: f7ff ffbf bl 8014d60 8014de2: 1c43 adds r3, r0, #1 8014de4: 4604 mov r4, r0 8014de6: d158 bne.n 8014e9a <_malloc_r+0xf6> 8014de8: f8d8 4000 ldr.w r4, [r8] 8014dec: 4627 mov r7, r4 8014dee: 2f00 cmp r7, #0 8014df0: d143 bne.n 8014e7a <_malloc_r+0xd6> 8014df2: 2c00 cmp r4, #0 8014df4: d04b beq.n 8014e8e <_malloc_r+0xea> 8014df6: 6823 ldr r3, [r4, #0] 8014df8: 4639 mov r1, r7 8014dfa: 4630 mov r0, r6 8014dfc: eb04 0903 add.w r9, r4, r3 8014e00: f000 fe46 bl 8015a90 <_sbrk_r> 8014e04: 4581 cmp r9, r0 8014e06: d142 bne.n 8014e8e <_malloc_r+0xea> 8014e08: 6821 ldr r1, [r4, #0] 8014e0a: 4630 mov r0, r6 8014e0c: 1a6d subs r5, r5, r1 8014e0e: 4629 mov r1, r5 8014e10: f7ff ffa6 bl 8014d60 8014e14: 3001 adds r0, #1 8014e16: d03a beq.n 8014e8e <_malloc_r+0xea> 8014e18: 6823 ldr r3, [r4, #0] 8014e1a: 442b add r3, r5 8014e1c: 6023 str r3, [r4, #0] 8014e1e: f8d8 3000 ldr.w r3, [r8] 8014e22: 685a ldr r2, [r3, #4] 8014e24: bb62 cbnz r2, 8014e80 <_malloc_r+0xdc> 8014e26: f8c8 7000 str.w r7, [r8] 8014e2a: e00f b.n 8014e4c <_malloc_r+0xa8> 8014e2c: 6822 ldr r2, [r4, #0] 8014e2e: 1b52 subs r2, r2, r5 8014e30: d420 bmi.n 8014e74 <_malloc_r+0xd0> 8014e32: 2a0b cmp r2, #11 8014e34: d917 bls.n 8014e66 <_malloc_r+0xc2> 8014e36: 1961 adds r1, r4, r5 8014e38: 42a3 cmp r3, r4 8014e3a: 6025 str r5, [r4, #0] 8014e3c: bf18 it ne 8014e3e: 6059 strne r1, [r3, #4] 8014e40: 6863 ldr r3, [r4, #4] 8014e42: bf08 it eq 8014e44: f8c8 1000 streq.w r1, [r8] 8014e48: 5162 str r2, [r4, r5] 8014e4a: 604b str r3, [r1, #4] 8014e4c: 4630 mov r0, r6 8014e4e: f000 f8d7 bl 8015000 <__malloc_unlock> 8014e52: f104 000b add.w r0, r4, #11 8014e56: 1d23 adds r3, r4, #4 8014e58: f020 0007 bic.w r0, r0, #7 8014e5c: 1ac2 subs r2, r0, r3 8014e5e: bf1c itt ne 8014e60: 1a1b subne r3, r3, r0 8014e62: 50a3 strne r3, [r4, r2] 8014e64: e7af b.n 8014dc6 <_malloc_r+0x22> 8014e66: 6862 ldr r2, [r4, #4] 8014e68: 42a3 cmp r3, r4 8014e6a: bf0c ite eq 8014e6c: f8c8 2000 streq.w r2, [r8] 8014e70: 605a strne r2, [r3, #4] 8014e72: e7eb b.n 8014e4c <_malloc_r+0xa8> 8014e74: 4623 mov r3, r4 8014e76: 6864 ldr r4, [r4, #4] 8014e78: e7ae b.n 8014dd8 <_malloc_r+0x34> 8014e7a: 463c mov r4, r7 8014e7c: 687f ldr r7, [r7, #4] 8014e7e: e7b6 b.n 8014dee <_malloc_r+0x4a> 8014e80: 461a mov r2, r3 8014e82: 685b ldr r3, [r3, #4] 8014e84: 42a3 cmp r3, r4 8014e86: d1fb bne.n 8014e80 <_malloc_r+0xdc> 8014e88: 2300 movs r3, #0 8014e8a: 6053 str r3, [r2, #4] 8014e8c: e7de b.n 8014e4c <_malloc_r+0xa8> 8014e8e: 230c movs r3, #12 8014e90: 4630 mov r0, r6 8014e92: 6033 str r3, [r6, #0] 8014e94: f000 f8b4 bl 8015000 <__malloc_unlock> 8014e98: e794 b.n 8014dc4 <_malloc_r+0x20> 8014e9a: 6005 str r5, [r0, #0] 8014e9c: e7d6 b.n 8014e4c <_malloc_r+0xa8> 8014e9e: bf00 nop 8014ea0: 20001324 .word 0x20001324 08014ea4 <__sflush_r>: 8014ea4: f9b1 200c ldrsh.w r2, [r1, #12] 8014ea8: b5f8 push {r3, r4, r5, r6, r7, lr} 8014eaa: 0716 lsls r6, r2, #28 8014eac: 4605 mov r5, r0 8014eae: 460c mov r4, r1 8014eb0: d454 bmi.n 8014f5c <__sflush_r+0xb8> 8014eb2: 684b ldr r3, [r1, #4] 8014eb4: 2b00 cmp r3, #0 8014eb6: dc02 bgt.n 8014ebe <__sflush_r+0x1a> 8014eb8: 6c0b ldr r3, [r1, #64] @ 0x40 8014eba: 2b00 cmp r3, #0 8014ebc: dd48 ble.n 8014f50 <__sflush_r+0xac> 8014ebe: 6ae6 ldr r6, [r4, #44] @ 0x2c 8014ec0: 2e00 cmp r6, #0 8014ec2: d045 beq.n 8014f50 <__sflush_r+0xac> 8014ec4: 2300 movs r3, #0 8014ec6: f412 5280 ands.w r2, r2, #4096 @ 0x1000 8014eca: 682f ldr r7, [r5, #0] 8014ecc: 6a21 ldr r1, [r4, #32] 8014ece: 602b str r3, [r5, #0] 8014ed0: d030 beq.n 8014f34 <__sflush_r+0x90> 8014ed2: 6d62 ldr r2, [r4, #84] @ 0x54 8014ed4: 89a3 ldrh r3, [r4, #12] 8014ed6: 0759 lsls r1, r3, #29 8014ed8: d505 bpl.n 8014ee6 <__sflush_r+0x42> 8014eda: 6863 ldr r3, [r4, #4] 8014edc: 1ad2 subs r2, r2, r3 8014ede: 6b63 ldr r3, [r4, #52] @ 0x34 8014ee0: b10b cbz r3, 8014ee6 <__sflush_r+0x42> 8014ee2: 6c23 ldr r3, [r4, #64] @ 0x40 8014ee4: 1ad2 subs r2, r2, r3 8014ee6: 2300 movs r3, #0 8014ee8: 4628 mov r0, r5 8014eea: 6ae6 ldr r6, [r4, #44] @ 0x2c 8014eec: 6a21 ldr r1, [r4, #32] 8014eee: 47b0 blx r6 8014ef0: 1c43 adds r3, r0, #1 8014ef2: 89a3 ldrh r3, [r4, #12] 8014ef4: d106 bne.n 8014f04 <__sflush_r+0x60> 8014ef6: 6829 ldr r1, [r5, #0] 8014ef8: 291d cmp r1, #29 8014efa: d82b bhi.n 8014f54 <__sflush_r+0xb0> 8014efc: 4a28 ldr r2, [pc, #160] @ (8014fa0 <__sflush_r+0xfc>) 8014efe: 40ca lsrs r2, r1 8014f00: 07d6 lsls r6, r2, #31 8014f02: d527 bpl.n 8014f54 <__sflush_r+0xb0> 8014f04: 2200 movs r2, #0 8014f06: 6062 str r2, [r4, #4] 8014f08: 6922 ldr r2, [r4, #16] 8014f0a: 04d9 lsls r1, r3, #19 8014f0c: 6022 str r2, [r4, #0] 8014f0e: d504 bpl.n 8014f1a <__sflush_r+0x76> 8014f10: 1c42 adds r2, r0, #1 8014f12: d101 bne.n 8014f18 <__sflush_r+0x74> 8014f14: 682b ldr r3, [r5, #0] 8014f16: b903 cbnz r3, 8014f1a <__sflush_r+0x76> 8014f18: 6560 str r0, [r4, #84] @ 0x54 8014f1a: 6b61 ldr r1, [r4, #52] @ 0x34 8014f1c: 602f str r7, [r5, #0] 8014f1e: b1b9 cbz r1, 8014f50 <__sflush_r+0xac> 8014f20: f104 0344 add.w r3, r4, #68 @ 0x44 8014f24: 4299 cmp r1, r3 8014f26: d002 beq.n 8014f2e <__sflush_r+0x8a> 8014f28: 4628 mov r0, r5 8014f2a: f000 fe11 bl 8015b50 <_free_r> 8014f2e: 2300 movs r3, #0 8014f30: 6363 str r3, [r4, #52] @ 0x34 8014f32: e00d b.n 8014f50 <__sflush_r+0xac> 8014f34: 2301 movs r3, #1 8014f36: 4628 mov r0, r5 8014f38: 47b0 blx r6 8014f3a: 4602 mov r2, r0 8014f3c: 1c50 adds r0, r2, #1 8014f3e: d1c9 bne.n 8014ed4 <__sflush_r+0x30> 8014f40: 682b ldr r3, [r5, #0] 8014f42: 2b00 cmp r3, #0 8014f44: d0c6 beq.n 8014ed4 <__sflush_r+0x30> 8014f46: 2b1d cmp r3, #29 8014f48: d001 beq.n 8014f4e <__sflush_r+0xaa> 8014f4a: 2b16 cmp r3, #22 8014f4c: d11d bne.n 8014f8a <__sflush_r+0xe6> 8014f4e: 602f str r7, [r5, #0] 8014f50: 2000 movs r0, #0 8014f52: e021 b.n 8014f98 <__sflush_r+0xf4> 8014f54: f043 0340 orr.w r3, r3, #64 @ 0x40 8014f58: b21b sxth r3, r3 8014f5a: e01a b.n 8014f92 <__sflush_r+0xee> 8014f5c: 690f ldr r7, [r1, #16] 8014f5e: 2f00 cmp r7, #0 8014f60: d0f6 beq.n 8014f50 <__sflush_r+0xac> 8014f62: 0793 lsls r3, r2, #30 8014f64: bf18 it ne 8014f66: 2300 movne r3, #0 8014f68: 680e ldr r6, [r1, #0] 8014f6a: bf08 it eq 8014f6c: 694b ldreq r3, [r1, #20] 8014f6e: 1bf6 subs r6, r6, r7 8014f70: 600f str r7, [r1, #0] 8014f72: 608b str r3, [r1, #8] 8014f74: 2e00 cmp r6, #0 8014f76: ddeb ble.n 8014f50 <__sflush_r+0xac> 8014f78: 4633 mov r3, r6 8014f7a: 463a mov r2, r7 8014f7c: 4628 mov r0, r5 8014f7e: 6a21 ldr r1, [r4, #32] 8014f80: f8d4 c028 ldr.w ip, [r4, #40] @ 0x28 8014f84: 47e0 blx ip 8014f86: 2800 cmp r0, #0 8014f88: dc07 bgt.n 8014f9a <__sflush_r+0xf6> 8014f8a: f9b4 300c ldrsh.w r3, [r4, #12] 8014f8e: f043 0340 orr.w r3, r3, #64 @ 0x40 8014f92: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8014f96: 81a3 strh r3, [r4, #12] 8014f98: bdf8 pop {r3, r4, r5, r6, r7, pc} 8014f9a: 4407 add r7, r0 8014f9c: 1a36 subs r6, r6, r0 8014f9e: e7e9 b.n 8014f74 <__sflush_r+0xd0> 8014fa0: 20400001 .word 0x20400001 08014fa4 <_fflush_r>: 8014fa4: b538 push {r3, r4, r5, lr} 8014fa6: 690b ldr r3, [r1, #16] 8014fa8: 4605 mov r5, r0 8014faa: 460c mov r4, r1 8014fac: b913 cbnz r3, 8014fb4 <_fflush_r+0x10> 8014fae: 2500 movs r5, #0 8014fb0: 4628 mov r0, r5 8014fb2: bd38 pop {r3, r4, r5, pc} 8014fb4: b118 cbz r0, 8014fbe <_fflush_r+0x1a> 8014fb6: 6a03 ldr r3, [r0, #32] 8014fb8: b90b cbnz r3, 8014fbe <_fflush_r+0x1a> 8014fba: f7fe fcdd bl 8013978 <__sinit> 8014fbe: f9b4 300c ldrsh.w r3, [r4, #12] 8014fc2: 2b00 cmp r3, #0 8014fc4: d0f3 beq.n 8014fae <_fflush_r+0xa> 8014fc6: 6e62 ldr r2, [r4, #100] @ 0x64 8014fc8: 07d0 lsls r0, r2, #31 8014fca: d404 bmi.n 8014fd6 <_fflush_r+0x32> 8014fcc: 0599 lsls r1, r3, #22 8014fce: d402 bmi.n 8014fd6 <_fflush_r+0x32> 8014fd0: 6da0 ldr r0, [r4, #88] @ 0x58 8014fd2: f7fe fd88 bl 8013ae6 <__retarget_lock_acquire_recursive> 8014fd6: 4628 mov r0, r5 8014fd8: 4621 mov r1, r4 8014fda: f7ff ff63 bl 8014ea4 <__sflush_r> 8014fde: 6e63 ldr r3, [r4, #100] @ 0x64 8014fe0: 4605 mov r5, r0 8014fe2: 07da lsls r2, r3, #31 8014fe4: d4e4 bmi.n 8014fb0 <_fflush_r+0xc> 8014fe6: 89a3 ldrh r3, [r4, #12] 8014fe8: 059b lsls r3, r3, #22 8014fea: d4e1 bmi.n 8014fb0 <_fflush_r+0xc> 8014fec: 6da0 ldr r0, [r4, #88] @ 0x58 8014fee: f7fe fd7b bl 8013ae8 <__retarget_lock_release_recursive> 8014ff2: e7dd b.n 8014fb0 <_fflush_r+0xc> 08014ff4 <__malloc_lock>: 8014ff4: 4801 ldr r0, [pc, #4] @ (8014ffc <__malloc_lock+0x8>) 8014ff6: f7fe bd76 b.w 8013ae6 <__retarget_lock_acquire_recursive> 8014ffa: bf00 nop 8014ffc: 2000131c .word 0x2000131c 08015000 <__malloc_unlock>: 8015000: 4801 ldr r0, [pc, #4] @ (8015008 <__malloc_unlock+0x8>) 8015002: f7fe bd71 b.w 8013ae8 <__retarget_lock_release_recursive> 8015006: bf00 nop 8015008: 2000131c .word 0x2000131c 0801500c <_Balloc>: 801500c: b570 push {r4, r5, r6, lr} 801500e: 69c6 ldr r6, [r0, #28] 8015010: 4604 mov r4, r0 8015012: 460d mov r5, r1 8015014: b976 cbnz r6, 8015034 <_Balloc+0x28> 8015016: 2010 movs r0, #16 8015018: f7ff fe9a bl 8014d50 801501c: 4602 mov r2, r0 801501e: 61e0 str r0, [r4, #28] 8015020: b920 cbnz r0, 801502c <_Balloc+0x20> 8015022: 216b movs r1, #107 @ 0x6b 8015024: 4b17 ldr r3, [pc, #92] @ (8015084 <_Balloc+0x78>) 8015026: 4818 ldr r0, [pc, #96] @ (8015088 <_Balloc+0x7c>) 8015028: f7fe fd80 bl 8013b2c <__assert_func> 801502c: e9c0 6601 strd r6, r6, [r0, #4] 8015030: 6006 str r6, [r0, #0] 8015032: 60c6 str r6, [r0, #12] 8015034: 69e6 ldr r6, [r4, #28] 8015036: 68f3 ldr r3, [r6, #12] 8015038: b183 cbz r3, 801505c <_Balloc+0x50> 801503a: 69e3 ldr r3, [r4, #28] 801503c: 68db ldr r3, [r3, #12] 801503e: f853 0025 ldr.w r0, [r3, r5, lsl #2] 8015042: b9b8 cbnz r0, 8015074 <_Balloc+0x68> 8015044: 2101 movs r1, #1 8015046: fa01 f605 lsl.w r6, r1, r5 801504a: 1d72 adds r2, r6, #5 801504c: 4620 mov r0, r4 801504e: 0092 lsls r2, r2, #2 8015050: f000 fd69 bl 8015b26 <_calloc_r> 8015054: b160 cbz r0, 8015070 <_Balloc+0x64> 8015056: e9c0 5601 strd r5, r6, [r0, #4] 801505a: e00e b.n 801507a <_Balloc+0x6e> 801505c: 2221 movs r2, #33 @ 0x21 801505e: 2104 movs r1, #4 8015060: 4620 mov r0, r4 8015062: f000 fd60 bl 8015b26 <_calloc_r> 8015066: 69e3 ldr r3, [r4, #28] 8015068: 60f0 str r0, [r6, #12] 801506a: 68db ldr r3, [r3, #12] 801506c: 2b00 cmp r3, #0 801506e: d1e4 bne.n 801503a <_Balloc+0x2e> 8015070: 2000 movs r0, #0 8015072: bd70 pop {r4, r5, r6, pc} 8015074: 6802 ldr r2, [r0, #0] 8015076: f843 2025 str.w r2, [r3, r5, lsl #2] 801507a: 2300 movs r3, #0 801507c: e9c0 3303 strd r3, r3, [r0, #12] 8015080: e7f7 b.n 8015072 <_Balloc+0x66> 8015082: bf00 nop 8015084: 080161c5 .word 0x080161c5 8015088: 08016256 .word 0x08016256 0801508c <_Bfree>: 801508c: b570 push {r4, r5, r6, lr} 801508e: 69c6 ldr r6, [r0, #28] 8015090: 4605 mov r5, r0 8015092: 460c mov r4, r1 8015094: b976 cbnz r6, 80150b4 <_Bfree+0x28> 8015096: 2010 movs r0, #16 8015098: f7ff fe5a bl 8014d50 801509c: 4602 mov r2, r0 801509e: 61e8 str r0, [r5, #28] 80150a0: b920 cbnz r0, 80150ac <_Bfree+0x20> 80150a2: 218f movs r1, #143 @ 0x8f 80150a4: 4b08 ldr r3, [pc, #32] @ (80150c8 <_Bfree+0x3c>) 80150a6: 4809 ldr r0, [pc, #36] @ (80150cc <_Bfree+0x40>) 80150a8: f7fe fd40 bl 8013b2c <__assert_func> 80150ac: e9c0 6601 strd r6, r6, [r0, #4] 80150b0: 6006 str r6, [r0, #0] 80150b2: 60c6 str r6, [r0, #12] 80150b4: b13c cbz r4, 80150c6 <_Bfree+0x3a> 80150b6: 69eb ldr r3, [r5, #28] 80150b8: 6862 ldr r2, [r4, #4] 80150ba: 68db ldr r3, [r3, #12] 80150bc: f853 1022 ldr.w r1, [r3, r2, lsl #2] 80150c0: 6021 str r1, [r4, #0] 80150c2: f843 4022 str.w r4, [r3, r2, lsl #2] 80150c6: bd70 pop {r4, r5, r6, pc} 80150c8: 080161c5 .word 0x080161c5 80150cc: 08016256 .word 0x08016256 080150d0 <__multadd>: 80150d0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80150d4: 4607 mov r7, r0 80150d6: 460c mov r4, r1 80150d8: 461e mov r6, r3 80150da: 2000 movs r0, #0 80150dc: 690d ldr r5, [r1, #16] 80150de: f101 0c14 add.w ip, r1, #20 80150e2: f8dc 3000 ldr.w r3, [ip] 80150e6: 3001 adds r0, #1 80150e8: b299 uxth r1, r3 80150ea: fb02 6101 mla r1, r2, r1, r6 80150ee: 0c1e lsrs r6, r3, #16 80150f0: 0c0b lsrs r3, r1, #16 80150f2: fb02 3306 mla r3, r2, r6, r3 80150f6: b289 uxth r1, r1 80150f8: eb01 4103 add.w r1, r1, r3, lsl #16 80150fc: 4285 cmp r5, r0 80150fe: ea4f 4613 mov.w r6, r3, lsr #16 8015102: f84c 1b04 str.w r1, [ip], #4 8015106: dcec bgt.n 80150e2 <__multadd+0x12> 8015108: b30e cbz r6, 801514e <__multadd+0x7e> 801510a: 68a3 ldr r3, [r4, #8] 801510c: 42ab cmp r3, r5 801510e: dc19 bgt.n 8015144 <__multadd+0x74> 8015110: 6861 ldr r1, [r4, #4] 8015112: 4638 mov r0, r7 8015114: 3101 adds r1, #1 8015116: f7ff ff79 bl 801500c <_Balloc> 801511a: 4680 mov r8, r0 801511c: b928 cbnz r0, 801512a <__multadd+0x5a> 801511e: 4602 mov r2, r0 8015120: 21ba movs r1, #186 @ 0xba 8015122: 4b0c ldr r3, [pc, #48] @ (8015154 <__multadd+0x84>) 8015124: 480c ldr r0, [pc, #48] @ (8015158 <__multadd+0x88>) 8015126: f7fe fd01 bl 8013b2c <__assert_func> 801512a: 6922 ldr r2, [r4, #16] 801512c: f104 010c add.w r1, r4, #12 8015130: 3202 adds r2, #2 8015132: 0092 lsls r2, r2, #2 8015134: 300c adds r0, #12 8015136: f7fe fceb bl 8013b10 801513a: 4621 mov r1, r4 801513c: 4638 mov r0, r7 801513e: f7ff ffa5 bl 801508c <_Bfree> 8015142: 4644 mov r4, r8 8015144: eb04 0385 add.w r3, r4, r5, lsl #2 8015148: 3501 adds r5, #1 801514a: 615e str r6, [r3, #20] 801514c: 6125 str r5, [r4, #16] 801514e: 4620 mov r0, r4 8015150: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8015154: 08016234 .word 0x08016234 8015158: 08016256 .word 0x08016256 0801515c <__hi0bits>: 801515c: 4603 mov r3, r0 801515e: f5b0 3f80 cmp.w r0, #65536 @ 0x10000 8015162: bf3a itte cc 8015164: 0403 lslcc r3, r0, #16 8015166: 2010 movcc r0, #16 8015168: 2000 movcs r0, #0 801516a: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 801516e: bf3c itt cc 8015170: 021b lslcc r3, r3, #8 8015172: 3008 addcc r0, #8 8015174: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8015178: bf3c itt cc 801517a: 011b lslcc r3, r3, #4 801517c: 3004 addcc r0, #4 801517e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8015182: bf3c itt cc 8015184: 009b lslcc r3, r3, #2 8015186: 3002 addcc r0, #2 8015188: 2b00 cmp r3, #0 801518a: db05 blt.n 8015198 <__hi0bits+0x3c> 801518c: f013 4f80 tst.w r3, #1073741824 @ 0x40000000 8015190: f100 0001 add.w r0, r0, #1 8015194: bf08 it eq 8015196: 2020 moveq r0, #32 8015198: 4770 bx lr 0801519a <__lo0bits>: 801519a: 6803 ldr r3, [r0, #0] 801519c: 4602 mov r2, r0 801519e: f013 0007 ands.w r0, r3, #7 80151a2: d00b beq.n 80151bc <__lo0bits+0x22> 80151a4: 07d9 lsls r1, r3, #31 80151a6: d421 bmi.n 80151ec <__lo0bits+0x52> 80151a8: 0798 lsls r0, r3, #30 80151aa: bf49 itett mi 80151ac: 085b lsrmi r3, r3, #1 80151ae: 089b lsrpl r3, r3, #2 80151b0: 2001 movmi r0, #1 80151b2: 6013 strmi r3, [r2, #0] 80151b4: bf5c itt pl 80151b6: 2002 movpl r0, #2 80151b8: 6013 strpl r3, [r2, #0] 80151ba: 4770 bx lr 80151bc: b299 uxth r1, r3 80151be: b909 cbnz r1, 80151c4 <__lo0bits+0x2a> 80151c0: 2010 movs r0, #16 80151c2: 0c1b lsrs r3, r3, #16 80151c4: b2d9 uxtb r1, r3 80151c6: b909 cbnz r1, 80151cc <__lo0bits+0x32> 80151c8: 3008 adds r0, #8 80151ca: 0a1b lsrs r3, r3, #8 80151cc: 0719 lsls r1, r3, #28 80151ce: bf04 itt eq 80151d0: 091b lsreq r3, r3, #4 80151d2: 3004 addeq r0, #4 80151d4: 0799 lsls r1, r3, #30 80151d6: bf04 itt eq 80151d8: 089b lsreq r3, r3, #2 80151da: 3002 addeq r0, #2 80151dc: 07d9 lsls r1, r3, #31 80151de: d403 bmi.n 80151e8 <__lo0bits+0x4e> 80151e0: 085b lsrs r3, r3, #1 80151e2: f100 0001 add.w r0, r0, #1 80151e6: d003 beq.n 80151f0 <__lo0bits+0x56> 80151e8: 6013 str r3, [r2, #0] 80151ea: 4770 bx lr 80151ec: 2000 movs r0, #0 80151ee: 4770 bx lr 80151f0: 2020 movs r0, #32 80151f2: 4770 bx lr 080151f4 <__i2b>: 80151f4: b510 push {r4, lr} 80151f6: 460c mov r4, r1 80151f8: 2101 movs r1, #1 80151fa: f7ff ff07 bl 801500c <_Balloc> 80151fe: 4602 mov r2, r0 8015200: b928 cbnz r0, 801520e <__i2b+0x1a> 8015202: f240 1145 movw r1, #325 @ 0x145 8015206: 4b04 ldr r3, [pc, #16] @ (8015218 <__i2b+0x24>) 8015208: 4804 ldr r0, [pc, #16] @ (801521c <__i2b+0x28>) 801520a: f7fe fc8f bl 8013b2c <__assert_func> 801520e: 2301 movs r3, #1 8015210: 6144 str r4, [r0, #20] 8015212: 6103 str r3, [r0, #16] 8015214: bd10 pop {r4, pc} 8015216: bf00 nop 8015218: 08016234 .word 0x08016234 801521c: 08016256 .word 0x08016256 08015220 <__multiply>: 8015220: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8015224: 4617 mov r7, r2 8015226: 690a ldr r2, [r1, #16] 8015228: 693b ldr r3, [r7, #16] 801522a: 4689 mov r9, r1 801522c: 429a cmp r2, r3 801522e: bfa2 ittt ge 8015230: 463b movge r3, r7 8015232: 460f movge r7, r1 8015234: 4699 movge r9, r3 8015236: 693d ldr r5, [r7, #16] 8015238: f8d9 a010 ldr.w sl, [r9, #16] 801523c: 68bb ldr r3, [r7, #8] 801523e: 6879 ldr r1, [r7, #4] 8015240: eb05 060a add.w r6, r5, sl 8015244: 42b3 cmp r3, r6 8015246: b085 sub sp, #20 8015248: bfb8 it lt 801524a: 3101 addlt r1, #1 801524c: f7ff fede bl 801500c <_Balloc> 8015250: b930 cbnz r0, 8015260 <__multiply+0x40> 8015252: 4602 mov r2, r0 8015254: f44f 71b1 mov.w r1, #354 @ 0x162 8015258: 4b40 ldr r3, [pc, #256] @ (801535c <__multiply+0x13c>) 801525a: 4841 ldr r0, [pc, #260] @ (8015360 <__multiply+0x140>) 801525c: f7fe fc66 bl 8013b2c <__assert_func> 8015260: f100 0414 add.w r4, r0, #20 8015264: 4623 mov r3, r4 8015266: 2200 movs r2, #0 8015268: eb04 0e86 add.w lr, r4, r6, lsl #2 801526c: 4573 cmp r3, lr 801526e: d320 bcc.n 80152b2 <__multiply+0x92> 8015270: f107 0814 add.w r8, r7, #20 8015274: f109 0114 add.w r1, r9, #20 8015278: eb08 0585 add.w r5, r8, r5, lsl #2 801527c: eb01 038a add.w r3, r1, sl, lsl #2 8015280: 9302 str r3, [sp, #8] 8015282: 1beb subs r3, r5, r7 8015284: 3b15 subs r3, #21 8015286: f023 0303 bic.w r3, r3, #3 801528a: 3304 adds r3, #4 801528c: 3715 adds r7, #21 801528e: 42bd cmp r5, r7 8015290: bf38 it cc 8015292: 2304 movcc r3, #4 8015294: 9301 str r3, [sp, #4] 8015296: 9b02 ldr r3, [sp, #8] 8015298: 9103 str r1, [sp, #12] 801529a: 428b cmp r3, r1 801529c: d80c bhi.n 80152b8 <__multiply+0x98> 801529e: 2e00 cmp r6, #0 80152a0: dd03 ble.n 80152aa <__multiply+0x8a> 80152a2: f85e 3d04 ldr.w r3, [lr, #-4]! 80152a6: 2b00 cmp r3, #0 80152a8: d055 beq.n 8015356 <__multiply+0x136> 80152aa: 6106 str r6, [r0, #16] 80152ac: b005 add sp, #20 80152ae: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80152b2: f843 2b04 str.w r2, [r3], #4 80152b6: e7d9 b.n 801526c <__multiply+0x4c> 80152b8: f8b1 a000 ldrh.w sl, [r1] 80152bc: f1ba 0f00 cmp.w sl, #0 80152c0: d01f beq.n 8015302 <__multiply+0xe2> 80152c2: 46c4 mov ip, r8 80152c4: 46a1 mov r9, r4 80152c6: 2700 movs r7, #0 80152c8: f85c 2b04 ldr.w r2, [ip], #4 80152cc: f8d9 3000 ldr.w r3, [r9] 80152d0: fa1f fb82 uxth.w fp, r2 80152d4: b29b uxth r3, r3 80152d6: fb0a 330b mla r3, sl, fp, r3 80152da: 443b add r3, r7 80152dc: f8d9 7000 ldr.w r7, [r9] 80152e0: 0c12 lsrs r2, r2, #16 80152e2: 0c3f lsrs r7, r7, #16 80152e4: fb0a 7202 mla r2, sl, r2, r7 80152e8: eb02 4213 add.w r2, r2, r3, lsr #16 80152ec: b29b uxth r3, r3 80152ee: ea43 4302 orr.w r3, r3, r2, lsl #16 80152f2: 4565 cmp r5, ip 80152f4: ea4f 4712 mov.w r7, r2, lsr #16 80152f8: f849 3b04 str.w r3, [r9], #4 80152fc: d8e4 bhi.n 80152c8 <__multiply+0xa8> 80152fe: 9b01 ldr r3, [sp, #4] 8015300: 50e7 str r7, [r4, r3] 8015302: 9b03 ldr r3, [sp, #12] 8015304: 3104 adds r1, #4 8015306: f8b3 9002 ldrh.w r9, [r3, #2] 801530a: f1b9 0f00 cmp.w r9, #0 801530e: d020 beq.n 8015352 <__multiply+0x132> 8015310: 4647 mov r7, r8 8015312: 46a4 mov ip, r4 8015314: f04f 0a00 mov.w sl, #0 8015318: 6823 ldr r3, [r4, #0] 801531a: f8b7 b000 ldrh.w fp, [r7] 801531e: f8bc 2002 ldrh.w r2, [ip, #2] 8015322: b29b uxth r3, r3 8015324: fb09 220b mla r2, r9, fp, r2 8015328: 4452 add r2, sl 801532a: ea43 4302 orr.w r3, r3, r2, lsl #16 801532e: f84c 3b04 str.w r3, [ip], #4 8015332: f857 3b04 ldr.w r3, [r7], #4 8015336: ea4f 4a13 mov.w sl, r3, lsr #16 801533a: f8bc 3000 ldrh.w r3, [ip] 801533e: 42bd cmp r5, r7 8015340: fb09 330a mla r3, r9, sl, r3 8015344: eb03 4312 add.w r3, r3, r2, lsr #16 8015348: ea4f 4a13 mov.w sl, r3, lsr #16 801534c: d8e5 bhi.n 801531a <__multiply+0xfa> 801534e: 9a01 ldr r2, [sp, #4] 8015350: 50a3 str r3, [r4, r2] 8015352: 3404 adds r4, #4 8015354: e79f b.n 8015296 <__multiply+0x76> 8015356: 3e01 subs r6, #1 8015358: e7a1 b.n 801529e <__multiply+0x7e> 801535a: bf00 nop 801535c: 08016234 .word 0x08016234 8015360: 08016256 .word 0x08016256 08015364 <__pow5mult>: 8015364: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8015368: 4615 mov r5, r2 801536a: f012 0203 ands.w r2, r2, #3 801536e: 4607 mov r7, r0 8015370: 460e mov r6, r1 8015372: d007 beq.n 8015384 <__pow5mult+0x20> 8015374: 4c25 ldr r4, [pc, #148] @ (801540c <__pow5mult+0xa8>) 8015376: 3a01 subs r2, #1 8015378: 2300 movs r3, #0 801537a: f854 2022 ldr.w r2, [r4, r2, lsl #2] 801537e: f7ff fea7 bl 80150d0 <__multadd> 8015382: 4606 mov r6, r0 8015384: 10ad asrs r5, r5, #2 8015386: d03d beq.n 8015404 <__pow5mult+0xa0> 8015388: 69fc ldr r4, [r7, #28] 801538a: b97c cbnz r4, 80153ac <__pow5mult+0x48> 801538c: 2010 movs r0, #16 801538e: f7ff fcdf bl 8014d50 8015392: 4602 mov r2, r0 8015394: 61f8 str r0, [r7, #28] 8015396: b928 cbnz r0, 80153a4 <__pow5mult+0x40> 8015398: f240 11b3 movw r1, #435 @ 0x1b3 801539c: 4b1c ldr r3, [pc, #112] @ (8015410 <__pow5mult+0xac>) 801539e: 481d ldr r0, [pc, #116] @ (8015414 <__pow5mult+0xb0>) 80153a0: f7fe fbc4 bl 8013b2c <__assert_func> 80153a4: e9c0 4401 strd r4, r4, [r0, #4] 80153a8: 6004 str r4, [r0, #0] 80153aa: 60c4 str r4, [r0, #12] 80153ac: f8d7 801c ldr.w r8, [r7, #28] 80153b0: f8d8 4008 ldr.w r4, [r8, #8] 80153b4: b94c cbnz r4, 80153ca <__pow5mult+0x66> 80153b6: f240 2171 movw r1, #625 @ 0x271 80153ba: 4638 mov r0, r7 80153bc: f7ff ff1a bl 80151f4 <__i2b> 80153c0: 2300 movs r3, #0 80153c2: 4604 mov r4, r0 80153c4: f8c8 0008 str.w r0, [r8, #8] 80153c8: 6003 str r3, [r0, #0] 80153ca: f04f 0900 mov.w r9, #0 80153ce: 07eb lsls r3, r5, #31 80153d0: d50a bpl.n 80153e8 <__pow5mult+0x84> 80153d2: 4631 mov r1, r6 80153d4: 4622 mov r2, r4 80153d6: 4638 mov r0, r7 80153d8: f7ff ff22 bl 8015220 <__multiply> 80153dc: 4680 mov r8, r0 80153de: 4631 mov r1, r6 80153e0: 4638 mov r0, r7 80153e2: f7ff fe53 bl 801508c <_Bfree> 80153e6: 4646 mov r6, r8 80153e8: 106d asrs r5, r5, #1 80153ea: d00b beq.n 8015404 <__pow5mult+0xa0> 80153ec: 6820 ldr r0, [r4, #0] 80153ee: b938 cbnz r0, 8015400 <__pow5mult+0x9c> 80153f0: 4622 mov r2, r4 80153f2: 4621 mov r1, r4 80153f4: 4638 mov r0, r7 80153f6: f7ff ff13 bl 8015220 <__multiply> 80153fa: 6020 str r0, [r4, #0] 80153fc: f8c0 9000 str.w r9, [r0] 8015400: 4604 mov r4, r0 8015402: e7e4 b.n 80153ce <__pow5mult+0x6a> 8015404: 4630 mov r0, r6 8015406: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 801540a: bf00 nop 801540c: 080162bc .word 0x080162bc 8015410: 080161c5 .word 0x080161c5 8015414: 08016256 .word 0x08016256 08015418 <__lshift>: 8015418: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 801541c: 460c mov r4, r1 801541e: 4607 mov r7, r0 8015420: 4691 mov r9, r2 8015422: 6923 ldr r3, [r4, #16] 8015424: 6849 ldr r1, [r1, #4] 8015426: eb03 1862 add.w r8, r3, r2, asr #5 801542a: 68a3 ldr r3, [r4, #8] 801542c: ea4f 1a62 mov.w sl, r2, asr #5 8015430: f108 0601 add.w r6, r8, #1 8015434: 42b3 cmp r3, r6 8015436: db0b blt.n 8015450 <__lshift+0x38> 8015438: 4638 mov r0, r7 801543a: f7ff fde7 bl 801500c <_Balloc> 801543e: 4605 mov r5, r0 8015440: b948 cbnz r0, 8015456 <__lshift+0x3e> 8015442: 4602 mov r2, r0 8015444: f44f 71ef mov.w r1, #478 @ 0x1de 8015448: 4b27 ldr r3, [pc, #156] @ (80154e8 <__lshift+0xd0>) 801544a: 4828 ldr r0, [pc, #160] @ (80154ec <__lshift+0xd4>) 801544c: f7fe fb6e bl 8013b2c <__assert_func> 8015450: 3101 adds r1, #1 8015452: 005b lsls r3, r3, #1 8015454: e7ee b.n 8015434 <__lshift+0x1c> 8015456: 2300 movs r3, #0 8015458: f100 0114 add.w r1, r0, #20 801545c: f100 0210 add.w r2, r0, #16 8015460: 4618 mov r0, r3 8015462: 4553 cmp r3, sl 8015464: db33 blt.n 80154ce <__lshift+0xb6> 8015466: 6920 ldr r0, [r4, #16] 8015468: ea2a 7aea bic.w sl, sl, sl, asr #31 801546c: f104 0314 add.w r3, r4, #20 8015470: f019 091f ands.w r9, r9, #31 8015474: eb01 018a add.w r1, r1, sl, lsl #2 8015478: eb03 0c80 add.w ip, r3, r0, lsl #2 801547c: d02b beq.n 80154d6 <__lshift+0xbe> 801547e: 468a mov sl, r1 8015480: 2200 movs r2, #0 8015482: f1c9 0e20 rsb lr, r9, #32 8015486: 6818 ldr r0, [r3, #0] 8015488: fa00 f009 lsl.w r0, r0, r9 801548c: 4310 orrs r0, r2 801548e: f84a 0b04 str.w r0, [sl], #4 8015492: f853 2b04 ldr.w r2, [r3], #4 8015496: 459c cmp ip, r3 8015498: fa22 f20e lsr.w r2, r2, lr 801549c: d8f3 bhi.n 8015486 <__lshift+0x6e> 801549e: ebac 0304 sub.w r3, ip, r4 80154a2: 3b15 subs r3, #21 80154a4: f023 0303 bic.w r3, r3, #3 80154a8: 3304 adds r3, #4 80154aa: f104 0015 add.w r0, r4, #21 80154ae: 4560 cmp r0, ip 80154b0: bf88 it hi 80154b2: 2304 movhi r3, #4 80154b4: 50ca str r2, [r1, r3] 80154b6: b10a cbz r2, 80154bc <__lshift+0xa4> 80154b8: f108 0602 add.w r6, r8, #2 80154bc: 3e01 subs r6, #1 80154be: 4638 mov r0, r7 80154c0: 4621 mov r1, r4 80154c2: 612e str r6, [r5, #16] 80154c4: f7ff fde2 bl 801508c <_Bfree> 80154c8: 4628 mov r0, r5 80154ca: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80154ce: f842 0f04 str.w r0, [r2, #4]! 80154d2: 3301 adds r3, #1 80154d4: e7c5 b.n 8015462 <__lshift+0x4a> 80154d6: 3904 subs r1, #4 80154d8: f853 2b04 ldr.w r2, [r3], #4 80154dc: 459c cmp ip, r3 80154de: f841 2f04 str.w r2, [r1, #4]! 80154e2: d8f9 bhi.n 80154d8 <__lshift+0xc0> 80154e4: e7ea b.n 80154bc <__lshift+0xa4> 80154e6: bf00 nop 80154e8: 08016234 .word 0x08016234 80154ec: 08016256 .word 0x08016256 080154f0 <__mcmp>: 80154f0: 4603 mov r3, r0 80154f2: 690a ldr r2, [r1, #16] 80154f4: 6900 ldr r0, [r0, #16] 80154f6: b530 push {r4, r5, lr} 80154f8: 1a80 subs r0, r0, r2 80154fa: d10e bne.n 801551a <__mcmp+0x2a> 80154fc: 3314 adds r3, #20 80154fe: 3114 adds r1, #20 8015500: eb03 0482 add.w r4, r3, r2, lsl #2 8015504: eb01 0182 add.w r1, r1, r2, lsl #2 8015508: f854 5d04 ldr.w r5, [r4, #-4]! 801550c: f851 2d04 ldr.w r2, [r1, #-4]! 8015510: 4295 cmp r5, r2 8015512: d003 beq.n 801551c <__mcmp+0x2c> 8015514: d205 bcs.n 8015522 <__mcmp+0x32> 8015516: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801551a: bd30 pop {r4, r5, pc} 801551c: 42a3 cmp r3, r4 801551e: d3f3 bcc.n 8015508 <__mcmp+0x18> 8015520: e7fb b.n 801551a <__mcmp+0x2a> 8015522: 2001 movs r0, #1 8015524: e7f9 b.n 801551a <__mcmp+0x2a> ... 08015528 <__mdiff>: 8015528: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 801552c: 4689 mov r9, r1 801552e: 4606 mov r6, r0 8015530: 4611 mov r1, r2 8015532: 4648 mov r0, r9 8015534: 4614 mov r4, r2 8015536: f7ff ffdb bl 80154f0 <__mcmp> 801553a: 1e05 subs r5, r0, #0 801553c: d112 bne.n 8015564 <__mdiff+0x3c> 801553e: 4629 mov r1, r5 8015540: 4630 mov r0, r6 8015542: f7ff fd63 bl 801500c <_Balloc> 8015546: 4602 mov r2, r0 8015548: b928 cbnz r0, 8015556 <__mdiff+0x2e> 801554a: f240 2137 movw r1, #567 @ 0x237 801554e: 4b3e ldr r3, [pc, #248] @ (8015648 <__mdiff+0x120>) 8015550: 483e ldr r0, [pc, #248] @ (801564c <__mdiff+0x124>) 8015552: f7fe faeb bl 8013b2c <__assert_func> 8015556: 2301 movs r3, #1 8015558: e9c0 3504 strd r3, r5, [r0, #16] 801555c: 4610 mov r0, r2 801555e: b003 add sp, #12 8015560: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8015564: bfbc itt lt 8015566: 464b movlt r3, r9 8015568: 46a1 movlt r9, r4 801556a: 4630 mov r0, r6 801556c: f8d9 1004 ldr.w r1, [r9, #4] 8015570: bfba itte lt 8015572: 461c movlt r4, r3 8015574: 2501 movlt r5, #1 8015576: 2500 movge r5, #0 8015578: f7ff fd48 bl 801500c <_Balloc> 801557c: 4602 mov r2, r0 801557e: b918 cbnz r0, 8015588 <__mdiff+0x60> 8015580: f240 2145 movw r1, #581 @ 0x245 8015584: 4b30 ldr r3, [pc, #192] @ (8015648 <__mdiff+0x120>) 8015586: e7e3 b.n 8015550 <__mdiff+0x28> 8015588: f100 0b14 add.w fp, r0, #20 801558c: f8d9 7010 ldr.w r7, [r9, #16] 8015590: f109 0310 add.w r3, r9, #16 8015594: 60c5 str r5, [r0, #12] 8015596: f04f 0c00 mov.w ip, #0 801559a: f109 0514 add.w r5, r9, #20 801559e: 46d9 mov r9, fp 80155a0: 6926 ldr r6, [r4, #16] 80155a2: f104 0e14 add.w lr, r4, #20 80155a6: eb05 0887 add.w r8, r5, r7, lsl #2 80155aa: eb0e 0686 add.w r6, lr, r6, lsl #2 80155ae: 9301 str r3, [sp, #4] 80155b0: 9b01 ldr r3, [sp, #4] 80155b2: f85e 0b04 ldr.w r0, [lr], #4 80155b6: f853 af04 ldr.w sl, [r3, #4]! 80155ba: b281 uxth r1, r0 80155bc: 9301 str r3, [sp, #4] 80155be: fa1f f38a uxth.w r3, sl 80155c2: 1a5b subs r3, r3, r1 80155c4: 0c00 lsrs r0, r0, #16 80155c6: 4463 add r3, ip 80155c8: ebc0 401a rsb r0, r0, sl, lsr #16 80155cc: eb00 4023 add.w r0, r0, r3, asr #16 80155d0: b29b uxth r3, r3 80155d2: ea43 4300 orr.w r3, r3, r0, lsl #16 80155d6: 4576 cmp r6, lr 80155d8: ea4f 4c20 mov.w ip, r0, asr #16 80155dc: f849 3b04 str.w r3, [r9], #4 80155e0: d8e6 bhi.n 80155b0 <__mdiff+0x88> 80155e2: 1b33 subs r3, r6, r4 80155e4: 3b15 subs r3, #21 80155e6: f023 0303 bic.w r3, r3, #3 80155ea: 3415 adds r4, #21 80155ec: 3304 adds r3, #4 80155ee: 42a6 cmp r6, r4 80155f0: bf38 it cc 80155f2: 2304 movcc r3, #4 80155f4: 441d add r5, r3 80155f6: 445b add r3, fp 80155f8: 461e mov r6, r3 80155fa: 462c mov r4, r5 80155fc: 4544 cmp r4, r8 80155fe: d30e bcc.n 801561e <__mdiff+0xf6> 8015600: f108 0103 add.w r1, r8, #3 8015604: 1b49 subs r1, r1, r5 8015606: f021 0103 bic.w r1, r1, #3 801560a: 3d03 subs r5, #3 801560c: 45a8 cmp r8, r5 801560e: bf38 it cc 8015610: 2100 movcc r1, #0 8015612: 440b add r3, r1 8015614: f853 1d04 ldr.w r1, [r3, #-4]! 8015618: b199 cbz r1, 8015642 <__mdiff+0x11a> 801561a: 6117 str r7, [r2, #16] 801561c: e79e b.n 801555c <__mdiff+0x34> 801561e: 46e6 mov lr, ip 8015620: f854 1b04 ldr.w r1, [r4], #4 8015624: fa1f fc81 uxth.w ip, r1 8015628: 44f4 add ip, lr 801562a: 0c08 lsrs r0, r1, #16 801562c: 4471 add r1, lr 801562e: eb00 402c add.w r0, r0, ip, asr #16 8015632: b289 uxth r1, r1 8015634: ea41 4100 orr.w r1, r1, r0, lsl #16 8015638: ea4f 4c20 mov.w ip, r0, asr #16 801563c: f846 1b04 str.w r1, [r6], #4 8015640: e7dc b.n 80155fc <__mdiff+0xd4> 8015642: 3f01 subs r7, #1 8015644: e7e6 b.n 8015614 <__mdiff+0xec> 8015646: bf00 nop 8015648: 08016234 .word 0x08016234 801564c: 08016256 .word 0x08016256 08015650 <__d2b>: 8015650: e92d 4373 stmdb sp!, {r0, r1, r4, r5, r6, r8, r9, lr} 8015654: 2101 movs r1, #1 8015656: 4690 mov r8, r2 8015658: 4699 mov r9, r3 801565a: 9e08 ldr r6, [sp, #32] 801565c: f7ff fcd6 bl 801500c <_Balloc> 8015660: 4604 mov r4, r0 8015662: b930 cbnz r0, 8015672 <__d2b+0x22> 8015664: 4602 mov r2, r0 8015666: f240 310f movw r1, #783 @ 0x30f 801566a: 4b23 ldr r3, [pc, #140] @ (80156f8 <__d2b+0xa8>) 801566c: 4823 ldr r0, [pc, #140] @ (80156fc <__d2b+0xac>) 801566e: f7fe fa5d bl 8013b2c <__assert_func> 8015672: f3c9 550a ubfx r5, r9, #20, #11 8015676: f3c9 0313 ubfx r3, r9, #0, #20 801567a: b10d cbz r5, 8015680 <__d2b+0x30> 801567c: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8015680: 9301 str r3, [sp, #4] 8015682: f1b8 0300 subs.w r3, r8, #0 8015686: d024 beq.n 80156d2 <__d2b+0x82> 8015688: 4668 mov r0, sp 801568a: 9300 str r3, [sp, #0] 801568c: f7ff fd85 bl 801519a <__lo0bits> 8015690: e9dd 1200 ldrd r1, r2, [sp] 8015694: b1d8 cbz r0, 80156ce <__d2b+0x7e> 8015696: f1c0 0320 rsb r3, r0, #32 801569a: fa02 f303 lsl.w r3, r2, r3 801569e: 430b orrs r3, r1 80156a0: 40c2 lsrs r2, r0 80156a2: 6163 str r3, [r4, #20] 80156a4: 9201 str r2, [sp, #4] 80156a6: 9b01 ldr r3, [sp, #4] 80156a8: 2b00 cmp r3, #0 80156aa: bf0c ite eq 80156ac: 2201 moveq r2, #1 80156ae: 2202 movne r2, #2 80156b0: 61a3 str r3, [r4, #24] 80156b2: 6122 str r2, [r4, #16] 80156b4: b1ad cbz r5, 80156e2 <__d2b+0x92> 80156b6: f2a5 4533 subw r5, r5, #1075 @ 0x433 80156ba: 4405 add r5, r0 80156bc: 6035 str r5, [r6, #0] 80156be: f1c0 0035 rsb r0, r0, #53 @ 0x35 80156c2: 9b09 ldr r3, [sp, #36] @ 0x24 80156c4: 6018 str r0, [r3, #0] 80156c6: 4620 mov r0, r4 80156c8: b002 add sp, #8 80156ca: e8bd 8370 ldmia.w sp!, {r4, r5, r6, r8, r9, pc} 80156ce: 6161 str r1, [r4, #20] 80156d0: e7e9 b.n 80156a6 <__d2b+0x56> 80156d2: a801 add r0, sp, #4 80156d4: f7ff fd61 bl 801519a <__lo0bits> 80156d8: 9b01 ldr r3, [sp, #4] 80156da: 2201 movs r2, #1 80156dc: 6163 str r3, [r4, #20] 80156de: 3020 adds r0, #32 80156e0: e7e7 b.n 80156b2 <__d2b+0x62> 80156e2: f2a0 4032 subw r0, r0, #1074 @ 0x432 80156e6: eb04 0382 add.w r3, r4, r2, lsl #2 80156ea: 6030 str r0, [r6, #0] 80156ec: 6918 ldr r0, [r3, #16] 80156ee: f7ff fd35 bl 801515c <__hi0bits> 80156f2: ebc0 1042 rsb r0, r0, r2, lsl #5 80156f6: e7e4 b.n 80156c2 <__d2b+0x72> 80156f8: 08016234 .word 0x08016234 80156fc: 08016256 .word 0x08016256 08015700 <__sread>: 8015700: b510 push {r4, lr} 8015702: 460c mov r4, r1 8015704: f9b1 100e ldrsh.w r1, [r1, #14] 8015708: f000 f9b0 bl 8015a6c <_read_r> 801570c: 2800 cmp r0, #0 801570e: bfab itete ge 8015710: 6d63 ldrge r3, [r4, #84] @ 0x54 8015712: 89a3 ldrhlt r3, [r4, #12] 8015714: 181b addge r3, r3, r0 8015716: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 801571a: bfac ite ge 801571c: 6563 strge r3, [r4, #84] @ 0x54 801571e: 81a3 strhlt r3, [r4, #12] 8015720: bd10 pop {r4, pc} 08015722 <__swrite>: 8015722: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8015726: 461f mov r7, r3 8015728: 898b ldrh r3, [r1, #12] 801572a: 4605 mov r5, r0 801572c: 05db lsls r3, r3, #23 801572e: 460c mov r4, r1 8015730: 4616 mov r6, r2 8015732: d505 bpl.n 8015740 <__swrite+0x1e> 8015734: 2302 movs r3, #2 8015736: 2200 movs r2, #0 8015738: f9b1 100e ldrsh.w r1, [r1, #14] 801573c: f000 f984 bl 8015a48 <_lseek_r> 8015740: 89a3 ldrh r3, [r4, #12] 8015742: 4632 mov r2, r6 8015744: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8015748: 81a3 strh r3, [r4, #12] 801574a: 4628 mov r0, r5 801574c: 463b mov r3, r7 801574e: f9b4 100e ldrsh.w r1, [r4, #14] 8015752: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8015756: f000 b9ab b.w 8015ab0 <_write_r> 0801575a <__sseek>: 801575a: b510 push {r4, lr} 801575c: 460c mov r4, r1 801575e: f9b1 100e ldrsh.w r1, [r1, #14] 8015762: f000 f971 bl 8015a48 <_lseek_r> 8015766: 1c43 adds r3, r0, #1 8015768: 89a3 ldrh r3, [r4, #12] 801576a: bf15 itete ne 801576c: 6560 strne r0, [r4, #84] @ 0x54 801576e: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 8015772: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 8015776: 81a3 strheq r3, [r4, #12] 8015778: bf18 it ne 801577a: 81a3 strhne r3, [r4, #12] 801577c: bd10 pop {r4, pc} 0801577e <__sclose>: 801577e: f9b1 100e ldrsh.w r1, [r1, #14] 8015782: f000 b9a7 b.w 8015ad4 <_close_r> ... 08015788 : 8015788: b40e push {r1, r2, r3} 801578a: b503 push {r0, r1, lr} 801578c: 4601 mov r1, r0 801578e: ab03 add r3, sp, #12 8015790: 4805 ldr r0, [pc, #20] @ (80157a8 ) 8015792: f853 2b04 ldr.w r2, [r3], #4 8015796: 6800 ldr r0, [r0, #0] 8015798: 9301 str r3, [sp, #4] 801579a: f7ff f9c1 bl 8014b20 <_vfiprintf_r> 801579e: b002 add sp, #8 80157a0: f85d eb04 ldr.w lr, [sp], #4 80157a4: b003 add sp, #12 80157a6: 4770 bx lr 80157a8: 20000084 .word 0x20000084 080157ac <_realloc_r>: 80157ac: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80157b0: 4607 mov r7, r0 80157b2: 4614 mov r4, r2 80157b4: 460d mov r5, r1 80157b6: b921 cbnz r1, 80157c2 <_realloc_r+0x16> 80157b8: 4611 mov r1, r2 80157ba: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 80157be: f7ff baf1 b.w 8014da4 <_malloc_r> 80157c2: b92a cbnz r2, 80157d0 <_realloc_r+0x24> 80157c4: f000 f9c4 bl 8015b50 <_free_r> 80157c8: 4625 mov r5, r4 80157ca: 4628 mov r0, r5 80157cc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80157d0: f000 fa18 bl 8015c04 <_malloc_usable_size_r> 80157d4: 4284 cmp r4, r0 80157d6: 4606 mov r6, r0 80157d8: d802 bhi.n 80157e0 <_realloc_r+0x34> 80157da: ebb4 0f50 cmp.w r4, r0, lsr #1 80157de: d8f4 bhi.n 80157ca <_realloc_r+0x1e> 80157e0: 4621 mov r1, r4 80157e2: 4638 mov r0, r7 80157e4: f7ff fade bl 8014da4 <_malloc_r> 80157e8: 4680 mov r8, r0 80157ea: b908 cbnz r0, 80157f0 <_realloc_r+0x44> 80157ec: 4645 mov r5, r8 80157ee: e7ec b.n 80157ca <_realloc_r+0x1e> 80157f0: 42b4 cmp r4, r6 80157f2: 4622 mov r2, r4 80157f4: 4629 mov r1, r5 80157f6: bf28 it cs 80157f8: 4632 movcs r2, r6 80157fa: f7fe f989 bl 8013b10 80157fe: 4629 mov r1, r5 8015800: 4638 mov r0, r7 8015802: f000 f9a5 bl 8015b50 <_free_r> 8015806: e7f1 b.n 80157ec <_realloc_r+0x40> 08015808 <__swbuf_r>: 8015808: b5f8 push {r3, r4, r5, r6, r7, lr} 801580a: 460e mov r6, r1 801580c: 4614 mov r4, r2 801580e: 4605 mov r5, r0 8015810: b118 cbz r0, 801581a <__swbuf_r+0x12> 8015812: 6a03 ldr r3, [r0, #32] 8015814: b90b cbnz r3, 801581a <__swbuf_r+0x12> 8015816: f7fe f8af bl 8013978 <__sinit> 801581a: 69a3 ldr r3, [r4, #24] 801581c: 60a3 str r3, [r4, #8] 801581e: 89a3 ldrh r3, [r4, #12] 8015820: 071a lsls r2, r3, #28 8015822: d501 bpl.n 8015828 <__swbuf_r+0x20> 8015824: 6923 ldr r3, [r4, #16] 8015826: b943 cbnz r3, 801583a <__swbuf_r+0x32> 8015828: 4621 mov r1, r4 801582a: 4628 mov r0, r5 801582c: f000 f82a bl 8015884 <__swsetup_r> 8015830: b118 cbz r0, 801583a <__swbuf_r+0x32> 8015832: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff 8015836: 4638 mov r0, r7 8015838: bdf8 pop {r3, r4, r5, r6, r7, pc} 801583a: 6823 ldr r3, [r4, #0] 801583c: 6922 ldr r2, [r4, #16] 801583e: b2f6 uxtb r6, r6 8015840: 1a98 subs r0, r3, r2 8015842: 6963 ldr r3, [r4, #20] 8015844: 4637 mov r7, r6 8015846: 4283 cmp r3, r0 8015848: dc05 bgt.n 8015856 <__swbuf_r+0x4e> 801584a: 4621 mov r1, r4 801584c: 4628 mov r0, r5 801584e: f7ff fba9 bl 8014fa4 <_fflush_r> 8015852: 2800 cmp r0, #0 8015854: d1ed bne.n 8015832 <__swbuf_r+0x2a> 8015856: 68a3 ldr r3, [r4, #8] 8015858: 3b01 subs r3, #1 801585a: 60a3 str r3, [r4, #8] 801585c: 6823 ldr r3, [r4, #0] 801585e: 1c5a adds r2, r3, #1 8015860: 6022 str r2, [r4, #0] 8015862: 701e strb r6, [r3, #0] 8015864: 6962 ldr r2, [r4, #20] 8015866: 1c43 adds r3, r0, #1 8015868: 429a cmp r2, r3 801586a: d004 beq.n 8015876 <__swbuf_r+0x6e> 801586c: 89a3 ldrh r3, [r4, #12] 801586e: 07db lsls r3, r3, #31 8015870: d5e1 bpl.n 8015836 <__swbuf_r+0x2e> 8015872: 2e0a cmp r6, #10 8015874: d1df bne.n 8015836 <__swbuf_r+0x2e> 8015876: 4621 mov r1, r4 8015878: 4628 mov r0, r5 801587a: f7ff fb93 bl 8014fa4 <_fflush_r> 801587e: 2800 cmp r0, #0 8015880: d0d9 beq.n 8015836 <__swbuf_r+0x2e> 8015882: e7d6 b.n 8015832 <__swbuf_r+0x2a> 08015884 <__swsetup_r>: 8015884: b538 push {r3, r4, r5, lr} 8015886: 4b29 ldr r3, [pc, #164] @ (801592c <__swsetup_r+0xa8>) 8015888: 4605 mov r5, r0 801588a: 6818 ldr r0, [r3, #0] 801588c: 460c mov r4, r1 801588e: b118 cbz r0, 8015898 <__swsetup_r+0x14> 8015890: 6a03 ldr r3, [r0, #32] 8015892: b90b cbnz r3, 8015898 <__swsetup_r+0x14> 8015894: f7fe f870 bl 8013978 <__sinit> 8015898: f9b4 300c ldrsh.w r3, [r4, #12] 801589c: 0719 lsls r1, r3, #28 801589e: d422 bmi.n 80158e6 <__swsetup_r+0x62> 80158a0: 06da lsls r2, r3, #27 80158a2: d407 bmi.n 80158b4 <__swsetup_r+0x30> 80158a4: 2209 movs r2, #9 80158a6: 602a str r2, [r5, #0] 80158a8: f043 0340 orr.w r3, r3, #64 @ 0x40 80158ac: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80158b0: 81a3 strh r3, [r4, #12] 80158b2: e033 b.n 801591c <__swsetup_r+0x98> 80158b4: 0758 lsls r0, r3, #29 80158b6: d512 bpl.n 80158de <__swsetup_r+0x5a> 80158b8: 6b61 ldr r1, [r4, #52] @ 0x34 80158ba: b141 cbz r1, 80158ce <__swsetup_r+0x4a> 80158bc: f104 0344 add.w r3, r4, #68 @ 0x44 80158c0: 4299 cmp r1, r3 80158c2: d002 beq.n 80158ca <__swsetup_r+0x46> 80158c4: 4628 mov r0, r5 80158c6: f000 f943 bl 8015b50 <_free_r> 80158ca: 2300 movs r3, #0 80158cc: 6363 str r3, [r4, #52] @ 0x34 80158ce: 89a3 ldrh r3, [r4, #12] 80158d0: f023 0324 bic.w r3, r3, #36 @ 0x24 80158d4: 81a3 strh r3, [r4, #12] 80158d6: 2300 movs r3, #0 80158d8: 6063 str r3, [r4, #4] 80158da: 6923 ldr r3, [r4, #16] 80158dc: 6023 str r3, [r4, #0] 80158de: 89a3 ldrh r3, [r4, #12] 80158e0: f043 0308 orr.w r3, r3, #8 80158e4: 81a3 strh r3, [r4, #12] 80158e6: 6923 ldr r3, [r4, #16] 80158e8: b94b cbnz r3, 80158fe <__swsetup_r+0x7a> 80158ea: 89a3 ldrh r3, [r4, #12] 80158ec: f403 7320 and.w r3, r3, #640 @ 0x280 80158f0: f5b3 7f00 cmp.w r3, #512 @ 0x200 80158f4: d003 beq.n 80158fe <__swsetup_r+0x7a> 80158f6: 4621 mov r1, r4 80158f8: 4628 mov r0, r5 80158fa: f000 f83e bl 801597a <__smakebuf_r> 80158fe: f9b4 300c ldrsh.w r3, [r4, #12] 8015902: f013 0201 ands.w r2, r3, #1 8015906: d00a beq.n 801591e <__swsetup_r+0x9a> 8015908: 2200 movs r2, #0 801590a: 60a2 str r2, [r4, #8] 801590c: 6962 ldr r2, [r4, #20] 801590e: 4252 negs r2, r2 8015910: 61a2 str r2, [r4, #24] 8015912: 6922 ldr r2, [r4, #16] 8015914: b942 cbnz r2, 8015928 <__swsetup_r+0xa4> 8015916: f013 0080 ands.w r0, r3, #128 @ 0x80 801591a: d1c5 bne.n 80158a8 <__swsetup_r+0x24> 801591c: bd38 pop {r3, r4, r5, pc} 801591e: 0799 lsls r1, r3, #30 8015920: bf58 it pl 8015922: 6962 ldrpl r2, [r4, #20] 8015924: 60a2 str r2, [r4, #8] 8015926: e7f4 b.n 8015912 <__swsetup_r+0x8e> 8015928: 2000 movs r0, #0 801592a: e7f7 b.n 801591c <__swsetup_r+0x98> 801592c: 20000084 .word 0x20000084 08015930 <__swhatbuf_r>: 8015930: b570 push {r4, r5, r6, lr} 8015932: 460c mov r4, r1 8015934: f9b1 100e ldrsh.w r1, [r1, #14] 8015938: 4615 mov r5, r2 801593a: 2900 cmp r1, #0 801593c: 461e mov r6, r3 801593e: b096 sub sp, #88 @ 0x58 8015940: da0c bge.n 801595c <__swhatbuf_r+0x2c> 8015942: 89a3 ldrh r3, [r4, #12] 8015944: 2100 movs r1, #0 8015946: f013 0f80 tst.w r3, #128 @ 0x80 801594a: bf14 ite ne 801594c: 2340 movne r3, #64 @ 0x40 801594e: f44f 6380 moveq.w r3, #1024 @ 0x400 8015952: 2000 movs r0, #0 8015954: 6031 str r1, [r6, #0] 8015956: 602b str r3, [r5, #0] 8015958: b016 add sp, #88 @ 0x58 801595a: bd70 pop {r4, r5, r6, pc} 801595c: 466a mov r2, sp 801595e: f000 f8c9 bl 8015af4 <_fstat_r> 8015962: 2800 cmp r0, #0 8015964: dbed blt.n 8015942 <__swhatbuf_r+0x12> 8015966: 9901 ldr r1, [sp, #4] 8015968: f401 4170 and.w r1, r1, #61440 @ 0xf000 801596c: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 8015970: 4259 negs r1, r3 8015972: 4159 adcs r1, r3 8015974: f44f 6380 mov.w r3, #1024 @ 0x400 8015978: e7eb b.n 8015952 <__swhatbuf_r+0x22> 0801597a <__smakebuf_r>: 801597a: 898b ldrh r3, [r1, #12] 801597c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 801597e: 079d lsls r5, r3, #30 8015980: 4606 mov r6, r0 8015982: 460c mov r4, r1 8015984: d507 bpl.n 8015996 <__smakebuf_r+0x1c> 8015986: f104 0347 add.w r3, r4, #71 @ 0x47 801598a: 6023 str r3, [r4, #0] 801598c: 6123 str r3, [r4, #16] 801598e: 2301 movs r3, #1 8015990: 6163 str r3, [r4, #20] 8015992: b003 add sp, #12 8015994: bdf0 pop {r4, r5, r6, r7, pc} 8015996: 466a mov r2, sp 8015998: ab01 add r3, sp, #4 801599a: f7ff ffc9 bl 8015930 <__swhatbuf_r> 801599e: 9f00 ldr r7, [sp, #0] 80159a0: 4605 mov r5, r0 80159a2: 4639 mov r1, r7 80159a4: 4630 mov r0, r6 80159a6: f7ff f9fd bl 8014da4 <_malloc_r> 80159aa: b948 cbnz r0, 80159c0 <__smakebuf_r+0x46> 80159ac: f9b4 300c ldrsh.w r3, [r4, #12] 80159b0: 059a lsls r2, r3, #22 80159b2: d4ee bmi.n 8015992 <__smakebuf_r+0x18> 80159b4: f023 0303 bic.w r3, r3, #3 80159b8: f043 0302 orr.w r3, r3, #2 80159bc: 81a3 strh r3, [r4, #12] 80159be: e7e2 b.n 8015986 <__smakebuf_r+0xc> 80159c0: 89a3 ldrh r3, [r4, #12] 80159c2: e9c4 0704 strd r0, r7, [r4, #16] 80159c6: f043 0380 orr.w r3, r3, #128 @ 0x80 80159ca: 81a3 strh r3, [r4, #12] 80159cc: 9b01 ldr r3, [sp, #4] 80159ce: 6020 str r0, [r4, #0] 80159d0: b15b cbz r3, 80159ea <__smakebuf_r+0x70> 80159d2: 4630 mov r0, r6 80159d4: f9b4 100e ldrsh.w r1, [r4, #14] 80159d8: f000 f826 bl 8015a28 <_isatty_r> 80159dc: b128 cbz r0, 80159ea <__smakebuf_r+0x70> 80159de: 89a3 ldrh r3, [r4, #12] 80159e0: f023 0303 bic.w r3, r3, #3 80159e4: f043 0301 orr.w r3, r3, #1 80159e8: 81a3 strh r3, [r4, #12] 80159ea: 89a3 ldrh r3, [r4, #12] 80159ec: 431d orrs r5, r3 80159ee: 81a5 strh r5, [r4, #12] 80159f0: e7cf b.n 8015992 <__smakebuf_r+0x18> 080159f2 : 80159f2: 4288 cmp r0, r1 80159f4: b510 push {r4, lr} 80159f6: eb01 0402 add.w r4, r1, r2 80159fa: d902 bls.n 8015a02 80159fc: 4284 cmp r4, r0 80159fe: 4623 mov r3, r4 8015a00: d807 bhi.n 8015a12 8015a02: 1e43 subs r3, r0, #1 8015a04: 42a1 cmp r1, r4 8015a06: d008 beq.n 8015a1a 8015a08: f811 2b01 ldrb.w r2, [r1], #1 8015a0c: f803 2f01 strb.w r2, [r3, #1]! 8015a10: e7f8 b.n 8015a04 8015a12: 4601 mov r1, r0 8015a14: 4402 add r2, r0 8015a16: 428a cmp r2, r1 8015a18: d100 bne.n 8015a1c 8015a1a: bd10 pop {r4, pc} 8015a1c: f813 4d01 ldrb.w r4, [r3, #-1]! 8015a20: f802 4d01 strb.w r4, [r2, #-1]! 8015a24: e7f7 b.n 8015a16 ... 08015a28 <_isatty_r>: 8015a28: b538 push {r3, r4, r5, lr} 8015a2a: 2300 movs r3, #0 8015a2c: 4d05 ldr r5, [pc, #20] @ (8015a44 <_isatty_r+0x1c>) 8015a2e: 4604 mov r4, r0 8015a30: 4608 mov r0, r1 8015a32: 602b str r3, [r5, #0] 8015a34: f7f7 fc37 bl 800d2a6 <_isatty> 8015a38: 1c43 adds r3, r0, #1 8015a3a: d102 bne.n 8015a42 <_isatty_r+0x1a> 8015a3c: 682b ldr r3, [r5, #0] 8015a3e: b103 cbz r3, 8015a42 <_isatty_r+0x1a> 8015a40: 6023 str r3, [r4, #0] 8015a42: bd38 pop {r3, r4, r5, pc} 8015a44: 20001328 .word 0x20001328 08015a48 <_lseek_r>: 8015a48: b538 push {r3, r4, r5, lr} 8015a4a: 4604 mov r4, r0 8015a4c: 4608 mov r0, r1 8015a4e: 4611 mov r1, r2 8015a50: 2200 movs r2, #0 8015a52: 4d05 ldr r5, [pc, #20] @ (8015a68 <_lseek_r+0x20>) 8015a54: 602a str r2, [r5, #0] 8015a56: 461a mov r2, r3 8015a58: f7f7 fc2f bl 800d2ba <_lseek> 8015a5c: 1c43 adds r3, r0, #1 8015a5e: d102 bne.n 8015a66 <_lseek_r+0x1e> 8015a60: 682b ldr r3, [r5, #0] 8015a62: b103 cbz r3, 8015a66 <_lseek_r+0x1e> 8015a64: 6023 str r3, [r4, #0] 8015a66: bd38 pop {r3, r4, r5, pc} 8015a68: 20001328 .word 0x20001328 08015a6c <_read_r>: 8015a6c: b538 push {r3, r4, r5, lr} 8015a6e: 4604 mov r4, r0 8015a70: 4608 mov r0, r1 8015a72: 4611 mov r1, r2 8015a74: 2200 movs r2, #0 8015a76: 4d05 ldr r5, [pc, #20] @ (8015a8c <_read_r+0x20>) 8015a78: 602a str r2, [r5, #0] 8015a7a: 461a mov r2, r3 8015a7c: f7f7 fbdc bl 800d238 <_read> 8015a80: 1c43 adds r3, r0, #1 8015a82: d102 bne.n 8015a8a <_read_r+0x1e> 8015a84: 682b ldr r3, [r5, #0] 8015a86: b103 cbz r3, 8015a8a <_read_r+0x1e> 8015a88: 6023 str r3, [r4, #0] 8015a8a: bd38 pop {r3, r4, r5, pc} 8015a8c: 20001328 .word 0x20001328 08015a90 <_sbrk_r>: 8015a90: b538 push {r3, r4, r5, lr} 8015a92: 2300 movs r3, #0 8015a94: 4d05 ldr r5, [pc, #20] @ (8015aac <_sbrk_r+0x1c>) 8015a96: 4604 mov r4, r0 8015a98: 4608 mov r0, r1 8015a9a: 602b str r3, [r5, #0] 8015a9c: f7f7 fc1a bl 800d2d4 <_sbrk> 8015aa0: 1c43 adds r3, r0, #1 8015aa2: d102 bne.n 8015aaa <_sbrk_r+0x1a> 8015aa4: 682b ldr r3, [r5, #0] 8015aa6: b103 cbz r3, 8015aaa <_sbrk_r+0x1a> 8015aa8: 6023 str r3, [r4, #0] 8015aaa: bd38 pop {r3, r4, r5, pc} 8015aac: 20001328 .word 0x20001328 08015ab0 <_write_r>: 8015ab0: b538 push {r3, r4, r5, lr} 8015ab2: 4604 mov r4, r0 8015ab4: 4608 mov r0, r1 8015ab6: 4611 mov r1, r2 8015ab8: 2200 movs r2, #0 8015aba: 4d05 ldr r5, [pc, #20] @ (8015ad0 <_write_r+0x20>) 8015abc: 602a str r2, [r5, #0] 8015abe: 461a mov r2, r3 8015ac0: f7f4 fcc6 bl 800a450 <_write> 8015ac4: 1c43 adds r3, r0, #1 8015ac6: d102 bne.n 8015ace <_write_r+0x1e> 8015ac8: 682b ldr r3, [r5, #0] 8015aca: b103 cbz r3, 8015ace <_write_r+0x1e> 8015acc: 6023 str r3, [r4, #0] 8015ace: bd38 pop {r3, r4, r5, pc} 8015ad0: 20001328 .word 0x20001328 08015ad4 <_close_r>: 8015ad4: b538 push {r3, r4, r5, lr} 8015ad6: 2300 movs r3, #0 8015ad8: 4d05 ldr r5, [pc, #20] @ (8015af0 <_close_r+0x1c>) 8015ada: 4604 mov r4, r0 8015adc: 4608 mov r0, r1 8015ade: 602b str r3, [r5, #0] 8015ae0: f7f7 fbc7 bl 800d272 <_close> 8015ae4: 1c43 adds r3, r0, #1 8015ae6: d102 bne.n 8015aee <_close_r+0x1a> 8015ae8: 682b ldr r3, [r5, #0] 8015aea: b103 cbz r3, 8015aee <_close_r+0x1a> 8015aec: 6023 str r3, [r4, #0] 8015aee: bd38 pop {r3, r4, r5, pc} 8015af0: 20001328 .word 0x20001328 08015af4 <_fstat_r>: 8015af4: b538 push {r3, r4, r5, lr} 8015af6: 2300 movs r3, #0 8015af8: 4d06 ldr r5, [pc, #24] @ (8015b14 <_fstat_r+0x20>) 8015afa: 4604 mov r4, r0 8015afc: 4608 mov r0, r1 8015afe: 4611 mov r1, r2 8015b00: 602b str r3, [r5, #0] 8015b02: f7f7 fbc1 bl 800d288 <_fstat> 8015b06: 1c43 adds r3, r0, #1 8015b08: d102 bne.n 8015b10 <_fstat_r+0x1c> 8015b0a: 682b ldr r3, [r5, #0] 8015b0c: b103 cbz r3, 8015b10 <_fstat_r+0x1c> 8015b0e: 6023 str r3, [r4, #0] 8015b10: bd38 pop {r3, r4, r5, pc} 8015b12: bf00 nop 8015b14: 20001328 .word 0x20001328 08015b18 : 8015b18: 2006 movs r0, #6 8015b1a: b508 push {r3, lr} 8015b1c: f000 f8b0 bl 8015c80 8015b20: 2001 movs r0, #1 8015b22: f7f7 fb7e bl 800d222 <_exit> 08015b26 <_calloc_r>: 8015b26: b570 push {r4, r5, r6, lr} 8015b28: fba1 5402 umull r5, r4, r1, r2 8015b2c: b934 cbnz r4, 8015b3c <_calloc_r+0x16> 8015b2e: 4629 mov r1, r5 8015b30: f7ff f938 bl 8014da4 <_malloc_r> 8015b34: 4606 mov r6, r0 8015b36: b928 cbnz r0, 8015b44 <_calloc_r+0x1e> 8015b38: 4630 mov r0, r6 8015b3a: bd70 pop {r4, r5, r6, pc} 8015b3c: 220c movs r2, #12 8015b3e: 2600 movs r6, #0 8015b40: 6002 str r2, [r0, #0] 8015b42: e7f9 b.n 8015b38 <_calloc_r+0x12> 8015b44: 462a mov r2, r5 8015b46: 4621 mov r1, r4 8015b48: f7fd ff9a bl 8013a80 8015b4c: e7f4 b.n 8015b38 <_calloc_r+0x12> ... 08015b50 <_free_r>: 8015b50: b538 push {r3, r4, r5, lr} 8015b52: 4605 mov r5, r0 8015b54: 2900 cmp r1, #0 8015b56: d040 beq.n 8015bda <_free_r+0x8a> 8015b58: f851 3c04 ldr.w r3, [r1, #-4] 8015b5c: 1f0c subs r4, r1, #4 8015b5e: 2b00 cmp r3, #0 8015b60: bfb8 it lt 8015b62: 18e4 addlt r4, r4, r3 8015b64: f7ff fa46 bl 8014ff4 <__malloc_lock> 8015b68: 4a1c ldr r2, [pc, #112] @ (8015bdc <_free_r+0x8c>) 8015b6a: 6813 ldr r3, [r2, #0] 8015b6c: b933 cbnz r3, 8015b7c <_free_r+0x2c> 8015b6e: 6063 str r3, [r4, #4] 8015b70: 6014 str r4, [r2, #0] 8015b72: 4628 mov r0, r5 8015b74: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8015b78: f7ff ba42 b.w 8015000 <__malloc_unlock> 8015b7c: 42a3 cmp r3, r4 8015b7e: d908 bls.n 8015b92 <_free_r+0x42> 8015b80: 6820 ldr r0, [r4, #0] 8015b82: 1821 adds r1, r4, r0 8015b84: 428b cmp r3, r1 8015b86: bf01 itttt eq 8015b88: 6819 ldreq r1, [r3, #0] 8015b8a: 685b ldreq r3, [r3, #4] 8015b8c: 1809 addeq r1, r1, r0 8015b8e: 6021 streq r1, [r4, #0] 8015b90: e7ed b.n 8015b6e <_free_r+0x1e> 8015b92: 461a mov r2, r3 8015b94: 685b ldr r3, [r3, #4] 8015b96: b10b cbz r3, 8015b9c <_free_r+0x4c> 8015b98: 42a3 cmp r3, r4 8015b9a: d9fa bls.n 8015b92 <_free_r+0x42> 8015b9c: 6811 ldr r1, [r2, #0] 8015b9e: 1850 adds r0, r2, r1 8015ba0: 42a0 cmp r0, r4 8015ba2: d10b bne.n 8015bbc <_free_r+0x6c> 8015ba4: 6820 ldr r0, [r4, #0] 8015ba6: 4401 add r1, r0 8015ba8: 1850 adds r0, r2, r1 8015baa: 4283 cmp r3, r0 8015bac: 6011 str r1, [r2, #0] 8015bae: d1e0 bne.n 8015b72 <_free_r+0x22> 8015bb0: 6818 ldr r0, [r3, #0] 8015bb2: 685b ldr r3, [r3, #4] 8015bb4: 4408 add r0, r1 8015bb6: 6010 str r0, [r2, #0] 8015bb8: 6053 str r3, [r2, #4] 8015bba: e7da b.n 8015b72 <_free_r+0x22> 8015bbc: d902 bls.n 8015bc4 <_free_r+0x74> 8015bbe: 230c movs r3, #12 8015bc0: 602b str r3, [r5, #0] 8015bc2: e7d6 b.n 8015b72 <_free_r+0x22> 8015bc4: 6820 ldr r0, [r4, #0] 8015bc6: 1821 adds r1, r4, r0 8015bc8: 428b cmp r3, r1 8015bca: bf01 itttt eq 8015bcc: 6819 ldreq r1, [r3, #0] 8015bce: 685b ldreq r3, [r3, #4] 8015bd0: 1809 addeq r1, r1, r0 8015bd2: 6021 streq r1, [r4, #0] 8015bd4: 6063 str r3, [r4, #4] 8015bd6: 6054 str r4, [r2, #4] 8015bd8: e7cb b.n 8015b72 <_free_r+0x22> 8015bda: bd38 pop {r3, r4, r5, pc} 8015bdc: 20001324 .word 0x20001324 08015be0 <__ascii_mbtowc>: 8015be0: b082 sub sp, #8 8015be2: b901 cbnz r1, 8015be6 <__ascii_mbtowc+0x6> 8015be4: a901 add r1, sp, #4 8015be6: b142 cbz r2, 8015bfa <__ascii_mbtowc+0x1a> 8015be8: b14b cbz r3, 8015bfe <__ascii_mbtowc+0x1e> 8015bea: 7813 ldrb r3, [r2, #0] 8015bec: 600b str r3, [r1, #0] 8015bee: 7812 ldrb r2, [r2, #0] 8015bf0: 1e10 subs r0, r2, #0 8015bf2: bf18 it ne 8015bf4: 2001 movne r0, #1 8015bf6: b002 add sp, #8 8015bf8: 4770 bx lr 8015bfa: 4610 mov r0, r2 8015bfc: e7fb b.n 8015bf6 <__ascii_mbtowc+0x16> 8015bfe: f06f 0001 mvn.w r0, #1 8015c02: e7f8 b.n 8015bf6 <__ascii_mbtowc+0x16> 08015c04 <_malloc_usable_size_r>: 8015c04: f851 3c04 ldr.w r3, [r1, #-4] 8015c08: 1f18 subs r0, r3, #4 8015c0a: 2b00 cmp r3, #0 8015c0c: bfbc itt lt 8015c0e: 580b ldrlt r3, [r1, r0] 8015c10: 18c0 addlt r0, r0, r3 8015c12: 4770 bx lr 08015c14 <__ascii_wctomb>: 8015c14: 4603 mov r3, r0 8015c16: 4608 mov r0, r1 8015c18: b141 cbz r1, 8015c2c <__ascii_wctomb+0x18> 8015c1a: 2aff cmp r2, #255 @ 0xff 8015c1c: d904 bls.n 8015c28 <__ascii_wctomb+0x14> 8015c1e: 228a movs r2, #138 @ 0x8a 8015c20: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015c24: 601a str r2, [r3, #0] 8015c26: 4770 bx lr 8015c28: 2001 movs r0, #1 8015c2a: 700a strb r2, [r1, #0] 8015c2c: 4770 bx lr 08015c2e <_raise_r>: 8015c2e: 291f cmp r1, #31 8015c30: b538 push {r3, r4, r5, lr} 8015c32: 4605 mov r5, r0 8015c34: 460c mov r4, r1 8015c36: d904 bls.n 8015c42 <_raise_r+0x14> 8015c38: 2316 movs r3, #22 8015c3a: 6003 str r3, [r0, #0] 8015c3c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015c40: bd38 pop {r3, r4, r5, pc} 8015c42: 6bc2 ldr r2, [r0, #60] @ 0x3c 8015c44: b112 cbz r2, 8015c4c <_raise_r+0x1e> 8015c46: f852 3021 ldr.w r3, [r2, r1, lsl #2] 8015c4a: b94b cbnz r3, 8015c60 <_raise_r+0x32> 8015c4c: 4628 mov r0, r5 8015c4e: f000 f831 bl 8015cb4 <_getpid_r> 8015c52: 4622 mov r2, r4 8015c54: 4601 mov r1, r0 8015c56: 4628 mov r0, r5 8015c58: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8015c5c: f000 b818 b.w 8015c90 <_kill_r> 8015c60: 2b01 cmp r3, #1 8015c62: d00a beq.n 8015c7a <_raise_r+0x4c> 8015c64: 1c59 adds r1, r3, #1 8015c66: d103 bne.n 8015c70 <_raise_r+0x42> 8015c68: 2316 movs r3, #22 8015c6a: 6003 str r3, [r0, #0] 8015c6c: 2001 movs r0, #1 8015c6e: e7e7 b.n 8015c40 <_raise_r+0x12> 8015c70: 2100 movs r1, #0 8015c72: 4620 mov r0, r4 8015c74: f842 1024 str.w r1, [r2, r4, lsl #2] 8015c78: 4798 blx r3 8015c7a: 2000 movs r0, #0 8015c7c: e7e0 b.n 8015c40 <_raise_r+0x12> ... 08015c80 : 8015c80: 4b02 ldr r3, [pc, #8] @ (8015c8c ) 8015c82: 4601 mov r1, r0 8015c84: 6818 ldr r0, [r3, #0] 8015c86: f7ff bfd2 b.w 8015c2e <_raise_r> 8015c8a: bf00 nop 8015c8c: 20000084 .word 0x20000084 08015c90 <_kill_r>: 8015c90: b538 push {r3, r4, r5, lr} 8015c92: 2300 movs r3, #0 8015c94: 4d06 ldr r5, [pc, #24] @ (8015cb0 <_kill_r+0x20>) 8015c96: 4604 mov r4, r0 8015c98: 4608 mov r0, r1 8015c9a: 4611 mov r1, r2 8015c9c: 602b str r3, [r5, #0] 8015c9e: f7f7 fab0 bl 800d202 <_kill> 8015ca2: 1c43 adds r3, r0, #1 8015ca4: d102 bne.n 8015cac <_kill_r+0x1c> 8015ca6: 682b ldr r3, [r5, #0] 8015ca8: b103 cbz r3, 8015cac <_kill_r+0x1c> 8015caa: 6023 str r3, [r4, #0] 8015cac: bd38 pop {r3, r4, r5, pc} 8015cae: bf00 nop 8015cb0: 20001328 .word 0x20001328 08015cb4 <_getpid_r>: 8015cb4: f7f7 ba9e b.w 800d1f4 <_getpid> 08015cb8 <_init>: 8015cb8: b5f8 push {r3, r4, r5, r6, r7, lr} 8015cba: bf00 nop 8015cbc: bcf8 pop {r3, r4, r5, r6, r7} 8015cbe: bc08 pop {r3} 8015cc0: 469e mov lr, r3 8015cc2: 4770 bx lr 08015cc4 <_fini>: 8015cc4: b5f8 push {r3, r4, r5, r6, r7, lr} 8015cc6: bf00 nop 8015cc8: bcf8 pop {r3, r4, r5, r6, r7} 8015cca: bc08 pop {r3} 8015ccc: 469e mov lr, r3 8015cce: 4770 bx lr