Protel Design System Design Rule Check
PCB File : C:\Users\ASUS\YandexDisk-gas@mtcgeo.com\Altium\NV_Project\EDISON_GIT\TKZU22_SIM800_adapter\PCB\SIM800_adapter.PcbDoc
Date     : 25.06.2024
Time     : 23:00:26

Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0

Processing Rule : Width Constraint (Min=0.15mm) (Max=10mm) (Preferred=0.4mm) (All)
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.2mm) (Conductor Width=0.2mm) (Air Gap=0.2mm) (Entries=4) (All)
Rule Violations :0

Processing Rule : Minimum Annular Ring (Minimum=0.15mm) (IsVia)
Rule Violations :0

Processing Rule : Minimum Annular Ring (Minimum=0.15mm) (IsPAD)
Rule Violations :0

Processing Rule : Minimum Annular Ring (Minimum=0.1mm) (IsVia)
Rule Violations :0

Processing Rule : Minimum Annular Ring (Minimum=0.2mm) (IsPAD)
Rule Violations :0

Processing Rule : Acute Angle Constraint (Minimum=35.000) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=0.6mm) (Max=5.9mm) (IsPad)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
Rule Violations :0

Processing Rule : Minimum Solder Mask Sliver (Gap=0.15mm) (All),(All)
Rule Violations :0

Processing Rule : Silk To Solder Mask (Clearance=0.15mm) (Disabled)(IsPad),(All)
Rule Violations :0

Processing Rule : Silk to Silk (Clearance=0.15mm) (Disabled)(All),(All)
Rule Violations :0

Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0

Processing Rule : Board Clearance Constraint (Gap=0mm) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0


Violations Detected : 0
Waived Violations : 0
Time Elapsed        : 00:00:01