Altium

Design Rule Verification Report

Date: 13.08.2024
Time: 0:18:12
Elapsed Time: 00:00:01
Filename: C:\Users\ASUS\YandexDisk-gas@mtcgeo.com\Altium\NV_Project\EDISON_GIT\TKZU22_SIM800_adapter\PCB\SIM800_adapter.PcbDoc
Warnings: 0
Rule Violations: 0

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=0.2mm) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=0.15mm) (Max=10mm) (Preferred=0.4mm) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.2mm) (Conductor Width=0.2mm) (Air Gap=0.2mm) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=0.15mm) (IsVia) 0
Minimum Annular Ring (Minimum=0.15mm) (IsPAD) 0
Minimum Annular Ring (Minimum=0.1mm) (IsVia) 0
Minimum Annular Ring (Minimum=0.2mm) (IsPAD) 0
Acute Angle Constraint (Minimum=35.000) (All) 0
Hole Size Constraint (Min=0.6mm) (Max=5.9mm) (IsPad) 0
Hole To Hole Clearance (Gap=0.25mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.15mm) (All),(All) 0
Silk To Solder Mask (Clearance=0.15mm) (Disabled)(IsPad),(All) 0
Silk to Silk (Clearance=0.15mm) (Disabled)(All),(All) 0
Net Antennae (Tolerance=0mm) (All) 0
Board Clearance Constraint (Gap=0mm) (All) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Total 0