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- вынес резисторы наружу модуля
- в ВОМ добавлены PBS-6 для модуля
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artem_golubev
2024-06-25 23:03:05 +03:00
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commit d2fcc44129
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66
Project Outputs for TKZU22_SIM800_adapter/Design Rule Check - SIM800_adapter.drc Normal file
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Protel Design System Design Rule Check
PCB File : C:\Users\ASUS\YandexDisk-gas@mtcgeo.com\Altium\NV_Project\EDISON_GIT\TKZU22_SIM800_adapter\PCB\SIM800_adapter.PcbDoc
Date : 25.06.2024
Time : 23:00:26
Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.15mm) (Max=10mm) (Preferred=0.4mm) (All)
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.2mm) (Conductor Width=0.2mm) (Air Gap=0.2mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Minimum Annular Ring (Minimum=0.15mm) (IsVia)
Rule Violations :0
Processing Rule : Minimum Annular Ring (Minimum=0.15mm) (IsPAD)
Rule Violations :0
Processing Rule : Minimum Annular Ring (Minimum=0.1mm) (IsVia)
Rule Violations :0
Processing Rule : Minimum Annular Ring (Minimum=0.2mm) (IsPAD)
Rule Violations :0
Processing Rule : Acute Angle Constraint (Minimum=35.000) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.6mm) (Max=5.9mm) (IsPad)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.15mm) (All),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0.15mm) (Disabled)(IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0.15mm) (Disabled)(All),(All)
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0
Processing Rule : Board Clearance Constraint (Gap=0mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Violations Detected : 0
Waived Violations : 0
Time Elapsed : 00:00:01

348
Project Outputs for TKZU22_SIM800_adapter/Design Rule Check - SIM800_adapter.html Normal file
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</script><title>Design Rule Verification Report</title>
</head>
<body onload=""><img ALT="Altium" src="
file://C:\Users\Public\Documents\Altium\AD24\Templates\AD_logo.png
"><h1>Design Rule Verification Report</h1>
<table class="header_holder">
<td class="column1">
<table class="front_matter">
<tr class="front_matter">
<td class="front_matter_column1">Date:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">25.06.2024</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Time:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">23:00:26</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Elapsed Time:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">00:00:01</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Filename:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3"><a href="file:///C:\Users\ASUS\YandexDisk-gas@mtcgeo.com\Altium\NV_Project\EDISON_GIT\TKZU22_SIM800_adapter\PCB\SIM800_adapter.PcbDoc" class="file"><acronym title="C:\Users\ASUS\YandexDisk-gas@mtcgeo.com\Altium\NV_Project\EDISON_GIT\TKZU22_SIM800_adapter\PCB\SIM800_adapter.PcbDoc">C:\Users\ASUS\YandexDisk-gas@mtcgeo.com\Altium\NV_Project\EDISON_GIT\TKZU22_SIM800_adapter\PCB\SIM800_adapter.PcbDoc</acronym></a></td>
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<td class="column2">
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<td class="DRC_summary_header_col1">Warnings:</td>
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<td class="DRC_summary_header_col3">0</td></tr>
<tr>
<td class="DRC_summary_header_col1">Rule Violations:</td>
<td class="DRC_summary_header_col2"></td>
<td class="DRC_summary_header_col3">0</td></tr>
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</td>
</table><a name="IDHHTAIGL5FB5BJ45VMZM1ZX32KMIFCQUF2JX311EQSQDYLBMNQ20N"><h2>Summary</h2></a><table>
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<th class="column1">Warnings</th>
<th class="column2">Count</th>
</tr>
<tr>
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
<td style="font-weight : bold" class="column2">0</td>
</tr>
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<tr>
<th class="column1">Rule Violations</th>
<th class="column2">Count</th>
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<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDKA42TEPTDU10PCEPFUFRW31DEGGOAI1SVFSBYTPWEXMGVSDUZZII">Clearance Constraint (Gap=0.2mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDENOJKYJQ2O4RLV3YQ3H4LIYLQC0E4H2YLY4S0ZPRGYAYSYNFKKIF">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
<td class="column2">0</td>
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<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDHT4LZPPL25JIKPZ2U0W2ROHZCI3PK0EQSCYJPPIKRFRGFB5UDXQM">Un-Routed Net Constraint ( (All) )</a></td>
<td class="column2">0</td>
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<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDWT23CTUYO41XBX4TCYJDT25GPDAVJ1BHOL1XB0ECQKKGYU2VWTEG">Modified Polygon (Allow modified: No), (Allow shelved: No)</a></td>
<td class="column2">0</td>
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<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDDJQQSZJCZCE3PXTKNVL0YZYWKI0YIAIIU5HCFEFOCFQ3VPWDHCL">Width Constraint (Min=0.15mm) (Max=10mm) (Preferred=0.4mm) (All)</a></td>
<td class="column2">0</td>
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<td class="column1"><a href="#IDRIHOQHEB32SMP0MDQ4TCLQRAVNBM1IV5IRVVWRODXIWA4JDNJPFK">Power Plane Connect Rule(Relief Connect )(Expansion=0.2mm) (Conductor Width=0.2mm) (Air Gap=0.2mm) (Entries=4) (All)</a></td>
<td class="column2">0</td>
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<td class="column1"><a href="#IDXREWKELKEHFFBMZCYRFGZLUWEL5GT5AV1BPNXHK1TXM14CLQ3SKH">Minimum Annular Ring (Minimum=0.15mm) (IsVia)</a></td>
<td class="column2">0</td>
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<td class="column1"><a href="#IDMGHRF0O43A2VDMKMQEK150MJNIXWPPIBGVKQROUTQUNJCVZS44F">Minimum Annular Ring (Minimum=0.15mm) (IsPAD)</a></td>
<td class="column2">0</td>
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<td class="column1"><a href="#IDGVDTY0NCLCRHHKILIYNJCDNSDKC1OHOBHUEJGGKRWJE5A4E3JTQJ">Minimum Annular Ring (Minimum=0.1mm) (IsVia)</a></td>
<td class="column2">0</td>
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<td class="column1"><a href="#IDHQEPPHM22LUKI3MDHVXXASH2RO35ELKXEU4UHBFBQ1E25JFE51FP">Minimum Annular Ring (Minimum=0.2mm) (IsPAD)</a></td>
<td class="column2">0</td>
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<td class="column2">0</td>
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<td class="column2">0</td>
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<td class="column2">0</td>
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<td class="column1"><a href="#IDOP3GJXU5G55OBZ41X2YBSLWLSP50DME15LV10AKPLYATB3CFVVT">Minimum Solder Mask Sliver (Gap=0.15mm) (All),(All)</a></td>
<td class="column2">0</td>
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<td class="column2">0</td>
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<td class="column1"><a href="#IDU4YQMUSJIQVVOGHYXPA4NWEZLJTT5V2PP4H5INGQDLV2CNCK5BZB">Silk to Silk (Clearance=0.15mm) (Disabled)(All),(All)</a></td>
<td class="column2">0</td>
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<td class="column1"><a href="#ID0DCCVBMF53VNIA2AAHPAXK5XYDTQTCEZ0EFFK1ORFYUIGUA4QCOM">Net Antennae (Tolerance=0mm) (All)</a></td>
<td class="column2">0</td>
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<td class="column1"><a href="#IDSS4KXDXBQDQ0MNCBTKGEYPI2AFJCEOOJ1XKLR5JJMSQBAUR14VX">Board Clearance Constraint (Gap=0mm) (All)</a></td>
<td class="column2">0</td>
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<td class="column2">0</td>
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<tr>
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
<td style="font-weight : bold" class="column2">0</td>
</tr>
</table><br></body>
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