Initialize LED_AC repository and set LED status colors per station modes.
Add project sources with a minimal gitignore for IDE/build artifacts only while keeping firmware files tracked. Made-with: Cursor
This commit is contained in:
+675
@@ -0,0 +1,675 @@
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/**
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******************************************************************************
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* @file stm32l0xx_hal.c
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* @author MCD Application Team
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* @brief HAL module driver.
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* This is the common part of the HAL initialization
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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The common HAL driver contains a set of generic and common APIs that can be
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used by the PPP peripheral drivers and the user to start using the HAL.
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[..]
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The HAL contains two APIs categories:
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(+) Common HAL APIs
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(+) Services HAL APIs
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@endverbatim
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l0xx_hal.h"
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/** @addtogroup STM32L0xx_HAL_Driver
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* @{
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*/
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#ifdef HAL_MODULE_ENABLED
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/** @addtogroup HAL
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* @brief HAL module driver.
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* @{
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*/
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/** @addtogroup HAL_Exported_Constants
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* @{
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*/
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/** @defgroup HAL_Version HAL Version
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* @{
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*/
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/**
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* @brief STM32L0xx HAL Driver version number
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*/
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#define __STM32L0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
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#define __STM32L0xx_HAL_VERSION_SUB1 (0x0AU) /*!< [23:16] sub1 version */
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#define __STM32L0xx_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */
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#define __STM32L0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
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#define __STM32L0xx_HAL_VERSION ((__STM32L0xx_HAL_VERSION_MAIN << 24U)\
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|(__STM32L0xx_HAL_VERSION_SUB1 << 16U)\
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|(__STM32L0xx_HAL_VERSION_SUB2 << 8U )\
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|(__STM32L0xx_HAL_VERSION_RC))
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#define IDCODE_DEVID_MASK (0x00000FFFU)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported variables --------------------------------------------------------*/
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/** @addtogroup HAL_Exported_Variables
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* @{
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*/
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__IO uint32_t uwTick;
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uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
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HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup HAL_Exported_Functions
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* @{
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*/
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/** @addtogroup HAL_Exported_Functions_Group1
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* @brief Initialization and de-initialization functions
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*
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@verbatim
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===============================================================================
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##### Initialization and de-initialization functions #####
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===============================================================================
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[..] This section provides functions allowing to:
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(+) Initialize the Flash interface, the NVIC allocation and initial clock
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configuration. It initializes the source of time base also when timeout
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is needed and the backup domain when enabled.
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(+) De-initialize common part of the HAL.
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(+) Configure the time base source to have 1ms time base with a dedicated
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Tick interrupt priority.
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(++) SysTick timer is used by default as source of time base, but user
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can eventually implement his proper time base source (a general purpose
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timer for example or other time source), keeping in mind that Time base
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duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
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handled in milliseconds basis.
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(++) Time base configuration function (HAL_InitTick ()) is called automatically
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at the beginning of the program after reset by HAL_Init() or at any time
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when clock is configured, by HAL_RCC_ClockConfig().
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(++) Source of time base is configured to generate interrupts at regular
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time intervals. Care must be taken if HAL_Delay() is called from a
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peripheral ISR process, the Tick interrupt line must have higher priority
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(numerically lower) than the peripheral interrupt. Otherwise the caller
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ISR process will be blocked.
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(++) functions affecting time base configurations are declared as __weak
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to make override possible in case of other implementations in user file.
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@endverbatim
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* @{
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*/
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/**
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* @brief This function configures the Flash prefetch, Flash preread and Buffer cache,
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* Configures time base source, NVIC and Low level hardware
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* @note This function is called at the beginning of program after reset and before
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* the clock configuration
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* @note The time base configuration is based on MSI clock when exiting from Reset.
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* Once done, time base tick start incrementing.
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* In the default implementation,Systick is used as source of time base.
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* the tick variable is incremented each 1ms in its ISR.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_Init(void)
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{
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HAL_StatusTypeDef status = HAL_OK;
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/* Configure Buffer cache, Flash prefetch, Flash preread */
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#if (BUFFER_CACHE_DISABLE != 0)
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__HAL_FLASH_BUFFER_CACHE_DISABLE();
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#endif /* BUFFER_CACHE_DISABLE */
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#if (PREREAD_ENABLE != 0)
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__HAL_FLASH_PREREAD_BUFFER_ENABLE();
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#endif /* PREREAD_ENABLE */
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#if (PREFETCH_ENABLE != 0)
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__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
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#endif /* PREFETCH_ENABLE */
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/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
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if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
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{
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status = HAL_ERROR;
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}
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else
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{
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/* Init the low level hardware */
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HAL_MspInit();
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}
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/* Return function status */
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return status;
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}
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/**
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* @brief This function de-initializes common part of the HAL and stops the source
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* of time base.
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* @note This function is optional.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DeInit(void)
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{
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/* Reset of all peripherals */
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__HAL_RCC_APB1_FORCE_RESET();
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__HAL_RCC_APB1_RELEASE_RESET();
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__HAL_RCC_APB2_FORCE_RESET();
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__HAL_RCC_APB2_RELEASE_RESET();
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__HAL_RCC_AHB_FORCE_RESET();
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__HAL_RCC_AHB_RELEASE_RESET();
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__HAL_RCC_IOP_FORCE_RESET();
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__HAL_RCC_IOP_RELEASE_RESET();
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/* De-Init the low level hardware */
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HAL_MspDeInit();
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/* Return function status */
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return HAL_OK;
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}
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/**
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* @brief Initializes the MSP.
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* @retval None
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*/
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__weak void HAL_MspInit(void)
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{
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/* NOTE : This function should not be modified, when the callback is needed,
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the HAL_MspInit could be implemented in the user file
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*/
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}
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/**
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* @brief DeInitializes the MSP.
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* @retval None
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||||
*/
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__weak void HAL_MspDeInit(void)
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{
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||||
/* NOTE : This function should not be modified, when the callback is needed,
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||||
the HAL_MspDeInit could be implemented in the user file
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||||
*/
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}
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||||
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/**
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* @brief This function configures the source of the time base:
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||||
* The time source is configured to have 1ms time base with a dedicated
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* Tick interrupt priority.
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||||
* @note This function is called automatically at the beginning of program after
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* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
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||||
* @note In the default implementation, SysTick timer is the source of time base.
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||||
* It is used to generate interrupts at regular time intervals.
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* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
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||||
* The SysTick interrupt must have higher priority (numerically lower)
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* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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* The function is declared as __weak to be overwritten in case of other
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* implementation in user file.
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* @param TickPriority Tick interrupt priority.
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* @retval HAL status
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*/
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__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
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{
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/* Configure the SysTick to have interrupt in 1ms time basis*/
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if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
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{
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return HAL_ERROR;
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}
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/* Configure the SysTick IRQ priority */
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if (TickPriority < (1UL << __NVIC_PRIO_BITS))
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{
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HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
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uwTickPrio = TickPriority;
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}
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else
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{
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return HAL_ERROR;
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}
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/* Return function status */
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return HAL_OK;
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}
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/**
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* @}
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*/
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/** @addtogroup HAL_Exported_Functions_Group2
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||||
* @brief HAL Control functions
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*
|
||||
@verbatim
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||||
===============================================================================
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||||
##### HAL Control functions #####
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||||
===============================================================================
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||||
[..] This section provides functions allowing to:
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(+) Provide a tick value in millisecond
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(+) Provide a blocking delay in millisecond
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(+) Suspend the time base source interrupt
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||||
(+) Resume the time base source interrupt
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||||
(+) Get the HAL API driver version
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(+) Get the device identifier
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||||
(+) Get the device revision identifier
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||||
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||||
@endverbatim
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||||
* @{
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||||
*/
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||||
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/**
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||||
* @brief This function is called to increment a global variable "uwTick"
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||||
* used as application time base.
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||||
* @note In the default implementation, this variable is incremented each 1ms
|
||||
* in SysTick ISR.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
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* implementations in user file.
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* @retval None
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||||
*/
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__weak void HAL_IncTick(void)
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{
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uwTick += uwTickFreq;
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}
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||||
/**
|
||||
* @brief Provides a tick value in millisecond.
|
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* @note This function is declared as __weak to be overwritten in case of other
|
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* implementations in user file.
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* @retval tick value
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*/
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__weak uint32_t HAL_GetTick(void)
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{
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return uwTick;
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}
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/**
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* @brief This function returns a tick priority.
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* @retval tick priority
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||||
*/
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uint32_t HAL_GetTickPrio(void)
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||||
{
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return uwTickPrio;
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}
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|
||||
/**
|
||||
* @brief Set new tick Freq.
|
||||
* @retval Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
HAL_TickFreqTypeDef prevTickFreq;
|
||||
|
||||
assert_param(IS_TICKFREQ(Freq));
|
||||
|
||||
if (uwTickFreq != Freq)
|
||||
{
|
||||
/* Back up uwTickFreq frequency */
|
||||
prevTickFreq = uwTickFreq;
|
||||
|
||||
/* Update uwTickFreq global variable used by HAL_InitTick() */
|
||||
uwTickFreq = Freq;
|
||||
|
||||
/* Apply the new tick Freq */
|
||||
status = HAL_InitTick(uwTickPrio);
|
||||
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Restore previous tick frequency */
|
||||
uwTickFreq = prevTickFreq;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return tick frequency.
|
||||
* @retval Tick frequency.
|
||||
* Value of @ref HAL_TickFreqTypeDef.
|
||||
*/
|
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
|
||||
{
|
||||
return uwTickFreq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function provides minimum delay (in milliseconds) based
|
||||
* on variable incremented.
|
||||
* @note In the default implementation , SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals where uwTick
|
||||
* is incremented.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param Delay specifies the delay time length, in milliseconds.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_Delay(uint32_t Delay)
|
||||
{
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
uint32_t wait = Delay;
|
||||
|
||||
/* Add a freq to guarantee minimum wait */
|
||||
if (wait < HAL_MAX_DELAY)
|
||||
{
|
||||
wait += (uint32_t)(uwTickFreq);
|
||||
}
|
||||
|
||||
while((HAL_GetTick() - tickstart) < wait)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspends the Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
|
||||
* is called, the SysTick interrupt will be disabled and so Tick increment
|
||||
* is suspended.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SuspendTick(void)
|
||||
{
|
||||
/* Disable SysTick Interrupt */
|
||||
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resumes the Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
|
||||
* is called, the SysTick interrupt will be enabled and so Tick increment
|
||||
* is resumed.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ResumeTick(void)
|
||||
{
|
||||
/* Enable SysTick Interrupt */
|
||||
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the HAL revision
|
||||
* @retval version: 0xXYZR (8bits for each decimal, R for RC)
|
||||
*/
|
||||
uint32_t HAL_GetHalVersion(void)
|
||||
{
|
||||
return __STM32L0xx_HAL_VERSION;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier.
|
||||
* @retval Device revision identifier
|
||||
*/
|
||||
uint32_t HAL_GetREVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) >> 16U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device identifier.
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetDEVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the first word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw0(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)UID_BASE)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the second word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw1(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)(UID_BASE + 0x04U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the third word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw2(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)(UID_BASE + 0x14U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group2
|
||||
* @brief HAL Debug functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### HAL Debug functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Enable/Disable Debug module during SLEEP mode
|
||||
(+) Enable/Disable Debug module during STOP mode
|
||||
(+) Enable/Disable Debug module during STANDBY mode
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables the Debug Module during SLEEP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGSleepMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Debug Module during SLEEP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGSleepMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable low power mode behavior when the MCU is in Debug mode.
|
||||
* @param Periph: specifies the low power mode.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
|
||||
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode
|
||||
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DBGMCU_PERIPH(Periph));
|
||||
|
||||
DBGMCU->CR |= Periph;
|
||||
|
||||
}
|
||||
/**
|
||||
* @brief Disable low power mode behavior when the MCU is in Debug mode.
|
||||
* @param Periph: specifies the low power mode.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
|
||||
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode
|
||||
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DBGMCU_PERIPH(Periph));
|
||||
{
|
||||
DBGMCU->CR &= ~Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group3
|
||||
* @brief HAL SYSCFG configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### HAL SYSCFG configuration functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Return the boot mode
|
||||
(+) Select the output of internal reference voltage (VREFINT)
|
||||
(+) Lock/Unlock the SYSCFG VREF register values
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the boot mode as configured by user.
|
||||
* @retval The boot mode as configured by user. The returned value can be one
|
||||
* of the following values:
|
||||
* - 0x00000000 : Boot is configured in Main Flash memory
|
||||
* - 0x00000100 : Boot is configured in System Flash memory
|
||||
* - 0x00000300 : Boot is configured in Embedded SRAM memory
|
||||
*/
|
||||
uint32_t HAL_SYSCFG_GetBootMode(void)
|
||||
{
|
||||
return (SYSCFG->CFGR1 & SYSCFG_CFGR1_BOOT_MODE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the output of internal reference voltage (VREFINT).
|
||||
* The VREFINT output can be routed to(PB0) or
|
||||
* (PB1) or both.
|
||||
* @param SYSCFG_Vrefint_OUTPUT: new state of the Vrefint output.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSCFG_VREFINT_OUT_NONE
|
||||
* @arg SYSCFG_VREFINT_OUT_PB0
|
||||
* @arg SYSCFG_VREFINT_OUT_PB1
|
||||
* @arg SYSCFG_VREFINT_OUT_PB0_PB1
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSCFG_VREFINT_OUT_SELECT(SYSCFG_Vrefint_OUTPUT));
|
||||
|
||||
/* Set the output Vrefint pin */
|
||||
SYSCFG->CFGR3 &= ~(SYSCFG_CFGR3_VREF_OUT);
|
||||
SYSCFG->CFGR3 |= (uint32_t)(SYSCFG_Vrefint_OUTPUT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Lock the SYSCFG VREF register values
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSCFG_Enable_Lock_VREFINT(void)
|
||||
{
|
||||
/* Enable the LOCK by setting REF_LOCK bit in the CFGR3 register */
|
||||
SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unlock the overall SYSCFG VREF register values
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSCFG_Disable_Lock_VREFINT(void)
|
||||
{
|
||||
/* Disable the LOCK by setting REF_LOCK bit in the CFGR3 register */
|
||||
CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* HAL_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
+416
@@ -0,0 +1,416 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l0xx_hal_cortex.c
|
||||
* @author MCD Application Team
|
||||
* @brief CORTEX HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the CORTEX:
|
||||
* + Initialization and Configuration functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
*** How to configure Interrupts using CORTEX HAL driver ***
|
||||
===========================================================
|
||||
[..]
|
||||
This section provides functions allowing to configure the NVIC interrupts (IRQ).
|
||||
The Cortex M0+ exceptions are managed by CMSIS functions.
|
||||
(#) Enable and Configure the priority of the selected IRQ Channels.
|
||||
The priority can be 0..3.
|
||||
|
||||
-@- Lower priority values gives higher priority.
|
||||
-@- Priority Order:
|
||||
(#@) Lowest priority.
|
||||
(#@) Lowest hardware priority (IRQn position).
|
||||
|
||||
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
|
||||
|
||||
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
|
||||
|
||||
[..]
|
||||
*** How to configure Systick using CORTEX HAL driver ***
|
||||
========================================================
|
||||
[..]
|
||||
Setup SysTick Timer for time base.
|
||||
|
||||
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
|
||||
is a CMSIS function that:
|
||||
(++) Configures the SysTick Reload register with value passed as function parameter.
|
||||
(++) Configures the SysTick IRQ priority to the lowest value (0x03).
|
||||
(++) Resets the SysTick Counter register.
|
||||
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
|
||||
(++) Enables the SysTick Interrupt.
|
||||
(++) Starts the SysTick Counter.
|
||||
|
||||
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function
|
||||
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
|
||||
HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() function is defined
|
||||
inside the stm32l0xx_hal_cortex.c file.
|
||||
|
||||
(+) You can change the SysTick IRQ priority by calling the
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
|
||||
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
|
||||
|
||||
(+) To adjust the SysTick time base, use the following formula:
|
||||
|
||||
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
|
||||
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
|
||||
(++) Reload Value should not exceed 0xFFFFFF
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
|
||||
/** @addtogroup CORTEX
|
||||
* @brief CORTEX HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group1
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
|
||||
Systick functionalities
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Sets the priority of an interrupt.
|
||||
* @param IRQn External interrupt number .
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
|
||||
* @param PreemptPriority The pre-emption priority for the IRQn channel.
|
||||
* This parameter can be a value between 0 and 3.
|
||||
* A lower priority value indicates a higher priority
|
||||
* @param SubPriority the subpriority level for the IRQ channel.
|
||||
* with stm32l0xx devices, this parameter is a dummy value and it is ignored, because
|
||||
* no subpriority supported in Cortex M0+ based products.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
||||
NVIC_SetPriority(IRQn,PreemptPriority);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable a device specific interrupt in the NVIC interrupt controller.
|
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
||||
* function should be called before.
|
||||
* @param IRQn External interrupt number .
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Enable interrupt */
|
||||
NVIC_EnableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable a device specific interrupt in the NVIC interrupt controller.
|
||||
* @param IRQn External interrupt number .
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Disable interrupt */
|
||||
NVIC_DisableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initiate a system reset request to reset the MCU.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SystemReset(void)
|
||||
{
|
||||
/* System Reset */
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick)
|
||||
* Counter is in free running mode to generate periodic interrupts.
|
||||
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
||||
* @retval status: - 0 Function succeeded.
|
||||
* - 1 Function failed.
|
||||
*/
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
||||
{
|
||||
return SysTick_Config(TicksNumb);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the CORTEX
|
||||
(NVIC, SYSTICK) functionalities.
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Gets the priority of an interrupt.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l0xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
/* Get priority for Cortex-M system or device specific interrupts */
|
||||
return NVIC_GetPriority(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets Pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Set interrupt pending */
|
||||
NVIC_SetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Pending Interrupt (read the pending register in the NVIC
|
||||
* and return the pending bit for the specified interrupt).
|
||||
* @param IRQn External interrupt number .
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
|
||||
* @retval status: - 0 Interrupt status is not pending.
|
||||
* - 1 Interrupt status is pending.
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Return 1 if pending else 0 */
|
||||
return NVIC_GetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number .
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Clear pending interrupt */
|
||||
NVIC_ClearPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configure the SysTick clock source.
|
||||
* @param CLKSource specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
|
||||
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle SYSTICK interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_IRQHandler(void)
|
||||
{
|
||||
HAL_SYSTICK_Callback();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SYSTICK callback.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SYSTICK_Callback(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_SYSTICK_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
/**
|
||||
* @brief Disable the MPU.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_Disable(void)
|
||||
{
|
||||
|
||||
/*Data Memory Barrier setup */
|
||||
__DMB();
|
||||
/* Disable the MPU */
|
||||
MPU->CTRL = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the MPU.
|
||||
* @param MPU_Control Specifies the control mode of the MPU during hard fault,
|
||||
* NMI, FAULTMASK and privileged access to the default memory
|
||||
* This parameter can be one of the following values:
|
||||
* @arg MPU_HFNMI_PRIVDEF_NONE
|
||||
* @arg MPU_HARDFAULT_NMI
|
||||
* @arg MPU_PRIVILEGED_DEFAULT
|
||||
* @arg MPU_HFNMI_PRIVDEF
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
/* Enable the MPU */
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
/* Data Synchronization Barrier setup */
|
||||
__DSB();
|
||||
/* Instruction Synchronization Barrier setup */
|
||||
__ISB();
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize and configure the Region and the memory to be protected.
|
||||
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
|
||||
* the initialization and configuration information.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
|
||||
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
|
||||
|
||||
/* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */
|
||||
__DMB();
|
||||
|
||||
/* Set the Region number */
|
||||
MPU->RNR = MPU_Init->Number;
|
||||
|
||||
if ((MPU_Init->Enable) == MPU_REGION_ENABLE)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
|
||||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
|
||||
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
|
||||
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
|
||||
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
|
||||
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
|
||||
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
|
||||
|
||||
/* Set the base adsress and set the 4 LSB to 0 */
|
||||
MPU->RBAR = (MPU_Init->BaseAddress) & 0xfffffff0U;
|
||||
|
||||
/* Fill the field RASR */
|
||||
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
|
||||
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
|
||||
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
|
||||
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
|
||||
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
|
||||
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
|
||||
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
|
||||
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
|
||||
}
|
||||
else
|
||||
{
|
||||
MPU->RBAR = 0x00U;
|
||||
MPU->RASR = 0x00U;
|
||||
}
|
||||
}
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
+886
@@ -0,0 +1,886 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l0xx_hal_dma.c
|
||||
* @author MCD Application Team
|
||||
* @brief DMA HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Direct Memory Access (DMA) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
* + Peripheral State and errors functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable and configure the peripheral to be connected to the DMA Channel
|
||||
(except for internal SRAM / FLASH memories: no initialization is
|
||||
necessary).
|
||||
|
||||
(#) For a given Channel, program the required configuration through the following parameters:
|
||||
Channel request, Transfer Direction, Source and Destination data formats,
|
||||
Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
|
||||
using HAL_DMA_Init() function.
|
||||
|
||||
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
|
||||
detection.
|
||||
|
||||
(#) Use HAL_DMA_Abort() function to abort the current transfer
|
||||
|
||||
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
|
||||
|
||||
*** Polling mode IO operation ***
|
||||
=================================
|
||||
[..]
|
||||
(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
|
||||
address and destination address and the Length of data to be transferred
|
||||
(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
|
||||
case a fixed Timeout can be configured by User depending from his application.
|
||||
|
||||
*** Interrupt mode IO operation ***
|
||||
===================================
|
||||
[..]
|
||||
(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
|
||||
(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
|
||||
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
|
||||
Source address and destination address and the Length of data to be transferred.
|
||||
In this case the DMA interrupt is configured
|
||||
(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
|
||||
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
|
||||
add his own function to register callbacks with HAL_DMA_RegisterCallback().
|
||||
|
||||
*** DMA HAL driver macros list ***
|
||||
=============================================
|
||||
[..]
|
||||
Below the list of macros in DMA HAL driver.
|
||||
|
||||
(+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
|
||||
(+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
|
||||
(+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
|
||||
(+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
|
||||
(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
|
||||
(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
|
||||
(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DMA HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA DMA
|
||||
* @brief DMA HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Functions DMA Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions DMA Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to initialize the DMA Channel source
|
||||
and destination addresses, incrementation and data sizes, transfer direction,
|
||||
circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
|
||||
[..]
|
||||
The HAL_DMA_Init() function follows the DMA configuration procedures as described in
|
||||
reference manual.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the DMA according to the specified
|
||||
* parameters in the DMA_InitTypeDef and initialize the associated handle.
|
||||
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
/* Check the DMA handle allocation */
|
||||
if(hdma == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
|
||||
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
|
||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
|
||||
assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
|
||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
|
||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
|
||||
assert_param(IS_DMA_MODE(hdma->Init.Mode));
|
||||
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
|
||||
|
||||
/* Compute the channel index */
|
||||
/* Only one DMA: DMA1 */
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
|
||||
hdma->DmaBaseAddress = DMA1;
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Get the CR register value */
|
||||
tmp = hdma->Instance->CCR;
|
||||
|
||||
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
|
||||
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE |
|
||||
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
|
||||
DMA_CCR_DIR | DMA_CCR_MEM2MEM));
|
||||
|
||||
/* Prepare the DMA Channel configuration */
|
||||
tmp |= hdma->Init.Direction |
|
||||
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
||||
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
||||
hdma->Init.Mode | hdma->Init.Priority;
|
||||
|
||||
/* Write to DMA Channel CR register */
|
||||
hdma->Instance->CCR = tmp;
|
||||
|
||||
/* Set request selection */
|
||||
if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
|
||||
{
|
||||
/* Write to DMA channel selection register */
|
||||
/* Reset request selection for DMA1 Channelx */
|
||||
DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
|
||||
|
||||
/* Configure request selection for DMA1 Channelx */
|
||||
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
|
||||
}
|
||||
|
||||
/* Initialise the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Initialize the DMA state*/
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Allocate lock resource and initialize it */
|
||||
hdma->Lock = HAL_UNLOCKED;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitialize the DMA peripheral.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
|
||||
/* Check the DMA handle allocation */
|
||||
if (NULL == hdma )
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
|
||||
/* Disable the selected DMA Channelx */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Compute the channel index */
|
||||
/* DMA1 */
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
|
||||
hdma->DmaBaseAddress = DMA1;
|
||||
|
||||
/* Reset DMA Channel control register */
|
||||
hdma->Instance->CCR = 0U;
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
|
||||
|
||||
/* Reset DMA channel selection register */
|
||||
/* DMA1 */
|
||||
DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
|
||||
|
||||
/* Clean callbacks */
|
||||
hdma->XferCpltCallback = NULL;
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
hdma->XferErrorCallback = NULL;
|
||||
hdma->XferAbortCallback = NULL;
|
||||
|
||||
/* Initialise the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Initialize the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @brief Input and Output operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure the source, destination address and data length and Start DMA transfer
|
||||
(+) Configure the source, destination address and data length and
|
||||
Start DMA transfer with interrupt
|
||||
(+) Abort DMA transfer
|
||||
(+) Poll for transfer complete
|
||||
(+) Handle DMA interrupt request
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start the DMA Transfer.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param DataLength The amount of data items to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Disable the peripheral */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Configure the source, destination address and the data length & clear flags*/
|
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DMA_ENABLE(hdma);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
status = HAL_BUSY;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start the DMA Transfer with interrupt enabled.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param DataLength The amount of data items to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Disable the peripheral */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Configure the source, destination address and the data length & clear flags*/
|
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the transfer complete interrupt */
|
||||
/* Enable the transfer Error interrupt */
|
||||
if(NULL != hdma->XferHalfCpltCallback )
|
||||
{
|
||||
/* Enable the Half transfer complete interrupt as well */
|
||||
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
||||
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
|
||||
}
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DMA_ENABLE(hdma);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Remain BUSY */
|
||||
status = HAL_BUSY;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Abort the DMA Transfer.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the DMA peripheral state */
|
||||
if(hdma->State != HAL_DMA_STATE_BUSY)
|
||||
{
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable DMA IT */
|
||||
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
||||
|
||||
/* Disable the channel */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Aborts the DMA Transfer in Interrupt mode.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if(HAL_DMA_STATE_BUSY != hdma->State)
|
||||
{
|
||||
/* no transfer ongoing */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable DMA IT */
|
||||
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
||||
|
||||
/* Disable the channel */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Call User Abort callback */
|
||||
if(hdma->XferAbortCallback != NULL)
|
||||
{
|
||||
hdma->XferAbortCallback(hdma);
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Polling for transfer complete.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param CompleteLevel Specifies the DMA level complete.
|
||||
* @param Timeout Timeout duration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
|
||||
{
|
||||
uint32_t temp;
|
||||
uint32_t tickstart;
|
||||
|
||||
if(HAL_DMA_STATE_BUSY != hdma->State)
|
||||
{
|
||||
/* no transfer ongoing */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
__HAL_UNLOCK(hdma);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Polling mode not supported in circular mode */
|
||||
if (0U != (hdma->Instance->CCR & DMA_CCR_CIRC))
|
||||
{
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Get the level transfer complete flag */
|
||||
if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
|
||||
{
|
||||
/* Transfer Complete flag */
|
||||
temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Half Transfer Complete flag */
|
||||
temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU);
|
||||
}
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while(0U == (hdma->DmaBaseAddress->ISR & temp))
|
||||
{
|
||||
if((0U != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1cU)))))
|
||||
{
|
||||
/* When a DMA transfer error occurs */
|
||||
/* A hardware clear of its EN bits is performed */
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State= HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check for the Timeout */
|
||||
if(Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
||||
{
|
||||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
|
||||
{
|
||||
/* Clear the transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1cU));
|
||||
|
||||
/* The selected Channelx EN bit is cleared (DMA is disabled and
|
||||
all transfers are complete) */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the half transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU));
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle DMA interrupt request.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
|
||||
uint32_t source_it = hdma->Instance->CCR;
|
||||
|
||||
/* Half Transfer Complete Interrupt management ******************************/
|
||||
if ((0U != (flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_HT)))
|
||||
{
|
||||
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
||||
{
|
||||
/* Disable the half transfer interrupt */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
||||
}
|
||||
/* Clear the half transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1cU);
|
||||
|
||||
/* DMA peripheral state is not updated in Half Transfer */
|
||||
/* but in Transfer Complete case */
|
||||
|
||||
if(hdma->XferHalfCpltCallback != NULL)
|
||||
{
|
||||
/* Half transfer callback */
|
||||
hdma->XferHalfCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
|
||||
/* Transfer Complete Interrupt management ***********************************/
|
||||
else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC)))
|
||||
{
|
||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
||||
{
|
||||
/* Disable the transfer complete and error interrupt */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
}
|
||||
/* Clear the transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1cU));
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if(hdma->XferCpltCallback != NULL)
|
||||
{
|
||||
/* Transfer complete callback */
|
||||
hdma->XferCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
|
||||
/* Transfer Error Interrupt management **************************************/
|
||||
else if ((0U != (flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TE)))
|
||||
{
|
||||
/* When a DMA transfer error occurs */
|
||||
/* A hardware clear of its EN bits is performed */
|
||||
/* Disable ALL DMA IT */
|
||||
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if (hdma->XferErrorCallback != NULL)
|
||||
{
|
||||
/* Transfer error callback */
|
||||
hdma->XferErrorCallback(hdma);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Nothing To Do */
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register callbacks
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param CallbackID User Callback identifier
|
||||
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
|
||||
* @param pCallback pointer to private callback function which has pointer to
|
||||
* a DMA_HandleTypeDef structure as parameter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DMA_XFER_CPLT_CB_ID:
|
||||
hdma->XferCpltCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
||||
hdma->XferHalfCpltCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ERROR_CB_ID:
|
||||
hdma->XferErrorCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ABORT_CB_ID:
|
||||
hdma->XferAbortCallback = pCallback;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister callbacks
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param CallbackID User Callback identifier
|
||||
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DMA_XFER_CPLT_CB_ID:
|
||||
hdma->XferCpltCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ERROR_CB_ID:
|
||||
hdma->XferErrorCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ABORT_CB_ID:
|
||||
hdma->XferAbortCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ALL_CB_ID:
|
||||
hdma->XferCpltCallback = NULL;
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
hdma->XferErrorCallback = NULL;
|
||||
hdma->XferAbortCallback = NULL;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @brief Peripheral State and Errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State and Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides functions allowing to
|
||||
(+) Check the DMA state
|
||||
(+) Get error code
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the DMA handle state.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Return DMA handle state */
|
||||
return hdma->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the DMA error code.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval DMA Error Code
|
||||
*/
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
return hdma->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Sets the DMA Transfer parameter.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param DataLength The amount of data items to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
|
||||
|
||||
/* Configure DMA Channel data length */
|
||||
hdma->Instance->CNDTR = DataLength;
|
||||
|
||||
/* Memory to Peripheral */
|
||||
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
||||
{
|
||||
/* Configure DMA Channel destination address */
|
||||
hdma->Instance->CPAR = DstAddress;
|
||||
|
||||
/* Configure DMA Channel source address */
|
||||
hdma->Instance->CMAR = SrcAddress;
|
||||
}
|
||||
/* Peripheral to Memory */
|
||||
else
|
||||
{
|
||||
/* Configure DMA Channel source address */
|
||||
hdma->Instance->CPAR = SrcAddress;
|
||||
|
||||
/* Configure DMA Channel destination address */
|
||||
hdma->Instance->CMAR = DstAddress;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
+547
@@ -0,0 +1,547 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l0xx_hal_exti.c
|
||||
* @author MCD Application Team
|
||||
* @brief EXTI HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### EXTI Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) Each Exti line can be configured within this driver.
|
||||
|
||||
(+) Exti line can be configured in 3 different modes
|
||||
(++) Interrupt
|
||||
(++) Event
|
||||
(++) Both of them
|
||||
|
||||
(+) Configurable Exti lines can be configured with 3 different triggers
|
||||
(++) Rising
|
||||
(++) Falling
|
||||
(++) Both of them
|
||||
|
||||
(+) When set in interrupt mode, configurable Exti lines have two different
|
||||
interrupts pending registers which allow to distinguish which transition
|
||||
occurs:
|
||||
(++) Rising edge pending interrupt
|
||||
(++) Falling
|
||||
|
||||
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
|
||||
be selected through multiplexer.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
|
||||
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
|
||||
(++) Choose the interrupt line number by setting "Line" member from
|
||||
EXTI_ConfigTypeDef structure.
|
||||
(++) Configure the interrupt and/or event mode using "Mode" member from
|
||||
EXTI_ConfigTypeDef structure.
|
||||
(++) For configurable lines, configure rising and/or falling trigger
|
||||
"Trigger" member from EXTI_ConfigTypeDef structure.
|
||||
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
|
||||
member from GPIO_InitTypeDef structure.
|
||||
|
||||
(#) Get current Exti configuration of a dedicated line using
|
||||
HAL_EXTI_GetConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
|
||||
|
||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
|
||||
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
|
||||
(++) Provide exiting handle as first parameter.
|
||||
(++) Provide which callback will be registered using one value from
|
||||
EXTI_CallbackIDTypeDef.
|
||||
(++) Provide callback function pointer.
|
||||
|
||||
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
|
||||
|
||||
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
|
||||
|
||||
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
|
||||
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
/** MISRA C:2012 deviation rule has been granted for following rule:
|
||||
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
|
||||
* of bounds [0,3] in following API :
|
||||
* HAL_EXTI_SetConfigLine
|
||||
* HAL_EXTI_GetConfigLine
|
||||
* HAL_EXTI_ClearConfigLine
|
||||
*/
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group1
|
||||
* @brief Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param pExtiConfig Pointer on EXTI configuration to be set.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
|
||||
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
|
||||
|
||||
/* Assign line number to handle */
|
||||
hexti->Line = pExtiConfig->Line;
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* Configure triggers for configurable lines */
|
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
|
||||
|
||||
/* Configure rising trigger */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
|
||||
{
|
||||
EXTI->RTSR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->RTSR &= ~maskline;
|
||||
}
|
||||
|
||||
/* Configure falling trigger */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
|
||||
{
|
||||
EXTI->FTSR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->FTSR &= ~maskline;
|
||||
}
|
||||
|
||||
|
||||
/* Configure gpio port selection in case of gpio exti line */
|
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
SYSCFG->EXTICR[linepos >> 2u] = regval;
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure interrupt mode : read current mode */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
|
||||
{
|
||||
EXTI->IMR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->IMR &= ~maskline;
|
||||
}
|
||||
|
||||
/* Configure event mode : read current mode */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
|
||||
{
|
||||
EXTI->EMR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->EMR &= ~maskline;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param pExtiConfig Pointer on structure to store Exti configuration.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
|
||||
/* Store handle line number to configuration structure */
|
||||
pExtiConfig->Line = hexti->Line;
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* 1] Get core mode : interrupt */
|
||||
|
||||
/* Check if selected line is enable */
|
||||
if ((EXTI->IMR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->Mode = EXTI_MODE_NONE;
|
||||
}
|
||||
|
||||
/* Get event mode */
|
||||
/* Check if selected line is enable */
|
||||
if ((EXTI->EMR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Mode |= EXTI_MODE_EVENT;
|
||||
}
|
||||
|
||||
/* Get default Trigger and GPIOSel configuration */
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
|
||||
pExtiConfig->GPIOSel = 0x00u;
|
||||
|
||||
/* 2] Get trigger for configurable lines : rising */
|
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
/* Check if configuration of selected line is enable */
|
||||
if ((EXTI->RTSR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
|
||||
}
|
||||
|
||||
/* Get falling configuration */
|
||||
/* Check if configuration of selected line is enable */
|
||||
if ((EXTI->FTSR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
|
||||
}
|
||||
|
||||
/* Get Gpio port selection for gpio lines */
|
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0;
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear whole configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if (hexti == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
|
||||
/* compute line mask */
|
||||
linepos = (hexti->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* 1] Clear interrupt mode */
|
||||
EXTI->IMR = (EXTI->IMR & ~maskline);
|
||||
|
||||
/* 2] Clear event mode */
|
||||
EXTI->EMR = (EXTI->EMR & ~maskline);
|
||||
|
||||
/* 3] Clear triggers in case of configurable lines */
|
||||
if ((hexti->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
EXTI->RTSR = (EXTI->RTSR & ~maskline);
|
||||
EXTI->FTSR = (EXTI->FTSR & ~maskline);
|
||||
|
||||
/* Get Gpio port selection for gpio lines */
|
||||
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
SYSCFG->EXTICR[linepos >> 2u] = regval;
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register callback for a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param CallbackID User callback identifier.
|
||||
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
|
||||
* @param pPendingCbfn function pointer to be stored as callback.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_EXTI_COMMON_CB_ID:
|
||||
hexti->PendingCallback = pPendingCbfn;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Store line number as handle private field.
|
||||
* @param hexti Exti handle.
|
||||
* @param ExtiLine Exti line number.
|
||||
* This parameter can be from 0 to @ref EXTI_LINE_NB.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(ExtiLine));
|
||||
|
||||
/* Check null pointer */
|
||||
if (hexti == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Store line number as handle private field */
|
||||
hexti->Line = ExtiLine;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group2
|
||||
* @brief EXTI IO functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Handle EXTI interrupt request.
|
||||
* @param hexti Exti handle.
|
||||
* @retval none.
|
||||
*/
|
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Get pending bit */
|
||||
regval = (EXTI->PR & maskline);
|
||||
if (regval != 0x00u)
|
||||
{
|
||||
/* Clear pending bit */
|
||||
EXTI->PR = maskline;
|
||||
|
||||
/* Call callback */
|
||||
if (hexti->PendingCallback != NULL)
|
||||
{
|
||||
hexti->PendingCallback();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt pending bit of a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @param Edge Specify which pending edge as to be checked.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||
* This parameter is kept for compatibility with other series.
|
||||
* @retval 1 if interrupt is pending else 0.
|
||||
*/
|
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (hexti->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* return 1 if bit is set else 0 */
|
||||
regval = ((EXTI->PR & maskline) >> linepos);
|
||||
return regval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear interrupt pending bit of a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @param Edge Specify which pending edge as to be clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||
* This parameter is kept for compatibility with other series.
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
{
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Clear Pending bit */
|
||||
EXTI->PR = maskline;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt for a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Generate Software interrupt */
|
||||
EXTI->SWIER = maskline;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
+762
@@ -0,0 +1,762 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l0xx_hal_flash.c
|
||||
* @author MCD Application Team
|
||||
* @brief FLASH HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the internal FLASH memory:
|
||||
* + Program operations functions
|
||||
* + Memory Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### FLASH peripheral features #####
|
||||
==============================================================================
|
||||
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
|
||||
to the Flash memory. It implements the erase and program Flash memory operations
|
||||
and the read and write protection mechanisms.
|
||||
|
||||
[..] The Flash memory interface accelerates code execution with a system of instruction
|
||||
prefetch.
|
||||
|
||||
[..] The FLASH main features are:
|
||||
(+) Flash memory read operations
|
||||
(+) Flash memory program/erase operations
|
||||
(+) Read / write protections
|
||||
(+) Prefetch on I-Code
|
||||
(+) Option Bytes programming
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver provides functions and macros to configure and program the FLASH
|
||||
memory of all STM32L0xx devices.
|
||||
|
||||
(#) FLASH Memory I/O Programming functions: this group includes all needed
|
||||
functions to erase and program the main memory:
|
||||
(++) Lock and Unlock the FLASH interface
|
||||
(++) Erase function: Erase page
|
||||
(++) Program functions: Fast Word and Half Page(should be
|
||||
executed from internal SRAM).
|
||||
|
||||
(#) DATA EEPROM Programming functions: this group includes all
|
||||
needed functions to erase and program the DATA EEPROM memory:
|
||||
(++) Lock and Unlock the DATA EEPROM interface.
|
||||
(++) Erase function: Erase Byte, erase HalfWord, erase Word, erase
|
||||
Double Word (should be executed from internal SRAM).
|
||||
(++) Program functions: Fast Program Byte, Fast Program Half-Word,
|
||||
FastProgramWord, Program Byte, Program Half-Word,
|
||||
Program Word and Program Double-Word (should be executed
|
||||
from internal SRAM).
|
||||
|
||||
(#) FLASH Option Bytes Programming functions: this group includes all needed
|
||||
functions to manage the Option Bytes:
|
||||
(++) Lock and Unlock the Option Bytes
|
||||
(++) Set/Reset the write protection
|
||||
(++) Set the Read protection Level
|
||||
(++) Program the user Option Bytes
|
||||
(++) Launch the Option Bytes loader
|
||||
(++) Set/Get the Read protection Level.
|
||||
(++) Set/Get the BOR level.
|
||||
(++) Get the Write protection.
|
||||
(++) Get the user option bytes.
|
||||
|
||||
(#) Interrupts and flags management functions : this group
|
||||
includes all needed functions to:
|
||||
(++) Handle FLASH interrupts
|
||||
(++) Wait for last FLASH operation according to its status
|
||||
(++) Get error flag status
|
||||
|
||||
(#) FLASH Interface configuration functions: this group includes
|
||||
the management of following features:
|
||||
(++) Enable/Disable the RUN PowerDown mode.
|
||||
(++) Enable/Disable the SLEEP PowerDown mode.
|
||||
|
||||
(#) FLASH Peripheral State methods: this group includes
|
||||
the management of following features:
|
||||
(++) Wait for the FLASH operation
|
||||
(++) Get the specific FLASH error flag
|
||||
|
||||
[..] In addition to these function, this driver includes a set of macros allowing
|
||||
to handle the following operations:
|
||||
|
||||
(+) Set/Get the latency
|
||||
(+) Enable/Disable the prefetch buffer
|
||||
(+) Enable/Disable the preread buffer
|
||||
(+) Enable/Disable the Flash power-down
|
||||
(+) Enable/Disable the FLASH interrupts
|
||||
(+) Monitor the FLASH flags status
|
||||
|
||||
##### Programming operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the FLASH
|
||||
program operations.
|
||||
|
||||
[..] The FLASH Memory Programming functions, includes the following functions:
|
||||
(+) HAL_FLASH_Unlock(void);
|
||||
(+) HAL_FLASH_Lock(void);
|
||||
(+) HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
|
||||
(+) HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
|
||||
|
||||
[..] Any operation of erase or program should follow these steps:
|
||||
(#) Call the HAL_FLASH_Unlock() function to enable the flash control register and
|
||||
program memory access.
|
||||
(#) Call the desired function to erase page or program data.
|
||||
(#) Call the HAL_FLASH_Lock() to disable the flash program memory access
|
||||
(recommended to protect the FLASH memory against possible unwanted operation).
|
||||
|
||||
##### Option Bytes Programming functions #####
|
||||
==============================================================================
|
||||
|
||||
[..] The FLASH_Option Bytes Programming_functions, includes the following functions:
|
||||
(+) HAL_FLASH_OB_Unlock(void);
|
||||
(+) HAL_FLASH_OB_Lock(void);
|
||||
(+) HAL_FLASH_OB_Launch(void);
|
||||
(+) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
(+) HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
|
||||
[..] Any operation of erase or program should follow these steps:
|
||||
(#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control
|
||||
register access.
|
||||
(#) Call the following functions to program the desired option bytes.
|
||||
(++) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
(#) Once all needed option bytes to be programmed are correctly written, call the
|
||||
HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process.
|
||||
(#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended
|
||||
to protect the option Bytes against possible unwanted operations).
|
||||
|
||||
[..] Proprietary code Read Out Protection (PcROP):
|
||||
(#) The PcROP sector is selected by using the same option bytes as the Write
|
||||
protection. As a result, these 2 options are exclusive each other.
|
||||
(#) To activate PCROP mode for Flash sectors(s), you need to follow the sequence below:
|
||||
(++) Use this function HAL_FLASHEx_AdvOBProgram with PCROPState = OB_PCROP_STATE_ENABLE.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/** @defgroup FLASH FLASH
|
||||
* @brief FLASH HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Constants FLASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro ---------------------------- ---------------------------------*/
|
||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Variables FLASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
/* Variables used for Erase pages under interruption*/
|
||||
FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Functions FLASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
static void FLASH_SetErrorCode(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
|
||||
* @brief Programming operation functions
|
||||
*
|
||||
@verbatim
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Program word at a specified address
|
||||
* @note To correctly run this function, the HAL_FLASH_Unlock() function
|
||||
* must be called before.
|
||||
* Call the HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation).
|
||||
*
|
||||
* @param TypeProgram Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address Specifie the address to be programmed.
|
||||
* @param Data Specifie the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/*Program word (32-bit) at a specified address.*/
|
||||
*(__IO uint32_t *)Address = Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program word at a specified address with interrupt enabled.
|
||||
*
|
||||
* @param TypeProgram Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address Specifie the address to be programmed.
|
||||
* @param Data Specifie the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Enable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
|
||||
|
||||
pFlash.Address = Address;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
/* Program word (32-bit) at a specified address. */
|
||||
*(__IO uint32_t *)Address = Data;
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles FLASH interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASH_IRQHandler(void)
|
||||
{
|
||||
uint32_t addresstmp = 0;
|
||||
|
||||
/* Check FLASH operation error flags */
|
||||
|
||||
/* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
|
||||
* (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
|
||||
* as expected. If the user run an application using the first
|
||||
* cut of the STM32L031xx device or the first cut of the STM32L041xx
|
||||
* device, the check on the FLASH_FLAG_OPTVERR bit should be ignored.
|
||||
*
|
||||
* Note :The revId of the device can be retrieved via the HAL_GetREVID()
|
||||
* function.
|
||||
*
|
||||
*/
|
||||
|
||||
if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) )
|
||||
{
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
|
||||
{
|
||||
/* Return the faulty sector */
|
||||
addresstmp = pFlash.Page;
|
||||
pFlash.Page = 0xFFFFFFFFU;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Return the faulty address */
|
||||
addresstmp = pFlash.Address;
|
||||
}
|
||||
/* Save the Error code */
|
||||
FLASH_SetErrorCode();
|
||||
|
||||
/* FLASH error interrupt user callback */
|
||||
HAL_FLASH_OperationErrorCallback(addresstmp);
|
||||
|
||||
/* Stop the procedure ongoing */
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
|
||||
/* Process can continue only if no error detected */
|
||||
if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
|
||||
{
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
|
||||
{
|
||||
/* Nb of pages to erased can be decreased */
|
||||
pFlash.NbPagesToErase--;
|
||||
|
||||
/* Check if there are still pages to erase */
|
||||
if(pFlash.NbPagesToErase != 0U)
|
||||
{
|
||||
addresstmp = pFlash.Page;
|
||||
/*Indicate user which sector has been erased */
|
||||
HAL_FLASH_EndOfOperationCallback(addresstmp);
|
||||
|
||||
/*Increment sector number*/
|
||||
addresstmp = pFlash.Page + FLASH_PAGE_SIZE;
|
||||
pFlash.Page = addresstmp;
|
||||
|
||||
/* If the erase operation is completed, disable the ERASE Bit */
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
|
||||
|
||||
FLASH_PageErase(addresstmp);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No more pages to Erase, user callback can be called. */
|
||||
/* Reset Sector and stop Erase pages procedure */
|
||||
pFlash.Page = addresstmp = 0xFFFFFFFFU;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(addresstmp);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If the program operation is completed, disable the PROG Bit */
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
||||
|
||||
/* Program ended. Return the selected address */
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
|
||||
|
||||
/* Reset Address and stop Program procedure */
|
||||
pFlash.Address = 0xFFFFFFFFU;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
|
||||
{
|
||||
/* Operation is completed, disable the PROG and ERASE */
|
||||
CLEAR_BIT(FLASH->PECR, (FLASH_PECR_ERASE | FLASH_PECR_PROG));
|
||||
|
||||
/* Disable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH end of operation interrupt callback
|
||||
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
|
||||
* - Pages Erase: Address of the page which has been erased
|
||||
* (if 0xFFFFFFFF, it means that all the selected pages have been erased)
|
||||
* - Program: Address which was selected for data program
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(ReturnValue);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH operation error interrupt callback
|
||||
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
|
||||
* - Pages Erase: Address of the page which returned an error
|
||||
* - Program: Address which was selected for data program
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(ReturnValue);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
memory operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH control register access
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
|
||||
{
|
||||
uint32_t primask_bit;
|
||||
|
||||
/* Unlocking FLASH_PECR register access*/
|
||||
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
|
||||
{
|
||||
/* Disable interrupts to avoid any interruption during unlock sequence */
|
||||
primask_bit = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
|
||||
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1);
|
||||
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2);
|
||||
|
||||
/* Re-enable the interrupts: restore previous priority mask */
|
||||
__set_PRIMASK(primask_bit);
|
||||
|
||||
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK))
|
||||
{
|
||||
/* Disable interrupts to avoid any interruption during unlock sequence */
|
||||
primask_bit = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
|
||||
/* Unlocking the program memory access */
|
||||
WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY1);
|
||||
WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY2);
|
||||
|
||||
/* Re-enable the interrupts: restore previous priority mask */
|
||||
__set_PRIMASK(primask_bit);
|
||||
|
||||
if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks the FLASH control register access
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void)
|
||||
{
|
||||
/* Set the PRGLOCK Bit to lock the FLASH Registers access */
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK);
|
||||
|
||||
/* Set the PELOCK Bit to lock the PECR Register access */
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PELOCK);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH Option Control Registers access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
|
||||
{
|
||||
uint32_t primask_bit;
|
||||
|
||||
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK))
|
||||
{
|
||||
/* Disable interrupts to avoid any interruption during unlock sequence */
|
||||
primask_bit = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
|
||||
/* Unlocking FLASH_PECR register access*/
|
||||
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
|
||||
{
|
||||
/* Unlocking FLASH_PECR register access*/
|
||||
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1);
|
||||
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2);
|
||||
}
|
||||
|
||||
/* Unlocking the option bytes block access */
|
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
|
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
|
||||
|
||||
/* Re-enable the interrupts: restore previous priority mask */
|
||||
__set_PRIMASK(primask_bit);
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Lock the FLASH Option Control Registers access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
|
||||
{
|
||||
/* Set the OPTLOCK Bit to lock the option bytes block access */
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_OPTLOCK);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Launch the option byte loading.
|
||||
* @note This function will reset automatically the MCU.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
|
||||
{
|
||||
/* Set the OBL_Launch bit to launch the option byte loading */
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_OBL_LAUNCH);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
|
||||
* @brief Peripheral errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permit to get in run-time errors of the FLASH peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get the specific FLASH error flag.
|
||||
* @retval FLASH_ErrorCode The returned value can be:
|
||||
* @ref FLASH_Error_Codes
|
||||
*/
|
||||
uint32_t HAL_FLASH_GetError(void)
|
||||
{
|
||||
return pFlash.ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Wait for a FLASH operation to complete.
|
||||
* @param Timeout maximum flash operation timeout
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
||||
{
|
||||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
||||
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
||||
flag will be set */
|
||||
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
|
||||
{
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
}
|
||||
|
||||
if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) )
|
||||
{
|
||||
/*Save the error code*/
|
||||
|
||||
/* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
|
||||
* (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
|
||||
* as expected. If the user run an application using the first
|
||||
* cut of the STM32L031xx device or the first cut of the STM32L041xx
|
||||
* device, this error should be ignored. The revId of the device
|
||||
* can be retrieved via the HAL_GetREVID() function.
|
||||
*
|
||||
*/
|
||||
FLASH_SetErrorCode();
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* There is no error flag set */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set the specific FLASH error flag.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_SetErrorCode(void)
|
||||
{
|
||||
uint32_t flags = 0;
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
|
||||
flags |= FLASH_FLAG_WRPERR;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
|
||||
flags |= FLASH_FLAG_PGAERR;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZE;
|
||||
flags |= FLASH_FLAG_SIZERR;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
|
||||
{
|
||||
/* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
|
||||
* (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
|
||||
* as expected. If the user run an application using the first
|
||||
* cut of the STM32L031xx device or the first cut of the STM32L041xx
|
||||
* device, this error should be ignored. The revId of the device
|
||||
* can be retrieved via the HAL_GetREVID() function.
|
||||
*
|
||||
*/
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
|
||||
flags |= FLASH_FLAG_OPTVERR;
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
|
||||
flags |= FLASH_FLAG_RDERR;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_FWWERR;
|
||||
flags |= HAL_FLASH_ERROR_FWWERR;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_NOTZERO;
|
||||
flags |= FLASH_FLAG_NOTZEROERR;
|
||||
}
|
||||
|
||||
/* Clear FLASH error pending bits */
|
||||
__HAL_FLASH_CLEAR_FLAG(flags);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
+1263
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,518 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l0xx_hal_flash_ramfunc.c
|
||||
* @author MCD Application Team
|
||||
* @brief FLASH RAMFUNC driver.
|
||||
* This file provides a Flash firmware functions which should be
|
||||
* executed from internal SRAM
|
||||
*
|
||||
* @verbatim
|
||||
|
||||
*** ARM Compiler ***
|
||||
--------------------
|
||||
[..] RAM functions are defined using the toolchain options.
|
||||
Functions that are be executed in RAM should reside in a separate
|
||||
source module. Using the 'Options for File' dialog you can simply change
|
||||
the 'Code / Const' area of a module to a memory space in physical RAM.
|
||||
Available memory areas are declared in the 'Target' tab of the
|
||||
Options for Target' dialog.
|
||||
|
||||
*** ICCARM Compiler ***
|
||||
-----------------------
|
||||
[..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
|
||||
*** GNU Compiler ***
|
||||
--------------------
|
||||
[..] RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".RamFunc")))".
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup FLASH_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
extern FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
|
||||
* @brief FLASH functions executed from RAM
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup FLASH_RAMFUNC_Private_Functions FLASH RAM Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout);
|
||||
static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAM Exported Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### ramfunc functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions that should be executed from RAM
|
||||
transfers.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the power down mode during RUN mode.
|
||||
* @note This function can be used only when the user code is running from Internal SRAM.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void)
|
||||
{
|
||||
/* Enable the Power Down in Run mode*/
|
||||
__HAL_FLASH_POWER_DOWN_ENABLE();
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the power down mode during RUN mode.
|
||||
* @note This function can be used only when the user code is running from Internal SRAM.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void)
|
||||
{
|
||||
/* Disable the Power Down in Run mode*/
|
||||
__HAL_FLASH_POWER_DOWN_DISABLE();
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group2 Programming and erasing operation functions
|
||||
*
|
||||
@verbatim
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(FLASH_PECR_PARALLBANK)
|
||||
/**
|
||||
* @brief Erases a specified 2 pages in program memory in parallel.
|
||||
* @note This function can be used only for STM32L07xxx/STM32L08xxx devices.
|
||||
* To correctly run this function, the @ref HAL_FLASH_Unlock() function
|
||||
* must be called before.
|
||||
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation).
|
||||
* @param Page_Address1: The page address in program memory to be erased in
|
||||
* the first Bank (BANK1). This parameter should be between FLASH_BASE
|
||||
* and FLASH_BANK1_END.
|
||||
* @param Page_Address2: The page address in program memory to be erased in
|
||||
* the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE
|
||||
* and FLASH_BANK2_END.
|
||||
* @note A Page is erased in the Program memory only if the address to load
|
||||
* is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes).
|
||||
* @retval HAL status
|
||||
*/
|
||||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Proceed to erase the page */
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
||||
|
||||
/* Write 00000000h to the first word of the first program page to erase */
|
||||
*(__IO uint32_t *)Page_Address1 = 0x00000000U;
|
||||
/* Write 00000000h to the first word of the second program page to erase */
|
||||
*(__IO uint32_t *)Page_Address2 = 0x00000000U;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
|
||||
}
|
||||
/* Return the Erase Status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program 2 half pages in program memory in parallel (half page size is 16 Words).
|
||||
* @note This function can be used only for STM32L07xxx/STM32L08xxx devices.
|
||||
* @param Address1: specifies the first address to be written in the first bank
|
||||
* (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE).
|
||||
* @param pBuffer1: pointer to the buffer containing the data to be written
|
||||
* to the first half page in the first bank.
|
||||
* @param Address2: specifies the second address to be written in the second bank
|
||||
* (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE).
|
||||
* @param pBuffer2: pointer to the buffer containing the data to be written
|
||||
* to the second half page in the second bank.
|
||||
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
|
||||
* must be called before.
|
||||
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation).
|
||||
* @note Half page write is possible only from SRAM.
|
||||
* @note A half page is written to the program memory only if the first
|
||||
* address to load is the start address of a half page (multiple of 64
|
||||
* bytes) and the 15 remaining words to load are in the same half page.
|
||||
* @note During the Program memory half page write all read operations are
|
||||
* forbidden (this includes DMA read operations and debugger read
|
||||
* operations such as breakpoints, periodic updates, etc.).
|
||||
* @note If a PGAERR is set during a Program memory half page write, the
|
||||
* complete write operation is aborted. Software should then reset the
|
||||
* FPRG and PROG/DATA bits and restart the write operation from the
|
||||
* beginning.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
|
||||
{
|
||||
uint32_t count = 0U;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Proceed to program the new half page */
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Disable all IRQs */
|
||||
__disable_irq();
|
||||
|
||||
/* Write the first half page directly with 16 different words */
|
||||
while(count < 16U)
|
||||
{
|
||||
/* Address1 doesn't need to be increased */
|
||||
*(__IO uint32_t*) Address1 = *pBuffer1;
|
||||
pBuffer1++;
|
||||
count ++;
|
||||
}
|
||||
|
||||
/* Write the second half page directly with 16 different words */
|
||||
count = 0U;
|
||||
while(count < 16U)
|
||||
{
|
||||
/* Address2 doesn't need to be increased */
|
||||
*(__IO uint32_t*) Address2 = *pBuffer2;
|
||||
pBuffer2++;
|
||||
count ++;
|
||||
}
|
||||
|
||||
/* Enable IRQs */
|
||||
__enable_irq();
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
|
||||
/* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
|
||||
}
|
||||
|
||||
/* Return the Write Status */
|
||||
return status;
|
||||
}
|
||||
#endif /* FLASH_PECR_PARALLBANK */
|
||||
|
||||
/**
|
||||
* @brief Program a half page in program memory.
|
||||
* @param Address specifies the address to be written.
|
||||
* @param pBuffer pointer to the buffer containing the data to be written to
|
||||
* the half page.
|
||||
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
|
||||
* must be called before.
|
||||
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation)
|
||||
* @note Half page write is possible only from SRAM.
|
||||
* @note A half page is written to the program memory only if the first
|
||||
* address to load is the start address of a half page (multiple of 64
|
||||
* bytes) and the 15 remaining words to load are in the same half page.
|
||||
* @note During the Program memory half page write all read operations are
|
||||
* forbidden (this includes DMA read operations and debugger read
|
||||
* operations such as breakpoints, periodic updates, etc.).
|
||||
* @note If a PGAERR is set during a Program memory half page write, the
|
||||
* complete write operation is aborted. Software should then reset the
|
||||
* FPRG and PROG/DATA bits and restart the write operation from the
|
||||
* beginning.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
|
||||
{
|
||||
uint32_t count = 0U;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Proceed to program the new half page */
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
||||
|
||||
/* Disable all IRQs */
|
||||
__disable_irq();
|
||||
|
||||
/* Write one half page directly with 16 different words */
|
||||
while(count < 16U)
|
||||
{
|
||||
/* Address doesn't need to be increased */
|
||||
*(__IO uint32_t*) Address = *pBuffer;
|
||||
pBuffer++;
|
||||
count ++;
|
||||
}
|
||||
|
||||
/* Enable IRQs */
|
||||
__enable_irq();
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the write operation is completed, disable the PROG and FPRG bits */
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
|
||||
}
|
||||
|
||||
/* Return the Write Status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group3 Peripheral errors functions
|
||||
* @brief Peripheral errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permit to get in run-time errors of the FLASH peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get the specific FLASH errors flag.
|
||||
* @param Error pointer is the error value. It can be a mixed of:
|
||||
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
|
||||
* @arg @ref HAL_FLASH_ERROR_SIZE FLASH Programming Parallelism error flag
|
||||
* @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming Alignment error flag
|
||||
* @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protected error flag
|
||||
* @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option valid error flag
|
||||
* @arg @ref HAL_FLASH_ERROR_FWWERR FLASH Write or Erase operation aborted
|
||||
* @arg @ref HAL_FLASH_ERROR_NOTZERO FLASH Write operation is done in a not-erased region
|
||||
* @retval HAL Status
|
||||
*/
|
||||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_GetError(uint32_t * Error)
|
||||
{
|
||||
*Error = pFlash.ErrorCode;
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_RAMFUNC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the specific FLASH error flag.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void)
|
||||
{
|
||||
uint32_t flags = 0;
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
|
||||
flags |= FLASH_FLAG_WRPERR;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
|
||||
flags |= FLASH_FLAG_PGAERR;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZE;
|
||||
flags |= FLASH_FLAG_SIZERR;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
|
||||
{
|
||||
/* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
|
||||
* (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
|
||||
* as expected. If the user run an application using the first
|
||||
* cut of the STM32L031xx device or the first cut of the STM32L041xx
|
||||
* device, this error should be ignored. The revId of the device
|
||||
* can be retrieved via the HAL_GetREVID() function.
|
||||
*
|
||||
*/
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
|
||||
flags |= FLASH_FLAG_OPTVERR;
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
|
||||
flags |= FLASH_FLAG_RDERR;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_FWWERR;
|
||||
flags |= HAL_FLASH_ERROR_FWWERR;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_NOTZERO;
|
||||
flags |= FLASH_FLAG_NOTZEROERR;
|
||||
}
|
||||
|
||||
/* Clear FLASH error pending bits */
|
||||
__HAL_FLASH_CLEAR_FLAG(flags);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait for a FLASH operation to complete.
|
||||
* @param Timeout maximum flash operationtimeout
|
||||
* @retval HAL status
|
||||
*/
|
||||
static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout)
|
||||
{
|
||||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
||||
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
||||
flag will be set */
|
||||
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00U))
|
||||
{
|
||||
Timeout--;
|
||||
}
|
||||
|
||||
if(Timeout == 0x00U)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
}
|
||||
|
||||
if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) )
|
||||
{
|
||||
/*Save the error code*/
|
||||
|
||||
/* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
|
||||
* (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
|
||||
* as expected. If the user run an application using the first
|
||||
* cut of the STM32L031xx device or the first cut of the STM32L041xx
|
||||
* device, this error should be ignored. The revId of the device
|
||||
* can be retrieved via the HAL_GetREVID() function.
|
||||
*
|
||||
*/
|
||||
FLASHRAM_SetErrorCode();
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* There is no error flag set */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
+531
@@ -0,0 +1,531 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l0xx_hal_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @brief GPIO HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### GPIO Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
|
||||
configured by software in several modes:
|
||||
(++) Input mode
|
||||
(++) Analog mode
|
||||
(++) Output mode
|
||||
(++) Alternate function mode
|
||||
(++) External interrupt/event lines
|
||||
|
||||
(+) During and just after reset, the alternate functions and external interrupt
|
||||
lines are not active and the I/O ports are configured in input floating mode.
|
||||
|
||||
(+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
|
||||
activated or not.
|
||||
|
||||
(+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
|
||||
type and the IO speed can be selected depending on the VDD value.
|
||||
|
||||
(+) The microcontroller IO pins are connected to onboard peripherals/modules through a
|
||||
multiplexer that allows only one peripheral alternate function (AF) connected
|
||||
to an IO pin at a time. In this way, there can be no conflict between peripherals
|
||||
sharing the same IO pin.
|
||||
|
||||
(+) All ports have external interrupt/event capability. To use external interrupt
|
||||
lines, the port must be configured in input mode. All available GPIO pins are
|
||||
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
|
||||
|
||||
(+) The external interrupt/event controller consists of up to 28 edge detectors
|
||||
(16 lines are connected to GPIO) for generating event/interrupt requests (each
|
||||
input line can be independently configured to select the type (interrupt or event)
|
||||
and the corresponding trigger event (rising or falling or both). Each line can
|
||||
also be masked independently.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO IOPORT clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
|
||||
|
||||
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
|
||||
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
|
||||
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
|
||||
structure.
|
||||
(++) In case of Output or alternate function mode selection: the speed is
|
||||
configured through "Speed" member from GPIO_InitTypeDef structure.
|
||||
(++) In alternate mode is selection, the alternate function connected to the IO
|
||||
is configured through "Alternate" member from GPIO_InitTypeDef structure.
|
||||
(++) Analog mode is required when a pin is to be used as ADC channel
|
||||
or DAC output.
|
||||
(++) In case of external interrupt/event selection the "Mode" member from
|
||||
GPIO_InitTypeDef structure select the type (interrupt or event) and
|
||||
the corresponding trigger event (rising or falling or both).
|
||||
|
||||
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
|
||||
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
|
||||
HAL_NVIC_EnableIRQ().
|
||||
|
||||
(#) HAL_GPIO_DeInit allows to set register values to their reset value. This function
|
||||
is also to be used when unconfiguring pin which was used as an external interrupt
|
||||
or in event mode. That is the only way to reset the corresponding bit in
|
||||
EXTI & SYSCFG registers.
|
||||
|
||||
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
|
||||
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
|
||||
|
||||
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
|
||||
|
||||
(#) During and just after reset, the alternate functions are not
|
||||
active and the GPIO pins are configured in input floating mode (except JTAG
|
||||
pins).
|
||||
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
|
||||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
|
||||
priority over the GPIO function.
|
||||
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
|
||||
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
|
||||
The HSE has priority over the GPIO function.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @brief GPIO HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_Private
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NUMBER (16U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @addtogroup GPIO_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group1
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
|
||||
* @param GPIOx where x can be (A..E and H) to select the GPIO peripheral for STM32L0XX family devices.
|
||||
* Note that GPIOE is not available on all devices.
|
||||
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
||||
* the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||
{
|
||||
uint32_t position = 0x00U;
|
||||
uint32_t iocurrent = 0x00U;
|
||||
uint32_t temp = 0x00U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
||||
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, (GPIO_Init->Pin)));
|
||||
|
||||
/* Configure the port pins */
|
||||
while (((GPIO_Init->Pin) >> position) != 0)
|
||||
{
|
||||
/* Get the IO position */
|
||||
iocurrent = (GPIO_Init->Pin) & (1U << position);
|
||||
|
||||
if (iocurrent)
|
||||
{
|
||||
/*--------------------- GPIO Mode Configuration ------------------------*/
|
||||
/* In case of Output or Alternate function mode selection */
|
||||
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
|
||||
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
||||
{
|
||||
/* Check the Speed parameter */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
||||
/* Configure the IO Speed */
|
||||
temp = GPIOx->OSPEEDR;
|
||||
temp &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U));
|
||||
temp |= (GPIO_Init->Speed << (position * 2U));
|
||||
GPIOx->OSPEEDR = temp;
|
||||
|
||||
/* Configure the IO Output Type */
|
||||
temp = GPIOx->OTYPER;
|
||||
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
||||
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
||||
GPIOx->OTYPER = temp;
|
||||
}
|
||||
|
||||
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
||||
{
|
||||
/* Check the Pull parameter */
|
||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||||
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||
temp = GPIOx->PUPDR;
|
||||
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
||||
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
||||
GPIOx->PUPDR = temp;
|
||||
}
|
||||
|
||||
/* In case of Alternate function mode selection */
|
||||
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
||||
{
|
||||
/* Check the Alternate function parameters */
|
||||
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
||||
|
||||
/* Configure Alternate function mapped with the current IO */
|
||||
temp = GPIOx->AFR[position >> 3U];
|
||||
temp &= ~(0xFUL << ((uint32_t)(position & 0x07UL) * 4U));
|
||||
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U));
|
||||
GPIOx->AFR[position >> 3U] = temp;
|
||||
}
|
||||
|
||||
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
||||
temp = GPIOx->MODER;
|
||||
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
|
||||
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
|
||||
GPIOx->MODER = temp;
|
||||
|
||||
/*--------------------- EXTI Mode Configuration ------------------------*/
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
|
||||
{
|
||||
/* Enable SYSCFG Clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
temp = SYSCFG->EXTICR[position >> 2U];
|
||||
CLEAR_BIT(temp, (0x0FUL) << (4U * (position & 0x03U)));
|
||||
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03U)));
|
||||
SYSCFG->EXTICR[position >> 2U] = temp;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
temp = EXTI->RTSR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->RTSR = temp;
|
||||
|
||||
temp = EXTI->FTSR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->FTSR = temp;
|
||||
|
||||
temp = EXTI->EMR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->EMR = temp;
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
temp = EXTI->IMR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->IMR = temp;
|
||||
}
|
||||
}
|
||||
position++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
|
||||
* @param GPIOx where x can be (A..E and H) to select the GPIO peripheral for STM32L0XX family devices.
|
||||
* Note that GPIOE is not available on all devices.
|
||||
* @param GPIO_Pin specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* All port bits are not necessarily available on all GPIOs.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
{
|
||||
uint32_t position = 0x00U;
|
||||
uint32_t iocurrent = 0x00U;
|
||||
uint32_t tmp = 0x00U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin));
|
||||
|
||||
/* Configure the port pins */
|
||||
while ((GPIO_Pin >> position) != 0)
|
||||
{
|
||||
/* Get the IO position */
|
||||
iocurrent = (GPIO_Pin) & (1U << position);
|
||||
|
||||
if (iocurrent)
|
||||
{
|
||||
/*------------------------- EXTI Mode Configuration --------------------*/
|
||||
/* Clear the External Interrupt or Event for the current IO */
|
||||
|
||||
tmp = SYSCFG->EXTICR[position >> 2U];
|
||||
tmp &= ((0x0FUL) << (4U * (position & 0x03U)));
|
||||
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
|
||||
{
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMR &= ~((uint32_t)iocurrent);
|
||||
EXTI->EMR &= ~((uint32_t)iocurrent);
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->FTSR &= ~((uint32_t)iocurrent);
|
||||
EXTI->RTSR &= ~((uint32_t)iocurrent);
|
||||
|
||||
tmp = (0x0FUL) << (4U * (position & 0x03U));
|
||||
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
|
||||
}
|
||||
|
||||
/*------------------------- GPIO Mode Configuration --------------------*/
|
||||
/* Configure IO Direction in Analog Mode (reset state) */
|
||||
GPIOx->MODER |= (GPIO_MODE_ANALOG << (position * 2U));
|
||||
|
||||
/* Configure the default Alternate Function in current IO */
|
||||
GPIOx->AFR[position >> 3U] &= ~(0xFUL << ((uint32_t)(position & 0x07UL) * 4U));
|
||||
|
||||
/* Deactivate the Pull-up oand Pull-down resistor for the current IO */
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
||||
|
||||
/* Configure the default value IO Output Type */
|
||||
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position);
|
||||
|
||||
/* Configure the default value for IO Speed */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U));
|
||||
}
|
||||
position++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group2
|
||||
* @brief GPIO Read and Write
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family devices.
|
||||
* Note that GPIOE is not available on all devices.
|
||||
* @param GPIO_Pin specifies the port bit to read.
|
||||
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
||||
* All port bits are not necessarily available on all GPIOs.
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
GPIO_PinState bitstatus;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
||||
{
|
||||
bitstatus = GPIO_PIN_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = GPIO_PIN_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
*
|
||||
* @note This function uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
*
|
||||
* @param GPIOx where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family devices.
|
||||
* Note that GPIOE is not available on all devices.
|
||||
* @param GPIO_Pin specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* All port bits are not necessarily available on all GPIOs.
|
||||
* @param PinState specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the GPIO_PinState enum values:
|
||||
* GPIO_PIN_RESET: to clear the port pin
|
||||
* GPIO_PIN_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin));
|
||||
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
||||
|
||||
if (PinState != GPIO_PIN_RESET)
|
||||
{
|
||||
GPIOx->BSRR = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BRR = GPIO_Pin ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the specified GPIO pins.
|
||||
* @param GPIOx Where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family devices.
|
||||
* Note that GPIOE is not available on all devices.
|
||||
* All port bits are not necessarily available on all GPIOs.
|
||||
* @param GPIO_Pin Specifies the pins to be toggled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint32_t odr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin));
|
||||
|
||||
/* get current Output Data Register value */
|
||||
odr = GPIOx->ODR;
|
||||
|
||||
/* Set selected pins that were at low level, and reset ones that were high */
|
||||
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* @note The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @param GPIOx where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family.
|
||||
* Note that GPIOE is not available on all devices.
|
||||
* @param GPIO_Pin specifies the port bit to be locked.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* All port bits are not necessarily available on all GPIOs.
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
__IO uint32_t tmp = GPIO_LCKR_LCKK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin));
|
||||
|
||||
/* Apply lock key write sequence */
|
||||
tmp |= GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK register. This read is mandatory to complete key lock sequence */
|
||||
tmp = GPIOx->LCKR;
|
||||
|
||||
/* read again in order to confirm lock is active */
|
||||
if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
|
||||
{
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @brief This function handles EXTI interrupt request.
|
||||
* @param GPIO_Pin Specifies the pins connected to the EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* EXTI line interrupt detected */
|
||||
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
|
||||
{
|
||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
||||
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI line detection callbacks.
|
||||
* @param GPIO_Pin Specifies the pins connected to the EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(GPIO_Pin);
|
||||
|
||||
/* NOTE: This function Should not be modified, when the callback is needed,
|
||||
the HAL_GPIO_EXTI_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
+7278
File diff suppressed because it is too large
Load Diff
+366
@@ -0,0 +1,366 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l0xx_hal_i2c_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief I2C Extended HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of I2C Extended peripheral:
|
||||
* + Filter Mode Functions
|
||||
* + WakeUp Mode Functions
|
||||
* + FastModePlus Functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### I2C peripheral Extended features #####
|
||||
==============================================================================
|
||||
|
||||
[..] Comparing to other previous devices, the I2C interface for STM32L0xx
|
||||
devices contains the following additional features
|
||||
|
||||
(+) Possibility to disable or enable Analog Noise Filter
|
||||
(+) Use of a configured Digital Noise Filter
|
||||
(+) Disable or enable wakeup from Stop mode(s)
|
||||
(+) Disable or enable Fast Mode Plus
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] This driver provides functions to configure Noise Filter and Wake Up Feature
|
||||
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
|
||||
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
|
||||
(#) Configure the enable or disable of I2C Wake Up Mode using the functions :
|
||||
(++) HAL_I2CEx_EnableWakeUp()
|
||||
(++) HAL_I2CEx_DisableWakeUp()
|
||||
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
|
||||
(++) HAL_I2CEx_EnableFastModePlus()
|
||||
(++) HAL_I2CEx_DisableFastModePlus()
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx I2CEx
|
||||
* @brief I2C Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
|
||||
* @brief Filter Mode Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Filter Mode Functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Noise Filters
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure I2C Analog noise filter.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param AnalogFilter New state of the Analog filter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Reset I2Cx ANOFF bit */
|
||||
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
|
||||
|
||||
/* Set analog filter bit*/
|
||||
hi2c->Instance->CR1 |= AnalogFilter;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure I2C Digital noise filter.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
||||
{
|
||||
uint32_t tmpreg;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Get the old register value */
|
||||
tmpreg = hi2c->Instance->CR1;
|
||||
|
||||
/* Reset I2Cx DNF bits [11:8] */
|
||||
tmpreg &= ~(I2C_CR1_DNF);
|
||||
|
||||
/* Set I2Cx DNF coefficient */
|
||||
tmpreg |= DigitalFilter << 8U;
|
||||
|
||||
/* Store the new register value */
|
||||
hi2c->Instance->CR1 = tmpreg;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
|
||||
* @brief WakeUp Mode Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### WakeUp Mode Functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Wake Up Feature
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable I2C wakeup from Stop mode(s).
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Enable wakeup from stop mode */
|
||||
hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable I2C wakeup from Stop mode(s).
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Enable wakeup from stop mode */
|
||||
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if (defined(SYSCFG_CFGR2_I2C_PB6_FMP) || defined(SYSCFG_CFGR2_I2C_PB7_FMP)) || (defined(SYSCFG_CFGR2_I2C_PB8_FMP) || defined(SYSCFG_CFGR2_I2C_PB9_FMP)) || (defined(SYSCFG_CFGR2_I2C1_FMP)) || defined(SYSCFG_CFGR2_I2C2_FMP) || defined(SYSCFG_CFGR2_I2C3_FMP)
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
|
||||
* @brief Fast Mode Plus Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Fast Mode Plus Functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Fast Mode Plus
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the I2C fast mode plus driving capability.
|
||||
* @param ConfigFastModePlus Selects the pin.
|
||||
* This parameter can be one of the @ref I2CEx_FastModePlus values
|
||||
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
|
||||
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
|
||||
* on each one of the following pins PB6, PB7, PB8 and PB9.
|
||||
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
|
||||
* can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
|
||||
* @note For all I2C2 pins fast mode plus driving capability can be enabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
|
||||
* @note For all I2C3 pins fast mode plus driving capability can be enabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
|
||||
|
||||
/* Enable SYSCFG clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* Enable fast mode plus driving capability for selected pin */
|
||||
SET_BIT(SYSCFG->CFGR2, (uint32_t)ConfigFastModePlus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the I2C fast mode plus driving capability.
|
||||
* @param ConfigFastModePlus Selects the pin.
|
||||
* This parameter can be one of the @ref I2CEx_FastModePlus values
|
||||
* @note For I2C1, fast mode plus driving capability can be disabled on all selected
|
||||
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
|
||||
* on each one of the following pins PB6, PB7, PB8 and PB9.
|
||||
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
|
||||
* can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
|
||||
* @note For all I2C2 pins fast mode plus driving capability can be disabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
|
||||
* @note For all I2C3 pins fast mode plus driving capability can be disabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
|
||||
|
||||
/* Enable SYSCFG clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* Disable fast mode plus driving capability for selected pin */
|
||||
CLEAR_BIT(SYSCFG->CFGR2, (uint32_t)ConfigFastModePlus);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* Fast Mode Plus Availability */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
+729
@@ -0,0 +1,729 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l0xx_hal_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @brief PWR HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Initialization/de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l0xx_hal.h"
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Private
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(PWR_PVD_SUPPORT)
|
||||
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
|
||||
* @{
|
||||
*/
|
||||
#define PVD_MODE_IT (0x00010000U)
|
||||
#define PVD_MODE_EVT (0x00020000U)
|
||||
#define PVD_RISING_EDGE (0x00000001U)
|
||||
#define PVD_FALLING_EDGE (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group1
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DeInit(void)
|
||||
{
|
||||
__HAL_RCC_PWR_FORCE_RESET();
|
||||
__HAL_RCC_PWR_RELEASE_RESET();
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group2
|
||||
* @brief Low Power modes configuration functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
|
||||
*** Backup domain ***
|
||||
=========================
|
||||
[..]
|
||||
After reset, the backup domain (RTC registers, RTC backup data
|
||||
registers) is protected against possible unwanted
|
||||
write accesses.
|
||||
To enable access to the RTC Domain and RTC registers, proceed as follows:
|
||||
(+) Enable the Power Controller (PWR) APB1 interface clock using the
|
||||
__HAL_RCC_PWR_CLK_ENABLE() macro.
|
||||
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
|
||||
|
||||
*** PVD configuration ***
|
||||
=========================
|
||||
[..]
|
||||
(+) The PVD is used to monitor the VDD power supply by comparing it to a
|
||||
threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
|
||||
(+) The PVD can use an external input analog voltage (PVD_IN) which is compared
|
||||
internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode
|
||||
when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).
|
||||
|
||||
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
|
||||
than the PVD threshold. This event is internally connected to the EXTI
|
||||
line16 and can generate an interrupt if enabled. This is done through
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
|
||||
(+) The PVD is stopped in Standby mode.
|
||||
(+) The PVD feature is not supported on L0 Value line.
|
||||
|
||||
*** WakeUp pin configuration ***
|
||||
================================
|
||||
[..]
|
||||
(+) WakeUp pin is used to wake up the system from Standby mode. This pin is
|
||||
forced in input pull-down configuration and is active on rising edges.
|
||||
(+) There are two WakeUp pins:
|
||||
WakeUp Pin 1 on PA.00.
|
||||
WakeUp Pin 2 on PC.13.
|
||||
WakeUp Pin 3 on PE.06 .
|
||||
|
||||
|
||||
[..]
|
||||
*** Main and Backup Regulators configuration ***
|
||||
================================================
|
||||
|
||||
(+) The main internal regulator can be configured to have a tradeoff between
|
||||
performance and power consumption when the device does not operate at
|
||||
the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG()
|
||||
macro which configures the two VOS bits in PWR_CR register:
|
||||
(++) PWR_REGULATOR_VOLTAGE_SCALE1 (VOS bits = 01), the regulator voltage output Scale 1 mode selected and
|
||||
the System frequency can go up to 32 MHz.
|
||||
(++) PWR_REGULATOR_VOLTAGE_SCALE2 (VOS bits = 10), the regulator voltage output Scale 2 mode selected and
|
||||
the System frequency can go up to 16 MHz.
|
||||
(++) PWR_REGULATOR_VOLTAGE_SCALE3 (VOS bits = 11), the regulator voltage output Scale 3 mode selected and
|
||||
the System frequency can go up to 4.2 MHz.
|
||||
|
||||
Refer to the datasheets for more details.
|
||||
|
||||
*** Low Power modes configuration ***
|
||||
=====================================
|
||||
[..]
|
||||
The device features 5 low-power modes:
|
||||
(+) Low power run mode: regulator in low power mode, limited clock frequency,
|
||||
limited number of peripherals running.
|
||||
(+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running.
|
||||
(+) Low power sleep mode: Cortex-M0+ core stopped, limited clock frequency,
|
||||
limited number of peripherals running, regulator in low power mode.
|
||||
(+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode.
|
||||
(+) Standby mode: VCORE domain powered off
|
||||
|
||||
*** Low power run mode ***
|
||||
=========================
|
||||
[..]
|
||||
To further reduce the consumption when the system is in Run mode, the regulator can be
|
||||
configured in low power mode. In this mode, the system frequency should not exceed
|
||||
MSI frequency range1.
|
||||
In Low power run mode, all I/O pins keep the same state as in Run mode.
|
||||
|
||||
(+) Entry:
|
||||
(++) VCORE in range2
|
||||
(++) Decrease the system frequency not to exceed the frequency of MSI frequency range1.
|
||||
(++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode()
|
||||
function.
|
||||
(+) Exit:
|
||||
(++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode()
|
||||
function.
|
||||
(++) Increase the system frequency if needed.
|
||||
|
||||
*** Sleep mode ***
|
||||
==================
|
||||
[..]
|
||||
(+) Entry:
|
||||
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
|
||||
functions with
|
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
|
||||
(+) Exit:
|
||||
(++) Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||||
controller (NVIC) can wake up the device from Sleep mode. If the WFE instruction was used to enter sleep mode,
|
||||
the MCU exits Sleep mode as soon as an event occurs.
|
||||
|
||||
*** Low power sleep mode ***
|
||||
============================
|
||||
[..]
|
||||
(+) Entry:
|
||||
The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx)
|
||||
functions with
|
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
(+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register.
|
||||
This reduces power consumption but increases the wake-up time.
|
||||
|
||||
(+) Exit:
|
||||
(++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt
|
||||
acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device
|
||||
from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode,
|
||||
the MCU exits Sleep mode as soon as an event occurs.
|
||||
|
||||
*** Stop mode ***
|
||||
=================
|
||||
[..]
|
||||
The Stop mode is based on the Cortex-M0+ deepsleep mode combined with peripheral
|
||||
clock gating. The voltage regulator can be configured either in normal or low-power mode.
|
||||
In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and
|
||||
the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.
|
||||
To get the lowest consumption in Stop mode, the internal Flash memory also enters low
|
||||
power mode. When the Flash memory is in power-down mode, an additional startup delay is
|
||||
incurred when waking up from Stop mode.
|
||||
To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
|
||||
sensor can be switched off before entering Stop mode. They can be switched on again by
|
||||
software after exiting Stop mode using the ULP bit in the PWR_CR register.
|
||||
In Stop mode, all I/O pins keep the same state as in Run mode.
|
||||
|
||||
(+) Entry:
|
||||
The Stop mode is entered using the HAL_PWR_EnterSTOPMode
|
||||
function with:
|
||||
(++) Main regulator ON.
|
||||
(++) Low Power regulator ON.
|
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
(+) Exit:
|
||||
(++) By issuing an interrupt or a wakeup event, the MSI or HSI16 RC
|
||||
oscillator is selected as system clock depending the bit STOPWUCK in the RCC_CFGR
|
||||
register
|
||||
|
||||
*** Standby mode ***
|
||||
====================
|
||||
[..]
|
||||
The Standby mode allows to achieve the lowest power consumption. It is based on the
|
||||
Cortex-M0+ deepsleep mode, with the voltage regulator disabled. The VCORE domain is
|
||||
consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are
|
||||
also switched off. SRAM and register contents are lost except for the RTC registers, RTC
|
||||
backup registers and Standby circuitry.
|
||||
|
||||
To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature
|
||||
sensor can be switched off before entering the Standby mode. They can be switched
|
||||
on again by software after exiting the Standby mode.
|
||||
function.
|
||||
|
||||
(+) Entry:
|
||||
(++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
|
||||
(+) Exit:
|
||||
(++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
|
||||
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
|
||||
|
||||
*** Auto-wakeup (AWU) from low-power mode ***
|
||||
=============================================
|
||||
[..]
|
||||
The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
|
||||
Wakeup event, a tamper event, a time-stamp event, or a comparator event,
|
||||
without depending on an external interrupt (Auto-wakeup mode).
|
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Stop mode
|
||||
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
|
||||
(+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
|
||||
or Event modes) using the EXTI_Init() function.
|
||||
(+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
|
||||
(+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
|
||||
and RTC_AlarmCmd() functions.
|
||||
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to:
|
||||
(+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
|
||||
or Event modes) using the EXTI_Init() function.
|
||||
(+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
|
||||
function.
|
||||
(+++) Configure the RTC to detect the tamper or time stamp event using the
|
||||
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
|
||||
functions.
|
||||
(++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
|
||||
(+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt
|
||||
or Event modes) using the EXTI_Init() function.
|
||||
(+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function.
|
||||
(+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
|
||||
RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
|
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Standby mode
|
||||
(++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
|
||||
(+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
|
||||
(+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
|
||||
and RTC_AlarmCmd() functions.
|
||||
(++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to:
|
||||
(+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
|
||||
function.
|
||||
(+++) Configure the RTC to detect the tamper or time stamp event using the
|
||||
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
|
||||
functions.
|
||||
(++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
|
||||
(+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
|
||||
(+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
|
||||
RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
|
||||
|
||||
(+) Comparator auto-wakeup (AWU) from the Stop mode
|
||||
(++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
|
||||
event, it is necessary to:
|
||||
(+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2
|
||||
to be sensitive to to the selected edges (falling, rising or falling
|
||||
and rising) (Interrupt or Event modes) using the EXTI_Init() function.
|
||||
(+++) Configure the comparator to generate the event.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables access to the backup domain (RTC registers, RTC
|
||||
* backup data registers ).
|
||||
* @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableBkUpAccess(void)
|
||||
{
|
||||
/* Enable access to RTC and backup registers */
|
||||
SET_BIT(PWR->CR, PWR_CR_DBP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables access to the backup domain
|
||||
* @note Applies to RTC registers, RTC backup data registers.
|
||||
* @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableBkUpAccess(void)
|
||||
{
|
||||
/* Disable access to RTC and backup registers */
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_DBP);
|
||||
}
|
||||
|
||||
#if defined(PWR_PVD_SUPPORT)
|
||||
/**
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
|
||||
* @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
|
||||
* information for the PVD.
|
||||
* @note Refer to the electrical characteristics of your device datasheet for
|
||||
* more details about the voltage threshold corresponding to each
|
||||
* detection level.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
|
||||
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
|
||||
|
||||
/* Set PLS[7:5] bits according to PVDLevel value */
|
||||
MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
|
||||
|
||||
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_IT();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
|
||||
|
||||
/* Configure interrupt mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_IT();
|
||||
}
|
||||
|
||||
/* Configure event mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
|
||||
}
|
||||
|
||||
/* Configure the edge */
|
||||
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
|
||||
}
|
||||
|
||||
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnablePVD(void)
|
||||
{
|
||||
/* Enable the power voltage detector */
|
||||
SET_BIT(PWR->CR, PWR_CR_PVDE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisablePVD(void)
|
||||
{
|
||||
/* Disable the power voltage detector */
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
|
||||
}
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
|
||||
/**
|
||||
* @brief Enables the WakeUp PINx functionality.
|
||||
* @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WAKEUP_PIN1
|
||||
* @arg PWR_WAKEUP_PIN2
|
||||
* @arg PWR_WAKEUP_PIN3 for stm32l07xxx and stm32l08xxx devices only.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
/* Enable the EWUPx pin */
|
||||
SET_BIT(PWR->CSR, WakeUpPinx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the WakeUp PINx functionality.
|
||||
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WAKEUP_PIN1
|
||||
* @arg PWR_WAKEUP_PIN2
|
||||
* @arg PWR_WAKEUP_PIN3 for stm32l07xxx and stm32l08xxx devices only.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
/* Disable the EWUPx pin */
|
||||
CLEAR_BIT(PWR->CSR, WakeUpPinx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Sleep mode.
|
||||
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
|
||||
* @param Regulator: Specifies the regulator state in SLEEP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
|
||||
* @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
|
||||
* @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
|
||||
* When WFI entry is used, tick interrupt have to be disabled if not desired as
|
||||
* the interrupt wake up source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0U;
|
||||
uint32_t ulpbit, vrefinbit;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
||||
|
||||
/* It is forbidden to configure both EN_VREFINT=1 and ULP=1 if the device is
|
||||
in Stop mode or in Sleep/Low-power sleep mode */
|
||||
ulpbit = READ_BIT(PWR->CR, PWR_CR_ULP);
|
||||
vrefinbit = READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_EN_VREFINT);
|
||||
if((ulpbit != 0) && (vrefinbit != 0))
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_ULP);
|
||||
}
|
||||
|
||||
/* Select the regulator state in Sleep mode ---------------------------------*/
|
||||
tmpreg = PWR->CR;
|
||||
|
||||
/* Clear PDDS and LPDS bits */
|
||||
CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR));
|
||||
|
||||
/* Set LPSDSR bit according to PWR_Regulator value */
|
||||
SET_BIT(tmpreg, Regulator);
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
|
||||
|
||||
/* Select SLEEP mode entry -------------------------------------------------*/
|
||||
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
|
||||
if((ulpbit != 0) && (vrefinbit != 0))
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_ULP);
|
||||
}
|
||||
|
||||
/* Additional NOP to ensure all pending instructions are flushed before entering low power mode */
|
||||
__NOP();
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Stop mode.
|
||||
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||||
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
|
||||
* MSI or HSI16 RCoscillator is selected as system clock depending
|
||||
* the bit STOPWUCK in the RCC_CFGR register.
|
||||
* @note When the voltage regulator operates in low power mode, an additional
|
||||
* startup delay is incurred when waking up from Stop mode.
|
||||
* By keeping the internal regulator ON during Stop mode, the consumption
|
||||
* is higher although the startup time is reduced.
|
||||
* @note Before entering in this function, it is important to ensure that the WUF
|
||||
* wakeup flag is cleared. To perform this action, it is possible to call the
|
||||
* following macro : __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU)
|
||||
*
|
||||
* @param Regulator: Specifies the regulator state in Stop mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
|
||||
* @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
|
||||
* @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
|
||||
* @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0U;
|
||||
uint32_t ulpbit, vrefinbit;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||||
|
||||
/* It is forbidden to configure both EN_VREFINT=1 and ULP=1 if the device is
|
||||
in Stop mode or in Sleep/Low-power sleep mode */
|
||||
ulpbit = READ_BIT(PWR->CR, PWR_CR_ULP);
|
||||
vrefinbit = READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_EN_VREFINT);
|
||||
if((ulpbit != 0) && (vrefinbit != 0))
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_ULP);
|
||||
}
|
||||
|
||||
/* Select the regulator state in Stop mode ---------------------------------*/
|
||||
tmpreg = PWR->CR;
|
||||
|
||||
/* Clear PDDS and LPDS bits */
|
||||
CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR));
|
||||
|
||||
/* Set LPSDSR bit according to PWR_Regulator value */
|
||||
SET_BIT(tmpreg, Regulator);
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
|
||||
|
||||
/* Select Stop mode entry --------------------------------------------------*/
|
||||
if(STOPEntry == PWR_STOPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
|
||||
|
||||
if((ulpbit != 0) && (vrefinbit != 0))
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_ULP);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Standby mode.
|
||||
* @note In Standby mode, all I/O pins are high impedance except for:
|
||||
* - Reset pad (still available)
|
||||
* - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
|
||||
* Alarm out, or RTC clock calibration out.
|
||||
* - RTC_AF2 pin (PC13) if configured for tamper.
|
||||
* - WKUP pin 1 (PA00) if enabled.
|
||||
* - WKUP pin 2 (PC13) if enabled.
|
||||
* - WKUP pin 3 (PE06) if enabled, for stm32l07xxx and stm32l08xxx devices only.
|
||||
* - WKUP pin 3 (PA02) if enabled, for stm32l031xx devices only.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
/* Select Standby mode */
|
||||
SET_BIT(PWR->CR, PWR_CR_PDDS);
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
|
||||
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM)
|
||||
__force_stores();
|
||||
#endif
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
|
||||
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* Setting this bit is useful when the processor is expected to run only on
|
||||
* interruptions handling.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSleepOnExit(void)
|
||||
{
|
||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
||||
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSleepOnExit(void)
|
||||
{
|
||||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enables CORTEX M0+ SEVONPEND bit.
|
||||
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSEVOnPend(void)
|
||||
{
|
||||
/* Set SEVONPEND bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disables CORTEX M0+ SEVONPEND bit.
|
||||
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSEVOnPend(void)
|
||||
{
|
||||
/* Clear SEVONPEND bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
#if defined(PWR_PVD_SUPPORT)
|
||||
/**
|
||||
* @brief This function handles the PWR PVD interrupt request.
|
||||
* @note This API should be called under the PVD_IRQHandler().
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_PVD_IRQHandler(void)
|
||||
{
|
||||
/* Check PWR exti flag */
|
||||
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
|
||||
{
|
||||
/* PWR PVD interrupt user callback */
|
||||
HAL_PWR_PVDCallback();
|
||||
|
||||
/* Clear PWR Exti pending bit */
|
||||
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PWR PVD interrupt callback
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PWR_PVDCallback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PWR_PVDCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
+180
@@ -0,0 +1,180 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l0xx_hal_pwr_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Extended Initialization and de-initialization functions
|
||||
* + Extended Peripheral Control functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l0xx_hal.h"
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx_Private
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Extended_TimeOut_Value PWREx Flag Setting Time Out Value
|
||||
* @{
|
||||
*/
|
||||
#define PWR_FLAG_SETTING_DELAY_US 50U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions
|
||||
* @brief Low Power modes configuration functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Peripheral extended features functions #####
|
||||
===============================================================================
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return Voltage Scaling Range.
|
||||
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or PWR_REGULATOR_VOLTAGE_SCALE3)
|
||||
*/
|
||||
uint32_t HAL_PWREx_GetVoltageRange(void)
|
||||
{
|
||||
return (PWR->CR & PWR_CR_VOS);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enables the Fast WakeUp from Ultra Low Power mode.
|
||||
* @note This bit works in conjunction with ULP bit.
|
||||
* Means, when ULP = 1 and FWU = 1 :VREFINT startup time is ignored when
|
||||
* exiting from low power mode.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_EnableFastWakeUp(void)
|
||||
{
|
||||
/* Enable the fast wake up */
|
||||
SET_BIT(PWR->CR, PWR_CR_FWU);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Fast WakeUp from Ultra Low Power mode.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_DisableFastWakeUp(void)
|
||||
{
|
||||
/* Disable the fast wake up */
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_FWU);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Ultra Low Power mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_EnableUltraLowPower(void)
|
||||
{
|
||||
/* Enable the Ultra Low Power mode */
|
||||
SET_BIT(PWR->CR, PWR_CR_ULP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Ultra Low Power mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_DisableUltraLowPower(void)
|
||||
{
|
||||
/* Disable the Ultra Low Power mode */
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_ULP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Low Power Run mode.
|
||||
* @note Low power run mode can only be entered when VCORE is in range 2.
|
||||
* In addition, the dynamic voltage scaling must not be used when Low
|
||||
* power run mode is selected. Only Stop and Sleep modes with regulator
|
||||
* configured in Low power mode is allowed when Low power run mode is
|
||||
* selected.
|
||||
* @note The frequency of the system clock must be decreased to not exceed the
|
||||
* frequency of RCC_MSIRANGE_1.
|
||||
* @note In Low power run mode, all I/O pins keep the same state as in Run mode.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_EnableLowPowerRunMode(void)
|
||||
{
|
||||
/* Enters the Low Power Run mode */
|
||||
SET_BIT(PWR->CR, PWR_CR_LPSDSR);
|
||||
SET_BIT(PWR->CR, PWR_CR_LPRUN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Low Power Run mode.
|
||||
* @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
|
||||
* REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
|
||||
* returns HAL_TIMEOUT status). The system clock frequency can then be
|
||||
* increased above 2 MHz.
|
||||
* @retval HAL_StatusTypeDef
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
|
||||
{
|
||||
uint32_t wait_loop_index = 0U;
|
||||
|
||||
/* Exit the Low Power Run mode */
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_LPRUN);
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR);
|
||||
|
||||
/* Wait until REGLPF is reset */
|
||||
wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U));
|
||||
|
||||
while ((wait_loop_index != 0U) && (HAL_IS_BIT_SET(PWR->CSR, PWR_CSR_REGLPF)))
|
||||
{
|
||||
wait_loop_index--;
|
||||
}
|
||||
|
||||
if (HAL_IS_BIT_SET(PWR->CSR, PWR_CSR_REGLPF))
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
+1501
File diff suppressed because it is too large
Load Diff
+1221
File diff suppressed because it is too large
Load Diff
+7173
File diff suppressed because it is too large
Load Diff
+426
@@ -0,0 +1,426 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l0xx_hal_tim_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief TIM HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Timer Extended peripheral:
|
||||
* + Time Master and Slave synchronization configuration
|
||||
* + Timer remapping capabilities configuration
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### TIMER Extended features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The Timer Extended features include:
|
||||
(#) Synchronization circuit to control the timer with external signals and to
|
||||
interconnect several timers together.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx TIMEx
|
||||
* @brief TIM Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to:
|
||||
(+) Configure Master synchronization.
|
||||
(+) Configure timer remapping capabilities.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the TIM in master mode.
|
||||
* @param htim TIM handle.
|
||||
* @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
|
||||
* contains the selected trigger output (TRGO) and the Master/Slave
|
||||
* mode.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
||||
const TIM_MasterConfigTypeDef *sMasterConfig)
|
||||
{
|
||||
uint32_t tmpcr2;
|
||||
uint32_t tmpsmcr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
||||
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
||||
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
||||
|
||||
/* Check input state */
|
||||
__HAL_LOCK(htim);
|
||||
|
||||
/* Change the handler state */
|
||||
htim->State = HAL_TIM_STATE_BUSY;
|
||||
|
||||
/* Get the TIMx CR2 register value */
|
||||
tmpcr2 = htim->Instance->CR2;
|
||||
|
||||
/* Get the TIMx SMCR register value */
|
||||
tmpsmcr = htim->Instance->SMCR;
|
||||
|
||||
/* Reset the MMS Bits */
|
||||
tmpcr2 &= ~TIM_CR2_MMS;
|
||||
/* Select the TRGO source */
|
||||
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
||||
|
||||
/* Update TIMx CR2 */
|
||||
htim->Instance->CR2 = tmpcr2;
|
||||
|
||||
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
||||
{
|
||||
/* Reset the MSM Bit */
|
||||
tmpsmcr &= ~TIM_SMCR_MSM;
|
||||
/* Set master mode */
|
||||
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
||||
|
||||
/* Update TIMx SMCR */
|
||||
htim->Instance->SMCR = tmpsmcr;
|
||||
}
|
||||
|
||||
/* Change the htim state */
|
||||
htim->State = HAL_TIM_STATE_READY;
|
||||
|
||||
__HAL_UNLOCK(htim);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the TIMx Remapping input capabilities.
|
||||
@if STM32L073xx
|
||||
* @note It is not possible to connect TIM2 and TIM21 on PB5(AF4) at the same time.
|
||||
* When selecting TIM3_TI2_GPIOB5_AF4, Channel2 of TIM3 will be
|
||||
* connected to PB5(AF4) and Channel2 of TIM21 will be connected to
|
||||
* some other GPIOs. (refer to alternate functions for more details)
|
||||
* When selecting TIM3_TI2_GPIO_DEF, Channel2 of Timer 3 will be
|
||||
* connected an GPIO (other than PB5(AF4)) and Channel2 of TIM21
|
||||
* will be connected to PB5(AF4).
|
||||
* @note When TIM2 ETR is fed with HSI48, this ETR must be prescaled internally
|
||||
* to the TIMER2 because the maximum system frequency is 32 MHz
|
||||
@endif
|
||||
* @param htim TIM handle.
|
||||
* @param Remap specifies the TIM remapping source.
|
||||
@if STM32L073xx
|
||||
* For TIM2, the parameter is a combination of 2 fields (field1 | field2):
|
||||
*
|
||||
* field1 can have the following values:
|
||||
* @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default):
|
||||
* PA0(AF5) or PA5(AF2) or PA15(AF2) or PE9(AF2)
|
||||
* @arg TIM2_ETR_HSI48: TIM2 ETR connected to HSI48
|
||||
* @arg TIM2_ETR_HSI16: TIM2 ETR connected to HSI16
|
||||
* @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE
|
||||
* @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output
|
||||
* @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output
|
||||
*
|
||||
* field2 can have the following values:
|
||||
* @arg TIM2_TI4_GPIO : TIM2 TI4 connected to GPIO1(default):
|
||||
* PA3(AF2) or PB11(AF2) or PE12(AF0)
|
||||
* @arg TIM2_TI4_COMP1: TIM2 TI4 connected to COMP1
|
||||
* @arg TIM2_TI4_COMP2: TIM2 TI4 connected to COMP2
|
||||
@endif
|
||||
@if STM32L031xx
|
||||
* For TIM2, the parameter is a combination of 2 fields (field1 | field2):
|
||||
*
|
||||
* field1 can have the following values:
|
||||
* @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default):
|
||||
* PA0(AF5) or PA5(AF2) or PA15(AF2)
|
||||
* @arg TIM2_ETR_HSI16: TIM2 ETR connected to HS16 (HSIOUT)
|
||||
* @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE
|
||||
* @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output
|
||||
* @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output
|
||||
*
|
||||
* field2 can have the following values:
|
||||
* @arg TIM2_TI4_GPIO : TIM2 TI4 connected to GPIO (default):
|
||||
* PA3(AF2) or PB11(AF2) or PB1(AF5)
|
||||
* @arg TIM2_TI4_COMP1_OUT: TIM2 TI4 connected to COMP1 output
|
||||
* @arg TIM2_TI4_COMP2_OUT: TIM2 TI4 connected to COMP2 output
|
||||
@endif
|
||||
@if STM32L011xx
|
||||
* For TIM2, the parameter is a combination of 2 fields (field1 | field2):
|
||||
*
|
||||
* field1 can have the following values:
|
||||
* @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default):
|
||||
* PA0(AF5) or PA5(AF2) or PA15(AF2)
|
||||
* @arg TIM2_ETR_HSI16: TIM2 ETR connected to HS16 (HSIOUT)
|
||||
* @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE
|
||||
* @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output
|
||||
* @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output
|
||||
*
|
||||
* field2 can have the following values:
|
||||
* @arg TIM2_TI4_GPIO : TIM2 TI4 connected to GPIO (default):
|
||||
* PA3(AF2) or PB11(AF2) or PB1(AF5)
|
||||
* @arg TIM2_TI4_COMP1_OUT: TIM2 TI4 connected to COMP1 output
|
||||
* @arg TIM2_TI4_COMP2_OUT: TIM2 TI4 connected to COMP2 output
|
||||
@endif
|
||||
@if STM32L051xx
|
||||
* For TIM2, the parameter is a combination of 2 fields (field1 | field2):
|
||||
*
|
||||
* field1 can have the following values:
|
||||
* @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default):
|
||||
* PA0(AF5) or PA5(AF2) or PA15(AF2) or PE9(AF2)
|
||||
* @arg TIM2_ETR_HSI48: TIM2 ETR connected to HSI48
|
||||
* @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE
|
||||
* @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output
|
||||
* @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output
|
||||
*
|
||||
* field2 can have the following values:
|
||||
* @arg TIM2_TI4_GPIO: TIM2 TI4 connected to GPIO1(default):
|
||||
* PA3(AF2) or PB11(AF2) or PE12(AF0)
|
||||
* @arg TIM2_TI4_COMP1: TIM2 TI4 connected to COMP1
|
||||
* @arg TIM2_TI4_COMP2: TIM2 TI4 connected to COMP2
|
||||
* @arg TIM2_TI4_GPIO2: TIM2 TI4 connected to GPIO2 :
|
||||
* PA3(AF2) or PB11(AF2) or PE12(AF0)
|
||||
@endif
|
||||
@if STM32L073xx
|
||||
*
|
||||
* For TIM3, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4):
|
||||
*
|
||||
* field1 can have the following values:
|
||||
* @arg TIM3_ETR_GPIO: TIM3 ETR connected to GPIO (default):
|
||||
* PE2(AF2) or PD2(AF2) or PE2(AF2)
|
||||
* @arg TIM3_ETR_HSI: TIM3 ETR connected to HSI
|
||||
*
|
||||
* field2 can have the following values:
|
||||
* @arg TIM3_TI1_USB_SOF: TIM3 TI1 connected to USB_SOF (default)
|
||||
* @arg TIM3_TI1_GPIO: TIM3 TI1 connected to GPIO :
|
||||
* PE3(AF2) or PA6(AF2) or PC6(AF2) or PB4(AF2)
|
||||
*
|
||||
* field3 can have the following values:
|
||||
* @arg TIM3_TI2_GPIOB5_AF4:TIM3 TI3 connected to P5(AF4)
|
||||
* (refer to note)
|
||||
* @arg TIM3_TI2_GPIO_DEF: TIM3 TI3 connected to GPIO (default):
|
||||
* PA7(AF2) or PB5(AF4) or PC7(AF2) or PE7(AF2)
|
||||
*
|
||||
* field4 can have the following values:
|
||||
* @arg TIM3_TI4_GPIO_DEF: TIM3 TI4 connected to GPIO:
|
||||
* PB1(AF2) or PE6(AF2)
|
||||
* @arg TIM3_TI4_GPIOC9_AF2:TIM3 TI4 connected to PC9(AF)2
|
||||
@endif
|
||||
@if STM32L073xx
|
||||
* For TIM21, the parameter is a combination of 3 fields (field1 | field2 | field3):
|
||||
*
|
||||
* field1 can have the following values:
|
||||
* @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) :
|
||||
* PC9(AF0) or PA1(AF5)
|
||||
* @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output
|
||||
* @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output
|
||||
* @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE
|
||||
*
|
||||
* field2 can have the following values:
|
||||
* @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO
|
||||
* @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt
|
||||
* @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC
|
||||
* @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock
|
||||
* @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE
|
||||
* @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI
|
||||
* @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT
|
||||
* @arg TIM21_TI1_GPIO: TIM21 TI1 connected to GPIO(default):
|
||||
* PA2(AF0) or PB13(AF6) or PE5(AF0) or PD0(AF0)
|
||||
*
|
||||
* field3 can have the following values:
|
||||
* @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default):
|
||||
* PA3(AF0) or PB14(AF6) or PE6(AF0) or PD7(AF1)
|
||||
* @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output
|
||||
@endif
|
||||
@if STM32L031xx
|
||||
* For TIM21, the parameter is a combination of 3 fields (field1 | field2 | field3):
|
||||
*
|
||||
* field1 can have the following values:
|
||||
* @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) :
|
||||
* PA1(AF5)
|
||||
* @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output
|
||||
* @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output
|
||||
* @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE
|
||||
*
|
||||
* field2 can have the following values:
|
||||
* @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO
|
||||
* @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt
|
||||
* @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC
|
||||
* @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock
|
||||
* @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE
|
||||
* @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI
|
||||
* @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT
|
||||
*
|
||||
* field3 can have the following values:
|
||||
* @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default):
|
||||
* PA3(AF0) or PB14(AF6)
|
||||
* @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output
|
||||
@endif
|
||||
@if STM32L011xx
|
||||
* For TIM21, the parameter is a combination of 3 fields (field1 | field2 | field3):
|
||||
*
|
||||
* field1 can have the following values:
|
||||
* @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) :
|
||||
* PA1(AF5)
|
||||
* @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output
|
||||
* @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output
|
||||
* @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE
|
||||
*
|
||||
* field2 can have the following values:
|
||||
* @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO
|
||||
* @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt
|
||||
* @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC
|
||||
* @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock
|
||||
* @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE
|
||||
* @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI
|
||||
* @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT
|
||||
*
|
||||
* field3 can have the following values:
|
||||
* @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default):
|
||||
* PA3(AF0) or PB14(AF6)
|
||||
* @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output
|
||||
@endif
|
||||
@if STM32L051xx
|
||||
* For TIM21, the parameter is a combination of 3 fields (field1 | field2 | field3):
|
||||
*
|
||||
* field1 can have the following values:
|
||||
* @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) :
|
||||
* PC9(AF0) or PA1(AF5)
|
||||
* @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output
|
||||
* @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output
|
||||
* @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE
|
||||
*
|
||||
* field2 can have the following values:
|
||||
* @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO
|
||||
* @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt
|
||||
* @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC
|
||||
* @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock
|
||||
* @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE
|
||||
* @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI
|
||||
* @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT
|
||||
* @arg TIM21_TI1_GPIO: TIM21 TI1 connected to GPIO(default):
|
||||
* PA2(AF0) or PB13(AF6) or PE5(AF0) or PD0(AF0)
|
||||
*
|
||||
* field3 can have the following values:
|
||||
* @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default):
|
||||
* PA3(AF0) or PB14(AF6) or PE6(AF0) or PD7(AF1)
|
||||
* @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output
|
||||
@endif
|
||||
@if STM32L073xx
|
||||
*
|
||||
* For TIM22, the parameter can have the following values:
|
||||
* @arg TIM22_ETR_LSE: TIM22 ETR connected to LSE
|
||||
* @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output
|
||||
* @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output
|
||||
* @arg TIM22_ETR_GPIO: TIM22 ETR connected to GPIO(default):
|
||||
* PC8(AF0) or PA4(AF5)
|
||||
* @arg TIM22_TI1_GPIO: TIM22 TI1 connected to GPIO(default):
|
||||
* PC6(AF0) or PA6(AF5) or PB4(AF4) or PE0(AF3)
|
||||
* @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output
|
||||
* @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output
|
||||
@endif
|
||||
@if STM32L031xx
|
||||
*
|
||||
* For TIM22, the parameter is a combination of 2 fields (field1 | field2):
|
||||
*
|
||||
* field1 can have the following values:
|
||||
* @arg TIM22_ETR_LSE: TIM22 ETR connected to LSE
|
||||
* @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output
|
||||
* @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output
|
||||
* @arg TIM22_ETR_GPIO: TIM22 ETR connected to GPIO(default):
|
||||
* PA4(AF5)
|
||||
*
|
||||
* field2 can have the following values:
|
||||
* @arg TIM22_TI1_GPIO: TIM22 TI1 connected to GPIO(default):
|
||||
* PC0(AF6) or PA5(AF6) or PB4(AF4)
|
||||
* @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output
|
||||
* @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output
|
||||
*
|
||||
@endif
|
||||
@if STM32L051xx
|
||||
*
|
||||
* For TIM22, the parameter is a combination of 2 fields (field1 | field2):
|
||||
*
|
||||
* field1 can have the following values:
|
||||
* @arg TIM22_ETR_LSE: TIM22 ETR connected to LSE
|
||||
* @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output
|
||||
* @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output
|
||||
* @arg TIM22_ETR_GPIO: TIM22 ETR connected to GPIO(default):
|
||||
* PC8(AF0) or PA4(AF5)
|
||||
*
|
||||
* field2 can have the following values:
|
||||
* @arg TIM22_TI1_GPIO: TIM22 TI1 connected to GPIO(default):
|
||||
* PC6(AF0) or PA6(AF5) or PB4(AF4) or PE0(AF3)
|
||||
* @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output
|
||||
* @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output
|
||||
@endif
|
||||
*
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
|
||||
{
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_TIM_REMAP(htim->Instance, Remap));
|
||||
|
||||
__HAL_LOCK(htim);
|
||||
|
||||
/* Set the Timer remapping configuration */
|
||||
WRITE_REG(htim->Instance->OR, Remap);
|
||||
|
||||
__HAL_UNLOCK(htim);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
Reference in New Issue
Block a user