GbTModuleSW.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001e4 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000d4fc 080001e8 080001e8 000011e8 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000dbc 0800d6e8 0800d6e8 0000e6e8 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 0800e4a4 0800e4a4 0001024c 2**0 CONTENTS 4 .ARM 00000008 0800e4a4 0800e4a4 0000f4a4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 0800e4ac 0800e4ac 0001024c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0800e4ac 0800e4ac 0000f4ac 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 0800e4b0 0800e4b0 0000f4b0 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 0000024c 20000000 0800e4b4 00010000 2**3 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000032d0 2000024c 0800e700 0001024c 2**2 ALLOC 10 ._user_heap_stack 00000604 2000351c 0800e700 0001051c 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 0001024c 2**0 CONTENTS, READONLY 12 .debug_info 00011c4c 00000000 00000000 00010275 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00004288 00000000 00000000 00021ec1 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 000010b8 00000000 00000000 00026150 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00000c95 00000000 00000000 00027208 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 000244b3 00000000 00000000 00027e9d 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0001799f 00000000 00000000 0004c350 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000c007a 00000000 00000000 00063cef 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 00123d69 2**0 CONTENTS, READONLY 20 .debug_frame 000059e0 00000000 00000000 00123dac 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000069 00000000 00000000 0012978c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001e8 <__do_global_dtors_aux>: 80001e8: b510 push {r4, lr} 80001ea: 4c05 ldr r4, [pc, #20] @ (8000200 <__do_global_dtors_aux+0x18>) 80001ec: 7823 ldrb r3, [r4, #0] 80001ee: b933 cbnz r3, 80001fe <__do_global_dtors_aux+0x16> 80001f0: 4b04 ldr r3, [pc, #16] @ (8000204 <__do_global_dtors_aux+0x1c>) 80001f2: b113 cbz r3, 80001fa <__do_global_dtors_aux+0x12> 80001f4: 4804 ldr r0, [pc, #16] @ (8000208 <__do_global_dtors_aux+0x20>) 80001f6: f3af 8000 nop.w 80001fa: 2301 movs r3, #1 80001fc: 7023 strb r3, [r4, #0] 80001fe: bd10 pop {r4, pc} 8000200: 2000024c .word 0x2000024c 8000204: 00000000 .word 0x00000000 8000208: 0800d6cc .word 0x0800d6cc 0800020c : 800020c: b508 push {r3, lr} 800020e: 4b03 ldr r3, [pc, #12] @ (800021c ) 8000210: b11b cbz r3, 800021a 8000212: 4903 ldr r1, [pc, #12] @ (8000220 ) 8000214: 4803 ldr r0, [pc, #12] @ (8000224 ) 8000216: f3af 8000 nop.w 800021a: bd08 pop {r3, pc} 800021c: 00000000 .word 0x00000000 8000220: 20000250 .word 0x20000250 8000224: 0800d6cc .word 0x0800d6cc 08000228 : 8000228: f810 2b01 ldrb.w r2, [r0], #1 800022c: f811 3b01 ldrb.w r3, [r1], #1 8000230: 2a01 cmp r2, #1 8000232: bf28 it cs 8000234: 429a cmpcs r2, r3 8000236: d0f7 beq.n 8000228 8000238: 1ad0 subs r0, r2, r3 800023a: 4770 bx lr 0800023c : 800023c: 4603 mov r3, r0 800023e: f813 2b01 ldrb.w r2, [r3], #1 8000242: 2a00 cmp r2, #0 8000244: d1fb bne.n 800023e 8000246: 1a18 subs r0, r3, r0 8000248: 3801 subs r0, #1 800024a: 4770 bx lr 0800024c <__aeabi_drsub>: 800024c: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 8000250: e002 b.n 8000258 <__adddf3> 8000252: bf00 nop 08000254 <__aeabi_dsub>: 8000254: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 08000258 <__adddf3>: 8000258: b530 push {r4, r5, lr} 800025a: ea4f 0441 mov.w r4, r1, lsl #1 800025e: ea4f 0543 mov.w r5, r3, lsl #1 8000262: ea94 0f05 teq r4, r5 8000266: bf08 it eq 8000268: ea90 0f02 teqeq r0, r2 800026c: bf1f itttt ne 800026e: ea54 0c00 orrsne.w ip, r4, r0 8000272: ea55 0c02 orrsne.w ip, r5, r2 8000276: ea7f 5c64 mvnsne.w ip, r4, asr #21 800027a: ea7f 5c65 mvnsne.w ip, r5, asr #21 800027e: f000 80e2 beq.w 8000446 <__adddf3+0x1ee> 8000282: ea4f 5454 mov.w r4, r4, lsr #21 8000286: ebd4 5555 rsbs r5, r4, r5, lsr #21 800028a: bfb8 it lt 800028c: 426d neglt r5, r5 800028e: dd0c ble.n 80002aa <__adddf3+0x52> 8000290: 442c add r4, r5 8000292: ea80 0202 eor.w r2, r0, r2 8000296: ea81 0303 eor.w r3, r1, r3 800029a: ea82 0000 eor.w r0, r2, r0 800029e: ea83 0101 eor.w r1, r3, r1 80002a2: ea80 0202 eor.w r2, r0, r2 80002a6: ea81 0303 eor.w r3, r1, r3 80002aa: 2d36 cmp r5, #54 @ 0x36 80002ac: bf88 it hi 80002ae: bd30 pophi {r4, r5, pc} 80002b0: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 80002b4: ea4f 3101 mov.w r1, r1, lsl #12 80002b8: f44f 1c80 mov.w ip, #1048576 @ 0x100000 80002bc: ea4c 3111 orr.w r1, ip, r1, lsr #12 80002c0: d002 beq.n 80002c8 <__adddf3+0x70> 80002c2: 4240 negs r0, r0 80002c4: eb61 0141 sbc.w r1, r1, r1, lsl #1 80002c8: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 80002cc: ea4f 3303 mov.w r3, r3, lsl #12 80002d0: ea4c 3313 orr.w r3, ip, r3, lsr #12 80002d4: d002 beq.n 80002dc <__adddf3+0x84> 80002d6: 4252 negs r2, r2 80002d8: eb63 0343 sbc.w r3, r3, r3, lsl #1 80002dc: ea94 0f05 teq r4, r5 80002e0: f000 80a7 beq.w 8000432 <__adddf3+0x1da> 80002e4: f1a4 0401 sub.w r4, r4, #1 80002e8: f1d5 0e20 rsbs lr, r5, #32 80002ec: db0d blt.n 800030a <__adddf3+0xb2> 80002ee: fa02 fc0e lsl.w ip, r2, lr 80002f2: fa22 f205 lsr.w r2, r2, r5 80002f6: 1880 adds r0, r0, r2 80002f8: f141 0100 adc.w r1, r1, #0 80002fc: fa03 f20e lsl.w r2, r3, lr 8000300: 1880 adds r0, r0, r2 8000302: fa43 f305 asr.w r3, r3, r5 8000306: 4159 adcs r1, r3 8000308: e00e b.n 8000328 <__adddf3+0xd0> 800030a: f1a5 0520 sub.w r5, r5, #32 800030e: f10e 0e20 add.w lr, lr, #32 8000312: 2a01 cmp r2, #1 8000314: fa03 fc0e lsl.w ip, r3, lr 8000318: bf28 it cs 800031a: f04c 0c02 orrcs.w ip, ip, #2 800031e: fa43 f305 asr.w r3, r3, r5 8000322: 18c0 adds r0, r0, r3 8000324: eb51 71e3 adcs.w r1, r1, r3, asr #31 8000328: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 800032c: d507 bpl.n 800033e <__adddf3+0xe6> 800032e: f04f 0e00 mov.w lr, #0 8000332: f1dc 0c00 rsbs ip, ip, #0 8000336: eb7e 0000 sbcs.w r0, lr, r0 800033a: eb6e 0101 sbc.w r1, lr, r1 800033e: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 8000342: d31b bcc.n 800037c <__adddf3+0x124> 8000344: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 8000348: d30c bcc.n 8000364 <__adddf3+0x10c> 800034a: 0849 lsrs r1, r1, #1 800034c: ea5f 0030 movs.w r0, r0, rrx 8000350: ea4f 0c3c mov.w ip, ip, rrx 8000354: f104 0401 add.w r4, r4, #1 8000358: ea4f 5244 mov.w r2, r4, lsl #21 800035c: f512 0f80 cmn.w r2, #4194304 @ 0x400000 8000360: f080 809a bcs.w 8000498 <__adddf3+0x240> 8000364: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8000368: bf08 it eq 800036a: ea5f 0c50 movseq.w ip, r0, lsr #1 800036e: f150 0000 adcs.w r0, r0, #0 8000372: eb41 5104 adc.w r1, r1, r4, lsl #20 8000376: ea41 0105 orr.w r1, r1, r5 800037a: bd30 pop {r4, r5, pc} 800037c: ea5f 0c4c movs.w ip, ip, lsl #1 8000380: 4140 adcs r0, r0 8000382: eb41 0101 adc.w r1, r1, r1 8000386: 3c01 subs r4, #1 8000388: bf28 it cs 800038a: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 800038e: d2e9 bcs.n 8000364 <__adddf3+0x10c> 8000390: f091 0f00 teq r1, #0 8000394: bf04 itt eq 8000396: 4601 moveq r1, r0 8000398: 2000 moveq r0, #0 800039a: fab1 f381 clz r3, r1 800039e: bf08 it eq 80003a0: 3320 addeq r3, #32 80003a2: f1a3 030b sub.w r3, r3, #11 80003a6: f1b3 0220 subs.w r2, r3, #32 80003aa: da0c bge.n 80003c6 <__adddf3+0x16e> 80003ac: 320c adds r2, #12 80003ae: dd08 ble.n 80003c2 <__adddf3+0x16a> 80003b0: f102 0c14 add.w ip, r2, #20 80003b4: f1c2 020c rsb r2, r2, #12 80003b8: fa01 f00c lsl.w r0, r1, ip 80003bc: fa21 f102 lsr.w r1, r1, r2 80003c0: e00c b.n 80003dc <__adddf3+0x184> 80003c2: f102 0214 add.w r2, r2, #20 80003c6: bfd8 it le 80003c8: f1c2 0c20 rsble ip, r2, #32 80003cc: fa01 f102 lsl.w r1, r1, r2 80003d0: fa20 fc0c lsr.w ip, r0, ip 80003d4: bfdc itt le 80003d6: ea41 010c orrle.w r1, r1, ip 80003da: 4090 lslle r0, r2 80003dc: 1ae4 subs r4, r4, r3 80003de: bfa2 ittt ge 80003e0: eb01 5104 addge.w r1, r1, r4, lsl #20 80003e4: 4329 orrge r1, r5 80003e6: bd30 popge {r4, r5, pc} 80003e8: ea6f 0404 mvn.w r4, r4 80003ec: 3c1f subs r4, #31 80003ee: da1c bge.n 800042a <__adddf3+0x1d2> 80003f0: 340c adds r4, #12 80003f2: dc0e bgt.n 8000412 <__adddf3+0x1ba> 80003f4: f104 0414 add.w r4, r4, #20 80003f8: f1c4 0220 rsb r2, r4, #32 80003fc: fa20 f004 lsr.w r0, r0, r4 8000400: fa01 f302 lsl.w r3, r1, r2 8000404: ea40 0003 orr.w r0, r0, r3 8000408: fa21 f304 lsr.w r3, r1, r4 800040c: ea45 0103 orr.w r1, r5, r3 8000410: bd30 pop {r4, r5, pc} 8000412: f1c4 040c rsb r4, r4, #12 8000416: f1c4 0220 rsb r2, r4, #32 800041a: fa20 f002 lsr.w r0, r0, r2 800041e: fa01 f304 lsl.w r3, r1, r4 8000422: ea40 0003 orr.w r0, r0, r3 8000426: 4629 mov r1, r5 8000428: bd30 pop {r4, r5, pc} 800042a: fa21 f004 lsr.w r0, r1, r4 800042e: 4629 mov r1, r5 8000430: bd30 pop {r4, r5, pc} 8000432: f094 0f00 teq r4, #0 8000436: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 800043a: bf06 itte eq 800043c: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 8000440: 3401 addeq r4, #1 8000442: 3d01 subne r5, #1 8000444: e74e b.n 80002e4 <__adddf3+0x8c> 8000446: ea7f 5c64 mvns.w ip, r4, asr #21 800044a: bf18 it ne 800044c: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000450: d029 beq.n 80004a6 <__adddf3+0x24e> 8000452: ea94 0f05 teq r4, r5 8000456: bf08 it eq 8000458: ea90 0f02 teqeq r0, r2 800045c: d005 beq.n 800046a <__adddf3+0x212> 800045e: ea54 0c00 orrs.w ip, r4, r0 8000462: bf04 itt eq 8000464: 4619 moveq r1, r3 8000466: 4610 moveq r0, r2 8000468: bd30 pop {r4, r5, pc} 800046a: ea91 0f03 teq r1, r3 800046e: bf1e ittt ne 8000470: 2100 movne r1, #0 8000472: 2000 movne r0, #0 8000474: bd30 popne {r4, r5, pc} 8000476: ea5f 5c54 movs.w ip, r4, lsr #21 800047a: d105 bne.n 8000488 <__adddf3+0x230> 800047c: 0040 lsls r0, r0, #1 800047e: 4149 adcs r1, r1 8000480: bf28 it cs 8000482: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 8000486: bd30 pop {r4, r5, pc} 8000488: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 800048c: bf3c itt cc 800048e: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 8000492: bd30 popcc {r4, r5, pc} 8000494: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8000498: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 800049c: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 80004a0: f04f 0000 mov.w r0, #0 80004a4: bd30 pop {r4, r5, pc} 80004a6: ea7f 5c64 mvns.w ip, r4, asr #21 80004aa: bf1a itte ne 80004ac: 4619 movne r1, r3 80004ae: 4610 movne r0, r2 80004b0: ea7f 5c65 mvnseq.w ip, r5, asr #21 80004b4: bf1c itt ne 80004b6: 460b movne r3, r1 80004b8: 4602 movne r2, r0 80004ba: ea50 3401 orrs.w r4, r0, r1, lsl #12 80004be: bf06 itte eq 80004c0: ea52 3503 orrseq.w r5, r2, r3, lsl #12 80004c4: ea91 0f03 teqeq r1, r3 80004c8: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 80004cc: bd30 pop {r4, r5, pc} 80004ce: bf00 nop 080004d0 <__aeabi_ui2d>: 80004d0: f090 0f00 teq r0, #0 80004d4: bf04 itt eq 80004d6: 2100 moveq r1, #0 80004d8: 4770 bxeq lr 80004da: b530 push {r4, r5, lr} 80004dc: f44f 6480 mov.w r4, #1024 @ 0x400 80004e0: f104 0432 add.w r4, r4, #50 @ 0x32 80004e4: f04f 0500 mov.w r5, #0 80004e8: f04f 0100 mov.w r1, #0 80004ec: e750 b.n 8000390 <__adddf3+0x138> 80004ee: bf00 nop 080004f0 <__aeabi_i2d>: 80004f0: f090 0f00 teq r0, #0 80004f4: bf04 itt eq 80004f6: 2100 moveq r1, #0 80004f8: 4770 bxeq lr 80004fa: b530 push {r4, r5, lr} 80004fc: f44f 6480 mov.w r4, #1024 @ 0x400 8000500: f104 0432 add.w r4, r4, #50 @ 0x32 8000504: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 8000508: bf48 it mi 800050a: 4240 negmi r0, r0 800050c: f04f 0100 mov.w r1, #0 8000510: e73e b.n 8000390 <__adddf3+0x138> 8000512: bf00 nop 08000514 <__aeabi_f2d>: 8000514: 0042 lsls r2, r0, #1 8000516: ea4f 01e2 mov.w r1, r2, asr #3 800051a: ea4f 0131 mov.w r1, r1, rrx 800051e: ea4f 7002 mov.w r0, r2, lsl #28 8000522: bf1f itttt ne 8000524: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 8000528: f093 4f7f teqne r3, #4278190080 @ 0xff000000 800052c: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 8000530: 4770 bxne lr 8000532: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 8000536: bf08 it eq 8000538: 4770 bxeq lr 800053a: f093 4f7f teq r3, #4278190080 @ 0xff000000 800053e: bf04 itt eq 8000540: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 8000544: 4770 bxeq lr 8000546: b530 push {r4, r5, lr} 8000548: f44f 7460 mov.w r4, #896 @ 0x380 800054c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8000550: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 8000554: e71c b.n 8000390 <__adddf3+0x138> 8000556: bf00 nop 08000558 <__aeabi_ul2d>: 8000558: ea50 0201 orrs.w r2, r0, r1 800055c: bf08 it eq 800055e: 4770 bxeq lr 8000560: b530 push {r4, r5, lr} 8000562: f04f 0500 mov.w r5, #0 8000566: e00a b.n 800057e <__aeabi_l2d+0x16> 08000568 <__aeabi_l2d>: 8000568: ea50 0201 orrs.w r2, r0, r1 800056c: bf08 it eq 800056e: 4770 bxeq lr 8000570: b530 push {r4, r5, lr} 8000572: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 8000576: d502 bpl.n 800057e <__aeabi_l2d+0x16> 8000578: 4240 negs r0, r0 800057a: eb61 0141 sbc.w r1, r1, r1, lsl #1 800057e: f44f 6480 mov.w r4, #1024 @ 0x400 8000582: f104 0432 add.w r4, r4, #50 @ 0x32 8000586: ea5f 5c91 movs.w ip, r1, lsr #22 800058a: f43f aed8 beq.w 800033e <__adddf3+0xe6> 800058e: f04f 0203 mov.w r2, #3 8000592: ea5f 0cdc movs.w ip, ip, lsr #3 8000596: bf18 it ne 8000598: 3203 addne r2, #3 800059a: ea5f 0cdc movs.w ip, ip, lsr #3 800059e: bf18 it ne 80005a0: 3203 addne r2, #3 80005a2: eb02 02dc add.w r2, r2, ip, lsr #3 80005a6: f1c2 0320 rsb r3, r2, #32 80005aa: fa00 fc03 lsl.w ip, r0, r3 80005ae: fa20 f002 lsr.w r0, r0, r2 80005b2: fa01 fe03 lsl.w lr, r1, r3 80005b6: ea40 000e orr.w r0, r0, lr 80005ba: fa21 f102 lsr.w r1, r1, r2 80005be: 4414 add r4, r2 80005c0: e6bd b.n 800033e <__adddf3+0xe6> 80005c2: bf00 nop 080005c4 <__aeabi_dmul>: 80005c4: b570 push {r4, r5, r6, lr} 80005c6: f04f 0cff mov.w ip, #255 @ 0xff 80005ca: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 80005ce: ea1c 5411 ands.w r4, ip, r1, lsr #20 80005d2: bf1d ittte ne 80005d4: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80005d8: ea94 0f0c teqne r4, ip 80005dc: ea95 0f0c teqne r5, ip 80005e0: f000 f8de bleq 80007a0 <__aeabi_dmul+0x1dc> 80005e4: 442c add r4, r5 80005e6: ea81 0603 eor.w r6, r1, r3 80005ea: ea21 514c bic.w r1, r1, ip, lsl #21 80005ee: ea23 534c bic.w r3, r3, ip, lsl #21 80005f2: ea50 3501 orrs.w r5, r0, r1, lsl #12 80005f6: bf18 it ne 80005f8: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80005fc: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8000600: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8000604: d038 beq.n 8000678 <__aeabi_dmul+0xb4> 8000606: fba0 ce02 umull ip, lr, r0, r2 800060a: f04f 0500 mov.w r5, #0 800060e: fbe1 e502 umlal lr, r5, r1, r2 8000612: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 8000616: fbe0 e503 umlal lr, r5, r0, r3 800061a: f04f 0600 mov.w r6, #0 800061e: fbe1 5603 umlal r5, r6, r1, r3 8000622: f09c 0f00 teq ip, #0 8000626: bf18 it ne 8000628: f04e 0e01 orrne.w lr, lr, #1 800062c: f1a4 04ff sub.w r4, r4, #255 @ 0xff 8000630: f5b6 7f00 cmp.w r6, #512 @ 0x200 8000634: f564 7440 sbc.w r4, r4, #768 @ 0x300 8000638: d204 bcs.n 8000644 <__aeabi_dmul+0x80> 800063a: ea5f 0e4e movs.w lr, lr, lsl #1 800063e: 416d adcs r5, r5 8000640: eb46 0606 adc.w r6, r6, r6 8000644: ea42 21c6 orr.w r1, r2, r6, lsl #11 8000648: ea41 5155 orr.w r1, r1, r5, lsr #21 800064c: ea4f 20c5 mov.w r0, r5, lsl #11 8000650: ea40 505e orr.w r0, r0, lr, lsr #21 8000654: ea4f 2ece mov.w lr, lr, lsl #11 8000658: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 800065c: bf88 it hi 800065e: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 8000662: d81e bhi.n 80006a2 <__aeabi_dmul+0xde> 8000664: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 8000668: bf08 it eq 800066a: ea5f 0e50 movseq.w lr, r0, lsr #1 800066e: f150 0000 adcs.w r0, r0, #0 8000672: eb41 5104 adc.w r1, r1, r4, lsl #20 8000676: bd70 pop {r4, r5, r6, pc} 8000678: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 800067c: ea46 0101 orr.w r1, r6, r1 8000680: ea40 0002 orr.w r0, r0, r2 8000684: ea81 0103 eor.w r1, r1, r3 8000688: ebb4 045c subs.w r4, r4, ip, lsr #1 800068c: bfc2 ittt gt 800068e: ebd4 050c rsbsgt r5, r4, ip 8000692: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8000696: bd70 popgt {r4, r5, r6, pc} 8000698: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 800069c: f04f 0e00 mov.w lr, #0 80006a0: 3c01 subs r4, #1 80006a2: f300 80ab bgt.w 80007fc <__aeabi_dmul+0x238> 80006a6: f114 0f36 cmn.w r4, #54 @ 0x36 80006aa: bfde ittt le 80006ac: 2000 movle r0, #0 80006ae: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 80006b2: bd70 pople {r4, r5, r6, pc} 80006b4: f1c4 0400 rsb r4, r4, #0 80006b8: 3c20 subs r4, #32 80006ba: da35 bge.n 8000728 <__aeabi_dmul+0x164> 80006bc: 340c adds r4, #12 80006be: dc1b bgt.n 80006f8 <__aeabi_dmul+0x134> 80006c0: f104 0414 add.w r4, r4, #20 80006c4: f1c4 0520 rsb r5, r4, #32 80006c8: fa00 f305 lsl.w r3, r0, r5 80006cc: fa20 f004 lsr.w r0, r0, r4 80006d0: fa01 f205 lsl.w r2, r1, r5 80006d4: ea40 0002 orr.w r0, r0, r2 80006d8: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 80006dc: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 80006e0: eb10 70d3 adds.w r0, r0, r3, lsr #31 80006e4: fa21 f604 lsr.w r6, r1, r4 80006e8: eb42 0106 adc.w r1, r2, r6 80006ec: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80006f0: bf08 it eq 80006f2: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80006f6: bd70 pop {r4, r5, r6, pc} 80006f8: f1c4 040c rsb r4, r4, #12 80006fc: f1c4 0520 rsb r5, r4, #32 8000700: fa00 f304 lsl.w r3, r0, r4 8000704: fa20 f005 lsr.w r0, r0, r5 8000708: fa01 f204 lsl.w r2, r1, r4 800070c: ea40 0002 orr.w r0, r0, r2 8000710: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8000714: eb10 70d3 adds.w r0, r0, r3, lsr #31 8000718: f141 0100 adc.w r1, r1, #0 800071c: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8000720: bf08 it eq 8000722: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8000726: bd70 pop {r4, r5, r6, pc} 8000728: f1c4 0520 rsb r5, r4, #32 800072c: fa00 f205 lsl.w r2, r0, r5 8000730: ea4e 0e02 orr.w lr, lr, r2 8000734: fa20 f304 lsr.w r3, r0, r4 8000738: fa01 f205 lsl.w r2, r1, r5 800073c: ea43 0302 orr.w r3, r3, r2 8000740: fa21 f004 lsr.w r0, r1, r4 8000744: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8000748: fa21 f204 lsr.w r2, r1, r4 800074c: ea20 0002 bic.w r0, r0, r2 8000750: eb00 70d3 add.w r0, r0, r3, lsr #31 8000754: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8000758: bf08 it eq 800075a: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800075e: bd70 pop {r4, r5, r6, pc} 8000760: f094 0f00 teq r4, #0 8000764: d10f bne.n 8000786 <__aeabi_dmul+0x1c2> 8000766: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 800076a: 0040 lsls r0, r0, #1 800076c: eb41 0101 adc.w r1, r1, r1 8000770: f411 1f80 tst.w r1, #1048576 @ 0x100000 8000774: bf08 it eq 8000776: 3c01 subeq r4, #1 8000778: d0f7 beq.n 800076a <__aeabi_dmul+0x1a6> 800077a: ea41 0106 orr.w r1, r1, r6 800077e: f095 0f00 teq r5, #0 8000782: bf18 it ne 8000784: 4770 bxne lr 8000786: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 800078a: 0052 lsls r2, r2, #1 800078c: eb43 0303 adc.w r3, r3, r3 8000790: f413 1f80 tst.w r3, #1048576 @ 0x100000 8000794: bf08 it eq 8000796: 3d01 subeq r5, #1 8000798: d0f7 beq.n 800078a <__aeabi_dmul+0x1c6> 800079a: ea43 0306 orr.w r3, r3, r6 800079e: 4770 bx lr 80007a0: ea94 0f0c teq r4, ip 80007a4: ea0c 5513 and.w r5, ip, r3, lsr #20 80007a8: bf18 it ne 80007aa: ea95 0f0c teqne r5, ip 80007ae: d00c beq.n 80007ca <__aeabi_dmul+0x206> 80007b0: ea50 0641 orrs.w r6, r0, r1, lsl #1 80007b4: bf18 it ne 80007b6: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80007ba: d1d1 bne.n 8000760 <__aeabi_dmul+0x19c> 80007bc: ea81 0103 eor.w r1, r1, r3 80007c0: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80007c4: f04f 0000 mov.w r0, #0 80007c8: bd70 pop {r4, r5, r6, pc} 80007ca: ea50 0641 orrs.w r6, r0, r1, lsl #1 80007ce: bf06 itte eq 80007d0: 4610 moveq r0, r2 80007d2: 4619 moveq r1, r3 80007d4: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80007d8: d019 beq.n 800080e <__aeabi_dmul+0x24a> 80007da: ea94 0f0c teq r4, ip 80007de: d102 bne.n 80007e6 <__aeabi_dmul+0x222> 80007e0: ea50 3601 orrs.w r6, r0, r1, lsl #12 80007e4: d113 bne.n 800080e <__aeabi_dmul+0x24a> 80007e6: ea95 0f0c teq r5, ip 80007ea: d105 bne.n 80007f8 <__aeabi_dmul+0x234> 80007ec: ea52 3603 orrs.w r6, r2, r3, lsl #12 80007f0: bf1c itt ne 80007f2: 4610 movne r0, r2 80007f4: 4619 movne r1, r3 80007f6: d10a bne.n 800080e <__aeabi_dmul+0x24a> 80007f8: ea81 0103 eor.w r1, r1, r3 80007fc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8000800: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 8000804: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 8000808: f04f 0000 mov.w r0, #0 800080c: bd70 pop {r4, r5, r6, pc} 800080e: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 8000812: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 8000816: bd70 pop {r4, r5, r6, pc} 08000818 <__aeabi_ddiv>: 8000818: b570 push {r4, r5, r6, lr} 800081a: f04f 0cff mov.w ip, #255 @ 0xff 800081e: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 8000822: ea1c 5411 ands.w r4, ip, r1, lsr #20 8000826: bf1d ittte ne 8000828: ea1c 5513 andsne.w r5, ip, r3, lsr #20 800082c: ea94 0f0c teqne r4, ip 8000830: ea95 0f0c teqne r5, ip 8000834: f000 f8a7 bleq 8000986 <__aeabi_ddiv+0x16e> 8000838: eba4 0405 sub.w r4, r4, r5 800083c: ea81 0e03 eor.w lr, r1, r3 8000840: ea52 3503 orrs.w r5, r2, r3, lsl #12 8000844: ea4f 3101 mov.w r1, r1, lsl #12 8000848: f000 8088 beq.w 800095c <__aeabi_ddiv+0x144> 800084c: ea4f 3303 mov.w r3, r3, lsl #12 8000850: f04f 5580 mov.w r5, #268435456 @ 0x10000000 8000854: ea45 1313 orr.w r3, r5, r3, lsr #4 8000858: ea43 6312 orr.w r3, r3, r2, lsr #24 800085c: ea4f 2202 mov.w r2, r2, lsl #8 8000860: ea45 1511 orr.w r5, r5, r1, lsr #4 8000864: ea45 6510 orr.w r5, r5, r0, lsr #24 8000868: ea4f 2600 mov.w r6, r0, lsl #8 800086c: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000 8000870: 429d cmp r5, r3 8000872: bf08 it eq 8000874: 4296 cmpeq r6, r2 8000876: f144 04fd adc.w r4, r4, #253 @ 0xfd 800087a: f504 7440 add.w r4, r4, #768 @ 0x300 800087e: d202 bcs.n 8000886 <__aeabi_ddiv+0x6e> 8000880: 085b lsrs r3, r3, #1 8000882: ea4f 0232 mov.w r2, r2, rrx 8000886: 1ab6 subs r6, r6, r2 8000888: eb65 0503 sbc.w r5, r5, r3 800088c: 085b lsrs r3, r3, #1 800088e: ea4f 0232 mov.w r2, r2, rrx 8000892: f44f 1080 mov.w r0, #1048576 @ 0x100000 8000896: f44f 2c00 mov.w ip, #524288 @ 0x80000 800089a: ebb6 0e02 subs.w lr, r6, r2 800089e: eb75 0e03 sbcs.w lr, r5, r3 80008a2: bf22 ittt cs 80008a4: 1ab6 subcs r6, r6, r2 80008a6: 4675 movcs r5, lr 80008a8: ea40 000c orrcs.w r0, r0, ip 80008ac: 085b lsrs r3, r3, #1 80008ae: ea4f 0232 mov.w r2, r2, rrx 80008b2: ebb6 0e02 subs.w lr, r6, r2 80008b6: eb75 0e03 sbcs.w lr, r5, r3 80008ba: bf22 ittt cs 80008bc: 1ab6 subcs r6, r6, r2 80008be: 4675 movcs r5, lr 80008c0: ea40 005c orrcs.w r0, r0, ip, lsr #1 80008c4: 085b lsrs r3, r3, #1 80008c6: ea4f 0232 mov.w r2, r2, rrx 80008ca: ebb6 0e02 subs.w lr, r6, r2 80008ce: eb75 0e03 sbcs.w lr, r5, r3 80008d2: bf22 ittt cs 80008d4: 1ab6 subcs r6, r6, r2 80008d6: 4675 movcs r5, lr 80008d8: ea40 009c orrcs.w r0, r0, ip, lsr #2 80008dc: 085b lsrs r3, r3, #1 80008de: ea4f 0232 mov.w r2, r2, rrx 80008e2: ebb6 0e02 subs.w lr, r6, r2 80008e6: eb75 0e03 sbcs.w lr, r5, r3 80008ea: bf22 ittt cs 80008ec: 1ab6 subcs r6, r6, r2 80008ee: 4675 movcs r5, lr 80008f0: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80008f4: ea55 0e06 orrs.w lr, r5, r6 80008f8: d018 beq.n 800092c <__aeabi_ddiv+0x114> 80008fa: ea4f 1505 mov.w r5, r5, lsl #4 80008fe: ea45 7516 orr.w r5, r5, r6, lsr #28 8000902: ea4f 1606 mov.w r6, r6, lsl #4 8000906: ea4f 03c3 mov.w r3, r3, lsl #3 800090a: ea43 7352 orr.w r3, r3, r2, lsr #29 800090e: ea4f 02c2 mov.w r2, r2, lsl #3 8000912: ea5f 1c1c movs.w ip, ip, lsr #4 8000916: d1c0 bne.n 800089a <__aeabi_ddiv+0x82> 8000918: f411 1f80 tst.w r1, #1048576 @ 0x100000 800091c: d10b bne.n 8000936 <__aeabi_ddiv+0x11e> 800091e: ea41 0100 orr.w r1, r1, r0 8000922: f04f 0000 mov.w r0, #0 8000926: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000 800092a: e7b6 b.n 800089a <__aeabi_ddiv+0x82> 800092c: f411 1f80 tst.w r1, #1048576 @ 0x100000 8000930: bf04 itt eq 8000932: 4301 orreq r1, r0 8000934: 2000 moveq r0, #0 8000936: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 800093a: bf88 it hi 800093c: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 8000940: f63f aeaf bhi.w 80006a2 <__aeabi_dmul+0xde> 8000944: ebb5 0c03 subs.w ip, r5, r3 8000948: bf04 itt eq 800094a: ebb6 0c02 subseq.w ip, r6, r2 800094e: ea5f 0c50 movseq.w ip, r0, lsr #1 8000952: f150 0000 adcs.w r0, r0, #0 8000956: eb41 5104 adc.w r1, r1, r4, lsl #20 800095a: bd70 pop {r4, r5, r6, pc} 800095c: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000 8000960: ea4e 3111 orr.w r1, lr, r1, lsr #12 8000964: eb14 045c adds.w r4, r4, ip, lsr #1 8000968: bfc2 ittt gt 800096a: ebd4 050c rsbsgt r5, r4, ip 800096e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8000972: bd70 popgt {r4, r5, r6, pc} 8000974: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8000978: f04f 0e00 mov.w lr, #0 800097c: 3c01 subs r4, #1 800097e: e690 b.n 80006a2 <__aeabi_dmul+0xde> 8000980: ea45 0e06 orr.w lr, r5, r6 8000984: e68d b.n 80006a2 <__aeabi_dmul+0xde> 8000986: ea0c 5513 and.w r5, ip, r3, lsr #20 800098a: ea94 0f0c teq r4, ip 800098e: bf08 it eq 8000990: ea95 0f0c teqeq r5, ip 8000994: f43f af3b beq.w 800080e <__aeabi_dmul+0x24a> 8000998: ea94 0f0c teq r4, ip 800099c: d10a bne.n 80009b4 <__aeabi_ddiv+0x19c> 800099e: ea50 3401 orrs.w r4, r0, r1, lsl #12 80009a2: f47f af34 bne.w 800080e <__aeabi_dmul+0x24a> 80009a6: ea95 0f0c teq r5, ip 80009aa: f47f af25 bne.w 80007f8 <__aeabi_dmul+0x234> 80009ae: 4610 mov r0, r2 80009b0: 4619 mov r1, r3 80009b2: e72c b.n 800080e <__aeabi_dmul+0x24a> 80009b4: ea95 0f0c teq r5, ip 80009b8: d106 bne.n 80009c8 <__aeabi_ddiv+0x1b0> 80009ba: ea52 3503 orrs.w r5, r2, r3, lsl #12 80009be: f43f aefd beq.w 80007bc <__aeabi_dmul+0x1f8> 80009c2: 4610 mov r0, r2 80009c4: 4619 mov r1, r3 80009c6: e722 b.n 800080e <__aeabi_dmul+0x24a> 80009c8: ea50 0641 orrs.w r6, r0, r1, lsl #1 80009cc: bf18 it ne 80009ce: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80009d2: f47f aec5 bne.w 8000760 <__aeabi_dmul+0x19c> 80009d6: ea50 0441 orrs.w r4, r0, r1, lsl #1 80009da: f47f af0d bne.w 80007f8 <__aeabi_dmul+0x234> 80009de: ea52 0543 orrs.w r5, r2, r3, lsl #1 80009e2: f47f aeeb bne.w 80007bc <__aeabi_dmul+0x1f8> 80009e6: e712 b.n 800080e <__aeabi_dmul+0x24a> 080009e8 <__gedf2>: 80009e8: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80009ec: e006 b.n 80009fc <__cmpdf2+0x4> 80009ee: bf00 nop 080009f0 <__ledf2>: 80009f0: f04f 0c01 mov.w ip, #1 80009f4: e002 b.n 80009fc <__cmpdf2+0x4> 80009f6: bf00 nop 080009f8 <__cmpdf2>: 80009f8: f04f 0c01 mov.w ip, #1 80009fc: f84d cd04 str.w ip, [sp, #-4]! 8000a00: ea4f 0c41 mov.w ip, r1, lsl #1 8000a04: ea7f 5c6c mvns.w ip, ip, asr #21 8000a08: ea4f 0c43 mov.w ip, r3, lsl #1 8000a0c: bf18 it ne 8000a0e: ea7f 5c6c mvnsne.w ip, ip, asr #21 8000a12: d01b beq.n 8000a4c <__cmpdf2+0x54> 8000a14: b001 add sp, #4 8000a16: ea50 0c41 orrs.w ip, r0, r1, lsl #1 8000a1a: bf0c ite eq 8000a1c: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 8000a20: ea91 0f03 teqne r1, r3 8000a24: bf02 ittt eq 8000a26: ea90 0f02 teqeq r0, r2 8000a2a: 2000 moveq r0, #0 8000a2c: 4770 bxeq lr 8000a2e: f110 0f00 cmn.w r0, #0 8000a32: ea91 0f03 teq r1, r3 8000a36: bf58 it pl 8000a38: 4299 cmppl r1, r3 8000a3a: bf08 it eq 8000a3c: 4290 cmpeq r0, r2 8000a3e: bf2c ite cs 8000a40: 17d8 asrcs r0, r3, #31 8000a42: ea6f 70e3 mvncc.w r0, r3, asr #31 8000a46: f040 0001 orr.w r0, r0, #1 8000a4a: 4770 bx lr 8000a4c: ea4f 0c41 mov.w ip, r1, lsl #1 8000a50: ea7f 5c6c mvns.w ip, ip, asr #21 8000a54: d102 bne.n 8000a5c <__cmpdf2+0x64> 8000a56: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000a5a: d107 bne.n 8000a6c <__cmpdf2+0x74> 8000a5c: ea4f 0c43 mov.w ip, r3, lsl #1 8000a60: ea7f 5c6c mvns.w ip, ip, asr #21 8000a64: d1d6 bne.n 8000a14 <__cmpdf2+0x1c> 8000a66: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000a6a: d0d3 beq.n 8000a14 <__cmpdf2+0x1c> 8000a6c: f85d 0b04 ldr.w r0, [sp], #4 8000a70: 4770 bx lr 8000a72: bf00 nop 08000a74 <__aeabi_cdrcmple>: 8000a74: 4684 mov ip, r0 8000a76: 4610 mov r0, r2 8000a78: 4662 mov r2, ip 8000a7a: 468c mov ip, r1 8000a7c: 4619 mov r1, r3 8000a7e: 4663 mov r3, ip 8000a80: e000 b.n 8000a84 <__aeabi_cdcmpeq> 8000a82: bf00 nop 08000a84 <__aeabi_cdcmpeq>: 8000a84: b501 push {r0, lr} 8000a86: f7ff ffb7 bl 80009f8 <__cmpdf2> 8000a8a: 2800 cmp r0, #0 8000a8c: bf48 it mi 8000a8e: f110 0f00 cmnmi.w r0, #0 8000a92: bd01 pop {r0, pc} 08000a94 <__aeabi_dcmpeq>: 8000a94: f84d ed08 str.w lr, [sp, #-8]! 8000a98: f7ff fff4 bl 8000a84 <__aeabi_cdcmpeq> 8000a9c: bf0c ite eq 8000a9e: 2001 moveq r0, #1 8000aa0: 2000 movne r0, #0 8000aa2: f85d fb08 ldr.w pc, [sp], #8 8000aa6: bf00 nop 08000aa8 <__aeabi_dcmplt>: 8000aa8: f84d ed08 str.w lr, [sp, #-8]! 8000aac: f7ff ffea bl 8000a84 <__aeabi_cdcmpeq> 8000ab0: bf34 ite cc 8000ab2: 2001 movcc r0, #1 8000ab4: 2000 movcs r0, #0 8000ab6: f85d fb08 ldr.w pc, [sp], #8 8000aba: bf00 nop 08000abc <__aeabi_dcmple>: 8000abc: f84d ed08 str.w lr, [sp, #-8]! 8000ac0: f7ff ffe0 bl 8000a84 <__aeabi_cdcmpeq> 8000ac4: bf94 ite ls 8000ac6: 2001 movls r0, #1 8000ac8: 2000 movhi r0, #0 8000aca: f85d fb08 ldr.w pc, [sp], #8 8000ace: bf00 nop 08000ad0 <__aeabi_dcmpge>: 8000ad0: f84d ed08 str.w lr, [sp, #-8]! 8000ad4: f7ff ffce bl 8000a74 <__aeabi_cdrcmple> 8000ad8: bf94 ite ls 8000ada: 2001 movls r0, #1 8000adc: 2000 movhi r0, #0 8000ade: f85d fb08 ldr.w pc, [sp], #8 8000ae2: bf00 nop 08000ae4 <__aeabi_dcmpgt>: 8000ae4: f84d ed08 str.w lr, [sp, #-8]! 8000ae8: f7ff ffc4 bl 8000a74 <__aeabi_cdrcmple> 8000aec: bf34 ite cc 8000aee: 2001 movcc r0, #1 8000af0: 2000 movcs r0, #0 8000af2: f85d fb08 ldr.w pc, [sp], #8 8000af6: bf00 nop 08000af8 <__aeabi_dcmpun>: 8000af8: ea4f 0c41 mov.w ip, r1, lsl #1 8000afc: ea7f 5c6c mvns.w ip, ip, asr #21 8000b00: d102 bne.n 8000b08 <__aeabi_dcmpun+0x10> 8000b02: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000b06: d10a bne.n 8000b1e <__aeabi_dcmpun+0x26> 8000b08: ea4f 0c43 mov.w ip, r3, lsl #1 8000b0c: ea7f 5c6c mvns.w ip, ip, asr #21 8000b10: d102 bne.n 8000b18 <__aeabi_dcmpun+0x20> 8000b12: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000b16: d102 bne.n 8000b1e <__aeabi_dcmpun+0x26> 8000b18: f04f 0000 mov.w r0, #0 8000b1c: 4770 bx lr 8000b1e: f04f 0001 mov.w r0, #1 8000b22: 4770 bx lr 08000b24 <__aeabi_d2iz>: 8000b24: ea4f 0241 mov.w r2, r1, lsl #1 8000b28: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 8000b2c: d215 bcs.n 8000b5a <__aeabi_d2iz+0x36> 8000b2e: d511 bpl.n 8000b54 <__aeabi_d2iz+0x30> 8000b30: f46f 7378 mvn.w r3, #992 @ 0x3e0 8000b34: ebb3 5262 subs.w r2, r3, r2, asr #21 8000b38: d912 bls.n 8000b60 <__aeabi_d2iz+0x3c> 8000b3a: ea4f 23c1 mov.w r3, r1, lsl #11 8000b3e: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8000b42: ea43 5350 orr.w r3, r3, r0, lsr #21 8000b46: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8000b4a: fa23 f002 lsr.w r0, r3, r2 8000b4e: bf18 it ne 8000b50: 4240 negne r0, r0 8000b52: 4770 bx lr 8000b54: f04f 0000 mov.w r0, #0 8000b58: 4770 bx lr 8000b5a: ea50 3001 orrs.w r0, r0, r1, lsl #12 8000b5e: d105 bne.n 8000b6c <__aeabi_d2iz+0x48> 8000b60: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000 8000b64: bf08 it eq 8000b66: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 8000b6a: 4770 bx lr 8000b6c: f04f 0000 mov.w r0, #0 8000b70: 4770 bx lr 8000b72: bf00 nop 08000b74 <__aeabi_d2f>: 8000b74: ea4f 0241 mov.w r2, r1, lsl #1 8000b78: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000 8000b7c: bf24 itt cs 8000b7e: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000 8000b82: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000 8000b86: d90d bls.n 8000ba4 <__aeabi_d2f+0x30> 8000b88: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8000b8c: ea4f 02c0 mov.w r2, r0, lsl #3 8000b90: ea4c 7050 orr.w r0, ip, r0, lsr #29 8000b94: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000 8000b98: eb40 0083 adc.w r0, r0, r3, lsl #2 8000b9c: bf08 it eq 8000b9e: f020 0001 biceq.w r0, r0, #1 8000ba2: 4770 bx lr 8000ba4: f011 4f80 tst.w r1, #1073741824 @ 0x40000000 8000ba8: d121 bne.n 8000bee <__aeabi_d2f+0x7a> 8000baa: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000 8000bae: bfbc itt lt 8000bb0: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000 8000bb4: 4770 bxlt lr 8000bb6: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8000bba: ea4f 5252 mov.w r2, r2, lsr #21 8000bbe: f1c2 0218 rsb r2, r2, #24 8000bc2: f1c2 0c20 rsb ip, r2, #32 8000bc6: fa10 f30c lsls.w r3, r0, ip 8000bca: fa20 f002 lsr.w r0, r0, r2 8000bce: bf18 it ne 8000bd0: f040 0001 orrne.w r0, r0, #1 8000bd4: ea4f 23c1 mov.w r3, r1, lsl #11 8000bd8: ea4f 23d3 mov.w r3, r3, lsr #11 8000bdc: fa03 fc0c lsl.w ip, r3, ip 8000be0: ea40 000c orr.w r0, r0, ip 8000be4: fa23 f302 lsr.w r3, r3, r2 8000be8: ea4f 0343 mov.w r3, r3, lsl #1 8000bec: e7cc b.n 8000b88 <__aeabi_d2f+0x14> 8000bee: ea7f 5362 mvns.w r3, r2, asr #21 8000bf2: d107 bne.n 8000c04 <__aeabi_d2f+0x90> 8000bf4: ea50 3301 orrs.w r3, r0, r1, lsl #12 8000bf8: bf1e ittt ne 8000bfa: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000 8000bfe: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000 8000c02: 4770 bxne lr 8000c04: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000 8000c08: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8000c0c: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8000c10: 4770 bx lr 8000c12: bf00 nop 08000c14 <__aeabi_frsub>: 8000c14: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000 8000c18: e002 b.n 8000c20 <__addsf3> 8000c1a: bf00 nop 08000c1c <__aeabi_fsub>: 8000c1c: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 08000c20 <__addsf3>: 8000c20: 0042 lsls r2, r0, #1 8000c22: bf1f itttt ne 8000c24: ea5f 0341 movsne.w r3, r1, lsl #1 8000c28: ea92 0f03 teqne r2, r3 8000c2c: ea7f 6c22 mvnsne.w ip, r2, asr #24 8000c30: ea7f 6c23 mvnsne.w ip, r3, asr #24 8000c34: d06a beq.n 8000d0c <__addsf3+0xec> 8000c36: ea4f 6212 mov.w r2, r2, lsr #24 8000c3a: ebd2 6313 rsbs r3, r2, r3, lsr #24 8000c3e: bfc1 itttt gt 8000c40: 18d2 addgt r2, r2, r3 8000c42: 4041 eorgt r1, r0 8000c44: 4048 eorgt r0, r1 8000c46: 4041 eorgt r1, r0 8000c48: bfb8 it lt 8000c4a: 425b neglt r3, r3 8000c4c: 2b19 cmp r3, #25 8000c4e: bf88 it hi 8000c50: 4770 bxhi lr 8000c52: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 8000c56: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8000c5a: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000 8000c5e: bf18 it ne 8000c60: 4240 negne r0, r0 8000c62: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8000c66: f441 0100 orr.w r1, r1, #8388608 @ 0x800000 8000c6a: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000 8000c6e: bf18 it ne 8000c70: 4249 negne r1, r1 8000c72: ea92 0f03 teq r2, r3 8000c76: d03f beq.n 8000cf8 <__addsf3+0xd8> 8000c78: f1a2 0201 sub.w r2, r2, #1 8000c7c: fa41 fc03 asr.w ip, r1, r3 8000c80: eb10 000c adds.w r0, r0, ip 8000c84: f1c3 0320 rsb r3, r3, #32 8000c88: fa01 f103 lsl.w r1, r1, r3 8000c8c: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8000c90: d502 bpl.n 8000c98 <__addsf3+0x78> 8000c92: 4249 negs r1, r1 8000c94: eb60 0040 sbc.w r0, r0, r0, lsl #1 8000c98: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000 8000c9c: d313 bcc.n 8000cc6 <__addsf3+0xa6> 8000c9e: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000 8000ca2: d306 bcc.n 8000cb2 <__addsf3+0x92> 8000ca4: 0840 lsrs r0, r0, #1 8000ca6: ea4f 0131 mov.w r1, r1, rrx 8000caa: f102 0201 add.w r2, r2, #1 8000cae: 2afe cmp r2, #254 @ 0xfe 8000cb0: d251 bcs.n 8000d56 <__addsf3+0x136> 8000cb2: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000 8000cb6: eb40 50c2 adc.w r0, r0, r2, lsl #23 8000cba: bf08 it eq 8000cbc: f020 0001 biceq.w r0, r0, #1 8000cc0: ea40 0003 orr.w r0, r0, r3 8000cc4: 4770 bx lr 8000cc6: 0049 lsls r1, r1, #1 8000cc8: eb40 0000 adc.w r0, r0, r0 8000ccc: 3a01 subs r2, #1 8000cce: bf28 it cs 8000cd0: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000 8000cd4: d2ed bcs.n 8000cb2 <__addsf3+0x92> 8000cd6: fab0 fc80 clz ip, r0 8000cda: f1ac 0c08 sub.w ip, ip, #8 8000cde: ebb2 020c subs.w r2, r2, ip 8000ce2: fa00 f00c lsl.w r0, r0, ip 8000ce6: bfaa itet ge 8000ce8: eb00 50c2 addge.w r0, r0, r2, lsl #23 8000cec: 4252 neglt r2, r2 8000cee: 4318 orrge r0, r3 8000cf0: bfbc itt lt 8000cf2: 40d0 lsrlt r0, r2 8000cf4: 4318 orrlt r0, r3 8000cf6: 4770 bx lr 8000cf8: f092 0f00 teq r2, #0 8000cfc: f481 0100 eor.w r1, r1, #8388608 @ 0x800000 8000d00: bf06 itte eq 8000d02: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000 8000d06: 3201 addeq r2, #1 8000d08: 3b01 subne r3, #1 8000d0a: e7b5 b.n 8000c78 <__addsf3+0x58> 8000d0c: ea4f 0341 mov.w r3, r1, lsl #1 8000d10: ea7f 6c22 mvns.w ip, r2, asr #24 8000d14: bf18 it ne 8000d16: ea7f 6c23 mvnsne.w ip, r3, asr #24 8000d1a: d021 beq.n 8000d60 <__addsf3+0x140> 8000d1c: ea92 0f03 teq r2, r3 8000d20: d004 beq.n 8000d2c <__addsf3+0x10c> 8000d22: f092 0f00 teq r2, #0 8000d26: bf08 it eq 8000d28: 4608 moveq r0, r1 8000d2a: 4770 bx lr 8000d2c: ea90 0f01 teq r0, r1 8000d30: bf1c itt ne 8000d32: 2000 movne r0, #0 8000d34: 4770 bxne lr 8000d36: f012 4f7f tst.w r2, #4278190080 @ 0xff000000 8000d3a: d104 bne.n 8000d46 <__addsf3+0x126> 8000d3c: 0040 lsls r0, r0, #1 8000d3e: bf28 it cs 8000d40: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000 8000d44: 4770 bx lr 8000d46: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000 8000d4a: bf3c itt cc 8000d4c: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000 8000d50: 4770 bxcc lr 8000d52: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8000d56: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000 8000d5a: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8000d5e: 4770 bx lr 8000d60: ea7f 6222 mvns.w r2, r2, asr #24 8000d64: bf16 itet ne 8000d66: 4608 movne r0, r1 8000d68: ea7f 6323 mvnseq.w r3, r3, asr #24 8000d6c: 4601 movne r1, r0 8000d6e: 0242 lsls r2, r0, #9 8000d70: bf06 itte eq 8000d72: ea5f 2341 movseq.w r3, r1, lsl #9 8000d76: ea90 0f01 teqeq r0, r1 8000d7a: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000 8000d7e: 4770 bx lr 08000d80 <__aeabi_ui2f>: 8000d80: f04f 0300 mov.w r3, #0 8000d84: e004 b.n 8000d90 <__aeabi_i2f+0x8> 8000d86: bf00 nop 08000d88 <__aeabi_i2f>: 8000d88: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000 8000d8c: bf48 it mi 8000d8e: 4240 negmi r0, r0 8000d90: ea5f 0c00 movs.w ip, r0 8000d94: bf08 it eq 8000d96: 4770 bxeq lr 8000d98: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000 8000d9c: 4601 mov r1, r0 8000d9e: f04f 0000 mov.w r0, #0 8000da2: e01c b.n 8000dde <__aeabi_l2f+0x2a> 08000da4 <__aeabi_ul2f>: 8000da4: ea50 0201 orrs.w r2, r0, r1 8000da8: bf08 it eq 8000daa: 4770 bxeq lr 8000dac: f04f 0300 mov.w r3, #0 8000db0: e00a b.n 8000dc8 <__aeabi_l2f+0x14> 8000db2: bf00 nop 08000db4 <__aeabi_l2f>: 8000db4: ea50 0201 orrs.w r2, r0, r1 8000db8: bf08 it eq 8000dba: 4770 bxeq lr 8000dbc: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000 8000dc0: d502 bpl.n 8000dc8 <__aeabi_l2f+0x14> 8000dc2: 4240 negs r0, r0 8000dc4: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000dc8: ea5f 0c01 movs.w ip, r1 8000dcc: bf02 ittt eq 8000dce: 4684 moveq ip, r0 8000dd0: 4601 moveq r1, r0 8000dd2: 2000 moveq r0, #0 8000dd4: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000 8000dd8: bf08 it eq 8000dda: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000 8000dde: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 8000de2: fabc f28c clz r2, ip 8000de6: 3a08 subs r2, #8 8000de8: eba3 53c2 sub.w r3, r3, r2, lsl #23 8000dec: db10 blt.n 8000e10 <__aeabi_l2f+0x5c> 8000dee: fa01 fc02 lsl.w ip, r1, r2 8000df2: 4463 add r3, ip 8000df4: fa00 fc02 lsl.w ip, r0, r2 8000df8: f1c2 0220 rsb r2, r2, #32 8000dfc: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8000e00: fa20 f202 lsr.w r2, r0, r2 8000e04: eb43 0002 adc.w r0, r3, r2 8000e08: bf08 it eq 8000e0a: f020 0001 biceq.w r0, r0, #1 8000e0e: 4770 bx lr 8000e10: f102 0220 add.w r2, r2, #32 8000e14: fa01 fc02 lsl.w ip, r1, r2 8000e18: f1c2 0220 rsb r2, r2, #32 8000e1c: ea50 004c orrs.w r0, r0, ip, lsl #1 8000e20: fa21 f202 lsr.w r2, r1, r2 8000e24: eb43 0002 adc.w r0, r3, r2 8000e28: bf08 it eq 8000e2a: ea20 70dc biceq.w r0, r0, ip, lsr #31 8000e2e: 4770 bx lr 08000e30 <__aeabi_fmul>: 8000e30: f04f 0cff mov.w ip, #255 @ 0xff 8000e34: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8000e38: bf1e ittt ne 8000e3a: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8000e3e: ea92 0f0c teqne r2, ip 8000e42: ea93 0f0c teqne r3, ip 8000e46: d06f beq.n 8000f28 <__aeabi_fmul+0xf8> 8000e48: 441a add r2, r3 8000e4a: ea80 0c01 eor.w ip, r0, r1 8000e4e: 0240 lsls r0, r0, #9 8000e50: bf18 it ne 8000e52: ea5f 2141 movsne.w r1, r1, lsl #9 8000e56: d01e beq.n 8000e96 <__aeabi_fmul+0x66> 8000e58: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8000e5c: ea43 1050 orr.w r0, r3, r0, lsr #5 8000e60: ea43 1151 orr.w r1, r3, r1, lsr #5 8000e64: fba0 3101 umull r3, r1, r0, r1 8000e68: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8000e6c: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000 8000e70: bf3e ittt cc 8000e72: 0049 lslcc r1, r1, #1 8000e74: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 8000e78: 005b lslcc r3, r3, #1 8000e7a: ea40 0001 orr.w r0, r0, r1 8000e7e: f162 027f sbc.w r2, r2, #127 @ 0x7f 8000e82: 2afd cmp r2, #253 @ 0xfd 8000e84: d81d bhi.n 8000ec2 <__aeabi_fmul+0x92> 8000e86: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8000e8a: eb40 50c2 adc.w r0, r0, r2, lsl #23 8000e8e: bf08 it eq 8000e90: f020 0001 biceq.w r0, r0, #1 8000e94: 4770 bx lr 8000e96: f090 0f00 teq r0, #0 8000e9a: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8000e9e: bf08 it eq 8000ea0: 0249 lsleq r1, r1, #9 8000ea2: ea4c 2050 orr.w r0, ip, r0, lsr #9 8000ea6: ea40 2051 orr.w r0, r0, r1, lsr #9 8000eaa: 3a7f subs r2, #127 @ 0x7f 8000eac: bfc2 ittt gt 8000eae: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 8000eb2: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8000eb6: 4770 bxgt lr 8000eb8: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8000ebc: f04f 0300 mov.w r3, #0 8000ec0: 3a01 subs r2, #1 8000ec2: dc5d bgt.n 8000f80 <__aeabi_fmul+0x150> 8000ec4: f112 0f19 cmn.w r2, #25 8000ec8: bfdc itt le 8000eca: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000 8000ece: 4770 bxle lr 8000ed0: f1c2 0200 rsb r2, r2, #0 8000ed4: 0041 lsls r1, r0, #1 8000ed6: fa21 f102 lsr.w r1, r1, r2 8000eda: f1c2 0220 rsb r2, r2, #32 8000ede: fa00 fc02 lsl.w ip, r0, r2 8000ee2: ea5f 0031 movs.w r0, r1, rrx 8000ee6: f140 0000 adc.w r0, r0, #0 8000eea: ea53 034c orrs.w r3, r3, ip, lsl #1 8000eee: bf08 it eq 8000ef0: ea20 70dc biceq.w r0, r0, ip, lsr #31 8000ef4: 4770 bx lr 8000ef6: f092 0f00 teq r2, #0 8000efa: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8000efe: bf02 ittt eq 8000f00: 0040 lsleq r0, r0, #1 8000f02: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 8000f06: 3a01 subeq r2, #1 8000f08: d0f9 beq.n 8000efe <__aeabi_fmul+0xce> 8000f0a: ea40 000c orr.w r0, r0, ip 8000f0e: f093 0f00 teq r3, #0 8000f12: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8000f16: bf02 ittt eq 8000f18: 0049 lsleq r1, r1, #1 8000f1a: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8000f1e: 3b01 subeq r3, #1 8000f20: d0f9 beq.n 8000f16 <__aeabi_fmul+0xe6> 8000f22: ea41 010c orr.w r1, r1, ip 8000f26: e78f b.n 8000e48 <__aeabi_fmul+0x18> 8000f28: ea0c 53d1 and.w r3, ip, r1, lsr #23 8000f2c: ea92 0f0c teq r2, ip 8000f30: bf18 it ne 8000f32: ea93 0f0c teqne r3, ip 8000f36: d00a beq.n 8000f4e <__aeabi_fmul+0x11e> 8000f38: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 8000f3c: bf18 it ne 8000f3e: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 8000f42: d1d8 bne.n 8000ef6 <__aeabi_fmul+0xc6> 8000f44: ea80 0001 eor.w r0, r0, r1 8000f48: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8000f4c: 4770 bx lr 8000f4e: f090 0f00 teq r0, #0 8000f52: bf17 itett ne 8000f54: f090 4f00 teqne r0, #2147483648 @ 0x80000000 8000f58: 4608 moveq r0, r1 8000f5a: f091 0f00 teqne r1, #0 8000f5e: f091 4f00 teqne r1, #2147483648 @ 0x80000000 8000f62: d014 beq.n 8000f8e <__aeabi_fmul+0x15e> 8000f64: ea92 0f0c teq r2, ip 8000f68: d101 bne.n 8000f6e <__aeabi_fmul+0x13e> 8000f6a: 0242 lsls r2, r0, #9 8000f6c: d10f bne.n 8000f8e <__aeabi_fmul+0x15e> 8000f6e: ea93 0f0c teq r3, ip 8000f72: d103 bne.n 8000f7c <__aeabi_fmul+0x14c> 8000f74: 024b lsls r3, r1, #9 8000f76: bf18 it ne 8000f78: 4608 movne r0, r1 8000f7a: d108 bne.n 8000f8e <__aeabi_fmul+0x15e> 8000f7c: ea80 0001 eor.w r0, r0, r1 8000f80: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8000f84: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8000f88: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8000f8c: 4770 bx lr 8000f8e: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8000f92: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000 8000f96: 4770 bx lr 08000f98 <__aeabi_fdiv>: 8000f98: f04f 0cff mov.w ip, #255 @ 0xff 8000f9c: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8000fa0: bf1e ittt ne 8000fa2: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8000fa6: ea92 0f0c teqne r2, ip 8000faa: ea93 0f0c teqne r3, ip 8000fae: d069 beq.n 8001084 <__aeabi_fdiv+0xec> 8000fb0: eba2 0203 sub.w r2, r2, r3 8000fb4: ea80 0c01 eor.w ip, r0, r1 8000fb8: 0249 lsls r1, r1, #9 8000fba: ea4f 2040 mov.w r0, r0, lsl #9 8000fbe: d037 beq.n 8001030 <__aeabi_fdiv+0x98> 8000fc0: f04f 5380 mov.w r3, #268435456 @ 0x10000000 8000fc4: ea43 1111 orr.w r1, r3, r1, lsr #4 8000fc8: ea43 1310 orr.w r3, r3, r0, lsr #4 8000fcc: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8000fd0: 428b cmp r3, r1 8000fd2: bf38 it cc 8000fd4: 005b lslcc r3, r3, #1 8000fd6: f142 027d adc.w r2, r2, #125 @ 0x7d 8000fda: f44f 0c00 mov.w ip, #8388608 @ 0x800000 8000fde: 428b cmp r3, r1 8000fe0: bf24 itt cs 8000fe2: 1a5b subcs r3, r3, r1 8000fe4: ea40 000c orrcs.w r0, r0, ip 8000fe8: ebb3 0f51 cmp.w r3, r1, lsr #1 8000fec: bf24 itt cs 8000fee: eba3 0351 subcs.w r3, r3, r1, lsr #1 8000ff2: ea40 005c orrcs.w r0, r0, ip, lsr #1 8000ff6: ebb3 0f91 cmp.w r3, r1, lsr #2 8000ffa: bf24 itt cs 8000ffc: eba3 0391 subcs.w r3, r3, r1, lsr #2 8001000: ea40 009c orrcs.w r0, r0, ip, lsr #2 8001004: ebb3 0fd1 cmp.w r3, r1, lsr #3 8001008: bf24 itt cs 800100a: eba3 03d1 subcs.w r3, r3, r1, lsr #3 800100e: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8001012: 011b lsls r3, r3, #4 8001014: bf18 it ne 8001016: ea5f 1c1c movsne.w ip, ip, lsr #4 800101a: d1e0 bne.n 8000fde <__aeabi_fdiv+0x46> 800101c: 2afd cmp r2, #253 @ 0xfd 800101e: f63f af50 bhi.w 8000ec2 <__aeabi_fmul+0x92> 8001022: 428b cmp r3, r1 8001024: eb40 50c2 adc.w r0, r0, r2, lsl #23 8001028: bf08 it eq 800102a: f020 0001 biceq.w r0, r0, #1 800102e: 4770 bx lr 8001030: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8001034: ea4c 2050 orr.w r0, ip, r0, lsr #9 8001038: 327f adds r2, #127 @ 0x7f 800103a: bfc2 ittt gt 800103c: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 8001040: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8001044: 4770 bxgt lr 8001046: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 800104a: f04f 0300 mov.w r3, #0 800104e: 3a01 subs r2, #1 8001050: e737 b.n 8000ec2 <__aeabi_fmul+0x92> 8001052: f092 0f00 teq r2, #0 8001056: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 800105a: bf02 ittt eq 800105c: 0040 lsleq r0, r0, #1 800105e: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 8001062: 3a01 subeq r2, #1 8001064: d0f9 beq.n 800105a <__aeabi_fdiv+0xc2> 8001066: ea40 000c orr.w r0, r0, ip 800106a: f093 0f00 teq r3, #0 800106e: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8001072: bf02 ittt eq 8001074: 0049 lsleq r1, r1, #1 8001076: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 800107a: 3b01 subeq r3, #1 800107c: d0f9 beq.n 8001072 <__aeabi_fdiv+0xda> 800107e: ea41 010c orr.w r1, r1, ip 8001082: e795 b.n 8000fb0 <__aeabi_fdiv+0x18> 8001084: ea0c 53d1 and.w r3, ip, r1, lsr #23 8001088: ea92 0f0c teq r2, ip 800108c: d108 bne.n 80010a0 <__aeabi_fdiv+0x108> 800108e: 0242 lsls r2, r0, #9 8001090: f47f af7d bne.w 8000f8e <__aeabi_fmul+0x15e> 8001094: ea93 0f0c teq r3, ip 8001098: f47f af70 bne.w 8000f7c <__aeabi_fmul+0x14c> 800109c: 4608 mov r0, r1 800109e: e776 b.n 8000f8e <__aeabi_fmul+0x15e> 80010a0: ea93 0f0c teq r3, ip 80010a4: d104 bne.n 80010b0 <__aeabi_fdiv+0x118> 80010a6: 024b lsls r3, r1, #9 80010a8: f43f af4c beq.w 8000f44 <__aeabi_fmul+0x114> 80010ac: 4608 mov r0, r1 80010ae: e76e b.n 8000f8e <__aeabi_fmul+0x15e> 80010b0: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 80010b4: bf18 it ne 80010b6: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 80010ba: d1ca bne.n 8001052 <__aeabi_fdiv+0xba> 80010bc: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000 80010c0: f47f af5c bne.w 8000f7c <__aeabi_fmul+0x14c> 80010c4: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000 80010c8: f47f af3c bne.w 8000f44 <__aeabi_fmul+0x114> 80010cc: e75f b.n 8000f8e <__aeabi_fmul+0x15e> 80010ce: bf00 nop 080010d0 <__gesf2>: 80010d0: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80010d4: e006 b.n 80010e4 <__cmpsf2+0x4> 80010d6: bf00 nop 080010d8 <__lesf2>: 80010d8: f04f 0c01 mov.w ip, #1 80010dc: e002 b.n 80010e4 <__cmpsf2+0x4> 80010de: bf00 nop 080010e0 <__cmpsf2>: 80010e0: f04f 0c01 mov.w ip, #1 80010e4: f84d cd04 str.w ip, [sp, #-4]! 80010e8: ea4f 0240 mov.w r2, r0, lsl #1 80010ec: ea4f 0341 mov.w r3, r1, lsl #1 80010f0: ea7f 6c22 mvns.w ip, r2, asr #24 80010f4: bf18 it ne 80010f6: ea7f 6c23 mvnsne.w ip, r3, asr #24 80010fa: d011 beq.n 8001120 <__cmpsf2+0x40> 80010fc: b001 add sp, #4 80010fe: ea52 0c53 orrs.w ip, r2, r3, lsr #1 8001102: bf18 it ne 8001104: ea90 0f01 teqne r0, r1 8001108: bf58 it pl 800110a: ebb2 0003 subspl.w r0, r2, r3 800110e: bf88 it hi 8001110: 17c8 asrhi r0, r1, #31 8001112: bf38 it cc 8001114: ea6f 70e1 mvncc.w r0, r1, asr #31 8001118: bf18 it ne 800111a: f040 0001 orrne.w r0, r0, #1 800111e: 4770 bx lr 8001120: ea7f 6c22 mvns.w ip, r2, asr #24 8001124: d102 bne.n 800112c <__cmpsf2+0x4c> 8001126: ea5f 2c40 movs.w ip, r0, lsl #9 800112a: d105 bne.n 8001138 <__cmpsf2+0x58> 800112c: ea7f 6c23 mvns.w ip, r3, asr #24 8001130: d1e4 bne.n 80010fc <__cmpsf2+0x1c> 8001132: ea5f 2c41 movs.w ip, r1, lsl #9 8001136: d0e1 beq.n 80010fc <__cmpsf2+0x1c> 8001138: f85d 0b04 ldr.w r0, [sp], #4 800113c: 4770 bx lr 800113e: bf00 nop 08001140 <__aeabi_cfrcmple>: 8001140: 4684 mov ip, r0 8001142: 4608 mov r0, r1 8001144: 4661 mov r1, ip 8001146: e7ff b.n 8001148 <__aeabi_cfcmpeq> 08001148 <__aeabi_cfcmpeq>: 8001148: b50f push {r0, r1, r2, r3, lr} 800114a: f7ff ffc9 bl 80010e0 <__cmpsf2> 800114e: 2800 cmp r0, #0 8001150: bf48 it mi 8001152: f110 0f00 cmnmi.w r0, #0 8001156: bd0f pop {r0, r1, r2, r3, pc} 08001158 <__aeabi_fcmpeq>: 8001158: f84d ed08 str.w lr, [sp, #-8]! 800115c: f7ff fff4 bl 8001148 <__aeabi_cfcmpeq> 8001160: bf0c ite eq 8001162: 2001 moveq r0, #1 8001164: 2000 movne r0, #0 8001166: f85d fb08 ldr.w pc, [sp], #8 800116a: bf00 nop 0800116c <__aeabi_fcmplt>: 800116c: f84d ed08 str.w lr, [sp, #-8]! 8001170: f7ff ffea bl 8001148 <__aeabi_cfcmpeq> 8001174: bf34 ite cc 8001176: 2001 movcc r0, #1 8001178: 2000 movcs r0, #0 800117a: f85d fb08 ldr.w pc, [sp], #8 800117e: bf00 nop 08001180 <__aeabi_fcmple>: 8001180: f84d ed08 str.w lr, [sp, #-8]! 8001184: f7ff ffe0 bl 8001148 <__aeabi_cfcmpeq> 8001188: bf94 ite ls 800118a: 2001 movls r0, #1 800118c: 2000 movhi r0, #0 800118e: f85d fb08 ldr.w pc, [sp], #8 8001192: bf00 nop 08001194 <__aeabi_fcmpge>: 8001194: f84d ed08 str.w lr, [sp, #-8]! 8001198: f7ff ffd2 bl 8001140 <__aeabi_cfrcmple> 800119c: bf94 ite ls 800119e: 2001 movls r0, #1 80011a0: 2000 movhi r0, #0 80011a2: f85d fb08 ldr.w pc, [sp], #8 80011a6: bf00 nop 080011a8 <__aeabi_fcmpgt>: 80011a8: f84d ed08 str.w lr, [sp, #-8]! 80011ac: f7ff ffc8 bl 8001140 <__aeabi_cfrcmple> 80011b0: bf34 ite cc 80011b2: 2001 movcc r0, #1 80011b4: 2000 movcs r0, #0 80011b6: f85d fb08 ldr.w pc, [sp], #8 80011ba: bf00 nop 080011bc <__aeabi_f2iz>: 80011bc: ea4f 0240 mov.w r2, r0, lsl #1 80011c0: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000 80011c4: d30f bcc.n 80011e6 <__aeabi_f2iz+0x2a> 80011c6: f04f 039e mov.w r3, #158 @ 0x9e 80011ca: ebb3 6212 subs.w r2, r3, r2, lsr #24 80011ce: d90d bls.n 80011ec <__aeabi_f2iz+0x30> 80011d0: ea4f 2300 mov.w r3, r0, lsl #8 80011d4: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80011d8: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 80011dc: fa23 f002 lsr.w r0, r3, r2 80011e0: bf18 it ne 80011e2: 4240 negne r0, r0 80011e4: 4770 bx lr 80011e6: f04f 0000 mov.w r0, #0 80011ea: 4770 bx lr 80011ec: f112 0f61 cmn.w r2, #97 @ 0x61 80011f0: d101 bne.n 80011f6 <__aeabi_f2iz+0x3a> 80011f2: 0242 lsls r2, r0, #9 80011f4: d105 bne.n 8001202 <__aeabi_f2iz+0x46> 80011f6: f010 4000 ands.w r0, r0, #2147483648 @ 0x80000000 80011fa: bf08 it eq 80011fc: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 8001200: 4770 bx lr 8001202: f04f 0000 mov.w r0, #0 8001206: 4770 bx lr 08001208 <__aeabi_ldivmod>: 8001208: b97b cbnz r3, 800122a <__aeabi_ldivmod+0x22> 800120a: b972 cbnz r2, 800122a <__aeabi_ldivmod+0x22> 800120c: 2900 cmp r1, #0 800120e: bfbe ittt lt 8001210: 2000 movlt r0, #0 8001212: f04f 4100 movlt.w r1, #2147483648 @ 0x80000000 8001216: e006 blt.n 8001226 <__aeabi_ldivmod+0x1e> 8001218: bf08 it eq 800121a: 2800 cmpeq r0, #0 800121c: bf1c itt ne 800121e: f06f 4100 mvnne.w r1, #2147483648 @ 0x80000000 8001222: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8001226: f000 b9d7 b.w 80015d8 <__aeabi_idiv0> 800122a: f1ad 0c08 sub.w ip, sp, #8 800122e: e96d ce04 strd ip, lr, [sp, #-16]! 8001232: 2900 cmp r1, #0 8001234: db09 blt.n 800124a <__aeabi_ldivmod+0x42> 8001236: 2b00 cmp r3, #0 8001238: db1a blt.n 8001270 <__aeabi_ldivmod+0x68> 800123a: f000 f84d bl 80012d8 <__udivmoddi4> 800123e: f8dd e004 ldr.w lr, [sp, #4] 8001242: e9dd 2302 ldrd r2, r3, [sp, #8] 8001246: b004 add sp, #16 8001248: 4770 bx lr 800124a: 4240 negs r0, r0 800124c: eb61 0141 sbc.w r1, r1, r1, lsl #1 8001250: 2b00 cmp r3, #0 8001252: db1b blt.n 800128c <__aeabi_ldivmod+0x84> 8001254: f000 f840 bl 80012d8 <__udivmoddi4> 8001258: f8dd e004 ldr.w lr, [sp, #4] 800125c: e9dd 2302 ldrd r2, r3, [sp, #8] 8001260: b004 add sp, #16 8001262: 4240 negs r0, r0 8001264: eb61 0141 sbc.w r1, r1, r1, lsl #1 8001268: 4252 negs r2, r2 800126a: eb63 0343 sbc.w r3, r3, r3, lsl #1 800126e: 4770 bx lr 8001270: 4252 negs r2, r2 8001272: eb63 0343 sbc.w r3, r3, r3, lsl #1 8001276: f000 f82f bl 80012d8 <__udivmoddi4> 800127a: f8dd e004 ldr.w lr, [sp, #4] 800127e: e9dd 2302 ldrd r2, r3, [sp, #8] 8001282: b004 add sp, #16 8001284: 4240 negs r0, r0 8001286: eb61 0141 sbc.w r1, r1, r1, lsl #1 800128a: 4770 bx lr 800128c: 4252 negs r2, r2 800128e: eb63 0343 sbc.w r3, r3, r3, lsl #1 8001292: f000 f821 bl 80012d8 <__udivmoddi4> 8001296: f8dd e004 ldr.w lr, [sp, #4] 800129a: e9dd 2302 ldrd r2, r3, [sp, #8] 800129e: b004 add sp, #16 80012a0: 4252 negs r2, r2 80012a2: eb63 0343 sbc.w r3, r3, r3, lsl #1 80012a6: 4770 bx lr 080012a8 <__aeabi_uldivmod>: 80012a8: b953 cbnz r3, 80012c0 <__aeabi_uldivmod+0x18> 80012aa: b94a cbnz r2, 80012c0 <__aeabi_uldivmod+0x18> 80012ac: 2900 cmp r1, #0 80012ae: bf08 it eq 80012b0: 2800 cmpeq r0, #0 80012b2: bf1c itt ne 80012b4: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 80012b8: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 80012bc: f000 b98c b.w 80015d8 <__aeabi_idiv0> 80012c0: f1ad 0c08 sub.w ip, sp, #8 80012c4: e96d ce04 strd ip, lr, [sp, #-16]! 80012c8: f000 f806 bl 80012d8 <__udivmoddi4> 80012cc: f8dd e004 ldr.w lr, [sp, #4] 80012d0: e9dd 2302 ldrd r2, r3, [sp, #8] 80012d4: b004 add sp, #16 80012d6: 4770 bx lr 080012d8 <__udivmoddi4>: 80012d8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80012dc: 9d08 ldr r5, [sp, #32] 80012de: 468e mov lr, r1 80012e0: 4604 mov r4, r0 80012e2: 4688 mov r8, r1 80012e4: 2b00 cmp r3, #0 80012e6: d14a bne.n 800137e <__udivmoddi4+0xa6> 80012e8: 428a cmp r2, r1 80012ea: 4617 mov r7, r2 80012ec: d962 bls.n 80013b4 <__udivmoddi4+0xdc> 80012ee: fab2 f682 clz r6, r2 80012f2: b14e cbz r6, 8001308 <__udivmoddi4+0x30> 80012f4: f1c6 0320 rsb r3, r6, #32 80012f8: fa01 f806 lsl.w r8, r1, r6 80012fc: fa20 f303 lsr.w r3, r0, r3 8001300: 40b7 lsls r7, r6 8001302: ea43 0808 orr.w r8, r3, r8 8001306: 40b4 lsls r4, r6 8001308: ea4f 4e17 mov.w lr, r7, lsr #16 800130c: fbb8 f1fe udiv r1, r8, lr 8001310: fa1f fc87 uxth.w ip, r7 8001314: fb0e 8811 mls r8, lr, r1, r8 8001318: fb01 f20c mul.w r2, r1, ip 800131c: 0c23 lsrs r3, r4, #16 800131e: ea43 4308 orr.w r3, r3, r8, lsl #16 8001322: 429a cmp r2, r3 8001324: d909 bls.n 800133a <__udivmoddi4+0x62> 8001326: 18fb adds r3, r7, r3 8001328: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 800132c: f080 80eb bcs.w 8001506 <__udivmoddi4+0x22e> 8001330: 429a cmp r2, r3 8001332: f240 80e8 bls.w 8001506 <__udivmoddi4+0x22e> 8001336: 3902 subs r1, #2 8001338: 443b add r3, r7 800133a: 1a9a subs r2, r3, r2 800133c: fbb2 f0fe udiv r0, r2, lr 8001340: fb0e 2210 mls r2, lr, r0, r2 8001344: fb00 fc0c mul.w ip, r0, ip 8001348: b2a3 uxth r3, r4 800134a: ea43 4302 orr.w r3, r3, r2, lsl #16 800134e: 459c cmp ip, r3 8001350: d909 bls.n 8001366 <__udivmoddi4+0x8e> 8001352: 18fb adds r3, r7, r3 8001354: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 8001358: f080 80d7 bcs.w 800150a <__udivmoddi4+0x232> 800135c: 459c cmp ip, r3 800135e: f240 80d4 bls.w 800150a <__udivmoddi4+0x232> 8001362: 443b add r3, r7 8001364: 3802 subs r0, #2 8001366: ea40 4001 orr.w r0, r0, r1, lsl #16 800136a: 2100 movs r1, #0 800136c: eba3 030c sub.w r3, r3, ip 8001370: b11d cbz r5, 800137a <__udivmoddi4+0xa2> 8001372: 2200 movs r2, #0 8001374: 40f3 lsrs r3, r6 8001376: e9c5 3200 strd r3, r2, [r5] 800137a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800137e: 428b cmp r3, r1 8001380: d905 bls.n 800138e <__udivmoddi4+0xb6> 8001382: b10d cbz r5, 8001388 <__udivmoddi4+0xb0> 8001384: e9c5 0100 strd r0, r1, [r5] 8001388: 2100 movs r1, #0 800138a: 4608 mov r0, r1 800138c: e7f5 b.n 800137a <__udivmoddi4+0xa2> 800138e: fab3 f183 clz r1, r3 8001392: 2900 cmp r1, #0 8001394: d146 bne.n 8001424 <__udivmoddi4+0x14c> 8001396: 4573 cmp r3, lr 8001398: d302 bcc.n 80013a0 <__udivmoddi4+0xc8> 800139a: 4282 cmp r2, r0 800139c: f200 8108 bhi.w 80015b0 <__udivmoddi4+0x2d8> 80013a0: 1a84 subs r4, r0, r2 80013a2: eb6e 0203 sbc.w r2, lr, r3 80013a6: 2001 movs r0, #1 80013a8: 4690 mov r8, r2 80013aa: 2d00 cmp r5, #0 80013ac: d0e5 beq.n 800137a <__udivmoddi4+0xa2> 80013ae: e9c5 4800 strd r4, r8, [r5] 80013b2: e7e2 b.n 800137a <__udivmoddi4+0xa2> 80013b4: 2a00 cmp r2, #0 80013b6: f000 8091 beq.w 80014dc <__udivmoddi4+0x204> 80013ba: fab2 f682 clz r6, r2 80013be: 2e00 cmp r6, #0 80013c0: f040 80a5 bne.w 800150e <__udivmoddi4+0x236> 80013c4: 1a8a subs r2, r1, r2 80013c6: 2101 movs r1, #1 80013c8: 0c03 lsrs r3, r0, #16 80013ca: ea4f 4e17 mov.w lr, r7, lsr #16 80013ce: b280 uxth r0, r0 80013d0: b2bc uxth r4, r7 80013d2: fbb2 fcfe udiv ip, r2, lr 80013d6: fb0e 221c mls r2, lr, ip, r2 80013da: ea43 4302 orr.w r3, r3, r2, lsl #16 80013de: fb04 f20c mul.w r2, r4, ip 80013e2: 429a cmp r2, r3 80013e4: d907 bls.n 80013f6 <__udivmoddi4+0x11e> 80013e6: 18fb adds r3, r7, r3 80013e8: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 80013ec: d202 bcs.n 80013f4 <__udivmoddi4+0x11c> 80013ee: 429a cmp r2, r3 80013f0: f200 80e3 bhi.w 80015ba <__udivmoddi4+0x2e2> 80013f4: 46c4 mov ip, r8 80013f6: 1a9b subs r3, r3, r2 80013f8: fbb3 f2fe udiv r2, r3, lr 80013fc: fb0e 3312 mls r3, lr, r2, r3 8001400: fb02 f404 mul.w r4, r2, r4 8001404: ea40 4303 orr.w r3, r0, r3, lsl #16 8001408: 429c cmp r4, r3 800140a: d907 bls.n 800141c <__udivmoddi4+0x144> 800140c: 18fb adds r3, r7, r3 800140e: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 8001412: d202 bcs.n 800141a <__udivmoddi4+0x142> 8001414: 429c cmp r4, r3 8001416: f200 80cd bhi.w 80015b4 <__udivmoddi4+0x2dc> 800141a: 4602 mov r2, r0 800141c: 1b1b subs r3, r3, r4 800141e: ea42 400c orr.w r0, r2, ip, lsl #16 8001422: e7a5 b.n 8001370 <__udivmoddi4+0x98> 8001424: f1c1 0620 rsb r6, r1, #32 8001428: 408b lsls r3, r1 800142a: fa22 f706 lsr.w r7, r2, r6 800142e: 431f orrs r7, r3 8001430: fa2e fa06 lsr.w sl, lr, r6 8001434: ea4f 4917 mov.w r9, r7, lsr #16 8001438: fbba f8f9 udiv r8, sl, r9 800143c: fa0e fe01 lsl.w lr, lr, r1 8001440: fa20 f306 lsr.w r3, r0, r6 8001444: fb09 aa18 mls sl, r9, r8, sl 8001448: fa1f fc87 uxth.w ip, r7 800144c: ea43 030e orr.w r3, r3, lr 8001450: fa00 fe01 lsl.w lr, r0, r1 8001454: fb08 f00c mul.w r0, r8, ip 8001458: 0c1c lsrs r4, r3, #16 800145a: ea44 440a orr.w r4, r4, sl, lsl #16 800145e: 42a0 cmp r0, r4 8001460: fa02 f201 lsl.w r2, r2, r1 8001464: d90a bls.n 800147c <__udivmoddi4+0x1a4> 8001466: 193c adds r4, r7, r4 8001468: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff 800146c: f080 809e bcs.w 80015ac <__udivmoddi4+0x2d4> 8001470: 42a0 cmp r0, r4 8001472: f240 809b bls.w 80015ac <__udivmoddi4+0x2d4> 8001476: f1a8 0802 sub.w r8, r8, #2 800147a: 443c add r4, r7 800147c: 1a24 subs r4, r4, r0 800147e: b298 uxth r0, r3 8001480: fbb4 f3f9 udiv r3, r4, r9 8001484: fb09 4413 mls r4, r9, r3, r4 8001488: fb03 fc0c mul.w ip, r3, ip 800148c: ea40 4404 orr.w r4, r0, r4, lsl #16 8001490: 45a4 cmp ip, r4 8001492: d909 bls.n 80014a8 <__udivmoddi4+0x1d0> 8001494: 193c adds r4, r7, r4 8001496: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 800149a: f080 8085 bcs.w 80015a8 <__udivmoddi4+0x2d0> 800149e: 45a4 cmp ip, r4 80014a0: f240 8082 bls.w 80015a8 <__udivmoddi4+0x2d0> 80014a4: 3b02 subs r3, #2 80014a6: 443c add r4, r7 80014a8: ea43 4008 orr.w r0, r3, r8, lsl #16 80014ac: eba4 040c sub.w r4, r4, ip 80014b0: fba0 8c02 umull r8, ip, r0, r2 80014b4: 4564 cmp r4, ip 80014b6: 4643 mov r3, r8 80014b8: 46e1 mov r9, ip 80014ba: d364 bcc.n 8001586 <__udivmoddi4+0x2ae> 80014bc: d061 beq.n 8001582 <__udivmoddi4+0x2aa> 80014be: b15d cbz r5, 80014d8 <__udivmoddi4+0x200> 80014c0: ebbe 0203 subs.w r2, lr, r3 80014c4: eb64 0409 sbc.w r4, r4, r9 80014c8: fa04 f606 lsl.w r6, r4, r6 80014cc: fa22 f301 lsr.w r3, r2, r1 80014d0: 431e orrs r6, r3 80014d2: 40cc lsrs r4, r1 80014d4: e9c5 6400 strd r6, r4, [r5] 80014d8: 2100 movs r1, #0 80014da: e74e b.n 800137a <__udivmoddi4+0xa2> 80014dc: fbb1 fcf2 udiv ip, r1, r2 80014e0: 0c01 lsrs r1, r0, #16 80014e2: ea41 410e orr.w r1, r1, lr, lsl #16 80014e6: b280 uxth r0, r0 80014e8: ea40 4201 orr.w r2, r0, r1, lsl #16 80014ec: 463b mov r3, r7 80014ee: fbb1 f1f7 udiv r1, r1, r7 80014f2: 4638 mov r0, r7 80014f4: 463c mov r4, r7 80014f6: 46b8 mov r8, r7 80014f8: 46be mov lr, r7 80014fa: 2620 movs r6, #32 80014fc: eba2 0208 sub.w r2, r2, r8 8001500: ea41 410c orr.w r1, r1, ip, lsl #16 8001504: e765 b.n 80013d2 <__udivmoddi4+0xfa> 8001506: 4601 mov r1, r0 8001508: e717 b.n 800133a <__udivmoddi4+0x62> 800150a: 4610 mov r0, r2 800150c: e72b b.n 8001366 <__udivmoddi4+0x8e> 800150e: f1c6 0120 rsb r1, r6, #32 8001512: fa2e fc01 lsr.w ip, lr, r1 8001516: 40b7 lsls r7, r6 8001518: fa0e fe06 lsl.w lr, lr, r6 800151c: fa20 f101 lsr.w r1, r0, r1 8001520: ea41 010e orr.w r1, r1, lr 8001524: ea4f 4e17 mov.w lr, r7, lsr #16 8001528: fbbc f8fe udiv r8, ip, lr 800152c: b2bc uxth r4, r7 800152e: fb0e cc18 mls ip, lr, r8, ip 8001532: fb08 f904 mul.w r9, r8, r4 8001536: 0c0a lsrs r2, r1, #16 8001538: ea42 420c orr.w r2, r2, ip, lsl #16 800153c: 40b0 lsls r0, r6 800153e: 4591 cmp r9, r2 8001540: ea4f 4310 mov.w r3, r0, lsr #16 8001544: b280 uxth r0, r0 8001546: d93e bls.n 80015c6 <__udivmoddi4+0x2ee> 8001548: 18ba adds r2, r7, r2 800154a: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 800154e: d201 bcs.n 8001554 <__udivmoddi4+0x27c> 8001550: 4591 cmp r9, r2 8001552: d81f bhi.n 8001594 <__udivmoddi4+0x2bc> 8001554: eba2 0209 sub.w r2, r2, r9 8001558: fbb2 f9fe udiv r9, r2, lr 800155c: fb09 f804 mul.w r8, r9, r4 8001560: fb0e 2a19 mls sl, lr, r9, r2 8001564: b28a uxth r2, r1 8001566: ea42 420a orr.w r2, r2, sl, lsl #16 800156a: 4542 cmp r2, r8 800156c: d229 bcs.n 80015c2 <__udivmoddi4+0x2ea> 800156e: 18ba adds r2, r7, r2 8001570: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 8001574: d2c2 bcs.n 80014fc <__udivmoddi4+0x224> 8001576: 4542 cmp r2, r8 8001578: d2c0 bcs.n 80014fc <__udivmoddi4+0x224> 800157a: f1a9 0102 sub.w r1, r9, #2 800157e: 443a add r2, r7 8001580: e7bc b.n 80014fc <__udivmoddi4+0x224> 8001582: 45c6 cmp lr, r8 8001584: d29b bcs.n 80014be <__udivmoddi4+0x1e6> 8001586: ebb8 0302 subs.w r3, r8, r2 800158a: eb6c 0c07 sbc.w ip, ip, r7 800158e: 3801 subs r0, #1 8001590: 46e1 mov r9, ip 8001592: e794 b.n 80014be <__udivmoddi4+0x1e6> 8001594: eba7 0909 sub.w r9, r7, r9 8001598: 444a add r2, r9 800159a: fbb2 f9fe udiv r9, r2, lr 800159e: f1a8 0c02 sub.w ip, r8, #2 80015a2: fb09 f804 mul.w r8, r9, r4 80015a6: e7db b.n 8001560 <__udivmoddi4+0x288> 80015a8: 4603 mov r3, r0 80015aa: e77d b.n 80014a8 <__udivmoddi4+0x1d0> 80015ac: 46d0 mov r8, sl 80015ae: e765 b.n 800147c <__udivmoddi4+0x1a4> 80015b0: 4608 mov r0, r1 80015b2: e6fa b.n 80013aa <__udivmoddi4+0xd2> 80015b4: 443b add r3, r7 80015b6: 3a02 subs r2, #2 80015b8: e730 b.n 800141c <__udivmoddi4+0x144> 80015ba: f1ac 0c02 sub.w ip, ip, #2 80015be: 443b add r3, r7 80015c0: e719 b.n 80013f6 <__udivmoddi4+0x11e> 80015c2: 4649 mov r1, r9 80015c4: e79a b.n 80014fc <__udivmoddi4+0x224> 80015c6: eba2 0209 sub.w r2, r2, r9 80015ca: fbb2 f9fe udiv r9, r2, lr 80015ce: 46c4 mov ip, r8 80015d0: fb09 f804 mul.w r8, r9, r4 80015d4: e7c4 b.n 8001560 <__udivmoddi4+0x288> 80015d6: bf00 nop 080015d8 <__aeabi_idiv0>: 80015d8: 4770 bx lr 80015da: bf00 nop 080015dc : ADC_HandleTypeDef hadc1; /* ADC1 init function */ void MX_ADC1_Init(void) { 80015dc: b580 push {r7, lr} 80015de: b084 sub sp, #16 80015e0: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 80015e2: 1d3b adds r3, r7, #4 80015e4: 2200 movs r2, #0 80015e6: 601a str r2, [r3, #0] 80015e8: 605a str r2, [r3, #4] 80015ea: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 80015ec: 4b18 ldr r3, [pc, #96] @ (8001650 ) 80015ee: 4a19 ldr r2, [pc, #100] @ (8001654 ) 80015f0: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 80015f2: 4b17 ldr r3, [pc, #92] @ (8001650 ) 80015f4: 2200 movs r2, #0 80015f6: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = DISABLE; 80015f8: 4b15 ldr r3, [pc, #84] @ (8001650 ) 80015fa: 2200 movs r2, #0 80015fc: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 80015fe: 4b14 ldr r3, [pc, #80] @ (8001650 ) 8001600: 2200 movs r2, #0 8001602: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8001604: 4b12 ldr r3, [pc, #72] @ (8001650 ) 8001606: f44f 2260 mov.w r2, #917504 @ 0xe0000 800160a: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 800160c: 4b10 ldr r3, [pc, #64] @ (8001650 ) 800160e: 2200 movs r2, #0 8001610: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 1; 8001612: 4b0f ldr r3, [pc, #60] @ (8001650 ) 8001614: 2201 movs r2, #1 8001616: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 8001618: 480d ldr r0, [pc, #52] @ (8001650 ) 800161a: f004 f96f bl 80058fc 800161e: 4603 mov r3, r0 8001620: 2b00 cmp r3, #0 8001622: d001 beq.n 8001628 { Error_Handler(); 8001624: f003 fd10 bl 8005048 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8001628: 2308 movs r3, #8 800162a: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 800162c: 2301 movs r3, #1 800162e: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 8001630: 2300 movs r3, #0 8001632: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8001634: 1d3b adds r3, r7, #4 8001636: 4619 mov r1, r3 8001638: 4805 ldr r0, [pc, #20] @ (8001650 ) 800163a: f004 fc23 bl 8005e84 800163e: 4603 mov r3, r0 8001640: 2b00 cmp r3, #0 8001642: d001 beq.n 8001648 { Error_Handler(); 8001644: f003 fd00 bl 8005048 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 8001648: bf00 nop 800164a: 3710 adds r7, #16 800164c: 46bd mov sp, r7 800164e: bd80 pop {r7, pc} 8001650: 20000268 .word 0x20000268 8001654: 40012400 .word 0x40012400 08001658 : void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 8001658: b580 push {r7, lr} 800165a: b08a sub sp, #40 @ 0x28 800165c: af00 add r7, sp, #0 800165e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001660: f107 0318 add.w r3, r7, #24 8001664: 2200 movs r2, #0 8001666: 601a str r2, [r3, #0] 8001668: 605a str r2, [r3, #4] 800166a: 609a str r2, [r3, #8] 800166c: 60da str r2, [r3, #12] if(adcHandle->Instance==ADC1) 800166e: 687b ldr r3, [r7, #4] 8001670: 681b ldr r3, [r3, #0] 8001672: 4a1f ldr r2, [pc, #124] @ (80016f0 ) 8001674: 4293 cmp r3, r2 8001676: d137 bne.n 80016e8 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 8001678: 4b1e ldr r3, [pc, #120] @ (80016f4 ) 800167a: 699b ldr r3, [r3, #24] 800167c: 4a1d ldr r2, [pc, #116] @ (80016f4 ) 800167e: f443 7300 orr.w r3, r3, #512 @ 0x200 8001682: 6193 str r3, [r2, #24] 8001684: 4b1b ldr r3, [pc, #108] @ (80016f4 ) 8001686: 699b ldr r3, [r3, #24] 8001688: f403 7300 and.w r3, r3, #512 @ 0x200 800168c: 617b str r3, [r7, #20] 800168e: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001690: 4b18 ldr r3, [pc, #96] @ (80016f4 ) 8001692: 699b ldr r3, [r3, #24] 8001694: 4a17 ldr r2, [pc, #92] @ (80016f4 ) 8001696: f043 0304 orr.w r3, r3, #4 800169a: 6193 str r3, [r2, #24] 800169c: 4b15 ldr r3, [pc, #84] @ (80016f4 ) 800169e: 699b ldr r3, [r3, #24] 80016a0: f003 0304 and.w r3, r3, #4 80016a4: 613b str r3, [r7, #16] 80016a6: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80016a8: 4b12 ldr r3, [pc, #72] @ (80016f4 ) 80016aa: 699b ldr r3, [r3, #24] 80016ac: 4a11 ldr r2, [pc, #68] @ (80016f4 ) 80016ae: f043 0308 orr.w r3, r3, #8 80016b2: 6193 str r3, [r2, #24] 80016b4: 4b0f ldr r3, [pc, #60] @ (80016f4 ) 80016b6: 699b ldr r3, [r3, #24] 80016b8: f003 0308 and.w r3, r3, #8 80016bc: 60fb str r3, [r7, #12] 80016be: 68fb ldr r3, [r7, #12] /**ADC1 GPIO Configuration PA6 ------> ADC1_IN6 PB0 ------> ADC1_IN8 PB1 ------> ADC1_IN9 */ GPIO_InitStruct.Pin = ADC_CC1_Pin; 80016c0: 2340 movs r3, #64 @ 0x40 80016c2: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80016c4: 2303 movs r3, #3 80016c6: 61fb str r3, [r7, #28] HAL_GPIO_Init(ADC_CC1_GPIO_Port, &GPIO_InitStruct); 80016c8: f107 0318 add.w r3, r7, #24 80016cc: 4619 mov r1, r3 80016ce: 480a ldr r0, [pc, #40] @ (80016f8 ) 80016d0: f005 ff14 bl 80074fc GPIO_InitStruct.Pin = ADC_NTC1_Pin|ADC_NTC2_Pin; 80016d4: 2303 movs r3, #3 80016d6: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80016d8: 2303 movs r3, #3 80016da: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80016dc: f107 0318 add.w r3, r7, #24 80016e0: 4619 mov r1, r3 80016e2: 4806 ldr r0, [pc, #24] @ (80016fc ) 80016e4: f005 ff0a bl 80074fc /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 80016e8: bf00 nop 80016ea: 3728 adds r7, #40 @ 0x28 80016ec: 46bd mov sp, r7 80016ee: bd80 pop {r7, pc} 80016f0: 40012400 .word 0x40012400 80016f4: 40021000 .word 0x40021000 80016f8: 40010800 .word 0x40010800 80016fc: 40010c00 .word 0x40010c00 08001700 : //TODO: //TEMP READ //GBT_TEMP_SENSORS void RELAY_Write(relay_t num, uint8_t state){ 8001700: b580 push {r7, lr} 8001702: b082 sub sp, #8 8001704: af00 add r7, sp, #0 8001706: 4603 mov r3, r0 8001708: 460a mov r2, r1 800170a: 71fb strb r3, [r7, #7] 800170c: 4613 mov r3, r2 800170e: 71bb strb r3, [r7, #6] if(num==RELAY_AUX)HAL_GPIO_WritePin(RELAY_AUX_GPIO_Port, RELAY_AUX_Pin, state); 8001710: 79fb ldrb r3, [r7, #7] 8001712: 2b00 cmp r3, #0 8001714: d105 bne.n 8001722 8001716: 79bb ldrb r3, [r7, #6] 8001718: 461a mov r2, r3 800171a: 2110 movs r1, #16 800171c: 4808 ldr r0, [pc, #32] @ (8001740 ) 800171e: f006 f888 bl 8007832 if(num==RELAY_CC)HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, state); 8001722: 79fb ldrb r3, [r7, #7] 8001724: 2b01 cmp r3, #1 8001726: d106 bne.n 8001736 8001728: 79bb ldrb r3, [r7, #6] 800172a: 461a mov r2, r3 800172c: f44f 4100 mov.w r1, #32768 @ 0x8000 8001730: 4804 ldr r0, [pc, #16] @ (8001744 ) 8001732: f006 f87e bl 8007832 } 8001736: bf00 nop 8001738: 3708 adds r7, #8 800173a: 46bd mov sp, r7 800173c: bd80 pop {r7, pc} 800173e: bf00 nop 8001740: 40010c00 .word 0x40010c00 8001744: 40011800 .word 0x40011800 08001748 : // // HAL_ADC_Stop(&hadc1); // stop adc return 0; } void Init_Peripheral(){ 8001748: b580 push {r7, lr} 800174a: af00 add r7, sp, #0 HAL_ADCEx_Calibration_Start(&hadc1); 800174c: 4806 ldr r0, [pc, #24] @ (8001768 ) 800174e: f004 fd2d bl 80061ac RELAY_Write(RELAY_AUX, 0); 8001752: 2100 movs r1, #0 8001754: 2000 movs r0, #0 8001756: f7ff ffd3 bl 8001700 RELAY_Write(RELAY_CC, 1); 800175a: 2101 movs r1, #1 800175c: 2001 movs r0, #1 800175e: f7ff ffcf bl 8001700 } 8001762: bf00 nop 8001764: bd80 pop {r7, pc} 8001766: bf00 nop 8001768: 20000268 .word 0x20000268 0800176c : float pt1000_to_temperature(float resistance) { 800176c: b590 push {r4, r7, lr} 800176e: b087 sub sp, #28 8001770: af00 add r7, sp, #0 8001772: 6078 str r0, [r7, #4] // Константы для PT1000 const float R0 = 1000.0; // Сопротивление при 0 °C 8001774: 4b0c ldr r3, [pc, #48] @ (80017a8 ) 8001776: 617b str r3, [r7, #20] const float C_A = 3.9083E-3f; 8001778: 4b0c ldr r3, [pc, #48] @ (80017ac ) 800177a: 613b str r3, [r7, #16] // const float B = -5.775e-07; // Второй коэффициент (°C^-2) // // // Расчет температуры по формуле // float temperature = -A / (B - (R0 / resistance - 1) * A); float temperature = (resistance-R0) / ( R0 * C_A); 800177c: 6979 ldr r1, [r7, #20] 800177e: 6878 ldr r0, [r7, #4] 8001780: f7ff fa4c bl 8000c1c <__aeabi_fsub> 8001784: 4603 mov r3, r0 8001786: 461c mov r4, r3 8001788: 6939 ldr r1, [r7, #16] 800178a: 6978 ldr r0, [r7, #20] 800178c: f7ff fb50 bl 8000e30 <__aeabi_fmul> 8001790: 4603 mov r3, r0 8001792: 4619 mov r1, r3 8001794: 4620 mov r0, r4 8001796: f7ff fbff bl 8000f98 <__aeabi_fdiv> 800179a: 4603 mov r3, r0 800179c: 60fb str r3, [r7, #12] return temperature; 800179e: 68fb ldr r3, [r7, #12] } 80017a0: 4618 mov r0, r3 80017a2: 371c adds r7, #28 80017a4: 46bd mov sp, r7 80017a6: bd90 pop {r4, r7, pc} 80017a8: 447a0000 .word 0x447a0000 80017ac: 3b801132 .word 0x3b801132 080017b0 : float calculate_NTC_resistance(int adc_value, float Vref, float Vin, float R) { 80017b0: b5b0 push {r4, r5, r7, lr} 80017b2: b086 sub sp, #24 80017b4: af00 add r7, sp, #0 80017b6: 60f8 str r0, [r7, #12] 80017b8: 60b9 str r1, [r7, #8] 80017ba: 607a str r2, [r7, #4] 80017bc: 603b str r3, [r7, #0] // Преобразуем значение АЦП в выходное напряжение float Vout = (adc_value / 4095.0) * Vref; 80017be: 68f8 ldr r0, [r7, #12] 80017c0: f7fe fe96 bl 80004f0 <__aeabi_i2d> 80017c4: a31c add r3, pc, #112 @ (adr r3, 8001838 ) 80017c6: e9d3 2300 ldrd r2, r3, [r3] 80017ca: f7ff f825 bl 8000818 <__aeabi_ddiv> 80017ce: 4602 mov r2, r0 80017d0: 460b mov r3, r1 80017d2: 4614 mov r4, r2 80017d4: 461d mov r5, r3 80017d6: 68b8 ldr r0, [r7, #8] 80017d8: f7fe fe9c bl 8000514 <__aeabi_f2d> 80017dc: 4602 mov r2, r0 80017de: 460b mov r3, r1 80017e0: 4620 mov r0, r4 80017e2: 4629 mov r1, r5 80017e4: f7fe feee bl 80005c4 <__aeabi_dmul> 80017e8: 4602 mov r2, r0 80017ea: 460b mov r3, r1 80017ec: 4610 mov r0, r2 80017ee: 4619 mov r1, r3 80017f0: f7ff f9c0 bl 8000b74 <__aeabi_d2f> 80017f4: 4603 mov r3, r0 80017f6: 617b str r3, [r7, #20] // Проверяем, чтобы Vout не было равно Vin if (Vout >= Vin) { 80017f8: 6879 ldr r1, [r7, #4] 80017fa: 6978 ldr r0, [r7, #20] 80017fc: f7ff fcca bl 8001194 <__aeabi_fcmpge> 8001800: 4603 mov r3, r0 8001802: 2b00 cmp r3, #0 8001804: d001 beq.n 800180a return -1; // Ошибка: Vout не может быть больше или равно Vin 8001806: 4b0e ldr r3, [pc, #56] @ (8001840 ) 8001808: e010 b.n 800182c } // Вычисляем сопротивление термистора float R_NTC = R * (Vout / (Vin - Vout)); 800180a: 6979 ldr r1, [r7, #20] 800180c: 6878 ldr r0, [r7, #4] 800180e: f7ff fa05 bl 8000c1c <__aeabi_fsub> 8001812: 4603 mov r3, r0 8001814: 4619 mov r1, r3 8001816: 6978 ldr r0, [r7, #20] 8001818: f7ff fbbe bl 8000f98 <__aeabi_fdiv> 800181c: 4603 mov r3, r0 800181e: 4619 mov r1, r3 8001820: 6838 ldr r0, [r7, #0] 8001822: f7ff fb05 bl 8000e30 <__aeabi_fmul> 8001826: 4603 mov r3, r0 8001828: 613b str r3, [r7, #16] return R_NTC; 800182a: 693b ldr r3, [r7, #16] } 800182c: 4618 mov r0, r3 800182e: 3718 adds r7, #24 8001830: 46bd mov sp, r7 8001832: bdb0 pop {r4, r5, r7, pc} 8001834: f3af 8000 nop.w 8001838: 00000000 .word 0x00000000 800183c: 40affe00 .word 0x40affe00 8001840: bf800000 .word 0xbf800000 08001844 : int16_t GBT_ReadTemp(uint8_t ch){ 8001844: b580 push {r7, lr} 8001846: b088 sub sp, #32 8001848: af00 add r7, sp, #0 800184a: 4603 mov r3, r0 800184c: 71fb strb r3, [r7, #7] //TODO if(ch)ADC_Select_Channel(ADC_CHANNEL_8); 800184e: 79fb ldrb r3, [r7, #7] 8001850: 2b00 cmp r3, #0 8001852: d003 beq.n 800185c 8001854: 2008 movs r0, #8 8001856: f000 f83b bl 80018d0 800185a: e002 b.n 8001862 else ADC_Select_Channel(ADC_CHANNEL_9); 800185c: 2009 movs r0, #9 800185e: f000 f837 bl 80018d0 // Начало конверсии HAL_ADC_Start(&hadc1); 8001862: 4817 ldr r0, [pc, #92] @ (80018c0 ) 8001864: f004 f922 bl 8005aac // Ожидание окончания конверсии HAL_ADC_PollForConversion(&hadc1, HAL_MAX_DELAY); 8001868: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800186c: 4814 ldr r0, [pc, #80] @ (80018c0 ) 800186e: f004 f9f7 bl 8005c60 // Получение значения uint32_t adcValue = HAL_ADC_GetValue(&hadc1); 8001872: 4813 ldr r0, [pc, #76] @ (80018c0 ) 8001874: f004 fafa bl 8005e6c 8001878: 61f8 str r0, [r7, #28] // Остановка АЦП (по желанию) HAL_ADC_Stop(&hadc1); 800187a: 4811 ldr r0, [pc, #68] @ (80018c0 ) 800187c: f004 f9c4 bl 8005c08 if(adcValue>4000) return 20; //Термодатчик не подключен 8001880: 69fb ldr r3, [r7, #28] 8001882: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 8001886: d901 bls.n 800188c 8001888: 2314 movs r3, #20 800188a: e015 b.n 80018b8 // int adc_value = 2048; // Пример значения АЦП float Vref = 3.3; // Напряжение опорное 800188c: 4b0d ldr r3, [pc, #52] @ (80018c4 ) 800188e: 61bb str r3, [r7, #24] float Vin = 5.0; // Входное напряжение 8001890: 4b0d ldr r3, [pc, #52] @ (80018c8 ) 8001892: 617b str r3, [r7, #20] float R = 1000; // Сопротивление резистора в Омах 8001894: 4b0d ldr r3, [pc, #52] @ (80018cc ) 8001896: 613b str r3, [r7, #16] float temp = pt1000_to_temperature(calculate_NTC_resistance(adcValue, Vref, Vin, R)); 8001898: 69f8 ldr r0, [r7, #28] 800189a: 693b ldr r3, [r7, #16] 800189c: 697a ldr r2, [r7, #20] 800189e: 69b9 ldr r1, [r7, #24] 80018a0: f7ff ff86 bl 80017b0 80018a4: 4603 mov r3, r0 80018a6: 4618 mov r0, r3 80018a8: f7ff ff60 bl 800176c 80018ac: 60f8 str r0, [r7, #12] return (int16_t)temp; 80018ae: 68f8 ldr r0, [r7, #12] 80018b0: f7ff fc84 bl 80011bc <__aeabi_f2iz> 80018b4: 4603 mov r3, r0 80018b6: b21b sxth r3, r3 } 80018b8: 4618 mov r0, r3 80018ba: 3720 adds r7, #32 80018bc: 46bd mov sp, r7 80018be: bd80 pop {r7, pc} 80018c0: 20000268 .word 0x20000268 80018c4: 40533333 .word 0x40533333 80018c8: 40a00000 .word 0x40a00000 80018cc: 447a0000 .word 0x447a0000 080018d0 : void ADC_Select_Channel(uint32_t ch) { 80018d0: b580 push {r7, lr} 80018d2: b086 sub sp, #24 80018d4: af00 add r7, sp, #0 80018d6: 6078 str r0, [r7, #4] ADC_ChannelConfTypeDef conf = { 80018d8: 687b ldr r3, [r7, #4] 80018da: 60fb str r3, [r7, #12] 80018dc: 2301 movs r3, #1 80018de: 613b str r3, [r7, #16] 80018e0: 2303 movs r3, #3 80018e2: 617b str r3, [r7, #20] .Channel = ch, .Rank = 1, .SamplingTime = ADC_SAMPLETIME_28CYCLES_5, }; if (HAL_ADC_ConfigChannel(&hadc1, &conf) != HAL_OK) { 80018e4: f107 030c add.w r3, r7, #12 80018e8: 4619 mov r1, r3 80018ea: 4806 ldr r0, [pc, #24] @ (8001904 ) 80018ec: f004 faca bl 8005e84 80018f0: 4603 mov r3, r0 80018f2: 2b00 cmp r3, #0 80018f4: d001 beq.n 80018fa Error_Handler(); 80018f6: f003 fba7 bl 8005048 } } 80018fa: bf00 nop 80018fc: 3718 adds r7, #24 80018fe: 46bd mov sp, r7 8001900: bd80 pop {r7, pc} 8001902: bf00 nop 8001904: 20000268 .word 0x20000268 08001908 : uint8_t SW_GetAddr(){ 8001908: b580 push {r7, lr} 800190a: af00 add r7, sp, #0 if(!HAL_GPIO_ReadPin(ADDR_0_GPIO_Port, ADDR_0_Pin)){ 800190c: f44f 6180 mov.w r1, #1024 @ 0x400 8001910: 480f ldr r0, [pc, #60] @ (8001950 ) 8001912: f005 ff77 bl 8007804 8001916: 4603 mov r3, r0 8001918: 2b00 cmp r3, #0 800191a: d10b bne.n 8001934 if(!HAL_GPIO_ReadPin(ADDR_1_GPIO_Port, ADDR_1_Pin)){ 800191c: f44f 6100 mov.w r1, #2048 @ 0x800 8001920: 480b ldr r0, [pc, #44] @ (8001950 ) 8001922: f005 ff6f bl 8007804 8001926: 4603 mov r3, r0 8001928: 2b00 cmp r3, #0 800192a: d101 bne.n 8001930 return 0x23; 800192c: 2323 movs r3, #35 @ 0x23 800192e: e00c b.n 800194a }else{ return 0x21; 8001930: 2321 movs r3, #33 @ 0x21 8001932: e00a b.n 800194a } }else{ if(!HAL_GPIO_ReadPin(ADDR_1_GPIO_Port, ADDR_1_Pin)){ 8001934: f44f 6100 mov.w r1, #2048 @ 0x800 8001938: 4805 ldr r0, [pc, #20] @ (8001950 ) 800193a: f005 ff63 bl 8007804 800193e: 4603 mov r3, r0 8001940: 2b00 cmp r3, #0 8001942: d101 bne.n 8001948 return 0x22; 8001944: 2322 movs r3, #34 @ 0x22 8001946: e000 b.n 800194a }else{ return 0x20; 8001948: 2320 movs r3, #32 } } } 800194a: 4618 mov r0, r3 800194c: bd80 pop {r7, pc} 800194e: bf00 nop 8001950: 40011800 .word 0x40011800 08001954 : CAN_HandleTypeDef hcan1; CAN_HandleTypeDef hcan2; /* CAN1 init function */ void MX_CAN1_Init(void) { 8001954: b580 push {r7, lr} 8001956: af00 add r7, sp, #0 /* USER CODE END CAN1_Init 0 */ /* USER CODE BEGIN CAN1_Init 1 */ /* USER CODE END CAN1_Init 1 */ hcan1.Instance = CAN1; 8001958: 4b17 ldr r3, [pc, #92] @ (80019b8 ) 800195a: 4a18 ldr r2, [pc, #96] @ (80019bc ) 800195c: 601a str r2, [r3, #0] hcan1.Init.Prescaler = 8; 800195e: 4b16 ldr r3, [pc, #88] @ (80019b8 ) 8001960: 2208 movs r2, #8 8001962: 605a str r2, [r3, #4] hcan1.Init.Mode = CAN_MODE_NORMAL; 8001964: 4b14 ldr r3, [pc, #80] @ (80019b8 ) 8001966: 2200 movs r2, #0 8001968: 609a str r2, [r3, #8] hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; 800196a: 4b13 ldr r3, [pc, #76] @ (80019b8 ) 800196c: 2200 movs r2, #0 800196e: 60da str r2, [r3, #12] hcan1.Init.TimeSeg1 = CAN_BS1_15TQ; 8001970: 4b11 ldr r3, [pc, #68] @ (80019b8 ) 8001972: f44f 2260 mov.w r2, #917504 @ 0xe0000 8001976: 611a str r2, [r3, #16] hcan1.Init.TimeSeg2 = CAN_BS2_2TQ; 8001978: 4b0f ldr r3, [pc, #60] @ (80019b8 ) 800197a: f44f 1280 mov.w r2, #1048576 @ 0x100000 800197e: 615a str r2, [r3, #20] hcan1.Init.TimeTriggeredMode = DISABLE; 8001980: 4b0d ldr r3, [pc, #52] @ (80019b8 ) 8001982: 2200 movs r2, #0 8001984: 761a strb r2, [r3, #24] hcan1.Init.AutoBusOff = ENABLE; 8001986: 4b0c ldr r3, [pc, #48] @ (80019b8 ) 8001988: 2201 movs r2, #1 800198a: 765a strb r2, [r3, #25] hcan1.Init.AutoWakeUp = ENABLE; 800198c: 4b0a ldr r3, [pc, #40] @ (80019b8 ) 800198e: 2201 movs r2, #1 8001990: 769a strb r2, [r3, #26] hcan1.Init.AutoRetransmission = DISABLE; 8001992: 4b09 ldr r3, [pc, #36] @ (80019b8 ) 8001994: 2200 movs r2, #0 8001996: 76da strb r2, [r3, #27] hcan1.Init.ReceiveFifoLocked = DISABLE; 8001998: 4b07 ldr r3, [pc, #28] @ (80019b8 ) 800199a: 2200 movs r2, #0 800199c: 771a strb r2, [r3, #28] hcan1.Init.TransmitFifoPriority = ENABLE; 800199e: 4b06 ldr r3, [pc, #24] @ (80019b8 ) 80019a0: 2201 movs r2, #1 80019a2: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan1) != HAL_OK) 80019a4: 4804 ldr r0, [pc, #16] @ (80019b8 ) 80019a6: f004 fcad bl 8006304 80019aa: 4603 mov r3, r0 80019ac: 2b00 cmp r3, #0 80019ae: d001 beq.n 80019b4 { Error_Handler(); 80019b0: f003 fb4a bl 8005048 } /* USER CODE BEGIN CAN1_Init 2 */ /* USER CODE END CAN1_Init 2 */ } 80019b4: bf00 nop 80019b6: bd80 pop {r7, pc} 80019b8: 20000298 .word 0x20000298 80019bc: 40006400 .word 0x40006400 080019c0 : /* CAN2 init function */ void MX_CAN2_Init(void) { 80019c0: b580 push {r7, lr} 80019c2: af00 add r7, sp, #0 /* USER CODE END CAN2_Init 0 */ /* USER CODE BEGIN CAN2_Init 1 */ /* USER CODE END CAN2_Init 1 */ hcan2.Instance = CAN2; 80019c4: 4b17 ldr r3, [pc, #92] @ (8001a24 ) 80019c6: 4a18 ldr r2, [pc, #96] @ (8001a28 ) 80019c8: 601a str r2, [r3, #0] hcan2.Init.Prescaler = 16; 80019ca: 4b16 ldr r3, [pc, #88] @ (8001a24 ) 80019cc: 2210 movs r2, #16 80019ce: 605a str r2, [r3, #4] hcan2.Init.Mode = CAN_MODE_NORMAL; 80019d0: 4b14 ldr r3, [pc, #80] @ (8001a24 ) 80019d2: 2200 movs r2, #0 80019d4: 609a str r2, [r3, #8] hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; 80019d6: 4b13 ldr r3, [pc, #76] @ (8001a24 ) 80019d8: 2200 movs r2, #0 80019da: 60da str r2, [r3, #12] hcan2.Init.TimeSeg1 = CAN_BS1_15TQ; 80019dc: 4b11 ldr r3, [pc, #68] @ (8001a24 ) 80019de: f44f 2260 mov.w r2, #917504 @ 0xe0000 80019e2: 611a str r2, [r3, #16] hcan2.Init.TimeSeg2 = CAN_BS2_2TQ; 80019e4: 4b0f ldr r3, [pc, #60] @ (8001a24 ) 80019e6: f44f 1280 mov.w r2, #1048576 @ 0x100000 80019ea: 615a str r2, [r3, #20] hcan2.Init.TimeTriggeredMode = DISABLE; 80019ec: 4b0d ldr r3, [pc, #52] @ (8001a24 ) 80019ee: 2200 movs r2, #0 80019f0: 761a strb r2, [r3, #24] hcan2.Init.AutoBusOff = ENABLE; 80019f2: 4b0c ldr r3, [pc, #48] @ (8001a24 ) 80019f4: 2201 movs r2, #1 80019f6: 765a strb r2, [r3, #25] hcan2.Init.AutoWakeUp = ENABLE; 80019f8: 4b0a ldr r3, [pc, #40] @ (8001a24 ) 80019fa: 2201 movs r2, #1 80019fc: 769a strb r2, [r3, #26] hcan2.Init.AutoRetransmission = ENABLE; 80019fe: 4b09 ldr r3, [pc, #36] @ (8001a24 ) 8001a00: 2201 movs r2, #1 8001a02: 76da strb r2, [r3, #27] hcan2.Init.ReceiveFifoLocked = DISABLE; 8001a04: 4b07 ldr r3, [pc, #28] @ (8001a24 ) 8001a06: 2200 movs r2, #0 8001a08: 771a strb r2, [r3, #28] hcan2.Init.TransmitFifoPriority = ENABLE; 8001a0a: 4b06 ldr r3, [pc, #24] @ (8001a24 ) 8001a0c: 2201 movs r2, #1 8001a0e: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan2) != HAL_OK) 8001a10: 4804 ldr r0, [pc, #16] @ (8001a24 ) 8001a12: f004 fc77 bl 8006304 8001a16: 4603 mov r3, r0 8001a18: 2b00 cmp r3, #0 8001a1a: d001 beq.n 8001a20 { Error_Handler(); 8001a1c: f003 fb14 bl 8005048 } /* USER CODE BEGIN CAN2_Init 2 */ /* USER CODE END CAN2_Init 2 */ } 8001a20: bf00 nop 8001a22: bd80 pop {r7, pc} 8001a24: 200002c0 .word 0x200002c0 8001a28: 40006800 .word 0x40006800 08001a2c : static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0; void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) { 8001a2c: b580 push {r7, lr} 8001a2e: b08e sub sp, #56 @ 0x38 8001a30: af00 add r7, sp, #0 8001a32: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001a34: f107 0320 add.w r3, r7, #32 8001a38: 2200 movs r2, #0 8001a3a: 601a str r2, [r3, #0] 8001a3c: 605a str r2, [r3, #4] 8001a3e: 609a str r2, [r3, #8] 8001a40: 60da str r2, [r3, #12] if(canHandle->Instance==CAN1) 8001a42: 687b ldr r3, [r7, #4] 8001a44: 681b ldr r3, [r3, #0] 8001a46: 4a61 ldr r2, [pc, #388] @ (8001bcc ) 8001a48: 4293 cmp r3, r2 8001a4a: d153 bne.n 8001af4 { /* USER CODE BEGIN CAN1_MspInit 0 */ /* USER CODE END CAN1_MspInit 0 */ /* CAN1 clock enable */ HAL_RCC_CAN1_CLK_ENABLED++; 8001a4c: 4b60 ldr r3, [pc, #384] @ (8001bd0 ) 8001a4e: 681b ldr r3, [r3, #0] 8001a50: 3301 adds r3, #1 8001a52: 4a5f ldr r2, [pc, #380] @ (8001bd0 ) 8001a54: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8001a56: 4b5e ldr r3, [pc, #376] @ (8001bd0 ) 8001a58: 681b ldr r3, [r3, #0] 8001a5a: 2b01 cmp r3, #1 8001a5c: d10b bne.n 8001a76 __HAL_RCC_CAN1_CLK_ENABLE(); 8001a5e: 4b5d ldr r3, [pc, #372] @ (8001bd4 ) 8001a60: 69db ldr r3, [r3, #28] 8001a62: 4a5c ldr r2, [pc, #368] @ (8001bd4 ) 8001a64: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8001a68: 61d3 str r3, [r2, #28] 8001a6a: 4b5a ldr r3, [pc, #360] @ (8001bd4 ) 8001a6c: 69db ldr r3, [r3, #28] 8001a6e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8001a72: 61fb str r3, [r7, #28] 8001a74: 69fb ldr r3, [r7, #28] } __HAL_RCC_GPIOD_CLK_ENABLE(); 8001a76: 4b57 ldr r3, [pc, #348] @ (8001bd4 ) 8001a78: 699b ldr r3, [r3, #24] 8001a7a: 4a56 ldr r2, [pc, #344] @ (8001bd4 ) 8001a7c: f043 0320 orr.w r3, r3, #32 8001a80: 6193 str r3, [r2, #24] 8001a82: 4b54 ldr r3, [pc, #336] @ (8001bd4 ) 8001a84: 699b ldr r3, [r3, #24] 8001a86: f003 0320 and.w r3, r3, #32 8001a8a: 61bb str r3, [r7, #24] 8001a8c: 69bb ldr r3, [r7, #24] /**CAN1 GPIO Configuration PD0 ------> CAN1_RX PD1 ------> CAN1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0; 8001a8e: 2301 movs r3, #1 8001a90: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001a92: 2300 movs r3, #0 8001a94: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001a96: 2300 movs r3, #0 8001a98: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001a9a: f107 0320 add.w r3, r7, #32 8001a9e: 4619 mov r1, r3 8001aa0: 484d ldr r0, [pc, #308] @ (8001bd8 ) 8001aa2: f005 fd2b bl 80074fc GPIO_InitStruct.Pin = GPIO_PIN_1; 8001aa6: 2302 movs r3, #2 8001aa8: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001aaa: 2302 movs r3, #2 8001aac: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001aae: 2303 movs r3, #3 8001ab0: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001ab2: f107 0320 add.w r3, r7, #32 8001ab6: 4619 mov r1, r3 8001ab8: 4847 ldr r0, [pc, #284] @ (8001bd8 ) 8001aba: f005 fd1f bl 80074fc __HAL_AFIO_REMAP_CAN1_3(); 8001abe: 4b47 ldr r3, [pc, #284] @ (8001bdc ) 8001ac0: 685b ldr r3, [r3, #4] 8001ac2: 633b str r3, [r7, #48] @ 0x30 8001ac4: 6b3b ldr r3, [r7, #48] @ 0x30 8001ac6: f423 43c0 bic.w r3, r3, #24576 @ 0x6000 8001aca: 633b str r3, [r7, #48] @ 0x30 8001acc: 6b3b ldr r3, [r7, #48] @ 0x30 8001ace: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8001ad2: 633b str r3, [r7, #48] @ 0x30 8001ad4: 6b3b ldr r3, [r7, #48] @ 0x30 8001ad6: f443 43c0 orr.w r3, r3, #24576 @ 0x6000 8001ada: 633b str r3, [r7, #48] @ 0x30 8001adc: 4a3f ldr r2, [pc, #252] @ (8001bdc ) 8001ade: 6b3b ldr r3, [r7, #48] @ 0x30 8001ae0: 6053 str r3, [r2, #4] /* CAN1 interrupt Init */ HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0); 8001ae2: 2200 movs r2, #0 8001ae4: 2100 movs r1, #0 8001ae6: 2014 movs r0, #20 8001ae8: f005 fb8f bl 800720a HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn); 8001aec: 2014 movs r0, #20 8001aee: f005 fba8 bl 8007242 HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); /* USER CODE BEGIN CAN2_MspInit 1 */ /* USER CODE END CAN2_MspInit 1 */ } } 8001af2: e067 b.n 8001bc4 else if(canHandle->Instance==CAN2) 8001af4: 687b ldr r3, [r7, #4] 8001af6: 681b ldr r3, [r3, #0] 8001af8: 4a39 ldr r2, [pc, #228] @ (8001be0 ) 8001afa: 4293 cmp r3, r2 8001afc: d162 bne.n 8001bc4 __HAL_RCC_CAN2_CLK_ENABLE(); 8001afe: 4b35 ldr r3, [pc, #212] @ (8001bd4 ) 8001b00: 69db ldr r3, [r3, #28] 8001b02: 4a34 ldr r2, [pc, #208] @ (8001bd4 ) 8001b04: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 8001b08: 61d3 str r3, [r2, #28] 8001b0a: 4b32 ldr r3, [pc, #200] @ (8001bd4 ) 8001b0c: 69db ldr r3, [r3, #28] 8001b0e: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8001b12: 617b str r3, [r7, #20] 8001b14: 697b ldr r3, [r7, #20] HAL_RCC_CAN1_CLK_ENABLED++; 8001b16: 4b2e ldr r3, [pc, #184] @ (8001bd0 ) 8001b18: 681b ldr r3, [r3, #0] 8001b1a: 3301 adds r3, #1 8001b1c: 4a2c ldr r2, [pc, #176] @ (8001bd0 ) 8001b1e: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8001b20: 4b2b ldr r3, [pc, #172] @ (8001bd0 ) 8001b22: 681b ldr r3, [r3, #0] 8001b24: 2b01 cmp r3, #1 8001b26: d10b bne.n 8001b40 __HAL_RCC_CAN1_CLK_ENABLE(); 8001b28: 4b2a ldr r3, [pc, #168] @ (8001bd4 ) 8001b2a: 69db ldr r3, [r3, #28] 8001b2c: 4a29 ldr r2, [pc, #164] @ (8001bd4 ) 8001b2e: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8001b32: 61d3 str r3, [r2, #28] 8001b34: 4b27 ldr r3, [pc, #156] @ (8001bd4 ) 8001b36: 69db ldr r3, [r3, #28] 8001b38: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8001b3c: 613b str r3, [r7, #16] 8001b3e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001b40: 4b24 ldr r3, [pc, #144] @ (8001bd4 ) 8001b42: 699b ldr r3, [r3, #24] 8001b44: 4a23 ldr r2, [pc, #140] @ (8001bd4 ) 8001b46: f043 0308 orr.w r3, r3, #8 8001b4a: 6193 str r3, [r2, #24] 8001b4c: 4b21 ldr r3, [pc, #132] @ (8001bd4 ) 8001b4e: 699b ldr r3, [r3, #24] 8001b50: f003 0308 and.w r3, r3, #8 8001b54: 60fb str r3, [r7, #12] 8001b56: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_5; 8001b58: 2320 movs r3, #32 8001b5a: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001b5c: 2300 movs r3, #0 8001b5e: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001b60: 2300 movs r3, #0 8001b62: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001b64: f107 0320 add.w r3, r7, #32 8001b68: 4619 mov r1, r3 8001b6a: 481e ldr r0, [pc, #120] @ (8001be4 ) 8001b6c: f005 fcc6 bl 80074fc GPIO_InitStruct.Pin = GPIO_PIN_6; 8001b70: 2340 movs r3, #64 @ 0x40 8001b72: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001b74: 2302 movs r3, #2 8001b76: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001b78: 2303 movs r3, #3 8001b7a: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001b7c: f107 0320 add.w r3, r7, #32 8001b80: 4619 mov r1, r3 8001b82: 4818 ldr r0, [pc, #96] @ (8001be4 ) 8001b84: f005 fcba bl 80074fc __HAL_AFIO_REMAP_CAN2_ENABLE(); 8001b88: 4b14 ldr r3, [pc, #80] @ (8001bdc ) 8001b8a: 685b ldr r3, [r3, #4] 8001b8c: 637b str r3, [r7, #52] @ 0x34 8001b8e: 6b7b ldr r3, [r7, #52] @ 0x34 8001b90: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8001b94: 637b str r3, [r7, #52] @ 0x34 8001b96: 6b7b ldr r3, [r7, #52] @ 0x34 8001b98: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8001b9c: 637b str r3, [r7, #52] @ 0x34 8001b9e: 4a0f ldr r2, [pc, #60] @ (8001bdc ) 8001ba0: 6b7b ldr r3, [r7, #52] @ 0x34 8001ba2: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(CAN2_TX_IRQn, 0, 0); 8001ba4: 2200 movs r2, #0 8001ba6: 2100 movs r1, #0 8001ba8: 203f movs r0, #63 @ 0x3f 8001baa: f005 fb2e bl 800720a HAL_NVIC_EnableIRQ(CAN2_TX_IRQn); 8001bae: 203f movs r0, #63 @ 0x3f 8001bb0: f005 fb47 bl 8007242 HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 0, 0); 8001bb4: 2200 movs r2, #0 8001bb6: 2100 movs r1, #0 8001bb8: 2041 movs r0, #65 @ 0x41 8001bba: f005 fb26 bl 800720a HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); 8001bbe: 2041 movs r0, #65 @ 0x41 8001bc0: f005 fb3f bl 8007242 } 8001bc4: bf00 nop 8001bc6: 3738 adds r7, #56 @ 0x38 8001bc8: 46bd mov sp, r7 8001bca: bd80 pop {r7, pc} 8001bcc: 40006400 .word 0x40006400 8001bd0: 200002e8 .word 0x200002e8 8001bd4: 40021000 .word 0x40021000 8001bd8: 40011400 .word 0x40011400 8001bdc: 40010000 .word 0x40010000 8001be0: 40006800 .word 0x40006800 8001be4: 40010c00 .word 0x40010c00 08001be8 : extern GBT_EDCAN_Output_t GBT_EDCAN_Output; extern GBT_EDCAN_Input_t GBT_EDCAN_Input; void GBT_Init(){ 8001be8: b580 push {r7, lr} 8001bea: af00 add r7, sp, #0 GBT_State = GBT_DISABLED; 8001bec: 4b16 ldr r3, [pc, #88] @ (8001c48 ) 8001bee: 2210 movs r2, #16 8001bf0: 701a strb r2, [r3, #0] GBT_EDCAN_Input.chargeControl = CHARGING_NOT_ALLOWED; 8001bf2: 4b16 ldr r3, [pc, #88] @ (8001c4c ) 8001bf4: 2201 movs r2, #1 8001bf6: 715a strb r2, [r3, #5] GBT_Reset(); 8001bf8: f000 fe38 bl 800286c GBT_MaxLoad.maxOutputVoltage = 1000*10; 8001bfc: 4b14 ldr r3, [pc, #80] @ (8001c50 ) 8001bfe: f242 7210 movw r2, #10000 @ 0x2710 8001c02: 801a strh r2, [r3, #0] GBT_MaxLoad.minOutputVoltage = 1500; //150V 8001c04: 4b12 ldr r3, [pc, #72] @ (8001c50 ) 8001c06: f240 52dc movw r2, #1500 @ 0x5dc 8001c0a: 805a strh r2, [r3, #2] //GBT_MaxLoad[conn].maxOutputCurrent = 4000 - (GBT_MAX_CURRENT*10); //250A GBT_MaxLoad.maxOutputCurrent = 4000 - (100*10*2); //200A 8001c0c: 4b10 ldr r3, [pc, #64] @ (8001c50 ) 8001c0e: f44f 62fa mov.w r2, #2000 @ 0x7d0 8001c12: 809a strh r2, [r3, #4] GBT_MaxLoad.minOutputCurrent = 3990; //400 - 1A 8001c14: 4b0e ldr r3, [pc, #56] @ (8001c50 ) 8001c16: f640 7296 movw r2, #3990 @ 0xf96 8001c1a: 80da strh r2, [r3, #6] //TODO Linux registers GBT_ChargerInfo.chargerLocation[0] = 'R'; 8001c1c: 4b0d ldr r3, [pc, #52] @ (8001c54 ) 8001c1e: 2252 movs r2, #82 @ 0x52 8001c20: 715a strb r2, [r3, #5] GBT_ChargerInfo.chargerLocation[1] = 'U'; 8001c22: 4b0c ldr r3, [pc, #48] @ (8001c54 ) 8001c24: 2255 movs r2, #85 @ 0x55 8001c26: 719a strb r2, [r3, #6] GBT_ChargerInfo.chargerLocation[2] = 'S'; 8001c28: 4b0a ldr r3, [pc, #40] @ (8001c54 ) 8001c2a: 2253 movs r2, #83 @ 0x53 8001c2c: 71da strb r2, [r3, #7] GBT_ChargerInfo.chargerNumber = 00001; 8001c2e: 4b09 ldr r3, [pc, #36] @ (8001c54 ) 8001c30: 2200 movs r2, #0 8001c32: f042 0201 orr.w r2, r2, #1 8001c36: 705a strb r2, [r3, #1] 8001c38: 2200 movs r2, #0 8001c3a: 709a strb r2, [r3, #2] 8001c3c: 2200 movs r2, #0 8001c3e: 70da strb r2, [r3, #3] 8001c40: 2200 movs r2, #0 8001c42: 711a strb r2, [r3, #4] } 8001c44: bf00 nop 8001c46: bd80 pop {r7, pc} 8001c48: 200002ec .word 0x200002ec 8001c4c: 200004c4 .word 0x200004c4 8001c50: 20000304 .word 0x20000304 8001c54: 2000030c .word 0x2000030c 08001c58 : void GBT_ChargerTask(){ 8001c58: b5b0 push {r4, r5, r7, lr} 8001c5a: b084 sub sp, #16 8001c5c: af02 add r7, sp, #8 //GBT_LockTask(); if(j_rx.state == 2){ 8001c5e: 4ba1 ldr r3, [pc, #644] @ (8001ee4 ) 8001c60: f893 310a ldrb.w r3, [r3, #266] @ 0x10a 8001c64: 2b02 cmp r3, #2 8001c66: f040 80c1 bne.w 8001dec switch (j_rx.PGN){ 8001c6a: 4b9e ldr r3, [pc, #632] @ (8001ee4 ) 8001c6c: f8d3 3100 ldr.w r3, [r3, #256] @ 0x100 8001c70: f5b3 5f1c cmp.w r3, #9984 @ 0x2700 8001c74: d044 beq.n 8001d00 8001c76: f5b3 5f1c cmp.w r3, #9984 @ 0x2700 8001c7a: f200 80b3 bhi.w 8001de4 8001c7e: f5b3 5fe0 cmp.w r3, #7168 @ 0x1c00 8001c82: f000 80a6 beq.w 8001dd2 8001c86: f5b3 5fe0 cmp.w r3, #7168 @ 0x1c00 8001c8a: f200 80ab bhi.w 8001de4 8001c8e: f5b3 5fb8 cmp.w r3, #5888 @ 0x1700 8001c92: f000 80a2 beq.w 8001dda 8001c96: f5b3 5fb8 cmp.w r3, #5888 @ 0x1700 8001c9a: f200 80a3 bhi.w 8001de4 8001c9e: f5b3 5fb0 cmp.w r3, #5632 @ 0x1600 8001ca2: f000 809c beq.w 8001dde 8001ca6: f5b3 5fb0 cmp.w r3, #5632 @ 0x1600 8001caa: f200 809b bhi.w 8001de4 8001cae: f5b3 5fa8 cmp.w r3, #5376 @ 0x1500 8001cb2: f000 8096 beq.w 8001de2 8001cb6: f5b3 5fa8 cmp.w r3, #5376 @ 0x1500 8001cba: f200 8093 bhi.w 8001de4 8001cbe: f5b3 5f98 cmp.w r3, #4864 @ 0x1300 8001cc2: d07b beq.n 8001dbc 8001cc4: f5b3 5f98 cmp.w r3, #4864 @ 0x1300 8001cc8: f200 808c bhi.w 8001de4 8001ccc: f5b3 5f88 cmp.w r3, #4352 @ 0x1100 8001cd0: d063 beq.n 8001d9a 8001cd2: f5b3 5f88 cmp.w r3, #4352 @ 0x1100 8001cd6: f200 8085 bhi.w 8001de4 8001cda: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8001cde: d044 beq.n 8001d6a 8001ce0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8001ce4: d87e bhi.n 8001de4 8001ce6: f5b3 6f10 cmp.w r3, #2304 @ 0x900 8001cea: d02b beq.n 8001d44 8001cec: f5b3 6f10 cmp.w r3, #2304 @ 0x900 8001cf0: d878 bhi.n 8001de4 8001cf2: f5b3 7f00 cmp.w r3, #512 @ 0x200 8001cf6: d00b beq.n 8001d10 8001cf8: f5b3 6fc0 cmp.w r3, #1536 @ 0x600 8001cfc: d018 beq.n 8001d30 8001cfe: e071 b.n 8001de4 case 0x2700: //PGN BHM GBT_BHM_recv = 1; 8001d00: 4b79 ldr r3, [pc, #484] @ (8001ee8 ) 8001d02: 2201 movs r2, #1 8001d04: 701a strb r2, [r3, #0] memcpy (&GBT_MaxVoltage, j_rx.data, sizeof(GBT_MaxVoltage)); 8001d06: 4b77 ldr r3, [pc, #476] @ (8001ee4 ) 8001d08: 881a ldrh r2, [r3, #0] 8001d0a: 4b78 ldr r3, [pc, #480] @ (8001eec ) 8001d0c: 801a strh r2, [r3, #0] break; 8001d0e: e069 b.n 8001de4 case 0x0200: //PGN BRM LONG GBT_BAT_INFO_recv = 1; 8001d10: 4b77 ldr r3, [pc, #476] @ (8001ef0 ) 8001d12: 2201 movs r2, #1 8001d14: 701a strb r2, [r3, #0] memcpy (&GBT_EVInfo, j_rx.data, sizeof(GBT_EVInfo)); 8001d16: 4a77 ldr r2, [pc, #476] @ (8001ef4 ) 8001d18: 4b72 ldr r3, [pc, #456] @ (8001ee4 ) 8001d1a: 4614 mov r4, r2 8001d1c: 461d mov r5, r3 8001d1e: cd0f ldmia r5!, {r0, r1, r2, r3} 8001d20: c40f stmia r4!, {r0, r1, r2, r3} 8001d22: cd0f ldmia r5!, {r0, r1, r2, r3} 8001d24: c40f stmia r4!, {r0, r1, r2, r3} 8001d26: cd0f ldmia r5!, {r0, r1, r2, r3} 8001d28: c40f stmia r4!, {r0, r1, r2, r3} 8001d2a: 682b ldr r3, [r5, #0] 8001d2c: 7023 strb r3, [r4, #0] break; 8001d2e: e059 b.n 8001de4 case 0x0600: //PGN BCP LONG GBT_BAT_STAT_recv = 1; 8001d30: 4b71 ldr r3, [pc, #452] @ (8001ef8 ) 8001d32: 2201 movs r2, #1 8001d34: 701a strb r2, [r3, #0] memcpy (&GBT_BATStat, j_rx.data, sizeof(GBT_BATStat)); 8001d36: 4a71 ldr r2, [pc, #452] @ (8001efc ) 8001d38: 4b6a ldr r3, [pc, #424] @ (8001ee4 ) 8001d3a: 4614 mov r4, r2 8001d3c: cb0f ldmia r3, {r0, r1, r2, r3} 8001d3e: c407 stmia r4!, {r0, r1, r2} 8001d40: 7023 strb r3, [r4, #0] break; 8001d42: e04f b.n 8001de4 case 0x0900: //PGN BRO GBT_BRO_recv = 1; 8001d44: 4b6e ldr r3, [pc, #440] @ (8001f00 ) 8001d46: 2201 movs r2, #1 8001d48: 701a strb r2, [r3, #0] if(j_rx.data[0] == 0xAA) EV_ready = 1; 8001d4a: 4b66 ldr r3, [pc, #408] @ (8001ee4 ) 8001d4c: 781b ldrb r3, [r3, #0] 8001d4e: 2baa cmp r3, #170 @ 0xaa 8001d50: d103 bne.n 8001d5a 8001d52: 4b6c ldr r3, [pc, #432] @ (8001f04 ) 8001d54: 2201 movs r2, #1 8001d56: 701a strb r2, [r3, #0] 8001d58: e002 b.n 8001d60 else EV_ready = 0; 8001d5a: 4b6a ldr r3, [pc, #424] @ (8001f04 ) 8001d5c: 2200 movs r2, #0 8001d5e: 701a strb r2, [r3, #0] GBT_BRO = j_rx.data[0]; 8001d60: 4b60 ldr r3, [pc, #384] @ (8001ee4 ) 8001d62: 781a ldrb r2, [r3, #0] 8001d64: 4b68 ldr r3, [pc, #416] @ (8001f08 ) 8001d66: 701a strb r2, [r3, #0] break; 8001d68: e03c b.n 8001de4 case 0x1000: //PGN BCL //TODO: power block memcpy (&GBT_ReqPower, j_rx.data, sizeof(GBT_ReqPower)); 8001d6a: 4b68 ldr r3, [pc, #416] @ (8001f0c ) 8001d6c: 4a5d ldr r2, [pc, #372] @ (8001ee4 ) 8001d6e: e892 0003 ldmia.w r2, {r0, r1} 8001d72: 6018 str r0, [r3, #0] 8001d74: 3304 adds r3, #4 8001d76: 7019 strb r1, [r3, #0] uint16_t volt=GBT_ReqPower.requestedVoltage; 8001d78: 4b64 ldr r3, [pc, #400] @ (8001f0c ) 8001d7a: 881b ldrh r3, [r3, #0] 8001d7c: 80fb strh r3, [r7, #6] GBT_EDCAN_Output.requestedVoltage = volt; 8001d7e: 4b64 ldr r3, [pc, #400] @ (8001f10 ) 8001d80: 88fa ldrh r2, [r7, #6] 8001d82: f8a3 2001 strh.w r2, [r3, #1] uint16_t curr=4000-GBT_ReqPower.requestedCurrent; 8001d86: 4b61 ldr r3, [pc, #388] @ (8001f0c ) 8001d88: 885b ldrh r3, [r3, #2] 8001d8a: f5c3 637a rsb r3, r3, #4000 @ 0xfa0 8001d8e: 80bb strh r3, [r7, #4] GBT_EDCAN_Output.requestedCurrent = curr; 8001d90: 4b5f ldr r3, [pc, #380] @ (8001f10 ) 8001d92: 88ba ldrh r2, [r7, #4] 8001d94: f8a3 2003 strh.w r2, [r3, #3] break; 8001d98: e024 b.n 8001de4 case 0x1100: //PGN BCS //TODO memcpy (&GBT_ChargingStatus, j_rx.data, sizeof(GBT_ChargingStatus)); 8001d9a: 4b5e ldr r3, [pc, #376] @ (8001f14 ) 8001d9c: 4a51 ldr r2, [pc, #324] @ (8001ee4 ) 8001d9e: ca07 ldmia r2, {r0, r1, r2} 8001da0: c303 stmia r3!, {r0, r1} 8001da2: 701a strb r2, [r3, #0] GBT_EDCAN_Output.chargingRemainingTimeMin = GBT_ChargingStatus.estimatedRemainingChargingTime; 8001da4: 4b5b ldr r3, [pc, #364] @ (8001f14 ) 8001da6: f8b3 3007 ldrh.w r3, [r3, #7] 8001daa: b29a uxth r2, r3 8001dac: 4b58 ldr r3, [pc, #352] @ (8001f10 ) 8001dae: f8a3 2007 strh.w r2, [r3, #7] GBT_EDCAN_Output.chargingPercentage = GBT_ChargingStatus.currentChargeState; 8001db2: 4b58 ldr r3, [pc, #352] @ (8001f14 ) 8001db4: 799a ldrb r2, [r3, #6] 8001db6: 4b56 ldr r3, [pc, #344] @ (8001f10 ) 8001db8: 719a strb r2, [r3, #6] break; 8001dba: e013 b.n 8001de4 case 0x1300: //PGN BSM //TODO memcpy (&GBT_BatteryStatus, j_rx.data, sizeof(GBT_BatteryStatus)); 8001dbc: 4b56 ldr r3, [pc, #344] @ (8001f18 ) 8001dbe: 4a49 ldr r2, [pc, #292] @ (8001ee4 ) 8001dc0: e892 0003 ldmia.w r2, {r0, r1} 8001dc4: 6018 str r0, [r3, #0] 8001dc6: 3304 adds r3, #4 8001dc8: 8019 strh r1, [r3, #0] 8001dca: 3302 adds r3, #2 8001dcc: 0c0a lsrs r2, r1, #16 8001dce: 701a strb r2, [r3, #0] break; 8001dd0: e008 b.n 8001de4 // case 0x1900: //PGN BST // break; case 0x1C00: //PGN BSD //TODO SOC Voltage Temp GBT_BSD_recv = 1; 8001dd2: 4b52 ldr r3, [pc, #328] @ (8001f1c ) 8001dd4: 2201 movs r2, #1 8001dd6: 701a strb r2, [r3, #0] break; 8001dd8: e004 b.n 8001de4 break; 8001dda: bf00 nop 8001ddc: e002 b.n 8001de4 break; 8001dde: bf00 nop 8001de0: e000 b.n 8001de4 break; 8001de2: bf00 nop // break; //BSM BMV BMT BSP BST BSD BEM } j_rx.state = 0; 8001de4: 4b3f ldr r3, [pc, #252] @ (8001ee4 ) 8001de6: 2200 movs r2, #0 8001de8: f883 210a strb.w r2, [r3, #266] @ 0x10a } if((HAL_GetTick() - GBT_delay_start) < GBT_delay){ 8001dec: f003 fd58 bl 80058a0 8001df0: 4602 mov r2, r0 8001df2: 4b4b ldr r3, [pc, #300] @ (8001f20 ) 8001df4: 681b ldr r3, [r3, #0] 8001df6: 1ad2 subs r2, r2, r3 8001df8: 4b4a ldr r3, [pc, #296] @ (8001f24 ) 8001dfa: 681b ldr r3, [r3, #0] 8001dfc: 429a cmp r2, r3 8001dfe: f0c0 83aa bcc.w 8002556 //waiting }else switch (GBT_State){ 8001e02: 4b49 ldr r3, [pc, #292] @ (8001f28 ) 8001e04: 781b ldrb r3, [r3, #0] 8001e06: 3b10 subs r3, #16 8001e08: 2b15 cmp r3, #21 8001e0a: f200 838b bhi.w 8002524 8001e0e: a201 add r2, pc, #4 @ (adr r2, 8001e14 ) 8001e10: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8001e14: 08001e6d .word 0x08001e6d 8001e18: 08002525 .word 0x08002525 8001e1c: 08002525 .word 0x08002525 8001e20: 08001e89 .word 0x08001e89 8001e24: 08001e99 .word 0x08001e99 8001e28: 08001f39 .word 0x08001f39 8001e2c: 08001fb5 .word 0x08001fb5 8001e30: 080020bf .word 0x080020bf 8001e34: 080021bd .word 0x080021bd 8001e38: 080022e3 .word 0x080022e3 8001e3c: 08002525 .word 0x08002525 8001e40: 08002525 .word 0x08002525 8001e44: 08002525 .word 0x08002525 8001e48: 08002525 .word 0x08002525 8001e4c: 08002525 .word 0x08002525 8001e50: 08002525 .word 0x08002525 8001e54: 08002311 .word 0x08002311 8001e58: 0800236f .word 0x0800236f 8001e5c: 0800249d .word 0x0800249d 8001e60: 080024df .word 0x080024df 8001e64: 080024ff .word 0x080024ff 8001e68: 08002511 .word 0x08002511 case GBT_DISABLED: RELAY_Write(RELAY_AUX, 0); 8001e6c: 2100 movs r1, #0 8001e6e: 2000 movs r0, #0 8001e70: f7ff fc46 bl 8001700 if(connectorState == CONN_Charging){ 8001e74: 4b2d ldr r3, [pc, #180] @ (8001f2c ) 8001e76: 781b ldrb r3, [r3, #0] 8001e78: 2b05 cmp r3, #5 8001e7a: f040 8357 bne.w 800252c GBT_Reset(); 8001e7e: f000 fcf5 bl 800286c GBT_Start();//TODO IF protections (maybe not needed) 8001e82: f000 fd7f bl 8002984 } break; 8001e86: e351 b.n 800252c // GBT_Delay(500); // } // break; case GBT_S3_STARTED: GBT_SwitchState(GBT_S31_WAIT_BHM); 8001e88: 2014 movs r0, #20 8001e8a: f000 fb91 bl 80025b0 GBT_Delay(500); 8001e8e: f44f 70fa mov.w r0, #500 @ 0x1f4 8001e92: f000 fc3f bl 8002714 break; 8001e96: e35e b.n 8002556 case GBT_S31_WAIT_BHM: if(j_rx.state == 0) GBT_SendCHM(); 8001e98: 4b12 ldr r3, [pc, #72] @ (8001ee4 ) 8001e9a: f893 310a ldrb.w r3, [r3, #266] @ 0x10a 8001e9e: 2b00 cmp r3, #0 8001ea0: d101 bne.n 8001ea6 8001ea2: f001 fde3 bl 8003a6c GBT_Delay(250); 8001ea6: 20fa movs r0, #250 @ 0xfa 8001ea8: f000 fc34 bl 8002714 if(GBT_BHM_recv) { 8001eac: 4b0e ldr r3, [pc, #56] @ (8001ee8 ) 8001eae: 781b ldrb r3, [r3, #0] 8001eb0: 2b00 cmp r3, #0 8001eb2: d002 beq.n 8001eba GBT_SwitchState(GBT_S4_ISOTEST); 8001eb4: 2015 movs r0, #21 8001eb6: f000 fb7b bl 80025b0 } //Timeout 10S if((GBT_BHM_recv == 0) && (GBT_StateTick()>10000)) { //BHM Timeout 8001eba: 4b0b ldr r3, [pc, #44] @ (8001ee8 ) 8001ebc: 781b ldrb r3, [r3, #0] 8001ebe: 2b00 cmp r3, #0 8001ec0: f040 8336 bne.w 8002530 8001ec4: f000 fc1a bl 80026fc 8001ec8: 4603 mov r3, r0 8001eca: f242 7210 movw r2, #10000 @ 0x2710 8001ece: 4293 cmp r3, r2 8001ed0: f240 832e bls.w 8002530 GBT_Error(0xFCF0C0FC); 8001ed4: 4816 ldr r0, [pc, #88] @ (8001f30 ) 8001ed6: f000 fcad bl 8002834 EDCAN_printf(LOG_WARN, "BHM Timeout\n"); 8001eda: 4916 ldr r1, [pc, #88] @ (8001f34 ) 8001edc: 2004 movs r0, #4 8001ede: f002 ff4b bl 8004d78 } break; 8001ee2: e325 b.n 8002530 8001ee4: 200004cc .word 0x200004cc 8001ee8: 200002ff .word 0x200002ff 8001eec: 20000314 .word 0x20000314 8001ef0: 200002fc .word 0x200002fc 8001ef4: 20000318 .word 0x20000318 8001ef8: 200002fd .word 0x200002fd 8001efc: 2000034c .word 0x2000034c 8001f00: 200002fe .word 0x200002fe 8001f04: 20000301 .word 0x20000301 8001f08: 20000390 .word 0x20000390 8001f0c: 2000035c .word 0x2000035c 8001f10: 200004b4 .word 0x200004b4 8001f14: 2000036c .word 0x2000036c 8001f18: 20000378 .word 0x20000378 8001f1c: 20000300 .word 0x20000300 8001f20: 200002f4 .word 0x200002f4 8001f24: 200002f8 .word 0x200002f8 8001f28: 200002ec .word 0x200002ec 8001f2c: 200003a1 .word 0x200003a1 8001f30: fcf0c0fc .word 0xfcf0c0fc 8001f34: 0800d6e8 .word 0x0800d6e8 case GBT_S4_ISOTEST: if(j_rx.state == 0) GBT_SendCHM(); 8001f38: 4bb7 ldr r3, [pc, #732] @ (8002218 ) 8001f3a: f893 310a ldrb.w r3, [r3, #266] @ 0x10a 8001f3e: 2b00 cmp r3, #0 8001f40: d101 bne.n 8001f46 8001f42: f001 fd93 bl 8003a6c GBT_Delay(250); 8001f46: 20fa movs r0, #250 @ 0xfa 8001f48: f000 fbe4 bl 8002714 GBT_EDCAN_Output.requestedVoltage = GBT_MaxVoltage.maxOutputVoltage; 8001f4c: 4bb3 ldr r3, [pc, #716] @ (800221c ) 8001f4e: 881a ldrh r2, [r3, #0] 8001f50: 4bb3 ldr r3, [pc, #716] @ (8002220 ) 8001f52: f8a3 2001 strh.w r2, [r3, #1] GBT_EDCAN_Output.requestedCurrent = 10; // 1A max 8001f56: 4bb2 ldr r3, [pc, #712] @ (8002220 ) 8001f58: 2200 movs r2, #0 8001f5a: f042 020a orr.w r2, r2, #10 8001f5e: 70da strb r2, [r3, #3] 8001f60: 2200 movs r2, #0 8001f62: 711a strb r2, [r3, #4] GBT_EDCAN_Output.enablePSU = 1; 8001f64: 4bae ldr r3, [pc, #696] @ (8002220 ) 8001f66: 2201 movs r2, #1 8001f68: 701a strb r2, [r3, #0] //TODO: Isolation test trigger if(GBT_EDCAN_Input.chargingError != CONN_NO_ERROR){ 8001f6a: 4bae ldr r3, [pc, #696] @ (8002224 ) 8001f6c: 799b ldrb r3, [r3, #6] 8001f6e: 2b00 cmp r3, #0 8001f70: d003 beq.n 8001f7a GBT_StopEVSE(GBT_CST_OTHERFALUT); 8001f72: f24f 40f0 movw r0, #62704 @ 0xf4f0 8001f76: f000 fc0d bl 8002794 } if(GBT_StateTick()>5000){ 8001f7a: f000 fbbf bl 80026fc 8001f7e: 4603 mov r3, r0 8001f80: f241 3288 movw r2, #5000 @ 0x1388 8001f84: 4293 cmp r3, r2 8001f86: f240 82d5 bls.w 8002534 GBT_SwitchState(GBT_S5_BAT_INFO); 8001f8a: 2016 movs r0, #22 8001f8c: f000 fb10 bl 80025b0 GBT_EDCAN_Output.requestedVoltage = 50; 8001f90: 4ba3 ldr r3, [pc, #652] @ (8002220 ) 8001f92: 2200 movs r2, #0 8001f94: f042 0232 orr.w r2, r2, #50 @ 0x32 8001f98: 705a strb r2, [r3, #1] 8001f9a: 2200 movs r2, #0 8001f9c: 709a strb r2, [r3, #2] GBT_EDCAN_Output.requestedCurrent = 10; // 1A max 8001f9e: 4ba0 ldr r3, [pc, #640] @ (8002220 ) 8001fa0: 2200 movs r2, #0 8001fa2: f042 020a orr.w r2, r2, #10 8001fa6: 70da strb r2, [r3, #3] 8001fa8: 2200 movs r2, #0 8001faa: 711a strb r2, [r3, #4] GBT_EDCAN_Output.enablePSU = 0; 8001fac: 4b9c ldr r3, [pc, #624] @ (8002220 ) 8001fae: 2200 movs r2, #0 8001fb0: 701a strb r2, [r3, #0] } break; 8001fb2: e2bf b.n 8002534 case GBT_S5_BAT_INFO: if(j_rx.state == 0) GBT_SendCRM(0x00); 8001fb4: 4b98 ldr r3, [pc, #608] @ (8002218 ) 8001fb6: f893 310a ldrb.w r3, [r3, #266] @ 0x10a 8001fba: 2b00 cmp r3, #0 8001fbc: d102 bne.n 8001fc4 8001fbe: 2000 movs r0, #0 8001fc0: f001 fd68 bl 8003a94 GBT_Delay(250); 8001fc4: 20fa movs r0, #250 @ 0xfa 8001fc6: f000 fba5 bl 8002714 if(GBT_BAT_INFO_recv){ //BRM 8001fca: 4b97 ldr r3, [pc, #604] @ (8002228 ) 8001fcc: 781b ldrb r3, [r3, #0] 8001fce: 2b00 cmp r3, #0 8001fd0: d060 beq.n 8002094 //Got battery info GBT_SwitchState(GBT_S6_BAT_STAT); 8001fd2: 2017 movs r0, #23 8001fd4: f000 faec bl 80025b0 EDCAN_printf(LOG_INFO, "EV info:\n"); 8001fd8: 4994 ldr r1, [pc, #592] @ (800222c ) 8001fda: 2006 movs r0, #6 8001fdc: f002 fecc bl 8004d78 EDCAN_printf(LOG_INFO, "GBT_ver V%d.%d%d\n",GBT_EVInfo.version[0],GBT_EVInfo.version[1],GBT_EVInfo.version[2]); 8001fe0: 4b93 ldr r3, [pc, #588] @ (8002230 ) 8001fe2: 781b ldrb r3, [r3, #0] 8001fe4: 461a mov r2, r3 8001fe6: 4b92 ldr r3, [pc, #584] @ (8002230 ) 8001fe8: 785b ldrb r3, [r3, #1] 8001fea: 4619 mov r1, r3 8001fec: 4b90 ldr r3, [pc, #576] @ (8002230 ) 8001fee: 789b ldrb r3, [r3, #2] 8001ff0: 9300 str r3, [sp, #0] 8001ff2: 460b mov r3, r1 8001ff4: 498f ldr r1, [pc, #572] @ (8002234 ) 8001ff6: 2006 movs r0, #6 8001ff8: f002 febe bl 8004d78 EDCAN_printf(LOG_INFO, "Battery type: %d\n",GBT_EVInfo.batteryType); 8001ffc: 4b8c ldr r3, [pc, #560] @ (8002230 ) 8001ffe: 78db ldrb r3, [r3, #3] 8002000: 461a mov r2, r3 8002002: 498d ldr r1, [pc, #564] @ (8002238 ) 8002004: 2006 movs r0, #6 8002006: f002 feb7 bl 8004d78 EDCAN_printf(LOG_INFO, "Battery capacity: %d\n", GBT_EVInfo.batteryCapacity); // 0.1Ah/bit 800200a: 4b89 ldr r3, [pc, #548] @ (8002230 ) 800200c: 889b ldrh r3, [r3, #4] 800200e: 461a mov r2, r3 8002010: 498a ldr r1, [pc, #552] @ (800223c ) 8002012: 2006 movs r0, #6 8002014: f002 feb0 bl 8004d78 EDCAN_printf(LOG_INFO, "Battery voltage: %d\n", GBT_EVInfo.batteryVoltage); // 0.1V/bit 8002018: 4b85 ldr r3, [pc, #532] @ (8002230 ) 800201a: 88db ldrh r3, [r3, #6] 800201c: 461a mov r2, r3 800201e: 4988 ldr r1, [pc, #544] @ (8002240 ) 8002020: 2006 movs r0, #6 8002022: f002 fea9 bl 8004d78 EDCAN_printf(LOG_INFO, "Battery vendor: %.4s\n", GBT_EVInfo.batteryVendor); // Battery vendor (ASCII string) 8002026: 4a87 ldr r2, [pc, #540] @ (8002244 ) 8002028: 4987 ldr r1, [pc, #540] @ (8002248 ) 800202a: 2006 movs r0, #6 800202c: f002 fea4 bl 8004d78 EDCAN_printf(LOG_INFO, "Battery SN: %lu\n", GBT_EVInfo.batterySN); // int 8002030: 4b7f ldr r3, [pc, #508] @ (8002230 ) 8002032: 68db ldr r3, [r3, #12] 8002034: 461a mov r2, r3 8002036: 4985 ldr r1, [pc, #532] @ (800224c ) 8002038: 2006 movs r0, #6 800203a: f002 fe9d bl 8004d78 EDCAN_printf(LOG_INFO, "Battery manufacture date: %02d.%02d.%04d\n", GBT_EVInfo.batteryManuD, GBT_EVInfo.batteryManuM ,GBT_EVInfo.batteryManuY+1985); // year (offset 1985) 800203e: 4b7c ldr r3, [pc, #496] @ (8002230 ) 8002040: 7c9b ldrb r3, [r3, #18] 8002042: 461a mov r2, r3 8002044: 4b7a ldr r3, [pc, #488] @ (8002230 ) 8002046: 7c5b ldrb r3, [r3, #17] 8002048: 4619 mov r1, r3 800204a: 4b79 ldr r3, [pc, #484] @ (8002230 ) 800204c: 7c1b ldrb r3, [r3, #16] 800204e: f203 73c1 addw r3, r3, #1985 @ 0x7c1 8002052: 9300 str r3, [sp, #0] 8002054: 460b mov r3, r1 8002056: 497e ldr r1, [pc, #504] @ (8002250 ) 8002058: 2006 movs r0, #6 800205a: f002 fe8d bl 8004d78 EDCAN_printf(LOG_INFO, "Battery cycles: %d\n", GBT_EVInfo.batteryCycleCount); //uint24_t 800205e: 4b74 ldr r3, [pc, #464] @ (8002230 ) 8002060: 7cda ldrb r2, [r3, #19] 8002062: 8a9b ldrh r3, [r3, #20] 8002064: 021b lsls r3, r3, #8 8002066: 4313 orrs r3, r2 8002068: 461a mov r2, r3 800206a: 497a ldr r1, [pc, #488] @ (8002254 ) 800206c: 2006 movs r0, #6 800206e: f002 fe83 bl 8004d78 EDCAN_printf(LOG_INFO, "Own auto: %d\n", GBT_EVInfo.ownAuto); // 0 = lizing, 1 = own auto 8002072: 4b6f ldr r3, [pc, #444] @ (8002230 ) 8002074: 7d9b ldrb r3, [r3, #22] 8002076: 461a mov r2, r3 8002078: 4977 ldr r1, [pc, #476] @ (8002258 ) 800207a: 2006 movs r0, #6 800207c: f002 fe7c bl 8004d78 EDCAN_printf(LOG_INFO, "EVIN: %.17s\n", GBT_EVInfo.EVIN); //EVIN 8002080: 4a76 ldr r2, [pc, #472] @ (800225c ) 8002082: 4977 ldr r1, [pc, #476] @ (8002260 ) 8002084: 2006 movs r0, #6 8002086: f002 fe77 bl 8004d78 EDCAN_printf(LOG_INFO, "EV_SW_VER: %.8s\n", GBT_EVInfo.EV_SW_VER); 800208a: 4a76 ldr r2, [pc, #472] @ (8002264 ) 800208c: 4976 ldr r1, [pc, #472] @ (8002268 ) 800208e: 2006 movs r0, #6 8002090: f002 fe72 bl 8004d78 } //Timeout if((GBT_StateTick()>5000) && (GBT_BAT_INFO_recv == 0)){ 8002094: f000 fb32 bl 80026fc 8002098: 4603 mov r3, r0 800209a: f241 3288 movw r2, #5000 @ 0x1388 800209e: 4293 cmp r3, r2 80020a0: f240 824a bls.w 8002538 80020a4: 4b60 ldr r3, [pc, #384] @ (8002228 ) 80020a6: 781b ldrb r3, [r3, #0] 80020a8: 2b00 cmp r3, #0 80020aa: f040 8245 bne.w 8002538 GBT_Error(0xFDF0C0FC); //BRM Timeout 80020ae: 486f ldr r0, [pc, #444] @ (800226c ) 80020b0: f000 fbc0 bl 8002834 EDCAN_printf(LOG_WARN, "BRM Timeout\n"); 80020b4: 496e ldr r1, [pc, #440] @ (8002270 ) 80020b6: 2004 movs r0, #4 80020b8: f002 fe5e bl 8004d78 } break; 80020bc: e23c b.n 8002538 case GBT_S6_BAT_STAT: if(j_rx.state == 0) GBT_SendCRM(0xAA); 80020be: 4b56 ldr r3, [pc, #344] @ (8002218 ) 80020c0: f893 310a ldrb.w r3, [r3, #266] @ 0x10a 80020c4: 2b00 cmp r3, #0 80020c6: d102 bne.n 80020ce 80020c8: 20aa movs r0, #170 @ 0xaa 80020ca: f001 fce3 bl 8003a94 GBT_Delay(250); 80020ce: 20fa movs r0, #250 @ 0xfa 80020d0: f000 fb20 bl 8002714 if(GBT_BAT_STAT_recv){ 80020d4: 4b67 ldr r3, [pc, #412] @ (8002274 ) 80020d6: 781b ldrb r3, [r3, #0] 80020d8: 2b00 cmp r3, #0 80020da: d05a beq.n 8002192 //Got battery status GBT_SwitchState(GBT_S7_BMS_WAIT); 80020dc: 2018 movs r0, #24 80020de: f000 fa67 bl 80025b0 EDCAN_printf(LOG_INFO, "Battery info:\n"); 80020e2: 4965 ldr r1, [pc, #404] @ (8002278 ) 80020e4: 2006 movs r0, #6 80020e6: f002 fe47 bl 8004d78 EDCAN_printf(LOG_INFO, "maxCV %dV\n",GBT_BATStat.maxCellVoltage/100); // 0.01v/bit 80020ea: 4b64 ldr r3, [pc, #400] @ (800227c ) 80020ec: 881b ldrh r3, [r3, #0] 80020ee: 4a64 ldr r2, [pc, #400] @ (8002280 ) 80020f0: fba2 2303 umull r2, r3, r2, r3 80020f4: 095b lsrs r3, r3, #5 80020f6: b29b uxth r3, r3 80020f8: 461a mov r2, r3 80020fa: 4962 ldr r1, [pc, #392] @ (8002284 ) 80020fc: 2006 movs r0, #6 80020fe: f002 fe3b bl 8004d78 EDCAN_printf(LOG_INFO, "maxCC %dA\n",GBT_BATStat.maxChargingCurrent/10); // 0.1A/bit 8002102: 4b5e ldr r3, [pc, #376] @ (800227c ) 8002104: 885b ldrh r3, [r3, #2] 8002106: 4a60 ldr r2, [pc, #384] @ (8002288 ) 8002108: fba2 2303 umull r2, r3, r2, r3 800210c: 08db lsrs r3, r3, #3 800210e: b29b uxth r3, r3 8002110: 461a mov r2, r3 8002112: 495e ldr r1, [pc, #376] @ (800228c ) 8002114: 2006 movs r0, #6 8002116: f002 fe2f bl 8004d78 EDCAN_printf(LOG_INFO, "totE %dkWh\n",GBT_BATStat.totalEnergy/10); // 0.1kWh 800211a: 4b58 ldr r3, [pc, #352] @ (800227c ) 800211c: 889b ldrh r3, [r3, #4] 800211e: 4a5a ldr r2, [pc, #360] @ (8002288 ) 8002120: fba2 2303 umull r2, r3, r2, r3 8002124: 08db lsrs r3, r3, #3 8002126: b29b uxth r3, r3 8002128: 461a mov r2, r3 800212a: 4959 ldr r1, [pc, #356] @ (8002290 ) 800212c: 2006 movs r0, #6 800212e: f002 fe23 bl 8004d78 EDCAN_printf(LOG_INFO, "maxCV %dV\n",GBT_BATStat.maxChargingVoltage/10); // 0.1V/ bit 8002132: 4b52 ldr r3, [pc, #328] @ (800227c ) 8002134: 88db ldrh r3, [r3, #6] 8002136: 4a54 ldr r2, [pc, #336] @ (8002288 ) 8002138: fba2 2303 umull r2, r3, r2, r3 800213c: 08db lsrs r3, r3, #3 800213e: b29b uxth r3, r3 8002140: 461a mov r2, r3 8002142: 4950 ldr r1, [pc, #320] @ (8002284 ) 8002144: 2006 movs r0, #6 8002146: f002 fe17 bl 8004d78 EDCAN_printf(LOG_INFO, "maxT %dC\n",(int16_t)GBT_BATStat.maxTemp-50); // 1C/bit, -50C offset 800214a: 4b4c ldr r3, [pc, #304] @ (800227c ) 800214c: 7a1b ldrb r3, [r3, #8] 800214e: 3b32 subs r3, #50 @ 0x32 8002150: 461a mov r2, r3 8002152: 4950 ldr r1, [pc, #320] @ (8002294 ) 8002154: 2006 movs r0, #6 8002156: f002 fe0f bl 8004d78 EDCAN_printf(LOG_INFO, "SOC %dp\n",GBT_BATStat.SOC/10); // 0.1%/bit , 0..100% 800215a: 4b48 ldr r3, [pc, #288] @ (800227c ) 800215c: f8b3 3009 ldrh.w r3, [r3, #9] 8002160: b29b uxth r3, r3 8002162: 4a49 ldr r2, [pc, #292] @ (8002288 ) 8002164: fba2 2303 umull r2, r3, r2, r3 8002168: 08db lsrs r3, r3, #3 800216a: b29b uxth r3, r3 800216c: 461a mov r2, r3 800216e: 494a ldr r1, [pc, #296] @ (8002298 ) 8002170: 2006 movs r0, #6 8002172: f002 fe01 bl 8004d78 EDCAN_printf(LOG_INFO, "Volt. %dV\n",GBT_BATStat.measVoltage/10); // 0.1V/bit 8002176: 4b41 ldr r3, [pc, #260] @ (800227c ) 8002178: f8b3 300b ldrh.w r3, [r3, #11] 800217c: b29b uxth r3, r3 800217e: 4a42 ldr r2, [pc, #264] @ (8002288 ) 8002180: fba2 2303 umull r2, r3, r2, r3 8002184: 08db lsrs r3, r3, #3 8002186: b29b uxth r3, r3 8002188: 461a mov r2, r3 800218a: 4944 ldr r1, [pc, #272] @ (800229c ) 800218c: 2006 movs r0, #6 800218e: f002 fdf3 bl 8004d78 } if((GBT_StateTick()>5000) && (GBT_BAT_STAT_recv == 0)){ 8002192: f000 fab3 bl 80026fc 8002196: 4603 mov r3, r0 8002198: f241 3288 movw r2, #5000 @ 0x1388 800219c: 4293 cmp r3, r2 800219e: f240 81cd bls.w 800253c 80021a2: 4b34 ldr r3, [pc, #208] @ (8002274 ) 80021a4: 781b ldrb r3, [r3, #0] 80021a6: 2b00 cmp r3, #0 80021a8: f040 81c8 bne.w 800253c GBT_Error(0xFCF1C0FC); //BCP Timeout 80021ac: 483c ldr r0, [pc, #240] @ (80022a0 ) 80021ae: f000 fb41 bl 8002834 EDCAN_printf(LOG_WARN, "BCP Timeout\n"); 80021b2: 493c ldr r1, [pc, #240] @ (80022a4 ) 80021b4: 2004 movs r0, #4 80021b6: f002 fddf bl 8004d78 } break; 80021ba: e1bf b.n 800253c case GBT_S7_BMS_WAIT: if(j_rx.state == 0) GBT_SendCTS(); 80021bc: 4b16 ldr r3, [pc, #88] @ (8002218 ) 80021be: f893 310a ldrb.w r3, [r3, #266] @ 0x10a 80021c2: 2b00 cmp r3, #0 80021c4: d101 bne.n 80021ca 80021c6: f001 fc2d bl 8003a24 HAL_Delay(2); 80021ca: 2002 movs r0, #2 80021cc: f003 fb72 bl 80058b4 if(j_rx.state == 0) GBT_SendCML(); 80021d0: 4b11 ldr r3, [pc, #68] @ (8002218 ) 80021d2: f893 310a ldrb.w r3, [r3, #266] @ 0x10a 80021d6: 2b00 cmp r3, #0 80021d8: d101 bne.n 80021de 80021da: f001 fc39 bl 8003a50 GBT_Delay(250); 80021de: 20fa movs r0, #250 @ 0xfa 80021e0: f000 fa98 bl 8002714 if((GBT_StateTick()>5000) && (GBT_BRO_recv == 0)){ 80021e4: f000 fa8a bl 80026fc 80021e8: 4603 mov r3, r0 80021ea: f241 3288 movw r2, #5000 @ 0x1388 80021ee: 4293 cmp r3, r2 80021f0: d90a bls.n 8002208 80021f2: 4b2d ldr r3, [pc, #180] @ (80022a8 ) 80021f4: 781b ldrb r3, [r3, #0] 80021f6: 2b00 cmp r3, #0 80021f8: d106 bne.n 8002208 GBT_Error(0xFCF4C0FC); //BRO Timeout 80021fa: 482c ldr r0, [pc, #176] @ (80022ac ) 80021fc: f000 fb1a bl 8002834 EDCAN_printf(LOG_WARN, "BRO Timeout\n"); 8002200: 492b ldr r1, [pc, #172] @ (80022b0 ) 8002202: 2004 movs r0, #4 8002204: f002 fdb8 bl 8004d78 } if(EV_ready){ 8002208: 4b2a ldr r3, [pc, #168] @ (80022b4 ) 800220a: 781b ldrb r3, [r3, #0] 800220c: 2b00 cmp r3, #0 800220e: d053 beq.n 80022b8 //EV ready (AA) GBT_SwitchState(GBT_S8_INIT_CHARGER); 8002210: 2019 movs r0, #25 8002212: f000 f9cd bl 80025b0 if((GBT_StateTick()>60000) && (GBT_BRO_recv == 1)){ GBT_Error(0xFCF4C0FC); //BRO Timeout EDCAN_printf(LOG_WARN, "BRO Timeout\n"); } } break; 8002216: e193 b.n 8002540 8002218: 200004cc .word 0x200004cc 800221c: 20000314 .word 0x20000314 8002220: 200004b4 .word 0x200004b4 8002224: 200004c4 .word 0x200004c4 8002228: 200002fc .word 0x200002fc 800222c: 0800d6f8 .word 0x0800d6f8 8002230: 20000318 .word 0x20000318 8002234: 0800d704 .word 0x0800d704 8002238: 0800d718 .word 0x0800d718 800223c: 0800d72c .word 0x0800d72c 8002240: 0800d744 .word 0x0800d744 8002244: 20000320 .word 0x20000320 8002248: 0800d75c .word 0x0800d75c 800224c: 0800d774 .word 0x0800d774 8002250: 0800d788 .word 0x0800d788 8002254: 0800d7b4 .word 0x0800d7b4 8002258: 0800d7c8 .word 0x0800d7c8 800225c: 20000330 .word 0x20000330 8002260: 0800d7d8 .word 0x0800d7d8 8002264: 20000341 .word 0x20000341 8002268: 0800d7e8 .word 0x0800d7e8 800226c: fdf0c0fc .word 0xfdf0c0fc 8002270: 0800d7fc .word 0x0800d7fc 8002274: 200002fd .word 0x200002fd 8002278: 0800d80c .word 0x0800d80c 800227c: 2000034c .word 0x2000034c 8002280: 51eb851f .word 0x51eb851f 8002284: 0800d81c .word 0x0800d81c 8002288: cccccccd .word 0xcccccccd 800228c: 0800d828 .word 0x0800d828 8002290: 0800d834 .word 0x0800d834 8002294: 0800d840 .word 0x0800d840 8002298: 0800d84c .word 0x0800d84c 800229c: 0800d858 .word 0x0800d858 80022a0: fcf1c0fc .word 0xfcf1c0fc 80022a4: 0800d864 .word 0x0800d864 80022a8: 200002fe .word 0x200002fe 80022ac: fcf4c0fc .word 0xfcf4c0fc 80022b0: 0800d874 .word 0x0800d874 80022b4: 20000301 .word 0x20000301 if((GBT_StateTick()>60000) && (GBT_BRO_recv == 1)){ 80022b8: f000 fa20 bl 80026fc 80022bc: 4603 mov r3, r0 80022be: f64e 2260 movw r2, #60000 @ 0xea60 80022c2: 4293 cmp r3, r2 80022c4: f240 813c bls.w 8002540 80022c8: 4ba5 ldr r3, [pc, #660] @ (8002560 ) 80022ca: 781b ldrb r3, [r3, #0] 80022cc: 2b01 cmp r3, #1 80022ce: f040 8137 bne.w 8002540 GBT_Error(0xFCF4C0FC); //BRO Timeout 80022d2: 48a4 ldr r0, [pc, #656] @ (8002564 ) 80022d4: f000 faae bl 8002834 EDCAN_printf(LOG_WARN, "BRO Timeout\n"); 80022d8: 49a3 ldr r1, [pc, #652] @ (8002568 ) 80022da: 2004 movs r0, #4 80022dc: f002 fd4c bl 8004d78 break; 80022e0: e12e b.n 8002540 case GBT_S8_INIT_CHARGER: if(j_rx.state == 0) GBT_SendCRO(0x00); 80022e2: 4ba2 ldr r3, [pc, #648] @ (800256c ) 80022e4: f893 310a ldrb.w r3, [r3, #266] @ 0x10a 80022e8: 2b00 cmp r3, #0 80022ea: d102 bne.n 80022f2 80022ec: 2000 movs r0, #0 80022ee: f001 fbe7 bl 8003ac0 //TODO GBT_Delay(250); 80022f2: 20fa movs r0, #250 @ 0xfa 80022f4: f000 fa0e bl 8002714 if(GBT_StateTick()>1500){ 80022f8: f000 fa00 bl 80026fc 80022fc: 4603 mov r3, r0 80022fe: f240 52dc movw r2, #1500 @ 0x5dc 8002302: 4293 cmp r3, r2 8002304: f240 811e bls.w 8002544 //Power Modules initiated GBT_SwitchState(GBT_S9_WAIT_BCL); 8002308: 2020 movs r0, #32 800230a: f000 f951 bl 80025b0 } break; 800230e: e119 b.n 8002544 case GBT_S9_WAIT_BCL: if(j_rx.state == 0) GBT_SendCRO(0xAA); 8002310: 4b96 ldr r3, [pc, #600] @ (800256c ) 8002312: f893 310a ldrb.w r3, [r3, #266] @ 0x10a 8002316: 2b00 cmp r3, #0 8002318: d102 bne.n 8002320 800231a: 20aa movs r0, #170 @ 0xaa 800231c: f001 fbd0 bl 8003ac0 GBT_Delay(250); 8002320: 20fa movs r0, #250 @ 0xfa 8002322: f000 f9f7 bl 8002714 if(GBT_ReqPower.chargingMode != 0){ //REFACTORING 8002326: 4b92 ldr r3, [pc, #584] @ (8002570 ) 8002328: 791b ldrb r3, [r3, #4] 800232a: 2b00 cmp r3, #0 800232c: f000 810c beq.w 8002548 //BCL power requirements received GBT_SwitchState(GBT_S10_CHARGING); 8002330: 2021 movs r0, #33 @ 0x21 8002332: f000 f93d bl 80025b0 CONN_SetState(CONN_Charging); 8002336: 2005 movs r0, #5 8002338: f000 fc2a bl 8002b90 uint16_t curr=4000-GBT_ReqPower.requestedCurrent; 800233c: 4b8c ldr r3, [pc, #560] @ (8002570 ) 800233e: 885b ldrh r3, [r3, #2] 8002340: f5c3 637a rsb r3, r3, #4000 @ 0xfa0 8002344: 807b strh r3, [r7, #2] uint16_t volt=GBT_ReqPower.requestedVoltage; 8002346: 4b8a ldr r3, [pc, #552] @ (8002570 ) 8002348: 881b ldrh r3, [r3, #0] 800234a: 803b strh r3, [r7, #0] //TODO Limits GBT_EDCAN_Output.requestedVoltage = volt; 800234c: 4b89 ldr r3, [pc, #548] @ (8002574 ) 800234e: 883a ldrh r2, [r7, #0] 8002350: f8a3 2001 strh.w r2, [r3, #1] GBT_EDCAN_Output.requestedCurrent = curr; 8002354: 4b87 ldr r3, [pc, #540] @ (8002574 ) 8002356: 887a ldrh r2, [r7, #2] 8002358: f8a3 2003 strh.w r2, [r3, #3] GBT_EDCAN_Output.enablePSU = 1; 800235c: 4b85 ldr r3, [pc, #532] @ (8002574 ) 800235e: 2201 movs r2, #1 8002360: 701a strb r2, [r3, #0] GBT_TimeChargingStarted = get_Current_Time(); 8002362: f002 feb7 bl 80050d4 8002366: 4603 mov r3, r0 8002368: 4a83 ldr r2, [pc, #524] @ (8002578 ) 800236a: 6013 str r3, [r2, #0] } break; 800236c: e0ec b.n 8002548 case GBT_S10_CHARGING: //CHARGING //TODO BCL BCS BSM missing ERRORS if(GBT_EDCAN_Input.chargeControl == CHARGING_NOT_ALLOWED) GBT_StopOCPP(GBT_CST_SUSPENDS_ARTIFICIALLY); 800236e: 4b83 ldr r3, [pc, #524] @ (800257c ) 8002370: 795b ldrb r3, [r3, #5] 8002372: 2b01 cmp r3, #1 8002374: d102 bne.n 800237c 8002376: 4882 ldr r0, [pc, #520] @ (8002580 ) 8002378: f000 fa28 bl 80027cc if(GBT_EDCAN_Input.chargeControl == FORCE_UNLOCK) GBT_StopOCPP(GBT_CST_SUSPENDS_ARTIFICIALLY); // --> Finished 800237c: 4b7f ldr r3, [pc, #508] @ (800257c ) 800237e: 795b ldrb r3, [r3, #5] 8002380: 2b03 cmp r3, #3 8002382: d102 bne.n 800238a 8002384: 487e ldr r0, [pc, #504] @ (8002580 ) 8002386: f000 fa21 bl 80027cc if(GBT_LockState.error) { 800238a: 4b7e ldr r3, [pc, #504] @ (8002584 ) 800238c: 785b ldrb r3, [r3, #1] 800238e: 2b00 cmp r3, #0 8002390: d006 beq.n 80023a0 GBT_StopEVSE(GBT_CST_OTHERFALUT); // --> Suspend EVSE 8002392: f24f 40f0 movw r0, #62704 @ 0xf4f0 8002396: f000 f9fd bl 8002794 GBT_EDCAN_Output.outputError = CONN_ERR_LOCK; 800239a: 4b76 ldr r3, [pc, #472] @ (8002574 ) 800239c: 2204 movs r2, #4 800239e: 735a strb r2, [r3, #13] } if((GBT_ReadTemp(0) > 90) || (GBT_ReadTemp(1) > 90)) { 80023a0: 2000 movs r0, #0 80023a2: f7ff fa4f bl 8001844 80023a6: 4603 mov r3, r0 80023a8: 2b5a cmp r3, #90 @ 0x5a 80023aa: dc05 bgt.n 80023b8 80023ac: 2001 movs r0, #1 80023ae: f7ff fa49 bl 8001844 80023b2: 4603 mov r3, r0 80023b4: 2b5a cmp r3, #90 @ 0x5a 80023b6: dd13 ble.n 80023e0 GBT_StopEVSE(GBT_CST_CONNECTOR_OVER_TEMP); 80023b8: 4873 ldr r0, [pc, #460] @ (8002588 ) 80023ba: f000 f9eb bl 8002794 GBT_EDCAN_Output.outputError = CONN_ERR_CONN_TEMP; 80023be: 4b6d ldr r3, [pc, #436] @ (8002574 ) 80023c0: 2205 movs r2, #5 80023c2: 735a strb r2, [r3, #13] EDCAN_printf(LOG_WARN, "Connector overheat %d %d\n", GBT_ReadTemp(0), GBT_ReadTemp(1)); 80023c4: 2000 movs r0, #0 80023c6: f7ff fa3d bl 8001844 80023ca: 4603 mov r3, r0 80023cc: 461c mov r4, r3 80023ce: 2001 movs r0, #1 80023d0: f7ff fa38 bl 8001844 80023d4: 4603 mov r3, r0 80023d6: 4622 mov r2, r4 80023d8: 496c ldr r1, [pc, #432] @ (800258c ) 80023da: 2004 movs r0, #4 80023dc: f002 fccc bl 8004d78 } if(GBT_EDCAN_Input.chargingError != CONN_NO_ERROR){ // --> Suspend EVSE 80023e0: 4b66 ldr r3, [pc, #408] @ (800257c ) 80023e2: 799b ldrb r3, [r3, #6] 80023e4: 2b00 cmp r3, #0 80023e6: d003 beq.n 80023f0 GBT_StopEVSE(GBT_CST_OTHERFALUT); 80023e8: f24f 40f0 movw r0, #62704 @ 0xf4f0 80023ec: f000 f9d2 bl 8002794 // EDCAN_printf(LOG_WARN, "Isolation error\n"); } //GBT_ChargerCurrentStatus.chargingPermissible = 0b1111111111111100;//NOT PERMITTED GBT_ChargerCurrentStatus.chargingPermissible = 0b1111111111111101; 80023f0: 4b67 ldr r3, [pc, #412] @ (8002590 ) 80023f2: f64f 72fd movw r2, #65533 @ 0xfffd 80023f6: 80da strh r2, [r3, #6] GBT_ChargerCurrentStatus.chargingTime = (get_Current_Time() - GBT_TimeChargingStarted)/60; 80023f8: f002 fe6c bl 80050d4 80023fc: 4602 mov r2, r0 80023fe: 4b5e ldr r3, [pc, #376] @ (8002578 ) 8002400: 681b ldr r3, [r3, #0] 8002402: 1ad3 subs r3, r2, r3 8002404: 4a63 ldr r2, [pc, #396] @ (8002594 ) 8002406: fba2 2303 umull r2, r3, r2, r3 800240a: 095b lsrs r3, r3, #5 800240c: b29a uxth r2, r3 800240e: 4b60 ldr r3, [pc, #384] @ (8002590 ) 8002410: 809a strh r2, [r3, #4] // GBT_ChargerCurrentStatus.outputCurrent = 4000 - GBT_EDCAN_Output.requestedCurrent; // GBT_ChargerCurrentStatus.outputVoltage = GBT_EDCAN_Output.requestedVoltage; GBT_ChargerCurrentStatus.outputCurrent = 4000 - GBT_EDCAN_Input.measuredCurrent; 8002412: 4b5a ldr r3, [pc, #360] @ (800257c ) 8002414: f8b3 3003 ldrh.w r3, [r3, #3] 8002418: b29b uxth r3, r3 800241a: f5c3 637a rsb r3, r3, #4000 @ 0xfa0 800241e: b29a uxth r2, r3 8002420: 4b5b ldr r3, [pc, #364] @ (8002590 ) 8002422: 805a strh r2, [r3, #2] GBT_ChargerCurrentStatus.outputVoltage = GBT_EDCAN_Input.measuredVoltage; 8002424: 4b55 ldr r3, [pc, #340] @ (800257c ) 8002426: f8b3 3001 ldrh.w r3, [r3, #1] 800242a: b29a uxth r2, r3 800242c: 4b58 ldr r3, [pc, #352] @ (8002590 ) 800242e: 801a strh r2, [r3, #0] GBT_EDCAN_Output.chargingElapsedTimeMin = (get_Current_Time() - GBT_TimeChargingStarted)/60; 8002430: f002 fe50 bl 80050d4 8002434: 4602 mov r2, r0 8002436: 4b50 ldr r3, [pc, #320] @ (8002578 ) 8002438: 681b ldr r3, [r3, #0] 800243a: 1ad3 subs r3, r2, r3 800243c: 4a55 ldr r2, [pc, #340] @ (8002594 ) 800243e: fba2 2303 umull r2, r3, r2, r3 8002442: 095b lsrs r3, r3, #5 8002444: b29a uxth r2, r3 8002446: 4b4b ldr r3, [pc, #300] @ (8002574 ) 8002448: f8a3 2009 strh.w r2, [r3, #9] GBT_EDCAN_Output.chargingElapsedTimeSec = (get_Current_Time() - GBT_TimeChargingStarted)%60; 800244c: f002 fe42 bl 80050d4 8002450: 4602 mov r2, r0 8002452: 4b49 ldr r3, [pc, #292] @ (8002578 ) 8002454: 681b ldr r3, [r3, #0] 8002456: 1ad1 subs r1, r2, r3 8002458: 4b4e ldr r3, [pc, #312] @ (8002594 ) 800245a: fba3 2301 umull r2, r3, r3, r1 800245e: 095a lsrs r2, r3, #5 8002460: 4613 mov r3, r2 8002462: 011b lsls r3, r3, #4 8002464: 1a9b subs r3, r3, r2 8002466: 009b lsls r3, r3, #2 8002468: 1aca subs r2, r1, r3 800246a: b2d2 uxtb r2, r2 800246c: 4b41 ldr r3, [pc, #260] @ (8002574 ) 800246e: 72da strb r2, [r3, #11] if(j_rx.state == 0) GBT_SendCCS(); 8002470: 4b3e ldr r3, [pc, #248] @ (800256c ) 8002472: f893 310a ldrb.w r3, [r3, #266] @ 0x10a 8002476: 2b00 cmp r3, #0 8002478: d101 bne.n 800247e 800247a: f001 fb35 bl 8003ae8 if(j_rx.state == 0) { 800247e: 4b3b ldr r3, [pc, #236] @ (800256c ) 8002480: f893 310a ldrb.w r3, [r3, #266] @ 0x10a 8002484: 2b00 cmp r3, #0 8002486: d105 bne.n 8002494 GBT_SendCCS(); 8002488: f001 fb2e bl 8003ae8 GBT_Delay(49); 800248c: 2031 movs r0, #49 @ 0x31 800248e: f000 f941 bl 8002714 // log_printf(LOG_WARN, "Resend packet\n"); } //TODO: снижение тока если перегрев контактов break; 8002492: e060 b.n 8002556 GBT_Delay(10); // Resend packet if not sent 8002494: 200a movs r0, #10 8002496: f000 f93d bl 8002714 break; 800249a: e05c b.n 8002556 case GBT_STOP: GBT_Delay(10); 800249c: 200a movs r0, #10 800249e: f000 f939 bl 8002714 GBT_EDCAN_Output.enablePSU = 0; 80024a2: 4b34 ldr r3, [pc, #208] @ (8002574 ) 80024a4: 2200 movs r2, #0 80024a6: 701a strb r2, [r3, #0] GBT_SendCST(GBT_StopCauseCode); 80024a8: 4b3b ldr r3, [pc, #236] @ (8002598 ) 80024aa: 681b ldr r3, [r3, #0] 80024ac: 4618 mov r0, r3 80024ae: f001 fb29 bl 8003b04 //RELAY_Write(RELAY_OUTPUT, 0); //GBT_SwitchState(GBT_DISABLED); if(GBT_StateTick()>10000){ 80024b2: f000 f923 bl 80026fc 80024b6: 4603 mov r3, r0 80024b8: f242 7210 movw r2, #10000 @ 0x2710 80024bc: 4293 cmp r3, r2 80024be: d906 bls.n 80024ce EDCAN_printf(LOG_WARN, "BSD Timeout\n"); 80024c0: 4936 ldr r1, [pc, #216] @ (800259c ) 80024c2: 2004 movs r0, #4 80024c4: f002 fc58 bl 8004d78 GBT_Error(0xFCF0C0FD); //BSD Timeout 80024c8: 4835 ldr r0, [pc, #212] @ (80025a0 ) 80024ca: f000 f9b3 bl 8002834 } if(GBT_BSD_recv != 0){ 80024ce: 4b35 ldr r3, [pc, #212] @ (80025a4 ) 80024d0: 781b ldrb r3, [r3, #0] 80024d2: 2b00 cmp r3, #0 80024d4: d03a beq.n 800254c GBT_SwitchState(GBT_STOP_CSD); 80024d6: 2023 movs r0, #35 @ 0x23 80024d8: f000 f86a bl 80025b0 } break; 80024dc: e036 b.n 800254c case GBT_STOP_CSD: GBT_Delay(250); 80024de: 20fa movs r0, #250 @ 0xfa 80024e0: f000 f918 bl 8002714 GBT_SendCSD(); 80024e4: f001 fb2e bl 8003b44 if(GBT_StateTick()>2500){ //2.5S 80024e8: f000 f908 bl 80026fc 80024ec: 4603 mov r3, r0 80024ee: f640 12c4 movw r2, #2500 @ 0x9c4 80024f2: 4293 cmp r3, r2 80024f4: d92c bls.n 8002550 GBT_SwitchState(GBT_COMPLETE); 80024f6: 2025 movs r0, #37 @ 0x25 80024f8: f000 f85a bl 80025b0 // GBT_Reset(); //CONN_SetState(CONN_Occupied_complete); //if(connectorState == CONN_Occupied_charging) //PSU_Mode(0x0100); } break; 80024fc: e028 b.n 8002550 case GBT_ERROR: GBT_SendCEM(GBT_ErrorCode); //2.5S 80024fe: 4b2a ldr r3, [pc, #168] @ (80025a8 ) 8002500: 681b ldr r3, [r3, #0] 8002502: 4618 mov r0, r3 8002504: f001 fb3e bl 8003b84 GBT_SwitchState(GBT_COMPLETE); 8002508: 2025 movs r0, #37 @ 0x25 800250a: f000 f851 bl 80025b0 // GBT_Reset(); // break; 800250e: e022 b.n 8002556 case GBT_COMPLETE: if(connectorState != CONN_Finishing) { 8002510: 4b26 ldr r3, [pc, #152] @ (80025ac ) 8002512: 781b ldrb r3, [r3, #0] 8002514: 2b06 cmp r3, #6 8002516: d01d beq.n 8002554 GBT_SwitchState(GBT_DISABLED); 8002518: 2010 movs r0, #16 800251a: f000 f849 bl 80025b0 GBT_Reset();//CHECK 800251e: f000 f9a5 bl 800286c } break; 8002522: e017 b.n 8002554 default: GBT_SwitchState(GBT_DISABLED); 8002524: 2010 movs r0, #16 8002526: f000 f843 bl 80025b0 } } 800252a: e014 b.n 8002556 break; 800252c: bf00 nop 800252e: e012 b.n 8002556 break; 8002530: bf00 nop 8002532: e010 b.n 8002556 break; 8002534: bf00 nop 8002536: e00e b.n 8002556 break; 8002538: bf00 nop 800253a: e00c b.n 8002556 break; 800253c: bf00 nop 800253e: e00a b.n 8002556 break; 8002540: bf00 nop 8002542: e008 b.n 8002556 break; 8002544: bf00 nop 8002546: e006 b.n 8002556 break; 8002548: bf00 nop 800254a: e004 b.n 8002556 break; 800254c: bf00 nop 800254e: e002 b.n 8002556 break; 8002550: bf00 nop 8002552: e000 b.n 8002556 break; 8002554: bf00 nop } 8002556: bf00 nop 8002558: 3708 adds r7, #8 800255a: 46bd mov sp, r7 800255c: bdb0 pop {r4, r5, r7, pc} 800255e: bf00 nop 8002560: 200002fe .word 0x200002fe 8002564: fcf4c0fc .word 0xfcf4c0fc 8002568: 0800d874 .word 0x0800d874 800256c: 200004cc .word 0x200004cc 8002570: 2000035c .word 0x2000035c 8002574: 200004b4 .word 0x200004b4 8002578: 20000394 .word 0x20000394 800257c: 200004c4 .word 0x200004c4 8002580: 0400f0f0 .word 0x0400f0f0 8002584: 20000000 .word 0x20000000 8002588: 0001f0f0 .word 0x0001f0f0 800258c: 0800d884 .word 0x0800d884 8002590: 20000380 .word 0x20000380 8002594: 88888889 .word 0x88888889 8002598: 20000398 .word 0x20000398 800259c: 0800d8a0 .word 0x0800d8a0 80025a0: fcf0c0fd .word 0xfcf0c0fd 80025a4: 20000300 .word 0x20000300 80025a8: 2000039c .word 0x2000039c 80025ac: 200003a1 .word 0x200003a1 080025b0 : void GBT_SwitchState(gbtState_t state){ 80025b0: b580 push {r7, lr} 80025b2: b082 sub sp, #8 80025b4: af00 add r7, sp, #0 80025b6: 4603 mov r3, r0 80025b8: 71fb strb r3, [r7, #7] GBT_State = state; 80025ba: 4a3f ldr r2, [pc, #252] @ (80026b8 ) 80025bc: 79fb ldrb r3, [r7, #7] 80025be: 7013 strb r3, [r2, #0] ED_status = state; 80025c0: 4a3e ldr r2, [pc, #248] @ (80026bc ) 80025c2: 79fb ldrb r3, [r7, #7] 80025c4: 7013 strb r3, [r2, #0] GBT_state_tick = HAL_GetTick(); 80025c6: f003 f96b bl 80058a0 80025ca: 4603 mov r3, r0 80025cc: 4a3c ldr r2, [pc, #240] @ (80026c0 ) 80025ce: 6013 str r3, [r2, #0] // if(GBT_State == GBT_STOP) printf ("GBT_STOP\n"); // if(GBT_State == GBT_STOP_CSD) printf ("GBT_STOP_CSD\n"); // if(GBT_State == GBT_ERROR) printf ("GBT_ERROR\n"); // if(GBT_State == GBT_COMPLETE) printf ("GBT_COMPLETE\n"); if(GBT_State == GBT_DISABLED) EDCAN_printf(LOG_INFO, "GBT_DISABLED\n"); 80025d0: 4b39 ldr r3, [pc, #228] @ (80026b8 ) 80025d2: 781b ldrb r3, [r3, #0] 80025d4: 2b10 cmp r3, #16 80025d6: d103 bne.n 80025e0 80025d8: 493a ldr r1, [pc, #232] @ (80026c4 ) 80025da: 2006 movs r0, #6 80025dc: f002 fbcc bl 8004d78 if(GBT_State == GBT_S3_STARTED) EDCAN_printf(LOG_INFO, "GBT_S3_STARTED\n"); 80025e0: 4b35 ldr r3, [pc, #212] @ (80026b8 ) 80025e2: 781b ldrb r3, [r3, #0] 80025e4: 2b13 cmp r3, #19 80025e6: d103 bne.n 80025f0 80025e8: 4937 ldr r1, [pc, #220] @ (80026c8 ) 80025ea: 2006 movs r0, #6 80025ec: f002 fbc4 bl 8004d78 if(GBT_State == GBT_S31_WAIT_BHM) EDCAN_printf(LOG_INFO, "GBT_S31_WAIT_BHM\n"); 80025f0: 4b31 ldr r3, [pc, #196] @ (80026b8 ) 80025f2: 781b ldrb r3, [r3, #0] 80025f4: 2b14 cmp r3, #20 80025f6: d103 bne.n 8002600 80025f8: 4934 ldr r1, [pc, #208] @ (80026cc ) 80025fa: 2006 movs r0, #6 80025fc: f002 fbbc bl 8004d78 if(GBT_State == GBT_S4_ISOTEST) EDCAN_printf(LOG_INFO, "GBT_S4_ISOTEST\n"); 8002600: 4b2d ldr r3, [pc, #180] @ (80026b8 ) 8002602: 781b ldrb r3, [r3, #0] 8002604: 2b15 cmp r3, #21 8002606: d103 bne.n 8002610 8002608: 4931 ldr r1, [pc, #196] @ (80026d0 ) 800260a: 2006 movs r0, #6 800260c: f002 fbb4 bl 8004d78 if(GBT_State == GBT_S5_BAT_INFO) EDCAN_printf(LOG_INFO, "GBT_S5_BAT_INFO\n"); 8002610: 4b29 ldr r3, [pc, #164] @ (80026b8 ) 8002612: 781b ldrb r3, [r3, #0] 8002614: 2b16 cmp r3, #22 8002616: d103 bne.n 8002620 8002618: 492e ldr r1, [pc, #184] @ (80026d4 ) 800261a: 2006 movs r0, #6 800261c: f002 fbac bl 8004d78 if(GBT_State == GBT_S6_BAT_STAT) EDCAN_printf(LOG_INFO, "GBT_S6_BAT_STAT\n"); 8002620: 4b25 ldr r3, [pc, #148] @ (80026b8 ) 8002622: 781b ldrb r3, [r3, #0] 8002624: 2b17 cmp r3, #23 8002626: d103 bne.n 8002630 8002628: 492b ldr r1, [pc, #172] @ (80026d8 ) 800262a: 2006 movs r0, #6 800262c: f002 fba4 bl 8004d78 if(GBT_State == GBT_S7_BMS_WAIT) EDCAN_printf(LOG_INFO, "GBT_S7_BMS_WAIT\n"); 8002630: 4b21 ldr r3, [pc, #132] @ (80026b8 ) 8002632: 781b ldrb r3, [r3, #0] 8002634: 2b18 cmp r3, #24 8002636: d103 bne.n 8002640 8002638: 4928 ldr r1, [pc, #160] @ (80026dc ) 800263a: 2006 movs r0, #6 800263c: f002 fb9c bl 8004d78 if(GBT_State == GBT_S8_INIT_CHARGER)EDCAN_printf(LOG_INFO, "GBT_S8_INIT_CHARGER\n"); 8002640: 4b1d ldr r3, [pc, #116] @ (80026b8 ) 8002642: 781b ldrb r3, [r3, #0] 8002644: 2b19 cmp r3, #25 8002646: d103 bne.n 8002650 8002648: 4925 ldr r1, [pc, #148] @ (80026e0 ) 800264a: 2006 movs r0, #6 800264c: f002 fb94 bl 8004d78 if(GBT_State == GBT_S9_WAIT_BCL) EDCAN_printf(LOG_INFO, "GBT_S9_WAIT_BCL\n"); 8002650: 4b19 ldr r3, [pc, #100] @ (80026b8 ) 8002652: 781b ldrb r3, [r3, #0] 8002654: 2b20 cmp r3, #32 8002656: d103 bne.n 8002660 8002658: 4922 ldr r1, [pc, #136] @ (80026e4 ) 800265a: 2006 movs r0, #6 800265c: f002 fb8c bl 8004d78 if(GBT_State == GBT_S10_CHARGING) EDCAN_printf(LOG_INFO, "GBT_S10_CHARGING\n"); 8002660: 4b15 ldr r3, [pc, #84] @ (80026b8 ) 8002662: 781b ldrb r3, [r3, #0] 8002664: 2b21 cmp r3, #33 @ 0x21 8002666: d103 bne.n 8002670 8002668: 491f ldr r1, [pc, #124] @ (80026e8 ) 800266a: 2006 movs r0, #6 800266c: f002 fb84 bl 8004d78 if(GBT_State == GBT_STOP) EDCAN_printf(LOG_INFO, "GBT_STOP\n"); 8002670: 4b11 ldr r3, [pc, #68] @ (80026b8 ) 8002672: 781b ldrb r3, [r3, #0] 8002674: 2b22 cmp r3, #34 @ 0x22 8002676: d103 bne.n 8002680 8002678: 491c ldr r1, [pc, #112] @ (80026ec ) 800267a: 2006 movs r0, #6 800267c: f002 fb7c bl 8004d78 if(GBT_State == GBT_STOP_CSD) EDCAN_printf(LOG_INFO, "GBT_STOP_CSD\n"); 8002680: 4b0d ldr r3, [pc, #52] @ (80026b8 ) 8002682: 781b ldrb r3, [r3, #0] 8002684: 2b23 cmp r3, #35 @ 0x23 8002686: d103 bne.n 8002690 8002688: 4919 ldr r1, [pc, #100] @ (80026f0 ) 800268a: 2006 movs r0, #6 800268c: f002 fb74 bl 8004d78 if(GBT_State == GBT_ERROR) EDCAN_printf(LOG_WARN, "GBT_ERROR\n"); 8002690: 4b09 ldr r3, [pc, #36] @ (80026b8 ) 8002692: 781b ldrb r3, [r3, #0] 8002694: 2b24 cmp r3, #36 @ 0x24 8002696: d103 bne.n 80026a0 8002698: 4916 ldr r1, [pc, #88] @ (80026f4 ) 800269a: 2004 movs r0, #4 800269c: f002 fb6c bl 8004d78 if(GBT_State == GBT_COMPLETE) EDCAN_printf(LOG_INFO, "GBT_COMPLETE\n"); 80026a0: 4b05 ldr r3, [pc, #20] @ (80026b8 ) 80026a2: 781b ldrb r3, [r3, #0] 80026a4: 2b25 cmp r3, #37 @ 0x25 80026a6: d103 bne.n 80026b0 80026a8: 4913 ldr r1, [pc, #76] @ (80026f8 ) 80026aa: 2006 movs r0, #6 80026ac: f002 fb64 bl 8004d78 } 80026b0: bf00 nop 80026b2: 3708 adds r7, #8 80026b4: 46bd mov sp, r7 80026b6: bd80 pop {r7, pc} 80026b8: 200002ec .word 0x200002ec 80026bc: 20003338 .word 0x20003338 80026c0: 200002f0 .word 0x200002f0 80026c4: 0800d8b0 .word 0x0800d8b0 80026c8: 0800d8c0 .word 0x0800d8c0 80026cc: 0800d8d0 .word 0x0800d8d0 80026d0: 0800d8e4 .word 0x0800d8e4 80026d4: 0800d8f4 .word 0x0800d8f4 80026d8: 0800d908 .word 0x0800d908 80026dc: 0800d91c .word 0x0800d91c 80026e0: 0800d930 .word 0x0800d930 80026e4: 0800d948 .word 0x0800d948 80026e8: 0800d95c .word 0x0800d95c 80026ec: 0800d970 .word 0x0800d970 80026f0: 0800d97c .word 0x0800d97c 80026f4: 0800d98c .word 0x0800d98c 80026f8: 0800d998 .word 0x0800d998 080026fc : uint32_t GBT_StateTick(){ 80026fc: b580 push {r7, lr} 80026fe: af00 add r7, sp, #0 return HAL_GetTick() - GBT_state_tick; 8002700: f003 f8ce bl 80058a0 8002704: 4602 mov r2, r0 8002706: 4b02 ldr r3, [pc, #8] @ (8002710 ) 8002708: 681b ldr r3, [r3, #0] 800270a: 1ad3 subs r3, r2, r3 } 800270c: 4618 mov r0, r3 800270e: bd80 pop {r7, pc} 8002710: 200002f0 .word 0x200002f0 08002714 : void GBT_Delay(uint32_t delay){ 8002714: b580 push {r7, lr} 8002716: b082 sub sp, #8 8002718: af00 add r7, sp, #0 800271a: 6078 str r0, [r7, #4] GBT_delay_start = HAL_GetTick(); 800271c: f003 f8c0 bl 80058a0 8002720: 4603 mov r3, r0 8002722: 4a04 ldr r2, [pc, #16] @ (8002734 ) 8002724: 6013 str r3, [r2, #0] GBT_delay = delay; 8002726: 4a04 ldr r2, [pc, #16] @ (8002738 ) 8002728: 687b ldr r3, [r7, #4] 800272a: 6013 str r3, [r2, #0] } 800272c: bf00 nop 800272e: 3708 adds r7, #8 8002730: 46bd mov sp, r7 8002732: bd80 pop {r7, pc} 8002734: 200002f4 .word 0x200002f4 8002738: 200002f8 .word 0x200002f8 0800273c : void GBT_StopEV(uint32_t causecode){ // --> Suspend EV 800273c: b580 push {r7, lr} 800273e: b082 sub sp, #8 8002740: af00 add r7, sp, #0 8002742: 6078 str r0, [r7, #4] if (GBT_EDCAN_Input.chargingError || GBT_EDCAN_Output.outputError){ 8002744: 4b0e ldr r3, [pc, #56] @ (8002780 ) 8002746: 799b ldrb r3, [r3, #6] 8002748: 2b00 cmp r3, #0 800274a: d103 bne.n 8002754 800274c: 4b0d ldr r3, [pc, #52] @ (8002784 ) 800274e: 7b5b ldrb r3, [r3, #13] 8002750: 2b00 cmp r3, #0 8002752: d003 beq.n 800275c GBT_StopSource = GBT_STOP_EVSE; 8002754: 4b0c ldr r3, [pc, #48] @ (8002788 ) 8002756: 2200 movs r2, #0 8002758: 701a strb r2, [r3, #0] 800275a: e002 b.n 8002762 }else{ GBT_StopSource = GBT_STOP_EV; 800275c: 4b0a ldr r3, [pc, #40] @ (8002788 ) 800275e: 2201 movs r2, #1 8002760: 701a strb r2, [r3, #0] } GBT_StopCauseCode = causecode; 8002762: 4a0a ldr r2, [pc, #40] @ (800278c ) 8002764: 687b ldr r3, [r7, #4] 8002766: 6013 str r3, [r2, #0] if(GBT_State != GBT_STOP) GBT_SwitchState(GBT_STOP); 8002768: 4b09 ldr r3, [pc, #36] @ (8002790 ) 800276a: 781b ldrb r3, [r3, #0] 800276c: 2b22 cmp r3, #34 @ 0x22 800276e: d002 beq.n 8002776 8002770: 2022 movs r0, #34 @ 0x22 8002772: f7ff ff1d bl 80025b0 } 8002776: bf00 nop 8002778: 3708 adds r7, #8 800277a: 46bd mov sp, r7 800277c: bd80 pop {r7, pc} 800277e: bf00 nop 8002780: 200004c4 .word 0x200004c4 8002784: 200004b4 .word 0x200004b4 8002788: 200003a0 .word 0x200003a0 800278c: 20000398 .word 0x20000398 8002790: 200002ec .word 0x200002ec 08002794 : void GBT_StopEVSE(uint32_t causecode){ // --> Suspend EVSE 8002794: b580 push {r7, lr} 8002796: b082 sub sp, #8 8002798: af00 add r7, sp, #0 800279a: 6078 str r0, [r7, #4] GBT_StopSource = GBT_STOP_EVSE; 800279c: 4b08 ldr r3, [pc, #32] @ (80027c0 ) 800279e: 2200 movs r2, #0 80027a0: 701a strb r2, [r3, #0] GBT_StopCauseCode = causecode; 80027a2: 4a08 ldr r2, [pc, #32] @ (80027c4 ) 80027a4: 687b ldr r3, [r7, #4] 80027a6: 6013 str r3, [r2, #0] if(GBT_State != GBT_STOP) GBT_SwitchState(GBT_STOP); 80027a8: 4b07 ldr r3, [pc, #28] @ (80027c8 ) 80027aa: 781b ldrb r3, [r3, #0] 80027ac: 2b22 cmp r3, #34 @ 0x22 80027ae: d002 beq.n 80027b6 80027b0: 2022 movs r0, #34 @ 0x22 80027b2: f7ff fefd bl 80025b0 } 80027b6: bf00 nop 80027b8: 3708 adds r7, #8 80027ba: 46bd mov sp, r7 80027bc: bd80 pop {r7, pc} 80027be: bf00 nop 80027c0: 200003a0 .word 0x200003a0 80027c4: 20000398 .word 0x20000398 80027c8: 200002ec .word 0x200002ec 080027cc : void GBT_StopOCPP(uint32_t causecode){ // --> Finished 80027cc: b580 push {r7, lr} 80027ce: b082 sub sp, #8 80027d0: af00 add r7, sp, #0 80027d2: 6078 str r0, [r7, #4] GBT_StopSource = GBT_STOP_OCPP; 80027d4: 4b08 ldr r3, [pc, #32] @ (80027f8 ) 80027d6: 2202 movs r2, #2 80027d8: 701a strb r2, [r3, #0] GBT_StopCauseCode = causecode; 80027da: 4a08 ldr r2, [pc, #32] @ (80027fc ) 80027dc: 687b ldr r3, [r7, #4] 80027de: 6013 str r3, [r2, #0] if(GBT_State != GBT_STOP) GBT_SwitchState(GBT_STOP); 80027e0: 4b07 ldr r3, [pc, #28] @ (8002800 ) 80027e2: 781b ldrb r3, [r3, #0] 80027e4: 2b22 cmp r3, #34 @ 0x22 80027e6: d002 beq.n 80027ee 80027e8: 2022 movs r0, #34 @ 0x22 80027ea: f7ff fee1 bl 80025b0 } 80027ee: bf00 nop 80027f0: 3708 adds r7, #8 80027f2: 46bd mov sp, r7 80027f4: bd80 pop {r7, pc} 80027f6: bf00 nop 80027f8: 200003a0 .word 0x200003a0 80027fc: 20000398 .word 0x20000398 8002800: 200002ec .word 0x200002ec 08002804 : void GBT_ForceStop(){ // --> Suspend EV 8002804: b580 push {r7, lr} 8002806: af00 add r7, sp, #0 GBT_StopSource = GBT_STOP_EV; 8002808: 4b08 ldr r3, [pc, #32] @ (800282c ) 800280a: 2201 movs r2, #1 800280c: 701a strb r2, [r3, #0] GBT_EDCAN_Output.enablePSU = 0; 800280e: 4b08 ldr r3, [pc, #32] @ (8002830 ) 8002810: 2200 movs r2, #0 8002812: 701a strb r2, [r3, #0] GBT_SwitchState(GBT_COMPLETE); 8002814: 2025 movs r0, #37 @ 0x25 8002816: f7ff fecb bl 80025b0 GBT_Lock(0); 800281a: 2000 movs r0, #0 800281c: f001 fd20 bl 8004260 RELAY_Write(RELAY_AUX, 0); 8002820: 2100 movs r1, #0 8002822: 2000 movs r0, #0 8002824: f7fe ff6c bl 8001700 } 8002828: bf00 nop 800282a: bd80 pop {r7, pc} 800282c: 200003a0 .word 0x200003a0 8002830: 200004b4 .word 0x200004b4 08002834 : void GBT_Error(uint32_t errorcode){ // --> Suspend EV 8002834: b580 push {r7, lr} 8002836: b082 sub sp, #8 8002838: af00 add r7, sp, #0 800283a: 6078 str r0, [r7, #4] GBT_StopSource = GBT_STOP_EV; 800283c: 4b08 ldr r3, [pc, #32] @ (8002860 ) 800283e: 2201 movs r2, #1 8002840: 701a strb r2, [r3, #0] EDCAN_printf(LOG_WARN, "GBT Error code: 0x%X\n", errorcode); 8002842: 687a ldr r2, [r7, #4] 8002844: 4907 ldr r1, [pc, #28] @ (8002864 ) 8002846: 2004 movs r0, #4 8002848: f002 fa96 bl 8004d78 GBT_ErrorCode = errorcode; 800284c: 4a06 ldr r2, [pc, #24] @ (8002868 ) 800284e: 687b ldr r3, [r7, #4] 8002850: 6013 str r3, [r2, #0] GBT_SwitchState(GBT_ERROR); 8002852: 2024 movs r0, #36 @ 0x24 8002854: f7ff feac bl 80025b0 } 8002858: bf00 nop 800285a: 3708 adds r7, #8 800285c: 46bd mov sp, r7 800285e: bd80 pop {r7, pc} 8002860: 200003a0 .word 0x200003a0 8002864: 0800d9a8 .word 0x0800d9a8 8002868: 2000039c .word 0x2000039c 0800286c : void GBT_Reset(){ 800286c: b580 push {r7, lr} 800286e: af00 add r7, sp, #0 GBT_BAT_INFO_recv = 0; 8002870: 4b32 ldr r3, [pc, #200] @ (800293c ) 8002872: 2200 movs r2, #0 8002874: 701a strb r2, [r3, #0] GBT_BAT_STAT_recv = 0; 8002876: 4b32 ldr r3, [pc, #200] @ (8002940 ) 8002878: 2200 movs r2, #0 800287a: 701a strb r2, [r3, #0] GBT_BRO_recv = 0; 800287c: 4b31 ldr r3, [pc, #196] @ (8002944 ) 800287e: 2200 movs r2, #0 8002880: 701a strb r2, [r3, #0] GBT_BHM_recv = 0; 8002882: 4b31 ldr r3, [pc, #196] @ (8002948 ) 8002884: 2200 movs r2, #0 8002886: 701a strb r2, [r3, #0] GBT_BSD_recv = 0; 8002888: 4b30 ldr r3, [pc, #192] @ (800294c ) 800288a: 2200 movs r2, #0 800288c: 701a strb r2, [r3, #0] EV_ready = 0; 800288e: 4b30 ldr r3, [pc, #192] @ (8002950 ) 8002890: 2200 movs r2, #0 8002892: 701a strb r2, [r3, #0] GBT_EDCAN_Output.chargingPercentage = 0; 8002894: 4b2f ldr r3, [pc, #188] @ (8002954 ) 8002896: 2200 movs r2, #0 8002898: 719a strb r2, [r3, #6] GBT_EDCAN_Output.enablePSU = 0; 800289a: 4b2e ldr r3, [pc, #184] @ (8002954 ) 800289c: 2200 movs r2, #0 800289e: 701a strb r2, [r3, #0] GBT_EDCAN_Output.requestedCurrent = 0; 80028a0: 4b2c ldr r3, [pc, #176] @ (8002954 ) 80028a2: 2200 movs r2, #0 80028a4: 70da strb r2, [r3, #3] 80028a6: 2200 movs r2, #0 80028a8: 711a strb r2, [r3, #4] GBT_EDCAN_Output.requestedVoltage = 500; 80028aa: 4b2a ldr r3, [pc, #168] @ (8002954 ) 80028ac: 2200 movs r2, #0 80028ae: f062 020b orn r2, r2, #11 80028b2: 705a strb r2, [r3, #1] 80028b4: 2200 movs r2, #0 80028b6: f042 0201 orr.w r2, r2, #1 80028ba: 709a strb r2, [r3, #2] GBT_EDCAN_Output.outputError = 0; 80028bc: 4b25 ldr r3, [pc, #148] @ (8002954 ) 80028be: 2200 movs r2, #0 80028c0: 735a strb r2, [r3, #13] memset(&GBT_EVInfo, 0, sizeof (GBT_EVInfo)); 80028c2: 2231 movs r2, #49 @ 0x31 80028c4: 2100 movs r1, #0 80028c6: 4824 ldr r0, [pc, #144] @ (8002958 ) 80028c8: f007 fc00 bl 800a0cc memset(&GBT_BATStat, 0, sizeof (GBT_BATStat)); 80028cc: 220d movs r2, #13 80028ce: 2100 movs r1, #0 80028d0: 4822 ldr r0, [pc, #136] @ (800295c ) 80028d2: f007 fbfb bl 800a0cc memset(&GBT_ReqPower, 0, sizeof (GBT_ReqPower)); 80028d6: 2205 movs r2, #5 80028d8: 2100 movs r1, #0 80028da: 4821 ldr r0, [pc, #132] @ (8002960 ) 80028dc: f007 fbf6 bl 800a0cc memset(&GBT_CurrPower, 0, sizeof (GBT_CurrPower)); 80028e0: 2205 movs r2, #5 80028e2: 2100 movs r1, #0 80028e4: 481f ldr r0, [pc, #124] @ (8002964 ) 80028e6: f007 fbf1 bl 800a0cc memset(&GBT_MaxVoltage, 0, sizeof (GBT_MaxVoltage)); 80028ea: 2202 movs r2, #2 80028ec: 2100 movs r1, #0 80028ee: 481e ldr r0, [pc, #120] @ (8002968 ) 80028f0: f007 fbec bl 800a0cc memset(&GBT_ChargingStatus, 0, sizeof (GBT_ChargingStatus)); 80028f4: 2209 movs r2, #9 80028f6: 2100 movs r1, #0 80028f8: 481c ldr r0, [pc, #112] @ (800296c ) 80028fa: f007 fbe7 bl 800a0cc memset(&GBT_BatteryStatus, 0, sizeof (GBT_BatteryStatus)); 80028fe: 2207 movs r2, #7 8002900: 2100 movs r1, #0 8002902: 481b ldr r0, [pc, #108] @ (8002970 ) 8002904: f007 fbe2 bl 800a0cc memset(&GBT_ChargerCurrentStatus, 0, sizeof (GBT_ChargerCurrentStatus)); 8002908: 2208 movs r2, #8 800290a: 2100 movs r1, #0 800290c: 4819 ldr r0, [pc, #100] @ (8002974 ) 800290e: f007 fbdd bl 800a0cc memset(&GBT_ChargerStop, 0, sizeof (GBT_ChargerStop)); 8002912: 2208 movs r2, #8 8002914: 2100 movs r1, #0 8002916: 4818 ldr r0, [pc, #96] @ (8002978 ) 8002918: f007 fbd8 bl 800a0cc GBT_CurrPower.requestedCurrent = 4000; //0A 800291c: 4b11 ldr r3, [pc, #68] @ (8002964 ) 800291e: f44f 627a mov.w r2, #4000 @ 0xfa0 8002922: 805a strh r2, [r3, #2] GBT_CurrPower.requestedVoltage = 500; //50V 8002924: 4b0f ldr r3, [pc, #60] @ (8002964 ) 8002926: f44f 72fa mov.w r2, #500 @ 0x1f4 800292a: 801a strh r2, [r3, #0] GBT_TimeChargingStarted = 0; 800292c: 4b13 ldr r3, [pc, #76] @ (800297c ) 800292e: 2200 movs r2, #0 8002930: 601a str r2, [r3, #0] GBT_BRO = 0x00; 8002932: 4b13 ldr r3, [pc, #76] @ (8002980 ) 8002934: 2200 movs r2, #0 8002936: 701a strb r2, [r3, #0] } 8002938: bf00 nop 800293a: bd80 pop {r7, pc} 800293c: 200002fc .word 0x200002fc 8002940: 200002fd .word 0x200002fd 8002944: 200002fe .word 0x200002fe 8002948: 200002ff .word 0x200002ff 800294c: 20000300 .word 0x20000300 8002950: 20000301 .word 0x20000301 8002954: 200004b4 .word 0x200004b4 8002958: 20000318 .word 0x20000318 800295c: 2000034c .word 0x2000034c 8002960: 2000035c .word 0x2000035c 8002964: 20000364 .word 0x20000364 8002968: 20000314 .word 0x20000314 800296c: 2000036c .word 0x2000036c 8002970: 20000378 .word 0x20000378 8002974: 20000380 .word 0x20000380 8002978: 20000388 .word 0x20000388 800297c: 20000394 .word 0x20000394 8002980: 20000390 .word 0x20000390 08002984 : void GBT_Start(){ 8002984: b580 push {r7, lr} 8002986: af00 add r7, sp, #0 RELAY_Write(RELAY_AUX, 1); 8002988: 2101 movs r1, #1 800298a: 2000 movs r0, #0 800298c: f7fe feb8 bl 8001700 GBT_SwitchState(GBT_S3_STARTED); 8002990: 2013 movs r0, #19 8002992: f7ff fe0d bl 80025b0 } 8002996: bf00 nop 8002998: bd80 pop {r7, pc} 0800299a : extern GBT_EDCAN_Output_t GBT_EDCAN_Output; extern GBT_EDCAN_Input_t GBT_EDCAN_Input; uint8_t CC_STATE_FILTERED; void CONN_Init(){ 800299a: b580 push {r7, lr} 800299c: af00 add r7, sp, #0 CONN_SetState(CONN_Initializing); 800299e: 2001 movs r0, #1 80029a0: f000 f8f6 bl 8002b90 } 80029a4: bf00 nop 80029a6: bd80 pop {r7, pc} 080029a8 : void CONN_Task(){ 80029a8: b580 push {r7, lr} 80029aa: af00 add r7, sp, #0 switch (connectorState){ 80029ac: 4b74 ldr r3, [pc, #464] @ (8002b80 ) 80029ae: 781b ldrb r3, [r3, #0] 80029b0: 3b01 subs r3, #1 80029b2: 2b07 cmp r3, #7 80029b4: f200 80d0 bhi.w 8002b58 80029b8: a201 add r2, pc, #4 @ (adr r2, 80029c0 ) 80029ba: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80029be: bf00 nop 80029c0: 080029e1 .word 0x080029e1 80029c4: 080029ef .word 0x080029ef 80029c8: 08002a15 .word 0x08002a15 80029cc: 08002a5b .word 0x08002a5b 80029d0: 08002a9f .word 0x08002a9f 80029d4: 08002b2d .word 0x08002b2d 80029d8: 08002ae5 .word 0x08002ae5 80029dc: 08002b09 .word 0x08002b09 case CONN_Initializing: // unlocked GBT_Lock(0); 80029e0: 2000 movs r0, #0 80029e2: f001 fc3d bl 8004260 CONN_SetState(CONN_Available); 80029e6: 2003 movs r0, #3 80029e8: f000 f8d2 bl 8002b90 break; 80029ec: e0c5 b.n 8002b7a case CONN_Faulted: //unlocked GBT_Lock(0); 80029ee: 2000 movs r0, #0 80029f0: f001 fc36 bl 8004260 if(GBT_EDCAN_Input.chargingError == 0) CONN_SetState(CONN_Available); 80029f4: 4b63 ldr r3, [pc, #396] @ (8002b84 ) 80029f6: 799b ldrb r3, [r3, #6] 80029f8: 2b00 cmp r3, #0 80029fa: d102 bne.n 8002a02 80029fc: 2003 movs r0, #3 80029fe: f000 f8c7 bl 8002b90 if(GBT_EDCAN_Input.chargeControl == FORCE_UNLOCK) GBT_ForceLock(0); 8002a02: 4b60 ldr r3, [pc, #384] @ (8002b84 ) 8002a04: 795b ldrb r3, [r3, #5] 8002a06: 2b03 cmp r3, #3 8002a08: f040 80aa bne.w 8002b60 8002a0c: 2000 movs r0, #0 8002a0e: f001 fbf1 bl 80041f4 break; 8002a12: e0a5 b.n 8002b60 case CONN_Available: //unlocked, waiting to connect GBT_Lock(0); 8002a14: 2000 movs r0, #0 8002a16: f001 fc23 bl 8004260 if(GBT_EDCAN_Input.chargingError != 0) CONN_SetState(CONN_Faulted); 8002a1a: 4b5a ldr r3, [pc, #360] @ (8002b84 ) 8002a1c: 799b ldrb r3, [r3, #6] 8002a1e: 2b00 cmp r3, #0 8002a20: d002 beq.n 8002a28 8002a22: 2002 movs r0, #2 8002a24: f000 f8b4 bl 8002b90 if(GBT_EDCAN_Input.chargeControl == FORCE_UNLOCK) GBT_ForceLock(0); 8002a28: 4b56 ldr r3, [pc, #344] @ (8002b84 ) 8002a2a: 795b ldrb r3, [r3, #5] 8002a2c: 2b03 cmp r3, #3 8002a2e: d102 bne.n 8002a36 8002a30: 2000 movs r0, #0 8002a32: f001 fbdf bl 80041f4 if((CONN_CC_GetState()==GBT_CC_4V) && (GBT_EDCAN_Input.chargeControl != FORCE_UNLOCK)){ // Исправить 8002a36: f000 f94b bl 8002cd0 8002a3a: 4603 mov r3, r0 8002a3c: 2b03 cmp r3, #3 8002a3e: f040 8091 bne.w 8002b64 8002a42: 4b50 ldr r3, [pc, #320] @ (8002b84 ) 8002a44: 795b ldrb r3, [r3, #5] 8002a46: 2b03 cmp r3, #3 8002a48: f000 808c beq.w 8002b64 CONN_SetState(CONN_Preparing); 8002a4c: 2004 movs r0, #4 8002a4e: f000 f89f bl 8002b90 GBT_Lock(1); 8002a52: 2001 movs r0, #1 8002a54: f001 fc04 bl 8004260 } break; 8002a58: e084 b.n 8002b64 // Выйти из двух состояний в Finished если force unlock case CONN_Preparing: //unlocked, waiting to charge GBT_Lock(0); 8002a5a: 2000 movs r0, #0 8002a5c: f001 fc00 bl 8004260 if(GBT_EDCAN_Input.chargeControl == FORCE_UNLOCK) GBT_ForceLock(0); 8002a60: 4b48 ldr r3, [pc, #288] @ (8002b84 ) 8002a62: 795b ldrb r3, [r3, #5] 8002a64: 2b03 cmp r3, #3 8002a66: d102 bne.n 8002a6e 8002a68: 2000 movs r0, #0 8002a6a: f001 fbc3 bl 80041f4 if(CONN_CC_GetState()==GBT_CC_4V){ 8002a6e: f000 f92f bl 8002cd0 8002a72: 4603 mov r3, r0 8002a74: 2b03 cmp r3, #3 8002a76: d10e bne.n 8002a96 if(GBT_EDCAN_Input.chargeControl == CHARGING_ALLOWED){ 8002a78: 4b42 ldr r3, [pc, #264] @ (8002b84 ) 8002a7a: 795b ldrb r3, [r3, #5] 8002a7c: 2b02 cmp r3, #2 8002a7e: d102 bne.n 8002a86 // RELAY_Write(RELAY_AUX, 1); // GBT_Start(); CONN_SetState(CONN_Charging); 8002a80: 2005 movs r0, #5 8002a82: f000 f885 bl 8002b90 } if(GBT_EDCAN_Input.chargeControl == FORCE_UNLOCK){ 8002a86: 4b3f ldr r3, [pc, #252] @ (8002b84 ) 8002a88: 795b ldrb r3, [r3, #5] 8002a8a: 2b03 cmp r3, #3 8002a8c: d16c bne.n 8002b68 CONN_SetState(CONN_Available);//TODO: CONN_Occupied_complete 8002a8e: 2003 movs r0, #3 8002a90: f000 f87e bl 8002b90 } //if (CHARGING_NOT_ALLOWED) stay here }else{ CONN_SetState(CONN_Available); } break; 8002a94: e068 b.n 8002b68 CONN_SetState(CONN_Available); 8002a96: 2003 movs r0, #3 8002a98: f000 f87a bl 8002b90 break; 8002a9c: e064 b.n 8002b68 case CONN_Charging://charging, locked GBT_Lock(1); 8002a9e: 2001 movs r0, #1 8002aa0: f001 fbde bl 8004260 if(GBT_State == GBT_COMPLETE){ 8002aa4: 4b38 ldr r3, [pc, #224] @ (8002b88 ) 8002aa6: 781b ldrb r3, [r3, #0] 8002aa8: 2b25 cmp r3, #37 @ 0x25 8002aaa: d15f bne.n 8002b6c if(GBT_StopSource == GBT_STOP_EVSE){ 8002aac: 4b37 ldr r3, [pc, #220] @ (8002b8c ) 8002aae: 781b ldrb r3, [r3, #0] 8002ab0: 2b00 cmp r3, #0 8002ab2: d103 bne.n 8002abc CONN_SetState(CONN_Suspended_EVSE); 8002ab4: 2008 movs r0, #8 8002ab6: f000 f86b bl 8002b90 CONN_SetState(CONN_Suspended_EVSE); } }//FIXME // break; 8002aba: e057 b.n 8002b6c }else if(GBT_StopSource == GBT_STOP_EV){ 8002abc: 4b33 ldr r3, [pc, #204] @ (8002b8c ) 8002abe: 781b ldrb r3, [r3, #0] 8002ac0: 2b01 cmp r3, #1 8002ac2: d103 bne.n 8002acc CONN_SetState(CONN_Suspended_EV); 8002ac4: 2007 movs r0, #7 8002ac6: f000 f863 bl 8002b90 break; 8002aca: e04f b.n 8002b6c }else if(GBT_StopSource == GBT_STOP_OCPP){ 8002acc: 4b2f ldr r3, [pc, #188] @ (8002b8c ) 8002ace: 781b ldrb r3, [r3, #0] 8002ad0: 2b02 cmp r3, #2 8002ad2: d103 bne.n 8002adc CONN_SetState(CONN_Finishing); 8002ad4: 2006 movs r0, #6 8002ad6: f000 f85b bl 8002b90 break; 8002ada: e047 b.n 8002b6c CONN_SetState(CONN_Suspended_EVSE); 8002adc: 2008 movs r0, #8 8002ade: f000 f857 bl 8002b90 break; 8002ae2: e043 b.n 8002b6c case CONN_Suspended_EV://charging completed by EV, waiting to transaction stop GBT_Lock(0); 8002ae4: 2000 movs r0, #0 8002ae6: f001 fbbb bl 8004260 if(GBT_EDCAN_Input.chargeControl == CHARGING_NOT_ALLOWED) CONN_SetState(CONN_Finishing); 8002aea: 4b26 ldr r3, [pc, #152] @ (8002b84 ) 8002aec: 795b ldrb r3, [r3, #5] 8002aee: 2b01 cmp r3, #1 8002af0: d102 bne.n 8002af8 8002af2: 2006 movs r0, #6 8002af4: f000 f84c bl 8002b90 if(GBT_EDCAN_Input.chargeControl == FORCE_UNLOCK) CONN_SetState(CONN_Finishing); // --> Finished 8002af8: 4b22 ldr r3, [pc, #136] @ (8002b84 ) 8002afa: 795b ldrb r3, [r3, #5] 8002afc: 2b03 cmp r3, #3 8002afe: d137 bne.n 8002b70 8002b00: 2006 movs r0, #6 8002b02: f000 f845 bl 8002b90 break; 8002b06: e033 b.n 8002b70 case CONN_Suspended_EVSE://charging completed by EVSE, waiting to transaction stop GBT_Lock(0); 8002b08: 2000 movs r0, #0 8002b0a: f001 fba9 bl 8004260 if(GBT_EDCAN_Input.chargeControl == CHARGING_NOT_ALLOWED) CONN_SetState(CONN_Finishing); 8002b0e: 4b1d ldr r3, [pc, #116] @ (8002b84 ) 8002b10: 795b ldrb r3, [r3, #5] 8002b12: 2b01 cmp r3, #1 8002b14: d102 bne.n 8002b1c 8002b16: 2006 movs r0, #6 8002b18: f000 f83a bl 8002b90 if(GBT_EDCAN_Input.chargeControl == FORCE_UNLOCK) CONN_SetState(CONN_Finishing); // --> Finished 8002b1c: 4b19 ldr r3, [pc, #100] @ (8002b84 ) 8002b1e: 795b ldrb r3, [r3, #5] 8002b20: 2b03 cmp r3, #3 8002b22: d127 bne.n 8002b74 8002b24: 2006 movs r0, #6 8002b26: f000 f833 bl 8002b90 break; 8002b2a: e023 b.n 8002b74 case CONN_Finishing://charging completed, waiting to disconnect, unlocked GBT_Lock(0); 8002b2c: 2000 movs r0, #0 8002b2e: f001 fb97 bl 8004260 //TODO Force unlock time limit if(GBT_EDCAN_Input.chargeControl == FORCE_UNLOCK) GBT_ForceLock(0); 8002b32: 4b14 ldr r3, [pc, #80] @ (8002b84 ) 8002b34: 795b ldrb r3, [r3, #5] 8002b36: 2b03 cmp r3, #3 8002b38: d102 bne.n 8002b40 8002b3a: 2000 movs r0, #0 8002b3c: f001 fb5a bl 80041f4 if(CONN_CC_GetState()==GBT_CC_6V){ 8002b40: f000 f8c6 bl 8002cd0 8002b44: 4603 mov r3, r0 8002b46: 2b02 cmp r3, #2 8002b48: d116 bne.n 8002b78 GBT_Lock(0); 8002b4a: 2000 movs r0, #0 8002b4c: f001 fb88 bl 8004260 CONN_SetState(CONN_Available); 8002b50: 2003 movs r0, #3 8002b52: f000 f81d bl 8002b90 } break; 8002b56: e00f b.n 8002b78 default: CONN_SetState(CONN_Initializing); 8002b58: 2001 movs r0, #1 8002b5a: f000 f819 bl 8002b90 } } 8002b5e: e00c b.n 8002b7a break; 8002b60: bf00 nop 8002b62: e00a b.n 8002b7a break; 8002b64: bf00 nop 8002b66: e008 b.n 8002b7a break; 8002b68: bf00 nop 8002b6a: e006 b.n 8002b7a break; 8002b6c: bf00 nop 8002b6e: e004 b.n 8002b7a break; 8002b70: bf00 nop 8002b72: e002 b.n 8002b7a break; 8002b74: bf00 nop 8002b76: e000 b.n 8002b7a break; 8002b78: bf00 nop } 8002b7a: bf00 nop 8002b7c: bd80 pop {r7, pc} 8002b7e: bf00 nop 8002b80: 200003a1 .word 0x200003a1 8002b84: 200004c4 .word 0x200004c4 8002b88: 200002ec .word 0x200002ec 8002b8c: 200003a0 .word 0x200003a0 08002b90 : //external //CONN_SetState(CONN_Error); //CONN_SetState(CONN_Occupied_charging); //CONN_SetState(CONN_Occupied_Complete); void CONN_SetState(CONN_State_t state){ 8002b90: b580 push {r7, lr} 8002b92: b082 sub sp, #8 8002b94: af00 add r7, sp, #0 8002b96: 4603 mov r3, r0 8002b98: 71fb strb r3, [r7, #7] connectorState = state; 8002b9a: 4a25 ldr r2, [pc, #148] @ (8002c30 ) 8002b9c: 79fb ldrb r3, [r7, #7] 8002b9e: 7013 strb r3, [r2, #0] if(connectorState == CONN_Initializing) EDCAN_printf(LOG_INFO,"CONN_Initializing\n"); 8002ba0: 4b23 ldr r3, [pc, #140] @ (8002c30 ) 8002ba2: 781b ldrb r3, [r3, #0] 8002ba4: 2b01 cmp r3, #1 8002ba6: d103 bne.n 8002bb0 8002ba8: 4922 ldr r1, [pc, #136] @ (8002c34 ) 8002baa: 2006 movs r0, #6 8002bac: f002 f8e4 bl 8004d78 if(connectorState == CONN_Faulted) EDCAN_printf(LOG_INFO,"CONN_Faulted\n"); 8002bb0: 4b1f ldr r3, [pc, #124] @ (8002c30 ) 8002bb2: 781b ldrb r3, [r3, #0] 8002bb4: 2b02 cmp r3, #2 8002bb6: d103 bne.n 8002bc0 8002bb8: 491f ldr r1, [pc, #124] @ (8002c38 ) 8002bba: 2006 movs r0, #6 8002bbc: f002 f8dc bl 8004d78 if(connectorState == CONN_Available) EDCAN_printf(LOG_INFO,"CONN_Available\n"); 8002bc0: 4b1b ldr r3, [pc, #108] @ (8002c30 ) 8002bc2: 781b ldrb r3, [r3, #0] 8002bc4: 2b03 cmp r3, #3 8002bc6: d103 bne.n 8002bd0 8002bc8: 491c ldr r1, [pc, #112] @ (8002c3c ) 8002bca: 2006 movs r0, #6 8002bcc: f002 f8d4 bl 8004d78 if(connectorState == CONN_Preparing) EDCAN_printf(LOG_INFO,"CONN_Preparing\n"); 8002bd0: 4b17 ldr r3, [pc, #92] @ (8002c30 ) 8002bd2: 781b ldrb r3, [r3, #0] 8002bd4: 2b04 cmp r3, #4 8002bd6: d103 bne.n 8002be0 8002bd8: 4919 ldr r1, [pc, #100] @ (8002c40 ) 8002bda: 2006 movs r0, #6 8002bdc: f002 f8cc bl 8004d78 if(connectorState == CONN_Charging) EDCAN_printf(LOG_INFO,"CONN_Charging\n"); 8002be0: 4b13 ldr r3, [pc, #76] @ (8002c30 ) 8002be2: 781b ldrb r3, [r3, #0] 8002be4: 2b05 cmp r3, #5 8002be6: d103 bne.n 8002bf0 8002be8: 4916 ldr r1, [pc, #88] @ (8002c44 ) 8002bea: 2006 movs r0, #6 8002bec: f002 f8c4 bl 8004d78 if(connectorState == CONN_Finishing) EDCAN_printf(LOG_INFO,"CONN_Finishing\n"); 8002bf0: 4b0f ldr r3, [pc, #60] @ (8002c30 ) 8002bf2: 781b ldrb r3, [r3, #0] 8002bf4: 2b06 cmp r3, #6 8002bf6: d103 bne.n 8002c00 8002bf8: 4913 ldr r1, [pc, #76] @ (8002c48 ) 8002bfa: 2006 movs r0, #6 8002bfc: f002 f8bc bl 8004d78 if(connectorState == CONN_Suspended_EV) EDCAN_printf(LOG_INFO,"CONN_Suspended_EV\n"); 8002c00: 4b0b ldr r3, [pc, #44] @ (8002c30 ) 8002c02: 781b ldrb r3, [r3, #0] 8002c04: 2b07 cmp r3, #7 8002c06: d103 bne.n 8002c10 8002c08: 4910 ldr r1, [pc, #64] @ (8002c4c ) 8002c0a: 2006 movs r0, #6 8002c0c: f002 f8b4 bl 8004d78 if(connectorState == CONN_Suspended_EVSE) EDCAN_printf(LOG_INFO,"CONN_Suspended_EVSE\n"); 8002c10: 4b07 ldr r3, [pc, #28] @ (8002c30 ) 8002c12: 781b ldrb r3, [r3, #0] 8002c14: 2b08 cmp r3, #8 8002c16: d103 bne.n 8002c20 8002c18: 490d ldr r1, [pc, #52] @ (8002c50 ) 8002c1a: 2006 movs r0, #6 8002c1c: f002 f8ac bl 8004d78 GBT_EDCAN_Output.connectorState = state; 8002c20: 4a0c ldr r2, [pc, #48] @ (8002c54 ) 8002c22: 79fb ldrb r3, [r7, #7] 8002c24: 7313 strb r3, [r2, #12] } 8002c26: bf00 nop 8002c28: 3708 adds r7, #8 8002c2a: 46bd mov sp, r7 8002c2c: bd80 pop {r7, pc} 8002c2e: bf00 nop 8002c30: 200003a1 .word 0x200003a1 8002c34: 0800d9c0 .word 0x0800d9c0 8002c38: 0800d9d4 .word 0x0800d9d4 8002c3c: 0800d9e4 .word 0x0800d9e4 8002c40: 0800d9f4 .word 0x0800d9f4 8002c44: 0800da04 .word 0x0800da04 8002c48: 0800da14 .word 0x0800da14 8002c4c: 0800da24 .word 0x0800da24 8002c50: 0800da38 .word 0x0800da38 8002c54: 200004b4 .word 0x200004b4 08002c58 : void CONN_CC_ReadStateFiltered() { 8002c58: b580 push {r7, lr} 8002c5a: b082 sub sp, #8 8002c5c: af00 add r7, sp, #0 static uint32_t last_change_time; static uint32_t last_check_time; static uint8_t prev_state; // if((last_check_time+100)>HAL_GetTick()) return; if((HAL_GetTick()-last_check_time)<100) return; 8002c5e: f002 fe1f bl 80058a0 8002c62: 4602 mov r2, r0 8002c64: 4b16 ldr r3, [pc, #88] @ (8002cc0 ) 8002c66: 681b ldr r3, [r3, #0] 8002c68: 1ad3 subs r3, r2, r3 8002c6a: 2b63 cmp r3, #99 @ 0x63 8002c6c: d924 bls.n 8002cb8 last_check_time = HAL_GetTick(); 8002c6e: f002 fe17 bl 80058a0 8002c72: 4603 mov r3, r0 8002c74: 4a12 ldr r2, [pc, #72] @ (8002cc0 ) 8002c76: 6013 str r3, [r2, #0] uint8_t new_state = CONN_CC_GetStateRaw(); 8002c78: f000 f834 bl 8002ce4 8002c7c: 4603 mov r3, r0 8002c7e: 71fb strb r3, [r7, #7] if (new_state != prev_state) { 8002c80: 4b10 ldr r3, [pc, #64] @ (8002cc4 ) 8002c82: 781b ldrb r3, [r3, #0] 8002c84: 79fa ldrb r2, [r7, #7] 8002c86: 429a cmp r2, r3 8002c88: d008 beq.n 8002c9c last_change_time = HAL_GetTick(); 8002c8a: f002 fe09 bl 80058a0 8002c8e: 4603 mov r3, r0 8002c90: 4a0d ldr r2, [pc, #52] @ (8002cc8 ) 8002c92: 6013 str r3, [r2, #0] prev_state = new_state; 8002c94: 4a0b ldr r2, [pc, #44] @ (8002cc4 ) 8002c96: 79fb ldrb r3, [r7, #7] 8002c98: 7013 strb r3, [r2, #0] 8002c9a: e00e b.n 8002cba } else if ((HAL_GetTick() - last_change_time) >= 300) { 8002c9c: f002 fe00 bl 80058a0 8002ca0: 4602 mov r2, r0 8002ca2: 4b09 ldr r3, [pc, #36] @ (8002cc8 ) 8002ca4: 681b ldr r3, [r3, #0] 8002ca6: 1ad3 subs r3, r2, r3 8002ca8: f5b3 7f96 cmp.w r3, #300 @ 0x12c 8002cac: d305 bcc.n 8002cba CC_STATE_FILTERED = prev_state; 8002cae: 4b05 ldr r3, [pc, #20] @ (8002cc4 ) 8002cb0: 781a ldrb r2, [r3, #0] 8002cb2: 4b06 ldr r3, [pc, #24] @ (8002ccc ) 8002cb4: 701a strb r2, [r3, #0] 8002cb6: e000 b.n 8002cba if((HAL_GetTick()-last_check_time)<100) return; 8002cb8: bf00 nop // case GBT_CC_2V: // printf("FGBT_CC_2V\n"); // break; // // } } 8002cba: 3708 adds r7, #8 8002cbc: 46bd mov sp, r7 8002cbe: bd80 pop {r7, pc} 8002cc0: 200003a4 .word 0x200003a4 8002cc4: 200003a8 .word 0x200003a8 8002cc8: 200003ac .word 0x200003ac 8002ccc: 200003a2 .word 0x200003a2 08002cd0 : uint8_t CONN_CC_GetState(){ 8002cd0: b480 push {r7} 8002cd2: af00 add r7, sp, #0 return CC_STATE_FILTERED; 8002cd4: 4b02 ldr r3, [pc, #8] @ (8002ce0 ) 8002cd6: 781b ldrb r3, [r3, #0] } 8002cd8: 4618 mov r0, r3 8002cda: 46bd mov sp, r7 8002cdc: bc80 pop {r7} 8002cde: 4770 bx lr 8002ce0: 200003a2 .word 0x200003a2 08002ce4 : uint8_t CONN_CC_GetStateRaw(){ 8002ce4: b580 push {r7, lr} 8002ce6: b082 sub sp, #8 8002ce8: af00 add r7, sp, #0 //Vin*k= 1.09v //12vin = 1353 ADC //TODO: Filter 100ms uint32_t adc; float volt; ADC_Select_Channel(ADC_CHANNEL_6); 8002cea: 2006 movs r0, #6 8002cec: f7fe fdf0 bl 80018d0 HAL_ADC_Start(&hadc1); 8002cf0: 482e ldr r0, [pc, #184] @ (8002dac ) 8002cf2: f002 fedb bl 8005aac HAL_ADC_PollForConversion(&hadc1, 100); 8002cf6: 2164 movs r1, #100 @ 0x64 8002cf8: 482c ldr r0, [pc, #176] @ (8002dac ) 8002cfa: f002 ffb1 bl 8005c60 adc = HAL_ADC_GetValue(&hadc1); 8002cfe: 482b ldr r0, [pc, #172] @ (8002dac ) 8002d00: f003 f8b4 bl 8005e6c 8002d04: 6078 str r0, [r7, #4] HAL_ADC_Stop(&hadc1); 8002d06: 4829 ldr r0, [pc, #164] @ (8002dac ) 8002d08: f002 ff7e bl 8005c08 volt = (float)adc/113.4f; 8002d0c: 6878 ldr r0, [r7, #4] 8002d0e: f7fe f837 bl 8000d80 <__aeabi_ui2f> 8002d12: 4603 mov r3, r0 8002d14: 4926 ldr r1, [pc, #152] @ (8002db0 ) 8002d16: 4618 mov r0, r3 8002d18: f7fe f93e bl 8000f98 <__aeabi_fdiv> 8002d1c: 4603 mov r3, r0 8002d1e: 603b str r3, [r7, #0] // if((volt<12.6f) && (volt>11.4f)) return GBT_CC_12V; // if((volt<6.8f) && (volt>5.2f)) return GBT_CC_6V; // if((volt<4.8f) && (volt>3.2f)) return GBT_CC_4V; // if((volt<2.8f) && (volt>1.2f)) return GBT_CC_2V; if((volt<13.0f) && (volt>11.0f)) return GBT_CC_12V; 8002d20: 4924 ldr r1, [pc, #144] @ (8002db4 ) 8002d22: 6838 ldr r0, [r7, #0] 8002d24: f7fe fa22 bl 800116c <__aeabi_fcmplt> 8002d28: 4603 mov r3, r0 8002d2a: 2b00 cmp r3, #0 8002d2c: d008 beq.n 8002d40 8002d2e: 4922 ldr r1, [pc, #136] @ (8002db8 ) 8002d30: 6838 ldr r0, [r7, #0] 8002d32: f7fe fa39 bl 80011a8 <__aeabi_fcmpgt> 8002d36: 4603 mov r3, r0 8002d38: 2b00 cmp r3, #0 8002d3a: d001 beq.n 8002d40 8002d3c: 2301 movs r3, #1 8002d3e: e031 b.n 8002da4 if((volt<7.2f) && (volt>4.8f)) return GBT_CC_6V; 8002d40: 491e ldr r1, [pc, #120] @ (8002dbc ) 8002d42: 6838 ldr r0, [r7, #0] 8002d44: f7fe fa12 bl 800116c <__aeabi_fcmplt> 8002d48: 4603 mov r3, r0 8002d4a: 2b00 cmp r3, #0 8002d4c: d008 beq.n 8002d60 8002d4e: 491c ldr r1, [pc, #112] @ (8002dc0 ) 8002d50: 6838 ldr r0, [r7, #0] 8002d52: f7fe fa29 bl 80011a8 <__aeabi_fcmpgt> 8002d56: 4603 mov r3, r0 8002d58: 2b00 cmp r3, #0 8002d5a: d001 beq.n 8002d60 8002d5c: 2302 movs r3, #2 8002d5e: e021 b.n 8002da4 if((volt<4.8f) && (volt>3.0f)) return GBT_CC_4V; 8002d60: 4917 ldr r1, [pc, #92] @ (8002dc0 ) 8002d62: 6838 ldr r0, [r7, #0] 8002d64: f7fe fa02 bl 800116c <__aeabi_fcmplt> 8002d68: 4603 mov r3, r0 8002d6a: 2b00 cmp r3, #0 8002d6c: d008 beq.n 8002d80 8002d6e: 4915 ldr r1, [pc, #84] @ (8002dc4 ) 8002d70: 6838 ldr r0, [r7, #0] 8002d72: f7fe fa19 bl 80011a8 <__aeabi_fcmpgt> 8002d76: 4603 mov r3, r0 8002d78: 2b00 cmp r3, #0 8002d7a: d001 beq.n 8002d80 8002d7c: 2303 movs r3, #3 8002d7e: e011 b.n 8002da4 if((volt<3.0f) && (volt>1.0f)) return GBT_CC_2V; 8002d80: 4910 ldr r1, [pc, #64] @ (8002dc4 ) 8002d82: 6838 ldr r0, [r7, #0] 8002d84: f7fe f9f2 bl 800116c <__aeabi_fcmplt> 8002d88: 4603 mov r3, r0 8002d8a: 2b00 cmp r3, #0 8002d8c: d009 beq.n 8002da2 8002d8e: f04f 517e mov.w r1, #1065353216 @ 0x3f800000 8002d92: 6838 ldr r0, [r7, #0] 8002d94: f7fe fa08 bl 80011a8 <__aeabi_fcmpgt> 8002d98: 4603 mov r3, r0 8002d9a: 2b00 cmp r3, #0 8002d9c: d001 beq.n 8002da2 8002d9e: 2304 movs r3, #4 8002da0: e000 b.n 8002da4 return GBT_CC_UNKNOWN; 8002da2: 2300 movs r3, #0 } 8002da4: 4618 mov r0, r3 8002da6: 3708 adds r7, #8 8002da8: 46bd mov sp, r7 8002daa: bd80 pop {r7, pc} 8002dac: 20000268 .word 0x20000268 8002db0: 42e2cccd .word 0x42e2cccd 8002db4: 41500000 .word 0x41500000 8002db8: 41300000 .word 0x41300000 8002dbc: 40e66666 .word 0x40e66666 8002dc0: 4099999a .word 0x4099999a 8002dc4: 40400000 .word 0x40400000 08002dc8 : float CONN_CC_GetAdc(){ 8002dc8: b580 push {r7, lr} 8002dca: b082 sub sp, #8 8002dcc: af00 add r7, sp, #0 //Vin*k= 1.09v //12vin = 1353 ADC uint32_t adc; float volt; ADC_Select_Channel(ADC_CHANNEL_6); 8002dce: 2006 movs r0, #6 8002dd0: f7fe fd7e bl 80018d0 HAL_ADC_Start(&hadc1); 8002dd4: 480e ldr r0, [pc, #56] @ (8002e10 ) 8002dd6: f002 fe69 bl 8005aac HAL_ADC_PollForConversion(&hadc1, 100); 8002dda: 2164 movs r1, #100 @ 0x64 8002ddc: 480c ldr r0, [pc, #48] @ (8002e10 ) 8002dde: f002 ff3f bl 8005c60 adc = HAL_ADC_GetValue(&hadc1); 8002de2: 480b ldr r0, [pc, #44] @ (8002e10 ) 8002de4: f003 f842 bl 8005e6c 8002de8: 6078 str r0, [r7, #4] HAL_ADC_Stop(&hadc1); 8002dea: 4809 ldr r0, [pc, #36] @ (8002e10 ) 8002dec: f002 ff0c bl 8005c08 volt = (float)adc/113.4f; 8002df0: 6878 ldr r0, [r7, #4] 8002df2: f7fd ffc5 bl 8000d80 <__aeabi_ui2f> 8002df6: 4603 mov r3, r0 8002df8: 4906 ldr r1, [pc, #24] @ (8002e14 ) 8002dfa: 4618 mov r0, r3 8002dfc: f7fe f8cc bl 8000f98 <__aeabi_fdiv> 8002e00: 4603 mov r3, r0 8002e02: 603b str r3, [r7, #0] return volt; 8002e04: 683b ldr r3, [r7, #0] } 8002e06: 4618 mov r0, r3 8002e08: 3708 adds r7, #8 8002e0a: 46bd mov sp, r7 8002e0c: bd80 pop {r7, pc} 8002e0e: bf00 nop 8002e10: 20000268 .word 0x20000268 8002e14: 42e2cccd .word 0x42e2cccd 08002e18 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 8002e18: b480 push {r7} 8002e1a: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 8002e1c: f3bf 8f4f dsb sy } 8002e20: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 8002e22: 4b06 ldr r3, [pc, #24] @ (8002e3c <__NVIC_SystemReset+0x24>) 8002e24: 68db ldr r3, [r3, #12] 8002e26: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8002e2a: 4904 ldr r1, [pc, #16] @ (8002e3c <__NVIC_SystemReset+0x24>) 8002e2c: 4b04 ldr r3, [pc, #16] @ (8002e40 <__NVIC_SystemReset+0x28>) 8002e2e: 4313 orrs r3, r2 8002e30: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 8002e32: f3bf 8f4f dsb sy } 8002e36: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 8002e38: bf00 nop 8002e3a: e7fd b.n 8002e38 <__NVIC_SystemReset+0x20> 8002e3c: e000ed00 .word 0xe000ed00 8002e40: 05fa0004 .word 0x05fa0004 08002e44 <_write>: extern UART_HandleTypeDef huart2; #if defined(__GNUC__) int _write(int fd, char * ptr, int len) { 8002e44: b580 push {r7, lr} 8002e46: b084 sub sp, #16 8002e48: af00 add r7, sp, #0 8002e4a: 60f8 str r0, [r7, #12] 8002e4c: 60b9 str r1, [r7, #8] 8002e4e: 607a str r2, [r7, #4] HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, 1); 8002e50: 2201 movs r2, #1 8002e52: 2110 movs r1, #16 8002e54: 480a ldr r0, [pc, #40] @ (8002e80 <_write+0x3c>) 8002e56: f004 fcec bl 8007832 HAL_UART_Transmit(&huart2, (uint8_t *) ptr, len, HAL_MAX_DELAY); 8002e5a: 687b ldr r3, [r7, #4] 8002e5c: b29a uxth r2, r3 8002e5e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002e62: 68b9 ldr r1, [r7, #8] 8002e64: 4807 ldr r0, [pc, #28] @ (8002e84 <_write+0x40>) 8002e66: f005 fe2b bl 8008ac0 HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, 0); 8002e6a: 2200 movs r2, #0 8002e6c: 2110 movs r1, #16 8002e6e: 4804 ldr r0, [pc, #16] @ (8002e80 <_write+0x3c>) 8002e70: f004 fcdf bl 8007832 return len; 8002e74: 687b ldr r3, [r7, #4] } 8002e76: 4618 mov r0, r3 8002e78: 3710 adds r7, #16 8002e7a: 46bd mov sp, r7 8002e7c: bd80 pop {r7, pc} 8002e7e: bf00 nop 8002e80: 40011400 .word 0x40011400 8002e84: 20003364 .word 0x20003364 08002e88 : #endif void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size){ 8002e88: b580 push {r7, lr} 8002e8a: b082 sub sp, #8 8002e8c: af00 add r7, sp, #0 8002e8e: 6078 str r0, [r7, #4] 8002e90: 460b mov r3, r1 8002e92: 807b strh r3, [r7, #2] // if(huart->Instance == USART1){ // mm_rx_interrupt(huart, Size); // } if(huart->Instance == USART2){ 8002e94: 687b ldr r3, [r7, #4] 8002e96: 681b ldr r3, [r3, #0] 8002e98: 4a05 ldr r2, [pc, #20] @ (8002eb0 ) 8002e9a: 4293 cmp r3, r2 8002e9c: d104 bne.n 8002ea8 debug_rx_interrupt(huart, Size); 8002e9e: 887b ldrh r3, [r7, #2] 8002ea0: 4619 mov r1, r3 8002ea2: 6878 ldr r0, [r7, #4] 8002ea4: f000 f806 bl 8002eb4 } } 8002ea8: bf00 nop 8002eaa: 3708 adds r7, #8 8002eac: 46bd mov sp, r7 8002eae: bd80 pop {r7, pc} 8002eb0: 40004400 .word 0x40004400 08002eb4 : void debug_rx_interrupt(UART_HandleTypeDef *huart, uint16_t Size){ 8002eb4: b480 push {r7} 8002eb6: b083 sub sp, #12 8002eb8: af00 add r7, sp, #0 8002eba: 6078 str r0, [r7, #4] 8002ebc: 460b mov r3, r1 8002ebe: 807b strh r3, [r7, #2] debug_rx_buffer[Size] = '\0'; 8002ec0: 887b ldrh r3, [r7, #2] 8002ec2: 4a07 ldr r2, [pc, #28] @ (8002ee0 ) 8002ec4: 2100 movs r1, #0 8002ec6: 54d1 strb r1, [r2, r3] debug_rx_buffer_size = Size; 8002ec8: 887b ldrh r3, [r7, #2] 8002eca: b2da uxtb r2, r3 8002ecc: 4b05 ldr r3, [pc, #20] @ (8002ee4 ) 8002ece: 701a strb r2, [r3, #0] debug_cmd_received = 1; 8002ed0: 4b05 ldr r3, [pc, #20] @ (8002ee8 ) 8002ed2: 2201 movs r2, #1 8002ed4: 701a strb r2, [r3, #0] } 8002ed6: bf00 nop 8002ed8: 370c adds r7, #12 8002eda: 46bd mov sp, r7 8002edc: bc80 pop {r7} 8002ede: 4770 bx lr 8002ee0: 200003b0 .word 0x200003b0 8002ee4: 200004b1 .word 0x200004b1 8002ee8: 200004b0 .word 0x200004b0 08002eec : void debug_init(){ 8002eec: b580 push {r7, lr} 8002eee: af00 add r7, sp, #0 HAL_UARTEx_ReceiveToIdle_IT(&huart2,debug_rx_buffer,255); 8002ef0: 22ff movs r2, #255 @ 0xff 8002ef2: 4903 ldr r1, [pc, #12] @ (8002f00 ) 8002ef4: 4803 ldr r0, [pc, #12] @ (8002f04 ) 8002ef6: f005 fe75 bl 8008be4 // mm_schedule_write(0x02, 0x00FF, 0xFFFF); //for (int i=0;i<60;i++) // mm_schedule_write(0x02, 0x0000, 0xFF00); // mm_schedule_write(0x01, 0x0000, 0x0100); // mm_schedule_write(0x01, 0x0000, 0x0100); } 8002efa: bf00 nop 8002efc: bd80 pop {r7, pc} 8002efe: bf00 nop 8002f00: 200003b0 .word 0x200003b0 8002f04: 20003364 .word 0x20003364 08002f08 : void parse_command(uint8_t* buffer, size_t length) { 8002f08: b5b0 push {r4, r5, r7, lr} 8002f0a: b086 sub sp, #24 8002f0c: af00 add r7, sp, #0 8002f0e: 6078 str r0, [r7, #4] 8002f10: 6039 str r1, [r7, #0] // ignore \r \n symbols size_t i = 0; 8002f12: 2300 movs r3, #0 8002f14: 617b str r3, [r7, #20] for (i = 0; i < length; i++) { 8002f16: 2300 movs r3, #0 8002f18: 617b str r3, [r7, #20] 8002f1a: e016 b.n 8002f4a if (buffer[i] == '\r' || buffer[i] == '\n') { 8002f1c: 687a ldr r2, [r7, #4] 8002f1e: 697b ldr r3, [r7, #20] 8002f20: 4413 add r3, r2 8002f22: 781b ldrb r3, [r3, #0] 8002f24: 2b0d cmp r3, #13 8002f26: d005 beq.n 8002f34 8002f28: 687a ldr r2, [r7, #4] 8002f2a: 697b ldr r3, [r7, #20] 8002f2c: 4413 add r3, r2 8002f2e: 781b ldrb r3, [r3, #0] 8002f30: 2b0a cmp r3, #10 8002f32: d107 bne.n 8002f44 buffer[i] = '\0'; 8002f34: 687a ldr r2, [r7, #4] 8002f36: 697b ldr r3, [r7, #20] 8002f38: 4413 add r3, r2 8002f3a: 2200 movs r2, #0 8002f3c: 701a strb r2, [r3, #0] length = i; 8002f3e: 697b ldr r3, [r7, #20] 8002f40: 603b str r3, [r7, #0] break; 8002f42: e006 b.n 8002f52 for (i = 0; i < length; i++) { 8002f44: 697b ldr r3, [r7, #20] 8002f46: 3301 adds r3, #1 8002f48: 617b str r3, [r7, #20] 8002f4a: 697a ldr r2, [r7, #20] 8002f4c: 683b ldr r3, [r7, #0] 8002f4e: 429a cmp r2, r3 8002f50: d3e4 bcc.n 8002f1c } } if (buffer[0] == 0) return; 8002f52: 687b ldr r3, [r7, #4] 8002f54: 781b ldrb r3, [r3, #0] 8002f56: 2b00 cmp r3, #0 8002f58: f000 82d4 beq.w 8003504 if (strncmp((const char*)buffer, "reset", length) == 0) { 8002f5c: 683a ldr r2, [r7, #0] 8002f5e: 49ad ldr r1, [pc, #692] @ (8003214 ) 8002f60: 6878 ldr r0, [r7, #4] 8002f62: f007 f8bb bl 800a0dc 8002f66: 4603 mov r3, r0 8002f68: 2b00 cmp r3, #0 8002f6a: d104 bne.n 8002f76 printf("Resetting...\n"); 8002f6c: 48aa ldr r0, [pc, #680] @ (8003218 ) 8002f6e: f007 f8a5 bl 800a0bc NVIC_SystemReset(); 8002f72: f7ff ff51 bl 8002e18 <__NVIC_SystemReset> } else if (strncmp((const char*)buffer, "relayaux", length) == 0) { 8002f76: 683a ldr r2, [r7, #0] 8002f78: 49a8 ldr r1, [pc, #672] @ (800321c ) 8002f7a: 6878 ldr r0, [r7, #4] 8002f7c: f007 f8ae bl 800a0dc 8002f80: 4603 mov r3, r0 8002f82: 2b00 cmp r3, #0 8002f84: d10e bne.n 8002fa4 printf("Relaying...\n"); 8002f86: 48a6 ldr r0, [pc, #664] @ (8003220 ) 8002f88: f007 f898 bl 800a0bc RELAY_Write(RELAY_AUX, 1); 8002f8c: 2101 movs r1, #1 8002f8e: 2000 movs r0, #0 8002f90: f7fe fbb6 bl 8001700 HAL_Delay(200); 8002f94: 20c8 movs r0, #200 @ 0xc8 8002f96: f002 fc8d bl 80058b4 RELAY_Write(RELAY_AUX, 0); 8002f9a: 2100 movs r1, #0 8002f9c: 2000 movs r0, #0 8002f9e: f7fe fbaf bl 8001700 8002fa2: e2b0 b.n 8003506 } else if (strncmp((const char*)buffer, "relaycc", length) == 0) { 8002fa4: 683a ldr r2, [r7, #0] 8002fa6: 499f ldr r1, [pc, #636] @ (8003224 ) 8002fa8: 6878 ldr r0, [r7, #4] 8002faa: f007 f897 bl 800a0dc 8002fae: 4603 mov r3, r0 8002fb0: 2b00 cmp r3, #0 8002fb2: d10e bne.n 8002fd2 printf("Relaying...\n"); 8002fb4: 489a ldr r0, [pc, #616] @ (8003220 ) 8002fb6: f007 f881 bl 800a0bc RELAY_Write(RELAY_CC, 1); 8002fba: 2101 movs r1, #1 8002fbc: 2001 movs r0, #1 8002fbe: f7fe fb9f bl 8001700 HAL_Delay(200); 8002fc2: 20c8 movs r0, #200 @ 0xc8 8002fc4: f002 fc76 bl 80058b4 RELAY_Write(RELAY_CC, 0); 8002fc8: 2100 movs r1, #0 8002fca: 2001 movs r0, #1 8002fcc: f7fe fb98 bl 8001700 8002fd0: e299 b.n 8003506 // } else if (strncmp((const char*)buffer, "voltage", length) == 0) { // printf("Voltaging...\n"); // mm_schedule_read(0x02, 0x0001); } else if (strncmp((const char*)buffer, "adc", length) == 0) { 8002fd2: 683a ldr r2, [r7, #0] 8002fd4: 4994 ldr r1, [pc, #592] @ (8003228 ) 8002fd6: 6878 ldr r0, [r7, #4] 8002fd8: f007 f880 bl 800a0dc 8002fdc: 4603 mov r3, r0 8002fde: 2b00 cmp r3, #0 8002fe0: d10b bne.n 8002ffa printf("CC1=%.2f\n", CONN_CC_GetAdc()); 8002fe2: f7ff fef1 bl 8002dc8 8002fe6: 4603 mov r3, r0 8002fe8: 4618 mov r0, r3 8002fea: f7fd fa93 bl 8000514 <__aeabi_f2d> 8002fee: 4602 mov r2, r0 8002ff0: 460b mov r3, r1 8002ff2: 488e ldr r0, [pc, #568] @ (800322c ) 8002ff4: f006 fffa bl 8009fec 8002ff8: e285 b.n 8003506 } else if (strncmp((const char*)buffer, "lock_state", length) == 0) { 8002ffa: 683a ldr r2, [r7, #0] 8002ffc: 498c ldr r1, [pc, #560] @ (8003230 ) 8002ffe: 6878 ldr r0, [r7, #4] 8003000: f007 f86c bl 800a0dc 8003004: 4603 mov r3, r0 8003006: 2b00 cmp r3, #0 8003008: d107 bne.n 800301a printf("Lock state=%d\n", GBT_LockGetState()); 800300a: f001 f90b bl 8004224 800300e: 4603 mov r3, r0 8003010: 4619 mov r1, r3 8003012: 4888 ldr r0, [pc, #544] @ (8003234 ) 8003014: f006 ffea bl 8009fec 8003018: e275 b.n 8003506 } else if (strncmp((const char*)buffer, "lock_lock", length) == 0) { 800301a: 683a ldr r2, [r7, #0] 800301c: 4986 ldr r1, [pc, #536] @ (8003238 ) 800301e: 6878 ldr r0, [r7, #4] 8003020: f007 f85c bl 800a0dc 8003024: 4603 mov r3, r0 8003026: 2b00 cmp r3, #0 8003028: d106 bne.n 8003038 printf("Locked\n"); 800302a: 4884 ldr r0, [pc, #528] @ (800323c ) 800302c: f007 f846 bl 800a0bc GBT_Lock(1); 8003030: 2001 movs r0, #1 8003032: f001 f915 bl 8004260 8003036: e266 b.n 8003506 } else if (strncmp((const char*)buffer, "lock_unlock", length) == 0) { 8003038: 683a ldr r2, [r7, #0] 800303a: 4981 ldr r1, [pc, #516] @ (8003240 ) 800303c: 6878 ldr r0, [r7, #4] 800303e: f007 f84d bl 800a0dc 8003042: 4603 mov r3, r0 8003044: 2b00 cmp r3, #0 8003046: d106 bne.n 8003056 printf("Unlocked\n"); 8003048: 487e ldr r0, [pc, #504] @ (8003244 ) 800304a: f007 f837 bl 800a0bc GBT_Lock(0); 800304e: 2000 movs r0, #0 8003050: f001 f906 bl 8004260 8003054: e257 b.n 8003506 } else if (strncmp((const char*)buffer, "complete", length) == 0) { 8003056: 683a ldr r2, [r7, #0] 8003058: 497b ldr r1, [pc, #492] @ (8003248 ) 800305a: 6878 ldr r0, [r7, #4] 800305c: f007 f83e bl 800a0dc 8003060: 4603 mov r3, r0 8003062: 2b00 cmp r3, #0 8003064: d103 bne.n 800306e CONN_SetState(CONN_Finishing); 8003066: 2006 movs r0, #6 8003068: f7ff fd92 bl 8002b90 800306c: e24b b.n 8003506 } else if (strncmp((const char*)buffer, "start", length) == 0) { 800306e: 683a ldr r2, [r7, #0] 8003070: 4976 ldr r1, [pc, #472] @ (800324c ) 8003072: 6878 ldr r0, [r7, #4] 8003074: f007 f832 bl 800a0dc 8003078: 4603 mov r3, r0 800307a: 2b00 cmp r3, #0 800307c: d105 bne.n 800308a printf("Started\n"); 800307e: 4874 ldr r0, [pc, #464] @ (8003250 ) 8003080: f007 f81c bl 800a0bc GBT_Start(); 8003084: f7ff fc7e bl 8002984 8003088: e23d b.n 8003506 } else if (strncmp((const char*)buffer, "stop", length) == 0) { 800308a: 683a ldr r2, [r7, #0] 800308c: 4971 ldr r1, [pc, #452] @ (8003254 ) 800308e: 6878 ldr r0, [r7, #4] 8003090: f007 f824 bl 800a0dc 8003094: 4603 mov r3, r0 8003096: 2b00 cmp r3, #0 8003098: d106 bne.n 80030a8 printf("Stopped\n"); 800309a: 486f ldr r0, [pc, #444] @ (8003258 ) 800309c: f007 f80e bl 800a0bc GBT_StopEVSE(GBT_CST_SUSPENDS_ARTIFICIALLY); 80030a0: 486e ldr r0, [pc, #440] @ (800325c ) 80030a2: f7ff fb77 bl 8002794 80030a6: e22e b.n 8003506 } else if (strncmp((const char*)buffer, "stop1", length) == 0) { 80030a8: 683a ldr r2, [r7, #0] 80030aa: 496d ldr r1, [pc, #436] @ (8003260 ) 80030ac: 6878 ldr r0, [r7, #4] 80030ae: f007 f815 bl 800a0dc 80030b2: 4603 mov r3, r0 80030b4: 2b00 cmp r3, #0 80030b6: d105 bne.n 80030c4 printf("Stopped\n"); 80030b8: 4867 ldr r0, [pc, #412] @ (8003258 ) 80030ba: f006 ffff bl 800a0bc GBT_ForceStop(); 80030be: f7ff fba1 bl 8002804 80030c2: e220 b.n 8003506 // printf("Stopped\n"); // GBT_Lock(1); // GBT_SwitchState(GBT_S2_LOCKED); // GBT_Delay(500); } else if (strncmp((const char*)buffer, "cc_state", length) == 0) { 80030c4: 683a ldr r2, [r7, #0] 80030c6: 4967 ldr r1, [pc, #412] @ (8003264 ) 80030c8: 6878 ldr r0, [r7, #4] 80030ca: f007 f807 bl 800a0dc 80030ce: 4603 mov r3, r0 80030d0: 2b00 cmp r3, #0 80030d2: d127 bne.n 8003124 switch(CONN_CC_GetState()){ 80030d4: f7ff fdfc bl 8002cd0 80030d8: 4603 mov r3, r0 80030da: 2b04 cmp r3, #4 80030dc: f200 8213 bhi.w 8003506 80030e0: a201 add r2, pc, #4 @ (adr r2, 80030e8 ) 80030e2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80030e6: bf00 nop 80030e8: 080030fd .word 0x080030fd 80030ec: 08003105 .word 0x08003105 80030f0: 0800310d .word 0x0800310d 80030f4: 08003115 .word 0x08003115 80030f8: 0800311d .word 0x0800311d case GBT_CC_UNKNOWN: printf("GBT_CC_UNKNOWN\n"); 80030fc: 485a ldr r0, [pc, #360] @ (8003268 ) 80030fe: f006 ffdd bl 800a0bc break; 8003102: e200 b.n 8003506 case GBT_CC_12V: printf("GBT_CC_12V\n"); 8003104: 4859 ldr r0, [pc, #356] @ (800326c ) 8003106: f006 ffd9 bl 800a0bc break; 800310a: e1fc b.n 8003506 case GBT_CC_6V: printf("GBT_CC_6V\n"); 800310c: 4858 ldr r0, [pc, #352] @ (8003270 ) 800310e: f006 ffd5 bl 800a0bc break; 8003112: e1f8 b.n 8003506 case GBT_CC_4V: printf("GBT_CC_4V\n"); 8003114: 4857 ldr r0, [pc, #348] @ (8003274 ) 8003116: f006 ffd1 bl 800a0bc break; 800311a: e1f4 b.n 8003506 case GBT_CC_2V: printf("GBT_CC_2V\n"); 800311c: 4856 ldr r0, [pc, #344] @ (8003278 ) 800311e: f006 ffcd bl 800a0bc break; 8003122: e1f0 b.n 8003506 } } else if (strncmp((const char*)buffer, "temp", length) == 0) { 8003124: 683a ldr r2, [r7, #0] 8003126: 4955 ldr r1, [pc, #340] @ (800327c ) 8003128: 6878 ldr r0, [r7, #4] 800312a: f006 ffd7 bl 800a0dc 800312e: 4603 mov r3, r0 8003130: 2b00 cmp r3, #0 8003132: d110 bne.n 8003156 printf("temp1 %d\n",GBT_ReadTemp(0)); 8003134: 2000 movs r0, #0 8003136: f7fe fb85 bl 8001844 800313a: 4603 mov r3, r0 800313c: 4619 mov r1, r3 800313e: 4850 ldr r0, [pc, #320] @ (8003280 ) 8003140: f006 ff54 bl 8009fec printf("temp2 %d\n",GBT_ReadTemp(1)); 8003144: 2001 movs r0, #1 8003146: f7fe fb7d bl 8001844 800314a: 4603 mov r3, r0 800314c: 4619 mov r1, r3 800314e: 484d ldr r0, [pc, #308] @ (8003284 ) 8003150: f006 ff4c bl 8009fec 8003154: e1d7 b.n 8003506 } else if (strncmp((const char*)buffer, "info1", length) == 0) { 8003156: 683a ldr r2, [r7, #0] 8003158: 494b ldr r1, [pc, #300] @ (8003288 ) 800315a: 6878 ldr r0, [r7, #4] 800315c: f006 ffbe bl 800a0dc 8003160: 4603 mov r3, r0 8003162: 2b00 cmp r3, #0 8003164: f040 80a6 bne.w 80032b4 printf("Battery info:\n"); 8003168: 4848 ldr r0, [pc, #288] @ (800328c ) 800316a: f006 ffa7 bl 800a0bc printf("maxCV %dV\n",GBT_BATStat.maxCellVoltage/100); // 0.01v/bit 800316e: 4b48 ldr r3, [pc, #288] @ (8003290 ) 8003170: 881b ldrh r3, [r3, #0] 8003172: b29b uxth r3, r3 8003174: 4a47 ldr r2, [pc, #284] @ (8003294 ) 8003176: fba2 2303 umull r2, r3, r2, r3 800317a: 095b lsrs r3, r3, #5 800317c: b29b uxth r3, r3 800317e: 4619 mov r1, r3 8003180: 4845 ldr r0, [pc, #276] @ (8003298 ) 8003182: f006 ff33 bl 8009fec printf("maxCC %dA\n",GBT_BATStat.maxChargingCurrent/10); // 0.1A/bit 8003186: 4b42 ldr r3, [pc, #264] @ (8003290 ) 8003188: 885b ldrh r3, [r3, #2] 800318a: b29b uxth r3, r3 800318c: 4a43 ldr r2, [pc, #268] @ (800329c ) 800318e: fba2 2303 umull r2, r3, r2, r3 8003192: 08db lsrs r3, r3, #3 8003194: b29b uxth r3, r3 8003196: 4619 mov r1, r3 8003198: 4841 ldr r0, [pc, #260] @ (80032a0 ) 800319a: f006 ff27 bl 8009fec printf("totE %dkWh\n",GBT_BATStat.totalEnergy/10); // 0.1kWh 800319e: 4b3c ldr r3, [pc, #240] @ (8003290 ) 80031a0: 889b ldrh r3, [r3, #4] 80031a2: b29b uxth r3, r3 80031a4: 4a3d ldr r2, [pc, #244] @ (800329c ) 80031a6: fba2 2303 umull r2, r3, r2, r3 80031aa: 08db lsrs r3, r3, #3 80031ac: b29b uxth r3, r3 80031ae: 4619 mov r1, r3 80031b0: 483c ldr r0, [pc, #240] @ (80032a4 ) 80031b2: f006 ff1b bl 8009fec printf("maxCV %dV\n",GBT_BATStat.maxChargingVoltage/10); // 0.1V/ bit 80031b6: 4b36 ldr r3, [pc, #216] @ (8003290 ) 80031b8: 88db ldrh r3, [r3, #6] 80031ba: b29b uxth r3, r3 80031bc: 4a37 ldr r2, [pc, #220] @ (800329c ) 80031be: fba2 2303 umull r2, r3, r2, r3 80031c2: 08db lsrs r3, r3, #3 80031c4: b29b uxth r3, r3 80031c6: 4619 mov r1, r3 80031c8: 4833 ldr r0, [pc, #204] @ (8003298 ) 80031ca: f006 ff0f bl 8009fec printf("maxT %dC\n",(int16_t)GBT_BATStat.maxTemp-50); // 1C/bit, -50C offset 80031ce: 4b30 ldr r3, [pc, #192] @ (8003290 ) 80031d0: 7a1b ldrb r3, [r3, #8] 80031d2: 3b32 subs r3, #50 @ 0x32 80031d4: 4619 mov r1, r3 80031d6: 4834 ldr r0, [pc, #208] @ (80032a8 ) 80031d8: f006 ff08 bl 8009fec printf("SOC %dp\n",GBT_BATStat.SOC/10); // 0.1%/bit , 0..100% 80031dc: 4b2c ldr r3, [pc, #176] @ (8003290 ) 80031de: f8b3 3009 ldrh.w r3, [r3, #9] 80031e2: b29b uxth r3, r3 80031e4: 4a2d ldr r2, [pc, #180] @ (800329c ) 80031e6: fba2 2303 umull r2, r3, r2, r3 80031ea: 08db lsrs r3, r3, #3 80031ec: b29b uxth r3, r3 80031ee: 4619 mov r1, r3 80031f0: 482e ldr r0, [pc, #184] @ (80032ac ) 80031f2: f006 fefb bl 8009fec printf("Volt. %dV\n",GBT_BATStat.measVoltage/10); // 0.1V/bit 80031f6: 4b26 ldr r3, [pc, #152] @ (8003290 ) 80031f8: f8b3 300b ldrh.w r3, [r3, #11] 80031fc: b29b uxth r3, r3 80031fe: 4a27 ldr r2, [pc, #156] @ (800329c ) 8003200: fba2 2303 umull r2, r3, r2, r3 8003204: 08db lsrs r3, r3, #3 8003206: b29b uxth r3, r3 8003208: 4619 mov r1, r3 800320a: 4829 ldr r0, [pc, #164] @ (80032b0 ) 800320c: f006 feee bl 8009fec 8003210: e179 b.n 8003506 8003212: bf00 nop 8003214: 0800da50 .word 0x0800da50 8003218: 0800da58 .word 0x0800da58 800321c: 0800da68 .word 0x0800da68 8003220: 0800da74 .word 0x0800da74 8003224: 0800da80 .word 0x0800da80 8003228: 0800da88 .word 0x0800da88 800322c: 0800da8c .word 0x0800da8c 8003230: 0800da98 .word 0x0800da98 8003234: 0800daa4 .word 0x0800daa4 8003238: 0800dab4 .word 0x0800dab4 800323c: 0800dac0 .word 0x0800dac0 8003240: 0800dac8 .word 0x0800dac8 8003244: 0800dad4 .word 0x0800dad4 8003248: 0800dae0 .word 0x0800dae0 800324c: 0800daec .word 0x0800daec 8003250: 0800daf4 .word 0x0800daf4 8003254: 0800dafc .word 0x0800dafc 8003258: 0800db04 .word 0x0800db04 800325c: 0400f0f0 .word 0x0400f0f0 8003260: 0800db0c .word 0x0800db0c 8003264: 0800db14 .word 0x0800db14 8003268: 0800db20 .word 0x0800db20 800326c: 0800db30 .word 0x0800db30 8003270: 0800db3c .word 0x0800db3c 8003274: 0800db48 .word 0x0800db48 8003278: 0800db54 .word 0x0800db54 800327c: 0800db60 .word 0x0800db60 8003280: 0800db68 .word 0x0800db68 8003284: 0800db74 .word 0x0800db74 8003288: 0800db80 .word 0x0800db80 800328c: 0800db88 .word 0x0800db88 8003290: 2000034c .word 0x2000034c 8003294: 51eb851f .word 0x51eb851f 8003298: 0800db98 .word 0x0800db98 800329c: cccccccd .word 0xcccccccd 80032a0: 0800dba4 .word 0x0800dba4 80032a4: 0800dbb0 .word 0x0800dbb0 80032a8: 0800dbbc .word 0x0800dbbc 80032ac: 0800dbc8 .word 0x0800dbc8 80032b0: 0800dbd4 .word 0x0800dbd4 } else if (strncmp((const char*)buffer, "info2", length) == 0) { 80032b4: 683a ldr r2, [r7, #0] 80032b6: 4995 ldr r1, [pc, #596] @ (800350c ) 80032b8: 6878 ldr r0, [r7, #4] 80032ba: f006 ff0f bl 800a0dc 80032be: 4603 mov r3, r0 80032c0: 2b00 cmp r3, #0 80032c2: d153 bne.n 800336c printf("EV info:\n"); 80032c4: 4892 ldr r0, [pc, #584] @ (8003510 ) 80032c6: f006 fef9 bl 800a0bc printf("GBT_ver V%d.%d%d\n",GBT_EVInfo.version[0],GBT_EVInfo.version[1],GBT_EVInfo.version[2]); 80032ca: 4b92 ldr r3, [pc, #584] @ (8003514 ) 80032cc: 781b ldrb r3, [r3, #0] 80032ce: 4619 mov r1, r3 80032d0: 4b90 ldr r3, [pc, #576] @ (8003514 ) 80032d2: 785b ldrb r3, [r3, #1] 80032d4: 461a mov r2, r3 80032d6: 4b8f ldr r3, [pc, #572] @ (8003514 ) 80032d8: 789b ldrb r3, [r3, #2] 80032da: 488f ldr r0, [pc, #572] @ (8003518 ) 80032dc: f006 fe86 bl 8009fec printf("Battery type: %d\n",GBT_EVInfo.batteryType); 80032e0: 4b8c ldr r3, [pc, #560] @ (8003514 ) 80032e2: 78db ldrb r3, [r3, #3] 80032e4: 4619 mov r1, r3 80032e6: 488d ldr r0, [pc, #564] @ (800351c ) 80032e8: f006 fe80 bl 8009fec printf("Battery capacity: %d\n", GBT_EVInfo.batteryCapacity); // 0.1Ah/bit 80032ec: 4b89 ldr r3, [pc, #548] @ (8003514 ) 80032ee: 889b ldrh r3, [r3, #4] 80032f0: b29b uxth r3, r3 80032f2: 4619 mov r1, r3 80032f4: 488a ldr r0, [pc, #552] @ (8003520 ) 80032f6: f006 fe79 bl 8009fec printf("Battery voltage: %d\n", GBT_EVInfo.batteryVoltage); // 0.1V/bit 80032fa: 4b86 ldr r3, [pc, #536] @ (8003514 ) 80032fc: 88db ldrh r3, [r3, #6] 80032fe: b29b uxth r3, r3 8003300: 4619 mov r1, r3 8003302: 4888 ldr r0, [pc, #544] @ (8003524 ) 8003304: f006 fe72 bl 8009fec printf("Battery vendor: %.4s\n", GBT_EVInfo.batteryVendor); // Battery vendor (ASCII string) 8003308: 4987 ldr r1, [pc, #540] @ (8003528 ) 800330a: 4888 ldr r0, [pc, #544] @ (800352c ) 800330c: f006 fe6e bl 8009fec printf("Battery SN: %lu\n", GBT_EVInfo.batterySN); // int 8003310: 4b80 ldr r3, [pc, #512] @ (8003514 ) 8003312: 68db ldr r3, [r3, #12] 8003314: 4619 mov r1, r3 8003316: 4886 ldr r0, [pc, #536] @ (8003530 ) 8003318: f006 fe68 bl 8009fec printf("Battery manufacture date: %02d.%02d.%04d\n", GBT_EVInfo.batteryManuD, GBT_EVInfo.batteryManuM ,GBT_EVInfo.batteryManuY+1985); // year (offset 1985) 800331c: 4b7d ldr r3, [pc, #500] @ (8003514 ) 800331e: 7c9b ldrb r3, [r3, #18] 8003320: 4619 mov r1, r3 8003322: 4b7c ldr r3, [pc, #496] @ (8003514 ) 8003324: 7c5b ldrb r3, [r3, #17] 8003326: 461a mov r2, r3 8003328: 4b7a ldr r3, [pc, #488] @ (8003514 ) 800332a: 7c1b ldrb r3, [r3, #16] 800332c: f203 73c1 addw r3, r3, #1985 @ 0x7c1 8003330: 4880 ldr r0, [pc, #512] @ (8003534 ) 8003332: f006 fe5b bl 8009fec printf("Battery cycles: %d\n", GBT_EVInfo.batteryCycleCount); //uint24_t 8003336: 4b77 ldr r3, [pc, #476] @ (8003514 ) 8003338: 7cda ldrb r2, [r3, #19] 800333a: 7d19 ldrb r1, [r3, #20] 800333c: 0209 lsls r1, r1, #8 800333e: 430a orrs r2, r1 8003340: 7d5b ldrb r3, [r3, #21] 8003342: 041b lsls r3, r3, #16 8003344: 4313 orrs r3, r2 8003346: 4619 mov r1, r3 8003348: 487b ldr r0, [pc, #492] @ (8003538 ) 800334a: f006 fe4f bl 8009fec printf("Own auto: %d\n", GBT_EVInfo.ownAuto); // 0 = lizing, 1 = own auto 800334e: 4b71 ldr r3, [pc, #452] @ (8003514 ) 8003350: 7d9b ldrb r3, [r3, #22] 8003352: 4619 mov r1, r3 8003354: 4879 ldr r0, [pc, #484] @ (800353c ) 8003356: f006 fe49 bl 8009fec printf("EVIN: %.17s\n", GBT_EVInfo.EVIN); //EVIN 800335a: 4979 ldr r1, [pc, #484] @ (8003540 ) 800335c: 4879 ldr r0, [pc, #484] @ (8003544 ) 800335e: f006 fe45 bl 8009fec printf("EV_SW_VER: %.8s\n", GBT_EVInfo.EV_SW_VER); 8003362: 4979 ldr r1, [pc, #484] @ (8003548 ) 8003364: 4879 ldr r0, [pc, #484] @ (800354c ) 8003366: f006 fe41 bl 8009fec 800336a: e0cc b.n 8003506 } else if (strncmp((const char*)buffer, "info3", length) == 0) { 800336c: 683a ldr r2, [r7, #0] 800336e: 4978 ldr r1, [pc, #480] @ (8003550 ) 8003370: 6878 ldr r0, [r7, #4] 8003372: f006 feb3 bl 800a0dc 8003376: 4603 mov r3, r0 8003378: 2b00 cmp r3, #0 800337a: d133 bne.n 80033e4 printf("GBT_MaxLoad info:\n"); 800337c: 4875 ldr r0, [pc, #468] @ (8003554 ) 800337e: f006 fe9d bl 800a0bc printf("Output max current: %d\n",GBT_MaxLoad.maxOutputCurrent); 8003382: 4b75 ldr r3, [pc, #468] @ (8003558 ) 8003384: 889b ldrh r3, [r3, #4] 8003386: b29b uxth r3, r3 8003388: 4619 mov r1, r3 800338a: 4874 ldr r0, [pc, #464] @ (800355c ) 800338c: f006 fe2e bl 8009fec printf("Output min current: %d\n",GBT_MaxLoad.minOutputCurrent); 8003390: 4b71 ldr r3, [pc, #452] @ (8003558 ) 8003392: 88db ldrh r3, [r3, #6] 8003394: b29b uxth r3, r3 8003396: 4619 mov r1, r3 8003398: 4871 ldr r0, [pc, #452] @ (8003560 ) 800339a: f006 fe27 bl 8009fec printf("Output max voltage: %d\n",GBT_MaxLoad.maxOutputVoltage); 800339e: 4b6e ldr r3, [pc, #440] @ (8003558 ) 80033a0: 881b ldrh r3, [r3, #0] 80033a2: b29b uxth r3, r3 80033a4: 4619 mov r1, r3 80033a6: 486f ldr r0, [pc, #444] @ (8003564 ) 80033a8: f006 fe20 bl 8009fec printf("Output min voltage: %d\n",GBT_MaxLoad.minOutputVoltage); 80033ac: 4b6a ldr r3, [pc, #424] @ (8003558 ) 80033ae: 885b ldrh r3, [r3, #2] 80033b0: b29b uxth r3, r3 80033b2: 4619 mov r1, r3 80033b4: 486c ldr r0, [pc, #432] @ (8003568 ) 80033b6: f006 fe19 bl 8009fec printf("\nGBT_ChargerInfo info:\n"); 80033ba: 486c ldr r0, [pc, #432] @ (800356c ) 80033bc: f006 fe7e bl 800a0bc printf("BMS Recognized: %d\n",GBT_ChargerInfo.bmsIdentified); 80033c0: 4b6b ldr r3, [pc, #428] @ (8003570 ) 80033c2: 781b ldrb r3, [r3, #0] 80033c4: 4619 mov r1, r3 80033c6: 486b ldr r0, [pc, #428] @ (8003574 ) 80033c8: f006 fe10 bl 8009fec printf("Charger location: %.3s\n",GBT_ChargerInfo.chargerLocation); 80033cc: 496a ldr r1, [pc, #424] @ (8003578 ) 80033ce: 486b ldr r0, [pc, #428] @ (800357c ) 80033d0: f006 fe0c bl 8009fec printf("Charger number: %lu\n",GBT_ChargerInfo.chargerNumber); 80033d4: 4b66 ldr r3, [pc, #408] @ (8003570 ) 80033d6: f8d3 3001 ldr.w r3, [r3, #1] 80033da: 4619 mov r1, r3 80033dc: 4868 ldr r0, [pc, #416] @ (8003580 ) 80033de: f006 fe05 bl 8009fec 80033e2: e090 b.n 8003506 } else if (strncmp((const char*)buffer, "help", length) == 0) { 80033e4: 683a ldr r2, [r7, #0] 80033e6: 4967 ldr r1, [pc, #412] @ (8003584 ) 80033e8: 6878 ldr r0, [r7, #4] 80033ea: f006 fe77 bl 800a0dc 80033ee: 4603 mov r3, r0 80033f0: 2b00 cmp r3, #0 80033f2: d136 bne.n 8003462 printf("Command list:\n"); 80033f4: 4864 ldr r0, [pc, #400] @ (8003588 ) 80033f6: f006 fe61 bl 800a0bc printf("reset\n"); 80033fa: 4864 ldr r0, [pc, #400] @ (800358c ) 80033fc: f006 fe5e bl 800a0bc printf("help\n"); 8003400: 4860 ldr r0, [pc, #384] @ (8003584 ) 8003402: f006 fe5b bl 800a0bc printf("cc_state\n"); 8003406: 4862 ldr r0, [pc, #392] @ (8003590 ) 8003408: f006 fe58 bl 800a0bc printf("lock_lock\n"); 800340c: 4861 ldr r0, [pc, #388] @ (8003594 ) 800340e: f006 fe55 bl 800a0bc printf("lock_unlock\n"); 8003412: 4861 ldr r0, [pc, #388] @ (8003598 ) 8003414: f006 fe52 bl 800a0bc printf("lock_state\n"); 8003418: 4860 ldr r0, [pc, #384] @ (800359c ) 800341a: f006 fe4f bl 800a0bc printf("adc\n"); 800341e: 4860 ldr r0, [pc, #384] @ (80035a0 ) 8003420: f006 fe4c bl 800a0bc printf("relay(cc,aux)\n"); 8003424: 485f ldr r0, [pc, #380] @ (80035a4 ) 8003426: f006 fe49 bl 800a0bc printf("start\n"); 800342a: 485f ldr r0, [pc, #380] @ (80035a8 ) 800342c: f006 fe46 bl 800a0bc printf("stop\n"); 8003430: 485e ldr r0, [pc, #376] @ (80035ac ) 8003432: f006 fe43 bl 800a0bc printf("stop1\n"); 8003436: 485e ldr r0, [pc, #376] @ (80035b0 ) 8003438: f006 fe40 bl 800a0bc // printf("force\n"); printf("temp\n"); 800343c: 485d ldr r0, [pc, #372] @ (80035b4 ) 800343e: f006 fe3d bl 800a0bc printf("info1\n"); 8003442: 485d ldr r0, [pc, #372] @ (80035b8 ) 8003444: f006 fe3a bl 800a0bc printf("info2\n"); 8003448: 4830 ldr r0, [pc, #192] @ (800350c ) 800344a: f006 fe37 bl 800a0bc printf("info3\n"); 800344e: 4840 ldr r0, [pc, #256] @ (8003550 ) 8003450: f006 fe34 bl 800a0bc printf("time\n"); 8003454: 4859 ldr r0, [pc, #356] @ (80035bc ) 8003456: f006 fe31 bl 800a0bc printf("cantest\n"); 800345a: 4859 ldr r0, [pc, #356] @ (80035c0 ) 800345c: f006 fe2e bl 800a0bc 8003460: e051 b.n 8003506 //TODO: info commands } else if (strncmp((const char*)buffer, "time", length) == 0) { 8003462: 683a ldr r2, [r7, #0] 8003464: 4955 ldr r1, [pc, #340] @ (80035bc ) 8003466: 6878 ldr r0, [r7, #4] 8003468: f006 fe38 bl 800a0dc 800346c: 4603 mov r3, r0 800346e: 2b00 cmp r3, #0 8003470: d135 bne.n 80034de time_t unix_time = (time_t)get_Current_Time(); 8003472: f001 fe2f bl 80050d4 8003476: 4603 mov r3, r0 8003478: 17da asrs r2, r3, #31 800347a: 461c mov r4, r3 800347c: 4615 mov r5, r2 800347e: e9c7 4502 strd r4, r5, [r7, #8] struct tm *parts = localtime(&unix_time); 8003482: f107 0308 add.w r3, r7, #8 8003486: 4618 mov r0, r3 8003488: f006 ff00 bl 800a28c 800348c: 6138 str r0, [r7, #16] printf("Year: %d\n", parts->tm_year + 1900); 800348e: 693b ldr r3, [r7, #16] 8003490: 695b ldr r3, [r3, #20] 8003492: f203 736c addw r3, r3, #1900 @ 0x76c 8003496: 4619 mov r1, r3 8003498: 484a ldr r0, [pc, #296] @ (80035c4 ) 800349a: f006 fda7 bl 8009fec printf("Month: %d\n", parts->tm_mon + 1); 800349e: 693b ldr r3, [r7, #16] 80034a0: 691b ldr r3, [r3, #16] 80034a2: 3301 adds r3, #1 80034a4: 4619 mov r1, r3 80034a6: 4848 ldr r0, [pc, #288] @ (80035c8 ) 80034a8: f006 fda0 bl 8009fec printf("Day: %d\n", parts->tm_mday); 80034ac: 693b ldr r3, [r7, #16] 80034ae: 68db ldr r3, [r3, #12] 80034b0: 4619 mov r1, r3 80034b2: 4846 ldr r0, [pc, #280] @ (80035cc ) 80034b4: f006 fd9a bl 8009fec printf("Hour: %d\n", parts->tm_hour); 80034b8: 693b ldr r3, [r7, #16] 80034ba: 689b ldr r3, [r3, #8] 80034bc: 4619 mov r1, r3 80034be: 4844 ldr r0, [pc, #272] @ (80035d0 ) 80034c0: f006 fd94 bl 8009fec printf("Minute: %d\n", parts->tm_min); 80034c4: 693b ldr r3, [r7, #16] 80034c6: 685b ldr r3, [r3, #4] 80034c8: 4619 mov r1, r3 80034ca: 4842 ldr r0, [pc, #264] @ (80035d4 ) 80034cc: f006 fd8e bl 8009fec printf("Second: %d\n", parts->tm_sec); 80034d0: 693b ldr r3, [r7, #16] 80034d2: 681b ldr r3, [r3, #0] 80034d4: 4619 mov r1, r3 80034d6: 4840 ldr r0, [pc, #256] @ (80035d8 ) 80034d8: f006 fd88 bl 8009fec 80034dc: e013 b.n 8003506 } else if (strncmp((const char*)buffer, "cantest", length) == 0) { 80034de: 683a ldr r2, [r7, #0] 80034e0: 4937 ldr r1, [pc, #220] @ (80035c0 ) 80034e2: 6878 ldr r0, [r7, #4] 80034e4: f006 fdfa bl 800a0dc 80034e8: 4603 mov r3, r0 80034ea: 2b00 cmp r3, #0 80034ec: d106 bne.n 80034fc //GBT_SendCHM(); GBT_Error(0xFDF0C0FC); //BRM Timeout 80034ee: 483b ldr r0, [pc, #236] @ (80035dc ) 80034f0: f7ff f9a0 bl 8002834 printf("can test\n"); 80034f4: 483a ldr r0, [pc, #232] @ (80035e0 ) 80034f6: f006 fde1 bl 800a0bc 80034fa: e004 b.n 8003506 } else { printf("Unknown command\n"); 80034fc: 4839 ldr r0, [pc, #228] @ (80035e4 ) 80034fe: f006 fddd bl 800a0bc 8003502: e000 b.n 8003506 if (buffer[0] == 0) return; 8003504: bf00 nop } } 8003506: 3718 adds r7, #24 8003508: 46bd mov sp, r7 800350a: bdb0 pop {r4, r5, r7, pc} 800350c: 0800dbe0 .word 0x0800dbe0 8003510: 0800dbe8 .word 0x0800dbe8 8003514: 20000318 .word 0x20000318 8003518: 0800dbf4 .word 0x0800dbf4 800351c: 0800dc08 .word 0x0800dc08 8003520: 0800dc1c .word 0x0800dc1c 8003524: 0800dc34 .word 0x0800dc34 8003528: 20000320 .word 0x20000320 800352c: 0800dc4c .word 0x0800dc4c 8003530: 0800dc64 .word 0x0800dc64 8003534: 0800dc78 .word 0x0800dc78 8003538: 0800dca4 .word 0x0800dca4 800353c: 0800dcb8 .word 0x0800dcb8 8003540: 20000330 .word 0x20000330 8003544: 0800dcc8 .word 0x0800dcc8 8003548: 20000341 .word 0x20000341 800354c: 0800dcd8 .word 0x0800dcd8 8003550: 0800dcec .word 0x0800dcec 8003554: 0800dcf4 .word 0x0800dcf4 8003558: 20000304 .word 0x20000304 800355c: 0800dd08 .word 0x0800dd08 8003560: 0800dd20 .word 0x0800dd20 8003564: 0800dd38 .word 0x0800dd38 8003568: 0800dd50 .word 0x0800dd50 800356c: 0800dd68 .word 0x0800dd68 8003570: 2000030c .word 0x2000030c 8003574: 0800dd80 .word 0x0800dd80 8003578: 20000311 .word 0x20000311 800357c: 0800dd94 .word 0x0800dd94 8003580: 0800ddac .word 0x0800ddac 8003584: 0800ddc4 .word 0x0800ddc4 8003588: 0800ddcc .word 0x0800ddcc 800358c: 0800da50 .word 0x0800da50 8003590: 0800db14 .word 0x0800db14 8003594: 0800dab4 .word 0x0800dab4 8003598: 0800dac8 .word 0x0800dac8 800359c: 0800da98 .word 0x0800da98 80035a0: 0800da88 .word 0x0800da88 80035a4: 0800dddc .word 0x0800dddc 80035a8: 0800daec .word 0x0800daec 80035ac: 0800dafc .word 0x0800dafc 80035b0: 0800db0c .word 0x0800db0c 80035b4: 0800db60 .word 0x0800db60 80035b8: 0800db80 .word 0x0800db80 80035bc: 0800ddec .word 0x0800ddec 80035c0: 0800ddf4 .word 0x0800ddf4 80035c4: 0800ddfc .word 0x0800ddfc 80035c8: 0800de08 .word 0x0800de08 80035cc: 0800de14 .word 0x0800de14 80035d0: 0800de20 .word 0x0800de20 80035d4: 0800de2c .word 0x0800de2c 80035d8: 0800de38 .word 0x0800de38 80035dc: fdf0c0fc .word 0xfdf0c0fc 80035e0: 0800de44 .word 0x0800de44 80035e4: 0800de50 .word 0x0800de50 080035e8 : void debug_task(){ 80035e8: b580 push {r7, lr} 80035ea: af00 add r7, sp, #0 if(debug_cmd_received){ 80035ec: 4b09 ldr r3, [pc, #36] @ (8003614 ) 80035ee: 781b ldrb r3, [r3, #0] 80035f0: 2b00 cmp r3, #0 80035f2: d00d beq.n 8003610 parse_command(debug_rx_buffer, debug_rx_buffer_size); 80035f4: 4b08 ldr r3, [pc, #32] @ (8003618 ) 80035f6: 781b ldrb r3, [r3, #0] 80035f8: 4619 mov r1, r3 80035fa: 4808 ldr r0, [pc, #32] @ (800361c ) 80035fc: f7ff fc84 bl 8002f08 HAL_UARTEx_ReceiveToIdle_IT(&huart2,debug_rx_buffer,255); 8003600: 22ff movs r2, #255 @ 0xff 8003602: 4906 ldr r1, [pc, #24] @ (800361c ) 8003604: 4806 ldr r0, [pc, #24] @ (8003620 ) 8003606: f005 faed bl 8008be4 debug_cmd_received = 0; 800360a: 4b02 ldr r3, [pc, #8] @ (8003614 ) 800360c: 2200 movs r2, #0 800360e: 701a strb r2, [r3, #0] } } 8003610: bf00 nop 8003612: bd80 pop {r7, pc} 8003614: 200004b0 .word 0x200004b0 8003618: 200004b1 .word 0x200004b1 800361c: 200003b0 .word 0x200003b0 8003620: 20003364 .word 0x20003364 08003624 : * DestinationID: Packet Destination ID * Addr: First register address in sequence * *data: pointer for data array * len: length of data (1..255) */ void EDCAN_ReadHandler(uint8_t SourceID, uint8_t DestinationID, uint16_t Addr, uint8_t *data, uint8_t len){ 8003624: b480 push {r7} 8003626: b085 sub sp, #20 8003628: af00 add r7, sp, #0 800362a: 603b str r3, [r7, #0] 800362c: 4603 mov r3, r0 800362e: 71fb strb r3, [r7, #7] 8003630: 460b mov r3, r1 8003632: 71bb strb r3, [r7, #6] 8003634: 4613 mov r3, r2 8003636: 80bb strh r3, [r7, #4] // printf("Destination ID = %d\n", DestinationID); // printf("Address = %d\n", Addr); // printf("Len = %d\n", len); // printf("\n"); for (uint16_t AddrOffset = 0; AddrOffset < len; AddrOffset++){ //по очереди перебираем все полученные регистры через Handler 8003638: 2300 movs r3, #0 800363a: 81fb strh r3, [r7, #14] 800363c: e002 b.n 8003644 800363e: 89fb ldrh r3, [r7, #14] 8003640: 3301 adds r3, #1 8003642: 81fb strh r3, [r7, #14] 8003644: 7e3b ldrb r3, [r7, #24] 8003646: b29b uxth r3, r3 8003648: 89fa ldrh r2, [r7, #14] 800364a: 429a cmp r2, r3 800364c: d3f7 bcc.n 800363e // } // } } // printf("\n"); } 800364e: bf00 nop 8003650: bf00 nop 8003652: 3714 adds r7, #20 8003654: 46bd mov sp, r7 8003656: bc80 pop {r7} 8003658: 4770 bx lr ... 0800365c : * DestinationID: Packet Destination ID * Addr: First register address in sequence * *data: pointer for data array * len: length of data (1..255) */ void EDCAN_WriteUserRegister(uint16_t addr, uint8_t value){ 800365c: b580 push {r7, lr} 800365e: b082 sub sp, #8 8003660: af00 add r7, sp, #0 8003662: 4603 mov r3, r0 8003664: 460a mov r2, r1 8003666: 80fb strh r3, [r7, #6] 8003668: 4613 mov r3, r2 800366a: 717b strb r3, [r7, #5] switch(addr){ 800366c: 88fb ldrh r3, [r7, #6] 800366e: f5b3 7f0a cmp.w r3, #552 @ 0x228 8003672: dc5d bgt.n 8003730 8003674: f5b3 7f00 cmp.w r3, #512 @ 0x200 8003678: f2c0 8088 blt.w 800378c 800367c: f5a3 7300 sub.w r3, r3, #512 @ 0x200 8003680: 2b28 cmp r3, #40 @ 0x28 8003682: f200 8083 bhi.w 800378c 8003686: a201 add r2, pc, #4 @ (adr r2, 800368c ) 8003688: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800368c: 0800376b .word 0x0800376b 8003690: 0800376b .word 0x0800376b 8003694: 0800376b .word 0x0800376b 8003698: 0800376b .word 0x0800376b 800369c: 0800376b .word 0x0800376b 80036a0: 0800376b .word 0x0800376b 80036a4: 0800376b .word 0x0800376b 80036a8: 0800376b .word 0x0800376b 80036ac: 0800376b .word 0x0800376b 80036b0: 0800378d .word 0x0800378d 80036b4: 0800378d .word 0x0800378d 80036b8: 0800378d .word 0x0800378d 80036bc: 0800378d .word 0x0800378d 80036c0: 0800378d .word 0x0800378d 80036c4: 0800378d .word 0x0800378d 80036c8: 0800378d .word 0x0800378d 80036cc: 0800373b .word 0x0800373b 80036d0: 08003747 .word 0x08003747 80036d4: 08003753 .word 0x08003753 80036d8: 0800375f .word 0x0800375f 80036dc: 0800378d .word 0x0800378d 80036e0: 0800378d .word 0x0800378d 80036e4: 0800378d .word 0x0800378d 80036e8: 0800378d .word 0x0800378d 80036ec: 0800378d .word 0x0800378d 80036f0: 0800378d .word 0x0800378d 80036f4: 0800378d .word 0x0800378d 80036f8: 0800378d .word 0x0800378d 80036fc: 0800378d .word 0x0800378d 8003700: 0800378d .word 0x0800378d 8003704: 0800378d .word 0x0800378d 8003708: 0800378d .word 0x0800378d 800370c: 0800378b .word 0x0800378b 8003710: 0800378b .word 0x0800378b 8003714: 0800378b .word 0x0800378b 8003718: 0800378b .word 0x0800378b 800371c: 0800378b .word 0x0800378b 8003720: 0800378b .word 0x0800378b 8003724: 0800378b .word 0x0800378b 8003728: 0800378b .word 0x0800378b 800372c: 0800378b .word 0x0800378b 8003730: f5a3 63b0 sub.w r3, r3, #1408 @ 0x580 8003734: 2b07 cmp r3, #7 8003736: d829 bhi.n 800378c 8003738: e01f b.n 800377a // if(value)GBT_Charger_Enable = 1; // else GBT_Charger_Enable = 0; // break; case EDCAN_REG_TIME_0: writeTimeReg(0, value); 800373a: 797b ldrb r3, [r7, #5] 800373c: 4619 mov r1, r3 800373e: 2000 movs r0, #0 8003740: f001 fd72 bl 8005228 break; 8003744: e022 b.n 800378c case EDCAN_REG_TIME_1: writeTimeReg(1, value); 8003746: 797b ldrb r3, [r7, #5] 8003748: 4619 mov r1, r3 800374a: 2001 movs r0, #1 800374c: f001 fd6c bl 8005228 break; 8003750: e01c b.n 800378c case EDCAN_REG_TIME_2: writeTimeReg(2, value); 8003752: 797b ldrb r3, [r7, #5] 8003754: 4619 mov r1, r3 8003756: 2002 movs r0, #2 8003758: f001 fd66 bl 8005228 break; 800375c: e016 b.n 800378c case EDCAN_REG_TIME_3: writeTimeReg(3, value); 800375e: 797b ldrb r3, [r7, #5] 8003760: 4619 mov r1, r3 8003762: 2003 movs r0, #3 8003764: f001 fd60 bl 8005228 break; 8003768: e010 b.n 800378c // ((uint8_t*)&GBT_MaxLoad)[addr - EDCAN_REG_MAX_LOAD] = value; break; //0x200 case EDCAN_REG_CHARGER_INFO ... (EDCAN_REG_CHARGER_INFO+sizeof(GBT_CRM_t)): ((uint8_t*)&GBT_ChargerInfo)[addr - EDCAN_REG_CHARGER_INFO] = value; 800376a: 88fb ldrh r3, [r7, #6] 800376c: f5a3 7300 sub.w r3, r3, #512 @ 0x200 8003770: 4a08 ldr r2, [pc, #32] @ (8003794 ) 8003772: 4413 add r3, r2 8003774: 797a ldrb r2, [r7, #5] 8003776: 701a strb r2, [r3, #0] break; 8003778: e008 b.n 800378c //0x580 case EDCAN_REG_INPUT ... (EDCAN_REG_INPUT+sizeof(GBT_EDCAN_Input_t)): ((uint8_t*)&GBT_EDCAN_Input)[addr - EDCAN_REG_INPUT] = value; 800377a: 88fb ldrh r3, [r7, #6] 800377c: f5a3 63b0 sub.w r3, r3, #1408 @ 0x580 8003780: 4a05 ldr r2, [pc, #20] @ (8003798 ) 8003782: 4413 add r3, r2 8003784: 797a ldrb r2, [r7, #5] 8003786: 701a strb r2, [r3, #0] //TODO //GBT_EDCAN_Input.measuredCurrent; break; 8003788: e000 b.n 800378c break; 800378a: bf00 nop default: //printf ("Unknown register\n"); } } 800378c: bf00 nop 800378e: 3708 adds r7, #8 8003790: 46bd mov sp, r7 8003792: bd80 pop {r7, pc} 8003794: 2000030c .word 0x2000030c 8003798: 200004c4 .word 0x200004c4 0800379c : uint8_t EDCAN_GetUserRegisterValue(uint16_t addr){ 800379c: b580 push {r7, lr} 800379e: b082 sub sp, #8 80037a0: af00 add r7, sp, #0 80037a2: 4603 mov r3, r0 80037a4: 80fb strh r3, [r7, #6] switch (addr){ 80037a6: 88fb ldrh r3, [r7, #6] 80037a8: f5b3 6fb1 cmp.w r3, #1416 @ 0x588 80037ac: f280 8122 bge.w 80039f4 80037b0: f5b3 6fb0 cmp.w r3, #1408 @ 0x580 80037b4: f280 8117 bge.w 80039e6 80037b8: f240 520e movw r2, #1294 @ 0x50e 80037bc: 4293 cmp r3, r2 80037be: f300 8119 bgt.w 80039f4 80037c2: f5b3 6fa0 cmp.w r3, #1280 @ 0x500 80037c6: f280 8107 bge.w 80039d8 80037ca: f5b3 7f62 cmp.w r3, #904 @ 0x388 80037ce: f280 8111 bge.w 80039f4 80037d2: f5b3 7f54 cmp.w r3, #848 @ 0x350 80037d6: da07 bge.n 80037e8 80037d8: f5b3 7f0a cmp.w r3, #552 @ 0x228 80037dc: f300 80b6 bgt.w 800394c 80037e0: f5b3 7f04 cmp.w r3, #528 @ 0x210 80037e4: da78 bge.n 80038d8 80037e6: e105 b.n 80039f4 80037e8: f5a3 7354 sub.w r3, r3, #848 @ 0x350 80037ec: 2b37 cmp r3, #55 @ 0x37 80037ee: f200 8101 bhi.w 80039f4 80037f2: a201 add r2, pc, #4 @ (adr r2, 80037f8 ) 80037f4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80037f8: 0800399b .word 0x0800399b 80037fc: 0800399b .word 0x0800399b 8003800: 0800399b .word 0x0800399b 8003804: 0800399b .word 0x0800399b 8003808: 0800399b .word 0x0800399b 800380c: 0800399b .word 0x0800399b 8003810: 0800399b .word 0x0800399b 8003814: 0800399b .word 0x0800399b 8003818: 0800399b .word 0x0800399b 800381c: 0800399b .word 0x0800399b 8003820: 0800399b .word 0x0800399b 8003824: 0800399b .word 0x0800399b 8003828: 0800399b .word 0x0800399b 800382c: 0800399b .word 0x0800399b 8003830: 080039f5 .word 0x080039f5 8003834: 080039a9 .word 0x080039a9 8003838: 080039af .word 0x080039af 800383c: 080039af .word 0x080039af 8003840: 080039af .word 0x080039af 8003844: 080039af .word 0x080039af 8003848: 080039af .word 0x080039af 800384c: 080039af .word 0x080039af 8003850: 080039f5 .word 0x080039f5 8003854: 080039f5 .word 0x080039f5 8003858: 080039f5 .word 0x080039f5 800385c: 080039f5 .word 0x080039f5 8003860: 080039f5 .word 0x080039f5 8003864: 080039f5 .word 0x080039f5 8003868: 080039f5 .word 0x080039f5 800386c: 080039f5 .word 0x080039f5 8003870: 080039f5 .word 0x080039f5 8003874: 080039f5 .word 0x080039f5 8003878: 080039bd .word 0x080039bd 800387c: 080039bd .word 0x080039bd 8003880: 080039bd .word 0x080039bd 8003884: 080039bd .word 0x080039bd 8003888: 080039bd .word 0x080039bd 800388c: 080039bd .word 0x080039bd 8003890: 080039bd .word 0x080039bd 8003894: 080039bd .word 0x080039bd 8003898: 080039bd .word 0x080039bd 800389c: 080039bd .word 0x080039bd 80038a0: 080039f5 .word 0x080039f5 80038a4: 080039f5 .word 0x080039f5 80038a8: 080039f5 .word 0x080039f5 80038ac: 080039f5 .word 0x080039f5 80038b0: 080039f5 .word 0x080039f5 80038b4: 080039f5 .word 0x080039f5 80038b8: 080039cb .word 0x080039cb 80038bc: 080039cb .word 0x080039cb 80038c0: 080039cb .word 0x080039cb 80038c4: 080039cb .word 0x080039cb 80038c8: 080039cb .word 0x080039cb 80038cc: 080039cb .word 0x080039cb 80038d0: 080039cb .word 0x080039cb 80038d4: 080039cb .word 0x080039cb 80038d8: f5a3 7304 sub.w r3, r3, #528 @ 0x210 80038dc: 2b18 cmp r3, #24 80038de: f200 8089 bhi.w 80039f4 80038e2: a201 add r2, pc, #4 @ (adr r2, 80038e8 ) 80038e4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80038e8: 08003957 .word 0x08003957 80038ec: 08003961 .word 0x08003961 80038f0: 0800396b .word 0x0800396b 80038f4: 08003975 .word 0x08003975 80038f8: 080039f5 .word 0x080039f5 80038fc: 080039f5 .word 0x080039f5 8003900: 080039f5 .word 0x080039f5 8003904: 080039f5 .word 0x080039f5 8003908: 080039f5 .word 0x080039f5 800390c: 080039f5 .word 0x080039f5 8003910: 080039f5 .word 0x080039f5 8003914: 080039f5 .word 0x080039f5 8003918: 080039f5 .word 0x080039f5 800391c: 080039f5 .word 0x080039f5 8003920: 080039f5 .word 0x080039f5 8003924: 080039f5 .word 0x080039f5 8003928: 0800397f .word 0x0800397f 800392c: 0800397f .word 0x0800397f 8003930: 0800397f .word 0x0800397f 8003934: 0800397f .word 0x0800397f 8003938: 0800397f .word 0x0800397f 800393c: 0800397f .word 0x0800397f 8003940: 0800397f .word 0x0800397f 8003944: 0800397f .word 0x0800397f 8003948: 0800397f .word 0x0800397f 800394c: f5a3 7344 sub.w r3, r3, #784 @ 0x310 8003950: 2b30 cmp r3, #48 @ 0x30 8003952: d84f bhi.n 80039f4 8003954: e01a b.n 800398c // /* регистры 256..2047 используются пользовательских нужд */ // 0x400 case EDCAN_REG_TIME_0: return getTimeReg(0); 8003956: 2000 movs r0, #0 8003958: f001 fc8e bl 8005278 800395c: 4603 mov r3, r0 800395e: e04a b.n 80039f6 break; case EDCAN_REG_TIME_1: return getTimeReg(1); 8003960: 2001 movs r0, #1 8003962: f001 fc89 bl 8005278 8003966: 4603 mov r3, r0 8003968: e045 b.n 80039f6 break; case EDCAN_REG_TIME_2: return getTimeReg(2); 800396a: 2002 movs r0, #2 800396c: f001 fc84 bl 8005278 8003970: 4603 mov r3, r0 8003972: e040 b.n 80039f6 break; case EDCAN_REG_TIME_3: return getTimeReg(3); 8003974: 2003 movs r0, #3 8003976: f001 fc7f bl 8005278 800397a: 4603 mov r3, r0 800397c: e03b b.n 80039f6 break; //0x220 case EDCAN_REG_MAX_LOAD ... (EDCAN_REG_MAX_LOAD+sizeof(GBT_CML_t)): return ((uint8_t*)&GBT_MaxLoad)[addr - EDCAN_REG_MAX_LOAD]; 800397e: 88fb ldrh r3, [r7, #6] 8003980: f5a3 7308 sub.w r3, r3, #544 @ 0x220 8003984: 4a1e ldr r2, [pc, #120] @ (8003a00 ) 8003986: 4413 add r3, r2 8003988: 781b ldrb r3, [r3, #0] 800398a: e034 b.n 80039f6 //0x310 case EDCAN_REG_BRM ... (EDCAN_REG_BRM+sizeof(GBT_BRM_t)-1): return ((uint8_t*)&GBT_EVInfo)[addr - EDCAN_REG_BRM]; 800398c: 88fb ldrh r3, [r7, #6] 800398e: f5a3 7344 sub.w r3, r3, #784 @ 0x310 8003992: 4a1c ldr r2, [pc, #112] @ (8003a04 ) 8003994: 4413 add r3, r2 8003996: 781b ldrb r3, [r3, #0] 8003998: e02d b.n 80039f6 //0x340 case EDCAN_REG_BCP ... (EDCAN_REG_BCP+sizeof(GBT_BCP_t)): return ((uint8_t*)&GBT_BATStat)[addr - EDCAN_REG_BCP]; 800399a: 88fb ldrh r3, [r7, #6] 800399c: f5a3 7354 sub.w r3, r3, #848 @ 0x350 80039a0: 4a19 ldr r2, [pc, #100] @ (8003a08 ) 80039a2: 4413 add r3, r2 80039a4: 781b ldrb r3, [r3, #0] 80039a6: e026 b.n 80039f6 //0x34F case EDCAN_REG_BRO: return GBT_BRO; 80039a8: 4b18 ldr r3, [pc, #96] @ (8003a0c ) 80039aa: 781b ldrb r3, [r3, #0] 80039ac: e023 b.n 80039f6 //0x350 case EDCAN_REG_BCL ... (EDCAN_REG_BCL+sizeof(GBT_BCL_t)): return ((uint8_t*)&GBT_ReqPower)[addr - EDCAN_REG_BCL]; 80039ae: 88fb ldrh r3, [r7, #6] 80039b0: f5a3 7358 sub.w r3, r3, #864 @ 0x360 80039b4: 4a16 ldr r2, [pc, #88] @ (8003a10 ) 80039b6: 4413 add r3, r2 80039b8: 781b ldrb r3, [r3, #0] 80039ba: e01c b.n 80039f6 //0x360 case EDCAN_REG_BCS ... (EDCAN_REG_BCS+sizeof(GBT_BCS_t)): return ((uint8_t*)&GBT_ChargingStatus)[addr - EDCAN_REG_BCS]; 80039bc: 88fb ldrh r3, [r7, #6] 80039be: f5a3 735c sub.w r3, r3, #880 @ 0x370 80039c2: 4a14 ldr r2, [pc, #80] @ (8003a14 ) 80039c4: 4413 add r3, r2 80039c6: 781b ldrb r3, [r3, #0] 80039c8: e015 b.n 80039f6 //0x370 case EDCAN_REG_BSM ... (EDCAN_REG_BSM+sizeof(GBT_BSM_t)): return ((uint8_t*)&GBT_BatteryStatus)[addr - EDCAN_REG_BSM]; 80039ca: 88fb ldrh r3, [r7, #6] 80039cc: f5a3 7360 sub.w r3, r3, #896 @ 0x380 80039d0: 4a11 ldr r2, [pc, #68] @ (8003a18 ) 80039d2: 4413 add r3, r2 80039d4: 781b ldrb r3, [r3, #0] 80039d6: e00e b.n 80039f6 //0x500 case EDCAN_REG_OUTPUT ... (EDCAN_REG_OUTPUT+sizeof(GBT_EDCAN_Output_t)): return ((uint8_t*)&GBT_EDCAN_Output)[addr - EDCAN_REG_OUTPUT]; 80039d8: 88fb ldrh r3, [r7, #6] 80039da: f5a3 63a0 sub.w r3, r3, #1280 @ 0x500 80039de: 4a0f ldr r2, [pc, #60] @ (8003a1c ) 80039e0: 4413 add r3, r2 80039e2: 781b ldrb r3, [r3, #0] 80039e4: e007 b.n 80039f6 //0x580 case EDCAN_REG_INPUT ... (EDCAN_REG_INPUT+sizeof(GBT_EDCAN_Input_t)): return ((uint8_t*)&GBT_EDCAN_Input)[addr - EDCAN_REG_INPUT]; 80039e6: 88fb ldrh r3, [r7, #6] 80039e8: f5a3 63b0 sub.w r3, r3, #1408 @ 0x580 80039ec: 4a0c ldr r2, [pc, #48] @ (8003a20 ) 80039ee: 4413 add r3, r2 80039f0: 781b ldrb r3, [r3, #0] 80039f2: e000 b.n 80039f6 default: return 0x00; 80039f4: 2300 movs r3, #0 } } 80039f6: 4618 mov r0, r3 80039f8: 3708 adds r7, #8 80039fa: 46bd mov sp, r7 80039fc: bd80 pop {r7, pc} 80039fe: bf00 nop 8003a00: 20000304 .word 0x20000304 8003a04: 20000318 .word 0x20000318 8003a08: 2000034c .word 0x2000034c 8003a0c: 20000390 .word 0x20000390 8003a10: 2000035c .word 0x2000035c 8003a14: 2000036c .word 0x2000036c 8003a18: 20000378 .word 0x20000378 8003a1c: 200004b4 .word 0x200004b4 8003a20: 200004c4 .word 0x200004c4 08003a24 : // GB/T Time Synchronization Packet #include "main.h" #include "soft_rtc.h" #include "charger_gbt.h" void GBT_SendCTS(){ 8003a24: b580 push {r7, lr} 8003a26: b082 sub sp, #8 8003a28: af00 add r7, sp, #0 uint8_t data[7]; unix_to_bcd(get_Current_Time(), data); 8003a2a: f001 fb53 bl 80050d4 8003a2e: 4602 mov r2, r0 8003a30: 463b mov r3, r7 8003a32: 4619 mov r1, r3 8003a34: 4610 mov r0, r2 8003a36: f001 fb8b bl 8005150 // data[3] = 0x05; //days // data[4] = 0x05; //month // data[5] = 0x24; //years // data[6] = 0x20; //centuries J_SendPacket(0x000700, 6, 7, data); 8003a3a: 463b mov r3, r7 8003a3c: 2207 movs r2, #7 8003a3e: 2106 movs r1, #6 8003a40: f44f 60e0 mov.w r0, #1792 @ 0x700 8003a44: f000 fb08 bl 8004058 } 8003a48: bf00 nop 8003a4a: 3708 adds r7, #8 8003a4c: 46bd mov sp, r7 8003a4e: bd80 pop {r7, pc} 08003a50 : //GB/T Max Load Packet void GBT_SendCML(){ 8003a50: b580 push {r7, lr} 8003a52: af00 add r7, sp, #0 // data[4] = 0xC4; //-150A maximum output current // data[5] = 0x09; // // data[6] = 0x8C; //-2A minimum output current // data[7] = 0x0F; // J_SendPacket(0x000800, 6, 8, (uint8_t*)&GBT_MaxLoad); 8003a54: 4b04 ldr r3, [pc, #16] @ (8003a68 ) 8003a56: 2208 movs r2, #8 8003a58: 2106 movs r1, #6 8003a5a: f44f 6000 mov.w r0, #2048 @ 0x800 8003a5e: f000 fafb bl 8004058 } 8003a62: bf00 nop 8003a64: bd80 pop {r7, pc} 8003a66: bf00 nop 8003a68: 20000304 .word 0x20000304 08003a6c : //GB/T Version packet void GBT_SendCHM(){ 8003a6c: b580 push {r7, lr} 8003a6e: b082 sub sp, #8 8003a70: af00 add r7, sp, #0 uint8_t data[3]; data[0] = 0x01; 8003a72: 2301 movs r3, #1 8003a74: 713b strb r3, [r7, #4] data[1] = 0x01; 8003a76: 2301 movs r3, #1 8003a78: 717b strb r3, [r7, #5] data[2] = 0x00; 8003a7a: 2300 movs r3, #0 8003a7c: 71bb strb r3, [r7, #6] J_SendPacket(0x2600, 6, 3, data); 8003a7e: 1d3b adds r3, r7, #4 8003a80: 2203 movs r2, #3 8003a82: 2106 movs r1, #6 8003a84: f44f 5018 mov.w r0, #9728 @ 0x2600 8003a88: f000 fae6 bl 8004058 } 8003a8c: bf00 nop 8003a8e: 3708 adds r7, #8 8003a90: 46bd mov sp, r7 8003a92: bd80 pop {r7, pc} 08003a94 : //GB/T CRM Packet (state=BMS identified) void GBT_SendCRM(uint8_t state){ 8003a94: b580 push {r7, lr} 8003a96: b082 sub sp, #8 8003a98: af00 add r7, sp, #0 8003a9a: 4603 mov r3, r0 8003a9c: 71fb strb r3, [r7, #7] // data[3] = 0x01; // data[4] = 0x00; // data[5] = 0x42; //TODO: location BFG // data[6] = 0x46; // data[7] = 0x47; GBT_ChargerInfo.bmsIdentified = state; 8003a9e: 4a07 ldr r2, [pc, #28] @ (8003abc ) 8003aa0: 79fb ldrb r3, [r7, #7] 8003aa2: 7013 strb r3, [r2, #0] J_SendPacket(0x100, 6, 8, (uint8_t *)&GBT_ChargerInfo); 8003aa4: 4b05 ldr r3, [pc, #20] @ (8003abc ) 8003aa6: 2208 movs r2, #8 8003aa8: 2106 movs r1, #6 8003aaa: f44f 7080 mov.w r0, #256 @ 0x100 8003aae: f000 fad3 bl 8004058 } 8003ab2: bf00 nop 8003ab4: 3708 adds r7, #8 8003ab6: 46bd mov sp, r7 8003ab8: bd80 pop {r7, pc} 8003aba: bf00 nop 8003abc: 2000030c .word 0x2000030c 08003ac0 : //GB/T CRO packet (Charger ready) void GBT_SendCRO(uint8_t state){ 8003ac0: b580 push {r7, lr} 8003ac2: b084 sub sp, #16 8003ac4: af00 add r7, sp, #0 8003ac6: 4603 mov r3, r0 8003ac8: 71fb strb r3, [r7, #7] uint8_t data[1]; data[0] = state; 8003aca: 79fb ldrb r3, [r7, #7] 8003acc: 733b strb r3, [r7, #12] J_SendPacket(0xA00, 4, 1, data); 8003ace: f107 030c add.w r3, r7, #12 8003ad2: 2201 movs r2, #1 8003ad4: 2104 movs r1, #4 8003ad6: f44f 6020 mov.w r0, #2560 @ 0xa00 8003ada: f000 fabd bl 8004058 } 8003ade: bf00 nop 8003ae0: 3710 adds r7, #16 8003ae2: 46bd mov sp, r7 8003ae4: bd80 pop {r7, pc} ... 08003ae8 : //GB/T CCS packet (Charger current status) void GBT_SendCCS(){ 8003ae8: b580 push {r7, lr} 8003aea: af00 add r7, sp, #0 // data[3] = GBT_CurrPower.requestedCurrent>>8; //TODO: current // data[4] = GBT_StateTick()/60000; //charging time (min) // data[5] = 0; //TODO: 255 min+ // data[6] = 0b11111101; //charging not permitted // data[7] = 0xFF; J_SendPacket(0x1200, 6, 8, (uint8_t *)&GBT_ChargerCurrentStatus); 8003aec: 4b04 ldr r3, [pc, #16] @ (8003b00 ) 8003aee: 2208 movs r2, #8 8003af0: 2106 movs r1, #6 8003af2: f44f 5090 mov.w r0, #4608 @ 0x1200 8003af6: f000 faaf bl 8004058 } 8003afa: bf00 nop 8003afc: bd80 pop {r7, pc} 8003afe: bf00 nop 8003b00: 20000380 .word 0x20000380 08003b04 : // GB/T Charging Stop packet void GBT_SendCST(uint32_t Cause){ 8003b04: b580 push {r7, lr} 8003b06: b084 sub sp, #16 8003b08: af00 add r7, sp, #0 8003b0a: 6078 str r0, [r7, #4] uint8_t data[8]; data[0] = (Cause>>24) & 0xFF; // Error 8003b0c: 687b ldr r3, [r7, #4] 8003b0e: 0e1b lsrs r3, r3, #24 8003b10: b2db uxtb r3, r3 8003b12: 723b strb r3, [r7, #8] data[1] = (Cause>>16) & 0xFF; // 8003b14: 687b ldr r3, [r7, #4] 8003b16: 0c1b lsrs r3, r3, #16 8003b18: b2db uxtb r3, r3 8003b1a: 727b strb r3, [r7, #9] data[2] = (Cause>>8) & 0xFF; // 8003b1c: 687b ldr r3, [r7, #4] 8003b1e: 0a1b lsrs r3, r3, #8 8003b20: b2db uxtb r3, r3 8003b22: 72bb strb r3, [r7, #10] data[3] = Cause & 0xFF; // 8003b24: 687b ldr r3, [r7, #4] 8003b26: b2db uxtb r3, r3 8003b28: 72fb strb r3, [r7, #11] J_SendPacket(0x1A00, 4, 4, data); 8003b2a: f107 0308 add.w r3, r7, #8 8003b2e: 2204 movs r2, #4 8003b30: 2104 movs r1, #4 8003b32: f44f 50d0 mov.w r0, #6656 @ 0x1a00 8003b36: f000 fa8f bl 8004058 } 8003b3a: bf00 nop 8003b3c: 3710 adds r7, #16 8003b3e: 46bd mov sp, r7 8003b40: bd80 pop {r7, pc} ... 08003b44 : void GBT_SendCSD(){ 8003b44: b580 push {r7, lr} 8003b46: af00 add r7, sp, #0 GBT_ChargerStop.chargerNumber = GBT_ChargerInfo.chargerNumber; 8003b48: 4b0b ldr r3, [pc, #44] @ (8003b78 ) 8003b4a: f8d3 3001 ldr.w r3, [r3, #1] 8003b4e: 4a0b ldr r2, [pc, #44] @ (8003b7c ) 8003b50: 6053 str r3, [r2, #4] GBT_ChargerStop.outputEnergy = 0; //TODO Energy meters 8003b52: 4b0a ldr r3, [pc, #40] @ (8003b7c ) 8003b54: 2200 movs r2, #0 8003b56: 709a strb r2, [r3, #2] 8003b58: 2200 movs r2, #0 8003b5a: 70da strb r2, [r3, #3] GBT_ChargerStop.chargingTime = GBT_ChargerCurrentStatus.chargingTime; 8003b5c: 4b08 ldr r3, [pc, #32] @ (8003b80 ) 8003b5e: 889b ldrh r3, [r3, #4] 8003b60: b29a uxth r2, r3 8003b62: 4b06 ldr r3, [pc, #24] @ (8003b7c ) 8003b64: 801a strh r2, [r3, #0] J_SendPacket(0x1D00, 6, 7, (uint8_t *)&GBT_ChargerStop); 8003b66: 4b05 ldr r3, [pc, #20] @ (8003b7c ) 8003b68: 2207 movs r2, #7 8003b6a: 2106 movs r1, #6 8003b6c: f44f 50e8 mov.w r0, #7424 @ 0x1d00 8003b70: f000 fa72 bl 8004058 } 8003b74: bf00 nop 8003b76: bd80 pop {r7, pc} 8003b78: 2000030c .word 0x2000030c 8003b7c: 20000388 .word 0x20000388 8003b80: 20000380 .word 0x20000380 08003b84 : void GBT_SendCEM(uint32_t ErrorCode){ 8003b84: b580 push {r7, lr} 8003b86: b084 sub sp, #16 8003b88: af00 add r7, sp, #0 8003b8a: 6078 str r0, [r7, #4] uint8_t data[8]; data[0] = (ErrorCode>>24) & 0xFF; // Error 8003b8c: 687b ldr r3, [r7, #4] 8003b8e: 0e1b lsrs r3, r3, #24 8003b90: b2db uxtb r3, r3 8003b92: 723b strb r3, [r7, #8] data[1] = (ErrorCode>>16) & 0xFF; // 8003b94: 687b ldr r3, [r7, #4] 8003b96: 0c1b lsrs r3, r3, #16 8003b98: b2db uxtb r3, r3 8003b9a: 727b strb r3, [r7, #9] data[2] = (ErrorCode>>8) & 0xFF; // 8003b9c: 687b ldr r3, [r7, #4] 8003b9e: 0a1b lsrs r3, r3, #8 8003ba0: b2db uxtb r3, r3 8003ba2: 72bb strb r3, [r7, #10] data[3] = ErrorCode & 0xFF; // 8003ba4: 687b ldr r3, [r7, #4] 8003ba6: b2db uxtb r3, r3 8003ba8: 72fb strb r3, [r7, #11] J_SendPacket(0x1F00, 4, 4, data); 8003baa: f107 0308 add.w r3, r7, #8 8003bae: 2204 movs r2, #4 8003bb0: 2104 movs r1, #4 8003bb2: f44f 50f8 mov.w r0, #7936 @ 0x1f00 8003bb6: f000 fa4f bl 8004058 } 8003bba: bf00 nop 8003bbc: 3710 adds r7, #16 8003bbe: 46bd mov sp, r7 8003bc0: bd80 pop {r7, pc} ... 08003bc4 : * Output * EVENT_OUT * EXTI */ void MX_GPIO_Init(void) { 8003bc4: b580 push {r7, lr} 8003bc6: b08a sub sp, #40 @ 0x28 8003bc8: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003bca: f107 0318 add.w r3, r7, #24 8003bce: 2200 movs r2, #0 8003bd0: 601a str r2, [r3, #0] 8003bd2: 605a str r2, [r3, #4] 8003bd4: 609a str r2, [r3, #8] 8003bd6: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8003bd8: 4b53 ldr r3, [pc, #332] @ (8003d28 ) 8003bda: 699b ldr r3, [r3, #24] 8003bdc: 4a52 ldr r2, [pc, #328] @ (8003d28 ) 8003bde: f043 0310 orr.w r3, r3, #16 8003be2: 6193 str r3, [r2, #24] 8003be4: 4b50 ldr r3, [pc, #320] @ (8003d28 ) 8003be6: 699b ldr r3, [r3, #24] 8003be8: f003 0310 and.w r3, r3, #16 8003bec: 617b str r3, [r7, #20] 8003bee: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8003bf0: 4b4d ldr r3, [pc, #308] @ (8003d28 ) 8003bf2: 699b ldr r3, [r3, #24] 8003bf4: 4a4c ldr r2, [pc, #304] @ (8003d28 ) 8003bf6: f043 0304 orr.w r3, r3, #4 8003bfa: 6193 str r3, [r2, #24] 8003bfc: 4b4a ldr r3, [pc, #296] @ (8003d28 ) 8003bfe: 699b ldr r3, [r3, #24] 8003c00: f003 0304 and.w r3, r3, #4 8003c04: 613b str r3, [r7, #16] 8003c06: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8003c08: 4b47 ldr r3, [pc, #284] @ (8003d28 ) 8003c0a: 699b ldr r3, [r3, #24] 8003c0c: 4a46 ldr r2, [pc, #280] @ (8003d28 ) 8003c0e: f043 0308 orr.w r3, r3, #8 8003c12: 6193 str r3, [r2, #24] 8003c14: 4b44 ldr r3, [pc, #272] @ (8003d28 ) 8003c16: 699b ldr r3, [r3, #24] 8003c18: f003 0308 and.w r3, r3, #8 8003c1c: 60fb str r3, [r7, #12] 8003c1e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 8003c20: 4b41 ldr r3, [pc, #260] @ (8003d28 ) 8003c22: 699b ldr r3, [r3, #24] 8003c24: 4a40 ldr r2, [pc, #256] @ (8003d28 ) 8003c26: f043 0340 orr.w r3, r3, #64 @ 0x40 8003c2a: 6193 str r3, [r2, #24] 8003c2c: 4b3e ldr r3, [pc, #248] @ (8003d28 ) 8003c2e: 699b ldr r3, [r3, #24] 8003c30: f003 0340 and.w r3, r3, #64 @ 0x40 8003c34: 60bb str r3, [r7, #8] 8003c36: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 8003c38: 4b3b ldr r3, [pc, #236] @ (8003d28 ) 8003c3a: 699b ldr r3, [r3, #24] 8003c3c: 4a3a ldr r2, [pc, #232] @ (8003d28 ) 8003c3e: f043 0320 orr.w r3, r3, #32 8003c42: 6193 str r3, [r2, #24] 8003c44: 4b38 ldr r3, [pc, #224] @ (8003d28 ) 8003c46: 699b ldr r3, [r3, #24] 8003c48: f003 0320 and.w r3, r3, #32 8003c4c: 607b str r3, [r7, #4] 8003c4e: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, LOCK_A_Pin|LOCK_B_Pin, GPIO_PIN_RESET); 8003c50: 2200 movs r2, #0 8003c52: 2130 movs r1, #48 @ 0x30 8003c54: 4835 ldr r0, [pc, #212] @ (8003d2c ) 8003c56: f003 fdec bl 8007832 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, GPIO_PIN_RESET); 8003c5a: 2200 movs r2, #0 8003c5c: f44f 4100 mov.w r1, #32768 @ 0x8000 8003c60: 4833 ldr r0, [pc, #204] @ (8003d30 ) 8003c62: f003 fde6 bl 8007832 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 8003c66: 2200 movs r2, #0 8003c68: 2110 movs r1, #16 8003c6a: 4832 ldr r0, [pc, #200] @ (8003d34 ) 8003c6c: f003 fde1 bl 8007832 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(RELAY_AUX_GPIO_Port, RELAY_AUX_Pin, GPIO_PIN_RESET); 8003c70: 2200 movs r2, #0 8003c72: 2110 movs r1, #16 8003c74: 4830 ldr r0, [pc, #192] @ (8003d38 ) 8003c76: f003 fddc bl 8007832 /*Configure GPIO pins : PCPin PCPin */ GPIO_InitStruct.Pin = LOCK_A_Pin|LOCK_B_Pin; 8003c7a: 2330 movs r3, #48 @ 0x30 8003c7c: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8003c7e: 2301 movs r3, #1 8003c80: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003c82: 2300 movs r3, #0 8003c84: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003c86: 2302 movs r3, #2 8003c88: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003c8a: f107 0318 add.w r3, r7, #24 8003c8e: 4619 mov r1, r3 8003c90: 4826 ldr r0, [pc, #152] @ (8003d2c ) 8003c92: f003 fc33 bl 80074fc /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = LOCK_FB_Pin; 8003c96: f44f 7300 mov.w r3, #512 @ 0x200 8003c9a: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8003c9c: 2300 movs r3, #0 8003c9e: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003ca0: 2300 movs r3, #0 8003ca2: 623b str r3, [r7, #32] HAL_GPIO_Init(LOCK_FB_GPIO_Port, &GPIO_InitStruct); 8003ca4: f107 0318 add.w r3, r7, #24 8003ca8: 4619 mov r1, r3 8003caa: 4821 ldr r0, [pc, #132] @ (8003d30 ) 8003cac: f003 fc26 bl 80074fc /*Configure GPIO pins : PEPin PEPin */ GPIO_InitStruct.Pin = ADDR_0_Pin|ADDR_1_Pin; 8003cb0: f44f 6340 mov.w r3, #3072 @ 0xc00 8003cb4: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8003cb6: 2300 movs r3, #0 8003cb8: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_PULLUP; 8003cba: 2301 movs r3, #1 8003cbc: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8003cbe: f107 0318 add.w r3, r7, #24 8003cc2: 4619 mov r1, r3 8003cc4: 481a ldr r0, [pc, #104] @ (8003d30 ) 8003cc6: f003 fc19 bl 80074fc /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = RELAY_CC_Pin; 8003cca: f44f 4300 mov.w r3, #32768 @ 0x8000 8003cce: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8003cd0: 2301 movs r3, #1 8003cd2: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003cd4: 2300 movs r3, #0 8003cd6: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003cd8: 2302 movs r3, #2 8003cda: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(RELAY_CC_GPIO_Port, &GPIO_InitStruct); 8003cdc: f107 0318 add.w r3, r7, #24 8003ce0: 4619 mov r1, r3 8003ce2: 4813 ldr r0, [pc, #76] @ (8003d30 ) 8003ce4: f003 fc0a bl 80074fc /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = USART2_DIR_Pin; 8003ce8: 2310 movs r3, #16 8003cea: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8003cec: 2301 movs r3, #1 8003cee: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003cf0: 2300 movs r3, #0 8003cf2: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003cf4: 2302 movs r3, #2 8003cf6: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(USART2_DIR_GPIO_Port, &GPIO_InitStruct); 8003cf8: f107 0318 add.w r3, r7, #24 8003cfc: 4619 mov r1, r3 8003cfe: 480d ldr r0, [pc, #52] @ (8003d34 ) 8003d00: f003 fbfc bl 80074fc /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = RELAY_AUX_Pin; 8003d04: 2310 movs r3, #16 8003d06: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8003d08: 2301 movs r3, #1 8003d0a: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003d0c: 2300 movs r3, #0 8003d0e: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003d10: 2302 movs r3, #2 8003d12: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(RELAY_AUX_GPIO_Port, &GPIO_InitStruct); 8003d14: f107 0318 add.w r3, r7, #24 8003d18: 4619 mov r1, r3 8003d1a: 4807 ldr r0, [pc, #28] @ (8003d38 ) 8003d1c: f003 fbee bl 80074fc } 8003d20: bf00 nop 8003d22: 3728 adds r7, #40 @ 0x28 8003d24: 46bd mov sp, r7 8003d26: bd80 pop {r7, pc} 8003d28: 40021000 .word 0x40021000 8003d2c: 40011000 .word 0x40011000 8003d30: 40011800 .word 0x40011800 8003d34: 40011400 .word 0x40011400 8003d38: 40010c00 .word 0x40010c00 08003d3c : extern GBT_BCL_t GBT_CurrPower; j_receive_t j_rx; void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { 8003d3c: b590 push {r4, r7, lr} 8003d3e: b0cd sub sp, #308 @ 0x134 8003d40: af40 add r7, sp, #256 @ 0x100 8003d42: 6078 str r0, [r7, #4] CAN_RxHeaderTypeDef RxHeader; uint8_t RxData[8] = {0,}; 8003d44: f107 030c add.w r3, r7, #12 8003d48: 2200 movs r2, #0 8003d4a: 601a str r2, [r3, #0] 8003d4c: 605a str r2, [r3, #4] if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &RxHeader, RxData) == HAL_OK) 8003d4e: f107 030c add.w r3, r7, #12 8003d52: f107 0214 add.w r2, r7, #20 8003d56: 2100 movs r1, #0 8003d58: 6878 ldr r0, [r7, #4] 8003d5a: f002 fe4a bl 80069f2 8003d5e: 4603 mov r3, r0 8003d60: 2b00 cmp r3, #0 8003d62: f040 8153 bne.w 800400c { if((RxHeader.ExtId & 0x00FFFF) == ((J_ID_SE << 8) | J_ID_EV)){ // SA, DA match 8003d66: 69bb ldr r3, [r7, #24] 8003d68: b29b uxth r3, r3 8003d6a: f245 62f4 movw r2, #22260 @ 0x56f4 8003d6e: 4293 cmp r3, r2 8003d70: f040 814c bne.w 800400c switch ((RxHeader.ExtId>>8) & 0x00FF00){ 8003d74: 69bb ldr r3, [r7, #24] 8003d76: 0a1b lsrs r3, r3, #8 8003d78: f403 437f and.w r3, r3, #65280 @ 0xff00 8003d7c: f5b3 4f6c cmp.w r3, #60416 @ 0xec00 8003d80: d013 beq.n 8003daa 8003d82: f5b3 4f6c cmp.w r3, #60416 @ 0xec00 8003d86: f200 810c bhi.w 8003fa2 8003d8a: f5b3 4f6b cmp.w r3, #60160 @ 0xeb00 8003d8e: d057 beq.n 8003e40 8003d90: f5b3 4f6b cmp.w r3, #60160 @ 0xeb00 8003d94: f200 8105 bhi.w 8003fa2 8003d98: f5b3 5fc8 cmp.w r3, #6400 @ 0x1900 8003d9c: f000 80dd beq.w 8003f5a 8003da0: f5b3 5ff0 cmp.w r3, #7680 @ 0x1e00 8003da4: f000 80b6 beq.w 8003f14 8003da8: e0fb b.n 8003fa2 case 0xEC00: //PGN Connection Management Message if(RxData[0] == 16){ //Request to Send 8003daa: 7b3b ldrb r3, [r7, #12] 8003dac: 2b10 cmp r3, #16 8003dae: d13e bne.n 8003e2e /* Set the RTS values */ j_rx.size = RxData[1] | (RxData[2]<<8); 8003db0: 7b7b ldrb r3, [r7, #13] 8003db2: b21a sxth r2, r3 8003db4: 7bbb ldrb r3, [r7, #14] 8003db6: b21b sxth r3, r3 8003db8: 021b lsls r3, r3, #8 8003dba: b21b sxth r3, r3 8003dbc: 4313 orrs r3, r2 8003dbe: b21b sxth r3, r3 8003dc0: b29a uxth r2, r3 8003dc2: 4b94 ldr r3, [pc, #592] @ (8004014 ) 8003dc4: f8a3 2104 strh.w r2, [r3, #260] @ 0x104 j_rx.packet = 1; 8003dc8: 4b92 ldr r3, [pc, #584] @ (8004014 ) 8003dca: 2201 movs r2, #1 8003dcc: f883 2107 strb.w r2, [r3, #263] @ 0x107 j_rx.packets = RxData[3]; 8003dd0: 7bfa ldrb r2, [r7, #15] 8003dd2: 4b90 ldr r3, [pc, #576] @ (8004014 ) 8003dd4: f883 2106 strb.w r2, [r3, #262] @ 0x106 j_rx.step = 2; //TODO 8003dd8: 4b8e ldr r3, [pc, #568] @ (8004014 ) 8003dda: 2202 movs r2, #2 8003ddc: f883 2108 strb.w r2, [r3, #264] @ 0x108 j_rx.step_cts_remain = j_rx.step; 8003de0: 4b8c ldr r3, [pc, #560] @ (8004014 ) 8003de2: f893 2108 ldrb.w r2, [r3, #264] @ 0x108 8003de6: 4b8b ldr r3, [pc, #556] @ (8004014 ) 8003de8: f883 2109 strb.w r2, [r3, #265] @ 0x109 j_rx.PGN = (RxData[7] << 16) | (RxData[6] << 8) | RxData[5]; 8003dec: 7cfb ldrb r3, [r7, #19] 8003dee: 041a lsls r2, r3, #16 8003df0: 7cbb ldrb r3, [r7, #18] 8003df2: 021b lsls r3, r3, #8 8003df4: 4313 orrs r3, r2 8003df6: 7c7a ldrb r2, [r7, #17] 8003df8: 4313 orrs r3, r2 8003dfa: 461a mov r2, r3 8003dfc: 4b85 ldr r3, [pc, #532] @ (8004014 ) 8003dfe: f8c3 2100 str.w r2, [r3, #256] @ 0x100 if(j_rx.size<256) { //TODO: valid check 8003e02: 4b84 ldr r3, [pc, #528] @ (8004014 ) 8003e04: f8b3 3104 ldrh.w r3, [r3, #260] @ 0x104 8003e08: 2bff cmp r3, #255 @ 0xff 8003e0a: d810 bhi.n 8003e2e J_SendCTS(j_rx); 8003e0c: 4c81 ldr r4, [pc, #516] @ (8004014 ) 8003e0e: 4668 mov r0, sp 8003e10: f104 0310 add.w r3, r4, #16 8003e14: f44f 7280 mov.w r2, #256 @ 0x100 8003e18: 4619 mov r1, r3 8003e1a: f006 fe77 bl 800ab0c 8003e1e: e894 000f ldmia.w r4, {r0, r1, r2, r3} 8003e22: f000 f941 bl 80040a8 j_rx.state = 1; 8003e26: 4b7b ldr r3, [pc, #492] @ (8004014 ) 8003e28: 2201 movs r2, #1 8003e2a: f883 210a strb.w r2, [r3, #266] @ 0x10a } } if(RxData[0] == 255){ //Connection Abort 8003e2e: 7b3b ldrb r3, [r7, #12] 8003e30: 2bff cmp r3, #255 @ 0xff 8003e32: f040 80e6 bne.w 8004002 j_rx.state = 0; 8003e36: 4b77 ldr r3, [pc, #476] @ (8004014 ) 8003e38: 2200 movs r2, #0 8003e3a: f883 210a strb.w r2, [r3, #266] @ 0x10a * 1CECF456 11 02 01 FF FF 00 02 00 * 1CEB56F4 01 01 01 00 03 46 05 40 * 1CEC56F4 FF FF FF FF FF 00 00 00 */ break; 8003e3e: e0e0 b.n 8004002 case 0xEB00: //PGN Data Message if(j_rx.state != 1) break; 8003e40: 4b74 ldr r3, [pc, #464] @ (8004014 ) 8003e42: f893 310a ldrb.w r3, [r3, #266] @ 0x10a 8003e46: 2b01 cmp r3, #1 8003e48: f040 80dd bne.w 8004006 if((RxData[0]>0) && (RxData[0]<35)){ //Array limit check 8003e4c: 7b3b ldrb r3, [r7, #12] 8003e4e: 2b00 cmp r3, #0 8003e50: f000 80db beq.w 800400a 8003e54: 7b3b ldrb r3, [r7, #12] 8003e56: 2b22 cmp r3, #34 @ 0x22 8003e58: f200 80d7 bhi.w 800400a if(j_rx.packet == RxData[0]){ //step check 8003e5c: 4b6d ldr r3, [pc, #436] @ (8004014 ) 8003e5e: f893 2107 ldrb.w r2, [r3, #263] @ 0x107 8003e62: 7b3b ldrb r3, [r7, #12] 8003e64: 429a cmp r2, r3 8003e66: f040 80d0 bne.w 800400a memcpy (&j_rx.data[(RxData[0]-1)*7], &RxData[1],7); 8003e6a: 7b3b ldrb r3, [r7, #12] 8003e6c: 1e5a subs r2, r3, #1 8003e6e: 4613 mov r3, r2 8003e70: 00db lsls r3, r3, #3 8003e72: 1a9b subs r3, r3, r2 8003e74: 4a67 ldr r2, [pc, #412] @ (8004014 ) 8003e76: 1898 adds r0, r3, r2 8003e78: f107 030c add.w r3, r7, #12 8003e7c: 3301 adds r3, #1 8003e7e: 2207 movs r2, #7 8003e80: 4619 mov r1, r3 8003e82: f006 fe43 bl 800ab0c j_rx.packet++; 8003e86: 4b63 ldr r3, [pc, #396] @ (8004014 ) 8003e88: f893 3107 ldrb.w r3, [r3, #263] @ 0x107 8003e8c: 3301 adds r3, #1 8003e8e: b2da uxtb r2, r3 8003e90: 4b60 ldr r3, [pc, #384] @ (8004014 ) 8003e92: f883 2107 strb.w r2, [r3, #263] @ 0x107 if(j_rx.packet > j_rx.packets){ 8003e96: 4b5f ldr r3, [pc, #380] @ (8004014 ) 8003e98: f893 2107 ldrb.w r2, [r3, #263] @ 0x107 8003e9c: 4b5d ldr r3, [pc, #372] @ (8004014 ) 8003e9e: f893 3106 ldrb.w r3, [r3, #262] @ 0x106 8003ea2: 429a cmp r2, r3 8003ea4: d911 bls.n 8003eca //End of transmission J_SendACK(j_rx); 8003ea6: 4c5b ldr r4, [pc, #364] @ (8004014 ) 8003ea8: 4668 mov r0, sp 8003eaa: f104 0310 add.w r3, r4, #16 8003eae: f44f 7280 mov.w r2, #256 @ 0x100 8003eb2: 4619 mov r1, r3 8003eb4: f006 fe2a bl 800ab0c 8003eb8: e894 000f ldmia.w r4, {r0, r1, r2, r3} 8003ebc: f000 f93a bl 8004134 j_rx.state = 2; 8003ec0: 4b54 ldr r3, [pc, #336] @ (8004014 ) 8003ec2: 2202 movs r2, #2 8003ec4: f883 210a strb.w r2, [r3, #266] @ 0x10a j_rx.step_cts_remain = 2; } } } } break; 8003ec8: e09f b.n 800400a if(j_rx.step_cts_remain > 0) j_rx.step_cts_remain--; 8003eca: 4b52 ldr r3, [pc, #328] @ (8004014 ) 8003ecc: f893 3109 ldrb.w r3, [r3, #265] @ 0x109 8003ed0: 2b00 cmp r3, #0 8003ed2: d007 beq.n 8003ee4 8003ed4: 4b4f ldr r3, [pc, #316] @ (8004014 ) 8003ed6: f893 3109 ldrb.w r3, [r3, #265] @ 0x109 8003eda: 3b01 subs r3, #1 8003edc: b2da uxtb r2, r3 8003ede: 4b4d ldr r3, [pc, #308] @ (8004014 ) 8003ee0: f883 2109 strb.w r2, [r3, #265] @ 0x109 if(j_rx.step_cts_remain == 0){ 8003ee4: 4b4b ldr r3, [pc, #300] @ (8004014 ) 8003ee6: f893 3109 ldrb.w r3, [r3, #265] @ 0x109 8003eea: 2b00 cmp r3, #0 8003eec: f040 808d bne.w 800400a J_SendCTS(j_rx); 8003ef0: 4c48 ldr r4, [pc, #288] @ (8004014 ) 8003ef2: 4668 mov r0, sp 8003ef4: f104 0310 add.w r3, r4, #16 8003ef8: f44f 7280 mov.w r2, #256 @ 0x100 8003efc: 4619 mov r1, r3 8003efe: f006 fe05 bl 800ab0c 8003f02: e894 000f ldmia.w r4, {r0, r1, r2, r3} 8003f06: f000 f8cf bl 80040a8 j_rx.step_cts_remain = 2; 8003f0a: 4b42 ldr r3, [pc, #264] @ (8004014 ) 8003f0c: 2202 movs r2, #2 8003f0e: f883 2109 strb.w r2, [r3, #265] @ 0x109 break; 8003f12: e07a b.n 800400a case 0x1E00: //PGN BEM (ERROR) //Error force stop // --> Suspend EV EDCAN_printf(LOG_WARN, "BEM Received, force stopping...\n"); 8003f14: 4940 ldr r1, [pc, #256] @ (8004018 ) 8003f16: 2004 movs r0, #4 8003f18: f000 ff2e bl 8004d78 EDCAN_printf(LOG_WARN, "BEM: %02X %02X %02X %02X", RxData[0], RxData[1], RxData[2], RxData[3]); 8003f1c: 7b3b ldrb r3, [r7, #12] 8003f1e: 4619 mov r1, r3 8003f20: 7b7b ldrb r3, [r7, #13] 8003f22: 4618 mov r0, r3 8003f24: 7bbb ldrb r3, [r7, #14] 8003f26: 7bfa ldrb r2, [r7, #15] 8003f28: 9201 str r2, [sp, #4] 8003f2a: 9300 str r3, [sp, #0] 8003f2c: 4603 mov r3, r0 8003f2e: 460a mov r2, r1 8003f30: 493a ldr r1, [pc, #232] @ (800401c ) 8003f32: 2004 movs r0, #4 8003f34: f000 ff20 bl 8004d78 EDCAN_printf(LOG_WARN, " %02X %02X %02X %02X\n", RxData[4], RxData[5], RxData[6], RxData[7]); 8003f38: 7c3b ldrb r3, [r7, #16] 8003f3a: 4619 mov r1, r3 8003f3c: 7c7b ldrb r3, [r7, #17] 8003f3e: 4618 mov r0, r3 8003f40: 7cbb ldrb r3, [r7, #18] 8003f42: 7cfa ldrb r2, [r7, #19] 8003f44: 9201 str r2, [sp, #4] 8003f46: 9300 str r3, [sp, #0] 8003f48: 4603 mov r3, r0 8003f4a: 460a mov r2, r1 8003f4c: 4934 ldr r1, [pc, #208] @ (8004020 ) 8003f4e: 2004 movs r0, #4 8003f50: f000 ff12 bl 8004d78 GBT_ForceStop(); 8003f54: f7fe fc56 bl 8002804 break; 8003f58: e058 b.n 800400c case 0x1900: //PGN BST (STOP) //Normal stop // --> Suspend EV EDCAN_printf(LOG_WARN, "BST Received, stopping...\n"); 8003f5a: 4932 ldr r1, [pc, #200] @ (8004024 ) 8003f5c: 2004 movs r0, #4 8003f5e: f000 ff0b bl 8004d78 EDCAN_printf(LOG_WARN, "BST: %02X %02X %02X %02X", RxData[0], RxData[1], RxData[2], RxData[3]); 8003f62: 7b3b ldrb r3, [r7, #12] 8003f64: 4619 mov r1, r3 8003f66: 7b7b ldrb r3, [r7, #13] 8003f68: 4618 mov r0, r3 8003f6a: 7bbb ldrb r3, [r7, #14] 8003f6c: 7bfa ldrb r2, [r7, #15] 8003f6e: 9201 str r2, [sp, #4] 8003f70: 9300 str r3, [sp, #0] 8003f72: 4603 mov r3, r0 8003f74: 460a mov r2, r1 8003f76: 492c ldr r1, [pc, #176] @ (8004028 ) 8003f78: 2004 movs r0, #4 8003f7a: f000 fefd bl 8004d78 EDCAN_printf(LOG_WARN, " %02X %02X %02X %02X\n", RxData[4], RxData[5], RxData[6], RxData[7]); 8003f7e: 7c3b ldrb r3, [r7, #16] 8003f80: 4619 mov r1, r3 8003f82: 7c7b ldrb r3, [r7, #17] 8003f84: 4618 mov r0, r3 8003f86: 7cbb ldrb r3, [r7, #18] 8003f88: 7cfa ldrb r2, [r7, #19] 8003f8a: 9201 str r2, [sp, #4] 8003f8c: 9300 str r3, [sp, #0] 8003f8e: 4603 mov r3, r0 8003f90: 460a mov r2, r1 8003f92: 4923 ldr r1, [pc, #140] @ (8004020 ) 8003f94: 2004 movs r0, #4 8003f96: f000 feef bl 8004d78 GBT_StopEV(GBT_CST_BMS_ACTIVELY_SUSPENDS); 8003f9a: 4824 ldr r0, [pc, #144] @ (800402c ) 8003f9c: f7fe fbce bl 800273c break; 8003fa0: e034 b.n 800400c default: if(j_rx.state == 0){//TODO protections 8003fa2: 4b1c ldr r3, [pc, #112] @ (8004014 ) 8003fa4: f893 310a ldrb.w r3, [r3, #266] @ 0x10a 8003fa8: 2b00 cmp r3, #0 8003faa: d12f bne.n 800400c //Short packet j_rx.size = RxHeader.DLC; 8003fac: 6a7b ldr r3, [r7, #36] @ 0x24 8003fae: b29a uxth r2, r3 8003fb0: 4b18 ldr r3, [pc, #96] @ (8004014 ) 8003fb2: f8a3 2104 strh.w r2, [r3, #260] @ 0x104 j_rx.packet = 1; 8003fb6: 4b17 ldr r3, [pc, #92] @ (8004014 ) 8003fb8: 2201 movs r2, #1 8003fba: f883 2107 strb.w r2, [r3, #263] @ 0x107 j_rx.packets = 1; 8003fbe: 4b15 ldr r3, [pc, #84] @ (8004014 ) 8003fc0: 2201 movs r2, #1 8003fc2: f883 2106 strb.w r2, [r3, #262] @ 0x106 j_rx.step = 1; 8003fc6: 4b13 ldr r3, [pc, #76] @ (8004014 ) 8003fc8: 2201 movs r2, #1 8003fca: f883 2108 strb.w r2, [r3, #264] @ 0x108 j_rx.step_cts_remain = 0; 8003fce: 4b11 ldr r3, [pc, #68] @ (8004014 ) 8003fd0: 2200 movs r2, #0 8003fd2: f883 2109 strb.w r2, [r3, #265] @ 0x109 j_rx.PGN = (RxHeader.ExtId>>8) & 0x00FF00; 8003fd6: 69bb ldr r3, [r7, #24] 8003fd8: 0a1b lsrs r3, r3, #8 8003fda: f403 437f and.w r3, r3, #65280 @ 0xff00 8003fde: 4a0d ldr r2, [pc, #52] @ (8004014 ) 8003fe0: f8c2 3100 str.w r3, [r2, #256] @ 0x100 j_rx.state = 2; 8003fe4: 4b0b ldr r3, [pc, #44] @ (8004014 ) 8003fe6: 2202 movs r2, #2 8003fe8: f883 210a strb.w r2, [r3, #266] @ 0x10a memcpy (j_rx.data, RxData, j_rx.size); 8003fec: 4b09 ldr r3, [pc, #36] @ (8004014 ) 8003fee: f8b3 3104 ldrh.w r3, [r3, #260] @ 0x104 8003ff2: 461a mov r2, r3 8003ff4: f107 030c add.w r3, r7, #12 8003ff8: 4619 mov r1, r3 8003ffa: 4806 ldr r0, [pc, #24] @ (8004014 ) 8003ffc: f006 fd86 bl 800ab0c } } } } } 8004000: e004 b.n 800400c break; 8004002: bf00 nop 8004004: e002 b.n 800400c if(j_rx.state != 1) break; 8004006: bf00 nop 8004008: e000 b.n 800400c break; 800400a: bf00 nop } 800400c: bf00 nop 800400e: 3734 adds r7, #52 @ 0x34 8004010: 46bd mov sp, r7 8004012: bd90 pop {r4, r7, pc} 8004014: 200004cc .word 0x200004cc 8004018: 0800de60 .word 0x0800de60 800401c: 0800de84 .word 0x0800de84 8004020: 0800dea0 .word 0x0800dea0 8004024: 0800deb8 .word 0x0800deb8 8004028: 0800ded4 .word 0x0800ded4 800402c: 4000f0f0 .word 0x4000f0f0 08004030 : void GBT_CAN_ReInit(){ 8004030: b580 push {r7, lr} 8004032: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan1); 8004034: 4807 ldr r0, [pc, #28] @ (8004054 ) 8004036: f002 fb85 bl 8006744 MX_CAN1_Init(); 800403a: f7fd fc8b bl 8001954 HAL_CAN_Start(&hcan1); 800403e: 4805 ldr r0, [pc, #20] @ (8004054 ) 8004040: f002 fb3c bl 80066bc HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING); 8004044: 2102 movs r1, #2 8004046: 4803 ldr r0, [pc, #12] @ (8004054 ) 8004048: f002 fde4 bl 8006c14 GBT_CAN_FilterInit(); 800404c: f000 f8ac bl 80041a8 } 8004050: bf00 nop 8004052: bd80 pop {r7, pc} 8004054: 20000298 .word 0x20000298 08004058 : void J_SendPacket(uint32_t PGN, uint8_t pri, uint8_t DLC, uint8_t *data){ 8004058: b580 push {r7, lr} 800405a: b08c sub sp, #48 @ 0x30 800405c: af00 add r7, sp, #0 800405e: 60f8 str r0, [r7, #12] 8004060: 607b str r3, [r7, #4] 8004062: 460b mov r3, r1 8004064: 72fb strb r3, [r7, #11] 8004066: 4613 mov r3, r2 8004068: 72bb strb r3, [r7, #10] CAN_TxHeaderTypeDef tx_header; uint32_t tx_mailbox; tx_header.ExtId = (pri << 26) | (PGN << 8) | (J_ID_EV << 8) | J_ID_SE; 800406a: 7afb ldrb r3, [r7, #11] 800406c: 069a lsls r2, r3, #26 800406e: 68fb ldr r3, [r7, #12] 8004070: 021b lsls r3, r3, #8 8004072: 4313 orrs r3, r2 8004074: f443 4374 orr.w r3, r3, #62464 @ 0xf400 8004078: f043 0356 orr.w r3, r3, #86 @ 0x56 800407c: 61fb str r3, [r7, #28] tx_header.RTR = CAN_RTR_DATA; 800407e: 2300 movs r3, #0 8004080: 627b str r3, [r7, #36] @ 0x24 tx_header.IDE = CAN_ID_EXT; 8004082: 2304 movs r3, #4 8004084: 623b str r3, [r7, #32] tx_header.DLC = DLC; 8004086: 7abb ldrb r3, [r7, #10] 8004088: 62bb str r3, [r7, #40] @ 0x28 //TODO buffer wait HAL_CAN_AddTxMessage(&hcan1, &tx_header, data, &tx_mailbox); 800408a: f107 0314 add.w r3, r7, #20 800408e: f107 0118 add.w r1, r7, #24 8004092: 687a ldr r2, [r7, #4] 8004094: 4803 ldr r0, [pc, #12] @ (80040a4 ) 8004096: f002 fb9e bl 80067d6 //HAL_Delay(2); } 800409a: bf00 nop 800409c: 3730 adds r7, #48 @ 0x30 800409e: 46bd mov sp, r7 80040a0: bd80 pop {r7, pc} 80040a2: bf00 nop 80040a4: 20000298 .word 0x20000298 080040a8 : //void J_SendPacketLong(){ // //TODO (no need) //} // J1939 sequence Clear To Send packet void J_SendCTS(j_receive_t rx){ 80040a8: b084 sub sp, #16 80040aa: b580 push {r7, lr} 80040ac: b082 sub sp, #8 80040ae: af00 add r7, sp, #0 80040b0: f107 0c10 add.w ip, r7, #16 80040b4: e88c 000f stmia.w ip, {r0, r1, r2, r3} //if(rx.packets <= rx.packet) return; TODO uint8_t data[8]; data[0] = 17; //CONTROL_BYTE_TP_CM_CTS 80040b8: 2311 movs r3, #17 80040ba: 703b strb r3, [r7, #0] data[1] = rx.step;//total_number_of_packages_transmitted 80040bc: f897 3118 ldrb.w r3, [r7, #280] @ 0x118 80040c0: 707b strb r3, [r7, #1] if (rx.step > (rx.packets - rx.packet+1)) data[1] = rx.packets - rx.packet+1; 80040c2: f897 3118 ldrb.w r3, [r7, #280] @ 0x118 80040c6: 461a mov r2, r3 80040c8: f897 3116 ldrb.w r3, [r7, #278] @ 0x116 80040cc: 4619 mov r1, r3 80040ce: f897 3117 ldrb.w r3, [r7, #279] @ 0x117 80040d2: 1acb subs r3, r1, r3 80040d4: 3301 adds r3, #1 80040d6: 429a cmp r2, r3 80040d8: dd08 ble.n 80040ec 80040da: f897 2116 ldrb.w r2, [r7, #278] @ 0x116 80040de: f897 3117 ldrb.w r3, [r7, #279] @ 0x117 80040e2: 1ad3 subs r3, r2, r3 80040e4: b2db uxtb r3, r3 80040e6: 3301 adds r3, #1 80040e8: b2db uxtb r3, r3 80040ea: 707b strb r3, [r7, #1] data[2] = rx.packet;//next_packet_number_transmitted 80040ec: f897 3117 ldrb.w r3, [r7, #279] @ 0x117 80040f0: 70bb strb r3, [r7, #2] data[3] = 0xFF; /* Reserved */ 80040f2: 23ff movs r3, #255 @ 0xff 80040f4: 70fb strb r3, [r7, #3] data[4] = 0xFF; 80040f6: 23ff movs r3, #255 @ 0xff 80040f8: 713b strb r3, [r7, #4] data[5] = rx.PGN; 80040fa: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 80040fe: b2db uxtb r3, r3 8004100: 717b strb r3, [r7, #5] data[6] = rx.PGN >> 8; 8004102: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 8004106: 0a1b lsrs r3, r3, #8 8004108: b2db uxtb r3, r3 800410a: 71bb strb r3, [r7, #6] data[7] = rx.PGN >> 16; 800410c: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 8004110: 0c1b lsrs r3, r3, #16 8004112: b2db uxtb r3, r3 8004114: 71fb strb r3, [r7, #7] J_SendPacket(0x00EC00, 7, 8, data); 8004116: 463b mov r3, r7 8004118: 2208 movs r2, #8 800411a: 2107 movs r1, #7 800411c: f44f 406c mov.w r0, #60416 @ 0xec00 8004120: f7ff ff9a bl 8004058 } 8004124: bf00 nop 8004126: 3708 adds r7, #8 8004128: 46bd mov sp, r7 800412a: e8bd 4080 ldmia.w sp!, {r7, lr} 800412e: b004 add sp, #16 8004130: 4770 bx lr ... 08004134 : // J1939 sequence ACK packet void J_SendACK(j_receive_t rx){//uint32_t PGN, uint8_t step, uint8_t packet){ 8004134: b084 sub sp, #16 8004136: b580 push {r7, lr} 8004138: b082 sub sp, #8 800413a: af00 add r7, sp, #0 800413c: f107 0c10 add.w ip, r7, #16 8004140: e88c 000f stmia.w ip, {r0, r1, r2, r3} uint8_t data[8]; data[0] = 19; //CONTROL_BYTE_TP_CM_ACK 8004144: 2313 movs r3, #19 8004146: 703b strb r3, [r7, #0] data[1] = j_rx.size; 8004148: 4b16 ldr r3, [pc, #88] @ (80041a4 ) 800414a: f8b3 3104 ldrh.w r3, [r3, #260] @ 0x104 800414e: b2db uxtb r3, r3 8004150: 707b strb r3, [r7, #1] data[2] = j_rx.size>>8; 8004152: 4b14 ldr r3, [pc, #80] @ (80041a4 ) 8004154: f8b3 3104 ldrh.w r3, [r3, #260] @ 0x104 8004158: 0a1b lsrs r3, r3, #8 800415a: b29b uxth r3, r3 800415c: b2db uxtb r3, r3 800415e: 70bb strb r3, [r7, #2] data[3] = j_rx.packets; 8004160: 4b10 ldr r3, [pc, #64] @ (80041a4 ) 8004162: f893 3106 ldrb.w r3, [r3, #262] @ 0x106 8004166: 70fb strb r3, [r7, #3] data[4] = 0xFF;//TODO 8004168: 23ff movs r3, #255 @ 0xff 800416a: 713b strb r3, [r7, #4] data[5] = rx.PGN; 800416c: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 8004170: b2db uxtb r3, r3 8004172: 717b strb r3, [r7, #5] data[6] = rx.PGN >> 8; 8004174: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 8004178: 0a1b lsrs r3, r3, #8 800417a: b2db uxtb r3, r3 800417c: 71bb strb r3, [r7, #6] data[7] = rx.PGN >> 16; 800417e: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 8004182: 0c1b lsrs r3, r3, #16 8004184: b2db uxtb r3, r3 8004186: 71fb strb r3, [r7, #7] J_SendPacket(0x00EC00, 7, 8, data); 8004188: 463b mov r3, r7 800418a: 2208 movs r2, #8 800418c: 2107 movs r1, #7 800418e: f44f 406c mov.w r0, #60416 @ 0xec00 8004192: f7ff ff61 bl 8004058 } 8004196: bf00 nop 8004198: 3708 adds r7, #8 800419a: 46bd mov sp, r7 800419c: e8bd 4080 ldmia.w sp!, {r7, lr} 80041a0: b004 add sp, #16 80041a2: 4770 bx lr 80041a4: 200004cc .word 0x200004cc 080041a8 : void GBT_CAN_FilterInit(){ 80041a8: b580 push {r7, lr} 80041aa: b08a sub sp, #40 @ 0x28 80041ac: af00 add r7, sp, #0 CAN_FilterTypeDef sFilterConfig; sFilterConfig.FilterBank = 0; 80041ae: 2300 movs r3, #0 80041b0: 617b str r3, [r7, #20] sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; 80041b2: 2300 movs r3, #0 80041b4: 61bb str r3, [r7, #24] sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; 80041b6: 2301 movs r3, #1 80041b8: 61fb str r3, [r7, #28] sFilterConfig.FilterIdHigh = 0x0000; 80041ba: 2300 movs r3, #0 80041bc: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = 0x0000; 80041be: 2300 movs r3, #0 80041c0: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 80041c2: 2300 movs r3, #0 80041c4: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = 0x0000; 80041c6: 2300 movs r3, #0 80041c8: 60fb str r3, [r7, #12] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; 80041ca: 2300 movs r3, #0 80041cc: 613b str r3, [r7, #16] sFilterConfig.FilterActivation = ENABLE; 80041ce: 2301 movs r3, #1 80041d0: 623b str r3, [r7, #32] //sFilterConfig.SlaveStartFilterBank = 14; if(HAL_CAN_ConfigFilter(&hcan1, &sFilterConfig) != HAL_OK) 80041d2: 463b mov r3, r7 80041d4: 4619 mov r1, r3 80041d6: 4806 ldr r0, [pc, #24] @ (80041f0 ) 80041d8: f002 f990 bl 80064fc 80041dc: 4603 mov r3, r0 80041de: 2b00 cmp r3, #0 80041e0: d001 beq.n 80041e6 { Error_Handler(); 80041e2: f000 ff31 bl 8005048 } } 80041e6: bf00 nop 80041e8: 3728 adds r7, #40 @ 0x28 80041ea: 46bd mov sp, r7 80041ec: bd80 pop {r7, pc} 80041ee: bf00 nop 80041f0: 20000298 .word 0x20000298 080041f4 : .retry_count = 0, .error_tick = 0 }; void GBT_ForceLock(uint8_t state){ 80041f4: b480 push {r7} 80041f6: b083 sub sp, #12 80041f8: af00 add r7, sp, #0 80041fa: 4603 mov r3, r0 80041fc: 71fb strb r3, [r7, #7] // Устанавливаем флаг для выполнения действия GBT_LockState.action_requested = state ? 1 : 0; 80041fe: 79fb ldrb r3, [r7, #7] 8004200: 2b00 cmp r3, #0 8004202: bf14 ite ne 8004204: 2301 movne r3, #1 8004206: 2300 moveq r3, #0 8004208: b2db uxtb r3, r3 800420a: 461a mov r2, r3 800420c: 4b04 ldr r3, [pc, #16] @ (8004220 ) 800420e: 709a strb r2, [r3, #2] GBT_LockState.retry_count = 0; 8004210: 4b03 ldr r3, [pc, #12] @ (8004220 ) 8004212: 2200 movs r2, #0 8004214: 721a strb r2, [r3, #8] } 8004216: bf00 nop 8004218: 370c adds r7, #12 800421a: 46bd mov sp, r7 800421c: bc80 pop {r7} 800421e: 4770 bx lr 8004220: 20000000 .word 0x20000000 08004224 : uint8_t GBT_LockGetState(){ 8004224: b580 push {r7, lr} 8004226: af00 add r7, sp, #0 //1 = locked //0 = unlocked if(LOCK_POLARITY){ 8004228: 4b0b ldr r3, [pc, #44] @ (8004258 ) 800422a: 781b ldrb r3, [r3, #0] 800422c: 2b00 cmp r3, #0 800422e: d006 beq.n 800423e return HAL_GPIO_ReadPin(LOCK_FB_GPIO_Port, LOCK_FB_Pin); 8004230: f44f 7100 mov.w r1, #512 @ 0x200 8004234: 4809 ldr r0, [pc, #36] @ (800425c ) 8004236: f003 fae5 bl 8007804 800423a: 4603 mov r3, r0 800423c: e00a b.n 8004254 }else{ return !HAL_GPIO_ReadPin(LOCK_FB_GPIO_Port, LOCK_FB_Pin); 800423e: f44f 7100 mov.w r1, #512 @ 0x200 8004242: 4806 ldr r0, [pc, #24] @ (800425c ) 8004244: f003 fade bl 8007804 8004248: 4603 mov r3, r0 800424a: 2b00 cmp r3, #0 800424c: bf0c ite eq 800424e: 2301 moveq r3, #1 8004250: 2300 movne r3, #0 8004252: b2db uxtb r3, r3 } } 8004254: 4618 mov r0, r3 8004256: bd80 pop {r7, pc} 8004258: 200005dc .word 0x200005dc 800425c: 40011800 .word 0x40011800 08004260 : void GBT_Lock(uint8_t state){ 8004260: b480 push {r7} 8004262: b083 sub sp, #12 8004264: af00 add r7, sp, #0 8004266: 4603 mov r3, r0 8004268: 71fb strb r3, [r7, #7] GBT_LockState.demand = state; 800426a: 4a04 ldr r2, [pc, #16] @ (800427c ) 800426c: 79fb ldrb r3, [r7, #7] 800426e: 7013 strb r3, [r2, #0] } 8004270: bf00 nop 8004272: 370c adds r7, #12 8004274: 46bd mov sp, r7 8004276: bc80 pop {r7} 8004278: 4770 bx lr 800427a: bf00 nop 800427c: 20000000 .word 0x20000000 08004280 <__NVIC_SystemReset>: { 8004280: b480 push {r7} 8004282: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 8004284: f3bf 8f4f dsb sy } 8004288: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800428a: 4b06 ldr r3, [pc, #24] @ (80042a4 <__NVIC_SystemReset+0x24>) 800428c: 68db ldr r3, [r3, #12] 800428e: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8004292: 4904 ldr r1, [pc, #16] @ (80042a4 <__NVIC_SystemReset+0x24>) 8004294: 4b04 ldr r3, [pc, #16] @ (80042a8 <__NVIC_SystemReset+0x28>) 8004296: 4313 orrs r3, r2 8004298: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800429a: f3bf 8f4f dsb sy } 800429e: bf00 nop __NOP(); 80042a0: bf00 nop 80042a2: e7fd b.n 80042a0 <__NVIC_SystemReset+0x20> 80042a4: e000ed00 .word 0xe000ed00 80042a8: 05fa0004 .word 0x05fa0004 080042ac : /** * @brief CAN Interrupt Handler for EDCAN (CAN2) * */ void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan){ 80042ac: b580 push {r7, lr} 80042ae: b082 sub sp, #8 80042b0: af00 add r7, sp, #0 80042b2: 6078 str r0, [r7, #4] if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO1, &RxHeader, RxData) == HAL_OK) 80042b4: 4b21 ldr r3, [pc, #132] @ (800433c ) 80042b6: 4a22 ldr r2, [pc, #136] @ (8004340 ) 80042b8: 2101 movs r1, #1 80042ba: 6878 ldr r0, [r7, #4] 80042bc: f002 fb99 bl 80069f2 80042c0: 4603 mov r3, r0 80042c2: 2b00 cmp r3, #0 80042c4: d136 bne.n 8004334 { memcpy(&RxFrame.ExtID, &RxHeader.ExtId, sizeof(RxFrame.ExtID)); 80042c6: 4b1e ldr r3, [pc, #120] @ (8004340 ) 80042c8: 685b ldr r3, [r3, #4] 80042ca: 4a1e ldr r2, [pc, #120] @ (8004344 ) 80042cc: 6013 str r3, [r2, #0] RxFrame.DLC = RxHeader.DLC; 80042ce: 4b1c ldr r3, [pc, #112] @ (8004340 ) 80042d0: 691b ldr r3, [r3, #16] 80042d2: b2da uxtb r2, r3 80042d4: 4b1b ldr r3, [pc, #108] @ (8004344 ) 80042d6: 731a strb r2, [r3, #12] memcpy(RxFrame.data, RxData, RxHeader.DLC); 80042d8: 4b19 ldr r3, [pc, #100] @ (8004340 ) 80042da: 691b ldr r3, [r3, #16] 80042dc: 461a mov r2, r3 80042de: 4917 ldr r1, [pc, #92] @ (800433c ) 80042e0: 4819 ldr r0, [pc, #100] @ (8004348 ) 80042e2: f006 fc13 bl 800ab0c if((RxFrame.ExtID.DestinationID == ED_OwnID) || (RxFrame.ExtID.DestinationID == 0xFF) || (RxFrame.ExtID.DestinationID == ED_SecondID)){ 80042e6: 4b17 ldr r3, [pc, #92] @ (8004344 ) 80042e8: 781a ldrb r2, [r3, #0] 80042ea: 4b18 ldr r3, [pc, #96] @ (800434c ) 80042ec: 781b ldrb r3, [r3, #0] 80042ee: 429a cmp r2, r3 80042f0: d009 beq.n 8004306 80042f2: 4b14 ldr r3, [pc, #80] @ (8004344 ) 80042f4: 781b ldrb r3, [r3, #0] 80042f6: 2bff cmp r3, #255 @ 0xff 80042f8: d005 beq.n 8004306 80042fa: 4b12 ldr r3, [pc, #72] @ (8004344 ) 80042fc: 781a ldrb r2, [r3, #0] 80042fe: 4b14 ldr r3, [pc, #80] @ (8004350 ) 8004300: 781b ldrb r3, [r3, #0] 8004302: 429a cmp r2, r3 8004304: d116 bne.n 8004334 //Мгновенная перезагрузка #ifndef EDCAN_RESET_REG if(RxFrame.ExtID.RegisterAddress == 0x26){ 8004306: 4b0f ldr r3, [pc, #60] @ (8004344 ) 8004308: 885b ldrh r3, [r3, #2] 800430a: f3c3 030a ubfx r3, r3, #0, #11 800430e: b29b uxth r3, r3 8004310: 2b26 cmp r3, #38 @ 0x26 8004312: d105 bne.n 8004320 if(RxFrame.data[0] == 0x66) NVIC_SystemReset(); 8004314: 4b0b ldr r3, [pc, #44] @ (8004344 ) 8004316: 791b ldrb r3, [r3, #4] 8004318: 2b66 cmp r3, #102 @ 0x66 800431a: d101 bne.n 8004320 800431c: f7ff ffb0 bl 8004280 <__NVIC_SystemReset> if(RxFrame.ExtID.RegisterAddress == EDCAN_RESET_REG){ if(RxFrame.data[0] == 0x66) NVIC_SystemReset(); } #endif //Выходим из Silent Mode сразу после получения любого пакета if(silentmode_enable) EDCAN_EnterSilentMode(0); 8004320: 4b0c ldr r3, [pc, #48] @ (8004354 ) 8004322: 681b ldr r3, [r3, #0] 8004324: 2b00 cmp r3, #0 8004326: d002 beq.n 800432e 8004328: 2000 movs r0, #0 800432a: f000 f999 bl 8004660 EDCAN_RxBufferAdd (&RxFrame); 800432e: 4805 ldr r0, [pc, #20] @ (8004344 ) 8004330: f000 fb04 bl 800493c // EDCAN_ExchangeRxBuffer(); } } } 8004334: bf00 nop 8004336: 3708 adds r7, #8 8004338: 46bd mov sp, r7 800433a: bd80 pop {r7, pc} 800433c: 200005e0 .word 0x200005e0 8004340: 200005e8 .word 0x200005e8 8004344: 20000604 .word 0x20000604 8004348: 20000608 .word 0x20000608 800434c: 200005dd .word 0x200005dd 8004350: 20000010 .word 0x20000010 8004354: 2000061c .word 0x2000061c 08004358 : #endif void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan_){ 8004358: b580 push {r7, lr} 800435a: b082 sub sp, #8 800435c: af00 add r7, sp, #0 800435e: 6078 str r0, [r7, #4] if (hcan_->Instance == ED_CAN_INSTANCE.Instance){ 8004360: 687b ldr r3, [r7, #4] 8004362: 681a ldr r2, [r3, #0] 8004364: 4b07 ldr r3, [pc, #28] @ (8004384 ) 8004366: 681b ldr r3, [r3, #0] 8004368: 429a cmp r2, r3 800436a: d107 bne.n 800437c lasttxexchangetime = HAL_GetTick() + 1; 800436c: f001 fa98 bl 80058a0 8004370: 4603 mov r3, r0 8004372: 3301 adds r3, #1 8004374: 4a04 ldr r2, [pc, #16] @ (8004388 ) 8004376: 6013 str r3, [r2, #0] EDCAN_ExchangeTxBuffer(); 8004378: f000 fa88 bl 800488c } } 800437c: bf00 nop 800437e: 3708 adds r7, #8 8004380: 46bd mov sp, r7 8004382: bd80 pop {r7, pc} 8004384: 200002c0 .word 0x200002c0 8004388: 20000620 .word 0x20000620 0800438c : void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan_){ 800438c: b580 push {r7, lr} 800438e: b082 sub sp, #8 8004390: af00 add r7, sp, #0 8004392: 6078 str r0, [r7, #4] if (hcan_->Instance == ED_CAN_INSTANCE.Instance){ 8004394: 687b ldr r3, [r7, #4] 8004396: 681a ldr r2, [r3, #0] 8004398: 4b07 ldr r3, [pc, #28] @ (80043b8 ) 800439a: 681b ldr r3, [r3, #0] 800439c: 429a cmp r2, r3 800439e: d107 bne.n 80043b0 lasttxexchangetime = HAL_GetTick() + 1; 80043a0: f001 fa7e bl 80058a0 80043a4: 4603 mov r3, r0 80043a6: 3301 adds r3, #1 80043a8: 4a04 ldr r2, [pc, #16] @ (80043bc ) 80043aa: 6013 str r3, [r2, #0] EDCAN_ExchangeTxBuffer(); 80043ac: f000 fa6e bl 800488c } } 80043b0: bf00 nop 80043b2: 3708 adds r7, #8 80043b4: 46bd mov sp, r7 80043b6: bd80 pop {r7, pc} 80043b8: 200002c0 .word 0x200002c0 80043bc: 20000620 .word 0x20000620 080043c0 : void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan_){ 80043c0: b580 push {r7, lr} 80043c2: b082 sub sp, #8 80043c4: af00 add r7, sp, #0 80043c6: 6078 str r0, [r7, #4] if (hcan_->Instance == ED_CAN_INSTANCE.Instance){ 80043c8: 687b ldr r3, [r7, #4] 80043ca: 681a ldr r2, [r3, #0] 80043cc: 4b07 ldr r3, [pc, #28] @ (80043ec ) 80043ce: 681b ldr r3, [r3, #0] 80043d0: 429a cmp r2, r3 80043d2: d107 bne.n 80043e4 lasttxexchangetime = HAL_GetTick() + 1; 80043d4: f001 fa64 bl 80058a0 80043d8: 4603 mov r3, r0 80043da: 3301 adds r3, #1 80043dc: 4a04 ldr r2, [pc, #16] @ (80043f0 ) 80043de: 6013 str r3, [r2, #0] EDCAN_ExchangeTxBuffer(); 80043e0: f000 fa54 bl 800488c } } 80043e4: bf00 nop 80043e6: 3708 adds r7, #8 80043e8: 46bd mov sp, r7 80043ea: bd80 pop {r7, pc} 80043ec: 200002c0 .word 0x200002c0 80043f0: 20000620 .word 0x20000620 080043f4 : /** * @brief EDCAN Initialization function * * @param _OwnID: EDCAN Device ID */ void EDCAN_Init(uint8_t _OwnID){ 80043f4: b480 push {r7} 80043f6: b083 sub sp, #12 80043f8: af00 add r7, sp, #0 80043fa: 4603 mov r3, r0 80043fc: 71fb strb r3, [r7, #7] ED_OwnID = _OwnID; 80043fe: 4a04 ldr r2, [pc, #16] @ (8004410 ) 8004400: 79fb ldrb r3, [r7, #7] 8004402: 7013 strb r3, [r2, #0] }; 8004404: bf00 nop 8004406: 370c adds r7, #12 8004408: 46bd mov sp, r7 800440a: bc80 pop {r7} 800440c: 4770 bx lr 800440e: bf00 nop 8004410: 200005dd .word 0x200005dd 08004414 : /** * @brief CAN Reinitialization function * * */ void CAN_ReInit(){ 8004414: b580 push {r7, lr} 8004416: af00 add r7, sp, #0 HAL_CAN_Stop(&ED_CAN_INSTANCE); 8004418: 4807 ldr r0, [pc, #28] @ (8004438 ) 800441a: f002 f993 bl 8006744 #ifdef ED_CAN1 MX_CAN1_Init(); #endif #ifdef ED_CAN2 MX_CAN2_Init(); 800441e: f7fd facf bl 80019c0 #endif EDCAN_FilterInit(); 8004422: f000 f80b bl 800443c HAL_CAN_Start(&ED_CAN_INSTANCE); 8004426: 4804 ldr r0, [pc, #16] @ (8004438 ) 8004428: f002 f948 bl 80066bc #ifdef ED_CAN1 HAL_CAN_ActivateNotification(&ED_CAN_INSTANCE, CAN_IT_RX_FIFO0_MSG_PENDING | /*CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE |*/ CAN_IT_TX_MAILBOX_EMPTY); #endif #ifdef ED_CAN2 HAL_CAN_ActivateNotification(&ED_CAN_INSTANCE, CAN_IT_RX_FIFO1_MSG_PENDING | /*CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE |*/ CAN_IT_TX_MAILBOX_EMPTY); 800442c: 2111 movs r1, #17 800442e: 4802 ldr r0, [pc, #8] @ (8004438 ) 8004430: f002 fbf0 bl 8006c14 #endif } 8004434: bf00 nop 8004436: bd80 pop {r7, pc} 8004438: 200002c0 .word 0x200002c0 0800443c : * * @param _OwnID: EDCAN Device ID * * @retval HAL status */ void EDCAN_FilterInit(){ 800443c: b580 push {r7, lr} 800443e: b08a sub sp, #40 @ 0x28 8004440: af00 add r7, sp, #0 CAN_FilterTypeDef sFilterConfig; //Filter for Own ID sFilterConfig.FilterBank = 0; 8004442: 2300 movs r3, #0 8004444: 617b str r3, [r7, #20] sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; 8004446: 2300 movs r3, #0 8004448: 61bb str r3, [r7, #24] sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; 800444a: 2301 movs r3, #1 800444c: 61fb str r3, [r7, #28] sFilterConfig.FilterIdHigh = 0x0000; 800444e: 2300 movs r3, #0 8004450: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = (uint16_t)(ED_OwnID<<3)|0b100; 8004452: 4b33 ldr r3, [pc, #204] @ (8004520 ) 8004454: 781b ldrb r3, [r3, #0] 8004456: 00db lsls r3, r3, #3 8004458: b29b uxth r3, r3 800445a: f043 0304 orr.w r3, r3, #4 800445e: b29b uxth r3, r3 8004460: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 8004462: 2300 movs r3, #0 8004464: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = (uint16_t)(0xFF<<3)|0b100; 8004466: f240 73fc movw r3, #2044 @ 0x7fc 800446a: 60fb str r3, [r7, #12] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; 800446c: 2300 movs r3, #0 800446e: 613b str r3, [r7, #16] sFilterConfig.FilterActivation = ENABLE; 8004470: 2301 movs r3, #1 8004472: 623b str r3, [r7, #32] #ifdef ED_CAN2 sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 8004474: 2301 movs r3, #1 8004476: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 8004478: 230e movs r3, #14 800447a: 627b str r3, [r7, #36] @ 0x24 sFilterConfig.FilterBank = 14; 800447c: 230e movs r3, #14 800447e: 617b str r3, [r7, #20] #endif if(HAL_CAN_ConfigFilter(&ED_CAN_INSTANCE, &sFilterConfig) != HAL_OK){ 8004480: 463b mov r3, r7 8004482: 4619 mov r1, r3 8004484: 4827 ldr r0, [pc, #156] @ (8004524 ) 8004486: f002 f839 bl 80064fc 800448a: 4603 mov r3, r0 800448c: 2b00 cmp r3, #0 800448e: d001 beq.n 8004494 Error_Handler(); 8004490: f000 fdda bl 8005048 } // Filter for broadcast ID sFilterConfig.FilterBank = 1; 8004494: 2301 movs r3, #1 8004496: 617b str r3, [r7, #20] sFilterConfig.FilterIdHigh = 0x0000; 8004498: 2300 movs r3, #0 800449a: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = (uint16_t)(0xFF<<3)|0b100; 800449c: f240 73fc movw r3, #2044 @ 0x7fc 80044a0: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 80044a2: 2300 movs r3, #0 80044a4: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = (uint16_t)(0xFF<<3)|0b100; 80044a6: f240 73fc movw r3, #2044 @ 0x7fc 80044aa: 60fb str r3, [r7, #12] #ifdef ED_CAN2 sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 80044ac: 2301 movs r3, #1 80044ae: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 80044b0: 230e movs r3, #14 80044b2: 627b str r3, [r7, #36] @ 0x24 sFilterConfig.FilterBank = 15; 80044b4: 230f movs r3, #15 80044b6: 617b str r3, [r7, #20] #endif if(HAL_CAN_ConfigFilter(&ED_CAN_INSTANCE, &sFilterConfig) != HAL_OK) 80044b8: 463b mov r3, r7 80044ba: 4619 mov r1, r3 80044bc: 4819 ldr r0, [pc, #100] @ (8004524 ) 80044be: f002 f81d bl 80064fc 80044c2: 4603 mov r3, r0 80044c4: 2b00 cmp r3, #0 80044c6: d001 beq.n 80044cc { Error_Handler(); 80044c8: f000 fdbe bl 8005048 } // Filter for second ID if(ED_SecondID != 0xFF){ 80044cc: 4b16 ldr r3, [pc, #88] @ (8004528 ) 80044ce: 781b ldrb r3, [r3, #0] 80044d0: 2bff cmp r3, #255 @ 0xff 80044d2: d020 beq.n 8004516 sFilterConfig.FilterBank = 2; 80044d4: 2302 movs r3, #2 80044d6: 617b str r3, [r7, #20] sFilterConfig.FilterIdHigh = 0x0000; 80044d8: 2300 movs r3, #0 80044da: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = (uint16_t)(ED_SecondID<<3)|0b100; 80044dc: 4b12 ldr r3, [pc, #72] @ (8004528 ) 80044de: 781b ldrb r3, [r3, #0] 80044e0: 00db lsls r3, r3, #3 80044e2: b29b uxth r3, r3 80044e4: f043 0304 orr.w r3, r3, #4 80044e8: b29b uxth r3, r3 80044ea: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 80044ec: 2300 movs r3, #0 80044ee: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = (uint16_t)(0xFF<<3)|0b100; 80044f0: f240 73fc movw r3, #2044 @ 0x7fc 80044f4: 60fb str r3, [r7, #12] #ifdef ED_CAN2 sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 80044f6: 2301 movs r3, #1 80044f8: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 80044fa: 230e movs r3, #14 80044fc: 627b str r3, [r7, #36] @ 0x24 sFilterConfig.FilterBank = 16; 80044fe: 2310 movs r3, #16 8004500: 617b str r3, [r7, #20] #endif if(HAL_CAN_ConfigFilter(&ED_CAN_INSTANCE, &sFilterConfig) != HAL_OK) 8004502: 463b mov r3, r7 8004504: 4619 mov r1, r3 8004506: 4807 ldr r0, [pc, #28] @ (8004524 ) 8004508: f001 fff8 bl 80064fc 800450c: 4603 mov r3, r0 800450e: 2b00 cmp r3, #0 8004510: d001 beq.n 8004516 { Error_Handler(); 8004512: f000 fd99 bl 8005048 } } } 8004516: bf00 nop 8004518: 3728 adds r7, #40 @ 0x28 800451a: 46bd mov sp, r7 800451c: bd80 pop {r7, pc} 800451e: bf00 nop 8004520: 200005dd .word 0x200005dd 8004524: 200002c0 .word 0x200002c0 8004528: 20000010 .word 0x20000010 0800452c : * @param DestinationID: Packet Destination ID * @param RegAddr: First register address in sequence * @param *data: pointer to data array to be send * @param len: length of data (1..8) */ void EDCAN_SendPacketRead(uint8_t DestinationID, uint16_t RegAddr, const uint8_t *data, uint8_t len){ 800452c: b580 push {r7, lr} 800452e: b08c sub sp, #48 @ 0x30 8004530: af00 add r7, sp, #0 8004532: 603a str r2, [r7, #0] 8004534: 461a mov r2, r3 8004536: 4603 mov r3, r0 8004538: 71fb strb r3, [r7, #7] 800453a: 460b mov r3, r1 800453c: 80bb strh r3, [r7, #4] 800453e: 4613 mov r3, r2 8004540: 71bb strb r3, [r7, #6] EDCAN_TxFrame_t tx_frame; EDCAN_frameId_t ExtID; //CAN_TxHeaderTypeDef tx_header; //uint32_t tx_mailbox; ExtID.DestinationID = DestinationID; 8004542: 79fb ldrb r3, [r7, #7] 8004544: 733b strb r3, [r7, #12] ExtID.SourceID = ED_OwnID; 8004546: 4b15 ldr r3, [pc, #84] @ (800459c ) 8004548: 781b ldrb r3, [r3, #0] 800454a: 737b strb r3, [r7, #13] ExtID.RegisterAddress = RegAddr; 800454c: 88bb ldrh r3, [r7, #4] 800454e: f3c3 030a ubfx r3, r3, #0, #11 8004552: b29a uxth r2, r3 8004554: 89fb ldrh r3, [r7, #14] 8004556: f362 030a bfi r3, r2, #0, #11 800455a: 81fb strh r3, [r7, #14] ExtID.PacketType = ED_READ; 800455c: 7bfb ldrb r3, [r7, #15] 800455e: 2202 movs r2, #2 8004560: f362 03c4 bfi r3, r2, #3, #2 8004564: 73fb strb r3, [r7, #15] memcpy(&tx_frame.tx_header.ExtId, &ExtID, sizeof(ExtID)); 8004566: 68fb ldr r3, [r7, #12] 8004568: 617b str r3, [r7, #20] tx_frame.tx_header.RTR = CAN_RTR_DATA; 800456a: 2300 movs r3, #0 800456c: 61fb str r3, [r7, #28] tx_frame.tx_header.IDE = CAN_ID_EXT; 800456e: 2304 movs r3, #4 8004570: 61bb str r3, [r7, #24] tx_frame.tx_header.DLC = len; 8004572: 79bb ldrb r3, [r7, #6] 8004574: 623b str r3, [r7, #32] memcpy(&tx_frame.data, data, len); 8004576: 79ba ldrb r2, [r7, #6] 8004578: f107 0310 add.w r3, r7, #16 800457c: 3318 adds r3, #24 800457e: 6839 ldr r1, [r7, #0] 8004580: 4618 mov r0, r3 8004582: f006 fac3 bl 800ab0c //EDCAN_AddTxMessage(&ED_CAN_INSTANCE, &tx_header, data, &tx_mailbox); //Добавление пакета в буфер EDCAN_TxBufferAdd(&tx_frame); 8004586: f107 0310 add.w r3, r7, #16 800458a: 4618 mov r0, r3 800458c: f000 f8be bl 800470c //Также, попытаемся сразу перенести пакет в CAN (если там есть свободное место) //Если свободного места нету, то пакет перенесется в CAN позже по прерыванию освобождения буфера EDCAN_ExchangeTxBuffer(); 8004590: f000 f97c bl 800488c } 8004594: bf00 nop 8004596: 3730 adds r7, #48 @ 0x30 8004598: 46bd mov sp, r7 800459a: bd80 pop {r7, pc} 800459c: 200005dd .word 0x200005dd 080045a0 : /** * @brief EDCAN loop function * Функция для управления буферами, должна быть в while(1) * */ void EDCAN_Loop(){ 80045a0: b580 push {r7, lr} 80045a2: af00 add r7, sp, #0 //Функция переинициализации пока что не используется // if(can_error){ // CAN_ReInit(); // can_error=0; // } if(silentmode_enable){ 80045a4: 4b1f ldr r3, [pc, #124] @ (8004624 ) 80045a6: 681b ldr r3, [r3, #0] 80045a8: 2b00 cmp r3, #0 80045aa: d00f beq.n 80045cc if((HAL_GetTick() - silentmode_start_time) > silentmode_delay){ 80045ac: f001 f978 bl 80058a0 80045b0: 4602 mov r2, r0 80045b2: 4b1d ldr r3, [pc, #116] @ (8004628 ) 80045b4: 681b ldr r3, [r3, #0] 80045b6: 1ad2 subs r2, r2, r3 80045b8: 4b1c ldr r3, [pc, #112] @ (800462c ) 80045ba: 681b ldr r3, [r3, #0] 80045bc: 429a cmp r2, r3 80045be: d905 bls.n 80045cc silentmode_enable = 0; 80045c0: 4b18 ldr r3, [pc, #96] @ (8004624 ) 80045c2: 2200 movs r2, #0 80045c4: 601a str r2, [r3, #0] EDCAN_SetSilentMode(0); 80045c6: 2000 movs r0, #0 80045c8: f000 f87a bl 80046c0 } } //every 2ms exchange buffer // if (HAL_GetTick() > lasttxexchangetime){ if(EDCAN_getTxBufferElementCount()>0){ 80045cc: f000 f8ec bl 80047a8 80045d0: 4603 mov r3, r0 80045d2: 2b00 cmp r3, #0 80045d4: d007 beq.n 80045e6 lasttxexchangetime = HAL_GetTick() + 1; 80045d6: f001 f963 bl 80058a0 80045da: 4603 mov r3, r0 80045dc: 3301 adds r3, #1 80045de: 4a14 ldr r2, [pc, #80] @ (8004630 ) 80045e0: 6013 str r3, [r2, #0] //__disable_irq(); EDCAN_ExchangeTxBuffer(); 80045e2: f000 f953 bl 800488c //__enable_irq(); } // } //every 1s alive packet if ((HAL_GetTick() - lastalivepackettime) > 1000){ 80045e6: f001 f95b bl 80058a0 80045ea: 4602 mov r2, r0 80045ec: 4b11 ldr r3, [pc, #68] @ (8004634 ) 80045ee: 681b ldr r3, [r3, #0] 80045f0: 1ad3 subs r3, r2, r3 80045f2: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 80045f6: d906 bls.n 8004606 lastalivepackettime = HAL_GetTick(); 80045f8: f001 f952 bl 80058a0 80045fc: 4603 mov r3, r0 80045fe: 4a0d ldr r2, [pc, #52] @ (8004634 ) 8004600: 6013 str r3, [r2, #0] EDCAN_SendAlivePacket(); 8004602: f000 f819 bl 8004638 } //exchange buffer // if (HAL_GetTick() > lastrxexchangetime){ if((EDCAN_getRxBufferElementCount()>0)&&(EDCAN_getTxBufferElementCount()<(BUFFER_SIZE*3/4))){ 8004606: f000 fa1f bl 8004a48 800460a: 4603 mov r3, r0 800460c: 2b00 cmp r3, #0 800460e: d006 beq.n 800461e 8004610: f000 f8ca bl 80047a8 8004614: 4603 mov r3, r0 8004616: 2bbf cmp r3, #191 @ 0xbf 8004618: d801 bhi.n 800461e // lastrxexchangetime = HAL_GetTick() + 1; EDCAN_ExchangeRxBuffer(); 800461a: f000 fa21 bl 8004a60 } // } } 800461e: bf00 nop 8004620: bd80 pop {r7, pc} 8004622: bf00 nop 8004624: 2000061c .word 0x2000061c 8004628: 20000614 .word 0x20000614 800462c: 20000618 .word 0x20000618 8004630: 20000620 .word 0x20000620 8004634: 20000624 .word 0x20000624 08004638 : void EDCAN_SendAlivePacket(){ 8004638: b580 push {r7, lr} 800463a: b082 sub sp, #8 800463c: af00 add r7, sp, #0 uint8_t data[1]; uint8_t DestinationID = 0x00; 800463e: 2300 movs r3, #0 8004640: 71fb strb r3, [r7, #7] data[0] = EDCAN_GetOwnRegisterValue(EDCAN_REG_SYS_STATUS); 8004642: 2000 movs r0, #0 8004644: f000 fb14 bl 8004c70 8004648: 4603 mov r3, r0 800464a: 713b strb r3, [r7, #4] EDCAN_SendPacketRead(DestinationID, EDCAN_REG_SYS_STATUS, data, 1); 800464c: 1d3a adds r2, r7, #4 800464e: 79f8 ldrb r0, [r7, #7] 8004650: 2301 movs r3, #1 8004652: 2100 movs r1, #0 8004654: f7ff ff6a bl 800452c } 8004658: bf00 nop 800465a: 3708 adds r7, #8 800465c: 46bd mov sp, r7 800465e: bd80 pop {r7, pc} 08004660 : //функция установки таймера для входа в Silent режим //По истечении времени time выход из режима silent //если time = 0, выход из режима silent и сброс таймера void EDCAN_EnterSilentMode(uint8_t time){ 8004660: b580 push {r7, lr} 8004662: b082 sub sp, #8 8004664: af00 add r7, sp, #0 8004666: 4603 mov r3, r0 8004668: 71fb strb r3, [r7, #7] if(time==0){ 800466a: 79fb ldrb r3, [r7, #7] 800466c: 2b00 cmp r3, #0 800466e: d10b bne.n 8004688 EDCAN_SetSilentMode(0); 8004670: 2000 movs r0, #0 8004672: f000 f825 bl 80046c0 silentmode_start_time = HAL_GetTick(); 8004676: f001 f913 bl 80058a0 800467a: 4603 mov r3, r0 800467c: 4a0d ldr r2, [pc, #52] @ (80046b4 ) 800467e: 6013 str r3, [r2, #0] silentmode_enable = 0; 8004680: 4b0d ldr r3, [pc, #52] @ (80046b8 ) 8004682: 2200 movs r2, #0 8004684: 601a str r2, [r3, #0] EDCAN_SetSilentMode(1); silentmode_delay = ((uint32_t)time * 1000); silentmode_start_time = HAL_GetTick(); silentmode_enable = 1; } } 8004686: e011 b.n 80046ac EDCAN_SetSilentMode(1); 8004688: 2001 movs r0, #1 800468a: f000 f819 bl 80046c0 silentmode_delay = ((uint32_t)time * 1000); 800468e: 79fb ldrb r3, [r7, #7] 8004690: f44f 727a mov.w r2, #1000 @ 0x3e8 8004694: fb02 f303 mul.w r3, r2, r3 8004698: 4a08 ldr r2, [pc, #32] @ (80046bc ) 800469a: 6013 str r3, [r2, #0] silentmode_start_time = HAL_GetTick(); 800469c: f001 f900 bl 80058a0 80046a0: 4603 mov r3, r0 80046a2: 4a04 ldr r2, [pc, #16] @ (80046b4 ) 80046a4: 6013 str r3, [r2, #0] silentmode_enable = 1; 80046a6: 4b04 ldr r3, [pc, #16] @ (80046b8 ) 80046a8: 2201 movs r2, #1 80046aa: 601a str r2, [r3, #0] } 80046ac: bf00 nop 80046ae: 3708 adds r7, #8 80046b0: 46bd mov sp, r7 80046b2: bd80 pop {r7, pc} 80046b4: 20000614 .word 0x20000614 80046b8: 2000061c .word 0x2000061c 80046bc: 20000618 .word 0x20000618 080046c0 : //Функция входа в Silent Режим void EDCAN_SetSilentMode(uint8_t state){ 80046c0: b580 push {r7, lr} 80046c2: b082 sub sp, #8 80046c4: af00 add r7, sp, #0 80046c6: 4603 mov r3, r0 80046c8: 71fb strb r3, [r7, #7] HAL_CAN_Stop(&ED_CAN_INSTANCE); 80046ca: 480f ldr r0, [pc, #60] @ (8004708 ) 80046cc: f002 f83a bl 8006744 if(state){ 80046d0: 79fb ldrb r3, [r7, #7] 80046d2: 2b00 cmp r3, #0 80046d4: d008 beq.n 80046e8 ED_CAN_INSTANCE.Instance->BTR |= CAN_MODE_SILENT; 80046d6: 4b0c ldr r3, [pc, #48] @ (8004708 ) 80046d8: 681b ldr r3, [r3, #0] 80046da: 69da ldr r2, [r3, #28] 80046dc: 4b0a ldr r3, [pc, #40] @ (8004708 ) 80046de: 681b ldr r3, [r3, #0] 80046e0: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 80046e4: 61da str r2, [r3, #28] 80046e6: e007 b.n 80046f8 }else{ ED_CAN_INSTANCE.Instance->BTR &= ~CAN_MODE_SILENT; 80046e8: 4b07 ldr r3, [pc, #28] @ (8004708 ) 80046ea: 681b ldr r3, [r3, #0] 80046ec: 69da ldr r2, [r3, #28] 80046ee: 4b06 ldr r3, [pc, #24] @ (8004708 ) 80046f0: 681b ldr r3, [r3, #0] 80046f2: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 80046f6: 61da str r2, [r3, #28] } HAL_CAN_Start(&ED_CAN_INSTANCE); 80046f8: 4803 ldr r0, [pc, #12] @ (8004708 ) 80046fa: f001 ffdf bl 80066bc } 80046fe: bf00 nop 8004700: 3708 adds r7, #8 8004702: 46bd mov sp, r7 8004704: bd80 pop {r7, pc} 8004706: bf00 nop 8004708: 200002c0 .word 0x200002c0 0800470c : TxCircularBuffer_t txBuffer = { .head = 0, .tail = 0, .count = 0, .busy = 0 }; RxCircularBuffer_t rxBuffer = { .head = 0, .tail = 0, .count = 0, .busy = 0 }; // Добавление элемента в буфер void EDCAN_TxBufferAdd(EDCAN_TxFrame_t *frame) { 800470c: b580 push {r7, lr} 800470e: b082 sub sp, #8 8004710: af00 add r7, sp, #0 8004712: 6078 str r0, [r7, #4] __ASM volatile ("cpsid i" : : : "memory"); 8004714: b672 cpsid i } 8004716: bf00 nop __disable_irq(); memcpy(&txBuffer.buffer[txBuffer.head], frame, sizeof(EDCAN_TxFrame_t)); 8004718: 4b22 ldr r3, [pc, #136] @ (80047a4 ) 800471a: f503 5300 add.w r3, r3, #8192 @ 0x2000 800471e: 881b ldrh r3, [r3, #0] 8004720: 015b lsls r3, r3, #5 8004722: 4a20 ldr r2, [pc, #128] @ (80047a4 ) 8004724: 4413 add r3, r2 8004726: 2220 movs r2, #32 8004728: 6879 ldr r1, [r7, #4] 800472a: 4618 mov r0, r3 800472c: f006 f9ee bl 800ab0c txBuffer.head = (txBuffer.head + 1) % BUFFER_SIZE; 8004730: 4b1c ldr r3, [pc, #112] @ (80047a4 ) 8004732: f503 5300 add.w r3, r3, #8192 @ 0x2000 8004736: 881b ldrh r3, [r3, #0] 8004738: 3301 adds r3, #1 800473a: 425a negs r2, r3 800473c: b2db uxtb r3, r3 800473e: b2d2 uxtb r2, r2 8004740: bf58 it pl 8004742: 4253 negpl r3, r2 8004744: b29a uxth r2, r3 8004746: 4b17 ldr r3, [pc, #92] @ (80047a4 ) 8004748: f503 5300 add.w r3, r3, #8192 @ 0x2000 800474c: 801a strh r2, [r3, #0] if (txBuffer.count == BUFFER_SIZE) { 800474e: 4b15 ldr r3, [pc, #84] @ (80047a4 ) 8004750: f503 5300 add.w r3, r3, #8192 @ 0x2000 8004754: f9b3 3004 ldrsh.w r3, [r3, #4] 8004758: f5b3 7f80 cmp.w r3, #256 @ 0x100 800475c: d10f bne.n 800477e txBuffer.tail = (txBuffer.tail + 1) % BUFFER_SIZE; // Перезапись старых данных 800475e: 4b11 ldr r3, [pc, #68] @ (80047a4 ) 8004760: f503 5300 add.w r3, r3, #8192 @ 0x2000 8004764: 885b ldrh r3, [r3, #2] 8004766: 3301 adds r3, #1 8004768: 425a negs r2, r3 800476a: b2db uxtb r3, r3 800476c: b2d2 uxtb r2, r2 800476e: bf58 it pl 8004770: 4253 negpl r3, r2 8004772: b29a uxth r2, r3 8004774: 4b0b ldr r3, [pc, #44] @ (80047a4 ) 8004776: f503 5300 add.w r3, r3, #8192 @ 0x2000 800477a: 805a strh r2, [r3, #2] 800477c: e00c b.n 8004798 } else { txBuffer.count++; 800477e: 4b09 ldr r3, [pc, #36] @ (80047a4 ) 8004780: f503 5300 add.w r3, r3, #8192 @ 0x2000 8004784: f9b3 3004 ldrsh.w r3, [r3, #4] 8004788: b29b uxth r3, r3 800478a: 3301 adds r3, #1 800478c: b29b uxth r3, r3 800478e: b21a sxth r2, r3 8004790: 4b04 ldr r3, [pc, #16] @ (80047a4 ) 8004792: f503 5300 add.w r3, r3, #8192 @ 0x2000 8004796: 809a strh r2, [r3, #4] __ASM volatile ("cpsie i" : : : "memory"); 8004798: b662 cpsie i } 800479a: bf00 nop } __enable_irq(); } 800479c: bf00 nop 800479e: 3708 adds r7, #8 80047a0: 46bd mov sp, r7 80047a2: bd80 pop {r7, pc} 80047a4: 20000628 .word 0x20000628 080047a8 : //Количество элементов в буфере uint16_t EDCAN_getTxBufferElementCount() { 80047a8: b480 push {r7} 80047aa: af00 add r7, sp, #0 return txBuffer.count; 80047ac: 4b04 ldr r3, [pc, #16] @ (80047c0 ) 80047ae: f503 5300 add.w r3, r3, #8192 @ 0x2000 80047b2: f9b3 3004 ldrsh.w r3, [r3, #4] 80047b6: b29b uxth r3, r3 } 80047b8: 4618 mov r0, r3 80047ba: 46bd mov sp, r7 80047bc: bc80 pop {r7} 80047be: 4770 bx lr 80047c0: 20000628 .word 0x20000628 080047c4 : // функция для получения первого элемента без удаления его из буфера bool EDCAN_TxBufferPeekFirst(EDCAN_TxFrame_t *frame) { 80047c4: b580 push {r7, lr} 80047c6: b082 sub sp, #8 80047c8: af00 add r7, sp, #0 80047ca: 6078 str r0, [r7, #4] if (txBuffer.count > 0) { 80047cc: 4b0c ldr r3, [pc, #48] @ (8004800 ) 80047ce: f503 5300 add.w r3, r3, #8192 @ 0x2000 80047d2: f9b3 3004 ldrsh.w r3, [r3, #4] 80047d6: 2b00 cmp r3, #0 80047d8: dd0d ble.n 80047f6 memcpy(frame, &txBuffer.buffer[txBuffer.tail], sizeof(EDCAN_TxFrame_t)); 80047da: 4b09 ldr r3, [pc, #36] @ (8004800 ) 80047dc: f503 5300 add.w r3, r3, #8192 @ 0x2000 80047e0: 885b ldrh r3, [r3, #2] 80047e2: 015b lsls r3, r3, #5 80047e4: 4a06 ldr r2, [pc, #24] @ (8004800 ) 80047e6: 4413 add r3, r2 80047e8: 2220 movs r2, #32 80047ea: 4619 mov r1, r3 80047ec: 6878 ldr r0, [r7, #4] 80047ee: f006 f98d bl 800ab0c return true; 80047f2: 2301 movs r3, #1 80047f4: e000 b.n 80047f8 } else { // Буфер пуст, можно добавить обработку ошибки return false; 80047f6: 2300 movs r3, #0 } } 80047f8: 4618 mov r0, r3 80047fa: 3708 adds r7, #8 80047fc: 46bd mov sp, r7 80047fe: bd80 pop {r7, pc} 8004800: 20000628 .word 0x20000628 08004804 : // функция для удаления первого элемента из буфера bool EDCAN_TxBufferRemoveFirst() { 8004804: b480 push {r7} 8004806: af00 add r7, sp, #0 if (txBuffer.count > 0) { 8004808: 4b1f ldr r3, [pc, #124] @ (8004888 ) 800480a: f503 5300 add.w r3, r3, #8192 @ 0x2000 800480e: f9b3 3004 ldrsh.w r3, [r3, #4] 8004812: 2b00 cmp r3, #0 8004814: dd33 ble.n 800487e txBuffer.tail = (txBuffer.tail + 1) % BUFFER_SIZE; 8004816: 4b1c ldr r3, [pc, #112] @ (8004888 ) 8004818: f503 5300 add.w r3, r3, #8192 @ 0x2000 800481c: 885b ldrh r3, [r3, #2] 800481e: 3301 adds r3, #1 8004820: 425a negs r2, r3 8004822: b2db uxtb r3, r3 8004824: b2d2 uxtb r2, r2 8004826: bf58 it pl 8004828: 4253 negpl r3, r2 800482a: b29a uxth r2, r3 800482c: 4b16 ldr r3, [pc, #88] @ (8004888 ) 800482e: f503 5300 add.w r3, r3, #8192 @ 0x2000 8004832: 805a strh r2, [r3, #2] txBuffer.count--; 8004834: 4b14 ldr r3, [pc, #80] @ (8004888 ) 8004836: f503 5300 add.w r3, r3, #8192 @ 0x2000 800483a: f9b3 3004 ldrsh.w r3, [r3, #4] 800483e: b29b uxth r3, r3 8004840: 3b01 subs r3, #1 8004842: b29b uxth r3, r3 8004844: b21a sxth r2, r3 8004846: 4b10 ldr r3, [pc, #64] @ (8004888 ) 8004848: f503 5300 add.w r3, r3, #8192 @ 0x2000 800484c: 809a strh r2, [r3, #4] if(txBuffer.count < 0){ 800484e: 4b0e ldr r3, [pc, #56] @ (8004888 ) 8004850: f503 5300 add.w r3, r3, #8192 @ 0x2000 8004854: f9b3 3004 ldrsh.w r3, [r3, #4] 8004858: 2b00 cmp r3, #0 800485a: da0e bge.n 800487a //printf("hueta\n"); txBuffer.count = 0; 800485c: 4b0a ldr r3, [pc, #40] @ (8004888 ) 800485e: f503 5300 add.w r3, r3, #8192 @ 0x2000 8004862: 2200 movs r2, #0 8004864: 809a strh r2, [r3, #4] txBuffer.tail = 0; 8004866: 4b08 ldr r3, [pc, #32] @ (8004888 ) 8004868: f503 5300 add.w r3, r3, #8192 @ 0x2000 800486c: 2200 movs r2, #0 800486e: 805a strh r2, [r3, #2] txBuffer.head = 0; 8004870: 4b05 ldr r3, [pc, #20] @ (8004888 ) 8004872: f503 5300 add.w r3, r3, #8192 @ 0x2000 8004876: 2200 movs r2, #0 8004878: 801a strh r2, [r3, #0] } return true; 800487a: 2301 movs r3, #1 800487c: e000 b.n 8004880 } else { // Буфер пуст, можно добавить обработку ошибки return false; 800487e: 2300 movs r3, #0 } } 8004880: 4618 mov r0, r3 8004882: 46bd mov sp, r7 8004884: bc80 pop {r7} 8004886: 4770 bx lr 8004888: 20000628 .word 0x20000628 0800488c : //Функция для передачи данных из буфера в mailbox CAN шины void EDCAN_ExchangeTxBuffer(){ 800488c: b580 push {r7, lr} 800488e: b08a sub sp, #40 @ 0x28 8004890: af00 add r7, sp, #0 EDCAN_TxFrame_t TxFrame; uint32_t tx_mailbox; HAL_StatusTypeDef CAN_result; //если буфер занят, то выходим нах if (txBuffer.busy) return; 8004892: 4b26 ldr r3, [pc, #152] @ (800492c ) 8004894: f503 5300 add.w r3, r3, #8192 @ 0x2000 8004898: 799b ldrb r3, [r3, #6] 800489a: 2b00 cmp r3, #0 800489c: d142 bne.n 8004924 txBuffer.busy = 1; 800489e: 4b23 ldr r3, [pc, #140] @ (800492c ) 80048a0: f503 5300 add.w r3, r3, #8192 @ 0x2000 80048a4: 2201 movs r2, #1 80048a6: 719a strb r2, [r3, #6] //Если есть свободные Mailbox if(HAL_CAN_GetTxMailboxesFreeLevel(&ED_CAN_INSTANCE) > 0){ 80048a8: 4821 ldr r0, [pc, #132] @ (8004930 ) 80048aa: f002 f86e bl 800698a 80048ae: 4603 mov r3, r0 80048b0: 2b00 cmp r3, #0 80048b2: d031 beq.n 8004918 //Если есть элементы в буфере, извлечь первый элемент буфера if(EDCAN_TxBufferPeekFirst(&TxFrame)) { 80048b4: 1d3b adds r3, r7, #4 80048b6: 4618 mov r0, r3 80048b8: f7ff ff84 bl 80047c4 80048bc: 4603 mov r3, r0 80048be: 2b00 cmp r3, #0 80048c0: d02a beq.n 8004918 /* отправка сообщения */ CAN_result = HAL_CAN_AddTxMessage(&ED_CAN_INSTANCE, &TxFrame.tx_header, TxFrame.data, &tx_mailbox); 80048c2: 4638 mov r0, r7 80048c4: 1d3b adds r3, r7, #4 80048c6: f103 0218 add.w r2, r3, #24 80048ca: 1d39 adds r1, r7, #4 80048cc: 4603 mov r3, r0 80048ce: 4818 ldr r0, [pc, #96] @ (8004930 ) 80048d0: f001 ff81 bl 80067d6 80048d4: 4603 mov r3, r0 80048d6: f887 3027 strb.w r3, [r7, #39] @ 0x27 /* если отправка удалась, выход */ if(CAN_result == HAL_OK) { 80048da: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 80048de: 2b00 cmp r3, #0 80048e0: d102 bne.n 80048e8 //Удаление элемента буфера в случае успешной передачи EDCAN_TxBufferRemoveFirst(); 80048e2: f7ff ff8f bl 8004804 80048e6: e017 b.n 8004918 //printf("tx ok\n"); }else if(CAN_result == HAL_ERROR) { 80048e8: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 80048ec: 2b01 cmp r3, #1 80048ee: d113 bne.n 8004918 /* если ошибка, обработка ошибки */ if(ED_CAN_INSTANCE.ErrorCode & HAL_CAN_ERROR_NOT_INITIALIZED) { 80048f0: 4b0f ldr r3, [pc, #60] @ (8004930 ) 80048f2: 6a5b ldr r3, [r3, #36] @ 0x24 80048f4: f403 2380 and.w r3, r3, #262144 @ 0x40000 80048f8: 2b00 cmp r3, #0 80048fa: d004 beq.n 8004906 CAN_ReInit(); //CAN не инициализирован, переинициализация 80048fc: f7ff fd8a bl 8004414 printf("CAN Reinit\n"); 8004900: 480c ldr r0, [pc, #48] @ (8004934 ) 8004902: f005 fbdb bl 800a0bc } //if(ED_CAN_INSTANCE.ErrorCode & HAL_CAN_ERROR_PARAM) printf("tx full\n"); printf("CAN.ErrorCode = %d\n",(int)ED_CAN_INSTANCE.ErrorCode); 8004906: 4b0a ldr r3, [pc, #40] @ (8004930 ) 8004908: 6a5b ldr r3, [r3, #36] @ 0x24 800490a: 4619 mov r1, r3 800490c: 480a ldr r0, [pc, #40] @ (8004938 ) 800490e: f005 fb6d bl 8009fec ED_CAN_INSTANCE.ErrorCode = 0; //Clear errors 8004912: 4b07 ldr r3, [pc, #28] @ (8004930 ) 8004914: 2200 movs r2, #0 8004916: 625a str r2, [r3, #36] @ 0x24 } } } txBuffer.busy = 0; 8004918: 4b04 ldr r3, [pc, #16] @ (800492c ) 800491a: f503 5300 add.w r3, r3, #8192 @ 0x2000 800491e: 2200 movs r2, #0 8004920: 719a strb r2, [r3, #6] 8004922: e000 b.n 8004926 if (txBuffer.busy) return; 8004924: bf00 nop } 8004926: 3728 adds r7, #40 @ 0x28 8004928: 46bd mov sp, r7 800492a: bd80 pop {r7, pc} 800492c: 20000628 .word 0x20000628 8004930: 200002c0 .word 0x200002c0 8004934: 0800def0 .word 0x0800def0 8004938: 0800defc .word 0x0800defc 0800493c : // return false; // } //} // Функции работы с Rx буфером void EDCAN_RxBufferAdd(EDCAN_RxFrame_t *frame) { 800493c: b580 push {r7, lr} 800493e: b082 sub sp, #8 8004940: af00 add r7, sp, #0 8004942: 6078 str r0, [r7, #4] // Исполнение из прерывания memcpy(&rxBuffer.buffer[rxBuffer.head], frame, sizeof(EDCAN_RxFrame_t)); 8004944: 4b1f ldr r3, [pc, #124] @ (80049c4 ) 8004946: f8b3 3d00 ldrh.w r3, [r3, #3328] @ 0xd00 800494a: 461a mov r2, r3 800494c: 4613 mov r3, r2 800494e: 005b lsls r3, r3, #1 8004950: 4413 add r3, r2 8004952: 009b lsls r3, r3, #2 8004954: 4413 add r3, r2 8004956: 4a1b ldr r2, [pc, #108] @ (80049c4 ) 8004958: 4413 add r3, r2 800495a: 220d movs r2, #13 800495c: 6879 ldr r1, [r7, #4] 800495e: 4618 mov r0, r3 8004960: f006 f8d4 bl 800ab0c rxBuffer.head = (rxBuffer.head + 1) % BUFFER_SIZE; 8004964: 4b17 ldr r3, [pc, #92] @ (80049c4 ) 8004966: f8b3 3d00 ldrh.w r3, [r3, #3328] @ 0xd00 800496a: 3301 adds r3, #1 800496c: 425a negs r2, r3 800496e: b2db uxtb r3, r3 8004970: b2d2 uxtb r2, r2 8004972: bf58 it pl 8004974: 4253 negpl r3, r2 8004976: b29a uxth r2, r3 8004978: 4b12 ldr r3, [pc, #72] @ (80049c4 ) 800497a: f8a3 2d00 strh.w r2, [r3, #3328] @ 0xd00 if (rxBuffer.count == BUFFER_SIZE) { 800497e: 4b11 ldr r3, [pc, #68] @ (80049c4 ) 8004980: f9b3 3d04 ldrsh.w r3, [r3, #3332] @ 0xd04 8004984: f5b3 7f80 cmp.w r3, #256 @ 0x100 8004988: d10d bne.n 80049a6 rxBuffer.tail = (rxBuffer.tail + 1) % BUFFER_SIZE; // Перезапись старых данных 800498a: 4b0e ldr r3, [pc, #56] @ (80049c4 ) 800498c: f8b3 3d02 ldrh.w r3, [r3, #3330] @ 0xd02 8004990: 3301 adds r3, #1 8004992: 425a negs r2, r3 8004994: b2db uxtb r3, r3 8004996: b2d2 uxtb r2, r2 8004998: bf58 it pl 800499a: 4253 negpl r3, r2 800499c: b29a uxth r2, r3 800499e: 4b09 ldr r3, [pc, #36] @ (80049c4 ) 80049a0: f8a3 2d02 strh.w r2, [r3, #3330] @ 0xd02 } else { rxBuffer.count++; } } 80049a4: e009 b.n 80049ba rxBuffer.count++; 80049a6: 4b07 ldr r3, [pc, #28] @ (80049c4 ) 80049a8: f9b3 3d04 ldrsh.w r3, [r3, #3332] @ 0xd04 80049ac: b29b uxth r3, r3 80049ae: 3301 adds r3, #1 80049b0: b29b uxth r3, r3 80049b2: b21a sxth r2, r3 80049b4: 4b03 ldr r3, [pc, #12] @ (80049c4 ) 80049b6: f8a3 2d04 strh.w r2, [r3, #3332] @ 0xd04 } 80049ba: bf00 nop 80049bc: 3708 adds r7, #8 80049be: 46bd mov sp, r7 80049c0: bd80 pop {r7, pc} 80049c2: bf00 nop 80049c4: 20002630 .word 0x20002630 080049c8 : //Извлечь и удалить первый элемент буфера bool EDCAN_RxBufferGet(EDCAN_RxFrame_t *frame) { 80049c8: b580 push {r7, lr} 80049ca: b082 sub sp, #8 80049cc: af00 add r7, sp, #0 80049ce: 6078 str r0, [r7, #4] __ASM volatile ("cpsid i" : : : "memory"); 80049d0: b672 cpsid i } 80049d2: bf00 nop //LOCKED function __disable_irq(); if (rxBuffer.count > 0) { 80049d4: 4b1b ldr r3, [pc, #108] @ (8004a44 ) 80049d6: f9b3 3d04 ldrsh.w r3, [r3, #3332] @ 0xd04 80049da: 2b00 cmp r3, #0 80049dc: dd2a ble.n 8004a34 memcpy(frame, &rxBuffer.buffer[rxBuffer.tail], sizeof(EDCAN_RxFrame_t)); 80049de: 4b19 ldr r3, [pc, #100] @ (8004a44 ) 80049e0: f8b3 3d02 ldrh.w r3, [r3, #3330] @ 0xd02 80049e4: 461a mov r2, r3 80049e6: 4613 mov r3, r2 80049e8: 005b lsls r3, r3, #1 80049ea: 4413 add r3, r2 80049ec: 009b lsls r3, r3, #2 80049ee: 4413 add r3, r2 80049f0: 4a14 ldr r2, [pc, #80] @ (8004a44 ) 80049f2: 4413 add r3, r2 80049f4: 220d movs r2, #13 80049f6: 4619 mov r1, r3 80049f8: 6878 ldr r0, [r7, #4] 80049fa: f006 f887 bl 800ab0c rxBuffer.tail = (rxBuffer.tail + 1) % BUFFER_SIZE; 80049fe: 4b11 ldr r3, [pc, #68] @ (8004a44 ) 8004a00: f8b3 3d02 ldrh.w r3, [r3, #3330] @ 0xd02 8004a04: 3301 adds r3, #1 8004a06: 425a negs r2, r3 8004a08: b2db uxtb r3, r3 8004a0a: b2d2 uxtb r2, r2 8004a0c: bf58 it pl 8004a0e: 4253 negpl r3, r2 8004a10: b29a uxth r2, r3 8004a12: 4b0c ldr r3, [pc, #48] @ (8004a44 ) 8004a14: f8a3 2d02 strh.w r2, [r3, #3330] @ 0xd02 rxBuffer.count--; 8004a18: 4b0a ldr r3, [pc, #40] @ (8004a44 ) 8004a1a: f9b3 3d04 ldrsh.w r3, [r3, #3332] @ 0xd04 8004a1e: b29b uxth r3, r3 8004a20: 3b01 subs r3, #1 8004a22: b29b uxth r3, r3 8004a24: b21a sxth r2, r3 8004a26: 4b07 ldr r3, [pc, #28] @ (8004a44 ) 8004a28: f8a3 2d04 strh.w r2, [r3, #3332] @ 0xd04 __ASM volatile ("cpsie i" : : : "memory"); 8004a2c: b662 cpsie i } 8004a2e: bf00 nop __enable_irq(); return true; 8004a30: 2301 movs r3, #1 8004a32: e002 b.n 8004a3a __ASM volatile ("cpsie i" : : : "memory"); 8004a34: b662 cpsie i } 8004a36: bf00 nop } else { // Буфер пуст, можно добавить обработку ошибки __enable_irq(); return false; 8004a38: 2300 movs r3, #0 } } 8004a3a: 4618 mov r0, r3 8004a3c: 3708 adds r7, #8 8004a3e: 46bd mov sp, r7 8004a40: bd80 pop {r7, pc} 8004a42: bf00 nop 8004a44: 20002630 .word 0x20002630 08004a48 : //Количество элементов в буфере uint16_t EDCAN_getRxBufferElementCount() { 8004a48: b480 push {r7} 8004a4a: af00 add r7, sp, #0 return rxBuffer.count; 8004a4c: 4b03 ldr r3, [pc, #12] @ (8004a5c ) 8004a4e: f9b3 3d04 ldrsh.w r3, [r3, #3332] @ 0xd04 8004a52: b29b uxth r3, r3 } 8004a54: 4618 mov r0, r3 8004a56: 46bd mov sp, r7 8004a58: bc80 pop {r7} 8004a5a: 4770 bx lr 8004a5c: 20002630 .word 0x20002630 08004a60 : //Функция для обработки входящих пакетов из буфера void EDCAN_ExchangeRxBuffer(){ 8004a60: b590 push {r4, r7, lr} 8004a62: b087 sub sp, #28 8004a64: af02 add r7, sp, #8 EDCAN_RxFrame_t Rxframe; if (EDCAN_RxBufferGet(&Rxframe)){ 8004a66: 463b mov r3, r7 8004a68: 4618 mov r0, r3 8004a6a: f7ff ffad bl 80049c8 8004a6e: 4603 mov r3, r0 8004a70: 2b00 cmp r3, #0 8004a72: d039 beq.n 8004ae8 if(Rxframe.ExtID.PacketType == ED_WRITE){ 8004a74: 78fb ldrb r3, [r7, #3] 8004a76: f003 0318 and.w r3, r3, #24 8004a7a: b2db uxtb r3, r3 8004a7c: 2b00 cmp r3, #0 8004a7e: d10e bne.n 8004a9e EDCAN_WriteHandler(Rxframe.ExtID.SourceID, Rxframe.ExtID.DestinationID, Rxframe.ExtID.RegisterAddress, Rxframe.data, Rxframe.DLC); 8004a80: 7878 ldrb r0, [r7, #1] 8004a82: 7839 ldrb r1, [r7, #0] 8004a84: 887b ldrh r3, [r7, #2] 8004a86: f3c3 030a ubfx r3, r3, #0, #11 8004a8a: b29b uxth r3, r3 8004a8c: 461c mov r4, r3 8004a8e: 7b3b ldrb r3, [r7, #12] 8004a90: 463a mov r2, r7 8004a92: 3204 adds r2, #4 8004a94: 9300 str r3, [sp, #0] 8004a96: 4613 mov r3, r2 8004a98: 4622 mov r2, r4 8004a9a: f000 f829 bl 8004af0 } if(Rxframe.ExtID.PacketType == ED_READREQ){ 8004a9e: 78fb ldrb r3, [r7, #3] 8004aa0: f003 0318 and.w r3, r3, #24 8004aa4: b2db uxtb r3, r3 8004aa6: 2b08 cmp r3, #8 8004aa8: d109 bne.n 8004abe EDCAN_ReadRequestHandler(Rxframe.ExtID.SourceID, Rxframe.ExtID.DestinationID, Rxframe.ExtID.RegisterAddress, Rxframe.data[0]); 8004aaa: 7878 ldrb r0, [r7, #1] 8004aac: 7839 ldrb r1, [r7, #0] 8004aae: 887b ldrh r3, [r7, #2] 8004ab0: f3c3 030a ubfx r3, r3, #0, #11 8004ab4: b29b uxth r3, r3 8004ab6: 461a mov r2, r3 8004ab8: 793b ldrb r3, [r7, #4] 8004aba: f000 f8f0 bl 8004c9e } if(Rxframe.ExtID.PacketType == ED_READ){ 8004abe: 78fb ldrb r3, [r7, #3] 8004ac0: f003 0318 and.w r3, r3, #24 8004ac4: b2db uxtb r3, r3 8004ac6: 2b10 cmp r3, #16 8004ac8: d10e bne.n 8004ae8 EDCAN_ReadHandler(Rxframe.ExtID.SourceID, Rxframe.ExtID.DestinationID, Rxframe.ExtID.RegisterAddress, Rxframe.data, Rxframe.DLC); 8004aca: 7878 ldrb r0, [r7, #1] 8004acc: 7839 ldrb r1, [r7, #0] 8004ace: 887b ldrh r3, [r7, #2] 8004ad0: f3c3 030a ubfx r3, r3, #0, #11 8004ad4: b29b uxth r3, r3 8004ad6: 461c mov r4, r3 8004ad8: 7b3b ldrb r3, [r7, #12] 8004ada: 463a mov r2, r7 8004adc: 3204 adds r2, #4 8004ade: 9300 str r3, [sp, #0] 8004ae0: 4613 mov r3, r2 8004ae2: 4622 mov r2, r4 8004ae4: f7fe fd9e bl 8003624 } } } 8004ae8: bf00 nop 8004aea: 3714 adds r7, #20 8004aec: 46bd mov sp, r7 8004aee: bd90 pop {r4, r7, pc} 08004af0 : * DestinationID: Packet Destination ID * Addr: First register address in sequence * *data: pointer for data array * len: length of data (1..255) */ void EDCAN_WriteHandler(uint8_t SourceID, uint8_t DestinationID, uint16_t Addr, uint8_t *data, uint8_t len){ 8004af0: b580 push {r7, lr} 8004af2: b084 sub sp, #16 8004af4: af00 add r7, sp, #0 8004af6: 603b str r3, [r7, #0] 8004af8: 4603 mov r3, r0 8004afa: 71fb strb r3, [r7, #7] 8004afc: 460b mov r3, r1 8004afe: 71bb strb r3, [r7, #6] 8004b00: 4613 mov r3, r2 8004b02: 80bb strh r3, [r7, #4] // printf("Destination ID = %d\n", DestinationID); // printf("Address = %d\n", Addr); // printf("Len = %d\n", len); // printf("\n"); for (uint16_t AddrOffset = 0; AddrOffset < len; AddrOffset++){ //по очереди перебираем все полученные регистры через Handler 8004b04: 2300 movs r3, #0 8004b06: 81fb strh r3, [r7, #14] 8004b08: e01e b.n 8004b48 // printf ("register[%d] = %d\n", Addr+AddrOffset, data[AddrOffset]); if((Addr+AddrOffset)>=256){ 8004b0a: 88ba ldrh r2, [r7, #4] 8004b0c: 89fb ldrh r3, [r7, #14] 8004b0e: 4413 add r3, r2 8004b10: 2bff cmp r3, #255 @ 0xff 8004b12: dd0b ble.n 8004b2c EDCAN_WriteUserRegister(Addr+AddrOffset, data[AddrOffset]); 8004b14: 88ba ldrh r2, [r7, #4] 8004b16: 89fb ldrh r3, [r7, #14] 8004b18: 4413 add r3, r2 8004b1a: b298 uxth r0, r3 8004b1c: 89fb ldrh r3, [r7, #14] 8004b1e: 683a ldr r2, [r7, #0] 8004b20: 4413 add r3, r2 8004b22: 781b ldrb r3, [r3, #0] 8004b24: 4619 mov r1, r3 8004b26: f7fe fd99 bl 800365c 8004b2a: e00a b.n 8004b42 }else{ EDCAN_WriteSystemRegister(Addr+AddrOffset, data[AddrOffset]); 8004b2c: 88ba ldrh r2, [r7, #4] 8004b2e: 89fb ldrh r3, [r7, #14] 8004b30: 4413 add r3, r2 8004b32: b298 uxth r0, r3 8004b34: 89fb ldrh r3, [r7, #14] 8004b36: 683a ldr r2, [r7, #0] 8004b38: 4413 add r3, r2 8004b3a: 781b ldrb r3, [r3, #0] 8004b3c: 4619 mov r1, r3 8004b3e: f000 f80d bl 8004b5c for (uint16_t AddrOffset = 0; AddrOffset < len; AddrOffset++){ //по очереди перебираем все полученные регистры через Handler 8004b42: 89fb ldrh r3, [r7, #14] 8004b44: 3301 adds r3, #1 8004b46: 81fb strh r3, [r7, #14] 8004b48: 7e3b ldrb r3, [r7, #24] 8004b4a: b29b uxth r3, r3 8004b4c: 89fa ldrh r2, [r7, #14] 8004b4e: 429a cmp r2, r3 8004b50: d3db bcc.n 8004b0a } } } 8004b52: bf00 nop 8004b54: bf00 nop 8004b56: 3710 adds r7, #16 8004b58: 46bd mov sp, r7 8004b5a: bd80 pop {r7, pc} 08004b5c : void EDCAN_WriteSystemRegister(uint16_t addr, uint8_t value){ 8004b5c: b580 push {r7, lr} 8004b5e: b082 sub sp, #8 8004b60: af00 add r7, sp, #0 8004b62: 4603 mov r3, r0 8004b64: 460a mov r2, r1 8004b66: 80fb strh r3, [r7, #6] 8004b68: 4613 mov r3, r2 8004b6a: 717b strb r3, [r7, #5] switch(addr){ 8004b6c: 88fb ldrh r3, [r7, #6] 8004b6e: 2b00 cmp r3, #0 8004b70: d002 beq.n 8004b78 8004b72: 2b20 cmp r3, #32 8004b74: d00b beq.n 8004b8e // break; //default: // printf ("Unknown register\n"); } } 8004b76: e010 b.n 8004b9a if(value == 0x10){ 8004b78: 797b ldrb r3, [r7, #5] 8004b7a: 2b10 cmp r3, #16 8004b7c: d10c bne.n 8004b98 if(ED_status==0)ED_status = 0x10; 8004b7e: 4b09 ldr r3, [pc, #36] @ (8004ba4 ) 8004b80: 781b ldrb r3, [r3, #0] 8004b82: 2b00 cmp r3, #0 8004b84: d108 bne.n 8004b98 8004b86: 4b07 ldr r3, [pc, #28] @ (8004ba4 ) 8004b88: 2210 movs r2, #16 8004b8a: 701a strb r2, [r3, #0] break; 8004b8c: e004 b.n 8004b98 EDCAN_EnterSilentMode(value); 8004b8e: 797b ldrb r3, [r7, #5] 8004b90: 4618 mov r0, r3 8004b92: f7ff fd65 bl 8004660 break; 8004b96: e000 b.n 8004b9a break; 8004b98: bf00 nop } 8004b9a: bf00 nop 8004b9c: 3708 adds r7, #8 8004b9e: 46bd mov sp, r7 8004ba0: bd80 pop {r7, pc} 8004ba2: bf00 nop 8004ba4: 20003338 .word 0x20003338 08004ba8 : * @brief Handler to get System register values (0..255) * * @param addr: register address * @retval register value (uint8_t) */ uint8_t EDCAN_GetSystemRegisterValue(uint16_t addr){ 8004ba8: b580 push {r7, lr} 8004baa: b082 sub sp, #8 8004bac: af00 add r7, sp, #0 8004bae: 4603 mov r3, r0 8004bb0: 80fb strh r3, [r7, #6] static uint32_t uptime_buffer; switch (addr){ 8004bb2: 88fb ldrh r3, [r7, #6] 8004bb4: 2b17 cmp r3, #23 8004bb6: d852 bhi.n 8004c5e 8004bb8: a201 add r2, pc, #4 @ (adr r2, 8004bc0 ) 8004bba: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004bbe: bf00 nop 8004bc0: 08004c21 .word 0x08004c21 8004bc4: 08004c2b .word 0x08004c2b 8004bc8: 08004c27 .word 0x08004c27 8004bcc: 08004c5f .word 0x08004c5f 8004bd0: 08004c5f .word 0x08004c5f 8004bd4: 08004c5f .word 0x08004c5f 8004bd8: 08004c5f .word 0x08004c5f 8004bdc: 08004c5f .word 0x08004c5f 8004be0: 08004c5f .word 0x08004c5f 8004be4: 08004c5f .word 0x08004c5f 8004be8: 08004c5f .word 0x08004c5f 8004bec: 08004c5f .word 0x08004c5f 8004bf0: 08004c5f .word 0x08004c5f 8004bf4: 08004c5f .word 0x08004c5f 8004bf8: 08004c5f .word 0x08004c5f 8004bfc: 08004c5f .word 0x08004c5f 8004c00: 08004c5f .word 0x08004c5f 8004c04: 08004c5f .word 0x08004c5f 8004c08: 08004c5f .word 0x08004c5f 8004c0c: 08004c5f .word 0x08004c5f 8004c10: 08004c2f .word 0x08004c2f 8004c14: 08004c41 .word 0x08004c41 8004c18: 08004c4b .word 0x08004c4b 8004c1c: 08004c55 .word 0x08004c55 /* регистры 0..255 используются для Системных регистров*/ case EDCAN_REG_SYS_STATUS: return ED_status; 8004c20: 4b11 ldr r3, [pc, #68] @ (8004c68 ) 8004c22: 781b ldrb r3, [r3, #0] 8004c24: e01c b.n 8004c60 break; case EDCAN_REG_SYS_FWVER: return FWVER; 8004c26: 2301 movs r3, #1 8004c28: e01a b.n 8004c60 break; case EDCAN_REG_SYS_DEVICEID: return DEVICE_ID; 8004c2a: 2320 movs r3, #32 8004c2c: e018 b.n 8004c60 break; case EDCAN_REG_SYS_UPTIME0: uptime_buffer = HAL_GetTick(); 8004c2e: f000 fe37 bl 80058a0 8004c32: 4603 mov r3, r0 8004c34: 4a0d ldr r2, [pc, #52] @ (8004c6c ) 8004c36: 6013 str r3, [r2, #0] return uptime_buffer & 0xFF; 8004c38: 4b0c ldr r3, [pc, #48] @ (8004c6c ) 8004c3a: 681b ldr r3, [r3, #0] 8004c3c: b2db uxtb r3, r3 8004c3e: e00f b.n 8004c60 break; case EDCAN_REG_SYS_UPTIME1: return (uptime_buffer>>8) & 0xFF; 8004c40: 4b0a ldr r3, [pc, #40] @ (8004c6c ) 8004c42: 681b ldr r3, [r3, #0] 8004c44: 0a1b lsrs r3, r3, #8 8004c46: b2db uxtb r3, r3 8004c48: e00a b.n 8004c60 break; case EDCAN_REG_SYS_UPTIME2: return (uptime_buffer>>16) & 0xFF; 8004c4a: 4b08 ldr r3, [pc, #32] @ (8004c6c ) 8004c4c: 681b ldr r3, [r3, #0] 8004c4e: 0c1b lsrs r3, r3, #16 8004c50: b2db uxtb r3, r3 8004c52: e005 b.n 8004c60 break; case EDCAN_REG_SYS_UPTIME3: return (uptime_buffer>>24) & 0xFF; 8004c54: 4b05 ldr r3, [pc, #20] @ (8004c6c ) 8004c56: 681b ldr r3, [r3, #0] 8004c58: 0e1b lsrs r3, r3, #24 8004c5a: b2db uxtb r3, r3 8004c5c: e000 b.n 8004c60 break; default: return 0x00; 8004c5e: 2300 movs r3, #0 } } 8004c60: 4618 mov r0, r3 8004c62: 3708 adds r7, #8 8004c64: 46bd mov sp, r7 8004c66: bd80 pop {r7, pc} 8004c68: 20003338 .word 0x20003338 8004c6c: 2000333c .word 0x2000333c 08004c70 : * @brief Handler to get own register values * * @param addr: register address * @retval register value (uint8_t) */ uint8_t EDCAN_GetOwnRegisterValue (uint16_t addr){ 8004c70: b580 push {r7, lr} 8004c72: b082 sub sp, #8 8004c74: af00 add r7, sp, #0 8004c76: 4603 mov r3, r0 8004c78: 80fb strh r3, [r7, #6] if(addr<256){ 8004c7a: 88fb ldrh r3, [r7, #6] 8004c7c: 2bff cmp r3, #255 @ 0xff 8004c7e: d805 bhi.n 8004c8c return EDCAN_GetSystemRegisterValue(addr); // 0..255 8004c80: 88fb ldrh r3, [r7, #6] 8004c82: 4618 mov r0, r3 8004c84: f7ff ff90 bl 8004ba8 8004c88: 4603 mov r3, r0 8004c8a: e004 b.n 8004c96 }else { return EDCAN_GetUserRegisterValue(addr); // 256..2047 8004c8c: 88fb ldrh r3, [r7, #6] 8004c8e: 4618 mov r0, r3 8004c90: f7fe fd84 bl 800379c 8004c94: 4603 mov r3, r0 } } 8004c96: 4618 mov r0, r3 8004c98: 3708 adds r7, #8 8004c9a: 46bd mov sp, r7 8004c9c: bd80 pop {r7, pc} 08004c9e : * DestinationID: Packet Destination ID * Addr: First register address in sequence * *data: pointer for data array * len: length of data (1..255) */ void EDCAN_ReadRequestHandler(uint8_t SourceID, uint8_t DestinationID, uint16_t Addr, uint8_t len){ 8004c9e: b590 push {r4, r7, lr} 8004ca0: b087 sub sp, #28 8004ca2: af00 add r7, sp, #0 8004ca4: 4604 mov r4, r0 8004ca6: 4608 mov r0, r1 8004ca8: 4611 mov r1, r2 8004caa: 461a mov r2, r3 8004cac: 4623 mov r3, r4 8004cae: 71fb strb r3, [r7, #7] 8004cb0: 4603 mov r3, r0 8004cb2: 71bb strb r3, [r7, #6] 8004cb4: 460b mov r3, r1 8004cb6: 80bb strh r3, [r7, #4] 8004cb8: 4613 mov r3, r2 8004cba: 70fb strb r3, [r7, #3] //Получили пакет Read (запрошенное значение регистров) uint8_t TxData[8]; uint16_t AddrOffset = Addr; 8004cbc: 88bb ldrh r3, [r7, #4] 8004cbe: 82fb strh r3, [r7, #22] // printf("Destination ID = %d\n", DestinationID); // printf("Address = %d\n", Addr); // printf("Len = %d\n", len); // printf("\n"); while (len>0){ //по очереди перебираем все полученные регистры через Handler 8004cc0: e051 b.n 8004d66 if(len>=8){ //если количество регистров больше 8, отправляем 8 и разбиваем на несколько пакетов 8004cc2: 78fb ldrb r3, [r7, #3] 8004cc4: 2b07 cmp r3, #7 8004cc6: d926 bls.n 8004d16 for(uint8_t n = 0; n < 8; n++){ 8004cc8: 2300 movs r3, #0 8004cca: 757b strb r3, [r7, #21] 8004ccc: e012 b.n 8004cf4 TxData[n] = EDCAN_GetOwnRegisterValue(n+AddrOffset); 8004cce: 7d7b ldrb r3, [r7, #21] 8004cd0: b29a uxth r2, r3 8004cd2: 8afb ldrh r3, [r7, #22] 8004cd4: 4413 add r3, r2 8004cd6: b29b uxth r3, r3 8004cd8: 7d7c ldrb r4, [r7, #21] 8004cda: 4618 mov r0, r3 8004cdc: f7ff ffc8 bl 8004c70 8004ce0: 4603 mov r3, r0 8004ce2: 461a mov r2, r3 8004ce4: f104 0318 add.w r3, r4, #24 8004ce8: 443b add r3, r7 8004cea: f803 2c0c strb.w r2, [r3, #-12] for(uint8_t n = 0; n < 8; n++){ 8004cee: 7d7b ldrb r3, [r7, #21] 8004cf0: 3301 adds r3, #1 8004cf2: 757b strb r3, [r7, #21] 8004cf4: 7d7b ldrb r3, [r7, #21] 8004cf6: 2b07 cmp r3, #7 8004cf8: d9e9 bls.n 8004cce //printf ("register[%d] = %d\n", n+AddrOffset, TxData[n]); } EDCAN_SendPacketRead(SourceID, AddrOffset, TxData, 8); /* отправляем ответный пакет со значениями собственных регистров */ 8004cfa: f107 020c add.w r2, r7, #12 8004cfe: 8af9 ldrh r1, [r7, #22] 8004d00: 79f8 ldrb r0, [r7, #7] 8004d02: 2308 movs r3, #8 8004d04: f7ff fc12 bl 800452c //printf ("sent%d, %d\n", AddrOffset, len); AddrOffset +=8; 8004d08: 8afb ldrh r3, [r7, #22] 8004d0a: 3308 adds r3, #8 8004d0c: 82fb strh r3, [r7, #22] len -=8; 8004d0e: 78fb ldrb r3, [r7, #3] 8004d10: 3b08 subs r3, #8 8004d12: 70fb strb r3, [r7, #3] 8004d14: e027 b.n 8004d66 }else{ for(uint8_t n = 0; n < len; n++){ 8004d16: 2300 movs r3, #0 8004d18: 753b strb r3, [r7, #20] 8004d1a: e012 b.n 8004d42 TxData[n] = EDCAN_GetOwnRegisterValue(n+AddrOffset); 8004d1c: 7d3b ldrb r3, [r7, #20] 8004d1e: b29a uxth r2, r3 8004d20: 8afb ldrh r3, [r7, #22] 8004d22: 4413 add r3, r2 8004d24: b29b uxth r3, r3 8004d26: 7d3c ldrb r4, [r7, #20] 8004d28: 4618 mov r0, r3 8004d2a: f7ff ffa1 bl 8004c70 8004d2e: 4603 mov r3, r0 8004d30: 461a mov r2, r3 8004d32: f104 0318 add.w r3, r4, #24 8004d36: 443b add r3, r7 8004d38: f803 2c0c strb.w r2, [r3, #-12] for(uint8_t n = 0; n < len; n++){ 8004d3c: 7d3b ldrb r3, [r7, #20] 8004d3e: 3301 adds r3, #1 8004d40: 753b strb r3, [r7, #20] 8004d42: 7d3a ldrb r2, [r7, #20] 8004d44: 78fb ldrb r3, [r7, #3] 8004d46: 429a cmp r2, r3 8004d48: d3e8 bcc.n 8004d1c //printf ("register[%d] = %d\n", n+AddrOffset, TxData[n]); } EDCAN_SendPacketRead(SourceID, AddrOffset, TxData, len); /* отправляем ответный пакет со значениями собственных регистров */ 8004d4a: 78fb ldrb r3, [r7, #3] 8004d4c: f107 020c add.w r2, r7, #12 8004d50: 8af9 ldrh r1, [r7, #22] 8004d52: 79f8 ldrb r0, [r7, #7] 8004d54: f7ff fbea bl 800452c //printf ("sent%d, %d\n", AddrOffset, len); AddrOffset +=len; 8004d58: 78fb ldrb r3, [r7, #3] 8004d5a: b29a uxth r2, r3 8004d5c: 8afb ldrh r3, [r7, #22] 8004d5e: 4413 add r3, r2 8004d60: 82fb strh r3, [r7, #22] len = 0; 8004d62: 2300 movs r3, #0 8004d64: 70fb strb r3, [r7, #3] while (len>0){ //по очереди перебираем все полученные регистры через Handler 8004d66: 78fb ldrb r3, [r7, #3] 8004d68: 2b00 cmp r3, #0 8004d6a: d1aa bne.n 8004cc2 } } // printf("\n"); } 8004d6c: bf00 nop 8004d6e: bf00 nop 8004d70: 371c adds r7, #28 8004d72: 46bd mov sp, r7 8004d74: bd90 pop {r4, r7, pc} ... 08004d78 : // EDCAN_printf(LOG_WARN, "LOG_WARN test\n"); // EDCAN_printf(LOG_NOTICE, "LOG_NOTICE test\n"); // EDCAN_printf(LOG_INFO, "LOG_INFO test\n"); // EDCAN_printf(LOG_DEBUG, "LOG_DEBUG test\n"); void EDCAN_printf(EDCAN_LogLevel_t loglevel, const char *format, ...) { 8004d78: b40e push {r1, r2, r3} 8004d7a: b580 push {r7, lr} 8004d7c: f2ad 4d14 subw sp, sp, #1044 @ 0x414 8004d80: af00 add r7, sp, #0 8004d82: 4602 mov r2, r0 8004d84: f507 6382 add.w r3, r7, #1040 @ 0x410 8004d88: f2a3 4309 subw r3, r3, #1033 @ 0x409 8004d8c: 701a strb r2, [r3, #0] char buffer[1024]; // Размер буфера можно изменить в зависимости от потребностей va_list args; va_start(args, format); 8004d8e: f507 6284 add.w r2, r7, #1056 @ 0x420 8004d92: f507 6382 add.w r3, r7, #1040 @ 0x410 8004d96: f5a3 6381 sub.w r3, r3, #1032 @ 0x408 8004d9a: 601a str r2, [r3, #0] int offset = snprintf(buffer, sizeof(buffer), "%d", loglevel); // Записываем лог-уровень в начало 8004d9c: f507 6382 add.w r3, r7, #1040 @ 0x410 8004da0: f2a3 4309 subw r3, r3, #1033 @ 0x409 8004da4: 781b ldrb r3, [r3, #0] 8004da6: f107 000c add.w r0, r7, #12 8004daa: 4a17 ldr r2, [pc, #92] @ (8004e08 ) 8004dac: f44f 6180 mov.w r1, #1024 @ 0x400 8004db0: f004 ffe8 bl 8009d84 8004db4: f8c7 040c str.w r0, [r7, #1036] @ 0x40c vsnprintf(buffer + offset, sizeof(buffer) - offset, format, args); // Записываем основное сообщение с учётом смещения 8004db8: f8d7 340c ldr.w r3, [r7, #1036] @ 0x40c 8004dbc: f107 020c add.w r2, r7, #12 8004dc0: 18d0 adds r0, r2, r3 8004dc2: f8d7 340c ldr.w r3, [r7, #1036] @ 0x40c 8004dc6: f5c3 6180 rsb r1, r3, #1024 @ 0x400 8004dca: f507 6382 add.w r3, r7, #1040 @ 0x410 8004dce: f5a3 6381 sub.w r3, r3, #1032 @ 0x408 8004dd2: 681b ldr r3, [r3, #0] 8004dd4: f8d7 241c ldr.w r2, [r7, #1052] @ 0x41c 8004dd8: f005 f8dc bl 8009f94 va_end(args); EDCAN_Log(buffer, strlen(buffer)); 8004ddc: f107 030c add.w r3, r7, #12 8004de0: 4618 mov r0, r3 8004de2: f7fb fa2b bl 800023c 8004de6: 4603 mov r3, r0 8004de8: b29a uxth r2, r3 8004dea: f107 030c add.w r3, r7, #12 8004dee: 4611 mov r1, r2 8004df0: 4618 mov r0, r3 8004df2: f000 f80b bl 8004e0c } 8004df6: bf00 nop 8004df8: f207 4714 addw r7, r7, #1044 @ 0x414 8004dfc: 46bd mov sp, r7 8004dfe: e8bd 4080 ldmia.w sp!, {r7, lr} 8004e02: b003 add sp, #12 8004e04: 4770 bx lr 8004e06: bf00 nop 8004e08: 0800df10 .word 0x0800df10 08004e0c : * @param DestinationID: Packet Destination ID * @param RegAddr: First register address in sequence * @param *data: pointer to data array to be send * @param len: length of data to be sent */ void EDCAN_Log(const char *data, uint16_t len) { 8004e0c: b580 push {r7, lr} 8004e0e: b086 sub sp, #24 8004e10: af00 add r7, sp, #0 8004e12: 6078 str r0, [r7, #4] 8004e14: 460b mov r3, r1 8004e16: 807b strh r3, [r7, #2] uint8_t DestinationID = 0x00; 8004e18: 2300 movs r3, #0 8004e1a: 73fb strb r3, [r7, #15] uint16_t remainingBytes = len;//strlen(data)+1; //add zero symbol 8004e1c: 887b ldrh r3, [r7, #2] 8004e1e: 82fb strh r3, [r7, #22] uint16_t currentRegAddr = 0x00; //LOG reg addr 8004e20: 2300 movs r3, #0 8004e22: 81bb strh r3, [r7, #12] uint8_t *currentDataPtr = data; 8004e24: 687b ldr r3, [r7, #4] 8004e26: 613b str r3, [r7, #16] while (remainingBytes > 0) { 8004e28: e014 b.n 8004e54 uint8_t packetSize = (remainingBytes > 8) ? 8 : remainingBytes; 8004e2a: 8afb ldrh r3, [r7, #22] 8004e2c: 2b08 cmp r3, #8 8004e2e: bf28 it cs 8004e30: 2308 movcs r3, #8 8004e32: b29b uxth r3, r3 8004e34: 72fb strb r3, [r7, #11] EDCAN_SendPacketLog(DestinationID, currentRegAddr, currentDataPtr, packetSize); 8004e36: 7afb ldrb r3, [r7, #11] 8004e38: 89b9 ldrh r1, [r7, #12] 8004e3a: 7bf8 ldrb r0, [r7, #15] 8004e3c: 693a ldr r2, [r7, #16] 8004e3e: f000 f811 bl 8004e64 remainingBytes -= packetSize; 8004e42: 7afb ldrb r3, [r7, #11] 8004e44: b29b uxth r3, r3 8004e46: 8afa ldrh r2, [r7, #22] 8004e48: 1ad3 subs r3, r2, r3 8004e4a: 82fb strh r3, [r7, #22] //currentRegAddr += packetSize; // Assuming the register address increments by the number of bytes sent currentDataPtr += packetSize; 8004e4c: 7afb ldrb r3, [r7, #11] 8004e4e: 693a ldr r2, [r7, #16] 8004e50: 4413 add r3, r2 8004e52: 613b str r3, [r7, #16] while (remainingBytes > 0) { 8004e54: 8afb ldrh r3, [r7, #22] 8004e56: 2b00 cmp r3, #0 8004e58: d1e7 bne.n 8004e2a } } 8004e5a: bf00 nop 8004e5c: bf00 nop 8004e5e: 3718 adds r7, #24 8004e60: 46bd mov sp, r7 8004e62: bd80 pop {r7, pc} 08004e64 : * @param DestinationID: Packet Destination ID * @param RegAddr: First register address in sequence * @param *data: pointer to data array to be send * @param len: length of data (1..8) */ void EDCAN_SendPacketLog(uint8_t DestinationID, uint16_t RegAddr, const uint8_t *data, uint8_t len){ 8004e64: b580 push {r7, lr} 8004e66: b08c sub sp, #48 @ 0x30 8004e68: af00 add r7, sp, #0 8004e6a: 603a str r2, [r7, #0] 8004e6c: 461a mov r2, r3 8004e6e: 4603 mov r3, r0 8004e70: 71fb strb r3, [r7, #7] 8004e72: 460b mov r3, r1 8004e74: 80bb strh r3, [r7, #4] 8004e76: 4613 mov r3, r2 8004e78: 71bb strb r3, [r7, #6] EDCAN_TxFrame_t tx_frame; EDCAN_frameId_t ExtID; //CAN_TxHeaderTypeDef tx_header; //uint32_t tx_mailbox; ExtID.DestinationID = DestinationID; 8004e7a: 79fb ldrb r3, [r7, #7] 8004e7c: 733b strb r3, [r7, #12] ExtID.SourceID = ED_OwnID; 8004e7e: 4b15 ldr r3, [pc, #84] @ (8004ed4 ) 8004e80: 781b ldrb r3, [r3, #0] 8004e82: 737b strb r3, [r7, #13] ExtID.RegisterAddress = RegAddr; 8004e84: 88bb ldrh r3, [r7, #4] 8004e86: f3c3 030a ubfx r3, r3, #0, #11 8004e8a: b29a uxth r2, r3 8004e8c: 89fb ldrh r3, [r7, #14] 8004e8e: f362 030a bfi r3, r2, #0, #11 8004e92: 81fb strh r3, [r7, #14] ExtID.PacketType = ED_LOG; 8004e94: 7bfb ldrb r3, [r7, #15] 8004e96: f043 0318 orr.w r3, r3, #24 8004e9a: 73fb strb r3, [r7, #15] memcpy(&tx_frame.tx_header.ExtId, &ExtID, sizeof(ExtID)); 8004e9c: 68fb ldr r3, [r7, #12] 8004e9e: 617b str r3, [r7, #20] tx_frame.tx_header.RTR = CAN_RTR_DATA; 8004ea0: 2300 movs r3, #0 8004ea2: 61fb str r3, [r7, #28] tx_frame.tx_header.IDE = CAN_ID_EXT; 8004ea4: 2304 movs r3, #4 8004ea6: 61bb str r3, [r7, #24] tx_frame.tx_header.DLC = len; 8004ea8: 79bb ldrb r3, [r7, #6] 8004eaa: 623b str r3, [r7, #32] memcpy(&tx_frame.data, data, len); 8004eac: 79ba ldrb r2, [r7, #6] 8004eae: f107 0310 add.w r3, r7, #16 8004eb2: 3318 adds r3, #24 8004eb4: 6839 ldr r1, [r7, #0] 8004eb6: 4618 mov r0, r3 8004eb8: f005 fe28 bl 800ab0c //EDCAN_AddTxMessage(&ED_CAN_INSTANCE, &tx_header, data, &tx_mailbox); //Добавление пакета в буфер EDCAN_TxBufferAdd(&tx_frame); 8004ebc: f107 0310 add.w r3, r7, #16 8004ec0: 4618 mov r0, r3 8004ec2: f7ff fc23 bl 800470c //Также, попытаемся сразу перенести пакет в CAN (если там есть свободное место) //Если свободного места нету, то пакет перенесется в CAN позже по прерыванию освобождения буфера EDCAN_ExchangeTxBuffer(); 8004ec6: f7ff fce1 bl 800488c } 8004eca: bf00 nop 8004ecc: 3730 adds r7, #48 @ 0x30 8004ece: 46bd mov sp, r7 8004ed0: bd80 pop {r7, pc} 8004ed2: bf00 nop 8004ed4: 200005dd .word 0x200005dd 08004ed8
: /** * @brief The application entry point. * @retval int */ int main(void) { 8004ed8: b580 push {r7, lr} 8004eda: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8004edc: f000 fc88 bl 80057f0 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8004ee0: f000 f842 bl 8004f68 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8004ee4: f7fe fe6e bl 8003bc4 MX_ADC1_Init(); 8004ee8: f7fc fb78 bl 80015dc MX_CAN1_Init(); 8004eec: f7fc fd32 bl 8001954 MX_CAN2_Init(); 8004ef0: f7fc fd66 bl 80019c0 MX_USART2_UART_Init(); 8004ef4: f000 fbca bl 800568c MX_RTC_Init(); 8004ef8: f000 f8ac bl 8005054 /* USER CODE BEGIN 2 */ CAN_ReInit(); 8004efc: f7ff fa8a bl 8004414 Init_Peripheral(); 8004f00: f7fc fc22 bl 8001748 HAL_Delay(300); 8004f04: f44f 7096 mov.w r0, #300 @ 0x12c 8004f08: f000 fcd4 bl 80058b4 GBT_Init(); 8004f0c: f7fc fe6c bl 8001be8 set_Time(1721651966); 8004f10: 4812 ldr r0, [pc, #72] @ (8004f5c ) 8004f12: f000 f8e9 bl 80050e8 printf("Startup (type \'help\' for command list)\n"); 8004f16: 4812 ldr r0, [pc, #72] @ (8004f60 ) 8004f18: f005 f8d0 bl 800a0bc debug_init(); 8004f1c: f7fd ffe6 bl 8002eec EDCAN_Init(SW_GetAddr()); //0x20..0x23 8004f20: f7fc fcf2 bl 8001908 8004f24: 4603 mov r3, r0 8004f26: 4618 mov r0, r3 8004f28: f7ff fa64 bl 80043f4 EDCAN_printf(LOG_INFO, "Startup FWVER = %d\n", FWVER); 8004f2c: 2201 movs r2, #1 8004f2e: 490d ldr r1, [pc, #52] @ (8004f64 ) 8004f30: 2006 movs r0, #6 8004f32: f7ff ff21 bl 8004d78 //EDCAN_Init(0x20); //Адрес EDCAN GBT_CAN_ReInit(); 8004f36: f7ff f87b bl 8004030 CAN_ReInit(); 8004f3a: f7ff fa6b bl 8004414 CONN_Init(); 8004f3e: f7fd fd2c bl 800299a { /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ // HAL_Delay(1); EDCAN_Loop(); 8004f42: f7ff fb2d bl 80045a0 //can_task(); debug_task(); 8004f46: f7fe fb4f bl 80035e8 CONN_CC_ReadStateFiltered(); 8004f4a: f7fd fe85 bl 8002c58 // GBT_ManageLock(); CONN_Task(); 8004f4e: f7fd fd2b bl 80029a8 GBT_ChargerTask(); 8004f52: f7fc fe81 bl 8001c58 { 8004f56: bf00 nop 8004f58: e7f3 b.n 8004f42 8004f5a: bf00 nop 8004f5c: 669e52fe .word 0x669e52fe 8004f60: 0800df14 .word 0x0800df14 8004f64: 0800df3c .word 0x0800df3c 08004f68 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8004f68: b580 push {r7, lr} 8004f6a: b09c sub sp, #112 @ 0x70 8004f6c: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8004f6e: f107 0338 add.w r3, r7, #56 @ 0x38 8004f72: 2238 movs r2, #56 @ 0x38 8004f74: 2100 movs r1, #0 8004f76: 4618 mov r0, r3 8004f78: f005 f8a8 bl 800a0cc RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8004f7c: f107 0324 add.w r3, r7, #36 @ 0x24 8004f80: 2200 movs r2, #0 8004f82: 601a str r2, [r3, #0] 8004f84: 605a str r2, [r3, #4] 8004f86: 609a str r2, [r3, #8] 8004f88: 60da str r2, [r3, #12] 8004f8a: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8004f8c: 1d3b adds r3, r7, #4 8004f8e: 2220 movs r2, #32 8004f90: 2100 movs r1, #0 8004f92: 4618 mov r0, r3 8004f94: f005 f89a bl 800a0cc /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; 8004f98: 2305 movs r3, #5 8004f9a: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8004f9c: f44f 3380 mov.w r3, #65536 @ 0x10000 8004fa0: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV5; 8004fa2: 2304 movs r3, #4 8004fa4: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 8004fa6: 2301 movs r3, #1 8004fa8: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8004faa: 2301 movs r3, #1 8004fac: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.Prediv1Source = RCC_PREDIV1_SOURCE_PLL2; 8004fae: f44f 3380 mov.w r3, #65536 @ 0x10000 8004fb2: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8004fb4: 2302 movs r3, #2 8004fb6: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8004fb8: f44f 3380 mov.w r3, #65536 @ 0x10000 8004fbc: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 8004fbe: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000 8004fc2: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL2.PLL2State = RCC_PLL2_ON; 8004fc4: 2302 movs r3, #2 8004fc6: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL2.PLL2MUL = RCC_PLL2_MUL8; 8004fc8: f44f 63c0 mov.w r3, #1536 @ 0x600 8004fcc: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL2.HSEPrediv2Value = RCC_HSE_PREDIV2_DIV5; 8004fce: 2340 movs r3, #64 @ 0x40 8004fd0: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8004fd2: f107 0338 add.w r3, r7, #56 @ 0x38 8004fd6: 4618 mov r0, r3 8004fd8: f002 fc50 bl 800787c 8004fdc: 4603 mov r3, r0 8004fde: 2b00 cmp r3, #0 8004fe0: d001 beq.n 8004fe6 { Error_Handler(); 8004fe2: f000 f831 bl 8005048 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8004fe6: 230f movs r3, #15 8004fe8: 627b str r3, [r7, #36] @ 0x24 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8004fea: 2302 movs r3, #2 8004fec: 62bb str r3, [r7, #40] @ 0x28 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8004fee: 2300 movs r3, #0 8004ff0: 62fb str r3, [r7, #44] @ 0x2c RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8004ff2: f44f 6380 mov.w r3, #1024 @ 0x400 8004ff6: 633b str r3, [r7, #48] @ 0x30 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8004ff8: 2300 movs r3, #0 8004ffa: 637b str r3, [r7, #52] @ 0x34 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8004ffc: f107 0324 add.w r3, r7, #36 @ 0x24 8005000: 2102 movs r1, #2 8005002: 4618 mov r0, r3 8005004: f002 ff50 bl 8007ea8 8005008: 4603 mov r3, r0 800500a: 2b00 cmp r3, #0 800500c: d001 beq.n 8005012 { Error_Handler(); 800500e: f000 f81b bl 8005048 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; 8005012: 2303 movs r3, #3 8005014: 607b str r3, [r7, #4] PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 8005016: f44f 7380 mov.w r3, #256 @ 0x100 800501a: 60bb str r3, [r7, #8] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 800501c: f44f 4300 mov.w r3, #32768 @ 0x8000 8005020: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8005022: 1d3b adds r3, r7, #4 8005024: 4618 mov r0, r3 8005026: f003 f957 bl 80082d8 800502a: 4603 mov r3, r0 800502c: 2b00 cmp r3, #0 800502e: d001 beq.n 8005034 { Error_Handler(); 8005030: f000 f80a bl 8005048 } /** Configure the Systick interrupt time */ __HAL_RCC_PLLI2S_ENABLE(); 8005034: 4b03 ldr r3, [pc, #12] @ (8005044 ) 8005036: 2201 movs r2, #1 8005038: 601a str r2, [r3, #0] } 800503a: bf00 nop 800503c: 3770 adds r7, #112 @ 0x70 800503e: 46bd mov sp, r7 8005040: bd80 pop {r7, pc} 8005042: bf00 nop 8005044: 42420070 .word 0x42420070 08005048 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8005048: b480 push {r7} 800504a: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800504c: b672 cpsid i } 800504e: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8005050: bf00 nop 8005052: e7fd b.n 8005050 08005054 : RTC_HandleTypeDef hrtc; /* RTC init function */ void MX_RTC_Init(void) { 8005054: b580 push {r7, lr} 8005056: af00 add r7, sp, #0 /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 8005058: 4b0a ldr r3, [pc, #40] @ (8005084 ) 800505a: 4a0b ldr r2, [pc, #44] @ (8005088 ) 800505c: 601a str r2, [r3, #0] hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; 800505e: 4b09 ldr r3, [pc, #36] @ (8005084 ) 8005060: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8005064: 605a str r2, [r3, #4] hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; 8005066: 4b07 ldr r3, [pc, #28] @ (8005084 ) 8005068: f44f 7280 mov.w r2, #256 @ 0x100 800506c: 609a str r2, [r3, #8] if (HAL_RTC_Init(&hrtc) != HAL_OK) 800506e: 4805 ldr r0, [pc, #20] @ (8005084 ) 8005070: f003 fbc6 bl 8008800 8005074: 4603 mov r3, r0 8005076: 2b00 cmp r3, #0 8005078: d001 beq.n 800507e { Error_Handler(); 800507a: f7ff ffe5 bl 8005048 } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 800507e: bf00 nop 8005080: bd80 pop {r7, pc} 8005082: bf00 nop 8005084: 20003340 .word 0x20003340 8005088: 40002800 .word 0x40002800 0800508c : void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) { 800508c: b580 push {r7, lr} 800508e: b084 sub sp, #16 8005090: af00 add r7, sp, #0 8005092: 6078 str r0, [r7, #4] if(rtcHandle->Instance==RTC) 8005094: 687b ldr r3, [r7, #4] 8005096: 681b ldr r3, [r3, #0] 8005098: 4a0b ldr r2, [pc, #44] @ (80050c8 ) 800509a: 4293 cmp r3, r2 800509c: d110 bne.n 80050c0 { /* USER CODE BEGIN RTC_MspInit 0 */ /* USER CODE END RTC_MspInit 0 */ HAL_PWR_EnableBkUpAccess(); 800509e: f002 fbe1 bl 8007864 /* Enable BKP CLK enable for backup registers */ __HAL_RCC_BKP_CLK_ENABLE(); 80050a2: 4b0a ldr r3, [pc, #40] @ (80050cc ) 80050a4: 69db ldr r3, [r3, #28] 80050a6: 4a09 ldr r2, [pc, #36] @ (80050cc ) 80050a8: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 80050ac: 61d3 str r3, [r2, #28] 80050ae: 4b07 ldr r3, [pc, #28] @ (80050cc ) 80050b0: 69db ldr r3, [r3, #28] 80050b2: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80050b6: 60fb str r3, [r7, #12] 80050b8: 68fb ldr r3, [r7, #12] /* RTC clock enable */ __HAL_RCC_RTC_ENABLE(); 80050ba: 4b05 ldr r3, [pc, #20] @ (80050d0 ) 80050bc: 2201 movs r2, #1 80050be: 601a str r2, [r3, #0] /* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE END RTC_MspInit 1 */ } } 80050c0: bf00 nop 80050c2: 3710 adds r7, #16 80050c4: 46bd mov sp, r7 80050c6: bd80 pop {r7, pc} 80050c8: 40002800 .word 0x40002800 80050cc: 40021000 .word 0x40021000 80050d0: 4242043c .word 0x4242043c 080050d4 : static uint32_t RTC1_ReadTimeCounter(RTC_HandleTypeDef *hrtc); static HAL_StatusTypeDef RTC1_ExitInitMode(RTC_HandleTypeDef *hrtc); static HAL_StatusTypeDef RTC1_EnterInitMode(RTC_HandleTypeDef *hrtc); uint32_t get_Current_Time(){ 80050d4: b580 push {r7, lr} 80050d6: af00 add r7, sp, #0 return RTC1_ReadTimeCounter(&hrtc); 80050d8: 4802 ldr r0, [pc, #8] @ (80050e4 ) 80050da: f000 f8fd bl 80052d8 80050de: 4603 mov r3, r0 } 80050e0: 4618 mov r0, r3 80050e2: bd80 pop {r7, pc} 80050e4: 20003340 .word 0x20003340 080050e8 : void set_Time(uint32_t unix_time){ 80050e8: b580 push {r7, lr} 80050ea: b082 sub sp, #8 80050ec: af00 add r7, sp, #0 80050ee: 6078 str r0, [r7, #4] RTC1_WriteTimeCounter(&hrtc, unix_time); 80050f0: 6879 ldr r1, [r7, #4] 80050f2: 4803 ldr r0, [pc, #12] @ (8005100 ) 80050f4: f000 f920 bl 8005338 } 80050f8: bf00 nop 80050fa: 3708 adds r7, #8 80050fc: 46bd mov sp, r7 80050fe: bd80 pop {r7, pc} 8005100: 20003340 .word 0x20003340 08005104 : uint8_t to_bcd(int value) { 8005104: b480 push {r7} 8005106: b083 sub sp, #12 8005108: af00 add r7, sp, #0 800510a: 6078 str r0, [r7, #4] return ((value / 10) << 4) | (value % 10); 800510c: 687b ldr r3, [r7, #4] 800510e: 4a0f ldr r2, [pc, #60] @ (800514c ) 8005110: fb82 1203 smull r1, r2, r2, r3 8005114: 1092 asrs r2, r2, #2 8005116: 17db asrs r3, r3, #31 8005118: 1ad3 subs r3, r2, r3 800511a: b25b sxtb r3, r3 800511c: 011b lsls r3, r3, #4 800511e: b258 sxtb r0, r3 8005120: 687a ldr r2, [r7, #4] 8005122: 4b0a ldr r3, [pc, #40] @ (800514c ) 8005124: fb83 1302 smull r1, r3, r3, r2 8005128: 1099 asrs r1, r3, #2 800512a: 17d3 asrs r3, r2, #31 800512c: 1ac9 subs r1, r1, r3 800512e: 460b mov r3, r1 8005130: 009b lsls r3, r3, #2 8005132: 440b add r3, r1 8005134: 005b lsls r3, r3, #1 8005136: 1ad1 subs r1, r2, r3 8005138: b24b sxtb r3, r1 800513a: 4303 orrs r3, r0 800513c: b25b sxtb r3, r3 800513e: b2db uxtb r3, r3 } 8005140: 4618 mov r0, r3 8005142: 370c adds r7, #12 8005144: 46bd mov sp, r7 8005146: bc80 pop {r7} 8005148: 4770 bx lr 800514a: bf00 nop 800514c: 66666667 .word 0x66666667 08005150 : void unix_to_bcd(uint32_t unix_time, uint8_t *time) { 8005150: b590 push {r4, r7, lr} 8005152: b087 sub sp, #28 8005154: af00 add r7, sp, #0 8005156: 6078 str r0, [r7, #4] 8005158: 6039 str r1, [r7, #0] struct tm *tm_info; time_t raw_time = (time_t)unix_time; 800515a: 6879 ldr r1, [r7, #4] 800515c: 2000 movs r0, #0 800515e: 460a mov r2, r1 8005160: 4603 mov r3, r0 8005162: e9c7 2302 strd r2, r3, [r7, #8] tm_info = gmtime(&raw_time); 8005166: f107 0308 add.w r3, r7, #8 800516a: 4618 mov r0, r3 800516c: f004 ffc8 bl 800a100 8005170: 6178 str r0, [r7, #20] time[0] = to_bcd(tm_info->tm_sec); 8005172: 697b ldr r3, [r7, #20] 8005174: 681b ldr r3, [r3, #0] 8005176: 4618 mov r0, r3 8005178: f7ff ffc4 bl 8005104 800517c: 4603 mov r3, r0 800517e: 461a mov r2, r3 8005180: 683b ldr r3, [r7, #0] 8005182: 701a strb r2, [r3, #0] time[1] = to_bcd(tm_info->tm_min); 8005184: 697b ldr r3, [r7, #20] 8005186: 685a ldr r2, [r3, #4] 8005188: 683b ldr r3, [r7, #0] 800518a: 1c5c adds r4, r3, #1 800518c: 4610 mov r0, r2 800518e: f7ff ffb9 bl 8005104 8005192: 4603 mov r3, r0 8005194: 7023 strb r3, [r4, #0] time[2] = to_bcd(tm_info->tm_hour); 8005196: 697b ldr r3, [r7, #20] 8005198: 689a ldr r2, [r3, #8] 800519a: 683b ldr r3, [r7, #0] 800519c: 1c9c adds r4, r3, #2 800519e: 4610 mov r0, r2 80051a0: f7ff ffb0 bl 8005104 80051a4: 4603 mov r3, r0 80051a6: 7023 strb r3, [r4, #0] time[3] = to_bcd(tm_info->tm_mday); 80051a8: 697b ldr r3, [r7, #20] 80051aa: 68da ldr r2, [r3, #12] 80051ac: 683b ldr r3, [r7, #0] 80051ae: 1cdc adds r4, r3, #3 80051b0: 4610 mov r0, r2 80051b2: f7ff ffa7 bl 8005104 80051b6: 4603 mov r3, r0 80051b8: 7023 strb r3, [r4, #0] time[4] = to_bcd(tm_info->tm_mon + 1); // tm_mon is 0-11 80051ba: 697b ldr r3, [r7, #20] 80051bc: 691b ldr r3, [r3, #16] 80051be: 1c5a adds r2, r3, #1 80051c0: 683b ldr r3, [r7, #0] 80051c2: 1d1c adds r4, r3, #4 80051c4: 4610 mov r0, r2 80051c6: f7ff ff9d bl 8005104 80051ca: 4603 mov r3, r0 80051cc: 7023 strb r3, [r4, #0] time[5] = to_bcd((tm_info->tm_year + 1900) % 100); // Year in 2 digits 80051ce: 697b ldr r3, [r7, #20] 80051d0: 695b ldr r3, [r3, #20] 80051d2: f203 736c addw r3, r3, #1900 @ 0x76c 80051d6: 4a13 ldr r2, [pc, #76] @ (8005224 ) 80051d8: fb82 1203 smull r1, r2, r2, r3 80051dc: 1151 asrs r1, r2, #5 80051de: 17da asrs r2, r3, #31 80051e0: 1a8a subs r2, r1, r2 80051e2: 2164 movs r1, #100 @ 0x64 80051e4: fb01 f202 mul.w r2, r1, r2 80051e8: 1a9a subs r2, r3, r2 80051ea: 683b ldr r3, [r7, #0] 80051ec: 1d5c adds r4, r3, #5 80051ee: 4610 mov r0, r2 80051f0: f7ff ff88 bl 8005104 80051f4: 4603 mov r3, r0 80051f6: 7023 strb r3, [r4, #0] time[6] = to_bcd((tm_info->tm_year + 1900) / 100); // Century in 2 digits 80051f8: 697b ldr r3, [r7, #20] 80051fa: 695b ldr r3, [r3, #20] 80051fc: f203 736c addw r3, r3, #1900 @ 0x76c 8005200: 4a08 ldr r2, [pc, #32] @ (8005224 ) 8005202: fb82 1203 smull r1, r2, r2, r3 8005206: 1152 asrs r2, r2, #5 8005208: 17db asrs r3, r3, #31 800520a: 1ad2 subs r2, r2, r3 800520c: 683b ldr r3, [r7, #0] 800520e: 1d9c adds r4, r3, #6 8005210: 4610 mov r0, r2 8005212: f7ff ff77 bl 8005104 8005216: 4603 mov r3, r0 8005218: 7023 strb r3, [r4, #0] } 800521a: bf00 nop 800521c: 371c adds r7, #28 800521e: 46bd mov sp, r7 8005220: bd90 pop {r4, r7, pc} 8005222: bf00 nop 8005224: 51eb851f .word 0x51eb851f 08005228 : void writeTimeReg(uint8_t reg_number, uint8_t value){ 8005228: b580 push {r7, lr} 800522a: b082 sub sp, #8 800522c: af00 add r7, sp, #0 800522e: 4603 mov r3, r0 8005230: 460a mov r2, r1 8005232: 71fb strb r3, [r7, #7] 8005234: 4613 mov r3, r2 8005236: 71bb strb r3, [r7, #6] tmp_time[reg_number] = value; 8005238: 79fb ldrb r3, [r7, #7] 800523a: 490e ldr r1, [pc, #56] @ (8005274 ) 800523c: 79ba ldrb r2, [r7, #6] 800523e: 54ca strb r2, [r1, r3] if(reg_number == 3) set_Time((tmp_time[0])+(tmp_time[1]<<8)+(tmp_time[2]<<16)+(tmp_time[3]<<24)); 8005240: 79fb ldrb r3, [r7, #7] 8005242: 2b03 cmp r3, #3 8005244: d111 bne.n 800526a 8005246: 4b0b ldr r3, [pc, #44] @ (8005274 ) 8005248: 781b ldrb r3, [r3, #0] 800524a: 461a mov r2, r3 800524c: 4b09 ldr r3, [pc, #36] @ (8005274 ) 800524e: 785b ldrb r3, [r3, #1] 8005250: 021b lsls r3, r3, #8 8005252: 441a add r2, r3 8005254: 4b07 ldr r3, [pc, #28] @ (8005274 ) 8005256: 789b ldrb r3, [r3, #2] 8005258: 041b lsls r3, r3, #16 800525a: 441a add r2, r3 800525c: 4b05 ldr r3, [pc, #20] @ (8005274 ) 800525e: 78db ldrb r3, [r3, #3] 8005260: 061b lsls r3, r3, #24 8005262: 4413 add r3, r2 8005264: 4618 mov r0, r3 8005266: f7ff ff3f bl 80050e8 }; 800526a: bf00 nop 800526c: 3708 adds r7, #8 800526e: 46bd mov sp, r7 8005270: bd80 pop {r7, pc} 8005272: bf00 nop 8005274: 20003354 .word 0x20003354 08005278 : uint8_t getTimeReg(uint8_t reg_number){ 8005278: b580 push {r7, lr} 800527a: b082 sub sp, #8 800527c: af00 add r7, sp, #0 800527e: 4603 mov r3, r0 8005280: 71fb strb r3, [r7, #7] if(reg_number == 0){ 8005282: 79fb ldrb r3, [r7, #7] 8005284: 2b00 cmp r3, #0 8005286: d108 bne.n 800529a tmp_time32 = get_Current_Time(); 8005288: f7ff ff24 bl 80050d4 800528c: 4603 mov r3, r0 800528e: 4a11 ldr r2, [pc, #68] @ (80052d4 ) 8005290: 6013 str r3, [r2, #0] return tmp_time32 & 0xFF; 8005292: 4b10 ldr r3, [pc, #64] @ (80052d4 ) 8005294: 681b ldr r3, [r3, #0] 8005296: b2db uxtb r3, r3 8005298: e018 b.n 80052cc }else if(reg_number == 1){ 800529a: 79fb ldrb r3, [r7, #7] 800529c: 2b01 cmp r3, #1 800529e: d104 bne.n 80052aa return (tmp_time32>>8) & 0xFF; 80052a0: 4b0c ldr r3, [pc, #48] @ (80052d4 ) 80052a2: 681b ldr r3, [r3, #0] 80052a4: 0a1b lsrs r3, r3, #8 80052a6: b2db uxtb r3, r3 80052a8: e010 b.n 80052cc }else if(reg_number == 2){ 80052aa: 79fb ldrb r3, [r7, #7] 80052ac: 2b02 cmp r3, #2 80052ae: d104 bne.n 80052ba return (tmp_time32>>16) & 0xFF; 80052b0: 4b08 ldr r3, [pc, #32] @ (80052d4 ) 80052b2: 681b ldr r3, [r3, #0] 80052b4: 0c1b lsrs r3, r3, #16 80052b6: b2db uxtb r3, r3 80052b8: e008 b.n 80052cc }else if(reg_number == 3){ 80052ba: 79fb ldrb r3, [r7, #7] 80052bc: 2b03 cmp r3, #3 80052be: d104 bne.n 80052ca return (tmp_time32>>24) & 0xFF; 80052c0: 4b04 ldr r3, [pc, #16] @ (80052d4 ) 80052c2: 681b ldr r3, [r3, #0] 80052c4: 0e1b lsrs r3, r3, #24 80052c6: b2db uxtb r3, r3 80052c8: e000 b.n 80052cc }else{ return 0x00; 80052ca: 2300 movs r3, #0 } }; 80052cc: 4618 mov r0, r3 80052ce: 3708 adds r7, #8 80052d0: 46bd mov sp, r7 80052d2: bd80 pop {r7, pc} 80052d4: 20003358 .word 0x20003358 080052d8 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval Time counter */ static uint32_t RTC1_ReadTimeCounter(RTC_HandleTypeDef *hrtc) { 80052d8: b480 push {r7} 80052da: b087 sub sp, #28 80052dc: af00 add r7, sp, #0 80052de: 6078 str r0, [r7, #4] uint16_t high1 = 0U, high2 = 0U, low = 0U; 80052e0: 2300 movs r3, #0 80052e2: 827b strh r3, [r7, #18] 80052e4: 2300 movs r3, #0 80052e6: 823b strh r3, [r7, #16] 80052e8: 2300 movs r3, #0 80052ea: 81fb strh r3, [r7, #14] uint32_t timecounter = 0U; 80052ec: 2300 movs r3, #0 80052ee: 617b str r3, [r7, #20] high1 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT); 80052f0: 687b ldr r3, [r7, #4] 80052f2: 681b ldr r3, [r3, #0] 80052f4: 699b ldr r3, [r3, #24] 80052f6: 827b strh r3, [r7, #18] low = READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT); 80052f8: 687b ldr r3, [r7, #4] 80052fa: 681b ldr r3, [r3, #0] 80052fc: 69db ldr r3, [r3, #28] 80052fe: 81fb strh r3, [r7, #14] high2 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT); 8005300: 687b ldr r3, [r7, #4] 8005302: 681b ldr r3, [r3, #0] 8005304: 699b ldr r3, [r3, #24] 8005306: 823b strh r3, [r7, #16] if (high1 != high2) 8005308: 8a7a ldrh r2, [r7, #18] 800530a: 8a3b ldrh r3, [r7, #16] 800530c: 429a cmp r2, r3 800530e: d008 beq.n 8005322 { /* In this case the counter roll over during reading of CNTL and CNTH registers, read again CNTL register then return the counter value */ timecounter = (((uint32_t) high2 << 16U) | READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT)); 8005310: 8a3b ldrh r3, [r7, #16] 8005312: 041a lsls r2, r3, #16 8005314: 687b ldr r3, [r7, #4] 8005316: 681b ldr r3, [r3, #0] 8005318: 69db ldr r3, [r3, #28] 800531a: b29b uxth r3, r3 800531c: 4313 orrs r3, r2 800531e: 617b str r3, [r7, #20] 8005320: e004 b.n 800532c } else { /* No counter roll over during reading of CNTL and CNTH registers, counter value is equal to first value of CNTL and CNTH */ timecounter = (((uint32_t) high1 << 16U) | low); 8005322: 8a7b ldrh r3, [r7, #18] 8005324: 041a lsls r2, r3, #16 8005326: 89fb ldrh r3, [r7, #14] 8005328: 4313 orrs r3, r2 800532a: 617b str r3, [r7, #20] } return timecounter; 800532c: 697b ldr r3, [r7, #20] } 800532e: 4618 mov r0, r3 8005330: 371c adds r7, #28 8005332: 46bd mov sp, r7 8005334: bc80 pop {r7} 8005336: 4770 bx lr 08005338 : * the configuration information for RTC. * @param TimeCounter: Counter to write in RTC_CNT registers * @retval HAL status */ static HAL_StatusTypeDef RTC1_WriteTimeCounter(RTC_HandleTypeDef *hrtc, uint32_t TimeCounter) { 8005338: b580 push {r7, lr} 800533a: b084 sub sp, #16 800533c: af00 add r7, sp, #0 800533e: 6078 str r0, [r7, #4] 8005340: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8005342: 2300 movs r3, #0 8005344: 73fb strb r3, [r7, #15] /* Set Initialization mode */ if (RTC1_EnterInitMode(hrtc) != HAL_OK) 8005346: 6878 ldr r0, [r7, #4] 8005348: f000 f81d bl 8005386 800534c: 4603 mov r3, r0 800534e: 2b00 cmp r3, #0 8005350: d002 beq.n 8005358 { status = HAL_ERROR; 8005352: 2301 movs r3, #1 8005354: 73fb strb r3, [r7, #15] 8005356: e011 b.n 800537c } else { /* Set RTC COUNTER MSB word */ WRITE_REG(hrtc->Instance->CNTH, (TimeCounter >> 16U)); 8005358: 687b ldr r3, [r7, #4] 800535a: 681b ldr r3, [r3, #0] 800535c: 683a ldr r2, [r7, #0] 800535e: 0c12 lsrs r2, r2, #16 8005360: 619a str r2, [r3, #24] /* Set RTC COUNTER LSB word */ WRITE_REG(hrtc->Instance->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT)); 8005362: 687b ldr r3, [r7, #4] 8005364: 681b ldr r3, [r3, #0] 8005366: 683a ldr r2, [r7, #0] 8005368: b292 uxth r2, r2 800536a: 61da str r2, [r3, #28] /* Wait for synchro */ if (RTC1_ExitInitMode(hrtc) != HAL_OK) 800536c: 6878 ldr r0, [r7, #4] 800536e: f000 f832 bl 80053d6 8005372: 4603 mov r3, r0 8005374: 2b00 cmp r3, #0 8005376: d001 beq.n 800537c { status = HAL_ERROR; 8005378: 2301 movs r3, #1 800537a: 73fb strb r3, [r7, #15] } } return status; 800537c: 7bfb ldrb r3, [r7, #15] } 800537e: 4618 mov r0, r3 8005380: 3710 adds r7, #16 8005382: 46bd mov sp, r7 8005384: bd80 pop {r7, pc} 08005386 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC1_EnterInitMode(RTC_HandleTypeDef *hrtc) { 8005386: b580 push {r7, lr} 8005388: b084 sub sp, #16 800538a: af00 add r7, sp, #0 800538c: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800538e: 2300 movs r3, #0 8005390: 60fb str r3, [r7, #12] tickstart = HAL_GetTick(); 8005392: f000 fa85 bl 80058a0 8005396: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8005398: e009 b.n 80053ae { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 800539a: f000 fa81 bl 80058a0 800539e: 4602 mov r2, r0 80053a0: 68fb ldr r3, [r7, #12] 80053a2: 1ad3 subs r3, r2, r3 80053a4: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 80053a8: d901 bls.n 80053ae { return HAL_TIMEOUT; 80053aa: 2303 movs r3, #3 80053ac: e00f b.n 80053ce while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 80053ae: 687b ldr r3, [r7, #4] 80053b0: 681b ldr r3, [r3, #0] 80053b2: 685b ldr r3, [r3, #4] 80053b4: f003 0320 and.w r3, r3, #32 80053b8: 2b00 cmp r3, #0 80053ba: d0ee beq.n 800539a } } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 80053bc: 687b ldr r3, [r7, #4] 80053be: 681b ldr r3, [r3, #0] 80053c0: 685a ldr r2, [r3, #4] 80053c2: 687b ldr r3, [r7, #4] 80053c4: 681b ldr r3, [r3, #0] 80053c6: f042 0210 orr.w r2, r2, #16 80053ca: 605a str r2, [r3, #4] return HAL_OK; 80053cc: 2300 movs r3, #0 } 80053ce: 4618 mov r0, r3 80053d0: 3710 adds r7, #16 80053d2: 46bd mov sp, r7 80053d4: bd80 pop {r7, pc} 080053d6 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC1_ExitInitMode(RTC_HandleTypeDef *hrtc) { 80053d6: b580 push {r7, lr} 80053d8: b084 sub sp, #16 80053da: af00 add r7, sp, #0 80053dc: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80053de: 2300 movs r3, #0 80053e0: 60fb str r3, [r7, #12] /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 80053e2: 687b ldr r3, [r7, #4] 80053e4: 681b ldr r3, [r3, #0] 80053e6: 685a ldr r2, [r3, #4] 80053e8: 687b ldr r3, [r7, #4] 80053ea: 681b ldr r3, [r3, #0] 80053ec: f022 0210 bic.w r2, r2, #16 80053f0: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 80053f2: f000 fa55 bl 80058a0 80053f6: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 80053f8: e009 b.n 800540e { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 80053fa: f000 fa51 bl 80058a0 80053fe: 4602 mov r2, r0 8005400: 68fb ldr r3, [r7, #12] 8005402: 1ad3 subs r3, r2, r3 8005404: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8005408: d901 bls.n 800540e { return HAL_TIMEOUT; 800540a: 2303 movs r3, #3 800540c: e007 b.n 800541e while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 800540e: 687b ldr r3, [r7, #4] 8005410: 681b ldr r3, [r3, #0] 8005412: 685b ldr r3, [r3, #4] 8005414: f003 0320 and.w r3, r3, #32 8005418: 2b00 cmp r3, #0 800541a: d0ee beq.n 80053fa } } return HAL_OK; 800541c: 2300 movs r3, #0 } 800541e: 4618 mov r0, r3 8005420: 3710 adds r7, #16 8005422: 46bd mov sp, r7 8005424: bd80 pop {r7, pc} ... 08005428 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8005428: b480 push {r7} 800542a: b085 sub sp, #20 800542c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 800542e: 4b15 ldr r3, [pc, #84] @ (8005484 ) 8005430: 699b ldr r3, [r3, #24] 8005432: 4a14 ldr r2, [pc, #80] @ (8005484 ) 8005434: f043 0301 orr.w r3, r3, #1 8005438: 6193 str r3, [r2, #24] 800543a: 4b12 ldr r3, [pc, #72] @ (8005484 ) 800543c: 699b ldr r3, [r3, #24] 800543e: f003 0301 and.w r3, r3, #1 8005442: 60bb str r3, [r7, #8] 8005444: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 8005446: 4b0f ldr r3, [pc, #60] @ (8005484 ) 8005448: 69db ldr r3, [r3, #28] 800544a: 4a0e ldr r2, [pc, #56] @ (8005484 ) 800544c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8005450: 61d3 str r3, [r2, #28] 8005452: 4b0c ldr r3, [pc, #48] @ (8005484 ) 8005454: 69db ldr r3, [r3, #28] 8005456: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800545a: 607b str r3, [r7, #4] 800545c: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 800545e: 4b0a ldr r3, [pc, #40] @ (8005488 ) 8005460: 685b ldr r3, [r3, #4] 8005462: 60fb str r3, [r7, #12] 8005464: 68fb ldr r3, [r7, #12] 8005466: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 800546a: 60fb str r3, [r7, #12] 800546c: 68fb ldr r3, [r7, #12] 800546e: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8005472: 60fb str r3, [r7, #12] 8005474: 4a04 ldr r2, [pc, #16] @ (8005488 ) 8005476: 68fb ldr r3, [r7, #12] 8005478: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800547a: bf00 nop 800547c: 3714 adds r7, #20 800547e: 46bd mov sp, r7 8005480: bc80 pop {r7} 8005482: 4770 bx lr 8005484: 40021000 .word 0x40021000 8005488: 40010000 .word 0x40010000 0800548c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 800548c: b480 push {r7} 800548e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8005490: bf00 nop 8005492: e7fd b.n 8005490 08005494 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8005494: b480 push {r7} 8005496: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8005498: bf00 nop 800549a: e7fd b.n 8005498 0800549c : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 800549c: b480 push {r7} 800549e: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80054a0: bf00 nop 80054a2: e7fd b.n 80054a0 080054a4 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80054a4: b480 push {r7} 80054a6: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80054a8: bf00 nop 80054aa: e7fd b.n 80054a8 080054ac : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80054ac: b480 push {r7} 80054ae: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80054b0: bf00 nop 80054b2: e7fd b.n 80054b0 080054b4 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80054b4: b480 push {r7} 80054b6: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80054b8: bf00 nop 80054ba: 46bd mov sp, r7 80054bc: bc80 pop {r7} 80054be: 4770 bx lr 080054c0 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80054c0: b480 push {r7} 80054c2: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 80054c4: bf00 nop 80054c6: 46bd mov sp, r7 80054c8: bc80 pop {r7} 80054ca: 4770 bx lr 080054cc : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 80054cc: b480 push {r7} 80054ce: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 80054d0: bf00 nop 80054d2: 46bd mov sp, r7 80054d4: bc80 pop {r7} 80054d6: 4770 bx lr 080054d8 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 80054d8: b580 push {r7, lr} 80054da: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 80054dc: f000 f9ce bl 800587c /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 80054e0: bf00 nop 80054e2: bd80 pop {r7, pc} 080054e4 : /** * @brief This function handles CAN1 RX0 interrupt. */ void CAN1_RX0_IRQHandler(void) { 80054e4: b580 push {r7, lr} 80054e6: af00 add r7, sp, #0 /* USER CODE BEGIN CAN1_RX0_IRQn 0 */ /* USER CODE END CAN1_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan1); 80054e8: 4802 ldr r0, [pc, #8] @ (80054f4 ) 80054ea: f001 fbb8 bl 8006c5e /* USER CODE BEGIN CAN1_RX0_IRQn 1 */ /* USER CODE END CAN1_RX0_IRQn 1 */ } 80054ee: bf00 nop 80054f0: bd80 pop {r7, pc} 80054f2: bf00 nop 80054f4: 20000298 .word 0x20000298 080054f8 : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 80054f8: b580 push {r7, lr} 80054fa: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 80054fc: 4802 ldr r0, [pc, #8] @ (8005508 ) 80054fe: f003 fbc1 bl 8008c84 /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 8005502: bf00 nop 8005504: bd80 pop {r7, pc} 8005506: bf00 nop 8005508: 20003364 .word 0x20003364 0800550c : /** * @brief This function handles CAN2 TX interrupt. */ void CAN2_TX_IRQHandler(void) { 800550c: b580 push {r7, lr} 800550e: af00 add r7, sp, #0 /* USER CODE BEGIN CAN2_TX_IRQn 0 */ /* USER CODE END CAN2_TX_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 8005510: 4802 ldr r0, [pc, #8] @ (800551c ) 8005512: f001 fba4 bl 8006c5e /* USER CODE BEGIN CAN2_TX_IRQn 1 */ /* USER CODE END CAN2_TX_IRQn 1 */ } 8005516: bf00 nop 8005518: bd80 pop {r7, pc} 800551a: bf00 nop 800551c: 200002c0 .word 0x200002c0 08005520 : /** * @brief This function handles CAN2 RX1 interrupt. */ void CAN2_RX1_IRQHandler(void) { 8005520: b580 push {r7, lr} 8005522: af00 add r7, sp, #0 /* USER CODE BEGIN CAN2_RX1_IRQn 0 */ /* USER CODE END CAN2_RX1_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 8005524: 4802 ldr r0, [pc, #8] @ (8005530 ) 8005526: f001 fb9a bl 8006c5e /* USER CODE BEGIN CAN2_RX1_IRQn 1 */ /* USER CODE END CAN2_RX1_IRQn 1 */ } 800552a: bf00 nop 800552c: bd80 pop {r7, pc} 800552e: bf00 nop 8005530: 200002c0 .word 0x200002c0 08005534 <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 8005534: b480 push {r7} 8005536: af00 add r7, sp, #0 return 1; 8005538: 2301 movs r3, #1 } 800553a: 4618 mov r0, r3 800553c: 46bd mov sp, r7 800553e: bc80 pop {r7} 8005540: 4770 bx lr 08005542 <_kill>: int _kill(int pid, int sig) { 8005542: b580 push {r7, lr} 8005544: b082 sub sp, #8 8005546: af00 add r7, sp, #0 8005548: 6078 str r0, [r7, #4] 800554a: 6039 str r1, [r7, #0] (void)pid; (void)sig; errno = EINVAL; 800554c: f004 ffac bl 800a4a8 <__errno> 8005550: 4603 mov r3, r0 8005552: 2216 movs r2, #22 8005554: 601a str r2, [r3, #0] return -1; 8005556: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800555a: 4618 mov r0, r3 800555c: 3708 adds r7, #8 800555e: 46bd mov sp, r7 8005560: bd80 pop {r7, pc} 08005562 <_exit>: void _exit (int status) { 8005562: b580 push {r7, lr} 8005564: b082 sub sp, #8 8005566: af00 add r7, sp, #0 8005568: 6078 str r0, [r7, #4] _kill(status, -1); 800556a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800556e: 6878 ldr r0, [r7, #4] 8005570: f7ff ffe7 bl 8005542 <_kill> while (1) {} /* Make sure we hang here */ 8005574: bf00 nop 8005576: e7fd b.n 8005574 <_exit+0x12> 08005578 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8005578: b580 push {r7, lr} 800557a: b086 sub sp, #24 800557c: af00 add r7, sp, #0 800557e: 60f8 str r0, [r7, #12] 8005580: 60b9 str r1, [r7, #8] 8005582: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8005584: 2300 movs r3, #0 8005586: 617b str r3, [r7, #20] 8005588: e00a b.n 80055a0 <_read+0x28> { *ptr++ = __io_getchar(); 800558a: f3af 8000 nop.w 800558e: 4601 mov r1, r0 8005590: 68bb ldr r3, [r7, #8] 8005592: 1c5a adds r2, r3, #1 8005594: 60ba str r2, [r7, #8] 8005596: b2ca uxtb r2, r1 8005598: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 800559a: 697b ldr r3, [r7, #20] 800559c: 3301 adds r3, #1 800559e: 617b str r3, [r7, #20] 80055a0: 697a ldr r2, [r7, #20] 80055a2: 687b ldr r3, [r7, #4] 80055a4: 429a cmp r2, r3 80055a6: dbf0 blt.n 800558a <_read+0x12> } return len; 80055a8: 687b ldr r3, [r7, #4] } 80055aa: 4618 mov r0, r3 80055ac: 3718 adds r7, #24 80055ae: 46bd mov sp, r7 80055b0: bd80 pop {r7, pc} 080055b2 <_close>: } return len; } int _close(int file) { 80055b2: b480 push {r7} 80055b4: b083 sub sp, #12 80055b6: af00 add r7, sp, #0 80055b8: 6078 str r0, [r7, #4] (void)file; return -1; 80055ba: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 80055be: 4618 mov r0, r3 80055c0: 370c adds r7, #12 80055c2: 46bd mov sp, r7 80055c4: bc80 pop {r7} 80055c6: 4770 bx lr 080055c8 <_fstat>: int _fstat(int file, struct stat *st) { 80055c8: b480 push {r7} 80055ca: b083 sub sp, #12 80055cc: af00 add r7, sp, #0 80055ce: 6078 str r0, [r7, #4] 80055d0: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 80055d2: 683b ldr r3, [r7, #0] 80055d4: f44f 5200 mov.w r2, #8192 @ 0x2000 80055d8: 605a str r2, [r3, #4] return 0; 80055da: 2300 movs r3, #0 } 80055dc: 4618 mov r0, r3 80055de: 370c adds r7, #12 80055e0: 46bd mov sp, r7 80055e2: bc80 pop {r7} 80055e4: 4770 bx lr 080055e6 <_isatty>: int _isatty(int file) { 80055e6: b480 push {r7} 80055e8: b083 sub sp, #12 80055ea: af00 add r7, sp, #0 80055ec: 6078 str r0, [r7, #4] (void)file; return 1; 80055ee: 2301 movs r3, #1 } 80055f0: 4618 mov r0, r3 80055f2: 370c adds r7, #12 80055f4: 46bd mov sp, r7 80055f6: bc80 pop {r7} 80055f8: 4770 bx lr 080055fa <_lseek>: int _lseek(int file, int ptr, int dir) { 80055fa: b480 push {r7} 80055fc: b085 sub sp, #20 80055fe: af00 add r7, sp, #0 8005600: 60f8 str r0, [r7, #12] 8005602: 60b9 str r1, [r7, #8] 8005604: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 8005606: 2300 movs r3, #0 } 8005608: 4618 mov r0, r3 800560a: 3714 adds r7, #20 800560c: 46bd mov sp, r7 800560e: bc80 pop {r7} 8005610: 4770 bx lr ... 08005614 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8005614: b580 push {r7, lr} 8005616: b086 sub sp, #24 8005618: af00 add r7, sp, #0 800561a: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 800561c: 4a14 ldr r2, [pc, #80] @ (8005670 <_sbrk+0x5c>) 800561e: 4b15 ldr r3, [pc, #84] @ (8005674 <_sbrk+0x60>) 8005620: 1ad3 subs r3, r2, r3 8005622: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8005624: 697b ldr r3, [r7, #20] 8005626: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 8005628: 4b13 ldr r3, [pc, #76] @ (8005678 <_sbrk+0x64>) 800562a: 681b ldr r3, [r3, #0] 800562c: 2b00 cmp r3, #0 800562e: d102 bne.n 8005636 <_sbrk+0x22> { __sbrk_heap_end = &_end; 8005630: 4b11 ldr r3, [pc, #68] @ (8005678 <_sbrk+0x64>) 8005632: 4a12 ldr r2, [pc, #72] @ (800567c <_sbrk+0x68>) 8005634: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 8005636: 4b10 ldr r3, [pc, #64] @ (8005678 <_sbrk+0x64>) 8005638: 681a ldr r2, [r3, #0] 800563a: 687b ldr r3, [r7, #4] 800563c: 4413 add r3, r2 800563e: 693a ldr r2, [r7, #16] 8005640: 429a cmp r2, r3 8005642: d207 bcs.n 8005654 <_sbrk+0x40> { errno = ENOMEM; 8005644: f004 ff30 bl 800a4a8 <__errno> 8005648: 4603 mov r3, r0 800564a: 220c movs r2, #12 800564c: 601a str r2, [r3, #0] return (void *)-1; 800564e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8005652: e009 b.n 8005668 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 8005654: 4b08 ldr r3, [pc, #32] @ (8005678 <_sbrk+0x64>) 8005656: 681b ldr r3, [r3, #0] 8005658: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 800565a: 4b07 ldr r3, [pc, #28] @ (8005678 <_sbrk+0x64>) 800565c: 681a ldr r2, [r3, #0] 800565e: 687b ldr r3, [r7, #4] 8005660: 4413 add r3, r2 8005662: 4a05 ldr r2, [pc, #20] @ (8005678 <_sbrk+0x64>) 8005664: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 8005666: 68fb ldr r3, [r7, #12] } 8005668: 4618 mov r0, r3 800566a: 3718 adds r7, #24 800566c: 46bd mov sp, r7 800566e: bd80 pop {r7, pc} 8005670: 20010000 .word 0x20010000 8005674: 00000400 .word 0x00000400 8005678: 20003360 .word 0x20003360 800567c: 20003520 .word 0x20003520 08005680 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8005680: b480 push {r7} 8005682: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 8005684: bf00 nop 8005686: 46bd mov sp, r7 8005688: bc80 pop {r7} 800568a: 4770 bx lr 0800568c : UART_HandleTypeDef huart2; /* USART2 init function */ void MX_USART2_UART_Init(void) { 800568c: b580 push {r7, lr} 800568e: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 8005690: 4b11 ldr r3, [pc, #68] @ (80056d8 ) 8005692: 4a12 ldr r2, [pc, #72] @ (80056dc ) 8005694: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 8005696: 4b10 ldr r3, [pc, #64] @ (80056d8 ) 8005698: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800569c: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 800569e: 4b0e ldr r3, [pc, #56] @ (80056d8 ) 80056a0: 2200 movs r2, #0 80056a2: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 80056a4: 4b0c ldr r3, [pc, #48] @ (80056d8 ) 80056a6: 2200 movs r2, #0 80056a8: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 80056aa: 4b0b ldr r3, [pc, #44] @ (80056d8 ) 80056ac: 2200 movs r2, #0 80056ae: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 80056b0: 4b09 ldr r3, [pc, #36] @ (80056d8 ) 80056b2: 220c movs r2, #12 80056b4: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80056b6: 4b08 ldr r3, [pc, #32] @ (80056d8 ) 80056b8: 2200 movs r2, #0 80056ba: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 80056bc: 4b06 ldr r3, [pc, #24] @ (80056d8 ) 80056be: 2200 movs r2, #0 80056c0: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 80056c2: 4805 ldr r0, [pc, #20] @ (80056d8 ) 80056c4: f003 f9af bl 8008a26 80056c8: 4603 mov r3, r0 80056ca: 2b00 cmp r3, #0 80056cc: d001 beq.n 80056d2 { Error_Handler(); 80056ce: f7ff fcbb bl 8005048 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 80056d2: bf00 nop 80056d4: bd80 pop {r7, pc} 80056d6: bf00 nop 80056d8: 20003364 .word 0x20003364 80056dc: 40004400 .word 0x40004400 080056e0 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 80056e0: b580 push {r7, lr} 80056e2: b08a sub sp, #40 @ 0x28 80056e4: af00 add r7, sp, #0 80056e6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80056e8: f107 0314 add.w r3, r7, #20 80056ec: 2200 movs r2, #0 80056ee: 601a str r2, [r3, #0] 80056f0: 605a str r2, [r3, #4] 80056f2: 609a str r2, [r3, #8] 80056f4: 60da str r2, [r3, #12] if(uartHandle->Instance==USART2) 80056f6: 687b ldr r3, [r7, #4] 80056f8: 681b ldr r3, [r3, #0] 80056fa: 4a26 ldr r2, [pc, #152] @ (8005794 ) 80056fc: 4293 cmp r3, r2 80056fe: d145 bne.n 800578c { /* USER CODE BEGIN USART2_MspInit 0 */ /* USER CODE END USART2_MspInit 0 */ /* USART2 clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); 8005700: 4b25 ldr r3, [pc, #148] @ (8005798 ) 8005702: 69db ldr r3, [r3, #28] 8005704: 4a24 ldr r2, [pc, #144] @ (8005798 ) 8005706: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800570a: 61d3 str r3, [r2, #28] 800570c: 4b22 ldr r3, [pc, #136] @ (8005798 ) 800570e: 69db ldr r3, [r3, #28] 8005710: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005714: 613b str r3, [r7, #16] 8005716: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOD_CLK_ENABLE(); 8005718: 4b1f ldr r3, [pc, #124] @ (8005798 ) 800571a: 699b ldr r3, [r3, #24] 800571c: 4a1e ldr r2, [pc, #120] @ (8005798 ) 800571e: f043 0320 orr.w r3, r3, #32 8005722: 6193 str r3, [r2, #24] 8005724: 4b1c ldr r3, [pc, #112] @ (8005798 ) 8005726: 699b ldr r3, [r3, #24] 8005728: f003 0320 and.w r3, r3, #32 800572c: 60fb str r3, [r7, #12] 800572e: 68fb ldr r3, [r7, #12] /**USART2 GPIO Configuration PD5 ------> USART2_TX PD6 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_5; 8005730: 2320 movs r3, #32 8005732: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8005734: 2302 movs r3, #2 8005736: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8005738: 2303 movs r3, #3 800573a: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800573c: f107 0314 add.w r3, r7, #20 8005740: 4619 mov r1, r3 8005742: 4816 ldr r0, [pc, #88] @ (800579c ) 8005744: f001 feda bl 80074fc GPIO_InitStruct.Pin = GPIO_PIN_6; 8005748: 2340 movs r3, #64 @ 0x40 800574a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800574c: 2300 movs r3, #0 800574e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005750: 2300 movs r3, #0 8005752: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8005754: f107 0314 add.w r3, r7, #20 8005758: 4619 mov r1, r3 800575a: 4810 ldr r0, [pc, #64] @ (800579c ) 800575c: f001 fece bl 80074fc __HAL_AFIO_REMAP_USART2_ENABLE(); 8005760: 4b0f ldr r3, [pc, #60] @ (80057a0 ) 8005762: 685b ldr r3, [r3, #4] 8005764: 627b str r3, [r7, #36] @ 0x24 8005766: 6a7b ldr r3, [r7, #36] @ 0x24 8005768: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800576c: 627b str r3, [r7, #36] @ 0x24 800576e: 6a7b ldr r3, [r7, #36] @ 0x24 8005770: f043 0308 orr.w r3, r3, #8 8005774: 627b str r3, [r7, #36] @ 0x24 8005776: 4a0a ldr r2, [pc, #40] @ (80057a0 ) 8005778: 6a7b ldr r3, [r7, #36] @ 0x24 800577a: 6053 str r3, [r2, #4] /* USART2 interrupt Init */ HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); 800577c: 2200 movs r2, #0 800577e: 2100 movs r1, #0 8005780: 2026 movs r0, #38 @ 0x26 8005782: f001 fd42 bl 800720a HAL_NVIC_EnableIRQ(USART2_IRQn); 8005786: 2026 movs r0, #38 @ 0x26 8005788: f001 fd5b bl 8007242 /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 800578c: bf00 nop 800578e: 3728 adds r7, #40 @ 0x28 8005790: 46bd mov sp, r7 8005792: bd80 pop {r7, pc} 8005794: 40004400 .word 0x40004400 8005798: 40021000 .word 0x40021000 800579c: 40011400 .word 0x40011400 80057a0: 40010000 .word 0x40010000 080057a4 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 80057a4: f7ff ff6c bl 8005680 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80057a8: 480b ldr r0, [pc, #44] @ (80057d8 ) ldr r1, =_edata 80057aa: 490c ldr r1, [pc, #48] @ (80057dc ) ldr r2, =_sidata 80057ac: 4a0c ldr r2, [pc, #48] @ (80057e0 ) movs r3, #0 80057ae: 2300 movs r3, #0 b LoopCopyDataInit 80057b0: e002 b.n 80057b8 080057b2 : CopyDataInit: ldr r4, [r2, r3] 80057b2: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80057b4: 50c4 str r4, [r0, r3] adds r3, r3, #4 80057b6: 3304 adds r3, #4 080057b8 : LoopCopyDataInit: adds r4, r0, r3 80057b8: 18c4 adds r4, r0, r3 cmp r4, r1 80057ba: 428c cmp r4, r1 bcc CopyDataInit 80057bc: d3f9 bcc.n 80057b2 /* Zero fill the bss segment. */ ldr r2, =_sbss 80057be: 4a09 ldr r2, [pc, #36] @ (80057e4 ) ldr r4, =_ebss 80057c0: 4c09 ldr r4, [pc, #36] @ (80057e8 ) movs r3, #0 80057c2: 2300 movs r3, #0 b LoopFillZerobss 80057c4: e001 b.n 80057ca 080057c6 : FillZerobss: str r3, [r2] 80057c6: 6013 str r3, [r2, #0] adds r2, r2, #4 80057c8: 3204 adds r2, #4 080057ca : LoopFillZerobss: cmp r2, r4 80057ca: 42a2 cmp r2, r4 bcc FillZerobss 80057cc: d3fb bcc.n 80057c6 /* Call static constructors */ bl __libc_init_array 80057ce: f004 fe71 bl 800a4b4 <__libc_init_array> /* Call the application's entry point.*/ bl main 80057d2: f7ff fb81 bl 8004ed8
bx lr 80057d6: 4770 bx lr ldr r0, =_sdata 80057d8: 20000000 .word 0x20000000 ldr r1, =_edata 80057dc: 2000024c .word 0x2000024c ldr r2, =_sidata 80057e0: 0800e4b4 .word 0x0800e4b4 ldr r2, =_sbss 80057e4: 2000024c .word 0x2000024c ldr r4, =_ebss 80057e8: 2000351c .word 0x2000351c 080057ec : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80057ec: e7fe b.n 80057ec ... 080057f0 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80057f0: b580 push {r7, lr} 80057f2: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80057f4: 4b08 ldr r3, [pc, #32] @ (8005818 ) 80057f6: 681b ldr r3, [r3, #0] 80057f8: 4a07 ldr r2, [pc, #28] @ (8005818 ) 80057fa: f043 0310 orr.w r3, r3, #16 80057fe: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8005800: 2003 movs r0, #3 8005802: f001 fcf7 bl 80071f4 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8005806: 200f movs r0, #15 8005808: f000 f808 bl 800581c /* Init the low level hardware */ HAL_MspInit(); 800580c: f7ff fe0c bl 8005428 /* Return function status */ return HAL_OK; 8005810: 2300 movs r3, #0 } 8005812: 4618 mov r0, r3 8005814: bd80 pop {r7, pc} 8005816: bf00 nop 8005818: 40022000 .word 0x40022000 0800581c : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800581c: b580 push {r7, lr} 800581e: b082 sub sp, #8 8005820: af00 add r7, sp, #0 8005822: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8005824: 4b12 ldr r3, [pc, #72] @ (8005870 ) 8005826: 681a ldr r2, [r3, #0] 8005828: 4b12 ldr r3, [pc, #72] @ (8005874 ) 800582a: 781b ldrb r3, [r3, #0] 800582c: 4619 mov r1, r3 800582e: f44f 737a mov.w r3, #1000 @ 0x3e8 8005832: fbb3 f3f1 udiv r3, r3, r1 8005836: fbb2 f3f3 udiv r3, r2, r3 800583a: 4618 mov r0, r3 800583c: f001 fd0f bl 800725e 8005840: 4603 mov r3, r0 8005842: 2b00 cmp r3, #0 8005844: d001 beq.n 800584a { return HAL_ERROR; 8005846: 2301 movs r3, #1 8005848: e00e b.n 8005868 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800584a: 687b ldr r3, [r7, #4] 800584c: 2b0f cmp r3, #15 800584e: d80a bhi.n 8005866 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8005850: 2200 movs r2, #0 8005852: 6879 ldr r1, [r7, #4] 8005854: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8005858: f001 fcd7 bl 800720a uwTickPrio = TickPriority; 800585c: 4a06 ldr r2, [pc, #24] @ (8005878 ) 800585e: 687b ldr r3, [r7, #4] 8005860: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8005862: 2300 movs r3, #0 8005864: e000 b.n 8005868 return HAL_ERROR; 8005866: 2301 movs r3, #1 } 8005868: 4618 mov r0, r3 800586a: 3708 adds r7, #8 800586c: 46bd mov sp, r7 800586e: bd80 pop {r7, pc} 8005870: 20000018 .word 0x20000018 8005874: 20000020 .word 0x20000020 8005878: 2000001c .word 0x2000001c 0800587c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800587c: b480 push {r7} 800587e: af00 add r7, sp, #0 uwTick += uwTickFreq; 8005880: 4b05 ldr r3, [pc, #20] @ (8005898 ) 8005882: 781b ldrb r3, [r3, #0] 8005884: 461a mov r2, r3 8005886: 4b05 ldr r3, [pc, #20] @ (800589c ) 8005888: 681b ldr r3, [r3, #0] 800588a: 4413 add r3, r2 800588c: 4a03 ldr r2, [pc, #12] @ (800589c ) 800588e: 6013 str r3, [r2, #0] } 8005890: bf00 nop 8005892: 46bd mov sp, r7 8005894: bc80 pop {r7} 8005896: 4770 bx lr 8005898: 20000020 .word 0x20000020 800589c: 200033a8 .word 0x200033a8 080058a0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80058a0: b480 push {r7} 80058a2: af00 add r7, sp, #0 return uwTick; 80058a4: 4b02 ldr r3, [pc, #8] @ (80058b0 ) 80058a6: 681b ldr r3, [r3, #0] } 80058a8: 4618 mov r0, r3 80058aa: 46bd mov sp, r7 80058ac: bc80 pop {r7} 80058ae: 4770 bx lr 80058b0: 200033a8 .word 0x200033a8 080058b4 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80058b4: b580 push {r7, lr} 80058b6: b084 sub sp, #16 80058b8: af00 add r7, sp, #0 80058ba: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 80058bc: f7ff fff0 bl 80058a0 80058c0: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 80058c2: 687b ldr r3, [r7, #4] 80058c4: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80058c6: 68fb ldr r3, [r7, #12] 80058c8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80058cc: d005 beq.n 80058da { wait += (uint32_t)(uwTickFreq); 80058ce: 4b0a ldr r3, [pc, #40] @ (80058f8 ) 80058d0: 781b ldrb r3, [r3, #0] 80058d2: 461a mov r2, r3 80058d4: 68fb ldr r3, [r7, #12] 80058d6: 4413 add r3, r2 80058d8: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 80058da: bf00 nop 80058dc: f7ff ffe0 bl 80058a0 80058e0: 4602 mov r2, r0 80058e2: 68bb ldr r3, [r7, #8] 80058e4: 1ad3 subs r3, r2, r3 80058e6: 68fa ldr r2, [r7, #12] 80058e8: 429a cmp r2, r3 80058ea: d8f7 bhi.n 80058dc { } } 80058ec: bf00 nop 80058ee: bf00 nop 80058f0: 3710 adds r7, #16 80058f2: 46bd mov sp, r7 80058f4: bd80 pop {r7, pc} 80058f6: bf00 nop 80058f8: 20000020 .word 0x20000020 080058fc : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 80058fc: b580 push {r7, lr} 80058fe: b086 sub sp, #24 8005900: af00 add r7, sp, #0 8005902: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8005904: 2300 movs r3, #0 8005906: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 8005908: 2300 movs r3, #0 800590a: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 800590c: 2300 movs r3, #0 800590e: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 8005910: 2300 movs r3, #0 8005912: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 8005914: 687b ldr r3, [r7, #4] 8005916: 2b00 cmp r3, #0 8005918: d101 bne.n 800591e { return HAL_ERROR; 800591a: 2301 movs r3, #1 800591c: e0be b.n 8005a9c assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 800591e: 687b ldr r3, [r7, #4] 8005920: 689b ldr r3, [r3, #8] 8005922: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8005924: 687b ldr r3, [r7, #4] 8005926: 6a9b ldr r3, [r3, #40] @ 0x28 8005928: 2b00 cmp r3, #0 800592a: d109 bne.n 8005940 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 800592c: 687b ldr r3, [r7, #4] 800592e: 2200 movs r2, #0 8005930: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8005932: 687b ldr r3, [r7, #4] 8005934: 2200 movs r2, #0 8005936: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800593a: 6878 ldr r0, [r7, #4] 800593c: f7fb fe8c bl 8001658 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8005940: 6878 ldr r0, [r7, #4] 8005942: f000 fbf1 bl 8006128 8005946: 4603 mov r3, r0 8005948: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 800594a: 687b ldr r3, [r7, #4] 800594c: 6a9b ldr r3, [r3, #40] @ 0x28 800594e: f003 0310 and.w r3, r3, #16 8005952: 2b00 cmp r3, #0 8005954: f040 8099 bne.w 8005a8a 8005958: 7dfb ldrb r3, [r7, #23] 800595a: 2b00 cmp r3, #0 800595c: f040 8095 bne.w 8005a8a (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8005960: 687b ldr r3, [r7, #4] 8005962: 6a9b ldr r3, [r3, #40] @ 0x28 8005964: f423 5388 bic.w r3, r3, #4352 @ 0x1100 8005968: f023 0302 bic.w r3, r3, #2 800596c: f043 0202 orr.w r2, r3, #2 8005970: 687b ldr r3, [r7, #4] 8005972: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 8005974: 687b ldr r3, [r7, #4] 8005976: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8005978: 687b ldr r3, [r7, #4] 800597a: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 800597c: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 800597e: 687b ldr r3, [r7, #4] 8005980: 7b1b ldrb r3, [r3, #12] 8005982: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8005984: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 8005986: 68ba ldr r2, [r7, #8] 8005988: 4313 orrs r3, r2 800598a: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 800598c: 687b ldr r3, [r7, #4] 800598e: 689b ldr r3, [r3, #8] 8005990: f5b3 7f80 cmp.w r3, #256 @ 0x100 8005994: d003 beq.n 800599e 8005996: 687b ldr r3, [r7, #4] 8005998: 689b ldr r3, [r3, #8] 800599a: 2b01 cmp r3, #1 800599c: d102 bne.n 80059a4 800599e: f44f 7380 mov.w r3, #256 @ 0x100 80059a2: e000 b.n 80059a6 80059a4: 2300 movs r3, #0 80059a6: 693a ldr r2, [r7, #16] 80059a8: 4313 orrs r3, r2 80059aa: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 80059ac: 687b ldr r3, [r7, #4] 80059ae: 7d1b ldrb r3, [r3, #20] 80059b0: 2b01 cmp r3, #1 80059b2: d119 bne.n 80059e8 { if (hadc->Init.ContinuousConvMode == DISABLE) 80059b4: 687b ldr r3, [r7, #4] 80059b6: 7b1b ldrb r3, [r3, #12] 80059b8: 2b00 cmp r3, #0 80059ba: d109 bne.n 80059d0 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 80059bc: 687b ldr r3, [r7, #4] 80059be: 699b ldr r3, [r3, #24] 80059c0: 3b01 subs r3, #1 80059c2: 035a lsls r2, r3, #13 80059c4: 693b ldr r3, [r7, #16] 80059c6: 4313 orrs r3, r2 80059c8: f443 6300 orr.w r3, r3, #2048 @ 0x800 80059cc: 613b str r3, [r7, #16] 80059ce: e00b b.n 80059e8 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80059d0: 687b ldr r3, [r7, #4] 80059d2: 6a9b ldr r3, [r3, #40] @ 0x28 80059d4: f043 0220 orr.w r2, r3, #32 80059d8: 687b ldr r3, [r7, #4] 80059da: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80059dc: 687b ldr r3, [r7, #4] 80059de: 6adb ldr r3, [r3, #44] @ 0x2c 80059e0: f043 0201 orr.w r2, r3, #1 80059e4: 687b ldr r3, [r7, #4] 80059e6: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 80059e8: 687b ldr r3, [r7, #4] 80059ea: 681b ldr r3, [r3, #0] 80059ec: 685b ldr r3, [r3, #4] 80059ee: f423 4169 bic.w r1, r3, #59648 @ 0xe900 80059f2: 687b ldr r3, [r7, #4] 80059f4: 681b ldr r3, [r3, #0] 80059f6: 693a ldr r2, [r7, #16] 80059f8: 430a orrs r2, r1 80059fa: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 80059fc: 687b ldr r3, [r7, #4] 80059fe: 681b ldr r3, [r3, #0] 8005a00: 689a ldr r2, [r3, #8] 8005a02: 4b28 ldr r3, [pc, #160] @ (8005aa4 ) 8005a04: 4013 ands r3, r2 8005a06: 687a ldr r2, [r7, #4] 8005a08: 6812 ldr r2, [r2, #0] 8005a0a: 68b9 ldr r1, [r7, #8] 8005a0c: 430b orrs r3, r1 8005a0e: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 8005a10: 687b ldr r3, [r7, #4] 8005a12: 689b ldr r3, [r3, #8] 8005a14: f5b3 7f80 cmp.w r3, #256 @ 0x100 8005a18: d003 beq.n 8005a22 8005a1a: 687b ldr r3, [r7, #4] 8005a1c: 689b ldr r3, [r3, #8] 8005a1e: 2b01 cmp r3, #1 8005a20: d104 bne.n 8005a2c { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 8005a22: 687b ldr r3, [r7, #4] 8005a24: 691b ldr r3, [r3, #16] 8005a26: 3b01 subs r3, #1 8005a28: 051b lsls r3, r3, #20 8005a2a: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 8005a2c: 687b ldr r3, [r7, #4] 8005a2e: 681b ldr r3, [r3, #0] 8005a30: 6adb ldr r3, [r3, #44] @ 0x2c 8005a32: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 8005a36: 687b ldr r3, [r7, #4] 8005a38: 681b ldr r3, [r3, #0] 8005a3a: 68fa ldr r2, [r7, #12] 8005a3c: 430a orrs r2, r1 8005a3e: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8005a40: 687b ldr r3, [r7, #4] 8005a42: 681b ldr r3, [r3, #0] 8005a44: 689a ldr r2, [r3, #8] 8005a46: 4b18 ldr r3, [pc, #96] @ (8005aa8 ) 8005a48: 4013 ands r3, r2 8005a4a: 68ba ldr r2, [r7, #8] 8005a4c: 429a cmp r2, r3 8005a4e: d10b bne.n 8005a68 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8005a50: 687b ldr r3, [r7, #4] 8005a52: 2200 movs r2, #0 8005a54: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 8005a56: 687b ldr r3, [r7, #4] 8005a58: 6a9b ldr r3, [r3, #40] @ 0x28 8005a5a: f023 0303 bic.w r3, r3, #3 8005a5e: f043 0201 orr.w r2, r3, #1 8005a62: 687b ldr r3, [r7, #4] 8005a64: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8005a66: e018 b.n 8005a9a HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8005a68: 687b ldr r3, [r7, #4] 8005a6a: 6a9b ldr r3, [r3, #40] @ 0x28 8005a6c: f023 0312 bic.w r3, r3, #18 8005a70: f043 0210 orr.w r2, r3, #16 8005a74: 687b ldr r3, [r7, #4] 8005a76: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8005a78: 687b ldr r3, [r7, #4] 8005a7a: 6adb ldr r3, [r3, #44] @ 0x2c 8005a7c: f043 0201 orr.w r2, r3, #1 8005a80: 687b ldr r3, [r7, #4] 8005a82: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 8005a84: 2301 movs r3, #1 8005a86: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8005a88: e007 b.n 8005a9a } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8005a8a: 687b ldr r3, [r7, #4] 8005a8c: 6a9b ldr r3, [r3, #40] @ 0x28 8005a8e: f043 0210 orr.w r2, r3, #16 8005a92: 687b ldr r3, [r7, #4] 8005a94: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 8005a96: 2301 movs r3, #1 8005a98: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 8005a9a: 7dfb ldrb r3, [r7, #23] } 8005a9c: 4618 mov r0, r3 8005a9e: 3718 adds r7, #24 8005aa0: 46bd mov sp, r7 8005aa2: bd80 pop {r7, pc} 8005aa4: ffe1f7fd .word 0xffe1f7fd 8005aa8: ff1f0efe .word 0xff1f0efe 08005aac : * Interruptions enabled in this function: None. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { 8005aac: b580 push {r7, lr} 8005aae: b084 sub sp, #16 8005ab0: af00 add r7, sp, #0 8005ab2: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8005ab4: 2300 movs r3, #0 8005ab6: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 8005ab8: 687b ldr r3, [r7, #4] 8005aba: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 8005abe: 2b01 cmp r3, #1 8005ac0: d101 bne.n 8005ac6 8005ac2: 2302 movs r3, #2 8005ac4: e098 b.n 8005bf8 8005ac6: 687b ldr r3, [r7, #4] 8005ac8: 2201 movs r2, #1 8005aca: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8005ace: 6878 ldr r0, [r7, #4] 8005ad0: f000 fad0 bl 8006074 8005ad4: 4603 mov r3, r0 8005ad6: 73fb strb r3, [r7, #15] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8005ad8: 7bfb ldrb r3, [r7, #15] 8005ada: 2b00 cmp r3, #0 8005adc: f040 8087 bne.w 8005bee { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8005ae0: 687b ldr r3, [r7, #4] 8005ae2: 6a9b ldr r3, [r3, #40] @ 0x28 8005ae4: f423 7340 bic.w r3, r3, #768 @ 0x300 8005ae8: f023 0301 bic.w r3, r3, #1 8005aec: f443 7280 orr.w r2, r3, #256 @ 0x100 8005af0: 687b ldr r3, [r7, #4] 8005af2: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 8005af4: 687b ldr r3, [r7, #4] 8005af6: 681b ldr r3, [r3, #0] 8005af8: 4a41 ldr r2, [pc, #260] @ (8005c00 ) 8005afa: 4293 cmp r3, r2 8005afc: d105 bne.n 8005b0a 8005afe: 4b41 ldr r3, [pc, #260] @ (8005c04 ) 8005b00: 685b ldr r3, [r3, #4] 8005b02: f403 2370 and.w r3, r3, #983040 @ 0xf0000 8005b06: 2b00 cmp r3, #0 8005b08: d115 bne.n 8005b36 { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8005b0a: 687b ldr r3, [r7, #4] 8005b0c: 6a9b ldr r3, [r3, #40] @ 0x28 8005b0e: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 8005b12: 687b ldr r3, [r7, #4] 8005b14: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 8005b16: 687b ldr r3, [r7, #4] 8005b18: 681b ldr r3, [r3, #0] 8005b1a: 685b ldr r3, [r3, #4] 8005b1c: f403 6380 and.w r3, r3, #1024 @ 0x400 8005b20: 2b00 cmp r3, #0 8005b22: d026 beq.n 8005b72 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8005b24: 687b ldr r3, [r7, #4] 8005b26: 6a9b ldr r3, [r3, #40] @ 0x28 8005b28: f423 5340 bic.w r3, r3, #12288 @ 0x3000 8005b2c: f443 5280 orr.w r2, r3, #4096 @ 0x1000 8005b30: 687b ldr r3, [r7, #4] 8005b32: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 8005b34: e01d b.n 8005b72 } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8005b36: 687b ldr r3, [r7, #4] 8005b38: 6a9b ldr r3, [r3, #40] @ 0x28 8005b3a: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 8005b3e: 687b ldr r3, [r7, #4] 8005b40: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 8005b42: 687b ldr r3, [r7, #4] 8005b44: 681b ldr r3, [r3, #0] 8005b46: 4a2f ldr r2, [pc, #188] @ (8005c04 ) 8005b48: 4293 cmp r3, r2 8005b4a: d004 beq.n 8005b56 8005b4c: 687b ldr r3, [r7, #4] 8005b4e: 681b ldr r3, [r3, #0] 8005b50: 4a2b ldr r2, [pc, #172] @ (8005c00 ) 8005b52: 4293 cmp r3, r2 8005b54: d10d bne.n 8005b72 8005b56: 4b2b ldr r3, [pc, #172] @ (8005c04 ) 8005b58: 685b ldr r3, [r3, #4] 8005b5a: f403 6380 and.w r3, r3, #1024 @ 0x400 8005b5e: 2b00 cmp r3, #0 8005b60: d007 beq.n 8005b72 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8005b62: 687b ldr r3, [r7, #4] 8005b64: 6a9b ldr r3, [r3, #40] @ 0x28 8005b66: f423 5340 bic.w r3, r3, #12288 @ 0x3000 8005b6a: f443 5280 orr.w r2, r3, #4096 @ 0x1000 8005b6e: 687b ldr r3, [r7, #4] 8005b70: 629a str r2, [r3, #40] @ 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8005b72: 687b ldr r3, [r7, #4] 8005b74: 6a9b ldr r3, [r3, #40] @ 0x28 8005b76: f403 5380 and.w r3, r3, #4096 @ 0x1000 8005b7a: 2b00 cmp r3, #0 8005b7c: d006 beq.n 8005b8c { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8005b7e: 687b ldr r3, [r7, #4] 8005b80: 6adb ldr r3, [r3, #44] @ 0x2c 8005b82: f023 0206 bic.w r2, r3, #6 8005b86: 687b ldr r3, [r7, #4] 8005b88: 62da str r2, [r3, #44] @ 0x2c 8005b8a: e002 b.n 8005b92 } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8005b8c: 687b ldr r3, [r7, #4] 8005b8e: 2200 movs r2, #0 8005b90: 62da str r2, [r3, #44] @ 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8005b92: 687b ldr r3, [r7, #4] 8005b94: 2200 movs r2, #0 8005b96: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Clear regular group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 8005b9a: 687b ldr r3, [r7, #4] 8005b9c: 681b ldr r3, [r3, #0] 8005b9e: f06f 0202 mvn.w r2, #2 8005ba2: 601a str r2, [r3, #0] /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ /* If ADC is master, ADC is enabled and conversion is started. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8005ba4: 687b ldr r3, [r7, #4] 8005ba6: 681b ldr r3, [r3, #0] 8005ba8: 689b ldr r3, [r3, #8] 8005baa: f403 2360 and.w r3, r3, #917504 @ 0xe0000 8005bae: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 8005bb2: d113 bne.n 8005bdc ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 8005bb4: 687b ldr r3, [r7, #4] 8005bb6: 681b ldr r3, [r3, #0] if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8005bb8: 4a11 ldr r2, [pc, #68] @ (8005c00 ) 8005bba: 4293 cmp r3, r2 8005bbc: d105 bne.n 8005bca ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 8005bbe: 4b11 ldr r3, [pc, #68] @ (8005c04 ) 8005bc0: 685b ldr r3, [r3, #4] 8005bc2: f403 2370 and.w r3, r3, #983040 @ 0xf0000 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8005bc6: 2b00 cmp r3, #0 8005bc8: d108 bne.n 8005bdc { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 8005bca: 687b ldr r3, [r7, #4] 8005bcc: 681b ldr r3, [r3, #0] 8005bce: 689a ldr r2, [r3, #8] 8005bd0: 687b ldr r3, [r7, #4] 8005bd2: 681b ldr r3, [r3, #0] 8005bd4: f442 02a0 orr.w r2, r2, #5242880 @ 0x500000 8005bd8: 609a str r2, [r3, #8] 8005bda: e00c b.n 8005bf6 } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 8005bdc: 687b ldr r3, [r7, #4] 8005bde: 681b ldr r3, [r3, #0] 8005be0: 689a ldr r2, [r3, #8] 8005be2: 687b ldr r3, [r7, #4] 8005be4: 681b ldr r3, [r3, #0] 8005be6: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 8005bea: 609a str r2, [r3, #8] 8005bec: e003 b.n 8005bf6 } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 8005bee: 687b ldr r3, [r7, #4] 8005bf0: 2200 movs r2, #0 8005bf2: f883 2024 strb.w r2, [r3, #36] @ 0x24 } /* Return function status */ return tmp_hal_status; 8005bf6: 7bfb ldrb r3, [r7, #15] } 8005bf8: 4618 mov r0, r3 8005bfa: 3710 adds r7, #16 8005bfc: 46bd mov sp, r7 8005bfe: bd80 pop {r7, pc} 8005c00: 40012800 .word 0x40012800 8005c04: 40012400 .word 0x40012400 08005c08 : * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { 8005c08: b580 push {r7, lr} 8005c0a: b084 sub sp, #16 8005c0c: af00 add r7, sp, #0 8005c0e: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8005c10: 2300 movs r3, #0 8005c12: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 8005c14: 687b ldr r3, [r7, #4] 8005c16: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 8005c1a: 2b01 cmp r3, #1 8005c1c: d101 bne.n 8005c22 8005c1e: 2302 movs r3, #2 8005c20: e01a b.n 8005c58 8005c22: 687b ldr r3, [r7, #4] 8005c24: 2201 movs r2, #1 8005c26: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8005c2a: 6878 ldr r0, [r7, #4] 8005c2c: f000 fa7c bl 8006128 8005c30: 4603 mov r3, r0 8005c32: 73fb strb r3, [r7, #15] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8005c34: 7bfb ldrb r3, [r7, #15] 8005c36: 2b00 cmp r3, #0 8005c38: d109 bne.n 8005c4e { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8005c3a: 687b ldr r3, [r7, #4] 8005c3c: 6a9b ldr r3, [r3, #40] @ 0x28 8005c3e: f423 5388 bic.w r3, r3, #4352 @ 0x1100 8005c42: f023 0301 bic.w r3, r3, #1 8005c46: f043 0201 orr.w r2, r3, #1 8005c4a: 687b ldr r3, [r7, #4] 8005c4c: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 8005c4e: 687b ldr r3, [r7, #4] 8005c50: 2200 movs r2, #0 8005c52: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 8005c56: 7bfb ldrb r3, [r7, #15] } 8005c58: 4618 mov r0, r3 8005c5a: 3710 adds r7, #16 8005c5c: 46bd mov sp, r7 8005c5e: bd80 pop {r7, pc} 08005c60 : * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { 8005c60: b590 push {r4, r7, lr} 8005c62: b087 sub sp, #28 8005c64: af00 add r7, sp, #0 8005c66: 6078 str r0, [r7, #4] 8005c68: 6039 str r1, [r7, #0] uint32_t tickstart = 0U; 8005c6a: 2300 movs r3, #0 8005c6c: 617b str r3, [r7, #20] /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; 8005c6e: 2300 movs r3, #0 8005c70: 60fb str r3, [r7, #12] uint32_t Conversion_Timeout_CPU_cycles_max = 0U; 8005c72: 2300 movs r3, #0 8005c74: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Get tick count */ tickstart = HAL_GetTick(); 8005c76: f7ff fe13 bl 80058a0 8005c7a: 6178 str r0, [r7, #20] /* Verification that ADC configuration is compliant with polling for */ /* each conversion: */ /* Particular case is ADC configured in DMA mode */ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) 8005c7c: 687b ldr r3, [r7, #4] 8005c7e: 681b ldr r3, [r3, #0] 8005c80: 689b ldr r3, [r3, #8] 8005c82: f403 7380 and.w r3, r3, #256 @ 0x100 8005c86: 2b00 cmp r3, #0 8005c88: d00b beq.n 8005ca2 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8005c8a: 687b ldr r3, [r7, #4] 8005c8c: 6a9b ldr r3, [r3, #40] @ 0x28 8005c8e: f043 0220 orr.w r2, r3, #32 8005c92: 687b ldr r3, [r7, #4] 8005c94: 629a str r2, [r3, #40] @ 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 8005c96: 687b ldr r3, [r7, #4] 8005c98: 2200 movs r2, #0 8005c9a: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 8005c9e: 2301 movs r3, #1 8005ca0: e0d3 b.n 8005e4a /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ /* As flag EOC is not set after each conversion, no timeout status can */ /* be set. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 8005ca2: 687b ldr r3, [r7, #4] 8005ca4: 681b ldr r3, [r3, #0] 8005ca6: 685b ldr r3, [r3, #4] 8005ca8: f403 7380 and.w r3, r3, #256 @ 0x100 8005cac: 2b00 cmp r3, #0 8005cae: d131 bne.n 8005d14 HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ) 8005cb0: 687b ldr r3, [r7, #4] 8005cb2: 681b ldr r3, [r3, #0] 8005cb4: 6adb ldr r3, [r3, #44] @ 0x2c 8005cb6: f403 0370 and.w r3, r3, #15728640 @ 0xf00000 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 8005cba: 2b00 cmp r3, #0 8005cbc: d12a bne.n 8005d14 { /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 8005cbe: e021 b.n 8005d04 { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 8005cc0: 683b ldr r3, [r7, #0] 8005cc2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8005cc6: d01d beq.n 8005d04 { if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) 8005cc8: 683b ldr r3, [r7, #0] 8005cca: 2b00 cmp r3, #0 8005ccc: d007 beq.n 8005cde 8005cce: f7ff fde7 bl 80058a0 8005cd2: 4602 mov r2, r0 8005cd4: 697b ldr r3, [r7, #20] 8005cd6: 1ad3 subs r3, r2, r3 8005cd8: 683a ldr r2, [r7, #0] 8005cda: 429a cmp r2, r3 8005cdc: d212 bcs.n 8005d04 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 8005cde: 687b ldr r3, [r7, #4] 8005ce0: 681b ldr r3, [r3, #0] 8005ce2: 681b ldr r3, [r3, #0] 8005ce4: f003 0302 and.w r3, r3, #2 8005ce8: 2b00 cmp r3, #0 8005cea: d10b bne.n 8005d04 { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 8005cec: 687b ldr r3, [r7, #4] 8005cee: 6a9b ldr r3, [r3, #40] @ 0x28 8005cf0: f043 0204 orr.w r2, r3, #4 8005cf4: 687b ldr r3, [r7, #4] 8005cf6: 629a str r2, [r3, #40] @ 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 8005cf8: 687b ldr r3, [r7, #4] 8005cfa: 2200 movs r2, #0 8005cfc: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_TIMEOUT; 8005d00: 2303 movs r3, #3 8005d02: e0a2 b.n 8005e4a while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 8005d04: 687b ldr r3, [r7, #4] 8005d06: 681b ldr r3, [r3, #0] 8005d08: 681b ldr r3, [r3, #0] 8005d0a: f003 0302 and.w r3, r3, #2 8005d0e: 2b00 cmp r3, #0 8005d10: d0d6 beq.n 8005cc0 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 8005d12: e070 b.n 8005df6 /* Replace polling by wait for maximum conversion time */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ /* and ADC maximum conversion cycles on all channels. */ /* - Wait for the expected ADC clock cycles delay */ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 8005d14: 4b4f ldr r3, [pc, #316] @ (8005e54 ) 8005d16: 681c ldr r4, [r3, #0] 8005d18: 2002 movs r0, #2 8005d1a: f002 fc0f bl 800853c 8005d1e: 4603 mov r3, r0 8005d20: fbb4 f2f3 udiv r2, r4, r3 * ADC_CONVCYCLES_MAX_RANGE(hadc) ); 8005d24: 687b ldr r3, [r7, #4] 8005d26: 681b ldr r3, [r3, #0] 8005d28: 6919 ldr r1, [r3, #16] 8005d2a: 4b4b ldr r3, [pc, #300] @ (8005e58 ) 8005d2c: 400b ands r3, r1 8005d2e: 2b00 cmp r3, #0 8005d30: d118 bne.n 8005d64 8005d32: 687b ldr r3, [r7, #4] 8005d34: 681b ldr r3, [r3, #0] 8005d36: 68d9 ldr r1, [r3, #12] 8005d38: 4b48 ldr r3, [pc, #288] @ (8005e5c ) 8005d3a: 400b ands r3, r1 8005d3c: 2b00 cmp r3, #0 8005d3e: d111 bne.n 8005d64 8005d40: 687b ldr r3, [r7, #4] 8005d42: 681b ldr r3, [r3, #0] 8005d44: 6919 ldr r1, [r3, #16] 8005d46: 4b46 ldr r3, [pc, #280] @ (8005e60 ) 8005d48: 400b ands r3, r1 8005d4a: 2b00 cmp r3, #0 8005d4c: d108 bne.n 8005d60 8005d4e: 687b ldr r3, [r7, #4] 8005d50: 681b ldr r3, [r3, #0] 8005d52: 68d9 ldr r1, [r3, #12] 8005d54: 4b43 ldr r3, [pc, #268] @ (8005e64 ) 8005d56: 400b ands r3, r1 8005d58: 2b00 cmp r3, #0 8005d5a: d101 bne.n 8005d60 8005d5c: 2314 movs r3, #20 8005d5e: e020 b.n 8005da2 8005d60: 2329 movs r3, #41 @ 0x29 8005d62: e01e b.n 8005da2 8005d64: 687b ldr r3, [r7, #4] 8005d66: 681b ldr r3, [r3, #0] 8005d68: 6919 ldr r1, [r3, #16] 8005d6a: 4b3d ldr r3, [pc, #244] @ (8005e60 ) 8005d6c: 400b ands r3, r1 8005d6e: 2b00 cmp r3, #0 8005d70: d106 bne.n 8005d80 8005d72: 687b ldr r3, [r7, #4] 8005d74: 681b ldr r3, [r3, #0] 8005d76: 68d9 ldr r1, [r3, #12] 8005d78: 4b3a ldr r3, [pc, #232] @ (8005e64 ) 8005d7a: 400b ands r3, r1 8005d7c: 2b00 cmp r3, #0 8005d7e: d00d beq.n 8005d9c 8005d80: 687b ldr r3, [r7, #4] 8005d82: 681b ldr r3, [r3, #0] 8005d84: 6919 ldr r1, [r3, #16] 8005d86: 4b38 ldr r3, [pc, #224] @ (8005e68 ) 8005d88: 400b ands r3, r1 8005d8a: 2b00 cmp r3, #0 8005d8c: d108 bne.n 8005da0 8005d8e: 687b ldr r3, [r7, #4] 8005d90: 681b ldr r3, [r3, #0] 8005d92: 68d9 ldr r1, [r3, #12] 8005d94: 4b34 ldr r3, [pc, #208] @ (8005e68 ) 8005d96: 400b ands r3, r1 8005d98: 2b00 cmp r3, #0 8005d9a: d101 bne.n 8005da0 8005d9c: 2354 movs r3, #84 @ 0x54 8005d9e: e000 b.n 8005da2 8005da0: 23fc movs r3, #252 @ 0xfc Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock 8005da2: fb02 f303 mul.w r3, r2, r3 8005da6: 613b str r3, [r7, #16] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 8005da8: e021 b.n 8005dee { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 8005daa: 683b ldr r3, [r7, #0] 8005dac: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8005db0: d01a beq.n 8005de8 { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) 8005db2: 683b ldr r3, [r7, #0] 8005db4: 2b00 cmp r3, #0 8005db6: d007 beq.n 8005dc8 8005db8: f7ff fd72 bl 80058a0 8005dbc: 4602 mov r2, r0 8005dbe: 697b ldr r3, [r7, #20] 8005dc0: 1ad3 subs r3, r2, r3 8005dc2: 683a ldr r2, [r7, #0] 8005dc4: 429a cmp r2, r3 8005dc6: d20f bcs.n 8005de8 { /* New check to avoid false timeout detection in case of preemption */ if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 8005dc8: 68fb ldr r3, [r7, #12] 8005dca: 693a ldr r2, [r7, #16] 8005dcc: 429a cmp r2, r3 8005dce: d90b bls.n 8005de8 { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 8005dd0: 687b ldr r3, [r7, #4] 8005dd2: 6a9b ldr r3, [r3, #40] @ 0x28 8005dd4: f043 0204 orr.w r2, r3, #4 8005dd8: 687b ldr r3, [r7, #4] 8005dda: 629a str r2, [r3, #40] @ 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 8005ddc: 687b ldr r3, [r7, #4] 8005dde: 2200 movs r2, #0 8005de0: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_TIMEOUT; 8005de4: 2303 movs r3, #3 8005de6: e030 b.n 8005e4a } } } Conversion_Timeout_CPU_cycles ++; 8005de8: 68fb ldr r3, [r7, #12] 8005dea: 3301 adds r3, #1 8005dec: 60fb str r3, [r7, #12] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 8005dee: 68fb ldr r3, [r7, #12] 8005df0: 693a ldr r2, [r7, #16] 8005df2: 429a cmp r2, r3 8005df4: d8d9 bhi.n 8005daa } } /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 8005df6: 687b ldr r3, [r7, #4] 8005df8: 681b ldr r3, [r3, #0] 8005dfa: f06f 0212 mvn.w r2, #18 8005dfe: 601a str r2, [r3, #0] /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8005e00: 687b ldr r3, [r7, #4] 8005e02: 6a9b ldr r3, [r3, #40] @ 0x28 8005e04: f443 7200 orr.w r2, r3, #512 @ 0x200 8005e08: 687b ldr r3, [r7, #4] 8005e0a: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8005e0c: 687b ldr r3, [r7, #4] 8005e0e: 681b ldr r3, [r3, #0] 8005e10: 689b ldr r3, [r3, #8] 8005e12: f403 2360 and.w r3, r3, #917504 @ 0xe0000 8005e16: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 8005e1a: d115 bne.n 8005e48 (hadc->Init.ContinuousConvMode == DISABLE) ) 8005e1c: 687b ldr r3, [r7, #4] 8005e1e: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8005e20: 2b00 cmp r3, #0 8005e22: d111 bne.n 8005e48 { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8005e24: 687b ldr r3, [r7, #4] 8005e26: 6a9b ldr r3, [r3, #40] @ 0x28 8005e28: f423 7280 bic.w r2, r3, #256 @ 0x100 8005e2c: 687b ldr r3, [r7, #4] 8005e2e: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8005e30: 687b ldr r3, [r7, #4] 8005e32: 6a9b ldr r3, [r3, #40] @ 0x28 8005e34: f403 5380 and.w r3, r3, #4096 @ 0x1000 8005e38: 2b00 cmp r3, #0 8005e3a: d105 bne.n 8005e48 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8005e3c: 687b ldr r3, [r7, #4] 8005e3e: 6a9b ldr r3, [r3, #40] @ 0x28 8005e40: f043 0201 orr.w r2, r3, #1 8005e44: 687b ldr r3, [r7, #4] 8005e46: 629a str r2, [r3, #40] @ 0x28 } } /* Return ADC state */ return HAL_OK; 8005e48: 2300 movs r3, #0 } 8005e4a: 4618 mov r0, r3 8005e4c: 371c adds r7, #28 8005e4e: 46bd mov sp, r7 8005e50: bd90 pop {r4, r7, pc} 8005e52: bf00 nop 8005e54: 20000018 .word 0x20000018 8005e58: 24924924 .word 0x24924924 8005e5c: 00924924 .word 0x00924924 8005e60: 12492492 .word 0x12492492 8005e64: 00492492 .word 0x00492492 8005e68: 00249249 .word 0x00249249 08005e6c : * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc: ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { 8005e6c: b480 push {r7} 8005e6e: b083 sub sp, #12 8005e70: af00 add r7, sp, #0 8005e72: 6078 str r0, [r7, #4] /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; 8005e74: 687b ldr r3, [r7, #4] 8005e76: 681b ldr r3, [r3, #0] 8005e78: 6cdb ldr r3, [r3, #76] @ 0x4c } 8005e7a: 4618 mov r0, r3 8005e7c: 370c adds r7, #12 8005e7e: 46bd mov sp, r7 8005e80: bc80 pop {r7} 8005e82: 4770 bx lr 08005e84 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8005e84: b480 push {r7} 8005e86: b085 sub sp, #20 8005e88: af00 add r7, sp, #0 8005e8a: 6078 str r0, [r7, #4] 8005e8c: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8005e8e: 2300 movs r3, #0 8005e90: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 8005e92: 2300 movs r3, #0 8005e94: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 8005e96: 687b ldr r3, [r7, #4] 8005e98: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 8005e9c: 2b01 cmp r3, #1 8005e9e: d101 bne.n 8005ea4 8005ea0: 2302 movs r3, #2 8005ea2: e0dc b.n 800605e 8005ea4: 687b ldr r3, [r7, #4] 8005ea6: 2201 movs r2, #1 8005ea8: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 8005eac: 683b ldr r3, [r7, #0] 8005eae: 685b ldr r3, [r3, #4] 8005eb0: 2b06 cmp r3, #6 8005eb2: d81c bhi.n 8005eee { MODIFY_REG(hadc->Instance->SQR3 , 8005eb4: 687b ldr r3, [r7, #4] 8005eb6: 681b ldr r3, [r3, #0] 8005eb8: 6b59 ldr r1, [r3, #52] @ 0x34 8005eba: 683b ldr r3, [r7, #0] 8005ebc: 685a ldr r2, [r3, #4] 8005ebe: 4613 mov r3, r2 8005ec0: 009b lsls r3, r3, #2 8005ec2: 4413 add r3, r2 8005ec4: 3b05 subs r3, #5 8005ec6: 221f movs r2, #31 8005ec8: fa02 f303 lsl.w r3, r2, r3 8005ecc: 43db mvns r3, r3 8005ece: 4019 ands r1, r3 8005ed0: 683b ldr r3, [r7, #0] 8005ed2: 6818 ldr r0, [r3, #0] 8005ed4: 683b ldr r3, [r7, #0] 8005ed6: 685a ldr r2, [r3, #4] 8005ed8: 4613 mov r3, r2 8005eda: 009b lsls r3, r3, #2 8005edc: 4413 add r3, r2 8005ede: 3b05 subs r3, #5 8005ee0: fa00 f203 lsl.w r2, r0, r3 8005ee4: 687b ldr r3, [r7, #4] 8005ee6: 681b ldr r3, [r3, #0] 8005ee8: 430a orrs r2, r1 8005eea: 635a str r2, [r3, #52] @ 0x34 8005eec: e03c b.n 8005f68 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 8005eee: 683b ldr r3, [r7, #0] 8005ef0: 685b ldr r3, [r3, #4] 8005ef2: 2b0c cmp r3, #12 8005ef4: d81c bhi.n 8005f30 { MODIFY_REG(hadc->Instance->SQR2 , 8005ef6: 687b ldr r3, [r7, #4] 8005ef8: 681b ldr r3, [r3, #0] 8005efa: 6b19 ldr r1, [r3, #48] @ 0x30 8005efc: 683b ldr r3, [r7, #0] 8005efe: 685a ldr r2, [r3, #4] 8005f00: 4613 mov r3, r2 8005f02: 009b lsls r3, r3, #2 8005f04: 4413 add r3, r2 8005f06: 3b23 subs r3, #35 @ 0x23 8005f08: 221f movs r2, #31 8005f0a: fa02 f303 lsl.w r3, r2, r3 8005f0e: 43db mvns r3, r3 8005f10: 4019 ands r1, r3 8005f12: 683b ldr r3, [r7, #0] 8005f14: 6818 ldr r0, [r3, #0] 8005f16: 683b ldr r3, [r7, #0] 8005f18: 685a ldr r2, [r3, #4] 8005f1a: 4613 mov r3, r2 8005f1c: 009b lsls r3, r3, #2 8005f1e: 4413 add r3, r2 8005f20: 3b23 subs r3, #35 @ 0x23 8005f22: fa00 f203 lsl.w r2, r0, r3 8005f26: 687b ldr r3, [r7, #4] 8005f28: 681b ldr r3, [r3, #0] 8005f2a: 430a orrs r2, r1 8005f2c: 631a str r2, [r3, #48] @ 0x30 8005f2e: e01b b.n 8005f68 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 8005f30: 687b ldr r3, [r7, #4] 8005f32: 681b ldr r3, [r3, #0] 8005f34: 6ad9 ldr r1, [r3, #44] @ 0x2c 8005f36: 683b ldr r3, [r7, #0] 8005f38: 685a ldr r2, [r3, #4] 8005f3a: 4613 mov r3, r2 8005f3c: 009b lsls r3, r3, #2 8005f3e: 4413 add r3, r2 8005f40: 3b41 subs r3, #65 @ 0x41 8005f42: 221f movs r2, #31 8005f44: fa02 f303 lsl.w r3, r2, r3 8005f48: 43db mvns r3, r3 8005f4a: 4019 ands r1, r3 8005f4c: 683b ldr r3, [r7, #0] 8005f4e: 6818 ldr r0, [r3, #0] 8005f50: 683b ldr r3, [r7, #0] 8005f52: 685a ldr r2, [r3, #4] 8005f54: 4613 mov r3, r2 8005f56: 009b lsls r3, r3, #2 8005f58: 4413 add r3, r2 8005f5a: 3b41 subs r3, #65 @ 0x41 8005f5c: fa00 f203 lsl.w r2, r0, r3 8005f60: 687b ldr r3, [r7, #4] 8005f62: 681b ldr r3, [r3, #0] 8005f64: 430a orrs r2, r1 8005f66: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 8005f68: 683b ldr r3, [r7, #0] 8005f6a: 681b ldr r3, [r3, #0] 8005f6c: 2b09 cmp r3, #9 8005f6e: d91c bls.n 8005faa { MODIFY_REG(hadc->Instance->SMPR1 , 8005f70: 687b ldr r3, [r7, #4] 8005f72: 681b ldr r3, [r3, #0] 8005f74: 68d9 ldr r1, [r3, #12] 8005f76: 683b ldr r3, [r7, #0] 8005f78: 681a ldr r2, [r3, #0] 8005f7a: 4613 mov r3, r2 8005f7c: 005b lsls r3, r3, #1 8005f7e: 4413 add r3, r2 8005f80: 3b1e subs r3, #30 8005f82: 2207 movs r2, #7 8005f84: fa02 f303 lsl.w r3, r2, r3 8005f88: 43db mvns r3, r3 8005f8a: 4019 ands r1, r3 8005f8c: 683b ldr r3, [r7, #0] 8005f8e: 6898 ldr r0, [r3, #8] 8005f90: 683b ldr r3, [r7, #0] 8005f92: 681a ldr r2, [r3, #0] 8005f94: 4613 mov r3, r2 8005f96: 005b lsls r3, r3, #1 8005f98: 4413 add r3, r2 8005f9a: 3b1e subs r3, #30 8005f9c: fa00 f203 lsl.w r2, r0, r3 8005fa0: 687b ldr r3, [r7, #4] 8005fa2: 681b ldr r3, [r3, #0] 8005fa4: 430a orrs r2, r1 8005fa6: 60da str r2, [r3, #12] 8005fa8: e019 b.n 8005fde ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 8005faa: 687b ldr r3, [r7, #4] 8005fac: 681b ldr r3, [r3, #0] 8005fae: 6919 ldr r1, [r3, #16] 8005fb0: 683b ldr r3, [r7, #0] 8005fb2: 681a ldr r2, [r3, #0] 8005fb4: 4613 mov r3, r2 8005fb6: 005b lsls r3, r3, #1 8005fb8: 4413 add r3, r2 8005fba: 2207 movs r2, #7 8005fbc: fa02 f303 lsl.w r3, r2, r3 8005fc0: 43db mvns r3, r3 8005fc2: 4019 ands r1, r3 8005fc4: 683b ldr r3, [r7, #0] 8005fc6: 6898 ldr r0, [r3, #8] 8005fc8: 683b ldr r3, [r7, #0] 8005fca: 681a ldr r2, [r3, #0] 8005fcc: 4613 mov r3, r2 8005fce: 005b lsls r3, r3, #1 8005fd0: 4413 add r3, r2 8005fd2: fa00 f203 lsl.w r2, r0, r3 8005fd6: 687b ldr r3, [r7, #4] 8005fd8: 681b ldr r3, [r3, #0] 8005fda: 430a orrs r2, r1 8005fdc: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 8005fde: 683b ldr r3, [r7, #0] 8005fe0: 681b ldr r3, [r3, #0] 8005fe2: 2b10 cmp r3, #16 8005fe4: d003 beq.n 8005fee (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 8005fe6: 683b ldr r3, [r7, #0] 8005fe8: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 8005fea: 2b11 cmp r3, #17 8005fec: d132 bne.n 8006054 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 8005fee: 687b ldr r3, [r7, #4] 8005ff0: 681b ldr r3, [r3, #0] 8005ff2: 4a1d ldr r2, [pc, #116] @ (8006068 ) 8005ff4: 4293 cmp r3, r2 8005ff6: d125 bne.n 8006044 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 8005ff8: 687b ldr r3, [r7, #4] 8005ffa: 681b ldr r3, [r3, #0] 8005ffc: 689b ldr r3, [r3, #8] 8005ffe: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8006002: 2b00 cmp r3, #0 8006004: d126 bne.n 8006054 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 8006006: 687b ldr r3, [r7, #4] 8006008: 681b ldr r3, [r3, #0] 800600a: 689a ldr r2, [r3, #8] 800600c: 687b ldr r3, [r7, #4] 800600e: 681b ldr r3, [r3, #0] 8006010: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 8006014: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 8006016: 683b ldr r3, [r7, #0] 8006018: 681b ldr r3, [r3, #0] 800601a: 2b10 cmp r3, #16 800601c: d11a bne.n 8006054 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 800601e: 4b13 ldr r3, [pc, #76] @ (800606c ) 8006020: 681b ldr r3, [r3, #0] 8006022: 4a13 ldr r2, [pc, #76] @ (8006070 ) 8006024: fba2 2303 umull r2, r3, r2, r3 8006028: 0c9a lsrs r2, r3, #18 800602a: 4613 mov r3, r2 800602c: 009b lsls r3, r3, #2 800602e: 4413 add r3, r2 8006030: 005b lsls r3, r3, #1 8006032: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8006034: e002 b.n 800603c { wait_loop_index--; 8006036: 68bb ldr r3, [r7, #8] 8006038: 3b01 subs r3, #1 800603a: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800603c: 68bb ldr r3, [r7, #8] 800603e: 2b00 cmp r3, #0 8006040: d1f9 bne.n 8006036 8006042: e007 b.n 8006054 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8006044: 687b ldr r3, [r7, #4] 8006046: 6a9b ldr r3, [r3, #40] @ 0x28 8006048: f043 0220 orr.w r2, r3, #32 800604c: 687b ldr r3, [r7, #4] 800604e: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 8006050: 2301 movs r3, #1 8006052: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8006054: 687b ldr r3, [r7, #4] 8006056: 2200 movs r2, #0 8006058: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800605c: 7bfb ldrb r3, [r7, #15] } 800605e: 4618 mov r0, r3 8006060: 3714 adds r7, #20 8006062: 46bd mov sp, r7 8006064: bc80 pop {r7} 8006066: 4770 bx lr 8006068: 40012400 .word 0x40012400 800606c: 20000018 .word 0x20000018 8006070: 431bde83 .word 0x431bde83 08006074 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 8006074: b580 push {r7, lr} 8006076: b084 sub sp, #16 8006078: af00 add r7, sp, #0 800607a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800607c: 2300 movs r3, #0 800607e: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 8006080: 2300 movs r3, #0 8006082: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 8006084: 687b ldr r3, [r7, #4] 8006086: 681b ldr r3, [r3, #0] 8006088: 689b ldr r3, [r3, #8] 800608a: f003 0301 and.w r3, r3, #1 800608e: 2b01 cmp r3, #1 8006090: d040 beq.n 8006114 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 8006092: 687b ldr r3, [r7, #4] 8006094: 681b ldr r3, [r3, #0] 8006096: 689a ldr r2, [r3, #8] 8006098: 687b ldr r3, [r7, #4] 800609a: 681b ldr r3, [r3, #0] 800609c: f042 0201 orr.w r2, r2, #1 80060a0: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 80060a2: 4b1f ldr r3, [pc, #124] @ (8006120 ) 80060a4: 681b ldr r3, [r3, #0] 80060a6: 4a1f ldr r2, [pc, #124] @ (8006124 ) 80060a8: fba2 2303 umull r2, r3, r2, r3 80060ac: 0c9b lsrs r3, r3, #18 80060ae: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80060b0: e002 b.n 80060b8 { wait_loop_index--; 80060b2: 68bb ldr r3, [r7, #8] 80060b4: 3b01 subs r3, #1 80060b6: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80060b8: 68bb ldr r3, [r7, #8] 80060ba: 2b00 cmp r3, #0 80060bc: d1f9 bne.n 80060b2 } /* Get tick count */ tickstart = HAL_GetTick(); 80060be: f7ff fbef bl 80058a0 80060c2: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 80060c4: e01f b.n 8006106 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 80060c6: f7ff fbeb bl 80058a0 80060ca: 4602 mov r2, r0 80060cc: 68fb ldr r3, [r7, #12] 80060ce: 1ad3 subs r3, r2, r3 80060d0: 2b02 cmp r3, #2 80060d2: d918 bls.n 8006106 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 80060d4: 687b ldr r3, [r7, #4] 80060d6: 681b ldr r3, [r3, #0] 80060d8: 689b ldr r3, [r3, #8] 80060da: f003 0301 and.w r3, r3, #1 80060de: 2b01 cmp r3, #1 80060e0: d011 beq.n 8006106 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80060e2: 687b ldr r3, [r7, #4] 80060e4: 6a9b ldr r3, [r3, #40] @ 0x28 80060e6: f043 0210 orr.w r2, r3, #16 80060ea: 687b ldr r3, [r7, #4] 80060ec: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80060ee: 687b ldr r3, [r7, #4] 80060f0: 6adb ldr r3, [r3, #44] @ 0x2c 80060f2: f043 0201 orr.w r2, r3, #1 80060f6: 687b ldr r3, [r7, #4] 80060f8: 62da str r2, [r3, #44] @ 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 80060fa: 687b ldr r3, [r7, #4] 80060fc: 2200 movs r2, #0 80060fe: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 8006102: 2301 movs r3, #1 8006104: e007 b.n 8006116 while(ADC_IS_ENABLE(hadc) == RESET) 8006106: 687b ldr r3, [r7, #4] 8006108: 681b ldr r3, [r3, #0] 800610a: 689b ldr r3, [r3, #8] 800610c: f003 0301 and.w r3, r3, #1 8006110: 2b01 cmp r3, #1 8006112: d1d8 bne.n 80060c6 } } } /* Return HAL status */ return HAL_OK; 8006114: 2300 movs r3, #0 } 8006116: 4618 mov r0, r3 8006118: 3710 adds r7, #16 800611a: 46bd mov sp, r7 800611c: bd80 pop {r7, pc} 800611e: bf00 nop 8006120: 20000018 .word 0x20000018 8006124: 431bde83 .word 0x431bde83 08006128 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 8006128: b580 push {r7, lr} 800612a: b084 sub sp, #16 800612c: af00 add r7, sp, #0 800612e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8006130: 2300 movs r3, #0 8006132: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 8006134: 687b ldr r3, [r7, #4] 8006136: 681b ldr r3, [r3, #0] 8006138: 689b ldr r3, [r3, #8] 800613a: f003 0301 and.w r3, r3, #1 800613e: 2b01 cmp r3, #1 8006140: d12e bne.n 80061a0 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 8006142: 687b ldr r3, [r7, #4] 8006144: 681b ldr r3, [r3, #0] 8006146: 689a ldr r2, [r3, #8] 8006148: 687b ldr r3, [r7, #4] 800614a: 681b ldr r3, [r3, #0] 800614c: f022 0201 bic.w r2, r2, #1 8006150: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 8006152: f7ff fba5 bl 80058a0 8006156: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 8006158: e01b b.n 8006192 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800615a: f7ff fba1 bl 80058a0 800615e: 4602 mov r2, r0 8006160: 68fb ldr r3, [r7, #12] 8006162: 1ad3 subs r3, r2, r3 8006164: 2b02 cmp r3, #2 8006166: d914 bls.n 8006192 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 8006168: 687b ldr r3, [r7, #4] 800616a: 681b ldr r3, [r3, #0] 800616c: 689b ldr r3, [r3, #8] 800616e: f003 0301 and.w r3, r3, #1 8006172: 2b01 cmp r3, #1 8006174: d10d bne.n 8006192 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006176: 687b ldr r3, [r7, #4] 8006178: 6a9b ldr r3, [r3, #40] @ 0x28 800617a: f043 0210 orr.w r2, r3, #16 800617e: 687b ldr r3, [r7, #4] 8006180: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006182: 687b ldr r3, [r7, #4] 8006184: 6adb ldr r3, [r3, #44] @ 0x2c 8006186: f043 0201 orr.w r2, r3, #1 800618a: 687b ldr r3, [r7, #4] 800618c: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 800618e: 2301 movs r3, #1 8006190: e007 b.n 80061a2 while(ADC_IS_ENABLE(hadc) != RESET) 8006192: 687b ldr r3, [r7, #4] 8006194: 681b ldr r3, [r3, #0] 8006196: 689b ldr r3, [r3, #8] 8006198: f003 0301 and.w r3, r3, #1 800619c: 2b01 cmp r3, #1 800619e: d0dc beq.n 800615a } } } /* Return HAL status */ return HAL_OK; 80061a0: 2300 movs r3, #0 } 80061a2: 4618 mov r0, r3 80061a4: 3710 adds r7, #16 80061a6: 46bd mov sp, r7 80061a8: bd80 pop {r7, pc} ... 080061ac : * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { 80061ac: b590 push {r4, r7, lr} 80061ae: b087 sub sp, #28 80061b0: af00 add r7, sp, #0 80061b2: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80061b4: 2300 movs r3, #0 80061b6: 75fb strb r3, [r7, #23] uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; 80061b8: 2300 movs r3, #0 80061ba: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 80061bc: 687b ldr r3, [r7, #4] 80061be: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 80061c2: 2b01 cmp r3, #1 80061c4: d101 bne.n 80061ca 80061c6: 2302 movs r3, #2 80061c8: e095 b.n 80062f6 80061ca: 687b ldr r3, [r7, #4] 80061cc: 2201 movs r2, #1 80061ce: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* 1. Calibration prerequisite: */ /* - ADC must be disabled for at least two ADC clock cycles in disable */ /* mode before ADC enable */ /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 80061d2: 6878 ldr r0, [r7, #4] 80061d4: f7ff ffa8 bl 8006128 80061d8: 4603 mov r3, r0 80061da: 75fb strb r3, [r7, #23] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 80061dc: 7dfb ldrb r3, [r7, #23] 80061de: 2b00 cmp r3, #0 80061e0: f040 8084 bne.w 80062ec { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80061e4: 687b ldr r3, [r7, #4] 80061e6: 6a9b ldr r3, [r3, #40] @ 0x28 80061e8: f423 5388 bic.w r3, r3, #4352 @ 0x1100 80061ec: f023 0302 bic.w r3, r3, #2 80061f0: f043 0202 orr.w r2, r3, #2 80061f4: 687b ldr r3, [r7, #4] 80061f6: 629a str r2, [r3, #40] @ 0x28 /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 80061f8: 4b41 ldr r3, [pc, #260] @ (8006300 ) 80061fa: 681c ldr r4, [r3, #0] 80061fc: 2002 movs r0, #2 80061fe: f002 f99d bl 800853c 8006202: 4603 mov r3, r0 8006204: fbb4 f3f3 udiv r3, r4, r3 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 8006208: 005b lsls r3, r3, #1 wait_loop_index = ((SystemCoreClock 800620a: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800620c: e002 b.n 8006214 { wait_loop_index--; 800620e: 68fb ldr r3, [r7, #12] 8006210: 3b01 subs r3, #1 8006212: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 8006214: 68fb ldr r3, [r7, #12] 8006216: 2b00 cmp r3, #0 8006218: d1f9 bne.n 800620e } /* 2. Enable the ADC peripheral */ ADC_Enable(hadc); 800621a: 6878 ldr r0, [r7, #4] 800621c: f7ff ff2a bl 8006074 /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 8006220: 687b ldr r3, [r7, #4] 8006222: 681b ldr r3, [r3, #0] 8006224: 689a ldr r2, [r3, #8] 8006226: 687b ldr r3, [r7, #4] 8006228: 681b ldr r3, [r3, #0] 800622a: f042 0208 orr.w r2, r2, #8 800622e: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 8006230: f7ff fb36 bl 80058a0 8006234: 6138 str r0, [r7, #16] /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 8006236: e01b b.n 8006270 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 8006238: f7ff fb32 bl 80058a0 800623c: 4602 mov r2, r0 800623e: 693b ldr r3, [r7, #16] 8006240: 1ad3 subs r3, r2, r3 8006242: 2b0a cmp r3, #10 8006244: d914 bls.n 8006270 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 8006246: 687b ldr r3, [r7, #4] 8006248: 681b ldr r3, [r3, #0] 800624a: 689b ldr r3, [r3, #8] 800624c: f003 0308 and.w r3, r3, #8 8006250: 2b00 cmp r3, #0 8006252: d00d beq.n 8006270 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8006254: 687b ldr r3, [r7, #4] 8006256: 6a9b ldr r3, [r3, #40] @ 0x28 8006258: f023 0312 bic.w r3, r3, #18 800625c: f043 0210 orr.w r2, r3, #16 8006260: 687b ldr r3, [r7, #4] 8006262: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 8006264: 687b ldr r3, [r7, #4] 8006266: 2200 movs r2, #0 8006268: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800626c: 2301 movs r3, #1 800626e: e042 b.n 80062f6 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 8006270: 687b ldr r3, [r7, #4] 8006272: 681b ldr r3, [r3, #0] 8006274: 689b ldr r3, [r3, #8] 8006276: f003 0308 and.w r3, r3, #8 800627a: 2b00 cmp r3, #0 800627c: d1dc bne.n 8006238 } } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 800627e: 687b ldr r3, [r7, #4] 8006280: 681b ldr r3, [r3, #0] 8006282: 689a ldr r2, [r3, #8] 8006284: 687b ldr r3, [r7, #4] 8006286: 681b ldr r3, [r3, #0] 8006288: f042 0204 orr.w r2, r2, #4 800628c: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800628e: f7ff fb07 bl 80058a0 8006292: 6138 str r0, [r7, #16] /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 8006294: e01b b.n 80062ce { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 8006296: f7ff fb03 bl 80058a0 800629a: 4602 mov r2, r0 800629c: 693b ldr r3, [r7, #16] 800629e: 1ad3 subs r3, r2, r3 80062a0: 2b0a cmp r3, #10 80062a2: d914 bls.n 80062ce { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 80062a4: 687b ldr r3, [r7, #4] 80062a6: 681b ldr r3, [r3, #0] 80062a8: 689b ldr r3, [r3, #8] 80062aa: f003 0304 and.w r3, r3, #4 80062ae: 2b00 cmp r3, #0 80062b0: d00d beq.n 80062ce { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 80062b2: 687b ldr r3, [r7, #4] 80062b4: 6a9b ldr r3, [r3, #40] @ 0x28 80062b6: f023 0312 bic.w r3, r3, #18 80062ba: f043 0210 orr.w r2, r3, #16 80062be: 687b ldr r3, [r7, #4] 80062c0: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 80062c2: 687b ldr r3, [r7, #4] 80062c4: 2200 movs r2, #0 80062c6: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 80062ca: 2301 movs r3, #1 80062cc: e013 b.n 80062f6 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 80062ce: 687b ldr r3, [r7, #4] 80062d0: 681b ldr r3, [r3, #0] 80062d2: 689b ldr r3, [r3, #8] 80062d4: f003 0304 and.w r3, r3, #4 80062d8: 2b00 cmp r3, #0 80062da: d1dc bne.n 8006296 } } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80062dc: 687b ldr r3, [r7, #4] 80062de: 6a9b ldr r3, [r3, #40] @ 0x28 80062e0: f023 0303 bic.w r3, r3, #3 80062e4: f043 0201 orr.w r2, r3, #1 80062e8: 687b ldr r3, [r7, #4] 80062ea: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 80062ec: 687b ldr r3, [r7, #4] 80062ee: 2200 movs r2, #0 80062f0: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 80062f4: 7dfb ldrb r3, [r7, #23] } 80062f6: 4618 mov r0, r3 80062f8: 371c adds r7, #28 80062fa: 46bd mov sp, r7 80062fc: bd90 pop {r4, r7, pc} 80062fe: bf00 nop 8006300: 20000018 .word 0x20000018 08006304 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { 8006304: b580 push {r7, lr} 8006306: b084 sub sp, #16 8006308: af00 add r7, sp, #0 800630a: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) 800630c: 687b ldr r3, [r7, #4] 800630e: 2b00 cmp r3, #0 8006310: d101 bne.n 8006316 { return HAL_ERROR; 8006312: 2301 movs r3, #1 8006314: e0ed b.n 80064f2 /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) 8006316: 687b ldr r3, [r7, #4] 8006318: f893 3020 ldrb.w r3, [r3, #32] 800631c: b2db uxtb r3, r3 800631e: 2b00 cmp r3, #0 8006320: d102 bne.n 8006328 { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); 8006322: 6878 ldr r0, [r7, #4] 8006324: f7fb fb82 bl 8001a2c } #endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 8006328: 687b ldr r3, [r7, #4] 800632a: 681b ldr r3, [r3, #0] 800632c: 681a ldr r2, [r3, #0] 800632e: 687b ldr r3, [r7, #4] 8006330: 681b ldr r3, [r3, #0] 8006332: f042 0201 orr.w r2, r2, #1 8006336: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8006338: f7ff fab2 bl 80058a0 800633c: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800633e: e012 b.n 8006366 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 8006340: f7ff faae bl 80058a0 8006344: 4602 mov r2, r0 8006346: 68fb ldr r3, [r7, #12] 8006348: 1ad3 subs r3, r2, r3 800634a: 2b0a cmp r3, #10 800634c: d90b bls.n 8006366 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800634e: 687b ldr r3, [r7, #4] 8006350: 6a5b ldr r3, [r3, #36] @ 0x24 8006352: f443 3200 orr.w r2, r3, #131072 @ 0x20000 8006356: 687b ldr r3, [r7, #4] 8006358: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800635a: 687b ldr r3, [r7, #4] 800635c: 2205 movs r2, #5 800635e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8006362: 2301 movs r3, #1 8006364: e0c5 b.n 80064f2 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 8006366: 687b ldr r3, [r7, #4] 8006368: 681b ldr r3, [r3, #0] 800636a: 685b ldr r3, [r3, #4] 800636c: f003 0301 and.w r3, r3, #1 8006370: 2b00 cmp r3, #0 8006372: d0e5 beq.n 8006340 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 8006374: 687b ldr r3, [r7, #4] 8006376: 681b ldr r3, [r3, #0] 8006378: 681a ldr r2, [r3, #0] 800637a: 687b ldr r3, [r7, #4] 800637c: 681b ldr r3, [r3, #0] 800637e: f022 0202 bic.w r2, r2, #2 8006382: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8006384: f7ff fa8c bl 80058a0 8006388: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800638a: e012 b.n 80063b2 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800638c: f7ff fa88 bl 80058a0 8006390: 4602 mov r2, r0 8006392: 68fb ldr r3, [r7, #12] 8006394: 1ad3 subs r3, r2, r3 8006396: 2b0a cmp r3, #10 8006398: d90b bls.n 80063b2 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800639a: 687b ldr r3, [r7, #4] 800639c: 6a5b ldr r3, [r3, #36] @ 0x24 800639e: f443 3200 orr.w r2, r3, #131072 @ 0x20000 80063a2: 687b ldr r3, [r7, #4] 80063a4: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 80063a6: 687b ldr r3, [r7, #4] 80063a8: 2205 movs r2, #5 80063aa: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 80063ae: 2301 movs r3, #1 80063b0: e09f b.n 80064f2 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 80063b2: 687b ldr r3, [r7, #4] 80063b4: 681b ldr r3, [r3, #0] 80063b6: 685b ldr r3, [r3, #4] 80063b8: f003 0302 and.w r3, r3, #2 80063bc: 2b00 cmp r3, #0 80063be: d1e5 bne.n 800638c } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) 80063c0: 687b ldr r3, [r7, #4] 80063c2: 7e1b ldrb r3, [r3, #24] 80063c4: 2b01 cmp r3, #1 80063c6: d108 bne.n 80063da { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 80063c8: 687b ldr r3, [r7, #4] 80063ca: 681b ldr r3, [r3, #0] 80063cc: 681a ldr r2, [r3, #0] 80063ce: 687b ldr r3, [r7, #4] 80063d0: 681b ldr r3, [r3, #0] 80063d2: f042 0280 orr.w r2, r2, #128 @ 0x80 80063d6: 601a str r2, [r3, #0] 80063d8: e007 b.n 80063ea } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 80063da: 687b ldr r3, [r7, #4] 80063dc: 681b ldr r3, [r3, #0] 80063de: 681a ldr r2, [r3, #0] 80063e0: 687b ldr r3, [r7, #4] 80063e2: 681b ldr r3, [r3, #0] 80063e4: f022 0280 bic.w r2, r2, #128 @ 0x80 80063e8: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) 80063ea: 687b ldr r3, [r7, #4] 80063ec: 7e5b ldrb r3, [r3, #25] 80063ee: 2b01 cmp r3, #1 80063f0: d108 bne.n 8006404 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 80063f2: 687b ldr r3, [r7, #4] 80063f4: 681b ldr r3, [r3, #0] 80063f6: 681a ldr r2, [r3, #0] 80063f8: 687b ldr r3, [r7, #4] 80063fa: 681b ldr r3, [r3, #0] 80063fc: f042 0240 orr.w r2, r2, #64 @ 0x40 8006400: 601a str r2, [r3, #0] 8006402: e007 b.n 8006414 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 8006404: 687b ldr r3, [r7, #4] 8006406: 681b ldr r3, [r3, #0] 8006408: 681a ldr r2, [r3, #0] 800640a: 687b ldr r3, [r7, #4] 800640c: 681b ldr r3, [r3, #0] 800640e: f022 0240 bic.w r2, r2, #64 @ 0x40 8006412: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) 8006414: 687b ldr r3, [r7, #4] 8006416: 7e9b ldrb r3, [r3, #26] 8006418: 2b01 cmp r3, #1 800641a: d108 bne.n 800642e { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800641c: 687b ldr r3, [r7, #4] 800641e: 681b ldr r3, [r3, #0] 8006420: 681a ldr r2, [r3, #0] 8006422: 687b ldr r3, [r7, #4] 8006424: 681b ldr r3, [r3, #0] 8006426: f042 0220 orr.w r2, r2, #32 800642a: 601a str r2, [r3, #0] 800642c: e007 b.n 800643e } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800642e: 687b ldr r3, [r7, #4] 8006430: 681b ldr r3, [r3, #0] 8006432: 681a ldr r2, [r3, #0] 8006434: 687b ldr r3, [r7, #4] 8006436: 681b ldr r3, [r3, #0] 8006438: f022 0220 bic.w r2, r2, #32 800643c: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) 800643e: 687b ldr r3, [r7, #4] 8006440: 7edb ldrb r3, [r3, #27] 8006442: 2b01 cmp r3, #1 8006444: d108 bne.n 8006458 { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); 8006446: 687b ldr r3, [r7, #4] 8006448: 681b ldr r3, [r3, #0] 800644a: 681a ldr r2, [r3, #0] 800644c: 687b ldr r3, [r7, #4] 800644e: 681b ldr r3, [r3, #0] 8006450: f022 0210 bic.w r2, r2, #16 8006454: 601a str r2, [r3, #0] 8006456: e007 b.n 8006468 } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); 8006458: 687b ldr r3, [r7, #4] 800645a: 681b ldr r3, [r3, #0] 800645c: 681a ldr r2, [r3, #0] 800645e: 687b ldr r3, [r7, #4] 8006460: 681b ldr r3, [r3, #0] 8006462: f042 0210 orr.w r2, r2, #16 8006466: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) 8006468: 687b ldr r3, [r7, #4] 800646a: 7f1b ldrb r3, [r3, #28] 800646c: 2b01 cmp r3, #1 800646e: d108 bne.n 8006482 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 8006470: 687b ldr r3, [r7, #4] 8006472: 681b ldr r3, [r3, #0] 8006474: 681a ldr r2, [r3, #0] 8006476: 687b ldr r3, [r7, #4] 8006478: 681b ldr r3, [r3, #0] 800647a: f042 0208 orr.w r2, r2, #8 800647e: 601a str r2, [r3, #0] 8006480: e007 b.n 8006492 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 8006482: 687b ldr r3, [r7, #4] 8006484: 681b ldr r3, [r3, #0] 8006486: 681a ldr r2, [r3, #0] 8006488: 687b ldr r3, [r7, #4] 800648a: 681b ldr r3, [r3, #0] 800648c: f022 0208 bic.w r2, r2, #8 8006490: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) 8006492: 687b ldr r3, [r7, #4] 8006494: 7f5b ldrb r3, [r3, #29] 8006496: 2b01 cmp r3, #1 8006498: d108 bne.n 80064ac { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800649a: 687b ldr r3, [r7, #4] 800649c: 681b ldr r3, [r3, #0] 800649e: 681a ldr r2, [r3, #0] 80064a0: 687b ldr r3, [r7, #4] 80064a2: 681b ldr r3, [r3, #0] 80064a4: f042 0204 orr.w r2, r2, #4 80064a8: 601a str r2, [r3, #0] 80064aa: e007 b.n 80064bc } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 80064ac: 687b ldr r3, [r7, #4] 80064ae: 681b ldr r3, [r3, #0] 80064b0: 681a ldr r2, [r3, #0] 80064b2: 687b ldr r3, [r7, #4] 80064b4: 681b ldr r3, [r3, #0] 80064b6: f022 0204 bic.w r2, r2, #4 80064ba: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | 80064bc: 687b ldr r3, [r7, #4] 80064be: 689a ldr r2, [r3, #8] 80064c0: 687b ldr r3, [r7, #4] 80064c2: 68db ldr r3, [r3, #12] 80064c4: 431a orrs r2, r3 80064c6: 687b ldr r3, [r7, #4] 80064c8: 691b ldr r3, [r3, #16] 80064ca: 431a orrs r2, r3 80064cc: 687b ldr r3, [r7, #4] 80064ce: 695b ldr r3, [r3, #20] 80064d0: ea42 0103 orr.w r1, r2, r3 80064d4: 687b ldr r3, [r7, #4] 80064d6: 685b ldr r3, [r3, #4] 80064d8: 1e5a subs r2, r3, #1 80064da: 687b ldr r3, [r7, #4] 80064dc: 681b ldr r3, [r3, #0] 80064de: 430a orrs r2, r1 80064e0: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 80064e2: 687b ldr r3, [r7, #4] 80064e4: 2200 movs r2, #0 80064e6: 625a str r2, [r3, #36] @ 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; 80064e8: 687b ldr r3, [r7, #4] 80064ea: 2201 movs r2, #1 80064ec: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 80064f0: 2300 movs r3, #0 } 80064f2: 4618 mov r0, r3 80064f4: 3710 adds r7, #16 80064f6: 46bd mov sp, r7 80064f8: bd80 pop {r7, pc} ... 080064fc : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) { 80064fc: b480 push {r7} 80064fe: b087 sub sp, #28 8006500: af00 add r7, sp, #0 8006502: 6078 str r0, [r7, #4] 8006504: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; 8006506: 687b ldr r3, [r7, #4] 8006508: 681b ldr r3, [r3, #0] 800650a: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; 800650c: 687b ldr r3, [r7, #4] 800650e: f893 3020 ldrb.w r3, [r3, #32] 8006512: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || 8006514: 7cfb ldrb r3, [r7, #19] 8006516: 2b01 cmp r3, #1 8006518: d003 beq.n 8006522 800651a: 7cfb ldrb r3, [r7, #19] 800651c: 2b02 cmp r3, #2 800651e: f040 80be bne.w 800669e assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); #if defined(CAN2) /* CAN1 and CAN2 are dual instances with 28 common filters banks */ /* Select master instance to access the filter banks */ can_ip = CAN1; 8006522: 4b65 ldr r3, [pc, #404] @ (80066b8 ) 8006524: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); #endif /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); 8006526: 697b ldr r3, [r7, #20] 8006528: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800652c: f043 0201 orr.w r2, r3, #1 8006530: 697b ldr r3, [r7, #20] 8006532: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #if defined(CAN2) /* Select the start filter number of CAN2 slave instance */ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); 8006536: 697b ldr r3, [r7, #20] 8006538: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800653c: f423 527c bic.w r2, r3, #16128 @ 0x3f00 8006540: 697b ldr r3, [r7, #20] 8006542: f8c3 2200 str.w r2, [r3, #512] @ 0x200 SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); 8006546: 697b ldr r3, [r7, #20] 8006548: f8d3 2200 ldr.w r2, [r3, #512] @ 0x200 800654c: 683b ldr r3, [r7, #0] 800654e: 6a5b ldr r3, [r3, #36] @ 0x24 8006550: 021b lsls r3, r3, #8 8006552: 431a orrs r2, r3 8006554: 697b ldr r3, [r7, #20] 8006556: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #endif /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); 800655a: 683b ldr r3, [r7, #0] 800655c: 695b ldr r3, [r3, #20] 800655e: f003 031f and.w r3, r3, #31 8006562: 2201 movs r2, #1 8006564: fa02 f303 lsl.w r3, r2, r3 8006568: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); 800656a: 697b ldr r3, [r7, #20] 800656c: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 8006570: 68fb ldr r3, [r7, #12] 8006572: 43db mvns r3, r3 8006574: 401a ands r2, r3 8006576: 697b ldr r3, [r7, #20] 8006578: f8c3 221c str.w r2, [r3, #540] @ 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) 800657c: 683b ldr r3, [r7, #0] 800657e: 69db ldr r3, [r3, #28] 8006580: 2b00 cmp r3, #0 8006582: d123 bne.n 80065cc { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); 8006584: 697b ldr r3, [r7, #20] 8006586: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800658a: 68fb ldr r3, [r7, #12] 800658c: 43db mvns r3, r3 800658e: 401a ands r2, r3 8006590: 697b ldr r3, [r7, #20] 8006592: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 8006596: 683b ldr r3, [r7, #0] 8006598: 68db ldr r3, [r3, #12] 800659a: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800659c: 683b ldr r3, [r7, #0] 800659e: 685b ldr r3, [r3, #4] 80065a0: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 80065a2: 683a ldr r2, [r7, #0] 80065a4: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 80065a6: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 80065a8: 697b ldr r3, [r7, #20] 80065aa: 3248 adds r2, #72 @ 0x48 80065ac: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 80065b0: 683b ldr r3, [r7, #0] 80065b2: 689b ldr r3, [r3, #8] 80065b4: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); 80065b6: 683b ldr r3, [r7, #0] 80065b8: 681b ldr r3, [r3, #0] 80065ba: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 80065bc: 683b ldr r3, [r7, #0] 80065be: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 80065c0: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 80065c2: 6979 ldr r1, [r7, #20] 80065c4: 3348 adds r3, #72 @ 0x48 80065c6: 00db lsls r3, r3, #3 80065c8: 440b add r3, r1 80065ca: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) 80065cc: 683b ldr r3, [r7, #0] 80065ce: 69db ldr r3, [r3, #28] 80065d0: 2b01 cmp r3, #1 80065d2: d122 bne.n 800661a { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); 80065d4: 697b ldr r3, [r7, #20] 80065d6: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 80065da: 68fb ldr r3, [r7, #12] 80065dc: 431a orrs r2, r3 80065de: 697b ldr r3, [r7, #20] 80065e0: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 80065e4: 683b ldr r3, [r7, #0] 80065e6: 681b ldr r3, [r3, #0] 80065e8: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 80065ea: 683b ldr r3, [r7, #0] 80065ec: 685b ldr r3, [r3, #4] 80065ee: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 80065f0: 683a ldr r2, [r7, #0] 80065f2: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 80065f4: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 80065f6: 697b ldr r3, [r7, #20] 80065f8: 3248 adds r2, #72 @ 0x48 80065fa: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 80065fe: 683b ldr r3, [r7, #0] 8006600: 689b ldr r3, [r3, #8] 8006602: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); 8006604: 683b ldr r3, [r7, #0] 8006606: 68db ldr r3, [r3, #12] 8006608: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800660a: 683b ldr r3, [r7, #0] 800660c: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800660e: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 8006610: 6979 ldr r1, [r7, #20] 8006612: 3348 adds r3, #72 @ 0x48 8006614: 00db lsls r3, r3, #3 8006616: 440b add r3, r1 8006618: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) 800661a: 683b ldr r3, [r7, #0] 800661c: 699b ldr r3, [r3, #24] 800661e: 2b00 cmp r3, #0 8006620: d109 bne.n 8006636 { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); 8006622: 697b ldr r3, [r7, #20] 8006624: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 8006628: 68fb ldr r3, [r7, #12] 800662a: 43db mvns r3, r3 800662c: 401a ands r2, r3 800662e: 697b ldr r3, [r7, #20] 8006630: f8c3 2204 str.w r2, [r3, #516] @ 0x204 8006634: e007 b.n 8006646 } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); 8006636: 697b ldr r3, [r7, #20] 8006638: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800663c: 68fb ldr r3, [r7, #12] 800663e: 431a orrs r2, r3 8006640: 697b ldr r3, [r7, #20] 8006642: f8c3 2204 str.w r2, [r3, #516] @ 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) 8006646: 683b ldr r3, [r7, #0] 8006648: 691b ldr r3, [r3, #16] 800664a: 2b00 cmp r3, #0 800664c: d109 bne.n 8006662 { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); 800664e: 697b ldr r3, [r7, #20] 8006650: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 8006654: 68fb ldr r3, [r7, #12] 8006656: 43db mvns r3, r3 8006658: 401a ands r2, r3 800665a: 697b ldr r3, [r7, #20] 800665c: f8c3 2214 str.w r2, [r3, #532] @ 0x214 8006660: e007 b.n 8006672 } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); 8006662: 697b ldr r3, [r7, #20] 8006664: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 8006668: 68fb ldr r3, [r7, #12] 800666a: 431a orrs r2, r3 800666c: 697b ldr r3, [r7, #20] 800666e: f8c3 2214 str.w r2, [r3, #532] @ 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) 8006672: 683b ldr r3, [r7, #0] 8006674: 6a1b ldr r3, [r3, #32] 8006676: 2b01 cmp r3, #1 8006678: d107 bne.n 800668a { SET_BIT(can_ip->FA1R, filternbrbitpos); 800667a: 697b ldr r3, [r7, #20] 800667c: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 8006680: 68fb ldr r3, [r7, #12] 8006682: 431a orrs r2, r3 8006684: 697b ldr r3, [r7, #20] 8006686: f8c3 221c str.w r2, [r3, #540] @ 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); 800668a: 697b ldr r3, [r7, #20] 800668c: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 8006690: f023 0201 bic.w r2, r3, #1 8006694: 697b ldr r3, [r7, #20] 8006696: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Return function status */ return HAL_OK; 800669a: 2300 movs r3, #0 800669c: e006 b.n 80066ac } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800669e: 687b ldr r3, [r7, #4] 80066a0: 6a5b ldr r3, [r3, #36] @ 0x24 80066a2: f443 2280 orr.w r2, r3, #262144 @ 0x40000 80066a6: 687b ldr r3, [r7, #4] 80066a8: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 80066aa: 2301 movs r3, #1 } } 80066ac: 4618 mov r0, r3 80066ae: 371c adds r7, #28 80066b0: 46bd mov sp, r7 80066b2: bc80 pop {r7} 80066b4: 4770 bx lr 80066b6: bf00 nop 80066b8: 40006400 .word 0x40006400 080066bc : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { 80066bc: b580 push {r7, lr} 80066be: b084 sub sp, #16 80066c0: af00 add r7, sp, #0 80066c2: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) 80066c4: 687b ldr r3, [r7, #4] 80066c6: f893 3020 ldrb.w r3, [r3, #32] 80066ca: b2db uxtb r3, r3 80066cc: 2b01 cmp r3, #1 80066ce: d12e bne.n 800672e { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; 80066d0: 687b ldr r3, [r7, #4] 80066d2: 2202 movs r2, #2 80066d4: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 80066d8: 687b ldr r3, [r7, #4] 80066da: 681b ldr r3, [r3, #0] 80066dc: 681a ldr r2, [r3, #0] 80066de: 687b ldr r3, [r7, #4] 80066e0: 681b ldr r3, [r3, #0] 80066e2: f022 0201 bic.w r2, r2, #1 80066e6: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 80066e8: f7ff f8da bl 80058a0 80066ec: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 80066ee: e012 b.n 8006716 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 80066f0: f7ff f8d6 bl 80058a0 80066f4: 4602 mov r2, r0 80066f6: 68fb ldr r3, [r7, #12] 80066f8: 1ad3 subs r3, r2, r3 80066fa: 2b0a cmp r3, #10 80066fc: d90b bls.n 8006716 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 80066fe: 687b ldr r3, [r7, #4] 8006700: 6a5b ldr r3, [r3, #36] @ 0x24 8006702: f443 3200 orr.w r2, r3, #131072 @ 0x20000 8006706: 687b ldr r3, [r7, #4] 8006708: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800670a: 687b ldr r3, [r7, #4] 800670c: 2205 movs r2, #5 800670e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8006712: 2301 movs r3, #1 8006714: e012 b.n 800673c while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 8006716: 687b ldr r3, [r7, #4] 8006718: 681b ldr r3, [r3, #0] 800671a: 685b ldr r3, [r3, #4] 800671c: f003 0301 and.w r3, r3, #1 8006720: 2b00 cmp r3, #0 8006722: d1e5 bne.n 80066f0 } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 8006724: 687b ldr r3, [r7, #4] 8006726: 2200 movs r2, #0 8006728: 625a str r2, [r3, #36] @ 0x24 /* Return function status */ return HAL_OK; 800672a: 2300 movs r3, #0 800672c: e006 b.n 800673c } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; 800672e: 687b ldr r3, [r7, #4] 8006730: 6a5b ldr r3, [r3, #36] @ 0x24 8006732: f443 2200 orr.w r2, r3, #524288 @ 0x80000 8006736: 687b ldr r3, [r7, #4] 8006738: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800673a: 2301 movs r3, #1 } } 800673c: 4618 mov r0, r3 800673e: 3710 adds r7, #16 8006740: 46bd mov sp, r7 8006742: bd80 pop {r7, pc} 08006744 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { 8006744: b580 push {r7, lr} 8006746: b084 sub sp, #16 8006748: af00 add r7, sp, #0 800674a: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_LISTENING) 800674c: 687b ldr r3, [r7, #4] 800674e: f893 3020 ldrb.w r3, [r3, #32] 8006752: b2db uxtb r3, r3 8006754: 2b02 cmp r3, #2 8006756: d133 bne.n 80067c0 { /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 8006758: 687b ldr r3, [r7, #4] 800675a: 681b ldr r3, [r3, #0] 800675c: 681a ldr r2, [r3, #0] 800675e: 687b ldr r3, [r7, #4] 8006760: 681b ldr r3, [r3, #0] 8006762: f042 0201 orr.w r2, r2, #1 8006766: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8006768: f7ff f89a bl 80058a0 800676c: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800676e: e012 b.n 8006796 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 8006770: f7ff f896 bl 80058a0 8006774: 4602 mov r2, r0 8006776: 68fb ldr r3, [r7, #12] 8006778: 1ad3 subs r3, r2, r3 800677a: 2b0a cmp r3, #10 800677c: d90b bls.n 8006796 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800677e: 687b ldr r3, [r7, #4] 8006780: 6a5b ldr r3, [r3, #36] @ 0x24 8006782: f443 3200 orr.w r2, r3, #131072 @ 0x20000 8006786: 687b ldr r3, [r7, #4] 8006788: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800678a: 687b ldr r3, [r7, #4] 800678c: 2205 movs r2, #5 800678e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8006792: 2301 movs r3, #1 8006794: e01b b.n 80067ce while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 8006796: 687b ldr r3, [r7, #4] 8006798: 681b ldr r3, [r3, #0] 800679a: 685b ldr r3, [r3, #4] 800679c: f003 0301 and.w r3, r3, #1 80067a0: 2b00 cmp r3, #0 80067a2: d0e5 beq.n 8006770 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 80067a4: 687b ldr r3, [r7, #4] 80067a6: 681b ldr r3, [r3, #0] 80067a8: 681a ldr r2, [r3, #0] 80067aa: 687b ldr r3, [r7, #4] 80067ac: 681b ldr r3, [r3, #0] 80067ae: f022 0202 bic.w r2, r2, #2 80067b2: 601a str r2, [r3, #0] /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_READY; 80067b4: 687b ldr r3, [r7, #4] 80067b6: 2201 movs r2, #1 80067b8: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 80067bc: 2300 movs r3, #0 80067be: e006 b.n 80067ce } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; 80067c0: 687b ldr r3, [r7, #4] 80067c2: 6a5b ldr r3, [r3, #36] @ 0x24 80067c4: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 80067c8: 687b ldr r3, [r7, #4] 80067ca: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 80067cc: 2301 movs r3, #1 } } 80067ce: 4618 mov r0, r3 80067d0: 3710 adds r7, #16 80067d2: 46bd mov sp, r7 80067d4: bd80 pop {r7, pc} 080067d6 : * the TxMailbox used to store the Tx message. * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) { 80067d6: b480 push {r7} 80067d8: b089 sub sp, #36 @ 0x24 80067da: af00 add r7, sp, #0 80067dc: 60f8 str r0, [r7, #12] 80067de: 60b9 str r1, [r7, #8] 80067e0: 607a str r2, [r7, #4] 80067e2: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; 80067e4: 68fb ldr r3, [r7, #12] 80067e6: f893 3020 ldrb.w r3, [r3, #32] 80067ea: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); 80067ec: 68fb ldr r3, [r7, #12] 80067ee: 681b ldr r3, [r3, #0] 80067f0: 689b ldr r3, [r3, #8] 80067f2: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || 80067f4: 7ffb ldrb r3, [r7, #31] 80067f6: 2b01 cmp r3, #1 80067f8: d003 beq.n 8006802 80067fa: 7ffb ldrb r3, [r7, #31] 80067fc: 2b02 cmp r3, #2 80067fe: f040 80b8 bne.w 8006972 (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || 8006802: 69bb ldr r3, [r7, #24] 8006804: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8006808: 2b00 cmp r3, #0 800680a: d10a bne.n 8006822 ((tsr & CAN_TSR_TME1) != 0U) || 800680c: 69bb ldr r3, [r7, #24] 800680e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || 8006812: 2b00 cmp r3, #0 8006814: d105 bne.n 8006822 ((tsr & CAN_TSR_TME2) != 0U)) 8006816: 69bb ldr r3, [r7, #24] 8006818: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || 800681c: 2b00 cmp r3, #0 800681e: f000 80a0 beq.w 8006962 { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; 8006822: 69bb ldr r3, [r7, #24] 8006824: 0e1b lsrs r3, r3, #24 8006826: f003 0303 and.w r3, r3, #3 800682a: 617b str r3, [r7, #20] /* Check transmit mailbox value */ if (transmitmailbox > 2U) 800682c: 697b ldr r3, [r7, #20] 800682e: 2b02 cmp r3, #2 8006830: d907 bls.n 8006842 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL; 8006832: 68fb ldr r3, [r7, #12] 8006834: 6a5b ldr r3, [r3, #36] @ 0x24 8006836: f443 0200 orr.w r2, r3, #8388608 @ 0x800000 800683a: 68fb ldr r3, [r7, #12] 800683c: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800683e: 2301 movs r3, #1 8006840: e09e b.n 8006980 } /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; 8006842: 2201 movs r2, #1 8006844: 697b ldr r3, [r7, #20] 8006846: 409a lsls r2, r3 8006848: 683b ldr r3, [r7, #0] 800684a: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) 800684c: 68bb ldr r3, [r7, #8] 800684e: 689b ldr r3, [r3, #8] 8006850: 2b00 cmp r3, #0 8006852: d10d bne.n 8006870 { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 8006854: 68bb ldr r3, [r7, #8] 8006856: 681b ldr r3, [r3, #0] 8006858: 055a lsls r2, r3, #21 pHeader->RTR); 800685a: 68bb ldr r3, [r7, #8] 800685c: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800685e: 68f9 ldr r1, [r7, #12] 8006860: 6809 ldr r1, [r1, #0] 8006862: 431a orrs r2, r3 8006864: 697b ldr r3, [r7, #20] 8006866: 3318 adds r3, #24 8006868: 011b lsls r3, r3, #4 800686a: 440b add r3, r1 800686c: 601a str r2, [r3, #0] 800686e: e00f b.n 8006890 } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8006870: 68bb ldr r3, [r7, #8] 8006872: 685b ldr r3, [r3, #4] 8006874: 00da lsls r2, r3, #3 pHeader->IDE | 8006876: 68bb ldr r3, [r7, #8] 8006878: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800687a: 431a orrs r2, r3 pHeader->RTR); 800687c: 68bb ldr r3, [r7, #8] 800687e: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8006880: 68f9 ldr r1, [r7, #12] 8006882: 6809 ldr r1, [r1, #0] pHeader->IDE | 8006884: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8006886: 697b ldr r3, [r7, #20] 8006888: 3318 adds r3, #24 800688a: 011b lsls r3, r3, #4 800688c: 440b add r3, r1 800688e: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); 8006890: 68fb ldr r3, [r7, #12] 8006892: 6819 ldr r1, [r3, #0] 8006894: 68bb ldr r3, [r7, #8] 8006896: 691a ldr r2, [r3, #16] 8006898: 697b ldr r3, [r7, #20] 800689a: 3318 adds r3, #24 800689c: 011b lsls r3, r3, #4 800689e: 440b add r3, r1 80068a0: 3304 adds r3, #4 80068a2: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) 80068a4: 68bb ldr r3, [r7, #8] 80068a6: 7d1b ldrb r3, [r3, #20] 80068a8: 2b01 cmp r3, #1 80068aa: d111 bne.n 80068d0 { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); 80068ac: 68fb ldr r3, [r7, #12] 80068ae: 681a ldr r2, [r3, #0] 80068b0: 697b ldr r3, [r7, #20] 80068b2: 3318 adds r3, #24 80068b4: 011b lsls r3, r3, #4 80068b6: 4413 add r3, r2 80068b8: 3304 adds r3, #4 80068ba: 681b ldr r3, [r3, #0] 80068bc: 68fa ldr r2, [r7, #12] 80068be: 6811 ldr r1, [r2, #0] 80068c0: f443 7280 orr.w r2, r3, #256 @ 0x100 80068c4: 697b ldr r3, [r7, #20] 80068c6: 3318 adds r3, #24 80068c8: 011b lsls r3, r3, #4 80068ca: 440b add r3, r1 80068cc: 3304 adds r3, #4 80068ce: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, 80068d0: 687b ldr r3, [r7, #4] 80068d2: 3307 adds r3, #7 80068d4: 781b ldrb r3, [r3, #0] 80068d6: 061a lsls r2, r3, #24 80068d8: 687b ldr r3, [r7, #4] 80068da: 3306 adds r3, #6 80068dc: 781b ldrb r3, [r3, #0] 80068de: 041b lsls r3, r3, #16 80068e0: 431a orrs r2, r3 80068e2: 687b ldr r3, [r7, #4] 80068e4: 3305 adds r3, #5 80068e6: 781b ldrb r3, [r3, #0] 80068e8: 021b lsls r3, r3, #8 80068ea: 4313 orrs r3, r2 80068ec: 687a ldr r2, [r7, #4] 80068ee: 3204 adds r2, #4 80068f0: 7812 ldrb r2, [r2, #0] 80068f2: 4610 mov r0, r2 80068f4: 68fa ldr r2, [r7, #12] 80068f6: 6811 ldr r1, [r2, #0] 80068f8: ea43 0200 orr.w r2, r3, r0 80068fc: 697b ldr r3, [r7, #20] 80068fe: 011b lsls r3, r3, #4 8006900: 440b add r3, r1 8006902: f503 73c6 add.w r3, r3, #396 @ 0x18c 8006906: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, 8006908: 687b ldr r3, [r7, #4] 800690a: 3303 adds r3, #3 800690c: 781b ldrb r3, [r3, #0] 800690e: 061a lsls r2, r3, #24 8006910: 687b ldr r3, [r7, #4] 8006912: 3302 adds r3, #2 8006914: 781b ldrb r3, [r3, #0] 8006916: 041b lsls r3, r3, #16 8006918: 431a orrs r2, r3 800691a: 687b ldr r3, [r7, #4] 800691c: 3301 adds r3, #1 800691e: 781b ldrb r3, [r3, #0] 8006920: 021b lsls r3, r3, #8 8006922: 4313 orrs r3, r2 8006924: 687a ldr r2, [r7, #4] 8006926: 7812 ldrb r2, [r2, #0] 8006928: 4610 mov r0, r2 800692a: 68fa ldr r2, [r7, #12] 800692c: 6811 ldr r1, [r2, #0] 800692e: ea43 0200 orr.w r2, r3, r0 8006932: 697b ldr r3, [r7, #20] 8006934: 011b lsls r3, r3, #4 8006936: 440b add r3, r1 8006938: f503 73c4 add.w r3, r3, #392 @ 0x188 800693c: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); 800693e: 68fb ldr r3, [r7, #12] 8006940: 681a ldr r2, [r3, #0] 8006942: 697b ldr r3, [r7, #20] 8006944: 3318 adds r3, #24 8006946: 011b lsls r3, r3, #4 8006948: 4413 add r3, r2 800694a: 681b ldr r3, [r3, #0] 800694c: 68fa ldr r2, [r7, #12] 800694e: 6811 ldr r1, [r2, #0] 8006950: f043 0201 orr.w r2, r3, #1 8006954: 697b ldr r3, [r7, #20] 8006956: 3318 adds r3, #24 8006958: 011b lsls r3, r3, #4 800695a: 440b add r3, r1 800695c: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800695e: 2300 movs r3, #0 8006960: e00e b.n 8006980 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 8006962: 68fb ldr r3, [r7, #12] 8006964: 6a5b ldr r3, [r3, #36] @ 0x24 8006966: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800696a: 68fb ldr r3, [r7, #12] 800696c: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800696e: 2301 movs r3, #1 8006970: e006 b.n 8006980 } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8006972: 68fb ldr r3, [r7, #12] 8006974: 6a5b ldr r3, [r3, #36] @ 0x24 8006976: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800697a: 68fb ldr r3, [r7, #12] 800697c: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800697e: 2301 movs r3, #1 } } 8006980: 4618 mov r0, r3 8006982: 3724 adds r7, #36 @ 0x24 8006984: 46bd mov sp, r7 8006986: bc80 pop {r7} 8006988: 4770 bx lr 0800698a : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval Number of free Tx Mailboxes. */ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) { 800698a: b480 push {r7} 800698c: b085 sub sp, #20 800698e: af00 add r7, sp, #0 8006990: 6078 str r0, [r7, #4] uint32_t freelevel = 0U; 8006992: 2300 movs r3, #0 8006994: 60fb str r3, [r7, #12] HAL_CAN_StateTypeDef state = hcan->State; 8006996: 687b ldr r3, [r7, #4] 8006998: f893 3020 ldrb.w r3, [r3, #32] 800699c: 72fb strb r3, [r7, #11] if ((state == HAL_CAN_STATE_READY) || 800699e: 7afb ldrb r3, [r7, #11] 80069a0: 2b01 cmp r3, #1 80069a2: d002 beq.n 80069aa 80069a4: 7afb ldrb r3, [r7, #11] 80069a6: 2b02 cmp r3, #2 80069a8: d11d bne.n 80069e6 (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 status */ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) 80069aa: 687b ldr r3, [r7, #4] 80069ac: 681b ldr r3, [r3, #0] 80069ae: 689b ldr r3, [r3, #8] 80069b0: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 80069b4: 2b00 cmp r3, #0 80069b6: d002 beq.n 80069be { freelevel++; 80069b8: 68fb ldr r3, [r7, #12] 80069ba: 3301 adds r3, #1 80069bc: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 1 status */ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) 80069be: 687b ldr r3, [r7, #4] 80069c0: 681b ldr r3, [r3, #0] 80069c2: 689b ldr r3, [r3, #8] 80069c4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80069c8: 2b00 cmp r3, #0 80069ca: d002 beq.n 80069d2 { freelevel++; 80069cc: 68fb ldr r3, [r7, #12] 80069ce: 3301 adds r3, #1 80069d0: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 2 status */ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) 80069d2: 687b ldr r3, [r7, #4] 80069d4: 681b ldr r3, [r3, #0] 80069d6: 689b ldr r3, [r3, #8] 80069d8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80069dc: 2b00 cmp r3, #0 80069de: d002 beq.n 80069e6 { freelevel++; 80069e0: 68fb ldr r3, [r7, #12] 80069e2: 3301 adds r3, #1 80069e4: 60fb str r3, [r7, #12] } } /* Return Tx Mailboxes free level */ return freelevel; 80069e6: 68fb ldr r3, [r7, #12] } 80069e8: 4618 mov r0, r3 80069ea: 3714 adds r7, #20 80069ec: 46bd mov sp, r7 80069ee: bc80 pop {r7} 80069f0: 4770 bx lr 080069f2 : * of the Rx frame will be stored. * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { 80069f2: b480 push {r7} 80069f4: b087 sub sp, #28 80069f6: af00 add r7, sp, #0 80069f8: 60f8 str r0, [r7, #12] 80069fa: 60b9 str r1, [r7, #8] 80069fc: 607a str r2, [r7, #4] 80069fe: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 8006a00: 68fb ldr r3, [r7, #12] 8006a02: f893 3020 ldrb.w r3, [r3, #32] 8006a06: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || 8006a08: 7dfb ldrb r3, [r7, #23] 8006a0a: 2b01 cmp r3, #1 8006a0c: d003 beq.n 8006a16 8006a0e: 7dfb ldrb r3, [r7, #23] 8006a10: 2b02 cmp r3, #2 8006a12: f040 80f3 bne.w 8006bfc (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 8006a16: 68bb ldr r3, [r7, #8] 8006a18: 2b00 cmp r3, #0 8006a1a: d10e bne.n 8006a3a { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) 8006a1c: 68fb ldr r3, [r7, #12] 8006a1e: 681b ldr r3, [r3, #0] 8006a20: 68db ldr r3, [r3, #12] 8006a22: f003 0303 and.w r3, r3, #3 8006a26: 2b00 cmp r3, #0 8006a28: d116 bne.n 8006a58 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 8006a2a: 68fb ldr r3, [r7, #12] 8006a2c: 6a5b ldr r3, [r3, #36] @ 0x24 8006a2e: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 8006a32: 68fb ldr r3, [r7, #12] 8006a34: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 8006a36: 2301 movs r3, #1 8006a38: e0e7 b.n 8006c0a } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) 8006a3a: 68fb ldr r3, [r7, #12] 8006a3c: 681b ldr r3, [r3, #0] 8006a3e: 691b ldr r3, [r3, #16] 8006a40: f003 0303 and.w r3, r3, #3 8006a44: 2b00 cmp r3, #0 8006a46: d107 bne.n 8006a58 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 8006a48: 68fb ldr r3, [r7, #12] 8006a4a: 6a5b ldr r3, [r3, #36] @ 0x24 8006a4c: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 8006a50: 68fb ldr r3, [r7, #12] 8006a52: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 8006a54: 2301 movs r3, #1 8006a56: e0d8 b.n 8006c0a } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; 8006a58: 68fb ldr r3, [r7, #12] 8006a5a: 681a ldr r2, [r3, #0] 8006a5c: 68bb ldr r3, [r7, #8] 8006a5e: 331b adds r3, #27 8006a60: 011b lsls r3, r3, #4 8006a62: 4413 add r3, r2 8006a64: 681b ldr r3, [r3, #0] 8006a66: f003 0204 and.w r2, r3, #4 8006a6a: 687b ldr r3, [r7, #4] 8006a6c: 609a str r2, [r3, #8] if (pHeader->IDE == CAN_ID_STD) 8006a6e: 687b ldr r3, [r7, #4] 8006a70: 689b ldr r3, [r3, #8] 8006a72: 2b00 cmp r3, #0 8006a74: d10c bne.n 8006a90 { pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; 8006a76: 68fb ldr r3, [r7, #12] 8006a78: 681a ldr r2, [r3, #0] 8006a7a: 68bb ldr r3, [r7, #8] 8006a7c: 331b adds r3, #27 8006a7e: 011b lsls r3, r3, #4 8006a80: 4413 add r3, r2 8006a82: 681b ldr r3, [r3, #0] 8006a84: 0d5b lsrs r3, r3, #21 8006a86: f3c3 020a ubfx r2, r3, #0, #11 8006a8a: 687b ldr r3, [r7, #4] 8006a8c: 601a str r2, [r3, #0] 8006a8e: e00b b.n 8006aa8 } else { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; 8006a90: 68fb ldr r3, [r7, #12] 8006a92: 681a ldr r2, [r3, #0] 8006a94: 68bb ldr r3, [r7, #8] 8006a96: 331b adds r3, #27 8006a98: 011b lsls r3, r3, #4 8006a9a: 4413 add r3, r2 8006a9c: 681b ldr r3, [r3, #0] 8006a9e: 08db lsrs r3, r3, #3 8006aa0: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 8006aa4: 687b ldr r3, [r7, #4] 8006aa6: 605a str r2, [r3, #4] } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); 8006aa8: 68fb ldr r3, [r7, #12] 8006aaa: 681a ldr r2, [r3, #0] 8006aac: 68bb ldr r3, [r7, #8] 8006aae: 331b adds r3, #27 8006ab0: 011b lsls r3, r3, #4 8006ab2: 4413 add r3, r2 8006ab4: 681b ldr r3, [r3, #0] 8006ab6: f003 0202 and.w r2, r3, #2 8006aba: 687b ldr r3, [r7, #4] 8006abc: 60da str r2, [r3, #12] pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; 8006abe: 68fb ldr r3, [r7, #12] 8006ac0: 681a ldr r2, [r3, #0] 8006ac2: 68bb ldr r3, [r7, #8] 8006ac4: 331b adds r3, #27 8006ac6: 011b lsls r3, r3, #4 8006ac8: 4413 add r3, r2 8006aca: 3304 adds r3, #4 8006acc: 681b ldr r3, [r3, #0] 8006ace: f003 020f and.w r2, r3, #15 8006ad2: 687b ldr r3, [r7, #4] 8006ad4: 611a str r2, [r3, #16] pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; 8006ad6: 68fb ldr r3, [r7, #12] 8006ad8: 681a ldr r2, [r3, #0] 8006ada: 68bb ldr r3, [r7, #8] 8006adc: 331b adds r3, #27 8006ade: 011b lsls r3, r3, #4 8006ae0: 4413 add r3, r2 8006ae2: 3304 adds r3, #4 8006ae4: 681b ldr r3, [r3, #0] 8006ae6: 0a1b lsrs r3, r3, #8 8006ae8: b2da uxtb r2, r3 8006aea: 687b ldr r3, [r7, #4] 8006aec: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; 8006aee: 68fb ldr r3, [r7, #12] 8006af0: 681a ldr r2, [r3, #0] 8006af2: 68bb ldr r3, [r7, #8] 8006af4: 331b adds r3, #27 8006af6: 011b lsls r3, r3, #4 8006af8: 4413 add r3, r2 8006afa: 3304 adds r3, #4 8006afc: 681b ldr r3, [r3, #0] 8006afe: 0c1b lsrs r3, r3, #16 8006b00: b29a uxth r2, r3 8006b02: 687b ldr r3, [r7, #4] 8006b04: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); 8006b06: 68fb ldr r3, [r7, #12] 8006b08: 681a ldr r2, [r3, #0] 8006b0a: 68bb ldr r3, [r7, #8] 8006b0c: 011b lsls r3, r3, #4 8006b0e: 4413 add r3, r2 8006b10: f503 73dc add.w r3, r3, #440 @ 0x1b8 8006b14: 681b ldr r3, [r3, #0] 8006b16: b2da uxtb r2, r3 8006b18: 683b ldr r3, [r7, #0] 8006b1a: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); 8006b1c: 68fb ldr r3, [r7, #12] 8006b1e: 681a ldr r2, [r3, #0] 8006b20: 68bb ldr r3, [r7, #8] 8006b22: 011b lsls r3, r3, #4 8006b24: 4413 add r3, r2 8006b26: f503 73dc add.w r3, r3, #440 @ 0x1b8 8006b2a: 681b ldr r3, [r3, #0] 8006b2c: 0a1a lsrs r2, r3, #8 8006b2e: 683b ldr r3, [r7, #0] 8006b30: 3301 adds r3, #1 8006b32: b2d2 uxtb r2, r2 8006b34: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); 8006b36: 68fb ldr r3, [r7, #12] 8006b38: 681a ldr r2, [r3, #0] 8006b3a: 68bb ldr r3, [r7, #8] 8006b3c: 011b lsls r3, r3, #4 8006b3e: 4413 add r3, r2 8006b40: f503 73dc add.w r3, r3, #440 @ 0x1b8 8006b44: 681b ldr r3, [r3, #0] 8006b46: 0c1a lsrs r2, r3, #16 8006b48: 683b ldr r3, [r7, #0] 8006b4a: 3302 adds r3, #2 8006b4c: b2d2 uxtb r2, r2 8006b4e: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); 8006b50: 68fb ldr r3, [r7, #12] 8006b52: 681a ldr r2, [r3, #0] 8006b54: 68bb ldr r3, [r7, #8] 8006b56: 011b lsls r3, r3, #4 8006b58: 4413 add r3, r2 8006b5a: f503 73dc add.w r3, r3, #440 @ 0x1b8 8006b5e: 681b ldr r3, [r3, #0] 8006b60: 0e1a lsrs r2, r3, #24 8006b62: 683b ldr r3, [r7, #0] 8006b64: 3303 adds r3, #3 8006b66: b2d2 uxtb r2, r2 8006b68: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); 8006b6a: 68fb ldr r3, [r7, #12] 8006b6c: 681a ldr r2, [r3, #0] 8006b6e: 68bb ldr r3, [r7, #8] 8006b70: 011b lsls r3, r3, #4 8006b72: 4413 add r3, r2 8006b74: f503 73de add.w r3, r3, #444 @ 0x1bc 8006b78: 681a ldr r2, [r3, #0] 8006b7a: 683b ldr r3, [r7, #0] 8006b7c: 3304 adds r3, #4 8006b7e: b2d2 uxtb r2, r2 8006b80: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); 8006b82: 68fb ldr r3, [r7, #12] 8006b84: 681a ldr r2, [r3, #0] 8006b86: 68bb ldr r3, [r7, #8] 8006b88: 011b lsls r3, r3, #4 8006b8a: 4413 add r3, r2 8006b8c: f503 73de add.w r3, r3, #444 @ 0x1bc 8006b90: 681b ldr r3, [r3, #0] 8006b92: 0a1a lsrs r2, r3, #8 8006b94: 683b ldr r3, [r7, #0] 8006b96: 3305 adds r3, #5 8006b98: b2d2 uxtb r2, r2 8006b9a: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); 8006b9c: 68fb ldr r3, [r7, #12] 8006b9e: 681a ldr r2, [r3, #0] 8006ba0: 68bb ldr r3, [r7, #8] 8006ba2: 011b lsls r3, r3, #4 8006ba4: 4413 add r3, r2 8006ba6: f503 73de add.w r3, r3, #444 @ 0x1bc 8006baa: 681b ldr r3, [r3, #0] 8006bac: 0c1a lsrs r2, r3, #16 8006bae: 683b ldr r3, [r7, #0] 8006bb0: 3306 adds r3, #6 8006bb2: b2d2 uxtb r2, r2 8006bb4: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); 8006bb6: 68fb ldr r3, [r7, #12] 8006bb8: 681a ldr r2, [r3, #0] 8006bba: 68bb ldr r3, [r7, #8] 8006bbc: 011b lsls r3, r3, #4 8006bbe: 4413 add r3, r2 8006bc0: f503 73de add.w r3, r3, #444 @ 0x1bc 8006bc4: 681b ldr r3, [r3, #0] 8006bc6: 0e1a lsrs r2, r3, #24 8006bc8: 683b ldr r3, [r7, #0] 8006bca: 3307 adds r3, #7 8006bcc: b2d2 uxtb r2, r2 8006bce: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 8006bd0: 68bb ldr r3, [r7, #8] 8006bd2: 2b00 cmp r3, #0 8006bd4: d108 bne.n 8006be8 { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); 8006bd6: 68fb ldr r3, [r7, #12] 8006bd8: 681b ldr r3, [r3, #0] 8006bda: 68da ldr r2, [r3, #12] 8006bdc: 68fb ldr r3, [r7, #12] 8006bde: 681b ldr r3, [r3, #0] 8006be0: f042 0220 orr.w r2, r2, #32 8006be4: 60da str r2, [r3, #12] 8006be6: e007 b.n 8006bf8 } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); 8006be8: 68fb ldr r3, [r7, #12] 8006bea: 681b ldr r3, [r3, #0] 8006bec: 691a ldr r2, [r3, #16] 8006bee: 68fb ldr r3, [r7, #12] 8006bf0: 681b ldr r3, [r3, #0] 8006bf2: f042 0220 orr.w r2, r2, #32 8006bf6: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; 8006bf8: 2300 movs r3, #0 8006bfa: e006 b.n 8006c0a } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8006bfc: 68fb ldr r3, [r7, #12] 8006bfe: 6a5b ldr r3, [r3, #36] @ 0x24 8006c00: f443 2280 orr.w r2, r3, #262144 @ 0x40000 8006c04: 68fb ldr r3, [r7, #12] 8006c06: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 8006c08: 2301 movs r3, #1 } } 8006c0a: 4618 mov r0, r3 8006c0c: 371c adds r7, #28 8006c0e: 46bd mov sp, r7 8006c10: bc80 pop {r7} 8006c12: 4770 bx lr 08006c14 : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { 8006c14: b480 push {r7} 8006c16: b085 sub sp, #20 8006c18: af00 add r7, sp, #0 8006c1a: 6078 str r0, [r7, #4] 8006c1c: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 8006c1e: 687b ldr r3, [r7, #4] 8006c20: f893 3020 ldrb.w r3, [r3, #32] 8006c24: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || 8006c26: 7bfb ldrb r3, [r7, #15] 8006c28: 2b01 cmp r3, #1 8006c2a: d002 beq.n 8006c32 8006c2c: 7bfb ldrb r3, [r7, #15] 8006c2e: 2b02 cmp r3, #2 8006c30: d109 bne.n 8006c46 (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); 8006c32: 687b ldr r3, [r7, #4] 8006c34: 681b ldr r3, [r3, #0] 8006c36: 6959 ldr r1, [r3, #20] 8006c38: 687b ldr r3, [r7, #4] 8006c3a: 681b ldr r3, [r3, #0] 8006c3c: 683a ldr r2, [r7, #0] 8006c3e: 430a orrs r2, r1 8006c40: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; 8006c42: 2300 movs r3, #0 8006c44: e006 b.n 8006c54 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8006c46: 687b ldr r3, [r7, #4] 8006c48: 6a5b ldr r3, [r3, #36] @ 0x24 8006c4a: f443 2280 orr.w r2, r3, #262144 @ 0x40000 8006c4e: 687b ldr r3, [r7, #4] 8006c50: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 8006c52: 2301 movs r3, #1 } } 8006c54: 4618 mov r0, r3 8006c56: 3714 adds r7, #20 8006c58: 46bd mov sp, r7 8006c5a: bc80 pop {r7} 8006c5c: 4770 bx lr 08006c5e : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { 8006c5e: b580 push {r7, lr} 8006c60: b08a sub sp, #40 @ 0x28 8006c62: af00 add r7, sp, #0 8006c64: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; 8006c66: 2300 movs r3, #0 8006c68: 627b str r3, [r7, #36] @ 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); 8006c6a: 687b ldr r3, [r7, #4] 8006c6c: 681b ldr r3, [r3, #0] 8006c6e: 695b ldr r3, [r3, #20] 8006c70: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); 8006c72: 687b ldr r3, [r7, #4] 8006c74: 681b ldr r3, [r3, #0] 8006c76: 685b ldr r3, [r3, #4] 8006c78: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); 8006c7a: 687b ldr r3, [r7, #4] 8006c7c: 681b ldr r3, [r3, #0] 8006c7e: 689b ldr r3, [r3, #8] 8006c80: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); 8006c82: 687b ldr r3, [r7, #4] 8006c84: 681b ldr r3, [r3, #0] 8006c86: 68db ldr r3, [r3, #12] 8006c88: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); 8006c8a: 687b ldr r3, [r7, #4] 8006c8c: 681b ldr r3, [r3, #0] 8006c8e: 691b ldr r3, [r3, #16] 8006c90: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); 8006c92: 687b ldr r3, [r7, #4] 8006c94: 681b ldr r3, [r3, #0] 8006c96: 699b ldr r3, [r3, #24] 8006c98: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) 8006c9a: 6a3b ldr r3, [r7, #32] 8006c9c: f003 0301 and.w r3, r3, #1 8006ca0: 2b00 cmp r3, #0 8006ca2: d07c beq.n 8006d9e { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) 8006ca4: 69bb ldr r3, [r7, #24] 8006ca6: f003 0301 and.w r3, r3, #1 8006caa: 2b00 cmp r3, #0 8006cac: d023 beq.n 8006cf6 { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); 8006cae: 687b ldr r3, [r7, #4] 8006cb0: 681b ldr r3, [r3, #0] 8006cb2: 2201 movs r2, #1 8006cb4: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) 8006cb6: 69bb ldr r3, [r7, #24] 8006cb8: f003 0302 and.w r3, r3, #2 8006cbc: 2b00 cmp r3, #0 8006cbe: d003 beq.n 8006cc8 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); 8006cc0: 6878 ldr r0, [r7, #4] 8006cc2: f7fd fb49 bl 8004358 8006cc6: e016 b.n 8006cf6 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) 8006cc8: 69bb ldr r3, [r7, #24] 8006cca: f003 0304 and.w r3, r3, #4 8006cce: 2b00 cmp r3, #0 8006cd0: d004 beq.n 8006cdc { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; 8006cd2: 6a7b ldr r3, [r7, #36] @ 0x24 8006cd4: f443 6300 orr.w r3, r3, #2048 @ 0x800 8006cd8: 627b str r3, [r7, #36] @ 0x24 8006cda: e00c b.n 8006cf6 } else if ((tsrflags & CAN_TSR_TERR0) != 0U) 8006cdc: 69bb ldr r3, [r7, #24] 8006cde: f003 0308 and.w r3, r3, #8 8006ce2: 2b00 cmp r3, #0 8006ce4: d004 beq.n 8006cf0 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; 8006ce6: 6a7b ldr r3, [r7, #36] @ 0x24 8006ce8: f443 5380 orr.w r3, r3, #4096 @ 0x1000 8006cec: 627b str r3, [r7, #36] @ 0x24 8006cee: e002 b.n 8006cf6 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); 8006cf0: 6878 ldr r0, [r7, #4] 8006cf2: f000 f96b bl 8006fcc } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) 8006cf6: 69bb ldr r3, [r7, #24] 8006cf8: f403 7380 and.w r3, r3, #256 @ 0x100 8006cfc: 2b00 cmp r3, #0 8006cfe: d024 beq.n 8006d4a { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); 8006d00: 687b ldr r3, [r7, #4] 8006d02: 681b ldr r3, [r3, #0] 8006d04: f44f 7280 mov.w r2, #256 @ 0x100 8006d08: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) 8006d0a: 69bb ldr r3, [r7, #24] 8006d0c: f403 7300 and.w r3, r3, #512 @ 0x200 8006d10: 2b00 cmp r3, #0 8006d12: d003 beq.n 8006d1c #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); 8006d14: 6878 ldr r0, [r7, #4] 8006d16: f7fd fb39 bl 800438c 8006d1a: e016 b.n 8006d4a #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) 8006d1c: 69bb ldr r3, [r7, #24] 8006d1e: f403 6380 and.w r3, r3, #1024 @ 0x400 8006d22: 2b00 cmp r3, #0 8006d24: d004 beq.n 8006d30 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; 8006d26: 6a7b ldr r3, [r7, #36] @ 0x24 8006d28: f443 5300 orr.w r3, r3, #8192 @ 0x2000 8006d2c: 627b str r3, [r7, #36] @ 0x24 8006d2e: e00c b.n 8006d4a } else if ((tsrflags & CAN_TSR_TERR1) != 0U) 8006d30: 69bb ldr r3, [r7, #24] 8006d32: f403 6300 and.w r3, r3, #2048 @ 0x800 8006d36: 2b00 cmp r3, #0 8006d38: d004 beq.n 8006d44 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; 8006d3a: 6a7b ldr r3, [r7, #36] @ 0x24 8006d3c: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8006d40: 627b str r3, [r7, #36] @ 0x24 8006d42: e002 b.n 8006d4a #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); 8006d44: 6878 ldr r0, [r7, #4] 8006d46: f000 f94a bl 8006fde } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) 8006d4a: 69bb ldr r3, [r7, #24] 8006d4c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8006d50: 2b00 cmp r3, #0 8006d52: d024 beq.n 8006d9e { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); 8006d54: 687b ldr r3, [r7, #4] 8006d56: 681b ldr r3, [r3, #0] 8006d58: f44f 3280 mov.w r2, #65536 @ 0x10000 8006d5c: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) 8006d5e: 69bb ldr r3, [r7, #24] 8006d60: f403 3300 and.w r3, r3, #131072 @ 0x20000 8006d64: 2b00 cmp r3, #0 8006d66: d003 beq.n 8006d70 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); 8006d68: 6878 ldr r0, [r7, #4] 8006d6a: f7fd fb29 bl 80043c0 8006d6e: e016 b.n 8006d9e #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) 8006d70: 69bb ldr r3, [r7, #24] 8006d72: f403 2380 and.w r3, r3, #262144 @ 0x40000 8006d76: 2b00 cmp r3, #0 8006d78: d004 beq.n 8006d84 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; 8006d7a: 6a7b ldr r3, [r7, #36] @ 0x24 8006d7c: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8006d80: 627b str r3, [r7, #36] @ 0x24 8006d82: e00c b.n 8006d9e } else if ((tsrflags & CAN_TSR_TERR2) != 0U) 8006d84: 69bb ldr r3, [r7, #24] 8006d86: f403 2300 and.w r3, r3, #524288 @ 0x80000 8006d8a: 2b00 cmp r3, #0 8006d8c: d004 beq.n 8006d98 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; 8006d8e: 6a7b ldr r3, [r7, #36] @ 0x24 8006d90: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8006d94: 627b str r3, [r7, #36] @ 0x24 8006d96: e002 b.n 8006d9e #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); 8006d98: 6878 ldr r0, [r7, #4] 8006d9a: f000 f929 bl 8006ff0 } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) 8006d9e: 6a3b ldr r3, [r7, #32] 8006da0: f003 0308 and.w r3, r3, #8 8006da4: 2b00 cmp r3, #0 8006da6: d00c beq.n 8006dc2 { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) 8006da8: 697b ldr r3, [r7, #20] 8006daa: f003 0310 and.w r3, r3, #16 8006dae: 2b00 cmp r3, #0 8006db0: d007 beq.n 8006dc2 { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; 8006db2: 6a7b ldr r3, [r7, #36] @ 0x24 8006db4: f443 7300 orr.w r3, r3, #512 @ 0x200 8006db8: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); 8006dba: 687b ldr r3, [r7, #4] 8006dbc: 681b ldr r3, [r3, #0] 8006dbe: 2210 movs r2, #16 8006dc0: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) 8006dc2: 6a3b ldr r3, [r7, #32] 8006dc4: f003 0304 and.w r3, r3, #4 8006dc8: 2b00 cmp r3, #0 8006dca: d00b beq.n 8006de4 { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) 8006dcc: 697b ldr r3, [r7, #20] 8006dce: f003 0308 and.w r3, r3, #8 8006dd2: 2b00 cmp r3, #0 8006dd4: d006 beq.n 8006de4 { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); 8006dd6: 687b ldr r3, [r7, #4] 8006dd8: 681b ldr r3, [r3, #0] 8006dda: 2208 movs r2, #8 8006ddc: 60da str r2, [r3, #12] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); 8006dde: 6878 ldr r0, [r7, #4] 8006de0: f000 f90f bl 8007002 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) 8006de4: 6a3b ldr r3, [r7, #32] 8006de6: f003 0302 and.w r3, r3, #2 8006dea: 2b00 cmp r3, #0 8006dec: d009 beq.n 8006e02 { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) 8006dee: 687b ldr r3, [r7, #4] 8006df0: 681b ldr r3, [r3, #0] 8006df2: 68db ldr r3, [r3, #12] 8006df4: f003 0303 and.w r3, r3, #3 8006df8: 2b00 cmp r3, #0 8006dfa: d002 beq.n 8006e02 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); 8006dfc: 6878 ldr r0, [r7, #4] 8006dfe: f7fc ff9d bl 8003d3c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) 8006e02: 6a3b ldr r3, [r7, #32] 8006e04: f003 0340 and.w r3, r3, #64 @ 0x40 8006e08: 2b00 cmp r3, #0 8006e0a: d00c beq.n 8006e26 { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) 8006e0c: 693b ldr r3, [r7, #16] 8006e0e: f003 0310 and.w r3, r3, #16 8006e12: 2b00 cmp r3, #0 8006e14: d007 beq.n 8006e26 { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; 8006e16: 6a7b ldr r3, [r7, #36] @ 0x24 8006e18: f443 6380 orr.w r3, r3, #1024 @ 0x400 8006e1c: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); 8006e1e: 687b ldr r3, [r7, #4] 8006e20: 681b ldr r3, [r3, #0] 8006e22: 2210 movs r2, #16 8006e24: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) 8006e26: 6a3b ldr r3, [r7, #32] 8006e28: f003 0320 and.w r3, r3, #32 8006e2c: 2b00 cmp r3, #0 8006e2e: d00b beq.n 8006e48 { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) 8006e30: 693b ldr r3, [r7, #16] 8006e32: f003 0308 and.w r3, r3, #8 8006e36: 2b00 cmp r3, #0 8006e38: d006 beq.n 8006e48 { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); 8006e3a: 687b ldr r3, [r7, #4] 8006e3c: 681b ldr r3, [r3, #0] 8006e3e: 2208 movs r2, #8 8006e40: 611a str r2, [r3, #16] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); 8006e42: 6878 ldr r0, [r7, #4] 8006e44: f000 f8e6 bl 8007014 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) 8006e48: 6a3b ldr r3, [r7, #32] 8006e4a: f003 0310 and.w r3, r3, #16 8006e4e: 2b00 cmp r3, #0 8006e50: d009 beq.n 8006e66 { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) 8006e52: 687b ldr r3, [r7, #4] 8006e54: 681b ldr r3, [r3, #0] 8006e56: 691b ldr r3, [r3, #16] 8006e58: f003 0303 and.w r3, r3, #3 8006e5c: 2b00 cmp r3, #0 8006e5e: d002 beq.n 8006e66 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); 8006e60: 6878 ldr r0, [r7, #4] 8006e62: f7fd fa23 bl 80042ac #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) 8006e66: 6a3b ldr r3, [r7, #32] 8006e68: f403 3300 and.w r3, r3, #131072 @ 0x20000 8006e6c: 2b00 cmp r3, #0 8006e6e: d00b beq.n 8006e88 { if ((msrflags & CAN_MSR_SLAKI) != 0U) 8006e70: 69fb ldr r3, [r7, #28] 8006e72: f003 0310 and.w r3, r3, #16 8006e76: 2b00 cmp r3, #0 8006e78: d006 beq.n 8006e88 { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); 8006e7a: 687b ldr r3, [r7, #4] 8006e7c: 681b ldr r3, [r3, #0] 8006e7e: 2210 movs r2, #16 8006e80: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->SleepCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); 8006e82: 6878 ldr r0, [r7, #4] 8006e84: f000 f8cf bl 8007026 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ if ((interrupts & CAN_IT_WAKEUP) != 0U) 8006e88: 6a3b ldr r3, [r7, #32] 8006e8a: f403 3380 and.w r3, r3, #65536 @ 0x10000 8006e8e: 2b00 cmp r3, #0 8006e90: d00b beq.n 8006eaa { if ((msrflags & CAN_MSR_WKUI) != 0U) 8006e92: 69fb ldr r3, [r7, #28] 8006e94: f003 0308 and.w r3, r3, #8 8006e98: 2b00 cmp r3, #0 8006e9a: d006 beq.n 8006eaa { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); 8006e9c: 687b ldr r3, [r7, #4] 8006e9e: 681b ldr r3, [r3, #0] 8006ea0: 2208 movs r2, #8 8006ea2: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->WakeUpFromRxMsgCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); 8006ea4: 6878 ldr r0, [r7, #4] 8006ea6: f000 f8c7 bl 8007038 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ if ((interrupts & CAN_IT_ERROR) != 0U) 8006eaa: 6a3b ldr r3, [r7, #32] 8006eac: f403 4300 and.w r3, r3, #32768 @ 0x8000 8006eb0: 2b00 cmp r3, #0 8006eb2: d07b beq.n 8006fac { if ((msrflags & CAN_MSR_ERRI) != 0U) 8006eb4: 69fb ldr r3, [r7, #28] 8006eb6: f003 0304 and.w r3, r3, #4 8006eba: 2b00 cmp r3, #0 8006ebc: d072 beq.n 8006fa4 { /* Check Error Warning Flag */ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 8006ebe: 6a3b ldr r3, [r7, #32] 8006ec0: f403 7380 and.w r3, r3, #256 @ 0x100 8006ec4: 2b00 cmp r3, #0 8006ec6: d008 beq.n 8006eda ((esrflags & CAN_ESR_EWGF) != 0U)) 8006ec8: 68fb ldr r3, [r7, #12] 8006eca: f003 0301 and.w r3, r3, #1 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 8006ece: 2b00 cmp r3, #0 8006ed0: d003 beq.n 8006eda { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; 8006ed2: 6a7b ldr r3, [r7, #36] @ 0x24 8006ed4: f043 0301 orr.w r3, r3, #1 8006ed8: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Warning Flag as read-only */ } /* Check Error Passive Flag */ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 8006eda: 6a3b ldr r3, [r7, #32] 8006edc: f403 7300 and.w r3, r3, #512 @ 0x200 8006ee0: 2b00 cmp r3, #0 8006ee2: d008 beq.n 8006ef6 ((esrflags & CAN_ESR_EPVF) != 0U)) 8006ee4: 68fb ldr r3, [r7, #12] 8006ee6: f003 0302 and.w r3, r3, #2 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 8006eea: 2b00 cmp r3, #0 8006eec: d003 beq.n 8006ef6 { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; 8006eee: 6a7b ldr r3, [r7, #36] @ 0x24 8006ef0: f043 0302 orr.w r3, r3, #2 8006ef4: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-off Flag */ if (((interrupts & CAN_IT_BUSOFF) != 0U) && 8006ef6: 6a3b ldr r3, [r7, #32] 8006ef8: f403 6380 and.w r3, r3, #1024 @ 0x400 8006efc: 2b00 cmp r3, #0 8006efe: d008 beq.n 8006f12 ((esrflags & CAN_ESR_BOFF) != 0U)) 8006f00: 68fb ldr r3, [r7, #12] 8006f02: f003 0304 and.w r3, r3, #4 if (((interrupts & CAN_IT_BUSOFF) != 0U) && 8006f06: 2b00 cmp r3, #0 8006f08: d003 beq.n 8006f12 { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; 8006f0a: 6a7b ldr r3, [r7, #36] @ 0x24 8006f0c: f043 0304 orr.w r3, r3, #4 8006f10: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Bus-Off as read-only */ } /* Check Last Error Code Flag */ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 8006f12: 6a3b ldr r3, [r7, #32] 8006f14: f403 6300 and.w r3, r3, #2048 @ 0x800 8006f18: 2b00 cmp r3, #0 8006f1a: d043 beq.n 8006fa4 ((esrflags & CAN_ESR_LEC) != 0U)) 8006f1c: 68fb ldr r3, [r7, #12] 8006f1e: f003 0370 and.w r3, r3, #112 @ 0x70 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 8006f22: 2b00 cmp r3, #0 8006f24: d03e beq.n 8006fa4 { switch (esrflags & CAN_ESR_LEC) 8006f26: 68fb ldr r3, [r7, #12] 8006f28: f003 0370 and.w r3, r3, #112 @ 0x70 8006f2c: 2b60 cmp r3, #96 @ 0x60 8006f2e: d02b beq.n 8006f88 8006f30: 2b60 cmp r3, #96 @ 0x60 8006f32: d82e bhi.n 8006f92 8006f34: 2b50 cmp r3, #80 @ 0x50 8006f36: d022 beq.n 8006f7e 8006f38: 2b50 cmp r3, #80 @ 0x50 8006f3a: d82a bhi.n 8006f92 8006f3c: 2b40 cmp r3, #64 @ 0x40 8006f3e: d019 beq.n 8006f74 8006f40: 2b40 cmp r3, #64 @ 0x40 8006f42: d826 bhi.n 8006f92 8006f44: 2b30 cmp r3, #48 @ 0x30 8006f46: d010 beq.n 8006f6a 8006f48: 2b30 cmp r3, #48 @ 0x30 8006f4a: d822 bhi.n 8006f92 8006f4c: 2b10 cmp r3, #16 8006f4e: d002 beq.n 8006f56 8006f50: 2b20 cmp r3, #32 8006f52: d005 beq.n 8006f60 case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): /* Set CAN error code to CRC error */ errorcode |= HAL_CAN_ERROR_CRC; break; default: break; 8006f54: e01d b.n 8006f92 errorcode |= HAL_CAN_ERROR_STF; 8006f56: 6a7b ldr r3, [r7, #36] @ 0x24 8006f58: f043 0308 orr.w r3, r3, #8 8006f5c: 627b str r3, [r7, #36] @ 0x24 break; 8006f5e: e019 b.n 8006f94 errorcode |= HAL_CAN_ERROR_FOR; 8006f60: 6a7b ldr r3, [r7, #36] @ 0x24 8006f62: f043 0310 orr.w r3, r3, #16 8006f66: 627b str r3, [r7, #36] @ 0x24 break; 8006f68: e014 b.n 8006f94 errorcode |= HAL_CAN_ERROR_ACK; 8006f6a: 6a7b ldr r3, [r7, #36] @ 0x24 8006f6c: f043 0320 orr.w r3, r3, #32 8006f70: 627b str r3, [r7, #36] @ 0x24 break; 8006f72: e00f b.n 8006f94 errorcode |= HAL_CAN_ERROR_BR; 8006f74: 6a7b ldr r3, [r7, #36] @ 0x24 8006f76: f043 0340 orr.w r3, r3, #64 @ 0x40 8006f7a: 627b str r3, [r7, #36] @ 0x24 break; 8006f7c: e00a b.n 8006f94 errorcode |= HAL_CAN_ERROR_BD; 8006f7e: 6a7b ldr r3, [r7, #36] @ 0x24 8006f80: f043 0380 orr.w r3, r3, #128 @ 0x80 8006f84: 627b str r3, [r7, #36] @ 0x24 break; 8006f86: e005 b.n 8006f94 errorcode |= HAL_CAN_ERROR_CRC; 8006f88: 6a7b ldr r3, [r7, #36] @ 0x24 8006f8a: f443 7380 orr.w r3, r3, #256 @ 0x100 8006f8e: 627b str r3, [r7, #36] @ 0x24 break; 8006f90: e000 b.n 8006f94 break; 8006f92: bf00 nop } /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); 8006f94: 687b ldr r3, [r7, #4] 8006f96: 681b ldr r3, [r3, #0] 8006f98: 699a ldr r2, [r3, #24] 8006f9a: 687b ldr r3, [r7, #4] 8006f9c: 681b ldr r3, [r3, #0] 8006f9e: f022 0270 bic.w r2, r2, #112 @ 0x70 8006fa2: 619a str r2, [r3, #24] } } /* Clear ERRI Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); 8006fa4: 687b ldr r3, [r7, #4] 8006fa6: 681b ldr r3, [r3, #0] 8006fa8: 2204 movs r2, #4 8006faa: 605a str r2, [r3, #4] } /* Call the Error call Back in case of Errors */ if (errorcode != HAL_CAN_ERROR_NONE) 8006fac: 6a7b ldr r3, [r7, #36] @ 0x24 8006fae: 2b00 cmp r3, #0 8006fb0: d008 beq.n 8006fc4 { /* Update error code in handle */ hcan->ErrorCode |= errorcode; 8006fb2: 687b ldr r3, [r7, #4] 8006fb4: 6a5a ldr r2, [r3, #36] @ 0x24 8006fb6: 6a7b ldr r3, [r7, #36] @ 0x24 8006fb8: 431a orrs r2, r3 8006fba: 687b ldr r3, [r7, #4] 8006fbc: 625a str r2, [r3, #36] @ 0x24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->ErrorCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); 8006fbe: 6878 ldr r0, [r7, #4] 8006fc0: f000 f843 bl 800704a #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } 8006fc4: bf00 nop 8006fc6: 3728 adds r7, #40 @ 0x28 8006fc8: 46bd mov sp, r7 8006fca: bd80 pop {r7, pc} 08006fcc : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { 8006fcc: b480 push {r7} 8006fce: b083 sub sp, #12 8006fd0: af00 add r7, sp, #0 8006fd2: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } 8006fd4: bf00 nop 8006fd6: 370c adds r7, #12 8006fd8: 46bd mov sp, r7 8006fda: bc80 pop {r7} 8006fdc: 4770 bx lr 08006fde : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { 8006fde: b480 push {r7} 8006fe0: b083 sub sp, #12 8006fe2: af00 add r7, sp, #0 8006fe4: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } 8006fe6: bf00 nop 8006fe8: 370c adds r7, #12 8006fea: 46bd mov sp, r7 8006fec: bc80 pop {r7} 8006fee: 4770 bx lr 08006ff0 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { 8006ff0: b480 push {r7} 8006ff2: b083 sub sp, #12 8006ff4: af00 add r7, sp, #0 8006ff6: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } 8006ff8: bf00 nop 8006ffa: 370c adds r7, #12 8006ffc: 46bd mov sp, r7 8006ffe: bc80 pop {r7} 8007000: 4770 bx lr 08007002 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { 8007002: b480 push {r7} 8007004: b083 sub sp, #12 8007006: af00 add r7, sp, #0 8007008: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } 800700a: bf00 nop 800700c: 370c adds r7, #12 800700e: 46bd mov sp, r7 8007010: bc80 pop {r7} 8007012: 4770 bx lr 08007014 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { 8007014: b480 push {r7} 8007016: b083 sub sp, #12 8007018: af00 add r7, sp, #0 800701a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } 800701c: bf00 nop 800701e: 370c adds r7, #12 8007020: 46bd mov sp, r7 8007022: bc80 pop {r7} 8007024: 4770 bx lr 08007026 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { 8007026: b480 push {r7} 8007028: b083 sub sp, #12 800702a: af00 add r7, sp, #0 800702c: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } 800702e: bf00 nop 8007030: 370c adds r7, #12 8007032: 46bd mov sp, r7 8007034: bc80 pop {r7} 8007036: 4770 bx lr 08007038 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { 8007038: b480 push {r7} 800703a: b083 sub sp, #12 800703c: af00 add r7, sp, #0 800703e: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } 8007040: bf00 nop 8007042: 370c adds r7, #12 8007044: 46bd mov sp, r7 8007046: bc80 pop {r7} 8007048: 4770 bx lr 0800704a : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { 800704a: b480 push {r7} 800704c: b083 sub sp, #12 800704e: af00 add r7, sp, #0 8007050: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } 8007052: bf00 nop 8007054: 370c adds r7, #12 8007056: 46bd mov sp, r7 8007058: bc80 pop {r7} 800705a: 4770 bx lr 0800705c <__NVIC_SetPriorityGrouping>: { 800705c: b480 push {r7} 800705e: b085 sub sp, #20 8007060: af00 add r7, sp, #0 8007062: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8007064: 687b ldr r3, [r7, #4] 8007066: f003 0307 and.w r3, r3, #7 800706a: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 800706c: 4b0c ldr r3, [pc, #48] @ (80070a0 <__NVIC_SetPriorityGrouping+0x44>) 800706e: 68db ldr r3, [r3, #12] 8007070: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8007072: 68ba ldr r2, [r7, #8] 8007074: f64f 03ff movw r3, #63743 @ 0xf8ff 8007078: 4013 ands r3, r2 800707a: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800707c: 68fb ldr r3, [r7, #12] 800707e: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8007080: 68bb ldr r3, [r7, #8] 8007082: 4313 orrs r3, r2 reg_value = (reg_value | 8007084: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8007088: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800708c: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800708e: 4a04 ldr r2, [pc, #16] @ (80070a0 <__NVIC_SetPriorityGrouping+0x44>) 8007090: 68bb ldr r3, [r7, #8] 8007092: 60d3 str r3, [r2, #12] } 8007094: bf00 nop 8007096: 3714 adds r7, #20 8007098: 46bd mov sp, r7 800709a: bc80 pop {r7} 800709c: 4770 bx lr 800709e: bf00 nop 80070a0: e000ed00 .word 0xe000ed00 080070a4 <__NVIC_GetPriorityGrouping>: { 80070a4: b480 push {r7} 80070a6: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80070a8: 4b04 ldr r3, [pc, #16] @ (80070bc <__NVIC_GetPriorityGrouping+0x18>) 80070aa: 68db ldr r3, [r3, #12] 80070ac: 0a1b lsrs r3, r3, #8 80070ae: f003 0307 and.w r3, r3, #7 } 80070b2: 4618 mov r0, r3 80070b4: 46bd mov sp, r7 80070b6: bc80 pop {r7} 80070b8: 4770 bx lr 80070ba: bf00 nop 80070bc: e000ed00 .word 0xe000ed00 080070c0 <__NVIC_EnableIRQ>: { 80070c0: b480 push {r7} 80070c2: b083 sub sp, #12 80070c4: af00 add r7, sp, #0 80070c6: 4603 mov r3, r0 80070c8: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80070ca: f997 3007 ldrsb.w r3, [r7, #7] 80070ce: 2b00 cmp r3, #0 80070d0: db0b blt.n 80070ea <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80070d2: 79fb ldrb r3, [r7, #7] 80070d4: f003 021f and.w r2, r3, #31 80070d8: 4906 ldr r1, [pc, #24] @ (80070f4 <__NVIC_EnableIRQ+0x34>) 80070da: f997 3007 ldrsb.w r3, [r7, #7] 80070de: 095b lsrs r3, r3, #5 80070e0: 2001 movs r0, #1 80070e2: fa00 f202 lsl.w r2, r0, r2 80070e6: f841 2023 str.w r2, [r1, r3, lsl #2] } 80070ea: bf00 nop 80070ec: 370c adds r7, #12 80070ee: 46bd mov sp, r7 80070f0: bc80 pop {r7} 80070f2: 4770 bx lr 80070f4: e000e100 .word 0xe000e100 080070f8 <__NVIC_SetPriority>: { 80070f8: b480 push {r7} 80070fa: b083 sub sp, #12 80070fc: af00 add r7, sp, #0 80070fe: 4603 mov r3, r0 8007100: 6039 str r1, [r7, #0] 8007102: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8007104: f997 3007 ldrsb.w r3, [r7, #7] 8007108: 2b00 cmp r3, #0 800710a: db0a blt.n 8007122 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800710c: 683b ldr r3, [r7, #0] 800710e: b2da uxtb r2, r3 8007110: 490c ldr r1, [pc, #48] @ (8007144 <__NVIC_SetPriority+0x4c>) 8007112: f997 3007 ldrsb.w r3, [r7, #7] 8007116: 0112 lsls r2, r2, #4 8007118: b2d2 uxtb r2, r2 800711a: 440b add r3, r1 800711c: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 8007120: e00a b.n 8007138 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8007122: 683b ldr r3, [r7, #0] 8007124: b2da uxtb r2, r3 8007126: 4908 ldr r1, [pc, #32] @ (8007148 <__NVIC_SetPriority+0x50>) 8007128: 79fb ldrb r3, [r7, #7] 800712a: f003 030f and.w r3, r3, #15 800712e: 3b04 subs r3, #4 8007130: 0112 lsls r2, r2, #4 8007132: b2d2 uxtb r2, r2 8007134: 440b add r3, r1 8007136: 761a strb r2, [r3, #24] } 8007138: bf00 nop 800713a: 370c adds r7, #12 800713c: 46bd mov sp, r7 800713e: bc80 pop {r7} 8007140: 4770 bx lr 8007142: bf00 nop 8007144: e000e100 .word 0xe000e100 8007148: e000ed00 .word 0xe000ed00 0800714c : { 800714c: b480 push {r7} 800714e: b089 sub sp, #36 @ 0x24 8007150: af00 add r7, sp, #0 8007152: 60f8 str r0, [r7, #12] 8007154: 60b9 str r1, [r7, #8] 8007156: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8007158: 68fb ldr r3, [r7, #12] 800715a: f003 0307 and.w r3, r3, #7 800715e: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8007160: 69fb ldr r3, [r7, #28] 8007162: f1c3 0307 rsb r3, r3, #7 8007166: 2b04 cmp r3, #4 8007168: bf28 it cs 800716a: 2304 movcs r3, #4 800716c: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800716e: 69fb ldr r3, [r7, #28] 8007170: 3304 adds r3, #4 8007172: 2b06 cmp r3, #6 8007174: d902 bls.n 800717c 8007176: 69fb ldr r3, [r7, #28] 8007178: 3b03 subs r3, #3 800717a: e000 b.n 800717e 800717c: 2300 movs r3, #0 800717e: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8007180: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007184: 69bb ldr r3, [r7, #24] 8007186: fa02 f303 lsl.w r3, r2, r3 800718a: 43da mvns r2, r3 800718c: 68bb ldr r3, [r7, #8] 800718e: 401a ands r2, r3 8007190: 697b ldr r3, [r7, #20] 8007192: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8007194: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8007198: 697b ldr r3, [r7, #20] 800719a: fa01 f303 lsl.w r3, r1, r3 800719e: 43d9 mvns r1, r3 80071a0: 687b ldr r3, [r7, #4] 80071a2: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80071a4: 4313 orrs r3, r2 } 80071a6: 4618 mov r0, r3 80071a8: 3724 adds r7, #36 @ 0x24 80071aa: 46bd mov sp, r7 80071ac: bc80 pop {r7} 80071ae: 4770 bx lr 080071b0 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 80071b0: b580 push {r7, lr} 80071b2: b082 sub sp, #8 80071b4: af00 add r7, sp, #0 80071b6: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80071b8: 687b ldr r3, [r7, #4] 80071ba: 3b01 subs r3, #1 80071bc: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 80071c0: d301 bcc.n 80071c6 { return (1UL); /* Reload value impossible */ 80071c2: 2301 movs r3, #1 80071c4: e00f b.n 80071e6 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80071c6: 4a0a ldr r2, [pc, #40] @ (80071f0 ) 80071c8: 687b ldr r3, [r7, #4] 80071ca: 3b01 subs r3, #1 80071cc: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 80071ce: 210f movs r1, #15 80071d0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80071d4: f7ff ff90 bl 80070f8 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80071d8: 4b05 ldr r3, [pc, #20] @ (80071f0 ) 80071da: 2200 movs r2, #0 80071dc: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80071de: 4b04 ldr r3, [pc, #16] @ (80071f0 ) 80071e0: 2207 movs r2, #7 80071e2: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 80071e4: 2300 movs r3, #0 } 80071e6: 4618 mov r0, r3 80071e8: 3708 adds r7, #8 80071ea: 46bd mov sp, r7 80071ec: bd80 pop {r7, pc} 80071ee: bf00 nop 80071f0: e000e010 .word 0xe000e010 080071f4 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80071f4: b580 push {r7, lr} 80071f6: b082 sub sp, #8 80071f8: af00 add r7, sp, #0 80071fa: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80071fc: 6878 ldr r0, [r7, #4] 80071fe: f7ff ff2d bl 800705c <__NVIC_SetPriorityGrouping> } 8007202: bf00 nop 8007204: 3708 adds r7, #8 8007206: 46bd mov sp, r7 8007208: bd80 pop {r7, pc} 0800720a : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800720a: b580 push {r7, lr} 800720c: b086 sub sp, #24 800720e: af00 add r7, sp, #0 8007210: 4603 mov r3, r0 8007212: 60b9 str r1, [r7, #8] 8007214: 607a str r2, [r7, #4] 8007216: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8007218: 2300 movs r3, #0 800721a: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800721c: f7ff ff42 bl 80070a4 <__NVIC_GetPriorityGrouping> 8007220: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8007222: 687a ldr r2, [r7, #4] 8007224: 68b9 ldr r1, [r7, #8] 8007226: 6978 ldr r0, [r7, #20] 8007228: f7ff ff90 bl 800714c 800722c: 4602 mov r2, r0 800722e: f997 300f ldrsb.w r3, [r7, #15] 8007232: 4611 mov r1, r2 8007234: 4618 mov r0, r3 8007236: f7ff ff5f bl 80070f8 <__NVIC_SetPriority> } 800723a: bf00 nop 800723c: 3718 adds r7, #24 800723e: 46bd mov sp, r7 8007240: bd80 pop {r7, pc} 08007242 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8007242: b580 push {r7, lr} 8007244: b082 sub sp, #8 8007246: af00 add r7, sp, #0 8007248: 4603 mov r3, r0 800724a: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800724c: f997 3007 ldrsb.w r3, [r7, #7] 8007250: 4618 mov r0, r3 8007252: f7ff ff35 bl 80070c0 <__NVIC_EnableIRQ> } 8007256: bf00 nop 8007258: 3708 adds r7, #8 800725a: 46bd mov sp, r7 800725c: bd80 pop {r7, pc} 0800725e : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800725e: b580 push {r7, lr} 8007260: b082 sub sp, #8 8007262: af00 add r7, sp, #0 8007264: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8007266: 6878 ldr r0, [r7, #4] 8007268: f7ff ffa2 bl 80071b0 800726c: 4603 mov r3, r0 } 800726e: 4618 mov r0, r3 8007270: 3708 adds r7, #8 8007272: 46bd mov sp, r7 8007274: bd80 pop {r7, pc} 08007276 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8007276: b480 push {r7} 8007278: b085 sub sp, #20 800727a: af00 add r7, sp, #0 800727c: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800727e: 2300 movs r3, #0 8007280: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 8007282: 687b ldr r3, [r7, #4] 8007284: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 8007288: 2b02 cmp r3, #2 800728a: d008 beq.n 800729e { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800728c: 687b ldr r3, [r7, #4] 800728e: 2204 movs r2, #4 8007290: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8007292: 687b ldr r3, [r7, #4] 8007294: 2200 movs r2, #0 8007296: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800729a: 2301 movs r3, #1 800729c: e020 b.n 80072e0 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800729e: 687b ldr r3, [r7, #4] 80072a0: 681b ldr r3, [r3, #0] 80072a2: 681a ldr r2, [r3, #0] 80072a4: 687b ldr r3, [r7, #4] 80072a6: 681b ldr r3, [r3, #0] 80072a8: f022 020e bic.w r2, r2, #14 80072ac: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 80072ae: 687b ldr r3, [r7, #4] 80072b0: 681b ldr r3, [r3, #0] 80072b2: 681a ldr r2, [r3, #0] 80072b4: 687b ldr r3, [r7, #4] 80072b6: 681b ldr r3, [r3, #0] 80072b8: f022 0201 bic.w r2, r2, #1 80072bc: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 80072be: 687b ldr r3, [r7, #4] 80072c0: 6c1a ldr r2, [r3, #64] @ 0x40 80072c2: 687b ldr r3, [r7, #4] 80072c4: 6bdb ldr r3, [r3, #60] @ 0x3c 80072c6: 2101 movs r1, #1 80072c8: fa01 f202 lsl.w r2, r1, r2 80072cc: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80072ce: 687b ldr r3, [r7, #4] 80072d0: 2201 movs r2, #1 80072d2: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80072d6: 687b ldr r3, [r7, #4] 80072d8: 2200 movs r2, #0 80072da: f883 2020 strb.w r2, [r3, #32] return status; 80072de: 7bfb ldrb r3, [r7, #15] } 80072e0: 4618 mov r0, r3 80072e2: 3714 adds r7, #20 80072e4: 46bd mov sp, r7 80072e6: bc80 pop {r7} 80072e8: 4770 bx lr ... 080072ec : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 80072ec: b580 push {r7, lr} 80072ee: b084 sub sp, #16 80072f0: af00 add r7, sp, #0 80072f2: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80072f4: 2300 movs r3, #0 80072f6: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 80072f8: 687b ldr r3, [r7, #4] 80072fa: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 80072fe: 2b02 cmp r3, #2 8007300: d005 beq.n 800730e { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8007302: 687b ldr r3, [r7, #4] 8007304: 2204 movs r2, #4 8007306: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 8007308: 2301 movs r3, #1 800730a: 73fb strb r3, [r7, #15] 800730c: e0d6 b.n 80074bc } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800730e: 687b ldr r3, [r7, #4] 8007310: 681b ldr r3, [r3, #0] 8007312: 681a ldr r2, [r3, #0] 8007314: 687b ldr r3, [r7, #4] 8007316: 681b ldr r3, [r3, #0] 8007318: f022 020e bic.w r2, r2, #14 800731c: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800731e: 687b ldr r3, [r7, #4] 8007320: 681b ldr r3, [r3, #0] 8007322: 681a ldr r2, [r3, #0] 8007324: 687b ldr r3, [r7, #4] 8007326: 681b ldr r3, [r3, #0] 8007328: f022 0201 bic.w r2, r2, #1 800732c: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 800732e: 687b ldr r3, [r7, #4] 8007330: 681b ldr r3, [r3, #0] 8007332: 461a mov r2, r3 8007334: 4b64 ldr r3, [pc, #400] @ (80074c8 ) 8007336: 429a cmp r2, r3 8007338: d958 bls.n 80073ec 800733a: 687b ldr r3, [r7, #4] 800733c: 681b ldr r3, [r3, #0] 800733e: 4a63 ldr r2, [pc, #396] @ (80074cc ) 8007340: 4293 cmp r3, r2 8007342: d04f beq.n 80073e4 8007344: 687b ldr r3, [r7, #4] 8007346: 681b ldr r3, [r3, #0] 8007348: 4a61 ldr r2, [pc, #388] @ (80074d0 ) 800734a: 4293 cmp r3, r2 800734c: d048 beq.n 80073e0 800734e: 687b ldr r3, [r7, #4] 8007350: 681b ldr r3, [r3, #0] 8007352: 4a60 ldr r2, [pc, #384] @ (80074d4 ) 8007354: 4293 cmp r3, r2 8007356: d040 beq.n 80073da 8007358: 687b ldr r3, [r7, #4] 800735a: 681b ldr r3, [r3, #0] 800735c: 4a5e ldr r2, [pc, #376] @ (80074d8 ) 800735e: 4293 cmp r3, r2 8007360: d038 beq.n 80073d4 8007362: 687b ldr r3, [r7, #4] 8007364: 681b ldr r3, [r3, #0] 8007366: 4a5d ldr r2, [pc, #372] @ (80074dc ) 8007368: 4293 cmp r3, r2 800736a: d030 beq.n 80073ce 800736c: 687b ldr r3, [r7, #4] 800736e: 681b ldr r3, [r3, #0] 8007370: 4a5b ldr r2, [pc, #364] @ (80074e0 ) 8007372: 4293 cmp r3, r2 8007374: d028 beq.n 80073c8 8007376: 687b ldr r3, [r7, #4] 8007378: 681b ldr r3, [r3, #0] 800737a: 4a53 ldr r2, [pc, #332] @ (80074c8 ) 800737c: 4293 cmp r3, r2 800737e: d020 beq.n 80073c2 8007380: 687b ldr r3, [r7, #4] 8007382: 681b ldr r3, [r3, #0] 8007384: 4a57 ldr r2, [pc, #348] @ (80074e4 ) 8007386: 4293 cmp r3, r2 8007388: d019 beq.n 80073be 800738a: 687b ldr r3, [r7, #4] 800738c: 681b ldr r3, [r3, #0] 800738e: 4a56 ldr r2, [pc, #344] @ (80074e8 ) 8007390: 4293 cmp r3, r2 8007392: d012 beq.n 80073ba 8007394: 687b ldr r3, [r7, #4] 8007396: 681b ldr r3, [r3, #0] 8007398: 4a54 ldr r2, [pc, #336] @ (80074ec ) 800739a: 4293 cmp r3, r2 800739c: d00a beq.n 80073b4 800739e: 687b ldr r3, [r7, #4] 80073a0: 681b ldr r3, [r3, #0] 80073a2: 4a53 ldr r2, [pc, #332] @ (80074f0 ) 80073a4: 4293 cmp r3, r2 80073a6: d102 bne.n 80073ae 80073a8: f44f 5380 mov.w r3, #4096 @ 0x1000 80073ac: e01b b.n 80073e6 80073ae: f44f 3380 mov.w r3, #65536 @ 0x10000 80073b2: e018 b.n 80073e6 80073b4: f44f 7380 mov.w r3, #256 @ 0x100 80073b8: e015 b.n 80073e6 80073ba: 2310 movs r3, #16 80073bc: e013 b.n 80073e6 80073be: 2301 movs r3, #1 80073c0: e011 b.n 80073e6 80073c2: f04f 7380 mov.w r3, #16777216 @ 0x1000000 80073c6: e00e b.n 80073e6 80073c8: f44f 1380 mov.w r3, #1048576 @ 0x100000 80073cc: e00b b.n 80073e6 80073ce: f44f 3380 mov.w r3, #65536 @ 0x10000 80073d2: e008 b.n 80073e6 80073d4: f44f 5380 mov.w r3, #4096 @ 0x1000 80073d8: e005 b.n 80073e6 80073da: f44f 7380 mov.w r3, #256 @ 0x100 80073de: e002 b.n 80073e6 80073e0: 2310 movs r3, #16 80073e2: e000 b.n 80073e6 80073e4: 2301 movs r3, #1 80073e6: 4a43 ldr r2, [pc, #268] @ (80074f4 ) 80073e8: 6053 str r3, [r2, #4] 80073ea: e057 b.n 800749c 80073ec: 687b ldr r3, [r7, #4] 80073ee: 681b ldr r3, [r3, #0] 80073f0: 4a36 ldr r2, [pc, #216] @ (80074cc ) 80073f2: 4293 cmp r3, r2 80073f4: d04f beq.n 8007496 80073f6: 687b ldr r3, [r7, #4] 80073f8: 681b ldr r3, [r3, #0] 80073fa: 4a35 ldr r2, [pc, #212] @ (80074d0 ) 80073fc: 4293 cmp r3, r2 80073fe: d048 beq.n 8007492 8007400: 687b ldr r3, [r7, #4] 8007402: 681b ldr r3, [r3, #0] 8007404: 4a33 ldr r2, [pc, #204] @ (80074d4 ) 8007406: 4293 cmp r3, r2 8007408: d040 beq.n 800748c 800740a: 687b ldr r3, [r7, #4] 800740c: 681b ldr r3, [r3, #0] 800740e: 4a32 ldr r2, [pc, #200] @ (80074d8 ) 8007410: 4293 cmp r3, r2 8007412: d038 beq.n 8007486 8007414: 687b ldr r3, [r7, #4] 8007416: 681b ldr r3, [r3, #0] 8007418: 4a30 ldr r2, [pc, #192] @ (80074dc ) 800741a: 4293 cmp r3, r2 800741c: d030 beq.n 8007480 800741e: 687b ldr r3, [r7, #4] 8007420: 681b ldr r3, [r3, #0] 8007422: 4a2f ldr r2, [pc, #188] @ (80074e0 ) 8007424: 4293 cmp r3, r2 8007426: d028 beq.n 800747a 8007428: 687b ldr r3, [r7, #4] 800742a: 681b ldr r3, [r3, #0] 800742c: 4a26 ldr r2, [pc, #152] @ (80074c8 ) 800742e: 4293 cmp r3, r2 8007430: d020 beq.n 8007474 8007432: 687b ldr r3, [r7, #4] 8007434: 681b ldr r3, [r3, #0] 8007436: 4a2b ldr r2, [pc, #172] @ (80074e4 ) 8007438: 4293 cmp r3, r2 800743a: d019 beq.n 8007470 800743c: 687b ldr r3, [r7, #4] 800743e: 681b ldr r3, [r3, #0] 8007440: 4a29 ldr r2, [pc, #164] @ (80074e8 ) 8007442: 4293 cmp r3, r2 8007444: d012 beq.n 800746c 8007446: 687b ldr r3, [r7, #4] 8007448: 681b ldr r3, [r3, #0] 800744a: 4a28 ldr r2, [pc, #160] @ (80074ec ) 800744c: 4293 cmp r3, r2 800744e: d00a beq.n 8007466 8007450: 687b ldr r3, [r7, #4] 8007452: 681b ldr r3, [r3, #0] 8007454: 4a26 ldr r2, [pc, #152] @ (80074f0 ) 8007456: 4293 cmp r3, r2 8007458: d102 bne.n 8007460 800745a: f44f 5380 mov.w r3, #4096 @ 0x1000 800745e: e01b b.n 8007498 8007460: f44f 3380 mov.w r3, #65536 @ 0x10000 8007464: e018 b.n 8007498 8007466: f44f 7380 mov.w r3, #256 @ 0x100 800746a: e015 b.n 8007498 800746c: 2310 movs r3, #16 800746e: e013 b.n 8007498 8007470: 2301 movs r3, #1 8007472: e011 b.n 8007498 8007474: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8007478: e00e b.n 8007498 800747a: f44f 1380 mov.w r3, #1048576 @ 0x100000 800747e: e00b b.n 8007498 8007480: f44f 3380 mov.w r3, #65536 @ 0x10000 8007484: e008 b.n 8007498 8007486: f44f 5380 mov.w r3, #4096 @ 0x1000 800748a: e005 b.n 8007498 800748c: f44f 7380 mov.w r3, #256 @ 0x100 8007490: e002 b.n 8007498 8007492: 2310 movs r3, #16 8007494: e000 b.n 8007498 8007496: 2301 movs r3, #1 8007498: 4a17 ldr r2, [pc, #92] @ (80074f8 ) 800749a: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800749c: 687b ldr r3, [r7, #4] 800749e: 2201 movs r2, #1 80074a0: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80074a4: 687b ldr r3, [r7, #4] 80074a6: 2200 movs r2, #0 80074a8: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 80074ac: 687b ldr r3, [r7, #4] 80074ae: 6b5b ldr r3, [r3, #52] @ 0x34 80074b0: 2b00 cmp r3, #0 80074b2: d003 beq.n 80074bc { hdma->XferAbortCallback(hdma); 80074b4: 687b ldr r3, [r7, #4] 80074b6: 6b5b ldr r3, [r3, #52] @ 0x34 80074b8: 6878 ldr r0, [r7, #4] 80074ba: 4798 blx r3 } } return status; 80074bc: 7bfb ldrb r3, [r7, #15] } 80074be: 4618 mov r0, r3 80074c0: 3710 adds r7, #16 80074c2: 46bd mov sp, r7 80074c4: bd80 pop {r7, pc} 80074c6: bf00 nop 80074c8: 40020080 .word 0x40020080 80074cc: 40020008 .word 0x40020008 80074d0: 4002001c .word 0x4002001c 80074d4: 40020030 .word 0x40020030 80074d8: 40020044 .word 0x40020044 80074dc: 40020058 .word 0x40020058 80074e0: 4002006c .word 0x4002006c 80074e4: 40020408 .word 0x40020408 80074e8: 4002041c .word 0x4002041c 80074ec: 40020430 .word 0x40020430 80074f0: 40020444 .word 0x40020444 80074f4: 40020400 .word 0x40020400 80074f8: 40020000 .word 0x40020000 080074fc : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80074fc: b480 push {r7} 80074fe: b08b sub sp, #44 @ 0x2c 8007500: af00 add r7, sp, #0 8007502: 6078 str r0, [r7, #4] 8007504: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8007506: 2300 movs r3, #0 8007508: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 800750a: 2300 movs r3, #0 800750c: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800750e: e169 b.n 80077e4 { /* Get the IO position */ ioposition = (0x01uL << position); 8007510: 2201 movs r2, #1 8007512: 6a7b ldr r3, [r7, #36] @ 0x24 8007514: fa02 f303 lsl.w r3, r2, r3 8007518: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 800751a: 683b ldr r3, [r7, #0] 800751c: 681b ldr r3, [r3, #0] 800751e: 69fa ldr r2, [r7, #28] 8007520: 4013 ands r3, r2 8007522: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8007524: 69ba ldr r2, [r7, #24] 8007526: 69fb ldr r3, [r7, #28] 8007528: 429a cmp r2, r3 800752a: f040 8158 bne.w 80077de { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 800752e: 683b ldr r3, [r7, #0] 8007530: 685b ldr r3, [r3, #4] 8007532: 4a9a ldr r2, [pc, #616] @ (800779c ) 8007534: 4293 cmp r3, r2 8007536: d05e beq.n 80075f6 8007538: 4a98 ldr r2, [pc, #608] @ (800779c ) 800753a: 4293 cmp r3, r2 800753c: d875 bhi.n 800762a 800753e: 4a98 ldr r2, [pc, #608] @ (80077a0 ) 8007540: 4293 cmp r3, r2 8007542: d058 beq.n 80075f6 8007544: 4a96 ldr r2, [pc, #600] @ (80077a0 ) 8007546: 4293 cmp r3, r2 8007548: d86f bhi.n 800762a 800754a: 4a96 ldr r2, [pc, #600] @ (80077a4 ) 800754c: 4293 cmp r3, r2 800754e: d052 beq.n 80075f6 8007550: 4a94 ldr r2, [pc, #592] @ (80077a4 ) 8007552: 4293 cmp r3, r2 8007554: d869 bhi.n 800762a 8007556: 4a94 ldr r2, [pc, #592] @ (80077a8 ) 8007558: 4293 cmp r3, r2 800755a: d04c beq.n 80075f6 800755c: 4a92 ldr r2, [pc, #584] @ (80077a8 ) 800755e: 4293 cmp r3, r2 8007560: d863 bhi.n 800762a 8007562: 4a92 ldr r2, [pc, #584] @ (80077ac ) 8007564: 4293 cmp r3, r2 8007566: d046 beq.n 80075f6 8007568: 4a90 ldr r2, [pc, #576] @ (80077ac ) 800756a: 4293 cmp r3, r2 800756c: d85d bhi.n 800762a 800756e: 2b12 cmp r3, #18 8007570: d82a bhi.n 80075c8 8007572: 2b12 cmp r3, #18 8007574: d859 bhi.n 800762a 8007576: a201 add r2, pc, #4 @ (adr r2, 800757c ) 8007578: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800757c: 080075f7 .word 0x080075f7 8007580: 080075d1 .word 0x080075d1 8007584: 080075e3 .word 0x080075e3 8007588: 08007625 .word 0x08007625 800758c: 0800762b .word 0x0800762b 8007590: 0800762b .word 0x0800762b 8007594: 0800762b .word 0x0800762b 8007598: 0800762b .word 0x0800762b 800759c: 0800762b .word 0x0800762b 80075a0: 0800762b .word 0x0800762b 80075a4: 0800762b .word 0x0800762b 80075a8: 0800762b .word 0x0800762b 80075ac: 0800762b .word 0x0800762b 80075b0: 0800762b .word 0x0800762b 80075b4: 0800762b .word 0x0800762b 80075b8: 0800762b .word 0x0800762b 80075bc: 0800762b .word 0x0800762b 80075c0: 080075d9 .word 0x080075d9 80075c4: 080075ed .word 0x080075ed 80075c8: 4a79 ldr r2, [pc, #484] @ (80077b0 ) 80075ca: 4293 cmp r3, r2 80075cc: d013 beq.n 80075f6 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 80075ce: e02c b.n 800762a config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 80075d0: 683b ldr r3, [r7, #0] 80075d2: 68db ldr r3, [r3, #12] 80075d4: 623b str r3, [r7, #32] break; 80075d6: e029 b.n 800762c config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 80075d8: 683b ldr r3, [r7, #0] 80075da: 68db ldr r3, [r3, #12] 80075dc: 3304 adds r3, #4 80075de: 623b str r3, [r7, #32] break; 80075e0: e024 b.n 800762c config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 80075e2: 683b ldr r3, [r7, #0] 80075e4: 68db ldr r3, [r3, #12] 80075e6: 3308 adds r3, #8 80075e8: 623b str r3, [r7, #32] break; 80075ea: e01f b.n 800762c config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 80075ec: 683b ldr r3, [r7, #0] 80075ee: 68db ldr r3, [r3, #12] 80075f0: 330c adds r3, #12 80075f2: 623b str r3, [r7, #32] break; 80075f4: e01a b.n 800762c if (GPIO_Init->Pull == GPIO_NOPULL) 80075f6: 683b ldr r3, [r7, #0] 80075f8: 689b ldr r3, [r3, #8] 80075fa: 2b00 cmp r3, #0 80075fc: d102 bne.n 8007604 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 80075fe: 2304 movs r3, #4 8007600: 623b str r3, [r7, #32] break; 8007602: e013 b.n 800762c else if (GPIO_Init->Pull == GPIO_PULLUP) 8007604: 683b ldr r3, [r7, #0] 8007606: 689b ldr r3, [r3, #8] 8007608: 2b01 cmp r3, #1 800760a: d105 bne.n 8007618 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 800760c: 2308 movs r3, #8 800760e: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8007610: 687b ldr r3, [r7, #4] 8007612: 69fa ldr r2, [r7, #28] 8007614: 611a str r2, [r3, #16] break; 8007616: e009 b.n 800762c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8007618: 2308 movs r3, #8 800761a: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 800761c: 687b ldr r3, [r7, #4] 800761e: 69fa ldr r2, [r7, #28] 8007620: 615a str r2, [r3, #20] break; 8007622: e003 b.n 800762c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8007624: 2300 movs r3, #0 8007626: 623b str r3, [r7, #32] break; 8007628: e000 b.n 800762c break; 800762a: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 800762c: 69bb ldr r3, [r7, #24] 800762e: 2bff cmp r3, #255 @ 0xff 8007630: d801 bhi.n 8007636 8007632: 687b ldr r3, [r7, #4] 8007634: e001 b.n 800763a 8007636: 687b ldr r3, [r7, #4] 8007638: 3304 adds r3, #4 800763a: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 800763c: 69bb ldr r3, [r7, #24] 800763e: 2bff cmp r3, #255 @ 0xff 8007640: d802 bhi.n 8007648 8007642: 6a7b ldr r3, [r7, #36] @ 0x24 8007644: 009b lsls r3, r3, #2 8007646: e002 b.n 800764e 8007648: 6a7b ldr r3, [r7, #36] @ 0x24 800764a: 3b08 subs r3, #8 800764c: 009b lsls r3, r3, #2 800764e: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8007650: 697b ldr r3, [r7, #20] 8007652: 681a ldr r2, [r3, #0] 8007654: 210f movs r1, #15 8007656: 693b ldr r3, [r7, #16] 8007658: fa01 f303 lsl.w r3, r1, r3 800765c: 43db mvns r3, r3 800765e: 401a ands r2, r3 8007660: 6a39 ldr r1, [r7, #32] 8007662: 693b ldr r3, [r7, #16] 8007664: fa01 f303 lsl.w r3, r1, r3 8007668: 431a orrs r2, r3 800766a: 697b ldr r3, [r7, #20] 800766c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 800766e: 683b ldr r3, [r7, #0] 8007670: 685b ldr r3, [r3, #4] 8007672: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8007676: 2b00 cmp r3, #0 8007678: f000 80b1 beq.w 80077de { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 800767c: 4b4d ldr r3, [pc, #308] @ (80077b4 ) 800767e: 699b ldr r3, [r3, #24] 8007680: 4a4c ldr r2, [pc, #304] @ (80077b4 ) 8007682: f043 0301 orr.w r3, r3, #1 8007686: 6193 str r3, [r2, #24] 8007688: 4b4a ldr r3, [pc, #296] @ (80077b4 ) 800768a: 699b ldr r3, [r3, #24] 800768c: f003 0301 and.w r3, r3, #1 8007690: 60bb str r3, [r7, #8] 8007692: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8007694: 4a48 ldr r2, [pc, #288] @ (80077b8 ) 8007696: 6a7b ldr r3, [r7, #36] @ 0x24 8007698: 089b lsrs r3, r3, #2 800769a: 3302 adds r3, #2 800769c: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80076a0: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 80076a2: 6a7b ldr r3, [r7, #36] @ 0x24 80076a4: f003 0303 and.w r3, r3, #3 80076a8: 009b lsls r3, r3, #2 80076aa: 220f movs r2, #15 80076ac: fa02 f303 lsl.w r3, r2, r3 80076b0: 43db mvns r3, r3 80076b2: 68fa ldr r2, [r7, #12] 80076b4: 4013 ands r3, r2 80076b6: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 80076b8: 687b ldr r3, [r7, #4] 80076ba: 4a40 ldr r2, [pc, #256] @ (80077bc ) 80076bc: 4293 cmp r3, r2 80076be: d013 beq.n 80076e8 80076c0: 687b ldr r3, [r7, #4] 80076c2: 4a3f ldr r2, [pc, #252] @ (80077c0 ) 80076c4: 4293 cmp r3, r2 80076c6: d00d beq.n 80076e4 80076c8: 687b ldr r3, [r7, #4] 80076ca: 4a3e ldr r2, [pc, #248] @ (80077c4 ) 80076cc: 4293 cmp r3, r2 80076ce: d007 beq.n 80076e0 80076d0: 687b ldr r3, [r7, #4] 80076d2: 4a3d ldr r2, [pc, #244] @ (80077c8 ) 80076d4: 4293 cmp r3, r2 80076d6: d101 bne.n 80076dc 80076d8: 2303 movs r3, #3 80076da: e006 b.n 80076ea 80076dc: 2304 movs r3, #4 80076de: e004 b.n 80076ea 80076e0: 2302 movs r3, #2 80076e2: e002 b.n 80076ea 80076e4: 2301 movs r3, #1 80076e6: e000 b.n 80076ea 80076e8: 2300 movs r3, #0 80076ea: 6a7a ldr r2, [r7, #36] @ 0x24 80076ec: f002 0203 and.w r2, r2, #3 80076f0: 0092 lsls r2, r2, #2 80076f2: 4093 lsls r3, r2 80076f4: 68fa ldr r2, [r7, #12] 80076f6: 4313 orrs r3, r2 80076f8: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 80076fa: 492f ldr r1, [pc, #188] @ (80077b8 ) 80076fc: 6a7b ldr r3, [r7, #36] @ 0x24 80076fe: 089b lsrs r3, r3, #2 8007700: 3302 adds r3, #2 8007702: 68fa ldr r2, [r7, #12] 8007704: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8007708: 683b ldr r3, [r7, #0] 800770a: 685b ldr r3, [r3, #4] 800770c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8007710: 2b00 cmp r3, #0 8007712: d006 beq.n 8007722 { SET_BIT(EXTI->IMR, iocurrent); 8007714: 4b2d ldr r3, [pc, #180] @ (80077cc ) 8007716: 681a ldr r2, [r3, #0] 8007718: 492c ldr r1, [pc, #176] @ (80077cc ) 800771a: 69bb ldr r3, [r7, #24] 800771c: 4313 orrs r3, r2 800771e: 600b str r3, [r1, #0] 8007720: e006 b.n 8007730 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8007722: 4b2a ldr r3, [pc, #168] @ (80077cc ) 8007724: 681a ldr r2, [r3, #0] 8007726: 69bb ldr r3, [r7, #24] 8007728: 43db mvns r3, r3 800772a: 4928 ldr r1, [pc, #160] @ (80077cc ) 800772c: 4013 ands r3, r2 800772e: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8007730: 683b ldr r3, [r7, #0] 8007732: 685b ldr r3, [r3, #4] 8007734: f403 3300 and.w r3, r3, #131072 @ 0x20000 8007738: 2b00 cmp r3, #0 800773a: d006 beq.n 800774a { SET_BIT(EXTI->EMR, iocurrent); 800773c: 4b23 ldr r3, [pc, #140] @ (80077cc ) 800773e: 685a ldr r2, [r3, #4] 8007740: 4922 ldr r1, [pc, #136] @ (80077cc ) 8007742: 69bb ldr r3, [r7, #24] 8007744: 4313 orrs r3, r2 8007746: 604b str r3, [r1, #4] 8007748: e006 b.n 8007758 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 800774a: 4b20 ldr r3, [pc, #128] @ (80077cc ) 800774c: 685a ldr r2, [r3, #4] 800774e: 69bb ldr r3, [r7, #24] 8007750: 43db mvns r3, r3 8007752: 491e ldr r1, [pc, #120] @ (80077cc ) 8007754: 4013 ands r3, r2 8007756: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8007758: 683b ldr r3, [r7, #0] 800775a: 685b ldr r3, [r3, #4] 800775c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8007760: 2b00 cmp r3, #0 8007762: d006 beq.n 8007772 { SET_BIT(EXTI->RTSR, iocurrent); 8007764: 4b19 ldr r3, [pc, #100] @ (80077cc ) 8007766: 689a ldr r2, [r3, #8] 8007768: 4918 ldr r1, [pc, #96] @ (80077cc ) 800776a: 69bb ldr r3, [r7, #24] 800776c: 4313 orrs r3, r2 800776e: 608b str r3, [r1, #8] 8007770: e006 b.n 8007780 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8007772: 4b16 ldr r3, [pc, #88] @ (80077cc ) 8007774: 689a ldr r2, [r3, #8] 8007776: 69bb ldr r3, [r7, #24] 8007778: 43db mvns r3, r3 800777a: 4914 ldr r1, [pc, #80] @ (80077cc ) 800777c: 4013 ands r3, r2 800777e: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8007780: 683b ldr r3, [r7, #0] 8007782: 685b ldr r3, [r3, #4] 8007784: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8007788: 2b00 cmp r3, #0 800778a: d021 beq.n 80077d0 { SET_BIT(EXTI->FTSR, iocurrent); 800778c: 4b0f ldr r3, [pc, #60] @ (80077cc ) 800778e: 68da ldr r2, [r3, #12] 8007790: 490e ldr r1, [pc, #56] @ (80077cc ) 8007792: 69bb ldr r3, [r7, #24] 8007794: 4313 orrs r3, r2 8007796: 60cb str r3, [r1, #12] 8007798: e021 b.n 80077de 800779a: bf00 nop 800779c: 10320000 .word 0x10320000 80077a0: 10310000 .word 0x10310000 80077a4: 10220000 .word 0x10220000 80077a8: 10210000 .word 0x10210000 80077ac: 10120000 .word 0x10120000 80077b0: 10110000 .word 0x10110000 80077b4: 40021000 .word 0x40021000 80077b8: 40010000 .word 0x40010000 80077bc: 40010800 .word 0x40010800 80077c0: 40010c00 .word 0x40010c00 80077c4: 40011000 .word 0x40011000 80077c8: 40011400 .word 0x40011400 80077cc: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 80077d0: 4b0b ldr r3, [pc, #44] @ (8007800 ) 80077d2: 68da ldr r2, [r3, #12] 80077d4: 69bb ldr r3, [r7, #24] 80077d6: 43db mvns r3, r3 80077d8: 4909 ldr r1, [pc, #36] @ (8007800 ) 80077da: 4013 ands r3, r2 80077dc: 60cb str r3, [r1, #12] } } } position++; 80077de: 6a7b ldr r3, [r7, #36] @ 0x24 80077e0: 3301 adds r3, #1 80077e2: 627b str r3, [r7, #36] @ 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 80077e4: 683b ldr r3, [r7, #0] 80077e6: 681a ldr r2, [r3, #0] 80077e8: 6a7b ldr r3, [r7, #36] @ 0x24 80077ea: fa22 f303 lsr.w r3, r2, r3 80077ee: 2b00 cmp r3, #0 80077f0: f47f ae8e bne.w 8007510 } } 80077f4: bf00 nop 80077f6: bf00 nop 80077f8: 372c adds r7, #44 @ 0x2c 80077fa: 46bd mov sp, r7 80077fc: bc80 pop {r7} 80077fe: 4770 bx lr 8007800: 40010400 .word 0x40010400 08007804 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8007804: b480 push {r7} 8007806: b085 sub sp, #20 8007808: af00 add r7, sp, #0 800780a: 6078 str r0, [r7, #4] 800780c: 460b mov r3, r1 800780e: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8007810: 687b ldr r3, [r7, #4] 8007812: 689a ldr r2, [r3, #8] 8007814: 887b ldrh r3, [r7, #2] 8007816: 4013 ands r3, r2 8007818: 2b00 cmp r3, #0 800781a: d002 beq.n 8007822 { bitstatus = GPIO_PIN_SET; 800781c: 2301 movs r3, #1 800781e: 73fb strb r3, [r7, #15] 8007820: e001 b.n 8007826 } else { bitstatus = GPIO_PIN_RESET; 8007822: 2300 movs r3, #0 8007824: 73fb strb r3, [r7, #15] } return bitstatus; 8007826: 7bfb ldrb r3, [r7, #15] } 8007828: 4618 mov r0, r3 800782a: 3714 adds r7, #20 800782c: 46bd mov sp, r7 800782e: bc80 pop {r7} 8007830: 4770 bx lr 08007832 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8007832: b480 push {r7} 8007834: b083 sub sp, #12 8007836: af00 add r7, sp, #0 8007838: 6078 str r0, [r7, #4] 800783a: 460b mov r3, r1 800783c: 807b strh r3, [r7, #2] 800783e: 4613 mov r3, r2 8007840: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8007842: 787b ldrb r3, [r7, #1] 8007844: 2b00 cmp r3, #0 8007846: d003 beq.n 8007850 { GPIOx->BSRR = GPIO_Pin; 8007848: 887a ldrh r2, [r7, #2] 800784a: 687b ldr r3, [r7, #4] 800784c: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 800784e: e003 b.n 8007858 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8007850: 887b ldrh r3, [r7, #2] 8007852: 041a lsls r2, r3, #16 8007854: 687b ldr r3, [r7, #4] 8007856: 611a str r2, [r3, #16] } 8007858: bf00 nop 800785a: 370c adds r7, #12 800785c: 46bd mov sp, r7 800785e: bc80 pop {r7} 8007860: 4770 bx lr ... 08007864 : * @note If the HSE divided by 128 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 8007864: b480 push {r7} 8007866: af00 add r7, sp, #0 /* Enable access to RTC and backup registers */ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 8007868: 4b03 ldr r3, [pc, #12] @ (8007878 ) 800786a: 2201 movs r2, #1 800786c: 601a str r2, [r3, #0] } 800786e: bf00 nop 8007870: 46bd mov sp, r7 8007872: bc80 pop {r7} 8007874: 4770 bx lr 8007876: bf00 nop 8007878: 420e0020 .word 0x420e0020 0800787c : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800787c: b580 push {r7, lr} 800787e: b086 sub sp, #24 8007880: af00 add r7, sp, #0 8007882: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8007884: 687b ldr r3, [r7, #4] 8007886: 2b00 cmp r3, #0 8007888: d101 bne.n 800788e { return HAL_ERROR; 800788a: 2301 movs r3, #1 800788c: e304 b.n 8007e98 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800788e: 687b ldr r3, [r7, #4] 8007890: 681b ldr r3, [r3, #0] 8007892: f003 0301 and.w r3, r3, #1 8007896: 2b00 cmp r3, #0 8007898: f000 8087 beq.w 80079aa { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 800789c: 4b92 ldr r3, [pc, #584] @ (8007ae8 ) 800789e: 685b ldr r3, [r3, #4] 80078a0: f003 030c and.w r3, r3, #12 80078a4: 2b04 cmp r3, #4 80078a6: d00c beq.n 80078c2 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 80078a8: 4b8f ldr r3, [pc, #572] @ (8007ae8 ) 80078aa: 685b ldr r3, [r3, #4] 80078ac: f003 030c and.w r3, r3, #12 80078b0: 2b08 cmp r3, #8 80078b2: d112 bne.n 80078da 80078b4: 4b8c ldr r3, [pc, #560] @ (8007ae8 ) 80078b6: 685b ldr r3, [r3, #4] 80078b8: f403 3380 and.w r3, r3, #65536 @ 0x10000 80078bc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80078c0: d10b bne.n 80078da { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80078c2: 4b89 ldr r3, [pc, #548] @ (8007ae8 ) 80078c4: 681b ldr r3, [r3, #0] 80078c6: f403 3300 and.w r3, r3, #131072 @ 0x20000 80078ca: 2b00 cmp r3, #0 80078cc: d06c beq.n 80079a8 80078ce: 687b ldr r3, [r7, #4] 80078d0: 689b ldr r3, [r3, #8] 80078d2: 2b00 cmp r3, #0 80078d4: d168 bne.n 80079a8 { return HAL_ERROR; 80078d6: 2301 movs r3, #1 80078d8: e2de b.n 8007e98 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80078da: 687b ldr r3, [r7, #4] 80078dc: 689b ldr r3, [r3, #8] 80078de: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80078e2: d106 bne.n 80078f2 80078e4: 4b80 ldr r3, [pc, #512] @ (8007ae8 ) 80078e6: 681b ldr r3, [r3, #0] 80078e8: 4a7f ldr r2, [pc, #508] @ (8007ae8 ) 80078ea: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80078ee: 6013 str r3, [r2, #0] 80078f0: e02e b.n 8007950 80078f2: 687b ldr r3, [r7, #4] 80078f4: 689b ldr r3, [r3, #8] 80078f6: 2b00 cmp r3, #0 80078f8: d10c bne.n 8007914 80078fa: 4b7b ldr r3, [pc, #492] @ (8007ae8 ) 80078fc: 681b ldr r3, [r3, #0] 80078fe: 4a7a ldr r2, [pc, #488] @ (8007ae8 ) 8007900: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8007904: 6013 str r3, [r2, #0] 8007906: 4b78 ldr r3, [pc, #480] @ (8007ae8 ) 8007908: 681b ldr r3, [r3, #0] 800790a: 4a77 ldr r2, [pc, #476] @ (8007ae8 ) 800790c: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8007910: 6013 str r3, [r2, #0] 8007912: e01d b.n 8007950 8007914: 687b ldr r3, [r7, #4] 8007916: 689b ldr r3, [r3, #8] 8007918: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800791c: d10c bne.n 8007938 800791e: 4b72 ldr r3, [pc, #456] @ (8007ae8 ) 8007920: 681b ldr r3, [r3, #0] 8007922: 4a71 ldr r2, [pc, #452] @ (8007ae8 ) 8007924: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8007928: 6013 str r3, [r2, #0] 800792a: 4b6f ldr r3, [pc, #444] @ (8007ae8 ) 800792c: 681b ldr r3, [r3, #0] 800792e: 4a6e ldr r2, [pc, #440] @ (8007ae8 ) 8007930: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8007934: 6013 str r3, [r2, #0] 8007936: e00b b.n 8007950 8007938: 4b6b ldr r3, [pc, #428] @ (8007ae8 ) 800793a: 681b ldr r3, [r3, #0] 800793c: 4a6a ldr r2, [pc, #424] @ (8007ae8 ) 800793e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8007942: 6013 str r3, [r2, #0] 8007944: 4b68 ldr r3, [pc, #416] @ (8007ae8 ) 8007946: 681b ldr r3, [r3, #0] 8007948: 4a67 ldr r2, [pc, #412] @ (8007ae8 ) 800794a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800794e: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8007950: 687b ldr r3, [r7, #4] 8007952: 689b ldr r3, [r3, #8] 8007954: 2b00 cmp r3, #0 8007956: d013 beq.n 8007980 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8007958: f7fd ffa2 bl 80058a0 800795c: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800795e: e008 b.n 8007972 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8007960: f7fd ff9e bl 80058a0 8007964: 4602 mov r2, r0 8007966: 693b ldr r3, [r7, #16] 8007968: 1ad3 subs r3, r2, r3 800796a: 2b64 cmp r3, #100 @ 0x64 800796c: d901 bls.n 8007972 { return HAL_TIMEOUT; 800796e: 2303 movs r3, #3 8007970: e292 b.n 8007e98 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8007972: 4b5d ldr r3, [pc, #372] @ (8007ae8 ) 8007974: 681b ldr r3, [r3, #0] 8007976: f403 3300 and.w r3, r3, #131072 @ 0x20000 800797a: 2b00 cmp r3, #0 800797c: d0f0 beq.n 8007960 800797e: e014 b.n 80079aa } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8007980: f7fd ff8e bl 80058a0 8007984: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8007986: e008 b.n 800799a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8007988: f7fd ff8a bl 80058a0 800798c: 4602 mov r2, r0 800798e: 693b ldr r3, [r7, #16] 8007990: 1ad3 subs r3, r2, r3 8007992: 2b64 cmp r3, #100 @ 0x64 8007994: d901 bls.n 800799a { return HAL_TIMEOUT; 8007996: 2303 movs r3, #3 8007998: e27e b.n 8007e98 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800799a: 4b53 ldr r3, [pc, #332] @ (8007ae8 ) 800799c: 681b ldr r3, [r3, #0] 800799e: f403 3300 and.w r3, r3, #131072 @ 0x20000 80079a2: 2b00 cmp r3, #0 80079a4: d1f0 bne.n 8007988 80079a6: e000 b.n 80079aa if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80079a8: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 80079aa: 687b ldr r3, [r7, #4] 80079ac: 681b ldr r3, [r3, #0] 80079ae: f003 0302 and.w r3, r3, #2 80079b2: 2b00 cmp r3, #0 80079b4: d063 beq.n 8007a7e /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 80079b6: 4b4c ldr r3, [pc, #304] @ (8007ae8 ) 80079b8: 685b ldr r3, [r3, #4] 80079ba: f003 030c and.w r3, r3, #12 80079be: 2b00 cmp r3, #0 80079c0: d00b beq.n 80079da || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 80079c2: 4b49 ldr r3, [pc, #292] @ (8007ae8 ) 80079c4: 685b ldr r3, [r3, #4] 80079c6: f003 030c and.w r3, r3, #12 80079ca: 2b08 cmp r3, #8 80079cc: d11c bne.n 8007a08 80079ce: 4b46 ldr r3, [pc, #280] @ (8007ae8 ) 80079d0: 685b ldr r3, [r3, #4] 80079d2: f403 3380 and.w r3, r3, #65536 @ 0x10000 80079d6: 2b00 cmp r3, #0 80079d8: d116 bne.n 8007a08 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80079da: 4b43 ldr r3, [pc, #268] @ (8007ae8 ) 80079dc: 681b ldr r3, [r3, #0] 80079de: f003 0302 and.w r3, r3, #2 80079e2: 2b00 cmp r3, #0 80079e4: d005 beq.n 80079f2 80079e6: 687b ldr r3, [r7, #4] 80079e8: 695b ldr r3, [r3, #20] 80079ea: 2b01 cmp r3, #1 80079ec: d001 beq.n 80079f2 { return HAL_ERROR; 80079ee: 2301 movs r3, #1 80079f0: e252 b.n 8007e98 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80079f2: 4b3d ldr r3, [pc, #244] @ (8007ae8 ) 80079f4: 681b ldr r3, [r3, #0] 80079f6: f023 02f8 bic.w r2, r3, #248 @ 0xf8 80079fa: 687b ldr r3, [r7, #4] 80079fc: 699b ldr r3, [r3, #24] 80079fe: 00db lsls r3, r3, #3 8007a00: 4939 ldr r1, [pc, #228] @ (8007ae8 ) 8007a02: 4313 orrs r3, r2 8007a04: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8007a06: e03a b.n 8007a7e } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8007a08: 687b ldr r3, [r7, #4] 8007a0a: 695b ldr r3, [r3, #20] 8007a0c: 2b00 cmp r3, #0 8007a0e: d020 beq.n 8007a52 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8007a10: 4b36 ldr r3, [pc, #216] @ (8007aec ) 8007a12: 2201 movs r2, #1 8007a14: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8007a16: f7fd ff43 bl 80058a0 8007a1a: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8007a1c: e008 b.n 8007a30 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8007a1e: f7fd ff3f bl 80058a0 8007a22: 4602 mov r2, r0 8007a24: 693b ldr r3, [r7, #16] 8007a26: 1ad3 subs r3, r2, r3 8007a28: 2b02 cmp r3, #2 8007a2a: d901 bls.n 8007a30 { return HAL_TIMEOUT; 8007a2c: 2303 movs r3, #3 8007a2e: e233 b.n 8007e98 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8007a30: 4b2d ldr r3, [pc, #180] @ (8007ae8 ) 8007a32: 681b ldr r3, [r3, #0] 8007a34: f003 0302 and.w r3, r3, #2 8007a38: 2b00 cmp r3, #0 8007a3a: d0f0 beq.n 8007a1e } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8007a3c: 4b2a ldr r3, [pc, #168] @ (8007ae8 ) 8007a3e: 681b ldr r3, [r3, #0] 8007a40: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8007a44: 687b ldr r3, [r7, #4] 8007a46: 699b ldr r3, [r3, #24] 8007a48: 00db lsls r3, r3, #3 8007a4a: 4927 ldr r1, [pc, #156] @ (8007ae8 ) 8007a4c: 4313 orrs r3, r2 8007a4e: 600b str r3, [r1, #0] 8007a50: e015 b.n 8007a7e } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8007a52: 4b26 ldr r3, [pc, #152] @ (8007aec ) 8007a54: 2200 movs r2, #0 8007a56: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8007a58: f7fd ff22 bl 80058a0 8007a5c: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8007a5e: e008 b.n 8007a72 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8007a60: f7fd ff1e bl 80058a0 8007a64: 4602 mov r2, r0 8007a66: 693b ldr r3, [r7, #16] 8007a68: 1ad3 subs r3, r2, r3 8007a6a: 2b02 cmp r3, #2 8007a6c: d901 bls.n 8007a72 { return HAL_TIMEOUT; 8007a6e: 2303 movs r3, #3 8007a70: e212 b.n 8007e98 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8007a72: 4b1d ldr r3, [pc, #116] @ (8007ae8 ) 8007a74: 681b ldr r3, [r3, #0] 8007a76: f003 0302 and.w r3, r3, #2 8007a7a: 2b00 cmp r3, #0 8007a7c: d1f0 bne.n 8007a60 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8007a7e: 687b ldr r3, [r7, #4] 8007a80: 681b ldr r3, [r3, #0] 8007a82: f003 0308 and.w r3, r3, #8 8007a86: 2b00 cmp r3, #0 8007a88: d03a beq.n 8007b00 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8007a8a: 687b ldr r3, [r7, #4] 8007a8c: 69db ldr r3, [r3, #28] 8007a8e: 2b00 cmp r3, #0 8007a90: d019 beq.n 8007ac6 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8007a92: 4b17 ldr r3, [pc, #92] @ (8007af0 ) 8007a94: 2201 movs r2, #1 8007a96: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8007a98: f7fd ff02 bl 80058a0 8007a9c: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8007a9e: e008 b.n 8007ab2 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8007aa0: f7fd fefe bl 80058a0 8007aa4: 4602 mov r2, r0 8007aa6: 693b ldr r3, [r7, #16] 8007aa8: 1ad3 subs r3, r2, r3 8007aaa: 2b02 cmp r3, #2 8007aac: d901 bls.n 8007ab2 { return HAL_TIMEOUT; 8007aae: 2303 movs r3, #3 8007ab0: e1f2 b.n 8007e98 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8007ab2: 4b0d ldr r3, [pc, #52] @ (8007ae8 ) 8007ab4: 6a5b ldr r3, [r3, #36] @ 0x24 8007ab6: f003 0302 and.w r3, r3, #2 8007aba: 2b00 cmp r3, #0 8007abc: d0f0 beq.n 8007aa0 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 8007abe: 2001 movs r0, #1 8007ac0: f000 fbec bl 800829c 8007ac4: e01c b.n 8007b00 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8007ac6: 4b0a ldr r3, [pc, #40] @ (8007af0 ) 8007ac8: 2200 movs r2, #0 8007aca: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8007acc: f7fd fee8 bl 80058a0 8007ad0: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8007ad2: e00f b.n 8007af4 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8007ad4: f7fd fee4 bl 80058a0 8007ad8: 4602 mov r2, r0 8007ada: 693b ldr r3, [r7, #16] 8007adc: 1ad3 subs r3, r2, r3 8007ade: 2b02 cmp r3, #2 8007ae0: d908 bls.n 8007af4 { return HAL_TIMEOUT; 8007ae2: 2303 movs r3, #3 8007ae4: e1d8 b.n 8007e98 8007ae6: bf00 nop 8007ae8: 40021000 .word 0x40021000 8007aec: 42420000 .word 0x42420000 8007af0: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8007af4: 4b9b ldr r3, [pc, #620] @ (8007d64 ) 8007af6: 6a5b ldr r3, [r3, #36] @ 0x24 8007af8: f003 0302 and.w r3, r3, #2 8007afc: 2b00 cmp r3, #0 8007afe: d1e9 bne.n 8007ad4 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8007b00: 687b ldr r3, [r7, #4] 8007b02: 681b ldr r3, [r3, #0] 8007b04: f003 0304 and.w r3, r3, #4 8007b08: 2b00 cmp r3, #0 8007b0a: f000 80a6 beq.w 8007c5a { FlagStatus pwrclkchanged = RESET; 8007b0e: 2300 movs r3, #0 8007b10: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8007b12: 4b94 ldr r3, [pc, #592] @ (8007d64 ) 8007b14: 69db ldr r3, [r3, #28] 8007b16: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8007b1a: 2b00 cmp r3, #0 8007b1c: d10d bne.n 8007b3a { __HAL_RCC_PWR_CLK_ENABLE(); 8007b1e: 4b91 ldr r3, [pc, #580] @ (8007d64 ) 8007b20: 69db ldr r3, [r3, #28] 8007b22: 4a90 ldr r2, [pc, #576] @ (8007d64 ) 8007b24: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007b28: 61d3 str r3, [r2, #28] 8007b2a: 4b8e ldr r3, [pc, #568] @ (8007d64 ) 8007b2c: 69db ldr r3, [r3, #28] 8007b2e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8007b32: 60bb str r3, [r7, #8] 8007b34: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8007b36: 2301 movs r3, #1 8007b38: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8007b3a: 4b8b ldr r3, [pc, #556] @ (8007d68 ) 8007b3c: 681b ldr r3, [r3, #0] 8007b3e: f403 7380 and.w r3, r3, #256 @ 0x100 8007b42: 2b00 cmp r3, #0 8007b44: d118 bne.n 8007b78 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8007b46: 4b88 ldr r3, [pc, #544] @ (8007d68 ) 8007b48: 681b ldr r3, [r3, #0] 8007b4a: 4a87 ldr r2, [pc, #540] @ (8007d68 ) 8007b4c: f443 7380 orr.w r3, r3, #256 @ 0x100 8007b50: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8007b52: f7fd fea5 bl 80058a0 8007b56: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8007b58: e008 b.n 8007b6c { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8007b5a: f7fd fea1 bl 80058a0 8007b5e: 4602 mov r2, r0 8007b60: 693b ldr r3, [r7, #16] 8007b62: 1ad3 subs r3, r2, r3 8007b64: 2b64 cmp r3, #100 @ 0x64 8007b66: d901 bls.n 8007b6c { return HAL_TIMEOUT; 8007b68: 2303 movs r3, #3 8007b6a: e195 b.n 8007e98 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8007b6c: 4b7e ldr r3, [pc, #504] @ (8007d68 ) 8007b6e: 681b ldr r3, [r3, #0] 8007b70: f403 7380 and.w r3, r3, #256 @ 0x100 8007b74: 2b00 cmp r3, #0 8007b76: d0f0 beq.n 8007b5a } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8007b78: 687b ldr r3, [r7, #4] 8007b7a: 691b ldr r3, [r3, #16] 8007b7c: 2b01 cmp r3, #1 8007b7e: d106 bne.n 8007b8e 8007b80: 4b78 ldr r3, [pc, #480] @ (8007d64 ) 8007b82: 6a1b ldr r3, [r3, #32] 8007b84: 4a77 ldr r2, [pc, #476] @ (8007d64 ) 8007b86: f043 0301 orr.w r3, r3, #1 8007b8a: 6213 str r3, [r2, #32] 8007b8c: e02d b.n 8007bea 8007b8e: 687b ldr r3, [r7, #4] 8007b90: 691b ldr r3, [r3, #16] 8007b92: 2b00 cmp r3, #0 8007b94: d10c bne.n 8007bb0 8007b96: 4b73 ldr r3, [pc, #460] @ (8007d64 ) 8007b98: 6a1b ldr r3, [r3, #32] 8007b9a: 4a72 ldr r2, [pc, #456] @ (8007d64 ) 8007b9c: f023 0301 bic.w r3, r3, #1 8007ba0: 6213 str r3, [r2, #32] 8007ba2: 4b70 ldr r3, [pc, #448] @ (8007d64 ) 8007ba4: 6a1b ldr r3, [r3, #32] 8007ba6: 4a6f ldr r2, [pc, #444] @ (8007d64 ) 8007ba8: f023 0304 bic.w r3, r3, #4 8007bac: 6213 str r3, [r2, #32] 8007bae: e01c b.n 8007bea 8007bb0: 687b ldr r3, [r7, #4] 8007bb2: 691b ldr r3, [r3, #16] 8007bb4: 2b05 cmp r3, #5 8007bb6: d10c bne.n 8007bd2 8007bb8: 4b6a ldr r3, [pc, #424] @ (8007d64 ) 8007bba: 6a1b ldr r3, [r3, #32] 8007bbc: 4a69 ldr r2, [pc, #420] @ (8007d64 ) 8007bbe: f043 0304 orr.w r3, r3, #4 8007bc2: 6213 str r3, [r2, #32] 8007bc4: 4b67 ldr r3, [pc, #412] @ (8007d64 ) 8007bc6: 6a1b ldr r3, [r3, #32] 8007bc8: 4a66 ldr r2, [pc, #408] @ (8007d64 ) 8007bca: f043 0301 orr.w r3, r3, #1 8007bce: 6213 str r3, [r2, #32] 8007bd0: e00b b.n 8007bea 8007bd2: 4b64 ldr r3, [pc, #400] @ (8007d64 ) 8007bd4: 6a1b ldr r3, [r3, #32] 8007bd6: 4a63 ldr r2, [pc, #396] @ (8007d64 ) 8007bd8: f023 0301 bic.w r3, r3, #1 8007bdc: 6213 str r3, [r2, #32] 8007bde: 4b61 ldr r3, [pc, #388] @ (8007d64 ) 8007be0: 6a1b ldr r3, [r3, #32] 8007be2: 4a60 ldr r2, [pc, #384] @ (8007d64 ) 8007be4: f023 0304 bic.w r3, r3, #4 8007be8: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8007bea: 687b ldr r3, [r7, #4] 8007bec: 691b ldr r3, [r3, #16] 8007bee: 2b00 cmp r3, #0 8007bf0: d015 beq.n 8007c1e { /* Get Start Tick */ tickstart = HAL_GetTick(); 8007bf2: f7fd fe55 bl 80058a0 8007bf6: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8007bf8: e00a b.n 8007c10 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8007bfa: f7fd fe51 bl 80058a0 8007bfe: 4602 mov r2, r0 8007c00: 693b ldr r3, [r7, #16] 8007c02: 1ad3 subs r3, r2, r3 8007c04: f241 3288 movw r2, #5000 @ 0x1388 8007c08: 4293 cmp r3, r2 8007c0a: d901 bls.n 8007c10 { return HAL_TIMEOUT; 8007c0c: 2303 movs r3, #3 8007c0e: e143 b.n 8007e98 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8007c10: 4b54 ldr r3, [pc, #336] @ (8007d64 ) 8007c12: 6a1b ldr r3, [r3, #32] 8007c14: f003 0302 and.w r3, r3, #2 8007c18: 2b00 cmp r3, #0 8007c1a: d0ee beq.n 8007bfa 8007c1c: e014 b.n 8007c48 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8007c1e: f7fd fe3f bl 80058a0 8007c22: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8007c24: e00a b.n 8007c3c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8007c26: f7fd fe3b bl 80058a0 8007c2a: 4602 mov r2, r0 8007c2c: 693b ldr r3, [r7, #16] 8007c2e: 1ad3 subs r3, r2, r3 8007c30: f241 3288 movw r2, #5000 @ 0x1388 8007c34: 4293 cmp r3, r2 8007c36: d901 bls.n 8007c3c { return HAL_TIMEOUT; 8007c38: 2303 movs r3, #3 8007c3a: e12d b.n 8007e98 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8007c3c: 4b49 ldr r3, [pc, #292] @ (8007d64 ) 8007c3e: 6a1b ldr r3, [r3, #32] 8007c40: f003 0302 and.w r3, r3, #2 8007c44: 2b00 cmp r3, #0 8007c46: d1ee bne.n 8007c26 } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8007c48: 7dfb ldrb r3, [r7, #23] 8007c4a: 2b01 cmp r3, #1 8007c4c: d105 bne.n 8007c5a { __HAL_RCC_PWR_CLK_DISABLE(); 8007c4e: 4b45 ldr r3, [pc, #276] @ (8007d64 ) 8007c50: 69db ldr r3, [r3, #28] 8007c52: 4a44 ldr r2, [pc, #272] @ (8007d64 ) 8007c54: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8007c58: 61d3 str r3, [r2, #28] #if defined(RCC_CR_PLL2ON) /*-------------------------------- PLL2 Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) 8007c5a: 687b ldr r3, [r7, #4] 8007c5c: 6adb ldr r3, [r3, #44] @ 0x2c 8007c5e: 2b00 cmp r3, #0 8007c60: f000 808c beq.w 8007d7c { /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 8007c64: 4b3f ldr r3, [pc, #252] @ (8007d64 ) 8007c66: 685b ldr r3, [r3, #4] 8007c68: f403 3380 and.w r3, r3, #65536 @ 0x10000 8007c6c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8007c70: d10e bne.n 8007c90 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 8007c72: 4b3c ldr r3, [pc, #240] @ (8007d64 ) 8007c74: 685b ldr r3, [r3, #4] 8007c76: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 8007c7a: 2b08 cmp r3, #8 8007c7c: d108 bne.n 8007c90 ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) 8007c7e: 4b39 ldr r3, [pc, #228] @ (8007d64 ) 8007c80: 6adb ldr r3, [r3, #44] @ 0x2c 8007c82: f403 3380 and.w r3, r3, #65536 @ 0x10000 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 8007c86: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8007c8a: d101 bne.n 8007c90 { return HAL_ERROR; 8007c8c: 2301 movs r3, #1 8007c8e: e103 b.n 8007e98 } else { if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) 8007c90: 687b ldr r3, [r7, #4] 8007c92: 6adb ldr r3, [r3, #44] @ 0x2c 8007c94: 2b02 cmp r3, #2 8007c96: d14e bne.n 8007d36 assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); /* Prediv2 can be written only when the PLLI2S is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 8007c98: 4b32 ldr r3, [pc, #200] @ (8007d64 ) 8007c9a: 681b ldr r3, [r3, #0] 8007c9c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8007ca0: 2b00 cmp r3, #0 8007ca2: d009 beq.n 8007cb8 (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) 8007ca4: 4b2f ldr r3, [pc, #188] @ (8007d64 ) 8007ca6: 6adb ldr r3, [r3, #44] @ 0x2c 8007ca8: f003 02f0 and.w r2, r3, #240 @ 0xf0 8007cac: 687b ldr r3, [r7, #4] 8007cae: 6b5b ldr r3, [r3, #52] @ 0x34 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 8007cb0: 429a cmp r2, r3 8007cb2: d001 beq.n 8007cb8 { return HAL_ERROR; 8007cb4: 2301 movs r3, #1 8007cb6: e0ef b.n 8007e98 } /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 8007cb8: 4b2c ldr r3, [pc, #176] @ (8007d6c ) 8007cba: 2200 movs r2, #0 8007cbc: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8007cbe: f7fd fdef bl 80058a0 8007cc2: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8007cc4: e008 b.n 8007cd8 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8007cc6: f7fd fdeb bl 80058a0 8007cca: 4602 mov r2, r0 8007ccc: 693b ldr r3, [r7, #16] 8007cce: 1ad3 subs r3, r2, r3 8007cd0: 2b64 cmp r3, #100 @ 0x64 8007cd2: d901 bls.n 8007cd8 { return HAL_TIMEOUT; 8007cd4: 2303 movs r3, #3 8007cd6: e0df b.n 8007e98 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8007cd8: 4b22 ldr r3, [pc, #136] @ (8007d64 ) 8007cda: 681b ldr r3, [r3, #0] 8007cdc: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8007ce0: 2b00 cmp r3, #0 8007ce2: d1f0 bne.n 8007cc6 } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); 8007ce4: 4b1f ldr r3, [pc, #124] @ (8007d64 ) 8007ce6: 6adb ldr r3, [r3, #44] @ 0x2c 8007ce8: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8007cec: 687b ldr r3, [r7, #4] 8007cee: 6b5b ldr r3, [r3, #52] @ 0x34 8007cf0: 491c ldr r1, [pc, #112] @ (8007d64 ) 8007cf2: 4313 orrs r3, r2 8007cf4: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); 8007cf6: 4b1b ldr r3, [pc, #108] @ (8007d64 ) 8007cf8: 6adb ldr r3, [r3, #44] @ 0x2c 8007cfa: f423 6270 bic.w r2, r3, #3840 @ 0xf00 8007cfe: 687b ldr r3, [r7, #4] 8007d00: 6b1b ldr r3, [r3, #48] @ 0x30 8007d02: 4918 ldr r1, [pc, #96] @ (8007d64 ) 8007d04: 4313 orrs r3, r2 8007d06: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); 8007d08: 4b18 ldr r3, [pc, #96] @ (8007d6c ) 8007d0a: 2201 movs r2, #1 8007d0c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8007d0e: f7fd fdc7 bl 80058a0 8007d12: 6138 str r0, [r7, #16] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8007d14: e008 b.n 8007d28 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8007d16: f7fd fdc3 bl 80058a0 8007d1a: 4602 mov r2, r0 8007d1c: 693b ldr r3, [r7, #16] 8007d1e: 1ad3 subs r3, r2, r3 8007d20: 2b64 cmp r3, #100 @ 0x64 8007d22: d901 bls.n 8007d28 { return HAL_TIMEOUT; 8007d24: 2303 movs r3, #3 8007d26: e0b7 b.n 8007e98 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8007d28: 4b0e ldr r3, [pc, #56] @ (8007d64 ) 8007d2a: 681b ldr r3, [r3, #0] 8007d2c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8007d30: 2b00 cmp r3, #0 8007d32: d0f0 beq.n 8007d16 8007d34: e022 b.n 8007d7c } } else { /* Set PREDIV1 source to HSE */ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); 8007d36: 4b0b ldr r3, [pc, #44] @ (8007d64 ) 8007d38: 6adb ldr r3, [r3, #44] @ 0x2c 8007d3a: 4a0a ldr r2, [pc, #40] @ (8007d64 ) 8007d3c: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8007d40: 62d3 str r3, [r2, #44] @ 0x2c /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 8007d42: 4b0a ldr r3, [pc, #40] @ (8007d6c ) 8007d44: 2200 movs r2, #0 8007d46: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8007d48: f7fd fdaa bl 80058a0 8007d4c: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8007d4e: e00f b.n 8007d70 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8007d50: f7fd fda6 bl 80058a0 8007d54: 4602 mov r2, r0 8007d56: 693b ldr r3, [r7, #16] 8007d58: 1ad3 subs r3, r2, r3 8007d5a: 2b64 cmp r3, #100 @ 0x64 8007d5c: d908 bls.n 8007d70 { return HAL_TIMEOUT; 8007d5e: 2303 movs r3, #3 8007d60: e09a b.n 8007e98 8007d62: bf00 nop 8007d64: 40021000 .word 0x40021000 8007d68: 40007000 .word 0x40007000 8007d6c: 42420068 .word 0x42420068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8007d70: 4b4b ldr r3, [pc, #300] @ (8007ea0 ) 8007d72: 681b ldr r3, [r3, #0] 8007d74: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8007d78: 2b00 cmp r3, #0 8007d7a: d1e9 bne.n 8007d50 #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8007d7c: 687b ldr r3, [r7, #4] 8007d7e: 6a1b ldr r3, [r3, #32] 8007d80: 2b00 cmp r3, #0 8007d82: f000 8088 beq.w 8007e96 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8007d86: 4b46 ldr r3, [pc, #280] @ (8007ea0 ) 8007d88: 685b ldr r3, [r3, #4] 8007d8a: f003 030c and.w r3, r3, #12 8007d8e: 2b08 cmp r3, #8 8007d90: d068 beq.n 8007e64 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8007d92: 687b ldr r3, [r7, #4] 8007d94: 6a1b ldr r3, [r3, #32] 8007d96: 2b02 cmp r3, #2 8007d98: d14d bne.n 8007e36 /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8007d9a: 4b42 ldr r3, [pc, #264] @ (8007ea4 ) 8007d9c: 2200 movs r2, #0 8007d9e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8007da0: f7fd fd7e bl 80058a0 8007da4: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8007da6: e008 b.n 8007dba { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8007da8: f7fd fd7a bl 80058a0 8007dac: 4602 mov r2, r0 8007dae: 693b ldr r3, [r7, #16] 8007db0: 1ad3 subs r3, r2, r3 8007db2: 2b02 cmp r3, #2 8007db4: d901 bls.n 8007dba { return HAL_TIMEOUT; 8007db6: 2303 movs r3, #3 8007db8: e06e b.n 8007e98 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8007dba: 4b39 ldr r3, [pc, #228] @ (8007ea0 ) 8007dbc: 681b ldr r3, [r3, #0] 8007dbe: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8007dc2: 2b00 cmp r3, #0 8007dc4: d1f0 bne.n 8007da8 } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 8007dc6: 687b ldr r3, [r7, #4] 8007dc8: 6a5b ldr r3, [r3, #36] @ 0x24 8007dca: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8007dce: d10f bne.n 8007df0 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); #if defined(RCC_CFGR2_PREDIV1SRC) assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); 8007dd0: 4b33 ldr r3, [pc, #204] @ (8007ea0 ) 8007dd2: 6ada ldr r2, [r3, #44] @ 0x2c 8007dd4: 687b ldr r3, [r7, #4] 8007dd6: 685b ldr r3, [r3, #4] 8007dd8: 4931 ldr r1, [pc, #196] @ (8007ea0 ) 8007dda: 4313 orrs r3, r2 8007ddc: 62cb str r3, [r1, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8007dde: 4b30 ldr r3, [pc, #192] @ (8007ea0 ) 8007de0: 6adb ldr r3, [r3, #44] @ 0x2c 8007de2: f023 020f bic.w r2, r3, #15 8007de6: 687b ldr r3, [r7, #4] 8007de8: 68db ldr r3, [r3, #12] 8007dea: 492d ldr r1, [pc, #180] @ (8007ea0 ) 8007dec: 4313 orrs r3, r2 8007dee: 62cb str r3, [r1, #44] @ 0x2c } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8007df0: 4b2b ldr r3, [pc, #172] @ (8007ea0 ) 8007df2: 685b ldr r3, [r3, #4] 8007df4: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 8007df8: 687b ldr r3, [r7, #4] 8007dfa: 6a59 ldr r1, [r3, #36] @ 0x24 8007dfc: 687b ldr r3, [r7, #4] 8007dfe: 6a9b ldr r3, [r3, #40] @ 0x28 8007e00: 430b orrs r3, r1 8007e02: 4927 ldr r1, [pc, #156] @ (8007ea0 ) 8007e04: 4313 orrs r3, r2 8007e06: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8007e08: 4b26 ldr r3, [pc, #152] @ (8007ea4 ) 8007e0a: 2201 movs r2, #1 8007e0c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8007e0e: f7fd fd47 bl 80058a0 8007e12: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8007e14: e008 b.n 8007e28 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8007e16: f7fd fd43 bl 80058a0 8007e1a: 4602 mov r2, r0 8007e1c: 693b ldr r3, [r7, #16] 8007e1e: 1ad3 subs r3, r2, r3 8007e20: 2b02 cmp r3, #2 8007e22: d901 bls.n 8007e28 { return HAL_TIMEOUT; 8007e24: 2303 movs r3, #3 8007e26: e037 b.n 8007e98 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8007e28: 4b1d ldr r3, [pc, #116] @ (8007ea0 ) 8007e2a: 681b ldr r3, [r3, #0] 8007e2c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8007e30: 2b00 cmp r3, #0 8007e32: d0f0 beq.n 8007e16 8007e34: e02f b.n 8007e96 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8007e36: 4b1b ldr r3, [pc, #108] @ (8007ea4 ) 8007e38: 2200 movs r2, #0 8007e3a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8007e3c: f7fd fd30 bl 80058a0 8007e40: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8007e42: e008 b.n 8007e56 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8007e44: f7fd fd2c bl 80058a0 8007e48: 4602 mov r2, r0 8007e4a: 693b ldr r3, [r7, #16] 8007e4c: 1ad3 subs r3, r2, r3 8007e4e: 2b02 cmp r3, #2 8007e50: d901 bls.n 8007e56 { return HAL_TIMEOUT; 8007e52: 2303 movs r3, #3 8007e54: e020 b.n 8007e98 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8007e56: 4b12 ldr r3, [pc, #72] @ (8007ea0 ) 8007e58: 681b ldr r3, [r3, #0] 8007e5a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8007e5e: 2b00 cmp r3, #0 8007e60: d1f0 bne.n 8007e44 8007e62: e018 b.n 8007e96 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8007e64: 687b ldr r3, [r7, #4] 8007e66: 6a1b ldr r3, [r3, #32] 8007e68: 2b01 cmp r3, #1 8007e6a: d101 bne.n 8007e70 { return HAL_ERROR; 8007e6c: 2301 movs r3, #1 8007e6e: e013 b.n 8007e98 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8007e70: 4b0b ldr r3, [pc, #44] @ (8007ea0 ) 8007e72: 685b ldr r3, [r3, #4] 8007e74: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8007e76: 68fb ldr r3, [r7, #12] 8007e78: f403 3280 and.w r2, r3, #65536 @ 0x10000 8007e7c: 687b ldr r3, [r7, #4] 8007e7e: 6a5b ldr r3, [r3, #36] @ 0x24 8007e80: 429a cmp r2, r3 8007e82: d106 bne.n 8007e92 (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8007e84: 68fb ldr r3, [r7, #12] 8007e86: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 8007e8a: 687b ldr r3, [r7, #4] 8007e8c: 6a9b ldr r3, [r3, #40] @ 0x28 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8007e8e: 429a cmp r2, r3 8007e90: d001 beq.n 8007e96 { return HAL_ERROR; 8007e92: 2301 movs r3, #1 8007e94: e000 b.n 8007e98 } } } } return HAL_OK; 8007e96: 2300 movs r3, #0 } 8007e98: 4618 mov r0, r3 8007e9a: 3718 adds r7, #24 8007e9c: 46bd mov sp, r7 8007e9e: bd80 pop {r7, pc} 8007ea0: 40021000 .word 0x40021000 8007ea4: 42420060 .word 0x42420060 08007ea8 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8007ea8: b580 push {r7, lr} 8007eaa: b084 sub sp, #16 8007eac: af00 add r7, sp, #0 8007eae: 6078 str r0, [r7, #4] 8007eb0: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8007eb2: 687b ldr r3, [r7, #4] 8007eb4: 2b00 cmp r3, #0 8007eb6: d101 bne.n 8007ebc { return HAL_ERROR; 8007eb8: 2301 movs r3, #1 8007eba: e0d0 b.n 800805e must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8007ebc: 4b6a ldr r3, [pc, #424] @ (8008068 ) 8007ebe: 681b ldr r3, [r3, #0] 8007ec0: f003 0307 and.w r3, r3, #7 8007ec4: 683a ldr r2, [r7, #0] 8007ec6: 429a cmp r2, r3 8007ec8: d910 bls.n 8007eec { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8007eca: 4b67 ldr r3, [pc, #412] @ (8008068 ) 8007ecc: 681b ldr r3, [r3, #0] 8007ece: f023 0207 bic.w r2, r3, #7 8007ed2: 4965 ldr r1, [pc, #404] @ (8008068 ) 8007ed4: 683b ldr r3, [r7, #0] 8007ed6: 4313 orrs r3, r2 8007ed8: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8007eda: 4b63 ldr r3, [pc, #396] @ (8008068 ) 8007edc: 681b ldr r3, [r3, #0] 8007ede: f003 0307 and.w r3, r3, #7 8007ee2: 683a ldr r2, [r7, #0] 8007ee4: 429a cmp r2, r3 8007ee6: d001 beq.n 8007eec { return HAL_ERROR; 8007ee8: 2301 movs r3, #1 8007eea: e0b8 b.n 800805e } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8007eec: 687b ldr r3, [r7, #4] 8007eee: 681b ldr r3, [r3, #0] 8007ef0: f003 0302 and.w r3, r3, #2 8007ef4: 2b00 cmp r3, #0 8007ef6: d020 beq.n 8007f3a { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8007ef8: 687b ldr r3, [r7, #4] 8007efa: 681b ldr r3, [r3, #0] 8007efc: f003 0304 and.w r3, r3, #4 8007f00: 2b00 cmp r3, #0 8007f02: d005 beq.n 8007f10 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8007f04: 4b59 ldr r3, [pc, #356] @ (800806c ) 8007f06: 685b ldr r3, [r3, #4] 8007f08: 4a58 ldr r2, [pc, #352] @ (800806c ) 8007f0a: f443 63e0 orr.w r3, r3, #1792 @ 0x700 8007f0e: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8007f10: 687b ldr r3, [r7, #4] 8007f12: 681b ldr r3, [r3, #0] 8007f14: f003 0308 and.w r3, r3, #8 8007f18: 2b00 cmp r3, #0 8007f1a: d005 beq.n 8007f28 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8007f1c: 4b53 ldr r3, [pc, #332] @ (800806c ) 8007f1e: 685b ldr r3, [r3, #4] 8007f20: 4a52 ldr r2, [pc, #328] @ (800806c ) 8007f22: f443 5360 orr.w r3, r3, #14336 @ 0x3800 8007f26: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8007f28: 4b50 ldr r3, [pc, #320] @ (800806c ) 8007f2a: 685b ldr r3, [r3, #4] 8007f2c: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8007f30: 687b ldr r3, [r7, #4] 8007f32: 689b ldr r3, [r3, #8] 8007f34: 494d ldr r1, [pc, #308] @ (800806c ) 8007f36: 4313 orrs r3, r2 8007f38: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8007f3a: 687b ldr r3, [r7, #4] 8007f3c: 681b ldr r3, [r3, #0] 8007f3e: f003 0301 and.w r3, r3, #1 8007f42: 2b00 cmp r3, #0 8007f44: d040 beq.n 8007fc8 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8007f46: 687b ldr r3, [r7, #4] 8007f48: 685b ldr r3, [r3, #4] 8007f4a: 2b01 cmp r3, #1 8007f4c: d107 bne.n 8007f5e { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8007f4e: 4b47 ldr r3, [pc, #284] @ (800806c ) 8007f50: 681b ldr r3, [r3, #0] 8007f52: f403 3300 and.w r3, r3, #131072 @ 0x20000 8007f56: 2b00 cmp r3, #0 8007f58: d115 bne.n 8007f86 { return HAL_ERROR; 8007f5a: 2301 movs r3, #1 8007f5c: e07f b.n 800805e } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8007f5e: 687b ldr r3, [r7, #4] 8007f60: 685b ldr r3, [r3, #4] 8007f62: 2b02 cmp r3, #2 8007f64: d107 bne.n 8007f76 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8007f66: 4b41 ldr r3, [pc, #260] @ (800806c ) 8007f68: 681b ldr r3, [r3, #0] 8007f6a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8007f6e: 2b00 cmp r3, #0 8007f70: d109 bne.n 8007f86 { return HAL_ERROR; 8007f72: 2301 movs r3, #1 8007f74: e073 b.n 800805e } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8007f76: 4b3d ldr r3, [pc, #244] @ (800806c ) 8007f78: 681b ldr r3, [r3, #0] 8007f7a: f003 0302 and.w r3, r3, #2 8007f7e: 2b00 cmp r3, #0 8007f80: d101 bne.n 8007f86 { return HAL_ERROR; 8007f82: 2301 movs r3, #1 8007f84: e06b b.n 800805e } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8007f86: 4b39 ldr r3, [pc, #228] @ (800806c ) 8007f88: 685b ldr r3, [r3, #4] 8007f8a: f023 0203 bic.w r2, r3, #3 8007f8e: 687b ldr r3, [r7, #4] 8007f90: 685b ldr r3, [r3, #4] 8007f92: 4936 ldr r1, [pc, #216] @ (800806c ) 8007f94: 4313 orrs r3, r2 8007f96: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8007f98: f7fd fc82 bl 80058a0 8007f9c: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8007f9e: e00a b.n 8007fb6 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8007fa0: f7fd fc7e bl 80058a0 8007fa4: 4602 mov r2, r0 8007fa6: 68fb ldr r3, [r7, #12] 8007fa8: 1ad3 subs r3, r2, r3 8007faa: f241 3288 movw r2, #5000 @ 0x1388 8007fae: 4293 cmp r3, r2 8007fb0: d901 bls.n 8007fb6 { return HAL_TIMEOUT; 8007fb2: 2303 movs r3, #3 8007fb4: e053 b.n 800805e while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8007fb6: 4b2d ldr r3, [pc, #180] @ (800806c ) 8007fb8: 685b ldr r3, [r3, #4] 8007fba: f003 020c and.w r2, r3, #12 8007fbe: 687b ldr r3, [r7, #4] 8007fc0: 685b ldr r3, [r3, #4] 8007fc2: 009b lsls r3, r3, #2 8007fc4: 429a cmp r2, r3 8007fc6: d1eb bne.n 8007fa0 } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8007fc8: 4b27 ldr r3, [pc, #156] @ (8008068 ) 8007fca: 681b ldr r3, [r3, #0] 8007fcc: f003 0307 and.w r3, r3, #7 8007fd0: 683a ldr r2, [r7, #0] 8007fd2: 429a cmp r2, r3 8007fd4: d210 bcs.n 8007ff8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8007fd6: 4b24 ldr r3, [pc, #144] @ (8008068 ) 8007fd8: 681b ldr r3, [r3, #0] 8007fda: f023 0207 bic.w r2, r3, #7 8007fde: 4922 ldr r1, [pc, #136] @ (8008068 ) 8007fe0: 683b ldr r3, [r7, #0] 8007fe2: 4313 orrs r3, r2 8007fe4: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8007fe6: 4b20 ldr r3, [pc, #128] @ (8008068 ) 8007fe8: 681b ldr r3, [r3, #0] 8007fea: f003 0307 and.w r3, r3, #7 8007fee: 683a ldr r2, [r7, #0] 8007ff0: 429a cmp r2, r3 8007ff2: d001 beq.n 8007ff8 { return HAL_ERROR; 8007ff4: 2301 movs r3, #1 8007ff6: e032 b.n 800805e } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8007ff8: 687b ldr r3, [r7, #4] 8007ffa: 681b ldr r3, [r3, #0] 8007ffc: f003 0304 and.w r3, r3, #4 8008000: 2b00 cmp r3, #0 8008002: d008 beq.n 8008016 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8008004: 4b19 ldr r3, [pc, #100] @ (800806c ) 8008006: 685b ldr r3, [r3, #4] 8008008: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800800c: 687b ldr r3, [r7, #4] 800800e: 68db ldr r3, [r3, #12] 8008010: 4916 ldr r1, [pc, #88] @ (800806c ) 8008012: 4313 orrs r3, r2 8008014: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8008016: 687b ldr r3, [r7, #4] 8008018: 681b ldr r3, [r3, #0] 800801a: f003 0308 and.w r3, r3, #8 800801e: 2b00 cmp r3, #0 8008020: d009 beq.n 8008036 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 8008022: 4b12 ldr r3, [pc, #72] @ (800806c ) 8008024: 685b ldr r3, [r3, #4] 8008026: f423 5260 bic.w r2, r3, #14336 @ 0x3800 800802a: 687b ldr r3, [r7, #4] 800802c: 691b ldr r3, [r3, #16] 800802e: 00db lsls r3, r3, #3 8008030: 490e ldr r1, [pc, #56] @ (800806c ) 8008032: 4313 orrs r3, r2 8008034: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8008036: f000 f821 bl 800807c 800803a: 4602 mov r2, r0 800803c: 4b0b ldr r3, [pc, #44] @ (800806c ) 800803e: 685b ldr r3, [r3, #4] 8008040: 091b lsrs r3, r3, #4 8008042: f003 030f and.w r3, r3, #15 8008046: 490a ldr r1, [pc, #40] @ (8008070 ) 8008048: 5ccb ldrb r3, [r1, r3] 800804a: fa22 f303 lsr.w r3, r2, r3 800804e: 4a09 ldr r2, [pc, #36] @ (8008074 ) 8008050: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 8008052: 4b09 ldr r3, [pc, #36] @ (8008078 ) 8008054: 681b ldr r3, [r3, #0] 8008056: 4618 mov r0, r3 8008058: f7fd fbe0 bl 800581c return HAL_OK; 800805c: 2300 movs r3, #0 } 800805e: 4618 mov r0, r3 8008060: 3710 adds r7, #16 8008062: 46bd mov sp, r7 8008064: bd80 pop {r7, pc} 8008066: bf00 nop 8008068: 40022000 .word 0x40022000 800806c: 40021000 .word 0x40021000 8008070: 0800df9c .word 0x0800df9c 8008074: 20000018 .word 0x20000018 8008078: 2000001c .word 0x2000001c 0800807c : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800807c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8008080: b099 sub sp, #100 @ 0x64 8008082: af00 add r7, sp, #0 #if defined(RCC_CFGR2_PREDIV1SRC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; 8008084: 4b66 ldr r3, [pc, #408] @ (8008220 ) 8008086: f107 0434 add.w r4, r7, #52 @ 0x34 800808a: cb0f ldmia r3, {r0, r1, r2, r3} 800808c: c407 stmia r4!, {r0, r1, r2} 800808e: 8023 strh r3, [r4, #0] const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; 8008090: 4b64 ldr r3, [pc, #400] @ (8008224 ) 8008092: f107 0424 add.w r4, r7, #36 @ 0x24 8008096: cb0f ldmia r3, {r0, r1, r2, r3} 8008098: e884 000f stmia.w r4, {r0, r1, r2, r3} #else const uint8_t aPredivFactorTable[2] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 800809c: 2300 movs r3, #0 800809e: 657b str r3, [r7, #84] @ 0x54 80080a0: 2300 movs r3, #0 80080a2: 653b str r3, [r7, #80] @ 0x50 80080a4: 2300 movs r3, #0 80080a6: 65fb str r3, [r7, #92] @ 0x5c 80080a8: 2300 movs r3, #0 80080aa: 64fb str r3, [r7, #76] @ 0x4c uint32_t sysclockfreq = 0U; 80080ac: 2300 movs r3, #0 80080ae: 65bb str r3, [r7, #88] @ 0x58 #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; 80080b0: 2300 movs r3, #0 80080b2: 64bb str r3, [r7, #72] @ 0x48 80080b4: 2300 movs r3, #0 80080b6: 647b str r3, [r7, #68] @ 0x44 #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 80080b8: 4b5b ldr r3, [pc, #364] @ (8008228 ) 80080ba: 685b ldr r3, [r3, #4] 80080bc: 657b str r3, [r7, #84] @ 0x54 /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 80080be: 6d7b ldr r3, [r7, #84] @ 0x54 80080c0: f003 030c and.w r3, r3, #12 80080c4: 2b04 cmp r3, #4 80080c6: d002 beq.n 80080ce 80080c8: 2b08 cmp r3, #8 80080ca: d003 beq.n 80080d4 80080cc: e09f b.n 800820e { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 80080ce: 4b57 ldr r3, [pc, #348] @ (800822c ) 80080d0: 65bb str r3, [r7, #88] @ 0x58 break; 80080d2: e09f b.n 8008214 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 80080d4: 6d7b ldr r3, [r7, #84] @ 0x54 80080d6: 0c9b lsrs r3, r3, #18 80080d8: f003 030f and.w r3, r3, #15 80080dc: 3340 adds r3, #64 @ 0x40 80080de: f107 0220 add.w r2, r7, #32 80080e2: 4413 add r3, r2 80080e4: f813 3c2c ldrb.w r3, [r3, #-44] 80080e8: 64fb str r3, [r7, #76] @ 0x4c if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 80080ea: 6d7b ldr r3, [r7, #84] @ 0x54 80080ec: f403 3380 and.w r3, r3, #65536 @ 0x10000 80080f0: 2b00 cmp r3, #0 80080f2: f000 8084 beq.w 80081fe { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 80080f6: 4b4c ldr r3, [pc, #304] @ (8008228 ) 80080f8: 6adb ldr r3, [r3, #44] @ 0x2c 80080fa: f003 030f and.w r3, r3, #15 80080fe: 3340 adds r3, #64 @ 0x40 8008100: f107 0220 add.w r2, r7, #32 8008104: 4413 add r3, r2 8008106: f813 3c3c ldrb.w r3, [r3, #-60] 800810a: 653b str r3, [r7, #80] @ 0x50 #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /*RCC_CFGR2_PREDIV1*/ #if defined(RCC_CFGR2_PREDIV1SRC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 800810c: 4b46 ldr r3, [pc, #280] @ (8008228 ) 800810e: 6adb ldr r3, [r3, #44] @ 0x2c 8008110: f403 3380 and.w r3, r3, #65536 @ 0x10000 8008114: 2b00 cmp r3, #0 8008116: d060 beq.n 80081da { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8008118: 4b43 ldr r3, [pc, #268] @ (8008228 ) 800811a: 6adb ldr r3, [r3, #44] @ 0x2c 800811c: 091b lsrs r3, r3, #4 800811e: f003 030f and.w r3, r3, #15 8008122: 3301 adds r3, #1 8008124: 64bb str r3, [r7, #72] @ 0x48 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 8008126: 4b40 ldr r3, [pc, #256] @ (8008228 ) 8008128: 6adb ldr r3, [r3, #44] @ 0x2c 800812a: 0a1b lsrs r3, r3, #8 800812c: f003 030f and.w r3, r3, #15 8008130: 3302 adds r3, #2 8008132: 647b str r3, [r7, #68] @ 0x44 pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); 8008134: 6c7b ldr r3, [r7, #68] @ 0x44 8008136: 2200 movs r2, #0 8008138: 613b str r3, [r7, #16] 800813a: 617a str r2, [r7, #20] 800813c: 6cfb ldr r3, [r7, #76] @ 0x4c 800813e: 2200 movs r2, #0 8008140: 61bb str r3, [r7, #24] 8008142: 61fa str r2, [r7, #28] 8008144: e9d7 3404 ldrd r3, r4, [r7, #16] 8008148: 4622 mov r2, r4 800814a: e9d7 0106 ldrd r0, r1, [r7, #24] 800814e: 4684 mov ip, r0 8008150: fb0c f202 mul.w r2, ip, r2 8008154: e9c7 0106 strd r0, r1, [r7, #24] 8008158: 468c mov ip, r1 800815a: 4618 mov r0, r3 800815c: 4621 mov r1, r4 800815e: 4603 mov r3, r0 8008160: fb03 f30c mul.w r3, r3, ip 8008164: 4413 add r3, r2 8008166: 4602 mov r2, r0 8008168: 69b9 ldr r1, [r7, #24] 800816a: fba2 8901 umull r8, r9, r2, r1 800816e: 444b add r3, r9 8008170: 4699 mov r9, r3 8008172: 4b2e ldr r3, [pc, #184] @ (800822c ) 8008174: fb03 f209 mul.w r2, r3, r9 8008178: 2300 movs r3, #0 800817a: fb03 f308 mul.w r3, r3, r8 800817e: 4413 add r3, r2 8008180: 4a2a ldr r2, [pc, #168] @ (800822c ) 8008182: fba8 ab02 umull sl, fp, r8, r2 8008186: 445b add r3, fp 8008188: 469b mov fp, r3 800818a: 6cbb ldr r3, [r7, #72] @ 0x48 800818c: 2200 movs r2, #0 800818e: 60bb str r3, [r7, #8] 8008190: 60fa str r2, [r7, #12] 8008192: 6d3b ldr r3, [r7, #80] @ 0x50 8008194: 2200 movs r2, #0 8008196: 603b str r3, [r7, #0] 8008198: 607a str r2, [r7, #4] 800819a: e9d7 3402 ldrd r3, r4, [r7, #8] 800819e: 4622 mov r2, r4 80081a0: e9d7 8900 ldrd r8, r9, [r7] 80081a4: 4641 mov r1, r8 80081a6: fb01 f202 mul.w r2, r1, r2 80081aa: 46cc mov ip, r9 80081ac: 4618 mov r0, r3 80081ae: 4621 mov r1, r4 80081b0: 4603 mov r3, r0 80081b2: fb03 f30c mul.w r3, r3, ip 80081b6: 4413 add r3, r2 80081b8: 4602 mov r2, r0 80081ba: 4641 mov r1, r8 80081bc: fba2 5601 umull r5, r6, r2, r1 80081c0: 4433 add r3, r6 80081c2: 461e mov r6, r3 80081c4: 462a mov r2, r5 80081c6: 4633 mov r3, r6 80081c8: 4650 mov r0, sl 80081ca: 4659 mov r1, fp 80081cc: f7f9 f86c bl 80012a8 <__aeabi_uldivmod> 80081d0: 4602 mov r2, r0 80081d2: 460b mov r3, r1 80081d4: 4613 mov r3, r2 80081d6: 65fb str r3, [r7, #92] @ 0x5c 80081d8: e007 b.n 80081ea } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 80081da: 6cfb ldr r3, [r7, #76] @ 0x4c 80081dc: 4a13 ldr r2, [pc, #76] @ (800822c ) 80081de: fb03 f202 mul.w r2, r3, r2 80081e2: 6d3b ldr r3, [r7, #80] @ 0x50 80081e4: fbb2 f3f3 udiv r3, r2, r3 80081e8: 65fb str r3, [r7, #92] @ 0x5c } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 80081ea: f897 3041 ldrb.w r3, [r7, #65] @ 0x41 80081ee: 461a mov r2, r3 80081f0: 6cfb ldr r3, [r7, #76] @ 0x4c 80081f2: 4293 cmp r3, r2 80081f4: d108 bne.n 8008208 { pllclk = pllclk / 2; 80081f6: 6dfb ldr r3, [r7, #92] @ 0x5c 80081f8: 085b lsrs r3, r3, #1 80081fa: 65fb str r3, [r7, #92] @ 0x5c 80081fc: e004 b.n 8008208 #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 80081fe: 6cfb ldr r3, [r7, #76] @ 0x4c 8008200: 4a0b ldr r2, [pc, #44] @ (8008230 ) 8008202: fb02 f303 mul.w r3, r2, r3 8008206: 65fb str r3, [r7, #92] @ 0x5c } sysclockfreq = pllclk; 8008208: 6dfb ldr r3, [r7, #92] @ 0x5c 800820a: 65bb str r3, [r7, #88] @ 0x58 break; 800820c: e002 b.n 8008214 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 800820e: 4b09 ldr r3, [pc, #36] @ (8008234 ) 8008210: 65bb str r3, [r7, #88] @ 0x58 break; 8008212: bf00 nop } } return sysclockfreq; 8008214: 6dbb ldr r3, [r7, #88] @ 0x58 } 8008216: 4618 mov r0, r3 8008218: 3764 adds r7, #100 @ 0x64 800821a: 46bd mov sp, r7 800821c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8008220: 0800df50 .word 0x0800df50 8008224: 0800df60 .word 0x0800df60 8008228: 40021000 .word 0x40021000 800822c: 017d7840 .word 0x017d7840 8008230: 003d0900 .word 0x003d0900 8008234: 007a1200 .word 0x007a1200 08008238 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8008238: b480 push {r7} 800823a: af00 add r7, sp, #0 return SystemCoreClock; 800823c: 4b02 ldr r3, [pc, #8] @ (8008248 ) 800823e: 681b ldr r3, [r3, #0] } 8008240: 4618 mov r0, r3 8008242: 46bd mov sp, r7 8008244: bc80 pop {r7} 8008246: 4770 bx lr 8008248: 20000018 .word 0x20000018 0800824c : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 800824c: b580 push {r7, lr} 800824e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8008250: f7ff fff2 bl 8008238 8008254: 4602 mov r2, r0 8008256: 4b05 ldr r3, [pc, #20] @ (800826c ) 8008258: 685b ldr r3, [r3, #4] 800825a: 0a1b lsrs r3, r3, #8 800825c: f003 0307 and.w r3, r3, #7 8008260: 4903 ldr r1, [pc, #12] @ (8008270 ) 8008262: 5ccb ldrb r3, [r1, r3] 8008264: fa22 f303 lsr.w r3, r2, r3 } 8008268: 4618 mov r0, r3 800826a: bd80 pop {r7, pc} 800826c: 40021000 .word 0x40021000 8008270: 0800dfac .word 0x0800dfac 08008274 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8008274: b580 push {r7, lr} 8008276: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8008278: f7ff ffde bl 8008238 800827c: 4602 mov r2, r0 800827e: 4b05 ldr r3, [pc, #20] @ (8008294 ) 8008280: 685b ldr r3, [r3, #4] 8008282: 0adb lsrs r3, r3, #11 8008284: f003 0307 and.w r3, r3, #7 8008288: 4903 ldr r1, [pc, #12] @ (8008298 ) 800828a: 5ccb ldrb r3, [r1, r3] 800828c: fa22 f303 lsr.w r3, r2, r3 } 8008290: 4618 mov r0, r3 8008292: bd80 pop {r7, pc} 8008294: 40021000 .word 0x40021000 8008298: 0800dfac .word 0x0800dfac 0800829c : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 800829c: b480 push {r7} 800829e: b085 sub sp, #20 80082a0: af00 add r7, sp, #0 80082a2: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 80082a4: 4b0a ldr r3, [pc, #40] @ (80082d0 ) 80082a6: 681b ldr r3, [r3, #0] 80082a8: 4a0a ldr r2, [pc, #40] @ (80082d4 ) 80082aa: fba2 2303 umull r2, r3, r2, r3 80082ae: 0a5b lsrs r3, r3, #9 80082b0: 687a ldr r2, [r7, #4] 80082b2: fb02 f303 mul.w r3, r2, r3 80082b6: 60fb str r3, [r7, #12] do { __NOP(); 80082b8: bf00 nop } while (Delay --); 80082ba: 68fb ldr r3, [r7, #12] 80082bc: 1e5a subs r2, r3, #1 80082be: 60fa str r2, [r7, #12] 80082c0: 2b00 cmp r3, #0 80082c2: d1f9 bne.n 80082b8 } 80082c4: bf00 nop 80082c6: bf00 nop 80082c8: 3714 adds r7, #20 80082ca: 46bd mov sp, r7 80082cc: bc80 pop {r7} 80082ce: 4770 bx lr 80082d0: 20000018 .word 0x20000018 80082d4: 10624dd3 .word 0x10624dd3 080082d8 : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 80082d8: b580 push {r7, lr} 80082da: b088 sub sp, #32 80082dc: af00 add r7, sp, #0 80082de: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 80082e0: 2300 movs r3, #0 80082e2: 617b str r3, [r7, #20] 80082e4: 2300 movs r3, #0 80082e6: 613b str r3, [r7, #16] #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t pllactive = 0U; 80082e8: 2300 movs r3, #0 80082ea: 61fb str r3, [r7, #28] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 80082ec: 687b ldr r3, [r7, #4] 80082ee: 681b ldr r3, [r3, #0] 80082f0: f003 0301 and.w r3, r3, #1 80082f4: 2b00 cmp r3, #0 80082f6: d07d beq.n 80083f4 { FlagStatus pwrclkchanged = RESET; 80082f8: 2300 movs r3, #0 80082fa: 76fb strb r3, [r7, #27] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80082fc: 4b8b ldr r3, [pc, #556] @ (800852c ) 80082fe: 69db ldr r3, [r3, #28] 8008300: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8008304: 2b00 cmp r3, #0 8008306: d10d bne.n 8008324 { __HAL_RCC_PWR_CLK_ENABLE(); 8008308: 4b88 ldr r3, [pc, #544] @ (800852c ) 800830a: 69db ldr r3, [r3, #28] 800830c: 4a87 ldr r2, [pc, #540] @ (800852c ) 800830e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8008312: 61d3 str r3, [r2, #28] 8008314: 4b85 ldr r3, [pc, #532] @ (800852c ) 8008316: 69db ldr r3, [r3, #28] 8008318: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800831c: 60fb str r3, [r7, #12] 800831e: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8008320: 2301 movs r3, #1 8008322: 76fb strb r3, [r7, #27] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8008324: 4b82 ldr r3, [pc, #520] @ (8008530 ) 8008326: 681b ldr r3, [r3, #0] 8008328: f403 7380 and.w r3, r3, #256 @ 0x100 800832c: 2b00 cmp r3, #0 800832e: d118 bne.n 8008362 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8008330: 4b7f ldr r3, [pc, #508] @ (8008530 ) 8008332: 681b ldr r3, [r3, #0] 8008334: 4a7e ldr r2, [pc, #504] @ (8008530 ) 8008336: f443 7380 orr.w r3, r3, #256 @ 0x100 800833a: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800833c: f7fd fab0 bl 80058a0 8008340: 6178 str r0, [r7, #20] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8008342: e008 b.n 8008356 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8008344: f7fd faac bl 80058a0 8008348: 4602 mov r2, r0 800834a: 697b ldr r3, [r7, #20] 800834c: 1ad3 subs r3, r2, r3 800834e: 2b64 cmp r3, #100 @ 0x64 8008350: d901 bls.n 8008356 { return HAL_TIMEOUT; 8008352: 2303 movs r3, #3 8008354: e0e5 b.n 8008522 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8008356: 4b76 ldr r3, [pc, #472] @ (8008530 ) 8008358: 681b ldr r3, [r3, #0] 800835a: f403 7380 and.w r3, r3, #256 @ 0x100 800835e: 2b00 cmp r3, #0 8008360: d0f0 beq.n 8008344 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 8008362: 4b72 ldr r3, [pc, #456] @ (800852c ) 8008364: 6a1b ldr r3, [r3, #32] 8008366: f403 7340 and.w r3, r3, #768 @ 0x300 800836a: 613b str r3, [r7, #16] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 800836c: 693b ldr r3, [r7, #16] 800836e: 2b00 cmp r3, #0 8008370: d02e beq.n 80083d0 8008372: 687b ldr r3, [r7, #4] 8008374: 685b ldr r3, [r3, #4] 8008376: f403 7340 and.w r3, r3, #768 @ 0x300 800837a: 693a ldr r2, [r7, #16] 800837c: 429a cmp r2, r3 800837e: d027 beq.n 80083d0 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8008380: 4b6a ldr r3, [pc, #424] @ (800852c ) 8008382: 6a1b ldr r3, [r3, #32] 8008384: f423 7340 bic.w r3, r3, #768 @ 0x300 8008388: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 800838a: 4b6a ldr r3, [pc, #424] @ (8008534 ) 800838c: 2201 movs r2, #1 800838e: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8008390: 4b68 ldr r3, [pc, #416] @ (8008534 ) 8008392: 2200 movs r2, #0 8008394: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 8008396: 4a65 ldr r2, [pc, #404] @ (800852c ) 8008398: 693b ldr r3, [r7, #16] 800839a: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 800839c: 693b ldr r3, [r7, #16] 800839e: f003 0301 and.w r3, r3, #1 80083a2: 2b00 cmp r3, #0 80083a4: d014 beq.n 80083d0 { /* Get Start Tick */ tickstart = HAL_GetTick(); 80083a6: f7fd fa7b bl 80058a0 80083aa: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80083ac: e00a b.n 80083c4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80083ae: f7fd fa77 bl 80058a0 80083b2: 4602 mov r2, r0 80083b4: 697b ldr r3, [r7, #20] 80083b6: 1ad3 subs r3, r2, r3 80083b8: f241 3288 movw r2, #5000 @ 0x1388 80083bc: 4293 cmp r3, r2 80083be: d901 bls.n 80083c4 { return HAL_TIMEOUT; 80083c0: 2303 movs r3, #3 80083c2: e0ae b.n 8008522 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80083c4: 4b59 ldr r3, [pc, #356] @ (800852c ) 80083c6: 6a1b ldr r3, [r3, #32] 80083c8: f003 0302 and.w r3, r3, #2 80083cc: 2b00 cmp r3, #0 80083ce: d0ee beq.n 80083ae } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80083d0: 4b56 ldr r3, [pc, #344] @ (800852c ) 80083d2: 6a1b ldr r3, [r3, #32] 80083d4: f423 7240 bic.w r2, r3, #768 @ 0x300 80083d8: 687b ldr r3, [r7, #4] 80083da: 685b ldr r3, [r3, #4] 80083dc: 4953 ldr r1, [pc, #332] @ (800852c ) 80083de: 4313 orrs r3, r2 80083e0: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 80083e2: 7efb ldrb r3, [r7, #27] 80083e4: 2b01 cmp r3, #1 80083e6: d105 bne.n 80083f4 { __HAL_RCC_PWR_CLK_DISABLE(); 80083e8: 4b50 ldr r3, [pc, #320] @ (800852c ) 80083ea: 69db ldr r3, [r3, #28] 80083ec: 4a4f ldr r2, [pc, #316] @ (800852c ) 80083ee: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80083f2: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 80083f4: 687b ldr r3, [r7, #4] 80083f6: 681b ldr r3, [r3, #0] 80083f8: f003 0302 and.w r3, r3, #2 80083fc: 2b00 cmp r3, #0 80083fe: d008 beq.n 8008412 { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8008400: 4b4a ldr r3, [pc, #296] @ (800852c ) 8008402: 685b ldr r3, [r3, #4] 8008404: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8008408: 687b ldr r3, [r7, #4] 800840a: 689b ldr r3, [r3, #8] 800840c: 4947 ldr r1, [pc, #284] @ (800852c ) 800840e: 4313 orrs r3, r2 8008410: 604b str r3, [r1, #4] } #if defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ I2S2 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) 8008412: 687b ldr r3, [r7, #4] 8008414: 681b ldr r3, [r3, #0] 8008416: f003 0304 and.w r3, r3, #4 800841a: 2b00 cmp r3, #0 800841c: d008 beq.n 8008430 { /* Check the parameters */ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); /* Configure the I2S2 clock source */ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); 800841e: 4b43 ldr r3, [pc, #268] @ (800852c ) 8008420: 6adb ldr r3, [r3, #44] @ 0x2c 8008422: f423 3200 bic.w r2, r3, #131072 @ 0x20000 8008426: 687b ldr r3, [r7, #4] 8008428: 68db ldr r3, [r3, #12] 800842a: 4940 ldr r1, [pc, #256] @ (800852c ) 800842c: 4313 orrs r3, r2 800842e: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ I2S3 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) 8008430: 687b ldr r3, [r7, #4] 8008432: 681b ldr r3, [r3, #0] 8008434: f003 0308 and.w r3, r3, #8 8008438: 2b00 cmp r3, #0 800843a: d008 beq.n 800844e { /* Check the parameters */ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); /* Configure the I2S3 clock source */ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); 800843c: 4b3b ldr r3, [pc, #236] @ (800852c ) 800843e: 6adb ldr r3, [r3, #44] @ 0x2c 8008440: f423 2280 bic.w r2, r3, #262144 @ 0x40000 8008444: 687b ldr r3, [r7, #4] 8008446: 691b ldr r3, [r3, #16] 8008448: 4938 ldr r1, [pc, #224] @ (800852c ) 800844a: 4313 orrs r3, r2 800844c: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ PLL I2S Configuration ----------------------*/ /* Check that PLLI2S need to be enabled */ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) 800844e: 4b37 ldr r3, [pc, #220] @ (800852c ) 8008450: 6adb ldr r3, [r3, #44] @ 0x2c 8008452: f403 3300 and.w r3, r3, #131072 @ 0x20000 8008456: 2b00 cmp r3, #0 8008458: d105 bne.n 8008466 800845a: 4b34 ldr r3, [pc, #208] @ (800852c ) 800845c: 6adb ldr r3, [r3, #44] @ 0x2c 800845e: f403 2380 and.w r3, r3, #262144 @ 0x40000 8008462: 2b00 cmp r3, #0 8008464: d001 beq.n 800846a { /* Update flag to indicate that PLL I2S should be active */ pllactive = 1; 8008466: 2301 movs r3, #1 8008468: 61fb str r3, [r7, #28] } /* Check if PLL I2S need to be enabled */ if (pllactive == 1) 800846a: 69fb ldr r3, [r7, #28] 800846c: 2b01 cmp r3, #1 800846e: d148 bne.n 8008502 { /* Enable PLL I2S only if not active */ if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) 8008470: 4b2e ldr r3, [pc, #184] @ (800852c ) 8008472: 681b ldr r3, [r3, #0] 8008474: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8008478: 2b00 cmp r3, #0 800847a: d138 bne.n 80084ee assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); /* Prediv2 can be written only when the PLL2 is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 800847c: 4b2b ldr r3, [pc, #172] @ (800852c ) 800847e: 681b ldr r3, [r3, #0] 8008480: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8008484: 2b00 cmp r3, #0 8008486: d009 beq.n 800849c (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) 8008488: 4b28 ldr r3, [pc, #160] @ (800852c ) 800848a: 6adb ldr r3, [r3, #44] @ 0x2c 800848c: f003 02f0 and.w r2, r3, #240 @ 0xf0 8008490: 687b ldr r3, [r7, #4] 8008492: 699b ldr r3, [r3, #24] if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 8008494: 429a cmp r2, r3 8008496: d001 beq.n 800849c { return HAL_ERROR; 8008498: 2301 movs r3, #1 800849a: e042 b.n 8008522 } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); 800849c: 4b23 ldr r3, [pc, #140] @ (800852c ) 800849e: 6adb ldr r3, [r3, #44] @ 0x2c 80084a0: f023 02f0 bic.w r2, r3, #240 @ 0xf0 80084a4: 687b ldr r3, [r7, #4] 80084a6: 699b ldr r3, [r3, #24] 80084a8: 4920 ldr r1, [pc, #128] @ (800852c ) 80084aa: 4313 orrs r3, r2 80084ac: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); 80084ae: 4b1f ldr r3, [pc, #124] @ (800852c ) 80084b0: 6adb ldr r3, [r3, #44] @ 0x2c 80084b2: f423 4270 bic.w r2, r3, #61440 @ 0xf000 80084b6: 687b ldr r3, [r7, #4] 80084b8: 695b ldr r3, [r3, #20] 80084ba: 491c ldr r1, [pc, #112] @ (800852c ) 80084bc: 4313 orrs r3, r2 80084be: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); 80084c0: 4b1d ldr r3, [pc, #116] @ (8008538 ) 80084c2: 2201 movs r2, #1 80084c4: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80084c6: f7fd f9eb bl 80058a0 80084ca: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 80084cc: e008 b.n 80084e0 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 80084ce: f7fd f9e7 bl 80058a0 80084d2: 4602 mov r2, r0 80084d4: 697b ldr r3, [r7, #20] 80084d6: 1ad3 subs r3, r2, r3 80084d8: 2b64 cmp r3, #100 @ 0x64 80084da: d901 bls.n 80084e0 { return HAL_TIMEOUT; 80084dc: 2303 movs r3, #3 80084de: e020 b.n 8008522 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 80084e0: 4b12 ldr r3, [pc, #72] @ (800852c ) 80084e2: 681b ldr r3, [r3, #0] 80084e4: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80084e8: 2b00 cmp r3, #0 80084ea: d0f0 beq.n 80084ce 80084ec: e009 b.n 8008502 } } else { /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) 80084ee: 4b0f ldr r3, [pc, #60] @ (800852c ) 80084f0: 6adb ldr r3, [r3, #44] @ 0x2c 80084f2: f403 4270 and.w r2, r3, #61440 @ 0xf000 80084f6: 687b ldr r3, [r7, #4] 80084f8: 695b ldr r3, [r3, #20] 80084fa: 429a cmp r2, r3 80084fc: d001 beq.n 8008502 { return HAL_ERROR; 80084fe: 2301 movs r3, #1 8008500: e00f b.n 8008522 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8008502: 687b ldr r3, [r7, #4] 8008504: 681b ldr r3, [r3, #0] 8008506: f003 0310 and.w r3, r3, #16 800850a: 2b00 cmp r3, #0 800850c: d008 beq.n 8008520 { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 800850e: 4b07 ldr r3, [pc, #28] @ (800852c ) 8008510: 685b ldr r3, [r3, #4] 8008512: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 8008516: 687b ldr r3, [r7, #4] 8008518: 69db ldr r3, [r3, #28] 800851a: 4904 ldr r1, [pc, #16] @ (800852c ) 800851c: 4313 orrs r3, r2 800851e: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 8008520: 2300 movs r3, #0 } 8008522: 4618 mov r0, r3 8008524: 3720 adds r7, #32 8008526: 46bd mov sp, r7 8008528: bd80 pop {r7, pc} 800852a: bf00 nop 800852c: 40021000 .word 0x40021000 8008530: 40007000 .word 0x40007000 8008534: 42420440 .word 0x42420440 8008538: 42420070 .word 0x42420070 0800853c : * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 800853c: b590 push {r4, r7, lr} 800853e: b093 sub sp, #76 @ 0x4c 8008540: af00 add r7, sp, #0 8008542: 6078 str r0, [r7, #4] #if defined(STM32F105xC) || defined(STM32F107xC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; 8008544: 4ba7 ldr r3, [pc, #668] @ (80087e4 ) 8008546: f107 0418 add.w r4, r7, #24 800854a: cb0f ldmia r3, {r0, r1, r2, r3} 800854c: c407 stmia r4!, {r0, r1, r2} 800854e: 8023 strh r3, [r4, #0] const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; 8008550: 4ba5 ldr r3, [pc, #660] @ (80087e8 ) 8008552: f107 0408 add.w r4, r7, #8 8008556: cb0f ldmia r3, {r0, r1, r2, r3} 8008558: e884 000f stmia.w r4, {r0, r1, r2, r3} uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; 800855c: 2300 movs r3, #0 800855e: 63fb str r3, [r7, #60] @ 0x3c 8008560: 2300 movs r3, #0 8008562: 647b str r3, [r7, #68] @ 0x44 8008564: 2300 movs r3, #0 8008566: 63bb str r3, [r7, #56] @ 0x38 uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; 8008568: 2300 movs r3, #0 800856a: 637b str r3, [r7, #52] @ 0x34 800856c: 2300 movs r3, #0 800856e: 633b str r3, [r7, #48] @ 0x30 8008570: 2300 movs r3, #0 8008572: 62fb str r3, [r7, #44] @ 0x2c const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; const uint8_t aPredivFactorTable[2] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 8008574: 2300 movs r3, #0 8008576: 62bb str r3, [r7, #40] @ 0x28 8008578: 2300 movs r3, #0 800857a: 643b str r3, [r7, #64] @ 0x40 /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 800857c: 687b ldr r3, [r7, #4] 800857e: 3b01 subs r3, #1 8008580: 2b0f cmp r3, #15 8008582: f200 8121 bhi.w 80087c8 8008586: a201 add r2, pc, #4 @ (adr r2, 800858c ) 8008588: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800858c: 08008749 .word 0x08008749 8008590: 080087ad .word 0x080087ad 8008594: 080087c9 .word 0x080087c9 8008598: 080086a7 .word 0x080086a7 800859c: 080087c9 .word 0x080087c9 80085a0: 080087c9 .word 0x080087c9 80085a4: 080087c9 .word 0x080087c9 80085a8: 080086f9 .word 0x080086f9 80085ac: 080087c9 .word 0x080087c9 80085b0: 080087c9 .word 0x080087c9 80085b4: 080087c9 .word 0x080087c9 80085b8: 080087c9 .word 0x080087c9 80085bc: 080087c9 .word 0x080087c9 80085c0: 080087c9 .word 0x080087c9 80085c4: 080087c9 .word 0x080087c9 80085c8: 080085cd .word 0x080085cd || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_USB: { /* Get RCC configuration ------------------------------------------------------*/ temp_reg = RCC->CFGR; 80085cc: 4b87 ldr r3, [pc, #540] @ (80087ec ) 80085ce: 685b ldr r3, [r3, #4] 80085d0: 62bb str r3, [r7, #40] @ 0x28 /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) 80085d2: 4b86 ldr r3, [pc, #536] @ (80087ec ) 80085d4: 681b ldr r3, [r3, #0] 80085d6: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80085da: 2b00 cmp r3, #0 80085dc: f000 80f6 beq.w 80087cc { pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 80085e0: 6abb ldr r3, [r7, #40] @ 0x28 80085e2: 0c9b lsrs r3, r3, #18 80085e4: f003 030f and.w r3, r3, #15 80085e8: 3348 adds r3, #72 @ 0x48 80085ea: 443b add r3, r7 80085ec: f813 3c30 ldrb.w r3, [r3, #-48] 80085f0: 63bb str r3, [r7, #56] @ 0x38 if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 80085f2: 6abb ldr r3, [r7, #40] @ 0x28 80085f4: f403 3380 and.w r3, r3, #65536 @ 0x10000 80085f8: 2b00 cmp r3, #0 80085fa: d03d beq.n 8008678 { #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ || defined(STM32F100xE) prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 80085fc: 4b7b ldr r3, [pc, #492] @ (80087ec ) 80085fe: 6adb ldr r3, [r3, #44] @ 0x2c 8008600: f003 030f and.w r3, r3, #15 8008604: 3348 adds r3, #72 @ 0x48 8008606: 443b add r3, r7 8008608: f813 3c40 ldrb.w r3, [r3, #-64] 800860c: 63fb str r3, [r7, #60] @ 0x3c #else prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 800860e: 4b77 ldr r3, [pc, #476] @ (80087ec ) 8008610: 6adb ldr r3, [r3, #44] @ 0x2c 8008612: f403 3380 and.w r3, r3, #65536 @ 0x10000 8008616: 2b00 cmp r3, #0 8008618: d01c beq.n 8008654 { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 800861a: 4b74 ldr r3, [pc, #464] @ (80087ec ) 800861c: 6adb ldr r3, [r3, #44] @ 0x2c 800861e: 091b lsrs r3, r3, #4 8008620: f003 030f and.w r3, r3, #15 8008624: 3301 adds r3, #1 8008626: 62fb str r3, [r7, #44] @ 0x2c pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 8008628: 4b70 ldr r3, [pc, #448] @ (80087ec ) 800862a: 6adb ldr r3, [r3, #44] @ 0x2c 800862c: 0a1b lsrs r3, r3, #8 800862e: f003 030f and.w r3, r3, #15 8008632: 3302 adds r3, #2 8008634: 637b str r3, [r7, #52] @ 0x34 pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); 8008636: 4a6e ldr r2, [pc, #440] @ (80087f0 ) 8008638: 6afb ldr r3, [r7, #44] @ 0x2c 800863a: fbb2 f3f3 udiv r3, r2, r3 800863e: 6b7a ldr r2, [r7, #52] @ 0x34 8008640: fb03 f202 mul.w r2, r3, r2 8008644: 6bfb ldr r3, [r7, #60] @ 0x3c 8008646: fbb2 f2f3 udiv r2, r2, r3 800864a: 6bbb ldr r3, [r7, #56] @ 0x38 800864c: fb02 f303 mul.w r3, r2, r3 8008650: 647b str r3, [r7, #68] @ 0x44 8008652: e007 b.n 8008664 } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); 8008654: 4a66 ldr r2, [pc, #408] @ (80087f0 ) 8008656: 6bfb ldr r3, [r7, #60] @ 0x3c 8008658: fbb2 f2f3 udiv r2, r2, r3 800865c: 6bbb ldr r3, [r7, #56] @ 0x38 800865e: fb02 f303 mul.w r3, r2, r3 8008662: 647b str r3, [r7, #68] @ 0x44 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 8008664: f897 3025 ldrb.w r3, [r7, #37] @ 0x25 8008668: 461a mov r2, r3 800866a: 6bbb ldr r3, [r7, #56] @ 0x38 800866c: 4293 cmp r3, r2 800866e: d108 bne.n 8008682 { pllclk = pllclk / 2; 8008670: 6c7b ldr r3, [r7, #68] @ 0x44 8008672: 085b lsrs r3, r3, #1 8008674: 647b str r3, [r7, #68] @ 0x44 8008676: e004 b.n 8008682 #endif /* STM32F105xC || STM32F107xC */ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8008678: 6bbb ldr r3, [r7, #56] @ 0x38 800867a: 4a5e ldr r2, [pc, #376] @ (80087f4 ) 800867c: fb02 f303 mul.w r3, r2, r3 8008680: 647b str r3, [r7, #68] @ 0x44 } /* Calcul of the USB frequency*/ #if defined(STM32F105xC) || defined(STM32F107xC) /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) 8008682: 4b5a ldr r3, [pc, #360] @ (80087ec ) 8008684: 685b ldr r3, [r3, #4] 8008686: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800868a: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800868e: d102 bne.n 8008696 { /* Prescaler of 2 selected for USB */ frequency = pllclk; 8008690: 6c7b ldr r3, [r7, #68] @ 0x44 8008692: 643b str r3, [r7, #64] @ 0x40 /* Prescaler of 1.5 selected for USB */ frequency = (pllclk * 2) / 3; } #endif } break; 8008694: e09a b.n 80087cc frequency = (2 * pllclk) / 3; 8008696: 6c7b ldr r3, [r7, #68] @ 0x44 8008698: 005b lsls r3, r3, #1 800869a: 4a57 ldr r2, [pc, #348] @ (80087f8 ) 800869c: fba2 2303 umull r2, r3, r2, r3 80086a0: 085b lsrs r3, r3, #1 80086a2: 643b str r3, [r7, #64] @ 0x40 break; 80086a4: e092 b.n 80087cc { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) 80086a6: 4b51 ldr r3, [pc, #324] @ (80087ec ) 80086a8: 6adb ldr r3, [r3, #44] @ 0x2c 80086aa: f403 3300 and.w r3, r3, #131072 @ 0x20000 80086ae: 2b00 cmp r3, #0 80086b0: d103 bne.n 80086ba { /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); 80086b2: f7ff fce3 bl 800807c 80086b6: 6438 str r0, [r7, #64] @ 0x40 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 80086b8: e08a b.n 80087d0 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 80086ba: 4b4c ldr r3, [pc, #304] @ (80087ec ) 80086bc: 681b ldr r3, [r3, #0] 80086be: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80086c2: 2b00 cmp r3, #0 80086c4: f000 8084 beq.w 80087d0 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 80086c8: 4b48 ldr r3, [pc, #288] @ (80087ec ) 80086ca: 6adb ldr r3, [r3, #44] @ 0x2c 80086cc: 091b lsrs r3, r3, #4 80086ce: f003 030f and.w r3, r3, #15 80086d2: 3301 adds r3, #1 80086d4: 62fb str r3, [r7, #44] @ 0x2c pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 80086d6: 4b45 ldr r3, [pc, #276] @ (80087ec ) 80086d8: 6adb ldr r3, [r3, #44] @ 0x2c 80086da: 0b1b lsrs r3, r3, #12 80086dc: f003 030f and.w r3, r3, #15 80086e0: 3302 adds r3, #2 80086e2: 633b str r3, [r7, #48] @ 0x30 frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 80086e4: 4a42 ldr r2, [pc, #264] @ (80087f0 ) 80086e6: 6afb ldr r3, [r7, #44] @ 0x2c 80086e8: fbb2 f3f3 udiv r3, r2, r3 80086ec: 6b3a ldr r2, [r7, #48] @ 0x30 80086ee: fb02 f303 mul.w r3, r2, r3 80086f2: 005b lsls r3, r3, #1 80086f4: 643b str r3, [r7, #64] @ 0x40 break; 80086f6: e06b b.n 80087d0 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) 80086f8: 4b3c ldr r3, [pc, #240] @ (80087ec ) 80086fa: 6adb ldr r3, [r3, #44] @ 0x2c 80086fc: f403 2380 and.w r3, r3, #262144 @ 0x40000 8008700: 2b00 cmp r3, #0 8008702: d103 bne.n 800870c { /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); 8008704: f7ff fcba bl 800807c 8008708: 6438 str r0, [r7, #64] @ 0x40 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 800870a: e063 b.n 80087d4 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 800870c: 4b37 ldr r3, [pc, #220] @ (80087ec ) 800870e: 681b ldr r3, [r3, #0] 8008710: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8008714: 2b00 cmp r3, #0 8008716: d05d beq.n 80087d4 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8008718: 4b34 ldr r3, [pc, #208] @ (80087ec ) 800871a: 6adb ldr r3, [r3, #44] @ 0x2c 800871c: 091b lsrs r3, r3, #4 800871e: f003 030f and.w r3, r3, #15 8008722: 3301 adds r3, #1 8008724: 62fb str r3, [r7, #44] @ 0x2c pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 8008726: 4b31 ldr r3, [pc, #196] @ (80087ec ) 8008728: 6adb ldr r3, [r3, #44] @ 0x2c 800872a: 0b1b lsrs r3, r3, #12 800872c: f003 030f and.w r3, r3, #15 8008730: 3302 adds r3, #2 8008732: 633b str r3, [r7, #48] @ 0x30 frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8008734: 4a2e ldr r2, [pc, #184] @ (80087f0 ) 8008736: 6afb ldr r3, [r7, #44] @ 0x2c 8008738: fbb2 f3f3 udiv r3, r2, r3 800873c: 6b3a ldr r2, [r7, #48] @ 0x30 800873e: fb02 f303 mul.w r3, r2, r3 8008742: 005b lsls r3, r3, #1 8008744: 643b str r3, [r7, #64] @ 0x40 break; 8008746: e045 b.n 80087d4 } #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ case RCC_PERIPHCLK_RTC: { /* Get RCC BDCR configuration ------------------------------------------------------*/ temp_reg = RCC->BDCR; 8008748: 4b28 ldr r3, [pc, #160] @ (80087ec ) 800874a: 6a1b ldr r3, [r3, #32] 800874c: 62bb str r3, [r7, #40] @ 0x28 /* Check if LSE is ready if RTC clock selection is LSE */ if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 800874e: 6abb ldr r3, [r7, #40] @ 0x28 8008750: f403 7340 and.w r3, r3, #768 @ 0x300 8008754: f5b3 7f80 cmp.w r3, #256 @ 0x100 8008758: d108 bne.n 800876c 800875a: 6abb ldr r3, [r7, #40] @ 0x28 800875c: f003 0302 and.w r3, r3, #2 8008760: 2b00 cmp r3, #0 8008762: d003 beq.n 800876c { frequency = LSE_VALUE; 8008764: f44f 4300 mov.w r3, #32768 @ 0x8000 8008768: 643b str r3, [r7, #64] @ 0x40 800876a: e01e b.n 80087aa } /* Check if LSI is ready if RTC clock selection is LSI */ else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 800876c: 6abb ldr r3, [r7, #40] @ 0x28 800876e: f403 7340 and.w r3, r3, #768 @ 0x300 8008772: f5b3 7f00 cmp.w r3, #512 @ 0x200 8008776: d109 bne.n 800878c 8008778: 4b1c ldr r3, [pc, #112] @ (80087ec ) 800877a: 6a5b ldr r3, [r3, #36] @ 0x24 800877c: f003 0302 and.w r3, r3, #2 8008780: 2b00 cmp r3, #0 8008782: d003 beq.n 800878c { frequency = LSI_VALUE; 8008784: f649 4340 movw r3, #40000 @ 0x9c40 8008788: 643b str r3, [r7, #64] @ 0x40 800878a: e00e b.n 80087aa } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 800878c: 6abb ldr r3, [r7, #40] @ 0x28 800878e: f403 7340 and.w r3, r3, #768 @ 0x300 8008792: f5b3 7f40 cmp.w r3, #768 @ 0x300 8008796: d11f bne.n 80087d8 8008798: 4b14 ldr r3, [pc, #80] @ (80087ec ) 800879a: 681b ldr r3, [r3, #0] 800879c: f403 3300 and.w r3, r3, #131072 @ 0x20000 80087a0: 2b00 cmp r3, #0 80087a2: d019 beq.n 80087d8 { frequency = HSE_VALUE / 128U; 80087a4: 4b15 ldr r3, [pc, #84] @ (80087fc ) 80087a6: 643b str r3, [r7, #64] @ 0x40 /* Clock not enabled for RTC*/ else { /* nothing to do: frequency already initialized to 0U */ } break; 80087a8: e016 b.n 80087d8 80087aa: e015 b.n 80087d8 } case RCC_PERIPHCLK_ADC: { frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 80087ac: f7ff fd62 bl 8008274 80087b0: 4602 mov r2, r0 80087b2: 4b0e ldr r3, [pc, #56] @ (80087ec ) 80087b4: 685b ldr r3, [r3, #4] 80087b6: 0b9b lsrs r3, r3, #14 80087b8: f003 0303 and.w r3, r3, #3 80087bc: 3301 adds r3, #1 80087be: 005b lsls r3, r3, #1 80087c0: fbb2 f3f3 udiv r3, r2, r3 80087c4: 643b str r3, [r7, #64] @ 0x40 break; 80087c6: e008 b.n 80087da } default: { break; 80087c8: bf00 nop 80087ca: e006 b.n 80087da break; 80087cc: bf00 nop 80087ce: e004 b.n 80087da break; 80087d0: bf00 nop 80087d2: e002 b.n 80087da break; 80087d4: bf00 nop 80087d6: e000 b.n 80087da break; 80087d8: bf00 nop } } return (frequency); 80087da: 6c3b ldr r3, [r7, #64] @ 0x40 } 80087dc: 4618 mov r0, r3 80087de: 374c adds r7, #76 @ 0x4c 80087e0: 46bd mov sp, r7 80087e2: bd90 pop {r4, r7, pc} 80087e4: 0800df70 .word 0x0800df70 80087e8: 0800df80 .word 0x0800df80 80087ec: 40021000 .word 0x40021000 80087f0: 017d7840 .word 0x017d7840 80087f4: 003d0900 .word 0x003d0900 80087f8: aaaaaaab .word 0xaaaaaaab 80087fc: 0002faf0 .word 0x0002faf0 08008800 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { 8008800: b580 push {r7, lr} 8008802: b084 sub sp, #16 8008804: af00 add r7, sp, #0 8008806: 6078 str r0, [r7, #4] uint32_t prescaler = 0U; 8008808: 2300 movs r3, #0 800880a: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 800880c: 687b ldr r3, [r7, #4] 800880e: 2b00 cmp r3, #0 8008810: d101 bne.n 8008816 { return HAL_ERROR; 8008812: 2301 movs r3, #1 8008814: e084 b.n 8008920 { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else if (hrtc->State == HAL_RTC_STATE_RESET) 8008816: 687b ldr r3, [r7, #4] 8008818: 7c5b ldrb r3, [r3, #17] 800881a: b2db uxtb r3, r3 800881c: 2b00 cmp r3, #0 800881e: d105 bne.n 800882c { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; 8008820: 687b ldr r3, [r7, #4] 8008822: 2200 movs r2, #0 8008824: 741a strb r2, [r3, #16] /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); 8008826: 6878 ldr r0, [r7, #4] 8008828: f7fc fc30 bl 800508c } #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; 800882c: 687b ldr r3, [r7, #4] 800882e: 2202 movs r2, #2 8008830: 745a strb r2, [r3, #17] /* Waiting for synchro */ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 8008832: 6878 ldr r0, [r7, #4] 8008834: f000 f87a bl 800892c 8008838: 4603 mov r3, r0 800883a: 2b00 cmp r3, #0 800883c: d004 beq.n 8008848 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 800883e: 687b ldr r3, [r7, #4] 8008840: 2204 movs r2, #4 8008842: 745a strb r2, [r3, #17] return HAL_ERROR; 8008844: 2301 movs r3, #1 8008846: e06b b.n 8008920 } /* Set Initialization mode */ if (RTC_EnterInitMode(hrtc) != HAL_OK) 8008848: 6878 ldr r0, [r7, #4] 800884a: f000 f89c bl 8008986 800884e: 4603 mov r3, r0 8008850: 2b00 cmp r3, #0 8008852: d004 beq.n 800885e { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8008854: 687b ldr r3, [r7, #4] 8008856: 2204 movs r2, #4 8008858: 745a strb r2, [r3, #17] return HAL_ERROR; 800885a: 2301 movs r3, #1 800885c: e060 b.n 8008920 } else { /* Clear Flags Bits */ CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); 800885e: 687b ldr r3, [r7, #4] 8008860: 681b ldr r3, [r3, #0] 8008862: 685a ldr r2, [r3, #4] 8008864: 687b ldr r3, [r7, #4] 8008866: 681b ldr r3, [r3, #0] 8008868: f022 0207 bic.w r2, r2, #7 800886c: 605a str r2, [r3, #4] if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) 800886e: 687b ldr r3, [r7, #4] 8008870: 689b ldr r3, [r3, #8] 8008872: 2b00 cmp r3, #0 8008874: d005 beq.n 8008882 { /* Disable the selected Tamper pin */ CLEAR_BIT(BKP->CR, BKP_CR_TPE); 8008876: 4b2c ldr r3, [pc, #176] @ (8008928 ) 8008878: 6b1b ldr r3, [r3, #48] @ 0x30 800887a: 4a2b ldr r2, [pc, #172] @ (8008928 ) 800887c: f023 0301 bic.w r3, r3, #1 8008880: 6313 str r3, [r2, #48] @ 0x30 } /* Set the signal which will be routed to RTC Tamper pin*/ MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); 8008882: 4b29 ldr r3, [pc, #164] @ (8008928 ) 8008884: 6adb ldr r3, [r3, #44] @ 0x2c 8008886: f423 7260 bic.w r2, r3, #896 @ 0x380 800888a: 687b ldr r3, [r7, #4] 800888c: 689b ldr r3, [r3, #8] 800888e: 4926 ldr r1, [pc, #152] @ (8008928 ) 8008890: 4313 orrs r3, r2 8008892: 62cb str r3, [r1, #44] @ 0x2c if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) 8008894: 687b ldr r3, [r7, #4] 8008896: 685b ldr r3, [r3, #4] 8008898: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800889c: d003 beq.n 80088a6 { /* RTC Prescaler provided directly by end-user*/ prescaler = hrtc->Init.AsynchPrediv; 800889e: 687b ldr r3, [r7, #4] 80088a0: 685b ldr r3, [r3, #4] 80088a2: 60fb str r3, [r7, #12] 80088a4: e00e b.n 80088c4 } else { /* RTC Prescaler will be automatically calculated to get 1 second timebase */ /* Get the RTCCLK frequency */ prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); 80088a6: 2001 movs r0, #1 80088a8: f7ff fe48 bl 800853c 80088ac: 60f8 str r0, [r7, #12] /* Check that RTC clock is enabled*/ if (prescaler == 0U) 80088ae: 68fb ldr r3, [r7, #12] 80088b0: 2b00 cmp r3, #0 80088b2: d104 bne.n 80088be { /* Should not happen. Frequency is not available*/ hrtc->State = HAL_RTC_STATE_ERROR; 80088b4: 687b ldr r3, [r7, #4] 80088b6: 2204 movs r2, #4 80088b8: 745a strb r2, [r3, #17] return HAL_ERROR; 80088ba: 2301 movs r3, #1 80088bc: e030 b.n 8008920 } else { /* RTC period = RTCCLK/(RTC_PR + 1) */ prescaler = prescaler - 1U; 80088be: 68fb ldr r3, [r7, #12] 80088c0: 3b01 subs r3, #1 80088c2: 60fb str r3, [r7, #12] } } /* Configure the RTC_PRLH / RTC_PRLL */ MODIFY_REG(hrtc->Instance->PRLH, RTC_PRLH_PRL, (prescaler >> 16U)); 80088c4: 687b ldr r3, [r7, #4] 80088c6: 681b ldr r3, [r3, #0] 80088c8: 689b ldr r3, [r3, #8] 80088ca: f023 010f bic.w r1, r3, #15 80088ce: 68fb ldr r3, [r7, #12] 80088d0: 0c1a lsrs r2, r3, #16 80088d2: 687b ldr r3, [r7, #4] 80088d4: 681b ldr r3, [r3, #0] 80088d6: 430a orrs r2, r1 80088d8: 609a str r2, [r3, #8] MODIFY_REG(hrtc->Instance->PRLL, RTC_PRLL_PRL, (prescaler & RTC_PRLL_PRL)); 80088da: 687b ldr r3, [r7, #4] 80088dc: 681b ldr r3, [r3, #0] 80088de: 68db ldr r3, [r3, #12] 80088e0: 0c1b lsrs r3, r3, #16 80088e2: 041b lsls r3, r3, #16 80088e4: 68fa ldr r2, [r7, #12] 80088e6: b291 uxth r1, r2 80088e8: 687a ldr r2, [r7, #4] 80088ea: 6812 ldr r2, [r2, #0] 80088ec: 430b orrs r3, r1 80088ee: 60d3 str r3, [r2, #12] /* Wait for synchro */ if (RTC_ExitInitMode(hrtc) != HAL_OK) 80088f0: 6878 ldr r0, [r7, #4] 80088f2: f000 f870 bl 80089d6 80088f6: 4603 mov r3, r0 80088f8: 2b00 cmp r3, #0 80088fa: d004 beq.n 8008906 { hrtc->State = HAL_RTC_STATE_ERROR; 80088fc: 687b ldr r3, [r7, #4] 80088fe: 2204 movs r2, #4 8008900: 745a strb r2, [r3, #17] return HAL_ERROR; 8008902: 2301 movs r3, #1 8008904: e00c b.n 8008920 } /* Initialize date to 1st of January 2000 */ hrtc->DateToUpdate.Year = 0x00U; 8008906: 687b ldr r3, [r7, #4] 8008908: 2200 movs r2, #0 800890a: 73da strb r2, [r3, #15] hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; 800890c: 687b ldr r3, [r7, #4] 800890e: 2201 movs r2, #1 8008910: 735a strb r2, [r3, #13] hrtc->DateToUpdate.Date = 0x01U; 8008912: 687b ldr r3, [r7, #4] 8008914: 2201 movs r2, #1 8008916: 739a strb r2, [r3, #14] /* Set RTC state */ hrtc->State = HAL_RTC_STATE_READY; 8008918: 687b ldr r3, [r7, #4] 800891a: 2201 movs r2, #1 800891c: 745a strb r2, [r3, #17] return HAL_OK; 800891e: 2300 movs r3, #0 } } 8008920: 4618 mov r0, r3 8008922: 3710 adds r7, #16 8008924: 46bd mov sp, r7 8008926: bd80 pop {r7, pc} 8008928: 40006c00 .word 0x40006c00 0800892c : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { 800892c: b580 push {r7, lr} 800892e: b084 sub sp, #16 8008930: af00 add r7, sp, #0 8008932: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8008934: 2300 movs r3, #0 8008936: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8008938: 687b ldr r3, [r7, #4] 800893a: 2b00 cmp r3, #0 800893c: d101 bne.n 8008942 { return HAL_ERROR; 800893e: 2301 movs r3, #1 8008940: e01d b.n 800897e } /* Clear RSF flag */ CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); 8008942: 687b ldr r3, [r7, #4] 8008944: 681b ldr r3, [r3, #0] 8008946: 685a ldr r2, [r3, #4] 8008948: 687b ldr r3, [r7, #4] 800894a: 681b ldr r3, [r3, #0] 800894c: f022 0208 bic.w r2, r2, #8 8008950: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8008952: f7fc ffa5 bl 80058a0 8008956: 60f8 str r0, [r7, #12] /* Wait the registers to be synchronised */ while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8008958: e009 b.n 800896e { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 800895a: f7fc ffa1 bl 80058a0 800895e: 4602 mov r2, r0 8008960: 68fb ldr r3, [r7, #12] 8008962: 1ad3 subs r3, r2, r3 8008964: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8008968: d901 bls.n 800896e { return HAL_TIMEOUT; 800896a: 2303 movs r3, #3 800896c: e007 b.n 800897e while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 800896e: 687b ldr r3, [r7, #4] 8008970: 681b ldr r3, [r3, #0] 8008972: 685b ldr r3, [r3, #4] 8008974: f003 0308 and.w r3, r3, #8 8008978: 2b00 cmp r3, #0 800897a: d0ee beq.n 800895a } } return HAL_OK; 800897c: 2300 movs r3, #0 } 800897e: 4618 mov r0, r3 8008980: 3710 adds r7, #16 8008982: 46bd mov sp, r7 8008984: bd80 pop {r7, pc} 08008986 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { 8008986: b580 push {r7, lr} 8008988: b084 sub sp, #16 800898a: af00 add r7, sp, #0 800898c: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800898e: 2300 movs r3, #0 8008990: 60fb str r3, [r7, #12] tickstart = HAL_GetTick(); 8008992: f7fc ff85 bl 80058a0 8008996: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8008998: e009 b.n 80089ae { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 800899a: f7fc ff81 bl 80058a0 800899e: 4602 mov r2, r0 80089a0: 68fb ldr r3, [r7, #12] 80089a2: 1ad3 subs r3, r2, r3 80089a4: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 80089a8: d901 bls.n 80089ae { return HAL_TIMEOUT; 80089aa: 2303 movs r3, #3 80089ac: e00f b.n 80089ce while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 80089ae: 687b ldr r3, [r7, #4] 80089b0: 681b ldr r3, [r3, #0] 80089b2: 685b ldr r3, [r3, #4] 80089b4: f003 0320 and.w r3, r3, #32 80089b8: 2b00 cmp r3, #0 80089ba: d0ee beq.n 800899a } } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 80089bc: 687b ldr r3, [r7, #4] 80089be: 681b ldr r3, [r3, #0] 80089c0: 685a ldr r2, [r3, #4] 80089c2: 687b ldr r3, [r7, #4] 80089c4: 681b ldr r3, [r3, #0] 80089c6: f042 0210 orr.w r2, r2, #16 80089ca: 605a str r2, [r3, #4] return HAL_OK; 80089cc: 2300 movs r3, #0 } 80089ce: 4618 mov r0, r3 80089d0: 3710 adds r7, #16 80089d2: 46bd mov sp, r7 80089d4: bd80 pop {r7, pc} 080089d6 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) { 80089d6: b580 push {r7, lr} 80089d8: b084 sub sp, #16 80089da: af00 add r7, sp, #0 80089dc: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80089de: 2300 movs r3, #0 80089e0: 60fb str r3, [r7, #12] /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 80089e2: 687b ldr r3, [r7, #4] 80089e4: 681b ldr r3, [r3, #0] 80089e6: 685a ldr r2, [r3, #4] 80089e8: 687b ldr r3, [r7, #4] 80089ea: 681b ldr r3, [r3, #0] 80089ec: f022 0210 bic.w r2, r2, #16 80089f0: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 80089f2: f7fc ff55 bl 80058a0 80089f6: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 80089f8: e009 b.n 8008a0e { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 80089fa: f7fc ff51 bl 80058a0 80089fe: 4602 mov r2, r0 8008a00: 68fb ldr r3, [r7, #12] 8008a02: 1ad3 subs r3, r2, r3 8008a04: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8008a08: d901 bls.n 8008a0e { return HAL_TIMEOUT; 8008a0a: 2303 movs r3, #3 8008a0c: e007 b.n 8008a1e while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8008a0e: 687b ldr r3, [r7, #4] 8008a10: 681b ldr r3, [r3, #0] 8008a12: 685b ldr r3, [r3, #4] 8008a14: f003 0320 and.w r3, r3, #32 8008a18: 2b00 cmp r3, #0 8008a1a: d0ee beq.n 80089fa } } return HAL_OK; 8008a1c: 2300 movs r3, #0 } 8008a1e: 4618 mov r0, r3 8008a20: 3710 adds r7, #16 8008a22: 46bd mov sp, r7 8008a24: bd80 pop {r7, pc} 08008a26 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8008a26: b580 push {r7, lr} 8008a28: b082 sub sp, #8 8008a2a: af00 add r7, sp, #0 8008a2c: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8008a2e: 687b ldr r3, [r7, #4] 8008a30: 2b00 cmp r3, #0 8008a32: d101 bne.n 8008a38 { return HAL_ERROR; 8008a34: 2301 movs r3, #1 8008a36: e03f b.n 8008ab8 assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 8008a38: 687b ldr r3, [r7, #4] 8008a3a: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8008a3e: b2db uxtb r3, r3 8008a40: 2b00 cmp r3, #0 8008a42: d106 bne.n 8008a52 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8008a44: 687b ldr r3, [r7, #4] 8008a46: 2200 movs r2, #0 8008a48: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8008a4c: 6878 ldr r0, [r7, #4] 8008a4e: f7fc fe47 bl 80056e0 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8008a52: 687b ldr r3, [r7, #4] 8008a54: 2224 movs r2, #36 @ 0x24 8008a56: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8008a5a: 687b ldr r3, [r7, #4] 8008a5c: 681b ldr r3, [r3, #0] 8008a5e: 68da ldr r2, [r3, #12] 8008a60: 687b ldr r3, [r7, #4] 8008a62: 681b ldr r3, [r3, #0] 8008a64: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8008a68: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8008a6a: 6878 ldr r0, [r7, #4] 8008a6c: f000 fca2 bl 80093b4 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8008a70: 687b ldr r3, [r7, #4] 8008a72: 681b ldr r3, [r3, #0] 8008a74: 691a ldr r2, [r3, #16] 8008a76: 687b ldr r3, [r7, #4] 8008a78: 681b ldr r3, [r3, #0] 8008a7a: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8008a7e: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8008a80: 687b ldr r3, [r7, #4] 8008a82: 681b ldr r3, [r3, #0] 8008a84: 695a ldr r2, [r3, #20] 8008a86: 687b ldr r3, [r7, #4] 8008a88: 681b ldr r3, [r3, #0] 8008a8a: f022 022a bic.w r2, r2, #42 @ 0x2a 8008a8e: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8008a90: 687b ldr r3, [r7, #4] 8008a92: 681b ldr r3, [r3, #0] 8008a94: 68da ldr r2, [r3, #12] 8008a96: 687b ldr r3, [r7, #4] 8008a98: 681b ldr r3, [r3, #0] 8008a9a: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8008a9e: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8008aa0: 687b ldr r3, [r7, #4] 8008aa2: 2200 movs r2, #0 8008aa4: 641a str r2, [r3, #64] @ 0x40 huart->gState = HAL_UART_STATE_READY; 8008aa6: 687b ldr r3, [r7, #4] 8008aa8: 2220 movs r2, #32 8008aaa: f883 203d strb.w r2, [r3, #61] @ 0x3d huart->RxState = HAL_UART_STATE_READY; 8008aae: 687b ldr r3, [r7, #4] 8008ab0: 2220 movs r2, #32 8008ab2: f883 203e strb.w r2, [r3, #62] @ 0x3e return HAL_OK; 8008ab6: 2300 movs r3, #0 } 8008ab8: 4618 mov r0, r3 8008aba: 3708 adds r7, #8 8008abc: 46bd mov sp, r7 8008abe: bd80 pop {r7, pc} 08008ac0 : * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8008ac0: b580 push {r7, lr} 8008ac2: b08a sub sp, #40 @ 0x28 8008ac4: af02 add r7, sp, #8 8008ac6: 60f8 str r0, [r7, #12] 8008ac8: 60b9 str r1, [r7, #8] 8008aca: 603b str r3, [r7, #0] 8008acc: 4613 mov r3, r2 8008ace: 80fb strh r3, [r7, #6] uint8_t *pdata8bits; uint16_t *pdata16bits; uint32_t tickstart = 0U; 8008ad0: 2300 movs r3, #0 8008ad2: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8008ad4: 68fb ldr r3, [r7, #12] 8008ad6: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8008ada: b2db uxtb r3, r3 8008adc: 2b20 cmp r3, #32 8008ade: d17c bne.n 8008bda { if ((pData == NULL) || (Size == 0U)) 8008ae0: 68bb ldr r3, [r7, #8] 8008ae2: 2b00 cmp r3, #0 8008ae4: d002 beq.n 8008aec 8008ae6: 88fb ldrh r3, [r7, #6] 8008ae8: 2b00 cmp r3, #0 8008aea: d101 bne.n 8008af0 { return HAL_ERROR; 8008aec: 2301 movs r3, #1 8008aee: e075 b.n 8008bdc } /* Process Locked */ __HAL_LOCK(huart); 8008af0: 68fb ldr r3, [r7, #12] 8008af2: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8008af6: 2b01 cmp r3, #1 8008af8: d101 bne.n 8008afe 8008afa: 2302 movs r3, #2 8008afc: e06e b.n 8008bdc 8008afe: 68fb ldr r3, [r7, #12] 8008b00: 2201 movs r2, #1 8008b02: f883 203c strb.w r2, [r3, #60] @ 0x3c huart->ErrorCode = HAL_UART_ERROR_NONE; 8008b06: 68fb ldr r3, [r7, #12] 8008b08: 2200 movs r2, #0 8008b0a: 641a str r2, [r3, #64] @ 0x40 huart->gState = HAL_UART_STATE_BUSY_TX; 8008b0c: 68fb ldr r3, [r7, #12] 8008b0e: 2221 movs r2, #33 @ 0x21 8008b10: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8008b14: f7fc fec4 bl 80058a0 8008b18: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 8008b1a: 68fb ldr r3, [r7, #12] 8008b1c: 88fa ldrh r2, [r7, #6] 8008b1e: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8008b20: 68fb ldr r3, [r7, #12] 8008b22: 88fa ldrh r2, [r7, #6] 8008b24: 84da strh r2, [r3, #38] @ 0x26 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8008b26: 68fb ldr r3, [r7, #12] 8008b28: 689b ldr r3, [r3, #8] 8008b2a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8008b2e: d108 bne.n 8008b42 8008b30: 68fb ldr r3, [r7, #12] 8008b32: 691b ldr r3, [r3, #16] 8008b34: 2b00 cmp r3, #0 8008b36: d104 bne.n 8008b42 { pdata8bits = NULL; 8008b38: 2300 movs r3, #0 8008b3a: 61fb str r3, [r7, #28] pdata16bits = (uint16_t *) pData; 8008b3c: 68bb ldr r3, [r7, #8] 8008b3e: 61bb str r3, [r7, #24] 8008b40: e003 b.n 8008b4a } else { pdata8bits = pData; 8008b42: 68bb ldr r3, [r7, #8] 8008b44: 61fb str r3, [r7, #28] pdata16bits = NULL; 8008b46: 2300 movs r3, #0 8008b48: 61bb str r3, [r7, #24] } /* Process Unlocked */ __HAL_UNLOCK(huart); 8008b4a: 68fb ldr r3, [r7, #12] 8008b4c: 2200 movs r2, #0 8008b4e: f883 203c strb.w r2, [r3, #60] @ 0x3c while (huart->TxXferCount > 0U) 8008b52: e02a b.n 8008baa { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8008b54: 683b ldr r3, [r7, #0] 8008b56: 9300 str r3, [sp, #0] 8008b58: 697b ldr r3, [r7, #20] 8008b5a: 2200 movs r2, #0 8008b5c: 2180 movs r1, #128 @ 0x80 8008b5e: 68f8 ldr r0, [r7, #12] 8008b60: f000 fa55 bl 800900e 8008b64: 4603 mov r3, r0 8008b66: 2b00 cmp r3, #0 8008b68: d001 beq.n 8008b6e { return HAL_TIMEOUT; 8008b6a: 2303 movs r3, #3 8008b6c: e036 b.n 8008bdc } if (pdata8bits == NULL) 8008b6e: 69fb ldr r3, [r7, #28] 8008b70: 2b00 cmp r3, #0 8008b72: d10b bne.n 8008b8c { huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); 8008b74: 69bb ldr r3, [r7, #24] 8008b76: 881b ldrh r3, [r3, #0] 8008b78: 461a mov r2, r3 8008b7a: 68fb ldr r3, [r7, #12] 8008b7c: 681b ldr r3, [r3, #0] 8008b7e: f3c2 0208 ubfx r2, r2, #0, #9 8008b82: 605a str r2, [r3, #4] pdata16bits++; 8008b84: 69bb ldr r3, [r7, #24] 8008b86: 3302 adds r3, #2 8008b88: 61bb str r3, [r7, #24] 8008b8a: e007 b.n 8008b9c } else { huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); 8008b8c: 69fb ldr r3, [r7, #28] 8008b8e: 781a ldrb r2, [r3, #0] 8008b90: 68fb ldr r3, [r7, #12] 8008b92: 681b ldr r3, [r3, #0] 8008b94: 605a str r2, [r3, #4] pdata8bits++; 8008b96: 69fb ldr r3, [r7, #28] 8008b98: 3301 adds r3, #1 8008b9a: 61fb str r3, [r7, #28] } huart->TxXferCount--; 8008b9c: 68fb ldr r3, [r7, #12] 8008b9e: 8cdb ldrh r3, [r3, #38] @ 0x26 8008ba0: b29b uxth r3, r3 8008ba2: 3b01 subs r3, #1 8008ba4: b29a uxth r2, r3 8008ba6: 68fb ldr r3, [r7, #12] 8008ba8: 84da strh r2, [r3, #38] @ 0x26 while (huart->TxXferCount > 0U) 8008baa: 68fb ldr r3, [r7, #12] 8008bac: 8cdb ldrh r3, [r3, #38] @ 0x26 8008bae: b29b uxth r3, r3 8008bb0: 2b00 cmp r3, #0 8008bb2: d1cf bne.n 8008b54 } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8008bb4: 683b ldr r3, [r7, #0] 8008bb6: 9300 str r3, [sp, #0] 8008bb8: 697b ldr r3, [r7, #20] 8008bba: 2200 movs r2, #0 8008bbc: 2140 movs r1, #64 @ 0x40 8008bbe: 68f8 ldr r0, [r7, #12] 8008bc0: f000 fa25 bl 800900e 8008bc4: 4603 mov r3, r0 8008bc6: 2b00 cmp r3, #0 8008bc8: d001 beq.n 8008bce { return HAL_TIMEOUT; 8008bca: 2303 movs r3, #3 8008bcc: e006 b.n 8008bdc } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8008bce: 68fb ldr r3, [r7, #12] 8008bd0: 2220 movs r2, #32 8008bd2: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8008bd6: 2300 movs r3, #0 8008bd8: e000 b.n 8008bdc } else { return HAL_BUSY; 8008bda: 2302 movs r3, #2 } } 8008bdc: 4618 mov r0, r3 8008bde: 3720 adds r7, #32 8008be0: 46bd mov sp, r7 8008be2: bd80 pop {r7, pc} 08008be4 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8008be4: b580 push {r7, lr} 8008be6: b086 sub sp, #24 8008be8: af00 add r7, sp, #0 8008bea: 60f8 str r0, [r7, #12] 8008bec: 60b9 str r1, [r7, #8] 8008bee: 4613 mov r3, r2 8008bf0: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8008bf2: 68fb ldr r3, [r7, #12] 8008bf4: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8008bf8: b2db uxtb r3, r3 8008bfa: 2b20 cmp r3, #32 8008bfc: d13c bne.n 8008c78 { if ((pData == NULL) || (Size == 0U)) 8008bfe: 68bb ldr r3, [r7, #8] 8008c00: 2b00 cmp r3, #0 8008c02: d002 beq.n 8008c0a 8008c04: 88fb ldrh r3, [r7, #6] 8008c06: 2b00 cmp r3, #0 8008c08: d101 bne.n 8008c0e { return HAL_ERROR; 8008c0a: 2301 movs r3, #1 8008c0c: e035 b.n 8008c7a } __HAL_LOCK(huart); 8008c0e: 68fb ldr r3, [r7, #12] 8008c10: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8008c14: 2b01 cmp r3, #1 8008c16: d101 bne.n 8008c1c 8008c18: 2302 movs r3, #2 8008c1a: e02e b.n 8008c7a 8008c1c: 68fb ldr r3, [r7, #12] 8008c1e: 2201 movs r2, #1 8008c20: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8008c24: 68fb ldr r3, [r7, #12] 8008c26: 2201 movs r2, #1 8008c28: 631a str r2, [r3, #48] @ 0x30 status = UART_Start_Receive_IT(huart, pData, Size); 8008c2a: 88fb ldrh r3, [r7, #6] 8008c2c: 461a mov r2, r3 8008c2e: 68b9 ldr r1, [r7, #8] 8008c30: 68f8 ldr r0, [r7, #12] 8008c32: f000 fa36 bl 80090a2 8008c36: 4603 mov r3, r0 8008c38: 75fb strb r3, [r7, #23] /* Check Rx process has been successfully started */ if (status == HAL_OK) 8008c3a: 7dfb ldrb r3, [r7, #23] 8008c3c: 2b00 cmp r3, #0 8008c3e: d119 bne.n 8008c74 { if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8008c40: 68fb ldr r3, [r7, #12] 8008c42: 6b1b ldr r3, [r3, #48] @ 0x30 8008c44: 2b01 cmp r3, #1 8008c46: d113 bne.n 8008c70 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8008c48: 2300 movs r3, #0 8008c4a: 613b str r3, [r7, #16] 8008c4c: 68fb ldr r3, [r7, #12] 8008c4e: 681b ldr r3, [r3, #0] 8008c50: 681b ldr r3, [r3, #0] 8008c52: 613b str r3, [r7, #16] 8008c54: 68fb ldr r3, [r7, #12] 8008c56: 681b ldr r3, [r3, #0] 8008c58: 685b ldr r3, [r3, #4] 8008c5a: 613b str r3, [r7, #16] 8008c5c: 693b ldr r3, [r7, #16] SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8008c5e: 68fb ldr r3, [r7, #12] 8008c60: 681b ldr r3, [r3, #0] 8008c62: 68da ldr r2, [r3, #12] 8008c64: 68fb ldr r3, [r7, #12] 8008c66: 681b ldr r3, [r3, #0] 8008c68: f042 0210 orr.w r2, r2, #16 8008c6c: 60da str r2, [r3, #12] 8008c6e: e001 b.n 8008c74 { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8008c70: 2301 movs r3, #1 8008c72: 75fb strb r3, [r7, #23] } } return status; 8008c74: 7dfb ldrb r3, [r7, #23] 8008c76: e000 b.n 8008c7a } else { return HAL_BUSY; 8008c78: 2302 movs r3, #2 } } 8008c7a: 4618 mov r0, r3 8008c7c: 3718 adds r7, #24 8008c7e: 46bd mov sp, r7 8008c80: bd80 pop {r7, pc} ... 08008c84 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8008c84: b580 push {r7, lr} 8008c86: b08a sub sp, #40 @ 0x28 8008c88: af00 add r7, sp, #0 8008c8a: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 8008c8c: 687b ldr r3, [r7, #4] 8008c8e: 681b ldr r3, [r3, #0] 8008c90: 681b ldr r3, [r3, #0] 8008c92: 627b str r3, [r7, #36] @ 0x24 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8008c94: 687b ldr r3, [r7, #4] 8008c96: 681b ldr r3, [r3, #0] 8008c98: 68db ldr r3, [r3, #12] 8008c9a: 623b str r3, [r7, #32] uint32_t cr3its = READ_REG(huart->Instance->CR3); 8008c9c: 687b ldr r3, [r7, #4] 8008c9e: 681b ldr r3, [r3, #0] 8008ca0: 695b ldr r3, [r3, #20] 8008ca2: 61fb str r3, [r7, #28] uint32_t errorflags = 0x00U; 8008ca4: 2300 movs r3, #0 8008ca6: 61bb str r3, [r7, #24] uint32_t dmarequest = 0x00U; 8008ca8: 2300 movs r3, #0 8008caa: 617b str r3, [r7, #20] /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8008cac: 6a7b ldr r3, [r7, #36] @ 0x24 8008cae: f003 030f and.w r3, r3, #15 8008cb2: 61bb str r3, [r7, #24] if (errorflags == RESET) 8008cb4: 69bb ldr r3, [r7, #24] 8008cb6: 2b00 cmp r3, #0 8008cb8: d10d bne.n 8008cd6 { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8008cba: 6a7b ldr r3, [r7, #36] @ 0x24 8008cbc: f003 0320 and.w r3, r3, #32 8008cc0: 2b00 cmp r3, #0 8008cc2: d008 beq.n 8008cd6 8008cc4: 6a3b ldr r3, [r7, #32] 8008cc6: f003 0320 and.w r3, r3, #32 8008cca: 2b00 cmp r3, #0 8008ccc: d003 beq.n 8008cd6 { UART_Receive_IT(huart); 8008cce: 6878 ldr r0, [r7, #4] 8008cd0: f000 fac7 bl 8009262 return; 8008cd4: e17b b.n 8008fce } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8008cd6: 69bb ldr r3, [r7, #24] 8008cd8: 2b00 cmp r3, #0 8008cda: f000 80b1 beq.w 8008e40 8008cde: 69fb ldr r3, [r7, #28] 8008ce0: f003 0301 and.w r3, r3, #1 8008ce4: 2b00 cmp r3, #0 8008ce6: d105 bne.n 8008cf4 8008ce8: 6a3b ldr r3, [r7, #32] 8008cea: f403 7390 and.w r3, r3, #288 @ 0x120 8008cee: 2b00 cmp r3, #0 8008cf0: f000 80a6 beq.w 8008e40 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 8008cf4: 6a7b ldr r3, [r7, #36] @ 0x24 8008cf6: f003 0301 and.w r3, r3, #1 8008cfa: 2b00 cmp r3, #0 8008cfc: d00a beq.n 8008d14 8008cfe: 6a3b ldr r3, [r7, #32] 8008d00: f403 7380 and.w r3, r3, #256 @ 0x100 8008d04: 2b00 cmp r3, #0 8008d06: d005 beq.n 8008d14 { huart->ErrorCode |= HAL_UART_ERROR_PE; 8008d08: 687b ldr r3, [r7, #4] 8008d0a: 6c1b ldr r3, [r3, #64] @ 0x40 8008d0c: f043 0201 orr.w r2, r3, #1 8008d10: 687b ldr r3, [r7, #4] 8008d12: 641a str r2, [r3, #64] @ 0x40 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8008d14: 6a7b ldr r3, [r7, #36] @ 0x24 8008d16: f003 0304 and.w r3, r3, #4 8008d1a: 2b00 cmp r3, #0 8008d1c: d00a beq.n 8008d34 8008d1e: 69fb ldr r3, [r7, #28] 8008d20: f003 0301 and.w r3, r3, #1 8008d24: 2b00 cmp r3, #0 8008d26: d005 beq.n 8008d34 { huart->ErrorCode |= HAL_UART_ERROR_NE; 8008d28: 687b ldr r3, [r7, #4] 8008d2a: 6c1b ldr r3, [r3, #64] @ 0x40 8008d2c: f043 0202 orr.w r2, r3, #2 8008d30: 687b ldr r3, [r7, #4] 8008d32: 641a str r2, [r3, #64] @ 0x40 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8008d34: 6a7b ldr r3, [r7, #36] @ 0x24 8008d36: f003 0302 and.w r3, r3, #2 8008d3a: 2b00 cmp r3, #0 8008d3c: d00a beq.n 8008d54 8008d3e: 69fb ldr r3, [r7, #28] 8008d40: f003 0301 and.w r3, r3, #1 8008d44: 2b00 cmp r3, #0 8008d46: d005 beq.n 8008d54 { huart->ErrorCode |= HAL_UART_ERROR_FE; 8008d48: 687b ldr r3, [r7, #4] 8008d4a: 6c1b ldr r3, [r3, #64] @ 0x40 8008d4c: f043 0204 orr.w r2, r3, #4 8008d50: 687b ldr r3, [r7, #4] 8008d52: 641a str r2, [r3, #64] @ 0x40 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) 8008d54: 6a7b ldr r3, [r7, #36] @ 0x24 8008d56: f003 0308 and.w r3, r3, #8 8008d5a: 2b00 cmp r3, #0 8008d5c: d00f beq.n 8008d7e 8008d5e: 6a3b ldr r3, [r7, #32] 8008d60: f003 0320 and.w r3, r3, #32 8008d64: 2b00 cmp r3, #0 8008d66: d104 bne.n 8008d72 8008d68: 69fb ldr r3, [r7, #28] 8008d6a: f003 0301 and.w r3, r3, #1 8008d6e: 2b00 cmp r3, #0 8008d70: d005 beq.n 8008d7e { huart->ErrorCode |= HAL_UART_ERROR_ORE; 8008d72: 687b ldr r3, [r7, #4] 8008d74: 6c1b ldr r3, [r3, #64] @ 0x40 8008d76: f043 0208 orr.w r2, r3, #8 8008d7a: 687b ldr r3, [r7, #4] 8008d7c: 641a str r2, [r3, #64] @ 0x40 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8008d7e: 687b ldr r3, [r7, #4] 8008d80: 6c1b ldr r3, [r3, #64] @ 0x40 8008d82: 2b00 cmp r3, #0 8008d84: f000 811e beq.w 8008fc4 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8008d88: 6a7b ldr r3, [r7, #36] @ 0x24 8008d8a: f003 0320 and.w r3, r3, #32 8008d8e: 2b00 cmp r3, #0 8008d90: d007 beq.n 8008da2 8008d92: 6a3b ldr r3, [r7, #32] 8008d94: f003 0320 and.w r3, r3, #32 8008d98: 2b00 cmp r3, #0 8008d9a: d002 beq.n 8008da2 { UART_Receive_IT(huart); 8008d9c: 6878 ldr r0, [r7, #4] 8008d9e: f000 fa60 bl 8009262 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8008da2: 687b ldr r3, [r7, #4] 8008da4: 681b ldr r3, [r3, #0] 8008da6: 695b ldr r3, [r3, #20] 8008da8: f003 0340 and.w r3, r3, #64 @ 0x40 8008dac: 2b00 cmp r3, #0 8008dae: bf14 ite ne 8008db0: 2301 movne r3, #1 8008db2: 2300 moveq r3, #0 8008db4: b2db uxtb r3, r3 8008db6: 617b str r3, [r7, #20] if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8008db8: 687b ldr r3, [r7, #4] 8008dba: 6c1b ldr r3, [r3, #64] @ 0x40 8008dbc: f003 0308 and.w r3, r3, #8 8008dc0: 2b00 cmp r3, #0 8008dc2: d102 bne.n 8008dca 8008dc4: 697b ldr r3, [r7, #20] 8008dc6: 2b00 cmp r3, #0 8008dc8: d031 beq.n 8008e2e { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8008dca: 6878 ldr r0, [r7, #4] 8008dcc: f000 f9a2 bl 8009114 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8008dd0: 687b ldr r3, [r7, #4] 8008dd2: 681b ldr r3, [r3, #0] 8008dd4: 695b ldr r3, [r3, #20] 8008dd6: f003 0340 and.w r3, r3, #64 @ 0x40 8008dda: 2b00 cmp r3, #0 8008ddc: d023 beq.n 8008e26 { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8008dde: 687b ldr r3, [r7, #4] 8008de0: 681b ldr r3, [r3, #0] 8008de2: 695a ldr r2, [r3, #20] 8008de4: 687b ldr r3, [r7, #4] 8008de6: 681b ldr r3, [r3, #0] 8008de8: f022 0240 bic.w r2, r2, #64 @ 0x40 8008dec: 615a str r2, [r3, #20] /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 8008dee: 687b ldr r3, [r7, #4] 8008df0: 6b9b ldr r3, [r3, #56] @ 0x38 8008df2: 2b00 cmp r3, #0 8008df4: d013 beq.n 8008e1e { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8008df6: 687b ldr r3, [r7, #4] 8008df8: 6b9b ldr r3, [r3, #56] @ 0x38 8008dfa: 4a76 ldr r2, [pc, #472] @ (8008fd4 ) 8008dfc: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8008dfe: 687b ldr r3, [r7, #4] 8008e00: 6b9b ldr r3, [r3, #56] @ 0x38 8008e02: 4618 mov r0, r3 8008e04: f7fe fa72 bl 80072ec 8008e08: 4603 mov r3, r0 8008e0a: 2b00 cmp r3, #0 8008e0c: d016 beq.n 8008e3c { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8008e0e: 687b ldr r3, [r7, #4] 8008e10: 6b9b ldr r3, [r3, #56] @ 0x38 8008e12: 6b5b ldr r3, [r3, #52] @ 0x34 8008e14: 687a ldr r2, [r7, #4] 8008e16: 6b92 ldr r2, [r2, #56] @ 0x38 8008e18: 4610 mov r0, r2 8008e1a: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8008e1c: e00e b.n 8008e3c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8008e1e: 6878 ldr r0, [r7, #4] 8008e20: f000 f8ec bl 8008ffc if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8008e24: e00a b.n 8008e3c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8008e26: 6878 ldr r0, [r7, #4] 8008e28: f000 f8e8 bl 8008ffc if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8008e2c: e006 b.n 8008e3c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8008e2e: 6878 ldr r0, [r7, #4] 8008e30: f000 f8e4 bl 8008ffc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8008e34: 687b ldr r3, [r7, #4] 8008e36: 2200 movs r2, #0 8008e38: 641a str r2, [r3, #64] @ 0x40 } } return; 8008e3a: e0c3 b.n 8008fc4 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8008e3c: bf00 nop return; 8008e3e: e0c1 b.n 8008fc4 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8008e40: 687b ldr r3, [r7, #4] 8008e42: 6b1b ldr r3, [r3, #48] @ 0x30 8008e44: 2b01 cmp r3, #1 8008e46: f040 80a1 bne.w 8008f8c &&((isrflags & USART_SR_IDLE) != 0U) 8008e4a: 6a7b ldr r3, [r7, #36] @ 0x24 8008e4c: f003 0310 and.w r3, r3, #16 8008e50: 2b00 cmp r3, #0 8008e52: f000 809b beq.w 8008f8c &&((cr1its & USART_SR_IDLE) != 0U)) 8008e56: 6a3b ldr r3, [r7, #32] 8008e58: f003 0310 and.w r3, r3, #16 8008e5c: 2b00 cmp r3, #0 8008e5e: f000 8095 beq.w 8008f8c { __HAL_UART_CLEAR_IDLEFLAG(huart); 8008e62: 2300 movs r3, #0 8008e64: 60fb str r3, [r7, #12] 8008e66: 687b ldr r3, [r7, #4] 8008e68: 681b ldr r3, [r3, #0] 8008e6a: 681b ldr r3, [r3, #0] 8008e6c: 60fb str r3, [r7, #12] 8008e6e: 687b ldr r3, [r7, #4] 8008e70: 681b ldr r3, [r3, #0] 8008e72: 685b ldr r3, [r3, #4] 8008e74: 60fb str r3, [r7, #12] 8008e76: 68fb ldr r3, [r7, #12] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8008e78: 687b ldr r3, [r7, #4] 8008e7a: 681b ldr r3, [r3, #0] 8008e7c: 695b ldr r3, [r3, #20] 8008e7e: f003 0340 and.w r3, r3, #64 @ 0x40 8008e82: 2b00 cmp r3, #0 8008e84: d04e beq.n 8008f24 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8008e86: 687b ldr r3, [r7, #4] 8008e88: 6b9b ldr r3, [r3, #56] @ 0x38 8008e8a: 681b ldr r3, [r3, #0] 8008e8c: 685b ldr r3, [r3, #4] 8008e8e: 823b strh r3, [r7, #16] if ( (nb_remaining_rx_data > 0U) 8008e90: 8a3b ldrh r3, [r7, #16] 8008e92: 2b00 cmp r3, #0 8008e94: f000 8098 beq.w 8008fc8 &&(nb_remaining_rx_data < huart->RxXferSize)) 8008e98: 687b ldr r3, [r7, #4] 8008e9a: 8d9b ldrh r3, [r3, #44] @ 0x2c 8008e9c: 8a3a ldrh r2, [r7, #16] 8008e9e: 429a cmp r2, r3 8008ea0: f080 8092 bcs.w 8008fc8 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8008ea4: 687b ldr r3, [r7, #4] 8008ea6: 8a3a ldrh r2, [r7, #16] 8008ea8: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8008eaa: 687b ldr r3, [r7, #4] 8008eac: 6b9b ldr r3, [r3, #56] @ 0x38 8008eae: 699b ldr r3, [r3, #24] 8008eb0: 2b20 cmp r3, #32 8008eb2: d02b beq.n 8008f0c { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8008eb4: 687b ldr r3, [r7, #4] 8008eb6: 681b ldr r3, [r3, #0] 8008eb8: 68da ldr r2, [r3, #12] 8008eba: 687b ldr r3, [r7, #4] 8008ebc: 681b ldr r3, [r3, #0] 8008ebe: f422 7280 bic.w r2, r2, #256 @ 0x100 8008ec2: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8008ec4: 687b ldr r3, [r7, #4] 8008ec6: 681b ldr r3, [r3, #0] 8008ec8: 695a ldr r2, [r3, #20] 8008eca: 687b ldr r3, [r7, #4] 8008ecc: 681b ldr r3, [r3, #0] 8008ece: f022 0201 bic.w r2, r2, #1 8008ed2: 615a str r2, [r3, #20] /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8008ed4: 687b ldr r3, [r7, #4] 8008ed6: 681b ldr r3, [r3, #0] 8008ed8: 695a ldr r2, [r3, #20] 8008eda: 687b ldr r3, [r7, #4] 8008edc: 681b ldr r3, [r3, #0] 8008ede: f022 0240 bic.w r2, r2, #64 @ 0x40 8008ee2: 615a str r2, [r3, #20] /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8008ee4: 687b ldr r3, [r7, #4] 8008ee6: 2220 movs r2, #32 8008ee8: f883 203e strb.w r2, [r3, #62] @ 0x3e huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8008eec: 687b ldr r3, [r7, #4] 8008eee: 2200 movs r2, #0 8008ef0: 631a str r2, [r3, #48] @ 0x30 CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8008ef2: 687b ldr r3, [r7, #4] 8008ef4: 681b ldr r3, [r3, #0] 8008ef6: 68da ldr r2, [r3, #12] 8008ef8: 687b ldr r3, [r7, #4] 8008efa: 681b ldr r3, [r3, #0] 8008efc: f022 0210 bic.w r2, r2, #16 8008f00: 60da str r2, [r3, #12] /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8008f02: 687b ldr r3, [r7, #4] 8008f04: 6b9b ldr r3, [r3, #56] @ 0x38 8008f06: 4618 mov r0, r3 8008f08: f7fe f9b5 bl 8007276 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8008f0c: 687b ldr r3, [r7, #4] 8008f0e: 8d9a ldrh r2, [r3, #44] @ 0x2c 8008f10: 687b ldr r3, [r7, #4] 8008f12: 8ddb ldrh r3, [r3, #46] @ 0x2e 8008f14: b29b uxth r3, r3 8008f16: 1ad3 subs r3, r2, r3 8008f18: b29b uxth r3, r3 8008f1a: 4619 mov r1, r3 8008f1c: 6878 ldr r0, [r7, #4] 8008f1e: f7f9 ffb3 bl 8002e88 #endif } return; 8008f22: e051 b.n 8008fc8 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8008f24: 687b ldr r3, [r7, #4] 8008f26: 8d9a ldrh r2, [r3, #44] @ 0x2c 8008f28: 687b ldr r3, [r7, #4] 8008f2a: 8ddb ldrh r3, [r3, #46] @ 0x2e 8008f2c: b29b uxth r3, r3 8008f2e: 1ad3 subs r3, r2, r3 8008f30: 827b strh r3, [r7, #18] if ( (huart->RxXferCount > 0U) 8008f32: 687b ldr r3, [r7, #4] 8008f34: 8ddb ldrh r3, [r3, #46] @ 0x2e 8008f36: b29b uxth r3, r3 8008f38: 2b00 cmp r3, #0 8008f3a: d047 beq.n 8008fcc &&(nb_rx_data > 0U) ) 8008f3c: 8a7b ldrh r3, [r7, #18] 8008f3e: 2b00 cmp r3, #0 8008f40: d044 beq.n 8008fcc { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8008f42: 687b ldr r3, [r7, #4] 8008f44: 681b ldr r3, [r3, #0] 8008f46: 68da ldr r2, [r3, #12] 8008f48: 687b ldr r3, [r7, #4] 8008f4a: 681b ldr r3, [r3, #0] 8008f4c: f422 7290 bic.w r2, r2, #288 @ 0x120 8008f50: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8008f52: 687b ldr r3, [r7, #4] 8008f54: 681b ldr r3, [r3, #0] 8008f56: 695a ldr r2, [r3, #20] 8008f58: 687b ldr r3, [r7, #4] 8008f5a: 681b ldr r3, [r3, #0] 8008f5c: f022 0201 bic.w r2, r2, #1 8008f60: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8008f62: 687b ldr r3, [r7, #4] 8008f64: 2220 movs r2, #32 8008f66: f883 203e strb.w r2, [r3, #62] @ 0x3e huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8008f6a: 687b ldr r3, [r7, #4] 8008f6c: 2200 movs r2, #0 8008f6e: 631a str r2, [r3, #48] @ 0x30 CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8008f70: 687b ldr r3, [r7, #4] 8008f72: 681b ldr r3, [r3, #0] 8008f74: 68da ldr r2, [r3, #12] 8008f76: 687b ldr r3, [r7, #4] 8008f78: 681b ldr r3, [r3, #0] 8008f7a: f022 0210 bic.w r2, r2, #16 8008f7e: 60da str r2, [r3, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8008f80: 8a7b ldrh r3, [r7, #18] 8008f82: 4619 mov r1, r3 8008f84: 6878 ldr r0, [r7, #4] 8008f86: f7f9 ff7f bl 8002e88 #endif } return; 8008f8a: e01f b.n 8008fcc } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8008f8c: 6a7b ldr r3, [r7, #36] @ 0x24 8008f8e: f003 0380 and.w r3, r3, #128 @ 0x80 8008f92: 2b00 cmp r3, #0 8008f94: d008 beq.n 8008fa8 8008f96: 6a3b ldr r3, [r7, #32] 8008f98: f003 0380 and.w r3, r3, #128 @ 0x80 8008f9c: 2b00 cmp r3, #0 8008f9e: d003 beq.n 8008fa8 { UART_Transmit_IT(huart); 8008fa0: 6878 ldr r0, [r7, #4] 8008fa2: f000 f8f7 bl 8009194 return; 8008fa6: e012 b.n 8008fce } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8008fa8: 6a7b ldr r3, [r7, #36] @ 0x24 8008faa: f003 0340 and.w r3, r3, #64 @ 0x40 8008fae: 2b00 cmp r3, #0 8008fb0: d00d beq.n 8008fce 8008fb2: 6a3b ldr r3, [r7, #32] 8008fb4: f003 0340 and.w r3, r3, #64 @ 0x40 8008fb8: 2b00 cmp r3, #0 8008fba: d008 beq.n 8008fce { UART_EndTransmit_IT(huart); 8008fbc: 6878 ldr r0, [r7, #4] 8008fbe: f000 f938 bl 8009232 return; 8008fc2: e004 b.n 8008fce return; 8008fc4: bf00 nop 8008fc6: e002 b.n 8008fce return; 8008fc8: bf00 nop 8008fca: e000 b.n 8008fce return; 8008fcc: bf00 nop } } 8008fce: 3728 adds r7, #40 @ 0x28 8008fd0: 46bd mov sp, r7 8008fd2: bd80 pop {r7, pc} 8008fd4: 0800916d .word 0x0800916d 08008fd8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 8008fd8: b480 push {r7} 8008fda: b083 sub sp, #12 8008fdc: af00 add r7, sp, #0 8008fde: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 8008fe0: bf00 nop 8008fe2: 370c adds r7, #12 8008fe4: 46bd mov sp, r7 8008fe6: bc80 pop {r7} 8008fe8: 4770 bx lr 08008fea : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8008fea: b480 push {r7} 8008fec: b083 sub sp, #12 8008fee: af00 add r7, sp, #0 8008ff0: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback could be implemented in the user file */ } 8008ff2: bf00 nop 8008ff4: 370c adds r7, #12 8008ff6: 46bd mov sp, r7 8008ff8: bc80 pop {r7} 8008ffa: 4770 bx lr 08008ffc : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8008ffc: b480 push {r7} 8008ffe: b083 sub sp, #12 8009000: af00 add r7, sp, #0 8009002: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback could be implemented in the user file */ } 8009004: bf00 nop 8009006: 370c adds r7, #12 8009008: 46bd mov sp, r7 800900a: bc80 pop {r7} 800900c: 4770 bx lr 0800900e : * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 800900e: b580 push {r7, lr} 8009010: b084 sub sp, #16 8009012: af00 add r7, sp, #0 8009014: 60f8 str r0, [r7, #12] 8009016: 60b9 str r1, [r7, #8] 8009018: 603b str r3, [r7, #0] 800901a: 4613 mov r3, r2 800901c: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800901e: e02c b.n 800907a { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8009020: 69bb ldr r3, [r7, #24] 8009022: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8009026: d028 beq.n 800907a { if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) 8009028: 69bb ldr r3, [r7, #24] 800902a: 2b00 cmp r3, #0 800902c: d007 beq.n 800903e 800902e: f7fc fc37 bl 80058a0 8009032: 4602 mov r2, r0 8009034: 683b ldr r3, [r7, #0] 8009036: 1ad3 subs r3, r2, r3 8009038: 69ba ldr r2, [r7, #24] 800903a: 429a cmp r2, r3 800903c: d21d bcs.n 800907a { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); 800903e: 68fb ldr r3, [r7, #12] 8009040: 681b ldr r3, [r3, #0] 8009042: 68da ldr r2, [r3, #12] 8009044: 68fb ldr r3, [r7, #12] 8009046: 681b ldr r3, [r3, #0] 8009048: f422 72d0 bic.w r2, r2, #416 @ 0x1a0 800904c: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800904e: 68fb ldr r3, [r7, #12] 8009050: 681b ldr r3, [r3, #0] 8009052: 695a ldr r2, [r3, #20] 8009054: 68fb ldr r3, [r7, #12] 8009056: 681b ldr r3, [r3, #0] 8009058: f022 0201 bic.w r2, r2, #1 800905c: 615a str r2, [r3, #20] huart->gState = HAL_UART_STATE_READY; 800905e: 68fb ldr r3, [r7, #12] 8009060: 2220 movs r2, #32 8009062: f883 203d strb.w r2, [r3, #61] @ 0x3d huart->RxState = HAL_UART_STATE_READY; 8009066: 68fb ldr r3, [r7, #12] 8009068: 2220 movs r2, #32 800906a: f883 203e strb.w r2, [r3, #62] @ 0x3e /* Process Unlocked */ __HAL_UNLOCK(huart); 800906e: 68fb ldr r3, [r7, #12] 8009070: 2200 movs r2, #0 8009072: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_TIMEOUT; 8009076: 2303 movs r3, #3 8009078: e00f b.n 800909a while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800907a: 68fb ldr r3, [r7, #12] 800907c: 681b ldr r3, [r3, #0] 800907e: 681a ldr r2, [r3, #0] 8009080: 68bb ldr r3, [r7, #8] 8009082: 4013 ands r3, r2 8009084: 68ba ldr r2, [r7, #8] 8009086: 429a cmp r2, r3 8009088: bf0c ite eq 800908a: 2301 moveq r3, #1 800908c: 2300 movne r3, #0 800908e: b2db uxtb r3, r3 8009090: 461a mov r2, r3 8009092: 79fb ldrb r3, [r7, #7] 8009094: 429a cmp r2, r3 8009096: d0c3 beq.n 8009020 } } } return HAL_OK; 8009098: 2300 movs r3, #0 } 800909a: 4618 mov r0, r3 800909c: 3710 adds r7, #16 800909e: 46bd mov sp, r7 80090a0: bd80 pop {r7, pc} 080090a2 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80090a2: b480 push {r7} 80090a4: b085 sub sp, #20 80090a6: af00 add r7, sp, #0 80090a8: 60f8 str r0, [r7, #12] 80090aa: 60b9 str r1, [r7, #8] 80090ac: 4613 mov r3, r2 80090ae: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 80090b0: 68fb ldr r3, [r7, #12] 80090b2: 68ba ldr r2, [r7, #8] 80090b4: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 80090b6: 68fb ldr r3, [r7, #12] 80090b8: 88fa ldrh r2, [r7, #6] 80090ba: 859a strh r2, [r3, #44] @ 0x2c huart->RxXferCount = Size; 80090bc: 68fb ldr r3, [r7, #12] 80090be: 88fa ldrh r2, [r7, #6] 80090c0: 85da strh r2, [r3, #46] @ 0x2e huart->ErrorCode = HAL_UART_ERROR_NONE; 80090c2: 68fb ldr r3, [r7, #12] 80090c4: 2200 movs r2, #0 80090c6: 641a str r2, [r3, #64] @ 0x40 huart->RxState = HAL_UART_STATE_BUSY_RX; 80090c8: 68fb ldr r3, [r7, #12] 80090ca: 2222 movs r2, #34 @ 0x22 80090cc: f883 203e strb.w r2, [r3, #62] @ 0x3e /* Process Unlocked */ __HAL_UNLOCK(huart); 80090d0: 68fb ldr r3, [r7, #12] 80090d2: 2200 movs r2, #0 80090d4: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); 80090d8: 68fb ldr r3, [r7, #12] 80090da: 681b ldr r3, [r3, #0] 80090dc: 68da ldr r2, [r3, #12] 80090de: 68fb ldr r3, [r7, #12] 80090e0: 681b ldr r3, [r3, #0] 80090e2: f442 7280 orr.w r2, r2, #256 @ 0x100 80090e6: 60da str r2, [r3, #12] /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); 80090e8: 68fb ldr r3, [r7, #12] 80090ea: 681b ldr r3, [r3, #0] 80090ec: 695a ldr r2, [r3, #20] 80090ee: 68fb ldr r3, [r7, #12] 80090f0: 681b ldr r3, [r3, #0] 80090f2: f042 0201 orr.w r2, r2, #1 80090f6: 615a str r2, [r3, #20] /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); 80090f8: 68fb ldr r3, [r7, #12] 80090fa: 681b ldr r3, [r3, #0] 80090fc: 68da ldr r2, [r3, #12] 80090fe: 68fb ldr r3, [r7, #12] 8009100: 681b ldr r3, [r3, #0] 8009102: f042 0220 orr.w r2, r2, #32 8009106: 60da str r2, [r3, #12] return HAL_OK; 8009108: 2300 movs r3, #0 } 800910a: 4618 mov r0, r3 800910c: 3714 adds r7, #20 800910e: 46bd mov sp, r7 8009110: bc80 pop {r7} 8009112: 4770 bx lr 08009114 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8009114: b480 push {r7} 8009116: b083 sub sp, #12 8009118: af00 add r7, sp, #0 800911a: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 800911c: 687b ldr r3, [r7, #4] 800911e: 681b ldr r3, [r3, #0] 8009120: 68da ldr r2, [r3, #12] 8009122: 687b ldr r3, [r7, #4] 8009124: 681b ldr r3, [r3, #0] 8009126: f422 7290 bic.w r2, r2, #288 @ 0x120 800912a: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800912c: 687b ldr r3, [r7, #4] 800912e: 681b ldr r3, [r3, #0] 8009130: 695a ldr r2, [r3, #20] 8009132: 687b ldr r3, [r7, #4] 8009134: 681b ldr r3, [r3, #0] 8009136: f022 0201 bic.w r2, r2, #1 800913a: 615a str r2, [r3, #20] /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800913c: 687b ldr r3, [r7, #4] 800913e: 6b1b ldr r3, [r3, #48] @ 0x30 8009140: 2b01 cmp r3, #1 8009142: d107 bne.n 8009154 { CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8009144: 687b ldr r3, [r7, #4] 8009146: 681b ldr r3, [r3, #0] 8009148: 68da ldr r2, [r3, #12] 800914a: 687b ldr r3, [r7, #4] 800914c: 681b ldr r3, [r3, #0] 800914e: f022 0210 bic.w r2, r2, #16 8009152: 60da str r2, [r3, #12] } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8009154: 687b ldr r3, [r7, #4] 8009156: 2220 movs r2, #32 8009158: f883 203e strb.w r2, [r3, #62] @ 0x3e huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800915c: 687b ldr r3, [r7, #4] 800915e: 2200 movs r2, #0 8009160: 631a str r2, [r3, #48] @ 0x30 } 8009162: bf00 nop 8009164: 370c adds r7, #12 8009166: 46bd mov sp, r7 8009168: bc80 pop {r7} 800916a: 4770 bx lr 0800916c : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 800916c: b580 push {r7, lr} 800916e: b084 sub sp, #16 8009170: af00 add r7, sp, #0 8009172: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8009174: 687b ldr r3, [r7, #4] 8009176: 6a5b ldr r3, [r3, #36] @ 0x24 8009178: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 800917a: 68fb ldr r3, [r7, #12] 800917c: 2200 movs r2, #0 800917e: 85da strh r2, [r3, #46] @ 0x2e huart->TxXferCount = 0x00U; 8009180: 68fb ldr r3, [r7, #12] 8009182: 2200 movs r2, #0 8009184: 84da strh r2, [r3, #38] @ 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8009186: 68f8 ldr r0, [r7, #12] 8009188: f7ff ff38 bl 8008ffc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 800918c: bf00 nop 800918e: 3710 adds r7, #16 8009190: 46bd mov sp, r7 8009192: bd80 pop {r7, pc} 08009194 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 8009194: b480 push {r7} 8009196: b085 sub sp, #20 8009198: af00 add r7, sp, #0 800919a: 6078 str r0, [r7, #4] uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 800919c: 687b ldr r3, [r7, #4] 800919e: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 80091a2: b2db uxtb r3, r3 80091a4: 2b21 cmp r3, #33 @ 0x21 80091a6: d13e bne.n 8009226 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80091a8: 687b ldr r3, [r7, #4] 80091aa: 689b ldr r3, [r3, #8] 80091ac: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80091b0: d114 bne.n 80091dc 80091b2: 687b ldr r3, [r7, #4] 80091b4: 691b ldr r3, [r3, #16] 80091b6: 2b00 cmp r3, #0 80091b8: d110 bne.n 80091dc { tmp = (uint16_t *) huart->pTxBuffPtr; 80091ba: 687b ldr r3, [r7, #4] 80091bc: 6a1b ldr r3, [r3, #32] 80091be: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 80091c0: 68fb ldr r3, [r7, #12] 80091c2: 881b ldrh r3, [r3, #0] 80091c4: 461a mov r2, r3 80091c6: 687b ldr r3, [r7, #4] 80091c8: 681b ldr r3, [r3, #0] 80091ca: f3c2 0208 ubfx r2, r2, #0, #9 80091ce: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 80091d0: 687b ldr r3, [r7, #4] 80091d2: 6a1b ldr r3, [r3, #32] 80091d4: 1c9a adds r2, r3, #2 80091d6: 687b ldr r3, [r7, #4] 80091d8: 621a str r2, [r3, #32] 80091da: e008 b.n 80091ee } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 80091dc: 687b ldr r3, [r7, #4] 80091de: 6a1b ldr r3, [r3, #32] 80091e0: 1c59 adds r1, r3, #1 80091e2: 687a ldr r2, [r7, #4] 80091e4: 6211 str r1, [r2, #32] 80091e6: 781a ldrb r2, [r3, #0] 80091e8: 687b ldr r3, [r7, #4] 80091ea: 681b ldr r3, [r3, #0] 80091ec: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 80091ee: 687b ldr r3, [r7, #4] 80091f0: 8cdb ldrh r3, [r3, #38] @ 0x26 80091f2: b29b uxth r3, r3 80091f4: 3b01 subs r3, #1 80091f6: b29b uxth r3, r3 80091f8: 687a ldr r2, [r7, #4] 80091fa: 4619 mov r1, r3 80091fc: 84d1 strh r1, [r2, #38] @ 0x26 80091fe: 2b00 cmp r3, #0 8009200: d10f bne.n 8009222 { /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8009202: 687b ldr r3, [r7, #4] 8009204: 681b ldr r3, [r3, #0] 8009206: 68da ldr r2, [r3, #12] 8009208: 687b ldr r3, [r7, #4] 800920a: 681b ldr r3, [r3, #0] 800920c: f022 0280 bic.w r2, r2, #128 @ 0x80 8009210: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8009212: 687b ldr r3, [r7, #4] 8009214: 681b ldr r3, [r3, #0] 8009216: 68da ldr r2, [r3, #12] 8009218: 687b ldr r3, [r7, #4] 800921a: 681b ldr r3, [r3, #0] 800921c: f042 0240 orr.w r2, r2, #64 @ 0x40 8009220: 60da str r2, [r3, #12] } return HAL_OK; 8009222: 2300 movs r3, #0 8009224: e000 b.n 8009228 } else { return HAL_BUSY; 8009226: 2302 movs r3, #2 } } 8009228: 4618 mov r0, r3 800922a: 3714 adds r7, #20 800922c: 46bd mov sp, r7 800922e: bc80 pop {r7} 8009230: 4770 bx lr 08009232 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8009232: b580 push {r7, lr} 8009234: b082 sub sp, #8 8009236: af00 add r7, sp, #0 8009238: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 800923a: 687b ldr r3, [r7, #4] 800923c: 681b ldr r3, [r3, #0] 800923e: 68da ldr r2, [r3, #12] 8009240: 687b ldr r3, [r7, #4] 8009242: 681b ldr r3, [r3, #0] 8009244: f022 0240 bic.w r2, r2, #64 @ 0x40 8009248: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 800924a: 687b ldr r3, [r7, #4] 800924c: 2220 movs r2, #32 800924e: f883 203d strb.w r2, [r3, #61] @ 0x3d #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8009252: 6878 ldr r0, [r7, #4] 8009254: f7ff fec0 bl 8008fd8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8009258: 2300 movs r3, #0 } 800925a: 4618 mov r0, r3 800925c: 3708 adds r7, #8 800925e: 46bd mov sp, r7 8009260: bd80 pop {r7, pc} 08009262 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 8009262: b580 push {r7, lr} 8009264: b086 sub sp, #24 8009266: af00 add r7, sp, #0 8009268: 6078 str r0, [r7, #4] uint8_t *pdata8bits; uint16_t *pdata16bits; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 800926a: 687b ldr r3, [r7, #4] 800926c: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8009270: b2db uxtb r3, r3 8009272: 2b22 cmp r3, #34 @ 0x22 8009274: f040 8099 bne.w 80093aa { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8009278: 687b ldr r3, [r7, #4] 800927a: 689b ldr r3, [r3, #8] 800927c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8009280: d117 bne.n 80092b2 8009282: 687b ldr r3, [r7, #4] 8009284: 691b ldr r3, [r3, #16] 8009286: 2b00 cmp r3, #0 8009288: d113 bne.n 80092b2 { pdata8bits = NULL; 800928a: 2300 movs r3, #0 800928c: 617b str r3, [r7, #20] pdata16bits = (uint16_t *) huart->pRxBuffPtr; 800928e: 687b ldr r3, [r7, #4] 8009290: 6a9b ldr r3, [r3, #40] @ 0x28 8009292: 613b str r3, [r7, #16] *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8009294: 687b ldr r3, [r7, #4] 8009296: 681b ldr r3, [r3, #0] 8009298: 685b ldr r3, [r3, #4] 800929a: b29b uxth r3, r3 800929c: f3c3 0308 ubfx r3, r3, #0, #9 80092a0: b29a uxth r2, r3 80092a2: 693b ldr r3, [r7, #16] 80092a4: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 80092a6: 687b ldr r3, [r7, #4] 80092a8: 6a9b ldr r3, [r3, #40] @ 0x28 80092aa: 1c9a adds r2, r3, #2 80092ac: 687b ldr r3, [r7, #4] 80092ae: 629a str r2, [r3, #40] @ 0x28 80092b0: e026 b.n 8009300 } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 80092b2: 687b ldr r3, [r7, #4] 80092b4: 6a9b ldr r3, [r3, #40] @ 0x28 80092b6: 617b str r3, [r7, #20] pdata16bits = NULL; 80092b8: 2300 movs r3, #0 80092ba: 613b str r3, [r7, #16] if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 80092bc: 687b ldr r3, [r7, #4] 80092be: 689b ldr r3, [r3, #8] 80092c0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80092c4: d007 beq.n 80092d6 80092c6: 687b ldr r3, [r7, #4] 80092c8: 689b ldr r3, [r3, #8] 80092ca: 2b00 cmp r3, #0 80092cc: d10a bne.n 80092e4 80092ce: 687b ldr r3, [r7, #4] 80092d0: 691b ldr r3, [r3, #16] 80092d2: 2b00 cmp r3, #0 80092d4: d106 bne.n 80092e4 { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 80092d6: 687b ldr r3, [r7, #4] 80092d8: 681b ldr r3, [r3, #0] 80092da: 685b ldr r3, [r3, #4] 80092dc: b2da uxtb r2, r3 80092de: 697b ldr r3, [r7, #20] 80092e0: 701a strb r2, [r3, #0] 80092e2: e008 b.n 80092f6 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 80092e4: 687b ldr r3, [r7, #4] 80092e6: 681b ldr r3, [r3, #0] 80092e8: 685b ldr r3, [r3, #4] 80092ea: b2db uxtb r3, r3 80092ec: f003 037f and.w r3, r3, #127 @ 0x7f 80092f0: b2da uxtb r2, r3 80092f2: 697b ldr r3, [r7, #20] 80092f4: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 80092f6: 687b ldr r3, [r7, #4] 80092f8: 6a9b ldr r3, [r3, #40] @ 0x28 80092fa: 1c5a adds r2, r3, #1 80092fc: 687b ldr r3, [r7, #4] 80092fe: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 8009300: 687b ldr r3, [r7, #4] 8009302: 8ddb ldrh r3, [r3, #46] @ 0x2e 8009304: b29b uxth r3, r3 8009306: 3b01 subs r3, #1 8009308: b29b uxth r3, r3 800930a: 687a ldr r2, [r7, #4] 800930c: 4619 mov r1, r3 800930e: 85d1 strh r1, [r2, #46] @ 0x2e 8009310: 2b00 cmp r3, #0 8009312: d148 bne.n 80093a6 { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8009314: 687b ldr r3, [r7, #4] 8009316: 681b ldr r3, [r3, #0] 8009318: 68da ldr r2, [r3, #12] 800931a: 687b ldr r3, [r7, #4] 800931c: 681b ldr r3, [r3, #0] 800931e: f022 0220 bic.w r2, r2, #32 8009322: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8009324: 687b ldr r3, [r7, #4] 8009326: 681b ldr r3, [r3, #0] 8009328: 68da ldr r2, [r3, #12] 800932a: 687b ldr r3, [r7, #4] 800932c: 681b ldr r3, [r3, #0] 800932e: f422 7280 bic.w r2, r2, #256 @ 0x100 8009332: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8009334: 687b ldr r3, [r7, #4] 8009336: 681b ldr r3, [r3, #0] 8009338: 695a ldr r2, [r3, #20] 800933a: 687b ldr r3, [r7, #4] 800933c: 681b ldr r3, [r3, #0] 800933e: f022 0201 bic.w r2, r2, #1 8009342: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8009344: 687b ldr r3, [r7, #4] 8009346: 2220 movs r2, #32 8009348: f883 203e strb.w r2, [r3, #62] @ 0x3e /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800934c: 687b ldr r3, [r7, #4] 800934e: 6b1b ldr r3, [r3, #48] @ 0x30 8009350: 2b01 cmp r3, #1 8009352: d123 bne.n 800939c { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8009354: 687b ldr r3, [r7, #4] 8009356: 2200 movs r2, #0 8009358: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800935a: 687b ldr r3, [r7, #4] 800935c: 681b ldr r3, [r3, #0] 800935e: 68da ldr r2, [r3, #12] 8009360: 687b ldr r3, [r7, #4] 8009362: 681b ldr r3, [r3, #0] 8009364: f022 0210 bic.w r2, r2, #16 8009368: 60da str r2, [r3, #12] /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 800936a: 687b ldr r3, [r7, #4] 800936c: 681b ldr r3, [r3, #0] 800936e: 681b ldr r3, [r3, #0] 8009370: f003 0310 and.w r3, r3, #16 8009374: 2b10 cmp r3, #16 8009376: d10a bne.n 800938e { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 8009378: 2300 movs r3, #0 800937a: 60fb str r3, [r7, #12] 800937c: 687b ldr r3, [r7, #4] 800937e: 681b ldr r3, [r3, #0] 8009380: 681b ldr r3, [r3, #0] 8009382: 60fb str r3, [r7, #12] 8009384: 687b ldr r3, [r7, #4] 8009386: 681b ldr r3, [r3, #0] 8009388: 685b ldr r3, [r3, #4] 800938a: 60fb str r3, [r7, #12] 800938c: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800938e: 687b ldr r3, [r7, #4] 8009390: 8d9b ldrh r3, [r3, #44] @ 0x2c 8009392: 4619 mov r1, r3 8009394: 6878 ldr r0, [r7, #4] 8009396: f7f9 fd77 bl 8002e88 800939a: e002 b.n 80093a2 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 800939c: 6878 ldr r0, [r7, #4] 800939e: f7ff fe24 bl 8008fea #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 80093a2: 2300 movs r3, #0 80093a4: e002 b.n 80093ac } return HAL_OK; 80093a6: 2300 movs r3, #0 80093a8: e000 b.n 80093ac } else { return HAL_BUSY; 80093aa: 2302 movs r3, #2 } } 80093ac: 4618 mov r0, r3 80093ae: 3718 adds r7, #24 80093b0: 46bd mov sp, r7 80093b2: bd80 pop {r7, pc} 080093b4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 80093b4: b580 push {r7, lr} 80093b6: b084 sub sp, #16 80093b8: af00 add r7, sp, #0 80093ba: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 80093bc: 687b ldr r3, [r7, #4] 80093be: 681b ldr r3, [r3, #0] 80093c0: 691b ldr r3, [r3, #16] 80093c2: f423 5140 bic.w r1, r3, #12288 @ 0x3000 80093c6: 687b ldr r3, [r7, #4] 80093c8: 68da ldr r2, [r3, #12] 80093ca: 687b ldr r3, [r7, #4] 80093cc: 681b ldr r3, [r3, #0] 80093ce: 430a orrs r2, r1 80093d0: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 80093d2: 687b ldr r3, [r7, #4] 80093d4: 689a ldr r2, [r3, #8] 80093d6: 687b ldr r3, [r7, #4] 80093d8: 691b ldr r3, [r3, #16] 80093da: 431a orrs r2, r3 80093dc: 687b ldr r3, [r7, #4] 80093de: 695b ldr r3, [r3, #20] 80093e0: 4313 orrs r3, r2 80093e2: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 80093e4: 687b ldr r3, [r7, #4] 80093e6: 681b ldr r3, [r3, #0] 80093e8: 68db ldr r3, [r3, #12] 80093ea: f423 53b0 bic.w r3, r3, #5632 @ 0x1600 80093ee: f023 030c bic.w r3, r3, #12 80093f2: 687a ldr r2, [r7, #4] 80093f4: 6812 ldr r2, [r2, #0] 80093f6: 68b9 ldr r1, [r7, #8] 80093f8: 430b orrs r3, r1 80093fa: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 80093fc: 687b ldr r3, [r7, #4] 80093fe: 681b ldr r3, [r3, #0] 8009400: 695b ldr r3, [r3, #20] 8009402: f423 7140 bic.w r1, r3, #768 @ 0x300 8009406: 687b ldr r3, [r7, #4] 8009408: 699a ldr r2, [r3, #24] 800940a: 687b ldr r3, [r7, #4] 800940c: 681b ldr r3, [r3, #0] 800940e: 430a orrs r2, r1 8009410: 615a str r2, [r3, #20] if(huart->Instance == USART1) 8009412: 687b ldr r3, [r7, #4] 8009414: 681b ldr r3, [r3, #0] 8009416: 4a2c ldr r2, [pc, #176] @ (80094c8 ) 8009418: 4293 cmp r3, r2 800941a: d103 bne.n 8009424 { pclk = HAL_RCC_GetPCLK2Freq(); 800941c: f7fe ff2a bl 8008274 8009420: 60f8 str r0, [r7, #12] 8009422: e002 b.n 800942a } else { pclk = HAL_RCC_GetPCLK1Freq(); 8009424: f7fe ff12 bl 800824c 8009428: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 800942a: 68fa ldr r2, [r7, #12] 800942c: 4613 mov r3, r2 800942e: 009b lsls r3, r3, #2 8009430: 4413 add r3, r2 8009432: 009a lsls r2, r3, #2 8009434: 441a add r2, r3 8009436: 687b ldr r3, [r7, #4] 8009438: 685b ldr r3, [r3, #4] 800943a: 009b lsls r3, r3, #2 800943c: fbb2 f3f3 udiv r3, r2, r3 8009440: 4a22 ldr r2, [pc, #136] @ (80094cc ) 8009442: fba2 2303 umull r2, r3, r2, r3 8009446: 095b lsrs r3, r3, #5 8009448: 0119 lsls r1, r3, #4 800944a: 68fa ldr r2, [r7, #12] 800944c: 4613 mov r3, r2 800944e: 009b lsls r3, r3, #2 8009450: 4413 add r3, r2 8009452: 009a lsls r2, r3, #2 8009454: 441a add r2, r3 8009456: 687b ldr r3, [r7, #4] 8009458: 685b ldr r3, [r3, #4] 800945a: 009b lsls r3, r3, #2 800945c: fbb2 f2f3 udiv r2, r2, r3 8009460: 4b1a ldr r3, [pc, #104] @ (80094cc ) 8009462: fba3 0302 umull r0, r3, r3, r2 8009466: 095b lsrs r3, r3, #5 8009468: 2064 movs r0, #100 @ 0x64 800946a: fb00 f303 mul.w r3, r0, r3 800946e: 1ad3 subs r3, r2, r3 8009470: 011b lsls r3, r3, #4 8009472: 3332 adds r3, #50 @ 0x32 8009474: 4a15 ldr r2, [pc, #84] @ (80094cc ) 8009476: fba2 2303 umull r2, r3, r2, r3 800947a: 095b lsrs r3, r3, #5 800947c: f003 03f0 and.w r3, r3, #240 @ 0xf0 8009480: 4419 add r1, r3 8009482: 68fa ldr r2, [r7, #12] 8009484: 4613 mov r3, r2 8009486: 009b lsls r3, r3, #2 8009488: 4413 add r3, r2 800948a: 009a lsls r2, r3, #2 800948c: 441a add r2, r3 800948e: 687b ldr r3, [r7, #4] 8009490: 685b ldr r3, [r3, #4] 8009492: 009b lsls r3, r3, #2 8009494: fbb2 f2f3 udiv r2, r2, r3 8009498: 4b0c ldr r3, [pc, #48] @ (80094cc ) 800949a: fba3 0302 umull r0, r3, r3, r2 800949e: 095b lsrs r3, r3, #5 80094a0: 2064 movs r0, #100 @ 0x64 80094a2: fb00 f303 mul.w r3, r0, r3 80094a6: 1ad3 subs r3, r2, r3 80094a8: 011b lsls r3, r3, #4 80094aa: 3332 adds r3, #50 @ 0x32 80094ac: 4a07 ldr r2, [pc, #28] @ (80094cc ) 80094ae: fba2 2303 umull r2, r3, r2, r3 80094b2: 095b lsrs r3, r3, #5 80094b4: f003 020f and.w r2, r3, #15 80094b8: 687b ldr r3, [r7, #4] 80094ba: 681b ldr r3, [r3, #0] 80094bc: 440a add r2, r1 80094be: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 80094c0: bf00 nop 80094c2: 3710 adds r7, #16 80094c4: 46bd mov sp, r7 80094c6: bd80 pop {r7, pc} 80094c8: 40013800 .word 0x40013800 80094cc: 51eb851f .word 0x51eb851f 080094d0 <__cvt>: 80094d0: 2b00 cmp r3, #0 80094d2: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80094d6: 461d mov r5, r3 80094d8: bfbb ittet lt 80094da: f103 4300 addlt.w r3, r3, #2147483648 @ 0x80000000 80094de: 461d movlt r5, r3 80094e0: 2300 movge r3, #0 80094e2: 232d movlt r3, #45 @ 0x2d 80094e4: b088 sub sp, #32 80094e6: 4614 mov r4, r2 80094e8: bfb8 it lt 80094ea: 4614 movlt r4, r2 80094ec: 9a12 ldr r2, [sp, #72] @ 0x48 80094ee: 9e10 ldr r6, [sp, #64] @ 0x40 80094f0: 7013 strb r3, [r2, #0] 80094f2: 9b14 ldr r3, [sp, #80] @ 0x50 80094f4: f8dd a04c ldr.w sl, [sp, #76] @ 0x4c 80094f8: f023 0820 bic.w r8, r3, #32 80094fc: f1b8 0f46 cmp.w r8, #70 @ 0x46 8009500: d005 beq.n 800950e <__cvt+0x3e> 8009502: f1b8 0f45 cmp.w r8, #69 @ 0x45 8009506: d100 bne.n 800950a <__cvt+0x3a> 8009508: 3601 adds r6, #1 800950a: 2302 movs r3, #2 800950c: e000 b.n 8009510 <__cvt+0x40> 800950e: 2303 movs r3, #3 8009510: aa07 add r2, sp, #28 8009512: 9204 str r2, [sp, #16] 8009514: aa06 add r2, sp, #24 8009516: e9cd a202 strd sl, r2, [sp, #8] 800951a: e9cd 3600 strd r3, r6, [sp] 800951e: 4622 mov r2, r4 8009520: 462b mov r3, r5 8009522: f001 fba9 bl 800ac78 <_dtoa_r> 8009526: f1b8 0f47 cmp.w r8, #71 @ 0x47 800952a: 4607 mov r7, r0 800952c: d119 bne.n 8009562 <__cvt+0x92> 800952e: 9b11 ldr r3, [sp, #68] @ 0x44 8009530: 07db lsls r3, r3, #31 8009532: d50e bpl.n 8009552 <__cvt+0x82> 8009534: eb00 0906 add.w r9, r0, r6 8009538: 2200 movs r2, #0 800953a: 2300 movs r3, #0 800953c: 4620 mov r0, r4 800953e: 4629 mov r1, r5 8009540: f7f7 faa8 bl 8000a94 <__aeabi_dcmpeq> 8009544: b108 cbz r0, 800954a <__cvt+0x7a> 8009546: f8cd 901c str.w r9, [sp, #28] 800954a: 2230 movs r2, #48 @ 0x30 800954c: 9b07 ldr r3, [sp, #28] 800954e: 454b cmp r3, r9 8009550: d31e bcc.n 8009590 <__cvt+0xc0> 8009552: 4638 mov r0, r7 8009554: 9b07 ldr r3, [sp, #28] 8009556: 9a15 ldr r2, [sp, #84] @ 0x54 8009558: 1bdb subs r3, r3, r7 800955a: 6013 str r3, [r2, #0] 800955c: b008 add sp, #32 800955e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8009562: f1b8 0f46 cmp.w r8, #70 @ 0x46 8009566: eb00 0906 add.w r9, r0, r6 800956a: d1e5 bne.n 8009538 <__cvt+0x68> 800956c: 7803 ldrb r3, [r0, #0] 800956e: 2b30 cmp r3, #48 @ 0x30 8009570: d10a bne.n 8009588 <__cvt+0xb8> 8009572: 2200 movs r2, #0 8009574: 2300 movs r3, #0 8009576: 4620 mov r0, r4 8009578: 4629 mov r1, r5 800957a: f7f7 fa8b bl 8000a94 <__aeabi_dcmpeq> 800957e: b918 cbnz r0, 8009588 <__cvt+0xb8> 8009580: f1c6 0601 rsb r6, r6, #1 8009584: f8ca 6000 str.w r6, [sl] 8009588: f8da 3000 ldr.w r3, [sl] 800958c: 4499 add r9, r3 800958e: e7d3 b.n 8009538 <__cvt+0x68> 8009590: 1c59 adds r1, r3, #1 8009592: 9107 str r1, [sp, #28] 8009594: 701a strb r2, [r3, #0] 8009596: e7d9 b.n 800954c <__cvt+0x7c> 08009598 <__exponent>: 8009598: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 800959a: 2900 cmp r1, #0 800959c: bfb6 itet lt 800959e: 232d movlt r3, #45 @ 0x2d 80095a0: 232b movge r3, #43 @ 0x2b 80095a2: 4249 neglt r1, r1 80095a4: 2909 cmp r1, #9 80095a6: 7002 strb r2, [r0, #0] 80095a8: 7043 strb r3, [r0, #1] 80095aa: dd29 ble.n 8009600 <__exponent+0x68> 80095ac: f10d 0307 add.w r3, sp, #7 80095b0: 461d mov r5, r3 80095b2: 270a movs r7, #10 80095b4: fbb1 f6f7 udiv r6, r1, r7 80095b8: 461a mov r2, r3 80095ba: fb07 1416 mls r4, r7, r6, r1 80095be: 3430 adds r4, #48 @ 0x30 80095c0: f802 4c01 strb.w r4, [r2, #-1] 80095c4: 460c mov r4, r1 80095c6: 2c63 cmp r4, #99 @ 0x63 80095c8: 4631 mov r1, r6 80095ca: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff 80095ce: dcf1 bgt.n 80095b4 <__exponent+0x1c> 80095d0: 3130 adds r1, #48 @ 0x30 80095d2: 1e94 subs r4, r2, #2 80095d4: f803 1c01 strb.w r1, [r3, #-1] 80095d8: 4623 mov r3, r4 80095da: 1c41 adds r1, r0, #1 80095dc: 42ab cmp r3, r5 80095de: d30a bcc.n 80095f6 <__exponent+0x5e> 80095e0: f10d 0309 add.w r3, sp, #9 80095e4: 1a9b subs r3, r3, r2 80095e6: 42ac cmp r4, r5 80095e8: bf88 it hi 80095ea: 2300 movhi r3, #0 80095ec: 3302 adds r3, #2 80095ee: 4403 add r3, r0 80095f0: 1a18 subs r0, r3, r0 80095f2: b003 add sp, #12 80095f4: bdf0 pop {r4, r5, r6, r7, pc} 80095f6: f813 6b01 ldrb.w r6, [r3], #1 80095fa: f801 6f01 strb.w r6, [r1, #1]! 80095fe: e7ed b.n 80095dc <__exponent+0x44> 8009600: 2330 movs r3, #48 @ 0x30 8009602: 3130 adds r1, #48 @ 0x30 8009604: 7083 strb r3, [r0, #2] 8009606: 70c1 strb r1, [r0, #3] 8009608: 1d03 adds r3, r0, #4 800960a: e7f1 b.n 80095f0 <__exponent+0x58> 0800960c <_printf_float>: 800960c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8009610: b091 sub sp, #68 @ 0x44 8009612: 460c mov r4, r1 8009614: f8dd 8068 ldr.w r8, [sp, #104] @ 0x68 8009618: 4616 mov r6, r2 800961a: 461f mov r7, r3 800961c: 4605 mov r5, r0 800961e: f001 fa5b bl 800aad8 <_localeconv_r> 8009622: 6803 ldr r3, [r0, #0] 8009624: 4618 mov r0, r3 8009626: 9308 str r3, [sp, #32] 8009628: f7f6 fe08 bl 800023c 800962c: 2300 movs r3, #0 800962e: 930e str r3, [sp, #56] @ 0x38 8009630: f8d8 3000 ldr.w r3, [r8] 8009634: 9009 str r0, [sp, #36] @ 0x24 8009636: 3307 adds r3, #7 8009638: f023 0307 bic.w r3, r3, #7 800963c: f103 0208 add.w r2, r3, #8 8009640: f894 a018 ldrb.w sl, [r4, #24] 8009644: f8d4 b000 ldr.w fp, [r4] 8009648: f8c8 2000 str.w r2, [r8] 800964c: e9d3 8900 ldrd r8, r9, [r3] 8009650: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000 8009654: 930b str r3, [sp, #44] @ 0x2c 8009656: f8cd 8028 str.w r8, [sp, #40] @ 0x28 800965a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800965e: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 8009662: e9c4 8912 strd r8, r9, [r4, #72] @ 0x48 8009666: 4b9c ldr r3, [pc, #624] @ (80098d8 <_printf_float+0x2cc>) 8009668: f7f7 fa46 bl 8000af8 <__aeabi_dcmpun> 800966c: bb70 cbnz r0, 80096cc <_printf_float+0xc0> 800966e: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 8009672: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8009676: 4b98 ldr r3, [pc, #608] @ (80098d8 <_printf_float+0x2cc>) 8009678: f7f7 fa20 bl 8000abc <__aeabi_dcmple> 800967c: bb30 cbnz r0, 80096cc <_printf_float+0xc0> 800967e: 2200 movs r2, #0 8009680: 2300 movs r3, #0 8009682: 4640 mov r0, r8 8009684: 4649 mov r1, r9 8009686: f7f7 fa0f bl 8000aa8 <__aeabi_dcmplt> 800968a: b110 cbz r0, 8009692 <_printf_float+0x86> 800968c: 232d movs r3, #45 @ 0x2d 800968e: f884 3043 strb.w r3, [r4, #67] @ 0x43 8009692: 4a92 ldr r2, [pc, #584] @ (80098dc <_printf_float+0x2d0>) 8009694: 4b92 ldr r3, [pc, #584] @ (80098e0 <_printf_float+0x2d4>) 8009696: f1ba 0f47 cmp.w sl, #71 @ 0x47 800969a: bf8c ite hi 800969c: 4690 movhi r8, r2 800969e: 4698 movls r8, r3 80096a0: 2303 movs r3, #3 80096a2: f04f 0900 mov.w r9, #0 80096a6: 6123 str r3, [r4, #16] 80096a8: f02b 0304 bic.w r3, fp, #4 80096ac: 6023 str r3, [r4, #0] 80096ae: 4633 mov r3, r6 80096b0: 4621 mov r1, r4 80096b2: 4628 mov r0, r5 80096b4: 9700 str r7, [sp, #0] 80096b6: aa0f add r2, sp, #60 @ 0x3c 80096b8: f000 f9d4 bl 8009a64 <_printf_common> 80096bc: 3001 adds r0, #1 80096be: f040 8090 bne.w 80097e2 <_printf_float+0x1d6> 80096c2: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80096c6: b011 add sp, #68 @ 0x44 80096c8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80096cc: 4642 mov r2, r8 80096ce: 464b mov r3, r9 80096d0: 4640 mov r0, r8 80096d2: 4649 mov r1, r9 80096d4: f7f7 fa10 bl 8000af8 <__aeabi_dcmpun> 80096d8: b148 cbz r0, 80096ee <_printf_float+0xe2> 80096da: 464b mov r3, r9 80096dc: 2b00 cmp r3, #0 80096de: bfb8 it lt 80096e0: 232d movlt r3, #45 @ 0x2d 80096e2: 4a80 ldr r2, [pc, #512] @ (80098e4 <_printf_float+0x2d8>) 80096e4: bfb8 it lt 80096e6: f884 3043 strblt.w r3, [r4, #67] @ 0x43 80096ea: 4b7f ldr r3, [pc, #508] @ (80098e8 <_printf_float+0x2dc>) 80096ec: e7d3 b.n 8009696 <_printf_float+0x8a> 80096ee: 6863 ldr r3, [r4, #4] 80096f0: f00a 01df and.w r1, sl, #223 @ 0xdf 80096f4: 1c5a adds r2, r3, #1 80096f6: d13f bne.n 8009778 <_printf_float+0x16c> 80096f8: 2306 movs r3, #6 80096fa: 6063 str r3, [r4, #4] 80096fc: 2200 movs r2, #0 80096fe: f44b 6380 orr.w r3, fp, #1024 @ 0x400 8009702: 6023 str r3, [r4, #0] 8009704: 9206 str r2, [sp, #24] 8009706: aa0e add r2, sp, #56 @ 0x38 8009708: e9cd a204 strd sl, r2, [sp, #16] 800970c: aa0d add r2, sp, #52 @ 0x34 800970e: 9203 str r2, [sp, #12] 8009710: f10d 0233 add.w r2, sp, #51 @ 0x33 8009714: e9cd 3201 strd r3, r2, [sp, #4] 8009718: 6863 ldr r3, [r4, #4] 800971a: 4642 mov r2, r8 800971c: 9300 str r3, [sp, #0] 800971e: 4628 mov r0, r5 8009720: 464b mov r3, r9 8009722: 910a str r1, [sp, #40] @ 0x28 8009724: f7ff fed4 bl 80094d0 <__cvt> 8009728: 990a ldr r1, [sp, #40] @ 0x28 800972a: 4680 mov r8, r0 800972c: 2947 cmp r1, #71 @ 0x47 800972e: 990d ldr r1, [sp, #52] @ 0x34 8009730: d128 bne.n 8009784 <_printf_float+0x178> 8009732: 1cc8 adds r0, r1, #3 8009734: db02 blt.n 800973c <_printf_float+0x130> 8009736: 6863 ldr r3, [r4, #4] 8009738: 4299 cmp r1, r3 800973a: dd40 ble.n 80097be <_printf_float+0x1b2> 800973c: f1aa 0a02 sub.w sl, sl, #2 8009740: fa5f fa8a uxtb.w sl, sl 8009744: 4652 mov r2, sl 8009746: 3901 subs r1, #1 8009748: f104 0050 add.w r0, r4, #80 @ 0x50 800974c: 910d str r1, [sp, #52] @ 0x34 800974e: f7ff ff23 bl 8009598 <__exponent> 8009752: 9a0e ldr r2, [sp, #56] @ 0x38 8009754: 4681 mov r9, r0 8009756: 1813 adds r3, r2, r0 8009758: 2a01 cmp r2, #1 800975a: 6123 str r3, [r4, #16] 800975c: dc02 bgt.n 8009764 <_printf_float+0x158> 800975e: 6822 ldr r2, [r4, #0] 8009760: 07d2 lsls r2, r2, #31 8009762: d501 bpl.n 8009768 <_printf_float+0x15c> 8009764: 3301 adds r3, #1 8009766: 6123 str r3, [r4, #16] 8009768: f89d 3033 ldrb.w r3, [sp, #51] @ 0x33 800976c: 2b00 cmp r3, #0 800976e: d09e beq.n 80096ae <_printf_float+0xa2> 8009770: 232d movs r3, #45 @ 0x2d 8009772: f884 3043 strb.w r3, [r4, #67] @ 0x43 8009776: e79a b.n 80096ae <_printf_float+0xa2> 8009778: 2947 cmp r1, #71 @ 0x47 800977a: d1bf bne.n 80096fc <_printf_float+0xf0> 800977c: 2b00 cmp r3, #0 800977e: d1bd bne.n 80096fc <_printf_float+0xf0> 8009780: 2301 movs r3, #1 8009782: e7ba b.n 80096fa <_printf_float+0xee> 8009784: f1ba 0f65 cmp.w sl, #101 @ 0x65 8009788: d9dc bls.n 8009744 <_printf_float+0x138> 800978a: f1ba 0f66 cmp.w sl, #102 @ 0x66 800978e: d118 bne.n 80097c2 <_printf_float+0x1b6> 8009790: 2900 cmp r1, #0 8009792: 6863 ldr r3, [r4, #4] 8009794: dd0b ble.n 80097ae <_printf_float+0x1a2> 8009796: 6121 str r1, [r4, #16] 8009798: b913 cbnz r3, 80097a0 <_printf_float+0x194> 800979a: 6822 ldr r2, [r4, #0] 800979c: 07d0 lsls r0, r2, #31 800979e: d502 bpl.n 80097a6 <_printf_float+0x19a> 80097a0: 3301 adds r3, #1 80097a2: 440b add r3, r1 80097a4: 6123 str r3, [r4, #16] 80097a6: f04f 0900 mov.w r9, #0 80097aa: 65a1 str r1, [r4, #88] @ 0x58 80097ac: e7dc b.n 8009768 <_printf_float+0x15c> 80097ae: b913 cbnz r3, 80097b6 <_printf_float+0x1aa> 80097b0: 6822 ldr r2, [r4, #0] 80097b2: 07d2 lsls r2, r2, #31 80097b4: d501 bpl.n 80097ba <_printf_float+0x1ae> 80097b6: 3302 adds r3, #2 80097b8: e7f4 b.n 80097a4 <_printf_float+0x198> 80097ba: 2301 movs r3, #1 80097bc: e7f2 b.n 80097a4 <_printf_float+0x198> 80097be: f04f 0a67 mov.w sl, #103 @ 0x67 80097c2: 9b0e ldr r3, [sp, #56] @ 0x38 80097c4: 4299 cmp r1, r3 80097c6: db05 blt.n 80097d4 <_printf_float+0x1c8> 80097c8: 6823 ldr r3, [r4, #0] 80097ca: 6121 str r1, [r4, #16] 80097cc: 07d8 lsls r0, r3, #31 80097ce: d5ea bpl.n 80097a6 <_printf_float+0x19a> 80097d0: 1c4b adds r3, r1, #1 80097d2: e7e7 b.n 80097a4 <_printf_float+0x198> 80097d4: 2900 cmp r1, #0 80097d6: bfcc ite gt 80097d8: 2201 movgt r2, #1 80097da: f1c1 0202 rsble r2, r1, #2 80097de: 4413 add r3, r2 80097e0: e7e0 b.n 80097a4 <_printf_float+0x198> 80097e2: 6823 ldr r3, [r4, #0] 80097e4: 055a lsls r2, r3, #21 80097e6: d407 bmi.n 80097f8 <_printf_float+0x1ec> 80097e8: 6923 ldr r3, [r4, #16] 80097ea: 4642 mov r2, r8 80097ec: 4631 mov r1, r6 80097ee: 4628 mov r0, r5 80097f0: 47b8 blx r7 80097f2: 3001 adds r0, #1 80097f4: d12b bne.n 800984e <_printf_float+0x242> 80097f6: e764 b.n 80096c2 <_printf_float+0xb6> 80097f8: f1ba 0f65 cmp.w sl, #101 @ 0x65 80097fc: f240 80dc bls.w 80099b8 <_printf_float+0x3ac> 8009800: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 8009804: 2200 movs r2, #0 8009806: 2300 movs r3, #0 8009808: f7f7 f944 bl 8000a94 <__aeabi_dcmpeq> 800980c: 2800 cmp r0, #0 800980e: d033 beq.n 8009878 <_printf_float+0x26c> 8009810: 2301 movs r3, #1 8009812: 4631 mov r1, r6 8009814: 4628 mov r0, r5 8009816: 4a35 ldr r2, [pc, #212] @ (80098ec <_printf_float+0x2e0>) 8009818: 47b8 blx r7 800981a: 3001 adds r0, #1 800981c: f43f af51 beq.w 80096c2 <_printf_float+0xb6> 8009820: e9dd 380d ldrd r3, r8, [sp, #52] @ 0x34 8009824: 4543 cmp r3, r8 8009826: db02 blt.n 800982e <_printf_float+0x222> 8009828: 6823 ldr r3, [r4, #0] 800982a: 07d8 lsls r0, r3, #31 800982c: d50f bpl.n 800984e <_printf_float+0x242> 800982e: e9dd 2308 ldrd r2, r3, [sp, #32] 8009832: 4631 mov r1, r6 8009834: 4628 mov r0, r5 8009836: 47b8 blx r7 8009838: 3001 adds r0, #1 800983a: f43f af42 beq.w 80096c2 <_printf_float+0xb6> 800983e: f04f 0900 mov.w r9, #0 8009842: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 8009846: f104 0a1a add.w sl, r4, #26 800984a: 45c8 cmp r8, r9 800984c: dc09 bgt.n 8009862 <_printf_float+0x256> 800984e: 6823 ldr r3, [r4, #0] 8009850: 079b lsls r3, r3, #30 8009852: f100 8102 bmi.w 8009a5a <_printf_float+0x44e> 8009856: 68e0 ldr r0, [r4, #12] 8009858: 9b0f ldr r3, [sp, #60] @ 0x3c 800985a: 4298 cmp r0, r3 800985c: bfb8 it lt 800985e: 4618 movlt r0, r3 8009860: e731 b.n 80096c6 <_printf_float+0xba> 8009862: 2301 movs r3, #1 8009864: 4652 mov r2, sl 8009866: 4631 mov r1, r6 8009868: 4628 mov r0, r5 800986a: 47b8 blx r7 800986c: 3001 adds r0, #1 800986e: f43f af28 beq.w 80096c2 <_printf_float+0xb6> 8009872: f109 0901 add.w r9, r9, #1 8009876: e7e8 b.n 800984a <_printf_float+0x23e> 8009878: 9b0d ldr r3, [sp, #52] @ 0x34 800987a: 2b00 cmp r3, #0 800987c: dc38 bgt.n 80098f0 <_printf_float+0x2e4> 800987e: 2301 movs r3, #1 8009880: 4631 mov r1, r6 8009882: 4628 mov r0, r5 8009884: 4a19 ldr r2, [pc, #100] @ (80098ec <_printf_float+0x2e0>) 8009886: 47b8 blx r7 8009888: 3001 adds r0, #1 800988a: f43f af1a beq.w 80096c2 <_printf_float+0xb6> 800988e: e9dd 390d ldrd r3, r9, [sp, #52] @ 0x34 8009892: ea59 0303 orrs.w r3, r9, r3 8009896: d102 bne.n 800989e <_printf_float+0x292> 8009898: 6823 ldr r3, [r4, #0] 800989a: 07d9 lsls r1, r3, #31 800989c: d5d7 bpl.n 800984e <_printf_float+0x242> 800989e: e9dd 2308 ldrd r2, r3, [sp, #32] 80098a2: 4631 mov r1, r6 80098a4: 4628 mov r0, r5 80098a6: 47b8 blx r7 80098a8: 3001 adds r0, #1 80098aa: f43f af0a beq.w 80096c2 <_printf_float+0xb6> 80098ae: f04f 0a00 mov.w sl, #0 80098b2: f104 0b1a add.w fp, r4, #26 80098b6: 9b0d ldr r3, [sp, #52] @ 0x34 80098b8: 425b negs r3, r3 80098ba: 4553 cmp r3, sl 80098bc: dc01 bgt.n 80098c2 <_printf_float+0x2b6> 80098be: 464b mov r3, r9 80098c0: e793 b.n 80097ea <_printf_float+0x1de> 80098c2: 2301 movs r3, #1 80098c4: 465a mov r2, fp 80098c6: 4631 mov r1, r6 80098c8: 4628 mov r0, r5 80098ca: 47b8 blx r7 80098cc: 3001 adds r0, #1 80098ce: f43f aef8 beq.w 80096c2 <_printf_float+0xb6> 80098d2: f10a 0a01 add.w sl, sl, #1 80098d6: e7ee b.n 80098b6 <_printf_float+0x2aa> 80098d8: 7fefffff .word 0x7fefffff 80098dc: 0800dfb8 .word 0x0800dfb8 80098e0: 0800dfb4 .word 0x0800dfb4 80098e4: 0800dfc0 .word 0x0800dfc0 80098e8: 0800dfbc .word 0x0800dfbc 80098ec: 0800e238 .word 0x0800e238 80098f0: 6da3 ldr r3, [r4, #88] @ 0x58 80098f2: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 80098f6: 4553 cmp r3, sl 80098f8: bfa8 it ge 80098fa: 4653 movge r3, sl 80098fc: 2b00 cmp r3, #0 80098fe: 4699 mov r9, r3 8009900: dc36 bgt.n 8009970 <_printf_float+0x364> 8009902: f04f 0b00 mov.w fp, #0 8009906: ea29 79e9 bic.w r9, r9, r9, asr #31 800990a: f104 021a add.w r2, r4, #26 800990e: 6da3 ldr r3, [r4, #88] @ 0x58 8009910: 930a str r3, [sp, #40] @ 0x28 8009912: eba3 0309 sub.w r3, r3, r9 8009916: 455b cmp r3, fp 8009918: dc31 bgt.n 800997e <_printf_float+0x372> 800991a: 9b0d ldr r3, [sp, #52] @ 0x34 800991c: 459a cmp sl, r3 800991e: dc3a bgt.n 8009996 <_printf_float+0x38a> 8009920: 6823 ldr r3, [r4, #0] 8009922: 07da lsls r2, r3, #31 8009924: d437 bmi.n 8009996 <_printf_float+0x38a> 8009926: 9b0d ldr r3, [sp, #52] @ 0x34 8009928: ebaa 0903 sub.w r9, sl, r3 800992c: 9b0a ldr r3, [sp, #40] @ 0x28 800992e: ebaa 0303 sub.w r3, sl, r3 8009932: 4599 cmp r9, r3 8009934: bfa8 it ge 8009936: 4699 movge r9, r3 8009938: f1b9 0f00 cmp.w r9, #0 800993c: dc33 bgt.n 80099a6 <_printf_float+0x39a> 800993e: f04f 0800 mov.w r8, #0 8009942: ea29 79e9 bic.w r9, r9, r9, asr #31 8009946: f104 0b1a add.w fp, r4, #26 800994a: 9b0d ldr r3, [sp, #52] @ 0x34 800994c: ebaa 0303 sub.w r3, sl, r3 8009950: eba3 0309 sub.w r3, r3, r9 8009954: 4543 cmp r3, r8 8009956: f77f af7a ble.w 800984e <_printf_float+0x242> 800995a: 2301 movs r3, #1 800995c: 465a mov r2, fp 800995e: 4631 mov r1, r6 8009960: 4628 mov r0, r5 8009962: 47b8 blx r7 8009964: 3001 adds r0, #1 8009966: f43f aeac beq.w 80096c2 <_printf_float+0xb6> 800996a: f108 0801 add.w r8, r8, #1 800996e: e7ec b.n 800994a <_printf_float+0x33e> 8009970: 4642 mov r2, r8 8009972: 4631 mov r1, r6 8009974: 4628 mov r0, r5 8009976: 47b8 blx r7 8009978: 3001 adds r0, #1 800997a: d1c2 bne.n 8009902 <_printf_float+0x2f6> 800997c: e6a1 b.n 80096c2 <_printf_float+0xb6> 800997e: 2301 movs r3, #1 8009980: 4631 mov r1, r6 8009982: 4628 mov r0, r5 8009984: 920a str r2, [sp, #40] @ 0x28 8009986: 47b8 blx r7 8009988: 3001 adds r0, #1 800998a: f43f ae9a beq.w 80096c2 <_printf_float+0xb6> 800998e: 9a0a ldr r2, [sp, #40] @ 0x28 8009990: f10b 0b01 add.w fp, fp, #1 8009994: e7bb b.n 800990e <_printf_float+0x302> 8009996: 4631 mov r1, r6 8009998: e9dd 2308 ldrd r2, r3, [sp, #32] 800999c: 4628 mov r0, r5 800999e: 47b8 blx r7 80099a0: 3001 adds r0, #1 80099a2: d1c0 bne.n 8009926 <_printf_float+0x31a> 80099a4: e68d b.n 80096c2 <_printf_float+0xb6> 80099a6: 9a0a ldr r2, [sp, #40] @ 0x28 80099a8: 464b mov r3, r9 80099aa: 4631 mov r1, r6 80099ac: 4628 mov r0, r5 80099ae: 4442 add r2, r8 80099b0: 47b8 blx r7 80099b2: 3001 adds r0, #1 80099b4: d1c3 bne.n 800993e <_printf_float+0x332> 80099b6: e684 b.n 80096c2 <_printf_float+0xb6> 80099b8: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 80099bc: f1ba 0f01 cmp.w sl, #1 80099c0: dc01 bgt.n 80099c6 <_printf_float+0x3ba> 80099c2: 07db lsls r3, r3, #31 80099c4: d536 bpl.n 8009a34 <_printf_float+0x428> 80099c6: 2301 movs r3, #1 80099c8: 4642 mov r2, r8 80099ca: 4631 mov r1, r6 80099cc: 4628 mov r0, r5 80099ce: 47b8 blx r7 80099d0: 3001 adds r0, #1 80099d2: f43f ae76 beq.w 80096c2 <_printf_float+0xb6> 80099d6: e9dd 2308 ldrd r2, r3, [sp, #32] 80099da: 4631 mov r1, r6 80099dc: 4628 mov r0, r5 80099de: 47b8 blx r7 80099e0: 3001 adds r0, #1 80099e2: f43f ae6e beq.w 80096c2 <_printf_float+0xb6> 80099e6: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 80099ea: 2200 movs r2, #0 80099ec: 2300 movs r3, #0 80099ee: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff 80099f2: f7f7 f84f bl 8000a94 <__aeabi_dcmpeq> 80099f6: b9c0 cbnz r0, 8009a2a <_printf_float+0x41e> 80099f8: 4653 mov r3, sl 80099fa: f108 0201 add.w r2, r8, #1 80099fe: 4631 mov r1, r6 8009a00: 4628 mov r0, r5 8009a02: 47b8 blx r7 8009a04: 3001 adds r0, #1 8009a06: d10c bne.n 8009a22 <_printf_float+0x416> 8009a08: e65b b.n 80096c2 <_printf_float+0xb6> 8009a0a: 2301 movs r3, #1 8009a0c: 465a mov r2, fp 8009a0e: 4631 mov r1, r6 8009a10: 4628 mov r0, r5 8009a12: 47b8 blx r7 8009a14: 3001 adds r0, #1 8009a16: f43f ae54 beq.w 80096c2 <_printf_float+0xb6> 8009a1a: f108 0801 add.w r8, r8, #1 8009a1e: 45d0 cmp r8, sl 8009a20: dbf3 blt.n 8009a0a <_printf_float+0x3fe> 8009a22: 464b mov r3, r9 8009a24: f104 0250 add.w r2, r4, #80 @ 0x50 8009a28: e6e0 b.n 80097ec <_printf_float+0x1e0> 8009a2a: f04f 0800 mov.w r8, #0 8009a2e: f104 0b1a add.w fp, r4, #26 8009a32: e7f4 b.n 8009a1e <_printf_float+0x412> 8009a34: 2301 movs r3, #1 8009a36: 4642 mov r2, r8 8009a38: e7e1 b.n 80099fe <_printf_float+0x3f2> 8009a3a: 2301 movs r3, #1 8009a3c: 464a mov r2, r9 8009a3e: 4631 mov r1, r6 8009a40: 4628 mov r0, r5 8009a42: 47b8 blx r7 8009a44: 3001 adds r0, #1 8009a46: f43f ae3c beq.w 80096c2 <_printf_float+0xb6> 8009a4a: f108 0801 add.w r8, r8, #1 8009a4e: 68e3 ldr r3, [r4, #12] 8009a50: 990f ldr r1, [sp, #60] @ 0x3c 8009a52: 1a5b subs r3, r3, r1 8009a54: 4543 cmp r3, r8 8009a56: dcf0 bgt.n 8009a3a <_printf_float+0x42e> 8009a58: e6fd b.n 8009856 <_printf_float+0x24a> 8009a5a: f04f 0800 mov.w r8, #0 8009a5e: f104 0919 add.w r9, r4, #25 8009a62: e7f4 b.n 8009a4e <_printf_float+0x442> 08009a64 <_printf_common>: 8009a64: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8009a68: 4616 mov r6, r2 8009a6a: 4698 mov r8, r3 8009a6c: 688a ldr r2, [r1, #8] 8009a6e: 690b ldr r3, [r1, #16] 8009a70: 4607 mov r7, r0 8009a72: 4293 cmp r3, r2 8009a74: bfb8 it lt 8009a76: 4613 movlt r3, r2 8009a78: 6033 str r3, [r6, #0] 8009a7a: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 8009a7e: 460c mov r4, r1 8009a80: f8dd 9020 ldr.w r9, [sp, #32] 8009a84: b10a cbz r2, 8009a8a <_printf_common+0x26> 8009a86: 3301 adds r3, #1 8009a88: 6033 str r3, [r6, #0] 8009a8a: 6823 ldr r3, [r4, #0] 8009a8c: 0699 lsls r1, r3, #26 8009a8e: bf42 ittt mi 8009a90: 6833 ldrmi r3, [r6, #0] 8009a92: 3302 addmi r3, #2 8009a94: 6033 strmi r3, [r6, #0] 8009a96: 6825 ldr r5, [r4, #0] 8009a98: f015 0506 ands.w r5, r5, #6 8009a9c: d106 bne.n 8009aac <_printf_common+0x48> 8009a9e: f104 0a19 add.w sl, r4, #25 8009aa2: 68e3 ldr r3, [r4, #12] 8009aa4: 6832 ldr r2, [r6, #0] 8009aa6: 1a9b subs r3, r3, r2 8009aa8: 42ab cmp r3, r5 8009aaa: dc2b bgt.n 8009b04 <_printf_common+0xa0> 8009aac: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 8009ab0: 6822 ldr r2, [r4, #0] 8009ab2: 3b00 subs r3, #0 8009ab4: bf18 it ne 8009ab6: 2301 movne r3, #1 8009ab8: 0692 lsls r2, r2, #26 8009aba: d430 bmi.n 8009b1e <_printf_common+0xba> 8009abc: 4641 mov r1, r8 8009abe: 4638 mov r0, r7 8009ac0: f104 0243 add.w r2, r4, #67 @ 0x43 8009ac4: 47c8 blx r9 8009ac6: 3001 adds r0, #1 8009ac8: d023 beq.n 8009b12 <_printf_common+0xae> 8009aca: 6823 ldr r3, [r4, #0] 8009acc: 6922 ldr r2, [r4, #16] 8009ace: f003 0306 and.w r3, r3, #6 8009ad2: 2b04 cmp r3, #4 8009ad4: bf14 ite ne 8009ad6: 2500 movne r5, #0 8009ad8: 6833 ldreq r3, [r6, #0] 8009ada: f04f 0600 mov.w r6, #0 8009ade: bf08 it eq 8009ae0: 68e5 ldreq r5, [r4, #12] 8009ae2: f104 041a add.w r4, r4, #26 8009ae6: bf08 it eq 8009ae8: 1aed subeq r5, r5, r3 8009aea: f854 3c12 ldr.w r3, [r4, #-18] 8009aee: bf08 it eq 8009af0: ea25 75e5 biceq.w r5, r5, r5, asr #31 8009af4: 4293 cmp r3, r2 8009af6: bfc4 itt gt 8009af8: 1a9b subgt r3, r3, r2 8009afa: 18ed addgt r5, r5, r3 8009afc: 42b5 cmp r5, r6 8009afe: d11a bne.n 8009b36 <_printf_common+0xd2> 8009b00: 2000 movs r0, #0 8009b02: e008 b.n 8009b16 <_printf_common+0xb2> 8009b04: 2301 movs r3, #1 8009b06: 4652 mov r2, sl 8009b08: 4641 mov r1, r8 8009b0a: 4638 mov r0, r7 8009b0c: 47c8 blx r9 8009b0e: 3001 adds r0, #1 8009b10: d103 bne.n 8009b1a <_printf_common+0xb6> 8009b12: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8009b16: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8009b1a: 3501 adds r5, #1 8009b1c: e7c1 b.n 8009aa2 <_printf_common+0x3e> 8009b1e: 2030 movs r0, #48 @ 0x30 8009b20: 18e1 adds r1, r4, r3 8009b22: f881 0043 strb.w r0, [r1, #67] @ 0x43 8009b26: 1c5a adds r2, r3, #1 8009b28: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 8009b2c: 4422 add r2, r4 8009b2e: 3302 adds r3, #2 8009b30: f882 1043 strb.w r1, [r2, #67] @ 0x43 8009b34: e7c2 b.n 8009abc <_printf_common+0x58> 8009b36: 2301 movs r3, #1 8009b38: 4622 mov r2, r4 8009b3a: 4641 mov r1, r8 8009b3c: 4638 mov r0, r7 8009b3e: 47c8 blx r9 8009b40: 3001 adds r0, #1 8009b42: d0e6 beq.n 8009b12 <_printf_common+0xae> 8009b44: 3601 adds r6, #1 8009b46: e7d9 b.n 8009afc <_printf_common+0x98> 08009b48 <_printf_i>: 8009b48: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8009b4c: 7e0f ldrb r7, [r1, #24] 8009b4e: 4691 mov r9, r2 8009b50: 2f78 cmp r7, #120 @ 0x78 8009b52: 4680 mov r8, r0 8009b54: 460c mov r4, r1 8009b56: 469a mov sl, r3 8009b58: 9e0c ldr r6, [sp, #48] @ 0x30 8009b5a: f101 0243 add.w r2, r1, #67 @ 0x43 8009b5e: d807 bhi.n 8009b70 <_printf_i+0x28> 8009b60: 2f62 cmp r7, #98 @ 0x62 8009b62: d80a bhi.n 8009b7a <_printf_i+0x32> 8009b64: 2f00 cmp r7, #0 8009b66: f000 80d1 beq.w 8009d0c <_printf_i+0x1c4> 8009b6a: 2f58 cmp r7, #88 @ 0x58 8009b6c: f000 80b8 beq.w 8009ce0 <_printf_i+0x198> 8009b70: f104 0642 add.w r6, r4, #66 @ 0x42 8009b74: f884 7042 strb.w r7, [r4, #66] @ 0x42 8009b78: e03a b.n 8009bf0 <_printf_i+0xa8> 8009b7a: f1a7 0363 sub.w r3, r7, #99 @ 0x63 8009b7e: 2b15 cmp r3, #21 8009b80: d8f6 bhi.n 8009b70 <_printf_i+0x28> 8009b82: a101 add r1, pc, #4 @ (adr r1, 8009b88 <_printf_i+0x40>) 8009b84: f851 f023 ldr.w pc, [r1, r3, lsl #2] 8009b88: 08009be1 .word 0x08009be1 8009b8c: 08009bf5 .word 0x08009bf5 8009b90: 08009b71 .word 0x08009b71 8009b94: 08009b71 .word 0x08009b71 8009b98: 08009b71 .word 0x08009b71 8009b9c: 08009b71 .word 0x08009b71 8009ba0: 08009bf5 .word 0x08009bf5 8009ba4: 08009b71 .word 0x08009b71 8009ba8: 08009b71 .word 0x08009b71 8009bac: 08009b71 .word 0x08009b71 8009bb0: 08009b71 .word 0x08009b71 8009bb4: 08009cf3 .word 0x08009cf3 8009bb8: 08009c1f .word 0x08009c1f 8009bbc: 08009cad .word 0x08009cad 8009bc0: 08009b71 .word 0x08009b71 8009bc4: 08009b71 .word 0x08009b71 8009bc8: 08009d15 .word 0x08009d15 8009bcc: 08009b71 .word 0x08009b71 8009bd0: 08009c1f .word 0x08009c1f 8009bd4: 08009b71 .word 0x08009b71 8009bd8: 08009b71 .word 0x08009b71 8009bdc: 08009cb5 .word 0x08009cb5 8009be0: 6833 ldr r3, [r6, #0] 8009be2: 1d1a adds r2, r3, #4 8009be4: 681b ldr r3, [r3, #0] 8009be6: 6032 str r2, [r6, #0] 8009be8: f104 0642 add.w r6, r4, #66 @ 0x42 8009bec: f884 3042 strb.w r3, [r4, #66] @ 0x42 8009bf0: 2301 movs r3, #1 8009bf2: e09c b.n 8009d2e <_printf_i+0x1e6> 8009bf4: 6833 ldr r3, [r6, #0] 8009bf6: 6820 ldr r0, [r4, #0] 8009bf8: 1d19 adds r1, r3, #4 8009bfa: 6031 str r1, [r6, #0] 8009bfc: 0606 lsls r6, r0, #24 8009bfe: d501 bpl.n 8009c04 <_printf_i+0xbc> 8009c00: 681d ldr r5, [r3, #0] 8009c02: e003 b.n 8009c0c <_printf_i+0xc4> 8009c04: 0645 lsls r5, r0, #25 8009c06: d5fb bpl.n 8009c00 <_printf_i+0xb8> 8009c08: f9b3 5000 ldrsh.w r5, [r3] 8009c0c: 2d00 cmp r5, #0 8009c0e: da03 bge.n 8009c18 <_printf_i+0xd0> 8009c10: 232d movs r3, #45 @ 0x2d 8009c12: 426d negs r5, r5 8009c14: f884 3043 strb.w r3, [r4, #67] @ 0x43 8009c18: 230a movs r3, #10 8009c1a: 4858 ldr r0, [pc, #352] @ (8009d7c <_printf_i+0x234>) 8009c1c: e011 b.n 8009c42 <_printf_i+0xfa> 8009c1e: 6821 ldr r1, [r4, #0] 8009c20: 6833 ldr r3, [r6, #0] 8009c22: 0608 lsls r0, r1, #24 8009c24: f853 5b04 ldr.w r5, [r3], #4 8009c28: d402 bmi.n 8009c30 <_printf_i+0xe8> 8009c2a: 0649 lsls r1, r1, #25 8009c2c: bf48 it mi 8009c2e: b2ad uxthmi r5, r5 8009c30: 2f6f cmp r7, #111 @ 0x6f 8009c32: 6033 str r3, [r6, #0] 8009c34: bf14 ite ne 8009c36: 230a movne r3, #10 8009c38: 2308 moveq r3, #8 8009c3a: 4850 ldr r0, [pc, #320] @ (8009d7c <_printf_i+0x234>) 8009c3c: 2100 movs r1, #0 8009c3e: f884 1043 strb.w r1, [r4, #67] @ 0x43 8009c42: 6866 ldr r6, [r4, #4] 8009c44: 2e00 cmp r6, #0 8009c46: 60a6 str r6, [r4, #8] 8009c48: db05 blt.n 8009c56 <_printf_i+0x10e> 8009c4a: 6821 ldr r1, [r4, #0] 8009c4c: 432e orrs r6, r5 8009c4e: f021 0104 bic.w r1, r1, #4 8009c52: 6021 str r1, [r4, #0] 8009c54: d04b beq.n 8009cee <_printf_i+0x1a6> 8009c56: 4616 mov r6, r2 8009c58: fbb5 f1f3 udiv r1, r5, r3 8009c5c: fb03 5711 mls r7, r3, r1, r5 8009c60: 5dc7 ldrb r7, [r0, r7] 8009c62: f806 7d01 strb.w r7, [r6, #-1]! 8009c66: 462f mov r7, r5 8009c68: 42bb cmp r3, r7 8009c6a: 460d mov r5, r1 8009c6c: d9f4 bls.n 8009c58 <_printf_i+0x110> 8009c6e: 2b08 cmp r3, #8 8009c70: d10b bne.n 8009c8a <_printf_i+0x142> 8009c72: 6823 ldr r3, [r4, #0] 8009c74: 07df lsls r7, r3, #31 8009c76: d508 bpl.n 8009c8a <_printf_i+0x142> 8009c78: 6923 ldr r3, [r4, #16] 8009c7a: 6861 ldr r1, [r4, #4] 8009c7c: 4299 cmp r1, r3 8009c7e: bfde ittt le 8009c80: 2330 movle r3, #48 @ 0x30 8009c82: f806 3c01 strble.w r3, [r6, #-1] 8009c86: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 8009c8a: 1b92 subs r2, r2, r6 8009c8c: 6122 str r2, [r4, #16] 8009c8e: 464b mov r3, r9 8009c90: 4621 mov r1, r4 8009c92: 4640 mov r0, r8 8009c94: f8cd a000 str.w sl, [sp] 8009c98: aa03 add r2, sp, #12 8009c9a: f7ff fee3 bl 8009a64 <_printf_common> 8009c9e: 3001 adds r0, #1 8009ca0: d14a bne.n 8009d38 <_printf_i+0x1f0> 8009ca2: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8009ca6: b004 add sp, #16 8009ca8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8009cac: 6823 ldr r3, [r4, #0] 8009cae: f043 0320 orr.w r3, r3, #32 8009cb2: 6023 str r3, [r4, #0] 8009cb4: 2778 movs r7, #120 @ 0x78 8009cb6: 4832 ldr r0, [pc, #200] @ (8009d80 <_printf_i+0x238>) 8009cb8: f884 7045 strb.w r7, [r4, #69] @ 0x45 8009cbc: 6823 ldr r3, [r4, #0] 8009cbe: 6831 ldr r1, [r6, #0] 8009cc0: 061f lsls r7, r3, #24 8009cc2: f851 5b04 ldr.w r5, [r1], #4 8009cc6: d402 bmi.n 8009cce <_printf_i+0x186> 8009cc8: 065f lsls r7, r3, #25 8009cca: bf48 it mi 8009ccc: b2ad uxthmi r5, r5 8009cce: 6031 str r1, [r6, #0] 8009cd0: 07d9 lsls r1, r3, #31 8009cd2: bf44 itt mi 8009cd4: f043 0320 orrmi.w r3, r3, #32 8009cd8: 6023 strmi r3, [r4, #0] 8009cda: b11d cbz r5, 8009ce4 <_printf_i+0x19c> 8009cdc: 2310 movs r3, #16 8009cde: e7ad b.n 8009c3c <_printf_i+0xf4> 8009ce0: 4826 ldr r0, [pc, #152] @ (8009d7c <_printf_i+0x234>) 8009ce2: e7e9 b.n 8009cb8 <_printf_i+0x170> 8009ce4: 6823 ldr r3, [r4, #0] 8009ce6: f023 0320 bic.w r3, r3, #32 8009cea: 6023 str r3, [r4, #0] 8009cec: e7f6 b.n 8009cdc <_printf_i+0x194> 8009cee: 4616 mov r6, r2 8009cf0: e7bd b.n 8009c6e <_printf_i+0x126> 8009cf2: 6833 ldr r3, [r6, #0] 8009cf4: 6825 ldr r5, [r4, #0] 8009cf6: 1d18 adds r0, r3, #4 8009cf8: 6961 ldr r1, [r4, #20] 8009cfa: 6030 str r0, [r6, #0] 8009cfc: 062e lsls r6, r5, #24 8009cfe: 681b ldr r3, [r3, #0] 8009d00: d501 bpl.n 8009d06 <_printf_i+0x1be> 8009d02: 6019 str r1, [r3, #0] 8009d04: e002 b.n 8009d0c <_printf_i+0x1c4> 8009d06: 0668 lsls r0, r5, #25 8009d08: d5fb bpl.n 8009d02 <_printf_i+0x1ba> 8009d0a: 8019 strh r1, [r3, #0] 8009d0c: 2300 movs r3, #0 8009d0e: 4616 mov r6, r2 8009d10: 6123 str r3, [r4, #16] 8009d12: e7bc b.n 8009c8e <_printf_i+0x146> 8009d14: 6833 ldr r3, [r6, #0] 8009d16: 2100 movs r1, #0 8009d18: 1d1a adds r2, r3, #4 8009d1a: 6032 str r2, [r6, #0] 8009d1c: 681e ldr r6, [r3, #0] 8009d1e: 6862 ldr r2, [r4, #4] 8009d20: 4630 mov r0, r6 8009d22: f000 fee5 bl 800aaf0 8009d26: b108 cbz r0, 8009d2c <_printf_i+0x1e4> 8009d28: 1b80 subs r0, r0, r6 8009d2a: 6060 str r0, [r4, #4] 8009d2c: 6863 ldr r3, [r4, #4] 8009d2e: 6123 str r3, [r4, #16] 8009d30: 2300 movs r3, #0 8009d32: f884 3043 strb.w r3, [r4, #67] @ 0x43 8009d36: e7aa b.n 8009c8e <_printf_i+0x146> 8009d38: 4632 mov r2, r6 8009d3a: 4649 mov r1, r9 8009d3c: 4640 mov r0, r8 8009d3e: 6923 ldr r3, [r4, #16] 8009d40: 47d0 blx sl 8009d42: 3001 adds r0, #1 8009d44: d0ad beq.n 8009ca2 <_printf_i+0x15a> 8009d46: 6823 ldr r3, [r4, #0] 8009d48: 079b lsls r3, r3, #30 8009d4a: d413 bmi.n 8009d74 <_printf_i+0x22c> 8009d4c: 68e0 ldr r0, [r4, #12] 8009d4e: 9b03 ldr r3, [sp, #12] 8009d50: 4298 cmp r0, r3 8009d52: bfb8 it lt 8009d54: 4618 movlt r0, r3 8009d56: e7a6 b.n 8009ca6 <_printf_i+0x15e> 8009d58: 2301 movs r3, #1 8009d5a: 4632 mov r2, r6 8009d5c: 4649 mov r1, r9 8009d5e: 4640 mov r0, r8 8009d60: 47d0 blx sl 8009d62: 3001 adds r0, #1 8009d64: d09d beq.n 8009ca2 <_printf_i+0x15a> 8009d66: 3501 adds r5, #1 8009d68: 68e3 ldr r3, [r4, #12] 8009d6a: 9903 ldr r1, [sp, #12] 8009d6c: 1a5b subs r3, r3, r1 8009d6e: 42ab cmp r3, r5 8009d70: dcf2 bgt.n 8009d58 <_printf_i+0x210> 8009d72: e7eb b.n 8009d4c <_printf_i+0x204> 8009d74: 2500 movs r5, #0 8009d76: f104 0619 add.w r6, r4, #25 8009d7a: e7f5 b.n 8009d68 <_printf_i+0x220> 8009d7c: 0800dfc4 .word 0x0800dfc4 8009d80: 0800dfd5 .word 0x0800dfd5 08009d84 : 8009d84: b40c push {r2, r3} 8009d86: b530 push {r4, r5, lr} 8009d88: 4b18 ldr r3, [pc, #96] @ (8009dec ) 8009d8a: 1e0c subs r4, r1, #0 8009d8c: 681d ldr r5, [r3, #0] 8009d8e: b09d sub sp, #116 @ 0x74 8009d90: da08 bge.n 8009da4 8009d92: 238b movs r3, #139 @ 0x8b 8009d94: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8009d98: 602b str r3, [r5, #0] 8009d9a: b01d add sp, #116 @ 0x74 8009d9c: e8bd 4030 ldmia.w sp!, {r4, r5, lr} 8009da0: b002 add sp, #8 8009da2: 4770 bx lr 8009da4: f44f 7302 mov.w r3, #520 @ 0x208 8009da8: f8ad 3014 strh.w r3, [sp, #20] 8009dac: f04f 0300 mov.w r3, #0 8009db0: 931b str r3, [sp, #108] @ 0x6c 8009db2: bf0c ite eq 8009db4: 4623 moveq r3, r4 8009db6: f104 33ff addne.w r3, r4, #4294967295 @ 0xffffffff 8009dba: 9304 str r3, [sp, #16] 8009dbc: 9307 str r3, [sp, #28] 8009dbe: f64f 73ff movw r3, #65535 @ 0xffff 8009dc2: 9002 str r0, [sp, #8] 8009dc4: 9006 str r0, [sp, #24] 8009dc6: f8ad 3016 strh.w r3, [sp, #22] 8009dca: 4628 mov r0, r5 8009dcc: ab21 add r3, sp, #132 @ 0x84 8009dce: 9a20 ldr r2, [sp, #128] @ 0x80 8009dd0: a902 add r1, sp, #8 8009dd2: 9301 str r3, [sp, #4] 8009dd4: f001 fdc2 bl 800b95c <_svfiprintf_r> 8009dd8: 1c43 adds r3, r0, #1 8009dda: bfbc itt lt 8009ddc: 238b movlt r3, #139 @ 0x8b 8009dde: 602b strlt r3, [r5, #0] 8009de0: 2c00 cmp r4, #0 8009de2: d0da beq.n 8009d9a 8009de4: 2200 movs r2, #0 8009de6: 9b02 ldr r3, [sp, #8] 8009de8: 701a strb r2, [r3, #0] 8009dea: e7d6 b.n 8009d9a 8009dec: 20000038 .word 0x20000038 08009df0 : 8009df0: 2300 movs r3, #0 8009df2: b510 push {r4, lr} 8009df4: 4604 mov r4, r0 8009df6: e9c0 3300 strd r3, r3, [r0] 8009dfa: e9c0 3304 strd r3, r3, [r0, #16] 8009dfe: 6083 str r3, [r0, #8] 8009e00: 8181 strh r1, [r0, #12] 8009e02: 6643 str r3, [r0, #100] @ 0x64 8009e04: 81c2 strh r2, [r0, #14] 8009e06: 6183 str r3, [r0, #24] 8009e08: 4619 mov r1, r3 8009e0a: 2208 movs r2, #8 8009e0c: 305c adds r0, #92 @ 0x5c 8009e0e: f000 f95d bl 800a0cc 8009e12: 4b0d ldr r3, [pc, #52] @ (8009e48 ) 8009e14: 6224 str r4, [r4, #32] 8009e16: 6263 str r3, [r4, #36] @ 0x24 8009e18: 4b0c ldr r3, [pc, #48] @ (8009e4c ) 8009e1a: 62a3 str r3, [r4, #40] @ 0x28 8009e1c: 4b0c ldr r3, [pc, #48] @ (8009e50 ) 8009e1e: 62e3 str r3, [r4, #44] @ 0x2c 8009e20: 4b0c ldr r3, [pc, #48] @ (8009e54 ) 8009e22: 6323 str r3, [r4, #48] @ 0x30 8009e24: 4b0c ldr r3, [pc, #48] @ (8009e58 ) 8009e26: 429c cmp r4, r3 8009e28: d006 beq.n 8009e38 8009e2a: f103 0268 add.w r2, r3, #104 @ 0x68 8009e2e: 4294 cmp r4, r2 8009e30: d002 beq.n 8009e38 8009e32: 33d0 adds r3, #208 @ 0xd0 8009e34: 429c cmp r4, r3 8009e36: d105 bne.n 8009e44 8009e38: f104 0058 add.w r0, r4, #88 @ 0x58 8009e3c: e8bd 4010 ldmia.w sp!, {r4, lr} 8009e40: f000 bc20 b.w 800a684 <__retarget_lock_init_recursive> 8009e44: bd10 pop {r4, pc} 8009e46: bf00 nop 8009e48: 0800c7ed .word 0x0800c7ed 8009e4c: 0800c813 .word 0x0800c813 8009e50: 0800c84b .word 0x0800c84b 8009e54: 0800c86f .word 0x0800c86f 8009e58: 200033ac .word 0x200033ac 08009e5c : 8009e5c: 4a02 ldr r2, [pc, #8] @ (8009e68 ) 8009e5e: 4903 ldr r1, [pc, #12] @ (8009e6c ) 8009e60: 4803 ldr r0, [pc, #12] @ (8009e70 ) 8009e62: f000 b8a5 b.w 8009fb0 <_fwalk_sglue> 8009e66: bf00 nop 8009e68: 20000024 .word 0x20000024 8009e6c: 0800c039 .word 0x0800c039 8009e70: 2000003c .word 0x2000003c 08009e74 : 8009e74: 6841 ldr r1, [r0, #4] 8009e76: 4b0c ldr r3, [pc, #48] @ (8009ea8 ) 8009e78: b510 push {r4, lr} 8009e7a: 4299 cmp r1, r3 8009e7c: 4604 mov r4, r0 8009e7e: d001 beq.n 8009e84 8009e80: f002 f8da bl 800c038 <_fflush_r> 8009e84: 68a1 ldr r1, [r4, #8] 8009e86: 4b09 ldr r3, [pc, #36] @ (8009eac ) 8009e88: 4299 cmp r1, r3 8009e8a: d002 beq.n 8009e92 8009e8c: 4620 mov r0, r4 8009e8e: f002 f8d3 bl 800c038 <_fflush_r> 8009e92: 68e1 ldr r1, [r4, #12] 8009e94: 4b06 ldr r3, [pc, #24] @ (8009eb0 ) 8009e96: 4299 cmp r1, r3 8009e98: d004 beq.n 8009ea4 8009e9a: 4620 mov r0, r4 8009e9c: e8bd 4010 ldmia.w sp!, {r4, lr} 8009ea0: f002 b8ca b.w 800c038 <_fflush_r> 8009ea4: bd10 pop {r4, pc} 8009ea6: bf00 nop 8009ea8: 200033ac .word 0x200033ac 8009eac: 20003414 .word 0x20003414 8009eb0: 2000347c .word 0x2000347c 08009eb4 : 8009eb4: b510 push {r4, lr} 8009eb6: 4b0b ldr r3, [pc, #44] @ (8009ee4 ) 8009eb8: 4c0b ldr r4, [pc, #44] @ (8009ee8 ) 8009eba: 4a0c ldr r2, [pc, #48] @ (8009eec ) 8009ebc: 4620 mov r0, r4 8009ebe: 601a str r2, [r3, #0] 8009ec0: 2104 movs r1, #4 8009ec2: 2200 movs r2, #0 8009ec4: f7ff ff94 bl 8009df0 8009ec8: f104 0068 add.w r0, r4, #104 @ 0x68 8009ecc: 2201 movs r2, #1 8009ece: 2109 movs r1, #9 8009ed0: f7ff ff8e bl 8009df0 8009ed4: f104 00d0 add.w r0, r4, #208 @ 0xd0 8009ed8: 2202 movs r2, #2 8009eda: e8bd 4010 ldmia.w sp!, {r4, lr} 8009ede: 2112 movs r1, #18 8009ee0: f7ff bf86 b.w 8009df0 8009ee4: 200034e4 .word 0x200034e4 8009ee8: 200033ac .word 0x200033ac 8009eec: 08009e5d .word 0x08009e5d 08009ef0 <__sfp_lock_acquire>: 8009ef0: 4801 ldr r0, [pc, #4] @ (8009ef8 <__sfp_lock_acquire+0x8>) 8009ef2: f000 bbc9 b.w 800a688 <__retarget_lock_acquire_recursive> 8009ef6: bf00 nop 8009ef8: 200034eb .word 0x200034eb 08009efc <__sfp_lock_release>: 8009efc: 4801 ldr r0, [pc, #4] @ (8009f04 <__sfp_lock_release+0x8>) 8009efe: f000 bbc5 b.w 800a68c <__retarget_lock_release_recursive> 8009f02: bf00 nop 8009f04: 200034eb .word 0x200034eb 08009f08 <__sinit>: 8009f08: b510 push {r4, lr} 8009f0a: 4604 mov r4, r0 8009f0c: f7ff fff0 bl 8009ef0 <__sfp_lock_acquire> 8009f10: 6a23 ldr r3, [r4, #32] 8009f12: b11b cbz r3, 8009f1c <__sinit+0x14> 8009f14: e8bd 4010 ldmia.w sp!, {r4, lr} 8009f18: f7ff bff0 b.w 8009efc <__sfp_lock_release> 8009f1c: 4b04 ldr r3, [pc, #16] @ (8009f30 <__sinit+0x28>) 8009f1e: 6223 str r3, [r4, #32] 8009f20: 4b04 ldr r3, [pc, #16] @ (8009f34 <__sinit+0x2c>) 8009f22: 681b ldr r3, [r3, #0] 8009f24: 2b00 cmp r3, #0 8009f26: d1f5 bne.n 8009f14 <__sinit+0xc> 8009f28: f7ff ffc4 bl 8009eb4 8009f2c: e7f2 b.n 8009f14 <__sinit+0xc> 8009f2e: bf00 nop 8009f30: 08009e75 .word 0x08009e75 8009f34: 200034e4 .word 0x200034e4 08009f38 <_vsniprintf_r>: 8009f38: b530 push {r4, r5, lr} 8009f3a: 4614 mov r4, r2 8009f3c: 2c00 cmp r4, #0 8009f3e: 4605 mov r5, r0 8009f40: 461a mov r2, r3 8009f42: b09b sub sp, #108 @ 0x6c 8009f44: da05 bge.n 8009f52 <_vsniprintf_r+0x1a> 8009f46: 238b movs r3, #139 @ 0x8b 8009f48: 6003 str r3, [r0, #0] 8009f4a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8009f4e: b01b add sp, #108 @ 0x6c 8009f50: bd30 pop {r4, r5, pc} 8009f52: f44f 7302 mov.w r3, #520 @ 0x208 8009f56: f8ad 300c strh.w r3, [sp, #12] 8009f5a: f04f 0300 mov.w r3, #0 8009f5e: 9319 str r3, [sp, #100] @ 0x64 8009f60: bf0c ite eq 8009f62: 4623 moveq r3, r4 8009f64: f104 33ff addne.w r3, r4, #4294967295 @ 0xffffffff 8009f68: 9302 str r3, [sp, #8] 8009f6a: 9305 str r3, [sp, #20] 8009f6c: f64f 73ff movw r3, #65535 @ 0xffff 8009f70: 9100 str r1, [sp, #0] 8009f72: 9104 str r1, [sp, #16] 8009f74: f8ad 300e strh.w r3, [sp, #14] 8009f78: 4669 mov r1, sp 8009f7a: 9b1e ldr r3, [sp, #120] @ 0x78 8009f7c: f001 fcee bl 800b95c <_svfiprintf_r> 8009f80: 1c43 adds r3, r0, #1 8009f82: bfbc itt lt 8009f84: 238b movlt r3, #139 @ 0x8b 8009f86: 602b strlt r3, [r5, #0] 8009f88: 2c00 cmp r4, #0 8009f8a: d0e0 beq.n 8009f4e <_vsniprintf_r+0x16> 8009f8c: 2200 movs r2, #0 8009f8e: 9b00 ldr r3, [sp, #0] 8009f90: 701a strb r2, [r3, #0] 8009f92: e7dc b.n 8009f4e <_vsniprintf_r+0x16> 08009f94 : 8009f94: b507 push {r0, r1, r2, lr} 8009f96: 9300 str r3, [sp, #0] 8009f98: 4613 mov r3, r2 8009f9a: 460a mov r2, r1 8009f9c: 4601 mov r1, r0 8009f9e: 4803 ldr r0, [pc, #12] @ (8009fac ) 8009fa0: 6800 ldr r0, [r0, #0] 8009fa2: f7ff ffc9 bl 8009f38 <_vsniprintf_r> 8009fa6: b003 add sp, #12 8009fa8: f85d fb04 ldr.w pc, [sp], #4 8009fac: 20000038 .word 0x20000038 08009fb0 <_fwalk_sglue>: 8009fb0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8009fb4: 4607 mov r7, r0 8009fb6: 4688 mov r8, r1 8009fb8: 4614 mov r4, r2 8009fba: 2600 movs r6, #0 8009fbc: e9d4 9501 ldrd r9, r5, [r4, #4] 8009fc0: f1b9 0901 subs.w r9, r9, #1 8009fc4: d505 bpl.n 8009fd2 <_fwalk_sglue+0x22> 8009fc6: 6824 ldr r4, [r4, #0] 8009fc8: 2c00 cmp r4, #0 8009fca: d1f7 bne.n 8009fbc <_fwalk_sglue+0xc> 8009fcc: 4630 mov r0, r6 8009fce: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8009fd2: 89ab ldrh r3, [r5, #12] 8009fd4: 2b01 cmp r3, #1 8009fd6: d907 bls.n 8009fe8 <_fwalk_sglue+0x38> 8009fd8: f9b5 300e ldrsh.w r3, [r5, #14] 8009fdc: 3301 adds r3, #1 8009fde: d003 beq.n 8009fe8 <_fwalk_sglue+0x38> 8009fe0: 4629 mov r1, r5 8009fe2: 4638 mov r0, r7 8009fe4: 47c0 blx r8 8009fe6: 4306 orrs r6, r0 8009fe8: 3568 adds r5, #104 @ 0x68 8009fea: e7e9 b.n 8009fc0 <_fwalk_sglue+0x10> 08009fec : 8009fec: b40f push {r0, r1, r2, r3} 8009fee: b507 push {r0, r1, r2, lr} 8009ff0: 4906 ldr r1, [pc, #24] @ (800a00c ) 8009ff2: ab04 add r3, sp, #16 8009ff4: 6808 ldr r0, [r1, #0] 8009ff6: f853 2b04 ldr.w r2, [r3], #4 8009ffa: 6881 ldr r1, [r0, #8] 8009ffc: 9301 str r3, [sp, #4] 8009ffe: f001 fdd1 bl 800bba4 <_vfiprintf_r> 800a002: b003 add sp, #12 800a004: f85d eb04 ldr.w lr, [sp], #4 800a008: b004 add sp, #16 800a00a: 4770 bx lr 800a00c: 20000038 .word 0x20000038 0800a010 <_puts_r>: 800a010: 6a03 ldr r3, [r0, #32] 800a012: b570 push {r4, r5, r6, lr} 800a014: 4605 mov r5, r0 800a016: 460e mov r6, r1 800a018: 6884 ldr r4, [r0, #8] 800a01a: b90b cbnz r3, 800a020 <_puts_r+0x10> 800a01c: f7ff ff74 bl 8009f08 <__sinit> 800a020: 6e63 ldr r3, [r4, #100] @ 0x64 800a022: 07db lsls r3, r3, #31 800a024: d405 bmi.n 800a032 <_puts_r+0x22> 800a026: 89a3 ldrh r3, [r4, #12] 800a028: 0598 lsls r0, r3, #22 800a02a: d402 bmi.n 800a032 <_puts_r+0x22> 800a02c: 6da0 ldr r0, [r4, #88] @ 0x58 800a02e: f000 fb2b bl 800a688 <__retarget_lock_acquire_recursive> 800a032: 89a3 ldrh r3, [r4, #12] 800a034: 0719 lsls r1, r3, #28 800a036: d502 bpl.n 800a03e <_puts_r+0x2e> 800a038: 6923 ldr r3, [r4, #16] 800a03a: 2b00 cmp r3, #0 800a03c: d135 bne.n 800a0aa <_puts_r+0x9a> 800a03e: 4621 mov r1, r4 800a040: 4628 mov r0, r5 800a042: f002 fd11 bl 800ca68 <__swsetup_r> 800a046: b380 cbz r0, 800a0aa <_puts_r+0x9a> 800a048: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff 800a04c: 6e63 ldr r3, [r4, #100] @ 0x64 800a04e: 07da lsls r2, r3, #31 800a050: d405 bmi.n 800a05e <_puts_r+0x4e> 800a052: 89a3 ldrh r3, [r4, #12] 800a054: 059b lsls r3, r3, #22 800a056: d402 bmi.n 800a05e <_puts_r+0x4e> 800a058: 6da0 ldr r0, [r4, #88] @ 0x58 800a05a: f000 fb17 bl 800a68c <__retarget_lock_release_recursive> 800a05e: 4628 mov r0, r5 800a060: bd70 pop {r4, r5, r6, pc} 800a062: 2b00 cmp r3, #0 800a064: da04 bge.n 800a070 <_puts_r+0x60> 800a066: 69a2 ldr r2, [r4, #24] 800a068: 429a cmp r2, r3 800a06a: dc17 bgt.n 800a09c <_puts_r+0x8c> 800a06c: 290a cmp r1, #10 800a06e: d015 beq.n 800a09c <_puts_r+0x8c> 800a070: 6823 ldr r3, [r4, #0] 800a072: 1c5a adds r2, r3, #1 800a074: 6022 str r2, [r4, #0] 800a076: 7019 strb r1, [r3, #0] 800a078: 68a3 ldr r3, [r4, #8] 800a07a: f816 1f01 ldrb.w r1, [r6, #1]! 800a07e: 3b01 subs r3, #1 800a080: 60a3 str r3, [r4, #8] 800a082: 2900 cmp r1, #0 800a084: d1ed bne.n 800a062 <_puts_r+0x52> 800a086: 2b00 cmp r3, #0 800a088: da11 bge.n 800a0ae <_puts_r+0x9e> 800a08a: 4622 mov r2, r4 800a08c: 210a movs r1, #10 800a08e: 4628 mov r0, r5 800a090: f002 fc32 bl 800c8f8 <__swbuf_r> 800a094: 3001 adds r0, #1 800a096: d0d7 beq.n 800a048 <_puts_r+0x38> 800a098: 250a movs r5, #10 800a09a: e7d7 b.n 800a04c <_puts_r+0x3c> 800a09c: 4622 mov r2, r4 800a09e: 4628 mov r0, r5 800a0a0: f002 fc2a bl 800c8f8 <__swbuf_r> 800a0a4: 3001 adds r0, #1 800a0a6: d1e7 bne.n 800a078 <_puts_r+0x68> 800a0a8: e7ce b.n 800a048 <_puts_r+0x38> 800a0aa: 3e01 subs r6, #1 800a0ac: e7e4 b.n 800a078 <_puts_r+0x68> 800a0ae: 6823 ldr r3, [r4, #0] 800a0b0: 1c5a adds r2, r3, #1 800a0b2: 6022 str r2, [r4, #0] 800a0b4: 220a movs r2, #10 800a0b6: 701a strb r2, [r3, #0] 800a0b8: e7ee b.n 800a098 <_puts_r+0x88> ... 0800a0bc : 800a0bc: 4b02 ldr r3, [pc, #8] @ (800a0c8 ) 800a0be: 4601 mov r1, r0 800a0c0: 6818 ldr r0, [r3, #0] 800a0c2: f7ff bfa5 b.w 800a010 <_puts_r> 800a0c6: bf00 nop 800a0c8: 20000038 .word 0x20000038 0800a0cc : 800a0cc: 4603 mov r3, r0 800a0ce: 4402 add r2, r0 800a0d0: 4293 cmp r3, r2 800a0d2: d100 bne.n 800a0d6 800a0d4: 4770 bx lr 800a0d6: f803 1b01 strb.w r1, [r3], #1 800a0da: e7f9 b.n 800a0d0 0800a0dc : 800a0dc: b510 push {r4, lr} 800a0de: b16a cbz r2, 800a0fc 800a0e0: 3901 subs r1, #1 800a0e2: 1884 adds r4, r0, r2 800a0e4: f810 2b01 ldrb.w r2, [r0], #1 800a0e8: f811 3f01 ldrb.w r3, [r1, #1]! 800a0ec: 429a cmp r2, r3 800a0ee: d103 bne.n 800a0f8 800a0f0: 42a0 cmp r0, r4 800a0f2: d001 beq.n 800a0f8 800a0f4: 2a00 cmp r2, #0 800a0f6: d1f5 bne.n 800a0e4 800a0f8: 1ad0 subs r0, r2, r3 800a0fa: bd10 pop {r4, pc} 800a0fc: 4610 mov r0, r2 800a0fe: e7fc b.n 800a0fa 0800a100 : 800a100: b538 push {r3, r4, r5, lr} 800a102: 4b0b ldr r3, [pc, #44] @ (800a130 ) 800a104: 4604 mov r4, r0 800a106: 681d ldr r5, [r3, #0] 800a108: 6b6b ldr r3, [r5, #52] @ 0x34 800a10a: b953 cbnz r3, 800a122 800a10c: 2024 movs r0, #36 @ 0x24 800a10e: f001 fe61 bl 800bdd4 800a112: 4602 mov r2, r0 800a114: 6368 str r0, [r5, #52] @ 0x34 800a116: b920 cbnz r0, 800a122 800a118: 213d movs r1, #61 @ 0x3d 800a11a: 4b06 ldr r3, [pc, #24] @ (800a134 ) 800a11c: 4806 ldr r0, [pc, #24] @ (800a138 ) 800a11e: f000 fd03 bl 800ab28 <__assert_func> 800a122: 4620 mov r0, r4 800a124: 6b69 ldr r1, [r5, #52] @ 0x34 800a126: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 800a12a: f000 b807 b.w 800a13c 800a12e: bf00 nop 800a130: 20000038 .word 0x20000038 800a134: 0800dfe6 .word 0x0800dfe6 800a138: 0800dffd .word 0x0800dffd 0800a13c : 800a13c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800a140: 2300 movs r3, #0 800a142: 460c mov r4, r1 800a144: e9d0 0100 ldrd r0, r1, [r0] 800a148: 4a4c ldr r2, [pc, #304] @ (800a27c ) 800a14a: f7f7 f85d bl 8001208 <__aeabi_ldivmod> 800a14e: f44f 6161 mov.w r1, #3600 @ 0xe10 800a152: 2a00 cmp r2, #0 800a154: bfbc itt lt 800a156: f502 32a8 addlt.w r2, r2, #86016 @ 0x15000 800a15a: f502 72c0 addlt.w r2, r2, #384 @ 0x180 800a15e: fbb2 f3f1 udiv r3, r2, r1 800a162: fb01 2213 mls r2, r1, r3, r2 800a166: f04f 013c mov.w r1, #60 @ 0x3c 800a16a: 60a3 str r3, [r4, #8] 800a16c: fbb2 f3f1 udiv r3, r2, r1 800a170: fb01 2213 mls r2, r1, r3, r2 800a174: 6022 str r2, [r4, #0] 800a176: f04f 0207 mov.w r2, #7 800a17a: f500 202f add.w r0, r0, #716800 @ 0xaf000 800a17e: bfac ite ge 800a180: f600 206c addwge r0, r0, #2668 @ 0xa6c 800a184: f600 206b addwlt r0, r0, #2667 @ 0xa6b 800a188: 6063 str r3, [r4, #4] 800a18a: 1cc3 adds r3, r0, #3 800a18c: fb93 f2f2 sdiv r2, r3, r2 800a190: ebc2 02c2 rsb r2, r2, r2, lsl #3 800a194: 1a9b subs r3, r3, r2 800a196: 493a ldr r1, [pc, #232] @ (800a280 ) 800a198: d555 bpl.n 800a246 800a19a: 3307 adds r3, #7 800a19c: 61a3 str r3, [r4, #24] 800a19e: f5a0 330e sub.w r3, r0, #145408 @ 0x23800 800a1a2: f5a3 732c sub.w r3, r3, #688 @ 0x2b0 800a1a6: fb93 f1f1 sdiv r1, r3, r1 800a1aa: 4b36 ldr r3, [pc, #216] @ (800a284 ) 800a1ac: f240 5cb4 movw ip, #1460 @ 0x5b4 800a1b0: fb03 0001 mla r0, r3, r1, r0 800a1b4: f648 63ac movw r3, #36524 @ 0x8eac 800a1b8: fbb0 f3f3 udiv r3, r0, r3 800a1bc: fbb0 f2fc udiv r2, r0, ip 800a1c0: 4403 add r3, r0 800a1c2: 1a9b subs r3, r3, r2 800a1c4: 4a30 ldr r2, [pc, #192] @ (800a288 ) 800a1c6: f240 176d movw r7, #365 @ 0x16d 800a1ca: fbb0 f2f2 udiv r2, r0, r2 800a1ce: 1a9b subs r3, r3, r2 800a1d0: fbb3 f2f7 udiv r2, r3, r7 800a1d4: 2664 movs r6, #100 @ 0x64 800a1d6: fbb3 f3fc udiv r3, r3, ip 800a1da: fbb2 f5f6 udiv r5, r2, r6 800a1de: 1aeb subs r3, r5, r3 800a1e0: 4403 add r3, r0 800a1e2: 2099 movs r0, #153 @ 0x99 800a1e4: fb07 3312 mls r3, r7, r2, r3 800a1e8: eb03 0783 add.w r7, r3, r3, lsl #2 800a1ec: 3702 adds r7, #2 800a1ee: fbb7 fcf0 udiv ip, r7, r0 800a1f2: f04f 0805 mov.w r8, #5 800a1f6: fb00 f00c mul.w r0, r0, ip 800a1fa: 3002 adds r0, #2 800a1fc: fbb0 f0f8 udiv r0, r0, r8 800a200: f103 0e01 add.w lr, r3, #1 800a204: ebae 0000 sub.w r0, lr, r0 800a208: f240 5ef9 movw lr, #1529 @ 0x5f9 800a20c: 4577 cmp r7, lr 800a20e: bf8c ite hi 800a210: f06f 0709 mvnhi.w r7, #9 800a214: 2702 movls r7, #2 800a216: 4467 add r7, ip 800a218: f44f 7cc8 mov.w ip, #400 @ 0x190 800a21c: fb0c 2101 mla r1, ip, r1, r2 800a220: 2f01 cmp r7, #1 800a222: bf98 it ls 800a224: 3101 addls r1, #1 800a226: f5b3 7f99 cmp.w r3, #306 @ 0x132 800a22a: d312 bcc.n 800a252 800a22c: f5a3 7399 sub.w r3, r3, #306 @ 0x132 800a230: 61e3 str r3, [r4, #28] 800a232: 2300 movs r3, #0 800a234: f2a1 716c subw r1, r1, #1900 @ 0x76c 800a238: 60e0 str r0, [r4, #12] 800a23a: e9c4 7104 strd r7, r1, [r4, #16] 800a23e: 4620 mov r0, r4 800a240: 6223 str r3, [r4, #32] 800a242: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800a246: 2800 cmp r0, #0 800a248: 61a3 str r3, [r4, #24] 800a24a: dba8 blt.n 800a19e 800a24c: fb90 f1f1 sdiv r1, r0, r1 800a250: e7ab b.n 800a1aa 800a252: f012 0f03 tst.w r2, #3 800a256: d102 bne.n 800a25e 800a258: fb06 2515 mls r5, r6, r5, r2 800a25c: b95d cbnz r5, 800a276 800a25e: f44f 75c8 mov.w r5, #400 @ 0x190 800a262: fbb2 f6f5 udiv r6, r2, r5 800a266: fb05 2216 mls r2, r5, r6, r2 800a26a: fab2 f282 clz r2, r2 800a26e: 0952 lsrs r2, r2, #5 800a270: 333b adds r3, #59 @ 0x3b 800a272: 4413 add r3, r2 800a274: e7dc b.n 800a230 800a276: 2201 movs r2, #1 800a278: e7fa b.n 800a270 800a27a: bf00 nop 800a27c: 00015180 .word 0x00015180 800a280: 00023ab1 .word 0x00023ab1 800a284: fffdc54f .word 0xfffdc54f 800a288: 00023ab0 .word 0x00023ab0 0800a28c : 800a28c: b538 push {r3, r4, r5, lr} 800a28e: 4b0b ldr r3, [pc, #44] @ (800a2bc ) 800a290: 4604 mov r4, r0 800a292: 681d ldr r5, [r3, #0] 800a294: 6b6b ldr r3, [r5, #52] @ 0x34 800a296: b953 cbnz r3, 800a2ae 800a298: 2024 movs r0, #36 @ 0x24 800a29a: f001 fd9b bl 800bdd4 800a29e: 4602 mov r2, r0 800a2a0: 6368 str r0, [r5, #52] @ 0x34 800a2a2: b920 cbnz r0, 800a2ae 800a2a4: 2132 movs r1, #50 @ 0x32 800a2a6: 4b06 ldr r3, [pc, #24] @ (800a2c0 ) 800a2a8: 4806 ldr r0, [pc, #24] @ (800a2c4 ) 800a2aa: f000 fc3d bl 800ab28 <__assert_func> 800a2ae: 4620 mov r0, r4 800a2b0: 6b69 ldr r1, [r5, #52] @ 0x34 800a2b2: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 800a2b6: f000 b807 b.w 800a2c8 800a2ba: bf00 nop 800a2bc: 20000038 .word 0x20000038 800a2c0: 0800dfe6 .word 0x0800dfe6 800a2c4: 0800e055 .word 0x0800e055 0800a2c8 : 800a2c8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800a2cc: 460c mov r4, r1 800a2ce: 4607 mov r7, r0 800a2d0: f002 fce0 bl 800cc94 <__gettzinfo> 800a2d4: 4621 mov r1, r4 800a2d6: 4605 mov r5, r0 800a2d8: 4638 mov r0, r7 800a2da: f7ff ff2f bl 800a13c 800a2de: 6943 ldr r3, [r0, #20] 800a2e0: 4604 mov r4, r0 800a2e2: 0799 lsls r1, r3, #30 800a2e4: f203 786c addw r8, r3, #1900 @ 0x76c 800a2e8: d106 bne.n 800a2f8 800a2ea: 2264 movs r2, #100 @ 0x64 800a2ec: fb98 f3f2 sdiv r3, r8, r2 800a2f0: fb02 8313 mls r3, r2, r3, r8 800a2f4: 2b00 cmp r3, #0 800a2f6: d171 bne.n 800a3dc 800a2f8: f44f 72c8 mov.w r2, #400 @ 0x190 800a2fc: fb98 f3f2 sdiv r3, r8, r2 800a300: fb02 8313 mls r3, r2, r3, r8 800a304: fab3 f383 clz r3, r3 800a308: 095b lsrs r3, r3, #5 800a30a: 425e negs r6, r3 800a30c: 4b64 ldr r3, [pc, #400] @ (800a4a0 ) 800a30e: f006 0630 and.w r6, r6, #48 @ 0x30 800a312: 441e add r6, r3 800a314: f000 f9a4 bl 800a660 <__tz_lock> 800a318: f000 f9ae bl 800a678 <_tzset_unlocked> 800a31c: 4b61 ldr r3, [pc, #388] @ (800a4a4 ) 800a31e: 681b ldr r3, [r3, #0] 800a320: 2b00 cmp r3, #0 800a322: d06a beq.n 800a3fa 800a324: 686b ldr r3, [r5, #4] 800a326: 4543 cmp r3, r8 800a328: d15a bne.n 800a3e0 800a32a: e9d7 2300 ldrd r2, r3, [r7] 800a32e: e9d5 0108 ldrd r0, r1, [r5, #32] 800a332: 682f ldr r7, [r5, #0] 800a334: 2f00 cmp r7, #0 800a336: d15b bne.n 800a3f0 800a338: 4282 cmp r2, r0 800a33a: eb73 0101 sbcs.w r1, r3, r1 800a33e: db5e blt.n 800a3fe 800a340: 2301 movs r3, #1 800a342: 6223 str r3, [r4, #32] 800a344: 6d2b ldr r3, [r5, #80] @ 0x50 800a346: f44f 6261 mov.w r2, #3600 @ 0xe10 800a34a: fb93 f0f2 sdiv r0, r3, r2 800a34e: fb02 3310 mls r3, r2, r0, r3 800a352: 223c movs r2, #60 @ 0x3c 800a354: fb93 f5f2 sdiv r5, r3, r2 800a358: fb02 3215 mls r2, r2, r5, r3 800a35c: 6823 ldr r3, [r4, #0] 800a35e: 6861 ldr r1, [r4, #4] 800a360: 1a9b subs r3, r3, r2 800a362: 68a2 ldr r2, [r4, #8] 800a364: 1b49 subs r1, r1, r5 800a366: 1a12 subs r2, r2, r0 800a368: 2b3b cmp r3, #59 @ 0x3b 800a36a: 6023 str r3, [r4, #0] 800a36c: 6061 str r1, [r4, #4] 800a36e: 60a2 str r2, [r4, #8] 800a370: dd51 ble.n 800a416 800a372: 3101 adds r1, #1 800a374: 6061 str r1, [r4, #4] 800a376: 3b3c subs r3, #60 @ 0x3c 800a378: 6023 str r3, [r4, #0] 800a37a: 6863 ldr r3, [r4, #4] 800a37c: 2b3b cmp r3, #59 @ 0x3b 800a37e: dd50 ble.n 800a422 800a380: 3201 adds r2, #1 800a382: 60a2 str r2, [r4, #8] 800a384: 3b3c subs r3, #60 @ 0x3c 800a386: 6063 str r3, [r4, #4] 800a388: 68a3 ldr r3, [r4, #8] 800a38a: 2b17 cmp r3, #23 800a38c: dd4f ble.n 800a42e 800a38e: 69e2 ldr r2, [r4, #28] 800a390: 3b18 subs r3, #24 800a392: 3201 adds r2, #1 800a394: 61e2 str r2, [r4, #28] 800a396: 69a2 ldr r2, [r4, #24] 800a398: 60a3 str r3, [r4, #8] 800a39a: 3201 adds r2, #1 800a39c: 2a07 cmp r2, #7 800a39e: bfa8 it ge 800a3a0: 2200 movge r2, #0 800a3a2: 61a2 str r2, [r4, #24] 800a3a4: 68e2 ldr r2, [r4, #12] 800a3a6: 6923 ldr r3, [r4, #16] 800a3a8: 3201 adds r2, #1 800a3aa: 60e2 str r2, [r4, #12] 800a3ac: f856 1023 ldr.w r1, [r6, r3, lsl #2] 800a3b0: 428a cmp r2, r1 800a3b2: dd0e ble.n 800a3d2 800a3b4: 2b0b cmp r3, #11 800a3b6: eba2 0201 sub.w r2, r2, r1 800a3ba: 60e2 str r2, [r4, #12] 800a3bc: f103 0201 add.w r2, r3, #1 800a3c0: bf05 ittet eq 800a3c2: 2200 moveq r2, #0 800a3c4: 6963 ldreq r3, [r4, #20] 800a3c6: 6122 strne r2, [r4, #16] 800a3c8: 3301 addeq r3, #1 800a3ca: bf02 ittt eq 800a3cc: 6122 streq r2, [r4, #16] 800a3ce: 6163 streq r3, [r4, #20] 800a3d0: 61e2 streq r2, [r4, #28] 800a3d2: f000 f94b bl 800a66c <__tz_unlock> 800a3d6: 4620 mov r0, r4 800a3d8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800a3dc: 2301 movs r3, #1 800a3de: e794 b.n 800a30a 800a3e0: 4640 mov r0, r8 800a3e2: f000 f88b bl 800a4fc <__tzcalc_limits> 800a3e6: 2800 cmp r0, #0 800a3e8: d19f bne.n 800a32a 800a3ea: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800a3ee: e004 b.n 800a3fa 800a3f0: 4282 cmp r2, r0 800a3f2: eb73 0101 sbcs.w r1, r3, r1 800a3f6: da02 bge.n 800a3fe 800a3f8: 2300 movs r3, #0 800a3fa: 6223 str r3, [r4, #32] 800a3fc: e009 b.n 800a412 800a3fe: e9d5 0112 ldrd r0, r1, [r5, #72] @ 0x48 800a402: 4282 cmp r2, r0 800a404: 418b sbcs r3, r1 800a406: bfb4 ite lt 800a408: 2301 movlt r3, #1 800a40a: 2300 movge r3, #0 800a40c: 6223 str r3, [r4, #32] 800a40e: 2b00 cmp r3, #0 800a410: d198 bne.n 800a344 800a412: 6aab ldr r3, [r5, #40] @ 0x28 800a414: e797 b.n 800a346 800a416: 2b00 cmp r3, #0 800a418: daaf bge.n 800a37a 800a41a: 3901 subs r1, #1 800a41c: 6061 str r1, [r4, #4] 800a41e: 333c adds r3, #60 @ 0x3c 800a420: e7aa b.n 800a378 800a422: 2b00 cmp r3, #0 800a424: dab0 bge.n 800a388 800a426: 3a01 subs r2, #1 800a428: 60a2 str r2, [r4, #8] 800a42a: 333c adds r3, #60 @ 0x3c 800a42c: e7ab b.n 800a386 800a42e: 2b00 cmp r3, #0 800a430: dacf bge.n 800a3d2 800a432: 69e2 ldr r2, [r4, #28] 800a434: 3318 adds r3, #24 800a436: 3a01 subs r2, #1 800a438: 61e2 str r2, [r4, #28] 800a43a: 69a2 ldr r2, [r4, #24] 800a43c: 60a3 str r3, [r4, #8] 800a43e: 3a01 subs r2, #1 800a440: bf48 it mi 800a442: 2206 movmi r2, #6 800a444: 61a2 str r2, [r4, #24] 800a446: 68e2 ldr r2, [r4, #12] 800a448: 3a01 subs r2, #1 800a44a: 60e2 str r2, [r4, #12] 800a44c: 2a00 cmp r2, #0 800a44e: d1c0 bne.n 800a3d2 800a450: 6923 ldr r3, [r4, #16] 800a452: 3b01 subs r3, #1 800a454: d405 bmi.n 800a462 800a456: 6123 str r3, [r4, #16] 800a458: 6923 ldr r3, [r4, #16] 800a45a: f856 3023 ldr.w r3, [r6, r3, lsl #2] 800a45e: 60e3 str r3, [r4, #12] 800a460: e7b7 b.n 800a3d2 800a462: 230b movs r3, #11 800a464: 6123 str r3, [r4, #16] 800a466: 6963 ldr r3, [r4, #20] 800a468: 1e5a subs r2, r3, #1 800a46a: 6162 str r2, [r4, #20] 800a46c: 0792 lsls r2, r2, #30 800a46e: f203 736b addw r3, r3, #1899 @ 0x76b 800a472: d105 bne.n 800a480 800a474: 2164 movs r1, #100 @ 0x64 800a476: fb93 f2f1 sdiv r2, r3, r1 800a47a: fb01 3212 mls r2, r1, r2, r3 800a47e: b962 cbnz r2, 800a49a 800a480: f44f 72c8 mov.w r2, #400 @ 0x190 800a484: fb93 f1f2 sdiv r1, r3, r2 800a488: fb02 3311 mls r3, r2, r1, r3 800a48c: fab3 f383 clz r3, r3 800a490: 095b lsrs r3, r3, #5 800a492: f503 73b6 add.w r3, r3, #364 @ 0x16c 800a496: 61e3 str r3, [r4, #28] 800a498: e7de b.n 800a458 800a49a: 2301 movs r3, #1 800a49c: e7f9 b.n 800a492 800a49e: bf00 nop 800a4a0: 0800e240 .word 0x0800e240 800a4a4: 2000350c .word 0x2000350c 0800a4a8 <__errno>: 800a4a8: 4b01 ldr r3, [pc, #4] @ (800a4b0 <__errno+0x8>) 800a4aa: 6818 ldr r0, [r3, #0] 800a4ac: 4770 bx lr 800a4ae: bf00 nop 800a4b0: 20000038 .word 0x20000038 0800a4b4 <__libc_init_array>: 800a4b4: b570 push {r4, r5, r6, lr} 800a4b6: 2600 movs r6, #0 800a4b8: 4d0c ldr r5, [pc, #48] @ (800a4ec <__libc_init_array+0x38>) 800a4ba: 4c0d ldr r4, [pc, #52] @ (800a4f0 <__libc_init_array+0x3c>) 800a4bc: 1b64 subs r4, r4, r5 800a4be: 10a4 asrs r4, r4, #2 800a4c0: 42a6 cmp r6, r4 800a4c2: d109 bne.n 800a4d8 <__libc_init_array+0x24> 800a4c4: f003 f902 bl 800d6cc <_init> 800a4c8: 2600 movs r6, #0 800a4ca: 4d0a ldr r5, [pc, #40] @ (800a4f4 <__libc_init_array+0x40>) 800a4cc: 4c0a ldr r4, [pc, #40] @ (800a4f8 <__libc_init_array+0x44>) 800a4ce: 1b64 subs r4, r4, r5 800a4d0: 10a4 asrs r4, r4, #2 800a4d2: 42a6 cmp r6, r4 800a4d4: d105 bne.n 800a4e2 <__libc_init_array+0x2e> 800a4d6: bd70 pop {r4, r5, r6, pc} 800a4d8: f855 3b04 ldr.w r3, [r5], #4 800a4dc: 4798 blx r3 800a4de: 3601 adds r6, #1 800a4e0: e7ee b.n 800a4c0 <__libc_init_array+0xc> 800a4e2: f855 3b04 ldr.w r3, [r5], #4 800a4e6: 4798 blx r3 800a4e8: 3601 adds r6, #1 800a4ea: e7f2 b.n 800a4d2 <__libc_init_array+0x1e> 800a4ec: 0800e4ac .word 0x0800e4ac 800a4f0: 0800e4ac .word 0x0800e4ac 800a4f4: 0800e4ac .word 0x0800e4ac 800a4f8: 0800e4b0 .word 0x0800e4b0 0800a4fc <__tzcalc_limits>: 800a4fc: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 800a500: 4604 mov r4, r0 800a502: f002 fbc7 bl 800cc94 <__gettzinfo> 800a506: f240 73b1 movw r3, #1969 @ 0x7b1 800a50a: 429c cmp r4, r3 800a50c: f340 80a2 ble.w 800a654 <__tzcalc_limits+0x158> 800a510: f46f 61f6 mvn.w r1, #1968 @ 0x7b0 800a514: f240 126d movw r2, #365 @ 0x16d 800a518: 1865 adds r5, r4, r1 800a51a: f2a4 73b2 subw r3, r4, #1970 @ 0x7b2 800a51e: 10ad asrs r5, r5, #2 800a520: fb02 5503 mla r5, r2, r3, r5 800a524: f06f 0263 mvn.w r2, #99 @ 0x63 800a528: f2a4 736d subw r3, r4, #1901 @ 0x76d 800a52c: fb93 f3f2 sdiv r3, r3, r2 800a530: f46f 66c8 mvn.w r6, #1600 @ 0x640 800a534: f44f 72c8 mov.w r2, #400 @ 0x190 800a538: 441d add r5, r3 800a53a: 19a3 adds r3, r4, r6 800a53c: fbb3 f3f2 udiv r3, r3, r2 800a540: 4601 mov r1, r0 800a542: 4e45 ldr r6, [pc, #276] @ (800a658 <__tzcalc_limits+0x15c>) 800a544: 6044 str r4, [r0, #4] 800a546: 441d add r5, r3 800a548: f100 0750 add.w r7, r0, #80 @ 0x50 800a54c: 7a0b ldrb r3, [r1, #8] 800a54e: f8d1 c014 ldr.w ip, [r1, #20] 800a552: 2b4a cmp r3, #74 @ 0x4a 800a554: d138 bne.n 800a5c8 <__tzcalc_limits+0xcc> 800a556: 07a2 lsls r2, r4, #30 800a558: eb05 030c add.w r3, r5, ip 800a55c: d106 bne.n 800a56c <__tzcalc_limits+0x70> 800a55e: f04f 0e64 mov.w lr, #100 @ 0x64 800a562: fb94 f2fe sdiv r2, r4, lr 800a566: fb0e 4212 mls r2, lr, r2, r4 800a56a: b932 cbnz r2, 800a57a <__tzcalc_limits+0x7e> 800a56c: f44f 7ec8 mov.w lr, #400 @ 0x190 800a570: fb94 f2fe sdiv r2, r4, lr 800a574: fb0e 4212 mls r2, lr, r2, r4 800a578: bb1a cbnz r2, 800a5c2 <__tzcalc_limits+0xc6> 800a57a: f1bc 0f3b cmp.w ip, #59 @ 0x3b 800a57e: bfd4 ite le 800a580: f04f 0c00 movle.w ip, #0 800a584: f04f 0c01 movgt.w ip, #1 800a588: 4463 add r3, ip 800a58a: 3b01 subs r3, #1 800a58c: 698a ldr r2, [r1, #24] 800a58e: ea4f 7ce2 mov.w ip, r2, asr #31 800a592: fbc3 2c06 smlal r2, ip, r3, r6 800a596: 6a8b ldr r3, [r1, #40] @ 0x28 800a598: 18d2 adds r2, r2, r3 800a59a: eb4c 73e3 adc.w r3, ip, r3, asr #31 800a59e: e9c1 2308 strd r2, r3, [r1, #32] 800a5a2: 3128 adds r1, #40 @ 0x28 800a5a4: 428f cmp r7, r1 800a5a6: d1d1 bne.n 800a54c <__tzcalc_limits+0x50> 800a5a8: e9d0 4308 ldrd r4, r3, [r0, #32] 800a5ac: e9d0 1212 ldrd r1, r2, [r0, #72] @ 0x48 800a5b0: 428c cmp r4, r1 800a5b2: 4193 sbcs r3, r2 800a5b4: bfb4 ite lt 800a5b6: 2301 movlt r3, #1 800a5b8: 2300 movge r3, #0 800a5ba: 6003 str r3, [r0, #0] 800a5bc: 2001 movs r0, #1 800a5be: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 800a5c2: f04f 0c00 mov.w ip, #0 800a5c6: e7df b.n 800a588 <__tzcalc_limits+0x8c> 800a5c8: 2b44 cmp r3, #68 @ 0x44 800a5ca: d102 bne.n 800a5d2 <__tzcalc_limits+0xd6> 800a5cc: eb05 030c add.w r3, r5, ip 800a5d0: e7dc b.n 800a58c <__tzcalc_limits+0x90> 800a5d2: 07a3 lsls r3, r4, #30 800a5d4: d105 bne.n 800a5e2 <__tzcalc_limits+0xe6> 800a5d6: 2264 movs r2, #100 @ 0x64 800a5d8: fb94 f3f2 sdiv r3, r4, r2 800a5dc: fb02 4313 mls r3, r2, r3, r4 800a5e0: bb8b cbnz r3, 800a646 <__tzcalc_limits+0x14a> 800a5e2: f44f 72c8 mov.w r2, #400 @ 0x190 800a5e6: fb94 f3f2 sdiv r3, r4, r2 800a5ea: fb02 4313 mls r3, r2, r3, r4 800a5ee: fab3 f383 clz r3, r3 800a5f2: 095b lsrs r3, r3, #5 800a5f4: 462a mov r2, r5 800a5f6: f04f 0800 mov.w r8, #0 800a5fa: f8df e060 ldr.w lr, [pc, #96] @ 800a65c <__tzcalc_limits+0x160> 800a5fe: 425b negs r3, r3 800a600: f003 0330 and.w r3, r3, #48 @ 0x30 800a604: f8d1 900c ldr.w r9, [r1, #12] 800a608: 4473 add r3, lr 800a60a: f108 0801 add.w r8, r8, #1 800a60e: 45c1 cmp r9, r8 800a610: f853 e028 ldr.w lr, [r3, r8, lsl #2] 800a614: dc19 bgt.n 800a64a <__tzcalc_limits+0x14e> 800a616: 2307 movs r3, #7 800a618: f102 0804 add.w r8, r2, #4 800a61c: fb98 f3f3 sdiv r3, r8, r3 800a620: ebc3 03c3 rsb r3, r3, r3, lsl #3 800a624: eba8 0303 sub.w r3, r8, r3 800a628: ebbc 0c03 subs.w ip, ip, r3 800a62c: 690b ldr r3, [r1, #16] 800a62e: bf48 it mi 800a630: f10c 0c07 addmi.w ip, ip, #7 800a634: 3b01 subs r3, #1 800a636: ebc3 03c3 rsb r3, r3, r3, lsl #3 800a63a: 449c add ip, r3 800a63c: 45f4 cmp ip, lr 800a63e: da06 bge.n 800a64e <__tzcalc_limits+0x152> 800a640: eb02 030c add.w r3, r2, ip 800a644: e7a2 b.n 800a58c <__tzcalc_limits+0x90> 800a646: 2301 movs r3, #1 800a648: e7d4 b.n 800a5f4 <__tzcalc_limits+0xf8> 800a64a: 4472 add r2, lr 800a64c: e7dd b.n 800a60a <__tzcalc_limits+0x10e> 800a64e: f1ac 0c07 sub.w ip, ip, #7 800a652: e7f3 b.n 800a63c <__tzcalc_limits+0x140> 800a654: 2000 movs r0, #0 800a656: e7b2 b.n 800a5be <__tzcalc_limits+0xc2> 800a658: 00015180 .word 0x00015180 800a65c: 0800e23c .word 0x0800e23c 0800a660 <__tz_lock>: 800a660: 4801 ldr r0, [pc, #4] @ (800a668 <__tz_lock+0x8>) 800a662: f000 b810 b.w 800a686 <__retarget_lock_acquire> 800a666: bf00 nop 800a668: 200034e8 .word 0x200034e8 0800a66c <__tz_unlock>: 800a66c: 4801 ldr r0, [pc, #4] @ (800a674 <__tz_unlock+0x8>) 800a66e: f000 b80c b.w 800a68a <__retarget_lock_release> 800a672: bf00 nop 800a674: 200034e8 .word 0x200034e8 0800a678 <_tzset_unlocked>: 800a678: 4b01 ldr r3, [pc, #4] @ (800a680 <_tzset_unlocked+0x8>) 800a67a: 6818 ldr r0, [r3, #0] 800a67c: f000 b808 b.w 800a690 <_tzset_unlocked_r> 800a680: 20000038 .word 0x20000038 0800a684 <__retarget_lock_init_recursive>: 800a684: 4770 bx lr 0800a686 <__retarget_lock_acquire>: 800a686: 4770 bx lr 0800a688 <__retarget_lock_acquire_recursive>: 800a688: 4770 bx lr 0800a68a <__retarget_lock_release>: 800a68a: 4770 bx lr 0800a68c <__retarget_lock_release_recursive>: 800a68c: 4770 bx lr ... 0800a690 <_tzset_unlocked_r>: 800a690: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800a694: b08d sub sp, #52 @ 0x34 800a696: 4607 mov r7, r0 800a698: f002 fafc bl 800cc94 <__gettzinfo> 800a69c: 496d ldr r1, [pc, #436] @ (800a854 <_tzset_unlocked_r+0x1c4>) 800a69e: 4604 mov r4, r0 800a6a0: 4638 mov r0, r7 800a6a2: f001 f8f9 bl 800b898 <_getenv_r> 800a6a6: 4d6c ldr r5, [pc, #432] @ (800a858 <_tzset_unlocked_r+0x1c8>) 800a6a8: 4606 mov r6, r0 800a6aa: bb10 cbnz r0, 800a6f2 <_tzset_unlocked_r+0x62> 800a6ac: 4b6b ldr r3, [pc, #428] @ (800a85c <_tzset_unlocked_r+0x1cc>) 800a6ae: 4a6c ldr r2, [pc, #432] @ (800a860 <_tzset_unlocked_r+0x1d0>) 800a6b0: 6018 str r0, [r3, #0] 800a6b2: 4b6c ldr r3, [pc, #432] @ (800a864 <_tzset_unlocked_r+0x1d4>) 800a6b4: 214a movs r1, #74 @ 0x4a 800a6b6: 6018 str r0, [r3, #0] 800a6b8: 4b6b ldr r3, [pc, #428] @ (800a868 <_tzset_unlocked_r+0x1d8>) 800a6ba: e9c4 0003 strd r0, r0, [r4, #12] 800a6be: e9c3 2200 strd r2, r2, [r3] 800a6c2: 2200 movs r2, #0 800a6c4: 2300 movs r3, #0 800a6c6: e9c4 0005 strd r0, r0, [r4, #20] 800a6ca: e9c4 000d strd r0, r0, [r4, #52] @ 0x34 800a6ce: e9c4 000f strd r0, r0, [r4, #60] @ 0x3c 800a6d2: 62a0 str r0, [r4, #40] @ 0x28 800a6d4: 6520 str r0, [r4, #80] @ 0x50 800a6d6: e9c4 2308 strd r2, r3, [r4, #32] 800a6da: e9c4 2312 strd r2, r3, [r4, #72] @ 0x48 800a6de: 6828 ldr r0, [r5, #0] 800a6e0: 7221 strb r1, [r4, #8] 800a6e2: f884 1030 strb.w r1, [r4, #48] @ 0x30 800a6e6: f001 fb7d bl 800bde4 800a6ea: 602e str r6, [r5, #0] 800a6ec: b00d add sp, #52 @ 0x34 800a6ee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800a6f2: 6829 ldr r1, [r5, #0] 800a6f4: 2900 cmp r1, #0 800a6f6: f040 808e bne.w 800a816 <_tzset_unlocked_r+0x186> 800a6fa: 6828 ldr r0, [r5, #0] 800a6fc: f001 fb72 bl 800bde4 800a700: 4630 mov r0, r6 800a702: f7f5 fd9b bl 800023c 800a706: 1c41 adds r1, r0, #1 800a708: 4638 mov r0, r7 800a70a: f001 fb95 bl 800be38 <_malloc_r> 800a70e: 6028 str r0, [r5, #0] 800a710: 2800 cmp r0, #0 800a712: f040 8086 bne.w 800a822 <_tzset_unlocked_r+0x192> 800a716: 2300 movs r3, #0 800a718: 4a52 ldr r2, [pc, #328] @ (800a864 <_tzset_unlocked_r+0x1d4>) 800a71a: 2000 movs r0, #0 800a71c: 6013 str r3, [r2, #0] 800a71e: 2100 movs r1, #0 800a720: 4a52 ldr r2, [pc, #328] @ (800a86c <_tzset_unlocked_r+0x1dc>) 800a722: f8df 8144 ldr.w r8, [pc, #324] @ 800a868 <_tzset_unlocked_r+0x1d8> 800a726: e9c4 3303 strd r3, r3, [r4, #12] 800a72a: e9c8 2200 strd r2, r2, [r8] 800a72e: 224a movs r2, #74 @ 0x4a 800a730: e9c4 3305 strd r3, r3, [r4, #20] 800a734: e9c4 0108 strd r0, r1, [r4, #32] 800a738: e9c4 330d strd r3, r3, [r4, #52] @ 0x34 800a73c: e9c4 330f strd r3, r3, [r4, #60] @ 0x3c 800a740: e9c4 0112 strd r0, r1, [r4, #72] @ 0x48 800a744: f8df a114 ldr.w sl, [pc, #276] @ 800a85c <_tzset_unlocked_r+0x1cc> 800a748: 7222 strb r2, [r4, #8] 800a74a: f8ca 3000 str.w r3, [sl] 800a74e: 62a3 str r3, [r4, #40] @ 0x28 800a750: f884 2030 strb.w r2, [r4, #48] @ 0x30 800a754: 6523 str r3, [r4, #80] @ 0x50 800a756: 7833 ldrb r3, [r6, #0] 800a758: 2b3a cmp r3, #58 @ 0x3a 800a75a: bf08 it eq 800a75c: 3601 addeq r6, #1 800a75e: 7833 ldrb r3, [r6, #0] 800a760: 2b3c cmp r3, #60 @ 0x3c 800a762: d162 bne.n 800a82a <_tzset_unlocked_r+0x19a> 800a764: 1c75 adds r5, r6, #1 800a766: 4628 mov r0, r5 800a768: 4a41 ldr r2, [pc, #260] @ (800a870 <_tzset_unlocked_r+0x1e0>) 800a76a: 4942 ldr r1, [pc, #264] @ (800a874 <_tzset_unlocked_r+0x1e4>) 800a76c: ab0a add r3, sp, #40 @ 0x28 800a76e: f002 f811 bl 800c794 800a772: 2800 cmp r0, #0 800a774: ddba ble.n 800a6ec <_tzset_unlocked_r+0x5c> 800a776: 9b0a ldr r3, [sp, #40] @ 0x28 800a778: 1eda subs r2, r3, #3 800a77a: 2a07 cmp r2, #7 800a77c: d8b6 bhi.n 800a6ec <_tzset_unlocked_r+0x5c> 800a77e: 5ceb ldrb r3, [r5, r3] 800a780: 2b3e cmp r3, #62 @ 0x3e 800a782: d1b3 bne.n 800a6ec <_tzset_unlocked_r+0x5c> 800a784: 3602 adds r6, #2 800a786: 9b0a ldr r3, [sp, #40] @ 0x28 800a788: 18f5 adds r5, r6, r3 800a78a: 5cf3 ldrb r3, [r6, r3] 800a78c: 2b2d cmp r3, #45 @ 0x2d 800a78e: d15a bne.n 800a846 <_tzset_unlocked_r+0x1b6> 800a790: f04f 39ff mov.w r9, #4294967295 @ 0xffffffff 800a794: 3501 adds r5, #1 800a796: 2300 movs r3, #0 800a798: af08 add r7, sp, #32 800a79a: f8ad 301e strh.w r3, [sp, #30] 800a79e: f8ad 3020 strh.w r3, [sp, #32] 800a7a2: ab0a add r3, sp, #40 @ 0x28 800a7a4: e9cd 3701 strd r3, r7, [sp, #4] 800a7a8: 9303 str r3, [sp, #12] 800a7aa: f10d 031e add.w r3, sp, #30 800a7ae: 9300 str r3, [sp, #0] 800a7b0: 4628 mov r0, r5 800a7b2: 4931 ldr r1, [pc, #196] @ (800a878 <_tzset_unlocked_r+0x1e8>) 800a7b4: ab0a add r3, sp, #40 @ 0x28 800a7b6: aa07 add r2, sp, #28 800a7b8: f001 ffec bl 800c794 800a7bc: 2800 cmp r0, #0 800a7be: dd95 ble.n 800a6ec <_tzset_unlocked_r+0x5c> 800a7c0: 223c movs r2, #60 @ 0x3c 800a7c2: f8bd 301e ldrh.w r3, [sp, #30] 800a7c6: f8bd 6020 ldrh.w r6, [sp, #32] 800a7ca: fb02 6603 mla r6, r2, r3, r6 800a7ce: f44f 6261 mov.w r2, #3600 @ 0xe10 800a7d2: f8bd 301c ldrh.w r3, [sp, #28] 800a7d6: fb02 6603 mla r6, r2, r3, r6 800a7da: 9b0a ldr r3, [sp, #40] @ 0x28 800a7dc: fb09 f606 mul.w r6, r9, r6 800a7e0: eb05 0903 add.w r9, r5, r3 800a7e4: 5ceb ldrb r3, [r5, r3] 800a7e6: 2b3c cmp r3, #60 @ 0x3c 800a7e8: f040 80e8 bne.w 800a9bc <_tzset_unlocked_r+0x32c> 800a7ec: f109 0501 add.w r5, r9, #1 800a7f0: 4628 mov r0, r5 800a7f2: 4a22 ldr r2, [pc, #136] @ (800a87c <_tzset_unlocked_r+0x1ec>) 800a7f4: 491f ldr r1, [pc, #124] @ (800a874 <_tzset_unlocked_r+0x1e4>) 800a7f6: ab0a add r3, sp, #40 @ 0x28 800a7f8: f001 ffcc bl 800c794 800a7fc: 2800 cmp r0, #0 800a7fe: dc41 bgt.n 800a884 <_tzset_unlocked_r+0x1f4> 800a800: f899 3001 ldrb.w r3, [r9, #1] 800a804: 2b3e cmp r3, #62 @ 0x3e 800a806: d13d bne.n 800a884 <_tzset_unlocked_r+0x1f4> 800a808: 4b19 ldr r3, [pc, #100] @ (800a870 <_tzset_unlocked_r+0x1e0>) 800a80a: 62a6 str r6, [r4, #40] @ 0x28 800a80c: e9c8 3300 strd r3, r3, [r8] 800a810: f8ca 6000 str.w r6, [sl] 800a814: e76a b.n 800a6ec <_tzset_unlocked_r+0x5c> 800a816: f7f5 fd07 bl 8000228 800a81a: 2800 cmp r0, #0 800a81c: f47f af6d bne.w 800a6fa <_tzset_unlocked_r+0x6a> 800a820: e764 b.n 800a6ec <_tzset_unlocked_r+0x5c> 800a822: 4631 mov r1, r6 800a824: f000 f95c bl 800aae0 800a828: e775 b.n 800a716 <_tzset_unlocked_r+0x86> 800a82a: 4630 mov r0, r6 800a82c: 4a10 ldr r2, [pc, #64] @ (800a870 <_tzset_unlocked_r+0x1e0>) 800a82e: 4914 ldr r1, [pc, #80] @ (800a880 <_tzset_unlocked_r+0x1f0>) 800a830: ab0a add r3, sp, #40 @ 0x28 800a832: f001 ffaf bl 800c794 800a836: 2800 cmp r0, #0 800a838: f77f af58 ble.w 800a6ec <_tzset_unlocked_r+0x5c> 800a83c: 9b0a ldr r3, [sp, #40] @ 0x28 800a83e: 3b03 subs r3, #3 800a840: 2b07 cmp r3, #7 800a842: d9a0 bls.n 800a786 <_tzset_unlocked_r+0xf6> 800a844: e752 b.n 800a6ec <_tzset_unlocked_r+0x5c> 800a846: 2b2b cmp r3, #43 @ 0x2b 800a848: f04f 0901 mov.w r9, #1 800a84c: bf08 it eq 800a84e: 3501 addeq r5, #1 800a850: e7a1 b.n 800a796 <_tzset_unlocked_r+0x106> 800a852: bf00 nop 800a854: 0800e0ae .word 0x0800e0ae 800a858: 200034ec .word 0x200034ec 800a85c: 20003508 .word 0x20003508 800a860: 0800e0b1 .word 0x0800e0b1 800a864: 2000350c .word 0x2000350c 800a868: 20000030 .word 0x20000030 800a86c: 0800e137 .word 0x0800e137 800a870: 200034fc .word 0x200034fc 800a874: 0800e0b5 .word 0x0800e0b5 800a878: 0800e0ea .word 0x0800e0ea 800a87c: 200034f0 .word 0x200034f0 800a880: 0800e0c8 .word 0x0800e0c8 800a884: 9b0a ldr r3, [sp, #40] @ 0x28 800a886: 1eda subs r2, r3, #3 800a888: 2a07 cmp r2, #7 800a88a: f63f af2f bhi.w 800a6ec <_tzset_unlocked_r+0x5c> 800a88e: 5ceb ldrb r3, [r5, r3] 800a890: 2b3e cmp r3, #62 @ 0x3e 800a892: f47f af2b bne.w 800a6ec <_tzset_unlocked_r+0x5c> 800a896: f109 0902 add.w r9, r9, #2 800a89a: 9b0a ldr r3, [sp, #40] @ 0x28 800a89c: eb09 0503 add.w r5, r9, r3 800a8a0: f819 3003 ldrb.w r3, [r9, r3] 800a8a4: 2b2d cmp r3, #45 @ 0x2d 800a8a6: f040 8098 bne.w 800a9da <_tzset_unlocked_r+0x34a> 800a8aa: f04f 39ff mov.w r9, #4294967295 @ 0xffffffff 800a8ae: 3501 adds r5, #1 800a8b0: 2300 movs r3, #0 800a8b2: f8ad 301c strh.w r3, [sp, #28] 800a8b6: f8ad 301e strh.w r3, [sp, #30] 800a8ba: f8ad 3020 strh.w r3, [sp, #32] 800a8be: 930a str r3, [sp, #40] @ 0x28 800a8c0: ab0a add r3, sp, #40 @ 0x28 800a8c2: e9cd 7302 strd r7, r3, [sp, #8] 800a8c6: 9301 str r3, [sp, #4] 800a8c8: f10d 031e add.w r3, sp, #30 800a8cc: 9300 str r3, [sp, #0] 800a8ce: 4628 mov r0, r5 800a8d0: 497a ldr r1, [pc, #488] @ (800aabc <_tzset_unlocked_r+0x42c>) 800a8d2: ab0a add r3, sp, #40 @ 0x28 800a8d4: aa07 add r2, sp, #28 800a8d6: f001 ff5d bl 800c794 800a8da: 2800 cmp r0, #0 800a8dc: f300 8083 bgt.w 800a9e6 <_tzset_unlocked_r+0x356> 800a8e0: f5a6 6361 sub.w r3, r6, #3600 @ 0xe10 800a8e4: 4627 mov r7, r4 800a8e6: f04f 0b00 mov.w fp, #0 800a8ea: 9304 str r3, [sp, #16] 800a8ec: 9b0a ldr r3, [sp, #40] @ 0x28 800a8ee: 441d add r5, r3 800a8f0: 782b ldrb r3, [r5, #0] 800a8f2: 2b2c cmp r3, #44 @ 0x2c 800a8f4: bf08 it eq 800a8f6: 3501 addeq r5, #1 800a8f8: f895 9000 ldrb.w r9, [r5] 800a8fc: f1b9 0f4d cmp.w r9, #77 @ 0x4d 800a900: f040 8084 bne.w 800aa0c <_tzset_unlocked_r+0x37c> 800a904: ab0a add r3, sp, #40 @ 0x28 800a906: f10d 0226 add.w r2, sp, #38 @ 0x26 800a90a: e9cd 3201 strd r3, r2, [sp, #4] 800a90e: aa09 add r2, sp, #36 @ 0x24 800a910: 9200 str r2, [sp, #0] 800a912: 4628 mov r0, r5 800a914: 496a ldr r1, [pc, #424] @ (800aac0 <_tzset_unlocked_r+0x430>) 800a916: 9303 str r3, [sp, #12] 800a918: f10d 0222 add.w r2, sp, #34 @ 0x22 800a91c: f001 ff3a bl 800c794 800a920: 2803 cmp r0, #3 800a922: f47f aee3 bne.w 800a6ec <_tzset_unlocked_r+0x5c> 800a926: f8bd 1022 ldrh.w r1, [sp, #34] @ 0x22 800a92a: 1e4b subs r3, r1, #1 800a92c: 2b0b cmp r3, #11 800a92e: f63f aedd bhi.w 800a6ec <_tzset_unlocked_r+0x5c> 800a932: f8bd 2024 ldrh.w r2, [sp, #36] @ 0x24 800a936: 1e53 subs r3, r2, #1 800a938: 2b04 cmp r3, #4 800a93a: f63f aed7 bhi.w 800a6ec <_tzset_unlocked_r+0x5c> 800a93e: f8bd 3026 ldrh.w r3, [sp, #38] @ 0x26 800a942: 2b06 cmp r3, #6 800a944: f63f aed2 bhi.w 800a6ec <_tzset_unlocked_r+0x5c> 800a948: e9c7 1203 strd r1, r2, [r7, #12] 800a94c: f887 9008 strb.w r9, [r7, #8] 800a950: 617b str r3, [r7, #20] 800a952: 9b0a ldr r3, [sp, #40] @ 0x28 800a954: eb05 0903 add.w r9, r5, r3 800a958: 2500 movs r5, #0 800a95a: f04f 0302 mov.w r3, #2 800a95e: f8ad 501e strh.w r5, [sp, #30] 800a962: f8ad 301c strh.w r3, [sp, #28] 800a966: f8ad 5020 strh.w r5, [sp, #32] 800a96a: 950a str r5, [sp, #40] @ 0x28 800a96c: f899 3000 ldrb.w r3, [r9] 800a970: 2b2f cmp r3, #47 @ 0x2f 800a972: d177 bne.n 800aa64 <_tzset_unlocked_r+0x3d4> 800a974: ab0a add r3, sp, #40 @ 0x28 800a976: aa08 add r2, sp, #32 800a978: e9cd 3201 strd r3, r2, [sp, #4] 800a97c: f10d 021e add.w r2, sp, #30 800a980: 9200 str r2, [sp, #0] 800a982: 4648 mov r0, r9 800a984: 494f ldr r1, [pc, #316] @ (800aac4 <_tzset_unlocked_r+0x434>) 800a986: 9303 str r3, [sp, #12] 800a988: aa07 add r2, sp, #28 800a98a: f001 ff03 bl 800c794 800a98e: 42a8 cmp r0, r5 800a990: dc68 bgt.n 800aa64 <_tzset_unlocked_r+0x3d4> 800a992: 214a movs r1, #74 @ 0x4a 800a994: 2200 movs r2, #0 800a996: 2300 movs r3, #0 800a998: e9c4 5503 strd r5, r5, [r4, #12] 800a99c: e9c4 5505 strd r5, r5, [r4, #20] 800a9a0: e9c4 2308 strd r2, r3, [r4, #32] 800a9a4: e9c4 550d strd r5, r5, [r4, #52] @ 0x34 800a9a8: e9c4 550f strd r5, r5, [r4, #60] @ 0x3c 800a9ac: e9c4 2312 strd r2, r3, [r4, #72] @ 0x48 800a9b0: 7221 strb r1, [r4, #8] 800a9b2: 62a5 str r5, [r4, #40] @ 0x28 800a9b4: f884 1030 strb.w r1, [r4, #48] @ 0x30 800a9b8: 6525 str r5, [r4, #80] @ 0x50 800a9ba: e697 b.n 800a6ec <_tzset_unlocked_r+0x5c> 800a9bc: 4648 mov r0, r9 800a9be: 4a42 ldr r2, [pc, #264] @ (800aac8 <_tzset_unlocked_r+0x438>) 800a9c0: 4942 ldr r1, [pc, #264] @ (800aacc <_tzset_unlocked_r+0x43c>) 800a9c2: ab0a add r3, sp, #40 @ 0x28 800a9c4: f001 fee6 bl 800c794 800a9c8: 2800 cmp r0, #0 800a9ca: f77f af1d ble.w 800a808 <_tzset_unlocked_r+0x178> 800a9ce: 9b0a ldr r3, [sp, #40] @ 0x28 800a9d0: 3b03 subs r3, #3 800a9d2: 2b07 cmp r3, #7 800a9d4: f67f af61 bls.w 800a89a <_tzset_unlocked_r+0x20a> 800a9d8: e688 b.n 800a6ec <_tzset_unlocked_r+0x5c> 800a9da: 2b2b cmp r3, #43 @ 0x2b 800a9dc: f04f 0901 mov.w r9, #1 800a9e0: bf08 it eq 800a9e2: 3501 addeq r5, #1 800a9e4: e764 b.n 800a8b0 <_tzset_unlocked_r+0x220> 800a9e6: 213c movs r1, #60 @ 0x3c 800a9e8: f8bd 201e ldrh.w r2, [sp, #30] 800a9ec: f8bd 3020 ldrh.w r3, [sp, #32] 800a9f0: fb01 3302 mla r3, r1, r2, r3 800a9f4: f44f 6161 mov.w r1, #3600 @ 0xe10 800a9f8: f8bd 201c ldrh.w r2, [sp, #28] 800a9fc: fb01 3302 mla r3, r1, r2, r3 800aa00: fb09 f303 mul.w r3, r9, r3 800aa04: e76e b.n 800a8e4 <_tzset_unlocked_r+0x254> 800aa06: f04f 0b01 mov.w fp, #1 800aa0a: e771 b.n 800a8f0 <_tzset_unlocked_r+0x260> 800aa0c: f1b9 0f4a cmp.w r9, #74 @ 0x4a 800aa10: bf0a itet eq 800aa12: 464b moveq r3, r9 800aa14: 2344 movne r3, #68 @ 0x44 800aa16: 3501 addeq r5, #1 800aa18: 220a movs r2, #10 800aa1a: 4628 mov r0, r5 800aa1c: a90b add r1, sp, #44 @ 0x2c 800aa1e: 9305 str r3, [sp, #20] 800aa20: f002 f818 bl 800ca54 800aa24: f8dd 902c ldr.w r9, [sp, #44] @ 0x2c 800aa28: 9b05 ldr r3, [sp, #20] 800aa2a: 45a9 cmp r9, r5 800aa2c: f8ad 0026 strh.w r0, [sp, #38] @ 0x26 800aa30: d114 bne.n 800aa5c <_tzset_unlocked_r+0x3cc> 800aa32: 234d movs r3, #77 @ 0x4d 800aa34: f1bb 0f00 cmp.w fp, #0 800aa38: d107 bne.n 800aa4a <_tzset_unlocked_r+0x3ba> 800aa3a: 2103 movs r1, #3 800aa3c: 7223 strb r3, [r4, #8] 800aa3e: 2302 movs r3, #2 800aa40: f8c4 b014 str.w fp, [r4, #20] 800aa44: e9c4 1303 strd r1, r3, [r4, #12] 800aa48: e786 b.n 800a958 <_tzset_unlocked_r+0x2c8> 800aa4a: 220b movs r2, #11 800aa4c: f884 3030 strb.w r3, [r4, #48] @ 0x30 800aa50: 2301 movs r3, #1 800aa52: e9c4 230d strd r2, r3, [r4, #52] @ 0x34 800aa56: 2300 movs r3, #0 800aa58: 63e3 str r3, [r4, #60] @ 0x3c 800aa5a: e77d b.n 800a958 <_tzset_unlocked_r+0x2c8> 800aa5c: b280 uxth r0, r0 800aa5e: 723b strb r3, [r7, #8] 800aa60: 6178 str r0, [r7, #20] 800aa62: e779 b.n 800a958 <_tzset_unlocked_r+0x2c8> 800aa64: 213c movs r1, #60 @ 0x3c 800aa66: f8bd 201e ldrh.w r2, [sp, #30] 800aa6a: f8bd 3020 ldrh.w r3, [sp, #32] 800aa6e: 3728 adds r7, #40 @ 0x28 800aa70: fb01 3302 mla r3, r1, r2, r3 800aa74: f44f 6161 mov.w r1, #3600 @ 0xe10 800aa78: f8bd 201c ldrh.w r2, [sp, #28] 800aa7c: fb01 3302 mla r3, r1, r2, r3 800aa80: f847 3c10 str.w r3, [r7, #-16] 800aa84: 9d0a ldr r5, [sp, #40] @ 0x28 800aa86: 444d add r5, r9 800aa88: f1bb 0f00 cmp.w fp, #0 800aa8c: d0bb beq.n 800aa06 <_tzset_unlocked_r+0x376> 800aa8e: 9b04 ldr r3, [sp, #16] 800aa90: 6860 ldr r0, [r4, #4] 800aa92: 6523 str r3, [r4, #80] @ 0x50 800aa94: 4b0e ldr r3, [pc, #56] @ (800aad0 <_tzset_unlocked_r+0x440>) 800aa96: 62a6 str r6, [r4, #40] @ 0x28 800aa98: f8c8 3000 str.w r3, [r8] 800aa9c: 4b0a ldr r3, [pc, #40] @ (800aac8 <_tzset_unlocked_r+0x438>) 800aa9e: f8c8 3004 str.w r3, [r8, #4] 800aaa2: f7ff fd2b bl 800a4fc <__tzcalc_limits> 800aaa6: 6aa2 ldr r2, [r4, #40] @ 0x28 800aaa8: 6d23 ldr r3, [r4, #80] @ 0x50 800aaaa: f8ca 2000 str.w r2, [sl] 800aaae: 1a9b subs r3, r3, r2 800aab0: bf18 it ne 800aab2: 2301 movne r3, #1 800aab4: 4a07 ldr r2, [pc, #28] @ (800aad4 <_tzset_unlocked_r+0x444>) 800aab6: 6013 str r3, [r2, #0] 800aab8: e618 b.n 800a6ec <_tzset_unlocked_r+0x5c> 800aaba: bf00 nop 800aabc: 0800e0ea .word 0x0800e0ea 800aac0: 0800e0d6 .word 0x0800e0d6 800aac4: 0800e0e9 .word 0x0800e0e9 800aac8: 200034f0 .word 0x200034f0 800aacc: 0800e0c8 .word 0x0800e0c8 800aad0: 200034fc .word 0x200034fc 800aad4: 2000350c .word 0x2000350c 0800aad8 <_localeconv_r>: 800aad8: 4800 ldr r0, [pc, #0] @ (800aadc <_localeconv_r+0x4>) 800aada: 4770 bx lr 800aadc: 200001d0 .word 0x200001d0 0800aae0 : 800aae0: 4603 mov r3, r0 800aae2: f811 2b01 ldrb.w r2, [r1], #1 800aae6: f803 2b01 strb.w r2, [r3], #1 800aaea: 2a00 cmp r2, #0 800aaec: d1f9 bne.n 800aae2 800aaee: 4770 bx lr 0800aaf0 : 800aaf0: 4603 mov r3, r0 800aaf2: b510 push {r4, lr} 800aaf4: b2c9 uxtb r1, r1 800aaf6: 4402 add r2, r0 800aaf8: 4293 cmp r3, r2 800aafa: 4618 mov r0, r3 800aafc: d101 bne.n 800ab02 800aafe: 2000 movs r0, #0 800ab00: e003 b.n 800ab0a 800ab02: 7804 ldrb r4, [r0, #0] 800ab04: 3301 adds r3, #1 800ab06: 428c cmp r4, r1 800ab08: d1f6 bne.n 800aaf8 800ab0a: bd10 pop {r4, pc} 0800ab0c : 800ab0c: 440a add r2, r1 800ab0e: 4291 cmp r1, r2 800ab10: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 800ab14: d100 bne.n 800ab18 800ab16: 4770 bx lr 800ab18: b510 push {r4, lr} 800ab1a: f811 4b01 ldrb.w r4, [r1], #1 800ab1e: 4291 cmp r1, r2 800ab20: f803 4f01 strb.w r4, [r3, #1]! 800ab24: d1f9 bne.n 800ab1a 800ab26: bd10 pop {r4, pc} 0800ab28 <__assert_func>: 800ab28: b51f push {r0, r1, r2, r3, r4, lr} 800ab2a: 4614 mov r4, r2 800ab2c: 461a mov r2, r3 800ab2e: 4b09 ldr r3, [pc, #36] @ (800ab54 <__assert_func+0x2c>) 800ab30: 4605 mov r5, r0 800ab32: 681b ldr r3, [r3, #0] 800ab34: 68d8 ldr r0, [r3, #12] 800ab36: b14c cbz r4, 800ab4c <__assert_func+0x24> 800ab38: 4b07 ldr r3, [pc, #28] @ (800ab58 <__assert_func+0x30>) 800ab3a: e9cd 3401 strd r3, r4, [sp, #4] 800ab3e: 9100 str r1, [sp, #0] 800ab40: 462b mov r3, r5 800ab42: 4906 ldr r1, [pc, #24] @ (800ab5c <__assert_func+0x34>) 800ab44: f001 fe98 bl 800c878 800ab48: f002 f8dc bl 800cd04 800ab4c: 4b04 ldr r3, [pc, #16] @ (800ab60 <__assert_func+0x38>) 800ab4e: 461c mov r4, r3 800ab50: e7f3 b.n 800ab3a <__assert_func+0x12> 800ab52: bf00 nop 800ab54: 20000038 .word 0x20000038 800ab58: 0800e0fc .word 0x0800e0fc 800ab5c: 0800e109 .word 0x0800e109 800ab60: 0800e137 .word 0x0800e137 0800ab64 : 800ab64: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 800ab68: 6903 ldr r3, [r0, #16] 800ab6a: 690c ldr r4, [r1, #16] 800ab6c: 4607 mov r7, r0 800ab6e: 42a3 cmp r3, r4 800ab70: db7e blt.n 800ac70 800ab72: 3c01 subs r4, #1 800ab74: 00a3 lsls r3, r4, #2 800ab76: f100 0514 add.w r5, r0, #20 800ab7a: f101 0814 add.w r8, r1, #20 800ab7e: 9300 str r3, [sp, #0] 800ab80: eb05 0384 add.w r3, r5, r4, lsl #2 800ab84: 9301 str r3, [sp, #4] 800ab86: f858 3024 ldr.w r3, [r8, r4, lsl #2] 800ab8a: f855 2024 ldr.w r2, [r5, r4, lsl #2] 800ab8e: 3301 adds r3, #1 800ab90: 429a cmp r2, r3 800ab92: fbb2 f6f3 udiv r6, r2, r3 800ab96: eb08 0984 add.w r9, r8, r4, lsl #2 800ab9a: d32e bcc.n 800abfa 800ab9c: f04f 0a00 mov.w sl, #0 800aba0: 46c4 mov ip, r8 800aba2: 46ae mov lr, r5 800aba4: 46d3 mov fp, sl 800aba6: f85c 3b04 ldr.w r3, [ip], #4 800abaa: b298 uxth r0, r3 800abac: fb06 a000 mla r0, r6, r0, sl 800abb0: 0c1b lsrs r3, r3, #16 800abb2: 0c02 lsrs r2, r0, #16 800abb4: fb06 2303 mla r3, r6, r3, r2 800abb8: f8de 2000 ldr.w r2, [lr] 800abbc: b280 uxth r0, r0 800abbe: b292 uxth r2, r2 800abc0: 1a12 subs r2, r2, r0 800abc2: 445a add r2, fp 800abc4: f8de 0000 ldr.w r0, [lr] 800abc8: ea4f 4a13 mov.w sl, r3, lsr #16 800abcc: b29b uxth r3, r3 800abce: ebc3 4322 rsb r3, r3, r2, asr #16 800abd2: eb03 4310 add.w r3, r3, r0, lsr #16 800abd6: b292 uxth r2, r2 800abd8: ea42 4203 orr.w r2, r2, r3, lsl #16 800abdc: 45e1 cmp r9, ip 800abde: ea4f 4b23 mov.w fp, r3, asr #16 800abe2: f84e 2b04 str.w r2, [lr], #4 800abe6: d2de bcs.n 800aba6 800abe8: 9b00 ldr r3, [sp, #0] 800abea: 58eb ldr r3, [r5, r3] 800abec: b92b cbnz r3, 800abfa 800abee: 9b01 ldr r3, [sp, #4] 800abf0: 3b04 subs r3, #4 800abf2: 429d cmp r5, r3 800abf4: 461a mov r2, r3 800abf6: d32f bcc.n 800ac58 800abf8: 613c str r4, [r7, #16] 800abfa: 4638 mov r0, r7 800abfc: f001 fcc2 bl 800c584 <__mcmp> 800ac00: 2800 cmp r0, #0 800ac02: db25 blt.n 800ac50 800ac04: 4629 mov r1, r5 800ac06: 2000 movs r0, #0 800ac08: f858 2b04 ldr.w r2, [r8], #4 800ac0c: f8d1 c000 ldr.w ip, [r1] 800ac10: fa1f fe82 uxth.w lr, r2 800ac14: fa1f f38c uxth.w r3, ip 800ac18: eba3 030e sub.w r3, r3, lr 800ac1c: 4403 add r3, r0 800ac1e: 0c12 lsrs r2, r2, #16 800ac20: ebc2 4223 rsb r2, r2, r3, asr #16 800ac24: eb02 421c add.w r2, r2, ip, lsr #16 800ac28: b29b uxth r3, r3 800ac2a: ea43 4302 orr.w r3, r3, r2, lsl #16 800ac2e: 45c1 cmp r9, r8 800ac30: ea4f 4022 mov.w r0, r2, asr #16 800ac34: f841 3b04 str.w r3, [r1], #4 800ac38: d2e6 bcs.n 800ac08 800ac3a: f855 2024 ldr.w r2, [r5, r4, lsl #2] 800ac3e: eb05 0384 add.w r3, r5, r4, lsl #2 800ac42: b922 cbnz r2, 800ac4e 800ac44: 3b04 subs r3, #4 800ac46: 429d cmp r5, r3 800ac48: 461a mov r2, r3 800ac4a: d30b bcc.n 800ac64 800ac4c: 613c str r4, [r7, #16] 800ac4e: 3601 adds r6, #1 800ac50: 4630 mov r0, r6 800ac52: b003 add sp, #12 800ac54: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800ac58: 6812 ldr r2, [r2, #0] 800ac5a: 3b04 subs r3, #4 800ac5c: 2a00 cmp r2, #0 800ac5e: d1cb bne.n 800abf8 800ac60: 3c01 subs r4, #1 800ac62: e7c6 b.n 800abf2 800ac64: 6812 ldr r2, [r2, #0] 800ac66: 3b04 subs r3, #4 800ac68: 2a00 cmp r2, #0 800ac6a: d1ef bne.n 800ac4c 800ac6c: 3c01 subs r4, #1 800ac6e: e7ea b.n 800ac46 800ac70: 2000 movs r0, #0 800ac72: e7ee b.n 800ac52 800ac74: 0000 movs r0, r0 ... 0800ac78 <_dtoa_r>: 800ac78: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800ac7c: 4614 mov r4, r2 800ac7e: 461d mov r5, r3 800ac80: 69c7 ldr r7, [r0, #28] 800ac82: b097 sub sp, #92 @ 0x5c 800ac84: 4681 mov r9, r0 800ac86: e9cd 4506 strd r4, r5, [sp, #24] 800ac8a: 9e23 ldr r6, [sp, #140] @ 0x8c 800ac8c: b97f cbnz r7, 800acae <_dtoa_r+0x36> 800ac8e: 2010 movs r0, #16 800ac90: f001 f8a0 bl 800bdd4 800ac94: 4602 mov r2, r0 800ac96: f8c9 001c str.w r0, [r9, #28] 800ac9a: b920 cbnz r0, 800aca6 <_dtoa_r+0x2e> 800ac9c: 21ef movs r1, #239 @ 0xef 800ac9e: 4bac ldr r3, [pc, #688] @ (800af50 <_dtoa_r+0x2d8>) 800aca0: 48ac ldr r0, [pc, #688] @ (800af54 <_dtoa_r+0x2dc>) 800aca2: f7ff ff41 bl 800ab28 <__assert_func> 800aca6: e9c0 7701 strd r7, r7, [r0, #4] 800acaa: 6007 str r7, [r0, #0] 800acac: 60c7 str r7, [r0, #12] 800acae: f8d9 301c ldr.w r3, [r9, #28] 800acb2: 6819 ldr r1, [r3, #0] 800acb4: b159 cbz r1, 800acce <_dtoa_r+0x56> 800acb6: 685a ldr r2, [r3, #4] 800acb8: 2301 movs r3, #1 800acba: 4093 lsls r3, r2 800acbc: 604a str r2, [r1, #4] 800acbe: 608b str r3, [r1, #8] 800acc0: 4648 mov r0, r9 800acc2: f001 fa2d bl 800c120 <_Bfree> 800acc6: 2200 movs r2, #0 800acc8: f8d9 301c ldr.w r3, [r9, #28] 800accc: 601a str r2, [r3, #0] 800acce: 1e2b subs r3, r5, #0 800acd0: bfaf iteee ge 800acd2: 2300 movge r3, #0 800acd4: 2201 movlt r2, #1 800acd6: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000 800acda: 9307 strlt r3, [sp, #28] 800acdc: bfa8 it ge 800acde: 6033 strge r3, [r6, #0] 800ace0: f8dd 801c ldr.w r8, [sp, #28] 800ace4: 4b9c ldr r3, [pc, #624] @ (800af58 <_dtoa_r+0x2e0>) 800ace6: bfb8 it lt 800ace8: 6032 strlt r2, [r6, #0] 800acea: ea33 0308 bics.w r3, r3, r8 800acee: d112 bne.n 800ad16 <_dtoa_r+0x9e> 800acf0: f242 730f movw r3, #9999 @ 0x270f 800acf4: 9a22 ldr r2, [sp, #136] @ 0x88 800acf6: 6013 str r3, [r2, #0] 800acf8: f3c8 0313 ubfx r3, r8, #0, #20 800acfc: 4323 orrs r3, r4 800acfe: f000 855e beq.w 800b7be <_dtoa_r+0xb46> 800ad02: 9b24 ldr r3, [sp, #144] @ 0x90 800ad04: f8df a254 ldr.w sl, [pc, #596] @ 800af5c <_dtoa_r+0x2e4> 800ad08: 2b00 cmp r3, #0 800ad0a: f000 8560 beq.w 800b7ce <_dtoa_r+0xb56> 800ad0e: f10a 0303 add.w r3, sl, #3 800ad12: f000 bd5a b.w 800b7ca <_dtoa_r+0xb52> 800ad16: e9dd 2306 ldrd r2, r3, [sp, #24] 800ad1a: e9cd 230c strd r2, r3, [sp, #48] @ 0x30 800ad1e: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 800ad22: 2200 movs r2, #0 800ad24: 2300 movs r3, #0 800ad26: f7f5 feb5 bl 8000a94 <__aeabi_dcmpeq> 800ad2a: 4607 mov r7, r0 800ad2c: b158 cbz r0, 800ad46 <_dtoa_r+0xce> 800ad2e: 2301 movs r3, #1 800ad30: 9a22 ldr r2, [sp, #136] @ 0x88 800ad32: 6013 str r3, [r2, #0] 800ad34: 9b24 ldr r3, [sp, #144] @ 0x90 800ad36: b113 cbz r3, 800ad3e <_dtoa_r+0xc6> 800ad38: 4b89 ldr r3, [pc, #548] @ (800af60 <_dtoa_r+0x2e8>) 800ad3a: 9a24 ldr r2, [sp, #144] @ 0x90 800ad3c: 6013 str r3, [r2, #0] 800ad3e: f8df a224 ldr.w sl, [pc, #548] @ 800af64 <_dtoa_r+0x2ec> 800ad42: f000 bd44 b.w 800b7ce <_dtoa_r+0xb56> 800ad46: ab14 add r3, sp, #80 @ 0x50 800ad48: 9301 str r3, [sp, #4] 800ad4a: ab15 add r3, sp, #84 @ 0x54 800ad4c: 9300 str r3, [sp, #0] 800ad4e: 4648 mov r0, r9 800ad50: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30 800ad54: f001 fcc6 bl 800c6e4 <__d2b> 800ad58: f3c8 560a ubfx r6, r8, #20, #11 800ad5c: 9003 str r0, [sp, #12] 800ad5e: 2e00 cmp r6, #0 800ad60: d078 beq.n 800ae54 <_dtoa_r+0x1dc> 800ad62: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 800ad66: 9b0d ldr r3, [sp, #52] @ 0x34 800ad68: f2a6 36ff subw r6, r6, #1023 @ 0x3ff 800ad6c: f3c3 0313 ubfx r3, r3, #0, #20 800ad70: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000 800ad74: f443 1340 orr.w r3, r3, #3145728 @ 0x300000 800ad78: 9712 str r7, [sp, #72] @ 0x48 800ad7a: 4619 mov r1, r3 800ad7c: 2200 movs r2, #0 800ad7e: 4b7a ldr r3, [pc, #488] @ (800af68 <_dtoa_r+0x2f0>) 800ad80: f7f5 fa68 bl 8000254 <__aeabi_dsub> 800ad84: a36c add r3, pc, #432 @ (adr r3, 800af38 <_dtoa_r+0x2c0>) 800ad86: e9d3 2300 ldrd r2, r3, [r3] 800ad8a: f7f5 fc1b bl 80005c4 <__aeabi_dmul> 800ad8e: a36c add r3, pc, #432 @ (adr r3, 800af40 <_dtoa_r+0x2c8>) 800ad90: e9d3 2300 ldrd r2, r3, [r3] 800ad94: f7f5 fa60 bl 8000258 <__adddf3> 800ad98: 4604 mov r4, r0 800ad9a: 4630 mov r0, r6 800ad9c: 460d mov r5, r1 800ad9e: f7f5 fba7 bl 80004f0 <__aeabi_i2d> 800ada2: a369 add r3, pc, #420 @ (adr r3, 800af48 <_dtoa_r+0x2d0>) 800ada4: e9d3 2300 ldrd r2, r3, [r3] 800ada8: f7f5 fc0c bl 80005c4 <__aeabi_dmul> 800adac: 4602 mov r2, r0 800adae: 460b mov r3, r1 800adb0: 4620 mov r0, r4 800adb2: 4629 mov r1, r5 800adb4: f7f5 fa50 bl 8000258 <__adddf3> 800adb8: 4604 mov r4, r0 800adba: 460d mov r5, r1 800adbc: f7f5 feb2 bl 8000b24 <__aeabi_d2iz> 800adc0: 2200 movs r2, #0 800adc2: 4607 mov r7, r0 800adc4: 2300 movs r3, #0 800adc6: 4620 mov r0, r4 800adc8: 4629 mov r1, r5 800adca: f7f5 fe6d bl 8000aa8 <__aeabi_dcmplt> 800adce: b140 cbz r0, 800ade2 <_dtoa_r+0x16a> 800add0: 4638 mov r0, r7 800add2: f7f5 fb8d bl 80004f0 <__aeabi_i2d> 800add6: 4622 mov r2, r4 800add8: 462b mov r3, r5 800adda: f7f5 fe5b bl 8000a94 <__aeabi_dcmpeq> 800adde: b900 cbnz r0, 800ade2 <_dtoa_r+0x16a> 800ade0: 3f01 subs r7, #1 800ade2: 2f16 cmp r7, #22 800ade4: d854 bhi.n 800ae90 <_dtoa_r+0x218> 800ade6: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 800adea: 4b60 ldr r3, [pc, #384] @ (800af6c <_dtoa_r+0x2f4>) 800adec: eb03 03c7 add.w r3, r3, r7, lsl #3 800adf0: e9d3 2300 ldrd r2, r3, [r3] 800adf4: f7f5 fe58 bl 8000aa8 <__aeabi_dcmplt> 800adf8: 2800 cmp r0, #0 800adfa: d04b beq.n 800ae94 <_dtoa_r+0x21c> 800adfc: 2300 movs r3, #0 800adfe: 3f01 subs r7, #1 800ae00: 930f str r3, [sp, #60] @ 0x3c 800ae02: 9b14 ldr r3, [sp, #80] @ 0x50 800ae04: 1b9b subs r3, r3, r6 800ae06: 1e5a subs r2, r3, #1 800ae08: bf49 itett mi 800ae0a: f1c3 0301 rsbmi r3, r3, #1 800ae0e: 2300 movpl r3, #0 800ae10: 9304 strmi r3, [sp, #16] 800ae12: 2300 movmi r3, #0 800ae14: 9209 str r2, [sp, #36] @ 0x24 800ae16: bf54 ite pl 800ae18: 9304 strpl r3, [sp, #16] 800ae1a: 9309 strmi r3, [sp, #36] @ 0x24 800ae1c: 2f00 cmp r7, #0 800ae1e: db3b blt.n 800ae98 <_dtoa_r+0x220> 800ae20: 9b09 ldr r3, [sp, #36] @ 0x24 800ae22: 970e str r7, [sp, #56] @ 0x38 800ae24: 443b add r3, r7 800ae26: 9309 str r3, [sp, #36] @ 0x24 800ae28: 2300 movs r3, #0 800ae2a: 930a str r3, [sp, #40] @ 0x28 800ae2c: 9b20 ldr r3, [sp, #128] @ 0x80 800ae2e: 2b09 cmp r3, #9 800ae30: d865 bhi.n 800aefe <_dtoa_r+0x286> 800ae32: 2b05 cmp r3, #5 800ae34: bfc4 itt gt 800ae36: 3b04 subgt r3, #4 800ae38: 9320 strgt r3, [sp, #128] @ 0x80 800ae3a: 9b20 ldr r3, [sp, #128] @ 0x80 800ae3c: bfc8 it gt 800ae3e: 2400 movgt r4, #0 800ae40: f1a3 0302 sub.w r3, r3, #2 800ae44: bfd8 it le 800ae46: 2401 movle r4, #1 800ae48: 2b03 cmp r3, #3 800ae4a: d864 bhi.n 800af16 <_dtoa_r+0x29e> 800ae4c: e8df f003 tbb [pc, r3] 800ae50: 2c385553 .word 0x2c385553 800ae54: e9dd 6314 ldrd r6, r3, [sp, #80] @ 0x50 800ae58: 441e add r6, r3 800ae5a: f206 4332 addw r3, r6, #1074 @ 0x432 800ae5e: 2b20 cmp r3, #32 800ae60: bfc1 itttt gt 800ae62: f1c3 0340 rsbgt r3, r3, #64 @ 0x40 800ae66: fa08 f803 lslgt.w r8, r8, r3 800ae6a: f206 4312 addwgt r3, r6, #1042 @ 0x412 800ae6e: fa24 f303 lsrgt.w r3, r4, r3 800ae72: bfd6 itet le 800ae74: f1c3 0320 rsble r3, r3, #32 800ae78: ea48 0003 orrgt.w r0, r8, r3 800ae7c: fa04 f003 lslle.w r0, r4, r3 800ae80: f7f5 fb26 bl 80004d0 <__aeabi_ui2d> 800ae84: 2201 movs r2, #1 800ae86: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000 800ae8a: 3e01 subs r6, #1 800ae8c: 9212 str r2, [sp, #72] @ 0x48 800ae8e: e774 b.n 800ad7a <_dtoa_r+0x102> 800ae90: 2301 movs r3, #1 800ae92: e7b5 b.n 800ae00 <_dtoa_r+0x188> 800ae94: 900f str r0, [sp, #60] @ 0x3c 800ae96: e7b4 b.n 800ae02 <_dtoa_r+0x18a> 800ae98: 9b04 ldr r3, [sp, #16] 800ae9a: 1bdb subs r3, r3, r7 800ae9c: 9304 str r3, [sp, #16] 800ae9e: 427b negs r3, r7 800aea0: 930a str r3, [sp, #40] @ 0x28 800aea2: 2300 movs r3, #0 800aea4: 930e str r3, [sp, #56] @ 0x38 800aea6: e7c1 b.n 800ae2c <_dtoa_r+0x1b4> 800aea8: 2301 movs r3, #1 800aeaa: 930b str r3, [sp, #44] @ 0x2c 800aeac: 9b21 ldr r3, [sp, #132] @ 0x84 800aeae: eb07 0b03 add.w fp, r7, r3 800aeb2: f10b 0301 add.w r3, fp, #1 800aeb6: 2b01 cmp r3, #1 800aeb8: 9308 str r3, [sp, #32] 800aeba: bfb8 it lt 800aebc: 2301 movlt r3, #1 800aebe: e006 b.n 800aece <_dtoa_r+0x256> 800aec0: 2301 movs r3, #1 800aec2: 930b str r3, [sp, #44] @ 0x2c 800aec4: 9b21 ldr r3, [sp, #132] @ 0x84 800aec6: 2b00 cmp r3, #0 800aec8: dd28 ble.n 800af1c <_dtoa_r+0x2a4> 800aeca: 469b mov fp, r3 800aecc: 9308 str r3, [sp, #32] 800aece: 2100 movs r1, #0 800aed0: 2204 movs r2, #4 800aed2: f8d9 001c ldr.w r0, [r9, #28] 800aed6: f102 0514 add.w r5, r2, #20 800aeda: 429d cmp r5, r3 800aedc: d926 bls.n 800af2c <_dtoa_r+0x2b4> 800aede: 6041 str r1, [r0, #4] 800aee0: 4648 mov r0, r9 800aee2: f001 f8dd bl 800c0a0 <_Balloc> 800aee6: 4682 mov sl, r0 800aee8: 2800 cmp r0, #0 800aeea: d143 bne.n 800af74 <_dtoa_r+0x2fc> 800aeec: 4602 mov r2, r0 800aeee: f240 11af movw r1, #431 @ 0x1af 800aef2: 4b1f ldr r3, [pc, #124] @ (800af70 <_dtoa_r+0x2f8>) 800aef4: e6d4 b.n 800aca0 <_dtoa_r+0x28> 800aef6: 2300 movs r3, #0 800aef8: e7e3 b.n 800aec2 <_dtoa_r+0x24a> 800aefa: 2300 movs r3, #0 800aefc: e7d5 b.n 800aeaa <_dtoa_r+0x232> 800aefe: 2401 movs r4, #1 800af00: 2300 movs r3, #0 800af02: 940b str r4, [sp, #44] @ 0x2c 800af04: 9320 str r3, [sp, #128] @ 0x80 800af06: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff 800af0a: 2200 movs r2, #0 800af0c: 2312 movs r3, #18 800af0e: f8cd b020 str.w fp, [sp, #32] 800af12: 9221 str r2, [sp, #132] @ 0x84 800af14: e7db b.n 800aece <_dtoa_r+0x256> 800af16: 2301 movs r3, #1 800af18: 930b str r3, [sp, #44] @ 0x2c 800af1a: e7f4 b.n 800af06 <_dtoa_r+0x28e> 800af1c: f04f 0b01 mov.w fp, #1 800af20: 465b mov r3, fp 800af22: f8cd b020 str.w fp, [sp, #32] 800af26: f8cd b084 str.w fp, [sp, #132] @ 0x84 800af2a: e7d0 b.n 800aece <_dtoa_r+0x256> 800af2c: 3101 adds r1, #1 800af2e: 0052 lsls r2, r2, #1 800af30: e7d1 b.n 800aed6 <_dtoa_r+0x25e> 800af32: bf00 nop 800af34: f3af 8000 nop.w 800af38: 636f4361 .word 0x636f4361 800af3c: 3fd287a7 .word 0x3fd287a7 800af40: 8b60c8b3 .word 0x8b60c8b3 800af44: 3fc68a28 .word 0x3fc68a28 800af48: 509f79fb .word 0x509f79fb 800af4c: 3fd34413 .word 0x3fd34413 800af50: 0800dfe6 .word 0x0800dfe6 800af54: 0800e145 .word 0x0800e145 800af58: 7ff00000 .word 0x7ff00000 800af5c: 0800e141 .word 0x0800e141 800af60: 0800e239 .word 0x0800e239 800af64: 0800e238 .word 0x0800e238 800af68: 3ff80000 .word 0x3ff80000 800af6c: 0800e2d8 .word 0x0800e2d8 800af70: 0800e19d .word 0x0800e19d 800af74: f8d9 301c ldr.w r3, [r9, #28] 800af78: 6018 str r0, [r3, #0] 800af7a: 9b08 ldr r3, [sp, #32] 800af7c: 2b0e cmp r3, #14 800af7e: f200 80a1 bhi.w 800b0c4 <_dtoa_r+0x44c> 800af82: 2c00 cmp r4, #0 800af84: f000 809e beq.w 800b0c4 <_dtoa_r+0x44c> 800af88: 2f00 cmp r7, #0 800af8a: dd33 ble.n 800aff4 <_dtoa_r+0x37c> 800af8c: 4b9c ldr r3, [pc, #624] @ (800b200 <_dtoa_r+0x588>) 800af8e: f007 020f and.w r2, r7, #15 800af92: eb03 03c2 add.w r3, r3, r2, lsl #3 800af96: 05f8 lsls r0, r7, #23 800af98: e9d3 3400 ldrd r3, r4, [r3] 800af9c: e9cd 3410 strd r3, r4, [sp, #64] @ 0x40 800afa0: ea4f 1427 mov.w r4, r7, asr #4 800afa4: d516 bpl.n 800afd4 <_dtoa_r+0x35c> 800afa6: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 800afaa: 4b96 ldr r3, [pc, #600] @ (800b204 <_dtoa_r+0x58c>) 800afac: 2603 movs r6, #3 800afae: e9d3 2308 ldrd r2, r3, [r3, #32] 800afb2: f7f5 fc31 bl 8000818 <__aeabi_ddiv> 800afb6: e9cd 0106 strd r0, r1, [sp, #24] 800afba: f004 040f and.w r4, r4, #15 800afbe: 4d91 ldr r5, [pc, #580] @ (800b204 <_dtoa_r+0x58c>) 800afc0: b954 cbnz r4, 800afd8 <_dtoa_r+0x360> 800afc2: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 800afc6: e9dd 0106 ldrd r0, r1, [sp, #24] 800afca: f7f5 fc25 bl 8000818 <__aeabi_ddiv> 800afce: e9cd 0106 strd r0, r1, [sp, #24] 800afd2: e028 b.n 800b026 <_dtoa_r+0x3ae> 800afd4: 2602 movs r6, #2 800afd6: e7f2 b.n 800afbe <_dtoa_r+0x346> 800afd8: 07e1 lsls r1, r4, #31 800afda: d508 bpl.n 800afee <_dtoa_r+0x376> 800afdc: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 800afe0: e9d5 2300 ldrd r2, r3, [r5] 800afe4: f7f5 faee bl 80005c4 <__aeabi_dmul> 800afe8: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 800afec: 3601 adds r6, #1 800afee: 1064 asrs r4, r4, #1 800aff0: 3508 adds r5, #8 800aff2: e7e5 b.n 800afc0 <_dtoa_r+0x348> 800aff4: f000 80af beq.w 800b156 <_dtoa_r+0x4de> 800aff8: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 800affc: 427c negs r4, r7 800affe: 4b80 ldr r3, [pc, #512] @ (800b200 <_dtoa_r+0x588>) 800b000: f004 020f and.w r2, r4, #15 800b004: eb03 03c2 add.w r3, r3, r2, lsl #3 800b008: e9d3 2300 ldrd r2, r3, [r3] 800b00c: f7f5 fada bl 80005c4 <__aeabi_dmul> 800b010: 2602 movs r6, #2 800b012: 2300 movs r3, #0 800b014: e9cd 0106 strd r0, r1, [sp, #24] 800b018: 4d7a ldr r5, [pc, #488] @ (800b204 <_dtoa_r+0x58c>) 800b01a: 1124 asrs r4, r4, #4 800b01c: 2c00 cmp r4, #0 800b01e: f040 808f bne.w 800b140 <_dtoa_r+0x4c8> 800b022: 2b00 cmp r3, #0 800b024: d1d3 bne.n 800afce <_dtoa_r+0x356> 800b026: e9dd 4506 ldrd r4, r5, [sp, #24] 800b02a: 9b0f ldr r3, [sp, #60] @ 0x3c 800b02c: 2b00 cmp r3, #0 800b02e: f000 8094 beq.w 800b15a <_dtoa_r+0x4e2> 800b032: 2200 movs r2, #0 800b034: 4620 mov r0, r4 800b036: 4629 mov r1, r5 800b038: 4b73 ldr r3, [pc, #460] @ (800b208 <_dtoa_r+0x590>) 800b03a: f7f5 fd35 bl 8000aa8 <__aeabi_dcmplt> 800b03e: 2800 cmp r0, #0 800b040: f000 808b beq.w 800b15a <_dtoa_r+0x4e2> 800b044: 9b08 ldr r3, [sp, #32] 800b046: 2b00 cmp r3, #0 800b048: f000 8087 beq.w 800b15a <_dtoa_r+0x4e2> 800b04c: f1bb 0f00 cmp.w fp, #0 800b050: dd34 ble.n 800b0bc <_dtoa_r+0x444> 800b052: 4620 mov r0, r4 800b054: 2200 movs r2, #0 800b056: 4629 mov r1, r5 800b058: 4b6c ldr r3, [pc, #432] @ (800b20c <_dtoa_r+0x594>) 800b05a: f7f5 fab3 bl 80005c4 <__aeabi_dmul> 800b05e: 465c mov r4, fp 800b060: e9cd 0106 strd r0, r1, [sp, #24] 800b064: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 800b068: 3601 adds r6, #1 800b06a: 4630 mov r0, r6 800b06c: f7f5 fa40 bl 80004f0 <__aeabi_i2d> 800b070: e9dd 2306 ldrd r2, r3, [sp, #24] 800b074: f7f5 faa6 bl 80005c4 <__aeabi_dmul> 800b078: 2200 movs r2, #0 800b07a: 4b65 ldr r3, [pc, #404] @ (800b210 <_dtoa_r+0x598>) 800b07c: f7f5 f8ec bl 8000258 <__adddf3> 800b080: 4605 mov r5, r0 800b082: f1a1 7650 sub.w r6, r1, #54525952 @ 0x3400000 800b086: 2c00 cmp r4, #0 800b088: d16a bne.n 800b160 <_dtoa_r+0x4e8> 800b08a: e9dd 0106 ldrd r0, r1, [sp, #24] 800b08e: 2200 movs r2, #0 800b090: 4b60 ldr r3, [pc, #384] @ (800b214 <_dtoa_r+0x59c>) 800b092: f7f5 f8df bl 8000254 <__aeabi_dsub> 800b096: 4602 mov r2, r0 800b098: 460b mov r3, r1 800b09a: e9cd 2306 strd r2, r3, [sp, #24] 800b09e: 462a mov r2, r5 800b0a0: 4633 mov r3, r6 800b0a2: f7f5 fd1f bl 8000ae4 <__aeabi_dcmpgt> 800b0a6: 2800 cmp r0, #0 800b0a8: f040 8298 bne.w 800b5dc <_dtoa_r+0x964> 800b0ac: e9dd 0106 ldrd r0, r1, [sp, #24] 800b0b0: 462a mov r2, r5 800b0b2: f106 4300 add.w r3, r6, #2147483648 @ 0x80000000 800b0b6: f7f5 fcf7 bl 8000aa8 <__aeabi_dcmplt> 800b0ba: bb38 cbnz r0, 800b10c <_dtoa_r+0x494> 800b0bc: e9dd 340c ldrd r3, r4, [sp, #48] @ 0x30 800b0c0: e9cd 3406 strd r3, r4, [sp, #24] 800b0c4: 9b15 ldr r3, [sp, #84] @ 0x54 800b0c6: 2b00 cmp r3, #0 800b0c8: f2c0 8157 blt.w 800b37a <_dtoa_r+0x702> 800b0cc: 2f0e cmp r7, #14 800b0ce: f300 8154 bgt.w 800b37a <_dtoa_r+0x702> 800b0d2: 4b4b ldr r3, [pc, #300] @ (800b200 <_dtoa_r+0x588>) 800b0d4: eb03 03c7 add.w r3, r3, r7, lsl #3 800b0d8: e9d3 3400 ldrd r3, r4, [r3] 800b0dc: e9cd 3404 strd r3, r4, [sp, #16] 800b0e0: 9b21 ldr r3, [sp, #132] @ 0x84 800b0e2: 2b00 cmp r3, #0 800b0e4: f280 80e5 bge.w 800b2b2 <_dtoa_r+0x63a> 800b0e8: 9b08 ldr r3, [sp, #32] 800b0ea: 2b00 cmp r3, #0 800b0ec: f300 80e1 bgt.w 800b2b2 <_dtoa_r+0x63a> 800b0f0: d10c bne.n 800b10c <_dtoa_r+0x494> 800b0f2: e9dd 0104 ldrd r0, r1, [sp, #16] 800b0f6: 2200 movs r2, #0 800b0f8: 4b46 ldr r3, [pc, #280] @ (800b214 <_dtoa_r+0x59c>) 800b0fa: f7f5 fa63 bl 80005c4 <__aeabi_dmul> 800b0fe: e9dd 2306 ldrd r2, r3, [sp, #24] 800b102: f7f5 fce5 bl 8000ad0 <__aeabi_dcmpge> 800b106: 2800 cmp r0, #0 800b108: f000 8266 beq.w 800b5d8 <_dtoa_r+0x960> 800b10c: 2400 movs r4, #0 800b10e: 4625 mov r5, r4 800b110: 9b21 ldr r3, [sp, #132] @ 0x84 800b112: 4656 mov r6, sl 800b114: ea6f 0803 mvn.w r8, r3 800b118: 2700 movs r7, #0 800b11a: 4621 mov r1, r4 800b11c: 4648 mov r0, r9 800b11e: f000 ffff bl 800c120 <_Bfree> 800b122: 2d00 cmp r5, #0 800b124: f000 80bd beq.w 800b2a2 <_dtoa_r+0x62a> 800b128: b12f cbz r7, 800b136 <_dtoa_r+0x4be> 800b12a: 42af cmp r7, r5 800b12c: d003 beq.n 800b136 <_dtoa_r+0x4be> 800b12e: 4639 mov r1, r7 800b130: 4648 mov r0, r9 800b132: f000 fff5 bl 800c120 <_Bfree> 800b136: 4629 mov r1, r5 800b138: 4648 mov r0, r9 800b13a: f000 fff1 bl 800c120 <_Bfree> 800b13e: e0b0 b.n 800b2a2 <_dtoa_r+0x62a> 800b140: 07e2 lsls r2, r4, #31 800b142: d505 bpl.n 800b150 <_dtoa_r+0x4d8> 800b144: e9d5 2300 ldrd r2, r3, [r5] 800b148: f7f5 fa3c bl 80005c4 <__aeabi_dmul> 800b14c: 2301 movs r3, #1 800b14e: 3601 adds r6, #1 800b150: 1064 asrs r4, r4, #1 800b152: 3508 adds r5, #8 800b154: e762 b.n 800b01c <_dtoa_r+0x3a4> 800b156: 2602 movs r6, #2 800b158: e765 b.n 800b026 <_dtoa_r+0x3ae> 800b15a: 46b8 mov r8, r7 800b15c: 9c08 ldr r4, [sp, #32] 800b15e: e784 b.n 800b06a <_dtoa_r+0x3f2> 800b160: 4b27 ldr r3, [pc, #156] @ (800b200 <_dtoa_r+0x588>) 800b162: 990b ldr r1, [sp, #44] @ 0x2c 800b164: eb03 03c4 add.w r3, r3, r4, lsl #3 800b168: e953 2302 ldrd r2, r3, [r3, #-8] 800b16c: 4454 add r4, sl 800b16e: 2900 cmp r1, #0 800b170: d054 beq.n 800b21c <_dtoa_r+0x5a4> 800b172: 2000 movs r0, #0 800b174: 4928 ldr r1, [pc, #160] @ (800b218 <_dtoa_r+0x5a0>) 800b176: f7f5 fb4f bl 8000818 <__aeabi_ddiv> 800b17a: 4633 mov r3, r6 800b17c: 462a mov r2, r5 800b17e: f7f5 f869 bl 8000254 <__aeabi_dsub> 800b182: 4656 mov r6, sl 800b184: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 800b188: e9dd 0106 ldrd r0, r1, [sp, #24] 800b18c: f7f5 fcca bl 8000b24 <__aeabi_d2iz> 800b190: 4605 mov r5, r0 800b192: f7f5 f9ad bl 80004f0 <__aeabi_i2d> 800b196: 4602 mov r2, r0 800b198: 460b mov r3, r1 800b19a: e9dd 0106 ldrd r0, r1, [sp, #24] 800b19e: f7f5 f859 bl 8000254 <__aeabi_dsub> 800b1a2: 4602 mov r2, r0 800b1a4: 460b mov r3, r1 800b1a6: 3530 adds r5, #48 @ 0x30 800b1a8: e9cd 2306 strd r2, r3, [sp, #24] 800b1ac: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 800b1b0: f806 5b01 strb.w r5, [r6], #1 800b1b4: f7f5 fc78 bl 8000aa8 <__aeabi_dcmplt> 800b1b8: 2800 cmp r0, #0 800b1ba: d172 bne.n 800b2a2 <_dtoa_r+0x62a> 800b1bc: e9dd 2306 ldrd r2, r3, [sp, #24] 800b1c0: 2000 movs r0, #0 800b1c2: 4911 ldr r1, [pc, #68] @ (800b208 <_dtoa_r+0x590>) 800b1c4: f7f5 f846 bl 8000254 <__aeabi_dsub> 800b1c8: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 800b1cc: f7f5 fc6c bl 8000aa8 <__aeabi_dcmplt> 800b1d0: 2800 cmp r0, #0 800b1d2: f040 80b4 bne.w 800b33e <_dtoa_r+0x6c6> 800b1d6: 42a6 cmp r6, r4 800b1d8: f43f af70 beq.w 800b0bc <_dtoa_r+0x444> 800b1dc: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 800b1e0: 2200 movs r2, #0 800b1e2: 4b0a ldr r3, [pc, #40] @ (800b20c <_dtoa_r+0x594>) 800b1e4: f7f5 f9ee bl 80005c4 <__aeabi_dmul> 800b1e8: 2200 movs r2, #0 800b1ea: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 800b1ee: e9dd 0106 ldrd r0, r1, [sp, #24] 800b1f2: 4b06 ldr r3, [pc, #24] @ (800b20c <_dtoa_r+0x594>) 800b1f4: f7f5 f9e6 bl 80005c4 <__aeabi_dmul> 800b1f8: e9cd 0106 strd r0, r1, [sp, #24] 800b1fc: e7c4 b.n 800b188 <_dtoa_r+0x510> 800b1fe: bf00 nop 800b200: 0800e2d8 .word 0x0800e2d8 800b204: 0800e2b0 .word 0x0800e2b0 800b208: 3ff00000 .word 0x3ff00000 800b20c: 40240000 .word 0x40240000 800b210: 401c0000 .word 0x401c0000 800b214: 40140000 .word 0x40140000 800b218: 3fe00000 .word 0x3fe00000 800b21c: 4631 mov r1, r6 800b21e: 4628 mov r0, r5 800b220: f7f5 f9d0 bl 80005c4 <__aeabi_dmul> 800b224: 4656 mov r6, sl 800b226: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 800b22a: 9413 str r4, [sp, #76] @ 0x4c 800b22c: e9dd 0106 ldrd r0, r1, [sp, #24] 800b230: f7f5 fc78 bl 8000b24 <__aeabi_d2iz> 800b234: 4605 mov r5, r0 800b236: f7f5 f95b bl 80004f0 <__aeabi_i2d> 800b23a: 4602 mov r2, r0 800b23c: 460b mov r3, r1 800b23e: e9dd 0106 ldrd r0, r1, [sp, #24] 800b242: f7f5 f807 bl 8000254 <__aeabi_dsub> 800b246: 4602 mov r2, r0 800b248: 460b mov r3, r1 800b24a: 3530 adds r5, #48 @ 0x30 800b24c: f806 5b01 strb.w r5, [r6], #1 800b250: 42a6 cmp r6, r4 800b252: e9cd 2306 strd r2, r3, [sp, #24] 800b256: f04f 0200 mov.w r2, #0 800b25a: d124 bne.n 800b2a6 <_dtoa_r+0x62e> 800b25c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 800b260: 4bae ldr r3, [pc, #696] @ (800b51c <_dtoa_r+0x8a4>) 800b262: f7f4 fff9 bl 8000258 <__adddf3> 800b266: 4602 mov r2, r0 800b268: 460b mov r3, r1 800b26a: e9dd 0106 ldrd r0, r1, [sp, #24] 800b26e: f7f5 fc39 bl 8000ae4 <__aeabi_dcmpgt> 800b272: 2800 cmp r0, #0 800b274: d163 bne.n 800b33e <_dtoa_r+0x6c6> 800b276: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 800b27a: 2000 movs r0, #0 800b27c: 49a7 ldr r1, [pc, #668] @ (800b51c <_dtoa_r+0x8a4>) 800b27e: f7f4 ffe9 bl 8000254 <__aeabi_dsub> 800b282: 4602 mov r2, r0 800b284: 460b mov r3, r1 800b286: e9dd 0106 ldrd r0, r1, [sp, #24] 800b28a: f7f5 fc0d bl 8000aa8 <__aeabi_dcmplt> 800b28e: 2800 cmp r0, #0 800b290: f43f af14 beq.w 800b0bc <_dtoa_r+0x444> 800b294: 9e13 ldr r6, [sp, #76] @ 0x4c 800b296: 1e73 subs r3, r6, #1 800b298: 9313 str r3, [sp, #76] @ 0x4c 800b29a: f816 3c01 ldrb.w r3, [r6, #-1] 800b29e: 2b30 cmp r3, #48 @ 0x30 800b2a0: d0f8 beq.n 800b294 <_dtoa_r+0x61c> 800b2a2: 4647 mov r7, r8 800b2a4: e03b b.n 800b31e <_dtoa_r+0x6a6> 800b2a6: 4b9e ldr r3, [pc, #632] @ (800b520 <_dtoa_r+0x8a8>) 800b2a8: f7f5 f98c bl 80005c4 <__aeabi_dmul> 800b2ac: e9cd 0106 strd r0, r1, [sp, #24] 800b2b0: e7bc b.n 800b22c <_dtoa_r+0x5b4> 800b2b2: 4656 mov r6, sl 800b2b4: e9dd 4506 ldrd r4, r5, [sp, #24] 800b2b8: e9dd 2304 ldrd r2, r3, [sp, #16] 800b2bc: 4620 mov r0, r4 800b2be: 4629 mov r1, r5 800b2c0: f7f5 faaa bl 8000818 <__aeabi_ddiv> 800b2c4: f7f5 fc2e bl 8000b24 <__aeabi_d2iz> 800b2c8: 4680 mov r8, r0 800b2ca: f7f5 f911 bl 80004f0 <__aeabi_i2d> 800b2ce: e9dd 2304 ldrd r2, r3, [sp, #16] 800b2d2: f7f5 f977 bl 80005c4 <__aeabi_dmul> 800b2d6: 4602 mov r2, r0 800b2d8: 460b mov r3, r1 800b2da: 4620 mov r0, r4 800b2dc: 4629 mov r1, r5 800b2de: f7f4 ffb9 bl 8000254 <__aeabi_dsub> 800b2e2: f108 0430 add.w r4, r8, #48 @ 0x30 800b2e6: 9d08 ldr r5, [sp, #32] 800b2e8: f806 4b01 strb.w r4, [r6], #1 800b2ec: eba6 040a sub.w r4, r6, sl 800b2f0: 42a5 cmp r5, r4 800b2f2: 4602 mov r2, r0 800b2f4: 460b mov r3, r1 800b2f6: d133 bne.n 800b360 <_dtoa_r+0x6e8> 800b2f8: f7f4 ffae bl 8000258 <__adddf3> 800b2fc: e9dd 2304 ldrd r2, r3, [sp, #16] 800b300: 4604 mov r4, r0 800b302: 460d mov r5, r1 800b304: f7f5 fbee bl 8000ae4 <__aeabi_dcmpgt> 800b308: b9c0 cbnz r0, 800b33c <_dtoa_r+0x6c4> 800b30a: e9dd 2304 ldrd r2, r3, [sp, #16] 800b30e: 4620 mov r0, r4 800b310: 4629 mov r1, r5 800b312: f7f5 fbbf bl 8000a94 <__aeabi_dcmpeq> 800b316: b110 cbz r0, 800b31e <_dtoa_r+0x6a6> 800b318: f018 0f01 tst.w r8, #1 800b31c: d10e bne.n 800b33c <_dtoa_r+0x6c4> 800b31e: 4648 mov r0, r9 800b320: 9903 ldr r1, [sp, #12] 800b322: f000 fefd bl 800c120 <_Bfree> 800b326: 2300 movs r3, #0 800b328: 7033 strb r3, [r6, #0] 800b32a: 9b22 ldr r3, [sp, #136] @ 0x88 800b32c: 3701 adds r7, #1 800b32e: 601f str r7, [r3, #0] 800b330: 9b24 ldr r3, [sp, #144] @ 0x90 800b332: 2b00 cmp r3, #0 800b334: f000 824b beq.w 800b7ce <_dtoa_r+0xb56> 800b338: 601e str r6, [r3, #0] 800b33a: e248 b.n 800b7ce <_dtoa_r+0xb56> 800b33c: 46b8 mov r8, r7 800b33e: 4633 mov r3, r6 800b340: 461e mov r6, r3 800b342: f813 2d01 ldrb.w r2, [r3, #-1]! 800b346: 2a39 cmp r2, #57 @ 0x39 800b348: d106 bne.n 800b358 <_dtoa_r+0x6e0> 800b34a: 459a cmp sl, r3 800b34c: d1f8 bne.n 800b340 <_dtoa_r+0x6c8> 800b34e: 2230 movs r2, #48 @ 0x30 800b350: f108 0801 add.w r8, r8, #1 800b354: f88a 2000 strb.w r2, [sl] 800b358: 781a ldrb r2, [r3, #0] 800b35a: 3201 adds r2, #1 800b35c: 701a strb r2, [r3, #0] 800b35e: e7a0 b.n 800b2a2 <_dtoa_r+0x62a> 800b360: 2200 movs r2, #0 800b362: 4b6f ldr r3, [pc, #444] @ (800b520 <_dtoa_r+0x8a8>) 800b364: f7f5 f92e bl 80005c4 <__aeabi_dmul> 800b368: 2200 movs r2, #0 800b36a: 2300 movs r3, #0 800b36c: 4604 mov r4, r0 800b36e: 460d mov r5, r1 800b370: f7f5 fb90 bl 8000a94 <__aeabi_dcmpeq> 800b374: 2800 cmp r0, #0 800b376: d09f beq.n 800b2b8 <_dtoa_r+0x640> 800b378: e7d1 b.n 800b31e <_dtoa_r+0x6a6> 800b37a: 9a0b ldr r2, [sp, #44] @ 0x2c 800b37c: 2a00 cmp r2, #0 800b37e: f000 80ea beq.w 800b556 <_dtoa_r+0x8de> 800b382: 9a20 ldr r2, [sp, #128] @ 0x80 800b384: 2a01 cmp r2, #1 800b386: f300 80cd bgt.w 800b524 <_dtoa_r+0x8ac> 800b38a: 9a12 ldr r2, [sp, #72] @ 0x48 800b38c: 2a00 cmp r2, #0 800b38e: f000 80c1 beq.w 800b514 <_dtoa_r+0x89c> 800b392: f203 4333 addw r3, r3, #1075 @ 0x433 800b396: 9c0a ldr r4, [sp, #40] @ 0x28 800b398: 9e04 ldr r6, [sp, #16] 800b39a: 9a04 ldr r2, [sp, #16] 800b39c: 2101 movs r1, #1 800b39e: 441a add r2, r3 800b3a0: 9204 str r2, [sp, #16] 800b3a2: 9a09 ldr r2, [sp, #36] @ 0x24 800b3a4: 4648 mov r0, r9 800b3a6: 441a add r2, r3 800b3a8: 9209 str r2, [sp, #36] @ 0x24 800b3aa: f000 ff6d bl 800c288 <__i2b> 800b3ae: 4605 mov r5, r0 800b3b0: b166 cbz r6, 800b3cc <_dtoa_r+0x754> 800b3b2: 9b09 ldr r3, [sp, #36] @ 0x24 800b3b4: 2b00 cmp r3, #0 800b3b6: dd09 ble.n 800b3cc <_dtoa_r+0x754> 800b3b8: 42b3 cmp r3, r6 800b3ba: bfa8 it ge 800b3bc: 4633 movge r3, r6 800b3be: 9a04 ldr r2, [sp, #16] 800b3c0: 1af6 subs r6, r6, r3 800b3c2: 1ad2 subs r2, r2, r3 800b3c4: 9204 str r2, [sp, #16] 800b3c6: 9a09 ldr r2, [sp, #36] @ 0x24 800b3c8: 1ad3 subs r3, r2, r3 800b3ca: 9309 str r3, [sp, #36] @ 0x24 800b3cc: 9b0a ldr r3, [sp, #40] @ 0x28 800b3ce: b30b cbz r3, 800b414 <_dtoa_r+0x79c> 800b3d0: 9b0b ldr r3, [sp, #44] @ 0x2c 800b3d2: 2b00 cmp r3, #0 800b3d4: f000 80c6 beq.w 800b564 <_dtoa_r+0x8ec> 800b3d8: 2c00 cmp r4, #0 800b3da: f000 80c0 beq.w 800b55e <_dtoa_r+0x8e6> 800b3de: 4629 mov r1, r5 800b3e0: 4622 mov r2, r4 800b3e2: 4648 mov r0, r9 800b3e4: f001 f808 bl 800c3f8 <__pow5mult> 800b3e8: 9a03 ldr r2, [sp, #12] 800b3ea: 4601 mov r1, r0 800b3ec: 4605 mov r5, r0 800b3ee: 4648 mov r0, r9 800b3f0: f000 ff60 bl 800c2b4 <__multiply> 800b3f4: 9903 ldr r1, [sp, #12] 800b3f6: 4680 mov r8, r0 800b3f8: 4648 mov r0, r9 800b3fa: f000 fe91 bl 800c120 <_Bfree> 800b3fe: 9b0a ldr r3, [sp, #40] @ 0x28 800b400: 1b1b subs r3, r3, r4 800b402: 930a str r3, [sp, #40] @ 0x28 800b404: f000 80b1 beq.w 800b56a <_dtoa_r+0x8f2> 800b408: 4641 mov r1, r8 800b40a: 9a0a ldr r2, [sp, #40] @ 0x28 800b40c: 4648 mov r0, r9 800b40e: f000 fff3 bl 800c3f8 <__pow5mult> 800b412: 9003 str r0, [sp, #12] 800b414: 2101 movs r1, #1 800b416: 4648 mov r0, r9 800b418: f000 ff36 bl 800c288 <__i2b> 800b41c: 9b0e ldr r3, [sp, #56] @ 0x38 800b41e: 4604 mov r4, r0 800b420: 2b00 cmp r3, #0 800b422: f000 81d8 beq.w 800b7d6 <_dtoa_r+0xb5e> 800b426: 461a mov r2, r3 800b428: 4601 mov r1, r0 800b42a: 4648 mov r0, r9 800b42c: f000 ffe4 bl 800c3f8 <__pow5mult> 800b430: 9b20 ldr r3, [sp, #128] @ 0x80 800b432: 4604 mov r4, r0 800b434: 2b01 cmp r3, #1 800b436: f300 809f bgt.w 800b578 <_dtoa_r+0x900> 800b43a: 9b06 ldr r3, [sp, #24] 800b43c: 2b00 cmp r3, #0 800b43e: f040 8097 bne.w 800b570 <_dtoa_r+0x8f8> 800b442: 9b07 ldr r3, [sp, #28] 800b444: f3c3 0313 ubfx r3, r3, #0, #20 800b448: 2b00 cmp r3, #0 800b44a: f040 8093 bne.w 800b574 <_dtoa_r+0x8fc> 800b44e: 9b07 ldr r3, [sp, #28] 800b450: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 800b454: 0d1b lsrs r3, r3, #20 800b456: 051b lsls r3, r3, #20 800b458: b133 cbz r3, 800b468 <_dtoa_r+0x7f0> 800b45a: 9b04 ldr r3, [sp, #16] 800b45c: 3301 adds r3, #1 800b45e: 9304 str r3, [sp, #16] 800b460: 9b09 ldr r3, [sp, #36] @ 0x24 800b462: 3301 adds r3, #1 800b464: 9309 str r3, [sp, #36] @ 0x24 800b466: 2301 movs r3, #1 800b468: 930a str r3, [sp, #40] @ 0x28 800b46a: 9b0e ldr r3, [sp, #56] @ 0x38 800b46c: 2b00 cmp r3, #0 800b46e: f000 81b8 beq.w 800b7e2 <_dtoa_r+0xb6a> 800b472: 6923 ldr r3, [r4, #16] 800b474: eb04 0383 add.w r3, r4, r3, lsl #2 800b478: 6918 ldr r0, [r3, #16] 800b47a: f000 feb9 bl 800c1f0 <__hi0bits> 800b47e: f1c0 0020 rsb r0, r0, #32 800b482: 9b09 ldr r3, [sp, #36] @ 0x24 800b484: 4418 add r0, r3 800b486: f010 001f ands.w r0, r0, #31 800b48a: f000 8082 beq.w 800b592 <_dtoa_r+0x91a> 800b48e: f1c0 0320 rsb r3, r0, #32 800b492: 2b04 cmp r3, #4 800b494: dd73 ble.n 800b57e <_dtoa_r+0x906> 800b496: 9b04 ldr r3, [sp, #16] 800b498: f1c0 001c rsb r0, r0, #28 800b49c: 4403 add r3, r0 800b49e: 9304 str r3, [sp, #16] 800b4a0: 9b09 ldr r3, [sp, #36] @ 0x24 800b4a2: 4406 add r6, r0 800b4a4: 4403 add r3, r0 800b4a6: 9309 str r3, [sp, #36] @ 0x24 800b4a8: 9b04 ldr r3, [sp, #16] 800b4aa: 2b00 cmp r3, #0 800b4ac: dd05 ble.n 800b4ba <_dtoa_r+0x842> 800b4ae: 461a mov r2, r3 800b4b0: 4648 mov r0, r9 800b4b2: 9903 ldr r1, [sp, #12] 800b4b4: f000 fffa bl 800c4ac <__lshift> 800b4b8: 9003 str r0, [sp, #12] 800b4ba: 9b09 ldr r3, [sp, #36] @ 0x24 800b4bc: 2b00 cmp r3, #0 800b4be: dd05 ble.n 800b4cc <_dtoa_r+0x854> 800b4c0: 4621 mov r1, r4 800b4c2: 461a mov r2, r3 800b4c4: 4648 mov r0, r9 800b4c6: f000 fff1 bl 800c4ac <__lshift> 800b4ca: 4604 mov r4, r0 800b4cc: 9b0f ldr r3, [sp, #60] @ 0x3c 800b4ce: 2b00 cmp r3, #0 800b4d0: d061 beq.n 800b596 <_dtoa_r+0x91e> 800b4d2: 4621 mov r1, r4 800b4d4: 9803 ldr r0, [sp, #12] 800b4d6: f001 f855 bl 800c584 <__mcmp> 800b4da: 2800 cmp r0, #0 800b4dc: da5b bge.n 800b596 <_dtoa_r+0x91e> 800b4de: 2300 movs r3, #0 800b4e0: 220a movs r2, #10 800b4e2: 4648 mov r0, r9 800b4e4: 9903 ldr r1, [sp, #12] 800b4e6: f000 fe3d bl 800c164 <__multadd> 800b4ea: 9b0b ldr r3, [sp, #44] @ 0x2c 800b4ec: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 800b4f0: 9003 str r0, [sp, #12] 800b4f2: 2b00 cmp r3, #0 800b4f4: f000 8177 beq.w 800b7e6 <_dtoa_r+0xb6e> 800b4f8: 4629 mov r1, r5 800b4fa: 2300 movs r3, #0 800b4fc: 220a movs r2, #10 800b4fe: 4648 mov r0, r9 800b500: f000 fe30 bl 800c164 <__multadd> 800b504: f1bb 0f00 cmp.w fp, #0 800b508: 4605 mov r5, r0 800b50a: dc6f bgt.n 800b5ec <_dtoa_r+0x974> 800b50c: 9b20 ldr r3, [sp, #128] @ 0x80 800b50e: 2b02 cmp r3, #2 800b510: dc49 bgt.n 800b5a6 <_dtoa_r+0x92e> 800b512: e06b b.n 800b5ec <_dtoa_r+0x974> 800b514: 9b14 ldr r3, [sp, #80] @ 0x50 800b516: f1c3 0336 rsb r3, r3, #54 @ 0x36 800b51a: e73c b.n 800b396 <_dtoa_r+0x71e> 800b51c: 3fe00000 .word 0x3fe00000 800b520: 40240000 .word 0x40240000 800b524: 9b08 ldr r3, [sp, #32] 800b526: 1e5c subs r4, r3, #1 800b528: 9b0a ldr r3, [sp, #40] @ 0x28 800b52a: 42a3 cmp r3, r4 800b52c: db09 blt.n 800b542 <_dtoa_r+0x8ca> 800b52e: 1b1c subs r4, r3, r4 800b530: 9b08 ldr r3, [sp, #32] 800b532: 2b00 cmp r3, #0 800b534: f6bf af30 bge.w 800b398 <_dtoa_r+0x720> 800b538: 9b04 ldr r3, [sp, #16] 800b53a: 9a08 ldr r2, [sp, #32] 800b53c: 1a9e subs r6, r3, r2 800b53e: 2300 movs r3, #0 800b540: e72b b.n 800b39a <_dtoa_r+0x722> 800b542: 9b0a ldr r3, [sp, #40] @ 0x28 800b544: 9a0e ldr r2, [sp, #56] @ 0x38 800b546: 1ae3 subs r3, r4, r3 800b548: 441a add r2, r3 800b54a: 940a str r4, [sp, #40] @ 0x28 800b54c: 9e04 ldr r6, [sp, #16] 800b54e: 2400 movs r4, #0 800b550: 9b08 ldr r3, [sp, #32] 800b552: 920e str r2, [sp, #56] @ 0x38 800b554: e721 b.n 800b39a <_dtoa_r+0x722> 800b556: 9c0a ldr r4, [sp, #40] @ 0x28 800b558: 9e04 ldr r6, [sp, #16] 800b55a: 9d0b ldr r5, [sp, #44] @ 0x2c 800b55c: e728 b.n 800b3b0 <_dtoa_r+0x738> 800b55e: f8dd 800c ldr.w r8, [sp, #12] 800b562: e751 b.n 800b408 <_dtoa_r+0x790> 800b564: 9a0a ldr r2, [sp, #40] @ 0x28 800b566: 9903 ldr r1, [sp, #12] 800b568: e750 b.n 800b40c <_dtoa_r+0x794> 800b56a: f8cd 800c str.w r8, [sp, #12] 800b56e: e751 b.n 800b414 <_dtoa_r+0x79c> 800b570: 2300 movs r3, #0 800b572: e779 b.n 800b468 <_dtoa_r+0x7f0> 800b574: 9b06 ldr r3, [sp, #24] 800b576: e777 b.n 800b468 <_dtoa_r+0x7f0> 800b578: 2300 movs r3, #0 800b57a: 930a str r3, [sp, #40] @ 0x28 800b57c: e779 b.n 800b472 <_dtoa_r+0x7fa> 800b57e: d093 beq.n 800b4a8 <_dtoa_r+0x830> 800b580: 9a04 ldr r2, [sp, #16] 800b582: 331c adds r3, #28 800b584: 441a add r2, r3 800b586: 9204 str r2, [sp, #16] 800b588: 9a09 ldr r2, [sp, #36] @ 0x24 800b58a: 441e add r6, r3 800b58c: 441a add r2, r3 800b58e: 9209 str r2, [sp, #36] @ 0x24 800b590: e78a b.n 800b4a8 <_dtoa_r+0x830> 800b592: 4603 mov r3, r0 800b594: e7f4 b.n 800b580 <_dtoa_r+0x908> 800b596: 9b08 ldr r3, [sp, #32] 800b598: 46b8 mov r8, r7 800b59a: 2b00 cmp r3, #0 800b59c: dc20 bgt.n 800b5e0 <_dtoa_r+0x968> 800b59e: 469b mov fp, r3 800b5a0: 9b20 ldr r3, [sp, #128] @ 0x80 800b5a2: 2b02 cmp r3, #2 800b5a4: dd1e ble.n 800b5e4 <_dtoa_r+0x96c> 800b5a6: f1bb 0f00 cmp.w fp, #0 800b5aa: f47f adb1 bne.w 800b110 <_dtoa_r+0x498> 800b5ae: 4621 mov r1, r4 800b5b0: 465b mov r3, fp 800b5b2: 2205 movs r2, #5 800b5b4: 4648 mov r0, r9 800b5b6: f000 fdd5 bl 800c164 <__multadd> 800b5ba: 4601 mov r1, r0 800b5bc: 4604 mov r4, r0 800b5be: 9803 ldr r0, [sp, #12] 800b5c0: f000 ffe0 bl 800c584 <__mcmp> 800b5c4: 2800 cmp r0, #0 800b5c6: f77f ada3 ble.w 800b110 <_dtoa_r+0x498> 800b5ca: 4656 mov r6, sl 800b5cc: 2331 movs r3, #49 @ 0x31 800b5ce: f108 0801 add.w r8, r8, #1 800b5d2: f806 3b01 strb.w r3, [r6], #1 800b5d6: e59f b.n 800b118 <_dtoa_r+0x4a0> 800b5d8: 46b8 mov r8, r7 800b5da: 9c08 ldr r4, [sp, #32] 800b5dc: 4625 mov r5, r4 800b5de: e7f4 b.n 800b5ca <_dtoa_r+0x952> 800b5e0: f8dd b020 ldr.w fp, [sp, #32] 800b5e4: 9b0b ldr r3, [sp, #44] @ 0x2c 800b5e6: 2b00 cmp r3, #0 800b5e8: f000 8101 beq.w 800b7ee <_dtoa_r+0xb76> 800b5ec: 2e00 cmp r6, #0 800b5ee: dd05 ble.n 800b5fc <_dtoa_r+0x984> 800b5f0: 4629 mov r1, r5 800b5f2: 4632 mov r2, r6 800b5f4: 4648 mov r0, r9 800b5f6: f000 ff59 bl 800c4ac <__lshift> 800b5fa: 4605 mov r5, r0 800b5fc: 9b0a ldr r3, [sp, #40] @ 0x28 800b5fe: 2b00 cmp r3, #0 800b600: d05c beq.n 800b6bc <_dtoa_r+0xa44> 800b602: 4648 mov r0, r9 800b604: 6869 ldr r1, [r5, #4] 800b606: f000 fd4b bl 800c0a0 <_Balloc> 800b60a: 4606 mov r6, r0 800b60c: b928 cbnz r0, 800b61a <_dtoa_r+0x9a2> 800b60e: 4602 mov r2, r0 800b610: f240 21ef movw r1, #751 @ 0x2ef 800b614: 4b80 ldr r3, [pc, #512] @ (800b818 <_dtoa_r+0xba0>) 800b616: f7ff bb43 b.w 800aca0 <_dtoa_r+0x28> 800b61a: 692a ldr r2, [r5, #16] 800b61c: f105 010c add.w r1, r5, #12 800b620: 3202 adds r2, #2 800b622: 0092 lsls r2, r2, #2 800b624: 300c adds r0, #12 800b626: f7ff fa71 bl 800ab0c 800b62a: 2201 movs r2, #1 800b62c: 4631 mov r1, r6 800b62e: 4648 mov r0, r9 800b630: f000 ff3c bl 800c4ac <__lshift> 800b634: 462f mov r7, r5 800b636: 4605 mov r5, r0 800b638: f10a 0301 add.w r3, sl, #1 800b63c: 9304 str r3, [sp, #16] 800b63e: eb0a 030b add.w r3, sl, fp 800b642: 930a str r3, [sp, #40] @ 0x28 800b644: 9b06 ldr r3, [sp, #24] 800b646: f003 0301 and.w r3, r3, #1 800b64a: 9309 str r3, [sp, #36] @ 0x24 800b64c: 9b04 ldr r3, [sp, #16] 800b64e: 4621 mov r1, r4 800b650: 9803 ldr r0, [sp, #12] 800b652: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff 800b656: f7ff fa85 bl 800ab64 800b65a: 4603 mov r3, r0 800b65c: 4639 mov r1, r7 800b65e: 3330 adds r3, #48 @ 0x30 800b660: 9006 str r0, [sp, #24] 800b662: 9803 ldr r0, [sp, #12] 800b664: 930b str r3, [sp, #44] @ 0x2c 800b666: f000 ff8d bl 800c584 <__mcmp> 800b66a: 462a mov r2, r5 800b66c: 9008 str r0, [sp, #32] 800b66e: 4621 mov r1, r4 800b670: 4648 mov r0, r9 800b672: f000 ffa3 bl 800c5bc <__mdiff> 800b676: 68c2 ldr r2, [r0, #12] 800b678: 4606 mov r6, r0 800b67a: 9b0b ldr r3, [sp, #44] @ 0x2c 800b67c: bb02 cbnz r2, 800b6c0 <_dtoa_r+0xa48> 800b67e: 4601 mov r1, r0 800b680: 9803 ldr r0, [sp, #12] 800b682: f000 ff7f bl 800c584 <__mcmp> 800b686: 4602 mov r2, r0 800b688: 9b0b ldr r3, [sp, #44] @ 0x2c 800b68a: 4631 mov r1, r6 800b68c: 4648 mov r0, r9 800b68e: e9cd 320b strd r3, r2, [sp, #44] @ 0x2c 800b692: f000 fd45 bl 800c120 <_Bfree> 800b696: 9b20 ldr r3, [sp, #128] @ 0x80 800b698: 9a0c ldr r2, [sp, #48] @ 0x30 800b69a: 9e04 ldr r6, [sp, #16] 800b69c: ea42 0103 orr.w r1, r2, r3 800b6a0: 9b09 ldr r3, [sp, #36] @ 0x24 800b6a2: 4319 orrs r1, r3 800b6a4: 9b0b ldr r3, [sp, #44] @ 0x2c 800b6a6: d10d bne.n 800b6c4 <_dtoa_r+0xa4c> 800b6a8: 2b39 cmp r3, #57 @ 0x39 800b6aa: d027 beq.n 800b6fc <_dtoa_r+0xa84> 800b6ac: 9a08 ldr r2, [sp, #32] 800b6ae: 2a00 cmp r2, #0 800b6b0: dd01 ble.n 800b6b6 <_dtoa_r+0xa3e> 800b6b2: 9b06 ldr r3, [sp, #24] 800b6b4: 3331 adds r3, #49 @ 0x31 800b6b6: f88b 3000 strb.w r3, [fp] 800b6ba: e52e b.n 800b11a <_dtoa_r+0x4a2> 800b6bc: 4628 mov r0, r5 800b6be: e7b9 b.n 800b634 <_dtoa_r+0x9bc> 800b6c0: 2201 movs r2, #1 800b6c2: e7e2 b.n 800b68a <_dtoa_r+0xa12> 800b6c4: 9908 ldr r1, [sp, #32] 800b6c6: 2900 cmp r1, #0 800b6c8: db04 blt.n 800b6d4 <_dtoa_r+0xa5c> 800b6ca: 9820 ldr r0, [sp, #128] @ 0x80 800b6cc: 4301 orrs r1, r0 800b6ce: 9809 ldr r0, [sp, #36] @ 0x24 800b6d0: 4301 orrs r1, r0 800b6d2: d120 bne.n 800b716 <_dtoa_r+0xa9e> 800b6d4: 2a00 cmp r2, #0 800b6d6: ddee ble.n 800b6b6 <_dtoa_r+0xa3e> 800b6d8: 2201 movs r2, #1 800b6da: 9903 ldr r1, [sp, #12] 800b6dc: 4648 mov r0, r9 800b6de: 9304 str r3, [sp, #16] 800b6e0: f000 fee4 bl 800c4ac <__lshift> 800b6e4: 4621 mov r1, r4 800b6e6: 9003 str r0, [sp, #12] 800b6e8: f000 ff4c bl 800c584 <__mcmp> 800b6ec: 2800 cmp r0, #0 800b6ee: 9b04 ldr r3, [sp, #16] 800b6f0: dc02 bgt.n 800b6f8 <_dtoa_r+0xa80> 800b6f2: d1e0 bne.n 800b6b6 <_dtoa_r+0xa3e> 800b6f4: 07da lsls r2, r3, #31 800b6f6: d5de bpl.n 800b6b6 <_dtoa_r+0xa3e> 800b6f8: 2b39 cmp r3, #57 @ 0x39 800b6fa: d1da bne.n 800b6b2 <_dtoa_r+0xa3a> 800b6fc: 2339 movs r3, #57 @ 0x39 800b6fe: f88b 3000 strb.w r3, [fp] 800b702: 4633 mov r3, r6 800b704: 461e mov r6, r3 800b706: f816 2c01 ldrb.w r2, [r6, #-1] 800b70a: 3b01 subs r3, #1 800b70c: 2a39 cmp r2, #57 @ 0x39 800b70e: d04e beq.n 800b7ae <_dtoa_r+0xb36> 800b710: 3201 adds r2, #1 800b712: 701a strb r2, [r3, #0] 800b714: e501 b.n 800b11a <_dtoa_r+0x4a2> 800b716: 2a00 cmp r2, #0 800b718: dd03 ble.n 800b722 <_dtoa_r+0xaaa> 800b71a: 2b39 cmp r3, #57 @ 0x39 800b71c: d0ee beq.n 800b6fc <_dtoa_r+0xa84> 800b71e: 3301 adds r3, #1 800b720: e7c9 b.n 800b6b6 <_dtoa_r+0xa3e> 800b722: 9a04 ldr r2, [sp, #16] 800b724: 990a ldr r1, [sp, #40] @ 0x28 800b726: f802 3c01 strb.w r3, [r2, #-1] 800b72a: 428a cmp r2, r1 800b72c: d028 beq.n 800b780 <_dtoa_r+0xb08> 800b72e: 2300 movs r3, #0 800b730: 220a movs r2, #10 800b732: 9903 ldr r1, [sp, #12] 800b734: 4648 mov r0, r9 800b736: f000 fd15 bl 800c164 <__multadd> 800b73a: 42af cmp r7, r5 800b73c: 9003 str r0, [sp, #12] 800b73e: f04f 0300 mov.w r3, #0 800b742: f04f 020a mov.w r2, #10 800b746: 4639 mov r1, r7 800b748: 4648 mov r0, r9 800b74a: d107 bne.n 800b75c <_dtoa_r+0xae4> 800b74c: f000 fd0a bl 800c164 <__multadd> 800b750: 4607 mov r7, r0 800b752: 4605 mov r5, r0 800b754: 9b04 ldr r3, [sp, #16] 800b756: 3301 adds r3, #1 800b758: 9304 str r3, [sp, #16] 800b75a: e777 b.n 800b64c <_dtoa_r+0x9d4> 800b75c: f000 fd02 bl 800c164 <__multadd> 800b760: 4629 mov r1, r5 800b762: 4607 mov r7, r0 800b764: 2300 movs r3, #0 800b766: 220a movs r2, #10 800b768: 4648 mov r0, r9 800b76a: f000 fcfb bl 800c164 <__multadd> 800b76e: 4605 mov r5, r0 800b770: e7f0 b.n 800b754 <_dtoa_r+0xadc> 800b772: f1bb 0f00 cmp.w fp, #0 800b776: bfcc ite gt 800b778: 465e movgt r6, fp 800b77a: 2601 movle r6, #1 800b77c: 2700 movs r7, #0 800b77e: 4456 add r6, sl 800b780: 2201 movs r2, #1 800b782: 9903 ldr r1, [sp, #12] 800b784: 4648 mov r0, r9 800b786: 9304 str r3, [sp, #16] 800b788: f000 fe90 bl 800c4ac <__lshift> 800b78c: 4621 mov r1, r4 800b78e: 9003 str r0, [sp, #12] 800b790: f000 fef8 bl 800c584 <__mcmp> 800b794: 2800 cmp r0, #0 800b796: dcb4 bgt.n 800b702 <_dtoa_r+0xa8a> 800b798: d102 bne.n 800b7a0 <_dtoa_r+0xb28> 800b79a: 9b04 ldr r3, [sp, #16] 800b79c: 07db lsls r3, r3, #31 800b79e: d4b0 bmi.n 800b702 <_dtoa_r+0xa8a> 800b7a0: 4633 mov r3, r6 800b7a2: 461e mov r6, r3 800b7a4: f813 2d01 ldrb.w r2, [r3, #-1]! 800b7a8: 2a30 cmp r2, #48 @ 0x30 800b7aa: d0fa beq.n 800b7a2 <_dtoa_r+0xb2a> 800b7ac: e4b5 b.n 800b11a <_dtoa_r+0x4a2> 800b7ae: 459a cmp sl, r3 800b7b0: d1a8 bne.n 800b704 <_dtoa_r+0xa8c> 800b7b2: 2331 movs r3, #49 @ 0x31 800b7b4: f108 0801 add.w r8, r8, #1 800b7b8: f88a 3000 strb.w r3, [sl] 800b7bc: e4ad b.n 800b11a <_dtoa_r+0x4a2> 800b7be: 9b24 ldr r3, [sp, #144] @ 0x90 800b7c0: f8df a058 ldr.w sl, [pc, #88] @ 800b81c <_dtoa_r+0xba4> 800b7c4: b11b cbz r3, 800b7ce <_dtoa_r+0xb56> 800b7c6: f10a 0308 add.w r3, sl, #8 800b7ca: 9a24 ldr r2, [sp, #144] @ 0x90 800b7cc: 6013 str r3, [r2, #0] 800b7ce: 4650 mov r0, sl 800b7d0: b017 add sp, #92 @ 0x5c 800b7d2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800b7d6: 9b20 ldr r3, [sp, #128] @ 0x80 800b7d8: 2b01 cmp r3, #1 800b7da: f77f ae2e ble.w 800b43a <_dtoa_r+0x7c2> 800b7de: 9b0e ldr r3, [sp, #56] @ 0x38 800b7e0: 930a str r3, [sp, #40] @ 0x28 800b7e2: 2001 movs r0, #1 800b7e4: e64d b.n 800b482 <_dtoa_r+0x80a> 800b7e6: f1bb 0f00 cmp.w fp, #0 800b7ea: f77f aed9 ble.w 800b5a0 <_dtoa_r+0x928> 800b7ee: 4656 mov r6, sl 800b7f0: 4621 mov r1, r4 800b7f2: 9803 ldr r0, [sp, #12] 800b7f4: f7ff f9b6 bl 800ab64 800b7f8: f100 0330 add.w r3, r0, #48 @ 0x30 800b7fc: f806 3b01 strb.w r3, [r6], #1 800b800: eba6 020a sub.w r2, r6, sl 800b804: 4593 cmp fp, r2 800b806: ddb4 ble.n 800b772 <_dtoa_r+0xafa> 800b808: 2300 movs r3, #0 800b80a: 220a movs r2, #10 800b80c: 4648 mov r0, r9 800b80e: 9903 ldr r1, [sp, #12] 800b810: f000 fca8 bl 800c164 <__multadd> 800b814: 9003 str r0, [sp, #12] 800b816: e7eb b.n 800b7f0 <_dtoa_r+0xb78> 800b818: 0800e19d .word 0x0800e19d 800b81c: 0800e138 .word 0x0800e138 0800b820 <_findenv_r>: 800b820: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} 800b824: f8df a06c ldr.w sl, [pc, #108] @ 800b894 <_findenv_r+0x74> 800b828: 4606 mov r6, r0 800b82a: 4689 mov r9, r1 800b82c: 4617 mov r7, r2 800b82e: f001 fa85 bl 800cd3c <__env_lock> 800b832: f8da 4000 ldr.w r4, [sl] 800b836: b134 cbz r4, 800b846 <_findenv_r+0x26> 800b838: 464b mov r3, r9 800b83a: 4698 mov r8, r3 800b83c: f813 2b01 ldrb.w r2, [r3], #1 800b840: b13a cbz r2, 800b852 <_findenv_r+0x32> 800b842: 2a3d cmp r2, #61 @ 0x3d 800b844: d1f9 bne.n 800b83a <_findenv_r+0x1a> 800b846: 4630 mov r0, r6 800b848: f001 fa7e bl 800cd48 <__env_unlock> 800b84c: 2000 movs r0, #0 800b84e: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} 800b852: eba8 0809 sub.w r8, r8, r9 800b856: 46a3 mov fp, r4 800b858: f854 0b04 ldr.w r0, [r4], #4 800b85c: 2800 cmp r0, #0 800b85e: d0f2 beq.n 800b846 <_findenv_r+0x26> 800b860: 4642 mov r2, r8 800b862: 4649 mov r1, r9 800b864: f7fe fc3a bl 800a0dc 800b868: 2800 cmp r0, #0 800b86a: d1f4 bne.n 800b856 <_findenv_r+0x36> 800b86c: f854 3c04 ldr.w r3, [r4, #-4] 800b870: eb03 0508 add.w r5, r3, r8 800b874: f813 3008 ldrb.w r3, [r3, r8] 800b878: 2b3d cmp r3, #61 @ 0x3d 800b87a: d1ec bne.n 800b856 <_findenv_r+0x36> 800b87c: f8da 3000 ldr.w r3, [sl] 800b880: 4630 mov r0, r6 800b882: ebab 0303 sub.w r3, fp, r3 800b886: 109b asrs r3, r3, #2 800b888: 603b str r3, [r7, #0] 800b88a: f001 fa5d bl 800cd48 <__env_unlock> 800b88e: 1c68 adds r0, r5, #1 800b890: e7dd b.n 800b84e <_findenv_r+0x2e> 800b892: bf00 nop 800b894: 20000014 .word 0x20000014 0800b898 <_getenv_r>: 800b898: b507 push {r0, r1, r2, lr} 800b89a: aa01 add r2, sp, #4 800b89c: f7ff ffc0 bl 800b820 <_findenv_r> 800b8a0: b003 add sp, #12 800b8a2: f85d fb04 ldr.w pc, [sp], #4 0800b8a6 <__ssputs_r>: 800b8a6: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800b8aa: 461f mov r7, r3 800b8ac: 688e ldr r6, [r1, #8] 800b8ae: 4682 mov sl, r0 800b8b0: 42be cmp r6, r7 800b8b2: 460c mov r4, r1 800b8b4: 4690 mov r8, r2 800b8b6: 680b ldr r3, [r1, #0] 800b8b8: d82d bhi.n 800b916 <__ssputs_r+0x70> 800b8ba: f9b1 200c ldrsh.w r2, [r1, #12] 800b8be: f412 6f90 tst.w r2, #1152 @ 0x480 800b8c2: d026 beq.n 800b912 <__ssputs_r+0x6c> 800b8c4: 6965 ldr r5, [r4, #20] 800b8c6: 6909 ldr r1, [r1, #16] 800b8c8: eb05 0545 add.w r5, r5, r5, lsl #1 800b8cc: eba3 0901 sub.w r9, r3, r1 800b8d0: eb05 75d5 add.w r5, r5, r5, lsr #31 800b8d4: 1c7b adds r3, r7, #1 800b8d6: 444b add r3, r9 800b8d8: 106d asrs r5, r5, #1 800b8da: 429d cmp r5, r3 800b8dc: bf38 it cc 800b8de: 461d movcc r5, r3 800b8e0: 0553 lsls r3, r2, #21 800b8e2: d527 bpl.n 800b934 <__ssputs_r+0x8e> 800b8e4: 4629 mov r1, r5 800b8e6: f000 faa7 bl 800be38 <_malloc_r> 800b8ea: 4606 mov r6, r0 800b8ec: b360 cbz r0, 800b948 <__ssputs_r+0xa2> 800b8ee: 464a mov r2, r9 800b8f0: 6921 ldr r1, [r4, #16] 800b8f2: f7ff f90b bl 800ab0c 800b8f6: 89a3 ldrh r3, [r4, #12] 800b8f8: f423 6390 bic.w r3, r3, #1152 @ 0x480 800b8fc: f043 0380 orr.w r3, r3, #128 @ 0x80 800b900: 81a3 strh r3, [r4, #12] 800b902: 6126 str r6, [r4, #16] 800b904: 444e add r6, r9 800b906: 6026 str r6, [r4, #0] 800b908: 463e mov r6, r7 800b90a: 6165 str r5, [r4, #20] 800b90c: eba5 0509 sub.w r5, r5, r9 800b910: 60a5 str r5, [r4, #8] 800b912: 42be cmp r6, r7 800b914: d900 bls.n 800b918 <__ssputs_r+0x72> 800b916: 463e mov r6, r7 800b918: 4632 mov r2, r6 800b91a: 4641 mov r1, r8 800b91c: 6820 ldr r0, [r4, #0] 800b91e: f001 f95a bl 800cbd6 800b922: 2000 movs r0, #0 800b924: 68a3 ldr r3, [r4, #8] 800b926: 1b9b subs r3, r3, r6 800b928: 60a3 str r3, [r4, #8] 800b92a: 6823 ldr r3, [r4, #0] 800b92c: 4433 add r3, r6 800b92e: 6023 str r3, [r4, #0] 800b930: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800b934: 462a mov r2, r5 800b936: f000 ffb1 bl 800c89c <_realloc_r> 800b93a: 4606 mov r6, r0 800b93c: 2800 cmp r0, #0 800b93e: d1e0 bne.n 800b902 <__ssputs_r+0x5c> 800b940: 4650 mov r0, sl 800b942: 6921 ldr r1, [r4, #16] 800b944: f001 fa06 bl 800cd54 <_free_r> 800b948: 230c movs r3, #12 800b94a: f8ca 3000 str.w r3, [sl] 800b94e: 89a3 ldrh r3, [r4, #12] 800b950: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800b954: f043 0340 orr.w r3, r3, #64 @ 0x40 800b958: 81a3 strh r3, [r4, #12] 800b95a: e7e9 b.n 800b930 <__ssputs_r+0x8a> 0800b95c <_svfiprintf_r>: 800b95c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800b960: 4698 mov r8, r3 800b962: 898b ldrh r3, [r1, #12] 800b964: 4607 mov r7, r0 800b966: 061b lsls r3, r3, #24 800b968: 460d mov r5, r1 800b96a: 4614 mov r4, r2 800b96c: b09d sub sp, #116 @ 0x74 800b96e: d510 bpl.n 800b992 <_svfiprintf_r+0x36> 800b970: 690b ldr r3, [r1, #16] 800b972: b973 cbnz r3, 800b992 <_svfiprintf_r+0x36> 800b974: 2140 movs r1, #64 @ 0x40 800b976: f000 fa5f bl 800be38 <_malloc_r> 800b97a: 6028 str r0, [r5, #0] 800b97c: 6128 str r0, [r5, #16] 800b97e: b930 cbnz r0, 800b98e <_svfiprintf_r+0x32> 800b980: 230c movs r3, #12 800b982: 603b str r3, [r7, #0] 800b984: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800b988: b01d add sp, #116 @ 0x74 800b98a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800b98e: 2340 movs r3, #64 @ 0x40 800b990: 616b str r3, [r5, #20] 800b992: 2300 movs r3, #0 800b994: 9309 str r3, [sp, #36] @ 0x24 800b996: 2320 movs r3, #32 800b998: f88d 3029 strb.w r3, [sp, #41] @ 0x29 800b99c: 2330 movs r3, #48 @ 0x30 800b99e: f04f 0901 mov.w r9, #1 800b9a2: f8cd 800c str.w r8, [sp, #12] 800b9a6: f8df 8198 ldr.w r8, [pc, #408] @ 800bb40 <_svfiprintf_r+0x1e4> 800b9aa: f88d 302a strb.w r3, [sp, #42] @ 0x2a 800b9ae: 4623 mov r3, r4 800b9b0: 469a mov sl, r3 800b9b2: f813 2b01 ldrb.w r2, [r3], #1 800b9b6: b10a cbz r2, 800b9bc <_svfiprintf_r+0x60> 800b9b8: 2a25 cmp r2, #37 @ 0x25 800b9ba: d1f9 bne.n 800b9b0 <_svfiprintf_r+0x54> 800b9bc: ebba 0b04 subs.w fp, sl, r4 800b9c0: d00b beq.n 800b9da <_svfiprintf_r+0x7e> 800b9c2: 465b mov r3, fp 800b9c4: 4622 mov r2, r4 800b9c6: 4629 mov r1, r5 800b9c8: 4638 mov r0, r7 800b9ca: f7ff ff6c bl 800b8a6 <__ssputs_r> 800b9ce: 3001 adds r0, #1 800b9d0: f000 80a7 beq.w 800bb22 <_svfiprintf_r+0x1c6> 800b9d4: 9a09 ldr r2, [sp, #36] @ 0x24 800b9d6: 445a add r2, fp 800b9d8: 9209 str r2, [sp, #36] @ 0x24 800b9da: f89a 3000 ldrb.w r3, [sl] 800b9de: 2b00 cmp r3, #0 800b9e0: f000 809f beq.w 800bb22 <_svfiprintf_r+0x1c6> 800b9e4: 2300 movs r3, #0 800b9e6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800b9ea: e9cd 2305 strd r2, r3, [sp, #20] 800b9ee: f10a 0a01 add.w sl, sl, #1 800b9f2: 9304 str r3, [sp, #16] 800b9f4: 9307 str r3, [sp, #28] 800b9f6: f88d 3053 strb.w r3, [sp, #83] @ 0x53 800b9fa: 931a str r3, [sp, #104] @ 0x68 800b9fc: 4654 mov r4, sl 800b9fe: 2205 movs r2, #5 800ba00: f814 1b01 ldrb.w r1, [r4], #1 800ba04: 484e ldr r0, [pc, #312] @ (800bb40 <_svfiprintf_r+0x1e4>) 800ba06: f7ff f873 bl 800aaf0 800ba0a: 9a04 ldr r2, [sp, #16] 800ba0c: b9d8 cbnz r0, 800ba46 <_svfiprintf_r+0xea> 800ba0e: 06d0 lsls r0, r2, #27 800ba10: bf44 itt mi 800ba12: 2320 movmi r3, #32 800ba14: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 800ba18: 0711 lsls r1, r2, #28 800ba1a: bf44 itt mi 800ba1c: 232b movmi r3, #43 @ 0x2b 800ba1e: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 800ba22: f89a 3000 ldrb.w r3, [sl] 800ba26: 2b2a cmp r3, #42 @ 0x2a 800ba28: d015 beq.n 800ba56 <_svfiprintf_r+0xfa> 800ba2a: 4654 mov r4, sl 800ba2c: 2000 movs r0, #0 800ba2e: f04f 0c0a mov.w ip, #10 800ba32: 9a07 ldr r2, [sp, #28] 800ba34: 4621 mov r1, r4 800ba36: f811 3b01 ldrb.w r3, [r1], #1 800ba3a: 3b30 subs r3, #48 @ 0x30 800ba3c: 2b09 cmp r3, #9 800ba3e: d94b bls.n 800bad8 <_svfiprintf_r+0x17c> 800ba40: b1b0 cbz r0, 800ba70 <_svfiprintf_r+0x114> 800ba42: 9207 str r2, [sp, #28] 800ba44: e014 b.n 800ba70 <_svfiprintf_r+0x114> 800ba46: eba0 0308 sub.w r3, r0, r8 800ba4a: fa09 f303 lsl.w r3, r9, r3 800ba4e: 4313 orrs r3, r2 800ba50: 46a2 mov sl, r4 800ba52: 9304 str r3, [sp, #16] 800ba54: e7d2 b.n 800b9fc <_svfiprintf_r+0xa0> 800ba56: 9b03 ldr r3, [sp, #12] 800ba58: 1d19 adds r1, r3, #4 800ba5a: 681b ldr r3, [r3, #0] 800ba5c: 9103 str r1, [sp, #12] 800ba5e: 2b00 cmp r3, #0 800ba60: bfbb ittet lt 800ba62: 425b neglt r3, r3 800ba64: f042 0202 orrlt.w r2, r2, #2 800ba68: 9307 strge r3, [sp, #28] 800ba6a: 9307 strlt r3, [sp, #28] 800ba6c: bfb8 it lt 800ba6e: 9204 strlt r2, [sp, #16] 800ba70: 7823 ldrb r3, [r4, #0] 800ba72: 2b2e cmp r3, #46 @ 0x2e 800ba74: d10a bne.n 800ba8c <_svfiprintf_r+0x130> 800ba76: 7863 ldrb r3, [r4, #1] 800ba78: 2b2a cmp r3, #42 @ 0x2a 800ba7a: d132 bne.n 800bae2 <_svfiprintf_r+0x186> 800ba7c: 9b03 ldr r3, [sp, #12] 800ba7e: 3402 adds r4, #2 800ba80: 1d1a adds r2, r3, #4 800ba82: 681b ldr r3, [r3, #0] 800ba84: 9203 str r2, [sp, #12] 800ba86: ea43 73e3 orr.w r3, r3, r3, asr #31 800ba8a: 9305 str r3, [sp, #20] 800ba8c: f8df a0b4 ldr.w sl, [pc, #180] @ 800bb44 <_svfiprintf_r+0x1e8> 800ba90: 2203 movs r2, #3 800ba92: 4650 mov r0, sl 800ba94: 7821 ldrb r1, [r4, #0] 800ba96: f7ff f82b bl 800aaf0 800ba9a: b138 cbz r0, 800baac <_svfiprintf_r+0x150> 800ba9c: 2240 movs r2, #64 @ 0x40 800ba9e: 9b04 ldr r3, [sp, #16] 800baa0: eba0 000a sub.w r0, r0, sl 800baa4: 4082 lsls r2, r0 800baa6: 4313 orrs r3, r2 800baa8: 3401 adds r4, #1 800baaa: 9304 str r3, [sp, #16] 800baac: f814 1b01 ldrb.w r1, [r4], #1 800bab0: 2206 movs r2, #6 800bab2: 4825 ldr r0, [pc, #148] @ (800bb48 <_svfiprintf_r+0x1ec>) 800bab4: f88d 1028 strb.w r1, [sp, #40] @ 0x28 800bab8: f7ff f81a bl 800aaf0 800babc: 2800 cmp r0, #0 800babe: d036 beq.n 800bb2e <_svfiprintf_r+0x1d2> 800bac0: 4b22 ldr r3, [pc, #136] @ (800bb4c <_svfiprintf_r+0x1f0>) 800bac2: bb1b cbnz r3, 800bb0c <_svfiprintf_r+0x1b0> 800bac4: 9b03 ldr r3, [sp, #12] 800bac6: 3307 adds r3, #7 800bac8: f023 0307 bic.w r3, r3, #7 800bacc: 3308 adds r3, #8 800bace: 9303 str r3, [sp, #12] 800bad0: 9b09 ldr r3, [sp, #36] @ 0x24 800bad2: 4433 add r3, r6 800bad4: 9309 str r3, [sp, #36] @ 0x24 800bad6: e76a b.n 800b9ae <_svfiprintf_r+0x52> 800bad8: 460c mov r4, r1 800bada: 2001 movs r0, #1 800badc: fb0c 3202 mla r2, ip, r2, r3 800bae0: e7a8 b.n 800ba34 <_svfiprintf_r+0xd8> 800bae2: 2300 movs r3, #0 800bae4: f04f 0c0a mov.w ip, #10 800bae8: 4619 mov r1, r3 800baea: 3401 adds r4, #1 800baec: 9305 str r3, [sp, #20] 800baee: 4620 mov r0, r4 800baf0: f810 2b01 ldrb.w r2, [r0], #1 800baf4: 3a30 subs r2, #48 @ 0x30 800baf6: 2a09 cmp r2, #9 800baf8: d903 bls.n 800bb02 <_svfiprintf_r+0x1a6> 800bafa: 2b00 cmp r3, #0 800bafc: d0c6 beq.n 800ba8c <_svfiprintf_r+0x130> 800bafe: 9105 str r1, [sp, #20] 800bb00: e7c4 b.n 800ba8c <_svfiprintf_r+0x130> 800bb02: 4604 mov r4, r0 800bb04: 2301 movs r3, #1 800bb06: fb0c 2101 mla r1, ip, r1, r2 800bb0a: e7f0 b.n 800baee <_svfiprintf_r+0x192> 800bb0c: ab03 add r3, sp, #12 800bb0e: 9300 str r3, [sp, #0] 800bb10: 462a mov r2, r5 800bb12: 4638 mov r0, r7 800bb14: 4b0e ldr r3, [pc, #56] @ (800bb50 <_svfiprintf_r+0x1f4>) 800bb16: a904 add r1, sp, #16 800bb18: f7fd fd78 bl 800960c <_printf_float> 800bb1c: 1c42 adds r2, r0, #1 800bb1e: 4606 mov r6, r0 800bb20: d1d6 bne.n 800bad0 <_svfiprintf_r+0x174> 800bb22: 89ab ldrh r3, [r5, #12] 800bb24: 065b lsls r3, r3, #25 800bb26: f53f af2d bmi.w 800b984 <_svfiprintf_r+0x28> 800bb2a: 9809 ldr r0, [sp, #36] @ 0x24 800bb2c: e72c b.n 800b988 <_svfiprintf_r+0x2c> 800bb2e: ab03 add r3, sp, #12 800bb30: 9300 str r3, [sp, #0] 800bb32: 462a mov r2, r5 800bb34: 4638 mov r0, r7 800bb36: 4b06 ldr r3, [pc, #24] @ (800bb50 <_svfiprintf_r+0x1f4>) 800bb38: a904 add r1, sp, #16 800bb3a: f7fe f805 bl 8009b48 <_printf_i> 800bb3e: e7ed b.n 800bb1c <_svfiprintf_r+0x1c0> 800bb40: 0800e1ae .word 0x0800e1ae 800bb44: 0800e1b4 .word 0x0800e1b4 800bb48: 0800e1b8 .word 0x0800e1b8 800bb4c: 0800960d .word 0x0800960d 800bb50: 0800b8a7 .word 0x0800b8a7 0800bb54 <__sfputc_r>: 800bb54: 6893 ldr r3, [r2, #8] 800bb56: b410 push {r4} 800bb58: 3b01 subs r3, #1 800bb5a: 2b00 cmp r3, #0 800bb5c: 6093 str r3, [r2, #8] 800bb5e: da07 bge.n 800bb70 <__sfputc_r+0x1c> 800bb60: 6994 ldr r4, [r2, #24] 800bb62: 42a3 cmp r3, r4 800bb64: db01 blt.n 800bb6a <__sfputc_r+0x16> 800bb66: 290a cmp r1, #10 800bb68: d102 bne.n 800bb70 <__sfputc_r+0x1c> 800bb6a: bc10 pop {r4} 800bb6c: f000 bec4 b.w 800c8f8 <__swbuf_r> 800bb70: 6813 ldr r3, [r2, #0] 800bb72: 1c58 adds r0, r3, #1 800bb74: 6010 str r0, [r2, #0] 800bb76: 7019 strb r1, [r3, #0] 800bb78: 4608 mov r0, r1 800bb7a: bc10 pop {r4} 800bb7c: 4770 bx lr 0800bb7e <__sfputs_r>: 800bb7e: b5f8 push {r3, r4, r5, r6, r7, lr} 800bb80: 4606 mov r6, r0 800bb82: 460f mov r7, r1 800bb84: 4614 mov r4, r2 800bb86: 18d5 adds r5, r2, r3 800bb88: 42ac cmp r4, r5 800bb8a: d101 bne.n 800bb90 <__sfputs_r+0x12> 800bb8c: 2000 movs r0, #0 800bb8e: e007 b.n 800bba0 <__sfputs_r+0x22> 800bb90: 463a mov r2, r7 800bb92: 4630 mov r0, r6 800bb94: f814 1b01 ldrb.w r1, [r4], #1 800bb98: f7ff ffdc bl 800bb54 <__sfputc_r> 800bb9c: 1c43 adds r3, r0, #1 800bb9e: d1f3 bne.n 800bb88 <__sfputs_r+0xa> 800bba0: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 0800bba4 <_vfiprintf_r>: 800bba4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800bba8: 460d mov r5, r1 800bbaa: 4614 mov r4, r2 800bbac: 4698 mov r8, r3 800bbae: 4606 mov r6, r0 800bbb0: b09d sub sp, #116 @ 0x74 800bbb2: b118 cbz r0, 800bbbc <_vfiprintf_r+0x18> 800bbb4: 6a03 ldr r3, [r0, #32] 800bbb6: b90b cbnz r3, 800bbbc <_vfiprintf_r+0x18> 800bbb8: f7fe f9a6 bl 8009f08 <__sinit> 800bbbc: 6e6b ldr r3, [r5, #100] @ 0x64 800bbbe: 07d9 lsls r1, r3, #31 800bbc0: d405 bmi.n 800bbce <_vfiprintf_r+0x2a> 800bbc2: 89ab ldrh r3, [r5, #12] 800bbc4: 059a lsls r2, r3, #22 800bbc6: d402 bmi.n 800bbce <_vfiprintf_r+0x2a> 800bbc8: 6da8 ldr r0, [r5, #88] @ 0x58 800bbca: f7fe fd5d bl 800a688 <__retarget_lock_acquire_recursive> 800bbce: 89ab ldrh r3, [r5, #12] 800bbd0: 071b lsls r3, r3, #28 800bbd2: d501 bpl.n 800bbd8 <_vfiprintf_r+0x34> 800bbd4: 692b ldr r3, [r5, #16] 800bbd6: b99b cbnz r3, 800bc00 <_vfiprintf_r+0x5c> 800bbd8: 4629 mov r1, r5 800bbda: 4630 mov r0, r6 800bbdc: f000 ff44 bl 800ca68 <__swsetup_r> 800bbe0: b170 cbz r0, 800bc00 <_vfiprintf_r+0x5c> 800bbe2: 6e6b ldr r3, [r5, #100] @ 0x64 800bbe4: 07dc lsls r4, r3, #31 800bbe6: d504 bpl.n 800bbf2 <_vfiprintf_r+0x4e> 800bbe8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800bbec: b01d add sp, #116 @ 0x74 800bbee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800bbf2: 89ab ldrh r3, [r5, #12] 800bbf4: 0598 lsls r0, r3, #22 800bbf6: d4f7 bmi.n 800bbe8 <_vfiprintf_r+0x44> 800bbf8: 6da8 ldr r0, [r5, #88] @ 0x58 800bbfa: f7fe fd47 bl 800a68c <__retarget_lock_release_recursive> 800bbfe: e7f3 b.n 800bbe8 <_vfiprintf_r+0x44> 800bc00: 2300 movs r3, #0 800bc02: 9309 str r3, [sp, #36] @ 0x24 800bc04: 2320 movs r3, #32 800bc06: f88d 3029 strb.w r3, [sp, #41] @ 0x29 800bc0a: 2330 movs r3, #48 @ 0x30 800bc0c: f04f 0901 mov.w r9, #1 800bc10: f8cd 800c str.w r8, [sp, #12] 800bc14: f8df 81a8 ldr.w r8, [pc, #424] @ 800bdc0 <_vfiprintf_r+0x21c> 800bc18: f88d 302a strb.w r3, [sp, #42] @ 0x2a 800bc1c: 4623 mov r3, r4 800bc1e: 469a mov sl, r3 800bc20: f813 2b01 ldrb.w r2, [r3], #1 800bc24: b10a cbz r2, 800bc2a <_vfiprintf_r+0x86> 800bc26: 2a25 cmp r2, #37 @ 0x25 800bc28: d1f9 bne.n 800bc1e <_vfiprintf_r+0x7a> 800bc2a: ebba 0b04 subs.w fp, sl, r4 800bc2e: d00b beq.n 800bc48 <_vfiprintf_r+0xa4> 800bc30: 465b mov r3, fp 800bc32: 4622 mov r2, r4 800bc34: 4629 mov r1, r5 800bc36: 4630 mov r0, r6 800bc38: f7ff ffa1 bl 800bb7e <__sfputs_r> 800bc3c: 3001 adds r0, #1 800bc3e: f000 80a7 beq.w 800bd90 <_vfiprintf_r+0x1ec> 800bc42: 9a09 ldr r2, [sp, #36] @ 0x24 800bc44: 445a add r2, fp 800bc46: 9209 str r2, [sp, #36] @ 0x24 800bc48: f89a 3000 ldrb.w r3, [sl] 800bc4c: 2b00 cmp r3, #0 800bc4e: f000 809f beq.w 800bd90 <_vfiprintf_r+0x1ec> 800bc52: 2300 movs r3, #0 800bc54: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800bc58: e9cd 2305 strd r2, r3, [sp, #20] 800bc5c: f10a 0a01 add.w sl, sl, #1 800bc60: 9304 str r3, [sp, #16] 800bc62: 9307 str r3, [sp, #28] 800bc64: f88d 3053 strb.w r3, [sp, #83] @ 0x53 800bc68: 931a str r3, [sp, #104] @ 0x68 800bc6a: 4654 mov r4, sl 800bc6c: 2205 movs r2, #5 800bc6e: f814 1b01 ldrb.w r1, [r4], #1 800bc72: 4853 ldr r0, [pc, #332] @ (800bdc0 <_vfiprintf_r+0x21c>) 800bc74: f7fe ff3c bl 800aaf0 800bc78: 9a04 ldr r2, [sp, #16] 800bc7a: b9d8 cbnz r0, 800bcb4 <_vfiprintf_r+0x110> 800bc7c: 06d1 lsls r1, r2, #27 800bc7e: bf44 itt mi 800bc80: 2320 movmi r3, #32 800bc82: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 800bc86: 0713 lsls r3, r2, #28 800bc88: bf44 itt mi 800bc8a: 232b movmi r3, #43 @ 0x2b 800bc8c: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 800bc90: f89a 3000 ldrb.w r3, [sl] 800bc94: 2b2a cmp r3, #42 @ 0x2a 800bc96: d015 beq.n 800bcc4 <_vfiprintf_r+0x120> 800bc98: 4654 mov r4, sl 800bc9a: 2000 movs r0, #0 800bc9c: f04f 0c0a mov.w ip, #10 800bca0: 9a07 ldr r2, [sp, #28] 800bca2: 4621 mov r1, r4 800bca4: f811 3b01 ldrb.w r3, [r1], #1 800bca8: 3b30 subs r3, #48 @ 0x30 800bcaa: 2b09 cmp r3, #9 800bcac: d94b bls.n 800bd46 <_vfiprintf_r+0x1a2> 800bcae: b1b0 cbz r0, 800bcde <_vfiprintf_r+0x13a> 800bcb0: 9207 str r2, [sp, #28] 800bcb2: e014 b.n 800bcde <_vfiprintf_r+0x13a> 800bcb4: eba0 0308 sub.w r3, r0, r8 800bcb8: fa09 f303 lsl.w r3, r9, r3 800bcbc: 4313 orrs r3, r2 800bcbe: 46a2 mov sl, r4 800bcc0: 9304 str r3, [sp, #16] 800bcc2: e7d2 b.n 800bc6a <_vfiprintf_r+0xc6> 800bcc4: 9b03 ldr r3, [sp, #12] 800bcc6: 1d19 adds r1, r3, #4 800bcc8: 681b ldr r3, [r3, #0] 800bcca: 9103 str r1, [sp, #12] 800bccc: 2b00 cmp r3, #0 800bcce: bfbb ittet lt 800bcd0: 425b neglt r3, r3 800bcd2: f042 0202 orrlt.w r2, r2, #2 800bcd6: 9307 strge r3, [sp, #28] 800bcd8: 9307 strlt r3, [sp, #28] 800bcda: bfb8 it lt 800bcdc: 9204 strlt r2, [sp, #16] 800bcde: 7823 ldrb r3, [r4, #0] 800bce0: 2b2e cmp r3, #46 @ 0x2e 800bce2: d10a bne.n 800bcfa <_vfiprintf_r+0x156> 800bce4: 7863 ldrb r3, [r4, #1] 800bce6: 2b2a cmp r3, #42 @ 0x2a 800bce8: d132 bne.n 800bd50 <_vfiprintf_r+0x1ac> 800bcea: 9b03 ldr r3, [sp, #12] 800bcec: 3402 adds r4, #2 800bcee: 1d1a adds r2, r3, #4 800bcf0: 681b ldr r3, [r3, #0] 800bcf2: 9203 str r2, [sp, #12] 800bcf4: ea43 73e3 orr.w r3, r3, r3, asr #31 800bcf8: 9305 str r3, [sp, #20] 800bcfa: f8df a0c8 ldr.w sl, [pc, #200] @ 800bdc4 <_vfiprintf_r+0x220> 800bcfe: 2203 movs r2, #3 800bd00: 4650 mov r0, sl 800bd02: 7821 ldrb r1, [r4, #0] 800bd04: f7fe fef4 bl 800aaf0 800bd08: b138 cbz r0, 800bd1a <_vfiprintf_r+0x176> 800bd0a: 2240 movs r2, #64 @ 0x40 800bd0c: 9b04 ldr r3, [sp, #16] 800bd0e: eba0 000a sub.w r0, r0, sl 800bd12: 4082 lsls r2, r0 800bd14: 4313 orrs r3, r2 800bd16: 3401 adds r4, #1 800bd18: 9304 str r3, [sp, #16] 800bd1a: f814 1b01 ldrb.w r1, [r4], #1 800bd1e: 2206 movs r2, #6 800bd20: 4829 ldr r0, [pc, #164] @ (800bdc8 <_vfiprintf_r+0x224>) 800bd22: f88d 1028 strb.w r1, [sp, #40] @ 0x28 800bd26: f7fe fee3 bl 800aaf0 800bd2a: 2800 cmp r0, #0 800bd2c: d03f beq.n 800bdae <_vfiprintf_r+0x20a> 800bd2e: 4b27 ldr r3, [pc, #156] @ (800bdcc <_vfiprintf_r+0x228>) 800bd30: bb1b cbnz r3, 800bd7a <_vfiprintf_r+0x1d6> 800bd32: 9b03 ldr r3, [sp, #12] 800bd34: 3307 adds r3, #7 800bd36: f023 0307 bic.w r3, r3, #7 800bd3a: 3308 adds r3, #8 800bd3c: 9303 str r3, [sp, #12] 800bd3e: 9b09 ldr r3, [sp, #36] @ 0x24 800bd40: 443b add r3, r7 800bd42: 9309 str r3, [sp, #36] @ 0x24 800bd44: e76a b.n 800bc1c <_vfiprintf_r+0x78> 800bd46: 460c mov r4, r1 800bd48: 2001 movs r0, #1 800bd4a: fb0c 3202 mla r2, ip, r2, r3 800bd4e: e7a8 b.n 800bca2 <_vfiprintf_r+0xfe> 800bd50: 2300 movs r3, #0 800bd52: f04f 0c0a mov.w ip, #10 800bd56: 4619 mov r1, r3 800bd58: 3401 adds r4, #1 800bd5a: 9305 str r3, [sp, #20] 800bd5c: 4620 mov r0, r4 800bd5e: f810 2b01 ldrb.w r2, [r0], #1 800bd62: 3a30 subs r2, #48 @ 0x30 800bd64: 2a09 cmp r2, #9 800bd66: d903 bls.n 800bd70 <_vfiprintf_r+0x1cc> 800bd68: 2b00 cmp r3, #0 800bd6a: d0c6 beq.n 800bcfa <_vfiprintf_r+0x156> 800bd6c: 9105 str r1, [sp, #20] 800bd6e: e7c4 b.n 800bcfa <_vfiprintf_r+0x156> 800bd70: 4604 mov r4, r0 800bd72: 2301 movs r3, #1 800bd74: fb0c 2101 mla r1, ip, r1, r2 800bd78: e7f0 b.n 800bd5c <_vfiprintf_r+0x1b8> 800bd7a: ab03 add r3, sp, #12 800bd7c: 9300 str r3, [sp, #0] 800bd7e: 462a mov r2, r5 800bd80: 4630 mov r0, r6 800bd82: 4b13 ldr r3, [pc, #76] @ (800bdd0 <_vfiprintf_r+0x22c>) 800bd84: a904 add r1, sp, #16 800bd86: f7fd fc41 bl 800960c <_printf_float> 800bd8a: 4607 mov r7, r0 800bd8c: 1c78 adds r0, r7, #1 800bd8e: d1d6 bne.n 800bd3e <_vfiprintf_r+0x19a> 800bd90: 6e6b ldr r3, [r5, #100] @ 0x64 800bd92: 07d9 lsls r1, r3, #31 800bd94: d405 bmi.n 800bda2 <_vfiprintf_r+0x1fe> 800bd96: 89ab ldrh r3, [r5, #12] 800bd98: 059a lsls r2, r3, #22 800bd9a: d402 bmi.n 800bda2 <_vfiprintf_r+0x1fe> 800bd9c: 6da8 ldr r0, [r5, #88] @ 0x58 800bd9e: f7fe fc75 bl 800a68c <__retarget_lock_release_recursive> 800bda2: 89ab ldrh r3, [r5, #12] 800bda4: 065b lsls r3, r3, #25 800bda6: f53f af1f bmi.w 800bbe8 <_vfiprintf_r+0x44> 800bdaa: 9809 ldr r0, [sp, #36] @ 0x24 800bdac: e71e b.n 800bbec <_vfiprintf_r+0x48> 800bdae: ab03 add r3, sp, #12 800bdb0: 9300 str r3, [sp, #0] 800bdb2: 462a mov r2, r5 800bdb4: 4630 mov r0, r6 800bdb6: 4b06 ldr r3, [pc, #24] @ (800bdd0 <_vfiprintf_r+0x22c>) 800bdb8: a904 add r1, sp, #16 800bdba: f7fd fec5 bl 8009b48 <_printf_i> 800bdbe: e7e4 b.n 800bd8a <_vfiprintf_r+0x1e6> 800bdc0: 0800e1ae .word 0x0800e1ae 800bdc4: 0800e1b4 .word 0x0800e1b4 800bdc8: 0800e1b8 .word 0x0800e1b8 800bdcc: 0800960d .word 0x0800960d 800bdd0: 0800bb7f .word 0x0800bb7f 0800bdd4 : 800bdd4: 4b02 ldr r3, [pc, #8] @ (800bde0 ) 800bdd6: 4601 mov r1, r0 800bdd8: 6818 ldr r0, [r3, #0] 800bdda: f000 b82d b.w 800be38 <_malloc_r> 800bdde: bf00 nop 800bde0: 20000038 .word 0x20000038 0800bde4 : 800bde4: 4b02 ldr r3, [pc, #8] @ (800bdf0 ) 800bde6: 4601 mov r1, r0 800bde8: 6818 ldr r0, [r3, #0] 800bdea: f000 bfb3 b.w 800cd54 <_free_r> 800bdee: bf00 nop 800bdf0: 20000038 .word 0x20000038 0800bdf4 : 800bdf4: b570 push {r4, r5, r6, lr} 800bdf6: 4e0f ldr r6, [pc, #60] @ (800be34 ) 800bdf8: 460c mov r4, r1 800bdfa: 6831 ldr r1, [r6, #0] 800bdfc: 4605 mov r5, r0 800bdfe: b911 cbnz r1, 800be06 800be00: f000 ff38 bl 800cc74 <_sbrk_r> 800be04: 6030 str r0, [r6, #0] 800be06: 4621 mov r1, r4 800be08: 4628 mov r0, r5 800be0a: f000 ff33 bl 800cc74 <_sbrk_r> 800be0e: 1c43 adds r3, r0, #1 800be10: d103 bne.n 800be1a 800be12: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 800be16: 4620 mov r0, r4 800be18: bd70 pop {r4, r5, r6, pc} 800be1a: 1cc4 adds r4, r0, #3 800be1c: f024 0403 bic.w r4, r4, #3 800be20: 42a0 cmp r0, r4 800be22: d0f8 beq.n 800be16 800be24: 1a21 subs r1, r4, r0 800be26: 4628 mov r0, r5 800be28: f000 ff24 bl 800cc74 <_sbrk_r> 800be2c: 3001 adds r0, #1 800be2e: d1f2 bne.n 800be16 800be30: e7ef b.n 800be12 800be32: bf00 nop 800be34: 20003510 .word 0x20003510 0800be38 <_malloc_r>: 800be38: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 800be3c: 1ccd adds r5, r1, #3 800be3e: f025 0503 bic.w r5, r5, #3 800be42: 3508 adds r5, #8 800be44: 2d0c cmp r5, #12 800be46: bf38 it cc 800be48: 250c movcc r5, #12 800be4a: 2d00 cmp r5, #0 800be4c: 4606 mov r6, r0 800be4e: db01 blt.n 800be54 <_malloc_r+0x1c> 800be50: 42a9 cmp r1, r5 800be52: d904 bls.n 800be5e <_malloc_r+0x26> 800be54: 230c movs r3, #12 800be56: 6033 str r3, [r6, #0] 800be58: 2000 movs r0, #0 800be5a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 800be5e: f8df 80d4 ldr.w r8, [pc, #212] @ 800bf34 <_malloc_r+0xfc> 800be62: f000 f911 bl 800c088 <__malloc_lock> 800be66: f8d8 3000 ldr.w r3, [r8] 800be6a: 461c mov r4, r3 800be6c: bb44 cbnz r4, 800bec0 <_malloc_r+0x88> 800be6e: 4629 mov r1, r5 800be70: 4630 mov r0, r6 800be72: f7ff ffbf bl 800bdf4 800be76: 1c43 adds r3, r0, #1 800be78: 4604 mov r4, r0 800be7a: d158 bne.n 800bf2e <_malloc_r+0xf6> 800be7c: f8d8 4000 ldr.w r4, [r8] 800be80: 4627 mov r7, r4 800be82: 2f00 cmp r7, #0 800be84: d143 bne.n 800bf0e <_malloc_r+0xd6> 800be86: 2c00 cmp r4, #0 800be88: d04b beq.n 800bf22 <_malloc_r+0xea> 800be8a: 6823 ldr r3, [r4, #0] 800be8c: 4639 mov r1, r7 800be8e: 4630 mov r0, r6 800be90: eb04 0903 add.w r9, r4, r3 800be94: f000 feee bl 800cc74 <_sbrk_r> 800be98: 4581 cmp r9, r0 800be9a: d142 bne.n 800bf22 <_malloc_r+0xea> 800be9c: 6821 ldr r1, [r4, #0] 800be9e: 4630 mov r0, r6 800bea0: 1a6d subs r5, r5, r1 800bea2: 4629 mov r1, r5 800bea4: f7ff ffa6 bl 800bdf4 800bea8: 3001 adds r0, #1 800beaa: d03a beq.n 800bf22 <_malloc_r+0xea> 800beac: 6823 ldr r3, [r4, #0] 800beae: 442b add r3, r5 800beb0: 6023 str r3, [r4, #0] 800beb2: f8d8 3000 ldr.w r3, [r8] 800beb6: 685a ldr r2, [r3, #4] 800beb8: bb62 cbnz r2, 800bf14 <_malloc_r+0xdc> 800beba: f8c8 7000 str.w r7, [r8] 800bebe: e00f b.n 800bee0 <_malloc_r+0xa8> 800bec0: 6822 ldr r2, [r4, #0] 800bec2: 1b52 subs r2, r2, r5 800bec4: d420 bmi.n 800bf08 <_malloc_r+0xd0> 800bec6: 2a0b cmp r2, #11 800bec8: d917 bls.n 800befa <_malloc_r+0xc2> 800beca: 1961 adds r1, r4, r5 800becc: 42a3 cmp r3, r4 800bece: 6025 str r5, [r4, #0] 800bed0: bf18 it ne 800bed2: 6059 strne r1, [r3, #4] 800bed4: 6863 ldr r3, [r4, #4] 800bed6: bf08 it eq 800bed8: f8c8 1000 streq.w r1, [r8] 800bedc: 5162 str r2, [r4, r5] 800bede: 604b str r3, [r1, #4] 800bee0: 4630 mov r0, r6 800bee2: f000 f8d7 bl 800c094 <__malloc_unlock> 800bee6: f104 000b add.w r0, r4, #11 800beea: 1d23 adds r3, r4, #4 800beec: f020 0007 bic.w r0, r0, #7 800bef0: 1ac2 subs r2, r0, r3 800bef2: bf1c itt ne 800bef4: 1a1b subne r3, r3, r0 800bef6: 50a3 strne r3, [r4, r2] 800bef8: e7af b.n 800be5a <_malloc_r+0x22> 800befa: 6862 ldr r2, [r4, #4] 800befc: 42a3 cmp r3, r4 800befe: bf0c ite eq 800bf00: f8c8 2000 streq.w r2, [r8] 800bf04: 605a strne r2, [r3, #4] 800bf06: e7eb b.n 800bee0 <_malloc_r+0xa8> 800bf08: 4623 mov r3, r4 800bf0a: 6864 ldr r4, [r4, #4] 800bf0c: e7ae b.n 800be6c <_malloc_r+0x34> 800bf0e: 463c mov r4, r7 800bf10: 687f ldr r7, [r7, #4] 800bf12: e7b6 b.n 800be82 <_malloc_r+0x4a> 800bf14: 461a mov r2, r3 800bf16: 685b ldr r3, [r3, #4] 800bf18: 42a3 cmp r3, r4 800bf1a: d1fb bne.n 800bf14 <_malloc_r+0xdc> 800bf1c: 2300 movs r3, #0 800bf1e: 6053 str r3, [r2, #4] 800bf20: e7de b.n 800bee0 <_malloc_r+0xa8> 800bf22: 230c movs r3, #12 800bf24: 4630 mov r0, r6 800bf26: 6033 str r3, [r6, #0] 800bf28: f000 f8b4 bl 800c094 <__malloc_unlock> 800bf2c: e794 b.n 800be58 <_malloc_r+0x20> 800bf2e: 6005 str r5, [r0, #0] 800bf30: e7d6 b.n 800bee0 <_malloc_r+0xa8> 800bf32: bf00 nop 800bf34: 20003514 .word 0x20003514 0800bf38 <__sflush_r>: 800bf38: f9b1 200c ldrsh.w r2, [r1, #12] 800bf3c: b5f8 push {r3, r4, r5, r6, r7, lr} 800bf3e: 0716 lsls r6, r2, #28 800bf40: 4605 mov r5, r0 800bf42: 460c mov r4, r1 800bf44: d454 bmi.n 800bff0 <__sflush_r+0xb8> 800bf46: 684b ldr r3, [r1, #4] 800bf48: 2b00 cmp r3, #0 800bf4a: dc02 bgt.n 800bf52 <__sflush_r+0x1a> 800bf4c: 6c0b ldr r3, [r1, #64] @ 0x40 800bf4e: 2b00 cmp r3, #0 800bf50: dd48 ble.n 800bfe4 <__sflush_r+0xac> 800bf52: 6ae6 ldr r6, [r4, #44] @ 0x2c 800bf54: 2e00 cmp r6, #0 800bf56: d045 beq.n 800bfe4 <__sflush_r+0xac> 800bf58: 2300 movs r3, #0 800bf5a: f412 5280 ands.w r2, r2, #4096 @ 0x1000 800bf5e: 682f ldr r7, [r5, #0] 800bf60: 6a21 ldr r1, [r4, #32] 800bf62: 602b str r3, [r5, #0] 800bf64: d030 beq.n 800bfc8 <__sflush_r+0x90> 800bf66: 6d62 ldr r2, [r4, #84] @ 0x54 800bf68: 89a3 ldrh r3, [r4, #12] 800bf6a: 0759 lsls r1, r3, #29 800bf6c: d505 bpl.n 800bf7a <__sflush_r+0x42> 800bf6e: 6863 ldr r3, [r4, #4] 800bf70: 1ad2 subs r2, r2, r3 800bf72: 6b63 ldr r3, [r4, #52] @ 0x34 800bf74: b10b cbz r3, 800bf7a <__sflush_r+0x42> 800bf76: 6c23 ldr r3, [r4, #64] @ 0x40 800bf78: 1ad2 subs r2, r2, r3 800bf7a: 2300 movs r3, #0 800bf7c: 4628 mov r0, r5 800bf7e: 6ae6 ldr r6, [r4, #44] @ 0x2c 800bf80: 6a21 ldr r1, [r4, #32] 800bf82: 47b0 blx r6 800bf84: 1c43 adds r3, r0, #1 800bf86: 89a3 ldrh r3, [r4, #12] 800bf88: d106 bne.n 800bf98 <__sflush_r+0x60> 800bf8a: 6829 ldr r1, [r5, #0] 800bf8c: 291d cmp r1, #29 800bf8e: d82b bhi.n 800bfe8 <__sflush_r+0xb0> 800bf90: 4a28 ldr r2, [pc, #160] @ (800c034 <__sflush_r+0xfc>) 800bf92: 40ca lsrs r2, r1 800bf94: 07d6 lsls r6, r2, #31 800bf96: d527 bpl.n 800bfe8 <__sflush_r+0xb0> 800bf98: 2200 movs r2, #0 800bf9a: 6062 str r2, [r4, #4] 800bf9c: 6922 ldr r2, [r4, #16] 800bf9e: 04d9 lsls r1, r3, #19 800bfa0: 6022 str r2, [r4, #0] 800bfa2: d504 bpl.n 800bfae <__sflush_r+0x76> 800bfa4: 1c42 adds r2, r0, #1 800bfa6: d101 bne.n 800bfac <__sflush_r+0x74> 800bfa8: 682b ldr r3, [r5, #0] 800bfaa: b903 cbnz r3, 800bfae <__sflush_r+0x76> 800bfac: 6560 str r0, [r4, #84] @ 0x54 800bfae: 6b61 ldr r1, [r4, #52] @ 0x34 800bfb0: 602f str r7, [r5, #0] 800bfb2: b1b9 cbz r1, 800bfe4 <__sflush_r+0xac> 800bfb4: f104 0344 add.w r3, r4, #68 @ 0x44 800bfb8: 4299 cmp r1, r3 800bfba: d002 beq.n 800bfc2 <__sflush_r+0x8a> 800bfbc: 4628 mov r0, r5 800bfbe: f000 fec9 bl 800cd54 <_free_r> 800bfc2: 2300 movs r3, #0 800bfc4: 6363 str r3, [r4, #52] @ 0x34 800bfc6: e00d b.n 800bfe4 <__sflush_r+0xac> 800bfc8: 2301 movs r3, #1 800bfca: 4628 mov r0, r5 800bfcc: 47b0 blx r6 800bfce: 4602 mov r2, r0 800bfd0: 1c50 adds r0, r2, #1 800bfd2: d1c9 bne.n 800bf68 <__sflush_r+0x30> 800bfd4: 682b ldr r3, [r5, #0] 800bfd6: 2b00 cmp r3, #0 800bfd8: d0c6 beq.n 800bf68 <__sflush_r+0x30> 800bfda: 2b1d cmp r3, #29 800bfdc: d001 beq.n 800bfe2 <__sflush_r+0xaa> 800bfde: 2b16 cmp r3, #22 800bfe0: d11d bne.n 800c01e <__sflush_r+0xe6> 800bfe2: 602f str r7, [r5, #0] 800bfe4: 2000 movs r0, #0 800bfe6: e021 b.n 800c02c <__sflush_r+0xf4> 800bfe8: f043 0340 orr.w r3, r3, #64 @ 0x40 800bfec: b21b sxth r3, r3 800bfee: e01a b.n 800c026 <__sflush_r+0xee> 800bff0: 690f ldr r7, [r1, #16] 800bff2: 2f00 cmp r7, #0 800bff4: d0f6 beq.n 800bfe4 <__sflush_r+0xac> 800bff6: 0793 lsls r3, r2, #30 800bff8: bf18 it ne 800bffa: 2300 movne r3, #0 800bffc: 680e ldr r6, [r1, #0] 800bffe: bf08 it eq 800c000: 694b ldreq r3, [r1, #20] 800c002: 1bf6 subs r6, r6, r7 800c004: 600f str r7, [r1, #0] 800c006: 608b str r3, [r1, #8] 800c008: 2e00 cmp r6, #0 800c00a: ddeb ble.n 800bfe4 <__sflush_r+0xac> 800c00c: 4633 mov r3, r6 800c00e: 463a mov r2, r7 800c010: 4628 mov r0, r5 800c012: 6a21 ldr r1, [r4, #32] 800c014: f8d4 c028 ldr.w ip, [r4, #40] @ 0x28 800c018: 47e0 blx ip 800c01a: 2800 cmp r0, #0 800c01c: dc07 bgt.n 800c02e <__sflush_r+0xf6> 800c01e: f9b4 300c ldrsh.w r3, [r4, #12] 800c022: f043 0340 orr.w r3, r3, #64 @ 0x40 800c026: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800c02a: 81a3 strh r3, [r4, #12] 800c02c: bdf8 pop {r3, r4, r5, r6, r7, pc} 800c02e: 4407 add r7, r0 800c030: 1a36 subs r6, r6, r0 800c032: e7e9 b.n 800c008 <__sflush_r+0xd0> 800c034: 20400001 .word 0x20400001 0800c038 <_fflush_r>: 800c038: b538 push {r3, r4, r5, lr} 800c03a: 690b ldr r3, [r1, #16] 800c03c: 4605 mov r5, r0 800c03e: 460c mov r4, r1 800c040: b913 cbnz r3, 800c048 <_fflush_r+0x10> 800c042: 2500 movs r5, #0 800c044: 4628 mov r0, r5 800c046: bd38 pop {r3, r4, r5, pc} 800c048: b118 cbz r0, 800c052 <_fflush_r+0x1a> 800c04a: 6a03 ldr r3, [r0, #32] 800c04c: b90b cbnz r3, 800c052 <_fflush_r+0x1a> 800c04e: f7fd ff5b bl 8009f08 <__sinit> 800c052: f9b4 300c ldrsh.w r3, [r4, #12] 800c056: 2b00 cmp r3, #0 800c058: d0f3 beq.n 800c042 <_fflush_r+0xa> 800c05a: 6e62 ldr r2, [r4, #100] @ 0x64 800c05c: 07d0 lsls r0, r2, #31 800c05e: d404 bmi.n 800c06a <_fflush_r+0x32> 800c060: 0599 lsls r1, r3, #22 800c062: d402 bmi.n 800c06a <_fflush_r+0x32> 800c064: 6da0 ldr r0, [r4, #88] @ 0x58 800c066: f7fe fb0f bl 800a688 <__retarget_lock_acquire_recursive> 800c06a: 4628 mov r0, r5 800c06c: 4621 mov r1, r4 800c06e: f7ff ff63 bl 800bf38 <__sflush_r> 800c072: 6e63 ldr r3, [r4, #100] @ 0x64 800c074: 4605 mov r5, r0 800c076: 07da lsls r2, r3, #31 800c078: d4e4 bmi.n 800c044 <_fflush_r+0xc> 800c07a: 89a3 ldrh r3, [r4, #12] 800c07c: 059b lsls r3, r3, #22 800c07e: d4e1 bmi.n 800c044 <_fflush_r+0xc> 800c080: 6da0 ldr r0, [r4, #88] @ 0x58 800c082: f7fe fb03 bl 800a68c <__retarget_lock_release_recursive> 800c086: e7dd b.n 800c044 <_fflush_r+0xc> 0800c088 <__malloc_lock>: 800c088: 4801 ldr r0, [pc, #4] @ (800c090 <__malloc_lock+0x8>) 800c08a: f7fe bafd b.w 800a688 <__retarget_lock_acquire_recursive> 800c08e: bf00 nop 800c090: 200034ea .word 0x200034ea 0800c094 <__malloc_unlock>: 800c094: 4801 ldr r0, [pc, #4] @ (800c09c <__malloc_unlock+0x8>) 800c096: f7fe baf9 b.w 800a68c <__retarget_lock_release_recursive> 800c09a: bf00 nop 800c09c: 200034ea .word 0x200034ea 0800c0a0 <_Balloc>: 800c0a0: b570 push {r4, r5, r6, lr} 800c0a2: 69c6 ldr r6, [r0, #28] 800c0a4: 4604 mov r4, r0 800c0a6: 460d mov r5, r1 800c0a8: b976 cbnz r6, 800c0c8 <_Balloc+0x28> 800c0aa: 2010 movs r0, #16 800c0ac: f7ff fe92 bl 800bdd4 800c0b0: 4602 mov r2, r0 800c0b2: 61e0 str r0, [r4, #28] 800c0b4: b920 cbnz r0, 800c0c0 <_Balloc+0x20> 800c0b6: 216b movs r1, #107 @ 0x6b 800c0b8: 4b17 ldr r3, [pc, #92] @ (800c118 <_Balloc+0x78>) 800c0ba: 4818 ldr r0, [pc, #96] @ (800c11c <_Balloc+0x7c>) 800c0bc: f7fe fd34 bl 800ab28 <__assert_func> 800c0c0: e9c0 6601 strd r6, r6, [r0, #4] 800c0c4: 6006 str r6, [r0, #0] 800c0c6: 60c6 str r6, [r0, #12] 800c0c8: 69e6 ldr r6, [r4, #28] 800c0ca: 68f3 ldr r3, [r6, #12] 800c0cc: b183 cbz r3, 800c0f0 <_Balloc+0x50> 800c0ce: 69e3 ldr r3, [r4, #28] 800c0d0: 68db ldr r3, [r3, #12] 800c0d2: f853 0025 ldr.w r0, [r3, r5, lsl #2] 800c0d6: b9b8 cbnz r0, 800c108 <_Balloc+0x68> 800c0d8: 2101 movs r1, #1 800c0da: fa01 f605 lsl.w r6, r1, r5 800c0de: 1d72 adds r2, r6, #5 800c0e0: 4620 mov r0, r4 800c0e2: 0092 lsls r2, r2, #2 800c0e4: f000 fe15 bl 800cd12 <_calloc_r> 800c0e8: b160 cbz r0, 800c104 <_Balloc+0x64> 800c0ea: e9c0 5601 strd r5, r6, [r0, #4] 800c0ee: e00e b.n 800c10e <_Balloc+0x6e> 800c0f0: 2221 movs r2, #33 @ 0x21 800c0f2: 2104 movs r1, #4 800c0f4: 4620 mov r0, r4 800c0f6: f000 fe0c bl 800cd12 <_calloc_r> 800c0fa: 69e3 ldr r3, [r4, #28] 800c0fc: 60f0 str r0, [r6, #12] 800c0fe: 68db ldr r3, [r3, #12] 800c100: 2b00 cmp r3, #0 800c102: d1e4 bne.n 800c0ce <_Balloc+0x2e> 800c104: 2000 movs r0, #0 800c106: bd70 pop {r4, r5, r6, pc} 800c108: 6802 ldr r2, [r0, #0] 800c10a: f843 2025 str.w r2, [r3, r5, lsl #2] 800c10e: 2300 movs r3, #0 800c110: e9c0 3303 strd r3, r3, [r0, #12] 800c114: e7f7 b.n 800c106 <_Balloc+0x66> 800c116: bf00 nop 800c118: 0800dfe6 .word 0x0800dfe6 800c11c: 0800e1bf .word 0x0800e1bf 0800c120 <_Bfree>: 800c120: b570 push {r4, r5, r6, lr} 800c122: 69c6 ldr r6, [r0, #28] 800c124: 4605 mov r5, r0 800c126: 460c mov r4, r1 800c128: b976 cbnz r6, 800c148 <_Bfree+0x28> 800c12a: 2010 movs r0, #16 800c12c: f7ff fe52 bl 800bdd4 800c130: 4602 mov r2, r0 800c132: 61e8 str r0, [r5, #28] 800c134: b920 cbnz r0, 800c140 <_Bfree+0x20> 800c136: 218f movs r1, #143 @ 0x8f 800c138: 4b08 ldr r3, [pc, #32] @ (800c15c <_Bfree+0x3c>) 800c13a: 4809 ldr r0, [pc, #36] @ (800c160 <_Bfree+0x40>) 800c13c: f7fe fcf4 bl 800ab28 <__assert_func> 800c140: e9c0 6601 strd r6, r6, [r0, #4] 800c144: 6006 str r6, [r0, #0] 800c146: 60c6 str r6, [r0, #12] 800c148: b13c cbz r4, 800c15a <_Bfree+0x3a> 800c14a: 69eb ldr r3, [r5, #28] 800c14c: 6862 ldr r2, [r4, #4] 800c14e: 68db ldr r3, [r3, #12] 800c150: f853 1022 ldr.w r1, [r3, r2, lsl #2] 800c154: 6021 str r1, [r4, #0] 800c156: f843 4022 str.w r4, [r3, r2, lsl #2] 800c15a: bd70 pop {r4, r5, r6, pc} 800c15c: 0800dfe6 .word 0x0800dfe6 800c160: 0800e1bf .word 0x0800e1bf 0800c164 <__multadd>: 800c164: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800c168: 4607 mov r7, r0 800c16a: 460c mov r4, r1 800c16c: 461e mov r6, r3 800c16e: 2000 movs r0, #0 800c170: 690d ldr r5, [r1, #16] 800c172: f101 0c14 add.w ip, r1, #20 800c176: f8dc 3000 ldr.w r3, [ip] 800c17a: 3001 adds r0, #1 800c17c: b299 uxth r1, r3 800c17e: fb02 6101 mla r1, r2, r1, r6 800c182: 0c1e lsrs r6, r3, #16 800c184: 0c0b lsrs r3, r1, #16 800c186: fb02 3306 mla r3, r2, r6, r3 800c18a: b289 uxth r1, r1 800c18c: eb01 4103 add.w r1, r1, r3, lsl #16 800c190: 4285 cmp r5, r0 800c192: ea4f 4613 mov.w r6, r3, lsr #16 800c196: f84c 1b04 str.w r1, [ip], #4 800c19a: dcec bgt.n 800c176 <__multadd+0x12> 800c19c: b30e cbz r6, 800c1e2 <__multadd+0x7e> 800c19e: 68a3 ldr r3, [r4, #8] 800c1a0: 42ab cmp r3, r5 800c1a2: dc19 bgt.n 800c1d8 <__multadd+0x74> 800c1a4: 6861 ldr r1, [r4, #4] 800c1a6: 4638 mov r0, r7 800c1a8: 3101 adds r1, #1 800c1aa: f7ff ff79 bl 800c0a0 <_Balloc> 800c1ae: 4680 mov r8, r0 800c1b0: b928 cbnz r0, 800c1be <__multadd+0x5a> 800c1b2: 4602 mov r2, r0 800c1b4: 21ba movs r1, #186 @ 0xba 800c1b6: 4b0c ldr r3, [pc, #48] @ (800c1e8 <__multadd+0x84>) 800c1b8: 480c ldr r0, [pc, #48] @ (800c1ec <__multadd+0x88>) 800c1ba: f7fe fcb5 bl 800ab28 <__assert_func> 800c1be: 6922 ldr r2, [r4, #16] 800c1c0: f104 010c add.w r1, r4, #12 800c1c4: 3202 adds r2, #2 800c1c6: 0092 lsls r2, r2, #2 800c1c8: 300c adds r0, #12 800c1ca: f7fe fc9f bl 800ab0c 800c1ce: 4621 mov r1, r4 800c1d0: 4638 mov r0, r7 800c1d2: f7ff ffa5 bl 800c120 <_Bfree> 800c1d6: 4644 mov r4, r8 800c1d8: eb04 0385 add.w r3, r4, r5, lsl #2 800c1dc: 3501 adds r5, #1 800c1de: 615e str r6, [r3, #20] 800c1e0: 6125 str r5, [r4, #16] 800c1e2: 4620 mov r0, r4 800c1e4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800c1e8: 0800e19d .word 0x0800e19d 800c1ec: 0800e1bf .word 0x0800e1bf 0800c1f0 <__hi0bits>: 800c1f0: 4603 mov r3, r0 800c1f2: f5b0 3f80 cmp.w r0, #65536 @ 0x10000 800c1f6: bf3a itte cc 800c1f8: 0403 lslcc r3, r0, #16 800c1fa: 2010 movcc r0, #16 800c1fc: 2000 movcs r0, #0 800c1fe: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800c202: bf3c itt cc 800c204: 021b lslcc r3, r3, #8 800c206: 3008 addcc r0, #8 800c208: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800c20c: bf3c itt cc 800c20e: 011b lslcc r3, r3, #4 800c210: 3004 addcc r0, #4 800c212: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800c216: bf3c itt cc 800c218: 009b lslcc r3, r3, #2 800c21a: 3002 addcc r0, #2 800c21c: 2b00 cmp r3, #0 800c21e: db05 blt.n 800c22c <__hi0bits+0x3c> 800c220: f013 4f80 tst.w r3, #1073741824 @ 0x40000000 800c224: f100 0001 add.w r0, r0, #1 800c228: bf08 it eq 800c22a: 2020 moveq r0, #32 800c22c: 4770 bx lr 0800c22e <__lo0bits>: 800c22e: 6803 ldr r3, [r0, #0] 800c230: 4602 mov r2, r0 800c232: f013 0007 ands.w r0, r3, #7 800c236: d00b beq.n 800c250 <__lo0bits+0x22> 800c238: 07d9 lsls r1, r3, #31 800c23a: d421 bmi.n 800c280 <__lo0bits+0x52> 800c23c: 0798 lsls r0, r3, #30 800c23e: bf49 itett mi 800c240: 085b lsrmi r3, r3, #1 800c242: 089b lsrpl r3, r3, #2 800c244: 2001 movmi r0, #1 800c246: 6013 strmi r3, [r2, #0] 800c248: bf5c itt pl 800c24a: 2002 movpl r0, #2 800c24c: 6013 strpl r3, [r2, #0] 800c24e: 4770 bx lr 800c250: b299 uxth r1, r3 800c252: b909 cbnz r1, 800c258 <__lo0bits+0x2a> 800c254: 2010 movs r0, #16 800c256: 0c1b lsrs r3, r3, #16 800c258: b2d9 uxtb r1, r3 800c25a: b909 cbnz r1, 800c260 <__lo0bits+0x32> 800c25c: 3008 adds r0, #8 800c25e: 0a1b lsrs r3, r3, #8 800c260: 0719 lsls r1, r3, #28 800c262: bf04 itt eq 800c264: 091b lsreq r3, r3, #4 800c266: 3004 addeq r0, #4 800c268: 0799 lsls r1, r3, #30 800c26a: bf04 itt eq 800c26c: 089b lsreq r3, r3, #2 800c26e: 3002 addeq r0, #2 800c270: 07d9 lsls r1, r3, #31 800c272: d403 bmi.n 800c27c <__lo0bits+0x4e> 800c274: 085b lsrs r3, r3, #1 800c276: f100 0001 add.w r0, r0, #1 800c27a: d003 beq.n 800c284 <__lo0bits+0x56> 800c27c: 6013 str r3, [r2, #0] 800c27e: 4770 bx lr 800c280: 2000 movs r0, #0 800c282: 4770 bx lr 800c284: 2020 movs r0, #32 800c286: 4770 bx lr 0800c288 <__i2b>: 800c288: b510 push {r4, lr} 800c28a: 460c mov r4, r1 800c28c: 2101 movs r1, #1 800c28e: f7ff ff07 bl 800c0a0 <_Balloc> 800c292: 4602 mov r2, r0 800c294: b928 cbnz r0, 800c2a2 <__i2b+0x1a> 800c296: f240 1145 movw r1, #325 @ 0x145 800c29a: 4b04 ldr r3, [pc, #16] @ (800c2ac <__i2b+0x24>) 800c29c: 4804 ldr r0, [pc, #16] @ (800c2b0 <__i2b+0x28>) 800c29e: f7fe fc43 bl 800ab28 <__assert_func> 800c2a2: 2301 movs r3, #1 800c2a4: 6144 str r4, [r0, #20] 800c2a6: 6103 str r3, [r0, #16] 800c2a8: bd10 pop {r4, pc} 800c2aa: bf00 nop 800c2ac: 0800e19d .word 0x0800e19d 800c2b0: 0800e1bf .word 0x0800e1bf 0800c2b4 <__multiply>: 800c2b4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800c2b8: 4617 mov r7, r2 800c2ba: 690a ldr r2, [r1, #16] 800c2bc: 693b ldr r3, [r7, #16] 800c2be: 4689 mov r9, r1 800c2c0: 429a cmp r2, r3 800c2c2: bfa2 ittt ge 800c2c4: 463b movge r3, r7 800c2c6: 460f movge r7, r1 800c2c8: 4699 movge r9, r3 800c2ca: 693d ldr r5, [r7, #16] 800c2cc: f8d9 a010 ldr.w sl, [r9, #16] 800c2d0: 68bb ldr r3, [r7, #8] 800c2d2: 6879 ldr r1, [r7, #4] 800c2d4: eb05 060a add.w r6, r5, sl 800c2d8: 42b3 cmp r3, r6 800c2da: b085 sub sp, #20 800c2dc: bfb8 it lt 800c2de: 3101 addlt r1, #1 800c2e0: f7ff fede bl 800c0a0 <_Balloc> 800c2e4: b930 cbnz r0, 800c2f4 <__multiply+0x40> 800c2e6: 4602 mov r2, r0 800c2e8: f44f 71b1 mov.w r1, #354 @ 0x162 800c2ec: 4b40 ldr r3, [pc, #256] @ (800c3f0 <__multiply+0x13c>) 800c2ee: 4841 ldr r0, [pc, #260] @ (800c3f4 <__multiply+0x140>) 800c2f0: f7fe fc1a bl 800ab28 <__assert_func> 800c2f4: f100 0414 add.w r4, r0, #20 800c2f8: 4623 mov r3, r4 800c2fa: 2200 movs r2, #0 800c2fc: eb04 0e86 add.w lr, r4, r6, lsl #2 800c300: 4573 cmp r3, lr 800c302: d320 bcc.n 800c346 <__multiply+0x92> 800c304: f107 0814 add.w r8, r7, #20 800c308: f109 0114 add.w r1, r9, #20 800c30c: eb08 0585 add.w r5, r8, r5, lsl #2 800c310: eb01 038a add.w r3, r1, sl, lsl #2 800c314: 9302 str r3, [sp, #8] 800c316: 1beb subs r3, r5, r7 800c318: 3b15 subs r3, #21 800c31a: f023 0303 bic.w r3, r3, #3 800c31e: 3304 adds r3, #4 800c320: 3715 adds r7, #21 800c322: 42bd cmp r5, r7 800c324: bf38 it cc 800c326: 2304 movcc r3, #4 800c328: 9301 str r3, [sp, #4] 800c32a: 9b02 ldr r3, [sp, #8] 800c32c: 9103 str r1, [sp, #12] 800c32e: 428b cmp r3, r1 800c330: d80c bhi.n 800c34c <__multiply+0x98> 800c332: 2e00 cmp r6, #0 800c334: dd03 ble.n 800c33e <__multiply+0x8a> 800c336: f85e 3d04 ldr.w r3, [lr, #-4]! 800c33a: 2b00 cmp r3, #0 800c33c: d055 beq.n 800c3ea <__multiply+0x136> 800c33e: 6106 str r6, [r0, #16] 800c340: b005 add sp, #20 800c342: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800c346: f843 2b04 str.w r2, [r3], #4 800c34a: e7d9 b.n 800c300 <__multiply+0x4c> 800c34c: f8b1 a000 ldrh.w sl, [r1] 800c350: f1ba 0f00 cmp.w sl, #0 800c354: d01f beq.n 800c396 <__multiply+0xe2> 800c356: 46c4 mov ip, r8 800c358: 46a1 mov r9, r4 800c35a: 2700 movs r7, #0 800c35c: f85c 2b04 ldr.w r2, [ip], #4 800c360: f8d9 3000 ldr.w r3, [r9] 800c364: fa1f fb82 uxth.w fp, r2 800c368: b29b uxth r3, r3 800c36a: fb0a 330b mla r3, sl, fp, r3 800c36e: 443b add r3, r7 800c370: f8d9 7000 ldr.w r7, [r9] 800c374: 0c12 lsrs r2, r2, #16 800c376: 0c3f lsrs r7, r7, #16 800c378: fb0a 7202 mla r2, sl, r2, r7 800c37c: eb02 4213 add.w r2, r2, r3, lsr #16 800c380: b29b uxth r3, r3 800c382: ea43 4302 orr.w r3, r3, r2, lsl #16 800c386: 4565 cmp r5, ip 800c388: ea4f 4712 mov.w r7, r2, lsr #16 800c38c: f849 3b04 str.w r3, [r9], #4 800c390: d8e4 bhi.n 800c35c <__multiply+0xa8> 800c392: 9b01 ldr r3, [sp, #4] 800c394: 50e7 str r7, [r4, r3] 800c396: 9b03 ldr r3, [sp, #12] 800c398: 3104 adds r1, #4 800c39a: f8b3 9002 ldrh.w r9, [r3, #2] 800c39e: f1b9 0f00 cmp.w r9, #0 800c3a2: d020 beq.n 800c3e6 <__multiply+0x132> 800c3a4: 4647 mov r7, r8 800c3a6: 46a4 mov ip, r4 800c3a8: f04f 0a00 mov.w sl, #0 800c3ac: 6823 ldr r3, [r4, #0] 800c3ae: f8b7 b000 ldrh.w fp, [r7] 800c3b2: f8bc 2002 ldrh.w r2, [ip, #2] 800c3b6: b29b uxth r3, r3 800c3b8: fb09 220b mla r2, r9, fp, r2 800c3bc: 4452 add r2, sl 800c3be: ea43 4302 orr.w r3, r3, r2, lsl #16 800c3c2: f84c 3b04 str.w r3, [ip], #4 800c3c6: f857 3b04 ldr.w r3, [r7], #4 800c3ca: ea4f 4a13 mov.w sl, r3, lsr #16 800c3ce: f8bc 3000 ldrh.w r3, [ip] 800c3d2: 42bd cmp r5, r7 800c3d4: fb09 330a mla r3, r9, sl, r3 800c3d8: eb03 4312 add.w r3, r3, r2, lsr #16 800c3dc: ea4f 4a13 mov.w sl, r3, lsr #16 800c3e0: d8e5 bhi.n 800c3ae <__multiply+0xfa> 800c3e2: 9a01 ldr r2, [sp, #4] 800c3e4: 50a3 str r3, [r4, r2] 800c3e6: 3404 adds r4, #4 800c3e8: e79f b.n 800c32a <__multiply+0x76> 800c3ea: 3e01 subs r6, #1 800c3ec: e7a1 b.n 800c332 <__multiply+0x7e> 800c3ee: bf00 nop 800c3f0: 0800e19d .word 0x0800e19d 800c3f4: 0800e1bf .word 0x0800e1bf 0800c3f8 <__pow5mult>: 800c3f8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 800c3fc: 4615 mov r5, r2 800c3fe: f012 0203 ands.w r2, r2, #3 800c402: 4607 mov r7, r0 800c404: 460e mov r6, r1 800c406: d007 beq.n 800c418 <__pow5mult+0x20> 800c408: 4c25 ldr r4, [pc, #148] @ (800c4a0 <__pow5mult+0xa8>) 800c40a: 3a01 subs r2, #1 800c40c: 2300 movs r3, #0 800c40e: f854 2022 ldr.w r2, [r4, r2, lsl #2] 800c412: f7ff fea7 bl 800c164 <__multadd> 800c416: 4606 mov r6, r0 800c418: 10ad asrs r5, r5, #2 800c41a: d03d beq.n 800c498 <__pow5mult+0xa0> 800c41c: 69fc ldr r4, [r7, #28] 800c41e: b97c cbnz r4, 800c440 <__pow5mult+0x48> 800c420: 2010 movs r0, #16 800c422: f7ff fcd7 bl 800bdd4 800c426: 4602 mov r2, r0 800c428: 61f8 str r0, [r7, #28] 800c42a: b928 cbnz r0, 800c438 <__pow5mult+0x40> 800c42c: f240 11b3 movw r1, #435 @ 0x1b3 800c430: 4b1c ldr r3, [pc, #112] @ (800c4a4 <__pow5mult+0xac>) 800c432: 481d ldr r0, [pc, #116] @ (800c4a8 <__pow5mult+0xb0>) 800c434: f7fe fb78 bl 800ab28 <__assert_func> 800c438: e9c0 4401 strd r4, r4, [r0, #4] 800c43c: 6004 str r4, [r0, #0] 800c43e: 60c4 str r4, [r0, #12] 800c440: f8d7 801c ldr.w r8, [r7, #28] 800c444: f8d8 4008 ldr.w r4, [r8, #8] 800c448: b94c cbnz r4, 800c45e <__pow5mult+0x66> 800c44a: f240 2171 movw r1, #625 @ 0x271 800c44e: 4638 mov r0, r7 800c450: f7ff ff1a bl 800c288 <__i2b> 800c454: 2300 movs r3, #0 800c456: 4604 mov r4, r0 800c458: f8c8 0008 str.w r0, [r8, #8] 800c45c: 6003 str r3, [r0, #0] 800c45e: f04f 0900 mov.w r9, #0 800c462: 07eb lsls r3, r5, #31 800c464: d50a bpl.n 800c47c <__pow5mult+0x84> 800c466: 4631 mov r1, r6 800c468: 4622 mov r2, r4 800c46a: 4638 mov r0, r7 800c46c: f7ff ff22 bl 800c2b4 <__multiply> 800c470: 4680 mov r8, r0 800c472: 4631 mov r1, r6 800c474: 4638 mov r0, r7 800c476: f7ff fe53 bl 800c120 <_Bfree> 800c47a: 4646 mov r6, r8 800c47c: 106d asrs r5, r5, #1 800c47e: d00b beq.n 800c498 <__pow5mult+0xa0> 800c480: 6820 ldr r0, [r4, #0] 800c482: b938 cbnz r0, 800c494 <__pow5mult+0x9c> 800c484: 4622 mov r2, r4 800c486: 4621 mov r1, r4 800c488: 4638 mov r0, r7 800c48a: f7ff ff13 bl 800c2b4 <__multiply> 800c48e: 6020 str r0, [r4, #0] 800c490: f8c0 9000 str.w r9, [r0] 800c494: 4604 mov r4, r0 800c496: e7e4 b.n 800c462 <__pow5mult+0x6a> 800c498: 4630 mov r0, r6 800c49a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 800c49e: bf00 nop 800c4a0: 0800e2a0 .word 0x0800e2a0 800c4a4: 0800dfe6 .word 0x0800dfe6 800c4a8: 0800e1bf .word 0x0800e1bf 0800c4ac <__lshift>: 800c4ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800c4b0: 460c mov r4, r1 800c4b2: 4607 mov r7, r0 800c4b4: 4691 mov r9, r2 800c4b6: 6923 ldr r3, [r4, #16] 800c4b8: 6849 ldr r1, [r1, #4] 800c4ba: eb03 1862 add.w r8, r3, r2, asr #5 800c4be: 68a3 ldr r3, [r4, #8] 800c4c0: ea4f 1a62 mov.w sl, r2, asr #5 800c4c4: f108 0601 add.w r6, r8, #1 800c4c8: 42b3 cmp r3, r6 800c4ca: db0b blt.n 800c4e4 <__lshift+0x38> 800c4cc: 4638 mov r0, r7 800c4ce: f7ff fde7 bl 800c0a0 <_Balloc> 800c4d2: 4605 mov r5, r0 800c4d4: b948 cbnz r0, 800c4ea <__lshift+0x3e> 800c4d6: 4602 mov r2, r0 800c4d8: f44f 71ef mov.w r1, #478 @ 0x1de 800c4dc: 4b27 ldr r3, [pc, #156] @ (800c57c <__lshift+0xd0>) 800c4de: 4828 ldr r0, [pc, #160] @ (800c580 <__lshift+0xd4>) 800c4e0: f7fe fb22 bl 800ab28 <__assert_func> 800c4e4: 3101 adds r1, #1 800c4e6: 005b lsls r3, r3, #1 800c4e8: e7ee b.n 800c4c8 <__lshift+0x1c> 800c4ea: 2300 movs r3, #0 800c4ec: f100 0114 add.w r1, r0, #20 800c4f0: f100 0210 add.w r2, r0, #16 800c4f4: 4618 mov r0, r3 800c4f6: 4553 cmp r3, sl 800c4f8: db33 blt.n 800c562 <__lshift+0xb6> 800c4fa: 6920 ldr r0, [r4, #16] 800c4fc: ea2a 7aea bic.w sl, sl, sl, asr #31 800c500: f104 0314 add.w r3, r4, #20 800c504: f019 091f ands.w r9, r9, #31 800c508: eb01 018a add.w r1, r1, sl, lsl #2 800c50c: eb03 0c80 add.w ip, r3, r0, lsl #2 800c510: d02b beq.n 800c56a <__lshift+0xbe> 800c512: 468a mov sl, r1 800c514: 2200 movs r2, #0 800c516: f1c9 0e20 rsb lr, r9, #32 800c51a: 6818 ldr r0, [r3, #0] 800c51c: fa00 f009 lsl.w r0, r0, r9 800c520: 4310 orrs r0, r2 800c522: f84a 0b04 str.w r0, [sl], #4 800c526: f853 2b04 ldr.w r2, [r3], #4 800c52a: 459c cmp ip, r3 800c52c: fa22 f20e lsr.w r2, r2, lr 800c530: d8f3 bhi.n 800c51a <__lshift+0x6e> 800c532: ebac 0304 sub.w r3, ip, r4 800c536: 3b15 subs r3, #21 800c538: f023 0303 bic.w r3, r3, #3 800c53c: 3304 adds r3, #4 800c53e: f104 0015 add.w r0, r4, #21 800c542: 4560 cmp r0, ip 800c544: bf88 it hi 800c546: 2304 movhi r3, #4 800c548: 50ca str r2, [r1, r3] 800c54a: b10a cbz r2, 800c550 <__lshift+0xa4> 800c54c: f108 0602 add.w r6, r8, #2 800c550: 3e01 subs r6, #1 800c552: 4638 mov r0, r7 800c554: 4621 mov r1, r4 800c556: 612e str r6, [r5, #16] 800c558: f7ff fde2 bl 800c120 <_Bfree> 800c55c: 4628 mov r0, r5 800c55e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800c562: f842 0f04 str.w r0, [r2, #4]! 800c566: 3301 adds r3, #1 800c568: e7c5 b.n 800c4f6 <__lshift+0x4a> 800c56a: 3904 subs r1, #4 800c56c: f853 2b04 ldr.w r2, [r3], #4 800c570: 459c cmp ip, r3 800c572: f841 2f04 str.w r2, [r1, #4]! 800c576: d8f9 bhi.n 800c56c <__lshift+0xc0> 800c578: e7ea b.n 800c550 <__lshift+0xa4> 800c57a: bf00 nop 800c57c: 0800e19d .word 0x0800e19d 800c580: 0800e1bf .word 0x0800e1bf 0800c584 <__mcmp>: 800c584: 4603 mov r3, r0 800c586: 690a ldr r2, [r1, #16] 800c588: 6900 ldr r0, [r0, #16] 800c58a: b530 push {r4, r5, lr} 800c58c: 1a80 subs r0, r0, r2 800c58e: d10e bne.n 800c5ae <__mcmp+0x2a> 800c590: 3314 adds r3, #20 800c592: 3114 adds r1, #20 800c594: eb03 0482 add.w r4, r3, r2, lsl #2 800c598: eb01 0182 add.w r1, r1, r2, lsl #2 800c59c: f854 5d04 ldr.w r5, [r4, #-4]! 800c5a0: f851 2d04 ldr.w r2, [r1, #-4]! 800c5a4: 4295 cmp r5, r2 800c5a6: d003 beq.n 800c5b0 <__mcmp+0x2c> 800c5a8: d205 bcs.n 800c5b6 <__mcmp+0x32> 800c5aa: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800c5ae: bd30 pop {r4, r5, pc} 800c5b0: 42a3 cmp r3, r4 800c5b2: d3f3 bcc.n 800c59c <__mcmp+0x18> 800c5b4: e7fb b.n 800c5ae <__mcmp+0x2a> 800c5b6: 2001 movs r0, #1 800c5b8: e7f9 b.n 800c5ae <__mcmp+0x2a> ... 0800c5bc <__mdiff>: 800c5bc: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 800c5c0: 4689 mov r9, r1 800c5c2: 4606 mov r6, r0 800c5c4: 4611 mov r1, r2 800c5c6: 4648 mov r0, r9 800c5c8: 4614 mov r4, r2 800c5ca: f7ff ffdb bl 800c584 <__mcmp> 800c5ce: 1e05 subs r5, r0, #0 800c5d0: d112 bne.n 800c5f8 <__mdiff+0x3c> 800c5d2: 4629 mov r1, r5 800c5d4: 4630 mov r0, r6 800c5d6: f7ff fd63 bl 800c0a0 <_Balloc> 800c5da: 4602 mov r2, r0 800c5dc: b928 cbnz r0, 800c5ea <__mdiff+0x2e> 800c5de: f240 2137 movw r1, #567 @ 0x237 800c5e2: 4b3e ldr r3, [pc, #248] @ (800c6dc <__mdiff+0x120>) 800c5e4: 483e ldr r0, [pc, #248] @ (800c6e0 <__mdiff+0x124>) 800c5e6: f7fe fa9f bl 800ab28 <__assert_func> 800c5ea: 2301 movs r3, #1 800c5ec: e9c0 3504 strd r3, r5, [r0, #16] 800c5f0: 4610 mov r0, r2 800c5f2: b003 add sp, #12 800c5f4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800c5f8: bfbc itt lt 800c5fa: 464b movlt r3, r9 800c5fc: 46a1 movlt r9, r4 800c5fe: 4630 mov r0, r6 800c600: f8d9 1004 ldr.w r1, [r9, #4] 800c604: bfba itte lt 800c606: 461c movlt r4, r3 800c608: 2501 movlt r5, #1 800c60a: 2500 movge r5, #0 800c60c: f7ff fd48 bl 800c0a0 <_Balloc> 800c610: 4602 mov r2, r0 800c612: b918 cbnz r0, 800c61c <__mdiff+0x60> 800c614: f240 2145 movw r1, #581 @ 0x245 800c618: 4b30 ldr r3, [pc, #192] @ (800c6dc <__mdiff+0x120>) 800c61a: e7e3 b.n 800c5e4 <__mdiff+0x28> 800c61c: f100 0b14 add.w fp, r0, #20 800c620: f8d9 7010 ldr.w r7, [r9, #16] 800c624: f109 0310 add.w r3, r9, #16 800c628: 60c5 str r5, [r0, #12] 800c62a: f04f 0c00 mov.w ip, #0 800c62e: f109 0514 add.w r5, r9, #20 800c632: 46d9 mov r9, fp 800c634: 6926 ldr r6, [r4, #16] 800c636: f104 0e14 add.w lr, r4, #20 800c63a: eb05 0887 add.w r8, r5, r7, lsl #2 800c63e: eb0e 0686 add.w r6, lr, r6, lsl #2 800c642: 9301 str r3, [sp, #4] 800c644: 9b01 ldr r3, [sp, #4] 800c646: f85e 0b04 ldr.w r0, [lr], #4 800c64a: f853 af04 ldr.w sl, [r3, #4]! 800c64e: b281 uxth r1, r0 800c650: 9301 str r3, [sp, #4] 800c652: fa1f f38a uxth.w r3, sl 800c656: 1a5b subs r3, r3, r1 800c658: 0c00 lsrs r0, r0, #16 800c65a: 4463 add r3, ip 800c65c: ebc0 401a rsb r0, r0, sl, lsr #16 800c660: eb00 4023 add.w r0, r0, r3, asr #16 800c664: b29b uxth r3, r3 800c666: ea43 4300 orr.w r3, r3, r0, lsl #16 800c66a: 4576 cmp r6, lr 800c66c: ea4f 4c20 mov.w ip, r0, asr #16 800c670: f849 3b04 str.w r3, [r9], #4 800c674: d8e6 bhi.n 800c644 <__mdiff+0x88> 800c676: 1b33 subs r3, r6, r4 800c678: 3b15 subs r3, #21 800c67a: f023 0303 bic.w r3, r3, #3 800c67e: 3415 adds r4, #21 800c680: 3304 adds r3, #4 800c682: 42a6 cmp r6, r4 800c684: bf38 it cc 800c686: 2304 movcc r3, #4 800c688: 441d add r5, r3 800c68a: 445b add r3, fp 800c68c: 461e mov r6, r3 800c68e: 462c mov r4, r5 800c690: 4544 cmp r4, r8 800c692: d30e bcc.n 800c6b2 <__mdiff+0xf6> 800c694: f108 0103 add.w r1, r8, #3 800c698: 1b49 subs r1, r1, r5 800c69a: f021 0103 bic.w r1, r1, #3 800c69e: 3d03 subs r5, #3 800c6a0: 45a8 cmp r8, r5 800c6a2: bf38 it cc 800c6a4: 2100 movcc r1, #0 800c6a6: 440b add r3, r1 800c6a8: f853 1d04 ldr.w r1, [r3, #-4]! 800c6ac: b199 cbz r1, 800c6d6 <__mdiff+0x11a> 800c6ae: 6117 str r7, [r2, #16] 800c6b0: e79e b.n 800c5f0 <__mdiff+0x34> 800c6b2: 46e6 mov lr, ip 800c6b4: f854 1b04 ldr.w r1, [r4], #4 800c6b8: fa1f fc81 uxth.w ip, r1 800c6bc: 44f4 add ip, lr 800c6be: 0c08 lsrs r0, r1, #16 800c6c0: 4471 add r1, lr 800c6c2: eb00 402c add.w r0, r0, ip, asr #16 800c6c6: b289 uxth r1, r1 800c6c8: ea41 4100 orr.w r1, r1, r0, lsl #16 800c6cc: ea4f 4c20 mov.w ip, r0, asr #16 800c6d0: f846 1b04 str.w r1, [r6], #4 800c6d4: e7dc b.n 800c690 <__mdiff+0xd4> 800c6d6: 3f01 subs r7, #1 800c6d8: e7e6 b.n 800c6a8 <__mdiff+0xec> 800c6da: bf00 nop 800c6dc: 0800e19d .word 0x0800e19d 800c6e0: 0800e1bf .word 0x0800e1bf 0800c6e4 <__d2b>: 800c6e4: e92d 4373 stmdb sp!, {r0, r1, r4, r5, r6, r8, r9, lr} 800c6e8: 2101 movs r1, #1 800c6ea: 4690 mov r8, r2 800c6ec: 4699 mov r9, r3 800c6ee: 9e08 ldr r6, [sp, #32] 800c6f0: f7ff fcd6 bl 800c0a0 <_Balloc> 800c6f4: 4604 mov r4, r0 800c6f6: b930 cbnz r0, 800c706 <__d2b+0x22> 800c6f8: 4602 mov r2, r0 800c6fa: f240 310f movw r1, #783 @ 0x30f 800c6fe: 4b23 ldr r3, [pc, #140] @ (800c78c <__d2b+0xa8>) 800c700: 4823 ldr r0, [pc, #140] @ (800c790 <__d2b+0xac>) 800c702: f7fe fa11 bl 800ab28 <__assert_func> 800c706: f3c9 550a ubfx r5, r9, #20, #11 800c70a: f3c9 0313 ubfx r3, r9, #0, #20 800c70e: b10d cbz r5, 800c714 <__d2b+0x30> 800c710: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800c714: 9301 str r3, [sp, #4] 800c716: f1b8 0300 subs.w r3, r8, #0 800c71a: d024 beq.n 800c766 <__d2b+0x82> 800c71c: 4668 mov r0, sp 800c71e: 9300 str r3, [sp, #0] 800c720: f7ff fd85 bl 800c22e <__lo0bits> 800c724: e9dd 1200 ldrd r1, r2, [sp] 800c728: b1d8 cbz r0, 800c762 <__d2b+0x7e> 800c72a: f1c0 0320 rsb r3, r0, #32 800c72e: fa02 f303 lsl.w r3, r2, r3 800c732: 430b orrs r3, r1 800c734: 40c2 lsrs r2, r0 800c736: 6163 str r3, [r4, #20] 800c738: 9201 str r2, [sp, #4] 800c73a: 9b01 ldr r3, [sp, #4] 800c73c: 2b00 cmp r3, #0 800c73e: bf0c ite eq 800c740: 2201 moveq r2, #1 800c742: 2202 movne r2, #2 800c744: 61a3 str r3, [r4, #24] 800c746: 6122 str r2, [r4, #16] 800c748: b1ad cbz r5, 800c776 <__d2b+0x92> 800c74a: f2a5 4533 subw r5, r5, #1075 @ 0x433 800c74e: 4405 add r5, r0 800c750: 6035 str r5, [r6, #0] 800c752: f1c0 0035 rsb r0, r0, #53 @ 0x35 800c756: 9b09 ldr r3, [sp, #36] @ 0x24 800c758: 6018 str r0, [r3, #0] 800c75a: 4620 mov r0, r4 800c75c: b002 add sp, #8 800c75e: e8bd 8370 ldmia.w sp!, {r4, r5, r6, r8, r9, pc} 800c762: 6161 str r1, [r4, #20] 800c764: e7e9 b.n 800c73a <__d2b+0x56> 800c766: a801 add r0, sp, #4 800c768: f7ff fd61 bl 800c22e <__lo0bits> 800c76c: 9b01 ldr r3, [sp, #4] 800c76e: 2201 movs r2, #1 800c770: 6163 str r3, [r4, #20] 800c772: 3020 adds r0, #32 800c774: e7e7 b.n 800c746 <__d2b+0x62> 800c776: f2a0 4032 subw r0, r0, #1074 @ 0x432 800c77a: eb04 0382 add.w r3, r4, r2, lsl #2 800c77e: 6030 str r0, [r6, #0] 800c780: 6918 ldr r0, [r3, #16] 800c782: f7ff fd35 bl 800c1f0 <__hi0bits> 800c786: ebc0 1042 rsb r0, r0, r2, lsl #5 800c78a: e7e4 b.n 800c756 <__d2b+0x72> 800c78c: 0800e19d .word 0x0800e19d 800c790: 0800e1bf .word 0x0800e1bf 0800c794 : 800c794: b40e push {r1, r2, r3} 800c796: f44f 7201 mov.w r2, #516 @ 0x204 800c79a: b570 push {r4, r5, r6, lr} 800c79c: 2500 movs r5, #0 800c79e: b09d sub sp, #116 @ 0x74 800c7a0: ac21 add r4, sp, #132 @ 0x84 800c7a2: f854 6b04 ldr.w r6, [r4], #4 800c7a6: f8ad 2014 strh.w r2, [sp, #20] 800c7aa: 951b str r5, [sp, #108] @ 0x6c 800c7ac: 9002 str r0, [sp, #8] 800c7ae: 9006 str r0, [sp, #24] 800c7b0: f7f3 fd44 bl 800023c 800c7b4: 4b0b ldr r3, [pc, #44] @ (800c7e4 ) 800c7b6: 9003 str r0, [sp, #12] 800c7b8: 930b str r3, [sp, #44] @ 0x2c 800c7ba: f64f 73ff movw r3, #65535 @ 0xffff 800c7be: 9007 str r0, [sp, #28] 800c7c0: 4809 ldr r0, [pc, #36] @ (800c7e8 ) 800c7c2: f8ad 3016 strh.w r3, [sp, #22] 800c7c6: 4632 mov r2, r6 800c7c8: 4623 mov r3, r4 800c7ca: a902 add r1, sp, #8 800c7cc: 6800 ldr r0, [r0, #0] 800c7ce: 950f str r5, [sp, #60] @ 0x3c 800c7d0: 9514 str r5, [sp, #80] @ 0x50 800c7d2: 9401 str r4, [sp, #4] 800c7d4: f000 fb60 bl 800ce98 <__ssvfiscanf_r> 800c7d8: b01d add sp, #116 @ 0x74 800c7da: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} 800c7de: b003 add sp, #12 800c7e0: 4770 bx lr 800c7e2: bf00 nop 800c7e4: 0800c80f .word 0x0800c80f 800c7e8: 20000038 .word 0x20000038 0800c7ec <__sread>: 800c7ec: b510 push {r4, lr} 800c7ee: 460c mov r4, r1 800c7f0: f9b1 100e ldrsh.w r1, [r1, #14] 800c7f4: f000 fa2c bl 800cc50 <_read_r> 800c7f8: 2800 cmp r0, #0 800c7fa: bfab itete ge 800c7fc: 6d63 ldrge r3, [r4, #84] @ 0x54 800c7fe: 89a3 ldrhlt r3, [r4, #12] 800c800: 181b addge r3, r3, r0 800c802: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 800c806: bfac ite ge 800c808: 6563 strge r3, [r4, #84] @ 0x54 800c80a: 81a3 strhlt r3, [r4, #12] 800c80c: bd10 pop {r4, pc} 0800c80e <__seofread>: 800c80e: 2000 movs r0, #0 800c810: 4770 bx lr 0800c812 <__swrite>: 800c812: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800c816: 461f mov r7, r3 800c818: 898b ldrh r3, [r1, #12] 800c81a: 4605 mov r5, r0 800c81c: 05db lsls r3, r3, #23 800c81e: 460c mov r4, r1 800c820: 4616 mov r6, r2 800c822: d505 bpl.n 800c830 <__swrite+0x1e> 800c824: 2302 movs r3, #2 800c826: 2200 movs r2, #0 800c828: f9b1 100e ldrsh.w r1, [r1, #14] 800c82c: f000 f9fe bl 800cc2c <_lseek_r> 800c830: 89a3 ldrh r3, [r4, #12] 800c832: 4632 mov r2, r6 800c834: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800c838: 81a3 strh r3, [r4, #12] 800c83a: 4628 mov r0, r5 800c83c: 463b mov r3, r7 800c83e: f9b4 100e ldrsh.w r1, [r4, #14] 800c842: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 800c846: f000 ba29 b.w 800cc9c <_write_r> 0800c84a <__sseek>: 800c84a: b510 push {r4, lr} 800c84c: 460c mov r4, r1 800c84e: f9b1 100e ldrsh.w r1, [r1, #14] 800c852: f000 f9eb bl 800cc2c <_lseek_r> 800c856: 1c43 adds r3, r0, #1 800c858: 89a3 ldrh r3, [r4, #12] 800c85a: bf15 itete ne 800c85c: 6560 strne r0, [r4, #84] @ 0x54 800c85e: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 800c862: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 800c866: 81a3 strheq r3, [r4, #12] 800c868: bf18 it ne 800c86a: 81a3 strhne r3, [r4, #12] 800c86c: bd10 pop {r4, pc} 0800c86e <__sclose>: 800c86e: f9b1 100e ldrsh.w r1, [r1, #14] 800c872: f000 ba25 b.w 800ccc0 <_close_r> ... 0800c878 : 800c878: b40e push {r1, r2, r3} 800c87a: b503 push {r0, r1, lr} 800c87c: 4601 mov r1, r0 800c87e: ab03 add r3, sp, #12 800c880: 4805 ldr r0, [pc, #20] @ (800c898 ) 800c882: f853 2b04 ldr.w r2, [r3], #4 800c886: 6800 ldr r0, [r0, #0] 800c888: 9301 str r3, [sp, #4] 800c88a: f7ff f98b bl 800bba4 <_vfiprintf_r> 800c88e: b002 add sp, #8 800c890: f85d eb04 ldr.w lr, [sp], #4 800c894: b003 add sp, #12 800c896: 4770 bx lr 800c898: 20000038 .word 0x20000038 0800c89c <_realloc_r>: 800c89c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800c8a0: 4607 mov r7, r0 800c8a2: 4614 mov r4, r2 800c8a4: 460d mov r5, r1 800c8a6: b921 cbnz r1, 800c8b2 <_realloc_r+0x16> 800c8a8: 4611 mov r1, r2 800c8aa: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 800c8ae: f7ff bac3 b.w 800be38 <_malloc_r> 800c8b2: b92a cbnz r2, 800c8c0 <_realloc_r+0x24> 800c8b4: f000 fa4e bl 800cd54 <_free_r> 800c8b8: 4625 mov r5, r4 800c8ba: 4628 mov r0, r5 800c8bc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800c8c0: f000 fdf5 bl 800d4ae <_malloc_usable_size_r> 800c8c4: 4284 cmp r4, r0 800c8c6: 4606 mov r6, r0 800c8c8: d802 bhi.n 800c8d0 <_realloc_r+0x34> 800c8ca: ebb4 0f50 cmp.w r4, r0, lsr #1 800c8ce: d8f4 bhi.n 800c8ba <_realloc_r+0x1e> 800c8d0: 4621 mov r1, r4 800c8d2: 4638 mov r0, r7 800c8d4: f7ff fab0 bl 800be38 <_malloc_r> 800c8d8: 4680 mov r8, r0 800c8da: b908 cbnz r0, 800c8e0 <_realloc_r+0x44> 800c8dc: 4645 mov r5, r8 800c8de: e7ec b.n 800c8ba <_realloc_r+0x1e> 800c8e0: 42b4 cmp r4, r6 800c8e2: 4622 mov r2, r4 800c8e4: 4629 mov r1, r5 800c8e6: bf28 it cs 800c8e8: 4632 movcs r2, r6 800c8ea: f7fe f90f bl 800ab0c 800c8ee: 4629 mov r1, r5 800c8f0: 4638 mov r0, r7 800c8f2: f000 fa2f bl 800cd54 <_free_r> 800c8f6: e7f1 b.n 800c8dc <_realloc_r+0x40> 0800c8f8 <__swbuf_r>: 800c8f8: b5f8 push {r3, r4, r5, r6, r7, lr} 800c8fa: 460e mov r6, r1 800c8fc: 4614 mov r4, r2 800c8fe: 4605 mov r5, r0 800c900: b118 cbz r0, 800c90a <__swbuf_r+0x12> 800c902: 6a03 ldr r3, [r0, #32] 800c904: b90b cbnz r3, 800c90a <__swbuf_r+0x12> 800c906: f7fd faff bl 8009f08 <__sinit> 800c90a: 69a3 ldr r3, [r4, #24] 800c90c: 60a3 str r3, [r4, #8] 800c90e: 89a3 ldrh r3, [r4, #12] 800c910: 071a lsls r2, r3, #28 800c912: d501 bpl.n 800c918 <__swbuf_r+0x20> 800c914: 6923 ldr r3, [r4, #16] 800c916: b943 cbnz r3, 800c92a <__swbuf_r+0x32> 800c918: 4621 mov r1, r4 800c91a: 4628 mov r0, r5 800c91c: f000 f8a4 bl 800ca68 <__swsetup_r> 800c920: b118 cbz r0, 800c92a <__swbuf_r+0x32> 800c922: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff 800c926: 4638 mov r0, r7 800c928: bdf8 pop {r3, r4, r5, r6, r7, pc} 800c92a: 6823 ldr r3, [r4, #0] 800c92c: 6922 ldr r2, [r4, #16] 800c92e: b2f6 uxtb r6, r6 800c930: 1a98 subs r0, r3, r2 800c932: 6963 ldr r3, [r4, #20] 800c934: 4637 mov r7, r6 800c936: 4283 cmp r3, r0 800c938: dc05 bgt.n 800c946 <__swbuf_r+0x4e> 800c93a: 4621 mov r1, r4 800c93c: 4628 mov r0, r5 800c93e: f7ff fb7b bl 800c038 <_fflush_r> 800c942: 2800 cmp r0, #0 800c944: d1ed bne.n 800c922 <__swbuf_r+0x2a> 800c946: 68a3 ldr r3, [r4, #8] 800c948: 3b01 subs r3, #1 800c94a: 60a3 str r3, [r4, #8] 800c94c: 6823 ldr r3, [r4, #0] 800c94e: 1c5a adds r2, r3, #1 800c950: 6022 str r2, [r4, #0] 800c952: 701e strb r6, [r3, #0] 800c954: 6962 ldr r2, [r4, #20] 800c956: 1c43 adds r3, r0, #1 800c958: 429a cmp r2, r3 800c95a: d004 beq.n 800c966 <__swbuf_r+0x6e> 800c95c: 89a3 ldrh r3, [r4, #12] 800c95e: 07db lsls r3, r3, #31 800c960: d5e1 bpl.n 800c926 <__swbuf_r+0x2e> 800c962: 2e0a cmp r6, #10 800c964: d1df bne.n 800c926 <__swbuf_r+0x2e> 800c966: 4621 mov r1, r4 800c968: 4628 mov r0, r5 800c96a: f7ff fb65 bl 800c038 <_fflush_r> 800c96e: 2800 cmp r0, #0 800c970: d0d9 beq.n 800c926 <__swbuf_r+0x2e> 800c972: e7d6 b.n 800c922 <__swbuf_r+0x2a> 0800c974 <_strtoul_l.isra.0>: 800c974: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 800c978: 4686 mov lr, r0 800c97a: 460d mov r5, r1 800c97c: 4e33 ldr r6, [pc, #204] @ (800ca4c <_strtoul_l.isra.0+0xd8>) 800c97e: 4628 mov r0, r5 800c980: f815 4b01 ldrb.w r4, [r5], #1 800c984: 5d37 ldrb r7, [r6, r4] 800c986: f017 0708 ands.w r7, r7, #8 800c98a: d1f8 bne.n 800c97e <_strtoul_l.isra.0+0xa> 800c98c: 2c2d cmp r4, #45 @ 0x2d 800c98e: d110 bne.n 800c9b2 <_strtoul_l.isra.0+0x3e> 800c990: 2701 movs r7, #1 800c992: 782c ldrb r4, [r5, #0] 800c994: 1c85 adds r5, r0, #2 800c996: f033 0010 bics.w r0, r3, #16 800c99a: d115 bne.n 800c9c8 <_strtoul_l.isra.0+0x54> 800c99c: 2c30 cmp r4, #48 @ 0x30 800c99e: d10d bne.n 800c9bc <_strtoul_l.isra.0+0x48> 800c9a0: 7828 ldrb r0, [r5, #0] 800c9a2: f000 00df and.w r0, r0, #223 @ 0xdf 800c9a6: 2858 cmp r0, #88 @ 0x58 800c9a8: d108 bne.n 800c9bc <_strtoul_l.isra.0+0x48> 800c9aa: 786c ldrb r4, [r5, #1] 800c9ac: 3502 adds r5, #2 800c9ae: 2310 movs r3, #16 800c9b0: e00a b.n 800c9c8 <_strtoul_l.isra.0+0x54> 800c9b2: 2c2b cmp r4, #43 @ 0x2b 800c9b4: bf04 itt eq 800c9b6: 782c ldrbeq r4, [r5, #0] 800c9b8: 1c85 addeq r5, r0, #2 800c9ba: e7ec b.n 800c996 <_strtoul_l.isra.0+0x22> 800c9bc: 2b00 cmp r3, #0 800c9be: d1f6 bne.n 800c9ae <_strtoul_l.isra.0+0x3a> 800c9c0: 2c30 cmp r4, #48 @ 0x30 800c9c2: bf14 ite ne 800c9c4: 230a movne r3, #10 800c9c6: 2308 moveq r3, #8 800c9c8: f04f 38ff mov.w r8, #4294967295 @ 0xffffffff 800c9cc: fbb8 f8f3 udiv r8, r8, r3 800c9d0: 2600 movs r6, #0 800c9d2: fb03 f908 mul.w r9, r3, r8 800c9d6: 4630 mov r0, r6 800c9d8: ea6f 0909 mvn.w r9, r9 800c9dc: f1a4 0c30 sub.w ip, r4, #48 @ 0x30 800c9e0: f1bc 0f09 cmp.w ip, #9 800c9e4: d810 bhi.n 800ca08 <_strtoul_l.isra.0+0x94> 800c9e6: 4664 mov r4, ip 800c9e8: 42a3 cmp r3, r4 800c9ea: dd1e ble.n 800ca2a <_strtoul_l.isra.0+0xb6> 800c9ec: f1b6 3fff cmp.w r6, #4294967295 @ 0xffffffff 800c9f0: d007 beq.n 800ca02 <_strtoul_l.isra.0+0x8e> 800c9f2: 4580 cmp r8, r0 800c9f4: d316 bcc.n 800ca24 <_strtoul_l.isra.0+0xb0> 800c9f6: d101 bne.n 800c9fc <_strtoul_l.isra.0+0x88> 800c9f8: 45a1 cmp r9, r4 800c9fa: db13 blt.n 800ca24 <_strtoul_l.isra.0+0xb0> 800c9fc: 2601 movs r6, #1 800c9fe: fb00 4003 mla r0, r0, r3, r4 800ca02: f815 4b01 ldrb.w r4, [r5], #1 800ca06: e7e9 b.n 800c9dc <_strtoul_l.isra.0+0x68> 800ca08: f1a4 0c41 sub.w ip, r4, #65 @ 0x41 800ca0c: f1bc 0f19 cmp.w ip, #25 800ca10: d801 bhi.n 800ca16 <_strtoul_l.isra.0+0xa2> 800ca12: 3c37 subs r4, #55 @ 0x37 800ca14: e7e8 b.n 800c9e8 <_strtoul_l.isra.0+0x74> 800ca16: f1a4 0c61 sub.w ip, r4, #97 @ 0x61 800ca1a: f1bc 0f19 cmp.w ip, #25 800ca1e: d804 bhi.n 800ca2a <_strtoul_l.isra.0+0xb6> 800ca20: 3c57 subs r4, #87 @ 0x57 800ca22: e7e1 b.n 800c9e8 <_strtoul_l.isra.0+0x74> 800ca24: f04f 36ff mov.w r6, #4294967295 @ 0xffffffff 800ca28: e7eb b.n 800ca02 <_strtoul_l.isra.0+0x8e> 800ca2a: 1c73 adds r3, r6, #1 800ca2c: d106 bne.n 800ca3c <_strtoul_l.isra.0+0xc8> 800ca2e: 2322 movs r3, #34 @ 0x22 800ca30: 4630 mov r0, r6 800ca32: f8ce 3000 str.w r3, [lr] 800ca36: b932 cbnz r2, 800ca46 <_strtoul_l.isra.0+0xd2> 800ca38: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 800ca3c: b107 cbz r7, 800ca40 <_strtoul_l.isra.0+0xcc> 800ca3e: 4240 negs r0, r0 800ca40: 2a00 cmp r2, #0 800ca42: d0f9 beq.n 800ca38 <_strtoul_l.isra.0+0xc4> 800ca44: b106 cbz r6, 800ca48 <_strtoul_l.isra.0+0xd4> 800ca46: 1e69 subs r1, r5, #1 800ca48: 6011 str r1, [r2, #0] 800ca4a: e7f5 b.n 800ca38 <_strtoul_l.isra.0+0xc4> 800ca4c: 0800e3a1 .word 0x0800e3a1 0800ca50 <_strtoul_r>: 800ca50: f7ff bf90 b.w 800c974 <_strtoul_l.isra.0> 0800ca54 : 800ca54: 4613 mov r3, r2 800ca56: 460a mov r2, r1 800ca58: 4601 mov r1, r0 800ca5a: 4802 ldr r0, [pc, #8] @ (800ca64 ) 800ca5c: 6800 ldr r0, [r0, #0] 800ca5e: f7ff bf89 b.w 800c974 <_strtoul_l.isra.0> 800ca62: bf00 nop 800ca64: 20000038 .word 0x20000038 0800ca68 <__swsetup_r>: 800ca68: b538 push {r3, r4, r5, lr} 800ca6a: 4b29 ldr r3, [pc, #164] @ (800cb10 <__swsetup_r+0xa8>) 800ca6c: 4605 mov r5, r0 800ca6e: 6818 ldr r0, [r3, #0] 800ca70: 460c mov r4, r1 800ca72: b118 cbz r0, 800ca7c <__swsetup_r+0x14> 800ca74: 6a03 ldr r3, [r0, #32] 800ca76: b90b cbnz r3, 800ca7c <__swsetup_r+0x14> 800ca78: f7fd fa46 bl 8009f08 <__sinit> 800ca7c: f9b4 300c ldrsh.w r3, [r4, #12] 800ca80: 0719 lsls r1, r3, #28 800ca82: d422 bmi.n 800caca <__swsetup_r+0x62> 800ca84: 06da lsls r2, r3, #27 800ca86: d407 bmi.n 800ca98 <__swsetup_r+0x30> 800ca88: 2209 movs r2, #9 800ca8a: 602a str r2, [r5, #0] 800ca8c: f043 0340 orr.w r3, r3, #64 @ 0x40 800ca90: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800ca94: 81a3 strh r3, [r4, #12] 800ca96: e033 b.n 800cb00 <__swsetup_r+0x98> 800ca98: 0758 lsls r0, r3, #29 800ca9a: d512 bpl.n 800cac2 <__swsetup_r+0x5a> 800ca9c: 6b61 ldr r1, [r4, #52] @ 0x34 800ca9e: b141 cbz r1, 800cab2 <__swsetup_r+0x4a> 800caa0: f104 0344 add.w r3, r4, #68 @ 0x44 800caa4: 4299 cmp r1, r3 800caa6: d002 beq.n 800caae <__swsetup_r+0x46> 800caa8: 4628 mov r0, r5 800caaa: f000 f953 bl 800cd54 <_free_r> 800caae: 2300 movs r3, #0 800cab0: 6363 str r3, [r4, #52] @ 0x34 800cab2: 89a3 ldrh r3, [r4, #12] 800cab4: f023 0324 bic.w r3, r3, #36 @ 0x24 800cab8: 81a3 strh r3, [r4, #12] 800caba: 2300 movs r3, #0 800cabc: 6063 str r3, [r4, #4] 800cabe: 6923 ldr r3, [r4, #16] 800cac0: 6023 str r3, [r4, #0] 800cac2: 89a3 ldrh r3, [r4, #12] 800cac4: f043 0308 orr.w r3, r3, #8 800cac8: 81a3 strh r3, [r4, #12] 800caca: 6923 ldr r3, [r4, #16] 800cacc: b94b cbnz r3, 800cae2 <__swsetup_r+0x7a> 800cace: 89a3 ldrh r3, [r4, #12] 800cad0: f403 7320 and.w r3, r3, #640 @ 0x280 800cad4: f5b3 7f00 cmp.w r3, #512 @ 0x200 800cad8: d003 beq.n 800cae2 <__swsetup_r+0x7a> 800cada: 4621 mov r1, r4 800cadc: 4628 mov r0, r5 800cade: f000 f83e bl 800cb5e <__smakebuf_r> 800cae2: f9b4 300c ldrsh.w r3, [r4, #12] 800cae6: f013 0201 ands.w r2, r3, #1 800caea: d00a beq.n 800cb02 <__swsetup_r+0x9a> 800caec: 2200 movs r2, #0 800caee: 60a2 str r2, [r4, #8] 800caf0: 6962 ldr r2, [r4, #20] 800caf2: 4252 negs r2, r2 800caf4: 61a2 str r2, [r4, #24] 800caf6: 6922 ldr r2, [r4, #16] 800caf8: b942 cbnz r2, 800cb0c <__swsetup_r+0xa4> 800cafa: f013 0080 ands.w r0, r3, #128 @ 0x80 800cafe: d1c5 bne.n 800ca8c <__swsetup_r+0x24> 800cb00: bd38 pop {r3, r4, r5, pc} 800cb02: 0799 lsls r1, r3, #30 800cb04: bf58 it pl 800cb06: 6962 ldrpl r2, [r4, #20] 800cb08: 60a2 str r2, [r4, #8] 800cb0a: e7f4 b.n 800caf6 <__swsetup_r+0x8e> 800cb0c: 2000 movs r0, #0 800cb0e: e7f7 b.n 800cb00 <__swsetup_r+0x98> 800cb10: 20000038 .word 0x20000038 0800cb14 <__swhatbuf_r>: 800cb14: b570 push {r4, r5, r6, lr} 800cb16: 460c mov r4, r1 800cb18: f9b1 100e ldrsh.w r1, [r1, #14] 800cb1c: 4615 mov r5, r2 800cb1e: 2900 cmp r1, #0 800cb20: 461e mov r6, r3 800cb22: b096 sub sp, #88 @ 0x58 800cb24: da0c bge.n 800cb40 <__swhatbuf_r+0x2c> 800cb26: 89a3 ldrh r3, [r4, #12] 800cb28: 2100 movs r1, #0 800cb2a: f013 0f80 tst.w r3, #128 @ 0x80 800cb2e: bf14 ite ne 800cb30: 2340 movne r3, #64 @ 0x40 800cb32: f44f 6380 moveq.w r3, #1024 @ 0x400 800cb36: 2000 movs r0, #0 800cb38: 6031 str r1, [r6, #0] 800cb3a: 602b str r3, [r5, #0] 800cb3c: b016 add sp, #88 @ 0x58 800cb3e: bd70 pop {r4, r5, r6, pc} 800cb40: 466a mov r2, sp 800cb42: f000 f8cd bl 800cce0 <_fstat_r> 800cb46: 2800 cmp r0, #0 800cb48: dbed blt.n 800cb26 <__swhatbuf_r+0x12> 800cb4a: 9901 ldr r1, [sp, #4] 800cb4c: f401 4170 and.w r1, r1, #61440 @ 0xf000 800cb50: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 800cb54: 4259 negs r1, r3 800cb56: 4159 adcs r1, r3 800cb58: f44f 6380 mov.w r3, #1024 @ 0x400 800cb5c: e7eb b.n 800cb36 <__swhatbuf_r+0x22> 0800cb5e <__smakebuf_r>: 800cb5e: 898b ldrh r3, [r1, #12] 800cb60: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 800cb62: 079d lsls r5, r3, #30 800cb64: 4606 mov r6, r0 800cb66: 460c mov r4, r1 800cb68: d507 bpl.n 800cb7a <__smakebuf_r+0x1c> 800cb6a: f104 0347 add.w r3, r4, #71 @ 0x47 800cb6e: 6023 str r3, [r4, #0] 800cb70: 6123 str r3, [r4, #16] 800cb72: 2301 movs r3, #1 800cb74: 6163 str r3, [r4, #20] 800cb76: b003 add sp, #12 800cb78: bdf0 pop {r4, r5, r6, r7, pc} 800cb7a: 466a mov r2, sp 800cb7c: ab01 add r3, sp, #4 800cb7e: f7ff ffc9 bl 800cb14 <__swhatbuf_r> 800cb82: 9f00 ldr r7, [sp, #0] 800cb84: 4605 mov r5, r0 800cb86: 4639 mov r1, r7 800cb88: 4630 mov r0, r6 800cb8a: f7ff f955 bl 800be38 <_malloc_r> 800cb8e: b948 cbnz r0, 800cba4 <__smakebuf_r+0x46> 800cb90: f9b4 300c ldrsh.w r3, [r4, #12] 800cb94: 059a lsls r2, r3, #22 800cb96: d4ee bmi.n 800cb76 <__smakebuf_r+0x18> 800cb98: f023 0303 bic.w r3, r3, #3 800cb9c: f043 0302 orr.w r3, r3, #2 800cba0: 81a3 strh r3, [r4, #12] 800cba2: e7e2 b.n 800cb6a <__smakebuf_r+0xc> 800cba4: 89a3 ldrh r3, [r4, #12] 800cba6: e9c4 0704 strd r0, r7, [r4, #16] 800cbaa: f043 0380 orr.w r3, r3, #128 @ 0x80 800cbae: 81a3 strh r3, [r4, #12] 800cbb0: 9b01 ldr r3, [sp, #4] 800cbb2: 6020 str r0, [r4, #0] 800cbb4: b15b cbz r3, 800cbce <__smakebuf_r+0x70> 800cbb6: 4630 mov r0, r6 800cbb8: f9b4 100e ldrsh.w r1, [r4, #14] 800cbbc: f000 f826 bl 800cc0c <_isatty_r> 800cbc0: b128 cbz r0, 800cbce <__smakebuf_r+0x70> 800cbc2: 89a3 ldrh r3, [r4, #12] 800cbc4: f023 0303 bic.w r3, r3, #3 800cbc8: f043 0301 orr.w r3, r3, #1 800cbcc: 81a3 strh r3, [r4, #12] 800cbce: 89a3 ldrh r3, [r4, #12] 800cbd0: 431d orrs r5, r3 800cbd2: 81a5 strh r5, [r4, #12] 800cbd4: e7cf b.n 800cb76 <__smakebuf_r+0x18> 0800cbd6 : 800cbd6: 4288 cmp r0, r1 800cbd8: b510 push {r4, lr} 800cbda: eb01 0402 add.w r4, r1, r2 800cbde: d902 bls.n 800cbe6 800cbe0: 4284 cmp r4, r0 800cbe2: 4623 mov r3, r4 800cbe4: d807 bhi.n 800cbf6 800cbe6: 1e43 subs r3, r0, #1 800cbe8: 42a1 cmp r1, r4 800cbea: d008 beq.n 800cbfe 800cbec: f811 2b01 ldrb.w r2, [r1], #1 800cbf0: f803 2f01 strb.w r2, [r3, #1]! 800cbf4: e7f8 b.n 800cbe8 800cbf6: 4601 mov r1, r0 800cbf8: 4402 add r2, r0 800cbfa: 428a cmp r2, r1 800cbfc: d100 bne.n 800cc00 800cbfe: bd10 pop {r4, pc} 800cc00: f813 4d01 ldrb.w r4, [r3, #-1]! 800cc04: f802 4d01 strb.w r4, [r2, #-1]! 800cc08: e7f7 b.n 800cbfa ... 0800cc0c <_isatty_r>: 800cc0c: b538 push {r3, r4, r5, lr} 800cc0e: 2300 movs r3, #0 800cc10: 4d05 ldr r5, [pc, #20] @ (800cc28 <_isatty_r+0x1c>) 800cc12: 4604 mov r4, r0 800cc14: 4608 mov r0, r1 800cc16: 602b str r3, [r5, #0] 800cc18: f7f8 fce5 bl 80055e6 <_isatty> 800cc1c: 1c43 adds r3, r0, #1 800cc1e: d102 bne.n 800cc26 <_isatty_r+0x1a> 800cc20: 682b ldr r3, [r5, #0] 800cc22: b103 cbz r3, 800cc26 <_isatty_r+0x1a> 800cc24: 6023 str r3, [r4, #0] 800cc26: bd38 pop {r3, r4, r5, pc} 800cc28: 20003518 .word 0x20003518 0800cc2c <_lseek_r>: 800cc2c: b538 push {r3, r4, r5, lr} 800cc2e: 4604 mov r4, r0 800cc30: 4608 mov r0, r1 800cc32: 4611 mov r1, r2 800cc34: 2200 movs r2, #0 800cc36: 4d05 ldr r5, [pc, #20] @ (800cc4c <_lseek_r+0x20>) 800cc38: 602a str r2, [r5, #0] 800cc3a: 461a mov r2, r3 800cc3c: f7f8 fcdd bl 80055fa <_lseek> 800cc40: 1c43 adds r3, r0, #1 800cc42: d102 bne.n 800cc4a <_lseek_r+0x1e> 800cc44: 682b ldr r3, [r5, #0] 800cc46: b103 cbz r3, 800cc4a <_lseek_r+0x1e> 800cc48: 6023 str r3, [r4, #0] 800cc4a: bd38 pop {r3, r4, r5, pc} 800cc4c: 20003518 .word 0x20003518 0800cc50 <_read_r>: 800cc50: b538 push {r3, r4, r5, lr} 800cc52: 4604 mov r4, r0 800cc54: 4608 mov r0, r1 800cc56: 4611 mov r1, r2 800cc58: 2200 movs r2, #0 800cc5a: 4d05 ldr r5, [pc, #20] @ (800cc70 <_read_r+0x20>) 800cc5c: 602a str r2, [r5, #0] 800cc5e: 461a mov r2, r3 800cc60: f7f8 fc8a bl 8005578 <_read> 800cc64: 1c43 adds r3, r0, #1 800cc66: d102 bne.n 800cc6e <_read_r+0x1e> 800cc68: 682b ldr r3, [r5, #0] 800cc6a: b103 cbz r3, 800cc6e <_read_r+0x1e> 800cc6c: 6023 str r3, [r4, #0] 800cc6e: bd38 pop {r3, r4, r5, pc} 800cc70: 20003518 .word 0x20003518 0800cc74 <_sbrk_r>: 800cc74: b538 push {r3, r4, r5, lr} 800cc76: 2300 movs r3, #0 800cc78: 4d05 ldr r5, [pc, #20] @ (800cc90 <_sbrk_r+0x1c>) 800cc7a: 4604 mov r4, r0 800cc7c: 4608 mov r0, r1 800cc7e: 602b str r3, [r5, #0] 800cc80: f7f8 fcc8 bl 8005614 <_sbrk> 800cc84: 1c43 adds r3, r0, #1 800cc86: d102 bne.n 800cc8e <_sbrk_r+0x1a> 800cc88: 682b ldr r3, [r5, #0] 800cc8a: b103 cbz r3, 800cc8e <_sbrk_r+0x1a> 800cc8c: 6023 str r3, [r4, #0] 800cc8e: bd38 pop {r3, r4, r5, pc} 800cc90: 20003518 .word 0x20003518 0800cc94 <__gettzinfo>: 800cc94: 4800 ldr r0, [pc, #0] @ (800cc98 <__gettzinfo+0x4>) 800cc96: 4770 bx lr 800cc98: 20000088 .word 0x20000088 0800cc9c <_write_r>: 800cc9c: b538 push {r3, r4, r5, lr} 800cc9e: 4604 mov r4, r0 800cca0: 4608 mov r0, r1 800cca2: 4611 mov r1, r2 800cca4: 2200 movs r2, #0 800cca6: 4d05 ldr r5, [pc, #20] @ (800ccbc <_write_r+0x20>) 800cca8: 602a str r2, [r5, #0] 800ccaa: 461a mov r2, r3 800ccac: f7f6 f8ca bl 8002e44 <_write> 800ccb0: 1c43 adds r3, r0, #1 800ccb2: d102 bne.n 800ccba <_write_r+0x1e> 800ccb4: 682b ldr r3, [r5, #0] 800ccb6: b103 cbz r3, 800ccba <_write_r+0x1e> 800ccb8: 6023 str r3, [r4, #0] 800ccba: bd38 pop {r3, r4, r5, pc} 800ccbc: 20003518 .word 0x20003518 0800ccc0 <_close_r>: 800ccc0: b538 push {r3, r4, r5, lr} 800ccc2: 2300 movs r3, #0 800ccc4: 4d05 ldr r5, [pc, #20] @ (800ccdc <_close_r+0x1c>) 800ccc6: 4604 mov r4, r0 800ccc8: 4608 mov r0, r1 800ccca: 602b str r3, [r5, #0] 800cccc: f7f8 fc71 bl 80055b2 <_close> 800ccd0: 1c43 adds r3, r0, #1 800ccd2: d102 bne.n 800ccda <_close_r+0x1a> 800ccd4: 682b ldr r3, [r5, #0] 800ccd6: b103 cbz r3, 800ccda <_close_r+0x1a> 800ccd8: 6023 str r3, [r4, #0] 800ccda: bd38 pop {r3, r4, r5, pc} 800ccdc: 20003518 .word 0x20003518 0800cce0 <_fstat_r>: 800cce0: b538 push {r3, r4, r5, lr} 800cce2: 2300 movs r3, #0 800cce4: 4d06 ldr r5, [pc, #24] @ (800cd00 <_fstat_r+0x20>) 800cce6: 4604 mov r4, r0 800cce8: 4608 mov r0, r1 800ccea: 4611 mov r1, r2 800ccec: 602b str r3, [r5, #0] 800ccee: f7f8 fc6b bl 80055c8 <_fstat> 800ccf2: 1c43 adds r3, r0, #1 800ccf4: d102 bne.n 800ccfc <_fstat_r+0x1c> 800ccf6: 682b ldr r3, [r5, #0] 800ccf8: b103 cbz r3, 800ccfc <_fstat_r+0x1c> 800ccfa: 6023 str r3, [r4, #0] 800ccfc: bd38 pop {r3, r4, r5, pc} 800ccfe: bf00 nop 800cd00: 20003518 .word 0x20003518 0800cd04 : 800cd04: 2006 movs r0, #6 800cd06: b508 push {r3, lr} 800cd08: f000 fcc4 bl 800d694 800cd0c: 2001 movs r0, #1 800cd0e: f7f8 fc28 bl 8005562 <_exit> 0800cd12 <_calloc_r>: 800cd12: b570 push {r4, r5, r6, lr} 800cd14: fba1 5402 umull r5, r4, r1, r2 800cd18: b934 cbnz r4, 800cd28 <_calloc_r+0x16> 800cd1a: 4629 mov r1, r5 800cd1c: f7ff f88c bl 800be38 <_malloc_r> 800cd20: 4606 mov r6, r0 800cd22: b928 cbnz r0, 800cd30 <_calloc_r+0x1e> 800cd24: 4630 mov r0, r6 800cd26: bd70 pop {r4, r5, r6, pc} 800cd28: 220c movs r2, #12 800cd2a: 2600 movs r6, #0 800cd2c: 6002 str r2, [r0, #0] 800cd2e: e7f9 b.n 800cd24 <_calloc_r+0x12> 800cd30: 462a mov r2, r5 800cd32: 4621 mov r1, r4 800cd34: f7fd f9ca bl 800a0cc 800cd38: e7f4 b.n 800cd24 <_calloc_r+0x12> ... 0800cd3c <__env_lock>: 800cd3c: 4801 ldr r0, [pc, #4] @ (800cd44 <__env_lock+0x8>) 800cd3e: f7fd bca3 b.w 800a688 <__retarget_lock_acquire_recursive> 800cd42: bf00 nop 800cd44: 200034e9 .word 0x200034e9 0800cd48 <__env_unlock>: 800cd48: 4801 ldr r0, [pc, #4] @ (800cd50 <__env_unlock+0x8>) 800cd4a: f7fd bc9f b.w 800a68c <__retarget_lock_release_recursive> 800cd4e: bf00 nop 800cd50: 200034e9 .word 0x200034e9 0800cd54 <_free_r>: 800cd54: b538 push {r3, r4, r5, lr} 800cd56: 4605 mov r5, r0 800cd58: 2900 cmp r1, #0 800cd5a: d040 beq.n 800cdde <_free_r+0x8a> 800cd5c: f851 3c04 ldr.w r3, [r1, #-4] 800cd60: 1f0c subs r4, r1, #4 800cd62: 2b00 cmp r3, #0 800cd64: bfb8 it lt 800cd66: 18e4 addlt r4, r4, r3 800cd68: f7ff f98e bl 800c088 <__malloc_lock> 800cd6c: 4a1c ldr r2, [pc, #112] @ (800cde0 <_free_r+0x8c>) 800cd6e: 6813 ldr r3, [r2, #0] 800cd70: b933 cbnz r3, 800cd80 <_free_r+0x2c> 800cd72: 6063 str r3, [r4, #4] 800cd74: 6014 str r4, [r2, #0] 800cd76: 4628 mov r0, r5 800cd78: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 800cd7c: f7ff b98a b.w 800c094 <__malloc_unlock> 800cd80: 42a3 cmp r3, r4 800cd82: d908 bls.n 800cd96 <_free_r+0x42> 800cd84: 6820 ldr r0, [r4, #0] 800cd86: 1821 adds r1, r4, r0 800cd88: 428b cmp r3, r1 800cd8a: bf01 itttt eq 800cd8c: 6819 ldreq r1, [r3, #0] 800cd8e: 685b ldreq r3, [r3, #4] 800cd90: 1809 addeq r1, r1, r0 800cd92: 6021 streq r1, [r4, #0] 800cd94: e7ed b.n 800cd72 <_free_r+0x1e> 800cd96: 461a mov r2, r3 800cd98: 685b ldr r3, [r3, #4] 800cd9a: b10b cbz r3, 800cda0 <_free_r+0x4c> 800cd9c: 42a3 cmp r3, r4 800cd9e: d9fa bls.n 800cd96 <_free_r+0x42> 800cda0: 6811 ldr r1, [r2, #0] 800cda2: 1850 adds r0, r2, r1 800cda4: 42a0 cmp r0, r4 800cda6: d10b bne.n 800cdc0 <_free_r+0x6c> 800cda8: 6820 ldr r0, [r4, #0] 800cdaa: 4401 add r1, r0 800cdac: 1850 adds r0, r2, r1 800cdae: 4283 cmp r3, r0 800cdb0: 6011 str r1, [r2, #0] 800cdb2: d1e0 bne.n 800cd76 <_free_r+0x22> 800cdb4: 6818 ldr r0, [r3, #0] 800cdb6: 685b ldr r3, [r3, #4] 800cdb8: 4408 add r0, r1 800cdba: 6010 str r0, [r2, #0] 800cdbc: 6053 str r3, [r2, #4] 800cdbe: e7da b.n 800cd76 <_free_r+0x22> 800cdc0: d902 bls.n 800cdc8 <_free_r+0x74> 800cdc2: 230c movs r3, #12 800cdc4: 602b str r3, [r5, #0] 800cdc6: e7d6 b.n 800cd76 <_free_r+0x22> 800cdc8: 6820 ldr r0, [r4, #0] 800cdca: 1821 adds r1, r4, r0 800cdcc: 428b cmp r3, r1 800cdce: bf01 itttt eq 800cdd0: 6819 ldreq r1, [r3, #0] 800cdd2: 685b ldreq r3, [r3, #4] 800cdd4: 1809 addeq r1, r1, r0 800cdd6: 6021 streq r1, [r4, #0] 800cdd8: 6063 str r3, [r4, #4] 800cdda: 6054 str r4, [r2, #4] 800cddc: e7cb b.n 800cd76 <_free_r+0x22> 800cdde: bd38 pop {r3, r4, r5, pc} 800cde0: 20003514 .word 0x20003514 0800cde4 <_sungetc_r>: 800cde4: b538 push {r3, r4, r5, lr} 800cde6: 1c4b adds r3, r1, #1 800cde8: 4614 mov r4, r2 800cdea: d103 bne.n 800cdf4 <_sungetc_r+0x10> 800cdec: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff 800cdf0: 4628 mov r0, r5 800cdf2: bd38 pop {r3, r4, r5, pc} 800cdf4: 8993 ldrh r3, [r2, #12] 800cdf6: b2cd uxtb r5, r1 800cdf8: f023 0320 bic.w r3, r3, #32 800cdfc: 8193 strh r3, [r2, #12] 800cdfe: 6b63 ldr r3, [r4, #52] @ 0x34 800ce00: 6852 ldr r2, [r2, #4] 800ce02: b18b cbz r3, 800ce28 <_sungetc_r+0x44> 800ce04: 6ba3 ldr r3, [r4, #56] @ 0x38 800ce06: 4293 cmp r3, r2 800ce08: dd08 ble.n 800ce1c <_sungetc_r+0x38> 800ce0a: 6823 ldr r3, [r4, #0] 800ce0c: 1e5a subs r2, r3, #1 800ce0e: 6022 str r2, [r4, #0] 800ce10: f803 5c01 strb.w r5, [r3, #-1] 800ce14: 6863 ldr r3, [r4, #4] 800ce16: 3301 adds r3, #1 800ce18: 6063 str r3, [r4, #4] 800ce1a: e7e9 b.n 800cdf0 <_sungetc_r+0xc> 800ce1c: 4621 mov r1, r4 800ce1e: f000 fb4e bl 800d4be <__submore> 800ce22: 2800 cmp r0, #0 800ce24: d0f1 beq.n 800ce0a <_sungetc_r+0x26> 800ce26: e7e1 b.n 800cdec <_sungetc_r+0x8> 800ce28: 6921 ldr r1, [r4, #16] 800ce2a: 6823 ldr r3, [r4, #0] 800ce2c: b151 cbz r1, 800ce44 <_sungetc_r+0x60> 800ce2e: 4299 cmp r1, r3 800ce30: d208 bcs.n 800ce44 <_sungetc_r+0x60> 800ce32: f813 1c01 ldrb.w r1, [r3, #-1] 800ce36: 42a9 cmp r1, r5 800ce38: d104 bne.n 800ce44 <_sungetc_r+0x60> 800ce3a: 3b01 subs r3, #1 800ce3c: 3201 adds r2, #1 800ce3e: 6023 str r3, [r4, #0] 800ce40: 6062 str r2, [r4, #4] 800ce42: e7d5 b.n 800cdf0 <_sungetc_r+0xc> 800ce44: e9c4 320f strd r3, r2, [r4, #60] @ 0x3c 800ce48: f104 0344 add.w r3, r4, #68 @ 0x44 800ce4c: 6363 str r3, [r4, #52] @ 0x34 800ce4e: 2303 movs r3, #3 800ce50: 63a3 str r3, [r4, #56] @ 0x38 800ce52: 4623 mov r3, r4 800ce54: f803 5f46 strb.w r5, [r3, #70]! 800ce58: 6023 str r3, [r4, #0] 800ce5a: 2301 movs r3, #1 800ce5c: e7dc b.n 800ce18 <_sungetc_r+0x34> 0800ce5e <__ssrefill_r>: 800ce5e: b510 push {r4, lr} 800ce60: 460c mov r4, r1 800ce62: 6b49 ldr r1, [r1, #52] @ 0x34 800ce64: b169 cbz r1, 800ce82 <__ssrefill_r+0x24> 800ce66: f104 0344 add.w r3, r4, #68 @ 0x44 800ce6a: 4299 cmp r1, r3 800ce6c: d001 beq.n 800ce72 <__ssrefill_r+0x14> 800ce6e: f7ff ff71 bl 800cd54 <_free_r> 800ce72: 2000 movs r0, #0 800ce74: 6c23 ldr r3, [r4, #64] @ 0x40 800ce76: 6360 str r0, [r4, #52] @ 0x34 800ce78: 6063 str r3, [r4, #4] 800ce7a: b113 cbz r3, 800ce82 <__ssrefill_r+0x24> 800ce7c: 6be3 ldr r3, [r4, #60] @ 0x3c 800ce7e: 6023 str r3, [r4, #0] 800ce80: bd10 pop {r4, pc} 800ce82: 6923 ldr r3, [r4, #16] 800ce84: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800ce88: 6023 str r3, [r4, #0] 800ce8a: 2300 movs r3, #0 800ce8c: 6063 str r3, [r4, #4] 800ce8e: 89a3 ldrh r3, [r4, #12] 800ce90: f043 0320 orr.w r3, r3, #32 800ce94: 81a3 strh r3, [r4, #12] 800ce96: e7f3 b.n 800ce80 <__ssrefill_r+0x22> 0800ce98 <__ssvfiscanf_r>: 800ce98: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800ce9c: 460c mov r4, r1 800ce9e: 2100 movs r1, #0 800cea0: 4606 mov r6, r0 800cea2: f5ad 7d23 sub.w sp, sp, #652 @ 0x28c 800cea6: e9cd 1144 strd r1, r1, [sp, #272] @ 0x110 800ceaa: 49ab ldr r1, [pc, #684] @ (800d158 <__ssvfiscanf_r+0x2c0>) 800ceac: f10d 0804 add.w r8, sp, #4 800ceb0: 91a0 str r1, [sp, #640] @ 0x280 800ceb2: 49aa ldr r1, [pc, #680] @ (800d15c <__ssvfiscanf_r+0x2c4>) 800ceb4: 4faa ldr r7, [pc, #680] @ (800d160 <__ssvfiscanf_r+0x2c8>) 800ceb6: f8cd 8118 str.w r8, [sp, #280] @ 0x118 800ceba: 91a1 str r1, [sp, #644] @ 0x284 800cebc: 9300 str r3, [sp, #0] 800cebe: f892 9000 ldrb.w r9, [r2] 800cec2: f1b9 0f00 cmp.w r9, #0 800cec6: f000 8159 beq.w 800d17c <__ssvfiscanf_r+0x2e4> 800ceca: f817 3009 ldrb.w r3, [r7, r9] 800cece: 1c55 adds r5, r2, #1 800ced0: f013 0308 ands.w r3, r3, #8 800ced4: d019 beq.n 800cf0a <__ssvfiscanf_r+0x72> 800ced6: 6863 ldr r3, [r4, #4] 800ced8: 2b00 cmp r3, #0 800ceda: dd0f ble.n 800cefc <__ssvfiscanf_r+0x64> 800cedc: 6823 ldr r3, [r4, #0] 800cede: 781a ldrb r2, [r3, #0] 800cee0: 5cba ldrb r2, [r7, r2] 800cee2: 0712 lsls r2, r2, #28 800cee4: d401 bmi.n 800ceea <__ssvfiscanf_r+0x52> 800cee6: 462a mov r2, r5 800cee8: e7e9 b.n 800cebe <__ssvfiscanf_r+0x26> 800ceea: 9a45 ldr r2, [sp, #276] @ 0x114 800ceec: 3301 adds r3, #1 800ceee: 3201 adds r2, #1 800cef0: 9245 str r2, [sp, #276] @ 0x114 800cef2: 6862 ldr r2, [r4, #4] 800cef4: 6023 str r3, [r4, #0] 800cef6: 3a01 subs r2, #1 800cef8: 6062 str r2, [r4, #4] 800cefa: e7ec b.n 800ced6 <__ssvfiscanf_r+0x3e> 800cefc: 4621 mov r1, r4 800cefe: 4630 mov r0, r6 800cf00: 9ba1 ldr r3, [sp, #644] @ 0x284 800cf02: 4798 blx r3 800cf04: 2800 cmp r0, #0 800cf06: d0e9 beq.n 800cedc <__ssvfiscanf_r+0x44> 800cf08: e7ed b.n 800cee6 <__ssvfiscanf_r+0x4e> 800cf0a: f1b9 0f25 cmp.w r9, #37 @ 0x25 800cf0e: f040 8086 bne.w 800d01e <__ssvfiscanf_r+0x186> 800cf12: 9341 str r3, [sp, #260] @ 0x104 800cf14: 9343 str r3, [sp, #268] @ 0x10c 800cf16: 7853 ldrb r3, [r2, #1] 800cf18: 2b2a cmp r3, #42 @ 0x2a 800cf1a: bf04 itt eq 800cf1c: 2310 moveq r3, #16 800cf1e: 1c95 addeq r5, r2, #2 800cf20: f04f 020a mov.w r2, #10 800cf24: bf08 it eq 800cf26: 9341 streq r3, [sp, #260] @ 0x104 800cf28: 46aa mov sl, r5 800cf2a: f81a 1b01 ldrb.w r1, [sl], #1 800cf2e: f1a1 0330 sub.w r3, r1, #48 @ 0x30 800cf32: 2b09 cmp r3, #9 800cf34: d91e bls.n 800cf74 <__ssvfiscanf_r+0xdc> 800cf36: f8df b22c ldr.w fp, [pc, #556] @ 800d164 <__ssvfiscanf_r+0x2cc> 800cf3a: 2203 movs r2, #3 800cf3c: 4658 mov r0, fp 800cf3e: f7fd fdd7 bl 800aaf0 800cf42: b138 cbz r0, 800cf54 <__ssvfiscanf_r+0xbc> 800cf44: 2301 movs r3, #1 800cf46: 4655 mov r5, sl 800cf48: 9a41 ldr r2, [sp, #260] @ 0x104 800cf4a: eba0 000b sub.w r0, r0, fp 800cf4e: 4083 lsls r3, r0 800cf50: 4313 orrs r3, r2 800cf52: 9341 str r3, [sp, #260] @ 0x104 800cf54: f815 3b01 ldrb.w r3, [r5], #1 800cf58: 2b78 cmp r3, #120 @ 0x78 800cf5a: d806 bhi.n 800cf6a <__ssvfiscanf_r+0xd2> 800cf5c: 2b57 cmp r3, #87 @ 0x57 800cf5e: d810 bhi.n 800cf82 <__ssvfiscanf_r+0xea> 800cf60: 2b25 cmp r3, #37 @ 0x25 800cf62: d05c beq.n 800d01e <__ssvfiscanf_r+0x186> 800cf64: d856 bhi.n 800d014 <__ssvfiscanf_r+0x17c> 800cf66: 2b00 cmp r3, #0 800cf68: d074 beq.n 800d054 <__ssvfiscanf_r+0x1bc> 800cf6a: 2303 movs r3, #3 800cf6c: 9347 str r3, [sp, #284] @ 0x11c 800cf6e: 230a movs r3, #10 800cf70: 9342 str r3, [sp, #264] @ 0x108 800cf72: e087 b.n 800d084 <__ssvfiscanf_r+0x1ec> 800cf74: 9b43 ldr r3, [sp, #268] @ 0x10c 800cf76: 4655 mov r5, sl 800cf78: fb02 1103 mla r1, r2, r3, r1 800cf7c: 3930 subs r1, #48 @ 0x30 800cf7e: 9143 str r1, [sp, #268] @ 0x10c 800cf80: e7d2 b.n 800cf28 <__ssvfiscanf_r+0x90> 800cf82: f1a3 0258 sub.w r2, r3, #88 @ 0x58 800cf86: 2a20 cmp r2, #32 800cf88: d8ef bhi.n 800cf6a <__ssvfiscanf_r+0xd2> 800cf8a: a101 add r1, pc, #4 @ (adr r1, 800cf90 <__ssvfiscanf_r+0xf8>) 800cf8c: f851 f022 ldr.w pc, [r1, r2, lsl #2] 800cf90: 0800d063 .word 0x0800d063 800cf94: 0800cf6b .word 0x0800cf6b 800cf98: 0800cf6b .word 0x0800cf6b 800cf9c: 0800d0bd .word 0x0800d0bd 800cfa0: 0800cf6b .word 0x0800cf6b 800cfa4: 0800cf6b .word 0x0800cf6b 800cfa8: 0800cf6b .word 0x0800cf6b 800cfac: 0800cf6b .word 0x0800cf6b 800cfb0: 0800cf6b .word 0x0800cf6b 800cfb4: 0800cf6b .word 0x0800cf6b 800cfb8: 0800cf6b .word 0x0800cf6b 800cfbc: 0800d0d3 .word 0x0800d0d3 800cfc0: 0800d0b9 .word 0x0800d0b9 800cfc4: 0800d01b .word 0x0800d01b 800cfc8: 0800d01b .word 0x0800d01b 800cfcc: 0800d01b .word 0x0800d01b 800cfd0: 0800cf6b .word 0x0800cf6b 800cfd4: 0800d075 .word 0x0800d075 800cfd8: 0800cf6b .word 0x0800cf6b 800cfdc: 0800cf6b .word 0x0800cf6b 800cfe0: 0800cf6b .word 0x0800cf6b 800cfe4: 0800cf6b .word 0x0800cf6b 800cfe8: 0800d0e3 .word 0x0800d0e3 800cfec: 0800d07d .word 0x0800d07d 800cff0: 0800d05b .word 0x0800d05b 800cff4: 0800cf6b .word 0x0800cf6b 800cff8: 0800cf6b .word 0x0800cf6b 800cffc: 0800d0df .word 0x0800d0df 800d000: 0800cf6b .word 0x0800cf6b 800d004: 0800d0b9 .word 0x0800d0b9 800d008: 0800cf6b .word 0x0800cf6b 800d00c: 0800cf6b .word 0x0800cf6b 800d010: 0800d063 .word 0x0800d063 800d014: 3b45 subs r3, #69 @ 0x45 800d016: 2b02 cmp r3, #2 800d018: d8a7 bhi.n 800cf6a <__ssvfiscanf_r+0xd2> 800d01a: 2305 movs r3, #5 800d01c: e031 b.n 800d082 <__ssvfiscanf_r+0x1ea> 800d01e: 6863 ldr r3, [r4, #4] 800d020: 2b00 cmp r3, #0 800d022: dd0d ble.n 800d040 <__ssvfiscanf_r+0x1a8> 800d024: 6823 ldr r3, [r4, #0] 800d026: 781a ldrb r2, [r3, #0] 800d028: 454a cmp r2, r9 800d02a: f040 80a7 bne.w 800d17c <__ssvfiscanf_r+0x2e4> 800d02e: 3301 adds r3, #1 800d030: 6862 ldr r2, [r4, #4] 800d032: 6023 str r3, [r4, #0] 800d034: 9b45 ldr r3, [sp, #276] @ 0x114 800d036: 3a01 subs r2, #1 800d038: 3301 adds r3, #1 800d03a: 6062 str r2, [r4, #4] 800d03c: 9345 str r3, [sp, #276] @ 0x114 800d03e: e752 b.n 800cee6 <__ssvfiscanf_r+0x4e> 800d040: 4621 mov r1, r4 800d042: 4630 mov r0, r6 800d044: 9ba1 ldr r3, [sp, #644] @ 0x284 800d046: 4798 blx r3 800d048: 2800 cmp r0, #0 800d04a: d0eb beq.n 800d024 <__ssvfiscanf_r+0x18c> 800d04c: 9844 ldr r0, [sp, #272] @ 0x110 800d04e: 2800 cmp r0, #0 800d050: f040 808c bne.w 800d16c <__ssvfiscanf_r+0x2d4> 800d054: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800d058: e08c b.n 800d174 <__ssvfiscanf_r+0x2dc> 800d05a: 9a41 ldr r2, [sp, #260] @ 0x104 800d05c: f042 0220 orr.w r2, r2, #32 800d060: 9241 str r2, [sp, #260] @ 0x104 800d062: 9a41 ldr r2, [sp, #260] @ 0x104 800d064: f442 7200 orr.w r2, r2, #512 @ 0x200 800d068: 9241 str r2, [sp, #260] @ 0x104 800d06a: 2210 movs r2, #16 800d06c: 2b6e cmp r3, #110 @ 0x6e 800d06e: 9242 str r2, [sp, #264] @ 0x108 800d070: d902 bls.n 800d078 <__ssvfiscanf_r+0x1e0> 800d072: e005 b.n 800d080 <__ssvfiscanf_r+0x1e8> 800d074: 2300 movs r3, #0 800d076: 9342 str r3, [sp, #264] @ 0x108 800d078: 2303 movs r3, #3 800d07a: e002 b.n 800d082 <__ssvfiscanf_r+0x1ea> 800d07c: 2308 movs r3, #8 800d07e: 9342 str r3, [sp, #264] @ 0x108 800d080: 2304 movs r3, #4 800d082: 9347 str r3, [sp, #284] @ 0x11c 800d084: 6863 ldr r3, [r4, #4] 800d086: 2b00 cmp r3, #0 800d088: dd39 ble.n 800d0fe <__ssvfiscanf_r+0x266> 800d08a: 9b41 ldr r3, [sp, #260] @ 0x104 800d08c: 0659 lsls r1, r3, #25 800d08e: d404 bmi.n 800d09a <__ssvfiscanf_r+0x202> 800d090: 6823 ldr r3, [r4, #0] 800d092: 781a ldrb r2, [r3, #0] 800d094: 5cba ldrb r2, [r7, r2] 800d096: 0712 lsls r2, r2, #28 800d098: d438 bmi.n 800d10c <__ssvfiscanf_r+0x274> 800d09a: 9b47 ldr r3, [sp, #284] @ 0x11c 800d09c: 2b02 cmp r3, #2 800d09e: dc47 bgt.n 800d130 <__ssvfiscanf_r+0x298> 800d0a0: 466b mov r3, sp 800d0a2: 4622 mov r2, r4 800d0a4: 4630 mov r0, r6 800d0a6: a941 add r1, sp, #260 @ 0x104 800d0a8: f000 f87c bl 800d1a4 <_scanf_chars> 800d0ac: 2801 cmp r0, #1 800d0ae: d065 beq.n 800d17c <__ssvfiscanf_r+0x2e4> 800d0b0: 2802 cmp r0, #2 800d0b2: f47f af18 bne.w 800cee6 <__ssvfiscanf_r+0x4e> 800d0b6: e7c9 b.n 800d04c <__ssvfiscanf_r+0x1b4> 800d0b8: 220a movs r2, #10 800d0ba: e7d7 b.n 800d06c <__ssvfiscanf_r+0x1d4> 800d0bc: 4629 mov r1, r5 800d0be: 4640 mov r0, r8 800d0c0: f000 f9bc bl 800d43c <__sccl> 800d0c4: 9b41 ldr r3, [sp, #260] @ 0x104 800d0c6: 4605 mov r5, r0 800d0c8: f043 0340 orr.w r3, r3, #64 @ 0x40 800d0cc: 9341 str r3, [sp, #260] @ 0x104 800d0ce: 2301 movs r3, #1 800d0d0: e7d7 b.n 800d082 <__ssvfiscanf_r+0x1ea> 800d0d2: 9b41 ldr r3, [sp, #260] @ 0x104 800d0d4: f043 0340 orr.w r3, r3, #64 @ 0x40 800d0d8: 9341 str r3, [sp, #260] @ 0x104 800d0da: 2300 movs r3, #0 800d0dc: e7d1 b.n 800d082 <__ssvfiscanf_r+0x1ea> 800d0de: 2302 movs r3, #2 800d0e0: e7cf b.n 800d082 <__ssvfiscanf_r+0x1ea> 800d0e2: 9841 ldr r0, [sp, #260] @ 0x104 800d0e4: 06c3 lsls r3, r0, #27 800d0e6: f53f aefe bmi.w 800cee6 <__ssvfiscanf_r+0x4e> 800d0ea: 9b00 ldr r3, [sp, #0] 800d0ec: 9a45 ldr r2, [sp, #276] @ 0x114 800d0ee: 1d19 adds r1, r3, #4 800d0f0: 9100 str r1, [sp, #0] 800d0f2: 681b ldr r3, [r3, #0] 800d0f4: 07c0 lsls r0, r0, #31 800d0f6: bf4c ite mi 800d0f8: 801a strhmi r2, [r3, #0] 800d0fa: 601a strpl r2, [r3, #0] 800d0fc: e6f3 b.n 800cee6 <__ssvfiscanf_r+0x4e> 800d0fe: 4621 mov r1, r4 800d100: 4630 mov r0, r6 800d102: 9ba1 ldr r3, [sp, #644] @ 0x284 800d104: 4798 blx r3 800d106: 2800 cmp r0, #0 800d108: d0bf beq.n 800d08a <__ssvfiscanf_r+0x1f2> 800d10a: e79f b.n 800d04c <__ssvfiscanf_r+0x1b4> 800d10c: 9a45 ldr r2, [sp, #276] @ 0x114 800d10e: 3201 adds r2, #1 800d110: 9245 str r2, [sp, #276] @ 0x114 800d112: 6862 ldr r2, [r4, #4] 800d114: 3a01 subs r2, #1 800d116: 2a00 cmp r2, #0 800d118: 6062 str r2, [r4, #4] 800d11a: dd02 ble.n 800d122 <__ssvfiscanf_r+0x28a> 800d11c: 3301 adds r3, #1 800d11e: 6023 str r3, [r4, #0] 800d120: e7b6 b.n 800d090 <__ssvfiscanf_r+0x1f8> 800d122: 4621 mov r1, r4 800d124: 4630 mov r0, r6 800d126: 9ba1 ldr r3, [sp, #644] @ 0x284 800d128: 4798 blx r3 800d12a: 2800 cmp r0, #0 800d12c: d0b0 beq.n 800d090 <__ssvfiscanf_r+0x1f8> 800d12e: e78d b.n 800d04c <__ssvfiscanf_r+0x1b4> 800d130: 2b04 cmp r3, #4 800d132: dc06 bgt.n 800d142 <__ssvfiscanf_r+0x2aa> 800d134: 466b mov r3, sp 800d136: 4622 mov r2, r4 800d138: 4630 mov r0, r6 800d13a: a941 add r1, sp, #260 @ 0x104 800d13c: f000 f88c bl 800d258 <_scanf_i> 800d140: e7b4 b.n 800d0ac <__ssvfiscanf_r+0x214> 800d142: 4b09 ldr r3, [pc, #36] @ (800d168 <__ssvfiscanf_r+0x2d0>) 800d144: 2b00 cmp r3, #0 800d146: f43f aece beq.w 800cee6 <__ssvfiscanf_r+0x4e> 800d14a: 466b mov r3, sp 800d14c: 4622 mov r2, r4 800d14e: 4630 mov r0, r6 800d150: a941 add r1, sp, #260 @ 0x104 800d152: f3af 8000 nop.w 800d156: e7a9 b.n 800d0ac <__ssvfiscanf_r+0x214> 800d158: 0800cde5 .word 0x0800cde5 800d15c: 0800ce5f .word 0x0800ce5f 800d160: 0800e3a1 .word 0x0800e3a1 800d164: 0800e1b4 .word 0x0800e1b4 800d168: 00000000 .word 0x00000000 800d16c: 89a3 ldrh r3, [r4, #12] 800d16e: 065b lsls r3, r3, #25 800d170: f53f af70 bmi.w 800d054 <__ssvfiscanf_r+0x1bc> 800d174: f50d 7d23 add.w sp, sp, #652 @ 0x28c 800d178: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800d17c: 9844 ldr r0, [sp, #272] @ 0x110 800d17e: e7f9 b.n 800d174 <__ssvfiscanf_r+0x2dc> 0800d180 <__ascii_mbtowc>: 800d180: b082 sub sp, #8 800d182: b901 cbnz r1, 800d186 <__ascii_mbtowc+0x6> 800d184: a901 add r1, sp, #4 800d186: b142 cbz r2, 800d19a <__ascii_mbtowc+0x1a> 800d188: b14b cbz r3, 800d19e <__ascii_mbtowc+0x1e> 800d18a: 7813 ldrb r3, [r2, #0] 800d18c: 600b str r3, [r1, #0] 800d18e: 7812 ldrb r2, [r2, #0] 800d190: 1e10 subs r0, r2, #0 800d192: bf18 it ne 800d194: 2001 movne r0, #1 800d196: b002 add sp, #8 800d198: 4770 bx lr 800d19a: 4610 mov r0, r2 800d19c: e7fb b.n 800d196 <__ascii_mbtowc+0x16> 800d19e: f06f 0001 mvn.w r0, #1 800d1a2: e7f8 b.n 800d196 <__ascii_mbtowc+0x16> 0800d1a4 <_scanf_chars>: 800d1a4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 800d1a8: 4615 mov r5, r2 800d1aa: 688a ldr r2, [r1, #8] 800d1ac: 4680 mov r8, r0 800d1ae: 460c mov r4, r1 800d1b0: b932 cbnz r2, 800d1c0 <_scanf_chars+0x1c> 800d1b2: 698a ldr r2, [r1, #24] 800d1b4: 2a00 cmp r2, #0 800d1b6: bf14 ite ne 800d1b8: f04f 32ff movne.w r2, #4294967295 @ 0xffffffff 800d1bc: 2201 moveq r2, #1 800d1be: 608a str r2, [r1, #8] 800d1c0: 2700 movs r7, #0 800d1c2: 6822 ldr r2, [r4, #0] 800d1c4: f8df 908c ldr.w r9, [pc, #140] @ 800d254 <_scanf_chars+0xb0> 800d1c8: 06d1 lsls r1, r2, #27 800d1ca: bf5f itttt pl 800d1cc: 681a ldrpl r2, [r3, #0] 800d1ce: 1d11 addpl r1, r2, #4 800d1d0: 6019 strpl r1, [r3, #0] 800d1d2: 6816 ldrpl r6, [r2, #0] 800d1d4: 69a0 ldr r0, [r4, #24] 800d1d6: b188 cbz r0, 800d1fc <_scanf_chars+0x58> 800d1d8: 2801 cmp r0, #1 800d1da: d107 bne.n 800d1ec <_scanf_chars+0x48> 800d1dc: 682b ldr r3, [r5, #0] 800d1de: 781a ldrb r2, [r3, #0] 800d1e0: 6963 ldr r3, [r4, #20] 800d1e2: 5c9b ldrb r3, [r3, r2] 800d1e4: b953 cbnz r3, 800d1fc <_scanf_chars+0x58> 800d1e6: 2f00 cmp r7, #0 800d1e8: d031 beq.n 800d24e <_scanf_chars+0xaa> 800d1ea: e022 b.n 800d232 <_scanf_chars+0x8e> 800d1ec: 2802 cmp r0, #2 800d1ee: d120 bne.n 800d232 <_scanf_chars+0x8e> 800d1f0: 682b ldr r3, [r5, #0] 800d1f2: 781b ldrb r3, [r3, #0] 800d1f4: f819 3003 ldrb.w r3, [r9, r3] 800d1f8: 071b lsls r3, r3, #28 800d1fa: d41a bmi.n 800d232 <_scanf_chars+0x8e> 800d1fc: 6823 ldr r3, [r4, #0] 800d1fe: 3701 adds r7, #1 800d200: 06da lsls r2, r3, #27 800d202: bf5e ittt pl 800d204: 682b ldrpl r3, [r5, #0] 800d206: 781b ldrbpl r3, [r3, #0] 800d208: f806 3b01 strbpl.w r3, [r6], #1 800d20c: 682a ldr r2, [r5, #0] 800d20e: 686b ldr r3, [r5, #4] 800d210: 3201 adds r2, #1 800d212: 602a str r2, [r5, #0] 800d214: 68a2 ldr r2, [r4, #8] 800d216: 3b01 subs r3, #1 800d218: 3a01 subs r2, #1 800d21a: 606b str r3, [r5, #4] 800d21c: 60a2 str r2, [r4, #8] 800d21e: b142 cbz r2, 800d232 <_scanf_chars+0x8e> 800d220: 2b00 cmp r3, #0 800d222: dcd7 bgt.n 800d1d4 <_scanf_chars+0x30> 800d224: 4629 mov r1, r5 800d226: 4640 mov r0, r8 800d228: f8d4 3180 ldr.w r3, [r4, #384] @ 0x180 800d22c: 4798 blx r3 800d22e: 2800 cmp r0, #0 800d230: d0d0 beq.n 800d1d4 <_scanf_chars+0x30> 800d232: 6823 ldr r3, [r4, #0] 800d234: f013 0310 ands.w r3, r3, #16 800d238: d105 bne.n 800d246 <_scanf_chars+0xa2> 800d23a: 68e2 ldr r2, [r4, #12] 800d23c: 3201 adds r2, #1 800d23e: 60e2 str r2, [r4, #12] 800d240: 69a2 ldr r2, [r4, #24] 800d242: b102 cbz r2, 800d246 <_scanf_chars+0xa2> 800d244: 7033 strb r3, [r6, #0] 800d246: 2000 movs r0, #0 800d248: 6923 ldr r3, [r4, #16] 800d24a: 443b add r3, r7 800d24c: 6123 str r3, [r4, #16] 800d24e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 800d252: bf00 nop 800d254: 0800e3a1 .word 0x0800e3a1 0800d258 <_scanf_i>: 800d258: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800d25c: 460c mov r4, r1 800d25e: 4698 mov r8, r3 800d260: 4b72 ldr r3, [pc, #456] @ (800d42c <_scanf_i+0x1d4>) 800d262: b087 sub sp, #28 800d264: 4682 mov sl, r0 800d266: 4616 mov r6, r2 800d268: e893 0007 ldmia.w r3, {r0, r1, r2} 800d26c: ab03 add r3, sp, #12 800d26e: e883 0007 stmia.w r3, {r0, r1, r2} 800d272: 4b6f ldr r3, [pc, #444] @ (800d430 <_scanf_i+0x1d8>) 800d274: 69a1 ldr r1, [r4, #24] 800d276: 4a6f ldr r2, [pc, #444] @ (800d434 <_scanf_i+0x1dc>) 800d278: 4627 mov r7, r4 800d27a: 2903 cmp r1, #3 800d27c: bf08 it eq 800d27e: 461a moveq r2, r3 800d280: 68a3 ldr r3, [r4, #8] 800d282: 9201 str r2, [sp, #4] 800d284: 1e5a subs r2, r3, #1 800d286: f5b2 7fae cmp.w r2, #348 @ 0x15c 800d28a: bf81 itttt hi 800d28c: f46f 75ae mvnhi.w r5, #348 @ 0x15c 800d290: eb03 0905 addhi.w r9, r3, r5 800d294: f240 135d movwhi r3, #349 @ 0x15d 800d298: 60a3 strhi r3, [r4, #8] 800d29a: f857 3b1c ldr.w r3, [r7], #28 800d29e: bf98 it ls 800d2a0: f04f 0900 movls.w r9, #0 800d2a4: 463d mov r5, r7 800d2a6: f04f 0b00 mov.w fp, #0 800d2aa: f443 6350 orr.w r3, r3, #3328 @ 0xd00 800d2ae: 6023 str r3, [r4, #0] 800d2b0: 6831 ldr r1, [r6, #0] 800d2b2: ab03 add r3, sp, #12 800d2b4: 2202 movs r2, #2 800d2b6: 7809 ldrb r1, [r1, #0] 800d2b8: f853 002b ldr.w r0, [r3, fp, lsl #2] 800d2bc: f7fd fc18 bl 800aaf0 800d2c0: b328 cbz r0, 800d30e <_scanf_i+0xb6> 800d2c2: f1bb 0f01 cmp.w fp, #1 800d2c6: d159 bne.n 800d37c <_scanf_i+0x124> 800d2c8: 6862 ldr r2, [r4, #4] 800d2ca: b92a cbnz r2, 800d2d8 <_scanf_i+0x80> 800d2cc: 2108 movs r1, #8 800d2ce: 6822 ldr r2, [r4, #0] 800d2d0: 6061 str r1, [r4, #4] 800d2d2: f442 7200 orr.w r2, r2, #512 @ 0x200 800d2d6: 6022 str r2, [r4, #0] 800d2d8: 6822 ldr r2, [r4, #0] 800d2da: f422 62a0 bic.w r2, r2, #1280 @ 0x500 800d2de: 6022 str r2, [r4, #0] 800d2e0: 68a2 ldr r2, [r4, #8] 800d2e2: 1e51 subs r1, r2, #1 800d2e4: 60a1 str r1, [r4, #8] 800d2e6: b192 cbz r2, 800d30e <_scanf_i+0xb6> 800d2e8: 6832 ldr r2, [r6, #0] 800d2ea: 1c51 adds r1, r2, #1 800d2ec: 6031 str r1, [r6, #0] 800d2ee: 7812 ldrb r2, [r2, #0] 800d2f0: f805 2b01 strb.w r2, [r5], #1 800d2f4: 6872 ldr r2, [r6, #4] 800d2f6: 3a01 subs r2, #1 800d2f8: 2a00 cmp r2, #0 800d2fa: 6072 str r2, [r6, #4] 800d2fc: dc07 bgt.n 800d30e <_scanf_i+0xb6> 800d2fe: 4631 mov r1, r6 800d300: 4650 mov r0, sl 800d302: f8d4 2180 ldr.w r2, [r4, #384] @ 0x180 800d306: 4790 blx r2 800d308: 2800 cmp r0, #0 800d30a: f040 8085 bne.w 800d418 <_scanf_i+0x1c0> 800d30e: f10b 0b01 add.w fp, fp, #1 800d312: f1bb 0f03 cmp.w fp, #3 800d316: d1cb bne.n 800d2b0 <_scanf_i+0x58> 800d318: 6863 ldr r3, [r4, #4] 800d31a: b90b cbnz r3, 800d320 <_scanf_i+0xc8> 800d31c: 230a movs r3, #10 800d31e: 6063 str r3, [r4, #4] 800d320: 6863 ldr r3, [r4, #4] 800d322: 4945 ldr r1, [pc, #276] @ (800d438 <_scanf_i+0x1e0>) 800d324: 6960 ldr r0, [r4, #20] 800d326: 1ac9 subs r1, r1, r3 800d328: f000 f888 bl 800d43c <__sccl> 800d32c: f04f 0b00 mov.w fp, #0 800d330: 68a3 ldr r3, [r4, #8] 800d332: 6822 ldr r2, [r4, #0] 800d334: 2b00 cmp r3, #0 800d336: d03d beq.n 800d3b4 <_scanf_i+0x15c> 800d338: 6831 ldr r1, [r6, #0] 800d33a: 6960 ldr r0, [r4, #20] 800d33c: f891 c000 ldrb.w ip, [r1] 800d340: f810 000c ldrb.w r0, [r0, ip] 800d344: 2800 cmp r0, #0 800d346: d035 beq.n 800d3b4 <_scanf_i+0x15c> 800d348: f1bc 0f30 cmp.w ip, #48 @ 0x30 800d34c: d124 bne.n 800d398 <_scanf_i+0x140> 800d34e: 0510 lsls r0, r2, #20 800d350: d522 bpl.n 800d398 <_scanf_i+0x140> 800d352: f10b 0b01 add.w fp, fp, #1 800d356: f1b9 0f00 cmp.w r9, #0 800d35a: d003 beq.n 800d364 <_scanf_i+0x10c> 800d35c: 3301 adds r3, #1 800d35e: f109 39ff add.w r9, r9, #4294967295 @ 0xffffffff 800d362: 60a3 str r3, [r4, #8] 800d364: 6873 ldr r3, [r6, #4] 800d366: 3b01 subs r3, #1 800d368: 2b00 cmp r3, #0 800d36a: 6073 str r3, [r6, #4] 800d36c: dd1b ble.n 800d3a6 <_scanf_i+0x14e> 800d36e: 6833 ldr r3, [r6, #0] 800d370: 3301 adds r3, #1 800d372: 6033 str r3, [r6, #0] 800d374: 68a3 ldr r3, [r4, #8] 800d376: 3b01 subs r3, #1 800d378: 60a3 str r3, [r4, #8] 800d37a: e7d9 b.n 800d330 <_scanf_i+0xd8> 800d37c: f1bb 0f02 cmp.w fp, #2 800d380: d1ae bne.n 800d2e0 <_scanf_i+0x88> 800d382: 6822 ldr r2, [r4, #0] 800d384: f402 61c0 and.w r1, r2, #1536 @ 0x600 800d388: f5b1 7f00 cmp.w r1, #512 @ 0x200 800d38c: d1c4 bne.n 800d318 <_scanf_i+0xc0> 800d38e: 2110 movs r1, #16 800d390: f442 7280 orr.w r2, r2, #256 @ 0x100 800d394: 6061 str r1, [r4, #4] 800d396: e7a2 b.n 800d2de <_scanf_i+0x86> 800d398: f422 6210 bic.w r2, r2, #2304 @ 0x900 800d39c: 6022 str r2, [r4, #0] 800d39e: 780b ldrb r3, [r1, #0] 800d3a0: f805 3b01 strb.w r3, [r5], #1 800d3a4: e7de b.n 800d364 <_scanf_i+0x10c> 800d3a6: 4631 mov r1, r6 800d3a8: 4650 mov r0, sl 800d3aa: f8d4 3180 ldr.w r3, [r4, #384] @ 0x180 800d3ae: 4798 blx r3 800d3b0: 2800 cmp r0, #0 800d3b2: d0df beq.n 800d374 <_scanf_i+0x11c> 800d3b4: 6823 ldr r3, [r4, #0] 800d3b6: 05d9 lsls r1, r3, #23 800d3b8: d50d bpl.n 800d3d6 <_scanf_i+0x17e> 800d3ba: 42bd cmp r5, r7 800d3bc: d909 bls.n 800d3d2 <_scanf_i+0x17a> 800d3be: f815 1c01 ldrb.w r1, [r5, #-1] 800d3c2: 4632 mov r2, r6 800d3c4: 4650 mov r0, sl 800d3c6: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c 800d3ca: f105 39ff add.w r9, r5, #4294967295 @ 0xffffffff 800d3ce: 4798 blx r3 800d3d0: 464d mov r5, r9 800d3d2: 42bd cmp r5, r7 800d3d4: d028 beq.n 800d428 <_scanf_i+0x1d0> 800d3d6: 6822 ldr r2, [r4, #0] 800d3d8: f012 0210 ands.w r2, r2, #16 800d3dc: d113 bne.n 800d406 <_scanf_i+0x1ae> 800d3de: 702a strb r2, [r5, #0] 800d3e0: 4639 mov r1, r7 800d3e2: 6863 ldr r3, [r4, #4] 800d3e4: 4650 mov r0, sl 800d3e6: 9e01 ldr r6, [sp, #4] 800d3e8: 47b0 blx r6 800d3ea: f8d8 3000 ldr.w r3, [r8] 800d3ee: 6821 ldr r1, [r4, #0] 800d3f0: 1d1a adds r2, r3, #4 800d3f2: f8c8 2000 str.w r2, [r8] 800d3f6: f011 0f20 tst.w r1, #32 800d3fa: 681b ldr r3, [r3, #0] 800d3fc: d00f beq.n 800d41e <_scanf_i+0x1c6> 800d3fe: 6018 str r0, [r3, #0] 800d400: 68e3 ldr r3, [r4, #12] 800d402: 3301 adds r3, #1 800d404: 60e3 str r3, [r4, #12] 800d406: 2000 movs r0, #0 800d408: 6923 ldr r3, [r4, #16] 800d40a: 1bed subs r5, r5, r7 800d40c: 445d add r5, fp 800d40e: 442b add r3, r5 800d410: 6123 str r3, [r4, #16] 800d412: b007 add sp, #28 800d414: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800d418: f04f 0b00 mov.w fp, #0 800d41c: e7ca b.n 800d3b4 <_scanf_i+0x15c> 800d41e: 07ca lsls r2, r1, #31 800d420: bf4c ite mi 800d422: 8018 strhmi r0, [r3, #0] 800d424: 6018 strpl r0, [r3, #0] 800d426: e7eb b.n 800d400 <_scanf_i+0x1a8> 800d428: 2001 movs r0, #1 800d42a: e7f2 b.n 800d412 <_scanf_i+0x1ba> 800d42c: 0800df90 .word 0x0800df90 800d430: 0800d625 .word 0x0800d625 800d434: 0800ca51 .word 0x0800ca51 800d438: 0800e232 .word 0x0800e232 0800d43c <__sccl>: 800d43c: b570 push {r4, r5, r6, lr} 800d43e: 780b ldrb r3, [r1, #0] 800d440: 4604 mov r4, r0 800d442: 2b5e cmp r3, #94 @ 0x5e 800d444: bf0b itete eq 800d446: 784b ldrbeq r3, [r1, #1] 800d448: 1c4a addne r2, r1, #1 800d44a: 1c8a addeq r2, r1, #2 800d44c: 2100 movne r1, #0 800d44e: bf08 it eq 800d450: 2101 moveq r1, #1 800d452: 3801 subs r0, #1 800d454: f104 05ff add.w r5, r4, #255 @ 0xff 800d458: f800 1f01 strb.w r1, [r0, #1]! 800d45c: 42a8 cmp r0, r5 800d45e: d1fb bne.n 800d458 <__sccl+0x1c> 800d460: b90b cbnz r3, 800d466 <__sccl+0x2a> 800d462: 1e50 subs r0, r2, #1 800d464: bd70 pop {r4, r5, r6, pc} 800d466: f081 0101 eor.w r1, r1, #1 800d46a: 4610 mov r0, r2 800d46c: 54e1 strb r1, [r4, r3] 800d46e: 4602 mov r2, r0 800d470: f812 5b01 ldrb.w r5, [r2], #1 800d474: 2d2d cmp r5, #45 @ 0x2d 800d476: d005 beq.n 800d484 <__sccl+0x48> 800d478: 2d5d cmp r5, #93 @ 0x5d 800d47a: d016 beq.n 800d4aa <__sccl+0x6e> 800d47c: 2d00 cmp r5, #0 800d47e: d0f1 beq.n 800d464 <__sccl+0x28> 800d480: 462b mov r3, r5 800d482: e7f2 b.n 800d46a <__sccl+0x2e> 800d484: 7846 ldrb r6, [r0, #1] 800d486: 2e5d cmp r6, #93 @ 0x5d 800d488: d0fa beq.n 800d480 <__sccl+0x44> 800d48a: 42b3 cmp r3, r6 800d48c: dcf8 bgt.n 800d480 <__sccl+0x44> 800d48e: 461a mov r2, r3 800d490: 3002 adds r0, #2 800d492: 3201 adds r2, #1 800d494: 4296 cmp r6, r2 800d496: 54a1 strb r1, [r4, r2] 800d498: dcfb bgt.n 800d492 <__sccl+0x56> 800d49a: 1af2 subs r2, r6, r3 800d49c: 3a01 subs r2, #1 800d49e: 42b3 cmp r3, r6 800d4a0: bfa8 it ge 800d4a2: 2200 movge r2, #0 800d4a4: 1c5d adds r5, r3, #1 800d4a6: 18ab adds r3, r5, r2 800d4a8: e7e1 b.n 800d46e <__sccl+0x32> 800d4aa: 4610 mov r0, r2 800d4ac: e7da b.n 800d464 <__sccl+0x28> 0800d4ae <_malloc_usable_size_r>: 800d4ae: f851 3c04 ldr.w r3, [r1, #-4] 800d4b2: 1f18 subs r0, r3, #4 800d4b4: 2b00 cmp r3, #0 800d4b6: bfbc itt lt 800d4b8: 580b ldrlt r3, [r1, r0] 800d4ba: 18c0 addlt r0, r0, r3 800d4bc: 4770 bx lr 0800d4be <__submore>: 800d4be: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800d4c2: 460c mov r4, r1 800d4c4: 6b49 ldr r1, [r1, #52] @ 0x34 800d4c6: f104 0344 add.w r3, r4, #68 @ 0x44 800d4ca: 4299 cmp r1, r3 800d4cc: d11b bne.n 800d506 <__submore+0x48> 800d4ce: f44f 6180 mov.w r1, #1024 @ 0x400 800d4d2: f7fe fcb1 bl 800be38 <_malloc_r> 800d4d6: b918 cbnz r0, 800d4e0 <__submore+0x22> 800d4d8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800d4dc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800d4e0: f44f 6380 mov.w r3, #1024 @ 0x400 800d4e4: 63a3 str r3, [r4, #56] @ 0x38 800d4e6: f894 3046 ldrb.w r3, [r4, #70] @ 0x46 800d4ea: 6360 str r0, [r4, #52] @ 0x34 800d4ec: f880 33ff strb.w r3, [r0, #1023] @ 0x3ff 800d4f0: f894 3045 ldrb.w r3, [r4, #69] @ 0x45 800d4f4: f200 30fd addw r0, r0, #1021 @ 0x3fd 800d4f8: 7043 strb r3, [r0, #1] 800d4fa: f894 3044 ldrb.w r3, [r4, #68] @ 0x44 800d4fe: 7003 strb r3, [r0, #0] 800d500: 6020 str r0, [r4, #0] 800d502: 2000 movs r0, #0 800d504: e7ea b.n 800d4dc <__submore+0x1e> 800d506: 6ba6 ldr r6, [r4, #56] @ 0x38 800d508: 0077 lsls r7, r6, #1 800d50a: 463a mov r2, r7 800d50c: f7ff f9c6 bl 800c89c <_realloc_r> 800d510: 4605 mov r5, r0 800d512: 2800 cmp r0, #0 800d514: d0e0 beq.n 800d4d8 <__submore+0x1a> 800d516: eb00 0806 add.w r8, r0, r6 800d51a: 4601 mov r1, r0 800d51c: 4632 mov r2, r6 800d51e: 4640 mov r0, r8 800d520: f7fd faf4 bl 800ab0c 800d524: e9c4 570d strd r5, r7, [r4, #52] @ 0x34 800d528: f8c4 8000 str.w r8, [r4] 800d52c: e7e9 b.n 800d502 <__submore+0x44> ... 0800d530 <_strtol_l.isra.0>: 800d530: 2b24 cmp r3, #36 @ 0x24 800d532: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800d536: 4686 mov lr, r0 800d538: 4690 mov r8, r2 800d53a: d801 bhi.n 800d540 <_strtol_l.isra.0+0x10> 800d53c: 2b01 cmp r3, #1 800d53e: d106 bne.n 800d54e <_strtol_l.isra.0+0x1e> 800d540: f7fc ffb2 bl 800a4a8 <__errno> 800d544: 2316 movs r3, #22 800d546: 6003 str r3, [r0, #0] 800d548: 2000 movs r0, #0 800d54a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800d54e: 460d mov r5, r1 800d550: 4833 ldr r0, [pc, #204] @ (800d620 <_strtol_l.isra.0+0xf0>) 800d552: 462a mov r2, r5 800d554: f815 4b01 ldrb.w r4, [r5], #1 800d558: 5d06 ldrb r6, [r0, r4] 800d55a: f016 0608 ands.w r6, r6, #8 800d55e: d1f8 bne.n 800d552 <_strtol_l.isra.0+0x22> 800d560: 2c2d cmp r4, #45 @ 0x2d 800d562: d110 bne.n 800d586 <_strtol_l.isra.0+0x56> 800d564: 2601 movs r6, #1 800d566: 782c ldrb r4, [r5, #0] 800d568: 1c95 adds r5, r2, #2 800d56a: f033 0210 bics.w r2, r3, #16 800d56e: d115 bne.n 800d59c <_strtol_l.isra.0+0x6c> 800d570: 2c30 cmp r4, #48 @ 0x30 800d572: d10d bne.n 800d590 <_strtol_l.isra.0+0x60> 800d574: 782a ldrb r2, [r5, #0] 800d576: f002 02df and.w r2, r2, #223 @ 0xdf 800d57a: 2a58 cmp r2, #88 @ 0x58 800d57c: d108 bne.n 800d590 <_strtol_l.isra.0+0x60> 800d57e: 786c ldrb r4, [r5, #1] 800d580: 3502 adds r5, #2 800d582: 2310 movs r3, #16 800d584: e00a b.n 800d59c <_strtol_l.isra.0+0x6c> 800d586: 2c2b cmp r4, #43 @ 0x2b 800d588: bf04 itt eq 800d58a: 782c ldrbeq r4, [r5, #0] 800d58c: 1c95 addeq r5, r2, #2 800d58e: e7ec b.n 800d56a <_strtol_l.isra.0+0x3a> 800d590: 2b00 cmp r3, #0 800d592: d1f6 bne.n 800d582 <_strtol_l.isra.0+0x52> 800d594: 2c30 cmp r4, #48 @ 0x30 800d596: bf14 ite ne 800d598: 230a movne r3, #10 800d59a: 2308 moveq r3, #8 800d59c: 2200 movs r2, #0 800d59e: f106 4c00 add.w ip, r6, #2147483648 @ 0x80000000 800d5a2: f10c 3cff add.w ip, ip, #4294967295 @ 0xffffffff 800d5a6: fbbc f9f3 udiv r9, ip, r3 800d5aa: 4610 mov r0, r2 800d5ac: fb03 ca19 mls sl, r3, r9, ip 800d5b0: f1a4 0730 sub.w r7, r4, #48 @ 0x30 800d5b4: 2f09 cmp r7, #9 800d5b6: d80f bhi.n 800d5d8 <_strtol_l.isra.0+0xa8> 800d5b8: 463c mov r4, r7 800d5ba: 42a3 cmp r3, r4 800d5bc: dd1b ble.n 800d5f6 <_strtol_l.isra.0+0xc6> 800d5be: 1c57 adds r7, r2, #1 800d5c0: d007 beq.n 800d5d2 <_strtol_l.isra.0+0xa2> 800d5c2: 4581 cmp r9, r0 800d5c4: d314 bcc.n 800d5f0 <_strtol_l.isra.0+0xc0> 800d5c6: d101 bne.n 800d5cc <_strtol_l.isra.0+0x9c> 800d5c8: 45a2 cmp sl, r4 800d5ca: db11 blt.n 800d5f0 <_strtol_l.isra.0+0xc0> 800d5cc: 2201 movs r2, #1 800d5ce: fb00 4003 mla r0, r0, r3, r4 800d5d2: f815 4b01 ldrb.w r4, [r5], #1 800d5d6: e7eb b.n 800d5b0 <_strtol_l.isra.0+0x80> 800d5d8: f1a4 0741 sub.w r7, r4, #65 @ 0x41 800d5dc: 2f19 cmp r7, #25 800d5de: d801 bhi.n 800d5e4 <_strtol_l.isra.0+0xb4> 800d5e0: 3c37 subs r4, #55 @ 0x37 800d5e2: e7ea b.n 800d5ba <_strtol_l.isra.0+0x8a> 800d5e4: f1a4 0761 sub.w r7, r4, #97 @ 0x61 800d5e8: 2f19 cmp r7, #25 800d5ea: d804 bhi.n 800d5f6 <_strtol_l.isra.0+0xc6> 800d5ec: 3c57 subs r4, #87 @ 0x57 800d5ee: e7e4 b.n 800d5ba <_strtol_l.isra.0+0x8a> 800d5f0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800d5f4: e7ed b.n 800d5d2 <_strtol_l.isra.0+0xa2> 800d5f6: 1c53 adds r3, r2, #1 800d5f8: d108 bne.n 800d60c <_strtol_l.isra.0+0xdc> 800d5fa: 2322 movs r3, #34 @ 0x22 800d5fc: 4660 mov r0, ip 800d5fe: f8ce 3000 str.w r3, [lr] 800d602: f1b8 0f00 cmp.w r8, #0 800d606: d0a0 beq.n 800d54a <_strtol_l.isra.0+0x1a> 800d608: 1e69 subs r1, r5, #1 800d60a: e006 b.n 800d61a <_strtol_l.isra.0+0xea> 800d60c: b106 cbz r6, 800d610 <_strtol_l.isra.0+0xe0> 800d60e: 4240 negs r0, r0 800d610: f1b8 0f00 cmp.w r8, #0 800d614: d099 beq.n 800d54a <_strtol_l.isra.0+0x1a> 800d616: 2a00 cmp r2, #0 800d618: d1f6 bne.n 800d608 <_strtol_l.isra.0+0xd8> 800d61a: f8c8 1000 str.w r1, [r8] 800d61e: e794 b.n 800d54a <_strtol_l.isra.0+0x1a> 800d620: 0800e3a1 .word 0x0800e3a1 0800d624 <_strtol_r>: 800d624: f7ff bf84 b.w 800d530 <_strtol_l.isra.0> 0800d628 <__ascii_wctomb>: 800d628: 4603 mov r3, r0 800d62a: 4608 mov r0, r1 800d62c: b141 cbz r1, 800d640 <__ascii_wctomb+0x18> 800d62e: 2aff cmp r2, #255 @ 0xff 800d630: d904 bls.n 800d63c <__ascii_wctomb+0x14> 800d632: 228a movs r2, #138 @ 0x8a 800d634: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800d638: 601a str r2, [r3, #0] 800d63a: 4770 bx lr 800d63c: 2001 movs r0, #1 800d63e: 700a strb r2, [r1, #0] 800d640: 4770 bx lr 0800d642 <_raise_r>: 800d642: 291f cmp r1, #31 800d644: b538 push {r3, r4, r5, lr} 800d646: 4605 mov r5, r0 800d648: 460c mov r4, r1 800d64a: d904 bls.n 800d656 <_raise_r+0x14> 800d64c: 2316 movs r3, #22 800d64e: 6003 str r3, [r0, #0] 800d650: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800d654: bd38 pop {r3, r4, r5, pc} 800d656: 6bc2 ldr r2, [r0, #60] @ 0x3c 800d658: b112 cbz r2, 800d660 <_raise_r+0x1e> 800d65a: f852 3021 ldr.w r3, [r2, r1, lsl #2] 800d65e: b94b cbnz r3, 800d674 <_raise_r+0x32> 800d660: 4628 mov r0, r5 800d662: f000 f831 bl 800d6c8 <_getpid_r> 800d666: 4622 mov r2, r4 800d668: 4601 mov r1, r0 800d66a: 4628 mov r0, r5 800d66c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 800d670: f000 b818 b.w 800d6a4 <_kill_r> 800d674: 2b01 cmp r3, #1 800d676: d00a beq.n 800d68e <_raise_r+0x4c> 800d678: 1c59 adds r1, r3, #1 800d67a: d103 bne.n 800d684 <_raise_r+0x42> 800d67c: 2316 movs r3, #22 800d67e: 6003 str r3, [r0, #0] 800d680: 2001 movs r0, #1 800d682: e7e7 b.n 800d654 <_raise_r+0x12> 800d684: 2100 movs r1, #0 800d686: 4620 mov r0, r4 800d688: f842 1024 str.w r1, [r2, r4, lsl #2] 800d68c: 4798 blx r3 800d68e: 2000 movs r0, #0 800d690: e7e0 b.n 800d654 <_raise_r+0x12> ... 0800d694 : 800d694: 4b02 ldr r3, [pc, #8] @ (800d6a0 ) 800d696: 4601 mov r1, r0 800d698: 6818 ldr r0, [r3, #0] 800d69a: f7ff bfd2 b.w 800d642 <_raise_r> 800d69e: bf00 nop 800d6a0: 20000038 .word 0x20000038 0800d6a4 <_kill_r>: 800d6a4: b538 push {r3, r4, r5, lr} 800d6a6: 2300 movs r3, #0 800d6a8: 4d06 ldr r5, [pc, #24] @ (800d6c4 <_kill_r+0x20>) 800d6aa: 4604 mov r4, r0 800d6ac: 4608 mov r0, r1 800d6ae: 4611 mov r1, r2 800d6b0: 602b str r3, [r5, #0] 800d6b2: f7f7 ff46 bl 8005542 <_kill> 800d6b6: 1c43 adds r3, r0, #1 800d6b8: d102 bne.n 800d6c0 <_kill_r+0x1c> 800d6ba: 682b ldr r3, [r5, #0] 800d6bc: b103 cbz r3, 800d6c0 <_kill_r+0x1c> 800d6be: 6023 str r3, [r4, #0] 800d6c0: bd38 pop {r3, r4, r5, pc} 800d6c2: bf00 nop 800d6c4: 20003518 .word 0x20003518 0800d6c8 <_getpid_r>: 800d6c8: f7f7 bf34 b.w 8005534 <_getpid> 0800d6cc <_init>: 800d6cc: b5f8 push {r3, r4, r5, r6, r7, lr} 800d6ce: bf00 nop 800d6d0: bcf8 pop {r3, r4, r5, r6, r7} 800d6d2: bc08 pop {r3} 800d6d4: 469e mov lr, r3 800d6d6: 4770 bx lr 0800d6d8 <_fini>: 800d6d8: b5f8 push {r3, r4, r5, r6, r7, lr} 800d6da: bf00 nop 800d6dc: bcf8 pop {r3, r4, r5, r6, r7} 800d6de: bc08 pop {r3} 800d6e0: 469e mov lr, r3 800d6e2: 4770 bx lr